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⌀ | license
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loa-org/loa-hdl
|
modules/adc_ad7266/hdl/adc_ad7266_module.vhd
|
2
|
6288
|
-------------------------------------------------------------------------------
-- Title : Bus Module for ADC AD7266
-- Project : Loa
-------------------------------------------------------------------------------
-- Copyright (c) 2013
-------------------------------------------------------------------------------
-- TODO mask does not work here
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.utils_pkg.all;
use work.bus_pkg.all;
use work.reg_file_pkg.all;
use work.adc_ad7266_pkg.all;
-------------------------------------------------------------------------------
entity adc_ad7266_single_ended_module is
generic (
BASE_ADDRESS : integer range 0 to 16#7FFF#;
CHANNELS : positive := 12); -- AD7266 has 12 single ended channels
port (
adc_out_p : out adc_ad7266_spi_out_type;
adc_in_p : in adc_ad7266_spi_in_type;
bus_o : out busdevice_out_type;
bus_i : in busdevice_in_type;
-- direct access to the read adc samples
adc_values_o : out adc_ad7266_values_type(CHANNELS - 1 downto 0);
clk : in std_logic
);
end adc_ad7266_single_ended_module;
-------------------------------------------------------------------------------
architecture behavioral of adc_ad7266_single_ended_module is
constant REG_ADDR_BIT : positive := required_bits(CHANNELS);
type adc_ad7266_module_state_type is (IDLE, WAIT_FOR_ADC);
type adc_ad7266_module_type is record
state : adc_ad7266_module_state_type;
start : std_logic;
current_ch : integer range 0 to (CHANNELS / 2) - 1;
reg : reg_file_type(2**REG_ADDR_BIT-1 downto 0);
end record;
-----------------------------------------------------------------------------
-- Internal signal declarations
-----------------------------------------------------------------------------
signal r, rin : adc_ad7266_module_type := (state => IDLE,
current_ch => (CHANNELS / 2) - 1,
start => '0',
reg => (others => (others => '0')));
signal adc_mode_s : std_logic;
signal channel_s : std_logic_vector(2 downto 0);
signal value_a_s : std_logic_vector(11 downto 0); --AD7266 converts two
--channels a,b at one
--address (12 channels
--vs 6 addresses)
signal value_b_s : std_logic_vector(11 downto 0);
signal done_s : std_logic;
signal reg_o : reg_file_type(2**REG_ADDR_BIT-1 downto 0);
signal reg_i : reg_file_type(2**REG_ADDR_BIT-1 downto 0);
signal mask_s : std_logic_vector(((CHANNELS / 2) - 1) downto 0);
begin
-- mapping signals to adc i/f
adc_mode_s <= '1'; -- we don't use differential mode
channel_s <= std_logic_vector(to_unsigned(r.current_ch, 3));
reg_i <= r.reg;
-- present last value of each channel on this modules ports
copy_loop : for ii in 0 to 11 generate -- (2**REG_ADDR_BIT-1)
adc_values_o(ii) <= r.reg(ii)(11 downto 0); --12bit ADC (AD7266)
end generate copy_loop;
-- register for channel mask
-- you will always mask out two channels at once
mask_s <= reg_o(0)((CHANNELS / 2) - 1 downto 0);
-------------------------------------------------------------------------------
---- seq part of FSM
-------------------------------------------------------------------------------
seq_proc : process(clk)
begin
if rising_edge(clk) then
r <= rin;
end if;
end process seq_proc;
-----------------------------------------------------------------------------
-- transitions and actions of FSM
-----------------------------------------------------------------------------
comb_proc : process(done_s, mask_s, r, value_a_s, value_b_s)
variable v : adc_ad7266_module_type;
begin
v := r;
case v.state is
when IDLE =>
-- in this state we iterate over the channels
if v.current_ch = ((CHANNELS / 2)-1) then
-- we wrap around (to 0)
v.current_ch := 0;
else
-- or increment the currently selected channel
v.current_ch := v.current_ch + 1;
end if;
-- if the channel isn't masked out, we take a sample
-- if mask_s(v.current_ch) = '0' then
v.start := '1';
v.state := WAIT_FOR_ADC;
-- end if;
when WAIT_FOR_ADC =>
-- adc i/f has already started conversion, we stay in this state until
-- the conversion is over.
v.start := '0';
if done_s = '1' then
-- if the conversion is done we put its result in the right register,
-- for each value a,b
-- and return to the "idle" state.
v.reg(v.current_ch) := ("0000") & value_a_s;
v.reg(v.current_ch + (CHANNELS / 2)) := ("0000") & value_b_s;
v.state := IDLE;
end if;
end case;
rin <= v;
end process comb_proc;
-----------------------------------------------------------------------------
-- Component instantiations
-----------------------------------------------------------------------------
-- Register file to present ADC values to bus
-- and configuration
reg_file_1 : reg_file
generic map (
BASE_ADDRESS => BASE_ADDRESS,
REG_ADDR_BIT => REG_ADDR_BIT)
port map (
bus_o => bus_o,
bus_i => bus_i,
reg_o => reg_o,
reg_i => reg_i,
clk => clk);
-- ADC interface module
adc_ad7266_1 : adc_ad7266_single_ended
generic map (
DELAY => 1)
port map (
adc_out => adc_out_p,
adc_in => adc_in_p,
start_p => r.start,
adc_mode_p => adc_mode_s,
channel_p => channel_s,
value_a_p => value_a_s,
value_b_p => value_b_s,
done_p => done_s,
clk => clk);
end behavioral;
|
bsd-3-clause
|
loa-org/loa-hdl
|
modules/ir_rx/hdl/ir_rx_adcs.vhd
|
2
|
2054
|
-------------------------------------------------------------------------------
-- Title : Two ADCs
-- Project :
-------------------------------------------------------------------------------
-- File : ir_rx_adcs.vhd
-- Author : strongly-typed
-- Created : 2012-04-27
-- Platform :
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2012 strongly-typed
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.adc_ltc2351_pkg.all;
use work.ir_rx_module_pkg.all;
entity ir_rx_adcs is
generic (
CHANNELS : positive := 12);
port (
clk_sample_en_i_p : in std_logic;
-- Ports to two ADCs
-- signals to and from real hardware
adc_o_p : out ir_rx_module_spi_out_type;
adc_i_p : in ir_rx_module_spi_in_type;
adc_values_o_p : out adc_ltc2351_values_type;
adc_done_o_p : out std_logic;
clk : in std_logic);
end ir_rx_adcs;
architecture structural of ir_rx_adcs is
signal adc_values_s : adc_ltc2351_values_type(CHANNELS-1 downto 0) := (others => (others => '0'));
signal adc_done_s : std_logic;
begin -- structural
adc_values_o_p <= adc_values_s;
adc_done_o_p <= adc_done_s;
-- Two ADCs
adc_ltc2351_0 : adc_ltc2351
port map (
adc_out => adc_o_p(0),
adc_in => adc_i_p(0),
start_p => clk_sample_en_i_p,
values_p => adc_values_s(5 downto 0),
done_p => adc_done_s,
clk => clk
);
adc_ltc2351_1 : adc_ltc2351
port map (
adc_out => adc_o_p(1),
adc_in => adc_i_p(1),
start_p => clk_sample_en_i_p,
values_p => adc_values_s(11 downto 6),
done_p => open,
clk => clk
);
end structural;
|
bsd-3-clause
|
loa-org/loa-hdl
|
modules/uart/tb/uart_rx_tb.vhd
|
1
|
2829
|
-------------------------------------------------------------------------------
-- Title : Testbench for design "uart_rx"
-------------------------------------------------------------------------------
-- Author : Fabian Greif
-- Standard : VHDL'x
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2013
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.uart_pkg.all;
use work.uart_tb_pkg.all;
-------------------------------------------------------------------------------
entity uart_rx_tb is
end entity uart_rx_tb;
-------------------------------------------------------------------------------
architecture behavourial of uart_rx_tb is
-- component ports
signal rxd : std_logic := '1';
signal disable : std_logic := '0';
signal data : std_logic_vector(7 downto 0);
signal we : std_logic;
signal rx_error : std_logic;
signal full : std_logic := '1';
signal clk_rx_en : std_logic := '0';
signal clk : std_logic := '0';
begin
-- component instantiation
dut : entity work.uart_rx
port map (
rxd_p => rxd,
disable_p => disable,
data_p => data,
we_p => we,
error_p => rx_error,
full_p => full,
clk_rx_en => clk_rx_en,
reset => '0',
clk => clk);
-- clock generation
clk <= not clk after 20 ns;
-- Generate a bit clock
bitclock : process
begin
wait until rising_edge(clk);
clk_rx_en <= '1';
wait until rising_edge(clk);
clk_rx_en <= '0';
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
end process bitclock;
-- waveform generation
waveform : process
begin
wait for 100 ns;
wait until rising_edge(clk);
-- glitch
rxd <= '0';
wait until rising_edge(clk);
rxd <= '1';
wait for 100 ns;
-- correct transmission
uart_transmit(rxd, "001111100", 10000000);
--wait for 200 ns;
wait for 800 ns;
-- correct transmission, odd parity in MSB
uart_transmit(rxd, "111111111", 1000000);
uart_transmit(rxd, "111111111", 1000000);
--wait for 200 ns;
---- check slightly off baudrates
uart_transmit(rxd, "001111100", 10500000);
--wait for 200 ns;
uart_transmit(rxd, "001111100", 9700000);
--wait for 200 ns;
-- send a wrong parity bit
uart_transmit(rxd, "101111100", 10000000);
wait for 200 ns;
wait;
end process waveform;
end architecture behavourial;
|
bsd-3-clause
|
loa-org/loa-hdl
|
modules/pwm/hdl/pwm_module.vhd
|
2
|
2239
|
-------------------------------------------------------------------------------
-- PWM Module
--
-- Connects the pwm entity to the internal bus system.
--
-- @author Fabian Greif
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.pwm_pkg.all;
use work.utils_pkg.all;
use work.bus_pkg.all;
-------------------------------------------------------------------------------
entity pwm_module is
generic (
BASE_ADDRESS : integer range 0 to 16#7FFF#;
WIDTH : positive := 12; -- Number of bits for the PWM generation (e.g. 12 => 0..4095)
PRESCALER : positive := 2
);
port (
pwm_p : out std_logic;
bus_o : out busdevice_out_type;
bus_i : in busdevice_in_type;
reset : in std_logic;
clk : in std_logic
);
end pwm_module;
-------------------------------------------------------------------------------
architecture behavioral of pwm_module is
type pwm_module_type is record
pwm : std_logic_vector (WIDTH - 1 downto 0);
end record;
signal r, rin : pwm_module_type;
signal clk_en : std_logic;
begin
seq_proc : process(reset, clk)
begin
if rising_edge(clk) then
if reset = '1' then
r.pwm <= (others => '0');
else
r <= rin;
end if;
end if;
end process seq_proc;
comb_proc : process(r, bus_i)
variable v : pwm_module_type;
begin
v := r;
if bus_i.we = '1' and
bus_i.addr = std_logic_vector(to_unsigned(BASE_ADDRESS, 15)) then
v.pwm := bus_i.data(WIDTH - 1 downto 0);
end if;
rin <= v;
end process comb_proc;
bus_o.data <= (others => '0');
-- Generate clock for the PWM generator
divider : clock_divider
generic map (
DIV => PRESCALER)
port map (
clk_out_p => clk_en,
clk => clk);
-- Generate a PWM
pwm_1 : pwm
generic map (
WIDTH => WIDTH)
port map (
clk_en_p => clk_en,
value_p => r.pwm,
output_p => pwm_p,
reset => reset,
clk => clk);
end behavioral;
|
bsd-3-clause
|
loa-org/loa-hdl
|
modules/uart/tb/uart_rx_disable_tb.vhd
|
2
|
2559
|
-------------------------------------------------------------------------------
-- Title : Testbench for design "uart_rx"
-------------------------------------------------------------------------------
-- Author : Fabian Greif
-- Standard : VHDL'x
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2013
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.uart_pkg.all;
use work.uart_tb_pkg.all;
-------------------------------------------------------------------------------
entity uart_rx_disable_tb is
end entity uart_rx_disable_tb;
-------------------------------------------------------------------------------
architecture behavourial of uart_rx_disable_tb is
-- component ports
signal rxd : std_logic := '1';
signal disable : std_logic := '0';
signal data : std_logic_vector(7 downto 0);
signal we : std_logic;
signal rx_error : std_logic;
signal full : std_logic := '1';
signal clk_rx_en : std_logic := '0';
signal clk : std_logic := '0';
begin
-- component instantiation
dut : entity work.uart_rx
port map (
rxd_p => rxd,
disable_p => disable,
data_p => data,
we_p => we,
error_p => rx_error,
full_p => full,
clk_rx_en => clk_rx_en,
clk => clk);
-- clock generation
clk <= not clk after 10 ns;
-- Generate a bit clock
bitclock : process
begin
clk_rx_en <= '1';
wait until rising_edge(clk);
-- clk_rx_en <= '1';
-- wait until rising_edge(clk);
-- clk_rx_en <= '0';
-- wait for 40 ns;
end process bitclock;
-- waveform generation
waveform : process
begin
wait until rising_edge(clk);
uart_transmit(rxd, "001111100", 10000000);
wait for 200 ns;
uart_transmit(rxd, "001111100", 10000000);
wait for 200 ns;
uart_transmit(rxd, "001111100", 10000000);
wait for 200 ns;
wait;
end process waveform;
gen_disable : process
begin
wait until rising_edge(clk);
wait for 50 ns;
disable <= '1';
wait for 20 ns;
disable <= '0';
wait for 3 us;
disable <= '1';
wait for 200 ns;
disable <= '0';
wait;
end process;
end architecture behavourial;
|
bsd-3-clause
|
loa-org/loa-hdl
|
modules/fifo_sync/hdl/fifo_sync.vhd
|
1
|
3523
|
-------------------------------------------------------------------------------
-- Title : Synchronous FIFO
-------------------------------------------------------------------------------
-- Author : Carl Treudler ([email protected])
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: A very plain FIFO, synchronous interfaces.
-------------------------------------------------------------------------------
-- Copyright (c) 2013, Carl Treudler
-- All Rights Reserved.
--
-- The file is part for the Loa project and is released under the
-- 3-clause BSD license. See the file `LICENSE` for the full license
-- governing this code.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.fifo_sync_pkg.all;
-------------------------------------------------------------------------------
entity fifo_sync is
generic (
DATA_WIDTH : positive;
ADDRESS_WIDTH : positive
);
port (
-- write side
di : in std_logic_vector(data_width -1 downto 0);
wr : in std_logic;
full : out std_logic;
-- read side
do : out std_logic_vector(data_width -1 downto 0);
rd : in std_logic;
empty : out std_logic;
valid : out std_logic; -- strobed once per word read
clk : in std_logic
);
end fifo_sync;
-------------------------------------------------------------------------------
architecture behavioural of fifo_sync is
-----------------------------------------------------------------------------
-- Internal signal declarations
-----------------------------------------------------------------------------
constant ADD_TOP : positive := (2**address_width)-1;
type mem_type is array(0 to ADD_TOP) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal mem : mem_type;
signal head : unsigned (address_width-1 downto 0) := (others => '0');
signal tail : unsigned (address_width-1 downto 0) := (others => '0');
signal full_s : std_logic := '0';
signal empty_s : std_logic := '0';
signal valid_s : std_logic := '0';
signal do_s : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
begin -- architecture behavourial
----------------------------------------------------------------------------
-- Connections between ports and signals
----------------------------------------------------------------------------
-- assign to ports
full <= full_s;
empty <= empty_s;
valid <= valid_s;
do <= do_s;
-- determine flags
full_s <= '1' when tail = head+1 else '0';
empty_s <= '1' when tail = head else '0';
-----------------------------------------------------------------------------
-- one process FSM
-----------------------------------------------------------------------------
process (CLK, di, wr, rd, full_s, empty_s)
begin
if rising_edge(CLK) then
if (wr = '1' and full_s = '0') then
mem(to_integer(head)) <= di;
head <= head + 1;
end if;
if (rd = '1' and empty_s = '0') then
do_s <= std_logic_vector(mem(to_integer(tail)));
valid_s <= '1';
tail <= tail + 1;
else
valid_s <= '0';
end if;
end if;
end process;
end behavioural;
|
bsd-3-clause
|
loa-org/loa-hdl
|
modules/servo/tb/servo_module_tb.vhd
|
2
|
3522
|
-------------------------------------------------------------------------------
-- Title : Testbench for design "encoder_module"
-------------------------------------------------------------------------------
-- Author : Fabian Greif <fabian@kleinvieh>
-- Platform : Spartan 3
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.servo_module_pkg.all;
use work.bus_pkg.all;
-------------------------------------------------------------------------------
entity servo_module_tb is
end servo_module_tb;
-------------------------------------------------------------------------------
architecture tb of servo_module_tb is
-- component generics
constant BASE_ADDRESS : positive := 16#0100#;
constant SERVO_COUNT : positive := 11;
-- component ports
signal servo : std_logic_vector(SERVO_COUNT-1 downto 0);
signal bus_o : busdevice_out_type;
signal bus_i : busdevice_in_type :=
(addr => (others => '0'),
data => (others => '0'),
we => '0',
re => '0');
signal clk : std_logic := '0';
begin
-- component instantiation
DUT : servo_module
generic map (
BASE_ADDRESS => BASE_ADDRESS,
SERVO_COUNT => SERVO_COUNT)
port map (
servo_p => servo,
bus_o => bus_o,
bus_i => bus_i,
clk => clk);
-- clock generation
clk <= not clk after 10 NS;
waveform : process
begin
wait for 20 NS;
for i in 0 to SERVO_COUNT-1 loop
wait until rising_edge(clk);
bus_i.addr <= std_logic_vector(
unsigned'(resize(x"0100", bus_i.addr'length)) + i);
bus_i.data <= x"7fff";
bus_i.we <= '1';
wait until rising_edge(clk);
bus_i.we <= '0';
end loop;
wait for 40 ns;
wait until rising_edge(clk);
bus_i.addr <= std_logic_vector(
unsigned'(resize(x"0102", bus_i.addr'length)));
bus_i.data <= x"ffff";
bus_i.we <= '1';
wait until rising_edge(clk);
bus_i.we <= '0';
wait until rising_edge(clk);
bus_i.addr <= std_logic_vector(
unsigned'(resize(x"0103", bus_i.addr'length)));
bus_i.data <= x"0002";
bus_i.we <= '1';
wait until rising_edge(clk);
bus_i.we <= '0';
wait until rising_edge(clk);
bus_i.addr <= std_logic_vector(
unsigned'(resize(x"0109", bus_i.addr'length)));
bus_i.data <= x"0000";
bus_i.we <= '1';
wait until rising_edge(clk);
bus_i.we <= '0';
wait until rising_edge(clk);
wait for 3000 US;
-- Change servo[1] during the signaling time. This change should become
-- active with the next periode.
wait until rising_edge(clk);
bus_i.addr <= std_logic_vector(
unsigned'(resize(x"0101", bus_i.addr'length)));
bus_i.data <= x"0000";
bus_i.we <= '1';
wait until rising_edge(clk);
bus_i.we <= '0';
wait until rising_edge(clk);
wait until rising_edge(clk);
bus_i.addr <= std_logic_vector(
unsigned'(resize(x"0109", bus_i.addr'length)));
bus_i.data <= x"7fff";
bus_i.we <= '1';
wait until rising_edge(clk);
bus_i.we <= '0';
wait until rising_edge(clk);
end process waveform;
end tb;
|
bsd-3-clause
|
loa-org/loa-hdl
|
modules/utils/hdl/fractional_clock_divider.vhd
|
1
|
1852
|
-------------------------------------------------------------------------------
-- Title : Generic clock divider
-- Project : Loa
-------------------------------------------------------------------------------
-- Author : Fabian Greif <[email protected]>
-- Company : Roboterclub Aachen e.V.
-- Platform : Spartan 3
-------------------------------------------------------------------------------
-- Description:
-- Generates a clock enable signal.
--
-- MUL must be smaller than DIV.
--
-- Example:
-- @code
-- process (clk)
-- begin
-- if rising_edge(clk) then
-- if enable = '1' then
-- ... do something with the period of the divided frequency ...
-- end if;
-- end if;
-- end process;
-- @endcode
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity fractional_clock_divider is
generic (
DIV : positive := 1;
MUL : positive := 1;
WIDTH : positive
);
port (
clk_out_p : out std_logic;
clk : in std_logic
);
end fractional_clock_divider;
-- ----------------------------------------------------------------------------
architecture behavior of fractional_clock_divider is
signal cnt : std_logic_vector(WIDTH-1 downto 0) := (others => '0');
begin
process(clk)
begin
if rising_edge(clk) then
-- report "div: " & integer'image(DIV);
if unsigned(cnt) >= to_unsigned(DIV, WIDTH) then
clk_out_p <= '1';
cnt <= std_logic_vector(unsigned(cnt) - DIV);
else
clk_out_p <= '0';
cnt <= std_logic_vector(unsigned(cnt) + MUL);
end if;
end if;
end process;
end behavior;
|
bsd-3-clause
|
loa-org/loa-hdl
|
modules/peripheral_register/hdl/reg_file_bram.vhd
|
1
|
6465
|
-------------------------------------------------------------------------------
-- Title : A Register File Made of Dual Port Block RAM
-------------------------------------------------------------------------------
-- Platform : Xilinx Spartan 3A
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description: A Larger Register File Using Block RAM.
--
-- A dual port block RAM is interfaced to the internal parallel
-- bus.
--
-- Each SelectRAM in Spartan-3(A/E/AN) has 18432 data bits and can
-- be configured as 1024 address x 16 data bits.
--
-- Port A of Block RAM: connected to the internal parallel bus:
-- 1024 addresses of 16 bits
-- 1024 address = 10 bits (9 downto 0)
--
-- Port B: used by the internal processes of the design.
-- Same configuration
--
-------------------------------------------------------------------------------
-- Copyright (c) 2012 strongly-typed
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.bus_pkg.all;
use work.reg_file_pkg.all;
use work.reset_pkg.all;
use work.xilinx_block_ram_pkg.all;
-------------------------------------------------------------------------------
entity reg_file_bram is
generic (
-- The module uses 10 bits for 1024 addresses and the base address must be aligned.
-- Valid BASE_ADDRESSes are 0x0000, 0x0400, 0x0800, ...
BASE_ADDRESS : integer range 0 to 2**15-1;
RESET_IMPL : reset_type := none);
port (
-- Interface to the internal parallel bus.
bus_o : out busdevice_out_type;
bus_i : in busdevice_in_type;
-- Read and write interface to the block RAM for the application.
bram_data_i : in std_logic_vector(15 downto 0) := (others => '0');
bram_data_o : out std_logic_vector(15 downto 0) := (others => '0');
bram_addr_i : in std_logic_vector(9 downto 0) := (others => '0');
bram_we_p : in std_logic := '0';
-- Dummy reset, all signals are initialised.
reset : in std_logic;
clk : in std_logic);
end reg_file_bram;
-------------------------------------------------------------------------------
architecture str of reg_file_bram is
constant BASE_ADDRESS_VECTOR : std_logic_vector(14 downto 0) :=
std_logic_vector(to_unsigned(BASE_ADDRESS, 15));
-- Port A to bus
constant ADDR_A_WIDTH : positive := 10;
constant DATA_A_WIDTH : positive := 16;
-- Port B to application
constant ADDR_B_WIDTH : positive := 10;
constant DATA_B_WIDTH : positive := 16;
-----------------------------------------------------------------------------
-- Internal signal declarations
-----------------------------------------------------------------------------
signal ram_a_addr : std_logic_vector(ADDR_A_WIDTH-1 downto 0) := (others => '0');
signal ram_a_out : std_logic_vector(DATA_A_WIDTH-1 downto 0) := (others => '0');
signal ram_a_in : std_logic_vector(DATA_A_WIDTH-1 downto 0) := (others => '0');
signal ram_a_we : std_logic := '0';
signal ram_a_en : std_logic := '0';
signal ram_a_ssr : std_logic := '0';
signal ram_b_addr : std_logic_vector(ADDR_B_WIDTH-1 downto 0) := (others => '0');
signal ram_b_out : std_logic_vector(DATA_B_WIDTH-1 downto 0) := (others => '0');
signal ram_b_in : std_logic_vector(DATA_B_WIDTH-1 downto 0) := (others => '0');
signal ram_b_we : std_logic := '0';
signal ram_b_en : std_logic := '0';
signal ram_b_ssr : std_logic := '0';
--
signal addr_match_a : std_logic;
signal bus_o_enable_d : std_logic := '0';
signal bus_o_enable_d2 : std_logic := '0';
begin -- str
----------------------------------------------------------------------------
-- Connections
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- Block RAM as dual port RAM with asymmetrical port widths.
----------------------------------------------------------------------------
dp_1 : xilinx_block_ram_dual_port
generic map (
ADDR_A_WIDTH => ADDR_A_WIDTH,
ADDR_B_WIDTH => ADDR_B_WIDTH,
DATA_A_WIDTH => DATA_A_WIDTH,
DATA_B_WIDTH => DATA_B_WIDTH)
port map (
addr_a => ram_a_addr,
addr_b => ram_b_addr,
din_a => ram_a_in,
din_b => ram_b_in,
dout_a => ram_a_out,
dout_b => ram_b_out,
we_a => ram_a_we,
we_b => ram_b_we,
en_a => ram_a_en,
en_b => ram_b_en,
ssr_a => ram_a_ssr,
ssr_b => ram_b_ssr,
clk_a => clk,
clk_b => clk);
----------------------------------------------------------------------------
-- Port A: parallel bus
----------------------------------------------------------------------------
-- Always present the address from the parallel bus to the block RAM.
-- When the bus address matches the address range of the block RAM
-- route the result of the Block RAM to the parallel bus.
ram_a_addr <= bus_i.addr(ADDR_A_WIDTH-1 downto 0);
ram_a_in <= bus_i.data;
-- ADDR_A_WIDTH = 10
-- 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-- |<---- match ---->|
addr_match_a <= '1' when (bus_i.addr(14 downto ADDR_A_WIDTH) = BASE_ADDRESS_VECTOR(14 downto ADDR_A_WIDTH)) else '0';
-- Always enable RAM
ram_a_en <= '1';
-- The block RAM keeps its output latches when EN is '0'. This behaviour is
-- not compatible with the parallel bus where the bus output must be 0 when
-- the device is not selected.
-- Solution: Use Synchronous Reset of the output latches:
ram_a_ssr <= '0' when (addr_match_a = '1') and (bus_i.re = '1') else '1';
-- Write enable
ram_a_we <= '1' when (addr_match_a = '1') and (bus_i.we = '1') else '0';
bus_o.data <= ram_a_out;
----------------------------------------------------------------------------
-- Port B: internal device
----------------------------------------------------------------------------
-- always enable the RAM
ram_b_en <= '1';
-- write to the RAM
ram_b_we <= bram_we_p;
ram_b_addr <= bram_addr_i;
ram_b_in <= bram_data_i;
bram_data_o <= ram_b_out;
end str;
-------------------------------------------------------------------------------
|
bsd-3-clause
|
loa-org/loa-hdl
|
modules/pwm/hdl/pwm_pkg.vhd
|
2
|
357
|
library ieee;
use ieee.std_logic_1164.all;
package pwm_pkg is
component pwm
generic (
WIDTH : natural);
port (
clk_en_p : in std_logic;
value_p : in std_logic_vector (width - 1 downto 0);
output_p : out std_logic;
reset : in std_logic;
clk : in std_logic);
end component;
end package pwm_pkg;
|
bsd-3-clause
|
loa-org/loa-hdl
|
modules/dds/hdl/dds_module.vhd
|
1
|
6091
|
-------------------------------------------------------------------------------
-- Title : Direct digital synhtesis module - 1 Channel
-------------------------------------------------------------------------------
-- Author : [email protected]
-------------------------------------------------------------------------------
-- Created : 2015-08-24
-------------------------------------------------------------------------------
-- Copyright (c) 2015, Carl Treudler
-- All Rights Reserved.
--
-- The file is part for the Loa project and is released under the
-- 3-clause BSD license. See the file `LICENSE` for the full license
-- governing this code.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.reg_file_pkg.all;
use work.nco_pkg.all;
use work.bus_pkg.all;
use work.reset_pkg.all;
entity dds_module is
generic (
BASE_ADDRESS : integer range 0 to 2**15-1;
RESET_IMPL : reset_type := none);
port (
bus_o : out busdevice_out_type;
bus_i : in busdevice_in_type;
-- NCO 0 output
dout : out std_logic_vector(15 downto 0);
reset : in std_logic;
clk : in std_logic);
end entity dds_module;
architecture structural of dds_module is
signal phase_increment : std_logic_vector(31 downto 0);
signal phase : std_logic_vector(9 downto 0);
signal ctrl_reg : std_logic_vector(15 downto 0);
signal accu_load0 : std_logic_vector(31 downto 0);
signal load0, en0 : std_logic;
signal bus_ram_o, bus_ctrl_reg_o, bus_phase_inc_lsb_register_o, bus_load_lsb_register_o, bus_phase_inc_msb_register_o, bus_load_msb_register_o : busdevice_out_type;
begin -- architecture structural
-----------------------------------------------------------------------------
-- NCO 0 - controls fed by bus mapped registers
-- output goes to waveform_ram below
-----------------------------------------------------------------------------
nco_0 : entity work.nco
generic map (
ACCU_WIDTH => 32,
PHASE_WIDTH => 10,
RESET_IMPL => RESET_IMPL)
port map (
en => en0,
phase_increment => phase_increment,
phase => phase,
load => load0,
accu_load => accu_load0,
reset => reset,
clk => clk);
-----------------------------------------------------------------------------
-- Double ported BRAM
-- waveform has to be loaded from bus-side
-- output is updated every cycle
-----------------------------------------------------------------------------
waveform_ram : entity work.reg_file_bram
generic map (
BASE_ADDRESS => BASE_ADDRESS,
RESET_IMPL => RESET_IMPL)
port map (
bus_o => bus_ram_o,
bus_i => bus_i,
bram_data_i => (others => '0'),
bram_data_o => dout,
bram_addr_i => phase,
bram_we_p => '0',
reset => reset,
clk => clk);
-----------------------------------------------------------------------------
-- Registers:
--
-- Control register
-- Enable
-- Load
--
-- Phase Increment Reg - sets increment
--
-- Accu Preload - sets Phase accumulator directly, has to be enabled by laod
-- bit in control register (and disabled).
-----------------------------------------------------------------------------
control_register : entity work.peripheral_register
generic map (
BASE_ADDRESS => BASE_ADDRESS + 16#400#,
RESET_IMPL => RESET_IMPL)
port map (
dout_p => ctrl_reg,
din_p => ctrl_reg,
bus_o => bus_ctrl_reg_o,
bus_i => bus_i,
reset => reset,
clk => clk);
phase_inc_lsb_register : entity work.peripheral_register
generic map (
BASE_ADDRESS => BASE_ADDRESS + 16#401#,
RESET_IMPL => RESET_IMPL)
port map (
dout_p => phase_increment(15 downto 0),
din_p => phase_increment(15 downto 0),
bus_o => bus_phase_inc_lsb_register_o,
bus_i => bus_i,
reset => reset,
clk => clk);
phase_inc_msb_register : entity work.peripheral_register
generic map (
BASE_ADDRESS => BASE_ADDRESS + 16#402#,
RESET_IMPL => RESET_IMPL)
port map (
dout_p => phase_increment(31 downto 16),
din_p => phase_increment(31 downto 16),
bus_o => bus_phase_inc_msb_register_o,
bus_i => bus_i,
reset => reset,
clk => clk);
load_lsb_register : entity work.peripheral_register
generic map (
BASE_ADDRESS => BASE_ADDRESS + 16#403#,
RESET_IMPL => RESET_IMPL)
port map (
dout_p => accu_load0(15 downto 0),
din_p => accu_load0(15 downto 0),
bus_o => bus_load_lsb_register_o,
bus_i => bus_i,
reset => reset,
clk => clk);
load_msb_register : entity work.peripheral_register
generic map (
BASE_ADDRESS => BASE_ADDRESS + 16#404#,
RESET_IMPL => RESET_IMPL)
port map (
dout_p => accu_load0(31 downto 16),
din_p => accu_load0(31 downto 16),
bus_o => bus_load_msb_register_o,
bus_i => bus_i,
reset => reset,
clk => clk);
-----------------------------------------------------------------------------
-- Control Register Mapping
-- (ctrl_reg bits to control signals)
-----------------------------------------------------------------------------
en0 <= ctrl_reg(0);
load0 <= ctrl_reg(1);
-----------------------------------------------------------------------------
-- combine bus_o signals of all components
-----------------------------------------------------------------------------
bus_o.data <= bus_load_lsb_register_o.data or
bus_load_msb_register_o.data or
bus_phase_inc_lsb_register_o.data or
bus_phase_inc_msb_register_o.data or
bus_ctrl_reg_o.data or
bus_ram_o.data;
end architecture structural;
|
bsd-3-clause
|
loa-org/loa-hdl
|
modules/ir_canon/tb/ir_canon_tb.vhd
|
1
|
2249
|
-------------------------------------------------------------------------------
-- Title : Testbench for design "ir_canon"
-- Project :
-------------------------------------------------------------------------------
-- File : ir_canon_tb.vhd
-- Author : user <calle@alukiste>
-- Company :
-- Created : 2014-12-16
-- Last update: 2014-12-16
-- Platform :
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2014
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-12-16 1.0 calle Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.ir_canon_pkg.all;
-------------------------------------------------------------------------------
entity ir_canon_tb is
end ir_canon_tb;
-------------------------------------------------------------------------------
architecture tb of ir_canon_tb is
component ir_canon
port (
ir_canon_in : in ir_canon_in_type;
ir_canon_out : out ir_canon_out_type;
clk : in std_logic);
end component;
-- component ports
signal ir_canon_in : ir_canon_in_type;
signal ir_canon_out : ir_canon_out_type;
-- clock
signal Clk : std_logic := '1';
begin -- tb
-- component instantiation
DUT : ir_canon
port map (
ir_canon_in => ir_canon_in,
ir_canon_out => ir_canon_out,
clk => clk);
-- clock generation
Clk <= not Clk after 10 ns;
-- waveform generation
WaveGen_Proc : process
begin
-- insert signal assignments here
ir_canon_in.trigger <= '0';
wait until Clk = '1';
wait until Clk = '1';
ir_canon_in.trigger <= '1';
wait until Clk = '1';
ir_canon_in.trigger <= '0';
wait for 15 ms;
end process WaveGen_Proc;
end tb;
-------------------------------------------------------------------------------
configuration ir_canon_tb_tb_cfg of ir_canon_tb is
for tb
end for;
end ir_canon_tb_tb_cfg;
|
bsd-3-clause
|
Sourangsu/RAM-Arbiter-VHDL-Code
|
RAM_TEST.vhd
|
1
|
2705
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY ram_test IS
END ram_test;
ARCHITECTURE behavior OF ram_test IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT RAM_NEW
PORT(
CLOCK : IN std_logic;
RST_N : IN std_logic;
RD_EN : IN std_logic;
WR_EN : IN std_logic;
RD_ADDR : IN std_logic_vector(3 downto 0);
WR_ADDR : IN std_logic_vector(3 downto 0);
WR_DATA : IN std_logic_vector(7 downto 0);
RD_DATA : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
signal CLOCK : std_logic := '0';
signal RST_N : std_logic := '0';
signal RD_EN : std_logic := '0';
signal WR_EN : std_logic := '0';
signal RD_ADDR : std_logic_vector(3 downto 0) := (others => '0');
signal WR_ADDR : std_logic_vector(3 downto 0) := (others => '0');
signal WR_DATA : std_logic_vector(7 downto 0) := (others => '0');
--Outputs
signal RD_DATA : std_logic_vector(7 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: RAM PORT MAP (
CLOCK => CLOCK,
RST_N => RST_N,
RD_EN => RD_EN,
WR_EN => WR_EN,
RD_ADDR => RD_ADDR,
WR_ADDR => WR_ADDR,
WR_DATA => WR_DATA,
RD_DATA => RD_DATA
);
CLOCK_process :process
begin
CLOCK <= '0';
wait for 50 ns;
CLOCK <= '1';
wait for 50 ns;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100ms.
wait for 100 ns;
RST_N<='1';
wait for 100 ns;
-------------------------------------------------------------------------------------------------------------------
-- Test Case 1: RAM Write Operation
-------------------------------------------------------------------------------------------------------------------
WR_EN<='1';
RD_EN<='0';
WR_ADDR<="1101";
WR_DATA<="11100111";
-------------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------------
--Test Case 2: RAM Read Operation
wr_en<='0';
rd_en<='1';
RD_ADDR<= "1101";
-------------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------------
-- Test Case 3: RAM Read & Write Operation
-------------------------------------------------------------------------------------------------------------------
WR_EN<='1';
RD_EN<='1';
RD_ADDR<= "1101";
WR_ADDR<="1011";
WR_DATA<="10111001";
wait for 1700 ns;
RD_ADDR<= "1011";
WR_ADDR <="1000";
WR_DATA <="10011111";
-------------------------------------------------------------------------------------------------------------------
wait;
end process;
END;
|
bsd-3-clause
|
mkreider/cocotb2
|
tests/designs/viterbi_decoder_axi4s/packages/pkg_param_derived.vhd
|
7
|
2420
|
--!
--! Copyright (C) 2011 - 2014 Creonic GmbH
--!
--! This file is part of the Creonic Viterbi Decoder, which is distributed
--! under the terms of the GNU General Public License version 2.
--!
--! @file
--! @brief Derived parameters
--! @author Markus Fehrenz
--! @date 2011/07/04
--!
--! @details This constants are derived from constants defined in pkg_param.
--! In order to prevent errors, there is no user choice for these parameters.
--!
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library dec_viterbi;
use dec_viterbi.pkg_param.all;
use dec_viterbi.pkg_helper.all;
package pkg_param_derived is
-- Calculation of constraint length.
function calc_constraint_length return natural;
-- Memory depth of the encoder shift register.
constant ENCODER_MEMORY_DEPTH : natural;
-- Number of trellis states corresponds to the nubmer of ACS units.
constant NUMBER_TRELLIS_STATES : natural;
-- Number of branch units for a single polynomial set
constant NUMBER_BRANCH_UNITS : natural;
-- Bitwidth constants are needed for type conversions
constant BW_TRELLIS_STATES : natural;
constant BW_MAX_WINDOW_LENGTH : natural;
constant BW_BRANCH_RESULT : natural;
constant BW_MAX_PROBABILITY : natural;
end package pkg_param_derived;
package body pkg_param_derived is
function calc_constraint_length return natural is
variable v_maximum : natural := 0;
begin
-- Find the position of the leftmost bit in the polynomials.
for i in NUMBER_PARITY_BITS - 1 downto 0 loop
v_maximum := max(v_maximum, no_bits_natural(PARITY_POLYNOMIALS(i)));
end loop;
v_maximum := max(v_maximum, no_bits_natural(FEEDBACK_POLYNOMIAL));
return v_maximum;
end function calc_constraint_length;
constant ENCODER_MEMORY_DEPTH : natural := calc_constraint_length - 1;
constant NUMBER_TRELLIS_STATES : natural := 2 ** ENCODER_MEMORY_DEPTH;
constant NUMBER_BRANCH_UNITS : natural := 2 ** NUMBER_PARITY_BITS;
constant BW_TRELLIS_STATES : natural := no_bits_natural(NUMBER_TRELLIS_STATES - 1);
constant BW_MAX_WINDOW_LENGTH : natural := no_bits_natural(MAX_WINDOW_LENGTH - 1);
constant BW_BRANCH_RESULT : natural := no_bits_natural((2 ** (BW_LLR_INPUT - 1)) * NUMBER_PARITY_BITS) + 1;
constant BW_MAX_PROBABILITY : natural := no_bits_natural(((2 ** (BW_LLR_INPUT - 1)) * NUMBER_PARITY_BITS) * 4 * ENCODER_MEMORY_DEPTH);
end package body pkg_param_derived;
|
bsd-3-clause
|
INTI-CMNB-FPGA/fpga_lib
|
vhdl/mems/testbench/fifo_tb.vhdl
|
1
|
16634
|
--
-- FIFO testbench
--
-- Author(s):
-- * Rodrigo A. Melo
--
-- Copyright (c) 2017 Authors and INTI
-- Distributed under the BSD 3-Clause License
--
library IEEE;
use IEEE.std_logic_1164.all;
library FPGALIB;
use FPGALIB.MEMs.all;
use FPGALIB.Simul.all;
entity FIFO_tb is
end entity FIFO_tb;
architecture TestBench of FIFO_tb is
constant DWIDTH : positive:=8;
constant DEPTH : positive:=5;
signal stop : boolean;
signal wclk, rclk : std_logic;
signal wrst, rrst : std_logic;
signal wen, ren : std_logic;
signal datai, datao : std_logic_vector(DWIDTH-1 downto 0);
signal full, empty : std_logic;
signal afull, aempty : std_logic;
signal over, under : std_logic;
signal valid : std_logic;
procedure wr_check(
full: in std_logic; vfull: in std_logic;
afull: in std_logic; vafull: in std_logic;
over: in std_logic; vover: in std_logic
) is
begin
assert full=vfull report "Wrong Full Flag" severity failure;
assert afull=vafull report "Wrong Almost Full Flag" severity failure;
assert over=vover report "Wrong Overflow Flag" severity failure;
end procedure wr_check;
procedure rd_check(
empty: in std_logic; vempty: in std_logic;
aempty: in std_logic; vaempty: in std_logic;
under: in std_logic; vunder: in std_logic
) is
begin
assert empty=vempty report "Wrong Empty Flag" severity failure;
assert aempty=vaempty report "Wrong Almost Empty Flag" severity failure;
assert under=vunder report "Wrong Underflow Flag" severity failure;
end procedure rd_check;
procedure ctrl(
signal clk: in std_logic;
signal wen: out std_logic;
wen_val: in std_logic;
signal ren: out std_logic;
ren_val: in std_logic;
signal data: out std_logic_vector;
data_val: in std_logic_vector;
wr_num: inout natural;
rd_num: inout natural
) is
begin
if wen_val='1' and ren_val='1' then
print("Write "&to_str(wr_num)&" - Read "&to_str(rd_num));
wr_num := wr_num + 1;
rd_num := rd_num + 1;
elsif wen_val='1' then
print("Write "&to_str(wr_num));
wr_num := wr_num + 1;
elsif ren_val='1' then
print("Read "&to_str(rd_num));
rd_num := rd_num + 1;
else
print("Nop");
end if;
wen <= wen_val;
ren <= ren_val;
data <= data_val;
wait until rising_edge(clk);
end procedure ctrl;
begin
wr_clock_i : Clock
generic map(FREQUENCY => 2)
port map(clk_o => wclk, rst_o => wrst, stop_i => stop);
rd_clock_i : Clock
generic map(FREQUENCY => 3)
port map(clk_o => rclk, rst_o => rrst, stop_i => stop);
fifo_sync_i: fifo
generic map (
DWIDTH => DWIDTH,
DEPTH => DEPTH,
OUTREG => FALSE,
AFULLOFFSET => 1,
AEMPTYOFFSET => 2,
ASYNC => FALSE
)
port map (
-- write side
wclk_i => wclk,
wrst_i => wrst,
wen_i => wen,
data_i => datai,
full_o => full,
afull_o => afull,
overflow_o => over,
-- read side
rclk_i => wclk,
rrst_i => wrst,
ren_i => ren,
data_o => datao,
empty_o => empty,
aempty_o => aempty,
underflow_o => under,
valid_o => valid
);
fifo_async_i: fifo
generic map (
DWIDTH => DWIDTH,
DEPTH => DEPTH,
OUTREG => FALSE,
AFULLOFFSET => 1,
AEMPTYOFFSET => 2,
ASYNC => TRUE
)
port map (
-- write side
wclk_i => wclk,
wrst_i => wrst,
wen_i => wen,
data_i => datai,
full_o => open,--full,
afull_o => open,--afull,
overflow_o => open,--over,
-- read side
rclk_i => rclk,
rrst_i => rrst,
ren_i => ren,
data_o => open,--datao,
empty_o => open,--empty,
aempty_o => open,--aempty,
underflow_o => open,--under,
valid_o => open --valid
);
test_p : process
variable wr_num, rd_num: natural:=1;
begin
ctrl(wclk, wen, '0', ren, '0', datai, x"00", wr_num, rd_num);
print("* Start of Test (DEPTH="&to_str(DEPTH)&")");
wait until rising_edge(wclk) and wrst = '0';
wr_check(full, '0', afull, '0', over, '0');
print("* Testing Write");
ctrl(wclk, wen, '1', ren, '0', datai, x"11", wr_num, rd_num); wr_check(full, '0', afull, '0', over, '0');
ctrl(wclk, wen, '1', ren, '0', datai, x"22", wr_num, rd_num); wr_check(full, '0', afull, '0', over, '0');
ctrl(wclk, wen, '1', ren, '0', datai, x"33", wr_num, rd_num); wr_check(full, '0', afull, '0', over, '0');
ctrl(wclk, wen, '1', ren, '0', datai, x"44", wr_num, rd_num); wr_check(full, '0', afull, '0', over, '0');
ctrl(wclk, wen, '1', ren, '0', datai, x"55", wr_num, rd_num); wr_check(full, '0', afull, '1', over, '0');
ctrl(wclk, wen, '1', ren, '0', datai, x"66", wr_num, rd_num); wr_check(full, '1', afull, '1', over, '0');
ctrl(wclk, wen, '1', ren, '0', datai, x"77", wr_num, rd_num); wr_check(full, '1', afull, '1', over, '1');
ctrl(wclk, wen, '0', ren, '0', datai, datai, wr_num, rd_num); wr_check(full, '1', afull, '1', over, '0');
print("* Testing Read");
ctrl(wclk, wen, '0', ren, '1', datai, datai, wr_num, rd_num); rd_check(empty, '0', aempty, '0', under, '0');
ctrl(wclk, wen, '0', ren, '1', datai, datai, wr_num, rd_num); rd_check(empty, '0', aempty, '0', under, '0');
ctrl(wclk, wen, '0', ren, '1', datai, datai, wr_num, rd_num); rd_check(empty, '0', aempty, '0', under, '0');
ctrl(wclk, wen, '0', ren, '1', datai, datai, wr_num, rd_num); rd_check(empty, '0', aempty, '1', under, '0');
ctrl(wclk, wen, '0', ren, '1', datai, datai, wr_num, rd_num); rd_check(empty, '0', aempty, '1', under, '0');
ctrl(wclk, wen, '0', ren, '1', datai, datai, wr_num, rd_num); rd_check(empty, '1', aempty, '1', under, '0');
ctrl(wclk, wen, '0', ren, '1', datai, datai, wr_num, rd_num); rd_check(empty, '1', aempty, '1', under, '1');
ctrl(wclk, wen, '0', ren, '0', datai, datai, wr_num, rd_num); rd_check(empty, '1', aempty, '1', under, '0');
print("* Testing Write");
ctrl(wclk, wen, '1', ren, '0', datai, x"88", wr_num, rd_num); wr_check(full, '0', afull, '0', over, '0');
ctrl(wclk, wen, '1', ren, '0', datai, x"99", wr_num, rd_num); wr_check(full, '0', afull, '0', over, '0');
ctrl(wclk, wen, '1', ren, '0', datai, x"AA", wr_num, rd_num); wr_check(full, '0', afull, '0', over, '0');
ctrl(wclk, wen, '1', ren, '0', datai, x"BB", wr_num, rd_num); wr_check(full, '0', afull, '0', over, '0');
ctrl(wclk, wen, '1', ren, '0', datai, x"CC", wr_num, rd_num); wr_check(full, '0', afull, '1', over, '0');
ctrl(wclk, wen, '1', ren, '0', datai, x"DD", wr_num, rd_num); wr_check(full, '1', afull, '1', over, '0');
ctrl(wclk, wen, '1', ren, '0', datai, x"EE", wr_num, rd_num); wr_check(full, '1', afull, '1', over, '1');
ctrl(wclk, wen, '0', ren, '0', datai, datai, wr_num, rd_num); wr_check(full, '1', afull, '1', over, '0');
print("* Testing Read");
ctrl(wclk, wen, '0', ren, '1', datai, datai, wr_num, rd_num); rd_check(empty, '0', aempty, '0', under, '0');
ctrl(wclk, wen, '0', ren, '1', datai, datai, wr_num, rd_num); rd_check(empty, '0', aempty, '0', under, '0');
ctrl(wclk, wen, '0', ren, '1', datai, datai, wr_num, rd_num); rd_check(empty, '0', aempty, '0', under, '0');
ctrl(wclk, wen, '0', ren, '1', datai, datai, wr_num, rd_num); rd_check(empty, '0', aempty, '1', under, '0');
ctrl(wclk, wen, '0', ren, '1', datai, datai, wr_num, rd_num); rd_check(empty, '0', aempty, '1', under, '0');
ctrl(wclk, wen, '0', ren, '1', datai, datai, wr_num, rd_num); rd_check(empty, '1', aempty, '1', under, '0');
ctrl(wclk, wen, '0', ren, '1', datai, datai, wr_num, rd_num); rd_check(empty, '1', aempty, '1', under, '1');
ctrl(wclk, wen, '0', ren, '0', datai, datai, wr_num, rd_num); rd_check(empty, '1', aempty, '1', under, '0');
print("* Testing Write");
ctrl(wclk, wen, '1', ren, '0', datai, x"FF", wr_num, rd_num); wr_check(full, '0', afull, '0', over, '0');
ctrl(wclk, wen, '1', ren, '0', datai, x"00", wr_num, rd_num); wr_check(full, '0', afull, '0', over, '0');
ctrl(wclk, wen, '1', ren, '0', datai, x"11", wr_num, rd_num); wr_check(full, '0', afull, '0', over, '0');
ctrl(wclk, wen, '1', ren, '0', datai, x"22", wr_num, rd_num); wr_check(full, '0', afull, '0', over, '0');
ctrl(wclk, wen, '1', ren, '0', datai, x"33", wr_num, rd_num); wr_check(full, '0', afull, '1', over, '0');
ctrl(wclk, wen, '1', ren, '0', datai, x"44", wr_num, rd_num); wr_check(full, '1', afull, '1', over, '0');
ctrl(wclk, wen, '1', ren, '0', datai, x"55", wr_num, rd_num); wr_check(full, '1', afull, '1', over, '1');
ctrl(wclk, wen, '0', ren, '0', datai, datai, wr_num, rd_num); wr_check(full, '1', afull, '1', over, '0');
print("* Testing Read");
ctrl(wclk, wen, '0', ren, '1', datai, datai, wr_num, rd_num); rd_check(empty, '0', aempty, '0', under, '0');
ctrl(wclk, wen, '0', ren, '1', datai, datai, wr_num, rd_num); rd_check(empty, '0', aempty, '0', under, '0');
ctrl(wclk, wen, '0', ren, '1', datai, datai, wr_num, rd_num); rd_check(empty, '0', aempty, '0', under, '0');
ctrl(wclk, wen, '0', ren, '1', datai, datai, wr_num, rd_num); rd_check(empty, '0', aempty, '1', under, '0');
ctrl(wclk, wen, '0', ren, '1', datai, datai, wr_num, rd_num); rd_check(empty, '0', aempty, '1', under, '0');
ctrl(wclk, wen, '0', ren, '1', datai, datai, wr_num, rd_num); rd_check(empty, '1', aempty, '1', under, '0');
ctrl(wclk, wen, '0', ren, '1', datai, datai, wr_num, rd_num); rd_check(empty, '1', aempty, '1', under, '1');
ctrl(wclk, wen, '0', ren, '0', datai, datai, wr_num, rd_num); rd_check(empty, '1', aempty, '1', under, '0');
print("* Testing Write+Read");
ctrl(wclk, wen, '1', ren, '0', datai, x"66", wr_num, rd_num); rd_check(empty, '1', aempty, '1', under, '0');
ctrl(wclk, wen, '1', ren, '0', datai, x"77", wr_num, rd_num); rd_check(empty, '0', aempty, '1', under, '0');
ctrl(wclk, wen, '1', ren, '1', datai, x"88", wr_num, rd_num); rd_check(empty, '0', aempty, '1', under, '0');
ctrl(wclk, wen, '1', ren, '0', datai, x"99", wr_num, rd_num); rd_check(empty, '0', aempty, '1', under, '0');
ctrl(wclk, wen, '1', ren, '1', datai, x"AA", wr_num, rd_num); rd_check(empty, '0', aempty, '1', under, '0');
ctrl(wclk, wen, '1', ren, '1', datai, x"BB", wr_num, rd_num);
ctrl(wclk, wen, '1', ren, '1', datai, x"CC", wr_num, rd_num);
ctrl(wclk, wen, '1', ren, '0', datai, x"DD", wr_num, rd_num); wr_check(full, '0', afull, '0', over, '0');
ctrl(wclk, wen, '1', ren, '0', datai, x"EE", wr_num, rd_num); wr_check(full, '0', afull, '1', over, '0');
ctrl(wclk, wen, '1', ren, '0', datai, x"FF", wr_num, rd_num); wr_check(full, '1', afull, '1', over, '0');
ctrl(wclk, wen, '0', ren, '1', datai, datai, wr_num, rd_num);
ctrl(wclk, wen, '0', ren, '1', datai, datai, wr_num, rd_num);
ctrl(wclk, wen, '0', ren, '1', datai, datai, wr_num, rd_num); rd_check(empty, '0', aempty, '0', under, '0');
ctrl(wclk, wen, '0', ren, '1', datai, datai, wr_num, rd_num); rd_check(empty, '0', aempty, '1', under, '0');
ctrl(wclk, wen, '0', ren, '1', datai, datai, wr_num, rd_num); rd_check(empty, '0', aempty, '1', under, '0');
ctrl(wclk, wen, '0', ren, '1', datai, datai, wr_num, rd_num); rd_check(empty, '1', aempty, '1', under, '0');
ctrl(wclk, wen, '0', ren, '0', datai, datai, wr_num, rd_num); rd_check(empty, '1', aempty, '1', under, '0');
print("* End of Test");
stop <= TRUE;
wait;
end process test_p;
read_p : process
begin
wait until rising_edge(wclk) and valid = '1';
assert datao=x"11" report "Received 0x"&to_str(datao,'H')&" but 0x11 awaited" severity failure;
wait until rising_edge(wclk) and valid = '1';
assert datao=x"22" report "Received 0x"&to_str(datao,'H')&" but 0x22 awaited" severity failure;
wait until rising_edge(wclk) and valid = '1';
assert datao=x"33" report "Received 0x"&to_str(datao,'H')&" but 0x33 awaited" severity failure;
wait until rising_edge(wclk) and valid = '1';
assert datao=x"44" report "Received 0x"&to_str(datao,'H')&" but 0x44 awaited" severity failure;
wait until rising_edge(wclk) and valid = '1';
assert datao=x"55" report "Received 0x"&to_str(datao,'H')&" but 0x55 awaited" severity failure;
wait until rising_edge(wclk) and valid = '1';
assert datao=x"66" report "Received 0x"&to_str(datao,'H')&" but 0x77 awaited" severity failure;
wait until rising_edge(wclk) and valid = '1';
-- x"77" was overflow
assert datao=x"88" report "Received 0x"&to_str(datao,'H')&" but 0x88 awaited" severity failure;
wait until rising_edge(wclk) and valid = '1';
assert datao=x"99" report "Received 0x"&to_str(datao,'H')&" but 0x99 awaited" severity failure;
wait until rising_edge(wclk) and valid = '1';
assert datao=x"AA" report "Received 0x"&to_str(datao,'H')&" but 0xAA awaited" severity failure;
wait until rising_edge(wclk) and valid = '1';
assert datao=x"BB" report "Received 0x"&to_str(datao,'H')&" but 0xBB awaited" severity failure;
wait until rising_edge(wclk) and valid = '1';
assert datao=x"CC" report "Received 0x"&to_str(datao,'H')&" but 0xDD awaited" severity failure;
wait until rising_edge(wclk) and valid = '1';
assert datao=x"DD" report "Received 0x"&to_str(datao,'H')&" but 0xEE awaited" severity failure;
wait until rising_edge(wclk) and valid = '1';
-- x"CC" was overflow
assert datao=x"FF" report "Received 0x"&to_str(datao,'H')&" but 0xFF awaited" severity failure;
wait until rising_edge(wclk) and valid = '1';
assert datao=x"00" report "Received 0x"&to_str(datao,'H')&" but 0x00 awaited" severity failure;
wait until rising_edge(wclk) and valid = '1';
assert datao=x"11" report "Received 0x"&to_str(datao,'H')&" but 0x11 awaited" severity failure;
wait until rising_edge(wclk) and valid = '1';
assert datao=x"22" report "Received 0x"&to_str(datao,'H')&" but 0x33 awaited" severity failure;
wait until rising_edge(wclk) and valid = '1';
assert datao=x"33" report "Received 0x"&to_str(datao,'H')&" but 0x33 awaited" severity failure;
wait until rising_edge(wclk) and valid = '1';
assert datao=x"44" report "Received 0x"&to_str(datao,'H')&" but 0x44 awaited" severity failure;
wait until rising_edge(wclk) and valid = '1';
-- x"55" was overflow
assert datao=x"66" report "Received 0x"&to_str(datao,'H')&" but 0x66 awaited" severity failure;
wait until rising_edge(wclk) and valid = '1';
assert datao=x"77" report "Received 0x"&to_str(datao,'H')&" but 0x77 awaited" severity failure;
wait until rising_edge(wclk) and valid = '1';
assert datao=x"88" report "Received 0x"&to_str(datao,'H')&" but 0x88 awaited" severity failure;
wait until rising_edge(wclk) and valid = '1';
assert datao=x"99" report "Received 0x"&to_str(datao,'H')&" but 0x99 awaited" severity failure;
wait until rising_edge(wclk) and valid = '1';
assert datao=x"AA" report "Received 0x"&to_str(datao,'H')&" but 0xAA awaited" severity failure;
wait until rising_edge(wclk) and valid = '1';
assert datao=x"BB" report "Received 0x"&to_str(datao,'H')&" but 0xBB awaited" severity failure;
wait until rising_edge(wclk) and valid = '1';
assert datao=x"CC" report "Received 0x"&to_str(datao,'H')&" but 0xBB awaited" severity failure;
wait until rising_edge(wclk) and valid = '1';
assert datao=x"DD" report "Received 0x"&to_str(datao,'H')&" but 0xBB awaited" severity failure;
wait until rising_edge(wclk) and valid = '1';
assert datao=x"EE" report "Received 0x"&to_str(datao,'H')&" but 0xBB awaited" severity failure;
wait until rising_edge(wclk) and valid = '1';
assert datao=x"FF" report "Received 0x"&to_str(datao,'H')&" but 0xBB awaited" severity failure;
wait;
end process read_p;
end architecture TestBench;
|
bsd-3-clause
|
INTI-CMNB-FPGA/fpga_lib
|
vhdl/sync/testbench/boundary_tb.vhdl
|
1
|
2332
|
--
-- Boundary Testbench
--
-- Author(s):
-- * Rodrigo A. Melo
--
-- Copyright (c) 2016 Authors and INTI
-- Distributed under the BSD 3-Clause License
--
library IEEE;
use IEEE.std_logic_1164.all;
library FPGALIB;
use FPGALIB.Simul.all;
use FPGALIB.Sync.all;
entity Boundary_Tb is
end entity Boundary_Tb;
architecture Test of Boundary_Tb is
constant FREQUENCY : positive:=150e6;
signal clk, rst : std_logic;
signal stop : boolean;
-- dut
constant PATTERN : std_logic_vector(3 downto 0):="1111";
type comma_t is array(0 to 23) of std_logic_vector (3 downto 0);
signal comma_in : comma_t:=(
"0000", -- aligned
"0000", -- aligned
"0000", -- aligned
"1000", -- 3
"0111", -- 3
"0000", -- 3
"1100", -- 2
"0011", -- 2
"0000", -- 2
"0000", -- 2
"1110", -- 1
"0001", -- 1
"0000", -- 1
"0000", -- 1
"1111", -- aligned
"0000", -- aligned
"0110", -- aligned
"1001", -- aligned
"0100", -- aligned
"0100", -- aligned
others => "0000"
);
signal index : natural:=0;
signal comma_aux, comma_out : std_logic_vector (3 downto 0);
signal data_out : std_logic_vector (31 downto 0);
begin
do_clk: Clock
generic map(FREQUENCY => FREQUENCY)
port map(clk_o => clk, rst_o => rst, stop_i => stop);
dut: Boundary
port map(
clk_i => clk,
pattern_i => PATTERN,
comma_i => comma_aux,
data_i => x"01234567",
comma_o => comma_out,
data_o => data_out
);
feeder: process
begin
wait until rising_edge(clk) and rst='0';
for i in 0 to 20 loop
comma_aux <= comma_in(i);
wait until rising_edge(clk);
end loop;
wait;
end process feeder;
checker: process
begin
wait until rising_edge(clk) and rst='0';
wait until rising_edge(clk) and comma_out="1111";
assert data_out=x"23456701";
wait until rising_edge(clk) and comma_out="1111";
assert data_out=x"45670123";
wait until rising_edge(clk) and comma_out="1111";
assert data_out=x"67012345";
wait until rising_edge(clk) and comma_out="1111";
assert data_out=x"01234567";
stop <= TRUE;
wait;
end process checker;
end architecture Test;
|
bsd-3-clause
|
freecores/wrimm
|
WrimmPackage.vhd
|
1
|
5073
|
--Propery of Tecphos Inc. See License.txt for license details
--Latest version of all project files available at http://opencores.org/project,wrimm
--See WrimmManual.pdf for the Wishbone Datasheet and implementation details.
--See wrimm subversion project for version history
library ieee;
use ieee.std_logic_1164.all;
package WrimmPackage is
constant WbAddrBits : Integer := 4;
constant WbDataBits : Integer := 8;
subtype WbAddrType is std_logic_vector(0 to WbAddrBits-1);
subtype WbDataType is std_logic_vector(0 to WbDataBits-1);
type WbMasterOutType is record
Strobe : std_logic; --Required
WrEn : std_logic;
Addr : WbAddrType;
Data : WbDataType;
--DataTag : std_logic_vector(0 to 1); --Write,Set,Clear,Toggle
Cyc : std_logic; --Required
--CycType : std_logic_vector(0 to 2); --For Burst Cycles
end record WbMasterOutType;
type WbSlaveOutType is record
Ack : std_logic; --Required
Err : std_logic;
Rty : std_logic;
Data : WbDataType;
end record WbSlaveOutType;
--=============================================================================
-------------------------------------------------------------------------------
-- Master Interfaces
-------------------------------------------------------------------------------
type WbMasterType is (
Q,
P);
type WbMasterOutArray is array (WbMasterType) of WbMasterOutType;
type WbSlaveOutArray is array (WbMasterType) of WbSlaveOutType;
type WbMasterGrantType is Array (WbMasterType'left to WbMasterType'right) of std_logic;
--=============================================================================
-------------------------------------------------------------------------------
-- Status Registers (Report internal results)
-------------------------------------------------------------------------------
type StatusFieldParams is record
BitWidth : integer;
MSBLoc : integer;
Address : WbAddrType;
end record StatusFieldParams;
type StatusFieldType is (
StatusA,
StatusB,
StatusC);
type StatusArrayType is Array (StatusFieldType'left to StatusFieldType'right) of WbDataType;
type StatusArrayBitType is Array (StatusFieldType'left to StatusFieldType'right) of std_logic;
type StatusFieldDefType is Array (StatusFieldType'left to StatusFieldType'right) of StatusFieldParams;
constant StatusParams : StatusFieldDefType :=(
StatusA => (BitWidth => 8, MSBLoc => 0, Address => x"0"),
StatusB => (BitWidth => 8, MSBLoc => 0, Address => x"1"),
StatusC => (BitWidth => 8, MSBLoc => 0, Address => x"2"));
--=============================================================================
-------------------------------------------------------------------------------
-- Setting Registers
-------------------------------------------------------------------------------
type SettingFieldParams is record
BitWidth : integer;
MSBLoc : integer;
Address : WbAddrType;
Default : WbDataType;
end record SettingFieldParams;
type SettingFieldType is (
SettingX,
SettingY,
SettingZ);
type SettingArrayType is Array (SettingFieldType'Left to SettingFieldType'Right) of WbDataType;
type SettingArrayBitType is Array (SettingFieldType'Left to SettingFieldType'Right) of std_logic;
type SettingFieldDefType is Array (SettingFieldType'Left to SettingFieldType'Right) of SettingFieldParams;
constant SettingParams : SettingFieldDefType :=(
SettingX => (BitWidth => 8, MSBLoc => 0, Address => x"6", Default => x"00"),
SettingY => (BitWidth => 8, MSBLoc => 0, Address => x"7", Default => x"00"),
SettingZ => (BitWidth => 8, MSBLoc => 0, Address => x"8", Default => x"00"));
--=============================================================================
-------------------------------------------------------------------------------
-- Trigger Registers (Report internal results)
-------------------------------------------------------------------------------
type TriggerFieldParams is record
BitLoc : integer;
Address : WbAddrType;
end record TriggerFieldParams;
type TriggerFieldType is (
TriggerR,
TriggerS,
TriggerT);
type TriggerArrayType is Array (TriggerFieldType'Left to TriggerFieldType'Right) of std_logic;
type TriggerFieldDefType is Array (TriggerFieldType'Left to TriggerFieldType'Right) of TriggerFieldParams;
constant TriggerParams : TriggerFieldDefType :=(
TriggerR => (BitLoc => 7, Address => x"A"),
TriggerS => (BitLoc => 7, Address => x"B"),
TriggerT => (BitLoc => 7, Address => x"C"));
end package WrimmPackage;
--package body WishBonePackage is
--
--
--
--end package body WishBonePackage;
|
bsd-3-clause
|
lanastasov/ace-builds
|
demo/kitchen-sink/docs/vhdl.vhd
|
472
|
830
|
library IEEE
user IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity COUNT16 is
port (
cOut :out std_logic_vector(15 downto 0); -- counter output
clkEn :in std_logic; -- count enable
clk :in std_logic; -- clock input
rst :in std_logic -- reset input
);
end entity;
architecture count_rtl of COUNT16 is
signal count :std_logic_vector (15 downto 0);
begin
process (clk, rst) begin
if(rst = '1') then
count <= (others=>'0');
elsif(rising_edge(clk)) then
if(clkEn = '1') then
count <= count + 1;
end if;
end if;
end process;
cOut <= count;
end architecture;
|
bsd-3-clause
|
sonologic/gmzpu
|
vhdl/testbenches/zwishbone_tb.vhdl
|
1
|
7086
|
------------------------------------------------------------------------------
---- ----
---- zwishbone testbench ----
---- ----
---- http://github.com/sonologic/gmzpu ----
---- ----
---- Description: ----
---- This is the testbench for the gmZPU core ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Salvador E. Tropea, salvador inti.gob.ar ----
---- - "Koen Martens" <gmc sonologic.nl> ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ----
---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ----
---- Copyright (c) 2014 Koen Martens ----
---- ----
---- Distributed under the BSD license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: zwishbone_TB ----
---- File name: gmzpu_tb.vhdl ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: zpu ----
---- Dependencies: IEEE.std_logic_1164 ----
---- IEEE.numeric_std ----
---- Target FPGA: n/a ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Modelsim ----
---- Simulation tools: Modelsim ----
---- Text editor: vim ----
---- ----
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library gmzpu;
use gmzpu.zwishbone;
entity zwishbone_TB is
end entity zwishbone_TB;
architecture Behave of zwishbone_TB is
constant CLK_FREQ : positive:=50; -- 50 MHz clock
constant CLK_S_PER : time:=1 us/(2.0*real(CLK_FREQ)); -- Clock semi period
component zwishbone_c_regs is
generic(
ADR_WIDTH : natural:=16;
DATA_WIDTH : natural:=32
);
port (
clk_i : in std_logic;
rst_i : in std_logic;
-- c_decode
en_i : in std_logic;
we_i : in std_logic;
adr_i : in unsigned(ADR_WIDTH-1 downto 0);
dat_i : in unsigned(DATA_WIDTH-1 downto 0);
dat_o : out unsigned(DATA_WIDTH-1 downto 0);
-- config register value (0x0000, for c_control)
cfg_o : out unsigned(DATA_WIDTH-1 downto 0)
);
end component zwishbone_c_regs;
signal clk : std_logic;
signal reset : std_logic:='1';
signal break : std_logic;
signal enable : std_logic;
signal we : std_logic;
signal adr : unsigned(15 downto 0);
signal dat_o : unsigned(31 downto 0);
signal dat_i : unsigned(31 downto 0);
signal cfg : unsigned(31 downto 0);
begin
c_regs : zwishbone_c_regs
generic map(
ADR_WIDTH => 16,
DATA_WIDTH => 32
)
port map(
clk_i => clk,
rst_i => reset,
en_i => enable,
we_i => we,
adr_i => adr,
dat_i => dat_o,
dat_o => dat_i,
cfg_o => cfg
);
do_clock:
process
begin
clk <= '0';
wait for CLK_S_PER;
clk <= '1';
wait for CLK_S_PER;
end process do_clock;
do_reset:
process
begin
wait until rising_edge(clk);
reset <= '0';
end process do_reset;
do_test:
process(clk)
variable state : integer:=0;
begin
if rising_edge(clk) then
if reset='1' then
adr <= (others => '0');
dat_o <= (others => '0');
enable <= '0';
we <= '0';
else
case state is
when 0 =>
adr <= (others => '0');
dat_o <= to_unsigned(2, dat_o'length);
we <= '1';
enable <= '1';
state := state + 1;
when 1 =>
adr <= (others => '0');
dat_o <= to_unsigned(2, dat_o'length);
we <= '1';
enable <= '1';
state := state + 1;
when 2 =>
we <= '0';
enable <= '0';
state := state + 1;
when 3 =>
we <= '0';
enable <= '0';
state := state + 1;
when 4 =>
adr <= (others => '0');
enable <= '1';
state := state + 1;
when 5 =>
adr <= (others => '0');
enable <= '1';
state := state +1;
when others =>
state := state + 1;
end case;
end if;
end if;
end process do_test;
end architecture Behave; -- Entity: zwishbone_TB
|
bsd-3-clause
|
sonologic/gmzpu
|
vhdl/wb_slaves/wb_slaves_pkg.vhdl
|
1
|
590
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
package tutorial is
component WBOPRT08 is
port(
-- WISHBONE SLAVE interface:
ACK_O : out std_logic;
CLK_I : in std_logic;
DAT_I : in std_logic_vector( 7 downto 0 );
DAT_O : out std_logic_vector( 7 downto 0 );
RST_I : in std_logic;
STB_I : in std_logic;
WE_I : in std_logic;
-- Output port (non-WISHBONE signals):
PRT_O : out std_logic_vector( 7 downto 0 )
);
end component WBOPRT08;
end package tutorial;
|
bsd-3-clause
|
sonologic/gmzpu
|
vhdl/devices/br_gen.vhdl
|
1
|
4728
|
------------------------------------------------------------------------------
---- ----
---- RS-232 baudrate generator ----
---- ----
---- http://www.opencores.org/ ----
---- ----
---- Description: ----
---- This counter is a parametrizable clock divider. The count value is ----
---- the generic parameter COUNT. It has a chip enable ce_i input. ----
---- (will count only if CE is high). ----
---- When it overflows, will emit a pulse on o_o. ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Philippe Carton, philippe.carton2 libertysurf.fr ----
---- - Juan Pablo Daniel Borgna, jpdborgna gmail.com ----
---- - Salvador E. Tropea, salvador inti.gob.ar ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2001-2003 Philippe Carton ----
---- Copyright (c) 2005 Juan Pablo Daniel Borgna ----
---- Copyright (c) 2005-2008 Salvador E. Tropea ----
---- Copyright (c) 2005-2008 Instituto Nacional de Tecnología Industrial ----
---- ----
---- Distributed under the GPL license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: BRGen(Behaviour) (Entity and architecture) ----
---- File name: br_gen.vhdl ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: zpu ----
---- Dependencies: IEEE.std_logic_1164 ----
---- Target FPGA: Spartan ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ----
---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----
---- Text editor: SETEdit 0.5.x ----
---- ----
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity BRGen is
generic(
COUNT : integer range 0 to 65535);-- Count revolution
port (
clk_i : in std_logic; -- Clock
reset_i : in std_logic; -- Reset input
ce_i : in std_logic; -- Chip Enable
o_o : out std_logic); -- Output
end entity BRGen;
architecture Behaviour of BRGen is
begin
CountGen:
if COUNT/=1 generate
Counter:
process (clk_i)
variable cnt : integer range 0 to COUNT-1;
begin
if rising_edge(clk_i) then
o_o <= '0';
if reset_i='1' then
cnt:=COUNT-1;
elsif ce_i='1' then
if cnt=0 then
o_o <= '1';
cnt:=COUNT-1;
else
cnt:=cnt-1;
end if; -- cnt/=0
end if; -- ce_i='1'
end if; -- rising_edge(clk_i)
end process Counter;
end generate CountGen;
CountWire:
if COUNT=1 generate
o_o <= '0' when reset_i='1' else ce_i;
end generate CountWire;
end architecture Behaviour; -- Entity: BRGen
|
bsd-3-clause
|
seiken-chuouniv/ecorun
|
ecorun_fi_hardware/fi_timer/FiTimer/TestStepper.vhd
|
1
|
2948
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:02:15 09/10/2016
-- Design Name:
-- Module Name: C:/Users/Yoshio/git/ecorun/ecorun_fi_hardware/fi_timer/FiTimer/TestStepper.vhd
-- Project Name: FiTimer
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: Stepper
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY TestStepper IS
END TestStepper;
ARCHITECTURE behavior OF TestStepper IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Stepper
PORT(
iac_pulse : IN std_logic;
iac_clockwise : IN std_logic;
iac_out : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
signal iac_pulse : std_logic := '0';
signal iac_clockwise : std_logic := '0';
--Outputs
signal iac_out : std_logic_vector(7 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Stepper PORT MAP (
iac_pulse => iac_pulse,
iac_clockwise => iac_clockwise,
iac_out => iac_out
);
-- Clock process definitions
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clk_period*10;
-- insert stimulus here
iac_clockwise <= '1';
iac_pulse <= '1';
wait for 10 ns;
iac_pulse <= '0';
wait for 10 ns;
iac_pulse <= '1';
wait for 10 ns;
iac_pulse <= '0';
wait for 10 ns;
iac_pulse <= '1';
wait for 10 ns;
iac_pulse <= '0';
wait for 10 ns;
iac_pulse <= '1';
wait for 10 ns;
iac_pulse <= '0';
wait for 10 ns;
iac_pulse <= '1';
wait for 10 ns;
iac_pulse <= '0';
wait for 10 ns;
iac_pulse <= '1';
wait for 10 ns;
iac_pulse <= '0';
wait for 10 ns;
iac_pulse <= '1';
wait for 10 ns;
iac_pulse <= '0';
wait for 10 ns;
iac_pulse <= '1';
wait for 10 ns;
iac_pulse <= '0';
wait for 10 ns;
wait;
end process;
END;
|
bsd-3-clause
|
sonologic/gmzpu
|
vhdl/testbenches/small1_tb.vhdl
|
1
|
6355
|
------------------------------------------------------------------------------
---- ----
---- Testbench for the ZPU Small connection to the FPGA ----
---- ----
---- http://www.opencores.org/ ----
---- ----
---- Description: ----
---- This is a testbench to simulate the ZPU_Small1 core as used in the ----
---- *_small1.vhdl ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Salvador E. Tropea, salvador inti.gob.ar ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ----
---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ----
---- ----
---- Distributed under the BSD license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: Small1_TB(Behave) (Entity and architecture) ----
---- File name: small1_tb.vhdl ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: work ----
---- Dependencies: IEEE.std_logic_1164 ----
---- IEEE.numeric_std ----
---- zpu.zpupkg ----
---- zpu.txt_util ----
---- work.zpu_memory ----
---- Target FPGA: Spartan 3 (XC3S1500-4-FG456) ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: N/A ----
---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----
---- Text editor: SETEdit 0.5.x ----
---- ----
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library zpu;
use zpu.zpupkg.all;
use zpu.txt_util.all;
library work;
use work.zpu_memory.all;
entity Small1_TB is
end entity Small1_TB;
architecture Behave of Small1_TB is
constant WORD_SIZE : natural:=32; -- 32 bits data path
constant ADDR_W : natural:=18; -- 18 bits address space=256 kB, 128 kB I/O
constant BRAM_W : natural:=15; -- 15 bits RAM space=32 kB
constant D_CARE_VAL : std_logic:='0'; -- Fill value
constant CLK_FREQ : positive:=50; -- 50 MHz clock
constant CLK_S_PER : time:=1 us/(2.0*real(CLK_FREQ)); -- Clock semi period
constant BRATE : positive:=115200;
component ZPU_Small1 is
generic(
WORD_SIZE : natural:=32; -- 32 bits data path
D_CARE_VAL : std_logic:='0'; -- Fill value
CLK_FREQ : positive:=50; -- 50 MHz clock
BRATE : positive:=115200; -- RS232 baudrate
ADDR_W : natural:=16; -- 16 bits address space=64 kB, 32 kB I/O
BRAM_W : natural:=15); -- 15 bits RAM space=32 kB
port(
clk_i : in std_logic; -- CPU clock
rst_i : in std_logic; -- Reset
break_o : out std_logic; -- Break executed
dbg_o : out zpu_dbgo_t; -- Debug info
rs232_tx_o : out std_logic; -- UART Tx
rs232_rx_i : in std_logic; -- UART Rx
gpio_in : in std_logic_vector(31 downto 0);
gpio_out : out std_logic_vector(31 downto 0);
gpio_dir : out std_logic_vector(31 downto 0) -- 1 = in, 0 = out
);
end component ZPU_Small1;
signal clk : std_logic;
signal reset : std_logic:='1';
signal break : std_logic;
signal dbg : zpu_dbgo_t; -- Debug info
signal rs232_tx : std_logic;
signal rs232_rx : std_logic;
begin
zpu : ZPU_Small1
generic map(
WORD_SIZE => WORD_SIZE, D_CARE_VAL => D_CARE_VAL,
CLK_FREQ => CLK_FREQ, BRATE => BRATE, ADDR_W => ADDR_W,
BRAM_W => BRAM_W)
port map(
clk_i => clk, rst_i => reset, rs232_tx_o => rs232_tx,
rs232_rx_i => rs232_rx, break_o => break, dbg_o => dbg,
gpio_in => (others => '0'));
trace_mod : Trace
generic map(
ADDR_W => ADDR_W, WORD_SIZE => WORD_SIZE,
LOG_FILE => "small1_trace.log")
port map(
clk_i => clk, dbg_i => dbg, stop_i => break, busy_i => '0');
do_clock:
process
begin
clk <= '0';
wait for CLK_S_PER;
clk <= '1';
wait for CLK_S_PER;
if break='1' then
print("* Break asserted, end of test");
wait;
end if;
end process do_clock;
do_reset:
process
begin
wait until rising_edge(clk);
reset <= '0';
end process do_reset;
end architecture Behave; -- Entity: Small1_TB
|
bsd-3-clause
|
loa-org/loa-hdl
|
modules/motor_control/tb/bldc_motor_module_tb.vhd
|
2
|
4318
|
-------------------------------------------------------------------------------
-- Title : Testbench for design "bldc_motor_module"
-------------------------------------------------------------------------------
-- Author : Fabian Greif <fabian@kleinvieh>
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2011
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.bus_pkg.all;
use work.motor_control_pkg.all;
-------------------------------------------------------------------------------
entity bldc_motor_module_tb is
end bldc_motor_module_tb;
-------------------------------------------------------------------------------
architecture tb of bldc_motor_module_tb is
-- component generics
constant BASE_ADDRESS : positive := 16#0100#;
constant WIDTH : positive := 8;
constant PRESCALER : positive := 2;
-- component ports
signal driver_stage : bldc_driver_stage_type;
signal hall : hall_sensor_type := ('0', '0', '0');
signal break : std_logic := '0';
signal bus_o : busdevice_out_type;
signal bus_i : busdevice_in_type :=
(addr => (others => '0'),
data => (others => '0'),
we => '0',
re => '0');
signal clk : std_logic := '0';
begin
-- component instantiation
DUT : bldc_motor_module
generic map (
BASE_ADDRESS => BASE_ADDRESS,
WIDTH => WIDTH,
PRESCALER => PRESCALER)
port map (
driver_stage_p => driver_stage,
hall_p => hall,
break_p => break,
bus_o => bus_o,
bus_i => bus_i,
clk => clk);
-- clock generation
clk <= not clk after 10 ns;
bus_waveform : process
begin
wait for 100 ns;
-- wrong address
wait until rising_edge(clk);
bus_i.addr <= std_logic_vector(unsigned'(resize(x"0020", bus_i.addr'length)));
bus_i.data <= x"0123";
bus_i.we <= '1';
wait until rising_edge(clk);
bus_i.we <= '0';
wait for 30 US;
-- correct address
wait until rising_edge(clk);
bus_i.addr <= std_logic_vector(unsigned'(resize(x"0100", bus_i.addr'length)));
bus_i.data <= x"00f0";
bus_i.we <= '1';
wait until rising_edge(clk);
bus_i.we <= '0';
wait for 30 US;
-- wrong address
wait until rising_edge(clk);
bus_i.addr <= std_logic_vector(unsigned'(resize(x"0110", bus_i.addr'length)));
bus_i.data <= x"0123";
bus_i.we <= '1';
wait until rising_edge(clk);
bus_i.we <= '0';
wait for 630 US;
wait until rising_edge(clk);
bus_i.addr <= std_logic_vector(unsigned'(resize(x"0100", bus_i.addr'length)));
bus_i.data <= x"000f";
bus_i.we <= '1';
wait until rising_edge(clk);
bus_i.we <= '0';
wait for 100 US;
-- Disable PWM via Shutdown
wait until rising_edge(clk);
bus_i.addr <= std_logic_vector(unsigned'(resize(x"0100", bus_i.addr'length)));
bus_i.data <= x"800f";
bus_i.we <= '1';
wait until rising_edge(clk);
bus_i.we <= '0';
end process;
hall_sensor_waveform : process
begin
wait for 50 US;
hall <= ('1', '0', '1');
wait for 100 US;
hall <= ('1', '0', '0');
wait for 100 US;
hall <= ('1', '1', '0');
wait for 100 US;
hall <= ('0', '1', '0');
wait for 100 US;
hall <= ('0', '1', '1');
wait for 100 US;
hall <= ('0', '0', '1');
wait for 100 US;
hall <= ('1', '0', '1');
wait for 100 US;
hall <= ('1', '0', '0');
wait for 100 US;
hall <= ('1', '1', '0');
wait for 100 US;
hall <= ('0', '1', '0');
wait for 100 US;
hall <= ('0', '1', '1');
wait for 100 US;
hall <= ('0', '0', '1');
end process;
-- Test break signal
process
begin
wait for 220 US;
break <= '1';
wait for 50 US;
break <= '0';
end process;
end tb;
|
bsd-3-clause
|
loa-org/loa-hdl
|
modules/motor_control/hdl/symmetric_pwm.vhd
|
2
|
3874
|
-------------------------------------------------------------------------------
-- Title : Symmetric PWM generator
-- Project : Loa
-------------------------------------------------------------------------------
-- Author : Fabian Greif <[email protected]>
-- Company : Roboterclub Aachen e.V.
-- Platform : Spartan 3-400
-------------------------------------------------------------------------------
-- Description:
--
-- Generates a center aligned PWM with deadtime. The deadtime and register width
-- can be changed by generics.
--
-- PWM frequency (f_pwm) is: f_pwm = clk / ((2 ^ width) - 1)
--
-- Example:
-- clk = 50 MHz
-- clk_en = constant '1' (no prescaler)
-- width = 8 => value = 0..255
--
-- => f_pwm = 1/510ns = 0,1960784 MHz = 50/255 MHz
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package symmetric_pwm_pkg is
component symmetric_pwm is
generic (
WIDTH : natural);
port (
pwm_p : out std_logic;
underflow_p : out std_logic;
overflow_p : out std_logic;
clk_en_p : in std_logic;
value_p : in std_logic_vector (WIDTH - 1 downto 0);
reset : in std_logic;
clk : in std_logic);
end component symmetric_pwm;
end package symmetric_pwm_pkg;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity symmetric_pwm is
generic (
WIDTH : natural := 12); -- Number of bits used for the PWM (12bit => 0..4095)
port (
pwm_p : out std_logic; -- PWM output
underflow_p : out std_logic; -- PWM is in the middle of the 'on'-periode
overflow_p : out std_logic; -- PWM is in the middle of the 'off'-periode
clk_en_p : in std_logic; -- clock enable
value_p : in std_logic_vector (WIDTH - 1 downto 0);
reset : in std_logic; -- High active, Restarts the PWM period
clk : in std_logic
);
end symmetric_pwm;
-- ----------------------------------------------------------------------------
architecture behavioral of symmetric_pwm is
signal count : integer range 0 to ((2 ** WIDTH) - 2) := 0;
signal value_buf : std_logic_vector(width - 1 downto 0) := (others => '0');
signal dir : std_logic := '0'; -- 0 = up
begin
-- Counter
process
begin
wait until rising_edge(clk);
if reset = '1' then
-- Load new value and reset counter => restart periode
count <= 0;
value_buf <= value_p;
underflow_p <= '0';
overflow_p <= '0';
elsif clk_en_p = '1' then
underflow_p <= '0';
overflow_p <= '0';
-- counter
if (dir = '0') then -- up
if count < ((2 ** WIDTH) - 2) then
count <= count + 1;
else
dir <= '1';
count <= count - 1;
overflow_p <= '1';
-- Load new value from the shadow register (not active before
-- the next clock cycle)
value_buf <= value_p;
end if;
else -- down
if (count > 0) then
count <= count - 1;
else
dir <= '0';
count <= count + 1;
underflow_p <= '1';
end if;
end if;
end if;
end process;
-- Generate Output
process
begin
wait until rising_edge(clk);
if reset = '1' then
pwm_p <= '0';
else
-- comparator for the output
if count >= to_integer(unsigned(value_buf)) then
pwm_p <= '0';
else
pwm_p <= '1';
end if;
end if;
end process;
end behavioral;
|
bsd-3-clause
|
olgirard/openmsp430
|
fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x8k_dp/example_design/ram_16x8k_dp_prod.vhd
|
1
|
10701
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: ram_16x8k_dp_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : spartan6
-- C_XDEVICEFAMILY : spartan6
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 2
-- C_BYTE_SIZE : 8
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 0
-- C_INIT_FILE_NAME : no_coe_file_loaded
-- C_USE_DEFAULT_DATA : 0
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 1
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 1
-- C_WEA_WIDTH : 2
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 16
-- C_READ_WIDTH_A : 16
-- C_WRITE_DEPTH_A : 8192
-- C_READ_DEPTH_A : 8192
-- C_ADDRA_WIDTH : 13
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 1
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 1
-- C_WEB_WIDTH : 2
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 16
-- C_READ_WIDTH_B : 16
-- C_WRITE_DEPTH_B : 8192
-- C_READ_DEPTH_B : 8192
-- C_ADDRB_WIDTH : 13
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 1
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY ram_16x8k_dp_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(12 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END ram_16x8k_dp_prod;
ARCHITECTURE xilinx OF ram_16x8k_dp_prod IS
COMPONENT ram_16x8k_dp_exdes IS
PORT (
--Port A
ENA : IN STD_LOGIC; --opt port
WEA : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Port B
ENB : IN STD_LOGIC; --opt port
WEB : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : ram_16x8k_dp_exdes
PORT MAP (
--Port A
ENA => ENA,
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA,
--Port B
ENB => ENB,
WEB => WEB,
ADDRB => ADDRB,
DINB => DINB,
DOUTB => DOUTB,
CLKB => CLKB
);
END xilinx;
|
bsd-3-clause
|
kirbyfan64/breathe
|
examples/doxygen/mux.vhdl
|
37
|
860
|
-------------------------------------------------------
--! @file
--! @brief 2:1 Mux using with-select
-------------------------------------------------------
--! Use standard library
library ieee;
--! Use logic elements
use ieee.std_logic_1164.all;
--! Mux entity brief description
--! Detailed description of this
--! mux design element.
entity mux_using_with is
port (
din_0 : in std_logic; --! Mux first input
din_1 : in std_logic; --! Mux Second input
sel : in std_logic; --! Select input
mux_out : out std_logic --! Mux output
);
end entity;
--! @brief Architecture definition of the MUX
--! @details More details about this mux element.
architecture behavior of mux_using_with is
begin
with (sel) select
mux_out <= din_0 when '0',
din_1 when others;
end architecture;
|
bsd-3-clause
|
gjtorikian/ace
|
demo/kitchen-sink/docs/vhdl.vhd
|
472
|
830
|
library IEEE
user IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity COUNT16 is
port (
cOut :out std_logic_vector(15 downto 0); -- counter output
clkEn :in std_logic; -- count enable
clk :in std_logic; -- clock input
rst :in std_logic -- reset input
);
end entity;
architecture count_rtl of COUNT16 is
signal count :std_logic_vector (15 downto 0);
begin
process (clk, rst) begin
if(rst = '1') then
count <= (others=>'0');
elsif(rising_edge(clk)) then
if(clkEn = '1') then
count <= count + 1;
end if;
end if;
end process;
cOut <= count;
end architecture;
|
bsd-3-clause
|
larskuhtz/MoCS
|
vhdl/countdown.vhdl
|
1
|
1533
|
-- *** MOCS-COPYRIGHT-NOTICE-BEGIN ***
--
-- This copyright notice is auto-generated by ./add-copyright-notice.
-- Additional copyright notices must be added below the last line of this notice.
--
-- MoCS (https://lewis.cs.uni-saarland.de/tools/mocs/): "vhdl/countdown.vhdl".
-- The content of this file is copyright of Saarland University -
-- Copyright (C) 2009 Saarland University, Reactive Systems Group, Lars Kuhtz.
--
-- This file is part of MoCS (https://lewis.cs.uni-saarland.de/tools/mocs/).
--
-- License: three-clause BSD style license.
-- The license text can be found in the file LICENSE.
--
-- *** MOCS-COPYRIGHT-NOTICE-END ***
-- Static down-counter based on integer decrement
-- Counts clock ticks
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity countdown is
generic(max : Integer := 0);
port(CLOCK : in STD_LOGIC;
output : out STD_LOGIC := '1');
end countdown;
-- Better provide a structural architecture
architecture Behavioral of countdown is
begin
process(CLOCK)
variable cnt: Integer := max-1;
begin
if (max > 0) then
if (cnt > -1 and CLOCK'event and CLOCK='1') then
cnt := cnt - 1;
end if;
if (cnt = 0) then output <= '1'; end if;
if (cnt = -1) then output <= '0'; end if;
else
if (CLOCK'event and CLOCK='1') then
cnt := cnt - 1;
end if;
if (cnt = -2) then output <= '1'; end if;
if (cnt < -2) then output <= '0'; end if;
end if;
end process;
end Behavioral;
|
bsd-3-clause
|
Xilinx/PYNQ
|
boards/ip/audio_codec_ctrl_v1.0/src/iis_ser.vhd
|
4
|
4342
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:20:51 08/06/2012
-- Design Name:
-- Module Name: iis_ser - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
entity iis_ser is
Port ( CLK_100MHZ : in STD_LOGIC; --gbuf clock
SCLK : in STD_LOGIC; --logic (not used as clk)
LRCLK : in STD_LOGIC; --logic (not used as clk)
SDATA : out STD_LOGIC;
EN : in STD_LOGIC;
LDATA : in STD_LOGIC_VECTOR (23 downto 0);
RDATA : in STD_LOGIC_VECTOR (23 downto 0));
end iis_ser;
architecture Behavioral of iis_ser is
--bit cntr counts to 25 (not 24) so that it can set sdata to zero after
--the 24th bit has been sent to the receiver
constant bit_cntr_max : std_logic_vector(4 downto 0) := "11001";--25
type IIS_STATE_TYPE is (RESET, WAIT_LEFT, WRITE_LEFT, WAIT_RIGHT, WRITE_RIGHT);
signal start_left : std_logic;
signal start_right : std_logic;
signal write_bit : std_logic;
signal sclk_d1 : std_logic := '0';
signal lrclk_d1 : std_logic := '0';
signal bit_cntr : std_logic_vector(4 downto 0) := (others => '0');
signal ldata_reg : std_logic_vector(23 downto 0) := (others => '0');
signal rdata_reg : std_logic_vector(23 downto 0) := (others => '0');
signal sdata_reg : std_logic := '0';
signal iis_state : IIS_STATE_TYPE := RESET;
begin
process(CLK_100MHZ)
begin
if (rising_edge(CLK_100MHZ)) then
sclk_d1 <= SCLK;
lrclk_d1 <= LRCLK;
end if;
end process;
--Detect falling edge on LRCLK
start_left <= (lrclk_d1 and not(LRCLK));
--Detect rising edge on LRCLK
start_right <= (not(lrclk_d1) and LRCLK);
--Detect falling edge on SCLK
write_bit <= (sclk_d1 and not(SCLK));
--Next state logic
next_iis_state_process : process (CLK_100MHZ)
begin
if (rising_edge(CLK_100MHZ)) then
case iis_state is
when RESET =>
if (EN = '1') then
iis_state <= WAIT_LEFT;
end if;
when WAIT_LEFT =>
if (EN = '0') then
iis_state <= RESET;
elsif (start_left = '1') then
iis_state <= WRITE_LEFT;
end if;
when WRITE_LEFT =>
if (EN = '0') then
iis_state <= RESET;
elsif (bit_cntr = bit_cntr_max) then
iis_state <= WAIT_RIGHT;
end if;
when WAIT_RIGHT =>
if (EN = '0') then
iis_state <= RESET;
elsif (start_right = '1') then
iis_state <= WRITE_RIGHT;
end if;
when WRITE_RIGHT =>
if (EN = '0') then
iis_state <= RESET;
elsif (bit_cntr = bit_cntr_max) then
iis_state <= WAIT_LEFT;
end if;
when others=> --should never be reached
iis_state <= RESET;
end case;
end if;
end process;
process (CLK_100MHZ)
begin
if (rising_edge(CLK_100MHZ)) then
if (iis_state = WRITE_RIGHT or iis_state = WRITE_LEFT) then
if (write_bit = '1') then
bit_cntr <= bit_cntr + 1;
end if;
else
bit_cntr <= (others => '0');
end if;
end if;
end process;
data_shift_proc : process (CLK_100MHZ)
begin
if (rising_edge(CLK_100MHZ)) then
if (iis_state = RESET) then
ldata_reg <= (others => '0');
rdata_reg <= (others => '0');
elsif ((iis_state = WAIT_LEFT) and (start_left = '1')) then
ldata_reg <= LDATA;
rdata_reg <= RDATA;
else
if (iis_state = WRITE_LEFT and write_bit = '1') then
ldata_reg(23 downto 1) <= ldata_reg(22 downto 0);
ldata_reg(0) <= '0';
end if;
if (iis_state = WRITE_RIGHT and write_bit = '1') then
rdata_reg(23 downto 1) <= rdata_reg(22 downto 0);
rdata_reg(0) <= '0';
end if;
end if;
end if;
end process data_shift_proc;
sdata_update_proc : process (CLK_100MHZ)
begin
if (rising_edge(CLK_100MHZ)) then
if (iis_state = RESET) then
sdata_reg <= '0';
elsif (iis_state = WRITE_LEFT and write_bit = '1') then
sdata_reg <= ldata_reg(23);
elsif (iis_state = WRITE_RIGHT and write_bit = '1') then
sdata_reg <= rdata_reg(23);
end if;
end if;
end process sdata_update_proc;
SDATA <= sdata_reg;
end Behavioral;
|
bsd-3-clause
|
larskuhtz/MoCS
|
vhdl/pipeline_tb.vhdl
|
1
|
1502
|
-- *** MOCS-COPYRIGHT-NOTICE-BEGIN ***
--
-- This copyright notice is auto-generated by ./add-copyright-notice.
-- Additional copyright notices must be added below the last line of this notice.
--
-- MoCS (https://lewis.cs.uni-saarland.de/tools/mocs/): "vhdl/pipeline_tb.vhdl".
-- The content of this file is copyright of Saarland University -
-- Copyright (C) 2009 Saarland University, Reactive Systems Group, Lars Kuhtz.
--
-- This file is part of MoCS (https://lewis.cs.uni-saarland.de/tools/mocs/).
--
-- License: three-clause BSD style license.
-- The license text can be found in the file LICENSE.
--
-- *** MOCS-COPYRIGHT-NOTICE-END ***
-- ----------------------------------------------------------------- --
-- use work.general.all;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.numeric_std.all;
use work.pipeline;
-- the pipeline for a single prop
entity pipeline_tb is
end pipeline_tb;
architecture Behavioral of pipeline_tb is
signal CLOCK : STD_LOGIC;
signal i : STD_LOGIC;
signal o : unsigned(5 downto 0);
begin
pipeline0: entity work.pipeline(Behavioral)
generic map (LENGTH => 5)
port map (CLOCK,i,o);
clk: process
begin
CLOCK <= '1'; wait for 5 ns;
CLOCK <= '0'; wait for 5 ns;
end process;
stimulus: process
begin
i <= '0'; wait for 8 ns;
i <= '1'; wait for 11 ns;
i <= '0'; wait for 13 ns;
i <= '1'; wait for 3 ns;
wait;
end process;
end Behavioral;
|
bsd-3-clause
|
VectorBlox/risc-v
|
ip/orca/hdl/decode.vhd
|
1
|
12756
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library work;
use work.rv_components.all;
use work.constants_pkg.all;
use work.utils.all;
entity decode is
generic (
REGISTER_SIZE : positive range 32 to 32;
SIGN_EXTENSION_SIZE : positive;
VCP_ENABLE : vcp_type;
PIPELINE_STAGES : natural range 1 to 2;
WRITE_FIRST_SMALL_RAMS : boolean;
FAMILY : string
);
port (
clk : in std_logic;
reset : in std_logic;
to_rf_select : in std_logic_vector(REGISTER_NAME_SIZE-1 downto 0);
to_rf_data : in std_logic_vector(REGISTER_SIZE-1 downto 0);
to_rf_valid : in std_logic;
to_decode_instruction : in std_logic_vector(INSTRUCTION_SIZE(vcp_type'(DISABLED))-1 downto 0);
to_decode_program_counter : in unsigned(REGISTER_SIZE-1 downto 0);
to_decode_predicted_pc : in unsigned(REGISTER_SIZE-1 downto 0);
to_decode_valid : in std_logic;
from_decode_ready : buffer std_logic;
from_decode_incomplete_instruction : out std_logic;
quash_decode : in std_logic;
decode_idle : out std_logic;
from_decode_rs1_data : out std_logic_vector(REGISTER_SIZE-1 downto 0);
from_decode_rs2_data : out std_logic_vector(REGISTER_SIZE-1 downto 0);
from_decode_rs3_data : out std_logic_vector(REGISTER_SIZE-1 downto 0);
from_decode_sign_extension : out std_logic_vector(SIGN_EXTENSION_SIZE-1 downto 0);
from_decode_program_counter : out unsigned(REGISTER_SIZE-1 downto 0);
from_decode_predicted_pc : out unsigned(REGISTER_SIZE-1 downto 0);
from_decode_instruction : out std_logic_vector(INSTRUCTION_SIZE(VCP_ENABLE)-1 downto 0);
from_decode_next_instruction : out std_logic_vector(INSTRUCTION_SIZE(vcp_type'(DISABLED))-1 downto 0);
from_decode_next_valid : out std_logic;
from_decode_valid : out std_logic;
to_decode_ready : in std_logic
);
end;
architecture rtl of decode is
signal from_decode_incomplete_instruction_signal : std_logic;
signal from_decode_instruction_signal : std_logic_vector(from_decode_instruction'range);
signal from_decode_valid_signal : std_logic;
alias to_decode_rs1_select : std_logic_vector(REGISTER_NAME_SIZE-1 downto 0) is
to_decode_instruction(REGISTER_RS1'range);
alias to_decode_rs2_select : std_logic_vector(REGISTER_NAME_SIZE-1 downto 0) is
to_decode_instruction(REGISTER_RS2'range);
alias to_decode_rs3_select : std_logic_vector(REGISTER_NAME_SIZE-1 downto 0) is
to_decode_instruction(REGISTER_RD'range);
signal rs1_select : std_logic_vector(REGISTER_NAME_SIZE-1 downto 0);
signal rs2_select : std_logic_vector(REGISTER_NAME_SIZE-1 downto 0);
signal rs3_select : std_logic_vector(REGISTER_NAME_SIZE-1 downto 0);
signal from_stage1_program_counter : unsigned(REGISTER_SIZE-1 downto 0);
signal from_stage1_predicted_pc : unsigned(REGISTER_SIZE-1 downto 0);
signal from_stage1_instruction : std_logic_vector(from_decode_instruction'range);
signal from_stage1_valid : std_logic;
signal to_stage1_ready : std_logic;
alias from_stage1_rs1_select : std_logic_vector(REGISTER_NAME_SIZE-1 downto 0) is
from_stage1_instruction(REGISTER_RS1'range);
alias from_stage1_rs2_select : std_logic_vector(REGISTER_NAME_SIZE-1 downto 0) is
from_stage1_instruction(REGISTER_RS2'range);
alias from_stage1_rs3_select : std_logic_vector(REGISTER_NAME_SIZE-1 downto 0) is
from_stage1_instruction(REGISTER_RD'range);
alias from_decode_rs1_select : std_logic_vector(REGISTER_NAME_SIZE-1 downto 0) is
from_decode_instruction_signal(REGISTER_RS1'range);
alias from_decode_rs2_select : std_logic_vector(REGISTER_NAME_SIZE-1 downto 0) is
from_decode_instruction_signal(REGISTER_RS2'range);
alias from_decode_rs3_select : std_logic_vector(REGISTER_NAME_SIZE-1 downto 0) is
from_decode_instruction_signal(REGISTER_RD'range);
signal rs1_data : std_logic_vector(REGISTER_SIZE-1 downto 0);
signal rs2_data : std_logic_vector(REGISTER_SIZE-1 downto 0);
signal rs3_data : std_logic_vector(REGISTER_SIZE-1 downto 0);
signal wb_select : std_logic_vector(REGISTER_NAME_SIZE-1 downto 0);
signal wb_data : std_logic_vector(REGISTER_SIZE-1 downto 0);
signal wb_enable : std_logic;
signal to_decode_sixty_four_bit_instruction : std_logic;
signal from_stage1_incomplete_instruction : std_logic;
begin
from_decode_incomplete_instruction <= from_decode_incomplete_instruction_signal;
from_decode_instruction <= from_decode_instruction_signal;
from_decode_valid <= from_decode_valid_signal;
the_register_file : register_file
generic map (
REGISTER_SIZE => REGISTER_SIZE,
REGISTER_NAME_SIZE => REGISTER_NAME_SIZE,
READ_PORTS => CONDITIONAL(VCP_ENABLE /= DISABLED, 3, 2),
WRITE_FIRST_SMALL_RAMS => WRITE_FIRST_SMALL_RAMS
)
port map(
clk => clk,
rs1_select => rs1_select,
rs2_select => rs2_select,
rs3_select => rs3_select,
wb_select => wb_select,
wb_data => wb_data,
wb_enable => wb_enable,
rs1_data => rs1_data,
rs2_data => rs2_data,
rs3_data => rs3_data
);
-- This is to handle Microsemi board's inability to initialize RAM to zero on startup.
reg_rst_en : if FAMILY = "MICROSEMI" generate
wb_select <= to_rf_select when reset = '0' else (others => '0');
wb_data <= to_rf_data when reset = '0' else (others => '0');
wb_enable <= to_rf_valid when reset = '0' else '1';
end generate reg_rst_en;
reg_rst_nen : if FAMILY /= "MICROSEMI" generate
wb_select <= to_rf_select;
wb_data <= to_rf_data;
wb_enable <= to_rf_valid;
end generate reg_rst_nen;
------------------------------------------------------------------------------
-- 32/64-bit logic
------------------------------------------------------------------------------
sixty_four_bit_gen : if VCP_ENABLE = SIXTY_FOUR_BIT generate
to_decode_sixty_four_bit_instruction <= (not from_decode_incomplete_instruction_signal) when
to_decode_instruction(6 downto 0) = VCP64_OP else
'0';
from_decode_incomplete_instruction_signal <= from_stage1_incomplete_instruction;
end generate sixty_four_bit_gen;
thirty_two_bit_gen : if VCP_ENABLE /= SIXTY_FOUR_BIT generate
to_decode_sixty_four_bit_instruction <= '0';
from_decode_incomplete_instruction_signal <= '0';
end generate thirty_two_bit_gen;
------------------------------------------------------------------------------
-- First stage
------------------------------------------------------------------------------
from_decode_ready <= to_stage1_ready or (not from_stage1_valid);
--Reread registers if stalled
rs1_select <=
to_decode_rs1_select when from_decode_ready = '1' and from_decode_incomplete_instruction_signal = '0' else
from_stage1_rs1_select;
rs2_select <=
to_decode_rs2_select when from_decode_ready = '1' and from_decode_incomplete_instruction_signal = '0' else
from_stage1_rs2_select;
rs3_select <=
to_decode_rs3_select when from_decode_ready = '1' and from_decode_incomplete_instruction_signal = '0' else
from_stage1_rs3_select;
process (clk) is
begin
if rising_edge(clk) then
if from_decode_ready = '1' then
from_stage1_instruction(from_stage1_instruction'left downto
from_stage1_instruction'left-31) <=
to_decode_instruction;
end if;
if from_decode_incomplete_instruction_signal = '1' then
if from_decode_ready = '1' and to_decode_valid = '1' then
from_stage1_incomplete_instruction <= '0';
from_stage1_valid <= '1';
end if;
else
if from_decode_ready = '1' then
from_stage1_incomplete_instruction <= to_decode_valid and
to_decode_sixty_four_bit_instruction;
from_stage1_program_counter <= to_decode_program_counter;
from_stage1_predicted_pc <= to_decode_predicted_pc;
from_stage1_instruction(to_decode_instruction'range) <= to_decode_instruction;
from_stage1_valid <= to_decode_valid and (not to_decode_sixty_four_bit_instruction);
end if;
end if;
if reset = '1' or quash_decode = '1' then
from_stage1_incomplete_instruction <= '0';
from_stage1_valid <= '0';
end if;
end if;
end process;
------------------------------------------------------------------------------
-- Second stage bypass (if one-stage)
------------------------------------------------------------------------------
one_cycle : if PIPELINE_STAGES = 1 generate
to_stage1_ready <= to_decode_ready;
decode_idle <= (not from_decode_valid_signal) and
(not from_decode_incomplete_instruction_signal);
from_decode_rs1_data <= rs1_data;
from_decode_rs2_data <= rs2_data;
from_decode_rs3_data <= rs3_data;
from_decode_sign_extension <=
std_logic_vector(resize(signed(from_stage1_instruction(from_stage1_instruction'left downto
from_stage1_instruction'left)),
SIGN_EXTENSION_SIZE));
from_decode_program_counter <= from_stage1_program_counter;
from_decode_predicted_pc <= from_stage1_predicted_pc;
from_decode_instruction_signal <= from_stage1_instruction;
from_decode_valid_signal <= from_stage1_valid;
from_decode_next_instruction <= to_decode_instruction;
from_decode_next_valid <= to_decode_valid;
end generate one_cycle;
------------------------------------------------------------------------------
-- Second stage (if two-stage)
------------------------------------------------------------------------------
two_cycle : if PIPELINE_STAGES = 2 generate
to_stage1_ready <= to_decode_ready or (not from_decode_valid_signal);
decode_idle <= (not from_stage1_valid) and
(not from_decode_valid_signal) and
(not from_decode_incomplete_instruction_signal);
process (clk) is
begin
if rising_edge(clk) then
if to_stage1_ready = '1' then
from_decode_rs1_data <= rs1_data;
from_decode_rs2_data <= rs2_data;
from_decode_rs3_data <= rs3_data;
from_decode_sign_extension <=
std_logic_vector(resize(signed(from_stage1_instruction(from_stage1_instruction'left downto
from_stage1_instruction'left)),
SIGN_EXTENSION_SIZE));
from_decode_program_counter <= from_stage1_program_counter;
from_decode_predicted_pc <= from_stage1_predicted_pc;
from_decode_instruction_signal <= from_stage1_instruction;
from_decode_valid_signal <= from_stage1_valid;
end if;
--Bypass registers already read out of register file
if to_rf_valid = '1' then
if to_stage1_ready = '1' then --Bypass registers just being read in
if to_rf_select = from_stage1_rs1_select then
from_decode_rs1_data <= to_rf_data;
end if;
if to_rf_select = from_stage1_rs2_select then
from_decode_rs2_data <= to_rf_data;
end if;
if to_rf_select = from_stage1_rs3_select then
from_decode_rs3_data <= to_rf_data;
end if;
else --Bypass data already read in
if to_rf_select = from_decode_rs1_select then
from_decode_rs1_data <= to_rf_data;
end if;
if to_rf_select = from_decode_rs2_select then
from_decode_rs2_data <= to_rf_data;
end if;
if to_rf_select = from_decode_rs3_select then
from_decode_rs3_data <= to_rf_data;
end if;
end if;
end if;
if reset = '1' or quash_decode = '1' then
from_decode_valid_signal <= '0';
end if;
end if;
end process;
from_decode_next_instruction <= from_stage1_instruction(from_decode_next_instruction'range);
from_decode_next_valid <= from_stage1_valid;
end generate two_cycle;
end architecture;
|
bsd-3-clause
|
VectorBlox/risc-v
|
ip/orca/hdl/vcp_handler.vhd
|
1
|
3415
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.std_logic_textio.all; -- I/O for logic types
library work;
use work.rv_components.all;
use work.utils.all;
use work.constants_pkg.all;
entity vcp_handler is
generic (
REGISTER_SIZE : positive range 32 to 32;
VCP_ENABLE : vcp_type
);
port (
clk : in std_logic;
reset : in std_logic;
instruction : in std_logic_vector(INSTRUCTION_SIZE(VCP_ENABLE)-1 downto 0);
to_vcp_valid : in std_logic;
vcp_select : in std_logic;
rs1_data : in std_logic_vector(REGISTER_SIZE-1 downto 0);
rs2_data : in std_logic_vector(REGISTER_SIZE-1 downto 0);
rs3_data : in std_logic_vector(REGISTER_SIZE-1 downto 0);
vcp_data0 : out std_logic_vector(REGISTER_SIZE-1 downto 0);
vcp_data1 : out std_logic_vector(REGISTER_SIZE-1 downto 0);
vcp_data2 : out std_logic_vector(REGISTER_SIZE-1 downto 0);
vcp_instruction : out std_logic_vector(40 downto 0);
vcp_valid_instr : out std_logic;
vcp_writeback_select : out std_logic
);
end entity vcp_handler;
architecture rtl of vcp_handler is
alias opcode : std_logic_vector(INSTR_OPCODE'length-1 downto 0) is instruction(INSTR_OPCODE'range);
signal dest_size : std_logic_vector(1 downto 0);
signal vcp64_instruction : boolean;
begin -- architecture rtl
--extended bits
dest_size <= instruction(31) & instruction(29);
vcp64_instruction <= opcode(2) = '1';
full_vcp_gen : if VCP_ENABLE = SIXTY_FOUR_BIT generate
vcp_instruction(40) <= instruction(40) when vcp64_instruction else '0'; --extra instruction
vcp_instruction(39) <= instruction(39) when vcp64_instruction else '0'; --masked
vcp_instruction(38) <= instruction(38) when vcp64_instruction else '1'; --bsign
vcp_instruction(37) <= instruction(37) when vcp64_instruction else '1'; --asign
vcp_instruction(36) <= instruction(36) when vcp64_instruction else '1'; --opsign
vcp_instruction(35 downto 34) <= instruction(35 downto 34) when vcp64_instruction else dest_size; --b size
vcp_instruction(33 downto 32) <= instruction(33 downto 32) when vcp64_instruction else dest_size; --a size
end generate full_vcp_gen;
light_vcp_gen : if VCP_ENABLE /= SIXTY_FOUR_BIT generate
vcp_instruction(40) <= '0'; --extra instruction
vcp_instruction(39) <= '0'; --masked
vcp_instruction(38) <= '1'; --bsign
vcp_instruction(37) <= '1'; --asign
vcp_instruction(36) <= '1'; --opsign
vcp_instruction(35 downto 34) <= dest_size; --b size
vcp_instruction(33 downto 32) <= dest_size; --a size
end generate light_vcp_gen;
vcp_instruction(31 downto 0) <= instruction(31 downto 0);
vcp_data0 <= rs1_data;
vcp_data1 <= rs2_data;
vcp_data2 <= rs3_data;
vcp_enabled_gen : if VCP_ENABLE /= DISABLED generate
vcp_valid_instr <= to_vcp_valid;
process (clk) is
begin
if rising_edge(clk) then
vcp_writeback_select <= vcp_select;
end if;
end process;
end generate vcp_enabled_gen;
vcp_disabled_gen : if VCP_ENABLE = DISABLED generate
vcp_valid_instr <= '0';
vcp_writeback_select <= '0';
end generate vcp_disabled_gen;
end architecture rtl;
|
bsd-3-clause
|
VectorBlox/risc-v
|
ip/orca/hdl/execute.vhd
|
1
|
27626
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.std_logic_textio.all; -- I/O for logic types
library work;
use work.rv_components.all;
use work.utils.all;
use work.constants_pkg.all;
library STD;
use STD.textio.all; -- basic I/O
entity execute is
generic (
REGISTER_SIZE : positive range 32 to 32;
SIGN_EXTENSION_SIZE : positive;
INTERRUPT_VECTOR : std_logic_vector(31 downto 0);
BTB_ENTRIES : natural;
POWER_OPTIMIZED : boolean;
MULTIPLY_ENABLE : boolean;
DIVIDE_ENABLE : boolean;
SHIFTER_MAX_CYCLES : positive range 1 to 32;
ENABLE_EXCEPTIONS : boolean;
ENABLE_EXT_INTERRUPTS : boolean;
NUM_EXT_INTERRUPTS : positive range 1 to 32;
VCP_ENABLE : vcp_type;
FAMILY : string;
AUX_MEMORY_REGIONS : natural range 0 to 4;
AMR0_ADDR_BASE : std_logic_vector(31 downto 0);
AMR0_ADDR_LAST : std_logic_vector(31 downto 0);
AMR0_READ_ONLY : boolean;
UC_MEMORY_REGIONS : natural range 0 to 4;
UMR0_ADDR_BASE : std_logic_vector(31 downto 0);
UMR0_ADDR_LAST : std_logic_vector(31 downto 0);
UMR0_READ_ONLY : boolean;
HAS_ICACHE : boolean;
HAS_DCACHE : boolean
);
port (
clk : in std_logic;
reset : in std_logic;
global_interrupts : in std_logic_vector(NUM_EXT_INTERRUPTS-1 downto 0);
program_counter : in unsigned(REGISTER_SIZE-1 downto 0);
core_idle : in std_logic;
memory_interface_idle : in std_logic;
to_execute_valid : in std_logic;
to_execute_program_counter : in unsigned(REGISTER_SIZE-1 downto 0);
to_execute_predicted_pc : in unsigned(REGISTER_SIZE-1 downto 0);
to_execute_instruction : in std_logic_vector(INSTRUCTION_SIZE(VCP_ENABLE)-1 downto 0);
to_execute_next_instruction : in std_logic_vector(31 downto 0);
to_execute_next_valid : in std_logic;
to_execute_rs1_data : in std_logic_vector(REGISTER_SIZE-1 downto 0);
to_execute_rs2_data : in std_logic_vector(REGISTER_SIZE-1 downto 0);
to_execute_rs3_data : in std_logic_vector(REGISTER_SIZE-1 downto 0);
to_execute_sign_extension : in std_logic_vector(SIGN_EXTENSION_SIZE-1 downto 0);
from_execute_ready : buffer std_logic;
--quash_execute input isn't needed as mispredicts have already resolved
execute_idle : out std_logic;
--To PC correction
to_pc_correction_data : out unsigned(REGISTER_SIZE-1 downto 0);
to_pc_correction_source_pc : out unsigned(REGISTER_SIZE-1 downto 0);
to_pc_correction_valid : buffer std_logic;
to_pc_correction_predictable : out std_logic;
from_pc_correction_ready : in std_logic;
--To register file
to_rf_select : buffer std_logic_vector(REGISTER_NAME_SIZE-1 downto 0);
to_rf_data : buffer std_logic_vector(REGISTER_SIZE-1 downto 0);
to_rf_valid : buffer std_logic;
--Data ORCA-internal memory-mapped master
lsu_oimm_address : buffer std_logic_vector(REGISTER_SIZE-1 downto 0);
lsu_oimm_byteenable : out std_logic_vector((REGISTER_SIZE/8)-1 downto 0);
lsu_oimm_requestvalid : buffer std_logic;
lsu_oimm_readnotwrite : buffer std_logic;
lsu_oimm_writedata : out std_logic_vector(REGISTER_SIZE-1 downto 0);
lsu_oimm_readdata : in std_logic_vector(REGISTER_SIZE-1 downto 0);
lsu_oimm_readdatavalid : in std_logic;
lsu_oimm_waitrequest : in std_logic;
--ICache control (Invalidate/flush/writeback)
from_icache_control_ready : in std_logic;
to_icache_control_valid : buffer std_logic;
to_icache_control_command : out cache_control_command;
--DCache control (Invalidate/flush/writeback)
from_dcache_control_ready : in std_logic;
to_dcache_control_valid : buffer std_logic;
to_dcache_control_command : out cache_control_command;
--Cache control common signals
to_cache_control_base : out std_logic_vector(REGISTER_SIZE-1 downto 0);
to_cache_control_last : out std_logic_vector(REGISTER_SIZE-1 downto 0);
--Auxiliary/Uncached memory regions
amr_base_addrs : out std_logic_vector((imax(AUX_MEMORY_REGIONS, 1)*REGISTER_SIZE)-1 downto 0);
amr_last_addrs : out std_logic_vector((imax(AUX_MEMORY_REGIONS, 1)*REGISTER_SIZE)-1 downto 0);
umr_base_addrs : out std_logic_vector((imax(UC_MEMORY_REGIONS, 1)*REGISTER_SIZE)-1 downto 0);
umr_last_addrs : out std_logic_vector((imax(UC_MEMORY_REGIONS, 1)*REGISTER_SIZE)-1 downto 0);
pause_ifetch : out std_logic;
--Timer signals
timer_value : in std_logic_vector(63 downto 0);
timer_interrupt : in std_logic;
--Vector coprocessor port
vcp_data0 : out std_logic_vector(REGISTER_SIZE-1 downto 0);
vcp_data1 : out std_logic_vector(REGISTER_SIZE-1 downto 0);
vcp_data2 : out std_logic_vector(REGISTER_SIZE-1 downto 0);
vcp_instruction : out std_logic_vector(40 downto 0);
vcp_valid_instr : out std_logic;
vcp_ready : in std_logic;
vcp_illegal : in std_logic;
vcp_writeback_data : in std_logic_vector(REGISTER_SIZE-1 downto 0);
vcp_writeback_en : in std_logic;
vcp_alu_data1 : in std_logic_vector(REGISTER_SIZE-1 downto 0);
vcp_alu_data2 : in std_logic_vector(REGISTER_SIZE-1 downto 0);
vcp_alu_source_valid : in std_logic;
vcp_alu_result : out std_logic_vector(REGISTER_SIZE-1 downto 0);
vcp_alu_result_valid : out std_logic
);
end entity execute;
architecture behavioural of execute is
constant INSTRUCTION32 : std_logic_vector(31 downto 0) := (others => '-');
alias opcode : std_logic_vector(6 downto 0) is to_execute_instruction(INSTR_OPCODE'range);
alias rd_select : std_logic_vector(REGISTER_NAME_SIZE-1 downto 0) is
to_execute_instruction(REGISTER_RD'range);
alias rs1_select : std_logic_vector(REGISTER_NAME_SIZE-1 downto 0) is
to_execute_instruction(REGISTER_RS1'range);
alias rs2_select : std_logic_vector(REGISTER_NAME_SIZE-1 downto 0) is
to_execute_instruction(REGISTER_RS2'range);
alias rs3_select : std_logic_vector(REGISTER_NAME_SIZE-1 downto 0) is
to_execute_instruction(REGISTER_RD'range);
signal use_after_produce_stall : std_logic;
signal to_rf_select_writeable : std_logic;
signal rs1_data : std_logic_vector(REGISTER_SIZE-1 downto 0);
signal rs2_data : std_logic_vector(REGISTER_SIZE-1 downto 0);
signal rs3_data : std_logic_vector(REGISTER_SIZE-1 downto 0);
alias next_rs1_select : std_logic_vector(REGISTER_NAME_SIZE-1 downto 0) is
to_execute_next_instruction(REGISTER_RS1'range);
alias next_rs2_select : std_logic_vector(REGISTER_NAME_SIZE-1 downto 0) is
to_execute_next_instruction(REGISTER_RS2'range);
alias next_rs3_select : std_logic_vector(REGISTER_NAME_SIZE-1 downto 0) is
to_execute_next_instruction(REGISTER_RD'range);
type fwd_mux_t is (ALU_FWD, NO_FWD);
signal rs1_mux : fwd_mux_t;
signal rs2_mux : fwd_mux_t;
signal rs3_mux : fwd_mux_t;
--Writeback data sources (VCP writes back through syscall)
signal alu_select : std_logic;
signal to_alu_valid : std_logic;
signal from_alu_ready : std_logic;
signal from_alu_illegal : std_logic;
signal from_alu_valid : std_logic;
signal from_alu_data : std_logic_vector(REGISTER_SIZE-1 downto 0);
signal branch_select : std_logic;
signal to_branch_valid : std_logic;
--signal from_branch_ready : std_logic; --Branch unit always ready
signal from_branch_illegal : std_logic;
signal from_branch_valid : std_logic;
signal from_branch_data : std_logic_vector(REGISTER_SIZE-1 downto 0);
signal lsu_select : std_logic;
signal to_lsu_valid : std_logic;
signal from_lsu_ready : std_logic;
signal from_lsu_illegal : std_logic;
signal from_lsu_misalign : std_logic;
signal from_lsu_valid : std_logic;
signal from_lsu_data : std_logic_vector(REGISTER_SIZE-1 downto 0);
signal syscall_select : std_logic;
signal to_syscall_valid : std_logic;
signal from_syscall_ready : std_logic;
signal from_syscall_illegal : std_logic;
signal from_syscall_valid : std_logic;
signal from_syscall_data : std_logic_vector(REGISTER_SIZE-1 downto 0);
signal vcp_select : std_logic;
signal to_vcp_valid : std_logic;
signal from_opcode_illegal : std_logic;
signal illegal_instruction : std_logic;
signal to_alu_rs1_data : std_logic_vector(REGISTER_SIZE-1 downto 0);
signal to_alu_rs2_data : std_logic_vector(REGISTER_SIZE-1 downto 0);
signal branch_to_pc_correction_valid : std_logic;
signal branch_to_pc_correction_data : unsigned(REGISTER_SIZE-1 downto 0);
signal writeback_stall_from_lsu : std_logic;
signal load_in_progress : std_logic;
signal lsu_idle : std_logic;
signal memory_idle : std_logic;
signal syscall_to_pc_correction_valid : std_logic;
signal syscall_to_pc_correction_data : unsigned(REGISTER_SIZE-1 downto 0);
signal from_writeback_ready : std_logic;
signal to_rf_mux : std_logic_vector(1 downto 0);
signal vcp_writeback_select : std_logic;
signal from_branch_misaligned : std_logic;
begin
--Decode instruction; could get pushed back to decode stage
process (opcode) is
begin
alu_select <= '0';
branch_select <= '0';
lsu_select <= '0';
syscall_select <= '0';
vcp_select <= '0';
from_opcode_illegal <= '0';
--Decode OPCODE to select submodule. All paths must decode to exactly one
--submodule.
--If ENABLE_EXCEPTIONS is false decode illegal instructions to ALU ops as
--the default way to handle.
case opcode is
when ALU_OP | ALUI_OP | LUI_OP | AUIPC_OP =>
alu_select <= '1';
when JAL_OP | JALR_OP | BRANCH_OP =>
branch_select <= '1';
when LOAD_OP | STORE_OP =>
lsu_select <= '1';
when SYSTEM_OP | MISC_MEM_OP =>
syscall_select <= '1';
when VCP32_OP =>
if VCP_ENABLE /= DISABLED then
vcp_select <= '1';
else
if ENABLE_EXCEPTIONS then
from_opcode_illegal <= '1';
else
alu_select <= '1';
end if;
end if;
when VCP64_OP =>
if VCP_ENABLE = SIXTY_FOUR_BIT then
vcp_select <= '1';
else
if ENABLE_EXCEPTIONS then
from_opcode_illegal <= '1';
else
alu_select <= '1';
end if;
end if;
when others =>
if ENABLE_EXCEPTIONS then
from_opcode_illegal <= '1';
else
alu_select <= '1';
end if;
end case;
end process;
--Currently only set valid/ready for execute when writeback is ready. This
--means that any instruction that completes in the execute cycle will be able to
--writeback without a stall; i.e. alu/branch/syscall instructions merely
--assert valid for once cycle and are done.
--Could be changed to have components hold their output if to_execute_ready
--was not true, which might slightly complicate logic but would allow some
--optimizations such as allowing a multicycle ALU op
--(multiply/shift/div/etc.) to start while waiting for a load to return.
to_alu_valid <= alu_select and to_execute_valid and from_writeback_ready;
to_branch_valid <= branch_select and to_execute_valid and from_writeback_ready;
to_lsu_valid <= lsu_select and to_execute_valid and from_writeback_ready;
to_syscall_valid <= syscall_select and to_execute_valid and from_writeback_ready;
to_vcp_valid <= vcp_select and to_execute_valid and from_writeback_ready;
from_execute_ready <= (not to_execute_valid) or (from_writeback_ready and
(((not lsu_select) or from_lsu_ready) and
((not alu_select) or from_alu_ready) and
((not syscall_select) or from_syscall_ready) and
((not vcp_select) or vcp_ready)));
illegal_instruction <= to_execute_valid and from_writeback_ready and (from_opcode_illegal or
(alu_select and from_alu_illegal) or
(branch_select and from_branch_illegal) or
(lsu_select and from_lsu_illegal) or
(syscall_select and from_syscall_illegal) or
(vcp_select and vcp_illegal));
-----------------------------------------------------------------------------
-- REGISTER FORWADING
-- Knowing the next instruction coming downt the pipeline, we can
-- generate the mux select bits for the next cycle.
-- there are several functional units that could generate a writeback. ALU,
-- JAL, Syscalls, load_store. the ALU forward directly to the next
-- instruction, The others stall the pipeline to wait for the registers to
-- propogate if the next instruction uses them.
--
-----------------------------------------------------------------------------
rs1_data <= from_alu_data when rs1_mux = ALU_FWD else
to_execute_rs1_data;
rs2_data <= from_alu_data when rs2_mux = ALU_FWD else
to_execute_rs2_data;
rs3_data <= from_alu_data when rs3_mux = ALU_FWD else
to_execute_rs3_data;
--No forward stall; system calls, loads, and branches aren't forwarded.
use_after_produce_stall <=
to_rf_select_writeable and (from_syscall_valid or load_in_progress or from_branch_valid) when
to_rf_select = rs1_select or to_rf_select = rs2_select or ((to_rf_select = rs3_select) and VCP_ENABLE /= DISABLED)
else '0';
--Calculate forwarding muxes for next instruction in advance in order to
--minimize execute cycle time.
process(clk)
begin
if rising_edge(clk) then
if from_writeback_ready = '1' then
rs1_mux <= NO_FWD;
rs2_mux <= NO_FWD;
rs3_mux <= NO_FWD;
end if;
if to_alu_valid = '1' and from_alu_ready = '1' then
if rd_select /= REGISTER_ZERO then
if rd_select = next_rs1_select then
rs1_mux <= ALU_FWD;
end if;
if rd_select = next_rs2_select then
rs2_mux <= ALU_FWD;
end if;
if rd_select = next_rs3_select then
rs3_mux <= ALU_FWD;
end if;
end if;
end if;
end if;
end process;
to_alu_rs1_data <= vcp_alu_data1 when vcp_select = '1' else
rs1_data;
to_alu_rs2_data <= vcp_alu_data2 when vcp_select = '1' else
rs2_data;
alu : arithmetic_unit
generic map (
REGISTER_SIZE => REGISTER_SIZE,
SIGN_EXTENSION_SIZE => SIGN_EXTENSION_SIZE,
POWER_OPTIMIZED => POWER_OPTIMIZED,
MULTIPLY_ENABLE => MULTIPLY_ENABLE,
DIVIDE_ENABLE => DIVIDE_ENABLE,
SHIFTER_MAX_CYCLES => SHIFTER_MAX_CYCLES,
ENABLE_EXCEPTIONS => ENABLE_EXCEPTIONS,
FAMILY => FAMILY
)
port map (
clk => clk,
to_alu_valid => to_alu_valid,
to_alu_rs1_data => to_alu_rs1_data,
to_alu_rs2_data => to_alu_rs2_data,
from_alu_ready => from_alu_ready,
from_alu_illegal => from_alu_illegal,
vcp_source_valid => vcp_alu_source_valid,
vcp_select => vcp_select,
from_execute_ready => from_execute_ready,
instruction => to_execute_instruction(INSTRUCTION32'range),
sign_extension => to_execute_sign_extension,
current_pc => to_execute_program_counter,
from_alu_data => from_alu_data,
from_alu_valid => from_alu_valid
);
branch : branch_unit
generic map (
REGISTER_SIZE => REGISTER_SIZE,
SIGN_EXTENSION_SIZE => SIGN_EXTENSION_SIZE,
BTB_ENTRIES => BTB_ENTRIES,
ENABLE_EXCEPTIONS => ENABLE_EXCEPTIONS
)
port map (
clk => clk,
reset => reset,
to_branch_valid => to_branch_valid,
from_branch_illegal => from_branch_illegal,
rs1_data => rs1_data,
rs2_data => rs2_data,
current_pc => to_execute_program_counter,
predicted_pc => to_execute_predicted_pc,
instruction => to_execute_instruction(INSTRUCTION32'range),
sign_extension => to_execute_sign_extension,
from_branch_valid => from_branch_valid,
from_branch_data => from_branch_data,
to_branch_ready => from_writeback_ready,
target_misaligned => from_branch_misaligned,
to_pc_correction_data => branch_to_pc_correction_data,
to_pc_correction_source_pc => to_pc_correction_source_pc,
to_pc_correction_valid => branch_to_pc_correction_valid,
from_pc_correction_ready => from_pc_correction_ready
);
ls_unit : load_store_unit
generic map (
REGISTER_SIZE => REGISTER_SIZE,
SIGN_EXTENSION_SIZE => SIGN_EXTENSION_SIZE,
ENABLE_EXCEPTIONS => ENABLE_EXCEPTIONS
)
port map (
clk => clk,
reset => reset,
lsu_idle => lsu_idle,
to_lsu_valid => to_lsu_valid,
from_lsu_illegal => from_lsu_illegal,
from_lsu_misalign => from_lsu_misalign,
rs1_data => rs1_data,
rs2_data => rs2_data,
instruction => to_execute_instruction(INSTRUCTION32'range),
sign_extension => to_execute_sign_extension,
load_in_progress => load_in_progress,
writeback_stall_from_lsu => writeback_stall_from_lsu,
lsu_ready => from_lsu_ready,
from_lsu_data => from_lsu_data,
from_lsu_valid => from_lsu_valid,
oimm_address => lsu_oimm_address,
oimm_byteenable => lsu_oimm_byteenable,
oimm_requestvalid => lsu_oimm_requestvalid,
oimm_readnotwrite => lsu_oimm_readnotwrite,
oimm_writedata => lsu_oimm_writedata,
oimm_readdata => lsu_oimm_readdata,
oimm_readdatavalid => lsu_oimm_readdatavalid,
oimm_waitrequest => lsu_oimm_waitrequest
);
memory_idle <= memory_interface_idle and lsu_idle;
syscall : sys_call
generic map (
REGISTER_SIZE => REGISTER_SIZE,
POWER_OPTIMIZED => POWER_OPTIMIZED,
INTERRUPT_VECTOR => INTERRUPT_VECTOR,
ENABLE_EXCEPTIONS => ENABLE_EXCEPTIONS,
ENABLE_EXT_INTERRUPTS => ENABLE_EXT_INTERRUPTS,
NUM_EXT_INTERRUPTS => NUM_EXT_INTERRUPTS,
VCP_ENABLE => VCP_ENABLE,
MULTIPLY_ENABLE => MULTIPLY_ENABLE,
AUX_MEMORY_REGIONS => AUX_MEMORY_REGIONS,
AMR0_ADDR_BASE => AMR0_ADDR_BASE,
AMR0_ADDR_LAST => AMR0_ADDR_LAST,
AMR0_READ_ONLY => AMR0_READ_ONLY,
UC_MEMORY_REGIONS => UC_MEMORY_REGIONS,
UMR0_ADDR_BASE => UMR0_ADDR_BASE,
UMR0_ADDR_LAST => UMR0_ADDR_LAST,
UMR0_READ_ONLY => UMR0_READ_ONLY,
HAS_ICACHE => HAS_ICACHE,
HAS_DCACHE => HAS_DCACHE
)
port map (
clk => clk,
reset => reset,
global_interrupts => global_interrupts,
core_idle => core_idle,
memory_idle => memory_idle,
program_counter => program_counter,
to_syscall_valid => to_syscall_valid,
from_syscall_illegal => from_syscall_illegal,
rs1_data => rs1_data,
rs2_data => rs2_data,
instruction => to_execute_instruction(INSTRUCTION32'range),
current_pc => to_execute_program_counter,
from_syscall_ready => from_syscall_ready,
from_branch_misaligned => from_branch_misaligned,
illegal_instruction => illegal_instruction,
from_lsu_addr_misalign => from_lsu_misalign,
from_lsu_address => lsu_oimm_address,
from_syscall_valid => from_syscall_valid,
from_syscall_data => from_syscall_data,
to_pc_correction_data => syscall_to_pc_correction_data,
to_pc_correction_valid => syscall_to_pc_correction_valid,
from_pc_correction_ready => from_pc_correction_ready,
from_icache_control_ready => from_icache_control_ready,
to_icache_control_valid => to_icache_control_valid,
to_icache_control_command => to_icache_control_command,
from_dcache_control_ready => from_dcache_control_ready,
to_dcache_control_valid => to_dcache_control_valid,
to_dcache_control_command => to_dcache_control_command,
to_cache_control_base => to_cache_control_base,
to_cache_control_last => to_cache_control_last,
amr_base_addrs => amr_base_addrs,
amr_last_addrs => amr_last_addrs,
umr_base_addrs => umr_base_addrs,
umr_last_addrs => umr_last_addrs,
pause_ifetch => pause_ifetch,
timer_value => timer_value,
timer_interrupt => timer_interrupt,
vcp_writeback_data => vcp_writeback_data,
vcp_writeback_en => vcp_writeback_en
);
vcp_port : vcp_handler
generic map (
REGISTER_SIZE => REGISTER_SIZE,
VCP_ENABLE => VCP_ENABLE
)
port map (
clk => clk,
reset => reset,
instruction => to_execute_instruction,
to_vcp_valid => to_vcp_valid,
vcp_select => vcp_select,
rs1_data => rs1_data,
rs2_data => rs2_data,
rs3_data => rs3_data,
vcp_data0 => vcp_data0,
vcp_data1 => vcp_data1,
vcp_data2 => vcp_data2,
vcp_instruction => vcp_instruction,
vcp_valid_instr => vcp_valid_instr,
vcp_writeback_select => vcp_writeback_select
);
vcp_alu_result_valid <= from_alu_valid;
vcp_alu_result <= from_alu_data;
------------------------------------------------------------------------------
-- PC correction (branch mispredict, interrupt, etc.)
------------------------------------------------------------------------------
to_pc_correction_data <= syscall_to_pc_correction_data when syscall_to_pc_correction_valid = '1' else
branch_to_pc_correction_data;
to_pc_correction_valid <= syscall_to_pc_correction_valid or branch_to_pc_correction_valid;
--Don't put syscalls in the BTB as they have side effects and must flush the
--pipeline anyway.
to_pc_correction_predictable <= not syscall_to_pc_correction_valid;
--Intuitively execute_idle is lsu_idle and alu_idle and branch_idle etc. for
--all the functional units. In practice the idle signal is only needed for
--interrupts, and it's fine to take an interrupt as long as the branch and
--syscall units have finished updating the PC and we're not waiting on a
--load. Even though for instance the ALU may have some internal state, since
--the execute unit is serialized it won't assert ready back to the decode
--unit until it has finished the instruction.
--Also note intuitively we'd want a writeback_idle signal as interrupts can
--be taken before writeback has occurred; however since there's no
--backpressure from writeback we can always guarantee that the writeback will
--occur before the interrupt handler decodes an instruction and reads a
--register.
execute_idle <= lsu_idle and (not to_pc_correction_valid);
------------------------------------------------------------------------------
-- Writeback
------------------------------------------------------------------------------
from_writeback_ready <= (not use_after_produce_stall) and (not writeback_stall_from_lsu);
process(clk)
begin
if rising_edge(clk) then
if from_writeback_ready = '1' then
to_rf_select <= rd_select;
if rd_select = REGISTER_ZERO then
to_rf_select_writeable <= '0';
else
to_rf_select_writeable <= '1';
end if;
end if;
end if;
end process;
to_rf_mux <= "00" when from_syscall_valid = '1' else
"01" when load_in_progress = '1' else
"10" when from_branch_valid = '1' else
"11";
with to_rf_mux select
to_rf_data <=
from_syscall_data when "00",
from_lsu_data when "01",
from_branch_data when "10",
from_alu_data when others;
to_rf_valid <= to_rf_select_writeable and (from_syscall_valid or
from_lsu_valid or
from_branch_valid or
(from_alu_valid and (not vcp_writeback_select)));
-------------------------------------------------------------------------------
-- Simulation assertions and debug
-------------------------------------------------------------------------------
--pragma translate_off
process(clk)
begin
if rising_edge(clk) then
if reset = '0' then
assert (bool_to_int(from_syscall_valid) +
bool_to_int(from_lsu_valid) +
bool_to_int(from_branch_valid) +
bool_to_int(from_alu_valid)) <= 1 report "Multiple Data Enables Asserted" severity failure;
end if;
end if;
end process;
my_print : process(clk)
variable my_line : line; -- type 'line' comes from textio
variable last_valid_pc : unsigned(REGISTER_SIZE-1 downto 0);
type register_list is array(0 to 31) of std_logic_vector(REGISTER_SIZE-1 downto 0);
variable shadow_registers : register_list := (others => (others => '0'));
constant DEBUG_WRITEBACK : boolean := false;
begin
if rising_edge(clk) then
if to_rf_valid = '1' and DEBUG_WRITEBACK then
write(my_line, string'("WRITEBACK: PC = "));
hwrite(my_line, std_logic_vector(last_valid_pc));
shadow_registers(to_integer(unsigned(to_rf_select))) := to_rf_data;
write(my_line, string'(" REGISTERS = {"));
for i in shadow_registers'range loop
hwrite(my_line, shadow_registers(i));
if i /= shadow_registers'right then
write(my_line, string'(","));
end if;
end loop; -- i
write(my_line, string'("}"));
writeline(output, my_line);
end if;
if to_execute_valid = '1' then
write(my_line, string'("executing pc = ")); -- formatting
hwrite(my_line, (std_logic_vector(to_execute_program_counter))); -- format type std_logic_vector as hex
write(my_line, string'(" instr = ")); -- formatting
if opcode = VCP64_OP then
hwrite(my_line, (to_execute_instruction)); -- format type std_logic_vector as hex
else
hwrite(my_line, (to_execute_instruction(31 downto 0))); -- format type std_logic_vector as hex
end if;
if from_execute_ready = '0' then
write(my_line, string'(" stalling")); -- formatting
else
last_valid_pc := to_execute_program_counter;
end if;
writeline(output, my_line); -- write to "output"
else
--write(my_line, string'("bubble")); -- formatting
--writeline(output, my_line); -- write to "output"
end if;
end if;
end process my_print;
--pragma translate_on
end architecture;
|
bsd-3-clause
|
VectorBlox/risc-v
|
ip/orca/hdl/a4l_master.vhd
|
1
|
4489
|
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.rv_components.all;
entity a4l_master is
generic (
ADDRESS_WIDTH : positive;
DATA_WIDTH : positive;
MAX_OUTSTANDING_REQUESTS : natural
);
port (
clk : in std_logic;
reset : in std_logic;
aresetn : in std_logic;
master_idle : out std_logic;
--ORCA-internal memory-mapped slave
oimm_address : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
oimm_byteenable : in std_logic_vector((DATA_WIDTH/8)-1 downto 0);
oimm_requestvalid : in std_logic;
oimm_readnotwrite : in std_logic;
oimm_writedata : in std_logic_vector(DATA_WIDTH-1 downto 0);
oimm_readdata : out std_logic_vector(DATA_WIDTH-1 downto 0);
oimm_readdatavalid : out std_logic;
oimm_waitrequest : out std_logic;
--AXI4-Lite memory-mapped master
AWADDR : out std_logic_vector(ADDRESS_WIDTH-1 downto 0);
AWPROT : out std_logic_vector(2 downto 0);
AWVALID : out std_logic;
AWREADY : in std_logic;
WSTRB : out std_logic_vector((DATA_WIDTH/8)-1 downto 0);
WVALID : out std_logic;
WDATA : out std_logic_vector(DATA_WIDTH-1 downto 0);
WREADY : in std_logic;
BRESP : in std_logic_vector(1 downto 0);
BVALID : in std_logic;
BREADY : out std_logic;
ARADDR : out std_logic_vector(ADDRESS_WIDTH-1 downto 0);
ARPROT : out std_logic_vector(2 downto 0);
ARVALID : out std_logic;
ARREADY : in std_logic;
RDATA : in std_logic_vector(DATA_WIDTH-1 downto 0);
RRESP : in std_logic_vector(1 downto 0);
RVALID : in std_logic;
RREADY : out std_logic
);
end entity a4l_master;
architecture rtl of a4l_master is
constant PROT_VAL : std_logic_vector(2 downto 0) := "000";
signal throttler_idle : std_logic;
signal unthrottled_oimm_readcomplete : std_logic;
signal unthrottled_oimm_writecomplete : std_logic;
signal unthrottled_oimm_waitrequest : std_logic;
signal throttled_oimm_requestvalid : std_logic;
signal AWVALID_signal : std_logic;
signal WVALID_signal : std_logic;
signal aw_sent : std_logic;
signal w_sent : std_logic;
begin
master_idle <= throttler_idle;
request_throttler : oimm_throttler
generic map (
MAX_OUTSTANDING_REQUESTS => MAX_OUTSTANDING_REQUESTS,
READ_WRITE_FENCE => true --AXI lacks intra-channel ordering
)
port map (
clk => clk,
reset => reset,
throttler_idle => throttler_idle,
--ORCA-internal memory-mapped slave
slave_oimm_requestvalid => oimm_requestvalid,
slave_oimm_readnotwrite => oimm_readnotwrite,
slave_oimm_writelast => '1',
slave_oimm_waitrequest => oimm_waitrequest,
--ORCA-internal memory-mapped master
master_oimm_requestvalid => throttled_oimm_requestvalid,
master_oimm_readcomplete => unthrottled_oimm_readcomplete,
master_oimm_writecomplete => unthrottled_oimm_writecomplete,
master_oimm_waitrequest => unthrottled_oimm_waitrequest
);
unthrottled_oimm_readcomplete <= RVALID;
unthrottled_oimm_writecomplete <= BVALID;
AWVALID <= AWVALID_signal;
WVALID <= WVALID_signal;
oimm_readdata <= RDATA;
oimm_readdatavalid <= RVALID;
unthrottled_oimm_waitrequest <= (not ARREADY) when oimm_readnotwrite = '1' else
(((not AWREADY) and (not aw_sent)) or ((not WREADY) and (not w_sent)));
AWADDR <= oimm_address;
AWPROT <= PROT_VAL;
AWVALID_signal <= ((not oimm_readnotwrite) and throttled_oimm_requestvalid) and (not aw_sent);
WSTRB <= oimm_byteenable;
WVALID_signal <= ((not oimm_readnotwrite) and throttled_oimm_requestvalid) and (not w_sent);
WDATA <= oimm_writedata;
BREADY <= '1';
ARADDR <= oimm_address;
ARPROT <= PROT_VAL;
ARVALID <= oimm_readnotwrite and throttled_oimm_requestvalid;
RREADY <= '1';
process (clk) is
begin
if rising_edge(clk) then
if AWVALID_signal = '1' and AWREADY = '1' then
aw_sent <= '1';
end if;
if WVALID_signal = '1' and WREADY = '1' then
w_sent <= '1';
end if;
if unthrottled_oimm_waitrequest = '0' then
aw_sent <= '0';
w_sent <= '0';
end if;
if aresetn = '0' then
aw_sent <= '0';
w_sent <= '0';
end if;
end if;
end process;
end architecture;
|
bsd-3-clause
|
alvieboy/xtc-base
|
uart_mv_filter.vhd
|
1
|
2412
|
--
-- UART for ZPUINO - Majority voting filter
--
-- Copyright 2011 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity uart_mv_filter is
generic (
bits: natural;
threshold: natural
);
port (
clk: in std_logic;
rst: in std_logic;
sin: in std_logic;
sout: out std_logic;
clear: in std_logic;
enable: in std_logic
);
end entity uart_mv_filter;
architecture behave of uart_mv_filter is
signal count_q: unsigned(bits-1 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
if rst='1' then
count_q <= (others => '0');
sout <= '0';
else
if clear='1' then
count_q <= (others => '0');
sout <= '0';
else
if enable='1' then
if sin='1' then
count_q <= count_q + 1;
end if;
end if;
if (count_q >= threshold) then
sout<='1';
end if;
end if;
end if;
end if;
end process;
end behave;
|
bsd-3-clause
|
alvieboy/xtc-base
|
uart_pty_tx.vhd
|
1
|
2061
|
library IEEE;
use IEEE.std_logic_1164.all;
use work.pty.all;
use ieee.std_logic_arith.all;
use IEEE.numeric_std.all;
entity uart_pty_tx is
port(
clk: in std_logic;
rst: in std_logic;
tx: out std_logic
);
end entity uart_pty_tx;
architecture sim of uart_pty_tx is
component TxUnit is
port (
clk_i : in std_logic; -- Clock signal
reset_i : in std_logic; -- Reset input
enable_i : in std_logic; -- Enable input
load_i : in std_logic; -- Load input
txd_o : out std_logic; -- RS-232 data output
busy_o : out std_logic; -- Tx Busy
datai_i : in std_logic_vector(7 downto 0)); -- Byte to transmit
end component TxUnit;
component uart_brgen is
port (
clk: in std_logic;
rst: in std_logic;
en: in std_logic;
count: in std_logic_vector(15 downto 0);
clkout: out std_logic
);
end component uart_brgen;
signal rxclk,txclk: std_logic;
signal load_data: std_logic;
signal busy: std_logic;
signal data: std_logic_vector(7 downto 0);
begin
rxclkgen: uart_brgen
port map (
clk => clk,
rst => rst,
en => '1',
count => x"0005", -- 1Mbps
clkout => rxclk
);
txclkgen: uart_brgen
port map (
clk => clk,
rst => rst,
en => rxclk,
count => x"000f",
clkout => txclk
);
txu: TxUnit
port map (
clk_i => clk,
reset_i => rst,
enable_i => txclk,
load_i => load_data,
txd_o => tx,
busy_o => busy,
datai_i => data
);
process(clk)
begin
if rising_edge(clk) then
if rst='1' then
load_data<='1';
else
load_data<='0';
if busy='0' then
if pty_available > 0 then
data <= conv_std_logic_vector(pty_receive,8);
load_data<='1';
end if;
end if;
end if;
end if;
end process;
process
variable c: integer;
begin
c := pty_initialize;
wait;
end process;
end sim;
|
bsd-3-clause
|
alvieboy/xtc-base
|
xtc.vhd
|
1
|
15615
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.xtcpkg.all;
use work.wishbonepkg.all;
-- synthesis translate_off
use work.txt_util.all;
-- synthesis translate_on
entity xtc is
port (
wb_syscon: in wb_syscon_type;
-- Master wishbone interface
wbo: out wb_mosi_type;
wbi: in wb_miso_type;
-- ROM wb interface
romwbo: out wb_mosi_type;
romwbi: in wb_miso_type;
nmi: in std_logic;
nmiack: out std_logic;
break: out std_logic;
intack: out std_logic;
rstreq: out std_logic;
edbg: in memory_debug_type
);
end xtc;
architecture behave of xtc is
signal fuo: fetch_output_type;
signal duo: decode_output_type;
signal fduo: fetchdata_output_type;
signal euo: execute_output_type;
signal muo: memory_output_type;
signal rbw1_addr: regaddress_type;
signal rbw1_wr: std_logic_vector(31 downto 0);
signal rbw1_we: std_logic;
signal rbw1_en: std_logic;
signal rbw2_addr: regaddress_type;
signal rbw2_wr: std_logic_vector(31 downto 0);
signal rbw2_we: std_logic := '0';
signal rbw2_en: std_logic := '0';
signal rb1_addr: regaddress_type;
signal rb1_en: std_logic;
signal rb1_rd: std_logic_vector(31 downto 0);
signal rb2_addr: regaddress_type;
signal rb2_en: std_logic;
signal rb2_rd: std_logic_vector(31 downto 0);
signal jumpaddr: word_type;
signal cache_valid: std_logic;
signal dcache_flush: std_logic;
signal dcache_inflush: std_logic;
signal icache_flush: std_logic;
signal icache_abort: std_logic;
signal cache_data: std_logic_vector(31 downto 0);
signal cache_address: std_logic_vector(31 downto 0);
signal cache_strobe: std_logic;
signal cache_enable: std_logic;
signal cache_stall: std_logic;
signal cache_seq: std_logic;
signal cache_nseq: std_logic;
signal decode_freeze: std_logic;
signal w_en: std_logic;
signal w_addr: regaddress_type;
signal memory_busy: std_logic;
signal execute_busy: std_logic;
signal wb_busy: std_logic;
signal refetch: std_logic;
signal dual: std_logic;
signal allvalid: std_logic;
signal notallvalid: std_logic;
signal e_busy: std_logic;
--signal refetch_registers: std_logic;
signal freeze_decoder: std_logic;
signal executed: boolean;
component tracer is
port (
clk: in std_logic;
dbgi: in execute_debug_type
);
end component tracer;
signal dbg: execute_debug_type;
signal mdbg: memory_debug_type;
signal cifo: copifo;
signal cifi: copifi;
signal co: copo_a;
signal ci: copi_a;
signal mwbi: wb_miso_type;
signal mwbo: wb_mosi_type;
signal immu_tlbw: std_logic:='0';
signal immu_tlbv: tlb_entry_type;
signal immu_tlba: std_logic_vector(2 downto 0):="000";
signal immu_context: std_logic_vector(5 downto 0):=(others => '0');
signal immu_paddr: std_logic_vector(31 downto 0);
signal immu_valid: std_logic;
signal immu_enabled: std_logic:='1';
signal cache_tag: std_logic_vector(31 downto 0);
signal dcache_accesstype: std_logic_vector(1 downto 0);
signal flushfd: std_logic;
signal clrhold: std_logic;
signal internalfault: std_logic;
signal pipeline_internalfault: std_logic;
signal busycnt: unsigned (31 downto 0);
signal proten: std_logic;
signal protw: std_logic_vector(31 downto 0);
signal rstreq_i: std_logic;
signal fflags: std_logic_vector(31 downto 0);
signal intin: std_logic_vector(31 downto 0);
signal trappc: std_logic_vector(31 downto 0);
signal trapaddr: std_logic_vector(31 downto 0);
signal trapbase: std_logic_vector(31 downto 0);
signal istrap: std_logic;
begin
process(wb_syscon.clk)
begin
if rising_edge(wb_syscon.clk) then
if pipeline_internalfault='1' then
fflags(0) <= execute_busy;
fflags(1) <= notallvalid;
fflags(2) <= freeze_decoder;
fflags(3) <= wb_busy;
fflags(4) <= memory_busy;
fflags(5) <= dbg.hold;
fflags(6) <= dbg.multvalid;
fflags(7) <= dbg.trap;
end if;
end if;
end process;
rstreq_i<= pipeline_internalfault ;
rstreq <= rstreq_i;
-- synthesis translate_off
trc: tracer
port map (
clk => wb_syscon.clk,
dbgi => dbg
);
-- synthesis translate_on
-- Register bank.
rbe: entity work.regbank_3p
generic map (
ADDRESS_BITS => 5,
ZEROSIZE => 4
)
port map (
clk => wb_syscon.clk,
rb1_en => rb1_en,
rb1_addr=> rb1_addr,
rb1_rd => rb1_rd,
rb2_en => rb2_en,
rb2_addr=> rb2_addr,
rb2_rd => rb2_rd,
rb3_en => rbw1_en,
rb3_we => rbw1_we,
rb3_addr=> rbw1_addr,
rb3_wr => rbw1_wr
);
cache: if INSTRUCTION_CACHE generate
cache: entity work.icache
generic map (
ADDRESS_HIGH => 31
)
port map (
syscon => wb_syscon,
valid => cache_valid,
data => cache_data,
address => cache_address,
strobe => cache_strobe,
stall => cache_stall,
enable => cache_enable,
flush => icache_flush,
abort => icache_abort,
seq => cache_seq,
tag => cache_tag,
tagen => immu_enabled,
mwbi => romwbi,
mwbo => romwbo
);
mmub: if MMU_ENABLED generate
cache_tag <= immu_paddr;
immuinst: entity work.mmu
port map (
clk => wb_syscon.clk,
rst => wb_syscon.rst,
addr => cache_address,
ctx => immu_context,
en => cache_strobe,
tlbw => immu_tlbw,
tlba => immu_tlba,
tlbv => immu_tlbv,
paddr => immu_paddr,
valid => immu_valid,
pw => open,
pr => open,
px => open,
ps => open
);
end generate;
end generate;
--romwbo.we<='0';
nocache: if not INSTRUCTION_CACHE generate
-- Hack... we need to provide a solution for ACK being held low
-- when no pipelined transaction exists
-- For now, the romram is hacked to do it.
--nopipe: if not EXTRA_PIPELINE generate
cache_valid <= romwbi.ack;
cache_data <= romwbi.dat;
romwbo.adr <= cache_address;
romwbo.stb <= cache_strobe;
romwbo.cyc <= cache_enable;
cache_stall <= romwbi.stall;
--end generate;
end generate;
fetch_unit: entity work.fetch
port map (
clk => wb_syscon.clk,
rst => wb_syscon.rst,
-- Connection to ROM
stall => cache_stall,
valid => cache_valid,
address => cache_address,
read => cache_data,
enable => cache_enable,
strobe => cache_strobe,
abort => icache_abort,
seq => cache_seq,
nseq => cache_nseq,
freeze => decode_freeze,
jump => euo.jump,
jumppriv => euo.jumppriv,
jumpaddr => euo.r.jumpaddr,
dual => dual,
-- Outputs for next stages
fuo => fuo
);
decode_unit: entity work.decode
port map (
clk => wb_syscon.clk,
rst => wb_syscon.rst,
-- Input from fetch unit
fui => fuo,
-- Outputs for next stages
duo => duo,
busy => decode_freeze,
freeze => freeze_decoder,
dual => dual,
flush => euo.jump, -- DELAY SLOT when fetchdata is passthrough
jump => euo.jump,
jumpmsb => euo.r.jumpaddr(1)
);
freeze_decoder <= execute_busy or notallvalid;
flushfd <= euo.jump or euo.trap;
fetchdata_unit: entity work.fetchdata
port map (
clk => wb_syscon.clk,
rst => wb_syscon.rst,
r1_en => rb1_en,
r1_addr => rb1_addr,
r1_read => rb1_rd,
r2_en => rb2_en,
r2_addr => rb2_addr,
r2_read => rb2_rd,
freeze => execute_busy,
flush => flushfd,-- euo.jump, -- DELAY SLOT
refetch => notallvalid, --refetch_registers,--execute_busy,-- TEST TEST: was refetch,
w_addr => w_addr,
w_en => w_en,
executed => executed,
clrhold => euo.clrhold,
-- Input from decode unit
dui => duo,
-- Outputs for next stages
fduo => fduo
);
busycheck: block
signal dirtyReg: regaddress_type;
signal dirty: std_logic;
signal v1,v2,v3: std_logic;
signal isBlocking: std_logic;
signal canProceed: std_logic;
begin
v1 <= '0' when dirty='1' and rb1_en='1' and rb1_addr=dirtyReg else '1';
v2 <= '0' when dirty='1' and rb2_en='1' and rb2_addr=dirtyReg else '1';
v3 <= '0' when dirty='1' and w_en='1' and w_addr=dirtyReg else '1';
isBlocking <= '1' when duo.r.valid='1' and ( duo.r.blocks='1' )
and execute_busy='0' and euo.jump='0'
and allvalid='1' and euo.trap='0'
else '0';
process(wb_syscon.clk)
begin
if rising_edge(wb_syscon.clk) then
if wb_syscon.rst='1' then
dirty <= '0';
dirtyReg <= (others => '0'); -- X
else
if isBlocking='1' and dirty='0' then -- and duo.r.sra2/="0000"
dirty <= '1';
dirtyReg <= duo.r.sra2;
end if;
-- Memory reads clear flags.
if muo.mregwe='1' and dirty='1' then
-- TODO here: why not use only the memory wb, rather than all wb ?
if (dirtyReg=muo.mreg) then
dirty <= '0';
dirtyReg <= (others => 'X');
--if (dirtyReg /= muo.mreg) then
-- report "Omg.. clearing reg " &hstr(muo.mreg) & ", but dirty register is "&hstr(dirtyReg) severity failure;
end if;
end if;
if muo.fault='1' then
dirty <= '0';
end if;
end if;
end if;
end process;
canProceed <= '0' when (dirty='1' and duo.r.valid='1' and duo.r.blocks='1') else '1';
allvalid <= v1 and v2 and v3 and canProceed;
notallvalid <= not allvalid;
end block;
execute_busy <= e_busy;
executed <= euo.executed;
execute_unit: entity work.execute
port map (
clk => wb_syscon.clk,
rst => wb_syscon.rst,
busy => e_busy,
mem_busy => memory_busy,
wb_busy => wb_busy,
refetch => refetch,
int => wbi.int,
nmi => nmi,
nmiack => nmiack,
intline => x"00",
-- Input from fetchdata unit
fdui => fduo,
-- Outputs for next stages
euo => euo,
-- Input from memory unit (spr update)
mui => muo,
-- COP
co => cifo,
ci => cifi,
-- Trap
trappc => trappc,
istrap => istrap,
trapbase => trapbase,
-- Debug
dbgo => dbg
);
-- MMU cop
copmmuinst: entity work.cop_mmu
port map (
clk => wb_syscon.clk,
rst => wb_syscon.rst,
tlbw => immu_tlbw,
tlba => immu_tlba,
tlbv => immu_tlbv,
mmuen => immu_enabled,
proten => proten,
protw => protw,
dbgi => dbg,
mdbgi => mdbg,--edbg,
fflags => fflags,
ci => ci(1),
co => co(1)
);
coparbinst: entity work.cop_arb
port map (
clk => wb_syscon.clk,
rst => wb_syscon.rst,
cfi => cifo,
cfo => cifi,
ci => co,
co => ci
);
-- MMU cop
copsysinst: entity work.cop_sys
port map (
clk => wb_syscon.clk,
rst => wb_syscon.rst,
icache_flush => icache_flush,
dcache_flush => dcache_flush,
dcache_inflush => dcache_inflush,
int_in => x"00000000",
trappc => trappc,
trapaddr => trapaddr,
istrap => istrap,
trapbase => trapbase,
--intacken => '0',
ci => ci(0),
co => co(0)
);
dcachegen: if DATA_CACHE generate
dcache_accesstype <= ACCESS_NOCACHE when mwbo.adr(31)='1' else
ACCESS_WT;
dcacheinst: entity work.dcache
generic map (
ADDRESS_HIGH => 31,
CACHE_MAX_BITS => 13, -- 8 Kb
CACHE_LINE_SIZE_BITS => 6 -- 64 bytes
)
port map (
syscon => wb_syscon,
ci.data => mwbo.dat,
ci.address => mwbo.adr,
ci.strobe => mwbo.stb,
ci.we => mwbo.we,
ci.wmask => mwbo.sel,
ci.enable => mwbo.cyc,
ci.tag => mwbo.tag,
ci.flush => dcache_flush,
ci.accesstype => dcache_accesstype,
co.in_flush => dcache_inflush,
co.data => mwbi.dat,
co.stall => mwbi.stall,
co.valid => mwbi.ack,
co.tag => mwbi.tag,
co.err => mwbi.err,
mwbi => wbi,
mwbo => wbo
);
end generate;
nodcache: if not DATA_CACHE generate
wbo<=mwbo;
mwbi<=wbi;
end generate;
memory_unit: entity work.memory
port map (
clk => wb_syscon.clk,
rst => wb_syscon.rst,
-- Memory interface
wb_ack_i => mwbi.ack,
wb_err_i => mwbi.err,
wb_dat_i => mwbi.dat,
wb_dat_o => mwbo.dat,
wb_adr_o => mwbo.adr,
wb_cyc_o => mwbo.cyc,
wb_stb_o => mwbo.stb,
wb_sel_o => mwbo.sel,
wb_tag_o => mwbo.tag,
wb_tag_i => mwbi.tag,
wb_we_o => mwbo.we,
wb_stall_i => mwbi.stall,
dbgo => mdbg,
refetch => refetch,
busy => memory_busy,
proten => proten,
protw => protw,
-- Input for previous stages
eui => euo,
-- Output for next stages
muo => muo
);
writeback_unit: entity work.writeback
port map (
clk => wb_syscon.clk,
rst => wb_syscon.rst,
busy => wb_busy,
r0_en => rbw1_en,
r0_we => rbw1_we,
r0_addr => rbw1_addr,
r0_write => rbw1_wr,
r1_en => rbw2_en,
r1_we => rbw2_we,
r1_addr => rbw2_addr,
r1_write => rbw2_wr,
--r_read => rbw_rd,
-- Input from previous stage
mui => muo,
eui => euo -- for fast register write
);
faultcheck: if FAULTCHECKS generate
-- Internal pipeline fault...
process(wb_syscon.clk)
begin
if rising_edge(wb_syscon.clk) then
if wb_syscon.rst='1' then
busycnt<=(others =>'0');
else
if execute_busy='1' or notallvalid='1' or freeze_decoder='1' then
busycnt<=busycnt+1;
else
busycnt<=(others =>'0');
end if;
end if;
end if;
end process;
pipeline_internalfault<='1' when busycnt > 65535 else '0';
end generate;
nofaultchecks: if not FAULTCHECKS generate
pipeline_internalfault<='0';
end generate;
-- synthesis translate_off
process
begin
wait on muo.internalfault;
if muo.internalfault'event and muo.internalfault='1' then
wait until rising_edge(wb_syscon.clk);
wait until rising_edge(wb_syscon.clk);
report "Internal memory fault" severity failure;
end if;
end process;
-- synthesis translate_on
end behave;
|
bsd-3-clause
|
Shadytel/Computer
|
Emulator/FPGA/ALU.vhd
|
1
|
2917
|
----------------------------------------------------------------------------------
-- Company: Lake Union Bell
-- Engineer: Nick Burrows
--
-- Create Date: 19:03:40 09/24/2011
-- Design Name:
-- Module Name: ALU - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ALU is
Port (
En: in STD_LOGIC;
LM: in STD_LOGIC; --Logical operation mode
A : in STD_LOGIC_VECTOR (11 downto 0);
B : in STD_LOGIC_VECTOR (11 downto 0);
Func: in STD_LOGIC_VECTOR (3 downto 0);
Output : out STD_LOGIC_VECTOR (11 downto 0)
);
end ALU;
architecture Behavioral of ALU is
begin
process (En, A, B, Func, LM)
begin
if(En = '1') then
if(LM = '0') then
if(Func = "0000") then
Output <= (A) + (B);
elsif(Func = "0001") then
Output <= (A) - (B);
elsif(Func = "0010") then
Output <= (B) - (A);
elsif(Func = "0011") then
Output <= (B) - 1;
elsif(Func = "0100") then
Output <= (B) + 1;
elsif(Func = "0101") then
Output <= 0 - (B);
elsif(Func = "0110") then
if((A) < (B)) then
Output(0) <= '1';
else
Output(0) <= '0';
end if;
elsif(Func = "0111") then
if((A) < (B)) then
Output(0) <= '1';
else
Output(0) <= '0';
end if;
else
Output <= "ZZZZZZZZZZZZ";
end if;
else
if(Func = "0000") then
Output <= not B;
elsif(Func = "0001") then
Output <= A nor B;
elsif(Func = "0010") then
Output <= (not B) and A;
elsif(Func = "0011") then
Output <= "000000000000";
elsif(Func = "0100") then
Output <= B nand A;
elsif(Func = "0101") then
Output <= not A;
elsif(Func = "0110") then
Output <= B xor A;
elsif(Func = "0111") then
Output <= B and (not A);
elsif(Func = "1000") then
Output <= (not B) or A;
elsif(Func = "1001") then
Output <= B xnor A;
elsif(Func = "1010") then
Output <= A;
elsif(Func = "1011") then
Output <= B and A;
elsif(Func = "1100") then
Output <= "000000000001";
elsif(Func = "1101") then
Output <= B or (not A);
elsif(Func = "1110") then
Output <= B or A;
elsif(Func = "1111") then
if(B = 0) then
Output(0) <= '1';
else
Output(0) <= '0';
end if;
end if;
end if;
else
Output <= "ZZZZZZZZZZZZ";
end if;
end process;
end Behavioral;
|
bsd-3-clause
|
alvieboy/xtc-base
|
alu_a.vhd
|
1
|
4245
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.xtcpkg.all;
entity alu is
port (
clk: in std_logic;
rst: in std_logic;
a: in unsigned(31 downto 0);
b: in unsigned(31 downto 0);
o: out unsigned(31 downto 0);
y: out unsigned(31 downto 0);
op: in alu_op_type;
en: in std_logic;
ci: in std_logic;
cen: in std_logic; -- Carry enable
busy: out std_logic;
valid: out std_logic;
co: out std_logic;
zero: out std_logic;
ovf: out std_logic;
sign: out std_logic
);
end entity;
architecture behave of alu is
signal alu_a, alu_b, alu_r: unsigned(32 downto 0);
signal alu_add_r, alu_sub_r: unsigned(32 downto 0);
signal carryext: unsigned (32 downto 0);
signal modify_flags: boolean;
component mult is
port (
clk: in std_logic;
rst: in std_logic;
lhs: in signed(31 downto 0);
rhs: in signed(31 downto 0);
en: in std_logic;
m: out signed(31 downto 0);
y: out signed(31 downto 0);
valid: out std_logic; -- Multiplication valid
comp: out std_logic -- Computing
);
end component;
component shifter is
port (
a: in unsigned(31 downto 0);
b: in unsigned(4 downto 0);
o: out unsigned(31 downto 0);
left: in std_logic;
arith:in std_logic
);
end component;
signal mult_en: std_logic;
signal mult_a: signed(31 downto 0);
signal mult_b: signed(31 downto 0);
signal mult_r: signed(31 downto 0);
signal mult_y: signed(31 downto 0);
signal mult_busy: std_logic;
signal mult_valid: std_logic;
signal shift_arith: std_logic;
signal shift_out: unsigned(31 downto 0);
signal shift_left: std_logic;
begin
mulen: if MULT_ENABLED generate
valid <= mult_valid;
multiplier: mult
port map (
clk => clk,
rst => rst,
lhs => mult_a,
rhs => mult_b,
en => mult_en,
m => mult_r,
y => mult_y,
valid => mult_valid,
comp => mult_busy
);
end generate;
muldis: if not MULT_ENABLED generate
mult_r <= (others => 'X');
mult_y <= (others => 'X');
mult_valid <= '0';
mult_busy <= '0';
end generate;
shifter_inst: shifter
port map (
a => alu_a(31 downto 0),
b => alu_b(4 downto 0),
o => shift_out,
left => shift_left,
arith => shift_arith
);
busy <= mult_busy;
alu_a <= '0' & a;
alu_b <= '0' & b;
mult_a <= signed(a);
mult_b <= signed(b);
carryext(32 downto 1) <= (others => '0');
carryext(0) <= ci when cen='1' else '0';--op=ALU_ADDC or op=ALU_SUBB else '0';
alu_add_r <= alu_a + alu_b + carryext;
alu_sub_r <= alu_a - alu_b - carryext;
mult_en <= '1' when op=ALU_MUL and en='1' else '0';
process(alu_add_r, carryext, alu_a, alu_b, alu_sub_r, op, mult_valid, mult_r,shift_out,mult_y)
begin
shift_left <= 'X';
shift_arith <= 'X';
case op is
when ALU_ADD => -- | ALU_ADDRI |ALU_ADDC =>
alu_r <= alu_add_r;
when ALU_SUB => --| ALU_CMP | ALU_SUBB =>
alu_r <= alu_sub_r;
when ALU_AND => alu_r <= alu_a and alu_b;
when ALU_OR => alu_r <= alu_a or alu_b;
--when ALU_NOT => alu_r <= not alu_a;
when ALU_XOR => alu_r <= alu_a xor alu_b;
when ALU_SEXTB => alu_r(7 downto 0) <= alu_a(7 downto 0);
alu_r(32 downto 8) <= (others => alu_a(7));
when ALU_SEXTS => alu_r(15 downto 0) <= alu_a(15 downto 0);
alu_r(32 downto 16) <= (others => alu_a(15));
when ALU_SHL =>
shift_arith<='X';
shift_left<='1';
alu_r <= 'X' & shift_out;
when ALU_SRA =>
shift_arith<='1';
shift_left<='0';
alu_r <= 'X' & shift_out;
when ALU_SRL =>
shift_arith<='0';
shift_left<='0';
alu_r <= 'X' & shift_out;
when ALU_MUL =>
alu_r <= mult_y(31) & unsigned(mult_r);
when others => alu_r <= (others =>'X');
end case;
-- if mult_valid='1' then
-- alu_r <= mult_y(31) & unsigned(mult_r);
-- end if;
end process;
y <= unsigned(mult_y);
o <= alu_r(31 downto 0);
co <= alu_sub_r(32);
sign <= alu_sub_r(31);
zero <= '1' when alu_sub_r(31 downto 0)=x"00000000" else '0';
end behave;
|
bsd-3-clause
|
alvieboy/xtc-base
|
insnqueue.vhd
|
1
|
2773
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity insnqueue is
port (
rst: in std_logic;
clkw: in std_logic;
din: in std_logic_vector(15 downto 0);
en: in std_logic;
clr: in std_logic;
full: out std_logic;
clkr: in std_logic;
pop: in std_logic;
dualpop: in std_logic;
dout0: out std_logic_vector(15 downto 0);
dout1: out std_logic_vector(15 downto 0);
empty: out std_logic;
dvalid: out std_logic
);
end entity;
architecture behave of insnqueue is
constant QUEUESIZE: integer := 8;
signal rdptr, wrptr, rdptrplus: integer range 0 to QUEUESIZE-1;
subtype insntype is std_logic_vector(15 downto 0);
type queuetype is array(0 to QUEUESIZE-1) of insntype;
signal qq: queuetype;
signal dvalid_int: std_logic;
begin
-- process(clkr)
-- begin
-- if rising_edge(clkr) then
process(rdptr,rdptrplus,qq)
begin
dout0 <= qq(rdptr);
dout1 <= qq(rdptrplus);
end process;
-- end if;
-- end process;
empty <= '1' when rdptr=wrptr else '0';
process(rdptr,wrptr)
begin
full <= '0';
if wrptr=QUEUESIZE-1 then
if rdptr=0 then
full <= '1';
end if;
else
if rdptr-wrptr=1 then
full<='1';
end if;
end if;
dvalid_int <= '0';
-- Now, how many items ?
if rdptr>wrptr then
dvalid_int <= '1';
elsif rdptr<wrptr then
if wrptr-rdptr>1 then
dvalid_int<='1';
end if;
end if;
end process;
process(rdptr)
begin
if rdptr=QUEUESIZE-1 then
rdptrplus <= 0;
else
rdptrplus <= rdptr+1;
end if;
end process;
process(clkw)
begin
if rising_edge(clkw) then
if rst='1' then
wrptr <= 0;
else
if clr='1' then
wrptr<=rdptr;
else
if en='1' then
qq(wrptr)<=din;
if wrptr=QUEUESIZE-1 then
wrptr<=0;
else
wrptr<=wrptr+1;
end if;
end if;
end if;
end if;
end if;
end process;
process(clkr)
begin
if rising_edge(clkr) then
if rst='1' then
rdptr<=0;
dvalid<='0';
else
if pop='1' then
if dualpop='0' then
if rdptr=QUEUESIZE-1 then
rdptr<=0;
else
rdptr<=rdptr+1;
end if;
else
if rdptr=QUEUESIZE-1 then
rdptr<=1;
elsif rdptr=QUEUESIZE-2 then
rdptr<=0;
else
rdptr<=rdptr+2;
end if;
end if;
end if;
dvalid <= dvalid_int;
end if;
end if;
end process;
end behave;
|
bsd-3-clause
|
alvieboy/xtc-base
|
wb_master_np_to_slave_p.vhd
|
1
|
2049
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
entity wb_master_np_to_slave_p is
generic (
ADDRESS_HIGH: integer := 31;
ADDRESS_LOW: integer := 0
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master signals
m_wb_dat_o: out std_logic_vector(31 downto 0);
m_wb_dat_i: in std_logic_vector(31 downto 0);
m_wb_adr_i: in std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
m_wb_sel_i: in std_logic_vector(3 downto 0);
m_wb_cti_i: in std_logic_vector(2 downto 0);
m_wb_we_i: in std_logic;
m_wb_cyc_i: in std_logic;
m_wb_stb_i: in std_logic;
m_wb_ack_o: out std_logic;
-- Slave signals
s_wb_dat_i: in std_logic_vector(31 downto 0);
s_wb_dat_o: out std_logic_vector(31 downto 0);
s_wb_adr_o: out std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
s_wb_sel_o: out std_logic_vector(3 downto 0);
s_wb_cti_o: out std_logic_vector(2 downto 0);
s_wb_we_o: out std_logic;
s_wb_cyc_o: out std_logic;
s_wb_stb_o: out std_logic;
s_wb_ack_i: in std_logic;
s_wb_stall_i: in std_logic
);
end entity wb_master_np_to_slave_p;
architecture behave of wb_master_np_to_slave_p is
type state_type is ( idle, wait_for_ack );
signal state: state_type;
begin
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
state <= idle;
else
case state is
when idle =>
if m_wb_cyc_i='1' and m_wb_stb_i='1' and s_wb_stall_i='0' then
state <= wait_for_ack;
end if;
when wait_for_ack =>
if s_wb_ack_i='1' then
state <= idle;
end if;
when others =>
end case;
end if;
end if;
end process;
s_wb_stb_o <= m_wb_stb_i when state=idle else '0';
s_wb_dat_o <= m_wb_dat_i;
s_wb_adr_o <= m_wb_adr_i;
s_wb_sel_o <= m_wb_sel_i;
s_wb_cti_o <= m_wb_cti_i;
s_wb_we_o <= m_wb_we_i;
s_wb_cyc_o <= m_wb_cyc_i;
m_wb_dat_o <= s_wb_dat_i;
m_wb_ack_o <= s_wb_ack_i;
end behave;
|
bsd-3-clause
|
alvieboy/xtc-base
|
xtc_ioctrl.vhd
|
1
|
2197
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.wishbonepkg.all;
use work.xtcpkg.all;
entity xtc_ioctrl is
port (
syscon: in wb_syscon_type;
wbi: in wb_mosi_type;
wbo: out wb_miso_type;
-- Slaves
swbi: in slot_wbi;
swbo: out slot_wbo;
sids: in slot_ids
);
end entity xtc_ioctrl;
architecture behave of xtc_ioctrl is
signal selector: std_logic_vector(15 downto 0);
signal selnum: integer range 0 to 15;
signal ackint: std_logic := '0';
signal trans_valid: std_logic := '1';
signal tagi: std_logic_vector(31 downto 0);
begin
process(wbi.adr)
variable num: integer range 0 to 15;
begin
num := to_integer(unsigned(wbi.adr(30 downto 28)));
selector<=(others => '0');
selector(num)<='1';
selnum<=num;
end process;
direct: if not IO_REGISTER_INPUTS generate
wbo.dat <= swbi(selnum).dat;
ackint <= swbi(selnum).ack;
wbo.err <= swbi(selnum).err;
wbo.tag <= tagi;
end generate;
indirect: if IO_REGISTER_INPUTS generate
trans_valid<='1' when ackint='0' else '0';
process(syscon.clk)
begin
if rising_edge(syscon.clk) then
if syscon.rst='1' then
wbo.dat <= (others => 'X');
ackint <= '0';
wbo.err <= '0';
wbo.tag <= (others => 'X');
else
wbo.dat <= swbi(selnum).dat;
ackint <= swbi(selnum).ack;
wbo.err <= swbi(selnum).err;
wbo.tag <= tagi;
end if;
end if;
end process;
end generate;
wbo.stall <= '0';
wbo.ack <= ackint;
-- Simple tag generator. Also resynchronizer
process(syscon.clk)
begin
if rising_edge(syscon.clk) then
--if syscon.rst='1' then
-- wbo.tag <= (others => '0');
--else
tagi <= wbi.tag;
--end if;
end if;
end process;
slavegen: for i in 0 to 15 generate
swbo(i).adr <= wbi.adr;
swbo(i).dat <= wbi.dat;
swbo(i).we <= wbi.we;
--swbo(i).tag <= wbi.tag;
swbo(i).cyc <= wbi.cyc and selector(i) and trans_valid;
swbo(i).stb <= wbi.stb and selector(i) and trans_valid;
end generate;
end behave;
|
bsd-3-clause
|
alvieboy/xtc-base
|
uart.vhd
|
1
|
7925
|
--
-- UART for Newcpu
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.wishbonepkg.all;
entity uart is
generic (
bits: integer := 11
);
port (
syscon: in wb_syscon_type;
wbi: in wb_mosi_type;
wbo: out wb_miso_type;
tx: out std_logic;
rx: in std_logic
);
end entity uart;
architecture behave of uart is
component uart_rx is
port (
clk: in std_logic;
rst: in std_logic;
rx: in std_logic;
rxclk: in std_logic;
read: in std_logic;
data: out std_logic_vector(7 downto 0);
data_av: out std_logic
);
end component uart_rx;
component TxUnit is
port (
clk_i : in std_logic; -- Clock signal
reset_i : in std_logic; -- Reset input
enable_i : in std_logic; -- Enable input
load_i : in std_logic; -- Load input
txd_o : out std_logic; -- RS-232 data output
busy_o : out std_logic; -- Tx Busy
intx_o : out std_logic; -- Tx in progress
datai_i : in std_logic_vector(7 downto 0)); -- Byte to transmit
end component TxUnit;
component uart_brgen is
port (
clk: in std_logic;
rst: in std_logic;
en: in std_logic;
count: in std_logic_vector(15 downto 0);
clkout: out std_logic
);
end component uart_brgen;
component fifo is
generic (
bits: integer := 11
);
port (
clk: in std_logic;
rst: in std_logic;
wr: in std_logic;
rd: in std_logic;
write: in std_logic_vector(7 downto 0);
read : out std_logic_vector(7 downto 0);
full: out std_logic;
empty: out std_logic
);
end component fifo;
signal uart_read: std_logic;
signal uart_write: std_logic;
signal divider_tx: std_logic_vector(15 downto 0) := x"000f";
signal divider_rx_q: std_logic_vector(15 downto 0);
signal data_ready: std_logic;
signal received_data: std_logic_vector(7 downto 0);
signal fifo_data: std_logic_vector(7 downto 0);
signal uart_busy: std_logic;
signal uart_intx: std_logic;
signal fifo_empty: std_logic;
signal rx_br: std_logic;
signal tx_br: std_logic;
signal rx_en: std_logic;
signal dready_q: std_logic;
signal data_ready_dly_q: std_logic;
signal fifo_rd: std_logic;
signal enabled_q: std_logic;
signal do_interrupt: std_logic;
signal int_enabled: std_logic;
signal ack: std_logic;
signal tsc: unsigned(31 downto 0);
signal millis: unsigned(31 downto 0);
constant FREQKHZ: integer := 96000; -- TODO
signal milliscount: integer range 0 to FREQKHZ-1;
begin
--enabled <= enabled_q;
wbo.int<= do_interrupt;
wbo.ack <= ack;
wbo.err <= '0';
rx_inst: uart_rx
port map(
clk => syscon.clk,
rst => syscon.rst,
rxclk => rx_br,
read => uart_read,
rx => rx,
data_av => data_ready,
data => received_data
);
uart_read <= dready_q;
tx_core: TxUnit
port map(
clk_i => syscon.clk,
reset_i => syscon.rst,
enable_i => tx_br,
load_i => uart_write,
txd_o => tx,
busy_o => uart_busy,
intx_o => uart_intx,
datai_i => wbi.dat(7 downto 0)
);
-- TODO: check multiple writes
-- Rx timing
rx_timer: uart_brgen
port map(
clk => syscon.clk,
rst => syscon.rst,
en => '1',
clkout => rx_br,
count => divider_rx_q
);
-- Tx timing
tx_timer: uart_brgen
port map(
clk => syscon.clk,
rst => syscon.rst,
en => rx_br,
clkout => tx_br,
count => divider_tx
);
process(syscon.clk)
begin
if rising_edge(syscon.clk) then
if syscon.rst='1' then
dready_q<='0';
data_ready_dly_q<='0';
else
data_ready_dly_q<=data_ready;
if data_ready='1' and data_ready_dly_q='0' then
dready_q<='1';
else
dready_q<='0';
end if;
end if;
end if;
end process;
fifo_instance: fifo
generic map (
bits => bits
)
port map (
clk => syscon.clk,
rst => syscon.rst,
wr => dready_q,
rd => fifo_rd,
write => received_data,
read => fifo_data,
full => open,
empty => fifo_empty
);
fifo_rd<='1' when wbi.adr(3 downto 2)="00" and (wbi.cyc='1' and wbi.stb='1' and wbi.we='0') else '0';
process(syscon.clk)--wb_adr_i, received_data, uart_busy, data_ready, fifo_empty, fifo_data,uart_intx, int_enabled)
begin
if rising_edge(syscon.clk) then
case wbi.adr(3 downto 2) is
when "01" =>
wbo.dat <= (others => '0');
wbo.dat(0) <= not fifo_empty;
wbo.dat(1) <= uart_busy;
wbo.dat(2) <= uart_intx;
wbo.dat(3) <= int_enabled;
when "00" =>
wbo.dat <= (others => '0');
wbo.dat(7 downto 0) <= fifo_data;
when "11" =>
wbo.dat <= std_logic_vector(tsc);
when "10" =>
wbo.dat <= std_logic_vector(millis);
when others =>
wbo.dat <= (others => 'X');
end case;
end if;
end process;
process(syscon.clk)
begin
if rising_edge(syscon.clk) then
if syscon.rst='1' then
tsc <= (others => '0');
milliscount<=FREQKHZ-1;
else
if milliscount=0 then
milliscount<=FREQKHZ-1;
tsc<=tsc+1;
else
milliscount<=milliscount-1;
end if;
end if;
end if;
end process;
process(syscon.clk)
begin
if rising_edge(syscon.clk) then
if syscon.rst='1' then
enabled_q<='0';
int_enabled <= '0';
do_interrupt<='0';
ack<='0';
else
ack <='0';
uart_write<='0';
if wbi.cyc='1' and wbi.stb='1' and ack='0' then
ack <= '1';
if wbi.we='1' then
case wbi.adr(3 downto 2) is
when "00" =>
uart_write <= '1';
when "01" =>
divider_rx_q <= wbi.dat(15 downto 0);
enabled_q <= wbi.dat(16);
when "10" =>
int_enabled <= wbi.dat(0);
do_interrupt <= '0';
when others =>
null;
end case;
end if;
else
if int_enabled='1' and fifo_empty='0' then
do_interrupt <= '1';
int_enabled <= '0';
end if;
end if;
end if;
end if;
end process;
end behave;
|
bsd-3-clause
|
richard42/CoCo3FPGA
|
T65_ALU.vhd
|
1
|
7783
|
-- ****
-- T65(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 300 Bugfixes by ehenciak added
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- 6502 compatible microprocessor core
--
-- Version : 0245
--
-- Copyright (c) 2002 Daniel Wallner ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t65/
--
-- Limitations :
--
-- File history :
--
-- 0245 : First version
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.T65_Pack.all;
entity T65_ALU is
port(
Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65816
Op : in std_logic_vector(3 downto 0);
BusA : in std_logic_vector(7 downto 0);
BusB : in std_logic_vector(7 downto 0);
P_In : in std_logic_vector(7 downto 0);
P_Out : out std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0)
);
end T65_ALU;
architecture rtl of T65_ALU is
-- AddSub variables (temporary signals)
signal ADC_Z : std_logic;
signal ADC_C : std_logic;
signal ADC_V : std_logic;
signal ADC_N : std_logic;
signal ADC_Q : std_logic_vector(7 downto 0);
signal SBC_Z : std_logic;
signal SBC_C : std_logic;
signal SBC_V : std_logic;
signal SBC_N : std_logic;
signal SBC_Q : std_logic_vector(7 downto 0);
begin
process (P_In, BusA, BusB)
variable AL : unsigned(6 downto 0);
variable AH : unsigned(6 downto 0);
variable C : std_logic;
begin
AL := resize(unsigned(BusA(3 downto 0) & P_In(Flag_C)), 7) + resize(unsigned(BusB(3 downto 0) & "1"), 7);
AH := resize(unsigned(BusA(7 downto 4) & AL(5)), 7) + resize(unsigned(BusB(7 downto 4) & "1"), 7);
-- pragma translate_off
if is_x(std_logic_vector(AL)) then AL := "0000000"; end if;
if is_x(std_logic_vector(AH)) then AH := "0000000"; end if;
-- pragma translate_on
if AL(4 downto 1) = 0 and AH(4 downto 1) = 0 then
ADC_Z <= '1';
else
ADC_Z <= '0';
end if;
if AL(5 downto 1) > 9 and P_In(Flag_D) = '1' then
AL(6 downto 1) := AL(6 downto 1) + 6;
end if;
C := AL(6) or AL(5);
AH := resize(unsigned(BusA(7 downto 4) & C), 7) + resize(unsigned(BusB(7 downto 4) & "1"), 7);
ADC_N <= AH(4);
ADC_V <= (AH(4) xor BusA(7)) and not (BusA(7) xor BusB(7));
-- pragma translate_off
if is_x(std_logic_vector(AH)) then AH := "0000000"; end if;
-- pragma translate_on
if AH(5 downto 1) > 9 and P_In(Flag_D) = '1' then
AH(6 downto 1) := AH(6 downto 1) + 6;
end if;
ADC_C <= AH(6) or AH(5);
ADC_Q <= std_logic_vector(AH(4 downto 1) & AL(4 downto 1));
end process;
process (Op, P_In, BusA, BusB)
variable AL : unsigned(6 downto 0);
variable AH : unsigned(5 downto 0);
variable C : std_logic;
begin
C := P_In(Flag_C) or not Op(0);
AL := resize(unsigned(BusA(3 downto 0) & C), 7) - resize(unsigned(BusB(3 downto 0) & "1"), 6);
AH := resize(unsigned(BusA(7 downto 4) & "0"), 6) - resize(unsigned(BusB(7 downto 4) & AL(5)), 6);
-- pragma translate_off
if is_x(std_logic_vector(AL)) then AL := "0000000"; end if;
if is_x(std_logic_vector(AH)) then AH := "000000"; end if;
-- pragma translate_on
if AL(4 downto 1) = 0 and AH(4 downto 1) = 0 then
SBC_Z <= '1';
else
SBC_Z <= '0';
end if;
SBC_C <= not AH(5);
SBC_V <= (AH(4) xor BusA(7)) and (BusA(7) xor BusB(7));
SBC_N <= AH(4);
if P_In(Flag_D) = '1' then
if AL(5) = '1' then
AL(5 downto 1) := AL(5 downto 1) - 6;
end if;
AH := resize(unsigned(BusA(7 downto 4) & "0"), 6) - resize(unsigned(BusB(7 downto 4) & AL(6)), 6);
if AH(5) = '1' then
AH(5 downto 1) := AH(5 downto 1) - 6;
end if;
end if;
SBC_Q <= std_logic_vector(AH(4 downto 1) & AL(4 downto 1));
end process;
process (Op, P_In, BusA, BusB,
ADC_Z, ADC_C, ADC_V, ADC_N, ADC_Q,
SBC_Z, SBC_C, SBC_V, SBC_N, SBC_Q)
variable Q_t : std_logic_vector(7 downto 0);
begin
-- ORA, AND, EOR, ADC, NOP, LD, CMP, SBC
-- ASL, ROL, LSR, ROR, BIT, LD, DEC, INC
P_Out <= P_In;
Q_t := BusA;
case Op(3 downto 0) is
when "0000" =>
-- ORA
Q_t := BusA or BusB;
when "0001" =>
-- AND
Q_t := BusA and BusB;
when "0010" =>
-- EOR
Q_t := BusA xor BusB;
when "0011" =>
-- ADC
P_Out(Flag_V) <= ADC_V;
P_Out(Flag_C) <= ADC_C;
Q_t := ADC_Q;
when "0101" | "1101" =>
-- LDA
when "0110" =>
-- CMP
P_Out(Flag_C) <= SBC_C;
when "0111" =>
-- SBC
P_Out(Flag_V) <= SBC_V;
P_Out(Flag_C) <= SBC_C;
Q_t := SBC_Q;
when "1000" =>
-- ASL
Q_t := BusA(6 downto 0) & "0";
P_Out(Flag_C) <= BusA(7);
when "1001" =>
-- ROL
Q_t := BusA(6 downto 0) & P_In(Flag_C);
P_Out(Flag_C) <= BusA(7);
when "1010" =>
-- LSR
Q_t := "0" & BusA(7 downto 1);
P_Out(Flag_C) <= BusA(0);
when "1011" =>
-- ROR
Q_t := P_In(Flag_C) & BusA(7 downto 1);
P_Out(Flag_C) <= BusA(0);
when "1100" =>
-- BIT
P_Out(Flag_V) <= BusB(6);
when "1110" =>
-- DEC
Q_t := std_logic_vector(unsigned(BusA) - 1);
when "1111" =>
-- INC
Q_t := std_logic_vector(unsigned(BusA) + 1);
when others =>
end case;
case Op(3 downto 0) is
when "0011" =>
P_Out(Flag_N) <= ADC_N;
P_Out(Flag_Z) <= ADC_Z;
when "0110" | "0111" =>
P_Out(Flag_N) <= SBC_N;
P_Out(Flag_Z) <= SBC_Z;
when "0100" =>
when "1100" =>
P_Out(Flag_N) <= BusB(7);
if (BusA and BusB) = "00000000" then
P_Out(Flag_Z) <= '1';
else
P_Out(Flag_Z) <= '0';
end if;
when others =>
P_Out(Flag_N) <= Q_t(7);
if Q_t = "00000000" then
P_Out(Flag_Z) <= '1';
else
P_Out(Flag_Z) <= '0';
end if;
end case;
Q <= Q_t;
end process;
end;
|
bsd-3-clause
|
cathalmccabe/PYNQ
|
boards/ip/rgb2dvi_v1_2/src/OutputSERDES.vhd
|
11
|
8366
|
-------------------------------------------------------------------------------
--
-- File: OutputSERDES.vhd
-- Author: Elod Gyorgy, Mihaita Nagy
-- Original Project: HDMI output on 7-series Xilinx FPGA
-- Date: 28 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module instantiates the Xilinx 7-series primitives necessary for
-- serializing the TMDS data stream.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity OutputSERDES is
Generic (
kParallelWidth : natural := 10); -- number of parallel bits
Port (
PixelClk : in STD_LOGIC; --TMDS clock x1 (CLKDIV)
SerialClk : in STD_LOGIC; --TMDS clock x5 (CLK)
--Encoded serial data
sDataOut_p : out STD_LOGIC;
sDataOut_n : out STD_LOGIC;
--Encoded parallel data (raw)
pDataOut : in STD_LOGIC_VECTOR (kParallelWidth-1 downto 0);
aRst : in STD_LOGIC);
end OutputSERDES;
architecture Behavioral of OutputSERDES is
signal sDataOut, ocascade1, ocascade2 : std_logic;
signal pDataOut_q : std_logic_vector(13 downto 0);
begin
-- Differential output buffer for TMDS I/O standard
OutputBuffer: OBUFDS
generic map (
IOSTANDARD => "TMDS_33")
port map (
O => sDataOut_p,
OB => sDataOut_n,
I => sDataOut);
-- Serializer, 10:1 (5:1 DDR), master-slave cascaded
SerializerMaster: OSERDESE2
generic map (
DATA_RATE_OQ => "DDR",
DATA_RATE_TQ => "SDR",
DATA_WIDTH => kParallelWidth,
TRISTATE_WIDTH => 1,
TBYTE_CTL => "FALSE",
TBYTE_SRC => "FALSE",
SERDES_MODE => "MASTER")
port map (
OFB => open, -- 1-bit output: Feedback path for data
OQ => sDataOut, -- 1-bit output: Data path output
-- SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)
SHIFTOUT1 => open,
SHIFTOUT2 => open,
TBYTEOUT => open, -- 1-bit output: Byte group tristate
TFB => open, -- 1-bit output: 3-state control
TQ => open, -- 1-bit output: 3-state control
CLK => SerialClk, -- 1-bit input: High speed clock
CLKDIV => PixelClk, -- 1-bit input: Divided clock
-- D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each)
D1 => pDataOut_q(13),
D2 => pDataOut_q(12),
D3 => pDataOut_q(11),
D4 => pDataOut_q(10),
D5 => pDataOut_q(9),
D6 => pDataOut_q(8),
D7 => pDataOut_q(7),
D8 => pDataOut_q(6),
OCE => '1', -- 1-bit input: Output data clock enable
RST => aRst, -- 1-bit input: Reset
-- SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)
SHIFTIN1 => ocascade1,
SHIFTIN2 => ocascade2,
-- T1 - T4: 1-bit (each) input: Parallel 3-state inputs
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TBYTEIN => '0', -- 1-bit input: Byte group tristate
TCE => '0' -- 1-bit input: 3-state clock enable
);
SerializerSlave: OSERDESE2
generic map (
DATA_RATE_OQ => "DDR",
DATA_RATE_TQ => "SDR",
DATA_WIDTH => kParallelWidth,
TRISTATE_WIDTH => 1,
TBYTE_CTL => "FALSE",
TBYTE_SRC => "FALSE",
SERDES_MODE => "SLAVE")
port map (
OFB => open, -- 1-bit output: Feedback path for data
OQ => open, -- 1-bit output: Data path output
-- SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)
SHIFTOUT1 => ocascade1,
SHIFTOUT2 => ocascade2,
TBYTEOUT => open, -- 1-bit output: Byte group tristate
TFB => open, -- 1-bit output: 3-state control
TQ => open, -- 1-bit output: 3-state control
CLK => SerialClk, -- 1-bit input: High speed clock
CLKDIV => PixelClk, -- 1-bit input: Divided clock
-- D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each)
D1 => '0',
D2 => '0',
D3 => pDataOut_q(5),
D4 => pDataOut_q(4),
D5 => pDataOut_q(3),
D6 => pDataOut_q(2),
D7 => pDataOut_q(1),
D8 => pDataOut_q(0),
OCE => '1', -- 1-bit input: Output data clock enable
RST => aRst, -- 1-bit input: Reset
-- SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)
SHIFTIN1 => '0',
SHIFTIN2 => '0',
-- T1 - T4: 1-bit (each) input: Parallel 3-state inputs
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TBYTEIN => '0', -- 1-bit input: Byte group tristate
TCE => '0' -- 1-bit input: 3-state clock enable
);
-------------------------------------------------------------
-- Concatenate the serdes inputs together. Keep the timesliced
-- bits together, and placing the earliest bits on the right
-- ie, if data comes in 0, 1, 2, 3, 4, 5, 6, 7, ...
-- the output will be 3210, 7654, ...
-------------------------------------------------------------
SliceOSERDES_q: for slice_count in 0 to kParallelWidth-1 generate begin
--DVI sends least significant bit first
--OSERDESE2 sends D1 bit first
pDataOut_q(14-slice_count-1) <= pDataOut(slice_count);
end generate SliceOSERDES_q;
end Behavioral;
|
bsd-3-clause
|
cathalmccabe/PYNQ
|
boards/ip/dvi2rgb_v1_7/src/ChannelBond.vhd
|
15
|
6809
|
-------------------------------------------------------------------------------
--
-- File: ChannelBond.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 8 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module de-skews data channels relative to each other. TMDS specs
-- allow 0.2 Tcharacter + 1.78ns skew between channels. To re-align the
-- channels all are buffered in FIFOs until a special marker (the beginning
-- of a blanking period) is found on all the channels.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.DVI_Constants.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ChannelBond is
Port (
PixelClk : in std_logic;
pDataInRaw : in std_logic_vector(9 downto 0);
pMeVld : in std_logic;
pOtherChVld : in std_logic_vector(1 downto 0);
pOtherChRdy : in std_logic_vector(1 downto 0);
pDataInBnd : out std_logic_vector(9 downto 0);
pMeRdy : out std_logic
);
end ChannelBond;
architecture Behavioral of ChannelBond is
constant kFIFO_Depth : natural := 32;
type FIFO_t is array (0 to kFIFO_Depth-1) of std_logic_vector(9 downto 0);
signal pFIFO : FIFO_t;
signal pDataFIFO : std_logic_vector(9 downto 0);
signal pRdA, pWrA : natural range 0 to kFIFO_Depth-1;
signal pRdEn : std_logic;
signal pAllVld, pAllVld_q, pMeRdy_int: std_logic;
signal pBlnkBgnFlag, pTokenFlag, pTokenFlag_q, pAllVldBgnFlag : std_logic;
begin
pAllVld <= pMeVld and pOtherChVld(0) and pOtherChVld(1);
pDataInBnd <= pDataFIFO; -- raw data with skew removed
pMeRdy <= pMeRdy_int; -- data is de-skewed and valid
-- The process below should result in a dual-port distributed RAM with registered output
FIFO: process (PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pAllVld = '1') then -- begin writing in FIFO as soon as all the channels have valid data
pFIFO(pWrA) <= pDataInRaw;
end if;
pDataFIFO <= pFIFO(pRdA); -- register FIFO output
end if;
end process FIFO;
-- FIFO address counters
FIFO_WrA: process (PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pAllVld = '1') then
pWrA <= pWrA + 1;
else -- when invalid data, go back to the beginning
pWrA <= 0;
end if;
end if;
end process FIFO_WrA;
FIFO_RdA: process (PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pAllVld = '0') then
pRdA <= 0;
elsif (pRdEn = '1') then
pRdA <= pRdA + 1;
end if;
end if;
end process FIFO_RdA;
DataValidFlag: process(PixelClk)
begin
if Rising_Edge(PixelClk) then
pAllVld_q <= pAllVld;
pAllVldBgnFlag <= not pAllVld_q and pAllVld; -- this flag used below delays enabling read, thus making sure data is written first before being read
end if;
end process DataValidFlag;
-------------------------------------------------------------------------------
-- Channel bonding is done here:
-- 1 When all the channels have valid data (ie. alignment lock), FIFO is flow-through
-- 2 When marker is found on this channel, FIFO read is paused, thus holding data
-- 3 When all channels report the marker, FIFO read begins again, thus syncing markers
-------------------------------------------------------------------------------
FIFO_RdEn: process(PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pAllVld = '0') then
pRdEn <= '0';
elsif (pAllVldBgnFlag = '1' or (pMeRdy_int = '1' and pOtherChRdy = "11")) then
pRdEn <= '1';
elsif (pBlnkBgnFlag = '1' and not (pMeRdy_int = '1' and pOtherChRdy = "11")) then
pRdEn <= '0';
end if;
end if;
end process FIFO_RdEn;
-- Detect blanking period begin
TokenDetect: process(PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pRdEn = '0' or pDataFIFO = kCtlTkn0 or pDataFIFO = kCtlTkn1 or pDataFIFO = kCtlTkn2 or pDataFIFO = kCtlTkn3) then
pTokenFlag <= '1'; --token flag activates on invalid data, which avoids a BlnkBgn pulse if the valid signal goes up in the middle of a blanking period
else
pTokenFlag <= '0';
end if;
pTokenFlag_q <= pTokenFlag;
pBlnkBgnFlag <= not pTokenFlag_q and pTokenFlag;
end if;
end process TokenDetect;
-- Ready signal when marker is received
IAmReady: process(PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pAllVld = '0') then -- if not all channels are valid, we are not ready either
pMeRdy_int <= '0';
elsif (pBlnkBgnFlag = '1') then
pMeRdy_int <= '1';
end if;
end if;
end process IAmReady;
end Behavioral;
|
bsd-3-clause
|
dh1dm/q27
|
src/vhdl/PoC/common/my_config_ML505.vhdl
|
2
|
1787
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Package: Project specific configuration.
--
-- Authors: Thomas B. Preusser
-- Martin Zabel
-- Patrick Lehmann
--
-- Package: Project specific configuration.
--
-- Description:
-- ------------
-- This file was created from the template file:
--
-- <PoCRoot>/src/common/my_config.template.vhdl
--
-- and customized for:
--
-- ML505
--
--
-- License:
-- =============================================================================
-- Copyright 2007-2014 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library PoC;
package my_config is
-- Change these lines to setup configuration.
constant MY_BOARD : string := "ML505";
constant MY_DEVICE : string := "None";
constant MY_VERBOSE : boolean := true;
end my_config;
package body my_config is
end my_config;
|
agpl-3.0
|
UnofficialRepos/OSVVM
|
MessageListPkg.vhd
|
1
|
5146
|
--
-- File Name: MessageListPkg.vhd
-- Design Unit Name: MessageListPkg
-- Revision: STANDARD VERSION
--
-- Maintainer: Jim Lewis email: [email protected]
-- Contributor(s):
-- Jim Lewis SynthWorks
--
--
-- Package Defines
-- Data structure for multi-line message
--
-- Developed for:
-- SynthWorks Design Inc.
-- VHDL Training Classes
-- 11898 SW 128th Ave. Tigard, Or 97223
-- http://www.SynthWorks.com
--
-- Revision History:
-- Date Version Description
-- 07/2021 2021.07 Initial revision.
-- Written as a replacement for protected types (MessagePkg)
-- to simplify usage in new data structure.
--
-- This file is part of OSVVM.
--
-- Copyright (c) 2021 by SynthWorks Design Inc.
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- https://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
library ieee ;
use std.textio.all ;
package MessageListPkg is
type MessageStructType ;
type MessageStructPtrType is access MessageStructType ;
type MessageStructType is record
Name : line ;
NextPtr : MessageStructPtrType ;
end record MessageStructType ;
procedure SetMessage (variable Message : inout MessageStructPtrType; Name : String) ;
procedure WriteMessage (variable buf : inout line; variable Message : inout MessageStructPtrType; prefix : string := "") ;
procedure WriteMessage (file f : text; variable Message : inout MessageStructPtrType; prefix : string := "") ;
procedure GetMessageCount (variable Message : inout MessageStructPtrType; variable Count : out integer) ;
procedure DeallocateMessage (variable Message : inout MessageStructPtrType) ;
end package MessageListPkg ;
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
package body MessageListPkg is
------------------------------------------------------------
procedure SetMessage (variable Message : inout MessageStructPtrType; Name : String) is
------------------------------------------------------------
variable M : MessageStructPtrType ;
begin
if Message = NULL then
Message := new MessageStructType ;
Message.Name := new string'(Name) ;
Message.NextPtr := NULL ;
else
M := Message ;
while M.NextPtr /= NULL loop
M := M.NextPtr ;
end loop ;
M.NextPtr := new MessageStructType ;
M := M.NextPtr ;
M.Name := new string'(Name) ;
M.NextPtr := NULL ;
end if ;
end procedure SetMessage ;
------------------------------------------------------------
procedure WriteMessage (variable buf : inout line; variable Message : inout MessageStructPtrType; prefix : string := "") is
------------------------------------------------------------
variable M : MessageStructPtrType ;
begin
M := Message ;
while M /= NULL loop
write(buf, prefix & M.Name.all & LF) ;
M := M.NextPtr ;
end loop ;
end procedure WriteMessage ;
------------------------------------------------------------
procedure WriteMessage (file f : text; variable Message : inout MessageStructPtrType; prefix : string := "") is
------------------------------------------------------------
variable M : MessageStructPtrType ;
variable buf : line ;
begin
M := Message ;
while M /= NULL loop
write(buf, prefix & M.Name.all) ;
writeline(f, buf) ;
M := M.NextPtr ;
end loop ;
end procedure WriteMessage ;
------------------------------------------------------------
procedure GetMessageCount (variable Message : inout MessageStructPtrType; variable Count : out integer) is
------------------------------------------------------------
variable M : MessageStructPtrType ;
begin
Count := 0 ;
M := Message ;
while M /= NULL loop
Count := Count + 1 ;
M := M.NextPtr ;
end loop ;
end procedure GetMessageCount ;
------------------------------------------------------------
procedure DeallocateMessage (variable Message : inout MessageStructPtrType) is
------------------------------------------------------------
variable OldM : MessageStructPtrType ;
begin
while Message /= NULL loop
OldM := Message ;
Message := Message.NextPtr ;
deallocate(OldM) ;
end loop ;
end procedure DeallocateMessage ;
end package body MessageListPkg ;
|
artistic-2.0
|
UnofficialRepos/OSVVM
|
ScoreboardGenericPkg.vhd
|
1
|
135946
|
--
-- File Name: ScoreBoardGenericPkg.vhd
-- Design Unit Name: ScoreBoardGenericPkg
-- Revision: STANDARD VERSION
--
-- Maintainer: Jim Lewis email: [email protected]
-- Contributor(s):
-- Jim Lewis email: [email protected]
--
--
-- Description:
-- Defines types and methods to implement a FIFO based Scoreboard
-- Defines type ScoreBoardPType
-- Defines methods for putting values the scoreboard
--
-- Developed for:
-- SynthWorks Design Inc.
-- VHDL Training Classes
-- 11898 SW 128th Ave. Tigard, Or 97223
-- http://www.SynthWorks.com
--
-- Revision History:
-- Date Version Description
-- 03/2022 2022.03 Removed deprecated SetAlertLogID in Singleton API
-- 02/2022 2022.02 Added WriteScoreboardYaml and GotScoreboards. Updated NewID with ParentID,
-- ReportMode, Search, PrintParent. Supports searching for Scoreboard models..
-- 01/2022 2022.01 Added CheckExpected. Added SetCheckCountZero to ScoreboardPType
-- 08/2021 2021.08 Removed SetAlertLogID from singleton public interface - set instead by NewID
-- 06/2021 2021.06 Updated Data Structure, IDs for new use model, and Wrapper Subprograms
-- 10/2020 2020.10 Added Peek
-- 05/2020 2020.05 Updated calls to IncAffirmCount
-- Overloaded Check with functions that return pass/fail (T/F)
-- Added GetFifoCount. Added GetPushCount which is same as GetItemCount
-- 01/2020 2020.01 Updated Licenses to Apache
-- 04/2018 2018.04 Made Pop Functions Visible. Prep for AlertLogIDType being a type.
-- 05/2017 2017.05 First print Actual then only print Expected if mis-match
-- 11/2016 2016.11 Released as part of OSVVM
-- 06/2015 2015.06 Added Alerts, SetAlertLogID, Revised LocalPush, GetDropCount,
-- Deprecated SetFinish and ReportMode - REPORT_NONE, FileOpen
-- Deallocate, Initialized, Function SetName
-- 09/2013 2013.09 Added file handling, Check Count, Finish Status
-- Find, Flush
-- 08/2013 2013.08 Generics: to_string replaced write, Match replaced check
-- Added Tags - Experimental
-- Added Array of Scoreboards
-- 08/2012 2012.08 Added Type and Subprogram Generics
-- 05/2012 2012.05 Changed FIFO to store pointers to ExpectedType
-- Allows usage of unconstrained arrays
-- 08/2010 2010.08 Added Tailpointer
-- 12/2006 2006.12 Initial revision
--
--
--
-- This file is part of OSVVM.
--
-- Copyright (c) 2006 - 2022 by SynthWorks Design Inc.
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- https://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
use std.textio.all ;
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
use work.TranscriptPkg.all ;
use work.TextUtilPkg.all ;
use work.AlertLogPkg.all ;
use work.NamePkg.all ;
use work.NameStorePkg.all ;
use work.ResolutionPkg.all ;
package ScoreboardGenericPkg is
generic (
type ExpectedType ;
type ActualType ;
function Match(Actual : ActualType ; -- defaults
Expected : ExpectedType) return boolean ; -- is "=" ;
function expected_to_string(A : ExpectedType) return string ; -- is to_string ;
function actual_to_string (A : ActualType) return string -- is to_string ;
) ;
-- -- For a VHDL-2002 package, comment out the generics and
-- -- uncomment the following, it replaces a generic instance of the package.
-- -- As a result, you will have multiple copies of the entire package.
-- -- Inconvenient, but ok as it still works the same.
-- subtype ExpectedType is std_logic_vector ;
-- subtype ActualType is std_logic_vector ;
-- alias Match is std_match [ActualType, ExpectedType return boolean] ; -- for std_logic_vector
-- alias expected_to_string is to_hstring [ExpectedType return string]; -- VHDL-2008
-- alias actual_to_string is to_hstring [ActualType return string]; -- VHDL-2008
-- ScoreboardReportType is deprecated
-- Replaced by Affirmations. ERROR is the default. ALL turns on PASSED flag
type ScoreboardReportType is (REPORT_ERROR, REPORT_ALL, REPORT_NONE) ; -- replaced by affirmations
type ScoreboardIdType is record
Id : integer_max ;
end record ScoreboardIdType ;
type ScoreboardIdArrayType is array (integer range <>) of ScoreboardIdType ;
type ScoreboardIdMatrixType is array (integer range <>, integer range <>) of ScoreboardIdType ;
-- Preparation for refactoring - if that ever happens.
subtype FifoIdType is ScoreboardIdType ;
subtype FifoIdArrayType is ScoreboardIdArrayType ;
subtype FifoIdMatrixType is ScoreboardIdMatrixType ;
------------------------------------------------------------
-- Used by Scoreboard Store
impure function NewID (
Name : String ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIDType ;
------------------------------------------------------------
-- Vector: 1 to Size
impure function NewID (
Name : String ;
Size : positive ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIDArrayType ;
------------------------------------------------------------
-- Vector: X(X'Left) to X(X'Right)
impure function NewID (
Name : String ;
X : integer_vector ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIDArrayType ;
------------------------------------------------------------
-- Matrix: 1 to X, 1 to Y
impure function NewID (
Name : String ;
X, Y : positive ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIdMatrixType ;
------------------------------------------------------------
-- Matrix: X(X'Left) to X(X'Right), Y(Y'Left) to Y(Y'Right)
impure function NewID (
Name : String ;
X, Y : integer_vector ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIdMatrixType ;
------------------------------------------------------------
-- Push items into the scoreboard/FIFO
-- Simple Scoreboard, no tag
procedure Push (
constant ID : in ScoreboardIDType ;
constant Item : in ExpectedType
) ;
-- Simple Tagged Scoreboard
procedure Push (
constant ID : in ScoreboardIDType ;
constant Tag : in string ;
constant Item : in ExpectedType
) ;
------------------------------------------------------------
-- Check received item with item in the scoreboard/FIFO
-- Simple Scoreboard, no tag
procedure Check (
constant ID : in ScoreboardIDType ;
constant ActualData : in ActualType
) ;
-- Simple Tagged Scoreboard
procedure Check (
constant ID : in ScoreboardIDType ;
constant Tag : in string ;
constant ActualData : in ActualType
) ;
-- Simple Scoreboard, no tag
impure function Check (
constant ID : in ScoreboardIDType ;
constant ActualData : in ActualType
) return boolean ;
-- Simple Tagged Scoreboard
impure function Check (
constant ID : in ScoreboardIDType ;
constant Tag : in string ;
constant ActualData : in ActualType
) return boolean ;
----------------------------------------------
-- Simple Scoreboard, no tag
procedure CheckExpected (
constant ID : in ScoreboardIDType ;
constant ExpectedData : in ActualType
) ;
-- Simple Tagged Scoreboard
procedure CheckExpected (
constant ID : in ScoreboardIDType ;
constant Tag : in string ;
constant ExpectedData : in ActualType
) ;
-- Simple Scoreboard, no tag
impure function CheckExpected (
constant ID : in ScoreboardIDType ;
constant ExpectedData : in ActualType
) return boolean ;
-- Simple Tagged Scoreboard
impure function CheckExpected (
constant ID : in ScoreboardIDType ;
constant Tag : in string ;
constant ExpectedData : in ActualType
) return boolean ;
------------------------------------------------------------
-- Pop the top item (FIFO) from the scoreboard/FIFO
-- Simple Scoreboard, no tag
procedure Pop (
constant ID : in ScoreboardIDType ;
variable Item : out ExpectedType
) ;
-- Simple Tagged Scoreboard
procedure Pop (
constant ID : in ScoreboardIDType ;
constant Tag : in string ;
variable Item : out ExpectedType
) ;
------------------------------------------------------------
-- Pop the top item (FIFO) from the scoreboard/FIFO
-- Caution: this did not work in older simulators (@2013)
-- Simple Scoreboard, no tag
impure function Pop (
constant ID : in ScoreboardIDType
) return ExpectedType ;
-- Simple Tagged Scoreboard
impure function Pop (
constant ID : in ScoreboardIDType ;
constant Tag : in string
) return ExpectedType ;
------------------------------------------------------------
-- Peek at the top item (FIFO) from the scoreboard/FIFO
-- Simple Tagged Scoreboard
procedure Peek (
constant ID : in ScoreboardIDType ;
constant Tag : in string ;
variable Item : out ExpectedType
) ;
-- Simple Scoreboard, no tag
procedure Peek (
constant ID : in ScoreboardIDType ;
variable Item : out ExpectedType
) ;
------------------------------------------------------------
-- Peek at the top item (FIFO) from the scoreboard/FIFO
-- Caution: this did not work in older simulators (@2013)
-- Tagged Scoreboards
impure function Peek (
constant ID : in ScoreboardIDType ;
constant Tag : in string
) return ExpectedType ;
-- Simple Scoreboard
impure function Peek (
constant ID : in ScoreboardIDType
) return ExpectedType ;
------------------------------------------------------------
-- Empty - check to see if scoreboard is empty
-- Simple
impure function ScoreboardEmpty (
constant ID : in ScoreboardIDType
) return boolean ;
-- Tagged
impure function ScoreboardEmpty (
constant ID : in ScoreboardIDType ;
constant Tag : in string
) return boolean ; -- Simple, Tagged
impure function Empty (
constant ID : in ScoreboardIDType
) return boolean ;
-- Tagged
impure function Empty (
constant ID : in ScoreboardIDType ;
constant Tag : in string
) return boolean ; -- Simple, Tagged
--!! ------------------------------------------------------------
--!! -- SetAlertLogID - associate an AlertLogID with a scoreboard to allow integrated error reporting
--!! procedure SetAlertLogID(
--!! constant ID : in ScoreboardIDType ;
--!! constant Name : in string ;
--!! constant ParentID : in AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
--!! constant CreateHierarchy : in Boolean := TRUE ;
--!! constant DoNotReport : in Boolean := FALSE
--!! ) ;
--!!
--!! -- Use when an AlertLogID is used by multiple items (Model or other Scoreboards). See also AlertLogPkg.GetAlertLogID
--!! procedure SetAlertLogID (
--!! constant ID : in ScoreboardIDType ;
--!! constant A : AlertLogIDType
--!! ) ;
impure function GetAlertLogID (
constant ID : in ScoreboardIDType
) return AlertLogIDType ;
------------------------------------------------------------
-- Scoreboard Introspection
-- Number of items put into scoreboard
impure function GetItemCount (
constant ID : in ScoreboardIDType
) return integer ; -- Simple, with or without tags
impure function GetPushCount (
constant ID : in ScoreboardIDType
) return integer ; -- Simple, with or without tags
-- Number of items removed from scoreboard by pop or check
impure function GetPopCount (
constant ID : in ScoreboardIDType
) return integer ;
-- Number of items currently in the scoreboard (= PushCount - PopCount - DropCount)
impure function GetFifoCount (
constant ID : in ScoreboardIDType
) return integer ;
-- Number of items checked by scoreboard
impure function GetCheckCount (
constant ID : in ScoreboardIDType
) return integer ; -- Simple, with or without tags
-- Number of items dropped by scoreboard. See Find/Flush
impure function GetDropCount (
constant ID : in ScoreboardIDType
) return integer ; -- Simple, with or without tags
------------------------------------------------------------
-- Find - Returns the ItemNumber for a value and tag (if applicable) in a scoreboard.
-- Find returns integer'left if no match found
-- Also See Flush. Flush will drop items up through the ItemNumber
-- Simple Scoreboard
impure function Find (
constant ID : in ScoreboardIDType ;
constant ActualData : in ActualType
) return integer ;
-- Tagged Scoreboard
impure function Find (
constant ID : in ScoreboardIDType ;
constant Tag : in string;
constant ActualData : in ActualType
) return integer ;
------------------------------------------------------------
-- Flush - Remove elements in the scoreboard upto and including the one with ItemNumber
-- See Find to identify an ItemNumber of a particular value and tag (if applicable)
-- Simple Scoreboards
procedure Flush (
constant ID : in ScoreboardIDType ;
constant ItemNumber : in integer
) ;
-- Tagged Scoreboards - only removes items that also match the tag
procedure Flush (
constant ID : in ScoreboardIDType ;
constant Tag : in string ;
constant ItemNumber : in integer
) ;
------------------------------------------------------------
-- Writing YAML Reports
impure function GotScoreboards return boolean ;
procedure WriteScoreboardYaml (FileName : string := ""; OpenKind : File_Open_Kind := WRITE_MODE) ;
------------------------------------------------------------
-- Generally these are not required. When a simulation ends and
-- another simulation is started, a simulator will release all allocated items.
procedure Deallocate (
constant ID : in ScoreboardIDType
) ; -- Deletes all allocated items
procedure Initialize (
constant ID : in ScoreboardIDType
) ; -- Creates initial data structure if it was destroyed with Deallocate
------------------------------------------------------------
-- Get error count
-- Deprecated, replaced by usage of Alerts
-- AlertFLow: Instead use AlertLogPkg.ReportAlerts or AlertLogPkg.GetAlertCount
-- Not AlertFlow: use GetErrorCount to get total error count
-- Scoreboards, with or without tag
impure function GetErrorCount(
constant ID : in ScoreboardIDType
) return integer ;
------------------------------------------------------------
procedure CheckFinish (
------------------------------------------------------------
ID : ScoreboardIDType ;
FinishCheckCount : integer ;
FinishEmpty : boolean
) ;
------------------------------------------------------------
-- SetReportMode
-- Not AlertFlow
-- REPORT_ALL: Replaced by AlertLogPkg.SetLogEnable(PASSED, TRUE)
-- REPORT_ERROR: Replaced by AlertLogPkg.SetLogEnable(PASSED, FALSE)
-- REPORT_NONE: Deprecated, do not use.
-- AlertFlow:
-- REPORT_ALL: Replaced by AlertLogPkg.SetLogEnable(AlertLogID, PASSED, TRUE)
-- REPORT_ERROR: Replaced by AlertLogPkg.SetLogEnable(AlertLogID, PASSED, FALSE)
-- REPORT_NONE: Replaced by AlertLogPkg.SetAlertEnable(AlertLogID, ERROR, FALSE)
procedure SetReportMode (
constant ID : in ScoreboardIDType ;
constant ReportModeIn : in ScoreboardReportType
) ;
impure function GetReportMode (
constant ID : in ScoreboardIDType
) return ScoreboardReportType ;
type ScoreBoardPType is protected
------------------------------------------------------------
-- Used by Scoreboard Store
impure function NewID (
Name : String ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIDType ;
------------------------------------------------------------
-- Vector: 1 to Size
impure function NewID (
Name : String ;
Size : positive ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIDArrayType ;
------------------------------------------------------------
-- Vector: X(X'Left) to X(X'Right)
impure function NewID (
Name : String ;
X : integer_vector ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIDArrayType ;
------------------------------------------------------------
-- Matrix: 1 to X, 1 to Y
impure function NewID (
Name : String ;
X, Y : positive ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIdMatrixType ;
------------------------------------------------------------
-- Matrix: X(X'Left) to X(X'Right), Y(Y'Left) to Y(Y'Right)
impure function NewID (
Name : String ;
X, Y : integer_vector ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIdMatrixType ;
------------------------------------------------------------
-- Emulate arrays of scoreboards
procedure SetArrayIndex(L, R : integer) ; -- supports integer indices
procedure SetArrayIndex(R : natural) ; -- indicies 1 to R
impure function GetArrayIndex return integer_vector ;
impure function GetArrayLength return natural ;
------------------------------------------------------------
-- Push items into the scoreboard/FIFO
-- Simple Scoreboard, no tag
procedure Push (Item : in ExpectedType) ;
-- Simple Tagged Scoreboard
procedure Push (
constant Tag : in string ;
constant Item : in ExpectedType
) ;
-- Array of Scoreboards, no tag
procedure Push (
constant Index : in integer ;
constant Item : in ExpectedType
) ;
-- Array of Tagged Scoreboards
procedure Push (
constant Index : in integer ;
constant Tag : in string ;
constant Item : in ExpectedType
) ;
-- ------------------------------------------------------------
-- -- Push items into the scoreboard/FIFO
-- -- Function form supports chaining of operations
-- -- In 2013, this caused overloading issues in some simulators, will retest later
--
-- -- Simple Scoreboard, no tag
-- impure function Push (Item : ExpectedType) return ExpectedType ;
--
-- -- Simple Tagged Scoreboard
-- impure function Push (
-- constant Tag : in string ;
-- constant Item : in ExpectedType
-- ) return ExpectedType ;
--
-- -- Array of Scoreboards, no tag
-- impure function Push (
-- constant Index : in integer ;
-- constant Item : in ExpectedType
-- ) return ExpectedType ;
--
-- -- Array of Tagged Scoreboards
-- impure function Push (
-- constant Index : in integer ;
-- constant Tag : in string ;
-- constant Item : in ExpectedType
-- ) return ExpectedType ; -- for chaining of operations
------------------------------------------------------------
-- Check received item with item in the scoreboard/FIFO
-- Simple Scoreboard, no tag
procedure Check (ActualData : ActualType) ;
-- Simple Tagged Scoreboard
procedure Check (
constant Tag : in string ;
constant ActualData : in ActualType
) ;
-- Array of Scoreboards, no tag
procedure Check (
constant Index : in integer ;
constant ActualData : in ActualType
) ;
-- Array of Tagged Scoreboards
procedure Check (
constant Index : in integer ;
constant Tag : in string ;
constant ActualData : in ActualType
) ;
-- Simple Scoreboard, no tag
impure function Check (ActualData : ActualType) return boolean ;
-- Simple Tagged Scoreboard
impure function Check (
constant Tag : in string ;
constant ActualData : in ActualType
) return boolean ;
-- Array of Scoreboards, no tag
impure function Check (
constant Index : in integer ;
constant ActualData : in ActualType
) return boolean ;
-- Array of Tagged Scoreboards
impure function Check (
constant Index : in integer ;
constant Tag : in string ;
constant ActualData : in ActualType
) return boolean ;
-------------------------------
-- Array of Tagged Scoreboards
impure function CheckExpected (
constant Index : in integer ;
constant Tag : in string ;
constant ExpectedData : in ActualType
) return boolean ;
------------------------------------------------------------
-- Pop the top item (FIFO) from the scoreboard/FIFO
-- Simple Scoreboard, no tag
procedure Pop (variable Item : out ExpectedType) ;
-- Simple Tagged Scoreboard
procedure Pop (
constant Tag : in string ;
variable Item : out ExpectedType
) ;
-- Array of Scoreboards, no tag
procedure Pop (
constant Index : in integer ;
variable Item : out ExpectedType
) ;
-- Array of Tagged Scoreboards
procedure Pop (
constant Index : in integer ;
constant Tag : in string ;
variable Item : out ExpectedType
) ;
------------------------------------------------------------
-- Pop the top item (FIFO) from the scoreboard/FIFO
-- Caution: this did not work in older simulators (@2013)
-- Simple Scoreboard, no tag
impure function Pop return ExpectedType ;
-- Simple Tagged Scoreboard
impure function Pop (
constant Tag : in string
) return ExpectedType ;
-- Array of Scoreboards, no tag
impure function Pop (Index : integer) return ExpectedType ;
-- Array of Tagged Scoreboards
impure function Pop (
constant Index : in integer ;
constant Tag : in string
) return ExpectedType ;
------------------------------------------------------------
-- Peek at the top item (FIFO) from the scoreboard/FIFO
-- Array of Tagged Scoreboards
procedure Peek (
constant Index : in integer ;
constant Tag : in string ;
variable Item : out ExpectedType
) ;
-- Array of Scoreboards, no tag
procedure Peek (
constant Index : in integer ;
variable Item : out ExpectedType
) ;
-- Simple Tagged Scoreboard
procedure Peek (
constant Tag : in string ;
variable Item : out ExpectedType
) ;
-- Simple Scoreboard, no tag
procedure Peek (variable Item : out ExpectedType) ;
------------------------------------------------------------
-- Peek at the top item (FIFO) from the scoreboard/FIFO
-- Caution: this did not work in older simulators (@2013)
-- Array of Tagged Scoreboards
impure function Peek (
constant Index : in integer ;
constant Tag : in string
) return ExpectedType ;
-- Array of Scoreboards, no tag
impure function Peek (Index : integer) return ExpectedType ;
-- Simple Tagged Scoreboard
impure function Peek (
constant Tag : in string
) return ExpectedType ;
-- Simple Scoreboard, no tag
impure function Peek return ExpectedType ;
------------------------------------------------------------
-- Empty - check to see if scoreboard is empty
impure function Empty return boolean ; -- Simple
impure function Empty (Tag : String) return boolean ; -- Simple, Tagged
impure function Empty (Index : integer) return boolean ; -- Array
impure function Empty (Index : integer; Tag : String) return boolean ; -- Array, Tagged
------------------------------------------------------------
-- SetAlertLogID - associate an AlertLogID with a scoreboard to allow integrated error reporting
-- ReportMode := ENABLED when not DoNotReport else DISABLED ;
procedure SetAlertLogID(Index : Integer; Name : string; ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID; CreateHierarchy : Boolean := TRUE; DoNotReport : Boolean := FALSE) ;
procedure SetAlertLogID(Name : string; ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID; CreateHierarchy : Boolean := TRUE; DoNotReport : Boolean := FALSE) ;
-- Use when an AlertLogID is used by multiple items (Model or other Scoreboards). See also AlertLogPkg.GetAlertLogID
procedure SetAlertLogID (Index : Integer ; A : AlertLogIDType) ;
procedure SetAlertLogID (A : AlertLogIDType) ;
impure function GetAlertLogID(Index : Integer) return AlertLogIDType ;
impure function GetAlertLogID return AlertLogIDType ;
------------------------------------------------------------
-- Set a scoreboard name.
-- Used when scoreboard AlertLogID is shared between different sources.
procedure SetName (Name : String) ;
impure function SetName (Name : String) return string ;
impure function GetName (DefaultName : string := "Scoreboard") return string ;
------------------------------------------------------------
-- Scoreboard Introspection
-- Number of items put into scoreboard
impure function GetItemCount return integer ; -- Simple, with or without tags
impure function GetItemCount (Index : integer) return integer ; -- Arrays, with or without tags
impure function GetPushCount return integer ; -- Simple, with or without tags
impure function GetPushCount (Index : integer) return integer ; -- Arrays, with or without tags
-- Number of items removed from scoreboard by pop or check
impure function GetPopCount (Index : integer) return integer ;
impure function GetPopCount return integer ;
-- Number of items currently in the scoreboard (= PushCount - PopCount - DropCount)
impure function GetFifoCount (Index : integer) return integer ;
impure function GetFifoCount return integer ;
-- Number of items checked by scoreboard
impure function GetCheckCount return integer ; -- Simple, with or without tags
impure function GetCheckCount (Index : integer) return integer ; -- Arrays, with or without tags
-- Number of items dropped by scoreboard. See Find/Flush
impure function GetDropCount return integer ; -- Simple, with or without tags
impure function GetDropCount (Index : integer) return integer ; -- Arrays, with or without tags
------------------------------------------------------------
-- Find - Returns the ItemNumber for a value and tag (if applicable) in a scoreboard.
-- Find returns integer'left if no match found
-- Also See Flush. Flush will drop items up through the ItemNumber
-- Simple Scoreboard
impure function Find (
constant ActualData : in ActualType
) return integer ;
-- Tagged Scoreboard
impure function Find (
constant Tag : in string;
constant ActualData : in ActualType
) return integer ;
-- Array of Simple Scoreboards
impure function Find (
constant Index : in integer ;
constant ActualData : in ActualType
) return integer ;
-- Array of Tagged Scoreboards
impure function Find (
constant Index : in integer ;
constant Tag : in string;
constant ActualData : in ActualType
) return integer ;
------------------------------------------------------------
-- Flush - Remove elements in the scoreboard upto and including the one with ItemNumber
-- See Find to identify an ItemNumber of a particular value and tag (if applicable)
-- Simple Scoreboard
procedure Flush (
constant ItemNumber : in integer
) ;
-- Tagged Scoreboard - only removes items that also match the tag
procedure Flush (
constant Tag : in string ;
constant ItemNumber : in integer
) ;
-- Array of Simple Scoreboards
procedure Flush (
constant Index : in integer ;
constant ItemNumber : in integer
) ;
-- Array of Tagged Scoreboards - only removes items that also match the tag
procedure Flush (
constant Index : in integer ;
constant Tag : in string ;
constant ItemNumber : in integer
) ;
------------------------------------------------------------
-- Writing YAML Reports
impure function GotScoreboards return boolean ;
procedure WriteScoreboardYaml (FileName : string := ""; OpenKind : File_Open_Kind := WRITE_MODE) ;
------------------------------------------------------------
-- Generally these are not required. When a simulation ends and
-- another simulation is started, a simulator will release all allocated items.
procedure Deallocate ; -- Deletes all allocated items
procedure Initialize ; -- Creates initial data structure if it was destroyed with Deallocate
------------------------------------------------------------
------------------------------------------------------------
-- Deprecated. Use alerts directly instead.
-- AlertIF(SB.GetCheckCount < 10, ....) ;
-- AlertIf(Not SB.Empty, ...) ;
------------------------------------------------------------
-- Set alerts if scoreboard not empty or if CheckCount <
-- Use if need to check empty or CheckCount for a specific scoreboard.
-- Simple Scoreboards, with or without tag
procedure CheckFinish (
FinishCheckCount : integer ;
FinishEmpty : boolean
) ;
-- Array of Scoreboards, with or without tag
procedure CheckFinish (
Index : integer ;
FinishCheckCount : integer ;
FinishEmpty : boolean
) ;
------------------------------------------------------------
-- Get error count
-- Deprecated, replaced by usage of Alerts
-- AlertFLow: Instead use AlertLogPkg.ReportAlerts or AlertLogPkg.GetAlertCount
-- Not AlertFlow: use GetErrorCount to get total error count
-- Simple Scoreboards, with or without tag
impure function GetErrorCount return integer ;
-- Array of Scoreboards, with or without tag
impure function GetErrorCount(Index : integer) return integer ;
------------------------------------------------------------
-- Error count manipulation
-- IncErrorCount - not recommended, use alerts instead - may be deprecated in the future
procedure IncErrorCount ; -- Simple, with or without tags
procedure IncErrorCount (Index : integer) ; -- Arrays, with or without tags
-- Clear error counter. Caution does not change AlertCounts, must also use AlertLogPkg.ClearAlerts
procedure SetErrorCountZero ; -- Simple, with or without tags
procedure SetErrorCountZero (Index : integer) ; -- Arrays, with or without tags
-- Clear check counter. Caution does not change AffirmationCounters
procedure SetCheckCountZero ; -- Simple, with or without tags
procedure SetCheckCountZero (Index : integer) ; -- Arrays, with or without tags
------------------------------------------------------------
------------------------------------------------------------
-- Deprecated. Names changed. Maintained for backward compatibility - would prefer an alias
------------------------------------------------------------
procedure FileOpen (FileName : string; OpenKind : File_Open_Kind ) ; -- Replaced by TranscriptPkg.TranscriptOpen
procedure PutExpectedData (ExpectedData : ExpectedType) ; -- Replaced by push
procedure CheckActualData (ActualData : ActualType) ; -- Replaced by Check
impure function GetItemNumber return integer ; -- Replaced by GetItemCount
procedure SetMessage (MessageIn : String) ; -- Replaced by SetName
impure function GetMessage return string ; -- Replaced by GetName
-- Deprecated and may be deleted in a future revision
procedure SetFinish ( -- Replaced by CheckFinish
Index : integer ;
FCheckCount : integer ;
FEmpty : boolean := TRUE;
FStatus : boolean := TRUE
) ;
procedure SetFinish ( -- Replaced by CheckFinish
FCheckCount : integer ;
FEmpty : boolean := TRUE;
FStatus : boolean := TRUE
) ;
------------------------------------------------------------
-- SetReportMode
-- Not AlertFlow
-- REPORT_ALL: Replaced by AlertLogPkg.SetLogEnable(PASSED, TRUE)
-- REPORT_ERROR: Replaced by AlertLogPkg.SetLogEnable(PASSED, FALSE)
-- REPORT_NONE: Deprecated, do not use.
-- AlertFlow:
-- REPORT_ALL: Replaced by AlertLogPkg.SetLogEnable(AlertLogID, PASSED, TRUE)
-- REPORT_ERROR: Replaced by AlertLogPkg.SetLogEnable(AlertLogID, PASSED, FALSE)
-- REPORT_NONE: Replaced by AlertLogPkg.SetAlertEnable(AlertLogID, ERROR, FALSE)
procedure SetReportMode (ReportModeIn : ScoreboardReportType) ;
impure function GetReportMode return ScoreboardReportType ;
------------------------------------------------------------
------------------------------------------------------------
-- -- Deprecated Interface to NewID
-- impure function NewID (Name : String; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIDType ;
-- -- Vector: 1 to Size
-- impure function NewID (Name : String; Size : positive; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIDArrayType ;
-- -- Vector: X(X'Left) to X(X'Right)
-- impure function NewID (Name : String; X : integer_vector; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIDArrayType ;
-- -- Matrix: 1 to X, 1 to Y
-- impure function NewID (Name : String; X, Y : positive; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIdMatrixType ;
-- -- Matrix: X(X'Left) to X(X'Right), Y(Y'Left) to Y(Y'Right)
-- impure function NewID (Name : String; X, Y : integer_vector; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIdMatrixType ;
end protected ScoreBoardPType ;
------------------------------------------------------------
-- Deprecated Interface to NewID
impure function NewID (Name : String; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIDType ;
-- Vector: 1 to Size
impure function NewID (Name : String; Size : positive; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIDArrayType ;
-- Vector: X(X'Left) to X(X'Right)
impure function NewID (Name : String; X : integer_vector; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIDArrayType ;
-- Matrix: 1 to X, 1 to Y
impure function NewID (Name : String; X, Y : positive; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIdMatrixType ;
-- Matrix: X(X'Left) to X(X'Right), Y(Y'Left) to Y(Y'Right)
impure function NewID (Name : String; X, Y : integer_vector; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIdMatrixType ;
end ScoreboardGenericPkg ;
-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
package body ScoreboardGenericPkg is
type ScoreBoardPType is protected body
type ExpectedPointerType is access ExpectedType ;
type ListType ;
type ListPointerType is access ListType ;
type ListType is record
ItemNumber : integer ;
TagPtr : line ;
ExpectedPtr : ExpectedPointerType ;
NextPtr : ListPointerType ;
end record ;
--!! Replace the following with
-- type ScoreboardRecType is record
-- HeadPointer : ListPointerType ;
-- TailPointer : ListPointerType ;
-- PopListPointer : ListPointerType ;
--
-- ErrCnt : integer ;
-- DropCount : integer ;
-- ItemNumber : integer ;
-- PopCount : integer ;
-- CheckCount : integer ;
-- AlertLogID : AlertLogIDType ;
-- Name : NameStoreIDType ;
-- ReportMode : ScoreboardReportType ;
-- end record ScoreboardRecType ;
--
-- type ScoreboardRecArrayType is array (integer range <>) of ScoreboardRecType ;
-- type ScoreboardRecArrayPointerType is access ScoreboardRecArrayType ;
-- variable ScoreboardPointer : ScoreboardRecArrayPointerType ;
--
-- -- Alas unfortunately aliases don't word as follows:
-- -- alias HeadPointer(I) is ScoreboardPointer(I).HeadPointer ;
type ListArrayType is array (integer range <>) of ListPointerType ;
type ListArrayPointerType is access ListArrayType ;
variable ArrayLengthVar : integer := 1 ;
-- Original Code
-- variable HeadPointer : ListArrayPointerType := new ListArrayType(1 to 1) ;
-- variable TailPointer : ListArrayPointerType := new ListArrayType(1 to 1) ;
-- -- PopListPointer needed for Pop to be a function - alternately need 2019 features
-- variable PopListPointer : ListArrayPointerType := new ListArrayType(1 to 1) ;
--
-- Legal, but crashes simulator more thoroughly
-- variable HeadPointer : ListArrayPointerType := new ListArrayType'(1 => NULL) ;
-- variable TailPointer : ListArrayPointerType := new ListArrayType'(1 => NULL) ;
-- -- PopListPointer needed for Pop to be a function - alternately need 2019 features
-- variable PopListPointer : ListArrayPointerType := new ListArrayType'(1 => NULL) ;
-- Working work around for QS 2020.04 and 2021.02
variable Template : ListArrayType(1 to 1) ; -- Work around for QS 2020.04 and 2021.02
variable HeadPointer : ListArrayPointerType := new ListArrayType'(Template) ;
variable TailPointer : ListArrayPointerType := new ListArrayType'(Template) ;
-- PopListPointer needed for Pop to be a function - alternately need 2019 features
variable PopListPointer : ListArrayPointerType := new ListArrayType'(Template) ;
type IntegerArrayType is array (integer range <>) of Integer ;
type IntegerArrayPointerType is access IntegerArrayType ;
type AlertLogIDArrayType is array (integer range <>) of AlertLogIDType ;
type AlertLogIDArrayPointerType is access AlertLogIDArrayType ;
variable ErrCntVar : IntegerArrayPointerType := new IntegerArrayType'(1 => 0) ;
variable DropCountVar : IntegerArrayPointerType := new IntegerArrayType'(1 => 0) ;
variable ItemNumberVar : IntegerArrayPointerType := new IntegerArrayType'(1 => 0) ;
variable PopCountVar : IntegerArrayPointerType := new IntegerArrayType'(1 => 0) ;
variable CheckCountVar : IntegerArrayPointerType := new IntegerArrayType'(1 => 0) ;
variable AlertLogIDVar : AlertLogIDArrayPointerType := new AlertLogIDArrayType'(1 => OSVVM_SCOREBOARD_ALERTLOG_ID) ;
variable NameVar : NamePType ;
variable ReportModeVar : ScoreboardReportType ;
variable FirstIndexVar : integer := 1 ;
variable PrintIndexVar : boolean := TRUE ;
variable CalledNewID : boolean := FALSE ;
variable LocalNameStore : NameStorePType ;
------------------------------------------------------------
-- Used by ScoreboardStore
variable NumItems : integer := 0 ;
constant MIN_NUM_ITEMS : integer := 4 ; -- Temporarily small for testing
-- constant MIN_NUM_ITEMS : integer := 32 ; -- Min amount to resize array
------------------------------------------------------------
procedure SetPrintIndex (Enable : boolean := TRUE) is
------------------------------------------------------------
begin
PrintIndexVar := Enable ;
end procedure SetPrintIndex ;
------------------------------------------------------------
-- Package Local
function NormalizeArraySize( NewNumItems, MinNumItems : integer ) return integer is
------------------------------------------------------------
variable NormNumItems : integer := NewNumItems ;
variable ModNumItems : integer := 0;
begin
ModNumItems := NewNumItems mod MinNumItems ;
if ModNumItems > 0 then
NormNumItems := NormNumItems + (MinNumItems - ModNumItems) ;
end if ;
return NormNumItems ;
end function NormalizeArraySize ;
------------------------------------------------------------
-- Package Local
procedure GrowNumberItems (
------------------------------------------------------------
variable NumItems : InOut integer ;
constant GrowAmount : in integer ;
constant MinNumItems : in integer
) is
variable NewNumItems : integer ;
begin
NewNumItems := NumItems + GrowAmount ;
if NewNumItems > HeadPointer'length then
SetArrayIndex(1, NormalizeArraySize(NewNumItems, MinNumItems)) ;
end if ;
NumItems := NewNumItems ;
end procedure GrowNumberItems ;
------------------------------------------------------------
-- Local/Private to package
impure function LocalNewID (
Name : String ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIDType is
------------------------------------------------------------
variable NameID : integer ;
begin
NameID := LocalNameStore.find(Name, ParentID, Search) ;
-- Share the scoreboards if they match
if NameID /= ID_NOT_FOUND.ID then
return ScoreboardIDType'(ID => NameID) ;
else
-- Resize Data Structure as necessary
GrowNumberItems(NumItems, GrowAmount => 1, MinNumItems => MIN_NUM_ITEMS) ;
-- Create AlertLogID
AlertLogIDVar(NumItems) := NewID(Name, ParentID, ReportMode, PrintParent, CreateHierarchy => FALSE) ;
-- Add item to NameStore
NameID := LocalNameStore.NewID(Name, ParentID, Search) ;
AlertIfNotEqual(AlertLogIDVar(NumItems), NameID, NumItems, "ScoreboardPkg: Index of LocalNameStore /= ScoreboardID") ;
return ScoreboardIDType'(ID => NumItems) ;
end if ;
end function LocalNewID ;
------------------------------------------------------------
-- Used by Scoreboard Store
impure function NewID (
Name : String ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIDType is
------------------------------------------------------------
variable ResolvedSearch : NameSearchType ;
variable ResolvedPrintParent : AlertLogPrintParentType ;
begin
CalledNewID := TRUE ;
SetPrintIndex(FALSE) ; -- historic, but needed
ResolvedSearch := ResolveSearch (ParentID /= OSVVM_SCOREBOARD_ALERTLOG_ID, Search) ;
ResolvedPrintParent := ResolvePrintParent(ParentID /= OSVVM_SCOREBOARD_ALERTLOG_ID, PrintParent) ;
return LocalNewID(Name, ParentID, ReportMode, ResolvedSearch, ResolvedPrintParent) ;
end function NewID ;
------------------------------------------------------------
-- Vector. Assumes valid range (done by NewID)
impure function LocalNewID (
Name : String ;
X : integer_vector ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIDArrayType is
------------------------------------------------------------
variable Result : ScoreboardIDArrayType(X(X'left) to X(X'right)) ;
variable ResolvedSearch : NameSearchType ;
variable ResolvedPrintParent : AlertLogPrintParentType ;
-- variable ArrayParentID : AlertLogIDType ;
begin
CalledNewID := TRUE ;
SetPrintIndex(FALSE) ; -- historic, but needed
ResolvedSearch := ResolveSearch (ParentID /= OSVVM_SCOREBOARD_ALERTLOG_ID, Search) ;
ResolvedPrintParent := ResolvePrintParent(ParentID /= OSVVM_SCOREBOARD_ALERTLOG_ID, PrintParent) ;
-- ArrayParentID := NewID(Name, ParentID, ReportMode, ResolvedPrintParent, CreateHierarchy => FALSE) ;
for i in Result'range loop
Result(i) := LocalNewID(Name & "(" & to_string(i) & ")", ParentID, ReportMode, ResolvedSearch, ResolvedPrintParent) ;
end loop ;
return Result ;
end function LocalNewID ;
------------------------------------------------------------
-- Vector: 1 to Size
impure function NewID (
Name : String ;
Size : positive ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIDArrayType is
------------------------------------------------------------
begin
return LocalNewID(Name, (1, Size) , ParentID, ReportMode, Search, PrintParent) ;
end function NewID ;
------------------------------------------------------------
-- Vector: X(X'Left) to X(X'Right)
impure function NewID (
Name : String ;
X : integer_vector ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIDArrayType is
------------------------------------------------------------
begin
AlertIf(ParentID, X'length /= 2, "ScoreboardPkg.NewID Array parameter X has " & to_string(X'length) & "dimensions. Required to be 2", FAILURE) ;
AlertIf(ParentID, X(X'Left) > X(X'right), "ScoreboardPkg.NewID Array parameter X(X'left): " & to_string(X'Left) & " must be <= X(X'right): " & to_string(X(X'right)), FAILURE) ;
return LocalNewID(Name, X, ParentID, ReportMode, Search, PrintParent) ;
end function NewID ;
------------------------------------------------------------
-- Matrix. Assumes valid indices (done by NewID)
impure function LocalNewID (
Name : String ;
X, Y : integer_vector ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIdMatrixType is
------------------------------------------------------------
variable Result : ScoreboardIdMatrixType(X(X'left) to X(X'right), Y(Y'left) to Y(Y'right)) ;
variable ResolvedSearch : NameSearchType ;
variable ResolvedPrintParent : AlertLogPrintParentType ;
-- variable ArrayParentID : AlertLogIDType ;
begin
CalledNewID := TRUE ;
SetPrintIndex(FALSE) ;
ResolvedSearch := ResolveSearch (ParentID /= OSVVM_SCOREBOARD_ALERTLOG_ID, Search) ;
ResolvedPrintParent := ResolvePrintParent(ParentID /= OSVVM_SCOREBOARD_ALERTLOG_ID, PrintParent) ;
-- ArrayParentID := NewID(Name, ParentID, ReportMode, ResolvedPrintParent, CreateHierarchy => FALSE) ;
for i in X(X'left) to X(X'right) loop
for j in Y(Y'left) to Y(Y'right) loop
Result(i, j) := LocalNewID(Name & "(" & to_string(i) & ", " & to_string(j) & ")", ParentID, ReportMode, ResolvedSearch, ResolvedPrintParent) ;
end loop ;
end loop ;
return Result ;
end function LocalNewID ;
------------------------------------------------------------
-- Matrix: 1 to X, 1 to Y
impure function NewID (
Name : String ;
X, Y : positive ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIdMatrixType is
------------------------------------------------------------
begin
return LocalNewID(Name, (1,X), (1,Y), ParentID, ReportMode, Search, PrintParent) ;
end function NewID ;
------------------------------------------------------------
-- Matrix: X(X'Left) to X(X'Right), Y(Y'Left) to Y(Y'Right)
impure function NewID (
Name : String ;
X, Y : integer_vector ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIdMatrixType is
------------------------------------------------------------
begin
AlertIf(ParentID, X'length /= 2, "ScoreboardPkg.NewID Matrix parameter X has " & to_string(X'length) & "dimensions. Required to be 2", FAILURE) ;
AlertIf(ParentID, Y'length /= 2, "ScoreboardPkg.NewID Matrix parameter Y has " & to_string(Y'length) & "dimensions. Required to be 2", FAILURE) ;
AlertIf(ParentID, X(X'Left) > X(X'right), "ScoreboardPkg.NewID Matrix parameter X(X'left): " & to_string(X'Left) & " must be <= X(X'right): " & to_string(X(X'right)), FAILURE) ;
AlertIf(ParentID, Y(Y'Left) > Y(Y'right), "ScoreboardPkg.NewID Matrix parameter Y(Y'left): " & to_string(Y'Left) & " must be <= Y(Y'right): " & to_string(Y(Y'right)), FAILURE) ;
return LocalNewID(Name, X, Y, ParentID, ReportMode, Search, PrintParent) ;
end function NewID ;
------------------------------------------------------------
procedure SetName (Name : String) is
------------------------------------------------------------
begin
NameVar.Set(Name) ;
end procedure SetName ;
------------------------------------------------------------
impure function SetName (Name : String) return string is
------------------------------------------------------------
begin
NameVar.Set(Name) ;
return Name ;
end function SetName ;
------------------------------------------------------------
impure function GetName (DefaultName : string := "Scoreboard") return string is
------------------------------------------------------------
begin
return NameVar.Get(DefaultName) ;
end function GetName ;
------------------------------------------------------------
procedure SetReportMode (ReportModeIn : ScoreboardReportType) is
------------------------------------------------------------
begin
ReportModeVar := ReportModeIn ;
if ReportModeVar = REPORT_ALL then
Alert(OSVVM_SCOREBOARD_ALERTLOG_ID, "ScoreboardGenericPkg.SetReportMode: To turn off REPORT_ALL, use osvvm.AlertLogPkg.SetLogEnable(PASSED, FALSE)", WARNING) ;
for i in AlertLogIDVar'range loop
SetLogEnable(AlertLogIDVar(i), PASSED, TRUE) ;
end loop ;
end if ;
if ReportModeVar = REPORT_NONE then
Alert(OSVVM_SCOREBOARD_ALERTLOG_ID, "ScoreboardGenericPkg.SetReportMode: ReportMode REPORT_NONE has been deprecated and will be removed in next revision. Please contact OSVVM architect Jim Lewis if you need this capability.", WARNING) ;
end if ;
end procedure SetReportMode ;
------------------------------------------------------------
impure function GetReportMode return ScoreboardReportType is
------------------------------------------------------------
begin
return ReportModeVar ;
end function GetReportMode ;
------------------------------------------------------------
procedure SetArrayIndex(L, R : integer) is
------------------------------------------------------------
variable OldHeadPointer, OldTailPointer, OldPopListPointer : ListArrayPointerType ;
variable OldErrCnt, OldDropCount, OldItemNumber, OldPopCount, OldCheckCount : IntegerArrayPointerType ;
variable OldAlertLogIDVar : AlertLogIDArrayPointerType ;
variable Min, Max, Len, OldLen, OldMax : integer ;
begin
Min := minimum(L, R) ;
Max := maximum(L, R) ;
OldLen := ArrayLengthVar ;
OldMax := Min + ArrayLengthVar - 1 ;
Len := Max - Min + 1 ;
ArrayLengthVar := Len ;
if Len >= OldLen then
FirstIndexVar := Min ;
OldHeadPointer := HeadPointer ;
HeadPointer := new ListArrayType(Min to Max) ;
if OldHeadPointer /= NULL then
HeadPointer(Min to OldMax) := OldHeadPointer.all ; -- (OldHeadPointer'range) ;
Deallocate(OldHeadPointer) ;
end if ;
OldTailPointer := TailPointer ;
TailPointer := new ListArrayType(Min to Max) ;
if OldTailPointer /= NULL then
TailPointer(Min to OldMax) := OldTailPointer.all ;
Deallocate(OldTailPointer) ;
end if ;
OldPopListPointer := PopListPointer ;
PopListPointer := new ListArrayType(Min to Max) ;
if OldPopListPointer /= NULL then
PopListPointer(Min to OldMax) := OldPopListPointer.all ;
Deallocate(OldPopListPointer) ;
end if ;
OldErrCnt := ErrCntVar ;
ErrCntVar := new IntegerArrayType'(Min to Max => 0) ;
if OldErrCnt /= NULL then
ErrCntVar(Min to OldMax) := OldErrCnt.all ;
Deallocate(OldErrCnt) ;
end if ;
OldDropCount := DropCountVar ;
DropCountVar := new IntegerArrayType'(Min to Max => 0) ;
if OldDropCount /= NULL then
DropCountVar(Min to OldMax) := OldDropCount.all ;
Deallocate(OldDropCount) ;
end if ;
OldItemNumber := ItemNumberVar ;
ItemNumberVar := new IntegerArrayType'(Min to Max => 0) ;
if OldItemNumber /= NULL then
ItemNumberVar(Min to OldMax) := OldItemNumber.all ;
Deallocate(OldItemNumber) ;
end if ;
OldPopCount := PopCountVar ;
PopCountVar := new IntegerArrayType'(Min to Max => 0) ;
if OldPopCount /= NULL then
PopCountVar(Min to OldMax) := OldPopCount.all ;
Deallocate(OldPopCount) ;
end if ;
OldCheckCount := CheckCountVar ;
CheckCountVar := new IntegerArrayType'(Min to Max => 0) ;
if OldCheckCount /= NULL then
CheckCountVar(Min to OldMax) := OldCheckCount.all ;
Deallocate(OldCheckCount) ;
end if ;
OldAlertLogIDVar := AlertLogIDVar ;
AlertLogIDVar := new AlertLogIDArrayType'(Min to Max => OSVVM_SCOREBOARD_ALERTLOG_ID) ;
if OldAlertLogIDVar /= NULL then
AlertLogIDVar(Min to OldMax) := OldAlertLogIDVar.all ;
Deallocate(OldAlertLogIDVar) ;
end if ;
elsif Len < OldLen then
report "ScoreboardGenericPkg: SetArrayIndex, new array Length <= current array length"
severity failure ;
end if ;
end procedure SetArrayIndex ;
------------------------------------------------------------
procedure SetArrayIndex(R : natural) is
------------------------------------------------------------
begin
SetArrayIndex(1, R) ;
end procedure SetArrayIndex ;
------------------------------------------------------------
procedure Deallocate is
------------------------------------------------------------
variable CurListPtr, LastListPtr : ListPointerType ;
begin
for Index in HeadPointer'range loop
-- Deallocate contents in the scoreboards
CurListPtr := HeadPointer(Index) ;
while CurListPtr /= Null loop
deallocate(CurListPtr.TagPtr) ;
deallocate(CurListPtr.ExpectedPtr) ;
LastListPtr := CurListPtr ;
CurListPtr := CurListPtr.NextPtr ;
Deallocate(LastListPtr) ;
end loop ;
end loop ;
for Index in PopListPointer'range loop
-- Deallocate PopListPointer - only has single element
CurListPtr := PopListPointer(Index) ;
if CurListPtr /= NULL then
deallocate(CurListPtr.TagPtr) ;
deallocate(CurListPtr.ExpectedPtr) ;
deallocate(CurListPtr) ;
end if ;
end loop ;
-- Deallocate arrays of pointers
Deallocate(HeadPointer) ;
Deallocate(TailPointer) ;
Deallocate(PopListPointer) ;
-- Deallocate supporting arrays
Deallocate(ErrCntVar) ;
Deallocate(DropCountVar) ;
Deallocate(ItemNumberVar) ;
Deallocate(PopCountVar) ;
Deallocate(CheckCountVar) ;
Deallocate(AlertLogIDVar) ;
-- Deallocate NameVar - NamePType
NameVar.Deallocate ;
ArrayLengthVar := 0 ;
NumItems := 0 ;
CalledNewID := FALSE ;
end procedure Deallocate ;
------------------------------------------------------------
-- Construct initial data structure
procedure Initialize is
------------------------------------------------------------
begin
SetArrayIndex(1, 1) ;
end procedure Initialize ;
------------------------------------------------------------
impure function GetArrayIndex return integer_vector is
------------------------------------------------------------
begin
return (1 => HeadPointer'left, 2 => HeadPointer'right) ;
end function GetArrayIndex ;
------------------------------------------------------------
impure function GetArrayLength return natural is
------------------------------------------------------------
begin
return ArrayLengthVar ; -- HeadPointer'length ;
end function GetArrayLength ;
------------------------------------------------------------
procedure SetAlertLogID (Index : Integer ; A : AlertLogIDType) is
------------------------------------------------------------
begin
AlertLogIDVar(Index) := A ;
end procedure SetAlertLogID ;
------------------------------------------------------------
procedure SetAlertLogID (A : AlertLogIDType) is
------------------------------------------------------------
begin
AlertLogIDVar(FirstIndexVar) := A ;
end procedure SetAlertLogID ;
------------------------------------------------------------
procedure SetAlertLogID(Index : Integer; Name : string; ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID; CreateHierarchy : Boolean := TRUE; DoNotReport : Boolean := FALSE) is
------------------------------------------------------------
variable ReportMode : AlertLogReportModeType ;
begin
ReportMode := ENABLED when not DoNotReport else DISABLED ;
AlertLogIDVar(Index) := NewID(Name, ParentID, ReportMode => ReportMode, PrintParent => PRINT_NAME, CreateHierarchy => CreateHierarchy) ;
end procedure SetAlertLogID ;
------------------------------------------------------------
procedure SetAlertLogID(Name : string; ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID; CreateHierarchy : Boolean := TRUE; DoNotReport : Boolean := FALSE) is
------------------------------------------------------------
variable ReportMode : AlertLogReportModeType ;
begin
ReportMode := ENABLED when not DoNotReport else DISABLED ;
AlertLogIDVar(FirstIndexVar) := NewID(Name, ParentID, ReportMode => ReportMode, PrintParent => PRINT_NAME, CreateHierarchy => CreateHierarchy) ;
end procedure SetAlertLogID ;
------------------------------------------------------------
impure function GetAlertLogID(Index : Integer) return AlertLogIDType is
------------------------------------------------------------
begin
return AlertLogIDVar(Index) ;
end function GetAlertLogID ;
------------------------------------------------------------
impure function GetAlertLogID return AlertLogIDType is
------------------------------------------------------------
begin
return AlertLogIDVar(FirstIndexVar) ;
end function GetAlertLogID ;
------------------------------------------------------------
impure function LocalOutOfRange(
------------------------------------------------------------
constant Index : in integer ;
constant Name : in string
) return boolean is
begin
return AlertIf(OSVVM_SCOREBOARD_ALERTLOG_ID, Index < HeadPointer'Low or Index > HeadPointer'High,
GetName & " " & Name & " Index: " & to_string(Index) &
"is not in the range (" & to_string(HeadPointer'Low) &
"to " & to_string(HeadPointer'High) & ")",
FAILURE ) ;
end function LocalOutOfRange ;
------------------------------------------------------------
procedure LocalPush (
------------------------------------------------------------
constant Index : in integer ;
constant Tag : in string ;
constant Item : in ExpectedType
) is
variable ExpectedPtr : ExpectedPointerType ;
variable TagPtr : line ;
begin
if LocalOutOfRange(Index, "Push") then
return ; -- error reporting in LocalOutOfRange
end if ;
ItemNumberVar(Index) := ItemNumberVar(Index) + 1 ;
ExpectedPtr := new ExpectedType'(Item) ;
TagPtr := new string'(Tag) ;
if HeadPointer(Index) = NULL then
-- 2015.05: allocation using ListTtype'(...) in a protected type does not work in some simulators
-- HeadPointer(Index) := new ListType'(ItemNumberVar(Index), TagPtr, ExpectedPtr, NULL) ;
HeadPointer(Index) := new ListType ;
HeadPointer(Index).ItemNumber := ItemNumberVar(Index) ;
HeadPointer(Index).TagPtr := TagPtr ;
HeadPointer(Index).ExpectedPtr := ExpectedPtr ;
HeadPointer(Index).NextPtr := NULL ;
TailPointer(Index) := HeadPointer(Index) ;
else
-- 2015.05: allocation using ListTtype'(...) in a protected type does not work in some simulators
-- TailPointer(Index).NextPtr := new ListType'(ItemNumberVar(Index), TagPtr, ExpectedPtr, NULL) ;
TailPointer(Index).NextPtr := new ListType ;
TailPointer(Index).NextPtr.ItemNumber := ItemNumberVar(Index) ;
TailPointer(Index).NextPtr.TagPtr := TagPtr ;
TailPointer(Index).NextPtr.ExpectedPtr := ExpectedPtr ;
TailPointer(Index).NextPtr.NextPtr := NULL ;
TailPointer(Index) := TailPointer(Index).NextPtr ;
end if ;
end procedure LocalPush ;
------------------------------------------------------------
-- Array of Tagged Scoreboards
procedure Push (
------------------------------------------------------------
constant Index : in integer ;
constant Tag : in string ;
constant Item : in ExpectedType
) is
variable ExpectedPtr : ExpectedPointerType ;
variable TagPtr : line ;
begin
if LocalOutOfRange(Index, "Push") then
return ; -- error reporting in LocalOutOfRange
end if ;
LocalPush(Index, Tag, Item) ;
end procedure Push ;
------------------------------------------------------------
-- Array of Scoreboards, no tag
procedure Push (
------------------------------------------------------------
constant Index : in integer ;
constant Item : in ExpectedType
) is
begin
if LocalOutOfRange(Index, "Push") then
return ; -- error reporting in LocalOutOfRange
end if ;
LocalPush(Index, "", Item) ;
end procedure Push ;
------------------------------------------------------------
-- Simple Tagged Scoreboard
procedure Push (
------------------------------------------------------------
constant Tag : in string ;
constant Item : in ExpectedType
) is
begin
LocalPush(FirstIndexVar, Tag, Item) ;
end procedure Push ;
------------------------------------------------------------
-- Simple Scoreboard, no tag
procedure Push (Item : in ExpectedType) is
------------------------------------------------------------
begin
LocalPush(FirstIndexVar, "", Item) ;
end procedure Push ;
------------------------------------------------------------
-- Array of Tagged Scoreboards
impure function Push (
------------------------------------------------------------
constant Index : in integer ;
constant Tag : in string ;
constant Item : in ExpectedType
) return ExpectedType is
begin
if LocalOutOfRange(Index, "Push") then
return Item ; -- error reporting in LocalOutOfRange
end if ;
LocalPush(Index, Tag, Item) ;
return Item ;
end function Push ;
------------------------------------------------------------
-- Array of Scoreboards, no tag
impure function Push (
------------------------------------------------------------
constant Index : in integer ;
constant Item : in ExpectedType
) return ExpectedType is
begin
if LocalOutOfRange(Index, "Push") then
return Item ; -- error reporting in LocalOutOfRange
end if ;
LocalPush(Index, "", Item) ;
return Item ;
end function Push ;
------------------------------------------------------------
-- Simple Tagged Scoreboard
impure function Push (
------------------------------------------------------------
constant Tag : in string ;
constant Item : in ExpectedType
) return ExpectedType is
begin
LocalPush(FirstIndexVar, Tag, Item) ;
return Item ;
end function Push ;
------------------------------------------------------------
-- Simple Scoreboard, no tag
impure function Push (Item : ExpectedType) return ExpectedType is
------------------------------------------------------------
begin
LocalPush(FirstIndexVar, "", Item) ;
return Item ;
end function Push ;
------------------------------------------------------------
-- Local Only
-- Pops highest element matching Tag into PopListPointer(Index)
procedure LocalPop (Index : integer ; Tag : string; Name : string) is
------------------------------------------------------------
variable CurPtr : ListPointerType ;
begin
if LocalOutOfRange(Index, "Pop/Check") then
return ; -- error reporting in LocalOutOfRange
end if ;
if HeadPointer(Index) = NULL then
ErrCntVar(Index) := ErrCntVar(Index) + 1 ;
Alert(AlertLogIDVar(Index), GetName & " Empty during " & Name, FAILURE) ;
return ;
end if ;
PopCountVar(Index) := PopCountVar(Index) + 1 ;
-- deallocate previous pointer
if PopListPointer(Index) /= NULL then
deallocate(PopListPointer(Index).TagPtr) ;
deallocate(PopListPointer(Index).ExpectedPtr) ;
deallocate(PopListPointer(Index)) ;
end if ;
-- Descend to find Tag field and extract
CurPtr := HeadPointer(Index) ;
if CurPtr.TagPtr.all = Tag then
-- Non-tagged scoreboards find this one.
PopListPointer(Index) := HeadPointer(Index) ;
HeadPointer(Index) := HeadPointer(Index).NextPtr ;
else
loop
if CurPtr.NextPtr = NULL then
ErrCntVar(Index) := ErrCntVar(Index) + 1 ;
Alert(AlertLogIDVar(Index), GetName & " Pop/Check (" & Name & "), tag: " & Tag & " not found", FAILURE) ;
exit ;
elsif CurPtr.NextPtr.TagPtr.all = Tag then
PopListPointer(Index) := CurPtr.NextPtr ;
CurPtr.NextPtr := CurPtr.NextPtr.NextPtr ;
if CurPtr.NextPtr = NULL then
TailPointer(Index) := CurPtr ;
end if ;
exit ;
else
CurPtr := CurPtr.NextPtr ;
end if ;
end loop ;
end if ;
end procedure LocalPop ;
------------------------------------------------------------
-- Local Only
procedure LocalCheck (
------------------------------------------------------------
constant Index : in integer ;
constant ActualData : in ActualType ;
variable FoundError : inout boolean ;
constant ExpectedInFIFO : in boolean := TRUE
) is
variable ExpectedPtr : ExpectedPointerType ;
variable CurrentItem : integer ;
variable WriteBuf : line ;
variable PassedFlagEnabled : boolean ;
begin
CheckCountVar(Index) := CheckCountVar(Index) + 1 ;
ExpectedPtr := PopListPointer(Index).ExpectedPtr ;
CurrentItem := PopListPointer(Index).ItemNumber ;
PassedFlagEnabled := GetLogEnable(AlertLogIDVar(Index), PASSED) ;
if not Match(ActualData, ExpectedPtr.all) then
ErrCntVar(Index) := ErrCntVar(Index) + 1 ;
FoundError := TRUE ;
IncAffirmCount(AlertLogIDVar(Index)) ;
else
FoundError := FALSE ;
if not PassedFlagEnabled then
IncAffirmPassedCount(AlertLogIDVar(Index)) ;
end if ;
end if ;
-- IncAffirmCount(AlertLogIDVar(Index)) ;
-- if FoundError or ReportModeVar = REPORT_ALL then
if FoundError or PassedFlagEnabled then
if AlertLogIDVar(Index) = OSVVM_SCOREBOARD_ALERTLOG_ID then
write(WriteBuf, GetName(DefaultName => "Scoreboard")) ;
else
write(WriteBuf, GetName(DefaultName => "")) ;
end if ;
if ArrayLengthVar > 1 and PrintIndexVar then
write(WriteBuf, " (" & to_string(Index) & ") ") ;
end if ;
if ExpectedInFIFO then
write(WriteBuf, " Received: " & actual_to_string(ActualData)) ;
if FoundError then
write(WriteBuf, " Expected: " & expected_to_string(ExpectedPtr.all)) ;
end if ;
else
write(WriteBuf, " Received: " & expected_to_string(ExpectedPtr.all)) ;
if FoundError then
write(WriteBuf, " Expected: " & actual_to_string(ActualData)) ;
end if ;
end if ;
if PopListPointer(Index).TagPtr.all /= "" then
write(WriteBuf, " Tag: " & PopListPointer(Index).TagPtr.all) ;
end if;
write(WriteBuf, " Item Number: " & to_string(CurrentItem)) ;
if FoundError then
if ReportModeVar /= REPORT_NONE then
-- Affirmation Failed
Alert(AlertLogIDVar(Index), WriteBuf.all, ERROR) ;
else
-- Affirmation Failed, but silent, unless in DEBUG mode
Log(AlertLogIDVar(Index), "ERROR " & WriteBuf.all, DEBUG) ;
IncAlertCount(AlertLogIDVar(Index)) ; -- Silent Counted Alert
end if ;
else
-- Affirmation passed, PASSED flag increments AffirmCount
Log(AlertLogIDVar(Index), WriteBuf.all, PASSED) ;
end if ;
deallocate(WriteBuf) ;
end if ;
end procedure LocalCheck ;
------------------------------------------------------------
-- Array of Tagged Scoreboards
procedure Check (
------------------------------------------------------------
constant Index : in integer ;
constant Tag : in string ;
constant ActualData : in ActualType
) is
variable FoundError : boolean ;
begin
if LocalOutOfRange(Index, "Check") then
return ; -- error reporting in LocalOutOfRange
end if ;
LocalPop(Index, Tag, "Check") ;
LocalCheck(Index, ActualData, FoundError) ;
end procedure Check ;
------------------------------------------------------------
-- Array of Scoreboards, no tag
procedure Check (
------------------------------------------------------------
constant Index : in integer ;
constant ActualData : in ActualType
) is
variable FoundError : boolean ;
begin
if LocalOutOfRange(Index, "Check") then
return ; -- error reporting in LocalOutOfRange
end if ;
LocalPop(Index, "", "Check") ;
LocalCheck(Index, ActualData, FoundError) ;
end procedure Check ;
------------------------------------------------------------
-- Simple Tagged Scoreboard
procedure Check (
------------------------------------------------------------
constant Tag : in string ;
constant ActualData : in ActualType
) is
variable FoundError : boolean ;
begin
LocalPop(FirstIndexVar, Tag, "Check") ;
LocalCheck(FirstIndexVar, ActualData, FoundError) ;
end procedure Check ;
------------------------------------------------------------
-- Simple Scoreboard, no tag
procedure Check (ActualData : ActualType) is
------------------------------------------------------------
variable FoundError : boolean ;
begin
LocalPop(FirstIndexVar, "", "Check") ;
LocalCheck(FirstIndexVar, ActualData, FoundError) ;
end procedure Check ;
------------------------------------------------------------
-- Array of Tagged Scoreboards
impure function Check (
------------------------------------------------------------
constant Index : in integer ;
constant Tag : in string ;
constant ActualData : in ActualType
) return boolean is
variable FoundError : boolean ;
begin
if LocalOutOfRange(Index, "Function Check") then
return FALSE ; -- error reporting in LocalOutOfRange
end if ;
LocalPop(Index, Tag, "Check") ;
LocalCheck(Index, ActualData, FoundError) ;
return not FoundError ;
end function Check ;
------------------------------------------------------------
-- Array of Scoreboards, no tag
impure function Check (
------------------------------------------------------------
constant Index : in integer ;
constant ActualData : in ActualType
) return boolean is
variable FoundError : boolean ;
begin
if LocalOutOfRange(Index, "Function Check") then
return FALSE ; -- error reporting in LocalOutOfRange
end if ;
LocalPop(Index, "", "Check") ;
LocalCheck(Index, ActualData, FoundError) ;
return not FoundError ;
end function Check ;
------------------------------------------------------------
-- Simple Tagged Scoreboard
impure function Check (
------------------------------------------------------------
constant Tag : in string ;
constant ActualData : in ActualType
) return boolean is
variable FoundError : boolean ;
begin
LocalPop(FirstIndexVar, Tag, "Check") ;
LocalCheck(FirstIndexVar, ActualData, FoundError) ;
return not FoundError ;
end function Check ;
------------------------------------------------------------
-- Simple Scoreboard, no tag
impure function Check (ActualData : ActualType) return boolean is
------------------------------------------------------------
variable FoundError : boolean ;
begin
LocalPop(FirstIndexVar, "", "Check") ;
LocalCheck(FirstIndexVar, ActualData, FoundError) ;
return not FoundError ;
end function Check ;
------------------------------------------------------------
-- Scoreboard Store. Index. Tag.
impure function CheckExpected (
------------------------------------------------------------
constant Index : in integer ;
constant Tag : in string ;
constant ExpectedData : in ActualType
) return boolean is
variable FoundError : boolean ;
begin
if LocalOutOfRange(Index, "Function Check") then
return FALSE ; -- error reporting in LocalOutOfRange
end if ;
LocalPop(Index, Tag, "Check") ;
LocalCheck(Index, ExpectedData, FoundError, ExpectedInFIFO => FALSE) ;
return not FoundError ;
end function CheckExpected ;
------------------------------------------------------------
-- Array of Tagged Scoreboards
procedure Pop (
------------------------------------------------------------
constant Index : in integer ;
constant Tag : in string ;
variable Item : out ExpectedType
) is
begin
if LocalOutOfRange(Index, "Pop") then
return ; -- error reporting in LocalOutOfRange
end if ;
LocalPop(Index, Tag, "Pop") ;
Item := PopListPointer(Index).ExpectedPtr.all ;
end procedure Pop ;
------------------------------------------------------------
-- Array of Scoreboards, no tag
procedure Pop (
------------------------------------------------------------
constant Index : in integer ;
variable Item : out ExpectedType
) is
begin
if LocalOutOfRange(Index, "Pop") then
return ; -- error reporting in LocalOutOfRange
end if ;
LocalPop(Index, "", "Pop") ;
Item := PopListPointer(Index).ExpectedPtr.all ;
end procedure Pop ;
------------------------------------------------------------
-- Simple Tagged Scoreboard
procedure Pop (
------------------------------------------------------------
constant Tag : in string ;
variable Item : out ExpectedType
) is
begin
LocalPop(FirstIndexVar, Tag, "Pop") ;
Item := PopListPointer(FirstIndexVar).ExpectedPtr.all ;
end procedure Pop ;
------------------------------------------------------------
-- Simple Scoreboard, no tag
procedure Pop (variable Item : out ExpectedType) is
------------------------------------------------------------
begin
LocalPop(FirstIndexVar, "", "Pop") ;
Item := PopListPointer(FirstIndexVar).ExpectedPtr.all ;
end procedure Pop ;
------------------------------------------------------------
-- Array of Tagged Scoreboards
impure function Pop (
------------------------------------------------------------
constant Index : in integer ;
constant Tag : in string
) return ExpectedType is
begin
if LocalOutOfRange(Index, "Pop") then
-- error reporting in LocalOutOfRange
return PopListPointer(FirstIndexVar).ExpectedPtr.all ;
end if ;
LocalPop(Index, Tag, "Pop") ;
return PopListPointer(Index).ExpectedPtr.all ;
end function Pop ;
------------------------------------------------------------
-- Array of Scoreboards, no tag
impure function Pop (Index : integer) return ExpectedType is
------------------------------------------------------------
begin
if LocalOutOfRange(Index, "Pop") then
-- error reporting in LocalOutOfRange
return PopListPointer(FirstIndexVar).ExpectedPtr.all ;
end if ;
LocalPop(Index, "", "Pop") ;
return PopListPointer(Index).ExpectedPtr.all ;
end function Pop ;
------------------------------------------------------------
-- Simple Tagged Scoreboard
impure function Pop (
------------------------------------------------------------
constant Tag : in string
) return ExpectedType is
begin
LocalPop(FirstIndexVar, Tag, "Pop") ;
return PopListPointer(FirstIndexVar).ExpectedPtr.all ;
end function Pop ;
------------------------------------------------------------
-- Simple Scoreboard, no tag
impure function Pop return ExpectedType is
------------------------------------------------------------
begin
LocalPop(FirstIndexVar, "", "Pop") ;
return PopListPointer(FirstIndexVar).ExpectedPtr.all ;
end function Pop ;
------------------------------------------------------------
-- Local Only similar to LocalPop
-- Returns a pointer to the highest element matching Tag
impure function LocalPeek (Index : integer ; Tag : string) return ListPointerType is
------------------------------------------------------------
variable CurPtr : ListPointerType ;
begin
--!! LocalPeek does this, but so do each of the indexed calls
--!! if LocalOutOfRange(Index, "Peek") then
--!! return NULL ; -- error reporting in LocalOutOfRange
--!! end if ;
if HeadPointer(Index) = NULL then
ErrCntVar(Index) := ErrCntVar(Index) + 1 ;
Alert(AlertLogIDVar(Index), GetName & " Empty during Peek", FAILURE) ;
return NULL ;
end if ;
-- Descend to find Tag field and extract
CurPtr := HeadPointer(Index) ;
if CurPtr.TagPtr.all = Tag then
-- Non-tagged scoreboards find this one.
return CurPtr ;
else
loop
if CurPtr.NextPtr = NULL then
ErrCntVar(Index) := ErrCntVar(Index) + 1 ;
Alert(AlertLogIDVar(Index), GetName & " Peek, tag: " & Tag & " not found", FAILURE) ;
return NULL ;
elsif CurPtr.NextPtr.TagPtr.all = Tag then
return CurPtr ;
else
CurPtr := CurPtr.NextPtr ;
end if ;
end loop ;
end if ;
end function LocalPeek ;
------------------------------------------------------------
-- Array of Tagged Scoreboards
procedure Peek (
------------------------------------------------------------
constant Index : in integer ;
constant Tag : in string ;
variable Item : out ExpectedType
) is
variable CurPtr : ListPointerType ;
begin
if LocalOutOfRange(Index, "Peek") then
return ; -- error reporting in LocalOutOfRange
end if ;
CurPtr := LocalPeek(Index, Tag) ;
if CurPtr /= NULL then
Item := CurPtr.ExpectedPtr.all ;
end if ;
end procedure Peek ;
------------------------------------------------------------
-- Array of Scoreboards, no tag
procedure Peek (
------------------------------------------------------------
constant Index : in integer ;
variable Item : out ExpectedType
) is
variable CurPtr : ListPointerType ;
begin
if LocalOutOfRange(Index, "Peek") then
return ; -- error reporting in LocalOutOfRange
end if ;
CurPtr := LocalPeek(Index, "") ;
if CurPtr /= NULL then
Item := CurPtr.ExpectedPtr.all ;
end if ;
end procedure Peek ;
------------------------------------------------------------
-- Simple Tagged Scoreboard
procedure Peek (
------------------------------------------------------------
constant Tag : in string ;
variable Item : out ExpectedType
) is
variable CurPtr : ListPointerType ;
begin
CurPtr := LocalPeek(FirstIndexVar, Tag) ;
if CurPtr /= NULL then
Item := CurPtr.ExpectedPtr.all ;
end if ;
end procedure Peek ;
------------------------------------------------------------
-- Simple Scoreboard, no tag
procedure Peek (variable Item : out ExpectedType) is
------------------------------------------------------------
variable CurPtr : ListPointerType ;
begin
CurPtr := LocalPeek(FirstIndexVar, "") ;
if CurPtr /= NULL then
Item := CurPtr.ExpectedPtr.all ;
end if ;
end procedure Peek ;
------------------------------------------------------------
-- Array of Tagged Scoreboards
impure function Peek (
------------------------------------------------------------
constant Index : in integer ;
constant Tag : in string
) return ExpectedType is
variable CurPtr : ListPointerType ;
begin
if LocalOutOfRange(Index, "Peek") then
-- error reporting in LocalOutOfRange
return PopListPointer(FirstIndexVar).ExpectedPtr.all ;
end if ;
CurPtr := LocalPeek(Index, Tag) ;
if CurPtr /= NULL then
return CurPtr.ExpectedPtr.all ;
else
-- Already issued failure, continuing for debug only
return PopListPointer(FirstIndexVar).ExpectedPtr.all ;
end if ;
end function Peek ;
------------------------------------------------------------
-- Array of Scoreboards, no tag
impure function Peek (Index : integer) return ExpectedType is
------------------------------------------------------------
variable CurPtr : ListPointerType ;
begin
if LocalOutOfRange(Index, "Peek") then
-- error reporting in LocalOutOfRange
return PopListPointer(FirstIndexVar).ExpectedPtr.all ;
end if ;
CurPtr := LocalPeek(Index, "") ;
if CurPtr /= NULL then
return CurPtr.ExpectedPtr.all ;
else
-- Already issued failure, continuing for debug only
return PopListPointer(FirstIndexVar).ExpectedPtr.all ;
end if ;
end function Peek ;
------------------------------------------------------------
-- Simple Tagged Scoreboard
impure function Peek (
------------------------------------------------------------
constant Tag : in string
) return ExpectedType is
variable CurPtr : ListPointerType ;
begin
CurPtr := LocalPeek(FirstIndexVar, Tag) ;
if CurPtr /= NULL then
return CurPtr.ExpectedPtr.all ;
else
-- Already issued failure, continuing for debug only
return PopListPointer(FirstIndexVar).ExpectedPtr.all ;
end if ;
end function Peek ;
------------------------------------------------------------
-- Simple Scoreboard, no tag
impure function Peek return ExpectedType is
------------------------------------------------------------
variable CurPtr : ListPointerType ;
begin
CurPtr := LocalPeek(FirstIndexVar, "") ;
if CurPtr /= NULL then
return CurPtr.ExpectedPtr.all ;
else
-- Already issued failure, continuing for debug only
return PopListPointer(FirstIndexVar).ExpectedPtr.all ;
end if ;
end function Peek ;
------------------------------------------------------------
-- Array of Tagged Scoreboards
impure function Empty (Index : integer; Tag : String) return boolean is
------------------------------------------------------------
variable CurPtr : ListPointerType ;
begin
CurPtr := HeadPointer(Index) ;
while CurPtr /= NULL loop
if CurPtr.TagPtr.all = Tag then
return FALSE ; -- Found Tag
end if ;
CurPtr := CurPtr.NextPtr ;
end loop ;
return TRUE ; -- Tag not found
end function Empty ;
------------------------------------------------------------
-- Array of Scoreboards, no tag
impure function Empty (Index : integer) return boolean is
------------------------------------------------------------
begin
return HeadPointer(Index) = NULL ;
end function Empty ;
------------------------------------------------------------
-- Simple Tagged Scoreboard
impure function Empty (Tag : String) return boolean is
------------------------------------------------------------
variable CurPtr : ListPointerType ;
begin
return Empty(FirstIndexVar, Tag) ;
end function Empty ;
------------------------------------------------------------
-- Simple Scoreboard, no tag
impure function Empty return boolean is
------------------------------------------------------------
begin
return HeadPointer(FirstIndexVar) = NULL ;
end function Empty ;
------------------------------------------------------------
procedure CheckFinish (
------------------------------------------------------------
Index : integer ;
FinishCheckCount : integer ;
FinishEmpty : boolean
) is
variable EmptyError : Boolean ;
variable WriteBuf : line ;
begin
if AlertLogIDVar(Index) = OSVVM_SCOREBOARD_ALERTLOG_ID then
write(WriteBuf, GetName(DefaultName => "Scoreboard")) ;
else
write(WriteBuf, GetName(DefaultName => "")) ;
end if ;
if ArrayLengthVar > 1 then
if WriteBuf.all /= "" then
swrite(WriteBuf, " ") ;
end if ;
write(WriteBuf, "Index(" & to_string(Index) & "), ") ;
else
if WriteBuf.all /= "" then
swrite(WriteBuf, ", ") ;
end if ;
end if ;
if FinishEmpty then
AffirmIf(AlertLogIDVar(Index), Empty(Index), WriteBuf.all & "Checking Empty: " & to_string(Empty(Index)) &
" FinishEmpty: " & to_string(FinishEmpty)) ;
if not Empty(Index) then
-- Increment internal count on FinishEmpty Error
ErrCntVar(Index) := ErrCntVar(Index) + 1 ;
end if ;
end if ;
AffirmIf(AlertLogIDVar(Index), CheckCountVar(Index) >= FinishCheckCount, WriteBuf.all &
"Checking CheckCount: " & to_string(CheckCountVar(Index)) &
" >= Expected: " & to_string(FinishCheckCount)) ;
if not (CheckCountVar(Index) >= FinishCheckCount) then
-- Increment internal count on FinishCheckCount Error
ErrCntVar(Index) := ErrCntVar(Index) + 1 ;
end if ;
deallocate(WriteBuf) ;
end procedure CheckFinish ;
------------------------------------------------------------
procedure CheckFinish (
------------------------------------------------------------
FinishCheckCount : integer ;
FinishEmpty : boolean
) is
begin
for AlertLogID in AlertLogIDVar'range loop
CheckFinish(AlertLogID, FinishCheckCount, FinishEmpty) ;
end loop ;
end procedure CheckFinish ;
------------------------------------------------------------
impure function GetErrorCount (Index : integer) return integer is
------------------------------------------------------------
begin
return ErrCntVar(Index) ;
end function GetErrorCount ;
------------------------------------------------------------
impure function GetErrorCount return integer is
------------------------------------------------------------
variable TotalErrorCount : integer := 0 ;
begin
for Index in AlertLogIDVar'range loop
TotalErrorCount := TotalErrorCount + GetErrorCount(Index) ;
end loop ;
return TotalErrorCount ;
end function GetErrorCount ;
------------------------------------------------------------
procedure IncErrorCount (Index : integer) is
------------------------------------------------------------
begin
ErrCntVar(Index) := ErrCntVar(Index) + 1 ;
IncAlertCount(AlertLogIDVar(Index), ERROR) ;
end IncErrorCount ;
------------------------------------------------------------
procedure IncErrorCount is
------------------------------------------------------------
begin
ErrCntVar(FirstIndexVar) := ErrCntVar(FirstIndexVar) + 1 ;
IncAlertCount(AlertLogIDVar(FirstIndexVar), ERROR) ;
end IncErrorCount ;
------------------------------------------------------------
procedure SetErrorCountZero (Index : integer) is
------------------------------------------------------------
begin
ErrCntVar(Index) := 0;
end procedure SetErrorCountZero ;
------------------------------------------------------------
procedure SetErrorCountZero is
------------------------------------------------------------
begin
ErrCntVar(FirstIndexVar) := 0 ;
end procedure SetErrorCountZero ;
------------------------------------------------------------
procedure SetCheckCountZero (Index : integer) is
------------------------------------------------------------
begin
CheckCountVar(Index) := 0;
end procedure SetCheckCountZero ;
------------------------------------------------------------
procedure SetCheckCountZero is
------------------------------------------------------------
begin
CheckCountVar(FirstIndexVar) := 0;
end procedure SetCheckCountZero ;
------------------------------------------------------------
impure function GetItemCount (Index : integer) return integer is
------------------------------------------------------------
begin
return ItemNumberVar(Index) ;
end function GetItemCount ;
------------------------------------------------------------
impure function GetItemCount return integer is
------------------------------------------------------------
begin
return ItemNumberVar(FirstIndexVar) ;
end function GetItemCount ;
------------------------------------------------------------
impure function GetPushCount (Index : integer) return integer is
------------------------------------------------------------
begin
return ItemNumberVar(Index) ;
end function GetPushCount ;
------------------------------------------------------------
impure function GetPushCount return integer is
------------------------------------------------------------
begin
return ItemNumberVar(FirstIndexVar) ;
end function GetPushCount ;
------------------------------------------------------------
impure function GetPopCount (Index : integer) return integer is
------------------------------------------------------------
begin
return PopCountVar(Index) ;
end function GetPopCount ;
------------------------------------------------------------
impure function GetPopCount return integer is
------------------------------------------------------------
begin
return PopCountVar(FirstIndexVar) ;
end function GetPopCount ;
------------------------------------------------------------
impure function GetFifoCount (Index : integer) return integer is
------------------------------------------------------------
begin
return ItemNumberVar(Index) - PopCountVar(Index) - DropCountVar(Index) ;
end function GetFifoCount ;
------------------------------------------------------------
impure function GetFifoCount return integer is
------------------------------------------------------------
begin
return GetFifoCount(FirstIndexVar) ;
end function GetFifoCount ;
------------------------------------------------------------
impure function GetCheckCount (Index : integer) return integer is
------------------------------------------------------------
begin
return CheckCountVar(Index) ;
end function GetCheckCount ;
------------------------------------------------------------
impure function GetCheckCount return integer is
------------------------------------------------------------
begin
return CheckCountVar(FirstIndexVar) ;
end function GetCheckCount ;
------------------------------------------------------------
impure function GetDropCount (Index : integer) return integer is
------------------------------------------------------------
begin
return DropCountVar(Index) ;
end function GetDropCount ;
------------------------------------------------------------
impure function GetDropCount return integer is
------------------------------------------------------------
begin
return DropCountVar(FirstIndexVar) ;
end function GetDropCount ;
------------------------------------------------------------
procedure SetFinish (
------------------------------------------------------------
Index : integer ;
FCheckCount : integer ;
FEmpty : boolean := TRUE;
FStatus : boolean := TRUE
) is
begin
Alert(AlertLogIDVar(Index), "OSVVM.ScoreboardGenericPkg.SetFinish: Deprecated and removed. See CheckFinish", ERROR) ;
end procedure SetFinish ;
------------------------------------------------------------
procedure SetFinish (
------------------------------------------------------------
FCheckCount : integer ;
FEmpty : boolean := TRUE;
FStatus : boolean := TRUE
) is
begin
SetFinish(FirstIndexVar, FCheckCount, FEmpty, FStatus) ;
end procedure SetFinish ;
------------------------------------------------------------
-- Array of Tagged Scoreboards
-- Find Element with Matching Tag and ActualData
-- Returns integer'left if no match found
impure function Find (
------------------------------------------------------------
constant Index : in integer ;
constant Tag : in string;
constant ActualData : in ActualType
) return integer is
variable CurPtr : ListPointerType ;
begin
if LocalOutOfRange(Index, "Find") then
return integer'left ; -- error reporting in LocalOutOfRange
end if ;
CurPtr := HeadPointer(Index) ;
loop
if CurPtr = NULL then
-- Failed to find it
ErrCntVar(Index) := ErrCntVar(Index) + 1 ;
if Tag /= "" then
Alert(AlertLogIDVar(Index),
GetName & " Did not find Tag: " & Tag & " and Actual Data: " & actual_to_string(ActualData),
FAILURE ) ;
else
Alert(AlertLogIDVar(Index),
GetName & " Did not find Actual Data: " & actual_to_string(ActualData),
FAILURE ) ;
end if ;
return integer'left ;
elsif CurPtr.TagPtr.all = Tag and
Match(ActualData, CurPtr.ExpectedPtr.all) then
-- Found it. Return Index.
return CurPtr.ItemNumber ;
else -- Descend
CurPtr := CurPtr.NextPtr ;
end if ;
end loop ;
end function Find ;
------------------------------------------------------------
-- Array of Simple Scoreboards
-- Find Element with Matching ActualData
impure function Find (
------------------------------------------------------------
constant Index : in integer ;
constant ActualData : in ActualType
) return integer is
begin
return Find(Index, "", ActualData) ;
end function Find ;
------------------------------------------------------------
-- Tagged Scoreboard
-- Find Element with Matching ActualData
impure function Find (
------------------------------------------------------------
constant Tag : in string;
constant ActualData : in ActualType
) return integer is
begin
return Find(FirstIndexVar, Tag, ActualData) ;
end function Find ;
------------------------------------------------------------
-- Simple Scoreboard
-- Find Element with Matching ActualData
impure function Find (
------------------------------------------------------------
constant ActualData : in ActualType
) return integer is
begin
return Find(FirstIndexVar, "", ActualData) ;
end function Find ;
------------------------------------------------------------
-- Array of Tagged Scoreboards
-- Flush Remove elements with tag whose itemNumber is <= ItemNumber parameter
procedure Flush (
------------------------------------------------------------
constant Index : in integer ;
constant Tag : in string ;
constant ItemNumber : in integer
) is
variable CurPtr, RemovePtr, LastPtr : ListPointerType ;
begin
if LocalOutOfRange(Index, "Find") then
return ; -- error reporting in LocalOutOfRange
end if ;
CurPtr := HeadPointer(Index) ;
LastPtr := NULL ;
loop
if CurPtr = NULL then
-- Done
return ;
elsif CurPtr.TagPtr.all = Tag then
if ItemNumber >= CurPtr.ItemNumber then
-- remove it
RemovePtr := CurPtr ;
if CurPtr = TailPointer(Index) then
TailPointer(Index) := LastPtr ;
end if ;
if CurPtr = HeadPointer(Index) then
HeadPointer(Index) := CurPtr.NextPtr ;
else -- if LastPtr /= NULL then
LastPtr.NextPtr := LastPtr.NextPtr.NextPtr ;
end if ;
CurPtr := CurPtr.NextPtr ;
-- LastPtr := LastPtr ; -- no change
DropCountVar(Index) := DropCountVar(Index) + 1 ;
deallocate(RemovePtr.TagPtr) ;
deallocate(RemovePtr.ExpectedPtr) ;
deallocate(RemovePtr) ;
else
-- Done
return ;
end if ;
else
-- Descend
LastPtr := CurPtr ;
CurPtr := CurPtr.NextPtr ;
end if ;
end loop ;
end procedure Flush ;
------------------------------------------------------------
-- Tagged Scoreboard
-- Flush Remove elements with tag whose itemNumber is <= ItemNumber parameter
procedure Flush (
------------------------------------------------------------
constant Tag : in string ;
constant ItemNumber : in integer
) is
begin
Flush(FirstIndexVar, Tag, ItemNumber) ;
end procedure Flush ;
------------------------------------------------------------
-- Array of Simple Scoreboards
-- Flush - Remove Elements upto and including the one with ItemNumber
procedure Flush (
------------------------------------------------------------
constant Index : in integer ;
constant ItemNumber : in integer
) is
variable CurPtr : ListPointerType ;
begin
if LocalOutOfRange(Index, "Find") then
return ; -- error reporting in LocalOutOfRange
end if ;
CurPtr := HeadPointer(Index) ;
loop
if CurPtr = NULL then
-- Done
return ;
elsif ItemNumber >= CurPtr.ItemNumber then
-- Descend, Check Tail, Deallocate
HeadPointer(Index) := HeadPointer(Index).NextPtr ;
if CurPtr = TailPointer(Index) then
TailPointer(Index) := NULL ;
end if ;
DropCountVar(Index) := DropCountVar(Index) + 1 ;
deallocate(CurPtr.TagPtr) ;
deallocate(CurPtr.ExpectedPtr) ;
deallocate(CurPtr) ;
CurPtr := HeadPointer(Index) ;
else
-- Done
return ;
end if ;
end loop ;
end procedure Flush ;
------------------------------------------------------------
-- Simple Scoreboard
-- Flush - Remove Elements upto and including the one with ItemNumber
procedure Flush (
------------------------------------------------------------
constant ItemNumber : in integer
) is
begin
Flush(FirstIndexVar, ItemNumber) ;
end procedure Flush ;
------------------------------------------------------------
impure function GotScoreboards return boolean is
------------------------------------------------------------
begin
return CalledNewID ;
end function GotScoreboards ;
------------------------------------------------------------
-- pt local
procedure WriteScoreboardYaml (Index : integer; file CovYamlFile : text) is
------------------------------------------------------------
variable buf : line ;
constant NAME_PREFIX : string := " " ;
begin
write(buf, NAME_PREFIX & "- Name: " & '"' & string'(GetAlertLogName(AlertLogIDVar(Index))) & '"' & LF) ;
write(buf, NAME_PREFIX & " ItemCount: " & '"' & to_string(ItemNumberVar(Index)) & '"' & LF) ;
write(buf, NAME_PREFIX & " ErrorCount: " & '"' & to_string(ErrCntVar(Index)) & '"' & LF) ;
write(buf, NAME_PREFIX & " ItemsChecked: " & '"' & to_string(CheckCountVar(Index)) & '"' & LF) ;
write(buf, NAME_PREFIX & " ItemsPopped: " & '"' & to_string(PopCountVar(Index)) & '"' & LF) ;
write(buf, NAME_PREFIX & " ItemsDropped: " & '"' & to_string(DropCountVar(Index)) & '"' & LF) ;
writeline(CovYamlFile, buf) ;
end procedure WriteScoreboardYaml ;
------------------------------------------------------------
procedure WriteScoreboardYaml (FileName : string := ""; OpenKind : File_Open_Kind := WRITE_MODE) is
------------------------------------------------------------
constant RESOLVED_FILE_NAME : string := IfElse(FileName = "", REPORTS_DIRECTORY & GetAlertLogName & "_sb.yml", FileName) ;
file SbYamlFile : text open OpenKind is RESOLVED_FILE_NAME ;
variable buf : line ;
begin
if AlertLogIDVar = NULL or AlertLogIDVar'length <= 0 then
Alert("Scoreboard.WriteScoreboardYaml: no scoreboards defined ", ERROR) ;
return ;
end if ;
swrite(buf, "Version: 1.0" & LF) ;
swrite(buf, "TestCase: " & '"' & GetAlertLogName & '"' & LF) ;
swrite(buf, "Scoreboards: ") ;
writeline(SbYamlFile, buf) ;
if CalledNewID then
-- Used by singleton
for i in 1 to NumItems loop
WriteScoreboardYaml(i, SbYamlFile) ;
end loop ;
else
-- Used by PT method, but not singleton
for i in AlertLogIDVar'range loop
WriteScoreboardYaml(i, SbYamlFile) ;
end loop ;
end if ;
file_close(SbYamlFile) ;
end procedure WriteScoreboardYaml ;
------------------------------------------------------------
------------------------------------------------------------
-- Remaining Deprecated.
------------------------------------------------------------
------------------------------------------------------------
------------------------------------------------------------
-- Deprecated. Maintained for backward compatibility.
-- Use TranscriptPkg.TranscriptOpen
procedure FileOpen (FileName : string; OpenKind : File_Open_Kind ) is
------------------------------------------------------------
begin
-- WriteFileInit := TRUE ;
-- file_open( WriteFile , FileName , OpenKind );
TranscriptOpen(FileName, OpenKind) ;
end procedure FileOpen ;
------------------------------------------------------------
-- Deprecated. Maintained for backward compatibility.
procedure PutExpectedData (ExpectedData : ExpectedType) is
------------------------------------------------------------
begin
Push(ExpectedData) ;
end procedure PutExpectedData ;
------------------------------------------------------------
-- Deprecated. Maintained for backward compatibility.
procedure CheckActualData (ActualData : ActualType) is
------------------------------------------------------------
begin
Check(ActualData) ;
end procedure CheckActualData ;
------------------------------------------------------------
-- Deprecated. Maintained for backward compatibility.
impure function GetItemNumber return integer is
------------------------------------------------------------
begin
return GetItemCount(FirstIndexVar) ;
end GetItemNumber ;
------------------------------------------------------------
-- Deprecated. Maintained for backward compatibility.
procedure SetMessage (MessageIn : String) is
------------------------------------------------------------
begin
-- deallocate(Message) ;
-- Message := new string'(MessageIn) ;
SetName(MessageIn) ;
end procedure SetMessage ;
------------------------------------------------------------
-- Deprecated. Maintained for backward compatibility.
impure function GetMessage return string is
------------------------------------------------------------
begin
-- return Message.all ;
return GetName("Scoreboard") ;
end function GetMessage ;
--!! ------------------------------------------------------------
--!! -- Deprecated Call to NewID, refactored to call new version of NewID
--!! impure function NewID (Name : String ; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIDType is
--!! ------------------------------------------------------------
--!! variable ReportMode : AlertLogReportModeType ;
--!! begin
--!! ReportMode := ENABLED when not DoNotReport else DISABLED ;
--!! return NewID(Name, ParentAlertLogID, ReportMode => ReportMode) ;
--!! end function NewID ;
--!!
--!! ------------------------------------------------------------
--!! -- Deprecated Call to NewID, refactored to call new version of NewID
--!! -- Vector: 1 to Size
--!! impure function NewID (Name : String ; Size : positive ; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIDArrayType is
--!! ------------------------------------------------------------
--!! variable ReportMode : AlertLogReportModeType ;
--!! begin
--!! ReportMode := ENABLED when not DoNotReport else DISABLED ;
--!! return NewID(Name, (1, Size) , ParentAlertLogID, ReportMode => ReportMode) ;
--!! end function NewID ;
--!!
--!! ------------------------------------------------------------
--!! -- Deprecated Call to NewID, refactored to call new version of NewID
--!! -- Vector: X(X'Left) to X(X'Right)
--!! impure function NewID (Name : String ; X : integer_vector ; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIDArrayType is
--!! ------------------------------------------------------------
--!! variable ReportMode : AlertLogReportModeType ;
--!! begin
--!! ReportMode := ENABLED when not DoNotReport else DISABLED ;
--!! return NewID(Name, X, ParentAlertLogID, ReportMode => ReportMode) ;
--!! end function NewID ;
--!!
--!! ------------------------------------------------------------
--!! -- Deprecated Call to NewID, refactored to call new version of NewID
--!! -- Matrix: 1 to X, 1 to Y
--!! impure function NewID (Name : String ; X, Y : positive ; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIdMatrixType is
--!! ------------------------------------------------------------
--!! variable ReportMode : AlertLogReportModeType ;
--!! begin
--!! ReportMode := ENABLED when not DoNotReport else DISABLED ;
--!! return NewID(Name, X, Y, ParentAlertLogID, ReportMode => ReportMode) ;
--!! end function NewID ;
--!!
--!! ------------------------------------------------------------
--!! -- Deprecated Call to NewID, refactored to call new version of NewID
--!! -- Matrix: X(X'Left) to X(X'Right), Y(Y'Left) to Y(Y'Right)
--!! impure function NewID (Name : String ; X, Y : integer_vector ; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIdMatrixType is
--!! ------------------------------------------------------------
--!! variable ReportMode : AlertLogReportModeType ;
--!! begin
--!! ReportMode := ENABLED when not DoNotReport else DISABLED ;
--!! return NewID(Name, X, Y, ParentAlertLogID, ReportMode => ReportMode) ;
--!! end function NewID ;
end protected body ScoreBoardPType ;
shared variable ScoreboardStore : ScoreBoardPType ;
------------------------------------------------------------
-- Used by Scoreboard Store
impure function NewID (
Name : String ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIDType is
------------------------------------------------------------
begin
return ScoreboardStore.NewID(Name, ParentID, ReportMode, Search, PrintParent) ;
end function NewID ;
------------------------------------------------------------
-- Vector: 1 to Size
impure function NewID (
Name : String ;
Size : positive ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIDArrayType is
------------------------------------------------------------
begin
return ScoreboardStore.NewID(Name, Size, ParentID, ReportMode, Search, PrintParent) ;
end function NewID ;
------------------------------------------------------------
-- Vector: X(X'Left) to X(X'Right)
impure function NewID (
Name : String ;
X : integer_vector ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIDArrayType is
------------------------------------------------------------
begin
return ScoreboardStore.NewID(Name, X, ParentID, ReportMode, Search, PrintParent) ;
end function NewID ;
------------------------------------------------------------
-- Matrix: 1 to X, 1 to Y
impure function NewID (
Name : String ;
X, Y : positive ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIdMatrixType is
------------------------------------------------------------
begin
return ScoreboardStore.NewID(Name, X, Y, ParentID, ReportMode, Search, PrintParent) ;
end function NewID ;
------------------------------------------------------------
-- Matrix: X(X'Left) to X(X'Right), Y(Y'Left) to Y(Y'Right)
impure function NewID (
Name : String ;
X, Y : integer_vector ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIdMatrixType is
------------------------------------------------------------
begin
return ScoreboardStore.NewID(Name, X, Y, ParentID, ReportMode, Search, PrintParent) ;
end function NewID ;
------------------------------------------------------------
-- Push items into the scoreboard/FIFO
------------------------------------------------------------
-- Simple Scoreboard, no tag
procedure Push (
------------------------------------------------------------
constant ID : in ScoreboardIDType ;
constant Item : in ExpectedType
) is
begin
ScoreboardStore.Push(ID.ID, Item) ;
end procedure Push ;
-- Simple Tagged Scoreboard
procedure Push (
constant ID : in ScoreboardIDType ;
constant Tag : in string ;
constant Item : in ExpectedType
) is
begin
ScoreboardStore.Push(ID.ID, Tag, Item) ;
end procedure Push ;
------------------------------------------------------------
-- Check received item with item in the scoreboard/FIFO
-- Simple Scoreboard, no tag
procedure Check (
constant ID : in ScoreboardIDType ;
constant ActualData : in ActualType
) is
begin
ScoreboardStore.Check(ID.ID, ActualData) ;
end procedure Check ;
-- Simple Tagged Scoreboard
procedure Check (
constant ID : in ScoreboardIDType ;
constant Tag : in string ;
constant ActualData : in ActualType
) is
begin
ScoreboardStore.Check(ID.ID, Tag, ActualData) ;
end procedure Check ;
-- Simple Scoreboard, no tag
impure function Check (
constant ID : in ScoreboardIDType ;
constant ActualData : in ActualType
) return boolean is
begin
return ScoreboardStore.Check(ID.ID, ActualData) ;
end function Check ;
-- Simple Tagged Scoreboard
impure function Check (
constant ID : in ScoreboardIDType ;
constant Tag : in string ;
constant ActualData : in ActualType
) return boolean is
begin
return ScoreboardStore.Check(ID.ID, Tag, ActualData) ;
end function Check ;
-------------
----------------------------------------------
-- Simple Scoreboard, no tag
procedure CheckExpected (
constant ID : in ScoreboardIDType ;
constant ExpectedData : in ActualType
) is
variable Passed : boolean ;
begin
Passed := ScoreboardStore.CheckExpected(ID.ID, "", ExpectedData) ;
end procedure CheckExpected ;
-- Simple Tagged Scoreboard
procedure CheckExpected (
constant ID : in ScoreboardIDType ;
constant Tag : in string ;
constant ExpectedData : in ActualType
) is
variable Passed : boolean ;
begin
Passed := ScoreboardStore.CheckExpected(ID.ID, Tag, ExpectedData) ;
end procedure CheckExpected ;
-- Simple Scoreboard, no tag
impure function CheckExpected (
constant ID : in ScoreboardIDType ;
constant ExpectedData : in ActualType
) return boolean is
begin
return ScoreboardStore.CheckExpected(ID.ID, "", ExpectedData) ;
end function CheckExpected ;
-- Simple Tagged Scoreboard
impure function CheckExpected (
constant ID : in ScoreboardIDType ;
constant Tag : in string ;
constant ExpectedData : in ActualType
) return boolean is
begin
return ScoreboardStore.CheckExpected(ID.ID, Tag, ExpectedData) ;
end function CheckExpected ;
------------------------------------------------------------
-- Pop the top item (FIFO) from the scoreboard/FIFO
-- Simple Scoreboard, no tag
procedure Pop (
constant ID : in ScoreboardIDType ;
variable Item : out ExpectedType
) is
begin
ScoreboardStore.Pop(ID.ID, Item) ;
end procedure Pop ;
-- Simple Tagged Scoreboard
procedure Pop (
constant ID : in ScoreboardIDType ;
constant Tag : in string ;
variable Item : out ExpectedType
) is
begin
ScoreboardStore.Pop(ID.ID, Tag, Item) ;
end procedure Pop ;
------------------------------------------------------------
-- Pop the top item (FIFO) from the scoreboard/FIFO
-- Caution: this did not work in older simulators (@2013)
-- Simple Scoreboard, no tag
impure function Pop (
constant ID : in ScoreboardIDType
) return ExpectedType is
begin
return ScoreboardStore.Pop(ID.ID) ;
end function Pop ;
-- Simple Tagged Scoreboard
impure function Pop (
constant ID : in ScoreboardIDType ;
constant Tag : in string
) return ExpectedType is
begin
return ScoreboardStore.Pop(ID.ID, Tag) ;
end function Pop ;
------------------------------------------------------------
-- Peek at the top item (FIFO) from the scoreboard/FIFO
-- Simple Tagged Scoreboard
procedure Peek (
constant ID : in ScoreboardIDType ;
constant Tag : in string ;
variable Item : out ExpectedType
) is
begin
ScoreboardStore.Peek(ID.ID, Tag, Item) ;
end procedure Peek ;
-- Simple Scoreboard, no tag
procedure Peek (
constant ID : in ScoreboardIDType ;
variable Item : out ExpectedType
) is
begin
ScoreboardStore.Peek(ID.ID, Item) ;
end procedure Peek ;
------------------------------------------------------------
-- Peek at the top item (FIFO) from the scoreboard/FIFO
-- Caution: this did not work in older simulators (@2013)
-- Tagged Scoreboards
impure function Peek (
constant ID : in ScoreboardIDType ;
constant Tag : in string
) return ExpectedType is
begin
-- return ScoreboardStore.Peek(Tag) ;
-- log("Issues compiling return later");
return ScoreboardStore.Peek(Index => ID.ID, Tag => Tag) ;
end function Peek ;
-- Simple Scoreboard
impure function Peek (
constant ID : in ScoreboardIDType
) return ExpectedType is
begin
return ScoreboardStore.Peek(Index => ID.ID) ;
end function Peek ;
------------------------------------------------------------
-- ScoreboardEmpty - check to see if scoreboard is empty
-- Simple
impure function ScoreboardEmpty (
constant ID : in ScoreboardIDType
) return boolean is
begin
return ScoreboardStore.Empty(ID.ID) ;
end function ScoreboardEmpty ;
-- Tagged
impure function ScoreboardEmpty (
constant ID : in ScoreboardIDType ;
constant Tag : in string
) return boolean is
begin
return ScoreboardStore.Empty(ID.ID, Tag) ;
end function ScoreboardEmpty ;
impure function Empty (
constant ID : in ScoreboardIDType
) return boolean is
begin
return ScoreboardStore.Empty(ID.ID) ;
end function Empty ;
-- Tagged
impure function Empty (
constant ID : in ScoreboardIDType ;
constant Tag : in string
) return boolean is
begin
return ScoreboardStore.Empty(ID.ID, Tag) ;
end function Empty ;
--!! ------------------------------------------------------------
--!! -- SetAlertLogID - associate an AlertLogID with a scoreboard to allow integrated error reporting
--!! procedure SetAlertLogID(
--!! constant ID : in ScoreboardIDType ;
--!! constant Name : in string ;
--!! constant ParentID : in AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
--!! constant CreateHierarchy : in Boolean := TRUE ;
--!! constant DoNotReport : in Boolean := FALSE
--!! ) is
--!! begin
--!! ScoreboardStore.SetAlertLogID(ID.ID, Name, ParentID, CreateHierarchy, DoNotReport) ;
--!! end procedure SetAlertLogID ;
--!!
--!! -- Use when an AlertLogID is used by multiple items (Model or other Scoreboards). See also AlertLogPkg.GetAlertLogID
--!! procedure SetAlertLogID (
--!! constant ID : in ScoreboardIDType ;
--!! constant A : AlertLogIDType
--!! ) is
--!! begin
--!! ScoreboardStore.SetAlertLogID(ID.ID, A) ;
--!! end procedure SetAlertLogID ;
impure function GetAlertLogID (
constant ID : in ScoreboardIDType
) return AlertLogIDType is
begin
return ScoreboardStore.GetAlertLogID(ID.ID) ;
end function GetAlertLogID ;
------------------------------------------------------------
-- Scoreboard Introspection
-- Number of items put into scoreboard
impure function GetItemCount (
constant ID : in ScoreboardIDType
) return integer is
begin
return ScoreboardStore.GetItemCount(ID.ID) ;
end function GetItemCount ;
impure function GetPushCount (
constant ID : in ScoreboardIDType
) return integer is
begin
return ScoreboardStore.GetPushCount(ID.ID) ;
end function GetPushCount ;
-- Number of items removed from scoreboard by pop or check
impure function GetPopCount (
constant ID : in ScoreboardIDType
) return integer is
begin
return ScoreboardStore.GetPopCount(ID.ID) ;
end function GetPopCount ;
-- Number of items currently in the scoreboard (= PushCount - PopCount - DropCount)
impure function GetFifoCount (
constant ID : in ScoreboardIDType
) return integer is
begin
return ScoreboardStore.GetFifoCount(ID.ID) ;
end function GetFifoCount ;
-- Number of items checked by scoreboard
impure function GetCheckCount (
constant ID : in ScoreboardIDType
) return integer is
begin
return ScoreboardStore.GetCheckCount(ID.ID) ;
end function GetCheckCount ;
-- Number of items dropped by scoreboard. See Find/Flush
impure function GetDropCount (
constant ID : in ScoreboardIDType
) return integer is
begin
return ScoreboardStore.GetDropCount(ID.ID) ;
end function GetDropCount ;
------------------------------------------------------------
-- Find - Returns the ItemNumber for a value and tag (if applicable) in a scoreboard.
-- Find returns integer'left if no match found
-- Also See Flush. Flush will drop items up through the ItemNumber
-- Simple Scoreboard
impure function Find (
constant ID : in ScoreboardIDType ;
constant ActualData : in ActualType
) return integer is
begin
return ScoreboardStore.Find(ID.ID, ActualData) ;
end function Find ;
-- Tagged Scoreboard
impure function Find (
constant ID : in ScoreboardIDType ;
constant Tag : in string;
constant ActualData : in ActualType
) return integer is
begin
return ScoreboardStore.Find(ID.ID, Tag, ActualData) ;
end function Find ;
------------------------------------------------------------
-- Flush - Remove elements in the scoreboard upto and including the one with ItemNumber
-- See Find to identify an ItemNumber of a particular value and tag (if applicable)
-- Simple Scoreboards
procedure Flush (
constant ID : in ScoreboardIDType ;
constant ItemNumber : in integer
) is
begin
ScoreboardStore.Flush(ID.ID, ItemNumber) ;
end procedure Flush ;
-- Tagged Scoreboards - only removes items that also match the tag
procedure Flush (
constant ID : in ScoreboardIDType ;
constant Tag : in string ;
constant ItemNumber : in integer
) is
begin
ScoreboardStore.Flush(ID.ID, Tag, ItemNumber) ;
end procedure Flush ;
------------------------------------------------------------
-- Scoreboard YAML Reports
impure function GotScoreboards return boolean is
begin
return ScoreboardStore.GotScoreboards ;
end function GotScoreboards ;
------------------------------------------------------------
procedure WriteScoreboardYaml (FileName : string := ""; OpenKind : File_Open_Kind := WRITE_MODE) is
begin
ScoreboardStore.WriteScoreboardYaml(FileName, OpenKind) ;
end procedure WriteScoreboardYaml ;
------------------------------------------------------------
-- Generally these are not required. When a simulation ends and
-- another simulation is started, a simulator will release all allocated items.
procedure Deallocate (
constant ID : in ScoreboardIDType
) is
begin
ScoreboardStore.Deallocate ;
end procedure Deallocate ;
procedure Initialize (
constant ID : in ScoreboardIDType
) is
begin
ScoreboardStore.Initialize ;
end procedure Initialize ;
------------------------------------------------------------
-- Get error count
-- Deprecated, replaced by usage of Alerts
-- AlertFLow: Instead use AlertLogPkg.ReportAlerts or AlertLogPkg.GetAlertCount
-- Not AlertFlow: use GetErrorCount to get total error count
-- Scoreboards, with or without tag
impure function GetErrorCount(
constant ID : in ScoreboardIDType
) return integer is
begin
return GetAlertCount(ScoreboardStore.GetAlertLogID(ID.ID)) ;
end function GetErrorCount ;
------------------------------------------------------------
procedure CheckFinish (
------------------------------------------------------------
ID : ScoreboardIDType ;
FinishCheckCount : integer ;
FinishEmpty : boolean
) is
begin
ScoreboardStore.CheckFinish(ID.ID, FinishCheckCount, FinishEmpty) ;
end procedure CheckFinish ;
------------------------------------------------------------
-- SetReportMode
-- Not AlertFlow
-- REPORT_ALL: Replaced by AlertLogPkg.SetLogEnable(PASSED, TRUE)
-- REPORT_ERROR: Replaced by AlertLogPkg.SetLogEnable(PASSED, FALSE)
-- REPORT_NONE: Deprecated, do not use.
-- AlertFlow:
-- REPORT_ALL: Replaced by AlertLogPkg.SetLogEnable(AlertLogID, PASSED, TRUE)
-- REPORT_ERROR: Replaced by AlertLogPkg.SetLogEnable(AlertLogID, PASSED, FALSE)
-- REPORT_NONE: Replaced by AlertLogPkg.SetAlertEnable(AlertLogID, ERROR, FALSE)
procedure SetReportMode (
constant ID : in ScoreboardIDType ;
constant ReportModeIn : in ScoreboardReportType
) is
begin
-- ScoreboardStore.SetReportMode(ID.ID, ReportModeIn) ;
ScoreboardStore.SetReportMode(ReportModeIn) ;
end procedure SetReportMode ;
impure function GetReportMode (
constant ID : in ScoreboardIDType
) return ScoreboardReportType is
begin
-- return ScoreboardStore.GetReportMode(ID.ID) ;
return ScoreboardStore.GetReportMode ;
end function GetReportMode ;
--==========================================================
--!! Deprecated Subprograms
--==========================================================
------------------------------------------------------------
-- Deprecated interface to NewID
impure function NewID (Name : String ; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIDType is
------------------------------------------------------------
variable ReportMode : AlertLogReportModeType ;
begin
ReportMode := ENABLED when not DoNotReport else DISABLED ;
return ScoreboardStore.NewID(Name, ParentAlertLogID, ReportMode => ReportMode) ;
end function NewID ;
------------------------------------------------------------
-- Vector: 1 to Size
impure function NewID (Name : String ; Size : positive ; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIDArrayType is
------------------------------------------------------------
variable ReportMode : AlertLogReportModeType ;
begin
ReportMode := ENABLED when not DoNotReport else DISABLED ;
return ScoreboardStore.NewID(Name, Size, ParentAlertLogID, ReportMode => ReportMode) ;
end function NewID ;
------------------------------------------------------------
-- Vector: X(X'Left) to X(X'Right)
impure function NewID (Name : String ; X : integer_vector ; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIDArrayType is
------------------------------------------------------------
variable ReportMode : AlertLogReportModeType ;
begin
ReportMode := ENABLED when not DoNotReport else DISABLED ;
return ScoreboardStore.NewID(Name, X, ParentAlertLogID, ReportMode => ReportMode) ;
end function NewID ;
------------------------------------------------------------
-- Matrix: 1 to X, 1 to Y
impure function NewID (Name : String ; X, Y : positive ; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIdMatrixType is
------------------------------------------------------------
variable ReportMode : AlertLogReportModeType ;
begin
ReportMode := ENABLED when not DoNotReport else DISABLED ;
return ScoreboardStore.NewID(Name, X, Y, ParentAlertLogID, ReportMode => ReportMode) ;
end function NewID ;
------------------------------------------------------------
-- Matrix: X(X'Left) to X(X'Right), Y(Y'Left) to Y(Y'Right)
impure function NewID (Name : String ; X, Y : integer_vector ; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIdMatrixType is
------------------------------------------------------------
variable ReportMode : AlertLogReportModeType ;
begin
ReportMode := ENABLED when not DoNotReport else DISABLED ;
return ScoreboardStore.NewID(Name, X, Y, ParentAlertLogID, ReportMode => ReportMode) ;
end function NewID ;
end ScoreboardGenericPkg ;
|
artistic-2.0
|
hterkelsen/mal
|
vhdl/step7_quote.vhdl
|
13
|
11888
|
entity step7_quote is
end entity step7_quote;
library STD;
use STD.textio.all;
library WORK;
use WORK.pkg_readline.all;
use WORK.types.all;
use WORK.printer.all;
use WORK.reader.all;
use WORK.env.all;
use WORK.core.all;
architecture test of step7_quote is
shared variable repl_env: env_ptr;
procedure mal_READ(str: in string; ast: out mal_val_ptr; err: out mal_val_ptr) is
begin
read_str(str, ast, err);
end procedure mal_READ;
procedure is_pair(ast: inout mal_val_ptr; pair: out boolean) is
begin
pair := is_sequential_type(ast.val_type) and ast.seq_val'length > 0;
end procedure is_pair;
procedure quasiquote(ast: inout mal_val_ptr; result: out mal_val_ptr) is
variable ast_pair, a0_pair: boolean;
variable seq: mal_seq_ptr;
variable a0, rest: mal_val_ptr;
begin
is_pair(ast, ast_pair);
if not ast_pair then
seq := new mal_seq(0 to 1);
new_symbol("quote", seq(0));
seq(1) := ast;
new_seq_obj(mal_list, seq, result);
return;
end if;
a0 := ast.seq_val(0);
if a0.val_type = mal_symbol and a0.string_val.all = "unquote" then
result := ast.seq_val(1);
else
is_pair(a0, a0_pair);
if a0_pair and a0.seq_val(0).val_type = mal_symbol and a0.seq_val(0).string_val.all = "splice-unquote" then
seq := new mal_seq(0 to 2);
new_symbol("concat", seq(0));
seq(1) := a0.seq_val(1);
seq_drop_prefix(ast, 1, rest);
quasiquote(rest, seq(2));
new_seq_obj(mal_list, seq, result);
else
seq := new mal_seq(0 to 2);
new_symbol("cons", seq(0));
quasiquote(a0, seq(1));
seq_drop_prefix(ast, 1, rest);
quasiquote(rest, seq(2));
new_seq_obj(mal_list, seq, result);
end if;
end if;
end procedure quasiquote;
-- Forward declaration
procedure EVAL(in_ast: inout mal_val_ptr; in_env: inout env_ptr; result: out mal_val_ptr; err: out mal_val_ptr);
procedure apply_func(fn: inout mal_val_ptr; args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr);
procedure fn_eval(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
begin
EVAL(args.seq_val(0), repl_env, result, err);
end procedure fn_eval;
procedure fn_swap(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable atom: mal_val_ptr := args.seq_val(0);
variable fn: mal_val_ptr := args.seq_val(1);
variable call_args_seq: mal_seq_ptr;
variable call_args, eval_res, sub_err: mal_val_ptr;
begin
call_args_seq := new mal_seq(0 to args.seq_val'length - 2);
call_args_seq(0) := atom.seq_val(0);
call_args_seq(1 to call_args_seq'length - 1) := args.seq_val(2 to args.seq_val'length - 1);
new_seq_obj(mal_list, call_args_seq, call_args);
apply_func(fn, call_args, eval_res, sub_err);
if sub_err /= null then
err := sub_err;
return;
end if;
atom.seq_val(0) := eval_res;
result := eval_res;
end procedure fn_swap;
procedure apply_native_func(func_sym: inout mal_val_ptr; args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
begin
if func_sym.string_val.all = "eval" then
fn_eval(args, result, err);
elsif func_sym.string_val.all = "swap!" then
fn_swap(args, result, err);
else
eval_native_func(func_sym, args, result, err);
end if;
end procedure apply_native_func;
procedure apply_func(fn: inout mal_val_ptr; args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable fn_env: env_ptr;
begin
case fn.val_type is
when mal_nativefn =>
apply_native_func(fn, args, result, err);
when mal_fn =>
new_env(fn_env, fn.func_val.f_env, fn.func_val.f_args, args);
EVAL(fn.func_val.f_body, fn_env, result, err);
when others =>
new_string("not a function", err);
return;
end case;
end procedure apply_func;
procedure eval_ast_seq(ast_seq: inout mal_seq_ptr; env: inout env_ptr; result: inout mal_seq_ptr; err: out mal_val_ptr) is
variable eval_err: mal_val_ptr;
begin
result := new mal_seq(0 to ast_seq'length - 1);
for i in result'range loop
EVAL(ast_seq(i), env, result(i), eval_err);
if eval_err /= null then
err := eval_err;
return;
end if;
end loop;
end procedure eval_ast_seq;
procedure eval_ast(ast: inout mal_val_ptr; env: inout env_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable key, val, eval_err, env_err: mal_val_ptr;
variable new_seq: mal_seq_ptr;
variable i: integer;
begin
case ast.val_type is
when mal_symbol =>
env_get(env, ast, val, env_err);
if env_err /= null then
err := env_err;
return;
end if;
result := val;
return;
when mal_list | mal_vector | mal_hashmap =>
eval_ast_seq(ast.seq_val, env, new_seq, eval_err);
if eval_err /= null then
err := eval_err;
return;
end if;
new_seq_obj(ast.val_type, new_seq, result);
return;
when others =>
result := ast;
return;
end case;
end procedure eval_ast;
procedure EVAL(in_ast: inout mal_val_ptr; in_env: inout env_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable i: integer;
variable ast, evaled_ast, a0, call_args, val, vars, sub_err, fn: mal_val_ptr;
variable env, let_env, fn_env: env_ptr;
begin
ast := in_ast;
env := in_env;
loop
if ast.val_type /= mal_list then
eval_ast(ast, env, result, err);
return;
end if;
if ast.seq_val'length = 0 then
result := ast;
return;
end if;
a0 := ast.seq_val(0);
if a0.val_type = mal_symbol then
if a0.string_val.all = "def!" then
EVAL(ast.seq_val(2), env, val, sub_err);
if sub_err /= null then
err := sub_err;
return;
end if;
env_set(env, ast.seq_val(1), val);
result := val;
return;
elsif a0.string_val.all = "let*" then
vars := ast.seq_val(1);
new_env(let_env, env);
i := 0;
while i < vars.seq_val'length loop
EVAL(vars.seq_val(i + 1), let_env, val, sub_err);
if sub_err /= null then
err := sub_err;
return;
end if;
env_set(let_env, vars.seq_val(i), val);
i := i + 2;
end loop;
env := let_env;
ast := ast.seq_val(2);
next; -- TCO
elsif a0.string_val.all = "quote" then
result := ast.seq_val(1);
return;
elsif a0.string_val.all = "quasiquote" then
quasiquote(ast.seq_val(1), ast);
next; -- TCO
elsif a0.string_val.all = "do" then
for i in 1 to ast.seq_val'high - 1 loop
EVAL(ast.seq_val(i), env, result, sub_err);
if sub_err /= null then
err := sub_err;
return;
end if;
end loop;
ast := ast.seq_val(ast.seq_val'high);
next; -- TCO
elsif a0.string_val.all = "if" then
EVAL(ast.seq_val(1), env, val, sub_err);
if sub_err /= null then
err := sub_err;
return;
end if;
if val.val_type = mal_nil or val.val_type = mal_false then
if ast.seq_val'length > 3 then
ast := ast.seq_val(3);
else
new_nil(result);
return;
end if;
else
ast := ast.seq_val(2);
end if;
next; -- TCO
elsif a0.string_val.all = "fn*" then
new_fn(ast.seq_val(2), ast.seq_val(1), env, result);
return;
end if;
end if;
eval_ast(ast, env, evaled_ast, sub_err);
if sub_err /= null then
err := sub_err;
return;
end if;
seq_drop_prefix(evaled_ast, 1, call_args);
fn := evaled_ast.seq_val(0);
case fn.val_type is
when mal_nativefn =>
apply_native_func(fn, call_args, result, err);
return;
when mal_fn =>
new_env(fn_env, fn.func_val.f_env, fn.func_val.f_args, call_args);
env := fn_env;
ast := fn.func_val.f_body;
next; -- TCO
when others =>
new_string("not a function", err);
return;
end case;
end loop;
end procedure EVAL;
procedure mal_PRINT(exp: inout mal_val_ptr; result: out line) is
begin
pr_str(exp, true, result);
end procedure mal_PRINT;
procedure RE(str: in string; env: inout env_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable ast, read_err: mal_val_ptr;
begin
mal_READ(str, ast, read_err);
if read_err /= null then
err := read_err;
result := null;
return;
end if;
if ast = null then
result := null;
return;
end if;
EVAL(ast, env, result, err);
end procedure RE;
procedure REP(str: in string; env: inout env_ptr; result: out line; err: out mal_val_ptr) is
variable eval_res, eval_err: mal_val_ptr;
begin
RE(str, env, eval_res, eval_err);
if eval_err /= null then
err := eval_err;
result := null;
return;
end if;
mal_PRINT(eval_res, result);
end procedure REP;
procedure set_argv(e: inout env_ptr; program_file: inout line) is
variable argv_var_name: string(1 to 6) := "*ARGV*";
variable argv_sym, argv_list: mal_val_ptr;
file f: text;
variable status: file_open_status;
variable one_line: line;
variable seq: mal_seq_ptr;
variable element: mal_val_ptr;
begin
program_file := null;
seq := new mal_seq(0 to -1);
file_open(status, f, external_name => "vhdl_argv.tmp", open_kind => read_mode);
if status = open_ok then
if not endfile(f) then
readline(f, program_file);
while not endfile(f) loop
readline(f, one_line);
new_string(one_line.all, element);
seq := new mal_seq'(seq.all & element);
end loop;
end if;
file_close(f);
end if;
new_seq_obj(mal_list, seq, argv_list);
new_symbol(argv_var_name, argv_sym);
env_set(e, argv_sym, argv_list);
end procedure set_argv;
procedure repl is
variable is_eof: boolean;
variable program_file, input_line, result: line;
variable eval_sym, eval_fn, dummy_val, err: mal_val_ptr;
variable outer: env_ptr;
variable eval_func_name: string(1 to 4) := "eval";
begin
outer := null;
new_env(repl_env, outer);
-- core.EXT: defined using VHDL (see core.vhdl)
define_core_functions(repl_env);
new_symbol(eval_func_name, eval_sym);
new_nativefn(eval_func_name, eval_fn);
env_set(repl_env, eval_sym, eval_fn);
set_argv(repl_env, program_file);
-- core.mal: defined using the language itself
RE("(def! not (fn* (a) (if a false true)))", repl_env, dummy_val, err);
RE("(def! load-file (fn* (f) (eval (read-string (str " & '"' & "(do " & '"' & " (slurp f) " & '"' & ")" & '"' & ")))))", repl_env, dummy_val, err);
if program_file /= null then
REP("(load-file " & '"' & program_file.all & '"' & ")", repl_env, result, err);
return;
end if;
loop
mal_readline("user> ", is_eof, input_line);
exit when is_eof;
next when input_line'length = 0;
REP(input_line.all, repl_env, result, err);
if err /= null then
pr_str(err, false, result);
result := new string'("Error: " & result.all);
end if;
if result /= null then
mal_printline(result.all);
end if;
deallocate(result);
deallocate(err);
end loop;
mal_printline("");
end procedure repl;
begin
repl;
end architecture test;
|
mpl-2.0
|
foresterre/mal
|
vhdl/step7_quote.vhdl
|
13
|
11888
|
entity step7_quote is
end entity step7_quote;
library STD;
use STD.textio.all;
library WORK;
use WORK.pkg_readline.all;
use WORK.types.all;
use WORK.printer.all;
use WORK.reader.all;
use WORK.env.all;
use WORK.core.all;
architecture test of step7_quote is
shared variable repl_env: env_ptr;
procedure mal_READ(str: in string; ast: out mal_val_ptr; err: out mal_val_ptr) is
begin
read_str(str, ast, err);
end procedure mal_READ;
procedure is_pair(ast: inout mal_val_ptr; pair: out boolean) is
begin
pair := is_sequential_type(ast.val_type) and ast.seq_val'length > 0;
end procedure is_pair;
procedure quasiquote(ast: inout mal_val_ptr; result: out mal_val_ptr) is
variable ast_pair, a0_pair: boolean;
variable seq: mal_seq_ptr;
variable a0, rest: mal_val_ptr;
begin
is_pair(ast, ast_pair);
if not ast_pair then
seq := new mal_seq(0 to 1);
new_symbol("quote", seq(0));
seq(1) := ast;
new_seq_obj(mal_list, seq, result);
return;
end if;
a0 := ast.seq_val(0);
if a0.val_type = mal_symbol and a0.string_val.all = "unquote" then
result := ast.seq_val(1);
else
is_pair(a0, a0_pair);
if a0_pair and a0.seq_val(0).val_type = mal_symbol and a0.seq_val(0).string_val.all = "splice-unquote" then
seq := new mal_seq(0 to 2);
new_symbol("concat", seq(0));
seq(1) := a0.seq_val(1);
seq_drop_prefix(ast, 1, rest);
quasiquote(rest, seq(2));
new_seq_obj(mal_list, seq, result);
else
seq := new mal_seq(0 to 2);
new_symbol("cons", seq(0));
quasiquote(a0, seq(1));
seq_drop_prefix(ast, 1, rest);
quasiquote(rest, seq(2));
new_seq_obj(mal_list, seq, result);
end if;
end if;
end procedure quasiquote;
-- Forward declaration
procedure EVAL(in_ast: inout mal_val_ptr; in_env: inout env_ptr; result: out mal_val_ptr; err: out mal_val_ptr);
procedure apply_func(fn: inout mal_val_ptr; args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr);
procedure fn_eval(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
begin
EVAL(args.seq_val(0), repl_env, result, err);
end procedure fn_eval;
procedure fn_swap(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable atom: mal_val_ptr := args.seq_val(0);
variable fn: mal_val_ptr := args.seq_val(1);
variable call_args_seq: mal_seq_ptr;
variable call_args, eval_res, sub_err: mal_val_ptr;
begin
call_args_seq := new mal_seq(0 to args.seq_val'length - 2);
call_args_seq(0) := atom.seq_val(0);
call_args_seq(1 to call_args_seq'length - 1) := args.seq_val(2 to args.seq_val'length - 1);
new_seq_obj(mal_list, call_args_seq, call_args);
apply_func(fn, call_args, eval_res, sub_err);
if sub_err /= null then
err := sub_err;
return;
end if;
atom.seq_val(0) := eval_res;
result := eval_res;
end procedure fn_swap;
procedure apply_native_func(func_sym: inout mal_val_ptr; args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
begin
if func_sym.string_val.all = "eval" then
fn_eval(args, result, err);
elsif func_sym.string_val.all = "swap!" then
fn_swap(args, result, err);
else
eval_native_func(func_sym, args, result, err);
end if;
end procedure apply_native_func;
procedure apply_func(fn: inout mal_val_ptr; args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable fn_env: env_ptr;
begin
case fn.val_type is
when mal_nativefn =>
apply_native_func(fn, args, result, err);
when mal_fn =>
new_env(fn_env, fn.func_val.f_env, fn.func_val.f_args, args);
EVAL(fn.func_val.f_body, fn_env, result, err);
when others =>
new_string("not a function", err);
return;
end case;
end procedure apply_func;
procedure eval_ast_seq(ast_seq: inout mal_seq_ptr; env: inout env_ptr; result: inout mal_seq_ptr; err: out mal_val_ptr) is
variable eval_err: mal_val_ptr;
begin
result := new mal_seq(0 to ast_seq'length - 1);
for i in result'range loop
EVAL(ast_seq(i), env, result(i), eval_err);
if eval_err /= null then
err := eval_err;
return;
end if;
end loop;
end procedure eval_ast_seq;
procedure eval_ast(ast: inout mal_val_ptr; env: inout env_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable key, val, eval_err, env_err: mal_val_ptr;
variable new_seq: mal_seq_ptr;
variable i: integer;
begin
case ast.val_type is
when mal_symbol =>
env_get(env, ast, val, env_err);
if env_err /= null then
err := env_err;
return;
end if;
result := val;
return;
when mal_list | mal_vector | mal_hashmap =>
eval_ast_seq(ast.seq_val, env, new_seq, eval_err);
if eval_err /= null then
err := eval_err;
return;
end if;
new_seq_obj(ast.val_type, new_seq, result);
return;
when others =>
result := ast;
return;
end case;
end procedure eval_ast;
procedure EVAL(in_ast: inout mal_val_ptr; in_env: inout env_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable i: integer;
variable ast, evaled_ast, a0, call_args, val, vars, sub_err, fn: mal_val_ptr;
variable env, let_env, fn_env: env_ptr;
begin
ast := in_ast;
env := in_env;
loop
if ast.val_type /= mal_list then
eval_ast(ast, env, result, err);
return;
end if;
if ast.seq_val'length = 0 then
result := ast;
return;
end if;
a0 := ast.seq_val(0);
if a0.val_type = mal_symbol then
if a0.string_val.all = "def!" then
EVAL(ast.seq_val(2), env, val, sub_err);
if sub_err /= null then
err := sub_err;
return;
end if;
env_set(env, ast.seq_val(1), val);
result := val;
return;
elsif a0.string_val.all = "let*" then
vars := ast.seq_val(1);
new_env(let_env, env);
i := 0;
while i < vars.seq_val'length loop
EVAL(vars.seq_val(i + 1), let_env, val, sub_err);
if sub_err /= null then
err := sub_err;
return;
end if;
env_set(let_env, vars.seq_val(i), val);
i := i + 2;
end loop;
env := let_env;
ast := ast.seq_val(2);
next; -- TCO
elsif a0.string_val.all = "quote" then
result := ast.seq_val(1);
return;
elsif a0.string_val.all = "quasiquote" then
quasiquote(ast.seq_val(1), ast);
next; -- TCO
elsif a0.string_val.all = "do" then
for i in 1 to ast.seq_val'high - 1 loop
EVAL(ast.seq_val(i), env, result, sub_err);
if sub_err /= null then
err := sub_err;
return;
end if;
end loop;
ast := ast.seq_val(ast.seq_val'high);
next; -- TCO
elsif a0.string_val.all = "if" then
EVAL(ast.seq_val(1), env, val, sub_err);
if sub_err /= null then
err := sub_err;
return;
end if;
if val.val_type = mal_nil or val.val_type = mal_false then
if ast.seq_val'length > 3 then
ast := ast.seq_val(3);
else
new_nil(result);
return;
end if;
else
ast := ast.seq_val(2);
end if;
next; -- TCO
elsif a0.string_val.all = "fn*" then
new_fn(ast.seq_val(2), ast.seq_val(1), env, result);
return;
end if;
end if;
eval_ast(ast, env, evaled_ast, sub_err);
if sub_err /= null then
err := sub_err;
return;
end if;
seq_drop_prefix(evaled_ast, 1, call_args);
fn := evaled_ast.seq_val(0);
case fn.val_type is
when mal_nativefn =>
apply_native_func(fn, call_args, result, err);
return;
when mal_fn =>
new_env(fn_env, fn.func_val.f_env, fn.func_val.f_args, call_args);
env := fn_env;
ast := fn.func_val.f_body;
next; -- TCO
when others =>
new_string("not a function", err);
return;
end case;
end loop;
end procedure EVAL;
procedure mal_PRINT(exp: inout mal_val_ptr; result: out line) is
begin
pr_str(exp, true, result);
end procedure mal_PRINT;
procedure RE(str: in string; env: inout env_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable ast, read_err: mal_val_ptr;
begin
mal_READ(str, ast, read_err);
if read_err /= null then
err := read_err;
result := null;
return;
end if;
if ast = null then
result := null;
return;
end if;
EVAL(ast, env, result, err);
end procedure RE;
procedure REP(str: in string; env: inout env_ptr; result: out line; err: out mal_val_ptr) is
variable eval_res, eval_err: mal_val_ptr;
begin
RE(str, env, eval_res, eval_err);
if eval_err /= null then
err := eval_err;
result := null;
return;
end if;
mal_PRINT(eval_res, result);
end procedure REP;
procedure set_argv(e: inout env_ptr; program_file: inout line) is
variable argv_var_name: string(1 to 6) := "*ARGV*";
variable argv_sym, argv_list: mal_val_ptr;
file f: text;
variable status: file_open_status;
variable one_line: line;
variable seq: mal_seq_ptr;
variable element: mal_val_ptr;
begin
program_file := null;
seq := new mal_seq(0 to -1);
file_open(status, f, external_name => "vhdl_argv.tmp", open_kind => read_mode);
if status = open_ok then
if not endfile(f) then
readline(f, program_file);
while not endfile(f) loop
readline(f, one_line);
new_string(one_line.all, element);
seq := new mal_seq'(seq.all & element);
end loop;
end if;
file_close(f);
end if;
new_seq_obj(mal_list, seq, argv_list);
new_symbol(argv_var_name, argv_sym);
env_set(e, argv_sym, argv_list);
end procedure set_argv;
procedure repl is
variable is_eof: boolean;
variable program_file, input_line, result: line;
variable eval_sym, eval_fn, dummy_val, err: mal_val_ptr;
variable outer: env_ptr;
variable eval_func_name: string(1 to 4) := "eval";
begin
outer := null;
new_env(repl_env, outer);
-- core.EXT: defined using VHDL (see core.vhdl)
define_core_functions(repl_env);
new_symbol(eval_func_name, eval_sym);
new_nativefn(eval_func_name, eval_fn);
env_set(repl_env, eval_sym, eval_fn);
set_argv(repl_env, program_file);
-- core.mal: defined using the language itself
RE("(def! not (fn* (a) (if a false true)))", repl_env, dummy_val, err);
RE("(def! load-file (fn* (f) (eval (read-string (str " & '"' & "(do " & '"' & " (slurp f) " & '"' & ")" & '"' & ")))))", repl_env, dummy_val, err);
if program_file /= null then
REP("(load-file " & '"' & program_file.all & '"' & ")", repl_env, result, err);
return;
end if;
loop
mal_readline("user> ", is_eof, input_line);
exit when is_eof;
next when input_line'length = 0;
REP(input_line.all, repl_env, result, err);
if err /= null then
pr_str(err, false, result);
result := new string'("Error: " & result.all);
end if;
if result /= null then
mal_printline(result.all);
end if;
deallocate(result);
deallocate(err);
end loop;
mal_printline("");
end procedure repl;
begin
repl;
end architecture test;
|
mpl-2.0
|
cpavlina/logicanalyzer
|
la-hdl/ipcore_dir/mig_39_2/user_design/sim/afifo.vhd
|
20
|
9200
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: afifo.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:16:34 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: A generic synchronous fifo.
-- Reference:
-- Revision History: 2009/01/09 corrected signal "buf_avail" and "almost_full" equation.
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
ENTITY afifo IS
GENERIC (
TCQ : TIME := 100 ps;
DSIZE : INTEGER := 32;
FIFO_DEPTH : INTEGER := 16;
ASIZE : INTEGER := 4;
SYNC : INTEGER := 1
);
PORT (
wr_clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
wr_en : IN STD_LOGIC;
wr_data : IN STD_LOGIC_VECTOR(DSIZE - 1 DOWNTO 0);
rd_en : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_data : OUT STD_LOGIC_VECTOR(DSIZE - 1 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC
);
END afifo;
ARCHITECTURE trans OF afifo IS
TYPE mem_array IS ARRAY (0 TO FIFO_DEPTH ) OF STD_LOGIC_VECTOR(DSIZE - 1 DOWNTO 0);
SIGNAL mem : mem_array;
SIGNAL rd_gray_nxt : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL rd_gray : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL rd_capture_ptr : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL pre_rd_capture_gray_ptr : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL rd_capture_gray_ptr : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL wr_gray : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL wr_gray_nxt : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL wr_capture_ptr : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL pre_wr_capture_gray_ptr : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL wr_capture_gray_ptr : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL buf_avail : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL buf_filled : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL wr_addr : STD_LOGIC_VECTOR(ASIZE - 1 DOWNTO 0);
SIGNAL rd_addr : STD_LOGIC_VECTOR(ASIZE - 1 DOWNTO 0);
SIGNAL wr_ptr : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL rd_ptr : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL i : INTEGER;
SIGNAL j : INTEGER;
SIGNAL k : INTEGER;
SIGNAL rd_strobe : STD_LOGIC;
SIGNAL n : INTEGER;
SIGNAL rd_ptr_tmp : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL wbin : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL wgraynext : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL wbinnext : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL ZERO : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL ONE : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
-- Declare intermediate signals for referenced outputs
SIGNAL full_xhdl1 : STD_LOGIC;
SIGNAL almost_full_int : STD_LOGIC;
SIGNAL empty_xhdl0 : STD_LOGIC;
BEGIN
-- Drive referenced outputs
ZERO <= std_logic_vector(to_unsigned(0,(ASIZE+1)));
ONE <= std_logic_vector(to_unsigned(1,(ASIZE+1)));
full <= full_xhdl1;
empty <= empty_xhdl0;
xhdl3 : IF (SYNC = 1) GENERATE
PROCESS (rd_ptr)
BEGIN
rd_capture_ptr <= rd_ptr;
END PROCESS;
END GENERATE;
xhdl4 : IF (SYNC = 1) GENERATE
PROCESS (wr_ptr)
BEGIN
wr_capture_ptr <= wr_ptr;
END PROCESS;
END GENERATE;
wr_addr <= wr_ptr(ASIZE-1 DOWNTO 0);
rd_data <= mem(conv_integer(rd_addr));
PROCESS (wr_clk)
BEGIN
IF (wr_clk'EVENT AND wr_clk = '1') THEN
IF ((wr_en AND NOT(full_xhdl1)) = '1') THEN
mem(to_integer(unsigned(wr_addr))) <= wr_data;
END IF;
END IF;
END PROCESS;
rd_addr <= rd_ptr(ASIZE - 1 DOWNTO 0);
rd_strobe <= rd_en AND NOT(empty_xhdl0);
PROCESS (rd_ptr)
BEGIN
rd_gray_nxt(ASIZE) <= rd_ptr(ASIZE);
FOR n IN 0 TO ASIZE - 1 LOOP
rd_gray_nxt(n) <= rd_ptr(n) XOR rd_ptr(n + 1);
END LOOP;
END PROCESS;
PROCESS (rd_clk)
BEGIN
IF (rd_clk'EVENT AND rd_clk = '1') THEN
IF (rst = '1') THEN
rd_ptr <= (others=> '0');
rd_gray <= (others=> '0');
ELSE
IF (rd_strobe = '1') THEN
rd_ptr <= rd_ptr + 1;
END IF;
rd_ptr_tmp <= rd_ptr;
rd_gray <= rd_gray_nxt;
END IF;
END IF;
END PROCESS;
buf_filled <= wr_capture_ptr - rd_ptr;
PROCESS (rd_clk)
BEGIN
IF (rd_clk'EVENT AND rd_clk = '1') THEN
IF (rst = '1') THEN
empty_xhdl0 <= '1';
ELSIF ((buf_filled = ZERO) OR (buf_filled = ONE AND rd_strobe = '1')) THEN
empty_xhdl0 <= '1';
ELSE
empty_xhdl0 <= '0';
END IF;
END IF;
END PROCESS;
PROCESS (rd_clk)
BEGIN
IF (rd_clk'EVENT AND rd_clk = '1') THEN
IF (rst = '1') THEN
wr_ptr <= (others => '0');
wr_gray <= (others => '0');
ELSE
IF (wr_en = '1') THEN
wr_ptr <= wr_ptr + 1;
END IF;
wr_gray <= wr_gray_nxt;
END IF;
END IF;
END PROCESS;
PROCESS (wr_ptr)
BEGIN
wr_gray_nxt(ASIZE) <= wr_ptr(ASIZE);
FOR n IN 0 TO ASIZE - 1 LOOP
wr_gray_nxt(n) <= wr_ptr(n) XOR wr_ptr(n + 1);
END LOOP;
END PROCESS;
buf_avail <= rd_capture_ptr + FIFO_DEPTH - wr_ptr;
PROCESS (wr_clk)
BEGIN
IF (wr_clk'EVENT AND wr_clk = '1') THEN
IF (rst = '1') THEN
full_xhdl1 <= '0';
ELSIF ((buf_avail = ZERO) OR (buf_avail = ONE AND wr_en = '1')) THEN
full_xhdl1 <= '1';
ELSE
full_xhdl1 <= '0';
END IF;
END IF;
END PROCESS;
almost_full <= almost_full_int;
PROCESS (wr_clk)
BEGIN
IF (wr_clk'EVENT AND wr_clk = '1') THEN
IF (rst = '1') THEN
almost_full_int <= '0';
ELSIF (buf_avail <= 3 AND wr_en = '1') THEN --FIFO_DEPTH
almost_full_int <= '1';
ELSE
almost_full_int <= '0';
END IF;
END IF;
END PROCESS;
END trans;
|
cc0-1.0
|
cpavlina/logicanalyzer
|
la-hdl/ipcore_dir/mig_39_2/user_design/sim/mcb_flow_control.vhd
|
20
|
18501
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: mcb_flow_control.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:16:40 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This module is the main flow control between cmd_gen.v,
-- write_data_path and read_data_path modules.
-- Reference:
-- Revision History:
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
ENTITY mcb_flow_control IS
GENERIC (
TCQ : TIME := 100 ps;
FAMILY : STRING := "SPARTAN6"
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
cmd_rdy_o : OUT STD_LOGIC;
cmd_valid_i : IN STD_LOGIC;
cmd_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bl_i : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
mcb_cmd_full : IN STD_LOGIC;
cmd_o : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bl_o : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
cmd_en_o : OUT STD_LOGIC;
last_word_wr_i : IN STD_LOGIC;
wdp_rdy_i : IN STD_LOGIC;
wdp_valid_o : OUT STD_LOGIC;
wdp_validB_o : OUT STD_LOGIC;
wdp_validC_o : OUT STD_LOGIC;
wr_addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
wr_bl_o : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
last_word_rd_i : IN STD_LOGIC;
rdp_rdy_i : IN STD_LOGIC;
rdp_valid_o : OUT STD_LOGIC;
rd_addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
rd_bl_o : OUT STD_LOGIC_VECTOR(5 DOWNTO 0)
);
END mcb_flow_control;
ARCHITECTURE trans OF mcb_flow_control IS
constant READY : std_logic_vector(4 downto 0) := "00001";
constant READ : std_logic_vector(4 downto 0) := "00010";
constant WRITE : std_logic_vector(4 downto 0) := "00100";
constant CMD_WAIT : std_logic_vector(4 downto 0) := "01000";
constant REFRESH_ST : std_logic_vector(4 downto 0) := "10000";
constant RD : std_logic_vector(2 downto 0) := "001";
constant RDP : std_logic_vector(2 downto 0) := "011";
constant WR : std_logic_vector(2 downto 0) := "000";
constant WRP : std_logic_vector(2 downto 0) := "010";
constant REFRESH : std_logic_vector(2 downto 0) := "100";
constant NOP : std_logic_vector(2 downto 0) := "101";
SIGNAL cmd_fifo_rdy : STD_LOGIC;
SIGNAL cmd_rd : STD_LOGIC;
SIGNAL cmd_wr : STD_LOGIC;
SIGNAL cmd_others : STD_LOGIC;
SIGNAL push_cmd : STD_LOGIC;
SIGNAL xfer_cmd : STD_LOGIC;
SIGNAL rd_vld : STD_LOGIC;
SIGNAL wr_vld : STD_LOGIC;
SIGNAL cmd_rdy : STD_LOGIC;
SIGNAL cmd_reg : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL addr_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL bl_reg : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL rdp_valid : STD_LOGIC;
SIGNAL wdp_valid : STD_LOGIC;
SIGNAL wdp_validB : STD_LOGIC;
SIGNAL wdp_validC : STD_LOGIC;
SIGNAL current_state : STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL next_state : STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL tstpointA : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL push_cmd_r : STD_LOGIC;
SIGNAL wait_done : STD_LOGIC;
SIGNAL cmd_en_r1 : STD_LOGIC;
SIGNAL wr_in_progress : STD_LOGIC;
SIGNAL tst_cmd_rdy_o : STD_LOGIC;
SIGNAL cmd_wr_pending_r1 : STD_LOGIC;
SIGNAL cmd_rd_pending_r1 : STD_LOGIC;
-- Declare intermediate signals for referenced outputs
SIGNAL cmd_rdy_o_xhdl0 : STD_LOGIC;
BEGIN
-- Drive referenced outputs
cmd_rdy_o <= cmd_rdy_o_xhdl0;
cmd_en_o <= cmd_en_r1;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
cmd_rdy_o_xhdl0 <= cmd_rdy;
tst_cmd_rdy_o <= cmd_rdy;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(8)) = '1') THEN
cmd_en_r1 <= '0' ;
ELSIF (xfer_cmd = '1') THEN
cmd_en_r1 <= '1' ;
ELSIF ((NOT(mcb_cmd_full)) = '1') THEN
cmd_en_r1 <= '0' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(9)) = '1') THEN
cmd_fifo_rdy <= '1';
ELSIF (xfer_cmd = '1') THEN
cmd_fifo_rdy <= '0';
ELSIF ((NOT(mcb_cmd_full)) = '1') THEN
cmd_fifo_rdy <= '1';
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(9)) = '1') THEN
addr_o <= (others => '0');
cmd_o <= (others => '0');
bl_o <= (others => '0');
ELSIF (xfer_cmd = '1') THEN
addr_o <= addr_reg;
IF (FAMILY = "SPARTAN6") THEN
cmd_o <= cmd_reg;
ELSE
cmd_o <= ("00" & cmd_reg(0));
END IF;
bl_o <= bl_reg;
END IF;
END IF;
END PROCESS;
wr_addr_o <= addr_i;
rd_addr_o <= addr_i;
rd_bl_o <= bl_i;
wr_bl_o <= bl_i;
wdp_valid_o <= wdp_valid;
wdp_validB_o <= wdp_validB;
wdp_validC_o <= wdp_validC;
rdp_valid_o <= rdp_valid;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(8)) = '1') THEN
wait_done <= '1' ;
ELSIF (push_cmd_r = '1') THEN
wait_done <= '1' ;
ELSIF ((cmd_rdy_o_xhdl0 AND cmd_valid_i) = '1' AND FAMILY = "SPARTAN6") THEN
wait_done <= '0' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
push_cmd_r <= push_cmd ;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (push_cmd = '1') THEN
cmd_reg <= cmd_i ;
addr_reg <= addr_i ;
bl_reg <= bl_i - "000001" ;
END IF;
END IF;
END PROCESS;
cmd_wr <= '1' WHEN (((cmd_i = WR) OR (cmd_i = WRP)) AND (cmd_valid_i = '1')) ELSE
'0';
cmd_rd <= '1' WHEN (((cmd_i = RD) OR (cmd_i = RDP)) AND (cmd_valid_i = '1')) ELSE
'0';
cmd_others <= '1' WHEN ((cmd_i(2) = '1') AND (cmd_valid_i = '1') AND (FAMILY = "SPARTAN6")) ELSE
'0';
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0)= '1') THEN
cmd_wr_pending_r1 <= '0' ;
ELSIF (last_word_wr_i = '1') THEN
cmd_wr_pending_r1 <= '1' ;
ELSIF (push_cmd = '1') THEN
cmd_wr_pending_r1 <= '0' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((cmd_rd AND push_cmd) = '1') THEN
cmd_rd_pending_r1 <= '1' ;
ELSIF (xfer_cmd = '1') THEN
cmd_rd_pending_r1 <= '0' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0)= '1') THEN
wr_in_progress <= '0';
ELSIF (last_word_wr_i = '1') THEN
wr_in_progress <= '0';
ELSIF (current_state = WRITE) THEN
wr_in_progress <= '1';
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0)= '1') THEN
current_state <= "00001" ;
ELSE
current_state <= next_state ;
END IF;
END IF;
END PROCESS;
PROCESS (current_state, rdp_rdy_i, cmd_rd, cmd_fifo_rdy, wdp_rdy_i, cmd_wr, last_word_rd_i, cmd_others, last_word_wr_i, cmd_valid_i, wait_done, wr_in_progress, cmd_wr_pending_r1)
BEGIN
push_cmd <= '0';
xfer_cmd <= '0';
wdp_valid <= '0';
wdp_validB <= '0';
wdp_validC <= '0';
rdp_valid <= '0';
cmd_rdy <= '0';
next_state <= current_state;
CASE current_state IS
WHEN READY =>
IF ((rdp_rdy_i AND cmd_rd AND cmd_fifo_rdy) = '1') THEN
next_state <= READ;
push_cmd <= '1';
xfer_cmd <= '0';
rdp_valid <= '1';
ELSIF ((wdp_rdy_i AND cmd_wr AND cmd_fifo_rdy) = '1') THEN
next_state <= WRITE;
push_cmd <= '1';
wdp_valid <= '1';
wdp_validB <= '1';
wdp_validC <= '1';
ELSIF ((cmd_others AND cmd_fifo_rdy) = '1') THEN
next_state <= REFRESH_ST;
push_cmd <= '1';
xfer_cmd <= '0';
ELSE
next_state <= READY;
push_cmd <= '0';
END IF;
IF (cmd_fifo_rdy = '1') THEN
cmd_rdy <= '1';
ELSE
cmd_rdy <= '0';
END IF;
WHEN REFRESH_ST =>
IF ((rdp_rdy_i AND cmd_rd AND cmd_fifo_rdy) = '1') THEN
next_state <= READ;
push_cmd <= '1';
rdp_valid <= '1';
wdp_valid <= '0';
xfer_cmd <= '1';
ELSIF ((cmd_fifo_rdy AND cmd_wr AND wdp_rdy_i) = '1') THEN
next_state <= WRITE;
push_cmd <= '1';
xfer_cmd <= '1';
wdp_valid <= '1';
wdp_validB <= '1';
wdp_validC <= '1';
ELSIF ((cmd_fifo_rdy and cmd_others) = '1') THEN
push_cmd <= '1';
xfer_cmd <= '1';
ELSIF ((not(cmd_fifo_rdy)) = '1') THEN
next_state <= CMD_WAIT;
tstpointA <= "1001";
ELSE
next_state <= READ;
END IF;
IF ((cmd_fifo_rdy AND ((rdp_rdy_i AND cmd_rd) OR (wdp_rdy_i AND cmd_wr) OR (cmd_others))) = '1') THEN
cmd_rdy <= '1';
ELSE
cmd_rdy <= '0';
END IF;
WHEN READ =>
IF ((rdp_rdy_i AND cmd_rd AND cmd_fifo_rdy) = '1') THEN
next_state <= READ;
push_cmd <= '1';
rdp_valid <= '1';
wdp_valid <= '0';
xfer_cmd <= '1';
tstpointA <= "0101";
ELSIF ((cmd_fifo_rdy AND cmd_wr AND wdp_rdy_i) = '1') THEN
next_state <= WRITE;
push_cmd <= '1';
xfer_cmd <= '1';
wdp_valid <= '1';
wdp_validB <= '1';
wdp_validC <= '1';
tstpointA <= "0110";
ELSIF ((NOT(rdp_rdy_i)) = '1') THEN
next_state <= READ;
push_cmd <= '0';
xfer_cmd <= '0';
tstpointA <= "0111";
wdp_valid <= '0';
wdp_validB <= '0';
wdp_validC <= '0';
rdp_valid <= '0';
ELSIF ((last_word_rd_i AND cmd_others AND cmd_fifo_rdy) = '1') THEN
next_state <= REFRESH_ST;
push_cmd <= '1';
xfer_cmd <= '1';
wdp_valid <= '0';
wdp_validB <= '0';
wdp_validC <= '0';
rdp_valid <= '0';
tstpointA <= "1000";
ELSIF ((NOT(cmd_fifo_rdy) OR NOT(wdp_rdy_i)) = '1') THEN
next_state <= CMD_WAIT;
tstpointA <= "1001";
ELSE
next_state <= READ;
END IF;
IF ((((rdp_rdy_i AND cmd_rd) OR (cmd_wr AND wdp_rdy_i) OR cmd_others) AND cmd_fifo_rdy) = '1') THEN
cmd_rdy <= wait_done; --'1';
ELSE
cmd_rdy <= '0';
END IF;
WHEN WRITE =>
IF ((cmd_fifo_rdy AND cmd_rd AND rdp_rdy_i AND last_word_wr_i) = '1') THEN
next_state <= READ;
push_cmd <= '1';
xfer_cmd <= '1';
rdp_valid <= '1';
tstpointA <= "0000";
ELSIF ((NOT(wdp_rdy_i) OR (wdp_rdy_i AND cmd_wr AND cmd_fifo_rdy AND last_word_wr_i)) = '1') THEN
next_state <= WRITE;
tstpointA <= "0001";
IF ((cmd_wr AND last_word_wr_i) = '1') THEN
wdp_valid <= '1';
wdp_validB <= '1';
wdp_validC <= '1';
ELSE
wdp_valid <= '0';
wdp_validB <= '0';
wdp_validC <= '0';
END IF;
IF (last_word_wr_i = '1') THEN
push_cmd <= '1';
xfer_cmd <= '1';
ELSE
push_cmd <= '0';
xfer_cmd <= '0';
END IF;
ELSIF ((last_word_wr_i AND cmd_others AND cmd_fifo_rdy) = '1') THEN
next_state <= REFRESH_ST;
push_cmd <= '1';
xfer_cmd <= '1';
tstpointA <= "0010";
wdp_valid <= '0';
wdp_validB <= '0';
wdp_validC <= '0';
rdp_valid <= '0';
ELSIF ((((NOT(cmd_fifo_rdy)) AND last_word_wr_i) OR (NOT(rdp_rdy_i)) OR (NOT(cmd_valid_i) AND wait_done)) = '1') THEN
next_state <= CMD_WAIT;
push_cmd <= '0';
xfer_cmd <= '0';
tstpointA <= "0011";
ELSE
next_state <= WRITE;
tstpointA <= "0100";
END IF;
IF ((last_word_wr_i AND (cmd_others OR (rdp_rdy_i AND cmd_rd) OR (cmd_wr AND wdp_rdy_i)) AND cmd_fifo_rdy) = '1') THEN
cmd_rdy <= wait_done;
ELSE
cmd_rdy <= '0';
END IF;
WHEN CMD_WAIT =>
IF ((NOT(cmd_fifo_rdy) OR wr_in_progress) = '1') THEN
next_state <= CMD_WAIT;
cmd_rdy <= '0';
tstpointA <= "1010";
ELSIF ((cmd_fifo_rdy AND rdp_rdy_i AND cmd_rd) = '1') THEN
next_state <= READ;
push_cmd <= '1';
xfer_cmd <= '1';
cmd_rdy <= '1';
rdp_valid <= '1';
tstpointA <= "1011";
ELSIF ((cmd_fifo_rdy AND cmd_wr AND (wait_done OR cmd_wr_pending_r1)) = '1') THEN
next_state <= WRITE;
push_cmd <= '1';
xfer_cmd <= '1';
wdp_valid <= '1';
wdp_validB <= '1';
wdp_validC <= '1';
cmd_rdy <= '1';
tstpointA <= "1100";
ELSIF ((cmd_fifo_rdy AND cmd_others) = '1') THEN
next_state <= REFRESH_ST;
push_cmd <= '1';
xfer_cmd <= '1';
tstpointA <= "1101";
cmd_rdy <= '1';
ELSE
next_state <= CMD_WAIT;
tstpointA <= "1110";
IF (((wdp_rdy_i AND rdp_rdy_i)) = '1') THEN
cmd_rdy <= '1';
ELSE
cmd_rdy <= '0';
END IF;
END IF;
WHEN OTHERS =>
push_cmd <= '0';
xfer_cmd <= '0';
wdp_valid <= '0';
wdp_validB <= '0';
wdp_validC <= '0';
next_state <= READY;
END CASE;
END PROCESS;
END trans;
|
cc0-1.0
|
qu1x/fsio
|
src/lib/fsio.vhd
|
1
|
2654
|
-- This file is part of fsio, see <https://qu1x.org/fsio>.
--
-- Copyright (c) 2016 Rouven Spreckels <[email protected]>
--
-- fsio is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Affero General Public License version 3
-- as published by the Free Software Foundation on 19 November 2007.
--
-- fsio is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Affero General Public License for more details.
--
-- You should have received a copy of the GNU Affero General Public License
-- along with fsio. If not, see <https://www.gnu.org/licenses>.
library ieee;
use ieee.std_logic_1164.all;
package fsio is
constant CAP: integer := 32;
constant LEN: integer := CAP;
component fsio_get is
generic (
-- Number of signals of all data maps
cap: integer := CAP;
-- Number of signals of all data maps actually being used
len: integer := LEN
);
port (
-- AXI core clock
clk: in std_logic;
-- AXI handshake input
hsi: in std_logic;
-- AXI handshake output as conditional feedback
hso: out std_logic;
-- AXI data input of all data maps
fsi: in std_logic_vector(cap - 1 downto 0);
-- AXI data output as feedback of all data maps
fso: out std_logic_vector(cap - 1 downto 0);
-- User data of all data maps to be read
dat: out std_logic_vector(len - 1 downto 0);
-- PS requests PL to read the data
-- Is set until acknowledged and the data has been fed back
req: out std_logic;
-- PL acknowledges when it has read the data
-- Must be kept set until request has been reset
ack: in std_logic
);
end component fsio_get;
component fsio_put is
generic (
-- Number of signals of all data maps
cap: integer := CAP;
-- Number of signals of all data maps actually being used
len: integer := LEN
);
port (
-- AXI core clock
clk: in std_logic;
-- AXI handshake input
hsi: in std_logic;
-- AXI handshake output as conditional feedback
hso: out std_logic;
-- AXI data input as feedback of all data maps
fsi: in std_logic_vector(cap - 1 downto 0);
-- AXI data output of all data maps
fso: out std_logic_vector(cap - 1 downto 0);
-- User data of all data maps to be written
dat: in std_logic_vector(len - 1 downto 0);
-- PS requests PL to write the data
-- Is set until acknowledged
req: out std_logic;
-- PL acknowledges when it has written the data
-- Must be set for exactly one clock cycle
ack: in std_logic
);
end component fsio_put;
end package;
|
agpl-3.0
|
cpavlina/logicanalyzer
|
la-hdl/ipcore_dir/mig_39_2/example_design/rtl/traffic_gen/cmd_gen.vhd
|
20
|
39433
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: cmd_gen.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/05/27 15:50:27 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This module genreates different type of commands, address,
-- burst_length to mcb_flow_control module.
-- Reference:
-- Revision History:
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
ENTITY cmd_gen IS
GENERIC (
FAMILY : STRING := "SPARTAN6";
MEM_BURST_LEN : INTEGER := 8;
TCQ : TIME := 100 ps;
PORT_MODE : STRING := "BI_MODE";
NUM_DQ_PINS : INTEGER := 8;
DATA_PATTERN : STRING := "DGEN_ALL";
CMD_PATTERN : STRING := "CGEN_ALL";
ADDR_WIDTH : INTEGER := 30;
DWIDTH : INTEGER := 32;
PIPE_STAGES : INTEGER := 0;
MEM_COL_WIDTH : INTEGER := 10;
PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"FFFFD000";
PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00002000";
PRBS_EADDR : std_logic_vector(31 downto 0) := X"00002000";
PRBS_SADDR : std_logic_vector(31 downto 0) := X"00002000"
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
run_traffic_i : IN STD_LOGIC;
rd_buff_avail_i : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
force_wrcmd_gen_i : IN STD_LOGIC;
start_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
end_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
cmd_seed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
data_seed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
load_seed_i : IN STD_LOGIC;
addr_mode_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
data_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
instr_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
bl_mode_i : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
mode_load_i : IN STD_LOGIC;
fixed_bl_i : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
fixed_instr_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
fixed_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_instr_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
bram_bl_i : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
bram_valid_i : IN STD_LOGIC;
bram_rdy_o : OUT STD_LOGIC;
reading_rd_data_i : IN STD_LOGIC;
rdy_i : IN STD_LOGIC;
addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
instr_o : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
bl_o : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
-- m_addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
cmd_o_vld : OUT STD_LOGIC
);
END cmd_gen;
ARCHITECTURE trans OF cmd_gen IS
constant PRBS_ADDR_WIDTH : INTEGER := 32;
constant INSTR_PRBS_WIDTH : INTEGER := 16;
constant BL_PRBS_WIDTH : INTEGER := 16;
constant BRAM_DATAL_MODE : std_logic_vector(3 downto 0) := "0000";
constant FIXED_DATA_MODE : std_logic_vector(3 downto 0) := "0001";
constant ADDR_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
constant HAMMER_DATA_MODE : std_logic_vector(3 downto 0) := "0011";
constant NEIGHBOR_DATA_MODE : std_logic_vector(3 downto 0) := "0100";
constant WALKING1_DATA_MODE : std_logic_vector(3 downto 0) := "0101";
constant WALKING0_DATA_MODE : std_logic_vector(3 downto 0) := "0110";
constant PRBS_DATA_MODE : std_logic_vector(3 downto 0) := "0111";
COMPONENT pipeline_inserter IS
GENERIC (
DATA_WIDTH : INTEGER := 32;
PIPE_STAGES : INTEGER := 1
);
PORT (
data_i : IN STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0);
clk_i : IN STD_LOGIC;
en_i : IN STD_LOGIC;
data_o : OUT STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT cmd_prbs_gen IS
GENERIC (
TCQ : time := 100 ps;
FAMILY : STRING := "SPARTAN6";
ADDR_WIDTH : INTEGER := 29;
DWIDTH : INTEGER := 32;
PRBS_CMD : STRING := "ADDRESS";
PRBS_WIDTH : INTEGER := 64;
SEED_WIDTH : INTEGER := 32;
PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"FFFFD000";
PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00002000";
PRBS_EADDR : std_logic_vector(31 downto 0) := X"00002000";
PRBS_SADDR : std_logic_vector(31 downto 0) := X"00002000"
);
PORT (
clk_i : IN STD_LOGIC;
prbs_seed_init : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
prbs_seed_i : IN STD_LOGIC_VECTOR(SEED_WIDTH - 1 DOWNTO 0);
prbs_o : OUT STD_LOGIC_VECTOR(SEED_WIDTH - 1 DOWNTO 0)
);
END COMPONENT;
function BOOLEAN_TO_STD_LOGIC(A : in BOOLEAN) return std_logic is
begin
if A = true then
return '1';
else
return '0';
end if;
end function BOOLEAN_TO_STD_LOGIC;
SIGNAL INC_COUNTS : STD_LOGIC_VECTOR(10 DOWNTO 0);
SIGNAL addr_mode_reg : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL bl_mode_reg : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL addr_counts : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL prbs_bl : STD_LOGIC_VECTOR(14 DOWNTO 0);
SIGNAL instr_out : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL prbs_instr_a : STD_LOGIC_VECTOR(14 DOWNTO 0);
SIGNAL prbs_instr_b : STD_LOGIC_VECTOR(14 DOWNTO 0);
SIGNAL prbs_brlen : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL prbs_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL seq_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL fixed_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL bl_out : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL bl_out_reg : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL mode_load_d1 : STD_LOGIC;
SIGNAL mode_load_d2 : STD_LOGIC;
SIGNAL mode_load_pulse : STD_LOGIC;
SIGNAL pipe_data_o : STD_LOGIC_VECTOR(41 DOWNTO 0);
SIGNAL cmd_clk_en : STD_LOGIC;
SIGNAL pipe_out_vld : STD_LOGIC;
SIGNAL end_addr_range : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL force_bl1 : STD_LOGIC;
SIGNAL A0_G_E0 : STD_LOGIC;
SIGNAL A1_G_E1 : STD_LOGIC;
SIGNAL A2_G_E2 : STD_LOGIC;
SIGNAL A3_G_E3 : STD_LOGIC;
SIGNAL AC3_G_E3 : STD_LOGIC;
SIGNAL AC2_G_E2 : STD_LOGIC;
SIGNAL AC1_G_E1 : STD_LOGIC;
SIGNAL bl_out_clk_en : STD_LOGIC;
SIGNAL pipe_data_in : STD_LOGIC_VECTOR(41 DOWNTO 0);
SIGNAL instr_vld : STD_LOGIC;
SIGNAL bl_out_vld : STD_LOGIC;
SIGNAL cmd_vld : STD_LOGIC;
SIGNAL run_traffic_r : STD_LOGIC;
SIGNAL run_traffic_pulse : STD_LOGIC;
SIGNAL pipe_data_in_vld : STD_LOGIC;
SIGNAL gen_addr_larger : STD_LOGIC;
SIGNAL buf_avail_r : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL rd_data_received_counts : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL rd_data_counts_asked : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL rd_data_received_counts_total : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL instr_vld_dly1 : STD_LOGIC;
SIGNAL first_load_pulse : STD_LOGIC;
SIGNAL mem_init_done : STD_LOGIC;
SIGNAL i : INTEGER;
SIGNAL force_wrcmd_gen : STD_LOGIC;
SIGNAL force_smallvalue : STD_LOGIC;
SIGNAL end_addr_r : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL force_rd_counts : STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL force_rd : STD_LOGIC;
SIGNAL addr_counts_next_r : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL refresh_cmd_en : STD_LOGIC;
SIGNAL refresh_timer : STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL refresh_prbs : STD_LOGIC;
SIGNAL cmd_clk_en_r : STD_LOGIC;
signal instr_mode_reg : std_logic_vector(3 downto 0);
-- X-HDL generated signals
SIGNAL xhdl4 : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL xhdl12 : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL xhdl14 : STD_LOGIC_VECTOR(5 DOWNTO 0);
-- Declare intermediate signals for referenced outputs
SIGNAL bl_o_xhdl0 : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL mode_load_pulse_r1 : STD_LOGIC;
BEGIN
-- Drive referenced outputs
bl_o <= bl_o_xhdl0;
addr_o <= pipe_data_o(31 DOWNTO 0);
instr_o <= pipe_data_o(34 DOWNTO 32);
bl_o_xhdl0 <= pipe_data_o(40 DOWNTO 35);
cmd_o_vld <= pipe_data_o(41) AND run_traffic_r;
pipe_out_vld <= pipe_data_o(41) AND run_traffic_r;
pipe_data_o <= pipe_data_in;
cv1 : IF (CMD_PATTERN = "CGEN_BRAM") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
cmd_vld <= cmd_clk_en;
END IF;
END PROCESS;
END GENERATE;
cv3 : IF (CMD_PATTERN = "CGEN_PRBS" OR CMD_PATTERN = "CGEN_ALL" OR CMD_PATTERN = "CGEN_SEQUENTIAL" OR CMD_PATTERN = "CGEN_FIXED") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
cmd_vld <= cmd_clk_en OR (mode_load_pulse AND first_load_pulse);
END IF;
END PROCESS;
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
run_traffic_r <= run_traffic_i ;
IF ( run_traffic_i= '1' AND run_traffic_r = '0' ) THEN
run_traffic_pulse <= '1' ;
ELSE
run_traffic_pulse <= '0' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
instr_vld <= cmd_clk_en OR (mode_load_pulse AND first_load_pulse) ;
bl_out_clk_en <= cmd_clk_en OR (mode_load_pulse AND first_load_pulse) ;
bl_out_vld <= bl_out_clk_en ;
pipe_data_in_vld <= instr_vld ;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0) = '1') THEN
first_load_pulse <= '1' ;
ELSIF (mode_load_pulse = '1') THEN
first_load_pulse <= '0' ;
ELSE
first_load_pulse <= first_load_pulse ;
END IF;
END IF;
END PROCESS;
cmd_clk_en <= (rdy_i AND pipe_out_vld AND run_traffic_i) OR (mode_load_pulse AND BOOLEAN_TO_STD_LOGIC(CMD_PATTERN = "CGEN_BRAM"));
pipe_in_s6 : IF (FAMILY = "SPARTAN6") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(0)) = '1') THEN
pipe_data_in(31 DOWNTO 0) <= start_addr_i ;
ELSIF (instr_vld = '1') THEN
IF (gen_addr_larger = '1' AND (addr_mode_reg = "100" OR addr_mode_reg = "010")) THEN
IF (DWIDTH = 32) THEN
pipe_data_in(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 8) & "00000000") ;
ELSIF (DWIDTH = 64) THEN
pipe_data_in(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 9) & "000000000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 10) & "0000000000") ;
END IF;
ELSE
IF (DWIDTH = 32) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 2) & "00") ;
ELSIF (DWIDTH = 64) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000") ;
ELSIF (DWIDTH = 128) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) & "0000") ;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
pipe_in_v6 : IF (FAMILY = "VIRTEX6") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(1)) = '1') THEN
pipe_data_in(31 DOWNTO 0) <= start_addr_i ;
ELSIF (instr_vld = '1') THEN
IF (gen_addr_larger = '1' AND (addr_mode_reg = "100" OR addr_mode_reg = "010")) THEN
pipe_data_in(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 8) & "00000000") ;
ELSIF ((NUM_DQ_PINS >= 128) AND (NUM_DQ_PINS <= 144)) THEN
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 7) & "0000000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 6) & "000000") ;
END IF;
ELSIF ((NUM_DQ_PINS >= 64) AND (NUM_DQ_PINS < 128)) THEN
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 6) & "000000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 5) & "00000") ;
END IF;
ELSIF ((NUM_DQ_PINS = 32) OR (NUM_DQ_PINS = 40) OR (NUM_DQ_PINS = 48) OR (NUM_DQ_PINS = 56)) THEN
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 5) & "00000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) & "0000") ;
END IF;
ELSIF ((NUM_DQ_PINS = 16) OR (NUM_DQ_PINS = 24)) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000");
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) & "0000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000") ;
END IF;
ELSIF (NUM_DQ_PINS = 8) THEN
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 2) & "00") ;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
-- pipe_m_addr_o : IF (FAMILY = "VIRTEX6") GENERATE
-- PROCESS (clk_i)
-- BEGIN
-- IF (clk_i'EVENT AND clk_i = '1') THEN
-- IF ((rst_i(1)) = '1') THEN
-- m_addr_o(31 DOWNTO 0) <= start_addr_i ;
-- ELSIF (instr_vld = '1') THEN
-- IF (gen_addr_larger = '1' AND (addr_mode_reg = "100" OR addr_mode_reg = "010")) THEN
-- m_addr_o(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 8) & "00000000") ;
--
-- ELSIF ((NUM_DQ_PINS >= 128) AND (NUM_DQ_PINS < 256)) THEN
-- m_addr_o <= (addr_out(31 DOWNTO 6) & "000000") ;
--
-- ELSIF ((NUM_DQ_PINS >= 64) AND (NUM_DQ_PINS < 128)) THEN
-- m_addr_o <= (addr_out(31 DOWNTO 5) & "00000") ;
-- ELSIF ((NUM_DQ_PINS = 32) OR (NUM_DQ_PINS = 40) OR (NUM_DQ_PINS = 48) OR (NUM_DQ_PINS = 56)) THEN
-- m_addr_o(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) & "0000") ;
-- ELSIF ((NUM_DQ_PINS = 16) OR (NUM_DQ_PINS = 17)) THEN
-- m_addr_o(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000") ;
-- ELSIF ((NUM_DQ_PINS = 8) OR (NUM_DQ_PINS = 9)) THEN
-- m_addr_o(31 DOWNTO 0) <= (addr_out(31 DOWNTO 2) & "00") ;
-- END IF;
-- END IF;
-- END IF;
-- END PROCESS;
--
-- END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0) = '1') THEN
force_wrcmd_gen <= '0' ;
ELSIF (buf_avail_r = "0111111") THEN
force_wrcmd_gen <= '0' ;
ELSIF (instr_vld_dly1 = '1' AND pipe_data_in(32) = '1' AND pipe_data_in(41 DOWNTO 35) > "0010000") THEN
force_wrcmd_gen <= '1' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
instr_mode_reg <= instr_mode_i ;
END IF;
END PROCESS;
-- **********************************************
PROCESS (clk_i) BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(2)) = '1') THEN
pipe_data_in(40 DOWNTO 32) <= "000000000";
force_smallvalue <= '0';
ELSIF (instr_vld = '1') THEN
IF (instr_mode_reg = 0) THEN
pipe_data_in(34 DOWNTO 32) <= instr_out ;
ELSIF (instr_out(2) = '1') THEN
pipe_data_in(34 DOWNTO 32) <= "100" ;
ELSIF (FAMILY = "SPARTAN6" AND PORT_MODE = "RD_MODE") THEN
pipe_data_in(34 DOWNTO 32) <= instr_out(2 downto 1) & '1' ;
ELSIF ((force_wrcmd_gen = '1' OR buf_avail_r <= "0001111") AND FAMILY = "SPARTAN6" AND PORT_MODE /= "RD_MODE") THEN
pipe_data_in(34 DOWNTO 32) <= instr_out(2) & "00";
ELSE
pipe_data_in(34 DOWNTO 32) <= instr_out;
END IF;
----********* condition the generated bl value except if TG is programmed for BRAM interface'
---- if the generated address is close to end address range, the bl_out will be altered to 1.
--
IF (bl_mode_i = 0) THEN
pipe_data_in(40 DOWNTO 35) <= bl_out ;
ELSIF ( FAMILY = "VIRTEX6") THEN
pipe_data_in(40 DOWNTO 35) <= bl_out ;
ELSIF (force_bl1 = '1' AND (bl_mode_reg = "10") AND FAMILY = "SPARTAN6") THEN
pipe_data_in(40 DOWNTO 35) <= "000001" ;
-- **********************************************
ELSIF (buf_avail_r(5 DOWNTO 0) >= "111100" AND buf_avail_r(6) = '0' AND pipe_data_in(32) = '1' AND FAMILY = "SPARTAN6") THEN
IF (bl_mode_reg = "10") THEN
force_smallvalue <= NOT(force_smallvalue) ;
END IF;
IF (buf_avail_r(6) = '1' AND bl_mode_reg = "10") THEN
pipe_data_in(40 DOWNTO 35) <= ("00" & bl_out(3 DOWNTO 1) & '1') ;
ELSE
pipe_data_in(40 DOWNTO 35) <= bl_out ;
END IF;
ELSIF (buf_avail_r < "1000000" AND rd_buff_avail_i >= "0000000" AND instr_out(0) = '1' AND (bl_mode_reg = "10")) THEN
IF (FAMILY = "SPARTAN6") THEN
pipe_data_in(40 DOWNTO 35) <= ("00" & bl_out(3 DOWNTO 0)) + '1' ;
ELSE
pipe_data_in(40 DOWNTO 35) <= bl_out ;
END IF;
END IF; --IF (bl_mode_i = 0) THEN
END IF; --IF ((rst_i(2)) = '1') THEN
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(2)) = '1') THEN
pipe_data_in(41) <= '0' ;
ELSIF (cmd_vld = '1') THEN
pipe_data_in(41) <= instr_vld ;
ELSIF ((rdy_i AND pipe_out_vld) = '1') THEN
pipe_data_in(41) <= '0' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
instr_vld_dly1 <= instr_vld;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0) = '1') THEN
rd_data_counts_asked <= (others => '0') ;
ELSIF (instr_vld_dly1 = '1' AND pipe_data_in(32) = '1') THEN
IF (pipe_data_in(40 DOWNTO 35) = "000000") THEN
rd_data_counts_asked <= rd_data_counts_asked + 64 ;
ELSE
rd_data_counts_asked <= rd_data_counts_asked + ('0' & (pipe_data_in(40 DOWNTO 35)));
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0) = '1') THEN
rd_data_received_counts <= (others => '0');
rd_data_received_counts_total <= (others => '0');
ELSIF (reading_rd_data_i = '1') THEN
rd_data_received_counts <= rd_data_received_counts + '1';
rd_data_received_counts_total <= rd_data_received_counts_total + "0000000000000001";
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
buf_avail_r <= (rd_data_received_counts + 64) - rd_data_counts_asked;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(3)) = '1') THEN
IF (CMD_PATTERN = "CGEN_BRAM") THEN
addr_mode_reg <= "000";
ELSE
addr_mode_reg <= "011";
END IF;
ELSIF (mode_load_pulse = '1') THEN
addr_mode_reg <= addr_mode_i;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (mode_load_pulse = '1') THEN
bl_mode_reg <= bl_mode_i;
END IF;
mode_load_d1 <= mode_load_i;
mode_load_d2 <= mode_load_d1;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
mode_load_pulse <= mode_load_d1 AND NOT(mode_load_d2);
END IF;
END PROCESS;
xhdl4 <= addr_mode_reg;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(3)) = '1') THEN
addr_out <= start_addr_i;
ELSE
CASE xhdl4 IS
WHEN "000" =>
addr_out <= bram_addr_i;
WHEN "001" =>
addr_out <= fixed_addr;
WHEN "010" =>
addr_out <= prbs_addr;
WHEN "011" =>
addr_out <= ("00" & seq_addr(29 DOWNTO 0));
WHEN "100" =>
-- addr_out <= (prbs_addr(31 DOWNTO 6) & "000000");
addr_out <= ("000" & seq_addr(6 DOWNTO 2) & seq_addr(23 DOWNTO 0));--(prbs_addr(31 DOWNTO 6) & "000000");
WHEN "101" =>
addr_out <= (prbs_addr(31 DOWNTO 20) & seq_addr(19 DOWNTO 0));
-- addr_out <= (prbs_addr(31 DOWNTO MEM_COL_WIDTH) & seq_addr(MEM_COL_WIDTH - 1 DOWNTO 0));
WHEN OTHERS =>
addr_out <= (others => '0');--"00000000000000000000000000000000";
END CASE;
END IF;
END IF;
END PROCESS;
xhdl5 : IF (CMD_PATTERN = "CGEN_PRBS" OR CMD_PATTERN = "CGEN_ALL") GENERATE
addr_prbs_gen : cmd_prbs_gen
GENERIC MAP (
family => FAMILY,
addr_width => 32,
dwidth => DWIDTH,
prbs_width => 32,
seed_width => 32,
prbs_eaddr_mask_pos => PRBS_EADDR_MASK_POS,
prbs_saddr_mask_pos => PRBS_SADDR_MASK_POS,
prbs_eaddr => PRBS_EADDR,
prbs_saddr => PRBS_SADDR
)
PORT MAP (
clk_i => clk_i,
clk_en => cmd_clk_en,
prbs_seed_init => mode_load_pulse,
prbs_seed_i => cmd_seed_i(31 DOWNTO 0),
prbs_o => prbs_addr
);
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (addr_out(31 DOWNTO 8) >= end_addr_i(31 DOWNTO 8)) THEN
gen_addr_larger <= '1';
ELSE
gen_addr_larger <= '0';
END IF;
END IF;
END PROCESS;
xhdl6 : IF (FAMILY = "SPARTAN6") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (mem_init_done = '1') THEN
INC_COUNTS <= std_logic_vector(to_unsigned((DWIDTH/8 * to_integer(unsigned(bl_out_reg))),11));
ELSE
IF (fixed_bl_i = "000000") THEN
INC_COUNTS <= std_logic_vector(to_unsigned((DWIDTH/8)*(64), 11));
ELSE
INC_COUNTS <= std_logic_vector(to_unsigned((DWIDTH/8 * to_integer(unsigned(fixed_bl_i))),11));
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
xhdl7 : IF (FAMILY = "VIRTEX6") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (NUM_DQ_PINS >= 128 AND NUM_DQ_PINS <= 144) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(64 * (MEM_BURST_LEN/4), 11));
ELSIF (NUM_DQ_PINS >= 64 AND NUM_DQ_PINS < 128) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(32 * (MEM_BURST_LEN/4), 11));
ELSIF (NUM_DQ_PINS >= 32 AND NUM_DQ_PINS < 64) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(16 * (MEM_BURST_LEN/4), 11));
ELSIF (NUM_DQ_PINS = 16 OR NUM_DQ_PINS = 24) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(8 * (MEM_BURST_LEN/4), 11));
ELSIF (NUM_DQ_PINS = 8 OR NUM_DQ_PINS = 9) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(4 * (MEM_BURST_LEN/4), 11));
END IF;
END IF;
END PROCESS;
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
end_addr_r <= end_addr_i - std_logic_vector(to_unsigned(DWIDTH/8*to_integer(unsigned(fixed_bl_i)),32)) + "00000000000000000000000000000001";
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (addr_out(31 DOWNTO 24) >= end_addr_r(31 DOWNTO 24)) THEN
AC3_G_E3 <= '1';
ELSE
AC3_G_E3 <= '0';
END IF;
IF (addr_out(23 DOWNTO 16) >= end_addr_r(23 DOWNTO 16)) THEN
AC2_G_E2 <= '1';
ELSE
AC2_G_E2 <= '0';
END IF;
IF (addr_out(15 DOWNTO 8) >= end_addr_r(15 DOWNTO 8)) THEN
AC1_G_E1 <= '1';
ELSE
AC1_G_E1 <= '0';
END IF;
END IF;
END PROCESS;
-- xhdl8 : IF (CMD_PATTERN = "CGEN_SEQUENTIAL" OR CMD_PATTERN = "CGEN_ALL") GENERATE
seq_addr <= addr_counts;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
mode_load_pulse_r1 <= mode_load_pulse;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
end_addr_range <= end_addr_i(15 DOWNTO 0) - std_logic_vector(to_unsigned((DWIDTH/8 * to_integer(unsigned(bl_out_reg))),16)) + "0000000000000001";
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
addr_counts_next_r <= addr_counts + (INC_COUNTS);
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
cmd_clk_en_r <= cmd_clk_en;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
addr_counts <= start_addr_i;
mem_init_done <= '0';
ELSIF ((cmd_clk_en_r OR mode_load_pulse_r1) = '1') THEN
-- IF ((DWIDTH = 32 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND (addr_counts(7 DOWNTO 0) >= end_addr_r(7 DOWNTO 0))) OR (DWIDTH = 64 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND (addr_counts(7 DOWNTO 0) >= end_addr_r(7 DOWNTO 0))) OR ((DWIDTH = 128 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND FAMILY = "SPARTAN6") OR (DWIDTH = 128 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND (addr_counts(7 DOWNTO 0) >= end_addr_r(7 DOWNTO 0)) AND FAMILY = "VIRTEX6") OR (DWIDTH >= 256 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND (addr_counts(7 DOWNTO 0) >= end_addr_r(7 DOWNTO 0)) AND FAMILY = "VIRTEX6"))) THEN
IF (addr_counts_next_r >= end_addr_i) THEN
addr_counts <= start_addr_i;
mem_init_done <= '1';
ELSIF (addr_counts < end_addr_r) THEN
addr_counts <= addr_counts + INC_COUNTS;
END IF;
END IF;
END IF;
END PROCESS;
--END GENERATE;
xhdl9 : IF (CMD_PATTERN = "CGEN_FIXED" OR CMD_PATTERN = "CGEN_ALL") GENERATE
fixed_addr <= (fixed_addr_i(31 DOWNTO 2) & "00") WHEN (DWIDTH = 32) ELSE
(fixed_addr_i(31 DOWNTO 3) & "000") WHEN (DWIDTH = 64) ELSE
(fixed_addr_i(31 DOWNTO 4) & "0000") WHEN (DWIDTH = 128) ELSE
(fixed_addr_i(31 DOWNTO 5) & "00000") WHEN (DWIDTH = 256) ELSE
(fixed_addr_i(31 DOWNTO 6) & "000000");
END GENERATE;
xhdl10 : IF (CMD_PATTERN = "CGEN_BRAM" OR CMD_PATTERN = "CGEN_ALL") GENERATE
bram_rdy_o <= (run_traffic_i AND cmd_clk_en AND bram_valid_i) OR (mode_load_pulse);
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
force_rd_counts <= (others => '0');--"0000000000";
ELSIF (instr_vld = '1') THEN
force_rd_counts <= force_rd_counts + "0000000001";
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
force_rd <= '0';
ELSIF ((force_rd_counts(3)) = '1') THEN
force_rd <= '1';
ELSE
force_rd <= '0';
END IF;
END IF;
END PROCESS;
-- adding refresh timer to limit the amount of issuing refresh command.
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
refresh_timer <= (others => '0');
ELSE
refresh_timer <= refresh_timer + 1;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
refresh_cmd_en <= '0';
ELSIF (refresh_timer = "1111111111") THEN
refresh_cmd_en <= '1';
ELSIF ((cmd_clk_en and refresh_cmd_en) = '1') THEN
refresh_cmd_en <= '0';
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (FAMILY = "SPARTAN6") THEN
refresh_prbs <= prbs_instr_b(3) and refresh_cmd_en;
ELSE
refresh_prbs <= '0';
END IF;
END IF;
END PROCESS;
--synthesis translate_off
PROCESS (instr_mode_i)
BEGIN
IF ((instr_mode_i > "0010") and (FAMILY = "VIRTEX6")) THEN
report "Error ! Not valid instruction mode";
END IF;
END PROCESS;
--synthesis translate_on
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
CASE instr_mode_i IS
WHEN "0000" =>
instr_out <= bram_instr_i;
WHEN "0001" =>
instr_out <= fixed_instr_i;
WHEN "0010" =>
instr_out <= ("00" & (prbs_instr_a(0) OR force_rd));
WHEN "0011" =>
instr_out <= ("00" & prbs_instr_a(0));
WHEN "0100" =>
instr_out <= ('0' & prbs_instr_b(0) & prbs_instr_a(0));
WHEN "0101" =>
instr_out <= (refresh_prbs & prbs_instr_b(0) & prbs_instr_a(0));
WHEN OTHERS =>
instr_out <= ("00" & prbs_instr_a(0));
END CASE;
END IF;
END PROCESS;
xhdl11 : IF (CMD_PATTERN = "CGEN_PRBS" OR CMD_PATTERN = "CGEN_ALL") GENERATE
instr_prbs_gen_a : cmd_prbs_gen
GENERIC MAP (
prbs_cmd => "INSTR",
family => FAMILY,
addr_width => 32,
seed_width => 15,
prbs_width => 20
)
PORT MAP (
clk_i => clk_i,
clk_en => cmd_clk_en,
prbs_seed_init => load_seed_i,
prbs_seed_i => cmd_seed_i(14 DOWNTO 0),
prbs_o => prbs_instr_a
);
instr_prbs_gen_b : cmd_prbs_gen
GENERIC MAP (
prbs_cmd => "INSTR",
family => FAMILY,
seed_width => 15,
prbs_width => 20
)
PORT MAP (
clk_i => clk_i,
clk_en => cmd_clk_en,
prbs_seed_init => load_seed_i,
prbs_seed_i => cmd_seed_i(16 DOWNTO 2),
prbs_o => prbs_instr_b
);
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (addr_out(31 DOWNTO 24) >= end_addr_i(31 DOWNTO 24)) THEN
A3_G_E3 <= '1' ;
ELSE
A3_G_E3 <= '0' ;
END IF;
IF (addr_out(23 DOWNTO 16) >= end_addr_i(23 DOWNTO 16)) THEN
A2_G_E2 <= '1' ;
ELSE
A2_G_E2 <= '0' ;
END IF;
IF (addr_out(15 DOWNTO 8) >= end_addr_i(15 DOWNTO 8)) THEN
A1_G_E1 <= '1' ;
ELSE
A1_G_E1 <= '0' ;
END IF;
IF (addr_out(7 DOWNTO 0) > (end_addr_i(7 DOWNTO 0) - std_logic_vector(to_unsigned((DWIDTH/8)*to_integer(unsigned(bl_out) ),32)) + '1') ) THEN -- OK
A0_G_E0 <= '1' ;
ELSE
A0_G_E0 <= '0' ;
END IF;
END IF;
END PROCESS;
--testout <= std_logic_vector(to_unsigned((DWIDTH/8)*to_integer(unsigned(bl_out) ),testout'length)) + '1';
PROCESS (addr_out,buf_avail_r, bl_out, end_addr_i, rst_i)
BEGIN
IF ((rst_i(5)) = '1') THEN
force_bl1 <= '0';
ELSIF (addr_out + std_logic_vector(to_unsigned((DWIDTH/8)*to_integer(unsigned(bl_out) ),32)) >= end_addr_i) OR
(buf_avail_r <= 50 and PORT_MODE = "RD_MODE") THEN
force_bl1 <= '1' ;
ELSE
force_bl1 <= '0' ;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(6)) = '1') THEN
bl_out_reg <= fixed_bl_i;
ELSIF (bl_out_vld = '1') THEN
bl_out_reg <= bl_out;
END IF;
END IF;
END PROCESS;
xhdl12 <= bl_mode_reg;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (mode_load_pulse = '1') THEN
bl_out <= fixed_bl_i;
ELSIF (cmd_clk_en = '1') THEN
CASE xhdl12 IS
WHEN "00" =>
bl_out <= bram_bl_i;
WHEN "01" =>
bl_out <= fixed_bl_i;
WHEN "10" =>
bl_out <= prbs_brlen;
WHEN OTHERS =>
bl_out <= "000001";
END CASE;
END IF;
END IF;
END PROCESS;
--synthesis translate_off
PROCESS (bl_out)
BEGIN
IF (bl_out > "000010" AND FAMILY = "VIRTEX6") THEN
report "Error ! Not valid burst length"; --severity ERROR;
END IF;
END PROCESS;
--synthesis translate_on
xhdl13 : IF (CMD_PATTERN = "CGEN_PRBS" OR CMD_PATTERN = "CGEN_ALL") GENERATE
bl_prbs_gen : cmd_prbs_gen
GENERIC MAP (
TCQ => TCQ,
family => FAMILY,
prbs_cmd => "BLEN",
addr_width => 32,
seed_width => 15,
prbs_width => 20
)
PORT MAP (
clk_i => clk_i,
clk_en => cmd_clk_en,
prbs_seed_init => load_seed_i,
prbs_seed_i => cmd_seed_i(16 DOWNTO 2),
prbs_o => prbs_bl
);
END GENERATE;
-- xhdl14 <= "000001" WHEN (prbs_bl(5 DOWNTO 0) = "000000") ELSE prbs_bl(5 DOWNTO 0);
PROCESS (prbs_bl) BEGIN
IF (FAMILY = "SPARTAN6") THEN
if (prbs_bl(5 DOWNTO 0) = "000000") then
-- prbs_brlen <= xhdl14;
prbs_brlen <= "000001";
else
prbs_brlen <= prbs_bl(5 DOWNTO 0);
end if;
ELSE
prbs_brlen <= "000010";
END IF;
END PROCESS;
END trans;
|
cc0-1.0
|
qu1x/fsio
|
src/lib/fsio_get.vhd
|
1
|
1393
|
-- This file is part of fsio, see <https://qu1x.org/fsio>.
--
-- Copyright (c) 2016 Rouven Spreckels <[email protected]>
--
-- fsio is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Affero General Public License version 3
-- as published by the Free Software Foundation on 19 November 2007.
--
-- fsio is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Affero General Public License for more details.
--
-- You should have received a copy of the GNU Affero General Public License
-- along with fsio. If not, see <https://www.gnu.org/licenses>.
library ieee;
use ieee.std_logic_1164.all;
library fsio;
use fsio.fsio.all;
entity fsio_get is
generic (
cap: integer := CAP;
len: integer := LEN
);
port (
clk: in std_logic;
hsi: in std_logic;
hso: out std_logic;
fsi: in std_logic_vector(cap - 1 downto 0);
fso: out std_logic_vector(cap - 1 downto 0);
dat: out std_logic_vector(len - 1 downto 0);
req: out std_logic;
ack: in std_logic
);
end fsio_get;
architecture behavioral of fsio_get is
begin
dat <= fso(len - 1 downto 0);
req <= hso xor hsi;
fso <= fsi;
ctl: process(clk)
begin
if rising_edge(clk) then
hso <= hso xor (req and ack);
end if;
end process ctl;
end behavioral;
|
agpl-3.0
|
chastell/art-decomp
|
kiss/s8_hot.vhd
|
1
|
2626
|
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity s8_hot is
port(
clock: in std_logic;
input: in std_logic_vector(3 downto 0);
output: out std_logic_vector(0 downto 0)
);
end s8_hot;
architecture behaviour of s8_hot is
constant s1: std_logic_vector(4 downto 0) := "10000";
constant s2: std_logic_vector(4 downto 0) := "01000";
constant s3: std_logic_vector(4 downto 0) := "00100";
constant s5: std_logic_vector(4 downto 0) := "00010";
constant s4: std_logic_vector(4 downto 0) := "00001";
signal current_state, next_state: std_logic_vector(4 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "-----"; output <= "-";
case current_state is
when s1 =>
if std_match(input, "1000") then next_state <= s1; output <= "1";
elsif std_match(input, "0100") then next_state <= s1; output <= "1";
elsif std_match(input, "0010") then next_state <= s2; output <= "1";
elsif std_match(input, "0001") then next_state <= s2; output <= "1";
end if;
when s2 =>
if std_match(input, "1000") then next_state <= s2; output <= "1";
elsif std_match(input, "0100") then next_state <= s3; output <= "1";
elsif std_match(input, "0010") then next_state <= s2; output <= "1";
elsif std_match(input, "0001") then next_state <= s1; output <= "1";
end if;
when s3 =>
if std_match(input, "1000") then next_state <= s3; output <= "1";
elsif std_match(input, "0100") then next_state <= s5; output <= "1";
elsif std_match(input, "0010") then next_state <= s3; output <= "1";
elsif std_match(input, "0001") then next_state <= s5; output <= "1";
end if;
when s4 =>
if std_match(input, "1000") then next_state <= s4; output <= "1";
elsif std_match(input, "0100") then next_state <= s2; output <= "1";
elsif std_match(input, "0010") then next_state <= s3; output <= "1";
elsif std_match(input, "0001") then next_state <= s3; output <= "1";
end if;
when s5 =>
if std_match(input, "1000") then next_state <= s5; output <= "1";
elsif std_match(input, "0100") then next_state <= s5; output <= "1";
elsif std_match(input, "0010") then next_state <= s1; output <= "1";
elsif std_match(input, "0001") then next_state <= s4; output <= "1";
end if;
when others => next_state <= "-----"; output <= "-";
end case;
end process;
end behaviour;
|
agpl-3.0
|
chastell/art-decomp
|
kiss/tbk_hot.vhd
|
1
|
133997
|
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity tbk_hot is
port(
clock: in std_logic;
input: in std_logic_vector(5 downto 0);
output: out std_logic_vector(2 downto 0)
);
end tbk_hot;
architecture behaviour of tbk_hot is
constant st0: std_logic_vector(31 downto 0) := "10000000000000000000000000000000";
constant st16: std_logic_vector(31 downto 0) := "01000000000000000000000000000000";
constant st1: std_logic_vector(31 downto 0) := "00100000000000000000000000000000";
constant st2: std_logic_vector(31 downto 0) := "00010000000000000000000000000000";
constant st3: std_logic_vector(31 downto 0) := "00001000000000000000000000000000";
constant st4: std_logic_vector(31 downto 0) := "00000100000000000000000000000000";
constant st5: std_logic_vector(31 downto 0) := "00000010000000000000000000000000";
constant st6: std_logic_vector(31 downto 0) := "00000001000000000000000000000000";
constant st7: std_logic_vector(31 downto 0) := "00000000100000000000000000000000";
constant st8: std_logic_vector(31 downto 0) := "00000000010000000000000000000000";
constant st9: std_logic_vector(31 downto 0) := "00000000001000000000000000000000";
constant st10: std_logic_vector(31 downto 0) := "00000000000100000000000000000000";
constant st11: std_logic_vector(31 downto 0) := "00000000000010000000000000000000";
constant st12: std_logic_vector(31 downto 0) := "00000000000001000000000000000000";
constant st13: std_logic_vector(31 downto 0) := "00000000000000100000000000000000";
constant st15: std_logic_vector(31 downto 0) := "00000000000000010000000000000000";
constant st14: std_logic_vector(31 downto 0) := "00000000000000001000000000000000";
constant st29: std_logic_vector(31 downto 0) := "00000000000000000100000000000000";
constant st31: std_logic_vector(31 downto 0) := "00000000000000000010000000000000";
constant st30: std_logic_vector(31 downto 0) := "00000000000000000001000000000000";
constant st17: std_logic_vector(31 downto 0) := "00000000000000000000100000000000";
constant st18: std_logic_vector(31 downto 0) := "00000000000000000000010000000000";
constant st19: std_logic_vector(31 downto 0) := "00000000000000000000001000000000";
constant st20: std_logic_vector(31 downto 0) := "00000000000000000000000100000000";
constant st21: std_logic_vector(31 downto 0) := "00000000000000000000000010000000";
constant st22: std_logic_vector(31 downto 0) := "00000000000000000000000001000000";
constant st23: std_logic_vector(31 downto 0) := "00000000000000000000000000100000";
constant st24: std_logic_vector(31 downto 0) := "00000000000000000000000000010000";
constant st25: std_logic_vector(31 downto 0) := "00000000000000000000000000001000";
constant st26: std_logic_vector(31 downto 0) := "00000000000000000000000000000100";
constant st27: std_logic_vector(31 downto 0) := "00000000000000000000000000000010";
constant st28: std_logic_vector(31 downto 0) := "00000000000000000000000000000001";
signal current_state, next_state: std_logic_vector(31 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "--------------------------------"; output <= "---";
case current_state is
when st0 =>
if std_match(input, "000000") then next_state <= st0; output <= "000";
elsif std_match(input, "000001") then next_state <= st0; output <= "000";
elsif std_match(input, "000010") then next_state <= st0; output <= "000";
elsif std_match(input, "000011") then next_state <= st0; output <= "000";
elsif std_match(input, "100011") then next_state <= st16; output <= "000";
elsif std_match(input, "11--00") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st0; output <= "000";
elsif std_match(input, "1--100") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st0; output <= "000";
elsif std_match(input, "--1100") then next_state <= st0; output <= "000";
elsif std_match(input, "11--01") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st0; output <= "000";
elsif std_match(input, "1--101") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st0; output <= "000";
elsif std_match(input, "--1101") then next_state <= st0; output <= "000";
elsif std_match(input, "11--10") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st0; output <= "000";
elsif std_match(input, "1--110") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st0; output <= "000";
elsif std_match(input, "--1110") then next_state <= st0; output <= "000";
elsif std_match(input, "000100") then next_state <= st1; output <= "000";
elsif std_match(input, "001000") then next_state <= st2; output <= "000";
elsif std_match(input, "010000") then next_state <= st3; output <= "000";
elsif std_match(input, "100000") then next_state <= st4; output <= "000";
elsif std_match(input, "000101") then next_state <= st5; output <= "000";
elsif std_match(input, "001001") then next_state <= st6; output <= "000";
elsif std_match(input, "010001") then next_state <= st7; output <= "000";
elsif std_match(input, "100001") then next_state <= st8; output <= "000";
elsif std_match(input, "000110") then next_state <= st9; output <= "000";
elsif std_match(input, "001010") then next_state <= st10; output <= "000";
elsif std_match(input, "010010") then next_state <= st11; output <= "000";
elsif std_match(input, "100010") then next_state <= st12; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st15; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st14; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st31; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st30; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st16 =>
if std_match(input, "000000") then next_state <= st16; output <= "000";
elsif std_match(input, "000001") then next_state <= st16; output <= "000";
elsif std_match(input, "000010") then next_state <= st16; output <= "000";
elsif std_match(input, "000011") then next_state <= st0; output <= "000";
elsif std_match(input, "100011") then next_state <= st16; output <= "000";
elsif std_match(input, "11--00") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st16; output <= "000";
elsif std_match(input, "1--100") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st16; output <= "000";
elsif std_match(input, "--1100") then next_state <= st16; output <= "000";
elsif std_match(input, "11--01") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st16; output <= "000";
elsif std_match(input, "1--101") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st16; output <= "000";
elsif std_match(input, "--1101") then next_state <= st16; output <= "000";
elsif std_match(input, "11--10") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st16; output <= "000";
elsif std_match(input, "1--110") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st16; output <= "000";
elsif std_match(input, "--1110") then next_state <= st16; output <= "000";
elsif std_match(input, "000100") then next_state <= st17; output <= "000";
elsif std_match(input, "001000") then next_state <= st18; output <= "000";
elsif std_match(input, "010000") then next_state <= st19; output <= "000";
elsif std_match(input, "100000") then next_state <= st20; output <= "000";
elsif std_match(input, "000101") then next_state <= st21; output <= "000";
elsif std_match(input, "001001") then next_state <= st22; output <= "000";
elsif std_match(input, "010001") then next_state <= st23; output <= "000";
elsif std_match(input, "100001") then next_state <= st24; output <= "000";
elsif std_match(input, "000110") then next_state <= st25; output <= "000";
elsif std_match(input, "001010") then next_state <= st26; output <= "000";
elsif std_match(input, "010010") then next_state <= st27; output <= "000";
elsif std_match(input, "100010") then next_state <= st28; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st15; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st14; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st31; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st30; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st1 =>
if std_match(input, "000000") then next_state <= st0; output <= "000";
elsif std_match(input, "000001") then next_state <= st1; output <= "000";
elsif std_match(input, "000010") then next_state <= st1; output <= "000";
elsif std_match(input, "000011") then next_state <= st1; output <= "000";
elsif std_match(input, "100011") then next_state <= st17; output <= "000";
elsif std_match(input, "11--00") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st0; output <= "000";
elsif std_match(input, "1--100") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st0; output <= "000";
elsif std_match(input, "--1100") then next_state <= st0; output <= "000";
elsif std_match(input, "11--01") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st0; output <= "000";
elsif std_match(input, "1--101") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st0; output <= "000";
elsif std_match(input, "--1101") then next_state <= st0; output <= "000";
elsif std_match(input, "11--10") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st0; output <= "000";
elsif std_match(input, "1--110") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st0; output <= "000";
elsif std_match(input, "--1110") then next_state <= st0; output <= "000";
elsif std_match(input, "000100") then next_state <= st1; output <= "010";
elsif std_match(input, "001000") then next_state <= st0; output <= "000";
elsif std_match(input, "010000") then next_state <= st0; output <= "000";
elsif std_match(input, "100000") then next_state <= st0; output <= "000";
elsif std_match(input, "000101") then next_state <= st0; output <= "000";
elsif std_match(input, "001001") then next_state <= st0; output <= "000";
elsif std_match(input, "010001") then next_state <= st0; output <= "000";
elsif std_match(input, "100001") then next_state <= st0; output <= "000";
elsif std_match(input, "000110") then next_state <= st0; output <= "000";
elsif std_match(input, "001010") then next_state <= st0; output <= "000";
elsif std_match(input, "010010") then next_state <= st0; output <= "000";
elsif std_match(input, "100010") then next_state <= st0; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st17 =>
if std_match(input, "000000") then next_state <= st16; output <= "000";
elsif std_match(input, "000001") then next_state <= st17; output <= "000";
elsif std_match(input, "000010") then next_state <= st17; output <= "000";
elsif std_match(input, "000011") then next_state <= st1; output <= "000";
elsif std_match(input, "100011") then next_state <= st17; output <= "000";
elsif std_match(input, "11--00") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st16; output <= "000";
elsif std_match(input, "1--100") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st16; output <= "000";
elsif std_match(input, "--1100") then next_state <= st16; output <= "000";
elsif std_match(input, "11--01") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st16; output <= "000";
elsif std_match(input, "1--101") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st16; output <= "000";
elsif std_match(input, "--1101") then next_state <= st16; output <= "000";
elsif std_match(input, "11--10") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st16; output <= "000";
elsif std_match(input, "1--110") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st16; output <= "000";
elsif std_match(input, "--1110") then next_state <= st16; output <= "000";
elsif std_match(input, "000100") then next_state <= st17; output <= "010";
elsif std_match(input, "001000") then next_state <= st16; output <= "000";
elsif std_match(input, "010000") then next_state <= st16; output <= "000";
elsif std_match(input, "100000") then next_state <= st16; output <= "000";
elsif std_match(input, "000101") then next_state <= st16; output <= "000";
elsif std_match(input, "001001") then next_state <= st16; output <= "000";
elsif std_match(input, "010001") then next_state <= st16; output <= "000";
elsif std_match(input, "100001") then next_state <= st16; output <= "000";
elsif std_match(input, "000110") then next_state <= st16; output <= "000";
elsif std_match(input, "001010") then next_state <= st16; output <= "000";
elsif std_match(input, "010010") then next_state <= st16; output <= "000";
elsif std_match(input, "100010") then next_state <= st16; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st2 =>
if std_match(input, "000000") then next_state <= st0; output <= "000";
elsif std_match(input, "000001") then next_state <= st2; output <= "000";
elsif std_match(input, "000010") then next_state <= st2; output <= "000";
elsif std_match(input, "000011") then next_state <= st2; output <= "000";
elsif std_match(input, "100011") then next_state <= st18; output <= "000";
elsif std_match(input, "11--00") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st0; output <= "000";
elsif std_match(input, "1--100") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st0; output <= "000";
elsif std_match(input, "--1100") then next_state <= st0; output <= "000";
elsif std_match(input, "11--01") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st0; output <= "000";
elsif std_match(input, "1--101") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st0; output <= "000";
elsif std_match(input, "--1101") then next_state <= st0; output <= "000";
elsif std_match(input, "11--10") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st0; output <= "000";
elsif std_match(input, "1--110") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st0; output <= "000";
elsif std_match(input, "--1110") then next_state <= st0; output <= "000";
elsif std_match(input, "000100") then next_state <= st0; output <= "000";
elsif std_match(input, "001000") then next_state <= st2; output <= "010";
elsif std_match(input, "010000") then next_state <= st0; output <= "000";
elsif std_match(input, "100000") then next_state <= st0; output <= "000";
elsif std_match(input, "000101") then next_state <= st0; output <= "000";
elsif std_match(input, "001001") then next_state <= st0; output <= "000";
elsif std_match(input, "010001") then next_state <= st0; output <= "000";
elsif std_match(input, "100001") then next_state <= st0; output <= "000";
elsif std_match(input, "000110") then next_state <= st0; output <= "000";
elsif std_match(input, "001010") then next_state <= st0; output <= "000";
elsif std_match(input, "010010") then next_state <= st0; output <= "000";
elsif std_match(input, "100010") then next_state <= st0; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st18 =>
if std_match(input, "000000") then next_state <= st16; output <= "000";
elsif std_match(input, "000001") then next_state <= st18; output <= "000";
elsif std_match(input, "000010") then next_state <= st18; output <= "000";
elsif std_match(input, "000011") then next_state <= st2; output <= "000";
elsif std_match(input, "100011") then next_state <= st18; output <= "000";
elsif std_match(input, "11--00") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st16; output <= "000";
elsif std_match(input, "1--100") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st16; output <= "000";
elsif std_match(input, "--1100") then next_state <= st16; output <= "000";
elsif std_match(input, "11--01") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st16; output <= "000";
elsif std_match(input, "1--101") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st16; output <= "000";
elsif std_match(input, "--1101") then next_state <= st16; output <= "000";
elsif std_match(input, "11--10") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st16; output <= "000";
elsif std_match(input, "1--110") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st16; output <= "000";
elsif std_match(input, "--1110") then next_state <= st16; output <= "000";
elsif std_match(input, "000100") then next_state <= st16; output <= "000";
elsif std_match(input, "001000") then next_state <= st18; output <= "010";
elsif std_match(input, "010000") then next_state <= st16; output <= "000";
elsif std_match(input, "100000") then next_state <= st16; output <= "000";
elsif std_match(input, "000101") then next_state <= st16; output <= "000";
elsif std_match(input, "001001") then next_state <= st16; output <= "000";
elsif std_match(input, "010001") then next_state <= st16; output <= "000";
elsif std_match(input, "100001") then next_state <= st16; output <= "000";
elsif std_match(input, "000110") then next_state <= st16; output <= "000";
elsif std_match(input, "001010") then next_state <= st16; output <= "000";
elsif std_match(input, "010010") then next_state <= st16; output <= "000";
elsif std_match(input, "100010") then next_state <= st16; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st3 =>
if std_match(input, "000000") then next_state <= st0; output <= "000";
elsif std_match(input, "000001") then next_state <= st3; output <= "000";
elsif std_match(input, "000010") then next_state <= st3; output <= "000";
elsif std_match(input, "000011") then next_state <= st3; output <= "000";
elsif std_match(input, "100011") then next_state <= st19; output <= "000";
elsif std_match(input, "11--00") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st0; output <= "000";
elsif std_match(input, "1--100") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st0; output <= "000";
elsif std_match(input, "--1100") then next_state <= st0; output <= "000";
elsif std_match(input, "11--01") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st0; output <= "000";
elsif std_match(input, "1--101") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st0; output <= "000";
elsif std_match(input, "--1101") then next_state <= st0; output <= "000";
elsif std_match(input, "11--10") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st0; output <= "000";
elsif std_match(input, "1--110") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st0; output <= "000";
elsif std_match(input, "--1110") then next_state <= st0; output <= "000";
elsif std_match(input, "000100") then next_state <= st0; output <= "000";
elsif std_match(input, "001000") then next_state <= st0; output <= "000";
elsif std_match(input, "010000") then next_state <= st3; output <= "010";
elsif std_match(input, "100000") then next_state <= st0; output <= "000";
elsif std_match(input, "000101") then next_state <= st0; output <= "000";
elsif std_match(input, "001001") then next_state <= st0; output <= "000";
elsif std_match(input, "010001") then next_state <= st0; output <= "000";
elsif std_match(input, "100001") then next_state <= st0; output <= "000";
elsif std_match(input, "000110") then next_state <= st0; output <= "000";
elsif std_match(input, "001010") then next_state <= st0; output <= "000";
elsif std_match(input, "010010") then next_state <= st0; output <= "000";
elsif std_match(input, "100010") then next_state <= st0; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st19 =>
if std_match(input, "000000") then next_state <= st16; output <= "000";
elsif std_match(input, "000001") then next_state <= st19; output <= "000";
elsif std_match(input, "000010") then next_state <= st19; output <= "000";
elsif std_match(input, "000011") then next_state <= st3; output <= "000";
elsif std_match(input, "100011") then next_state <= st19; output <= "000";
elsif std_match(input, "11--00") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st16; output <= "000";
elsif std_match(input, "1--100") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st16; output <= "000";
elsif std_match(input, "--1100") then next_state <= st16; output <= "000";
elsif std_match(input, "11--01") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st16; output <= "000";
elsif std_match(input, "1--101") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st16; output <= "000";
elsif std_match(input, "--1101") then next_state <= st16; output <= "000";
elsif std_match(input, "11--10") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st16; output <= "000";
elsif std_match(input, "1--110") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st16; output <= "000";
elsif std_match(input, "--1110") then next_state <= st16; output <= "000";
elsif std_match(input, "000100") then next_state <= st16; output <= "000";
elsif std_match(input, "001000") then next_state <= st16; output <= "000";
elsif std_match(input, "010000") then next_state <= st19; output <= "010";
elsif std_match(input, "100000") then next_state <= st16; output <= "000";
elsif std_match(input, "000101") then next_state <= st16; output <= "000";
elsif std_match(input, "001001") then next_state <= st16; output <= "000";
elsif std_match(input, "010001") then next_state <= st16; output <= "000";
elsif std_match(input, "100001") then next_state <= st16; output <= "000";
elsif std_match(input, "000110") then next_state <= st16; output <= "000";
elsif std_match(input, "001010") then next_state <= st16; output <= "000";
elsif std_match(input, "010010") then next_state <= st16; output <= "000";
elsif std_match(input, "100010") then next_state <= st16; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st4 =>
if std_match(input, "000000") then next_state <= st0; output <= "000";
elsif std_match(input, "000001") then next_state <= st4; output <= "000";
elsif std_match(input, "000010") then next_state <= st4; output <= "000";
elsif std_match(input, "000011") then next_state <= st4; output <= "000";
elsif std_match(input, "100011") then next_state <= st20; output <= "000";
elsif std_match(input, "11--00") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st0; output <= "000";
elsif std_match(input, "1--100") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st0; output <= "000";
elsif std_match(input, "--1100") then next_state <= st0; output <= "000";
elsif std_match(input, "11--01") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st0; output <= "000";
elsif std_match(input, "1--101") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st0; output <= "000";
elsif std_match(input, "--1101") then next_state <= st0; output <= "000";
elsif std_match(input, "11--10") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st0; output <= "000";
elsif std_match(input, "1--110") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st0; output <= "000";
elsif std_match(input, "--1110") then next_state <= st0; output <= "000";
elsif std_match(input, "000100") then next_state <= st0; output <= "000";
elsif std_match(input, "001000") then next_state <= st0; output <= "000";
elsif std_match(input, "010000") then next_state <= st0; output <= "000";
elsif std_match(input, "100000") then next_state <= st4; output <= "010";
elsif std_match(input, "000101") then next_state <= st0; output <= "000";
elsif std_match(input, "001001") then next_state <= st0; output <= "000";
elsif std_match(input, "010001") then next_state <= st0; output <= "000";
elsif std_match(input, "100001") then next_state <= st0; output <= "000";
elsif std_match(input, "000110") then next_state <= st0; output <= "000";
elsif std_match(input, "001010") then next_state <= st0; output <= "000";
elsif std_match(input, "010010") then next_state <= st0; output <= "000";
elsif std_match(input, "100010") then next_state <= st0; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st20 =>
if std_match(input, "000000") then next_state <= st16; output <= "000";
elsif std_match(input, "000001") then next_state <= st20; output <= "000";
elsif std_match(input, "000010") then next_state <= st20; output <= "000";
elsif std_match(input, "000011") then next_state <= st4; output <= "000";
elsif std_match(input, "100011") then next_state <= st20; output <= "000";
elsif std_match(input, "11--00") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st16; output <= "000";
elsif std_match(input, "1--100") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st16; output <= "000";
elsif std_match(input, "--1100") then next_state <= st16; output <= "000";
elsif std_match(input, "11--01") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st16; output <= "000";
elsif std_match(input, "1--101") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st16; output <= "000";
elsif std_match(input, "--1101") then next_state <= st16; output <= "000";
elsif std_match(input, "11--10") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st16; output <= "000";
elsif std_match(input, "1--110") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st16; output <= "000";
elsif std_match(input, "--1110") then next_state <= st16; output <= "000";
elsif std_match(input, "000100") then next_state <= st16; output <= "000";
elsif std_match(input, "001000") then next_state <= st16; output <= "000";
elsif std_match(input, "010000") then next_state <= st16; output <= "000";
elsif std_match(input, "100000") then next_state <= st20; output <= "010";
elsif std_match(input, "000101") then next_state <= st16; output <= "000";
elsif std_match(input, "001001") then next_state <= st16; output <= "000";
elsif std_match(input, "010001") then next_state <= st16; output <= "000";
elsif std_match(input, "100001") then next_state <= st16; output <= "000";
elsif std_match(input, "000110") then next_state <= st16; output <= "000";
elsif std_match(input, "001010") then next_state <= st16; output <= "000";
elsif std_match(input, "010010") then next_state <= st16; output <= "000";
elsif std_match(input, "100010") then next_state <= st16; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st5 =>
if std_match(input, "000001") then next_state <= st0; output <= "000";
elsif std_match(input, "000000") then next_state <= st5; output <= "000";
elsif std_match(input, "000010") then next_state <= st5; output <= "000";
elsif std_match(input, "000011") then next_state <= st5; output <= "000";
elsif std_match(input, "100011") then next_state <= st21; output <= "000";
elsif std_match(input, "11--00") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st0; output <= "000";
elsif std_match(input, "1--100") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st0; output <= "000";
elsif std_match(input, "--1100") then next_state <= st0; output <= "000";
elsif std_match(input, "11--01") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st0; output <= "000";
elsif std_match(input, "1--101") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st0; output <= "000";
elsif std_match(input, "--1101") then next_state <= st0; output <= "000";
elsif std_match(input, "11--10") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st0; output <= "000";
elsif std_match(input, "1--110") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st0; output <= "000";
elsif std_match(input, "--1110") then next_state <= st0; output <= "000";
elsif std_match(input, "000100") then next_state <= st0; output <= "000";
elsif std_match(input, "001000") then next_state <= st0; output <= "000";
elsif std_match(input, "010000") then next_state <= st0; output <= "000";
elsif std_match(input, "100000") then next_state <= st0; output <= "000";
elsif std_match(input, "000101") then next_state <= st5; output <= "010";
elsif std_match(input, "001001") then next_state <= st0; output <= "000";
elsif std_match(input, "010001") then next_state <= st0; output <= "000";
elsif std_match(input, "100001") then next_state <= st0; output <= "000";
elsif std_match(input, "000110") then next_state <= st0; output <= "000";
elsif std_match(input, "001010") then next_state <= st0; output <= "000";
elsif std_match(input, "010010") then next_state <= st0; output <= "000";
elsif std_match(input, "100010") then next_state <= st0; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st21 =>
if std_match(input, "000001") then next_state <= st16; output <= "000";
elsif std_match(input, "000000") then next_state <= st21; output <= "000";
elsif std_match(input, "000010") then next_state <= st21; output <= "000";
elsif std_match(input, "000011") then next_state <= st5; output <= "000";
elsif std_match(input, "100011") then next_state <= st21; output <= "000";
elsif std_match(input, "11--00") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st16; output <= "000";
elsif std_match(input, "1--100") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st16; output <= "000";
elsif std_match(input, "--1100") then next_state <= st16; output <= "000";
elsif std_match(input, "11--01") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st16; output <= "000";
elsif std_match(input, "1--101") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st16; output <= "000";
elsif std_match(input, "--1101") then next_state <= st16; output <= "000";
elsif std_match(input, "11--10") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st16; output <= "000";
elsif std_match(input, "1--110") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st16; output <= "000";
elsif std_match(input, "--1110") then next_state <= st16; output <= "000";
elsif std_match(input, "000100") then next_state <= st16; output <= "000";
elsif std_match(input, "001000") then next_state <= st16; output <= "000";
elsif std_match(input, "010000") then next_state <= st16; output <= "000";
elsif std_match(input, "100000") then next_state <= st16; output <= "000";
elsif std_match(input, "000101") then next_state <= st21; output <= "010";
elsif std_match(input, "001001") then next_state <= st16; output <= "000";
elsif std_match(input, "010001") then next_state <= st16; output <= "000";
elsif std_match(input, "100001") then next_state <= st16; output <= "000";
elsif std_match(input, "000110") then next_state <= st16; output <= "000";
elsif std_match(input, "001010") then next_state <= st16; output <= "000";
elsif std_match(input, "010010") then next_state <= st16; output <= "000";
elsif std_match(input, "100010") then next_state <= st16; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st6 =>
if std_match(input, "000001") then next_state <= st0; output <= "000";
elsif std_match(input, "000000") then next_state <= st6; output <= "000";
elsif std_match(input, "000010") then next_state <= st6; output <= "000";
elsif std_match(input, "000011") then next_state <= st6; output <= "000";
elsif std_match(input, "100011") then next_state <= st22; output <= "000";
elsif std_match(input, "11--00") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st0; output <= "000";
elsif std_match(input, "1--100") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st0; output <= "000";
elsif std_match(input, "--1100") then next_state <= st0; output <= "000";
elsif std_match(input, "11--01") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st0; output <= "000";
elsif std_match(input, "1--101") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st0; output <= "000";
elsif std_match(input, "--1101") then next_state <= st0; output <= "000";
elsif std_match(input, "11--10") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st0; output <= "000";
elsif std_match(input, "1--110") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st0; output <= "000";
elsif std_match(input, "--1110") then next_state <= st0; output <= "000";
elsif std_match(input, "000100") then next_state <= st0; output <= "000";
elsif std_match(input, "001000") then next_state <= st0; output <= "000";
elsif std_match(input, "010000") then next_state <= st0; output <= "000";
elsif std_match(input, "100000") then next_state <= st0; output <= "000";
elsif std_match(input, "000101") then next_state <= st0; output <= "000";
elsif std_match(input, "001001") then next_state <= st6; output <= "010";
elsif std_match(input, "010001") then next_state <= st0; output <= "000";
elsif std_match(input, "100001") then next_state <= st0; output <= "000";
elsif std_match(input, "000110") then next_state <= st0; output <= "000";
elsif std_match(input, "001010") then next_state <= st0; output <= "000";
elsif std_match(input, "010010") then next_state <= st0; output <= "000";
elsif std_match(input, "100010") then next_state <= st0; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st22 =>
if std_match(input, "000001") then next_state <= st16; output <= "000";
elsif std_match(input, "000000") then next_state <= st22; output <= "000";
elsif std_match(input, "000010") then next_state <= st22; output <= "000";
elsif std_match(input, "000011") then next_state <= st6; output <= "000";
elsif std_match(input, "100011") then next_state <= st22; output <= "000";
elsif std_match(input, "11--00") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st16; output <= "000";
elsif std_match(input, "1--100") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st16; output <= "000";
elsif std_match(input, "--1100") then next_state <= st16; output <= "000";
elsif std_match(input, "11--01") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st16; output <= "000";
elsif std_match(input, "1--101") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st16; output <= "000";
elsif std_match(input, "--1101") then next_state <= st16; output <= "000";
elsif std_match(input, "11--10") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st16; output <= "000";
elsif std_match(input, "1--110") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st16; output <= "000";
elsif std_match(input, "--1110") then next_state <= st16; output <= "000";
elsif std_match(input, "000100") then next_state <= st16; output <= "000";
elsif std_match(input, "001000") then next_state <= st16; output <= "000";
elsif std_match(input, "010000") then next_state <= st16; output <= "000";
elsif std_match(input, "100000") then next_state <= st16; output <= "000";
elsif std_match(input, "000101") then next_state <= st16; output <= "000";
elsif std_match(input, "001001") then next_state <= st22; output <= "010";
elsif std_match(input, "010001") then next_state <= st16; output <= "000";
elsif std_match(input, "100001") then next_state <= st16; output <= "000";
elsif std_match(input, "000110") then next_state <= st16; output <= "000";
elsif std_match(input, "001010") then next_state <= st16; output <= "000";
elsif std_match(input, "010010") then next_state <= st16; output <= "000";
elsif std_match(input, "100010") then next_state <= st16; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st7 =>
if std_match(input, "000001") then next_state <= st0; output <= "000";
elsif std_match(input, "000000") then next_state <= st7; output <= "000";
elsif std_match(input, "000010") then next_state <= st7; output <= "000";
elsif std_match(input, "000011") then next_state <= st7; output <= "000";
elsif std_match(input, "100011") then next_state <= st23; output <= "000";
elsif std_match(input, "11--00") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st0; output <= "000";
elsif std_match(input, "1--100") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st0; output <= "000";
elsif std_match(input, "--1100") then next_state <= st0; output <= "000";
elsif std_match(input, "11--01") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st0; output <= "000";
elsif std_match(input, "1--101") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st0; output <= "000";
elsif std_match(input, "--1101") then next_state <= st0; output <= "000";
elsif std_match(input, "11--10") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st0; output <= "000";
elsif std_match(input, "1--110") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st0; output <= "000";
elsif std_match(input, "--1110") then next_state <= st0; output <= "000";
elsif std_match(input, "000100") then next_state <= st0; output <= "000";
elsif std_match(input, "001000") then next_state <= st0; output <= "000";
elsif std_match(input, "010000") then next_state <= st0; output <= "000";
elsif std_match(input, "100000") then next_state <= st0; output <= "000";
elsif std_match(input, "000101") then next_state <= st0; output <= "000";
elsif std_match(input, "001001") then next_state <= st0; output <= "000";
elsif std_match(input, "010001") then next_state <= st7; output <= "010";
elsif std_match(input, "100001") then next_state <= st0; output <= "000";
elsif std_match(input, "000110") then next_state <= st0; output <= "000";
elsif std_match(input, "001010") then next_state <= st0; output <= "000";
elsif std_match(input, "010010") then next_state <= st0; output <= "000";
elsif std_match(input, "100010") then next_state <= st0; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st23 =>
if std_match(input, "000001") then next_state <= st16; output <= "000";
elsif std_match(input, "000000") then next_state <= st23; output <= "000";
elsif std_match(input, "000010") then next_state <= st23; output <= "000";
elsif std_match(input, "000011") then next_state <= st7; output <= "000";
elsif std_match(input, "100011") then next_state <= st23; output <= "000";
elsif std_match(input, "11--00") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st16; output <= "000";
elsif std_match(input, "1--100") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st16; output <= "000";
elsif std_match(input, "--1100") then next_state <= st16; output <= "000";
elsif std_match(input, "11--01") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st16; output <= "000";
elsif std_match(input, "1--101") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st16; output <= "000";
elsif std_match(input, "--1101") then next_state <= st16; output <= "000";
elsif std_match(input, "11--10") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st16; output <= "000";
elsif std_match(input, "1--110") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st16; output <= "000";
elsif std_match(input, "--1110") then next_state <= st16; output <= "000";
elsif std_match(input, "000100") then next_state <= st16; output <= "000";
elsif std_match(input, "001000") then next_state <= st16; output <= "000";
elsif std_match(input, "010000") then next_state <= st16; output <= "000";
elsif std_match(input, "100000") then next_state <= st16; output <= "000";
elsif std_match(input, "000101") then next_state <= st16; output <= "000";
elsif std_match(input, "001001") then next_state <= st16; output <= "000";
elsif std_match(input, "010001") then next_state <= st23; output <= "010";
elsif std_match(input, "100001") then next_state <= st16; output <= "000";
elsif std_match(input, "000110") then next_state <= st16; output <= "000";
elsif std_match(input, "001010") then next_state <= st16; output <= "000";
elsif std_match(input, "010010") then next_state <= st16; output <= "000";
elsif std_match(input, "100010") then next_state <= st16; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st8 =>
if std_match(input, "000001") then next_state <= st0; output <= "000";
elsif std_match(input, "000000") then next_state <= st8; output <= "000";
elsif std_match(input, "000010") then next_state <= st8; output <= "000";
elsif std_match(input, "000011") then next_state <= st8; output <= "000";
elsif std_match(input, "100011") then next_state <= st24; output <= "000";
elsif std_match(input, "11--00") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st0; output <= "000";
elsif std_match(input, "1--100") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st0; output <= "000";
elsif std_match(input, "--1100") then next_state <= st0; output <= "000";
elsif std_match(input, "11--01") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st0; output <= "000";
elsif std_match(input, "1--101") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st0; output <= "000";
elsif std_match(input, "--1101") then next_state <= st0; output <= "000";
elsif std_match(input, "11--10") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st0; output <= "000";
elsif std_match(input, "1--110") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st0; output <= "000";
elsif std_match(input, "--1110") then next_state <= st0; output <= "000";
elsif std_match(input, "000100") then next_state <= st0; output <= "000";
elsif std_match(input, "001000") then next_state <= st0; output <= "000";
elsif std_match(input, "010000") then next_state <= st0; output <= "000";
elsif std_match(input, "100000") then next_state <= st0; output <= "000";
elsif std_match(input, "000101") then next_state <= st0; output <= "000";
elsif std_match(input, "001001") then next_state <= st0; output <= "000";
elsif std_match(input, "010001") then next_state <= st0; output <= "000";
elsif std_match(input, "100001") then next_state <= st8; output <= "010";
elsif std_match(input, "000110") then next_state <= st0; output <= "000";
elsif std_match(input, "001010") then next_state <= st0; output <= "000";
elsif std_match(input, "010010") then next_state <= st0; output <= "000";
elsif std_match(input, "100010") then next_state <= st0; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st24 =>
if std_match(input, "000001") then next_state <= st16; output <= "000";
elsif std_match(input, "000000") then next_state <= st24; output <= "000";
elsif std_match(input, "000010") then next_state <= st24; output <= "000";
elsif std_match(input, "000011") then next_state <= st8; output <= "000";
elsif std_match(input, "100011") then next_state <= st24; output <= "000";
elsif std_match(input, "11--00") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st16; output <= "000";
elsif std_match(input, "1--100") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st16; output <= "000";
elsif std_match(input, "--1100") then next_state <= st16; output <= "000";
elsif std_match(input, "11--01") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st16; output <= "000";
elsif std_match(input, "1--101") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st16; output <= "000";
elsif std_match(input, "--1101") then next_state <= st16; output <= "000";
elsif std_match(input, "11--10") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st16; output <= "000";
elsif std_match(input, "1--110") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st16; output <= "000";
elsif std_match(input, "--1110") then next_state <= st16; output <= "000";
elsif std_match(input, "000100") then next_state <= st16; output <= "000";
elsif std_match(input, "001000") then next_state <= st16; output <= "000";
elsif std_match(input, "010000") then next_state <= st16; output <= "000";
elsif std_match(input, "100000") then next_state <= st16; output <= "000";
elsif std_match(input, "000101") then next_state <= st16; output <= "000";
elsif std_match(input, "001001") then next_state <= st16; output <= "000";
elsif std_match(input, "010001") then next_state <= st16; output <= "000";
elsif std_match(input, "100001") then next_state <= st24; output <= "010";
elsif std_match(input, "000110") then next_state <= st16; output <= "000";
elsif std_match(input, "001010") then next_state <= st16; output <= "000";
elsif std_match(input, "010010") then next_state <= st16; output <= "000";
elsif std_match(input, "100010") then next_state <= st16; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st9 =>
if std_match(input, "000010") then next_state <= st0; output <= "000";
elsif std_match(input, "000001") then next_state <= st9; output <= "000";
elsif std_match(input, "000000") then next_state <= st9; output <= "000";
elsif std_match(input, "000011") then next_state <= st9; output <= "000";
elsif std_match(input, "100011") then next_state <= st25; output <= "000";
elsif std_match(input, "11--00") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st0; output <= "000";
elsif std_match(input, "1--100") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st0; output <= "000";
elsif std_match(input, "--1100") then next_state <= st0; output <= "000";
elsif std_match(input, "11--01") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st0; output <= "000";
elsif std_match(input, "1--101") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st0; output <= "000";
elsif std_match(input, "--1101") then next_state <= st0; output <= "000";
elsif std_match(input, "11--10") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st0; output <= "000";
elsif std_match(input, "1--110") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st0; output <= "000";
elsif std_match(input, "--1110") then next_state <= st0; output <= "000";
elsif std_match(input, "000100") then next_state <= st0; output <= "000";
elsif std_match(input, "001000") then next_state <= st0; output <= "000";
elsif std_match(input, "010000") then next_state <= st0; output <= "000";
elsif std_match(input, "100000") then next_state <= st0; output <= "000";
elsif std_match(input, "000101") then next_state <= st0; output <= "000";
elsif std_match(input, "001001") then next_state <= st0; output <= "000";
elsif std_match(input, "010001") then next_state <= st0; output <= "000";
elsif std_match(input, "100001") then next_state <= st0; output <= "000";
elsif std_match(input, "000110") then next_state <= st9; output <= "010";
elsif std_match(input, "001010") then next_state <= st0; output <= "000";
elsif std_match(input, "010010") then next_state <= st0; output <= "000";
elsif std_match(input, "100010") then next_state <= st0; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st25 =>
if std_match(input, "000010") then next_state <= st16; output <= "000";
elsif std_match(input, "000001") then next_state <= st25; output <= "000";
elsif std_match(input, "000000") then next_state <= st25; output <= "000";
elsif std_match(input, "000011") then next_state <= st9; output <= "000";
elsif std_match(input, "100011") then next_state <= st25; output <= "000";
elsif std_match(input, "11--00") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st16; output <= "000";
elsif std_match(input, "1--100") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st16; output <= "000";
elsif std_match(input, "--1100") then next_state <= st16; output <= "000";
elsif std_match(input, "11--01") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st16; output <= "000";
elsif std_match(input, "1--101") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st16; output <= "000";
elsif std_match(input, "--1101") then next_state <= st16; output <= "000";
elsif std_match(input, "11--10") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st16; output <= "000";
elsif std_match(input, "1--110") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st16; output <= "000";
elsif std_match(input, "--1110") then next_state <= st16; output <= "000";
elsif std_match(input, "000100") then next_state <= st16; output <= "000";
elsif std_match(input, "001000") then next_state <= st16; output <= "000";
elsif std_match(input, "010000") then next_state <= st16; output <= "000";
elsif std_match(input, "100000") then next_state <= st16; output <= "000";
elsif std_match(input, "000101") then next_state <= st16; output <= "000";
elsif std_match(input, "001001") then next_state <= st16; output <= "000";
elsif std_match(input, "010001") then next_state <= st16; output <= "000";
elsif std_match(input, "100001") then next_state <= st16; output <= "000";
elsif std_match(input, "000110") then next_state <= st25; output <= "010";
elsif std_match(input, "001010") then next_state <= st16; output <= "000";
elsif std_match(input, "010010") then next_state <= st16; output <= "000";
elsif std_match(input, "100010") then next_state <= st16; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st10 =>
if std_match(input, "000010") then next_state <= st0; output <= "000";
elsif std_match(input, "000001") then next_state <= st10; output <= "000";
elsif std_match(input, "000000") then next_state <= st10; output <= "000";
elsif std_match(input, "000011") then next_state <= st10; output <= "000";
elsif std_match(input, "100011") then next_state <= st26; output <= "000";
elsif std_match(input, "11--00") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st0; output <= "000";
elsif std_match(input, "1--100") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st0; output <= "000";
elsif std_match(input, "--1100") then next_state <= st0; output <= "000";
elsif std_match(input, "11--01") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st0; output <= "000";
elsif std_match(input, "1--101") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st0; output <= "000";
elsif std_match(input, "--1101") then next_state <= st0; output <= "000";
elsif std_match(input, "11--10") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st0; output <= "000";
elsif std_match(input, "1--110") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st0; output <= "000";
elsif std_match(input, "--1110") then next_state <= st0; output <= "000";
elsif std_match(input, "000100") then next_state <= st0; output <= "000";
elsif std_match(input, "001000") then next_state <= st0; output <= "000";
elsif std_match(input, "010000") then next_state <= st0; output <= "000";
elsif std_match(input, "100000") then next_state <= st0; output <= "000";
elsif std_match(input, "000101") then next_state <= st0; output <= "000";
elsif std_match(input, "001001") then next_state <= st0; output <= "000";
elsif std_match(input, "010001") then next_state <= st0; output <= "000";
elsif std_match(input, "100001") then next_state <= st0; output <= "000";
elsif std_match(input, "000110") then next_state <= st0; output <= "000";
elsif std_match(input, "001010") then next_state <= st10; output <= "010";
elsif std_match(input, "010010") then next_state <= st0; output <= "000";
elsif std_match(input, "100010") then next_state <= st0; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st26 =>
if std_match(input, "000010") then next_state <= st16; output <= "000";
elsif std_match(input, "000001") then next_state <= st26; output <= "000";
elsif std_match(input, "000000") then next_state <= st26; output <= "000";
elsif std_match(input, "000011") then next_state <= st10; output <= "000";
elsif std_match(input, "100011") then next_state <= st26; output <= "000";
elsif std_match(input, "11--00") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st16; output <= "000";
elsif std_match(input, "1--100") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st16; output <= "000";
elsif std_match(input, "--1100") then next_state <= st16; output <= "000";
elsif std_match(input, "11--01") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st16; output <= "000";
elsif std_match(input, "1--101") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st16; output <= "000";
elsif std_match(input, "--1101") then next_state <= st16; output <= "000";
elsif std_match(input, "11--10") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st16; output <= "000";
elsif std_match(input, "1--110") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st16; output <= "000";
elsif std_match(input, "--1110") then next_state <= st16; output <= "000";
elsif std_match(input, "000100") then next_state <= st16; output <= "000";
elsif std_match(input, "001000") then next_state <= st16; output <= "000";
elsif std_match(input, "010000") then next_state <= st16; output <= "000";
elsif std_match(input, "100000") then next_state <= st16; output <= "000";
elsif std_match(input, "000101") then next_state <= st16; output <= "000";
elsif std_match(input, "001001") then next_state <= st16; output <= "000";
elsif std_match(input, "010001") then next_state <= st16; output <= "000";
elsif std_match(input, "100001") then next_state <= st16; output <= "000";
elsif std_match(input, "000110") then next_state <= st16; output <= "000";
elsif std_match(input, "001010") then next_state <= st26; output <= "010";
elsif std_match(input, "010010") then next_state <= st16; output <= "000";
elsif std_match(input, "100010") then next_state <= st16; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st11 =>
if std_match(input, "000010") then next_state <= st0; output <= "000";
elsif std_match(input, "000001") then next_state <= st11; output <= "000";
elsif std_match(input, "000000") then next_state <= st11; output <= "000";
elsif std_match(input, "000011") then next_state <= st11; output <= "000";
elsif std_match(input, "100011") then next_state <= st27; output <= "000";
elsif std_match(input, "11--00") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st0; output <= "000";
elsif std_match(input, "1--100") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st0; output <= "000";
elsif std_match(input, "--1100") then next_state <= st0; output <= "000";
elsif std_match(input, "11--01") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st0; output <= "000";
elsif std_match(input, "1--101") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st0; output <= "000";
elsif std_match(input, "--1101") then next_state <= st0; output <= "000";
elsif std_match(input, "11--10") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st0; output <= "000";
elsif std_match(input, "1--110") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st0; output <= "000";
elsif std_match(input, "--1110") then next_state <= st0; output <= "000";
elsif std_match(input, "000100") then next_state <= st0; output <= "000";
elsif std_match(input, "001000") then next_state <= st0; output <= "000";
elsif std_match(input, "010000") then next_state <= st0; output <= "000";
elsif std_match(input, "100000") then next_state <= st0; output <= "000";
elsif std_match(input, "000101") then next_state <= st0; output <= "000";
elsif std_match(input, "001001") then next_state <= st0; output <= "000";
elsif std_match(input, "010001") then next_state <= st0; output <= "000";
elsif std_match(input, "100001") then next_state <= st0; output <= "000";
elsif std_match(input, "000110") then next_state <= st0; output <= "000";
elsif std_match(input, "001010") then next_state <= st0; output <= "000";
elsif std_match(input, "010010") then next_state <= st11; output <= "010";
elsif std_match(input, "100010") then next_state <= st0; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st27 =>
if std_match(input, "000010") then next_state <= st16; output <= "000";
elsif std_match(input, "000001") then next_state <= st27; output <= "000";
elsif std_match(input, "000000") then next_state <= st27; output <= "000";
elsif std_match(input, "000011") then next_state <= st11; output <= "000";
elsif std_match(input, "100011") then next_state <= st27; output <= "000";
elsif std_match(input, "11--00") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st16; output <= "000";
elsif std_match(input, "1--100") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st16; output <= "000";
elsif std_match(input, "--1100") then next_state <= st16; output <= "000";
elsif std_match(input, "11--01") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st16; output <= "000";
elsif std_match(input, "1--101") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st16; output <= "000";
elsif std_match(input, "--1101") then next_state <= st16; output <= "000";
elsif std_match(input, "11--10") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st16; output <= "000";
elsif std_match(input, "1--110") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st16; output <= "000";
elsif std_match(input, "--1110") then next_state <= st16; output <= "000";
elsif std_match(input, "000100") then next_state <= st16; output <= "000";
elsif std_match(input, "001000") then next_state <= st16; output <= "000";
elsif std_match(input, "010000") then next_state <= st16; output <= "000";
elsif std_match(input, "100000") then next_state <= st16; output <= "000";
elsif std_match(input, "000101") then next_state <= st16; output <= "000";
elsif std_match(input, "001001") then next_state <= st16; output <= "000";
elsif std_match(input, "010001") then next_state <= st16; output <= "000";
elsif std_match(input, "100001") then next_state <= st16; output <= "000";
elsif std_match(input, "000110") then next_state <= st16; output <= "000";
elsif std_match(input, "001010") then next_state <= st16; output <= "000";
elsif std_match(input, "010010") then next_state <= st27; output <= "010";
elsif std_match(input, "100010") then next_state <= st16; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st12 =>
if std_match(input, "000010") then next_state <= st0; output <= "000";
elsif std_match(input, "000001") then next_state <= st12; output <= "000";
elsif std_match(input, "000000") then next_state <= st12; output <= "000";
elsif std_match(input, "000011") then next_state <= st12; output <= "000";
elsif std_match(input, "100011") then next_state <= st28; output <= "000";
elsif std_match(input, "11--00") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st0; output <= "000";
elsif std_match(input, "1--100") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st0; output <= "000";
elsif std_match(input, "--1100") then next_state <= st0; output <= "000";
elsif std_match(input, "11--01") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st0; output <= "000";
elsif std_match(input, "1--101") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st0; output <= "000";
elsif std_match(input, "--1101") then next_state <= st0; output <= "000";
elsif std_match(input, "11--10") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st0; output <= "000";
elsif std_match(input, "1--110") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st0; output <= "000";
elsif std_match(input, "--1110") then next_state <= st0; output <= "000";
elsif std_match(input, "000100") then next_state <= st0; output <= "000";
elsif std_match(input, "001000") then next_state <= st0; output <= "000";
elsif std_match(input, "010000") then next_state <= st0; output <= "000";
elsif std_match(input, "100000") then next_state <= st0; output <= "000";
elsif std_match(input, "000101") then next_state <= st0; output <= "000";
elsif std_match(input, "001001") then next_state <= st0; output <= "000";
elsif std_match(input, "010001") then next_state <= st0; output <= "000";
elsif std_match(input, "100001") then next_state <= st0; output <= "000";
elsif std_match(input, "000110") then next_state <= st0; output <= "000";
elsif std_match(input, "001010") then next_state <= st0; output <= "000";
elsif std_match(input, "010010") then next_state <= st0; output <= "000";
elsif std_match(input, "100010") then next_state <= st12; output <= "010";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st28 =>
if std_match(input, "000010") then next_state <= st16; output <= "000";
elsif std_match(input, "000001") then next_state <= st28; output <= "000";
elsif std_match(input, "000000") then next_state <= st28; output <= "000";
elsif std_match(input, "000011") then next_state <= st12; output <= "000";
elsif std_match(input, "100011") then next_state <= st28; output <= "000";
elsif std_match(input, "11--00") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st16; output <= "000";
elsif std_match(input, "1--100") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st16; output <= "000";
elsif std_match(input, "--1100") then next_state <= st16; output <= "000";
elsif std_match(input, "11--01") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st16; output <= "000";
elsif std_match(input, "1--101") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st16; output <= "000";
elsif std_match(input, "--1101") then next_state <= st16; output <= "000";
elsif std_match(input, "11--10") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st16; output <= "000";
elsif std_match(input, "1--110") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st16; output <= "000";
elsif std_match(input, "--1110") then next_state <= st16; output <= "000";
elsif std_match(input, "000100") then next_state <= st16; output <= "000";
elsif std_match(input, "001000") then next_state <= st16; output <= "000";
elsif std_match(input, "010000") then next_state <= st16; output <= "000";
elsif std_match(input, "100000") then next_state <= st16; output <= "000";
elsif std_match(input, "000101") then next_state <= st16; output <= "000";
elsif std_match(input, "001001") then next_state <= st16; output <= "000";
elsif std_match(input, "010001") then next_state <= st16; output <= "000";
elsif std_match(input, "100001") then next_state <= st16; output <= "000";
elsif std_match(input, "000110") then next_state <= st16; output <= "000";
elsif std_match(input, "001010") then next_state <= st16; output <= "000";
elsif std_match(input, "010010") then next_state <= st16; output <= "000";
elsif std_match(input, "100010") then next_state <= st28; output <= "010";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st13 =>
if std_match(input, "000011") then next_state <= st0; output <= "000";
elsif std_match(input, "100011") then next_state <= st16; output <= "000";
elsif std_match(input, "000001") then next_state <= st13; output <= "100";
elsif std_match(input, "000010") then next_state <= st13; output <= "100";
elsif std_match(input, "000000") then next_state <= st13; output <= "100";
elsif std_match(input, "11--00") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st0; output <= "000";
elsif std_match(input, "1--100") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st0; output <= "000";
elsif std_match(input, "--1100") then next_state <= st0; output <= "000";
elsif std_match(input, "11--01") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st0; output <= "000";
elsif std_match(input, "1--101") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st0; output <= "000";
elsif std_match(input, "--1101") then next_state <= st0; output <= "000";
elsif std_match(input, "11--10") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st0; output <= "000";
elsif std_match(input, "1--110") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st0; output <= "000";
elsif std_match(input, "--1110") then next_state <= st0; output <= "000";
elsif std_match(input, "000100") then next_state <= st0; output <= "000";
elsif std_match(input, "001000") then next_state <= st0; output <= "000";
elsif std_match(input, "010000") then next_state <= st0; output <= "000";
elsif std_match(input, "100000") then next_state <= st0; output <= "000";
elsif std_match(input, "000101") then next_state <= st0; output <= "000";
elsif std_match(input, "001001") then next_state <= st0; output <= "000";
elsif std_match(input, "010001") then next_state <= st0; output <= "000";
elsif std_match(input, "100001") then next_state <= st0; output <= "000";
elsif std_match(input, "000110") then next_state <= st0; output <= "000";
elsif std_match(input, "001010") then next_state <= st0; output <= "000";
elsif std_match(input, "010010") then next_state <= st0; output <= "000";
elsif std_match(input, "100010") then next_state <= st0; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st29 =>
if std_match(input, "000011") then next_state <= st0; output <= "000";
elsif std_match(input, "100011") then next_state <= st16; output <= "000";
elsif std_match(input, "000001") then next_state <= st29; output <= "100";
elsif std_match(input, "000010") then next_state <= st29; output <= "100";
elsif std_match(input, "000000") then next_state <= st29; output <= "100";
elsif std_match(input, "11--00") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st16; output <= "000";
elsif std_match(input, "1--100") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st16; output <= "000";
elsif std_match(input, "--1100") then next_state <= st16; output <= "000";
elsif std_match(input, "11--01") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st16; output <= "000";
elsif std_match(input, "1--101") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st16; output <= "000";
elsif std_match(input, "--1101") then next_state <= st16; output <= "000";
elsif std_match(input, "11--10") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st16; output <= "000";
elsif std_match(input, "1--110") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st16; output <= "000";
elsif std_match(input, "--1110") then next_state <= st16; output <= "000";
elsif std_match(input, "000100") then next_state <= st16; output <= "000";
elsif std_match(input, "001000") then next_state <= st16; output <= "000";
elsif std_match(input, "010000") then next_state <= st16; output <= "000";
elsif std_match(input, "100000") then next_state <= st16; output <= "000";
elsif std_match(input, "000101") then next_state <= st16; output <= "000";
elsif std_match(input, "001001") then next_state <= st16; output <= "000";
elsif std_match(input, "010001") then next_state <= st16; output <= "000";
elsif std_match(input, "100001") then next_state <= st16; output <= "000";
elsif std_match(input, "000110") then next_state <= st16; output <= "000";
elsif std_match(input, "001010") then next_state <= st16; output <= "000";
elsif std_match(input, "010010") then next_state <= st16; output <= "000";
elsif std_match(input, "100010") then next_state <= st16; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st15 =>
if std_match(input, "000011") then next_state <= st0; output <= "000";
elsif std_match(input, "100011") then next_state <= st16; output <= "000";
elsif std_match(input, "000001") then next_state <= st15; output <= "000";
elsif std_match(input, "000010") then next_state <= st15; output <= "000";
elsif std_match(input, "000000") then next_state <= st15; output <= "000";
elsif std_match(input, "11--00") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st0; output <= "000";
elsif std_match(input, "1--100") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st0; output <= "000";
elsif std_match(input, "--1100") then next_state <= st0; output <= "000";
elsif std_match(input, "11--01") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st0; output <= "000";
elsif std_match(input, "1--101") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st0; output <= "000";
elsif std_match(input, "--1101") then next_state <= st0; output <= "000";
elsif std_match(input, "11--10") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st0; output <= "000";
elsif std_match(input, "1--110") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st0; output <= "000";
elsif std_match(input, "--1110") then next_state <= st0; output <= "000";
elsif std_match(input, "000100") then next_state <= st0; output <= "000";
elsif std_match(input, "001000") then next_state <= st0; output <= "000";
elsif std_match(input, "010000") then next_state <= st0; output <= "000";
elsif std_match(input, "100000") then next_state <= st0; output <= "000";
elsif std_match(input, "000101") then next_state <= st0; output <= "000";
elsif std_match(input, "001001") then next_state <= st0; output <= "000";
elsif std_match(input, "010001") then next_state <= st0; output <= "000";
elsif std_match(input, "100001") then next_state <= st0; output <= "000";
elsif std_match(input, "000110") then next_state <= st0; output <= "000";
elsif std_match(input, "001010") then next_state <= st0; output <= "000";
elsif std_match(input, "010010") then next_state <= st0; output <= "000";
elsif std_match(input, "100010") then next_state <= st0; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st15; output <= "011";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st31; output <= "011";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st31 =>
if std_match(input, "000011") then next_state <= st0; output <= "000";
elsif std_match(input, "100011") then next_state <= st16; output <= "000";
elsif std_match(input, "000001") then next_state <= st31; output <= "000";
elsif std_match(input, "000010") then next_state <= st31; output <= "000";
elsif std_match(input, "000000") then next_state <= st31; output <= "000";
elsif std_match(input, "11--00") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st16; output <= "000";
elsif std_match(input, "1--100") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st16; output <= "000";
elsif std_match(input, "--1100") then next_state <= st16; output <= "000";
elsif std_match(input, "11--01") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st16; output <= "000";
elsif std_match(input, "1--101") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st16; output <= "000";
elsif std_match(input, "--1101") then next_state <= st16; output <= "000";
elsif std_match(input, "11--10") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st16; output <= "000";
elsif std_match(input, "1--110") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st16; output <= "000";
elsif std_match(input, "--1110") then next_state <= st16; output <= "000";
elsif std_match(input, "000100") then next_state <= st16; output <= "000";
elsif std_match(input, "001000") then next_state <= st16; output <= "000";
elsif std_match(input, "010000") then next_state <= st16; output <= "000";
elsif std_match(input, "100000") then next_state <= st16; output <= "000";
elsif std_match(input, "000101") then next_state <= st16; output <= "000";
elsif std_match(input, "001001") then next_state <= st16; output <= "000";
elsif std_match(input, "010001") then next_state <= st16; output <= "000";
elsif std_match(input, "100001") then next_state <= st16; output <= "000";
elsif std_match(input, "000110") then next_state <= st16; output <= "000";
elsif std_match(input, "001010") then next_state <= st16; output <= "000";
elsif std_match(input, "010010") then next_state <= st16; output <= "000";
elsif std_match(input, "100010") then next_state <= st16; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st15; output <= "011";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st0; output <= "000";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st31; output <= "011";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st16; output <= "000";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st14 =>
if std_match(input, "000011") then next_state <= st0; output <= "000";
elsif std_match(input, "100011") then next_state <= st16; output <= "000";
elsif std_match(input, "000001") then next_state <= st14; output <= "000";
elsif std_match(input, "000010") then next_state <= st14; output <= "000";
elsif std_match(input, "000000") then next_state <= st14; output <= "000";
elsif std_match(input, "11--00") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st0; output <= "000";
elsif std_match(input, "1--100") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st0; output <= "000";
elsif std_match(input, "--1100") then next_state <= st0; output <= "000";
elsif std_match(input, "11--01") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st0; output <= "000";
elsif std_match(input, "1--101") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st0; output <= "000";
elsif std_match(input, "--1101") then next_state <= st0; output <= "000";
elsif std_match(input, "11--10") then next_state <= st0; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st0; output <= "000";
elsif std_match(input, "1--110") then next_state <= st0; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st0; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st0; output <= "000";
elsif std_match(input, "--1110") then next_state <= st0; output <= "000";
elsif std_match(input, "000100") then next_state <= st0; output <= "000";
elsif std_match(input, "001000") then next_state <= st0; output <= "000";
elsif std_match(input, "010000") then next_state <= st0; output <= "000";
elsif std_match(input, "100000") then next_state <= st0; output <= "000";
elsif std_match(input, "000101") then next_state <= st0; output <= "000";
elsif std_match(input, "001001") then next_state <= st0; output <= "000";
elsif std_match(input, "010001") then next_state <= st0; output <= "000";
elsif std_match(input, "100001") then next_state <= st0; output <= "000";
elsif std_match(input, "000110") then next_state <= st0; output <= "000";
elsif std_match(input, "001010") then next_state <= st0; output <= "000";
elsif std_match(input, "010010") then next_state <= st0; output <= "000";
elsif std_match(input, "100010") then next_state <= st0; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st14; output <= "001";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st30; output <= "001";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when st30 =>
if std_match(input, "000011") then next_state <= st0; output <= "000";
elsif std_match(input, "100011") then next_state <= st16; output <= "000";
elsif std_match(input, "000001") then next_state <= st30; output <= "000";
elsif std_match(input, "000010") then next_state <= st30; output <= "000";
elsif std_match(input, "000000") then next_state <= st30; output <= "000";
elsif std_match(input, "11--00") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-00") then next_state <= st16; output <= "000";
elsif std_match(input, "1--100") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-00") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-100") then next_state <= st16; output <= "000";
elsif std_match(input, "--1100") then next_state <= st16; output <= "000";
elsif std_match(input, "11--01") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-01") then next_state <= st16; output <= "000";
elsif std_match(input, "1--101") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-01") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-101") then next_state <= st16; output <= "000";
elsif std_match(input, "--1101") then next_state <= st16; output <= "000";
elsif std_match(input, "11--10") then next_state <= st16; output <= "000";
elsif std_match(input, "1-1-10") then next_state <= st16; output <= "000";
elsif std_match(input, "1--110") then next_state <= st16; output <= "000";
elsif std_match(input, "-11-10") then next_state <= st16; output <= "000";
elsif std_match(input, "-1-110") then next_state <= st16; output <= "000";
elsif std_match(input, "--1110") then next_state <= st16; output <= "000";
elsif std_match(input, "000100") then next_state <= st16; output <= "000";
elsif std_match(input, "001000") then next_state <= st16; output <= "000";
elsif std_match(input, "010000") then next_state <= st16; output <= "000";
elsif std_match(input, "100000") then next_state <= st16; output <= "000";
elsif std_match(input, "000101") then next_state <= st16; output <= "000";
elsif std_match(input, "001001") then next_state <= st16; output <= "000";
elsif std_match(input, "010001") then next_state <= st16; output <= "000";
elsif std_match(input, "100001") then next_state <= st16; output <= "000";
elsif std_match(input, "000110") then next_state <= st16; output <= "000";
elsif std_match(input, "001010") then next_state <= st16; output <= "000";
elsif std_match(input, "010010") then next_state <= st16; output <= "000";
elsif std_match(input, "100010") then next_state <= st16; output <= "000";
elsif std_match(input, "000111") then next_state <= st13; output <= "100";
elsif std_match(input, "001011") then next_state <= st0; output <= "000";
elsif std_match(input, "001111") then next_state <= st13; output <= "100";
elsif std_match(input, "010011") then next_state <= st14; output <= "001";
elsif std_match(input, "010111") then next_state <= st13; output <= "100";
elsif std_match(input, "011011") then next_state <= st0; output <= "000";
elsif std_match(input, "011111") then next_state <= st13; output <= "100";
elsif std_match(input, "100111") then next_state <= st29; output <= "100";
elsif std_match(input, "101011") then next_state <= st16; output <= "000";
elsif std_match(input, "101111") then next_state <= st29; output <= "100";
elsif std_match(input, "110011") then next_state <= st30; output <= "001";
elsif std_match(input, "110111") then next_state <= st29; output <= "100";
elsif std_match(input, "111011") then next_state <= st16; output <= "000";
elsif std_match(input, "111111") then next_state <= st29; output <= "100";
end if;
when others => next_state <= "--------------------------------"; output <= "---";
end case;
end process;
end behaviour;
|
agpl-3.0
|
chastell/art-decomp
|
kiss/s1494_jed.vhd
|
1
|
31360
|
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity s1494_jed is
port(
clock: in std_logic;
input: in std_logic_vector(7 downto 0);
output: out std_logic_vector(18 downto 0)
);
end s1494_jed;
architecture behaviour of s1494_jed is
constant s000000: std_logic_vector(5 downto 0) := "000000";
constant s001110: std_logic_vector(5 downto 0) := "000001";
constant s011000: std_logic_vector(5 downto 0) := "111000";
constant s010000: std_logic_vector(5 downto 0) := "101001";
constant s010100: std_logic_vector(5 downto 0) := "100000";
constant s110011: std_logic_vector(5 downto 0) := "010000";
constant s010011: std_logic_vector(5 downto 0) := "101110";
constant s000100: std_logic_vector(5 downto 0) := "011000";
constant s010111: std_logic_vector(5 downto 0) := "100010";
constant s010110: std_logic_vector(5 downto 0) := "100011";
constant s100011: std_logic_vector(5 downto 0) := "100110";
constant s001100: std_logic_vector(5 downto 0) := "110010";
constant s011011: std_logic_vector(5 downto 0) := "101100";
constant s010001: std_logic_vector(5 downto 0) := "001110";
constant s100110: std_logic_vector(5 downto 0) := "000100";
constant s011101: std_logic_vector(5 downto 0) := "111010";
constant s101110: std_logic_vector(5 downto 0) := "001000";
constant s010101: std_logic_vector(5 downto 0) := "010110";
constant s111110: std_logic_vector(5 downto 0) := "000101";
constant s000011: std_logic_vector(5 downto 0) := "100100";
constant s111011: std_logic_vector(5 downto 0) := "100101";
constant s011010: std_logic_vector(5 downto 0) := "101000";
constant s111010: std_logic_vector(5 downto 0) := "100001";
constant s100111: std_logic_vector(5 downto 0) := "001011";
constant s110010: std_logic_vector(5 downto 0) := "001010";
constant s100000: std_logic_vector(5 downto 0) := "000011";
constant s011100: std_logic_vector(5 downto 0) := "101010";
constant s101010: std_logic_vector(5 downto 0) := "001100";
constant s100010: std_logic_vector(5 downto 0) := "000110";
constant s101000: std_logic_vector(5 downto 0) := "110011";
constant s011110: std_logic_vector(5 downto 0) := "110000";
constant s110000: std_logic_vector(5 downto 0) := "111001";
constant s010010: std_logic_vector(5 downto 0) := "001101";
constant s001010: std_logic_vector(5 downto 0) := "110001";
constant s100100: std_logic_vector(5 downto 0) := "001001";
constant s111000: std_logic_vector(5 downto 0) := "011001";
constant s001011: std_logic_vector(5 downto 0) := "110110";
constant s110100: std_logic_vector(5 downto 0) := "010100";
constant s001000: std_logic_vector(5 downto 0) := "010001";
constant s000010: std_logic_vector(5 downto 0) := "000010";
constant s000111: std_logic_vector(5 downto 0) := "101101";
constant s101011: std_logic_vector(5 downto 0) := "011010";
constant s001111: std_logic_vector(5 downto 0) := "011100";
constant s000110: std_logic_vector(5 downto 0) := "101011";
constant s110110: std_logic_vector(5 downto 0) := "110100";
constant s011111: std_logic_vector(5 downto 0) := "111100";
constant s111100: std_logic_vector(5 downto 0) := "010011";
constant s101100: std_logic_vector(5 downto 0) := "010010";
signal current_state, next_state: std_logic_vector(5 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "------"; output <= "-------------------";
case current_state is
when s000000 =>
if std_match(input, "0-01----") then next_state <= s000000; output <= "1000000001000000001";
elsif std_match(input, "0-00----") then next_state <= s000000; output <= "1000000000100000001";
elsif std_match(input, "0-10----") then next_state <= s000000; output <= "0000000000000000000";
elsif std_match(input, "0-11----") then next_state <= s000000; output <= "0001001100111110001";
elsif std_match(input, "1-01----") then next_state <= s000000; output <= "1000000001000000001";
elsif std_match(input, "1-00----") then next_state <= s000000; output <= "1000000000100000001";
elsif std_match(input, "1-11----") then next_state <= s001110; output <= "0001001100111110001";
elsif std_match(input, "1-10----") then next_state <= s000000; output <= "0000000000000000000";
end if;
when s001110 =>
if std_match(input, "1---0---") then next_state <= s011000; output <= "0000000000100100101";
elsif std_match(input, "11--1---") then next_state <= s010000; output <= "1000010010100000101";
elsif std_match(input, "10--1---") then next_state <= s011000; output <= "0000000000100100101";
elsif std_match(input, "00------") then next_state <= s000000; output <= "0000000000100100101";
elsif std_match(input, "01--1---") then next_state <= s000000; output <= "1000010010100000101";
elsif std_match(input, "01--0---") then next_state <= s000000; output <= "0000000000100100101";
end if;
when s011000 =>
if std_match(input, "0-00-000") then next_state <= s000000; output <= "1000000000110000110";
elsif std_match(input, "0-00-010") then next_state <= s000000; output <= "1000000000100000110";
elsif std_match(input, "0-00-110") then next_state <= s000000; output <= "1000000100100000110";
elsif std_match(input, "0-00-100") then next_state <= s000000; output <= "1000000100110000110";
elsif std_match(input, "0-01-100") then next_state <= s000000; output <= "1000001101010000110";
elsif std_match(input, "0-01-110") then next_state <= s000000; output <= "1000001101000000110";
elsif std_match(input, "0-01-010") then next_state <= s000000; output <= "1000001001000000110";
elsif std_match(input, "0-01-000") then next_state <= s000000; output <= "1000001001010000110";
elsif std_match(input, "0-0---01") then next_state <= s000000; output <= "0100000000111111100";
elsif std_match(input, "0-0---11") then next_state <= s000000; output <= "0100000000101111100";
elsif std_match(input, "0-10-000") then next_state <= s000000; output <= "0000001000010000000";
elsif std_match(input, "0-10-010") then next_state <= s000000; output <= "0000001000000000000";
elsif std_match(input, "0-11-0-0") then next_state <= s000000; output <= "0000001000110110110";
elsif std_match(input, "0-10-110") then next_state <= s000000; output <= "0000001100000000000";
elsif std_match(input, "0-10-100") then next_state <= s000000; output <= "0000001100010000000";
elsif std_match(input, "0-11-1-0") then next_state <= s000000; output <= "0000001100110110110";
elsif std_match(input, "0-1---01") then next_state <= s000000; output <= "0100000000111111100";
elsif std_match(input, "0-1---11") then next_state <= s000000; output <= "0100000000101111100";
elsif std_match(input, "1--1--01") then next_state <= s010100; output <= "0100000000111111100";
elsif std_match(input, "1--1--11") then next_state <= s010100; output <= "0100000000101111100";
elsif std_match(input, "1-11-0-0") then next_state <= s110011; output <= "0000001000110110110";
elsif std_match(input, "1-11-1-0") then next_state <= s110011; output <= "0000001100110110110";
elsif std_match(input, "1-01-110") then next_state <= s010100; output <= "1000001101000000110";
elsif std_match(input, "1-01-100") then next_state <= s010100; output <= "1000001101010000110";
elsif std_match(input, "1-01-010") then next_state <= s010100; output <= "1000001001000000110";
elsif std_match(input, "1-01-000") then next_state <= s010100; output <= "1000001001010000110";
elsif std_match(input, "1--0--11") then next_state <= s010100; output <= "0100000000101111100";
elsif std_match(input, "1--0--01") then next_state <= s010100; output <= "0100000000111111100";
elsif std_match(input, "1-10-100") then next_state <= s010100; output <= "0000001100010000000";
elsif std_match(input, "1-10-110") then next_state <= s010100; output <= "0000001100000000000";
elsif std_match(input, "1-10-000") then next_state <= s010100; output <= "0000001000010000000";
elsif std_match(input, "1-10-010") then next_state <= s010100; output <= "0000001000000000000";
elsif std_match(input, "1-00-110") then next_state <= s010100; output <= "1000000100100000110";
elsif std_match(input, "1-00-100") then next_state <= s010100; output <= "1000000100110000110";
elsif std_match(input, "1-00-000") then next_state <= s010100; output <= "1000000000110000110";
elsif std_match(input, "1-00-010") then next_state <= s010100; output <= "1000000000100000110";
end if;
when s010100 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
elsif std_match(input, "1-------") then next_state <= s010011; output <= "0000000000100100101";
end if;
when s010011 =>
if std_match(input, "0----0--") then next_state <= s000000; output <= "1000000000111100001";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "1000000100111100001";
elsif std_match(input, "1----1--") then next_state <= s000100; output <= "1000000100111100001";
elsif std_match(input, "1----0--") then next_state <= s000100; output <= "1000000000111100001";
end if;
when s000100 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
elsif std_match(input, "10---11-") then next_state <= s010111; output <= "0000000000100100101";
elsif std_match(input, "11--011-") then next_state <= s010111; output <= "0000000000100100101";
elsif std_match(input, "11--111-") then next_state <= s010110; output <= "0000000000100100101";
elsif std_match(input, "11---01-") then next_state <= s100011; output <= "0000000000100100101";
elsif std_match(input, "10---01-") then next_state <= s010111; output <= "0000000000100100101";
elsif std_match(input, "1-----0-") then next_state <= s010111; output <= "0000000000100100101";
end if;
when s010111 =>
if std_match(input, "0----1--") then next_state <= s000000; output <= "0000000100101011000";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "0000000000101011000";
elsif std_match(input, "1----0--") then next_state <= s001100; output <= "0000000000101011000";
elsif std_match(input, "1----1--") then next_state <= s001100; output <= "0000000100101011000";
end if;
when s001100 =>
if std_match(input, "1----1--") then next_state <= s011011; output <= "0000000000100100101";
elsif std_match(input, "1----0--") then next_state <= s010001; output <= "0000000000100100101";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
end if;
when s011011 =>
if std_match(input, "0----11-") then next_state <= s000000; output <= "0000000100101110100";
elsif std_match(input, "0----10-") then next_state <= s000000; output <= "0000000100111110100";
elsif std_match(input, "0----01-") then next_state <= s000000; output <= "0000000000101110100";
elsif std_match(input, "0----00-") then next_state <= s000000; output <= "0000000000111110100";
elsif std_match(input, "1----11-") then next_state <= s100110; output <= "0000000100101110100";
elsif std_match(input, "1----10-") then next_state <= s100110; output <= "0000000100111110100";
elsif std_match(input, "1----01-") then next_state <= s100110; output <= "0000000000101110100";
elsif std_match(input, "1----00-") then next_state <= s100110; output <= "0000000000111110100";
end if;
when s100110 =>
if std_match(input, "1-------") then next_state <= s011101; output <= "0000000000100100101";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
end if;
when s011101 =>
if std_match(input, "0----01-") then next_state <= s000000; output <= "0000000000110011010";
elsif std_match(input, "0----00-") then next_state <= s000000; output <= "0000000000100011010";
elsif std_match(input, "0----10-") then next_state <= s000000; output <= "0000000100100011010";
elsif std_match(input, "0----11-") then next_state <= s000000; output <= "0000000100110011010";
elsif std_match(input, "1----11-") then next_state <= s101110; output <= "0000000100110011010";
elsif std_match(input, "1----10-") then next_state <= s101110; output <= "0000000100100011010";
elsif std_match(input, "1----01-") then next_state <= s101110; output <= "0000000000110011010";
elsif std_match(input, "1----00-") then next_state <= s101110; output <= "0000000000100011010";
end if;
when s101110 =>
if std_match(input, "1-------") then next_state <= s010101; output <= "0000000000100100101";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
end if;
when s010101 =>
if std_match(input, "1----0--") then next_state <= s111110; output <= "1000000000110100110";
elsif std_match(input, "1----1--") then next_state <= s111110; output <= "1000000100110100110";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "1000000000110100110";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "1000000100110100110";
end if;
when s111110 =>
if std_match(input, "01----0-") then next_state <= s000000; output <= "0000000000100100101";
elsif std_match(input, "00--1-0-") then next_state <= s000000; output <= "0000100000100100101";
elsif std_match(input, "00--0-0-") then next_state <= s000000; output <= "0000000000100100101";
elsif std_match(input, "11----01") then next_state <= s000011; output <= "0000000000100100101";
elsif std_match(input, "11--0-00") then next_state <= s000011; output <= "0000000000100100101";
elsif std_match(input, "11--1-00") then next_state <= s111011; output <= "0000000000100100101";
elsif std_match(input, "10--0-0-") then next_state <= s000011; output <= "0000000000100100101";
elsif std_match(input, "10--1-00") then next_state <= s011010; output <= "0000100000100100101";
elsif std_match(input, "10--1-01") then next_state <= s111010; output <= "0000100000100100101";
elsif std_match(input, "0---1-1-") then next_state <= s000000; output <= "0000100000100100101";
elsif std_match(input, "0---0-1-") then next_state <= s000000; output <= "0000000000100100101";
elsif std_match(input, "1---0-1-") then next_state <= s000011; output <= "0000000000100100101";
elsif std_match(input, "1---1-10") then next_state <= s011010; output <= "0000100000100100101";
elsif std_match(input, "1---1-11") then next_state <= s111010; output <= "0000100000100100101";
end if;
when s000011 =>
if std_match(input, "0----0-1") then next_state <= s000000; output <= "0000000000111110001";
elsif std_match(input, "0----1-1") then next_state <= s000000; output <= "0000000100111110001";
elsif std_match(input, "0----0-0") then next_state <= s000000; output <= "1000000000111110001";
elsif std_match(input, "0----1-0") then next_state <= s000000; output <= "0000000100111110001";
elsif std_match(input, "1----0-1") then next_state <= s001110; output <= "0000000000111110001";
elsif std_match(input, "1----1-1") then next_state <= s001110; output <= "0000000100111110001";
elsif std_match(input, "1----0-0") then next_state <= s001110; output <= "1000000000111110001";
elsif std_match(input, "1----1-0") then next_state <= s001110; output <= "0000000100111110001";
end if;
when s111011 =>
if std_match(input, "1----0--") then next_state <= s100111; output <= "1000000000111110001";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "1000000000111110001";
elsif std_match(input, "1----1--") then next_state <= s010000; output <= "0000010110111110001";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0000010110111110001";
end if;
when s100111 =>
if std_match(input, "1-------") then next_state <= s111011; output <= "0000000000100100101";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
end if;
when s010000 =>
if std_match(input, "--------") then next_state <= s000000; output <= "0000000000101110100";
end if;
when s011010 =>
if std_match(input, "1----01-") then next_state <= s110010; output <= "0000000000100101001";
elsif std_match(input, "1----00-") then next_state <= s110010; output <= "0000000000110101001";
elsif std_match(input, "1----1--") then next_state <= s100000; output <= "0000000100111110001";
elsif std_match(input, "0----01-") then next_state <= s000000; output <= "0000000000100101001";
elsif std_match(input, "0----00-") then next_state <= s000000; output <= "0000000000110101001";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0000000100111110001";
end if;
when s110010 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
elsif std_match(input, "1----00-") then next_state <= s011100; output <= "0000000000100100101";
elsif std_match(input, "1----01-") then next_state <= s011010; output <= "0000000000100100101";
elsif std_match(input, "1----11-") then next_state <= s011100; output <= "0000000000100100101";
elsif std_match(input, "1----10-") then next_state <= s011010; output <= "0000000000100100101";
end if;
when s011100 =>
if std_match(input, "1----10-") then next_state <= s101010; output <= "0000000100101111100";
elsif std_match(input, "1----11-") then next_state <= s101010; output <= "0000000100111111100";
elsif std_match(input, "1----00-") then next_state <= s100010; output <= "0000000000101111100";
elsif std_match(input, "1----01-") then next_state <= s100010; output <= "0000000000111111100";
elsif std_match(input, "0----10-") then next_state <= s000000; output <= "0000000100101111100";
elsif std_match(input, "0----11-") then next_state <= s000000; output <= "0000000100111111100";
elsif std_match(input, "0----00-") then next_state <= s000000; output <= "0000000000101111100";
elsif std_match(input, "0----01-") then next_state <= s000000; output <= "0000000000111111100";
end if;
when s101010 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
elsif std_match(input, "1-------") then next_state <= s111010; output <= "0000000000100100101";
end if;
when s111010 =>
if std_match(input, "1-------") then next_state <= s100000; output <= "0000000000111110001";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000000000111110001";
end if;
when s100000 =>
if std_match(input, "11------") then next_state <= s101000; output <= "0100000000100100101";
elsif std_match(input, "01------") then next_state <= s000000; output <= "0100000000100100101";
elsif std_match(input, "00--0---") then next_state <= s000000; output <= "0000000000100100101";
elsif std_match(input, "00--1---") then next_state <= s000000; output <= "0000010000100100101";
elsif std_match(input, "10--0---") then next_state <= s011110; output <= "0000000000100100101";
elsif std_match(input, "10--1---") then next_state <= s110000; output <= "0000010000100100101";
end if;
when s101000 =>
if std_match(input, "1-------") then next_state <= s010010; output <= "1000000000111100001";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "1000000000111100001";
end if;
when s010010 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
elsif std_match(input, "1---1---") then next_state <= s001010; output <= "0000000000100100101";
elsif std_match(input, "1---0---") then next_state <= s011110; output <= "0000000000100100101";
end if;
when s001010 =>
if std_match(input, "1----1--") then next_state <= s100100; output <= "0000000100110110110";
elsif std_match(input, "1----0--") then next_state <= s111000; output <= "0000000000110101001";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0000000100110110110";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "0000000000110101001";
end if;
when s100100 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0010000000100100101";
elsif std_match(input, "1-------") then next_state <= s001011; output <= "0010000000100100101";
end if;
when s001011 =>
if std_match(input, "0----0--") then next_state <= s000000; output <= "0000000000101110110";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0000000100101110110";
elsif std_match(input, "1----0--") then next_state <= s110100; output <= "0000000000101110110";
elsif std_match(input, "1----1--") then next_state <= s110100; output <= "0000000100101110110";
end if;
when s110100 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0010000000100100101";
elsif std_match(input, "1-------") then next_state <= s011011; output <= "0010000000100100101";
end if;
when s111000 =>
if std_match(input, "1----0--") then next_state <= s001000; output <= "0000000000100100101";
elsif std_match(input, "1---11--") then next_state <= s001000; output <= "0000000000100100101";
elsif std_match(input, "1---01--") then next_state <= s001010; output <= "0000000000100100101";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
end if;
when s001000 =>
if std_match(input, "1----1--") then next_state <= s100100; output <= "0000000100110110110";
elsif std_match(input, "1----0--") then next_state <= s100100; output <= "0000000000110110110";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "0000000000110110110";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0000000100110110110";
end if;
when s011110 =>
if std_match(input, "0----1--") then next_state <= s000000; output <= "0000000100111110001";
elsif std_match(input, "0-11-0--") then next_state <= s000000; output <= "0000001000110110110";
elsif std_match(input, "0-10-00-") then next_state <= s000000; output <= "0000001000000000000";
elsif std_match(input, "0-10-01-") then next_state <= s000000; output <= "0000001000010000000";
elsif std_match(input, "0-00-00-") then next_state <= s000000; output <= "1000000000100000110";
elsif std_match(input, "0-00-01-") then next_state <= s000000; output <= "1000000000110000110";
elsif std_match(input, "0-01-01-") then next_state <= s000000; output <= "1000001001010000110";
elsif std_match(input, "0-01-00-") then next_state <= s000000; output <= "1000001001000000110";
elsif std_match(input, "1----1--") then next_state <= s100000; output <= "0000000100111110001";
elsif std_match(input, "1-00-00-") then next_state <= s000010; output <= "1000000000100000110";
elsif std_match(input, "1-00-01-") then next_state <= s000010; output <= "1000000000110000110";
elsif std_match(input, "1-01-01-") then next_state <= s000010; output <= "1000001001010000110";
elsif std_match(input, "1-01-00-") then next_state <= s000010; output <= "1000001001000000110";
elsif std_match(input, "1-11-0--") then next_state <= s110011; output <= "0000001000110110110";
elsif std_match(input, "1-10-00-") then next_state <= s000010; output <= "0000001000000000000";
elsif std_match(input, "1-10-01-") then next_state <= s000010; output <= "0000001000010000000";
end if;
when s000010 =>
if std_match(input, "1----0--") then next_state <= s011110; output <= "0010000000100100101";
elsif std_match(input, "1----1--") then next_state <= s011110; output <= "0000000000100100101";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "0010000000100100101";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0000000000100100101";
end if;
when s110011 =>
if std_match(input, "1-------") then next_state <= s000111; output <= "0000000000100100101";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
end if;
when s000111 =>
if std_match(input, "0----1--") then next_state <= s000000; output <= "0000000100101110110";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "0000000000101110110";
elsif std_match(input, "1----1--") then next_state <= s101011; output <= "0000000100101110110";
elsif std_match(input, "1----0--") then next_state <= s101011; output <= "0000000000101110110";
end if;
when s101011 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
elsif std_match(input, "1-------") then next_state <= s001111; output <= "0000000000100100101";
end if;
when s001111 =>
if std_match(input, "1----1--") then next_state <= s000100; output <= "0010000100111001110";
elsif std_match(input, "1----0--") then next_state <= s000100; output <= "0010000000111001110";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0010000100111001110";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "0010000000111001110";
end if;
when s110000 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "1000000000110100110";
elsif std_match(input, "1-------") then next_state <= s000110; output <= "1000000000110100110";
end if;
when s000110 =>
if std_match(input, "1---01--") then next_state <= s011000; output <= "0001000000100100101";
elsif std_match(input, "1---00--") then next_state <= s011000; output <= "0010000000100100101";
elsif std_match(input, "1---10--") then next_state <= s011110; output <= "0010000000100100101";
elsif std_match(input, "1---11--") then next_state <= s011110; output <= "0001000000100100101";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "0010000000100100101";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0001000000100100101";
end if;
when s100010 =>
if std_match(input, "1-------") then next_state <= s011010; output <= "0000000000100100101";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
end if;
when s010001 =>
if std_match(input, "1----0--") then next_state <= s110110; output <= "1000000000111110100";
elsif std_match(input, "1----1--") then next_state <= s110110; output <= "1000000100111110100";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "1000000100111110100";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "1000000000111110100";
end if;
when s110110 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
elsif std_match(input, "1-------") then next_state <= s011111; output <= "0000000000100100101";
end if;
when s011111 =>
if std_match(input, "0----11-") then next_state <= s000000; output <= "1000000100111011010";
elsif std_match(input, "0----10-") then next_state <= s000000; output <= "1000000100101011010";
elsif std_match(input, "0----00-") then next_state <= s000000; output <= "1000000000101011010";
elsif std_match(input, "0----01-") then next_state <= s000000; output <= "1000000000111011010";
elsif std_match(input, "1----10-") then next_state <= s101110; output <= "1000000100101011010";
elsif std_match(input, "1----11-") then next_state <= s101110; output <= "1000000100111011010";
elsif std_match(input, "1----00-") then next_state <= s101110; output <= "1000000000101011010";
elsif std_match(input, "1----01-") then next_state <= s101110; output <= "1000000000111011010";
end if;
when s010110 =>
if std_match(input, "1----1--") then next_state <= s111100; output <= "0001000100111110001";
elsif std_match(input, "1-00-0--") then next_state <= s101100; output <= "1000000000100000110";
elsif std_match(input, "1-01-0--") then next_state <= s101100; output <= "1000001001000000110";
elsif std_match(input, "1-10-0--") then next_state <= s101100; output <= "0000001000000000000";
elsif std_match(input, "1-11-0--") then next_state <= s110011; output <= "0000001000110110110";
elsif std_match(input, "0-00-0--") then next_state <= s000000; output <= "1000000000100000110";
elsif std_match(input, "0-01-0--") then next_state <= s000000; output <= "1000001001000000110";
elsif std_match(input, "0-0--1--") then next_state <= s000000; output <= "0001000100111110001";
elsif std_match(input, "0-1--1--") then next_state <= s000000; output <= "0001000100111110001";
elsif std_match(input, "0-10-0--") then next_state <= s000000; output <= "0000001000000000000";
elsif std_match(input, "0-11-0--") then next_state <= s000000; output <= "0000001000110110110";
end if;
when s111100 =>
if std_match(input, "1-------") then next_state <= s100011; output <= "0100000000100100101";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0100000000100100101";
end if;
when s100011 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000000000110110110";
elsif std_match(input, "1-------") then next_state <= s110011; output <= "0000000000110110110";
end if;
when s101100 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
elsif std_match(input, "1-------") then next_state <= s010110; output <= "0000000000100100101";
end if;
when others => next_state <= "------"; output <= "-------------------";
end case;
end process;
end behaviour;
|
agpl-3.0
|
chastell/art-decomp
|
kiss/sse_hot.vhd
|
1
|
7190
|
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity sse_hot is
port(
clock: in std_logic;
input: in std_logic_vector(6 downto 0);
output: out std_logic_vector(6 downto 0)
);
end sse_hot;
architecture behaviour of sse_hot is
constant st11: std_logic_vector(15 downto 0) := "1000000000000000";
constant st10: std_logic_vector(15 downto 0) := "0100000000000000";
constant st4: std_logic_vector(15 downto 0) := "0010000000000000";
constant st12: std_logic_vector(15 downto 0) := "0001000000000000";
constant st7: std_logic_vector(15 downto 0) := "0000100000000000";
constant st6: std_logic_vector(15 downto 0) := "0000010000000000";
constant st1: std_logic_vector(15 downto 0) := "0000001000000000";
constant st0: std_logic_vector(15 downto 0) := "0000000100000000";
constant st8: std_logic_vector(15 downto 0) := "0000000010000000";
constant st9: std_logic_vector(15 downto 0) := "0000000001000000";
constant st3: std_logic_vector(15 downto 0) := "0000000000100000";
constant st2: std_logic_vector(15 downto 0) := "0000000000010000";
constant st5: std_logic_vector(15 downto 0) := "0000000000001000";
constant st13: std_logic_vector(15 downto 0) := "0000000000000100";
constant st14: std_logic_vector(15 downto 0) := "0000000000000010";
constant st15: std_logic_vector(15 downto 0) := "0000000000000001";
signal current_state, next_state: std_logic_vector(15 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "----------------"; output <= "-------";
case current_state is
when st11 =>
if std_match(input, "0------") then next_state <= st11; output <= "0000000";
elsif std_match(input, "10----0") then next_state <= st10; output <= "00110-0";
elsif std_match(input, "10----1") then next_state <= st10; output <= "00010-0";
elsif std_match(input, "11----0") then next_state <= st4; output <= "0011010";
elsif std_match(input, "11----1") then next_state <= st4; output <= "0001010";
end if;
when st10 =>
if std_match(input, "100----") then next_state <= st10; output <= "00000-0";
elsif std_match(input, "101-1--") then next_state <= st12; output <= "10000-0";
elsif std_match(input, "101-0--") then next_state <= st7; output <= "10000-0";
elsif std_match(input, "0------") then next_state <= st4; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st4; output <= "0000010";
end if;
when st7 =>
if std_match(input, "10-----") then next_state <= st6; output <= "00000-0";
elsif std_match(input, "0------") then next_state <= st4; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st4; output <= "0000010";
end if;
when st6 =>
if std_match(input, "10--0--") then next_state <= st7; output <= "10000-0";
elsif std_match(input, "10--1--") then next_state <= st12; output <= "10000-0";
elsif std_match(input, "0------") then next_state <= st4; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st4; output <= "0000010";
end if;
when st12 =>
if std_match(input, "10-----") then next_state <= st1; output <= "00000-0";
elsif std_match(input, "0------") then next_state <= st4; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st4; output <= "0000010";
end if;
when st1 =>
if std_match(input, "10-1---") then next_state <= st12; output <= "10000-0";
elsif std_match(input, "10--1--") then next_state <= st12; output <= "10000-0";
elsif std_match(input, "10-00--") then next_state <= st0; output <= "0100010";
elsif std_match(input, "0------") then next_state <= st4; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st4; output <= "0000010";
end if;
when st0 =>
if std_match(input, "10---0-") then next_state <= st0; output <= "0100000";
elsif std_match(input, "10---1-") then next_state <= st8; output <= "01000-0";
elsif std_match(input, "0------") then next_state <= st4; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st4; output <= "0000010";
end if;
when st8 =>
if std_match(input, "10-----") then next_state <= st9; output <= "0000010";
elsif std_match(input, "0------") then next_state <= st4; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st4; output <= "0000010";
end if;
when st9 =>
if std_match(input, "10---0-") then next_state <= st9; output <= "0000000";
elsif std_match(input, "10---1-") then next_state <= st3; output <= "10000-0";
elsif std_match(input, "0------") then next_state <= st4; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st4; output <= "0000010";
end if;
when st3 =>
if std_match(input, "10-----") then next_state <= st2; output <= "00000-0";
elsif std_match(input, "0------") then next_state <= st4; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st4; output <= "0000010";
end if;
when st2 =>
if std_match(input, "1001---") then next_state <= st2; output <= "00000-0";
elsif std_match(input, "10-01--") then next_state <= st10; output <= "00010-0";
elsif std_match(input, "10-00--") then next_state <= st0; output <= "0100010";
elsif std_match(input, "1011---") then next_state <= st3; output <= "10000-0";
elsif std_match(input, "0------") then next_state <= st4; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st4; output <= "0000010";
end if;
when st4 =>
if std_match(input, "0----0-") then next_state <= st4; output <= "000--00";
elsif std_match(input, "11---0-") then next_state <= st4; output <= "0000000";
elsif std_match(input, "0----1-") then next_state <= st11; output <= "000---1";
elsif std_match(input, "10-----") then next_state <= st10; output <= "00000-0";
elsif std_match(input, "11---1-") then next_state <= st5; output <= "00001-0";
end if;
when st5 =>
if std_match(input, "11-----") then next_state <= st5; output <= "00001-0";
elsif std_match(input, "10-----") then next_state <= st10; output <= "00000-0";
elsif std_match(input, "0------") then next_state <= st4; output <= "000--10";
end if;
when st13 =>
if std_match(input, "0------") then next_state <= st4; output <= "000--10";
end if;
when st14 =>
if std_match(input, "0------") then next_state <= st4; output <= "000--10";
end if;
when st15 =>
if std_match(input, "0------") then next_state <= st4; output <= "000--10";
end if;
when others => next_state <= "----------------"; output <= "-------";
end case;
end process;
end behaviour;
|
agpl-3.0
|
chastell/art-decomp
|
kiss/ex6_hot.vhd
|
1
|
4281
|
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity ex6_hot is
port(
clock: in std_logic;
input: in std_logic_vector(4 downto 0);
output: out std_logic_vector(7 downto 0)
);
end ex6_hot;
architecture behaviour of ex6_hot is
constant s1: std_logic_vector(7 downto 0) := "10000000";
constant s3: std_logic_vector(7 downto 0) := "01000000";
constant s2: std_logic_vector(7 downto 0) := "00100000";
constant s4: std_logic_vector(7 downto 0) := "00010000";
constant s5: std_logic_vector(7 downto 0) := "00001000";
constant s6: std_logic_vector(7 downto 0) := "00000100";
constant s7: std_logic_vector(7 downto 0) := "00000010";
constant s8: std_logic_vector(7 downto 0) := "00000001";
signal current_state, next_state: std_logic_vector(7 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "--------"; output <= "--------";
case current_state is
when s1 =>
if std_match(input, "11---") then next_state <= s3; output <= "10111000";
elsif std_match(input, "00---") then next_state <= s2; output <= "11000000";
elsif std_match(input, "10---") then next_state <= s4; output <= "00101000";
end if;
when s2 =>
if std_match(input, "0-0--") then next_state <= s2; output <= "11000000";
elsif std_match(input, "--1--") then next_state <= s5; output <= "00001110";
elsif std_match(input, "110--") then next_state <= s3; output <= "10111000";
elsif std_match(input, "100--") then next_state <= s4; output <= "00101000";
end if;
when s3 =>
if std_match(input, "10---") then next_state <= s4; output <= "00111000";
elsif std_match(input, "00---") then next_state <= s2; output <= "11010000";
elsif std_match(input, "11---") then next_state <= s3; output <= "10111000";
elsif std_match(input, "01---") then next_state <= s6; output <= "00110101";
end if;
when s4 =>
if std_match(input, "010--") then next_state <= s6; output <= "00100101";
elsif std_match(input, "--1--") then next_state <= s7; output <= "00101000";
elsif std_match(input, "110--") then next_state <= s3; output <= "10111000";
elsif std_match(input, "000--") then next_state <= s2; output <= "11000000";
elsif std_match(input, "100--") then next_state <= s4; output <= "00101000";
end if;
when s5 =>
if std_match(input, "1-10-") then next_state <= s8; output <= "10000100";
elsif std_match(input, "--0--") then next_state <= s2; output <= "11000000";
elsif std_match(input, "--11-") then next_state <= s8; output <= "10000100";
elsif std_match(input, "0-10-") then next_state <= s5; output <= "00001110";
end if;
when s6 =>
if std_match(input, "----1") then next_state <= s2; output <= "11000001";
elsif std_match(input, "10--0") then next_state <= s4; output <= "00101001";
elsif std_match(input, "00--0") then next_state <= s2; output <= "11000001";
elsif std_match(input, "11--0") then next_state <= s3; output <= "10111001";
elsif std_match(input, "01--0") then next_state <= s6; output <= "00100101";
end if;
when s7 =>
if std_match(input, "--0--") then next_state <= s2; output <= "11000000";
elsif std_match(input, "101--") then next_state <= s7; output <= "00101000";
elsif std_match(input, "011--") then next_state <= s6; output <= "00100101";
elsif std_match(input, "111--") then next_state <= s3; output <= "10111000";
elsif std_match(input, "001--") then next_state <= s2; output <= "11000000";
end if;
when s8 =>
if std_match(input, "101--") then next_state <= s7; output <= "00101000";
elsif std_match(input, "--0--") then next_state <= s2; output <= "11000000";
elsif std_match(input, "0-1--") then next_state <= s8; output <= "10000100";
elsif std_match(input, "111--") then next_state <= s3; output <= "10111000";
end if;
when others => next_state <= "--------"; output <= "--------";
end case;
end process;
end behaviour;
|
agpl-3.0
|
chastell/art-decomp
|
kiss/sse_nov.vhd
|
1
|
6957
|
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity sse_nov is
port(
clock: in std_logic;
input: in std_logic_vector(6 downto 0);
output: out std_logic_vector(6 downto 0)
);
end sse_nov;
architecture behaviour of sse_nov is
constant st11: std_logic_vector(3 downto 0) := "1100";
constant st10: std_logic_vector(3 downto 0) := "0000";
constant st7: std_logic_vector(3 downto 0) := "0111";
constant st6: std_logic_vector(3 downto 0) := "0001";
constant st12: std_logic_vector(3 downto 0) := "0110";
constant st1: std_logic_vector(3 downto 0) := "0011";
constant st0: std_logic_vector(3 downto 0) := "0101";
constant st8: std_logic_vector(3 downto 0) := "0100";
constant st9: std_logic_vector(3 downto 0) := "1011";
constant st3: std_logic_vector(3 downto 0) := "1010";
constant st2: std_logic_vector(3 downto 0) := "0010";
constant st4: std_logic_vector(3 downto 0) := "1101";
constant st5: std_logic_vector(3 downto 0) := "1001";
constant st13: std_logic_vector(3 downto 0) := "1000";
constant st14: std_logic_vector(3 downto 0) := "1111";
constant st15: std_logic_vector(3 downto 0) := "1110";
signal current_state, next_state: std_logic_vector(3 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "----"; output <= "-------";
case current_state is
when st11 =>
if std_match(input, "0------") then next_state <= st11; output <= "0000000";
elsif std_match(input, "10----0") then next_state <= st10; output <= "00110-0";
elsif std_match(input, "10----1") then next_state <= st10; output <= "00010-0";
elsif std_match(input, "11----0") then next_state <= st4; output <= "0011010";
elsif std_match(input, "11----1") then next_state <= st4; output <= "0001010";
end if;
when st10 =>
if std_match(input, "100----") then next_state <= st10; output <= "00000-0";
elsif std_match(input, "101-1--") then next_state <= st12; output <= "10000-0";
elsif std_match(input, "101-0--") then next_state <= st7; output <= "10000-0";
elsif std_match(input, "0------") then next_state <= st4; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st4; output <= "0000010";
end if;
when st7 =>
if std_match(input, "10-----") then next_state <= st6; output <= "00000-0";
elsif std_match(input, "0------") then next_state <= st4; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st4; output <= "0000010";
end if;
when st6 =>
if std_match(input, "10--0--") then next_state <= st7; output <= "10000-0";
elsif std_match(input, "10--1--") then next_state <= st12; output <= "10000-0";
elsif std_match(input, "0------") then next_state <= st4; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st4; output <= "0000010";
end if;
when st12 =>
if std_match(input, "10-----") then next_state <= st1; output <= "00000-0";
elsif std_match(input, "0------") then next_state <= st4; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st4; output <= "0000010";
end if;
when st1 =>
if std_match(input, "10-1---") then next_state <= st12; output <= "10000-0";
elsif std_match(input, "10--1--") then next_state <= st12; output <= "10000-0";
elsif std_match(input, "10-00--") then next_state <= st0; output <= "0100010";
elsif std_match(input, "0------") then next_state <= st4; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st4; output <= "0000010";
end if;
when st0 =>
if std_match(input, "10---0-") then next_state <= st0; output <= "0100000";
elsif std_match(input, "10---1-") then next_state <= st8; output <= "01000-0";
elsif std_match(input, "0------") then next_state <= st4; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st4; output <= "0000010";
end if;
when st8 =>
if std_match(input, "10-----") then next_state <= st9; output <= "0000010";
elsif std_match(input, "0------") then next_state <= st4; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st4; output <= "0000010";
end if;
when st9 =>
if std_match(input, "10---0-") then next_state <= st9; output <= "0000000";
elsif std_match(input, "10---1-") then next_state <= st3; output <= "10000-0";
elsif std_match(input, "0------") then next_state <= st4; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st4; output <= "0000010";
end if;
when st3 =>
if std_match(input, "10-----") then next_state <= st2; output <= "00000-0";
elsif std_match(input, "0------") then next_state <= st4; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st4; output <= "0000010";
end if;
when st2 =>
if std_match(input, "1001---") then next_state <= st2; output <= "00000-0";
elsif std_match(input, "10-01--") then next_state <= st10; output <= "00010-0";
elsif std_match(input, "10-00--") then next_state <= st0; output <= "0100010";
elsif std_match(input, "1011---") then next_state <= st3; output <= "10000-0";
elsif std_match(input, "0------") then next_state <= st4; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st4; output <= "0000010";
end if;
when st4 =>
if std_match(input, "0----0-") then next_state <= st4; output <= "000--00";
elsif std_match(input, "11---0-") then next_state <= st4; output <= "0000000";
elsif std_match(input, "0----1-") then next_state <= st11; output <= "000---1";
elsif std_match(input, "10-----") then next_state <= st10; output <= "00000-0";
elsif std_match(input, "11---1-") then next_state <= st5; output <= "00001-0";
end if;
when st5 =>
if std_match(input, "11-----") then next_state <= st5; output <= "00001-0";
elsif std_match(input, "10-----") then next_state <= st10; output <= "00000-0";
elsif std_match(input, "0------") then next_state <= st4; output <= "000--10";
end if;
when st13 =>
if std_match(input, "0------") then next_state <= st4; output <= "000--10";
end if;
when st14 =>
if std_match(input, "0------") then next_state <= st4; output <= "000--10";
end if;
when st15 =>
if std_match(input, "0------") then next_state <= st4; output <= "000--10";
end if;
when others => next_state <= "----"; output <= "-------";
end case;
end process;
end behaviour;
|
agpl-3.0
|
chastell/art-decomp
|
kiss/s1a_nov.vhd
|
1
|
11806
|
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity s1a_nov is
port(
clock: in std_logic;
input: in std_logic_vector(7 downto 0);
output: out std_logic_vector(5 downto 0)
);
end s1a_nov;
architecture behaviour of s1a_nov is
constant st0: std_logic_vector(4 downto 0) := "10110";
constant st1: std_logic_vector(4 downto 0) := "11010";
constant st2: std_logic_vector(4 downto 0) := "10101";
constant st3: std_logic_vector(4 downto 0) := "01010";
constant st4: std_logic_vector(4 downto 0) := "11001";
constant st5: std_logic_vector(4 downto 0) := "00110";
constant st6: std_logic_vector(4 downto 0) := "00011";
constant st7: std_logic_vector(4 downto 0) := "01110";
constant st8: std_logic_vector(4 downto 0) := "00000";
constant st9: std_logic_vector(4 downto 0) := "11111";
constant st10: std_logic_vector(4 downto 0) := "00100";
constant st11: std_logic_vector(4 downto 0) := "01001";
constant st12: std_logic_vector(4 downto 0) := "00001";
constant st13: std_logic_vector(4 downto 0) := "10001";
constant st14: std_logic_vector(4 downto 0) := "10010";
constant st15: std_logic_vector(4 downto 0) := "11100";
constant st16: std_logic_vector(4 downto 0) := "11110";
constant st17: std_logic_vector(4 downto 0) := "01101";
constant st18: std_logic_vector(4 downto 0) := "00010";
constant st19: std_logic_vector(4 downto 0) := "11101";
signal current_state, next_state: std_logic_vector(4 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "-----"; output <= "------";
case current_state is
when st0 =>
if std_match(input, "-1-00---") then next_state <= st0; output <= "000000";
elsif std_match(input, "00--0---") then next_state <= st0; output <= "000000";
elsif std_match(input, "-0--1---") then next_state <= st1; output <= "000000";
elsif std_match(input, "-1-01---") then next_state <= st1; output <= "000000";
elsif std_match(input, "01-10---") then next_state <= st2; output <= "000000";
elsif std_match(input, "11-10---") then next_state <= st5; output <= "000000";
elsif std_match(input, "-1-11---") then next_state <= st3; output <= "000000";
elsif std_match(input, "10--0---") then next_state <= st4; output <= "000000";
end if;
when st1 =>
if std_match(input, "-0------") then next_state <= st6; output <= "000000";
elsif std_match(input, "-1-0----") then next_state <= st6; output <= "000000";
elsif std_match(input, "-1-1----") then next_state <= st7; output <= "000000";
end if;
when st2 =>
if std_match(input, "0---0---") then next_state <= st2; output <= "000000";
elsif std_match(input, "----1---") then next_state <= st3; output <= "000000";
elsif std_match(input, "1---0---") then next_state <= st5; output <= "000000";
end if;
when st3 =>
if std_match(input, "--------") then next_state <= st7; output <= "000000";
end if;
when st4 =>
if std_match(input, "--0-----") then next_state <= st12; output <= "000000";
elsif std_match(input, "--1-----") then next_state <= st13; output <= "000000";
end if;
when st5 =>
if std_match(input, "--------") then next_state <= st13; output <= "000000";
end if;
when st6 =>
if std_match(input, "-0--1---") then next_state <= st6; output <= "000000";
elsif std_match(input, "-1-01---") then next_state <= st6; output <= "000000";
elsif std_match(input, "-1-11---") then next_state <= st7; output <= "000000";
elsif std_match(input, "00--0---") then next_state <= st8; output <= "000000";
elsif std_match(input, "-1-00---") then next_state <= st8; output <= "000000";
elsif std_match(input, "11-10---") then next_state <= st11; output <= "000000";
elsif std_match(input, "10--0---") then next_state <= st15; output <= "000000";
elsif std_match(input, "01-10---") then next_state <= st9; output <= "000000";
end if;
when st7 =>
if std_match(input, "----1---") then next_state <= st7; output <= "000000";
elsif std_match(input, "0---0---") then next_state <= st9; output <= "000000";
elsif std_match(input, "1---0---") then next_state <= st11; output <= "000000";
end if;
when st8 =>
if std_match(input, "00--00--") then next_state <= st8; output <= "000000";
elsif std_match(input, "00---1-0") then next_state <= st8; output <= "000000";
elsif std_match(input, "-1-000--") then next_state <= st8; output <= "000000";
elsif std_match(input, "-1-0-1-0") then next_state <= st8; output <= "000000";
elsif std_match(input, "00--01-1") then next_state <= st0; output <= "000000";
elsif std_match(input, "-1-001-1") then next_state <= st0; output <= "000000";
elsif std_match(input, "-0--11-1") then next_state <= st1; output <= "000000";
elsif std_match(input, "-1-011-1") then next_state <= st1; output <= "000000";
elsif std_match(input, "10--01-1") then next_state <= st4; output <= "000000";
elsif std_match(input, "01-100--") then next_state <= st9; output <= "000000";
elsif std_match(input, "01-1-1--") then next_state <= st9; output <= "000000";
elsif std_match(input, "01-110--") then next_state <= st10; output <= "000000";
elsif std_match(input, "11-1----") then next_state <= st11; output <= "000000";
elsif std_match(input, "100-10--") then next_state <= st14; output <= "000000";
elsif std_match(input, "-1-010--") then next_state <= st14; output <= "000000";
elsif std_match(input, "101-101-") then next_state <= st14; output <= "000000";
elsif std_match(input, "00--10--") then next_state <= st14; output <= "000000";
elsif std_match(input, "10--00--") then next_state <= st15; output <= "000000";
elsif std_match(input, "10---1-0") then next_state <= st15; output <= "000000";
elsif std_match(input, "101-100-") then next_state <= st15; output <= "000000";
end if;
when st9 =>
if std_match(input, "0---00--") then next_state <= st9; output <= "000000";
elsif std_match(input, "0----1-0") then next_state <= st9; output <= "000000";
elsif std_match(input, "0---01-1") then next_state <= st2; output <= "000000";
elsif std_match(input, "0---10--") then next_state <= st10; output <= "000000";
elsif std_match(input, "0---11-1") then next_state <= st3; output <= "000000";
elsif std_match(input, "1----0--") then next_state <= st11; output <= "000000";
elsif std_match(input, "1----1-0") then next_state <= st11; output <= "000000";
elsif std_match(input, "1----1-1") then next_state <= st5; output <= "000000";
end if;
when st10 =>
if std_match(input, "------0-") then next_state <= st16; output <= "000000";
elsif std_match(input, "------1-") then next_state <= st7; output <= "000000";
end if;
when st11 =>
if std_match(input, "-----1-1") then next_state <= st13; output <= "000000";
elsif std_match(input, "-----0--") then next_state <= st17; output <= "000000";
elsif std_match(input, "-----1-0") then next_state <= st17; output <= "000000";
end if;
when st12 =>
if std_match(input, "1-0-----") then next_state <= st12; output <= "000000";
elsif std_match(input, "1-1-----") then next_state <= st13; output <= "000000";
elsif std_match(input, "0---1---") then next_state <= st1; output <= "000000";
elsif std_match(input, "0---0---") then next_state <= st0; output <= "000000";
end if;
when st13 =>
if std_match(input, "1-------") then next_state <= st13; output <= "000000";
elsif std_match(input, "0---0---") then next_state <= st0; output <= "000000";
elsif std_match(input, "0---1---") then next_state <= st1; output <= "000000";
end if;
when st14 =>
if std_match(input, "---0--1-") then next_state <= st6; output <= "000000";
elsif std_match(input, "---0--0-") then next_state <= st18; output <= "000000";
elsif std_match(input, "-0-1----") then next_state <= st18; output <= "000000";
elsif std_match(input, "-1-1----") then next_state <= st16; output <= "000000";
end if;
when st15 =>
if std_match(input, "--0--0--") then next_state <= st19; output <= "000000";
elsif std_match(input, "--0--1-0") then next_state <= st19; output <= "000000";
elsif std_match(input, "--0--1-1") then next_state <= st12; output <= "000000";
elsif std_match(input, "--1-----") then next_state <= st17; output <= "000000";
end if;
when st16 =>
if std_match(input, "----1-0-") then next_state <= st16; output <= "000000";
elsif std_match(input, "----1-1-") then next_state <= st7; output <= "000000";
elsif std_match(input, "1---0---") then next_state <= st11; output <= "000000";
elsif std_match(input, "0---0---") then next_state <= st9; output <= "000000";
end if;
when st17 =>
if std_match(input, "1----0--") then next_state <= st17; output <= "000000";
elsif std_match(input, "1----1-0") then next_state <= st17; output <= "000000";
elsif std_match(input, "0---00--") then next_state <= st8; output <= "000000";
elsif std_match(input, "0----1-0") then next_state <= st8; output <= "000000";
elsif std_match(input, "0---01-1") then next_state <= st0; output <= "000000";
elsif std_match(input, "0---11-1") then next_state <= st1; output <= "000000";
elsif std_match(input, "1----1-1") then next_state <= st13; output <= "000000";
elsif std_match(input, "0---10--") then next_state <= st14; output <= "000000";
end if;
when st18 =>
if std_match(input, "----1-1-") then next_state <= st6; output <= "000000";
elsif std_match(input, "00--0---") then next_state <= st8; output <= "000000";
elsif std_match(input, "-1-00---") then next_state <= st8; output <= "000000";
elsif std_match(input, "01-10---") then next_state <= st9; output <= "000000";
elsif std_match(input, "11-10---") then next_state <= st11; output <= "000000";
elsif std_match(input, "10--0---") then next_state <= st15; output <= "000000";
elsif std_match(input, "-1-11-0-") then next_state <= st16; output <= "000000";
elsif std_match(input, "-0--1-0-") then next_state <= st18; output <= "000000";
elsif std_match(input, "-1-01-0-") then next_state <= st18; output <= "000000";
end if;
when st19 =>
if std_match(input, "1-0--0--") then next_state <= st19; output <= "000000";
elsif std_match(input, "1-0--1-0") then next_state <= st19; output <= "000000";
elsif std_match(input, "0---00--") then next_state <= st8; output <= "000000";
elsif std_match(input, "0----1-0") then next_state <= st8; output <= "000000";
elsif std_match(input, "0---01-1") then next_state <= st0; output <= "000000";
elsif std_match(input, "0---10--") then next_state <= st14; output <= "000000";
elsif std_match(input, "0---11-1") then next_state <= st1; output <= "000000";
elsif std_match(input, "1-0--1-1") then next_state <= st12; output <= "000000";
elsif std_match(input, "1-1-----") then next_state <= st17; output <= "000000";
end if;
when others => next_state <= "-----"; output <= "------";
end case;
end process;
end behaviour;
|
agpl-3.0
|
chastell/art-decomp
|
kiss/dk17_rnd.vhd
|
1
|
4134
|
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity dk17_rnd is
port(
clock: in std_logic;
input: in std_logic_vector(1 downto 0);
output: out std_logic_vector(2 downto 0)
);
end dk17_rnd;
architecture behaviour of dk17_rnd is
constant s10000000: std_logic_vector(2 downto 0) := "101";
constant s01000000: std_logic_vector(2 downto 0) := "010";
constant s00100000: std_logic_vector(2 downto 0) := "011";
constant s00010000: std_logic_vector(2 downto 0) := "110";
constant s00001000: std_logic_vector(2 downto 0) := "111";
constant s00000100: std_logic_vector(2 downto 0) := "001";
constant s00000010: std_logic_vector(2 downto 0) := "000";
constant s00000001: std_logic_vector(2 downto 0) := "100";
signal current_state, next_state: std_logic_vector(2 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "---"; output <= "---";
case current_state is
when s10000000 =>
if std_match(input, "00") then next_state <= s10000000; output <= "001";
elsif std_match(input, "01") then next_state <= s00010000; output <= "010";
elsif std_match(input, "10") then next_state <= s01000000; output <= "001";
elsif std_match(input, "11") then next_state <= s00001000; output <= "010";
end if;
when s01000000 =>
if std_match(input, "00") then next_state <= s00100000; output <= "000";
elsif std_match(input, "01") then next_state <= s00010000; output <= "000";
elsif std_match(input, "10") then next_state <= s00100000; output <= "010";
elsif std_match(input, "11") then next_state <= s00000100; output <= "000";
end if;
when s00100000 =>
if std_match(input, "00") then next_state <= s10000000; output <= "001";
elsif std_match(input, "01") then next_state <= s10000000; output <= "101";
elsif std_match(input, "10") then next_state <= s01000000; output <= "001";
elsif std_match(input, "11") then next_state <= s01000000; output <= "101";
end if;
when s00010000 =>
if std_match(input, "00") then next_state <= s00010000; output <= "100";
elsif std_match(input, "01") then next_state <= s00001000; output <= "101";
elsif std_match(input, "10") then next_state <= s00010000; output <= "010";
elsif std_match(input, "11") then next_state <= s00001000; output <= "101";
end if;
when s00001000 =>
if std_match(input, "00") then next_state <= s00100000; output <= "000";
elsif std_match(input, "01") then next_state <= s00010000; output <= "100";
elsif std_match(input, "10") then next_state <= s00100000; output <= "010";
elsif std_match(input, "11") then next_state <= s00100000; output <= "100";
end if;
when s00000100 =>
if std_match(input, "00") then next_state <= s00000010; output <= "000";
elsif std_match(input, "01") then next_state <= s00000001; output <= "000";
elsif std_match(input, "10") then next_state <= s00100000; output <= "010";
elsif std_match(input, "11") then next_state <= s00100000; output <= "100";
end if;
when s00000010 =>
if std_match(input, "00") then next_state <= s00010000; output <= "010";
elsif std_match(input, "01") then next_state <= s10000000; output <= "101";
elsif std_match(input, "10") then next_state <= s00001000; output <= "010";
elsif std_match(input, "11") then next_state <= s01000000; output <= "101";
end if;
when s00000001 =>
if std_match(input, "00") then next_state <= s00010000; output <= "100";
elsif std_match(input, "01") then next_state <= s00001000; output <= "100";
elsif std_match(input, "10") then next_state <= s00100000; output <= "010";
elsif std_match(input, "11") then next_state <= s00100000; output <= "100";
end if;
when others => next_state <= "---"; output <= "---";
end case;
end process;
end behaviour;
|
agpl-3.0
|
chastell/art-decomp
|
kiss/dk14_nov.vhd
|
1
|
6084
|
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity dk14_nov is
port(
clock: in std_logic;
input: in std_logic_vector(2 downto 0);
output: out std_logic_vector(4 downto 0)
);
end dk14_nov;
architecture behaviour of dk14_nov is
constant state_1: std_logic_vector(2 downto 0) := "101";
constant state_2: std_logic_vector(2 downto 0) := "111";
constant state_3: std_logic_vector(2 downto 0) := "001";
constant state_4: std_logic_vector(2 downto 0) := "100";
constant state_5: std_logic_vector(2 downto 0) := "011";
constant state_6: std_logic_vector(2 downto 0) := "010";
constant state_7: std_logic_vector(2 downto 0) := "000";
signal current_state, next_state: std_logic_vector(2 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "---"; output <= "-----";
case current_state is
when state_1 =>
if std_match(input, "000") then next_state <= state_3; output <= "00010";
elsif std_match(input, "100") then next_state <= state_4; output <= "00010";
elsif std_match(input, "111") then next_state <= state_3; output <= "01010";
elsif std_match(input, "110") then next_state <= state_4; output <= "01010";
elsif std_match(input, "011") then next_state <= state_3; output <= "01000";
elsif std_match(input, "001") then next_state <= state_5; output <= "00010";
elsif std_match(input, "101") then next_state <= state_5; output <= "01010";
elsif std_match(input, "010") then next_state <= state_6; output <= "01000";
end if;
when state_2 =>
if std_match(input, "000") then next_state <= state_1; output <= "01001";
elsif std_match(input, "100") then next_state <= state_2; output <= "01001";
elsif std_match(input, "111") then next_state <= state_3; output <= "00100";
elsif std_match(input, "110") then next_state <= state_5; output <= "00100";
elsif std_match(input, "011") then next_state <= state_2; output <= "00101";
elsif std_match(input, "001") then next_state <= state_1; output <= "00101";
elsif std_match(input, "101") then next_state <= state_1; output <= "00001";
elsif std_match(input, "010") then next_state <= state_2; output <= "00001";
end if;
when state_3 =>
if std_match(input, "000") then next_state <= state_3; output <= "10010";
elsif std_match(input, "100") then next_state <= state_4; output <= "10010";
elsif std_match(input, "111") then next_state <= state_3; output <= "01010";
elsif std_match(input, "110") then next_state <= state_4; output <= "01010";
elsif std_match(input, "011") then next_state <= state_3; output <= "01000";
elsif std_match(input, "001") then next_state <= state_5; output <= "10010";
elsif std_match(input, "101") then next_state <= state_5; output <= "01010";
elsif std_match(input, "010") then next_state <= state_6; output <= "01000";
end if;
when state_4 =>
if std_match(input, "000") then next_state <= state_3; output <= "00010";
elsif std_match(input, "100") then next_state <= state_4; output <= "00010";
elsif std_match(input, "111") then next_state <= state_3; output <= "00100";
elsif std_match(input, "110") then next_state <= state_5; output <= "00100";
elsif std_match(input, "011") then next_state <= state_3; output <= "10100";
elsif std_match(input, "001") then next_state <= state_5; output <= "00010";
elsif std_match(input, "101") then next_state <= state_5; output <= "10100";
elsif std_match(input, "010") then next_state <= state_7; output <= "10000";
end if;
when state_5 =>
if std_match(input, "000") then next_state <= state_1; output <= "01001";
elsif std_match(input, "100") then next_state <= state_2; output <= "01001";
elsif std_match(input, "111") then next_state <= state_1; output <= "10001";
elsif std_match(input, "110") then next_state <= state_1; output <= "10101";
elsif std_match(input, "011") then next_state <= state_2; output <= "00101";
elsif std_match(input, "001") then next_state <= state_1; output <= "00101";
elsif std_match(input, "101") then next_state <= state_2; output <= "10001";
elsif std_match(input, "010") then next_state <= state_2; output <= "10101";
end if;
when state_6 =>
if std_match(input, "000") then next_state <= state_1; output <= "01001";
elsif std_match(input, "100") then next_state <= state_2; output <= "01001";
elsif std_match(input, "111") then next_state <= state_1; output <= "10001";
elsif std_match(input, "110") then next_state <= state_1; output <= "10101";
elsif std_match(input, "011") then next_state <= state_3; output <= "10100";
elsif std_match(input, "001") then next_state <= state_5; output <= "10100";
elsif std_match(input, "101") then next_state <= state_2; output <= "10001";
elsif std_match(input, "010") then next_state <= state_2; output <= "10101";
end if;
when state_7 =>
if std_match(input, "000") then next_state <= state_3; output <= "10010";
elsif std_match(input, "100") then next_state <= state_4; output <= "10010";
elsif std_match(input, "111") then next_state <= state_1; output <= "10001";
elsif std_match(input, "110") then next_state <= state_1; output <= "10101";
elsif std_match(input, "011") then next_state <= state_3; output <= "10100";
elsif std_match(input, "001") then next_state <= state_5; output <= "10010";
elsif std_match(input, "101") then next_state <= state_2; output <= "10001";
elsif std_match(input, "010") then next_state <= state_2; output <= "10101";
end if;
when others => next_state <= "---"; output <= "-----";
end case;
end process;
end behaviour;
|
agpl-3.0
|
chastell/art-decomp
|
kiss/s510_nov.vhd
|
1
|
13167
|
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity s510_nov is
port(
clock: in std_logic;
input: in std_logic_vector(18 downto 0);
output: out std_logic_vector(6 downto 0)
);
end s510_nov;
architecture behaviour of s510_nov is
constant s000000: std_logic_vector(5 downto 0) := "111101";
constant s010010: std_logic_vector(5 downto 0) := "000010";
constant s010011: std_logic_vector(5 downto 0) := "111100";
constant s000100: std_logic_vector(5 downto 0) := "000011";
constant s000001: std_logic_vector(5 downto 0) := "111111";
constant s100101: std_logic_vector(5 downto 0) := "000000";
constant s100100: std_logic_vector(5 downto 0) := "111110";
constant s000010: std_logic_vector(5 downto 0) := "000001";
constant s000011: std_logic_vector(5 downto 0) := "111001";
constant s011100: std_logic_vector(5 downto 0) := "000110";
constant s011101: std_logic_vector(5 downto 0) := "111000";
constant s000111: std_logic_vector(5 downto 0) := "000111";
constant s000101: std_logic_vector(5 downto 0) := "111011";
constant s010000: std_logic_vector(5 downto 0) := "000100";
constant s010001: std_logic_vector(5 downto 0) := "111010";
constant s001000: std_logic_vector(5 downto 0) := "000101";
constant s001001: std_logic_vector(5 downto 0) := "110101";
constant s010100: std_logic_vector(5 downto 0) := "001010";
constant s010101: std_logic_vector(5 downto 0) := "110100";
constant s001010: std_logic_vector(5 downto 0) := "001011";
constant s001011: std_logic_vector(5 downto 0) := "110111";
constant s011000: std_logic_vector(5 downto 0) := "001000";
constant s011001: std_logic_vector(5 downto 0) := "110110";
constant s011010: std_logic_vector(5 downto 0) := "001001";
constant s011011: std_logic_vector(5 downto 0) := "110001";
constant s001100: std_logic_vector(5 downto 0) := "001110";
constant s001101: std_logic_vector(5 downto 0) := "110000";
constant s011110: std_logic_vector(5 downto 0) := "001111";
constant s011111: std_logic_vector(5 downto 0) := "110011";
constant s100000: std_logic_vector(5 downto 0) := "001100";
constant s100001: std_logic_vector(5 downto 0) := "110010";
constant s100010: std_logic_vector(5 downto 0) := "001101";
constant s100011: std_logic_vector(5 downto 0) := "101101";
constant s001110: std_logic_vector(5 downto 0) := "010010";
constant s001111: std_logic_vector(5 downto 0) := "101100";
constant s100110: std_logic_vector(5 downto 0) := "010011";
constant s100111: std_logic_vector(5 downto 0) := "101111";
constant s101000: std_logic_vector(5 downto 0) := "010000";
constant s101001: std_logic_vector(5 downto 0) := "101110";
constant s101010: std_logic_vector(5 downto 0) := "010001";
constant s101011: std_logic_vector(5 downto 0) := "101001";
constant s101100: std_logic_vector(5 downto 0) := "010110";
constant s101101: std_logic_vector(5 downto 0) := "101000";
constant s101110: std_logic_vector(5 downto 0) := "010111";
constant s010110: std_logic_vector(5 downto 0) := "101011";
constant s010111: std_logic_vector(5 downto 0) := "010100";
constant s000110: std_logic_vector(5 downto 0) := "101010";
signal current_state, next_state: std_logic_vector(5 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "------"; output <= "-------";
case current_state is
when s000000 =>
if std_match(input, "-------------------") then next_state <= s010010; output <= "0011100";
end if;
when s010010 =>
if std_match(input, "--1----------------") then next_state <= s010011; output <= "0000100";
elsif std_match(input, "--0----------------") then next_state <= s010010; output <= "0000100";
end if;
when s010011 =>
if std_match(input, "-------------------") then next_state <= s000100; output <= "0001101";
end if;
when s000100 =>
if std_match(input, "---11--------------") then next_state <= s000001; output <= "0000101";
elsif std_match(input, "---10--------------") then next_state <= s000000; output <= "0000101";
elsif std_match(input, "---0---------------") then next_state <= s000100; output <= "0000101";
end if;
when s000001 =>
if std_match(input, "-------------------") then next_state <= s100101; output <= "0011000";
end if;
when s100101 =>
if std_match(input, "-----1-------------") then next_state <= s100100; output <= "0000000";
elsif std_match(input, "-----0-------------") then next_state <= s100101; output <= "0000000";
end if;
when s100100 =>
if std_match(input, "-------------------") then next_state <= s000010; output <= "0001001";
end if;
when s000010 =>
if std_match(input, "------0------------") then next_state <= s000010; output <= "0000001";
elsif std_match(input, "------10-----------") then next_state <= s000001; output <= "0000001";
elsif std_match(input, "------11-----------") then next_state <= s000011; output <= "0000001";
end if;
when s000011 =>
if std_match(input, "-------------------") then next_state <= s011100; output <= "0011100";
end if;
when s011100 =>
if std_match(input, "--1----------------") then next_state <= s011101; output <= "0000100";
elsif std_match(input, "--0----------------") then next_state <= s011100; output <= "0000100";
end if;
when s011101 =>
if std_match(input, "-------------------") then next_state <= s000111; output <= "0001101";
end if;
when s000111 =>
if std_match(input, "---0---------------") then next_state <= s000111; output <= "0000101";
elsif std_match(input, "---1----0----------") then next_state <= s000011; output <= "0000101";
elsif std_match(input, "---1----1----------") then next_state <= s000101; output <= "0000101";
end if;
when s000101 =>
if std_match(input, "-------------------") then next_state <= s010000; output <= "0001100";
end if;
when s010000 =>
if std_match(input, "--1----------------") then next_state <= s010001; output <= "0000100";
elsif std_match(input, "--0----------------") then next_state <= s010000; output <= "0000100";
end if;
when s010001 =>
if std_match(input, "-------------------") then next_state <= s001000; output <= "0001101";
end if;
when s001000 =>
if std_match(input, "---------0---------") then next_state <= s001000; output <= "0000101";
elsif std_match(input, "---------1---------") then next_state <= s001001; output <= "0000101";
end if;
when s001001 =>
if std_match(input, "-------------------") then next_state <= s010100; output <= "0011100";
end if;
when s010100 =>
if std_match(input, "----------0--------") then next_state <= s010100; output <= "0000100";
elsif std_match(input, "----------1--------") then next_state <= s010101; output <= "0000100";
end if;
when s010101 =>
if std_match(input, "-------------------") then next_state <= s001010; output <= "0001101";
end if;
when s001010 =>
if std_match(input, "-----------00------") then next_state <= s001010; output <= "0000101";
elsif std_match(input, "-----------10------") then next_state <= s001001; output <= "0000101";
elsif std_match(input, "-----------01------") then next_state <= s001010; output <= "0000101";
elsif std_match(input, "-----------11------") then next_state <= s001011; output <= "0000101";
end if;
when s001011 =>
if std_match(input, "-------------------") then next_state <= s011000; output <= "0101100";
end if;
when s011000 =>
if std_match(input, "----------0--------") then next_state <= s011000; output <= "0000100";
elsif std_match(input, "----------1--------") then next_state <= s011001; output <= "0000100";
end if;
when s011001 =>
if std_match(input, "-------------------") then next_state <= s011010; output <= "0001101";
end if;
when s011010 =>
if std_match(input, "-------------0-----") then next_state <= s011010; output <= "0000101";
elsif std_match(input, "-------------1-----") then next_state <= s011011; output <= "0000101";
end if;
when s011011 =>
if std_match(input, "-------------------") then next_state <= s001100; output <= "0001111";
end if;
when s001100 =>
if std_match(input, "--------------0----") then next_state <= s001100; output <= "0000111";
elsif std_match(input, "--------------1----") then next_state <= s001101; output <= "0000111";
end if;
when s001101 =>
if std_match(input, "-------------------") then next_state <= s011110; output <= "0001101";
end if;
when s011110 =>
if std_match(input, "---------------1---") then next_state <= s011111; output <= "0000101";
elsif std_match(input, "---------------0---") then next_state <= s011110; output <= "0000101";
end if;
when s011111 =>
if std_match(input, "-------------------") then next_state <= s100000; output <= "0011100";
end if;
when s100000 =>
if std_match(input, "----------1--------") then next_state <= s100001; output <= "0000100";
elsif std_match(input, "----------0--------") then next_state <= s100000; output <= "0000100";
end if;
when s100001 =>
if std_match(input, "-------------------") then next_state <= s100010; output <= "0001101";
end if;
when s100010 =>
if std_match(input, "------0------------") then next_state <= s100010; output <= "0000101";
elsif std_match(input, "------1------------") then next_state <= s100011; output <= "0000101";
end if;
when s100011 =>
if std_match(input, "-------------------") then next_state <= s001110; output <= "0001111";
end if;
when s001110 =>
if std_match(input, "----------------00-") then next_state <= s001110; output <= "0000111";
elsif std_match(input, "----------------10-") then next_state <= s001101; output <= "0000111";
elsif std_match(input, "----------------01-") then next_state <= s001110; output <= "0000111";
elsif std_match(input, "----------------11-") then next_state <= s001111; output <= "0000111";
end if;
when s001111 =>
if std_match(input, "-------------------") then next_state <= s100110; output <= "0001101";
end if;
when s100110 =>
if std_match(input, "---------------1---") then next_state <= s100111; output <= "0000101";
elsif std_match(input, "---------------0---") then next_state <= s100110; output <= "0000101";
end if;
when s100111 =>
if std_match(input, "-------------------") then next_state <= s101000; output <= "0001100";
end if;
when s101000 =>
if std_match(input, "----------0--------") then next_state <= s101000; output <= "0000100";
elsif std_match(input, "----------1--------") then next_state <= s101001; output <= "0000100";
end if;
when s101001 =>
if std_match(input, "-------------------") then next_state <= s101010; output <= "0001101";
end if;
when s101010 =>
if std_match(input, "------0------------") then next_state <= s101010; output <= "0000101";
elsif std_match(input, "------1------------") then next_state <= s101011; output <= "0000101";
end if;
when s101011 =>
if std_match(input, "-------------------") then next_state <= s101100; output <= "0001111";
end if;
when s101100 =>
if std_match(input, "------------------1") then next_state <= s101101; output <= "0000111";
elsif std_match(input, "------------------0") then next_state <= s101100; output <= "0000111";
end if;
when s101101 =>
if std_match(input, "-------------------") then next_state <= s101110; output <= "1000111";
end if;
when s101110 =>
if std_match(input, "-------------------") then next_state <= s010110; output <= "1000111";
end if;
when s010110 =>
if std_match(input, "1------------------") then next_state <= s010111; output <= "0000000";
elsif std_match(input, "0------------------") then next_state <= s010110; output <= "0000000";
end if;
when s010111 =>
if std_match(input, "-------------------") then next_state <= s000110; output <= "0101100";
end if;
when s000110 =>
if std_match(input, "-1-----------------") then next_state <= s000000; output <= "0000100";
elsif std_match(input, "-0-----------------") then next_state <= s000110; output <= "0000100";
end if;
when others => next_state <= "------"; output <= "-------";
end case;
end process;
end behaviour;
|
agpl-3.0
|
chastell/art-decomp
|
kiss/s420_hot.vhd
|
1
|
17828
|
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity s420_hot is
port(
clock: in std_logic;
input: in std_logic_vector(18 downto 0);
output: out std_logic_vector(1 downto 0)
);
end s420_hot;
architecture behaviour of s420_hot is
constant s1111111111111111: std_logic_vector(17 downto 0) := "100000000000000000";
constant s0000000000000000: std_logic_vector(17 downto 0) := "010000000000000000";
constant s0001000000000000: std_logic_vector(17 downto 0) := "001000000000000000";
constant s0010000000000000: std_logic_vector(17 downto 0) := "000100000000000000";
constant s0011000000000000: std_logic_vector(17 downto 0) := "000010000000000000";
constant s0100000000000000: std_logic_vector(17 downto 0) := "000001000000000000";
constant s0101000000000000: std_logic_vector(17 downto 0) := "000000100000000000";
constant s0110000000000000: std_logic_vector(17 downto 0) := "000000010000000000";
constant s0111000000000000: std_logic_vector(17 downto 0) := "000000001000000000";
constant s1000000000000000: std_logic_vector(17 downto 0) := "000000000100000000";
constant s1001000000000000: std_logic_vector(17 downto 0) := "000000000010000000";
constant s1010000000000000: std_logic_vector(17 downto 0) := "000000000001000000";
constant s1011000000000000: std_logic_vector(17 downto 0) := "000000000000100000";
constant s1100000000000000: std_logic_vector(17 downto 0) := "000000000000010000";
constant s1101000000000000: std_logic_vector(17 downto 0) := "000000000000001000";
constant s1110000000000000: std_logic_vector(17 downto 0) := "000000000000000100";
constant s1111000000000000: std_logic_vector(17 downto 0) := "000000000000000010";
constant s0000000100000000: std_logic_vector(17 downto 0) := "000000000000000001";
signal current_state, next_state: std_logic_vector(17 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "------------------"; output <= "--";
case current_state is
when s1111111111111111 =>
if std_match(input, "1----------------1-") then next_state <= s0000000000000000; output <= "11";
elsif std_match(input, "1----------------00") then next_state <= s0000000000000000; output <= "10";
elsif std_match(input, "1----------------01") then next_state <= s0000000000000000; output <= "11";
elsif std_match(input, "0------------------") then next_state <= s0000000000000000; output <= "10";
end if;
when s0000000000000000 =>
if std_match(input, "10----------------1") then next_state <= s0001000000000000; output <= "01";
elsif std_match(input, "10----------------0") then next_state <= s0001000000000000; output <= "00";
elsif std_match(input, "00-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "01----------------1") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11----------------1") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "-1----------------0") then next_state <= s0000000000000000; output <= "00";
end if;
when s0001000000000000 =>
if std_match(input, "0------------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11---------------1-") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11---------------00") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11---------------01") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "10---------------00") then next_state <= s0010000000000000; output <= "00";
elsif std_match(input, "10---------------10") then next_state <= s0010000000000000; output <= "01";
elsif std_match(input, "10----------------1") then next_state <= s0010000000000000; output <= "01";
end if;
when s0010000000000000 =>
if std_match(input, "00-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "10--------------0-0") then next_state <= s0011000000000000; output <= "00";
elsif std_match(input, "10--------------1-0") then next_state <= s0011000000000000; output <= "01";
elsif std_match(input, "10----------------1") then next_state <= s0011000000000000; output <= "01";
elsif std_match(input, "01-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11--------------0-0") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11--------------1-0") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11----------------1") then next_state <= s0000000000000000; output <= "01";
end if;
when s0011000000000000 =>
if std_match(input, "0------------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11---------------10") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11---------------00") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11----------------1") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "10---------------1-") then next_state <= s0100000000000000; output <= "01";
elsif std_match(input, "10---------------01") then next_state <= s0100000000000000; output <= "01";
elsif std_match(input, "10---------------00") then next_state <= s0100000000000000; output <= "00";
end if;
when s0100000000000000 =>
if std_match(input, "10----------------1") then next_state <= s0101000000000000; output <= "01";
elsif std_match(input, "10-------------0--0") then next_state <= s0101000000000000; output <= "00";
elsif std_match(input, "10-------------1--0") then next_state <= s0101000000000000; output <= "01";
elsif std_match(input, "00-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "01-------------0--1") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11-------------0--1") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "-1-------------0--0") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "01-------------1---") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11-------------1---") then next_state <= s0000000000000000; output <= "01";
end if;
when s0101000000000000 =>
if std_match(input, "0------------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11---------------10") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11---------------00") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11----------------1") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "10---------------10") then next_state <= s0110000000000000; output <= "01";
elsif std_match(input, "10---------------00") then next_state <= s0110000000000000; output <= "00";
elsif std_match(input, "10----------------1") then next_state <= s0110000000000000; output <= "01";
end if;
when s0110000000000000 =>
if std_match(input, "0------------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11--------------1-0") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11--------------0-0") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11----------------1") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "10--------------1--") then next_state <= s0111000000000000; output <= "01";
elsif std_match(input, "10--------------0-0") then next_state <= s0111000000000000; output <= "00";
elsif std_match(input, "10--------------0-1") then next_state <= s0111000000000000; output <= "01";
end if;
when s0111000000000000 =>
if std_match(input, "0------------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11---------------1-") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11---------------00") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11---------------01") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "10---------------1-") then next_state <= s1000000000000000; output <= "01";
elsif std_match(input, "10---------------01") then next_state <= s1000000000000000; output <= "01";
elsif std_match(input, "10---------------00") then next_state <= s1000000000000000; output <= "00";
end if;
when s1000000000000000 =>
if std_match(input, "00-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "10----------------1") then next_state <= s1001000000000000; output <= "01";
elsif std_match(input, "10------------1---0") then next_state <= s1001000000000000; output <= "01";
elsif std_match(input, "10------------0---0") then next_state <= s1001000000000000; output <= "00";
elsif std_match(input, "01------------0---1") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11------------0---1") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11------------1---1") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "01------------1---1") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11------------1---0") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11------------0---0") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "01----------------0") then next_state <= s0000000000000000; output <= "00";
end if;
when s1001000000000000 =>
if std_match(input, "00-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "10---------------1-") then next_state <= s1010000000000000; output <= "01";
elsif std_match(input, "10---------------00") then next_state <= s1010000000000000; output <= "00";
elsif std_match(input, "10---------------01") then next_state <= s1010000000000000; output <= "01";
elsif std_match(input, "01-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11---------------1-") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11---------------01") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11---------------00") then next_state <= s0000000000000000; output <= "00";
end if;
when s1010000000000000 =>
if std_match(input, "00-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "10--------------1--") then next_state <= s1011000000000000; output <= "01";
elsif std_match(input, "10--------------0-1") then next_state <= s1011000000000000; output <= "01";
elsif std_match(input, "10--------------0-0") then next_state <= s1011000000000000; output <= "00";
elsif std_match(input, "01-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11--------------1-0") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11--------------0-0") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11----------------1") then next_state <= s0000000000000000; output <= "01";
end if;
when s1011000000000000 =>
if std_match(input, "00-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "10---------------00") then next_state <= s1100000000000000; output <= "00";
elsif std_match(input, "10---------------10") then next_state <= s1100000000000000; output <= "01";
elsif std_match(input, "10----------------1") then next_state <= s1100000000000000; output <= "01";
elsif std_match(input, "01-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11---------------10") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11---------------00") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11----------------1") then next_state <= s0000000000000000; output <= "01";
end if;
when s1100000000000000 =>
if std_match(input, "00-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "10-------------0--1") then next_state <= s1101000000000000; output <= "01";
elsif std_match(input, "10-------------0--0") then next_state <= s1101000000000000; output <= "00";
elsif std_match(input, "10-------------1---") then next_state <= s1101000000000000; output <= "01";
elsif std_match(input, "11----------------1") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "01----------------1") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11-------------0--0") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11-------------1--0") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "01----------------0") then next_state <= s0000000000000000; output <= "00";
end if;
when s1101000000000000 =>
if std_match(input, "0------------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "10---------------1-") then next_state <= s1110000000000000; output <= "01";
elsif std_match(input, "10---------------00") then next_state <= s1110000000000000; output <= "00";
elsif std_match(input, "10---------------01") then next_state <= s1110000000000000; output <= "01";
elsif std_match(input, "11---------------1-") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11---------------00") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11---------------01") then next_state <= s0000000000000000; output <= "01";
end if;
when s1110000000000000 =>
if std_match(input, "10--------------1--") then next_state <= s1111000000000000; output <= "01";
elsif std_match(input, "10--------------0-0") then next_state <= s1111000000000000; output <= "00";
elsif std_match(input, "10--------------0-1") then next_state <= s1111000000000000; output <= "01";
elsif std_match(input, "00-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "01-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11--------------1--") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11--------------0-0") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11--------------0-1") then next_state <= s0000000000000000; output <= "01";
end if;
when s1111000000000000 =>
if std_match(input, "01-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11---------------00") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11---------------10") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11----------------1") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "00-----------------") then next_state <= s0000000100000000; output <= "00";
elsif std_match(input, "10---------------10") then next_state <= s0000000100000000; output <= "01";
elsif std_match(input, "10---------------00") then next_state <= s0000000100000000; output <= "00";
elsif std_match(input, "10----------------1") then next_state <= s0000000100000000; output <= "01";
end if;
when s0000000100000000 =>
if std_match(input, "00-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "10-----------1-----") then next_state <= s0001000000000000; output <= "01";
elsif std_match(input, "10-----------0----0") then next_state <= s0001000000000000; output <= "00";
elsif std_match(input, "10-----------0----1") then next_state <= s0001000000000000; output <= "01";
elsif std_match(input, "01-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11-----------1----0") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11-----------0----0") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11----------------1") then next_state <= s0000000000000000; output <= "01";
end if;
when others => next_state <= "------------------"; output <= "--";
end case;
end process;
end behaviour;
|
agpl-3.0
|
chastell/art-decomp
|
kiss/donfile_jed.vhd
|
1
|
10163
|
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity donfile_jed is
port(
clock: in std_logic;
input: in std_logic_vector(1 downto 0);
output: out std_logic_vector(0 downto 0)
);
end donfile_jed;
architecture behaviour of donfile_jed is
constant st0: std_logic_vector(4 downto 0) := "10111";
constant st6: std_logic_vector(4 downto 0) := "10110";
constant st12: std_logic_vector(4 downto 0) := "10001";
constant st18: std_logic_vector(4 downto 0) := "10000";
constant st1: std_logic_vector(4 downto 0) := "10101";
constant st7: std_logic_vector(4 downto 0) := "10100";
constant st2: std_logic_vector(4 downto 0) := "11111";
constant st19: std_logic_vector(4 downto 0) := "00000";
constant st3: std_logic_vector(4 downto 0) := "01111";
constant st13: std_logic_vector(4 downto 0) := "01001";
constant st4: std_logic_vector(4 downto 0) := "00101";
constant st5: std_logic_vector(4 downto 0) := "00111";
constant st14: std_logic_vector(4 downto 0) := "11101";
constant st20: std_logic_vector(4 downto 0) := "11100";
constant st8: std_logic_vector(4 downto 0) := "11110";
constant st21: std_logic_vector(4 downto 0) := "11000";
constant st9: std_logic_vector(4 downto 0) := "01110";
constant st15: std_logic_vector(4 downto 0) := "11001";
constant st10: std_logic_vector(4 downto 0) := "00100";
constant st11: std_logic_vector(4 downto 0) := "00110";
constant st22: std_logic_vector(4 downto 0) := "01000";
constant st23: std_logic_vector(4 downto 0) := "01100";
constant st16: std_logic_vector(4 downto 0) := "00001";
constant st17: std_logic_vector(4 downto 0) := "01101";
signal current_state, next_state: std_logic_vector(4 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "-----"; output <= "-";
case current_state is
when st0 =>
if std_match(input, "00") then next_state <= st0; output <= "1";
elsif std_match(input, "01") then next_state <= st6; output <= "1";
elsif std_match(input, "10") then next_state <= st12; output <= "1";
elsif std_match(input, "11") then next_state <= st18; output <= "1";
end if;
when st1 =>
if std_match(input, "00") then next_state <= st1; output <= "1";
elsif std_match(input, "01") then next_state <= st7; output <= "1";
elsif std_match(input, "10") then next_state <= st12; output <= "1";
elsif std_match(input, "11") then next_state <= st18; output <= "1";
end if;
when st2 =>
if std_match(input, "00") then next_state <= st2; output <= "1";
elsif std_match(input, "01") then next_state <= st6; output <= "1";
elsif std_match(input, "10") then next_state <= st12; output <= "1";
elsif std_match(input, "11") then next_state <= st19; output <= "1";
end if;
when st3 =>
if std_match(input, "00") then next_state <= st3; output <= "1";
elsif std_match(input, "01") then next_state <= st6; output <= "1";
elsif std_match(input, "10") then next_state <= st13; output <= "1";
elsif std_match(input, "11") then next_state <= st19; output <= "1";
end if;
when st4 =>
if std_match(input, "00") then next_state <= st4; output <= "1";
elsif std_match(input, "01") then next_state <= st7; output <= "1";
elsif std_match(input, "10") then next_state <= st13; output <= "1";
elsif std_match(input, "11") then next_state <= st18; output <= "1";
end if;
when st5 =>
if std_match(input, "00") then next_state <= st5; output <= "1";
elsif std_match(input, "01") then next_state <= st7; output <= "1";
elsif std_match(input, "10") then next_state <= st13; output <= "1";
elsif std_match(input, "11") then next_state <= st19; output <= "1";
end if;
when st6 =>
if std_match(input, "00") then next_state <= st0; output <= "1";
elsif std_match(input, "01") then next_state <= st6; output <= "1";
elsif std_match(input, "10") then next_state <= st14; output <= "1";
elsif std_match(input, "11") then next_state <= st20; output <= "1";
end if;
when st7 =>
if std_match(input, "00") then next_state <= st1; output <= "1";
elsif std_match(input, "01") then next_state <= st7; output <= "1";
elsif std_match(input, "10") then next_state <= st14; output <= "1";
elsif std_match(input, "11") then next_state <= st20; output <= "1";
end if;
when st8 =>
if std_match(input, "00") then next_state <= st0; output <= "1";
elsif std_match(input, "01") then next_state <= st8; output <= "1";
elsif std_match(input, "10") then next_state <= st14; output <= "1";
elsif std_match(input, "11") then next_state <= st21; output <= "1";
end if;
when st9 =>
if std_match(input, "00") then next_state <= st0; output <= "1";
elsif std_match(input, "01") then next_state <= st9; output <= "1";
elsif std_match(input, "10") then next_state <= st15; output <= "1";
elsif std_match(input, "11") then next_state <= st21; output <= "1";
end if;
when st10 =>
if std_match(input, "00") then next_state <= st1; output <= "1";
elsif std_match(input, "01") then next_state <= st10; output <= "1";
elsif std_match(input, "10") then next_state <= st15; output <= "1";
elsif std_match(input, "11") then next_state <= st20; output <= "1";
end if;
when st11 =>
if std_match(input, "00") then next_state <= st1; output <= "1";
elsif std_match(input, "01") then next_state <= st11; output <= "1";
elsif std_match(input, "10") then next_state <= st15; output <= "1";
elsif std_match(input, "11") then next_state <= st21; output <= "1";
end if;
when st12 =>
if std_match(input, "00") then next_state <= st2; output <= "1";
elsif std_match(input, "01") then next_state <= st8; output <= "1";
elsif std_match(input, "10") then next_state <= st12; output <= "1";
elsif std_match(input, "11") then next_state <= st22; output <= "1";
end if;
when st13 =>
if std_match(input, "00") then next_state <= st3; output <= "1";
elsif std_match(input, "01") then next_state <= st8; output <= "1";
elsif std_match(input, "10") then next_state <= st13; output <= "1";
elsif std_match(input, "11") then next_state <= st22; output <= "1";
end if;
when st14 =>
if std_match(input, "00") then next_state <= st2; output <= "1";
elsif std_match(input, "01") then next_state <= st8; output <= "1";
elsif std_match(input, "10") then next_state <= st14; output <= "1";
elsif std_match(input, "11") then next_state <= st23; output <= "1";
end if;
when st15 =>
if std_match(input, "00") then next_state <= st2; output <= "1";
elsif std_match(input, "01") then next_state <= st9; output <= "1";
elsif std_match(input, "10") then next_state <= st15; output <= "1";
elsif std_match(input, "11") then next_state <= st23; output <= "1";
end if;
when st16 =>
if std_match(input, "00") then next_state <= st3; output <= "1";
elsif std_match(input, "01") then next_state <= st9; output <= "1";
elsif std_match(input, "10") then next_state <= st16; output <= "1";
elsif std_match(input, "11") then next_state <= st22; output <= "1";
end if;
when st17 =>
if std_match(input, "00") then next_state <= st3; output <= "1";
elsif std_match(input, "01") then next_state <= st9; output <= "1";
elsif std_match(input, "10") then next_state <= st17; output <= "1";
elsif std_match(input, "11") then next_state <= st23; output <= "1";
end if;
when st18 =>
if std_match(input, "00") then next_state <= st4; output <= "1";
elsif std_match(input, "01") then next_state <= st10; output <= "1";
elsif std_match(input, "10") then next_state <= st16; output <= "1";
elsif std_match(input, "11") then next_state <= st18; output <= "1";
end if;
when st19 =>
if std_match(input, "00") then next_state <= st5; output <= "1";
elsif std_match(input, "01") then next_state <= st10; output <= "1";
elsif std_match(input, "10") then next_state <= st16; output <= "1";
elsif std_match(input, "11") then next_state <= st19; output <= "1";
end if;
when st20 =>
if std_match(input, "00") then next_state <= st4; output <= "1";
elsif std_match(input, "01") then next_state <= st10; output <= "1";
elsif std_match(input, "10") then next_state <= st17; output <= "1";
elsif std_match(input, "11") then next_state <= st20; output <= "1";
end if;
when st21 =>
if std_match(input, "00") then next_state <= st4; output <= "1";
elsif std_match(input, "01") then next_state <= st11; output <= "1";
elsif std_match(input, "10") then next_state <= st17; output <= "1";
elsif std_match(input, "11") then next_state <= st21; output <= "1";
end if;
when st22 =>
if std_match(input, "00") then next_state <= st5; output <= "1";
elsif std_match(input, "01") then next_state <= st11; output <= "1";
elsif std_match(input, "10") then next_state <= st16; output <= "1";
elsif std_match(input, "11") then next_state <= st22; output <= "1";
end if;
when st23 =>
if std_match(input, "00") then next_state <= st5; output <= "1";
elsif std_match(input, "01") then next_state <= st11; output <= "1";
elsif std_match(input, "10") then next_state <= st17; output <= "1";
elsif std_match(input, "11") then next_state <= st23; output <= "1";
end if;
when others => next_state <= "-----"; output <= "-";
end case;
end process;
end behaviour;
|
agpl-3.0
|
chastell/art-decomp
|
kiss/opus_hot.vhd
|
1
|
3568
|
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity opus_hot is
port(
clock: in std_logic;
input: in std_logic_vector(4 downto 0);
output: out std_logic_vector(5 downto 0)
);
end opus_hot;
architecture behaviour of opus_hot is
constant init0: std_logic_vector(9 downto 0) := "1000000000";
constant init1: std_logic_vector(9 downto 0) := "0100000000";
constant init2: std_logic_vector(9 downto 0) := "0010000000";
constant init4: std_logic_vector(9 downto 0) := "0001000000";
constant IOwait: std_logic_vector(9 downto 0) := "0000100000";
constant read0: std_logic_vector(9 downto 0) := "0000010000";
constant write0: std_logic_vector(9 downto 0) := "0000001000";
constant RMACK: std_logic_vector(9 downto 0) := "0000000100";
constant WMACK: std_logic_vector(9 downto 0) := "0000000010";
constant read1: std_logic_vector(9 downto 0) := "0000000001";
signal current_state, next_state: std_logic_vector(9 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "----------"; output <= "------";
if std_match(input, "--1--") then next_state <= init0; output <= "110000";
else
case current_state is
when init0 =>
if std_match(input, "--1--") then next_state <= init0; output <= "110000";
elsif std_match(input, "--0--") then next_state <= init1; output <= "110000";
end if;
when init1 =>
if std_match(input, "--00-") then next_state <= init1; output <= "110000";
elsif std_match(input, "--01-") then next_state <= init2; output <= "110001";
end if;
when init2 =>
if std_match(input, "--0--") then next_state <= init4; output <= "110100";
end if;
when init4 =>
if std_match(input, "--01-") then next_state <= init4; output <= "110100";
elsif std_match(input, "--00-") then next_state <= IOwait; output <= "000000";
end if;
when IOwait =>
if std_match(input, "0000-") then next_state <= IOwait; output <= "000000";
elsif std_match(input, "1000-") then next_state <= init1; output <= "110000";
elsif std_match(input, "01000") then next_state <= read0; output <= "101000";
elsif std_match(input, "11000") then next_state <= write0; output <= "100010";
elsif std_match(input, "01001") then next_state <= RMACK; output <= "100000";
elsif std_match(input, "11001") then next_state <= WMACK; output <= "100000";
elsif std_match(input, "--01-") then next_state <= init2; output <= "110001";
end if;
when RMACK =>
if std_match(input, "--0-0") then next_state <= RMACK; output <= "100000";
elsif std_match(input, "--0-1") then next_state <= read0; output <= "101000";
end if;
when WMACK =>
if std_match(input, "--0-0") then next_state <= WMACK; output <= "100000";
elsif std_match(input, "--0-1") then next_state <= write0; output <= "100010";
end if;
when read0 =>
if std_match(input, "--0--") then next_state <= read1; output <= "101001";
end if;
when read1 =>
if std_match(input, "--0--") then next_state <= IOwait; output <= "000000";
end if;
when write0 =>
if std_match(input, "--0--") then next_state <= IOwait; output <= "000000";
end if;
when others => next_state <= "----------"; output <= "------";
end case;
end if;
end process;
end behaviour;
|
agpl-3.0
|
chastell/art-decomp
|
kiss/s832_rnd.vhd
|
1
|
30735
|
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity s832_rnd is
port(
clock: in std_logic;
input: in std_logic_vector(17 downto 0);
output: out std_logic_vector(18 downto 0)
);
end s832_rnd;
architecture behaviour of s832_rnd is
constant s00000: std_logic_vector(4 downto 0) := "11101";
constant s10000: std_logic_vector(4 downto 0) := "00010";
constant s01110: std_logic_vector(4 downto 0) := "11011";
constant s10001: std_logic_vector(4 downto 0) := "11110";
constant s01111: std_logic_vector(4 downto 0) := "11111";
constant s00010: std_logic_vector(4 downto 0) := "10001";
constant s00001: std_logic_vector(4 downto 0) := "10110";
constant s00100: std_logic_vector(4 downto 0) := "01011";
constant s00011: std_logic_vector(4 downto 0) := "01111";
constant s00101: std_logic_vector(4 downto 0) := "00001";
constant s00110: std_logic_vector(4 downto 0) := "10000";
constant s11111: std_logic_vector(4 downto 0) := "11010";
constant s00111: std_logic_vector(4 downto 0) := "11000";
constant s10111: std_logic_vector(4 downto 0) := "01000";
constant s01011: std_logic_vector(4 downto 0) := "00100";
constant s01000: std_logic_vector(4 downto 0) := "01001";
constant s01100: std_logic_vector(4 downto 0) := "00110";
constant s01101: std_logic_vector(4 downto 0) := "11100";
constant s01001: std_logic_vector(4 downto 0) := "00011";
constant s01010: std_logic_vector(4 downto 0) := "10111";
constant s11000: std_logic_vector(4 downto 0) := "10011";
constant s11011: std_logic_vector(4 downto 0) := "10010";
constant s11001: std_logic_vector(4 downto 0) := "00111";
constant s11010: std_logic_vector(4 downto 0) := "01100";
constant s11100: std_logic_vector(4 downto 0) := "10101";
signal current_state, next_state: std_logic_vector(4 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "-----"; output <= "-------------------";
case current_state is
when s00000 =>
if std_match(input, "-1---------------1") then next_state <= s00000; output <= "0001000000000010000";
elsif std_match(input, "-0-0------------11") then next_state <= s00000; output <= "0000000000000010001";
elsif std_match(input, "-0-0------------01") then next_state <= s00000; output <= "0000000000000010000";
elsif std_match(input, "-0-1------------11") then next_state <= s00000; output <= "0000000000000010001";
elsif std_match(input, "-0-1------------01") then next_state <= s00000; output <= "0010000000000010000";
elsif std_match(input, "-1---------------0") then next_state <= s10000; output <= "0001000000000010000";
elsif std_match(input, "-001------------00") then next_state <= s00000; output <= "0010000000000010000";
elsif std_match(input, "-000------------00") then next_state <= s00000; output <= "0000000000000010000";
elsif std_match(input, "-011------------00") then next_state <= s00000; output <= "0010000000000010000";
elsif std_match(input, "-010------------00") then next_state <= s01110; output <= "0000000000000010000";
elsif std_match(input, "-0--------------10") then next_state <= s10001; output <= "0000000000000010001";
end if;
when s10000 =>
if std_match(input, "-----------------1") then next_state <= s00000; output <= "0000000000000000000";
elsif std_match(input, "1----------------0") then next_state <= s00000; output <= "0000000000000000000";
elsif std_match(input, "0----------------0") then next_state <= s10000; output <= "0000000000000000000";
end if;
when s01110 =>
if std_match(input, "-----------------1") then next_state <= s00000; output <= "0000000001000000000";
elsif std_match(input, "-----------------0") then next_state <= s01111; output <= "0000000001000000000";
end if;
when s01111 =>
if std_match(input, "----------------00") then next_state <= s00010; output <= "0000000000000010000";
elsif std_match(input, "----------------01") then next_state <= s00000; output <= "0000000000000010000";
elsif std_match(input, "----------------11") then next_state <= s00000; output <= "0000010000000010000";
elsif std_match(input, "----------------10") then next_state <= s00001; output <= "0000010000000010000";
end if;
when s00010 =>
if std_match(input, "--------------01-1") then next_state <= s00000; output <= "0000001000000000100";
elsif std_match(input, "--------------11-1") then next_state <= s00000; output <= "0000001000001000100";
elsif std_match(input, "--------------01-0") then next_state <= s00100; output <= "0000001000000000100";
elsif std_match(input, "--------------11-0") then next_state <= s00011; output <= "0000001000001000100";
elsif std_match(input, "---------------0-0") then next_state <= s00010; output <= "0000001000000000000";
elsif std_match(input, "---------------0-1") then next_state <= s00000; output <= "0000001000000000000";
end if;
when s00100 =>
if std_match(input, "----0-1001-----110") then next_state <= s00101; output <= "0000000100000000000";
elsif std_match(input, "----0-0001-----110") then next_state <= s00100; output <= "0000000100000000000";
elsif std_match(input, "----0--101-----110") then next_state <= s00100; output <= "0000000100000000000";
elsif std_match(input, "----0---11-----110") then next_state <= s00100; output <= "0000000100000000000";
elsif std_match(input, "----0----0-----110") then next_state <= s00100; output <= "0000000100000000000";
elsif std_match(input, "----0----------010") then next_state <= s00100; output <= "0000000100000000000";
elsif std_match(input, "----0-----------11") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----1-----------10") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "----1-----------11") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----0-----------01") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----0-----------00") then next_state <= s00010; output <= "0000000100000000001";
elsif std_match(input, "----1-----------01") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----1-----------00") then next_state <= s00001; output <= "0000000100000000001";
end if;
when s00101 =>
if std_match(input, "----0-----------11") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----1-----------11") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----------------01") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----1------------0") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "----0----------010") then next_state <= s00101; output <= "0000000100000000000";
elsif std_match(input, "----0----------110") then next_state <= s00110; output <= "0000000100000000000";
elsif std_match(input, "----0-----------00") then next_state <= s00010; output <= "0000000100000000001";
end if;
when s00001 =>
if std_match(input, "------0--------0-1") then next_state <= s00000; output <= "0000000000000000000";
elsif std_match(input, "------0--------010") then next_state <= s00001; output <= "0000000000000000000";
elsif std_match(input, "------0--------000") then next_state <= s00010; output <= "0000000000000000000";
elsif std_match(input, "------0--------101") then next_state <= s00000; output <= "0000000000000000000";
elsif std_match(input, "------0--------100") then next_state <= s00010; output <= "0000000000000000000";
elsif std_match(input, "------0--------111") then next_state <= s00000; output <= "0000000000000000000";
elsif std_match(input, "------0--------110") then next_state <= s00001; output <= "0000000000000000000";
elsif std_match(input, "------10---------1") then next_state <= s00000; output <= "0000000000000000000";
elsif std_match(input, "----1-10--------10") then next_state <= s00001; output <= "0000000000000000000";
elsif std_match(input, "----0-10-------010") then next_state <= s00001; output <= "0000000000000000000";
elsif std_match(input, "----0-10-------110") then next_state <= s00001; output <= "0000000000000000000";
elsif std_match(input, "------10--------00") then next_state <= s00010; output <= "0000000000000000000";
elsif std_match(input, "------110--------1") then next_state <= s00000; output <= "0000000000000000000";
elsif std_match(input, "----1-110-------10") then next_state <= s00001; output <= "0000000000000000000";
elsif std_match(input, "----0-110------010") then next_state <= s00001; output <= "0000000000000000000";
elsif std_match(input, "----0-110------110") then next_state <= s00001; output <= "0000000000000000000";
elsif std_match(input, "------110-------00") then next_state <= s00010; output <= "0000000000000000000";
elsif std_match(input, "------111--------1") then next_state <= s00000; output <= "0000000000000000000";
elsif std_match(input, "------1110-----010") then next_state <= s00001; output <= "0000000000000000000";
elsif std_match(input, "------1110-----000") then next_state <= s00010; output <= "0000000000000000000";
elsif std_match(input, "------1110-----110") then next_state <= s00001; output <= "0000000000000000000";
elsif std_match(input, "------1110-----100") then next_state <= s00010; output <= "0000000000000000000";
elsif std_match(input, "------1111------00") then next_state <= s00010; output <= "0000000000000000000";
elsif std_match(input, "------1111------10") then next_state <= s00001; output <= "0000000000000000000";
end if;
when s00110 =>
if std_match(input, "----------------01") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----0----------011") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----1----------011") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----1----------111") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----0-----110--111") then next_state <= s00000; output <= "0000100100000000000";
elsif std_match(input, "----0-----100--111") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----0-----0-0--111") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----0-----001--111") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----0-----101--111") then next_state <= s00000; output <= "0000100100000000000";
elsif std_match(input, "----0------11--111") then next_state <= s00000; output <= "0000100100000000000";
elsif std_match(input, "----1-----1------0") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "----0-----1----000") then next_state <= s00010; output <= "0000000100000000001";
elsif std_match(input, "----0-----1----010") then next_state <= s00110; output <= "0000000100000000000";
elsif std_match(input, "----0-----11---110") then next_state <= s11111; output <= "0000100100000000000";
elsif std_match(input, "----0-----11---100") then next_state <= s00010; output <= "0000000100000000001";
elsif std_match(input, "----0-----10---100") then next_state <= s00010; output <= "0000000100000000001";
elsif std_match(input, "----0-----101--110") then next_state <= s11111; output <= "0000100100000000000";
elsif std_match(input, "----0-----100--110") then next_state <= s00111; output <= "0000000100000000000";
elsif std_match(input, "----1-----0------0") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "----0-----0----010") then next_state <= s00110; output <= "0000000100000000000";
elsif std_match(input, "----0-----0----000") then next_state <= s00010; output <= "0000000100000000001";
elsif std_match(input, "----0-----011--110") then next_state <= s11111; output <= "0000100100000000000";
elsif std_match(input, "----0-----010--110") then next_state <= s10111; output <= "0000000100000000000";
elsif std_match(input, "----0-----01---100") then next_state <= s00010; output <= "0000000100000000001";
elsif std_match(input, "----0-----00---100") then next_state <= s00010; output <= "0000000100000000001";
elsif std_match(input, "----0-----00---110") then next_state <= s01011; output <= "0000000100000000000";
end if;
when s11111 =>
if std_match(input, "0----------------1") then next_state <= s00000; output <= "0000000000000000000";
elsif std_match(input, "0----------------0") then next_state <= s11111; output <= "0000000000000000000";
elsif std_match(input, "1-----------------") then next_state <= s00000; output <= "0000000000000000000";
end if;
when s00111 =>
if std_match(input, "----1-----------11") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----0-----------11") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----------------01") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----1----------110") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "----0--------0-110") then next_state <= s01011; output <= "0000000100000000000";
elsif std_match(input, "----0--------1-110") then next_state <= s01000; output <= "0000000100000000000";
elsif std_match(input, "----0----------010") then next_state <= s00111; output <= "0000000100000000000";
elsif std_match(input, "----1----------010") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "----0-----------00") then next_state <= s00010; output <= "0000000100000000001";
elsif std_match(input, "----1-----------00") then next_state <= s00001; output <= "0000000100000000001";
end if;
when s01011 =>
if std_match(input, "----0----------010") then next_state <= s01011; output <= "0000000100000000000";
elsif std_match(input, "----0----------110") then next_state <= s01011; output <= "0000000100000000000";
elsif std_match(input, "----0-----------00") then next_state <= s01100; output <= "0000000100010000000";
elsif std_match(input, "----0-----------11") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----0-----------01") then next_state <= s00000; output <= "0000000100010000000";
elsif std_match(input, "----1------------0") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "----1------------1") then next_state <= s00000; output <= "0000000100000000001";
end if;
when s01100 =>
if std_match(input, "-----0-----------1") then next_state <= s00000; output <= "0000000010000100000";
elsif std_match(input, "-----0-----------0") then next_state <= s01101; output <= "0000000010000100000";
elsif std_match(input, "-----1-----------1") then next_state <= s00000; output <= "0000000000000101000";
elsif std_match(input, "-----1-----------0") then next_state <= s00010; output <= "0000000000000101000";
end if;
when s01101 =>
if std_match(input, "-1---------------1") then next_state <= s00000; output <= "0101000000000000010";
elsif std_match(input, "-1---------------0") then next_state <= s10000; output <= "0101000000000000010";
elsif std_match(input, "-0---------------1") then next_state <= s00000; output <= "0100000000000000010";
elsif std_match(input, "-010-------------0") then next_state <= s01110; output <= "0100000000000000010";
elsif std_match(input, "-000-------------0") then next_state <= s01101; output <= "0100000000000000010";
elsif std_match(input, "-0-1-------------0") then next_state <= s00000; output <= "0100000000000000010";
end if;
when s01000 =>
if std_match(input, "----1----------011") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----0----------011") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----1----------111") then next_state <= s00000; output <= "0000000100100000001";
elsif std_match(input, "----0----------111") then next_state <= s00000; output <= "0000000100100000000";
elsif std_match(input, "----0----------010") then next_state <= s01000; output <= "0000000100000000000";
elsif std_match(input, "----0----------110") then next_state <= s01001; output <= "0000000100100000000";
elsif std_match(input, "----1----------110") then next_state <= s00001; output <= "0000000100100000001";
elsif std_match(input, "----1----------010") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "---------------001") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "---------------101") then next_state <= s00000; output <= "0000000100100000001";
elsif std_match(input, "----0----------100") then next_state <= s00010; output <= "0000000100100000001";
elsif std_match(input, "----0----------000") then next_state <= s00010; output <= "0000000100000000001";
elsif std_match(input, "----1----------000") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "----1----------100") then next_state <= s00001; output <= "0000000100100000001";
end if;
when s01001 =>
if std_match(input, "----0----------010") then next_state <= s01001; output <= "0000000100000000000";
elsif std_match(input, "----0----------110") then next_state <= s01010; output <= "1000000100000000000";
elsif std_match(input, "----0----------011") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----0----------111") then next_state <= s00000; output <= "1000000100000000000";
elsif std_match(input, "----1----------111") then next_state <= s00000; output <= "1000000100000000001";
elsif std_match(input, "----1----------011") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----1----------010") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "----1----------110") then next_state <= s00001; output <= "1000000100000000001";
elsif std_match(input, "---------------001") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "---------------101") then next_state <= s00000; output <= "1000000100000000001";
elsif std_match(input, "----1----------000") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "----1----------100") then next_state <= s00001; output <= "1000000100000000001";
elsif std_match(input, "----0----------000") then next_state <= s00010; output <= "0000000100000000001";
elsif std_match(input, "----0----------100") then next_state <= s00010; output <= "1000000100000000001";
end if;
when s01010 =>
if std_match(input, "----1-----------11") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----0-----------11") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----1-----------10") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "----0----------110") then next_state <= s01011; output <= "0000000100000000000";
elsif std_match(input, "----0----------010") then next_state <= s01010; output <= "0000000100000000000";
elsif std_match(input, "----------------01") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----0-----------00") then next_state <= s00010; output <= "0000000100000000001";
elsif std_match(input, "----1-----------00") then next_state <= s00001; output <= "0000000100000000001";
end if;
when s10111 =>
if std_match(input, "----1-----------11") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----0-----------11") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----1-----------10") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "----0----------010") then next_state <= s10111; output <= "0000000100000000000";
elsif std_match(input, "----0--------1-110") then next_state <= s11000; output <= "0000000100000000000";
elsif std_match(input, "----0--------0-110") then next_state <= s11011; output <= "0000000100000000000";
elsif std_match(input, "----0-----------01") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----0-----------00") then next_state <= s00010; output <= "0000000100000000001";
elsif std_match(input, "----1-----------01") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----1-----------00") then next_state <= s00001; output <= "0000000100000000001";
end if;
when s11000 =>
if std_match(input, "---------------101") then next_state <= s00000; output <= "0000000100100000001";
elsif std_match(input, "----0----------111") then next_state <= s00000; output <= "0000000100100000000";
elsif std_match(input, "----1----------111") then next_state <= s00000; output <= "0000000100100000001";
elsif std_match(input, "----0----------001") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----0----------011") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----1----------0-1") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----1----------1-0") then next_state <= s00001; output <= "0000000100100000001";
elsif std_match(input, "----1----------0-0") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "----0----------110") then next_state <= s11001; output <= "0000000100100000000";
elsif std_match(input, "----0----------010") then next_state <= s11000; output <= "0000000100000000000";
elsif std_match(input, "----0----------000") then next_state <= s00010; output <= "0000000100000000001";
elsif std_match(input, "----0----------100") then next_state <= s00010; output <= "0000000100100000001";
end if;
when s11001 =>
if std_match(input, "----1----------111") then next_state <= s00000; output <= "1000000100000000001";
elsif std_match(input, "----0----------111") then next_state <= s00000; output <= "1000000100000000000";
elsif std_match(input, "----1----------011") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----0----------011") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----0----------110") then next_state <= s11010; output <= "1000000100000000000";
elsif std_match(input, "----0----------010") then next_state <= s11001; output <= "0000000100000000000";
elsif std_match(input, "----1----------110") then next_state <= s00001; output <= "1000000100000000001";
elsif std_match(input, "----1----------010") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "---------------001") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "---------------101") then next_state <= s00000; output <= "1000000100000000001";
elsif std_match(input, "----1----------000") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "----1----------100") then next_state <= s00001; output <= "1000000100000000001";
elsif std_match(input, "----0----------100") then next_state <= s00010; output <= "1000000100000000001";
elsif std_match(input, "----0----------000") then next_state <= s00010; output <= "0000000100000000001";
end if;
when s11010 =>
if std_match(input, "----0-----------01") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----0-----------11") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----1------------1") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----1------------0") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "----0----------110") then next_state <= s11011; output <= "0000000100000000000";
elsif std_match(input, "----0----------010") then next_state <= s11010; output <= "0000000100000000000";
elsif std_match(input, "----0-----------00") then next_state <= s00010; output <= "0000000100000000001";
end if;
when s11011 =>
if std_match(input, "----1-----------11") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----0-0--------111") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----0-1011-----111") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----0-1111-----111") then next_state <= s00000; output <= "0000000100010000000";
elsif std_match(input, "----0-1-01-----111") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----0-1--0-----111") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----0----------011") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----0-0--1-----110") then next_state <= s11011; output <= "0000000100000000000";
elsif std_match(input, "----0-1011-----110") then next_state <= s11011; output <= "0000000100000000000";
elsif std_match(input, "----0-1111-----110") then next_state <= s11100; output <= "0000000100010000000";
elsif std_match(input, "----0-1-01-----110") then next_state <= s11011; output <= "0000000100000000000";
elsif std_match(input, "----0----0-----110") then next_state <= s11011; output <= "0000000100000000000";
elsif std_match(input, "----0----------010") then next_state <= s11011; output <= "0000000100000000000";
elsif std_match(input, "----1-----------10") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "----0-----------01") then next_state <= s00000; output <= "0000000100010000000";
elsif std_match(input, "----1-----------01") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----1-----------00") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "----0-----------00") then next_state <= s01100; output <= "0000000100010000000";
end if;
when s11100 =>
if std_match(input, "----0------------1") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----1------------1") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----0-----------10") then next_state <= s11100; output <= "0000000100000000000";
elsif std_match(input, "----1-----------10") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "----0-----------00") then next_state <= s01100; output <= "0000000100000000000";
elsif std_match(input, "----1-----------00") then next_state <= s00001; output <= "0000000100000000001";
end if;
when s00011 =>
if std_match(input, "----1----------1-1") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----0----------111") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----0----------101") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----1----------1-0") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "----0----------110") then next_state <= s00100; output <= "0000000100000000000";
elsif std_match(input, "----0----------100") then next_state <= s00010; output <= "0000000100000000001";
elsif std_match(input, "----0----------011") then next_state <= s00000; output <= "0000000100000000000";
elsif std_match(input, "----1----------011") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----1----------010") then next_state <= s00001; output <= "0000000100000000001";
elsif std_match(input, "----0----------010") then next_state <= s00011; output <= "0000000100000000000";
elsif std_match(input, "---------------001") then next_state <= s00000; output <= "0000000100000000001";
elsif std_match(input, "----0----------000") then next_state <= s00010; output <= "0000000100000000001";
elsif std_match(input, "----1----------000") then next_state <= s00001; output <= "0000000100000000001";
end if;
when s10001 =>
if std_match(input, "-----------------1") then next_state <= s00000; output <= "0000000000000000000";
elsif std_match(input, "----------------00") then next_state <= s00000; output <= "0000000000000000000";
elsif std_match(input, "----------------10") then next_state <= s10001; output <= "0000000000000000000";
end if;
when others => next_state <= "-----"; output <= "-------------------";
end case;
end process;
end behaviour;
|
agpl-3.0
|
chastell/art-decomp
|
kiss/mc_nov.vhd
|
1
|
1790
|
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity mc_nov is
port(
clock: in std_logic;
input: in std_logic_vector(2 downto 0);
output: out std_logic_vector(4 downto 0)
);
end mc_nov;
architecture behaviour of mc_nov is
constant HG: std_logic_vector(1 downto 0) := "00";
constant HY: std_logic_vector(1 downto 0) := "11";
constant FG: std_logic_vector(1 downto 0) := "01";
constant FY: std_logic_vector(1 downto 0) := "10";
signal current_state, next_state: std_logic_vector(1 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "--"; output <= "-----";
case current_state is
when HG =>
if std_match(input, "0--") then next_state <= HG; output <= "00010";
elsif std_match(input, "-0-") then next_state <= HG; output <= "00010";
elsif std_match(input, "11-") then next_state <= HY; output <= "10010";
end if;
when HY =>
if std_match(input, "--0") then next_state <= HY; output <= "00110";
elsif std_match(input, "--1") then next_state <= FG; output <= "10110";
end if;
when FG =>
if std_match(input, "10-") then next_state <= FG; output <= "01000";
elsif std_match(input, "0--") then next_state <= FY; output <= "11000";
elsif std_match(input, "-1-") then next_state <= FY; output <= "11000";
end if;
when FY =>
if std_match(input, "--0") then next_state <= FY; output <= "01001";
elsif std_match(input, "--1") then next_state <= HG; output <= "11001";
end if;
when others => next_state <= "--"; output <= "-----";
end case;
end process;
end behaviour;
|
agpl-3.0
|
chastell/art-decomp
|
kiss/tma_nov.vhd
|
1
|
6129
|
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity tma_nov is
port(
clock: in std_logic;
input: in std_logic_vector(6 downto 0);
output: out std_logic_vector(5 downto 0)
);
end tma_nov;
architecture behaviour of tma_nov is
constant I0: std_logic_vector(4 downto 0) := "11110";
constant T1: std_logic_vector(4 downto 0) := "00000";
constant T3: std_logic_vector(4 downto 0) := "00001";
constant T4: std_logic_vector(4 downto 0) := "01101";
constant T5: std_logic_vector(4 downto 0) := "00101";
constant T6: std_logic_vector(4 downto 0) := "11010";
constant T7: std_logic_vector(4 downto 0) := "11111";
constant T8: std_logic_vector(4 downto 0) := "11100";
constant T9: std_logic_vector(4 downto 0) := "10011";
constant T2: std_logic_vector(4 downto 0) := "10100";
constant R1: std_logic_vector(4 downto 0) := "00100";
constant R2: std_logic_vector(4 downto 0) := "01011";
constant R3: std_logic_vector(4 downto 0) := "00011";
constant R4: std_logic_vector(4 downto 0) := "00010";
constant R6: std_logic_vector(4 downto 0) := "00111";
constant R7: std_logic_vector(4 downto 0) := "11011";
constant R8: std_logic_vector(4 downto 0) := "11000";
constant R5: std_logic_vector(4 downto 0) := "00110";
constant I2: std_logic_vector(4 downto 0) := "01000";
constant I1: std_logic_vector(4 downto 0) := "01001";
signal current_state, next_state: std_logic_vector(4 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "-----"; output <= "------";
case current_state is
when I0 =>
if std_match(input, "11110--") then next_state <= T1; output <= "000000";
elsif std_match(input, "101-1--") then next_state <= R1; output <= "000000";
end if;
when T1 =>
if std_match(input, "1110---") then next_state <= T3; output <= "100000";
elsif std_match(input, "100----") then next_state <= T9; output <= "100000";
elsif std_match(input, "101--1-") then next_state <= T9; output <= "100000";
end if;
when T3 =>
if std_match(input, "111----") then next_state <= T4; output <= "110000";
elsif std_match(input, "100----") then next_state <= T9; output <= "110000";
elsif std_match(input, "101--1-") then next_state <= T9; output <= "110000";
end if;
when T4 =>
if std_match(input, "111----") then next_state <= T5; output <= "001000";
elsif std_match(input, "100----") then next_state <= T9; output <= "001000";
elsif std_match(input, "101--1-") then next_state <= T9; output <= "001000";
end if;
when T5 =>
if std_match(input, "111-0--") then next_state <= T6; output <= "101000";
elsif std_match(input, "100----") then next_state <= T9; output <= "101000";
elsif std_match(input, "101-1--") then next_state <= T9; output <= "101000";
end if;
when T6 =>
if std_match(input, "101-0--") then next_state <= T7; output <= "011000";
elsif std_match(input, "101-1--") then next_state <= T8; output <= "011000";
elsif std_match(input, "100----") then next_state <= T9; output <= "011000";
end if;
when T7 =>
if std_match(input, "10-----") then next_state <= I2; output <= "111000";
end if;
when T8 =>
if std_match(input, "10-----") then next_state <= I2; output <= "000100";
end if;
when T9 =>
if std_match(input, "101-0--") then next_state <= T2; output <= "100100";
elsif std_match(input, "100----") then next_state <= T2; output <= "100100";
end if;
when T2 =>
if std_match(input, "10-----") then next_state <= T8; output <= "010100";
end if;
when R1 =>
if std_match(input, "101-1--") then next_state <= R2; output <= "100010";
elsif std_match(input, "100----") then next_state <= I1; output <= "100010";
elsif std_match(input, "101-0--") then next_state <= I2; output <= "100010";
end if;
when R2 =>
if std_match(input, "101-1--") then next_state <= R3; output <= "010010";
elsif std_match(input, "100----") then next_state <= I1; output <= "010010";
elsif std_match(input, "101-0--") then next_state <= I2; output <= "010010";
end if;
when R3 =>
if std_match(input, "101-1--") then next_state <= R4; output <= "110010";
elsif std_match(input, "101-0-0") then next_state <= R6; output <= "110010";
elsif std_match(input, "101-0-1") then next_state <= R8; output <= "110010";
elsif std_match(input, "100----") then next_state <= R5; output <= "110010";
end if;
when R4 =>
if std_match(input, "101-0-0") then next_state <= R6; output <= "001010";
elsif std_match(input, "101-0-1") then next_state <= R8; output <= "001010";
elsif std_match(input, "100----") then next_state <= R5; output <= "001010";
end if;
when R6 =>
if std_match(input, "101-0--") then next_state <= R7; output <= "011010";
elsif std_match(input, "101-1--") then next_state <= R5; output <= "011010";
elsif std_match(input, "100----") then next_state <= R5; output <= "011010";
end if;
when R7 =>
if std_match(input, "10-----") then next_state <= I2; output <= "111010";
end if;
when R8 =>
if std_match(input, "10-----") then next_state <= R5; output <= "000110";
end if;
when R5 =>
if std_match(input, "101----") then next_state <= I2; output <= "100110";
elsif std_match(input, "100----") then next_state <= I1; output <= "100110";
end if;
when I2 =>
if std_match(input, "-------") then next_state <= I0; output <= "000001";
end if;
when I1 =>
if std_match(input, "111-0--") then next_state <= I0; output <= "010111";
end if;
when others => next_state <= "-----"; output <= "------";
end case;
end process;
end behaviour;
|
agpl-3.0
|
chastell/art-decomp
|
kiss/s1494_rnd.vhd
|
1
|
31360
|
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity s1494_rnd is
port(
clock: in std_logic;
input: in std_logic_vector(7 downto 0);
output: out std_logic_vector(18 downto 0)
);
end s1494_rnd;
architecture behaviour of s1494_rnd is
constant s000000: std_logic_vector(5 downto 0) := "111101";
constant s001110: std_logic_vector(5 downto 0) := "000010";
constant s011000: std_logic_vector(5 downto 0) := "011011";
constant s010000: std_logic_vector(5 downto 0) := "111110";
constant s010100: std_logic_vector(5 downto 0) := "111111";
constant s110011: std_logic_vector(5 downto 0) := "010001";
constant s010011: std_logic_vector(5 downto 0) := "010110";
constant s000100: std_logic_vector(5 downto 0) := "001011";
constant s010111: std_logic_vector(5 downto 0) := "001111";
constant s010110: std_logic_vector(5 downto 0) := "011110";
constant s100011: std_logic_vector(5 downto 0) := "101011";
constant s001100: std_logic_vector(5 downto 0) := "100001";
constant s011011: std_logic_vector(5 downto 0) := "110000";
constant s010001: std_logic_vector(5 downto 0) := "101111";
constant s100110: std_logic_vector(5 downto 0) := "011010";
constant s011101: std_logic_vector(5 downto 0) := "111000";
constant s101110: std_logic_vector(5 downto 0) := "110110";
constant s010101: std_logic_vector(5 downto 0) := "001000";
constant s111110: std_logic_vector(5 downto 0) := "000001";
constant s000011: std_logic_vector(5 downto 0) := "100100";
constant s111011: std_logic_vector(5 downto 0) := "001001";
constant s011010: std_logic_vector(5 downto 0) := "101001";
constant s111010: std_logic_vector(5 downto 0) := "100110";
constant s100111: std_logic_vector(5 downto 0) := "111011";
constant s110010: std_logic_vector(5 downto 0) := "011100";
constant s100000: std_logic_vector(5 downto 0) := "100011";
constant s011100: std_logic_vector(5 downto 0) := "100010";
constant s101010: std_logic_vector(5 downto 0) := "011000";
constant s100010: std_logic_vector(5 downto 0) := "000011";
constant s101000: std_logic_vector(5 downto 0) := "110111";
constant s011110: std_logic_vector(5 downto 0) := "010011";
constant s110000: std_logic_vector(5 downto 0) := "110010";
constant s010010: std_logic_vector(5 downto 0) := "000111";
constant s001010: std_logic_vector(5 downto 0) := "001100";
constant s100100: std_logic_vector(5 downto 0) := "110101";
constant s111000: std_logic_vector(5 downto 0) := "010100";
constant s001011: std_logic_vector(5 downto 0) := "000000";
constant s110100: std_logic_vector(5 downto 0) := "100111";
constant s001000: std_logic_vector(5 downto 0) := "011101";
constant s000010: std_logic_vector(5 downto 0) := "101101";
constant s000111: std_logic_vector(5 downto 0) := "100101";
constant s101011: std_logic_vector(5 downto 0) := "100000";
constant s001111: std_logic_vector(5 downto 0) := "111100";
constant s000110: std_logic_vector(5 downto 0) := "000100";
constant s110110: std_logic_vector(5 downto 0) := "110011";
constant s011111: std_logic_vector(5 downto 0) := "010111";
constant s111100: std_logic_vector(5 downto 0) := "111010";
constant s101100: std_logic_vector(5 downto 0) := "111001";
signal current_state, next_state: std_logic_vector(5 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "------"; output <= "-------------------";
case current_state is
when s000000 =>
if std_match(input, "0-01----") then next_state <= s000000; output <= "1000000001000000001";
elsif std_match(input, "0-00----") then next_state <= s000000; output <= "1000000000100000001";
elsif std_match(input, "0-10----") then next_state <= s000000; output <= "0000000000000000000";
elsif std_match(input, "0-11----") then next_state <= s000000; output <= "0001001100111110001";
elsif std_match(input, "1-01----") then next_state <= s000000; output <= "1000000001000000001";
elsif std_match(input, "1-00----") then next_state <= s000000; output <= "1000000000100000001";
elsif std_match(input, "1-11----") then next_state <= s001110; output <= "0001001100111110001";
elsif std_match(input, "1-10----") then next_state <= s000000; output <= "0000000000000000000";
end if;
when s001110 =>
if std_match(input, "1---0---") then next_state <= s011000; output <= "0000000000100100101";
elsif std_match(input, "11--1---") then next_state <= s010000; output <= "1000010010100000101";
elsif std_match(input, "10--1---") then next_state <= s011000; output <= "0000000000100100101";
elsif std_match(input, "00------") then next_state <= s000000; output <= "0000000000100100101";
elsif std_match(input, "01--1---") then next_state <= s000000; output <= "1000010010100000101";
elsif std_match(input, "01--0---") then next_state <= s000000; output <= "0000000000100100101";
end if;
when s011000 =>
if std_match(input, "0-00-000") then next_state <= s000000; output <= "1000000000110000110";
elsif std_match(input, "0-00-010") then next_state <= s000000; output <= "1000000000100000110";
elsif std_match(input, "0-00-110") then next_state <= s000000; output <= "1000000100100000110";
elsif std_match(input, "0-00-100") then next_state <= s000000; output <= "1000000100110000110";
elsif std_match(input, "0-01-100") then next_state <= s000000; output <= "1000001101010000110";
elsif std_match(input, "0-01-110") then next_state <= s000000; output <= "1000001101000000110";
elsif std_match(input, "0-01-010") then next_state <= s000000; output <= "1000001001000000110";
elsif std_match(input, "0-01-000") then next_state <= s000000; output <= "1000001001010000110";
elsif std_match(input, "0-0---01") then next_state <= s000000; output <= "0100000000111111100";
elsif std_match(input, "0-0---11") then next_state <= s000000; output <= "0100000000101111100";
elsif std_match(input, "0-10-000") then next_state <= s000000; output <= "0000001000010000000";
elsif std_match(input, "0-10-010") then next_state <= s000000; output <= "0000001000000000000";
elsif std_match(input, "0-11-0-0") then next_state <= s000000; output <= "0000001000110110110";
elsif std_match(input, "0-10-110") then next_state <= s000000; output <= "0000001100000000000";
elsif std_match(input, "0-10-100") then next_state <= s000000; output <= "0000001100010000000";
elsif std_match(input, "0-11-1-0") then next_state <= s000000; output <= "0000001100110110110";
elsif std_match(input, "0-1---01") then next_state <= s000000; output <= "0100000000111111100";
elsif std_match(input, "0-1---11") then next_state <= s000000; output <= "0100000000101111100";
elsif std_match(input, "1--1--01") then next_state <= s010100; output <= "0100000000111111100";
elsif std_match(input, "1--1--11") then next_state <= s010100; output <= "0100000000101111100";
elsif std_match(input, "1-11-0-0") then next_state <= s110011; output <= "0000001000110110110";
elsif std_match(input, "1-11-1-0") then next_state <= s110011; output <= "0000001100110110110";
elsif std_match(input, "1-01-110") then next_state <= s010100; output <= "1000001101000000110";
elsif std_match(input, "1-01-100") then next_state <= s010100; output <= "1000001101010000110";
elsif std_match(input, "1-01-010") then next_state <= s010100; output <= "1000001001000000110";
elsif std_match(input, "1-01-000") then next_state <= s010100; output <= "1000001001010000110";
elsif std_match(input, "1--0--11") then next_state <= s010100; output <= "0100000000101111100";
elsif std_match(input, "1--0--01") then next_state <= s010100; output <= "0100000000111111100";
elsif std_match(input, "1-10-100") then next_state <= s010100; output <= "0000001100010000000";
elsif std_match(input, "1-10-110") then next_state <= s010100; output <= "0000001100000000000";
elsif std_match(input, "1-10-000") then next_state <= s010100; output <= "0000001000010000000";
elsif std_match(input, "1-10-010") then next_state <= s010100; output <= "0000001000000000000";
elsif std_match(input, "1-00-110") then next_state <= s010100; output <= "1000000100100000110";
elsif std_match(input, "1-00-100") then next_state <= s010100; output <= "1000000100110000110";
elsif std_match(input, "1-00-000") then next_state <= s010100; output <= "1000000000110000110";
elsif std_match(input, "1-00-010") then next_state <= s010100; output <= "1000000000100000110";
end if;
when s010100 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
elsif std_match(input, "1-------") then next_state <= s010011; output <= "0000000000100100101";
end if;
when s010011 =>
if std_match(input, "0----0--") then next_state <= s000000; output <= "1000000000111100001";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "1000000100111100001";
elsif std_match(input, "1----1--") then next_state <= s000100; output <= "1000000100111100001";
elsif std_match(input, "1----0--") then next_state <= s000100; output <= "1000000000111100001";
end if;
when s000100 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
elsif std_match(input, "10---11-") then next_state <= s010111; output <= "0000000000100100101";
elsif std_match(input, "11--011-") then next_state <= s010111; output <= "0000000000100100101";
elsif std_match(input, "11--111-") then next_state <= s010110; output <= "0000000000100100101";
elsif std_match(input, "11---01-") then next_state <= s100011; output <= "0000000000100100101";
elsif std_match(input, "10---01-") then next_state <= s010111; output <= "0000000000100100101";
elsif std_match(input, "1-----0-") then next_state <= s010111; output <= "0000000000100100101";
end if;
when s010111 =>
if std_match(input, "0----1--") then next_state <= s000000; output <= "0000000100101011000";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "0000000000101011000";
elsif std_match(input, "1----0--") then next_state <= s001100; output <= "0000000000101011000";
elsif std_match(input, "1----1--") then next_state <= s001100; output <= "0000000100101011000";
end if;
when s001100 =>
if std_match(input, "1----1--") then next_state <= s011011; output <= "0000000000100100101";
elsif std_match(input, "1----0--") then next_state <= s010001; output <= "0000000000100100101";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
end if;
when s011011 =>
if std_match(input, "0----11-") then next_state <= s000000; output <= "0000000100101110100";
elsif std_match(input, "0----10-") then next_state <= s000000; output <= "0000000100111110100";
elsif std_match(input, "0----01-") then next_state <= s000000; output <= "0000000000101110100";
elsif std_match(input, "0----00-") then next_state <= s000000; output <= "0000000000111110100";
elsif std_match(input, "1----11-") then next_state <= s100110; output <= "0000000100101110100";
elsif std_match(input, "1----10-") then next_state <= s100110; output <= "0000000100111110100";
elsif std_match(input, "1----01-") then next_state <= s100110; output <= "0000000000101110100";
elsif std_match(input, "1----00-") then next_state <= s100110; output <= "0000000000111110100";
end if;
when s100110 =>
if std_match(input, "1-------") then next_state <= s011101; output <= "0000000000100100101";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
end if;
when s011101 =>
if std_match(input, "0----01-") then next_state <= s000000; output <= "0000000000110011010";
elsif std_match(input, "0----00-") then next_state <= s000000; output <= "0000000000100011010";
elsif std_match(input, "0----10-") then next_state <= s000000; output <= "0000000100100011010";
elsif std_match(input, "0----11-") then next_state <= s000000; output <= "0000000100110011010";
elsif std_match(input, "1----11-") then next_state <= s101110; output <= "0000000100110011010";
elsif std_match(input, "1----10-") then next_state <= s101110; output <= "0000000100100011010";
elsif std_match(input, "1----01-") then next_state <= s101110; output <= "0000000000110011010";
elsif std_match(input, "1----00-") then next_state <= s101110; output <= "0000000000100011010";
end if;
when s101110 =>
if std_match(input, "1-------") then next_state <= s010101; output <= "0000000000100100101";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
end if;
when s010101 =>
if std_match(input, "1----0--") then next_state <= s111110; output <= "1000000000110100110";
elsif std_match(input, "1----1--") then next_state <= s111110; output <= "1000000100110100110";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "1000000000110100110";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "1000000100110100110";
end if;
when s111110 =>
if std_match(input, "01----0-") then next_state <= s000000; output <= "0000000000100100101";
elsif std_match(input, "00--1-0-") then next_state <= s000000; output <= "0000100000100100101";
elsif std_match(input, "00--0-0-") then next_state <= s000000; output <= "0000000000100100101";
elsif std_match(input, "11----01") then next_state <= s000011; output <= "0000000000100100101";
elsif std_match(input, "11--0-00") then next_state <= s000011; output <= "0000000000100100101";
elsif std_match(input, "11--1-00") then next_state <= s111011; output <= "0000000000100100101";
elsif std_match(input, "10--0-0-") then next_state <= s000011; output <= "0000000000100100101";
elsif std_match(input, "10--1-00") then next_state <= s011010; output <= "0000100000100100101";
elsif std_match(input, "10--1-01") then next_state <= s111010; output <= "0000100000100100101";
elsif std_match(input, "0---1-1-") then next_state <= s000000; output <= "0000100000100100101";
elsif std_match(input, "0---0-1-") then next_state <= s000000; output <= "0000000000100100101";
elsif std_match(input, "1---0-1-") then next_state <= s000011; output <= "0000000000100100101";
elsif std_match(input, "1---1-10") then next_state <= s011010; output <= "0000100000100100101";
elsif std_match(input, "1---1-11") then next_state <= s111010; output <= "0000100000100100101";
end if;
when s000011 =>
if std_match(input, "0----0-1") then next_state <= s000000; output <= "0000000000111110001";
elsif std_match(input, "0----1-1") then next_state <= s000000; output <= "0000000100111110001";
elsif std_match(input, "0----0-0") then next_state <= s000000; output <= "1000000000111110001";
elsif std_match(input, "0----1-0") then next_state <= s000000; output <= "0000000100111110001";
elsif std_match(input, "1----0-1") then next_state <= s001110; output <= "0000000000111110001";
elsif std_match(input, "1----1-1") then next_state <= s001110; output <= "0000000100111110001";
elsif std_match(input, "1----0-0") then next_state <= s001110; output <= "1000000000111110001";
elsif std_match(input, "1----1-0") then next_state <= s001110; output <= "0000000100111110001";
end if;
when s111011 =>
if std_match(input, "1----0--") then next_state <= s100111; output <= "1000000000111110001";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "1000000000111110001";
elsif std_match(input, "1----1--") then next_state <= s010000; output <= "0000010110111110001";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0000010110111110001";
end if;
when s100111 =>
if std_match(input, "1-------") then next_state <= s111011; output <= "0000000000100100101";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
end if;
when s010000 =>
if std_match(input, "--------") then next_state <= s000000; output <= "0000000000101110100";
end if;
when s011010 =>
if std_match(input, "1----01-") then next_state <= s110010; output <= "0000000000100101001";
elsif std_match(input, "1----00-") then next_state <= s110010; output <= "0000000000110101001";
elsif std_match(input, "1----1--") then next_state <= s100000; output <= "0000000100111110001";
elsif std_match(input, "0----01-") then next_state <= s000000; output <= "0000000000100101001";
elsif std_match(input, "0----00-") then next_state <= s000000; output <= "0000000000110101001";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0000000100111110001";
end if;
when s110010 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
elsif std_match(input, "1----00-") then next_state <= s011100; output <= "0000000000100100101";
elsif std_match(input, "1----01-") then next_state <= s011010; output <= "0000000000100100101";
elsif std_match(input, "1----11-") then next_state <= s011100; output <= "0000000000100100101";
elsif std_match(input, "1----10-") then next_state <= s011010; output <= "0000000000100100101";
end if;
when s011100 =>
if std_match(input, "1----10-") then next_state <= s101010; output <= "0000000100101111100";
elsif std_match(input, "1----11-") then next_state <= s101010; output <= "0000000100111111100";
elsif std_match(input, "1----00-") then next_state <= s100010; output <= "0000000000101111100";
elsif std_match(input, "1----01-") then next_state <= s100010; output <= "0000000000111111100";
elsif std_match(input, "0----10-") then next_state <= s000000; output <= "0000000100101111100";
elsif std_match(input, "0----11-") then next_state <= s000000; output <= "0000000100111111100";
elsif std_match(input, "0----00-") then next_state <= s000000; output <= "0000000000101111100";
elsif std_match(input, "0----01-") then next_state <= s000000; output <= "0000000000111111100";
end if;
when s101010 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
elsif std_match(input, "1-------") then next_state <= s111010; output <= "0000000000100100101";
end if;
when s111010 =>
if std_match(input, "1-------") then next_state <= s100000; output <= "0000000000111110001";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000000000111110001";
end if;
when s100000 =>
if std_match(input, "11------") then next_state <= s101000; output <= "0100000000100100101";
elsif std_match(input, "01------") then next_state <= s000000; output <= "0100000000100100101";
elsif std_match(input, "00--0---") then next_state <= s000000; output <= "0000000000100100101";
elsif std_match(input, "00--1---") then next_state <= s000000; output <= "0000010000100100101";
elsif std_match(input, "10--0---") then next_state <= s011110; output <= "0000000000100100101";
elsif std_match(input, "10--1---") then next_state <= s110000; output <= "0000010000100100101";
end if;
when s101000 =>
if std_match(input, "1-------") then next_state <= s010010; output <= "1000000000111100001";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "1000000000111100001";
end if;
when s010010 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
elsif std_match(input, "1---1---") then next_state <= s001010; output <= "0000000000100100101";
elsif std_match(input, "1---0---") then next_state <= s011110; output <= "0000000000100100101";
end if;
when s001010 =>
if std_match(input, "1----1--") then next_state <= s100100; output <= "0000000100110110110";
elsif std_match(input, "1----0--") then next_state <= s111000; output <= "0000000000110101001";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0000000100110110110";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "0000000000110101001";
end if;
when s100100 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0010000000100100101";
elsif std_match(input, "1-------") then next_state <= s001011; output <= "0010000000100100101";
end if;
when s001011 =>
if std_match(input, "0----0--") then next_state <= s000000; output <= "0000000000101110110";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0000000100101110110";
elsif std_match(input, "1----0--") then next_state <= s110100; output <= "0000000000101110110";
elsif std_match(input, "1----1--") then next_state <= s110100; output <= "0000000100101110110";
end if;
when s110100 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0010000000100100101";
elsif std_match(input, "1-------") then next_state <= s011011; output <= "0010000000100100101";
end if;
when s111000 =>
if std_match(input, "1----0--") then next_state <= s001000; output <= "0000000000100100101";
elsif std_match(input, "1---11--") then next_state <= s001000; output <= "0000000000100100101";
elsif std_match(input, "1---01--") then next_state <= s001010; output <= "0000000000100100101";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
end if;
when s001000 =>
if std_match(input, "1----1--") then next_state <= s100100; output <= "0000000100110110110";
elsif std_match(input, "1----0--") then next_state <= s100100; output <= "0000000000110110110";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "0000000000110110110";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0000000100110110110";
end if;
when s011110 =>
if std_match(input, "0----1--") then next_state <= s000000; output <= "0000000100111110001";
elsif std_match(input, "0-11-0--") then next_state <= s000000; output <= "0000001000110110110";
elsif std_match(input, "0-10-00-") then next_state <= s000000; output <= "0000001000000000000";
elsif std_match(input, "0-10-01-") then next_state <= s000000; output <= "0000001000010000000";
elsif std_match(input, "0-00-00-") then next_state <= s000000; output <= "1000000000100000110";
elsif std_match(input, "0-00-01-") then next_state <= s000000; output <= "1000000000110000110";
elsif std_match(input, "0-01-01-") then next_state <= s000000; output <= "1000001001010000110";
elsif std_match(input, "0-01-00-") then next_state <= s000000; output <= "1000001001000000110";
elsif std_match(input, "1----1--") then next_state <= s100000; output <= "0000000100111110001";
elsif std_match(input, "1-00-00-") then next_state <= s000010; output <= "1000000000100000110";
elsif std_match(input, "1-00-01-") then next_state <= s000010; output <= "1000000000110000110";
elsif std_match(input, "1-01-01-") then next_state <= s000010; output <= "1000001001010000110";
elsif std_match(input, "1-01-00-") then next_state <= s000010; output <= "1000001001000000110";
elsif std_match(input, "1-11-0--") then next_state <= s110011; output <= "0000001000110110110";
elsif std_match(input, "1-10-00-") then next_state <= s000010; output <= "0000001000000000000";
elsif std_match(input, "1-10-01-") then next_state <= s000010; output <= "0000001000010000000";
end if;
when s000010 =>
if std_match(input, "1----0--") then next_state <= s011110; output <= "0010000000100100101";
elsif std_match(input, "1----1--") then next_state <= s011110; output <= "0000000000100100101";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "0010000000100100101";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0000000000100100101";
end if;
when s110011 =>
if std_match(input, "1-------") then next_state <= s000111; output <= "0000000000100100101";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
end if;
when s000111 =>
if std_match(input, "0----1--") then next_state <= s000000; output <= "0000000100101110110";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "0000000000101110110";
elsif std_match(input, "1----1--") then next_state <= s101011; output <= "0000000100101110110";
elsif std_match(input, "1----0--") then next_state <= s101011; output <= "0000000000101110110";
end if;
when s101011 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
elsif std_match(input, "1-------") then next_state <= s001111; output <= "0000000000100100101";
end if;
when s001111 =>
if std_match(input, "1----1--") then next_state <= s000100; output <= "0010000100111001110";
elsif std_match(input, "1----0--") then next_state <= s000100; output <= "0010000000111001110";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0010000100111001110";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "0010000000111001110";
end if;
when s110000 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "1000000000110100110";
elsif std_match(input, "1-------") then next_state <= s000110; output <= "1000000000110100110";
end if;
when s000110 =>
if std_match(input, "1---01--") then next_state <= s011000; output <= "0001000000100100101";
elsif std_match(input, "1---00--") then next_state <= s011000; output <= "0010000000100100101";
elsif std_match(input, "1---10--") then next_state <= s011110; output <= "0010000000100100101";
elsif std_match(input, "1---11--") then next_state <= s011110; output <= "0001000000100100101";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "0010000000100100101";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0001000000100100101";
end if;
when s100010 =>
if std_match(input, "1-------") then next_state <= s011010; output <= "0000000000100100101";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
end if;
when s010001 =>
if std_match(input, "1----0--") then next_state <= s110110; output <= "1000000000111110100";
elsif std_match(input, "1----1--") then next_state <= s110110; output <= "1000000100111110100";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "1000000100111110100";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "1000000000111110100";
end if;
when s110110 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
elsif std_match(input, "1-------") then next_state <= s011111; output <= "0000000000100100101";
end if;
when s011111 =>
if std_match(input, "0----11-") then next_state <= s000000; output <= "1000000100111011010";
elsif std_match(input, "0----10-") then next_state <= s000000; output <= "1000000100101011010";
elsif std_match(input, "0----00-") then next_state <= s000000; output <= "1000000000101011010";
elsif std_match(input, "0----01-") then next_state <= s000000; output <= "1000000000111011010";
elsif std_match(input, "1----10-") then next_state <= s101110; output <= "1000000100101011010";
elsif std_match(input, "1----11-") then next_state <= s101110; output <= "1000000100111011010";
elsif std_match(input, "1----00-") then next_state <= s101110; output <= "1000000000101011010";
elsif std_match(input, "1----01-") then next_state <= s101110; output <= "1000000000111011010";
end if;
when s010110 =>
if std_match(input, "1----1--") then next_state <= s111100; output <= "0001000100111110001";
elsif std_match(input, "1-00-0--") then next_state <= s101100; output <= "1000000000100000110";
elsif std_match(input, "1-01-0--") then next_state <= s101100; output <= "1000001001000000110";
elsif std_match(input, "1-10-0--") then next_state <= s101100; output <= "0000001000000000000";
elsif std_match(input, "1-11-0--") then next_state <= s110011; output <= "0000001000110110110";
elsif std_match(input, "0-00-0--") then next_state <= s000000; output <= "1000000000100000110";
elsif std_match(input, "0-01-0--") then next_state <= s000000; output <= "1000001001000000110";
elsif std_match(input, "0-0--1--") then next_state <= s000000; output <= "0001000100111110001";
elsif std_match(input, "0-1--1--") then next_state <= s000000; output <= "0001000100111110001";
elsif std_match(input, "0-10-0--") then next_state <= s000000; output <= "0000001000000000000";
elsif std_match(input, "0-11-0--") then next_state <= s000000; output <= "0000001000110110110";
end if;
when s111100 =>
if std_match(input, "1-------") then next_state <= s100011; output <= "0100000000100100101";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0100000000100100101";
end if;
when s100011 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000000000110110110";
elsif std_match(input, "1-------") then next_state <= s110011; output <= "0000000000110110110";
end if;
when s101100 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
elsif std_match(input, "1-------") then next_state <= s010110; output <= "0000000000100100101";
end if;
when others => next_state <= "------"; output <= "-------------------";
end case;
end process;
end behaviour;
|
agpl-3.0
|
chastell/art-decomp
|
kiss/s420_jed.vhd
|
1
|
17549
|
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity s420_jed is
port(
clock: in std_logic;
input: in std_logic_vector(18 downto 0);
output: out std_logic_vector(1 downto 0)
);
end s420_jed;
architecture behaviour of s420_jed is
constant s1111111111111111: std_logic_vector(4 downto 0) := "11000";
constant s0000000000000000: std_logic_vector(4 downto 0) := "00001";
constant s0001000000000000: std_logic_vector(4 downto 0) := "01001";
constant s0010000000000000: std_logic_vector(4 downto 0) := "11001";
constant s0011000000000000: std_logic_vector(4 downto 0) := "01101";
constant s0100000000000000: std_logic_vector(4 downto 0) := "10000";
constant s0101000000000000: std_logic_vector(4 downto 0) := "10001";
constant s0110000000000000: std_logic_vector(4 downto 0) := "10101";
constant s0111000000000000: std_logic_vector(4 downto 0) := "01111";
constant s1000000000000000: std_logic_vector(4 downto 0) := "00010";
constant s1001000000000000: std_logic_vector(4 downto 0) := "00011";
constant s1010000000000000: std_logic_vector(4 downto 0) := "01000";
constant s1011000000000000: std_logic_vector(4 downto 0) := "00111";
constant s1100000000000000: std_logic_vector(4 downto 0) := "00000";
constant s1101000000000000: std_logic_vector(4 downto 0) := "10011";
constant s1110000000000000: std_logic_vector(4 downto 0) := "00100";
constant s1111000000000000: std_logic_vector(4 downto 0) := "01011";
constant s0000000100000000: std_logic_vector(4 downto 0) := "00101";
signal current_state, next_state: std_logic_vector(4 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "-----"; output <= "--";
case current_state is
when s1111111111111111 =>
if std_match(input, "1----------------1-") then next_state <= s0000000000000000; output <= "11";
elsif std_match(input, "1----------------00") then next_state <= s0000000000000000; output <= "10";
elsif std_match(input, "1----------------01") then next_state <= s0000000000000000; output <= "11";
elsif std_match(input, "0------------------") then next_state <= s0000000000000000; output <= "10";
end if;
when s0000000000000000 =>
if std_match(input, "10----------------1") then next_state <= s0001000000000000; output <= "01";
elsif std_match(input, "10----------------0") then next_state <= s0001000000000000; output <= "00";
elsif std_match(input, "00-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "01----------------1") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11----------------1") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "-1----------------0") then next_state <= s0000000000000000; output <= "00";
end if;
when s0001000000000000 =>
if std_match(input, "0------------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11---------------1-") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11---------------00") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11---------------01") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "10---------------00") then next_state <= s0010000000000000; output <= "00";
elsif std_match(input, "10---------------10") then next_state <= s0010000000000000; output <= "01";
elsif std_match(input, "10----------------1") then next_state <= s0010000000000000; output <= "01";
end if;
when s0010000000000000 =>
if std_match(input, "00-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "10--------------0-0") then next_state <= s0011000000000000; output <= "00";
elsif std_match(input, "10--------------1-0") then next_state <= s0011000000000000; output <= "01";
elsif std_match(input, "10----------------1") then next_state <= s0011000000000000; output <= "01";
elsif std_match(input, "01-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11--------------0-0") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11--------------1-0") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11----------------1") then next_state <= s0000000000000000; output <= "01";
end if;
when s0011000000000000 =>
if std_match(input, "0------------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11---------------10") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11---------------00") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11----------------1") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "10---------------1-") then next_state <= s0100000000000000; output <= "01";
elsif std_match(input, "10---------------01") then next_state <= s0100000000000000; output <= "01";
elsif std_match(input, "10---------------00") then next_state <= s0100000000000000; output <= "00";
end if;
when s0100000000000000 =>
if std_match(input, "10----------------1") then next_state <= s0101000000000000; output <= "01";
elsif std_match(input, "10-------------0--0") then next_state <= s0101000000000000; output <= "00";
elsif std_match(input, "10-------------1--0") then next_state <= s0101000000000000; output <= "01";
elsif std_match(input, "00-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "01-------------0--1") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11-------------0--1") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "-1-------------0--0") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "01-------------1---") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11-------------1---") then next_state <= s0000000000000000; output <= "01";
end if;
when s0101000000000000 =>
if std_match(input, "0------------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11---------------10") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11---------------00") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11----------------1") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "10---------------10") then next_state <= s0110000000000000; output <= "01";
elsif std_match(input, "10---------------00") then next_state <= s0110000000000000; output <= "00";
elsif std_match(input, "10----------------1") then next_state <= s0110000000000000; output <= "01";
end if;
when s0110000000000000 =>
if std_match(input, "0------------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11--------------1-0") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11--------------0-0") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11----------------1") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "10--------------1--") then next_state <= s0111000000000000; output <= "01";
elsif std_match(input, "10--------------0-0") then next_state <= s0111000000000000; output <= "00";
elsif std_match(input, "10--------------0-1") then next_state <= s0111000000000000; output <= "01";
end if;
when s0111000000000000 =>
if std_match(input, "0------------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11---------------1-") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11---------------00") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11---------------01") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "10---------------1-") then next_state <= s1000000000000000; output <= "01";
elsif std_match(input, "10---------------01") then next_state <= s1000000000000000; output <= "01";
elsif std_match(input, "10---------------00") then next_state <= s1000000000000000; output <= "00";
end if;
when s1000000000000000 =>
if std_match(input, "00-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "10----------------1") then next_state <= s1001000000000000; output <= "01";
elsif std_match(input, "10------------1---0") then next_state <= s1001000000000000; output <= "01";
elsif std_match(input, "10------------0---0") then next_state <= s1001000000000000; output <= "00";
elsif std_match(input, "01------------0---1") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11------------0---1") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11------------1---1") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "01------------1---1") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11------------1---0") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11------------0---0") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "01----------------0") then next_state <= s0000000000000000; output <= "00";
end if;
when s1001000000000000 =>
if std_match(input, "00-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "10---------------1-") then next_state <= s1010000000000000; output <= "01";
elsif std_match(input, "10---------------00") then next_state <= s1010000000000000; output <= "00";
elsif std_match(input, "10---------------01") then next_state <= s1010000000000000; output <= "01";
elsif std_match(input, "01-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11---------------1-") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11---------------01") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11---------------00") then next_state <= s0000000000000000; output <= "00";
end if;
when s1010000000000000 =>
if std_match(input, "00-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "10--------------1--") then next_state <= s1011000000000000; output <= "01";
elsif std_match(input, "10--------------0-1") then next_state <= s1011000000000000; output <= "01";
elsif std_match(input, "10--------------0-0") then next_state <= s1011000000000000; output <= "00";
elsif std_match(input, "01-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11--------------1-0") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11--------------0-0") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11----------------1") then next_state <= s0000000000000000; output <= "01";
end if;
when s1011000000000000 =>
if std_match(input, "00-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "10---------------00") then next_state <= s1100000000000000; output <= "00";
elsif std_match(input, "10---------------10") then next_state <= s1100000000000000; output <= "01";
elsif std_match(input, "10----------------1") then next_state <= s1100000000000000; output <= "01";
elsif std_match(input, "01-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11---------------10") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11---------------00") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11----------------1") then next_state <= s0000000000000000; output <= "01";
end if;
when s1100000000000000 =>
if std_match(input, "00-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "10-------------0--1") then next_state <= s1101000000000000; output <= "01";
elsif std_match(input, "10-------------0--0") then next_state <= s1101000000000000; output <= "00";
elsif std_match(input, "10-------------1---") then next_state <= s1101000000000000; output <= "01";
elsif std_match(input, "11----------------1") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "01----------------1") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11-------------0--0") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11-------------1--0") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "01----------------0") then next_state <= s0000000000000000; output <= "00";
end if;
when s1101000000000000 =>
if std_match(input, "0------------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "10---------------1-") then next_state <= s1110000000000000; output <= "01";
elsif std_match(input, "10---------------00") then next_state <= s1110000000000000; output <= "00";
elsif std_match(input, "10---------------01") then next_state <= s1110000000000000; output <= "01";
elsif std_match(input, "11---------------1-") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11---------------00") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11---------------01") then next_state <= s0000000000000000; output <= "01";
end if;
when s1110000000000000 =>
if std_match(input, "10--------------1--") then next_state <= s1111000000000000; output <= "01";
elsif std_match(input, "10--------------0-0") then next_state <= s1111000000000000; output <= "00";
elsif std_match(input, "10--------------0-1") then next_state <= s1111000000000000; output <= "01";
elsif std_match(input, "00-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "01-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11--------------1--") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11--------------0-0") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11--------------0-1") then next_state <= s0000000000000000; output <= "01";
end if;
when s1111000000000000 =>
if std_match(input, "01-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11---------------00") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11---------------10") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11----------------1") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "00-----------------") then next_state <= s0000000100000000; output <= "00";
elsif std_match(input, "10---------------10") then next_state <= s0000000100000000; output <= "01";
elsif std_match(input, "10---------------00") then next_state <= s0000000100000000; output <= "00";
elsif std_match(input, "10----------------1") then next_state <= s0000000100000000; output <= "01";
end if;
when s0000000100000000 =>
if std_match(input, "00-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "10-----------1-----") then next_state <= s0001000000000000; output <= "01";
elsif std_match(input, "10-----------0----0") then next_state <= s0001000000000000; output <= "00";
elsif std_match(input, "10-----------0----1") then next_state <= s0001000000000000; output <= "01";
elsif std_match(input, "01-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11-----------1----0") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11-----------0----0") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11----------------1") then next_state <= s0000000000000000; output <= "01";
end if;
when others => next_state <= "-----"; output <= "--";
end case;
end process;
end behaviour;
|
agpl-3.0
|
chastell/art-decomp
|
kiss/scf_hot.vhd
|
1
|
53522
|
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity scf_hot is
port(
clock: in std_logic;
input: in std_logic_vector(26 downto 0);
output: out std_logic_vector(55 downto 0)
);
end scf_hot;
architecture behaviour of scf_hot is
constant state1: std_logic_vector(120 downto 0) := "1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant state3: std_logic_vector(120 downto 0) := "0100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant state2: std_logic_vector(120 downto 0) := "0010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant state4: std_logic_vector(120 downto 0) := "0001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant state5: std_logic_vector(120 downto 0) := "0000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant state7: std_logic_vector(120 downto 0) := "0000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant state6: std_logic_vector(120 downto 0) := "0000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant state9: std_logic_vector(120 downto 0) := "0000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant state8: std_logic_vector(120 downto 0) := "0000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant state17: std_logic_vector(120 downto 0) := "0000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant state12: std_logic_vector(120 downto 0) := "0000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant state10: std_logic_vector(120 downto 0) := "0000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant state11: std_logic_vector(120 downto 0) := "0000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant state15: std_logic_vector(120 downto 0) := "0000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant state13: std_logic_vector(120 downto 0) := "0000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant state29: std_logic_vector(120 downto 0) := "0000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant state14: std_logic_vector(120 downto 0) := "0000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant state59: std_logic_vector(120 downto 0) := "0000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant state16: std_logic_vector(120 downto 0) := "0000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant state18: std_logic_vector(120 downto 0) := "0000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant state19: std_logic_vector(120 downto 0) := "0000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant state21: std_logic_vector(120 downto 0) := "0000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant state20: std_logic_vector(120 downto 0) := "0000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant state22: std_logic_vector(120 downto 0) := "0000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant state23: std_logic_vector(120 downto 0) := "0000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant state24: std_logic_vector(120 downto 0) := "0000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant state26: std_logic_vector(120 downto 0) := "0000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant state25: std_logic_vector(120 downto 0) := "0000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant state28: std_logic_vector(120 downto 0) := "0000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant state27: std_logic_vector(120 downto 0) := "0000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant state36: std_logic_vector(120 downto 0) := "0000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant state34: std_logic_vector(120 downto 0) := "0000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant state32: std_logic_vector(120 downto 0) := "0000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant state30: std_logic_vector(120 downto 0) := "0000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant state38: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant state31: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant state37: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant state55: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant state33: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant state57: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant state35: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant state43: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant state41: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant state39: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000";
constant state45: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000";
constant state40: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000";
constant state44: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000";
constant state50: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000";
constant state42: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000";
constant state48: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000";
constant state46: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000";
constant state47: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000";
constant state49: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000";
constant state52: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000";
constant state51: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000";
constant state54: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000";
constant state53: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000";
constant state56: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000";
constant state58: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000";
constant state67: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000";
constant state60: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000";
constant state65: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000";
constant state63: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000";
constant state61: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000";
constant state82: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000";
constant state62: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000";
constant state83: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000";
constant state64: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000";
constant state89: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000";
constant state66: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000";
constant state81: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000";
constant state80: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000";
constant state78: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000";
constant state76: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000";
constant state74: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000";
constant state72: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000";
constant state70: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000";
constant state68: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000";
constant state96: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000";
constant state69: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000";
constant state98: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000";
constant state71: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000";
constant state103: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000";
constant state73: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000";
constant state107: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000";
constant state75: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000";
constant state115: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000";
constant state77: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000";
constant state117: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000";
constant state79: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000";
constant state84: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000";
constant state86: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000";
constant state85: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000";
constant state88: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000";
constant state87: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000";
constant state91: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000";
constant state90: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000";
constant state92: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000";
constant state95: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000";
constant state93: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000";
constant state94: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000";
constant state97: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000";
constant state101: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000";
constant state99: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000";
constant state100: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000";
constant state102: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000";
constant state105: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000";
constant state104: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000";
constant state106: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000";
constant state112: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000";
constant state108: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000";
constant state110: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000";
constant state109: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000";
constant state111: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000";
constant state114: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000";
constant state113: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000";
constant state116: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000";
constant state118: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000";
constant state121: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100";
constant state119: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010";
constant state120: std_logic_vector(120 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001";
signal current_state, next_state: std_logic_vector(120 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "-------------------------------------------------------------------------------------------------------------------------"; output <= "--------------------------------------------------------";
if std_match(input, "0--------------------------") then next_state <= state1; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
else
case current_state is
when state1 =>
if std_match(input, "1--------------------------") then next_state <= state3; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state2 =>
if std_match(input, "1--------------------------") then next_state <= state1; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state3 =>
if std_match(input, "1--------------------------") then next_state <= state4; output <= "00000010010000001-0000000-00-0001001000010-0-----00-0---";
end if;
when state4 =>
if std_match(input, "1--------------------------") then next_state <= state5; output <= "00000010000000000-0000000-00-0000000110101-0-----00-0---";
end if;
when state5 =>
if std_match(input, "1--------------------------") then next_state <= state7; output <= "00000001000000000-0000000-00-0000000001000-0-----00-0---";
end if;
when state6 =>
if std_match(input, "1--------------------------") then next_state <= state2; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state7 =>
if std_match(input, "1-----0--------------------") then next_state <= state9; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1-----1--------------------") then next_state <= state8; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state8 =>
if std_match(input, "1--------------------------") then next_state <= state17; output <= "00000010000000000-0000000-00-0000000001000-0-----00-0---";
end if;
when state9 =>
if std_match(input, "1----0---------------------") then next_state <= state12; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1----1---------------------") then next_state <= state10; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state10 =>
if std_match(input, "1--------------------------") then next_state <= state11; output <= "00000010000000000-0000001-00-0000000000001-0-----00-0---";
end if;
when state11 =>
if std_match(input, "1--------------------------") then next_state <= state12; output <= "00000000000000000-0000000-00-0000010000000-0-----00-0---";
end if;
when state12 =>
if std_match(input, "1---0----------------------") then next_state <= state15; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1---1----------------------") then next_state <= state13; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state13 =>
if std_match(input, "1--------------------------") then next_state <= state29; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state14 =>
if std_match(input, "1--------------------------") then next_state <= state17; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state15 =>
if std_match(input, "1--------------------------") then next_state <= state59; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state16 =>
if std_match(input, "1--------------------------") then next_state <= state17; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state17 =>
if std_match(input, "1--------------------------") then next_state <= state18; output <= "0000000000010100001000000-10-000000000000011-----00-0---";
end if;
when state18 =>
if std_match(input, "1--------------------------") then next_state <= state19; output <= "00100000000000000-0000000-00-0000000000000-0000--00-0---";
end if;
when state19 =>
if std_match(input, "1--0-----------------------") then next_state <= state21; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1--1-----------------------") then next_state <= state20; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state20 =>
if std_match(input, "1--------------------------") then next_state <= state21; output <= "00000001000000000-0000000-00-0000000100000-0-----00-0---";
end if;
when state21 =>
if std_match(input, "1--------------------------") then next_state <= state22; output <= "01000000000100000-0000000-10-100000000000000000001001---";
end if;
when state22 =>
if std_match(input, "1--------------------------") then next_state <= state23; output <= "00010000000000000-0000000-00-0000000000000-0000--01-0---";
end if;
when state23 =>
if std_match(input, "1--------------------------") then next_state <= state24; output <= "00000000100000000-0000000-00-0000000000000-0---0000-0---";
end if;
when state24 =>
if std_match(input, "1-0------------------------") then next_state <= state26; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1-1------------------------") then next_state <= state25; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state25 =>
if std_match(input, "1--------------------------") then next_state <= state26; output <= "00000001000000000-0000000-00-0000000010000-0-----00-0---";
end if;
when state26 =>
if std_match(input, "10-------------------------") then next_state <= state28; output <= "00000000010000010-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "11-------------------------") then next_state <= state27; output <= "00000000010000010-0000000-00-0000000000000-0-----00-0---";
end if;
when state27 =>
if std_match(input, "1--------------------------") then next_state <= state28; output <= "00000000000000000-0000000-00-0010000000000-0-----00-0---";
end if;
when state28 =>
if std_match(input, "1--------------------------") then next_state <= state7; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state29 =>
if std_match(input, "1------1-------------------") then next_state <= state36; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------01------------------") then next_state <= state36; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------0011----------------") then next_state <= state36; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------0010----------------") then next_state <= state34; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------0001----------------") then next_state <= state32; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------0000----------------") then next_state <= state30; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state30 =>
if std_match(input, "1--------------------------") then next_state <= state38; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state31 =>
if std_match(input, "1--------------------------") then next_state <= state37; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state32 =>
if std_match(input, "1--------------------------") then next_state <= state55; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state33 =>
if std_match(input, "1--------------------------") then next_state <= state37; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state34 =>
if std_match(input, "1--------------------------") then next_state <= state57; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state35 =>
if std_match(input, "1--------------------------") then next_state <= state37; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state36 =>
if std_match(input, "1--------------------------") then next_state <= state37; output <= "00000001000000000-0000000-00-0000000010000-0-----00-0---";
end if;
when state37 =>
if std_match(input, "1--------------------------") then next_state <= state14; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state38 =>
if std_match(input, "1----------1---------------") then next_state <= state43; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1----------01--------------") then next_state <= state43; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1----------001-------------") then next_state <= state43; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1----------0001------------") then next_state <= state41; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1----------0000------------") then next_state <= state39; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state39 =>
if std_match(input, "1--------------------------") then next_state <= state45; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state40 =>
if std_match(input, "1--------------------------") then next_state <= state44; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state41 =>
if std_match(input, "1--------------------------") then next_state <= state50; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state42 =>
if std_match(input, "1--------------------------") then next_state <= state44; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state43 =>
if std_match(input, "1--------------------------") then next_state <= state44; output <= "00000001000000000-0000000-00-0000000010000-0-----00-0---";
end if;
when state44 =>
if std_match(input, "1--------------------------") then next_state <= state31; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state45 =>
if std_match(input, "1--------------0-----------") then next_state <= state48; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1--------------1-----------") then next_state <= state46; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state46 =>
if std_match(input, "1--------------------------") then next_state <= state47; output <= "0000000001000101001000000-00-0000000000000-0-----00-0---";
end if;
when state47 =>
if std_match(input, "1--------------------------") then next_state <= state49; output <= "00000000000000000-0000000-00-0000100000000-0-----00-0---";
end if;
when state48 =>
if std_match(input, "1--------------------------") then next_state <= state49; output <= "0000000000100000111001010-00-0000000000000-0-----00-0---";
end if;
when state49 =>
if std_match(input, "1--------------------------") then next_state <= state40; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state50 =>
if std_match(input, "1--------------0-----------") then next_state <= state52; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1--------------1-----------") then next_state <= state51; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state51 =>
if std_match(input, "1--------------------------") then next_state <= state54; output <= "0000000000100000111001010-00-0000000000000-0-----00-0---";
end if;
when state52 =>
if std_match(input, "1--------------------------") then next_state <= state53; output <= "0000000000000101001000000-00-0000000000000-0-----00-0---";
end if;
when state53 =>
if std_match(input, "1--------------------------") then next_state <= state54; output <= "00000000000000000-0000000-00-0000100000000-0-----00-0---";
end if;
when state54 =>
if std_match(input, "1--------------------------") then next_state <= state42; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state55 =>
if std_match(input, "1--------------------------") then next_state <= state56; output <= "0000000000100000111001010-00-0000000000000-0-----00-0---";
end if;
when state56 =>
if std_match(input, "1--------------------------") then next_state <= state33; output <= "00000000000000000-0000000-00-0000100000000-0-----00-0---";
end if;
when state57 =>
if std_match(input, "1--------------------------") then next_state <= state58; output <= "00000000001000001-0001000-00-0000000000000-0-----00-0---";
end if;
when state58 =>
if std_match(input, "1--------------------------") then next_state <= state35; output <= "00000000000000000-0000000-00-0000100000000-0-----00-0---";
end if;
when state59 =>
if std_match(input, "1---------------0----------") then next_state <= state67; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1---------------1----------") then next_state <= state60; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state60 =>
if std_match(input, "1------1-------------------") then next_state <= state67; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------01------------------") then next_state <= state67; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------0011----------------") then next_state <= state67; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------0010----------------") then next_state <= state65; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------0001----------------") then next_state <= state63; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------0000----------------") then next_state <= state61; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state61 =>
if std_match(input, "1--------------------------") then next_state <= state82; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state62 =>
if std_match(input, "1--------------------------") then next_state <= state67; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state63 =>
if std_match(input, "1--------------------------") then next_state <= state83; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state64 =>
if std_match(input, "1--------------------------") then next_state <= state67; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state65 =>
if std_match(input, "1--------------------------") then next_state <= state89; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state66 =>
if std_match(input, "1--------------------------") then next_state <= state81; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state67 =>
if std_match(input, "1------1-------------------") then next_state <= state80; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------011-----------------") then next_state <= state80; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------0101----------------") then next_state <= state78; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------0100----------------") then next_state <= state76; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------0011----------------") then next_state <= state74; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------0010----------------") then next_state <= state72; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------0001----------------") then next_state <= state70; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1------0000----------------") then next_state <= state68; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state68 =>
if std_match(input, "1--------------------------") then next_state <= state96; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state69 =>
if std_match(input, "1--------------------------") then next_state <= state81; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state70 =>
if std_match(input, "1--------------------------") then next_state <= state98; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state71 =>
if std_match(input, "1--------------------------") then next_state <= state81; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state72 =>
if std_match(input, "1--------------------------") then next_state <= state103; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state73 =>
if std_match(input, "1--------------------------") then next_state <= state81; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state74 =>
if std_match(input, "1--------------------------") then next_state <= state107; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state75 =>
if std_match(input, "1--------------------------") then next_state <= state81; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state76 =>
if std_match(input, "1--------------------------") then next_state <= state115; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state77 =>
if std_match(input, "1--------------------------") then next_state <= state81; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state78 =>
if std_match(input, "1--------------------------") then next_state <= state117; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state79 =>
if std_match(input, "1--------------------------") then next_state <= state81; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state80 =>
if std_match(input, "1--------------------------") then next_state <= state81; output <= "00000001000000000-0000000-00-0000000010000-0-----00-0---";
end if;
when state81 =>
if std_match(input, "1--------------------------") then next_state <= state16; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state82 =>
if std_match(input, "1--------------------------") then next_state <= state62; output <= "00000001000000000-0000000-00-0000000010000-0-----00-0---";
end if;
when state83 =>
if std_match(input, "1--------------------------") then next_state <= state84; output <= "00000001000000000-0000000-00-0000000001000-0-----00-0---";
end if;
when state84 =>
if std_match(input, "1--------------------------") then next_state <= state86; output <= "00001000000001001-0000000-00-0000000000000-0100--00-0---";
end if;
when state85 =>
if std_match(input, "1--------------------------") then next_state <= state64; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state86 =>
if std_match(input, "1----------------0---------") then next_state <= state88; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1----------------1---------") then next_state <= state87; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state87 =>
if std_match(input, "1--------------------------") then next_state <= state16; output <= "00000001000000000-0000000-00-0000100001000-0-----00-0---";
end if;
when state88 =>
if std_match(input, "1--------------------------") then next_state <= state86; output <= "00000000000000000-0000000-00-0000100000000-0-----00-0---";
end if;
when state89 =>
if std_match(input, "1--------------------------") then next_state <= state91; output <= "00001001000000000-0000000-00-0001000001000-0-----00-0---";
end if;
when state90 =>
if std_match(input, "1--------------------------") then next_state <= state66; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state91 =>
if std_match(input, "1--------------------------") then next_state <= state92; output <= "00000010000000000-0000000-00-0000000000000-0010--00-0---";
end if;
when state92 =>
if std_match(input, "1--0-----------------------") then next_state <= state95; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1--1-----------------------") then next_state <= state93; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state93 =>
if std_match(input, "1--------------------------") then next_state <= state94; output <= "00000000000100001-0000000-10-0000000000000-0-----00-0---";
end if;
when state94 =>
if std_match(input, "1--------------------------") then next_state <= state16; output <= "00000000000000000-0000000-00-0000100000000-0-----00-0---";
end if;
when state95 =>
if std_match(input, "1--------------------------") then next_state <= state91; output <= "00000000000000000-0000000-00-0010100000000-0-----00-0---";
end if;
when state96 =>
if std_match(input, "1--------------------------") then next_state <= state97; output <= "00000100000001000-0000000-00-000000000000011101111011101";
end if;
when state97 =>
if std_match(input, "1--------------------------") then next_state <= state69; output <= "001000010000000100101010010110100000000001-0-----00-0---";
end if;
when state98 =>
if std_match(input, "1--------------0-----------") then next_state <= state101; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1--------------1-----------") then next_state <= state99; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state99 =>
if std_match(input, "1--------------------------") then next_state <= state100; output <= "00000100000001000-0000000-00-000000000000011101111011101";
end if;
when state100 =>
if std_match(input, "1--------------------------") then next_state <= state102; output <= "001000010000000100101010010110100000000001-0-----00-0---";
end if;
when state101 =>
if std_match(input, "1--------------------------") then next_state <= state102; output <= "00000100000001001-0000000-00-0000000001000-0100--00-0---";
end if;
when state102 =>
if std_match(input, "1--------------------------") then next_state <= state71; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state103 =>
if std_match(input, "1--------------0-----------") then next_state <= state105; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1--------------1-----------") then next_state <= state104; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state104 =>
if std_match(input, "1--------------------------") then next_state <= state106; output <= "0000000000000101001000000-00-0000000000000-0-----00-0---";
end if;
when state105 =>
if std_match(input, "1--------------------------") then next_state <= state106; output <= "00000100000001001-0000000-00-0000000001000-0100--00-0---";
end if;
when state106 =>
if std_match(input, "1--------------------------") then next_state <= state73; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state107 =>
if std_match(input, "1--------------0-----------") then next_state <= state112; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1--------------1-----------") then next_state <= state108; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state108 =>
if std_match(input, "1-----------------00000000-") then next_state <= state110; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1-----------------1--------") then next_state <= state110; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1-----------------01-------") then next_state <= state110; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1-----------------001------") then next_state <= state110; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1-----------------0001-----") then next_state <= state110; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1-----------------00001----") then next_state <= state110; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1-----------------000001---") then next_state <= state110; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1-----------------0000001--") then next_state <= state110; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1-----------------00000001-") then next_state <= state109; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state109 =>
if std_match(input, "1--------------------------") then next_state <= state112; output <= "0000000000001100101000000-00-0000000000000-0-----00-0100";
end if;
when state110 =>
if std_match(input, "1--------------------------") then next_state <= state111; output <= "0000010000000101001010000-0000100000000000111000110-0100";
end if;
when state111 =>
if std_match(input, "1--------------------------") then next_state <= state114; output <= "00000001000000000-0000100001-0000000000001-0-----00-0---";
end if;
when state112 =>
if std_match(input, "1--------------------------") then next_state <= state113; output <= "00000100000001001-0000000-00-0000000000000-0100--00-0---";
end if;
when state113 =>
if std_match(input, "1--------------------------") then next_state <= state114; output <= "00000001000000000-0000000-00-0000000001000-0-----00-0---";
end if;
when state114 =>
if std_match(input, "1--------------------------") then next_state <= state75; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state115 =>
if std_match(input, "1--------------------------") then next_state <= state116; output <= "00001000000010001-0010000-00-0000000000000-01011010-0101";
end if;
when state116 =>
if std_match(input, "1--------------------------") then next_state <= state77; output <= "10000001000000000-0000100-00-0001000001101-0-----00-0---";
end if;
when state117 =>
if std_match(input, "1--------------------------") then next_state <= state118; output <= "00000010000000000-0000000-00-0000000000000-0-----00-0011";
end if;
when state118 =>
if std_match(input, "1-------------------------0") then next_state <= state121; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
elsif std_match(input, "1-------------------------1") then next_state <= state119; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when state119 =>
if std_match(input, "1--------------------------") then next_state <= state120; output <= "0000010000001000001000000-00-0000000000000111011010-0101";
end if;
when state120 =>
if std_match(input, "1--------------------------") then next_state <= state16; output <= "00010010000000010-000000000110100000000100-0-----00-0---";
end if;
when state121 =>
if std_match(input, "1--------------------------") then next_state <= state79; output <= "00000000000000000-0000000-00-0000000000000-0-----00-0---";
end if;
when others => next_state <= "-------------------------------------------------------------------------------------------------------------------------"; output <= "--------------------------------------------------------";
end case;
end if;
end process;
end behaviour;
|
agpl-3.0
|
chastell/art-decomp
|
kiss/s27_rnd.vhd
|
1
|
3869
|
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity s27_rnd is
port(
clock: in std_logic;
input: in std_logic_vector(3 downto 0);
output: out std_logic_vector(0 downto 0)
);
end s27_rnd;
architecture behaviour of s27_rnd is
constant s000: std_logic_vector(2 downto 0) := "101";
constant s001: std_logic_vector(2 downto 0) := "010";
constant s101: std_logic_vector(2 downto 0) := "011";
constant s100: std_logic_vector(2 downto 0) := "110";
constant s010: std_logic_vector(2 downto 0) := "111";
constant s011: std_logic_vector(2 downto 0) := "001";
signal current_state, next_state: std_logic_vector(2 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "---"; output <= "-";
case current_state is
when s000 =>
if std_match(input, "010-") then next_state <= s001; output <= "1";
elsif std_match(input, "011-") then next_state <= s000; output <= "1";
elsif std_match(input, "110-") then next_state <= s101; output <= "1";
elsif std_match(input, "111-") then next_state <= s100; output <= "1";
elsif std_match(input, "10-0") then next_state <= s100; output <= "1";
elsif std_match(input, "00-0") then next_state <= s000; output <= "1";
elsif std_match(input, "-0-1") then next_state <= s010; output <= "0";
end if;
when s001 =>
if std_match(input, "0-0-") then next_state <= s001; output <= "1";
elsif std_match(input, "0-1-") then next_state <= s000; output <= "1";
elsif std_match(input, "1-0-") then next_state <= s101; output <= "1";
elsif std_match(input, "1-1-") then next_state <= s100; output <= "1";
end if;
when s101 =>
if std_match(input, "0-0-") then next_state <= s001; output <= "1";
elsif std_match(input, "0-1-") then next_state <= s000; output <= "1";
elsif std_match(input, "1-0-") then next_state <= s101; output <= "1";
elsif std_match(input, "1-1-") then next_state <= s100; output <= "1";
end if;
when s100 =>
if std_match(input, "010-") then next_state <= s001; output <= "1";
elsif std_match(input, "011-") then next_state <= s000; output <= "1";
elsif std_match(input, "00--") then next_state <= s000; output <= "1";
elsif std_match(input, "111-") then next_state <= s100; output <= "1";
elsif std_match(input, "110-") then next_state <= s101; output <= "1";
elsif std_match(input, "10--") then next_state <= s100; output <= "1";
end if;
when s010 =>
if std_match(input, "0-1-") then next_state <= s010; output <= "0";
elsif std_match(input, "000-") then next_state <= s010; output <= "0";
elsif std_match(input, "010-") then next_state <= s011; output <= "0";
elsif std_match(input, "1101") then next_state <= s101; output <= "1";
elsif std_match(input, "1111") then next_state <= s100; output <= "1";
elsif std_match(input, "10-1") then next_state <= s010; output <= "0";
elsif std_match(input, "1100") then next_state <= s101; output <= "1";
elsif std_match(input, "1110") then next_state <= s100; output <= "1";
elsif std_match(input, "10-0") then next_state <= s100; output <= "1";
end if;
when s011 =>
if std_match(input, "0-0-") then next_state <= s011; output <= "0";
elsif std_match(input, "0-1-") then next_state <= s010; output <= "0";
elsif std_match(input, "1-1-") then next_state <= s100; output <= "1";
elsif std_match(input, "1-0-") then next_state <= s101; output <= "1";
end if;
when others => next_state <= "---"; output <= "-";
end case;
end process;
end behaviour;
|
agpl-3.0
|
chastell/art-decomp
|
kiss/beecount_hot.vhd
|
1
|
3554
|
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity beecount_hot is
port(
clock: in std_logic;
input: in std_logic_vector(2 downto 0);
output: out std_logic_vector(3 downto 0)
);
end beecount_hot;
architecture behaviour of beecount_hot is
constant st0: std_logic_vector(6 downto 0) := "1000000";
constant st1: std_logic_vector(6 downto 0) := "0100000";
constant st4: std_logic_vector(6 downto 0) := "0010000";
constant st2: std_logic_vector(6 downto 0) := "0001000";
constant st3: std_logic_vector(6 downto 0) := "0000100";
constant st5: std_logic_vector(6 downto 0) := "0000010";
constant st6: std_logic_vector(6 downto 0) := "0000001";
signal current_state, next_state: std_logic_vector(6 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "-------"; output <= "----";
case current_state is
when st0 =>
if std_match(input, "000") then next_state <= st0; output <= "0101";
elsif std_match(input, "100") then next_state <= st1; output <= "0101";
elsif std_match(input, "010") then next_state <= st4; output <= "0101";
elsif std_match(input, "--1") then next_state <= st0; output <= "1010";
end if;
when st1 =>
if std_match(input, "100") then next_state <= st1; output <= "0101";
elsif std_match(input, "0-0") then next_state <= st0; output <= "0101";
elsif std_match(input, "110") then next_state <= st2; output <= "0101";
elsif std_match(input, "--1") then next_state <= st0; output <= "1010";
end if;
when st2 =>
if std_match(input, "110") then next_state <= st2; output <= "0101";
elsif std_match(input, "100") then next_state <= st1; output <= "0101";
elsif std_match(input, "010") then next_state <= st3; output <= "0101";
elsif std_match(input, "--1") then next_state <= st0; output <= "1010";
end if;
when st3 =>
if std_match(input, "010") then next_state <= st3; output <= "0101";
elsif std_match(input, "110") then next_state <= st2; output <= "0101";
elsif std_match(input, "000") then next_state <= st0; output <= "0110";
elsif std_match(input, "--1") then next_state <= st0; output <= "1010";
end if;
when st4 =>
if std_match(input, "010") then next_state <= st4; output <= "0101";
elsif std_match(input, "-00") then next_state <= st0; output <= "0101";
elsif std_match(input, "110") then next_state <= st5; output <= "0101";
elsif std_match(input, "--1") then next_state <= st0; output <= "1010";
end if;
when st5 =>
if std_match(input, "110") then next_state <= st5; output <= "0101";
elsif std_match(input, "010") then next_state <= st4; output <= "0101";
elsif std_match(input, "100") then next_state <= st6; output <= "0101";
elsif std_match(input, "--1") then next_state <= st0; output <= "1010";
end if;
when st6 =>
if std_match(input, "100") then next_state <= st6; output <= "0101";
elsif std_match(input, "110") then next_state <= st5; output <= "0101";
elsif std_match(input, "000") then next_state <= st0; output <= "1001";
elsif std_match(input, "--1") then next_state <= st0; output <= "1010";
end if;
when others => next_state <= "-------"; output <= "----";
end case;
end process;
end behaviour;
|
agpl-3.0
|
chastell/art-decomp
|
kiss/bbara_hot.vhd
|
1
|
6347
|
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity bbara_hot is
port(
clock: in std_logic;
input: in std_logic_vector(3 downto 0);
output: out std_logic_vector(1 downto 0)
);
end bbara_hot;
architecture behaviour of bbara_hot is
constant st0: std_logic_vector(9 downto 0) := "1000000000";
constant st1: std_logic_vector(9 downto 0) := "0100000000";
constant st4: std_logic_vector(9 downto 0) := "0010000000";
constant st2: std_logic_vector(9 downto 0) := "0001000000";
constant st3: std_logic_vector(9 downto 0) := "0000100000";
constant st7: std_logic_vector(9 downto 0) := "0000010000";
constant st5: std_logic_vector(9 downto 0) := "0000001000";
constant st6: std_logic_vector(9 downto 0) := "0000000100";
constant st8: std_logic_vector(9 downto 0) := "0000000010";
constant st9: std_logic_vector(9 downto 0) := "0000000001";
signal current_state, next_state: std_logic_vector(9 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "----------"; output <= "--";
case current_state is
when st0 =>
if std_match(input, "--01") then next_state <= st0; output <= "00";
elsif std_match(input, "--10") then next_state <= st0; output <= "00";
elsif std_match(input, "--00") then next_state <= st0; output <= "00";
elsif std_match(input, "0011") then next_state <= st0; output <= "00";
elsif std_match(input, "-111") then next_state <= st1; output <= "00";
elsif std_match(input, "1011") then next_state <= st4; output <= "00";
end if;
when st1 =>
if std_match(input, "--01") then next_state <= st1; output <= "00";
elsif std_match(input, "--10") then next_state <= st1; output <= "00";
elsif std_match(input, "--00") then next_state <= st1; output <= "00";
elsif std_match(input, "0011") then next_state <= st0; output <= "00";
elsif std_match(input, "-111") then next_state <= st2; output <= "00";
elsif std_match(input, "1011") then next_state <= st4; output <= "00";
end if;
when st2 =>
if std_match(input, "--01") then next_state <= st2; output <= "00";
elsif std_match(input, "--10") then next_state <= st2; output <= "00";
elsif std_match(input, "--00") then next_state <= st2; output <= "00";
elsif std_match(input, "0011") then next_state <= st1; output <= "00";
elsif std_match(input, "-111") then next_state <= st3; output <= "00";
elsif std_match(input, "1011") then next_state <= st4; output <= "00";
end if;
when st3 =>
if std_match(input, "--01") then next_state <= st3; output <= "10";
elsif std_match(input, "--10") then next_state <= st3; output <= "10";
elsif std_match(input, "--00") then next_state <= st3; output <= "10";
elsif std_match(input, "0011") then next_state <= st7; output <= "00";
elsif std_match(input, "-111") then next_state <= st3; output <= "10";
elsif std_match(input, "1011") then next_state <= st4; output <= "00";
end if;
when st4 =>
if std_match(input, "--01") then next_state <= st4; output <= "00";
elsif std_match(input, "--10") then next_state <= st4; output <= "00";
elsif std_match(input, "--00") then next_state <= st4; output <= "00";
elsif std_match(input, "0011") then next_state <= st0; output <= "00";
elsif std_match(input, "-111") then next_state <= st1; output <= "00";
elsif std_match(input, "1011") then next_state <= st5; output <= "00";
end if;
when st5 =>
if std_match(input, "--01") then next_state <= st5; output <= "00";
elsif std_match(input, "--10") then next_state <= st5; output <= "00";
elsif std_match(input, "--00") then next_state <= st5; output <= "00";
elsif std_match(input, "0011") then next_state <= st4; output <= "00";
elsif std_match(input, "-111") then next_state <= st1; output <= "00";
elsif std_match(input, "1011") then next_state <= st6; output <= "00";
end if;
when st6 =>
if std_match(input, "--01") then next_state <= st6; output <= "01";
elsif std_match(input, "--10") then next_state <= st6; output <= "01";
elsif std_match(input, "--00") then next_state <= st6; output <= "01";
elsif std_match(input, "0011") then next_state <= st7; output <= "00";
elsif std_match(input, "-111") then next_state <= st1; output <= "00";
elsif std_match(input, "1011") then next_state <= st6; output <= "01";
end if;
when st7 =>
if std_match(input, "--01") then next_state <= st7; output <= "00";
elsif std_match(input, "--10") then next_state <= st7; output <= "00";
elsif std_match(input, "--00") then next_state <= st7; output <= "00";
elsif std_match(input, "0011") then next_state <= st8; output <= "00";
elsif std_match(input, "-111") then next_state <= st1; output <= "00";
elsif std_match(input, "1011") then next_state <= st4; output <= "00";
end if;
when st8 =>
if std_match(input, "--01") then next_state <= st8; output <= "00";
elsif std_match(input, "--10") then next_state <= st8; output <= "00";
elsif std_match(input, "--00") then next_state <= st8; output <= "00";
elsif std_match(input, "0011") then next_state <= st9; output <= "00";
elsif std_match(input, "-111") then next_state <= st1; output <= "00";
elsif std_match(input, "1011") then next_state <= st4; output <= "00";
end if;
when st9 =>
if std_match(input, "--01") then next_state <= st9; output <= "00";
elsif std_match(input, "--10") then next_state <= st9; output <= "00";
elsif std_match(input, "--00") then next_state <= st9; output <= "00";
elsif std_match(input, "0011") then next_state <= st0; output <= "00";
elsif std_match(input, "-111") then next_state <= st1; output <= "00";
elsif std_match(input, "1011") then next_state <= st4; output <= "00";
end if;
when others => next_state <= "----------"; output <= "--";
end case;
end process;
end behaviour;
|
agpl-3.0
|
JimLewis/OSVVM
|
TextUtilPkg.vhd
|
1
|
17500
|
--
-- File Name: TextUtilPkg.vhd
-- Design Unit Name: TextUtilPkg
-- Revision: STANDARD VERSION
--
-- Maintainer: Jim Lewis email: [email protected]
-- Contributor(s):
-- Jim Lewis [email protected]
--
--
-- Description:
-- Shared Utilities for handling text files
--
--
-- Developed for:
-- SynthWorks Design Inc.
-- VHDL Training Classes
-- 11898 SW 128th Ave. Tigard, Or 97223
-- http://www.SynthWorks.com
--
-- Revision History:
-- Date Version Description
-- 01/2015 2015.05 Initial revision
-- 01/2016 2016.01 Update for L.all(L'left)
-- 11/2016 2016.11 Added IsUpper, IsLower, to_upper, to_lower
-- 01/2020 2020.01 Updated Licenses to Apache
-- 08/2020 2020.08 Added ReadUntilDelimiterOrEOL and FindDelimiter
--
--
-- This file is part of OSVVM.
--
-- Copyright (c) 2015 - 2020 by SynthWorks Design Inc.
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- https://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
use std.textio.all ;
library ieee ;
use ieee.std_logic_1164.all ;
package TextUtilPkg is
------------------------------------------------------------
function IsUpper (constant Char : character ) return boolean ;
function IsLower (constant Char : character ) return boolean ;
function to_lower (constant Char : character ) return character ;
function to_lower (constant Str : string ) return string ;
function to_upper (constant Char : character ) return character ;
function to_upper (constant Str : string ) return string ;
function IsHex (constant Char : character ) return boolean ;
function IsNumber (constant Char : character ) return boolean ;
function IsNumber (Name : string ) return boolean ;
function isstd_logic (constant Char : character ) return boolean ;
-- Crutch until VHDL-2019 conditional initialization
function IfElse(Expr : boolean ; A, B : string) return string ;
------------------------------------------------------------
procedure SkipWhiteSpace (
------------------------------------------------------------
variable L : InOut line ;
variable Empty : out boolean
) ;
procedure SkipWhiteSpace (variable L : InOut line) ;
------------------------------------------------------------
procedure EmptyOrCommentLine (
------------------------------------------------------------
variable L : InOut line ;
variable Empty : InOut boolean ;
variable MultiLineComment : inout boolean
) ;
------------------------------------------------------------
procedure ReadUntilDelimiterOrEOL(
------------------------------------------------------------
variable L : InOut line ;
variable Name : InOut line ;
constant Delimiter : In character ;
variable ReadValid : Out boolean
) ;
------------------------------------------------------------
procedure FindDelimiter(
------------------------------------------------------------
variable L : InOut line ;
constant Delimiter : In character ;
variable Found : Out boolean
) ;
------------------------------------------------------------
procedure ReadHexToken (
-- Reads Upto Result'length values, less is ok.
-- Does not skip white space
------------------------------------------------------------
variable L : InOut line ;
variable Result : Out std_logic_vector ;
variable StrLen : Out integer
) ;
------------------------------------------------------------
procedure ReadBinaryToken (
-- Reads Upto Result'length values, less is ok.
-- Does not skip white space
------------------------------------------------------------
variable L : InOut line ;
variable Result : Out std_logic_vector ;
variable StrLen : Out integer
) ;
end TextUtilPkg ;
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
package body TextUtilPkg is
constant LOWER_TO_UPPER_OFFSET : integer := character'POS('a') - character'POS('A') ;
------------------------------------------------------------
function "-" (R : character ; L : integer ) return character is
------------------------------------------------------------
begin
return character'VAL(character'pos(R) - L) ;
end function "-" ;
------------------------------------------------------------
function "+" (R : character ; L : integer ) return character is
------------------------------------------------------------
begin
return character'VAL(character'pos(R) + L) ;
end function "+" ;
------------------------------------------------------------
function IsUpper (constant Char : character ) return boolean is
------------------------------------------------------------
begin
if Char >= 'A' and Char <= 'Z' then
return TRUE ;
else
return FALSE ;
end if ;
end function IsUpper ;
------------------------------------------------------------
function IsLower (constant Char : character ) return boolean is
------------------------------------------------------------
begin
if Char >= 'a' and Char <= 'z' then
return TRUE ;
else
return FALSE ;
end if ;
end function IsLower ;
------------------------------------------------------------
function to_lower (constant Char : character ) return character is
------------------------------------------------------------
begin
if IsUpper(Char) then
return Char + LOWER_TO_UPPER_OFFSET ;
else
return Char ;
end if ;
end function to_lower ;
------------------------------------------------------------
function to_lower (constant Str : string ) return string is
------------------------------------------------------------
variable result : string(Str'range) ;
begin
for i in Str'range loop
result(i) := to_lower(Str(i)) ;
end loop ;
return result ;
end function to_lower ;
------------------------------------------------------------
function to_upper (constant Char : character ) return character is
------------------------------------------------------------
begin
if IsLower(Char) then
return Char - LOWER_TO_UPPER_OFFSET ;
else
return Char ;
end if ;
end function to_upper ;
------------------------------------------------------------
function to_upper (constant Str : string ) return string is
------------------------------------------------------------
variable result : string(Str'range) ;
begin
for i in Str'range loop
result(i) := to_upper(Str(i)) ;
end loop ;
return result ;
end function to_upper ;
------------------------------------------------------------
function IsHex (constant Char : character ) return boolean is
------------------------------------------------------------
begin
if Char >= '0' and Char <= '9' then
return TRUE ;
elsif Char >= 'a' and Char <= 'f' then
return TRUE ;
elsif Char >= 'A' and Char <= 'F' then
return TRUE ;
else
return FALSE ;
end if ;
end function IsHex ;
------------------------------------------------------------
function IsNumber (constant Char : character ) return boolean is
------------------------------------------------------------
begin
return Char >= '0' and Char <= '9' ;
end function IsNumber ;
------------------------------------------------------------
function IsNumber (Name : string ) return boolean is
------------------------------------------------------------
begin
for i in Name'range loop
if not IsNumber(Name(i)) then
return FALSE ;
end if ;
end loop ;
return TRUE ;
end function IsNumber ;
------------------------------------------------------------
function isstd_logic (constant Char : character ) return boolean is
------------------------------------------------------------
begin
case Char is
when 'U' | 'X' | '0' | '1' | 'Z' | 'W' | 'L' | 'H' | '-' =>
return TRUE ;
when others =>
return FALSE ;
end case ;
end function isstd_logic ;
------------------------------------------------------------
function IfElse(Expr : boolean ; A, B : string) return string is
------------------------------------------------------------
begin
if Expr then
return A ;
else
return B ;
end if ;
end function IfElse ;
-- ------------------------------------------------------------
-- function iscomment (constant Char : character ) return boolean is
-- ------------------------------------------------------------
-- begin
-- case Char is
-- when '#' | '/' | '-' =>
-- return TRUE ;
-- when others =>
-- return FALSE ;
-- end case ;
-- end function iscomment ;
------------------------------------------------------------
procedure SkipWhiteSpace (
------------------------------------------------------------
variable L : InOut line ;
variable Empty : out boolean
) is
variable Valid : boolean ;
variable Char : character ;
constant NBSP : CHARACTER := CHARACTER'val(160); -- space character
begin
Empty := TRUE ;
WhiteSpLoop : while L /= null and L.all'length > 0 loop
if (L.all(L'left) = ' ' or L.all(L'left) = NBSP or L.all(L'left) = HT) then
read (L, Char, Valid) ;
exit when not Valid ;
else
Empty := FALSE ;
return ;
end if ;
end loop WhiteSpLoop ;
end procedure SkipWhiteSpace ;
------------------------------------------------------------
procedure SkipWhiteSpace (
------------------------------------------------------------
variable L : InOut line
) is
variable Empty : boolean ;
begin
SkipWhiteSpace(L, Empty) ;
end procedure SkipWhiteSpace ;
------------------------------------------------------------
-- Package Local
procedure FindCommentEnd (
------------------------------------------------------------
variable L : InOut line ;
variable Empty : out boolean ;
variable MultiLineComment : inout boolean
) is
variable Valid : boolean ;
variable Char : character ;
begin
MultiLineComment := TRUE ;
Empty := TRUE ;
FindEndOfCommentLoop : while L /= null and L.all'length > 1 loop
read(L, Char, Valid) ;
if Char = '*' and L.all(L'left) = '/' then
read(L, Char, Valid) ;
Empty := FALSE ;
MultiLineComment := FALSE ;
exit FindEndOfCommentLoop ;
end if ;
end loop ;
end procedure FindCommentEnd ;
------------------------------------------------------------
procedure EmptyOrCommentLine (
------------------------------------------------------------
variable L : InOut line ;
variable Empty : InOut boolean ;
variable MultiLineComment : inout boolean
) is
variable Valid : boolean ;
variable Next2Char : string(1 to 2) ;
constant NBSP : CHARACTER := CHARACTER'val(160); -- space character
begin
if MultiLineComment then
FindCommentEnd(L, Empty, MultiLineComment) ;
end if ;
EmptyCheckLoop : while not MultiLineComment loop
SkipWhiteSpace(L, Empty) ;
exit when Empty ; -- line null or 0 in length detected by SkipWhite
Empty := TRUE ;
exit when L.all(L'left) = '#' ; -- shell style comment
if L.all'length >= 2 then
if L'ascending then
Next2Char := L.all(L'left to L'left+1) ;
else
Next2Char := L.all(L'left downto L'left-1) ;
end if;
exit when Next2Char = "//" ; -- C style comment
exit when Next2Char = "--" ; -- VHDL style comment
if Next2Char = "/*" then -- C style multi line comment
FindCommentEnd(L, Empty, MultiLineComment) ;
exit when Empty ;
next EmptyCheckLoop ; -- Found end of comment, restart processing line
end if ;
end if ;
Empty := FALSE ;
exit ;
end loop EmptyCheckLoop ;
end procedure EmptyOrCommentLine ;
------------------------------------------------------------
procedure ReadUntilDelimiterOrEOL(
------------------------------------------------------------
variable L : InOut line ;
variable Name : InOut line ;
constant Delimiter : In character ;
variable ReadValid : Out boolean
) is
variable NameStr : string(1 to L'length) ;
variable ReadLen : integer := 1 ;
variable Good : boolean ;
begin
ReadValid := TRUE ;
for i in NameStr'range loop
Read(L, NameStr(i), Good) ;
ReadValid := ReadValid and Good ;
if NameStr(i) = Delimiter then
-- Read(L, NameStr(1 to i), ReadValid) ;
Name := new string'(NameStr(1 to i-1)) ;
exit ;
elsif i = NameStr'length then
-- Read(L, NameStr(1 to i), ReadValid) ;
Name := new string'(NameStr(1 to i)) ;
exit ;
end if ;
end loop ;
end procedure ReadUntilDelimiterOrEOL ;
------------------------------------------------------------
procedure FindDelimiter(
------------------------------------------------------------
variable L : InOut line ;
constant Delimiter : In character ;
variable Found : Out boolean
) is
variable Char : Character ;
variable ReadValid : boolean ;
begin
Found := FALSE ;
ReadLoop : loop
if Delimiter /= ' ' then
SkipWhiteSpace(L) ;
end if ;
Read(L, Char, ReadValid) ;
exit when ReadValid = FALSE or Char /= Delimiter ;
Found := TRUE ;
exit ;
end loop ;
end procedure FindDelimiter ;
------------------------------------------------------------
procedure ReadHexToken (
-- Reads Upto Result'length values, less is ok.
-- Does not skip white space
------------------------------------------------------------
variable L : InOut line ;
variable Result : Out std_logic_vector ;
variable StrLen : Out integer
) is
constant NumHexChars : integer := (Result'length+3)/4 ;
constant ResultNormLen : integer := NumHexChars * 4 ;
variable NextChar : character ;
variable CharCount : integer ;
variable ReturnVal : std_logic_vector(ResultNormLen-1 downto 0) ;
variable ReadVal : std_logic_vector(3 downto 0) ;
variable ReadValid : boolean ;
begin
ReturnVal := (others => '0') ;
CharCount := 0 ;
ReadLoop : while L /= null and L.all'length > 0 loop
NextChar := L.all(L'left) ;
if ishex(NextChar) or NextChar = 'X' or NextChar = 'Z' then
hread(L, ReadVal, ReadValid) ;
ReturnVal := ReturnVal(ResultNormLen-5 downto 0) & ReadVal ;
CharCount := CharCount + 1 ;
exit ReadLoop when CharCount >= NumHexChars ;
elsif NextChar = '_' then
read(L, NextChar, ReadValid) ;
else
exit ;
end if ;
end loop ReadLoop ;
if CharCount >= NumHexChars then
StrLen := Result'length ;
else
StrLen := CharCount * 4 ;
end if ;
Result := ReturnVal(Result'length-1 downto 0) ;
end procedure ReadHexToken ;
------------------------------------------------------------
procedure ReadBinaryToken (
-- Reads Upto Result'length values, less is ok.
-- Does not skip white space
------------------------------------------------------------
variable L : InOut line ;
variable Result : Out std_logic_vector ;
variable StrLen : Out integer
) is
variable NextChar : character ;
variable CharCount : integer ;
variable ReadVal : std_logic ;
variable ReturnVal : std_logic_vector(Result'length-1 downto 0) ;
variable ReadValid : boolean ;
begin
ReturnVal := (others => '0') ;
CharCount := 0 ;
ReadLoop : while L /= null and L.all'length > 0 loop
NextChar := L.all(L'left) ;
if isstd_logic(NextChar) then
read(L, ReadVal, ReadValid) ;
ReturnVal := ReturnVal(Result'length-2 downto 0) & ReadVal ;
CharCount := CharCount + 1 ;
exit ReadLoop when CharCount >= Result'length ;
elsif NextChar = '_' then
read(L, NextChar, ReadValid) ;
else
exit ;
end if ;
end loop ReadLoop ;
StrLen := CharCount ;
Result := ReturnVal ;
end procedure ReadBinaryToken ;
end package body TextUtilPkg ;
|
artistic-2.0
|
JimLewis/OSVVM
|
ResolutionPkg.vhd
|
1
|
21683
|
--
-- File Name: ResolutionPkg.vhd
-- Design Unit Name: ResolutionPkg
-- Revision: STANDARD VERSION
--
-- Maintainer: Jim Lewis email: [email protected]
-- Contributor(s):
-- Jim Lewis email: [email protected]
--
-- Package Defines
-- resolved resolution functions for integer, real, and time
-- types resolved_integer, resolved_real, resolved_time
--
-- Developed for:
-- SynthWorks Design Inc.
-- VHDL Training Classes
-- 11898 SW 128th Ave. Tigard, Or 97223
-- http://www.SynthWorks.com
--
-- Revision History:
-- Date Version Description
-- 09/2006 0.1 Initial revision
-- Numerous revisions for VHDL Testbenches and Verification
-- 02/2009 1.0 VHDL-2008 STANDARD VERSION
-- 05/2015 2015.05 Added Alerts
-- -- Replaced Alerts with asserts as alerts are illegal in pure functions
-- 11/2016 2016.11 Removed Asserts as they are not working as intended.
-- See ResolutionPkg_debug as it uses Alerts to correctly detect errors
-- 01/2020 2020.01 Updated Licenses to Apache
-- 12/2020 2020.12 Updated ToTransaction and FromTransaction with length parameter.
-- Downsizing now permitted when it does not change the value.
--
--
-- This file is part of OSVVM.
--
-- Copyright (c) 2005 - 2020 by SynthWorks Design Inc.
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- https://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
library osvvm ;
use osvvm.AlertLogPkg.all ;
package ResolutionPkg is
constant MULTIPLE_DRIVER_SEVERITY : severity_level := ERROR ;
--
-- Note that not all simulators support resolution functions of the form:
-- subtype std_logic_vector_max is (resolved_max) std_ulogic_vector ;
--
-- Hence, types of the form are offered as a temporary workaround until they do:
-- std_logic_vector_max_c is array (natural range <>) of std_logic_max ; -- for non VHDL-2008
--
-- resolved_max
-- return maximum value.
-- No initializations required on ports, default of type'left is ok
function resolved_max ( s : std_ulogic_vector) return std_ulogic ;
subtype std_logic_max is resolved_max std_ulogic ;
subtype std_logic_vector_max is (resolved_max) std_ulogic_vector ;
type std_logic_vector_max_c is array (natural range <>) of std_logic_max ; -- for non VHDL-2008
subtype unsigned_max is (resolved_max) unresolved_unsigned ;
type unsigned_max_c is array (natural range <>) of std_logic_max ; -- for non VHDL-2008
subtype signed_max is (resolved_max) unresolved_signed ;
type signed_max_c is array (natural range <>) of std_logic_max ; -- for non VHDL-2008
function resolved_max ( s : bit_vector) return bit ;
subtype bit_max is resolved_max bit ;
subtype bit_vector_max is (resolved_max) bit_vector ;
type bit_vector_max_c is array (natural range <>) of bit_max ; -- for non VHDL-2008
function resolved_max ( s : integer_vector ) return integer ;
subtype integer_max is resolved_max integer ;
subtype integer_vector_max is (resolved_max) integer_vector ;
type integer_vector_max_c is array (natural range <>) of integer_max ; -- for non VHDL-2008
function resolved_max ( s : time_vector ) return time ;
subtype time_max is resolved_max time ;
subtype time_vector_max is (resolved_max) time_vector ;
type time_vector_max_c is array (natural range <>) of time_max ; -- for non VHDL-2008
function resolved_max ( s : real_vector ) return real ;
subtype real_max is resolved_max real ;
subtype real_vector_max is (resolved_max) real_vector ;
type real_vector_max_c is array (natural range <>) of real_max ; -- for non VHDL-2008
function resolved_max ( s : string) return character ;
subtype character_max is resolved_max character ;
subtype string_max is (resolved_max) string ;
type string_max_c is array (positive range <>) of character_max ; -- for non VHDL-2008
function resolved_max ( s : boolean_vector) return boolean ;
subtype boolean_max is resolved_max boolean ;
subtype boolean_vector_max is (resolved_max) boolean_vector ;
type boolean_vector_max_c is array (natural range <>) of boolean_max ; -- for non VHDL-2008
--
-- ToTransaction and FromTransaction
-- Convert from Common types to their corresponding _max_c type
--
function Extend(A: std_logic_vector; Size : natural) return std_logic_vector ;
function Reduce(A: std_logic_vector; Size : natural) return std_logic_vector ;
function ToTransaction(A : std_logic_vector) return std_logic_vector_max_c ;
impure function ToTransaction(A : std_logic_vector ; Size : natural) return std_logic_vector_max_c ;
function ToTransaction(A : integer; Size : natural) return std_logic_vector_max_c ;
function FromTransaction (A: std_logic_vector_max_c) return std_logic_vector ;
impure function FromTransaction (A: std_logic_vector_max_c ; Size : natural) return std_logic_vector ;
function FromTransaction (A: std_logic_vector_max_c) return integer ;
--
-- ToTransaction and FromTransaction for _max provided to support a
-- common methodology, conversions are not needed
function ToTransaction(A : std_logic_vector) return std_logic_vector_max ;
impure function ToTransaction(A : std_logic_vector ; Size : natural) return std_logic_vector_max ;
function ToTransaction(A : integer; Size : natural) return std_logic_vector_max ;
function FromTransaction (A: std_logic_vector_max) return std_logic_vector ;
impure function FromTransaction (A: std_logic_vector_max ; Size : natural) return std_logic_vector ;
function FromTransaction (A: std_logic_vector_max) return integer ;
-- return sum of values that /= type'left
-- No initializations required on ports, default of type'left is ok
function resolved_sum ( s : integer_vector ) return integer ;
subtype integer_sum is resolved_sum integer ;
subtype integer_vector_sum is (resolved_sum) integer_vector ;
type integer_vector_sum_c is array (natural range <>) of integer_sum ; -- for non VHDL-2008
function resolved_sum ( s : time_vector ) return time ;
subtype time_sum is resolved_sum time ;
subtype time_vector_sum is (resolved_sum) time_vector ;
type time_vector_sum_c is array (natural range <>) of time_sum ; -- for non VHDL-2008
function resolved_sum ( s : real_vector ) return real ;
subtype real_sum is resolved_sum real ;
subtype real_vector_sum is (resolved_sum) real_vector ;
type real_vector_sum_c is array (natural range <>) of real_sum ; -- for non VHDL-2008
-- resolved_weak
-- Special just for std_ulogic
-- No initializations required on ports, default of type'left is ok
function resolved_weak (s : std_ulogic_vector) return std_ulogic ; -- no init, type'left
subtype std_logic_weak is resolved_weak std_ulogic ;
subtype std_logic_vector_weak is (resolved_weak) std_ulogic_vector ;
-- legacy stuff
-- requires ports to be initialized to 0 in the appropriate type.
function resolved ( s : integer_vector ) return integer ;
subtype resolved_integer is resolved integer ;
function resolved ( s : time_vector ) return time ;
subtype resolved_time is resolved time ;
function resolved ( s : real_vector ) return real ;
subtype resolved_real is resolved real ;
function resolved (s : string) return character ; -- same as resolved_max
subtype resolved_character is resolved character ;
-- subtype resolved_string is (resolved) string ; -- subtype will replace type later
type resolved_string is array (positive range <>) of resolved_character; -- will change to subtype -- assert but no init
function resolved ( s : boolean_vector) return boolean ; --same as resolved_max
subtype resolved_boolean is resolved boolean ;
end package ResolutionPkg ;
package body ResolutionPkg is
--
-- ToTransaction and FromTransaction
-- Convert from Common types to their corresponding _max_c type
--
function Extend(A: std_logic_vector; Size : natural) return std_logic_vector is
variable extA : std_logic_vector(Size downto 1) := (others => '0') ;
begin
extA(A'length downto 1) := A ;
return extA ;
end function Extend ;
function Reduce(A: std_logic_vector; Size : natural) return std_logic_vector is
alias aA : std_logic_vector(A'length-1 downto 0) is A ;
begin
return aA(Size-1 downto 0) ;
end function Reduce ;
-- SafeResize - handles std_logic_vector as unsigned
impure function SafeResize(A: std_logic_vector; Size : natural) return std_logic_vector is
variable Result : std_logic_vector(Size-1 downto 0) := (others => '0') ;
alias aA : std_logic_vector(A'length-1 downto 0) is A ;
begin
if A'length <= Size then
-- Extend A
Result(A'length-1 downto 0) := aA ;
else
-- Reduce A and Error if any extra bits of A are a '1'
AlertIf((OR aA(A'length-1 downto Size) = '1'), "ToTransaction/FromTransaction, threw away a 1") ;
Result := aA(Size-1 downto 0) ;
end if ;
return Result ;
end function SafeResize ;
function ToTransaction(A : std_logic_vector) return std_logic_vector_max_c is
begin
return std_logic_vector_max_c(A) ;
end function ToTransaction ;
impure function ToTransaction(A : std_logic_vector ; Size : natural) return std_logic_vector_max_c is
begin
return std_logic_vector_max_c(SafeResize(A, Size)) ;
end function ToTransaction ;
function ToTransaction(A : integer; Size : natural) return std_logic_vector_max_c is
begin
return std_logic_vector_max_c(to_signed(A, Size)) ;
end function ToTransaction ;
function FromTransaction (A: std_logic_vector_max_c) return std_logic_vector is
begin
return std_logic_vector(A) ;
end function FromTransaction ;
impure function FromTransaction (A: std_logic_vector_max_c ; Size : natural) return std_logic_vector is
begin
return SafeResize(std_logic_vector(A), Size) ;
end function FromTransaction ;
function FromTransaction (A: std_logic_vector_max_c) return integer is
begin
return to_integer(signed(A)) ;
end function FromTransaction ;
----------------------
-- Support for _max provided to support a common methodology,
-- conversions are not needed
function ToTransaction(A : std_logic_vector) return std_logic_vector_max is
begin
return A ;
end function ToTransaction ;
impure function ToTransaction(A : std_logic_vector ; Size : natural) return std_logic_vector_max is
begin
return SafeResize(A, Size) ;
end function ToTransaction ;
function ToTransaction(A : integer; Size : natural) return std_logic_vector_max is
begin
return std_logic_vector_max(to_signed(A, Size)) ;
end function ToTransaction ;
function FromTransaction (A: std_logic_vector_max) return std_logic_vector is
begin
return A ;
end function FromTransaction ;
impure function FromTransaction (A: std_logic_vector_max ; Size : natural) return std_logic_vector is
begin
return SafeResize(A, Size) ;
end function FromTransaction ;
function FromTransaction (A: std_logic_vector_max) return integer is
begin
return to_integer(signed(A)) ;
end function FromTransaction ;
-- resolved_max
-- return maximum value. Assert FAILURE if more than 1 /= type'left
-- No initializations required on ports, default of type'left is ok
-- Optimized version is just the following:
-- ------------------------------------------------------------
-- function resolved_max ( s : <array_type> ) return <element_type> is
-- ------------------------------------------------------------
-- begin
-- return maximum(s) ;
-- end function resolved_max ;
------------------------------------------------------------
function resolved_max (s : std_ulogic_vector) return std_ulogic is
------------------------------------------------------------
begin
return maximum(s) ;
end function resolved_max ;
------------------------------------------------------------
function resolved_max ( s : bit_vector ) return bit is
------------------------------------------------------------
begin
return maximum(s) ;
end function resolved_max ;
------------------------------------------------------------
function resolved_max ( s : integer_vector ) return integer is
------------------------------------------------------------
begin
return maximum(s) ;
end function resolved_max ;
------------------------------------------------------------
function resolved_max ( s : time_vector ) return time is
------------------------------------------------------------
begin
return maximum(s) ;
end function resolved_max ;
------------------------------------------------------------
function resolved_max ( s : real_vector ) return real is
------------------------------------------------------------
begin
return maximum(s) ;
end function resolved_max ;
------------------------------------------------------------
function resolved_max ( s : string ) return character is
------------------------------------------------------------
begin
return maximum(s) ;
end function resolved_max ;
------------------------------------------------------------
function resolved_max ( s : boolean_vector) return boolean is
------------------------------------------------------------
begin
return maximum(s) ;
end function resolved_max ;
-- resolved_sum - appropriate for numeric types
-- return sum of values that /= type'left
-- No initializations required on ports, default of type'left is ok
------------------------------------------------------------
function resolved_sum ( s : integer_vector ) return integer is
------------------------------------------------------------
variable result : integer := 0 ;
begin
for i in s'RANGE loop
if s(i) /= integer'left then
result := s(i) + result;
end if ;
end loop ;
return result ;
end function resolved_sum ;
------------------------------------------------------------
function resolved_sum ( s : time_vector ) return time is
------------------------------------------------------------
variable result : time := 0 sec ;
begin
for i in s'RANGE loop
if s(i) /= time'left then
result := s(i) + result;
end if ;
end loop ;
return result ;
end function resolved_sum ;
------------------------------------------------------------
function resolved_sum ( s : real_vector ) return real is
------------------------------------------------------------
variable result : real := 0.0 ;
begin
for i in s'RANGE loop
if s(i) /= real'left then
result := s(i) + result;
end if ;
end loop ;
return result ;
end function resolved_sum ;
-- resolved_weak
-- Special just for std_ulogic
-- No initializations required on ports, default of type'left is ok
type stdlogic_table is array(STD_ULOGIC, STD_ULOGIC) of STD_ULOGIC;
constant weak_resolution_table : stdlogic_table := (
-- Resolution order: Z < U < W < X < - < L < H < 0 < 1
-- ---------------------------------------------------------
-- | U X 0 1 Z W L H - | |
-- ---------------------------------------------------------
('U', 'X', '0', '1', 'U', 'W', 'L', 'H', '-'), -- | U |
('X', 'X', '0', '1', 'X', 'X', 'L', 'H', '-'), -- | X |
('0', '0', '0', '1', '0', '0', '0', '0', '0'), -- | 0 |
('1', '1', '1', '1', '1', '1', '1', '1', '1'), -- | 1 |
('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-'), -- | Z |
('W', 'X', '0', '1', 'W', 'W', 'L', 'H', '-'), -- | W |
('L', 'L', '0', '1', 'L', 'L', 'L', 'H', 'L'), -- | L |
('H', 'H', '0', '1', 'H', 'H', 'W', 'H', 'H'), -- | H |
('-', '-', '0', '1', '-', '-', 'L', 'H', '-') -- | - |
);
------------------------------------------------------------
function resolved_weak (s : std_ulogic_vector) return std_ulogic is
------------------------------------------------------------
variable result : std_ulogic := 'Z' ;
begin
for i in s'RANGE loop
result := weak_resolution_table(result, s(i)) ;
end loop ;
return result ;
end function resolved_weak ;
-- legacy stuff.
-- requires ports to be initialized to 0 in the appropriate type.
------------------------------------------------------------
function resolved ( s : integer_vector ) return integer is
-- requires interface to be initialized to 0
------------------------------------------------------------
variable result : integer := 0 ;
variable failed : boolean := FALSE ;
begin
for i in s'RANGE loop
if s(i) /= 0 then
failed := failed or (result /= 0) ;
result := maximum(s(i),result);
end if ;
end loop ;
assert not failed report "ResolutionPkg.resolved: multiple drivers on integer" severity MULTIPLE_DRIVER_SEVERITY ;
-- AlertIf(OSVVM_ALERTLOG_ID, failed, "ResolutionPkg.resolved: multiple drivers on integer") ;
return result ;
end function resolved ;
------------------------------------------------------------
function resolved ( s : time_vector ) return time is
-- requires interface to be initialized to 0 ns
------------------------------------------------------------
variable result : time := 0 ns ;
variable failed : boolean := FALSE ;
begin
for i in s'RANGE loop
if s(i) > 0 ns then
failed := failed or (result /= 0 ns) ;
result := maximum(s(i),result);
end if ;
end loop ;
assert not failed report "ResolutionPkg.resolved: multiple drivers on time" severity MULTIPLE_DRIVER_SEVERITY ;
-- AlertIf(OSVVM_ALERTLOG_ID, failed, "ResolutionPkg.resolved: multiple drivers on time") ;
return result ;
end function resolved ;
------------------------------------------------------------
function resolved ( s : real_vector ) return real is
-- requires interface to be initialized to 0.0
------------------------------------------------------------
variable result : real := 0.0 ;
variable failed : boolean := FALSE ;
begin
for i in s'RANGE loop
if s(i) /= 0.0 then
failed := failed or (result /= 0.0) ;
result := maximum(s(i),result);
end if ;
end loop ;
assert not failed report "ResolutionPkg.resolved: multiple drivers on real" severity MULTIPLE_DRIVER_SEVERITY ;
-- AlertIf(OSVVM_ALERTLOG_ID, failed, "ResolutionPkg.resolved: multiple drivers on real") ;
return result ;
end function resolved ;
------------------------------------------------------------
function resolved (s : string) return character is
-- same as resolved_max
------------------------------------------------------------
variable result : character := NUL ;
variable failed : boolean := FALSE ;
begin
for i in s'RANGE loop
if s(i) /= NUL then
failed := failed or (result /= NUL) ;
result := maximum(result, s(i)) ;
end if ;
end loop ;
assert not failed report "ResolutionPkg.resolved: multiple drivers on character" severity MULTIPLE_DRIVER_SEVERITY ;
-- AlertIf(OSVVM_ALERTLOG_ID, failed, "ResolutionPkg.resolved: multiple drivers on character") ;
return result ;
end function resolved ;
------------------------------------------------------------
function resolved ( s : boolean_vector) return boolean is
-- same as resolved_max
------------------------------------------------------------
variable result : boolean := FALSE ;
variable failed : boolean := FALSE ;
begin
for i in s'RANGE loop
if s(i) then
failed := failed or result ;
result := TRUE ;
end if ;
end loop ;
assert not failed report "ResolutionPkg.resolved: multiple drivers on boolean" severity MULTIPLE_DRIVER_SEVERITY ;
-- AlertIf(OSVVM_ALERTLOG_ID, failed, "ResolutionPkg.resolved: multiple drivers on boolean") ;
return result ;
end function resolved ;
end package body ResolutionPkg ;
|
artistic-2.0
|
mariobarbareschi/vhdl_ci
|
testbench/mux4_1/mux4_1_testbench.vhd
|
1
|
1321
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use std.textio.all;
-- entity declaration for your testbench. Dont declare any ports here
ENTITY mux4_1_testbench IS
END mux4_1_testbench;
ARCHITECTURE behavioral OF mux4_1_testbench IS
-- Component Declaration for the Unit Under Test (UUT)
component mux4_1 is
Port ( SEL : in STD_LOGIC_VECTOR(1 downto 0);
A : in STD_LOGIC_VECTOR(3 downto 0);
X : out STD_LOGIC
);
end component;
--declare inputs and initialize them
signal SEL : STD_LOGIC_VECTOR(1 downto 0) := (others => '0');
signal A : STD_LOGIC_VECTOR(3 downto 0) := (others => '0');
--declare outputs and initialize them
signal X : STD_LOGIC := '0';
begin
-- Instantiate the Unit Under Test (UUT)
-- TODO
uut: mux4_1 port map(
SEL => SEL,
A => A,
X => X
);
-- Stimulus process
stim_proc: process
variable l : line;
begin
write (l, String'("Testbench for mux4_1"));
writeline (output, l);
wait for 10 ns;
SEL <= "01";
A <= x"A";
wait for 10 ns;
SEL <= "10";
wait for 10 ns;
SEL <= "11";
wait for 10 ns;
assert (X = '0') report "X should be 1" severity error;
A <= x"0";
wait for 10 ns;
wait;
end process;
END behavioral;
|
agpl-3.0
|
aggroskater/ee4321-vhdl-digital-design
|
Project-4-4bit-ALU/lib/shift_rotate/shift_rotate_testBench.vhd
|
1
|
3818
|
--READ THIS LINK:
--http://homepage.ntlworld.com/jonathan.deboynepollard/FGA/bit-shifts-in-vhdl.html
--Important bit:
--Arithmetic and logical shifts and rotates are done with
--functions in VHDL, not operators.
--
--The problem with the operators -- sll, sla, srl, sra, rol, and rar, -- is
--that they were an afterthought, weren't specified correctly, and have been
--removed from IEEE 1076.
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_unsigned.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY shift_rotate_testBench IS
END shift_rotate_testBench;
ARCHITECTURE behavior OF shift_rotate_testBench IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT shift_rotate
PORT(
A : IN std_logic_vector(3 downto 0);
B : IN std_logic_vector(3 downto 0);
op : IN std_logic_vector(2 downto 0);
R : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
--Inputs
signal A : std_logic_vector(3 downto 0) := (others => '0');
signal B : std_logic_vector(3 downto 0) := (others => '0');
signal op : std_logic_vector(2 downto 0) := (others => '0');
--Outputs
signal R : std_logic_vector(3 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
--constant <clock>_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: shift_rotate PORT MAP (
A => A,
B => B,
op => op,
R => R
);
-- Clock process definitions
--<clock>_process :process
--begin
-- <clock> <= '0';
-- wait for <clock>_period/2;
-- <clock> <= '1';
-- wait for <clock>_period/2;
--end process;
-- Stimulus process
stim_proc: process
variable count : integer :=0;
begin
-- TEST Rotate Left
A <= "0000";
B <= "0000";
op <= "000";
wait for 1 ns;
for i in 0 to 15 loop
for j in 0 to 15 loop
wait for 1 ns;
if NOT(R = std_logic_vector(rotate_left(unsigned(A),to_integer(unsigned(B)))))
then
assert R = std_logic_vector(rotate_left(unsigned(A),to_integer(unsigned(B))))
report "R = A rol B should have been " &
integer'image(to_integer(rotate_left(unsigned(A),to_integer(unsigned(B))))) &
" with A=" & integer'image(to_integer(unsigned(A))) &
" and B=" & integer'image(to_integer(unsigned(B))) &
" but instead R was " & integer'image(to_integer(unsigned(R)))
severity ERROR;
count := count + 1;
else
--nada
end if;
B <= B + "0001";
end loop;
A <= A + "0001";
end loop;
-- TEST Rotate Right
A <= "0000";
B <= "0000";
op <= "001";
wait for 1 ns;
for i in 0 to 15 loop
for j in 0 to 15 loop
wait for 1 ns;
if NOT(R = std_logic_vector(rotate_right(unsigned(A),to_integer(unsigned(B)))))
then
assert R = std_logic_vector(rotate_right(unsigned(A),to_integer(unsigned(B))))
report "R = A rol B should have been " &
integer'image(to_integer(rotate_right(unsigned(A),to_integer(unsigned(B))))) &
" with A=" & integer'image(to_integer(unsigned(A))) &
" and B=" & integer'image(to_integer(unsigned(B))) &
" but instead R was " & integer'image(to_integer(unsigned(R)))
severity ERROR;
count := count + 1;
else
--nada
end if;
B <= B + "0001";
end loop;
A <= A + "0001";
end loop;
--testing done
report "TEST FINISHED.";
report "ERROR COUNT: " & integer'image(count);
wait;
end process;
END;
|
agpl-3.0
|
aggroskater/ee4321-vhdl-digital-design
|
Exam-1-Lab/rca_4_bit.vhd
|
1
|
1879
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:15:26 02/12/2014
-- Design Name:
-- Module Name: rca_4_bit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity rca_4_bit is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
Cin : in STD_LOGIC;
Sum : out STD_LOGIC_VECTOR (3 downto 0);
Cout : out STD_LOGIC);
end rca_4_bit;
architecture Behavioral of rca_4_bit is
signal c0, c1, c2 : std_logic:='0';
signal b0, b1, b2, b3 : std_logic:='0';
begin
--add/sub control; If Cin is high, then we are subtracting, and these
--muxes output the inverse of B. If Cin is low, then we are adding, and
--these muxes just pass B.
mux0: entity work.mux2 port map (B(0),NOT(B(0)),Cin,b0);
mux1: entity work.mux2 port map (B(1),NOT(B(1)),Cin,b1);
mux2: entity work.mux2 port map (B(2),NOT(B(2)),Cin,b2);
mux3: entity work.mux2 port map (B(3),NOT(B(3)),Cin,b3);
FA0: entity work.full_adder_1_bit port map (A(0),b0,Cin,c0,Sum(0));
FA1: entity work.full_adder_1_bit port map (A(1),b1,c0,c1,Sum(1));
FA2: entity work.full_adder_1_bit port map (A(2),b2,c1,c2,Sum(2));
FA3: entity work.full_adder_1_bit port map (A(3),b3,c2,Cout,Sum(3));
end Behavioral;
|
agpl-3.0
|
aggroskater/ee4321-vhdl-digital-design
|
Project-3-4bit-CLA/cl_logic.vhd
|
2
|
2085
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:41:32 02/12/2014
-- Design Name:
-- Module Name: full_adder_1_bit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity cl_logic is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
Cin : in STD_LOGIC;
Cin1 : out STD_LOGIC;
Cin2 : out STD_LOGIC;
Cin3 : out STD_LOGIC;
Cout : out STD_LOGIC);
end cl_logic;
architecture Behavioral of cl_logic is
begin
-- Cin1 = G_0 + P_0 * Cin0
Cin1 <= ( A(0) AND B(0) )
OR ( (Cin)
AND (A(0) OR B(0)) );
-- Cin2 = G_1 + P_1 * Cin1
Cin2 <= ( A(1) AND B(1) )
OR ( (A(0) AND B(0))
AND (A(1) OR B(1)) )
OR ( (Cin)
AND (A(0) OR B(0))
AND (A(1) OR B(1)) );
-- Cin3 = G_2 + P_2 * Cin2
Cin3 <= ( A(2) AND B(2) )
OR ( (A(1) AND B(1))
AND (A(2) OR B(2)) )
OR ( (A(0) AND B(0))
AND (A(1) OR B(1))
AND (A(2) OR B(2)) )
OR ( (Cin)
AND (A(0) OR B(0))
AND (A(1) OR B(1))
AND (A(2) OR B(2)) );
-- Cout = G_3 + P_3 * Cin3
Cout <= ( A(3) AND B(3) )
OR ( (A(2) AND B(2))
AND (A(3) OR B(3)) )
OR ( (A(1) AND B(1))
AND (A(2) OR B(2))
AND (A(3) OR B(3)) )
OR ( (A(0) AND B(0))
AND (A(1) OR B(1))
AND (A(2) OR B(2))
AND (A(3) OR B(3)) )
OR ( (Cin)
AND (A(0) OR B(0))
AND (A(1) OR B(1))
AND (A(2) OR B(2))
AND (A(3) OR B(3)) );
end Behavioral;
|
agpl-3.0
|
dominikstanojevic/InteraktivniVHDL
|
testovi/sklopI.vhdl
|
1
|
255
|
entity sklopI is port (
a,b: in std_logic;
f, test: out std_logic);
end sklopI;
architecture pon of sklopI is
signal pomocni: std_logic;
begin
pomocni <= a and b after 3 s;
f <= pomocni after 100 ms;
test <= pomocni after 2 s;
end pon;
|
mpl-2.0
|
mpwillson/mal
|
vhdl/step9_try.vhdl
|
11
|
16609
|
entity step9_try is
end entity step9_try;
library STD;
use STD.textio.all;
library WORK;
use WORK.pkg_readline.all;
use WORK.types.all;
use WORK.printer.all;
use WORK.reader.all;
use WORK.env.all;
use WORK.core.all;
architecture test of step9_try is
shared variable repl_env: env_ptr;
procedure mal_READ(str: in string; ast: out mal_val_ptr; err: out mal_val_ptr) is
begin
read_str(str, ast, err);
end procedure mal_READ;
procedure is_pair(ast: inout mal_val_ptr; pair: out boolean) is
begin
pair := is_sequential_type(ast.val_type) and ast.seq_val'length > 0;
end procedure is_pair;
procedure quasiquote(ast: inout mal_val_ptr; result: out mal_val_ptr) is
variable ast_pair, a0_pair: boolean;
variable seq: mal_seq_ptr;
variable a0, rest: mal_val_ptr;
begin
is_pair(ast, ast_pair);
if not ast_pair then
seq := new mal_seq(0 to 1);
new_symbol("quote", seq(0));
seq(1) := ast;
new_seq_obj(mal_list, seq, result);
return;
end if;
a0 := ast.seq_val(0);
if a0.val_type = mal_symbol and a0.string_val.all = "unquote" then
result := ast.seq_val(1);
else
is_pair(a0, a0_pair);
if a0_pair and a0.seq_val(0).val_type = mal_symbol and a0.seq_val(0).string_val.all = "splice-unquote" then
seq := new mal_seq(0 to 2);
new_symbol("concat", seq(0));
seq(1) := a0.seq_val(1);
seq_drop_prefix(ast, 1, rest);
quasiquote(rest, seq(2));
new_seq_obj(mal_list, seq, result);
else
seq := new mal_seq(0 to 2);
new_symbol("cons", seq(0));
quasiquote(a0, seq(1));
seq_drop_prefix(ast, 1, rest);
quasiquote(rest, seq(2));
new_seq_obj(mal_list, seq, result);
end if;
end if;
end procedure quasiquote;
-- Forward declaration
procedure EVAL(in_ast: inout mal_val_ptr; in_env: inout env_ptr; result: out mal_val_ptr; err: out mal_val_ptr);
procedure apply_func(fn: inout mal_val_ptr; args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr);
procedure is_macro_call(ast: inout mal_val_ptr; env: inout env_ptr; is_macro: out boolean) is
variable f, env_err: mal_val_ptr;
begin
is_macro := false;
if ast.val_type = mal_list and
ast.seq_val'length > 0 and
ast.seq_val(0).val_type = mal_symbol then
env_get(env, ast.seq_val(0), f, env_err);
if env_err = null and f /= null and
f.val_type = mal_fn and f.func_val.f_is_macro then
is_macro := true;
end if;
end if;
end procedure is_macro_call;
procedure macroexpand(in_ast: inout mal_val_ptr; env: inout env_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable ast, macro_fn, call_args, macro_err: mal_val_ptr;
variable is_macro: boolean;
begin
ast := in_ast;
is_macro_call(ast, env, is_macro);
while is_macro loop
env_get(env, ast.seq_val(0), macro_fn, macro_err);
seq_drop_prefix(ast, 1, call_args);
apply_func(macro_fn, call_args, ast, macro_err);
if macro_err /= null then
err := macro_err;
return;
end if;
is_macro_call(ast, env, is_macro);
end loop;
result := ast;
end procedure macroexpand;
procedure fn_eval(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
begin
EVAL(args.seq_val(0), repl_env, result, err);
end procedure fn_eval;
procedure fn_swap(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable atom: mal_val_ptr := args.seq_val(0);
variable fn: mal_val_ptr := args.seq_val(1);
variable call_args_seq: mal_seq_ptr;
variable call_args, eval_res, sub_err: mal_val_ptr;
begin
call_args_seq := new mal_seq(0 to args.seq_val'length - 2);
call_args_seq(0) := atom.seq_val(0);
call_args_seq(1 to call_args_seq'length - 1) := args.seq_val(2 to args.seq_val'length - 1);
new_seq_obj(mal_list, call_args_seq, call_args);
apply_func(fn, call_args, eval_res, sub_err);
if sub_err /= null then
err := sub_err;
return;
end if;
atom.seq_val(0) := eval_res;
result := eval_res;
end procedure fn_swap;
procedure fn_apply(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable fn: mal_val_ptr := args.seq_val(0);
variable rest: mal_val_ptr;
variable mid_args_count, rest_args_count: integer;
variable call_args: mal_val_ptr;
variable call_args_seq: mal_seq_ptr;
begin
rest := args.seq_val(args.seq_val'high);
mid_args_count := args.seq_val'length - 2;
rest_args_count := rest.seq_val'length;
call_args_seq := new mal_seq(0 to mid_args_count + rest_args_count - 1);
call_args_seq(0 to mid_args_count - 1) := args.seq_val(1 to args.seq_val'length - 2);
call_args_seq(mid_args_count to call_args_seq'high) := rest.seq_val(rest.seq_val'range);
new_seq_obj(mal_list, call_args_seq, call_args);
apply_func(fn, call_args, result, err);
end procedure fn_apply;
procedure fn_map(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable fn: mal_val_ptr := args.seq_val(0);
variable lst: mal_val_ptr := args.seq_val(1);
variable call_args, sub_err: mal_val_ptr;
variable new_seq: mal_seq_ptr;
variable i: integer;
begin
new_seq := new mal_seq(lst.seq_val'range); -- (0 to lst.seq_val.length - 1);
for i in new_seq'range loop
new_one_element_list(lst.seq_val(i), call_args);
apply_func(fn, call_args, new_seq(i), sub_err);
if sub_err /= null then
err := sub_err;
return;
end if;
end loop;
new_seq_obj(mal_list, new_seq, result);
end procedure fn_map;
procedure apply_native_func(func_sym: inout mal_val_ptr; args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
begin
if func_sym.string_val.all = "eval" then
fn_eval(args, result, err);
elsif func_sym.string_val.all = "swap!" then
fn_swap(args, result, err);
elsif func_sym.string_val.all = "apply" then
fn_apply(args, result, err);
elsif func_sym.string_val.all = "map" then
fn_map(args, result, err);
else
eval_native_func(func_sym, args, result, err);
end if;
end procedure apply_native_func;
procedure apply_func(fn: inout mal_val_ptr; args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable fn_env: env_ptr;
begin
case fn.val_type is
when mal_nativefn =>
apply_native_func(fn, args, result, err);
when mal_fn =>
new_env(fn_env, fn.func_val.f_env, fn.func_val.f_args, args);
EVAL(fn.func_val.f_body, fn_env, result, err);
when others =>
new_string("not a function", err);
return;
end case;
end procedure apply_func;
procedure eval_ast_seq(ast_seq: inout mal_seq_ptr; env: inout env_ptr; result: inout mal_seq_ptr; err: out mal_val_ptr) is
variable eval_err: mal_val_ptr;
begin
result := new mal_seq(0 to ast_seq'length - 1);
for i in result'range loop
EVAL(ast_seq(i), env, result(i), eval_err);
if eval_err /= null then
err := eval_err;
return;
end if;
end loop;
end procedure eval_ast_seq;
procedure eval_ast(ast: inout mal_val_ptr; env: inout env_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable key, val, eval_err, env_err: mal_val_ptr;
variable new_seq: mal_seq_ptr;
variable i: integer;
begin
case ast.val_type is
when mal_symbol =>
env_get(env, ast, val, env_err);
if env_err /= null then
err := env_err;
return;
end if;
result := val;
return;
when mal_list | mal_vector | mal_hashmap =>
eval_ast_seq(ast.seq_val, env, new_seq, eval_err);
if eval_err /= null then
err := eval_err;
return;
end if;
new_seq_obj(ast.val_type, new_seq, result);
return;
when others =>
result := ast;
return;
end case;
end procedure eval_ast;
procedure EVAL(in_ast: inout mal_val_ptr; in_env: inout env_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable i: integer;
variable ast, evaled_ast, a0, call_args, val, vars, sub_err, fn: mal_val_ptr;
variable env, let_env, catch_env, fn_env: env_ptr;
begin
ast := in_ast;
env := in_env;
loop
if ast.val_type /= mal_list then
eval_ast(ast, env, result, err);
return;
end if;
macroexpand(ast, env, ast, sub_err);
if sub_err /= null then
err := sub_err;
return;
end if;
if ast.val_type /= mal_list then
eval_ast(ast, env, result, err);
return;
end if;
if ast.seq_val'length = 0 then
result := ast;
return;
end if;
a0 := ast.seq_val(0);
if a0.val_type = mal_symbol then
if a0.string_val.all = "def!" then
EVAL(ast.seq_val(2), env, val, sub_err);
if sub_err /= null then
err := sub_err;
return;
end if;
env_set(env, ast.seq_val(1), val);
result := val;
return;
elsif a0.string_val.all = "let*" then
vars := ast.seq_val(1);
new_env(let_env, env);
i := 0;
while i < vars.seq_val'length loop
EVAL(vars.seq_val(i + 1), let_env, val, sub_err);
if sub_err /= null then
err := sub_err;
return;
end if;
env_set(let_env, vars.seq_val(i), val);
i := i + 2;
end loop;
env := let_env;
ast := ast.seq_val(2);
next; -- TCO
elsif a0.string_val.all = "quote" then
result := ast.seq_val(1);
return;
elsif a0.string_val.all = "quasiquote" then
quasiquote(ast.seq_val(1), ast);
next; -- TCO
elsif a0.string_val.all = "defmacro!" then
EVAL(ast.seq_val(2), env, val, sub_err);
if sub_err /= null then
err := sub_err;
return;
end if;
val.func_val.f_is_macro := true;
env_set(env, ast.seq_val(1), val);
result := val;
return;
elsif a0.string_val.all = "macroexpand" then
macroexpand(ast.seq_val(1), env, result, err);
return;
elsif a0.string_val.all = "try*" then
EVAL(ast.seq_val(1), env, result, sub_err);
if sub_err /= null then
if ast.seq_val'length > 2 and
ast.seq_val(2).val_type = mal_list and
ast.seq_val(2).seq_val(0).val_type = mal_symbol and
ast.seq_val(2).seq_val(0).string_val.all = "catch*" then
new_one_element_list(ast.seq_val(2).seq_val(1), vars);
new_one_element_list(sub_err, call_args);
new_env(catch_env, env, vars, call_args);
EVAL(ast.seq_val(2).seq_val(2), catch_env, result, err);
else
new_nil(result);
end if;
end if;
return;
elsif a0.string_val.all = "do" then
for i in 1 to ast.seq_val'high - 1 loop
EVAL(ast.seq_val(i), env, result, sub_err);
if sub_err /= null then
err := sub_err;
return;
end if;
end loop;
ast := ast.seq_val(ast.seq_val'high);
next; -- TCO
elsif a0.string_val.all = "if" then
EVAL(ast.seq_val(1), env, val, sub_err);
if sub_err /= null then
err := sub_err;
return;
end if;
if val.val_type = mal_nil or val.val_type = mal_false then
if ast.seq_val'length > 3 then
ast := ast.seq_val(3);
else
new_nil(result);
return;
end if;
else
ast := ast.seq_val(2);
end if;
next; -- TCO
elsif a0.string_val.all = "fn*" then
new_fn(ast.seq_val(2), ast.seq_val(1), env, result);
return;
end if;
end if;
eval_ast(ast, env, evaled_ast, sub_err);
if sub_err /= null then
err := sub_err;
return;
end if;
seq_drop_prefix(evaled_ast, 1, call_args);
fn := evaled_ast.seq_val(0);
case fn.val_type is
when mal_nativefn =>
apply_native_func(fn, call_args, result, err);
return;
when mal_fn =>
new_env(fn_env, fn.func_val.f_env, fn.func_val.f_args, call_args);
env := fn_env;
ast := fn.func_val.f_body;
next; -- TCO
when others =>
new_string("not a function", err);
return;
end case;
end loop;
end procedure EVAL;
procedure mal_PRINT(exp: inout mal_val_ptr; result: out line) is
begin
pr_str(exp, true, result);
end procedure mal_PRINT;
procedure RE(str: in string; env: inout env_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable ast, read_err: mal_val_ptr;
begin
mal_READ(str, ast, read_err);
if read_err /= null then
err := read_err;
result := null;
return;
end if;
if ast = null then
result := null;
return;
end if;
EVAL(ast, env, result, err);
end procedure RE;
procedure REP(str: in string; env: inout env_ptr; result: out line; err: out mal_val_ptr) is
variable eval_res, eval_err: mal_val_ptr;
begin
RE(str, env, eval_res, eval_err);
if eval_err /= null then
err := eval_err;
result := null;
return;
end if;
mal_PRINT(eval_res, result);
end procedure REP;
procedure set_argv(e: inout env_ptr; program_file: inout line) is
variable argv_var_name: string(1 to 6) := "*ARGV*";
variable argv_sym, argv_list: mal_val_ptr;
file f: text;
variable status: file_open_status;
variable one_line: line;
variable seq: mal_seq_ptr;
variable element: mal_val_ptr;
begin
program_file := null;
seq := new mal_seq(0 to -1);
file_open(status, f, external_name => "vhdl_argv.tmp", open_kind => read_mode);
if status = open_ok then
if not endfile(f) then
readline(f, program_file);
while not endfile(f) loop
readline(f, one_line);
new_string(one_line.all, element);
seq := new mal_seq'(seq.all & element);
end loop;
end if;
file_close(f);
end if;
new_seq_obj(mal_list, seq, argv_list);
new_symbol(argv_var_name, argv_sym);
env_set(e, argv_sym, argv_list);
end procedure set_argv;
procedure repl is
variable is_eof: boolean;
variable program_file, input_line, result: line;
variable eval_sym, eval_fn, dummy_val, err: mal_val_ptr;
variable outer: env_ptr;
variable eval_func_name: string(1 to 4) := "eval";
begin
outer := null;
new_env(repl_env, outer);
-- core.EXT: defined using VHDL (see core.vhdl)
define_core_functions(repl_env);
new_symbol(eval_func_name, eval_sym);
new_nativefn(eval_func_name, eval_fn);
env_set(repl_env, eval_sym, eval_fn);
set_argv(repl_env, program_file);
-- core.mal: defined using the language itself
RE("(def! not (fn* (a) (if a false true)))", repl_env, dummy_val, err);
RE("(def! load-file (fn* (f) (eval (read-string (str " & '"' & "(do " & '"' & " (slurp f) " & '"' & ")" & '"' & ")))))", repl_env, dummy_val, err);
RE("(defmacro! cond (fn* (& xs) (if (> (count xs) 0) (list 'if (first xs) (if (> (count xs) 1) (nth xs 1) (throw " & '"' & "odd number of forms to cond" & '"' & ")) (cons 'cond (rest (rest xs)))))))", repl_env, dummy_val, err);
RE("(defmacro! or (fn* (& xs) (if (empty? xs) nil (if (= 1 (count xs)) (first xs) `(let* (or_FIXME ~(first xs)) (if or_FIXME or_FIXME (or ~@(rest xs))))))))", repl_env, dummy_val, err);
if program_file /= null then
REP("(load-file " & '"' & program_file.all & '"' & ")", repl_env, result, err);
return;
end if;
loop
mal_readline("user> ", is_eof, input_line);
exit when is_eof;
next when input_line'length = 0;
REP(input_line.all, repl_env, result, err);
if err /= null then
pr_str(err, false, result);
result := new string'("Error: " & result.all);
end if;
if result /= null then
mal_printline(result.all);
end if;
deallocate(result);
deallocate(err);
end loop;
mal_printline("");
end procedure repl;
begin
repl;
end architecture test;
|
mpl-2.0
|
mpwillson/mal
|
vhdl/core.vhdl
|
8
|
25023
|
library STD;
use STD.textio.all;
library WORK;
use WORK.types.all;
use WORK.env.all;
use WORK.reader.all;
use WORK.printer.all;
use WORK.pkg_readline.all;
package core is
procedure eval_native_func(func_sym: inout mal_val_ptr; args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr);
procedure define_core_functions(e: inout env_ptr);
end package core;
package body core is
procedure fn_equal(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable is_equal: boolean;
begin
equal_q(args.seq_val(0), args.seq_val(1), is_equal);
new_boolean(is_equal, result);
end procedure fn_equal;
procedure fn_throw(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
begin
err := args.seq_val(0);
end procedure fn_throw;
procedure fn_nil_q(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
begin
new_boolean(args.seq_val(0).val_type = mal_nil, result);
end procedure fn_nil_q;
procedure fn_true_q(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
begin
new_boolean(args.seq_val(0).val_type = mal_true, result);
end procedure fn_true_q;
procedure fn_false_q(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
begin
new_boolean(args.seq_val(0).val_type = mal_false, result);
end procedure fn_false_q;
procedure fn_string_q(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
begin
new_boolean(args.seq_val(0).val_type = mal_string, result);
end procedure fn_string_q;
procedure fn_symbol(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
begin
new_symbol(args.seq_val(0).string_val, result);
end procedure fn_symbol;
procedure fn_symbol_q(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
begin
new_boolean(args.seq_val(0).val_type = mal_symbol, result);
end procedure fn_symbol_q;
procedure fn_keyword(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
begin
new_keyword(args.seq_val(0).string_val, result);
end procedure fn_keyword;
procedure fn_keyword_q(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
begin
new_boolean(args.seq_val(0).val_type = mal_keyword, result);
end procedure fn_keyword_q;
procedure fn_pr_str(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable s: line;
begin
pr_seq("", "", " ", args.seq_val, true, s);
new_string(s, result);
end procedure fn_pr_str;
procedure fn_str(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable s: line;
begin
pr_seq("", "", "", args.seq_val, false, s);
new_string(s, result);
end procedure fn_str;
procedure fn_prn(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable s: line;
begin
pr_seq("", "", " ", args.seq_val, true, s);
mal_printline(s.all);
new_nil(result);
end procedure fn_prn;
procedure fn_println(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable s: line;
begin
pr_seq("", "", " ", args.seq_val, false, s);
mal_printline(s.all);
new_nil(result);
end procedure fn_println;
procedure fn_read_string(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable ast: mal_val_ptr;
begin
read_str(args.seq_val(0).string_val.all, ast, err);
if ast = null then
new_nil(result);
else
result := ast;
end if;
end procedure fn_read_string;
procedure fn_readline(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable input_line: line;
variable is_eof: boolean;
begin
mal_readline(args.seq_val(0).string_val.all, is_eof, input_line);
if is_eof then
new_nil(result);
else
new_string(input_line, result);
end if;
end procedure fn_readline;
procedure fn_slurp(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
file f: text;
variable status: file_open_status;
variable save_content, content, one_line: line;
begin
file_open(status, f, external_name => args.seq_val(0).string_val.all, open_kind => read_mode);
if status = open_ok then
content := new string'("");
while not endfile(f) loop
readline(f, one_line);
save_content := content;
content := new string'(save_content.all & one_line.all & LF);
deallocate(save_content);
end loop;
file_close(f);
new_string(content, result);
else
new_string("Error opening file", err);
end if;
end procedure fn_slurp;
procedure fn_lt(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
begin
new_boolean(args.seq_val(0).number_val < args.seq_val(1).number_val, result);
end procedure fn_lt;
procedure fn_lte(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
begin
new_boolean(args.seq_val(0).number_val <= args.seq_val(1).number_val, result);
end procedure fn_lte;
procedure fn_gt(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
begin
new_boolean(args.seq_val(0).number_val > args.seq_val(1).number_val, result);
end procedure fn_gt;
procedure fn_gte(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
begin
new_boolean(args.seq_val(0).number_val >= args.seq_val(1).number_val, result);
end procedure fn_gte;
procedure fn_add(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
begin
new_number(args.seq_val(0).number_val + args.seq_val(1).number_val, result);
end procedure fn_add;
procedure fn_sub(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
begin
new_number(args.seq_val(0).number_val - args.seq_val(1).number_val, result);
end procedure fn_sub;
procedure fn_mul(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
begin
new_number(args.seq_val(0).number_val * args.seq_val(1).number_val, result);
end procedure fn_mul;
procedure fn_div(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
begin
new_number(args.seq_val(0).number_val / args.seq_val(1).number_val, result);
end procedure fn_div;
-- Define physical types (c_seconds64, c_microseconds64) because these are
-- represented as 64-bit words when passed to C functions
type c_seconds64 is range 0 to 1E16
units
c_sec;
end units c_seconds64;
type c_microseconds64 is range 0 to 1E6
units
c_usec;
end units c_microseconds64;
type c_timeval is record
tv_sec: c_seconds64;
tv_usec: c_microseconds64;
end record c_timeval;
-- Leave enough room for two 64-bit words
type c_timezone is record
dummy_1: c_seconds64;
dummy_2: c_seconds64;
end record c_timezone;
function gettimeofday(tv: c_timeval; tz: c_timezone) return integer;
attribute foreign of gettimeofday: function is "VHPIDIRECT gettimeofday";
function gettimeofday(tv: c_timeval; tz: c_timezone) return integer is
begin
assert false severity failure;
end function gettimeofday;
-- Returns the number of milliseconds since 2000-01-01 00:00:00 UTC because
-- a standard VHDL integer is 32-bit and therefore cannot hold the number of
-- milliseconds since 1970-01-01.
procedure fn_time_ms(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable tv: c_timeval;
variable dummy: c_timezone;
variable rc: integer;
constant utc_2000_01_01: c_seconds64 := 946684800 c_sec; -- UNIX time at 2000-01-01 00:00:00 UTC
begin
rc := gettimeofday(tv, dummy);
new_number(((tv.tv_sec - utc_2000_01_01) / 1 c_sec) * 1000 + (tv.tv_usec / 1000 c_usec), result);
end procedure fn_time_ms;
procedure fn_list(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
begin
result := args;
end procedure fn_list;
procedure fn_list_q(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
begin
new_boolean(args.seq_val(0).val_type = mal_list, result);
end procedure fn_list_q;
procedure fn_vector(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
begin
args.val_type := mal_vector;
result := args;
end procedure fn_vector;
procedure fn_vector_q(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
begin
new_boolean(args.seq_val(0).val_type = mal_vector, result);
end procedure fn_vector_q;
procedure fn_hash_map(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
begin
args.val_type := mal_hashmap;
result := args;
end procedure fn_hash_map;
procedure fn_map_q(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
begin
new_boolean(args.seq_val(0).val_type = mal_hashmap, result);
end procedure fn_map_q;
procedure fn_assoc(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable new_hashmap: mal_val_ptr;
variable i: integer;
begin
hashmap_copy(args.seq_val(0), new_hashmap);
i := 1;
while i < args.seq_val'length loop
hashmap_put(new_hashmap, args.seq_val(i), args.seq_val(i + 1));
i := i + 2;
end loop;
result := new_hashmap;
end procedure fn_assoc;
procedure fn_dissoc(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable new_hashmap: mal_val_ptr;
variable i: integer;
begin
hashmap_copy(args.seq_val(0), new_hashmap);
for i in 1 to args.seq_val'high loop
hashmap_delete(new_hashmap, args.seq_val(i));
end loop;
result := new_hashmap;
end procedure fn_dissoc;
procedure fn_get(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable a0: mal_val_ptr := args.seq_val(0);
variable a1: mal_val_ptr := args.seq_val(1);
variable val: mal_val_ptr;
begin
if a0.val_type = mal_nil then
new_nil(result);
else
hashmap_get(a0, a1, val);
if val = null then
new_nil(result);
else
result := val;
end if;
end if;
end procedure fn_get;
procedure fn_contains_q(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable a0: mal_val_ptr := args.seq_val(0);
variable a1: mal_val_ptr := args.seq_val(1);
variable found: boolean;
begin
hashmap_contains(a0, a1, found);
new_boolean(found, result);
end procedure fn_contains_q;
procedure fn_keys(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable a0: mal_val_ptr := args.seq_val(0);
variable seq: mal_seq_ptr;
begin
seq := new mal_seq(0 to a0.seq_val'length / 2 - 1);
for i in seq'range loop
seq(i) := a0.seq_val(i * 2);
end loop;
new_seq_obj(mal_list, seq, result);
end procedure fn_keys;
procedure fn_vals(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable a0: mal_val_ptr := args.seq_val(0);
variable seq: mal_seq_ptr;
begin
seq := new mal_seq(0 to a0.seq_val'length / 2 - 1);
for i in seq'range loop
seq(i) := a0.seq_val(i * 2 + 1);
end loop;
new_seq_obj(mal_list, seq, result);
end procedure fn_vals;
procedure cons_helper(a0: inout mal_val_ptr; a1: inout mal_val_ptr; result: out mal_val_ptr) is
variable seq: mal_seq_ptr;
begin
seq := new mal_seq(0 to a1.seq_val'length);
seq(0) := a0;
seq(1 to seq'length - 1) := a1.seq_val(0 to a1.seq_val'length - 1);
new_seq_obj(mal_list, seq, result);
end procedure cons_helper;
procedure fn_cons(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable a0: mal_val_ptr := args.seq_val(0);
variable a1: mal_val_ptr := args.seq_val(1);
variable seq: mal_seq_ptr;
begin
cons_helper(a0, a1, result);
end procedure fn_cons;
procedure fn_sequential_q(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
begin
new_boolean(is_sequential_type(args.seq_val(0).val_type), result);
end procedure fn_sequential_q;
procedure fn_concat(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable seq: mal_seq_ptr;
variable i: integer;
begin
seq := new mal_seq(0 to -1);
for i in args.seq_val'range loop
seq := new mal_seq'(seq.all & args.seq_val(i).seq_val.all);
end loop;
new_seq_obj(mal_list, seq, result);
end procedure fn_concat;
procedure fn_nth(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable lst_seq: mal_seq_ptr := args.seq_val(0).seq_val;
variable index: integer := args.seq_val(1).number_val;
begin
if index >= lst_seq'length then
new_string("nth: index out of range", err);
else
result := lst_seq(index);
end if;
end procedure fn_nth;
procedure fn_first(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable a0: mal_val_ptr := args.seq_val(0);
begin
if a0.val_type = mal_nil or a0.seq_val'length = 0 then
new_nil(result);
else
result := a0.seq_val(0);
end if;
end procedure fn_first;
procedure fn_rest(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable a0: mal_val_ptr := args.seq_val(0);
variable seq: mal_seq_ptr;
variable new_list: mal_val_ptr;
begin
if a0.val_type = mal_nil or a0.seq_val'length = 0 then
seq := new mal_seq(0 to -1);
new_seq_obj(mal_list, seq, result);
else
seq_drop_prefix(a0, 1, new_list);
new_list.val_type := mal_list;
result := new_list;
end if;
end procedure fn_rest;
procedure fn_empty_q(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable is_empty: boolean;
begin
case args.seq_val(0).val_type is
when mal_nil => new_boolean(true, result);
when mal_list | mal_vector => new_boolean(args.seq_val(0).seq_val'length = 0, result);
when others => new_string("empty?: invalid argument type", err);
end case;
end procedure fn_empty_q;
procedure fn_count(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable count: integer;
begin
case args.seq_val(0).val_type is
when mal_nil => new_number(0, result);
when mal_list | mal_vector => new_number(args.seq_val(0).seq_val'length, result);
when others => new_string("count: invalid argument type", err);
end case;
end procedure fn_count;
procedure fn_conj(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable a0: mal_val_ptr := args.seq_val(0);
variable r: mal_val_ptr;
variable seq: mal_seq_ptr;
begin
case a0.val_type is
when mal_list =>
r := a0;
for i in 1 to args.seq_val'high loop
cons_helper(args.seq_val(i), r, r);
end loop;
result := r;
when mal_vector =>
seq := new mal_seq(0 to a0.seq_val'length + args.seq_val'length - 2);
seq(0 to a0.seq_val'high) := a0.seq_val(a0.seq_val'range);
seq(a0.seq_val'high + 1 to seq'high) := args.seq_val(1 to args.seq_val'high);
new_seq_obj(mal_vector, seq, result);
when others =>
new_string("conj requires list or vector", err);
end case;
end procedure fn_conj;
procedure fn_seq(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable a0: mal_val_ptr := args.seq_val(0);
variable new_seq: mal_seq_ptr;
begin
case a0.val_type is
when mal_string =>
if a0.string_val'length = 0 then
new_nil(result);
else
new_seq := new mal_seq(0 to a0.string_val'length - 1);
for i in new_seq'range loop
new_string("" & a0.string_val(i + 1), new_seq(i));
end loop;
new_seq_obj(mal_list, new_seq, result);
end if;
when mal_list =>
if a0.seq_val'length = 0 then
new_nil(result);
else
result := a0;
end if;
when mal_vector =>
if a0.seq_val'length = 0 then
new_nil(result);
else
new_seq_obj(mal_list, a0.seq_val, result);
end if;
when mal_nil =>
new_nil(result);
when others =>
new_string("seq requires string or list or vector or nil", err);
end case;
end procedure fn_seq;
procedure fn_meta(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable meta_val: mal_val_ptr;
begin
meta_val := args.seq_val(0).meta_val;
if meta_val = null then
new_nil(result);
else
result := meta_val;
end if;
end procedure fn_meta;
procedure fn_with_meta(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable a0: mal_val_ptr := args.seq_val(0);
begin
result := new mal_val'(val_type => a0.val_type, number_val => a0.number_val, string_val => a0.string_val, seq_val => a0.seq_val, func_val => a0.func_val, meta_val => args.seq_val(1));
end procedure fn_with_meta;
procedure fn_atom(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
begin
new_atom(args.seq_val(0), result);
end procedure fn_atom;
procedure fn_atom_q(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable a0: mal_val_ptr := args.seq_val(0);
begin
new_boolean(a0.val_type = mal_atom, result);
end procedure fn_atom_q;
procedure fn_deref(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable a0: mal_val_ptr := args.seq_val(0);
begin
result := a0.seq_val(0);
end procedure fn_deref;
procedure fn_reset(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable a0: mal_val_ptr := args.seq_val(0);
variable a1: mal_val_ptr := args.seq_val(1);
begin
a0.seq_val(0) := a1;
result := a1;
end procedure fn_reset;
procedure eval_native_func(func_sym: inout mal_val_ptr; args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable f: line;
begin
if func_sym.val_type /= mal_nativefn then
new_string("not a native function!", err);
return;
end if;
f := func_sym.string_val;
if f.all = "=" then fn_equal(args, result, err);
elsif f.all = "throw" then fn_throw(args, result, err);
elsif f.all = "nil?" then fn_nil_q(args, result, err);
elsif f.all = "true?" then fn_true_q(args, result, err);
elsif f.all = "false?" then fn_false_q(args, result, err);
elsif f.all = "string?" then fn_string_q(args, result, err);
elsif f.all = "symbol" then fn_symbol(args, result, err);
elsif f.all = "symbol?" then fn_symbol_q(args, result, err);
elsif f.all = "keyword" then fn_keyword(args, result, err);
elsif f.all = "keyword?" then fn_keyword_q(args, result, err);
elsif f.all = "pr-str" then fn_pr_str(args, result, err);
elsif f.all = "str" then fn_str(args, result, err);
elsif f.all = "prn" then fn_prn(args, result, err);
elsif f.all = "println" then fn_println(args, result, err);
elsif f.all = "read-string" then fn_read_string(args, result, err);
elsif f.all = "readline" then fn_readline(args, result, err);
elsif f.all = "slurp" then fn_slurp(args, result, err);
elsif f.all = "<" then fn_lt(args, result, err);
elsif f.all = "<=" then fn_lte(args, result, err);
elsif f.all = ">" then fn_gt(args, result, err);
elsif f.all = ">=" then fn_gte(args, result, err);
elsif f.all = "+" then fn_add(args, result, err);
elsif f.all = "-" then fn_sub(args, result, err);
elsif f.all = "*" then fn_mul(args, result, err);
elsif f.all = "/" then fn_div(args, result, err);
elsif f.all = "time-ms" then fn_time_ms(args, result, err);
elsif f.all = "list" then fn_list(args, result, err);
elsif f.all = "list?" then fn_list_q(args, result, err);
elsif f.all = "vector" then fn_vector(args, result, err);
elsif f.all = "vector?" then fn_vector_q(args, result, err);
elsif f.all = "hash-map" then fn_hash_map(args, result, err);
elsif f.all = "map?" then fn_map_q(args, result, err);
elsif f.all = "assoc" then fn_assoc(args, result, err);
elsif f.all = "dissoc" then fn_dissoc(args, result, err);
elsif f.all = "get" then fn_get(args, result, err);
elsif f.all = "contains?" then fn_contains_q(args, result, err);
elsif f.all = "keys" then fn_keys(args, result, err);
elsif f.all = "vals" then fn_vals(args, result, err);
elsif f.all = "sequential?" then fn_sequential_q(args, result, err);
elsif f.all = "cons" then fn_cons(args, result, err);
elsif f.all = "concat" then fn_concat(args, result, err);
elsif f.all = "nth" then fn_nth(args, result, err);
elsif f.all = "first" then fn_first(args, result, err);
elsif f.all = "rest" then fn_rest(args, result, err);
elsif f.all = "empty?" then fn_empty_q(args, result, err);
elsif f.all = "count" then fn_count(args, result, err);
elsif f.all = "conj" then fn_conj(args, result, err);
elsif f.all = "seq" then fn_seq(args, result, err);
elsif f.all = "meta" then fn_meta(args, result, err);
elsif f.all = "with-meta" then fn_with_meta(args, result, err);
elsif f.all = "atom" then fn_atom(args, result, err);
elsif f.all = "atom?" then fn_atom_q(args, result, err);
elsif f.all = "deref" then fn_deref(args, result, err);
elsif f.all = "reset!" then fn_reset(args, result, err);
else
result := null;
end if;
end procedure eval_native_func;
procedure define_core_function(e: inout env_ptr; func_name: in string) is
variable sym: mal_val_ptr;
variable fn: mal_val_ptr;
begin
new_symbol(func_name, sym);
new_nativefn(func_name, fn);
env_set(e, sym, fn);
end procedure define_core_function;
procedure define_core_functions(e: inout env_ptr) is
variable is_eof: boolean;
variable input_line, result, err: line;
variable sym: mal_val_ptr;
variable fn: mal_val_ptr;
variable outer: env_ptr;
variable repl_env: env_ptr;
begin
define_core_function(e, "=");
define_core_function(e, "throw");
define_core_function(e, "nil?");
define_core_function(e, "true?");
define_core_function(e, "false?");
define_core_function(e, "string?");
define_core_function(e, "symbol");
define_core_function(e, "symbol?");
define_core_function(e, "keyword");
define_core_function(e, "keyword?");
define_core_function(e, "pr-str");
define_core_function(e, "str");
define_core_function(e, "prn");
define_core_function(e, "println");
define_core_function(e, "read-string");
define_core_function(e, "readline");
define_core_function(e, "slurp");
define_core_function(e, "<");
define_core_function(e, "<=");
define_core_function(e, ">");
define_core_function(e, ">=");
define_core_function(e, "+");
define_core_function(e, "-");
define_core_function(e, "*");
define_core_function(e, "/");
define_core_function(e, "time-ms");
define_core_function(e, "list");
define_core_function(e, "list?");
define_core_function(e, "vector");
define_core_function(e, "vector?");
define_core_function(e, "hash-map");
define_core_function(e, "map?");
define_core_function(e, "assoc");
define_core_function(e, "dissoc");
define_core_function(e, "get");
define_core_function(e, "contains?");
define_core_function(e, "keys");
define_core_function(e, "vals");
define_core_function(e, "sequential?");
define_core_function(e, "cons");
define_core_function(e, "concat");
define_core_function(e, "nth");
define_core_function(e, "first");
define_core_function(e, "rest");
define_core_function(e, "empty?");
define_core_function(e, "count");
define_core_function(e, "apply"); -- implemented in the stepN_XXX files
define_core_function(e, "map"); -- implemented in the stepN_XXX files
define_core_function(e, "conj");
define_core_function(e, "seq");
define_core_function(e, "meta");
define_core_function(e, "with-meta");
define_core_function(e, "atom");
define_core_function(e, "atom?");
define_core_function(e, "deref");
define_core_function(e, "reset!");
define_core_function(e, "swap!"); -- implemented in the stepN_XXX files
end procedure define_core_functions;
end package body core;
|
mpl-2.0
|
SawyerHood/mal
|
vhdl/types.vhdl
|
17
|
13485
|
library STD;
use STD.textio.all;
package types is
procedure debugline(l: inout line);
procedure debug(str: in string);
procedure debug(ch: in character);
procedure debug(i: in integer);
type mal_type_tag is (mal_nil, mal_true, mal_false, mal_number,
mal_symbol, mal_string, mal_keyword,
mal_list, mal_vector, mal_hashmap,
mal_atom, mal_nativefn, mal_fn);
-- Forward declarations
type mal_val;
type mal_seq;
type mal_func;
type env_record;
type mal_val_ptr is access mal_val;
type mal_seq_ptr is access mal_seq;
type mal_func_ptr is access mal_func;
type env_ptr is access env_record;
type mal_val is record
val_type: mal_type_tag;
number_val: integer; -- For types: number
string_val: line; -- For types: symbol, string, keyword, nativefn
seq_val: mal_seq_ptr; -- For types: list, vector, hashmap, atom
func_val: mal_func_ptr; -- For fn
meta_val: mal_val_ptr;
end record mal_val;
type mal_seq is array (natural range <>) of mal_val_ptr;
type mal_func is record
f_body: mal_val_ptr;
f_args: mal_val_ptr;
f_env: env_ptr;
f_is_macro: boolean;
end record mal_func;
type env_record is record
outer: env_ptr;
data: mal_val_ptr;
end record env_record;
procedure new_nil(obj: out mal_val_ptr);
procedure new_true(obj: out mal_val_ptr);
procedure new_false(obj: out mal_val_ptr);
procedure new_boolean(b: in boolean; obj: out mal_val_ptr);
procedure new_number(v: in integer; obj: out mal_val_ptr);
procedure new_symbol(name: in string; obj: out mal_val_ptr);
procedure new_symbol(name: inout line; obj: out mal_val_ptr);
procedure new_string(name: in string; obj: out mal_val_ptr);
procedure new_string(name: inout line; obj: out mal_val_ptr);
procedure new_keyword(name: in string; obj: out mal_val_ptr);
procedure new_keyword(name: inout line; obj: out mal_val_ptr);
procedure new_nativefn(name: in string; obj: out mal_val_ptr);
procedure new_fn(body_ast: inout mal_val_ptr; args: inout mal_val_ptr; env: inout env_ptr; obj: out mal_val_ptr);
procedure new_seq_obj(seq_type: in mal_type_tag; seq: inout mal_seq_ptr; obj: out mal_val_ptr);
procedure new_one_element_list(val: inout mal_val_ptr; obj: out mal_val_ptr);
procedure new_empty_hashmap(obj: out mal_val_ptr);
procedure new_atom(val: inout mal_val_ptr; obj: out mal_val_ptr);
procedure hashmap_copy(hashmap: inout mal_val_ptr; obj: out mal_val_ptr);
procedure hashmap_get(hashmap: inout mal_val_ptr; key: inout mal_val_ptr; val: out mal_val_ptr);
procedure hashmap_contains(hashmap: inout mal_val_ptr; key: inout mal_val_ptr; ok: out boolean);
procedure hashmap_put(hashmap: inout mal_val_ptr; key: inout mal_val_ptr; val: inout mal_val_ptr);
procedure hashmap_delete(hashmap: inout mal_val_ptr; key: inout mal_val_ptr);
procedure seq_drop_prefix(src: inout mal_val_ptr; prefix_length: in integer; result: out mal_val_ptr);
function is_sequential_type(t: in mal_type_tag) return boolean;
procedure equal_q(a: inout mal_val_ptr; b: inout mal_val_ptr; result: out boolean);
end package types;
package body types is
procedure debugline(l: inout line) is
variable l2: line;
begin
l2 := new string(1 to 7 + l'length);
l2(1 to l2'length) := "DEBUG: " & l.all;
writeline(output, l2);
end procedure debugline;
procedure debug(str: in string) is
variable d: line;
begin
write(d, str);
debugline(d);
end procedure debug;
procedure debug(ch: in character) is
variable d: line;
begin
write(d, ch);
debugline(d);
end procedure debug;
procedure debug(i: in integer) is
variable d: line;
begin
write(d, i);
debugline(d);
end procedure debug;
procedure new_nil(obj: out mal_val_ptr) is
begin
obj := new mal_val'(val_type => mal_nil, number_val => 0, string_val => null, seq_val => null, func_val => null, meta_val => null);
end procedure new_nil;
procedure new_true(obj: out mal_val_ptr) is
begin
obj := new mal_val'(val_type => mal_true, number_val => 0, string_val => null, seq_val => null, func_val => null, meta_val => null);
end procedure new_true;
procedure new_false(obj: out mal_val_ptr) is
begin
obj := new mal_val'(val_type => mal_false, number_val => 0, string_val => null, seq_val => null, func_val => null, meta_val => null);
end procedure new_false;
procedure new_boolean(b: in boolean; obj: out mal_val_ptr) is
begin
if b then
new_true(obj);
else
new_false(obj);
end if;
end procedure new_boolean;
procedure new_number(v: in integer; obj: out mal_val_ptr) is
begin
obj := new mal_val'(val_type => mal_number, number_val => v, string_val => null, seq_val => null, func_val => null, meta_val => null);
end procedure new_number;
procedure new_symbol(name: in string; obj: out mal_val_ptr) is
begin
obj := new mal_val'(val_type => mal_symbol, number_val => 0, string_val => new string'(name), seq_val => null, func_val => null, meta_val => null);
end procedure new_symbol;
procedure new_symbol(name: inout line; obj: out mal_val_ptr) is
begin
obj := new mal_val'(val_type => mal_symbol, number_val => 0, string_val => name, seq_val => null, func_val => null, meta_val => null);
end procedure new_symbol;
procedure new_string(name: in string; obj: out mal_val_ptr) is
begin
obj := new mal_val'(val_type => mal_string, number_val => 0, string_val => new string'(name), seq_val => null, func_val => null, meta_val => null);
end procedure new_string;
procedure new_string(name: inout line; obj: out mal_val_ptr) is
begin
obj := new mal_val'(val_type => mal_string, number_val => 0, string_val => name, seq_val => null, func_val => null, meta_val => null);
end procedure new_string;
procedure new_keyword(name: in string; obj: out mal_val_ptr) is
begin
obj := new mal_val'(val_type => mal_keyword, number_val => 0, string_val => new string'(name), seq_val => null, func_val => null, meta_val => null);
end procedure new_keyword;
procedure new_keyword(name: inout line; obj: out mal_val_ptr) is
begin
obj := new mal_val'(val_type => mal_keyword, number_val => 0, string_val => name, seq_val => null, func_val => null, meta_val => null);
end procedure new_keyword;
procedure new_nativefn(name: in string; obj: out mal_val_ptr) is
begin
obj := new mal_val'(val_type => mal_nativefn, number_val => 0, string_val => new string'(name), seq_val => null, func_val => null, meta_val => null);
end procedure new_nativefn;
procedure new_fn(body_ast: inout mal_val_ptr; args: inout mal_val_ptr; env: inout env_ptr; obj: out mal_val_ptr) is
variable f: mal_func_ptr;
begin
f := new mal_func'(f_body => body_ast, f_args => args, f_env => env, f_is_macro => false);
obj := new mal_val'(val_type => mal_fn, number_val => 0, string_val => null, seq_val => null, func_val => f, meta_val => null);
end procedure new_fn;
procedure new_seq_obj(seq_type: in mal_type_tag; seq: inout mal_seq_ptr; obj: out mal_val_ptr) is
begin
obj := new mal_val'(val_type => seq_type, number_val => 0, string_val => null, seq_val => seq, func_val => null, meta_val => null);
end procedure new_seq_obj;
procedure new_one_element_list(val: inout mal_val_ptr; obj: out mal_val_ptr) is
variable seq: mal_seq_ptr;
begin
seq := new mal_seq(0 to 0);
seq(0) := val;
new_seq_obj(mal_list, seq, obj);
end procedure new_one_element_list;
procedure new_empty_hashmap(obj: out mal_val_ptr) is
variable seq: mal_seq_ptr;
begin
seq := new mal_seq(0 to -1);
new_seq_obj(mal_hashmap, seq, obj);
end procedure new_empty_hashmap;
procedure new_atom(val: inout mal_val_ptr; obj: out mal_val_ptr) is
variable atom_seq: mal_seq_ptr;
begin
atom_seq := new mal_seq(0 to 0);
atom_seq(0) := val;
new_seq_obj(mal_atom, atom_seq, obj);
end procedure new_atom;
procedure hashmap_copy(hashmap: inout mal_val_ptr; obj: out mal_val_ptr) is
variable new_seq: mal_seq_ptr;
begin
new_seq := new mal_seq(hashmap.seq_val'range);
new_seq(new_seq'range) := hashmap.seq_val(hashmap.seq_val'range);
new_seq_obj(mal_hashmap, new_seq, obj);
end procedure hashmap_copy;
procedure hashmap_get(hashmap: inout mal_val_ptr; key: inout mal_val_ptr; val: out mal_val_ptr) is
variable i: natural;
variable curr_key: mal_val_ptr;
begin
i := 0;
while i < hashmap.seq_val'length loop
curr_key := hashmap.seq_val(i);
if key.val_type = curr_key.val_type and key.string_val.all = curr_key.string_val.all then
val := hashmap.seq_val(i + 1);
return;
end if;
i := i + 2;
end loop;
val := null;
end procedure hashmap_get;
procedure hashmap_contains(hashmap: inout mal_val_ptr; key: inout mal_val_ptr; ok: out boolean) is
variable val: mal_val_ptr;
begin
hashmap_get(hashmap, key, val);
if val = null then
ok := false;
else
ok := true;
end if;
end procedure hashmap_contains;
procedure hashmap_put(hashmap: inout mal_val_ptr; key: inout mal_val_ptr; val: inout mal_val_ptr) is
variable i: natural;
variable curr_key: mal_val_ptr;
variable new_seq: mal_seq_ptr;
begin
i := 0;
while i < hashmap.seq_val'length loop
curr_key := hashmap.seq_val(i);
if key.val_type = curr_key.val_type and key.string_val.all = curr_key.string_val.all then
hashmap.seq_val(i + 1) := val;
return;
end if;
i := i + 2;
end loop;
-- Not found so far, need to extend the seq
new_seq := new mal_seq(0 to hashmap.seq_val'length + 1);
for i in hashmap.seq_val'range loop
new_seq(i) := hashmap.seq_val(i);
end loop;
new_seq(new_seq'length - 2) := key;
new_seq(new_seq'length - 1) := val;
deallocate(hashmap.seq_val);
hashmap.seq_val := new_seq;
end procedure hashmap_put;
procedure hashmap_delete(hashmap: inout mal_val_ptr; key: inout mal_val_ptr) is
variable i, dst_i: natural;
variable curr_key: mal_val_ptr;
variable new_seq: mal_seq_ptr;
variable found: boolean;
begin
hashmap_contains(hashmap, key, found);
if not found then
return;
end if;
i := 0;
dst_i := 0;
new_seq := new mal_seq(0 to hashmap.seq_val'high - 2);
while i < hashmap.seq_val'length loop
curr_key := hashmap.seq_val(i);
if key.val_type = curr_key.val_type and key.string_val.all = curr_key.string_val.all then
i := i + 2;
else
new_seq(dst_i to dst_i + 1) := hashmap.seq_val(i to i + 1);
dst_i := dst_i + 2;
i := i + 2;
end if;
end loop;
deallocate(hashmap.seq_val);
hashmap.seq_val := new_seq;
end procedure hashmap_delete;
procedure seq_drop_prefix(src: inout mal_val_ptr; prefix_length: in integer; result: out mal_val_ptr) is
variable seq: mal_seq_ptr;
begin
seq := new mal_seq(0 to src.seq_val'length - 1 - prefix_length);
for i in seq'range loop
seq(i) := src.seq_val(i + prefix_length);
end loop;
new_seq_obj(src.val_type, seq, result);
end procedure seq_drop_prefix;
function is_sequential_type(t: in mal_type_tag) return boolean is
begin
return t = mal_list or t = mal_vector;
end function is_sequential_type;
procedure equal_seq_q(a: inout mal_val_ptr; b: inout mal_val_ptr; result: out boolean) is
variable i: integer;
variable is_element_equal: boolean;
begin
if a.seq_val'length = b.seq_val'length then
for i in a.seq_val'range loop
equal_q(a.seq_val(i), b.seq_val(i), is_element_equal);
if not is_element_equal then
result := false;
return;
end if;
end loop;
result := true;
else
result := false;
end if;
end procedure equal_seq_q;
procedure equal_hashmap_q(a: inout mal_val_ptr; b: inout mal_val_ptr; result: out boolean) is
variable i: integer;
variable is_value_equal: boolean;
variable b_val: mal_val_ptr;
begin
if a.seq_val'length = b.seq_val'length then
i := 0;
while i < a.seq_val'length loop
hashmap_get(b, a.seq_val(i), b_val);
if b_val = null then
result := false;
return;
else
equal_q(a.seq_val(i + 1), b_val, is_value_equal);
if not is_value_equal then
result := false;
return;
end if;
end if;
i := i + 2;
end loop;
result := true;
else
result := false;
end if;
end procedure equal_hashmap_q;
procedure equal_q(a: inout mal_val_ptr; b: inout mal_val_ptr; result: out boolean) is
begin
if is_sequential_type(a.val_type) and is_sequential_type(b.val_type) then
equal_seq_q(a, b, result);
elsif a.val_type = b.val_type then
case a.val_type is
when mal_nil | mal_true | mal_false =>
result := true;
when mal_number =>
result := a.number_val = b.number_val;
when mal_symbol | mal_string | mal_keyword =>
result := a.string_val.all = b.string_val.all;
when mal_hashmap =>
equal_hashmap_q(a, b, result);
when mal_atom =>
equal_q(a.seq_val(0), b.seq_val(0), result);
when others =>
result := false;
end case;
else
result := false;
end if;
end procedure equal_q;
end package body types;
|
mpl-2.0
|
preusser/q27
|
src/vhdl/PoC/ocram/ocram_sdp.vhdl
|
2
|
5084
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Martin Zabel
-- Thomas B. Preusser
-- Patrick Lehmann
--
-- Module: Simple dual-port memory.
--
-- Description:
-- ------------------------------------
-- Inferring / instantiating simple dual-port memory, with:
-- * dual clock, clock enable,
-- * 1 read port plus 1 write port.
--
-- The generalized behavior across Altera and Xilinx FPGAs since
-- Stratix/Cyclone and Spartan-3/Virtex-5, respectively, is as follows:
--
-- The Altera M512/M4K TriMatrix memory (as found e.g. in Stratix and
-- Stratix II FPGAs) defines the minimum time after which the written data at
-- the write port can be read-out at read port again. As stated in the Stratix
-- Handbook, Volume 2, page 2-13, data is actually written with the falling
-- (instead of the rising) edge of the clock into the memory array. The write
-- itself takes the write-cycle time which is less or equal to the minimum
-- clock-period time. After this, the data can be read-out at the other port.
-- Consequently, data "d" written at the rising-edge of "wclk" at address
-- "wa" can be read-out at the read port from the same address with the
-- 2nd rising-edge of "rclk" following the falling-edge of "wclk".
-- If the rising-edge of "rclk" coincides with the falling-edge of "wclk"
-- (e.g. same clock signal), then it is counted as the 1st rising-edge of
-- "rclk" in this timing.
--
-- WARNING: The simulated behavior on RT-level is not correct.
--
-- TODO: add timing diagram
-- TODO: implement correct behavior for RT-level simulation
--
-- License:
-- ============================================================================
-- Copyright 2008-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity ocram_sdp is
generic (
A_BITS : positive;
D_BITS : positive
);
port (
rclk : in std_logic; -- read clock
rce : in std_logic; -- read clock-enable
wclk : in std_logic; -- write clock
wce : in std_logic; -- write clock-enable
we : in std_logic; -- write enable
ra : in unsigned(A_BITS-1 downto 0); -- read address
wa : in unsigned(A_BITS-1 downto 0); -- write address
d : in std_logic_vector(D_BITS-1 downto 0); -- data in
q : out std_logic_vector(D_BITS-1 downto 0)); -- data out
end entity;
library PoC;
use PoC.config.all;
architecture rtl of ocram_sdp is
attribute ramstyle : string;
constant DEPTH : positive := 2**A_BITS;
begin
gInfer: if VENDOR = VENDOR_XILINX or VENDOR = VENDOR_ALTERA generate
-- RAM can be inferred correctly
-- Xilinx notes:
-- WRITE_MODE is set to WRITE_FIRST, but this also means that read data
-- is unknown on the opposite port. (As expected.)
-- Altera notes:
-- Setting attribute "ramstyle" to "no_rw_check" suppresses generation of
-- bypass logic, when 'clk1'='clk2' and 'ra' is feed from a register.
-- This is the expected behaviour.
-- With two different clocks, synthesis complains about an undefined
-- read-write behaviour, that can be ignored.
subtype word_t is std_logic_vector(D_BITS - 1 downto 0);
type ram_t is array(0 to DEPTH - 1) of word_t;
signal ram : ram_t;
attribute ramstyle of ram : signal is "no_rw_check";
begin
process (wclk)
begin
if rising_edge(wclk) then
if (wce and we) = '1' then
ram(to_integer(wa)) <= d;
end if;
end if;
end process;
process (rclk)
begin
if rising_edge(rclk) then
-- read data doesn't care, when reading at write address
if rce = '1' then
--synthesis translate_off
if Is_X(std_logic_vector(ra)) then
q <= (others => 'X');
else
--synthesis translate_on
q <= ram(to_integer(ra));
--synthesis translate_off
end if;
--synthesis translate_on
end if;
end if;
end process;
end generate gInfer;
assert VENDOR = VENDOR_XILINX or VENDOR = VENDOR_ALTERA
report "Device not yet supported."
severity failure;
end rtl;
|
agpl-3.0
|
preusser/q27
|
src/vhdl/PoC/uart/uart.pkg.vhdl
|
2
|
2426
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ===========================================================================
-- Package: UART (RS232) Components
--
-- Authors: Martin Zabel
-- Thomas B. Preusser
--
-- License:
-- ===========================================================================
-- Copyright 2007-2014 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ===========================================================================
library IEEE;
use IEEE.std_logic_1164.all;
package uart is
component uart_bclk
generic (
CLK_FREQ : positive;
BAUDRATE : positive
);
port (
clk : in std_logic;
rst : in std_logic;
bclk : out std_logic;
bclk_x8 : out std_logic
);
end component;
component uart_rx is
generic (
SYNC_DEPTH : natural := 2 -- use zero for already clock-synchronous rx
);
port (
-- Global Control
clk : in std_logic;
rst : in std_logic;
-- Bit Clock and RX Line
bclk_x8 : in std_logic; -- bit clock, eight strobes per bit length
rx : in std_logic;
-- Byte Stream Output
do : out std_logic_vector(7 downto 0);
stb : out std_logic
);
end component;
component uart_tx is
port (
-- Global Control
clk : in std_logic;
rst : in std_logic;
-- Bit Clock and TX Line
bclk : in std_logic; -- bit clock, one strobe each bit length
tx : out std_logic;
-- Byte Stream Input
di : in std_logic_vector(7 downto 0);
put : in std_logic;
ful : out std_logic
);
end component;
end uart;
package body uart is
end uart;
|
agpl-3.0
|
preusser/q27
|
src/vhdl/PoC/ocram/ocram.pkg.vhdl
|
2
|
2043
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Martin Zabel
-- Patrick Lehmann
--
-- Package: VHDL package for component declarations, types and functions
-- associated to the PoC.mem.ocram namespace
--
-- Description:
-- ------------------------------------
-- On-Chip RAMs and ROMs for FPGAs.
--
-- A detailed documentation is included in each module.
--
-- License:
-- ============================================================================
-- Copyright 2008-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
package ocram is
-- Simple-Dual-Port
component ocram_sdp
generic (
A_BITS : positive;
D_BITS : positive
);
port (
rclk : in std_logic;
rce : in std_logic;
wclk : in std_logic;
wce : in std_logic;
we : in std_logic;
ra : in unsigned(A_BITS-1 downto 0);
wa : in unsigned(A_BITS-1 downto 0);
d : in std_logic_vector(D_BITS-1 downto 0);
q : out std_logic_vector(D_BITS-1 downto 0)
);
end component;
end package;
|
agpl-3.0
|
preusser/q27
|
src/vhdl/PoC/common/my_config_VC707.vhdl
|
2
|
1750
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Thomas B. Preusser
-- Martin Zabel
-- Patrick Lehmann
--
-- Package: Project specific configuration.
--
-- Description:
-- ------------------------------------
-- This file was created from template <PoCRoot>/src/common/my_config.template.vhdl.
--
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library PoC;
package my_config is
-- Change these lines to setup configuration.
constant MY_BOARD : string := "VC707"; -- VC707 - Xilinx Virtex 7 reference design board: XC7V485T
constant MY_DEVICE : string := "None"; -- infer from MY_BOARD
-- For internal use only
constant MY_VERBOSE : boolean := true;
end package;
|
agpl-3.0
|
preusser/q27
|
src/vhdl/PoC/xilinx/xil_SystemMonitor_Virtex6.vhdl
|
2
|
5256
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Patrick Lehmann
--
-- Module: System Monitor wrapper for temperature supervision applications
--
-- Description:
-- ------------------------------------
-- This module wraps a Virtex-6 System Monitor primitive to report if preconfigured
-- temperature values are overrun.
--
-- Temperature curve:
-- ------------------
--
-- | /-----\
-- Temp_ov on=80 | - - - - - - /-------/ \
-- | / | \
-- Temp_ov off=60 | - - - - - / - - - - | - - - - \----\
-- | / | \
-- | / | | \
-- Temp_us on=35 | - /---/ | | \
-- Temp_us off=30 | - / - -|- - - - - - | - - - - - - -|- \------\
-- | / | | | \
-- ----------------|--------|------------|--------------|----------|---------
-- pwm = | min | medium | max | medium | min
--
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
LIBRARY UniSim;
USE UniSim.vComponents.ALL;
entity xil_SystemMonitor_Virtex6 is
port (
Reset : in STD_LOGIC; -- Reset signal for the System Monitor control logic
Alarm_UserTemp : out STD_LOGIC; -- Temperature-sensor alarm output
Alarm_OverTemp : out STD_LOGIC; -- Over-Temperature alarm output
Alarm : out STD_LOGIC; -- OR'ed output of all the Alarms
VP : in STD_LOGIC; -- Dedicated Analog Input Pair
VN : in STD_LOGIC
);
end;
architecture xilinx of xil_SystemMonitor_Virtex6 is
signal FLOAT_VCCAUX_ALARM : STD_LOGIC;
signal FLOAT_VCCINT_ALARM : STD_LOGIC;
signal aux_channel_p : STD_LOGIC_VECTOR(15 downto 0);
signal aux_channel_n : STD_LOGIC_VECTOR(15 downto 0);
signal SysMonitor_Alarm : STD_LOGIC_VECTOR(2 downto 0);
signal SysMonitor_OverTemp : STD_LOGIC;
begin
genAUXChannel : for i in 0 to 15 generate
aux_channel_p(i) <= '0';
aux_channel_n(i) <= '0';
end generate;
SysMonitor : SYSMON
generic map (
INIT_40 => x"0000", -- config reg 0
INIT_41 => x"300c", -- config reg 1
INIT_42 => x"0a00", -- config reg 2
INIT_48 => x"0100", -- Sequencer channel selection
INIT_49 => x"0000", -- Sequencer channel selection
INIT_4A => x"0000", -- Sequencer Average selection
INIT_4B => x"0000", -- Sequencer Average selection
INIT_4C => x"0000", -- Sequencer Bipolar selection
INIT_4D => x"0000", -- Sequencer Bipolar selection
INIT_4E => x"0000", -- Sequencer Acq time selection
INIT_4F => x"0000", -- Sequencer Acq time selection
INIT_50 => x"a418", -- Temp alarm trigger
INIT_51 => x"5999", -- Vccint upper alarm limit
INIT_52 => x"e000", -- Vccaux upper alarm limit
INIT_53 => x"b363", -- Temp alarm OT upper
INIT_54 => x"9c87", -- Temp alarm reset
INIT_55 => x"5111", -- Vccint lower alarm limit
INIT_56 => x"caaa", -- Vccaux lower alarm limit
INIT_57 => x"a425", -- Temp alarm OT reset
SIM_DEVICE => "VIRTEX6",
SIM_MONITOR_FILE => "SystemMonitor_sim.txt"
)
port map (
-- Control and Clock
RESET => Reset,
CONVSTCLK => '0',
CONVST => '0',
-- DRP port
DCLK => '0',
DEN => '0',
DADDR => "0000000",
DWE => '0',
DI => x"0000",
DO => open,
DRDY => open,
-- External analog inputs
VAUXN => aux_channel_n(15 downto 0),
VAUXP => aux_channel_p(15 downto 0),
VN => VN,
VP => VP,
-- Alarms
OT => SysMonitor_OverTemp,
ALM => SysMonitor_Alarm,
-- Status
CHANNEL => open,
BUSY => open,
EOC => open,
EOS => open,
JTAGBUSY => open,
JTAGLOCKED => open,
JTAGMODIFIED => open
);
Alarm_UserTemp <= SysMonitor_Alarm(0);
Alarm_OverTemp <= SysMonitor_OverTemp;
Alarm <= SysMonitor_Alarm(0) or SysMonitor_OverTemp;
end;
|
agpl-3.0
|
preusser/q27
|
src/vhdl/PoC/io/io_FrequencyCounter.vhdl
|
2
|
3850
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Patrick Lehmann
--
-- Module: TODO
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- ============================================================================
-- Copyright 2007-2014 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library PoC;
use PoC.utils.all;
use PoC.physical.all;
entity io_FrequencyCounter is
generic (
CLOCK_FREQ : FREQ := 100 MHz;
TIMEBASE : TIME := 1 sec;
RESOLUTION : POSITIVE := 8
);
port (
Clock : in STD_LOGIC;
Reset : in STD_LOGIC;
FreqIn : in STD_LOGIC;
FreqOut : out STD_LOGIC_VECTOR(RESOLUTION - 1 downto 0)
);
end;
architecture rtl of io_FrequencyCounter is
constant TIMEBASECOUNTER_MAX : POSITIVE := TimingToCycles(TIMEBASE, CLOCK_FREQ);
constant TIMEBASECOUNTER_BITS : POSITIVE := log2ceilnz(TIMEBASECOUNTER_MAX);
constant REQUENCYCOUNTER_MAX : POSITIVE := 2**RESOLUTION;
constant FREQUENCYCOUNTER_BITS : POSITIVE := RESOLUTION;
signal TimeBaseCounter_us : UNSIGNED(TIMEBASECOUNTER_BITS - 1 downto 0) := (others => '0');
signal TimeBaseCounter_ov : STD_LOGIC;
signal FrequencyCounter_us : UNSIGNED(FREQUENCYCOUNTER_BITS downto 0) := (others => '0');
signal FrequencyCounter_ov : STD_LOGIC;
signal FreqIn_d : STD_LOGIC := '0';
signal FreqIn_re : STD_LOGIC;
signal FreqOut_d : STD_LOGIC_VECTOR(RESOLUTION - 1 downto 0) := (others => '0');
begin
FreqIn_d <= FreqIn when rising_edge(Clock);
FreqIn_re <= not FreqIn_d and FreqIn;
-- timebase counter
process(Clock)
begin
if rising_edge(clock) then
if ((Reset or TimeBaseCounter_ov) = '1') then
TimeBaseCounter_us <= (others => '0');
else
TimeBaseCounter_us <= TimeBaseCounter_us + 1;
end if;
end if;
end process;
TimeBaseCounter_ov <= to_sl(TimeBaseCounter_us = TIMEBASECOUNTER_MAX);
-- frequency counter
process(Clock)
begin
if rising_edge(Clock) then
if ((Reset or TimeBaseCounter_ov) = '1') then
FrequencyCounter_us <= (others => '0');
elsif (FrequencyCounter_ov = '0') and (FreqIn_re = '1') then
FrequencyCounter_us <= FrequencyCounter_us + 1;
end if;
end if;
end process;
FrequencyCounter_ov <= FrequencyCounter_us(FrequencyCounter_us'high);
-- hold counter value until next TimeBaseCounter event
process(Clock)
begin
if rising_edge(Clock) then
if (Reset = '1') then
FreqOut_d <= (others => '0');
elsif (TimeBaseCounter_ov = '1') then
if (FrequencyCounter_ov = '1') then
FreqOut_d <= (others => '1');
else
FreqOut_d <= std_logic_vector(FrequencyCounter_us(FreqOut_d'range));
end if;
end if;
end if;
end process;
FreqOut <= FreqOut_d;
end;
|
agpl-3.0
|
preusser/q27
|
src/vhdl/PoC/fifo/fifo_cc_got_tempput.vhdl
|
1
|
13774
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================================================================================================
-- Module: FIFO, common clock (cc), pipelined interface,
-- writes only become effective after explicit commit
--
-- Authors: Thomas B. Preusser
-- Steffen Koehler
-- Martin Zabel
--
-- Description:
-- ------------------------------------
-- The specified depth (MIN_DEPTH) is rounded up to the next suitable value.
--
-- As uncommitted writes populate FIFO space that is not yet available for
-- reading, an instance of this FIFO can, indeed, report 'full' and 'not vld'
-- at the same time. While a 'commit' would eventually make data available for
-- reading ('vld'), a 'rollback' would free the space for subsequent writing
-- ('not ful').
--
-- 'commit' and 'rollback' are inclusive and apply to all writes ('put') since
-- the previous 'commit' or 'rollback' up to and including a potentially
-- simultaneous write.
--
-- The FIFO state upon a simultaneous assertion of 'commit' and 'rollback' is
-- *undefined*!
--
-- *STATE_*_BITS defines the granularity of the fill state indicator
-- '*state_*'. 'fstate_rd' is associated with the read clock domain and outputs
-- the guaranteed number of words available in the FIFO. 'estate_wr' is
-- associated with the write clock domain and outputs the number of words that
-- is guaranteed to be accepted by the FIFO without a capacity overflow. Note
-- that both these indicators cannot replace the 'full' or 'valid' outputs as
-- they may be implemented as giving pessimistic bounds that are minimally off
-- the true fill state.
--
-- If a fill state is not of interest, set *STATE_*_BITS = 0.
--
-- 'fstate_rd' and 'estate_wr' are combinatorial outputs and include an address
-- comparator (subtractor) in their path.
--
-- Examples:
-- - FSTATE_RD_BITS = 1: fstate_rd == 0 => 0/2 full
-- fstate_rd == 1 => 1/2 full (half full)
--
-- - FSTATE_RD_BITS = 2: fstate_rd == 0 => 0/4 full
-- fstate_rd == 1 => 1/4 full
-- fstate_rd == 2 => 2/4 full
-- fstate_rd == 3 => 3/4 full
--
-- License:
-- ============================================================================================================================================================
-- Copyright 2007-2014 Technische Universitaet Dresden - Germany, Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================================================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library poc;
use poc.config.all;
USE poc.utils.all;
use poc.ocram.ocram_sdp;
entity fifo_cc_got_tempput is
generic (
D_BITS : positive; -- Data Width
MIN_DEPTH : positive; -- Minimum FIFO Depth
DATA_REG : boolean := false; -- Store Data Content in Registers
STATE_REG : boolean := false; -- Registered Full/Empty Indicators
OUTPUT_REG : boolean := false; -- Registered FIFO Output
ESTATE_WR_BITS : natural := 0; -- Empty State Bits
FSTATE_RD_BITS : natural := 0 -- Full State Bits
);
port (
-- Global Reset and Clock
rst, clk : in std_logic;
-- Writing Interface
put : in std_logic; -- Write Request
din : in std_logic_vector(D_BITS-1 downto 0); -- Input Data
full : out std_logic;
estate_wr : out std_logic_vector(imax(0, ESTATE_WR_BITS-1) downto 0);
commit : in std_logic;
rollback : in std_logic;
-- Reading Interface
got : in std_logic; -- Read Completed
dout : out std_logic_vector(D_BITS-1 downto 0); -- Output Data
valid : out std_logic;
fstate_rd : out std_logic_vector(imax(0, FSTATE_RD_BITS-1) downto 0)
);
end fifo_cc_got_tempput;
architecture rtl of fifo_cc_got_tempput is
-- Address Width
constant A_BITS : natural := log2ceil(MIN_DEPTH);
-- Force Carry-Chain Use for Pointer Increments on Xilinx Architectures
constant FORCE_XILCY : boolean := (not SIMULATION) and (VENDOR = VENDOR_XILINX) and STATE_REG and (A_BITS > 4);
-----------------------------------------------------------------------------
-- Memory Pointers
-- Actual Input and Output Pointers
signal IP0 : unsigned(A_BITS-1 downto 0) := (others => '0');
signal OP0 : unsigned(A_BITS-1 downto 0) := (others => '0');
-- Incremented Input and Output Pointers
signal IP1 : unsigned(A_BITS-1 downto 0);
signal OP1 : unsigned(A_BITS-1 downto 0);
-- Committed Write Pointer (Commit Marker)
signal IPm : unsigned(A_BITS-1 downto 0) := (others => '0');
-----------------------------------------------------------------------------
-- Backing Memory Connectivity
-- Write Port
signal wa : unsigned(A_BITS-1 downto 0);
signal we : std_logic;
-- Read Port
signal ra : unsigned(A_BITS-1 downto 0);
signal re : std_logic;
-- Internal full and empty indicators
signal fulli : std_logic;
signal empti : std_logic;
begin
-----------------------------------------------------------------------------
-- Pointer Logic
genCCN: if not FORCE_XILCY generate
IP1 <= IP0 + 1;
OP1 <= OP0 + 1;
end generate;
genCCY: if FORCE_XILCY generate
component MUXCY
port (
O : out std_ulogic;
CI : in std_ulogic;
DI : in std_ulogic;
S : in std_ulogic
);
end component;
component XORCY
port (
O : out std_ulogic;
CI : in std_ulogic;
LI : in std_ulogic
);
end component;
signal ci, co : std_logic_vector(A_BITS downto 0);
begin
ci(0) <= '1';
genCCI : for i in 0 to A_BITS-1 generate
MUXCY_inst : MUXCY
port map (
O => ci(i+1),
CI => ci(i),
DI => '0',
S => IP0(i)
);
XORCY_inst : XORCY
port map (
O => IP1(i),
CI => ci(i),
LI => IP0(i)
);
end generate genCCI;
co(0) <= '1';
genCCO: for i in 0 to A_BITS-1 generate
MUXCY_inst : MUXCY
port map (
O => co(i+1),
CI => co(i),
DI => '0',
S => OP0(i)
);
XORCY_inst : XORCY
port map (
O => OP1(i),
CI => co(i),
LI => OP0(i)
);
end generate genCCO;
end generate;
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
IP0 <= (others => '0');
IPm <= (others => '0');
OP0 <= (others => '0');
else
-- Update Input Pointer upon Write
if rollback = '1' then
IP0 <= IPm;
elsif we = '1' then
IP0 <= IP1;
end if;
-- Update Commit Marker
if commit = '1' then
if we = '1' then
IPm <= IP1;
else
IPm <= IP0;
end if;
end if;
-- Update Output Pointer upon Read
if re = '1' then
OP0 <= OP1;
end if;
end if;
end if;
end process;
wa <= IP0;
ra <= OP0;
-- Fill State Computation (soft indicators)
process(fulli, IP0, IPm, OP0)
variable d : std_logic_vector(A_BITS-1 downto 0);
begin
-- Available Space
if ESTATE_WR_BITS > 0 then
-- Compute Pointer Difference
if fulli = '1' then
d := (others => '1'); -- true number minus one when full
else
d := std_logic_vector(IP0 - OP0); -- true number of valid entries
end if;
estate_wr <= not d(d'left downto d'left-ESTATE_WR_BITS+1);
else
estate_wr <= (others => 'X');
end if;
-- Available Content
if FSTATE_RD_BITS > 0 then
-- Compute Pointer Difference
if fulli = '1' then
d := (others => '1'); -- true number minus one when full
else
d := std_logic_vector(IPm - OP0); -- true number of valid entries
end if;
fstate_rd <= d(d'left downto d'left-FSTATE_RD_BITS+1);
else
fstate_rd <= (others => 'X');
end if;
end process;
-----------------------------------------------------------------------------
-- Computation of full and empty indications.
--
-- The STATE_REG generic is ignored as two different comparators are
-- needed to compare OP with IPm (empty) and IP with OP (full) anyways.
-- So the register implementation is always used.
blkState: block
signal Ful : std_logic := '0';
signal Pnd : std_logic := '0';
signal Avl : std_logic := '0';
begin
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
Ful <= '0';
Pnd <= '0';
Avl <= '0';
else
-- Pending Indicator for uncommitted Data
if commit = '1' or rollback = '1' then
Pnd <= '0';
elsif we = '1' then
Pnd <= '1';
end if;
-- Update Full Indicator
if re = '1' or (rollback = '1' and Pnd = '1') then
Ful <= '0';
elsif we = '1' and re = '0' and IP1 = OP0 then
Ful <= '1';
end if;
-- Update Empty Indicator
if commit = '1' and (we = '1' or Pnd = '1') then
Avl <= '1';
elsif re = '1' and OP1 = IPm then
Avl <= '0';
end if;
end if;
end if;
end process;
fulli <= Ful;
empti <= not Avl;
end block;
-----------------------------------------------------------------------------
-- Memory Access
-- Write Interface => Input
full <= fulli;
we <= put and not fulli;
-- Backing Memory and Read Interface => Output
genLarge: if not DATA_REG generate
signal do : std_logic_vector(D_BITS-1 downto 0);
begin
-- Backing Memory
ram : ocram_sdp
generic map (
A_BITS => A_BITS,
D_BITS => D_BITS
)
port map (
wclk => clk,
rclk => clk,
wce => '1',
wa => wa,
we => we,
d => din,
ra => ra,
rce => re,
q => do
);
-- Read Interface => Output
genOutputCmb : if not OUTPUT_REG generate
signal Vld : std_logic := '0'; -- valid output of RAM module
begin
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
Vld <= '0';
else
Vld <= (Vld and not got) or not empti;
end if;
end if;
end process;
re <= (not Vld or got) and not empti;
dout <= do;
valid <= Vld;
end generate genOutputCmb;
genOutputReg: if OUTPUT_REG generate
-- Extra Buffer Register for Output Data
signal Buf : std_logic_vector(D_BITS-1 downto 0) := (others => '-');
signal Vld : std_logic_vector(0 to 1) := (others => '0');
-- Vld(0) -- valid output of RAM module
-- Vld(1) -- valid word in Buf
begin
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
Buf <= (others => '-');
Vld <= (others => '0');
else
Vld(0) <= (Vld(0) and Vld(1) and not got) or not empti;
Vld(1) <= (Vld(1) and not got) or Vld(0);
if Vld(1) = '0' or got = '1' then
Buf <= do;
end if;
end if;
end if;
end process;
re <= (not Vld(0) or not Vld(1) or got) and not empti;
dout <= Buf;
valid <= Vld(1);
end generate genOutputReg;
end generate genLarge;
genSmall: if DATA_REG generate
-- Memory modelled as Array
type regfile_t is array(0 to 2**A_BITS-1) of std_logic_vector(D_BITS-1 downto 0);
signal regfile : regfile_t;
attribute ram_style : string; -- XST specific
attribute ram_style of regfile : signal is "distributed";
-- Altera Quartus II: Allow automatic RAM type selection.
-- For small RAMs, registers are used on Cyclone devices and the M512 type
-- is used on Stratix devices. Pass-through logic is automatically added
-- if required. (Warning can be ignored.)
begin
-- Memory State
process(clk)
begin
if rising_edge(clk) then
--synthesis translate_off
if SIMULATION AND (rst = '1') then
regfile <= (others => (others => '-'));
else
--synthesis translate_on
if we = '1' then
regfile(to_integer(wa)) <= din;
end if;
--synthesis translate_off
end if;
--synthesis translate_on
end if;
end process;
-- Memory Output
re <= got and not empti;
dout <= (others => 'X') when Is_X(std_logic_vector(ra)) else
regfile(to_integer(ra));
valid <= not empti;
end generate genSmall;
end rtl;
|
agpl-3.0
|
BBN-Q/APS2-Comms
|
src/tcp_mux.vhd
|
1
|
4021
|
-- Mux streams going to tcp tx: memory write/read response, CPLD tx
-- Cross to the tcp clock
-- Adapt to 8bit wide data path
-- Byte-swaping as necessary
-- Original author: Colm Ryan
-- Copyright 2015, Raytheon BBN Technologies
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.tcp_bridge_pkg.all;
entity tcp_mux is
port (
clk : in std_logic;
rst : in std_logic;
clk_tcp : in std_logic;
rst_tcp : in std_logic;
--memory write/read streams
memory_tx_write_resp_tdata : in std_logic_vector(31 downto 0);
memory_tx_write_resp_tvalid : in std_logic;
memory_tx_write_resp_tlast : in std_logic;
memory_tx_write_resp_tready : out std_logic;
memory_tx_read_resp_tdata : in std_logic_vector(31 downto 0);
memory_tx_read_resp_tvalid : in std_logic;
memory_tx_read_resp_tlast : in std_logic;
memory_tx_read_resp_tready : out std_logic;
--CPLD tx stream
cpld_tx_tdata : in std_logic_vector(31 downto 0);
cpld_tx_tvalid : in std_logic;
cpld_tx_tready : out std_logic;
cpld_tx_tlast : in std_logic;
--TCP tx stream
tcp_tx_tdata : out std_logic_vector(7 downto 0);
tcp_tx_tvalid : out std_logic;
tcp_tx_tready : in std_logic
);
end entity;
architecture arch of tcp_mux is
signal muxed_tdata : std_logic_vector(31 downto 0) := (others => '0');
signal muxed_tvalid, muxed_tlast, muxed_tready : std_logic := '0';
signal muxed_tcp_clk_tdata : std_logic_vector(31 downto 0) := (others => '0');
signal muxed_tcp_clk_tvalid, muxed_tcp_clk_tlast, muxed_tcp_clk_tready : std_logic := '0';
begin
--Mux together all the streams
mux_inst : axis_arb_mux_3
generic map (
DATA_WIDTH => 32,
ARB_TYPE => "ROUND_ROBIN",
LSB_PRIORITY => "HIGH"
)
port map (
clk => clk,
rst => rst,
input_0_axis_tdata => memory_tx_read_resp_tdata,
input_0_axis_tvalid => memory_tx_read_resp_tvalid,
input_0_axis_tready => memory_tx_read_resp_tready,
input_0_axis_tlast => memory_tx_read_resp_tlast,
input_0_axis_tuser => '0',
input_1_axis_tdata => memory_tx_write_resp_tdata,
input_1_axis_tvalid => memory_tx_write_resp_tvalid,
input_1_axis_tready => memory_tx_write_resp_tready,
input_1_axis_tlast => memory_tx_write_resp_tlast,
input_1_axis_tuser => '0',
input_2_axis_tdata => cpld_tx_tdata,
input_2_axis_tvalid => cpld_tx_tvalid,
input_2_axis_tready => cpld_tx_tready,
input_2_axis_tlast => cpld_tx_tlast,
input_2_axis_tuser => '0',
output_axis_tdata => muxed_tdata,
output_axis_tvalid => muxed_tvalid,
output_axis_tready => muxed_tready,
output_axis_tlast => muxed_tlast,
output_axis_tuser => open
);
--Cross to the tcp clock domain
axi2tcp_fifo_inst : axis_async_fifo
generic map (
ADDR_WIDTH => 5,
DATA_WIDTH => 32
)
port map (
async_rst => rst,
input_clk => clk,
input_axis_tdata => muxed_tdata,
input_axis_tvalid => muxed_tvalid,
input_axis_tready => muxed_tready,
input_axis_tlast => muxed_tlast,
input_axis_tuser => '0',
output_clk => clk_tcp,
output_axis_tdata => muxed_tcp_clk_tdata,
output_axis_tvalid => muxed_tcp_clk_tvalid,
output_axis_tready => muxed_tcp_clk_tready,
output_axis_tlast => muxed_tcp_clk_tlast,
output_axis_tuser => open
);
--Convert down to the byte wide data path
to_8bit_adapter_inst : axis_adapter
generic map (
INPUT_DATA_WIDTH => 32,
INPUT_KEEP_WIDTH => 4,
OUTPUT_DATA_WIDTH => 8,
OUTPUT_KEEP_WIDTH => 1
)
port map (
clk => clk_tcp,
rst => rst_tcp,
input_axis_tdata => byte_swap(muxed_tcp_clk_tdata),
input_axis_tkeep => (others => '1'),
input_axis_tvalid => muxed_tcp_clk_tvalid,
input_axis_tready => muxed_tcp_clk_tready,
input_axis_tlast => '0',
input_axis_tuser => '0',
output_axis_tdata => tcp_tx_tdata,
output_axis_tkeep => open,
output_axis_tvalid => tcp_tx_tvalid,
output_axis_tready => tcp_tx_tready,
output_axis_tlast => open,
output_axis_tuser => open
);
end architecture;
|
mpl-2.0
|
sils1297/HWPrak14
|
task_2/project_2/project_2.srcs/sources_1/new/Dimmer.vhd
|
1
|
1328
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Toggles the LED state every half second
entity Dimmer is
generic (
WIDTH : integer := 25
);
port (
LED : out std_ulogic_vector(3 downto 0);
CLK_66MHZ : in std_ulogic
);
end;
architecture DimmerArchitecture of Dimmer is
signal counter : unsigned(WIDTH downto 0) := (others => '0'); -- that makes 67108864 bit combinations
signal duty_cycle : unsigned (7 downto 0) := (others => '0');
signal state: unsigned (2 downto 0) := (others => '0');
begin
ledpwm : entity work.LEDPWM(Behavioral)
port map (
LED => LED,
CLK_66MHZ => CLK_66MHZ,
duty_cycle => duty_cycle
);
counterProcess : process(CLK_66MHZ)
begin
if(rising_edge(CLK_66MHZ)) then
counter <= counter + 1;
if(counter = 0) then
case state is
when "000" => duty_cycle <= "00000000"; --0
when "001" => duty_cycle <= "00011001"; --25
when "010" => duty_cycle <= "00110010"; --50
when "011" => duty_cycle <= "01001011"; --75
when "100" => duty_cycle <= "01100100"; --100
when "101" => duty_cycle <= "10010110"; --150
when "110" => duty_cycle <= "11001000"; --200
when "111" => duty_cycle <= "11111111"; --255
when others => null;
end case;
state <= state + 1;
end if;
end if;
end process;
end DimmerArchitecture;
|
agpl-3.0
|
sils1297/HWPrak14
|
task_4/project_1.srcs/sources_1/new/Register.vhd
|
1
|
607
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity SimpleRegister is
generic(
WIDTH : integer := 16
);
Port(
inval : in std_ulogic_vector(WIDTH - 1 downto 0);
outval : out std_ulogic_vector(WIDTH - 1 downto 0);
set : in std_ulogic;
reset : in std_ulogic;
clock : in std_ulogic
);
end SimpleRegister;
architecture Behavioral of SimpleRegister is
begin
process(clock, set)
begin
if reset = '1' then
outval <= (others => '0');
else
if set = '1' and rising_edge(clock) then
outval <= inval;
end if;
end if;
end process;
end Behavioral;
|
agpl-3.0
|
sils1297/HWPrak14
|
task_3/task_3.srcs/sim_1/new/test.vhd
|
1
|
3435
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ADS7830 is
generic (I2C_ADR : std_logic_vector(6 downto 0) := "1001000"
);
port (
SDA : inout std_logic;
SCL : in std_logic
);
end ADS7830;
architecture RTL of ADS7830 is
constant CMD_WORD : std_logic_vector(7 downto 0) := x"8C";
constant MEM_WORD : std_logic_vector(7 downto 0) := x"55"; --x"9A";
signal SDA_latched : std_logic := '1';
signal start_or_stop : std_logic;
signal bitcnt : unsigned(3 downto 0) := "1111"; -- counts the I2C bits from 7 downto 0, plus an ACK bit
signal bit_DATA : std_logic;
signal bit_ACK : std_logic;
signal data_phase : std_logic := '0';
signal adr_phase : std_logic;
signal adr_match : std_logic := '0';
signal op_read : std_logic := '0';
signal mem : std_logic_vector(7 downto 0) := MEM_WORD;
signal op_write : std_logic;
signal mem_bit_low : std_logic;
signal SDA_assert_low : std_logic;
signal SDA_assert_ACK : std_logic;
signal SDA_low : std_logic;
signal adr_reg : std_logic_vector(6 downto 0) := "0000000";
signal SDA_int : std_logic;
signal SCL_int : std_logic;
signal initialized : std_logic := '0';
signal SDA_edge : std_logic;
begin
-- for simulation only
SDA_int <= '0' when SDA = '0' else '1';
SCL_int <= '0' when SCL = '0' else '1';
-- We use two wires with a combinatorial loop to detect the start and stop conditions
-- making sure these two wires don't get optimized away
SDA_latched <= SDA_int when (SCL_int = '0') else --((SCL_int = '0') or (start_or_stop = '1')) else
SDA_latched;
SDA_edge <= SDA_int xor SDA_latched;
start_or_stop <= '0' when (SCL_int = '0') else
SDA_edge;
bit_ACK <= bitcnt(3); -- the ACK bit is the 9th bit sent
bit_DATA <= not bit_ACK;
bitcounter: process (SCL_int, start_or_stop)
begin
if (start_or_stop = '1') then
bitcnt <= x"7"; -- the bit 7 is received first
data_phase <= '0';
elsif (SCL_int'event and SCL_int = '0') then
if (bit_ACK = '1') then
bitcnt <= x"7";
data_phase <= '1';
else
bitcnt <= bitcnt - 1;
end if;
end if;
end process;
adr_phase <= not data_phase;
op_write <= not op_read;
regs: process (SCL_int, start_or_stop)
variable cmd_reg : std_logic_vector(7 downto 0) := x"00";
begin
if (start_or_stop = '1') then
adr_match <= '0';
op_read <= '0';
elsif (SCL_int'event and SCL_int = '1') then
if (adr_phase = '1') then
if (bitcnt > "000") then
adr_reg <= adr_reg(5 downto 0) & SDA_int;
else
op_read <= SDA_int;
if (adr_reg = I2C_ADR(6 downto 0)) then
adr_match <= '1';
end if;
end if;
end if;
if (data_phase='1' and adr_match = '1') then
if (op_write='1' and initialized='0') then
if (bitcnt >= "000") then
cmd_reg := cmd_reg(6 downto 0) & SDA_int;
end if;
if (bitcnt = "000" and cmd_reg = CMD_WORD) then
initialized <= '1';
end if;
end if;
end if;
end if;
end process;
mem_bit_low <= not mem(to_integer(bitcnt(2 downto 0)));
SDA_assert_low <= adr_match and bit_DATA and data_phase and op_read and mem_bit_low and initialized;
SDA_assert_ACK <= adr_match and bit_ACK and (adr_phase or op_write);
SDA_low <= SDA_assert_low or SDA_assert_ACK;
SDA <= '0' when (SDA_low = '1') else 'Z';
end RTL;
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agpl-3.0
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