repo_name
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stringlengths 1
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stringlengths 0
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⌀ | license
stringclasses 15
values |
|---|---|---|---|---|---|
masson2013/heterogeneous_hthreads
|
src/platforms/xilinx/ml605_pr_smp1_14_7/design/pcores/plb_scheduler_v1_00_a/devl/bfmsim/simulation/behavioral/synch_bus_wrapper.vhd
|
6
|
975
|
-------------------------------------------------------------------------------
-- synch_bus_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library bfm_synch_v1_00_a;
use bfm_synch_v1_00_a.all;
entity synch_bus_wrapper is
port (
FROM_SYNCH_OUT : in std_logic_vector(0 to 127);
TO_SYNCH_IN : out std_logic_vector(0 to 31)
);
end synch_bus_wrapper;
architecture STRUCTURE of synch_bus_wrapper is
component bfm_synch is
generic (
C_NUM_SYNCH : integer
);
port (
FROM_SYNCH_OUT : in std_logic_vector(0 to (C_NUM_SYNCH*32)-1);
TO_SYNCH_IN : out std_logic_vector(0 to 31)
);
end component;
begin
synch_bus : bfm_synch
generic map (
C_NUM_SYNCH => 4
)
port map (
FROM_SYNCH_OUT => FROM_SYNCH_OUT,
TO_SYNCH_IN => TO_SYNCH_IN
);
end architecture STRUCTURE;
|
bsd-3-clause
|
masson2013/heterogeneous_hthreads
|
src/platforms/xilinx/smp3_opbhwti/design/pcores/opb_v20_v1_10_d/hdl/vhdl/pf_occ_counter_top.vhd
|
3
|
12665
|
-------------------------------------------------------------------------------
-- $Id: pf_occ_counter_top.vhd,v 1.1.2.1 2009/10/06 21:15:01 gburch Exp $
-------------------------------------------------------------------------------
-- pf_occ_counter_top - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pf_occ_counter_top.vhd
--
-- Description: Implements parameterized up/down counter
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pf_occ_counter_top.vhd
--
-------------------------------------------------------------------------------
-- Author: D. Thorpe
-- Revision: $Revision: 1.1.2.1 $
-- Date: $Date: 2009/10/06 21:15:01 $
--
-- History:
-- DET 2001-08-30 First Version
--
--
--
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
--Use IEEE.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
library opb_v20_v1_10_d;
use opb_v20_v1_10_d.pf_occ_counter;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity pf_occ_counter_top is
generic (
C_COUNT_WIDTH : integer := 10
);
port (
Clk : in std_logic;
Rst : in std_logic;
Load_Enable : in std_logic;
Load_value : in std_logic_vector(0 to C_COUNT_WIDTH-1);
Count_Down : in std_logic;
Count_Up : in std_logic;
By_2 : In std_logic;
Count_Out : out std_logic_vector(0 to C_COUNT_WIDTH-1);
almost_full : Out std_logic;
full : Out std_logic;
almost_empty : Out std_logic;
empty : Out std_logic
);
end entity pf_occ_counter_top;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of pf_occ_counter_top is
Signal sig_cnt_enable : std_logic;
Signal sig_cnt_up_n_dwn : std_logic;
Signal sig_carry_out : std_logic;
Signal sig_count_out : std_logic_vector(0 to C_COUNT_WIDTH-1);
Signal upper_cleared : std_logic;
Signal lower_set : std_logic;
Signal lower_cleared : std_logic;
Signal empty_state : std_logic_vector(0 to 2);
Signal full_state : std_logic_vector(0 to 3);
Signal sig_full : std_logic;
Signal sig_almost_full : std_logic;
Signal sig_going_full : std_logic;
Signal sig_empty : std_logic;
Signal sig_almost_empty : std_logic;
begin -- VHDL_RTL
full <= sig_full;
almost_full <= sig_almost_full;
empty <= sig_empty;
almost_empty <= sig_almost_empty;
-- Misc signal assignments
Count_Out <= sig_count_out;
sig_cnt_enable <= (Count_Up and not(sig_full))
xor (Count_Down and not(sig_empty));
sig_cnt_up_n_dwn <= not(Count_Up);
I_UP_DWN_COUNTER : entity opb_v20_v1_10_d.pf_occ_counter
generic map (
C_COUNT_WIDTH
)
port map(
Clk => Clk,
Rst => Rst,
Carry_Out => sig_carry_out,
Load_In => Load_value,
Count_Enable => sig_cnt_enable,
Count_Load => Load_Enable,
Count_Down => sig_cnt_up_n_dwn,
Cnt_by_2 => By_2,
Count_Out => sig_count_out
);
TEST_UPPER_BITS : process (sig_count_out)
Variable all_cleared : boolean;
Variable loop_count : integer;
Begin
--loop_count := 0;
all_cleared := True;
for loop_count in 0 to C_COUNT_WIDTH-2 loop
If (sig_count_out(loop_count) = '1') Then
all_cleared := False;
else
null;
End if;
End loop;
-- -- Search through the upper counter bits starting with the MSB
-- while (loop_count < C_COUNT_WIDTH-2) loop
--
-- If (sig_count_out(loop_count) = '1') Then
-- all_cleared := False;
-- else
-- null;
-- End if;
--
-- loop_count := loop_count + 1;
--
-- End loop;
-- now assign the outputs
If (all_cleared) then
upper_cleared <= '1';
else
upper_cleared <= '0';
End if;
End process TEST_UPPER_BITS;
empty_state <= upper_cleared & sig_count_out(C_COUNT_WIDTH-2) &
sig_count_out(C_COUNT_WIDTH-1);
STATIC_EMPTY_DETECT : process (empty_state)
Begin
Case empty_state Is
When "100" =>
sig_empty <= '1';
sig_almost_empty <= '0';
When "101" =>
sig_empty <= '0';
sig_almost_empty <= '1';
When "110" =>
sig_empty <= '0';
sig_almost_empty <= '0';
When others =>
sig_empty <= '0';
sig_almost_empty <= '0';
End case;
End process STATIC_EMPTY_DETECT;
TEST_LOWER_BITS : process (sig_count_out)
Variable all_cleared : boolean;
Variable all_set : boolean;
Variable loop_count : integer;
Begin
--loop_count := 1;
all_set := True;
all_cleared := True;
for loop_count in 1 to C_COUNT_WIDTH-1 loop
If (sig_count_out(loop_count) = '0') Then
all_set := False;
else
all_cleared := False;
End if;
End loop;
-- -- Search through the lower counter bits starting with the MSB+1
-- while (loop_count < C_COUNT_WIDTH-1) loop
--
-- If (sig_count_out(loop_count) = '0') Then
-- all_set := False;
-- else
-- all_cleared := False;
-- End if;
--
-- loop_count := loop_count + 1;
--
-- End loop;
-- now assign the outputs
If (all_cleared) then
lower_cleared <= '1';
lower_set <= '0';
elsif (all_set) Then
lower_cleared <= '0';
lower_set <= '1';
else
lower_cleared <= '0';
lower_set <= '0';
End if;
End process TEST_LOWER_BITS;
full_state <= sig_count_out(0)
& lower_set
& lower_cleared
& sig_count_out(C_COUNT_WIDTH-1);
STATIC_FULL_DETECT : process (full_state, sig_count_out)
Begin
sig_full <= sig_count_out(0); -- MSB set implies full
Case full_state Is
When "0100" =>
sig_almost_full <= '0';
sig_going_full <= '1';
When "0101" =>
sig_almost_full <= '1';
sig_going_full <= '0';
When others =>
sig_almost_full <= '0';
sig_going_full <= '0';
End case;
End process STATIC_FULL_DETECT;
end architecture implementation;
|
bsd-3-clause
|
masson2013/heterogeneous_hthreads
|
src/platforms/xilinx/smp3_opbhwti/design/pcores/opb_ipif_v2_00_h/hdl/vhdl/pf_counter_top.vhd
|
3
|
4524
|
-------------------------------------------------------------------------------
-- $Id: pf_counter_top.vhd,v 1.2 2004/11/23 01:04:03 jcanaris Exp $
-------------------------------------------------------------------------------
-- pf_counter_top - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: pf_counter_top.vhd
--
-- Description: Implements parameterized up/down counter
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pf_counter_top.vhd
--
-------------------------------------------------------------------------------
-- Author: D. Thorpe
-- Revision: $Revision: 1.2 $
-- Date: $Date: 2004/11/23 01:04:03 $
--
-- History:
-- DET 2001-08-30 First Version
-- LCW Nov 8, 2004 -- updated for NCSim
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
--Use IEEE.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
library opb_ipif_v2_00_h;
use opb_ipif_v2_00_h.pf_counter;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity pf_counter_top is
generic (
C_COUNT_WIDTH : integer := 10
);
port (
Clk : in std_logic;
Rst : in std_logic;
Load_Enable : in std_logic;
Load_value : in std_logic_vector(0 to C_COUNT_WIDTH-1);
Count_Down : in std_logic;
Count_Up : in std_logic;
--Carry_Out : out std_logic;
Count_Out : out std_logic_vector(0 to C_COUNT_WIDTH-1)
);
end entity pf_counter_top;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of pf_counter_top is
Signal sig_cnt_enable : std_logic;
Signal sig_cnt_up_n_dwn : std_logic;
Signal sig_carry_out : std_logic;
Signal sig_count_out : std_logic_vector(0 to C_COUNT_WIDTH-1);
begin -- VHDL_RTL
-- Misc signal assignments
Count_Out <= sig_count_out;
--Carry_Out <= sig_carry_Out;
sig_cnt_enable <= Count_Up xor Count_Down;
sig_cnt_up_n_dwn <= not(Count_Up);
I_UP_DWN_COUNTER : entity opb_ipif_v2_00_h.pf_counter
generic map (
C_COUNT_WIDTH => C_COUNT_WIDTH
)
port map(
Clk => Clk, -- : in std_logic;
Rst => Rst, -- : in std_logic;
Carry_Out => sig_carry_out, -- : out std_logic;
Load_In => Load_value, -- : in std_logic_vector(0 to C_COUNT_WIDTH-1);
Count_Enable => sig_cnt_enable, -- : in std_logic;
Count_Load => Load_Enable, -- : in std_logic;
Count_Down => sig_cnt_up_n_dwn,-- : in std_logic;
Count_Out => sig_count_out -- : out std_logic_vector(0 to C_COUNT_WIDTH-1)
);
end architecture implementation;
|
bsd-3-clause
|
masson2013/heterogeneous_hthreads
|
src/hardware/MyRepository/pcores/hvm_core_v1_00_a/hdl/vhdl/hvm_core.vhd
|
2
|
4127
|
----------------------------------------------------------------------------------
-- Written by Jason Agron
-- Summer '07
-- ******************************
-- Company:
-- Engineer:
--
-- Create Date: 15:25:12 12/22/2006
-- Design Name:
-- Module Name: hvm_core - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISPM;
--use UNISPM.VComponents.all;
library hvm_core_v1_00_a;
use hvm_core_v1_00_a.all;
entity hvm_core is
port(
clk : in std_logic;
reset : in std_logic;
go : IN std_logic;
done : OUT std_logic;
mode : IN std_logic_vector(0 to 1);
debug_address : out std_logic_vector(0 to 31);
debug_data : out std_logic_vector(0 to 31);
BRAM_Clk_PM : out std_logic;
BRAM_EN_PM : out std_logic;
BRAM_WE_PM : out std_logic_vector(0 to 3);
BRAM_Addr_PM : out std_logic_vector(0 to 31);
BRAM_Din_PM : in std_logic_vector(0 to 31);
BRAM_Dout_PM : out std_logic_vector(0 to 31);
BRAM_Clk_SM : out std_logic;
BRAM_EN_SM : out std_logic;
BRAM_WE_SM : out std_logic_vector(0 to 3);
BRAM_Addr_SM : out std_logic_vector(0 to 31);
BRAM_Din_SM : in std_logic_vector(0 to 31);
BRAM_Dout_SM : out std_logic_vector(0 to 31)
);
end hvm_core;
architecture Behavioral of hvm_core is
COMPONENT interp
PORT(
prog_mem_dOUT0 : IN std_logic_vector(0 to 31);
state_mem_dOUT0 : IN std_logic_vector(0 to 31);
go : IN std_logic;
mode : IN std_logic_vector(0 to 1);
done : out std_logic;
clock_sig : IN std_logic;
reset_sig : IN std_logic;
prog_mem_addr0 : OUT std_logic_vector(0 to 31);
prog_mem_dIN0 : OUT std_logic_vector(0 to 31);
prog_mem_rENA0 : OUT std_logic;
prog_mem_wENA0 : OUT std_logic;
state_mem_addr0 : OUT std_logic_vector(0 to 7);
state_mem_dIN0 : OUT std_logic_vector(0 to 31);
state_mem_rENA0 : OUT std_logic;
state_mem_wENA0 : OUT std_logic
);
END COMPONENT;
SIGNAL prog_mem_dOUT0 : std_logic_vector(0 to 31);
SIGNAL state_mem_dOUT0 : std_logic_vector(0 to 31);
SIGNAL prog_mem_addr0 : std_logic_vector(0 to 31);
SIGNAL prog_mem_dIN0 : std_logic_vector(0 to 31);
SIGNAL prog_mem_rENA0 : std_logic;
SIGNAL prog_mem_wENA0 : std_logic;
SIGNAL state_mem_addr0 : std_logic_vector(0 to 7);
SIGNAL state_mem_dIN0 : std_logic_vector(0 to 31);
SIGNAL state_mem_rENA0 : std_logic;
SIGNAL state_mem_wENA0 : std_logic;
begin
-- Instantiate the Unit Under Test (UUT)
uut: interp PORT MAP(
prog_mem_addr0 => prog_mem_addr0,
prog_mem_dIN0 => prog_mem_dIN0,
prog_mem_dOUT0 => prog_mem_dOUT0,
prog_mem_rENA0 => prog_mem_rENA0,
prog_mem_wENA0 => prog_mem_wENA0,
state_mem_addr0 => state_mem_addr0,
state_mem_dIN0 => state_mem_dIN0,
state_mem_dOUT0 => state_mem_dOUT0,
state_mem_rENA0 => state_mem_rENA0,
state_mem_wENA0 => state_mem_wENA0,
go => go,
done => done,
mode => mode,
clock_sig => clk,
reset_sig => reset
);
-- Old method (before done was internal to the interpreter)
-- done <= '1' when prog_mem_addr0 = x"FFFFFFFF" else '0';
-- Hook up debug interface
debug_address <= prog_mem_addr0;
debug_data <= prog_mem_dOUT0;
-- Connect up PM BRAM interface
BRAM_Clk_PM <= clk;
BRAM_EN_PM <= prog_mem_rENA0;
BRAM_WE_PM <= prog_mem_wENA0 & prog_mem_wENA0 & prog_mem_wENA0 & prog_mem_wENA0;
BRAM_Addr_PM <= prog_mem_addr0;
prog_mem_dOUT0 <= BRAM_Din_PM;
BRAM_Dout_PM <= prog_mem_dIN0;
-- Connect up SM BRAM interface
BRAM_Clk_SM <= clk;
BRAM_EN_SM <= state_mem_rENA0;
BRAM_WE_SM <= state_mem_wENA0 & state_mem_wENA0 & state_mem_wENA0 & state_mem_wENA0;
BRAM_Addr_SM <= x"00000" & "00" & state_mem_addr0 & "00"; -- Make addresses word addressable
state_mem_dOUT0 <= BRAM_Din_SM;
BRAM_Dout_SM <= state_mem_dIN0;
end Behavioral;
|
bsd-3-clause
|
masson2013/heterogeneous_hthreads
|
src/platforms/xilinx/smp3_opbhwti/design/pcores/opb_ipif_v2_00_h/hdl/vhdl/rdpfifo_dp_cntl.vhd
|
3
|
28824
|
-------------------------------------------------------------------------------
-- $Id: rdpfifo_dp_cntl.vhd,v 1.2 2004/11/23 01:04:03 jcanaris Exp $
-------------------------------------------------------------------------------
--rdpfifo_dp_cntl.vhd
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: rdpfifo_dp_cntl.vhd
--
-- Description: This VHDL design file is for the Mauna Loa Read Packet
-- FIFO Dual Port Control block and the status
-- calculations for the Occupancy, Vacancy, Full, and Empty.
--
-------------------------------------------------------------------------------
-- Structure: This is the hierarchical structure of the RPFIFO design.
--
--
-- rdpfifo_dp_cntl.vhd
-- |
-- |
-- |-- pf_counter_top.vhd
-- | |
-- | |-- pf_counter.vhd
-- | |
-- | |-- pf_counter_bit.vhd
-- |
-- |
-- |-- pf_occ_counter_top.vhd
-- | |
-- | |-- occ_counter.vhd
-- | |
-- | |-- pf_counter_bit.vhd
-- |
-- |-- pf_adder.vhd
-- |
-- |-- pf_adder_bit.vhd
--
--
--
-------------------------------------------------------------------------------
-- Author: Doug Thorpe
--
-- History:
-- DET August 15, 2001 -- Initial version adapted from pt design
--
-- DET Sept. 21, 2001 -- Size Optimized redesign and parameterization
-- LCW Nov 8, 2004 -- updated for NCSim
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
---------------------------------------------------------------------
-- Library definitions
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.std_logic_arith.all;
library ieee;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
library opb_ipif_v2_00_h;
use opb_ipif_v2_00_h.pf_counter_top;
use opb_ipif_v2_00_h.pf_occ_counter_top;
use opb_ipif_v2_00_h.pf_adder;
-------------------------------------------------------------------------------
entity rdpfifo_dp_cntl is
Generic (
C_DP_ADDRESS_WIDTH : Integer := 9;
-- number of bits needed for dual port addressing
-- of requested FIFO depth
C_INCLUDE_PACKET_MODE : Boolean := true;
-- Select for inclusion/ommision of packet mode
-- features
C_INCLUDE_VACANCY : Boolean := true
-- Enable for Vacancy calc feature
);
port (
-- Inputs
Bus_rst : In std_logic;
Bus_clk : In std_logic;
Rdreq : In std_logic;
Wrreq : In std_logic;
Burst_rd_xfer : In std_logic;
Mark : In std_logic;
Restore : In std_logic;
Release : In std_logic;
-- Outputs
WrAck : Out std_logic;
RdAck : Out std_logic;
Full : Out std_logic;
Empty : Out std_logic;
Almost_Full : Out std_logic;
Almost_Empty : Out std_logic;
DeadLock : Out std_logic;
Occupancy : Out std_logic_vector(0 to C_DP_ADDRESS_WIDTH);
Vacancy : Out std_logic_vector(0 to C_DP_ADDRESS_WIDTH);
DP_core_wren : Out std_logic;
Wr_Addr : Out std_logic_vector(0 to C_DP_ADDRESS_WIDTH-1);
DP_core_rden : Out std_logic;
Rd_Addr : Out std_logic_vector(0 to C_DP_ADDRESS_WIDTH-1)
);
end rdpfifo_dp_cntl ;
-------------------------------------------------------------------------------
architecture implementation of rdpfifo_dp_cntl is
-- Components
-- CONSTANTS
Constant OCC_CNTR_WIDTH : integer := C_DP_ADDRESS_WIDTH+1;
Constant ADDR_CNTR_WIDTH : integer := C_DP_ADDRESS_WIDTH;
Constant MAX_OCCUPANCY : integer := 2**ADDR_CNTR_WIDTH;
Constant LOGIC_LOW : std_logic := '0';
-- shared signals
signal sig_normal_occupancy : std_logic_vector(0 to OCC_CNTR_WIDTH-1);
-------------------------------------------------------------------------------
----------------- start architecture logic ------------------------------------
begin
------------------------------------------------------------------------------
-- Generate the Read PFIFO with packetizing features included
------------------------------------------------------------------------------
INCLUDE_PACKET_FEATURES : if (C_INCLUDE_PACKET_MODE = true) generate
--TYPES
type transition_state_type is (
reset1,
normal_op,
packet_op,
rest1,
mark1,
rls1,
pkt_update,
nml_update
);
--INTERNAL SIGNALS
signal int_full : std_logic;
signal int_full_dly1 : std_logic;
signal int_full_dly2 : std_logic;
signal int_almost_full : std_logic;
signal int_empty : std_logic;
signal int_almost_empty : std_logic;
Signal int_almost_empty_dly1 : std_logic;
Signal int_empty_dly1 : std_logic;
Signal trans_state : transition_state_type;
signal hold_ack : std_logic;
Signal inc_rd_addr : std_logic;
Signal decr_rd_addr : std_logic;
Signal inc_wr_addr : std_logic;
Signal inc_mark_addr : std_logic;
Signal rd_backup : std_logic;
Signal dummy_empty : std_logic;
Signal dummy_almost_empty : std_logic;
Signal dummy_full : std_logic;
Signal dummy_almost_full : std_logic;
signal ld_occ_norm_into_mark : std_logic;
signal ld_addr_mark_into_write : std_logic;
signal ld_addr_write_into_mark : std_logic;
signal ld_occ_mark_into_norm : std_logic;
signal enable_mark_addr_inc : std_logic;
signal enable_wr_addr_inc : std_logic;
signal enable_rd_addr_inc : std_logic;
signal enable_rd_addr_decr : std_logic;
signal sig_mark_occupancy : std_logic_vector(0 to OCC_CNTR_WIDTH-1);
signal write_address : std_logic_vector(0 to ADDR_CNTR_WIDTH-1);
signal mark_address : std_logic_vector(0 to ADDR_CNTR_WIDTH-1);
signal read_address : std_logic_vector(0 to ADDR_CNTR_WIDTH-1);
signal sig_zeros : std_logic_vector(0 to ADDR_CNTR_WIDTH-1);
signal inc_nocc : std_logic;
signal inc_mocc : std_logic;
signal inc_nocc_by_2 : std_logic;
signal inc_mocc_by_2 : std_logic;
begin
--Misc I/O Assignments
Full <= int_full;
Almost_Full <= int_almost_full;
Empty <= int_empty; -- Align Empty flag with the DP occupancy
Almost_Empty <= int_almost_empty; -- Align Almost_Empty flag with the
-- DP occupancy
Occupancy <= sig_mark_occupancy;
Wr_Addr <= write_address;
Rd_Addr <= read_address;
WrAck <= inc_wr_addr; -- currently combinitorial
RdAck <= inc_rd_addr; -- currently combinitorial
DeadLock <= int_full and int_empty; -- both full and empty at
-- the same time
DP_core_rden <= not(int_empty)-- assert read enable when not empty
or Bus_rst; -- or during reset
DP_core_wren <= not(int_full) -- assert write enable when not full
or Bus_rst; -- or during reset
-----------------------------------------------------------------------
-- Main Transition sequence state machine
-----------------------------------------------------------------------
TRANSITION_STATE_PROCESS : process (Bus_rst, Bus_Clk)
Begin
If (Bus_rst = '1') Then
trans_state <= reset1;
hold_ack <= '1';
ld_occ_norm_into_mark <= '0';
ld_addr_mark_into_write <= '0';
ld_addr_write_into_mark <= '0';
ld_occ_mark_into_norm <= '0';
enable_mark_addr_inc <= '0';
enable_wr_addr_inc <= '0';
enable_rd_addr_inc <= '0';
enable_rd_addr_decr <= '0';
Elsif (Bus_Clk'event and Bus_Clk = '1') Then
-- set default values
trans_state <= reset1;
hold_ack <= '1';
ld_occ_norm_into_mark <= '0';
ld_addr_mark_into_write <= '0';
ld_addr_write_into_mark <= '0';
ld_occ_mark_into_norm <= '0';
enable_mark_addr_inc <= '0';
enable_wr_addr_inc <= '0';
enable_rd_addr_inc <= '1';
enable_rd_addr_decr <= '1';
Case trans_state Is
When reset1 =>
trans_state <= normal_op;
hold_ack <= '1';
enable_rd_addr_inc <= '0';
enable_rd_addr_decr <= '0';
When normal_op => -- Ignore restore and release inputs
-- during normal op
enable_mark_addr_inc <= '1';
enable_wr_addr_inc <= '1';
enable_rd_addr_inc <= '1';
enable_rd_addr_decr <= '1';
If (Mark = '1') Then -- transition to packet op on a
-- Mark command
trans_state <= mark1;
hold_ack <= '1';
else
trans_state <= normal_op;
hold_ack <= '0';
End if;
When packet_op =>
enable_wr_addr_inc <= '1';
enable_rd_addr_inc <= '1';
enable_rd_addr_decr <= '1';
If (Restore = '1') Then
trans_state <= rest1;
hold_ack <= '1';
Elsif (Mark = '1') Then
trans_state <= mark1;
hold_ack <= '1';
Elsif (Release = '1') Then
trans_state <= rls1;
hold_ack <= '1';
else
trans_state <= packet_op;
hold_ack <= '0';
End if;
When rest1 =>
trans_state <= pkt_update;
hold_ack <= '1';
ld_addr_mark_into_write <= '1'; -- load the mark address into
-- the wr cntr
ld_occ_mark_into_norm <= '1'; -- load the marked occupancy
-- into the normal occupancy
-- cntr
When mark1 =>
trans_state <= pkt_update;
hold_ack <= '1';
ld_occ_norm_into_mark <= '1'; -- load the normal occupancy
-- into mark occupancy cntr
ld_addr_write_into_mark <= '1'; -- load the write address
-- into mark register
When rls1 =>
trans_state <= nml_update;
hold_ack <= '1';
ld_occ_norm_into_mark <= '1'; -- load the normal occupancy
-- into mark occupancy cntr
ld_addr_write_into_mark <= '1'; -- load the write address
-- into mark register
When nml_update =>
trans_state <= normal_op;
hold_ack <= '0';
When pkt_update =>
trans_state <= packet_op;
hold_ack <= '0';
When others =>
trans_state <= normal_op;
hold_ack <= '0';
End case;
Else
null;
End if;
End process; -- TRANSITION_STATE_PROCESS
--------------------------------------------------------------------------
-- Instantiate the Occupancy Counter relative to marking operations
-- This counter establishes the empty flag states
--------------------------------------------------------------------------
inc_mocc_by_2 <= decr_rd_addr and inc_mark_addr;
inc_mocc <= decr_rd_addr or inc_mark_addr;
I_MARK_OCCUPANCY : entity opb_ipif_v2_00_h.pf_occ_counter_top
generic map(
C_COUNT_WIDTH => OCC_CNTR_WIDTH
)
port map(
Clk => Bus_clk,
Rst => Bus_rst,
Load_Enable => ld_occ_norm_into_mark,
Load_value => sig_normal_occupancy,
Count_Down => inc_rd_addr,
Count_Up => inc_mocc,
By_2 => inc_mocc_by_2,
Count_Out => sig_mark_occupancy,
almost_full => dummy_almost_full,
full => dummy_full,
almost_empty => int_almost_empty,
empty => int_empty
);
--------------------------------------------------------------------------
-- Instantiate the Occupancy Counter relative to normal operations
-- This counter establishes the full flag states.
--------------------------------------------------------------------------
inc_nocc_by_2 <= decr_rd_addr and inc_wr_addr;
inc_nocc <= decr_rd_addr or inc_wr_addr;
I_NORMAL_OCCUPANCY : entity opb_ipif_v2_00_h.pf_occ_counter_top
generic map(
C_COUNT_WIDTH => OCC_CNTR_WIDTH
)
port map(
Clk => Bus_clk,
Rst => Bus_rst,
Load_Enable => ld_occ_mark_into_norm,
Load_value => sig_mark_occupancy,
Count_Down => inc_rd_addr,
Count_Up => inc_nocc,
By_2 => inc_nocc_by_2,
Count_Out => sig_normal_occupancy,
almost_full => int_almost_full,
full => int_full,
almost_empty => dummy_almost_empty,
empty => dummy_empty
);
--------------------------------------------------------------------------
-- Register and delay Full/Empty flags
--------------------------------------------------------------------------
REGISTER_FLAG_PROCESS : process (Bus_rst, Bus_Clk)
Begin
If (Bus_rst = '1') Then
int_full_dly1 <= '0';
int_full_dly2 <= '0';
int_almost_empty_dly1 <= '0';
int_empty_dly1 <= '1';
Elsif (Bus_Clk'event and Bus_Clk = '1') Then
int_full_dly1 <= int_full;
int_full_dly2 <= int_full_dly1;
int_almost_empty_dly1 <= int_almost_empty;
int_empty_dly1 <= int_empty;
Else
null;
End if;
End process; -- REGISTER_FLAG_PROCESS
--------------------------------------------------------------------------
-- Write Address Counter Logic
inc_wr_addr <= WrReq
and not(int_full)
and not(int_full_dly1)
and not(int_full_dly2)
and not(hold_ack)
and not(rd_backup and int_almost_full)
and enable_wr_addr_inc;
I_WRITE_ADDR_CNTR : entity opb_ipif_v2_00_h.pf_counter_top
Generic Map (
C_COUNT_WIDTH => ADDR_CNTR_WIDTH
)
Port Map (
Clk => Bus_Clk,
Rst => Bus_rst,
Load_Enable => ld_addr_mark_into_write,
Load_value => mark_address,
Count_Down => '0',
Count_Up => inc_wr_addr,
Count_Out => write_address
);
-- end of write counter logic
--------------------------------------------------------------------------
--------------------------------------------------------------------------
-- Read Address Counter Logic
-----------------------------------------------------------------------
-- Detect end of burst read by IP and set backup condition
-----------------------------------------------------------------------
DETECT_RDCNT_BACKUP : process (Burst_rd_xfer, RdReq, int_empty_dly1)
Begin
if (Burst_rd_xfer = '1'
and RdReq = '0'
and int_empty_dly1 = '0') then
rd_backup <= '1';
else
rd_backup <= '0';
end if;
End process; -- DETECT_RDCNT_BACKUP
inc_rd_addr <= RdReq
and not(int_empty)
and not(int_empty_dly1)
and enable_rd_addr_inc;
decr_rd_addr <= rd_backup
and enable_rd_addr_decr;
sig_zeros <= (others => '0');
I_READ_ADDR_CNTR : entity opb_ipif_v2_00_h.pf_counter_top
Generic Map ( C_COUNT_WIDTH => ADDR_CNTR_WIDTH
)
Port Map (
Clk => Bus_Clk,
Rst => Bus_rst,
Load_Enable => '0',
Load_value => sig_zeros,
Count_Down => decr_rd_addr,
Count_Up => inc_rd_addr,
Count_Out => read_address
);
-- end read address counter logic
--------------------------------------------------------------------------
--------------------------------------------------------------------------
-- Mark Register Control
inc_mark_addr <= inc_wr_addr
and enable_mark_addr_inc;
I_MARKREG_ADDR_CNTR : entity opb_ipif_v2_00_h.pf_counter_top
Generic Map ( C_COUNT_WIDTH => ADDR_CNTR_WIDTH
)
Port Map (
Clk => Bus_Clk,
Rst => Bus_rst,
Load_Enable => ld_addr_write_into_mark,
Load_value => write_address,
Count_Down => '0',
Count_Up => inc_mark_addr,
Count_Out => mark_address
);
-- end mark address counter logic
--------------------------------------------------------------------------
end generate INCLUDE_PACKET_FEATURES;
------------------------------------------------------------------------------
-- Generate the Read PFIFO with no packetizing features
------------------------------------------------------------------------------
OMIT_PACKET_FEATURES : if (C_INCLUDE_PACKET_MODE = false) generate
--Internal Signals
signal int_almost_full : std_logic;
signal int_full : std_logic;
signal int_full_dly1 : std_logic;
signal int_full_dly2 : std_logic;
signal int_empty : std_logic;
signal int_almost_empty : std_logic;
Signal int_almost_empty_dly1 : std_logic;
Signal int_empty_dly1 : std_logic;
Signal inc_rd_addr : std_logic;
Signal decr_rd_addr : std_logic;
Signal inc_wr_addr : std_logic;
Signal rd_backup : std_logic;
Signal dummy_empty : std_logic;
Signal dummy_almost_empty : std_logic;
Signal dummy_full : std_logic;
Signal dummy_almost_full : std_logic;
signal write_address : std_logic_vector(0 to ADDR_CNTR_WIDTH-1);
signal read_address : std_logic_vector(0 to ADDR_CNTR_WIDTH-1);
signal sig_zeros : std_logic_vector(0 to ADDR_CNTR_WIDTH-1);
signal inc_nocc : std_logic;
signal inc_nocc_by_2 : std_logic;
signal occ_load_value : std_logic_vector(0 to OCC_CNTR_WIDTH-1);
begin
--Misc I/O Assignments
Full <= int_full;
Almost_Full <= int_almost_full;
Empty <= int_empty; -- Align Empty flag with the DP occupancy
Almost_Empty <= int_almost_empty; -- Align Almost_Empty flag with the
-- DP occupancy
Occupancy <= sig_normal_occupancy;
Wr_Addr <= write_address;
Rd_Addr <= read_address;
WrAck <= inc_wr_addr; -- currently combinitorial
RdAck <= inc_rd_addr; -- currently combinitorial
DeadLock <= int_full and int_empty; -- both full and empty at the
-- same time
DP_core_rden <= not(int_empty)-- assert read enable when not empty
or Bus_rst; -- or during reset
DP_core_wren <= not(int_full) -- assert write enable when not full
or Bus_rst; -- or during reset
--------------------------------------------------------------------------
-- Instantiate the Occupancy Counter relative to normal operations
-- This counter establishes the empty and full flag states.
--------------------------------------------------------------------------
inc_nocc_by_2 <= decr_rd_addr and inc_wr_addr;
inc_nocc <= decr_rd_addr or inc_wr_addr;
occ_load_value <= (others => '0');
I_NORMAL_OCCUPANCY : entity opb_ipif_v2_00_h.pf_occ_counter_top
generic map(
C_COUNT_WIDTH => OCC_CNTR_WIDTH
)
port map(
Clk => Bus_clk,
Rst => Bus_rst,
Load_Enable => '0',
Load_value => occ_load_value,
Count_Down => inc_rd_addr,
Count_Up => inc_nocc,
By_2 => inc_nocc_by_2,
Count_Out => sig_normal_occupancy,
almost_full => int_almost_full,
full => int_full,
almost_empty => int_almost_empty,
empty => int_empty
);
--------------------------------------------------------------------------
-- Register and delay Full/Empty flags
--------------------------------------------------------------------------
REGISTER_FLAG_PROCESS : process (Bus_rst, Bus_Clk)
Begin
If (Bus_rst = '1') Then
int_full_dly1 <= '0';
int_full_dly2 <= '0';
int_almost_empty_dly1 <= '0';
int_empty_dly1 <= '1';
Elsif (Bus_Clk'event and Bus_Clk = '1') Then
int_full_dly1 <= int_full;
int_full_dly2 <= int_full_dly1;
int_almost_empty_dly1 <= int_almost_empty;
int_empty_dly1 <= int_empty;
Else
null;
End if;
End process; -- TRANSITION_STATE_PROCESS
-----------------------------------------------------------------------
-- Write Address Counter Logic
inc_wr_addr <= WrReq
and not(int_full)
and not(int_full_dly1)
and not(int_full_dly2)
and not(rd_backup and int_almost_full);
I_WRITE_ADDR_CNTR : entity opb_ipif_v2_00_h.pf_counter_top
Generic Map (
C_COUNT_WIDTH => ADDR_CNTR_WIDTH
)
Port Map (
Clk => Bus_Clk,
Rst => Bus_rst,
Load_Enable => '0',
Load_value => sig_zeros,
Count_Down => '0',
Count_Up => inc_wr_addr,
Count_Out => write_address
);
-- end of write counter logic
-------------------------------------------------------------------------
-----------------------------------------------------------------------
-- Read Address Counter Logic
--------------------------------------------------------------------
-- Detect end of burst read by IP and set backup condition
--------------------------------------------------------------------
DETECT_RDCNT_BACKUP : process (Burst_rd_xfer, RdReq, int_empty_dly1)
Begin
if (Burst_rd_xfer = '1'
and RdReq = '0'
and int_empty_dly1 = '0') then
rd_backup <= '1';
else
rd_backup <= '0';
end if;
End process; -- DETECT_RDCNT_BACKUP
inc_rd_addr <= RdReq
and not(int_empty)
and not(int_empty_dly1);
decr_rd_addr <= rd_backup;
sig_zeros <= (others => '0');
I_READ_ADDR_CNTR : entity opb_ipif_v2_00_h.pf_counter_top
Generic Map ( C_COUNT_WIDTH => ADDR_CNTR_WIDTH
)
Port Map (
Clk => Bus_Clk,
Rst => Bus_rst,
Load_Enable => '0',
Load_value => sig_zeros,
Count_Down => decr_rd_addr,
Count_Up => inc_rd_addr,
Count_Out => read_address
);
-- end read address counter logic
----------------------------------------------------------------
end generate OMIT_PACKET_FEATURES;
INCLUDE_VACANCY : if (C_INCLUDE_VACANCY = true) generate
Constant REGISTER_VACANCY : boolean := false;
Signal slv_max_vacancy : std_logic_vector(0 to OCC_CNTR_WIDTH-1);
Signal int_vacancy : std_logic_vector(0 to OCC_CNTR_WIDTH-1);
begin
Vacancy <= int_vacancy; -- set to zeroes for now.
slv_max_vacancy <= CONV_STD_LOGIC_VECTOR(MAX_OCCUPANCY, OCC_CNTR_WIDTH);
I_VAC_CALC : entity opb_ipif_v2_00_h.pf_adder
generic map(
C_REGISTERED_RESULT => REGISTER_VACANCY,
C_COUNT_WIDTH => OCC_CNTR_WIDTH
)
port map (
Clk => Bus_Clk,
Rst => Bus_rst,
--Carry_Out => ,
Ain => slv_max_vacancy,
Bin => sig_normal_occupancy,
Add_sub_n => '0', -- always subtract
result_out => int_vacancy
);
end generate; -- INCLUDE_VACANCY
OMIT_VACANCY : if (C_INCLUDE_VACANCY = false) generate
Signal int_vacancy : std_logic_vector(0 to OCC_CNTR_WIDTH-1);
begin
int_vacancy <= (others => '0');
Vacancy <= int_vacancy; -- set to zeroes for now.
end generate; -- INCLUDE_VACANCY
end implementation;
|
bsd-3-clause
|
masson2013/heterogeneous_hthreads
|
src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/opb_ipif_v2_00_h/hdl/vhdl/rdpfifo_dp_cntl.vhd
|
3
|
28824
|
-------------------------------------------------------------------------------
-- $Id: rdpfifo_dp_cntl.vhd,v 1.2 2004/11/23 01:04:03 jcanaris Exp $
-------------------------------------------------------------------------------
--rdpfifo_dp_cntl.vhd
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: rdpfifo_dp_cntl.vhd
--
-- Description: This VHDL design file is for the Mauna Loa Read Packet
-- FIFO Dual Port Control block and the status
-- calculations for the Occupancy, Vacancy, Full, and Empty.
--
-------------------------------------------------------------------------------
-- Structure: This is the hierarchical structure of the RPFIFO design.
--
--
-- rdpfifo_dp_cntl.vhd
-- |
-- |
-- |-- pf_counter_top.vhd
-- | |
-- | |-- pf_counter.vhd
-- | |
-- | |-- pf_counter_bit.vhd
-- |
-- |
-- |-- pf_occ_counter_top.vhd
-- | |
-- | |-- occ_counter.vhd
-- | |
-- | |-- pf_counter_bit.vhd
-- |
-- |-- pf_adder.vhd
-- |
-- |-- pf_adder_bit.vhd
--
--
--
-------------------------------------------------------------------------------
-- Author: Doug Thorpe
--
-- History:
-- DET August 15, 2001 -- Initial version adapted from pt design
--
-- DET Sept. 21, 2001 -- Size Optimized redesign and parameterization
-- LCW Nov 8, 2004 -- updated for NCSim
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
---------------------------------------------------------------------
-- Library definitions
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.std_logic_arith.all;
library ieee;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
library opb_ipif_v2_00_h;
use opb_ipif_v2_00_h.pf_counter_top;
use opb_ipif_v2_00_h.pf_occ_counter_top;
use opb_ipif_v2_00_h.pf_adder;
-------------------------------------------------------------------------------
entity rdpfifo_dp_cntl is
Generic (
C_DP_ADDRESS_WIDTH : Integer := 9;
-- number of bits needed for dual port addressing
-- of requested FIFO depth
C_INCLUDE_PACKET_MODE : Boolean := true;
-- Select for inclusion/ommision of packet mode
-- features
C_INCLUDE_VACANCY : Boolean := true
-- Enable for Vacancy calc feature
);
port (
-- Inputs
Bus_rst : In std_logic;
Bus_clk : In std_logic;
Rdreq : In std_logic;
Wrreq : In std_logic;
Burst_rd_xfer : In std_logic;
Mark : In std_logic;
Restore : In std_logic;
Release : In std_logic;
-- Outputs
WrAck : Out std_logic;
RdAck : Out std_logic;
Full : Out std_logic;
Empty : Out std_logic;
Almost_Full : Out std_logic;
Almost_Empty : Out std_logic;
DeadLock : Out std_logic;
Occupancy : Out std_logic_vector(0 to C_DP_ADDRESS_WIDTH);
Vacancy : Out std_logic_vector(0 to C_DP_ADDRESS_WIDTH);
DP_core_wren : Out std_logic;
Wr_Addr : Out std_logic_vector(0 to C_DP_ADDRESS_WIDTH-1);
DP_core_rden : Out std_logic;
Rd_Addr : Out std_logic_vector(0 to C_DP_ADDRESS_WIDTH-1)
);
end rdpfifo_dp_cntl ;
-------------------------------------------------------------------------------
architecture implementation of rdpfifo_dp_cntl is
-- Components
-- CONSTANTS
Constant OCC_CNTR_WIDTH : integer := C_DP_ADDRESS_WIDTH+1;
Constant ADDR_CNTR_WIDTH : integer := C_DP_ADDRESS_WIDTH;
Constant MAX_OCCUPANCY : integer := 2**ADDR_CNTR_WIDTH;
Constant LOGIC_LOW : std_logic := '0';
-- shared signals
signal sig_normal_occupancy : std_logic_vector(0 to OCC_CNTR_WIDTH-1);
-------------------------------------------------------------------------------
----------------- start architecture logic ------------------------------------
begin
------------------------------------------------------------------------------
-- Generate the Read PFIFO with packetizing features included
------------------------------------------------------------------------------
INCLUDE_PACKET_FEATURES : if (C_INCLUDE_PACKET_MODE = true) generate
--TYPES
type transition_state_type is (
reset1,
normal_op,
packet_op,
rest1,
mark1,
rls1,
pkt_update,
nml_update
);
--INTERNAL SIGNALS
signal int_full : std_logic;
signal int_full_dly1 : std_logic;
signal int_full_dly2 : std_logic;
signal int_almost_full : std_logic;
signal int_empty : std_logic;
signal int_almost_empty : std_logic;
Signal int_almost_empty_dly1 : std_logic;
Signal int_empty_dly1 : std_logic;
Signal trans_state : transition_state_type;
signal hold_ack : std_logic;
Signal inc_rd_addr : std_logic;
Signal decr_rd_addr : std_logic;
Signal inc_wr_addr : std_logic;
Signal inc_mark_addr : std_logic;
Signal rd_backup : std_logic;
Signal dummy_empty : std_logic;
Signal dummy_almost_empty : std_logic;
Signal dummy_full : std_logic;
Signal dummy_almost_full : std_logic;
signal ld_occ_norm_into_mark : std_logic;
signal ld_addr_mark_into_write : std_logic;
signal ld_addr_write_into_mark : std_logic;
signal ld_occ_mark_into_norm : std_logic;
signal enable_mark_addr_inc : std_logic;
signal enable_wr_addr_inc : std_logic;
signal enable_rd_addr_inc : std_logic;
signal enable_rd_addr_decr : std_logic;
signal sig_mark_occupancy : std_logic_vector(0 to OCC_CNTR_WIDTH-1);
signal write_address : std_logic_vector(0 to ADDR_CNTR_WIDTH-1);
signal mark_address : std_logic_vector(0 to ADDR_CNTR_WIDTH-1);
signal read_address : std_logic_vector(0 to ADDR_CNTR_WIDTH-1);
signal sig_zeros : std_logic_vector(0 to ADDR_CNTR_WIDTH-1);
signal inc_nocc : std_logic;
signal inc_mocc : std_logic;
signal inc_nocc_by_2 : std_logic;
signal inc_mocc_by_2 : std_logic;
begin
--Misc I/O Assignments
Full <= int_full;
Almost_Full <= int_almost_full;
Empty <= int_empty; -- Align Empty flag with the DP occupancy
Almost_Empty <= int_almost_empty; -- Align Almost_Empty flag with the
-- DP occupancy
Occupancy <= sig_mark_occupancy;
Wr_Addr <= write_address;
Rd_Addr <= read_address;
WrAck <= inc_wr_addr; -- currently combinitorial
RdAck <= inc_rd_addr; -- currently combinitorial
DeadLock <= int_full and int_empty; -- both full and empty at
-- the same time
DP_core_rden <= not(int_empty)-- assert read enable when not empty
or Bus_rst; -- or during reset
DP_core_wren <= not(int_full) -- assert write enable when not full
or Bus_rst; -- or during reset
-----------------------------------------------------------------------
-- Main Transition sequence state machine
-----------------------------------------------------------------------
TRANSITION_STATE_PROCESS : process (Bus_rst, Bus_Clk)
Begin
If (Bus_rst = '1') Then
trans_state <= reset1;
hold_ack <= '1';
ld_occ_norm_into_mark <= '0';
ld_addr_mark_into_write <= '0';
ld_addr_write_into_mark <= '0';
ld_occ_mark_into_norm <= '0';
enable_mark_addr_inc <= '0';
enable_wr_addr_inc <= '0';
enable_rd_addr_inc <= '0';
enable_rd_addr_decr <= '0';
Elsif (Bus_Clk'event and Bus_Clk = '1') Then
-- set default values
trans_state <= reset1;
hold_ack <= '1';
ld_occ_norm_into_mark <= '0';
ld_addr_mark_into_write <= '0';
ld_addr_write_into_mark <= '0';
ld_occ_mark_into_norm <= '0';
enable_mark_addr_inc <= '0';
enable_wr_addr_inc <= '0';
enable_rd_addr_inc <= '1';
enable_rd_addr_decr <= '1';
Case trans_state Is
When reset1 =>
trans_state <= normal_op;
hold_ack <= '1';
enable_rd_addr_inc <= '0';
enable_rd_addr_decr <= '0';
When normal_op => -- Ignore restore and release inputs
-- during normal op
enable_mark_addr_inc <= '1';
enable_wr_addr_inc <= '1';
enable_rd_addr_inc <= '1';
enable_rd_addr_decr <= '1';
If (Mark = '1') Then -- transition to packet op on a
-- Mark command
trans_state <= mark1;
hold_ack <= '1';
else
trans_state <= normal_op;
hold_ack <= '0';
End if;
When packet_op =>
enable_wr_addr_inc <= '1';
enable_rd_addr_inc <= '1';
enable_rd_addr_decr <= '1';
If (Restore = '1') Then
trans_state <= rest1;
hold_ack <= '1';
Elsif (Mark = '1') Then
trans_state <= mark1;
hold_ack <= '1';
Elsif (Release = '1') Then
trans_state <= rls1;
hold_ack <= '1';
else
trans_state <= packet_op;
hold_ack <= '0';
End if;
When rest1 =>
trans_state <= pkt_update;
hold_ack <= '1';
ld_addr_mark_into_write <= '1'; -- load the mark address into
-- the wr cntr
ld_occ_mark_into_norm <= '1'; -- load the marked occupancy
-- into the normal occupancy
-- cntr
When mark1 =>
trans_state <= pkt_update;
hold_ack <= '1';
ld_occ_norm_into_mark <= '1'; -- load the normal occupancy
-- into mark occupancy cntr
ld_addr_write_into_mark <= '1'; -- load the write address
-- into mark register
When rls1 =>
trans_state <= nml_update;
hold_ack <= '1';
ld_occ_norm_into_mark <= '1'; -- load the normal occupancy
-- into mark occupancy cntr
ld_addr_write_into_mark <= '1'; -- load the write address
-- into mark register
When nml_update =>
trans_state <= normal_op;
hold_ack <= '0';
When pkt_update =>
trans_state <= packet_op;
hold_ack <= '0';
When others =>
trans_state <= normal_op;
hold_ack <= '0';
End case;
Else
null;
End if;
End process; -- TRANSITION_STATE_PROCESS
--------------------------------------------------------------------------
-- Instantiate the Occupancy Counter relative to marking operations
-- This counter establishes the empty flag states
--------------------------------------------------------------------------
inc_mocc_by_2 <= decr_rd_addr and inc_mark_addr;
inc_mocc <= decr_rd_addr or inc_mark_addr;
I_MARK_OCCUPANCY : entity opb_ipif_v2_00_h.pf_occ_counter_top
generic map(
C_COUNT_WIDTH => OCC_CNTR_WIDTH
)
port map(
Clk => Bus_clk,
Rst => Bus_rst,
Load_Enable => ld_occ_norm_into_mark,
Load_value => sig_normal_occupancy,
Count_Down => inc_rd_addr,
Count_Up => inc_mocc,
By_2 => inc_mocc_by_2,
Count_Out => sig_mark_occupancy,
almost_full => dummy_almost_full,
full => dummy_full,
almost_empty => int_almost_empty,
empty => int_empty
);
--------------------------------------------------------------------------
-- Instantiate the Occupancy Counter relative to normal operations
-- This counter establishes the full flag states.
--------------------------------------------------------------------------
inc_nocc_by_2 <= decr_rd_addr and inc_wr_addr;
inc_nocc <= decr_rd_addr or inc_wr_addr;
I_NORMAL_OCCUPANCY : entity opb_ipif_v2_00_h.pf_occ_counter_top
generic map(
C_COUNT_WIDTH => OCC_CNTR_WIDTH
)
port map(
Clk => Bus_clk,
Rst => Bus_rst,
Load_Enable => ld_occ_mark_into_norm,
Load_value => sig_mark_occupancy,
Count_Down => inc_rd_addr,
Count_Up => inc_nocc,
By_2 => inc_nocc_by_2,
Count_Out => sig_normal_occupancy,
almost_full => int_almost_full,
full => int_full,
almost_empty => dummy_almost_empty,
empty => dummy_empty
);
--------------------------------------------------------------------------
-- Register and delay Full/Empty flags
--------------------------------------------------------------------------
REGISTER_FLAG_PROCESS : process (Bus_rst, Bus_Clk)
Begin
If (Bus_rst = '1') Then
int_full_dly1 <= '0';
int_full_dly2 <= '0';
int_almost_empty_dly1 <= '0';
int_empty_dly1 <= '1';
Elsif (Bus_Clk'event and Bus_Clk = '1') Then
int_full_dly1 <= int_full;
int_full_dly2 <= int_full_dly1;
int_almost_empty_dly1 <= int_almost_empty;
int_empty_dly1 <= int_empty;
Else
null;
End if;
End process; -- REGISTER_FLAG_PROCESS
--------------------------------------------------------------------------
-- Write Address Counter Logic
inc_wr_addr <= WrReq
and not(int_full)
and not(int_full_dly1)
and not(int_full_dly2)
and not(hold_ack)
and not(rd_backup and int_almost_full)
and enable_wr_addr_inc;
I_WRITE_ADDR_CNTR : entity opb_ipif_v2_00_h.pf_counter_top
Generic Map (
C_COUNT_WIDTH => ADDR_CNTR_WIDTH
)
Port Map (
Clk => Bus_Clk,
Rst => Bus_rst,
Load_Enable => ld_addr_mark_into_write,
Load_value => mark_address,
Count_Down => '0',
Count_Up => inc_wr_addr,
Count_Out => write_address
);
-- end of write counter logic
--------------------------------------------------------------------------
--------------------------------------------------------------------------
-- Read Address Counter Logic
-----------------------------------------------------------------------
-- Detect end of burst read by IP and set backup condition
-----------------------------------------------------------------------
DETECT_RDCNT_BACKUP : process (Burst_rd_xfer, RdReq, int_empty_dly1)
Begin
if (Burst_rd_xfer = '1'
and RdReq = '0'
and int_empty_dly1 = '0') then
rd_backup <= '1';
else
rd_backup <= '0';
end if;
End process; -- DETECT_RDCNT_BACKUP
inc_rd_addr <= RdReq
and not(int_empty)
and not(int_empty_dly1)
and enable_rd_addr_inc;
decr_rd_addr <= rd_backup
and enable_rd_addr_decr;
sig_zeros <= (others => '0');
I_READ_ADDR_CNTR : entity opb_ipif_v2_00_h.pf_counter_top
Generic Map ( C_COUNT_WIDTH => ADDR_CNTR_WIDTH
)
Port Map (
Clk => Bus_Clk,
Rst => Bus_rst,
Load_Enable => '0',
Load_value => sig_zeros,
Count_Down => decr_rd_addr,
Count_Up => inc_rd_addr,
Count_Out => read_address
);
-- end read address counter logic
--------------------------------------------------------------------------
--------------------------------------------------------------------------
-- Mark Register Control
inc_mark_addr <= inc_wr_addr
and enable_mark_addr_inc;
I_MARKREG_ADDR_CNTR : entity opb_ipif_v2_00_h.pf_counter_top
Generic Map ( C_COUNT_WIDTH => ADDR_CNTR_WIDTH
)
Port Map (
Clk => Bus_Clk,
Rst => Bus_rst,
Load_Enable => ld_addr_write_into_mark,
Load_value => write_address,
Count_Down => '0',
Count_Up => inc_mark_addr,
Count_Out => mark_address
);
-- end mark address counter logic
--------------------------------------------------------------------------
end generate INCLUDE_PACKET_FEATURES;
------------------------------------------------------------------------------
-- Generate the Read PFIFO with no packetizing features
------------------------------------------------------------------------------
OMIT_PACKET_FEATURES : if (C_INCLUDE_PACKET_MODE = false) generate
--Internal Signals
signal int_almost_full : std_logic;
signal int_full : std_logic;
signal int_full_dly1 : std_logic;
signal int_full_dly2 : std_logic;
signal int_empty : std_logic;
signal int_almost_empty : std_logic;
Signal int_almost_empty_dly1 : std_logic;
Signal int_empty_dly1 : std_logic;
Signal inc_rd_addr : std_logic;
Signal decr_rd_addr : std_logic;
Signal inc_wr_addr : std_logic;
Signal rd_backup : std_logic;
Signal dummy_empty : std_logic;
Signal dummy_almost_empty : std_logic;
Signal dummy_full : std_logic;
Signal dummy_almost_full : std_logic;
signal write_address : std_logic_vector(0 to ADDR_CNTR_WIDTH-1);
signal read_address : std_logic_vector(0 to ADDR_CNTR_WIDTH-1);
signal sig_zeros : std_logic_vector(0 to ADDR_CNTR_WIDTH-1);
signal inc_nocc : std_logic;
signal inc_nocc_by_2 : std_logic;
signal occ_load_value : std_logic_vector(0 to OCC_CNTR_WIDTH-1);
begin
--Misc I/O Assignments
Full <= int_full;
Almost_Full <= int_almost_full;
Empty <= int_empty; -- Align Empty flag with the DP occupancy
Almost_Empty <= int_almost_empty; -- Align Almost_Empty flag with the
-- DP occupancy
Occupancy <= sig_normal_occupancy;
Wr_Addr <= write_address;
Rd_Addr <= read_address;
WrAck <= inc_wr_addr; -- currently combinitorial
RdAck <= inc_rd_addr; -- currently combinitorial
DeadLock <= int_full and int_empty; -- both full and empty at the
-- same time
DP_core_rden <= not(int_empty)-- assert read enable when not empty
or Bus_rst; -- or during reset
DP_core_wren <= not(int_full) -- assert write enable when not full
or Bus_rst; -- or during reset
--------------------------------------------------------------------------
-- Instantiate the Occupancy Counter relative to normal operations
-- This counter establishes the empty and full flag states.
--------------------------------------------------------------------------
inc_nocc_by_2 <= decr_rd_addr and inc_wr_addr;
inc_nocc <= decr_rd_addr or inc_wr_addr;
occ_load_value <= (others => '0');
I_NORMAL_OCCUPANCY : entity opb_ipif_v2_00_h.pf_occ_counter_top
generic map(
C_COUNT_WIDTH => OCC_CNTR_WIDTH
)
port map(
Clk => Bus_clk,
Rst => Bus_rst,
Load_Enable => '0',
Load_value => occ_load_value,
Count_Down => inc_rd_addr,
Count_Up => inc_nocc,
By_2 => inc_nocc_by_2,
Count_Out => sig_normal_occupancy,
almost_full => int_almost_full,
full => int_full,
almost_empty => int_almost_empty,
empty => int_empty
);
--------------------------------------------------------------------------
-- Register and delay Full/Empty flags
--------------------------------------------------------------------------
REGISTER_FLAG_PROCESS : process (Bus_rst, Bus_Clk)
Begin
If (Bus_rst = '1') Then
int_full_dly1 <= '0';
int_full_dly2 <= '0';
int_almost_empty_dly1 <= '0';
int_empty_dly1 <= '1';
Elsif (Bus_Clk'event and Bus_Clk = '1') Then
int_full_dly1 <= int_full;
int_full_dly2 <= int_full_dly1;
int_almost_empty_dly1 <= int_almost_empty;
int_empty_dly1 <= int_empty;
Else
null;
End if;
End process; -- TRANSITION_STATE_PROCESS
-----------------------------------------------------------------------
-- Write Address Counter Logic
inc_wr_addr <= WrReq
and not(int_full)
and not(int_full_dly1)
and not(int_full_dly2)
and not(rd_backup and int_almost_full);
I_WRITE_ADDR_CNTR : entity opb_ipif_v2_00_h.pf_counter_top
Generic Map (
C_COUNT_WIDTH => ADDR_CNTR_WIDTH
)
Port Map (
Clk => Bus_Clk,
Rst => Bus_rst,
Load_Enable => '0',
Load_value => sig_zeros,
Count_Down => '0',
Count_Up => inc_wr_addr,
Count_Out => write_address
);
-- end of write counter logic
-------------------------------------------------------------------------
-----------------------------------------------------------------------
-- Read Address Counter Logic
--------------------------------------------------------------------
-- Detect end of burst read by IP and set backup condition
--------------------------------------------------------------------
DETECT_RDCNT_BACKUP : process (Burst_rd_xfer, RdReq, int_empty_dly1)
Begin
if (Burst_rd_xfer = '1'
and RdReq = '0'
and int_empty_dly1 = '0') then
rd_backup <= '1';
else
rd_backup <= '0';
end if;
End process; -- DETECT_RDCNT_BACKUP
inc_rd_addr <= RdReq
and not(int_empty)
and not(int_empty_dly1);
decr_rd_addr <= rd_backup;
sig_zeros <= (others => '0');
I_READ_ADDR_CNTR : entity opb_ipif_v2_00_h.pf_counter_top
Generic Map ( C_COUNT_WIDTH => ADDR_CNTR_WIDTH
)
Port Map (
Clk => Bus_Clk,
Rst => Bus_rst,
Load_Enable => '0',
Load_value => sig_zeros,
Count_Down => decr_rd_addr,
Count_Up => inc_rd_addr,
Count_Out => read_address
);
-- end read address counter logic
----------------------------------------------------------------
end generate OMIT_PACKET_FEATURES;
INCLUDE_VACANCY : if (C_INCLUDE_VACANCY = true) generate
Constant REGISTER_VACANCY : boolean := false;
Signal slv_max_vacancy : std_logic_vector(0 to OCC_CNTR_WIDTH-1);
Signal int_vacancy : std_logic_vector(0 to OCC_CNTR_WIDTH-1);
begin
Vacancy <= int_vacancy; -- set to zeroes for now.
slv_max_vacancy <= CONV_STD_LOGIC_VECTOR(MAX_OCCUPANCY, OCC_CNTR_WIDTH);
I_VAC_CALC : entity opb_ipif_v2_00_h.pf_adder
generic map(
C_REGISTERED_RESULT => REGISTER_VACANCY,
C_COUNT_WIDTH => OCC_CNTR_WIDTH
)
port map (
Clk => Bus_Clk,
Rst => Bus_rst,
--Carry_Out => ,
Ain => slv_max_vacancy,
Bin => sig_normal_occupancy,
Add_sub_n => '0', -- always subtract
result_out => int_vacancy
);
end generate; -- INCLUDE_VACANCY
OMIT_VACANCY : if (C_INCLUDE_VACANCY = false) generate
Signal int_vacancy : std_logic_vector(0 to OCC_CNTR_WIDTH-1);
begin
int_vacancy <= (others => '0');
Vacancy <= int_vacancy; -- set to zeroes for now.
end generate; -- INCLUDE_VACANCY
end implementation;
|
bsd-3-clause
|
masson2013/heterogeneous_hthreads
|
src/platforms/xilinx/ml605_pr_smp1_14_7/design/pcores/plb_sync_manager_v1_00_a/hdl/vhdl/trylock_fsm.vhd
|
11
|
6378
|
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use work.common.all;
entity trylock_fsm is
generic
(
C_AWIDTH : integer := 32;
C_DWIDTH : integer := 32;
C_TWIDTH : integer := 8;
C_MWIDTH : integer := 6;
C_CWIDTH : integer := 8
);
port
(
clk : in std_logic;
rst : in std_logic;
start : in std_logic;
finish : out std_logic;
data : out std_logic_vector(0 to C_DWIDTH-1);
mutex : in std_logic_vector(0 to C_MWIDTH-1);
thread : in std_logic_vector(0 to C_TWIDTH-1);
miowner : in std_logic_vector(0 to C_TWIDTH-1);
milast : in std_logic_vector(0 to C_TWIDTH-1);
minext : in std_logic_vector(0 to C_TWIDTH-1);
micount : in std_logic_vector(0 to C_CWIDTH-1);
mikind : in std_logic_vector(0 to 1);
tinext : in std_logic_vector(0 to C_TWIDTH-1);
moaddr : out std_logic_vector(0 to C_MWIDTH-1);
moena : out std_logic;
mowea : out std_logic;
moowner : out std_logic_vector(0 to C_TWIDTH-1);
monext : out std_logic_vector(0 to C_TWIDTH-1);
molast : out std_logic_vector(0 to C_TWIDTH-1);
mocount : out std_logic_vector(0 to C_CWIDTH-1);
mokind : out std_logic_vector(0 to 1);
sysrst : in std_logic;
rstdone : out std_logic;
toaddr : out std_logic_vector(0 to C_TWIDTH-1);
toena : out std_logic;
towea : out std_logic;
tonext : out std_logic_vector(0 to C_TWIDTH-1)
);
end trylock_fsm;
architecture behavioral of trylock_fsm is
-- A type for the states in the try fsm
type try_state is
(
IDLE,
READ,
DONE
);
-- Declare signals for the try fsm
signal try_cs : try_state;
signal try_ns : try_state;
begin
-- This core resets in one clock cycle so it is always "done"
rstdone <= '1';
try_update : process (clk,rst,sysrst,try_ns) is
begin
if( rising_edge(clk) ) then
if( rst = '1' or sysrst = '1' ) then
try_cs <= IDLE;
else
try_cs <= try_ns;
end if;
end if;
end process try_update;
try_controller : process (try_cs,start,mutex,micount,mikind,miowner,milast,minext,thread) is
begin
try_ns <= try_cs;
finish <= '0';
data <= (others => '0');
moaddr <= (others => '0');
moena <= '0';
mowea <= '0';
moowner <= (others => '0');
monext <= (others => '0');
molast <= (others => '0');
mokind <= (others => '0');
mocount <= (others => '0');
toaddr <= (others => '0');
toena <= '0';
towea <= '0';
tonext <= (others => '0');
case try_cs is
when IDLE =>
if( start = '1' ) then
moaddr <= mutex;
moena <= '1';
mowea <= '0';
try_ns <= READ;
end if;
when READ =>
try_ns <= DONE;
when DONE =>
if( micount = zero(C_CWIDTH) ) then
moaddr <= mutex;
moena <= '1';
mowea <= '1';
moowner <= thread;
monext <= thread;
molast <= thread;
mocount <= one( C_CWIDTH );
mokind <= mikind;
elsif( mikind = SYNCH_RECURS and miowner = thread ) then
moaddr <= mutex;
moena <= '1';
mowea <= '1';
moowner <= miowner;
monext <= minext;
molast <= milast;
mocount <= micount + 1;
mokind <= mikind;
else
data(1) <= '1';
end if;
finish <= '1';
try_ns <= IDLE;
end case;
end process try_controller;
end behavioral;
|
bsd-3-clause
|
masson2013/heterogeneous_hthreads
|
src/hardware/MyRepository/pcores/plb_sync_manager_v1_00_a/devl/bfmsim/pcores/plb_sync_manager_tb_v1_00_a/simhdl/vhdl/plb_sync_manager_tb.vhd
|
3
|
21234
|
------------------------------------------------------------------------------
--
-- This vhdl module is a template for creating IP testbenches using the IBM
-- BFM toolkits. It provides a fixed interface to the subsystem testbench.
--
-- DO NOT CHANGE THE entity name, architecture name, generic parameter
-- declaration or port declaration of this file. You may add components,
-- instances, constants, signals, etc. as you wish.
--
-- See IBM Bus Functional Model Toolkit User's Manual for more information
-- on the BFMs.
--
------------------------------------------------------------------------------
-- plb_sync_manager_tb.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: plb_sync_manager_tb.vhd
-- Version: 1.00.a
-- Description: IP testbench
-- Date: Thu May 7 14:29:08 2009 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library plb_sync_manager_v1_00_a;
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
entity plb_sync_manager_tb is
------------------------------------------
-- DO NOT CHANGE THIS GENERIC DECLARATION
------------------------------------------
generic
(
-- Bus protocol parameters, do not add to or delete
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_SPLB_AWIDTH : integer := 32;
C_SPLB_DWIDTH : integer := 128;
C_SPLB_NUM_MASTERS : integer := 8;
C_SPLB_MID_WIDTH : integer := 3;
C_SPLB_NATIVE_DWIDTH : integer := 32;
C_SPLB_P2P : integer := 0;
C_SPLB_SUPPORT_BURSTS : integer := 0;
C_SPLB_SMALLEST_MASTER : integer := 32;
C_SPLB_CLK_PERIOD_PS : integer := 10000;
C_INCLUDE_DPHASE_TIMER : integer := 0;
C_FAMILY : string := "virtex5";
C_MPLB_AWIDTH : integer := 32;
C_MPLB_DWIDTH : integer := 128;
C_MPLB_NATIVE_DWIDTH : integer := 32;
C_MPLB_P2P : integer := 0;
C_MPLB_SMALLEST_SLAVE : integer := 32;
C_MPLB_CLK_PERIOD_PS : integer := 10000
);
------------------------------------------
-- DO NOT CHANGE THIS PORT DECLARATION
------------------------------------------
port
(
-- PLB (v4.6) bus interface, do not add or delete
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to C_SPLB_MID_WIDTH-1);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to C_SPLB_DWIDTH/8-1);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to C_SPLB_DWIDTH-1);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to C_SPLB_DWIDTH-1);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MWrErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MRdErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MIRQ : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
MPLB_Clk : in std_logic;
MPLB_Rst : in std_logic;
MD_error : out std_logic;
M_request : out std_logic;
M_priority : out std_logic_vector(0 to 1);
M_busLock : out std_logic;
M_RNW : out std_logic;
M_BE : out std_logic_vector(0 to C_MPLB_DWIDTH/8-1);
M_MSize : out std_logic_vector(0 to 1);
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_TAttribute : out std_logic_vector(0 to 15);
M_lockErr : out std_logic;
M_abort : out std_logic;
M_UABus : out std_logic_vector(0 to 31);
M_ABus : out std_logic_vector(0 to 31);
M_wrDBus : out std_logic_vector(0 to C_MPLB_DWIDTH-1);
M_wrBurst : out std_logic;
M_rdBurst : out std_logic;
PLB_MAddrAck : in std_logic;
PLB_MSSize : in std_logic_vector(0 to 1);
PLB_MRearbitrate : in std_logic;
PLB_MTimeout : in std_logic;
PLB_MBusy : in std_logic;
PLB_MRdErr : in std_logic;
PLB_MWrErr : in std_logic;
PLB_MIRQ : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to (C_MPLB_DWIDTH-1));
PLB_MRdWdAddr : in std_logic_vector(0 to 3);
PLB_MRdDAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MWrBTerm : in std_logic;
-- BFM synchronization bus interface
SYNCH_IN : in std_logic_vector(0 to 31) := (others => '0');
SYNCH_OUT : out std_logic_vector(0 to 31) := (others => '0')
);
end entity plb_sync_manager_tb;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture testbench of plb_sync_manager_tb is
--USER testbench signal declarations added here as you wish
------------------------------------------
-- Signal to hook up master detected error and synch bus
------------------------------------------
signal sig_dev_mderr : std_logic;
------------------------------------------
-- Standard constants for bfl/vhdl communication
------------------------------------------
constant NOP : integer := 0;
constant START : integer := 1;
constant STOP : integer := 2;
constant WAIT_IN : integer := 3;
constant WAIT_OUT : integer := 4;
constant ASSERT_IN : integer := 5;
constant ASSERT_OUT : integer := 6;
constant ASSIGN_IN : integer := 7;
constant ASSIGN_OUT : integer := 8;
constant RESET_WDT : integer := 9;
constant MST_ERROR : integer := 30;
constant INTERRUPT : integer := 31;
begin
------------------------------------------
-- Instance of IP under test.
-- Communication with the BFL is by using SYNCH_IN/SYNCH_OUT signals.
------------------------------------------
UUT : entity plb_sync_manager_v1_00_a.plb_sync_manager
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
--USER generics mapped here
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_BASEADDR => C_BASEADDR,
C_HIGHADDR => C_HIGHADDR,
C_SPLB_AWIDTH => C_SPLB_AWIDTH,
C_SPLB_DWIDTH => C_SPLB_DWIDTH,
C_SPLB_NUM_MASTERS => C_SPLB_NUM_MASTERS,
C_SPLB_MID_WIDTH => C_SPLB_MID_WIDTH,
C_SPLB_NATIVE_DWIDTH => C_SPLB_NATIVE_DWIDTH,
C_SPLB_P2P => C_SPLB_P2P,
C_SPLB_SUPPORT_BURSTS => C_SPLB_SUPPORT_BURSTS,
C_SPLB_SMALLEST_MASTER => C_SPLB_SMALLEST_MASTER,
C_SPLB_CLK_PERIOD_PS => C_SPLB_CLK_PERIOD_PS,
C_INCLUDE_DPHASE_TIMER => C_INCLUDE_DPHASE_TIMER,
C_FAMILY => C_FAMILY,
C_MPLB_AWIDTH => C_MPLB_AWIDTH,
C_MPLB_DWIDTH => C_MPLB_DWIDTH,
C_MPLB_NATIVE_DWIDTH => C_MPLB_NATIVE_DWIDTH,
C_MPLB_P2P => C_MPLB_P2P,
C_MPLB_SMALLEST_SLAVE => C_MPLB_SMALLEST_SLAVE,
C_MPLB_CLK_PERIOD_PS => C_MPLB_CLK_PERIOD_PS
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
--USER ports mapped here
-- MAP USER PORTS ABOVE THIS LINE ------------------
SPLB_Clk => SPLB_Clk,
SPLB_Rst => SPLB_Rst,
PLB_ABus => PLB_ABus,
PLB_UABus => PLB_UABus,
PLB_PAValid => PLB_PAValid,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_masterID => PLB_masterID,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_MSize => PLB_MSize,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_lockErr => PLB_lockErr,
PLB_wrDBus => PLB_wrDBus,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendPri => PLB_rdPendPri,
PLB_reqPri => PLB_reqPri,
PLB_TAttribute => PLB_TAttribute,
Sl_addrAck => Sl_addrAck,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MBusy => Sl_MBusy,
Sl_MWrErr => Sl_MWrErr,
Sl_MRdErr => Sl_MRdErr,
Sl_MIRQ => Sl_MIRQ,
MPLB_Clk => MPLB_Clk,
MPLB_Rst => MPLB_Rst,
MD_error => sig_dev_mderr,
M_request => M_request,
M_priority => M_priority,
M_busLock => M_busLock,
M_RNW => M_RNW,
M_BE => M_BE,
M_MSize => M_MSize,
M_size => M_size,
M_type => M_type,
M_TAttribute => M_TAttribute,
M_lockErr => M_lockErr,
M_abort => M_abort,
M_UABus => M_UABus,
M_ABus => M_ABus,
M_wrDBus => M_wrDBus,
M_wrBurst => M_wrBurst,
M_rdBurst => M_rdBurst,
PLB_MAddrAck => PLB_MAddrAck,
PLB_MSSize => PLB_MSSize,
PLB_MRearbitrate => PLB_MRearbitrate,
PLB_MTimeout => PLB_MTimeout,
PLB_MBusy => PLB_MBusy,
PLB_MRdErr => PLB_MRdErr,
PLB_MWrErr => PLB_MWrErr,
PLB_MIRQ => PLB_MIRQ,
PLB_MRdDBus => PLB_MRdDBus,
PLB_MRdWdAddr => PLB_MRdWdAddr,
PLB_MRdDAck => PLB_MRdDAck,
PLB_MRdBTerm => PLB_MRdBTerm,
PLB_MWrDAck => PLB_MWrDAck,
PLB_MWrBTerm => PLB_MWrBTerm
);
------------------------------------------
-- Hook up UUT MD_error to synch_out bit for Master Detected Error status monitor
------------------------------------------
SYNCH_OUT(MST_ERROR) <= sig_dev_mderr;
------------------------------------------
-- Zero out the unused synch_out bits
------------------------------------------
SYNCH_OUT(10 to 31) <= (others => '0');
------------------------------------------
-- Test bench code itself
--
-- The test bench itself can be arbitrarily complex and may include
-- hierarchy as the designer sees fit
------------------------------------------
TEST_PROCESS : process
begin
SYNCH_OUT(NOP) <= '0';
SYNCH_OUT(START) <= '0';
SYNCH_OUT(STOP) <= '0';
SYNCH_OUT(WAIT_IN) <= '0';
SYNCH_OUT(WAIT_OUT) <= '0';
SYNCH_OUT(ASSERT_IN) <= '0';
SYNCH_OUT(ASSERT_OUT) <= '0';
SYNCH_OUT(ASSIGN_IN) <= '0';
SYNCH_OUT(ASSIGN_OUT) <= '0';
SYNCH_OUT(RESET_WDT) <= '0';
-- initializations
-- wait for reset to stabalize after power-up
wait for 200 ns;
-- wait for end of reset
wait until (SPLB_Rst'EVENT and SPLB_Rst = '0');
assert FALSE report "*** Real simulation starts here ***" severity NOTE;
-- wait for reset to be completed
wait for 200 ns;
------------------------------------------
-- Test User Logic Slave Register
------------------------------------------
-- send out start signal to begin testing ...
wait until (SPLB_Clk'EVENT and SPLB_Clk = '1');
SYNCH_OUT(START) <= '1';
assert FALSE report "*** Start User Logic Slave Register Test ***" severity NOTE;
wait until (SPLB_Clk'EVENT and SPLB_Clk = '1');
SYNCH_OUT(START) <= '0';
-- wait stop signal for end of testing ...
wait until (SYNCH_IN(STOP)'EVENT and SYNCH_IN(STOP) = '1');
assert FALSE report "*** User Logic Slave Register Test Complete ***" severity NOTE;
wait for 1 us;
------------------------------------------
-- Test User Logic IP Master
------------------------------------------
-- send out start signal to begin testing ...
wait until (SPLB_Clk'EVENT and SPLB_Clk = '1');
SYNCH_OUT(START) <= '1';
assert FALSE report "*** Start User Logic IP Master Read Test ***" severity NOTE;
wait until (SPLB_Clk'EVENT and SPLB_Clk = '1');
SYNCH_OUT(START) <= '0';
-- wait for awhile for wait_out signal to let user logic master complete master read ...
wait until (SYNCH_IN(WAIT_OUT)'EVENT and SYNCH_IN(WAIT_OUT) = '1');
assert FALSE report "*** User Logic is doing master read transaction now ***" severity NOTE;
wait for 1 us;
-- send out wait_in signal to continue testing ...
wait until (SPLB_Clk'EVENT and SPLB_Clk = '1');
SYNCH_OUT(WAIT_IN) <= '1';
assert FALSE report "*** Continue User Logic IP Master Write Test ***" severity NOTE;
wait until (SPLB_Clk'EVENT and SPLB_Clk = '1');
SYNCH_OUT(WAIT_IN) <= '0';
-- wait for awhile for wait_out signal to let user logic master complete master write ...
wait until (SYNCH_IN(WAIT_OUT)'EVENT and SYNCH_IN(WAIT_OUT) = '1');
assert FALSE report "*** User Logic is doing master write transaction now ***" severity NOTE;
wait for 1 us;
-- send out wait_in signal to continue testing ...
wait until (SPLB_Clk'EVENT and SPLB_Clk = '1');
SYNCH_OUT(WAIT_IN) <= '1';
assert FALSE report "*** Continue the rest of User Logic IP Master Test ***" severity NOTE;
wait until (SPLB_Clk'EVENT and SPLB_Clk = '1');
SYNCH_OUT(WAIT_IN) <= '0';
-- wait stop signal for end of testing ...
wait until (SYNCH_IN(STOP)'EVENT and SYNCH_IN(STOP) = '1');
assert FALSE report "*** User Logic IP Master Test Complete ***" severity NOTE;
wait for 1 us;
------------------------------------------
-- Test User I/Os and other features
------------------------------------------
--USER code added here to stimulate any user I/Os
wait;
end process TEST_PROCESS;
end architecture testbench;
|
bsd-3-clause
|
masson2013/heterogeneous_hthreads
|
src/hardware/MyRepository/pcores/plb_fsmlang_special_pic_v1_00_a/hdl/vhdl/complete_pic_test.vhd
|
2
|
6970
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:58:07 09/10/2009
-- Design Name:
-- Module Name: /home/abaez/ise_projects/complete_pic/src//complete_pic_test.vhd
-- Project Name: ise_proj
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: complete_pic
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY complete_pic_test IS
generic (
C_NUM_INTERRUPTS : integer := 8;
C_REG_SIZE : integer := 9;
C_CMD_WIDTH : integer := 4;
)
END complete_pic_test;
ARCHITECTURE behavior OF complete_pic_test IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT complete_pic
PORT(
msg_chan_channelDataIn : OUT std_logic_vector(0 to 7);
msg_chan_channelDataOut : IN std_logic_vector(0 to 7);
msg_chan_exists : IN std_logic;
msg_chan_full : IN std_logic;
msg_chan_channelRead : OUT std_logic;
msg_chan_channelWrite : OUT std_logic;
go : IN std_logic;
ack : OUT std_logic;
TID_IN : IN std_logic_vector(0 to 7);
IID_IN : IN std_logic_vector(0 to log2(C_NUM_INTERRUPTS)-1);
CMD_IN : IN std_logic_vector(0 to C_CMD_WIDTH-1);
RET_OUT : OUT std_logic_vector(0 to 7);
TID_OUT : OUT std_logic_vector(0 to 7);
interrupts_in : IN std_logic_vector(0 to C_NUM_INTERRUPTS-1);
clock_sig : IN std_logic;
reset_sig : IN std_logic
);
END COMPONENT;
--Inputs
signal msg_chan_channelDataOut : std_logic_vector(0 to 7) := (others => '0');
signal msg_chan_exists : std_logic := '0';
signal msg_chan_full : std_logic := '0';
signal go : std_logic := '0';
signal TID_IN : std_logic_vector(0 to 7) := (others => '0');
signal IID_IN : std_logic_vector(0 to log2(C_NUM_INTERRUPTS)-1) := (others => '0');
signal CMD_IN : std_logic_vector(0 to C_CMD_WIDTH-1) := (others => '0');
signal interrupts_in : std_logic_vector(0 to C_CMD_WIDTH-1) := (others => '0');
signal clock_sig : std_logic := '0';
signal reset_sig : std_logic := '0';
--Outputs
signal msg_chan_channelDataIn : std_logic_vector(0 to 7);
signal msg_chan_channelRead : std_logic;
signal msg_chan_channelWrite : std_logic;
signal ack : std_logic;
signal RET_OUT : std_logic_vector(0 to 7);
signal TID_OUT : std_logic_vector(0 to 7);
-- Clock period definitions
constant clock_sig_period : time := 1 us;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: complete_pic PORT MAP (
msg_chan_channelDataIn => msg_chan_channelDataIn,
msg_chan_channelDataOut => msg_chan_channelDataOut,
msg_chan_exists => msg_chan_exists,
msg_chan_full => msg_chan_full,
msg_chan_channelRead => msg_chan_channelRead,
msg_chan_channelWrite => msg_chan_channelWrite,
go => go,
ack => ack,
TID_IN => TID_IN,
IID_IN => IID_IN,
CMD_IN => CMD_IN,
RET_OUT => RET_OUT,
TID_OUT => TID_OUT,
interrupts_in => interrupts_in,
clock_sig => clock_sig,
reset_sig => reset_sig
);
-- Clock process definitions
clock_sig_process :process
begin
clock_sig <= '0';
wait for clock_sig_period/2;
clock_sig <= '1';
wait for clock_sig_period/2;
end process;
-- Calculate the log base 2 of some natural number. This function can be
-- used to determine the minimum number of bits needed to represent the
-- given natural number.
function log2( n : in natural ) return positive is
begin
if n <= 2 then
return 1;
else
return 1 + log2(n/2);
end if;
end function log2;
-- Stimulus process
stim_proc: process
procedure assoc(tid : in std_logic_vector(0 to 7); iid : in std_logic_vector(0 to log2(C_NUM_INTERRUPTS)-1)) is
begin
wait until clock_sig = '0';
TID_IN <= tid;
IID_IN <= iid;
CMD_IN <= "0001";
go <= '1';
wait until ack = '1';
wait for 2*clock_sig_period;
TID_IN <= tid;
IID_IN <= iid;
CMD_IN <= "0001";
go <= '0';
wait until ack = '0';
end procedure assoc;
procedure read_entry(tid : in std_logic_vector(0 to 7); iid : in std_logic_vector(0 to log2(C_NUM_INTERRUPTS)-1)) is
begin
wait until clock_sig = '0';
TID_IN <= tid;
IID_IN <= iid;
CMD_IN <= "0000";
go <= '1';
wait until ack = '1';
wait for 2*clock_sig_period;
TID_IN <= tid;
IID_IN <= iid;
CMD_IN <= "0000";
go <= '0';
wait until ack = '0';
end procedure read_entry;
procedure clear_entry(tid : in std_logic_vector(0 to 7); iid : in std_logic_vector(0 to log2(C_NUM_INTERRUPTS)-1)) is
begin
wait until clock_sig = '0';
TID_IN <= tid;
IID_IN <= iid;
CMD_IN <= "0010";
go <= '1';
wait until ack = '1';
wait for 2*clock_sig_period;
TID_IN <= tid;
IID_IN <= iid;
CMD_IN <= "0010";
go <= '0';
wait until ack = '0';
end procedure clear_entry;
procedure generate_interrupt(intr : in std_logic_vector(0 to C_NUM_INTERRUPTS-1)) is
begin
wait until clock_sig = '0';
interrupts_in <= intr;
wait until clock_sig = '1';
wait for 5*clock_sig_period;
end procedure generate_interrupt;
begin
-- hold reset state for 100ms.
wait for 50 ns;
reset_sig <= '1';
wait for clock_sig_period;
reset_sig <= '0';
wait for 5*clock_sig_period;
-- insert stimulus here
go <= '0';
-- start. Write into memory #2 and #3 values 15 and 8.
assoc("00001111","010");
assoc("00001000","011");
-- Change the command to interrupt read an empty register
generate_interrupt("0100");
read_entry("00001010","010");
-- write another TID to memory #0
assoc("10110000","000");
-- specify another write to already chosen memory #0 - failure condition
assoc("00100000","000");
-- Set go to LOW and try to write.
wait for 4*clock_sig_period;
go <= '0';
TID_IN <= "11001100";
IID_IN <= "10";
-- Generate an interrupt for registers #0,#1 and #3
generate_interrupt("1101");
-- read memory address 3
read_entry("00110011","011");
-- Generate last interrupt
wait for 5*clock_sig_period;
generate_interrupt("1111");
wait;
end process;
END;
|
bsd-3-clause
|
masson2013/heterogeneous_hthreads
|
src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/ipif_common_v1_00_c/hdl/vhdl/ctrl_reg.vhd
|
2
|
4906
|
-------------------------------------------------------------------------------
-- $Id: ctrl_reg.vhd,v 1.1 2003/02/18 19:16:00 ostlerf Exp $
-------------------------------------------------------------------------------
-- A generic control register for use with the dma_sg block.
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: ctrl_reg.vhd
--
-- Description: Control register with parameterizable width and two
-- write enables.
--
-------------------------------------------------------------------------------
-- Structure:
-- ctrl_reg.vhds
--
-------------------------------------------------------------------------------
-- Author: Farrell Ostler
-- History:
-- FLO 12/19/01 -- Header added
--
-- -- Two point solution registers are declared
-- -- for this version as XST E.33 does not handle
-- -- the parameterized width.
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity ctrl_reg is
generic(
C_RESET_VAL: std_logic_vector
);
port(
clk : in std_logic;
rst : in std_logic;
chan_sel : in std_logic;
reg_sel : in std_logic;
wr_ce : in std_logic;
d : in std_logic_vector;
q : out std_logic_vector
);
end ctrl_reg;
architecture sim of ctrl_reg is
begin
CTRL_REG_PROCESS: process (clk)
begin
if clk'event and clk='1' then
if (rst = '1') then
q <= C_RESET_VAL;
elsif (chan_sel and reg_sel and wr_ce) = '1' then
q <= d;
end if;
end if;
end process;
end;
library ieee;
use ieee.std_logic_1164.all;
entity ctrl_reg_0_to_6 is
generic(
C_RESET_VAL: std_logic_vector
);
port(
clk : in std_logic;
rst : in std_logic;
chan_sel : in std_logic;
reg_sel : in std_logic;
wr_ce : in std_logic;
d : in std_logic_vector(0 to 6);
q : out std_logic_vector(0 to 6)
);
end ctrl_reg_0_to_6;
architecture sim of ctrl_reg_0_to_6 is
begin
CTRL_REG_PROCESS: process (clk)
begin
if clk'event and clk='1' then
if (rst = '1') then
q <= C_RESET_VAL;
elsif (chan_sel and reg_sel and wr_ce) = '1' then
q <= d;
end if;
end if;
end process;
end;
library ieee;
use ieee.std_logic_1164.all;
entity ctrl_reg_0_to_0 is
generic(
C_RESET_VAL: std_logic_vector
);
port(
clk : in std_logic;
rst : in std_logic;
chan_sel : in std_logic;
reg_sel : in std_logic;
wr_ce : in std_logic;
-- XGR_E33 d : in std_logic_vector(0 to 0);
-- XGR_E33 q : out std_logic_vector(0 to 0)
d : in std_logic;
q : out std_logic
);
end ctrl_reg_0_to_0;
architecture sim of ctrl_reg_0_to_0 is
begin
CTRL_REG_PROCESS: process (clk)
begin
if clk'event and clk='1' then
if (rst = '1') then
-- XGR_E33 q <= C_RESET_VAL;
q <= C_RESET_VAL(0);
elsif (chan_sel and reg_sel and wr_ce) = '1' then
q <= d;
end if;
end if;
end process;
end;
|
bsd-3-clause
|
masson2013/heterogeneous_hthreads
|
src/platforms/xilinx/smp3_opbhwti/design/pcores/opb_ipif_v2_00_h/hdl/vhdl/bus2ip_amux.vhd
|
3
|
8587
|
-------------------------------------------------------------------------------
-- $Id: bus2ip_amux.vhd,v 1.1 2003/03/15 01:05:24 ostlerf Exp $
-------------------------------------------------------------------------------
-- bus2ip_amux.vhd - vhdl design file for the entity and architecture
-- of the Mauna Loa IPIF Bus to IPIF Bus Address
-- multiplexer.
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: bus2ip_amux.vhd
--
-- Description: This vhdl design file is for the entity and architecture
-- of the Mauna Loa IPIF Bus to IPIF Bus Address Bus Output
-- multiplexer.
--
-------------------------------------------------------------------------------
-- Structure:
--
--
-- bus2ip_amux.vhd
--
-------------------------------------------------------------------------------
-- Author: D. Thorpe
-- History:
--
-- DET May-9-01
-- ~~~~~~
-- First version
-- ^^^^^^
--
-- DET May-22-01
-- ~~~~~~
-- Changed architecture to reflect addr counter
-- and non-registered address outputs.
-- ^^^^^^
--
-- FO Oct-15-01
-- ~~~~~~
-- Added byte-enable channel.
-- Subsumed ipif_interrupt.vhd into this file; there is no
-- longer a wrapper.
-- ^^^^^^
--
-- FO Dec-11-01
-- ~~~~~~
-- The automatic sequential address now increments by the word size
-- in bytes instead of by one byte.
-- ^^^^^^
--
-- FO Jan-02-02
-- ~~~~~~
-- Misc cleanup and signal rename actions.
-- ^^^^^^
--
-- FO Nov-01-02
-- ~~~~~~
-- Added an XST workaround (keep attribute on signal reg_addr_plus1).
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
-- Library definitions
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all; -- need the unsigned functions
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
entity bus2ip_amux is
Generic (
C_IPIF_ABUS_WIDTH : Integer;
C_IPIF_DBUS_WIDTH : integer
);
port (
-- Clock and Reset
Bus2IP_Reset_i : in std_logic;
Bus2IP_Clk_i : in std_logic;
-- Select control from the Master Attachment
Mstr_sel_ma : in std_logic;
-- Slave Attachment I/O
Addr_Cntr_ClkEN : in std_logic;
Addr_Sel : in std_logic_vector(0 to 1);
Bus2IP_Addr_sa : in std_logic_vector(0 to C_IPIF_ABUS_WIDTH-1);
-- Address Bus inputs from the IP Master
IP2IP_Addr : in std_logic_vector(0 to C_IPIF_ABUS_WIDTH-1);
-- Address Bus inputs from the DMA/SG engine
DMA2IP_Addr : in std_logic_vector(0 to C_IPIF_ABUS_WIDTH-1);
-- IPIF & IP address bus source (AMUX output)
Bus2IP_Addr_i : out std_logic_vector(0 to C_IPIF_ABUS_WIDTH-1);
-- Byte-enable channels
Bus2IP_BE_sa : in std_logic_vector(0 to C_IPIF_DBUS_WIDTH/8 -1);
IP2IP_BE : in std_logic_vector(0 to C_IPIF_DBUS_WIDTH/8 -1);
DMA2IP_BE : in std_logic_vector(0 to C_IPIF_DBUS_WIDTH/8 -1);
Bus2IP_BE_i : out std_logic_vector(0 to C_IPIF_DBUS_WIDTH/8 -1)
);
end bus2ip_amux;
architecture implementation of bus2ip_amux is
-- COMPONENTS
--TYPES
-- no types
-- CONSTANTS
-- no constants
--INTERNAL SIGNALS
Signal selected_addr : std_logic_vector(0 to C_IPIF_ABUS_WIDTH-1);
Signal reg_addr_plus1 : unsigned(0 to C_IPIF_ABUS_WIDTH-1);
Signal addr_plus1 : unsigned(0 to C_IPIF_ABUS_WIDTH-1);
Signal selected_be : std_logic_vector(0 to C_IPIF_DBUS_WIDTH/8-1);
-------------------------
-- XST Begin Work Around, needed at least until F.28, where a fix is planned.
-------------------------
attribute KEEP : string;
attribute KEEP of reg_addr_plus1: signal is "TRUE";
-----------------------
-- XST End Work Around
-----------------------
--------------------------------------------------------------------------------------------------------------
-------------------------------------- start of logic -------------------------------------------------
begin
Bus2IP_Addr_i <= selected_addr;
Bus2IP_BE_i <= selected_be;
-------------------------------------------------------------------------
-- This process switches the desired input address to the MUX output.
-------------------------------------------------------------------------
SELECT_THE_ADDRESSES : process (Addr_Sel, Mstr_sel_ma, Bus2IP_Addr_sa, DMA2IP_Addr,
IP2IP_Addr, reg_addr_plus1,
DMA2IP_BE, IP2IP_BE, Bus2IP_BE_sa)
Begin
Case Addr_Sel Is
When "00" => -- External Bus address Selected
selected_addr <= Bus2IP_Addr_sa;
selected_be <= Bus2IP_BE_sa;
When "01" => -- Local Master Address Selected
If (Mstr_sel_ma = '1') Then
selected_addr <= DMA2IP_Addr;
selected_be <= DMA2IP_BE;
else
selected_addr <= IP2IP_Addr;
selected_be <= IP2IP_BE;
End if;
When "10" => -- Address Register Output Plus 1 Selected
selected_addr <= std_logic_vector(reg_addr_plus1);
If (Mstr_sel_ma = '1') Then
selected_be <= DMA2IP_BE;
else
selected_be <= IP2IP_BE;
End if;
When others => -- Default to External Bus Selected
selected_addr <= Bus2IP_Addr_sa;
selected_be <= Bus2IP_BE_sa;
End case;
End process; --SELECT_THE_ADDRESSES
-------------------------------------------------------------------------
-- Combinationally increment the registered address output for
-- feedback into the select mux
-------------------------------------------------------------------------
INCREMENT_THE_ADDR : process (selected_addr)
Begin
addr_plus1 <= unsigned(selected_addr) + C_IPIF_DBUS_WIDTH/8;
End process; -- INCREMENT_THE_ADDR
-------------------------------------------------------------------------
-- Combinationally increment the registered address by the word size for
-- feedback into the select mux
-------------------------------------------------------------------------
REG_THE_ADDR_PLUS_1 : process (Bus2IP_Reset_i, Bus2IP_Clk_i)
Begin
If (Bus2IP_Reset_i = '1') Then
reg_addr_plus1 <= (others => '0');
Elsif (Bus2IP_Clk_i'EVENT and Bus2IP_Clk_i = '1') Then
If (Addr_Cntr_ClkEN = '1') Then
reg_addr_plus1 <= addr_plus1; -- register address+1 input
Else
null; -- Hold last address+1 registered
End if;
else
null;
End if;
End process; -- REG_THE_ADDR_PLUS_1
end implementation;
|
bsd-3-clause
|
masson2013/heterogeneous_hthreads
|
src/platforms/xilinx/numa3_hwti/design/pcores/plb_scheduler_v1_00_a/hdl/vhdl/parallel.vhd
|
11
|
9985
|
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity parallel is
generic
(
-- The number of input bits into the priority encoder
INPUT_BITS : integer := 128;
-- The number of output bits from the priority encoder.
-- For correct operation the number of output bits should be
-- any number greater than or equal to log2( INPUT_BITS ).
OUTPUT_BITS : integer := 7;
-- The number of bits to consider at a time.
-- This number should be less that INPUT_BITS and should divide
-- INPUT_BITS evenly.
CHUNK_BITS : integer := 32
);
port
(
clk : in std_logic;
rst : in std_logic;
input : in std_logic_vector(0 to INPUT_BITS - 1);
enable : in std_logic;
output : out std_logic_vector(0 to OUTPUT_BITS - 1)
);
end entity parallel;
-------------------------------------------------------------------------------
-- architecture
-------------------------------------------------------------------------------
architecture imp of parallel is
type find_state is ( narrow_search, prior_encode, prior_read );
-- Find the log base 2 of a natural number.
-- This function works for both synthesis and simulation
function log2( N : in natural ) return positive is
begin
if N <= 2 then
return 1;
else
return 1 + log2(N/2);
end if;
end;
-- Determine if any bit in the array is set.
-- If any of the bits are set then '1' is returned,
-- otherwise '0' is returned.
function bit_set( data : in std_logic_vector ) return std_logic is
begin
for i in data'range loop
if( data(i) = '1' ) then
return '1';
end if;
end loop;
return '0';
end function;
-- Return the array slice that is used for a given chunk index
function bit_range( data : in std_logic_vector; index : in integer ) return std_logic_vector is
begin
return data( (index * CHUNK_BITS) to ((index + 1) * CHUNK_BITS) - 1 );
end function;
-- Given the number of INPUT_BITS and the number of CHUNK_BITS we
-- can determine the number of chunks we will need to look at.
constant CHUNK_NUM : integer := INPUT_BITS / CHUNK_BITS;
-- Given the number of CHUNK_BITS we can determine the number of output
-- bits that the priority encoder is going to return.
constant CHUNK_OUT : integer := log2( CHUNK_BITS );
-- The number of EXTRA bits is the number of extra bits that we number add
-- to the output of the priority encoder to get the real output.
constant EXTRA_BITS : integer := OUTPUT_BITS - CHUNK_OUT;
-- These two signals control the state transitions in the FSM which
-- produces the output for this entity.
signal find_current : find_state;
signal find_next : find_state;
-- These signals are the input signals into the priority encoder.
signal pri_in : std_logic_vector(0 to CHUNK_BITS - 1);
signal pri_in_next : std_logic_vector(0 to CHUNK_BITS - 1);
-- This signal is the output from the priority encoder.
signal pri_out : std_logic_vector(0 to CHUNK_OUT - 1 );
-- This is the overall output from the design. It could be removed
-- by just assigning to output instead, however, that would mean that
-- output would need to be an inout signal instead of just an out.
signal best : std_logic_vector(0 to OUTPUT_BITS - 1);
signal best_next : std_logic_vector(0 to OUTPUT_BITS - 1);
-- These signals are used to narrow our search for the highest priority.
signal narrow : std_logic_vector(0 to CHUNK_NUM - 1);
signal narrow_next : std_logic_vector(0 to CHUNK_NUM - 1);
-- This forces the synthesizer to recognize the pri_out signal as the
-- output from a priority encoder. XST documentation says that the
-- synthesizer will recognize a priority encoder by setting this to
-- "yes" but will not actually generate a priority encoder unless this
-- is set to "force".
attribute PRIORITY_EXTRACT : string;
attribute PRIORITY_EXTRACT of pri_out: signal is "force";
begin
-- Output the best priority
output <= best;
-- This process is the priority encoder. It will determine the highest bits
-- set in the array pri_in and will return its index on the signal pri_out.
--
-- Notice that this process is NOT sensitive to the clock. This process
-- would not be recognized as a priority encoder if it were sensitive to
-- the clock.
priority_encoder : process ( pri_in ) is
begin
-- The default output. It no bits are set in the array (or if only
-- bit 0 is set) then this is the value returned.
pri_out <= (others => '0');
-- This statement loops over the entire array and finds the index of the
-- highest bit set. The index of the highest bit set is then converted
-- into a std_logic_vector and output onto pri_out.
--
-- Notice that the loop starts at the highest index and proceeds to the
-- lowest index. This is because in our system the lower the bit index
-- the higher the priority.
for i in pri_in'high downto 0 loop
if( pri_in(i) = '1' ) then
pri_out <= std_logic_vector( to_unsigned(i, pri_out'length) );
end if;
end loop;
end process priority_encoder;
-- This process controls the state transition from the current state
-- to the next state (and also handles reset). It also takes care of
-- transitioning FSM inputs to there next values.
find_best_next : process ( clk, rst, find_next ) is
begin
if( rising_edge(clk) ) then
if( rst = '1' ) then
find_current <= narrow_search;
best <= (others => '0');
pri_in <= (others => '0');
narrow <= (others => '0');
else
find_current <= find_next;
best <= best_next;
pri_in <= pri_in_next;
narrow <= narrow_next;
end if;
end if;
end process find_best_next;
-- This process implements the FSM logic. It is broken into three states.
-- NARROW_SEARCH:
-- This state narrows the priority search by taking each chunk of the input and
-- or'ing all of the chunks bits together. This provides an indication of which
-- chunk of the input contains the highest priority.
--
-- This allows use to use a smaller priority encoder as the expense of a 2 clock
-- cycle delay. However, the smaller priority encoder provides significant savings
-- in terms of slice utilization.
--
-- PRIOR_ENCODE:
-- This state determines which of the chunks contains the highest priority input and
-- then places that chunk's input bits onto the priority encoders input lines. If no
-- bits in the input array are set then the priority encoders input lines are NOT
-- changed.
--
-- PRIOR_READ:
-- This state reads the data off of the priority encoder and then adds the extra bits
-- needed to produce the full priority value. This is done because the priority encoder
-- returns the index of the highest bit of the selected chunk but we want the index
-- of the highest bit set in the input not in the chunk.
--
-- Luckily, the translation from chunk index to input index it straight forward because
-- chunks are just non-overlapping slices of the input array.
find_best_logic : process( find_current, input, best, pri_in, narrow, pri_out, enable ) is
begin
find_next <= find_current;
best_next <= best;
pri_in_next <= pri_in;
narrow_next <= narrow;
case find_current is
when narrow_search =>
if( enable = '1' ) then
for i in narrow'high downto 0 loop
narrow_next(i) <= bit_set( bit_range( input, i ) );
end loop;
find_next <= prior_encode;
end if;
when prior_encode =>
for i in narrow'high downto 0 loop
if( narrow(i) = '1' ) then
pri_in_next <= bit_range( input, i );
--exit;
end if;
end loop;
find_next <= prior_read;
when prior_read =>
for i in narrow'high downto 0 loop
if( narrow(i) = '1' ) then
best_next <= std_logic_vector(to_unsigned(i,EXTRA_BITS)) & pri_out;
end if;
end loop;
find_next <= narrow_search;
end case;
end process find_best_logic;
end architecture imp;
|
bsd-3-clause
|
masson2013/heterogeneous_hthreads
|
src/platforms/xilinx/ml605_pr_smp1_14_7/design/pcores/plb_scheduler_v1_00_a/hdl/vhdl/parallel.vhd
|
11
|
9985
|
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity parallel is
generic
(
-- The number of input bits into the priority encoder
INPUT_BITS : integer := 128;
-- The number of output bits from the priority encoder.
-- For correct operation the number of output bits should be
-- any number greater than or equal to log2( INPUT_BITS ).
OUTPUT_BITS : integer := 7;
-- The number of bits to consider at a time.
-- This number should be less that INPUT_BITS and should divide
-- INPUT_BITS evenly.
CHUNK_BITS : integer := 32
);
port
(
clk : in std_logic;
rst : in std_logic;
input : in std_logic_vector(0 to INPUT_BITS - 1);
enable : in std_logic;
output : out std_logic_vector(0 to OUTPUT_BITS - 1)
);
end entity parallel;
-------------------------------------------------------------------------------
-- architecture
-------------------------------------------------------------------------------
architecture imp of parallel is
type find_state is ( narrow_search, prior_encode, prior_read );
-- Find the log base 2 of a natural number.
-- This function works for both synthesis and simulation
function log2( N : in natural ) return positive is
begin
if N <= 2 then
return 1;
else
return 1 + log2(N/2);
end if;
end;
-- Determine if any bit in the array is set.
-- If any of the bits are set then '1' is returned,
-- otherwise '0' is returned.
function bit_set( data : in std_logic_vector ) return std_logic is
begin
for i in data'range loop
if( data(i) = '1' ) then
return '1';
end if;
end loop;
return '0';
end function;
-- Return the array slice that is used for a given chunk index
function bit_range( data : in std_logic_vector; index : in integer ) return std_logic_vector is
begin
return data( (index * CHUNK_BITS) to ((index + 1) * CHUNK_BITS) - 1 );
end function;
-- Given the number of INPUT_BITS and the number of CHUNK_BITS we
-- can determine the number of chunks we will need to look at.
constant CHUNK_NUM : integer := INPUT_BITS / CHUNK_BITS;
-- Given the number of CHUNK_BITS we can determine the number of output
-- bits that the priority encoder is going to return.
constant CHUNK_OUT : integer := log2( CHUNK_BITS );
-- The number of EXTRA bits is the number of extra bits that we number add
-- to the output of the priority encoder to get the real output.
constant EXTRA_BITS : integer := OUTPUT_BITS - CHUNK_OUT;
-- These two signals control the state transitions in the FSM which
-- produces the output for this entity.
signal find_current : find_state;
signal find_next : find_state;
-- These signals are the input signals into the priority encoder.
signal pri_in : std_logic_vector(0 to CHUNK_BITS - 1);
signal pri_in_next : std_logic_vector(0 to CHUNK_BITS - 1);
-- This signal is the output from the priority encoder.
signal pri_out : std_logic_vector(0 to CHUNK_OUT - 1 );
-- This is the overall output from the design. It could be removed
-- by just assigning to output instead, however, that would mean that
-- output would need to be an inout signal instead of just an out.
signal best : std_logic_vector(0 to OUTPUT_BITS - 1);
signal best_next : std_logic_vector(0 to OUTPUT_BITS - 1);
-- These signals are used to narrow our search for the highest priority.
signal narrow : std_logic_vector(0 to CHUNK_NUM - 1);
signal narrow_next : std_logic_vector(0 to CHUNK_NUM - 1);
-- This forces the synthesizer to recognize the pri_out signal as the
-- output from a priority encoder. XST documentation says that the
-- synthesizer will recognize a priority encoder by setting this to
-- "yes" but will not actually generate a priority encoder unless this
-- is set to "force".
attribute PRIORITY_EXTRACT : string;
attribute PRIORITY_EXTRACT of pri_out: signal is "force";
begin
-- Output the best priority
output <= best;
-- This process is the priority encoder. It will determine the highest bits
-- set in the array pri_in and will return its index on the signal pri_out.
--
-- Notice that this process is NOT sensitive to the clock. This process
-- would not be recognized as a priority encoder if it were sensitive to
-- the clock.
priority_encoder : process ( pri_in ) is
begin
-- The default output. It no bits are set in the array (or if only
-- bit 0 is set) then this is the value returned.
pri_out <= (others => '0');
-- This statement loops over the entire array and finds the index of the
-- highest bit set. The index of the highest bit set is then converted
-- into a std_logic_vector and output onto pri_out.
--
-- Notice that the loop starts at the highest index and proceeds to the
-- lowest index. This is because in our system the lower the bit index
-- the higher the priority.
for i in pri_in'high downto 0 loop
if( pri_in(i) = '1' ) then
pri_out <= std_logic_vector( to_unsigned(i, pri_out'length) );
end if;
end loop;
end process priority_encoder;
-- This process controls the state transition from the current state
-- to the next state (and also handles reset). It also takes care of
-- transitioning FSM inputs to there next values.
find_best_next : process ( clk, rst, find_next ) is
begin
if( rising_edge(clk) ) then
if( rst = '1' ) then
find_current <= narrow_search;
best <= (others => '0');
pri_in <= (others => '0');
narrow <= (others => '0');
else
find_current <= find_next;
best <= best_next;
pri_in <= pri_in_next;
narrow <= narrow_next;
end if;
end if;
end process find_best_next;
-- This process implements the FSM logic. It is broken into three states.
-- NARROW_SEARCH:
-- This state narrows the priority search by taking each chunk of the input and
-- or'ing all of the chunks bits together. This provides an indication of which
-- chunk of the input contains the highest priority.
--
-- This allows use to use a smaller priority encoder as the expense of a 2 clock
-- cycle delay. However, the smaller priority encoder provides significant savings
-- in terms of slice utilization.
--
-- PRIOR_ENCODE:
-- This state determines which of the chunks contains the highest priority input and
-- then places that chunk's input bits onto the priority encoders input lines. If no
-- bits in the input array are set then the priority encoders input lines are NOT
-- changed.
--
-- PRIOR_READ:
-- This state reads the data off of the priority encoder and then adds the extra bits
-- needed to produce the full priority value. This is done because the priority encoder
-- returns the index of the highest bit of the selected chunk but we want the index
-- of the highest bit set in the input not in the chunk.
--
-- Luckily, the translation from chunk index to input index it straight forward because
-- chunks are just non-overlapping slices of the input array.
find_best_logic : process( find_current, input, best, pri_in, narrow, pri_out, enable ) is
begin
find_next <= find_current;
best_next <= best;
pri_in_next <= pri_in;
narrow_next <= narrow;
case find_current is
when narrow_search =>
if( enable = '1' ) then
for i in narrow'high downto 0 loop
narrow_next(i) <= bit_set( bit_range( input, i ) );
end loop;
find_next <= prior_encode;
end if;
when prior_encode =>
for i in narrow'high downto 0 loop
if( narrow(i) = '1' ) then
pri_in_next <= bit_range( input, i );
--exit;
end if;
end loop;
find_next <= prior_read;
when prior_read =>
for i in narrow'high downto 0 loop
if( narrow(i) = '1' ) then
best_next <= std_logic_vector(to_unsigned(i,EXTRA_BITS)) & pri_out;
end if;
end loop;
find_next <= narrow_search;
end case;
end process find_best_logic;
end architecture imp;
|
bsd-3-clause
|
masson2013/heterogeneous_hthreads
|
src/platforms/xilinx/numa3_hwti/design/pcores/plb_scheduler_v1_00_a/hdl/vhdl/plb_scheduler.vhd
|
9
|
35549
|
------------------------------------------------------------------------------
-- plb_scheduler.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: plb_scheduler.vhd
-- Version: 1.00.a
-- Description: Top level design, instantiates library components and user logic.
-- Date: Mon Apr 6 14:20:46 2009 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library plbv46_slave_single_v1_01_a;
use plbv46_slave_single_v1_01_a.plbv46_slave_single;
library plbv46_master_single_v1_01_a;
use plbv46_master_single_v1_01_a.plbv46_master_single;
library plb_scheduler_v1_00_a;
use plb_scheduler_v1_00_a.user_logic;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_BASEADDR -- PLBv46 slave: base address
-- C_HIGHADDR -- PLBv46 slave: high address
-- C_SPLB_AWIDTH -- PLBv46 slave: address bus width
-- C_SPLB_DWIDTH -- PLBv46 slave: data bus width
-- C_SPLB_NUM_MASTERS -- PLBv46 slave: Number of masters
-- C_SPLB_MID_WIDTH -- PLBv46 slave: master ID bus width
-- C_SPLB_NATIVE_DWIDTH -- PLBv46 slave: internal native data bus width
-- C_SPLB_P2P -- PLBv46 slave: point to point interconnect scheme
-- C_SPLB_SUPPORT_BURSTS -- PLBv46 slave: support bursts
-- C_SPLB_SMALLEST_MASTER -- PLBv46 slave: width of the smallest master
-- C_SPLB_CLK_PERIOD_PS -- PLBv46 slave: bus clock in picoseconds
-- C_INCLUDE_DPHASE_TIMER -- PLBv46 slave: Data Phase Timer configuration; 0 = exclude timer, 1 = include timer
-- C_FAMILY -- Xilinx FPGA family
-- C_MPLB_AWIDTH -- PLBv46 master: address bus width
-- C_MPLB_DWIDTH -- PLBv46 master: data bus width
-- C_MPLB_NATIVE_DWIDTH -- PLBv46 master: internal native data width
-- C_MPLB_P2P -- PLBv46 master: point to point interconnect scheme
-- C_MPLB_SMALLEST_SLAVE -- PLBv46 master: width of the smallest slave
-- C_MPLB_CLK_PERIOD_PS -- PLBv46 master: bus clock in picoseconds
--
-- Definition of Ports:
-- SPLB_Clk -- PLB main bus clock
-- SPLB_Rst -- PLB main bus reset
-- PLB_ABus -- PLB address bus
-- PLB_UABus -- PLB upper address bus
-- PLB_PAValid -- PLB primary address valid indicator
-- PLB_SAValid -- PLB secondary address valid indicator
-- PLB_rdPrim -- PLB secondary to primary read request indicator
-- PLB_wrPrim -- PLB secondary to primary write request indicator
-- PLB_masterID -- PLB current master identifier
-- PLB_abort -- PLB abort request indicator
-- PLB_busLock -- PLB bus lock
-- PLB_RNW -- PLB read/not write
-- PLB_BE -- PLB byte enables
-- PLB_MSize -- PLB master data bus size
-- PLB_size -- PLB transfer size
-- PLB_type -- PLB transfer type
-- PLB_lockErr -- PLB lock error indicator
-- PLB_wrDBus -- PLB write data bus
-- PLB_wrBurst -- PLB burst write transfer indicator
-- PLB_rdBurst -- PLB burst read transfer indicator
-- PLB_wrPendReq -- PLB write pending bus request indicator
-- PLB_rdPendReq -- PLB read pending bus request indicator
-- PLB_wrPendPri -- PLB write pending request priority
-- PLB_rdPendPri -- PLB read pending request priority
-- PLB_reqPri -- PLB current request priority
-- PLB_TAttribute -- PLB transfer attribute
-- Sl_addrAck -- Slave address acknowledge
-- Sl_SSize -- Slave data bus size
-- Sl_wait -- Slave wait indicator
-- Sl_rearbitrate -- Slave re-arbitrate bus indicator
-- Sl_wrDAck -- Slave write data acknowledge
-- Sl_wrComp -- Slave write transfer complete indicator
-- Sl_wrBTerm -- Slave terminate write burst transfer
-- Sl_rdDBus -- Slave read data bus
-- Sl_rdWdAddr -- Slave read word address
-- Sl_rdDAck -- Slave read data acknowledge
-- Sl_rdComp -- Slave read transfer complete indicator
-- Sl_rdBTerm -- Slave terminate read burst transfer
-- Sl_MBusy -- Slave busy indicator
-- Sl_MWrErr -- Slave write error indicator
-- Sl_MRdErr -- Slave read error indicator
-- Sl_MIRQ -- Slave interrupt indicator
-- MPLB_Clk -- PLB main bus Clock
-- MPLB_Rst -- PLB main bus Reset
-- MD_error -- Master detected error status output
-- M_request -- Master request
-- M_priority -- Master request priority
-- M_busLock -- Master buslock
-- M_RNW -- Master read/nor write
-- M_BE -- Master byte enables
-- M_MSize -- Master data bus size
-- M_size -- Master transfer size
-- M_type -- Master transfer type
-- M_TAttribute -- Master transfer attribute
-- M_lockErr -- Master lock error indicator
-- M_abort -- Master abort bus request indicator
-- M_UABus -- Master upper address bus
-- M_ABus -- Master address bus
-- M_wrDBus -- Master write data bus
-- M_wrBurst -- Master burst write transfer indicator
-- M_rdBurst -- Master burst read transfer indicator
-- PLB_MAddrAck -- PLB reply to master for address acknowledge
-- PLB_MSSize -- PLB reply to master for slave data bus size
-- PLB_MRearbitrate -- PLB reply to master for bus re-arbitrate indicator
-- PLB_MTimeout -- PLB reply to master for bus time out indicator
-- PLB_MBusy -- PLB reply to master for slave busy indicator
-- PLB_MRdErr -- PLB reply to master for slave read error indicator
-- PLB_MWrErr -- PLB reply to master for slave write error indicator
-- PLB_MIRQ -- PLB reply to master for slave interrupt indicator
-- PLB_MRdDBus -- PLB reply to master for read data bus
-- PLB_MRdWdAddr -- PLB reply to master for read word address
-- PLB_MRdDAck -- PLB reply to master for read data acknowledge
-- PLB_MRdBTerm -- PLB reply to master for terminate read burst indicator
-- PLB_MWrDAck -- PLB reply to master for write data acknowledge
-- PLB_MWrBTerm -- PLB reply to master for terminate write burst indicator
------------------------------------------------------------------------------
entity plb_scheduler is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_SPLB_AWIDTH : integer := 32;
C_SPLB_DWIDTH : integer := 128;
C_SPLB_NUM_MASTERS : integer := 8;
C_SPLB_MID_WIDTH : integer := 3;
C_SPLB_NATIVE_DWIDTH : integer := 32;
C_SPLB_P2P : integer := 0;
C_SPLB_SUPPORT_BURSTS : integer := 0;
C_SPLB_SMALLEST_MASTER : integer := 32;
C_SPLB_CLK_PERIOD_PS : integer := 10000;
C_INCLUDE_DPHASE_TIMER : integer := 0;
C_FAMILY : string := "virtex5";
C_MPLB_AWIDTH : integer := 32;
C_MPLB_DWIDTH : integer := 128;
C_MPLB_NATIVE_DWIDTH : integer := 32;
C_MPLB_P2P : integer := 0;
C_MPLB_SMALLEST_SLAVE : integer := 32;
C_MPLB_CLK_PERIOD_PS : integer := 10000
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
Soft_Reset : in std_logic;
Reset_Done : out std_logic;
Soft_Stop : in std_logic;
SWTM_DOB : in std_logic_vector(0 to 31);
SWTM_ADDRB : out std_logic_vector(0 to 8);
SWTM_DIB : out std_logic_vector(0 to 31);
SWTM_ENB : out std_logic;
SWTM_WEB : out std_logic;
TM2SCH_current_cpu_tid : in std_logic_vector(0 to 7);
TM2SCH_opcode : in std_logic_vector(0 to 5);
TM2SCH_data : in std_logic_vector(0 to 7);
TM2SCH_request : in std_logic;
SCH2TM_busy : out std_logic;
SCH2TM_data : out std_logic_vector(0 to 7);
SCH2TM_next_cpu_tid : out std_logic_vector(0 to 7);
SCH2TM_next_tid_valid : out std_logic;
Preemption_Interrupt : out std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to C_SPLB_MID_WIDTH-1);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to C_SPLB_DWIDTH/8-1);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to C_SPLB_DWIDTH-1);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to C_SPLB_DWIDTH-1);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MWrErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MRdErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MIRQ : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
MPLB_Clk : in std_logic;
MPLB_Rst : in std_logic;
MD_error : out std_logic;
M_request : out std_logic;
M_priority : out std_logic_vector(0 to 1);
M_busLock : out std_logic;
M_RNW : out std_logic;
M_BE : out std_logic_vector(0 to C_MPLB_DWIDTH/8-1);
M_MSize : out std_logic_vector(0 to 1);
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_TAttribute : out std_logic_vector(0 to 15);
M_lockErr : out std_logic;
M_abort : out std_logic;
M_UABus : out std_logic_vector(0 to 31);
M_ABus : out std_logic_vector(0 to 31);
M_wrDBus : out std_logic_vector(0 to C_MPLB_DWIDTH-1);
M_wrBurst : out std_logic;
M_rdBurst : out std_logic;
PLB_MAddrAck : in std_logic;
PLB_MSSize : in std_logic_vector(0 to 1);
PLB_MRearbitrate : in std_logic;
PLB_MTimeout : in std_logic;
PLB_MBusy : in std_logic;
PLB_MRdErr : in std_logic;
PLB_MWrErr : in std_logic;
PLB_MIRQ : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to (C_MPLB_DWIDTH-1));
PLB_MRdWdAddr : in std_logic_vector(0 to 3);
PLB_MRdDAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MWrBTerm : in std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of SPLB_Clk : signal is "CLK";
attribute SIGIS of MPLB_Clk : signal is "CLK";
attribute SIGIS of SPLB_Rst : signal is "RST";
attribute SIGIS of MPLB_Rst : signal is "RST";
end entity plb_scheduler;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of plb_scheduler is
------------------------------------------
-- Array of base/high address pairs for each address range
------------------------------------------
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
--constant USER_MST_BASEADDR : std_logic_vector := C_BASEADDR or X"00000100";
--constant USER_MST_HIGHADDR : std_logic_vector := C_BASEADDR or X"000001FF";
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
ZERO_ADDR_PAD & USER_SLV_HIGHADDR -- user logic slave space high address
);
------------------------------------------
-- Array of desired number of chip enables for each address range
------------------------------------------
constant USER_SLV_NUM_REG : integer := 1;
--constant USER_MST_NUM_REG : integer := 4;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;--+USER_MST_NUM_REG;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => pad_power2(USER_SLV_NUM_REG) -- number of ce for user logic slave space
);
------------------------------------------
-- Ratio of bus clock to core clock (for use in dual clock systems)
-- 1 = ratio is 1:1
-- 2 = ratio is 2:1
------------------------------------------
constant IPIF_BUS2CORE_CLK_RATIO : integer := 1;
------------------------------------------
-- Width of the slave data bus (32 only)
------------------------------------------
constant USER_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
constant IPIF_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
------------------------------------------
-- Width of the master data bus (32 only)
------------------------------------------
constant USER_MST_DWIDTH : integer := C_MPLB_NATIVE_DWIDTH;
constant IPIF_MST_DWIDTH : integer := C_MPLB_NATIVE_DWIDTH;
------------------------------------------
-- Width of the master address bus (32 only)
------------------------------------------
constant USER_MST_AWIDTH : integer := C_MPLB_AWIDTH;
------------------------------------------
-- Index for CS/CE
------------------------------------------
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
--constant USER_MST_CS_INDEX : integer := 1;
--constant USER_MST_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_MST_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations
------------------------------------------
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Reset : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(0 to C_SPLB_AWIDTH-1);
signal ipif_Bus2IP_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(0 to IPIF_SLV_DWIDTH/8-1);
signal ipif_Bus2IP_CS : std_logic_vector(0 to ((IPIF_ARD_ADDR_RANGE_ARRAY'length)/2)-1);
signal ipif_Bus2IP_RdCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
signal ipif_Bus2IP_WrCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
signal ipif_IP2Bus_MstRd_Req : std_logic;
signal ipif_IP2Bus_MstWr_Req : std_logic;
signal ipif_IP2Bus_Mst_Addr : std_logic_vector(0 to C_MPLB_AWIDTH-1);
signal ipif_IP2Bus_Mst_BE : std_logic_vector(0 to C_MPLB_NATIVE_DWIDTH/8-1);
signal ipif_IP2Bus_Mst_Lock : std_logic;
signal ipif_IP2Bus_Mst_Reset : std_logic;
signal ipif_Bus2IP_Mst_CmdAck : std_logic;
signal ipif_Bus2IP_Mst_Cmplt : std_logic;
signal ipif_Bus2IP_Mst_Error : std_logic;
signal ipif_Bus2IP_Mst_Rearbitrate : std_logic;
signal ipif_Bus2IP_Mst_Cmd_Timeout : std_logic;
signal ipif_Bus2IP_MstRd_d : std_logic_vector(0 to C_MPLB_NATIVE_DWIDTH-1);
signal ipif_Bus2IP_MstRd_src_rdy_n : std_logic;
signal ipif_IP2Bus_MstWr_d : std_logic_vector(0 to C_MPLB_NATIVE_DWIDTH-1);
signal ipif_Bus2IP_MstWr_dst_rdy_n : std_logic;
signal user_Bus2IP_RdCE : std_logic_vector(0 to USER_NUM_REG-1);
signal user_Bus2IP_WrCE : std_logic_vector(0 to USER_NUM_REG-1);
signal user_IP2Bus_Data : std_logic_vector(0 to USER_SLV_DWIDTH-1);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
begin
------------------------------------------
-- instantiate plbv46_slave_single
------------------------------------------
PLBV46_SLAVE_SINGLE_I : entity plbv46_slave_single_v1_01_a.plbv46_slave_single
generic map
(
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_SPLB_P2P => C_SPLB_P2P,
C_BUS2CORE_CLK_RATIO => IPIF_BUS2CORE_CLK_RATIO,
C_SPLB_MID_WIDTH => C_SPLB_MID_WIDTH,
C_SPLB_NUM_MASTERS => C_SPLB_NUM_MASTERS,
C_SPLB_AWIDTH => C_SPLB_AWIDTH,
C_SPLB_DWIDTH => C_SPLB_DWIDTH,
C_SIPIF_DWIDTH => IPIF_SLV_DWIDTH,
C_INCLUDE_DPHASE_TIMER => C_INCLUDE_DPHASE_TIMER,
C_FAMILY => C_FAMILY
)
port map
(
SPLB_Clk => SPLB_Clk,
SPLB_Rst => SPLB_Rst,
PLB_ABus => PLB_ABus,
PLB_UABus => PLB_UABus,
PLB_PAValid => PLB_PAValid,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_masterID => PLB_masterID,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_MSize => PLB_MSize,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_lockErr => PLB_lockErr,
PLB_wrDBus => PLB_wrDBus,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendPri => PLB_rdPendPri,
PLB_reqPri => PLB_reqPri,
PLB_TAttribute => PLB_TAttribute,
Sl_addrAck => Sl_addrAck,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MBusy => Sl_MBusy,
Sl_MWrErr => Sl_MWrErr,
Sl_MRdErr => Sl_MRdErr,
Sl_MIRQ => Sl_MIRQ,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => ipif_Bus2IP_Reset,
IP2Bus_Data => ipif_IP2Bus_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE
);
------------------------------------------
-- instantiate plbv46_master_single
------------------------------------------
PLBV46_MASTER_SINGLE_I : entity plbv46_master_single_v1_01_a.plbv46_master_single
generic map
(
C_MPLB_AWIDTH => C_MPLB_AWIDTH,
C_MPLB_DWIDTH => C_MPLB_DWIDTH,
C_MPLB_NATIVE_DWIDTH => IPIF_MST_DWIDTH,
C_FAMILY => C_FAMILY
)
port map
(
MPLB_Clk => MPLB_Clk,
MPLB_Rst => MPLB_Rst,
MD_error => MD_error,
M_request => M_request,
M_priority => M_priority,
M_busLock => M_busLock,
M_RNW => M_RNW,
M_BE => M_BE,
M_MSize => M_MSize,
M_size => M_size,
M_type => M_type,
M_TAttribute => M_TAttribute,
M_lockErr => M_lockErr,
M_abort => M_abort,
M_UABus => M_UABus,
M_ABus => M_ABus,
M_wrDBus => M_wrDBus,
M_wrBurst => M_wrBurst,
M_rdBurst => M_rdBurst,
PLB_MAddrAck => PLB_MAddrAck,
PLB_MSSize => PLB_MSSize,
PLB_MRearbitrate => PLB_MRearbitrate,
PLB_MTimeout => PLB_MTimeout,
PLB_MBusy => PLB_MBusy,
PLB_MRdErr => PLB_MRdErr,
PLB_MWrErr => PLB_MWrErr,
PLB_MIRQ => PLB_MIRQ,
PLB_MRdDBus => PLB_MRdDBus,
PLB_MRdWdAddr => PLB_MRdWdAddr,
PLB_MRdDAck => PLB_MRdDAck,
PLB_MRdBTerm => PLB_MRdBTerm,
PLB_MWrDAck => PLB_MWrDAck,
PLB_MWrBTerm => PLB_MWrBTerm,
IP2Bus_MstRd_Req => ipif_IP2Bus_MstRd_Req,
IP2Bus_MstWr_Req => ipif_IP2Bus_MstWr_Req,
IP2Bus_Mst_Addr => ipif_IP2Bus_Mst_Addr,
IP2Bus_Mst_BE => ipif_IP2Bus_Mst_BE,
IP2Bus_Mst_Lock => ipif_IP2Bus_Mst_Lock,
IP2Bus_Mst_Reset => ipif_IP2Bus_Mst_Reset,
Bus2IP_Mst_CmdAck => ipif_Bus2IP_Mst_CmdAck,
Bus2IP_Mst_Cmplt => ipif_Bus2IP_Mst_Cmplt,
Bus2IP_Mst_Error => ipif_Bus2IP_Mst_Error,
Bus2IP_Mst_Rearbitrate => ipif_Bus2IP_Mst_Rearbitrate,
Bus2IP_Mst_Cmd_Timeout => ipif_Bus2IP_Mst_Cmd_Timeout,
Bus2IP_MstRd_d => ipif_Bus2IP_MstRd_d,
Bus2IP_MstRd_src_rdy_n => ipif_Bus2IP_MstRd_src_rdy_n,
IP2Bus_MstWr_d => ipif_IP2Bus_MstWr_d,
Bus2IP_MstWr_dst_rdy_n => ipif_Bus2IP_MstWr_dst_rdy_n
);
------------------------------------------
-- instantiate User Logic
------------------------------------------
USER_LOGIC_I : entity plb_scheduler_v1_00_a.user_logic
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
--USER generics mapped here
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_SLV_DWIDTH => USER_SLV_DWIDTH,
C_MST_AWIDTH => USER_MST_AWIDTH,
C_MST_DWIDTH => USER_MST_DWIDTH,
C_NUM_REG => USER_NUM_REG
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
--USER ports mapped here
Soft_Reset => Soft_Reset ,
Reset_Done => Reset_Done ,
Soft_Stop => Soft_Stop ,
SWTM_DOB => SWTM_DOB ,
SWTM_ADDRB => SWTM_ADDRB ,
SWTM_DIB => SWTM_DIB ,
SWTM_ENB => SWTM_ENB ,
SWTM_WEB => SWTM_WEB ,
TM2SCH_current_cpu_tid => TM2SCH_current_cpu_tid ,
TM2SCH_opcode => TM2SCH_opcode ,
TM2SCH_data => TM2SCH_data ,
TM2SCH_request => TM2SCH_request ,
SCH2TM_busy => SCH2TM_busy ,
SCH2TM_data => SCH2TM_data ,
SCH2TM_next_cpu_tid => SCH2TM_next_cpu_tid ,
SCH2TM_next_tid_valid => SCH2TM_next_tid_valid ,
Preemption_Interrupt => Preemption_Interrupt ,
-- MAP USER PORTS ABOVE THIS LINE ------------------
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => ipif_Bus2IP_Reset,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error,
IP2Bus_MstRd_Req => ipif_IP2Bus_MstRd_Req,
IP2Bus_MstWr_Req => ipif_IP2Bus_MstWr_Req,
IP2Bus_Mst_Addr => ipif_IP2Bus_Mst_Addr,
IP2Bus_Mst_BE => ipif_IP2Bus_Mst_BE,
IP2Bus_Mst_Lock => ipif_IP2Bus_Mst_Lock,
IP2Bus_Mst_Reset => ipif_IP2Bus_Mst_Reset,
Bus2IP_Mst_CmdAck => ipif_Bus2IP_Mst_CmdAck,
Bus2IP_Mst_Cmplt => ipif_Bus2IP_Mst_Cmplt,
Bus2IP_Mst_Error => ipif_Bus2IP_Mst_Error,
Bus2IP_Mst_Rearbitrate => ipif_Bus2IP_Mst_Rearbitrate,
Bus2IP_Mst_Cmd_Timeout => ipif_Bus2IP_Mst_Cmd_Timeout,
Bus2IP_MstRd_d => ipif_Bus2IP_MstRd_d,
Bus2IP_MstRd_src_rdy_n => ipif_Bus2IP_MstRd_src_rdy_n,
IP2Bus_MstWr_d => ipif_IP2Bus_MstWr_d,
Bus2IP_MstWr_dst_rdy_n => ipif_Bus2IP_MstWr_dst_rdy_n
);
------------------------------------------
-- connect internal signals
------------------------------------------
IP2BUS_DATA_MUX_PROC : process( ipif_Bus2IP_CS, user_IP2Bus_Data ) is
begin
case ipif_Bus2IP_CS is
when "1" => ipif_IP2Bus_Data <= user_IP2Bus_Data;
when others => ipif_IP2Bus_Data <= (others => '0');
end case;
end process IP2BUS_DATA_MUX_PROC;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;
user_Bus2IP_RdCE(0 to USER_SLV_NUM_REG-1) <= ipif_Bus2IP_RdCE(USER_SLV_CE_INDEX to USER_SLV_CE_INDEX+USER_SLV_NUM_REG-1);
--user_Bus2IP_RdCE(USER_SLV_NUM_REG to USER_NUM_REG-1) <= ipif_Bus2IP_RdCE(USER_MST_CE_INDEX to USER_MST_CE_INDEX+USER_MST_NUM_REG-1);
user_Bus2IP_WrCE(0 to USER_SLV_NUM_REG-1) <= ipif_Bus2IP_WrCE(USER_SLV_CE_INDEX to USER_SLV_CE_INDEX+USER_SLV_NUM_REG-1);
--user_Bus2IP_WrCE(USER_SLV_NUM_REG to USER_NUM_REG-1) <= ipif_Bus2IP_WrCE(USER_MST_CE_INDEX to USER_MST_CE_INDEX+USER_MST_NUM_REG-1);
end IMP;
|
bsd-3-clause
|
masson2013/heterogeneous_hthreads
|
src/platforms/xilinx/hwti_mblaze_6smp/design/pcores/plb_cond_vars_v1_00_a/hdl/vhdl/condvar_tb.vhd
|
9
|
5092
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:46:38 06/16/2009
-- Design Name:
-- Module Name: /home/jagron/ise_projects/cond_var/proj/condvar_tb.vhd
-- Project Name: proj
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: condvar
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
ENTITY condvar_tb IS
END condvar_tb;
ARCHITECTURE behavior OF condvar_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT condvar
PORT(
msg_chan_channelDataIn : OUT std_logic_vector(0 to 7);
msg_chan_channelDataOut : IN std_logic_vector(0 to 7);
msg_chan_exists : IN std_logic;
msg_chan_full : IN std_logic;
msg_chan_channelRead : OUT std_logic;
msg_chan_channelWrite : OUT std_logic;
cmd : IN std_logic;
opcode : IN std_logic_vector(0 to 1);
cvar : IN std_logic_vector(0 to 7);
tid : IN std_logic_vector(0 to 7);
ack : OUT std_logic;
clock_sig : IN std_logic;
reset_sig : IN std_logic
);
END COMPONENT;
--Inputs
signal msg_chan_channelDataOut : std_logic_vector(0 to 7) := (others => '0');
signal msg_chan_exists : std_logic := '0';
signal msg_chan_full : std_logic := '0';
signal cmd : std_logic := '0';
signal opcode : std_logic_vector(0 to 1) := (others => '0');
signal cvar : std_logic_vector(0 to 7) := (others => '0');
signal tid : std_logic_vector(0 to 7) := (others => '0');
signal clock_sig : std_logic := '0';
signal reset_sig : std_logic := '0';
--Outputs
signal msg_chan_channelDataIn : std_logic_vector(0 to 7);
signal msg_chan_channelRead : std_logic;
signal msg_chan_channelWrite : std_logic;
signal ack : std_logic;
-- Clock period definitions
constant clock_sig_period : time := 10 ns;
constant C_ENQ : std_logic_vector(0 to 2-1) := conv_std_logic_vector(0, 2); -- Opcode for "wait" enqueue
constant C_DEQ : std_logic_vector(0 to 2-1) := conv_std_logic_vector(1, 2); -- Opcode for "signal" dequeue
constant C_DEQALL : std_logic_vector(0 to 2-1) := conv_std_logic_vector(2, 2); -- Opcode for "broadcast" dequeue
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: condvar PORT MAP (
msg_chan_channelDataIn => msg_chan_channelDataIn,
msg_chan_channelDataOut => msg_chan_channelDataOut,
msg_chan_exists => msg_chan_exists,
msg_chan_full => msg_chan_full,
msg_chan_channelRead => msg_chan_channelRead,
msg_chan_channelWrite => msg_chan_channelWrite,
cmd => cmd,
opcode => opcode,
cvar => cvar,
tid => tid,
ack => ack,
clock_sig => clock_sig,
reset_sig => reset_sig
);
-- Clock process definitions
clock_sig_process :process
begin
clock_sig <= '0';
wait for clock_sig_period/2;
clock_sig <= '1';
wait for clock_sig_period/2;
end process;
-- Stimulus process
stim_proc: process
procedure operation(aopcode : in std_logic_vector(0 to 1); acvar: in integer; atid : in integer) is
begin
-- Send a packet
wait until clock_sig = '0' and ack = '0';
cvar <= conv_std_logic_vector(acvar,8);
tid <= conv_std_logic_vector(atid,8);
cmd <= '1';
opcode <= aopcode;
wait until ack = '1';
cvar <= conv_std_logic_vector(0, 8);
tid <= conv_std_logic_vector(0, 8);
cmd <= '0';
opcode <= "00";
wait until clock_sig = '0';
wait for 4*clock_sig_period;
end procedure operation;
begin
wait for clock_sig_period*10;
-- Reset the core
reset_sig <= '1';
wait for clock_sig_period;
reset_sig <= '0';
wait for clock_sig_period;
-- Delay
wait for clock_sig_period*2048;
-- ENQ
operation(C_ENQ,0,9);
-- ENQ
operation(C_ENQ,0,7);
-- ENQ
operation(C_ENQ,0,5);
-- ENQ
operation(C_ENQ,0,3);
-- ENQ
operation(C_ENQ,1,10);
-- ENQ
operation(C_ENQ,1,8);
-- ENQ
operation(C_ENQ,1,6);
-- ENQ
operation(C_ENQ,1,4);
-- DEQ
operation(C_DEQ,0,0);
operation(C_DEQ,0,0);
operation(C_DEQ,0,0);
-- DEQ-ALL
operation(C_DEQALL,1,0);
-- DEQ-ALL
operation(C_DEQALL,0,0);
wait;
end process;
END;
|
bsd-3-clause
|
masson2013/heterogeneous_hthreads
|
src/hardware/MyRepository/pcores/smp_synch_core_v1_00_a/hdl/vhdl/user_logic.vhd
|
2
|
17674
|
------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: user_logic.vhd
-- Version: 1.00.a
-- Description: User logic.
-- Date: Tue Aug 4 00:06:12 2009 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v2_00_a;
use proc_common_v2_00_a.proc_common_pkg.all;
-- DO NOT EDIT ABOVE THIS LINE --------------------
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_SLV_DWIDTH -- Slave interface data bus width
-- C_NUM_REG -- Number of software accessible registers
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Reset -- Bus to IP reset
-- Bus2IP_Data -- Bus to IP data bus
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- IP2Bus_Data -- IP to Bus data bus
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- IP2Bus_Error -- IP to Bus error response
------------------------------------------------------------------------------
entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_SLV_DWIDTH : integer := 32;
C_NUM_REG : integer := 16
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Data : in std_logic_vector(0 to C_SLV_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_SLV_DWIDTH/8-1);
Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_REG-1);
Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_REG-1);
IP2Bus_Data : out std_logic_vector(0 to C_SLV_DWIDTH-1);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk : signal is "CLK";
attribute SIGIS of Bus2IP_Reset : signal is "RST";
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
--USER signal declarations added here, as needed for user logic
------------------------------------------
-- Signals for user logic slave model s/w accessible register example
------------------------------------------
signal slv_reg0 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg1 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg2 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg3 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg4 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg5 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg6 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg7 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg8 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg9 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg10 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg11 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg12 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg13 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg14 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg15 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg_write_sel : std_logic_vector(0 to 15);
signal slv_reg_read_sel : std_logic_vector(0 to 15);
signal slv_ip2bus_data : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;
begin
--USER logic implementation added here
------------------------------------------
-- Example code to read/write user logic slave model s/w accessible registers
--
-- Note:
-- The example code presented here is to show you one way of reading/writing
-- software accessible registers implemented in the user logic slave model.
-- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond
-- to one software accessible register by the top level template. For example,
-- if you have four 32 bit software accessible registers in the user logic,
-- you are basically operating on the following memory mapped registers:
--
-- Bus2IP_WrCE/Bus2IP_RdCE Memory Mapped Register
-- "1000" C_BASEADDR + 0x0
-- "0100" C_BASEADDR + 0x4
-- "0010" C_BASEADDR + 0x8
-- "0001" C_BASEADDR + 0xC
--
------------------------------------------
slv_reg_write_sel <= Bus2IP_WrCE(0 to 15);
slv_reg_read_sel <= Bus2IP_RdCE(0 to 15);
slv_write_ack <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1) or Bus2IP_WrCE(2) or Bus2IP_WrCE(3) or Bus2IP_WrCE(4) or Bus2IP_WrCE(5) or Bus2IP_WrCE(6) or Bus2IP_WrCE(7) or Bus2IP_WrCE(8) or Bus2IP_WrCE(9) or Bus2IP_WrCE(10) or Bus2IP_WrCE(11) or Bus2IP_WrCE(12) or Bus2IP_WrCE(13) or Bus2IP_WrCE(14) or Bus2IP_WrCE(15);
slv_read_ack <= Bus2IP_RdCE(0) or Bus2IP_RdCE(1) or Bus2IP_RdCE(2) or Bus2IP_RdCE(3) or Bus2IP_RdCE(4) or Bus2IP_RdCE(5) or Bus2IP_RdCE(6) or Bus2IP_RdCE(7) or Bus2IP_RdCE(8) or Bus2IP_RdCE(9) or Bus2IP_RdCE(10) or Bus2IP_RdCE(11) or Bus2IP_RdCE(12) or Bus2IP_RdCE(13) or Bus2IP_RdCE(14) or Bus2IP_RdCE(15);
-- implement slave model software accessible register(s)
SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Reset = '1' then
slv_reg0 <= (others => '0');
slv_reg1 <= (others => '0');
slv_reg2 <= (others => '0');
slv_reg3 <= (others => '0');
slv_reg4 <= (others => '0');
slv_reg5 <= (others => '0');
slv_reg6 <= (others => '0');
slv_reg7 <= (others => '0');
slv_reg8 <= (others => '0');
slv_reg9 <= (others => '0');
slv_reg10 <= (others => '0');
slv_reg11 <= (others => '0');
slv_reg12 <= (others => '0');
slv_reg13 <= (others => '0');
slv_reg14 <= (others => '0');
slv_reg15 <= (others => '0');
else
case slv_reg_write_sel is
when "1000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
-- JA: Writing slv_reg0 updates both slv_reg0 and slv_reg1
slv_reg0(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
slv_reg1(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "0100000000000000" =>
-- JA: Upon writing, slv_reg1 auto increments
slv_reg1 <= slv_reg1 + 1;
-- for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
-- if ( Bus2IP_BE(byte_index) = '1' ) then
-- slv_reg1(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
-- end if;
-- end loop;
when "0010000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg2(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "0001000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg3(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "0000100000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg4(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "0000010000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg5(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "0000001000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg6(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "0000000100000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg7(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "0000000010000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg8(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "0000000001000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg9(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "0000000000100000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg10(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "0000000000010000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg11(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "0000000000001000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg12(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "0000000000000100" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg13(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "0000000000000010" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg14(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "0000000000000001" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg15(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when others => null;
end case;
end if;
end if;
end process SLAVE_REG_WRITE_PROC;
-- implement slave model software accessible register(s) read mux
SLAVE_REG_READ_PROC : process( slv_reg_read_sel, slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, slv_reg8, slv_reg9, slv_reg10, slv_reg11, slv_reg12, slv_reg13, slv_reg14, slv_reg15 ) is
begin
case slv_reg_read_sel is
when "1000000000000000" => slv_ip2bus_data <= slv_reg0;
when "0100000000000000" => slv_ip2bus_data <= slv_reg1;
when "0010000000000000" => slv_ip2bus_data <= slv_reg2;
when "0001000000000000" => slv_ip2bus_data <= slv_reg3;
when "0000100000000000" => slv_ip2bus_data <= slv_reg4;
when "0000010000000000" => slv_ip2bus_data <= slv_reg5;
when "0000001000000000" => slv_ip2bus_data <= slv_reg6;
when "0000000100000000" => slv_ip2bus_data <= slv_reg7;
when "0000000010000000" => slv_ip2bus_data <= slv_reg8;
when "0000000001000000" => slv_ip2bus_data <= slv_reg9;
when "0000000000100000" => slv_ip2bus_data <= slv_reg10;
when "0000000000010000" => slv_ip2bus_data <= slv_reg11;
when "0000000000001000" => slv_ip2bus_data <= slv_reg12;
when "0000000000000100" => slv_ip2bus_data <= slv_reg13;
when "0000000000000010" => slv_ip2bus_data <= slv_reg14;
when "0000000000000001" => slv_ip2bus_data <= slv_reg15;
when others => slv_ip2bus_data <= (others => '0');
end case;
end process SLAVE_REG_READ_PROC;
------------------------------------------
-- Example code to drive IP to Bus signals
------------------------------------------
IP2Bus_Data <= slv_ip2bus_data when slv_read_ack = '1' else
(others => '0');
IP2Bus_WrAck <= slv_write_ack;
IP2Bus_RdAck <= slv_read_ack;
IP2Bus_Error <= '0';
end IMP;
|
bsd-3-clause
|
masson2013/heterogeneous_hthreads
|
src/hardware/MyRepository/pcores/hw_threads/hw_acc_v1_00_a/hdl/vhdl/user_logics/functional/attr_destroy_3.vhd
|
2
|
15295
|
---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
FUNCTION_EXIT,
STATE_1,
STATE_2,
STATE_3,
STATE_4,
STATE_5,
STATE_6,
STATE_7,
STATE_8,
STATE_9,
STATE_10,
STATE_11,
STATE_12,
STATE_13,
STATE_14,
STATE_15,
STATE_16,
STATE_17,
STATE_18,
STATE_19,
STATE_20,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_STATE_1 : std_logic_vector(0 to 15) := x"0101";
constant U_STATE_2 : std_logic_vector(0 to 15) := x"0102";
constant U_STATE_3 : std_logic_vector(0 to 15) := x"0103";
constant U_STATE_4 : std_logic_vector(0 to 15) := x"0104";
constant U_STATE_5 : std_logic_vector(0 to 15) := x"0105";
constant U_STATE_6 : std_logic_vector(0 to 15) := x"0106";
constant U_STATE_7 : std_logic_vector(0 to 15) := x"0107";
constant U_STATE_8 : std_logic_vector(0 to 15) := x"0108";
constant U_STATE_9 : std_logic_vector(0 to 15) := x"0109";
constant U_STATE_10 : std_logic_vector(0 to 15) := x"0110";
constant U_STATE_11 : std_logic_vector(0 to 15) := x"0111";
constant U_STATE_12 : std_logic_vector(0 to 15) := x"0112";
constant U_STATE_13 : std_logic_vector(0 to 15) := x"0113";
constant U_STATE_14 : std_logic_vector(0 to 15) := x"0114";
constant U_STATE_15 : std_logic_vector(0 to 15) := x"0115";
constant U_STATE_16 : std_logic_vector(0 to 15) := x"0116";
constant U_STATE_17 : std_logic_vector(0 to 15) := x"0117";
constant U_STATE_18 : std_logic_vector(0 to 15) := x"0118";
constant U_STATE_19 : std_logic_vector(0 to 15) := x"0119";
constant U_STATE_20 : std_logic_vector(0 to 15) := x"0120";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
signal retVal, retVal_next : std_logic_vector(0 to 31);
signal arg, arg_next : std_logic_vector(0 to 31);
signal reg1, reg1_next : std_logic_vector(0 to 31);
signal reg2, reg2_next : std_logic_vector(0 to 31);
signal reg3, reg3_next : std_logic_vector(0 to 31);
signal reg4, reg4_next : std_logic_vector(0 to 31);
signal reg5, reg5_next : std_logic_vector(0 to 31);
signal reg6, reg6_next : std_logic_vector(0 to 31);
signal reg7, reg7_next : std_logic_vector(0 to 31);
signal reg8, reg8_next : std_logic_vector(0 to 31);
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock, intrfc2thrd_goWait) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
return_state <= return_state_next;
retVal <= retVal_next;
arg <= arg_next;
reg1 <= reg1_next;
reg2 <= reg2_next;
reg3 <= reg3_next;
reg4 <= reg4_next;
reg5 <= reg5_next;
reg6 <= reg6_next;
reg7 <= reg7_next;
reg8 <= reg8_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_STATE_1 =>
current_state <= STATE_1;
when U_STATE_2 =>
current_state <= STATE_2;
when U_STATE_3 =>
current_state <= STATE_3;
when U_STATE_4 =>
current_state <= STATE_4;
when U_STATE_5 =>
current_state <= STATE_5;
when U_STATE_6 =>
current_state <= STATE_6;
when U_STATE_7 =>
current_state <= STATE_7;
when U_STATE_8 =>
current_state <= STATE_8;
when U_STATE_9 =>
current_state <= STATE_9;
when U_STATE_10 =>
current_state <= STATE_10;
when U_STATE_11 =>
current_state <= STATE_11;
when U_STATE_12 =>
current_state <= STATE_12;
when U_STATE_13 =>
current_state <= STATE_13;
when U_STATE_14 =>
current_state <= STATE_14;
when U_STATE_15 =>
current_state <= STATE_15;
when U_STATE_16 =>
current_state <= STATE_16;
when U_STATE_17 =>
current_state <= STATE_17;
when U_STATE_18 =>
current_state <= STATE_18;
when U_STATE_19 =>
current_state <= STATE_19;
when U_STATE_20 =>
current_state <= STATE_20;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
retVal_next <= retVal;
arg_next <= arg;
reg1_next <= reg1;
reg2_next <= reg2;
reg3_next <= reg3;
reg4_next <= reg4;
reg5_next <= reg5;
reg6_next <= reg6;
reg7_next <= reg7;
reg8_next <= reg8;
-- attr_destroy_3.c
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
-- hthread_attr_t * attr = (hthread_attr_t *) arg
when FUNCTION_START =>
-- Pop the argument
thrd2intrfc_value <= Z32;
thrd2intrfc_opcode <= OPCODE_POP;
next_state <= WAIT_STATE;
return_state_next <= STATE_1;
-- hthread_attr_init( attr );
when STATE_1 =>
-- Push the argument to hthread_attr_init
arg_next <= intrfc2thrd_value;
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= intrfc2thrd_value;
next_state <= WAIT_STATE;
return_state_next <= STATE_2;
when STATE_2 =>
-- Call hthread_attr_init
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_ATTR_INIT;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_3;
next_state <= WAIT_STATE;
-- retVal = hthread_attr_destroy( attr );
when STATE_3 =>
-- Push the argument to hthread_attr_init
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg;
next_state <= WAIT_STATE;
return_state_next <= STATE_4;
when STATE_4 =>
-- Call hthread_attr_destroy
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_ATTR_DESTROY;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_5;
next_state <= WAIT_STATE;
when STATE_5 =>
retVal_next <= intrfc2thrd_value;
next_state <= FUNCTION_EXIT;
when FUNCTION_EXIT =>
--Same as hthread_exit( (void *) retVal );
thrd2intrfc_value <= retVal;
thrd2intrfc_opcode <= OPCODE_RETURN;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
|
bsd-3-clause
|
masson2013/heterogeneous_hthreads
|
src/hardware/MyRepository/pcores/hw_threads/hw_acc_v1_00_a/hdl/vhdl/user_logics/functional/equal_2.vhd
|
2
|
15082
|
---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
FUNCTION_EXIT,
STATE_1,
STATE_2,
STATE_3,
STATE_4,
STATE_5,
STATE_6,
STATE_7,
STATE_8,
STATE_9,
STATE_10,
STATE_11,
STATE_12,
STATE_13,
STATE_14,
STATE_15,
STATE_16,
STATE_17,
STATE_18,
STATE_19,
STATE_20,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_STATE_1 : std_logic_vector(0 to 15) := x"0101";
constant U_STATE_2 : std_logic_vector(0 to 15) := x"0102";
constant U_STATE_3 : std_logic_vector(0 to 15) := x"0103";
constant U_STATE_4 : std_logic_vector(0 to 15) := x"0104";
constant U_STATE_5 : std_logic_vector(0 to 15) := x"0105";
constant U_STATE_6 : std_logic_vector(0 to 15) := x"0106";
constant U_STATE_7 : std_logic_vector(0 to 15) := x"0107";
constant U_STATE_8 : std_logic_vector(0 to 15) := x"0108";
constant U_STATE_9 : std_logic_vector(0 to 15) := x"0109";
constant U_STATE_10 : std_logic_vector(0 to 15) := x"0110";
constant U_STATE_11 : std_logic_vector(0 to 15) := x"0111";
constant U_STATE_12 : std_logic_vector(0 to 15) := x"0112";
constant U_STATE_13 : std_logic_vector(0 to 15) := x"0113";
constant U_STATE_14 : std_logic_vector(0 to 15) := x"0114";
constant U_STATE_15 : std_logic_vector(0 to 15) := x"0115";
constant U_STATE_16 : std_logic_vector(0 to 15) := x"0116";
constant U_STATE_17 : std_logic_vector(0 to 15) := x"0117";
constant U_STATE_18 : std_logic_vector(0 to 15) := x"0118";
constant U_STATE_19 : std_logic_vector(0 to 15) := x"0119";
constant U_STATE_20 : std_logic_vector(0 to 15) := x"0120";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
signal retVal, retVal_next : std_logic_vector(0 to 31);
signal arg, arg_next : std_logic_vector(0 to 31);
signal reg1, reg1_next : std_logic_vector(0 to 31);
signal reg2, reg2_next : std_logic_vector(0 to 31);
signal reg3, reg3_next : std_logic_vector(0 to 31);
signal reg4, reg4_next : std_logic_vector(0 to 31);
signal reg5, reg5_next : std_logic_vector(0 to 31);
signal reg6, reg6_next : std_logic_vector(0 to 31);
signal reg7, reg7_next : std_logic_vector(0 to 31);
signal reg8, reg8_next : std_logic_vector(0 to 31);
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock, intrfc2thrd_goWait) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
return_state <= return_state_next;
retVal <= retVal_next;
arg <= arg_next;
reg1 <= reg1_next;
reg2 <= reg2_next;
reg3 <= reg3_next;
reg4 <= reg4_next;
reg5 <= reg5_next;
reg6 <= reg6_next;
reg7 <= reg7_next;
reg8 <= reg8_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_STATE_1 =>
current_state <= STATE_1;
when U_STATE_2 =>
current_state <= STATE_2;
when U_STATE_3 =>
current_state <= STATE_3;
when U_STATE_4 =>
current_state <= STATE_4;
when U_STATE_5 =>
current_state <= STATE_5;
when U_STATE_6 =>
current_state <= STATE_6;
when U_STATE_7 =>
current_state <= STATE_7;
when U_STATE_8 =>
current_state <= STATE_8;
when U_STATE_9 =>
current_state <= STATE_9;
when U_STATE_10 =>
current_state <= STATE_10;
when U_STATE_11 =>
current_state <= STATE_11;
when U_STATE_12 =>
current_state <= STATE_12;
when U_STATE_13 =>
current_state <= STATE_13;
when U_STATE_14 =>
current_state <= STATE_14;
when U_STATE_15 =>
current_state <= STATE_15;
when U_STATE_16 =>
current_state <= STATE_16;
when U_STATE_17 =>
current_state <= STATE_17;
when U_STATE_18 =>
current_state <= STATE_18;
when U_STATE_19 =>
current_state <= STATE_19;
when U_STATE_20 =>
current_state <= STATE_20;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
retVal_next <= retVal;
arg_next <= arg;
reg1_next <= reg1;
reg2_next <= reg2;
reg3_next <= reg3;
reg4_next <= reg4;
reg5_next <= reg5;
reg6_next <= reg6;
reg7_next <= reg7;
reg8_next <= reg8;
-----------------------------------------------------------------------
-- equal_2.c
-- FIRST_THREAD 5
-- SECOND_THREAD 7
-----------------------------------------------------------------------
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
-- if ( hthread_self( FIRST_THREAD, SECOND_THREAD ) == 0 ) retVal = SUCCESS;
-- else retVal = FAILURE;
when FUNCTION_START =>
-- Push FIRST_THREAD
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= x"00000005";
next_state <= WAIT_STATE;
return_state_next <= STATE_1;
when STATE_1 =>
-- Push SECOND_THREAD
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= x"00000007";
next_state <= WAIT_STATE;
return_state_next <= STATE_2;
when STATE_2 =>
-- Call hthread_equal
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_EQUAL;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_3;
next_state <= WAIT_STATE;
when STATE_3 =>
case intrfc2thrd_value is
when x"00000000" =>
retVal_next <= Z32;
when others =>
retVal_next <= x"00000001";
end case;
next_state <= FUNCTION_EXIT;
when FUNCTION_EXIT =>
--Same as hthread_exit( (void *) retVal );
thrd2intrfc_value <= retVal;
thrd2intrfc_opcode <= OPCODE_RETURN;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
|
bsd-3-clause
|
masson2013/heterogeneous_hthreads
|
src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/plbv46_opb_bridge_v1_01_a/hdl/vhdl/opb_master.vhd
|
3
|
22716
|
-------------------------------------------------------------------------------
-- $Id: opb_master.vhd,v 1.1.2.1 2008/12/19 20:58:34 mlovejoy Exp $
-------------------------------------------------------------------------------
-- opb_master.vhd - Version v1_0_a
-------------------------------------------------------------------------------
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2006, 2007, 2008 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
--
-- Filename: opb_master.vhd
-- Version: v1_01_a
-- Description:
--
-------------------------------------------------------------------------------
-- Structure:
--
-------------------------------------------------------------------------------
-- Author: <Tim Davis>
--
-- History:
--
-- TRD 9/8/2006
-- ~~~~~~
-- - Initial release of v1_00_a
-- ^^^^^^
-- MLL 8/28/2008
-- New version plbv46_opb_bridge_v1_01_a to include new
-- plbv46_slave_burst_v1_01_a and proc_common v3.00.a.
-- Also added coverage off/on for code coverage testing.
-- Removed Changelog and DISCLAIMER OF LIABILITY updated.
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
-- NOTES:
-- 1) The CE's from the IPIC are not used but included for consistency to make
-- it easier to connect things up. That unfortunately makes it necessary to
-- include the C_ARD_ADDR_RANGE_ARRAY and C_ARD_NUM_CE_ARRAY generics. **Maybe**
-- there is a chance these might be used in the future.
--
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
--use ieee.std_logic_misc.all;
LIBRARY proc_common_v3_00_a;
USE proc_common_v3_00_a.proc_common_pkg.ALL;
--use proc_common_v2_00_a.proc_common_pkg.log2;
--use proc_common_v2_00_a.proc_common_pkg.max2;
USE proc_common_v3_00_a.family.ALL;
USE proc_common_v3_00_a.ipif_pkg.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY plbv46_opb_bridge_v1_01_a;
USE plbv46_opb_bridge_v1_01_a.ALL;
-------------------------------------------------------------------------------
ENTITY opb_master IS
GENERIC (
-- Base address and high address pairs.
C_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
X"0000_0000_7000_0000", -- IP user0 base address
X"0000_0000_7000_00FF", -- IP user0 high address
X"0000_0000_7000_0100", -- IP user1 base address
X"0000_0000_7000_01FF" -- IP user1 high address
);
-- This array speifies the number of Chip Enables (CE) that is
-- required by the cooresponding baseaddr pair.
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
1, -- User0 CE Number
8 -- User1 CE Number
);
-- width of the PLB Address Bus (in bits)
C_SPLB_AWIDTH : integer RANGE 32 TO 36 := 32;
-- Width of IPIF (Hence IPIC) Data Bus (in bits). This parameter is kept
-- for consistency with the plbv46_slave_burst core but should always be
-- 32 to match the OPB data width.
C_SPLB_DWIDTH : integer RANGE 32 TO 128 := 128;
C_SIPIF_DWIDTH : integer RANGE 32 TO 32 := 32;
-- PLB:OPB clock period ratio. 1=1:1, 2=1:2
C_BUS_CLOCK_PERIOD_RATIO : integer RANGE 1 TO 2 := 1;
C_FAMILY : string := virtex4 -- Select the target architecture type
);
PORT (
-- IP Interconnect (IPIC) Interface from PLBv46 IPIF
Bus2IP_Clk : IN std_logic;
Bus2IP_Reset : IN std_logic;
IP2Bus_Data : OUT std_logic_vector(0 TO C_SIPIF_DWIDTH-1);
IP2Bus_WrAck : OUT std_logic;
IP2Bus_RdAck : OUT std_logic;
IP2Bus_AddrAck : OUT std_logic;
IP2Bus_Error : OUT std_logic;
Bus2IP_Addr : IN std_logic_vector(0 TO C_SPLB_AWIDTH-1);
Bus2IP_Data : IN std_logic_vector(0 TO C_SIPIF_DWIDTH-1);
Bus2IP_RNW : IN std_logic;
Bus2IP_BE : IN std_logic_vector(0 TO C_SIPIF_DWIDTH/8-1);
Bus2IP_Burst : IN std_logic;
Bus2IP_BurstLength : IN std_logic_vector(0 TO log2(16 * (C_SPLB_DWIDTH/8)));
Bus2IP_WrReq : IN std_logic;
Bus2IP_RdReq : IN std_logic;
Bus2IP_CS : IN std_logic_vector(0 TO ((C_ARD_ADDR_RANGE_ARRAY'length)/2)-1);
Bus2IP_RdCE : IN std_logic_vector(0 TO calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
Bus2IP_WrCE : IN std_logic_vector(0 TO calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
-- OPB Bus Master Interface
OPB_Clk : IN std_logic;
OPB_Rst : IN std_logic;
Mn_request : OUT std_logic;
Mn_busLock : OUT std_logic;
Mn_select : OUT std_logic;
Mn_RNW : OUT std_logic;
Mn_BE : OUT std_logic_vector(0 TO 32/8-1);
Mn_seqAddr : OUT std_logic;
Mn_DBus : OUT std_logic_vector(0 TO 32-1);
Mn_ABus : OUT std_logic_vector(0 TO 32-1);
OPB_MGrant : IN std_logic := '0';
OPB_xferAck : IN std_logic := '0';
OPB_errAck : IN std_logic := '0';
OPB_retry : IN std_logic := '0';
OPB_timeout : IN std_logic := '0';
OPB_DBus : IN std_logic_vector(0 TO 32 - 1)
);
END ENTITY opb_master;
ARCHITECTURE syn OF opb_master IS
CONSTANT prop_delay : time := 1 NS; -- For simulation clarity only
CONSTANT ce_all_zero : std_logic_vector(Bus2IP_WrCE'range) := (OTHERS => '0');
TYPE bridge_state_type IS (REQUEST, TRANSACT, WAIT_DESELECT, FORCEWT);
SIGNAL bridge_ns, bridge_cs : bridge_state_type;
SIGNAL Mn_select_ns, Mn_select_cs : std_logic;
SIGNAL Mn_busLock_ns, Mn_busLock_cs : std_logic;
SIGNAL Mn_seqAddr_ns, Mn_seqAddr_cs : std_logic;
SIGNAL Mn_RNW_ns, Mn_RNW_cs : std_logic;
SIGNAL Mn_BE_ns, Mn_BE_cs : std_logic_vector(0 TO 3);
SIGNAL IP2Bus_AddrAck_ns, IP2Bus_AddrAck_cs : std_logic;
SIGNAL IP2Bus_WrAck_ns, IP2Bus_WrAck_cs : std_logic;
SIGNAL IP2Bus_RdAck_ns, IP2Bus_RdAck_cs : std_logic;
SIGNAL IP2Bus_Error_ns, IP2Bus_Error_cs : std_logic;
SIGNAL ce_reduce : std_logic; -- 'OR' Reduce of the Bus2IP chip enables
SIGNAL bus2ip_select : std_logic; -- Indicates transaction req from bus
BEGIN
--coverage off
ASSERT (C_SPLB_AWIDTH = 32)
REPORT "The PLB Address Width does not equal 32 which is required by the OPB bus."
SEVERITY FAILURE;
--coverage on
-- The bridge reacts when one of the chip enables from the IPIC interface
-- asserts indicating a request to the bridge. For smallest amount of logic
-- there should only be one chip enable per (chip select) address region.
-- The s1, s2, and s3 signal assignments below use an OR-reduce operation on
-- the read and write IPIC chip enables to identify when the
-- plbv46_slave_burst is requesting access to the OPB bus. In the 1:2 clock
-- ratio case the select signal deassertion period needs to be stretched.
s1 : ce_reduce <= '0' AFTER prop_delay WHEN
Bus2IP_WrCE = ce_all_zero
AND Bus2IP_RdCE = ce_all_zero
ELSE
'1' AFTER prop_delay;
select_gen1 : IF (C_BUS_CLOCK_PERIOD_RATIO = 1) GENERATE
-- No pulse stretching is required in the 1:1 clock ratio case.
s2 : bus2ip_select <= ce_reduce;
END GENERATE select_gen1;
select_gen2 : IF (C_BUS_CLOCK_PERIOD_RATIO = 2) GENERATE
-- This process stretches the low going pulse of the ce_reduce to
-- ensure that it lasts for two Bus2IP_clk periods which equals one
-- OPB_CLK period. That way the state machine can see the
-- deassertion of the IPIC interface request.
PROCESS (Bus2IP_Clk, ce_reduce) IS
VARIABLE ce_reduce_dly1 : std_logic;
BEGIN
s3 : bus2ip_select <= ce_reduce AND ce_reduce_dly1;
IF (rising_edge(Bus2IP_Clk)) THEN
ce_reduce_dly1 := ce_reduce;
END IF;
END PROCESS;
END GENERATE select_gen2;
--
-- The state machine connects the two protocols -- opb and ipic
--
bfsm : PROCESS (Bus2IP_BE, Bus2IP_Burst, Bus2IP_RNW, IP2Bus_AddrAck_cs,
IP2Bus_Error_cs, IP2Bus_RdAck_cs, IP2Bus_WrAck_cs, Mn_BE_cs,
Mn_RNW_cs, Mn_busLock_cs, Mn_select_cs,
Mn_seqAddr_cs, OPB_MGrant, OPB_errAck, OPB_retry,
OPB_timeout, OPB_xferAck, bridge_cs, bus2ip_select) IS
-- Combinatorial Next state and output decoding
BEGIN
-- Default to holding current state of all outputs
bridge_ns <= bridge_cs AFTER prop_delay;
Mn_select_ns <= Mn_select_cs AFTER prop_delay;
Mn_busLock_ns <= Mn_busLock_cs AFTER prop_delay;
Mn_seqAddr_ns <= Mn_seqAddr_cs AFTER prop_delay;
Mn_RNW_ns <= Mn_RNW_cs AFTER prop_delay;
Mn_BE_ns <= Mn_BE_cs AFTER prop_delay;
IP2Bus_AddrAck_ns <= IP2Bus_AddrAck_cs AFTER prop_delay;
IP2Bus_WrAck_ns <= IP2Bus_WrAck_cs AFTER prop_delay;
IP2Bus_RdAck_ns <= IP2Bus_RdAck_cs AFTER prop_delay;
IP2Bus_Error_ns <= IP2Bus_Error_cs AFTER prop_delay;
CASE bridge_cs IS
WHEN REQUEST =>
IP2Bus_Error_ns <= '0' AFTER prop_delay;
IP2Bus_AddrAck_ns <= '0' AFTER prop_delay;
IP2Bus_WrAck_ns <= '0' AFTER prop_delay;
IP2BUS_RdAck_ns <= '0' AFTER prop_delay;
-- Waiting for a request from the PLBv46 IPIF
-- (plbv46_slave_burst_v1_01_a) via Chip enable assertion
IF (OPB_MGrant = '1') THEN
-- Because Mn_request is combinatorially dependent on
-- bus2ip_select='1' already it would seem that the following if
-- condition is redundant. This is true except when bus parking
-- is activated in which case the OPB_MGrant can assert without
-- Mn_request ever asserting. DONT'T REMOVE THIS CONDITION!
-- (OPB Arbiter bus parking on this Master permits a faster
-- response by pre-issuing the grant prior to a request. Note
-- that the request never has to be asserted. I'm assuming it
-- can be without harm.)
IF (bus2ip_select = '1') THEN
bridge_ns <= TRANSACT AFTER prop_delay;
Mn_select_ns <= '1' AFTER prop_delay;
Mn_busLock_ns <= Bus2IP_Burst AFTER prop_delay;
Mn_seqAddr_ns <= Bus2IP_Burst AFTER prop_delay;
Mn_RNW_ns <= Bus2IP_RNW AFTER prop_delay;
Mn_BE_ns <= Bus2IP_BE AFTER prop_delay;
END IF;
END IF;
WHEN TRANSACT =>
IP2Bus_AddrAck_ns <= OPB_xferAck AND NOT OPB_retry AFTER prop_delay;
IP2Bus_WrAck_ns <= OPB_xferAck AND NOT Bus2IP_RNW AFTER prop_delay;
IP2BUS_RdAck_ns <= OPB_xferAck AND Bus2IP_RNW AFTER prop_delay;
IP2BUS_Error_ns <= (OPB_xferAck AND OPB_errAck)
OR (OPB_timeout AND NOT OPB_xferAck) AFTER prop_delay;
IF (bus2ip_select = '1') THEN
IF (OPB_retry = '1') THEN
-- IPIF still wants to get it's request satisfied but the SM
-- must go back to re-request the OPB bus again. Retry and
-- xferAck are mutually exclusive so the IPIF won't be ack'd
-- on retry. The slave can retry indefinately. (Note: This
-- should be fixed eventually via a retry timeout counter.)
bridge_ns <= FORCEWT AFTER prop_delay;
Mn_seqAddr_ns <= '0' AFTER prop_delay;
Mn_busLock_ns <= '0' AFTER prop_delay;
Mn_RNW_ns <= '0' AFTER prop_delay;
mn_BE_ns <= (OTHERS => '0') AFTER prop_delay;
Mn_select_ns <= '0' AFTER prop_delay;
ELSIF (OPB_xferAck) = '1' THEN
IF(NOT Bus2IP_Burst) = '1' THEN
-- End of transaction from IPIF
bridge_ns <= WAIT_DESELECT AFTER prop_delay;
Mn_seqAddr_ns <= '0' AFTER prop_delay;
Mn_busLock_ns <= '0' AFTER prop_delay;
Mn_RNW_ns <= '0' AFTER prop_delay;
mn_BE_ns <= (OTHERS => '0') AFTER prop_delay;
Mn_select_ns <= '0' AFTER prop_delay;
END IF;
ELSIF OPB_timeout = '1' THEN
-- OPB_xferAck takes precedence over OPB_timeout
bridge_ns <= WAIT_DESELECT AFTER prop_delay;
Mn_seqAddr_ns <= '0' AFTER prop_delay;
Mn_busLock_ns <= '0' AFTER prop_delay;
Mn_RNW_ns <= '0' AFTER prop_delay;
mn_BE_ns <= (OTHERS => '0') AFTER prop_delay;
Mn_select_ns <= '0' AFTER prop_delay;
END IF;
ELSE
-- This represents an OPB "Master Abort"
bridge_ns <= REQUEST AFTER prop_delay;
-- Must deassert bus lock here in case of abnormal termination
Mn_seqAddr_ns <= '0' AFTER prop_delay;
Mn_busLock_ns <= '0' AFTER prop_delay;
Mn_RNW_ns <= '0' AFTER prop_delay;
mn_BE_ns <= (OTHERS => '0') AFTER prop_delay;
Mn_select_ns <= '0' AFTER prop_delay;
END IF;
WHEN WAIT_DESELECT =>
-- The plbv46_burst_slave_v1_00_a pipelines its Bus2IP chip
-- selects. They won't disappear until the *ack is sampled
-- high at the next rising edge. This state checks that it IS
-- deasserted. Otherwise, the state machine will recognize a NEW
-- transaction immediately after the first one completes.
IP2Bus_AddrAck_ns <= '0' AFTER prop_delay;
IP2Bus_WrAck_ns <= '0' AFTER prop_delay;
IP2BUS_RdAck_ns <= '0' AFTER prop_delay;
IP2BUS_Error_ns <= '0' AFTER prop_delay;
bridge_ns <= REQUEST AFTER prop_delay;
WHEN FORCEWT =>
-- After a retry the master is required to stay off the bus for one
-- clock.
bridge_ns <= REQUEST AFTER prop_delay;
--coverage off
WHEN OTHERS => NULL;
--coverage on
END CASE;
END PROCESS bfsm;
state : PROCESS (OPB_Clk, OPB_Rst) IS
-- State Machine state register
BEGIN
IF (OPB_Rst = '1') THEN
bridge_cs <= REQUEST AFTER prop_delay;
ELSIF (rising_edge(OPB_Clk)) THEN
bridge_cs <= bridge_ns AFTER prop_delay;
END IF;
END PROCESS state;
oreg : PROCESS (OPB_Clk, OPB_Rst) IS
-- State Machine output registers
BEGIN
IF (OPB_Rst = '1') THEN
Mn_select_cs <= '0' AFTER prop_delay;
Mn_busLock_cs <= '0' AFTER prop_delay;
Mn_seqAddr_cs <= '0' AFTER prop_delay;
Mn_RNW_cs <= '0' AFTER prop_delay;
Mn_BE_cs <= (OTHERS => '0') AFTER prop_delay;
IP2Bus_AddrAck_cs <= '0' AFTER prop_delay;
IP2Bus_WrAck_cs <= '0' AFTER prop_delay;
IP2Bus_RdAck_cs <= '0' AFTER prop_delay;
IP2Bus_Error_cs <= '0' AFTER prop_delay;
ELSIF (rising_edge(OPB_Clk)) THEN
Mn_select_cs <= Mn_select_ns AFTER prop_delay;
Mn_busLock_cs <= Mn_busLock_ns AFTER prop_delay;
Mn_seqAddr_cs <= Mn_seqAddr_ns AFTER prop_delay;
Mn_RNW_cs <= Mn_RNW_ns AFTER prop_delay;
Mn_BE_cs <= Mn_BE_ns AFTER prop_delay;
IP2Bus_AddrAck_cs <= IP2Bus_AddrAck_ns AFTER prop_delay;
IP2Bus_WrAck_cs <= IP2Bus_WrAck_ns AFTER prop_delay;
IP2Bus_RdAck_cs <= IP2Bus_RdAck_ns AFTER prop_delay;
IP2Bus_Error_cs <= IP2Bus_Error_ns AFTER prop_delay;
END IF;
END PROCESS oreg;
apath : PROCESS (Bus2IP_Addr(0 TO 31), Mn_select_cs) IS
-- Master address bus registers
BEGIN
IF Mn_select_cs = '0' THEN
-- The Master's ABus is or'd externally with the other Master ABus'.
-- The master must not drive its ABus unless it is selected.
Mn_ABus <= (OTHERS => '0');
ELSE
-- PLBv46 spec, pg 32, sect 2.5.1.1, "For non-line transfers, this
-- 32-bit bus indicates the lowest numbered byte address of the target
-- data to be read/written over the PLB."
Mn_ABus <= Bus2IP_Addr(0 TO 31);
END IF;
END PROCESS apath;
mn_dpath : PROCESS (Bus2IP_Data(0 TO 31), Bus2IP_RNW, Mn_select_cs) IS
-- Master data bus registers
BEGIN
IF (NOT Mn_select_cs OR Bus2IP_RNW) = '1' THEN
-- The Master's DBus is or'd externally with the slave's bus. On Reads
-- the master must not be driving anything or the data on the OPB_DBus
-- will be corrupted. It must not drive anything on writes if not
-- selected either.
Mn_DBus <= (OTHERS => '0');
ELSE
Mn_DBus <= Bus2IP_Data(0 TO 31);
END IF;
END PROCESS mn_dpath;
s2 : IP2Bus_Data(0 TO 31) <= OPB_DBus AFTER prop_delay;
clkratio1to1 : IF (C_BUS_CLOCK_PERIOD_RATIO = 1) GENERATE
-- Does the opb_master only see acks when its select is asserted? Or does it
-- see every device's ack? IE Does it need to qualify the acks w/ select?
s3 : IP2Bus_AddrAck <= IP2Bus_AddrAck_ns;
s4 : IP2Bus_WrAck <= IP2Bus_WrAck_ns;
s5 : IP2Bus_RdAck <= IP2Bus_RdAck_ns;
s6 : IP2Bus_Error <= IP2Bus_Error_ns;
END GENERATE clkratio1to1;
clkratio1to2 : IF (C_BUS_CLOCK_PERIOD_RATIO = 2) GENERATE
--
-- To jump the clock domain boundary the longer (OPB_Clk period) acks are
-- translated to a single pulse in the (PLB_Clk period) domain. Note that
-- the OPB_CLK is "data" with respect to the BUS2IP_CLK (plb clock) even
-- though both are presumably generated from the same DLL.
--
-- __ __ __
-- BUS2IP_Clk __/ \__/ \__/ \__/
-- _____ _____
-- OPB_Clk __/ \_____/ \
-- ___________
-- IP2Bus_AddrAck_ns ___/ \______
-- _____
-- IP2Bus_AddrAck _________/ \______
--
s3 : IP2Bus_AddrAck <= IP2Bus_AddrAck_ns AND NOT OPB_CLK;
s4 : IP2Bus_WrAck <= IP2Bus_WrAck_ns AND NOT OPB_CLK;
s5 : IP2Bus_RdAck <= IP2Bus_RdAck_ns AND NOT OPB_CLK;
s6 : IP2Bus_Error <= IP2Bus_Error_ns AND NOT OPB_CLK;
END GENERATE clkratio1to2;
s10 : Mn_request <= '1' AFTER prop_delay WHEN bus2ip_select = '1' AND bridge_cs = REQUEST ELSE
'0' AFTER prop_delay; -- The request has to drop synchronously
-- in case the grant is simply the
-- request fed back asynchronously.
s11 : Mn_select <= Mn_select_cs;
s12 : Mn_busLock <= Mn_busLock_cs;
s13 : Mn_seqAddr <= Mn_seqAddr_cs;
s14 : Mn_RNW <= Mn_RNW_cs;
s15 : Mn_BE <= Mn_BE_cs;
END ARCHITECTURE syn;
|
bsd-3-clause
|
masson2013/heterogeneous_hthreads
|
src/platforms/xilinx/smp3_opbhwti/design/pcores/opb_v20_v1_10_d/hdl/vhdl/pf_adder_bit.vhd
|
3
|
10202
|
-------------------------------------------------------------------------------
-- $Id: pf_adder_bit.vhd,v 1.1.2.1 2009/10/06 21:15:01 gburch Exp $
-------------------------------------------------------------------------------
-- pf_adder_bit.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pf_adder_bit.vhd
--
-- Description: Implements 1 bit of the pf_adder
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pf_adder_bit.vhd
--
-------------------------------------------------------------------------------
-- Author: D. Thorpe
-- Revision: $Revision: 1.1.2.1 $
-- Date: $Date: 2009/10/06 21:15:01 $
--
-- History:
-- D. Thorpe 2001-08-30 First Version
-- - adapted from B Tise MicroBlaze counters
--
-- DET 2001-09-11
-- - Added the Rst input signal and connected it to the FDRE
-- reset input.
--
-- DET 2001-09-25
-- - Added generic to allow selection of a registered output
--
-- DET 2002-02-24
-- - Changed to call out proc_common_v1_00_b library.
-- - CHanged the use of MUXCY_L to MUXCY.
--
--
-- DET 3/25/2004 ipif to v1_00_f
-- ~~~~~~
-- - Changed to call out proc_common_v2_00_a library.
-- ^^^^^^
--
--
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
library opb_v20_v1_10_d;
Use opb_v20_v1_10_d.inferred_lut4;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity pf_adder_bit is
generic (
C_REGISTERED_RESULT : Boolean := true
);
port (
Clk : in std_logic;
Rst : In std_logic;
Ain : in std_logic; -- A operand
Bin : in std_logic; -- B operand
Add_sub_n : in std_logic; -- Function ('1' = add, '0' = A - B)
Carry_In : in std_logic;
Clock_Enable : in std_logic;
Result : out std_logic;
Carry_Out : out std_logic
);
end pf_adder_bit;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of pf_adder_bit is
--- xst wrk around component LUT4 is
--- xst wrk around generic(
--- xst wrk around -- synthesis translate_off
--- xst wrk around Xon : boolean;
--- xst wrk around -- synthesis translate_on
--- xst wrk around INIT : bit_vector := X"0000"
--- xst wrk around );
--- xst wrk around port (
--- xst wrk around O : out std_logic;
--- xst wrk around I0 : in std_logic;
--- xst wrk around I1 : in std_logic;
--- xst wrk around I2 : in std_logic;
--- xst wrk around I3 : in std_logic);
--- xst wrk around end component LUT4;
signal lutout_AddSub : std_logic;
signal addsub_result : std_logic;
signal addsub_result_Reg : std_logic;
attribute INIT : string;
begin -- VHDL_RTL
--- xst wrk around I_ALU_LUT : LUT4
--- xst wrk around generic map(
--- xst wrk around -- synthesis translate_off
--- xst wrk around Xon => false,
--- xst wrk around -- synthesis translate_on
--- xst wrk around INIT => X"0069"
--- xst wrk around )
--- xst wrk around port map (
--- xst wrk around O => lutout_AddSub,
--- xst wrk around I0 => Bin,
--- xst wrk around I1 => Ain,
--- xst wrk around I2 => Add_sub_n,
--- xst wrk around I3 => '0');
I_ALU_LUT : entity opb_v20_v1_10_d.inferred_lut4
generic map(
INIT => X"0069"
)
port map (
O => lutout_AddSub,
I0 => Bin,
I1 => Ain,
I2 => Add_sub_n,
I3 => '0');
MUXCY_I : MUXCY
port map (
DI => Ain,
CI => Carry_In,
S => lutout_AddSub,
O => Carry_Out);
XOR_I : XORCY
port map (
LI => lutout_AddSub,
CI => Carry_In,
O => addsub_result);
FDRE_I: FDRE
port map (
Q => addsub_result_Reg,
C => Clk,
CE => Clock_Enable,
D => addsub_result,
R => Rst
);
USE_REGISTERED_RESULT : if (C_REGISTERED_RESULT = true) generate
Result <= addsub_result_Reg; -- registered version
end generate USE_REGISTERED_RESULT;
USE_COMBINATIONAL_RESULT : if (C_REGISTERED_RESULT = false) generate
Result <= addsub_result; -- combinational version
end generate USE_COMBINATIONAL_RESULT;
end implementation;
|
bsd-3-clause
|
masson2013/heterogeneous_hthreads
|
src/hardware/MyRepository/pcores/hw_threads/hw_acc_v1_00_a/hdl/vhdl/user_logics/functional/equal_1.vhd
|
2
|
15082
|
---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
FUNCTION_EXIT,
STATE_1,
STATE_2,
STATE_3,
STATE_4,
STATE_5,
STATE_6,
STATE_7,
STATE_8,
STATE_9,
STATE_10,
STATE_11,
STATE_12,
STATE_13,
STATE_14,
STATE_15,
STATE_16,
STATE_17,
STATE_18,
STATE_19,
STATE_20,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_STATE_1 : std_logic_vector(0 to 15) := x"0101";
constant U_STATE_2 : std_logic_vector(0 to 15) := x"0102";
constant U_STATE_3 : std_logic_vector(0 to 15) := x"0103";
constant U_STATE_4 : std_logic_vector(0 to 15) := x"0104";
constant U_STATE_5 : std_logic_vector(0 to 15) := x"0105";
constant U_STATE_6 : std_logic_vector(0 to 15) := x"0106";
constant U_STATE_7 : std_logic_vector(0 to 15) := x"0107";
constant U_STATE_8 : std_logic_vector(0 to 15) := x"0108";
constant U_STATE_9 : std_logic_vector(0 to 15) := x"0109";
constant U_STATE_10 : std_logic_vector(0 to 15) := x"0110";
constant U_STATE_11 : std_logic_vector(0 to 15) := x"0111";
constant U_STATE_12 : std_logic_vector(0 to 15) := x"0112";
constant U_STATE_13 : std_logic_vector(0 to 15) := x"0113";
constant U_STATE_14 : std_logic_vector(0 to 15) := x"0114";
constant U_STATE_15 : std_logic_vector(0 to 15) := x"0115";
constant U_STATE_16 : std_logic_vector(0 to 15) := x"0116";
constant U_STATE_17 : std_logic_vector(0 to 15) := x"0117";
constant U_STATE_18 : std_logic_vector(0 to 15) := x"0118";
constant U_STATE_19 : std_logic_vector(0 to 15) := x"0119";
constant U_STATE_20 : std_logic_vector(0 to 15) := x"0120";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
signal retVal, retVal_next : std_logic_vector(0 to 31);
signal arg, arg_next : std_logic_vector(0 to 31);
signal reg1, reg1_next : std_logic_vector(0 to 31);
signal reg2, reg2_next : std_logic_vector(0 to 31);
signal reg3, reg3_next : std_logic_vector(0 to 31);
signal reg4, reg4_next : std_logic_vector(0 to 31);
signal reg5, reg5_next : std_logic_vector(0 to 31);
signal reg6, reg6_next : std_logic_vector(0 to 31);
signal reg7, reg7_next : std_logic_vector(0 to 31);
signal reg8, reg8_next : std_logic_vector(0 to 31);
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock, intrfc2thrd_goWait) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
return_state <= return_state_next;
retVal <= retVal_next;
arg <= arg_next;
reg1 <= reg1_next;
reg2 <= reg2_next;
reg3 <= reg3_next;
reg4 <= reg4_next;
reg5 <= reg5_next;
reg6 <= reg6_next;
reg7 <= reg7_next;
reg8 <= reg8_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_STATE_1 =>
current_state <= STATE_1;
when U_STATE_2 =>
current_state <= STATE_2;
when U_STATE_3 =>
current_state <= STATE_3;
when U_STATE_4 =>
current_state <= STATE_4;
when U_STATE_5 =>
current_state <= STATE_5;
when U_STATE_6 =>
current_state <= STATE_6;
when U_STATE_7 =>
current_state <= STATE_7;
when U_STATE_8 =>
current_state <= STATE_8;
when U_STATE_9 =>
current_state <= STATE_9;
when U_STATE_10 =>
current_state <= STATE_10;
when U_STATE_11 =>
current_state <= STATE_11;
when U_STATE_12 =>
current_state <= STATE_12;
when U_STATE_13 =>
current_state <= STATE_13;
when U_STATE_14 =>
current_state <= STATE_14;
when U_STATE_15 =>
current_state <= STATE_15;
when U_STATE_16 =>
current_state <= STATE_16;
when U_STATE_17 =>
current_state <= STATE_17;
when U_STATE_18 =>
current_state <= STATE_18;
when U_STATE_19 =>
current_state <= STATE_19;
when U_STATE_20 =>
current_state <= STATE_20;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
retVal_next <= retVal;
arg_next <= arg;
reg1_next <= reg1;
reg2_next <= reg2;
reg3_next <= reg3;
reg4_next <= reg4;
reg5_next <= reg5;
reg6_next <= reg6;
reg7_next <= reg7;
reg8_next <= reg8;
-----------------------------------------------------------------------
-- equal_1.c
-- FIRST_THREAD 5
-- SECOND_THREAD 5
-----------------------------------------------------------------------
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
-- if ( hthread_self( FIRST_THREAD, SECOND_THREAD ) != 0 ) retVal = SUCCESS;
-- else retVal = FAILURE;
when FUNCTION_START =>
-- Push FIRST_THREAD
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= x"00000005";
next_state <= WAIT_STATE;
return_state_next <= STATE_1;
when STATE_1 =>
-- Push SECOND_THREAD
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= x"00000005";
next_state <= WAIT_STATE;
return_state_next <= STATE_2;
when STATE_2 =>
-- Call hthread_equal
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_EQUAL;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_3;
next_state <= WAIT_STATE;
when STATE_3 =>
case intrfc2thrd_value is
when x"00000000" =>
retVal_next <= x"00000001";
when others =>
retVal_next <= Z32;
end case;
next_state <= FUNCTION_EXIT;
when FUNCTION_EXIT =>
--Same as hthread_exit( (void *) retVal );
thrd2intrfc_value <= retVal;
thrd2intrfc_opcode <= OPCODE_RETURN;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
|
bsd-3-clause
|
masson2013/heterogeneous_hthreads
|
src/platforms/xilinx/smp1/design/pcores/plb_scheduler_v1_00_a/hdl/vhdl/user_logic.vhd
|
10
|
89379
|
------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: user_logic.vhd
-- Version: 1.00.a
-- Description: User logic.
-- Date: Mon Apr 6 14:20:46 2009 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.srl_fifo_f;
-- DO NOT EDIT ABOVE THIS LINE --------------------
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_SLV_DWIDTH -- Slave interface data bus width
-- C_MST_AWIDTH -- Master interface address bus width
-- C_MST_DWIDTH -- Master interface data bus width
-- C_NUM_REG -- Number of software accessible registers
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Reset -- Bus to IP reset
-- Bus2IP_Addr -- Bus to IP address bus
-- Bus2IP_Data -- Bus to IP data bus
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- IP2Bus_Data -- IP to Bus data bus
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- IP2Bus_Error -- IP to Bus error response
-- IP2Bus_MstRd_Req -- IP to Bus master read request
-- IP2Bus_MstWr_Req -- IP to Bus master write request
-- IP2Bus_Mst_Addr -- IP to Bus master address bus
-- IP2Bus_Mst_BE -- IP to Bus master byte enables
-- IP2Bus_Mst_Lock -- IP to Bus master lock
-- IP2Bus_Mst_Reset -- IP to Bus master reset
-- Bus2IP_Mst_CmdAck -- Bus to IP master command acknowledgement
-- Bus2IP_Mst_Cmplt -- Bus to IP master transfer completion
-- Bus2IP_Mst_Error -- Bus to IP master error response
-- Bus2IP_Mst_Rearbitrate -- Bus to IP master re-arbitrate
-- Bus2IP_Mst_Cmd_Timeout -- Bus to IP master command timeout
-- Bus2IP_MstRd_d -- Bus to IP master read data bus
-- Bus2IP_MstRd_src_rdy_n -- Bus to IP master read source ready
-- IP2Bus_MstWr_d -- IP to Bus master write data bus
-- Bus2IP_MstWr_dst_rdy_n -- Bus to IP master write destination ready
------------------------------------------------------------------------------
entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_SLV_DWIDTH : integer := 32;
C_MST_AWIDTH : integer := 32;
C_MST_DWIDTH : integer := 32;
C_NUM_REG : integer := 5
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
Soft_Reset : in std_logic;
Reset_Done : out std_logic;
Soft_Stop : in std_logic;
SWTM_DOB : in std_logic_vector(0 to 31);
SWTM_ADDRB : out std_logic_vector(0 to 8);
SWTM_DIB : out std_logic_vector(0 to 31);
SWTM_ENB : out std_logic;
SWTM_WEB : out std_logic;
TM2SCH_current_cpu_tid : in std_logic_vector(0 to 7);
TM2SCH_opcode : in std_logic_vector(0 to 5);
TM2SCH_data : in std_logic_vector(0 to 7);
TM2SCH_request : in std_logic;
SCH2TM_busy : out std_logic;
SCH2TM_data : out std_logic_vector(0 to 7);
SCH2TM_next_cpu_tid : out std_logic_vector(0 to 7);
SCH2TM_next_tid_valid : out std_logic;
Preemption_Interrupt : out std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Addr : in std_logic_vector(0 to 31);
Bus2IP_Data : in std_logic_vector(0 to C_SLV_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_SLV_DWIDTH/8-1);
Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_REG-1);
Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_REG-1);
IP2Bus_Data : out std_logic_vector(0 to C_SLV_DWIDTH-1);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic;
IP2Bus_MstRd_Req : out std_logic;
IP2Bus_MstWr_Req : out std_logic;
IP2Bus_Mst_Addr : out std_logic_vector(0 to C_MST_AWIDTH-1);
IP2Bus_Mst_BE : out std_logic_vector(0 to C_MST_DWIDTH/8-1);
IP2Bus_Mst_Lock : out std_logic;
IP2Bus_Mst_Reset : out std_logic;
Bus2IP_Mst_CmdAck : in std_logic;
Bus2IP_Mst_Cmplt : in std_logic;
Bus2IP_Mst_Error : in std_logic;
Bus2IP_Mst_Rearbitrate : in std_logic;
Bus2IP_Mst_Cmd_Timeout : in std_logic;
Bus2IP_MstRd_d : in std_logic_vector(0 to C_MST_DWIDTH-1);
Bus2IP_MstRd_src_rdy_n : in std_logic;
IP2Bus_MstWr_d : out std_logic_vector(0 to C_MST_DWIDTH-1);
Bus2IP_MstWr_dst_rdy_n : in std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk : signal is "CLK";
attribute SIGIS of Bus2IP_Reset : signal is "RST";
attribute SIGIS of IP2Bus_Mst_Reset: signal is "RST";
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
--USER signal declarations added here, as needed for user logic
-- Define the memory map for each command register, Address[24 to 31]
-- This value is the offset from the base address assigned to this module
constant C_TOGGLE_PREEMPTION : std_logic_vector(0 to 7) := "01001000"; -- 0x48
constant C_SET_DEFAULT_PRIORITY : std_logic_vector(0 to 7) := "01001100"; -- 0x4C
constant C_GET_IDLE_THREAD : std_logic_vector(0 to 7) := "01010000"; -- 0x50
constant C_SET_IDLE_THREAD : std_logic_vector(0 to 7) := "01010100"; -- 0x54
constant C_GET_ENCODER_OUTPUT : std_logic_vector(0 to 7) := "01011000"; -- 0x58
constant C_SET_SCHEDPARAM : std_logic_vector(0 to 7) := "01011100"; -- 0x5C
constant C_GET_ENTRY : std_logic_vector(0 to 7) := "01100000"; -- 0x60
constant C_GET_SCHEDPARAM : std_logic_vector(0 to 7) := "01100100"; -- 0x64
constant C_CHECK_SCHEDPARAM : std_logic_vector(0 to 7) := "01101000"; -- 0x68
constant C_MALLOC_LOCK : std_logic_vector(0 to 7) := "01000100"; -- 0x44
-- TM Command Opcodes
constant ENQUEUE_OPCODE : std_logic_vector(0 to 5) := "000010";
constant DEQUEUE_OPCODE : std_logic_vector(0 to 5) := "000011";
constant IS_QUEUED_OPCODE : std_logic_vector(0 to 5) := "000001";
constant IS_EMPTY_OPCODE : std_logic_vector(0 to 5) := "000110";
-- HW Thread Opcodes
constant HW_THREAD_START : std_logic_vector(0 to 3) := "0001";
-- Initialization Strings & Constants
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
constant BRAM_init_string : std_logic_vector(0 to 31) := Z32(0 to 31);
-- Busy Signals
signal Next_Thread_Valid_reg : std_logic;
signal Next_Thread_Valid_next : std_logic;
signal sched_busy : std_logic;
signal sched_busy_next : std_logic;
-- ACK signal
signal IP2Bus_Ack : std_logic;
-- Reset Signals
signal reset_addr : std_logic_vector(0 to 8);
-- CE concatenation signals
signal Bus2IP_RdCE_concat : std_logic;
signal Bus2IP_WrCE_concat : std_logic;
-- TM Output Controller signals
signal TM_data_ready : std_logic;
signal TM_data_out : std_logic_vector (0 to 7);
-- Bus Output Controller signals
signal bus_data_ready : std_logic;
signal bus_ack_ready : std_logic;
signal bus_data_out : std_logic_vector (0 to 31);
-- Interrupt Signals
signal Preemption_Interrupt_Line : std_logic;
signal Preemption_Interrupt_Enable : std_logic;
signal Preemption_Interrupt_Enable_next : std_logic;
-- Thread ID registers
signal TM2SCH_current_cpu_tid_reg : std_logic_vector(0 to 7);
signal next_thread_id_reg : std_logic_vector(0 to 7);
signal next_thread_id_next : std_logic_vector(0 to 7);
-- TM <--> SCH Debug Register
signal debug_reg : std_logic_vector(0 to 31);
signal debug_reg_next : std_logic_vector(0 to 31);
-- Reset Signals
-- FIXME: It would be nice to eliminate the default values here
signal inside_reset : std_logic := '0';
signal inside_reset_next : std_logic := '0';
-- Signals for each event type
signal Enqueue_Request : std_logic;
signal Dequeue_Request : std_logic;
signal Is_Queued_Request : std_logic;
signal Is_Empty_Request : std_logic;
signal Get_EncoderOutput_Request : std_logic;
signal Set_SchedParam_Request : std_logic;
signal Get_SchedParam_Request : std_logic;
signal Check_SchedParam_Request : std_logic;
signal Toggle_Preemption_Request : std_logic;
signal Get_IdleThread_Request : std_logic;
signal Set_IdleThread_Request : std_logic;
signal Get_Entry_Request : std_logic;
signal Default_Priority_Request : std_logic;
signal Error_Request : std_logic;
signal MALLOC_Lock_Request : std_logic;
-- State Machine data signals
signal lookup_entry : std_logic_vector(0 to 31);
signal lookup_entry_next : std_logic_vector(0 to 31);
signal dequeue_entry : std_logic_vector(0 to 31);
signal dequeue_entry_next : std_logic_vector(0 to 31);
signal enqueue_entry : std_logic_vector(0 to 31);
signal enqueue_entry_next : std_logic_vector(0 to 31);
signal enqueue_pri_entry : std_logic_vector(0 to 31);
signal enqueue_pri_entry_next : std_logic_vector(0 to 31);
signal deq_pri_entry : std_logic_vector(0 to 31);
signal deq_pri_entry_next : std_logic_vector(0 to 31);
signal sched_param : std_logic_vector(0 to 31);
signal sched_param_next : std_logic_vector(0 to 31);
signal old_tail_ptr : std_logic_vector(0 to 7);
signal old_tail_ptr_next : std_logic_vector(0 to 7);
signal current_entry_pri_value : std_logic_vector(0 to 6);
signal current_entry_pri_value_next : std_logic_vector(0 to 6);
signal old_priority : std_logic_vector(0 to 6);
signal old_priority_next : std_logic_vector(0 to 6);
signal new_priority : std_logic_vector(0 to 6);
signal new_priority_next : std_logic_vector(0 to 6);
signal lookup_id : std_logic_vector(0 to 7);
signal lookup_id_next : std_logic_vector(0 to 7);
signal idle_thread_id : std_logic_vector(0 to 7);
signal idle_thread_id_next : std_logic_vector(0 to 7);
signal idle_thread_valid : std_logic;
signal idle_thread_valid_next : std_logic;
signal temp_valid : std_logic;
signal temp_valid_next : std_logic;
-- BRAM Constants
constant BRAM_ADDRESS_BITS : integer := 9;
constant BRAM_DATA_BITS : integer := 32;
-- BRAM signals (THREAD_DATA)
signal DOA : std_logic_vector(0 to BRAM_DATA_BITS - 1) := (others => '0');
signal ADDRA : std_logic_vector(0 to BRAM_ADDRESS_BITS - 1) := (others => '0');
signal DIA : std_logic_vector(0 to BRAM_DATA_BITS - 1) := (others => '0');
signal ENA : std_logic := '0';
signal WEA : std_logic := '0';
-- BRAM signals (PRIORITY_DATA)
signal DOB : std_logic_vector(0 to BRAM_DATA_BITS - 1) := (others => '0');
signal ADDRB : std_logic_vector(0 to BRAM_ADDRESS_BITS - 1) := (others => '0');
signal DIB : std_logic_vector(0 to BRAM_DATA_BITS - 1) := (others => '0');
signal ENB : std_logic := '0';
signal WEB : std_logic := '0';
-- BRAM signals (PARAM_DATA)
signal DOU : std_logic_vector(0 to BRAM_DATA_BITS - 1) := (others => '0');
signal ADDRU : std_logic_vector(0 to BRAM_ADDRESS_BITS - 1) := (others => '0');
signal DIU : std_logic_vector(0 to BRAM_DATA_BITS - 1) := (others => '0');
signal ENU : std_logic := '0';
signal WEU : std_logic := '0';
-- Priority Encoder Constants & Signals
constant INPUT_BITS : integer := 128;
constant OUTPUT_BITS : integer := 7;
constant CHUNK_BITS : integer := 32;
signal encoder_reset : std_logic;
signal encoder_input : std_logic_vector(0 to INPUT_BITS - 1);
signal encoder_input_next : std_logic_vector(0 to INPUT_BITS - 1);
signal encoder_output : std_logic_vector(0 to OUTPUT_BITS - 1);
signal encoder_enable_next : std_logic;
signal encoder_enable : std_logic;
-- Lock/Mutex signals
signal lock_op : std_logic;
signal lock_op_next : std_logic;
signal lock_count : std_logic_vector(0 to 3);
signal lock_count_next : std_logic_vector(0 to 3);
signal malloc_mutex : std_logic;
signal malloc_mutex_next : std_logic;
signal malloc_mutex_holder : std_logic_vector(0 to 7);
signal malloc_mutex_holder_next : std_logic_vector(0 to 7);
-- signal and type for MASTER FSM
type master_state_type is
(
idle, -- idle states
wait_trans_done, -- wait for bus transaction to complete
reset, -- reset states
reset_BRAM,
reset_wait_4_ack,
GET_encoder_output, -- get_encoder_output state
SET_SCHED_PARAM_begin, -- set_sched_param states
SET_SCHED_PARAM_lookup_setpri_entries_begin,
SET_SCHED_PARAM_lookup_setpri_entries_idle,
SET_SCHED_PARAM_lookup_setpri_entries_finished,
SET_SCHED_PARAM_lookup_old_pri_entry_idle,
SET_SCHED_PARAM_lookup_old_pri_entry_finished,
SET_SCHED_PARAM_priority_field_check,
SET_SCHED_PARAM_lookup_old_head_ptr_idle,
SET_SCHED_PARAM_lookup_old_head_ptr_finished,
SET_SCHED_PARAM_lookup_old_tail_ptr_idle,
SET_SCHED_PARAM_lookup_old_tail_ptr_finished,
SET_SCHED_PARAM_lookup_prev_ptr_idle,
SET_SCHED_PARAM_lookup_prev_ptr_finished,
SET_SCHED_PARAM_write_back_deq_pri_entry,
SET_SCHED_PARAM_begin_add_to_new_pri_queue,
SET_SCHED_PARAM_init_tail_ptr,
SET_SCHED_PARAM_lookup_enq_old_tail_ptr_idle,
SET_SCHED_PARAM_update_enqueue_info,
SET_SCHED_PARAM_write_back_entries,
SET_SCHED_PARAM_wait_for_encoder_0,
SET_SCHED_PARAM_wait_for_encoder_1,
SET_SCHED_PARAM_last_wait_0,
SET_SCHED_PARAM_last_wait_1,
SET_SCHED_PARAM_check_encoder,
SET_SCHED_PARAM_lookup_highest_pri_entry_idle,
SET_SCHED_PARAM_lookup_highest_pri_entry_finished,
SET_SCHED_PARAM_preemption_check,
SET_SCHED_PARAM_return_with_error,
SET_SCHED_PARAM_return_with_no_error,
GET_SCHED_PARAM_begin, -- get_sched_param states
GET_SCHED_PARAM_lookup_entry,
GET_SCHED_PARAM_lookup_entry_idle,
GET_SCHED_PARAM_lookup_entry_finished,
CHECK_SCHED_PARAM_begin, -- check_sched_param states
CHECK_SCHED_PARAM_lookup_entries,
CHECK_SCHED_PARAM_lookup_entries_idle,
CHECK_SCHED_PARAM_lookup_entries_finished,
ENQ_begin, -- enqueue states
ENQ_lookup_enqueue_entry_idle,
ENQ_lookup_enqueue_entry_finished,
ENQ_start_hw_thread_begin,
ENQ_start_hw_thread_finished,
ENQ_lookup_enqueue_pri_entry_idle,
ENQ_lookup_enqueue_pri_entry_finished,
ENQ_init_head_pointer,
ENQ_init_tail_pointer,
ENQ_wait_for_encoder_0,
ENQ_lookup_old_tail_ptr,
ENQ_lookup_old_tail_ptr_idle,
ENQ_lookup_old_tail_ptr_finished,
ENQ_write_back_entries,
ENQ_lookup_highest_pri_entry,
ENQ_lookup_highest_pri_entry_idle,
ENQ_lookup_highest_pri_entry_finished,
ENQ_preemption_check,
DEQ_begin, -- dequeue states
DEQ_lookup_dequeue_entry_idle,
DEQ_lookup_dequeue_entry_finished,
DEQ_lookup_deq_pri_entry_idle,
DEQ_lookup_deq_pri_entry_finished,
DEQ_lookup_old_head_ptr_idle,
DEQ_lookup_old_head_ptr_finished,
DEQ_write_back_entries,
DEQ_wait_for_encoder_0,
DEQ_wait_for_encoder_1,
DEQ_wait_for_encoder_2,
DEQ_check_encoder_output,
DEQ_lookup_highest_pri_entry_idle,
DEQ_lookup_highest_pri_entry_finished,
MALLOC_LOCK, -- MALLOC lock states
MALLOC_LOCK_idle,
MALLOC_LOCK_idle_finished,
MALLOC_LOCK_ACQUIRE,
MALLOC_LOCK_ACQUIRE_RETURN,
MALLOC_LOCK_RELEASE,
MALLOC_LOCK_RELEASE_next,
MALLOC_LOCK_RELEASE_RETURN,
GET_ENTRY_begin, -- get entry states
GET_ENTRY_lookup_entry,
GET_ENTRY_lookup_entry_idle,
GET_ENTRY_lookup_entry_finished,
IS_QUEUED_begin, -- is_queued states
IS_QUEUED_lookup_entry,
IS_QUEUED_lookup_entry_idle,
IS_QUEUED_lookup_entry_finished,
IS_EMPTY_check, -- is_empty states
IS_EMPTY_finished,
SET_IDLE_THREAD_begin, -- set_idle_thread states
SET_IDLE_THREAD_lookup_entries_idle,
SET_IDLE_THREAD_lookup_entries_finished,
SET_IDLE_THREAD_return_with_error,
SET_IDLE_THREAD_return_with_no_error
);
signal current_state_master, next_state_master : master_state_type := idle;
---------------------------------------------------
-- is_encoder_bit_zero()
--********************
-- Function used to check an encoder bit
-- Returns booleans:
-- * '0' --> True
-- * '1' --> False
---------------------------------------------------
function is_encoder_bit_zero(pri_index: integer; e_entry: std_logic_vector(0 to INPUT_BITS-1)) return boolean is
begin
if (e_entry(pri_index) = '0') then
return true;
else
return false;
end if;
end function is_encoder_bit_zero;
---------------------------------------------------
---------------------------------------------------
-- set_encoder_bit()
-- *******************
-- Function used to set an encoder bit
--
---------------------------------------------------
function set_encoder_bit(e_bit: std_logic; pri: integer; e_entry: std_logic_vector(0 to INPUT_BITS - 1)) return std_logic_vector is
variable temp_entry : std_logic_vector(0 to INPUT_BITS-1);
begin
temp_entry := e_entry; -- make a copy of the entry
temp_entry(pri) := e_bit; -- update bit in entry
return temp_entry; -- return new entry
end function set_encoder_bit;
---------------------------------------------------
---------------------------------------------------
-- bit_set()
-- *******************
-- Determine if any bit in the array is set.
-- If any of the bits are set then '1' is returned,
-- otherwise '0' is returned.
---------------------------------------------------
function bit_set( data : in std_logic_vector ) return std_logic is
begin
for i in data'range loop
if( data(i) = '1' ) then
return '1';
end if;
end loop;
return '0';
end function;
---------------------------------------------------
---------------------------------------------------
-- get_head_pointer()
-- *******************
-- function to extract the head_pointer field from a
-- priority attribute entry
--
---------------------------------------------------
function get_head_pointer(entry: std_logic_vector(0 to 31)) return std_logic_vector is
begin
return entry(0 to 7);
end function get_head_pointer;
---------------------------------------------------
---------------------------------------------------
-- set_head_pointer()
-- *******************
-- function to set the head_pointer field for a
-- priority attribute entry
--
---------------------------------------------------
function set_head_pointer(head_ptr: std_logic_vector(0 to 7); entry: std_logic_vector(0 to 31)) return std_logic_vector is
begin
return head_ptr & entry(8 to 31);
end function set_head_pointer;
---------------------------------------------------
---------------------------------------------------
-- get_tail_pointer()
-- *******************
-- function to extract the tail_pointer field from a
-- priority attribute entry
--
---------------------------------------------------
function get_tail_pointer(entry: std_logic_vector(0 to 31)) return std_logic_vector is
begin
return entry(8 to 15);
end function get_tail_pointer;
---------------------------------------------------
---------------------------------------------------
-- set_tail_pointer()
-- *******************
-- function to set the tail_pointer field for a
-- priority attribute entry
--
---------------------------------------------------
function set_tail_pointer(tail_ptr: std_logic_vector(0 to 7); entry: std_logic_vector(0 to 31)) return std_logic_vector is
begin
return entry(0 to 7) & tail_ptr & entry(16 to 31);
end function set_tail_pointer;
---------------------------------------------------
---------------------------------------------------
-- get_priority()
-- *******************
-- function to extract the priority field from a
-- scheduler attribute entry
--
---------------------------------------------------
function get_priority(entry: std_logic_vector(0 to 31)) return std_logic_vector is
begin
return entry(9 to 15);
end function get_priority;
---------------------------------------------------
---------------------------------------------------
-- set_priority()
-- *******************
-- function to set the priority field for a
-- scheduler attribute entry
--
---------------------------------------------------
function set_priority(priority: std_logic_vector(0 to 6); entry: std_logic_vector(0 to 31)) return std_logic_vector is
begin
return entry(0 to 8) & priority & entry(16 to 31);
end function set_priority;
---------------------------------------------------
---------------------------------------------------
-- get_next_pointer()
-- *******************
-- function to extract the next_pointer field from a
-- scheduler attribute entry
--
---------------------------------------------------
function get_next_pointer(entry: std_logic_vector(0 to 31)) return std_logic_vector is
begin
return entry(1 to 8);
end function get_next_pointer;
---------------------------------------------------
---------------------------------------------------
-- set_next_pointer()
-- *******************
-- function to set the next_pointer field for a
-- scheduler attribute entry
--
---------------------------------------------------
function set_next_pointer(next_ptr: std_logic_vector(0 to 7); entry: std_logic_vector(0 to 31)) return std_logic_vector is
begin
return entry(0) & next_ptr & entry(9 to 31);
end function set_next_pointer;
---------------------------------------------------
---------------------------------------------------
-- get_prev_pointer()
-- *******************
-- function to extract the prev_pointer field from a
-- scheduler attribute entry
--
---------------------------------------------------
function get_prev_pointer(entry: std_logic_vector(0 to 31)) return std_logic_vector is
begin
return entry(16 to 23);
end function get_prev_pointer;
---------------------------------------------------
---------------------------------------------------
-- set_prev_pointer()
-- *******************
-- function to set the prev_pointer field for a
-- scheduler attribute entry
--
---------------------------------------------------
function set_prev_pointer(prev_ptr: std_logic_vector(0 to 7); entry: std_logic_vector(0 to 31)) return std_logic_vector is
begin
return entry(0 to 15) & prev_ptr & entry(24 to 31);
end function set_prev_pointer;
---------------------------------------------------
---------------------------------------------------
-- get_queue_bit()
-- *******************
-- function to extract the queue bit field from a
-- scheduler attribute entry
--
---------------------------------------------------
function get_queue_bit(entry: std_logic_vector(0 to 31)) return std_logic is
begin
return entry(0);
end function get_queue_bit;
---------------------------------------------------
---------------------------------------------------
-- set_queue_bit()
-- *******************
-- function to set the queue bit field for a
-- scheduler attribute entry
--
---------------------------------------------------
function set_queue_bit(q_bit: std_logic; entry: std_logic_vector(0 to 31)) return std_logic_vector is
begin
return q_bit & entry(1 to 31);
end function set_queue_bit;
---------------------------------------------------
---------------------------------------------------
-- Component Instantiation of the Priority Encoder
---------------------------------------------------
component parallel
generic
(
INPUT_BITS : integer := 128;
OUTPUT_BITS : integer := 7;
CHUNK_BITS : integer := 32
);
port
(
clk : in std_logic;
rst : in std_logic;
input : in std_logic_vector(0 to 127);
enable : in std_logic;
output : out std_logic_vector(0 to 6)
);
end component parallel;
---------------------------------------------------
-- Component Instantiation of the Inferred BRAM entity
---------------------------------------------------
component infer_bram
generic
(
ADDRESS_BITS : integer := 9;
DATA_BITS : integer := 32
);
port (
CLKA : in std_logic;
ENA : in std_logic;
WEA : in std_logic;
ADDRA : in std_logic_vector(0 to ADDRESS_BITS - 1);
DIA : in std_logic_vector(0 to DATA_BITS - 1);
DOA : out std_logic_vector(0 to DATA_BITS - 1)
);
end component infer_BRAM;
---------------------------------------------------
--*************************************************
-- Beginning of user_logic ARCHITECTURE
--*************************************************
------------------------------------------
-- Signals for user logic master model example
------------------------------------------
-- signals for master model control/status registers write/read
signal mst_ip2bus_data : std_logic_vector(0 to C_SLV_DWIDTH-1);
-- signals for master model control/status registers
type BYTE_REG_TYPE is array(0 to 15) of std_logic_vector(0 to 7);
signal mst_go, IP2Bus_MstWrReq : std_logic;
-- signals for master model command interface state machine
type CMD_CNTL_SM_TYPE is (CMD_IDLE, CMD_RUN, CMD_WAIT_FOR_DATA, CMD_DONE);
signal mst_cmd_sm_state : CMD_CNTL_SM_TYPE;
signal mst_cmd_sm_set_done : std_logic;
signal mst_cmd_sm_set_error : std_logic;
signal mst_cmd_sm_set_timeout : std_logic;
signal mst_cmd_sm_busy : std_logic;
signal mst_cmd_sm_clr_go : std_logic;
signal mst_cmd_sm_rd_req : std_logic;
signal mst_cmd_sm_wr_req : std_logic;
signal mst_cmd_sm_reset : std_logic;
signal mst_cmd_sm_bus_lock : std_logic;
signal IP2Bus_Addr, mst_cmd_sm_ip2bus_addr : std_logic_vector(0 to C_MST_AWIDTH-1);
signal mst_cmd_sm_ip2bus_be : std_logic_vector(0 to C_MST_DWIDTH/8-1);
signal mst_fifo_valid_write_xfer : std_logic;
signal mst_fifo_valid_read_xfer : std_logic;
begin
--USER logic implementation added here
-- user logic master command interface assignments
IP2Bus_MstRd_Req <= mst_cmd_sm_rd_req;
IP2Bus_MstWr_Req <= mst_cmd_sm_wr_req;
IP2Bus_Mst_Addr <= mst_cmd_sm_ip2bus_addr;
IP2Bus_Mst_BE <= mst_cmd_sm_ip2bus_be;
IP2Bus_Mst_Lock <= mst_cmd_sm_bus_lock;
IP2Bus_Mst_Reset <= mst_cmd_sm_reset;
--implement master command interface state machine
mst_go <= IP2Bus_MstWrReq;
MASTER_CMD_SM_PROC : process( Bus2IP_Clk ) is
begin
if ( Bus2IP_Clk'event and Bus2IP_Clk = '1' ) then
if ( Bus2IP_Reset = '1' ) then
-- reset condition
mst_cmd_sm_state <= CMD_IDLE;
mst_cmd_sm_clr_go <= '0';
mst_cmd_sm_rd_req <= '0';
mst_cmd_sm_wr_req <= '0';
mst_cmd_sm_bus_lock <= '0';
mst_cmd_sm_reset <= '0';
mst_cmd_sm_ip2bus_addr <= (others => '0');
mst_cmd_sm_ip2bus_be <= (others => '0');
mst_cmd_sm_set_done <= '0';
mst_cmd_sm_set_error <= '0';
mst_cmd_sm_set_timeout <= '0';
mst_cmd_sm_busy <= '0';
else
-- default condition
mst_cmd_sm_clr_go <= '0';
mst_cmd_sm_rd_req <= '0';
mst_cmd_sm_wr_req <= '0';
mst_cmd_sm_bus_lock <= '0';
mst_cmd_sm_reset <= '0';
mst_cmd_sm_ip2bus_addr <= (others => '0');
mst_cmd_sm_ip2bus_be <= (others => '0');
mst_cmd_sm_set_done <= '0';
mst_cmd_sm_set_error <= '0';
mst_cmd_sm_set_timeout <= '0';
mst_cmd_sm_busy <= '1';
-- state transition
case mst_cmd_sm_state is
when CMD_IDLE =>
if ( mst_go = '1' ) then
mst_cmd_sm_state <= CMD_RUN;
mst_cmd_sm_clr_go <= '1';
else
mst_cmd_sm_state <= CMD_IDLE;
mst_cmd_sm_busy <= '0';
end if;
when CMD_RUN =>
if ( Bus2IP_Mst_CmdAck = '1' and Bus2IP_Mst_Cmplt = '0' ) then
mst_cmd_sm_state <= CMD_WAIT_FOR_DATA;
elsif ( Bus2IP_Mst_Cmplt = '1' ) then
mst_cmd_sm_state <= CMD_DONE;
if ( Bus2IP_Mst_Cmd_Timeout = '1' ) then
-- PLB address phase timeout
mst_cmd_sm_set_error <= '1';
mst_cmd_sm_set_timeout <= '1';
elsif ( Bus2IP_Mst_Error = '1' ) then
-- PLB data transfer error
mst_cmd_sm_set_error <= '1';
end if;
else
mst_cmd_sm_state <= CMD_RUN;
mst_cmd_sm_rd_req <= '0'; -- Perform a write (rd = '0', wr = '1')
mst_cmd_sm_wr_req <= '1';
mst_cmd_sm_ip2bus_addr <= IP2Bus_Addr; -- Setup address
mst_cmd_sm_ip2bus_be <= (others => '1'); -- Use all byte lanes
mst_cmd_sm_bus_lock <= '0'; -- De-assert bus lock
end if;
when CMD_WAIT_FOR_DATA =>
if ( Bus2IP_Mst_Cmplt = '1' ) then
mst_cmd_sm_state <= CMD_DONE;
else
mst_cmd_sm_state <= CMD_WAIT_FOR_DATA;
end if;
when CMD_DONE =>
mst_cmd_sm_state <= CMD_IDLE;
mst_cmd_sm_set_done <= '1';
mst_cmd_sm_busy <= '0';
when others =>
mst_cmd_sm_state <= CMD_IDLE;
mst_cmd_sm_busy <= '0';
end case;
end if;
end if;
end process MASTER_CMD_SM_PROC;
---------------------------------------------------
-- Entity Instantiation of the Priority Encoder
---------------------------------------------------
priority_encoder : parallel
generic map
(
INPUT_BITS => INPUT_BITS,
OUTPUT_BITS => OUTPUT_BITS,
CHUNK_BITS => CHUNK_BITS
)
port map
(
clk => Bus2IP_Clk,
rst => encoder_reset,
input => encoder_input,
enable => encoder_enable,
output => encoder_output
);
---------------------------------------------------
-- Entity Instantiation of the THREAD_DATA BRAM
---------------------------------------------------
thread_data_bram : infer_bram
generic map
(
ADDRESS_BITS => BRAM_ADDRESS_BITS,
DATA_BITS => BRAM_DATA_BITS
)
port map
(
CLKA => Bus2IP_Clk,
ENA => ENA,
WEA => WEA,
ADDRA => ADDRA,
DIA => DIA,
DOA => DOA
);
---------------------------------------------------
-- Entity Instantiation of the PRIORITY_DATA BRAM
---------------------------------------------------
priority_data_bram : infer_bram
generic map
(
ADDRESS_BITS => BRAM_ADDRESS_BITS,
DATA_BITS => BRAM_DATA_BITS
)
port map
(
CLKA => Bus2IP_Clk,
ENA => ENB,
WEA => WEB,
ADDRA => ADDRB,
DIA => DIB,
DOA => DOB
);
---------------------------------------------------
-- Entity Instantiation of the PARAM_DATA BRAM
---------------------------------------------------
param_data_bram : infer_bram
generic map
(
ADDRESS_BITS => BRAM_ADDRESS_BITS,
DATA_BITS => BRAM_DATA_BITS
)
port map
(
CLKA => Bus2IP_Clk,
ENA => ENU,
WEA => WEU,
ADDRA => ADDRU,
DIA => DIU,
DOA => DOU
);
-- Create concatenation signals
Bus2IP_RdCE_concat <= bit_set(Bus2IP_RdCE);
Bus2IP_WrCE_concat <= bit_set(Bus2IP_WrCE);
-- Connect registers to external port signals...
SCH2TM_busy <= sched_busy;
SCH2TM_next_cpu_tid <= next_thread_id_reg;
SCH2TM_next_tid_valid <= Next_Thread_Valid_reg;
-- Connect port signals to registers...
TM2SCH_current_cpu_tid_reg <= TM2SCH_current_cpu_tid;
-- Toggle on/off timeout suppression with read/write requests
--IP2Bus_ToutSup <= (Bus2IP_RdCE_concat) or (Bus2IP_WrCE_concat);
-- AND the Preemption Interrupt Enable w/ the Interrupt line
Preemption_Interrupt <= (Preemption_Interrupt_Line) and (Preemption_Interrupt_Enable);
-- *************************************************************************
-- Process: TM_OUTPUT_CONTROLLER
-- Purpose: Control output from IP to TM
-- * Can be controlled using TM_data_ready and TM_data_out signals.
-- *************************************************************************
TM_OUTPUT_CONTROLLER : process( Bus2IP_Clk, tm_data_ready ) is
begin
if( Bus2IP_Clk'event and Bus2IP_Clk = '1' ) then
if( TM_data_ready = '1' ) then
SCH2TM_data <= TM_data_out; -- put data out to TM and leave until next transaction
end if;
end if;
end process TM_OUTPUT_CONTROLLER;
-- *************************************************************************
-- Process: BUS_OUTPUT_CONTROLLER
-- Purpose: Control output from IP to Bus
-- * Can be controlled using bus_data_ready, bus_ack_ready, and bus_data_out signals.
-- *************************************************************************
BUS_OUTPUT_CONTROLLER : process( Bus2IP_Clk, bus_data_ready, bus_ack_ready ) is
begin
if( Bus2IP_Clk'event and Bus2IP_Clk = '1' ) then
if( bus_data_ready = '1' and bus_ack_ready = '1' ) then
IP2Bus_Data <= bus_data_out; -- put data on bus
IP2Bus_Ack <= '1'; -- ACK bus
elsif (bus_data_ready = '1' and bus_ack_ready = '0') then
IP2Bus_Data <= bus_data_out; -- put data on bus
IP2Bus_Ack <= '0'; -- turn off ACK
else
IP2Bus_Data <= (others => '0'); -- output 0's on bus
IP2Bus_Ack <= '0'; -- turn off ACK
end if;
end if;
end process BUS_OUTPUT_CONTROLLER;
ACK_ROUTER : process (IP2Bus_Ack, Bus2IP_RdCE_concat, Bus2IP_WrCE_concat) is
begin
-- Turn an "ACK" into a specific ACK (read or write ACK)
if (Bus2IP_RdCE_concat = '1') then
IP2Bus_RdAck <= IP2Bus_Ack;
IP2Bus_WrAck <= '0';
else
IP2Bus_RdAck <= '0';
IP2Bus_WrAck <= IP2Bus_Ack;
end if;
end process;
-- FIXME: This process should be incorporated into the FSM
-- *************************************************************************
-- Process: RESET_ADDR_INC
-- Purpose: Process to increment the "reset" address so that each element of
-- the BRAMs can be indexed and initialized
-- *************************************************************************
RESET_ADDR_INC : process( Bus2IP_Clk, Soft_Reset, inside_reset, ENA ) is
begin
if( Bus2IP_Clk'event and Bus2IP_Clk = '1' ) then
if( Soft_Reset = '1' and inside_reset = '0' ) then
reset_addr <= (others => '0');
elsif( ENA = '1' ) then
reset_addr <= reset_addr + 1;
end if;
end if;
end process RESET_ADDR_INC;
-- *************************************************************************
-- Process: TM_CMD_PROC
-- Purpose: Controller and decoder for incoming TM operations (requests)
-- *************************************************************************
TM_CMD_PROC : process (Bus2IP_Clk, TM2SCH_opcode, TM2SCH_data, TM2SCH_request ) is
begin
if( Bus2IP_Clk'event and Bus2IP_Clk = '1' ) then
Enqueue_Request <= '0';
Dequeue_Request <= '0';
Is_Queued_Request <= '0';
Is_Empty_Request <= '0';
if (TM2SCH_request = '1') then
case (TM2SCH_opcode) is
when ENQUEUE_OPCODE => Enqueue_Request <= '1';
when DEQUEUE_OPCODE => Dequeue_Request <= '1';
when IS_QUEUED_OPCODE => Is_Queued_Request <= '1';
when IS_EMPTY_OPCODE => Is_Empty_Request <= '1';
when others => null;
end case;
end if;
end if;
end process TM_CMD_PROC;
-- *************************************************************************
-- Process: BUS_CMD_PROC
-- Purpose: Controller and decoder for incoming bus operations (reads and writes)
-- *************************************************************************
BUS_CMD_PROC : process (Bus2IP_Clk, Bus2IP_RdCE_concat, Bus2IP_WrCE_concat, Bus2IP_Addr ) is
begin
if( Bus2IP_Clk'event and Bus2IP_Clk = '1' ) then
Get_EncoderOutput_Request <= '0';
Set_SchedParam_Request <= '0';
Get_SchedParam_Request <= '0';
Check_SchedParam_Request <= '0';
Toggle_Preemption_Request <= '0';
Get_IdleThread_Request <= '0';
Set_IdleThread_Request <= '0';
Get_Entry_Request <= '0';
Default_Priority_Request <= '0';
Error_Request <= '0';
MALLOC_Lock_Request <= '0';
if( Bus2IP_WrCE_concat = '1' ) then
case Bus2IP_Addr(24 to 31) is
when C_SET_SCHEDPARAM => Set_SchedParam_Request <= '1';
when C_TOGGLE_PREEMPTION => Toggle_Preemption_Request <= '1';
when others => Error_Request <= '1';
end case;
elsif( Bus2IP_RdCE_concat = '1' ) then
case Bus2IP_Addr(24 to 31) is
when C_GET_IDLE_THREAD => Get_IdleThread_Request <= '1';
when C_SET_IDLE_THREAD => Set_IdleThread_Request <= '1';
when C_GET_ENTRY => Get_Entry_Request <= '1';
when C_GET_ENCODER_OUTPUT => Get_EncoderOutput_Request <= '1';
when C_SET_DEFAULT_PRIORITY => Default_Priority_Request <= '1';
when C_GET_SCHEDPARAM => Get_SchedParam_Request <= '1';
when C_CHECK_SCHEDPARAM => Check_SchedParam_Request <= '1';
when C_MALLOC_LOCK => MALLOC_Lock_Request <= '1';
when others => Error_Request <= '1';
end case;
end if;
end if;
end process BUS_CMD_PROC;
-- *************************************************************************
-- Process: MASTER_FSM_STATE_PROC
-- Purpose: Synchronous FSM controller for the master state machine
-- *************************************************************************
MASTER_FSM_STATE_PROC: process(
Bus2IP_Clk, Soft_Reset, inside_reset, next_state_master, encoder_enable_next,
enqueue_pri_entry_next, deq_pri_entry_next, old_tail_ptr_next,
encoder_input_next, next_thread_id_next, lookup_entry_next, sched_param_next,
dequeue_entry_next, enqueue_entry_next, current_entry_pri_value_next,
old_priority_next, new_priority_next, lookup_id_next, idle_thread_id_next,
idle_thread_valid_next, inside_reset_next, Preemption_Interrupt_Enable_next,
sched_busy_next, Next_Thread_Valid_next, debug_reg_next, temp_valid_next,
lock_op_next, lock_count_next, malloc_mutex_next, malloc_mutex_holder_next ) is
begin
if ( Bus2IP_Clk'event and Bus2IP_Clk = '1' ) then
if( Soft_Reset = '1' and inside_reset = '0' ) then
-- Initialize all signals...
current_state_master <= reset;
encoder_enable <= '0';
enqueue_pri_entry <= (others => '0');
deq_pri_entry <= (others => '0');
old_tail_ptr <= (others => '0');
encoder_input <= (others => '0');
next_thread_id_reg <= (others => '0');
lookup_entry <= (others => '0');
sched_param <= (others => '0');
dequeue_entry <= (others => '0');
enqueue_entry <= (others => '0');
current_entry_pri_value <= (others => '0');
old_priority <= (others => '0');
new_priority <= (others => '0');
lookup_id <= (others => '0');
idle_thread_id <= (others => '0');
debug_reg <= (others => '0');
idle_thread_valid <= '0';
temp_valid <= '0';
inside_reset <= '1';
Preemption_Interrupt_Enable <= '0';
sched_busy <= '0';
Next_Thread_Valid_reg <= '0';
lock_count <= (others => '0');
lock_op <= '0';
malloc_mutex <= '0';
malloc_mutex_holder <= x"FF";
else
-- Assign all signals to their next state...
current_state_master <= next_state_master;
encoder_enable <= encoder_enable_next;
enqueue_pri_entry <= enqueue_pri_entry_next;
deq_pri_entry <= deq_pri_entry_next;
old_tail_ptr <= old_tail_ptr_next;
encoder_input <= encoder_input_next;
next_thread_id_reg <= next_thread_id_next;
lookup_entry <= lookup_entry_next;
sched_param <= sched_param_next;
dequeue_entry <= dequeue_entry_next;
enqueue_entry <= enqueue_entry_next;
current_entry_pri_value <= current_entry_pri_value_next;
old_priority <= old_priority_next;
new_priority <= new_priority_next;
lookup_id <= lookup_id_next;
idle_thread_id <= idle_thread_id_next;
debug_reg <= debug_reg_next;
idle_thread_valid <= idle_thread_valid_next;
temp_valid <= temp_valid_next;
inside_reset <= inside_reset_next;
Preemption_Interrupt_Enable <= Preemption_Interrupt_Enable_next;
sched_busy <= sched_busy_next;
Next_Thread_Valid_reg <= Next_Thread_Valid_next;
lock_count <= lock_count_next;
lock_op <= lock_op_next;
malloc_mutex <= malloc_mutex_next;
malloc_mutex_holder <= malloc_mutex_holder_next;
end if;
end if;
end process MASTER_FSM_STATE_PROC;
-- *************************************************************************
-- Process: MASTER_FSM_LOGIC_PROC
-- Purpose: Combinational process that contains all state machine logic and
-- state transitions for the master state machine
-- *************************************************************************
MASTER_FSM_LOGIC_PROC: process (
reset_addr, next_thread_id_reg, lookup_entry, sched_param, dequeue_entry,
enqueue_entry, current_entry_pri_value, old_priority, new_priority, lookup_id,
idle_thread_id, idle_thread_valid, temp_valid, current_state_master, inside_reset,
Preemption_Interrupt_Enable, Enqueue_Request, Dequeue_Request,
Is_Queued_Request, Is_Empty_Request, Get_EncoderOutput_Request, Error_Request,
Set_SchedParam_Request, Get_SchedParam_Request, Check_SchedParam_Request,
Toggle_Preemption_Request, Bus2IP_Data, Get_IdleThread_Request,
Set_IdleThread_Request, Get_Entry_Request, Default_Priority_Request,
Bus2IP_RdCE_concat, Bus2IP_WrCE_concat, Soft_Reset, DOA, debug_reg,
TM2SCH_current_cpu_tid_reg, TM2SCH_current_cpu_tid, Bus2IP_Addr, sched_busy,
Next_Thread_Valid_reg, SWTM_DOB, encoder_input, encoder_output, encoder_enable,
enqueue_pri_entry, deq_pri_entry, old_tail_ptr, DOB, DOU, TM2SCH_data,
lock_op, lock_count, malloc_mutex, malloc_mutex_holder, MALLOC_Lock_Request ) is
-- Idle Variable, concatenation of all request signals
variable idle_concat : std_logic_vector(0 to 14);
begin
IP2Bus_Error <= '0'; -- no error
IP2Bus_Addr <= (others => '0');
IP2Bus_MstWrReq <= '0';
IP2Bus_MstWr_d <= (others => '0');
Reset_Done <= '0'; -- reset is done unless we override it later
encoder_reset <= '0';
ADDRA <= (others => '0');
DIA <= (others => '0');
ENA <= '0';
WEA <= '0';
ADDRB <= (others => '0');
DIB <= (others => '0');
ENB <= '0';
WEB <= '0';
ADDRU <= (others => '0');
DIU <= (others => '0');
ENU <= '0';
WEU <= '0';
SWTM_ADDRB <= (others => '0');
SWTM_DIB <= (others => '0');
SWTM_ENB <= '0';
SWTM_WEB <= '0';
encoder_enable_next <= '0';
enqueue_pri_entry_next <= enqueue_pri_entry;
deq_pri_entry_next <= deq_pri_entry;
old_tail_ptr_next <= old_tail_ptr;
encoder_input_next <= encoder_input;
next_state_master <= current_state_master;
next_thread_id_next <= next_thread_id_reg;
lookup_entry_next <= lookup_entry;
sched_param_next <= sched_param;
dequeue_entry_next <= dequeue_entry;
enqueue_entry_next <= enqueue_entry;
current_entry_pri_value_next <= current_entry_pri_value;
old_priority_next <= old_priority;
new_priority_next <= new_priority;
lookup_id_next <= lookup_id;
idle_thread_id_next <= idle_thread_id;
debug_reg_next <= debug_reg;
idle_thread_valid_next <= idle_thread_valid;
temp_valid_next <= temp_valid;
inside_reset_next <= inside_reset;
bus_data_out <= (others => '0');
bus_data_ready <= '0';
bus_ack_ready <= '0';
TM_data_out <= (others => '0');
TM_data_ready <= '0';
Preemption_Interrupt_Line <= '0';
Preemption_Interrupt_Enable_next<= Preemption_Interrupt_Enable;
sched_busy_next <= sched_busy;
Next_Thread_Valid_next <= Next_Thread_Valid_reg;
lock_count_next <= lock_count;
lock_op_next <= lock_op;
malloc_mutex_next <= malloc_mutex;
malloc_mutex_holder_next <= malloc_mutex_holder;
case current_state_master is
when idle =>
-- Assign to variable for case statement
idle_concat := (Enqueue_Request & Dequeue_Request & Is_Queued_Request & Is_Empty_Request & Get_EncoderOutput_Request &
Set_SchedParam_Request & Toggle_Preemption_Request & Get_IdleThread_Request &
Set_IdleThread_Request & Get_Entry_Request & Default_Priority_Request &
Get_SchedParam_Request & Check_SchedParam_Request & MALLOC_Lock_Request & Error_Request);
-- Decode request
case (idle_concat) is
when "100000000000000" => next_state_master <= ENQ_begin; -- Enqueue
when "010000000000000" => next_state_master <= DEQ_begin; -- Dequeue
when "001000000000000" => next_state_master <= IS_QUEUED_begin; -- Is_Queued
when "000100000000000" => next_state_master <= IS_EMPTY_check; -- Is_Empty
when "000010000000000" => next_state_master <= GET_encoder_output; -- Get_EncoderOutput
when "000001000000000" => next_state_master <= SET_SCHED_PARAM_begin; -- Set_SchedParam
when "000000100000000" => Preemption_Interrupt_Enable_next <= Bus2IP_Data(0); -- Toggle_Preemption (single clock cycle op.)
bus_data_out <= (others => '0');
bus_data_ready <= '1';
bus_ack_ready <= '1';
next_state_master <= wait_trans_done;
when "000000010000000" => bus_data_out <= Z32(0 to 22) & idle_thread_id & idle_thread_valid; -- Get_IdleThread
bus_data_ready <= '1';
bus_ack_ready <= '1';
next_state_master <= wait_trans_done;
when "000000001000000" => next_state_master <= SET_IDLE_THREAD_begin; -- Set_IdleThread
when "000000000100000" => next_state_master <= GET_ENTRY_begin; -- Get_Entry
when "000000000010000" => bus_data_out <= (others => '1'); -- ERROR (Set_Default_Priority)
bus_data_ready <= '1';
bus_ack_ready <= '1';
next_state_master <= wait_trans_done;
when "000000000001000" => next_state_master <= GET_SCHED_PARAM_begin; -- Get_SchedParam
when "000000000000100" => next_state_master <= CHECK_SCHED_PARAM_begin; -- Check_SchedParam
when "000000000000010" => next_state_master <= MALLOC_LOCK; -- MALLOC Lock
when "000000000000001" => bus_data_out <= (others => '1'); -- Error!!!
bus_data_ready <= '1';
bus_ack_ready <= '1';
next_state_master <= wait_trans_done;
when others => next_state_master <= idle; -- Others, stay in idle state
end case;
when wait_trans_done =>
-- Goal of this state is to return to the idle state ONLY (iff) the bus transaction has COMPLETELY ended!
bus_data_ready <= '0'; -- de-assert bus transaction signals
bus_ack_ready <= '0';
if( Bus2IP_RdCE_concat = '0' and Bus2IP_WrCE_concat = '0' ) then
next_state_master <= idle;
end if;
----------------------------
-- RESET: begin
----------------------------
when reset =>
WEA <= '0'; -- Turn off any BRAM access that was active
ENA <= '0';
WEB <= '0';
ENB <= '0';
WEU <= '0';
ENU <= '0';
SWTM_WEB<= '0';
SWTM_ENB<= '0';
encoder_reset <= '1'; -- Reset priority encoder
TM_data_out <= (others => '0'); -- Reset TM data out
TM_data_ready <= '1';
Reset_Done <= '0'; -- De-assert Reset_Done
next_state_master <= reset_BRAM;
when reset_BRAM =>
ADDRA <= reset_addr; -- setup BRAM write to init. THREAD_DATA entry
DIA <= set_priority("1000000", BRAM_init_string(0 to 22) & reset_addr);
ENA <= '1';
WEA <= '1';
ADDRB <= reset_addr; -- setup BRAM write to init. PRIORITY_DATA entry
DIB <= BRAM_init_string;
ENB <= '1';
WEB <= '1';
ADDRU <= reset_addr; -- setup BRAM write to init. PARAM_DATA entry
DIU <= BRAM_init_string;
ENU <= '1';
WEU <= '1';
if( reset_addr = "011111111" ) then
next_state_master <= reset_wait_4_ack;
end if;
when reset_wait_4_ack =>
ENA <= '0'; -- turn off BRAM access
WEA <= '0';
ENB <= '0'; -- turn off BRAM access
WEB <= '0';
ENU <= '0'; -- turn off BRAM access
WEU <= '0';
Reset_Done <= '1'; -- Assert that reset has completed
if( Soft_Reset = '0' ) then -- if reset is complete
Reset_Done <= '0'; -- de-assert that reset is complete
inside_reset_next <= '0'; -- de-assert to signal that process is no longer in reset
next_state_master <= idle; -- return to idle stage
end if;
----------------------------
-- RESET: end
----------------------------
----------------------------
-- MALLOC_LOCK: begin
----------------------------
-- Communication - BusCom
-- Submit a request to acquire or release the malloc lock
-- returns zero if the request was denied, one if the request was granted
when MALLOC_LOCK =>
-- Bus2IP_Addr(13) = 0 : RELEASE lock
-- Bus2IP_Addr(13) = 1 : ACQUIRE lock
lock_op_next <= Bus2IP_Addr(13);
-- Store tid requesting the lock
lookup_id_next <= Bus2IP_Addr(16 to 23);
next_state_master <= MALLOC_LOCK_IDLE;
when MALLOC_LOCK_idle =>
-- idle state
next_state_master <= MALLOC_LOCK_idle_finished;
when MALLOC_LOCK_idle_finished =>
-- default next state
next_state_master <= MALLOC_LOCK_ACQUIRE;
if(lock_op = '0') then
-- Override default next state
next_state_master <= MALLOC_LOCK_RELEASE;
end if;
when MALLOC_LOCK_ACQUIRE =>
if(malloc_mutex = '0') then
malloc_mutex_holder_next <= lookup_id;
lock_count_next <= lock_count + 1;
malloc_mutex_next <= '1';
elsif(malloc_mutex = '1' AND malloc_mutex_holder = lookup_id) then
lock_count_next <= lock_count + 1;
end if;
next_state_master <= MALLOC_LOCK_ACQUIRE_RETURN;
when MALLOC_LOCK_ACQUIRE_RETURN =>
if(malloc_mutex_holder = lookup_id) then
bus_data_out <= Z32(0 to 3) & lock_count & malloc_mutex_holder & Z32(16 to 30) & '1';
else
bus_data_out <= Z32(0 to 3) & lock_count & malloc_mutex_holder & Z32(16 to 31);
end if;
bus_data_ready <= '1';
bus_ack_ready <= '1';
next_state_master <= wait_trans_done;
when MALLOC_LOCK_RELEASE =>
if(malloc_mutex_holder = lookup_id) then
lock_count_next <= lock_count - 1;
end if;
next_state_master <= MALLOC_LOCK_RELEASE_next;
when MALLOC_LOCK_RELEASE_next =>
if(lock_count = x"0") then
-- Release the lock
malloc_mutex_next <= '0';
malloc_mutex_holder_next <= x"FF";
end if;
next_state_master <= MALLOC_LOCK_RELEASE_RETURN;
when MALLOC_LOCK_RELEASE_RETURN =>
if(malloc_mutex_holder = lookup_id) then
bus_data_out <= Z32(0 to 3) & lock_count & malloc_mutex_holder & Z32(16 to 30) & '1';
else
bus_data_out <= Z32(0 to 3) & lock_count & malloc_mutex_holder & Z32(16 to 31);
end if;
bus_data_ready <= '1';
bus_ack_ready <= '1';
next_state_master <= wait_trans_done;
----------------------------
-- MALLOC_LOCK: end
----------------------------
----------------------------
-- ENQ: begin
----------------------------
when ENQ_begin =>
debug_reg_next <= "00" & ENQUEUE_OPCODE & TM2SCH_data & Z32(16 to 31); -- store debug info
sched_busy_next <= '1'; -- assert that scheduler is busy
lookup_id_next <= TM2SCH_data; -- store threadID to ENQ
ADDRA <= '0' & TM2SCH_data; -- setup BRAM read for tid to enqueue from THREAD_DATA
ENA <= '1';
WEA <= '0';
ADDRU <= '0' & TM2SCH_data; -- setup BRAM read for tid to enqueue from PARAM_DATA
ENU <= '1';
WEU <= '0';
next_state_master <= ENQ_lookup_enqueue_entry_idle;
when ENQ_lookup_enqueue_entry_idle =>
-- idle stage
next_state_master <= ENQ_lookup_enqueue_entry_finished;
when ENQ_lookup_enqueue_entry_finished =>
-- DOA has THREAD_DATA entry for tid to ENQ
-- DOU has PARAM_DATA entry for tid to ENQ
-- Check scheduling paramter:
-- If HW range: start HW thread
-- If SW range: add thread to ready-to-run queue
case ( DOU(0 to 24) ) is
when "0000000000000000000000000" =>
-- SW-valid range, proceed with ENQ operation...
debug_reg_next <= debug_reg(0 to 27) & "1000";
Next_Thread_Valid_next <= '0'; -- invalidate the current next_thread
enqueue_entry_next <= set_queue_bit('1',DOA); -- store entry and set as queued
new_priority_next <= get_priority(DOA); -- Assigned priority to this signal b/c used to address encoder_input (used in state below)
ADDRB <= "00" & get_priority(DOA); -- setup BRAM read to get PRIORITY_DATA entry for the enq'd thread
ENB <= '1';
WEB <= '0';
next_state_master <=ENQ_lookup_enqueue_pri_entry_idle;
when others =>
-- HW-valid range, proceed with start HW thread operation...
debug_reg_next <= debug_reg(0 to 27) & "1110";
sched_param_next <= DOU; -- store scheduling param. (base addr. of HW thread)
TM_data_out <= Z32(0 to 7); -- return status to the TM, so the TM will continue processing
TM_data_ready <= '1'; -- and unlock the bus (freeing it so that we can make a master transaction)
sched_busy_next <= '0';
-- No longer use these lines for the new PLB interface
--bus_data_out <= Z32(0 to 27) & HW_THREAD_START; -- put data on bus w/o ACK (for the upcoming write operation)
--bus_data_ready <= '1';
--bus_ack_ready <= '0';
next_state_master <= ENQ_start_hw_thread_begin;
end case;
when ENQ_start_hw_thread_begin =>
-- Start a bus write transaction to start HW thread
IP2Bus_Addr <= sched_param; -- write to base addr. of HW thread (data was put on bus in previous state)
IP2Bus_MstWrReq <= '1';
IP2Bus_MstWr_d <= Z32(0 to 27) & HW_THREAD_START; -- put data to write on bus w/o ACK
next_state_master <= ENQ_start_hw_thread_finished;
when ENQ_start_hw_thread_finished =>
if (mst_cmd_sm_busy = '0') then
-- Master FSM has finished our request, de-assert request lines, and continue on
-- HW thread has been started
-- TM has already been ACK'ed
-- now just return to idle
IP2Bus_Addr <= (others => '0'); -- write to base addr. of HW thread (data was put on bus in previous state)
IP2Bus_MstWrReq <= '0';
IP2Bus_MstWr_d <= (others => '0'); -- put data to write on bus w/o ACK
next_state_master <= idle;
else
-- Master FSM has not yet detected the request, persist
IP2Bus_Addr <= sched_param; -- write to base addr. of HW thread (data was put on bus in previous state)
IP2Bus_MstWrReq <= '1';
IP2Bus_MstWr_d <= Z32(0 to 27) & HW_THREAD_START; -- put data to write on bus w/o ACK
next_state_master <= ENQ_start_hw_thread_finished;
end if;
when ENQ_lookup_enqueue_pri_entry_idle =>
-- idle stage
next_state_master <= ENQ_lookup_enqueue_pri_entry_finished;
when ENQ_lookup_enqueue_pri_entry_finished =>
enqueue_pri_entry_next <= DOB; -- store pri_entry
if ( is_encoder_bit_zero(conv_integer(new_priority), encoder_input)) then
-- Queue is empty for this priority level
-- set encoder_input bit for given priority
encoder_input_next <= set_encoder_bit('1', conv_integer(get_priority(enqueue_entry)), encoder_input);
encoder_enable_next <= '1'; -- allow the priority encoder to process, 1
next_state_master <= ENQ_init_head_pointer;
else
-- Queue is not empty for this priority level
old_tail_ptr_next <= get_tail_pointer(DOB); -- store old tail_ptr
next_state_master <= ENQ_lookup_old_tail_ptr;
end if;
when ENQ_init_head_pointer =>
-- Set head_ptr to the lookup_id
enqueue_pri_entry_next <= set_head_pointer(lookup_id, enqueue_pri_entry);
next_state_master <= ENQ_init_tail_pointer;
when ENQ_init_tail_pointer =>
-- Set tail_ptr to the lookup_id
enqueue_pri_entry_next <= set_tail_pointer(lookup_id, enqueue_pri_entry);
next_state_master <= ENQ_wait_for_encoder_0;
when ENQ_wait_for_encoder_0 =>
-- idle stage
next_state_master <= ENQ_write_back_entries;
when ENQ_lookup_old_tail_ptr =>
ADDRA <= '0' & old_tail_ptr; -- setup read of old tail_ptr
ENA <= '1';
WEA <= '0';
next_state_master <= ENQ_lookup_old_tail_ptr_idle;
when ENQ_lookup_old_tail_ptr_idle =>
-- idle stage
next_state_master <= ENQ_lookup_old_tail_ptr_finished;
when ENQ_lookup_old_tail_ptr_finished =>
-- setup write to make old_tail_ptr's next_ptr point to newly enq'd thread
ADDRA <= '0' & old_tail_ptr;
ENA <= '1';
WEA <= '1';
DIA <= set_next_pointer(lookup_id, DOA);
-- Update enqueue_entry's prev. ptr to point to old_tail_ptr
enqueue_entry_next <= set_prev_pointer(old_tail_ptr, enqueue_entry);
-- Update priority entry's tail_ptr to be newly enq'd thread
enqueue_pri_entry_next <= set_tail_pointer(lookup_id, enqueue_pri_entry);
next_state_master <= ENQ_write_back_entries;
when ENQ_write_back_entries =>
ADDRA <= '0' & lookup_id; -- Write back enqueue_entry
ENA <= '1';
WEA <= '1';
DIA <= enqueue_entry;
ADDRB <= "00" & get_priority(enqueue_entry); -- Write back enqueue_pri_entry
ENB <= '1';
WEB <= '1';
DIB <= enqueue_pri_entry;
next_state_master <= ENQ_lookup_highest_pri_entry;
when ENQ_lookup_highest_pri_entry =>
ADDRB <= "00" & encoder_output; -- setup read of highest PRIORITY_DATA entry in system
ENB <= '1';
WEA <= '0';
ADDRA <= '0' & TM2SCH_current_cpu_tid_reg; -- setup read of currently running thread
ENA <= '1';
WEA <= '0';
next_state_master <= ENQ_lookup_highest_pri_entry_idle;
when ENQ_lookup_highest_pri_entry_idle =>
-- idle stage
next_state_master <= ENQ_lookup_highest_pri_entry_finished;
when ENQ_lookup_highest_pri_entry_finished =>
-- DOA has current thread entry
-- DOB has highest priority entry
current_entry_pri_value_next <= get_priority(DOA); -- store current_entry's priority
next_thread_id_next <= get_head_pointer(DOB); -- store next_thread_id
next_state_master <= ENQ_preemption_check;
when ENQ_preemption_check =>
-- Check if next_thread_id has "better" priority than the current_entry_pri_value
if( encoder_output < current_entry_pri_value ) then
Preemption_Interrupt_Line <= '1';
end if;
TM_data_out <= get_queue_bit(enqueue_entry) & Z32(1 to 7); -- return 0x80 to TM
TM_data_ready <= '1';
Next_Thread_Valid_next <= '1'; -- Assert that the next_thread is valid
sched_busy_next <= '0'; -- de-assert busy signal
next_state_master <= idle; -- return to idle stage
----------------------------
-- ENQ: end
----------------------------
----------------------------
-- DEQ: begin
----------------------------
when DEQ_begin =>
debug_reg_next <= "00" & DEQUEUE_OPCODE & TM2SCH_data & Z32(16 to 31); -- store debug info
sched_busy_next <= '1'; -- assert that scheduler is busy
Next_Thread_Valid_next <= '0'; -- invalidate the next_thread
ADDRA <= '0' & TM2SCH_current_cpu_tid; -- setup BRAM read of thread to dequeue
ENA <= '1';
WEA <= '0';
next_state_master <= DEQ_lookup_dequeue_entry_idle;
when DEQ_lookup_dequeue_entry_idle =>
-- idle stage
next_state_master <= DEQ_lookup_dequeue_entry_finished;
when DEQ_lookup_dequeue_entry_finished =>
dequeue_entry_next <= set_queue_bit('0',DOA); -- store entry in variable and clear queue-bit
ADDRB <= "00" & get_priority(DOA); -- setup read of deq_pri_entry
ENB <= '1';
WEB <= '0';
next_state_master <= DEQ_lookup_deq_pri_entry_idle;
when DEQ_lookup_deq_pri_entry_idle =>
-- idle stage
next_state_master <= DEQ_lookup_deq_pri_entry_finished;
when DEQ_lookup_deq_pri_entry_finished =>
deq_pri_entry_next <= DOB; -- store deq entry from PRIORITY_DATA
if ( get_head_pointer(DOB) = get_tail_pointer(DOB) ) then
-- If list priority Q has 1 element (head = tail) then list will now be empty
-- Clear encoder bit for given priority
encoder_input_next <= set_encoder_bit('0', conv_integer(get_priority(dequeue_entry)), encoder_input);
encoder_enable_next <= '1'; -- allow the priority encoder to process, 1
next_state_master <= DEQ_wait_for_encoder_0;
else
-- Otherwise...
ADDRA <= '0' & get_head_pointer(DOB); -- setup read of head_ptr
ENA <= '1';
WEA <= '0';
next_state_master <= DEQ_lookup_old_head_ptr_idle;
end if;
when DEQ_wait_for_encoder_0 =>
-- idle stage
next_state_master <= DEQ_wait_for_encoder_1;
when DEQ_wait_for_encoder_1 =>
-- idle stage
next_state_master <= DEQ_wait_for_encoder_2;
when DEQ_wait_for_encoder_2 =>
-- idle stage
next_state_master <= DEQ_write_back_entries;
when DEQ_lookup_old_head_ptr_idle =>
-- idle stage
next_state_master <= DEQ_lookup_old_head_ptr_finished;
when DEQ_lookup_old_head_ptr_finished =>
-- DOA has old_head_ptr entry
-- update head_ptr to be next_ptr of old head_ptr
deq_pri_entry_next <= set_head_pointer( get_next_pointer(DOA), deq_pri_entry);
next_state_master <= DEQ_write_back_entries;
when DEQ_write_back_entries =>
ADDRA <= '0' & TM2SCH_current_cpu_tid; -- setup write to update dequeue_entry
ENA <= '1';
WEA <= '1';
DIA <= dequeue_entry;
ADDRB <= "00" & get_priority(dequeue_entry); -- setup write to update deq_pri_entry
ENB <= '1';
WEB <= '1';
DIB <= deq_pri_entry;
next_state_master <= DEQ_check_encoder_output;
when DEQ_check_encoder_output =>
if (encoder_input = 0 ) then
-- No queued threads in the system: finish with invalid next thread or with idle thread if one exists
if (idle_thread_valid = '1') then
Next_Thread_Valid_next <= '1';
next_thread_id_next <= idle_thread_id;
else
Next_Thread_Valid_next <= '0';
end if;
TM_data_out <= Z32(0 to 7); -- return all 0's (success) to TM
TM_data_ready <= '1';
sched_busy_next <= '0'; -- de-assert busy signal
next_state_master <= idle;
else
-- Queued threads exist...
ADDRB <= "00" & encoder_output; -- setup read of highest priority (PRIORITY_DATA) entry
ENB <= '1';
WEB <= '0';
next_state_master <= DEQ_lookup_highest_pri_entry_idle;
end if;
when DEQ_lookup_highest_pri_entry_idle =>
-- idle stage
next_state_master <= DEQ_lookup_highest_pri_entry_finished;
when DEQ_lookup_highest_pri_entry_finished =>
next_thread_id_next <= get_head_pointer(DOB); -- store next_thread_id
TM_data_out <= Z32(0 to 7); -- return all 0's (success) to TM
TM_data_ready <= '1';
sched_busy_next <= '0'; -- de-assert busy signal
Next_Thread_Valid_next <= '1'; -- Assert that the next_thread is valid
next_state_master <= idle; -- return to idle stage
----------------------------
-- DEQ: end
----------------------------
----------------------------
-- GET_ENTRY: begin
----------------------------
when GET_ENTRY_begin =>
lookup_id_next <= Bus2IP_Addr(16 to 23); -- latch thread_id to lookup
next_state_master <= GET_ENTRY_lookup_entry;
when GET_ENTRY_lookup_entry =>
ADDRA <= '0' & lookup_id; -- setup BRAM read of lookup thread_id
ENA <= '1';
WEA <= '0';
next_state_master <= GET_ENTRY_lookup_entry_idle;
when GET_ENTRY_lookup_entry_idle =>
-- idle stage
next_state_master <= GET_ENTRY_lookup_entry_finished;
when GET_ENTRY_lookup_entry_finished =>
ENA <= '0'; -- turn off BRAM access
WEA <= '0';
bus_data_out <= DOA; -- return entry on bus
bus_data_ready <= '1';
bus_ack_ready <= '1';
next_state_master <= wait_trans_done;
----------------------------
-- GET_ENTRY: end
----------------------------
----------------------------
-- IS_QUEUED: begin
----------------------------
when IS_QUEUED_begin =>
debug_reg_next <= "00" & IS_QUEUED_OPCODE & TM2SCH_data & Z32(16 to 31); -- store debug info
sched_busy_next <= '1'; -- assert that operation is busy
lookup_id_next <= TM2SCH_data; -- latch thread_id to lookup
next_state_master <= IS_QUEUED_lookup_entry;
when IS_QUEUED_lookup_entry =>
ADDRA <= '0' & lookup_id; -- setup BRAM read of lookup thread_id
ENA <= '1';
WEA <= '0';
next_state_master <= IS_QUEUED_lookup_entry_idle;
when IS_QUEUED_lookup_entry_idle =>
-- idle stage
next_state_master <= IS_QUEUED_lookup_entry_finished;
when IS_QUEUED_lookup_entry_finished =>
ENA <= '0'; -- turn off BRAM access
WEA <= '0';
TM_data_out <= Z32(0 to 6) & get_queue_bit(DOA); -- return data to TM
TM_data_ready <= '1';
sched_busy_next <= '0'; -- de-assert busy signal
next_state_master <= idle;
----------------------------
-- IS_QUEUED: end
----------------------------
----------------------------
-- IS_EMPTY: begin
----------------------------
when IS_EMPTY_check =>
debug_reg_next <= "00" & IS_EMPTY_OPCODE & TM2SCH_data & Z32(16 to 31); -- store debug info
sched_busy_next <= '1'; -- assert that scheduler is busy
next_state_master <= IS_EMPTY_finished;
when IS_EMPTY_finished =>
-- Check to see if all queues are empty
if (encoder_input = 0) then
TM_data_out <= Z32(0 to 6) & '1'; -- set data_out to true, (LSB = 1)
else
TM_data_out <= Z32(0 to 6) & '0'; -- set data_out to false, (LSB = 0)
end if;
sched_busy_next <= '0'; --de-assert busy signal
TM_data_ready <= '1'; -- return results to TM
next_state_master <= idle;
----------------------------
-- IS_EMPTY: end
----------------------------
----------------------------
-- GET_encoder_output: begin
----------------------------
when GET_encoder_output =>
-- bus_data_out <= Z32(0 to 24)& encoder_output; -- return highest priority entry on bus
bus_data_out <= debug_reg; -- return debug reg on bus FIXME (last TM request)
bus_data_ready <= '1';
bus_ack_ready <= '1';
next_state_master <= wait_trans_done;
----------------------------
-- GET_encoder_output: end
----------------------------
----------------------------
-- SET_sched_param: begin
----------------------------
when SET_SCHED_PARAM_begin =>
debug_reg_next <= (others => '1');
temp_valid_next <= Next_Thread_Valid_reg; -- Store the current Next_Thread_Valid bit (used for restore later)
Next_Thread_Valid_next <= '0'; -- invalidate the next thread
lookup_id_next <= Bus2IP_Addr(16 to 23); -- store tid
sched_param_next <= Bus2IP_Data(0 to 31); -- store sched_param
new_priority_next <= Bus2IP_Data(25 to 31); -- store priority (low 7 bits of sched_param)
ADDRU <= '0' & Bus2IP_Addr(16 to 23); -- setup BRAM write to update sched param value in PARAM_DATA
DIU <= Bus2IP_Data(0 to 31);
ENU <= '1';
WEU <= '1';
-- Check to see if sched param is in SW-valid range
case ( Bus2IP_Data(0 to 24) ) is
when "0000000000000000000000000" => -- SW-valid range, proceed with a set_priority operation
next_state_master <= SET_SCHED_PARAM_lookup_setpri_entries_begin;
when others => -- HW-valid range, simply end, no error checks
next_state_master <= SET_SCHED_PARAM_return_with_no_error;
end case;
when SET_SCHED_PARAM_lookup_setpri_entries_begin =>
ADDRA <= '0' & lookup_id; -- setup BRAM read of thread_id to
ENA <= '1';
WEA <= '0';
ADDRB <= "00" & new_priority; -- setup BRAM read of new_priority_entry
ENB <= '1';
WEB <= '0';
SWTM_ADDRB <= '0' & lookup_id; -- setup SWTM_BRAM read of thread_id
SWTM_ENB <= '1';
SWTM_WEB <= '0';
next_state_master <= SET_SCHED_PARAM_lookup_setpri_entries_idle;
when SET_SCHED_PARAM_lookup_setpri_entries_idle =>
-- idle stage
next_state_master <= SET_SCHED_PARAM_lookup_setpri_entries_finished;
when SET_SCHED_PARAM_lookup_setpri_entries_finished =>
old_priority_next <= get_priority(DOA); -- store old_priority value
lookup_entry_next <= DOA; -- store setpri_entry
enqueue_pri_entry_next <= DOB; -- store new_priority_entry
-- Check Validity of Set_Priority operation
if ( (SWTM_DOB(26) = '1') and
( (lookup_id = TM2SCH_current_cpu_tid_reg) or
(SWTM_DOB(16 to 23) = TM2SCH_current_cpu_tid_reg)
)
) then
if(get_queue_bit(DOA) = '1') then
-- If QUEUED...
ADDRB <= "00" & get_priority(DOA); -- setup read of old_pri_entry
ENB <= '1';
WEB <= '0';
next_state_master <= SET_SCHED_PARAM_lookup_old_pri_entry_idle;
else
-- IF ~QUEUED...
ADDRA <= '0' & lookup_id; -- setup BRAM write to update priority value in THREAD_DATA
DIA <= set_priority(new_priority, DOA);
ENA <= '1';
WEA <= '1';
next_state_master <= SET_SCHED_PARAM_check_encoder;
end if;
else
-- Otherwise, return with an error b/c operation cannot be completed...
next_state_master <= SET_SCHED_PARAM_return_with_error;
end if;
when SET_SCHED_PARAM_lookup_old_pri_entry_idle =>
-- idle stage
next_state_master <= SET_SCHED_PARAM_lookup_old_pri_entry_finished;
when SET_SCHED_PARAM_lookup_old_pri_entry_finished =>
deq_pri_entry_next <= DOB; -- store old_priority_entry
next_state_master <= SET_SCHED_PARAM_priority_field_check;
when SET_SCHED_PARAM_priority_field_check =>
-- update priority value to new_priority
lookup_entry_next <= set_priority(new_priority, lookup_entry);
-- FIXME: The following bunch of IF's could be replaced by a sig_case stmt where
-- the sigs are head==tail,lookup_id=head,lookup_id=tail
-- If (head_ptr = tail_ptr) then Q will now be empty
if ( get_tail_pointer(deq_pri_entry) = get_head_pointer(deq_pri_entry) ) then
-- Clear encoder bit for given priority
encoder_input_next <= set_encoder_bit('0', conv_integer(old_priority), encoder_input);
next_state_master <= SET_SCHED_PARAM_begin_add_to_new_pri_queue;
else -- If the Q will not be empty
-- If the head is being deq'd
if ( lookup_id = get_head_pointer(deq_pri_entry) ) then
-- Setup BRAM read of old head_ptr's entry
ADDRA <= '0' & get_head_pointer(deq_pri_entry);
ENA <= '1';
WEA <= '0';
next_state_master <= SET_SCHED_PARAM_lookup_old_head_ptr_idle;
-- If the tail is being deq'd
elsif ( lookup_id = get_tail_pointer(deq_pri_entry) ) then
-- Setup BRAM read of old tail_ptr's entry
ADDRA <= '0' & get_tail_pointer(deq_pri_entry);
ENA <= '1';
WEA <= '0';
next_state_master <= SET_SCHED_PARAM_lookup_old_tail_ptr_idle;
-- If an item in the "middle" of the list is being deq'd
else
-- Setup BRAM read of prev_ptr's entry
ADDRA <= '0' & get_prev_pointer(lookup_entry);
ENA <= '1';
WEA <= '0';
next_state_master <= SET_SCHED_PARAM_lookup_prev_ptr_idle;
end if;
end if;
when SET_SCHED_PARAM_lookup_old_head_ptr_idle =>
-- idle stage
next_state_master <= SET_SCHED_PARAM_lookup_old_head_ptr_finished;
when SET_SCHED_PARAM_lookup_old_head_ptr_finished =>
-- DOA has old head_ptr entry on it
deq_pri_entry_next <= set_head_pointer(get_next_pointer(DOA), deq_pri_entry);
next_state_master <= SET_SCHED_PARAM_write_back_deq_pri_entry;
when SET_SCHED_PARAM_lookup_old_tail_ptr_idle =>
-- idle stage
next_state_master <= SET_SCHED_PARAM_lookup_old_tail_ptr_finished;
when SET_SCHED_PARAM_lookup_old_tail_ptr_finished =>
-- DOA has old tail_ptr entry on it
deq_pri_entry_next <= set_tail_pointer(get_prev_pointer(DOA), deq_pri_entry);
next_state_master <= SET_SCHED_PARAM_write_back_deq_pri_entry;
when SET_SCHED_PARAM_lookup_prev_ptr_idle =>
-- idle stage
next_state_master <= SET_SCHED_PARAM_lookup_prev_ptr_finished;
when SET_SCHED_PARAM_lookup_prev_ptr_finished =>
-- DOA has prev_ptr entry on it
-- set next_ptr of prev_ptr to that of next_ptr of setpri_entry (AKA lookup_entry)
ADDRA <= '0' & get_prev_pointer(lookup_entry);
ENA <= '1';
WEA <= '1';
DIA <= set_next_pointer(get_next_pointer(lookup_entry),DOA);
next_state_master <= SET_SCHED_PARAM_begin_add_to_new_pri_queue;
when SET_SCHED_PARAM_write_back_deq_pri_entry =>
-- Write back old_priority entry (AKA deq_pri_entry)
ADDRB <= "00" & old_priority;
ENB <= '1';
WEB <= '1';
DIB <= deq_pri_entry;
next_state_master <= SET_SCHED_PARAM_begin_add_to_new_pri_queue;
when SET_SCHED_PARAM_begin_add_to_new_pri_queue =>
-- If the new priority Q is empty...
if ( is_encoder_bit_zero(conv_integer(new_priority), encoder_input)) then
-- update head_ptr to that of lookup_id (AKA setpri_ID)
enqueue_pri_entry_next <= set_head_pointer(lookup_id, enqueue_pri_entry);
-- set encoder input bit for new_priority to '1'
encoder_input_next <= set_encoder_bit('1', conv_integer(new_priority), encoder_input);
-- now update the tail_ptr to that of lookup_id (AKA setpri_ID)
next_state_master <= SET_SCHED_PARAM_init_tail_ptr;
else -- new priority Q is not empty
-- Setup read of old tail_ptr in new Q
ADDRA <= '0' & get_tail_pointer(enqueue_pri_entry);
ENA <= '1';
WEA <= '0';
next_state_master <= SET_SCHED_PARAM_lookup_enq_old_tail_ptr_idle;
end if;
when SET_SCHED_PARAM_init_tail_ptr =>
enqueue_pri_entry_next <= set_tail_pointer(lookup_id, enqueue_pri_entry);
encoder_enable_next <= '1'; -- allow priority encoder to process, 1a
next_state_master <= SET_SCHED_PARAM_write_back_entries;
when SET_SCHED_PARAM_lookup_enq_old_tail_ptr_idle =>
-- idle stage
-- Change the prev_ptr of lookup_id (AKA setpri_ID) to that of old_tail_ptr
lookup_entry_next <= set_prev_pointer(get_tail_pointer(enqueue_pri_entry), lookup_entry);
next_state_master <= SET_SCHED_PARAM_update_enqueue_info;
when SET_SCHED_PARAM_update_enqueue_info =>
-- DOA has old tail_ptr info for new Q
-- Change & Write-back the old tail_ptr's next_ptr to that of lookup_id (AKA setpri_ID)
ADDRA <= '0' & get_tail_pointer(enqueue_pri_entry);
ENA <= '1';
WEA <= '1';
DIA <= set_next_pointer(lookup_id, DOA);
-- Update the tail_ptr of new priority Q to be that of lookup_id (AKA setpri_ID)
enqueue_pri_entry_next <= set_tail_pointer(lookup_id, enqueue_pri_entry);
encoder_enable_next <= '1'; -- allow priority encoder to process, 1b
next_state_master <= SET_SCHED_PARAM_write_back_entries;
when SET_SCHED_PARAM_write_back_entries =>
-- Write back lookup_entry (AKA setpri_entry)
ADDRA <= '0' & lookup_id;
ENA <= '1';
WEA <= '1';
DIA <= lookup_entry;
-- Write back enqueue_pri_entry (AKA new_priority_entry)
ADDRB <= "00" & new_priority;
ENB <= '1';
WEB <= '1';
DIB <= enqueue_pri_entry;
next_state_master <= SET_SCHED_PARAM_wait_for_encoder_0;
when SET_SCHED_PARAM_wait_for_encoder_0 =>
-- idle stage
next_state_master <= SET_SCHED_PARAM_wait_for_encoder_1;
when SET_SCHED_PARAM_wait_for_encoder_1 =>
-- idle stage
next_state_master <= SET_SCHED_PARAM_last_wait_0;
when SET_SCHED_PARAM_last_wait_0=>
-- idle stage
next_state_master <= SET_SCHED_PARAM_last_wait_1;
when SET_SCHED_PARAM_last_wait_1=>
-- idle stage
next_state_master <= SET_SCHED_PARAM_check_encoder;
when SET_SCHED_PARAM_check_encoder =>
-- Continue to find highest priority thread in the system...
ADDRB <= "00" & encoder_output; -- setup read of highest PRIORITY_DATA entry in system
ENB <= '1';
WEA <= '0';
ADDRA <= '0' & TM2SCH_current_cpu_tid_reg; -- setup read of currently running thread
ENA <= '1';
WEA <= '0';
next_state_master <= SET_SCHED_PARAM_lookup_highest_pri_entry_idle;
when SET_SCHED_PARAM_lookup_highest_pri_entry_idle =>
-- idle stage
next_state_master <= SET_SCHED_PARAM_lookup_highest_pri_entry_finished;
when SET_SCHED_PARAM_lookup_highest_pri_entry_finished =>
-- DOA has current thread entry
-- DOB has highest priority entry
current_entry_pri_value_next <= get_priority(DOA); -- store current_entry's priority
next_thread_id_next <= get_head_pointer(DOB); -- store next_thread_id
next_state_master <= SET_SCHED_PARAM_preemption_check;
when SET_SCHED_PARAM_preemption_check =>
-- Check if next_thread_id has "better" priority than the current_entry_pri_value
if( encoder_output < current_entry_pri_value ) then
Preemption_Interrupt_Line <= '1';
end if;
-- Late check for scheduling idle thread when encoder shows there are no
-- threads to schedule
if (encoder_input = 0) then
if (idle_thread_valid = '1') then
Next_Thread_Valid_next <= '1';
next_thread_id_next <= idle_thread_id;
else
Next_Thread_Valid_next <= '0';
end if;
else
-- There was data to process, so set thread valid
Next_Thread_Valid_next <= '1'; -- Assert that the next_thread is valid
end if;
Next_Thread_Valid_next <= '1'; -- Assert that the next_thread is valid
next_state_master <= SET_SCHED_PARAM_return_with_no_error; -- return to idle stage
when SET_SCHED_PARAM_return_with_error =>
ENA <= '0';
WEA <= '0';
debug_reg_next <= debug_reg(0 to 30) & '1';
bus_data_out <= Z32(0 to 27) & "0000"; -- return with error status (not possible with write op's, so just return all 0's)
bus_data_ready <= '1';
bus_ack_ready <= '1';
Next_Thread_Valid_next <= temp_valid; -- restore Next_Thread_Valid
next_state_master <= wait_trans_done;
when SET_SCHED_PARAM_return_with_no_error =>
ENA <= '0';
WEA <= '0';
debug_reg_next <= debug_reg(0 to 30) & '0';
bus_data_out <= Z32(0 to 27) & "0000"; -- return with successful status
bus_data_ready <= '1';
bus_ack_ready <= '1';
Next_Thread_Valid_next <= temp_valid; -- restore Next_Thread_Valid
next_state_master <= wait_trans_done;
----------------------------
-- SET_sched_param: end
----------------------------
----------------------------
-- GET_sched_param: begin
----------------------------
when GET_SCHED_PARAM_begin =>
lookup_id_next <= Bus2IP_Addr(16 to 23);
next_state_master <= GET_SCHED_PARAM_lookup_entry;
when GET_SCHED_PARAM_lookup_entry =>
ADDRU <= '0' & lookup_id; -- setup read from PARAM_DATA[tid]
ENU <= '1';
WEU <= '0';
next_state_master <= GET_SCHED_PARAM_lookup_entry_idle;
when GET_SCHED_PARAM_lookup_entry_idle =>
-- idle stage
next_state_master <= GET_SCHED_PARAM_lookup_entry_finished;
when GET_SCHED_PARAM_lookup_entry_finished =>
-- DOU has sched_param on it
bus_data_out <= DOU(0 to 31); -- return sched_param on bus and ACK
bus_data_ready <= '1';
bus_ack_ready <= '1';
next_state_master <= wait_trans_done;
----------------------------
-- GET_sched_param: end
----------------------------
----------------------------
-- CHECK_sched_param: begin
----------------------------
when CHECK_SCHED_PARAM_begin =>
lookup_id_next <= Bus2IP_Addr(16 to 23);
next_state_master <= CHECK_SCHED_PARAM_lookup_entries;
when CHECK_SCHED_PARAM_lookup_entries =>
ADDRA <= '0' & lookup_id; -- Setup read from THREAD_DATA[tid]
ENA <= '1';
WEA <= '0';
ADDRU <= '0' & lookup_id; -- Setup read from PARAM_DATA[tid]
ENU <= '1';
WEU <= '0';
SWTM_ADDRB <= '0' & lookup_id; -- Setup read from SWTM_DATA[tid]
SWTM_ENB <= '1';
SWTM_WEB <= '0';
next_state_master <= CHECK_SCHED_PARAM_lookup_entries_idle;
when CHECK_SCHED_PARAM_lookup_entries_idle =>
-- idle stage
next_state_master <= CHECK_SCHED_PARAM_lookup_entries_finished;
when CHECK_SCHED_PARAM_lookup_entries_finished =>
-- DOA, DOU, and SWTM DOB have entries on them
-- Error check for properness of sched_param:
-- * If queued : sched_param must in the SW-valid range (less than 128)
-- * If not-queued : sched param can be in any range
if(get_queue_bit(DOA) = '1') then
-- thread is QUEUED
-- then check to see if Most Significant 25 bits of sched_param are 0's => in SW-valid range
case ( DOU(0 to 24) ) is
when "0000000000000000000000000" => -- SW-valid range, return all 0's
bus_data_out <= Z32(0 to 31);
when others => -- Not in SW-valid range, return LSB=1, error bit
bus_data_out <= Z32(0 to 30) & '1';
end case;
else
-- thread is ~QUEUED, return all 0's
bus_data_out <= Z32(0 to 31);
end if;
bus_data_ready <= '1'; -- ACK Bus, with data put on it
bus_ack_ready <= '1';
next_state_master <= wait_trans_done;
----------------------------
-- CHECK_sched_param: end
----------------------------
----------------------------
-- SET_IDLE_THREAD: begin
----------------------------
when SET_IDLE_THREAD_begin =>
lookup_id_next <= Bus2IP_Addr(16 to 23); -- store thread_id
ADDRA <= '0' & Bus2IP_Addr(16 to 23); -- setup BRAM read of THREAD_DATA[tid]
ENA <= '1';
WEA <= '0';
ADDRU <= '0' & Bus2IP_Addr(16 to 23); -- setup BRAM read of PARAM_DATA[tid]
ENU <= '1';
WEU <= '0';
SWTM_ADDRB <= '0' & Bus2IP_Addr(16 to 23); -- setup SWTM_BRAM read of thread_id to set_pri
SWTM_ENB <= '1';
SWTM_WEB <= '0';
next_state_master <= SET_IDLE_THREAD_lookup_entries_idle;
when SET_IDLE_THREAD_lookup_entries_idle =>
-- idle stage
next_state_master <= SET_IDLE_THREAD_lookup_entries_finished;
when SET_IDLE_THREAD_lookup_entries_finished =>
-- Check to see if this thread can become the idle thread
-- * TID must be ~queued
-- * TID must be created and used.
-- * TID must not have a HW sched param.
if ( get_queue_bit(DOA) = '0' and
SWTM_DOB(26) = '1' and
DOU(0 to 24) = "0000000000000000000000000"
) then
idle_thread_id_next <= lookup_id;
idle_thread_valid_next <= '1';
next_state_master <= SET_IDLE_THREAD_return_with_no_error;
else
-- This thread cannot become the idle thread
next_state_master <= SET_IDLE_THREAD_return_with_error;
end if;
when SET_IDLE_THREAD_return_with_error =>
bus_data_out <= Z32(0 to 30) & '1'; -- return LSB=1, error bit, on bus and ACK
bus_data_ready <= '1';
bus_ack_ready <= '1';
next_state_master <= wait_trans_done;
when SET_IDLE_THREAD_return_with_no_error =>
-- FIXME: this if statement and body may not be needed (idle thread should be set up at all times)
-- If there is not a next thread ready to run, then make the newly set idle thread ready to run.
if (Next_Thread_Valid_reg = '0') then
Next_Thread_Valid_next <= '1';
next_thread_id_next <= idle_thread_id;
end if;
bus_data_out <= Z32(0 to 31); -- return all 0's on bus and ACK
bus_data_ready <= '1';
bus_ack_ready <= '1';
next_state_master <= wait_trans_done;
----------------------------
-- SET_IDLE_THREAD: end
----------------------------
when others =>
ENA <= '0'; -- turn off any BRAM access
WEA <= '0';
ENB <= '0';
WEB <= '0';
ENU <= '0';
WEU <= '0';
next_state_master <= idle;
end case; -- END CASE (current_state_master)
end process MASTER_FSM_LOGIC_PROC;
end architecture IMP;
|
bsd-3-clause
|
masson2013/heterogeneous_hthreads
|
src/hardware/XilinxProcessorIP/pcores/opb_ac97_v1_00_a/hdl/vhdl/ac97_model.vhd
|
7
|
14137
|
-------------------------------------------------------------------------------
-- ac97_model.vhd
-------------------------------------------------------------------------------
--
-- Mike Wirthlin
--
-------------------------------------------------------------------------------
-- Filename: ac97_model.vhd
--
-- Description:
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
--use ieee.numeric_std.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use std.TextIO.all;
entity ac97_model is
generic (
BIT_CLK_STARTUP_TIME : time := 1 us
);
port (
AC97Reset_n : in std_logic;
Bit_Clk : out std_logic;
Sync : in std_logic;
SData_Out : in std_logic;
SData_In : out std_logic
);
end entity ac97_model;
library opb_ac97_v2_00_a;
use opb_ac97_v2_00_a.all;
use opb_ac97_v2_00_a.testbench_ac97_package.all;
architecture model of ac97_model is
signal reset_delay : std_logic := '1';
signal initial_reset : std_logic := '0';
signal bit_clk_i, bit_clk_freq : std_logic;
signal sync_d, end_of_frame, end_of_slot : std_logic;
signal frame_count : integer := 1;
signal valid_frame,codec_rdy : std_logic := '0';
signal shift_reg_in, shift_reg_out : std_logic_vector(19 downto 0) := (others => '0');
signal left_in_data, right_in_data : std_logic_vector(15 downto 0);
signal register_control_valid, register_data_valid : std_logic;
signal register_write, register_read : std_logic := '0';
signal register_address : std_logic_vector(6 downto 0) := (others => '0');
signal slot0_in : std_logic_vector(15 downto 0) := (others => '0');
signal slot1_in : std_logic_vector(19 downto 0) := (others => '0');
signal slot2_in : std_logic_vector(19 downto 0) := (others => '0');
signal slot3_in : std_logic_vector(19 downto 0) := (others => '0');
signal slot4_in : std_logic_vector(19 downto 0) := (others => '0');
signal slot0_out : std_logic_vector(15 downto 0) := (others => '0');
signal slot1_out : std_logic_vector(19 downto 0):= (others => '0');
signal slot2_out : std_logic_vector(19 downto 0):= (others => '0');
signal slot3_out : std_logic_vector(19 downto 0):= (others => '0');
signal slot4_out : std_logic_vector(19 downto 0) := (others => '0');
signal slot_counter : integer;
signal bit_counter : integer;
--
type register_type is array(0 to 63) of std_logic_vector(15 downto 0);
signal ac97_registers : register_type := (
X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000",
X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000",
X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000",
X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000",
X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000",
X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000",
X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000",
X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000", X"0000"
);
type audio_type is array(0 to 15) of std_logic_vector(15 downto 0);
signal record_values : audio_type := (
X"1234", X"2345", X"3456", X"4567", X"5678", X"6789", X"789a", X"89ab",
X"1234", X"2345", X"3456", X"4567", X"5678", X"6789", X"789a", X"89ab"
);
signal record_value : unsigned(19 downto 0) := X"00010";
signal record_sample_counter : integer := 0;
signal temp_record_sample_count : integer := 0;
signal temp_play_sample_count : integer := 0;
signal valid_record_data : std_logic := '0';
signal request_play_data : std_logic := '0';
constant sample_skip : integer := 3; -- skip every 3rd sample
begin
-----------------------------------------------------------------------------
-- Clock
-----------------------------------------------------------------------------
-- simulate a 12.8? MHz ac97 clk
ac97_clk_freq_PROCESS: process
begin
Bit_Clk_freq <= '0';
wait for 40.69 ns;
Bit_Clk_freq <= '1';
wait for 40.69 ns;
end process ac97_clk_freq_PROCESS;
process (ac97reset_n)
begin
if ac97reset_n = '0' and ac97reset_n'event then
initial_reset <= '1';
end if;
end process;
-- Delay state machine to simulate a delay on the bit clock
reset_delay <= transport AC97Reset_n after BIT_CLK_STARTUP_TIME;
-- Gated bit clock signal
Bit_Clk_i <= Bit_Clk_freq when reset_delay = '1' and ac97reset_n = '1'
and initial_reset = '1'
else '0';
bit_clk <= bit_clk_i;
-----------------------------------------------------------------------------
-- Receiving shift register
-----------------------------------------------------------------------------
process (bit_clk_i)
begin
if (bit_clk_i = '0' and bit_clk_i'event) then
shift_reg_out <= shift_reg_out(18 downto 0) & sdata_out;
end if;
end process;
process (bit_clk_i)
begin
if (bit_clk_i = '0' and bit_clk_i'event) then
if (bit_counter = 0) then
if (slot_counter = 1) then
slot0_out <= shift_reg_out(15 downto 0);
elsif (slot_counter = 2) then
slot1_out <= shift_reg_out;
elsif (slot_counter = 3) then
slot2_out <= shift_reg_out;
elsif (slot_counter = 4) then
slot3_out <= shift_reg_out;
elsif (slot_counter = 5) then
slot4_out <= shift_reg_out;
end if;
end if;
end if;
end process;
register_control_valid <= slot0_out(14) and slot0_out(15);
register_data_valid <= slot0_out(13) and slot0_out(15);
register_address <= slot1_out(18 downto 12);
register_write <= register_control_valid and (not slot1_out(19));
register_read <= register_control_valid and slot1_out(19);
-----------------------------------------------------------------------------
-- Register return data interface
-----------------------------------------------------------------------------
process (bit_clk_i)
variable my_line : LINE;
begin
if bit_clk_i = '1' and bit_clk_i'event and end_of_slot = '1'
and slot_counter = 5 then
if register_read = '1' then
slot2_in <= X"A55A0"; -- send sample data
slot0_in(13) <= '1';
write(my_line, string'("CODEC: Reading from address "));
write(my_line, bit_vector'( To_bitvector( register_address) ));
writeline(output, my_line);
else
slot2_in <= (others => '0');
slot0_in(13) <= '0';
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- Register write
-----------------------------------------------------------------------------
process (bit_clk_i)
variable my_line : LINE;
begin
if bit_clk_i = '1' and bit_clk_i'event and end_of_slot = '1'
and slot_counter = 5 then
if register_write = '1' then
write(my_line, string'("CODEC: Writing value "));
write(my_line, bit_vector'( To_bitvector( slot2_out(19 downto 4))));
write(my_line, string'(" to address "));
write(my_line, bit_vector'( To_bitvector( register_address) ));
writeline(output, my_line);
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- Slot in
-----------------------------------------------------------------------------
slot0_in(15) <= codec_rdy;
slot0_in(14) <= register_control_valid; -- mimic register command
-- slot_in(13) set by register return state machine
slot0_in(12) <= valid_record_data; -- valid PCM
slot0_in(11) <= valid_record_data; -- valid PCM
slot0_in(10 downto 0) <= (others => '0');
slot1_in <= '0' & register_address &
(not request_play_data) & (not request_play_data) & "0000000000";
-----------------------------------------------------------------------------
-- Play Data
-----------------------------------------------------------------------------
process (bit_clk_i)
variable my_line : LINE;
begin
if ac97reset_n = '0' then
request_play_data <= '0';
temp_play_sample_count <= 0;
elsif bit_clk_i = '1' and bit_clk_i'event and end_of_slot = '1'
and slot_counter = 6 then
temp_play_sample_count <= temp_play_sample_count + 1;
if temp_play_sample_count = sample_skip then
temp_play_sample_count <= 0;
request_play_data <= '0';
else
request_play_data <= '1';
end if;
end if;
end process;
process (bit_clk_i)
variable my_line : LINE;
begin
if bit_clk_i = '1' and bit_clk_i'event and end_of_slot = '1'
and slot_counter = 5 then
if request_play_data = '1' then
write(my_line, string'("CODEC: Playback Left="));
write(my_line, bit_vector'( To_bitvector( slot3_out ) ));
write(my_line, string'(" Playback Right="));
write(my_line, bit_vector'( To_bitvector( slot4_out ) ));
writeline(output, my_line);
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- Record Data
-----------------------------------------------------------------------------
process (bit_clk_i)
variable my_line : LINE;
begin
if ac97reset_n = '0' then
slot3_in <= (others => '0');
slot4_in <= (others => '0');
valid_record_data <= '0';
elsif bit_clk_i = '1' and bit_clk_i'event and end_of_slot = '1'
and slot_counter = 5 then
temp_record_sample_count <= temp_record_sample_count + 1;
if temp_record_sample_count = sample_skip then
temp_record_sample_count <= 0;
slot3_in <= X"00000";
slot4_in <= X"00000";
valid_record_data <= '0';
else
slot3_in <= CONV_STD_LOGIC_VECTOR(record_value,20);
slot4_in <= CONV_STD_LOGIC_VECTOR(record_value,20);
record_value <= record_value + 16;
valid_record_data <= '1';
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- Sending shift register
-----------------------------------------------------------------------------
process (bit_clk_i)
begin
if ac97reset_n = '0' then
shift_reg_in <= (others => '0');
elsif (bit_clk_i = '1' and bit_clk_i'event) then
if end_of_slot = '1' then
case slot_counter is
when 12 => -- slot 0
shift_reg_in <= slot0_in & "0000";
when 0 => -- slot 1
shift_reg_in <= slot1_in;
when 1 =>
shift_reg_in <= slot2_in;
when 2 =>
shift_reg_in <= slot3_in;
when 3 =>
shift_reg_in <= slot4_in;
when others =>
shift_reg_in <= (others => '0');
end case;
else
shift_reg_in <= shift_reg_in(18 downto 0) & '0';
end if;
end if;
end process;
SData_In <= shift_reg_in(19);
-----------------------------------------------------------------------------
-- Codec Ready
-----------------------------------------------------------------------------
process(bit_clk_i)
begin
if (AC97Reset_n = '0') then
codec_rdy <= '0';
elsif (bit_clk_i = '1' and bit_clk_i'event) then
if codec_rdy = '0' and end_of_frame = '1' and valid_frame = '1' then
codec_rdy <= '1';
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- Valid frame checker
-----------------------------------------------------------------------------
process(bit_clk_i)
begin
if (AC97Reset_n = '0') then
valid_frame <= '0';
frame_count <= 0;
elsif (bit_clk_i = '1' and bit_clk_i'event) then
if end_of_frame = '1' then
if (frame_count = 255) then
valid_frame <= '1';
else
valid_frame <= '0';
end if;
frame_count <= 0;
else
frame_count <= frame_count + 1;
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- End of frame set by sync
-----------------------------------------------------------------------------
process(bit_clk_i)
begin
if (bit_clk_i = '1' and bit_clk_i'event) then
sync_d <= sync;
end if;
end process;
end_of_frame <= sync and (not sync_d);
-----------------------------------------------------------------------------
-- slot_counter & bit_counter state machine
-----------------------------------------------------------------------------
end_of_slot <= '1' when ((slot_counter = 0 and bit_counter = 15) or
bit_counter = 19)
else '0';
process (bit_clk_i)
begin
if (AC97Reset_n = '0') then
bit_counter <= 0;
slot_counter <= 0;
elsif (bit_clk_i = '1' and bit_clk_i'event) then
-- wait for sync to initialize sequence
if (end_of_frame = '1') then
slot_counter <= 0;
bit_counter <= 0;
else
if end_of_slot = '1' then
bit_counter <= 0;
if slot_counter = 12 then
slot_counter <= 0;
else
slot_counter <= slot_counter + 1;
end if;
else
bit_counter <= bit_counter +1;
end if;
end if;
end if;
end process;
end architecture model;
|
bsd-3-clause
|
masson2013/heterogeneous_hthreads
|
src/hardware/MyRepository/pcores/plb_thread_manager_v1_00_a/devl/bfmsim/pcores/plb_thread_manager_tb_v1_00_a/simhdl/vhdl/plb_thread_manager_tb.vhd
|
3
|
14573
|
------------------------------------------------------------------------------
--
-- This vhdl module is a template for creating IP testbenches using the IBM
-- BFM toolkits. It provides a fixed interface to the subsystem testbench.
--
-- DO NOT CHANGE THE entity name, architecture name, generic parameter
-- declaration or port declaration of this file. You may add components,
-- instances, constants, signals, etc. as you wish.
--
-- See IBM Bus Functional Model Toolkit User's Manual for more information
-- on the BFMs.
--
------------------------------------------------------------------------------
-- plb_thread_manager_tb.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: plb_thread_manager_tb.vhd
-- Version: 1.00.a
-- Description: IP testbench
-- Date: Tue Apr 14 15:01:55 2009 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library plb_thread_manager_v1_00_a;
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
entity plb_thread_manager_tb is
------------------------------------------
-- DO NOT CHANGE THIS GENERIC DECLARATION
------------------------------------------
generic
(
-- Bus protocol parameters, do not add to or delete
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_SPLB_AWIDTH : integer := 32;
C_SPLB_DWIDTH : integer := 128;
C_SPLB_NUM_MASTERS : integer := 8;
C_SPLB_MID_WIDTH : integer := 3;
C_SPLB_NATIVE_DWIDTH : integer := 32;
C_SPLB_P2P : integer := 0;
C_SPLB_SUPPORT_BURSTS : integer := 0;
C_SPLB_SMALLEST_MASTER : integer := 32;
C_SPLB_CLK_PERIOD_PS : integer := 10000;
C_INCLUDE_DPHASE_TIMER : integer := 0;
C_FAMILY : string := "virtex5"
);
------------------------------------------
-- DO NOT CHANGE THIS PORT DECLARATION
------------------------------------------
port
(
-- PLB (v4.6) bus interface, do not add or delete
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to C_SPLB_MID_WIDTH-1);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to C_SPLB_DWIDTH/8-1);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to C_SPLB_DWIDTH-1);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to C_SPLB_DWIDTH-1);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MWrErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MRdErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MIRQ : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
-- BFM synchronization bus interface
SYNCH_IN : in std_logic_vector(0 to 31) := (others => '0');
SYNCH_OUT : out std_logic_vector(0 to 31) := (others => '0')
);
end entity plb_thread_manager_tb;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture testbench of plb_thread_manager_tb is
--USER testbench signal declarations added here as you wish
------------------------------------------
-- Standard constants for bfl/vhdl communication
------------------------------------------
constant NOP : integer := 0;
constant START : integer := 1;
constant STOP : integer := 2;
constant WAIT_IN : integer := 3;
constant WAIT_OUT : integer := 4;
constant ASSERT_IN : integer := 5;
constant ASSERT_OUT : integer := 6;
constant ASSIGN_IN : integer := 7;
constant ASSIGN_OUT : integer := 8;
constant RESET_WDT : integer := 9;
constant INTERRUPT : integer := 31;
begin
------------------------------------------
-- Instance of IP under test.
-- Communication with the BFL is by using SYNCH_IN/SYNCH_OUT signals.
------------------------------------------
UUT : entity plb_thread_manager_v1_00_a.plb_thread_manager
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
--USER generics mapped here
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_BASEADDR => C_BASEADDR,
C_HIGHADDR => C_HIGHADDR,
C_SPLB_AWIDTH => C_SPLB_AWIDTH,
C_SPLB_DWIDTH => C_SPLB_DWIDTH,
C_SPLB_NUM_MASTERS => C_SPLB_NUM_MASTERS,
C_SPLB_MID_WIDTH => C_SPLB_MID_WIDTH,
C_SPLB_NATIVE_DWIDTH => C_SPLB_NATIVE_DWIDTH,
C_SPLB_P2P => C_SPLB_P2P,
C_SPLB_SUPPORT_BURSTS => C_SPLB_SUPPORT_BURSTS,
C_SPLB_SMALLEST_MASTER => C_SPLB_SMALLEST_MASTER,
C_SPLB_CLK_PERIOD_PS => C_SPLB_CLK_PERIOD_PS,
C_INCLUDE_DPHASE_TIMER => C_INCLUDE_DPHASE_TIMER,
C_FAMILY => C_FAMILY
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
--USER ports mapped here
-- MAP USER PORTS ABOVE THIS LINE ------------------
SPLB_Clk => SPLB_Clk,
SPLB_Rst => SPLB_Rst,
PLB_ABus => PLB_ABus,
PLB_UABus => PLB_UABus,
PLB_PAValid => PLB_PAValid,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_masterID => PLB_masterID,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_MSize => PLB_MSize,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_lockErr => PLB_lockErr,
PLB_wrDBus => PLB_wrDBus,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendPri => PLB_rdPendPri,
PLB_reqPri => PLB_reqPri,
PLB_TAttribute => PLB_TAttribute,
Sl_addrAck => Sl_addrAck,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MBusy => Sl_MBusy,
Sl_MWrErr => Sl_MWrErr,
Sl_MRdErr => Sl_MRdErr,
Sl_MIRQ => Sl_MIRQ
);
------------------------------------------
-- Zero out the unused synch_out bits
------------------------------------------
SYNCH_OUT(10 to 31) <= (others => '0');
------------------------------------------
-- Test bench code itself
--
-- The test bench itself can be arbitrarily complex and may include
-- hierarchy as the designer sees fit
------------------------------------------
TEST_PROCESS : process
begin
SYNCH_OUT(NOP) <= '0';
SYNCH_OUT(START) <= '0';
SYNCH_OUT(STOP) <= '0';
SYNCH_OUT(WAIT_IN) <= '0';
SYNCH_OUT(WAIT_OUT) <= '0';
SYNCH_OUT(ASSERT_IN) <= '0';
SYNCH_OUT(ASSERT_OUT) <= '0';
SYNCH_OUT(ASSIGN_IN) <= '0';
SYNCH_OUT(ASSIGN_OUT) <= '0';
SYNCH_OUT(RESET_WDT) <= '0';
-- initializations
-- wait for reset to stabalize after power-up
wait for 200 ns;
-- wait for end of reset
wait until (SPLB_Rst'EVENT and SPLB_Rst = '0');
assert FALSE report "*** Real simulation starts here ***" severity NOTE;
-- wait for reset to be completed
wait for 200 ns;
------------------------------------------
-- Test User Logic Slave Register
------------------------------------------
-- send out start signal to begin testing ...
wait until (SPLB_Clk'EVENT and SPLB_Clk = '1');
SYNCH_OUT(START) <= '1';
assert FALSE report "*** Start User Logic Slave Register Test ***" severity NOTE;
wait until (SPLB_Clk'EVENT and SPLB_Clk = '1');
SYNCH_OUT(START) <= '0';
-- wait stop signal for end of testing ...
wait until (SYNCH_IN(STOP)'EVENT and SYNCH_IN(STOP) = '1');
assert FALSE report "*** User Logic Slave Register Test Complete ***" severity NOTE;
wait for 1 us;
------------------------------------------
-- Test User I/Os and other features
------------------------------------------
--USER code added here to stimulate any user I/Os
wait;
end process TEST_PROCESS;
end architecture testbench;
|
bsd-3-clause
|
masson2013/heterogeneous_hthreads
|
src/hardware/XilinxProcessorIP/pcores/opb_ac97_v1_00_a/hdl/vhdl/ac97_if.vhd
|
7
|
11332
|
-------------------------------------------------------------------------------
-- Filename: ac97_fifo.vhd
--
-- Description: This module provides a simple FIFO interface for the AC97
-- module and provides an asyncrhonous interface for a
-- higher level module that is not synchronous with the AC97
-- clock (Bit_Clk).
--
-- This module will handle all of the initial commands
-- for the AC97 interface.
--
-- This module provides a bus independent interface so the
-- module can be used for more than one bus interface.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- ac97_core
-- ac97_timing
-- srl_fifo
--
-------------------------------------------------------------------------------
-- Author: Mike Wirthlin
-- Revision: $$
-- Date: $$
--
-- History:
-- Mike Wirthlin
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library opb_ac97_v2_00_a;
use opb_ac97_v2_00_a.all;
entity ac97_if is
port (
ClkIn : in std_logic;
Reset : in std_logic;
-- All signals synchronous to ClkIn
PCM_Playback_Left: in std_logic_vector(15 downto 0);
PCM_Playback_Right: in std_logic_vector(15 downto 0);
PCM_Playback_Accept: out std_logic;
PCM_Record_Left: out std_logic_vector(15 downto 0);
PCM_Record_Right: out std_logic_vector(15 downto 0);
PCM_Record_Valid: out std_logic;
Debug : out std_logic_Vector(3 downto 0);
AC97Reset_n : out std_logic; -- AC97Clk
AC97Clk : in std_logic;
Sync : out std_logic;
SData_Out : out std_logic;
SData_In : in std_logic
);
end entity ac97_if;
library opb_ac97_v2_00_a;
use opb_ac97_v2_00_a.all;
library unisim;
use unisim.all;
architecture IMP of ac97_if is
component ac97_core is
generic (
C_PCM_DATA_WIDTH : integer := 16
);
port (
Reset : in std_logic;
-- signals attaching directly to AC97 codec
AC97_Bit_Clk : in std_logic;
AC97_Sync : out std_logic;
AC97_SData_Out : out std_logic;
AC97_SData_In : in std_logic;
-- AC97 register interface
AC97_Reg_Addr : in std_logic_vector(0 to 6);
AC97_Reg_Write_Data : in std_logic_vector(0 to 15);
AC97_Reg_Read_Data : out std_logic_vector(0 to 15);
AC97_Reg_Read_Strobe : in std_logic; -- initiates a "read" command
AC97_Reg_Write_Strobe : in std_logic; -- initiates a "write" command
AC97_Reg_Busy : out std_logic;
AC97_Reg_Error : out std_logic;
AC97_Reg_Read_Data_Valid : out std_logic;
-- Playback signal interface
PCM_Playback_Left: in std_logic_vector(0 to C_PCM_DATA_WIDTH-1);
PCM_Playback_Right: in std_logic_vector(0 to C_PCM_DATA_WIDTH-1);
PCM_Playback_Left_Valid: in std_logic;
PCM_Playback_Right_Valid: in std_logic;
PCM_Playback_Left_Accept: out std_logic;
PCM_Playback_Right_Accept: out std_logic;
-- Record signal interface
PCM_Record_Left: out std_logic_vector(0 to C_PCM_DATA_WIDTH-1);
PCM_Record_Right: out std_logic_vector(0 to C_PCM_DATA_WIDTH-1);
PCM_Record_Left_Valid: out std_logic;
PCM_Record_Right_Valid: out std_logic;
--
CODEC_RDY : out std_logic
);
end component ac97_core;
component ac97_command_rom is
port (
ClkIn : in std_logic;
ROMAddr : in std_logic_vector(3 downto 0);
ROMData : out std_logic_vector(24 downto 0)
);
end component ac97_command_rom;
signal pcm_playback_accept_ac97clk : std_logic;
signal pcm_playback_accept_ClkIn_0 : std_logic;
signal pcm_playback_accept_ClkIn_1 : std_logic;
signal pcm_playback_accept_ClkIn : std_logic;
signal pcm_record_valid_ac97clk, pcm_record_valid_ClkIn_0, pcm_record_valid_ClkIn_1 : std_logic;
signal pcm_record_valid_ClkIn : std_logic;
signal command_addr : std_logic_vector(6 downto 0);
signal write_data : std_logic_vector(15 downto 0);
signal read_data : std_logic_vector(15 downto 0);
signal codec_rdy : std_logic;
signal debug_i : std_logic_vector(3 downto 0);
signal reg_write_strobe_ac97, reg_busy_ac97, reg_error_ac97 : std_logic;
signal get_next_command : std_logic;
signal valid_command : std_logic;
signal command_num : unsigned(3 downto 0) := "0000";
type read_access_states is (AC97_READY, WARM_START,
REVIEW_COMMAND,ISSUE_COMMAND,
WAIT_COMMAND, NEXT_COMMAND,
READ_COMMAND, DONE);
signal command_SM : read_access_states;
signal reset_counter : unsigned(10 downto 0) := (others => '0');
signal AC97Reset_n_i : std_logic := '0';
signal rom_data : std_logic_vector(24 downto 0);
signal command_addr_i : std_logic_Vector(3 downto 0);
signal start_frame_delay : natural range 0 to 3 := 0;
attribute rom_style: string;
--attribute rom_style of ac97_command_rom: entity is "distributed";
begin -- architecture IMP
-----------------------------------------------------------------------------
-- Command loading
-----------------------------------------------------------------------------
load_commands_SM_PROCESS : process (AC97clk) is
begin
if AC97clk'event and AC97clk = '1' then
if Reset = '1' then
command_SM <= AC97_READY;
command_num <= "0000";
else
case command_SM is
-- Issue some reset?
when AC97_READY =>
-- wait until codec is ready
if codec_rdy = '1' then
command_SM <= REVIEW_COMMAND;
start_frame_delay <= 0;
end if;
when WARM_START =>
if pcm_playback_accept_ac97clk = '1' then
if start_frame_delay = 3 then
command_SM <= REVIEW_COMMAND;
else
start_frame_delay <= start_frame_delay + 1;
end if;
end if;
when REVIEW_COMMAND =>
-- if command is valid, go on to issue command. otherwise, go to
-- end state.
if valid_command = '1' then
command_SM <= ISSUE_COMMAND;
else
command_SM <= DONE;
end if;
when ISSUE_COMMAND =>
-- strobe is issued in output forming logic
command_SM <= WAIT_COMMAND;
when WAIT_COMMAND =>
if reg_busy_ac97 = '0' then
command_SM <= NEXT_COMMAND;
end if;
-- error processing?
when NEXT_COMMAND =>
command_SM <= READ_COMMAND;
command_num <= command_num + 1;
when READ_COMMAND =>
command_SM <= REVIEW_COMMAND;
when DONE =>
-- do nothing
when others => NULL;
end case;
end if;
end if;
end process;
reg_write_strobe_ac97 <= '1' when command_SM = ISSUE_COMMAND else
'0';
get_next_command <= '1' when command_SM = NEXT_COMMAND else
'0';
-- ClkIn processes
-- The AC97 reset signal needs to be driven by ClkIn
-- (AC97 clock does not operate when reset asserted)
reset_process : process (ClkIn) is
begin
if Reset = '1' then
reset_counter <= (others => '0');
AC97Reset_n_i <= '0';
elsif ClkIn'event and ClkIn='1' then
if reset_counter(10) = '1' then
AC97Reset_n_i <= '1';
else
reset_counter <= reset_counter+1;
AC97Reset_n_i <= '0';
end if;
end if;
end process;
AC97Reset_n <= AC97Reset_n_i;
process (ClkIn)
begin
if ClkIn'event and ClkIn='1' then
pcm_playback_accept_ClkIn_0 <= pcm_playback_accept_ac97clk; -- async
pcm_playback_accept_ClkIn_1 <= pcm_playback_accept_ClkIn_0;
pcm_playback_accept_ClkIn <= pcm_playback_accept_ClkIn_0 and not pcm_playback_accept_ClkIn_1;
end if;
end process;
PCM_Playback_Accept <= pcm_playback_accept_ClkIn;
process (ClkIn)
begin
if ClkIn'event and ClkIn='1' then
pcm_record_valid_ClkIn_0 <= pcm_record_valid_ac97clk; -- async
pcm_record_valid_ClkIn_1 <= pcm_record_valid_ClkIn_0;
pcm_record_valid_ClkIn <= pcm_record_valid_ClkIn_0 and not pcm_record_valid_ClkIn_1;
end if;
end process;
PCM_Record_Valid <= pcm_record_valid_ClkIn;
-----------------------------------------------------------------------------
-- Command ROM
-----------------------------------------------------------------------------
ROM : ac97_command_rom
port map (
ClkIn => AC97Clk,
ROMAddr => command_addr_i,
ROMData => rom_data
);
command_addr_i <= CONV_STD_LOGIC_VECTOR(command_num, 4);
write_data <= rom_data(15 downto 0);
command_addr <= rom_data(22 downto 16);
valid_command <= rom_data(24);
-- debug_i(0) <= codec_rdy;
-- debug_i(1) <= '1' when command_SM = DONE else
-- '0';
-- debug_i(2) <= AC97Reset_n_i;
-- debug_i(3) <= reg_error_ac97;
debug_i <= command_addr_i;
debug <= debug_i;
-----------------------------------------------------------------------------
-- Instantiating the core
-----------------------------------------------------------------------------
ac97_core_I : ac97_core
port map (
Reset => Reset,
AC97_Bit_Clk => AC97Clk,
AC97_Sync => Sync,
AC97_SData_Out => SData_Out,
AC97_SData_In => SData_In,
AC97_Reg_Addr => command_addr,
AC97_Reg_Write_Data => write_data,
AC97_Reg_Read_Data => open, -- No reading from AC97
AC97_Reg_Read_Strobe => '0', -- No reading from AC97
AC97_Reg_Write_Strobe => reg_write_strobe_ac97, -- do
AC97_Reg_Busy => reg_busy_ac97, -- do
AC97_Reg_Error => reg_error_ac97, -- do
AC97_Reg_Read_Data_Valid => open, -- No reading from AC97
PCM_Playback_Left => PCM_Playback_Left, -- async
PCM_Playback_Right => PCM_Playback_right, -- async
PCM_Playback_Left_Valid => '1',
PCM_Playback_Right_Valid => '1',
PCM_Playback_Left_Accept => pcm_playback_accept_ac97clk,
PCM_Playback_Right_Accept => open, -- use left_accept
PCM_Record_Left => PCM_Record_Left,
PCM_Record_Right => PCM_Record_Right,
PCM_Record_Left_Valid => pcm_record_valid_ac97clk,
PCM_Record_Right_Valid => open, -- use left_valid
CODEC_RDY => codec_rdy
);
-- leds(3) <= not codec_rdy; -- and (command_SM = DONE);
-- leds(2) <= '0' when command_SM = INIT else '1';
-- leds(1) <= '0';
-- leds(0) <= AC97Clk; -- '0' when command_SM = DONE else '1';
end architecture IMP;
|
bsd-3-clause
|
masson2013/heterogeneous_hthreads
|
src/platforms/xilinx/smp3_opbhwti/design/pcores/ipif_common_v1_00_d/hdl/vhdl/burst_size_calc.vhd
|
3
|
15480
|
-------------------------------------------------------------------------------
-- $Id: burst_size_calc.vhd,v 1.5 2003/10/22 15:06:35 ostlerf Exp $
-------------------------------------------------------------------------------
-- Burst Size Calculation
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: burst_size_calc.vhd
-- Version:
--------------------------------------------------------------------------------
-- Description: This module calculates the size to use for a dma transfer.
-- The main complications are that for Rx channels the minimum
-- of LENGTH and PLENGTH must be used instead of LENGTH and
-- that for the last transfer there may be a need to round up
-- to include bytes that are insufficient to reach a unit of
-- C_BYTES_PER_SINGLE_TRANSFER.
--
-------------------------------------------------------------------------------
-- Structure:
-- burst_size_calc.vhd
-------------------------------------------------------------------------------
-- Author: FO
--
-- History:
--
-- FO 05/09/2003 -- First version
--
-- FLO 05/14/2003
-- ^^^^^^
-- Removed the pipe stage between LENGTH_cco comparison to
-- PLENGTH_cco and thre rest of the logic.
-- Corrected the high-order bits of MstNum from '1' to '0'.
-- ~~~~~~
-- FLO 05/14/2003
-- ^^^^^^
-- Removed C_DMA_ALLOW_BURST; case is now handled as
-- C_DMA_BURST_SIZE = 1.
-- Added the option to handle the remainder (the amount left
-- to be moved by DMA when it is less than a full burst) as
-- a succession of single transactions rather than as a
-- short burst. This adds generic C_DMA_SHORT_BURST_REMAINDER
-- to the parameters. So, these options are now available:
--
-- 1. Single transactions only when C_DMA_BURST_SIZE = 1.
-- 2. Burst transactions, with remainders as singles when
-- C_DMA_BURST_SIZE > 1 and
-- C_DMA_SHORT_BURST_REMAINDER= false.
-- 3. Burst transactions, with remainders as short burst when
-- C_DMA_BURST_SIZE > 1 and
-- C_DMA_SHORT_BURST_REMAINDER = true.
-- ~~~~~~
-- FLO 06/26/2003
-- ^^^^^^
-- Implemented XST WA for G.23 that was communicated by XST team.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library proc_common_v1_00_b;
use proc_common_v1_00_b.proc_common_pkg.log2;
entity burst_size_calc is
generic (
C_LENGTH_WIDTH : positive := 11;
C_MSTNUM_WIDTH : positive := 5;
C_DMA_BURST_SIZE : positive := 16;
C_BYTES_PER_SINGLE_TRANSFER : positive := 4;
C_DMA_SHORT_BURST_REMAINDER : integer := 0
);
port (
Bus2IP_Clk : in std_logic;
LENGTH_cco : in std_logic_vector(0 to C_LENGTH_WIDTH-1);
PLENGTH_cco : in std_logic_vector(0 to C_LENGTH_WIDTH-1);
Rx_cco : in std_logic;
MstNum : out std_logic_vector(0 to C_MSTNUM_WIDTH-1)
);
-- Operational constraints:
-- - PLENGTH_cco is used only for Rx channels and for Rx channels, it is
-- assumed that LENGTH_cco decrements if and only if PLENGTH_cco decrements
-- by the same ammount. Thus, the relationship LENGTH_cco < PLENGTH_cco
-- remains invariant as these quantities change value.
-- - C_BYTES_PER_SINGLE_TRANSFER must be a power of two.
constant TPB : positive := C_DMA_BURST_SIZE; -- Transfers Per Burst
constant BPST : positive := C_BYTES_PER_SINGLE_TRANSFER;
constant BPST_BITS : natural := log2(BPST);
end burst_size_calc;
library unisim;
--use unisim.all;
use unisim.VCOMPONENTS.all;
library ieee;
use ieee.numeric_std.UNSIGNED;
use ieee.numeric_std.TO_UNSIGNED;
library proc_common_v1_00_b;
use proc_common_v1_00_b.or_muxcy;
architecture imp of burst_size_calc is
type bo2sl_type is array (boolean) of std_logic;
constant bo2sl : bo2sl_type := ('0', '1');
-- Number of of high-order bits that give a length in
-- units of single transfers (units of the bus width).
-- LW_STU stands for LENGTH_WIDTH in Single Transfer Units.
constant LW_STU : positive := C_LENGTH_WIDTH-BPST_BITS;
constant TPB_U : UNSIGNED(0 to LW_STU-1)
:= (TO_UNSIGNED(TPB, LW_STU));
constant TPB_BITS : natural := log2(TPB+1); -- 0 to TPB values to encode
signal pl_gte_l : std_logic; -- PLENGTH_cco >= LENGTH_cco (forced
-- to true when not Rx_cco, which
-- causes PLENGTH_cco to be ignored
-- in downstream calculations).
signal pl_gte_l_d1 : std_logic;
signal min_pl_l_gte_tpb : std_logic; -- min(PLENGTH_cco, LENGTH_cco) is
-- greater than or equal to TPB
signal min_pl_l_minus_tpb : std_logic_vector(0 to C_LENGTH_WIDTH-1);
-- min(PLENGTH_cco, LENGTH_cco) - TPB
component or_muxcy is
generic (
C_NUM_BITS : integer := 8
);
port (
In_bus : in std_logic_vector(0 to C_NUM_BITS-1);
Or_out : out std_logic
);
end component or_muxcy;
begin
DISALLOW_BURST_GEN: if C_DMA_BURST_SIZE = 1 generate
begin
MstNum <= std_logic_vector(TO_UNSIGNED(1, MstNum'length));
end generate;
ALLOW_BURST_GEN: if C_DMA_BURST_SIZE > 1 generate ---(
begin
-- indentation waived
PL_GTE_L_BLOCK: block ---(
signal brw_n : std_logic_vector(0 to C_LENGTH_WIDTH);
signal lut : std_logic_vector(0 to C_LENGTH_WIDTH-1);
signal mult_and : std_logic_vector(0 to C_LENGTH_WIDTH-1);
begin
--------------------------------------------------------------------------
-- This block assigns:
--
-- pl_gte_l <= not Rx_cco or bo2sl( PLENGTH_cco(0 to C_LENGTH_WIDTH-1)
-- > LENGTH_cco(0 to C_LENGTH_WIDTH-1)
-- );
--------------------------------------------------------------------------
brw_n(brw_n'right) <= '1';
PL_GTE_L_BIT_GEN: for i in C_LENGTH_WIDTH-1 downto 0 generate
begin
lut(i) <= not (Rx_cco and LENGTH_cco(i))
xor PLENGTH_cco(i);
--
-- When Rx_cco = '1', then the minimum of LENGTH_cco and
-- PLENGTH_cco is used in the calculation of the burst
-- size. Otherwise, only LENGTH_cco is used. A little trick
-- is used to assure that LENGTH_cco is used when Rx_cco = '0'.
-- The trick is that PLENGTH_cco is compared with a
-- forced zero, assuring that pl_gte_l is true and that
-- LENGTH_cco will be used in the next stage.
----------------------------------------------------------------------
-- brw_n(i) <= (not lut(i) and not mult_and(i)) or
-- ( lut(i) and brw_n(i+1));
----------------------------------------------------------------------
I_MUXCY: MUXCY
port map (
DI => PLENGTH_cco(i),
CI => brw_n(i+1),
S => lut(i),
O => brw_n(i)
);
end generate;
pl_gte_l <= brw_n(0);
end block; ---)
PL_GTE_L_D1_PROC: process(Bus2IP_Clk)
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
pl_gte_l_d1 <= pl_gte_l;
end if;
end process;
MIN_PL_L_MINUS_TPB_BLOCK: block ---(
signal brw_n : std_logic_vector(0 to C_LENGTH_WIDTH);
signal lut : std_logic_vector(0 to C_LENGTH_WIDTH-1);
constant TPBB_U : UNSIGNED(0 to C_LENGTH_WIDTH-1)
:= (TO_UNSIGNED(TPB*BPST, C_LENGTH_WIDTH));
signal lut_tmp1 : std_logic_vector(0 to C_LENGTH_WIDTH-1); --XST WA for G.23
signal lut_tmp2 : std_logic_vector(0 to C_LENGTH_WIDTH-1); --XST WA for G.23
begin
brw_n(brw_n'length-1) <= '1';
MIN_PL_L_MINUS_TPB_BIT_GEN: for i in C_LENGTH_WIDTH-1 downto 0 generate
begin
-- lut(i) <= ( ( pl_gte_l_d1 and LENGTH_cco(i))
-- or (not pl_gte_l_d1 and PLENGTH_cco(i))
-- )
-- xor not TPBB_U(i);
-------------------
-- The above, using a cycle-delayed pl_gte_l may not
-- be permissable because MstNum likely is used
-- in state DONECHK when on the cycle right after cco changes.
lut_tmp1(i) <= not TPBB_U(i); --XST WA for G.23
lut_tmp2(i) <= ( ( pl_gte_l and LENGTH_cco(i))
or (not pl_gte_l and PLENGTH_cco(i))
);
lut(i) <= lut_tmp2(i)
xor lut_tmp1(i);
-- lut(i) <= ( ( pl_gte_l and LENGTH_cco(i))
-- or (not pl_gte_l and PLENGTH_cco(i))
-- )
-- xor not TPBB_U(i);
----------------------------------------------------------------------
-- brw_n(i) <= (not lut(i) and not TPBB_U(i)) or (lut(i) and brw_n(i+1));
----------------------------------------------------------------------
I_MUXCY: MUXCY
port map (
DI => (not TPBB_U(i)),
CI => brw_n(i+1),
S => lut(i),
O => brw_n(i)
);
----------------------------------------------------------------------
-- min_pl_l_minus_tpb(i) <= lut(i) xor brw_n(i+1);
----------------------------------------------------------------------
I_XORCY: XORCY
port map (
LI => lut(i),
CI => brw_n(i+1),
O => min_pl_l_minus_tpb(i)
);
end generate;
min_pl_l_gte_tpb <= brw_n(0);
end block; ---)
MSTNUM_SINGLES_REM_GEN:
if C_DMA_SHORT_BURST_REMAINDER = 0 generate ---(
begin
MstNum <= std_logic_vector(TO_UNSIGNED(TPB, MstNum'length))
when min_pl_l_gte_tpb = '1' else
std_logic_vector(TO_UNSIGNED(1, MstNum'length));
end generate; ---)
MSTNUM_BURST_REM_GEN:
if C_DMA_SHORT_BURST_REMAINDER = 1 generate ---(
signal cry : std_logic_vector(0 to TPB_BITS);
signal lut : std_logic_vector(0 to TPB_BITS-1);
signal min_pl_l_lt_tpb : std_logic;
signal mult_and_out : std_logic_vector(0 to TPB_BITS-1);
signal has_partial_bpst: std_logic; -- min(PLENGTH_cco, LENGTH_cco)
-- divided by BPST leaves a non-zero
-- remainder.
signal mplmt_a : std_logic_vector(0 to TPB_BITS-1);
signal mstnum_a : std_logic_vector(0 to TPB_BITS-1);
constant tpb_a : std_logic_vector(0 to TPB_BITS-1)
:= std_logic_vector(TO_UNSIGNED(TPB, TPB_BITS));
begin
I_HAS_PARTIAL_BPST : or_muxcy
generic map (
C_NUM_BITS => BPST_BITS
)
port map (
In_bus => min_pl_l_minus_tpb(C_LENGTH_WIDTH-BPST_BITS to
C_LENGTH_WIDTH-1),
Or_out => has_partial_bpst
);
mplmt_a <= min_pl_l_minus_tpb(C_LENGTH_WIDTH-TPB_BITS-BPST_BITS to
C_LENGTH_WIDTH-BPST_BITS-1);
min_pl_l_lt_tpb <= not min_pl_l_gte_tpb;
cry(cry'right) <= has_partial_bpst and min_pl_l_lt_tpb;
MSTNUM_BIT_GEN: for i in TPB_BITS-1 downto 0 generate
begin
----------------------------------------------------------------------
lut(i) <= ( min_pl_l_lt_tpb -- Use "amount left" if it is < TPB.
and ( mplmt_a(i) -- Reconstruct "amount left" by
xor tpb_a(i)) -- adding back TPB.
)
or ( not min_pl_l_lt_tpb
and tpb_a(i) -- Use TPB if "amount left" >= TPB
);
----------------------------------------------------------------------
-- mult_and_out(i) <= min_pl_l_lt_tpb and mplmt_a(i);
----------------------------------------------------------------------
I_MULT_AND: MULT_AND
port map (
LO => mult_and_out(i),
I1 => min_pl_l_lt_tpb,
I0 => mplmt_a(i)
);
----------------------------------------------------------------------
-- cry(i) <= (not lut(i) and mult_and_out(i)) or (lut(i) and cry(i+1));
----------------------------------------------------------------------
I_MUXCY: MUXCY
port map (
DI => mult_and_out(i),
CI => cry(i+1),
S => lut(i),
O => cry(i)
);
----------------------------------------------------------------------
-- mstnum_a(i) <= lut(i) xor cry(i+1);
----------------------------------------------------------------------
I_XORCY: XORCY
port map (
LI => lut(i),
CI => cry(i+1),
O => mstnum_a(i)
);
end generate;
MstNum(C_MSTNUM_WIDTH-TPB_BITS to C_MSTNUM_WIDTH-1) <= mstnum_a;
XST_NULL_SLICE_WORKAROUND_MSTNUM_HIGH_BITS_GEN:
if C_MSTNUM_WIDTH > TPB_BITS generate
MstNum(0 to C_MSTNUM_WIDTH-TPB_BITS-1) <= (others => '0');
end generate;
end generate; ---)
-- indentation waived
end generate; ---)
end imp;
|
bsd-3-clause
|
masson2013/heterogeneous_hthreads
|
src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/opb_v20_v1_10_d/hdl/vhdl/srl_fifo3.vhd
|
3
|
13894
|
-------------------------------------------------------------------------------
-- $Id: srl_fifo3.vhd,v 1.1.2.1 2009/10/06 21:15:02 gburch Exp $
-------------------------------------------------------------------------------
-- srl_fifo3 - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2002,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: srl_fifo3.vhd
--
-- Description: same as srl_fifo except the Addr port has the correct bit
-- ordering, there is a true FIFO_Empty port, and the C_DEPTH
-- generic actually controlls how many elements the fifo will
-- hold (up to 16). includes an assertion statement to check
-- that C_DEPTH is less than or equal to 16. changed
-- C_DATA_BITS to C_DWIDTH and changed it from natural to
-- positive (the width should be 1 or greater, zero width
-- didn't make sense to me!). Changed C_DEPTH from natural
-- to positive (zero elements doesn't make sense).
-- The Addr port in srl_fifo has the bits reversed which
-- made it more difficult to use. C_DEPTH was not used in
-- srl_fifo. Data_Exists is delayed by one clock so it is
-- not usefull for generating an empty flag. FIFO_Empty is
-- generated directly from the address, the same way that
-- FIFO_Full is generated.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl_fifo3.vhd
--
-------------------------------------------------------------------------------
-- Author: jam
--
-- History:
-- jam 02/20/02 First Version - modified from original srl_fifo
--
-- DCW 2002-03-12 Structural implementation of synchronous reset for
-- Data_Exists DFF (using FDR)
-- jam 04/12/02 Added C_XON generic for mixed vhdl/verilog sims
--
-- als 2002-04-18 added default for XON generic in SRL16E, FDRE, and FDR
-- component declarations
-- jam 2002-05-01 changed FIFO_Empty output from buffer_Empty, which had a
-- clock delay, to the not of data_Exists_I, which doesn't
-- have any delay
-- als 01/19/04 added FIFO_AlmostEmpty output from the not of next_data_exists
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
library unisim;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all; -- conv_std_logic_vector
use unisim.vcomponents.all;
entity srl_fifo3 is
generic (
C_DWIDTH : positive := 8; -- changed to positive
C_DEPTH : positive := 16; -- changed to positive
C_XON : boolean := false -- added for mixed mode sims
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DWIDTH-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
FIFO_Full : out std_logic;
FIFO_Empty : out std_logic;
FIFO_AlmostEmpty : out std_logic; -- new port
Data_Exists : out std_logic;
Addr : out std_logic_vector(0 to 3)
);
end entity srl_fifo3;
architecture imp of srl_fifo3 is
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- convert C_DEPTH to a std_logic_vector so FIFO_Full can be generated
-- based on the selected depth rather than fixed at 16
constant DEPTH : std_logic_vector(0 to 3) :=
conv_std_logic_vector(C_DEPTH-1,4);
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
signal addr_i : std_logic_vector(0 to 3);
signal buffer_Full : std_logic;
signal buffer_Empty : std_logic;
signal next_Data_Exists : std_logic;
signal data_Exists_I : std_logic;
signal valid_Write : std_logic;
signal hsum_A : std_logic_vector(0 to 3);
signal sum_A : std_logic_vector(0 to 3);
signal addr_cy : std_logic_vector(0 to 4);
-------------------------------------------------------------------------------
-- Begin Architecture
-------------------------------------------------------------------------------
begin -- architecture IMP
-- C_DEPTH is positive so that ensures the fifo is at least 1 element deep
-- make sure it is not greater than 16 locations deep
-- pragma translate_off
assert C_DEPTH <= 16
report "SRL Fifo's must be 16 or less elements deep"
severity FAILURE;
-- pragma translate_on
-- since srl16 address is 3 downto 0 need to compare individual bits
-- didn't muck with addr_i since the basic addressing works - Addr output
-- is generated correctly below
buffer_Full <= '1' when (addr_i(0) = DEPTH(3) and
addr_i(1) = DEPTH(2) and
addr_i(2) = DEPTH(1) and
addr_i(3) = DEPTH(0)
) else '0';
FIFO_Full <= buffer_Full;
buffer_Empty <= '1' when (addr_i = "0000") else '0';
FIFO_Empty <= not data_Exists_I; -- generate a true empty flag with no delay
-- was buffer_Empty, which had a clock dly
next_Data_Exists <= (data_Exists_I and not buffer_Empty) or
(buffer_Empty and FIFO_Write) or
(data_Exists_I and not FIFO_Read);
FIFO_AlmostEmpty <= not(next_Data_Exists);
Data_Exists_DFF : FDR
port map (
Q => data_Exists_I, -- [out std_logic]
C => Clk, -- [in std_logic]
D => next_Data_Exists, -- [in std_logic]
R => Reset); -- [in std_logic]
Data_Exists <= data_Exists_I;
valid_Write <= FIFO_Write and (FIFO_Read or not buffer_Full);
addr_cy(0) <= valid_Write;
Addr_Counters : for I in 0 to 3 generate
hsum_A(I) <= (FIFO_Read xor addr_i(I)) and (FIFO_Write or not buffer_Empty);
MUXCY_L_I : MUXCY_L
port map (
DI => addr_i(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
S => hsum_A(I), -- [in std_logic]
LO => addr_cy(I+1)); -- [out std_logic]
XORCY_I : XORCY
port map (
LI => hsum_A(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
O => sum_A(I)); -- [out std_logic]
FDRE_I : FDRE
port map (
Q => addr_i(I), -- [out std_logic]
C => Clk, -- [in std_logic]
CE => data_Exists_I, -- [in std_logic]
D => sum_A(I), -- [in std_logic]
R => Reset); -- [in std_logic]
end generate Addr_Counters;
FIFO_RAM : for I in 0 to C_DWIDTH-1 generate
SRL16E_I : SRL16E
-- pragma translate_off
generic map (
INIT => x"0000")
-- pragma translate_on
port map (
CE => valid_Write, -- [in std_logic]
D => Data_In(I), -- [in std_logic]
Clk => Clk, -- [in std_logic]
A0 => addr_i(0), -- [in std_logic]
A1 => addr_i(1), -- [in std_logic]
A2 => addr_i(2), -- [in std_logic]
A3 => addr_i(3), -- [in std_logic]
Q => Data_Out(I)); -- [out std_logic]
end generate FIFO_RAM;
-------------------------------------------------------------------------------
-- INT_ADDR_PROCESS
-------------------------------------------------------------------------------
-- This process assigns the internal address to the output port
-------------------------------------------------------------------------------
-- modified the process to flip the bits since the address bits from the
-- srl16 are 3 downto 0 and Addr needs to be 0 to 3
INT_ADDR_PROCESS:process (addr_i)
begin -- process
for i in Addr'range
loop
Addr(i) <= addr_i(3 - i); -- flip the bits to account for srl16 addr
end loop;
end process;
end architecture imp;
|
bsd-3-clause
|
masson2013/heterogeneous_hthreads
|
src/platforms/xilinx/smp3_opbhwti/design/pcores/opb_v20_v1_10_d/hdl/vhdl/srl_fifo3.vhd
|
3
|
13894
|
-------------------------------------------------------------------------------
-- $Id: srl_fifo3.vhd,v 1.1.2.1 2009/10/06 21:15:02 gburch Exp $
-------------------------------------------------------------------------------
-- srl_fifo3 - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2002,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: srl_fifo3.vhd
--
-- Description: same as srl_fifo except the Addr port has the correct bit
-- ordering, there is a true FIFO_Empty port, and the C_DEPTH
-- generic actually controlls how many elements the fifo will
-- hold (up to 16). includes an assertion statement to check
-- that C_DEPTH is less than or equal to 16. changed
-- C_DATA_BITS to C_DWIDTH and changed it from natural to
-- positive (the width should be 1 or greater, zero width
-- didn't make sense to me!). Changed C_DEPTH from natural
-- to positive (zero elements doesn't make sense).
-- The Addr port in srl_fifo has the bits reversed which
-- made it more difficult to use. C_DEPTH was not used in
-- srl_fifo. Data_Exists is delayed by one clock so it is
-- not usefull for generating an empty flag. FIFO_Empty is
-- generated directly from the address, the same way that
-- FIFO_Full is generated.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl_fifo3.vhd
--
-------------------------------------------------------------------------------
-- Author: jam
--
-- History:
-- jam 02/20/02 First Version - modified from original srl_fifo
--
-- DCW 2002-03-12 Structural implementation of synchronous reset for
-- Data_Exists DFF (using FDR)
-- jam 04/12/02 Added C_XON generic for mixed vhdl/verilog sims
--
-- als 2002-04-18 added default for XON generic in SRL16E, FDRE, and FDR
-- component declarations
-- jam 2002-05-01 changed FIFO_Empty output from buffer_Empty, which had a
-- clock delay, to the not of data_Exists_I, which doesn't
-- have any delay
-- als 01/19/04 added FIFO_AlmostEmpty output from the not of next_data_exists
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
library unisim;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all; -- conv_std_logic_vector
use unisim.vcomponents.all;
entity srl_fifo3 is
generic (
C_DWIDTH : positive := 8; -- changed to positive
C_DEPTH : positive := 16; -- changed to positive
C_XON : boolean := false -- added for mixed mode sims
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DWIDTH-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
FIFO_Full : out std_logic;
FIFO_Empty : out std_logic;
FIFO_AlmostEmpty : out std_logic; -- new port
Data_Exists : out std_logic;
Addr : out std_logic_vector(0 to 3)
);
end entity srl_fifo3;
architecture imp of srl_fifo3 is
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- convert C_DEPTH to a std_logic_vector so FIFO_Full can be generated
-- based on the selected depth rather than fixed at 16
constant DEPTH : std_logic_vector(0 to 3) :=
conv_std_logic_vector(C_DEPTH-1,4);
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
signal addr_i : std_logic_vector(0 to 3);
signal buffer_Full : std_logic;
signal buffer_Empty : std_logic;
signal next_Data_Exists : std_logic;
signal data_Exists_I : std_logic;
signal valid_Write : std_logic;
signal hsum_A : std_logic_vector(0 to 3);
signal sum_A : std_logic_vector(0 to 3);
signal addr_cy : std_logic_vector(0 to 4);
-------------------------------------------------------------------------------
-- Begin Architecture
-------------------------------------------------------------------------------
begin -- architecture IMP
-- C_DEPTH is positive so that ensures the fifo is at least 1 element deep
-- make sure it is not greater than 16 locations deep
-- pragma translate_off
assert C_DEPTH <= 16
report "SRL Fifo's must be 16 or less elements deep"
severity FAILURE;
-- pragma translate_on
-- since srl16 address is 3 downto 0 need to compare individual bits
-- didn't muck with addr_i since the basic addressing works - Addr output
-- is generated correctly below
buffer_Full <= '1' when (addr_i(0) = DEPTH(3) and
addr_i(1) = DEPTH(2) and
addr_i(2) = DEPTH(1) and
addr_i(3) = DEPTH(0)
) else '0';
FIFO_Full <= buffer_Full;
buffer_Empty <= '1' when (addr_i = "0000") else '0';
FIFO_Empty <= not data_Exists_I; -- generate a true empty flag with no delay
-- was buffer_Empty, which had a clock dly
next_Data_Exists <= (data_Exists_I and not buffer_Empty) or
(buffer_Empty and FIFO_Write) or
(data_Exists_I and not FIFO_Read);
FIFO_AlmostEmpty <= not(next_Data_Exists);
Data_Exists_DFF : FDR
port map (
Q => data_Exists_I, -- [out std_logic]
C => Clk, -- [in std_logic]
D => next_Data_Exists, -- [in std_logic]
R => Reset); -- [in std_logic]
Data_Exists <= data_Exists_I;
valid_Write <= FIFO_Write and (FIFO_Read or not buffer_Full);
addr_cy(0) <= valid_Write;
Addr_Counters : for I in 0 to 3 generate
hsum_A(I) <= (FIFO_Read xor addr_i(I)) and (FIFO_Write or not buffer_Empty);
MUXCY_L_I : MUXCY_L
port map (
DI => addr_i(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
S => hsum_A(I), -- [in std_logic]
LO => addr_cy(I+1)); -- [out std_logic]
XORCY_I : XORCY
port map (
LI => hsum_A(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
O => sum_A(I)); -- [out std_logic]
FDRE_I : FDRE
port map (
Q => addr_i(I), -- [out std_logic]
C => Clk, -- [in std_logic]
CE => data_Exists_I, -- [in std_logic]
D => sum_A(I), -- [in std_logic]
R => Reset); -- [in std_logic]
end generate Addr_Counters;
FIFO_RAM : for I in 0 to C_DWIDTH-1 generate
SRL16E_I : SRL16E
-- pragma translate_off
generic map (
INIT => x"0000")
-- pragma translate_on
port map (
CE => valid_Write, -- [in std_logic]
D => Data_In(I), -- [in std_logic]
Clk => Clk, -- [in std_logic]
A0 => addr_i(0), -- [in std_logic]
A1 => addr_i(1), -- [in std_logic]
A2 => addr_i(2), -- [in std_logic]
A3 => addr_i(3), -- [in std_logic]
Q => Data_Out(I)); -- [out std_logic]
end generate FIFO_RAM;
-------------------------------------------------------------------------------
-- INT_ADDR_PROCESS
-------------------------------------------------------------------------------
-- This process assigns the internal address to the output port
-------------------------------------------------------------------------------
-- modified the process to flip the bits since the address bits from the
-- srl16 are 3 downto 0 and Addr needs to be 0 to 3
INT_ADDR_PROCESS:process (addr_i)
begin -- process
for i in Addr'range
loop
Addr(i) <= addr_i(3 - i); -- flip the bits to account for srl16 addr
end loop;
end process;
end architecture imp;
|
bsd-3-clause
|
masson2013/heterogeneous_hthreads
|
src/hardware/MyRepository/pcores/hw_threads/hw_acc_v1_00_a/hdl/vhdl/user_logics/stress/join_1.vhd
|
2
|
21015
|
---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
FUNCTION_EXIT,
STATE_1,
STATE_2,
STATE_3,
STATE_4,
STATE_5,
STATE_6,
STATE_7,
STATE_8,
STATE_9,
STATE_10,
STATE_11,
STATE_12,
STATE_13,
STATE_14,
STATE_15,
STATE_16,
STATE_17,
STATE_18,
STATE_19,
STATE_20,
STATE_21,
STATE_22,
STATE_23,
STATE_24,
STATE_25,
STATE_26,
STATE_27,
STATE_28,
STATE_29,
STATE_30,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_STATE_1 : std_logic_vector(0 to 15) := x"0101";
constant U_STATE_2 : std_logic_vector(0 to 15) := x"0102";
constant U_STATE_3 : std_logic_vector(0 to 15) := x"0103";
constant U_STATE_4 : std_logic_vector(0 to 15) := x"0104";
constant U_STATE_5 : std_logic_vector(0 to 15) := x"0105";
constant U_STATE_6 : std_logic_vector(0 to 15) := x"0106";
constant U_STATE_7 : std_logic_vector(0 to 15) := x"0107";
constant U_STATE_8 : std_logic_vector(0 to 15) := x"0108";
constant U_STATE_9 : std_logic_vector(0 to 15) := x"0109";
constant U_STATE_10 : std_logic_vector(0 to 15) := x"0110";
constant U_STATE_11 : std_logic_vector(0 to 15) := x"0111";
constant U_STATE_12 : std_logic_vector(0 to 15) := x"0112";
constant U_STATE_13 : std_logic_vector(0 to 15) := x"0113";
constant U_STATE_14 : std_logic_vector(0 to 15) := x"0114";
constant U_STATE_15 : std_logic_vector(0 to 15) := x"0115";
constant U_STATE_16 : std_logic_vector(0 to 15) := x"0116";
constant U_STATE_17 : std_logic_vector(0 to 15) := x"0117";
constant U_STATE_18 : std_logic_vector(0 to 15) := x"0118";
constant U_STATE_19 : std_logic_vector(0 to 15) := x"0119";
constant U_STATE_20 : std_logic_vector(0 to 15) := x"0120";
constant U_STATE_21 : std_logic_vector(0 to 15) := x"0121";
constant U_STATE_22 : std_logic_vector(0 to 15) := x"0122";
constant U_STATE_23 : std_logic_vector(0 to 15) := x"0123";
constant U_STATE_24 : std_logic_vector(0 to 15) := x"0124";
constant U_STATE_25 : std_logic_vector(0 to 15) := x"0125";
constant U_STATE_26 : std_logic_vector(0 to 15) := x"0126";
constant U_STATE_27 : std_logic_vector(0 to 15) := x"0127";
constant U_STATE_28 : std_logic_vector(0 to 15) := x"0128";
constant U_STATE_29 : std_logic_vector(0 to 15) := x"0129";
constant U_STATE_30 : std_logic_vector(0 to 15) := x"0130";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
--signal retVal, retVal_next : std_logic_vector(0 to 31);
signal arg, arg_next : std_logic_vector(0 to 31);
signal reg1, reg1_next : std_logic_vector(0 to 31);
signal reg2, reg2_next : std_logic_vector(0 to 31);
signal reg3, reg3_next : std_logic_vector(0 to 31);
signal reg4, reg4_next : std_logic_vector(0 to 31);
signal reg5, reg5_next : std_logic_vector(0 to 31);
signal reg6, reg6_next : std_logic_vector(0 to 31);
--signal reg7, reg7_next : std_logic_vector(0 to 31);
--signal reg8, reg8_next : std_logic_vector(0 to 31);
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock, intrfc2thrd_goWait) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
return_state <= return_state_next;
--retVal <= retVal_next;
arg <= arg_next;
reg1 <= reg1_next;
reg2 <= reg2_next;
reg3 <= reg3_next;
reg4 <= reg4_next;
reg5 <= reg5_next;
reg6 <= reg6_next;
--reg7 <= reg7_next;
--reg8 <= reg8_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_STATE_1 =>
current_state <= STATE_1;
when U_STATE_2 =>
current_state <= STATE_2;
when U_STATE_3 =>
current_state <= STATE_3;
when U_STATE_4 =>
current_state <= STATE_4;
when U_STATE_5 =>
current_state <= STATE_5;
when U_STATE_6 =>
current_state <= STATE_6;
when U_STATE_7 =>
current_state <= STATE_7;
when U_STATE_8 =>
current_state <= STATE_8;
when U_STATE_9 =>
current_state <= STATE_9;
when U_STATE_10 =>
current_state <= STATE_10;
when U_STATE_11 =>
current_state <= STATE_11;
when U_STATE_12 =>
current_state <= STATE_12;
when U_STATE_13 =>
current_state <= STATE_13;
when U_STATE_14 =>
current_state <= STATE_14;
when U_STATE_15 =>
current_state <= STATE_15;
when U_STATE_16 =>
current_state <= STATE_16;
when U_STATE_17 =>
current_state <= STATE_17;
when U_STATE_18 =>
current_state <= STATE_18;
when U_STATE_19 =>
current_state <= STATE_19;
when U_STATE_20 =>
current_state <= STATE_20;
when U_STATE_21 =>
current_state <= STATE_21;
when U_STATE_22 =>
current_state <= STATE_22;
when U_STATE_23 =>
current_state <= STATE_23;
when U_STATE_24 =>
current_state <= STATE_24;
when U_STATE_25 =>
current_state <= STATE_25;
when U_STATE_26 =>
current_state <= STATE_26;
when U_STATE_27 =>
current_state <= STATE_27;
when U_STATE_28 =>
current_state <= STATE_28;
when U_STATE_29 =>
current_state <= STATE_29;
when U_STATE_30 =>
current_state <= STATE_30;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
--retVal_next <= retVal;
arg_next <= arg;
reg1_next <= reg1;
reg2_next <= reg2;
reg3_next <= reg3;
reg4_next <= reg4;
reg5_next <= reg5;
reg6_next <= reg6;
--reg7_next <= reg7;
--reg8_next <= reg8;
-----------------------------------------------------------------------
-- Testcase: join_1_stress
-- reg1 = numberOfTestsToComplete
-- reg2 = * numberOfTestsCompleted
-- reg3 = * function
-- reg4 = thread
-- reg5 = i
-- reg6 = joinReturn
-----------------------------------------------------------------------
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
-- hthread_attr_t * attr = (hthread_attr_t *) arg
when FUNCTION_START =>
-- Pop the argument
thrd2intrfc_value <= Z32;
thrd2intrfc_opcode <= OPCODE_POP;
next_state <= WAIT_STATE;
return_state_next <= STATE_1;
when STATE_1 =>
arg_next <= intrfc2thrd_value;
-- Read the address of numberOfTestsToComplete
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= intrfc2thrd_value;
next_state <= WAIT_STATE;
return_state_next <= STATE_2;
when STATE_2 =>
-- Read the value of numberOfTestsToComplete
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= intrfc2thrd_value;
next_state <= WAIT_STATE;
return_state_next <= STATE_3;
when STATE_3 =>
reg1_next <= intrfc2thrd_value;
-- Read the address of numberOfTestsCompleted
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + 4;
next_state <= WAIT_STATE;
return_state_next <= STATE_4;
when STATE_4 =>
reg2_next <= intrfc2thrd_value;
-- Read the address of function
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + 8;
next_state <= WAIT_STATE;
return_state_next <= STATE_5;
--joinValue = SUCCESS
-- for( i=0; i<*(data->numberOfTestsTocomplete); i++ )
when STATE_5 =>
reg3_next <= intrfc2thrd_value;
reg5_next <= Z32;
reg6_next <= Z32;
next_state <= STATE_6;
when STATE_6 =>
-- Do the comparision between i and toBeCompleted
if ( reg5 < reg1 ) then
next_state <= STATE_7;
else
next_state <= STATE_13;
end if;
when STATE_7 =>
next_state <= STATE_8;
-- createReturn == hthread_create( &(data->threads[i]), NULL, data->function, NULL );
when STATE_8 =>
-- push NULL
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= Z32;
next_state <= WAIT_STATE;
return_state_next <= STATE_9;
when STATE_9 =>
-- push data->function
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg3;
next_state <= WAIT_STATE;
return_state_next <= STATE_10;
when STATE_10 =>
-- push NULL
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= Z32;
next_state <= WAIT_STATE;
return_state_next <= STATE_11;
when STATE_11 =>
-- push &( data->threads[i] )
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg + x"0000000C" + ( reg5(2 to 31) & "00" );
next_state <= WAIT_STATE;
return_state_next <= STATE_12;
when STATE_12 =>
-- call create
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_CREATE;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_6;
next_state <= WAIT_STATE;
-- increment i
reg5_next <= reg5 + "x00000001";
-- END OF FOR LOOP
-- for( i=0; i<*(data->numberOfTestsTocomplete); i++ )
when STATE_13 =>
reg5_next <= Z32;
next_state <= STATE_14;
when STATE_14 =>
-- Do the comparision between i and toBeCompleted
if ( reg5 < reg1 ) then
next_state <= STATE_15;
else
next_state <= STATE_;
end if;
-- hthread_join( data->thread[i], NULL );
when STATE_15 =>
-- read the value of data->thread[i]
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + x"0000000C" + ( reg5(2 to 31) & "00" );
next_state <= WAIT_STATE;
return_state_next <= STATE_16;
when STATE_16 =>
reg4_next <= intrfc2thrd_value;
-- push NULL
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= Z32;
next_state <= WAIT_STATE;
return_state_next <= STATE_17;
when STATE_17 =>
-- push thread
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg4;
next_state <= WAIT_STATE;
return_state_next <= STATE_18;
when STATE_18 =>
-- call hthread_join
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_JOIN;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_19;
next_state <= WAIT_STATE;
when STATE_15 =>
-- Read the value of numberOfTestsCompleted
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= reg2;
next_state <= WAIT_STATE;
return_state_next <= STATE_16;
reg5_next <= reg5 + x"00000001";
when STATE_16 =>
thrd2intrfc_opcode <= OPCODE_STORE;
thrd2intrfc_address <= reg2;
thrd2intrfc_value <= intrfc2thrd_value + x"00000001";
next_state <= WAIT_STATE;
return_state_next <= STATE_6;
-- for( i=0; i< *(data->numberOfTestsCompleted); i++ );
when STATE_17 =>
-- set i to 0
reg5_next <= Z32;
-- Read the value of numberOfTestsCompleted
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= reg2;
next_state <= WAIT_STATE;
return_state_next <= STATE_24;
when STATE_18 =>
reg6_next <= intrfc2thrd_value;
next_state <= STATE_19;
when STATE_19 =>
-- compare i and numberOfTestsComplted
if ( reg5 < reg6 ) then
next_state <= STATE_20;
else
next_state <=FUNCTION_EXIT;
end if;
when STATE_24 =>
reg5_next <= reg5 + x"00000001";
next_state <= STATE_19;
when FUNCTION_EXIT =>
--Same as hthread_exit( (void *) retVal );
thrd2intrfc_value <= Z32;
thrd2intrfc_opcode <= OPCODE_RETURN;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
|
bsd-3-clause
|
masson2013/heterogeneous_hthreads
|
src/hardware/MyRepository/pcores/axi_hthread_cores/axi_sync_manager_v1_00_a/hdl/vhdl/mutex_store.vhd
|
11
|
7532
|
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use work.common.all;
entity mutex_store is
generic
(
C_AWIDTH : integer := 32;
C_DWIDTH : integer := 32;
C_TWIDTH : integer := 8;
C_MWIDTH : integer := 6;
C_CWIDTH : integer := 8
);
port
(
clk : in std_logic;
rst : in std_logic;
miaddr : in std_logic_vector(0 to C_MWIDTH-1);
miena : in std_logic;
miwea : in std_logic;
miowner : in std_logic_vector(0 to C_TWIDTH-1);
minext : in std_logic_vector(0 to C_TWIDTH-1);
milast : in std_logic_vector(0 to C_TWIDTH-1);
mikind : in std_logic_vector(0 to 1);
micount : in std_logic_vector(0 to C_CWIDTH-1);
sysrst : in std_logic;
rstdone : out std_logic;
moowner : out std_logic_vector(0 to C_TWIDTH-1);
monext : out std_logic_vector(0 to C_TWIDTH-1);
molast : out std_logic_vector(0 to C_TWIDTH-1);
mokind : out std_logic_vector(0 to 1);
mocount : out std_logic_vector(0 to C_CWIDTH-1)
);
end mutex_store;
architecture behavioral of mutex_store is
-- Calculate the number of mutexes to use
constant MUTEXES : integer := pow2( C_MWIDTH );
-- Constant for the last position to be reset
constant RST_END : std_logic_vector(0 to C_MWIDTH-1) := (others => '1');
-- Calculate the beginning and ending bit positions for data
constant OWN_SRT : integer := 0;
constant OWN_END : integer := OWN_SRT + C_TWIDTH-1;
constant NXT_SRT : integer := OWN_END+1;
constant NXT_END : integer := NXT_SRT + C_TWIDTH-1;
constant LST_SRT : integer := NXT_END+1;
constant LST_END : integer := LST_SRT + C_TWIDTH-1;
constant KND_SRT : integer := LST_END+1;
constant KND_END : integer := KND_SRT + 1;
constant CNT_SRT : integer := KND_END + 1;
constant CNT_END : integer := CNT_SRT + C_CWIDTH-1;
-- Declare a storage area for the mutex data
type mstore is array(0 to MUTEXES-1) of std_logic_vector(0 to 3*C_TWIDTH+C_CWIDTH+1);
-- Declare signals for the mutex storage area
signal store : mstore;
signal mena : std_logic;
signal mwea : std_logic;
signal maddr : std_logic_vector(0 to C_MWIDTH-1);
signal minput : std_logic_vector(0 to 3*C_TWIDTH+C_CWIDTH+1);
signal moutput : std_logic_vector(0 to 3*C_TWIDTH+C_CWIDTH+1);
-- Type for the reset state machine
type rststate is
(
IDLE,
RESET
);
-- Declare signals for the reset
signal rena : std_logic;
signal rwea : std_logic;
signal rst_cs : rststate;
signal raddr : std_logic_vector(0 to C_MWIDTH-1);
signal raddrn : std_logic_vector(0 to C_MWIDTH-1);
signal rowner : std_logic_vector(0 to C_TWIDTH-1);
signal rnext : std_logic_vector(0 to C_TWIDTH-1);
signal rlast : std_logic_vector(0 to C_TWIDTH-1);
signal rkind : std_logic_vector(0 to 1);
signal rcount : std_logic_vector(0 to C_CWIDTH-1);
begin
moowner <= moutput(OWN_SRT to OWN_END);
monext <= moutput(NXT_SRT to NXT_END);
molast <= moutput(LST_SRT to LST_END);
mokind <= moutput(KND_SRT to KND_END);
mocount <= moutput(CNT_SRT to CNT_END);
mutex_mux : process(clk,rst,sysrst,rena,rwea,raddr,rowner,rnext,rlast,rkind,rcount,
miena,miwea,miaddr,miowner,milast,mikind,micount) is
begin
if( rising_edge(clk) ) then
if( rst = '1' or sysrst = '1' ) then
mena <= rena;
mwea <= rwea;
maddr <= raddr;
minput <= rowner & rnext & rlast & rkind & rcount;
else
mena <= miena;
mwea <= miwea;
maddr <= miaddr;
minput <= miowner & minext & milast & mikind & micount;
end if;
end if;
end process mutex_mux;
mutex_reset_controller : process(clk,rst) is
begin
if( rising_edge(clk) ) then
if( rst = '1' or sysrst = '1' ) then
rst_cs <= RESET;
raddr <= raddrn;
else
rst_cs <= IDLE;
end if;
end if;
end process mutex_reset_controller;
mutex_reset_logic : process(rst_cs,raddr) is
begin
rena <= '1';
rwea <= '1';
rstdone <= '1';
rowner <= (others => '0');
rnext <= (others => '0');
rlast <= (others => '0');
rkind <= (others => '0');
rcount <= (others => '0');
case rst_cs is
when IDLE =>
raddrn <= (others => '0');
when RESET =>
if( raddr = RST_END ) then
raddrn <= raddr;
else
rstdone <= '0';
raddrn <= raddr + 1;
end if;
end case;
end process mutex_reset_logic;
mutex_store_controller : process (clk) is
begin
if( rising_edge(clk) ) then
if( mena = '1' ) then
if( mwea = '1' ) then
store( conv_integer(maddr) ) <= minput;
end if;
moutput <= store( conv_integer(maddr) );
end if;
end if;
end process mutex_store_controller;
end behavioral;
|
bsd-3-clause
|
masson2013/heterogeneous_hthreads
|
src/platforms/xilinx/smp3_opbhwti/design/pcores/opb_v20_v1_10_d/hdl/vhdl/wrpfifo_dp_cntl.vhd
|
3
|
51701
|
-------------------------------------------------------------------------------
-- $Id: wrpfifo_dp_cntl.vhd,v 1.1.2.1 2009/10/06 21:15:02 gburch Exp $
-------------------------------------------------------------------------------
--wrpfifo_dp_cntl.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: wrpfifo_dp_cntl.vhd
--
-- Description: This VHDL design file is for the Mauna Loa Write Packet
-- FIFO Dual Port Control block and the status
-- calculations for the Occupancy, Vacancy, Full, and Empty.
--
-------------------------------------------------------------------------------
-- Structure: This is the hierarchical structure of the WPFIFO design.
--
--
-- wrpfifo_dp_cntl.vhd
-- |
-- |
-- |-- pf_counter_top.vhd
-- | |
-- | |-- pf_counter.vhd
-- | |
-- | |-- pf_counter_bit.vhd
-- |
-- |
-- |-- pf_occ_counter_top.vhd
-- | |
-- | |-- pf_occ_counter.vhd
-- | |
-- | |-- pf_counter_bit.vhd
-- |
-- |-- pf_adder.vhd
-- | |
-- | |-- pf_adder_bit.vhd
-- |
-- |
-- |
-- |-- pf_dly1_mux.vhd
--
--
--
--
--
-------------------------------------------------------------------------------
-- Author: Doug Thorpe
--
-- History:
-- Doug Thorpe April 6, 2001 -- V1.00b (Backup of read count at end of
-- read)
--
-- DET May 24, 2001 -- V1.00c (fixed bug where RdAck was
-- issued if RdReq from IP occured on the
-- immediatly following clock cycle after
-- a 'Release' command
--
-- DET June 25, 2001 -- Added the DP Core with the ENB input
-- so that the DP port B (Read port) is
-- disabled when the WrFIFO is empty. This
-- clears up MTI sim warnings.
--
--
-- DET Sept. 27, 2001 -- Size Optimized redesign and
-- parameterization
--
-- DET Oct. 10, 2001 -- added pf_dly1_mux module to design
--
--
-- DET 1/21/2003 V2_00_a
-- ~~~~~~
-- - Corrected a burst read problem where the IP stops a burst read
-- with one data value left in the FIFO.
-- ^^^^^^
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
--
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
--
-- Designed by: D. Thorpe
-- Xilinx Mona Loa IP Team
-- Albuquerque, NM
-- APR 10, 2001
--
--
---------------------------------------------------------------------
-- Library definitions
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library opb_v20_v1_10_d;
Use opb_v20_v1_10_d.pf_counter_top;
Use opb_v20_v1_10_d.pf_occ_counter_top;
Use opb_v20_v1_10_d.pf_adder;
Use opb_v20_v1_10_d.pf_dly1_mux;
----------------------------------------------------------------------
entity wrpfifo_dp_cntl is
Generic (
C_DP_ADDRESS_WIDTH : Integer := 5;
-- number of bits needed for dual port addressing
-- of requested FIFO depth
C_INCLUDE_PACKET_MODE : Boolean := true;
-- Select for inclusion/ommision of packet mode
-- features
C_INCLUDE_VACANCY : Boolean := true
-- Enable for Vacancy calc feature
);
port(
-- Inputs
Bus_rst : In std_logic;
Bus_clk : In std_logic;
Rdreq : In std_logic;
Wrreq : In std_logic;
Burst_wr_xfer : In std_logic;
Mark : In std_logic;
Restore : In std_logic;
Release : In std_logic;
-- Outputs
WrAck : Out std_logic;
RdAck : Out std_logic;
Full : Out std_logic;
Empty : Out std_logic;
Almost_Full : Out std_logic;
Almost_Empty : Out std_logic;
DeadLock : Out std_logic;
Occupancy : Out std_logic_vector(0 to C_DP_ADDRESS_WIDTH);
Vacancy : Out std_logic_vector(0 to C_DP_ADDRESS_WIDTH);
DP_core_wren : Out std_logic;
Wr_Addr : Out std_logic_vector(0 to C_DP_ADDRESS_WIDTH-1);
DP_core_rden : Out std_logic;
Rd_Addr : Out std_logic_vector(0 to C_DP_ADDRESS_WIDTH-1)
);
end wrpfifo_dp_cntl ;
-------------------------------------------------------------------------------
architecture implementation of wrpfifo_dp_cntl is
-- Components
-- CONSTANTS
Constant OCC_CNTR_WIDTH : integer := C_DP_ADDRESS_WIDTH+1;
Constant ADDR_CNTR_WIDTH : integer := C_DP_ADDRESS_WIDTH;
Constant MAX_OCCUPANCY : integer := 2**ADDR_CNTR_WIDTH;
Constant LOGIC_LOW : std_logic := '0';
Constant DLY_MUX_WIDTH : integer := OCC_CNTR_WIDTH+2;
--Shared internal signals
Signal base_occupancy : std_logic_vector(0 to OCC_CNTR_WIDTH-1);
-------------------------------------------------------------------------------
-------------------------- start processes ------------------------------------
begin -- architecture
---------------------------------------------------------------------------
-- Generate the Write PFIFO with packetizing features included
---------------------------------------------------------------------------
INCLUDE_PACKET_FEATURES : if (C_INCLUDE_PACKET_MODE = true) generate
--TYPES
type transition_state_type is (reset1,
--reset2,
--reset3,
normal_op,
packet_op,
rest1,
rest2,
mark1,
--mark2,
rls1,
--rls2,
--pkt_rd_backup,
--nml_rd_backup,
pkt_update,
nml_update
);
signal int_full : std_logic;
signal int_full_dly1 : std_logic;
signal int_full_dly2 : std_logic;
signal int_almost_full : std_logic;
signal int_empty : std_logic;
signal int_almost_empty : std_logic;
Signal int_almost_empty_dly1 : std_logic;
Signal int_empty_dly1 : std_logic;
Signal trans_state : transition_state_type;
signal hold_ack : std_logic;
Signal inc_rd_addr : std_logic;
Signal decr_rd_addr : std_logic;
Signal inc_wr_addr : std_logic;
Signal inc_mark_addr : std_logic;
Signal decr_mark_addr : std_logic;
Signal rd_backup : std_logic;
Signal dummy_empty : std_logic;
Signal dummy_almost_empty : std_logic;
Signal dummy_full : std_logic;
Signal dummy_almost_full : std_logic;
signal ld_occ_norm_into_mark : std_logic;
signal ld_addr_mark_into_read : std_logic;
signal ld_addr_read_into_mark : std_logic;
signal ld_occ_mark_into_norm : std_logic;
signal enable_mark_addr_decr : std_logic;
signal enable_mark_addr_inc : std_logic;
signal enable_wr_addr_inc : std_logic;
signal enable_rd_addr_inc : std_logic;
signal enable_rd_addr_decr : std_logic;
signal sig_mark_occupancy : std_logic_vector(0 to
OCC_CNTR_WIDTH-1);
signal sig_normal_occupancy : std_logic_vector(0 to
OCC_CNTR_WIDTH-1);
--signal sig_normal_occupancy_dly1 : std_logic_vector(0 to
-- OCC_CNTR_WIDTH-1);
signal write_address : std_logic_vector(0 to
ADDR_CNTR_WIDTH-1);
signal mark_address : std_logic_vector(0 to
ADDR_CNTR_WIDTH-1);
signal read_address : std_logic_vector(0 to
ADDR_CNTR_WIDTH-1);
signal sig_zeros : std_logic_vector(0 to
ADDR_CNTR_WIDTH-1);
signal inc_nocc : std_logic;
signal inc_mocc : std_logic;
signal inc_nocc_by_2 : std_logic;
signal inc_mocc_by_2 : std_logic;
Signal burst_ack_inhib : std_logic;
signal int_rdack : std_logic;
Signal valid_read : std_logic;
Signal back_to_back_rd : std_logic;
Signal rdreq_dly1 : std_logic;
Signal dly_mux_in :std_logic_vector(0 to
DLY_MUX_WIDTH-1);
Signal dly_mux_out :std_logic_vector(0 to
DLY_MUX_WIDTH-1);
Signal rdack_dly1 : std_logic;
Signal rdack_i : std_logic;
Signal bkup_recover : std_logic;
begin
--Misc I/O Assignments
Full <= int_full
or int_full_dly1
or int_full_dly2;
Almost_Full <= int_almost_full
and not(int_full_dly1)
and not(int_full_dly2);
base_occupancy <= sig_mark_occupancy;
Wr_Addr <= write_address;
Rd_Addr <= read_address;
WrAck <= inc_wr_addr ; -- currently combinitorial
RdAck <= rdack_i;
rdack_i <= int_rdack
and Rdreq -- RdReq used to terminate acknowledge
and not(burst_ack_inhib)
-- needed during burst to fill pipeline
-- (1 clock) out of DPort Block
and not(hold_ack);
-- added May 24 to fix RdAck generation
-- immediately after release
DeadLock <= int_full and int_empty; -- both full and empty at
-- the same time
DP_core_rden <= not(int_empty)-- assert read enable when not empty
or Bus_rst; -- or during reset
DP_core_wren <= not(int_full) -- assert write enable when not full
or Bus_rst; -- or during reset
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_RDACK
--
-- Process Description:
-- Register the RdAck by one clock.
--
-------------------------------------------------------------
REG_RDACK : process (bus_clk)
begin
if (Bus_Clk'event and Bus_Clk = '1') then
if (Bus_Rst = '1') then
rdack_dly1 <= '0';
else
rdack_dly1 <= rdack_i;
end if;
else
null;
end if;
end process REG_RDACK;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: GEN_BKUP_RECOVER
--
-- Process Description:
-- This process generates a signal indicating the required
-- recovery cycle after a backup condition has occured.
--
-------------------------------------------------------------
GEN_BKUP_RECOVER : process (bus_clk)
begin
if (Bus_Clk'event and Bus_Clk = '1') then
if (Bus_Rst = '1') then
bkup_recover <= '0';
else
bkup_recover <= rd_backup;
end if;
else
null;
end if;
end process GEN_BKUP_RECOVER;
----------------------------------------------------------------------
-- Compensate for timing differences needed for Empty flag and
-- Occupancy outputs during single cycle reads and burst reads
-- No delay on single cycle reads
-- 1 clock delay during burst reads
dly_mux_in(0) <= int_empty;
dly_mux_in(1) <= int_almost_empty;
dly_mux_in(2 to DLY_MUX_WIDTH-1) <= sig_normal_occupancy;
I_DELAY_MUX : entity opb_v20_v1_10_d.pf_dly1_mux
Generic map(C_MUX_WIDTH => DLY_MUX_WIDTH
)
port map(
Clk => Bus_clk,
Rst => Bus_rst,
dly_sel1 => '0',
dly_sel2 => back_to_back_rd,
Inputs => dly_mux_in,
Y_out => dly_mux_out
);
Empty <= dly_mux_out(0);
Almost_empty <= dly_mux_out(1);
Occupancy <= dly_mux_out(2 to DLY_MUX_WIDTH-1);
---------------------------------------------------------------------
--------------------------------------------------------------------
-- Transition sequence state machine
--------------------------------------------------------------------
TRANSITION_STATE_PROCESS : process (Bus_rst, Bus_clk)
Begin
If (Bus_rst = '1') Then
ld_occ_norm_into_mark <= '0';
ld_addr_read_into_mark <= '0';
ld_addr_mark_into_read <= '0';
ld_occ_mark_into_norm <= '0';
enable_mark_addr_inc <= '0';
enable_mark_addr_decr <= '0';
enable_wr_addr_inc <= '0';
enable_rd_addr_inc <= '0';
enable_rd_addr_decr <= '0';
trans_state <= reset1;
hold_ack <= '1';
Elsif (Bus_clk'event and Bus_clk = '1') Then
-- set default values
trans_state <= reset1;
hold_ack <= '1';
ld_occ_norm_into_mark <= '0';
ld_addr_read_into_mark <= '0';
ld_addr_mark_into_read <= '0';
ld_occ_mark_into_norm <= '0';
enable_mark_addr_inc <= '0';
enable_mark_addr_decr <= '0';
enable_wr_addr_inc <= '1';
enable_rd_addr_inc <= '0';
enable_rd_addr_decr <= '0';
Case trans_state Is
When reset1 =>
--trans_state <= reset2;
trans_state <= normal_op;
hold_ack <= '1';
enable_wr_addr_inc <= '0';
-- When reset2 =>
-- trans_state <= reset3;
-- hold_ack <= '1';
-- When reset3 =>
-- trans_state <= normal_op;
-- hold_ack <= '0';
When normal_op => -- Ignore restore and release inputs
-- during normal op
enable_mark_addr_inc <= '1';
enable_mark_addr_decr <= '1';
enable_rd_addr_inc <= '1';
enable_rd_addr_decr <= '1';
If (Mark = '1') Then -- transition to packet op on a
-- Mark command
trans_state <= mark1;
hold_ack <= '1';
-- Elsif (rd_backup = '1') Then
-- trans_state <= nml_rd_backup;
-- hold_ack <= '1';
else
trans_state <= normal_op;
hold_ack <= '0';
End if;
When packet_op =>
enable_rd_addr_inc <= '1';
enable_rd_addr_decr <= '1';
If (Restore = '1') Then
trans_state <= rest1;
hold_ack <= '1';
Elsif (Mark = '1') Then
trans_state <= mark1;
hold_ack <= '1';
Elsif (Release = '1') Then
trans_state <= rls1;
hold_ack <= '1';
-- elsif (rd_backup = '1') then
-- trans_state <= pkt_rd_backup;
-- hold_ack <= '1';
else
trans_state <= packet_op;
hold_ack <= '0';
End if;
When rest1 =>
ld_addr_mark_into_read <= '1';
ld_occ_mark_into_norm <= '1';
trans_state <= rest2;
--trans_state <= pkt_update;
hold_ack <= '1';
When rest2 =>
trans_state <= pkt_update;
hold_ack <= '1';
When mark1 =>
ld_occ_norm_into_mark <= '1';
ld_addr_read_into_mark <= '1';
--trans_state <= mark2;
trans_state <= pkt_update;
hold_ack <= '1';
-- When mark2 =>
-- trans_state <= pkt_update;
-- hold_ack <= '1';
When rls1 =>
ld_occ_norm_into_mark <= '1';
ld_addr_read_into_mark <= '1';
--trans_state <= rls2;
trans_state <= nml_update;
hold_ack <= '1';
-- When rls2 =>
-- trans_state <= nml_update;
-- hold_ack <= '1';
-- When pkt_rd_backup =>
-- trans_state <= pkt_update;
-- hold_ack <= '1';
-- When nml_rd_backup =>
-- trans_state <= nml_update;
-- hold_ack <= '1';
When nml_update =>
enable_mark_addr_inc <= '1';
enable_mark_addr_decr <= '1';
enable_rd_addr_inc <= '1';
enable_rd_addr_decr <= '1';
trans_state <= normal_op;
hold_ack <= '0';
When pkt_update =>
enable_rd_addr_inc <= '1';
enable_rd_addr_decr <= '1';
trans_state <= packet_op;
hold_ack <= '0';
When others =>
trans_state <= normal_op;
hold_ack <= '0';
End case;
Else
null;
End if;
End process; -- TRANSITION_STATE_PROCESS
------------------------------------------------------------------
-- Instantiate the Occupancy Counter relative to marking
-- operations. This counter establishes the full flag states
------------------------------------------------------------------
--inc_mocc_by_2 <= decr_rd_addr and inc_mark_addr;
inc_mocc_by_2 <= decr_mark_addr and inc_wr_addr;
inc_mocc <= decr_mark_addr or inc_wr_addr;
I_MARK_OCCUPANCY : entity opb_v20_v1_10_d.pf_occ_counter_top
generic map(
C_COUNT_WIDTH => OCC_CNTR_WIDTH
)
port map(
Clk => Bus_clk,
Rst => Bus_rst,
Load_Enable => ld_occ_norm_into_mark,
Load_value => sig_normal_occupancy,
Count_Down => inc_mark_addr,
Count_Up => inc_mocc,
By_2 => inc_mocc_by_2,
Count_Out => sig_mark_occupancy,
almost_full => int_almost_full,
full => int_full,
almost_empty => dummy_almost_empty,
empty => dummy_empty
);
------------------------------------------------------------------
-- Instantiate the Occupancy Counter relative to normal operations
-- This counter establishes the empty flag states.
------------------------------------------------------------------
inc_nocc_by_2 <= decr_rd_addr and inc_wr_addr;
inc_nocc <= decr_rd_addr or inc_wr_addr;
I_NORMAL_OCCUPANCY : entity opb_v20_v1_10_d.pf_occ_counter_top
generic map(
C_COUNT_WIDTH => OCC_CNTR_WIDTH
)
port map(
Clk => Bus_clk,
Rst => Bus_rst,
Load_Enable => ld_occ_mark_into_norm,
Load_value => sig_mark_occupancy,
Count_Down => inc_rd_addr,
Count_Up => inc_nocc,
By_2 => inc_nocc_by_2,
Count_Out => sig_normal_occupancy,
almost_full => dummy_almost_full,
full => dummy_full,
almost_empty => int_almost_empty,
empty => int_empty
);
------------------------------------------------------------------
-- Register and delay Full/Empty flags
------------------------------------------------------------------
REGISTER_FLAG_PROCESS : process (Bus_rst, Bus_clk)
Begin
If (Bus_rst = '1') Then
int_empty_dly1 <= '1';
int_almost_empty_dly1 <= '0';
int_rdack <= '0';
int_full_dly1 <= '0';
int_full_dly2 <= '0';
--sig_normal_occupancy_dly1 <= (others => '0');
Elsif (Bus_clk'EVENT and Bus_clk = '1') Then
int_empty_dly1 <= int_empty;
int_almost_empty_dly1 <= int_almost_empty;
int_rdack <= not(int_empty)
and not(rd_backup) ;
-- added as part of V0_00c mods
int_full_dly1 <= int_full;
int_full_dly2 <= int_full_dly1;
--sig_normal_occupancy_dly1 <= sig_normal_occupancy;
else
null;
End if;
End process; -- REGISTER_FLAG_PROCESS
------------------------------------------------------------------
-- Write Address Counter Logic
-- inc_wr_addr <= WrReq
-- and not(int_full)
-- and not(int_full_dly1)
-- and not(int_full_dly2)
-- and not(hold_ack)
-- and not(rd_backup and int_almost_full)
-- and enable_wr_addr_inc;
inc_wr_addr <= WrReq
and not(int_full)
and not(int_full_dly1)
and not(int_full_dly2)
and enable_wr_addr_inc;
sig_zeros <= (others => '0');
I_WRITE_ADDR_CNTR : entity opb_v20_v1_10_d.pf_counter_top
Generic Map (
C_COUNT_WIDTH => ADDR_CNTR_WIDTH
)
Port Map (
Clk => Bus_clk,
Rst => Bus_rst,
Load_Enable => '0',
Load_value => sig_zeros,
Count_Down => '0',
Count_Up => inc_wr_addr,
Count_Out => write_address
);
-- end of write counter logic
------------------------------------------------------------------
------------------------------------------------------------------
-- Read Address Counter Logic
---------------------------------------------------------------
-- Detect Back to back reads
---------------------------------------------------------------
BACK_TO_BACK_DETECT : process (Bus_rst, Bus_clk)
Begin
If (Bus_rst = '1') Then
valid_read <= '0';
back_to_back_rd <= '0';
Elsif (Bus_clk'EVENT and Bus_clk = '1') Then
if (inc_rd_addr = '1') Then
valid_read <= '1';
back_to_back_rd <= valid_read;
else
valid_read <= '0';
back_to_back_rd <= '0';
End if;
else
null;
End if;
End process; -- BACK_TO_BACK_DETECT
-- Must create a rdack inhibit the second clock into a burst
-- read to allow the data pipeline to catch up.
--
burst_ack_inhib <= RdReq
and valid_read
and not(back_to_back_rd) -- not yet detected a back to back
and rdack_dly1; -- must have ack'd a read one clock before
---------------------------------------------------------------
-- Register the IP Read Request for use in read counter backup
-- function
---------------------------------------------------------------
REG_READ_REQUEST : process (Bus_rst, Bus_clk)
Begin
If (Bus_rst = '1') Then
rdreq_dly1 <= '0';
Elsif (Bus_clk'EVENT and Bus_clk = '1') Then
rdreq_dly1 <= RdReq;
else
null;
End if;
End process; -- process_name
inc_rd_addr <= RdReq
And not(bkup_recover) -- DET added for
and not(hold_ack)
and not(int_empty)
and not(int_empty_dly1)
and enable_rd_addr_inc;
rd_backup <= not(RdReq)
And back_to_back_rd
-- DET Test fix for --And not(int_empty);
And not(int_empty_dly1);
decr_rd_addr <= rd_backup
and enable_rd_addr_decr;
I_READ_ADDR_CNTR : entity opb_v20_v1_10_d.pf_counter_top
Generic Map ( C_COUNT_WIDTH => ADDR_CNTR_WIDTH
)
Port Map (
Clk => Bus_clk,
Rst => Bus_rst,
Load_Enable => ld_addr_mark_into_read,
Load_value => mark_address,
Count_Down => decr_rd_addr,
Count_Up => inc_rd_addr,
Count_Out => read_address
);
-- end read address counter logic
------------------------------------------------------------------
------------------------------------------------------------------
-- Mark Register Control
inc_mark_addr <= inc_rd_addr
and enable_mark_addr_inc;
decr_mark_addr <= rd_backup
and enable_rd_addr_decr
and enable_mark_addr_decr;
I_MARKREG_ADDR_CNTR : entity opb_v20_v1_10_d.pf_counter_top
Generic Map ( C_COUNT_WIDTH => ADDR_CNTR_WIDTH
)
Port Map (
Clk => Bus_clk,
Rst => Bus_rst,
Load_Enable => ld_addr_read_into_mark,
Load_value => read_address,
Count_Down => decr_mark_addr,
Count_Up => inc_mark_addr,
Count_Out => mark_address
);
-- end mark address counter logic
------------------------------------------------------------------
end generate INCLUDE_PACKET_FEATURES;
----------------------------------------------------------------------------
-- Generate the Write PFIFO with no packetizing features
----------------------------------------------------------------------------
OMIT_PACKET_FEATURES : if (C_INCLUDE_PACKET_MODE = false) generate
-- Internal signals
signal int_full : std_logic;
signal int_full_dly1 : std_logic;
signal int_full_dly2 : std_logic;
signal int_almost_full : std_logic;
signal int_empty : std_logic;
signal int_almost_empty : std_logic;
Signal int_almost_empty_dly1 : std_logic;
Signal int_empty_dly1 : std_logic;
Signal inc_wr_addr : std_logic;
signal write_address : std_logic_vector(0 to
ADDR_CNTR_WIDTH-1);
Signal inc_rd_addr : std_logic;
Signal decr_rd_addr : std_logic;
Signal rd_backup : std_logic;
signal read_address : std_logic_vector(0 to
ADDR_CNTR_WIDTH-1);
signal sig_zeros : std_logic_vector(0 to
ADDR_CNTR_WIDTH-1);
signal inc_nocc : std_logic;
signal inc_nocc_by_2 : std_logic;
signal sig_normal_occupancy : std_logic_vector(0 to
OCC_CNTR_WIDTH-1);
signal occ_load_value : std_logic_vector(0 to
OCC_CNTR_WIDTH-1);
Signal burst_ack_inhib : std_logic;
signal int_rdack : std_logic;
Signal valid_read : std_logic;
Signal back_to_back_rd : std_logic;
Signal rdreq_dly1 : std_logic;
Signal dly_mux_in :std_logic_vector(0 to
DLY_MUX_WIDTH-1);
Signal dly_mux_out :std_logic_vector(0 to
DLY_MUX_WIDTH-1);
Signal rdack_dly1 : std_logic;
Signal rdack_i : std_logic;
Signal bkup_recover : std_logic;
begin
--Misc I/O Assignments
Full <= int_full
or int_full_dly1
or int_full_dly2;
Almost_Full <= int_almost_full
and not(int_full_dly1)
and not(int_full_dly2);
Wr_Addr <= write_address;
Rd_Addr <= read_address;
WrAck <= inc_wr_addr ; -- currently combinitorial
RdAck <= rdack_i;
rdack_i <= int_rdack
and Rdreq -- RdReq used to terminate acknowledge
and not(burst_ack_inhib);
-- needed during burst to fill
-- pipeline (1 clock) out of DPort
-- Block
DeadLock <= int_full and int_empty; -- both full and empty
-- at the same time
DP_core_rden <= not(int_empty)-- assert read enable when not
or Bus_rst; -- empty or during reset
DP_core_wren <= not(int_full) -- assert write enable when not
or Bus_rst; -- full or during reset
base_occupancy <= sig_normal_occupancy;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_RDACK
--
-- Process Description:
-- Register the RdAck by one clock.
--
-------------------------------------------------------------
REG_RDACK : process (bus_clk)
begin
if (Bus_Clk'event and Bus_Clk = '1') then
if (Bus_Rst = '1') then
rdack_dly1 <= '0';
else
rdack_dly1 <= rdack_i;
end if;
else
null;
end if;
end process REG_RDACK;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: GEN_BKUP_RECOVER
--
-- Process Description:
-- This process generates a signal indicating the required
-- recovery cycle after a backup condition has occured.
--
-------------------------------------------------------------
GEN_BKUP_RECOVER : process (bus_clk)
begin
if (Bus_Clk'event and Bus_Clk = '1') then
if (Bus_Rst = '1') then
bkup_recover <= '0';
else
bkup_recover <= rd_backup;
end if;
else
null;
end if;
end process GEN_BKUP_RECOVER;
----------------------------------------------------------------------
-- Compensate for timing differences needed for Empty flag and
-- Occupancy outputs during single cycle reads and burst reads
-- No delay on single cycle reads
-- 1 clock delay during burst reads
dly_mux_in(0) <= int_empty;
dly_mux_in(1) <= int_almost_empty;
dly_mux_in(2 to DLY_MUX_WIDTH-1) <= sig_normal_occupancy;
I_DELAY_MUX : entity opb_v20_v1_10_d.pf_dly1_mux
Generic map(C_MUX_WIDTH => DLY_MUX_WIDTH
)
port map(
Clk => Bus_clk,-- : in std_logic;
Rst => Bus_rst,-- : In std_logic;
dly_sel1 => '0', --burst_ack_inhib,-- : in std_logic;
dly_sel2 => back_to_back_rd,-- : in std_logic;
Inputs => dly_mux_in,-- : in std_logic_vector;
Y_out => dly_mux_out-- : out std_logic_vector
);
Empty <= dly_mux_out(0);
Almost_empty <= dly_mux_out(1);
Occupancy <= dly_mux_out(2 to DLY_MUX_WIDTH-1);
---------------------------------------------------------------------
------------------------------------------------------------------
-- Instantiate the Occupancy Counter relative to normal operations
-- This counter establishes the empty flag states.
------------------------------------------------------------------
inc_nocc_by_2 <= decr_rd_addr and inc_wr_addr;
inc_nocc <= decr_rd_addr or inc_wr_addr;
occ_load_value <= (others => '0');
I_NORMAL_OCCUPANCY : entity opb_v20_v1_10_d.pf_occ_counter_top
generic map(
C_COUNT_WIDTH => OCC_CNTR_WIDTH
)
port map(
Clk => Bus_clk,
Rst => Bus_rst,
Load_Enable => '0',
Load_value => occ_load_value,
Count_Down => inc_rd_addr,
Count_Up => inc_nocc,
By_2 => inc_nocc_by_2,
Count_Out => sig_normal_occupancy,
almost_full => int_almost_full,
full => int_full,
almost_empty => int_almost_empty,
empty => int_empty
);
------------------------------------------------------------------
-- Register and delay Full/Empty flags
------------------------------------------------------------------
REGISTER_FLAG_PROCESS : process (Bus_rst, Bus_clk)
Begin
If (Bus_rst = '1') Then
int_empty_dly1 <= '1';
int_almost_empty_dly1 <= '0';
int_rdack <= '0';
int_full_dly1 <= '0';
int_full_dly2 <= '0';
--sig_normal_occupancy_dly1 <= (others => '0');
Elsif (Bus_clk'EVENT and Bus_clk = '1') Then
int_empty_dly1 <= int_empty;
int_almost_empty_dly1 <= int_almost_empty;
int_rdack <= not(int_empty)
and not(rd_backup);
int_full_dly1 <= int_full;
int_full_dly2 <= int_full_dly1;
--sig_normal_occupancy_dly1 <= sig_normal_occupancy;
else
null;
End if;
End process; -- REGISTER_FLAG_PROCESS
------------------------------------------------------------------
-- Write Address Counter Logic
inc_wr_addr <= WrReq
and not(int_full)
and not(int_full_dly1)
and not(int_full_dly2);
sig_zeros <= (others => '0');
I_WRITE_ADDR_CNTR : entity opb_v20_v1_10_d.pf_counter_top
Generic Map (
C_COUNT_WIDTH => ADDR_CNTR_WIDTH
)
Port Map (
Clk => Bus_clk,
Rst => Bus_rst,
Load_Enable => '0',
Load_value => sig_zeros,
Count_Down => '0',
Count_Up => inc_wr_addr,
Count_Out => write_address
);
-- end of write counter logic
------------------------------------------------------------------
------------------------------------------------------------------
-- Read Address Counter Logic
---------------------------------------------------------------
-- Detect Back to back reads
---------------------------------------------------------------
BACK_TO_BACK_DETECT : process (Bus_rst, Bus_clk)
Begin
If (Bus_rst = '1') Then
valid_read <= '0';
back_to_back_rd <= '0';
Elsif (Bus_clk'EVENT and Bus_clk = '1') Then
if (inc_rd_addr = '1') Then
valid_read <= '1';
back_to_back_rd <= valid_read;
else
valid_read <= '0';
back_to_back_rd <= '0';
End if;
else
null;
End if;
End process; -- BACK_TO_BACK_DETECT
-- Must create a rdack inhibit the second clock into a burst
-- read to allow the data pipeline to catch up.
--
burst_ack_inhib <= RdReq
and valid_read
and not(back_to_back_rd) -- not yet detected a back to back
and rdack_dly1; -- must have ack'd a read one clock before
---------------------------------------------------------------
-- Register the IP Read Request for use in read counter backup
-- function
---------------------------------------------------------------
REG_READ_REQUEST : process (Bus_rst, Bus_clk)
Begin
If (Bus_rst = '1') Then
rdreq_dly1 <= '0';
Elsif (Bus_clk'EVENT and Bus_clk = '1') Then
rdreq_dly1 <= RdReq;
else
null;
End if;
End process; -- REG_READ_REQUEST
inc_rd_addr <= RdReq
And not(bkup_recover) -- DET added for
and not(int_empty)
and not(int_empty_dly1);
rd_backup <= not(RdReq)
And back_to_back_rd
-- DET Test fix for --And not(int_empty);
And not(int_empty_dly1);
decr_rd_addr <= rd_backup;
I_READ_ADDR_CNTR : entity opb_v20_v1_10_d.pf_counter_top
Generic Map ( C_COUNT_WIDTH => ADDR_CNTR_WIDTH
)
Port Map (
Clk => Bus_clk,
Rst => Bus_rst,
Load_Enable => '0',
Load_value => sig_zeros,
Count_Down => decr_rd_addr,
Count_Up => inc_rd_addr,
Count_Out => read_address
);
-- end read address counter logic
------------------------------------------------------------------
end generate OMIT_PACKET_FEATURES;
INCLUDE_VACANCY : if (C_INCLUDE_VACANCY = true) generate
Constant REGISTER_VACANCY : boolean := false;
Signal slv_max_vacancy : std_logic_vector(0 to OCC_CNTR_WIDTH-1);
Signal int_vacancy : std_logic_vector(0 to OCC_CNTR_WIDTH-1);
begin
Vacancy <= int_vacancy; -- set to zeroes for now.
slv_max_vacancy <= CONV_STD_LOGIC_VECTOR(MAX_OCCUPANCY, OCC_CNTR_WIDTH);
I_VAC_CALC : entity opb_v20_v1_10_d.pf_adder
generic map(
C_REGISTERED_RESULT => REGISTER_VACANCY,
C_COUNT_WIDTH => OCC_CNTR_WIDTH
)
port map (
Clk => Bus_clk,
Rst => Bus_rst,
Ain => slv_max_vacancy,
Bin => base_occupancy,
Add_sub_n => '0', -- always subtract
result_out => int_vacancy
);
end generate; -- INCLUDE_VACANCY
OMIT_VACANCY : if (C_INCLUDE_VACANCY = false) generate
Signal int_vacancy : std_logic_vector(0 to OCC_CNTR_WIDTH-1);
begin
int_vacancy <= (others => '0');
Vacancy <= int_vacancy; -- set to zeroes for now.
end generate; -- INCLUDE_VACANCY
end implementation;
|
bsd-3-clause
|
masson2013/heterogeneous_hthreads
|
src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/opb_v20_v1_10_d/hdl/vhdl/wrpfifo_dp_cntl.vhd
|
3
|
51701
|
-------------------------------------------------------------------------------
-- $Id: wrpfifo_dp_cntl.vhd,v 1.1.2.1 2009/10/06 21:15:02 gburch Exp $
-------------------------------------------------------------------------------
--wrpfifo_dp_cntl.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: wrpfifo_dp_cntl.vhd
--
-- Description: This VHDL design file is for the Mauna Loa Write Packet
-- FIFO Dual Port Control block and the status
-- calculations for the Occupancy, Vacancy, Full, and Empty.
--
-------------------------------------------------------------------------------
-- Structure: This is the hierarchical structure of the WPFIFO design.
--
--
-- wrpfifo_dp_cntl.vhd
-- |
-- |
-- |-- pf_counter_top.vhd
-- | |
-- | |-- pf_counter.vhd
-- | |
-- | |-- pf_counter_bit.vhd
-- |
-- |
-- |-- pf_occ_counter_top.vhd
-- | |
-- | |-- pf_occ_counter.vhd
-- | |
-- | |-- pf_counter_bit.vhd
-- |
-- |-- pf_adder.vhd
-- | |
-- | |-- pf_adder_bit.vhd
-- |
-- |
-- |
-- |-- pf_dly1_mux.vhd
--
--
--
--
--
-------------------------------------------------------------------------------
-- Author: Doug Thorpe
--
-- History:
-- Doug Thorpe April 6, 2001 -- V1.00b (Backup of read count at end of
-- read)
--
-- DET May 24, 2001 -- V1.00c (fixed bug where RdAck was
-- issued if RdReq from IP occured on the
-- immediatly following clock cycle after
-- a 'Release' command
--
-- DET June 25, 2001 -- Added the DP Core with the ENB input
-- so that the DP port B (Read port) is
-- disabled when the WrFIFO is empty. This
-- clears up MTI sim warnings.
--
--
-- DET Sept. 27, 2001 -- Size Optimized redesign and
-- parameterization
--
-- DET Oct. 10, 2001 -- added pf_dly1_mux module to design
--
--
-- DET 1/21/2003 V2_00_a
-- ~~~~~~
-- - Corrected a burst read problem where the IP stops a burst read
-- with one data value left in the FIFO.
-- ^^^^^^
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
--
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
--
-- Designed by: D. Thorpe
-- Xilinx Mona Loa IP Team
-- Albuquerque, NM
-- APR 10, 2001
--
--
---------------------------------------------------------------------
-- Library definitions
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library opb_v20_v1_10_d;
Use opb_v20_v1_10_d.pf_counter_top;
Use opb_v20_v1_10_d.pf_occ_counter_top;
Use opb_v20_v1_10_d.pf_adder;
Use opb_v20_v1_10_d.pf_dly1_mux;
----------------------------------------------------------------------
entity wrpfifo_dp_cntl is
Generic (
C_DP_ADDRESS_WIDTH : Integer := 5;
-- number of bits needed for dual port addressing
-- of requested FIFO depth
C_INCLUDE_PACKET_MODE : Boolean := true;
-- Select for inclusion/ommision of packet mode
-- features
C_INCLUDE_VACANCY : Boolean := true
-- Enable for Vacancy calc feature
);
port(
-- Inputs
Bus_rst : In std_logic;
Bus_clk : In std_logic;
Rdreq : In std_logic;
Wrreq : In std_logic;
Burst_wr_xfer : In std_logic;
Mark : In std_logic;
Restore : In std_logic;
Release : In std_logic;
-- Outputs
WrAck : Out std_logic;
RdAck : Out std_logic;
Full : Out std_logic;
Empty : Out std_logic;
Almost_Full : Out std_logic;
Almost_Empty : Out std_logic;
DeadLock : Out std_logic;
Occupancy : Out std_logic_vector(0 to C_DP_ADDRESS_WIDTH);
Vacancy : Out std_logic_vector(0 to C_DP_ADDRESS_WIDTH);
DP_core_wren : Out std_logic;
Wr_Addr : Out std_logic_vector(0 to C_DP_ADDRESS_WIDTH-1);
DP_core_rden : Out std_logic;
Rd_Addr : Out std_logic_vector(0 to C_DP_ADDRESS_WIDTH-1)
);
end wrpfifo_dp_cntl ;
-------------------------------------------------------------------------------
architecture implementation of wrpfifo_dp_cntl is
-- Components
-- CONSTANTS
Constant OCC_CNTR_WIDTH : integer := C_DP_ADDRESS_WIDTH+1;
Constant ADDR_CNTR_WIDTH : integer := C_DP_ADDRESS_WIDTH;
Constant MAX_OCCUPANCY : integer := 2**ADDR_CNTR_WIDTH;
Constant LOGIC_LOW : std_logic := '0';
Constant DLY_MUX_WIDTH : integer := OCC_CNTR_WIDTH+2;
--Shared internal signals
Signal base_occupancy : std_logic_vector(0 to OCC_CNTR_WIDTH-1);
-------------------------------------------------------------------------------
-------------------------- start processes ------------------------------------
begin -- architecture
---------------------------------------------------------------------------
-- Generate the Write PFIFO with packetizing features included
---------------------------------------------------------------------------
INCLUDE_PACKET_FEATURES : if (C_INCLUDE_PACKET_MODE = true) generate
--TYPES
type transition_state_type is (reset1,
--reset2,
--reset3,
normal_op,
packet_op,
rest1,
rest2,
mark1,
--mark2,
rls1,
--rls2,
--pkt_rd_backup,
--nml_rd_backup,
pkt_update,
nml_update
);
signal int_full : std_logic;
signal int_full_dly1 : std_logic;
signal int_full_dly2 : std_logic;
signal int_almost_full : std_logic;
signal int_empty : std_logic;
signal int_almost_empty : std_logic;
Signal int_almost_empty_dly1 : std_logic;
Signal int_empty_dly1 : std_logic;
Signal trans_state : transition_state_type;
signal hold_ack : std_logic;
Signal inc_rd_addr : std_logic;
Signal decr_rd_addr : std_logic;
Signal inc_wr_addr : std_logic;
Signal inc_mark_addr : std_logic;
Signal decr_mark_addr : std_logic;
Signal rd_backup : std_logic;
Signal dummy_empty : std_logic;
Signal dummy_almost_empty : std_logic;
Signal dummy_full : std_logic;
Signal dummy_almost_full : std_logic;
signal ld_occ_norm_into_mark : std_logic;
signal ld_addr_mark_into_read : std_logic;
signal ld_addr_read_into_mark : std_logic;
signal ld_occ_mark_into_norm : std_logic;
signal enable_mark_addr_decr : std_logic;
signal enable_mark_addr_inc : std_logic;
signal enable_wr_addr_inc : std_logic;
signal enable_rd_addr_inc : std_logic;
signal enable_rd_addr_decr : std_logic;
signal sig_mark_occupancy : std_logic_vector(0 to
OCC_CNTR_WIDTH-1);
signal sig_normal_occupancy : std_logic_vector(0 to
OCC_CNTR_WIDTH-1);
--signal sig_normal_occupancy_dly1 : std_logic_vector(0 to
-- OCC_CNTR_WIDTH-1);
signal write_address : std_logic_vector(0 to
ADDR_CNTR_WIDTH-1);
signal mark_address : std_logic_vector(0 to
ADDR_CNTR_WIDTH-1);
signal read_address : std_logic_vector(0 to
ADDR_CNTR_WIDTH-1);
signal sig_zeros : std_logic_vector(0 to
ADDR_CNTR_WIDTH-1);
signal inc_nocc : std_logic;
signal inc_mocc : std_logic;
signal inc_nocc_by_2 : std_logic;
signal inc_mocc_by_2 : std_logic;
Signal burst_ack_inhib : std_logic;
signal int_rdack : std_logic;
Signal valid_read : std_logic;
Signal back_to_back_rd : std_logic;
Signal rdreq_dly1 : std_logic;
Signal dly_mux_in :std_logic_vector(0 to
DLY_MUX_WIDTH-1);
Signal dly_mux_out :std_logic_vector(0 to
DLY_MUX_WIDTH-1);
Signal rdack_dly1 : std_logic;
Signal rdack_i : std_logic;
Signal bkup_recover : std_logic;
begin
--Misc I/O Assignments
Full <= int_full
or int_full_dly1
or int_full_dly2;
Almost_Full <= int_almost_full
and not(int_full_dly1)
and not(int_full_dly2);
base_occupancy <= sig_mark_occupancy;
Wr_Addr <= write_address;
Rd_Addr <= read_address;
WrAck <= inc_wr_addr ; -- currently combinitorial
RdAck <= rdack_i;
rdack_i <= int_rdack
and Rdreq -- RdReq used to terminate acknowledge
and not(burst_ack_inhib)
-- needed during burst to fill pipeline
-- (1 clock) out of DPort Block
and not(hold_ack);
-- added May 24 to fix RdAck generation
-- immediately after release
DeadLock <= int_full and int_empty; -- both full and empty at
-- the same time
DP_core_rden <= not(int_empty)-- assert read enable when not empty
or Bus_rst; -- or during reset
DP_core_wren <= not(int_full) -- assert write enable when not full
or Bus_rst; -- or during reset
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_RDACK
--
-- Process Description:
-- Register the RdAck by one clock.
--
-------------------------------------------------------------
REG_RDACK : process (bus_clk)
begin
if (Bus_Clk'event and Bus_Clk = '1') then
if (Bus_Rst = '1') then
rdack_dly1 <= '0';
else
rdack_dly1 <= rdack_i;
end if;
else
null;
end if;
end process REG_RDACK;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: GEN_BKUP_RECOVER
--
-- Process Description:
-- This process generates a signal indicating the required
-- recovery cycle after a backup condition has occured.
--
-------------------------------------------------------------
GEN_BKUP_RECOVER : process (bus_clk)
begin
if (Bus_Clk'event and Bus_Clk = '1') then
if (Bus_Rst = '1') then
bkup_recover <= '0';
else
bkup_recover <= rd_backup;
end if;
else
null;
end if;
end process GEN_BKUP_RECOVER;
----------------------------------------------------------------------
-- Compensate for timing differences needed for Empty flag and
-- Occupancy outputs during single cycle reads and burst reads
-- No delay on single cycle reads
-- 1 clock delay during burst reads
dly_mux_in(0) <= int_empty;
dly_mux_in(1) <= int_almost_empty;
dly_mux_in(2 to DLY_MUX_WIDTH-1) <= sig_normal_occupancy;
I_DELAY_MUX : entity opb_v20_v1_10_d.pf_dly1_mux
Generic map(C_MUX_WIDTH => DLY_MUX_WIDTH
)
port map(
Clk => Bus_clk,
Rst => Bus_rst,
dly_sel1 => '0',
dly_sel2 => back_to_back_rd,
Inputs => dly_mux_in,
Y_out => dly_mux_out
);
Empty <= dly_mux_out(0);
Almost_empty <= dly_mux_out(1);
Occupancy <= dly_mux_out(2 to DLY_MUX_WIDTH-1);
---------------------------------------------------------------------
--------------------------------------------------------------------
-- Transition sequence state machine
--------------------------------------------------------------------
TRANSITION_STATE_PROCESS : process (Bus_rst, Bus_clk)
Begin
If (Bus_rst = '1') Then
ld_occ_norm_into_mark <= '0';
ld_addr_read_into_mark <= '0';
ld_addr_mark_into_read <= '0';
ld_occ_mark_into_norm <= '0';
enable_mark_addr_inc <= '0';
enable_mark_addr_decr <= '0';
enable_wr_addr_inc <= '0';
enable_rd_addr_inc <= '0';
enable_rd_addr_decr <= '0';
trans_state <= reset1;
hold_ack <= '1';
Elsif (Bus_clk'event and Bus_clk = '1') Then
-- set default values
trans_state <= reset1;
hold_ack <= '1';
ld_occ_norm_into_mark <= '0';
ld_addr_read_into_mark <= '0';
ld_addr_mark_into_read <= '0';
ld_occ_mark_into_norm <= '0';
enable_mark_addr_inc <= '0';
enable_mark_addr_decr <= '0';
enable_wr_addr_inc <= '1';
enable_rd_addr_inc <= '0';
enable_rd_addr_decr <= '0';
Case trans_state Is
When reset1 =>
--trans_state <= reset2;
trans_state <= normal_op;
hold_ack <= '1';
enable_wr_addr_inc <= '0';
-- When reset2 =>
-- trans_state <= reset3;
-- hold_ack <= '1';
-- When reset3 =>
-- trans_state <= normal_op;
-- hold_ack <= '0';
When normal_op => -- Ignore restore and release inputs
-- during normal op
enable_mark_addr_inc <= '1';
enable_mark_addr_decr <= '1';
enable_rd_addr_inc <= '1';
enable_rd_addr_decr <= '1';
If (Mark = '1') Then -- transition to packet op on a
-- Mark command
trans_state <= mark1;
hold_ack <= '1';
-- Elsif (rd_backup = '1') Then
-- trans_state <= nml_rd_backup;
-- hold_ack <= '1';
else
trans_state <= normal_op;
hold_ack <= '0';
End if;
When packet_op =>
enable_rd_addr_inc <= '1';
enable_rd_addr_decr <= '1';
If (Restore = '1') Then
trans_state <= rest1;
hold_ack <= '1';
Elsif (Mark = '1') Then
trans_state <= mark1;
hold_ack <= '1';
Elsif (Release = '1') Then
trans_state <= rls1;
hold_ack <= '1';
-- elsif (rd_backup = '1') then
-- trans_state <= pkt_rd_backup;
-- hold_ack <= '1';
else
trans_state <= packet_op;
hold_ack <= '0';
End if;
When rest1 =>
ld_addr_mark_into_read <= '1';
ld_occ_mark_into_norm <= '1';
trans_state <= rest2;
--trans_state <= pkt_update;
hold_ack <= '1';
When rest2 =>
trans_state <= pkt_update;
hold_ack <= '1';
When mark1 =>
ld_occ_norm_into_mark <= '1';
ld_addr_read_into_mark <= '1';
--trans_state <= mark2;
trans_state <= pkt_update;
hold_ack <= '1';
-- When mark2 =>
-- trans_state <= pkt_update;
-- hold_ack <= '1';
When rls1 =>
ld_occ_norm_into_mark <= '1';
ld_addr_read_into_mark <= '1';
--trans_state <= rls2;
trans_state <= nml_update;
hold_ack <= '1';
-- When rls2 =>
-- trans_state <= nml_update;
-- hold_ack <= '1';
-- When pkt_rd_backup =>
-- trans_state <= pkt_update;
-- hold_ack <= '1';
-- When nml_rd_backup =>
-- trans_state <= nml_update;
-- hold_ack <= '1';
When nml_update =>
enable_mark_addr_inc <= '1';
enable_mark_addr_decr <= '1';
enable_rd_addr_inc <= '1';
enable_rd_addr_decr <= '1';
trans_state <= normal_op;
hold_ack <= '0';
When pkt_update =>
enable_rd_addr_inc <= '1';
enable_rd_addr_decr <= '1';
trans_state <= packet_op;
hold_ack <= '0';
When others =>
trans_state <= normal_op;
hold_ack <= '0';
End case;
Else
null;
End if;
End process; -- TRANSITION_STATE_PROCESS
------------------------------------------------------------------
-- Instantiate the Occupancy Counter relative to marking
-- operations. This counter establishes the full flag states
------------------------------------------------------------------
--inc_mocc_by_2 <= decr_rd_addr and inc_mark_addr;
inc_mocc_by_2 <= decr_mark_addr and inc_wr_addr;
inc_mocc <= decr_mark_addr or inc_wr_addr;
I_MARK_OCCUPANCY : entity opb_v20_v1_10_d.pf_occ_counter_top
generic map(
C_COUNT_WIDTH => OCC_CNTR_WIDTH
)
port map(
Clk => Bus_clk,
Rst => Bus_rst,
Load_Enable => ld_occ_norm_into_mark,
Load_value => sig_normal_occupancy,
Count_Down => inc_mark_addr,
Count_Up => inc_mocc,
By_2 => inc_mocc_by_2,
Count_Out => sig_mark_occupancy,
almost_full => int_almost_full,
full => int_full,
almost_empty => dummy_almost_empty,
empty => dummy_empty
);
------------------------------------------------------------------
-- Instantiate the Occupancy Counter relative to normal operations
-- This counter establishes the empty flag states.
------------------------------------------------------------------
inc_nocc_by_2 <= decr_rd_addr and inc_wr_addr;
inc_nocc <= decr_rd_addr or inc_wr_addr;
I_NORMAL_OCCUPANCY : entity opb_v20_v1_10_d.pf_occ_counter_top
generic map(
C_COUNT_WIDTH => OCC_CNTR_WIDTH
)
port map(
Clk => Bus_clk,
Rst => Bus_rst,
Load_Enable => ld_occ_mark_into_norm,
Load_value => sig_mark_occupancy,
Count_Down => inc_rd_addr,
Count_Up => inc_nocc,
By_2 => inc_nocc_by_2,
Count_Out => sig_normal_occupancy,
almost_full => dummy_almost_full,
full => dummy_full,
almost_empty => int_almost_empty,
empty => int_empty
);
------------------------------------------------------------------
-- Register and delay Full/Empty flags
------------------------------------------------------------------
REGISTER_FLAG_PROCESS : process (Bus_rst, Bus_clk)
Begin
If (Bus_rst = '1') Then
int_empty_dly1 <= '1';
int_almost_empty_dly1 <= '0';
int_rdack <= '0';
int_full_dly1 <= '0';
int_full_dly2 <= '0';
--sig_normal_occupancy_dly1 <= (others => '0');
Elsif (Bus_clk'EVENT and Bus_clk = '1') Then
int_empty_dly1 <= int_empty;
int_almost_empty_dly1 <= int_almost_empty;
int_rdack <= not(int_empty)
and not(rd_backup) ;
-- added as part of V0_00c mods
int_full_dly1 <= int_full;
int_full_dly2 <= int_full_dly1;
--sig_normal_occupancy_dly1 <= sig_normal_occupancy;
else
null;
End if;
End process; -- REGISTER_FLAG_PROCESS
------------------------------------------------------------------
-- Write Address Counter Logic
-- inc_wr_addr <= WrReq
-- and not(int_full)
-- and not(int_full_dly1)
-- and not(int_full_dly2)
-- and not(hold_ack)
-- and not(rd_backup and int_almost_full)
-- and enable_wr_addr_inc;
inc_wr_addr <= WrReq
and not(int_full)
and not(int_full_dly1)
and not(int_full_dly2)
and enable_wr_addr_inc;
sig_zeros <= (others => '0');
I_WRITE_ADDR_CNTR : entity opb_v20_v1_10_d.pf_counter_top
Generic Map (
C_COUNT_WIDTH => ADDR_CNTR_WIDTH
)
Port Map (
Clk => Bus_clk,
Rst => Bus_rst,
Load_Enable => '0',
Load_value => sig_zeros,
Count_Down => '0',
Count_Up => inc_wr_addr,
Count_Out => write_address
);
-- end of write counter logic
------------------------------------------------------------------
------------------------------------------------------------------
-- Read Address Counter Logic
---------------------------------------------------------------
-- Detect Back to back reads
---------------------------------------------------------------
BACK_TO_BACK_DETECT : process (Bus_rst, Bus_clk)
Begin
If (Bus_rst = '1') Then
valid_read <= '0';
back_to_back_rd <= '0';
Elsif (Bus_clk'EVENT and Bus_clk = '1') Then
if (inc_rd_addr = '1') Then
valid_read <= '1';
back_to_back_rd <= valid_read;
else
valid_read <= '0';
back_to_back_rd <= '0';
End if;
else
null;
End if;
End process; -- BACK_TO_BACK_DETECT
-- Must create a rdack inhibit the second clock into a burst
-- read to allow the data pipeline to catch up.
--
burst_ack_inhib <= RdReq
and valid_read
and not(back_to_back_rd) -- not yet detected a back to back
and rdack_dly1; -- must have ack'd a read one clock before
---------------------------------------------------------------
-- Register the IP Read Request for use in read counter backup
-- function
---------------------------------------------------------------
REG_READ_REQUEST : process (Bus_rst, Bus_clk)
Begin
If (Bus_rst = '1') Then
rdreq_dly1 <= '0';
Elsif (Bus_clk'EVENT and Bus_clk = '1') Then
rdreq_dly1 <= RdReq;
else
null;
End if;
End process; -- process_name
inc_rd_addr <= RdReq
And not(bkup_recover) -- DET added for
and not(hold_ack)
and not(int_empty)
and not(int_empty_dly1)
and enable_rd_addr_inc;
rd_backup <= not(RdReq)
And back_to_back_rd
-- DET Test fix for --And not(int_empty);
And not(int_empty_dly1);
decr_rd_addr <= rd_backup
and enable_rd_addr_decr;
I_READ_ADDR_CNTR : entity opb_v20_v1_10_d.pf_counter_top
Generic Map ( C_COUNT_WIDTH => ADDR_CNTR_WIDTH
)
Port Map (
Clk => Bus_clk,
Rst => Bus_rst,
Load_Enable => ld_addr_mark_into_read,
Load_value => mark_address,
Count_Down => decr_rd_addr,
Count_Up => inc_rd_addr,
Count_Out => read_address
);
-- end read address counter logic
------------------------------------------------------------------
------------------------------------------------------------------
-- Mark Register Control
inc_mark_addr <= inc_rd_addr
and enable_mark_addr_inc;
decr_mark_addr <= rd_backup
and enable_rd_addr_decr
and enable_mark_addr_decr;
I_MARKREG_ADDR_CNTR : entity opb_v20_v1_10_d.pf_counter_top
Generic Map ( C_COUNT_WIDTH => ADDR_CNTR_WIDTH
)
Port Map (
Clk => Bus_clk,
Rst => Bus_rst,
Load_Enable => ld_addr_read_into_mark,
Load_value => read_address,
Count_Down => decr_mark_addr,
Count_Up => inc_mark_addr,
Count_Out => mark_address
);
-- end mark address counter logic
------------------------------------------------------------------
end generate INCLUDE_PACKET_FEATURES;
----------------------------------------------------------------------------
-- Generate the Write PFIFO with no packetizing features
----------------------------------------------------------------------------
OMIT_PACKET_FEATURES : if (C_INCLUDE_PACKET_MODE = false) generate
-- Internal signals
signal int_full : std_logic;
signal int_full_dly1 : std_logic;
signal int_full_dly2 : std_logic;
signal int_almost_full : std_logic;
signal int_empty : std_logic;
signal int_almost_empty : std_logic;
Signal int_almost_empty_dly1 : std_logic;
Signal int_empty_dly1 : std_logic;
Signal inc_wr_addr : std_logic;
signal write_address : std_logic_vector(0 to
ADDR_CNTR_WIDTH-1);
Signal inc_rd_addr : std_logic;
Signal decr_rd_addr : std_logic;
Signal rd_backup : std_logic;
signal read_address : std_logic_vector(0 to
ADDR_CNTR_WIDTH-1);
signal sig_zeros : std_logic_vector(0 to
ADDR_CNTR_WIDTH-1);
signal inc_nocc : std_logic;
signal inc_nocc_by_2 : std_logic;
signal sig_normal_occupancy : std_logic_vector(0 to
OCC_CNTR_WIDTH-1);
signal occ_load_value : std_logic_vector(0 to
OCC_CNTR_WIDTH-1);
Signal burst_ack_inhib : std_logic;
signal int_rdack : std_logic;
Signal valid_read : std_logic;
Signal back_to_back_rd : std_logic;
Signal rdreq_dly1 : std_logic;
Signal dly_mux_in :std_logic_vector(0 to
DLY_MUX_WIDTH-1);
Signal dly_mux_out :std_logic_vector(0 to
DLY_MUX_WIDTH-1);
Signal rdack_dly1 : std_logic;
Signal rdack_i : std_logic;
Signal bkup_recover : std_logic;
begin
--Misc I/O Assignments
Full <= int_full
or int_full_dly1
or int_full_dly2;
Almost_Full <= int_almost_full
and not(int_full_dly1)
and not(int_full_dly2);
Wr_Addr <= write_address;
Rd_Addr <= read_address;
WrAck <= inc_wr_addr ; -- currently combinitorial
RdAck <= rdack_i;
rdack_i <= int_rdack
and Rdreq -- RdReq used to terminate acknowledge
and not(burst_ack_inhib);
-- needed during burst to fill
-- pipeline (1 clock) out of DPort
-- Block
DeadLock <= int_full and int_empty; -- both full and empty
-- at the same time
DP_core_rden <= not(int_empty)-- assert read enable when not
or Bus_rst; -- empty or during reset
DP_core_wren <= not(int_full) -- assert write enable when not
or Bus_rst; -- full or during reset
base_occupancy <= sig_normal_occupancy;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_RDACK
--
-- Process Description:
-- Register the RdAck by one clock.
--
-------------------------------------------------------------
REG_RDACK : process (bus_clk)
begin
if (Bus_Clk'event and Bus_Clk = '1') then
if (Bus_Rst = '1') then
rdack_dly1 <= '0';
else
rdack_dly1 <= rdack_i;
end if;
else
null;
end if;
end process REG_RDACK;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: GEN_BKUP_RECOVER
--
-- Process Description:
-- This process generates a signal indicating the required
-- recovery cycle after a backup condition has occured.
--
-------------------------------------------------------------
GEN_BKUP_RECOVER : process (bus_clk)
begin
if (Bus_Clk'event and Bus_Clk = '1') then
if (Bus_Rst = '1') then
bkup_recover <= '0';
else
bkup_recover <= rd_backup;
end if;
else
null;
end if;
end process GEN_BKUP_RECOVER;
----------------------------------------------------------------------
-- Compensate for timing differences needed for Empty flag and
-- Occupancy outputs during single cycle reads and burst reads
-- No delay on single cycle reads
-- 1 clock delay during burst reads
dly_mux_in(0) <= int_empty;
dly_mux_in(1) <= int_almost_empty;
dly_mux_in(2 to DLY_MUX_WIDTH-1) <= sig_normal_occupancy;
I_DELAY_MUX : entity opb_v20_v1_10_d.pf_dly1_mux
Generic map(C_MUX_WIDTH => DLY_MUX_WIDTH
)
port map(
Clk => Bus_clk,-- : in std_logic;
Rst => Bus_rst,-- : In std_logic;
dly_sel1 => '0', --burst_ack_inhib,-- : in std_logic;
dly_sel2 => back_to_back_rd,-- : in std_logic;
Inputs => dly_mux_in,-- : in std_logic_vector;
Y_out => dly_mux_out-- : out std_logic_vector
);
Empty <= dly_mux_out(0);
Almost_empty <= dly_mux_out(1);
Occupancy <= dly_mux_out(2 to DLY_MUX_WIDTH-1);
---------------------------------------------------------------------
------------------------------------------------------------------
-- Instantiate the Occupancy Counter relative to normal operations
-- This counter establishes the empty flag states.
------------------------------------------------------------------
inc_nocc_by_2 <= decr_rd_addr and inc_wr_addr;
inc_nocc <= decr_rd_addr or inc_wr_addr;
occ_load_value <= (others => '0');
I_NORMAL_OCCUPANCY : entity opb_v20_v1_10_d.pf_occ_counter_top
generic map(
C_COUNT_WIDTH => OCC_CNTR_WIDTH
)
port map(
Clk => Bus_clk,
Rst => Bus_rst,
Load_Enable => '0',
Load_value => occ_load_value,
Count_Down => inc_rd_addr,
Count_Up => inc_nocc,
By_2 => inc_nocc_by_2,
Count_Out => sig_normal_occupancy,
almost_full => int_almost_full,
full => int_full,
almost_empty => int_almost_empty,
empty => int_empty
);
------------------------------------------------------------------
-- Register and delay Full/Empty flags
------------------------------------------------------------------
REGISTER_FLAG_PROCESS : process (Bus_rst, Bus_clk)
Begin
If (Bus_rst = '1') Then
int_empty_dly1 <= '1';
int_almost_empty_dly1 <= '0';
int_rdack <= '0';
int_full_dly1 <= '0';
int_full_dly2 <= '0';
--sig_normal_occupancy_dly1 <= (others => '0');
Elsif (Bus_clk'EVENT and Bus_clk = '1') Then
int_empty_dly1 <= int_empty;
int_almost_empty_dly1 <= int_almost_empty;
int_rdack <= not(int_empty)
and not(rd_backup);
int_full_dly1 <= int_full;
int_full_dly2 <= int_full_dly1;
--sig_normal_occupancy_dly1 <= sig_normal_occupancy;
else
null;
End if;
End process; -- REGISTER_FLAG_PROCESS
------------------------------------------------------------------
-- Write Address Counter Logic
inc_wr_addr <= WrReq
and not(int_full)
and not(int_full_dly1)
and not(int_full_dly2);
sig_zeros <= (others => '0');
I_WRITE_ADDR_CNTR : entity opb_v20_v1_10_d.pf_counter_top
Generic Map (
C_COUNT_WIDTH => ADDR_CNTR_WIDTH
)
Port Map (
Clk => Bus_clk,
Rst => Bus_rst,
Load_Enable => '0',
Load_value => sig_zeros,
Count_Down => '0',
Count_Up => inc_wr_addr,
Count_Out => write_address
);
-- end of write counter logic
------------------------------------------------------------------
------------------------------------------------------------------
-- Read Address Counter Logic
---------------------------------------------------------------
-- Detect Back to back reads
---------------------------------------------------------------
BACK_TO_BACK_DETECT : process (Bus_rst, Bus_clk)
Begin
If (Bus_rst = '1') Then
valid_read <= '0';
back_to_back_rd <= '0';
Elsif (Bus_clk'EVENT and Bus_clk = '1') Then
if (inc_rd_addr = '1') Then
valid_read <= '1';
back_to_back_rd <= valid_read;
else
valid_read <= '0';
back_to_back_rd <= '0';
End if;
else
null;
End if;
End process; -- BACK_TO_BACK_DETECT
-- Must create a rdack inhibit the second clock into a burst
-- read to allow the data pipeline to catch up.
--
burst_ack_inhib <= RdReq
and valid_read
and not(back_to_back_rd) -- not yet detected a back to back
and rdack_dly1; -- must have ack'd a read one clock before
---------------------------------------------------------------
-- Register the IP Read Request for use in read counter backup
-- function
---------------------------------------------------------------
REG_READ_REQUEST : process (Bus_rst, Bus_clk)
Begin
If (Bus_rst = '1') Then
rdreq_dly1 <= '0';
Elsif (Bus_clk'EVENT and Bus_clk = '1') Then
rdreq_dly1 <= RdReq;
else
null;
End if;
End process; -- REG_READ_REQUEST
inc_rd_addr <= RdReq
And not(bkup_recover) -- DET added for
and not(int_empty)
and not(int_empty_dly1);
rd_backup <= not(RdReq)
And back_to_back_rd
-- DET Test fix for --And not(int_empty);
And not(int_empty_dly1);
decr_rd_addr <= rd_backup;
I_READ_ADDR_CNTR : entity opb_v20_v1_10_d.pf_counter_top
Generic Map ( C_COUNT_WIDTH => ADDR_CNTR_WIDTH
)
Port Map (
Clk => Bus_clk,
Rst => Bus_rst,
Load_Enable => '0',
Load_value => sig_zeros,
Count_Down => decr_rd_addr,
Count_Up => inc_rd_addr,
Count_Out => read_address
);
-- end read address counter logic
------------------------------------------------------------------
end generate OMIT_PACKET_FEATURES;
INCLUDE_VACANCY : if (C_INCLUDE_VACANCY = true) generate
Constant REGISTER_VACANCY : boolean := false;
Signal slv_max_vacancy : std_logic_vector(0 to OCC_CNTR_WIDTH-1);
Signal int_vacancy : std_logic_vector(0 to OCC_CNTR_WIDTH-1);
begin
Vacancy <= int_vacancy; -- set to zeroes for now.
slv_max_vacancy <= CONV_STD_LOGIC_VECTOR(MAX_OCCUPANCY, OCC_CNTR_WIDTH);
I_VAC_CALC : entity opb_v20_v1_10_d.pf_adder
generic map(
C_REGISTERED_RESULT => REGISTER_VACANCY,
C_COUNT_WIDTH => OCC_CNTR_WIDTH
)
port map (
Clk => Bus_clk,
Rst => Bus_rst,
Ain => slv_max_vacancy,
Bin => base_occupancy,
Add_sub_n => '0', -- always subtract
result_out => int_vacancy
);
end generate; -- INCLUDE_VACANCY
OMIT_VACANCY : if (C_INCLUDE_VACANCY = false) generate
Signal int_vacancy : std_logic_vector(0 to OCC_CNTR_WIDTH-1);
begin
int_vacancy <= (others => '0');
Vacancy <= int_vacancy; -- set to zeroes for now.
end generate; -- INCLUDE_VACANCY
end implementation;
|
bsd-3-clause
|
masson2013/heterogeneous_hthreads
|
src/hardware/MyRepository/pcores/plb_sync_manager_v1_00_a/hdl/vhdl/master.vhd
|
10
|
10243
|
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use work.common.all;
entity master is
generic
(
C_BASEADDR : std_logic_vector := x"00000000";
C_HIGHADDR : std_logic_vector := x"FFFFFFFF";
C_SCHED_BASEADDR : std_logic_vector := x"00000000";
C_RESULT_BASEADDR : std_logic_vector := x"00000000";
C_NUM_THREADS : integer := 256;
C_NUM_MUTEXES : integer := 64;
C_AWIDTH : integer := 32;
C_DWIDTH : integer := 32;
C_MAX_AR_DWIDTH : integer := 32;
C_NUM_ADDR_RNG : integer := 6;
C_NUM_CE : integer := 4
);
port
(
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
-- Bus2IP_MstLastAck : in std_logic;
-- IP2Bus_Addr : out std_logic_vector(0 to C_AWIDTH-1);
-- IP2Bus_MstBE : out std_logic_vector(0 to C_DWIDTH/8-1);
-- IP2Bus_MstBurst : out std_logic;
-- IP2Bus_MstBusLock : out std_logic;
-- IP2Bus_MstRdReq : out std_logic;
-- IP2Bus_MstWrReq : out std_logic;
-- IP2IP_Addr : out std_logic_vector(0 to C_AWIDTH-1);
IP2Bus_MstRd_Req : out std_logic;
IP2Bus_MstWr_Req : out std_logic;
IP2Bus_Mst_Addr : out std_logic_vector(0 to C_AWIDTH-1);
IP2Bus_Mst_BE : out std_logic_vector(0 to C_DWIDTH/8-1);
IP2Bus_Mst_Lock : out std_logic;
IP2Bus_Mst_Reset : out std_logic;
Bus2IP_Mst_CmdAck : in std_logic;
Bus2IP_Mst_Cmplt : in std_logic;
Bus2IP_Mst_Error : in std_logic;
Bus2IP_Mst_Rearbitrate : in std_logic;
Bus2IP_Mst_Cmd_Timeout : in std_logic;
Bus2IP_MstRd_d : in std_logic_vector(0 to C_DWIDTH-1);
Bus2IP_MstRd_src_rdy_n : in std_logic;
IP2Bus_MstWr_d : out std_logic_vector(0 to C_DWIDTH-1);
Bus2IP_MstWr_dst_rdy_n : in std_logic;
system_reset : in std_logic;
system_resetdone : out std_logic;
send_ena : in std_logic;
send_id : in std_logic_vector(0 to log2(C_NUM_THREADS)-1);
send_ack : out std_logic;
saddr : out std_logic_vector(0 to log2(C_NUM_THREADS)-1);
sena : out std_logic;
swea : out std_logic;
sonext : out std_logic_vector(0 to log2(C_NUM_THREADS)-1);
sinext : in std_logic_vector(0 to log2(C_NUM_THREADS)-1)
);
end master;
architecture behavioral of master is
constant THR_BIT : integer := log2( C_NUM_THREADS );
type send_state is
(
IDLE,
SENDING,
FINISH
);
type queue_state is
(
IDLE,
DONE,
GETWAIT,
GETDONE
);
signal mst_cmplt : std_logic;
signal send_cs : send_state;
signal send_ns : send_state;
signal queue_cs : queue_state;
signal queue_ns : queue_state;
signal send_rdy : std_logic;
signal send_valid : std_logic;
signal send_validn : std_logic;
signal send_cur : std_logic_vector(0 to THR_BIT-1);
signal send_curn : std_logic_vector(0 to THR_BIT-1);
signal send_first : std_logic_vector(0 to THR_BIT-1);
signal send_firstn : std_logic_vector(0 to THR_BIT-1);
signal send_last : std_logic_vector(0 to THR_BIT-1);
signal send_lastn : std_logic_vector(0 to THR_BIT-1);
signal send_count : std_logic_vector(0 to THR_BIT-1);
signal send_countn : std_logic_vector(0 to THR_BIT-1);
begin
-- System reset only takes one clock cycle so were always "done"
system_resetdone <= '1';
queue_update : process(Bus2IP_Clk) is
begin
if( rising_edge(Bus2IP_Clk) ) then
if( Bus2IP_Reset = '1' or system_reset = '1' ) then
queue_cs <= IDLE;
send_count <= (others => '0');
send_first <= (others => '0');
send_last <= (others => '0');
send_cur <= (others => '0');
send_valid <= '0';
else
queue_cs <= queue_ns;
send_count <= send_countn;
send_first <= send_firstn;
send_last <= send_lastn;
send_cur <= send_curn;
send_valid <= send_validn;
end if;
end if;
end process queue_update;
queue_controller : process(Bus2IP_Clk,queue_cs, send_cur, send_last, send_first, send_count, send_ena, send_id, send_rdy, sinext) is
begin
sena <= '0';
swea <= '0';
saddr <= (others => '0');
sonext <= (others => '0');
queue_ns <= queue_cs;
send_curn <= send_cur;
send_lastn <= send_last;
send_firstn <= send_first;
send_countn <= send_count;
send_validn <= '0';
case queue_cs is
when IDLE =>
if( send_ena = '1' ) then
if( send_count = zero(THR_BIT) ) then
send_firstn <= send_id;
else
sena <= '1';
swea <= '1';
saddr <= send_last;
sonext <= send_id;
end if;
send_lastn <= send_id;
send_countn <= send_count+1;
send_ack <= '1';
queue_ns <= DONE;
elsif( send_rdy = '1' and send_count /= zero(THR_BIT) ) then
send_curn <= send_first;
send_validn <= '1';
sena <= '1';
saddr <= send_first;
queue_ns <= GETWAIT;
end if;
when DONE =>
send_ack <= '1';
if( send_ena = '0' ) then
queue_ns <= IDLE;
end if;
when GETWAIT => null;
queue_ns <= GETDONE;
when GETDONE =>
send_firstn <= sinext;
send_countn <= send_count-1;
queue_ns <= IDLE;
end case;
end process queue_controller;
send_update : process (Bus2IP_Clk,send_ns) is
begin
if( rising_edge(Bus2IP_Clk) ) then
if( Bus2IP_Reset = '1' or system_reset = '1' ) then
send_cs <= IDLE;
else
send_cs <= send_ns;
end if;
end if;
end process send_update;
send_controller : process (Bus2IP_Mst_CmdAck, Bus2IP_MstRd_src_rdy_n, send_cs,send_valid,send_cur) is
begin
send_ns <= send_cs;
send_rdy <= '0';
IP2Bus_Mst_Addr <= (others => '0');
IP2Bus_Mst_BE <= (others => '0');
IP2Bus_MstRd_Req <= '0';
case send_cs is
when IDLE =>
send_rdy <= '1';
if( send_valid = '1' ) then
send_ns <= SENDING;
end if;
when SENDING =>
-- Capture the Bus2IP_Mst_Cmplt value for later.
if (mst_cmplt = '0') then
mst_cmplt <= Bus2IP_Mst_Cmplt;
end if;
if (Bus2IP_Mst_CmdAck = '1') then
send_ns <= FINISH;
else
IP2Bus_Mst_Addr <= add_thread(C_SCHED_BASEADDR,send_cur);
IP2Bus_MstRd_Req <= '1';
IP2Bus_Mst_BE <= "1111";
send_ns <= SENDING;
end if;
when FINISH =>
if ((mst_cmplt = '1') or (Bus2IP_Mst_Cmplt = '1')) then
send_ns <= IDLE;
else
send_ns <= FINISH;
end if;
end case;
end process send_controller;
end behavioral;
|
bsd-3-clause
|
masson2013/heterogeneous_hthreads
|
src/hardware/MyRepository/pcores/axi_hthread_cores/proc_common_v3_00_a/hdl/vhdl/pf_dpram_select.vhd
|
2
|
118964
|
-------------------------------------------------------------------------------
-- $Id: pf_dpram_select.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pf_dpram_select.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pf_dpram_select.vhd
--
-- Description: This vhdl design file uses three input parameters describing
-- the desired storage depth, data width, and FPGA family type.
-- From these, the design selects the optimum Block RAM
-- primitive for the basic storage element and connects them
-- in parallel to accomodate the desired data width.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pf_dpram_select.vhd
--
-------------------------------------------------------------------------------
-- Author: D. Thorpe
-- Revision: $Revision: 1.1.4.1 $
-- Date: $Date: 2010/09/14 22:35:47 $
--
-- History:
-- DET Oct. 7, 2001 First Version
-- - Adopted design concepts from Goran Bilski's
-- opb_bram.vhd design in the formulation of this
-- design for the Mauna Loa packet FIFO dual port
-- core function.
--
-- DET Oct-31-2001
-- - Changed the generic input parameter C_FAMILY of type string
-- back to the boolean type parameter C_VIRTEX_II. XST support
-- change.
--
--
-- DET 1/17/2008 v3_00_a
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library unisim;
use unisim.all; -- uses BRAM primitives
-------------------------------------------------------------------------------
entity pf_dpram_select is
generic (
C_DP_DATA_WIDTH : Integer := 32;
C_DP_ADDRESS_WIDTH : Integer := 9;
C_VIRTEX_II : Boolean := true
);
port (
-- Write Port signals
Wr_rst : In std_logic;
Wr_Clk : in std_logic;
Wr_Enable : In std_logic;
Wr_Req : In std_logic;
Wr_Address : in std_logic_vector(0 to C_DP_ADDRESS_WIDTH-1);
Wr_Data : In std_logic_vector(0 to C_DP_DATA_WIDTH-1);
-- Read Port Signals
Rd_rst : In std_logic;
Rd_Clk : in std_logic;
Rd_Enable : In std_logic;
Rd_Address : in std_logic_vector(0 to C_DP_ADDRESS_WIDTH-1);
Rd_Data : out std_logic_vector(0 to C_DP_DATA_WIDTH-1)
);
end entity pf_dpram_select;
architecture implementation of pf_dpram_select is
Type family_type is (
any ,
x4k ,
x4ke ,
x4kl ,
x4kex ,
x4kxl ,
x4kxv ,
x4kxla ,
spartan ,
spartanxl,
spartan2 ,
spartan2e,
virtex ,
virtexe ,
virtex2 ,
virtex2p ,
unsupported
);
Type bram_prim_type is (
use_srl ,
B4_S1_S1 ,
B4_S2_S2 ,
B4_S4_S4 ,
B4_S8_S8 ,
B4_S16_S16 ,
B16_S1_S1 ,
B16_S2_S2 ,
B16_S4_S4 ,
B16_S9_S9 ,
B16_S18_S18 ,
B16_S36_S36 ,
indeterminate
);
-----------------------------------------------------------------------------
-- This function converts the input C_VIRTEX_II boolean type to an enumerated
-- type. Only Virtex and Virtex II types are currently supported. This
-- used to convert a string to a family type function but string support in
-- the synthesis tools was found to be mutually exclusive between Synplicity
-- and XST.
-----------------------------------------------------------------------------
function get_prim_family (vertex2_select : boolean) return family_type is
Variable prim_family : family_type;
begin
If (vertex2_select) Then
prim_family := virtex2;
else
prim_family := virtex;
End if;
Return (prim_family);
end function get_prim_family;
-----------------------------------------------------------------------------
-- This function chooses the optimum BRAM primitive to utilize as
-- specified by the inputs for data depth, data width, and FPGA part family.
-----------------------------------------------------------------------------
function get_bram_primitive (target_depth: integer;
target_width: integer;
family : family_type )
return bram_prim_type is
Variable primitive : bram_prim_type;
begin
Case family Is
When virtex2p | virtex2 =>
Case target_depth Is
When 1 | 2 =>
primitive := indeterminate; -- depth is too small for BRAM
-- based fifo control logic
When 4 | 8 | 16 =>
-- primitive := use_srl; -- activate when SRL FIFO incorporated
Case target_width Is -- use BRAM for now
When 1 =>
primitive := B16_S1_S1;
When 2 =>
primitive := B16_S2_S2;
When 3 | 4 =>
primitive := B16_S4_S4;
When 5 | 6 | 7 | 8 | 9 =>
primitive := B16_S9_S9;
When 10 | 11 | 12 | 13 | 14 |
15 | 16 | 17 | 18 =>
primitive := B16_S18_S18;
When others =>
primitive := B16_S36_S36;
End case;
when 32 | 64 | 128 | 256 | 512 =>
Case target_width Is
When 1 =>
primitive := B16_S1_S1;
When 2 =>
primitive := B16_S2_S2;
When 3 | 4 =>
primitive := B16_S4_S4;
When 5 | 6 | 7 | 8 | 9 =>
primitive := B16_S9_S9;
When 10 | 11 | 12 | 13 | 14 |
15 | 16 | 17 | 18 =>
primitive := B16_S18_S18;
When others =>
primitive := B16_S36_S36;
End case;
When 1024 =>
Case target_width Is
When 1 =>
primitive := B16_S1_S1;
When 2 =>
primitive := B16_S2_S2;
When 3 | 4 =>
primitive := B16_S4_S4;
When 5 | 6 | 7 | 8 | 9 =>
primitive := B16_S9_S9;
When others =>
primitive := B16_S18_S18;
End case;
When 2048 =>
Case target_width Is
When 1 =>
primitive := B16_S1_S1;
When 2 =>
primitive := B16_S2_S2;
When 3 | 4 =>
primitive := B16_S4_S4;
When others =>
primitive := B16_S9_S9;
End case;
When 4096 =>
Case target_width Is
When 1 =>
primitive := B16_S1_S1;
When 2 =>
primitive := B16_S2_S2;
When others =>
primitive := B16_S4_S4;
End case;
When 8192 =>
Case target_width Is
When 1 =>
primitive := B16_S1_S1;
When others =>
primitive := B16_S2_S2;
End case;
When 16384 =>
primitive := B16_S1_S1;
When others =>
primitive := indeterminate;
End case;
When spartan2 | spartan2e | virtex | virtexe =>
Case target_depth Is
When 1 | 2 =>
primitive := indeterminate; -- depth is too small for BRAM
-- based fifo control logic
When 4 | 8 | 16 =>
-- primitive := use_srl; -- activate this when SRL FIFO is
-- incorporated
Case target_width Is -- use BRAM for now
When 1 =>
primitive := B4_S1_S1;
When 2 =>
primitive := B4_S2_S2;
When 3 | 4 =>
primitive := B4_S4_S4;
When 5 | 6 | 7 | 8 =>
primitive := B4_S8_S8;
When others =>
primitive := B4_S16_S16;
End case;
when 32 | 64 | 128 | 256 =>
Case target_width Is
When 1 =>
primitive := B4_S1_S1;
When 2 =>
primitive := B4_S2_S2;
When 3 | 4 =>
primitive := B4_S4_S4;
When 5 | 6 | 7 | 8 =>
primitive := B4_S8_S8;
When others =>
primitive := B4_S16_S16;
End case;
when 512 =>
Case target_width Is
When 1 =>
primitive := B4_S1_S1;
When 2 =>
primitive := B4_S2_S2;
When 3 | 4 =>
primitive := B4_S4_S4;
When others =>
primitive := B4_S8_S8;
End case;
When 1024 =>
Case target_width Is
When 1 =>
primitive := B4_S1_S1;
When 2 =>
primitive := B4_S2_S2;
When others =>
primitive := B4_S4_S4;
End case;
When 2048 =>
Case target_width Is
When 1 =>
primitive := B4_S1_S1;
When others =>
primitive := B4_S2_S2;
End case;
When 4096 =>
primitive := B4_S1_S1;
When others =>
primitive := indeterminate;
End case;
When others =>
primitive := indeterminate;
End case;
Return primitive;
end function get_bram_primitive;
-----------------------------------------------------------------------------
-- This function calculates the number of BRAM primitives required as
-- specified by the inputs for data width and BRAM primitive type.
-----------------------------------------------------------------------------
function get_num_prims (bram_prim : bram_prim_type;
mem_width : integer)
return integer is
Variable bram_num : integer;
begin
Case bram_prim Is
When B16_S1_S1 | B4_S1_S1 =>
bram_num := mem_width;
When B16_S2_S2 | B4_S2_S2 =>
bram_num := (mem_width+1)/2;
When B16_S4_S4 | B4_S4_S4 =>
bram_num := (mem_width+3)/4;
When B4_S8_S8 =>
bram_num := (mem_width+7)/8;
When B16_S9_S9 =>
bram_num := (mem_width+8)/9;
When B4_S16_S16 =>
bram_num := (mem_width+15)/16;
When B16_S18_S18 =>
bram_num := (mem_width+17)/18;
When B16_S36_S36 =>
bram_num := (mem_width+35)/36;
When others =>
bram_num := 1;
End case;
Return (bram_num);
end function get_num_prims;
-- Now set the global CONSTANTS needed for IF-Generates
-- Determine the number of BRAM storage locations needed
constant FIFO_DEPTH : Integer := 2**C_DP_ADDRESS_WIDTH;
-- Convert the input C_VIRTEX_II generic boolean to enumerated type
Constant BRAM_FAMILY : family_type :=
get_prim_family(C_VIRTEX_II);
-- Select the optimum BRAM primitive to use
constant BRAM_PRIMITIVE : bram_prim_type :=
get_bram_primitive(FIFO_DEPTH,
C_DP_DATA_WIDTH,
BRAM_FAMILY);
-- Calculate how many of the selected primitives are needed
-- to populate the desired data width
constant BRAM_NUM : integer :=
get_num_prims(BRAM_PRIMITIVE,
C_DP_DATA_WIDTH);
begin -- architecture
----------------------------------------------------------------------------
-- Using VII 512 x 36 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S36_S36 : if (BRAM_PRIMITIVE = B16_S36_S36) generate
component RAMB16_S36_S36
port (DIA : in STD_LOGIC_VECTOR (31 downto 0);
DIB : in STD_LOGIC_VECTOR (31 downto 0);
DIPA : in STD_LOGIC_VECTOR (3 downto 0);
DIPB : in STD_LOGIC_VECTOR (3 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in STD_LOGIC_VECTOR (8 downto 0);
ADDRB : in STD_LOGIC_VECTOR (8 downto 0);
DOA : out STD_LOGIC_VECTOR (31 downto 0);
DOB : out STD_LOGIC_VECTOR (31 downto 0);
DOPA : out STD_LOGIC_VECTOR (3 downto 0);
DOPB : out STD_LOGIC_VECTOR (3 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 9; -- 512 deep
Constant PRIM_PDBUS_WIDTH : integer := 4; -- 4 parity data bits
Constant PRIM_DBUS_WIDTH : integer := 32; -- 4 parity data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
type pdbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_512x32 : RAMB16_S36_S36
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
DIPA => slice_a_pdbus_in(i),
DIPB => slice_b_pdbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i),
DOPA => slice_a_pdbus_out(i),
DOPB => slice_b_pdbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S36_S36;
--==========================================================================
----------------------------------------------------------------------------
-- Using VII 1024 x 18 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S18_S18 : if (BRAM_PRIMITIVE = B16_S18_S18) generate
component RAMB16_S18_S18
port (DIA : in STD_LOGIC_VECTOR (15 downto 0);
DIB : in STD_LOGIC_VECTOR (15 downto 0);
DIPA : in STD_LOGIC_VECTOR (1 downto 0);
DIPB : in STD_LOGIC_VECTOR (1 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in STD_LOGIC_VECTOR (9 downto 0);
ADDRB : in STD_LOGIC_VECTOR (9 downto 0);
DOA : out STD_LOGIC_VECTOR (15 downto 0);
DOB : out STD_LOGIC_VECTOR (15 downto 0);
DOPA : out STD_LOGIC_VECTOR (1 downto 0);
DOPB : out STD_LOGIC_VECTOR (1 downto 0)
);
end component;
Constant PRIM_ADDR_WIDTH : integer := 10; -- 1024 deep
Constant PRIM_PDBUS_WIDTH : integer := 2; -- 2 parity data bits
Constant PRIM_DBUS_WIDTH : integer := 16; -- 16 data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
type pdbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_1024x18 : RAMB16_S18_S18
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
DIPA => slice_a_pdbus_in(i),
DIPB => slice_b_pdbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i),
DOPA => slice_a_pdbus_out(i),
DOPB => slice_b_pdbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S18_S18;
--==========================================================================
----------------------------------------------------------------------------
-- Using VII 2048 x 9 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S9_S9 : if (BRAM_PRIMITIVE = B16_S9_S9) generate
component RAMB16_S9_S9
port (
DIA : in std_logic_vector (7 downto 0);
DIB : in std_logic_vector (7 downto 0);
DIPA : in std_logic_vector (0 downto 0);
DIPB : in std_logic_vector (0 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (10 downto 0);
ADDRB : in std_logic_vector (10 downto 0);
DOA : out std_logic_vector (7 downto 0);
DOB : out std_logic_vector (7 downto 0);
DOPA : out std_logic_vector (0 downto 0);
DOPB : out std_logic_vector (0 downto 0) );
end component;
Constant PRIM_ADDR_WIDTH : integer := 11; -- 2048 deep
Constant PRIM_PDBUS_WIDTH : integer := 1; -- 1 parity data bit
Constant PRIM_DBUS_WIDTH : integer := 8; -- 8 data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
type pdbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_2048x9 : RAMB16_S9_S9
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
DIPA => slice_a_pdbus_in(i),
DIPB => slice_b_pdbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i),
DOPA => slice_a_pdbus_out(i),
DOPB => slice_b_pdbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S9_S9;
--==========================================================================
----------------------------------------------------------------------------
-- Using VII 4096 x 4 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S4_S4 : if (BRAM_PRIMITIVE = B16_S4_S4) generate
component RAMB16_S4_S4
port (
DIA : in std_logic_vector (3 downto 0);
DIB : in std_logic_vector (3 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (11 downto 0);
ADDRB : in std_logic_vector (11 downto 0);
DOA : out std_logic_vector (3 downto 0);
DOB : out std_logic_vector (3 downto 0) );
end component;
Constant PRIM_ADDR_WIDTH : integer := 12; -- 4096 deep
Constant PRIM_PDBUS_WIDTH : integer := 0; -- 0 parity data bits
Constant PRIM_DBUS_WIDTH : integer := 4; -- 4 data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--type pdbus_slice_array is array(BRAM_NUM downto 1) of
-- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
--slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
--slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_4096x4 : RAMB16_S4_S4
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S4_S4;
--==========================================================================
----------------------------------------------------------------------------
-- Using VII 8192 x 2 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S2_S2 : if (BRAM_PRIMITIVE = B16_S2_S2) generate
component RAMB16_S2_S2
port (
DIA : in std_logic_vector (1 downto 0);
DIB : in std_logic_vector (1 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (12 downto 0);
ADDRB : in std_logic_vector (12 downto 0);
DOA : out std_logic_vector (1 downto 0);
DOB : out std_logic_vector (1 downto 0) );
end component;
Constant PRIM_ADDR_WIDTH : integer := 13; -- 8192 deep
Constant PRIM_PDBUS_WIDTH : integer := 0; -- 0 parity data bits
Constant PRIM_DBUS_WIDTH : integer := 2; -- 2 data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--type pdbus_slice_array is array(BRAM_NUM downto 1) of
-- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
--slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
--slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_8192x2 : RAMB16_S2_S2
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S2_S2;
--==========================================================================
----------------------------------------------------------------------------
-- Using VII 16384 x 1 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB16_S1_S1 : if (BRAM_PRIMITIVE = B16_S1_S1) generate
component RAMB16_S1_S1
port (
DIA : in std_logic_vector (0 downto 0);
DIB : in std_logic_vector (0 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (13 downto 0);
ADDRB : in std_logic_vector (13 downto 0);
DOA : out std_logic_vector (0 downto 0);
DOB : out std_logic_vector (0 downto 0) );
end component;
Constant PRIM_ADDR_WIDTH : integer := 14; -- 16384 deep
Constant PRIM_PDBUS_WIDTH : integer := 0; -- 0 parity data bits
Constant PRIM_DBUS_WIDTH : integer := 1; -- 1 data bits
Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH
+ PRIM_PDBUS_WIDTH; -- (data + parity)
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--type pdbus_slice_array is array(BRAM_NUM downto 1) of
-- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
--Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0);
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= Wr_rst;
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= Rd_rst;
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
--slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i);
port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
--slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH);
slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH);
--port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto
-- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i);
port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto
(i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB16_16384x1 : RAMB16_S1_S1
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
SSRA => port_a_ssr,
SSRB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB16_S1_S1;
--==========================================================================
-- End of Virtex-II and Virtex-II Pro support
--///////////////////////////////////////////////////////////////////////////
--///////////////////////////////////////////////////////////////////////////
-- Start Spartan-II, Spartan-IIE, Virtex, and VirtexE support
----------------------------------------------------------------------------
-- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE
-- 4096 x 1 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB4_S1_S1 : if (BRAM_PRIMITIVE = B4_S1_S1) generate
component RAMB4_S1_S1
port (
DIA : in std_logic_vector (0 downto 0);
DIB : in std_logic_vector (0 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
RSTA : in std_logic;
RSTB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (11 downto 0);
ADDRB : in std_logic_vector (11 downto 0);
DOA : out std_logic_vector (0 downto 0);
DOB : out std_logic_vector (0 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 12; -- 4096 deep
Constant PRIM_DBUS_WIDTH : integer := 1; -- 1 data bit
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array;
Signal slice_a_dbus_out : dbus_slice_array;
Signal slice_b_dbus_in : dbus_slice_array;
Signal slice_b_dbus_out : dbus_slice_array;
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= wr_rst; -- no output reset value
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= rd_rst; -- no output reset value
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_dbus_in(i) <= port_a_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_a_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_dbus_in(i) <= port_b_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_b_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB4_4096x1 : RAMB4_S1_S1
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
RSTA => port_a_ssr,
RSTB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB4_S1_S1;
--==========================================================================
----------------------------------------------------------------------------
-- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE
-- 2048 x 2 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB4_S2_S2 : if (BRAM_PRIMITIVE = B4_S2_S2) generate
component RAMB4_S2_S2
port (
DIA : in std_logic_vector (1 downto 0);
DIB : in std_logic_vector (1 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
RSTA : in std_logic;
RSTB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (10 downto 0);
ADDRB : in std_logic_vector (10 downto 0);
DOA : out std_logic_vector (1 downto 0);
DOB : out std_logic_vector (1 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 11; -- 2048 deep
Constant PRIM_DBUS_WIDTH : integer := 2; -- 2 data bits
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array;
Signal slice_a_dbus_out : dbus_slice_array;
Signal slice_b_dbus_in : dbus_slice_array;
Signal slice_b_dbus_out : dbus_slice_array;
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= wr_rst; -- no output reset value
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= rd_rst; -- no output reset value
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_dbus_in(i) <= port_a_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_a_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_dbus_in(i) <= port_b_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_b_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB4_2048x2 : RAMB4_S2_S2
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
RSTA => port_a_ssr,
RSTB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB4_S2_S2;
--==========================================================================
----------------------------------------------------------------------------
-- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE
-- 1024 x 4 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB4_S4_S4 : if (BRAM_PRIMITIVE = B4_S4_S4) generate
component RAMB4_S4_S4
port (
DIA : in std_logic_vector (3 downto 0);
DIB : in std_logic_vector (3 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
RSTA : in std_logic;
RSTB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (9 downto 0);
ADDRB : in std_logic_vector (9 downto 0);
DOA : out std_logic_vector (3 downto 0);
DOB : out std_logic_vector (3 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 10; -- 1024 deep
Constant PRIM_DBUS_WIDTH : integer := 4; -- 4 data bits
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array;
Signal slice_a_dbus_out : dbus_slice_array;
Signal slice_b_dbus_in : dbus_slice_array;
Signal slice_b_dbus_out : dbus_slice_array;
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= wr_rst; -- no output reset value
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= rd_rst; -- no output reset value
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_dbus_in(i) <= port_a_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_a_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_dbus_in(i) <= port_b_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_b_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB4_1024x4 : RAMB4_S4_S4
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
RSTA => port_a_ssr,
RSTB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB4_S4_S4;
--==========================================================================
----------------------------------------------------------------------------
-- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE
-- 512 x 8 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB4_S8_S8 : if (BRAM_PRIMITIVE = B4_S8_S8) generate
component RAMB4_S8_S8
port (
DIA : in std_logic_vector (7 downto 0);
DIB : in std_logic_vector (7 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
RSTA : in std_logic;
RSTB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in std_logic_vector (8 downto 0);
ADDRB : in std_logic_vector (8 downto 0);
DOA : out std_logic_vector (7 downto 0);
DOB : out std_logic_vector (7 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 9; -- 512 deep
Constant PRIM_DBUS_WIDTH : integer := 8; -- 8 data bits
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array;
Signal slice_a_dbus_out : dbus_slice_array;
Signal slice_b_dbus_in : dbus_slice_array;
Signal slice_b_dbus_out : dbus_slice_array;
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= wr_rst; -- no output reset value
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= rd_rst; -- no output reset value
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_dbus_in(i) <= port_a_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_a_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_dbus_in(i) <= port_b_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_b_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB4_512x8 : RAMB4_S8_S8
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
RSTA => port_a_ssr,
RSTB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB4_S8_S8;
--==========================================================================
----------------------------------------------------------------------------
-- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE
-- 256 x 16 Dual Port Primitive
----------------------------------------------------------------------------
Using_RAMB4_S16_S16 : if (BRAM_PRIMITIVE = B4_S16_S16) generate
component RAMB4_S16_S16
port (DIA : in STD_LOGIC_VECTOR (15 downto 0);
DIB : in STD_LOGIC_VECTOR (15 downto 0);
ENA : in std_logic;
ENB : in std_logic;
WEA : in std_logic;
WEB : in std_logic;
RSTA : in std_logic;
RSTB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
ADDRA : in STD_LOGIC_VECTOR (7 downto 0);
ADDRB : in STD_LOGIC_VECTOR (7 downto 0);
DOA : out STD_LOGIC_VECTOR (15 downto 0);
DOB : out STD_LOGIC_VECTOR (15 downto 0));
end component;
Constant PRIM_ADDR_WIDTH : integer := 8; -- 256 deep
Constant PRIM_DBUS_WIDTH : integer := 16; -- 16 data bits
Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH;
type dbus_slice_array is array(BRAM_NUM downto 1) of
std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0);
Signal slice_a_dbus_in : dbus_slice_array;
Signal slice_a_dbus_out : dbus_slice_array;
Signal slice_b_dbus_in : dbus_slice_array;
Signal slice_b_dbus_out : dbus_slice_array;
Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic;
signal port_a_ssr : std_logic;
signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic;
signal port_b_ssr : std_logic;
begin -- generate
port_a_enable <= Wr_Enable;
port_a_wr_enable <= Wr_Req;
port_a_ssr <= wr_rst; -- no output reset value
port_b_data_in <= (others => '0'); -- no input data to port B
port_b_enable <= Rd_Enable;
port_b_wr_enable <= '0'; -- no writing to port B
port_b_ssr <= rd_rst; -- no output reset value
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
Begin
port_a_data_in <= (others => '0');
for i in C_DP_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i);
Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i);
End loop;
End process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
Begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i);
End loop;
End process TRANSLATE_ADDRESS;
slice_a_abus <= port_a_addr;
slice_b_abus <= port_b_addr;
BRAM_LOOP : for i in BRAM_NUM downto 1 generate
slice_a_dbus_in(i) <= port_a_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_a_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i);
slice_b_dbus_in(i) <= port_b_data_in((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH);
port_b_data_out((i*PRIM_DBUS_WIDTH)-1 downto
(i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i);
-- Port A is fixed as the input (write) port
-- Port B is fixed as the output (read) port
I_DPB4_256x16 : RAMB4_S16_S16
port map(
DIA => slice_a_dbus_in(i),
DIB => slice_b_dbus_in(i),
ENA => port_a_enable,
ENB => port_b_enable,
WEA => port_a_wr_enable,
WEB => port_b_wr_enable,
RSTA => port_a_ssr,
RSTB => port_b_ssr,
CLKA => Wr_Clk,
CLKB => Rd_Clk,
ADDRA => slice_a_abus,
ADDRB => slice_b_abus,
DOA => slice_a_dbus_out(i),
DOB => slice_b_dbus_out(i)
);
End generate BRAM_LOOP;
end generate Using_RAMB4_S16_S16;
--==========================================================================
UNSUPPORTED_FAMILY : if (BRAM_PRIMITIVE = indeterminate) generate
begin
-- assert (false)
-- report "Unsupported Part Family Selected or FIFO Depth/Width is invalid!"
-- severity failure;
--
end generate UNSUPPORTED_FAMILY;
end architecture implementation;
|
bsd-3-clause
|
masson2013/heterogeneous_hthreads
|
src/platforms/xilinx/pr_6smp/design/pcores/plb_hthread_reset_core_v1_00_a/hdl/vhdl/user_logic.vhd
|
10
|
12147
|
------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: user_logic.vhd
-- Version: 1.00.a
-- Description: User logic.
-- Date: Wed Sep 24 16:19:15 2008 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
-- DO NOT EDIT ABOVE THIS LINE --------------------
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_SLV_DWIDTH -- Slave interface data bus width
-- C_NUM_REG -- Number of software accessible registers
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Reset -- Bus to IP reset
-- Bus2IP_Addr -- Bus to IP address bus
-- Bus2IP_Data -- Bus to IP data bus
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- IP2Bus_Data -- IP to Bus data bus
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- IP2Bus_Error -- IP to Bus error response
------------------------------------------------------------------------------
entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_SLV_DWIDTH : integer := 32;
C_NUM_REG : integer := 4
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
reset_port0 : out std_logic;
reset_response_port0 : in std_logic;
reset_port1 : out std_logic;
reset_response_port1 : in std_logic;
reset_port2 : out std_logic;
reset_response_port2 : in std_logic;
reset_port3 : out std_logic;
reset_response_port3 : in std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Addr : in std_logic_vector(0 to 31);
Bus2IP_Data : in std_logic_vector(0 to C_SLV_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_SLV_DWIDTH/8-1);
Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_REG-1);
Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_REG-1);
IP2Bus_Data : out std_logic_vector(0 to C_SLV_DWIDTH-1);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk : signal is "CLK";
attribute SIGIS of Bus2IP_Reset : signal is "RST";
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
--USER signal declarations added here, as needed for user logic
------------------------------------------
-- Signals for user logic slave model s/w accessible register example
------------------------------------------
signal slv_reg0 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg1 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg2 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg3 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg_write_sel : std_logic_vector(0 to 3);
signal slv_reg_read_sel : std_logic_vector(0 to 3);
signal slv_ip2bus_data : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;
begin
--USER logic implementation added here
------------------------------------------
-- Example code to read/write user logic slave model s/w accessible registers
--
-- Note:
-- The example code presented here is to show you one way of reading/writing
-- software accessible registers implemented in the user logic slave model.
-- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond
-- to one software accessible register by the top level template. For example,
-- if you have four 32 bit software accessible registers in the user logic,
-- you are basically operating on the following memory mapped registers:
--
-- Bus2IP_WrCE/Bus2IP_RdCE Memory Mapped Register
-- "1000" C_BASEADDR + 0x0
-- "0100" C_BASEADDR + 0x4
-- "0010" C_BASEADDR + 0x8
-- "0001" C_BASEADDR + 0xC
--
------------------------------------------
slv_reg_write_sel <= Bus2IP_WrCE(0 to 3);
slv_reg_read_sel <= Bus2IP_RdCE(0 to 3);
slv_write_ack <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1) or Bus2IP_WrCE(2) or Bus2IP_WrCE(3);
slv_read_ack <= Bus2IP_RdCE(0) or Bus2IP_RdCE(1) or Bus2IP_RdCE(2) or Bus2IP_RdCE(3);
-- Connect reset signal ports from reg0
reset_port0 <= slv_reg0(C_SLV_DWIDTH-1);
reset_port1 <= slv_reg0(C_SLV_DWIDTH-2);
reset_port2 <= slv_reg0(C_SLV_DWIDTH-3);
reset_port3 <= slv_reg0(C_SLV_DWIDTH-4);
-- Connect reg1 to reset responses so that they can be read
RESET_RESPONSE_REG : process (Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (Bus2IP_Reset = '1') then
slv_reg1 <= (others => '0');
else
slv_reg1(C_SLV_DWIDTH-1) <= reset_response_port0;
slv_reg1(C_SLV_DWIDTH-2) <= reset_response_port1;
slv_reg1(C_SLV_DWIDTH-3) <= reset_response_port2;
slv_reg1(C_SLV_DWIDTH-4) <= reset_response_port3;
end if;
end if;
end process RESET_RESPONSE_REG;
-- implement slave model software accessible register(s)
SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Reset = '1' then
slv_reg0 <= (others => '0');
-- slv_reg1 <= (others => '0');
slv_reg2 <= (others => '0');
slv_reg3 <= (others => '0');
else
case slv_reg_write_sel is
when "1000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg0(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
-- when "0100" =>
-- for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
-- if ( Bus2IP_BE(byte_index) = '1' ) then
-- slv_reg1(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
-- end if;
-- end loop;
when "0010" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg2(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "0001" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg3(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when others => null;
end case;
end if;
end if;
end process SLAVE_REG_WRITE_PROC;
-- implement slave model software accessible register(s) read mux
SLAVE_REG_READ_PROC : process( slv_reg_read_sel, slv_reg0, slv_reg1, slv_reg2, slv_reg3 ) is
begin
case slv_reg_read_sel is
when "1000" => slv_ip2bus_data <= slv_reg0;
when "0100" => slv_ip2bus_data <= slv_reg1;
when "0010" => slv_ip2bus_data <= slv_reg2;
when "0001" => slv_ip2bus_data <= slv_reg3;
when others => slv_ip2bus_data <= (others => '0');
end case;
end process SLAVE_REG_READ_PROC;
------------------------------------------
-- Example code to drive IP to Bus signals
------------------------------------------
IP2Bus_Data <= slv_ip2bus_data when slv_read_ack = '1' else
(others => '0');
IP2Bus_WrAck <= slv_write_ack;
IP2Bus_RdAck <= slv_read_ack;
IP2Bus_Error <= '0';
end IMP;
|
bsd-3-clause
|
masson2013/heterogeneous_hthreads
|
src/platforms/xilinx/pr_6smp/design/pcores/plb_sync_manager_v1_00_a/hdl/vhdl/user_logic.vhd
|
10
|
26990
|
------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: user_logic.vhd
-- Version: 1.00.a
-- Description: User logic.
-- Date: Thu May 7 14:29:05 2009 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.srl_fifo_f;
-- DO NOT EDIT ABOVE THIS LINE --------------------
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_SLV_DWIDTH -- Slave interface data bus width
-- C_MST_AWIDTH -- Master interface address bus width
-- C_MST_DWIDTH -- Master interface data bus width
-- C_NUM_REG -- Number of software accessible registers
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Reset -- Bus to IP reset
-- Bus2IP_Addr -- Bus to IP address bus
-- Bus2IP_CS -- Bus to IP chip select
-- Bus2IP_RNW -- Bus to IP read/not write
-- Bus2IP_Data -- Bus to IP data bus
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- IP2Bus_Data -- IP to Bus data bus
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- IP2Bus_Error -- IP to Bus error response
-- IP2Bus_MstRd_Req -- IP to Bus master read request
-- IP2Bus_MstWr_Req -- IP to Bus master write request
-- IP2Bus_Mst_Addr -- IP to Bus master address bus
-- IP2Bus_Mst_BE -- IP to Bus master byte enables
-- IP2Bus_Mst_Lock -- IP to Bus master lock
-- IP2Bus_Mst_Reset -- IP to Bus master reset
-- Bus2IP_Mst_CmdAck -- Bus to IP master command acknowledgement
-- Bus2IP_Mst_Cmplt -- Bus to IP master transfer completion
-- Bus2IP_Mst_Error -- Bus to IP master error response
-- Bus2IP_Mst_Rearbitrate -- Bus to IP master re-arbitrate
-- Bus2IP_Mst_Cmd_Timeout -- Bus to IP master command timeout
-- Bus2IP_MstRd_d -- Bus to IP master read data bus
-- Bus2IP_MstRd_src_rdy_n -- Bus to IP master read source ready
-- IP2Bus_MstWr_d -- IP to Bus master write data bus
-- Bus2IP_MstWr_dst_rdy_n -- Bus to IP master write destination ready
------------------------------------------------------------------------------
entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_SLV_DWIDTH : integer := 32;
C_MST_AWIDTH : integer := 32;
C_MST_DWIDTH : integer := 32;
C_NUM_REG : integer := 5
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Addr : in std_logic_vector(0 to 31);
Bus2IP_CS : in std_logic_vector(0 to 1);
Bus2IP_RNW : in std_logic;
Bus2IP_Data : in std_logic_vector(0 to C_SLV_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_SLV_DWIDTH/8-1);
Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_REG-1);
Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_REG-1);
IP2Bus_Data : out std_logic_vector(0 to C_SLV_DWIDTH-1);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic;
IP2Bus_MstRd_Req : out std_logic;
IP2Bus_MstWr_Req : out std_logic;
IP2Bus_Mst_Addr : out std_logic_vector(0 to C_MST_AWIDTH-1);
IP2Bus_Mst_BE : out std_logic_vector(0 to C_MST_DWIDTH/8-1);
IP2Bus_Mst_Lock : out std_logic;
IP2Bus_Mst_Reset : out std_logic;
Bus2IP_Mst_CmdAck : in std_logic;
Bus2IP_Mst_Cmplt : in std_logic;
Bus2IP_Mst_Error : in std_logic;
Bus2IP_Mst_Rearbitrate : in std_logic;
Bus2IP_Mst_Cmd_Timeout : in std_logic;
Bus2IP_MstRd_d : in std_logic_vector(0 to C_MST_DWIDTH-1);
Bus2IP_MstRd_src_rdy_n : in std_logic;
IP2Bus_MstWr_d : out std_logic_vector(0 to C_MST_DWIDTH-1);
Bus2IP_MstWr_dst_rdy_n : in std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk : signal is "CLK";
attribute SIGIS of Bus2IP_Reset : signal is "RST";
attribute SIGIS of IP2Bus_Mst_Reset: signal is "RST";
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
--USER signal declarations added here, as needed for user logic
------------------------------------------
-- Signals for user logic slave model s/w accessible register example
------------------------------------------
signal slv_reg0 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg_write_sel : std_logic_vector(0 to 0);
signal slv_reg_read_sel : std_logic_vector(0 to 0);
signal slv_ip2bus_data : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;
------------------------------------------
-- Signals for user logic master model example
------------------------------------------
-- signals for master model control/status registers write/read
signal mst_ip2bus_data : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal mst_reg_write_req : std_logic;
signal mst_reg_read_req : std_logic;
signal mst_reg_write_sel : std_logic_vector(0 to 3);
signal mst_reg_read_sel : std_logic_vector(0 to 3);
signal mst_write_ack : std_logic;
signal mst_read_ack : std_logic;
-- signals for master model control/status registers
type BYTE_REG_TYPE is array(0 to 15) of std_logic_vector(0 to 7);
signal mst_reg : BYTE_REG_TYPE;
signal mst_byte_we : std_logic_vector(0 to 15);
signal mst_cntl_rd_req : std_logic;
signal mst_cntl_wr_req : std_logic;
signal mst_cntl_bus_lock : std_logic;
signal mst_cntl_burst : std_logic;
signal mst_ip2bus_addr : std_logic_vector(0 to C_MST_AWIDTH-1);
signal mst_xfer_length : std_logic_vector(0 to 11);
signal mst_ip2bus_be : std_logic_vector(0 to 15);
signal mst_go : std_logic;
-- signals for master model command interface state machine
type CMD_CNTL_SM_TYPE is (CMD_IDLE, CMD_RUN, CMD_WAIT_FOR_DATA, CMD_DONE);
signal mst_cmd_sm_state : CMD_CNTL_SM_TYPE;
signal mst_cmd_sm_set_done : std_logic;
signal mst_cmd_sm_set_error : std_logic;
signal mst_cmd_sm_set_timeout : std_logic;
signal mst_cmd_sm_busy : std_logic;
signal mst_cmd_sm_clr_go : std_logic;
signal mst_cmd_sm_rd_req : std_logic;
signal mst_cmd_sm_wr_req : std_logic;
signal mst_cmd_sm_reset : std_logic;
signal mst_cmd_sm_bus_lock : std_logic;
signal mst_cmd_sm_ip2bus_addr : std_logic_vector(0 to C_MST_AWIDTH-1);
signal mst_cmd_sm_ip2bus_be : std_logic_vector(0 to C_MST_DWIDTH/8-1);
signal mst_fifo_valid_write_xfer : std_logic;
signal mst_fifo_valid_read_xfer : std_logic;
begin
--USER logic implementation added here
------------------------------------------
-- Example code to read/write user logic slave model s/w accessible registers
--
-- Note:
-- The example code presented here is to show you one way of reading/writing
-- software accessible registers implemented in the user logic slave model.
-- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond
-- to one software accessible register by the top level template. For example,
-- if you have four 32 bit software accessible registers in the user logic,
-- you are basically operating on the following memory mapped registers:
--
-- Bus2IP_WrCE/Bus2IP_RdCE Memory Mapped Register
-- "1000" C_BASEADDR + 0x0
-- "0100" C_BASEADDR + 0x4
-- "0010" C_BASEADDR + 0x8
-- "0001" C_BASEADDR + 0xC
--
------------------------------------------
slv_reg_write_sel <= Bus2IP_WrCE(0 to 0);
slv_reg_read_sel <= Bus2IP_RdCE(0 to 0);
slv_write_ack <= Bus2IP_WrCE(0);
slv_read_ack <= Bus2IP_RdCE(0);
-- implement slave model software accessible register(s)
SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Reset = '1' then
slv_reg0 <= (others => '0');
else
case slv_reg_write_sel is
when "1" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg0(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when others => null;
end case;
end if;
end if;
end process SLAVE_REG_WRITE_PROC;
-- implement slave model software accessible register(s) read mux
SLAVE_REG_READ_PROC : process( slv_reg_read_sel, slv_reg0 ) is
begin
case slv_reg_read_sel is
when "1" => slv_ip2bus_data <= slv_reg0;
when others => slv_ip2bus_data <= (others => '0');
end case;
end process SLAVE_REG_READ_PROC;
------------------------------------------
-- Example code to demonstrate user logic master model functionality
--
-- Note:
-- The example code presented here is to show you one way of stimulating
-- the PLBv46 master interface under user control. It is provided for
-- demonstration purposes only and allows the user to exercise the PLBv46
-- master interface during test and evaluation of the template.
-- This user logic master model contains a 16-byte flattened register and
-- the user is required to initialize the value to desire and then write to
-- the model's 'Go' port to initiate the user logic master operation.
--
-- Control Register (C_BASEADDR + OFFSET + 0x0):
-- bit 0 - Rd (Read Request Control)
-- bit 1 - Wr (Write Request Control)
-- bit 2 - BL (Bus Lock Control)
-- bit 3 - Brst (Burst Assertion Control)
-- bit 4-7 - Spare (Spare Control Bits)
-- Status Register (C_BASEADDR + OFFSET + 0x1):
-- bit 0 - Done (Transfer Done Status)
-- bit 1 - Busy (User Logic Master is Busy)
-- bit 2 - Error (User Logic Master request got error response)
-- bit 3 - Tmout (User Logic Master request is timeout)
-- bit 2-7 - Spare (Spare Status Bits)
-- Addrress Register (C_BASEADDR + OFFSET + 0x4):
-- bit 0-31 - Target Address (This 32-bit value is used to populate the
-- IP2Bus_Mst_Addr(0:31) address bus during a Read or Write
-- user logic master operation)
-- Byte Enable Register (C_BASEADDR + OFFSET + 0x8):
-- bit 0-15 - Master BE (This 16-bit value is used to populate the
-- IP2Bus_Mst_BE byte enable bus during a Read or Write user
-- logic master operation for single data beat transfer)
-- Length Register (C_BASEADDR + OFFSET + 0xC):
-- bit 0-3 - Reserved
-- bit 4-15 - Transfer Length (This 12-bit value is used to populate the
-- IP2Bus_Mst_Length(0:11) transfer length bus which specifies
-- the number of bytes (1 to 4096) to transfer during user logic
-- master Read or Write fixed length burst operations)
-- Go Register (C_BASEADDR + OFFSET + 0xF):
-- bit 0-7 - Go Port (Write to this byte address initiates the user
-- logic master transfer, data key value of 0x0A must be used)
--
-- Note: OFFSET may be different depending on your address space configuration,
-- by default it's either 0x0 or 0x100. Refer to IPIF address range array
-- for actual value.
--
-- Here's an example procedure in your software application to initiate a 4-byte
-- write operation (single data beat) of this master model:
-- 1. write 0x40 to the control register
-- 2. write the target address to the address register
-- 3. write valid byte lane value to the be register
-- - note: this value must be aligned with ip2bus address
-- 4. write 0x0004 to the length register
-- 5. write 0x0a to the go register, this will start the master write operation
--
------------------------------------------
mst_reg_write_req <= Bus2IP_WrCE(1) or Bus2IP_WrCE(2) or Bus2IP_WrCE(3) or Bus2IP_WrCE(4);
mst_reg_read_req <= Bus2IP_RdCE(1) or Bus2IP_RdCE(2) or Bus2IP_RdCE(3) or Bus2IP_RdCE(4);
mst_reg_write_sel <= Bus2IP_WrCE(1 to 4);
mst_reg_read_sel <= Bus2IP_RdCE(1 to 4);
mst_write_ack <= mst_reg_write_req;
mst_read_ack <= mst_reg_read_req;
-- rip control bits from master model registers
mst_cntl_rd_req <= mst_reg(0)(0);
mst_cntl_wr_req <= mst_reg(0)(1);
mst_cntl_bus_lock <= mst_reg(0)(2);
mst_cntl_burst <= mst_reg(0)(3);
mst_ip2bus_addr <= mst_reg(4) & mst_reg(5) & mst_reg(6) & mst_reg(7);
mst_ip2bus_be <= mst_reg(8) & mst_reg(9);
mst_xfer_length <= mst_reg(12)(4 to 7) & mst_reg(13);
-- implement byte write enable for each byte slice of the master model registers
MASTER_REG_BYTE_WR_EN : process( Bus2IP_BE, mst_reg_write_req, mst_reg_write_sel ) is
constant BE_WIDTH : integer := C_SLV_DWIDTH/8;
begin
for byte_index in 0 to 15 loop
mst_byte_we(byte_index) <= mst_reg_write_req and
mst_reg_write_sel(byte_index/BE_WIDTH) and
Bus2IP_BE(byte_index-(byte_index/BE_WIDTH)*BE_WIDTH);
end loop;
end process MASTER_REG_BYTE_WR_EN;
-- implement master model registers
MASTER_REG_WRITE_PROC : process( Bus2IP_Clk ) is
constant BE_WIDTH : integer := C_SLV_DWIDTH/8;
begin
if ( Bus2IP_Clk'event and Bus2IP_Clk = '1' ) then
if ( Bus2IP_Reset = '1' ) then
mst_reg(0 to 14) <= (others => "00000000");
else
-- control register (byte 0)
if ( mst_byte_we(0) = '1' ) then
mst_reg(0) <= Bus2IP_Data(0 to 7);
end if;
-- status register (byte 1)
mst_reg(1)(1) <= mst_cmd_sm_busy;
if ( mst_byte_we(1) = '1' ) then
-- allows a clear of the 'Done'/'error'/'timeout'
mst_reg(1)(0) <= Bus2IP_Data((1-(1/BE_WIDTH)*BE_WIDTH)*8);
mst_reg(1)(2) <= Bus2IP_Data((1-(1/BE_WIDTH)*BE_WIDTH)*8+2);
mst_reg(1)(3) <= Bus2IP_Data((1-(1/BE_WIDTH)*BE_WIDTH)*8+3);
else
-- 'Done'/'error'/'timeout' from master control state machine
mst_reg(1)(0) <= mst_cmd_sm_set_done or mst_reg(1)(0);
mst_reg(1)(2) <= mst_cmd_sm_set_error or mst_reg(1)(2);
mst_reg(1)(3) <= mst_cmd_sm_set_timeout or mst_reg(1)(3);
end if;
-- byte 2 and 3 are reserved
-- address register (byte 4 to 7)
-- be register (byte 8 to 9)
-- length register (byte 12 to 13)
-- byte 10, 11 and 14 are reserved
for byte_index in 4 to 14 loop
if ( mst_byte_we(byte_index) = '1' ) then
mst_reg(byte_index) <= Bus2IP_Data(
(byte_index-(byte_index/BE_WIDTH)*BE_WIDTH)*8 to
(byte_index-(byte_index/BE_WIDTH)*BE_WIDTH)*8+7);
end if;
end loop;
end if;
end if;
end process MASTER_REG_WRITE_PROC;
-- implement master model write only 'go' port
MASTER_WRITE_GO_PORT : process( Bus2IP_Clk ) is
constant GO_DATA_KEY : std_logic_vector(0 to 7) := X"0A";
constant GO_BYTE_LANE : integer := 15;
constant BE_WIDTH : integer := C_SLV_DWIDTH/8;
begin
if ( Bus2IP_Clk'event and Bus2IP_Clk = '1' ) then
if ( Bus2IP_Reset = '1' or mst_cmd_sm_clr_go = '1' ) then
mst_go <= '0';
elsif ( mst_cmd_sm_busy = '0' and mst_byte_we(GO_BYTE_LANE) = '1' and
Bus2IP_Data((GO_BYTE_LANE-(GO_BYTE_LANE/BE_WIDTH)*BE_WIDTH)*8 to
(GO_BYTE_LANE-(GO_BYTE_LANE/BE_WIDTH)*BE_WIDTH)*8+7) = GO_DATA_KEY ) then
mst_go <= '1';
else
null;
end if;
end if;
end process MASTER_WRITE_GO_PORT;
-- implement master model register read mux
MASTER_REG_READ_PROC : process( mst_reg_read_sel, mst_reg ) is
constant BE_WIDTH : integer := C_SLV_DWIDTH/8;
begin
case mst_reg_read_sel is
when "1000" =>
for byte_index in 0 to BE_WIDTH-1 loop
mst_ip2bus_data(byte_index*8 to byte_index*8+7) <= mst_reg(byte_index);
end loop;
when "0100" =>
for byte_index in 0 to BE_WIDTH-1 loop
mst_ip2bus_data(byte_index*8 to byte_index*8+7) <= mst_reg(BE_WIDTH+byte_index);
end loop;
when "0010" =>
for byte_index in 0 to BE_WIDTH-1 loop
mst_ip2bus_data(byte_index*8 to byte_index*8+7) <= mst_reg(BE_WIDTH*2+byte_index);
end loop;
when "0001" =>
for byte_index in 0 to BE_WIDTH-1 loop
if ( byte_index = BE_WIDTH-1 ) then
-- go port is not readable
mst_ip2bus_data(byte_index*8 to byte_index*8+7) <= (others => '0');
else
mst_ip2bus_data(byte_index*8 to byte_index*8+7) <= mst_reg(BE_WIDTH*3+byte_index);
end if;
end loop;
when others =>
mst_ip2bus_data <= (others => '0');
end case;
end process MASTER_REG_READ_PROC;
-- user logic master command interface assignments
IP2Bus_MstRd_Req <= mst_cmd_sm_rd_req;
IP2Bus_MstWr_Req <= mst_cmd_sm_wr_req;
IP2Bus_Mst_Addr <= mst_cmd_sm_ip2bus_addr;
IP2Bus_Mst_BE <= mst_cmd_sm_ip2bus_be;
IP2Bus_Mst_Lock <= mst_cmd_sm_bus_lock;
IP2Bus_Mst_Reset <= mst_cmd_sm_reset;
--implement master command interface state machine
MASTER_CMD_SM_PROC : process( Bus2IP_Clk ) is
begin
if ( Bus2IP_Clk'event and Bus2IP_Clk = '1' ) then
if ( Bus2IP_Reset = '1' ) then
-- reset condition
mst_cmd_sm_state <= CMD_IDLE;
mst_cmd_sm_clr_go <= '0';
mst_cmd_sm_rd_req <= '0';
mst_cmd_sm_wr_req <= '0';
mst_cmd_sm_bus_lock <= '0';
mst_cmd_sm_reset <= '0';
mst_cmd_sm_ip2bus_addr <= (others => '0');
mst_cmd_sm_ip2bus_be <= (others => '0');
mst_cmd_sm_set_done <= '0';
mst_cmd_sm_set_error <= '0';
mst_cmd_sm_set_timeout <= '0';
mst_cmd_sm_busy <= '0';
else
-- default condition
mst_cmd_sm_clr_go <= '0';
mst_cmd_sm_rd_req <= '0';
mst_cmd_sm_wr_req <= '0';
mst_cmd_sm_bus_lock <= '0';
mst_cmd_sm_reset <= '0';
mst_cmd_sm_ip2bus_addr <= (others => '0');
mst_cmd_sm_ip2bus_be <= (others => '0');
mst_cmd_sm_set_done <= '0';
mst_cmd_sm_set_error <= '0';
mst_cmd_sm_set_timeout <= '0';
mst_cmd_sm_busy <= '1';
-- state transition
case mst_cmd_sm_state is
when CMD_IDLE =>
if ( mst_go = '1' ) then
mst_cmd_sm_state <= CMD_RUN;
mst_cmd_sm_clr_go <= '1';
else
mst_cmd_sm_state <= CMD_IDLE;
mst_cmd_sm_busy <= '0';
end if;
when CMD_RUN =>
if ( Bus2IP_Mst_CmdAck = '1' and Bus2IP_Mst_Cmplt = '0' ) then
mst_cmd_sm_state <= CMD_WAIT_FOR_DATA;
elsif ( Bus2IP_Mst_Cmplt = '1' ) then
mst_cmd_sm_state <= CMD_DONE;
if ( Bus2IP_Mst_Cmd_Timeout = '1' ) then
-- PLB address phase timeout
mst_cmd_sm_set_error <= '1';
mst_cmd_sm_set_timeout <= '1';
elsif ( Bus2IP_Mst_Error = '1' ) then
-- PLB data transfer error
mst_cmd_sm_set_error <= '1';
end if;
else
mst_cmd_sm_state <= CMD_RUN;
mst_cmd_sm_rd_req <= mst_cntl_rd_req;
mst_cmd_sm_wr_req <= mst_cntl_wr_req;
mst_cmd_sm_ip2bus_addr <= mst_ip2bus_addr;
mst_cmd_sm_ip2bus_be <= mst_ip2bus_be(16-C_MST_DWIDTH/8 to 15);
mst_cmd_sm_bus_lock <= mst_cntl_bus_lock;
end if;
when CMD_WAIT_FOR_DATA =>
if ( Bus2IP_Mst_Cmplt = '1' ) then
mst_cmd_sm_state <= CMD_DONE;
else
mst_cmd_sm_state <= CMD_WAIT_FOR_DATA;
end if;
when CMD_DONE =>
mst_cmd_sm_state <= CMD_IDLE;
mst_cmd_sm_set_done <= '1';
mst_cmd_sm_busy <= '0';
when others =>
mst_cmd_sm_state <= CMD_IDLE;
mst_cmd_sm_busy <= '0';
end case;
end if;
end if;
end process MASTER_CMD_SM_PROC;
-- local srl fifo for data storage
mst_fifo_valid_write_xfer <= not(Bus2IP_MstRd_src_rdy_n);
mst_fifo_valid_read_xfer <= not(Bus2IP_MstWr_dst_rdy_n);
DATA_CAPTURE_FIFO_I : entity proc_common_v3_00_a.srl_fifo_f
generic map
(
C_DWIDTH => C_MST_DWIDTH,
C_DEPTH => 16
)
port map
(
Clk => Bus2IP_Clk,
Reset => Bus2IP_Reset,
FIFO_Write => mst_fifo_valid_write_xfer,
Data_In => Bus2IP_MstRd_d,
FIFO_Read => mst_fifo_valid_read_xfer,
Data_Out => IP2Bus_MstWr_d,
FIFO_Full => open,
FIFO_Empty => open,
Addr => open
);
------------------------------------------
-- Example code to drive IP to Bus signals
------------------------------------------
IP2Bus_Data <= slv_ip2bus_data when slv_read_ack = '1' else
mst_ip2bus_data when mst_read_ack = '1' else
(others => '0');
IP2Bus_WrAck <= slv_write_ack or mst_write_ack;
IP2Bus_RdAck <= slv_read_ack or mst_read_ack;
IP2Bus_Error <= '0';
end IMP;
|
bsd-3-clause
|
masson2013/heterogeneous_hthreads
|
src/platforms/xilinx/ml605_pr_smp1_14_7/design/pcores/plb_sync_manager_v1_00_a/hdl/vhdl/user_logic.vhd
|
10
|
26990
|
------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: user_logic.vhd
-- Version: 1.00.a
-- Description: User logic.
-- Date: Thu May 7 14:29:05 2009 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.srl_fifo_f;
-- DO NOT EDIT ABOVE THIS LINE --------------------
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_SLV_DWIDTH -- Slave interface data bus width
-- C_MST_AWIDTH -- Master interface address bus width
-- C_MST_DWIDTH -- Master interface data bus width
-- C_NUM_REG -- Number of software accessible registers
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Reset -- Bus to IP reset
-- Bus2IP_Addr -- Bus to IP address bus
-- Bus2IP_CS -- Bus to IP chip select
-- Bus2IP_RNW -- Bus to IP read/not write
-- Bus2IP_Data -- Bus to IP data bus
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- IP2Bus_Data -- IP to Bus data bus
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- IP2Bus_Error -- IP to Bus error response
-- IP2Bus_MstRd_Req -- IP to Bus master read request
-- IP2Bus_MstWr_Req -- IP to Bus master write request
-- IP2Bus_Mst_Addr -- IP to Bus master address bus
-- IP2Bus_Mst_BE -- IP to Bus master byte enables
-- IP2Bus_Mst_Lock -- IP to Bus master lock
-- IP2Bus_Mst_Reset -- IP to Bus master reset
-- Bus2IP_Mst_CmdAck -- Bus to IP master command acknowledgement
-- Bus2IP_Mst_Cmplt -- Bus to IP master transfer completion
-- Bus2IP_Mst_Error -- Bus to IP master error response
-- Bus2IP_Mst_Rearbitrate -- Bus to IP master re-arbitrate
-- Bus2IP_Mst_Cmd_Timeout -- Bus to IP master command timeout
-- Bus2IP_MstRd_d -- Bus to IP master read data bus
-- Bus2IP_MstRd_src_rdy_n -- Bus to IP master read source ready
-- IP2Bus_MstWr_d -- IP to Bus master write data bus
-- Bus2IP_MstWr_dst_rdy_n -- Bus to IP master write destination ready
------------------------------------------------------------------------------
entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_SLV_DWIDTH : integer := 32;
C_MST_AWIDTH : integer := 32;
C_MST_DWIDTH : integer := 32;
C_NUM_REG : integer := 5
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Addr : in std_logic_vector(0 to 31);
Bus2IP_CS : in std_logic_vector(0 to 1);
Bus2IP_RNW : in std_logic;
Bus2IP_Data : in std_logic_vector(0 to C_SLV_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_SLV_DWIDTH/8-1);
Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_REG-1);
Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_REG-1);
IP2Bus_Data : out std_logic_vector(0 to C_SLV_DWIDTH-1);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic;
IP2Bus_MstRd_Req : out std_logic;
IP2Bus_MstWr_Req : out std_logic;
IP2Bus_Mst_Addr : out std_logic_vector(0 to C_MST_AWIDTH-1);
IP2Bus_Mst_BE : out std_logic_vector(0 to C_MST_DWIDTH/8-1);
IP2Bus_Mst_Lock : out std_logic;
IP2Bus_Mst_Reset : out std_logic;
Bus2IP_Mst_CmdAck : in std_logic;
Bus2IP_Mst_Cmplt : in std_logic;
Bus2IP_Mst_Error : in std_logic;
Bus2IP_Mst_Rearbitrate : in std_logic;
Bus2IP_Mst_Cmd_Timeout : in std_logic;
Bus2IP_MstRd_d : in std_logic_vector(0 to C_MST_DWIDTH-1);
Bus2IP_MstRd_src_rdy_n : in std_logic;
IP2Bus_MstWr_d : out std_logic_vector(0 to C_MST_DWIDTH-1);
Bus2IP_MstWr_dst_rdy_n : in std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk : signal is "CLK";
attribute SIGIS of Bus2IP_Reset : signal is "RST";
attribute SIGIS of IP2Bus_Mst_Reset: signal is "RST";
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
--USER signal declarations added here, as needed for user logic
------------------------------------------
-- Signals for user logic slave model s/w accessible register example
------------------------------------------
signal slv_reg0 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg_write_sel : std_logic_vector(0 to 0);
signal slv_reg_read_sel : std_logic_vector(0 to 0);
signal slv_ip2bus_data : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;
------------------------------------------
-- Signals for user logic master model example
------------------------------------------
-- signals for master model control/status registers write/read
signal mst_ip2bus_data : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal mst_reg_write_req : std_logic;
signal mst_reg_read_req : std_logic;
signal mst_reg_write_sel : std_logic_vector(0 to 3);
signal mst_reg_read_sel : std_logic_vector(0 to 3);
signal mst_write_ack : std_logic;
signal mst_read_ack : std_logic;
-- signals for master model control/status registers
type BYTE_REG_TYPE is array(0 to 15) of std_logic_vector(0 to 7);
signal mst_reg : BYTE_REG_TYPE;
signal mst_byte_we : std_logic_vector(0 to 15);
signal mst_cntl_rd_req : std_logic;
signal mst_cntl_wr_req : std_logic;
signal mst_cntl_bus_lock : std_logic;
signal mst_cntl_burst : std_logic;
signal mst_ip2bus_addr : std_logic_vector(0 to C_MST_AWIDTH-1);
signal mst_xfer_length : std_logic_vector(0 to 11);
signal mst_ip2bus_be : std_logic_vector(0 to 15);
signal mst_go : std_logic;
-- signals for master model command interface state machine
type CMD_CNTL_SM_TYPE is (CMD_IDLE, CMD_RUN, CMD_WAIT_FOR_DATA, CMD_DONE);
signal mst_cmd_sm_state : CMD_CNTL_SM_TYPE;
signal mst_cmd_sm_set_done : std_logic;
signal mst_cmd_sm_set_error : std_logic;
signal mst_cmd_sm_set_timeout : std_logic;
signal mst_cmd_sm_busy : std_logic;
signal mst_cmd_sm_clr_go : std_logic;
signal mst_cmd_sm_rd_req : std_logic;
signal mst_cmd_sm_wr_req : std_logic;
signal mst_cmd_sm_reset : std_logic;
signal mst_cmd_sm_bus_lock : std_logic;
signal mst_cmd_sm_ip2bus_addr : std_logic_vector(0 to C_MST_AWIDTH-1);
signal mst_cmd_sm_ip2bus_be : std_logic_vector(0 to C_MST_DWIDTH/8-1);
signal mst_fifo_valid_write_xfer : std_logic;
signal mst_fifo_valid_read_xfer : std_logic;
begin
--USER logic implementation added here
------------------------------------------
-- Example code to read/write user logic slave model s/w accessible registers
--
-- Note:
-- The example code presented here is to show you one way of reading/writing
-- software accessible registers implemented in the user logic slave model.
-- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond
-- to one software accessible register by the top level template. For example,
-- if you have four 32 bit software accessible registers in the user logic,
-- you are basically operating on the following memory mapped registers:
--
-- Bus2IP_WrCE/Bus2IP_RdCE Memory Mapped Register
-- "1000" C_BASEADDR + 0x0
-- "0100" C_BASEADDR + 0x4
-- "0010" C_BASEADDR + 0x8
-- "0001" C_BASEADDR + 0xC
--
------------------------------------------
slv_reg_write_sel <= Bus2IP_WrCE(0 to 0);
slv_reg_read_sel <= Bus2IP_RdCE(0 to 0);
slv_write_ack <= Bus2IP_WrCE(0);
slv_read_ack <= Bus2IP_RdCE(0);
-- implement slave model software accessible register(s)
SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Reset = '1' then
slv_reg0 <= (others => '0');
else
case slv_reg_write_sel is
when "1" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg0(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when others => null;
end case;
end if;
end if;
end process SLAVE_REG_WRITE_PROC;
-- implement slave model software accessible register(s) read mux
SLAVE_REG_READ_PROC : process( slv_reg_read_sel, slv_reg0 ) is
begin
case slv_reg_read_sel is
when "1" => slv_ip2bus_data <= slv_reg0;
when others => slv_ip2bus_data <= (others => '0');
end case;
end process SLAVE_REG_READ_PROC;
------------------------------------------
-- Example code to demonstrate user logic master model functionality
--
-- Note:
-- The example code presented here is to show you one way of stimulating
-- the PLBv46 master interface under user control. It is provided for
-- demonstration purposes only and allows the user to exercise the PLBv46
-- master interface during test and evaluation of the template.
-- This user logic master model contains a 16-byte flattened register and
-- the user is required to initialize the value to desire and then write to
-- the model's 'Go' port to initiate the user logic master operation.
--
-- Control Register (C_BASEADDR + OFFSET + 0x0):
-- bit 0 - Rd (Read Request Control)
-- bit 1 - Wr (Write Request Control)
-- bit 2 - BL (Bus Lock Control)
-- bit 3 - Brst (Burst Assertion Control)
-- bit 4-7 - Spare (Spare Control Bits)
-- Status Register (C_BASEADDR + OFFSET + 0x1):
-- bit 0 - Done (Transfer Done Status)
-- bit 1 - Busy (User Logic Master is Busy)
-- bit 2 - Error (User Logic Master request got error response)
-- bit 3 - Tmout (User Logic Master request is timeout)
-- bit 2-7 - Spare (Spare Status Bits)
-- Addrress Register (C_BASEADDR + OFFSET + 0x4):
-- bit 0-31 - Target Address (This 32-bit value is used to populate the
-- IP2Bus_Mst_Addr(0:31) address bus during a Read or Write
-- user logic master operation)
-- Byte Enable Register (C_BASEADDR + OFFSET + 0x8):
-- bit 0-15 - Master BE (This 16-bit value is used to populate the
-- IP2Bus_Mst_BE byte enable bus during a Read or Write user
-- logic master operation for single data beat transfer)
-- Length Register (C_BASEADDR + OFFSET + 0xC):
-- bit 0-3 - Reserved
-- bit 4-15 - Transfer Length (This 12-bit value is used to populate the
-- IP2Bus_Mst_Length(0:11) transfer length bus which specifies
-- the number of bytes (1 to 4096) to transfer during user logic
-- master Read or Write fixed length burst operations)
-- Go Register (C_BASEADDR + OFFSET + 0xF):
-- bit 0-7 - Go Port (Write to this byte address initiates the user
-- logic master transfer, data key value of 0x0A must be used)
--
-- Note: OFFSET may be different depending on your address space configuration,
-- by default it's either 0x0 or 0x100. Refer to IPIF address range array
-- for actual value.
--
-- Here's an example procedure in your software application to initiate a 4-byte
-- write operation (single data beat) of this master model:
-- 1. write 0x40 to the control register
-- 2. write the target address to the address register
-- 3. write valid byte lane value to the be register
-- - note: this value must be aligned with ip2bus address
-- 4. write 0x0004 to the length register
-- 5. write 0x0a to the go register, this will start the master write operation
--
------------------------------------------
mst_reg_write_req <= Bus2IP_WrCE(1) or Bus2IP_WrCE(2) or Bus2IP_WrCE(3) or Bus2IP_WrCE(4);
mst_reg_read_req <= Bus2IP_RdCE(1) or Bus2IP_RdCE(2) or Bus2IP_RdCE(3) or Bus2IP_RdCE(4);
mst_reg_write_sel <= Bus2IP_WrCE(1 to 4);
mst_reg_read_sel <= Bus2IP_RdCE(1 to 4);
mst_write_ack <= mst_reg_write_req;
mst_read_ack <= mst_reg_read_req;
-- rip control bits from master model registers
mst_cntl_rd_req <= mst_reg(0)(0);
mst_cntl_wr_req <= mst_reg(0)(1);
mst_cntl_bus_lock <= mst_reg(0)(2);
mst_cntl_burst <= mst_reg(0)(3);
mst_ip2bus_addr <= mst_reg(4) & mst_reg(5) & mst_reg(6) & mst_reg(7);
mst_ip2bus_be <= mst_reg(8) & mst_reg(9);
mst_xfer_length <= mst_reg(12)(4 to 7) & mst_reg(13);
-- implement byte write enable for each byte slice of the master model registers
MASTER_REG_BYTE_WR_EN : process( Bus2IP_BE, mst_reg_write_req, mst_reg_write_sel ) is
constant BE_WIDTH : integer := C_SLV_DWIDTH/8;
begin
for byte_index in 0 to 15 loop
mst_byte_we(byte_index) <= mst_reg_write_req and
mst_reg_write_sel(byte_index/BE_WIDTH) and
Bus2IP_BE(byte_index-(byte_index/BE_WIDTH)*BE_WIDTH);
end loop;
end process MASTER_REG_BYTE_WR_EN;
-- implement master model registers
MASTER_REG_WRITE_PROC : process( Bus2IP_Clk ) is
constant BE_WIDTH : integer := C_SLV_DWIDTH/8;
begin
if ( Bus2IP_Clk'event and Bus2IP_Clk = '1' ) then
if ( Bus2IP_Reset = '1' ) then
mst_reg(0 to 14) <= (others => "00000000");
else
-- control register (byte 0)
if ( mst_byte_we(0) = '1' ) then
mst_reg(0) <= Bus2IP_Data(0 to 7);
end if;
-- status register (byte 1)
mst_reg(1)(1) <= mst_cmd_sm_busy;
if ( mst_byte_we(1) = '1' ) then
-- allows a clear of the 'Done'/'error'/'timeout'
mst_reg(1)(0) <= Bus2IP_Data((1-(1/BE_WIDTH)*BE_WIDTH)*8);
mst_reg(1)(2) <= Bus2IP_Data((1-(1/BE_WIDTH)*BE_WIDTH)*8+2);
mst_reg(1)(3) <= Bus2IP_Data((1-(1/BE_WIDTH)*BE_WIDTH)*8+3);
else
-- 'Done'/'error'/'timeout' from master control state machine
mst_reg(1)(0) <= mst_cmd_sm_set_done or mst_reg(1)(0);
mst_reg(1)(2) <= mst_cmd_sm_set_error or mst_reg(1)(2);
mst_reg(1)(3) <= mst_cmd_sm_set_timeout or mst_reg(1)(3);
end if;
-- byte 2 and 3 are reserved
-- address register (byte 4 to 7)
-- be register (byte 8 to 9)
-- length register (byte 12 to 13)
-- byte 10, 11 and 14 are reserved
for byte_index in 4 to 14 loop
if ( mst_byte_we(byte_index) = '1' ) then
mst_reg(byte_index) <= Bus2IP_Data(
(byte_index-(byte_index/BE_WIDTH)*BE_WIDTH)*8 to
(byte_index-(byte_index/BE_WIDTH)*BE_WIDTH)*8+7);
end if;
end loop;
end if;
end if;
end process MASTER_REG_WRITE_PROC;
-- implement master model write only 'go' port
MASTER_WRITE_GO_PORT : process( Bus2IP_Clk ) is
constant GO_DATA_KEY : std_logic_vector(0 to 7) := X"0A";
constant GO_BYTE_LANE : integer := 15;
constant BE_WIDTH : integer := C_SLV_DWIDTH/8;
begin
if ( Bus2IP_Clk'event and Bus2IP_Clk = '1' ) then
if ( Bus2IP_Reset = '1' or mst_cmd_sm_clr_go = '1' ) then
mst_go <= '0';
elsif ( mst_cmd_sm_busy = '0' and mst_byte_we(GO_BYTE_LANE) = '1' and
Bus2IP_Data((GO_BYTE_LANE-(GO_BYTE_LANE/BE_WIDTH)*BE_WIDTH)*8 to
(GO_BYTE_LANE-(GO_BYTE_LANE/BE_WIDTH)*BE_WIDTH)*8+7) = GO_DATA_KEY ) then
mst_go <= '1';
else
null;
end if;
end if;
end process MASTER_WRITE_GO_PORT;
-- implement master model register read mux
MASTER_REG_READ_PROC : process( mst_reg_read_sel, mst_reg ) is
constant BE_WIDTH : integer := C_SLV_DWIDTH/8;
begin
case mst_reg_read_sel is
when "1000" =>
for byte_index in 0 to BE_WIDTH-1 loop
mst_ip2bus_data(byte_index*8 to byte_index*8+7) <= mst_reg(byte_index);
end loop;
when "0100" =>
for byte_index in 0 to BE_WIDTH-1 loop
mst_ip2bus_data(byte_index*8 to byte_index*8+7) <= mst_reg(BE_WIDTH+byte_index);
end loop;
when "0010" =>
for byte_index in 0 to BE_WIDTH-1 loop
mst_ip2bus_data(byte_index*8 to byte_index*8+7) <= mst_reg(BE_WIDTH*2+byte_index);
end loop;
when "0001" =>
for byte_index in 0 to BE_WIDTH-1 loop
if ( byte_index = BE_WIDTH-1 ) then
-- go port is not readable
mst_ip2bus_data(byte_index*8 to byte_index*8+7) <= (others => '0');
else
mst_ip2bus_data(byte_index*8 to byte_index*8+7) <= mst_reg(BE_WIDTH*3+byte_index);
end if;
end loop;
when others =>
mst_ip2bus_data <= (others => '0');
end case;
end process MASTER_REG_READ_PROC;
-- user logic master command interface assignments
IP2Bus_MstRd_Req <= mst_cmd_sm_rd_req;
IP2Bus_MstWr_Req <= mst_cmd_sm_wr_req;
IP2Bus_Mst_Addr <= mst_cmd_sm_ip2bus_addr;
IP2Bus_Mst_BE <= mst_cmd_sm_ip2bus_be;
IP2Bus_Mst_Lock <= mst_cmd_sm_bus_lock;
IP2Bus_Mst_Reset <= mst_cmd_sm_reset;
--implement master command interface state machine
MASTER_CMD_SM_PROC : process( Bus2IP_Clk ) is
begin
if ( Bus2IP_Clk'event and Bus2IP_Clk = '1' ) then
if ( Bus2IP_Reset = '1' ) then
-- reset condition
mst_cmd_sm_state <= CMD_IDLE;
mst_cmd_sm_clr_go <= '0';
mst_cmd_sm_rd_req <= '0';
mst_cmd_sm_wr_req <= '0';
mst_cmd_sm_bus_lock <= '0';
mst_cmd_sm_reset <= '0';
mst_cmd_sm_ip2bus_addr <= (others => '0');
mst_cmd_sm_ip2bus_be <= (others => '0');
mst_cmd_sm_set_done <= '0';
mst_cmd_sm_set_error <= '0';
mst_cmd_sm_set_timeout <= '0';
mst_cmd_sm_busy <= '0';
else
-- default condition
mst_cmd_sm_clr_go <= '0';
mst_cmd_sm_rd_req <= '0';
mst_cmd_sm_wr_req <= '0';
mst_cmd_sm_bus_lock <= '0';
mst_cmd_sm_reset <= '0';
mst_cmd_sm_ip2bus_addr <= (others => '0');
mst_cmd_sm_ip2bus_be <= (others => '0');
mst_cmd_sm_set_done <= '0';
mst_cmd_sm_set_error <= '0';
mst_cmd_sm_set_timeout <= '0';
mst_cmd_sm_busy <= '1';
-- state transition
case mst_cmd_sm_state is
when CMD_IDLE =>
if ( mst_go = '1' ) then
mst_cmd_sm_state <= CMD_RUN;
mst_cmd_sm_clr_go <= '1';
else
mst_cmd_sm_state <= CMD_IDLE;
mst_cmd_sm_busy <= '0';
end if;
when CMD_RUN =>
if ( Bus2IP_Mst_CmdAck = '1' and Bus2IP_Mst_Cmplt = '0' ) then
mst_cmd_sm_state <= CMD_WAIT_FOR_DATA;
elsif ( Bus2IP_Mst_Cmplt = '1' ) then
mst_cmd_sm_state <= CMD_DONE;
if ( Bus2IP_Mst_Cmd_Timeout = '1' ) then
-- PLB address phase timeout
mst_cmd_sm_set_error <= '1';
mst_cmd_sm_set_timeout <= '1';
elsif ( Bus2IP_Mst_Error = '1' ) then
-- PLB data transfer error
mst_cmd_sm_set_error <= '1';
end if;
else
mst_cmd_sm_state <= CMD_RUN;
mst_cmd_sm_rd_req <= mst_cntl_rd_req;
mst_cmd_sm_wr_req <= mst_cntl_wr_req;
mst_cmd_sm_ip2bus_addr <= mst_ip2bus_addr;
mst_cmd_sm_ip2bus_be <= mst_ip2bus_be(16-C_MST_DWIDTH/8 to 15);
mst_cmd_sm_bus_lock <= mst_cntl_bus_lock;
end if;
when CMD_WAIT_FOR_DATA =>
if ( Bus2IP_Mst_Cmplt = '1' ) then
mst_cmd_sm_state <= CMD_DONE;
else
mst_cmd_sm_state <= CMD_WAIT_FOR_DATA;
end if;
when CMD_DONE =>
mst_cmd_sm_state <= CMD_IDLE;
mst_cmd_sm_set_done <= '1';
mst_cmd_sm_busy <= '0';
when others =>
mst_cmd_sm_state <= CMD_IDLE;
mst_cmd_sm_busy <= '0';
end case;
end if;
end if;
end process MASTER_CMD_SM_PROC;
-- local srl fifo for data storage
mst_fifo_valid_write_xfer <= not(Bus2IP_MstRd_src_rdy_n);
mst_fifo_valid_read_xfer <= not(Bus2IP_MstWr_dst_rdy_n);
DATA_CAPTURE_FIFO_I : entity proc_common_v3_00_a.srl_fifo_f
generic map
(
C_DWIDTH => C_MST_DWIDTH,
C_DEPTH => 16
)
port map
(
Clk => Bus2IP_Clk,
Reset => Bus2IP_Reset,
FIFO_Write => mst_fifo_valid_write_xfer,
Data_In => Bus2IP_MstRd_d,
FIFO_Read => mst_fifo_valid_read_xfer,
Data_Out => IP2Bus_MstWr_d,
FIFO_Full => open,
FIFO_Empty => open,
Addr => open
);
------------------------------------------
-- Example code to drive IP to Bus signals
------------------------------------------
IP2Bus_Data <= slv_ip2bus_data when slv_read_ack = '1' else
mst_ip2bus_data when mst_read_ack = '1' else
(others => '0');
IP2Bus_WrAck <= slv_write_ack or mst_write_ack;
IP2Bus_RdAck <= slv_read_ack or mst_read_ack;
IP2Bus_Error <= '0';
end IMP;
|
bsd-3-clause
|
masson2013/heterogeneous_hthreads
|
src/platforms/xilinx/smp3_opbhwti/design/pcores/opb_plbv46_bridge_v1_01_a/hdl/vhdl/opb_plbv46_bridge.vhd
|
3
|
35705
|
-------------------------------------------------------------------------------
-- $Id: opb_plbv46_bridge.vhd,v 1.1.2.1 2008/12/17 19:04:49 mlovejoy Exp $
-------------------------------------------------------------------------------
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2006, 2008 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
--
-------------------------------------------------------------------------------
-- Filename: opb_plbv46_bridge.vhd
--
-- Description: This bridge accepts OPB master transactions directed at any
-- one of up-to four address ranges and bridges them to the
-- PLBV46 bus. Write transactions are accepted immediately and
-- posted to an internal write buffer. The write data is
-- transported to the PLBV46 bus as soon as it is ready. Read
-- requests are satisfied through a prefetch mechanism. Once
-- the read prefetch has completed on the PLBV46 bus and data
-- from the read has been buffered internal to the bridge an
-- OPB request that matches the address of the original
-- prefetch can claim the buffer contents.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
--
--
-------------------------------------------------------------------------------
-- Author: TRD
-- Revision: $Revision: 1.1.2.1 $
-- Date: $11/06/2006$
--
-- History:
-- TRD 11/06/2006 Initial V46 Version
-- MLL 09/02/2008 Rev`d to proc_common v3, added coverage/off/on
-- statements, new v1.01.a version and CHANGELOG
-- removed
-- MLL 12/17/2008 Legal header updated
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
LIBRARY proc_common_v3_00_a;
USE proc_common_v3_00_a.proc_common_pkg.ALL; -- need log2()
USE proc_common_v3_00_a.family.ALL; -- need C_FAMILY definitions
LIBRARY opb_plbv46_bridge_v1_01_a;
LIBRARY plbv46_master_burst_v1_01_a;
-------------------------------------------------------------------------------
ENTITY opb_plbv46_bridge IS
GENERIC (
-- OPB Address range definition
C_NUM_ADDR_RNG : integer RANGE 1 TO 4 := 1; -- Number of Address Ranges
C_RNG0_BASEADDR : std_logic_vector(0 TO 31) := X"FFFFFFFF"; -- Address range definition base address
C_RNG0_HIGHADDR : std_logic_vector(0 TO 31) := X"00000000"; -- Address range definition high address
C_RNG1_BASEADDR : std_logic_vector(0 TO 31) := X"FFFFFFFF"; -- Address range definition base address
C_RNG1_HIGHADDR : std_logic_vector(0 TO 31) := X"00000000"; -- Address range definition high address
C_RNG2_BASEADDR : std_logic_vector(0 TO 31) := X"FFFFFFFF"; -- Address range definition base address
C_RNG2_HIGHADDR : std_logic_vector(0 TO 31) := X"00000000"; -- Address range definition high address
C_RNG3_BASEADDR : std_logic_vector(0 TO 31) := X"FFFFFFFF"; -- Address range definition base address
C_RNG3_HIGHADDR : std_logic_vector(0 TO 31) := X"00000000"; -- Address range definition high address
-- BRIDGE CONFIGURATION
C_BUS_CLOCK_PERIOD_RATIO : integer RANGE 1 TO 2 := 1;
C_PREFETCH_TIMEOUT : integer RANGE 1 TO 32 := 10; -- prefetch timeout counter size (bits)
-- PLB I/O Specification
C_MPLB_AWIDTH : integer RANGE 32 TO 64 := 32; -- Used Address bits out of the available 64 bits of PLBV46 addressing
C_MPLB_DWIDTH : integer RANGE 32 TO 128 := 32; --Width of the PLB Data Bus to which the Master is attached
C_MPLB_NATIVE_DWIDTH : integer RANGE 32 TO 128 := 32; --Specifies the internal native data width of the Master
C_FAMILY : string := "virtex4" -- Xilinx FPGA Family Type spartan3, virtex4,virtex5
);
PORT (
-------------------------------------------------------------------------
-- PLBV46 Bus Master Interface
-------------------------------------------------------------------------
-- System Ports
MPLB_Clk : IN std_logic;
MPLB_Rst : IN std_logic;
MD_Error : OUT std_logic;
-- Master Request/Qualifiers to PLB V4.6 (outputs)
M_request : OUT std_logic;
M_priority : OUT std_logic_vector(0 TO 1);
M_busLock : OUT std_logic;
M_RNW : OUT std_logic;
M_BE : OUT std_logic_vector(0 TO (C_MPLB_DWIDTH/8) - 1);
M_MSize : OUT std_logic_vector(0 TO 1);
M_size : OUT std_logic_vector(0 TO 3);
M_type : OUT std_logic_vector(0 TO 2);
M_ABus : OUT std_logic_vector(0 TO 31);
M_wrBurst : OUT std_logic;
M_rdBurst : OUT std_logic;
M_wrDBus : OUT std_logic_vector(0 TO C_MPLB_DWIDTH-1);
-- PLB Reply to Master (inputs)
PLB_MAddrAck : IN std_logic;
PLB_MSSize : IN std_logic_vector(0 TO 1);
PLB_MRearbitrate : IN std_logic;
PLB_MTimeout : IN std_logic;
PLB_MRdErr : IN std_logic;
PLB_MWrErr : IN std_logic;
PLB_MRdDBus : IN std_logic_vector(0 TO C_MPLB_DWIDTH-1);
PLB_MRdDAck : IN std_logic;
PLB_MRdBTerm : IN std_logic;
PLB_MWrDAck : IN std_logic;
PLB_MWrBTerm : IN std_logic;
-- Included PLB ports but unused in the design
M_TAttribute : OUT std_logic_vector(0 TO 15);
M_lockErr : OUT std_logic;
M_abort : OUT std_logic;
M_UABus : OUT std_logic_vector(0 TO 31);
PLB_MBusy : IN std_logic;
PLB_MIRQ : IN std_logic;
PLB_MRdWdAddr : IN std_logic_vector(0 TO 3);
--------------------------------------------------------------------------
-- OPB Bus Slave Interface
--------------------------------------------------------------------------
-- System Interface
SOPB_rst : IN std_logic; -- opb reset
SOPB_clk : IN std_logic; -- opb clock
-- Slave ports
OPB_Select : IN std_logic; -- OPB select
OPB_RNW : IN std_logic; -- OPB Read not Write
OPB_BE : IN std_logic_vector(0 TO (32/8)-1); -- OPB transaction byte enables
OPB_seqAddr : IN std_logic; -- OPB sequential address
OPB_DBus : IN std_logic_vector(0 TO 32-1); -- OPB master data bus
OPB_ABus : IN std_logic_vector(0 TO 32-1); -- OPB Slave address bus
Sl_xferAck : OUT std_logic; -- OPB Slave transfer acknowledgement
Sl_errAck : OUT std_logic; -- OPB Slave transaction error acknowledgement
Sl_retry : OUT std_logic; -- OPB Slave transaction retry
Sl_ToutSup : OUT std_logic; -- OPB Slave timeout suppress
Sl_DBus : OUT std_logic_vector(0 TO 32-1) -- OPB Slave data BUS
);
-- Platform Specification Attributes
ATTRIBUTE IMP_NETLIST : string;
ATTRIBUTE IMP_NETLIST OF opb_plbv46_bridge : ENTITY IS "TRUE";
ATTRIBUTE IPTYPE : string;
ATTRIBUTE IPTYPE OF opb_plbv46_bridge : ENTITY IS "BRIDGE";
ATTRIBUTE STYLE : string;
ATTRIBUTE STYLE OF opb_plbv46_bridge : ENTITY IS "HDL";
ATTRIBUTE HDL : string;
ATTRIBUTE HDL OF opb_plbv46_bridge : ENTITY IS "VHDL";
-- ATTRIBUTE BUSIF : string;
-- ATTRIBUTE BUSIF OF C_RNG0_BASEADDR : CONSTANT IS "SOPB";
-- ATTRIBUTE BUSIF OF C_RNG0_HIGHADDR : CONSTANT IS "SOPB";
-- ATTRIBUTE BUSIF OF C_RNG1_BASEADDR : CONSTANT IS "SOPB";
-- ATTRIBUTE BUSIF OF C_RNG1_HIGHADDR : CONSTANT IS "SOPB";
-- ATTRIBUTE BUSIF OF C_RNG2_BASEADDR : CONSTANT IS "SOPB";
-- ATTRIBUTE BUSIF OF C_RNG2_HIGHADDR : CONSTANT IS "SOPB";
-- ATTRIBUTE BUSIF OF C_RNG3_BASEADDR : CONSTANT IS "SOPB";
-- ATTRIBUTE BUSIF OF C_RNG3_HIGHADDR : CONSTANT IS "SOPB";
ATTRIBUTE SIGIS : string;
ATTRIBUTE SIGIS OF SOPB_rst : SIGNAL IS "RST";
ATTRIBUTE SIGIS OF SOPB_clk : SIGNAL IS "CLK";
ATTRIBUTE SIGIS OF MPLB_rst : SIGNAL IS "RST";
ATTRIBUTE SIGIS OF MPLB_clk : SIGNAL IS "CLK";
END ENTITY opb_plbv46_bridge;
ARCHITECTURE syn OF opb_plbv46_bridge IS
CONSTANT C_MPLB_SMALLEST_SLAVE : integer RANGE 32 TO 128 := 32;
CONSTANT C_INHIBIT_CC_BLE_INCLUSION : integer RANGE 0 TO 1 := 0;
-- IP Master Request/Qualifiers
SIGNAL IP2Bus_MstRd_Req : std_logic; -- [In]
SIGNAL IP2Bus_MstWr_Req : std_logic; -- [In]
SIGNAL IP2Bus_Mst_Addr : std_logic_vector(0 TO
C_MPLB_AWIDTH-1); -- [in]
SIGNAL IP2Bus_Mst_Length : std_logic_vector(0 TO 11); -- [in]
SIGNAL IP2Bus_Mst_BE : std_logic_vector(0 TO
(C_MPLB_NATIVE_DWIDTH/8) -1); -- [in]
SIGNAL IP2Bus_Mst_Type : std_logic; -- [in]
SIGNAL IP2Bus_Mst_Lock : std_logic; -- [In]
SIGNAL IP2Bus_Mst_Reset : std_logic; -- [In]
-- IP Master Primary Read Request Status Reply
SIGNAL Bus2IP_Mst_CmdAck : std_logic; -- [Out]
SIGNAL Bus2IP_Mst_Cmplt : std_logic; -- [Out]
SIGNAL Bus2IP_Mst_Error : std_logic; -- [Out]
SIGNAL Bus2IP_Mst_Rearbitrate : std_logic; -- [Out]
SIGNAL Bus2IP_Mst_Cmd_Timeout : std_logic; -- [out]
-- IP Master Primary Read LocalLink Interface
SIGNAL Bus2IP_MstRd_d : std_logic_vector(0 TO
C_MPLB_NATIVE_DWIDTH-1); -- [out]
SIGNAL Bus2IP_MstRd_rem : std_logic_vector(0 TO
(C_MPLB_NATIVE_DWIDTH/8)-1); -- [out]
SIGNAL Bus2IP_MstRd_sof_n : std_logic; -- [Out]
SIGNAL Bus2IP_MstRd_eof_n : std_logic; -- [Out]
SIGNAL Bus2IP_MstRd_src_rdy_n : std_logic; -- [Out]
SIGNAL Bus2IP_MstRd_src_dsc_n : std_logic; -- [Out]
SIGNAL IP2Bus_MstRd_dst_rdy_n : std_logic; -- [In]
SIGNAL IP2Bus_MstRd_dst_dsc_n : std_logic; -- [In]
-- IP Master Primary Write LocalLink Interface
SIGNAL IP2Bus_MstWr_d : std_logic_vector(0 TO
C_MPLB_NATIVE_DWIDTH-1); -- [In]
SIGNAL IP2Bus_MstWr_rem : std_logic_vector(0 TO
(C_MPLB_NATIVE_DWIDTH/8)-1) := (OTHERS => '1'); -- [In]
SIGNAL IP2Bus_MstWr_sof_n : std_logic; -- [In]
SIGNAL IP2Bus_MstWr_eof_n : std_logic; -- [In]
SIGNAL IP2Bus_MstWr_src_rdy_n : std_logic; -- [In]
SIGNAL IP2Bus_MstWr_src_dsc_n : std_logic; -- [In]
SIGNAL Bus2IP_MstWr_dst_rdy_n : std_logic; -- [Out]
SIGNAL Bus2IP_MstWr_dst_dsc_n : std_logic; -- [Out]
-- OPB slave to Bridge Interface
SIGNAL brdg_block : std_logic; -- [IN] bridge block
SIGNAL brdg_prefetch_cmplt : std_logic; -- [IN] bridge prefetch complete
SIGNAL brdg_prefetch_status : std_logic; -- [IN] bridge prefetch status
SIGNAL brdg_prefetch_addr : std_logic_vector(0 TO 31); -- [IN] bridge prefetch address
SIGNAL opbs_prefetch_req : std_logic; -- [OUT] opb slave prefetch request
SIGNAL opbs_type : std_logic; -- [OUT] opb slave transaction request type
SIGNAL opbs_prefetch_clr : std_logic; -- [OUT] opb slave prefetch clear
SIGNAL opbs_postedwr_clr : std_logic; -- [OUT] opb slave posted write clear
SIGNAL opbs_trans_addr : std_logic_vector(0 TO 31); -- [OUT] opb slave transaction address
SIGNAL opbs_length : std_logic_vector(0 TO 11); -- [OUT] opb slave transaction length
SIGNAL opbs_postedwrt_req : std_logic; -- [OUT] opb slave posted write request
SIGNAL opbs_be : std_logic_vector(0 TO 3); -- [OUT] opb slave byte enable
-- Local Link Read Buffer
SIGNAL bfs_data : std_logic_vector(0 TO 31); -- [IN] Read data output to user logic
SIGNAL bfs_sof_n : std_logic; -- [IN] Active low signal indicating the starting data beat of a read local link transfer (unused by slave)
SIGNAL bfs_eof_n : std_logic; -- [IN] Active low signal indicating the ending data beat of a Read local link transfer. (Unused by slave)
SIGNAL bfs_src_rdy_n : std_logic; -- [IN] Asserts active low to indicate the presence of valid data on signal bfs_data.
SIGNAL bfs_src_dsc_n : std_logic; -- [IN] Active low signal indicating that the read local link source (master) needs to discontinue the transfer. (Unused. Drive high)
SIGNAL bfs_dst_rdy_n : std_logic; -- [OUT] Destination (ie the slave) asserts active low to signal it is ready to take valid data on bfs_data.
SIGNAL bfs_dst_dsc_n : std_logic; -- [OUT] Active low signal that the read local link destination needs to discontinue the transfer.
SIGNAL brdg_rd_bf_rst : std_logic; -- [IN]
-- Local Link Write Buffer
SIGNAL bfd_data : std_logic_vector(0 TO 31); -- [OUT]
SIGNAL bfd_sof_n : std_logic; -- [OUT]
SIGNAL bfd_eof_n : std_logic; -- [OUT]
SIGNAL bfd_src_rdy_n : std_logic; -- [OUT]
SIGNAL bfd_src_dsc_n : std_logic; -- [OUT]
SIGNAL bfd_dst_rdy_n : std_logic; -- [IN]
SIGNAL bfd_dst_dsc_n : std_logic; -- [IN]
SIGNAL brdg_wr_bf_rst : std_logic; -- [IN]
BEGIN
x_plbv46_master_burst : ENTITY plbv46_master_burst_v1_01_a.plbv46_master_burst
GENERIC MAP (
-- PLB Parameters
C_MPLB_AWIDTH => C_MPLB_AWIDTH, -- [INTEGER range 32 to 36]
-- Number of PLBV46 Address Bus bits actually used.
C_MPLB_DWIDTH => C_MPLB_DWIDTH, -- [INTEGER range 32 to 128]
-- Width of the PLBV46 Data Bus Attachment (in bits)
C_MPLB_NATIVE_DWIDTH => C_MPLB_NATIVE_DWIDTH, -- [INTEGER range 32 to 32]
-- Set this equal to largest data bus width needed by IPIF
-- and IP elements.
C_MPLB_SMALLEST_SLAVE => C_MPLB_SMALLEST_SLAVE,
-- Indicates the Native Data Width of the smallest slave
-- on the PLB connected to this Master. If this parameter's
-- value is less than the native Data width of the Master,
-- then the Conversion Cycle and Burst Length Expansion
-- Adapter will be included in the Master's implementation.
C_INHIBIT_CC_BLE_INCLUSION => C_INHIBIT_CC_BLE_INCLUSION,
-- This parameter will inhibit the automatic inclusion
-- of the Conversion Cycle and Burst length Expansion
-- Adapter. This override is useful if the connected PLB has
-- narrow Slaves attached to it but this Master will not access
-- those narrow Slaves.
-- FPGA Family Parameter
C_FAMILY => C_FAMILY) -- [String]
PORT MAP (
-- System Ports
MPLB_Clk => MPLB_Clk, -- [In std_logic]
MPLB_Rst => MPLB_Rst, -- [In std_logic]
MD_Error => MD_Error, -- [Out std_logic]
-- Master Request/Qualifiers to PLB V4.6 (outputs)
M_request => M_request, -- [out std_logic]
M_priority => M_priority, -- [out std_logic_vector(0 to 1)]
M_busLock => M_busLock, -- [out std_logic]
M_RNW => M_RNW, -- [out std_logic]
M_BE => M_BE, -- [out std_logic_vector(0 to (C_MPLB_DWIDTH/8) - 1)]
M_MSize => M_MSize, -- [out std_logic_vector(0 to 1)]
M_size => M_size, -- [out std_logic_vector(0 to 3)]
M_type => M_type, -- [out std_logic_vector(0 to 2)]
M_ABus => M_ABus, -- [out std_logic_vector(0 to 31)]
M_wrBurst => M_wrBurst, -- [out std_logic]
M_rdBurst => M_rdBurst, -- [out std_logic]
M_wrDBus => M_wrDBus, -- [out std_logic_vector(0 to C_MPLB_DWIDTH-1)]
-- PLB Reply to Master (inputs)
PLB_MAddrAck => PLB_MAddrAck, -- [in std_logic]
PLB_MSSize => PLB_MSSize, -- [in std_logic_vector(0 to 1)]
PLB_MRearbitrate => PLB_MRearbitrate, -- [in std_logic]
PLB_MTimeout => PLB_MTimeout, -- [in std_logic]
PLB_MRdErr => PLB_MRdErr, -- [in std_logic]
PLB_MWrErr => PLB_MWrErr, -- [in std_logic]
PLB_MRdDBus => PLB_MRdDBus, -- [in std_logic_vector(0 to C_MPLB_DWIDTH-1)]
PLB_MRdDAck => PLB_MRdDAck, -- [in std_logic]
PLB_MRdBTerm => PLB_MRdBTerm, -- [in std_logic]
PLB_MWrDAck => PLB_MWrDAck, -- [in std_logic]
PLB_MWrBTerm => PLB_MWrBTerm, -- [in std_logic]
-- Included PLB ports but unused in the design
M_TAttribute => M_TAttribute, -- [out std_logic_vector(0 to 15)]
M_lockErr => M_lockErr, -- [out std_logic]
M_abort => M_abort, -- [out std_logic]
M_UABus => M_UABus, -- [out std_logic_vector(0 to 31)]
PLB_MBusy => PLB_MBusy, -- [in std_logic]
PLB_MIRQ => PLB_MIRQ, -- [in std_logic]
PLB_MRdWdAddr => PLB_MRdWdAddr, -- [in std_logic_vector(0 to 3)]
-- IP Master Request/Qualifiers
IP2Bus_MstRd_Req => IP2Bus_MstRd_Req, -- [In std_logic]
IP2Bus_MstWr_Req => IP2Bus_MstWr_Req, -- [In std_logic]
IP2Bus_Mst_Addr => IP2Bus_Mst_Addr, -- [in std_logic_vector(0 toC_MPLB_AWIDTH-1)]
IP2Bus_Mst_Length => IP2Bus_Mst_Length, -- [in std_logic_vector(0 to 11)]
IP2Bus_Mst_BE => IP2Bus_Mst_BE, -- [in std_logic_vector(0 to(C_MPLB_NATIVE_DWIDTH/8) -1)]
IP2Bus_Mst_Type => IP2Bus_Mst_Type, -- [in std_logic]
IP2Bus_Mst_Lock => IP2Bus_Mst_Lock, -- [In std_logic]
IP2Bus_Mst_Reset => IP2Bus_Mst_Reset, -- [In std_logic]
-- IP Master Primary Read Request Status Reply
Bus2IP_Mst_CmdAck => Bus2IP_Mst_CmdAck, -- [Out std_logic]
Bus2IP_Mst_Cmplt => Bus2IP_Mst_Cmplt, -- [Out std_logic]
Bus2IP_Mst_Error => Bus2IP_Mst_Error, -- [Out std_logic]
Bus2IP_Mst_Rearbitrate => Bus2IP_Mst_Rearbitrate, -- [Out std_logic]
Bus2IP_Mst_Cmd_Timeout => Bus2IP_Mst_Cmd_Timeout, -- [out std_logic]
-- IP Master Primary Read LocalLink Interface
Bus2IP_MstRd_d => Bus2IP_MstRd_d, -- [out std_logic_vector(0 to C_MPLB_NATIVE_DWIDTH-1)]
Bus2IP_MstRd_rem => OPEN, -- [out std_logic_vector(0 to (C_MPLB_NATIVE_DWIDTH/8)-1)]
Bus2IP_MstRd_sof_n => Bus2IP_MstRd_sof_n, -- [Out std_logic]
Bus2IP_MstRd_eof_n => Bus2IP_MstRd_eof_n, -- [Out std_logic]
Bus2IP_MstRd_src_rdy_n => Bus2IP_MstRd_src_rdy_n, -- [Out std_logic]
Bus2IP_MstRd_src_dsc_n => Bus2IP_MstRd_src_dsc_n, -- [Out std_logic]
IP2Bus_MstRd_dst_rdy_n => IP2Bus_MstRd_dst_rdy_n, -- [In std_logic]
IP2Bus_MstRd_dst_dsc_n => IP2Bus_MstRd_dst_dsc_n, -- [In std_logic]
-- IP Master Primary Write LocalLink Interface
IP2Bus_MstWr_d => IP2Bus_MstWr_d, -- [In std_logic_vector(0 to C_MPLB_NATIVE_DWIDTH-1)]
IP2Bus_MstWr_rem => IP2Bus_MstWr_rem, -- [In std_logic_vector(0 to (C_MPLB_NATIVE_DWIDTH/8)-1)]
IP2Bus_MstWr_sof_n => IP2Bus_MstWr_sof_n, -- [In std_logic]
IP2Bus_MstWr_eof_n => IP2Bus_MstWr_eof_n, -- [In std_logic]
IP2Bus_MstWr_src_rdy_n => IP2Bus_MstWr_src_rdy_n, -- [In std_logic]
IP2Bus_MstWr_src_dsc_n => IP2Bus_MstWr_src_dsc_n, -- [In std_logic]
Bus2IP_MstWr_dst_rdy_n => Bus2IP_MstWr_dst_rdy_n, -- [Out std_logic]
Bus2IP_MstWr_dst_dsc_n => Bus2IP_MstWr_dst_dsc_n); -- [Out std_logic]
x_rd_buffer : ENTITY opb_plbv46_bridge_v1_01_a.buffer_x16
GENERIC MAP (
C_FAMILY => C_FAMILY) -- [string] Xilinx FPGA Family Type spartan3, virtex4, virtex5
PORT MAP (
-- Source Interface (from the OPB slave)
bfs_data => bfs_data, -- [OUT std_logic_vector(0 TO 31)] Read data output to user logic
bfs_sof_n => bfs_sof_n, -- [OUT std_logic] Active low signal indicating the starting data beat of a read local link transfer (unused by slave)
bfs_eof_n => bfs_eof_n, -- [OUT std_logic] Active low signal indicating the ending data beat of a Read local link transfer. (Unused by slave)
bfs_src_rdy_n => bfs_src_rdy_n, -- [OUT std_logic] Asserts active low to indicate the presence of valid data on signal bfs_data.
bfs_src_dsc_n => bfs_src_dsc_n, -- [OUT std_logic] Active low signal indicating that the read local link source (master) needs to discontinue the transfer. (Unused. Drive high)
bfs_dst_rdy_n => bfs_dst_rdy_n, -- [IN std_logic] Destination (ie the slave) asserts active low to signal it is ready to take valid data on bfs_data.
bfs_dst_dsc_n => bfs_dst_dsc_n, -- [IN std_logic] Active low signal that the read local link destination needs to discontinue the transfer.
-- Destination (Sink) Interface (to the plbv46_master_burst)
bfd_data => Bus2IP_MstRd_d, -- [IN std_logic_vector(0 TO 31)]
bfd_sof_n => Bus2IP_MstRd_sof_n, -- [IN std_logic]
bfd_eof_n => Bus2IP_MstRd_eof_n, -- [IN std_logic]
bfd_src_rdy_n => Bus2IP_MstRd_src_rdy_n, -- [IN std_logic]
bfd_src_dsc_n => Bus2IP_MstRd_src_dsc_n, -- [IN std_logic]
bfd_dst_rdy_n => IP2Bus_MstRd_dst_rdy_n, -- [OUT std_logic]
bfd_dst_dsc_n => IP2Bus_MstRd_dst_dsc_n, -- [OUT std_logic]
-- System Interface
rst => brdg_rd_bf_rst, -- [IN std_logic] reset
clk => MPLB_clk); -- [IN std_logic] clock
x_wr_buffer : ENTITY opb_plbv46_bridge_v1_01_a.buffer_x16
GENERIC MAP (
C_FAMILY => C_FAMILY) -- [string] Xilinx FPGA Family Type spartan3, virtex4, virtex5
PORT MAP (
-- Source Interface (from the plbv46_master_burst)
bfs_data => IP2Bus_MstWr_d, -- [OUT std_logic_vector(0 TO 31)] Read data output to user logic
bfs_sof_n => IP2Bus_MstWr_sof_n, -- [OUT std_logic] Active low signal indicating the starting data beat of a read local link transfer (unused by slave)
bfs_eof_n => IP2Bus_MstWr_eof_n, -- [OUT std_logic] Active low signal indicating the ending data beat of a Read local link transfer. (Unused by slave)
bfs_src_rdy_n => IP2Bus_MstWr_src_rdy_n, -- [OUT std_logic] Asserts active low to indicate the presence of valid data on signal bfs_data.
bfs_src_dsc_n => IP2Bus_MstWr_src_dsc_n, -- [OUT std_logic] Active low signal indicating that the read local link source (master) needs to discontinue the transfer. (Unused. Drive high)
bfs_dst_rdy_n => Bus2IP_MstWr_dst_rdy_n, -- [IN std_logic] Destination (ie the slave) asserts active low to signal it is ready to take valid data on bfs_data.
bfs_dst_dsc_n => Bus2IP_MstWr_dst_dsc_n, -- [IN std_logic] Active low signal that the read local link destination needs to discontinue the transfer.
-- Destination (Sink) Interface (to the opb_slave)
bfd_data => bfd_data, -- [IN std_logic_vector(0 TO 31)]
bfd_sof_n => bfd_sof_n, -- [IN std_logic]
bfd_eof_n => bfd_eof_n, -- [IN std_logic]
bfd_src_rdy_n => bfd_src_rdy_n, -- [IN std_logic]
bfd_src_dsc_n => bfd_src_dsc_n, -- [IN std_logic]
bfd_dst_rdy_n => bfd_dst_rdy_n, -- [OUT std_logic]
bfd_dst_dsc_n => bfd_dst_dsc_n, -- [OUT std_logic]
-- System Interface
rst => brdg_wr_bf_rst, -- [IN std_logic] reset
clk => MPLB_clk); -- [IN std_logic] clock
x_bridge : ENTITY opb_plbv46_bridge_v1_01_a.bridge
GENERIC MAP (
-- BRIDGE CONFIGURATION
C_PREFETCH_TIMEOUT => C_PREFETCH_TIMEOUT, --
-- System wide Specification
C_FAMILY => C_FAMILY) -- [string] Xilinx FPGA Family Type spartan3, virtex4, virtex5
PORT MAP (
-- PLBV46 Master Burst Interface
IP2Bus_MstRd_Req => IP2Bus_MstRd_Req, -- [OUT std_logic] User Logic Read Request
IP2Bus_MstWr_Req => IP2Bus_MstWr_Req, -- [OUT std_logic] User Logic Write Request
IP2Bus_Mst_Addr => IP2Bus_Mst_Addr, -- [OUT std_logic_vector(0 TO 32-1)] User Logic Request Address
IP2Bus_Mst_BE => IP2Bus_Mst_BE, -- [OUT std_logic_vector(0 TO (32/8)-1)] User Logic Request Byte Enables (only used during single data beat requests)
IP2Bus_Mst_Length => IP2Bus_Mst_Length, -- [OUT std_logic_vector(0 TO 11)]
IP2Bus_Mst_Type => IP2Bus_Mst_Type, -- [OUT std_logic] User Logic Request Type Indicator
IP2Bus_Mst_Lock => IP2Bus_Mst_Lock, -- [OUT std_logic] User Logic Bus Lock Request
IP2Bus_Mst_Reset => IP2Bus_Mst_Reset, -- [OUT std_logic] Optional User Logic Reset Request.
Bus2IP_Mst_CmdAck => Bus2IP_Mst_CmdAck, -- [IN std_logic] Command Acknowledge Status
Bus2IP_Mst_Cmplt => Bus2IP_Mst_Cmplt, -- [IN std_logic] Command Complete Status
Bus2IP_Mst_Error => Bus2IP_Mst_Error, -- [IN std_logic] Command Error Status
Bus2IP_Mst_Rearbitrate => Bus2IP_Mst_Rearbitrate, -- [IN std_logic] Command Rearbitrate Status
Bus2IP_Mst_Cmd_Timeout => Bus2IP_Mst_Cmd_Timeout, -- [IN std_logic] Command Timeout Status
-- opb_slave Interface
opbs_prefetch_req => opbs_prefetch_req, -- [IN std_logic] opb slave prefetch request
opbs_type => opbs_type, -- [IN std_logic] opb slave transaction request type
opbs_prefetch_clr => opbs_prefetch_clr, -- [IN std_logic] opb slave prefetch clear
opbs_postedwr_clr => opbs_postedwr_clr, -- [IN std_logic] opb slave posted write clear
opbs_length => opbs_length, -- [IN std_logic_vector(0 TO 11)] opb slave transaction length
opbs_postedwrt_req => opbs_postedwrt_req, -- [IN std_logic] opb slave posted write request
opbs_trans_addr => opbs_trans_addr, -- [IN std_logic_vector(0 TO 31)] opb slave transaction address
opbs_be => opbs_be, -- [IN std_logic_vector(0 TO 3)] opb slave byte enable
brdg_block => brdg_block, -- [OUT std_logic] bridge block
brdg_prefetch_cmplt => brdg_prefetch_cmplt, -- [OUT std_logic] bridge prefetch complete
brdg_prefetch_status => brdg_prefetch_status, -- [OUT std_logic] bridge prefetch status
-- Buffer Interface
brdg_wr_bf_rst => brdg_wr_bf_rst, -- [OUT std_logic] bridge write buffer reset
brdg_rd_bf_rst => brdg_rd_bf_rst, -- [OUT std_logic] bridge read buffer reset
-- System
MPLB_rst => MPLB_rst, -- [IN std_logic] plb reset
MPLB_clk => MPLB_clk); -- [IN std_logic] plb clock
x_opb_slave : ENTITY opb_plbv46_bridge_v1_01_a.opb_slave
GENERIC MAP (
-- OPB Address range definition
C_NUM_ADDR_RNG => C_NUM_ADDR_RNG, -- [integer RANGE 1 TO 4] Number of Address Ranges
C_RNG0_BASEADDR => C_RNG0_BASEADDR, -- [std_logic_vector(0 TO 31)] Address range definition base address
C_RNG0_HIGHADDR => C_RNG0_HIGHADDR, -- [std_logic_vector(0 TO 31)] Address range definition high address
C_RNG1_BASEADDR => C_RNG1_BASEADDR, -- [std_logic_vector(0 TO 31)] Address range definition base address
C_RNG1_HIGHADDR => C_RNG1_HIGHADDR, -- [std_logic_vector(0 TO 31)] Address range definition high address
C_RNG2_BASEADDR => C_RNG2_BASEADDR, -- [std_logic_vector(0 TO 31)] Address range definition base address
C_RNG2_HIGHADDR => C_RNG2_HIGHADDR, -- [std_logic_vector(0 TO 31)] Address range definition high address
C_RNG3_BASEADDR => C_RNG3_BASEADDR, -- [std_logic_vector(0 TO 31)] Address range definition base address
C_RNG3_HIGHADDR => C_RNG3_HIGHADDR, -- [std_logic_vector(0 TO 31)] Address range definition high address
-- BRIDGE CONFIGURATION
C_BUS_CLOCK_PERIOD_RATIO => C_BUS_CLOCK_PERIOD_RATIO, -- [integer RANGE 1 TO 2]
-- PLB I/O Specification
C_FAMILY => C_FAMILY) -- [string] Xilinx FPGA Family Type spartan3, virtex4, virtex5
PORT MAP (
-- OPBS Interface
brdg_block => brdg_block, -- [IN std_logic] bridge block
brdg_prefetch_cmplt => brdg_prefetch_cmplt, -- [IN std_logic] bridge prefetch complete
brdg_prefetch_status => brdg_prefetch_status, -- [IN std_logic] bridge prefetch status
opbs_prefetch_req => opbs_prefetch_req, -- [OUT std_logic] opb slave prefetch request
opbs_type => opbs_type, -- [OUT std_logic] opb slave transaction request type
opbs_prefetch_clr => opbs_prefetch_clr, -- [OUT std_logic] opb slave prefetch clear
opbs_postedwr_clr => opbs_postedwr_clr, -- [OUT std_logic] opb slave posted write clear
opbs_trans_addr => opbs_trans_addr, -- [OUT std_logic_vector(0 TO 31)] opb slave transaction address
opbs_length => opbs_length, -- [OUT std_logic_vector(0 TO 11)] opb slave transaction length
opbs_postedwrt_req => opbs_postedwrt_req, -- [OUT std_logic] opb slave posted write request
opbs_be => opbs_be, -- [OUT std_logic_vector(0 TO 3)] opb slave byte enable
-- Local Link Read Buffer
bfs_data => bfs_data, -- [IN std_logic_vector(0 TO 31)] Read data output to user logic
bfs_sof_n => bfs_sof_n, -- [IN std_logic] Active low signal indicating the starting data beat of a read local link transfer (unused by slave)
bfs_eof_n => bfs_eof_n, -- [IN std_logic] Active low signal indicating the ending data beat of a Read local link transfer. (Unused by slave)
bfs_src_rdy_n => bfs_src_rdy_n, -- [IN std_logic] Asserts active low to indicate the presence of valid data on signal bfs_data.
bfs_src_dsc_n => bfs_src_dsc_n, -- [IN std_logic] Active low signal indicating that the read local link source (master) needs to discontinue the transfer. (Unused. Drive high)
bfs_dst_rdy_n => bfs_dst_rdy_n, -- [OUT std_logic] Destination (ie the slave) asserts active low to signal it is ready to take valid data on bfs_data.
bfs_dst_dsc_n => bfs_dst_dsc_n, -- [OUT std_logic] Active low signal that the read local link destination needs to discontinue the transfer.
-- Local Link Write Buffer
bfd_data => bfd_data, -- [OUT std_logic_vector(0 TO 31)]
bfd_sof_n => bfd_sof_n, -- [OUT std_logic]
bfd_eof_n => bfd_eof_n, -- [OUT std_logic]
bfd_src_rdy_n => bfd_src_rdy_n, -- [OUT std_logic]
bfd_src_dsc_n => bfd_src_dsc_n, -- [OUT std_logic]
bfd_dst_rdy_n => bfd_dst_rdy_n, -- [IN std_logic]
bfd_dst_dsc_n => bfd_dst_dsc_n, -- [IN std_logic]
-- OPB Slave Interface
OPB_Select => OPB_Select, -- [IN std_logic] OPB Master select
OPB_RNW => OPB_RNW, -- [IN std_logic] OPB Read not Write
OPB_BE => OPB_BE, -- [IN std_logic_vector(0 TO (32/8)-1)] OPB transaction byte enables
OPB_seqAddr => OPB_seqAddr, -- [IN std_logic] OPB sequential address
OPB_DBus => OPB_DBus, -- [IN std_logic_vector(0 TO 32-1)] OPB master data bus
OPB_ABus => OPB_ABus, -- [IN std_logic_vector(0 TO 32-1)] OPB Slave address bus
Sl_xferAck => Sl_xferAck, -- [OUT std_logic] OPB Slave transfer acknowledgement
Sl_errAck => Sl_errAck, -- [OUT std_logic] OPB Slave transaction error acknowledgement
Sl_retry => Sl_retry, -- [OUT std_logic] OPB Slave transaction retry
Sl_ToutSup => Sl_ToutSup, -- [OUT std_logic] OPB Slave timeout suppress
Sl_DBus => Sl_DBus, -- [OUT std_logic_vector(0 TO 32-1)] OPB Slave data BUS
-- System Interface
MPLB_rst => MPLB_rst, -- [IN std_logic] plb reset
MPLB_clk => MPLB_clk, -- [IN std_logic] plb clock
SOPB_rst => SOPB_rst, -- [IN std_logic] opbv46 reset
SOPB_clk => SOPB_clk); -- [IN std_logic] opbv46 clock
END ARCHITECTURE syn;
|
bsd-3-clause
|
jevinskie/aes-over-pcie
|
source/tb_aes_rcu.vhd
|
1
|
2425
|
-- File name: tb_aes_rcu.vhd
-- Created: 4/4/2009
-- Author: Zachary Curosh
-- Lab Section: 337-02
-- Version: 1.0 Initial Test Bench
use work.aes.all;
library ieee;
--library gold_lib; --UNCOMMENT if you're using a GOLD model
use ieee.std_logic_1164.all;
--use gold_lib.all; --UNCOMMENT if you're using a GOLD model
entity tb_aes_rcu is
generic (clk_per : time := 4 ns);
end tb_aes_rcu ;
architecture TEST of tb_aes_rcu is
-- Insert signals Declarations here
signal clk : std_logic := '0';
signal nrst : std_logic;
signal p : g_index;
signal subblock : subblock_type;
signal encryption_key : key_type;
signal stop : std_logic := '1';
signal sbox_lookup, sbox_return : byte;
signal round_key : key_type;
signal start_key : std_logic;
signal key_done : std_logic;
signal go : std_logic;
signal done: std_logic;
signal current_round: round_type;
begin
behavioral: entity work.aes_rcu (behavioral) port map(
clk => clk,
nrst => nrst,
p => p,
subblock => subblock,
start_key => start_key,
key_done => done,
current_round => current_round,
got_pt => open,
got_key => open
);
keysched: entity work.key_scheduler(behavioral) port map(
clk => clk,
nrst => nrst,
sbox_lookup=>sbox_lookup,
sbox_return=>sbox_return,
round => current_round,
key_load,
round_key => round_key,
go => start_key,
done => done
);
data : entity work.sbox(dataflow) port map (
clk => clk, a => sbox_lookup, b => sbox_return
);
-- GOLD: <GOLD_NAME> port map(<put mappings here>);
-- clock when stop isnt asserted
clk <= not clk and not stop after clk_per/2;
process
begin
encryption_key <= ((x"00", x"00", x"00", x"00"), (x"00", x"00",
x"00", x"00"), (x"00", x"00", x"00", x"00"),
(x"00", x"00", x"00", x"00"));
-- start the clock
stop <= '0';
nrst <= '0';
wait for clk_per*4;
nrst <= '1';
wait for clk_per*2;
wait for clk_per*3000;
-- stop the clock
stop <= '1';
wait;
end process;
end TEST;
|
bsd-3-clause
|
masson2013/heterogeneous_hthreads
|
src/platforms/xilinx/smp3_opbhwti/design/pcores/opb_v20_v1_10_d/hdl/vhdl/arbitration_logic.vhd
|
3
|
34676
|
-------------------------------------------------------------------------------
-- $Id: arbitration_logic.vhd,v 1.1.2.1 2009/10/06 21:14:59 gburch Exp $
------------------------------------------------------------------------------
-- arbitration_logic.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
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-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
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-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
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-- ** code, or information as one possible implementation of **
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-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: arbitration_logic.vhd
-- Version: v1.02e
-- Description:
-- This file contains the priority encoding for the Masters.
-- Based on the current priority of the Masters and their
-- requests, it determines an intermediate grant signal for
-- the Masters. This intermediate grant signal is then input
-- to the Park Lock Logic block to determine the final grant
-- signal based on bus parking and locking.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- opb_arbiter.vhd
-- --opb_arbiter_core.vhd
-- -- ipif_regonly_slave.vhd
-- -- priority_register_logic.vhd
-- -- priority_reg.vhd
-- -- onehot2encoded.vhd
-- -- or_bits.vhd
-- -- control_register.vhd
-- -- arb2bus_data_mux.vhd
-- -- mux_onehot.vhd
-- -- or_bits.vhd
-- -- watchdog_timer.vhd
-- -- arbitration_logic.vhd
-- -- or_bits.vhd
-- -- park_lock_logic.vhd
-- -- or_bits.vhd
-- -- or_gate.vhd
-- -- or_muxcy.vhd
-------------------------------------------------------------------------------
-- Author: ALS
-- History:
-- ALS 08/28/01 -- Version 1.01a creation to include IPIF v1.22a
-- ALS 10/04/01 -- Version 1.02a creation to include IPIF v1.23a
-- ALS 11/30/01
-- ^^^^^^
-- Created version 1.02b to fix problem with registered grants in fixed priority.
-- Created a state machine to generate arb_cycle when grants are registered and
-- in fixed priority. This is not needed in dynamic priority because the internal
-- grant pipeline registers are only enabled during valid arb cycles - also not
-- needed in combinational grants because there isn't a clock delay before master
-- sees the grant and responds with select.
-- ~~~~~~
--
-- ALS 01/24/02
-- ^^^^^^
-- Created version 1.02c to fix problem with registered grants, and buslock when
-- the buslock master is holding request high and performing conversion cycles.
-- Modified the code so that the arbitration cycle and/or the internal grant
-- register enables are based off the external grants, i.e., grants output
-- to the bus taking into account buslock and park.
-- When in dynamic priority and combinational outputs, the internal grant
-- registers are like the final registers, so the state machine to control
-- the enable is based on the external grants. When in dynamic priority and
-- registered outputs, the internal state machine is enabled by using the
-- internal grants and the grant registers are enabled by arb_cycle. Arb_cycle
-- is generated from a state machine that uses the external grants. When in
-- fixed priority and registered grants, the same applies. When in fixed priority
-- and combinational grants, arb_cycle is generated by simply examining OPB_Select
-- and OPB_xferAck.
-- ~~~~~~~
-- ALS 01/09/03
-- ^^^^^^
-- Created version 1.02d to register OPB_timeout to improve timing
-- ~~~~~~
-- bsbrao 09/27/04
-- ^^^^^^
-- Created version 1.02e to upgrade IPIF from opb_ipif_v1_23_a to
-- opb_ipif_v3_01_a
-- ~~~~~~
-- LCW 02/04/05 - update library statements
-- ~~~~~~
-- chandan 05/25/06
-- ^^^^^^
-- Modified the process MASTERLOOP to remove the latch it was creating.
-- ~~~~~~
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.std_logic_arith.conv_std_logic_vector;
--
-- library unsigned is used for overloading of "=" which allows integer to
-- be compared to std_logic_vector
use ieee.std_logic_unsigned.all;
-- The unisim library is required to instantiate Xilinx primitives.
library unisim;
use unisim.vcomponents.all;
library opb_v20_v1_10_d;
use opb_v20_v1_10_d.opb_arb_pkg.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_NUM_MASTERS -- number of masters
-- C_NUM_MID_BITS -- number of bits required to encode master ids
-- C_OPBDATA_WIDTH -- number of bits in OPB data bus
-- C_DYNAM_PRIORITY -- dynamic or fixed priority
-- C_REG_GRANTS -- registered or combinatorial grant outputs
--
-- Definition of Ports:
--
-- input OPB_select -- indicates a Master is controlling the bus
-- input OPB_xferAck -- transfer acknowledge
-- input M_request -- bus of master request signals
-- input OPB_buslock -- indicates the OPB is locked
-- input Bus_park -- indicates that the bus is parked
-- input Any_mgrant -- indicates that a Master has been granted the bus
-- input Priority_ids -- the priority IDs of the masters
--
-- output Arb_cycle -- arbitration cycle
-- output Grant -- intermediate Master grant signals
--
-- -- System signals
-- input Clk
-- input Rst
--
-------------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity arbitration_logic is
generic( C_NUM_MASTERS : integer := 16;
C_NUM_MID_BITS : integer := 4;
C_OPBDATA_WIDTH : integer := 32;
C_DYNAM_PRIORITY: boolean := false;
C_REG_GRANTS : boolean := false
);
port (
OPB_select : in std_logic;
OPB_xferAck : in std_logic;
M_request : in std_logic_vector(0 to C_NUM_MASTERS-1);
OPB_buslock : in std_logic;
Bus_park : in std_logic;
Any_mgrant : in std_logic;
Priority_ids : in std_logic_vector(0 to C_NUM_MASTERS*C_NUM_MID_BITS-1);
Arb_cycle : out std_logic;
Grant : out std_logic_vector(0 to C_NUM_MASTERS-1);
Clk : in std_logic;
Rst : in std_logic
);
end arbitration_logic;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of arbitration_logic is
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- number of priority levels is equal to the number of masters
constant NUM_LVLS : integer := C_NUM_MASTERS;
-- pad number of masters to nearest power of 2 for mux_encode_sel
constant NUM_MSTRS_PAD : integer := pad_power2(C_NUM_MASTERS);
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
-- Need active low request signals to properly drive select lines of muxes
-- this bus will use NUM_MSTRS_PAD so that bus is sized to nearest power of 2
-- for mux_encode_sel. Bus defaults to '0', only the bits up to C_NUM_MASTERS
-- will get assigned a real value.
signal m_request_n : std_logic_vector(0 to NUM_MSTRS_PAD-1) := (others => '0');
-- declare a 2-dimensional array for each master's priority level and mux chain
type MASTER_LVL_TYPE is array(0 to C_NUM_MASTERS-1) of std_logic_vector(0 to NUM_LVLS-1);
signal M_req_lvl : MASTER_LVL_TYPE; -- holds master's priority levels
signal M_muxout : MASTER_LVL_TYPE; -- output of each MUXCY
-- declare a signal to hold decode requests
-- active low bus where if the bit location =0, a request was received at that priority
-- level
signal request_lvl_n : std_logic_vector(0 to NUM_LVLS-1);
-- internal intermediate grant signals
signal grant_i : std_logic_vector(0 to C_NUM_MASTERS-1);
-- OR of all intermediate grant signals
signal any_grant : std_logic;
-- enables grant registers
signal en_grant_reg : std_logic := '0';
-- Enable Grant State Machine signals for dynamic priority, registered outputs
type ENGRNTREG_STATE_TYPE is (IDLE, WAIT1, WAIT2, CHK_SELECT);
signal engrntreg_cs : ENGRNTREG_STATE_TYPE := IDLE;
signal engrntreg_ns : ENGRNTREG_STATE_TYPE := IDLE;
-- Enable Grant State Machine signals for dynamic priority, combinational outputs
type ENGRNTCMB_STATE_TYPE is (IDLE, CHK_SELECT);
signal engrntcmb_cs : ENGRNTCMB_STATE_TYPE := IDLE;
signal engrntcmb_ns : ENGRNTCMB_STATE_TYPE := IDLE;
-- Arb Cycle State Machine signals
type ARBCYCLE_STATE_TYPE is (IDLE, CHK_SELECT);
signal arbcycle_cs : ARBCYCLE_STATE_TYPE := IDLE;
signal arbcycle_ns : ARBCYCLE_STATE_TYPE := IDLE;
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- MUXCY - carry chain multiplexors
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- OR_BITS is used to OR all of the intermediate Grant signals so that the
-- enable can be generated to the grant registers (only used when C_DYNAM_PRIORITY
-- =1)
-------------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Begin architecture
-----------------------------------------------------------------------------
begin
-- If Dynamic priority with registered outputs, determine
-- if any grant has been asserted. This is to used to enable the
-- internal grant registers at the proper time.
ANY_GRNT_GEN: if (C_DYNAM_PRIORITY and C_REG_GRANTS) generate
OR_IGRNTS_I: entity opb_v20_v1_10_d.or_bits
generic map( C_NUM_BITS => C_NUM_MASTERS,
C_START_BIT => 0,
C_BUS_SIZE => C_NUM_MASTERS)
port map ( In_bus => grant_i,
Sig => '0',
Or_out => any_grant
);
end generate ANY_GRNT_GEN;
-------------------------------------------------------------------------------
-- Set output grants to internal grants
-- If parameterized for dynamic priority, register these signals
-- have to generate the correct clock enables for these internal registers
-- If parameterized for fixed priority, simply assign them
-------------------------------------------------------------------------------
FIXED_GRANT_GENERATE: if not(C_DYNAM_PRIORITY) generate
Grant <= grant_i;
end generate FIXED_GRANT_GENERATE;
DYNAM_GRANT_GENERATE: if C_DYNAM_PRIORITY generate
-- when dyanmic priority and combinational outputs, generate enables to
-- internal grant registers based on the external bus grants (any_mgrant).
DYNAM_CMB_GRANT_GEN: if not(C_REG_GRANTS) generate
---------------------------------------------------------------------------
--ENGRNTCMB_CMB_PROCESS
--ENGRNTCMB_REG_PROCESS
--
-- This state machine generates the enable for the grant registers. When
-- any bus grant is asserted, the grant registers are enabled. Then the state
-- machine checks OPB_select. If its
-- negated, the master has aborted the transaction and the grant registers
-- are enabled if any_mgrant is still asserted. If select is asserted, then
-- the state machine waits for OPB_xferAck and enables
-- the grant registers when these are asserted.
---------------------------------------------------------------------------
ENGRNTCMB_CMB_PROCESS: process (OPB_select, any_mgrant, OPB_xferAck, engrntcmb_cs)
begin
-- set defaults
en_grant_reg<= '0';
engrntcmb_ns <= engrntcmb_cs;
case engrntcmb_cs is
-------------------------- IDLE State -----------------------------
-- wait in this state until OPB_Select or any_mgrant asserts
-- negate en_grant_reg and either wait for OPB_select to assert or
-- if its asserted, wait for XferAck.
when IDLE =>
en_grant_reg<= '1';
if OPB_Select = '1' or
any_mgrant = '1' then
en_grant_reg<= '0';
engrntcmb_ns <= CHK_SELECT;
end if;
-------------------------- CHK_SELECT State -----------------------
-- OPB_Select should be asserted in this state
-- if its not asserted, the master has aborted the transaction,so
-- en_grant_reg should be asserted. If OPB_select is asserted, wait
-- for OPB_xferAck to assert en_grant_reg. If any_mgrant
-- is asserted, return to IDLE, otherwise stay in this
-- state
when CHK_SELECT =>
if OPB_select = '0' then
if any_mgrant = '0' then
en_grant_reg<= '1';
engrntcmb_ns <= IDLE;
end if;
elsif OPB_xferAck = '1'then
if any_mgrant = '0' then
en_grant_reg<= '1';
engrntcmb_ns <= IDLE;
end if;
end if;
-------------------------- DEFAULT State --------------------------
when others =>
engrntcmb_ns <= IDLE;
end case;
end process ENGRNTCMB_CMB_PROCESS;
-- ENGRNTCMB_REG_PROCESS
ENGRNTCMB_REG_PROCESS:
process (Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst = RESET_ACTIVE) then
engrntcmb_cs <= IDLE;
else
engrntcmb_cs <= engrntcmb_ns;
end if;
end if;
end process ENGRNTCMB_REG_PROCESS;
end generate DYNAM_CMB_GRANT_GEN;
-- when dyanmic priority and registered outputs, generate enables to
-- internal grant registers based on the internal bus grants (any_grant).
DYNAM_REG_GRANT_GEN: if C_REG_GRANTS generate
ENGRNTREG_CMB_PROCESS: process (OPB_select, any_grant, OPB_xferAck, engrntreg_cs)
-- set defaults
begin
en_grant_reg <= '0';
engrntreg_ns <= engrntreg_cs;
case engrntreg_cs is
-------------------------- IDLE State -----------------------------
-- wait in this state until any_grant asserts, then enable the
-- grant registers and begin waiting through the grant pipeline
when IDLE =>
if OPB_select = '1' then
engrntreg_ns <= CHK_SELECT;
elsif any_grant = '1' then
engrntreg_ns <= WAIT1;
en_grant_reg <= '1';
end if;
-------------------------- WAIT1 State ----------------------------
-- this state represents the internal grant registers
-- wait another state before checking OPB_select
when WAIT1 =>
engrntreg_ns <= WAIT2;
-------------------------- WAIT2 State ----------------------------
-- this state represents the registers on the grant outputs
-- check OPB_select in the next clock
when WAIT2 =>
engrntreg_ns <= CHK_SELECT;
-------------------------- CHK_SELECT State -----------------------
-- OPB_Select should be asserted in this state
-- if its not asserted, the master has aborted the transaction,so
-- the grant registers need to be enabled to allow the next grant
-- to flow through the pipeline. If OPB_select is asserted, wait
-- for OPB_xferAck assert. When asserted, enable the grant registers.
-- If any_grant is asserted, return to the WAIT1 state, otherwise
-- return to the IDLE state.
when CHK_SELECT =>
if OPB_select = '0' then
if any_grant = '1' then
en_grant_reg <= '1';
engrntreg_ns <= WAIT1;
else
engrntreg_ns <= IDLE;
end if;
elsif OPB_xferAck = '1' then
if any_grant = '1' then
en_grant_reg <= '1';
engrntreg_ns <= WAIT1;
else
engrntreg_ns <= IDLE;
end if;
end if;
-------------------------- DEFAULT State --------------------------
when others =>
engrntreg_ns <= IDLE;
end case;
end process ENGRNTREG_CMB_PROCESS;
-- ENGRNTREG_REG_PROCESS
ENGRNTREG_REG_PROCESS:
process (Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst = RESET_ACTIVE) then
engrntreg_cs <= IDLE;
else
engrntreg_cs <= engrntreg_ns;
end if;
end if;
end process ENGRNTREG_REG_PROCESS;
end generate DYNAM_REG_GRANT_GEN;
---------------------------------------------------------------------------
-- REGGRNT_PROCESS defines the registes on the arbiter grant outputs
---------------------------------------------------------------------------
REGGRNT_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Rst = RESET_ACTIVE then
Grant <= (others => '0');
elsif en_grant_reg = '1' then
Grant <= grant_i;
else
Grant <= (others => '0');
end if;
end if;
end process;
end generate DYNAM_GRANT_GENERATE;
-------------------------------------------------------------------------------
-- Set arbitration cycle signal
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- When combinational grant outputs, valid arbitration cycles
-- are when OPB_select = 0 or OPB_xferAck = 1
-------------------------------------------------------------------------------
CMB_ARBCYCLE_GEN: if not(C_REG_GRANTS) generate
Arb_cycle <= '1' when OPB_select = '0' or OPB_xferAck = '1'
else '0';
end generate CMB_ARBCYCLE_GEN;
-------------------------------------------------------------------------------
-- When registered grant outputs, arb_cycle is determined by
-- a state machine which waits the external bus grants to be output
-- and then checks select. Since it uses the output of the grant registers,
-- parking and locking are accounted for.
-------------------------------------------------------------------------------
REG_ARBCYCLE_GEN: if C_REG_GRANTS generate
ARBCYCLE_CMB_PROCESS: process (OPB_select, any_mgrant, OPB_xferAck,
arbcycle_cs, Bus_park)
begin
-- set defaults
Arb_cycle<= '0';
arbcycle_ns <= arbcycle_cs;
case arbcycle_cs is
-------------------------- IDLE State -----------------------------
-- wait in this state until OPB_Select or any_mgrant asserts
-- negate Arb_cycle and either wait for OPB_select to assert or
-- if its asserted, wait for XferAck.
when IDLE =>
Arb_cycle<= '1';
if (OPB_Select = '1' and OPB_xferAck = '0') or
(any_mgrant = '1') then
Arb_cycle<= '0';
arbcycle_ns <= CHK_SELECT;
end if;
-------------------------- CHK_SELECT State -----------------------
-- OPB_Select should be asserted in this state
-- if its not asserted, the master has aborted the transaction,so
-- Arb_cycle should be asserted. If OPB_select is asserted, wait
-- for OPB_xferAck to assert arb_cycle.
when CHK_SELECT =>
if OPB_select = '0' then
Arb_cycle<= '1';
if bus_park = '0' then
arbcycle_ns <= IDLE;
end if;
elsif OPB_xferAck = '1'then
Arb_cycle<= '1';
arbcycle_ns <= IDLE;
end if;
-------------------------- DEFAULT State --------------------------
when others =>
arbcycle_ns <= IDLE;
end case;
end process ARBCYCLE_CMB_PROCESS;
-- ARBCYCLE_REG_PROCESS
ARBCYCLE_REG_PROCESS:
process (Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst = RESET_ACTIVE) then
arbcycle_cs <= IDLE;
else
arbcycle_cs <= arbcycle_ns;
end if;
end if;
end process ARBCYCLE_REG_PROCESS;
end generate REG_ARBCYCLE_GEN;
--
-------------------------------------------------------------------------------
-- LOGIC DESCRIPTION
-------------------------------------------------------------------------------
-- The arbitration logic was designed using the Xilinx FPGA primitives so that
-- the fastest speed could be achieved. LUTs (Look-Up Tables) were used as MUXs
-- and OR/AND gates to determine the request level of each Master. The outputs
-- of the LUTs were then input to the carry chain muxes to determine whether
-- grant signal for that Master would be asserted. The MUX select signals were
-- signals indicating whether any Master had asserted a request for each
-- priority level.The inputs to the muxes were signals indicating
-- the level of each master's request. For example, the
-- first mux in the carry chain for Master 0 had the LVL3_0 and the LVL2_0
-- signals as inputs and the select signal was LVL2_REQ_N indicating that a
-- LVL2 request had been received. If this signal was asserted (active low)
-- then the output of the mux would be LVL2_0 and this would be an input to the
-- next mux in the priority carry chain which would select between LVL1 and
-- LVL2 requests, etc.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Mux Selects
-------------------------------------------------------------------------------
-- The mux selects are used in the carry chain for all masters. These signals
-- indicate whether any master had a request at a particular priority level.
-- This is essentially an encoded mux with each priority ID being the selects
-- and the Master requests being the data.
-------------------------------------------------------------------------------
MASTERLOOP: for i in 0 to C_NUM_MASTERS-1 generate --4
-- need active low request signals to properly drive mux select lines
-- if bus lock is not asserted
m_request_n(i) <= not(M_request(i))
when OPB_buslock = '0'
else '1';
MASTER_4 : if C_NUM_MID_BITS = 4 generate
signal priority_ids_int : std_logic_vector(0 to 3);
begin
priority_ids_int <= priority_ids(i*C_NUM_MID_BITS to (i*C_NUM_MID_BITS)+C_NUM_MID_BITS-1);
DECODE_REQ_PROCESS: process(m_request_n, priority_ids_int)
begin
case priority_ids_int is
when "0000" => request_lvl_n(i) <= m_request_n(0);
when "0001" => request_lvl_n(i) <= m_request_n(1);
when "0010" => request_lvl_n(i) <= m_request_n(2);
when "0011" => request_lvl_n(i) <= m_request_n(3);
when "0100" => request_lvl_n(i) <= m_request_n(4);
when "0101" => request_lvl_n(i) <= m_request_n(5);
when "0110" => request_lvl_n(i) <= m_request_n(6);
when "0111" => request_lvl_n(i) <= m_request_n(7);
when "1000" => request_lvl_n(i) <= m_request_n(8);
when "1001" => request_lvl_n(i) <= m_request_n(9);
when "1010" => request_lvl_n(i) <= m_request_n(10);
when "1011" => request_lvl_n(i) <= m_request_n(11);
when "1100" => request_lvl_n(i) <= m_request_n(12);
when "1101" => request_lvl_n(i) <= m_request_n(13);
when "1110" => request_lvl_n(i) <= m_request_n(14);
when others => request_lvl_n(i) <= m_request_n(15);
end case;
end process DECODE_REQ_PROCESS;
end generate MASTER_4;
MASTER_3 : if C_NUM_MID_BITS = 3 generate
signal priority_ids_int : std_logic_vector(0 to 2);
begin
priority_ids_int <= priority_ids(i*C_NUM_MID_BITS to (i*C_NUM_MID_BITS)+C_NUM_MID_BITS-1);
DECODE_REQ_PROCESS: process(m_request_n, priority_ids_int)
begin
case priority_ids_int is
when "000" => request_lvl_n(i) <= m_request_n(0);
when "001" => request_lvl_n(i) <= m_request_n(1);
when "010" => request_lvl_n(i) <= m_request_n(2);
when "011" => request_lvl_n(i) <= m_request_n(3);
when "100" => request_lvl_n(i) <= m_request_n(4);
when "101" => request_lvl_n(i) <= m_request_n(5);
when "110" => request_lvl_n(i) <= m_request_n(6);
when others => request_lvl_n(i) <= m_request_n(7);
end case;
end process DECODE_REQ_PROCESS;
end generate MASTER_3;
MASTER_2 : if C_NUM_MID_BITS = 2 generate
signal priority_ids_int : std_logic_vector(0 to 1);
begin
priority_ids_int <= priority_ids(i*C_NUM_MID_BITS to (i*C_NUM_MID_BITS)+C_NUM_MID_BITS-1);
DECODE_REQ_PROCESS: process(m_request_n, priority_ids_int)
begin
case priority_ids_int is
when "00" => request_lvl_n(i) <= m_request_n(0);
when "01" => request_lvl_n(i) <= m_request_n(1);
when "10" => request_lvl_n(i) <= m_request_n(2);
when others => request_lvl_n(i) <= m_request_n(3);
end case;
end process DECODE_REQ_PROCESS;
end generate MASTER_2;
MASTER_1 : if C_NUM_MID_BITS = 1 generate
signal priority_ids_int : std_logic_vector (0 to 0);
begin
priority_ids_int <= priority_ids(i*C_NUM_MID_BITS to (i*C_NUM_MID_BITS)+C_NUM_MID_BITS-1);
DECODE_REQ_PROCESS: process(m_request_n, priority_ids_int)
begin
case priority_ids_int is
when "0" => request_lvl_n(i) <= m_request_n(0);
when others => request_lvl_n(i) <= m_request_n(1);
end case;
end process DECODE_REQ_PROCESS;
end generate MASTER_1;
-- for each master, determine its priority level and if its request
-- is asserted
MASTERREQ_LVL: for j in 0 to NUM_LVLS-1 generate
REQPROC: process (m_request_n(i),
Priority_ids(j*C_NUM_MID_BITS to j*C_NUM_MID_BITS+C_NUM_MID_BITS-1))
begin
if m_request_n(i) = '0' then
if Priority_ids(j*C_NUM_MID_BITS to j*C_NUM_MID_BITS+C_NUM_MID_BITS-1)
= conv_std_logic_vector(i, C_NUM_MID_BITS) then
M_req_lvl(i)(j) <= '1';
else
M_req_lvl(i)(j) <= '0';
end if;
else
M_req_lvl(i)(j) <= '0';
end if;
end process REQPROC;
end generate MASTERREQ_LVL;
-- for each master, set up carry chain
MASTER_CHAIN: for j in NUM_LVLS-2 downto 0 generate
FIRSTMUX_GEN: if j = NUM_LVLS-2 generate
FIRST_I: MUXCY
port map (
O => M_muxout(i)(j), --[out]
CI => M_req_lvl(i)(j+1),--[in]
DI => M_req_lvl(i)(j), --[in]
S => request_lvl_n(j) --[in]
);
end generate FIRSTMUX_GEN;
OTHERMUX_GEN: if j /= NUM_LVLS-2 generate
OTHERS_I: MUXCY
port map (
O => M_muxout(i)(j), --[out]
CI => M_muxout(i)(j+1), --[in]
DI => M_req_lvl(i)(j),--[in]
S => request_lvl_n(j) --[in]
);
end generate OTHERMUX_GEN;
end generate MASTER_CHAIN;
grant_i(i) <= M_muxout(i)(0);
end generate MASTERLOOP;
end implementation;
|
bsd-3-clause
|
masson2013/heterogeneous_hthreads
|
src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/opb_v20_v1_10_d/hdl/vhdl/pf_counter_top.vhd
|
3
|
8419
|
-------------------------------------------------------------------------------
-- $Id: pf_counter_top.vhd,v 1.1.2.1 2009/10/06 21:15:01 gburch Exp $
-------------------------------------------------------------------------------
-- pf_counter_top - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pf_counter_top.vhd
--
-- Description: Implements parameterized up/down counter
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pf_counter_top.vhd
--
-------------------------------------------------------------------------------
-- Author: D. Thorpe
-- Revision: $Revision: 1.1.2.1 $
-- Date: $Date: 2009/10/06 21:15:01 $
--
-- History:
-- DET 2001-08-30 First Version
--
--
--
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
--Use IEEE.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
library opb_v20_v1_10_d;
use opb_v20_v1_10_d.pf_counter;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity pf_counter_top is
generic (
C_COUNT_WIDTH : integer := 10
);
port (
Clk : in std_logic;
Rst : in std_logic;
Load_Enable : in std_logic;
Load_value : in std_logic_vector(0 to C_COUNT_WIDTH-1);
Count_Down : in std_logic;
Count_Up : in std_logic;
--Carry_Out : out std_logic;
Count_Out : out std_logic_vector(0 to C_COUNT_WIDTH-1)
);
end entity pf_counter_top;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of pf_counter_top is
Signal sig_cnt_enable : std_logic;
Signal sig_cnt_up_n_dwn : std_logic;
Signal sig_carry_out : std_logic;
Signal sig_count_out : std_logic_vector(0 to C_COUNT_WIDTH-1);
begin -- VHDL_RTL
-- Misc signal assignments
Count_Out <= sig_count_out;
--Carry_Out <= sig_carry_Out;
sig_cnt_enable <= Count_Up xor Count_Down;
sig_cnt_up_n_dwn <= not(Count_Up);
I_UP_DWN_COUNTER : entity opb_v20_v1_10_d.pf_counter
generic map (
C_COUNT_WIDTH => C_COUNT_WIDTH
)
port map(
Clk => Clk, -- : in std_logic;
Rst => Rst, -- : in std_logic;
Carry_Out => sig_carry_out, -- : out std_logic;
Load_In => Load_value, -- : in std_logic_vector(0 to C_COUNT_WIDTH-1);
Count_Enable => sig_cnt_enable, -- : in std_logic;
Count_Load => Load_Enable, -- : in std_logic;
Count_Down => sig_cnt_up_n_dwn,-- : in std_logic;
Count_Out => sig_count_out -- : out std_logic_vector(0 to C_COUNT_WIDTH-1)
);
end architecture implementation;
|
bsd-3-clause
|
masson2013/heterogeneous_hthreads
|
src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/plb_cond_vars_v1_00_a/hdl/vhdl/condvar.vhd
|
10
|
18666
|
-- ************************************
-- Automatically Generated FSM
-- condvar
-- ************************************
-- **********************
-- Library inclusions
-- **********************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
-- **********************
-- Entity Definition
-- **********************
entity condvar is
generic(
G_ADDR_WIDTH : integer := 11;
G_OP_WIDTH : integer := 2;
G_TID_WIDTH : integer := 8
);
port
(
msg_chan_channelDataIn : out std_logic_vector(0 to (G_TID_WIDTH - 1));
msg_chan_channelDataOut : in std_logic_vector(0 to (G_TID_WIDTH - 1));
msg_chan_exists : in std_logic;
msg_chan_full : in std_logic;
msg_chan_channelRead : out std_logic;
msg_chan_channelWrite : out std_logic;
cmd : in std_logic;
opcode : in std_logic_vector(0 to G_OP_WIDTH - 1);
cvar : in std_logic_vector(0 to G_TID_WIDTH - 1);
tid : in std_logic_vector(0 to G_TID_WIDTH - 1);
ack : out std_logic;
clock_sig : in std_logic;
reset_sig : in std_logic
);
end entity condvar;
-- *************************
-- Architecture Definition
-- *************************
architecture IMPLEMENTATION of condvar is
component infer_bram
generic
(
ADDRESS_BITS : integer := 9;
DATA_BITS : integer := 32
);
port (
CLKA : in std_logic;
ENA : in std_logic;
WEA : in std_logic;
ADDRA : in std_logic_vector(0 to (ADDRESS_BITS - 1));
DIA : in std_logic_vector(0 to (DATA_BITS - 1));
DOA : out std_logic_vector(0 to (DATA_BITS - 1));
CLKB : in std_logic;
ENB : in std_logic;
WEB : in std_logic;
ADDRB : in std_logic_vector(0 to (ADDRESS_BITS - 1));
DIB : in std_logic_vector(0 to (DATA_BITS - 1));
DOB : out std_logic_vector(0 to (DATA_BITS - 1))
);
end component infer_BRAM;
-- ****************************************************
-- Type definitions for state signals
-- ****************************************************
type STATE_MACHINE_TYPE is
(
reset,
init_bram,
idle,
enq_begin,
deq_begin,
deqall_begin,
extra1,
extra2,
enq_adjust_queue,
enq_add_to_empty_queue,
enq_add_to_nonempty_queue,
transaction_complete,
extra3,
extra4,
enq_add_link,
extra5,
extra6,
deq_examine_length,
extra7,
extra8,
deq_remove_only,
extra9,
extra10,
deq_remove_general,
extra11,
extra12,
deq_send_owner,
extra13,
extra14,
deqall_examine_length,
extra15,
extra16,
extra17,
extra18,
deqall_remove_loop,
extra19,
extra20,
deqall_done,
return_to_idle
);
signal current_state,next_state: STATE_MACHINE_TYPE :=reset;
-- ****************************************************
-- Type definitions for FSM signals
-- ****************************************************
signal addr_counter, addr_counter_next : std_logic_vector(0 to G_ADDR_WIDTH - 1);
signal arg_cvar, arg_cvar_next : std_logic_vector(0 to G_TID_WIDTH - 1);
signal arg_tid, arg_tid_next : std_logic_vector(0 to G_TID_WIDTH - 1);
signal entry, entry_next : std_logic_vector(0 to G_TID_WIDTH - 1);
signal done, done_next : std_logic;
-- **************************
-- BRAM Signals for table
-- **************************
signal table_addr0 : std_logic_vector(0 to (G_ADDR_WIDTH - 1));
signal table_dIN0 : std_logic_vector(0 to (G_TID_WIDTH - 1));
signal table_dOUT0 : std_logic_vector(0 to (G_TID_WIDTH - 1));
signal table_rENA0 : std_logic;
signal table_wENA0 : std_logic;
signal table_addr1 : std_logic_vector(0 to (G_ADDR_WIDTH - 1));
signal table_dIN1 : std_logic_vector(0 to (G_TID_WIDTH - 1));
signal table_dOUT1 : std_logic_vector(0 to (G_TID_WIDTH - 1));
signal table_rENA1 : std_logic;
signal table_wENA1 : std_logic;
-- ****************************************************
-- User-defined VHDL Section
-- ****************************************************
constant OPCODE_ENQUEUE : std_logic_vector(0 to G_OP_WIDTH-1) := conv_std_logic_vector(2, G_OP_WIDTH); -- Opcode for "wait" enqueue
constant OPCODE_DEQUEUE : std_logic_vector(0 to G_OP_WIDTH-1) := conv_std_logic_vector(1, G_OP_WIDTH); -- Opcode for "signal" dequeue
constant OPCODE_DEQUEUE_ALL : std_logic_vector(0 to G_OP_WIDTH-1) := conv_std_logic_vector(3, G_OP_WIDTH); -- Opcode for "broadcast" dequeue
-- Helper Functions
pure function lengthEntry(cvar : std_logic_vector(0 to G_TID_WIDTH-1)) return std_logic_vector is
variable header : std_logic_vector(0 to G_ADDR_WIDTH - G_TID_WIDTH - 1);
begin
header := conv_std_logic_vector(0,G_ADDR_WIDTH - G_TID_WIDTH);
return header & cvar;
end function lengthEntry;
pure function linkEntry(tid : std_logic_vector(0 to G_TID_WIDTH-1)) return std_logic_vector is
variable header : std_logic_vector(0 to G_ADDR_WIDTH - G_TID_WIDTH - 1);
begin
header := conv_std_logic_vector(1,G_ADDR_WIDTH - G_TID_WIDTH);
return header & tid;
end function linkEntry;
pure function lastReqEntry(cvar : std_logic_vector(0 to G_TID_WIDTH-1)) return std_logic_vector is
variable header : std_logic_vector(0 to G_ADDR_WIDTH - G_TID_WIDTH - 1);
begin
header := conv_std_logic_vector(2,G_ADDR_WIDTH - G_TID_WIDTH);
return header & cvar;
end function lastReqEntry;
pure function ownerEntry(cvar : std_logic_vector(0 to G_TID_WIDTH-1)) return std_logic_vector is
variable header : std_logic_vector(0 to G_ADDR_WIDTH - G_TID_WIDTH - 1);
begin
header := conv_std_logic_vector(3,G_ADDR_WIDTH - G_TID_WIDTH);
return header & cvar;
end function ownerEntry;
pure function getLength(entry : std_logic_vector(0 to G_TID_WIDTH-1)) return std_logic_vector is
begin
return entry;
end function getLength;
-- Architecture Section
begin
-- ************************
-- Permanent Connections
-- ************************
ack <= done;
-- ************************
-- BRAM implementations
-- ************************
table_BRAM : infer_bram
generic map (
ADDRESS_BITS => G_ADDR_WIDTH,
DATA_BITS => G_TID_WIDTH
)
port map (
CLKA => clock_sig,
ENA => table_rENA0,
WEA => table_wENA0,
ADDRA => table_addr0,
DIA => table_dIN0,
DOA => table_dOUT0,
CLKB => clock_sig,
ENB => table_rENA1,
WEB => table_wENA1,
ADDRB => table_addr1,
DIB => table_dIN1,
DOB => table_dOUT1
);
-- ****************************************************
-- Process to handle the synchronous portion of an FSM
-- ****************************************************
FSM_SYNC_PROCESS : process(
addr_counter_next,
arg_cvar_next,
arg_tid_next,
entry_next,
done_next,
next_state,
clock_sig, reset_sig) is
begin
if (clock_sig'event and clock_sig = '1') then
if (reset_sig = '1') then
-- Reset all FSM signals, and enter the initial state
addr_counter <= (others => '0');
arg_cvar <= (others => '0');
arg_tid <= (others => '0');
entry <= (others => '0');
done <= '0';
current_state <= reset;
else
-- Transition to next state
addr_counter <= addr_counter_next;
arg_cvar <= arg_cvar_next;
arg_tid <= arg_tid_next;
entry <= entry_next;
done <= done_next;
current_state <= next_state;
end if;
end if;
end process FSM_SYNC_PROCESS;
-- ************************************************************************
-- Process to handle the asynchronous (combinational) portion of an FSM
-- ************************************************************************
FSM_COMB_PROCESS : process(
table_dOUT0, table_dOUT1,
msg_chan_channelDataOut, msg_chan_full, msg_chan_exists,
cmd,
opcode,
cvar,
tid,
addr_counter,
arg_cvar,
arg_tid,
entry,
done,
current_state) is
begin
-- Default signal assignments
addr_counter_next <= addr_counter;
arg_cvar_next <= arg_cvar;
arg_tid_next <= arg_tid;
entry_next <= entry;
done_next <= done;
table_addr0 <= (others => '0');
table_dIN0 <= (others => '0');
table_rENA0 <= '0';
table_wENA0 <= '0';
table_addr1 <= (others => '0');
table_dIN1 <= (others => '0');
table_rENA1 <= '0';
table_wENA1 <= '0';
msg_chan_channelDataIn <= (others => '0');
msg_chan_channelRead <= '0';
msg_chan_channelWrite <= '0';
next_state <= current_state;
-- FSM logic
case (current_state) is
when deq_begin =>
table_addr0 <= lengthEntry(arg_cvar);
table_rENA0 <= '1';
next_state <= extra5;
when deq_examine_length =>
if ( getLength(entry) = 0 ) then
done_next <= '1';
next_state <= transaction_complete;
elsif ( getLength(entry) = 1 ) then
table_addr1 <= ownerEntry(arg_cvar);
table_rENA1 <= '1';
next_state <= extra7;
else
table_addr1 <= ownerEntry(arg_cvar);
table_rENA1 <= '1';
next_state <= extra9;
end if;
when deq_remove_general =>
table_addr1 <= linkEntry(entry);
table_rENA1 <= '1';
next_state <= extra11;
when deq_remove_only =>
if msg_chan_full /= '0' then
next_state <= deq_remove_only;
elsif msg_chan_full = '0' then
done_next <= '1';
msg_chan_channelDataIn <= entry;
msg_chan_channelWrite <= '1';
next_state <= transaction_complete;
end if;
when deq_send_owner =>
if msg_chan_full /= '0' then
next_state <= deq_send_owner;
elsif msg_chan_full = '0' then
done_next <= '1';
msg_chan_channelDataIn <= entry;
msg_chan_channelWrite <= '1';
next_state <= transaction_complete;
end if;
when deqall_begin =>
table_addr0 <= lengthEntry(arg_cvar);
table_rENA0 <= '1';
next_state <= extra13;
when deqall_done =>
done_next <= '1';
next_state <= transaction_complete;
when deqall_examine_length =>
if ( getLength(entry) = 0 ) then
done_next <= '1';
next_state <= transaction_complete;
elsif ( getLength(entry) = 1 ) then
table_addr1 <= ownerEntry(arg_cvar);
table_rENA1 <= '1';
next_state <= extra15;
else
table_addr1 <= ownerEntry(arg_cvar);
table_rENA1 <= '1';
next_state <= extra17;
end if;
when deqall_remove_loop =>
if ( arg_tid > 0 ) then
table_addr0 <= linkEntry(entry);
table_rENA0 <= '1';
next_state <= extra19;
else
next_state <= deqall_done;
end if;
when enq_add_link =>
done_next <= '1';
table_addr0 <= lastReqEntry(arg_cvar);
table_dIN0 <= arg_tid;
table_wENA0 <= '1';
table_rENA0 <= '1';
table_addr1 <= linkEntry(entry);
table_dIN1 <= arg_tid;
table_wENA1 <= '1';
table_rENA1 <= '1';
next_state <= transaction_complete;
when enq_add_to_empty_queue =>
done_next <= '1';
table_addr0 <= ownerEntry(arg_cvar);
table_dIN0 <= arg_tid;
table_wENA0 <= '1';
table_rENA0 <= '1';
table_addr1 <= lastReqEntry(arg_cvar);
table_dIN1 <= arg_tid;
table_wENA1 <= '1';
table_rENA1 <= '1';
next_state <= transaction_complete;
when enq_add_to_nonempty_queue =>
table_addr0 <= lastReqEntry(arg_cvar);
table_rENA0 <= '1';
next_state <= extra3;
when enq_adjust_queue =>
if ( getLength(entry) = 1 ) then
table_addr0 <= lengthEntry(arg_cvar);
table_dIN0 <= entry;
table_wENA0 <= '1';
table_rENA0 <= '1';
next_state <= enq_add_to_empty_queue;
else
table_addr0 <= lengthEntry(arg_cvar);
table_dIN0 <= entry;
table_wENA0 <= '1';
table_rENA0 <= '1';
next_state <= enq_add_to_nonempty_queue;
end if;
when enq_begin =>
table_addr0 <= lengthEntry(arg_cvar);
table_rENA0 <= '1';
next_state <= extra1;
when extra1 =>
next_state <= extra2;
when extra10 =>
entry_next <= table_dOUT1;
table_addr0 <= lengthEntry(arg_cvar);
table_dIN0 <= entry - 1;
table_wENA0 <= '1';
table_rENA0 <= '1';
next_state <= deq_remove_general;
when extra11 =>
next_state <= extra12;
when extra12 =>
table_addr0 <= ownerEntry(arg_cvar);
table_dIN0 <= table_dOUT1;
table_wENA0 <= '1';
table_rENA0 <= '1';
next_state <= deq_send_owner;
when extra13 =>
next_state <= extra14;
when extra14 =>
entry_next <= table_dOUT0;
next_state <= deqall_examine_length;
when extra15 =>
next_state <= extra16;
when extra16 =>
entry_next <= table_dOUT1;
table_addr0 <= lengthEntry(arg_cvar);
table_dIN0 <= (others => '0');
table_wENA0 <= '1';
table_rENA0 <= '1';
next_state <= deq_remove_only;
when extra17 =>
next_state <= extra18;
when extra18 =>
entry_next <= table_dOUT1;
arg_tid_next <= getLength(entry);
table_addr0 <= lengthEntry(arg_cvar);
table_dIN0 <= (others => '0');
table_wENA0 <= '1';
table_rENA0 <= '1';
next_state <= deqall_remove_loop;
when extra19 =>
next_state <= extra20;
when extra2 =>
entry_next <= table_dOUT0 + 1;
next_state <= enq_adjust_queue;
when extra20 =>
if msg_chan_full /= '0' then
next_state <= extra20;
elsif msg_chan_full = '0' then
entry_next <= table_dOUT0;
arg_tid_next <= arg_tid - 1;
msg_chan_channelDataIn <= entry;
msg_chan_channelWrite <= '1';
next_state <= deqall_remove_loop;
end if;
when extra3 =>
next_state <= extra4;
when extra4 =>
entry_next <= table_dOUT0;
next_state <= enq_add_link;
when extra5 =>
next_state <= extra6;
when extra6 =>
entry_next <= table_dOUT0;
next_state <= deq_examine_length;
when extra7 =>
next_state <= extra8;
when extra8 =>
entry_next <= table_dOUT1;
table_addr0 <= lengthEntry(arg_cvar);
table_dIN0 <= (others => '0');
table_wENA0 <= '1';
table_rENA0 <= '1';
next_state <= deq_remove_only;
when extra9 =>
next_state <= extra10;
when idle =>
if ( cmd = '1' and opcode = OPCODE_ENQUEUE ) then
arg_cvar_next <= cvar;
arg_tid_next <= tid;
next_state <= enq_begin;
elsif ( cmd = '1' and opcode = OPCODE_DEQUEUE ) then
arg_cvar_next <= cvar;
next_state <= deq_begin;
elsif ( cmd = '1' and opcode = OPCODE_DEQUEUE_ALL ) then
arg_cvar_next <= cvar;
next_state <= deqall_begin;
else
done_next <= '0';
next_state <= idle;
end if;
when init_bram =>
if ( addr_counter > 0 ) then
addr_counter_next <= addr_counter - 1;
table_addr0 <= addr_counter;
table_dIN0 <= (others => '0');
table_wENA0 <= '1';
table_rENA0 <= '1';
next_state <= init_bram;
else
done_next <= '1';
next_state <= idle;
end if;
when reset =>
table_addr0 <= (others => '0');
table_dIN0 <= (others => '0');
table_wENA0 <= '1';
table_rENA0 <= '1';
addr_counter_next <= (others => '1');
next_state <= init_bram;
when return_to_idle =>
if ( cmd = '0' ) then
next_state <= idle;
else
next_state <= return_to_idle;
end if;
when transaction_complete =>
done_next <= '0';
next_state <= return_to_idle;
when others =>
next_state <= reset;
end case;
end process FSM_COMB_PROCESS;
end architecture IMPLEMENTATION;
-- $$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$
-- $$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$
-- ************************************************
-- Entity used for implementing the inferred BRAMs
-- ************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_misc.all;
use IEEE.numeric_std.all;
-- *************************************************************************
-- Entity declaration
-- *************************************************************************
entity infer_bram is
generic (
ADDRESS_BITS : integer := 9;
DATA_BITS : integer := 32
);
port (
CLKA : in std_logic;
ENA : in std_logic;
WEA : in std_logic;
ADDRA : in std_logic_vector(0 to (ADDRESS_BITS - 1));
DIA : in std_logic_vector(0 to (DATA_BITS - 1));
DOA : out std_logic_vector(0 to (DATA_BITS - 1));
CLKB : in std_logic;
ENB : in std_logic;
WEB : in std_logic;
ADDRB : in std_logic_vector(0 to (ADDRESS_BITS - 1));
DIB : in std_logic_vector(0 to (DATA_BITS - 1));
DOB : out std_logic_vector(0 to (DATA_BITS - 1))
);
end entity infer_bram;
-- *************************************************************************
-- Architecture declaration
-- *************************************************************************
architecture implementation of infer_bram is
-- Constant declarations
constant BRAM_SIZE : integer := 2 **ADDRESS_BITS; -- # of entries in the inferred BRAM
-- BRAM data storage (array)
type bram_storage is array( 0 to BRAM_SIZE - 1 ) of std_logic_vector( 0 to DATA_BITS - 1 );
shared variable BRAM_DATA : bram_storage;
-- attribute ram_style : string;
-- attribute ram_style of BRAM_DATA : signal is "block";
begin
-- *************************************************************************
-- Process: BRAM_CONTROLLER_A
-- Purpose: Controller for Port A of inferred dual-port BRAM, BRAM_DATA
-- *************************************************************************
BRAM_CONTROLLER_A : process(CLKA) is
begin
if( CLKA'event and CLKA = '1' ) then
if( ENA = '1' ) then
if( WEA = '1' ) then
BRAM_DATA( conv_integer(ADDRA) ) := DIA;
end if;
DOA <= BRAM_DATA( conv_integer(ADDRA) );
end if;
end if;
end process BRAM_CONTROLLER_A;
-- *************************************************************************
-- Process: BRAM_CONTROLLER_B
-- Purpose: Controller for Port B of inferred dual-port BRAM, BRAM_DATA
-- *************************************************************************
BRAM_CONTROLLER_B : process(CLKB) is
begin
if( CLKB'event and CLKB = '1' ) then
if( ENB = '1' ) then
if( WEB = '1' ) then
BRAM_DATA( conv_integer(ADDRB) ) := DIB;
end if;
DOB <= BRAM_DATA( conv_integer(ADDRB) );
end if;
end if;
end process BRAM_CONTROLLER_B;
end architecture implementation;
|
bsd-3-clause
|
masson2013/heterogeneous_hthreads
|
src/platforms/xilinx/pr_6smp/design/pcores/plb_hthread_reset_core_v1_00_a/hdl/vhdl/plb_hthread_reset_core.vhd
|
9
|
24727
|
------------------------------------------------------------------------------
-- plb_hthread_reset_core.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: plb_hthread_reset_core.vhd
-- Version: 1.00.a
-- Description: Top level design, instantiates library components and user logic.
-- Date: Wed Sep 24 16:19:15 2008 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
use proc_common_v3_00_a.soft_reset;
library plbv46_slave_single_v1_01_a;
use plbv46_slave_single_v1_01_a.plbv46_slave_single;
library plb_hthread_reset_core_v1_00_a;
use plb_hthread_reset_core_v1_00_a.user_logic;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_BASEADDR -- PLBv46 slave: base address
-- C_HIGHADDR -- PLBv46 slave: high address
-- C_SPLB_AWIDTH -- PLBv46 slave: address bus width
-- C_SPLB_DWIDTH -- PLBv46 slave: data bus width
-- C_SPLB_NUM_MASTERS -- PLBv46 slave: Number of masters
-- C_SPLB_MID_WIDTH -- PLBv46 slave: master ID bus width
-- C_SPLB_NATIVE_DWIDTH -- PLBv46 slave: internal native data bus width
-- C_SPLB_P2P -- PLBv46 slave: point to point interconnect scheme
-- C_SPLB_SUPPORT_BURSTS -- PLBv46 slave: support bursts
-- C_SPLB_SMALLEST_MASTER -- PLBv46 slave: width of the smallest master
-- C_SPLB_CLK_PERIOD_PS -- PLBv46 slave: bus clock in picoseconds
-- C_INCLUDE_DPHASE_TIMER -- PLBv46 slave: Data Phase Timer configuration; 0 = exclude timer, 1 = include timer
-- C_FAMILY -- Xilinx FPGA family
--
-- Definition of Ports:
-- SPLB_Clk -- PLB main bus clock
-- SPLB_Rst -- PLB main bus reset
-- PLB_ABus -- PLB address bus
-- PLB_UABus -- PLB upper address bus
-- PLB_PAValid -- PLB primary address valid indicator
-- PLB_SAValid -- PLB secondary address valid indicator
-- PLB_rdPrim -- PLB secondary to primary read request indicator
-- PLB_wrPrim -- PLB secondary to primary write request indicator
-- PLB_masterID -- PLB current master identifier
-- PLB_abort -- PLB abort request indicator
-- PLB_busLock -- PLB bus lock
-- PLB_RNW -- PLB read/not write
-- PLB_BE -- PLB byte enables
-- PLB_MSize -- PLB master data bus size
-- PLB_size -- PLB transfer size
-- PLB_type -- PLB transfer type
-- PLB_lockErr -- PLB lock error indicator
-- PLB_wrDBus -- PLB write data bus
-- PLB_wrBurst -- PLB burst write transfer indicator
-- PLB_rdBurst -- PLB burst read transfer indicator
-- PLB_wrPendReq -- PLB write pending bus request indicator
-- PLB_rdPendReq -- PLB read pending bus request indicator
-- PLB_wrPendPri -- PLB write pending request priority
-- PLB_rdPendPri -- PLB read pending request priority
-- PLB_reqPri -- PLB current request priority
-- PLB_TAttribute -- PLB transfer attribute
-- Sl_addrAck -- Slave address acknowledge
-- Sl_SSize -- Slave data bus size
-- Sl_wait -- Slave wait indicator
-- Sl_rearbitrate -- Slave re-arbitrate bus indicator
-- Sl_wrDAck -- Slave write data acknowledge
-- Sl_wrComp -- Slave write transfer complete indicator
-- Sl_wrBTerm -- Slave terminate write burst transfer
-- Sl_rdDBus -- Slave read data bus
-- Sl_rdWdAddr -- Slave read word address
-- Sl_rdDAck -- Slave read data acknowledge
-- Sl_rdComp -- Slave read transfer complete indicator
-- Sl_rdBTerm -- Slave terminate read burst transfer
-- Sl_MBusy -- Slave busy indicator
-- Sl_MWrErr -- Slave write error indicator
-- Sl_MRdErr -- Slave read error indicator
-- Sl_MIRQ -- Slave interrupt indicator
------------------------------------------------------------------------------
entity plb_hthread_reset_core is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_SPLB_AWIDTH : integer := 32;
C_SPLB_DWIDTH : integer := 128;
C_SPLB_NUM_MASTERS : integer := 8;
C_SPLB_MID_WIDTH : integer := 3;
C_SPLB_NATIVE_DWIDTH : integer := 32;
C_SPLB_P2P : integer := 0;
C_SPLB_SUPPORT_BURSTS : integer := 0;
C_SPLB_SMALLEST_MASTER : integer := 32;
C_SPLB_CLK_PERIOD_PS : integer := 10000;
C_INCLUDE_DPHASE_TIMER : integer := 0;
C_FAMILY : string := "virtex5"
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
reset_port0 : out std_logic;
reset_response_port0 : in std_logic;
reset_port1 : out std_logic;
reset_response_port1 : in std_logic;
reset_port2 : out std_logic;
reset_response_port2 : in std_logic;
reset_port3 : out std_logic;
reset_response_port3 : in std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to C_SPLB_MID_WIDTH-1);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to C_SPLB_DWIDTH/8-1);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to C_SPLB_DWIDTH-1);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to C_SPLB_DWIDTH-1);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MWrErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MRdErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MIRQ : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1)
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of SPLB_Clk : signal is "CLK";
attribute SIGIS of SPLB_Rst : signal is "RST";
end entity plb_hthread_reset_core;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of plb_hthread_reset_core is
------------------------------------------
-- Array of base/high address pairs for each address range
------------------------------------------
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR or X"00000000";
constant USER_SLV_HIGHADDR : std_logic_vector := C_BASEADDR or X"000000FF";
constant RST_BASEADDR : std_logic_vector := C_BASEADDR or X"00000100";
constant RST_HIGHADDR : std_logic_vector := C_BASEADDR or X"000001FF";
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
ZERO_ADDR_PAD & USER_SLV_HIGHADDR, -- user logic slave space high address
ZERO_ADDR_PAD & RST_BASEADDR, -- soft reset space base address
ZERO_ADDR_PAD & RST_HIGHADDR -- soft reset space high address
);
------------------------------------------
-- Array of desired number of chip enables for each address range
------------------------------------------
constant USER_SLV_NUM_REG : integer := 4;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant RST_NUM_CE : integer := 1;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => pad_power2(USER_SLV_NUM_REG), -- number of ce for user logic slave space
1 => RST_NUM_CE -- number of ce for soft reset space
);
------------------------------------------
-- Ratio of bus clock to core clock (for use in dual clock systems)
-- 1 = ratio is 1:1
-- 2 = ratio is 2:1
------------------------------------------
constant IPIF_BUS2CORE_CLK_RATIO : integer := 1;
------------------------------------------
-- Width of the slave data bus (32 only)
------------------------------------------
constant USER_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
constant IPIF_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
------------------------------------------
-- Width of triggered reset in bus clocks
------------------------------------------
constant RESET_WIDTH : integer := 4;
------------------------------------------
-- Index for CS/CE
------------------------------------------
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant RST_CS_INDEX : integer := 1;
constant RST_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, RST_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations
------------------------------------------
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Reset : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(0 to C_SPLB_AWIDTH-1);
signal ipif_Bus2IP_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(0 to IPIF_SLV_DWIDTH/8-1);
signal ipif_Bus2IP_CS : std_logic_vector(0 to ((IPIF_ARD_ADDR_RANGE_ARRAY'length)/2)-1);
signal ipif_Bus2IP_RdCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
signal ipif_Bus2IP_WrCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
signal rst_Bus2IP_Reset : std_logic;
signal rst_IP2Bus_WrAck : std_logic;
signal rst_IP2Bus_Error : std_logic;
signal user_Bus2IP_RdCE : std_logic_vector(0 to USER_NUM_REG-1);
signal user_Bus2IP_WrCE : std_logic_vector(0 to USER_NUM_REG-1);
signal user_IP2Bus_Data : std_logic_vector(0 to USER_SLV_DWIDTH-1);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
begin
------------------------------------------
-- instantiate plbv46_slave_single
------------------------------------------
PLBV46_SLAVE_SINGLE_I : entity plbv46_slave_single_v1_01_a.plbv46_slave_single
generic map
(
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_SPLB_P2P => C_SPLB_P2P,
C_BUS2CORE_CLK_RATIO => IPIF_BUS2CORE_CLK_RATIO,
C_SPLB_MID_WIDTH => C_SPLB_MID_WIDTH,
C_SPLB_NUM_MASTERS => C_SPLB_NUM_MASTERS,
C_SPLB_AWIDTH => C_SPLB_AWIDTH,
C_SPLB_DWIDTH => C_SPLB_DWIDTH,
C_SIPIF_DWIDTH => IPIF_SLV_DWIDTH,
C_INCLUDE_DPHASE_TIMER => C_INCLUDE_DPHASE_TIMER,
C_FAMILY => C_FAMILY
)
port map
(
SPLB_Clk => SPLB_Clk,
SPLB_Rst => SPLB_Rst,
PLB_ABus => PLB_ABus,
PLB_UABus => PLB_UABus,
PLB_PAValid => PLB_PAValid,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_masterID => PLB_masterID,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_MSize => PLB_MSize,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_lockErr => PLB_lockErr,
PLB_wrDBus => PLB_wrDBus,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendPri => PLB_rdPendPri,
PLB_reqPri => PLB_reqPri,
PLB_TAttribute => PLB_TAttribute,
Sl_addrAck => Sl_addrAck,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MBusy => Sl_MBusy,
Sl_MWrErr => Sl_MWrErr,
Sl_MRdErr => Sl_MRdErr,
Sl_MIRQ => Sl_MIRQ,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => ipif_Bus2IP_Reset,
IP2Bus_Data => ipif_IP2Bus_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE
);
------------------------------------------
-- instantiate soft_reset
------------------------------------------
SOFT_RESET_I : entity proc_common_v3_00_a.soft_reset
generic map
(
C_SIPIF_DWIDTH => IPIF_SLV_DWIDTH,
C_RESET_WIDTH => RESET_WIDTH
)
port map
(
Bus2IP_Reset => ipif_Bus2IP_Reset,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_WrCE => ipif_Bus2IP_WrCE(RST_CE_INDEX),
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Reset2IP_Reset => rst_Bus2IP_Reset,
Reset2Bus_WrAck => rst_IP2Bus_WrAck,
Reset2Bus_Error => rst_IP2Bus_Error,
Reset2Bus_ToutSup => open
);
------------------------------------------
-- instantiate User Logic
------------------------------------------
USER_LOGIC_I : entity plb_hthread_reset_core_v1_00_a.user_logic
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
--USER generics mapped here
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_SLV_DWIDTH => USER_SLV_DWIDTH,
C_NUM_REG => USER_NUM_REG
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
--USER ports mapped here
reset_port0 => reset_port0,
reset_response_port0 => reset_response_port0,
reset_port1 => reset_port1,
reset_response_port1 => reset_response_port1,
reset_port2 => reset_port2,
reset_response_port2 => reset_response_port2,
reset_port3 => reset_port3,
reset_response_port3 => reset_response_port3,
-- MAP USER PORTS ABOVE THIS LINE ------------------
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => rst_Bus2IP_Reset,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error
);
------------------------------------------
-- connect internal signals
------------------------------------------
IP2BUS_DATA_MUX_PROC : process( ipif_Bus2IP_CS, user_IP2Bus_Data ) is
begin
case ipif_Bus2IP_CS is
when "10" => ipif_IP2Bus_Data <= user_IP2Bus_Data;
when "01" => ipif_IP2Bus_Data <= (others => '0');
when others => ipif_IP2Bus_Data <= (others => '0');
end case;
end process IP2BUS_DATA_MUX_PROC;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck or rst_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error or rst_IP2Bus_Error;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
end IMP;
|
bsd-3-clause
|
masson2013/heterogeneous_hthreads
|
src/platforms/xilinx/ml605_pr_smp1_14_7/design/pcores/plb_hthread_reset_core_v1_00_a/hdl/vhdl/plb_hthread_reset_core.vhd
|
9
|
24727
|
------------------------------------------------------------------------------
-- plb_hthread_reset_core.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: plb_hthread_reset_core.vhd
-- Version: 1.00.a
-- Description: Top level design, instantiates library components and user logic.
-- Date: Wed Sep 24 16:19:15 2008 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
use proc_common_v3_00_a.soft_reset;
library plbv46_slave_single_v1_01_a;
use plbv46_slave_single_v1_01_a.plbv46_slave_single;
library plb_hthread_reset_core_v1_00_a;
use plb_hthread_reset_core_v1_00_a.user_logic;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_BASEADDR -- PLBv46 slave: base address
-- C_HIGHADDR -- PLBv46 slave: high address
-- C_SPLB_AWIDTH -- PLBv46 slave: address bus width
-- C_SPLB_DWIDTH -- PLBv46 slave: data bus width
-- C_SPLB_NUM_MASTERS -- PLBv46 slave: Number of masters
-- C_SPLB_MID_WIDTH -- PLBv46 slave: master ID bus width
-- C_SPLB_NATIVE_DWIDTH -- PLBv46 slave: internal native data bus width
-- C_SPLB_P2P -- PLBv46 slave: point to point interconnect scheme
-- C_SPLB_SUPPORT_BURSTS -- PLBv46 slave: support bursts
-- C_SPLB_SMALLEST_MASTER -- PLBv46 slave: width of the smallest master
-- C_SPLB_CLK_PERIOD_PS -- PLBv46 slave: bus clock in picoseconds
-- C_INCLUDE_DPHASE_TIMER -- PLBv46 slave: Data Phase Timer configuration; 0 = exclude timer, 1 = include timer
-- C_FAMILY -- Xilinx FPGA family
--
-- Definition of Ports:
-- SPLB_Clk -- PLB main bus clock
-- SPLB_Rst -- PLB main bus reset
-- PLB_ABus -- PLB address bus
-- PLB_UABus -- PLB upper address bus
-- PLB_PAValid -- PLB primary address valid indicator
-- PLB_SAValid -- PLB secondary address valid indicator
-- PLB_rdPrim -- PLB secondary to primary read request indicator
-- PLB_wrPrim -- PLB secondary to primary write request indicator
-- PLB_masterID -- PLB current master identifier
-- PLB_abort -- PLB abort request indicator
-- PLB_busLock -- PLB bus lock
-- PLB_RNW -- PLB read/not write
-- PLB_BE -- PLB byte enables
-- PLB_MSize -- PLB master data bus size
-- PLB_size -- PLB transfer size
-- PLB_type -- PLB transfer type
-- PLB_lockErr -- PLB lock error indicator
-- PLB_wrDBus -- PLB write data bus
-- PLB_wrBurst -- PLB burst write transfer indicator
-- PLB_rdBurst -- PLB burst read transfer indicator
-- PLB_wrPendReq -- PLB write pending bus request indicator
-- PLB_rdPendReq -- PLB read pending bus request indicator
-- PLB_wrPendPri -- PLB write pending request priority
-- PLB_rdPendPri -- PLB read pending request priority
-- PLB_reqPri -- PLB current request priority
-- PLB_TAttribute -- PLB transfer attribute
-- Sl_addrAck -- Slave address acknowledge
-- Sl_SSize -- Slave data bus size
-- Sl_wait -- Slave wait indicator
-- Sl_rearbitrate -- Slave re-arbitrate bus indicator
-- Sl_wrDAck -- Slave write data acknowledge
-- Sl_wrComp -- Slave write transfer complete indicator
-- Sl_wrBTerm -- Slave terminate write burst transfer
-- Sl_rdDBus -- Slave read data bus
-- Sl_rdWdAddr -- Slave read word address
-- Sl_rdDAck -- Slave read data acknowledge
-- Sl_rdComp -- Slave read transfer complete indicator
-- Sl_rdBTerm -- Slave terminate read burst transfer
-- Sl_MBusy -- Slave busy indicator
-- Sl_MWrErr -- Slave write error indicator
-- Sl_MRdErr -- Slave read error indicator
-- Sl_MIRQ -- Slave interrupt indicator
------------------------------------------------------------------------------
entity plb_hthread_reset_core is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_SPLB_AWIDTH : integer := 32;
C_SPLB_DWIDTH : integer := 128;
C_SPLB_NUM_MASTERS : integer := 8;
C_SPLB_MID_WIDTH : integer := 3;
C_SPLB_NATIVE_DWIDTH : integer := 32;
C_SPLB_P2P : integer := 0;
C_SPLB_SUPPORT_BURSTS : integer := 0;
C_SPLB_SMALLEST_MASTER : integer := 32;
C_SPLB_CLK_PERIOD_PS : integer := 10000;
C_INCLUDE_DPHASE_TIMER : integer := 0;
C_FAMILY : string := "virtex5"
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
reset_port0 : out std_logic;
reset_response_port0 : in std_logic;
reset_port1 : out std_logic;
reset_response_port1 : in std_logic;
reset_port2 : out std_logic;
reset_response_port2 : in std_logic;
reset_port3 : out std_logic;
reset_response_port3 : in std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to C_SPLB_MID_WIDTH-1);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to C_SPLB_DWIDTH/8-1);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to C_SPLB_DWIDTH-1);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to C_SPLB_DWIDTH-1);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MWrErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MRdErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MIRQ : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1)
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of SPLB_Clk : signal is "CLK";
attribute SIGIS of SPLB_Rst : signal is "RST";
end entity plb_hthread_reset_core;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of plb_hthread_reset_core is
------------------------------------------
-- Array of base/high address pairs for each address range
------------------------------------------
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR or X"00000000";
constant USER_SLV_HIGHADDR : std_logic_vector := C_BASEADDR or X"000000FF";
constant RST_BASEADDR : std_logic_vector := C_BASEADDR or X"00000100";
constant RST_HIGHADDR : std_logic_vector := C_BASEADDR or X"000001FF";
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
ZERO_ADDR_PAD & USER_SLV_HIGHADDR, -- user logic slave space high address
ZERO_ADDR_PAD & RST_BASEADDR, -- soft reset space base address
ZERO_ADDR_PAD & RST_HIGHADDR -- soft reset space high address
);
------------------------------------------
-- Array of desired number of chip enables for each address range
------------------------------------------
constant USER_SLV_NUM_REG : integer := 4;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant RST_NUM_CE : integer := 1;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => pad_power2(USER_SLV_NUM_REG), -- number of ce for user logic slave space
1 => RST_NUM_CE -- number of ce for soft reset space
);
------------------------------------------
-- Ratio of bus clock to core clock (for use in dual clock systems)
-- 1 = ratio is 1:1
-- 2 = ratio is 2:1
------------------------------------------
constant IPIF_BUS2CORE_CLK_RATIO : integer := 1;
------------------------------------------
-- Width of the slave data bus (32 only)
------------------------------------------
constant USER_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
constant IPIF_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
------------------------------------------
-- Width of triggered reset in bus clocks
------------------------------------------
constant RESET_WIDTH : integer := 4;
------------------------------------------
-- Index for CS/CE
------------------------------------------
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant RST_CS_INDEX : integer := 1;
constant RST_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, RST_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations
------------------------------------------
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Reset : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(0 to C_SPLB_AWIDTH-1);
signal ipif_Bus2IP_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(0 to IPIF_SLV_DWIDTH/8-1);
signal ipif_Bus2IP_CS : std_logic_vector(0 to ((IPIF_ARD_ADDR_RANGE_ARRAY'length)/2)-1);
signal ipif_Bus2IP_RdCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
signal ipif_Bus2IP_WrCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
signal rst_Bus2IP_Reset : std_logic;
signal rst_IP2Bus_WrAck : std_logic;
signal rst_IP2Bus_Error : std_logic;
signal user_Bus2IP_RdCE : std_logic_vector(0 to USER_NUM_REG-1);
signal user_Bus2IP_WrCE : std_logic_vector(0 to USER_NUM_REG-1);
signal user_IP2Bus_Data : std_logic_vector(0 to USER_SLV_DWIDTH-1);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
begin
------------------------------------------
-- instantiate plbv46_slave_single
------------------------------------------
PLBV46_SLAVE_SINGLE_I : entity plbv46_slave_single_v1_01_a.plbv46_slave_single
generic map
(
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_SPLB_P2P => C_SPLB_P2P,
C_BUS2CORE_CLK_RATIO => IPIF_BUS2CORE_CLK_RATIO,
C_SPLB_MID_WIDTH => C_SPLB_MID_WIDTH,
C_SPLB_NUM_MASTERS => C_SPLB_NUM_MASTERS,
C_SPLB_AWIDTH => C_SPLB_AWIDTH,
C_SPLB_DWIDTH => C_SPLB_DWIDTH,
C_SIPIF_DWIDTH => IPIF_SLV_DWIDTH,
C_INCLUDE_DPHASE_TIMER => C_INCLUDE_DPHASE_TIMER,
C_FAMILY => C_FAMILY
)
port map
(
SPLB_Clk => SPLB_Clk,
SPLB_Rst => SPLB_Rst,
PLB_ABus => PLB_ABus,
PLB_UABus => PLB_UABus,
PLB_PAValid => PLB_PAValid,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_masterID => PLB_masterID,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_MSize => PLB_MSize,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_lockErr => PLB_lockErr,
PLB_wrDBus => PLB_wrDBus,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendPri => PLB_rdPendPri,
PLB_reqPri => PLB_reqPri,
PLB_TAttribute => PLB_TAttribute,
Sl_addrAck => Sl_addrAck,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MBusy => Sl_MBusy,
Sl_MWrErr => Sl_MWrErr,
Sl_MRdErr => Sl_MRdErr,
Sl_MIRQ => Sl_MIRQ,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => ipif_Bus2IP_Reset,
IP2Bus_Data => ipif_IP2Bus_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE
);
------------------------------------------
-- instantiate soft_reset
------------------------------------------
SOFT_RESET_I : entity proc_common_v3_00_a.soft_reset
generic map
(
C_SIPIF_DWIDTH => IPIF_SLV_DWIDTH,
C_RESET_WIDTH => RESET_WIDTH
)
port map
(
Bus2IP_Reset => ipif_Bus2IP_Reset,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_WrCE => ipif_Bus2IP_WrCE(RST_CE_INDEX),
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Reset2IP_Reset => rst_Bus2IP_Reset,
Reset2Bus_WrAck => rst_IP2Bus_WrAck,
Reset2Bus_Error => rst_IP2Bus_Error,
Reset2Bus_ToutSup => open
);
------------------------------------------
-- instantiate User Logic
------------------------------------------
USER_LOGIC_I : entity plb_hthread_reset_core_v1_00_a.user_logic
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
--USER generics mapped here
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_SLV_DWIDTH => USER_SLV_DWIDTH,
C_NUM_REG => USER_NUM_REG
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
--USER ports mapped here
reset_port0 => reset_port0,
reset_response_port0 => reset_response_port0,
reset_port1 => reset_port1,
reset_response_port1 => reset_response_port1,
reset_port2 => reset_port2,
reset_response_port2 => reset_response_port2,
reset_port3 => reset_port3,
reset_response_port3 => reset_response_port3,
-- MAP USER PORTS ABOVE THIS LINE ------------------
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => rst_Bus2IP_Reset,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error
);
------------------------------------------
-- connect internal signals
------------------------------------------
IP2BUS_DATA_MUX_PROC : process( ipif_Bus2IP_CS, user_IP2Bus_Data ) is
begin
case ipif_Bus2IP_CS is
when "10" => ipif_IP2Bus_Data <= user_IP2Bus_Data;
when "01" => ipif_IP2Bus_Data <= (others => '0');
when others => ipif_IP2Bus_Data <= (others => '0');
end case;
end process IP2BUS_DATA_MUX_PROC;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck or rst_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error or rst_IP2Bus_Error;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
end IMP;
|
bsd-3-clause
|
masson2013/heterogeneous_hthreads
|
src/platforms/xilinx/ml605_pr_smp1_14_7/design/pcores/plb_sync_manager_v1_00_a/hdl/vhdl/testbench.vhd
|
11
|
11805
|
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.common.all;
entity testbench is
end testbench;
architecture behavior of testbench is
-- Synch Manager Configuration Constants
constant SCHED_BADDR : std_logic_vector(0 to 31) := x"60000000";
constant SCHED_HADDR : std_logic_vector(0 to 31) := x"6FFFFFFF";
constant MUTEX_BADDR : std_logic_vector(0 to 31) := x"70000000";
constant MUTEX_HADDR : std_logic_vector(0 to 31) := x"7FFFFFFF";
constant SYNCH_THREADS : integer := 256;
constant SYNCH_MUTEXES : integer := 64;
-- Constants for the number of bits needed to represent certain data
constant MUTEX_BITS : integer := log2(SYNCH_MUTEXES);
constant THREAD_BITS : integer := log2(SYNCH_THREADS);
constant KIND_BITS : integer := 2;
constant COUNT_BITS : integer := 8;
constant COMMAND_BITS : integer := 3;
constant DATA_BITS : integer := 32;
--Inputs
signal OPB_Clk : std_logic := '0';
signal OPB_Rst : std_logic := '0';
signal OPB_RNW : std_logic := '0';
signal OPB_select : std_logic := '0';
signal OPB_seqAddr : std_logic := '0';
signal OPB_errAck : std_logic := '0';
signal OPB_MGrant : std_logic := '0';
signal OPB_retry : std_logic := '0';
signal OPB_timeout : std_logic := '0';
signal OPB_xferAck : std_logic := '0';
signal OPB_ABus : std_logic_vector(0 to 31) := (others=>'0');
signal OPB_BE : std_logic_vector(0 to 3) := (others=>'0');
signal OPB_DBus : std_logic_vector(0 to 31) := (others=>'0');
--Outputs
signal Sl_DBus : std_logic_vector(0 to 31);
signal Sl_errAck : std_logic;
signal Sl_retry : std_logic;
signal Sl_toutSup : std_logic;
signal Sl_xferAck : std_logic;
signal M_ABus : std_logic_vector(0 to 31);
signal M_BE : std_logic_vector(0 to 3);
signal M_busLock : std_logic;
signal M_request : std_logic;
signal M_RNW : std_logic;
signal M_select : std_logic;
signal M_seqAddr : std_logic;
-- Reset signals
signal system_reset : std_logic;
signal system_resetdone : std_logic;
begin
-- Instantiate the Unit Under Test (UUT)
synch : entity work.opb_synchmanager
generic map
(
C_NUM_THREADS => SYNCH_THREADS,
C_NUM_MUTEXES => SYNCH_MUTEXES,
C_SCHED_BADDR => SCHED_BADDR,
C_SCHED_HADDR => SCHED_HADDR,
C_BASEADDR => MUTEX_BADDR,
C_HIGHADDR => MUTEX_HADDR
)
port map
(
OPB_Clk => OPB_Clk,
OPB_Rst => OPB_Rst,
Sl_DBus => Sl_DBus,
Sl_errAck => Sl_errAck,
Sl_retry => Sl_retry,
Sl_toutSup => Sl_toutSup,
Sl_xferAck => Sl_xferAck,
OPB_ABus => OPB_ABus,
OPB_BE => OPB_BE,
OPB_DBus => OPB_DBus,
OPB_RNW => OPB_RNW,
OPB_select => OPB_select,
OPB_seqAddr => OPB_seqAddr,
M_ABus => M_ABus,
M_BE => M_BE,
M_busLock => M_busLock,
M_request => M_request,
M_RNW => M_RNW,
M_select => M_select,
M_seqAddr => M_seqAddr,
OPB_errAck => OPB_errAck,
OPB_MGrant => OPB_MGrant,
OPB_retry => OPB_retry,
OPB_timeout => OPB_timeout,
OPB_xferAck => OPB_xferAck,
system_reset => system_reset,
system_resetdone => system_resetdone
);
tb : process
procedure bus_trans( rnw : in std_logic;
abus : in std_logic_vector(0 to 31);
dbus : in std_logic_vector(0 to 31) ) is
begin
wait until OPB_Clk = '1';
OPB_ABus <= abus;
OPB_DBus <= dbus;
OPB_RNW <= rnw;
OPB_select <= '1';
OPB_BE <= (others => '1');
wait until Sl_xferAck = '1' and OPB_Clk = '1';
OPB_ABus <= (others => '0');
OPB_DBus <= (others => '0');
OPB_RNW <= '0';
OPB_select <= '0';
OPB_BE <= (others => '0');
wait until OPB_Clk = '1';
end procedure bus_trans;
procedure bus_reset is
begin
wait until OPB_Clk = '1';
OPB_Rst <= '1';
OPB_select <= '0';
OPB_seqAddr <= '0';
OPB_RNW <= '0';
OPB_BE <= (others => '0');
OPB_ABus <= (others => '0');
OPB_DBus <= (others => '0');
wait until OPB_Clk = '1';
OPB_Rst <= '0';
end procedure bus_reset;
procedure sys_reset is
begin
-- Issue a bus reset first
bus_reset;
-- Assert the system reset signal
system_reset <= '1';
-- Wait until the core is finished resetting
wait until system_resetdone = '1';
-- Deassert the system reset signal
system_reset <= '0';
end procedure sys_reset;
function synch_cmd( tid : in std_logic_vector(0 to THREAD_BITS-1);
mid : in std_logic_vector(0 to MUTEX_BITS-1);
cmd : in std_logic_vector(0 to COMMAND_BITS-1) )
return std_logic_vector is
variable addr : std_logic_vector(0 to 31);
begin
addr := MUTEX_BADDR;
addr(30-MUTEX_BITS to 29) := mid;
addr(30-MUTEX_BITS-THREAD_BITS to 29-MUTEX_BITS) := tid;
addr(30-MUTEX_BITS-THREAD_BITS-COMMAND_BITS to 29-MUTEX_BITS-THREAD_BITS) := cmd;
return addr;
end function synch_cmd;
procedure synchm_lock( tid : in std_logic_vector(0 to THREAD_BITS-1);
mid : in std_logic_vector(0 to MUTEX_BITS-1) ) is
begin
bus_trans('1',synch_cmd(tid,mid,SYNCH_LOCK),x"FFFFFFFF");
end procedure synchm_lock;
procedure synchm_unlock( tid : in std_logic_vector(0 to THREAD_BITS-1);
mid : in std_logic_vector(0 to MUTEX_BITS-1) ) is
begin
bus_trans('1',synch_cmd(tid,mid,SYNCH_UNLOCK),x"FFFFFFFF");
end procedure synchm_unlock;
procedure synchm_trylock( tid : in std_logic_vector(0 to THREAD_BITS-1);
mid : in std_logic_vector(0 to MUTEX_BITS-1) ) is
begin
bus_trans('1',synch_cmd(tid,mid,SYNCH_TRY),x"FFFFFFFF");
end procedure synchm_trylock;
procedure synchm_kind( mid : in std_logic_vector(0 to MUTEX_BITS-1) ) is
begin
bus_trans('1',synch_cmd(x"00",mid,SYNCH_KIND),x"FFFFFFFF");
end procedure synchm_kind;
procedure synchm_count( mid : in std_logic_vector(0 to MUTEX_BITS-1) ) is
begin
bus_trans('1',synch_cmd(x"00",mid,SYNCH_COUNT),x"FFFFFFFF");
end procedure synchm_count;
procedure synchm_owner( mid : in std_logic_vector(0 to MUTEX_BITS-1) ) is
begin
bus_trans('1',synch_cmd(x"00",mid,SYNCH_OWNER),x"FFFFFFFF");
end procedure synchm_owner;
procedure synchm_setkind( mid : in std_logic_vector(0 to MUTEX_BITS-1);
kind : in std_logic_vector(0 to KIND_BITS-1)) is
variable data : std_logic_vector(0 to DATA_BITS-1);
begin
data := (others => '0');
data(DATA_BITS-KIND_BITS to DATA_BITS-1) := kind;
bus_trans('0',synch_cmd(x"00",mid,SYNCH_KIND),data);
end procedure synchm_setkind;
begin
-- Wait 100 ns for global reset to finish
wait for 100 ns;
-- Send a bus reset command
sys_reset;
-- Setup the mutex kinds
synchm_setkind( "000000", SYNCH_FAST );
synchm_setkind( "000001", SYNCH_FAST );
synchm_setkind( "000010", SYNCH_ERROR );
synchm_setkind( "000011", SYNCH_RECURS );
-- Test standard locking and unlocking
synchm_lock( x"01", "000000" );
synchm_lock( x"02", "000000" );
synchm_trylock( x"03", "000000" );
synchm_lock( x"04", "000000" );
synchm_unlock( x"01", "000000" );
synchm_unlock( x"02", "000000" );
synchm_unlock( x"04", "000000" );
-- Test that fast mutex locking method works properly
synchm_lock( x"0A", "000001" );
synchm_lock( x"0A", "000001" );
synchm_lock( x"0A", "000001" );
synchm_lock( x"0A", "000001" );
-- Test that error checking mutex locking method works properly
synchm_lock( x"0B", "000010" );
synchm_lock( x"0B", "000010" );
synchm_lock( x"0B", "000010" );
synchm_lock( x"0B", "000010" );
-- Test that recursive mutex locking method works properly
synchm_lock( x"0C", "000011" );
synchm_lock( x"0C", "000011" );
synchm_lock( x"0C", "000011" );
synchm_lock( x"0C", "000011" );
-- Test that getting the owner works properly
synchm_owner( "000001" );
synchm_owner( "000010" );
synchm_owner( "000011" );
-- Test that getting the count works properly
synchm_count( "000011" );
-- Test that getting the kind works properly
synchm_kind( "000000" );
synchm_kind( "000001" );
synchm_kind( "000010" );
synchm_kind( "000011" );
-- Test that recursive mutex unlocking works
synchm_unlock( x"0C", "000011" );
synchm_unlock( x"0C", "000011" );
synchm_unlock( x"0C", "000011" );
synchm_unlock( x"0C", "000011" );
wait; -- will wait forever
end process;
clk : process
begin
OPB_Clk <= '0';
wait for 10 ns;
loop
OPB_Clk <= '1', '0' after 5 ns;
wait for 10 ns;
end loop;
end process;
end;
|
bsd-3-clause
|
masson2013/heterogeneous_hthreads
|
src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/opb_v20_v1_10_d/hdl/vhdl/pf_dly1_mux.vhd
|
3
|
9364
|
-------------------------------------------------------------------------------
-- $Id: pf_dly1_mux.vhd,v 1.1.2.1 2009/10/06 21:15:01 gburch Exp $
-------------------------------------------------------------------------------
-- pf_dly1_mux.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pf_dly1_mux.vhd
--
-- Description: Implements a multiplexer and register combo that allows
-- selection of a registered or non-registered version of
-- the input signal for output.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pf_dly1_mux.vhd
--
-------------------------------------------------------------------------------
-- Author: B.L. Tise
-- Revision: $Revision: 1.1.2.1 $
-- Date: $Date: 2009/10/06 21:15:01 $
--
-- History:
-- D. Thorpe 2001-08-30 First Version
-- - adapted from B Tise MicroBlaze counters
--
-- DET 2001-09-11
-- - Added the Rst input signal and connected it to the FDRE
-- reset input.
--
--
-- DET 4/2/2004 IPIF to v2_02_a
-- ~~~~~~
-- - Updated proc common library reference to v2_00_a
-- ^^^^^^
--
--
-- DET 4/12/2004 IPIF to V1_00_f
-- ~~~~~~
-- - Updated unisim library reference to unisim.vcomponents.all.
-- - Commented out Xilinx primitive component declarations
-- ^^^^^^
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-----------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library opb_v20_v1_10_d;
Use opb_v20_v1_10_d.inferred_lut4;
-- Xilinx primitive library
library unisim;
use unisim.vcomponents.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity pf_dly1_mux is
Generic (C_MUX_WIDTH : Integer := 12
);
port (
Clk : in std_logic;
Rst : In std_logic;
dly_sel1 : in std_logic;
dly_sel2 : in std_logic;
Inputs : in std_logic_vector(0 to C_MUX_WIDTH-1);
Y_out : out std_logic_vector(0 to C_MUX_WIDTH-1)
);
end pf_dly1_mux;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of pf_dly1_mux is
signal lut_out : std_logic_vector(0 to C_MUX_WIDTH-1);
signal reg_out : std_logic_vector(0 to C_MUX_WIDTH-1);
signal count_Result_Reg : std_logic;
attribute INIT : string;
begin -- VHDL_RTL
MAKE_DLY_MUX : for i in 0 to C_MUX_WIDTH-1 generate
--- xst wrk around I_SEL_LUT : LUT4
--- xst wrk around generic map(
--- xst wrk around -- synthesis translate_off
--- xst wrk around Xon => false,
--- xst wrk around -- synthesis translate_on
--- xst wrk around INIT => X"FE10"
--- xst wrk around )
--- xst wrk around port map (
--- xst wrk around O => lut_out(i),
--- xst wrk around I0 => dly_sel1,
--- xst wrk around I1 => dly_sel2,
--- xst wrk around I2 => Inputs(i),
--- xst wrk around I3 => reg_out(i)
--- xst wrk around );
I_SEL_LUT : entity opb_v20_v1_10_d.inferred_lut4
generic map(
INIT => X"FE10"
)
port map (
O => lut_out(i),
I0 => dly_sel1,
I1 => dly_sel2,
I2 => Inputs(i),
I3 => reg_out(i)
);
FDRE_I: FDRE
port map (
Q => reg_out(i),
C => Clk,
CE => '1',
D => Inputs(i),
R => Rst
);
End generate MAKE_DLY_MUX;
Y_out <= lut_out;
end implementation;
|
bsd-3-clause
|
masson2013/heterogeneous_hthreads
|
src/hardware/MyRepository/pcores/plb_fsmlang_special_pic_v1_00_a/hdl/vhdl/user_logic.vhd
|
2
|
34238
|
------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: user_logic.vhd
-- Version: 1.00.a
-- Description: User logic.
-- Date: Mon Apr 6 14:20:46 2009 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library fsl_v20_v2_11_a;
use fsl_v20_v2_11_a.all;
--library proc_common_v2_00_a;
--use proc_common_v2_00_a.proc_common_pkg.all;
--use proc_common_v2_00_a.srl_fifo_f;
-- DO NOT EDIT ABOVE THIS LINE --------------------
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_SLV_DWIDTH -- Slave interface data bus width
-- C_MST_AWIDTH -- Master interface address bus width
-- C_MST_DWIDTH -- Master interface data bus width
-- C_NUM_REG -- Number of software accessible registers
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Reset -- Bus to IP reset
-- Bus2IP_Addr -- Bus to IP address bus
-- Bus2IP_Data -- Bus to IP data bus
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- IP2Bus_Data -- IP to Bus data bus
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- IP2Bus_Error -- IP to Bus error response
-- IP2Bus_MstRd_Req -- IP to Bus master read request
-- IP2Bus_MstWr_Req -- IP to Bus master write request
-- IP2Bus_Mst_Addr -- IP to Bus master address bus
-- IP2Bus_Mst_BE -- IP to Bus master byte enables
-- IP2Bus_Mst_Lock -- IP to Bus master lock
-- IP2Bus_Mst_Reset -- IP to Bus master reset
-- Bus2IP_Mst_CmdAck -- Bus to IP master command acknowledgement
-- Bus2IP_Mst_Cmplt -- Bus to IP master transfer completion
-- Bus2IP_Mst_Error -- Bus to IP master error response
-- Bus2IP_Mst_Rearbitrate -- Bus to IP master re-arbitrate
-- Bus2IP_Mst_Cmd_Timeout -- Bus to IP master command timeout
-- Bus2IP_MstRd_d -- Bus to IP master read data bus
-- Bus2IP_MstRd_src_rdy_n -- Bus to IP master read source ready
-- IP2Bus_MstWr_d -- IP to Bus master write data bus
-- Bus2IP_MstWr_dst_rdy_n -- Bus to IP master write destination ready
------------------------------------------------------------------------------
entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
C_TM_BASE : std_logic_vector := x"11000000";
C_IID_WIDTH : integer := 3;
C_REG_SIZE : integer := 9;
C_CMD_WIDTH : integer := 4;
C_NUM_INTERRUPTS : integer := 8;
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_SLV_DWIDTH : integer := 32;
C_MST_AWIDTH : integer := 32;
C_MST_DWIDTH : integer := 32;
C_NUM_REG : integer := 5
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
Soft_Reset : in std_logic;
Reset_Done : out std_logic;
--interrupts_in : in std_logic_vector(0 to 2**C_IID_WIDTH-1);
interrupts_in : in std_logic_vector(0 to C_NUM_INTERRUPTS-1);
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Addr : in std_logic_vector(0 to 31);
Bus2IP_Data : in std_logic_vector(0 to C_SLV_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_SLV_DWIDTH/8-1);
Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_REG-1);
Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_REG-1);
IP2Bus_Data : out std_logic_vector(0 to C_SLV_DWIDTH-1);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic;
IP2Bus_MstRd_Req : out std_logic;
IP2Bus_MstWr_Req : out std_logic;
IP2Bus_Mst_Addr : out std_logic_vector(0 to C_MST_AWIDTH-1);
IP2Bus_Mst_BE : out std_logic_vector(0 to C_MST_DWIDTH/8-1);
IP2Bus_Mst_Lock : out std_logic;
IP2Bus_Mst_Reset : out std_logic;
Bus2IP_Mst_CmdAck : in std_logic;
Bus2IP_Mst_Cmplt : in std_logic;
Bus2IP_Mst_Error : in std_logic;
Bus2IP_Mst_Rearbitrate : in std_logic;
Bus2IP_Mst_Cmd_Timeout : in std_logic;
Bus2IP_MstRd_d : in std_logic_vector(0 to C_MST_DWIDTH-1);
Bus2IP_MstRd_src_rdy_n : in std_logic;
IP2Bus_MstWr_d : out std_logic_vector(0 to C_MST_DWIDTH-1);
Bus2IP_MstWr_dst_rdy_n : in std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
-- Added in by Xilinx even though XST doesn't even recognize these attributes
--attribute SIGIS : string;
--attribute SIGIS of Bus2IP_Clk : signal is "CLK";
--attribute SIGIS of Bus2IP_Reset : signal is "RST";
--attribute SIGIS of IP2Bus_Mst_Reset: signal is "RST";
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
--USER signal declarations added here, as needed for user logic
-- Define the memory map for each command register, Address[13 to 14]
-- This value is the offset from the base address assigned to this module
constant OPCODE_READ : std_logic_vector(0 to 4-1) := x"0";
constant OPCODE_WRITE : std_logic_vector(0 to 4-1) := x"1";
constant OPCODE_CLEAR : std_logic_vector(0 to 4-1) := x"2";
constant OPCODE_MANUAL_RESET : std_logic_vector(0 to 4-1) := x"3";
-- ACK signal
signal IP2Bus_Ack : std_logic;
-- CE concatenation signals
signal Bus2IP_RdCE_concat : std_logic;
signal Bus2IP_WrCE_concat : std_logic;
-- Bus Output Controller signals
signal bus_data_ready : std_logic;
signal bus_ack_ready : std_logic;
signal bus_data_out : std_logic_vector (0 to 31);
-- Reset Signals
-- FIXME: It would be nice to eliminate the default values here
signal inside_reset : std_logic := '0';
signal inside_reset_next : std_logic := '0';
-- Signals for each event type
signal OPWrite_Request : std_logic;
signal OPRead_Request : std_logic;
signal OPClear_Request : std_logic;
signal OPManualReset_Request : std_logic;
signal Error_Request : std_logic;
-- signal and type for MASTER FSM
type master_state_type is
(
idle, -- idle states
wait_trans_done, -- wait for bus transaction to complete
reset, -- reset states
reset_core,
reset_wait_4_ack,
opwrite_begin,
opwrite_wait_4_busy,
opwrite_finish,
opread_begin,
opread_wait_4_busy,
opread_finish,
manual_reset_begin,
manual_reset_wait,
manual_reset_finish,
opclear_begin,
opclear_wait_4_busy,
opclear_finish
);
signal current_state, next_state : master_state_type := idle;
--Core Inputs
signal msg_chan_channelDataOut : std_logic_vector(0 to 7) := (others => '0');
signal msg_chan_exists : std_logic := '0';
signal msg_chan_full : std_logic := '0';
signal cmd : std_logic := '0';
signal opcode : std_logic_vector(0 to C_CMD_WIDTH-1) := (others => '0');
signal iid : std_logic_vector(0 to C_IID_WIDTH-1) := (others => '0');
signal tid : std_logic_vector(0 to 7) := (others => '0');
signal core_reset, reset_sig : std_logic := '0';
-- Core Outputs
signal msg_chan_channelDataIn : std_logic_vector(0 to 7);
signal msg_chan_channelRead : std_logic;
signal msg_chan_channelWrite : std_logic;
signal ack : std_logic;
signal ret_out: std_logic_vector(0 to 7);
signal tid_out : std_logic_vector(0 to 7);
-- Message channels signals
signal FSL_S_Read : std_logic;
signal FSL_S_Exists : std_logic;
signal FSL_Has_Data : std_logic;
signal FSL_Data : std_logic_vector(0 to 7);
------------------------------------------
-- Signals for user logic master model example
------------------------------------------
-- signals for master model control/status registers write/read
signal mst_ip2bus_data : std_logic_vector(0 to C_SLV_DWIDTH-1);
-- signals for master model control/status registers
type BYTE_REG_TYPE is array(0 to 15) of std_logic_vector(0 to 7);
signal mst_go, IP2Bus_MstRdReq : std_logic;
-- signals for master model command interface state machine
type CMD_CNTL_SM_TYPE is (CMD_IDLE, CMD_RUN, CMD_WAIT_FOR_DATA, CMD_DONE);
signal mst_cmd_sm_state : CMD_CNTL_SM_TYPE;
signal mst_cmd_sm_set_done : std_logic;
signal mst_cmd_sm_set_error : std_logic;
signal mst_cmd_sm_set_timeout : std_logic;
signal mst_cmd_sm_busy : std_logic;
signal mst_cmd_sm_clr_go : std_logic;
signal mst_cmd_sm_rd_req : std_logic;
signal mst_cmd_sm_wr_req : std_logic;
signal mst_cmd_sm_reset : std_logic;
signal mst_cmd_sm_bus_lock : std_logic;
signal IP2Bus_Addr, mst_cmd_sm_ip2bus_addr : std_logic_vector(0 to C_MST_AWIDTH-1);
signal mst_cmd_sm_ip2bus_be : std_logic_vector(0 to C_MST_DWIDTH/8-1);
signal mst_fifo_valid_write_xfer : std_logic;
signal mst_fifo_valid_read_xfer : std_logic;
COMPONENT complete_pic
generic(
IID_WIDTH : integer := 3;
REG_SIZE : integer := 9;
CMD_WIDTH : integer := 4;
C_NUM_INTERRUPTS : integer := 8
);
PORT(
msg_chan_channelDataIn : OUT std_logic_vector(0 to 7);
msg_chan_channelDataOut : IN std_logic_vector(0 to 7);
msg_chan_exists : IN std_logic;
msg_chan_full : IN std_logic;
msg_chan_channelRead : OUT std_logic;
msg_chan_channelWrite : OUT std_logic;
go : IN std_logic;
ack : OUT std_logic;
TID_IN : IN std_logic_vector(0 to 7);
IID_IN : in std_logic_vector(0 to IID_WIDTH - 1);
CMD_IN : in std_logic_vector(0 to CMD_WIDTH - 1);
RET_OUT : OUT std_logic_vector(0 to 7);
TID_OUT : OUT std_logic_vector(0 to 7);
-- interrupts_in : in std_logic_vector(0 to 2**IID_WIDTH - 1);
-- TODO: Fix files to handle variable number and not exactly 8!
interrupts_in : in std_logic_vector(0 to C_NUM_INTERRUPTS-1);
clock_sig : IN std_logic;
reset_sig : IN std_logic
);
END COMPONENT;
component fsl_v20 is
generic (
C_EXT_RESET_HIGH : integer;
C_ASYNC_CLKS : integer;
C_IMPL_STYLE : integer;
C_USE_CONTROL : integer;
C_FSL_DWIDTH : integer;
C_FSL_DEPTH : integer;
C_READ_CLOCK_PERIOD : integer
);
port (
FSL_Clk : in std_logic;
SYS_Rst : in std_logic;
FSL_Rst : out std_logic;
FSL_M_Clk : in std_logic;
FSL_M_Data : in std_logic_vector(0 to C_FSL_DWIDTH-1);
FSL_M_Control : in std_logic;
FSL_M_Write : in std_logic;
FSL_M_Full : out std_logic;
FSL_S_Clk : in std_logic;
FSL_S_Data : out std_logic_vector(0 to C_FSL_DWIDTH-1);
FSL_S_Control : out std_logic;
FSL_S_Read : in std_logic;
FSL_S_Exists : out std_logic;
FSL_Full : out std_logic;
FSL_Has_Data : out std_logic;
FSL_Control_IRQ : out std_logic
);
end component;
-- ***************************
-- ChipScope Cores
-- ***************************
-- ChipScope signals
-- signal CONTROL0 : std_logic_vector(35 downto 0);
-- signal TRIG0 : std_logic_vector(15 downto 0);
-- signal TRIG1 : std_logic_vector(31 downto 0);
-- signal TRIG2 : std_logic_vector(3 downto 0);
--
-- component chipscope_icon_v1_03_a
-- PORT (
-- CONTROL0 : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0));
--
-- end component;
--
-- component chipscope_ila_ul_v1_02_a
-- PORT (
-- CONTROL : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
-- CLK : IN STD_LOGIC;
-- TRIG0 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
-- TRIG1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
-- TRIG2 : IN STD_LOGIC_VECTOR(3 DOWNTO 0));
--
-- end component;
---------------------------------------------------
-- bit_set()
-- *******************
-- Determine if any bit in the array is set.
-- If any of the bits are set then '1' is returned,
-- otherwise '0' is returned.
---------------------------------------------------
function bit_set( data : in std_logic_vector ) return std_logic is
begin
for i in data'range loop
if( data(i) = '1' ) then
return '1';
end if;
end loop;
return '0';
end function;
---------------------------------------------------
function getIID( addr : in std_logic_vector(0 to 31)) return std_logic_vector is
begin
--return "00" & addr(24 to 29);
return addr( 24 to (24+C_IID_WIDTH-1) );
end function;
function getTID( addr : in std_logic_vector(0 to 31)) return std_logic_vector is
begin
return addr(16 to 23);
end function;
function form_tm_addr( tid : in std_logic_vector(0 to 7)) return std_logic_vector is
variable mask : std_logic_vector(0 to 31);
begin
mask := x"00001" & "00" & tid & "00";
return C_TM_BASE or mask;
end function;
--*************************************************
-- Beginning of user_logic ARCHITECTURE
--*************************************************
begin
core_reset <= reset_sig; -- or Bus2IP_Reset;
-- Instantiate the Core
internalCore: complete_pic
-- internalCore : entity plb_fsmlang_special_pic_v1_00_a.complete_pic
-- internalCore : entity complete_pic
GENERIC MAP (
IID_WIDTH => C_IID_WIDTH,
REG_SIZE => C_REG_SIZE,
CMD_WIDTH => C_CMD_WIDTH,
C_NUM_INTERRUPTS => C_NUM_INTERRUPTS
)
PORT MAP (
msg_chan_channelDataIn => msg_chan_channelDataIn,
msg_chan_channelDataOut => msg_chan_channelDataOut,
msg_chan_exists => msg_chan_exists,
msg_chan_full => msg_chan_full,
msg_chan_channelRead => msg_chan_channelRead,
msg_chan_channelWrite => msg_chan_channelWrite,
go => cmd,
ack => ack,
TID_IN => tid,
IID_IN => iid,
CMD_IN => opcode,
RET_OUT => ret_out,
TID_OUT => tid_out,
interrupts_in => interrupts_in,
clock_sig => Bus2IP_Clk,
reset_sig => core_reset
);
-- ChipScope Instantiations
-- pic_icon : chipscope_icon_v1_03_a
-- port map (
-- CONTROL0 => CONTROL0);
--
-- pic_ila_ul : chipscope_ila_ul_v1_02_a
-- port map (
-- CONTROL => CONTROL0,
-- CLK => Bus2IP_Clk,
-- TRIG0 => TRIG0,
-- TRIG1 => TRIG1,
-- TRIG2 => TRIG2);
--
-- TRIG0 <= FSL_S_Exists & FSL_S_Read & mst_go & mst_cmd_sm_rd_req & Bus2IP_Mst_CmdAck & Bus2IP_Mst_Cmplt & Bus2IP_Mst_Cmd_Timeout & Bus2IP_Mst_Error & FSL_Data;
-- TRIG1 <= mst_cmd_sm_ip2bus_addr;
-- TRIG2 <= interrupts_in;
message_channel : fsl_v20
generic map (
C_EXT_RESET_HIGH => 1,
C_ASYNC_CLKS => 0,
C_IMPL_STYLE => 1,
C_USE_CONTROL => 0,
C_FSL_DWIDTH => 8,
C_FSL_DEPTH => 256,
C_READ_CLOCK_PERIOD => 0
)
port map (
FSL_Clk => Bus2IP_Clk,
SYS_Rst => Bus2IP_Reset,
FSL_Rst => open,
FSL_M_Clk => Bus2IP_Clk,
FSL_M_Data => msg_chan_channelDataIn,
FSL_M_Control => '0',
FSL_M_Write => msg_chan_channelWrite,
FSL_M_Full => msg_chan_full,
FSL_S_Clk => Bus2IP_Clk,
FSL_S_Data => FSL_Data,
FSL_S_Control => open,
FSL_S_Read => FSL_S_Read,
FSL_S_Exists => FSL_S_Exists,
FSL_Full => open,
FSL_Has_Data => FSL_Has_Data,
FSL_Control_IRQ => open
);
-- user logic master command interface assignments
IP2Bus_MstRd_Req <= mst_cmd_sm_rd_req;
IP2Bus_MstWr_Req <= mst_cmd_sm_wr_req;
IP2Bus_Mst_Addr <= mst_cmd_sm_ip2bus_addr;
IP2Bus_Mst_BE <= mst_cmd_sm_ip2bus_be;
IP2Bus_Mst_Lock <= mst_cmd_sm_bus_lock;
IP2Bus_Mst_Reset <= mst_cmd_sm_reset;
--implement master command interface state machine
mst_go <= FSL_S_Exists; -- Start master transaction when data exists in the FSL
MASTER_CMD_SM_PROC : process( Bus2IP_Clk ) is
begin
if ( Bus2IP_Clk'event and Bus2IP_Clk = '1' ) then
if ( Bus2IP_Reset = '1' ) then
-- reset condition
mst_cmd_sm_state <= CMD_IDLE;
mst_cmd_sm_clr_go <= '0';
mst_cmd_sm_rd_req <= '0';
mst_cmd_sm_wr_req <= '0';
mst_cmd_sm_bus_lock <= '0';
mst_cmd_sm_reset <= '0';
mst_cmd_sm_ip2bus_addr <= (others => '0');
mst_cmd_sm_ip2bus_be <= (others => '0');
mst_cmd_sm_set_done <= '0';
mst_cmd_sm_set_error <= '0';
mst_cmd_sm_set_timeout <= '0';
mst_cmd_sm_busy <= '0';
FSL_S_Read <= '0';
else
-- default condition
mst_cmd_sm_clr_go <= '0';
mst_cmd_sm_rd_req <= '0';
mst_cmd_sm_wr_req <= '0';
mst_cmd_sm_bus_lock <= '0';
mst_cmd_sm_reset <= '0';
mst_cmd_sm_ip2bus_addr <= (others => '0');
mst_cmd_sm_ip2bus_be <= (others => '0');
mst_cmd_sm_set_done <= '0';
mst_cmd_sm_set_error <= '0';
mst_cmd_sm_set_timeout <= '0';
mst_cmd_sm_busy <= '1';
FSL_S_Read <= '0';
-- state transition
case mst_cmd_sm_state is
when CMD_IDLE =>
if ( mst_go = '1' ) then
mst_cmd_sm_state <= CMD_RUN;
mst_cmd_sm_clr_go <= '1';
else
mst_cmd_sm_state <= CMD_IDLE;
mst_cmd_sm_busy <= '0';
end if;
when CMD_RUN =>
if ( Bus2IP_Mst_CmdAck = '1' and Bus2IP_Mst_Cmplt = '0' ) then
-- Signal a read on the FSL to pop off the element
FSL_S_Read <= '1';
mst_cmd_sm_state <= CMD_WAIT_FOR_DATA;
elsif ( Bus2IP_Mst_Cmplt = '1' ) then
-- Signal a read on the FSL to pop off the element
FSL_S_Read <= '1';
mst_cmd_sm_state <= CMD_DONE;
if ( Bus2IP_Mst_Cmd_Timeout = '1' ) then
-- PLB address phase timeout
mst_cmd_sm_set_error <= '1';
mst_cmd_sm_set_timeout <= '1';
elsif ( Bus2IP_Mst_Error = '1' ) then
-- PLB data transfer error
mst_cmd_sm_set_error <= '1';
end if;
else
mst_cmd_sm_state <= CMD_RUN;
mst_cmd_sm_rd_req <= '1'; -- Perform a write (rd = '1', wr = '0')
mst_cmd_sm_wr_req <= '0';
mst_cmd_sm_ip2bus_addr <= form_tm_addr(FSL_Data); -- Setup address
mst_cmd_sm_ip2bus_be <= (others => '1'); -- Use all byte lanes
mst_cmd_sm_bus_lock <= '0'; -- De-assert bus lock
end if;
when CMD_WAIT_FOR_DATA =>
if ( Bus2IP_Mst_Cmplt = '1' ) then
mst_cmd_sm_state <= CMD_DONE;
else
mst_cmd_sm_state <= CMD_WAIT_FOR_DATA;
end if;
when CMD_DONE =>
mst_cmd_sm_state <= CMD_IDLE;
mst_cmd_sm_set_done <= '1';
mst_cmd_sm_busy <= '0';
when others =>
mst_cmd_sm_state <= CMD_IDLE;
mst_cmd_sm_busy <= '0';
end case;
end if;
end if;
end process MASTER_CMD_SM_PROC;
-- Create concatenation signals
Bus2IP_RdCE_concat <= bit_set(Bus2IP_RdCE);
Bus2IP_WrCE_concat <= bit_set(Bus2IP_WrCE);
-- *************************************************************************
-- Process: BUS_OUTPUT_CONTROLLER
-- Purpose: Control output from IP to Bus
-- * Can be controlled using bus_data_ready, bus_ack_ready, and bus_data_out signals.
-- *************************************************************************
BUS_OUTPUT_CONTROLLER : process( Bus2IP_Clk, bus_data_ready, bus_ack_ready ) is
begin
if( Bus2IP_Clk'event and Bus2IP_Clk = '1' ) then
if( bus_data_ready = '1' and bus_ack_ready = '1' ) then
IP2Bus_Data <= bus_data_out; -- put data on bus
IP2Bus_Ack <= '1'; -- ACK bus
elsif (bus_data_ready = '1' and bus_ack_ready = '0') then
IP2Bus_Data <= bus_data_out; -- put data on bus
IP2Bus_Ack <= '0'; -- turn off ACK
else
IP2Bus_Data <= (others => '0'); -- output 0's on bus
IP2Bus_Ack <= '0'; -- turn off ACK
end if;
end if;
end process BUS_OUTPUT_CONTROLLER;
ACK_ROUTER : process (IP2Bus_Ack, Bus2IP_RdCE_concat, Bus2IP_WrCE_concat) is
begin
-- Turn an "ACK" into a specific ACK (read or write ACK)
if (Bus2IP_RdCE_concat = '1') then
IP2Bus_RdAck <= IP2Bus_Ack;
IP2Bus_WrAck <= '0';
else
IP2Bus_RdAck <= '0';
IP2Bus_WrAck <= IP2Bus_Ack;
end if;
end process;
-- *************************************************************************
-- Process: BUS_CMD_PROC
-- Purpose: Controller and decoder for incoming bus operations (reads and writes)
-- *************************************************************************
BUS_CMD_PROC : process (Bus2IP_Clk, Bus2IP_RdCE_concat, Bus2IP_WrCE_concat, Bus2IP_Addr ) is
begin
if( Bus2IP_Clk'event and Bus2IP_Clk = '1' ) then
OPWrite_Request <= '0';
OPRead_Request <= '0';
OPClear_Request <= '0';
OPManualReset_Request <= '0';
Error_Request <= '0';
if( Bus2IP_WrCE_concat = '1' ) then
Error_Request <= '1';
elsif( Bus2IP_RdCE_concat = '1' ) then
case Bus2IP_Addr(12 to 15) is
when OPCODE_WRITE => OPWrite_Request <= '1';
when OPCODE_READ => OPRead_Request <= '1';
when OPCODE_CLEAR => OPClear_Request <= '1';
when OPCODE_MANUAL_RESET => OPManualReset_Request <= '1';
when others => Error_Request <= '1';
end case;
end if;
end if;
end process BUS_CMD_PROC;
-- *************************************************************************
-- Process: MASTER_FSM_STATE_PROC
-- Purpose: Synchronous FSM controller for the master state machine
-- *************************************************************************
MASTER_FSM_STATE_PROC: process(
Bus2IP_Clk, Soft_Reset, inside_reset, inside_reset_next, next_state) is
begin
if ( Bus2IP_Clk'event and Bus2IP_Clk = '1' ) then
if( Soft_Reset = '1' and inside_reset = '0' ) then
-- Initialize all signals...
current_state <= reset;
inside_reset <= '1';
else
-- Assign all signals to their next state...
current_state <= next_state;
inside_reset <= inside_reset_next;
end if;
end if;
end process MASTER_FSM_STATE_PROC;
-- *************************************************************************
-- Process: MASTER_FSM_LOGIC_PROC
-- Purpose: Combinational process that contains all state machine logic and
-- state transitions for the master state machine
-- *************************************************************************
MASTER_FSM_LOGIC_PROC: process (
current_state, inside_reset, OPWrite_Request, OPRead_Request, OPManualReset_Request,
OPClear_Request, Error_Request, Bus2IP_Data, Bus2IP_RdCE_concat, Bus2IP_WrCE_concat, Soft_Reset, Bus2IP_Addr, ack ) is
-- Idle Variable, concatenation of all request signals
variable idle_concat : std_logic_vector(0 to 4);
begin
IP2Bus_Error <= '0'; -- no error
IP2Bus_Addr <= (others => '0');
IP2Bus_MstRdReq <= '0';
IP2Bus_MstWr_d <= (others => '0');
Reset_Done <= '0'; -- reset is done unless we override it later
next_state <= current_state;
inside_reset_next <= inside_reset;
bus_data_out <= (others => '0');
bus_data_ready <= '0';
bus_ack_ready <= '0';
cmd <= '0';
opcode <= (others => '0');
iid <= (others => '0');
tid <= (others => '0');
reset_sig <= '0';
case current_state is
when idle =>
-- Assign to variable for case statement
idle_concat := (OPWrite_Request & OPRead_Request & OPClear_Request & OPManualReset_Request & Error_Request);
-- Decode request
case (idle_concat) is
when "10000" => next_state <= opwrite_begin; -- OPWrite
when "01000" => next_state <= opread_begin; -- OPRead
when "00100" => next_state <= opclear_begin; -- OPReadAll
when "00010" => next_state <= manual_reset_begin; -- Manual Reset
when "00001" => bus_data_out <= (others => '1'); -- Error!!!
bus_data_ready <= '1';
bus_ack_ready <= '1';
next_state <= wait_trans_done;
when others => next_state <= idle; -- Others, stay in idle state
end case;
when wait_trans_done =>
-- Goal of this state is to return to the idle state ONLY (iff) the bus transaction has COMPLETELY ended!
bus_data_ready <= '0'; -- de-assert bus transaction signals
bus_ack_ready <= '0';
if( Bus2IP_RdCE_concat = '0' and Bus2IP_WrCE_concat = '0' ) then
next_state <= idle;
end if;
----------------------------
-- RESET: begin
----------------------------
when reset =>
reset_sig <= '1'; -- begin reset on cvCore
Reset_Done <= '0'; -- De-assert Reset_Done
next_state <= reset_core;
when reset_core =>
if (ack = '1') then
next_state <= reset_wait_4_ack;
else
next_state <= reset_core;
end if;
when reset_wait_4_ack =>
Reset_Done <= '1'; -- Assert that reset has completed
if( Soft_Reset = '0' ) then -- if reset is complete
Reset_Done <= '0'; -- de-assert that reset is complete
inside_reset_next <= '0'; -- de-assert to signal that process is no longer in reset
next_state <= idle; -- return to idle stage
end if;
----------------------------
-- RESET: end
----------------------------
----------------------------
-- MANUAL_RESET: begin
----------------------------
when manual_reset_begin =>
reset_sig <= '1'; -- begin reset on cvCore
next_state <= manual_reset_wait;
when manual_reset_wait =>
if (ack = '1') then
next_state <= manual_reset_finish;
else
next_state <= manual_reset_wait;
end if;
when manual_reset_finish =>
-- Finish transaction
bus_data_out <= x"ABCDABCD";
bus_data_ready <= '1';
bus_ack_ready <= '1';
next_state <= wait_trans_done;
----------------------------
-- MANUAL_RESET: end
----------------------------
----------------------------
-- WRITE: begin
----------------------------
when opwrite_begin =>
-- Setup Command
cmd <= '1';
opcode <= OPCODE_WRITE;
iid <= getIID(Bus2IP_Addr);
tid <= getTID(Bus2IP_Addr);
-- Persist with command until busy is received
if (ack = '1') then
next_state <= opwrite_wait_4_busy;
else
-- Persist with request and remain
next_state <= opwrite_begin;
end if;
when opwrite_wait_4_busy =>
if (ack = '0') then
-- Continue on when core is no longer busy
cmd <= '0';
opcode <= (others => '0');
iid <= (others => '0');
tid <= (others => '0');
next_state <= opwrite_finish;
else
-- Persist with request
cmd <= '1';
opcode <= OPCODE_WRITE;
iid <= getIID(Bus2IP_Addr);
tid <= getTID(Bus2IP_Addr);
next_state <= opwrite_wait_4_busy;
end if;
when opwrite_finish =>
-- Finish transaction
bus_data_out <= conv_std_logic_vector(conv_integer(ret_out),32);
bus_data_ready <= '1';
bus_ack_ready <= '1';
next_state <= wait_trans_done;
----------------------------
-- READ: begin
----------------------------
when opread_begin =>
-- Setup Command
cmd <= '1';
opcode <= OPCODE_READ;
iid <= getIID(Bus2IP_Addr);
tid <= getTID(Bus2IP_Addr);
-- Persist with command until busy is received
if (ack = '1') then
next_state <= opread_wait_4_busy;
else
-- Persist with request and remain
next_state <= opread_begin;
end if;
when opread_wait_4_busy =>
if (ack = '0') then
-- Continue on when core is no longer busy
cmd <= '0';
opcode <= (others => '0');
iid <= (others => '0');
tid <= (others => '0');
next_state <= opread_finish;
else
-- Persist with request
cmd <= '1';
opcode <= OPCODE_READ;
iid <= getIID(Bus2IP_Addr);
tid <= getTID(Bus2IP_Addr);
next_state <= opread_wait_4_busy;
end if;
when opread_finish =>
-- Finish transaction
bus_data_out <= conv_std_logic_vector(conv_integer(ret_out(7) & tid_out),32);
bus_data_ready <= '1';
bus_ack_ready <= '1';
next_state <= wait_trans_done;
----------------------------
-- CLEAR: begin
----------------------------
when opclear_begin =>
-- Setup Command
cmd <= '1';
opcode <= OPCODE_CLEAR;
iid <= getIID(Bus2IP_Addr);
tid <= getTID(Bus2IP_Addr);
-- Persist with command until busy is received
if (ack = '1') then
next_state <= opclear_wait_4_busy;
else
-- Persist with request and remain
next_state <= opclear_begin;
end if;
when opclear_wait_4_busy =>
if (ack = '0') then
-- Continue on when core is no longer busy
cmd <= '0';
opcode <= (others => '0');
iid <= (others => '0');
tid <= (others => '0');
next_state <= opclear_finish;
else
-- Persist with request
cmd <= '1';
opcode <= OPCODE_CLEAR;
iid <= getIID(Bus2IP_Addr);
tid <= getTID(Bus2IP_Addr);
next_state <= opclear_wait_4_busy;
end if;
when opclear_finish =>
-- Finish transaction
bus_data_out <= (others => '0');
bus_data_ready <= '1';
bus_ack_ready <= '1';
next_state <= wait_trans_done;
when others =>
next_state <= idle;
end case; -- END CASE (current_state)
end process MASTER_FSM_LOGIC_PROC;
end architecture IMP;
|
bsd-3-clause
|
masson2013/heterogeneous_hthreads
|
src/platforms/xilinx/smp1/design/pcores/plb_thread_manager_v1_00_a/hdl/vhdl/plb_thread_manager.vhd
|
9
|
24206
|
------------------------------------------------------------------------------
-- plb_thread_manager.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: plb_thread_manager.vhd
-- Version: 1.00.a
-- Description: Top level design, instantiates library components and user logic.
-- Date: Tue Apr 14 15:01:53 2009 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library plbv46_slave_single_v1_01_a;
use plbv46_slave_single_v1_01_a.plbv46_slave_single;
library plb_thread_manager_v1_00_a;
use plb_thread_manager_v1_00_a.user_logic;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_BASEADDR -- PLBv46 slave: base address
-- C_HIGHADDR -- PLBv46 slave: high address
-- C_SPLB_AWIDTH -- PLBv46 slave: address bus width
-- C_SPLB_DWIDTH -- PLBv46 slave: data bus width
-- C_SPLB_NUM_MASTERS -- PLBv46 slave: Number of masters
-- C_SPLB_MID_WIDTH -- PLBv46 slave: master ID bus width
-- C_SPLB_NATIVE_DWIDTH -- PLBv46 slave: internal native data bus width
-- C_SPLB_P2P -- PLBv46 slave: point to point interconnect scheme
-- C_SPLB_SUPPORT_BURSTS -- PLBv46 slave: support bursts
-- C_SPLB_SMALLEST_MASTER -- PLBv46 slave: width of the smallest master
-- C_SPLB_CLK_PERIOD_PS -- PLBv46 slave: bus clock in picoseconds
-- C_INCLUDE_DPHASE_TIMER -- PLBv46 slave: Data Phase Timer configuration; 0 = exclude timer, 1 = include timer
-- C_FAMILY -- Xilinx FPGA family
--
-- Definition of Ports:
-- SPLB_Clk -- PLB main bus clock
-- SPLB_Rst -- PLB main bus reset
-- PLB_ABus -- PLB address bus
-- PLB_UABus -- PLB upper address bus
-- PLB_PAValid -- PLB primary address valid indicator
-- PLB_SAValid -- PLB secondary address valid indicator
-- PLB_rdPrim -- PLB secondary to primary read request indicator
-- PLB_wrPrim -- PLB secondary to primary write request indicator
-- PLB_masterID -- PLB current master identifier
-- PLB_abort -- PLB abort request indicator
-- PLB_busLock -- PLB bus lock
-- PLB_RNW -- PLB read/not write
-- PLB_BE -- PLB byte enables
-- PLB_MSize -- PLB master data bus size
-- PLB_size -- PLB transfer size
-- PLB_type -- PLB transfer type
-- PLB_lockErr -- PLB lock error indicator
-- PLB_wrDBus -- PLB write data bus
-- PLB_wrBurst -- PLB burst write transfer indicator
-- PLB_rdBurst -- PLB burst read transfer indicator
-- PLB_wrPendReq -- PLB write pending bus request indicator
-- PLB_rdPendReq -- PLB read pending bus request indicator
-- PLB_wrPendPri -- PLB write pending request priority
-- PLB_rdPendPri -- PLB read pending request priority
-- PLB_reqPri -- PLB current request priority
-- PLB_TAttribute -- PLB transfer attribute
-- Sl_addrAck -- Slave address acknowledge
-- Sl_SSize -- Slave data bus size
-- Sl_wait -- Slave wait indicator
-- Sl_rearbitrate -- Slave re-arbitrate bus indicator
-- Sl_wrDAck -- Slave write data acknowledge
-- Sl_wrComp -- Slave write transfer complete indicator
-- Sl_wrBTerm -- Slave terminate write burst transfer
-- Sl_rdDBus -- Slave read data bus
-- Sl_rdWdAddr -- Slave read word address
-- Sl_rdDAck -- Slave read data acknowledge
-- Sl_rdComp -- Slave read transfer complete indicator
-- Sl_rdBTerm -- Slave terminate read burst transfer
-- Sl_MBusy -- Slave busy indicator
-- Sl_MWrErr -- Slave write error indicator
-- Sl_MRdErr -- Slave read error indicator
-- Sl_MIRQ -- Slave interrupt indicator
------------------------------------------------------------------------------
entity plb_thread_manager is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_SPLB_AWIDTH : integer := 32;
C_SPLB_DWIDTH : integer := 128;
C_SPLB_NUM_MASTERS : integer := 8;
C_SPLB_MID_WIDTH : integer := 3;
C_SPLB_NATIVE_DWIDTH : integer := 32;
C_SPLB_P2P : integer := 0;
C_SPLB_SUPPORT_BURSTS : integer := 0;
C_SPLB_SMALLEST_MASTER : integer := 32;
C_SPLB_CLK_PERIOD_PS : integer := 10000;
C_INCLUDE_DPHASE_TIMER : integer := 0;
C_FAMILY : string := "virtex5";
C_RESET_TIMEOUT : natural := 4096
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to C_SPLB_MID_WIDTH-1);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to C_SPLB_DWIDTH/8-1);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to C_SPLB_DWIDTH-1);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to C_SPLB_DWIDTH-1);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MWrErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MRdErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MIRQ : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
-- DO NOT EDIT ABOVE THIS LINE ---------------------
Access_Intr : out std_logic;
Scheduler_Reset : out std_logic;
Scheduler_Reset_Done : in std_logic;
Semaphore_Reset : out std_logic;
Semaphore_Reset_Done : in std_logic;
SpinLock_Reset : out std_logic;
SpinLock_Reset_Done : in std_logic;
User_IP_Reset : out std_logic;
User_IP_Reset_Done : in std_logic;
Soft_Stop : out std_logic;
tm2sch_cpu_thread_id : out std_logic_vector(0 to 7);
tm2sch_opcode : out std_logic_vector(0 to 5);
tm2sch_data : out std_logic_vector(0 to 7);
tm2sch_request : out std_logic;
tm2sch_DOB : out std_logic_vector(0 to 31);
sch2tm_ADDRB : in std_logic_vector(0 to 8);
sch2tm_DIB : in std_logic_vector(0 to 31);
sch2tm_ENB : in std_logic;
sch2tm_WEB : in std_logic;
sch2tm_busy : in std_logic;
sch2tm_data : in std_logic_vector(0 to 7);
sch2tm_next_id : in std_logic_vector(0 to 7);
sch2tm_next_id_valid : in std_logic
);
attribute SIGIS : string;
attribute SIGIS of SPLB_Clk : signal is "CLK";
attribute SIGIS of SPLB_Rst : signal is "RST";
end entity plb_thread_manager;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of plb_thread_manager is
------------------------------------------
-- Array of base/high address pairs for each address range
------------------------------------------
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
ZERO_ADDR_PAD & USER_SLV_HIGHADDR -- user logic slave space high address
);
------------------------------------------
-- Array of desired number of chip enables for each address range
------------------------------------------
constant USER_SLV_NUM_REG : integer := 1;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => pad_power2(USER_SLV_NUM_REG) -- number of ce for user logic slave space
);
------------------------------------------
-- Ratio of bus clock to core clock (for use in dual clock systems)
-- 1 = ratio is 1:1
-- 2 = ratio is 2:1
------------------------------------------
constant IPIF_BUS2CORE_CLK_RATIO : integer := 1;
------------------------------------------
-- Width of the slave data bus (32 only)
------------------------------------------
constant USER_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
constant IPIF_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
------------------------------------------
-- Index for CS/CE
------------------------------------------
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations
------------------------------------------
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Reset : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(0 to C_SPLB_AWIDTH-1);
signal ipif_Bus2IP_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(0 to IPIF_SLV_DWIDTH/8-1);
signal ipif_Bus2IP_CS : std_logic_vector(0 to ((IPIF_ARD_ADDR_RANGE_ARRAY'length)/2)-1);
signal ipif_Bus2IP_RdCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
signal ipif_Bus2IP_WrCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
signal user_Bus2IP_RdCE : std_logic_vector(0 to USER_NUM_REG-1);
signal user_Bus2IP_WrCE : std_logic_vector(0 to USER_NUM_REG-1);
signal user_IP2Bus_Data : std_logic_vector(0 to USER_SLV_DWIDTH-1);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
begin
------------------------------------------
-- instantiate plbv46_slave_single
------------------------------------------
PLBV46_SLAVE_SINGLE_I : entity plbv46_slave_single_v1_01_a.plbv46_slave_single
generic map
(
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_SPLB_P2P => C_SPLB_P2P,
C_BUS2CORE_CLK_RATIO => IPIF_BUS2CORE_CLK_RATIO,
C_SPLB_MID_WIDTH => C_SPLB_MID_WIDTH,
C_SPLB_NUM_MASTERS => C_SPLB_NUM_MASTERS,
C_SPLB_AWIDTH => C_SPLB_AWIDTH,
C_SPLB_DWIDTH => C_SPLB_DWIDTH,
C_SIPIF_DWIDTH => IPIF_SLV_DWIDTH,
C_INCLUDE_DPHASE_TIMER => C_INCLUDE_DPHASE_TIMER,
C_FAMILY => C_FAMILY
)
port map
(
SPLB_Clk => SPLB_Clk,
SPLB_Rst => SPLB_Rst,
PLB_ABus => PLB_ABus,
PLB_UABus => PLB_UABus,
PLB_PAValid => PLB_PAValid,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_masterID => PLB_masterID,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_MSize => PLB_MSize,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_lockErr => PLB_lockErr,
PLB_wrDBus => PLB_wrDBus,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendPri => PLB_rdPendPri,
PLB_reqPri => PLB_reqPri,
PLB_TAttribute => PLB_TAttribute,
Sl_addrAck => Sl_addrAck,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MBusy => Sl_MBusy,
Sl_MWrErr => Sl_MWrErr,
Sl_MRdErr => Sl_MRdErr,
Sl_MIRQ => Sl_MIRQ,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => ipif_Bus2IP_Reset,
IP2Bus_Data => ipif_IP2Bus_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE
);
------------------------------------------
-- instantiate User Logic
------------------------------------------
USER_LOGIC_I : entity plb_thread_manager_v1_00_a.user_logic
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
--USER generics mapped here
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_SLV_DWIDTH => USER_SLV_DWIDTH,
C_NUM_REG => USER_NUM_REG,
C_RESET_TIMEOUT => C_RESET_TIMEOUT
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
--USER ports mapped here
-- MAP USER PORTS ABOVE THIS LINE ------------------
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => ipif_Bus2IP_Reset,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error,
Access_Intr => Access_Intr,
Scheduler_Reset => Scheduler_Reset,
Scheduler_Reset_Done => Scheduler_Reset_Done,
Semaphore_Reset => Semaphore_Reset,
Semaphore_Reset_Done => Semaphore_Reset_Done,
SpinLock_Reset => SpinLock_Reset,
SpinLock_Reset_Done => SpinLock_Reset_Done,
User_IP_Reset => User_IP_Reset,
User_IP_Reset_Done => User_IP_Reset_Done,
Soft_Stop => Soft_Stop,
tm2sch_cpu_thread_id => tm2sch_cpu_thread_id,
tm2sch_opcode => tm2sch_opcode,
tm2sch_data => tm2sch_data,
tm2sch_request => tm2sch_request,
tm2sch_DOB => tm2sch_DOB,
sch2tm_ADDRB => sch2tm_ADDRB,
sch2tm_DIB => sch2tm_DIB,
sch2tm_ENB => sch2tm_ENB,
sch2tm_WEB => sch2tm_WEB,
sch2tm_busy => sch2tm_busy,
sch2tm_data => sch2tm_data,
sch2tm_next_id => sch2tm_next_id,
sch2tm_next_id_valid => sch2tm_next_id_valid
);
------------------------------------------
-- connect internal signals
------------------------------------------
ipif_IP2Bus_Data <= user_IP2Bus_Data;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
end IMP;
|
bsd-3-clause
|
masson2013/heterogeneous_hthreads
|
src/platforms/xilinx/ml605_pr_smp1_14_7/design/pcores/plb_thread_manager_v1_00_a/hdl/vhdl/plb_thread_manager.vhd
|
9
|
24206
|
------------------------------------------------------------------------------
-- plb_thread_manager.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: plb_thread_manager.vhd
-- Version: 1.00.a
-- Description: Top level design, instantiates library components and user logic.
-- Date: Tue Apr 14 15:01:53 2009 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library plbv46_slave_single_v1_01_a;
use plbv46_slave_single_v1_01_a.plbv46_slave_single;
library plb_thread_manager_v1_00_a;
use plb_thread_manager_v1_00_a.user_logic;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_BASEADDR -- PLBv46 slave: base address
-- C_HIGHADDR -- PLBv46 slave: high address
-- C_SPLB_AWIDTH -- PLBv46 slave: address bus width
-- C_SPLB_DWIDTH -- PLBv46 slave: data bus width
-- C_SPLB_NUM_MASTERS -- PLBv46 slave: Number of masters
-- C_SPLB_MID_WIDTH -- PLBv46 slave: master ID bus width
-- C_SPLB_NATIVE_DWIDTH -- PLBv46 slave: internal native data bus width
-- C_SPLB_P2P -- PLBv46 slave: point to point interconnect scheme
-- C_SPLB_SUPPORT_BURSTS -- PLBv46 slave: support bursts
-- C_SPLB_SMALLEST_MASTER -- PLBv46 slave: width of the smallest master
-- C_SPLB_CLK_PERIOD_PS -- PLBv46 slave: bus clock in picoseconds
-- C_INCLUDE_DPHASE_TIMER -- PLBv46 slave: Data Phase Timer configuration; 0 = exclude timer, 1 = include timer
-- C_FAMILY -- Xilinx FPGA family
--
-- Definition of Ports:
-- SPLB_Clk -- PLB main bus clock
-- SPLB_Rst -- PLB main bus reset
-- PLB_ABus -- PLB address bus
-- PLB_UABus -- PLB upper address bus
-- PLB_PAValid -- PLB primary address valid indicator
-- PLB_SAValid -- PLB secondary address valid indicator
-- PLB_rdPrim -- PLB secondary to primary read request indicator
-- PLB_wrPrim -- PLB secondary to primary write request indicator
-- PLB_masterID -- PLB current master identifier
-- PLB_abort -- PLB abort request indicator
-- PLB_busLock -- PLB bus lock
-- PLB_RNW -- PLB read/not write
-- PLB_BE -- PLB byte enables
-- PLB_MSize -- PLB master data bus size
-- PLB_size -- PLB transfer size
-- PLB_type -- PLB transfer type
-- PLB_lockErr -- PLB lock error indicator
-- PLB_wrDBus -- PLB write data bus
-- PLB_wrBurst -- PLB burst write transfer indicator
-- PLB_rdBurst -- PLB burst read transfer indicator
-- PLB_wrPendReq -- PLB write pending bus request indicator
-- PLB_rdPendReq -- PLB read pending bus request indicator
-- PLB_wrPendPri -- PLB write pending request priority
-- PLB_rdPendPri -- PLB read pending request priority
-- PLB_reqPri -- PLB current request priority
-- PLB_TAttribute -- PLB transfer attribute
-- Sl_addrAck -- Slave address acknowledge
-- Sl_SSize -- Slave data bus size
-- Sl_wait -- Slave wait indicator
-- Sl_rearbitrate -- Slave re-arbitrate bus indicator
-- Sl_wrDAck -- Slave write data acknowledge
-- Sl_wrComp -- Slave write transfer complete indicator
-- Sl_wrBTerm -- Slave terminate write burst transfer
-- Sl_rdDBus -- Slave read data bus
-- Sl_rdWdAddr -- Slave read word address
-- Sl_rdDAck -- Slave read data acknowledge
-- Sl_rdComp -- Slave read transfer complete indicator
-- Sl_rdBTerm -- Slave terminate read burst transfer
-- Sl_MBusy -- Slave busy indicator
-- Sl_MWrErr -- Slave write error indicator
-- Sl_MRdErr -- Slave read error indicator
-- Sl_MIRQ -- Slave interrupt indicator
------------------------------------------------------------------------------
entity plb_thread_manager is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_SPLB_AWIDTH : integer := 32;
C_SPLB_DWIDTH : integer := 128;
C_SPLB_NUM_MASTERS : integer := 8;
C_SPLB_MID_WIDTH : integer := 3;
C_SPLB_NATIVE_DWIDTH : integer := 32;
C_SPLB_P2P : integer := 0;
C_SPLB_SUPPORT_BURSTS : integer := 0;
C_SPLB_SMALLEST_MASTER : integer := 32;
C_SPLB_CLK_PERIOD_PS : integer := 10000;
C_INCLUDE_DPHASE_TIMER : integer := 0;
C_FAMILY : string := "virtex5";
C_RESET_TIMEOUT : natural := 4096
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to C_SPLB_MID_WIDTH-1);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to C_SPLB_DWIDTH/8-1);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to C_SPLB_DWIDTH-1);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to C_SPLB_DWIDTH-1);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MWrErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MRdErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MIRQ : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
-- DO NOT EDIT ABOVE THIS LINE ---------------------
Access_Intr : out std_logic;
Scheduler_Reset : out std_logic;
Scheduler_Reset_Done : in std_logic;
Semaphore_Reset : out std_logic;
Semaphore_Reset_Done : in std_logic;
SpinLock_Reset : out std_logic;
SpinLock_Reset_Done : in std_logic;
User_IP_Reset : out std_logic;
User_IP_Reset_Done : in std_logic;
Soft_Stop : out std_logic;
tm2sch_cpu_thread_id : out std_logic_vector(0 to 7);
tm2sch_opcode : out std_logic_vector(0 to 5);
tm2sch_data : out std_logic_vector(0 to 7);
tm2sch_request : out std_logic;
tm2sch_DOB : out std_logic_vector(0 to 31);
sch2tm_ADDRB : in std_logic_vector(0 to 8);
sch2tm_DIB : in std_logic_vector(0 to 31);
sch2tm_ENB : in std_logic;
sch2tm_WEB : in std_logic;
sch2tm_busy : in std_logic;
sch2tm_data : in std_logic_vector(0 to 7);
sch2tm_next_id : in std_logic_vector(0 to 7);
sch2tm_next_id_valid : in std_logic
);
attribute SIGIS : string;
attribute SIGIS of SPLB_Clk : signal is "CLK";
attribute SIGIS of SPLB_Rst : signal is "RST";
end entity plb_thread_manager;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of plb_thread_manager is
------------------------------------------
-- Array of base/high address pairs for each address range
------------------------------------------
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
ZERO_ADDR_PAD & USER_SLV_HIGHADDR -- user logic slave space high address
);
------------------------------------------
-- Array of desired number of chip enables for each address range
------------------------------------------
constant USER_SLV_NUM_REG : integer := 1;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => pad_power2(USER_SLV_NUM_REG) -- number of ce for user logic slave space
);
------------------------------------------
-- Ratio of bus clock to core clock (for use in dual clock systems)
-- 1 = ratio is 1:1
-- 2 = ratio is 2:1
------------------------------------------
constant IPIF_BUS2CORE_CLK_RATIO : integer := 1;
------------------------------------------
-- Width of the slave data bus (32 only)
------------------------------------------
constant USER_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
constant IPIF_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
------------------------------------------
-- Index for CS/CE
------------------------------------------
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations
------------------------------------------
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Reset : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(0 to C_SPLB_AWIDTH-1);
signal ipif_Bus2IP_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(0 to IPIF_SLV_DWIDTH/8-1);
signal ipif_Bus2IP_CS : std_logic_vector(0 to ((IPIF_ARD_ADDR_RANGE_ARRAY'length)/2)-1);
signal ipif_Bus2IP_RdCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
signal ipif_Bus2IP_WrCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
signal user_Bus2IP_RdCE : std_logic_vector(0 to USER_NUM_REG-1);
signal user_Bus2IP_WrCE : std_logic_vector(0 to USER_NUM_REG-1);
signal user_IP2Bus_Data : std_logic_vector(0 to USER_SLV_DWIDTH-1);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
begin
------------------------------------------
-- instantiate plbv46_slave_single
------------------------------------------
PLBV46_SLAVE_SINGLE_I : entity plbv46_slave_single_v1_01_a.plbv46_slave_single
generic map
(
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_SPLB_P2P => C_SPLB_P2P,
C_BUS2CORE_CLK_RATIO => IPIF_BUS2CORE_CLK_RATIO,
C_SPLB_MID_WIDTH => C_SPLB_MID_WIDTH,
C_SPLB_NUM_MASTERS => C_SPLB_NUM_MASTERS,
C_SPLB_AWIDTH => C_SPLB_AWIDTH,
C_SPLB_DWIDTH => C_SPLB_DWIDTH,
C_SIPIF_DWIDTH => IPIF_SLV_DWIDTH,
C_INCLUDE_DPHASE_TIMER => C_INCLUDE_DPHASE_TIMER,
C_FAMILY => C_FAMILY
)
port map
(
SPLB_Clk => SPLB_Clk,
SPLB_Rst => SPLB_Rst,
PLB_ABus => PLB_ABus,
PLB_UABus => PLB_UABus,
PLB_PAValid => PLB_PAValid,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_masterID => PLB_masterID,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_MSize => PLB_MSize,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_lockErr => PLB_lockErr,
PLB_wrDBus => PLB_wrDBus,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendPri => PLB_rdPendPri,
PLB_reqPri => PLB_reqPri,
PLB_TAttribute => PLB_TAttribute,
Sl_addrAck => Sl_addrAck,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MBusy => Sl_MBusy,
Sl_MWrErr => Sl_MWrErr,
Sl_MRdErr => Sl_MRdErr,
Sl_MIRQ => Sl_MIRQ,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => ipif_Bus2IP_Reset,
IP2Bus_Data => ipif_IP2Bus_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE
);
------------------------------------------
-- instantiate User Logic
------------------------------------------
USER_LOGIC_I : entity plb_thread_manager_v1_00_a.user_logic
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
--USER generics mapped here
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_SLV_DWIDTH => USER_SLV_DWIDTH,
C_NUM_REG => USER_NUM_REG,
C_RESET_TIMEOUT => C_RESET_TIMEOUT
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
--USER ports mapped here
-- MAP USER PORTS ABOVE THIS LINE ------------------
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => ipif_Bus2IP_Reset,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error,
Access_Intr => Access_Intr,
Scheduler_Reset => Scheduler_Reset,
Scheduler_Reset_Done => Scheduler_Reset_Done,
Semaphore_Reset => Semaphore_Reset,
Semaphore_Reset_Done => Semaphore_Reset_Done,
SpinLock_Reset => SpinLock_Reset,
SpinLock_Reset_Done => SpinLock_Reset_Done,
User_IP_Reset => User_IP_Reset,
User_IP_Reset_Done => User_IP_Reset_Done,
Soft_Stop => Soft_Stop,
tm2sch_cpu_thread_id => tm2sch_cpu_thread_id,
tm2sch_opcode => tm2sch_opcode,
tm2sch_data => tm2sch_data,
tm2sch_request => tm2sch_request,
tm2sch_DOB => tm2sch_DOB,
sch2tm_ADDRB => sch2tm_ADDRB,
sch2tm_DIB => sch2tm_DIB,
sch2tm_ENB => sch2tm_ENB,
sch2tm_WEB => sch2tm_WEB,
sch2tm_busy => sch2tm_busy,
sch2tm_data => sch2tm_data,
sch2tm_next_id => sch2tm_next_id,
sch2tm_next_id_valid => sch2tm_next_id_valid
);
------------------------------------------
-- connect internal signals
------------------------------------------
ipif_IP2Bus_Data <= user_IP2Bus_Data;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
end IMP;
|
bsd-3-clause
|
jevinskie/aes-over-pcie
|
source/add_round_key.vhd
|
1
|
855
|
-- File name: add_round_key.vhd
-- Created: 2009-03-30
-- Author: Zachary Curosh
-- Lab Section: 337-02
-- Version: 1.0 Initial Design Entry
-- Description: each byte of the state is combined with the round
-- key; each round key is derived from the cipher key using the
-- key scheduler
use work.aes.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity add_round_key is
port (
data_in : in byte;
key_in : in byte;
data_out : out byte
);
end entity add_round_key;
architecture dataflow of add_round_key is
begin
-- for each round of the addroundkey step, a subkey byte that was
-- derived from the key scheduler is added to the corresponding
-- byte of the state using bitwise XOR.
data_out <= data_in xor key_in;
end architecture dataflow;
|
bsd-3-clause
|
jevinskie/aes-over-pcie
|
source/top_top.vhd
|
1
|
3449
|
-- File name: aes_top.vhd
-- Created: 2009-04-04
-- Author: Jevin Sweval
-- Lab Section: 337-02
-- Version: 1.0 Initial Design Entry
-- Description: AES top level
use work.aes.all;
use work.pcie.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity top_top is
port (
clk : in std_logic;
nrst : in std_logic;
rx_data : in byte;
rx_data_k : in std_logic;
rx_status : in std_logic_vector(2 downto 0);
rx_elec_idle : in std_logic;
phy_status : in std_logic;
rx_valid : in std_logic;
tx_detect_rx : out std_logic;
tx_elec_idle : out std_logic;
tx_comp : out std_logic;
rx_pol : out std_logic;
power_down : out std_logic_vector(1 downto 0);
tx_data : out byte;
tx_data_k : out std_logic
);
end entity top_top;
architecture structural of top_top is
signal got_key : std_logic;
signal got_pt : std_logic;
signal send_ct : std_logic;
signal aes_done : std_logic;
signal tx_data_aes : byte;
signal last_rx_data : byte;
begin
pcie_top_b : entity work.pcie_top(structural) port map (
clk => clk, nrst => nrst, rx_data => rx_data,
rx_data_k => rx_data_k, rx_status => rx_status,
rx_elec_idle => rx_elec_idle, phy_status => phy_status,
rx_valid => rx_valid, tx_detect_rx => tx_detect_rx,
tx_elec_idle => tx_elec_idle, tx_comp => tx_comp,
rx_pol => rx_pol, power_down => power_down,
tx_data => tx_data, tx_data_k => tx_data_k,
tx_data_aes => tx_data_aes, aes_done => aes_done,
got_key => got_key, got_pt => got_pt, send_ct => send_ct
);
-- leda C_1406 off
process(clk)
begin
if rising_edge(clk) then
last_rx_data <= rx_data;
end if;
end process;
-- leda C_1406 on
aes_top_b : entity work.aes_top(structural) port map (
clk => clk, nrst => nrst, rx_data => last_rx_data,
got_key => got_key, got_pt => got_pt, send_ct => send_ct,
aes_done => aes_done, tx_data => tx_data_aes
);
end architecture structural;
architecture structural_p of top_top is
signal got_key : std_logic;
signal got_pt : std_logic;
signal send_ct : std_logic;
signal aes_done : std_logic;
signal tx_data_aes : byte;
signal last_rx_data : byte;
begin
pcie_top_b : entity work.pcie_top(structural) port map (
clk => clk, nrst => nrst, rx_data => rx_data,
rx_data_k => rx_data_k, rx_status => rx_status,
rx_elec_idle => rx_elec_idle, phy_status => phy_status,
rx_valid => rx_valid, tx_detect_rx => tx_detect_rx,
tx_elec_idle => tx_elec_idle, tx_comp => tx_comp,
rx_pol => rx_pol, power_down => power_down,
tx_data => tx_data, tx_data_k => tx_data_k,
tx_data_aes => tx_data_aes, aes_done => aes_done,
got_key => got_key, got_pt => got_pt, send_ct => send_ct
);
-- leda C_1406 off
process(clk)
begin
if rising_edge(clk) then
last_rx_data <= rx_data;
end if;
end process;
-- leda C_1406 on
aes_top_p_b : entity work.aes_top(structural_p) port map (
clk => clk, nrst => nrst, rx_data => last_rx_data,
got_key => got_key, got_pt => got_pt, send_ct => send_ct,
aes_done => aes_done, tx_data => tx_data_aes
);
end architecture structural_p;
|
bsd-3-clause
|
masson2013/heterogeneous_hthreads
|
src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/opb_ipif_v2_00_h/hdl/vhdl/ip2bus_srmux_blk.vhd
|
3
|
5669
|
-------------------------------------------------------------------------------
-- $Id: ip2bus_srmux_blk.vhd,v 1.2 2004/11/23 01:04:03 jcanaris Exp $
-------------------------------------------------------------------------------
-- ip2bus_srmux_blk.vhd - VHD design file
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: ip2bus_srmux_blk.vhd
--
-- Description: VHDL design file that is a wrapper around the IPIF status
-- reply MUX design.
--
-------------------------------------------------------------------------------
-- Structure:
--
-- ip2bus_srmux_blk.vhd
-- ip2bus_srmux.vhd
--
-------------------------------------------------------------------------------
-- Author: D. Thorpe
--
-- History:
-- DET Aug 21, 2001 -- First version adapted from Visual HDL output
-- LCW Nov 8, 2004 -- updated for NCSim
--
--
--
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
---------------------------------------------------------------------------------
library IEEE;
use IEEE.Std_Logic_1164.all;
library unisim;
use unisim.vcomponents.all;
library opb_ipif_v2_00_h;
use opb_ipif_v2_00_h.ip2bus_srmux;
entity ip2bus_srmux_blk is
port (
DMA2Bus_Error : in std_logic;
DMA2Bus_RdAck : in std_logic;
DMA2Bus_Retry : in std_logic;
DMA2Bus_ToutSup : in std_logic;
DMA2Bus_WrAck : in std_logic;
Intr2Bus_Error : in std_logic;
Intr2Bus_RdAck : in std_logic;
Intr2Bus_Retry : in std_logic;
Intr2Bus_ToutSup : in std_logic;
Intr2Bus_WrAck : in std_logic;
IP2Bus_Error : in std_logic;
IP2Bus_Error_mx : out std_logic;
IP2Bus_RdAck : in std_logic;
IP2Bus_RdAck_mx : out std_logic;
IP2Bus_Retry : in std_logic;
IP2Bus_Retry_mx : out std_logic;
IP2Bus_ToutSup : in std_logic;
IP2Bus_ToutSup_mx : out std_logic;
IP2Bus_WrAck : in std_logic;
IP2Bus_WrAck_mx : out std_logic;
RFIFO_Error : in std_logic;
RFIFO_RdAck : in std_logic;
RFIFO_Retry : in std_logic;
RFIFO_ToutSup : in std_logic;
RFIFO_WrAck : in std_logic;
Rst2Bus_Error : in std_logic;
Rst2Bus_RdAck : in std_logic;
Rst2Bus_Retry : in std_logic;
Rst2Bus_ToutSup : in std_logic;
Rst2Bus_WrAck : in std_logic;
WFIFO_Error : in std_logic;
WFIFO_RdAck : in std_logic;
WFIFO_Retry : in std_logic;
WFIFO_ToutSup : in std_logic;
WFIFO_WrAck : in std_logic
);
end ip2bus_srmux_blk;
architecture implementation of ip2bus_srmux_blk is
begin
I_IP2BUS_SRMUX: entity opb_ipif_v2_00_h.ip2bus_srmux
port map (
IP2Bus_WrAck => IP2Bus_WrAck,
IP2Bus_RdAck => IP2Bus_RdAck,
IP2Bus_Retry => IP2Bus_Retry,
IP2Bus_Error => IP2Bus_Error,
IP2Bus_ToutSup => IP2Bus_ToutSup,
WFIFO_WrAck => WFIFO_WrAck,
WFIFO_RdAck => WFIFO_RdAck,
WFIFO_Retry => WFIFO_Retry,
WFIFO_Error => WFIFO_Error,
WFIFO_ToutSup => WFIFO_ToutSup,
RFIFO_WrAck => RFIFO_WrAck,
RFIFO_RdAck => RFIFO_RdAck,
RFIFO_Retry => RFIFO_Retry,
RFIFO_Error => RFIFO_Error,
RFIFO_ToutSup => RFIFO_ToutSup,
DMA2Bus_WrAck => DMA2Bus_WrAck,
DMA2Bus_RdAck => DMA2Bus_RdAck,
DMA2Bus_Retry => DMA2Bus_Retry,
DMA2Bus_Error => DMA2Bus_Error,
DMA2Bus_ToutSup => DMA2Bus_ToutSup,
IRPT_WrAck => Intr2Bus_WrAck,
IRPT_RdAck => Intr2Bus_RdAck,
IRPT_Retry => Intr2Bus_Retry,
IRPT_Error => Intr2Bus_Error,
IRPT_ToutSup => Intr2Bus_ToutSup,
RESET_WrAck => Rst2Bus_WrAck,
RESET_RdAck => Rst2Bus_RdAck,
RESET_Retry => Rst2Bus_Retry,
RESET_Error => Rst2Bus_Error,
RESET_ToutSup => Rst2Bus_ToutSup,
IP2Bus_WrAck_mx => IP2Bus_WrAck_mx,
IP2Bus_RdAck_mx => IP2Bus_RdAck_mx,
IP2Bus_Retry_mx => IP2Bus_Retry_mx,
IP2Bus_Error_mx => IP2Bus_Error_mx,
IP2Bus_ToutSup_mx => IP2Bus_ToutSup_mx);
end implementation;
|
bsd-3-clause
|
masson2013/heterogeneous_hthreads
|
src/platforms/xilinx/numa3_hwti/design/pcores/plb_sync_manager_v1_00_a/hdl/vhdl/plb_sync_manager.vhd
|
9
|
47769
|
------------------------------------------------------------------------------
-- plb_sync_manager.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: plb_sync_manager.vhd
-- Version: 1.00.a
-- Description: Top level design, instantiates library components and user logic.
-- Date: Thu May 7 14:29:05 2009 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library plbv46_slave_single_v1_01_a;
use plbv46_slave_single_v1_01_a.plbv46_slave_single;
library plbv46_master_single_v1_01_a;
use plbv46_master_single_v1_01_a.plbv46_master_single;
library plb_sync_manager_v1_00_a;
use plb_sync_manager_v1_00_a.user_logic;
use work.common.SYNCH_LOCK;
use work.common.SYNCH_UNLOCK;
use work.common.SYNCH_TRY;
use work.common.SYNCH_OWNER;
use work.common.SYNCH_KIND;
use work.common.SYNCH_COUNT;
use work.common.SYNCH_RESULT;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_BASEADDR -- PLBv46 slave: base address
-- C_HIGHADDR -- PLBv46 slave: high address
-- C_SPLB_AWIDTH -- PLBv46 slave: address bus width
-- C_SPLB_DWIDTH -- PLBv46 slave: data bus width
-- C_SPLB_NUM_MASTERS -- PLBv46 slave: Number of masters
-- C_SPLB_MID_WIDTH -- PLBv46 slave: master ID bus width
-- C_SPLB_NATIVE_DWIDTH -- PLBv46 slave: internal native data bus width
-- C_SPLB_P2P -- PLBv46 slave: point to point interconnect scheme
-- C_SPLB_SUPPORT_BURSTS -- PLBv46 slave: support bursts
-- C_SPLB_SMALLEST_MASTER -- PLBv46 slave: width of the smallest master
-- C_SPLB_CLK_PERIOD_PS -- PLBv46 slave: bus clock in picoseconds
-- C_INCLUDE_DPHASE_TIMER -- PLBv46 slave: Data Phase Timer configuration; 0 = exclude timer, 1 = include timer
-- C_FAMILY -- Xilinx FPGA family
-- C_MPLB_AWIDTH -- PLBv46 master: address bus width
-- C_MPLB_DWIDTH -- PLBv46 master: data bus width
-- C_MPLB_NATIVE_DWIDTH -- PLBv46 master: internal native data width
-- C_MPLB_P2P -- PLBv46 master: point to point interconnect scheme
-- C_MPLB_SMALLEST_SLAVE -- PLBv46 master: width of the smallest slave
-- C_MPLB_CLK_PERIOD_PS -- PLBv46 master: bus clock in picoseconds
--
-- Definition of Ports:
-- SPLB_Clk -- PLB main bus clock
-- SPLB_Rst -- PLB main bus reset
-- PLB_ABus -- PLB address bus
-- PLB_UABus -- PLB upper address bus
-- PLB_PAValid -- PLB primary address valid indicator
-- PLB_SAValid -- PLB secondary address valid indicator
-- PLB_rdPrim -- PLB secondary to primary read request indicator
-- PLB_wrPrim -- PLB secondary to primary write request indicator
-- PLB_masterID -- PLB current master identifier
-- PLB_abort -- PLB abort request indicator
-- PLB_busLock -- PLB bus lock
-- PLB_RNW -- PLB read/not write
-- PLB_BE -- PLB byte enables
-- PLB_MSize -- PLB master data bus size
-- PLB_size -- PLB transfer size
-- PLB_type -- PLB transfer type
-- PLB_lockErr -- PLB lock error indicator
-- PLB_wrDBus -- PLB write data bus
-- PLB_wrBurst -- PLB burst write transfer indicator
-- PLB_rdBurst -- PLB burst read transfer indicator
-- PLB_wrPendReq -- PLB write pending bus request indicator
-- PLB_rdPendReq -- PLB read pending bus request indicator
-- PLB_wrPendPri -- PLB write pending request priority
-- PLB_rdPendPri -- PLB read pending request priority
-- PLB_reqPri -- PLB current request priority
-- PLB_TAttribute -- PLB transfer attribute
-- Sl_addrAck -- Slave address acknowledge
-- Sl_SSize -- Slave data bus size
-- Sl_wait -- Slave wait indicator
-- Sl_rearbitrate -- Slave re-arbitrate bus indicator
-- Sl_wrDAck -- Slave write data acknowledge
-- Sl_wrComp -- Slave write transfer complete indicator
-- Sl_wrBTerm -- Slave terminate write burst transfer
-- Sl_rdDBus -- Slave read data bus
-- Sl_rdWdAddr -- Slave read word address
-- Sl_rdDAck -- Slave read data acknowledge
-- Sl_rdComp -- Slave read transfer complete indicator
-- Sl_rdBTerm -- Slave terminate read burst transfer
-- Sl_MBusy -- Slave busy indicator
-- Sl_MWrErr -- Slave write error indicator
-- Sl_MRdErr -- Slave read error indicator
-- Sl_MIRQ -- Slave interrupt indicator
-- MPLB_Clk -- PLB main bus Clock
-- MPLB_Rst -- PLB main bus Reset
-- MD_error -- Master detected error status output
-- M_request -- Master request
-- M_priority -- Master request priority
-- M_busLock -- Master buslock
-- M_RNW -- Master read/nor write
-- M_BE -- Master byte enables
-- M_MSize -- Master data bus size
-- M_size -- Master transfer size
-- M_type -- Master transfer type
-- M_TAttribute -- Master transfer attribute
-- M_lockErr -- Master lock error indicator
-- M_abort -- Master abort bus request indicator
-- M_UABus -- Master upper address bus
-- M_ABus -- Master address bus
-- M_wrDBus -- Master write data bus
-- M_wrBurst -- Master burst write transfer indicator
-- M_rdBurst -- Master burst read transfer indicator
-- PLB_MAddrAck -- PLB reply to master for address acknowledge
-- PLB_MSSize -- PLB reply to master for slave data bus size
-- PLB_MRearbitrate -- PLB reply to master for bus re-arbitrate indicator
-- PLB_MTimeout -- PLB reply to master for bus time out indicator
-- PLB_MBusy -- PLB reply to master for slave busy indicator
-- PLB_MRdErr -- PLB reply to master for slave read error indicator
-- PLB_MWrErr -- PLB reply to master for slave write error indicator
-- PLB_MIRQ -- PLB reply to master for slave interrupt indicator
-- PLB_MRdDBus -- PLB reply to master for read data bus
-- PLB_MRdWdAddr -- PLB reply to master for read word address
-- PLB_MRdDAck -- PLB reply to master for read data acknowledge
-- PLB_MRdBTerm -- PLB reply to master for terminate read burst indicator
-- PLB_MWrDAck -- PLB reply to master for write data acknowledge
-- PLB_MWrBTerm -- PLB reply to master for terminate write burst indicator
------------------------------------------------------------------------------
entity plb_sync_manager is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
C_NUM_THREADS : integer := 256;
C_NUM_MUTEXES : integer := 64;
C_SCHED_BADDR : std_logic_vector := X"00000000";
C_SCHED_HADDR : std_logic_vector := X"00000000";
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_SPLB_AWIDTH : integer := 32;
C_SPLB_DWIDTH : integer := 128;
C_SPLB_NUM_MASTERS : integer := 8;
C_SPLB_MID_WIDTH : integer := 3;
C_SPLB_NATIVE_DWIDTH : integer := 32;
C_SPLB_P2P : integer := 0;
C_SPLB_SUPPORT_BURSTS : integer := 0;
C_SPLB_SMALLEST_MASTER : integer := 32;
C_SPLB_CLK_PERIOD_PS : integer := 10000;
C_INCLUDE_DPHASE_TIMER : integer := 0;
C_FAMILY : string := "virtex5";
C_MPLB_AWIDTH : integer := 32;
C_MPLB_DWIDTH : integer := 128;
C_MPLB_NATIVE_DWIDTH : integer := 32;
C_MPLB_P2P : integer := 0;
C_MPLB_SMALLEST_SLAVE : integer := 32;
C_MPLB_CLK_PERIOD_PS : integer := 10000
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
system_reset : in std_logic;
system_resetdone : out std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to C_SPLB_MID_WIDTH-1);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to C_SPLB_DWIDTH/8-1);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to C_SPLB_DWIDTH-1);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to C_SPLB_DWIDTH-1);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MWrErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MRdErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MIRQ : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
MPLB_Clk : in std_logic;
MPLB_Rst : in std_logic;
MD_error : out std_logic;
M_request : out std_logic;
M_priority : out std_logic_vector(0 to 1);
M_busLock : out std_logic;
M_RNW : out std_logic;
M_BE : out std_logic_vector(0 to C_MPLB_DWIDTH/8-1);
M_MSize : out std_logic_vector(0 to 1);
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_TAttribute : out std_logic_vector(0 to 15);
M_lockErr : out std_logic;
M_abort : out std_logic;
M_UABus : out std_logic_vector(0 to 31);
M_ABus : out std_logic_vector(0 to 31);
M_wrDBus : out std_logic_vector(0 to C_MPLB_DWIDTH-1);
M_wrBurst : out std_logic;
M_rdBurst : out std_logic;
PLB_MAddrAck : in std_logic;
PLB_MSSize : in std_logic_vector(0 to 1);
PLB_MRearbitrate : in std_logic;
PLB_MTimeout : in std_logic;
PLB_MBusy : in std_logic;
PLB_MRdErr : in std_logic;
PLB_MWrErr : in std_logic;
PLB_MIRQ : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to (C_MPLB_DWIDTH-1));
PLB_MRdWdAddr : in std_logic_vector(0 to 3);
PLB_MRdDAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MWrBTerm : in std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of SPLB_Clk : signal is "CLK";
attribute SIGIS of MPLB_Clk : signal is "CLK";
attribute SIGIS of SPLB_Rst : signal is "RST";
attribute SIGIS of MPLB_Rst : signal is "RST";
end entity plb_sync_manager;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of plb_sync_manager is
-------------------------------------------------------------------
-- BEGIN CODE COPIED FROM OPB SYNCH MANAGER
-------------------------------------------------------------------
-- Constants for the number of bits needed to represent certain data
constant MUTEX_BITS : integer := log2(C_NUM_MUTEXES);
constant THREAD_BITS : integer := log2(C_NUM_THREADS);
constant KIND_BITS : integer := 2;
constant COUNT_BITS : integer := 8;
constant COMMAND_BITS : integer := 3;
function calc_base( cmd : in std_logic_vector(0 to COMMAND_BITS-1) )
return std_logic_vector is
variable addr : std_logic_vector(0 to C_SPLB_AWIDTH - 1);
begin
addr := C_BASEADDR;
addr(C_SPLB_AWIDTH - MUTEX_BITS - THREAD_BITS - COMMAND_BITS - 2 to
C_SPLB_AWIDTH - MUTEX_BITS - THREAD_BITS - 3) := cmd;
return addr;
end function calc_base;
function calc_high( cmd : in std_logic_vector(0 to COMMAND_BITS-1) )
return std_logic_vector is
variable addr : std_logic_vector(0 to C_SPLB_AWIDTH - 1);
begin
addr := C_BASEADDR;
addr(C_SPLB_AWIDTH - MUTEX_BITS - 2 to
C_SPLB_AWIDTH - 3) := (others => '1');
addr(C_SPLB_AWIDTH - MUTEX_BITS - THREAD_BITS - 2 to
C_SPLB_AWIDTH - MUTEX_BITS - 3) := (others => '1');
addr(C_SPLB_AWIDTH - MUTEX_BITS - THREAD_BITS - COMMAND_BITS - 2 to
C_SPLB_AWIDTH - MUTEX_BITS - THREAD_BITS - 3) := cmd;
return addr;
end function calc_high;
------------------------------------------
-- constants: figure out addresses of address ranges
------------------------------------------
constant LOCK_BASE:std_logic_vector(0 to C_SPLB_AWIDTH-1)
:= calc_base(SYNCH_LOCK);
constant LOCK_HIGH : std_logic_vector(0 to C_SPLB_AWIDTH-1)
:= calc_high(SYNCH_LOCK);
constant UNLOCK_BASE : std_logic_vector(0 to C_SPLB_AWIDTH-1)
:= calc_base(SYNCH_UNLOCK);
constant UNLOCK_HIGH : std_logic_vector(0 to C_SPLB_AWIDTH-1)
:= calc_high(SYNCH_UNLOCK);
constant TRY_BASE : std_logic_vector(0 to C_SPLB_AWIDTH-1)
:= calc_base(SYNCH_TRY);
constant TRY_HIGH : std_logic_vector(0 to C_SPLB_AWIDTH-1)
:= calc_high(SYNCH_TRY);
constant OWNER_BASE : std_logic_vector(0 to C_SPLB_AWIDTH-1)
:= calc_base(SYNCH_OWNER);
constant OWNER_HIGH : std_logic_vector(0 to C_SPLB_AWIDTH-1)
:= calc_high(SYNCH_OWNER);
constant KIND_BASE : std_logic_vector(0 to C_SPLB_AWIDTH-1)
:= calc_base(SYNCH_KIND);
constant KIND_HIGH : std_logic_vector(0 to C_SPLB_AWIDTH-1)
:= calc_high(SYNCH_KIND);
constant COUNT_BASE : std_logic_vector(0 to C_SPLB_AWIDTH-1)
:= calc_base(SYNCH_COUNT);
constant COUNT_HIGH : std_logic_vector(0 to C_SPLB_AWIDTH-1)
:= calc_high(SYNCH_COUNT);
constant RESULT_BASE : std_logic_vector(0 to C_SPLB_AWIDTH-1)
:= calc_base(SYNCH_RESULT);
constant RESULT_HIGH : std_logic_vector(0 to C_SPLB_AWIDTH-1)
:= calc_high(SYNCH_RESULT);
constant C_AR0_BASEADDR : std_logic_vector := LOCK_BASE;
constant C_AR0_HIGHADDR : std_logic_vector := LOCK_HIGH;
constant C_AR1_BASEADDR : std_logic_vector := UNLOCK_BASE;
constant C_AR1_HIGHADDR : std_logic_vector := UNLOCK_HIGH;
constant C_AR2_BASEADDR : std_logic_vector := TRY_BASE;
constant C_AR2_HIGHADDR : std_logic_vector := TRY_HIGH;
constant C_AR3_BASEADDR : std_logic_vector := OWNER_BASE;
constant C_AR3_HIGHADDR : std_logic_vector := OWNER_HIGH;
constant C_AR4_BASEADDR : std_logic_vector := KIND_BASE;
constant C_AR4_HIGHADDR : std_logic_vector := KIND_HIGH;
constant C_AR5_BASEADDR : std_logic_vector := COUNT_BASE;
constant C_AR5_HIGHADDR : std_logic_vector := COUNT_HIGH;
constant C_AR6_BASEADDR : std_logic_vector := RESULT_BASE;
constant C_AR6_HIGHADDR : std_logic_vector := RESULT_HIGH;
-- specify user logic address bus width, must be same as the target bus.
constant USER_AWIDTH : integer := C_SPLB_AWIDTH;
-- specify maximum data bus width among all user logic address ranges.
constant USER_DWIDTH : integer := 32;
-- specify number of user logic address ranges.
constant USER_NUM_ADDR_RNG : integer := 7;
-- specify number of user logic chip enables
constant USER_NUM_CE : integer := 1;
-- Signals for the system reset
signal master_resetdone : std_logic;
signal slave_resetdone : std_logic;
-- Signals for the master and slave interaction
signal send_ena : std_logic;
signal send_id : std_logic_vector(0 to log2(C_NUM_THREADS)-1);
signal send_ack : std_logic;
-- Signals for the send thread id store
signal siaddr : std_logic_vector(0 to log2(C_NUM_THREADS)-1);
signal siena : std_logic;
signal siwea : std_logic;
signal sinext : std_logic_vector(0 to log2(C_NUM_THREADS)-1);
signal sonext : std_logic_vector(0 to log2(C_NUM_THREADS)-1);
-------------------------------------------------------------------
-- END CODE COPIED FROM OPB SYNCH MANAGER
-------------------------------------------------------------------
------------------------------------------
-- Array of base/high address pairs for each address range
------------------------------------------
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
-- constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR or X"00000000";
-- constant USER_SLV_HIGHADDR : std_logic_vector := C_BASEADDR or X"000000FF";
-- constant USER_MST_BASEADDR : std_logic_vector := C_BASEADDR or X"00000100";
-- constant USER_MST_HIGHADDR : std_logic_vector := C_BASEADDR or X"000001FF";
--
-- constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
-- (
-- ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
-- ZERO_ADDR_PAD & USER_SLV_HIGHADDR, -- user logic slave space high address
-- ZERO_ADDR_PAD & USER_MST_BASEADDR, -- user logic master space base address
-- ZERO_ADDR_PAD & USER_MST_HIGHADDR -- user logic master space high address
-- );
-- ------------------------------------------
-- -- Array of desired number of chip enables for each address range
-- ------------------------------------------
constant USER_SLV_NUM_REG : integer := 1;
constant USER_MST_NUM_REG : integer := 4;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG+USER_MST_NUM_REG;
--
-- constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
-- (
-- 0 => pad_power2(USER_SLV_NUM_REG), -- number of ce for user logic slave space
-- 1 => pad_power2(USER_MST_NUM_REG) -- number of ce for user logic master space
-- );
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & C_AR0_BASEADDR, -- user logic address range 0 base address
ZERO_ADDR_PAD & C_AR0_HIGHADDR, -- user logic address range 0 high address
ZERO_ADDR_PAD & C_AR1_BASEADDR, -- user logic address range 1 base address
ZERO_ADDR_PAD & C_AR1_HIGHADDR, -- user logic address range 1 high address
ZERO_ADDR_PAD & C_AR2_BASEADDR, -- user logic address range 2 base address
ZERO_ADDR_PAD & C_AR2_HIGHADDR, -- user logic address range 2 high address
ZERO_ADDR_PAD & C_AR3_BASEADDR, -- user logic address range 3 base address
ZERO_ADDR_PAD & C_AR3_HIGHADDR, -- user logic address range 3 high address
ZERO_ADDR_PAD & C_AR4_BASEADDR, -- user logic address range 4 base address
ZERO_ADDR_PAD & C_AR4_HIGHADDR, -- user logic address range 4 high address
ZERO_ADDR_PAD & C_AR5_BASEADDR, -- user logic address range 5 base address
ZERO_ADDR_PAD & C_AR5_HIGHADDR, -- user logic address range 5 high address
ZERO_ADDR_PAD & C_AR6_BASEADDR, -- user logic address range 6 base address
ZERO_ADDR_PAD & C_AR6_HIGHADDR -- user logic address range 6 high address
);
-- specify desired number of chip enables for each address range,
-- typically one ce per register and each ipif service has its
-- predefined value.
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 1, -- user logic address range 0 bank (always 1 chip enable)
1 => 1, -- user logic address range 1 bank (always 1 chip enable)
2 => 1, -- user logic address range 2 bank (always 1 chip enable)
3 => 1, -- user logic address range 3 bank (always 1 chip enable)
4 => 1, -- user logic address range 4 bank (always 1 chip enable)
5 => 1, -- user logic address range 5 bank (always 1 chip enable)
6 => 1 -- user logic address range 6 bank (always 1 chip enable)
);
------------------------------------------
-- Ratio of bus clock to core clock (for use in dual clock systems)
-- 1 = ratio is 1:1
-- 2 = ratio is 2:1
------------------------------------------
constant IPIF_BUS2CORE_CLK_RATIO : integer := 1;
------------------------------------------
-- Width of the slave data bus (32 only)
------------------------------------------
constant USER_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
constant IPIF_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
------------------------------------------
-- Width of the master data bus (32 only)
------------------------------------------
constant USER_MST_DWIDTH : integer := C_MPLB_NATIVE_DWIDTH;
constant IPIF_MST_DWIDTH : integer := C_MPLB_NATIVE_DWIDTH;
------------------------------------------
-- Width of the master address bus (32 only)
------------------------------------------
constant USER_MST_AWIDTH : integer := C_MPLB_AWIDTH;
------------------------------------------
-- Index for CS/CE
------------------------------------------
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant USER_MST_CS_INDEX : integer := 1;
constant USER_MST_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_MST_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations
------------------------------------------
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Reset : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(0 to C_SPLB_AWIDTH-1);
signal ipif_Bus2IP_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(0 to IPIF_SLV_DWIDTH/8-1);
signal ipif_Bus2IP_CS : std_logic_vector(0 to ((IPIF_ARD_ADDR_RANGE_ARRAY'length)/2)-1);
signal ipif_Bus2IP_RdCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
signal ipif_Bus2IP_WrCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
signal ipif_IP2Bus_MstRd_Req : std_logic;
signal ipif_IP2Bus_MstWr_Req : std_logic;
signal ipif_IP2Bus_Mst_Addr : std_logic_vector(0 to C_MPLB_AWIDTH-1);
signal ipif_IP2Bus_Mst_BE : std_logic_vector(0 to C_MPLB_NATIVE_DWIDTH/8-1);
signal ipif_IP2Bus_Mst_Lock : std_logic;
signal ipif_IP2Bus_Mst_Reset : std_logic;
signal ipif_Bus2IP_Mst_CmdAck : std_logic;
signal ipif_Bus2IP_Mst_Cmplt : std_logic;
signal ipif_Bus2IP_Mst_Error : std_logic;
signal ipif_Bus2IP_Mst_Rearbitrate : std_logic;
signal ipif_Bus2IP_Mst_Cmd_Timeout : std_logic;
signal ipif_Bus2IP_MstRd_d : std_logic_vector(0 to C_MPLB_NATIVE_DWIDTH-1);
signal ipif_Bus2IP_MstRd_src_rdy_n : std_logic;
signal ipif_IP2Bus_MstWr_d : std_logic_vector(0 to C_MPLB_NATIVE_DWIDTH-1);
signal ipif_Bus2IP_MstWr_dst_rdy_n : std_logic;
signal user_Bus2IP_RdCE : std_logic_vector(0 to USER_NUM_REG-1);
signal user_Bus2IP_WrCE : std_logic_vector(0 to USER_NUM_REG-1);
signal user_IP2Bus_Data : std_logic_vector(0 to USER_SLV_DWIDTH-1);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
begin
------------------------------------------
-- instantiate plbv46_slave_single
------------------------------------------
PLBV46_SLAVE_SINGLE_I : entity plbv46_slave_single_v1_01_a.plbv46_slave_single
generic map
(
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_SPLB_P2P => C_SPLB_P2P,
C_BUS2CORE_CLK_RATIO => IPIF_BUS2CORE_CLK_RATIO,
C_SPLB_MID_WIDTH => C_SPLB_MID_WIDTH,
C_SPLB_NUM_MASTERS => C_SPLB_NUM_MASTERS,
C_SPLB_AWIDTH => C_SPLB_AWIDTH,
C_SPLB_DWIDTH => C_SPLB_DWIDTH,
C_SIPIF_DWIDTH => IPIF_SLV_DWIDTH,
C_INCLUDE_DPHASE_TIMER => C_INCLUDE_DPHASE_TIMER,
C_FAMILY => C_FAMILY
)
port map
(
SPLB_Clk => SPLB_Clk,
SPLB_Rst => SPLB_Rst,
PLB_ABus => PLB_ABus,
PLB_UABus => PLB_UABus,
PLB_PAValid => PLB_PAValid,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_masterID => PLB_masterID,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_MSize => PLB_MSize,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_lockErr => PLB_lockErr,
PLB_wrDBus => PLB_wrDBus,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendPri => PLB_rdPendPri,
PLB_reqPri => PLB_reqPri,
PLB_TAttribute => PLB_TAttribute,
Sl_addrAck => Sl_addrAck,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MBusy => Sl_MBusy,
Sl_MWrErr => Sl_MWrErr,
Sl_MRdErr => Sl_MRdErr,
Sl_MIRQ => Sl_MIRQ,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => ipif_Bus2IP_Reset,
IP2Bus_Data => ipif_IP2Bus_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE
);
------------------------------------------
-- instantiate plbv46_master_single
------------------------------------------
PLBV46_MASTER_SINGLE_I : entity plbv46_master_single_v1_01_a.plbv46_master_single
generic map
(
C_MPLB_AWIDTH => C_MPLB_AWIDTH,
C_MPLB_DWIDTH => C_MPLB_DWIDTH,
C_MPLB_NATIVE_DWIDTH => IPIF_MST_DWIDTH,
C_FAMILY => C_FAMILY
)
port map
(
MPLB_Clk => MPLB_Clk,
MPLB_Rst => MPLB_Rst,
MD_error => MD_error,
M_request => M_request,
M_priority => M_priority,
M_busLock => M_busLock,
M_RNW => M_RNW,
M_BE => M_BE,
M_MSize => M_MSize,
M_size => M_size,
M_type => M_type,
M_TAttribute => M_TAttribute,
M_lockErr => M_lockErr,
M_abort => M_abort,
M_UABus => M_UABus,
M_ABus => M_ABus,
M_wrDBus => M_wrDBus,
M_wrBurst => M_wrBurst,
M_rdBurst => M_rdBurst,
PLB_MAddrAck => PLB_MAddrAck,
PLB_MSSize => PLB_MSSize,
PLB_MRearbitrate => PLB_MRearbitrate,
PLB_MTimeout => PLB_MTimeout,
PLB_MBusy => PLB_MBusy,
PLB_MRdErr => PLB_MRdErr,
PLB_MWrErr => PLB_MWrErr,
PLB_MIRQ => PLB_MIRQ,
PLB_MRdDBus => PLB_MRdDBus,
PLB_MRdWdAddr => PLB_MRdWdAddr,
PLB_MRdDAck => PLB_MRdDAck,
PLB_MRdBTerm => PLB_MRdBTerm,
PLB_MWrDAck => PLB_MWrDAck,
PLB_MWrBTerm => PLB_MWrBTerm,
IP2Bus_MstRd_Req => ipif_IP2Bus_MstRd_Req,
IP2Bus_MstWr_Req => ipif_IP2Bus_MstWr_Req,
IP2Bus_Mst_Addr => ipif_IP2Bus_Mst_Addr,
IP2Bus_Mst_BE => ipif_IP2Bus_Mst_BE,
IP2Bus_Mst_Lock => ipif_IP2Bus_Mst_Lock,
IP2Bus_Mst_Reset => ipif_IP2Bus_Mst_Reset,
Bus2IP_Mst_CmdAck => ipif_Bus2IP_Mst_CmdAck,
Bus2IP_Mst_Cmplt => ipif_Bus2IP_Mst_Cmplt,
Bus2IP_Mst_Error => ipif_Bus2IP_Mst_Error,
Bus2IP_Mst_Rearbitrate => ipif_Bus2IP_Mst_Rearbitrate,
Bus2IP_Mst_Cmd_Timeout => ipif_Bus2IP_Mst_Cmd_Timeout,
Bus2IP_MstRd_d => ipif_Bus2IP_MstRd_d,
Bus2IP_MstRd_src_rdy_n => ipif_Bus2IP_MstRd_src_rdy_n,
IP2Bus_MstWr_d => ipif_IP2Bus_MstWr_d,
Bus2IP_MstWr_dst_rdy_n => ipif_Bus2IP_MstWr_dst_rdy_n
);
-- ------------------------------------------
-- -- instantiate User Logic
-- ------------------------------------------
-- USER_LOGIC_I : entity plb_sync_manager_v1_00_a.user_logic
-- generic map
-- (
-- -- MAP USER GENERICS BELOW THIS LINE ---------------
-- --USER generics mapped here
-- -- MAP USER GENERICS ABOVE THIS LINE ---------------
--
-- C_SLV_DWIDTH => USER_SLV_DWIDTH,
-- C_MST_AWIDTH => USER_MST_AWIDTH,
-- C_MST_DWIDTH => USER_MST_DWIDTH,
-- C_NUM_REG => USER_NUM_REG
-- )
-- port map
-- (
-- -- MAP USER PORTS BELOW THIS LINE ------------------
-- --USER ports mapped here
-- -- MAP USER PORTS ABOVE THIS LINE ------------------
--
-- Bus2IP_Clk => ipif_Bus2IP_Clk,
-- Bus2IP_Reset => ipif_Bus2IP_Reset,
-- Bus2IP_Addr => ipif_Bus2IP_Addr,
-- Bus2IP_CS => ipif_Bus2IP_CS,
-- Bus2IP_RNW => ipif_Bus2IP_RNW,
-- Bus2IP_Data => ipif_Bus2IP_Data,
-- Bus2IP_BE => ipif_Bus2IP_BE,
-- Bus2IP_RdCE => user_Bus2IP_RdCE,
-- Bus2IP_WrCE => user_Bus2IP_WrCE,
-- IP2Bus_Data => user_IP2Bus_Data,
-- IP2Bus_RdAck => user_IP2Bus_RdAck,
-- IP2Bus_WrAck => user_IP2Bus_WrAck,
-- IP2Bus_Error => user_IP2Bus_Error,
-- IP2Bus_MstRd_Req => ipif_IP2Bus_MstRd_Req,
-- IP2Bus_MstWr_Req => ipif_IP2Bus_MstWr_Req,
-- IP2Bus_Mst_Addr => ipif_IP2Bus_Mst_Addr,
-- IP2Bus_Mst_BE => ipif_IP2Bus_Mst_BE,
-- IP2Bus_Mst_Lock => ipif_IP2Bus_Mst_Lock,
-- IP2Bus_Mst_Reset => ipif_IP2Bus_Mst_Reset,
-- Bus2IP_Mst_CmdAck => ipif_Bus2IP_Mst_CmdAck,
-- Bus2IP_Mst_Cmplt => ipif_Bus2IP_Mst_Cmplt,
-- Bus2IP_Mst_Error => ipif_Bus2IP_Mst_Error,
-- Bus2IP_Mst_Rearbitrate => ipif_Bus2IP_Mst_Rearbitrate,
-- Bus2IP_Mst_Cmd_Timeout => ipif_Bus2IP_Mst_Cmd_Timeout,
-- Bus2IP_MstRd_d => ipif_Bus2IP_MstRd_d,
-- Bus2IP_MstRd_src_rdy_n => ipif_Bus2IP_MstRd_src_rdy_n,
-- IP2Bus_MstWr_d => ipif_IP2Bus_MstWr_d,
-- Bus2IP_MstWr_dst_rdy_n => ipif_Bus2IP_MstWr_dst_rdy_n
-- );
--------------------------------------------------------------------------
-- Instantiate the Slave Logic
--------------------------------------------------------------------------
slave_logic_i : entity work.slave
generic map
(
C_NUM_THREADS => C_NUM_THREADS,
C_NUM_MUTEXES => C_NUM_MUTEXES,
C_AWIDTH => USER_AWIDTH,
C_DWIDTH => USER_DWIDTH,
C_MAX_AR_DWIDTH => USER_DWIDTH,
C_NUM_ADDR_RNG => USER_NUM_ADDR_RNG,
C_NUM_CE => USER_NUM_CE
)
port map
(
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => ipif_Bus2IP_Reset,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RNW => ipif_Bus2IP_RNW,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_Error => user_IP2Bus_Error,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
system_reset => system_reset,
system_resetdone => slave_resetdone,
send_ena => send_ena,
send_id => send_id,
send_ack => send_ack,
siaddr => siaddr,
siena => siena,
siwea => siwea,
sinext => sinext,
sonext => sonext
);
--------------------------------------------------------------------------
-- Instantiate the Master Logic
--------------------------------------------------------------------------
master_logic_i : entity work.master
generic map
(
C_BASEADDR => C_BASEADDR,
C_HIGHADDR => C_HIGHADDR,
C_SCHED_BASEADDR => C_SCHED_BADDR,
C_RESULT_BASEADDR => RESULT_BASE,
C_NUM_THREADS => C_NUM_THREADS,
C_NUM_MUTEXES => C_NUM_MUTEXES,
C_AWIDTH => USER_AWIDTH,
C_DWIDTH => USER_DWIDTH,
C_MAX_AR_DWIDTH => USER_DWIDTH,
C_NUM_ADDR_RNG => USER_NUM_ADDR_RNG,
C_NUM_CE => USER_NUM_CE
)
port map
(
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => ipif_Bus2IP_Reset,
-- Bus2IP_Addr => iBus2IP_Addr,
-- Bus2IP_Data => uBus2IP_Data,
-- Bus2IP_BE => uBus2IP_BE,
-- Bus2IP_RNW => iBus2IP_RNW,
-- Bus2IP_RdCE => uBus2IP_RdCE,
-- Bus2IP_WrCE => uBus2IP_WrCE,
-- Bus2IP_RdReq => iBus2IP_RdReq,
-- Bus2IP_WrReq => iBus2IP_WrReq,
-- Bus2IP_MstError => iBus2IP_MstError,
-- Bus2IP_MstLastAck => iBus2IP_MstLastAck,
-- Bus2IP_MstRdAck => iBus2IP_MstRdAck,
-- Bus2IP_MstWrAck => iBus2IP_MstWrAck,
-- Bus2IP_MstRetry => iBus2IP_MstRetry,
-- Bus2IP_MstTimeOut => iBus2IP_MstTimeOut,
-- IP2Bus_Addr => iIP2Bus_Addr,
-- IP2Bus_MstBE => uIP2Bus_MstBE,
-- IP2Bus_MstBurst => iIP2Bus_MstBurst,
-- IP2Bus_MstBusLock => iIP2Bus_MstBusLock,
-- IP2Bus_MstRdReq => iIP2Bus_MstRdReq,
-- IP2Bus_MstWrReq => iIP2Bus_MstWrReq,
-- IP2IP_Addr => iIP2IP_Addr,
IP2Bus_MstRd_Req => ipif_IP2Bus_MstRd_Req,
IP2Bus_MstWr_Req => ipif_IP2Bus_MstWr_Req,
IP2Bus_Mst_Addr => ipif_IP2Bus_Mst_Addr,
IP2Bus_Mst_BE => ipif_IP2Bus_Mst_BE,
IP2Bus_Mst_Lock => ipif_IP2Bus_Mst_Lock,
IP2Bus_Mst_Reset => ipif_IP2Bus_Mst_Reset,
Bus2IP_Mst_CmdAck => ipif_Bus2IP_Mst_CmdAck,
Bus2IP_Mst_Cmplt => ipif_Bus2IP_Mst_Cmplt,
Bus2IP_Mst_Error => ipif_Bus2IP_Mst_Error,
Bus2IP_Mst_Rearbitrate => ipif_Bus2IP_Mst_Rearbitrate,
Bus2IP_Mst_Cmd_Timeout => ipif_Bus2IP_Mst_Cmd_Timeout,
Bus2IP_MstRd_d => ipif_Bus2IP_MstRd_d,
Bus2IP_MstRd_src_rdy_n => ipif_Bus2IP_MstRd_src_rdy_n,
IP2Bus_MstWr_d => ipif_IP2Bus_MstWr_d,
Bus2IP_MstWr_dst_rdy_n => ipif_Bus2IP_MstWr_dst_rdy_n,
system_reset => system_reset,
system_resetdone => master_resetdone,
send_ena => send_ena,
send_id => send_id,
send_ack => send_ack,
saddr => siaddr,
sena => siena,
swea => siwea,
sonext => sinext,
sinext => sonext
);
------------------------------------------
-- connect internal signals
------------------------------------------
-- IP2BUS_DATA_MUX_PROC : process( ipif_Bus2IP_CS, user_IP2Bus_Data ) is
-- begin
--
-- case ipif_Bus2IP_CS is
-- when "10" => ipif_IP2Bus_Data <= user_IP2Bus_Data;
-- when "01" => ipif_IP2Bus_Data <= user_IP2Bus_Data;
-- when others => ipif_IP2Bus_Data <= (others => '0');
-- end case;
--
-- end process IP2BUS_DATA_MUX_PROC;
ipif_IP2Bus_Data <= user_IP2Bus_Data;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;
user_Bus2IP_RdCE(0 to USER_SLV_NUM_REG-1) <= ipif_Bus2IP_RdCE(USER_SLV_CE_INDEX to USER_SLV_CE_INDEX+USER_SLV_NUM_REG-1);
user_Bus2IP_RdCE(USER_SLV_NUM_REG to USER_NUM_REG-1) <= ipif_Bus2IP_RdCE(USER_MST_CE_INDEX to USER_MST_CE_INDEX+USER_MST_NUM_REG-1);
user_Bus2IP_WrCE(0 to USER_SLV_NUM_REG-1) <= ipif_Bus2IP_WrCE(USER_SLV_CE_INDEX to USER_SLV_CE_INDEX+USER_SLV_NUM_REG-1);
user_Bus2IP_WrCE(USER_SLV_NUM_REG to USER_NUM_REG-1) <= ipif_Bus2IP_WrCE(USER_MST_CE_INDEX to USER_MST_CE_INDEX+USER_MST_NUM_REG-1);
------------------------------------------
-- hooking reset done signals
------------------------------------------
system_resetdone <= master_resetdone and slave_resetdone;
end IMP;
|
bsd-3-clause
|
masson2013/heterogeneous_hthreads
|
src/hardware/MyRepository/pcores/plb_sync_manager_v1_00_a/hdl/vhdl/plb_sync_manager.vhd
|
9
|
47769
|
------------------------------------------------------------------------------
-- plb_sync_manager.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: plb_sync_manager.vhd
-- Version: 1.00.a
-- Description: Top level design, instantiates library components and user logic.
-- Date: Thu May 7 14:29:05 2009 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library plbv46_slave_single_v1_01_a;
use plbv46_slave_single_v1_01_a.plbv46_slave_single;
library plbv46_master_single_v1_01_a;
use plbv46_master_single_v1_01_a.plbv46_master_single;
library plb_sync_manager_v1_00_a;
use plb_sync_manager_v1_00_a.user_logic;
use work.common.SYNCH_LOCK;
use work.common.SYNCH_UNLOCK;
use work.common.SYNCH_TRY;
use work.common.SYNCH_OWNER;
use work.common.SYNCH_KIND;
use work.common.SYNCH_COUNT;
use work.common.SYNCH_RESULT;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_BASEADDR -- PLBv46 slave: base address
-- C_HIGHADDR -- PLBv46 slave: high address
-- C_SPLB_AWIDTH -- PLBv46 slave: address bus width
-- C_SPLB_DWIDTH -- PLBv46 slave: data bus width
-- C_SPLB_NUM_MASTERS -- PLBv46 slave: Number of masters
-- C_SPLB_MID_WIDTH -- PLBv46 slave: master ID bus width
-- C_SPLB_NATIVE_DWIDTH -- PLBv46 slave: internal native data bus width
-- C_SPLB_P2P -- PLBv46 slave: point to point interconnect scheme
-- C_SPLB_SUPPORT_BURSTS -- PLBv46 slave: support bursts
-- C_SPLB_SMALLEST_MASTER -- PLBv46 slave: width of the smallest master
-- C_SPLB_CLK_PERIOD_PS -- PLBv46 slave: bus clock in picoseconds
-- C_INCLUDE_DPHASE_TIMER -- PLBv46 slave: Data Phase Timer configuration; 0 = exclude timer, 1 = include timer
-- C_FAMILY -- Xilinx FPGA family
-- C_MPLB_AWIDTH -- PLBv46 master: address bus width
-- C_MPLB_DWIDTH -- PLBv46 master: data bus width
-- C_MPLB_NATIVE_DWIDTH -- PLBv46 master: internal native data width
-- C_MPLB_P2P -- PLBv46 master: point to point interconnect scheme
-- C_MPLB_SMALLEST_SLAVE -- PLBv46 master: width of the smallest slave
-- C_MPLB_CLK_PERIOD_PS -- PLBv46 master: bus clock in picoseconds
--
-- Definition of Ports:
-- SPLB_Clk -- PLB main bus clock
-- SPLB_Rst -- PLB main bus reset
-- PLB_ABus -- PLB address bus
-- PLB_UABus -- PLB upper address bus
-- PLB_PAValid -- PLB primary address valid indicator
-- PLB_SAValid -- PLB secondary address valid indicator
-- PLB_rdPrim -- PLB secondary to primary read request indicator
-- PLB_wrPrim -- PLB secondary to primary write request indicator
-- PLB_masterID -- PLB current master identifier
-- PLB_abort -- PLB abort request indicator
-- PLB_busLock -- PLB bus lock
-- PLB_RNW -- PLB read/not write
-- PLB_BE -- PLB byte enables
-- PLB_MSize -- PLB master data bus size
-- PLB_size -- PLB transfer size
-- PLB_type -- PLB transfer type
-- PLB_lockErr -- PLB lock error indicator
-- PLB_wrDBus -- PLB write data bus
-- PLB_wrBurst -- PLB burst write transfer indicator
-- PLB_rdBurst -- PLB burst read transfer indicator
-- PLB_wrPendReq -- PLB write pending bus request indicator
-- PLB_rdPendReq -- PLB read pending bus request indicator
-- PLB_wrPendPri -- PLB write pending request priority
-- PLB_rdPendPri -- PLB read pending request priority
-- PLB_reqPri -- PLB current request priority
-- PLB_TAttribute -- PLB transfer attribute
-- Sl_addrAck -- Slave address acknowledge
-- Sl_SSize -- Slave data bus size
-- Sl_wait -- Slave wait indicator
-- Sl_rearbitrate -- Slave re-arbitrate bus indicator
-- Sl_wrDAck -- Slave write data acknowledge
-- Sl_wrComp -- Slave write transfer complete indicator
-- Sl_wrBTerm -- Slave terminate write burst transfer
-- Sl_rdDBus -- Slave read data bus
-- Sl_rdWdAddr -- Slave read word address
-- Sl_rdDAck -- Slave read data acknowledge
-- Sl_rdComp -- Slave read transfer complete indicator
-- Sl_rdBTerm -- Slave terminate read burst transfer
-- Sl_MBusy -- Slave busy indicator
-- Sl_MWrErr -- Slave write error indicator
-- Sl_MRdErr -- Slave read error indicator
-- Sl_MIRQ -- Slave interrupt indicator
-- MPLB_Clk -- PLB main bus Clock
-- MPLB_Rst -- PLB main bus Reset
-- MD_error -- Master detected error status output
-- M_request -- Master request
-- M_priority -- Master request priority
-- M_busLock -- Master buslock
-- M_RNW -- Master read/nor write
-- M_BE -- Master byte enables
-- M_MSize -- Master data bus size
-- M_size -- Master transfer size
-- M_type -- Master transfer type
-- M_TAttribute -- Master transfer attribute
-- M_lockErr -- Master lock error indicator
-- M_abort -- Master abort bus request indicator
-- M_UABus -- Master upper address bus
-- M_ABus -- Master address bus
-- M_wrDBus -- Master write data bus
-- M_wrBurst -- Master burst write transfer indicator
-- M_rdBurst -- Master burst read transfer indicator
-- PLB_MAddrAck -- PLB reply to master for address acknowledge
-- PLB_MSSize -- PLB reply to master for slave data bus size
-- PLB_MRearbitrate -- PLB reply to master for bus re-arbitrate indicator
-- PLB_MTimeout -- PLB reply to master for bus time out indicator
-- PLB_MBusy -- PLB reply to master for slave busy indicator
-- PLB_MRdErr -- PLB reply to master for slave read error indicator
-- PLB_MWrErr -- PLB reply to master for slave write error indicator
-- PLB_MIRQ -- PLB reply to master for slave interrupt indicator
-- PLB_MRdDBus -- PLB reply to master for read data bus
-- PLB_MRdWdAddr -- PLB reply to master for read word address
-- PLB_MRdDAck -- PLB reply to master for read data acknowledge
-- PLB_MRdBTerm -- PLB reply to master for terminate read burst indicator
-- PLB_MWrDAck -- PLB reply to master for write data acknowledge
-- PLB_MWrBTerm -- PLB reply to master for terminate write burst indicator
------------------------------------------------------------------------------
entity plb_sync_manager is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
C_NUM_THREADS : integer := 256;
C_NUM_MUTEXES : integer := 64;
C_SCHED_BADDR : std_logic_vector := X"00000000";
C_SCHED_HADDR : std_logic_vector := X"00000000";
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_SPLB_AWIDTH : integer := 32;
C_SPLB_DWIDTH : integer := 128;
C_SPLB_NUM_MASTERS : integer := 8;
C_SPLB_MID_WIDTH : integer := 3;
C_SPLB_NATIVE_DWIDTH : integer := 32;
C_SPLB_P2P : integer := 0;
C_SPLB_SUPPORT_BURSTS : integer := 0;
C_SPLB_SMALLEST_MASTER : integer := 32;
C_SPLB_CLK_PERIOD_PS : integer := 10000;
C_INCLUDE_DPHASE_TIMER : integer := 0;
C_FAMILY : string := "virtex5";
C_MPLB_AWIDTH : integer := 32;
C_MPLB_DWIDTH : integer := 128;
C_MPLB_NATIVE_DWIDTH : integer := 32;
C_MPLB_P2P : integer := 0;
C_MPLB_SMALLEST_SLAVE : integer := 32;
C_MPLB_CLK_PERIOD_PS : integer := 10000
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
system_reset : in std_logic;
system_resetdone : out std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to C_SPLB_MID_WIDTH-1);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to C_SPLB_DWIDTH/8-1);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to C_SPLB_DWIDTH-1);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to C_SPLB_DWIDTH-1);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MWrErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MRdErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MIRQ : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
MPLB_Clk : in std_logic;
MPLB_Rst : in std_logic;
MD_error : out std_logic;
M_request : out std_logic;
M_priority : out std_logic_vector(0 to 1);
M_busLock : out std_logic;
M_RNW : out std_logic;
M_BE : out std_logic_vector(0 to C_MPLB_DWIDTH/8-1);
M_MSize : out std_logic_vector(0 to 1);
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_TAttribute : out std_logic_vector(0 to 15);
M_lockErr : out std_logic;
M_abort : out std_logic;
M_UABus : out std_logic_vector(0 to 31);
M_ABus : out std_logic_vector(0 to 31);
M_wrDBus : out std_logic_vector(0 to C_MPLB_DWIDTH-1);
M_wrBurst : out std_logic;
M_rdBurst : out std_logic;
PLB_MAddrAck : in std_logic;
PLB_MSSize : in std_logic_vector(0 to 1);
PLB_MRearbitrate : in std_logic;
PLB_MTimeout : in std_logic;
PLB_MBusy : in std_logic;
PLB_MRdErr : in std_logic;
PLB_MWrErr : in std_logic;
PLB_MIRQ : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to (C_MPLB_DWIDTH-1));
PLB_MRdWdAddr : in std_logic_vector(0 to 3);
PLB_MRdDAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MWrBTerm : in std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of SPLB_Clk : signal is "CLK";
attribute SIGIS of MPLB_Clk : signal is "CLK";
attribute SIGIS of SPLB_Rst : signal is "RST";
attribute SIGIS of MPLB_Rst : signal is "RST";
end entity plb_sync_manager;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of plb_sync_manager is
-------------------------------------------------------------------
-- BEGIN CODE COPIED FROM OPB SYNCH MANAGER
-------------------------------------------------------------------
-- Constants for the number of bits needed to represent certain data
constant MUTEX_BITS : integer := log2(C_NUM_MUTEXES);
constant THREAD_BITS : integer := log2(C_NUM_THREADS);
constant KIND_BITS : integer := 2;
constant COUNT_BITS : integer := 8;
constant COMMAND_BITS : integer := 3;
function calc_base( cmd : in std_logic_vector(0 to COMMAND_BITS-1) )
return std_logic_vector is
variable addr : std_logic_vector(0 to C_SPLB_AWIDTH - 1);
begin
addr := C_BASEADDR;
addr(C_SPLB_AWIDTH - MUTEX_BITS - THREAD_BITS - COMMAND_BITS - 2 to
C_SPLB_AWIDTH - MUTEX_BITS - THREAD_BITS - 3) := cmd;
return addr;
end function calc_base;
function calc_high( cmd : in std_logic_vector(0 to COMMAND_BITS-1) )
return std_logic_vector is
variable addr : std_logic_vector(0 to C_SPLB_AWIDTH - 1);
begin
addr := C_BASEADDR;
addr(C_SPLB_AWIDTH - MUTEX_BITS - 2 to
C_SPLB_AWIDTH - 3) := (others => '1');
addr(C_SPLB_AWIDTH - MUTEX_BITS - THREAD_BITS - 2 to
C_SPLB_AWIDTH - MUTEX_BITS - 3) := (others => '1');
addr(C_SPLB_AWIDTH - MUTEX_BITS - THREAD_BITS - COMMAND_BITS - 2 to
C_SPLB_AWIDTH - MUTEX_BITS - THREAD_BITS - 3) := cmd;
return addr;
end function calc_high;
------------------------------------------
-- constants: figure out addresses of address ranges
------------------------------------------
constant LOCK_BASE:std_logic_vector(0 to C_SPLB_AWIDTH-1)
:= calc_base(SYNCH_LOCK);
constant LOCK_HIGH : std_logic_vector(0 to C_SPLB_AWIDTH-1)
:= calc_high(SYNCH_LOCK);
constant UNLOCK_BASE : std_logic_vector(0 to C_SPLB_AWIDTH-1)
:= calc_base(SYNCH_UNLOCK);
constant UNLOCK_HIGH : std_logic_vector(0 to C_SPLB_AWIDTH-1)
:= calc_high(SYNCH_UNLOCK);
constant TRY_BASE : std_logic_vector(0 to C_SPLB_AWIDTH-1)
:= calc_base(SYNCH_TRY);
constant TRY_HIGH : std_logic_vector(0 to C_SPLB_AWIDTH-1)
:= calc_high(SYNCH_TRY);
constant OWNER_BASE : std_logic_vector(0 to C_SPLB_AWIDTH-1)
:= calc_base(SYNCH_OWNER);
constant OWNER_HIGH : std_logic_vector(0 to C_SPLB_AWIDTH-1)
:= calc_high(SYNCH_OWNER);
constant KIND_BASE : std_logic_vector(0 to C_SPLB_AWIDTH-1)
:= calc_base(SYNCH_KIND);
constant KIND_HIGH : std_logic_vector(0 to C_SPLB_AWIDTH-1)
:= calc_high(SYNCH_KIND);
constant COUNT_BASE : std_logic_vector(0 to C_SPLB_AWIDTH-1)
:= calc_base(SYNCH_COUNT);
constant COUNT_HIGH : std_logic_vector(0 to C_SPLB_AWIDTH-1)
:= calc_high(SYNCH_COUNT);
constant RESULT_BASE : std_logic_vector(0 to C_SPLB_AWIDTH-1)
:= calc_base(SYNCH_RESULT);
constant RESULT_HIGH : std_logic_vector(0 to C_SPLB_AWIDTH-1)
:= calc_high(SYNCH_RESULT);
constant C_AR0_BASEADDR : std_logic_vector := LOCK_BASE;
constant C_AR0_HIGHADDR : std_logic_vector := LOCK_HIGH;
constant C_AR1_BASEADDR : std_logic_vector := UNLOCK_BASE;
constant C_AR1_HIGHADDR : std_logic_vector := UNLOCK_HIGH;
constant C_AR2_BASEADDR : std_logic_vector := TRY_BASE;
constant C_AR2_HIGHADDR : std_logic_vector := TRY_HIGH;
constant C_AR3_BASEADDR : std_logic_vector := OWNER_BASE;
constant C_AR3_HIGHADDR : std_logic_vector := OWNER_HIGH;
constant C_AR4_BASEADDR : std_logic_vector := KIND_BASE;
constant C_AR4_HIGHADDR : std_logic_vector := KIND_HIGH;
constant C_AR5_BASEADDR : std_logic_vector := COUNT_BASE;
constant C_AR5_HIGHADDR : std_logic_vector := COUNT_HIGH;
constant C_AR6_BASEADDR : std_logic_vector := RESULT_BASE;
constant C_AR6_HIGHADDR : std_logic_vector := RESULT_HIGH;
-- specify user logic address bus width, must be same as the target bus.
constant USER_AWIDTH : integer := C_SPLB_AWIDTH;
-- specify maximum data bus width among all user logic address ranges.
constant USER_DWIDTH : integer := 32;
-- specify number of user logic address ranges.
constant USER_NUM_ADDR_RNG : integer := 7;
-- specify number of user logic chip enables
constant USER_NUM_CE : integer := 1;
-- Signals for the system reset
signal master_resetdone : std_logic;
signal slave_resetdone : std_logic;
-- Signals for the master and slave interaction
signal send_ena : std_logic;
signal send_id : std_logic_vector(0 to log2(C_NUM_THREADS)-1);
signal send_ack : std_logic;
-- Signals for the send thread id store
signal siaddr : std_logic_vector(0 to log2(C_NUM_THREADS)-1);
signal siena : std_logic;
signal siwea : std_logic;
signal sinext : std_logic_vector(0 to log2(C_NUM_THREADS)-1);
signal sonext : std_logic_vector(0 to log2(C_NUM_THREADS)-1);
-------------------------------------------------------------------
-- END CODE COPIED FROM OPB SYNCH MANAGER
-------------------------------------------------------------------
------------------------------------------
-- Array of base/high address pairs for each address range
------------------------------------------
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
-- constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR or X"00000000";
-- constant USER_SLV_HIGHADDR : std_logic_vector := C_BASEADDR or X"000000FF";
-- constant USER_MST_BASEADDR : std_logic_vector := C_BASEADDR or X"00000100";
-- constant USER_MST_HIGHADDR : std_logic_vector := C_BASEADDR or X"000001FF";
--
-- constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
-- (
-- ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
-- ZERO_ADDR_PAD & USER_SLV_HIGHADDR, -- user logic slave space high address
-- ZERO_ADDR_PAD & USER_MST_BASEADDR, -- user logic master space base address
-- ZERO_ADDR_PAD & USER_MST_HIGHADDR -- user logic master space high address
-- );
-- ------------------------------------------
-- -- Array of desired number of chip enables for each address range
-- ------------------------------------------
constant USER_SLV_NUM_REG : integer := 1;
constant USER_MST_NUM_REG : integer := 4;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG+USER_MST_NUM_REG;
--
-- constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
-- (
-- 0 => pad_power2(USER_SLV_NUM_REG), -- number of ce for user logic slave space
-- 1 => pad_power2(USER_MST_NUM_REG) -- number of ce for user logic master space
-- );
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & C_AR0_BASEADDR, -- user logic address range 0 base address
ZERO_ADDR_PAD & C_AR0_HIGHADDR, -- user logic address range 0 high address
ZERO_ADDR_PAD & C_AR1_BASEADDR, -- user logic address range 1 base address
ZERO_ADDR_PAD & C_AR1_HIGHADDR, -- user logic address range 1 high address
ZERO_ADDR_PAD & C_AR2_BASEADDR, -- user logic address range 2 base address
ZERO_ADDR_PAD & C_AR2_HIGHADDR, -- user logic address range 2 high address
ZERO_ADDR_PAD & C_AR3_BASEADDR, -- user logic address range 3 base address
ZERO_ADDR_PAD & C_AR3_HIGHADDR, -- user logic address range 3 high address
ZERO_ADDR_PAD & C_AR4_BASEADDR, -- user logic address range 4 base address
ZERO_ADDR_PAD & C_AR4_HIGHADDR, -- user logic address range 4 high address
ZERO_ADDR_PAD & C_AR5_BASEADDR, -- user logic address range 5 base address
ZERO_ADDR_PAD & C_AR5_HIGHADDR, -- user logic address range 5 high address
ZERO_ADDR_PAD & C_AR6_BASEADDR, -- user logic address range 6 base address
ZERO_ADDR_PAD & C_AR6_HIGHADDR -- user logic address range 6 high address
);
-- specify desired number of chip enables for each address range,
-- typically one ce per register and each ipif service has its
-- predefined value.
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 1, -- user logic address range 0 bank (always 1 chip enable)
1 => 1, -- user logic address range 1 bank (always 1 chip enable)
2 => 1, -- user logic address range 2 bank (always 1 chip enable)
3 => 1, -- user logic address range 3 bank (always 1 chip enable)
4 => 1, -- user logic address range 4 bank (always 1 chip enable)
5 => 1, -- user logic address range 5 bank (always 1 chip enable)
6 => 1 -- user logic address range 6 bank (always 1 chip enable)
);
------------------------------------------
-- Ratio of bus clock to core clock (for use in dual clock systems)
-- 1 = ratio is 1:1
-- 2 = ratio is 2:1
------------------------------------------
constant IPIF_BUS2CORE_CLK_RATIO : integer := 1;
------------------------------------------
-- Width of the slave data bus (32 only)
------------------------------------------
constant USER_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
constant IPIF_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
------------------------------------------
-- Width of the master data bus (32 only)
------------------------------------------
constant USER_MST_DWIDTH : integer := C_MPLB_NATIVE_DWIDTH;
constant IPIF_MST_DWIDTH : integer := C_MPLB_NATIVE_DWIDTH;
------------------------------------------
-- Width of the master address bus (32 only)
------------------------------------------
constant USER_MST_AWIDTH : integer := C_MPLB_AWIDTH;
------------------------------------------
-- Index for CS/CE
------------------------------------------
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant USER_MST_CS_INDEX : integer := 1;
constant USER_MST_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_MST_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations
------------------------------------------
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Reset : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(0 to C_SPLB_AWIDTH-1);
signal ipif_Bus2IP_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(0 to IPIF_SLV_DWIDTH/8-1);
signal ipif_Bus2IP_CS : std_logic_vector(0 to ((IPIF_ARD_ADDR_RANGE_ARRAY'length)/2)-1);
signal ipif_Bus2IP_RdCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
signal ipif_Bus2IP_WrCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
signal ipif_IP2Bus_MstRd_Req : std_logic;
signal ipif_IP2Bus_MstWr_Req : std_logic;
signal ipif_IP2Bus_Mst_Addr : std_logic_vector(0 to C_MPLB_AWIDTH-1);
signal ipif_IP2Bus_Mst_BE : std_logic_vector(0 to C_MPLB_NATIVE_DWIDTH/8-1);
signal ipif_IP2Bus_Mst_Lock : std_logic;
signal ipif_IP2Bus_Mst_Reset : std_logic;
signal ipif_Bus2IP_Mst_CmdAck : std_logic;
signal ipif_Bus2IP_Mst_Cmplt : std_logic;
signal ipif_Bus2IP_Mst_Error : std_logic;
signal ipif_Bus2IP_Mst_Rearbitrate : std_logic;
signal ipif_Bus2IP_Mst_Cmd_Timeout : std_logic;
signal ipif_Bus2IP_MstRd_d : std_logic_vector(0 to C_MPLB_NATIVE_DWIDTH-1);
signal ipif_Bus2IP_MstRd_src_rdy_n : std_logic;
signal ipif_IP2Bus_MstWr_d : std_logic_vector(0 to C_MPLB_NATIVE_DWIDTH-1);
signal ipif_Bus2IP_MstWr_dst_rdy_n : std_logic;
signal user_Bus2IP_RdCE : std_logic_vector(0 to USER_NUM_REG-1);
signal user_Bus2IP_WrCE : std_logic_vector(0 to USER_NUM_REG-1);
signal user_IP2Bus_Data : std_logic_vector(0 to USER_SLV_DWIDTH-1);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
begin
------------------------------------------
-- instantiate plbv46_slave_single
------------------------------------------
PLBV46_SLAVE_SINGLE_I : entity plbv46_slave_single_v1_01_a.plbv46_slave_single
generic map
(
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_SPLB_P2P => C_SPLB_P2P,
C_BUS2CORE_CLK_RATIO => IPIF_BUS2CORE_CLK_RATIO,
C_SPLB_MID_WIDTH => C_SPLB_MID_WIDTH,
C_SPLB_NUM_MASTERS => C_SPLB_NUM_MASTERS,
C_SPLB_AWIDTH => C_SPLB_AWIDTH,
C_SPLB_DWIDTH => C_SPLB_DWIDTH,
C_SIPIF_DWIDTH => IPIF_SLV_DWIDTH,
C_INCLUDE_DPHASE_TIMER => C_INCLUDE_DPHASE_TIMER,
C_FAMILY => C_FAMILY
)
port map
(
SPLB_Clk => SPLB_Clk,
SPLB_Rst => SPLB_Rst,
PLB_ABus => PLB_ABus,
PLB_UABus => PLB_UABus,
PLB_PAValid => PLB_PAValid,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_masterID => PLB_masterID,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_MSize => PLB_MSize,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_lockErr => PLB_lockErr,
PLB_wrDBus => PLB_wrDBus,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendPri => PLB_rdPendPri,
PLB_reqPri => PLB_reqPri,
PLB_TAttribute => PLB_TAttribute,
Sl_addrAck => Sl_addrAck,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MBusy => Sl_MBusy,
Sl_MWrErr => Sl_MWrErr,
Sl_MRdErr => Sl_MRdErr,
Sl_MIRQ => Sl_MIRQ,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => ipif_Bus2IP_Reset,
IP2Bus_Data => ipif_IP2Bus_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE
);
------------------------------------------
-- instantiate plbv46_master_single
------------------------------------------
PLBV46_MASTER_SINGLE_I : entity plbv46_master_single_v1_01_a.plbv46_master_single
generic map
(
C_MPLB_AWIDTH => C_MPLB_AWIDTH,
C_MPLB_DWIDTH => C_MPLB_DWIDTH,
C_MPLB_NATIVE_DWIDTH => IPIF_MST_DWIDTH,
C_FAMILY => C_FAMILY
)
port map
(
MPLB_Clk => MPLB_Clk,
MPLB_Rst => MPLB_Rst,
MD_error => MD_error,
M_request => M_request,
M_priority => M_priority,
M_busLock => M_busLock,
M_RNW => M_RNW,
M_BE => M_BE,
M_MSize => M_MSize,
M_size => M_size,
M_type => M_type,
M_TAttribute => M_TAttribute,
M_lockErr => M_lockErr,
M_abort => M_abort,
M_UABus => M_UABus,
M_ABus => M_ABus,
M_wrDBus => M_wrDBus,
M_wrBurst => M_wrBurst,
M_rdBurst => M_rdBurst,
PLB_MAddrAck => PLB_MAddrAck,
PLB_MSSize => PLB_MSSize,
PLB_MRearbitrate => PLB_MRearbitrate,
PLB_MTimeout => PLB_MTimeout,
PLB_MBusy => PLB_MBusy,
PLB_MRdErr => PLB_MRdErr,
PLB_MWrErr => PLB_MWrErr,
PLB_MIRQ => PLB_MIRQ,
PLB_MRdDBus => PLB_MRdDBus,
PLB_MRdWdAddr => PLB_MRdWdAddr,
PLB_MRdDAck => PLB_MRdDAck,
PLB_MRdBTerm => PLB_MRdBTerm,
PLB_MWrDAck => PLB_MWrDAck,
PLB_MWrBTerm => PLB_MWrBTerm,
IP2Bus_MstRd_Req => ipif_IP2Bus_MstRd_Req,
IP2Bus_MstWr_Req => ipif_IP2Bus_MstWr_Req,
IP2Bus_Mst_Addr => ipif_IP2Bus_Mst_Addr,
IP2Bus_Mst_BE => ipif_IP2Bus_Mst_BE,
IP2Bus_Mst_Lock => ipif_IP2Bus_Mst_Lock,
IP2Bus_Mst_Reset => ipif_IP2Bus_Mst_Reset,
Bus2IP_Mst_CmdAck => ipif_Bus2IP_Mst_CmdAck,
Bus2IP_Mst_Cmplt => ipif_Bus2IP_Mst_Cmplt,
Bus2IP_Mst_Error => ipif_Bus2IP_Mst_Error,
Bus2IP_Mst_Rearbitrate => ipif_Bus2IP_Mst_Rearbitrate,
Bus2IP_Mst_Cmd_Timeout => ipif_Bus2IP_Mst_Cmd_Timeout,
Bus2IP_MstRd_d => ipif_Bus2IP_MstRd_d,
Bus2IP_MstRd_src_rdy_n => ipif_Bus2IP_MstRd_src_rdy_n,
IP2Bus_MstWr_d => ipif_IP2Bus_MstWr_d,
Bus2IP_MstWr_dst_rdy_n => ipif_Bus2IP_MstWr_dst_rdy_n
);
-- ------------------------------------------
-- -- instantiate User Logic
-- ------------------------------------------
-- USER_LOGIC_I : entity plb_sync_manager_v1_00_a.user_logic
-- generic map
-- (
-- -- MAP USER GENERICS BELOW THIS LINE ---------------
-- --USER generics mapped here
-- -- MAP USER GENERICS ABOVE THIS LINE ---------------
--
-- C_SLV_DWIDTH => USER_SLV_DWIDTH,
-- C_MST_AWIDTH => USER_MST_AWIDTH,
-- C_MST_DWIDTH => USER_MST_DWIDTH,
-- C_NUM_REG => USER_NUM_REG
-- )
-- port map
-- (
-- -- MAP USER PORTS BELOW THIS LINE ------------------
-- --USER ports mapped here
-- -- MAP USER PORTS ABOVE THIS LINE ------------------
--
-- Bus2IP_Clk => ipif_Bus2IP_Clk,
-- Bus2IP_Reset => ipif_Bus2IP_Reset,
-- Bus2IP_Addr => ipif_Bus2IP_Addr,
-- Bus2IP_CS => ipif_Bus2IP_CS,
-- Bus2IP_RNW => ipif_Bus2IP_RNW,
-- Bus2IP_Data => ipif_Bus2IP_Data,
-- Bus2IP_BE => ipif_Bus2IP_BE,
-- Bus2IP_RdCE => user_Bus2IP_RdCE,
-- Bus2IP_WrCE => user_Bus2IP_WrCE,
-- IP2Bus_Data => user_IP2Bus_Data,
-- IP2Bus_RdAck => user_IP2Bus_RdAck,
-- IP2Bus_WrAck => user_IP2Bus_WrAck,
-- IP2Bus_Error => user_IP2Bus_Error,
-- IP2Bus_MstRd_Req => ipif_IP2Bus_MstRd_Req,
-- IP2Bus_MstWr_Req => ipif_IP2Bus_MstWr_Req,
-- IP2Bus_Mst_Addr => ipif_IP2Bus_Mst_Addr,
-- IP2Bus_Mst_BE => ipif_IP2Bus_Mst_BE,
-- IP2Bus_Mst_Lock => ipif_IP2Bus_Mst_Lock,
-- IP2Bus_Mst_Reset => ipif_IP2Bus_Mst_Reset,
-- Bus2IP_Mst_CmdAck => ipif_Bus2IP_Mst_CmdAck,
-- Bus2IP_Mst_Cmplt => ipif_Bus2IP_Mst_Cmplt,
-- Bus2IP_Mst_Error => ipif_Bus2IP_Mst_Error,
-- Bus2IP_Mst_Rearbitrate => ipif_Bus2IP_Mst_Rearbitrate,
-- Bus2IP_Mst_Cmd_Timeout => ipif_Bus2IP_Mst_Cmd_Timeout,
-- Bus2IP_MstRd_d => ipif_Bus2IP_MstRd_d,
-- Bus2IP_MstRd_src_rdy_n => ipif_Bus2IP_MstRd_src_rdy_n,
-- IP2Bus_MstWr_d => ipif_IP2Bus_MstWr_d,
-- Bus2IP_MstWr_dst_rdy_n => ipif_Bus2IP_MstWr_dst_rdy_n
-- );
--------------------------------------------------------------------------
-- Instantiate the Slave Logic
--------------------------------------------------------------------------
slave_logic_i : entity work.slave
generic map
(
C_NUM_THREADS => C_NUM_THREADS,
C_NUM_MUTEXES => C_NUM_MUTEXES,
C_AWIDTH => USER_AWIDTH,
C_DWIDTH => USER_DWIDTH,
C_MAX_AR_DWIDTH => USER_DWIDTH,
C_NUM_ADDR_RNG => USER_NUM_ADDR_RNG,
C_NUM_CE => USER_NUM_CE
)
port map
(
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => ipif_Bus2IP_Reset,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RNW => ipif_Bus2IP_RNW,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_Error => user_IP2Bus_Error,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
system_reset => system_reset,
system_resetdone => slave_resetdone,
send_ena => send_ena,
send_id => send_id,
send_ack => send_ack,
siaddr => siaddr,
siena => siena,
siwea => siwea,
sinext => sinext,
sonext => sonext
);
--------------------------------------------------------------------------
-- Instantiate the Master Logic
--------------------------------------------------------------------------
master_logic_i : entity work.master
generic map
(
C_BASEADDR => C_BASEADDR,
C_HIGHADDR => C_HIGHADDR,
C_SCHED_BASEADDR => C_SCHED_BADDR,
C_RESULT_BASEADDR => RESULT_BASE,
C_NUM_THREADS => C_NUM_THREADS,
C_NUM_MUTEXES => C_NUM_MUTEXES,
C_AWIDTH => USER_AWIDTH,
C_DWIDTH => USER_DWIDTH,
C_MAX_AR_DWIDTH => USER_DWIDTH,
C_NUM_ADDR_RNG => USER_NUM_ADDR_RNG,
C_NUM_CE => USER_NUM_CE
)
port map
(
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => ipif_Bus2IP_Reset,
-- Bus2IP_Addr => iBus2IP_Addr,
-- Bus2IP_Data => uBus2IP_Data,
-- Bus2IP_BE => uBus2IP_BE,
-- Bus2IP_RNW => iBus2IP_RNW,
-- Bus2IP_RdCE => uBus2IP_RdCE,
-- Bus2IP_WrCE => uBus2IP_WrCE,
-- Bus2IP_RdReq => iBus2IP_RdReq,
-- Bus2IP_WrReq => iBus2IP_WrReq,
-- Bus2IP_MstError => iBus2IP_MstError,
-- Bus2IP_MstLastAck => iBus2IP_MstLastAck,
-- Bus2IP_MstRdAck => iBus2IP_MstRdAck,
-- Bus2IP_MstWrAck => iBus2IP_MstWrAck,
-- Bus2IP_MstRetry => iBus2IP_MstRetry,
-- Bus2IP_MstTimeOut => iBus2IP_MstTimeOut,
-- IP2Bus_Addr => iIP2Bus_Addr,
-- IP2Bus_MstBE => uIP2Bus_MstBE,
-- IP2Bus_MstBurst => iIP2Bus_MstBurst,
-- IP2Bus_MstBusLock => iIP2Bus_MstBusLock,
-- IP2Bus_MstRdReq => iIP2Bus_MstRdReq,
-- IP2Bus_MstWrReq => iIP2Bus_MstWrReq,
-- IP2IP_Addr => iIP2IP_Addr,
IP2Bus_MstRd_Req => ipif_IP2Bus_MstRd_Req,
IP2Bus_MstWr_Req => ipif_IP2Bus_MstWr_Req,
IP2Bus_Mst_Addr => ipif_IP2Bus_Mst_Addr,
IP2Bus_Mst_BE => ipif_IP2Bus_Mst_BE,
IP2Bus_Mst_Lock => ipif_IP2Bus_Mst_Lock,
IP2Bus_Mst_Reset => ipif_IP2Bus_Mst_Reset,
Bus2IP_Mst_CmdAck => ipif_Bus2IP_Mst_CmdAck,
Bus2IP_Mst_Cmplt => ipif_Bus2IP_Mst_Cmplt,
Bus2IP_Mst_Error => ipif_Bus2IP_Mst_Error,
Bus2IP_Mst_Rearbitrate => ipif_Bus2IP_Mst_Rearbitrate,
Bus2IP_Mst_Cmd_Timeout => ipif_Bus2IP_Mst_Cmd_Timeout,
Bus2IP_MstRd_d => ipif_Bus2IP_MstRd_d,
Bus2IP_MstRd_src_rdy_n => ipif_Bus2IP_MstRd_src_rdy_n,
IP2Bus_MstWr_d => ipif_IP2Bus_MstWr_d,
Bus2IP_MstWr_dst_rdy_n => ipif_Bus2IP_MstWr_dst_rdy_n,
system_reset => system_reset,
system_resetdone => master_resetdone,
send_ena => send_ena,
send_id => send_id,
send_ack => send_ack,
saddr => siaddr,
sena => siena,
swea => siwea,
sonext => sinext,
sinext => sonext
);
------------------------------------------
-- connect internal signals
------------------------------------------
-- IP2BUS_DATA_MUX_PROC : process( ipif_Bus2IP_CS, user_IP2Bus_Data ) is
-- begin
--
-- case ipif_Bus2IP_CS is
-- when "10" => ipif_IP2Bus_Data <= user_IP2Bus_Data;
-- when "01" => ipif_IP2Bus_Data <= user_IP2Bus_Data;
-- when others => ipif_IP2Bus_Data <= (others => '0');
-- end case;
--
-- end process IP2BUS_DATA_MUX_PROC;
ipif_IP2Bus_Data <= user_IP2Bus_Data;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;
user_Bus2IP_RdCE(0 to USER_SLV_NUM_REG-1) <= ipif_Bus2IP_RdCE(USER_SLV_CE_INDEX to USER_SLV_CE_INDEX+USER_SLV_NUM_REG-1);
user_Bus2IP_RdCE(USER_SLV_NUM_REG to USER_NUM_REG-1) <= ipif_Bus2IP_RdCE(USER_MST_CE_INDEX to USER_MST_CE_INDEX+USER_MST_NUM_REG-1);
user_Bus2IP_WrCE(0 to USER_SLV_NUM_REG-1) <= ipif_Bus2IP_WrCE(USER_SLV_CE_INDEX to USER_SLV_CE_INDEX+USER_SLV_NUM_REG-1);
user_Bus2IP_WrCE(USER_SLV_NUM_REG to USER_NUM_REG-1) <= ipif_Bus2IP_WrCE(USER_MST_CE_INDEX to USER_MST_CE_INDEX+USER_MST_NUM_REG-1);
------------------------------------------
-- hooking reset done signals
------------------------------------------
system_resetdone <= master_resetdone and slave_resetdone;
end IMP;
|
bsd-3-clause
|
masson2013/heterogeneous_hthreads
|
src/hardware/MyRepository/pcores/axi_hthread_cores/axi_sync_manager_v1_00_a/hdl/vhdl/count_fsm.vhd
|
11
|
5764
|
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use work.common.all;
entity count_fsm is
generic
(
C_AWIDTH : integer := 32;
C_DWIDTH : integer := 32;
C_TWIDTH : integer := 8;
C_MWIDTH : integer := 6;
C_CWIDTH : integer := 8
);
port
(
clk : in std_logic;
rst : in std_logic;
start : in std_logic;
finish : out std_logic;
data : out std_logic_vector(0 to C_DWIDTH-1);
mutex : in std_logic_vector(0 to C_MWIDTH-1);
thread : in std_logic_vector(0 to C_TWIDTH-1);
miowner : in std_logic_vector(0 to C_TWIDTH-1);
minext : in std_logic_vector(0 to C_TWIDTH-1);
milast : in std_logic_vector(0 to C_TWIDTH-1);
micount : in std_logic_vector(0 to C_CWIDTH-1);
mikind : in std_logic_vector(0 to 1);
tinext : in std_logic_vector(0 to C_TWIDTH-1);
moaddr : out std_logic_vector(0 to C_MWIDTH-1);
moena : out std_logic;
mowea : out std_logic;
moowner : out std_logic_vector(0 to C_TWIDTH-1);
monext : out std_logic_vector(0 to C_TWIDTH-1);
molast : out std_logic_vector(0 to C_TWIDTH-1);
mocount : out std_logic_vector(0 to C_CWIDTH-1);
mokind : out std_logic_vector(0 to 1);
sysrst : in std_logic;
rstdone : out std_logic;
toaddr : out std_logic_vector(0 to C_TWIDTH-1);
toena : out std_logic;
towea : out std_logic;
tonext : out std_logic_vector(0 to C_TWIDTH-1)
);
end count_fsm;
architecture behavioral of count_fsm is
-- A type for the states in the count fsm
type count_state is
(
IDLE,
READ,
DONE
);
-- Declare signals for the count fsm
signal count_cs : count_state;
signal count_ns : count_state;
-- Alias the location to store the count information
alias cdata : std_logic_vector(0 to C_CWIDTH-1) is data(C_DWIDTH-C_CWIDTH to C_DWIDTH-1);
begin
-- This core resets in one clock cycle so it is always "done"
rstdone <= '1';
count_update : process(clk,rst,sysrst,count_ns) is
begin
if( rising_edge(clk) ) then
if( rst = '1' or sysrst = '1' ) then
count_cs <= IDLE;
else
count_cs <= count_ns;
end if;
end if;
end process count_update;
count_controller : process(count_cs,start,mutex,micount) is
begin
count_ns <= count_cs;
finish <= '0';
data <= (others => '0');
moaddr <= (others => '0');
moena <= '0';
mowea <= '0';
moowner <= (others => '0');
monext <= (others => '0');
molast <= (others => '0');
mokind <= (others => '0');
mocount <= (others => '0');
toaddr <= (others => '0');
toena <= '0';
towea <= '0';
tonext <= (others => '0');
case count_cs is
when IDLE =>
if( start = '1' ) then
moaddr <= mutex;
moena <= '1';
mowea <= '0';
count_ns <= READ;
end if;
when READ =>
count_ns <= DONE;
when DONE =>
finish <= '1';
cdata <= micount;
count_ns <= IDLE;
end case;
end process count_controller;
end behavioral;
|
bsd-3-clause
|
masson2013/heterogeneous_hthreads
|
src/platforms/xilinx/ml605_pr_smp1_14_7/design/pcores/plb_thread_manager_v1_00_a/hdl/vhdl/user_logic.vhd
|
9
|
57513
|
------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
--
-- Title Thread Manager
--
-- 26 Jul 2004: Mike Finley: Original author
-- 08 Jun 2005: Erik Anderson: Changes for new interface between TM and
-- Scheduler. Also adding function isQueue().
-- 15 Apr 2009: Jim Stevens: Ported to PLB version 4.6.
--
---------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
-- DO NOT EDIT ABOVE THIS LINE --------------------
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_SLV_DWIDTH -- Slave interface data bus width
-- C_NUM_REG -- Number of software accessible registers
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Reset -- Bus to IP reset
-- Bus2IP_Addr -- Bus to IP address bus
-- Bus2IP_CS -- Bus to IP chip select
-- Bus2IP_RNW -- Bus to IP read/not write
-- Bus2IP_Data -- Bus to IP data bus
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- IP2Bus_Data -- IP to Bus data bus
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- IP2Bus_Error -- IP to Bus error response
------------------------------------------------------------------------------
entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_SLV_DWIDTH : integer := 32;
C_NUM_REG : integer := 1;
-- DO NOT EDIT ABOVE THIS LINE ---------------------
C_RESET_TIMEOUT : natural := 4096
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Addr : in std_logic_vector(0 to 31);
Bus2IP_CS : in std_logic_vector(0 to 0);
Bus2IP_RNW : in std_logic;
Bus2IP_Data : in std_logic_vector(0 to C_SLV_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_SLV_DWIDTH/8-1);
Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_REG-1);
Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_REG-1);
IP2Bus_Data : out std_logic_vector(0 to C_SLV_DWIDTH-1);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic;
-- DO NOT EDIT ABOVE THIS LINE ---------------------
Access_Intr : out std_logic;
Scheduler_Reset : out std_logic;
Scheduler_Reset_Done : in std_logic;
Semaphore_Reset : out std_logic;
Semaphore_Reset_Done : in std_logic;
SpinLock_Reset : out std_logic;
SpinLock_Reset_Done : in std_logic;
User_IP_Reset : out std_logic;
User_IP_Reset_Done : in std_logic;
Soft_Stop : out std_logic;
tm2sch_cpu_thread_id : out std_logic_vector(0 to 7);
tm2sch_opcode : out std_logic_vector(0 to 5);
tm2sch_data : out std_logic_vector(0 to 7);
tm2sch_request : out std_logic;
tm2sch_DOB : out std_logic_vector(0 to 31);
sch2tm_ADDRB : in std_logic_vector(0 to 8);
sch2tm_DIB : in std_logic_vector(0 to 31);
sch2tm_ENB : in std_logic;
sch2tm_WEB : in std_logic;
sch2tm_busy : in std_logic;
sch2tm_data : in std_logic_vector(0 to 7);
sch2tm_next_id : in std_logic_vector(0 to 7);
sch2tm_next_id_valid : in std_logic
);
attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk : signal is "CLK";
attribute SIGIS of Bus2IP_Reset : signal is "RST";
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
-- Define the memory map for each register, Address[16 to 21]
--
constant C_CLEAR_THREAD : std_logic_vector(0 to 5) := "000000";
constant C_JOIN_THREAD : std_logic_vector(0 to 5) := "000001";
constant C_READ_THREAD : std_logic_vector(0 to 5) := "000011";
constant C_ADD_THREAD : std_logic_vector(0 to 5) := "000100";
constant C_CREATE_THREAD_J : std_logic_vector(0 to 5) := "000101";
constant C_CREATE_THREAD_D : std_logic_vector(0 to 5) := "000110";
constant C_EXIT_THREAD : std_logic_vector(0 to 5) := "000111";
constant C_NEXT_THREAD : std_logic_vector(0 to 5) := "001000";
constant C_YIELD_THREAD : std_logic_vector(0 to 5) := "001001";
constant C_CURRENT_THREAD : std_logic_vector(0 to 5) := "010000";
constant C_IS_DETACHED : std_logic_vector(0 to 5) := "011000";
constant C_IS_QUEUED : std_logic_vector(0 to 5) := "011001";
constant C_EXCEPTION_ADDR : std_logic_vector(0 to 5) := "010011";
constant C_EXCEPTION_REG : std_logic_vector(0 to 5) := "010100";
constant C_SOFT_START : std_logic_vector(0 to 5) := "010101";
constant C_SOFT_STOP : std_logic_vector(0 to 5) := "010110";
constant C_SOFT_RESET : std_logic_vector(0 to 5) := "010111";
constant C_SCHED_LINES : std_logic_vector(0 to 5) := "011010";
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
constant OPCODE_IS_QUEUED : std_logic_vector(0 to 5) := "000001";
constant OPCODE_ENQUEUE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DEQUEUE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_IS_EMPTY : std_logic_vector(0 to 5) := "000110";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
constant H32 : std_logic_vector(0 to 31) := (others => '1');
constant MAX_QUEUE_SIZE : std_logic_vector(0 to 7) := (others => '1');
constant TOUT_CYCLES : natural := 3; -- assert timeout suppress
signal cycle_count : std_logic_vector(0 to 15);
signal timeout_expired : std_logic;
-- Extended Thread Error Codes returned in lower 4 bits
constant ERROR_IN_STATUS : std_logic_vector(0 to 3) := "0001";
constant THREAD_ALREADY_TERMINATED : std_logic_vector(0 to 3) := "0011";
constant THREAD_ALREADY_QUEUED : std_logic_vector(0 to 3) := "0101";
constant ERROR_FROM_SCHEDULER : std_logic_vector(0 to 3) := "0111";
constant JOIN_ERROR_CHILD_JOINED : std_logic_vector(0 to 3) := "1001";
constant JOIN_ERROR_NOT_CHILD : std_logic_vector(0 to 3) := "1011";
constant JOIN_ERROR_CHILD_DETACHED : std_logic_vector(0 to 3) := "1101";
constant JOIN_ERROR_CHILD_NOT_USED : std_logic_vector(0 to 3) := "1111";
constant JOIN_ERROR_UNKNOWN : std_logic_vector(0 to 3) := "0001";
constant CLEAR_ERROR_NOT_USED : std_logic_vector(0 to 3) := "1001";
-- Exception "cause" returned in Exception register
constant EXCEPTION_WRITE_TO_READ_ONLY : std_logic_vector(0 to 3) := "0001";
constant EXCEPTION_UNDEFINED_ADDRESS : std_logic_vector(0 to 3) := "0010";
constant EXCEPTION_TO_SOFT_RESET : std_logic_vector(0 to 3) := "0011";
constant EXCEPTION_TO_SCHD_ISQUEUED : std_logic_vector(0 to 3) := "0100";
constant EXCEPTION_TO_SCHD_ENQUEUE : std_logic_vector(0 to 3) := "0101";
constant EXCEPTION_TO_SCHD_DEQUEUE : std_logic_vector(0 to 3) := "0110";
constant EXCEPTION_TO_SCHD_ISEMPTY : std_logic_vector(0 to 3) := "0111";
constant EXCEPTION_TO_SCHD_NEXT_THREAD : std_logic_vector(0 to 3) := "1000";
constant EXCEPTION_SCHD_INVALID_THREAD : std_logic_vector(0 to 3) := "1001";
constant EXCEPTION_ILLEGAL_STATE : std_logic_vector(0 to 3) := "1111";
-- BRAM constants
constant BRAM_ADDRESS_BITS : integer := 9;
constant BRAM_DATA_BITS : integer := 32;
-- Address,Cause for access exceptions
--
signal Exception_Address : std_logic_vector(0 to 31);
signal Exception_Address_next : std_logic_vector(0 to 31);
signal Exception_Cause : std_logic_vector(0 to 3);
signal Exception_Cause_next : std_logic_vector(0 to 3);
signal access_error : std_logic;
-- Debug control signals
--
-- Soft reset signals, LSB = SWTM reset; reset IP(s) if '1'
-- Resets done, handshake from IPs if done resetting(1)
-- core_stop , halt state machines at next appropriate point if '1'
--
signal soft_resets : std_logic_vector(0 to 4);
signal soft_resets_next : std_logic_vector(0 to 4);
signal resets_done : std_logic_vector(0 to 4);
signal reset_status : std_logic_vector(0 to 4);
signal reset_status_next : std_logic_vector(0 to 4);
signal core_stop : std_logic;
signal core_stop_next : std_logic;
-- Declarations for each register
-- Current thread,Idle thread : bits 0..7 = ID, bit 8 = '1' = invalid
signal current_cpu_thread : std_logic_vector(0 to 8);
signal current_cpu_thread_next : std_logic_vector(0 to 8);
-- internal signals
signal next_ID : std_logic_vector(0 to 8);
signal next_ID_next : std_logic_vector(0 to 8);
signal temp_thread_id : std_logic_vector(0 to 7);
signal temp_thread_id_next : std_logic_vector(0 to 7);
signal temp_thread_id2 : std_logic_vector(0 to 7);
signal temp_thread_id2_next : std_logic_vector(0 to 7);
signal reset_ID : std_logic_vector(0 to 8);
type swtm_state_type is
(IDLE_STATE,
SOFT_RESET_WRITE_INIT,
SOFT_RESET_INIT_TABLE,
SOFT_RESET_WAIT,
READ_THREAD_INIT,
READ_THREAD_RD_WAIT,
READ_THREAD_DONE,
CREATE_THREAD_INIT,
CT_NEW_ID_RD_WAIT,
CT_NEW_ID_AVAILABLE,
CT_ENTRY_RD_WAIT,
CT_ENTRY_AVAILABLE,
CT_DONE,
CLEAR_THREAD_INIT,
CLEAR_ENTRY_RD_WAIT,
CLEAR_ENTRY_AVAIABLE,
DEALLOCATE_ID,
DEALLOCATE_NEXT_ENTRY_RD_WAIT,
DEALLOCATE_NEXT_ENTRY_AVAIL,
JOIN_THREAD_INIT,
JOIN_RD_ENTRY_RD_WAIT,
JOIN_RD_ENTRY_AVAILABLE,
IS_QUEUED_INIT,
IS_QUEUED_DONE,
IS_DETACHED_THREAD_INIT,
IS_DETACHED_ENTRY_RD_WAIT,
IS_DETACHED_ENTRY_AVAILABLE,
NEXT_THREAD_INIT,
NEXT_THREAD_WAIT4_SCHEDULER,
NEXT_THREAD_RD_WAIT,
NEXT_THREAD_AVAILABLE,
NEXT_THREAD_CHECK_DEQUEUE,
ADD_THREAD_INIT,
AT_ENTRY_RD_WAIT,
AT_ENTRY_AVAILABLE,
AT_ISQUEUED_WAIT,
AT_CHECK_ISQUEUE,
AT_ENQUEUE_WAIT,
AT_CHECK_ENQUEUE,
ISQUEUED_WAIT_ACK,
ISQUEUED_WAIT_COMPLETE,
ENQUEUE_WAIT_ACK,
ENQUEUE_WAIT_COMPLETE,
DEQUEUE_WAIT_ACK,
DEQUEUE_WAIT_COMPLETE,
IS_QUEUE_EMPTY_WAIT_ACK,
IS_QUEUE_EMPTY_WAIT_COMPLETE,
YIELD_THREAD_INIT,
YIELD_CURRENT_THREAD_RD_WAIT,
YIELD_CURRENT_THREAD_AVAILABLE,
YIELD_CHECK_QUEUE_EMPTY,
YIELD_ENQUEUE,
YIELD_CHECK_ENQUEUE,
-- YIELD_dummy_is_queued,
YIELD_DEQUEUE,
YIELD_CHECK_DEQUEUE,
EXIT_THREAD_INIT,
EXIT_THREAD_RD_WAIT,
EXIT_THREAD_AVAIABLE,
EXIT_DEALLOCATE,
EXIT_NEXT_THREAD_RD_WAIT,
EXIT_NEXT_THREAD_AVAILABLE,
EXIT_READ_PARENT,
EXIT_READ_PARENT_WAIT,
EXIT_READ_PARENT_AVAILABLE,
EXIT_CHECK_ENQUEUE,
RAISE_EXCEPTION,
END_TRANSACTION,
END_TRANSACTION_WAIT);
signal current_state, next_state : swtm_state_type := IDLE_STATE;
signal return_state, return_state_next : swtm_state_type := IDLE_STATE;
signal bus_data_out : std_logic_vector(0 to 31);
signal bus_data_out_next : std_logic_vector(0 to 31);
signal current_status : std_logic_vector(0 to 31);
signal current_status_next : std_logic_vector(0 to 31);
signal Swtm_Reset_Done : std_logic;
signal Swtm_Reset_Done_next : std_logic;
signal new_ID : std_logic_vector(0 to 7);
signal new_ID_next : std_logic_vector(0 to 7);
signal tm2sch_request_next : std_logic;
signal tm2sch_request_reg : std_logic;
signal tm2sch_data_next : std_logic_vector(0 to 7);
signal tm2sch_data_reg : std_logic_vector(0 to 7);
signal tm2sch_opcode_next : std_logic_vector(0 to 5);
signal tm2sch_opcode_reg : std_logic_vector(0 to 5);
-- Signals for thread table BRAM
signal ENA : std_logic;
signal WEA : std_logic;
signal ADDRA : std_logic_vector(0 to BRAM_ADDRESS_BITS - 1);
signal DIA : std_logic_vector(0 to BRAM_DATA_BITS - 1);
signal DOA : std_logic_vector(0 to BRAM_DATA_BITS - 1);
alias addr :std_logic_vector(0 to 5) is Bus2IP_Addr(16 to 21);
---------------------------------------------------------------------------
-- Component Instantiation of inferred dual ported block RAM
---------------------------------------------------------------------------
component infer_bram_dual_port is
generic (
ADDRESS_BITS : integer := 9;
DATA_BITS : integer := 32
);
port (
CLKA : in std_logic;
ENA : in std_logic;
WEA : in std_logic;
ADDRA : in std_logic_vector(0 to ADDRESS_BITS - 1);
DIA : in std_logic_vector(0 to DATA_BITS - 1);
DOA : out std_logic_vector(0 to DATA_BITS - 1);
CLKB : in std_logic;
ENB : in std_logic;
WEB : in std_logic;
ADDRB : in std_logic_vector(0 to ADDRESS_BITS - 1);
DIB : in std_logic_vector(0 to DATA_BITS - 1);
DOB : out std_logic_vector(0 to DATA_BITS - 1)
);
end component infer_bram_dual_port;
-------------------------------------------------------------------
-- ICON core signal declarations
-------------------------------------------------------------------
signal control0 : std_logic_vector(35 downto 0);
signal my_ack, my_tout_sup, my_error, my_sched_req : std_logic; -- TODO: This line might be gone.
signal my_counter : std_logic_vector(0 to 31);
-------------------------------------------------------------------
-- ICON core component declaration
-------------------------------------------------------------------
-- simulation translate_off
--component chipscope_icon_v1_03_a
-- port
-- (
-- control0 : out std_logic_vector(35 downto 0)
-- );
--end component;
-- simulation translate_on
-------------------------------------------------------------------
-- ILA core component declaration
-------------------------------------------------------------------
-- simulation translate_off
--component chipscope_ila_v1_02_a
-- port
-- (
--- control : in std_logic_vector(35 downto 0);
-- clk : in std_logic;
-- trig0 : in std_logic_vector(63 downto 0);
-- trig1 : in std_logic_vector(63 downto 0);
-- trig2 : in std_logic_vector(31 downto 0);
-- trig3 : in std_logic_vector(31 downto 0);
-- trig4 : in std_logic_vector(15 downto 0)
-- );
--end component;
-- simulation translate_on
begin
thread_table_bram : infer_bram_dual_port
generic map (
ADDRESS_BITS => BRAM_ADDRESS_BITS,
DATA_BITS => BRAM_DATA_BITS
)
port map (
CLKA => Bus2IP_Clk,
ENA => ENA,
WEA => WEA,
ADDRA => ADDRA,
DIA => DIA,
DOA => DOA,
CLKB => Bus2IP_Clk,
ENB => sch2tm_ENB,
WEB => sch2tm_WEB,
ADDRB => sch2tm_ADDRB,
DIB => sch2tm_DIB,
DOB => tm2sch_DOB
);
tm2sch_opcode <= tm2sch_opcode_reg;
tm2sch_data <= tm2sch_data_reg;
tm2sch_request <= tm2sch_request_reg;
Soft_Stop <= core_stop;
Scheduler_Reset <= soft_resets(3);
Semaphore_Reset <= soft_resets(2);
SpinLock_Reset <= soft_resets(1);
User_IP_Reset <= soft_resets(0);
Access_Intr <= access_error;
CYCLE_PROC : process (Bus2IP_Clk, Bus2IP_CS) is
begin
if( Bus2IP_Clk'event and Bus2IP_Clk='1' ) then
if( Bus2IP_CS(0) = '0' ) then
cycle_count <= (others => '0');
else
cycle_count <= cycle_count + 1;
end if;
end if;
end process CYCLE_PROC;
--
-- create a counter for the number of elapsed cycles
-- in each bus transaction.
-- assert TimeOut suppress when count = TOUT_CYCLES
--
CYCLE_CONTROL : process( cycle_count ) is
begin
IP2Bus_Error <= '0'; -- no error
--
-- count the number of elapsed clock cycles in transaction
--
if cycle_count < C_RESET_TIMEOUT then
timeout_expired <= '0';
else
--timeout_expired <= '1';
timeout_expired <= '0'; -- Disable timeouts.
end if;
--
-- activate time out suppress if count exceeds TOUT_CYCLES
-- edk. Why isn't this done inside the clk_event ???
--
-- if cycle_count > TOUT_CYCLES then
-- --IP2Bus_ToutSup <= '1'; -- halt time out counter
-- my_tout_sup <= '1'; -- halt time out counter
-- else
-- --IP2Bus_ToutSup <= '0'; -- release
-- my_tout_sup <= '0'; -- release
-- end if;
end process CYCLE_CONTROL;
-- IP2Bus_ToutSup <= my_tout_sup;
RESET_PROC : process (Bus2IP_Clk, addr, current_state)
begin
if( Bus2IP_Clk'event and Bus2IP_Clk = '1' ) then
if( addr = C_SOFT_RESET and current_state = SOFT_RESET_WRITE_INIT ) then
reset_ID <= (others => '0');
else
reset_ID <= reset_ID + 1;
end if;
end if;
end process;
ACK_PROC : process(my_ack, Bus2IP_RdCE, Bus2IP_WrCE)
begin
if (Bus2IP_RdCE(0) = '1') then
IP2Bus_RdAck <= my_ack;
else
IP2Bus_RdAck <= '0';
end if;
if (Bus2IP_WrCE(0) = '1') then
IP2Bus_WrAck <= my_ack;
else
IP2Bus_WrAck <= '0';
end if;
end process;
SWTM_STATE_PROC : process (Bus2IP_Clk, core_stop_next, new_ID_next, next_ID_next, temp_thread_id_next, temp_thread_id2_next, current_cpu_thread_next, Current_status_next, soft_resets_next, reset_status_next, Swtm_Reset_Done_next, Scheduler_Reset_Done, Semaphore_Reset_Done, SpinLock_Reset_Done, User_IP_Reset_Done, next_state, return_state_next, Bus2IP_Reset,Exception_Cause_next) is
begin
if (Bus2IP_Clk'event and (Bus2IP_Clk = '1')) then
core_stop <= core_stop_next;
new_ID <= new_ID_next;
next_ID <= next_ID_next;
temp_thread_id <= temp_thread_id_next;
temp_thread_id2 <= temp_thread_id2_next;
current_cpu_thread <= current_cpu_thread_next;
tm2sch_cpu_thread_id <= current_cpu_thread_next(0 to 7);
tm2sch_data_reg <= tm2sch_data_next;
tm2sch_opcode_reg <= tm2sch_opcode_next;
tm2sch_request_reg <= tm2sch_request_next;
current_status <= current_status_next;
Exception_Address <= Exception_Address_next;
Exception_Cause <= Exception_Cause_next;
soft_resets <= soft_resets_next;
reset_status <= reset_status_next;
bus_data_out <= bus_data_out_next;
Swtm_Reset_Done <= Swtm_Reset_Done_next;
resets_done(4) <= Swtm_Reset_Done_next;
resets_done(3) <= Scheduler_Reset_Done;
resets_done(2) <= Semaphore_Reset_Done;
resets_done(1) <= SpinLock_Reset_Done;
resets_done(0) <= User_IP_Reset_Done;
return_state <= return_state_next;
if( Bus2IP_Reset = '1' ) then
current_state <= IDLE_STATE;
else
current_state <= next_state;
end if;
end if;
end process SWTM_STATE_PROC;
-- IP2Bus_Ack <= my_ack; -- pulse(010) to end bus transaction
SWTM_LOGIC_PROC : process (current_state, core_stop, new_ID, next_ID, current_cpu_thread, current_status, reset_status, Swtm_Reset_Done, soft_resets, Bus2IP_Addr, Bus2IP_Data, Exception_Address, Bus2IP_WrCE, addr, Bus2IP_RdCE, reset_ID, resets_done, timeout_expired, DOA, sch2tm_next_id_valid, sch2tm_next_id, sch2tm_busy, bus_data_out, Exception_Cause, tm2sch_request_reg, tm2sch_data_reg, tm2sch_opcode_reg, temp_thread_id, temp_thread_id2) is
begin
-- -------------------------------------------------
-- default output signal assignments
-- -------------------------------------------------
my_ack <= '0'; -- pulse(010) to end bus transaction
access_error <= '0'; -- pulse(010) for access error interrupt
IP2Bus_Data <= (others => '0');
ADDRA <= (others => '0');
ENA <= '0';
WEA <= '0';
DIA <= (others => '0');
-- -------------------------------------------------
-- default register assignments
-- -------------------------------------------------
next_state <= current_state;
return_state_next <= return_state;
core_stop_next <= core_stop;
new_ID_next <= new_ID;
next_ID_next <= next_ID;
temp_thread_id_next <= temp_thread_id;
temp_thread_id2_next <= temp_thread_id2;
current_cpu_thread_next <= current_cpu_thread;
current_status_next <= current_status;
Exception_Address_next <= Exception_Address;
reset_status_next <= reset_status;
Swtm_Reset_Done_next <= Swtm_Reset_Done;
Exception_Cause_next <= Exception_Cause;
tm2sch_request_next <= tm2sch_request_reg;
tm2sch_data_next <= tm2sch_data_reg;
tm2sch_opcode_next <= tm2sch_opcode_reg;
bus_data_out_next <= bus_data_out;
soft_resets_next <= soft_resets;
case current_state is
-- Command (addr) decode whenever we are waiting for something new to do.
when IDLE_STATE =>
bus_data_out_next <= (others => '0');
if (Bus2IP_WrCE(0) = '1') then
case addr is
when C_SOFT_START =>
-- Any write to soft_start address clears
-- all soft reset signals and the Soft_Stop signal
soft_resets_next <= (others => '0');
swtm_reset_done_next <= '0'; -- clear SWTM's reset done
core_stop_next <= '0'; -- clear core_stop
next_state <= END_TRANSACTION;
when C_SOFT_STOP =>
-- write any data to Soft_Stop to assert the Soft_Stop signal
core_stop_next <= '1';
next_state <= END_TRANSACTION;
when C_SOFT_RESET =>
next_state <= SOFT_RESET_WRITE_INIT;
when C_READ_THREAD =>
if (core_stop = '1') then
ADDRA <= '0' & Bus2IP_Addr(22 to 29); -- thread ID
WEA <= '1';
ENA <= '1';
DIA <= Bus2IP_Data(0 to 31);
next_state <= END_TRANSACTION;
else
Exception_Cause_next <= EXCEPTION_WRITE_TO_READ_ONLY;
next_state <= RAISE_EXCEPTION;
end if;
when others =>
Exception_Cause_next <= EXCEPTION_UNDEFINED_ADDRESS;
next_state <= RAISE_EXCEPTION;
end case;
elsif (Bus2IP_RdCE(0) = '1') then
case addr is
when C_SOFT_START =>
bus_data_out_next <= (others => '0');
next_state <= END_TRANSACTION;
when C_SOFT_STOP =>
-- returns signal level in LSB on read
bus_data_out_next <= Z32(0 to 30) & core_stop;
next_state <= END_TRANSACTION;
when C_SOFT_RESET =>
-- returns 1's in bit positions that failed
bus_data_out_next <= Z32(0 to 26) & reset_status;
next_state <= END_TRANSACTION;
when C_CURRENT_THREAD =>
bus_data_out_next <= Z32(0 to 22) & current_cpu_thread;
next_state <= END_TRANSACTION;
when C_EXCEPTION_ADDR =>
bus_data_out_next <= Exception_Address;
Exception_Address_next <= (others => '0');
next_state <= END_TRANSACTION;
when C_EXCEPTION_REG =>
bus_data_out_next <= Z32(0 to 27) & Exception_Cause;
Exception_Cause_next <= (others => '0');
next_state <= END_TRANSACTION;
when C_SCHED_LINES =>
bus_data_out_next <= Z32(0 to 6) & sch2tm_busy & sch2tm_data &
Z32(16 to 22) & sch2tm_next_id_valid &
sch2tm_next_id;
next_state <= END_TRANSACTION;
when C_READ_THREAD => next_state <= READ_THREAD_INIT;
when C_CREATE_THREAD_D => next_state <= CREATE_THREAD_INIT;
when C_CREATE_THREAD_J => next_state <= CREATE_THREAD_INIT;
when C_CLEAR_THREAD => next_state <= CLEAR_THREAD_INIT;
when C_JOIN_THREAD => next_state <= JOIN_THREAD_INIT;
when C_IS_DETACHED => next_state <= IS_DETACHED_THREAD_INIT;
when C_IS_QUEUED => next_state <= IS_QUEUED_INIT;
when C_NEXT_THREAD => next_state <= NEXT_THREAD_INIT;
when C_ADD_THREAD => next_state <= ADD_THREAD_INIT;
when C_YIELD_THREAD => next_state <= YIELD_THREAD_INIT;
when C_EXIT_THREAD => next_state <= EXIT_THREAD_INIT;
when others =>
Exception_Cause_next <= EXCEPTION_UNDEFINED_ADDRESS;
next_state <= RAISE_EXCEPTION;
end case;
end if;
--
-- read/write to the soft resets register (1 bit per IP)
-- write '1' to reset, reads '1' if timeout error occured
-- before IP reports finished
--
-- SW Thread Manager = bit#4 (LSB)
-- Scheduler = bit#3
-- Semaphore = bit#2
-- SpinLock = bit#1
-- User_IP = bit#0
--
when SOFT_RESET_WRITE_INIT =>
soft_resets_next <= Bus2IP_Data(27 to 31);
reset_status_next <= (others => '0');
swtm_reset_done_next <= '0'; -- clear SWTM's reset_done
if (Bus2IP_Data(31) = '1') then -- soft_resets(4)
--
-- perform a soft reset on SWTM
--
bus_data_out_next <= (others => '0');
new_ID_next <= (others => '0');
next_ID_next <= (others => '0');
temp_thread_id_next <= (others => '0');
current_cpu_thread_next <= Z32(0 to 7) & '1';
core_stop_next <= '0';
tm2sch_opcode_next <= OPCODE_NOOP;
tm2sch_data_next <= (others => '0');
tm2sch_request_next <= '0';
next_state <= SOFT_RESET_INIT_TABLE;
else
next_state <= SOFT_RESET_WAIT;
end if;
-- initialize the thread ID table to all zeros
-- and the next available stack to 0..255
when SOFT_RESET_INIT_TABLE =>
ADDRA <= reset_ID;
ENA <= '1';
WEA <= '1';
if( reset_ID(0) = '0' ) then
-- init available ID stack & thread ID table
DIA <= reset_ID(1 to 8) & Z32(0 to 23);
else
-- clear 2nd half of table (unused)
DIA <= Z32(0 to 31);
end if;
if( reset_ID = H32(0 to 8) ) then
swtm_reset_done_next<= '1'; -- done
next_state <= soft_reset_wait;
end if;
-- wait for all IPs to finish initialization or
-- the maximum time to be exceeded then
-- ack to finish transaction
when SOFT_RESET_WAIT =>
if (resets_done = soft_resets) then -- done
next_state <= END_TRANSACTION;
elsif (timeout_expired = '1') then
reset_status_next <= (resets_done xor soft_resets);
Exception_Cause_next <= EXCEPTION_TO_SOFT_RESET;
next_state <= RAISE_EXCEPTION; -- timeout
else
next_state <= current_state;
end if;
when READ_THREAD_INIT =>
ADDRA <= '0' & Bus2IP_Addr(22 to 29); -- thread ID
WEA <= '0';
ENA <= '1';
next_state <= READ_THREAD_RD_WAIT;
when READ_THREAD_RD_WAIT =>
next_state <= READ_THREAD_DONE;
when READ_THREAD_DONE =>
bus_data_out_next <= DOA;
next_state <= END_TRANSACTION;
when CREATE_THREAD_INIT =>
if next_ID(0) = '1' then
-- no IDs available, return with error bit set
--
bus_data_out_next <= Z32(0 to 30) & '1';
next_state <= END_TRANSACTION;
else
-- read next ID from stack
--
ADDRA <= next_ID;
ENA <= '1';
next_state <= CT_NEW_ID_RD_WAIT;
end if;
when CT_NEW_ID_RD_WAIT =>
next_state <= CT_NEW_ID_AVAILABLE;
when CT_NEW_ID_AVAILABLE =>
new_ID_next <= DOA(0 to 7); -- save new ID#
ADDRA <= '0' & DOA(0 to 7); -- point to new thread
ENA <= '1';
next_state <= CT_ENTRY_RD_WAIT;
when CT_ENTRY_RD_WAIT =>
next_state <= CT_ENTRY_AVAILABLE;
when CT_ENTRY_AVAILABLE =>
ADDRA <= '0' & new_ID;
ENA <= '1';
WEA <= '1'; -- enable write to bram
-- Determine if the thread to create is DETACHED / JOINABLE
if addr = C_CREATE_THREAD_D then -- set new thread status
-- create detached
DIA <= DOA(0 to 7) & Z32(0 to 7) &
Z32(0 to 7) & "1011" & Z32(0 to 3);
else
-- create joinable
DIA <= DOA(0 to 7) & Z32(0 to 7) &
current_cpu_thread(0 to 7) & "0011" & Z32(0 to 3);
end if;
next_state <= CT_DONE;
when CT_DONE =>
-- return new ID with no error,
bus_data_out_next <= Z32(0 to 22) & new_ID & '0';
-- point to next available ID
next_ID_next <= next_ID + 1;
next_state <= END_TRANSACTION;
when CLEAR_THREAD_INIT =>
-- clear the encoded thread ID if it is used and exited
ADDRA <= '0' & Bus2IP_Addr(22 to 29); -- thread ID
ENA <= '1';
next_state <= CLEAR_ENTRY_RD_WAIT;
when CLEAR_ENTRY_RD_WAIT =>
next_state <= CLEAR_ENTRY_AVAIABLE ;
when CLEAR_ENTRY_AVAIABLE =>
if (DOA(26 to 27) = "10") then -- used and exited
bus_data_out_next <= Z32; -- success, return zero
ADDRA <= '0' & Bus2IP_Addr(22 to 29); -- thread ID
ENA <= '1';
WEA <= '1'; -- clear old status but
DIA <= DOA(0 to 7) & Z32(0 to 23); -- preserve ID stack
next_state <= DEALLOCATE_ID;
else
-- error occurred, return thread status w/ LSB=1
bus_data_out_next <= DOA(0 to 27) & CLEAR_ERROR_NOT_USED;
next_state <= END_TRANSACTION;
end if;
when DEALLOCATE_ID =>
if (next_ID /= Z32(0 to 8)) then
ADDRA <= next_ID - 1;
ENA <= '1';
next_ID_next <= next_ID - 1;
next_state <= DEALLOCATE_NEXT_ENTRY_RD_WAIT;
else
next_state <= END_TRANSACTION;
end if;
when DEALLOCATE_NEXT_ENTRY_RD_WAIT =>
next_state <= DEALLOCATE_NEXT_ENTRY_AVAIL;
when DEALLOCATE_NEXT_ENTRY_AVAIL =>
-- put ID back on stack, preserve other bits
ADDRA <= next_ID;
ENA <= '1';
WEA <= '1';
DIA <= Bus2IP_Addr(22 to 29) & DOA(8 to 31);
next_state <= END_TRANSACTION;
when JOIN_THREAD_INIT =>
-- join on the encoded thread ID if its PID = current_thread
-- and its status = used,~joined,~detached
ADDRA <= '0' & Bus2IP_Addr(22 to 29); -- thread ID
ENA <= '1';
next_state <= JOIN_RD_ENTRY_RD_WAIT;
when JOIN_RD_ENTRY_RD_WAIT =>
next_state <= JOIN_RD_ENTRY_AVAILABLE;
when JOIN_RD_ENTRY_AVAILABLE =>
if ((DOA(16 to 23) & '0' = current_cpu_thread) and -- PID = current thread
(DOA(24 to 25) = "00") and -- ~detached,~joined
(DOA(26 to 27) /= "00")) then -- not unused
if DOA(27) = '0' then
-- thread has already exited, return a WARNING code
bus_data_out_next <= Z32(0 to 27) & THREAD_ALREADY_TERMINATED;
next_state <= END_TRANSACTION;
else
-- thread has not exited
bus_data_out_next <= Z32; -- success, return zero
ADDRA <= '0' & Bus2IP_Addr(22 to 29); -- thread ID
ENA <= '1';
WEA <= '1';
-- clear old status but
-- set joined bit; and preserve all other bits
DIA <= DOA(0 to 24) & '1' & DOA(26 to 31);
next_state <= END_TRANSACTION;
end if;
else
-- An error occured. Determine the error and return correct error code.
if( DOA(24) = '1' ) then
-- trying to join on a detached thread
bus_data_out_next <= DOA(0 to 27) & JOIN_ERROR_CHILD_DETACHED;
elsif ( DOA(24 to 25) = "01" ) then
-- tyring to join on a thread that is already joined
bus_data_out_next <= DOA(0 to 27) & JOIN_ERROR_CHILD_JOINED;
elsif( DOA(26) = '0' ) then
-- trying to join on a thread that is not used
bus_data_out_next <= DOA(0 to 27) & JOIN_ERROR_CHILD_NOT_USED;
elsif( DOA(16 to 23) & '0' /= current_cpu_thread ) then
-- trying to join to a thread that is not the current thread's child
bus_data_out_next <= DOA(0 to 27) & JOIN_ERROR_NOT_CHILD;
else
bus_data_out_next <= DOA(0 to 27) & JOIN_ERROR_UNKNOWN;
end if;
next_state <= END_TRANSACTION;
end if;
when IS_DETACHED_THREAD_INIT =>
-- Returns a 1 if the encoded thread ID is detached, else returns 0
ADDRA <= '0' & Bus2IP_Addr(22 to 29); -- thread ID
ENA <= '1';
next_state <= IS_DETACHED_ENTRY_RD_WAIT;
when IS_DETACHED_ENTRY_RD_WAIT =>
next_state <= IS_DETACHED_ENTRY_AVAILABLE;
when IS_DETACHED_ENTRY_AVAILABLE =>
if (DOA(24) = '1' and DOA(26) = '1') then
-- Thread is detached, return 1
bus_data_out_next <= Z32(0 to 29) & "10"; -- The 0 in the last bit indicates no error
else
-- Thread is not detached, or not used, return 0
bus_data_out_next <= Z32;
end if;
next_state <= END_TRANSACTION;
when IS_QUEUED_INIT =>
tm2sch_opcode_next <= OPCODE_IS_QUEUED;
tm2sch_request_next <= '1';
tm2sch_data_next <= Bus2IP_Addr(22 to 29); -- thread ID
next_state <= ISQUEUED_WAIT_ACK;
return_state_next <= IS_QUEUED_DONE;
when IS_QUEUED_DONE =>
bus_data_out_next <= Z32(0 to 22) & sch2tm_data & '0';
next_state <= END_TRANSACTION;
when NEXT_THREAD_INIT =>
-- Return to the caller the value of the next thread to run
if sch2tm_next_id_valid = '1' then
-- the next thread has been identified,
-- read from Scheduler and check thread status
-- as stored by SWTM for consistency
ADDRA <= '0' & sch2tm_next_id;
ENA <= '1';
next_state <= NEXT_THREAD_RD_WAIT;
else
next_state <= NEXT_THREAD_WAIT4_SCHEDULER;
end if;
when NEXT_THREAD_WAIT4_SCHEDULER =>
if (sch2tm_next_id_valid = '1') then
-- Scheduler has made a scheduling decision
ADDRA <= '0' & sch2tm_next_id;
ENA <= '1';
next_state <= NEXT_THREAD_RD_WAIT;
elsif (timeout_expired = '1') then
-- Timed out waiting for scheduler
Exception_Cause_next <= EXCEPTION_TO_SCHD_NEXT_THREAD;
next_state <= RAISE_EXCEPTION; -- timeout
else
-- Continue waiting for scheduler
next_state <= current_state;
end if;
when NEXT_THREAD_RD_WAIT =>
next_state <= NEXT_THREAD_AVAILABLE;
when NEXT_THREAD_AVAILABLE =>
if DOA(26 to 27) = "11" then
-- thread status is used and not exited
-- dequeue the next_thread_id from the scheduler's queue
current_cpu_thread_next <= sch2tm_next_id & '0';
-- Send dequeue opperation to scheduler
tm2sch_opcode_next <= OPCODE_DEQUEUE;
tm2sch_request_next <= '1';
tm2sch_data_next <= Z32(0 to 7);
next_state <= DEQUEUE_WAIT_ACK;
return_state_next <= NEXT_THREAD_CHECK_DEQUEUE;
else
-- TM and SCHEDULER disagree if thread was used and not exited
-- return thread ID, set error bit and raise exception
bus_data_out_next <= Z32(0 to 22) & sch2tm_next_id & '1';
Exception_Cause_next <= EXCEPTION_SCHD_INVALID_THREAD;
next_state <= RAISE_EXCEPTION; -- timeout
end if;
when NEXT_THREAD_CHECK_DEQUEUE =>
-- Perform a check to make sure scheduler completed successfully
if sch2tm_data(7) = '1' then
-- error during enqueue
bus_data_out_next <= Z32(0 to 27) & ERROR_FROM_SCHEDULER;
next_state <= END_TRANSACTION;
else
-- enqueue completed correctly
-- return the value of the next thread id (which by now is in the current_cpu_thread register)
bus_data_out_next <= Z32(0 to 22) & current_cpu_thread(0 to 7) & '0';
next_state <= END_TRANSACTION;
end if;
when ADD_THREAD_INIT =>
-- if the thread is !used or exited return error
-- call scheduler to check queued status
-- if queued return error
-- call scheduler to enqueue thread ID
ADDRA <= '0' & Bus2IP_Addr(22 to 29); -- encoded thread ID
ENA <= '1';
next_state <= AT_ENTRY_RD_WAIT;
when AT_ENTRY_RD_WAIT =>
next_state <= AT_ENTRY_AVAILABLE;
when AT_ENTRY_AVAILABLE =>
-- check to see if the thread is used and !exited
if (DOA(26 to 27) = "11") then
-- thread is used and not exited
-- call scheduler isQueued
tm2sch_request_next <= '1';
tm2sch_data_next <= Bus2IP_Addr(22 to 29);
tm2sch_opcode_next <= OPCODE_IS_QUEUED;
next_state <= ISQUEUED_WAIT_ACK;
return_state_next <= AT_CHECK_ISQUEUE;
else
-- thread is unused or exited (or both)
-- operation failed, return error code
bus_data_out_next <= DOA(0 to 27) & ERROR_IN_STATUS;
next_state <= END_TRANSACTION;
end if;
when AT_CHECK_ISQUEUE =>
-- Check to see if the thread is queued
if sch2tm_data(7) = '0' then
-- Thread is not queued, call scheduler's enqueue
tm2sch_request_next <= '1';
tm2sch_data_next <= Bus2IP_Addr(22 to 29);
tm2sch_opcode_next <= OPCODE_ENQUEUE;
next_state <= ENQUEUE_WAIT_ACK;
return_state_next <= AT_CHECK_ENQUEUE;
else
-- Thread is queued, return error
bus_data_out_next <= DOA(0 to 7) & sch2tm_data & DOA(16 to 27) & THREAD_ALREADY_QUEUED;
next_state <= END_TRANSACTION;
end if;
when AT_CHECK_ENQUEUE =>
-- Check to make sure the scheduler added the thread correctly
if sch2tm_data(7) = '1' then
-- error during enqueue
bus_data_out_next <= Z32(0 to 7) & sch2tm_data & Z32(16 to 27) & ERROR_FROM_SCHEDULER;
next_state <= END_TRANSACTION;
else
-- enqueue completed correctly
bus_data_out_next <= Z32(0 to 7) & sch2tm_data & Z32(16 to 31);
next_state <= END_TRANSACTION;
end if;
when ISQUEUED_WAIT_ACK =>
-- wait for the scheduler to acknowledge the isqueued request
if sch2tm_busy = '0' then
-- scheduler has not yet responded to request
next_state <= current_state;
elsif (timeout_expired = '1') then
-- timed out waiting for scheduler
Exception_Cause_next <= EXCEPTION_TO_SCHD_ISQUEUED;
next_state <= RAISE_EXCEPTION;
else
-- scheduler acknowledged request, lower request line
tm2sch_request_next <= '0';
tm2sch_data_next <= Z32(0 to 7);
tm2sch_opcode_next <= OPCODE_NOOP;
next_state <= ISQUEUED_WAIT_COMPLETE;
end if;
when ISQUEUED_WAIT_COMPLETE =>
-- wait for the scheduler to complete the isqueued request
if sch2tm_busy = '1' then
-- scheduler has not yet completed request
next_state <= current_state;
elsif (timeout_expired = '1') then
-- timed out waiting for scheduler
Exception_Cause_next <= EXCEPTION_TO_SCHD_ISQUEUED;
next_state <= RAISE_EXCEPTION;
else
-- scheduler finished request, and (should) have data on data_return line
tm2sch_data_next <= Z32(0 to 7);
tm2sch_opcode_next <= OPCODE_NOOP;
next_state <= return_state;
end if;
when ENQUEUE_WAIT_ACK =>
-- Wait for the scheduler to acknowledge the enqueue request
if sch2tm_busy = '0' then
-- Scheduler has not yet responded
next_state <= current_state;
elsif (timeout_expired = '1') then
-- Timed out waiting for queue
Exception_Cause_next <= EXCEPTION_TO_SCHD_ENQUEUE;
next_state <= RAISE_EXCEPTION;
else
-- Scheduler has acknowledged the request
tm2sch_request_next <= '0';
tm2sch_data_next <= Z32(0 to 7);
tm2sch_opcode_next <= OPCODE_NOOP;
next_state <= ENQUEUE_WAIT_COMPLETE;
end if;
when ENQUEUE_WAIT_COMPLETE =>
-- wait for the scheduler to complete the enqueue request
if sch2tm_busy = '1' then
-- scheduler has notyet completed request
elsif (timeout_expired = '1') then
-- Timed out waiting for queue
Exception_Cause_next <= EXCEPTION_TO_SCHD_ENQUEUE;
next_state <= RAISE_EXCEPTION;
else
-- Scheduler has completed the request
tm2sch_data_next <= Z32(0 to 7);
tm2sch_opcode_next <= OPCODE_NOOP;
next_state <= return_state;
end if;
when DEQUEUE_WAIT_ACK =>
-- Wait for the scheduler to acknowledge the dequeue request
if sch2tm_busy = '0' then
-- Scheduler has not yet responded
next_state <= current_state;
elsif (timeout_expired = '1') then
-- Timed out waiting for queue
Exception_Cause_next <= EXCEPTION_TO_SCHD_DEQUEUE;
next_state <= RAISE_EXCEPTION;
else
-- Scheduler has acknowledged the request
tm2sch_request_next <= '0';
tm2sch_data_next <= Z32(0 to 7);
tm2sch_opcode_next <= OPCODE_NOOP;
next_state <= DEQUEUE_WAIT_COMPLETE;
end if;
when DEQUEUE_WAIT_COMPLETE =>
-- wait for the scheduler to complete the dequeue request
if sch2tm_busy = '1' then
-- scheduler has not yet completed request
elsif (timeout_expired = '1') then
-- Timed out waiting for queue
Exception_Cause_next <= EXCEPTION_TO_SCHD_DEQUEUE;
next_state <= RAISE_EXCEPTION;
else
-- Scheduler has completed the request
tm2sch_data_next <= Z32(0 to 7);
tm2sch_opcode_next <= OPCODE_NOOP;
next_state <= return_state;
end if;
when IS_QUEUE_EMPTY_WAIT_ACK =>
-- Wait for the scheduler to acknowledge the is queue empty request
if sch2tm_busy = '0' then
-- Scheduler has not yet responded
next_state <= current_state;
elsif (timeout_expired = '1') then
-- Timed out waiting for queue
Exception_Cause_next <= EXCEPTION_TO_SCHD_ISEMPTY;
next_state <= RAISE_EXCEPTION;
else
-- Scheduler has acknowledged the request
tm2sch_request_next <= '0';
tm2sch_data_next <= Z32(0 to 7);
tm2sch_opcode_next <= OPCODE_NOOP;
next_state <= IS_QUEUE_EMPTY_WAIT_COMPLETE;
end if;
when IS_QUEUE_EMPTY_WAIT_COMPLETE =>
-- wait for the scheduler to complete the is queue empty request
if sch2tm_busy = '1' then
-- scheduler has not yet completed request
elsif (timeout_expired = '1') then
-- Timed out waiting for queue
Exception_Cause_next <= EXCEPTION_TO_SCHD_ISEMPTY;
next_state <= RAISE_EXCEPTION;
else
-- Scheduler has completed the request
tm2sch_data_next <= Z32(0 to 7);
tm2sch_opcode_next <= OPCODE_NOOP;
next_state <= return_state;
end if;
when YIELD_THREAD_INIT =>
-- Retrieve the status of the current cpu thread
ADDRA <= '0' & current_cpu_thread(0 to 7);
ENA <= '1';
next_state <= YIELD_CURRENT_THREAD_RD_WAIT;
when YIELD_CURRENT_THREAD_RD_WAIT =>
next_state <= YIELD_CURRENT_THREAD_AVAILABLE;
when YIELD_CURRENT_THREAD_AVAILABLE =>
-- check to see if thread's status is used,~exited,~queued
if (DOA(26 to 27) = "11") then
-- check to see if the scheduler's queue is empty
tm2sch_request_next <= '1';
tm2sch_opcode_next <= OPCODE_IS_EMPTY;
tm2sch_data_next <= Z32(0 to 7);
next_state <= IS_QUEUE_EMPTY_WAIT_ACK;
return_state_next <= YIELD_CHECK_QUEUE_EMPTY;
else
-- operation failed, return error code
bus_data_out_next <= DOA(0 to 27) & ERROR_IN_STATUS;
next_state <= END_TRANSACTION;
end if;
when YIELD_CHECK_QUEUE_EMPTY =>
if (sch2tm_data(7) = '1') then
-- Queue is empty, return the current thread id
bus_data_out_next <= Z32(0 to 22) & current_cpu_thread;
next_state <= END_TRANSACTION;
else
-- Queue is not empty, add currently running thread to Q and then follow with a DEQ
next_state <= YIELD_ENQUEUE;
end if;
when YIELD_ENQUEUE =>
tm2sch_request_next <= '1';
tm2sch_opcode_next <= OPCODE_ENQUEUE;
tm2sch_data_next <= current_cpu_thread(0 to 7);
next_state <= ENQUEUE_WAIT_ACK;
return_state_next <= YIELD_CHECK_ENQUEUE;
when YIELD_CHECK_ENQUEUE =>
if (sch2tm_data(7) = '0') then
-- ENQ was successful, now DEQ to get next scheduling decision
current_cpu_thread_next <= sch2tm_next_id & '0'; -- update the currently running thread to the one that is scheduled to run next (AKA to be DEQ'd)
-- next_state <= YIELD_dummy_is_queued;
next_state <= YIELD_DEQUEUE;
else
-- ENQ failed, return error to caller
bus_data_out_next <= Z32(0 to 27) & ERROR_FROM_SCHEDULER;
next_state <= END_TRANSACTION;
end if;
-- when YIELD_dummy_is_queued =>
-- tm2sch_request_next <= '1'; -- request the dummy is_queued operation
-- tm2sch_opcode_next <= OPCODE_IS_QUEUED;
-- tm2sch_data_next <= "11111111";
-- next_state <= ISQUEUED_WAIT_ACK;
-- return_state_next <= YIELD_DEQUEUE;
when YIELD_DEQUEUE =>
tm2sch_request_next <= '1'; -- request the DEQ operation to remove the thread to run from Q
tm2sch_opcode_next <= OPCODE_DEQUEUE;
tm2sch_data_next <= Z32(0 to 7);
next_state <= DEQUEUE_WAIT_ACK;
return_state_next <= YIELD_CHECK_DEQUEUE;
when YIELD_CHECK_DEQUEUE =>
if (sch2tm_data(7) = '1') then
-- error during DEQ...
bus_data_out_next <= Z32(0 to 27) & ERROR_FROM_SCHEDULER;
next_state <= END_TRANSACTION;
else
-- DEQ completed successfully, end operation
bus_data_out_next <= Z32(0 to 22) & current_cpu_thread(0 to 7) & '0'; -- setup the return value of the next thread to run (now in the currently running thread)
next_state <= END_TRANSACTION;
end if;
when EXIT_THREAD_INIT =>
bus_data_out_next <= Z32; -- change if failure occurs
ADDRA <= '0' & Bus2IP_Addr(22 to 29);
ENA <= '1';
next_state <= EXIT_THREAD_RD_WAIT;
when EXIT_THREAD_RD_WAIT =>
next_state <= EXIT_THREAD_AVAIABLE;
when EXIT_THREAD_AVAIABLE =>
-- full entry for the current_thread is required in later states
current_status_next <= DOA(0 to 31);
ADDRA <= '0' & Bus2IP_Addr(22 to 29);
ENA <= '1';
WEA <= '1';
if (DOA(24) = '1') then
-- Thread is detached
-- Make the thread status used and exited.
DIA <= DOA(0 to 25) & "10" & DOA(28 to 31);
next_state <= END_TRANSACTION;
elsif (DOA(25) = '1') then
-- Thread is joined
-- Make the thread status used and exited, and wake the parent
DIA <= DOA(0 to 25) & "10" & DOA(28 to 31);
next_state <= EXIT_READ_PARENT;
else
-- Thread is not detached and still joinable
-- Set the thread status to used and exited
DIA <= DOA(0 to 25) & "10" & DOA(28 to 31);
next_state <= END_TRANSACTION;
end if;
when EXIT_READ_PARENT =>
-- The thread that is exiting was joined, wake the parent up
ADDRA <= '0' & current_status(16 to 23);
ENA <= '1';
next_state <= EXIT_READ_PARENT_WAIT;
when EXIT_READ_PARENT_WAIT =>
next_state <= EXIT_READ_PARENT_AVAILABLE;
when EXIT_READ_PARENT_AVAILABLE =>
-- Make sure the parent thread is used and not exited
if (DOA(26 to 27) = "11") then
-- Parent thread is used and not exited.
-- Add the parent thread tothe scheduler's queue
tm2sch_opcode_next <= OPCODE_ENQUEUE;
tm2sch_request_next <= '1';
tm2sch_data_next <= current_status(16 to 23);
return_state_next <= EXIT_CHECK_ENQUEUE;
next_state <= ENQUEUE_WAIT_ACK;
else
-- Parent thread is either unused or exited, neither of which it should be
-- operation failed, return error code
bus_data_out_next <= DOA(0 to 27) & ERROR_IN_STATUS;
next_state <= END_TRANSACTION;
end if;
when EXIT_CHECK_ENQUEUE =>
-- Check to make sure the scheduler added the thread correctly
if sch2tm_data(7) = '1' then
-- error during enqueue
bus_data_out_next <= Z32(0 to 27) & ERROR_FROM_SCHEDULER;
next_state <= END_TRANSACTION;
else
-- enqueue completed correctly
bus_data_out_next <= Z32(0 to 31);
next_state <= END_TRANSACTION;
end if;
when RAISE_EXCEPTION =>
-- NOTE !!! You must assign Exception_Cause
-- where-ever you assign next_state <= RAISE_EXCEPTION;
Exception_Address_next <= Bus2IP_Addr(0 to 31); -- save address
access_error <= '1'; -- assert interrupt
my_ack <= '1'; -- done, "ack" the bus
next_state <= END_TRANSACTION_WAIT;
when END_TRANSACTION =>
IP2Bus_Data <= bus_data_out;
my_ack <= '1'; -- done, "ack" the bus
next_state <= END_TRANSACTION_WAIT;
when END_TRANSACTION_WAIT =>
if( Bus2IP_RdCE(0)='0' and Bus2IP_WrCE(0)='0' ) then
next_state <= IDLE_STATE;
else
next_state <= current_state;
end if;
when others =>
Exception_Cause_next <= EXCEPTION_ILLEGAL_STATE;
next_state <= RAISE_EXCEPTION;
end case; -- case current_state
end process SWTM_LOGIC_PROC;
-------------------------------------------------------------------
-- ICON core instance
-------------------------------------------------------------------
-- -- simulation translate_off
-- i_icon : chipscope_icon_v1_03_a
-- port map
-- (
-- control0 => control0
-- );
-- -- simulation translate_on
--
-- COUNTER_PROC : process (Bus2IP_Clk) is
-- begin
-- if( Bus2IP_Clk'event and Bus2IP_Clk='1' ) then
-- if (Bus2IP_Reset = '1') then
-- my_counter <= (others => '0');
-- else
-- my_counter <= my_counter + 1;
-- end if;
-- end if;
-- end process COUNTER_PROC;
--
-- --
--
-- -------------------------------------------------------------------
-- -- ILA core instance
-- -------------------------------------------------------------------
--
-- -- simulation translate_off
-- i_ila : chipscope_ila_v1_02_a
-- port map
-- (
-- control => control0,
-- clk => Bus2IP_Clk,
-- trig0(63 downto 32) => Bus2IP_Data,
-- trig0(31 downto 0) => my_counter, -- 64 bits -- Add in chipscope signals and run on board!!!!
-- trig1(63 downto 32) => Bus2IP_Addr,
-- trig1(31 downto 0) => bus_data_out, -- 64 bits
-- trig2 => current_status, -- 32 bits
-- trig3 => Bus2IP_Addr, -- 32 bits
-- trig4(0) => Bus2IP_RdCE, -- 16 bits
-- trig4(1) => Bus2IP_WrCE,
-- trig4(2) => my_ack,
-- trig4(3) => my_tout_sup,
-- trig4(4) => Bus2IP_Reset,
-- trig4(5) => '0',
-- trig4(6) => tm2sch_request_reg,
-- trig4(7) => next_ID(0),
-- trig4(8) => next_ID(1),
-- trig4(9) => next_ID(2),
-- trig4(10) => next_ID(3),
-- trig4(11) => next_ID(4),
-- trig4(12) => next_ID(5),
-- trig4(13) => next_ID(6),
-- trig4(14) => next_ID(7),
-- trig4(15) => next_ID(8)
-- );
-- -- simulation translate_on
--
end IMP;
|
bsd-3-clause
|
masson2013/heterogeneous_hthreads
|
src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/ipif_common_v1_00_d/hdl/vhdl/dma_sg.vhd
|
3
|
8321
|
-------------------------------------------------------------------------------
-- $Id: dma_sg.vhd,v 1.5 2003/11/04 20:11:33 ostlerf Exp $
-------------------------------------------------------------------------------
-- dma_sg entity (DMA and scatter gather)
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: dma_sg.vhd
--
-- Description: Entity declaration for dma_sg.
-- This entity defines a DMA capability that is intended
-- for embodiement inside the IPIF (IP Interface).
--
-- Four types of DMA channels are available:
-- (1) Simple DMA
-- (2) Scatter gather DMA
-- (3) Scatter gather packet transmit
-- (4) Scatter gather packet receive
--
-- An arbitrary number of channels, each of any of the types,
-- may be included in an instantiation through appropriate
-- generic settings.
--
-- Packet transmit and receive channels may be outfitted with
-- optional interrupt-coalescing support.
--
-- The maximum length of DMA transfers is user selectable and
-- using the smallest feasible value may reduce FPGA resource
-- usage.
--
-------------------------------------------------------------------------------
-- Structure:
--
-- dma_sg.vhds
-- dma_sg_pkg.vhds
--
-------------------------------------------------------------------------------
-- Author: Farrell Ostler
-- History:
-- FLO 12/19/01 -- Header added
-- -- Channels fixed at two for this version
-- -- to allow XST E.33 compatibility.
--
-- FLO 06/07/02 -- Added generic C_WFIFO_VACANCY_WIDTH.
--
-- FLO 01/30/03
-- ^^^^^^
-- Fixed Bus2IP_Data and DMA2Bus_Data at 32 bits, 0 to 31.
-- Fixed Bus2IP_BE 4 bits, 0 to 3.
-- ~~~~~~
--
-- FLO 03/02/03
-- ^^^^^^
-- Added signal DMA2Bus_MstLoc2Loc.
-- ~~~~~~
--
-- FLO 05/15/2003
-- ^^^^^^
-- Added generics C_DMA_SHORT_BURST_REMAINDER and C_DMA_BURST_SIZE.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library ipif_common_v1_00_d;
use ipif_common_v1_00_d.ipif_pkg.SLV64_ARRAY_TYPE;
use ipif_common_v1_00_d.ipif_pkg.INTEGER_ARRAY_TYPE;
library proc_common_v1_00_b;
use proc_common_v1_00_b.proc_common_pkg.log2;
entity dma_sg is
-- Four channel, 0123, simple sg tx rx coalesc.
generic (
C_OPB_DWIDTH : natural := 32; -- Width of data bus (32, 64).
C_OPB_AWIDTH : natural := 32; -- width of Bus addr.
C_IPIF_ABUS_WIDTH : natural :=15;
C_CLK_PERIOD_PS : integer := 16000; --ps Period of Bus2IP_Clk.
-- The time unit, in nanoseconds, that applies to
-- the Packet Wait Bound register. The specified value of this
-- generic is 1,000,000 (1 ms), but a smaller value can be used for
-- simulations.
C_PACKET_WAIT_UNIT_NS : integer := 1000000; --ns
C_DMA_CHAN_TYPE -- 0=simple, 1=sg, 2=tx, 3=rx
: INTEGER_ARRAY_TYPE
:= ( 0, 1, 2, 3 );
-- The leftmost defined bit of the LENGTH field, assuming
-- big endian bit numbering and a LSB at bit 31.
-- If the channel is a packet channel, it is assumed that
-- the number bits defined in the LENGTH register is also
-- enough bits to hold the length of a maximum sized packet.
-- ToDo, current impl requires all channels to be the same length.
C_DMA_LENGTH_WIDTH
: INTEGER_ARRAY_TYPE
:= ( 11, 11, 11, 11 );
C_LEN_FIFO_ADDR
: SLV64_ARRAY_TYPE
:= ( X"0000_0000_0000_0000",
X"0000_0000_0000_0000",
X"0000_0000_0000_3800",
X"0000_0000_0000_4800" );
C_STAT_FIFO_ADDR
: SLV64_ARRAY_TYPE
:= ( X"0000_0000_0000_0000",
X"0000_0000_0000_0000",
X"0000_0000_0000_3804",
X"0000_0000_0000_4804" );
C_INTR_COALESCE
: INTEGER_ARRAY_TYPE
:= ( 0, 0, 1, 1 );
C_DEV_BLK_ID : integer := 0;
C_DMA_BASEADDR : std_logic_vector
:= X"0000_0000_0000_0000";
C_DMA_BURST_SIZE: positive := 16; -- Must be a power of 2
C_DMA_SHORT_BURST_REMAINDER : integer := 1;
C_MA2SA_NUM_WIDTH : INTEGER := 8;
C_WFIFO_VACANCY_WIDTH : integer := 10
);
port (
DMA2Bus_Data : out std_logic_vector(0 to 31);
DMA2Bus_Addr : out std_logic_vector(0 to C_OPB_AWIDTH-1 );
DMA2Bus_MstBE : out std_logic_vector(0 to C_OPB_DWIDTH/8 - 1);
DMA2Bus_MstWrReq : out std_logic;
DMA2Bus_MstRdReq : out std_logic;
DMA2Bus_MstNum : out std_logic_vector(0 to C_MA2SA_NUM_WIDTH-1);
DMA2Bus_MstBurst : out std_logic;
DMA2Bus_MstBusLock : out std_logic;
DMA2Bus_MstLoc2Loc : out std_logic;
DMA2IP_Addr : out std_logic_vector(0 to C_IPIF_ABUS_WIDTH-3);
DMA2Bus_WrAck : out std_logic;
DMA2Bus_RdAck : out std_logic;
DMA2Bus_Retry : out std_logic;
DMA2Bus_Error : out std_logic;
DMA2Bus_ToutSup : out std_logic;
Bus2IP_MstWrAck : in std_logic;
Bus2IP_MstRdAck : in std_logic;
Mstr_sel_ma : in std_logic;
Bus2IP_MstRetry : in std_logic;
Bus2IP_MstError : in std_logic;
Bus2IP_MstTimeOut : in std_logic;
Bus2IP_BE : in std_logic_vector(0 to 3);
Bus2IP_WrReq : in std_logic;
Bus2IP_RdReq : in std_logic;
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Freeze : in std_logic;
Bus2IP_Addr : in std_logic_vector(0 to C_IPIF_ABUS_WIDTH-3);
Bus2IP_Data : in std_logic_vector(0 to 31);
Bus2IP_Burst : in std_logic;
WFIFO2DMA_Vacancy : in std_logic_vector(0 to C_WFIFO_VACANCY_WIDTH-1);
Bus2IP_MstLastAck : in std_logic;
DMA_RdCE : in std_logic;
DMA_WrCE : in std_logic;
IP2DMA_RxStatus_Empty : in std_logic;
IP2DMA_RxLength_Empty : in std_logic;
IP2DMA_TxStatus_Empty : in std_logic;
IP2DMA_TxLength_Full : in std_logic;
IP2Bus_DMA_Req : in std_logic;
Bus2IP_DMA_Ack : out std_logic;
DMA2Intr_Intr : out std_logic_vector(0 to C_DMA_CHAN_TYPE'length-1)
);
constant TPB : positive := C_DMA_BURST_SIZE;
end dma_sg;
|
bsd-3-clause
|
masson2013/heterogeneous_hthreads
|
src/hardware/MyRepository/pcores/hw_acc_vector_v1_00_a/hdl/vhdl/user_logic_hwtulslow.vhd
|
2
|
17884
|
--First version. It takes 6 cycle to process a data.
--accm
-- ************************************
-- Automatically Generated FSM
-- vector_chan
-- ************************************
-- **********************
-- Library inclusions
-- **********************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
-- **********************
-- Entity Definition
-- **********************
entity vector_chan is
generic(
G_ADDR_WIDTH : integer := 32;
G_DATA_WIDTH : integer := 32;
OPCODE_BITS : integer := 6;
FUNC_BITS : integer := 6
);
port
(
Vector_A_addr0 : out std_logic_vector(0 to (G_ADDR_WIDTH - 1));
Vector_A_dIN0 : out std_logic_vector(0 to (G_DATA_WIDTH - 1));
Vector_A_dOUT0 : in std_logic_vector(0 to (G_DATA_WIDTH - 1));
Vector_A_rENA0 : out std_logic;
Vector_A_wENA0 : out std_logic_vector(0 to (G_DATA_WIDTH/8) -1);
Vector_B_addr0 : out std_logic_vector(0 to (G_ADDR_WIDTH - 1));
Vector_B_dIN0 : out std_logic_vector(0 to (G_DATA_WIDTH - 1));
Vector_B_dOUT0 : in std_logic_vector(0 to (G_DATA_WIDTH - 1));
Vector_B_rENA0 : out std_logic;
Vector_B_wENA0 : out std_logic_vector(0 to (G_DATA_WIDTH/8) -1);
Vector_C_addr0 : out std_logic_vector(0 to (G_ADDR_WIDTH - 1));
Vector_C_dIN0 : out std_logic_vector(0 to (G_DATA_WIDTH - 1));
Vector_C_dOUT0 : in std_logic_vector(0 to (G_DATA_WIDTH - 1));
Vector_C_rENA0 : out std_logic;
Vector_C_wENA0 : out std_logic_vector(0 to (G_DATA_WIDTH/8) -1);
chan1_channelDataIn : out std_logic_vector(0 to (32 - 1));
chan1_channelDataOut : in std_logic_vector(0 to (32 - 1));
chan1_exists : in std_logic;
chan1_full : in std_logic;
chan1_channelRead : out std_logic;
chan1_channelWrite : out std_logic;
clock_sig : in std_logic;
reset_sig : in std_logic
);
end entity vector_chan;
-- *************************
-- Architecture Definition
-- *************************
architecture IMPLEMENTATION of vector_chan is
component infer_bram
generic
(
ADDRESS_BITS : integer := 9;
DATA_BITS : integer := 32
);
port (
CLKA : in std_logic;
ENA : in std_logic;
WEA : in std_logic;
ADDRA : in std_logic_vector(0 to (ADDRESS_BITS - 1));
DIA : in std_logic_vector(0 to (DATA_BITS - 1));
DOA : out std_logic_vector(0 to (DATA_BITS - 1));
CLKB : in std_logic;
ENB : in std_logic;
WEB : in std_logic;
ADDRB : in std_logic_vector(0 to (ADDRESS_BITS - 1));
DIB : in std_logic_vector(0 to (DATA_BITS - 1));
DOB : out std_logic_vector(0 to (DATA_BITS - 1))
);
end component infer_BRAM;
-- ****************************************************
-- Type definitions for state signals
-- ****************************************************
type STATE_MACHINE_TYPE is
(
reset,
fetch,
get_instr,
read_size,
read_index,
decode,
defunc,
halt,
addv_for_loop,
extra1,
addv_ALU,
addv_write_back,
mulv_for_loop,
extra2,
mulv_ALU,
mulv_write_back,
redv_for_loop,
extra3,
redv_ALU,
redv_write_back,
before_fetch,
xxx,
after_read_size
);
signal current_state,next_state: STATE_MACHINE_TYPE :=reset;
-- ****************************************************
-- Type definitions for FSM signals
-- ****************************************************
signal in_Vector_A_addr0 : std_logic_vector(0 to (G_ADDR_WIDTH - 1));
signal in_Vector_B_addr0 : std_logic_vector(0 to (G_ADDR_WIDTH - 1));
signal in_Vector_C_addr0 : std_logic_vector(0 to (G_ADDR_WIDTH - 1));
signal swapped, swapped_next : std_logic;
signal i, i_next : std_logic_vector(0 to G_ADDR_WIDTH - 1);
signal n, n_next : std_logic_vector(0 to G_DATA_WIDTH - 1);
signal n_new, n_new_next : std_logic_vector(0 to G_DATA_WIDTH - 1);
signal instruction, instruction_next : std_logic_vector(0 to G_DATA_WIDTH - 1);
signal index, index_next : std_logic_vector(0 to G_DATA_WIDTH - 1);
signal ret, ret_next : std_logic_vector(0 to G_DATA_WIDTH - 1);
signal dataA1, dataA1_next : std_logic_vector(0 to G_DATA_WIDTH - 1);
signal dataA2, dataA2_next : std_logic_vector(0 to G_DATA_WIDTH - 1);
signal dataB1, dataB1_next : std_logic_vector(0 to G_DATA_WIDTH - 1);
signal dataB2, dataB2_next : std_logic_vector(0 to G_DATA_WIDTH - 1);
signal dataC1, dataC1_next : std_logic_vector(0 to G_DATA_WIDTH - 1);
signal dataC2, dataC2_next : std_logic_vector(0 to G_DATA_WIDTH - 1);
signal dataMUL, dataMUL_next : std_logic_vector(0 to G_DATA_WIDTH + G_DATA_WIDTH - 1);
signal op, op_next : std_logic_vector(0 to 5);
signal rs, rs_next : std_logic_vector(0 to 4);
signal rt, rt_next : std_logic_vector(0 to 4);
signal rd, rd_next : std_logic_vector(0 to 4);
signal sh, sh_next : std_logic_vector(0 to 4);
signal fn, fn_next : std_logic_vector(0 to 5);
-- ****************************************************
-- User-defined VHDL Section
-- ****************************************************
constant OP_R : std_logic_vector(0 to OPCODE_BITS-1) := "000000";
constant FN_NOP : std_logic_vector(0 to FUNC_BITS-1) := "000000"; -- 0/00H
constant FN_ADDV : std_logic_vector(0 to FUNC_BITS-1) := "110000"; -- 0/30H
constant FN_MULV : std_logic_vector(0 to FUNC_BITS-1) := "110001"; -- 0/31
constant FN_REDV : std_logic_vector(0 to FUNC_BITS-1) := "110010"; -- 0/32
--constant OP_NOP : std_logic_vector(0 to OPCODE_BITS-1) := x"0";
--constant OP_ADD : std_logic_vector(0 to OPCODE_BITS-1) := x"1";
--constant OP_SUB : std_logic_vector(0 to OPCODE_BITS-1) := x"2";
--constant OP_ADDi : std_logic_vector(0 to OPCODE_BITS-1) := x"3";
--constant OP_SUBi : std_logic_vector(0 to OPCODE_BITS-1) := x"4";
--constant OP_ADDV : std_logic_vector(0 to OPCODE_BITS-1) := x"5";
--constant OP_SUBV : std_logic_vector(0 to OPCODE_BITS-1) := x"6";
--constant OP_ADDVS : std_logic_vector(0 to OPCODE_BITS-1) := x"7";
--constant OP_SUBVS : std_logic_vector(0 to OPCODE_BITS-1) := x"8";
--constant OP_SNEV : std_logic_vector(0 to OPCODE_BITS-1) := x"9";
--constant OP_SNEVS : std_logic_vector(0 to OPCODE_BITS-1) := x"A";
--constant OP_SLTV : std_logic_vector(0 to OPCODE_BITS-1) := x"B";
--constant OP_SLTVS : std_logic_vector(0 to OPCODE_BITS-1) := x"C";
--constant OP_CVM : std_logic_vector(0 to OPCODE_BITS-1) := x"D";
--constant OP_SVLR : std_logic_vector(0 to OPCODE_BITS-1) := x"E";
--constant OP_SVMR : std_logic_vector(0 to OPCODE_BITS-1) := x"F";
-- Architecture Section
begin
-- ************************
-- Permanent Connections
-- ************************
Vector_A_addr0 <= in_Vector_A_addr0(2 to 31) & "00";
Vector_B_addr0 <= in_Vector_B_addr0(2 to 31) & "00";
Vector_C_addr0 <= in_Vector_C_addr0(2 to 31) & "00";
-- ************************
-- BRAM implementations
-- ************************
-- ****************************************************
-- Process to handle the synchronous portion of an FSM
-- ****************************************************
FSM_SYNC_PROCESS : process(
swapped_next,
i_next,
n_next,
n_new_next,
instruction_next,
index_next,
ret_next,
dataA1_next,
dataA2_next,
dataB1_next,
dataB2_next,
dataC1_next,
dataC2_next,
dataMUL_next,
op_next,
rs_next,
rt_next,
rd_next,
sh_next,
fn_next,
next_state,
clock_sig, reset_sig) is
begin
if (clock_sig'event and clock_sig = '1') then
if (reset_sig = '1') then
-- Reset all FSM signals, and enter the initial state
swapped <= '0';
i <= (others => '0');
n <= (others => '0');
n_new <= (others => '0');
instruction <= (others => '0');
index <= (others => '0');
ret <= (others => '0');
dataA1 <= (others => '0');
dataA2 <= (others => '0');
dataB1 <= (others => '0');
dataB2 <= (others => '0');
dataC1 <= (others => '0');
dataC2 <= (others => '0');
dataMUL <= (others => '0');
op <= (others => '0');
rs <= (others => '0');
rt <= (others => '0');
rd <= (others => '0');
sh <= (others => '0');
fn <= (others => '0');
current_state <= reset;
else
-- Transition to next state
swapped <= swapped_next;
i <= i_next;
n <= n_next;
n_new <= n_new_next;
instruction <= instruction_next;
index <= index_next;
ret <= ret_next;
dataA1 <= dataA1_next;
dataA2 <= dataA2_next;
dataB1 <= dataB1_next;
dataB2 <= dataB2_next;
dataC1 <= dataC1_next;
dataC2 <= dataC2_next;
dataMUL <= dataMUL_next;
op <= op_next;
rs <= rs_next;
rt <= rt_next;
rd <= rd_next;
sh <= sh_next;
fn <= fn_next;
current_state <= next_state;
end if;
end if;
end process FSM_SYNC_PROCESS;
-- ************************************************************************
-- Process to handle the asynchronous (combinational) portion of an FSM
-- ************************************************************************
FSM_COMB_PROCESS : process(
Vector_A_dOUT0,
Vector_B_dOUT0,
Vector_C_dOUT0,
chan1_channelDataOut, chan1_full, chan1_exists,
swapped,
i,
n,
n_new,
instruction,
index,
ret,
dataA1,
dataA2,
dataB1,
dataB2,
dataC1,
dataC2,
dataMUL,
op,
rs,
rt,
rd,
sh,
fn,
current_state) is
begin
-- Default signal assignments
swapped_next <= swapped;
i_next <= i;
n_next <= n;
n_new_next <= n_new;
instruction_next <= instruction;
index_next <= index;
ret_next <= ret;
dataA1_next <= dataA1;
dataA2_next <= dataA2;
dataB1_next <= dataB1;
dataB2_next <= dataB2;
dataC1_next <= dataC1;
dataC2_next <= dataC2;
dataMUL_next <= dataMUL;
op_next <= op;
rs_next <= rs;
rt_next <= rt;
rd_next <= rd;
sh_next <= sh;
fn_next <= fn;
in_Vector_A_addr0 <= (others => '0');
Vector_A_dIN0 <= (others => '0');
Vector_A_rENA0 <= '0';
Vector_A_wENA0 <= (others => '0');
in_Vector_B_addr0 <= (others => '0');
Vector_B_dIN0 <= (others => '0');
Vector_B_rENA0 <= '0';
Vector_B_wENA0 <= (others => '0');
in_Vector_C_addr0 <= (others => '0');
Vector_C_dIN0 <= (others => '0');
Vector_C_rENA0 <= '0';
Vector_C_wENA0 <= (others => '0');
chan1_channelDataIn <= (others => '0');
chan1_channelRead <= '0';
chan1_channelWrite <= '0';
next_state <= current_state;
-- FSM logic
case (current_state) is
when addv_ALU =>
dataC1_next <= dataA1 + dataB1;
next_state <= addv_write_back;
when addv_for_loop =>
if ( i >= n ) then
next_state <= halt;
elsif ( i < n ) then
in_Vector_A_addr0 <= i;
Vector_A_rENA0 <= '1';
in_Vector_B_addr0 <= i;
Vector_B_rENA0 <= '1';
next_state <= extra1;
end if;
when addv_write_back =>
i_next <= i + 1;
in_Vector_C_addr0 <= i;
Vector_C_dIN0 <= dataC1;
Vector_C_wENA0 <= (others => '1');
Vector_C_rENA0 <= '1';
next_state <= addv_for_loop;
when decode =>
if ( op = OP_R ) then
next_state <= defunc;
end if;
when defunc =>
if ( fn = FN_NOP ) then
next_state <= halt;
elsif ( fn = FN_ADDV ) then
i_next <= index;
next_state <= addv_for_loop;
elsif ( fn = FN_MULV ) then
i_next <= index;
next_state <= mulv_for_loop;
elsif ( fn = FN_REDV ) then
i_next <= index;
next_state <= redv_for_loop;
end if;
when extra1 =>
dataB1_next <= Vector_B_dOUT0;
dataA1_next <= Vector_A_dOUT0;
next_state <= addv_ALU;
when extra2 =>
dataB1_next <= Vector_B_dOUT0;
dataA1_next <= Vector_A_dOUT0;
next_state <= mulv_ALU;
when extra3 =>
dataB1_next <= Vector_B_dOUT0;
dataA1_next <= Vector_A_dOUT0;
next_state <= redv_ALU;
when fetch =>
if chan1_exists = '0' then
next_state <= fetch;
elsif chan1_exists /= '0' then
instruction_next <= chan1_channelDataOut;
chan1_channelRead <= '1';
next_state <= get_instr;
i_next <= (others => '0');
end if;
when get_instr =>
ret_next <= (others => '0');
fn_next <= instruction(26 to 31);
sh_next <= instruction(21 to 25);
rt_next <= instruction(16 to 20);
rs_next <= instruction(11 to 15);
rd_next <= instruction(6 to 10);
op_next <= instruction(0 to 5);
next_state <= read_size;
when halt =>
next_state <= before_fetch;
i_next <= (others => '0');
when before_fetch =>
if (i >=n) then
next_state <= xxx;
else
i_next <= i +1;
in_Vector_C_addr0 <= i;
Vector_C_rENA0 <= '1';
end if;
when xxx =>
if chan1_full /= '0' then
next_state <= xxx;
elsif chan1_full = '0' then
chan1_channelDataIn <= ret;
chan1_channelWrite <= '1';
next_state <= fetch;
end if;
when mulv_ALU =>
dataMUL_next <= dataA1 * dataB1;
next_state <= mulv_write_back;
when mulv_for_loop =>
if ( i >= n ) then
next_state <= halt;
elsif ( i < n ) then
in_Vector_A_addr0 <= i;
Vector_A_rENA0 <= '1';
in_Vector_B_addr0 <= i;
Vector_B_rENA0 <= '1';
next_state <= extra2;
end if;
when mulv_write_back =>
i_next <= i + 1;
in_Vector_C_addr0 <= i;
Vector_C_dIN0 <= dataMUL(32 to 63);
Vector_C_wENA0 <= (others => '1');
Vector_C_rENA0 <= '1';
next_state <= mulv_for_loop;
when read_index =>
if chan1_exists = '0' then
next_state <= read_index;
elsif chan1_exists /= '0' then
index_next <= chan1_channelDataOut;
chan1_channelRead <= '1';
next_state <= decode;
end if;
when read_size =>
if chan1_exists = '0' then
next_state <= read_size;
elsif chan1_exists /= '0' then
n_next <= chan1_channelDataOut;
chan1_channelRead <= '1';
next_state <= after_read_size;
end if;
when after_read_size =>
if (i >=n) then
next_state <= read_index;
else
i_next <= i +1;
in_Vector_C_addr0 <= i;
Vector_C_rENA0 <= '1';
end if;
when redv_ALU =>
dataMUL_next <= dataA1 * dataB1;
next_state <= redv_write_back;
when redv_for_loop =>
if ( i >= n ) then
next_state <= halt;
elsif ( i < n ) then
in_Vector_A_addr0 <= i;
Vector_A_rENA0 <= '1';
in_Vector_B_addr0 <= i;
Vector_B_rENA0 <= '1';
next_state <= extra3;
end if;
when redv_write_back =>
i_next <= i + 1;
ret_next <= ret + dataMUL(32 to 63);
next_state <= redv_for_loop;
when reset =>
next_state <= fetch;
when others =>
next_state <= reset;
end case;
end process FSM_COMB_PROCESS;
end architecture IMPLEMENTATION;
-- $$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$
-- $$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$
-- ************************************************
-- Entity used for implementing the inferred BRAMs
-- ************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_misc.all;
use IEEE.numeric_std.all;
-- *************************************************************************
-- Entity declaration
-- *************************************************************************
entity infer_bram is
generic (
ADDRESS_BITS : integer := 9;
DATA_BITS : integer := 32
);
port (
CLKA : in std_logic;
ENA : in std_logic;
WEA : in std_logic;
ADDRA : in std_logic_vector(0 to (ADDRESS_BITS - 1));
DIA : in std_logic_vector(0 to (DATA_BITS - 1));
DOA : out std_logic_vector(0 to (DATA_BITS - 1));
CLKB : in std_logic;
ENB : in std_logic;
WEB : in std_logic;
ADDRB : in std_logic_vector(0 to (ADDRESS_BITS - 1));
DIB : in std_logic_vector(0 to (DATA_BITS - 1));
DOB : out std_logic_vector(0 to (DATA_BITS - 1))
);
end entity infer_bram;
-- *************************************************************************
-- Architecture declaration
-- *************************************************************************
architecture implementation of infer_bram is
-- Constant declarations
constant BRAM_SIZE : integer := 2 **ADDRESS_BITS; -- # of entries in the inferred BRAM
-- BRAM data storage (array)
type bram_storage is array( 0 to BRAM_SIZE - 1 ) of std_logic_vector( 0 to DATA_BITS - 1 );
shared variable BRAM_DATA : bram_storage;
-- attribute ram_style : string;
-- attribute ram_style of BRAM_DATA : signal is "block";
begin
-- *************************************************************************
-- Process: BRAM_CONTROLLER_A
-- Purpose: Controller for Port A of inferred dual-port BRAM, BRAM_DATA
-- *************************************************************************
BRAM_CONTROLLER_A : process(CLKA) is
begin
if( CLKA'event and CLKA = '1' ) then
if( ENA = '1' ) then
if( WEA = '1' ) then
BRAM_DATA( conv_integer(ADDRA) ) := DIA;
end if;
DOA <= BRAM_DATA( conv_integer(ADDRA) );
end if;
end if;
end process BRAM_CONTROLLER_A;
-- *************************************************************************
-- Process: BRAM_CONTROLLER_B
-- Purpose: Controller for Port B of inferred dual-port BRAM, BRAM_DATA
-- *************************************************************************
BRAM_CONTROLLER_B : process(CLKB) is
begin
if( CLKB'event and CLKB = '1' ) then
if( ENB = '1' ) then
if( WEB = '1' ) then
BRAM_DATA( conv_integer(ADDRB) ) := DIB;
end if;
DOB <= BRAM_DATA( conv_integer(ADDRB) );
end if;
end if;
end process BRAM_CONTROLLER_B;
end architecture implementation;
|
bsd-3-clause
|
masson2013/heterogeneous_hthreads
|
src/hardware/MyRepository/pcores/axi_hthread_cores/proc_common_v3_00_a/hdl/vhdl/pselect_f.vhd
|
2
|
12541
|
-------------------------------------------------------------------------------
-- $Id: pselect_f.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pselect_f.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pselect_f.vhd
--
-- Description:
-- (Note: At least as early as I.31, XST implements a carry-
-- chain structure for most decoders when these are coded in
-- inferrable VHLD. An example of such code can be seen
-- below in the "INFERRED_GEN" Generate Statement.
--
-- -> New code should not need to instantiate pselect-type
-- components.
--
-- -> Existing code can be ported to Virtex5 and later by
-- replacing pselect instances by pselect_f instances.
-- As long as the C_FAMILY parameter is not included
-- in the Generic Map, an inferred implementation
-- will result.
--
-- -> If the designer wishes to force an explicit carry-
-- chain implementation, pselect_f can be used with
-- the C_FAMILY parameter set to the target
-- Xilinx FPGA family.
-- )
--
-- Parameterizeable peripheral select (address decode).
-- AValid qualifier comes in on Carry In at bottom
-- of carry chain.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: pselect_f.vhd
-- family_support.vhd
--
-------------------------------------------------------------------------------
-- History:
-- Vaibhav & FLO 05/26/06 First Version
--
-- DET 1/17/2008 v3_00_a
-- ~~~~~~
-- - Changed proc_common library version to v3_00_a
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.family_support.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_AB -- number of address bits to decode
-- C_AW -- width of address bus
-- C_BAR -- base address of peripheral (peripheral select
-- is asserted when the C_AB most significant
-- address bits match the C_AB most significant
-- C_BAR bits
-- Definition of Ports:
-- A -- address input
-- AValid -- address qualifier
-- CS -- peripheral select
-------------------------------------------------------------------------------
entity pselect_f is
generic (
C_AB : integer := 9;
C_AW : integer := 32;
C_BAR : std_logic_vector;
C_FAMILY : string := "nofamily"
);
port (
A : in std_logic_vector(0 to C_AW-1);
AValid : in std_logic;
CS : out std_logic
);
end entity pselect_f;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of pselect_f is
component MUXCY is
port (
O : out std_logic;
CI : in std_logic;
DI : in std_logic;
S : in std_logic
);
end component MUXCY;
constant NLS : natural := native_lut_size(C_FAMILY);
constant USE_INFERRED : boolean := not supported(C_FAMILY, u_MUXCY)
or NLS=0 -- LUT not supported.
or C_AB <= NLS; -- Just one LUT
-- needed.
-----------------------------------------------------------------------------
-- C_BAR may not be indexed from 0 and may not be ascending;
-- BAR recasts C_BAR to have these properties.
-----------------------------------------------------------------------------
constant BAR : std_logic_vector(0 to C_BAR'length-1) := C_BAR;
type bo2sl_type is array (boolean) of std_logic;
constant bo2sl : bo2sl_type := (false => '0', true => '1');
function min(i, j: integer) return integer is
begin
if i<j then return i; else return j; end if;
end;
begin
------------------------------------------------------------------------------
-- Check that the generics are valid.
------------------------------------------------------------------------------
-- synthesis translate_off
assert (C_AB <= C_BAR'length) and (C_AB <= C_AW)
report "pselect_f generic error: " &
"(C_AB <= C_BAR'length) and (C_AB <= C_AW)" &
" does not hold."
severity failure;
-- synthesis translate_on
------------------------------------------------------------------------------
-- Build a behavioral decoder
------------------------------------------------------------------------------
INFERRED_GEN : if (USE_INFERRED = TRUE ) generate
begin
XST_WA:if C_AB > 0 generate
CS <= AValid when A(0 to C_AB-1) = BAR (0 to C_AB-1) else
'0' ;
end generate XST_WA;
PASS_ON_GEN:if C_AB = 0 generate
CS <= AValid ;
end generate PASS_ON_GEN;
end generate INFERRED_GEN;
------------------------------------------------------------------------------
-- Build a structural decoder using the fast carry chain
------------------------------------------------------------------------------
GEN_STRUCTURAL_A : if (USE_INFERRED = FALSE ) generate
constant NUM_LUTS : integer := (C_AB+(NLS-1))/NLS;
signal lut_out : std_logic_vector(0 to NUM_LUTS); -- XST workaround
signal carry_chain : std_logic_vector(0 to NUM_LUTS);
begin
carry_chain(NUM_LUTS) <= AValid; -- Initialize start of carry chain.
CS <= carry_chain(0); -- Assign end of carry chain to output.
XST_WA: if NUM_LUTS > 0 generate -- workaround for XST
begin
GEN_DECODE: for i in 0 to NUM_LUTS-1 generate
constant NI : natural := i;
constant BTL : positive := min(NLS, C_AB-NI*NLS);-- num Bits This LUT
begin
lut_out(i) <= bo2sl(A(NI*NLS to NI*NLS+BTL-1) = -- LUT
BAR(NI*NLS to NI*NLS+BTL-1));
MUXCY_I: component MUXCY -- MUXCY
port map (
O => carry_chain(i),
CI => carry_chain(i+1),
DI => '0',
S => lut_out(i)
);
end generate GEN_DECODE;
end generate XST_WA;
end generate GEN_STRUCTURAL_A;
end imp;
|
bsd-3-clause
|
masson2013/heterogeneous_hthreads
|
src/hardware/MyRepository/pcores/hw_acc_crc_v1_00_a/hdl/vhdl/user_logic_withoutbram.vhd
|
2
|
8227
|
-- ************************************
-- Automatically Generated FSM
-- crc_channel
-- ************************************
-- **********************
-- Library inclusions
-- **********************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
-- **********************
-- Entity Definition
-- **********************
entity crc_channel is
generic(
G_INPUT_WIDTH : integer := 32;
G_DIVISOR_WIDTH : integer := 4;
divisor : std_logic_vector(0 to 3) := "1011"
);
port
(
fsl1_channelDataIn : out std_logic_vector(0 to (G_INPUT_WIDTH - 1));
fsl1_channelDataOut : in std_logic_vector(0 to (G_INPUT_WIDTH - 1));
fsl1_exists : in std_logic;
fsl1_full : in std_logic;
fsl1_channelRead : out std_logic;
fsl1_channelWrite : out std_logic;
clock_sig : in std_logic;
reset_sig : in std_logic
);
end entity crc_channel;
-- *************************
-- Architecture Definition
-- *************************
architecture IMPLEMENTATION of crc_channel is
component infer_bram
generic
(
ADDRESS_BITS : integer := 9;
DATA_BITS : integer := 32
);
port (
CLKA : in std_logic;
ENA : in std_logic;
WEA : in std_logic;
ADDRA : in std_logic_vector(0 to (ADDRESS_BITS - 1));
DIA : in std_logic_vector(0 to (DATA_BITS - 1));
DOA : out std_logic_vector(0 to (DATA_BITS - 1));
CLKB : in std_logic;
ENB : in std_logic;
WEB : in std_logic;
ADDRB : in std_logic_vector(0 to (ADDRESS_BITS - 1));
DIB : in std_logic_vector(0 to (DATA_BITS - 1));
DOB : out std_logic_vector(0 to (DATA_BITS - 1))
);
end component infer_BRAM;
-- ****************************************************
-- Type definitions for state signals
-- ****************************************************
type STATE_MACHINE_TYPE is
(
reset,
idle,
do_crc
);
signal current_state,next_state: STATE_MACHINE_TYPE :=reset;
-- ****************************************************
-- Type definitions for FSM signals
-- ****************************************************
signal i, i_next : std_logic_vector(0 to 7);
signal result, result_next : std_logic_vector(0 to G_INPUT_WIDTH - 1);
-- ****************************************************
-- User-defined VHDL Section
-- ****************************************************
-- Architecture Section
begin
-- ************************
-- Permanent Connections
-- ************************
-- ************************
-- BRAM implementations
-- ************************
-- ****************************************************
-- Process to handle the synchronous portion of an FSM
-- ****************************************************
FSM_SYNC_PROCESS : process(
i_next,
result_next,
next_state,
clock_sig, reset_sig) is
begin
if (clock_sig'event and clock_sig = '1') then
if (reset_sig = '1') then
-- Reset all FSM signals, and enter the initial state
i <= (others => '0');
result <= (others => '0');
current_state <= reset;
else
-- Transition to next state
i <= i_next;
result <= result_next;
current_state <= next_state;
end if;
end if;
end process FSM_SYNC_PROCESS;
-- ************************************************************************
-- Process to handle the asynchronous (combinational) portion of an FSM
-- ************************************************************************
FSM_COMB_PROCESS : process(
fsl1_channelDataOut, fsl1_full, fsl1_exists,
i,
result,
current_state) is
begin
-- Default signal assignments
i_next <= i;
result_next <= result;
fsl1_channelDataIn <= (others => '0');
fsl1_channelRead <= '0';
fsl1_channelWrite <= '0';
next_state <= current_state;
-- FSM logic
case (current_state) is
when do_crc =>
if ( i < G_INPUT_WIDTH - G_DIVISOR_WIDTH + 1 ) and ( result(conv_integer(i)) = '0' ) then
i_next <= i + 1;
next_state <= do_crc;
elsif ( i < G_INPUT_WIDTH - G_DIVISOR_WIDTH + 1 ) then
result_next(conv_integer(i) to conv_integer(i) + ( G_DIVISOR_WIDTH - 1 )) <= result(conv_integer(i) to conv_integer(i) + ( G_DIVISOR_WIDTH - 1 )) xor divisor;
i_next <= i + 1;
next_state <= do_crc;
elsif fsl1_full /= '0' then
next_state <= do_crc;
elsif fsl1_full = '0' then
fsl1_channelDataIn <= result;
fsl1_channelWrite <= '1';
next_state <= idle;
end if;
when idle =>
if fsl1_exists = '0' then
next_state <= idle;
elsif fsl1_exists /= '0' then
i_next <= conv_std_logic_vector(0,8);
result_next <= fsl1_channelDataOut;
fsl1_channelRead <= '1';
next_state <= do_crc;
end if;
when reset =>
next_state <= idle;
when others =>
next_state <= reset;
end case;
end process FSM_COMB_PROCESS;
end architecture IMPLEMENTATION;
-- $$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$
-- $$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$
-- ************************************************
-- Entity used for implementing the inferred BRAMs
-- ************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_misc.all;
use IEEE.numeric_std.all;
-- *************************************************************************
-- Entity declaration
-- *************************************************************************
entity infer_bram is
generic (
ADDRESS_BITS : integer := 9;
DATA_BITS : integer := 32
);
port (
CLKA : in std_logic;
ENA : in std_logic;
WEA : in std_logic;
ADDRA : in std_logic_vector(0 to (ADDRESS_BITS - 1));
DIA : in std_logic_vector(0 to (DATA_BITS - 1));
DOA : out std_logic_vector(0 to (DATA_BITS - 1));
CLKB : in std_logic;
ENB : in std_logic;
WEB : in std_logic;
ADDRB : in std_logic_vector(0 to (ADDRESS_BITS - 1));
DIB : in std_logic_vector(0 to (DATA_BITS - 1));
DOB : out std_logic_vector(0 to (DATA_BITS - 1))
);
end entity infer_bram;
-- *************************************************************************
-- Architecture declaration
-- *************************************************************************
architecture implementation of infer_bram is
-- Constant declarations
constant BRAM_SIZE : integer := 2 **ADDRESS_BITS; -- # of entries in the inferred BRAM
-- BRAM data storage (array)
type bram_storage is array( 0 to BRAM_SIZE - 1 ) of std_logic_vector( 0 to DATA_BITS - 1 );
shared variable BRAM_DATA : bram_storage;
-- attribute ram_style : string;
-- attribute ram_style of BRAM_DATA : signal is "block";
begin
-- *************************************************************************
-- Process: BRAM_CONTROLLER_A
-- Purpose: Controller for Port A of inferred dual-port BRAM, BRAM_DATA
-- *************************************************************************
BRAM_CONTROLLER_A : process(CLKA) is
begin
if( CLKA'event and CLKA = '1' ) then
if( ENA = '1' ) then
if( WEA = '1' ) then
BRAM_DATA( conv_integer(ADDRA) ) := DIA;
end if;
DOA <= BRAM_DATA( conv_integer(ADDRA) );
end if;
end if;
end process BRAM_CONTROLLER_A;
-- *************************************************************************
-- Process: BRAM_CONTROLLER_B
-- Purpose: Controller for Port B of inferred dual-port BRAM, BRAM_DATA
-- *************************************************************************
BRAM_CONTROLLER_B : process(CLKB) is
begin
if( CLKB'event and CLKB = '1' ) then
if( ENB = '1' ) then
if( WEB = '1' ) then
BRAM_DATA( conv_integer(ADDRB) ) := DIB;
end if;
DOB <= BRAM_DATA( conv_integer(ADDRB) );
end if;
end if;
end process BRAM_CONTROLLER_B;
end architecture implementation;
|
bsd-3-clause
|
masson2013/heterogeneous_hthreads
|
src/hardware/MyRepository/pcores/vivado_cores/acc_vadd/solution1/impl/ip/hdl/vhdl/acc_vadd.vhd
|
4
|
5291
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.2
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity acc_vadd is
port (
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
sI1_TDATA : IN STD_LOGIC_VECTOR (31 downto 0);
sI1_TVALID : IN STD_LOGIC;
sI1_TREADY : OUT STD_LOGIC;
sI2_TDATA : IN STD_LOGIC_VECTOR (31 downto 0);
sI2_TVALID : IN STD_LOGIC;
sI2_TREADY : OUT STD_LOGIC;
mO1_TDATA : OUT STD_LOGIC_VECTOR (31 downto 0);
mO1_TVALID : OUT STD_LOGIC;
mO1_TREADY : IN STD_LOGIC );
end;
architecture behav of acc_vadd is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"acc_vadd,hls_ip_2014_2,{HLS_INPUT_TYPE=c,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7k325tffg900-2,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=1.600000,HLS_SYN_LAT=0,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=0,HLS_SYN_LUT=0}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
signal ap_CS_fsm : STD_LOGIC_VECTOR (0 downto 0) := "0";
signal ap_sig_bdd_23 : BOOLEAN;
signal ap_sig_ioackin_mO1_TREADY : STD_LOGIC;
signal ap_reg_ioackin_mO1_TREADY : STD_LOGIC := '0';
signal ap_NS_fsm : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_bdd_48 : BOOLEAN;
begin
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n = '0') then
ap_CS_fsm <= ap_ST_st1_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- ap_reg_ioackin_mO1_TREADY assign process. --
ap_reg_ioackin_mO1_TREADY_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n = '0') then
ap_reg_ioackin_mO1_TREADY <= ap_const_logic_0;
else
if ((ap_ST_st1_fsm_0 = ap_CS_fsm)) then
if (not((ap_sig_bdd_23 or (ap_const_logic_0 = ap_sig_ioackin_mO1_TREADY)))) then
ap_reg_ioackin_mO1_TREADY <= ap_const_logic_0;
elsif (ap_sig_bdd_48) then
ap_reg_ioackin_mO1_TREADY <= ap_const_logic_1;
end if;
end if;
end if;
end if;
end process;
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_CS_fsm, ap_sig_bdd_23, ap_sig_ioackin_mO1_TREADY)
begin
case ap_CS_fsm is
when ap_ST_st1_fsm_0 =>
ap_NS_fsm <= ap_ST_st1_fsm_0;
when others =>
ap_NS_fsm <= "X";
end case;
end process;
-- ap_sig_bdd_23 assign process. --
ap_sig_bdd_23_assign_proc : process(sI1_TVALID, sI2_TVALID)
begin
ap_sig_bdd_23 <= ((sI1_TVALID = ap_const_logic_0) or (sI2_TVALID = ap_const_logic_0));
end process;
-- ap_sig_bdd_48 assign process. --
ap_sig_bdd_48_assign_proc : process(mO1_TREADY, ap_sig_bdd_23)
begin
ap_sig_bdd_48 <= (not(ap_sig_bdd_23) and (ap_const_logic_1 = mO1_TREADY));
end process;
-- ap_sig_ioackin_mO1_TREADY assign process. --
ap_sig_ioackin_mO1_TREADY_assign_proc : process(mO1_TREADY, ap_reg_ioackin_mO1_TREADY)
begin
if ((ap_const_logic_0 = ap_reg_ioackin_mO1_TREADY)) then
ap_sig_ioackin_mO1_TREADY <= mO1_TREADY;
else
ap_sig_ioackin_mO1_TREADY <= ap_const_logic_1;
end if;
end process;
mO1_TDATA <= std_logic_vector(unsigned(sI2_TDATA) + unsigned(sI1_TDATA));
-- mO1_TVALID assign process. --
mO1_TVALID_assign_proc : process(ap_CS_fsm, ap_sig_bdd_23, ap_reg_ioackin_mO1_TREADY)
begin
if (((ap_ST_st1_fsm_0 = ap_CS_fsm) and not(ap_sig_bdd_23) and (ap_const_logic_0 = ap_reg_ioackin_mO1_TREADY))) then
mO1_TVALID <= ap_const_logic_1;
else
mO1_TVALID <= ap_const_logic_0;
end if;
end process;
-- sI1_TREADY assign process. --
sI1_TREADY_assign_proc : process(ap_CS_fsm, ap_sig_bdd_23, ap_sig_ioackin_mO1_TREADY)
begin
if (((ap_ST_st1_fsm_0 = ap_CS_fsm) and not((ap_sig_bdd_23 or (ap_const_logic_0 = ap_sig_ioackin_mO1_TREADY))))) then
sI1_TREADY <= ap_const_logic_1;
else
sI1_TREADY <= ap_const_logic_0;
end if;
end process;
-- sI2_TREADY assign process. --
sI2_TREADY_assign_proc : process(ap_CS_fsm, ap_sig_bdd_23, ap_sig_ioackin_mO1_TREADY)
begin
if (((ap_ST_st1_fsm_0 = ap_CS_fsm) and not((ap_sig_bdd_23 or (ap_const_logic_0 = ap_sig_ioackin_mO1_TREADY))))) then
sI2_TREADY <= ap_const_logic_1;
else
sI2_TREADY <= ap_const_logic_0;
end if;
end process;
end behav;
|
bsd-3-clause
|
masson2013/heterogeneous_hthreads
|
src/platforms/xilinx/smp3_opbhwti/design/pcores/opb_ipif_v2_00_h/hdl/vhdl/pf_counter.vhd
|
3
|
5355
|
-------------------------------------------------------------------------------
-- $Id: pf_counter.vhd,v 1.2 2004/11/23 01:04:03 jcanaris Exp $
-------------------------------------------------------------------------------
-- pf_counter - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: pf_counter.vhd
--
-- Description: Implements 32-bit timer/counter
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pf_counter.vhd
--
-------------------------------------------------------------------------------
-- Author: B.L. Tise
-- Revision: $Revision: 1.2 $
-- Date: $Date: 2004/11/23 01:04:03 $
--
-- History:
-- D. Thorpe 2001-08-30 First Version
-- - adapted from B Tise MicroBlaze counters
--
-- DET 2001-09-11
-- - Added the Rst input to the pf_counter_bit component
-- LCW Nov 8, 2004 -- updated for NCSim
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
library opb_ipif_v2_00_h;
use opb_ipif_v2_00_h.pf_counter_bit;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity pf_counter is
generic (
C_COUNT_WIDTH : integer := 9
);
port (
Clk : in std_logic;
Rst : in std_logic;
Carry_Out : out std_logic;
Load_In : in std_logic_vector(0 to C_COUNT_WIDTH-1);
Count_Enable : in std_logic;
Count_Load : in std_logic;
Count_Down : in std_logic;
Count_Out : out std_logic_vector(0 to C_COUNT_WIDTH-1)
);
end entity pf_counter;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of pf_counter is
constant CY_START : integer := 1;
signal alu_cy : std_logic_vector(0 to C_COUNT_WIDTH);
signal iCount_Out : std_logic_vector(0 to C_COUNT_WIDTH-1);
signal count_clock_en : std_logic;
signal carry_active_high : std_logic;
begin -- VHDL_RTL
-----------------------------------------------------------------------------
-- Generate the Counter bits
-----------------------------------------------------------------------------
alu_cy(C_COUNT_WIDTH) <= (Count_Down and Count_Load) or
(not Count_Down and not Count_load);
count_clock_en <= Count_Enable or Count_Load;
I_ADDSUB_GEN : for i in 0 to C_COUNT_WIDTH-1 generate
begin
Counter_Bit_I : entity opb_ipif_v2_00_h.pf_counter_bit
port map (
Clk => Clk, -- [in]
Rst => Rst, -- [in]
Count_In => iCount_Out(i), -- [in]
Load_In => Load_In(i), -- [in]
Count_Load => Count_Load, -- [in]
Count_Down => Count_Down, -- [in]
Carry_In => alu_cy(i+CY_Start), -- [in]
Clock_Enable => count_clock_en, -- [in]
Result => iCount_Out(i), -- [out]
Carry_Out => alu_cy(i+(1-CY_Start))); -- [out]
end generate I_ADDSUB_GEN;
carry_active_high <= alu_cy(0) xor Count_Down;
I_CARRY_OUT: FDRE
port map (
Q => Carry_Out, -- [out]
C => Clk, -- [in]
CE => count_clock_en, -- [in]
D => carry_active_high, -- [in]
R => Rst -- [in]
);
Count_Out <= iCount_Out;
end architecture implementation;
|
bsd-3-clause
|
masson2013/heterogeneous_hthreads
|
src/hardware/MyRepository/pcores/hw_threads/hw_acc_v1_00_a/hdl/vhdl/user_logics/functional/attr_init_2.vhd
|
2
|
17321
|
---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
FUNCTION_EXIT,
STATE_1,
STATE_2,
STATE_3,
STATE_4,
STATE_5,
STATE_6,
STATE_7,
STATE_8,
STATE_9,
STATE_10,
STATE_11,
STATE_12,
STATE_13,
STATE_14,
STATE_15,
STATE_16,
STATE_17,
STATE_18,
STATE_19,
STATE_20,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_STATE_1 : std_logic_vector(0 to 15) := x"0101";
constant U_STATE_2 : std_logic_vector(0 to 15) := x"0102";
constant U_STATE_3 : std_logic_vector(0 to 15) := x"0103";
constant U_STATE_4 : std_logic_vector(0 to 15) := x"0104";
constant U_STATE_5 : std_logic_vector(0 to 15) := x"0105";
constant U_STATE_6 : std_logic_vector(0 to 15) := x"0106";
constant U_STATE_7 : std_logic_vector(0 to 15) := x"0107";
constant U_STATE_8 : std_logic_vector(0 to 15) := x"0108";
constant U_STATE_9 : std_logic_vector(0 to 15) := x"0109";
constant U_STATE_10 : std_logic_vector(0 to 15) := x"0110";
constant U_STATE_11 : std_logic_vector(0 to 15) := x"0111";
constant U_STATE_12 : std_logic_vector(0 to 15) := x"0112";
constant U_STATE_13 : std_logic_vector(0 to 15) := x"0113";
constant U_STATE_14 : std_logic_vector(0 to 15) := x"0114";
constant U_STATE_15 : std_logic_vector(0 to 15) := x"0115";
constant U_STATE_16 : std_logic_vector(0 to 15) := x"0116";
constant U_STATE_17 : std_logic_vector(0 to 15) := x"0117";
constant U_STATE_18 : std_logic_vector(0 to 15) := x"0118";
constant U_STATE_19 : std_logic_vector(0 to 15) := x"0119";
constant U_STATE_20 : std_logic_vector(0 to 15) := x"0120";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
signal retVal, retVal_next : std_logic_vector(0 to 31);
signal arg, arg_next : std_logic_vector(0 to 31);
signal reg1, reg1_next : std_logic_vector(0 to 31);
signal reg2, reg2_next : std_logic_vector(0 to 31);
signal reg3, reg3_next : std_logic_vector(0 to 31);
signal reg4, reg4_next : std_logic_vector(0 to 31);
signal reg5, reg5_next : std_logic_vector(0 to 31);
signal reg6, reg6_next : std_logic_vector(0 to 31);
signal reg7, reg7_next : std_logic_vector(0 to 31);
signal reg8, reg8_next : std_logic_vector(0 to 31);
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock, intrfc2thrd_goWait) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
return_state <= return_state_next;
retVal <= retVal_next;
arg <= arg_next;
reg1 <= reg1_next;
reg2 <= reg2_next;
reg3 <= reg3_next;
reg4 <= reg4_next;
reg5 <= reg5_next;
reg6 <= reg6_next;
reg7 <= reg7_next;
reg8 <= reg8_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_STATE_1 =>
current_state <= STATE_1;
when U_STATE_2 =>
current_state <= STATE_2;
when U_STATE_3 =>
current_state <= STATE_3;
when U_STATE_4 =>
current_state <= STATE_4;
when U_STATE_5 =>
current_state <= STATE_5;
when U_STATE_6 =>
current_state <= STATE_6;
when U_STATE_7 =>
current_state <= STATE_7;
when U_STATE_8 =>
current_state <= STATE_8;
when U_STATE_9 =>
current_state <= STATE_9;
when U_STATE_10 =>
current_state <= STATE_10;
when U_STATE_11 =>
current_state <= STATE_11;
when U_STATE_12 =>
current_state <= STATE_12;
when U_STATE_13 =>
current_state <= STATE_13;
when U_STATE_14 =>
current_state <= STATE_14;
when U_STATE_15 =>
current_state <= STATE_15;
when U_STATE_16 =>
current_state <= STATE_16;
when U_STATE_17 =>
current_state <= STATE_17;
when U_STATE_18 =>
current_state <= STATE_18;
when U_STATE_19 =>
current_state <= STATE_19;
when U_STATE_20 =>
current_state <= STATE_20;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
retVal_next <= retVal;
arg_next <= arg;
reg1_next <= reg1;
reg2_next <= reg2;
reg3_next <= reg3;
reg4_next <= reg4;
reg5_next <= reg5;
reg6_next <= reg6;
reg7_next <= reg7;
reg8_next <= reg8;
-----------------------------------------------------------------------
-- Testcase: attr_init_2.c
-- reg2 = * attr
-- reg3 = * function
-- reg4 = thread[i]
-----------------------------------------------------------------------
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
-- hthread_attr_t * attr = (hthread_attr_t *) arg
when FUNCTION_START =>
-- Pop the argument
thrd2intrfc_value <= Z32;
thrd2intrfc_opcode <= OPCODE_POP;
next_state <= WAIT_STATE;
return_state_next <= STATE_1;
when STATE_1 =>
arg_next <= intrfc2thrd_value;
-- Read the address of attr
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= intrfc2thrd_value;
next_state <= WAIT_STATE;
return_state_next <= STATE_2;
when STATE_2 =>
reg2_next <= intrfc2thrd_value;
-- Read the address of function
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + 4;
next_state <= WAIT_STATE;
return_state_next <= STATE_3;
-- hthread_attr_init( data->attr );
when STATE_3 =>
reg3_next <= intrfc2thrd_value;
-- Push the argument to hthread_attr_init
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg2;
next_state <= WAIT_STATE;
return_state_next <= STATE_4;
when STATE_4 =>
-- Call hthread_attr_init
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_ATTR_INIT;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_5;
next_state <= WAIT_STATE;
-- hthread_create( &data->thread, &data->attr, data->function, NULL );
when STATE_5 =>
-- push NULL
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= Z32;
next_state <= WAIT_STATE;
return_state_next <= STATE_6;
when STATE_6 =>
-- push data->function
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg3;
next_state <= WAIT_STATE;
return_state_next <= STATE_7;
when STATE_7 =>
-- push &data->attr
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg2;
next_state <= WAIT_STATE;
return_state_next <= STATE_8;
when STATE_8 =>
-- push &data->thread
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg + 8;
next_state <= WAIT_STATE;
return_state_next <= STATE_9;
when STATE_9 =>
-- call hthread_create
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_CREATE;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_10;
next_state <= WAIT_STATE;
-- retVal = hthread_join( data->thread, NULL );
when STATE_10 =>
-- Load the value of data->thread
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + 8;
next_state <= WAIT_STATE;
return_state_next <= STATE_11;
when STATE_11 =>
reg4_next <= intrfc2thrd_value;
-- push NULL
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= Z32;
next_state <= WAIT_STATE;
return_state_next <= STATE_12;
when STATE_12 =>
-- push data->thread
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg4;
next_state <= WAIT_STATE;
return_state_next <= STATE_13;
when STATE_13 =>
-- call hthread_join
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_JOIN;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_14;
next_state <= WAIT_STATE;
when STATE_14 =>
retVal_next <= intrfc2thrd_value;
next_state <= FUNCTION_EXIT;
when FUNCTION_EXIT =>
--Same as hthread_exit( (void *) retVal );
thrd2intrfc_value <= retVal;
thrd2intrfc_opcode <= OPCODE_RETURN;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
|
bsd-3-clause
|
masson2013/heterogeneous_hthreads
|
src/platforms/xilinx/numa3_hwti/design/pcores/plb_sync_manager_v1_00_a/hdl/vhdl/send_store.vhd
|
11
|
5763
|
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use work.common.all;
entity send_store is
generic
(
C_AWIDTH : integer := 32;
C_DWIDTH : integer := 32;
C_TWIDTH : integer := 8;
C_MWIDTH : integer := 6;
C_CWIDTH : integer := 8
);
port
(
clk : in std_logic;
rst : in std_logic;
sysrst : in std_logic;
rstdone : out std_logic;
siaddr : in std_logic_vector(0 to C_TWIDTH-1);
siena : in std_logic;
siwea : in std_logic;
sinext : in std_logic_vector(0 to C_TWIDTH-1);
sonext : out std_logic_vector(0 to C_TWIDTH-1)
);
end send_store;
architecture behavioral of send_store is
-- Calculate the number of mutexes to use
constant THREADS : integer := pow2( C_TWIDTH );
-- Constant for the last location to be reset
constant RST_END : std_logic_vector(0 to C_TWIDTH-1) := (others => '1');
-- Declare a storage area for the mutex data
type tstore is array(0 to THREADS-1) of std_logic_vector(0 to C_TWIDTH-1);
-- Declare signals for the mutex storage area
signal store : tstore;
signal sena : std_logic;
signal swea : std_logic;
signal saddr : std_logic_vector(0 to C_TWIDTH - 1);
signal sinput : std_logic_vector(0 to C_TWIDTH - 1);
signal soutput : std_logic_vector(0 to C_TWIDTH - 1);
-- Type for the reset state machine
type rststate is
(
IDLE,
RESET
);
-- Declare signals for the reset
signal rst_cs : rststate;
signal rena : std_logic;
signal rwea : std_logic;
signal raddr : std_logic_vector(0 to C_TWIDTH - 1);
signal raddrn : std_logic_vector(0 to C_TWIDTH - 1);
signal rnext : std_logic_vector(0 to C_TWIDTH - 1);
begin
sonext <= soutput(0 to C_TWIDTH-1);
send_mux : process(clk,rst,sysrst) is
begin
if( rising_edge(clk) ) then
if( rst = '1' or sysrst = '1' ) then
sena <= rena;
swea <= rwea;
saddr <= raddr;
sinput <= rnext;
else
sena <= siena;
swea <= siwea;
saddr <= siaddr;
sinput <= sinext;
end if;
end if;
end process send_mux;
send_reset_controller : process(clk,rst,sysrst) is
begin
if( rising_edge(clk) ) then
if( rst = '1' or sysrst = '1' ) then
rst_cs <= RESET;
raddr <= raddrn;
else
rst_cs <= IDLE;
end if;
end if;
end process send_reset_controller;
send_reset_logic : process(rst_cs,raddr) is
begin
rena <= '1';
rwea <= '1';
rstdone <= '1';
rnext <= (others => '0');
case rst_cs is
when IDLE =>
raddrn <= (others => '0');
when RESET =>
if( raddr = RST_END ) then
raddrn <= raddr;
else
rstdone <= '0';
raddrn <= raddr + 1;
end if;
end case;
end process send_reset_logic;
send_store_controller : process (clk) is
variable output : std_logic_vector(0 to C_TWIDTH-1);
begin
if( rising_edge(clk) ) then
if( sena = '1' ) then
if( swea = '1' ) then
store( conv_integer(saddr) ) <= sinput;
end if;
soutput <= store( conv_integer(saddr) );
end if;
end if;
end process send_store_controller;
end behavioral;
|
bsd-3-clause
|
masson2013/heterogeneous_hthreads
|
src/hardware/MyRepository/pcores/opb_SynchManager_v1_00_c/hdl/vhdl/kind_fsm.vhd
|
11
|
6373
|
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use work.common.all;
entity kind_fsm is
generic
(
C_AWIDTH : integer := 32;
C_DWIDTH : integer := 32;
C_TWIDTH : integer := 8;
C_MWIDTH : integer := 6;
C_CWIDTH : integer := 8
);
port
(
clk : in std_logic;
rst : in std_logic;
start : in std_logic;
finish : out std_logic;
rnw : in std_logic;
datain : in std_logic_vector(0 to C_DWIDTH-1);
data : out std_logic_vector(0 to C_DWIDTH-1);
mutex : in std_logic_vector(0 to C_MWIDTH-1);
thread : in std_logic_vector(0 to C_TWIDTH-1);
miowner : in std_logic_vector(0 to C_TWIDTH-1);
minext : in std_logic_vector(0 to C_TWIDTH-1);
milast : in std_logic_vector(0 to C_TWIDTH-1);
micount : in std_logic_vector(0 to C_CWIDTH-1);
mikind : in std_logic_vector(0 to 1);
tinext : in std_logic_vector(0 to C_TWIDTH-1);
moaddr : out std_logic_vector(0 to C_MWIDTH-1);
moena : out std_logic;
mowea : out std_logic;
moowner : out std_logic_vector(0 to C_TWIDTH-1);
monext : out std_logic_vector(0 to C_TWIDTH-1);
molast : out std_logic_vector(0 to C_TWIDTH-1);
mocount : out std_logic_vector(0 to C_CWIDTH-1);
mokind : out std_logic_vector(0 to 1);
sysrst : in std_logic;
rstdone : out std_logic;
toaddr : out std_logic_vector(0 to C_TWIDTH-1);
toena : out std_logic;
towea : out std_logic;
tonext : out std_logic_vector(0 to C_TWIDTH-1)
);
end kind_fsm;
architecture behavioral of kind_fsm is
-- A type for the states in the kind fsm
type kind_state is
(
IDLE,
READ,
DONE
);
-- Declare signals for the kind register fsm
signal kind_cs : kind_state;
signal kind_ns : kind_state;
-- Alias the kind input and output bits
alias kidata : std_logic_vector(0 to 1) is datain(C_DWIDTH-2 to C_DWIDTH-1);
alias kodata : std_logic_vector(0 to 1) is data(C_DWIDTH-2 to C_DWIDTH-1);
begin
-- This core resets in one clock cycle so it is always "done"
rstdone <= '1';
kind_update : process (clk,rst,sysrst,kind_ns) is
begin
if( rising_edge(clk) ) then
if( rst = '1' or sysrst = '1' ) then
kind_cs <= IDLE;
else
kind_cs <= kind_ns;
end if;
end if;
end process kind_update;
kind_controller : process (kind_cs,start,mutex,miowner,micount,mikind,milast,minext,rnw,datain) is
begin
kind_ns <= kind_cs;
finish <= '0';
data <= (others => '0');
moaddr <= (others => '0');
moena <= '0';
mowea <= '0';
moowner <= (others => '0');
monext <= (others => '0');
molast <= (others => '0');
mokind <= (others => '0');
mocount <= (others => '0');
toaddr <= (others => '0');
toena <= '0';
towea <= '0';
tonext <= (others => '0');
case kind_cs is
when IDLE =>
if( start = '1' ) then
moaddr <= mutex;
mowea <= '0';
moena <= '1';
kind_ns <= READ;
end if;
when READ =>
kind_ns <= DONE;
when DONE =>
if( rnw = '0' ) then
moaddr <= mutex;
moena <= '1';
mowea <= '1';
moowner <= miowner;
mokind <= kidata;
mocount <= micount;
monext <= minext;
molast <= milast;
finish <= '1';
kind_ns <= IDLE;
else
finish <= '1';
kodata <= mikind;
kind_ns <= IDLE;
end if;
end case;
end process kind_controller;
end behavioral;
|
bsd-3-clause
|
masson2013/heterogeneous_hthreads
|
src/platforms/xilinx/ml605_pr_smp1_14_7/design/pcores/plb_sync_manager_v1_00_a/hdl/vhdl/kind_fsm.vhd
|
11
|
6373
|
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use work.common.all;
entity kind_fsm is
generic
(
C_AWIDTH : integer := 32;
C_DWIDTH : integer := 32;
C_TWIDTH : integer := 8;
C_MWIDTH : integer := 6;
C_CWIDTH : integer := 8
);
port
(
clk : in std_logic;
rst : in std_logic;
start : in std_logic;
finish : out std_logic;
rnw : in std_logic;
datain : in std_logic_vector(0 to C_DWIDTH-1);
data : out std_logic_vector(0 to C_DWIDTH-1);
mutex : in std_logic_vector(0 to C_MWIDTH-1);
thread : in std_logic_vector(0 to C_TWIDTH-1);
miowner : in std_logic_vector(0 to C_TWIDTH-1);
minext : in std_logic_vector(0 to C_TWIDTH-1);
milast : in std_logic_vector(0 to C_TWIDTH-1);
micount : in std_logic_vector(0 to C_CWIDTH-1);
mikind : in std_logic_vector(0 to 1);
tinext : in std_logic_vector(0 to C_TWIDTH-1);
moaddr : out std_logic_vector(0 to C_MWIDTH-1);
moena : out std_logic;
mowea : out std_logic;
moowner : out std_logic_vector(0 to C_TWIDTH-1);
monext : out std_logic_vector(0 to C_TWIDTH-1);
molast : out std_logic_vector(0 to C_TWIDTH-1);
mocount : out std_logic_vector(0 to C_CWIDTH-1);
mokind : out std_logic_vector(0 to 1);
sysrst : in std_logic;
rstdone : out std_logic;
toaddr : out std_logic_vector(0 to C_TWIDTH-1);
toena : out std_logic;
towea : out std_logic;
tonext : out std_logic_vector(0 to C_TWIDTH-1)
);
end kind_fsm;
architecture behavioral of kind_fsm is
-- A type for the states in the kind fsm
type kind_state is
(
IDLE,
READ,
DONE
);
-- Declare signals for the kind register fsm
signal kind_cs : kind_state;
signal kind_ns : kind_state;
-- Alias the kind input and output bits
alias kidata : std_logic_vector(0 to 1) is datain(C_DWIDTH-2 to C_DWIDTH-1);
alias kodata : std_logic_vector(0 to 1) is data(C_DWIDTH-2 to C_DWIDTH-1);
begin
-- This core resets in one clock cycle so it is always "done"
rstdone <= '1';
kind_update : process (clk,rst,sysrst,kind_ns) is
begin
if( rising_edge(clk) ) then
if( rst = '1' or sysrst = '1' ) then
kind_cs <= IDLE;
else
kind_cs <= kind_ns;
end if;
end if;
end process kind_update;
kind_controller : process (kind_cs,start,mutex,miowner,micount,mikind,milast,minext,rnw,datain) is
begin
kind_ns <= kind_cs;
finish <= '0';
data <= (others => '0');
moaddr <= (others => '0');
moena <= '0';
mowea <= '0';
moowner <= (others => '0');
monext <= (others => '0');
molast <= (others => '0');
mokind <= (others => '0');
mocount <= (others => '0');
toaddr <= (others => '0');
toena <= '0';
towea <= '0';
tonext <= (others => '0');
case kind_cs is
when IDLE =>
if( start = '1' ) then
moaddr <= mutex;
mowea <= '0';
moena <= '1';
kind_ns <= READ;
end if;
when READ =>
kind_ns <= DONE;
when DONE =>
if( rnw = '0' ) then
moaddr <= mutex;
moena <= '1';
mowea <= '1';
moowner <= miowner;
mokind <= kidata;
mocount <= micount;
monext <= minext;
molast <= milast;
finish <= '1';
kind_ns <= IDLE;
else
finish <= '1';
kodata <= mikind;
kind_ns <= IDLE;
end if;
end case;
end process kind_controller;
end behavioral;
|
bsd-3-clause
|
masson2013/heterogeneous_hthreads
|
src/platforms/xilinx/smp1/design/pcores/plb_sync_manager_v1_00_a/hdl/vhdl/owner_fsm.vhd
|
11
|
5733
|
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use work.common.all;
entity owner_fsm is
generic
(
C_AWIDTH : integer := 32;
C_DWIDTH : integer := 32;
C_TWIDTH : integer := 8;
C_MWIDTH : integer := 6;
C_CWIDTH : integer := 8
);
port
(
clk : in std_logic;
rst : in std_logic;
start : in std_logic;
finish : out std_logic;
data : out std_logic_vector(0 to C_DWIDTH-1);
mutex : in std_logic_vector(0 to C_MWIDTH-1);
thread : in std_logic_vector(0 to C_TWIDTH-1);
miowner : in std_logic_vector(0 to C_TWIDTH-1);
minext : in std_logic_vector(0 to C_TWIDTH-1);
milast : in std_logic_vector(0 to C_TWIDTH-1);
micount : in std_logic_vector(0 to C_CWIDTH-1);
mikind : in std_logic_vector(0 to 1);
tinext : in std_logic_vector(0 to C_TWIDTH-1);
moaddr : out std_logic_vector(0 to C_MWIDTH-1);
moena : out std_logic;
mowea : out std_logic;
moowner : out std_logic_vector(0 to C_TWIDTH-1);
monext : out std_logic_vector(0 to C_TWIDTH-1);
molast : out std_logic_vector(0 to C_TWIDTH-1);
mocount : out std_logic_vector(0 to C_CWIDTH-1);
mokind : out std_logic_vector(0 to 1);
sysrst : in std_logic;
rstdone : out std_logic;
toaddr : out std_logic_vector(0 to C_TWIDTH-1);
toena : out std_logic;
towea : out std_logic;
tonext : out std_logic_vector(0 to C_TWIDTH-1)
);
end owner_fsm;
architecture behavioral of owner_fsm is
-- A type for the states in the owner fsm
type owner_state is
(
IDLE,
READ,
DONE
);
-- Declare signals for the owner fsm
signal owner_cs : owner_state;
signal owner_ns : owner_state;
-- Alias owner output
alias odata : std_logic_vector(0 to C_TWIDTH-1) is data(C_DWIDTH-C_TWIDTH to C_DWIDTH-1);
begin
-- This core resets in one clock cycle so it is always "done"
rstdone <= '1';
owner_update : process(clk,rst,sysrst,owner_ns) is
begin
if( rising_edge(clk) ) then
if( rst = '1' or sysrst = '1' ) then
owner_cs <= IDLE;
else
owner_cs <= owner_ns;
end if;
end if;
end process owner_update;
owner_controller : process(owner_cs,start,mutex,miowner) is
begin
owner_ns <= owner_cs;
finish <= '0';
data <= (others => '0');
moaddr <= (others => '0');
moena <= '0';
mowea <= '0';
moowner <= (others => '0');
monext <= (others => '0');
molast <= (others => '0');
mokind <= (others => '0');
mocount <= (others => '0');
toaddr <= (others => '0');
toena <= '0';
towea <= '0';
tonext <= (others => '0');
case owner_cs is
when IDLE =>
if( start = '1' ) then
moaddr <= mutex;
moena <= '1';
mowea <= '0';
owner_ns <= READ;
end if;
when READ =>
owner_ns <= DONE;
when DONE =>
finish <= '1';
odata <= miowner;
owner_ns <= IDLE;
end case;
end process owner_controller;
end behavioral;
|
bsd-3-clause
|
masson2013/heterogeneous_hthreads
|
src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/plb_sync_manager_v1_00_a/hdl/vhdl/owner_fsm.vhd
|
11
|
5733
|
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use work.common.all;
entity owner_fsm is
generic
(
C_AWIDTH : integer := 32;
C_DWIDTH : integer := 32;
C_TWIDTH : integer := 8;
C_MWIDTH : integer := 6;
C_CWIDTH : integer := 8
);
port
(
clk : in std_logic;
rst : in std_logic;
start : in std_logic;
finish : out std_logic;
data : out std_logic_vector(0 to C_DWIDTH-1);
mutex : in std_logic_vector(0 to C_MWIDTH-1);
thread : in std_logic_vector(0 to C_TWIDTH-1);
miowner : in std_logic_vector(0 to C_TWIDTH-1);
minext : in std_logic_vector(0 to C_TWIDTH-1);
milast : in std_logic_vector(0 to C_TWIDTH-1);
micount : in std_logic_vector(0 to C_CWIDTH-1);
mikind : in std_logic_vector(0 to 1);
tinext : in std_logic_vector(0 to C_TWIDTH-1);
moaddr : out std_logic_vector(0 to C_MWIDTH-1);
moena : out std_logic;
mowea : out std_logic;
moowner : out std_logic_vector(0 to C_TWIDTH-1);
monext : out std_logic_vector(0 to C_TWIDTH-1);
molast : out std_logic_vector(0 to C_TWIDTH-1);
mocount : out std_logic_vector(0 to C_CWIDTH-1);
mokind : out std_logic_vector(0 to 1);
sysrst : in std_logic;
rstdone : out std_logic;
toaddr : out std_logic_vector(0 to C_TWIDTH-1);
toena : out std_logic;
towea : out std_logic;
tonext : out std_logic_vector(0 to C_TWIDTH-1)
);
end owner_fsm;
architecture behavioral of owner_fsm is
-- A type for the states in the owner fsm
type owner_state is
(
IDLE,
READ,
DONE
);
-- Declare signals for the owner fsm
signal owner_cs : owner_state;
signal owner_ns : owner_state;
-- Alias owner output
alias odata : std_logic_vector(0 to C_TWIDTH-1) is data(C_DWIDTH-C_TWIDTH to C_DWIDTH-1);
begin
-- This core resets in one clock cycle so it is always "done"
rstdone <= '1';
owner_update : process(clk,rst,sysrst,owner_ns) is
begin
if( rising_edge(clk) ) then
if( rst = '1' or sysrst = '1' ) then
owner_cs <= IDLE;
else
owner_cs <= owner_ns;
end if;
end if;
end process owner_update;
owner_controller : process(owner_cs,start,mutex,miowner) is
begin
owner_ns <= owner_cs;
finish <= '0';
data <= (others => '0');
moaddr <= (others => '0');
moena <= '0';
mowea <= '0';
moowner <= (others => '0');
monext <= (others => '0');
molast <= (others => '0');
mokind <= (others => '0');
mocount <= (others => '0');
toaddr <= (others => '0');
toena <= '0';
towea <= '0';
tonext <= (others => '0');
case owner_cs is
when IDLE =>
if( start = '1' ) then
moaddr <= mutex;
moena <= '1';
mowea <= '0';
owner_ns <= READ;
end if;
when READ =>
owner_ns <= DONE;
when DONE =>
finish <= '1';
odata <= miowner;
owner_ns <= IDLE;
end case;
end process owner_controller;
end behavioral;
|
bsd-3-clause
|
masson2013/heterogeneous_hthreads
|
src/hardware/MyRepository/pcores/axi_hthread_cores/axi_scheduler_v1_00_a/hdl/vhdl/axi_scheduler.vhd
|
2
|
28962
|
------------------------------------------------------------------------------
-- axi_scheduler.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: axi_scheduler.vhd
-- Version: 1.00.a
-- Description: Top level design, instantiates library components and user logic.
-- Date: Thu Jun 26 14:24:54 2014 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library axi_lite_ipif_v1_01_a;
use axi_lite_ipif_v1_01_a.axi_lite_ipif;
library axi_master_lite_v1_00_a;
use axi_master_lite_v1_00_a.axi_master_lite;
library axi_scheduler_v1_00_a;
use axi_scheduler_v1_00_a.user_logic;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_S_AXI_DATA_WIDTH -- AXI4LITE slave: Data width
-- C_S_AXI_ADDR_WIDTH -- AXI4LITE slave: Address Width
-- C_S_AXI_MIN_SIZE -- AXI4LITE slave: Min Size
-- C_USE_WSTRB -- AXI4LITE slave: Write Strobe
-- C_DPHASE_TIMEOUT -- AXI4LITE slave: Data Phase Timeout
-- C_BASEADDR -- AXI4LITE slave: base address
-- C_HIGHADDR -- AXI4LITE slave: high address
-- C_FAMILY -- FPGA Family
-- C_NUM_REG -- Number of software accessible registers
-- C_NUM_MEM -- Number of address-ranges
-- C_SLV_AWIDTH -- Slave interface address bus width
-- C_SLV_DWIDTH -- Slave interface data bus width
-- C_M_AXI_LITE_ADDR_WIDTH -- Master-Intf address bus width
-- C_M_AXI_LITE_DATA_WIDTH -- Master-Intf data bus width
--
-- Definition of Ports:
-- S_AXI_ACLK -- AXI4LITE slave: Clock
-- S_AXI_ARESETN -- AXI4LITE slave: Reset
-- S_AXI_AWADDR -- AXI4LITE slave: Write address
-- S_AXI_AWVALID -- AXI4LITE slave: Write address valid
-- S_AXI_WDATA -- AXI4LITE slave: Write data
-- S_AXI_WSTRB -- AXI4LITE slave: Write strobe
-- S_AXI_WVALID -- AXI4LITE slave: Write data valid
-- S_AXI_BREADY -- AXI4LITE slave: Response ready
-- S_AXI_ARADDR -- AXI4LITE slave: Read address
-- S_AXI_ARVALID -- AXI4LITE slave: Read address valid
-- S_AXI_RREADY -- AXI4LITE slave: Read data ready
-- S_AXI_ARREADY -- AXI4LITE slave: read addres ready
-- S_AXI_RDATA -- AXI4LITE slave: Read data
-- S_AXI_RRESP -- AXI4LITE slave: Read data response
-- S_AXI_RVALID -- AXI4LITE slave: Read data valid
-- S_AXI_WREADY -- AXI4LITE slave: Write data ready
-- S_AXI_BRESP -- AXI4LITE slave: Response
-- S_AXI_BVALID -- AXI4LITE slave: Resonse valid
-- S_AXI_AWREADY -- AXI4LITE slave: Wrte address ready
-- m_axi_lite_aclk -- AXI4LITE master: Clock
-- m_axi_lite_aresetn -- AXI4LITE master: Reset
-- md_error -- AXI4LITE master: Error
-- m_axi_lite_arready -- AXI4LITE master: Read address ready
-- m_axi_lite_arvalid -- AXI4LITE master: read address valid
-- m_axi_lite_araddr -- AXI4LITE master: read address protection
-- m_axi_lite_arprot -- AXI4LITE master: Read address protection
-- m_axi_lite_rready -- AXI4LITE master: Read data ready
-- m_axi_lite_rvalid -- AXI4LITE master: Read data valid
-- m_axi_lite_rdata -- AXI4LITE master: Read data
-- m_axi_lite_rresp -- AXI4LITE master: read data response
-- m_axi_lite_awready -- AXI4LITE master: write address ready
-- m_axi_lite_awvalid -- AXI4LITE master: write address valid
-- m_axi_lite_awaddr -- AXI4LITE master: write address valid
-- m_axi_lite_awprot -- AXI4LITE master: write address protection
-- m_axi_lite_wready -- AXI4LITE master: write data ready
-- m_axi_lite_wvalid -- AXI4LITE master: write data valid
-- m_axi_lite_wdata -- AXI4LITE master: write data
-- m_axi_lite_wstrb -- AXI4LITE master: write data strobe
-- m_axi_lite_bready -- AXI4LITE master: read response ready
-- m_axi_lite_bvalid -- AXI4LITE master: read response valid
-- m_axi_lite_bresp -- AXI4LITE master: read response
------------------------------------------------------------------------------
entity axi_scheduler is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector := X"00FFFFFF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer := 0;
C_BASEADDR : std_logic_vector(0 to 31) := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector(0 to 31) := X"00000000";
C_FAMILY : string := "virtex6";
C_NUM_REG : integer := 1;
C_NUM_MEM : integer := 1;
C_SLV_AWIDTH : integer := 32;
C_SLV_DWIDTH : integer := 32;
C_M_AXI_LITE_ADDR_WIDTH : integer := 32;
C_M_AXI_LITE_DATA_WIDTH : integer := 32
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
Soft_Reset : in std_logic;
Reset_Done : out std_logic;
Soft_Stop : in std_logic;
SWTM_DOB : in std_logic_vector(0 to 31);
SWTM_ADDRB : out std_logic_vector(0 to 8);
SWTM_DIB : out std_logic_vector(0 to 31);
SWTM_ENB : out std_logic;
SWTM_WEB : out std_logic;
TM2SCH_current_cpu_tid : in std_logic_vector(0 to 7);
TM2SCH_opcode : in std_logic_vector(0 to 5);
TM2SCH_data : in std_logic_vector(0 to 7);
TM2SCH_request : in std_logic;
SCH2TM_busy : out std_logic;
SCH2TM_data : out std_logic_vector(0 to 7);
SCH2TM_next_cpu_tid : out std_logic_vector(0 to 7);
SCH2TM_next_tid_valid : out std_logic;
Preemption_Interrupt : out std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic;
m_axi_lite_aclk : in std_logic;
m_axi_lite_aresetn : in std_logic;
md_error : out std_logic;
m_axi_lite_arready : in std_logic;
m_axi_lite_arvalid : out std_logic;
m_axi_lite_araddr : out std_logic_vector(C_M_AXI_LITE_ADDR_WIDTH-1 downto 0);
m_axi_lite_arprot : out std_logic_vector(2 downto 0);
m_axi_lite_rready : out std_logic;
m_axi_lite_rvalid : in std_logic;
m_axi_lite_rdata : in std_logic_vector(C_M_AXI_LITE_DATA_WIDTH-1 downto 0);
m_axi_lite_rresp : in std_logic_vector(1 downto 0);
m_axi_lite_awready : in std_logic;
m_axi_lite_awvalid : out std_logic;
m_axi_lite_awaddr : out std_logic_vector(C_M_AXI_LITE_ADDR_WIDTH-1 downto 0);
m_axi_lite_awprot : out std_logic_vector(2 downto 0);
m_axi_lite_wready : in std_logic;
m_axi_lite_wvalid : out std_logic;
m_axi_lite_wdata : out std_logic_vector(C_M_AXI_LITE_DATA_WIDTH-1 downto 0);
m_axi_lite_wstrb : out std_logic_vector((C_M_AXI_LITE_DATA_WIDTH/8)-1 downto 0);
m_axi_lite_bready : out std_logic;
m_axi_lite_bvalid : in std_logic;
m_axi_lite_bresp : in std_logic_vector(1 downto 0)
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute MAX_FANOUT of S_AXI_ACLK : signal is "10000";
attribute MAX_FANOUT of S_AXI_ARESETN : signal is "10000";
attribute SIGIS of S_AXI_ACLK : signal is "Clk";
attribute SIGIS of S_AXI_ARESETN : signal is "Rst";
attribute MAX_FANOUT of m_axi_lite_aclk : signal is "10000";
attribute MAX_FANOUT of m_axi_lite_aresetn : signal is "10000";
attribute SIGIS of m_axi_lite_aclk : signal is "Clk";
attribute SIGIS of m_axi_lite_aresetn : signal is "Rst";
end entity axi_scheduler;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of axi_scheduler is
constant USER_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant IPIF_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector(0 to 31) := C_BASEADDR or X"00000000";
constant USER_SLV_HIGHADDR : std_logic_vector(0 to 31) := C_BASEADDR or X"000000FF";
--constant USER_MST_BASEADDR : std_logic_vector := C_BASEADDR or X"00000100";
-- constant USER_MST_HIGHADDR : std_logic_vector := C_BASEADDR or X"000001FF";
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
ZERO_ADDR_PAD & USER_SLV_HIGHADDR -- user logic slave space high address
--ZERO_ADDR_PAD & USER_MST_BASEADDR, -- user logic master space base address
--ZERO_ADDR_PAD & USER_MST_HIGHADDR -- user logic master space high address
);
constant USER_SLV_NUM_REG : integer := 1;
--constant USER_MST_NUM_REG : integer := 4;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;--+USER_MST_NUM_REG;
constant TOTAL_IPIF_CE : integer := USER_NUM_REG;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => (USER_SLV_NUM_REG) -- number of ce for user logic slave space
-- 1 => (USER_MST_NUM_REG) -- number of ce for user logic master space
);
------------------------------------------
-- Width of the master address bus (32 only)
------------------------------------------
constant USER_MST_AWIDTH : integer := C_M_AXI_LITE_ADDR_WIDTH;
------------------------------------------
-- Width of the master data bus (32 only)
------------------------------------------
constant USER_MST_DWIDTH : integer := C_M_AXI_LITE_DATA_WIDTH;
------------------------------------------
-- Index for CS/CE
------------------------------------------
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
--constant USER_MST_CS_INDEX : integer := 1;
--constant USER_MST_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_MST_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations
------------------------------------------
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Resetn : std_logic;
signal ipif_Bus2IP_Reset : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(IPIF_SLV_DWIDTH/8-1 downto 0);
signal ipif_Bus2IP_CS : std_logic_vector((IPIF_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1 downto 0);
signal ipif_Bus2IP_RdCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_WrCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal ipif_ip2bus_mstrd_req : std_logic;
signal ipif_ip2bus_mstwr_req : std_logic;
signal ipif_ip2bus_mst_addr : std_logic_vector(0 to C_M_AXI_LITE_ADDR_WIDTH-1);
signal ipif_ip2bus_mst_be : std_logic_vector(0 to (C_M_AXI_LITE_DATA_WIDTH/8)-1);
signal ipif_ip2bus_mst_lock : std_logic;
signal ipif_ip2bus_mst_reset : std_logic;
signal ipif_bus2ip_mst_cmdack : std_logic;
signal ipif_bus2ip_mst_cmplt : std_logic;
signal ipif_bus2ip_mst_error : std_logic;
signal ipif_bus2ip_mst_rearbitrate : std_logic;
signal ipif_bus2ip_mst_cmd_timeout : std_logic;
signal ipif_bus2ip_mstrd_d : std_logic_vector(0 to C_M_AXI_LITE_DATA_WIDTH-1);
signal ipif_bus2ip_mstrd_src_rdy_n : std_logic;
signal ipif_ip2bus_mstwr_d : std_logic_vector(0 to C_M_AXI_LITE_DATA_WIDTH-1);
signal ipif_bus2ip_mstwr_dst_rdy_n : std_logic;
signal user_Bus2IP_RdCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_Bus2IP_WrCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_IP2Bus_Data : std_logic_vector(USER_SLV_DWIDTH-1 downto 0);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
begin
------------------------------------------
-- instantiate axi_lite_ipif
------------------------------------------
AXI_LITE_IPIF_I : entity axi_lite_ipif_v1_01_a.axi_lite_ipif
generic map
(
C_S_AXI_DATA_WIDTH => IPIF_SLV_DWIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map
(
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE,
Bus2IP_Data => ipif_Bus2IP_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
IP2Bus_Data => ipif_IP2Bus_Data
);
------------------------------------------
-- instantiate axi_master_lite
------------------------------------------
AXI_MASTER_LITE_I : entity axi_master_lite_v1_00_a.axi_master_lite
generic map
(
C_M_AXI_LITE_ADDR_WIDTH => C_M_AXI_LITE_ADDR_WIDTH,
C_M_AXI_LITE_DATA_WIDTH => C_M_AXI_LITE_DATA_WIDTH,
C_FAMILY => C_FAMILY
)
port map
(
m_axi_lite_aclk => m_axi_lite_aclk,
m_axi_lite_aresetn => m_axi_lite_aresetn,
md_error => md_error,
m_axi_lite_arready => m_axi_lite_arready,
m_axi_lite_arvalid => m_axi_lite_arvalid,
m_axi_lite_araddr => m_axi_lite_araddr,
m_axi_lite_arprot => m_axi_lite_arprot,
m_axi_lite_rready => m_axi_lite_rready,
m_axi_lite_rvalid => m_axi_lite_rvalid,
m_axi_lite_rdata => m_axi_lite_rdata,
m_axi_lite_rresp => m_axi_lite_rresp,
m_axi_lite_awready => m_axi_lite_awready,
m_axi_lite_awvalid => m_axi_lite_awvalid,
m_axi_lite_awaddr => m_axi_lite_awaddr,
m_axi_lite_awprot => m_axi_lite_awprot,
m_axi_lite_wready => m_axi_lite_wready,
m_axi_lite_wvalid => m_axi_lite_wvalid,
m_axi_lite_wdata => m_axi_lite_wdata,
m_axi_lite_wstrb => m_axi_lite_wstrb,
m_axi_lite_bready => m_axi_lite_bready,
m_axi_lite_bvalid => m_axi_lite_bvalid,
m_axi_lite_bresp => m_axi_lite_bresp,
ip2bus_mstrd_req => ipif_ip2bus_mstrd_req,
ip2bus_mstwr_req => ipif_ip2bus_mstwr_req,
ip2bus_mst_addr => ipif_ip2bus_mst_addr,
ip2bus_mst_be => ipif_ip2bus_mst_be,
ip2bus_mst_lock => ipif_ip2bus_mst_lock,
ip2bus_mst_reset => ipif_ip2bus_mst_reset,
bus2ip_mst_cmdack => ipif_bus2ip_mst_cmdack,
bus2ip_mst_cmplt => ipif_bus2ip_mst_cmplt,
bus2ip_mst_error => ipif_bus2ip_mst_error,
bus2ip_mst_rearbitrate => ipif_bus2ip_mst_rearbitrate,
bus2ip_mst_cmd_timeout => ipif_bus2ip_mst_cmd_timeout,
bus2ip_mstrd_d => ipif_bus2ip_mstrd_d,
bus2ip_mstrd_src_rdy_n => ipif_bus2ip_mstrd_src_rdy_n,
ip2bus_mstwr_d => ipif_ip2bus_mstwr_d,
bus2ip_mstwr_dst_rdy_n => ipif_bus2ip_mstwr_dst_rdy_n
);
------------------------------------------
-- instantiate User Logic
------------------------------------------
USER_LOGIC_I : entity axi_scheduler_v1_00_a.user_logic
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
--USER generics mapped here
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_MST_AWIDTH => USER_MST_AWIDTH,
C_MST_DWIDTH => USER_MST_DWIDTH,
C_NUM_REG => USER_NUM_REG,
C_SLV_DWIDTH => USER_SLV_DWIDTH
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
Soft_Reset => Soft_Reset ,
Reset_Done => Reset_Done ,
Soft_Stop => Soft_Stop ,
SWTM_DOB => SWTM_DOB ,
SWTM_ADDRB => SWTM_ADDRB ,
SWTM_DIB => SWTM_DIB ,
SWTM_ENB => SWTM_ENB ,
SWTM_WEB => SWTM_WEB ,
TM2SCH_current_cpu_tid => TM2SCH_current_cpu_tid ,
TM2SCH_opcode => TM2SCH_opcode ,
TM2SCH_data => TM2SCH_data ,
TM2SCH_request => TM2SCH_request ,
SCH2TM_busy => SCH2TM_busy ,
SCH2TM_data => SCH2TM_data ,
SCH2TM_next_cpu_tid => SCH2TM_next_cpu_tid ,
SCH2TM_next_tid_valid => SCH2TM_next_tid_valid ,
Preemption_Interrupt => Preemption_Interrupt ,
-- MAP USER PORTS ABOVE THIS LINE ------------------
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => ipif_Bus2IP_Reset,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error,
ip2bus_mstrd_req => ipif_ip2bus_mstrd_req,
ip2bus_mstwr_req => ipif_ip2bus_mstwr_req,
ip2bus_mst_addr => ipif_ip2bus_mst_addr,
ip2bus_mst_be => ipif_ip2bus_mst_be,
ip2bus_mst_lock => ipif_ip2bus_mst_lock,
ip2bus_mst_reset => ipif_ip2bus_mst_reset,
bus2ip_mst_cmdack => ipif_bus2ip_mst_cmdack,
bus2ip_mst_cmplt => ipif_bus2ip_mst_cmplt,
bus2ip_mst_error => ipif_bus2ip_mst_error,
bus2ip_mst_rearbitrate => ipif_bus2ip_mst_rearbitrate,
bus2ip_mst_cmd_timeout => ipif_bus2ip_mst_cmd_timeout,
bus2ip_mstrd_d => ipif_bus2ip_mstrd_d,
bus2ip_mstrd_src_rdy_n => ipif_bus2ip_mstrd_src_rdy_n,
ip2bus_mstwr_d => ipif_ip2bus_mstwr_d,
bus2ip_mstwr_dst_rdy_n => ipif_bus2ip_mstwr_dst_rdy_n
);
------------------------------------------
-- connect internal signals
------------------------------------------
IP2BUS_DATA_MUX_PROC : process( ipif_Bus2IP_CS, user_IP2Bus_Data ) is
begin
case ipif_Bus2IP_CS is
when "1" => ipif_IP2Bus_Data <= user_IP2Bus_Data;
when others => ipif_IP2Bus_Data <= (others => '0');
end case;
end process IP2BUS_DATA_MUX_PROC;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;
user_Bus2IP_RdCE(USER_SLV_NUM_REG-1 downto 0) <= ipif_Bus2IP_RdCE(TOTAL_IPIF_CE -USER_SLV_CE_INDEX -1 downto TOTAL_IPIF_CE - USER_SLV_CE_INDEX -USER_SLV_NUM_REG);
user_Bus2IP_WrCE(USER_SLV_NUM_REG-1 downto 0) <= ipif_Bus2IP_WrCE(TOTAL_IPIF_CE -USER_SLV_CE_INDEX -1 downto TOTAL_IPIF_CE - USER_SLV_CE_INDEX -USER_SLV_NUM_REG);
-- user_Bus2IP_RdCE(USER_NUM_REG-1 downto USER_NUM_REG-USER_MST_NUM_REG) <= ipif_Bus2IP_RdCE(TOTAL_IPIF_CE - USER_MST_CE_INDEX -1 downto TOTAL_IPIF_CE - USER_MST_CE_INDEX -USER_MST_NUM_REG);
-- user_Bus2IP_WrCE(USER_NUM_REG-1 downto USER_NUM_REG- USER_MST_NUM_REG) <= ipif_Bus2IP_WrCE(TOTAL_IPIF_CE - USER_MST_CE_INDEX -1 downto TOTAL_IPIF_CE - USER_MST_CE_INDEX -USER_MST_NUM_REG);
ipif_Bus2IP_Reset <= not ipif_Bus2IP_Resetn;
end IMP;
|
bsd-3-clause
|
masson2013/heterogeneous_hthreads
|
src/platforms/xilinx/smp3_opbhwti/design/pcores/ipif_common_v1_00_d/hdl/vhdl/steer_module_read.vhd
|
3
|
23737
|
--SINGLE_FILE_TAG
-------------------------------------------------------------------------------
-- $Id: steer_module_read.vhd,v 1.2 2003/05/19 17:34:26 ostlerf Exp $
-------------------------------------------------------------------------------
-- Steer_Module_Read - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: steer_module_read.vhd
-- Version: v1.00b
-- Description: Read and Write Steering logic for IPIF
--
-- For writes, this logic steers data from the correct byte
-- lane to IPIF devices which may be smaller than the bus
-- width. The BE signals are also steered if the BE_Steer
-- signal is asserted, which indicates that the address space
-- being accessed has a smaller maximum data transfer size
-- than the bus size.
--
-- For writes, the Decode_size signal determines how read
-- data is steered onto the byte lanes. To simplify the
-- logic, the read data is mirrored onto the entire data
-- bus, insuring that the lanes corrsponding to the BE's
-- have correct data.
--
--
--
-------------------------------------------------------------------------------
-- Structure:
--
-- steer_module_read.vhd
--
-------------------------------------------------------------------------------
-- Author: BLT
-- History:
-- BLT 4-26-2002 -- First version
-- ^^^^^^
-- First version of steering logic module.
-- ~~~~~~
-- BLT 11-18-2002 -- Update to version v1.00b
-- ^^^^^^
-- Updated to use ipif_common_v1_00_b, which fixed a simulation problem
-- in the ipif_steer logic
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_signed.all;
use IEEE.std_logic_misc.all;
library ipif_common_v1_00_d;
use ipif_common_v1_00_d.STEER_TYPES.all;
-------------------------------------------------------------------------------
-- Port declarations
-- generic definitions:
-- C_DWIDTH : integer := width of host databus attached to the IPIF
-- C_SMALLEST : integer := width of smallest device (not access size)
-- attached to the IPIF
-- C_LARGEST : integer := width of largest device (not access size)
-- attached to the IPIF
-- C_MIRROR_SIZE : integer := smallest unit of data that is mirrored
-- C_AWIDTH : integer := width of the host address bus attached to
-- the IPIF
-- port definitions:
-- Wr_Data_In : in Write Data In (from host data bus)
-- Rd_Data_In : in Read Data In (from IPIC data bus)
-- Addr : in Address bus from host address bus
-- BE_In : in Byte Enables In from host side
-- Decode_size : in Size of MAXIMUM data access allowed to
-- a particular address map decode.
--
-- Size indication (Decode_size)
-- 001 - byte
-- 010 - halfword
-- 011 - word
-- 100 - doubleword
-- 101 - 128-b
-- 110 - 256-b
-- 111 - 512-b
-- num_bytes = 2^(n-1)
--
-- BE_Steer : in BE_Steer = 1 : steer BE's onto IPIF BE bus
-- BE_Steer = 0 : don't steer BE's, pass through
-- Wr_Data_Out : out Write Data Out (to IPIF data bus)
-- Rd_Data_Out : out Read Data Out (to host data bus)
-- BE_Out : out Byte Enables Out to IPIF side
--
-------------------------------------------------------------------------------
entity Steer_Module_Read is
generic (
C_DWIDTH_IN : integer := 32; -- 8, 16, 32, 64, 128, 256, or 512
C_DWIDTH_OUT : integer := 64; -- 8, 16, 32, 64, 128, 256, or 512
C_SMALLEST_OUT : integer := 32; -- 8, 16, 32, 64, 128, 256, or 512
C_SMALLEST_IN : integer := 8; -- 8, 16, 32, 64, 128, 256, or 512
C_AWIDTH : integer := 32
);
port (
Data_In : in std_logic_vector(0 to C_DWIDTH_IN-1);
Addr : in std_logic_vector(0 to C_AWIDTH-1);
Decode_size : in std_logic_vector(0 to 2);
Data_Out : out std_logic_vector(0 to C_DWIDTH_OUT-1)
);
end entity Steer_Module_Read;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture IMP of Steer_Module_Read is
-------------------------------------------------------------------------------
-- Function max -- returns maximum of x and y
-------------------------------------------------------------------------------
function max(x : integer; y : integer) return integer is
begin
if x > y then return x;
else return y;
end if;
end function max;
-------------------------------------------------------------------------------
-- Function min -- returns minimum of x and y
-------------------------------------------------------------------------------
function min(x : integer; y : integer) return integer is
begin
if x < y then return x;
else return y;
end if;
end function min;
-------------------------------------------------------------------------------
-- Function log2 -- returns number of bits needed to encode x choices
-- x = 0 returns 0
-- x = 1 returns 0
-- x = 2 returns 1
-- x = 4 returns 2, etc.
-------------------------------------------------------------------------------
function log2(x : natural) return integer is
variable i : integer := 0;
variable val: integer := 1;
begin
if x = 0 then return 0;
else
for j in 0 to 8 loop -- for loop for XST
if val >= x then null;
else
i := i+1;
val := val*2;
end if;
end loop;
return i;
end if;
end function log2;
-------------------------------------------------------------------------------
-- Function pwr -- returns x**y for integers x and y, y>=0
-------------------------------------------------------------------------------
function pwr(x: integer; y: integer) return integer is
variable z : integer := 1;
begin
if y = 0 then return 1;
else
for i in 1 to y loop
z := z * x;
end loop;
return z;
end if;
end function pwr;
function Addr_Start_Func (C_SMALLEST_OUT : integer;
C_DWIDTH_IN : integer)
return integer is
variable IP_Addr_Start : integer;
variable IP_Addr_Stop : integer;
begin
case C_SMALLEST_OUT is
when 8 =>
case C_DWIDTH_IN is
when 8 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 16 => IP_Addr_Start := 0; IP_Addr_Stop := 0;
when 32 => IP_Addr_Start := 0; IP_Addr_Stop := 1;
when 64 => IP_Addr_Start := 0; IP_Addr_Stop := 2;
when 128 => IP_Addr_Start := 0; IP_Addr_Stop := 3;
when 256 => IP_Addr_Start := 0; IP_Addr_Stop := 4;
when 512 => IP_Addr_Start := 0; IP_Addr_Stop := 5;
when others => IP_Addr_Start := 0; IP_Addr_Stop := 6;
end case;
when 16 =>
case C_DWIDTH_IN is
when 8 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 16 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 32 => IP_Addr_Start := 1; IP_Addr_Stop := 1;
when 64 => IP_Addr_Start := 1; IP_Addr_Stop := 2;
when 128 => IP_Addr_Start := 1; IP_Addr_Stop := 3;
when 256 => IP_Addr_Start := 1; IP_Addr_Stop := 4;
when 512 => IP_Addr_Start := 1; IP_Addr_Stop := 5;
when others => IP_Addr_Start := 1; IP_Addr_Stop := 6;
end case;
when 32 =>
case C_DWIDTH_IN is
when 8 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 16 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 32 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 64 => IP_Addr_Start := 2; IP_Addr_Stop := 2;
when 128 => IP_Addr_Start := 2; IP_Addr_Stop := 3;
when 256 => IP_Addr_Start := 2; IP_Addr_Stop := 4;
when 512 => IP_Addr_Start := 2; IP_Addr_Stop := 5;
when others => IP_Addr_Start := 2; IP_Addr_Stop := 6;
end case;
when 64 =>
case C_DWIDTH_IN is
when 8 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 16 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 32 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 64 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 128 => IP_Addr_Start := 3; IP_Addr_Stop := 3;
when 256 => IP_Addr_Start := 3; IP_Addr_Stop := 4;
when 512 => IP_Addr_Start := 3; IP_Addr_Stop := 5;
when others => IP_Addr_Start := 3; IP_Addr_Stop := 6;
end case;
when 128 =>
case C_DWIDTH_IN is
when 8 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 16 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 32 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 64 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 128 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 256 => IP_Addr_Start := 4; IP_Addr_Stop := 4;
when 512 => IP_Addr_Start := 4; IP_Addr_Stop := 5;
when others => IP_Addr_Start := 4; IP_Addr_Stop := 6;
end case;
when 256 =>
case C_DWIDTH_IN is
when 8 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 16 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 32 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 64 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 128 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 256 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 512 => IP_Addr_Start := 5; IP_Addr_Stop := 5;
when others => IP_Addr_Start := 5; IP_Addr_Stop := 6;
end case;
when 512 =>
case C_DWIDTH_IN is
when 8 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 16 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 32 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 64 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 128 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 256 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 512 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when others => IP_Addr_Start := 6; IP_Addr_Stop := 6;
end case;
when others => IP_Addr_Start := -1; IP_Addr_Stop := -1;
end case;
return IP_Addr_Start;
end function Addr_Start_Func;
function Addr_Stop_Func (C_SMALLEST_OUT : integer;
C_DWIDTH_IN : integer)
return integer is
variable IP_Addr_Start : integer;
variable IP_Addr_Stop : integer;
begin
case C_SMALLEST_OUT is
when 8 =>
case C_DWIDTH_IN is
when 8 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 16 => IP_Addr_Start := 0; IP_Addr_Stop := 0;
when 32 => IP_Addr_Start := 0; IP_Addr_Stop := 1;
when 64 => IP_Addr_Start := 0; IP_Addr_Stop := 2;
when 128 => IP_Addr_Start := 0; IP_Addr_Stop := 3;
when 256 => IP_Addr_Start := 0; IP_Addr_Stop := 4;
when 512 => IP_Addr_Start := 0; IP_Addr_Stop := 5;
when others => IP_Addr_Start := 0; IP_Addr_Stop := 6;
end case;
when 16 =>
case C_DWIDTH_IN is
when 8 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 16 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 32 => IP_Addr_Start := 1; IP_Addr_Stop := 1;
when 64 => IP_Addr_Start := 1; IP_Addr_Stop := 2;
when 128 => IP_Addr_Start := 1; IP_Addr_Stop := 3;
when 256 => IP_Addr_Start := 1; IP_Addr_Stop := 4;
when 512 => IP_Addr_Start := 1; IP_Addr_Stop := 5;
when others => IP_Addr_Start := 1; IP_Addr_Stop := 6;
end case;
when 32 =>
case C_DWIDTH_IN is
when 8 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 16 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 32 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 64 => IP_Addr_Start := 2; IP_Addr_Stop := 2;
when 128 => IP_Addr_Start := 2; IP_Addr_Stop := 3;
when 256 => IP_Addr_Start := 2; IP_Addr_Stop := 4;
when 512 => IP_Addr_Start := 2; IP_Addr_Stop := 5;
when others => IP_Addr_Start := 2; IP_Addr_Stop := 6;
end case;
when 64 =>
case C_DWIDTH_IN is
when 8 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 16 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 32 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 64 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 128 => IP_Addr_Start := 3; IP_Addr_Stop := 3;
when 256 => IP_Addr_Start := 3; IP_Addr_Stop := 4;
when 512 => IP_Addr_Start := 3; IP_Addr_Stop := 5;
when others => IP_Addr_Start := 3; IP_Addr_Stop := 6;
end case;
when 128 =>
case C_DWIDTH_IN is
when 8 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 16 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 32 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 64 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 128 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 256 => IP_Addr_Start := 4; IP_Addr_Stop := 4;
when 512 => IP_Addr_Start := 4; IP_Addr_Stop := 5;
when others => IP_Addr_Start := 4; IP_Addr_Stop := 6;
end case;
when 256 =>
case C_DWIDTH_IN is
when 8 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 16 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 32 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 64 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 128 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 256 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 512 => IP_Addr_Start := 5; IP_Addr_Stop := 5;
when others => IP_Addr_Start := 5; IP_Addr_Stop := 6;
end case;
when 512 =>
case C_DWIDTH_IN is
when 8 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 16 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 32 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 64 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 128 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 256 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when 512 => IP_Addr_Start := -1; IP_Addr_Stop := -1;
when others => IP_Addr_Start := 6; IP_Addr_Stop := 6;
end case;
when others => IP_Addr_Start := -1; IP_Addr_Stop := -1;
end case;
return IP_Addr_Stop;
end function Addr_Stop_Func;
constant Addr_Size : integer_array_type(0 to 63) :=
(1=>1,3=>1,5=>1,7=>1,9=>1,11=>1,13=>1,15=>1,
17=>1,19=>1,21=>1,23=>1,25=>1,27=>1,29=>1,31=>1,
33=>1,35=>1,37=>1,39=>1,41=>1,43=>1,45=>1,47=>1,
49=>1,51=>1,53=>1,55=>1,57=>1,59=>1,61=>1,63=>1,
2=>2,6=>2,10=>2,14=>2,18=>2,22=>2,26=>2,30=>2,
34=>2,38=>2,42=>2,46=>2,50=>2,54=>2,58=>2,62=>2,
4=>4,12=>4,20=>4,28=>4,36=>4,44=>4,52=>4,60=>4,
8=>8,24=>8,40=>8,56=>8,16=>16,48=>16,32=>32,0=>64);
constant IP_Addr_Start : integer := Addr_Start_Func(C_SMALLEST_OUT,C_DWIDTH_IN);
constant IP_Addr_Stop : integer := Addr_Stop_Func(C_SMALLEST_OUT,C_DWIDTH_IN);
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin -- architecture IMP
MUX_PROCESS: process( Data_In,Decode_size,Addr ) is
variable factor : integer;
variable addr_loop : integer;
variable addr_integer : integer;
variable num_addr_bits : integer;
variable size : integer;
variable address : integer;
variable data_address : integer;
variable replicate_factor : integer;
begin
num_addr_bits := IP_Addr_Stop-IP_Addr_Start+1;
-- Set up default condition
if C_DWIDTH_IN <= C_DWIDTH_OUT then
for i in 0 to C_DWIDTH_OUT/C_DWIDTH_IN-1 loop
Data_Out(i*C_DWIDTH_IN to (i+1)*C_DWIDTH_IN-1) <= Data_In;
end loop;
else
Data_Out <= Data_In(0 to C_DWIDTH_OUT-1);
end if;
if C_DWIDTH_IN > C_SMALLEST_IN then -- Data_Out is a function of Decode_size
for k in log2(C_SMALLEST_IN/8)+1 to log2(C_DWIDTH_IN/8)+1 loop -- 1,2,3,4,5,6,7 6 for now
factor := pwr(2,k)/2; -- 1,2,4,8,16,32,64 number of byte lanes
if Decode_size = Conv_std_logic_vector(k,3) then
if IP_Addr_Start > -1 then -- Data_Out IS a function of address -- TESTED
for j in 0 to pwr(2,num_addr_bits)-1 loop
if Addr(C_AWIDTH-IP_Addr_Stop-1 to C_AWIDTH-IP_Addr_Start-1) = Conv_std_logic_vector(j,num_addr_bits) then
address := j*pwr(2,IP_Addr_Start); -- generate real address from j loop variable
data_address := address;
if address = 0 then -- special case for address zero
size := factor*8; -- size in bits
end if;
if address > 0 then -- else look up in size table
size := ADDR_SIZE(address)*8; -- size in bits
end if;
if size <= C_DWIDTH_OUT then -- for case when data at address is smaller than host data bus
replicate_factor := C_DWIDTH_OUT/size;
while data_address >= factor loop -- modulo operator since mod doesn't work in Synplify if right side isn't constant
data_address := data_address - factor;
end loop;
for r in 0 to replicate_factor-1 loop
for m in 0 to size-1 loop -- set first "size" data to data on Data_In at "address"
Data_Out(r*size+m) <= Data_In(data_address*8 + m);
end loop;
end loop;
else -- for case when data at address is larger than host data bus, just det first C_DWIDTH_OUT bits
Data_Out(0 to C_DWIDTH_OUT-1) <= Data_In(address*8 to address*8+C_DWIDTH_OUT-1);
end if;
end if;
end loop;
else -- Data_Out is not a function of address
if factor*8 <= C_DWIDTH_OUT then
for m in 0 to C_DWIDTH_OUT/(factor*8)-1 loop
Data_Out(factor*8*m to factor*8*(m+1)-1) <= Data_In(0 to factor*8-1);
end loop;
else
for m in 0 to C_DWIDTH_OUT-1 loop
Data_Out(m) <= Data_In(m mod C_DWIDTH_IN); -- just carry data across.
end loop;
end if;
end if;
end if;
end loop;
else -- Data_Out is not a function of Decode_Size
if IP_Addr_Start > -1 then -- Data_Out IS a function of address -- TESTED
for j in 0 to pwr(2,num_addr_bits)-1 loop
if Addr(C_AWIDTH-IP_Addr_Stop-1 to C_AWIDTH-IP_Addr_Start-1) = Conv_std_logic_vector(j,num_addr_bits) then
address := j*pwr(2,IP_Addr_Start); -- generate real address from j loop variable
if address = 0 then -- special case for address zero
size := C_DWIDTH_IN; -- size in bits
end if;
if address > 0 then -- else look up in size table
size := ADDR_SIZE(address)*8; -- size in bits
end if;
if size <= C_DWIDTH_OUT then -- for case when data at address is smaller than host data bus
replicate_factor := C_DWIDTH_OUT/size;
for r in 0 to replicate_factor-1 loop
for m in 0 to size-1 loop -- set first "size" data to data on Data_In at "address"
Data_Out(r*size+m) <= Data_In(address*8+m);
end loop;
end loop;
-- for m in size to C_DWIDTH_OUT-1 loop -- set remaining bits to default
-- Data_Out(m) <= Data_In(m mod C_DWIDTH_IN); -- mod in case host data bus larger than Data_In
-- end loop;
else -- for case when data at address is larger than host data bus, just det first C_DWIDTH_OUT bits
Data_Out(0 to C_DWIDTH_OUT-1) <= Data_In(address*8 to address*8+C_DWIDTH_OUT-1);
end if;
end if;
end loop;
else -- Data_Out is not a function of address
for m in 0 to C_DWIDTH_OUT-1 loop -- 0 to 3
Data_Out(m) <= Data_In(m mod C_DWIDTH_IN); -- just carry data across.
end loop;
end if;
end if;
end process MUX_PROCESS;
end architecture IMP;
|
bsd-3-clause
|
masson2013/heterogeneous_hthreads
|
src/hardware/MyRepository/pcores/hw_threads/hw_acc_v1_00_a/hdl/vhdl/user_logics/functional/attr_destroy_2.vhd
|
2
|
15751
|
---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
FUNCTION_EXIT,
STATE_1,
STATE_2,
STATE_3,
STATE_4,
STATE_5,
STATE_6,
STATE_7,
STATE_8,
STATE_9,
STATE_10,
STATE_11,
STATE_12,
STATE_13,
STATE_14,
STATE_15,
STATE_16,
STATE_17,
STATE_18,
STATE_19,
STATE_20,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_STATE_1 : std_logic_vector(0 to 15) := x"0101";
constant U_STATE_2 : std_logic_vector(0 to 15) := x"0102";
constant U_STATE_3 : std_logic_vector(0 to 15) := x"0103";
constant U_STATE_4 : std_logic_vector(0 to 15) := x"0104";
constant U_STATE_5 : std_logic_vector(0 to 15) := x"0105";
constant U_STATE_6 : std_logic_vector(0 to 15) := x"0106";
constant U_STATE_7 : std_logic_vector(0 to 15) := x"0107";
constant U_STATE_8 : std_logic_vector(0 to 15) := x"0108";
constant U_STATE_9 : std_logic_vector(0 to 15) := x"0109";
constant U_STATE_10 : std_logic_vector(0 to 15) := x"0110";
constant U_STATE_11 : std_logic_vector(0 to 15) := x"0111";
constant U_STATE_12 : std_logic_vector(0 to 15) := x"0112";
constant U_STATE_13 : std_logic_vector(0 to 15) := x"0113";
constant U_STATE_14 : std_logic_vector(0 to 15) := x"0114";
constant U_STATE_15 : std_logic_vector(0 to 15) := x"0115";
constant U_STATE_16 : std_logic_vector(0 to 15) := x"0116";
constant U_STATE_17 : std_logic_vector(0 to 15) := x"0117";
constant U_STATE_18 : std_logic_vector(0 to 15) := x"0118";
constant U_STATE_19 : std_logic_vector(0 to 15) := x"0119";
constant U_STATE_20 : std_logic_vector(0 to 15) := x"0120";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
signal retVal, retVal_next : std_logic_vector(0 to 31);
signal arg, arg_next : std_logic_vector(0 to 31);
signal reg1, reg1_next : std_logic_vector(0 to 31);
signal reg2, reg2_next : std_logic_vector(0 to 31);
signal reg3, reg3_next : std_logic_vector(0 to 31);
signal reg4, reg4_next : std_logic_vector(0 to 31);
signal reg5, reg5_next : std_logic_vector(0 to 31);
signal reg6, reg6_next : std_logic_vector(0 to 31);
signal reg7, reg7_next : std_logic_vector(0 to 31);
signal reg8, reg8_next : std_logic_vector(0 to 31);
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock, intrfc2thrd_goWait) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
return_state <= return_state_next;
retVal <= retVal_next;
arg <= arg_next;
reg1 <= reg1_next;
reg2 <= reg2_next;
reg3 <= reg3_next;
reg4 <= reg4_next;
reg5 <= reg5_next;
reg6 <= reg6_next;
reg7 <= reg7_next;
reg8 <= reg8_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_STATE_1 =>
current_state <= STATE_1;
when U_STATE_2 =>
current_state <= STATE_2;
when U_STATE_3 =>
current_state <= STATE_3;
when U_STATE_4 =>
current_state <= STATE_4;
when U_STATE_5 =>
current_state <= STATE_5;
when U_STATE_6 =>
current_state <= STATE_6;
when U_STATE_7 =>
current_state <= STATE_7;
when U_STATE_8 =>
current_state <= STATE_8;
when U_STATE_9 =>
current_state <= STATE_9;
when U_STATE_10 =>
current_state <= STATE_10;
when U_STATE_11 =>
current_state <= STATE_11;
when U_STATE_12 =>
current_state <= STATE_12;
when U_STATE_13 =>
current_state <= STATE_13;
when U_STATE_14 =>
current_state <= STATE_14;
when U_STATE_15 =>
current_state <= STATE_15;
when U_STATE_16 =>
current_state <= STATE_16;
when U_STATE_17 =>
current_state <= STATE_17;
when U_STATE_18 =>
current_state <= STATE_18;
when U_STATE_19 =>
current_state <= STATE_19;
when U_STATE_20 =>
current_state <= STATE_20;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
retVal_next <= retVal;
arg_next <= arg;
reg1_next <= reg1;
reg2_next <= reg2;
reg3_next <= reg3;
reg4_next <= reg4;
reg5_next <= reg5;
reg6_next <= reg6;
reg7_next <= reg7;
reg8_next <= reg8;
-- attr_destroy_2.c
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
-- hthread_attr_t * attr = (hthread_attr_t *) arg
when FUNCTION_START =>
-- Pop the argument
thrd2intrfc_value <= Z32;
thrd2intrfc_opcode <= OPCODE_POP;
next_state <= WAIT_STATE;
return_state_next <= STATE_1;
-- hthread_attr_init( attr );
when STATE_1 =>
-- Push the argument to hthread_attr_init
arg_next <= intrfc2thrd_value;
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= intrfc2thrd_value;
next_state <= WAIT_STATE;
return_state_next <= STATE_2;
when STATE_2 =>
-- Call hthread_attr_init
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_ATTR_INIT;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_3;
next_state <= WAIT_STATE;
-- hthread_attr_destroy( attr );
when STATE_3 =>
-- Push the argument to hthread_attr_init
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg;
next_state <= WAIT_STATE;
return_state_next <= STATE_4;
when STATE_4 =>
-- Call hthread_attr_destroy
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_ATTR_DESTROY;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_5;
next_state <= WAIT_STATE;
-- retVal = hthread_attr_init( attr );
when STATE_5 =>
-- Push the argument to hthread_attr_init
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg;
next_state <= WAIT_STATE;
return_state_next <= STATE_6;
when STATE_6 =>
-- Call hthread_attr_init
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_ATTR_INIT;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_7;
next_state <= WAIT_STATE;
when STATE_7 =>
retVal_next <= intrfc2thrd_value;
next_state <= FUNCTION_EXIT;
when FUNCTION_EXIT =>
--Same as hthread_exit( (void *) retVal );
thrd2intrfc_value <= retVal;
thrd2intrfc_opcode <= OPCODE_RETURN;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
|
bsd-3-clause
|
masson2013/heterogeneous_hthreads
|
src/hardware/MyRepository/pcores/axi_hthread_cores/proc_common_v3_00_a/hdl/vhdl/srl_fifo2.vhd
|
2
|
14431
|
-------------------------------------------------------------------------------
-- $Id: srl_fifo2.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- srl_fifo2 - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2002-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: srl_fifo2.vhd
--
-- Description: same as srl_fifo except the Addr port has the correct bit
-- ordering, there is a true FIFO_Empty port, and the C_DEPTH
-- generic actually controlls how many elements the fifo will
-- hold (up to 16). includes an assertion statement to check
-- that C_DEPTH is less than or equal to 16. changed
-- C_DATA_BITS to C_DWIDTH and changed it from natural to
-- positive (the width should be 1 or greater, zero width
-- didn't make sense to me!). Changed C_DEPTH from natural
-- to positive (zero elements doesn't make sense).
-- The Addr port in srl_fifo has the bits reversed which
-- made it more difficult to use. C_DEPTH was not used in
-- srl_fifo. Data_Exists is delayed by one clock so it is
-- not usefull for generating an empty flag. FIFO_Empty is
-- generated directly from the address, the same way that
-- FIFO_Full is generated.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl_fifo2.vhd
--
-------------------------------------------------------------------------------
-- Author: jam
--
-- History:
-- jam 02/20/02 First Version - modified from original srl_fifo
--
-- DCW 2002-03-12 Structural implementation of synchronous reset for
-- Data_Exists DFF (using FDR)
-- jam 04/12/02 Added C_XON generic for mixed vhdl/verilog sims
--
-- als 2002-04-18 added default for XON generic in SRL16E, FDRE, and FDR
-- component declarations
-- jam 2002-05-01 changed FIFO_Empty output from buffer_Empty, which had a
-- clock delay, to the not of data_Exists_I, which doesn't
-- have any delay
--
-- DET 1/17/2008 v3_00_a
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
library unisim;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all; -- conv_std_logic_vector
use unisim.all;
entity srl_fifo2 is
generic (
C_DWIDTH : positive := 8; -- changed to positive
C_DEPTH : positive := 16; -- changed to positive
C_XON : boolean := false -- added for mixed mode sims
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DWIDTH-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
FIFO_Full : out std_logic;
FIFO_Empty : out std_logic; -- new port
Data_Exists : out std_logic;
Addr : out std_logic_vector(0 to 3)
);
end entity srl_fifo2;
architecture imp of srl_fifo2 is
-- convert C_DEPTH to a std_logic_vector so FIFO_Full can be generated
-- based on the selected depth rather than fixed at 16
constant DEPTH : std_logic_vector(0 to 3) :=
conv_std_logic_vector(C_DEPTH-1,4);
component SRL16E is
-- pragma translate_off
generic (
INIT : bit_vector := X"0000"
);
-- pragma translate_on
port (
CE : in std_logic;
D : in std_logic;
Clk : in std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
Q : out std_logic);
end component SRL16E;
-- component LUT4
-- generic(
-- INIT : bit_vector := X"0000"
-- );
-- port (
-- O : out std_logic;
-- I0 : in std_logic;
-- I1 : in std_logic;
-- I2 : in std_logic;
-- I3 : in std_logic);
-- end component;
component MULT_AND
port (
I0 : in std_logic;
I1 : in std_logic;
LO : out std_logic);
end component;
component MUXCY_L
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
LO : out std_logic);
end component;
component XORCY
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic);
end component FDRE;
component FDR is
port (
Q : out std_logic;
C : in std_logic;
D : in std_logic;
R : in std_logic);
end component FDR;
signal addr_i : std_logic_vector(0 to 3);
signal buffer_Full : std_logic;
signal buffer_Empty : std_logic;
signal next_Data_Exists : std_logic;
signal data_Exists_I : std_logic;
signal valid_Write : std_logic;
signal hsum_A : std_logic_vector(0 to 3);
signal sum_A : std_logic_vector(0 to 3);
signal addr_cy : std_logic_vector(0 to 4);
begin -- architecture IMP
-- C_DEPTH is positive so that ensures the fifo is at least 1 element deep
-- make sure it is not greater than 16 locations deep
-- pragma translate_off
assert C_DEPTH <= 16
report "SRL Fifo's must be 16 or less elements deep"
severity FAILURE;
-- pragma translate_on
-- since srl16 address is 3 downto 0 need to compare individual bits
-- didn't muck with addr_i since the basic addressing works - Addr output
-- is generated correctly below
buffer_Full <= '1' when (addr_i(0) = DEPTH(3) and
addr_i(1) = DEPTH(2) and
addr_i(2) = DEPTH(1) and
addr_i(3) = DEPTH(0)
) else '0';
FIFO_Full <= buffer_Full;
buffer_Empty <= '1' when (addr_i = "0000") else '0';
FIFO_Empty <= not data_Exists_I; -- generate a true empty flag with no delay
-- was buffer_Empty, which had a clock dly
next_Data_Exists <= (data_Exists_I and not buffer_Empty) or
(buffer_Empty and FIFO_Write) or
(data_Exists_I and not FIFO_Read);
Data_Exists_DFF : FDR
port map (
Q => data_Exists_I, -- [out std_logic]
C => Clk, -- [in std_logic]
D => next_Data_Exists, -- [in std_logic]
R => Reset); -- [in std_logic]
Data_Exists <= data_Exists_I;
valid_Write <= FIFO_Write and (FIFO_Read or not buffer_Full);
addr_cy(0) <= valid_Write;
Addr_Counters : for I in 0 to 3 generate
hsum_A(I) <= (FIFO_Read xor addr_i(I)) and (FIFO_Write or not buffer_Empty);
MUXCY_L_I : MUXCY_L
port map (
DI => addr_i(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
S => hsum_A(I), -- [in std_logic]
LO => addr_cy(I+1)); -- [out std_logic]
XORCY_I : XORCY
port map (
LI => hsum_A(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
O => sum_A(I)); -- [out std_logic]
FDRE_I : FDRE
port map (
Q => addr_i(I), -- [out std_logic]
C => Clk, -- [in std_logic]
CE => data_Exists_I, -- [in std_logic]
D => sum_A(I), -- [in std_logic]
R => Reset); -- [in std_logic]
end generate Addr_Counters;
FIFO_RAM : for I in 0 to C_DWIDTH-1 generate
SRL16E_I : SRL16E
-- pragma translate_off
generic map (
INIT => x"0000")
-- pragma translate_on
port map (
CE => valid_Write, -- [in std_logic]
D => Data_In(I), -- [in std_logic]
Clk => Clk, -- [in std_logic]
A0 => addr_i(0), -- [in std_logic]
A1 => addr_i(1), -- [in std_logic]
A2 => addr_i(2), -- [in std_logic]
A3 => addr_i(3), -- [in std_logic]
Q => Data_Out(I)); -- [out std_logic]
end generate FIFO_RAM;
-------------------------------------------------------------------------------
-- INT_ADDR_PROCESS
-------------------------------------------------------------------------------
-- This process assigns the internal address to the output port
-------------------------------------------------------------------------------
-- modified the process to flip the bits since the address bits from the
-- srl16 are 3 downto 0 and Addr needs to be 0 to 3
INT_ADDR_PROCESS:process (addr_i)
begin -- process
for i in Addr'range
loop
Addr(i) <= addr_i(3 - i); -- flip the bits to account for srl16 addr
end loop;
end process;
end architecture imp;
|
bsd-3-clause
|
masson2013/heterogeneous_hthreads
|
src/hardware/MyRepository/pcores/plb_hwt_exit_v1_00_a/hdl/vhdl/old/testbench.vhd
|
3
|
27888
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v1_00_b;
use proc_common_v1_00_b.proc_common_pkg.all;
library ipif_common_v1_00_e;
use ipif_common_v1_00_e.ipif_pkg.all;
library plb_ipif_v2_01_a;
use plb_ipif_v2_01_a.all;
library plb_hwti_v1_00_a;
use plb_hwti_v1_00_a.all;
library plb_v34_v1_02_a;
library opb_v20_v1_10_c;
library plb2opb_bridge_v1_01_a;
entity testbench is
end entity;
architecture behavioral of testbench is
constant PLB_NUM_MASTERS : integer := 1;
constant PLB_NUM_SLAVES : integer := 1;
constant PLB_AWIDTH : integer := 32;
constant PLB_DWIDTH : integer := 64;
constant OPB_NUM_MASTERS : integer := 1;
constant OPB_NUM_SLAVES : integer := 1;
constant OPB_AWIDTH : integer := 32;
constant OPB_DWIDTH : integer := 32;
constant DCR_AWIDTH : integer := 10;
constant DCR_DWIDTH : integer := 32;
constant PLB_MID_WIDTH : integer := 2;
constant PLB_TAWIDTH : integer := PLB_NUM_MASTERS*PLB_AWIDTH;
constant PLB_TDWIDTH : integer := PLB_NUM_MASTERS*PLB_DWIDTH;
constant PLB_SAWIDTH : integer := PLB_NUM_SLAVES*PLB_AWIDTH;
constant PLB_SDWIDTH : integer := PLB_NUM_SLAVES*PLB_DWIDTH;
constant PLB_SLVMST : integer := PLB_NUM_SLAVES*PLB_NUM_MASTERS;
constant HWTI_SLV : integer := 0;
constant HWTI_MST : integer := 0;
-- Signals for the PLB bus
signal PLB_SaddrAck : std_logic;
signal PLB2OPB_rearb : std_logic_vector(0 to PLB_NUM_SLAVES-1);
signal DCR_ABus : std_logic_vector(0 to DCR_AWIDTH-1);
signal DCR_DBus : std_logic_vector(0 to DCR_DWIDTH-1);
signal DCR_Read : std_logic;
signal DCR_Write : std_logic;
signal PLB_dcrAck : std_logic;
signal PLB_dcrDBus : std_logic_vector(0 to DCR_DWIDTH-1);
signal M_ABus : std_logic_vector(0 to PLB_TAWIDTH-1);
signal M_BE : std_logic_vector(0 to PLB_TDWIDTH/8-1);
signal M_RNW : std_logic_vector(0 to PLB_NUM_MASTERS-1);
signal M_abort : std_logic_vector(0 to PLB_NUM_MASTERS-1);
signal M_busLock : std_logic_vector(0 to PLB_NUM_MASTERS-1);
signal M_compress : std_logic_vector(0 to PLB_NUM_MASTERS-1);
signal M_guarded : std_logic_vector(0 to PLB_NUM_MASTERS-1);
signal M_lockErr : std_logic_vector(0 to PLB_NUM_MASTERS-1);
signal M_MSize : std_logic_vector(0 to PLB_NUM_MASTERS*2-1);
signal M_ordered : std_logic_vector(0 to PLB_NUM_MASTERS-1);
signal M_priority : std_logic_vector(0 to PLB_NUM_MASTERS*2-1);
signal M_rdBurst : std_logic_vector(0 to PLB_NUM_MASTERS-1);
signal M_request : std_logic_vector(0 to PLB_NUM_MASTERS-1);
signal M_size : std_logic_vector(0 to PLB_NUM_MASTERS*4-1);
signal M_type : std_logic_vector(0 to PLB_NUM_MASTERS*3-1);
signal M_wrBurst : std_logic_vector(0 to PLB_NUM_MASTERS-1);
signal M_wrDBus : std_logic_vector(0 to PLB_TDWIDTH-1);
signal PLB_ABus : std_logic_vector(0 to PLB_AWIDTH-1);
signal PLB_BE : std_logic_vector(0 to PLB_DWIDTH/8-1);
signal PLB_MAddrAck : std_logic_vector(0 to PLB_NUM_MASTERS-1);
signal PLB_MBusy : std_logic_vector(0 to PLB_NUM_MASTERS-1);
signal PLB_MErr : std_logic_vector(0 to PLB_NUM_MASTERS-1);
signal PLB_MRdBTerm : std_logic_vector(0 to PLB_NUM_MASTERS-1);
signal PLB_MRdDAck : std_logic_vector(0 to PLB_NUM_MASTERS-1);
signal PLB_MRdDBus : std_logic_vector(0 to PLB_TDWIDTH-1);
signal PLB_MRdWdAddr : std_logic_vector(0 to PLB_NUM_MASTERS*4-1);
signal PLB_MRearbitrate : std_logic_vector(0 to PLB_NUM_MASTERS-1);
signal PLB_MWrBTerm : std_logic_vector(0 to PLB_NUM_MASTERS-1);
signal PLB_MWrDAck : std_logic_vector(0 to PLB_NUM_MASTERS-1);
signal PLB_MSSize : std_logic_vector(0 to PLB_NUM_MASTERS*2-1);
signal PLB_PAValid : std_logic;
signal PLB_RNW : std_logic;
signal PLB_SAValid : std_logic;
signal PLB_abort : std_logic;
signal PLB_busLock : std_logic;
signal PLB_compress : std_logic;
signal PLB_guarded : std_logic;
signal PLB_lockErr : std_logic;
signal PLB_masterID : std_logic_vector(0 to PLB_MID_WIDTH-1);
signal PLB_MSize : std_logic_vector(0 to 1);
signal PLB_ordered : std_logic;
signal PLB_pendPri : std_logic_vector(0 to 1);
signal PLB_pendReq : std_logic;
signal PLB_rdBurst : std_logic;
signal PLB_rdPrim : std_logic;
signal PLB_reqPri : std_logic_vector(0 to 1);
signal PLB_size : std_logic_vector(0 to 3);
signal PLB_type : std_logic_vector(0 to 2);
signal PLB_wrBurst : std_logic;
signal PLB_wrDBus : std_logic_vector(0 to PLB_DWIDTH-1);
signal PLB_wrPrim : std_logic;
signal Sl_addrAck : std_logic_vector(0 to PLB_NUM_SLAVES-1);
signal Sl_MErr : std_logic_vector(0 to PLB_SLVMST-1);
signal Sl_MBusy : std_logic_vector(0 to PLB_SLVMST-1);
signal Sl_rdBTerm : std_logic_vector(0 to PLB_NUM_SLAVES-1);
signal Sl_rdComp : std_logic_vector(0 to PLB_NUM_SLAVES-1);
signal Sl_rdDAck : std_logic_vector(0 to PLB_NUM_SLAVES-1);
signal Sl_rdDBus : std_logic_vector(0 to PLB_SDWIDTH-1);
signal Sl_rdWdAddr : std_logic_vector(0 to PLB_NUM_SLAVES*4-1);
signal Sl_rearbitrate : std_logic_vector(0 to PLB_NUM_SLAVES-1);
signal Sl_SSize : std_logic_vector(0 to PLB_NUM_SLAVES*2-1);
signal Sl_wait : std_logic_vector(0 to PLB_NUM_SLAVES-1);
signal Sl_wrBTerm : std_logic_vector(0 to PLB_NUM_SLAVES-1);
signal Sl_wrComp : std_logic_vector(0 to PLB_NUM_SLAVES-1);
signal Sl_wrDAck : std_logic_vector(0 to PLB_NUM_SLAVES-1);
signal PLB_SMErr : std_logic_vector(0 to PLB_NUM_MASTERS-1);
signal PLB_SMBusy : std_logic_vector(0 to PLB_NUM_MASTERS-1);
signal PLB_SrdBTerm : std_logic;
signal PLB_SrdComp : std_logic;
signal PLB_SrdDAck : std_logic;
signal PLB_SrdDBus : std_logic_vector(0 to PLB_DWIDTH-1);
signal PLB_SrdWdAddr : std_logic_vector(0 to 3);
signal PLB_Srearbitrate : std_logic;
signal PLB_Sssize : std_logic_vector(0 to 1);
signal PLB_Swait : std_logic;
signal PLB_SwrBTerm : std_logic;
signal PLB_SwrComp : std_logic;
signal PLB_SwrDAck : std_logic;
signal ArbAddrVldReg : std_logic;
signal SYS_Rst : std_logic;
signal Bus_Error_Det : std_logic;
signal PLB_Rst : std_logic;
signal PLB_Clk : std_logic;
-- Signals for the OPB bus
signal Debug_SYS_Rst : std_logic;
signal WDT_Rst : std_logic;
signal OPB_Clk : std_logic;
signal OPB_Rst : std_logic;
signal OM_ABus : std_logic_vector(0 to OPB_AWIDTH*OPB_NUM_MASTERS-1);
signal OM_BE : std_logic_vector(0 to (OPB_DWIDTH+7)/8*OPB_NUM_MASTERS-1);
signal OM_beXfer : std_logic_vector(0 to OPB_NUM_MASTERS-1);
signal OM_busLock : std_logic_vector(0 to OPB_NUM_MASTERS-1);
signal OM_DBus : std_logic_vector(0 to OPB_DWIDTH*OPB_NUM_MASTERS-1);
signal OM_DBusEn : std_logic_vector(0 to OPB_NUM_MASTERS-1);
signal OM_DBusEn32_63 : std_logic_vector(0 to OPB_NUM_MASTERS-1);
signal OM_dwXfer : std_logic_vector(0 to OPB_NUM_MASTERS-1);
signal OM_fwXfer : std_logic_vector(0 to OPB_NUM_MASTERS-1);
signal OM_hwXfer : std_logic_vector(0 to OPB_NUM_MASTERS-1);
signal OM_request : std_logic_vector(0 to OPB_NUM_MASTERS-1);
signal OM_RNW : std_logic_vector(0 to OPB_NUM_MASTERS-1);
signal OM_select : std_logic_vector(0 to OPB_NUM_MASTERS-1);
signal OM_seqAddr : std_logic_vector(0 to OPB_NUM_MASTERS-1);
signal OSl_beAck : std_logic_vector(0 to OPB_NUM_SLAVES-1);
signal OSl_DBus : std_logic_vector(0 to OPB_DWIDTH*OPB_NUM_SLAVES-1);
signal OSl_DBusEn : std_logic_vector(0 to OPB_NUM_SLAVES-1);
signal OSl_DBusEn32_63 : std_logic_vector(0 to OPB_NUM_SLAVES-1);
signal OSl_errAck : std_logic_vector(0 to OPB_NUM_SLAVES-1);
signal OSl_dwAck : std_logic_vector(0 to OPB_NUM_SLAVES-1);
signal OSl_fwAck : std_logic_vector(0 to OPB_NUM_SLAVES-1);
signal OSl_hwAck : std_logic_vector(0 to OPB_NUM_SLAVES-1);
signal OSl_retry : std_logic_vector(0 to OPB_NUM_SLAVES-1);
signal OSl_toutSup : std_logic_vector(0 to OPB_NUM_SLAVES-1);
signal OSl_xferAck : std_logic_vector(0 to OPB_NUM_SLAVES-1);
signal OPB_MRequest : std_logic_vector(0 to OPB_NUM_MASTERS-1);
signal OPB_ABus : std_logic_vector(0 to OPB_AWIDTH-1);
signal OPB_BE : std_logic_vector(0 to (OPB_DWIDTH+7)/8-1);
signal OPB_beXfer : std_logic;
signal OPB_beAck : std_logic;
signal OPB_busLock : std_logic;
signal OPB_rdDBus : std_logic_vector(0 to OPB_DWIDTH-1);
signal OPB_wrDBus : std_logic_vector(0 to OPB_DWIDTH-1);
signal OPB_DBus : std_logic_vector(0 to OPB_DWIDTH-1);
signal OPB_errAck : std_logic;
signal OPB_dwAck : std_logic;
signal OPB_dwXfer : std_logic;
signal OPB_fwAck : std_logic;
signal OPB_fwXfer : std_logic;
signal OPB_hwAck : std_logic;
signal OPB_hwXfer : std_logic;
signal OPB_MGrant : std_logic_vector(0 to OPB_NUM_MASTERS-1);
signal OPB_pendReq : std_logic_vector(0 to OPB_NUM_MASTERS-1);
signal OPB_retry : std_logic;
signal OPB_RNW : std_logic;
signal OPB_select : std_logic;
signal OPB_seqAddr : std_logic;
signal OPB_timeout : std_logic;
signal OPB_toutSup : std_logic;
signal OPB_xferAck : std_logic;
-- Signals for the PLB2OPB bridge
PLB_Rst : std_logic; -- unused input
PLB_Clk : std_logic;
OPB_Rst : std_logic;
OPB_Clk : std_logic;
Bus_Error_Det : std_logic;
BGI_Trans_Abort : std_logic;
PLB_abort : std_logic;
PLB_ABus : std_logic_vector (0 to C_PLB_AWIDTH-1);
PLB_BE : std_logic_vector (0 to C_PLB_DWIDTH/8-1);
PLB_busLock : std_logic;
PLB_compress : std_logic;
PLB_guarded : std_logic;
PLB_lockErr : std_logic;
PLB_masterID : std_logic_vector (0 to C_PLB_MID_WIDTH-1);
PLB_MSize : std_logic_vector (0 to 1);
PLB_ordered : std_logic;
PLB_PAValid : std_logic;
PLB_RNW : std_logic;
PLB_size : std_logic_vector (0 to 3);
PLB_type : std_logic_vector (0 to 2);
BGO_addrAck : std_logic;
BGO_MBusy : std_logic_vector (0 to C_PLB_NUM_MASTERS-1);
BGO_MErr : std_logic_vector (0 to C_PLB_NUM_MASTERS-1);
BGO_rearbitrate : std_logic;
BGO_SSize : std_logic_vector (0 to 1);
BGO_wait : std_logic;
PLB_rdPrim : std_logic;
PLB_SAValid : std_logic;
PLB_wrPrim : std_logic;
PLB_wrBurst : std_logic;
PLB_wrDBus : std_logic_vector (0 to C_PLB_DWIDTH-1);
BGO_wrBTerm : std_logic;
BGO_wrComp : std_logic;
BGO_wrDAck : std_logic;
PLB_rdBurst : std_logic;
BGO_rdBTerm : std_logic;
BGO_rdComp : std_logic;
BGO_rdDAck : std_logic;
BGO_rdDBus : std_logic_vector (0 to C_PLB_DWIDTH-1);
BGO_rdWdAddr : std_logic_vector (0 to 3) ;
OPB_DBus : std_logic_vector (0 to C_OPB_DWIDTH-1);
OPB_errAck : std_logic;
OPB_MnGrant : std_logic;
OPB_retry : std_logic;
OPB_timeout : std_logic;
OPB_xferAck : std_logic;
BGO_ABus : std_logic_vector (0 to C_OPB_AWIDTH-1);
BGO_BE : std_logic_vector (0 to C_OPB_DWIDTH/8-1) ;
BGO_busLock : std_logic;
BGO_DBus : std_logic_vector (0 to C_OPB_DWIDTH-1);
BGO_request : std_logic;
BGO_RNW : std_logic;
BGO_select : std_logic;
BGO_seqAddr : std_logic;
DCR_ABus : std_logic_vector (0 to C_DCR_AWIDTH-1);
DCR_DBus : std_logic_vector (0 to C_DCR_DWIDTH-1);
DCR_Read : std_logic;
DCR_Write : std_logic;
BGO_dcrAck : std_logic;
BGO_dcrDBus : std_logic_vector (0 to C_DCR_DWIDTH-1);
PLB2OPB_rearb : std_logic
-- Signals for the HWTI
signal tid : std_logic_vector(0 to 7);
signal arg : std_logic_vector(0 to 31);
signal opgo : std_logic;
signal opcode : std_logic_vector(0 to 7);
signal oparg : std_logic_vector(0 to 31);
signal opack : std_logic;
signal operr : std_logic;
signal opres : std_logic_vector(0 to 31);
begin
ihwti : entity plb_hwti_v1_00_a.plb_hwti
generic map
(
C_MANAG_BASEADDR => x"00000000",
C_SCHED_BASEADDR => x"00000000",
C_MUTEX_BASEADDR => x"00000000",
C_CONDV_BASEADDR => x"00000000",
C_BASEADDR => X"FFFFFFFF",
C_HIGHADDR => X"00000000",
C_PLB_AWIDTH => PLB_AWIDTH,
C_PLB_DWIDTH => PLB_DWIDTH,
C_PLB_NUM_MASTERS => PLB_NUM_MASTERS,
C_PLB_MID_WIDTH => PLB_MID_WIDTH
)
port map
(
tid => tid,
arg => arg,
opgo => opgo,
opcode => opcode,
oparg => oparg,
opack => opack,
operr => operr,
opres => opres,
PLB_Clk => PLB_Clk,
PLB_Rst => PLB_Rst,
Sl_addrAck => Sl_addrAck(0),
Sl_MBusy => Sl_MBusy(0*PLB_NUM_MASTERS to 1*PLB_NUM_MASTERS-1),
Sl_MErr => Sl_MErr(0*PLB_NUM_MASTERS to 1*PLB_NUM_MASTERS-1),
Sl_rdBTerm => Sl_rdBTerm(0),
Sl_rdComp => Sl_rdComp(0),
Sl_rdDAck => Sl_rdDAck(0),
Sl_rdDBus => Sl_rdDBus(0*PLB_DWIDTH to 1*PLB_DWIDTH-1),
Sl_rdWdAddr => Sl_rdWdAddr(0*4 to 1*4-1),
Sl_rearbitrate => Sl_rearbitrate(0),
Sl_SSize => Sl_SSize(0*2 to 1*2-1),
Sl_wait => Sl_wait(0),
Sl_wrBTerm => Sl_wrBTerm(0),
Sl_wrComp => Sl_wrComp(0),
Sl_wrDAck => SL_wrDAck(0),
PLB_abort => PLB_abort,
PLB_ABus => PLB_ABus,
PLB_BE => PLB_BE,
PLB_busLock => PLB_busLock,
PLB_compress => PLB_compress,
PLB_guarded => PLB_guarded,
PLB_lockErr => PLB_lockErr,
PLB_masterID => PLB_masterID,
PLB_MSize => PLB_MSize,
PLB_ordered => PLB_ordered,
PLB_PAValid => PLB_PAValid,
PLB_pendPri => PLB_pendPri,
PLB_pendReq => PLB_pendReq,
PLB_rdBurst => PLB_rdBurst,
PLB_rdPrim => PLB_rdPrim,
PLB_reqPri => PLB_reqPri,
PLB_RNW => PLB_RNW,
PLB_SAValid => PLB_SAValid,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_wrBurst => PLB_wrBurst,
PLB_wrDBus => PLB_wrDBus,
PLB_wrPrim => PLB_wrPrim,
M_abort => M_abort(0),
M_ABus => M_ABus(0*PLB_AWIDTH to 1*PLB_AWIDTH-1),
M_BE => M_BE(0*(PLB_DWIDTH/8) to 1*(PLB_DWIDTH/8)-1),
M_busLock => M_busLock(0),
M_compress => M_compress(0),
M_guarded => M_guarded(0),
M_lockErr => M_lockErr(0),
M_MSize => M_MSize(0*2 to 1*2-1),
M_ordered => M_ordered(0),
M_priority => M_priority(0*2 to 1*2-1),
M_rdBurst => M_rdBurst(0),
M_request => M_request(0),
M_RNW => M_RNW(0),
M_size => M_size(0*4 to 1*4-1),
M_type => M_type(0*3 to 1*3-1),
M_wrBurst => M_wrBurst(0),
M_wrDBus => M_wrDBus(0*PLB_DWIDTH to 1*PLB_DWIDTH-1),
PLB_MBusy => PLB_MBusy(0),
PLB_MErr => PLB_MErr(0),
PLB_MWrBTerm => PLB_MWrBTerm(0),
PLB_MWrDAck => PLB_MWrDAck(0),
PLB_MAddrAck => PLB_MAddrAck(0),
PLB_MRdBTerm => PLB_MRdBTerm(0),
PLB_MRdDAck => PLB_MRdDAck(0),
PLB_MRdDBus => PLB_MRdDBus(0*PLB_DWIDTH to 1*PLB_DWIDTH-1),
PLB_MRdWdAddr => PLB_MRdWdAddr(0*4 to 1*4-1),
PLB_MRearbitrate => PLB_MRearbitrate(0),
PLB_MSSize => PLB_MSSize(0*2 to 1*2-1)
);
iplb : entity plb_v34_v1_02_a.plb_v34
generic map
(
C_PLB_NUM_MASTERS => PLB_NUM_MASTERS,
C_PLB_NUM_SLAVES => PLB_NUM_SLAVES,
C_PLB_MID_WIDTH => PLB_MID_WIDTH,
C_PLB_AWIDTH => PLB_AWIDTH,
C_PLB_DWIDTH => PLB_DWIDTH,
C_DCR_INTFCE => 0,
C_BASEADDR => "1111111111",
C_HIGHADDR => "0000000000",
C_DCR_AWIDTH => DCR_AWIDTH,
C_DCR_DWIDTH => DCR_DWIDTH,
C_EXT_RESET_HIGH => 1,
C_IRQ_ACTIVE => '1',
C_NUM_OPBCLK_PLB2OPB_REARB => 25
)
port map
(
DCR_ABus => DCR_ABus,
DCR_DBus => DCR_DBus,
DCR_Read => DCR_Read,
DCR_Write => DCR_Write,
PLB_dcrAck => PLB_dcrAck,
PLB_dcrDBus => PLB_dcrDBus,
M_ABus => M_ABus,
M_BE => M_BE,
M_RNW => M_RNW,
M_abort => M_abort,
M_busLock => M_busLock,
M_compress => M_compress,
M_guarded => M_guarded,
M_lockErr => M_lockErr,
M_MSize => M_MSize,
M_ordered => M_ordered,
M_priority => M_priority,
M_rdBurst => M_rdBurst,
M_request => M_request,
M_size => M_size,
M_type => M_type,
M_wrBurst => M_wrBurst,
M_wrDBus => M_wrDBus,
PLB_ABus => PLB_ABus,
PLB_BE => PLB_BE,
PLB_MAddrAck => PLB_MAddrAck,
PLB_MBusy => PLB_MBusy,
PLB_MErr => PLB_MErr,
PLB_MRdBTerm => PLB_MRdBTerm,
PLB_MRdDAck => PLB_MRdDAck,
PLB_MRdDBus => PLB_MRdDBus,
PLB_MRdWdAddr => PLB_MRdWdAddr,
PLB_MRearbitrate => PLB_MRearbitrate,
PLB_MWrBTerm => PLB_MWrBTerm,
PLB_MWrDAck => PLB_MWrDAck,
PLB_MSSize => PLB_MSSize,
PLB_PAValid => PLB_PAValid,
PLB_RNW => PLB_RNW,
PLB_SAValid => PLB_SAValid,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_compress => PLB_compress,
PLB_guarded => PLB_guarded,
PLB_lockErr => PLB_lockErr,
PLB_masterID => PLB_masterID,
PLB_MSize => PLB_MSize,
PLB_ordered => PLB_ordered,
PLB_pendPri => PLB_pendPri,
PLB_pendReq => PLB_pendReq,
PLB_rdBurst => PLB_rdBurst,
PLB_rdPrim => PLB_rdPrim,
PLB_reqPri => PLB_reqPri,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_wrBurst => PLB_wrBurst,
PLB_wrDBus => PLB_wrDBus,
PLB_wrPrim => PLB_wrPrim,
Sl_addrAck => Sl_addrAck,
Sl_MErr => Sl_MErr,
Sl_MBusy => Sl_MBusy,
Sl_rdBTerm => Sl_rdBTerm,
Sl_rdComp => Sl_rdComp,
Sl_rdDAck => Sl_rdDAck,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rearbitrate => Sl_rearbitrate,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_wrBTerm => Sl_wrBTerm,
Sl_wrComp => Sl_wrComp,
Sl_wrDAck => Sl_wrDAck,
PLB_SaddrAck => PLB_SaddrAck,
PLB_SMErr => PLB_SMErr,
PLB_SMBusy => PLB_SMBusy,
PLB_SrdBTerm => PLB_SrdBTerm,
PLB_SrdComp => PLB_SrdComp,
PLB_SrdDAck => PLB_SrdDAck,
PLB_SrdDBus => PLB_SrdDBus,
PLB_SrdWdAddr => PLB_SrdWdAddr,
PLB_Srearbitrate => PLB_Srearbitrate,
PLB_Sssize => PLB_Sssize,
PLB_Swait => PLB_Swait,
PLB_SwrBTerm => PLB_SwrBTerm,
PLB_SwrComp => PLB_SwrComp,
PLB_SwrDAck => PLB_SwrDAck,
PLB2OPB_rearb => PLB2OPB_rearb,
ArbAddrVldReg => ArbAddrVldReg,
SYS_Rst => SYS_Rst,
Bus_Error_Det => Bus_Error_Det,
PLB_Rst => PLB_Rst,
PLB_Clk => PLB_Clk
);
iopb : entity opb_v20_v1_10_c.opb_v20
generic map
(
C_OPB_AWIDTH => OPB_AWIDTH,
C_OPB_DWIDTH => OPB_DWIDTH,
C_NUM_MASTERS => OPB_NUM_MASTERS,
C_NUM_SLAVES => OPB_NUM_SLAVES,
C_USE_LUT_OR => 0,
C_EXT_RESET_HIGH => 1,
C_BASEADDR => x"10000000",
C_HIGHADDR => x"100001FF",
C_DYNAM_PRIORITY => 1,
C_PARK => 1,
C_PROC_INTRFCE => 1,
C_REG_GRANTS => 1,
C_DEV_BLK_ID => 0,
C_DEV_MIR_ENABLE => 0
)
port map
(
SYS_Rst => SYS_Rst,
Debug_SYS_Rst => Debug_SYS_Rst,
WDT_Rst => WDT_Rst,
OPB_Clk => OPB_Clk,
OPB_Rst => OPB_Rst,
M_ABus => OM_ABus,
M_BE => OM_BE,
M_beXfer => OM_beXfer,
M_busLock => OM_busLock,
M_DBus => OM_DBus,
M_DBusEn => OM_DBusEn,
M_DBusEn32_63 => OM_DBusEn32_63,
M_dwXfer => OM_dwXfer,
M_fwXfer => OM_fwXfer,
M_hwXfer => OM_hwXfer,
M_request => OM_request,
M_RNW => OM_RNW,
M_select => OM_select,
M_seqAddr => OM_seqAddr,
Sl_beAck => OSl_beAck,
Sl_DBus => OSl_DBus,
Sl_DBusEn => OSl_DBusEn,
Sl_DBusEn32_63 => OSl_DBusEn32_63,
Sl_errAck => OSl_errAck,
Sl_dwAck => OSl_dwAck,
Sl_fwAck => OSl_fwAck,
Sl_hwAck => OSl_hwAck,
Sl_retry => OSl_retry,
Sl_toutSup => OSl_toutSup,
Sl_xferAck => OSl_xferAck,
OPB_MRequest => OPB_MRequest,
OPB_ABus => OPB_ABus,
OPB_BE => OPB_BE,
OPB_beXfer => OPB_beXfer,
OPB_beAck => OPB_beAck,
OPB_busLock => OPB_busLock,
OPB_rdDBus => OPB_rdDBus,
OPB_wrDBus => OPB_wrDBus,
OPB_DBus => OPB_DBus,
OPB_errAck => OPB_errAck,
OPB_dwAck => OPB_dwAck,
OPB_dwXfer => OPB_dwXfer,
OPB_fwAck => OPB_fwAck,
OPB_fwXfer => OPB_fwXfer,
OPB_hwAck => OPB_hwAck,
OPB_hwXfer => OPB_hwXfer,
OPB_MGrant => OPB_MGrant,
OPB_pendReq => OPB_pendReq,
OPB_retry => OPB_retry,
OPB_RNW => OPB_RNW,
OPB_select => OPB_select,
OPB_seqAddr => OPB_seqAddr,
OPB_timeout => OPB_timeout,
OPB_toutSup => OPB_toutSup,
OPB_xferAck => OPB_xferAck
);
iplb2opb : entity plb2opb_bridge_v1_01_a.plb2opb_bridge
generic map
(
C_NO_PLB_BURST => 0,
C_DCR_INTFCE => 0,
C_NUM_ADDR_RNG => 1,
C_RNG0_BASEADDR => x"00000000";
C_RNG0_HIGHADDR => x"0003FFFF";
C_RNG1_BASEADDR => x"00000000";
C_RNG1_HIGHADDR => x"00000000";
C_RNG2_BASEADDR => x"00000000";
C_RNG2_HIGHADDR => x"00000000";
C_RNG3_BASEADDR => x"00000000";
C_RNG3_HIGHADDR => x"00000000";
C_PLB_AWIDTH => PLB_AWIDTH,
C_PLB_DWIDTH => PLB_DWIDTH,
C_PLB_NUM_MASTERS => PLB_NUM_MASTERS,
C_PLB_MID_WIDTH => PLB_MID_WIDTH,
C_OPB_AWIDTH => OPB_AWIDTH,
C_OPB_DWIDTH => OPB_DWIDTH,
C_DCR_BASEADDR => "0000000000",
C_DCR_HIGHADDR => "0000000111",
C_DCR_AWIDTH => DCR_AWIDTH,
C_DCR_DWIDTH => DCR_DWIDTH
)
port map
(
PLB_Rst => PLB_Rst,
PLB_Clk => PLB_Clk,
OPB_Rst => OPB_Rst,
OPB_Clk => OPB_Clk,
Bus_Error_Det => Bus_Error_Det,
BGI_Trans_Abort => BGI_Trans_Abort,
PLB_abort => PLB_abort,
PLB_ABus => PLB_ABus,
PLB_BE => PLB_BE,
PLB_busLock => PLB_busLock,
PLB_compress => PLB_compress,
PLB_guarded => PLB_guarded,
PLB_lockErr => PLB_lockErr,
PLB_masterID => PLB_masterID,
PLB_MSize => PLB_MSize,
PLB_ordered => PLB_ordered,
PLB_PAValid => PLB_PAValid,
PLB_RNW => PLB_RNW,
PLB_size => PLB_size,
PLB_type => PLB_type,
BGO_addrAck => BGO_addrAck,
BGO_MBusy => BGO_MBusy,
BGO_MErr => BGO_MErr,
BGO_rearbitrate => BGO_rearbitrate,
BGO_SSize => BGO_SSize,
BGO_wait => BGO_wait,
PLB_rdPrim => PLB_rdPrim,
PLB_SAValid => PLB_SAValid,
PLB_wrPrim => PLB_wrPrim,
PLB_wrBurst => PLB_wrBurst,
PLB_wrDBus => PLB_wrDBus,
BGO_wrBTerm => BGO_wrBTerm,
BGO_wrComp => BGO_wrComp,
BGO_wrDAck => BGO_wrDAck,
PLB_rdBurst => PLB_rdBurst,
BGO_rdBTerm => BGO_rdBTerm,
BGO_rdComp => BGO_rdComp,
BGO_rdDAck => BGO_rdDAck,
BGO_rdDBus => BGO_rdDBus,
BGO_rdWdAddr => BGO_rdWdAddr,
OPB_DBus => OPB_DBus,
OPB_errAck => OPB_errAck,
OPB_MnGrant => OPB_MnGrant,
OPB_retry => OPB_retry,
OPB_timeout => OPB_timeout,
OPB_xferAck => OPB_xferAck,
BGO_ABus => BGO_ABus,
BGO_BE => BGO_BE,
BGO_busLock => BGO_busLock,
BGO_DBus => BGO_DBus,
BGO_request => BGO_request,
BGO_RNW => BGO_RNW,
BGO_select => BGO_select,
BGO_seqAddr => BGO_seqAddr,
DCR_ABus => DCR_ABus,
DCR_DBus => DCR_DBus,
DCR_Read => DCR_Read,
DCR_Write => DCR_Write,
BGO_dcrAck => BGO_dcrAck,
BGO_dcrDBus => BGO_dcrDBus,
PLB2OPB_rearb => PLB2OPB_rearb
);
end behavioral;
|
bsd-3-clause
|
masson2013/heterogeneous_hthreads
|
src/platforms/xilinx/smp3_opbhwti/design/pcores/opb_v20_v1_10_d/hdl/vhdl/watchdog_timer.vhd
|
3
|
12783
|
-------------------------------------------------------------------------------
-- $Id: watchdog_timer.vhd,v 1.1.2.1 2009/10/06 21:15:02 gburch Exp $
-------------------------------------------------------------------------------
-- watchdog_timer.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: watchdog_timer.vhd
-- Version: v1.02e
-- Description:
-- This file contains the watchdog timer and generates the
-- OPB_timeout signal if OPB_retry, OPB_xferAck, or
-- OPB_toutSup are not asserted within 15 clock cycles after
-- OPB_select is asserted.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- opb_arbiter.vhd
-- --opb_arbiter_core.vhd
-- -- ipif_regonly_slave.vhd
-- -- priority_register_logic.vhd
-- -- priority_reg.vhd
-- -- onehot2encoded.vhd
-- -- or_bits.vhd
-- -- control_register.vhd
-- -- arb2bus_data_mux.vhd
-- -- mux_onehot.vhd
-- -- or_bits.vhd
-- -- watchdog_timer.vhd
-- -- arbitration_logic.vhd
-- -- or_bits.vhd
-- -- park_lock_logic.vhd
-- -- or_bits.vhd
-- -- or_gate.vhd
-- -- or_muxcy.vhd
-------------------------------------------------------------------------------
-- Author: ALS
-- History:
-- ALS 08/28/01 -- Version 1.01a creation to include IPIF v1.22a
-- ALS 10/04/01 -- Version 1.02a creation to include IPIF v1.23a
-- ALS 11/27/01
-- ^^^^^^
-- Version 1.02b created to fix registered grant problem.
-- ~~~~~~
-- ALS 01/26/02
-- ^^^^^^
-- Created version 1.02c to fix problem with registered grants, and buslock when
-- the buslock master is holding request high and performing conversion cycles.
-- ~~~~~~
-- ALS 01/09/03
-- ^^^^^^
-- Created version 1.02d to register OPB_timeout to improve timing
-- Registered Opb_timeout, therefore OPB_XferAck, OPB_Retry, and OPB_toutSup MUST
-- be asserted in 15 clocks instead of 16
-- ~~~~~~
-- bsbrao 09/27/04
-- ^^^^^^
-- Created version 1.02e to upgrade IPIF from opb_ipif_v1_23_a to
-- opb_ipif_v3_01_a
-- ~~~~~~
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.STD_LOGIC_ARITH.all;
--Package file that contains constant definition for RESET_ACTIVE
--and OPB_TIMEOUT_CNT
library opb_v20_v1_10_d;
use opb_v20_v1_10_d.opb_arb_pkg.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- No Generics were used for this Entity
--
-- -- OPB Interface Signals
-- input OPB_select; -- master select
-- input OPB_xferAck; -- slave transfer acknowledge
-- input OPB_retry; -- slave retry
-- input OPB_toutSup; -- slave timeout suppress
-- output OPB_timeout; -- timeout asserted OPB_TIMEOUT_CNT
-- -- clocks after OPB_select asserts
-- -- Clock and Reset
-- input Clk;
-- input Rst;
-------------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity watchdog_timer is
port (
OPB_select : in std_logic;
OPB_xferAck : in std_logic;
OPB_retry : in std_logic;
OPB_toutSup : in std_logic;
OPB_timeout : out std_logic;
Clk : in std_logic;
Rst : in std_logic
);
end watchdog_timer;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of watchdog_timer is
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- Constants used in this design are found in opb_arbiter_pkg.vhd
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal timeout_cnt : unsigned(0 to 3 ); -- output from counter
-----------------------------------------------------------------------------
-- Begin architecture
-----------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- WATCHDOG_TIMER_PROCESS
-------------------------------------------------------------------------------
-- This process counts clocks after OPB_select is asserted while OPB_xferAck
-- and OPB_retry are negated. The assertion of OPB_toutSup suspends the counter.
-------------------------------------------------------------------------------
WATCHDOG_TIMER_PROCESS:process (Clk, Rst, OPB_select, OPB_retry, OPB_xferAck,
OPB_toutSup, timeout_cnt)
begin
if Clk'event and Clk = '1' then
-- active high, synchronous reset
if Rst = RESET_ACTIVE then
timeout_cnt <= (others => '0');
elsif OPB_select = '1' and OPB_retry = '0' and OPB_xferAck = '0' then
-- Enable timeout counter once OPB_select asserts
-- and OPB_retry and OPB_xferAck are negated.
-- Reset counter if either OPB_retry or
-- OPB_xferAck assert while OPB_select
-- is asserted
if OPB_toutSup = '0' then
timeout_cnt <= timeout_cnt + 1;
else
timeout_cnt <= timeout_cnt;
end if;
else
timeout_cnt <= (others => '0');
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- TIMEOUT_PROCESS
-------------------------------------------------------------------------------
-- This process asserts the OPB_timeout signal when the output of the watchdog
-- timer is OPB_TIMEOUTCNT-2 (0-14=15 clocks) and OPB_toutSup is negated.
-- OPB_timeout is registered to improve FPGA implementation timing
-------------------------------------------------------------------------------
TIMEOUT_PROCESS:process (Clk,Rst)
begin -- process
-- Assert OPB_timeout OPB_TIMEOUT_CNT-2 clocks
-- after OPB_select asserts if OPB_toutSup is negated
if Clk'event and Clk = '1' then
if Rst = RESET_ACTIVE then
OPB_Timeout <= '0';
elsif timeout_cnt = OPB_TIMEOUT_CNT -2 and OPB_toutSup = '0' and
OPB_select = '1' and OPB_retry = '0' and OPB_xferAck = '0'then
OPB_timeout <= '1';
else
OPB_timeout <= '0';
end if;
end if;
end process;
end implementation;
|
bsd-3-clause
|
masson2013/heterogeneous_hthreads
|
src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/opb_v20_v1_10_d/hdl/vhdl/proc_common_pkg.vhd
|
3
|
18158
|
-------------------------------------------------------------------------------
-- $Id: proc_common_pkg.vhd,v 1.1.2.1 2009/10/06 21:15:02 gburch Exp $
-------------------------------------------------------------------------------
-- Processor Common Library Package
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: proc_common_pkg.vhd
-- Version: v1.21b
-- Description: This file contains the constants and functions used in the
-- processor common library components.
--
-------------------------------------------------------------------------------
-- Structure:
--
-------------------------------------------------------------------------------
-- Author: ALS
-- History:
-- ALS 09/12/01 -- Created from opb_arb_pkg.vhd
--
-- ALS 09/21/01
-- ^^^^^^
-- Added pwr function. Replaced log2 function with one that works for XST.
-- ~~~~~~
--
-- ALS 12/07/01
-- ^^^^^^
-- Added Addr_bits function.
-- ~~~~~~
-- ALS 01/31/02
-- ^^^^^^
-- Added max2 function.
-- ~~~~~~
-- FLO 02/22/02
-- ^^^^^^
-- Extended input argument range of log2 function to 2^30. Also, added
-- a check that the argument does not exceed this value; a failure
-- assertion violation is generated if it does not.
-- ~~~~~~
-- FLO 08/31/06
-- ^^^^^^
-- Removed type TARGET_FAMILY_TYPE and functions Get_Reg_File_Area and
-- Get_RLOC_Name. These objects are not used. Further, the functions
-- produced misleading warnings (CR419886, CR419898).
-- ~~~~~~
-- FLO 05/25/07
-- ^^^^^^
-- -Reimplemented function pad_power2 to correct error when the input
-- argument is 1. (fixes CR 303469)
-- -Added function clog2(x), which returns the integer ceiling of the
-- base 2 logarithm of x. This function can be used in place of log2
-- when wishing to avoid the XST warning, "VHDL Assertion Statement
-- with non constant condition is ignored".
-- ~~~~~~
--
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- need conversion function to convert reals/integers to std logic vectors
use ieee.std_logic_arith.conv_std_logic_vector;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
package proc_common_pkg is
-------------------------------------------------------------------------------
-- Type Declarations
-------------------------------------------------------------------------------
type CHAR_TO_INT_TYPE is array (character) of integer;
-- type INTEGER_ARRAY_TYPE is array (natural range <>) of integer;
-- Type SLV64_ARRAY_TYPE is array (natural range <>) of std_logic_vector(0 to 63);
-------------------------------------------------------------------------------
-- Function and Procedure Declarations
-------------------------------------------------------------------------------
function max2 (num1, num2 : integer) return integer;
function min2 (num1, num2 : integer) return integer;
function Addr_Bits(x,y : std_logic_vector) return integer;
function clog2(x : positive) return natural;
function pad_power2 ( in_num : integer ) return integer;
function pad_4 ( in_num : integer ) return integer;
function log2(x : natural) return integer;
function pwr(x: integer; y: integer) return integer;
function String_To_Int(S : string) return integer;
function itoa (int : integer) return string;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- the RESET_ACTIVE constant should denote the logic level of an active reset
constant RESET_ACTIVE : std_logic := '1';
-- table containing strings representing hex characters for conversion to
-- integers
constant STRHEX_TO_INT_TABLE : CHAR_TO_INT_TYPE :=
('0' => 0,
'1' => 1,
'2' => 2,
'3' => 3,
'4' => 4,
'5' => 5,
'6' => 6,
'7' => 7,
'8' => 8,
'9' => 9,
'A'|'a' => 10,
'B'|'b' => 11,
'C'|'c' => 12,
'D'|'d' => 13,
'E'|'e' => 14,
'F'|'f' => 15,
others => -1);
end proc_common_pkg;
package body proc_common_pkg is
-------------------------------------------------------------------------------
-- Function Definitions
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Function max2
--
-- This function returns the greater of two numbers.
-------------------------------------------------------------------------------
function max2 (num1, num2 : integer) return integer is
begin
if num1 >= num2 then
return num1;
else
return num2;
end if;
end function max2;
-------------------------------------------------------------------------------
-- Function min2
--
-- This function returns the lesser of two numbers.
-------------------------------------------------------------------------------
function min2 (num1, num2 : integer) return integer is
begin
if num1 <= num2 then
return num1;
else
return num2;
end if;
end function min2;
-------------------------------------------------------------------------------
-- Function Addr_bits
--
-- function to convert an address range (base address and an upper address)
-- into the number of upper address bits needed for decoding a device
-- select signal. will handle slices and big or little endian
-------------------------------------------------------------------------------
function Addr_Bits(x,y : std_logic_vector) return integer is
variable addr_xor : std_logic_vector(x'range);
variable count : integer := 0;
begin
assert x'length = y'length and (x'ascending xnor y'ascending)
report "Addr_Bits: arguments are not the same type"
severity ERROR;
addr_xor := x xor y;
for i in x'range
loop
if addr_xor(i) = '1' then return count;
end if;
count := count + 1;
end loop;
return x'length;
end Addr_Bits;
--------------------------------------------------------------------------------
-- Function clog2 - returns the integer ceiling of the base 2 logarithm of x,
-- i.e., the least integer greater than or equal to log2(x).
--------------------------------------------------------------------------------
function clog2(x : positive) return natural is
variable r : natural := 0;
variable rp : natural := 1; -- rp tracks the value 2**r
begin
while rp < x loop -- Termination condition T: x <= 2**r
-- Loop invariant L: 2**(r-1) < x
r := r + 1;
if rp > integer'high - rp then exit; end if; -- If doubling rp overflows
-- the integer range, the doubled value would exceed x, so safe to exit.
rp := rp + rp;
end loop;
-- L and T <-> 2**(r-1) < x <= 2**r <-> (r-1) < log2(x) <= r
return r; --
end clog2;
-------------------------------------------------------------------------------
-- Function pad_power2
--
-- This function returns the next power of 2 from the input number. If the
-- input number is a power of 2, this function returns the input number.
--
-- This function is used to round up the number of masters to the next power
-- of 2 if the number of masters is not already a power of 2.
--
-- Input argument 0, which is not a power of two, is accepted and returns 0.
-- Input arguments less than 0 are not allowed.
-------------------------------------------------------------------------------
--
function pad_power2 (in_num : integer ) return integer is
begin
if in_num = 0 then
return 0;
else
return 2**(clog2(in_num));
end if;
end pad_power2;
-------------------------------------------------------------------------------
-- Function pad_4
--
-- This function returns the next multiple of 4 from the input number. If the
-- input number is a multiple of 4, this function returns the input number.
--
-------------------------------------------------------------------------------
--
function pad_4 (in_num : integer ) return integer is
variable out_num : integer;
begin
out_num := (((in_num-1)/4) + 1)*4;
return out_num;
end pad_4;
-------------------------------------------------------------------------------
-- Function log2 -- returns number of bits needed to encode x choices
-- x = 0 returns 0
-- x = 1 returns 0
-- x = 2 returns 1
-- x = 4 returns 2, etc.
-------------------------------------------------------------------------------
--
function log2(x : natural) return integer is
variable i : integer := 0;
variable val: integer := 1;
begin
if x = 0 then return 0;
else
for j in 0 to 29 loop -- for loop for XST
if val >= x then null;
else
i := i+1;
val := val*2;
end if;
end loop;
assert val >= x
report "Function log2 received argument larger" &
" than its capability of 2^30. "
severity failure;
return i;
end if;
end function log2;
-------------------------------------------------------------------------------
-- Function pwr -- x**y
-- negative numbers not allowed for y
-------------------------------------------------------------------------------
function pwr(x: integer; y: integer) return integer is
variable z : integer := 1;
begin
if y = 0 then return 1;
else
for i in 1 to y loop
z := z * x;
end loop;
return z;
end if;
end function pwr;
-------------------------------------------------------------------------------
-- Function itoa
--
-- The itoa function converts an integer to a text string.
-- This function is required since `image doesn't work in Synplicity
-- Valid input range is -9999 to 9999
-------------------------------------------------------------------------------
--
function itoa (int : integer) return string is
type table is array (0 to 9) of string (1 to 1);
constant LUT : table :=
("0", "1", "2", "3", "4", "5", "6", "7", "8", "9");
variable str1 : string(1 to 1);
variable str2 : string(1 to 2);
variable str3 : string(1 to 3);
variable str4 : string(1 to 4);
variable str5 : string(1 to 5);
variable abs_int : natural;
variable thousands_place : natural;
variable hundreds_place : natural;
variable tens_place : natural;
variable ones_place : natural;
variable sign : integer;
begin
abs_int := abs(int);
if abs_int > int then sign := -1;
else sign := 1;
end if;
thousands_place := abs_int/1000;
hundreds_place := (abs_int-thousands_place*1000)/100;
tens_place := (abs_int-thousands_place*1000-hundreds_place*100)/10;
ones_place :=
(abs_int-thousands_place*1000-hundreds_place*100-tens_place*10);
if sign>0 then
if thousands_place>0 then
str4 := LUT(thousands_place) & LUT(hundreds_place) & LUT(tens_place) &
LUT(ones_place);
return str4;
elsif hundreds_place>0 then
str3 := LUT(hundreds_place) & LUT(tens_place) & LUT(ones_place);
return str3;
elsif tens_place>0 then
str2 := LUT(tens_place) & LUT(ones_place);
return str2;
else
str1 := LUT(ones_place);
return str1;
end if;
else
if thousands_place>0 then
str5 := "-" & LUT(thousands_place) & LUT(hundreds_place) &
LUT(tens_place) & LUT(ones_place);
return str5;
elsif hundreds_place>0 then
str4 := "-" & LUT(hundreds_place) & LUT(tens_place) & LUT(ones_place);
return str4;
elsif tens_place>0 then
str3 := "-" & LUT(tens_place) & LUT(ones_place);
return str3;
else
str2 := "-" & LUT(ones_place);
return str2;
end if;
end if;
end itoa;
-----------------------------------------------------------------------------
-- Function String_To_Int
--
-- Converts a string of hex character to an integer
-- accept negative numbers
-----------------------------------------------------------------------------
function String_To_Int(S : String) return Integer is
variable Result : integer := 0;
variable Temp : integer := S'Left;
variable Negative : integer := 1;
begin
for I in S'Left to S'Right loop
-- ASCII value - 42 TBD
if (S(I) = '-') then
Temp := 0;
Negative := -1;
else
Temp := STRHEX_TO_INT_TABLE(S(I));
if (Temp = -1) then
assert false
report "Wrong value in String_To_Int conversion " & S(I)
severity error;
end if;
end if;
Result := Result * 16 + Temp;
end loop;
return (Negative * Result);
end String_To_Int;
end package body proc_common_pkg;
|
bsd-3-clause
|
masson2013/heterogeneous_hthreads
|
src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/opb_v20_v1_10_d/hdl/vhdl/direct_path_cntr_ai.vhd
|
3
|
11437
|
--ENTITY_TAG
-------------------------------------------------------------------------------
-- $Id: direct_path_cntr_ai.vhd,v 1.1.2.1 2009/10/06 21:15:00 gburch Exp $
-------------------------------------------------------------------------------
-- direct_path_cntr_ai.vhd - entity/arch
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: direct_path_cntr_ai.vhd
--
-- Description: Direct-path counter with arbitrary increment.
--
-- This is an up counter with a combinatorial direct pass-
-- through mode. The passed-through value also serves as
-- the initial "loaded" value when the counter switches to
-- count mode. In pass-though mode, Dout <= Din.
--
-- The mode is controlled by two signals, Load_n and Cnt_en.
-- The counter is in direct pass-through mode any time Load_n
-- is true (low) and up to the first cycle where Cnt_en is
-- true after Load_n goes false. When Load_n = '1' (load
-- disabled) Dout increments by Delta each time Cnt_en is
-- true at the positive edge of Clk.
--
-- The implementation has a one-LUT delay from Din to Dout
-- (via the XORCY) in direct pass-through mode and the same
-- delay plus carry-chain propogation in count mode. There
-- is an additional LUT delay (added to the Din to Dout
-- delay) from the Load_n input or from the clock edge that
-- puts the counter into count mode.
-------------------------------------------------------------------------------
-- Structure: direct_path_cntr_ai.vhd
-------------------------------------------------------------------------------
-- Author: FLO
-- History:
-- FLO 12/02/2003 -- First version derived from
-- direct_path_cntr.vhd
--
--
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity direct_path_cntr_ai is
generic (
C_WIDTH : natural := 8
);
port (
Clk : in std_logic;
Din : in std_logic_vector(0 to C_WIDTH-1);
Dout : out std_logic_vector(0 to C_WIDTH-1);
Load_n : in std_logic;
Cnt_en : in std_logic;
Delta : in std_logic_vector(0 to C_WIDTH-1)
);
end direct_path_cntr_ai;
library unisim;
use unisim.vcomponents.all;
architecture imp of direct_path_cntr_ai is
signal q_i,
lut_out,
q_i_ns : std_logic_vector(0 to C_WIDTH-1);
signal cry : std_logic_vector(0 to C_WIDTH);
signal sel_cntr : std_logic;
signal sel_cntr_and_Load_n : std_logic; -- AND of sel_cntr and Load_n
signal mdelta : std_logic_vector(0 to Delta'length-1); -- "My delta"
-- Delta, adjusted to assure ascending range referenced from zero.
begin
mdelta <= Delta;
----------------------------------------------------------------------------
-- Load_n takes effect combinatorially, causing Dout to be directly driven
-- from Din when Load_n is asserted. When Load_n is not asserted, then the
-- first clocking of asserted Cnt_en switches modes so that Dout is driven
-- by the register value plus one. The value of Dout is clocked into the
-- register with each Cnt_en, thus realizing the counting behavior.
-- The combinatorial override of Load_n takes place in the LUT and covers
-- the cycle that it takes for the mode to recover (since the mode FF has a
-- synchronous reset). Use of an asynchronous reset is rejected as an
-- option to avoid the requirement that Load_n be generated glitch free.
----------------------------------------------------------------------------
I_MODE_SELECTION : process(Clk)
begin
if Clk'event and Clk='1' then
if Load_n = '0' then
sel_cntr <= '0';
elsif Cnt_en = '1' then
sel_cntr <= '1';
end if;
end if;
end process;
sel_cntr_and_Load_n <= sel_cntr and Load_n;
Dout <= q_i_ns;
cry(C_WIDTH) <= '0';
PERBIT_GEN: for j in C_WIDTH-1 downto 0 generate
begin
------------------------------------------------------------------------
-- LUT output generation and MUXCY carry handling.
------------------------------------------------------------------------
DELTA_LUT_GEN: if j >= C_WIDTH-mdelta'length generate
signal gen_cry: std_logic;
begin
lut_out(j) <= q_i(j) xor mdelta(mdelta'length + j - C_WIDTH)
when (sel_cntr_and_Load_n)='1'
else
Din(j);
I_MULT_AND : MULT_AND
port map (
LO => gen_cry,
I1 => sel_cntr_and_Load_n,
I0 => q_i(j)
);
MUXCY_i1: MUXCY
port map (
DI => gen_cry,
CI => cry(j+1),
S => lut_out(j),
O => cry(j)
);
end generate;
--
--
NON_DELTA_LUT_GEN : if j < C_WIDTH-mdelta'length generate
begin
lut_out(j) <= q_i(j) when (sel_cntr_and_Load_n)='1' else Din(j);
MUXCY_i1: MUXCY
port map (
DI => '0',
CI => cry(j+1),
S => lut_out(j),
O => cry(j)
);
end generate;
------------------------------------------------------------------------
-- Apply the effect of carry in.
------------------------------------------------------------------------
XORCY_i1: XORCY
port map (
LI => lut_out(j),
CI => cry(j+1),
O => q_i_ns(j)
);
FDE_i1: FDE
port map (
Q => q_i(j),
C => Clk,
CE => Cnt_en,
D => q_i_ns(j)
);
end generate;
end imp;
|
bsd-3-clause
|
masson2013/heterogeneous_hthreads
|
src/hardware/MyRepository/pcores/hw_threads/hw_acc_v1_00_a/hdl/vhdl/user_logics/functional/join_5.vhd
|
2
|
16797
|
---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
FUNCTION_EXIT,
STATE_1,
STATE_2,
STATE_3,
STATE_4,
STATE_5,
STATE_6,
STATE_7,
STATE_8,
STATE_9,
STATE_10,
STATE_11,
STATE_12,
STATE_13,
STATE_14,
STATE_15,
STATE_16,
STATE_17,
STATE_18,
STATE_19,
STATE_20,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_STATE_1 : std_logic_vector(0 to 15) := x"0101";
constant U_STATE_2 : std_logic_vector(0 to 15) := x"0102";
constant U_STATE_3 : std_logic_vector(0 to 15) := x"0103";
constant U_STATE_4 : std_logic_vector(0 to 15) := x"0104";
constant U_STATE_5 : std_logic_vector(0 to 15) := x"0105";
constant U_STATE_6 : std_logic_vector(0 to 15) := x"0106";
constant U_STATE_7 : std_logic_vector(0 to 15) := x"0107";
constant U_STATE_8 : std_logic_vector(0 to 15) := x"0108";
constant U_STATE_9 : std_logic_vector(0 to 15) := x"0109";
constant U_STATE_10 : std_logic_vector(0 to 15) := x"0110";
constant U_STATE_11 : std_logic_vector(0 to 15) := x"0111";
constant U_STATE_12 : std_logic_vector(0 to 15) := x"0112";
constant U_STATE_13 : std_logic_vector(0 to 15) := x"0113";
constant U_STATE_14 : std_logic_vector(0 to 15) := x"0114";
constant U_STATE_15 : std_logic_vector(0 to 15) := x"0115";
constant U_STATE_16 : std_logic_vector(0 to 15) := x"0116";
constant U_STATE_17 : std_logic_vector(0 to 15) := x"0117";
constant U_STATE_18 : std_logic_vector(0 to 15) := x"0118";
constant U_STATE_19 : std_logic_vector(0 to 15) := x"0119";
constant U_STATE_20 : std_logic_vector(0 to 15) := x"0120";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
signal retVal, retVal_next : std_logic_vector(0 to 31);
signal arg, arg_next : std_logic_vector(0 to 31);
signal reg1, reg1_next : std_logic_vector(0 to 31);
signal reg2, reg2_next : std_logic_vector(0 to 31);
signal reg3, reg3_next : std_logic_vector(0 to 31);
signal reg4, reg4_next : std_logic_vector(0 to 31);
signal reg5, reg5_next : std_logic_vector(0 to 31);
signal reg6, reg6_next : std_logic_vector(0 to 31);
signal reg7, reg7_next : std_logic_vector(0 to 31);
signal reg8, reg8_next : std_logic_vector(0 to 31);
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock, intrfc2thrd_goWait) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
return_state <= return_state_next;
retVal <= retVal_next;
arg <= arg_next;
reg1 <= reg1_next;
reg2 <= reg2_next;
reg3 <= reg3_next;
reg4 <= reg4_next;
reg5 <= reg5_next;
reg6 <= reg6_next;
reg7 <= reg7_next;
reg8 <= reg8_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_STATE_1 =>
current_state <= STATE_1;
when U_STATE_2 =>
current_state <= STATE_2;
when U_STATE_3 =>
current_state <= STATE_3;
when U_STATE_4 =>
current_state <= STATE_4;
when U_STATE_5 =>
current_state <= STATE_5;
when U_STATE_6 =>
current_state <= STATE_6;
when U_STATE_7 =>
current_state <= STATE_7;
when U_STATE_8 =>
current_state <= STATE_8;
when U_STATE_9 =>
current_state <= STATE_9;
when U_STATE_10 =>
current_state <= STATE_10;
when U_STATE_11 =>
current_state <= STATE_11;
when U_STATE_12 =>
current_state <= STATE_12;
when U_STATE_13 =>
current_state <= STATE_13;
when U_STATE_14 =>
current_state <= STATE_14;
when U_STATE_15 =>
current_state <= STATE_15;
when U_STATE_16 =>
current_state <= STATE_16;
when U_STATE_17 =>
current_state <= STATE_17;
when U_STATE_18 =>
current_state <= STATE_18;
when U_STATE_19 =>
current_state <= STATE_19;
when U_STATE_20 =>
current_state <= STATE_20;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
retVal_next <= retVal;
arg_next <= arg;
reg1_next <= reg1;
reg2_next <= reg2;
reg3_next <= reg3;
reg4_next <= reg4;
reg5_next <= reg5;
reg6_next <= reg6;
reg7_next <= reg7;
reg8_next <= reg8;
-----------------------------------------------------------------------
-- Testcase: join_5.c
-- RETURN_VALUE 31
-- reg6 = * function
-- reg7 = thread
-----------------------------------------------------------------------
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
-- struct test_data * data = (struct test_data *) arg;
when FUNCTION_START =>
-- Pop the argument
thrd2intrfc_value <= Z32;
thrd2intrfc_opcode <= OPCODE_POP;
next_state <= WAIT_STATE;
return_state_next <= STATE_1;
when STATE_1 =>
arg_next <= intrfc2thrd_value;
-- Read the address of function
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= intrfc2thrd_value;
next_state <= WAIT_STATE;
return_state_next <= STATE_2;
when STATE_2 =>
reg6_next <= intrfc2thrd_value;
next_state <= STATE_3;
-- hthread_create( &data->thread, NULL, data->function, NULL );
when STATE_3 =>
-- push NULL
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= Z32;
next_state <= WAIT_STATE;
return_state_next <= STATE_4;
when STATE_4 =>
-- push data->function
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg6;
next_state <= WAIT_STATE;
return_state_next <= STATE_5;
when STATE_5 =>
-- push NULL
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= Z32;
next_state <= WAIT_STATE;
return_state_next <= STATE_6;
when STATE_6 =>
-- push &data->thread
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg + x"00000004";
next_state <= WAIT_STATE;
return_state_next <= STATE_7;
when STATE_7 =>
-- call hthread_create
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_CREATE;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_8;
next_state <= WAIT_STATE;
-- retVal = hthread_join( data->thread, NULL );
when STATE_8 =>
-- Load the value of data->thread
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + x"00000004";
next_state <= WAIT_STATE;
return_state_next <= STATE_9;
when STATE_9 =>
reg7_next <= intrfc2thrd_value;
-- push NULL
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= Z32;
next_state <= WAIT_STATE;
return_state_next <= STATE_10;
when STATE_10 =>
-- push data->thread
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg7;
next_state <= WAIT_STATE;
return_state_next <= STATE_11;
when STATE_11 =>
-- call hthread_join
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_JOIN;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_12;
next_state <= WAIT_STATE;
when STATE_12 =>
retVal_next <= intrfc2thrd_value;
next_state <= FUNCTION_EXIT;
when FUNCTION_EXIT =>
--Same as hthread_exit( (void *) retVal );
thrd2intrfc_value <= retVal;
thrd2intrfc_opcode <= OPCODE_RETURN;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
|
bsd-3-clause
|
arteymix/lmc
|
lmc.vhd
|
1
|
5195
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity lmc is
port(
clk: in std_logic;
rst: in std_logic;
input: in signed(11 downto 0);
output: out signed(11 downto 0) := x"000";
input_warn: out std_logic;
output_warn: out std_logic;
halt_warn: out std_logic
);
end entity;
architecture lmc of lmc is
subtype word_t is std_logic_vector(11 downto 0);
subtype instruction_t is std_logic_vector(3 downto 0);
type memory_t is array(255 downto 0) of word_t;
constant HLT: instruction_t := x"0"; -- halt (coffee break)
constant ADD: instruction_t := x"1"; -- add
constant SUB: instruction_t := x"2";
constant STA: instruction_t := x"3";
constant NOP: instruction_t := x"4";
constant LDA: instruction_t := x"5";
constant BRA: instruction_t := x"6";
constant BRZ: instruction_t := x"7";
constant BRP: instruction_t := x"8";
constant IO: instruction_t := x"9"; -- 901 in, 902 out
signal memory: memory_t := (
0 => x"901",
1 => x"1FF",
2 => x"902",
3 => x"901",
4 => x"2FF",
5 => x"902",
6 => x"901",
7 => x"3F0",
8 => x"901",
9 => x"400",
10 => x"5F0",
11 => x"902",
12 => x"901",
13 => x"70C",
14 => x"5FE",
15 => x"902",
16 => x"901",
17 => x"810",
18 => x"5FD",
19 => x"902",
20 => x"600",
-- data
253 => x"00A", -- fd
254 => x"00B", -- fe
255 => x"005", -- ff
others => x"000"
);
signal ordinal_counter: unsigned(7 downto 0) := x"00";
signal accumulator: signed(11 downto 0) := x"000";
signal instruction_register: word_t := memory(to_integer(ordinal_counter));
signal instruction: instruction_t := instruction_register(11 downto 8);
signal address: unsigned(7 downto 0) := unsigned(instruction_register(7 downto 0));
begin
instruction_register <= memory(to_integer(ordinal_counter));
instruction <= instruction_register(11 downto 8);
address <= unsigned(instruction_register(7 downto 0));
-- output combinatory
input_warn <= '1' when instruction = IO and address = x"01" else '0';
output_warn <= '1' when instruction = IO and address = x"02" else '0';
halt_warn <= '1' when instruction = HLT else '0';
output <= accumulator when instruction = IO and address = x"02" else x"000";
process (clk, rst) is
begin
if rst = '0' then -- le reset est inversé avec KEY1
ordinal_counter <= x"00";
accumulator <= x"000";
elsif falling_edge(clk) then -- l'horloge est inversé avec KEY0
case instruction is
when HLT => -- terminate the program (counter will not increase)
report "Program halted." severity NOTE;
when ADD =>
accumulator <= accumulator + signed(memory(to_integer(address)));
ordinal_counter <= ordinal_counter + 1;
when SUB =>
accumulator <= accumulator - signed(memory(to_integer(address)));
ordinal_counter <= ordinal_counter + 1;
when LDA =>
accumulator <= signed(memory(to_integer(address)));
ordinal_counter <= ordinal_counter + 1;
when NOP =>
ordinal_counter <= ordinal_counter + 1;
when STA =>
memory(to_integer(address)) <= std_logic_vector(accumulator);
ordinal_counter <= ordinal_counter + 1;
when BRA =>
ordinal_counter <= address;
when BRZ =>
if accumulator = 0 then
ordinal_counter <= address;
else
ordinal_counter <= ordinal_counter + 1;
end if;
when BRP =>
if accumulator >= 0 then
ordinal_counter <= address;
else
ordinal_counter <= ordinal_counter + 1;
end if;
when IO =>
case address is
when x"01" => -- 901
accumulator <= input;
when x"02" => -- 902
null; -- gérée dans la combinatoire de l'output
when others =>
assert FALSE report "Illegal i/o instruction." severity ERROR;
end case;
ordinal_counter <= ordinal_counter + 1;
when others =>
assert FALSE report "Illegal instruction." severity ERROR;
end case;
end if;
end process;
end architecture;
|
bsd-3-clause
|
natsutan/NPU
|
fpga_implement/npu8/npu8.srcs/sources_1/ip/mult_17x16/hdl/xbip_bram18k_v3_0_vh_rfs.vhd
|
12
|
103154
|
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`protect end_protected
|
bsd-3-clause
|
natsutan/NPU
|
fpga_implement/npu8/npu8.cache/ip/6d1e8401c16773dd/mul_16_32_sim_netlist.vhdl
|
1
|
1137957
| null |
bsd-3-clause
|
drhodes/jade2hdl
|
test-data/vhdl-examples/and.vhdl
|
1
|
341
|
library ieee;
use ieee.std_logic_1164.all;
entity example_and is
port (
input_1 : in std_logic;
input_2 : in std_logic;
and_result : out std_logic
);
end example_and;
architecture rtl of example_and is
signal and_gate : std_logic;
begin
and_gate <= input_1 and input_2;
and_result <= and_gate;
end rtl;
|
bsd-3-clause
|
JorisBolsens/PYNQ
|
Pynq-Z1/vivado/ip/rgb2dvi_v1_2/src/OutputSERDES.vhd
|
11
|
8366
|
-------------------------------------------------------------------------------
--
-- File: OutputSERDES.vhd
-- Author: Elod Gyorgy, Mihaita Nagy
-- Original Project: HDMI output on 7-series Xilinx FPGA
-- Date: 28 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module instantiates the Xilinx 7-series primitives necessary for
-- serializing the TMDS data stream.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity OutputSERDES is
Generic (
kParallelWidth : natural := 10); -- number of parallel bits
Port (
PixelClk : in STD_LOGIC; --TMDS clock x1 (CLKDIV)
SerialClk : in STD_LOGIC; --TMDS clock x5 (CLK)
--Encoded serial data
sDataOut_p : out STD_LOGIC;
sDataOut_n : out STD_LOGIC;
--Encoded parallel data (raw)
pDataOut : in STD_LOGIC_VECTOR (kParallelWidth-1 downto 0);
aRst : in STD_LOGIC);
end OutputSERDES;
architecture Behavioral of OutputSERDES is
signal sDataOut, ocascade1, ocascade2 : std_logic;
signal pDataOut_q : std_logic_vector(13 downto 0);
begin
-- Differential output buffer for TMDS I/O standard
OutputBuffer: OBUFDS
generic map (
IOSTANDARD => "TMDS_33")
port map (
O => sDataOut_p,
OB => sDataOut_n,
I => sDataOut);
-- Serializer, 10:1 (5:1 DDR), master-slave cascaded
SerializerMaster: OSERDESE2
generic map (
DATA_RATE_OQ => "DDR",
DATA_RATE_TQ => "SDR",
DATA_WIDTH => kParallelWidth,
TRISTATE_WIDTH => 1,
TBYTE_CTL => "FALSE",
TBYTE_SRC => "FALSE",
SERDES_MODE => "MASTER")
port map (
OFB => open, -- 1-bit output: Feedback path for data
OQ => sDataOut, -- 1-bit output: Data path output
-- SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)
SHIFTOUT1 => open,
SHIFTOUT2 => open,
TBYTEOUT => open, -- 1-bit output: Byte group tristate
TFB => open, -- 1-bit output: 3-state control
TQ => open, -- 1-bit output: 3-state control
CLK => SerialClk, -- 1-bit input: High speed clock
CLKDIV => PixelClk, -- 1-bit input: Divided clock
-- D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each)
D1 => pDataOut_q(13),
D2 => pDataOut_q(12),
D3 => pDataOut_q(11),
D4 => pDataOut_q(10),
D5 => pDataOut_q(9),
D6 => pDataOut_q(8),
D7 => pDataOut_q(7),
D8 => pDataOut_q(6),
OCE => '1', -- 1-bit input: Output data clock enable
RST => aRst, -- 1-bit input: Reset
-- SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)
SHIFTIN1 => ocascade1,
SHIFTIN2 => ocascade2,
-- T1 - T4: 1-bit (each) input: Parallel 3-state inputs
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TBYTEIN => '0', -- 1-bit input: Byte group tristate
TCE => '0' -- 1-bit input: 3-state clock enable
);
SerializerSlave: OSERDESE2
generic map (
DATA_RATE_OQ => "DDR",
DATA_RATE_TQ => "SDR",
DATA_WIDTH => kParallelWidth,
TRISTATE_WIDTH => 1,
TBYTE_CTL => "FALSE",
TBYTE_SRC => "FALSE",
SERDES_MODE => "SLAVE")
port map (
OFB => open, -- 1-bit output: Feedback path for data
OQ => open, -- 1-bit output: Data path output
-- SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)
SHIFTOUT1 => ocascade1,
SHIFTOUT2 => ocascade2,
TBYTEOUT => open, -- 1-bit output: Byte group tristate
TFB => open, -- 1-bit output: 3-state control
TQ => open, -- 1-bit output: 3-state control
CLK => SerialClk, -- 1-bit input: High speed clock
CLKDIV => PixelClk, -- 1-bit input: Divided clock
-- D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each)
D1 => '0',
D2 => '0',
D3 => pDataOut_q(5),
D4 => pDataOut_q(4),
D5 => pDataOut_q(3),
D6 => pDataOut_q(2),
D7 => pDataOut_q(1),
D8 => pDataOut_q(0),
OCE => '1', -- 1-bit input: Output data clock enable
RST => aRst, -- 1-bit input: Reset
-- SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)
SHIFTIN1 => '0',
SHIFTIN2 => '0',
-- T1 - T4: 1-bit (each) input: Parallel 3-state inputs
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TBYTEIN => '0', -- 1-bit input: Byte group tristate
TCE => '0' -- 1-bit input: 3-state clock enable
);
-------------------------------------------------------------
-- Concatenate the serdes inputs together. Keep the timesliced
-- bits together, and placing the earliest bits on the right
-- ie, if data comes in 0, 1, 2, 3, 4, 5, 6, 7, ...
-- the output will be 3210, 7654, ...
-------------------------------------------------------------
SliceOSERDES_q: for slice_count in 0 to kParallelWidth-1 generate begin
--DVI sends least significant bit first
--OSERDESE2 sends D1 bit first
pDataOut_q(14-slice_count-1) <= pDataOut(slice_count);
end generate SliceOSERDES_q;
end Behavioral;
|
bsd-3-clause
|
natsutan/NPU
|
fpga_implement/npu8/npu8.ip_user_files/ip/mul8_8/mul8_8_stub.vhdl
|
2
|
1335
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (lin64) Build 1733598 Wed Dec 14 22:35:42 MST 2016
-- Date : Sat Jan 21 17:57:15 2017
-- Host : natu-OMEN-by-HP-Laptop running 64-bit Ubuntu 16.04.1 LTS
-- Command : write_vhdl -force -mode synth_stub
-- /media/natu/data/proj/myproj/NPU/fpga_implement/npu8/npu8.srcs/sources_1/ip/mul8_8/mul8_8_stub.vhdl
-- Design : mul8_8
-- Purpose : Stub declaration of top-level module interface
-- Device : xcku035-fbva676-3-e
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mul8_8 is
Port (
CLK : in STD_LOGIC;
A : in STD_LOGIC_VECTOR ( 7 downto 0 );
B : in STD_LOGIC_VECTOR ( 7 downto 0 );
P : out STD_LOGIC_VECTOR ( 15 downto 0 )
);
end mul8_8;
architecture stub of mul8_8 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "CLK,A[7:0],B[7:0],P[15:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "mult_gen_v12_0_12,Vivado 2016.4";
begin
end;
|
bsd-3-clause
|
natsutan/NPU
|
fpga_implement/npu8/npu8.ip_user_files/ip/mul16_16/mul16_16_stub.vhdl
|
2
|
1351
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (lin64) Build 1733598 Wed Dec 14 22:35:42 MST 2016
-- Date : Sat Jan 21 17:58:33 2017
-- Host : natu-OMEN-by-HP-Laptop running 64-bit Ubuntu 16.04.1 LTS
-- Command : write_vhdl -force -mode synth_stub
-- /media/natu/data/proj/myproj/NPU/fpga_implement/npu8/npu8.srcs/sources_1/ip/mul16_16/mul16_16_stub.vhdl
-- Design : mul16_16
-- Purpose : Stub declaration of top-level module interface
-- Device : xcku035-fbva676-3-e
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mul16_16 is
Port (
CLK : in STD_LOGIC;
A : in STD_LOGIC_VECTOR ( 15 downto 0 );
B : in STD_LOGIC_VECTOR ( 15 downto 0 );
P : out STD_LOGIC_VECTOR ( 15 downto 0 )
);
end mul16_16;
architecture stub of mul16_16 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "CLK,A[15:0],B[15:0],P[15:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "mult_gen_v12_0_12,Vivado 2016.4";
begin
end;
|
bsd-3-clause
|
JorisBolsens/PYNQ
|
Pynq-Z1/vivado/ip/dvi2rgb_v1_6/src/GlitchFilter.vhd
|
15
|
3919
|
-------------------------------------------------------------------------------
--
-- File: GlitchFilter.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 22 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module filters any pulses on sIn lasting less than the number of
-- periods specified in kNoOfPeriodsToFilter. The output sOut will be
-- delayed by kNoOfPeriodsToFilter cycles, but glitch-free.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity GlitchFilter is
Generic (
kNoOfPeriodsToFilter : natural);
Port (
SampleClk : in STD_LOGIC;
sIn : in STD_LOGIC;
sOut : out STD_LOGIC;
sRst : in STD_LOGIC);
end GlitchFilter;
architecture Behavioral of GlitchFilter is
signal cntPeriods : natural range 0 to kNoOfPeriodsToFilter - 1 := kNoOfPeriodsToFilter - 1;
signal sIn_q : std_logic;
begin
Bypass: if kNoOfPeriodsToFilter = 0 generate
sOut <= sIn;
end generate Bypass;
Filter: if kNoOfPeriodsToFilter > 0 generate
process (SampleClk)
begin
if Rising_Edge(SampleClk) then
sIn_q <= sIn;
if (cntPeriods = 0) then
sOut <= sIn_q;
end if;
end if;
end process;
PeriodCounter: process (SampleClk)
begin
if Rising_Edge(SampleClk) then
if (sIn_q /= sIn or sRst = '1') then --edge detected
cntPeriods <= kNoOfPeriodsToFilter - 1; --reset counter
elsif (cntPeriods /= 0) then
cntPeriods <= cntPeriods - 1; --count down
end if;
end if;
end process PeriodCounter;
end generate Filter;
end Behavioral;
|
bsd-3-clause
|
natsutan/NPU
|
fpga_implement/npu8/npu8.cache/ip/3401eab6b7fd8ff8/mul8_16_sim_netlist.vhdl
|
1
|
294820
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (lin64) Build 1733598 Wed Dec 14 22:35:42 MST 2016
-- Date : Sat Jan 21 14:28:14 2017
-- Host : natu-OMEN-by-HP-Laptop running 64-bit Ubuntu 16.04.1 LTS
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ mul8_16_sim_netlist.vhdl
-- Design : mul8_16
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xcku035-fbva676-3-e
-- --------------------------------------------------------------------------------
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`protect end_protected
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 is
port (
CLK : in STD_LOGIC;
A : in STD_LOGIC_VECTOR ( 7 downto 0 );
B : in STD_LOGIC_VECTOR ( 15 downto 0 );
CE : in STD_LOGIC;
SCLR : in STD_LOGIC;
ZERO_DETECT : out STD_LOGIC_VECTOR ( 1 downto 0 );
P : out STD_LOGIC_VECTOR ( 15 downto 0 );
PCASC : out STD_LOGIC_VECTOR ( 47 downto 0 )
);
attribute C_A_TYPE : integer;
attribute C_A_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 1;
attribute C_A_WIDTH : integer;
attribute C_A_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 8;
attribute C_B_TYPE : integer;
attribute C_B_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 0;
attribute C_B_VALUE : string;
attribute C_B_VALUE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is "10000001";
attribute C_B_WIDTH : integer;
attribute C_B_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 16;
attribute C_CCM_IMP : integer;
attribute C_CCM_IMP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 0;
attribute C_CE_OVERRIDES_SCLR : integer;
attribute C_CE_OVERRIDES_SCLR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 0;
attribute C_HAS_CE : integer;
attribute C_HAS_CE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 0;
attribute C_HAS_SCLR : integer;
attribute C_HAS_SCLR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 0;
attribute C_HAS_ZERO_DETECT : integer;
attribute C_HAS_ZERO_DETECT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 0;
attribute C_LATENCY : integer;
attribute C_LATENCY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 3;
attribute C_MODEL_TYPE : integer;
attribute C_MODEL_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 0;
attribute C_MULT_TYPE : integer;
attribute C_MULT_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 0;
attribute C_OPTIMIZE_GOAL : integer;
attribute C_OPTIMIZE_GOAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 1;
attribute C_OUT_HIGH : integer;
attribute C_OUT_HIGH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 23;
attribute C_OUT_LOW : integer;
attribute C_OUT_LOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 8;
attribute C_ROUND_OUTPUT : integer;
attribute C_ROUND_OUTPUT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 0;
attribute C_ROUND_PT : integer;
attribute C_ROUND_PT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 0;
attribute C_VERBOSITY : integer;
attribute C_VERBOSITY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is 0;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is "kintexu";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 : entity is "yes";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 is
signal \<const0>\ : STD_LOGIC;
signal NLW_i_mult_PCASC_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_i_mult_ZERO_DETECT_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_A_TYPE of i_mult : label is 1;
attribute C_A_WIDTH of i_mult : label is 8;
attribute C_B_TYPE of i_mult : label is 0;
attribute C_B_VALUE of i_mult : label is "10000001";
attribute C_B_WIDTH of i_mult : label is 16;
attribute C_CCM_IMP of i_mult : label is 0;
attribute C_CE_OVERRIDES_SCLR of i_mult : label is 0;
attribute C_HAS_CE of i_mult : label is 0;
attribute C_HAS_SCLR of i_mult : label is 0;
attribute C_HAS_ZERO_DETECT of i_mult : label is 0;
attribute C_LATENCY of i_mult : label is 3;
attribute C_MODEL_TYPE of i_mult : label is 0;
attribute C_MULT_TYPE of i_mult : label is 0;
attribute C_OUT_HIGH of i_mult : label is 23;
attribute C_OUT_LOW of i_mult : label is 8;
attribute C_ROUND_OUTPUT of i_mult : label is 0;
attribute C_ROUND_PT of i_mult : label is 0;
attribute C_VERBOSITY of i_mult : label is 0;
attribute C_XDEVICEFAMILY of i_mult : label is "kintexu";
attribute c_optimize_goal of i_mult : label is 1;
attribute downgradeipidentifiedwarnings of i_mult : label is "yes";
begin
PCASC(47) <= \<const0>\;
PCASC(46) <= \<const0>\;
PCASC(45) <= \<const0>\;
PCASC(44) <= \<const0>\;
PCASC(43) <= \<const0>\;
PCASC(42) <= \<const0>\;
PCASC(41) <= \<const0>\;
PCASC(40) <= \<const0>\;
PCASC(39) <= \<const0>\;
PCASC(38) <= \<const0>\;
PCASC(37) <= \<const0>\;
PCASC(36) <= \<const0>\;
PCASC(35) <= \<const0>\;
PCASC(34) <= \<const0>\;
PCASC(33) <= \<const0>\;
PCASC(32) <= \<const0>\;
PCASC(31) <= \<const0>\;
PCASC(30) <= \<const0>\;
PCASC(29) <= \<const0>\;
PCASC(28) <= \<const0>\;
PCASC(27) <= \<const0>\;
PCASC(26) <= \<const0>\;
PCASC(25) <= \<const0>\;
PCASC(24) <= \<const0>\;
PCASC(23) <= \<const0>\;
PCASC(22) <= \<const0>\;
PCASC(21) <= \<const0>\;
PCASC(20) <= \<const0>\;
PCASC(19) <= \<const0>\;
PCASC(18) <= \<const0>\;
PCASC(17) <= \<const0>\;
PCASC(16) <= \<const0>\;
PCASC(15) <= \<const0>\;
PCASC(14) <= \<const0>\;
PCASC(13) <= \<const0>\;
PCASC(12) <= \<const0>\;
PCASC(11) <= \<const0>\;
PCASC(10) <= \<const0>\;
PCASC(9) <= \<const0>\;
PCASC(8) <= \<const0>\;
PCASC(7) <= \<const0>\;
PCASC(6) <= \<const0>\;
PCASC(5) <= \<const0>\;
PCASC(4) <= \<const0>\;
PCASC(3) <= \<const0>\;
PCASC(2) <= \<const0>\;
PCASC(1) <= \<const0>\;
PCASC(0) <= \<const0>\;
ZERO_DETECT(1) <= \<const0>\;
ZERO_DETECT(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
i_mult: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12_viv
port map (
A(7 downto 0) => A(7 downto 0),
B(15 downto 0) => B(15 downto 0),
CE => '0',
CLK => CLK,
P(15 downto 0) => P(15 downto 0),
PCASC(47 downto 0) => NLW_i_mult_PCASC_UNCONNECTED(47 downto 0),
SCLR => '0',
ZERO_DETECT(1 downto 0) => NLW_i_mult_ZERO_DETECT_UNCONNECTED(1 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
CLK : in STD_LOGIC;
A : in STD_LOGIC_VECTOR ( 7 downto 0 );
B : in STD_LOGIC_VECTOR ( 15 downto 0 );
P : out STD_LOGIC_VECTOR ( 15 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "mul8_16,mult_gen_v12_0_12,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "mult_gen_v12_0_12,Vivado 2016.4";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal NLW_U0_PCASC_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_U0_ZERO_DETECT_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_A_TYPE : integer;
attribute C_A_TYPE of U0 : label is 1;
attribute C_A_WIDTH : integer;
attribute C_A_WIDTH of U0 : label is 8;
attribute C_B_TYPE : integer;
attribute C_B_TYPE of U0 : label is 0;
attribute C_B_VALUE : string;
attribute C_B_VALUE of U0 : label is "10000001";
attribute C_B_WIDTH : integer;
attribute C_B_WIDTH of U0 : label is 16;
attribute C_CCM_IMP : integer;
attribute C_CCM_IMP of U0 : label is 0;
attribute C_CE_OVERRIDES_SCLR : integer;
attribute C_CE_OVERRIDES_SCLR of U0 : label is 0;
attribute C_HAS_CE : integer;
attribute C_HAS_CE of U0 : label is 0;
attribute C_HAS_SCLR : integer;
attribute C_HAS_SCLR of U0 : label is 0;
attribute C_HAS_ZERO_DETECT : integer;
attribute C_HAS_ZERO_DETECT of U0 : label is 0;
attribute C_LATENCY : integer;
attribute C_LATENCY of U0 : label is 3;
attribute C_MODEL_TYPE : integer;
attribute C_MODEL_TYPE of U0 : label is 0;
attribute C_MULT_TYPE : integer;
attribute C_MULT_TYPE of U0 : label is 0;
attribute C_OUT_HIGH : integer;
attribute C_OUT_HIGH of U0 : label is 23;
attribute C_OUT_LOW : integer;
attribute C_OUT_LOW of U0 : label is 8;
attribute C_ROUND_OUTPUT : integer;
attribute C_ROUND_OUTPUT of U0 : label is 0;
attribute C_ROUND_PT : integer;
attribute C_ROUND_PT of U0 : label is 0;
attribute C_VERBOSITY : integer;
attribute C_VERBOSITY of U0 : label is 0;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "kintexu";
attribute c_optimize_goal : integer;
attribute c_optimize_goal of U0 : label is 1;
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12
port map (
A(7 downto 0) => A(7 downto 0),
B(15 downto 0) => B(15 downto 0),
CE => '1',
CLK => CLK,
P(15 downto 0) => P(15 downto 0),
PCASC(47 downto 0) => NLW_U0_PCASC_UNCONNECTED(47 downto 0),
SCLR => '0',
ZERO_DETECT(1 downto 0) => NLW_U0_ZERO_DETECT_UNCONNECTED(1 downto 0)
);
end STRUCTURE;
|
bsd-3-clause
|
natsutan/NPU
|
fpga_implement/npu8/npu8.srcs/sources_1/ip/mult16_16/hdl/xbip_utils_v3_0_vh_rfs.vhd
|
13
|
163693
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname = "xilinx_2016_05", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 119040)
`protect data_block
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`protect end_protected
|
bsd-3-clause
|
natsutan/NPU
|
fpga_implement/npu8/npu8.srcs/sources_1/ip/mul17_16/hdl/xbip_utils_v3_0_vh_rfs.vhd
|
13
|
163693
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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Uh0w/eBguw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname = "xilinx_2016_05", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 119040)
`protect data_block
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`protect end_protected
|
bsd-3-clause
|
natsutan/NPU
|
fpga_implement/npu8/npu8.srcs/sources_1/ip/mult16_16/hdl/xbip_pipe_v3_0_vh_rfs.vhd
|
13
|
30077
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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cnDlo0luIQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname = "xilinx_2016_05", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 20128)
`protect data_block
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`protect end_protected
|
bsd-3-clause
|
natsutan/NPU
|
fpga_implement/npu8/npu8.srcs/sources_1/ip/mul8_16/hdl/xbip_pipe_v3_0_vh_rfs.vhd
|
13
|
30077
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname = "xilinx_2016_05", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 20128)
`protect data_block
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`protect end_protected
|
bsd-3-clause
|
GustaMagik/RSA_Security_Token
|
VHDL_code/ver_B/RSA_Security_Token_USB_Version/rsa_512/trunk/rtl/m_calc.vhd
|
1
|
2040
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:33:10 10/29/2009
-- Design Name:
-- Module Name: m_calc - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity m_calc is
port(
clk : in std_logic;
reset : in std_logic;
ab : in std_logic_vector (15 downto 0);
t : in std_logic_vector (15 downto 0);
n_cons : in std_logic_vector (15 downto 0);
m : out std_logic_vector (15 downto 0);
mult_valid : in std_logic; -- indica que los datos de entrada son validos
m_valid : out std_logic); -- la m calculada es valida
end m_calc;
architecture Behavioral of m_calc is
signal sum_res, next_sum_res : std_logic_vector(15 downto 0);
signal mult_valid_1, mult_valid_2 : std_logic; --delay del valido a lo largo del calculo
signal mult : std_logic_vector(31 downto 0);
begin
mult <= sum_res * n_cons;
process(clk, reset)
begin
if(clk = '1' and clk'event) then
if(reset = '1') then
sum_res <= (others => '0');
mult_valid_1 <= '0';
mult_valid_2 <= '0';
else
sum_res <= next_sum_res;
mult_valid_1 <= mult_valid;
mult_valid_2 <= mult_valid_1;
end if;
end if;
end process;
process(ab, t, mult_valid_2)
begin
m <= mult(15 downto 0);
next_sum_res <= ab+t;
m_valid <= mult_valid_2;
end process;
end Behavioral;
|
bsd-3-clause
|
GustaMagik/RSA_Security_Token
|
VHDL_code/ver_B/RSA_Security_Token_USB_Version/rsa_512/trunk/rtl/montgomery_step.vhd
|
1
|
8248
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:40:41 11/01/2009
-- Design Name:
-- Module Name: module_with_fifo - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity montgomery_step is
port(
clk : in std_logic;
reset : in std_logic;
valid_in : in std_logic;
a : in std_logic_vector(15 downto 0);
b : in std_logic_vector(15 downto 0);
n : in std_logic_vector(15 downto 0);
s_prev : in std_logic_vector(15 downto 0);
n_c : in std_logic_vector(15 downto 0);
s : out std_logic_vector( 15 downto 0);
valid_out : out std_logic; -- es le valid out TODO : cambiar nombre
busy : out std_logic;
b_req : out std_logic;
a_out : out std_logic_vector(15 downto 0);
n_out : out std_logic_vector(15 downto 0); --señal que indica que el modulo está ocupado y no puede procesar nuevas peticiones
c_step : out std_logic; --genera un pulso cuando termina su computo para avisar al modulo superior
stop : in std_logic
);
end montgomery_step;
architecture Behavioral of montgomery_step is
component pe_wrapper
port(
clk : in std_logic;
reset : in std_logic;
ab_valid : in std_logic;
valid_in : in std_logic;
a : in std_logic_vector(15 downto 0);
b : in std_logic_vector(15 downto 0);
n : in std_logic_vector(15 downto 0);
s_prev : in std_logic_vector(15 downto 0);
n_c : in std_logic_vector(15 downto 0);
s : out std_logic_vector( 15 downto 0);
data_ready : out std_logic;
fifo_req : out std_logic;
m_val : out std_logic;
reset_the_PE : in std_logic); -- estamos preparados para aceptar el siguiente dato
end component;
--Inputs
signal ab_valid : std_logic;
signal valid_mont, fifo_read, m_val, valid_mont_out, reset_pe : std_logic;
--Outputs
--definimos los estados
type state_type is (wait_valid, wait_m, mont_proc, getting_results, prep_m, b_stable);
signal state, next_state : state_type;
signal counter, next_counter : std_logic_vector(7 downto 0); -- cuenta las palabras que han salido para ir cortando
--Señales nuevas
signal mont_input_a, mont_input_n, mont_input_s : std_logic_vector(15 downto 0);
signal reg_constant, next_reg_constant, next_reg_input, reg_input : std_logic_vector(47 downto 0);
signal reg_out, reg_out_1, reg_out_2, reg_out_3, reg_out_4 : std_logic_vector(31 downto 0);
signal next_reg_out : std_logic_vector(31 downto 0);
--Cadena de registros hacia fuera
signal reg_input_1, reg_input_2, reg_input_3, reg_input_4, reg_input_5 : std_logic_vector(47 downto 0);
begin
mont : pe_wrapper port map (
clk => clk,
reset => reset,
ab_valid => ab_valid,
a => mont_input_a,
b => b,
n => mont_input_n,
s_prev => mont_input_s,
n_c => n_c,
s => s,
valid_in => valid_mont,
data_ready => valid_mont_out,
m_val => m_val,
reset_the_PE => reset_pe
);
process(clk, reset)
begin
if(clk = '1' and clk'event) then
if(reset = '1')then
state <= wait_valid;
counter <= (others => '0');
reg_constant <= (others => '0');
reg_input <= (others => '0');
reg_input_1 <= (others => '0');
reg_input_2 <= (others => '0');
reg_input_3 <= (others => '0');
reg_input_4 <= (others => '0');
reg_out <= (others => '0');
reg_out_1 <= (others => '0');
reg_out_2 <= (others => '0');
reg_out_3 <= (others => '0');
reg_out_4 <= (others => '0');
else
reg_input <= next_reg_input;
reg_input_1 <= reg_input;
reg_input_2 <= reg_input_1;
reg_input_3 <= reg_input_2;
reg_input_4 <= reg_input_3;
reg_input_5 <= reg_input_4;
reg_out <= reg_input_4(47 downto 32) & reg_input_4(31 downto 16);
reg_out_1 <= reg_out;
reg_out_2 <= reg_out_1;
reg_out_3 <= reg_out_2;
reg_out_4 <= reg_out_3;
state <= next_state;
counter <= next_counter;
reg_constant <= next_reg_constant;
end if;
end if;
end process;
process(state, valid_in, m_val, a, n, s_prev, counter, valid_mont_out, stop, reg_constant, reg_input_5, reg_out_4)
begin
--reset_fifo <= '0';
next_reg_input <= a&n&s_prev; --Propagación de la entrada TODO add variable
--next_reg_out <= a&n; --Vamos retrasando la entrada TODO add variable
a_out <= reg_out_4(31 downto 16);
n_out <= reg_out_4(15 downto 0);
next_state <= state;
next_counter <= counter;
--write_fifos <= valid_in;
ab_valid <= '0';
valid_mont <= '0';
valid_out <= '0';
reset_pe <= '0';
busy <= '1';
b_req <= '0';
c_step <= '0';
--Todo esto es nuevo
mont_input_a <= (others => '0');
mont_input_n <= (others => '0');
mont_input_s <= (others => '0');
next_reg_constant <= reg_constant;
case state is
when wait_valid =>
busy <= '0'; --esperamos la peticion
reset_pe <= '1';
if(valid_in = '1') then
b_req <= '1'; --Solicitamos al modulo externo la b
next_state <= b_stable;
next_reg_constant <= a&n&s_prev; --TODO add variable
end if;
when b_stable =>
next_state <= prep_m;
when prep_m =>
mont_input_a <= reg_constant(47 downto 32); --TODO add this to sensitivity
mont_input_n <= reg_constant(31 downto 16);
mont_input_s <= reg_constant(15 downto 0);
ab_valid <= '1';
next_state <= wait_m;
when wait_m =>
--Mantenemos las entradas para que nos calcule m correctamente
mont_input_a <= reg_constant(47 downto 32); --TODO add this to sensitivity
mont_input_n <= reg_constant(31 downto 16);
mont_input_s <= reg_constant(15 downto 0);
if (m_val = '1') then
valid_mont <= '1';
next_state <= mont_proc;
mont_input_a <= reg_input_5(47 downto 32);
mont_input_n <= reg_input_5(31 downto 16);
mont_input_s <= reg_input_5(15 downto 0);
end if;
when mont_proc =>
valid_mont <= '1';
mont_input_a <= reg_input_5(47 downto 32);
mont_input_n <= reg_input_5(31 downto 16);
mont_input_s <= reg_input_5(15 downto 0);
if(valid_mont_out = '1') then
next_counter <= x"00";
next_state <= getting_results;
end if;
when getting_results =>
valid_out <= '1';
next_counter <= counter+1;
valid_mont <= '1';
mont_input_a <= reg_input_5(47 downto 32);
mont_input_n <= reg_input_5(31 downto 16);
mont_input_s <= reg_input_5(15 downto 0);
if(counter = (x"22")) then
next_state <= wait_valid;
c_step <= '1';
reset_pe <= '1';
end if;
end case;
if(stop = '1') then
next_state <= wait_valid;
--reset_fifo <= '1';
reset_pe <= '1';
end if;
end process;
end Behavioral;
|
bsd-3-clause
|
GustaMagik/RSA_Security_Token
|
VHDL_code/ver_B/RSA_Security_Token_USB_Version/Security_Token_Top_USB.vhd
|
1
|
23239
|
--Copyright 2017 Christoffer Mathiesen, Gustav Örtenberg
--Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
--
--1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
--
--2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the
--documentation and/or other materials provided with the distribution.
--
--3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this
--software without specific prior written permission.
--
--THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS
--BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
--GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
--LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Library IEEE;
Use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_MISC.ALL;
Use IEEE.STD_LOGIC_UNSIGNED.ALL;
Use IEEE.NUMERIC_STD.all;
Use IEEE.MATH_REAL."log2";
Use IEEE.MATH_REAL."ceil";
Use work.all;
-----------------------------------Top_Module---------------------------------------------
--This module house all submodules that make up the 'koddosa' which is a
--challenge-response system that takes signs messages of length 512 bits
--with a predefined RSA key. The messages are sent over USB UART and
--uses a simple communication protocol defined in USB_TOP
--
--The flow of the program is:
--PowerOn->Init->PIN->Input from PC->RSA-encryption->Signal data avalible to PC ->
--On keyboard press soft reset circuit (returns to INIT).
--If a wrong PIN is input MAX_TRIES times in a row the program freezes at a blank screen
------------------------------------------------------------------------------------------
Entity Security_Token_Top_USB is
Generic( --PIN settings
PIN_LENGTH : Integer := 4; --Variable length of PIN
PIN_PSWRD : STD_LOGIC_VECTOR := x"ABCD"; --PIN, should have the same amount of numbers as PIN_LENGTH indicates
MAX_TRIES : Integer := 3; --Number of tries. 3 means one initial and 2 retries
SHOW_PIN : boolean := false; --If true the characters will be printed on screen when in PIN state, if false '*' will appear
TIMEOUT_SECONDS: INTEGER := 5; --Amount of seconds the device waits for a message to sign after the PIN is put
--Encryption settings
KEY_LENGTH : Integer := 512; --Key length in bits. HAS to be 512 with current modules
EXPONENT : STD_LOGIC_VECTOR := x"b15f20094a5fbcd7605b23bb7dbe7d421556df00d266c649d019cfc87eae543f703f6870013851130d3a2ed993ef76a1c377a96b95fe326f7326a319bae5fe01"; --Exponent of the RSA
MODULO : STD_LOGIC_VECTOR := x"bb847f2d87e8030926eea2a0a3f89877e6f63c1e2f65f3791e9c85549f48863a1dcc9f8b477c36dfea2573c49fc59259efe83b9996d093b4be09666e904cb17f"; --Modulus of the RSA
R_C_VAL : STD_LOGIC_VECTOR := x"8F80651391C778113C509FDD5C205AE6648A94DBC225A1ECA53F149BCF135AFCAC7E47DF209AC030325E1904AD7D260E236CE56D6753F488E3E489D50A6C2B0E"; --R_C value
--R_C is calculated by the formula 2^(16*([Words into RSA_512] + 1) * 2) mod MODULO, in standard case 2^(1056) mod MODULO
--If you are going to use this in a real world scenario, please use self-generated keys
--String pointers
STRING_PTR_0 : unsigned := to_unsigned(0,6);
STRING_PTR_1 : unsigned := to_unsigned(10,6);
STRING_PTR_2 : unsigned := to_unsigned(21,6);
STRING_PTR_3 : unsigned := to_unsigned(38,6);
--USB settings
Frequency : integer := 100_000_000;
BAUD : integer := 115200
);
Port ( clk : in STD_LOGIC;
Hex_in : in STD_LOGIC_VECTOR(3 downto 0);
Hex_out : out STD_LOGIC_VECTOR (3 downto 0);
LCD_RS : out STD_LOGIC;
LCD_RW : out STD_LOGIC;
LCD_E : out STD_LOGIC;
LCD_DB : out STD_LOGIC_VECTOR (7 downto 0);
TXD : out STD_LOGIC;
RXD : in STD_LOGIC;
RESET : in STD_LOGIC
);
end Security_Token_Top_USB;
architecture USB_behav of Security_Token_Top_USB is
constant MemSize : integer := (KEY_LENGTH/8);
constant LCD_CLEAR : STD_LOGIC_VECTOR (1 downto 0) := "00";
constant LCD_PRINT : STD_LOGIC_VECTOR (1 downto 0) := "01";
constant LCD_CHANGE: STD_LOGIC_VECTOR (1 downto 0) := "10";
constant PASSWORD : STD_LOGIC_VECTOR (PIN_LENGTH * 4 - 1 downto 0) := PIN_PSWRD;
constant MEM_BUS_WIDTH : Integer := integer(ceil(log2(real(MemSize))));
constant RAM_MAX_ADDR: unsigned(MEM_BUS_WIDTH-1 downto 0) := (others => '1');
constant ROM_MAX_ADDR: unsigned(5 downto 0) := (others => '1');
constant RSA_E : STD_LOGIC_VECTOR(KEY_LENGTH-1 downto 0) := EXPONENT;
constant RSA_M : STD_LOGIC_VECTOR(KEY_LENGTH-1 downto 0) := MODULO;
constant RSA_R_C : STD_LOGIC_VECTOR(KEY_LENGTH-1 downto 0) := R_C_VAL;
type PRG_STATE is (INIT, PRINT_MSG_1, GET_INPUT, PIN, RSA_2, RSA, PRINT_MSG_2,PRINT_MSG_3);
type LCD_SELECT is (SELECT_ASCII, SELECT_ROM, SELECT_RAM);
Signal STATE : PRG_STATE := INIT;
Signal WRONG_PIN_COUNTER : unsigned(1 downto 0) := (others => '0'); --if max tries more than 3, change this vector
Signal In_data : STD_LOGIC_VECTOR(3 downto 0); --From Keyboard
signal In_data_e, LCD_INPUT, INPUT_ASCII : STD_LOGIC_VECTOR (7 downto 0) := x"00";
Signal RDY, DO_CMD, RDY_CMD, WRITE_BACK, PIN_CORRECT : STD_LOGIC := '0';
Signal flag, WE, Read_RAM, INPUT_LSB, no_print : STD_LOGIC := '0';
Signal ROM_ADDR : UNSIGNED (5 downto 0) := (others => '0');
Signal RAM_ADDR : UNSIGNED (MEM_BUS_WIDTH-1 downto 0) := (others => '0');
Signal ROM_DATA, RAM_DATA_IN, RAM_DATA_OUT, ASCII_ENCODED : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
Signal Input_counter : UNSIGNED (MEM_BUS_WIDTH-1 downto 0) := (others => '0');
Signal MODE_SELECT : STD_LOGIC_VECTOR (1 downto 0) := LCD_CLEAR;
Signal TMP_INPUT : STD_LOGIC_VECTOR (3 downto 0);
Signal RSA_RESET, RSA_DONE, RSA_WE : STD_LOGIC := '0';
Signal RSA_START_ADDR, RSA_MEM_ADDR : STD_LOGIC_VECTOR (MEM_BUS_WIDTH-1 downto 0) := (others => '0');
Signal RSA_MEM_DATA_IN, RSA_MEM_DATA_OUT : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
signal RSA_WORD : integer range 0 to 32 := 0;
signal RSA_byte : integer range 0 to 64 := 0;
Signal LCD_INPUT_SELECT : LCD_SELECT := SELECT_ROM;
Signal valid_in, start_in, valid_out : STD_LOGIC;
Signal x, y, m, r_c, s : STD_LOGIC_VECTOR(15 downto 0);
component Keyboard
Port ( Row_Input : in STD_LOGIC_VECTOR (3 downto 0);
Col_Input_A : out STD_LOGIC_VECTOR (3 downto 0) := (others => '1');
Output : out STD_LOGIC_VECTOR (3 downto 0) := (others => '0');
RDY : out STD_LOGIC := '0';
CLK : in STD_LOGIC;
RESET : in STD_LOGIC
);
end component;
component byte_to_six_bit_splitter
Port ( DATA_IN : in STD_LOGIC_VECTOR (7 downto 0);
DATA_OUT : out STD_LOGIC_VECTOR (5 downto 0);
INC_ADDR : out STD_LOGIC;
ACTIVE : in STD_LOGIC;
CLK : in STD_LOGIC;
RESET : in STD_LOGIC
);
end component;
component LCD
Generic (Frequency: integer := Frequency);
Port ( INPUT : in STD_LOGIC_VECTOR (7 downto 0); --ASCII IN
CLK : in STD_LOGIC; --FPGA Clock (100MHz)
RESET : in STD_LOGIC; --RESET
DATA_BUS : out STD_LOGIC_VECTOR (7 downto 0); --DB 7 downto DB 0
RW : out STD_LOGIC := '0'; --RW signal (unused as of now)
RS : out STD_LOGIC; --RS signal
E : out STD_LOGIC; --E (200Hz)
MODE_SELECT : in STD_LOGIC_VECTOR (1 downto 0); --SELECT WHAT THE SCREEN IS TO DO
RDY_CMD : out STD_LOGIC := '0'; --Tell ouside world that the ready for the command
DO_CMD : in STD_LOGIC); --Outside world tell module to do the current command
end component;
component USB_TOP is
generic ( data_addr_width : integer := MEM_BUS_WIDTH;
BAUD_RATE : integer := BAUD;
CLOCK_RATE : integer := Frequency;
OVERSAMPLES : integer := 4);
Port ( CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
TXD : out STD_LOGIC;
RXD : in STD_LOGIC;
RAM_ADDR : out STD_LOGIC_VECTOR (data_addr_width-1 downto 0);
RAM_DATA_IN : in STD_LOGIC_VECTOR (7 downto 0);
RAM_DATA_OUT : out STD_LOGIC_VECTOR (7 downto 0);
RAM_WE : out STD_LOGIC;
READY_FOR_DATA : in STD_LOGIC;
RSA_DONE : in STD_LOGIC;
DATA_READY : out STD_LOGIC);
end component;
component ascii_encoder is
Port(input : in STD_LOGIC_VECTOR (7 downto 0);
output : out STD_LOGIC_VECTOR (7 downto 0)
);
end component;
component mem_array is
GENERIC(
DATA_WIDTH : integer := 8;
ADDR_WIDTH : integer := MEM_BUS_WIDTH);
Port(
ADDR : in STD_LOGIC_VECTOR(ADDR_WIDTH-1 downto 0);
DATAIN : in STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
clk : in std_logic;
WE : in std_logic;
OUTPUT : out STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0)
);
end component;
component mem_array_ROM is
GENERIC(
DATA_WIDTH : integer := 8;
ADDR_WIDTH : integer := 6);
Port(
ADDR : in STD_LOGIC_VECTOR(ADDR_WIDTH-1 downto 0);
OUTPUT : out STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0)
);
end component;
component RSA_top is
port(
clk : in std_logic;
reset : in std_logic;
valid_in : in std_logic;
start_in : in std_logic;
x : in std_logic_vector(15 downto 0); -- estos 3 son x^y mod m
y : in std_logic_vector(15 downto 0);
m : in std_logic_vector(15 downto 0);
r_c : in std_logic_vector(15 downto 0); --constante de montgomery r^2 mod m
s : out std_logic_vector(15 downto 0);
valid_out : out std_logic;
bit_size : in std_logic_vector(15 downto 0) --tamano bit del exponente y (log2(y))
);
end component;
signal RAM_DATA_IN_USB, RAM_DATA_OUT_USB : STD_LOGIC_VECTOR(7 downto 0);
signal RAM_ADDR_USB : STD_LOGIC_VECTOR(MEM_BUS_WIDTH-1 downto 0);
signal RAM_WE_USB, READY_FOR_DATA, DATA_READY: STD_LOGIC;
signal RSA_X : STD_LOGIC_VECTOR (511 downto 0);
signal RESETN, soft_reset : STD_LOGIC;
signal timeout_timer : integer := 0;
--signal clk, tog : std_logic;
begin
ASCII: ascii_encoder port map (
input => INPUT_ASCII,
output => ASCII_ENCODED
);
USB: USB_TOP Port map (
CLK => clk,
RESET => RESETN,
TXD => TXD,
RXD => RXD,
RAM_ADDR => RAM_ADDR_USB,
RAM_DATA_IN => RAM_DATA_OUT,
RAM_DATA_OUT => RAM_DATA_OUT_USB,
RAM_WE => RAM_WE_USB,
DATA_READY => DATA_READY,
READY_FOR_DATA => READY_FOR_DATA,
RSA_DONE => RSA_DONE);
RSA_MODULE: RSA_top port map(
clk => clk,
reset => RESETN,
valid_in => valid_in,
start_in => start_in,
x => x, -- estos 3 son x^y mod m
y => y,
m => m,
r_c => r_c, --constante de montgomery r^2 mod m
s => s,
valid_out => valid_out,
bit_size => x"0200" --512 --tamano bit del exponente y (log2(y))
);
SCREEN: LCD port map (
INPUT => LCD_INPUT,
CLK => clk,
RESET => RESETN,
DATA_BUS => LCD_DB,
RW => LCD_RW,
RS => LCD_RS,
E => LCD_E,
MODE_SELECT => MODE_SELECT,
RDY_CMD => RDY_CMD,
DO_CMD => DO_CMD
);
KBD : Keyboard port map (
Row_Input => Hex_in,
Col_Input_A => Hex_out,
Output => In_data,
RDY => RDY,
CLK => clk,
RESET => RESETN
);
ROM:
mem_array_ROM port map(
ADDR => STD_LOGIC_VECTOR(ROM_ADDR),
OUTPUT => ROM_DATA
);
RAM:
mem_array port map(
ADDR => STD_LOGIC_VECTOR(RAM_ADDR),
DATAIN => RAM_DATA_IN,
clk => clk,
WE => WE,
OUTPUT => RAM_DATA_OUT);
INPUT_ASCII <= "0000" & IN_DATA;
with STATE select
RAM_DATA_IN <=
RAM_DATA_OUT_USB when GET_INPUT,
RSA_MEM_DATA_IN when RSA,
RAM_DATA_OUT_USB when others;
with STATE select
RAM_ADDR <=
unsigned(RAM_ADDR_USB) when GET_INPUT,
unsigned(RSA_MEM_ADDR) when RSA, --Give the RSA access to the memory when it needs it
unsigned(RAM_ADDR_USB) when others; --Otherwise make the USB able to use it
with STATE select
WE <=
RAM_WE_USB when GET_INPUT,
RSA_WE when RSA,
RAM_WE_USB when others;
LCD_INPUT <= ROM_DATA when LCD_INPUT_SELECT = SELECT_ROM else --LCD gets data from ROM
RAM_DATA_OUT when LCD_INPUT_SELECT = SELECT_RAM else --LCD gets data from RAM
ASCII_ENCODED when (LCD_INPUT_SELECT = SELECT_ASCII AND SHOW_PIN) else -- LCD gets data from keyboard and shows the characters (show PIN)
x"2A" when (LCD_INPUT_SELECT = SELECT_ASCII AND NOT SHOW_PIN) else --LCD only prints '*' when otherwise it would read from keyboard (NOT show PIN)
ROM_DATA;
RESETN <= NOT RESET or soft_reset; --Invert the reset signal as the input is low when the button is pressed
--State changes
process(clk)
begin
if rising_edge(clk) then --synchronous reset
if RESETN = '1' then
STATE <= INIT;
flag <= '0';
ROM_ADDR <= (others => '0');
LCD_INPUT_SELECT <= SELECT_ROM;
valid_in <= '0';
start_in <= '0';
DO_CMD <= '0';
Input_counter <= (others => '0');
--WRONG_PIN_COUNTER <= (others => '0'); --Uncomment if debug
PIN_CORRECT <= '0';
READY_FOR_DATA <= '0';
RSA_DONE <= '0';
RSA_X <= (others => '0');
RSA_MEM_ADDR <= (others => '0');
RSA_BYTE <= 0;
RSA_WORD <= 0;
RSA_MEM_DATA_IN <= (others => '0');
x <= (others => '0');
y <= (others => '0');
m <= (others => '0');
r_c <= (others => '0');
READY_FOR_DATA <= '0';
soft_reset <= '0';
timeout_timer <= 0;
else
--If we are telling the screen to do a command and RDY_CMD goes to 0
--it means that the screen is working on it. Thus we should stop
--telling the screen to do commands.
if RDY_CMD = '0' and DO_CMD = '1' then
DO_CMD <= '0';
else
--reset <= '0';
case STATE is
------------------------------------------------------------------------------
when INIT =>
soft_reset <= '0';
if RDY_CMD = '1' and DO_CMD = '0' then --Wait for the LCD to be ready
MODE_SELECT <= LCD_CLEAR;
DO_CMD <= '1'; --Clear the screen
STATE <= PIN; --if PIN is unwanted, change this to Print_MSG_1
ROM_ADDR <= STRING_PTR_0 - 1;
--RESET <= '1';
flag <= '0';
end if;
------------------------------------------------------------------------------
when PIN =>
--RESET <= '0';
if flag = '0' then --If in print mode
if RDY_CMD = '1' and DO_CMD = '0' then --If the screen is ready for a command
LCD_INPUT_SELECT <= SELECT_ROM; --Use characters from ROM
MODE_SELECT <= LCD_PRINT; --Set the screen in print mode
DO_CMD <= '1'; --Execute the command
if ROM_DATA = x"00" and ROM_ADDR /= STRING_PTR_0 - 1 then --char is '\0' (and not the last rom addr)
MODE_SELECT <= LCD_CHANGE; --Set screen in change row mode
Input_counter <= to_unsigned(PIN_LENGTH, MEM_BUS_WIDTH); --Set the input counter to the PIN length
-- RAM_ADDR <= (others => '0');
PIN_CORRECT <= '1'; --Assume correct pin
flag <= '1'; --Insert PIN mode
else
ROM_ADDR <= ROM_ADDR + 1; --Inc the ROM ptr while printing
end if;
end if;
elsif RDY_CMD = '1' and DO_CMD = '0' then --If the screen is ready for a character
LCD_INPUT_SELECT <= SELECT_ASCII;
if Input_counter = 0 and PIN_CORRECT = '1' then --if the entire PIN is put and it was correct
MODE_SELECT <= LCD_CLEAR; --Clear the screen
flag <= '0'; --reset this flag
DO_CMD <= '1'; --Do the command
STATE <= PRINT_MSG_1; --move on to next part of program
ROM_ADDR <= STRING_PTR_2 - 1; --set the pointer for next part of program
WRONG_PIN_COUNTER <= (others => '0'); --Reset the amount of incorrect tries
elsif Input_counter = 0 and PIN_CORRECT = '0' then --If entire PIN is put and it was incorrect
MODE_SELECT <= LCD_CLEAR; --Clear the screen
STATE <= PRINT_MSG_3; --
ROM_ADDR <= STRING_PTR_1 - 1;
DO_CMD <= '1';
WRONG_PIN_COUNTER <= WRONG_PIN_COUNTER + 1; --Inc the counter
flag <= '0'; --reset the flag
elsif RDY = '1' then --if a character was input from the keyboard
MODE_SELECT <= LCD_PRINT;
DO_CMD <= '1';
if PASSWORD(to_integer(input_counter * 4 - 1) downto to_integer(input_counter * 4 - 4)) /= In_data then -- if the current number was wrong the entire pin is wrong
PIN_CORRECT <= '0'; --set to incorrect pin
end if;
Input_counter <= Input_counter - 1; --dec the counter
end if;
end if;
---------------------------------------------------------------------
when PRINT_MSG_3 =>
if WRONG_PIN_COUNTER < MAX_TRIES then
if RDY_CMD = '1' and DO_CMD = '0' then
LCD_INPUT_SELECT <= SELECT_ROM;
MODE_SELECT <= LCD_PRINT;
DO_CMD <= '1';
if ROM_DATA /= x"00" or ROM_ADDR = STRING_PTR_1 - 1 then --char is not '\0', continue printing
ROM_ADDR <= ROM_ADDR + 1;
elsif RDY = '1' then
MODE_SELECT <= LCD_CLEAR;
STATE <= INIT;
Input_counter <= (others => '0');
-- RAM_ADDR <= (others => '0');
else
DO_CMD <= '0';
end if;
end if;
end if;
------------------------------------------------------------------------------
when PRINT_MSG_1 =>
if RDY_CMD = '1' and DO_CMD = '0' then
LCD_INPUT_SELECT <= SELECT_ROM;
MODE_SELECT <= LCD_PRINT;
DO_CMD <= '1';
if ROM_DATA /= x"00" or ROM_ADDR = STRING_PTR_2 - 1 then --char is not '\0', continue printing
ROM_ADDR <= ROM_ADDR + 1;
else
MODE_SELECT <= LCD_CHANGE;
STATE <= GET_INPUT;
READY_FOR_DATA <= '1'; --Signal the USB-controller that we are ready for loading the RAM with data
Input_counter <= (others => '0');
-- RAM_ADDR <= (others => '0');
end if;
end if;
------------------------------------------------------------------------------
when GET_INPUT =>
READY_FOR_DATA <= '1'; --Signal the USB-controller that we are ready for loading the RAM with data
RSA_DONE <= '0'; --Signal the USB-controller that the RSA is NOT done
flag <= '1';
timeout_timer <= timeout_timer + 1;
if timeout_timer = timeout_seconds * frequency then
SOFT_RESET <= '1';
elsif DATA_READY = '1' and flag = '1' then --Data recieved. (and one cycle extra passed to let things catch up in a loop scenario)
STATE <= RSA; --Perform the RSA
READY_FOR_DATA <= '0';--And set so the USB can't write to the RAM anymore
RSA_MEM_ADDR <= (others => '0'); --reset the RSA_MEM_ADDR pointer
READY_FOR_DATA <= '0';
STATE <= RSA;
flag <= '0';
end if;
------------------------------------------------------------------------------
when RSA =>
--First prepare the data from memory to introduction into RSA_512
if flag = '0' then --if not in the writing stage
if RSA_BYTE < 64 then --Loading of the data
RSA_X(RSA_BYTE*8+7 downto RSA_BYTE*8) <= RAM_DATA_OUT;
RSA_MEM_ADDR <= RSA_MEM_ADDR + 1; --inc the pointer
RSA_BYTE <= RSA_BYTE + 1;
else
--RSA_X(RSA_BYTE*8+7 downto RSA_BYTE*8) <= RAM_DATA_OUT; --Last byte to be read
RSA_MEM_ADDR <= (others => '1'); --reset the pointer
end if;
end if;
if RSA_WORD = 32 then
valid_in <= '0';
end if;
if flag = '0' then --The loading of the RSA module
if RSA_MEM_ADDR < 31-8 then --preload the n_c value for the RSA init-sequence
m(15 downto 0) <= RSA_M(15 downto 0);
elsif RSA_MEM_ADDR = 31 - 8 then --Start the init-sequence when half-6 bytes are loaded to the register
start_in <= '1';
elsif RSA_MEM_ADDR <= 31 then --Set the flag low again and wait for 6 cycles
start_in <= '0';
elsif RSA_MEM_ADDR > 31 and RSA_WORD < 32 then --Start loading the RSA_512
x <= RSA_X(RSA_WORD*16+15 downto RSA_WORD*16); --Message value
y <= RSA_E(RSA_WORD*16+15 downto RSA_WORD*16); --Key value
m <= RSA_M(RSA_WORD*16+15 downto RSA_WORD*16); --Modulo value
r_c <= RSA_R_C(RSA_WORD*16+15 downto RSA_WORD*16); --R_C value
valid_in <= '1'; --Valid data in flag
RSA_WORD <= RSA_WORD + 1; --inc the pointer
if RSA_WORD = 31 then
--notihing
end if;
else
valid_in <= '0'; --No more data in
flag <= '1'; --set the mode to write back to memory
RSA_WORD <= 0; --reset the counter to 0
end if;
else --Writing to memory
if RSA_WORD < 32 AND valid_out = '1' then --if not the final byte from RSA_512 result (s)
RSA_X(RSA_WORD*16+15 downto RSA_WORD*16) <= s; --save it in the register
RSA_WORD <= RSA_WORD + 1; --inc the pointer
input_counter <= (others => '0');
RSA_MEM_ADDR <= (others => '1'); --Set this to max to overflow back to 0 and thus inserting the correct number in that cell
RSA_BYTE <= 0;
elsif RSA_WORD = 32 then --start writing back to RAM
if RSA_BYTE < 64 then --If we haven't written the entire result to memory
RSA_MEM_ADDR <= RSA_MEM_ADDR + 1; --increase the addr
RSA_MEM_DATA_IN <= RSA_X(RSA_BYTE*8+7 downto RSA_BYTE*8); --use the correct part of the result
RSA_WE <= '1'; --write it to memory
RSA_BYTE <= RSA_BYTE + 1; --increase the counter
else --everything written back
RSA_WE <= '0'; --stop writing
flag <= '0'; --reset this flag
RSA_DONE <= '1'; --The result is done and in memory. Tell USB-cmd so
STATE <= PRINT_MSG_2; --move on
RSA_BYTE <= 0;
RSA_WORD <= 0;
end if;
end if;
end if;
-----------------------------------------------------------------------------------------------------
when PRINT_MSG_2 =>
if RDY_CMD = '1' and DO_CMD = '0' then
MODE_SELECT <= LCD_PRINT;
DO_CMD <= '1';
LCD_INPUT_SELECT <= SELECT_ROM;
if ROM_DATA /= x"00" or ROM_ADDR = STRING_PTR_3 - 1 then --char is not '\0', continue printing
ROM_ADDR <= ROM_ADDR + 1;
else
DO_CMD <= '0';
if RDY = '1' then --wait for a press on the keyboard
Input_counter <= (others => '0');
soft_reset <= '1';
STATE <= INIT;
end if;
end if;
end if;
------------------------------------------------------------------------------
when others =>
--kill me
end case;
end if;
end if;
end if;
end process;
end USB_behav;
|
bsd-3-clause
|
bzero/freezing-spice
|
src/mem.vhd
|
2
|
352
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.common.all;
use work.mem_pkg.all;
entity memory_stage is
port (mem_d : in mem_in;
mem_q : out mem_out);
end entity memory_stage;
architecture Behavioral of memory_stage is
begin -- architecture Behavioral
end architecture Behavioral;
|
bsd-3-clause
|
iti-luebeck/RTeasy1
|
src/main/resources/vhdltmpl/demux.vhd
|
1
|
2446
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY demux IS
GENERIC(
select_width, line_width : positive;
default_out : std_logic
);
PORT(
INPUT : IN std_logic_vector(line_width-1 DOWNTO 0);
SEL : IN std_logic_vector(select_width-1 DOWNTO 0);
FLOOD : IN std_logic; -- FLOOD=1 causes all bits of OUTPUT to be set to 1
OUTPUT : OUT std_logic_vector(2**select_width*line_width-1 DOWNTO 0)
);
END demux;
ARCHITECTURE recursive OF demux IS
SIGNAL subdemux_0_IN, subdemux_1_IN : std_logic_vector(line_width-1 DOWNTO 0);
COMPONENT demux
GENERIC(
select_width, line_width : positive;
default_out : std_logic
);
PORT(
INPUT : IN std_logic_vector(line_width-1 DOWNTO 0);
SEL : IN std_logic_vector(select_width-1 DOWNTO 0);
FLOOD : IN std_logic; -- FLOOD=1 causes all bits of OUTPUT to be set to 1
OUTPUT : OUT std_logic_vector(2**select_width*line_width-1 DOWNTO 0)
);
END COMPONENT;
FOR ALL : demux USE ENTITY WORK.demux(recursive);
BEGIN
demux1to2: IF select_width=1 GENERATE
OUTPUT(line_width-1 DOWNTO 0) <= (OTHERS => '1') WHEN FLOOD='1'
ELSE INPUT WHEN SEL="0" ELSE (OTHERS => default_out);
OUTPUT(2*line_width-1 DOWNTO line_width) <= (OTHERS => '1') WHEN FLOOD='1'
ELSE INPUT WHEN SEL="1" ELSE (OTHERS => default_out);
END GENERATE;
demux1toN: IF select_width>1 GENERATE
subdemux_0: demux
GENERIC MAP(select_width => select_width-1, line_width => line_width,
default_out => default_out)
PORT MAP(INPUT => subdemux_0_IN,
SEL => SEL(select_width-2 DOWNTO 0),
FLOOD => FLOOD,
OUTPUT => OUTPUT(2**(select_width-1)*line_width-1 DOWNTO 0));
subdemux_1: demux
GENERIC MAP(select_width => select_width-1, line_width => line_width,
default_out => default_out)
PORT MAP(INPUT => subdemux_1_IN,
SEL => SEL(select_width-2 DOWNTO 0),
FLOOD => FLOOD,
OUTPUT => OUTPUT(2**select_width*line_width-1
DOWNTO 2**(select_width-1)*line_width));
subdemux_0_IN <= INPUT WHEN SEL(select_width-1)='0'
ELSE (OTHERS => default_out);
subdemux_1_IN <= INPUT WHEN SEL(select_width-1)='1'
ELSE (OTHERS => default_out);
END GENERATE;
END recursive;
|
bsd-3-clause
|
iti-luebeck/RTeasy1
|
src/main/resources/vhdltmpl/cu_architecture_signals.vhd
|
3
|
168
|
SIGNAL I_BUFFERED : std_logic_vector(0 TO %%I_MAX);
SIGNAL C_SIG : std_logic_vector(0 TO %%C_MAX);
SIGNAL STATE, NEXTSTATE : std_logic_vector(%%STATEWIDTH_M1 DOWNTO 0);
|
bsd-3-clause
|
eamadio/fpgaMSP430
|
fmsp430/dbg/fmsp_dbg_hwbrk.vhd
|
1
|
14279
|
------------------------------------------------------------------------------
--! Copyright (C) 2009 , Olivier Girard
--
--! Redistribution and use in source and binary forms, with or without
--! modification, are permitted provided that the following conditions
--! are met:
--! * Redistributions of source code must retain the above copyright
--! notice, this list of conditions and the following disclaimer.
--! * Redistributions in binary form must reproduce the above copyright
--! notice, this list of conditions and the following disclaimer in the
--! documentation and/or other materials provided with the distribution.
--! * Neither the name of the authors nor the names of its contributors
--! may be used to endorse or promote products derived from this software
--! without specific prior written permission.
--
--! THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--! AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
--! IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
--! ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
--! LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
--! OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--! SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--! INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--! CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--! ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
--! THE POSSIBILITY OF SUCH DAMAGE
--
------------------------------------------------------------------------------
--
--! @file fmsp_dbg_hwbrk.vhd
--!
--! @brief fpgaMSP430 Hardware Breakpoint / Watchpoint module
--
--! @author Olivier Girard, [email protected]
--! @author Emmanuel Amadio, [email protected] (VHDL Rewrite)
--
------------------------------------------------------------------------------
--! @version 1
--! @date: 2017-04-21
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all; --! standard unresolved logic UX01ZWLH-
use ieee.numeric_std.all; --! for the signed, unsigned types and arithmetic ops
use work.fmsp_dbg_package.all;
entity fmsp_dbg_hwbrk is
generic (
DBG_HWBRK_EN : boolean := false -- Include hardware breakpoints unit
);
port (
dbg_clk : in std_logic; --! Debug unit clock
dbg_rst : in std_logic; --! Debug unit reset
--! INPUTs
brk_reg_rd : in std_logic_vector(3 downto 0); --! Hardware break/watch-point register read select
brk_reg_wr : in std_logic_vector(3 downto 0); --! Hardware break/watch-point register write select
dbg_din : in std_logic_vector(15 downto 0); --! Debug register data input
decode_noirq : in std_logic; --! Frontend decode instruction
eu_mab : in std_logic_vector(15 downto 0); --! Execution-Unit Memory address bus
eu_mb_en : in std_logic; --! Execution-Unit Memory bus enable
eu_mb_wr : in std_logic_vector(1 downto 0); --! Execution-Unit Memory bus write transfer
pc : in std_logic_vector(15 downto 0); --! Program counter
--! OUTPUTs
brk_halt : out std_logic; --! Hardware breakpoint command
brk_pnd : out std_logic; --! Hardware break/watch-point pending
brk_dout : out std_logic_vector(15 downto 0) --! Hardware break/watch-point register data input
);
end entity fmsp_dbg_hwbrk;
architecture RTL of fmsp_dbg_hwbrk is
constant C_HWBRK_RANGE : std_logic := '0';
constant BRK_CTL : integer := 0;
constant BRK_STAT : integer := 1;
constant BRK_ADDR0 : integer := 2;
constant BRK_ADDR1 : integer := 3;
type fmsp_dbg_hwbrk_in_type is record
brk_reg_rd : std_logic_vector(3 downto 0); --! Hardware break/watch-point register read select
brk_reg_wr : std_logic_vector(3 downto 0); --! Hardware break/watch-point register write select
dbg_din : std_logic_vector(15 downto 0); --! Debug register data input
decode_noirq : std_logic; --! Frontend decode instruction
eu_mab : std_logic_vector(15 downto 0); --! Execution-Unit Memory address bus
eu_mb_en : std_logic; --! Execution-Unit Memory bus enable
eu_mb_wr : std_logic_vector(1 downto 0); --! Execution-Unit Memory bus write transfer
pc : std_logic_vector(15 downto 0); --! Program counter
end record;
type reg_type is record
brk_ctl : std_logic_vector(4 downto 0);
brk_stat : std_logic_vector(5 downto 0);
brk_addr0 : std_logic_vector(15 downto 0);
brk_addr1 : std_logic_vector(15 downto 0);
end record;
signal d : fmsp_dbg_hwbrk_in_type;
signal r : reg_type := ( brk_ctl => "00000",
brk_stat => "000000",
brk_addr0 => x"0000",
brk_addr1 => x"0000"
);
signal rin : reg_type;
begin
d.brk_reg_rd <= brk_reg_rd;
d.brk_reg_wr <= brk_reg_wr;
d.dbg_din <= dbg_din;
d.decode_noirq <= decode_noirq;
d.eu_mab <= eu_mab;
d.eu_mb_en <= eu_mb_en;
d.eu_mb_wr <= eu_mb_wr;
d.pc <= pc;
COMB : process (d, r)
variable v : reg_type;
variable v_brk_ctl_wr : std_logic;
variable v_brk_ctl_full : std_logic_vector(7 downto 0);
variable v_brk_stat_wr : std_logic;
variable v_brk_stat_set : std_logic_vector(5 downto 0);
variable v_brk_stat_clr : std_logic_vector(5 downto 0);
variable v_brk_stat_full : std_logic_vector(7 downto 0);
variable v_brk_pnd : std_logic;
variable v_brk_addr0_wr : std_logic;
variable v_brk_addr1_wr : std_logic;
variable v_brk_ctl_rd : std_logic_vector(15 downto 0);
variable v_brk_stat_rd : std_logic_vector(15 downto 0);
variable v_brk_addr0_rd : std_logic_vector(15 downto 0);
variable v_brk_addr1_rd : std_logic_vector(15 downto 0);
variable v_brk_dout : std_logic_vector(15 downto 0);
variable v_equ_d_addr0 : std_logic;
variable v_equ_d_addr1 : std_logic;
variable v_equ_d_range : std_logic;
variable v_equ_i_addr0 : std_logic;
variable v_equ_i_addr1 : std_logic;
variable v_equ_i_range : std_logic;
--! Detect Instruction read access
variable v_i_addr0_rd : std_logic;
variable v_i_addr1_rd : std_logic;
variable v_i_range_rd : std_logic;
--! Detect Execution-Unit write access
variable v_d_addr0_wr : std_logic;
variable v_d_addr1_wr : std_logic;
variable v_d_range_wr : std_logic;
--! Detect DATA read acces
variable v_d_addr0_rd : std_logic;
variable v_d_addr1_rd : std_logic;
variable v_d_range_rd : std_logic;
--! Set flags
variable v_addr0_rd_set : std_logic;
variable v_addr0_wr_set : std_logic;
variable v_addr1_rd_set : std_logic;
variable v_addr1_wr_set : std_logic;
variable v_range_rd_set : std_logic;
variable v_range_wr_set : std_logic;
--! Break CPU
variable v_brk_halt : std_logic;
begin
--! default assignment
v := r;
--! overriding assignments
--============================================================================
--! 4) BREAKPOINT / WATCHPOINT GENERATION
--============================================================================
--! Comparators
-----------------------------
--! Note: here the comparison logic is instanciated several times in order
--! to improve the timings, at the cost of a bit more area.
v_equ_d_addr0 := '0';
v_equ_d_addr1 := '0';
v_equ_d_range := '0';
if ( UNSIGNED(d.eu_mab) = UNSIGNED(r.brk_addr0) ) then
v_equ_d_addr0 := d.eu_mb_en and not(r.brk_ctl(C_BRK_RANGE));
end if;
if ( UNSIGNED(d.eu_mab) = UNSIGNED(r.brk_addr1) ) then
v_equ_d_addr1 := d.eu_mb_en and not(r.brk_ctl(C_BRK_RANGE));
end if;
if ( ( UNSIGNED(d.eu_mab) >= UNSIGNED(r.brk_addr0) )
or ( UNSIGNED(d.eu_mab) <= UNSIGNED(r.brk_addr1) ) ) then
v_equ_d_range := d.eu_mb_en and not(r.brk_ctl(C_BRK_RANGE)) and C_HWBRK_RANGE;
end if;
v_equ_i_addr0 := '0';
v_equ_i_addr1 := '0';
v_equ_i_range := '0';
if ( UNSIGNED(d.pc) = UNSIGNED(r.brk_addr0) ) then
v_equ_i_addr0 := d.decode_noirq and not(r.brk_ctl(C_BRK_RANGE));
end if;
if ( UNSIGNED(d.pc) = UNSIGNED(r.brk_addr1) ) then
v_equ_i_addr1 := d.decode_noirq and not(r.brk_ctl(C_BRK_RANGE));
end if;
if ( ( UNSIGNED(d.pc) >= UNSIGNED(r.brk_addr0) )
or ( UNSIGNED(d.pc) <= UNSIGNED(r.brk_addr1) ) ) then
v_equ_i_range := d.decode_noirq and not(r.brk_ctl(C_BRK_RANGE)) and C_HWBRK_RANGE;
end if;
--! Detect accesses
-----------------------------
--! Detect Instruction read access
v_i_addr0_rd := v_equ_i_addr0 and r.brk_ctl(C_BRK_I_EN);
v_i_addr1_rd := v_equ_i_addr1 and r.brk_ctl(C_BRK_I_EN);
v_i_range_rd := v_equ_i_range and r.brk_ctl(C_BRK_I_EN);
--! Detect Execution-Unit write access
v_d_addr0_wr := v_equ_d_addr0 and not(r.brk_ctl(C_BRK_I_EN)) and (d.eu_mb_wr(0) or d.eu_mb_wr(1));
v_d_addr1_wr := v_equ_d_addr1 and not(r.brk_ctl(C_BRK_I_EN)) and (d.eu_mb_wr(0) or d.eu_mb_wr(1));
v_d_range_wr := v_equ_d_range and not(r.brk_ctl(C_BRK_I_EN)) and (d.eu_mb_wr(0) or d.eu_mb_wr(1));
--! Detect DATA read access
v_d_addr0_rd := v_equ_d_addr0 and not(r.brk_ctl(C_BRK_I_EN)) and not(d.eu_mb_wr(0) or d.eu_mb_wr(1));
v_d_addr1_rd := v_equ_d_addr1 and not(r.brk_ctl(C_BRK_I_EN)) and not(d.eu_mb_wr(0) or d.eu_mb_wr(1));
v_d_range_rd := v_equ_d_range and not(r.brk_ctl(C_BRK_I_EN)) and not(d.eu_mb_wr(0) or d.eu_mb_wr(1));
--! Set flags
v_addr0_rd_set := r.brk_ctl(C_BRK_MODE_RD) and (v_d_addr0_rd or v_i_addr0_rd);
v_addr0_wr_set := r.brk_ctl(C_BRK_MODE_WR) and v_d_addr0_wr;
v_addr1_rd_set := r.brk_ctl(C_BRK_MODE_RD) and (v_d_addr1_rd or v_i_addr1_rd);
v_addr1_wr_set := r.brk_ctl(C_BRK_MODE_WR) and v_d_addr1_wr;
v_range_rd_set := r.brk_ctl(C_BRK_MODE_RD) and (v_d_range_rd or v_i_range_rd);
v_range_wr_set := r.brk_ctl(C_BRK_MODE_WR) and v_d_range_wr;
--=============================================================================
--! 2) CONFIGURATION REGISTERS
--=============================================================================
--! BRK_CTL Register
-------------------------------------------------------------------------------
--! 7 6 5 4 3 2 1 0
--! Reserved RANGE_MODE INST_EN BREAK_EN ACCESS_MODE
--
--! ACCESS_MODE: - 00 : Disabled
--! - 01 : Detect read access
--! - 10 : Detect write access
--! - 11 : Detect read/write access
--! NOTE: '10' & '11' modes are not supported on the instruction flow
--
--! BREAK_EN: - 0 : Watchmode enable
--! - 1 : Break enable
--
--! INST_EN: - 0 : Checks are done on the execution unit (data flow)
--! - 1 : Checks are done on the frontend (instruction flow)
--
--! RANGE_MODE: - 0 : Address match on BRK_ADDR0 or BRK_ADDR1
--! - 1 : Address match on BRK_ADDR0->BRK_ADDR1 range
--
-------------------------------------------------------------------------------
v_brk_ctl_wr := d.brk_reg_wr(BRK_CTL);
if (v_brk_ctl_wr) then
v.brk_ctl := (C_HWBRK_RANGE and d.dbg_din(4)) & d.dbg_din(3 downto 0);
end if;
v_brk_ctl_full := "000" & r.brk_ctl;
--! BRK_STAT Register
-------------------------------------------------------------------------------
--! 7 6 5 4 3 2 1 0
--! Reserved RANGE_WR RANGE_RD ADDR1_WR ADDR1_RD ADDR0_WR ADDR0_RD
-------------------------------------------------------------------------------
v_brk_stat_wr := d.brk_reg_wr(BRK_STAT);
v_brk_stat_set := (v_range_wr_set and C_HWBRK_RANGE)
& (v_range_rd_set and C_HWBRK_RANGE)
& v_addr1_wr_set & v_addr1_rd_set
& v_addr0_wr_set & v_addr0_rd_set;
v_brk_stat_clr := not(d.dbg_din(5 downto 0));
if (v_brk_stat_wr) then
v.brk_stat := v_brk_stat_set or (r.brk_stat and v_brk_stat_clr);
else
v.brk_stat := v_brk_stat_set or r.brk_stat;
end if;
v_brk_stat_full := "00" & r.brk_stat;
v_brk_pnd := r.brk_stat(0) or r.brk_stat(1) or r.brk_stat(2) or r.brk_stat(3) or r.brk_stat(4) or r.brk_stat(5);
--! BRK_ADDR0 Register
-------------------------------------------------------------------------------
v_brk_addr0_wr := d.brk_reg_wr(BRK_ADDR0);
if (v_brk_addr0_wr) then
v.brk_addr0 := d.dbg_din;
end if;
--! BRK_ADDR1/DATA0 Register
-------------------------------------------------------------------------------
v_brk_addr1_wr := d.brk_reg_wr(BRK_ADDR1);
if (v_brk_addr1_wr) then
v.brk_addr1 := d.dbg_din;
end if;
--============================================================================
--! 3) DATA OUTPUT GENERATION
--============================================================================
v_brk_ctl_rd := x"0000";
v_brk_stat_rd := x"0000";
v_brk_addr0_rd := x"0000";
v_brk_addr1_rd := x"0000";
if ( d.brk_reg_rd(BRK_CTL) = '1' ) then
v_brk_ctl_rd := x"00" & v_brk_ctl_full;
end if;
if ( d.brk_reg_rd(BRK_STAT) = '1' ) then
v_brk_stat_rd := x"00" & v_brk_stat_full;
end if;
if ( d.brk_reg_rd(BRK_CTL) = '1' ) then
v_brk_addr0_rd := r.brk_addr0;
end if;
if ( d.brk_reg_rd(BRK_STAT) = '1' ) then
v_brk_addr1_rd := r.brk_addr1;
end if;
v_brk_dout := v_brk_ctl_rd
or v_brk_stat_rd
or v_brk_addr0_rd
or v_brk_addr1_rd;
--! Break CPU
v_brk_halt := '0';
if ( v_brk_stat_set /= "000000" ) then
v_brk_halt := r.brk_ctl(C_BRK_EN);
end if;
if (DBG_HWBRK_EN = false) then
v_brk_halt := '0';
v_brk_pnd := '0';
v_brk_dout := x"0000";
end if;
--! drive register inputs
rin <= v;
--! drive module outputs
brk_halt <= v_brk_halt; --! Hardware breakpoint command
brk_pnd <= v_brk_pnd; --! Hardware break/watch-point pending
brk_dout <= v_brk_dout; --! Hardware break/watch-point register data input
end process COMB;
REGS : process (dbg_clk,dbg_rst)
begin
if (dbg_rst = '1') then
r <= ( brk_ctl => "00000",
brk_stat => "000000",
brk_addr0 => x"0000",
brk_addr1 => x"0000"
);
elsif rising_edge(dbg_clk) then
r <= rin;
end if;
end process REGS;
end RTL;
|
bsd-3-clause
|
eamadio/fpgaMSP430
|
fmsp430/per/fmsp_gpio.vhd
|
1
|
33253
|
------------------------------------------------------------------------------
--! Copyright (C) 2009 , Olivier Girard
--
--! Redistribution and use in source and binary forms, with or without
--! modification, are permitted provided that the following conditions
--! are met:
--! * Redistributions of source code must retain the above copyright
--! notice, this list of conditions and the following disclaimer.
--! * Redistributions in binary form must reproduce the above copyright
--! notice, this list of conditions and the following disclaimer in the
--! documentation and/or other materials provided with the distribution.
--! * Neither the name of the authors nor the names of its contributors
--! may be used to endorse or promote products derived from this software
--! without specific prior written permission.
--
--! THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--! AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
--! IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
--! ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
--! LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
--! OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--! SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--! INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--! CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--! ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
--! THE POSSIBILITY OF SUCH DAMAGE
--
------------------------------------------------------------------------------
--
--! @file fmsp_gpio.vhd
--!
--! @brief fpgaMSP430 constant Digital I/O interface
--
--! @author Emmanuel Amadio, [email protected]
--
------------------------------------------------------------------------------
--! @version 1
--! @date: 2017-04-21
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all; --! standard unresolved logic UX01ZWLH-
use ieee.numeric_std.all; --! for the signed, unsigned types and arithmetic ops
use ieee.math_real.all;
use work.fmsp_misc_package.all;
use work.fmsp_per_package.all;
use work.fmsp_functions.all;
entity fmsp_gpio is
generic (
P1_EN : boolean := true; --! Enable Port 1
P2_EN : boolean := true; --! Enable Port 2
P3_EN : boolean := false; --! Enable Port 3
P4_EN : boolean := false; --! Enable Port 4
P5_EN : boolean := false; --! Enable Port 5
P6_EN : boolean := false; --! Enable Port 6
SYNC_P1 : boolean := true; --! Synchronize Port 1 inputs
SYNC_P2 : boolean := true; --! Synchronize Port 2 inputs
SYNC_P3 : boolean := true; --! Synchronize Port 3 inputs
SYNC_P4 : boolean := true; --! Synchronize Port 4 inputs
SYNC_P5 : boolean := true; --! Synchronize Port 5 inputs
SYNC_P6 : boolean := true --! Synchronize Port 6 inputs
);
port (
mclk : in std_logic; --! Main system clock
mrst : in std_logic; --! Main system reset
--! INPUTs
p1_din : in std_logic_vector(7 downto 0); --! Port 1 data input
p2_din : in std_logic_vector(7 downto 0); --! Port 2 data input
p3_din : in std_logic_vector(7 downto 0); --! Port 3 data input
p4_din : in std_logic_vector(7 downto 0); --! Port 4 data input
p5_din : in std_logic_vector(7 downto 0); --! Port 5 data input
p6_din : in std_logic_vector(7 downto 0); --! Port 6 data input
per_addr : in std_logic_vector(13 downto 0); --! Peripheral address
per_din : in std_logic_vector(15 downto 0); --! Peripheral data input
per_en : in std_logic; --! Peripheral enable (high active)
per_we : in std_logic_vector(1 downto 0); --! Peripheral write enable (high active)
--! OUTPUTs
irq_port1 : out std_logic; --! Port 1 interrupt
irq_port2 : out std_logic; --! Port 2 interrupt
p1_dout : out std_logic_vector(7 downto 0); --! Port 1 data output
p1_dout_en : out std_logic_vector(7 downto 0); --! Port 1 data output enable
p1_sel : out std_logic_vector(7 downto 0); --! Port 1 function select
p2_dout : out std_logic_vector(7 downto 0); --! Port 2 data output
p2_dout_en : out std_logic_vector(7 downto 0); --! Port 2 data output enable
p2_sel : out std_logic_vector(7 downto 0); --! Port 2 function select
p3_dout : out std_logic_vector(7 downto 0); --! Port 3 data output
p3_dout_en : out std_logic_vector(7 downto 0); --! Port 3 data output enable
p3_sel : out std_logic_vector(7 downto 0); --! Port 3 function select
p4_dout : out std_logic_vector(7 downto 0); --! Port 4 data output
p4_dout_en : out std_logic_vector(7 downto 0); --! Port 4 data output enable
p4_sel : out std_logic_vector(7 downto 0); --! Port 4 function select
p5_dout : out std_logic_vector(7 downto 0); --! Port 5 data output
p5_dout_en : out std_logic_vector(7 downto 0); --! Port 5 data output enable
p5_sel : out std_logic_vector(7 downto 0); --! Port 5 function select
p6_dout : out std_logic_vector(7 downto 0); --! Port 6 data output
p6_dout_en : out std_logic_vector(7 downto 0); --! Port 6 data output enable
p6_sel : out std_logic_vector(7 downto 0); --! Port 6 function select
per_dout : out std_logic_vector(15 downto 0) --! Peripheral data output
);
end entity fmsp_gpio;
architecture RTL of fmsp_gpio is
--=============================================================================
--! 1) PARAMETER DECLARATION
--=============================================================================
--! Register base address (must be aligned to decoder bit width)
constant BASE_ADDR : std_logic_vector(14 downto 0) := "000000000000000";
--! Decoder bit width (defines how many bits are considered for address decoding)
constant DEC_WD : integer := 7;
--! Register addresses offset
constant LED_CTRL : integer := 0; --! ''h0,
constant P1IN : integer := 32; --! ''h20, --! Port 1
constant P1OUT : integer := 33; --! ''h21,
constant P1DIR : integer := 34; --! ''h22,
constant P1IFG : integer := 35; --! ''h23,
constant P1IES : integer := 36; --! ''h24,
constant P1IE : integer := 37; --! ''h25,
constant P1SEL : integer := 38; --! ''h26,
constant P2IN : integer := 40; --! ''h28, --! Port 2
constant P2OUT : integer := 41; --! ''h29,
constant P2DIR : integer := 42; --! ''h2A,
constant P2IFG : integer := 43; --! ''h2B,
constant P2IES : integer := 44; --! ''h2C,
constant P2IE : integer := 45; --! ''h2D,
constant P2SEL : integer := 46; --! ''h2E,
constant P3IN : integer := 24; --! ''h18, --! Port 3
constant P3OUT : integer := 25; --! ''h19,
constant P3DIR : integer := 26; --! ''h1A,
constant P3SEL : integer := 27; --! ''h1B,
constant P4IN : integer := 28; --! ''h1C, --! Port 4
constant P4OUT : integer := 29; --! ''h1D,
constant P4DIR : integer := 30; --! ''h1E,
constant P4SEL : integer := 31; --! ''h1F,
constant P5IN : integer := 48; --! ''h30, --! Port 5
constant P5OUT : integer := 49; --! ''h31,
constant P5DIR : integer := 50; --! ''h32,
constant P5SEL : integer := 51; --! ''h33,
constant P6IN : integer := 52; --! ''h34, --! Port 6
constant P6OUT : integer := 53; --! ''h35,
constant P6DIR : integer := 54; --! ''h36,
constant P6SEL : integer := 55; --! ''h37;
--! Register one-hot decoder utilities
constant DEC_SZ : integer := (2**DEC_WD);
type fmsp_gpio_in_type is record
p1_din : std_logic_vector(7 downto 0); --! Port 1 data input
p2_din : std_logic_vector(7 downto 0); --! Port 2 data input
p3_din : std_logic_vector(7 downto 0); --! Port 3 data input
p4_din : std_logic_vector(7 downto 0); --! Port 4 data input
p5_din : std_logic_vector(7 downto 0); --! Port 5 data input
p6_din : std_logic_vector(7 downto 0); --! Port 6 data input
per_addr : std_logic_vector(13 downto 0); --! Peripheral address
per_din : std_logic_vector(15 downto 0); --! Peripheral data input
per_en : std_logic; --! Peripheral enable (high active)
per_we : std_logic_vector(1 downto 0); --! Peripheral write enable (high active)
--! From sub modules
p1in : std_logic_vector(7 downto 0); --! Port 1 data input
p2in : std_logic_vector(7 downto 0); --! Port 2 data input
p3in : std_logic_vector(7 downto 0); --! Port 3 data input
p4in : std_logic_vector(7 downto 0); --! Port 4 data input
p5in : std_logic_vector(7 downto 0); --! Port 5 data input
p6in : std_logic_vector(7 downto 0); --! Port 6 data input
end record;
type reg_type is record
p1out : std_logic_vector(7 downto 0);
p1dir : std_logic_vector(7 downto 0);
p1ifg : std_logic_vector(7 downto 0);
p1ies : std_logic_vector(7 downto 0);
p1ie : std_logic_vector(7 downto 0);
p1sel : std_logic_vector(7 downto 0);
p2out : std_logic_vector(7 downto 0);
p2dir : std_logic_vector(7 downto 0);
p2ifg : std_logic_vector(7 downto 0);
p2ies : std_logic_vector(7 downto 0);
p2ie : std_logic_vector(7 downto 0);
p2sel : std_logic_vector(7 downto 0);
p3out : std_logic_vector(7 downto 0);
p3dir : std_logic_vector(7 downto 0);
p3sel : std_logic_vector(7 downto 0);
p4out : std_logic_vector(7 downto 0);
p4dir : std_logic_vector(7 downto 0);
p4sel : std_logic_vector(7 downto 0);
p5out : std_logic_vector(7 downto 0);
p5dir : std_logic_vector(7 downto 0);
p5sel : std_logic_vector(7 downto 0);
p6out : std_logic_vector(7 downto 0);
p6dir : std_logic_vector(7 downto 0);
p6sel : std_logic_vector(7 downto 0);
p1in_dly : std_logic_vector(7 downto 0);
p2in_dly : std_logic_vector(7 downto 0);
end record;
signal d : fmsp_gpio_in_type;
signal r : reg_type := ( p1out => "00000000",
p1dir => "00000000",
p1ifg => "00000000",
p1ies => "00000000",
p1ie => "00000000",
p1sel => "00000000",
p2out => "00000000",
p2dir => "00000000",
p2ifg => "00000000",
p2ies => "00000000",
p2ie => "00000000",
p2sel => "00000000",
p3out => "00000000",
p3dir => "00000000",
p3sel => "00000000",
p4out => "00000000",
p4dir => "00000000",
p4sel => "00000000",
p5out => "00000000",
p5dir => "00000000",
p5sel => "00000000",
p6out => "00000000",
p6dir => "00000000",
p6sel => "00000000",
p1in_dly => "00000000",
p2in_dly => "00000000"
);
signal rin : reg_type;
begin
d.p1_din <= p1_din;
d.p2_din <= p2_din;
d.p3_din <= p3_din;
d.p4_din <= p4_din;
d.p5_din <= p5_din;
d.p6_din <= p6_din;
d.per_addr <= per_addr;
d.per_din <= per_din;
d.per_en <= per_en;
d.per_we <= per_we;
COMB : process (d, r)
variable v : reg_type;
--! Local register selection
variable v_reg_sel : std_logic;
--! Register local address
variable v_reg_addr : std_logic_vector(DEC_WD-2 downto 0);
--! Register address decode
variable v_reg_dec : std_logic_vector((DEC_SZ/2)-1 downto 0);
--! Read/Write probes
variable v_reg_lo_write : std_logic;
variable v_reg_hi_write : std_logic;
variable v_reg_read : std_logic;
--! Read/Write vectors
variable v_reg_wr : std_logic_vector(DEC_SZ-1 downto 0);
variable v_reg_rd : std_logic_vector(DEC_SZ-1 downto 0);
--! P1OUT Register
variable v_p1in : std_logic_vector(7 downto 0);
variable v_p1out_wr : std_logic;
variable v_p1out_nxt : std_logic_vector(7 downto 0);
--! P1DIR Register
variable v_p1dir_wr : std_logic;
variable v_p1dir_nxt : std_logic_vector(7 downto 0);
variable v_p1_dout_en : std_logic_vector(7 downto 0);
--! P1IFG Register
variable v_p1ifg_wr : std_logic;
variable v_p1ifg_nxt : std_logic_vector(7 downto 0);
variable v_p1ifg_set : std_logic_vector(7 downto 0);
--! P1IES Register
variable v_p1ies_wr : std_logic;
variable v_p1ies_nxt : std_logic_vector(7 downto 0);
--! P1IE Register
variable v_p1ie_wr : std_logic;
variable v_p1ie_nxt : std_logic_vector(7 downto 0);
--! P1SEL Register
variable v_p1sel_wr : std_logic;
variable v_p1sel_nxt : std_logic_vector(7 downto 0);
variable v_p1_sel : std_logic_vector(7 downto 0);
--! P2IN Register
variable v_p2in : std_logic_vector(7 downto 0);
--! P2OUT Register
variable v_p2out_wr : std_logic;
variable v_p2out_nxt : std_logic_vector(7 downto 0);
--! P2DIR Register
variable v_p2dir_wr : std_logic;
variable v_p2dir_nxt : std_logic_vector(7 downto 0);
variable v_p2_dout_en : std_logic_vector(7 downto 0);
--! P2IFG Register
variable v_p2ifg_wr : std_logic;
variable v_p2ifg_nxt : std_logic_vector(7 downto 0);
variable v_p2ifg_set : std_logic_vector(7 downto 0);
--! P2IES Register
variable v_p2ies_wr : std_logic;
variable v_p2ies_nxt : std_logic_vector(7 downto 0);
--! P2IE Register
variable v_p2ie_wr : std_logic;
variable v_p2ie_nxt : std_logic_vector(7 downto 0);
--! P2SEL Register
variable v_p2sel_wr : std_logic;
variable v_p2sel_nxt : std_logic_vector(7 downto 0);
variable v_p2_sel : std_logic_vector(7 downto 0);
--! P3OUT Register
variable v_p3in : std_logic_vector(7 downto 0);
variable v_p3out_wr : std_logic;
variable v_p3out_nxt : std_logic_vector(7 downto 0);
--! P3DIR Register
variable v_p3dir_wr : std_logic;
variable v_p3dir_nxt : std_logic_vector(7 downto 0);
variable v_p3_dout_en : std_logic;
--! P3SEL Register
variable v_p3sel_wr : std_logic;
variable v_p3sel_nxt : std_logic_vector(7 downto 0);
variable v_p3_sel : std_logic_vector(7 downto 0);
--! P4OUT Register
variable v_p4in : std_logic_vector(7 downto 0);
variable v_p4out_wr : std_logic;
variable v_p4out_nxt : std_logic_vector(7 downto 0);
--! P4DIR Register
variable v_p4dir_wr : std_logic;
variable v_p4dir_nxt : std_logic_vector(7 downto 0);
variable v_p4_dout_en : std_logic_vector(7 downto 0);
--! P4SEL Register
variable v_p4sel_wr : std_logic;
variable v_p4sel_nxt : std_logic_vector(7 downto 0);
variable v_p4_sel : std_logic_vector(7 downto 0);
--! P5OUT Register
variable v_p5in : std_logic_vector(7 downto 0);
variable v_p5out_wr : std_logic;
variable v_p5out_nxt : std_logic_vector(7 downto 0);
--! P5DIR Register
variable v_p5dir_wr : std_logic;
variable v_p5dir_nxt : std_logic_vector(7 downto 0);
variable v_p5_dout_en : std_logic;
--! P5SEL Register
variable v_p5sel_wr : std_logic;
variable v_p5sel_nxt : std_logic_vector(7 downto 0);
variable v_p5_sel : std_logic_vector(7 downto 0);
--! P6OUT Register
variable v_p6in : std_logic_vector(7 downto 0);
variable v_p6out_wr : std_logic;
variable v_p6out_nxt : std_logic_vector(7 downto 0);
--! P6DIR Register
variable v_p6dir_wr : std_logic;
variable v_p6dir_nxt : std_logic_vector(7 downto 0);
variable v_p6_dout_en : std_logic_vector(7 downto 0);
--! P6SEL Register
variable v_p6sel_wr : std_logic;
variable v_p6sel_nxt : std_logic_vector(7 downto 0);
variable v_p6_sel : std_logic_vector(7 downto 0);
--! 4) INTERRUPT GENERATION
--! Port 1 interrupt
--! Edge detection
variable v_p1in_re : std_logic_vector(7 downto 0);
variable v_p1in_fe : std_logic_vector(7 downto 0);
--! Set interrupt flag
--variable v_p1ifg_set : std_logic;
--! Generate CPU interrupt
variable v_irq_port1 : std_logic;
--! Port 1 interrupt
--------------------
--! Delay input
--! Edge detection
variable v_p2in_re : std_logic_vector(7 downto 0);
variable v_p2in_fe : std_logic_vector(7 downto 0);
--! Set interrupt flag
--variable v_p2ifg_set : std_logic;
--! Generate CPU interrupt
variable v_irq_port2 : std_logic;
--! Data output mux
variable v_p1in_rd : std_logic_vector(15 downto 0);
variable v_p1out_rd : std_logic_vector(15 downto 0);
variable v_p1dir_rd : std_logic_vector(15 downto 0);
variable v_p1ifg_rd : std_logic_vector(15 downto 0);
variable v_p1ies_rd : std_logic_vector(15 downto 0);
variable v_p1ie_rd : std_logic_vector(15 downto 0);
variable v_p1sel_rd : std_logic_vector(15 downto 0);
variable v_p2in_rd : std_logic_vector(15 downto 0);
variable v_p2out_rd : std_logic_vector(15 downto 0);
variable v_p2dir_rd : std_logic_vector(15 downto 0);
variable v_p2ifg_rd : std_logic_vector(15 downto 0);
variable v_p2ies_rd : std_logic_vector(15 downto 0);
variable v_p2ie_rd : std_logic_vector(15 downto 0);
variable v_p2sel_rd : std_logic_vector(15 downto 0);
variable v_p3in_rd : std_logic_vector(15 downto 0);
variable v_p3out_rd : std_logic_vector(15 downto 0);
variable v_p3dir_rd : std_logic_vector(15 downto 0);
variable v_p3sel_rd : std_logic_vector(15 downto 0);
variable v_p4in_rd : std_logic_vector(15 downto 0);
variable v_p4out_rd : std_logic_vector(15 downto 0);
variable v_p4dir_rd : std_logic_vector(15 downto 0);
variable v_p4sel_rd : std_logic_vector(15 downto 0);
variable v_p5in_rd : std_logic_vector(15 downto 0);
variable v_p5out_rd : std_logic_vector(15 downto 0);
variable v_p5dir_rd : std_logic_vector(15 downto 0);
variable v_p5sel_rd : std_logic_vector(15 downto 0);
variable v_p6in_rd : std_logic_vector(15 downto 0);
variable v_p6out_rd : std_logic_vector(15 downto 0);
variable v_p6dir_rd : std_logic_vector(15 downto 0);
variable v_p6sel_rd : std_logic_vector(15 downto 0);
variable v_per_dout : std_logic_vector(15 downto 0);
begin
--! default assignment
v := r;
--! overriding assignments
--============================================================================
--! 2) REGISTER DECODER
--============================================================================
--! Local register selection
if ( d.per_addr(13 downto DEC_WD-1) = BASE_ADDR(14 downto DEC_WD) ) then
v_reg_sel := d.per_en;
else
v_reg_sel := '0';
end if;
--! Register local address
v_reg_addr := d.per_addr(DEC_WD-2 downto 0);
--! Register address decode
v_reg_dec := onehot(v_reg_addr);
--! Read/Write probes
v_reg_lo_write := v_reg_sel and d.per_we(0);
v_reg_hi_write := v_reg_sel and d.per_we(1);
v_reg_read := v_reg_sel and not(d.per_we(0) or d.per_we(1));
--! Read/Write vectors
for i in 0 to (DEC_SZ/2)-1 loop
v_reg_wr((i*2)+0) := v_reg_dec(i) and v_reg_lo_write;
v_reg_wr((i*2)+1) := v_reg_dec(i) and v_reg_hi_write;
v_reg_rd((i*2)+0) := v_reg_dec(i) and v_reg_read;
v_reg_rd((i*2)+1) := v_reg_dec(i) and v_reg_read;
end loop;
--============================================================================
--! 4) INTERRUPT GENERATION
--============================================================================
--! Port 1 interrupt
if (P1_EN = false) then
v_p1in := "00000000";
elsif (SYNC_P1 = true) then
v_p1in := d.p1in;
else
v_p1in := d.p1_din;
end if;
--! Delay input
v.p1in_dly := v_p1in;
--! Edge detection
v_p1in_re := v_p1in and not( r.p1in_dly);
v_p1in_fe := not(v_p1in) and r.p1in_dly;
--! Set interrupt flag
for i in 0 to 7 loop
if (P1_EN = false) then
v_p1ifg_set(i) := '0';
elsif (r.p1ies(i) = '1') then
v_p1ifg_set(i) := v_p1in_fe(i);
else
v_p1ifg_set(i) := v_p1in_re(i);
end if;
end loop;
--! Generate CPU interrupt
if (P1_EN = false) then
v_irq_port1 := '0';
elsif ( (r.p1ie and r.p1ifg) /= "00000000") then
v_irq_port1 := '1';
else
v_irq_port1 := '0';
end if;
--! Port 2 interrupt
if (P2_EN = false) then
v_p2in := "00000000";
elsif (SYNC_P2 = true) then
v_p2in := d.p2in;
else
v_p2in := d.p2_din;
end if;
--! Delay input
v.p2in_dly := v_p2in;
--! Edge detection
v_p2in_re := d.p2in and not( r.p2in_dly);
v_p2in_fe := not(d.p2in) and r.p2in_dly;
--! Set interrupt flag
for i in 0 to 7 loop
if (P2_EN = false) then
v_p2ifg_set(i) := '0';
elsif (r.p2ies(i) = '1') then
v_p2ifg_set(i) := v_p2in_fe(i);
else
v_p2ifg_set(i) := v_p2in_re(i);
end if;
end loop;
--! Generate CPU interrupt
if (P2_EN = false) then
v_irq_port2 := '0';
elsif ( (r.p2ie and r.p2ifg) /= "00000000") then
v_irq_port2 := '1';
else
v_irq_port2 := '0';
end if;
--============================================================================
--! 3) REGISTERS
--============================================================================
--! P1IFG Register
v_p1ifg_wr := v_reg_wr(P1IFG);
v_p1ifg_nxt := byte_per_select_din( P1IFG, d.per_din );
if (P1_EN = false) then
v.p1ifg := "00000000";
elsif (v_p1ies_wr = '1') then
v.p1ifg := v_p1ifg_nxt or v_p1ifg_set;
else
v.p1ifg := r.p1ifg or v_p1ifg_set;
end if;
--! P1IES Register
v_p1ies_wr := v_reg_wr(P1IES);
v_p1ies_nxt := byte_per_select_din( P1IES, d.per_din );
if (P1_EN = false) then
v.p1ies := "00000000";
elsif (v_p1ies_wr = '1') then
v.p1ies := v_p1ies_nxt;
end if;
--! P1IE Register
v_p1ie_wr := v_reg_wr(P1IE);
v_p1ie_nxt := byte_per_select_din( P1IE, d.per_din );
if (P1_EN = false) then
v.p1ie := "00000000";
elsif (v_p1ie_wr = '1') then
v.p1ie := v_p1ie_nxt;
end if;
--! P2IFG Register
v_p2ifg_wr := v_reg_wr(P2IFG);
v_p2ifg_nxt := byte_per_select_din( P2IFG, d.per_din );
if (P2_EN = false) then
v.p2ifg := "00000000";
elsif (v_p2ies_wr = '1') then
v.p2ifg := v_p2ifg_nxt or v_p2ifg_set;
else
v.p2ifg := r.p2ifg or v_p2ifg_set;
end if;
--! P2IES Register
v_p2ies_wr := v_reg_wr(P2IES);
v_p2ies_nxt := byte_per_select_din( P2IES, d.per_din );
if (P2_EN = false) then
v.p2ies := "00000000";
elsif (v_p2ies_wr = '1') then
v.p2ies := v_p2ies_nxt;
end if;
--! P2IE Register
v_p2ie_wr := v_reg_wr(P2IE);
v_p2ie_nxt := byte_per_select_din( P2IE, d.per_din );
if (P2_EN = false) then
v.p2ie := "00000000";
elsif (v_p2ie_wr = '1') then
v.p2ie := v_p2ie_nxt;
end if;
--! P1OUT Register
v_p1out_wr := v_reg_wr(P1OUT);
v_p1out_nxt := byte_per_select_din( P1OUT, d.per_din );
if (P1_EN = false) then
v.p1out := "00000000";
elsif (v_p1out_wr = '1') then
v.p1out := v_p1out_nxt;
end if;
--! P1DIR Register
v_p1dir_wr := v_reg_wr(P1DIR);
v_p1dir_nxt := byte_per_select_din( P1DIR, d.per_din );
if (P1_EN = false) then
v.p1dir := "00000000";
elsif (v_p1dir_wr = '1') then
v.p1dir := v_p1dir_nxt;
end if;
--! P1SEL Register
v_p1sel_wr := v_reg_wr(P1SEL);
v_p1sel_nxt := byte_per_select_din( P1SEL, d.per_din );
if (P1_EN = false) then
v.p1sel := "00000000";
elsif (v_p1sel_wr = '1') then
v.p1sel := v_p1sel_nxt;
end if;
--! P2OUT Register
v_p2out_wr := v_reg_wr(P2OUT);
v_p2out_nxt := byte_per_select_din( P2OUT, d.per_din );
if (P2_EN = false) then
v.p2out := "00000000";
elsif (v_p2out_wr = '1') then
v.p2out := v_p2out_nxt;
end if;
--! P2DIR Register
v_p2dir_wr := v_reg_wr(P2DIR);
v_p2dir_nxt := byte_per_select_din( P2DIR, d.per_din );
if (P2_EN = false) then
v.p2dir := "00000000";
elsif (v_p2dir_wr = '1') then
v.p2dir := v_p2dir_nxt;
end if;
--! P2SEL Register
v_p2sel_wr := v_reg_wr(P2SEL);
v_p2sel_nxt := byte_per_select_din( P2SEL, d.per_din );
if (P2_EN = false) then
v.p2sel := "00000000";
elsif (v_p2sel_wr = '1') then
v.p2sel := v_p2sel_nxt;
end if;
--! P3IN Register
if (P3_EN = false) then
v_p3in := "00000000";
elsif (SYNC_P3 = true) then
v_p3in := d.p3in;
else
v_p3in := d.p3_din;
end if;
--! P3OUT Register
v_p3out_wr := v_reg_wr(P3OUT);
v_p3out_nxt := byte_per_select_din( P3OUT, d.per_din );
if (P3_EN = false) then
v.p3out := "00000000";
elsif (v_p3out_wr = '1') then
v.p3out := v_p3out_nxt;
end if;
--! P3DIR Register
v_p3dir_wr := v_reg_wr(P3DIR);
v_p3dir_nxt := byte_per_select_din( P3DIR, d.per_din );
if (P3_EN = false) then
v.p3dir := "00000000";
elsif (v_p3dir_wr = '1') then
v.p3dir := v_p3dir_nxt;
end if;
--! P3SEL Register
v_p3sel_wr := v_reg_wr(P3SEL);
v_p3sel_nxt := byte_per_select_din( P3SEL, d.per_din );
if (P3_EN = false) then
v.p3sel := "00000000";
elsif (v_p3sel_wr = '1') then
v.p3sel := v_p3sel_nxt;
end if;
--! P4IN Register
if (P4_EN = false) then
v_p4in := "00000000";
elsif (SYNC_P4 = true) then
v_p4in := d.p4in;
else
v_p4in := d.p4_din;
end if;
--! P4OUT Register
v_p4out_wr := v_reg_wr(P4OUT);
v_p4out_nxt := byte_per_select_din( P4OUT, d.per_din );
if (P4_EN = false) then
v.p4out := "00000000";
elsif (v_p4out_wr = '1') then
v.p4out := v_p4out_nxt;
end if;
--! P4DIR Register
v_p4dir_wr := v_reg_wr(P4DIR);
v_p4dir_nxt := byte_per_select_din( P4DIR, d.per_din );
if (P4_EN = false) then
v.p4dir := "00000000";
elsif (v_p4dir_wr = '1') then
v.p4dir := v_p4dir_nxt;
end if;
--! P4SEL Register
v_p4sel_wr := v_reg_wr(P4SEL);
v_p4sel_nxt := byte_per_select_din( P4SEL, d.per_din );
if (P4_EN = false) then
v.p4sel := "00000000";
elsif (v_p4sel_wr = '1') then
v.p4sel := v_p4sel_nxt;
end if;
--! P5IN Register
if (P5_EN = false) then
v_p5in := "00000000";
elsif (SYNC_P5 = true) then
v_p5in := d.p5in;
else
v_p5in := d.p5_din;
end if;
--! P5OUT Register
v_p5out_wr := v_reg_wr(P5OUT);
v_p5out_nxt := byte_per_select_din( P5OUT, d.per_din );
if (P5_EN = false) then
v.p5out := "00000000";
elsif (v_p5out_wr = '1') then
v.p5out := v_p5out_nxt;
end if;
--! P5DIR Register
v_p5dir_wr := v_reg_wr(P5DIR);
v_p5dir_nxt := byte_per_select_din( P5DIR, d.per_din );
if (P5_EN = false) then
v.p5dir := "00000000";
elsif (v_p5dir_wr = '1') then
v.p5dir := v_p5dir_nxt;
end if;
--! P5SEL Register
v_p5sel_wr := v_reg_wr(P5SEL);
v_p5sel_nxt := byte_per_select_din( P5SEL, d.per_din );
if (P5_EN = false) then
v.p5sel := "00000000";
elsif (v_p5sel_wr = '1') then
v.p5sel := v_p5sel_nxt;
end if;
--! P6IN Register
if (P6_EN = false) then
v_p6in := "00000000";
elsif (SYNC_P6 = true) then
v_p6in := d.p6in;
else
v_p6in := d.p6_din;
end if;
--! P6OUT Register
v_p6out_wr := v_reg_wr(P6OUT);
v_p6out_nxt := byte_per_select_din( P6OUT, d.per_din );
if (P6_EN = false) then
v.p6out := "00000000";
elsif (v_p6out_wr = '1') then
v.p6out := v_p6out_nxt;
end if;
--! P6DIR Register
v_p6dir_wr := v_reg_wr(P6DIR);
v_p6dir_nxt := byte_per_select_din( P6DIR, d.per_din );
if (P6_EN = false) then
v.p6dir := "00000000";
elsif (v_p6dir_wr = '1') then
v.p6dir := v_p6dir_nxt;
end if;
--! P6SEL Register
v_p6sel_wr := v_reg_wr(P6SEL);
v_p6sel_nxt := byte_per_select_din( P6SEL, d.per_din );
if (P6_EN = false) then
v.p6sel := "00000000";
elsif (v_p6sel_wr = '1') then
v.p6sel := v_p6sel_nxt;
end if;
--============================================================================
--! 5) DATA OUTPUT GENERATION
--============================================================================
--! Data output mux
v_p1in_rd := byte_per_select_dout( P1IN, v_reg_rd, v_p1in );
v_p1out_rd := byte_per_select_dout( P1OUT, v_reg_rd, r.p1out );
v_p1dir_rd := byte_per_select_dout( P1DIR, v_reg_rd, r.p1dir );
v_p1ifg_rd := byte_per_select_dout( P1IFG, v_reg_rd, r.p1ifg );
v_p1ies_rd := byte_per_select_dout( P1IES, v_reg_rd, r.p1ies );
v_p1ie_rd := byte_per_select_dout( P1IE, v_reg_rd, r.p1ie );
v_p1sel_rd := byte_per_select_dout( P1SEL, v_reg_rd, r.p1sel );
v_p2in_rd := byte_per_select_dout( P2IN, v_reg_rd, v_p2in );
v_p2out_rd := byte_per_select_dout( P2OUT, v_reg_rd, r.p2out );
v_p2dir_rd := byte_per_select_dout( P2DIR, v_reg_rd, r.p2dir );
v_p2ifg_rd := byte_per_select_dout( P2IFG, v_reg_rd, r.p2ifg );
v_p2ies_rd := byte_per_select_dout( P2IES, v_reg_rd, r.p2ies );
v_p2ie_rd := byte_per_select_dout( P2IE, v_reg_rd, r.p2ie );
v_p2sel_rd := byte_per_select_dout( P2SEL, v_reg_rd, r.p2sel );
v_p3in_rd := byte_per_select_dout( P3IN, v_reg_rd, v_p3in );
v_p3out_rd := byte_per_select_dout( P3OUT, v_reg_rd, r.p3out );
v_p3dir_rd := byte_per_select_dout( P3DIR, v_reg_rd, r.p3dir );
v_p3sel_rd := byte_per_select_dout( P3SEL, v_reg_rd, r.p3sel );
v_p4in_rd := byte_per_select_dout( P4IN, v_reg_rd, v_p4in );
v_p4out_rd := byte_per_select_dout( P4OUT, v_reg_rd, r.p4out );
v_p4dir_rd := byte_per_select_dout( P4DIR, v_reg_rd, r.p4dir );
v_p4sel_rd := byte_per_select_dout( P4SEL, v_reg_rd, r.p4sel );
v_p5in_rd := byte_per_select_dout( P5IN, v_reg_rd, v_p5in );
v_p5out_rd := byte_per_select_dout( P5OUT, v_reg_rd, r.p5out );
v_p5dir_rd := byte_per_select_dout( P5DIR, v_reg_rd, r.p5dir );
v_p5sel_rd := byte_per_select_dout( P5SEL, v_reg_rd, r.p5sel );
v_p6in_rd := byte_per_select_dout( P6IN, v_reg_rd, v_p6in );
v_p6out_rd := byte_per_select_dout( P6OUT, v_reg_rd, r.p6out );
v_p6dir_rd := byte_per_select_dout( P6DIR, v_reg_rd, r.p6dir );
v_p6sel_rd := byte_per_select_dout( P6SEL, v_reg_rd, r.p6sel );
v_per_dout := v_p1in_rd
or v_p1out_rd
or v_p1dir_rd
or v_p1ifg_rd
or v_p1ies_rd
or v_p1ie_rd
or v_p1sel_rd
or v_p2in_rd
or v_p2out_rd
or v_p2dir_rd
or v_p2ifg_rd
or v_p2ies_rd
or v_p2ie_rd
or v_p2sel_rd
or v_p3in_rd
or v_p3out_rd
or v_p3dir_rd
or v_p3sel_rd
or v_p4in_rd
or v_p4out_rd
or v_p4dir_rd
or v_p4sel_rd
or v_p5in_rd
or v_p5out_rd
or v_p5dir_rd
or v_p5sel_rd
or v_p6in_rd
or v_p6out_rd
or v_p6dir_rd
or v_p6sel_rd;
--! drive register inputs
rin <= v;
--! drive module outputs
irq_port1 <= v_irq_port1; --! Port 1 interrupt
irq_port2 <= v_irq_port2; --! Port 2 interrupt
p1_dout <= r.p1out; --! Port 1 data output
p1_dout_en <= r.p1dir; --! Port 1 data output enable
p1_sel <= r.p1sel; --! Port 1 function select
p2_dout <= r.p2out; --! Port 2 data output
p2_dout_en <= r.p2dir; --! Port 2 data output enable
p2_sel <= r.p2sel; --! Port 2 function select
p3_dout <= r.p3out; --! Port 3 data output
p3_dout_en <= r.p3dir; --! Port 3 data output enable
p3_sel <= r.p3sel; --! Port 3 function select
p4_dout <= r.p4out; --! Port 4 data output
p4_dout_en <= r.p4dir; --! Port 4 data output enable
p4_sel <= r.p4sel; --! Port 4 function select
p5_dout <= r.p5out; --! Port 5 data output
p5_dout_en <= r.p5dir; --! Port 5 data output enable
p5_sel <= r.p5sel; --! Port 5 function select
p6_dout <= r.p6out; --! Port 6 data output
p6_dout_en <= r.p6dir; --! Port 6 data output enable
p6_sel <= r.p6sel; --! Port 6 function select
per_dout <= v_per_dout; --! Peripheral data output
end process COMB;
REGS : process (mclk,mrst)
begin
if (mrst = '1') then
r.p1out <= "00000000";
r.p1dir <= "00000000";
r.p1ifg <= "00000000";
r.p1ies <= "00000000";
r.p1ie <= "00000000";
r.p1sel <= "00000000";
r.p2out <= "00000000";
r.p2dir <= "00000000";
r.p2ifg <= "00000000";
r.p2ies <= "00000000";
r.p2ie <= "00000000";
r.p2sel <= "00000000";
r.p3out <= "00000000";
r.p3dir <= "00000000";
r.p3sel <= "00000000";
r.p4out <= "00000000";
r.p4dir <= "00000000";
r.p4sel <= "00000000";
r.p5out <= "00000000";
r.p5dir <= "00000000";
r.p5sel <= "00000000";
r.p6out <= "00000000";
r.p6dir <= "00000000";
r.p6sel <= "00000000";
r.p1in_dly <= "00000000";
r.p2in_dly <= "00000000";
elsif rising_edge(mclk) then
r <= rin;
end if;
end process REGS;
p1_in_sync : for i in 0 to 7 generate
sync_cell_p1in : fmsp_sync_cell
port map(
clk => mclk,
rst => mrst,
data_in => p1_din(i),
data_out => d.p1in(i)
);
end generate;
p2_in_sync : for i in 0 to 7 generate
sync_cell_p2in : fmsp_sync_cell
port map(
clk => mclk,
rst => mrst,
data_in => p2_din(i),
data_out => d.p2in(i)
);
end generate;
p3_in_sync : for i in 0 to 7 generate
sync_cell_p3in : fmsp_sync_cell
port map(
clk => mclk,
rst => mrst,
data_in => p3_din(i),
data_out => d.p3in(i)
);
end generate;
p4_in_sync : for i in 0 to 7 generate
sync_cell_p4in : fmsp_sync_cell
port map(
clk => mclk,
rst => mrst,
data_in => p4_din(i),
data_out => d.p4in(i)
);
end generate;
p5_in_sync : for i in 0 to 7 generate
sync_cell_p5in : fmsp_sync_cell
port map(
clk => mclk,
rst => mrst,
data_in => p5_din(i),
data_out => d.p5in(i)
);
end generate;
p6_in_sync : for i in 0 to 7 generate
sync_cell_p6in : fmsp_sync_cell
port map(
clk => mclk,
rst => mrst,
data_in => p6_din(i),
data_out => d.p6in(i)
);
end generate;
end RTL; --! fmsp_gpio
|
bsd-3-clause
|
loa-org/loa-hdl
|
modules/utils/tb/fractional_clock_divider_tb.vhd
|
1
|
523
|
library ieee;
use ieee.std_logic_1164.all;
use work.utils_pkg.all;
entity fractional_clock_divider_tb is
end fractional_clock_divider_tb;
architecture tb of fractional_clock_divider_tb is
signal clk : std_logic := '0';
signal output : std_logic;
begin
clk <= not clk after 10 NS; -- 50 Mhz clock
uut : fractional_clock_divider
generic map (
MUL => 41,
DIV => 31250,
WIDTH => 16 )
port map(
clk_out_p => output,
clk => clk);
end tb;
|
bsd-3-clause
|
loa-org/loa-hdl
|
modules/signalprocessing/hdl/signalprocessing_pkg.vhd
|
2
|
6015
|
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.bus_pkg.all;
use work.adc_ltc2351_pkg.all;
-------------------------------------------------------------------------------
package signalprocessing_pkg is
constant CALC_WIDTH : natural := 18; -- Width of all calculations.
constant INPUT_WIDTH : natural := 14; -- Width of ADC values
-- All calculations are based on that type:
subtype goertzel_data_type is signed(CALC_WIDTH-1 downto 0);
-- The result of the Goertzel Algorithm are always a pair of two values
type goertzel_result_type is array (1 downto 0) of goertzel_data_type;
-- The result for more channels and frequencies:
type goertzel_results_type is array (natural range <>, natural range <>) of goertzel_result_type;
-- One input to the algorithm.
subtype goertzel_input_type is signed(INPUT_WIDTH-1 downto 0);
-- The input for many different channels
type goertzel_inputs_type is array (natural range <>) of goertzel_input_type;
-- One goertzel coefficient corresponds to a certain frequency.
subtype goertzel_coef_type is signed(CALC_WIDTH-1 downto 0);
-- The input for different frequencies
type goertzel_coefs_type is array (natural range <>) of goertzel_coef_type;
component goertzel
generic (
Q : natural;
SAMPLES : natural
);
port (
clk : in std_logic;
coef_p : in unsigned(17 downto 0);
start_p : in std_logic;
adc_value_p : in signed(13 downto 0);
result_p : out goertzel_result_type;
done_p : out std_logic
);
end component;
component goertzel_pipelined
generic (
Q : natural;
CHANNELS : natural;
FREQUENCIES : natural;
SAMPLES : natural);
port (
coefs_p : in goertzel_coefs_type;
inputs_p : in goertzel_inputs_type;
start_p : in std_logic;
results_p : out goertzel_results_type;
done_p : out std_logic;
clk : in std_logic);
end component;
----------------------------------------------------------------------------
-- New version, consists of pipeline, muxes and control_unit
----------------------------------------------------------------------------
component goertzel_pipeline is
generic (
Q : natural);
port (
coef_p : in goertzel_coef_type;
input_p : in goertzel_input_type;
delay_p : in goertzel_result_type;
result_p : out goertzel_result_type;
clk : in std_logic);
end component goertzel_pipeline;
component goertzel_muxes is
generic (
CHANNELS : positive;
FREQUENCIES : positive);
port (
mux_delay1_p : in std_logic;
mux_delay2_p : in std_logic;
mux_coef : in natural range FREQUENCIES-1 downto 0;
mux_input : in natural range CHANNELS-1 downto 0;
bram_data : in goertzel_result_type;
coefs_p : in goertzel_coefs_type;
inputs_p : in goertzel_inputs_type;
delay1_p : out goertzel_data_type;
delay2_p : out goertzel_data_type;
coef_p : out goertzel_coef_type;
input_p : out goertzel_input_type);
end component goertzel_muxes;
component goertzel_control_unit is
generic (
SAMPLES : positive;
FREQUENCIES : positive;
CHANNELS : positive);
port (
start_p : in std_logic;
ready_p : out std_logic := '0';
bram_addr_p : out std_logic_vector(7 downto 0) := (others => '0');
bram_we_p : out std_logic := '0';
mux_delay1_p : out std_logic := '0';
mux_delay2_p : out std_logic := '0';
mux_coef_p : out natural range FREQUENCIES-1 downto 0 := 0;
mux_input_p : out natural range CHANNELS-1 downto 0 := 0;
clk : in std_logic);
end component goertzel_control_unit;
component goertzel_pipelined_v2 is
generic (
FREQUENCIES : positive;
CHANNELS : positive;
SAMPLES : positive;
Q : positive);
port (
start_p : in std_logic;
bram_addr_p : out std_logic_vector(7 downto 0);
bram_data_i : in std_logic_vector(35 downto 0);
bram_data_o : out std_logic_vector(35 downto 0);
bram_we_p : out std_logic;
ready_p : out std_logic;
enable_p : in std_logic;
coefs_p : in goertzel_coefs_type(FREQUENCIES-1 downto 0);
inputs_p : in goertzel_inputs_type(CHANNELS-1 downto 0);
clk : in std_logic);
end component goertzel_pipelined_v2;
----------------------------------------------------------------------------
-- Helpers
----------------------------------------------------------------------------
constant TIMESTAMP_WIDTH : natural := 48; -- 2**48 - 1 * 20 us = 65 days. This counter will not overflow.
subtype timestamp_type is signed(TIMESTAMP_WIDTH-1 downto 0);
component timestamp_generator is
port (
timestamp_o_p : out timestamp_type;
clk : in std_logic);
end component timestamp_generator;
component timestamp_taker is
generic (
BASE_ADDRESS : integer);
port (
timestamp_i_p : in timestamp_type;
trigger_i_p : in std_logic;
bank_x_i_p : in std_logic;
bank_y_i_p : in std_logic;
bus_o : out busdevice_out_type;
bus_i : in busdevice_in_type;
clk : in std_logic);
end component;
end signalprocessing_pkg;
|
bsd-3-clause
|
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