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stringlengths 6
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stringlengths 1
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stringlengths 0
1.04M
⌀ | license
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values |
|---|---|---|---|---|---|
BBN-Q/APS2-Comms
|
test/IPv4_packet_pkg.vhd
|
1
|
8164
|
-- Package for handling IPv4 headers, UDP and TCP packets
--
-- Original author: Colm Ryan
-- Copyright 2015,2016 Raytheon BBN Technologies
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.ethernet_frame_pkg.byte_array;
package IPv4_packet_pkg is
subtype IPv4_addr_t is byte_array(0 to 3);
function header_checksum(header : byte_array) return std_logic_vector;
function ipv4_header(
protocol : std_logic_vector(7 downto 0);
packet_length : natural;
src_IP : IPv4_addr_t;
dest_IP : IPv4_addr_t
) return byte_array;
function udp_checksum(packet : byte_array) return std_logic_vector;
function udp_packet (
src_IP : IPv4_addr_t;
dest_IP : IPv4_addr_t;
src_port : std_logic_vector(15 downto 0);
dest_port : std_logic_vector(15 downto 0);
payload : byte_array
) return byte_array;
function tcp_checksum(packet : byte_array) return std_logic_vector;
function tcp_packet (
src_IP : IPv4_addr_t;
dest_IP : IPv4_addr_t;
src_port : std_logic_vector(15 downto 0);
dest_port : std_logic_vector(15 downto 0);
seq_num : natural;
ack_num : natural;
syn : std_logic;
ack : std_logic;
payload : byte_array
) return byte_array;
end IPv4_packet_pkg;
package body IPv4_packet_pkg is
function header_checksum(header : byte_array) return std_logic_vector is
variable sum : unsigned(31 downto 0) := (others => '0');
variable checksum : std_logic_vector(15 downto 0);
variable tmp : std_logic_vector(15 downto 0);
begin
--Sum header
for ct in 0 to 9 loop
--For some reason Vivado can't infer this as one line
-- sum := sum + unsigned(header(2*ct) & header(2*ct+1))
tmp := header(2*ct) & header(2*ct+1);
sum := sum + unsigned(tmp);
end loop;
--Fold back in the carry
checksum := std_logic_vector(sum(15 downto 0) + sum(31 downto 16));
--Return one's complement
return not checksum;
end header_checksum;
function ipv4_header(
protocol : std_logic_vector(7 downto 0);
packet_length : natural;
src_IP : IPv4_addr_t;
dest_IP : IPv4_addr_t
) return byte_array is
variable header : byte_array(0 to 19);
variable len : unsigned(15 downto 0);
variable checksum : std_logic_vector(15 downto 0);
variable idx : natural := 0;
begin
header(0) := x"45"; --version and header length
header(1) := x"00"; --type of service
len := to_unsigned(packet_length, 16);
header(2) := std_logic_vector(len(15 downto 8));
header(3) := std_logic_vector(len(7 downto 0));
header(4) := x"ba"; header(5) := x"ad"; -- identification
header(6) := x"00"; header(7) := x"00"; --flags and fragment
header(8) := x"80"; --time to live
header(9) := protocol; --protocol
header(10) := x"00"; header(11) := x"00"; --checksum
idx := 12;
--source IP
for ct in 0 to 3 loop
header(idx) := src_IP(ct);
idx := idx + 1;
end loop;
--destination IP
for ct in 0 to 3 loop
header(idx) := dest_IP(ct);
idx := idx + 1;
end loop;
--Calculate checksum and insert it
checksum := header_checksum(header);
header(10) := checksum(15 downto 8);
header(11) := checksum(7 downto 0);
return header;
end ipv4_header;
function udp_checksum(packet : byte_array) return std_logic_vector is
variable sum : unsigned(31 downto 0) := (others => '0');
variable checksum : std_logic_vector(15 downto 0);
variable tmp : std_logic_vector(15 downto 0);
variable udp_length : natural;
begin
--Extract pseudo packet header
--source and dest IP
for ct in 0 to 3 loop
tmp := packet(12 + 2*ct) & packet(12 + 2*ct + 1);
sum := sum + unsigned(tmp);
end loop;
--Protocol 0x0011
sum := sum + to_unsigned(17, 32);
--UDP length
tmp := packet(24) & packet(25);
sum := sum + unsigned(tmp);
udp_length := to_integer(unsigned(tmp));
for ct in 0 to udp_length/2 - 1 loop
tmp := packet(20 + 2*ct) & packet(20 + 2*ct + 1);
sum := sum + unsigned(tmp);
end loop;
--Fold back in carry
checksum := std_logic_vector(sum(15 downto 0) + sum(31 downto 16));
--return one's complement
return not checksum;
end udp_checksum;
function udp_packet (
src_IP : IPv4_addr_t;
dest_IP : IPv4_addr_t;
src_port : std_logic_vector(15 downto 0);
dest_port : std_logic_vector(15 downto 0);
payload : byte_array
) return byte_array is
variable packet_length : natural := 20 + 8 + payload'length; --IPv4 header + UDP header
variable len : unsigned(15 downto 0);
variable checksum : std_logic_vector(15 downto 0);
variable packet : byte_array(0 to packet_length-1);
begin
--IPv4 header
packet(0 to 19) := ipv4_header(x"11", packet_length, src_IP, dest_IP);
--UDP source and destination port
packet(20) := src_port(15 downto 8);
packet(21) := src_port(7 downto 0);
packet(22) := dest_port(15 downto 8);
packet(23) := dest_port(7 downto 0);
--UDP packet length
len := to_unsigned(8 + payload'length, 16);
packet(24) := std_logic_vector(len(15 downto 8));
packet(25) := std_logic_vector(len(7 downto 0));
--checksum
packet(26) := x"00";
packet(27) := x"00";
--start after IPv4 + UDP header
for ct in 0 to payload'high loop
packet(28+ct) := payload(ct);
end loop;
--Go back and fill in checksum
checksum := udp_checksum(packet);
packet(26) := checksum(15 downto 8);
packet(27) := checksum(7 downto 0);
return packet;
end udp_packet;
function tcp_checksum(packet : byte_array) return std_logic_vector is
variable sum : unsigned(31 downto 0) := (others => '0');
variable checksum : std_logic_vector(15 downto 0);
variable tmp : std_logic_vector(15 downto 0);
variable tcp_length : natural;
begin
--Extract pseudo packet header
--source and dest IP
for ct in 0 to 3 loop
tmp := packet(12 + 2*ct) & packet(12 + 2*ct + 1);
sum := sum + unsigned(tmp);
end loop;
--Protocol 0x0006
sum := sum + to_unsigned(6, 32);
--tcp length - subtract off ipv4 header (20 bytes)
tcp_length := packet'length - 20;
sum := sum + to_unsigned(tcp_length, 32);
for ct in 0 to tcp_length/2 - 1 loop
tmp := packet(20 + 2*ct) & packet(20 + 2*ct + 1);
sum := sum + unsigned(tmp);
end loop;
--Fold back in carry
checksum := std_logic_vector(sum(15 downto 0) + sum(31 downto 16));
--return one's complement
return not checksum;
end tcp_checksum;
function tcp_packet (
src_IP : IPv4_addr_t;
dest_IP : IPv4_addr_t;
src_port : std_logic_vector(15 downto 0);
dest_port : std_logic_vector(15 downto 0);
seq_num : natural;
ack_num : natural;
syn : std_logic;
ack : std_logic;
payload : byte_array
) return byte_array is
variable packet_length : natural := 20 + 20 + payload'length; --IPv4 header + TCP header
variable len : unsigned(15 downto 0);
variable checksum : std_logic_vector(15 downto 0);
variable packet : byte_array(0 to packet_length-1);
variable num : std_logic_vector(31 downto 0);
begin
--IPv4 header
packet(0 to 19) := ipv4_header(x"06", packet_length, src_IP, dest_IP);
--TCP source and destination port
packet(20) := src_port(15 downto 8);
packet(21) := src_port(7 downto 0);
packet(22) := dest_port(15 downto 8);
packet(23) := dest_port(7 downto 0);
--sequence number
num := std_logic_vector(to_unsigned(seq_num, 32));
packet(24) := num(31 downto 24);
packet(25) := num(23 downto 16);
packet(26) := num(15 downto 8);
packet(27) := num(7 downto 0);
--ack number
num := std_logic_vector(to_unsigned(ack_num, 32));
packet(28) := num(31 downto 24);
packet(29) := num(23 downto 16);
packet(30) := num(15 downto 8);
packet(31) := num(7 downto 0);
packet(32) := x"50"; --data offset
--flags
if payload'length > 0 then
packet(33) := "000" & ack & "00" & syn & "0";
else
packet(33) := "000" & ack & "10" & syn & "0";
end if;
--window size
packet(34) := x"08";
packet(35) := x"00";
--checksum
packet(36) := x"00";
packet(37) := x"00";
--urgent pointer
packet(38) := x"00"; packet(39) := x"00";
for ct in 0 to payload'high loop
packet(40+ct) := payload(ct);
end loop;
--Go back and fill in checksum
checksum := tcp_checksum(packet);
packet(36) := checksum(15 downto 8);
packet(37) := checksum(7 downto 0);
return packet;
end tcp_packet;
end package body;
|
mpl-2.0
|
BBN-Q/APS2-TDM
|
src/PWMA8.vhd
|
1
|
628
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity PWMA8 is
port
(
CLK : in std_logic;
RESET : in std_logic;
DIN : in std_logic_vector (7 downto 0) := "00000000";
PWM_OUT : out std_logic
);
end PWMA8;
architecture behavior of PWMA8 is
signal PWM_Accumulator : std_logic_vector(8 downto 0);
begin
process(CLK, RESET)
begin
if RESET = '1' then
PWM_Accumulator <= (others => '0');
elsif rising_edge(CLK) then
PWM_Accumulator <= ("0" & PWM_Accumulator(7 downto 0)) + ("0" & DIN);
end if;
end process;
PWM_OUT <= PWM_Accumulator(8);
end behavior;
|
mpl-2.0
|
BBN-Q/APS2-TDM
|
src/TriggerOutLogic.vhd
|
1
|
3308
|
-- TriggerOutLogic.vhd
--
-- Serializes the triggers written to the input FIFO by the User Logic.
-- The FIFO allows the trigger output logic and the User Logic clock to have independent clocks.
--
-- REVISIONS
--
-- 3/6/2014 CRJ
-- Created
--
-- 7/30/2014 CRJ
-- Updated comments
--
-- 7/31/2014 CRJ
-- Modified to allow use of I/O buffer for loopback
--
-- 8/5/2014 CRJ
-- Unmodified
--
-- 8/28/2014 CRJ
-- Changed back to 0xF0 clock, since now bit slipping in logic versus the input cell
--
-- END REVISIONS
--
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity TriggerOutLogic is
port
(
-- These clocks are usually generated from SYS_MMCM.
CLK_100MHZ : in std_logic; -- 100 MHz trigger output serial clock, must be from same MMCM as CLK_400MHZ
CLK_400MHZ : in std_logic; -- 400 MHz DDR serial output clock
RESET : in std_logic; -- Asynchronous reset for the trigger logic
TRIG_TX : in std_logic_vector(7 downto 0); -- Current trigger value, synchronous to CLK_100MHZ
TRIG_VALID : in std_logic; -- Valid flag for TRIG_TX
TRIG_CLKP : out std_logic; -- 100MHz Serial Clock
TRIG_CLKN : out std_logic;
TRIG_DATP : out std_logic; -- 800 Mbps Serial Data
TRIG_DATN : out std_logic
);
end TriggerOutLogic;
architecture behavior of TriggerOutLogic is
signal ClkOutP : STD_LOGIC_VECTOR(0 DOWNTO 0);
signal ClkOutN : STD_LOGIC_VECTOR(0 DOWNTO 0);
signal DatOutP : STD_LOGIC_VECTOR(0 DOWNTO 0);
signal DatOutN : STD_LOGIC_VECTOR(0 DOWNTO 0);
signal DataOut : STD_LOGIC_VECTOR(1 DOWNTO 0);
signal SerTrigIn : std_logic_vector(7 downto 0);
signal SerTrigOut : std_logic_vector(7 downto 0);
signal SerDatOut : std_logic_vector(15 downto 0);
signal dTRIG_VALID : std_logic;
begin
-- Connect serial output vectors to output pins
TRIG_CLKP <= ClkOutP(0);
TRIG_CLKN <= ClkOutN(0);
TRIG_DATP <= DatOutP(0);
TRIG_DATN <= DatOutN(0);
-- Data sent externally LSB first, because the SelectIO wizard IP internally
-- assigns the LSB to D1 of the OSERDESE2.
-- Fixed 0xF0 clock pattern.
SCLK1 : entity work.SEROUT8
port map
(
data_out_to_pins_p => ClkOutP,
data_out_to_pins_n => ClkOutN,
clk_in => CLK_400MHZ,
clk_div_in => CLK_100MHZ,
data_out_from_device => "11110000", -- Fixed clock data pattern, sent LSB first.
io_reset => RESET
);
SDAT1 : entity work.SEROUT8
port map
(
data_out_to_pins_p => DatOutP,
data_out_to_pins_n => DatOutN,
clk_in => CLK_400MHZ,
clk_div_in => CLK_100MHZ,
data_out_from_device => SerTrigOut, -- Trigger Byte
io_reset => RESET
);
-- One level of input data pipelining to allow for easier routing
process(CLK_100MHZ, RESET)
begin
if RESET = '1' then
SerTrigIn <= (others => '0');
dTRIG_VALID <= '0';
elsif rising_edge(CLK_100MHZ) then
SerTrigIn <= TRIG_TX;
dTRIG_VALID <= TRIG_VALID;
end if;
end process;
-- Only present non-zero data when there is a valid input
-- The output is ALWAYS writing. When there are not triggers, it writes 0xFF
SerTrigOut <= SerTrigIn when dTRIG_VALID = '1' else x"ff";
end behavior;
|
mpl-2.0
|
YosysHQ/nextpnr
|
machxo2/examples/prims.vhd
|
2
|
331
|
library ieee;
use ieee.std_logic_1164.all;
-- We don't have VHDL primitives yet, so declare them in examples for now.
package components is
component OSCH
generic (
NOM_FREQ : string := "2.08"
);
port(
STDBY : in std_logic;
OSC : out std_logic;
SEDSTDBY : out std_logic
);
end component;
end components;
|
isc
|
0gajun/mal
|
vhdl/step9_try.vhdl
|
11
|
16609
|
entity step9_try is
end entity step9_try;
library STD;
use STD.textio.all;
library WORK;
use WORK.pkg_readline.all;
use WORK.types.all;
use WORK.printer.all;
use WORK.reader.all;
use WORK.env.all;
use WORK.core.all;
architecture test of step9_try is
shared variable repl_env: env_ptr;
procedure mal_READ(str: in string; ast: out mal_val_ptr; err: out mal_val_ptr) is
begin
read_str(str, ast, err);
end procedure mal_READ;
procedure is_pair(ast: inout mal_val_ptr; pair: out boolean) is
begin
pair := is_sequential_type(ast.val_type) and ast.seq_val'length > 0;
end procedure is_pair;
procedure quasiquote(ast: inout mal_val_ptr; result: out mal_val_ptr) is
variable ast_pair, a0_pair: boolean;
variable seq: mal_seq_ptr;
variable a0, rest: mal_val_ptr;
begin
is_pair(ast, ast_pair);
if not ast_pair then
seq := new mal_seq(0 to 1);
new_symbol("quote", seq(0));
seq(1) := ast;
new_seq_obj(mal_list, seq, result);
return;
end if;
a0 := ast.seq_val(0);
if a0.val_type = mal_symbol and a0.string_val.all = "unquote" then
result := ast.seq_val(1);
else
is_pair(a0, a0_pair);
if a0_pair and a0.seq_val(0).val_type = mal_symbol and a0.seq_val(0).string_val.all = "splice-unquote" then
seq := new mal_seq(0 to 2);
new_symbol("concat", seq(0));
seq(1) := a0.seq_val(1);
seq_drop_prefix(ast, 1, rest);
quasiquote(rest, seq(2));
new_seq_obj(mal_list, seq, result);
else
seq := new mal_seq(0 to 2);
new_symbol("cons", seq(0));
quasiquote(a0, seq(1));
seq_drop_prefix(ast, 1, rest);
quasiquote(rest, seq(2));
new_seq_obj(mal_list, seq, result);
end if;
end if;
end procedure quasiquote;
-- Forward declaration
procedure EVAL(in_ast: inout mal_val_ptr; in_env: inout env_ptr; result: out mal_val_ptr; err: out mal_val_ptr);
procedure apply_func(fn: inout mal_val_ptr; args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr);
procedure is_macro_call(ast: inout mal_val_ptr; env: inout env_ptr; is_macro: out boolean) is
variable f, env_err: mal_val_ptr;
begin
is_macro := false;
if ast.val_type = mal_list and
ast.seq_val'length > 0 and
ast.seq_val(0).val_type = mal_symbol then
env_get(env, ast.seq_val(0), f, env_err);
if env_err = null and f /= null and
f.val_type = mal_fn and f.func_val.f_is_macro then
is_macro := true;
end if;
end if;
end procedure is_macro_call;
procedure macroexpand(in_ast: inout mal_val_ptr; env: inout env_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable ast, macro_fn, call_args, macro_err: mal_val_ptr;
variable is_macro: boolean;
begin
ast := in_ast;
is_macro_call(ast, env, is_macro);
while is_macro loop
env_get(env, ast.seq_val(0), macro_fn, macro_err);
seq_drop_prefix(ast, 1, call_args);
apply_func(macro_fn, call_args, ast, macro_err);
if macro_err /= null then
err := macro_err;
return;
end if;
is_macro_call(ast, env, is_macro);
end loop;
result := ast;
end procedure macroexpand;
procedure fn_eval(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
begin
EVAL(args.seq_val(0), repl_env, result, err);
end procedure fn_eval;
procedure fn_swap(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable atom: mal_val_ptr := args.seq_val(0);
variable fn: mal_val_ptr := args.seq_val(1);
variable call_args_seq: mal_seq_ptr;
variable call_args, eval_res, sub_err: mal_val_ptr;
begin
call_args_seq := new mal_seq(0 to args.seq_val'length - 2);
call_args_seq(0) := atom.seq_val(0);
call_args_seq(1 to call_args_seq'length - 1) := args.seq_val(2 to args.seq_val'length - 1);
new_seq_obj(mal_list, call_args_seq, call_args);
apply_func(fn, call_args, eval_res, sub_err);
if sub_err /= null then
err := sub_err;
return;
end if;
atom.seq_val(0) := eval_res;
result := eval_res;
end procedure fn_swap;
procedure fn_apply(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable fn: mal_val_ptr := args.seq_val(0);
variable rest: mal_val_ptr;
variable mid_args_count, rest_args_count: integer;
variable call_args: mal_val_ptr;
variable call_args_seq: mal_seq_ptr;
begin
rest := args.seq_val(args.seq_val'high);
mid_args_count := args.seq_val'length - 2;
rest_args_count := rest.seq_val'length;
call_args_seq := new mal_seq(0 to mid_args_count + rest_args_count - 1);
call_args_seq(0 to mid_args_count - 1) := args.seq_val(1 to args.seq_val'length - 2);
call_args_seq(mid_args_count to call_args_seq'high) := rest.seq_val(rest.seq_val'range);
new_seq_obj(mal_list, call_args_seq, call_args);
apply_func(fn, call_args, result, err);
end procedure fn_apply;
procedure fn_map(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable fn: mal_val_ptr := args.seq_val(0);
variable lst: mal_val_ptr := args.seq_val(1);
variable call_args, sub_err: mal_val_ptr;
variable new_seq: mal_seq_ptr;
variable i: integer;
begin
new_seq := new mal_seq(lst.seq_val'range); -- (0 to lst.seq_val.length - 1);
for i in new_seq'range loop
new_one_element_list(lst.seq_val(i), call_args);
apply_func(fn, call_args, new_seq(i), sub_err);
if sub_err /= null then
err := sub_err;
return;
end if;
end loop;
new_seq_obj(mal_list, new_seq, result);
end procedure fn_map;
procedure apply_native_func(func_sym: inout mal_val_ptr; args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
begin
if func_sym.string_val.all = "eval" then
fn_eval(args, result, err);
elsif func_sym.string_val.all = "swap!" then
fn_swap(args, result, err);
elsif func_sym.string_val.all = "apply" then
fn_apply(args, result, err);
elsif func_sym.string_val.all = "map" then
fn_map(args, result, err);
else
eval_native_func(func_sym, args, result, err);
end if;
end procedure apply_native_func;
procedure apply_func(fn: inout mal_val_ptr; args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable fn_env: env_ptr;
begin
case fn.val_type is
when mal_nativefn =>
apply_native_func(fn, args, result, err);
when mal_fn =>
new_env(fn_env, fn.func_val.f_env, fn.func_val.f_args, args);
EVAL(fn.func_val.f_body, fn_env, result, err);
when others =>
new_string("not a function", err);
return;
end case;
end procedure apply_func;
procedure eval_ast_seq(ast_seq: inout mal_seq_ptr; env: inout env_ptr; result: inout mal_seq_ptr; err: out mal_val_ptr) is
variable eval_err: mal_val_ptr;
begin
result := new mal_seq(0 to ast_seq'length - 1);
for i in result'range loop
EVAL(ast_seq(i), env, result(i), eval_err);
if eval_err /= null then
err := eval_err;
return;
end if;
end loop;
end procedure eval_ast_seq;
procedure eval_ast(ast: inout mal_val_ptr; env: inout env_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable key, val, eval_err, env_err: mal_val_ptr;
variable new_seq: mal_seq_ptr;
variable i: integer;
begin
case ast.val_type is
when mal_symbol =>
env_get(env, ast, val, env_err);
if env_err /= null then
err := env_err;
return;
end if;
result := val;
return;
when mal_list | mal_vector | mal_hashmap =>
eval_ast_seq(ast.seq_val, env, new_seq, eval_err);
if eval_err /= null then
err := eval_err;
return;
end if;
new_seq_obj(ast.val_type, new_seq, result);
return;
when others =>
result := ast;
return;
end case;
end procedure eval_ast;
procedure EVAL(in_ast: inout mal_val_ptr; in_env: inout env_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable i: integer;
variable ast, evaled_ast, a0, call_args, val, vars, sub_err, fn: mal_val_ptr;
variable env, let_env, catch_env, fn_env: env_ptr;
begin
ast := in_ast;
env := in_env;
loop
if ast.val_type /= mal_list then
eval_ast(ast, env, result, err);
return;
end if;
macroexpand(ast, env, ast, sub_err);
if sub_err /= null then
err := sub_err;
return;
end if;
if ast.val_type /= mal_list then
eval_ast(ast, env, result, err);
return;
end if;
if ast.seq_val'length = 0 then
result := ast;
return;
end if;
a0 := ast.seq_val(0);
if a0.val_type = mal_symbol then
if a0.string_val.all = "def!" then
EVAL(ast.seq_val(2), env, val, sub_err);
if sub_err /= null then
err := sub_err;
return;
end if;
env_set(env, ast.seq_val(1), val);
result := val;
return;
elsif a0.string_val.all = "let*" then
vars := ast.seq_val(1);
new_env(let_env, env);
i := 0;
while i < vars.seq_val'length loop
EVAL(vars.seq_val(i + 1), let_env, val, sub_err);
if sub_err /= null then
err := sub_err;
return;
end if;
env_set(let_env, vars.seq_val(i), val);
i := i + 2;
end loop;
env := let_env;
ast := ast.seq_val(2);
next; -- TCO
elsif a0.string_val.all = "quote" then
result := ast.seq_val(1);
return;
elsif a0.string_val.all = "quasiquote" then
quasiquote(ast.seq_val(1), ast);
next; -- TCO
elsif a0.string_val.all = "defmacro!" then
EVAL(ast.seq_val(2), env, val, sub_err);
if sub_err /= null then
err := sub_err;
return;
end if;
val.func_val.f_is_macro := true;
env_set(env, ast.seq_val(1), val);
result := val;
return;
elsif a0.string_val.all = "macroexpand" then
macroexpand(ast.seq_val(1), env, result, err);
return;
elsif a0.string_val.all = "try*" then
EVAL(ast.seq_val(1), env, result, sub_err);
if sub_err /= null then
if ast.seq_val'length > 2 and
ast.seq_val(2).val_type = mal_list and
ast.seq_val(2).seq_val(0).val_type = mal_symbol and
ast.seq_val(2).seq_val(0).string_val.all = "catch*" then
new_one_element_list(ast.seq_val(2).seq_val(1), vars);
new_one_element_list(sub_err, call_args);
new_env(catch_env, env, vars, call_args);
EVAL(ast.seq_val(2).seq_val(2), catch_env, result, err);
else
new_nil(result);
end if;
end if;
return;
elsif a0.string_val.all = "do" then
for i in 1 to ast.seq_val'high - 1 loop
EVAL(ast.seq_val(i), env, result, sub_err);
if sub_err /= null then
err := sub_err;
return;
end if;
end loop;
ast := ast.seq_val(ast.seq_val'high);
next; -- TCO
elsif a0.string_val.all = "if" then
EVAL(ast.seq_val(1), env, val, sub_err);
if sub_err /= null then
err := sub_err;
return;
end if;
if val.val_type = mal_nil or val.val_type = mal_false then
if ast.seq_val'length > 3 then
ast := ast.seq_val(3);
else
new_nil(result);
return;
end if;
else
ast := ast.seq_val(2);
end if;
next; -- TCO
elsif a0.string_val.all = "fn*" then
new_fn(ast.seq_val(2), ast.seq_val(1), env, result);
return;
end if;
end if;
eval_ast(ast, env, evaled_ast, sub_err);
if sub_err /= null then
err := sub_err;
return;
end if;
seq_drop_prefix(evaled_ast, 1, call_args);
fn := evaled_ast.seq_val(0);
case fn.val_type is
when mal_nativefn =>
apply_native_func(fn, call_args, result, err);
return;
when mal_fn =>
new_env(fn_env, fn.func_val.f_env, fn.func_val.f_args, call_args);
env := fn_env;
ast := fn.func_val.f_body;
next; -- TCO
when others =>
new_string("not a function", err);
return;
end case;
end loop;
end procedure EVAL;
procedure mal_PRINT(exp: inout mal_val_ptr; result: out line) is
begin
pr_str(exp, true, result);
end procedure mal_PRINT;
procedure RE(str: in string; env: inout env_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable ast, read_err: mal_val_ptr;
begin
mal_READ(str, ast, read_err);
if read_err /= null then
err := read_err;
result := null;
return;
end if;
if ast = null then
result := null;
return;
end if;
EVAL(ast, env, result, err);
end procedure RE;
procedure REP(str: in string; env: inout env_ptr; result: out line; err: out mal_val_ptr) is
variable eval_res, eval_err: mal_val_ptr;
begin
RE(str, env, eval_res, eval_err);
if eval_err /= null then
err := eval_err;
result := null;
return;
end if;
mal_PRINT(eval_res, result);
end procedure REP;
procedure set_argv(e: inout env_ptr; program_file: inout line) is
variable argv_var_name: string(1 to 6) := "*ARGV*";
variable argv_sym, argv_list: mal_val_ptr;
file f: text;
variable status: file_open_status;
variable one_line: line;
variable seq: mal_seq_ptr;
variable element: mal_val_ptr;
begin
program_file := null;
seq := new mal_seq(0 to -1);
file_open(status, f, external_name => "vhdl_argv.tmp", open_kind => read_mode);
if status = open_ok then
if not endfile(f) then
readline(f, program_file);
while not endfile(f) loop
readline(f, one_line);
new_string(one_line.all, element);
seq := new mal_seq'(seq.all & element);
end loop;
end if;
file_close(f);
end if;
new_seq_obj(mal_list, seq, argv_list);
new_symbol(argv_var_name, argv_sym);
env_set(e, argv_sym, argv_list);
end procedure set_argv;
procedure repl is
variable is_eof: boolean;
variable program_file, input_line, result: line;
variable eval_sym, eval_fn, dummy_val, err: mal_val_ptr;
variable outer: env_ptr;
variable eval_func_name: string(1 to 4) := "eval";
begin
outer := null;
new_env(repl_env, outer);
-- core.EXT: defined using VHDL (see core.vhdl)
define_core_functions(repl_env);
new_symbol(eval_func_name, eval_sym);
new_nativefn(eval_func_name, eval_fn);
env_set(repl_env, eval_sym, eval_fn);
set_argv(repl_env, program_file);
-- core.mal: defined using the language itself
RE("(def! not (fn* (a) (if a false true)))", repl_env, dummy_val, err);
RE("(def! load-file (fn* (f) (eval (read-string (str " & '"' & "(do " & '"' & " (slurp f) " & '"' & ")" & '"' & ")))))", repl_env, dummy_val, err);
RE("(defmacro! cond (fn* (& xs) (if (> (count xs) 0) (list 'if (first xs) (if (> (count xs) 1) (nth xs 1) (throw " & '"' & "odd number of forms to cond" & '"' & ")) (cons 'cond (rest (rest xs)))))))", repl_env, dummy_val, err);
RE("(defmacro! or (fn* (& xs) (if (empty? xs) nil (if (= 1 (count xs)) (first xs) `(let* (or_FIXME ~(first xs)) (if or_FIXME or_FIXME (or ~@(rest xs))))))))", repl_env, dummy_val, err);
if program_file /= null then
REP("(load-file " & '"' & program_file.all & '"' & ")", repl_env, result, err);
return;
end if;
loop
mal_readline("user> ", is_eof, input_line);
exit when is_eof;
next when input_line'length = 0;
REP(input_line.all, repl_env, result, err);
if err /= null then
pr_str(err, false, result);
result := new string'("Error: " & result.all);
end if;
if result /= null then
mal_printline(result.all);
end if;
deallocate(result);
deallocate(err);
end loop;
mal_printline("");
end procedure repl;
begin
repl;
end architecture test;
|
mpl-2.0
|
0gajun/mal
|
vhdl/env.vhdl
|
17
|
2358
|
library STD;
use STD.textio.all;
library WORK;
use WORK.types.all;
package env is
procedure new_env(e: out env_ptr; an_outer: inout env_ptr);
procedure new_env(e: out env_ptr; an_outer: inout env_ptr; binds: inout mal_val_ptr; exprs: inout mal_val_ptr);
procedure env_set(e: inout env_ptr; key: inout mal_val_ptr; val: inout mal_val_ptr);
procedure env_get(e: inout env_ptr; key: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr);
end package env;
package body env is
procedure new_env(e: out env_ptr; an_outer: inout env_ptr) is
variable null_list: mal_val_ptr;
begin
null_list := null;
new_env(e, an_outer, null_list, null_list);
end procedure new_env;
procedure new_env(e: out env_ptr; an_outer: inout env_ptr; binds: inout mal_val_ptr; exprs: inout mal_val_ptr) is
variable the_data, more_exprs: mal_val_ptr;
variable i: integer;
begin
new_empty_hashmap(the_data);
if binds /= null then
for i in binds.seq_val'range loop
if binds.seq_val(i).string_val.all = "&" then
seq_drop_prefix(exprs, i, more_exprs);
hashmap_put(the_data, binds.seq_val(i + 1), more_exprs);
exit;
else
hashmap_put(the_data, binds.seq_val(i), exprs.seq_val(i));
end if;
end loop;
end if;
e := new env_record'(outer => an_outer, data => the_data);
end procedure new_env;
procedure env_set(e: inout env_ptr; key: inout mal_val_ptr; val: inout mal_val_ptr) is
begin
hashmap_put(e.data, key, val);
end procedure env_set;
procedure env_find(e: inout env_ptr; key: inout mal_val_ptr; found_env: out env_ptr) is
variable found: boolean;
begin
hashmap_contains(e.data, key, found);
if found then
found_env := e;
else
if e.outer = null then
found_env := null;
else
env_find(e.outer, key, found_env);
end if;
end if;
end procedure env_find;
procedure env_get(e: inout env_ptr; key: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable found_env: env_ptr;
begin
env_find(e, key, found_env);
if found_env = null then
new_string("'" & key.string_val.all & "' not found", err);
result := null;
return;
end if;
hashmap_get(found_env.data, key, result);
end procedure env_get;
end package body env;
|
mpl-2.0
|
eeshangarg/oh-mainline
|
vendor/packages/Pygments/tests/examplefiles/test.vhdl
|
75
|
4446
|
library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity top_testbench is --test
generic ( -- test
n : integer := 8 -- test
); -- test
end top_testbench; -- test
architecture top_testbench_arch of top_testbench is
component top is
generic (
n : integer
) ;
port (
clk : in std_logic;
rst : in std_logic;
d1 : in std_logic_vector (n-1 downto 0);
d2 : in std_logic_vector (n-1 downto 0);
operation : in std_logic;
result : out std_logic_vector (2*n-1 downto 0)
);
end component;
signal clk : std_logic;
signal rst : std_logic;
signal operation : std_logic;
signal d1 : std_logic_vector (n-1 downto 0);
signal d2 : std_logic_vector (n-1 downto 0);
signal result : std_logic_vector (2*n-1 downto 0);
type test_type is ( a1, a2, a3, a4, a5, a6, a7, a8, a9, a10);
attribute enum_encoding of my_state : type is "001 010 011 100 111";
begin
TESTUNIT : top generic map (n => n)
port map (clk => clk,
rst => rst,
d1 => d1,
d2 => d2,
operation => operation,
result => result);
clock_process : process
begin
clk <= '0';
wait for 5 ns;
clk <= '1';
wait for 5 ns;
end process;
data_process : process
begin
-- test case #1
operation <= '0';
rst <= '1';
wait for 5 ns;
rst <= '0';
wait for 5 ns;
d1 <= std_logic_vector(to_unsigned(60, d1'length));
d2 <= std_logic_vector(to_unsigned(12, d2'length));
wait for 360 ns;
assert (result = std_logic_vector(to_unsigned(720, result'length)))
report "Test case #1 failed" severity error;
-- test case #2
operation <= '0';
rst <= '1';
wait for 5 ns;
rst <= '0';
wait for 5 ns;
d1 <= std_logic_vector(to_unsigned(55, d1'length));
d2 <= std_logic_vector(to_unsigned(1, d2'length));
wait for 360 ns;
assert (result = std_logic_vector(to_unsigned(55, result'length)))
report "Test case #2 failed" severity error;
-- etc
end process;
end top_testbench_arch;
configuration testbench_for_top of top_testbench is
for top_testbench_arch
for TESTUNIT : top
use entity work.top(top_arch);
end for;
end for;
end testbench_for_top;
function compare(A: std_logic, B: std_Logic) return std_logic is
constant pi : real := 3.14159;
constant half_pi : real := pi / 2.0;
constant cycle_time : time := 2 ns;
constant N, N5 : integer := 5;
begin
if (A = '0' and B = '1') then
return B;
else
return A;
end if ;
end compare;
procedure print(P : std_logic_vector(7 downto 0);
U : std_logic_vector(3 downto 0)) is
variable my_line : line;
alias swrite is write [line, string, side, width] ;
begin
swrite(my_line, "sqrt( ");
write(my_line, P);
swrite(my_line, " )= ");
write(my_line, U);
writeline(output, my_line);
end print;
entity add32csa is -- one stage of carry save adder for multiplier
port(
b : in std_logic; -- a multiplier bit
a : in std_logic_vector(31 downto 0); -- multiplicand
sum_in : in std_logic_vector(31 downto 0); -- sums from previous stage
cin : in std_logic_vector(31 downto 0); -- carrys from previous stage
sum_out : out std_logic_vector(31 downto 0); -- sums to next stage
cout : out std_logic_vector(31 downto 0)); -- carrys to next stage
end add32csa;
ARCHITECTURE circuits of add32csa IS
SIGNAL zero : STD_LOGIC_VECTOR(31 downto 0) := X"00000000";
SIGNAL aa : std_logic_vector(31 downto 0) := X"00000000";
COMPONENT fadd -- duplicates entity port
PoRT(a : in std_logic;
b : in std_logic;
cin : in std_logic;
s : out std_logic;
cout : out std_logic);
end comPonent fadd;
begin -- circuits of add32csa
aa <= a when b='1' else zero after 1 ns;
stage: for I in 0 to 31 generate
sta: fadd port map(aa(I), sum_in(I), cin(I) , sum_out(I), cout(I));
end generate stage;
end architecture circuits; -- of add32csa
|
agpl-3.0
|
hlange/LogSoCR
|
gaisler/leon3/mmucache/typ_adapters.vhd
|
3
|
2809
|
-- *********************************************************************
-- Copyright 2010, Institute of Computer and Network Engineering,
-- TU-Braunschweig
-- All rights reserved
-- Any reproduction, use, distribution or disclosure of this program,
-- without the express, prior written consent of the authors is
-- strictly prohibited.
--
-- University of Technology Braunschweig
-- Institute of Computer and Network Engineering
-- Hans-Sommer-Str. 66
-- 38118 Braunschweig, Germany
--
-- ESA SPECIAL LICENSE
--
-- This program may be freely used, copied, modified, and redistributed
-- by the European Space Agency for the Agency's own requirements.
--
-- The program is provided "as is", there is no warranty that
-- the program is correct or suitable for any purpose,
-- neither implicit nor explicit. The program and the information in it
-- contained do not necessarily reflect the policy of the
-- European Space Agency or of TU-Braunschweig.
-- **********************************************************************
-- Title: typ_adapters.vhd
--
-- ScssId:
--
-- Origin: HW-SW SystemC Co-Simulation SoC Validation Platform
--
-- Purpose: Adapter for datatyps that can not be automatically
-- mapped from RTL to SystemC.
--
-- Method:
--
-- Principal: European Space Agency
-- Author: VLSI working group @ IDA @ TUBS
-- Maintainer: Thomas Schuster
-- Reviewed:
-- **********************************************************************
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.libiu.all;
use gaisler.libcache.all;
use gaisler.mmuconfig.all;
use gaisler.mmuiface.all;
use gaisler.libmmu.all;
package typ_adapters is
type ahb_mst_out_type_adapter is record
hbusreq : std_ulogic; -- bus request
hlock : std_ulogic; -- lock request
htrans : std_logic_vector(1 downto 0); -- transfer type
haddr : std_logic_vector(31 downto 0); -- address bus (byte)
hwrite : std_ulogic; -- read/write
hsize : std_logic_vector(2 downto 0); -- transfer size
hburst : std_logic_vector(2 downto 0); -- burst type
hprot : std_logic_vector(3 downto 0); -- protection control
hwdata : std_logic_vector(31 downto 0); -- write data bus
hirq : std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt bus
hconfig : ahb_config_type; -- memory access reg.
hindex : integer; -- diagnostic use only
end record;
end typ_adapters;
|
agpl-3.0
|
BBN-Q/VHDL-Components
|
test/FakeOSERDES.vhd
|
1
|
1203
|
-- Fake testing module that mocks a 4:1 DDR OSERDES module
--
-- Original authors Diego Riste and Colm Ryan
-- Copyright 2015, Raytheon BBN Technologies
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity FakeOSERDES is
generic (
SAMPLE_WIDTH : natural := 16;
CLK_PERIOD : time := 2 ns
);
port (
reset : in std_logic;
data_in : in std_logic_vector(4*SAMPLE_WIDTH-1 downto 0);
clk_in : in std_logic;
data_out : out std_logic_vector(SAMPLE_WIDTH-1 downto 0)
);
end entity ; -- FakeOSERDES
architecture arch of FakeOSERDES is
begin
serialize : process
variable registered_data : std_logic_vector(4*SAMPLE_WIDTH-1 downto 0);
begin
wait until rising_edge(clk_in);
while true loop
--register the input data as a crude clock crosser
registered_data := data_in;
if reset = '1' then
data_out <= (others => '0');
wait for CLK_PERIOD;
else
for ct in 0 to 3 loop
data_out <= registered_data((ct+1)*SAMPLE_WIDTH-1 downto ct*SAMPLE_WIDTH);
if ct = 3 then
wait until rising_edge(clk_in);
else
wait for CLK_PERIOD/2;
end if;
end loop; --
end if;
end loop ; --
end process; -- serialize
end architecture ; -- arch
|
mpl-2.0
|
DomBlack/mal
|
vhdl/pkg_readline.vhdl
|
17
|
928
|
library STD;
use STD.textio.all;
package pkg_readline is
procedure mal_printline(l: string);
procedure mal_readline(prompt: string; eof_detected: out boolean; l: inout line);
end package pkg_readline;
package body pkg_readline is
type charfile is file of character;
file stdout_char: charfile open write_mode is "STD_OUTPUT";
procedure mal_printstr(l: string) is
begin
for i in l'range loop
write(stdout_char, l(i));
end loop;
end procedure mal_printstr;
procedure mal_printline(l: string) is
begin
mal_printstr(l);
write(stdout_char, LF);
end procedure mal_printline;
procedure mal_readline(prompt: string; eof_detected: out boolean; l: inout line) is
begin
mal_printstr(prompt);
if endfile(input) then
eof_detected := true;
else
readline(input, l);
eof_detected := false;
end if;
end procedure mal_readline;
end package body pkg_readline;
|
mpl-2.0
|
DomBlack/mal
|
vhdl/core.vhdl
|
8
|
25023
|
library STD;
use STD.textio.all;
library WORK;
use WORK.types.all;
use WORK.env.all;
use WORK.reader.all;
use WORK.printer.all;
use WORK.pkg_readline.all;
package core is
procedure eval_native_func(func_sym: inout mal_val_ptr; args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr);
procedure define_core_functions(e: inout env_ptr);
end package core;
package body core is
procedure fn_equal(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable is_equal: boolean;
begin
equal_q(args.seq_val(0), args.seq_val(1), is_equal);
new_boolean(is_equal, result);
end procedure fn_equal;
procedure fn_throw(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
begin
err := args.seq_val(0);
end procedure fn_throw;
procedure fn_nil_q(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
begin
new_boolean(args.seq_val(0).val_type = mal_nil, result);
end procedure fn_nil_q;
procedure fn_true_q(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
begin
new_boolean(args.seq_val(0).val_type = mal_true, result);
end procedure fn_true_q;
procedure fn_false_q(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
begin
new_boolean(args.seq_val(0).val_type = mal_false, result);
end procedure fn_false_q;
procedure fn_string_q(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
begin
new_boolean(args.seq_val(0).val_type = mal_string, result);
end procedure fn_string_q;
procedure fn_symbol(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
begin
new_symbol(args.seq_val(0).string_val, result);
end procedure fn_symbol;
procedure fn_symbol_q(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
begin
new_boolean(args.seq_val(0).val_type = mal_symbol, result);
end procedure fn_symbol_q;
procedure fn_keyword(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
begin
new_keyword(args.seq_val(0).string_val, result);
end procedure fn_keyword;
procedure fn_keyword_q(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
begin
new_boolean(args.seq_val(0).val_type = mal_keyword, result);
end procedure fn_keyword_q;
procedure fn_pr_str(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable s: line;
begin
pr_seq("", "", " ", args.seq_val, true, s);
new_string(s, result);
end procedure fn_pr_str;
procedure fn_str(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable s: line;
begin
pr_seq("", "", "", args.seq_val, false, s);
new_string(s, result);
end procedure fn_str;
procedure fn_prn(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable s: line;
begin
pr_seq("", "", " ", args.seq_val, true, s);
mal_printline(s.all);
new_nil(result);
end procedure fn_prn;
procedure fn_println(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable s: line;
begin
pr_seq("", "", " ", args.seq_val, false, s);
mal_printline(s.all);
new_nil(result);
end procedure fn_println;
procedure fn_read_string(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable ast: mal_val_ptr;
begin
read_str(args.seq_val(0).string_val.all, ast, err);
if ast = null then
new_nil(result);
else
result := ast;
end if;
end procedure fn_read_string;
procedure fn_readline(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable input_line: line;
variable is_eof: boolean;
begin
mal_readline(args.seq_val(0).string_val.all, is_eof, input_line);
if is_eof then
new_nil(result);
else
new_string(input_line, result);
end if;
end procedure fn_readline;
procedure fn_slurp(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
file f: text;
variable status: file_open_status;
variable save_content, content, one_line: line;
begin
file_open(status, f, external_name => args.seq_val(0).string_val.all, open_kind => read_mode);
if status = open_ok then
content := new string'("");
while not endfile(f) loop
readline(f, one_line);
save_content := content;
content := new string'(save_content.all & one_line.all & LF);
deallocate(save_content);
end loop;
file_close(f);
new_string(content, result);
else
new_string("Error opening file", err);
end if;
end procedure fn_slurp;
procedure fn_lt(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
begin
new_boolean(args.seq_val(0).number_val < args.seq_val(1).number_val, result);
end procedure fn_lt;
procedure fn_lte(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
begin
new_boolean(args.seq_val(0).number_val <= args.seq_val(1).number_val, result);
end procedure fn_lte;
procedure fn_gt(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
begin
new_boolean(args.seq_val(0).number_val > args.seq_val(1).number_val, result);
end procedure fn_gt;
procedure fn_gte(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
begin
new_boolean(args.seq_val(0).number_val >= args.seq_val(1).number_val, result);
end procedure fn_gte;
procedure fn_add(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
begin
new_number(args.seq_val(0).number_val + args.seq_val(1).number_val, result);
end procedure fn_add;
procedure fn_sub(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
begin
new_number(args.seq_val(0).number_val - args.seq_val(1).number_val, result);
end procedure fn_sub;
procedure fn_mul(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
begin
new_number(args.seq_val(0).number_val * args.seq_val(1).number_val, result);
end procedure fn_mul;
procedure fn_div(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
begin
new_number(args.seq_val(0).number_val / args.seq_val(1).number_val, result);
end procedure fn_div;
-- Define physical types (c_seconds64, c_microseconds64) because these are
-- represented as 64-bit words when passed to C functions
type c_seconds64 is range 0 to 1E16
units
c_sec;
end units c_seconds64;
type c_microseconds64 is range 0 to 1E6
units
c_usec;
end units c_microseconds64;
type c_timeval is record
tv_sec: c_seconds64;
tv_usec: c_microseconds64;
end record c_timeval;
-- Leave enough room for two 64-bit words
type c_timezone is record
dummy_1: c_seconds64;
dummy_2: c_seconds64;
end record c_timezone;
function gettimeofday(tv: c_timeval; tz: c_timezone) return integer;
attribute foreign of gettimeofday: function is "VHPIDIRECT gettimeofday";
function gettimeofday(tv: c_timeval; tz: c_timezone) return integer is
begin
assert false severity failure;
end function gettimeofday;
-- Returns the number of milliseconds since 2000-01-01 00:00:00 UTC because
-- a standard VHDL integer is 32-bit and therefore cannot hold the number of
-- milliseconds since 1970-01-01.
procedure fn_time_ms(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable tv: c_timeval;
variable dummy: c_timezone;
variable rc: integer;
constant utc_2000_01_01: c_seconds64 := 946684800 c_sec; -- UNIX time at 2000-01-01 00:00:00 UTC
begin
rc := gettimeofday(tv, dummy);
new_number(((tv.tv_sec - utc_2000_01_01) / 1 c_sec) * 1000 + (tv.tv_usec / 1000 c_usec), result);
end procedure fn_time_ms;
procedure fn_list(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
begin
result := args;
end procedure fn_list;
procedure fn_list_q(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
begin
new_boolean(args.seq_val(0).val_type = mal_list, result);
end procedure fn_list_q;
procedure fn_vector(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
begin
args.val_type := mal_vector;
result := args;
end procedure fn_vector;
procedure fn_vector_q(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
begin
new_boolean(args.seq_val(0).val_type = mal_vector, result);
end procedure fn_vector_q;
procedure fn_hash_map(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
begin
args.val_type := mal_hashmap;
result := args;
end procedure fn_hash_map;
procedure fn_map_q(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
begin
new_boolean(args.seq_val(0).val_type = mal_hashmap, result);
end procedure fn_map_q;
procedure fn_assoc(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable new_hashmap: mal_val_ptr;
variable i: integer;
begin
hashmap_copy(args.seq_val(0), new_hashmap);
i := 1;
while i < args.seq_val'length loop
hashmap_put(new_hashmap, args.seq_val(i), args.seq_val(i + 1));
i := i + 2;
end loop;
result := new_hashmap;
end procedure fn_assoc;
procedure fn_dissoc(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable new_hashmap: mal_val_ptr;
variable i: integer;
begin
hashmap_copy(args.seq_val(0), new_hashmap);
for i in 1 to args.seq_val'high loop
hashmap_delete(new_hashmap, args.seq_val(i));
end loop;
result := new_hashmap;
end procedure fn_dissoc;
procedure fn_get(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable a0: mal_val_ptr := args.seq_val(0);
variable a1: mal_val_ptr := args.seq_val(1);
variable val: mal_val_ptr;
begin
if a0.val_type = mal_nil then
new_nil(result);
else
hashmap_get(a0, a1, val);
if val = null then
new_nil(result);
else
result := val;
end if;
end if;
end procedure fn_get;
procedure fn_contains_q(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable a0: mal_val_ptr := args.seq_val(0);
variable a1: mal_val_ptr := args.seq_val(1);
variable found: boolean;
begin
hashmap_contains(a0, a1, found);
new_boolean(found, result);
end procedure fn_contains_q;
procedure fn_keys(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable a0: mal_val_ptr := args.seq_val(0);
variable seq: mal_seq_ptr;
begin
seq := new mal_seq(0 to a0.seq_val'length / 2 - 1);
for i in seq'range loop
seq(i) := a0.seq_val(i * 2);
end loop;
new_seq_obj(mal_list, seq, result);
end procedure fn_keys;
procedure fn_vals(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable a0: mal_val_ptr := args.seq_val(0);
variable seq: mal_seq_ptr;
begin
seq := new mal_seq(0 to a0.seq_val'length / 2 - 1);
for i in seq'range loop
seq(i) := a0.seq_val(i * 2 + 1);
end loop;
new_seq_obj(mal_list, seq, result);
end procedure fn_vals;
procedure cons_helper(a0: inout mal_val_ptr; a1: inout mal_val_ptr; result: out mal_val_ptr) is
variable seq: mal_seq_ptr;
begin
seq := new mal_seq(0 to a1.seq_val'length);
seq(0) := a0;
seq(1 to seq'length - 1) := a1.seq_val(0 to a1.seq_val'length - 1);
new_seq_obj(mal_list, seq, result);
end procedure cons_helper;
procedure fn_cons(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable a0: mal_val_ptr := args.seq_val(0);
variable a1: mal_val_ptr := args.seq_val(1);
variable seq: mal_seq_ptr;
begin
cons_helper(a0, a1, result);
end procedure fn_cons;
procedure fn_sequential_q(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
begin
new_boolean(is_sequential_type(args.seq_val(0).val_type), result);
end procedure fn_sequential_q;
procedure fn_concat(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable seq: mal_seq_ptr;
variable i: integer;
begin
seq := new mal_seq(0 to -1);
for i in args.seq_val'range loop
seq := new mal_seq'(seq.all & args.seq_val(i).seq_val.all);
end loop;
new_seq_obj(mal_list, seq, result);
end procedure fn_concat;
procedure fn_nth(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable lst_seq: mal_seq_ptr := args.seq_val(0).seq_val;
variable index: integer := args.seq_val(1).number_val;
begin
if index >= lst_seq'length then
new_string("nth: index out of range", err);
else
result := lst_seq(index);
end if;
end procedure fn_nth;
procedure fn_first(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable a0: mal_val_ptr := args.seq_val(0);
begin
if a0.val_type = mal_nil or a0.seq_val'length = 0 then
new_nil(result);
else
result := a0.seq_val(0);
end if;
end procedure fn_first;
procedure fn_rest(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable a0: mal_val_ptr := args.seq_val(0);
variable seq: mal_seq_ptr;
variable new_list: mal_val_ptr;
begin
if a0.val_type = mal_nil or a0.seq_val'length = 0 then
seq := new mal_seq(0 to -1);
new_seq_obj(mal_list, seq, result);
else
seq_drop_prefix(a0, 1, new_list);
new_list.val_type := mal_list;
result := new_list;
end if;
end procedure fn_rest;
procedure fn_empty_q(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable is_empty: boolean;
begin
case args.seq_val(0).val_type is
when mal_nil => new_boolean(true, result);
when mal_list | mal_vector => new_boolean(args.seq_val(0).seq_val'length = 0, result);
when others => new_string("empty?: invalid argument type", err);
end case;
end procedure fn_empty_q;
procedure fn_count(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable count: integer;
begin
case args.seq_val(0).val_type is
when mal_nil => new_number(0, result);
when mal_list | mal_vector => new_number(args.seq_val(0).seq_val'length, result);
when others => new_string("count: invalid argument type", err);
end case;
end procedure fn_count;
procedure fn_conj(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable a0: mal_val_ptr := args.seq_val(0);
variable r: mal_val_ptr;
variable seq: mal_seq_ptr;
begin
case a0.val_type is
when mal_list =>
r := a0;
for i in 1 to args.seq_val'high loop
cons_helper(args.seq_val(i), r, r);
end loop;
result := r;
when mal_vector =>
seq := new mal_seq(0 to a0.seq_val'length + args.seq_val'length - 2);
seq(0 to a0.seq_val'high) := a0.seq_val(a0.seq_val'range);
seq(a0.seq_val'high + 1 to seq'high) := args.seq_val(1 to args.seq_val'high);
new_seq_obj(mal_vector, seq, result);
when others =>
new_string("conj requires list or vector", err);
end case;
end procedure fn_conj;
procedure fn_seq(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable a0: mal_val_ptr := args.seq_val(0);
variable new_seq: mal_seq_ptr;
begin
case a0.val_type is
when mal_string =>
if a0.string_val'length = 0 then
new_nil(result);
else
new_seq := new mal_seq(0 to a0.string_val'length - 1);
for i in new_seq'range loop
new_string("" & a0.string_val(i + 1), new_seq(i));
end loop;
new_seq_obj(mal_list, new_seq, result);
end if;
when mal_list =>
if a0.seq_val'length = 0 then
new_nil(result);
else
result := a0;
end if;
when mal_vector =>
if a0.seq_val'length = 0 then
new_nil(result);
else
new_seq_obj(mal_list, a0.seq_val, result);
end if;
when mal_nil =>
new_nil(result);
when others =>
new_string("seq requires string or list or vector or nil", err);
end case;
end procedure fn_seq;
procedure fn_meta(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable meta_val: mal_val_ptr;
begin
meta_val := args.seq_val(0).meta_val;
if meta_val = null then
new_nil(result);
else
result := meta_val;
end if;
end procedure fn_meta;
procedure fn_with_meta(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable a0: mal_val_ptr := args.seq_val(0);
begin
result := new mal_val'(val_type => a0.val_type, number_val => a0.number_val, string_val => a0.string_val, seq_val => a0.seq_val, func_val => a0.func_val, meta_val => args.seq_val(1));
end procedure fn_with_meta;
procedure fn_atom(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
begin
new_atom(args.seq_val(0), result);
end procedure fn_atom;
procedure fn_atom_q(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable a0: mal_val_ptr := args.seq_val(0);
begin
new_boolean(a0.val_type = mal_atom, result);
end procedure fn_atom_q;
procedure fn_deref(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable a0: mal_val_ptr := args.seq_val(0);
begin
result := a0.seq_val(0);
end procedure fn_deref;
procedure fn_reset(args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable a0: mal_val_ptr := args.seq_val(0);
variable a1: mal_val_ptr := args.seq_val(1);
begin
a0.seq_val(0) := a1;
result := a1;
end procedure fn_reset;
procedure eval_native_func(func_sym: inout mal_val_ptr; args: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable f: line;
begin
if func_sym.val_type /= mal_nativefn then
new_string("not a native function!", err);
return;
end if;
f := func_sym.string_val;
if f.all = "=" then fn_equal(args, result, err);
elsif f.all = "throw" then fn_throw(args, result, err);
elsif f.all = "nil?" then fn_nil_q(args, result, err);
elsif f.all = "true?" then fn_true_q(args, result, err);
elsif f.all = "false?" then fn_false_q(args, result, err);
elsif f.all = "string?" then fn_string_q(args, result, err);
elsif f.all = "symbol" then fn_symbol(args, result, err);
elsif f.all = "symbol?" then fn_symbol_q(args, result, err);
elsif f.all = "keyword" then fn_keyword(args, result, err);
elsif f.all = "keyword?" then fn_keyword_q(args, result, err);
elsif f.all = "pr-str" then fn_pr_str(args, result, err);
elsif f.all = "str" then fn_str(args, result, err);
elsif f.all = "prn" then fn_prn(args, result, err);
elsif f.all = "println" then fn_println(args, result, err);
elsif f.all = "read-string" then fn_read_string(args, result, err);
elsif f.all = "readline" then fn_readline(args, result, err);
elsif f.all = "slurp" then fn_slurp(args, result, err);
elsif f.all = "<" then fn_lt(args, result, err);
elsif f.all = "<=" then fn_lte(args, result, err);
elsif f.all = ">" then fn_gt(args, result, err);
elsif f.all = ">=" then fn_gte(args, result, err);
elsif f.all = "+" then fn_add(args, result, err);
elsif f.all = "-" then fn_sub(args, result, err);
elsif f.all = "*" then fn_mul(args, result, err);
elsif f.all = "/" then fn_div(args, result, err);
elsif f.all = "time-ms" then fn_time_ms(args, result, err);
elsif f.all = "list" then fn_list(args, result, err);
elsif f.all = "list?" then fn_list_q(args, result, err);
elsif f.all = "vector" then fn_vector(args, result, err);
elsif f.all = "vector?" then fn_vector_q(args, result, err);
elsif f.all = "hash-map" then fn_hash_map(args, result, err);
elsif f.all = "map?" then fn_map_q(args, result, err);
elsif f.all = "assoc" then fn_assoc(args, result, err);
elsif f.all = "dissoc" then fn_dissoc(args, result, err);
elsif f.all = "get" then fn_get(args, result, err);
elsif f.all = "contains?" then fn_contains_q(args, result, err);
elsif f.all = "keys" then fn_keys(args, result, err);
elsif f.all = "vals" then fn_vals(args, result, err);
elsif f.all = "sequential?" then fn_sequential_q(args, result, err);
elsif f.all = "cons" then fn_cons(args, result, err);
elsif f.all = "concat" then fn_concat(args, result, err);
elsif f.all = "nth" then fn_nth(args, result, err);
elsif f.all = "first" then fn_first(args, result, err);
elsif f.all = "rest" then fn_rest(args, result, err);
elsif f.all = "empty?" then fn_empty_q(args, result, err);
elsif f.all = "count" then fn_count(args, result, err);
elsif f.all = "conj" then fn_conj(args, result, err);
elsif f.all = "seq" then fn_seq(args, result, err);
elsif f.all = "meta" then fn_meta(args, result, err);
elsif f.all = "with-meta" then fn_with_meta(args, result, err);
elsif f.all = "atom" then fn_atom(args, result, err);
elsif f.all = "atom?" then fn_atom_q(args, result, err);
elsif f.all = "deref" then fn_deref(args, result, err);
elsif f.all = "reset!" then fn_reset(args, result, err);
else
result := null;
end if;
end procedure eval_native_func;
procedure define_core_function(e: inout env_ptr; func_name: in string) is
variable sym: mal_val_ptr;
variable fn: mal_val_ptr;
begin
new_symbol(func_name, sym);
new_nativefn(func_name, fn);
env_set(e, sym, fn);
end procedure define_core_function;
procedure define_core_functions(e: inout env_ptr) is
variable is_eof: boolean;
variable input_line, result, err: line;
variable sym: mal_val_ptr;
variable fn: mal_val_ptr;
variable outer: env_ptr;
variable repl_env: env_ptr;
begin
define_core_function(e, "=");
define_core_function(e, "throw");
define_core_function(e, "nil?");
define_core_function(e, "true?");
define_core_function(e, "false?");
define_core_function(e, "string?");
define_core_function(e, "symbol");
define_core_function(e, "symbol?");
define_core_function(e, "keyword");
define_core_function(e, "keyword?");
define_core_function(e, "pr-str");
define_core_function(e, "str");
define_core_function(e, "prn");
define_core_function(e, "println");
define_core_function(e, "read-string");
define_core_function(e, "readline");
define_core_function(e, "slurp");
define_core_function(e, "<");
define_core_function(e, "<=");
define_core_function(e, ">");
define_core_function(e, ">=");
define_core_function(e, "+");
define_core_function(e, "-");
define_core_function(e, "*");
define_core_function(e, "/");
define_core_function(e, "time-ms");
define_core_function(e, "list");
define_core_function(e, "list?");
define_core_function(e, "vector");
define_core_function(e, "vector?");
define_core_function(e, "hash-map");
define_core_function(e, "map?");
define_core_function(e, "assoc");
define_core_function(e, "dissoc");
define_core_function(e, "get");
define_core_function(e, "contains?");
define_core_function(e, "keys");
define_core_function(e, "vals");
define_core_function(e, "sequential?");
define_core_function(e, "cons");
define_core_function(e, "concat");
define_core_function(e, "nth");
define_core_function(e, "first");
define_core_function(e, "rest");
define_core_function(e, "empty?");
define_core_function(e, "count");
define_core_function(e, "apply"); -- implemented in the stepN_XXX files
define_core_function(e, "map"); -- implemented in the stepN_XXX files
define_core_function(e, "conj");
define_core_function(e, "seq");
define_core_function(e, "meta");
define_core_function(e, "with-meta");
define_core_function(e, "atom");
define_core_function(e, "atom?");
define_core_function(e, "deref");
define_core_function(e, "reset!");
define_core_function(e, "swap!"); -- implemented in the stepN_XXX files
end procedure define_core_functions;
end package body core;
|
mpl-2.0
|
nxt4hll/roccc-2.0
|
roccc-compiler/src/llvm-2.3/include/rocccLibrary/DoubleSingleWordVoter.vhd
|
1
|
1278
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity DoubleSingleWordVoter is
port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
inputReady : in STD_LOGIC;
outputReady : out STD_LOGIC;
done : out STD_LOGIC;
stall : in STD_LOGIC;
error : out STD_LOGIC;
val0_in : in STD_LOGIC_VECTOR(31 downto 0);
val1_in : in STD_LOGIC_VECTOR(31 downto 0);
val2_in : in STD_LOGIC_VECTOR(31 downto 0);
val0_out : out STD_LOGIC_VECTOR(31 downto 0);
val1_out : out STD_LOGIC_VECTOR(31 downto 0);
val2_out : out STD_LOGIC_VECTOR(31 downto 0)
);
end DoubleSingleWordVoter;
architecture Behavioral of DoubleSingleWordVoter is
begin
process(clk, rst)
begin
if( rst = '1' ) then
elsif( clk'event and clk = '1' ) then
val0_out <= (others=>'0');
val1_out <= (others=>'0');
val2_out <= (others=>'0');
error <= '1';
if( val0_in = val1_in ) then
val0_out <= val0_in;
val1_out <= val0_in;
val2_out <= val0_in;
error <= '0';
end if;
end if;
end process;
end Behavioral;
|
epl-1.0
|
jwalsh/mal
|
vhdl/step1_read_print.vhdl
|
17
|
1721
|
entity step1_read_print is
end entity step1_read_print;
library STD;
use STD.textio.all;
library WORK;
use WORK.pkg_readline.all;
use WORK.types.all;
use WORK.printer.all;
use WORK.reader.all;
architecture test of step1_read_print is
procedure mal_READ(str: in string; ast: out mal_val_ptr; err: out mal_val_ptr) is
begin
read_str(str, ast, err);
end procedure mal_READ;
procedure EVAL(ast: inout mal_val_ptr; env: in string; result: out mal_val_ptr) is
begin
result := ast;
end procedure EVAL;
procedure mal_PRINT(exp: inout mal_val_ptr; result: out line) is
begin
pr_str(exp, true, result);
end procedure mal_PRINT;
procedure REP(str: in string; result: out line; err: out mal_val_ptr) is
variable ast, eval_res, read_err: mal_val_ptr;
begin
mal_READ(str, ast, read_err);
if read_err /= null then
err := read_err;
result := null;
return;
end if;
if ast = null then
result := null;
return;
end if;
EVAL(ast, "", eval_res);
mal_PRINT(eval_res, result);
end procedure REP;
procedure repl is
variable is_eof: boolean;
variable input_line, result: line;
variable err: mal_val_ptr;
begin
loop
mal_readline("user> ", is_eof, input_line);
exit when is_eof;
next when input_line'length = 0;
REP(input_line.all, result, err);
if err /= null then
pr_str(err, false, result);
result := new string'("Error: " & result.all);
end if;
if result /= null then
mal_printline(result.all);
end if;
deallocate(result);
deallocate(err);
end loop;
mal_printline("");
end procedure repl;
begin
repl;
end architecture test;
|
mpl-2.0
|
jwalsh/mal
|
vhdl/pkg_readline.vhdl
|
17
|
928
|
library STD;
use STD.textio.all;
package pkg_readline is
procedure mal_printline(l: string);
procedure mal_readline(prompt: string; eof_detected: out boolean; l: inout line);
end package pkg_readline;
package body pkg_readline is
type charfile is file of character;
file stdout_char: charfile open write_mode is "STD_OUTPUT";
procedure mal_printstr(l: string) is
begin
for i in l'range loop
write(stdout_char, l(i));
end loop;
end procedure mal_printstr;
procedure mal_printline(l: string) is
begin
mal_printstr(l);
write(stdout_char, LF);
end procedure mal_printline;
procedure mal_readline(prompt: string; eof_detected: out boolean; l: inout line) is
begin
mal_printstr(prompt);
if endfile(input) then
eof_detected := true;
else
readline(input, l);
eof_detected := false;
end if;
end procedure mal_readline;
end package body pkg_readline;
|
mpl-2.0
|
gtarciso/INE5406
|
aritmetico.vhd
|
1
|
638
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity aritmetico is
generic (width: integer:= 8);
port (
inpt0: in signed(width-1 downto 0);
inpt1: in signed(width-1 downto 0);
ctrl: in std_logic_vector(1 downto 0);
outp: out signed(width-1 downto 0)
);
end;
architecture arch of aritmetico is
begin
process(inpt0, inpt1, ctrl)
begin
if ctrl="00" then
outp <= inpt0 + inpt1;
elsif ctrl="01" then
outp <= inpt0 - inpt1;
elsif ctrl="10" then
outp <= inpt0 + 1;
else
outp <= inpt0 - 1;
end if;
end process;
end;
|
cc0-1.0
|
xdsopl/vhdl
|
max10_10M08E144_eval_test2.vhd
|
1
|
1547
|
-- test2 - clock divider controlled by quadrature decoder
-- Written in 2016 by <Ahmet Inan> <[email protected]>
-- To the extent possible under law, the author(s) have dedicated all copyright and related and neighboring rights to this software to the public domain worldwide. This software is distributed without any warranty.
-- You should have received a copy of the CC0 Public Domain Dedication along with this software. If not, see <http://creativecommons.org/publicdomain/zero/1.0/>.
library ieee;
use ieee.std_logic_1164.all;
entity max10_10M08E144_eval_test2 is
generic (
NUM_LEDS : positive := 5
);
port (
clock : in std_logic;
reset_n : in std_logic;
rotary_n : in std_logic_vector (1 downto 0);
leds_n : out std_logic_vector (NUM_LEDS-1 downto 0);
dclock : out std_logic
);
end max10_10M08E144_eval_test2;
architecture rtl of max10_10M08E144_eval_test2 is
attribute chip_pin : string;
attribute chip_pin of clock : signal is "27";
attribute chip_pin of dclock : signal is "62";
attribute chip_pin of reset_n : signal is "121";
attribute chip_pin of rotary_n : signal is "70, 69"; -- need to enable weak pullup resistor
attribute chip_pin of leds_n : signal is "132, 134, 135, 140, 141";
signal reset : std_logic;
signal rotary : std_logic_vector (1 downto 0);
signal leds : std_logic_vector (NUM_LEDS-1 downto 0);
begin
reset <= not reset_n;
rotary <= not rotary_n;
leds_n <= not leds;
test2_inst : entity work.test2
generic map (NUM_LEDS)
port map (clock, reset, rotary, leds, dclock);
end rtl;
|
cc0-1.0
|
xdsopl/vhdl
|
quadrature_decoder_testbench.vhd
|
1
|
2339
|
-- quadrature_decoder_testbench - testbench for quadrature decoder
-- Written in 2016 by <Ahmet Inan> <[email protected]>
-- To the extent possible under law, the author(s) have dedicated all copyright and related and neighboring rights to this software to the public domain worldwide. This software is distributed without any warranty.
-- You should have received a copy of the CC0 Public Domain Dedication along with this software. If not, see <http://creativecommons.org/publicdomain/zero/1.0/>.
library ieee;
use ieee.std_logic_1164.all;
entity quadrature_decoder_testbench is
end quadrature_decoder_testbench;
architecture behavioral of quadrature_decoder_testbench is
signal clock : std_logic := '0';
signal a, b : std_logic := '0';
signal rotary : std_logic_vector (1 downto 0);
signal direction : std_logic;
signal pulse : std_logic;
signal done : boolean := false;
procedure noise(variable n : inout std_logic_vector(15 downto 0)) is
begin
-- Thanks Maxim on smspower for (reverse engineered?) specs.
-- Generator polynomial for noise channel of SN76489
-- used on the SMS is not irrereducible: X^16 + X^13 + 1
n := (n(0) xor n(3)) & n(15 downto 1);
end procedure;
procedure switch(
signal s : out std_logic;
constant v : std_logic;
variable n : inout std_logic_vector(15 downto 0)) is
begin
s <= v;
wait for 10 us;
for i in 1 to 19 loop
s <= n(0);
noise(n);
wait for 10 us;
end loop;
s <= v;
wait for 800 us;
end procedure;
begin
rotary <= b & a;
quadrature_decoder_inst : entity work.quadrature_decoder
port map (clock, rotary, direction, pulse);
clk_gen : process
begin
if done then
wait;
else
wait for 1 us;
clock <= not clock;
end if;
end process;
stimulus : process
variable n : std_logic_vector(15 downto 0) := (15 => '1', others => '0');
begin
-- start position
a <= '0';
b <= '0';
wait for 2 ms;
for j in 0 to 2 loop
for i in 0 to j loop
-- one step left
switch(a, '1', n);
switch(b, '1', n);
switch(a, '0', n);
switch(b, '0', n);
wait for 1 ms;
end loop;
for i in 0 to j loop
-- one step right
switch(b, '1', n);
switch(a, '1', n);
switch(b, '0', n);
switch(a, '0', n);
wait for 1 ms;
end loop;
end loop;
done <= true;
wait;
end process;
end behavioral;
|
cc0-1.0
|
olofk/libstorage
|
rtl/vhdl/generic/fifo_fwft_adapter.vhd
|
1
|
2813
|
--
-- FIFO First word fall through adapter. Part of libstorage
--
-- Copyright (C) 2015 Olof Kindgren <[email protected]>
--
-- Permission to use, copy, modify, and/or distribute this software for any
-- purpose with or without fee is hereby granted, provided that the above
-- copyright notice and this permission notice appear in all copies.
--
-- THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-- WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-- ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-- WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-- ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-- OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
--
library ieee;
use ieee.std_logic_1164.all;
entity fifo_fwft_adapter is
generic (
type data_type);
port (
clk : in std_ulogic;
rst : in std_ulogic;
fifo_rd_en_o : out std_ulogic;
fifo_rd_data_i : in data_type;
fifo_empty_i : in std_ulogic;
rd_en_i : in std_ulogic;
rd_data_o : out data_type;
empty_o : out std_ulogic);
end entity;
architecture rtl of fifo_fwft_adapter is
signal fifo_valid : std_ulogic;
signal middle_valid : std_ulogic;
signal dout_valid : std_ulogic;
signal will_update_middle : std_ulogic;
signal will_update_dout : std_ulogic;
signal middle_dout : data_type;
begin
will_update_middle <= fifo_valid and (middle_valid ?= will_update_dout);
will_update_dout <= (middle_valid or fifo_valid) and
(rd_en_i or not dout_valid);
fifo_rd_en_o <= (not fifo_empty_i) and
not (middle_valid and dout_valid and fifo_valid);
empty_o <= not dout_valid;
p_main : process(clk)
begin
if rising_edge(clk) then
if will_update_middle then
middle_dout <= fifo_rd_data_i;
end if;
if will_update_dout then
if middle_valid = '1' then
rd_data_o <= middle_dout;
else
rd_data_o <= fifo_rd_data_i;
end if;
end if;
if fifo_rd_en_o then
fifo_valid <= '1';
elsif will_update_middle or will_update_dout then
fifo_valid <= '0';
end if;
if will_update_middle then
middle_valid <= '1';
elsif will_update_dout then
middle_valid <= '0';
end if;
if will_update_dout then
dout_valid <= '1';
elsif rd_en_i then
dout_valid <= '0';
end if;
if rst then
fifo_valid <= '0';
middle_valid <= '0';
dout_valid <= '0';
end if;
end if;
end process;
end architecture rtl;
|
isc
|
olofk/libstorage
|
rtl/vhdl/generic/fifo_generic.vhd
|
1
|
2630
|
--
-- FIFO. Part of libstorage
--
-- Copyright (C) 2015 Olof Kindgren <[email protected]>
--
-- Permission to use, copy, modify, and/or distribute this software for any
-- purpose with or without fee is hereby granted, provided that the above
-- copyright notice and this permission notice appear in all copies.
--
-- THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-- WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-- ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-- WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-- ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-- OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
--
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
library libstorage_1;
use libstorage_1.libstorage_pkg.all;
entity fifo_generic is
generic (
type data_type;
DEPTH : positive);
port (
clk : in std_ulogic;
rst : in std_ulogic;
rd_en_i : in std_ulogic;
rd_data_o : out data_type;
full_o : out std_ulogic;
wr_en_i : in std_ulogic;
wr_data_i : in data_type;
empty_o : out std_ulogic);
end entity fifo_generic;
architecture rtl of fifo_generic is
constant ADDR_WIDTH : natural := clog2(DEPTH);
signal wr_addr : unsigned(ADDR_WIDTH downto 0) := (others => '0');
signal rd_addr : unsigned(ADDR_WIDTH downto 0) := (others => '0');
signal full_or_empty : std_ulogic;
signal empty_not_full : std_ulogic;
begin
full_o <= full_or_empty and not empty_not_full;
empty_o <= full_or_empty and empty_not_full;
empty_not_full <= (wr_addr(ADDR_WIDTH) ?= rd_addr(ADDR_WIDTH));
full_or_empty <= (wr_addr(ADDR_WIDTH-1 downto 0) ?= rd_addr(ADDR_WIDTH-1 downto 0));
p_main: process (clk) is
begin
if rising_edge(clk) then
if wr_en_i then
wr_addr <= wr_addr + 1;
end if;
if rd_en_i then
rd_addr <= rd_addr + 1;
end if;
if rst then
wr_addr <= (others => '0');
rd_addr <= (others => '0');
end if;
end if;
end process p_main;
dpram: entity libstorage_1.dpram_generic
generic map (
data_type => data_type,
DEPTH => DEPTH)
port map (
clk => clk,
rd_en_i => rd_en_i,
rd_addr_i => rd_addr(ADDR_WIDTH-1 downto 0),
rd_data_o => rd_data_o,
wr_en_i => wr_en_i,
wr_addr_i => wr_addr(ADDR_WIDTH-1 downto 0),
wr_data_i => wr_data_i);
end architecture rtl;
|
isc
|
dh1dm/q27
|
src/vhdl/queens/xilinx/arbit_forward.vhdl
|
1
|
2814
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-------------------------------------------------------------------------------
-- This file is part of the Queens@TUD solver suite
-- for enumerating and counting the solutions of an N-Queens Puzzle.
--
-- Copyright (C) 2008-2015
-- Thomas B. Preusser <[email protected]>
-------------------------------------------------------------------------------
-- This design is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Affero General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Affero General Public License for more details.
--
-- You should have received a copy of the GNU Affero General Public License
-- along with this design. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity arbit_forward is
generic (
N : positive -- Length of Token Chain
);
port (
tin : in std_logic; -- Fed Token
have : in std_logic_vector(0 to N-1); -- Token Owner
pass : in std_logic_vector(0 to N-1); -- Token Passers
grnt : out std_logic_vector(0 to N-1); -- Token Output
tout : out std_logic -- Unused Token
);
end arbit_forward;
library UNISIM;
use UNISIM.vcomponents.all;
architecture rtl_xilinx of arbit_forward is
-- Intermediate Token Signals
signal q : std_logic_vector(0 to N);
begin
-- First MUXCY only with switching LUT
q(0) <= have(0) or (tin and pass(0));
MUXCY_inst : MUXCY
port map (
O => q(1), -- Carry output signal
CI => '1', -- Carry input signal
DI => '0', -- Data input signal
S => q(0) -- MUX select
);
grnt(0) <= tin and not pass(0);
genChain: for i in 1 to N-1 generate
signal p : std_logic;
begin
--q(i+1) <= have(i) or (q(i) and pass(i));
p <= pass(i) and not have(i);
MUXCY_inst : MUXCY
port map (
O => q(i+1), -- Carry output signal
CI => q(i), -- Carry input signal
DI => have(i), -- Data input signal
S => p -- MUX select
);
grnt(i) <= q(i) and not q(i+1);
end generate;
tout <= q(N);
end rtl_xilinx;
|
agpl-3.0
|
UnofficialRepos/OSVVM
|
SortListPkg_int.vhd
|
2
|
13651
|
--
-- File Name: SortListPkg_int.vhd
-- Design Unit Name: SortListPkg_int
-- Revision: STANDARD VERSION
--
-- Maintainer: Jim Lewis email: [email protected]
-- Contributor(s):
-- Jim Lewis [email protected]
--
-- Description:
-- Sorting utility for array of scalars
-- Uses protected type so as to shrink and expand the data structure
--
-- Developed for:
-- SynthWorks Design Inc.
-- VHDL Training Classes
-- 11898 SW 128th Ave. Tigard, Or 97223
-- http://www.SynthWorks.com
--
-- Revision History:
-- Date Version Description
-- 06/2008: 0.1 Initial revision
-- Numerous revisions for VHDL Testbenches and Verification
-- 02/2009: 1.0 First Public Released Version
-- 02/25/2009 1.1 Replaced reference to std_2008 with a reference to
-- ieee_proposed.standard_additions.all ;
-- 06/16/2010 1.2 Added EraseList parameter to to_array
-- 3/2011 2.0 added inside as non protected type
-- 6/2011 2.1 added sort as non protected type
-- 4/2013 2013.04 No Changes
-- 5/2013 2013.05 No changes of substance.
-- Deleted extra variable declaration in procedure remove
-- 1/2014 2014.01 Added RevSort. Added AllowDuplicate paramter to Add procedure
-- 1/2015 2015.01 Changed Assert/Report to Alert
-- 11/2016 2016.11 Revised Add. When AllowDuplicate, add a matching value last.
-- 01/2020 2020.01 Updated Licenses to Apache
--
--
-- This file is part of OSVVM.
--
-- Copyright (c) 2008 - 2020 by SynthWorks Design Inc.
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- https://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
use work.OsvvmGlobalPkg.all ;
use work.AlertLogPkg.all ;
use std.textio.all ;
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
use ieee.std_logic_textio.all ;
-- comment out following 2 lines with VHDL-2008. Leave in for VHDL-2002
-- library ieee_proposed ; -- remove with VHDL-2008
-- use ieee_proposed.standard_additions.all ; -- remove with VHDL-2008
package SortListPkg_int is
-- with VHDL-2008, convert package to generic package
-- convert subtypes ElementType and ArrayofElementType to generics
-- package SortListGenericPkg is
subtype ElementType is integer ;
subtype ArrayofElementType is integer_vector ;
impure function inside (constant E : ElementType; constant A : in ArrayofElementType) return boolean ;
impure function sort (constant A : in ArrayofElementType) return ArrayofElementType ;
impure function revsort (constant A : in ArrayofElementType) return ArrayofElementType ;
type SortListPType is protected
procedure add ( constant A : in ElementType ; constant AllowDuplicate : Boolean := FALSE ) ;
procedure add ( constant A : in ArrayofElementType ) ;
procedure add ( constant A : in ArrayofElementType ; Min, Max : ElementType ) ;
procedure add ( variable A : inout SortListPType ) ;
-- Count items in list
impure function count return integer ;
impure function find_index ( constant A : ElementType) return integer ;
impure function inside (constant A : ElementType) return boolean ;
procedure insert ( constant A : in ElementType; constant index : in integer := 1 ) ;
impure function get ( constant index : in integer := 1 ) return ElementType ;
procedure erase ;
impure function Empty return boolean ;
procedure print ;
procedure remove ( constant A : in ElementType ) ;
procedure remove ( constant A : in ArrayofElementType ) ;
procedure remove ( variable A : inout SortListPType ) ;
impure function to_array (constant EraseList : boolean := FALSE) return ArrayofElementType ;
impure function to_rev_array (constant EraseList : boolean := FALSE) return ArrayofElementType ;
end protected SortListPType ;
end SortListPkg_int ;
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
package body SortListPkg_int is
impure function inside (constant E : ElementType; constant A : in ArrayofElementType) return boolean is
begin
for i in A'range loop
if E = A(i) then
return TRUE ;
end if ;
end loop ;
return FALSE ;
end function inside ;
type SortListPType is protected body
type ListType ;
type ListPointerType is access ListType ;
type ListType is record
A : ElementType ;
-- item_num : integer ;
NextPtr : ListPointerType ;
-- PrevPtr : ListPointerType ;
end record ;
variable HeadPointer : ListPointerType := NULL ;
-- variable TailPointer : ListPointerType := NULL ;
procedure add ( constant A : in ElementType ; constant AllowDuplicate : Boolean := FALSE ) is
variable CurPtr, tempPtr : ListPointerType ;
begin
if HeadPointer = NULL then
HeadPointer := new ListType'(A, NULL) ;
elsif A = HeadPointer.A then -- ignore duplicates
if AllowDuplicate then
tempPtr := HeadPointer ;
HeadPointer := new ListType'(A, tempPtr) ;
end if ;
elsif A < HeadPointer.A then
tempPtr := HeadPointer ;
HeadPointer := new ListType'(A, tempPtr) ;
else
CurPtr := HeadPointer ;
AddLoop : loop
exit AddLoop when CurPtr.NextPtr = NULL ;
exit AddLoop when A < CurPtr.NextPtr.A ;
if A = CurPtr.NextPtr.A then
-- if AllowDuplicate then -- changed s.t. insert at after match rather than before
-- exit AddLoop ; -- insert
-- else
if not AllowDuplicate then
return ; -- return without insert
end if;
end if ;
CurPtr := CurPtr.NextPtr ;
end loop AddLoop ;
tempPtr := CurPtr.NextPtr ;
CurPtr.NextPtr := new ListType'(A, tempPtr) ;
end if ;
end procedure add ;
procedure add ( constant A : in ArrayofElementType ) is
begin
for i in A'range loop
add(A(i)) ;
end loop ;
end procedure add ;
procedure add ( constant A : in ArrayofElementType ; Min, Max : ElementType ) is
begin
for i in A'range loop
if A(i) >= Min and A(i) <= Max then
add(A(i)) ;
end if ;
end loop ;
end procedure add ;
procedure add ( variable A : inout SortListPType ) is
begin
for i in 1 to A.Count loop
add(A.Get(i)) ;
end loop ;
end procedure add ;
-- Count items in list
impure function count return integer is
variable result : positive := 1 ;
variable CurPtr : ListPointerType ;
begin
if HeadPointer = NULL then
return 0 ;
else
CurPtr := HeadPointer ;
loop
exit when CurPtr.NextPtr = NULL ;
result := result + 1 ;
CurPtr := CurPtr.NextPtr ;
end loop ;
return result ;
end if ;
end function count ;
impure function find_index (constant A : ElementType) return integer is
variable result : positive := 2 ;
variable CurPtr : ListPointerType ;
begin
if HeadPointer = NULL then
return 0 ;
elsif A <= HeadPointer.A then
return 1 ;
else
CurPtr := HeadPointer ;
loop
exit when CurPtr.NextPtr = NULL ;
exit when A <= CurPtr.NextPtr.A ;
result := result + 1 ;
CurPtr := CurPtr.NextPtr ;
end loop ;
return result ;
end if ;
end function find_index ;
impure function inside (constant A : ElementType) return boolean is
variable CurPtr : ListPointerType ;
begin
if HeadPointer = NULL then
return FALSE ;
end if ;
if A = HeadPointer.A then
return TRUE ;
else
CurPtr := HeadPointer ;
loop
exit when CurPtr.NextPtr = NULL ;
exit when A < CurPtr.NextPtr.A ;
if A = CurPtr.NextPtr.A then
return TRUE ; -- exit
end if;
CurPtr := CurPtr.NextPtr ;
end loop ;
end if ;
return FALSE ;
end function inside ;
procedure insert( constant A : in ElementType; constant index : in integer := 1 ) is
variable CurPtr, tempPtr : ListPointerType ;
begin
if index <= 1 then
tempPtr := HeadPointer ;
HeadPointer := new ListType'(A, tempPtr) ;
else
CurPtr := HeadPointer ;
for i in 3 to index loop
exit when CurPtr.NextPtr = NULL ; -- end of list
CurPtr := CurPtr.NextPtr ;
end loop ;
tempPtr := CurPtr.NextPtr ;
CurPtr.NextPtr := new ListType'(A, tempPtr) ;
end if;
end procedure insert ;
impure function get ( constant index : in integer := 1 ) return ElementType is
variable CurPtr : ListPointerType ;
begin
if index > Count then
Alert(OSVVM_ALERTLOG_ID, "SortLIstPkg_int.get index out of range", FAILURE) ;
return ElementType'left ;
elsif HeadPointer = NULL then
return ElementType'left ;
elsif index <= 1 then
return HeadPointer.A ;
else
CurPtr := HeadPointer ;
for i in 2 to index loop
CurPtr := CurPtr.NextPtr ;
end loop ;
return CurPtr.A ;
end if;
end function get ;
procedure erase (variable CurPtr : inout ListPointerType ) is
begin
if CurPtr.NextPtr /= NULL then
erase (CurPtr.NextPtr) ;
end if ;
deallocate (CurPtr) ;
end procedure erase ;
procedure erase is
begin
if HeadPointer /= NULL then
erase(HeadPointer) ;
-- deallocate (HeadPointer) ;
HeadPointer := NULL ;
end if;
end procedure erase ;
impure function Empty return boolean is
begin
return HeadPointer = NULL ;
end Empty ;
procedure print is
variable buf : line ;
variable CurPtr : ListPointerType ;
begin
if HeadPointer = NULL then
write (buf, string'("( )")) ;
else
CurPtr := HeadPointer ;
write (buf, string'("(")) ;
loop
write (buf, CurPtr.A) ;
exit when CurPtr.NextPtr = NULL ;
write (buf, string'(", ")) ;
CurPtr := CurPtr.NextPtr ;
end loop ;
write (buf, string'(")")) ;
end if ;
writeline(OUTPUT, buf) ;
end procedure print ;
procedure remove ( constant A : in ElementType ) is
variable CurPtr, tempPtr : ListPointerType ;
begin
if HeadPointer = NULL then
return ;
elsif A = HeadPointer.A then
tempPtr := HeadPointer ;
HeadPointer := HeadPointer.NextPtr ;
deallocate (tempPtr) ;
else
CurPtr := HeadPointer ;
loop
exit when CurPtr.NextPtr = NULL ;
if A = CurPtr.NextPtr.A then
tempPtr := CurPtr.NextPtr ;
CurPtr.NextPtr := CurPtr.NextPtr.NextPtr ;
deallocate (tempPtr) ;
exit ;
end if ;
exit when A < CurPtr.NextPtr.A ;
CurPtr := CurPtr.NextPtr ;
end loop ;
end if ;
end procedure remove ;
procedure remove ( constant A : in ArrayofElementType ) is
begin
for i in A'range loop
remove(A(i)) ;
end loop ;
end procedure remove ;
procedure remove ( variable A : inout SortListPType ) is
begin
for i in 1 to A.Count loop
remove(A.Get(i)) ;
end loop ;
end procedure remove ;
impure function to_array (constant EraseList : boolean := FALSE) return ArrayofElementType is
variable result : ArrayofElementType(1 to Count) ;
begin
for i in 1 to Count loop
result(i) := Get(i) ;
end loop ;
if EraseList then
erase ;
end if ;
return result ;
end function to_array ;
impure function to_rev_array (constant EraseList : boolean := FALSE) return ArrayofElementType is
variable result : ArrayofElementType(Count downto 1) ;
begin
for i in 1 to Count loop
result(i) := Get(i) ;
end loop ;
if EraseList then
erase ;
end if ;
return result ;
end function to_rev_array ;
end protected body SortListPType ;
impure function sort (constant A : in ArrayofElementType) return ArrayofElementType is
variable Result : SortListPType ;
begin
for i in A'range loop
Result.Add(A(i), TRUE) ;
end loop ;
return Result.to_array(EraseList => TRUE) ;
end function sort ;
impure function revsort (constant A : in ArrayofElementType) return ArrayofElementType is
variable Result : SortListPType ;
begin
for i in A'range loop
Result.Add(A(i), TRUE) ;
end loop ;
return Result.to_rev_array(EraseList => TRUE) ;
end function revsort ;
end SortListPkg_int ;
|
artistic-2.0
|
mediocregopher/chdl
|
src/chdl_examples/beta/basic.vhd
|
1
|
511
|
ENTITY xorer IS
PORT(inSig0 : in BIT;
inSig1 : in BIT;
inSig2 : in BIT;
inSig3 : in BIT;
inSig4 : in BIT;
inSig5 : in BIT;
inSig6 : in BIT;
inSig7 : in BIT;
outSig0 : out BIT;
outSig1 : out BIT;
outSig2 : out BIT;
outSig3 : out BIT);
BEGIN
END ENTITY xorer;
ARCHITECTURE arch OF xorer IS
BEGIN
outSig0 <= (inSig0 xor inSig1);
outSig1 <= (inSig2 xor inSig3);
outSig2 <= (inSig4 xor inSig5);
outSig3 <= (inSig6 xor inSig7);
END ARCHITECTURE arch;
|
epl-1.0
|
capitanov/fp23_logic
|
fp23_rtl/fp23_op/fp23_fix2float.vhd
|
1
|
7928
|
-------------------------------------------------------------------------------
--
-- Title : fp23_fix2float
-- Design : fpfftk
-- Author : Kapitanov
-- Company :
--
-------------------------------------------------------------------------------
--
-- Description : Signed fix 16 bit to float fp23 converter
--
-------------------------------------------------------------------------------
--
-- Version 1.0 25.05.2013
-- Description:
-- Bus width for:
-- din = 15
-- dout = 23
-- exp = 6
-- sign = 1
-- mant = 15 + 1
-- Math expression:
-- A = (-1)^sign(A) * 2^(exp(A)-31) * mant(A)
-- NB:
-- 1's complement
-- Converting from fixed to float takes only 9 clock cycles
--
-- MODES: Mode0 : normal fix2float (1's complement data)
-- Mode1 : +1 fix2float for negative data (uncomment and
-- change this code a little: add a component
-- sp_addsub_m1 and some signals): 2's complement data.
--
--
-- Version 1.1 15.01.2015
-- Description:
-- Based on fp27_fix2float_m3 (FP27 FORMAT)
-- New version of FP (Reduced fraction width)
--
-- Version 1.2 18.03.2015
-- Description:
-- Changed CE signal
-- This version has ena. See OR5+OR5 stages
--
-- Version 1.3 24.03.2015
-- Description:
-- Deleted ENABLE signal
-- This version is fully pipelined !!!
--
-- Version 1.4 04.10.2015
-- Description:
-- DSP48E1 has been removed. Barrel shift is used now.
-- Delay 9 clocks
--
-- Version 1.5 04.01.2016
-- Description:
-- New barrel shifter with minimum resources.
-- New FP format: FP24 -> FP23.
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- The MIT License (MIT)
-- Copyright (c) 2016 Kapitanov Alexander
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"),
-- to deal in the Software without restriction, including without limitation
-- the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- and/or sell copies of the Software, and to permit persons to whom the
-- Software is furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-- THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
-- IN THE SOFTWARE.
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library work;
use work.fp_m1_pkg.fp23_data;
use work.reduce_pack.nor_reduce;
entity fp23_fix2float is
port(
din : in std_logic_vector(15 downto 0); --! Fixed input data
ena : in std_logic; --! Data enable
dout : out fp23_data; --! Float output data
vld : out std_logic; --! Data out valid
clk : in std_logic; --! Clock
reset : in std_logic --! Negative Reset
);
end fp23_fix2float;
architecture fp23_fix2float of fp23_fix2float is
constant FP32_EXP : std_logic_vector(5 downto 0):="011111";
signal true_form : std_logic_vector(15 downto 0):=(others => '0');
signal norm : std_logic_vector(15 downto 0);
signal frac : std_logic_vector(15 downto 0);
signal set_zero : std_logic;
signal sum_man : std_logic_vector(15 downto 0);
signal msb_num : std_logic_vector(4 downto 0);
signal msb_numn : std_logic_vector(5 downto 0);
signal msb_numt : std_logic_vector(4 downto 0);
signal msb_numz : std_logic_vector(5 downto 0);
signal expc : std_logic_vector(5 downto 0); -- (E - 127) by (IEEE754)
signal sign : std_logic_vector(2 downto 0);
signal valid : std_logic_vector(4 downto 0);
--signal dinz : std_logic_vector(15 downto 0);
signal dinz : std_logic_vector(15 downto 0);
signal dinh : std_logic;
signal dinx : std_logic;
begin
-- x2S_COMPL: if (IS_CMPL = TRUE) generate
pr_sgn: process(clk) is
begin
if rising_edge(clk) then
dinz <= din - din(15);
dinh <= din(15);
end if;
end process;
---- make abs(data) by using XOR ----
pr_abs: process(clk) is
begin
if rising_edge(clk) then
true_form(15) <= dinz(15) or dinh;
for ii in 0 to 14 loop
true_form(ii) <= dinz(ii) xor (dinz(15) or dinh);
end loop;
end if;
end process;
sum_man <= true_form(14 downto 0) & '0' when rising_edge(clk);
---- find MSB (highest '1' position) ----
pr_lead: process(clk) is
begin
if rising_edge(clk) then
if (true_form(14-00)='1') then msb_num <= "00001";--"00010";--"00001";
elsif (true_form(14-01)='1') then msb_num <= "00010";--"00011";--"00010";
elsif (true_form(14-02)='1') then msb_num <= "00011";--"00100";--"00011";
elsif (true_form(14-03)='1') then msb_num <= "00100";--"00101";--"00100";
elsif (true_form(14-04)='1') then msb_num <= "00101";--"00110";--"00101";
elsif (true_form(14-05)='1') then msb_num <= "00110";--"00111";--"00110";
elsif (true_form(14-06)='1') then msb_num <= "00111";--"01000";--"00111";
elsif (true_form(14-07)='1') then msb_num <= "01000";--"01001";--"01000";
elsif (true_form(14-08)='1') then msb_num <= "01001";--"01010";--"01001";
elsif (true_form(14-09)='1') then msb_num <= "01010";--"01011";--"01010";
elsif (true_form(14-10)='1') then msb_num <= "01011";--"01100";--"01011";
elsif (true_form(14-11)='1') then msb_num <= "01100";--"01101";--"01100";
elsif (true_form(14-12)='1') then msb_num <= "01101";--"01110";--"01101";
elsif (true_form(14-13)='1') then msb_num <= "01110";--"01111";--"01110";
elsif (true_form(14-14)='1') then msb_num <= "01111";--"10000";--"01111";
else msb_num <= "00000";
end if;
end if;
end process;
dinx <= dinz(15) xor dinh when rising_edge(clk);
msb_numz(5) <= dinx when rising_edge(clk);
msb_numz(4 downto 0) <= msb_num;
msb_numt <= msb_num when rising_edge(clk);
---- barrel shifter by 0-15 ----
norm <= STD_LOGIC_VECTOR(SHL(UNSIGNED(sum_man), UNSIGNED(msb_num))) when rising_edge(clk);
frac <= norm when rising_edge(clk);
---- Check zero value for fraction and exponent ----
set_zero <= nor_reduce(msb_numz) when rising_edge(clk);
---- find exponent (inv msb - x"2E") ----
pr_sub: process(clk) is
begin
if rising_edge(clk) then
if (set_zero = '1') then
expc <= (others=>'0');
else
expc <= FP32_EXP - msb_numt;
end if;
end if;
end process;
---- sign delay ----
sign <= sign(sign'left-1 downto 0) & true_form(15) when rising_edge(clk);
---- output data ----
pr_out: process(clk) is
begin
if rising_edge(clk) then
if (reset = '1') then
dout <= ("000000", '0', x"0000");
elsif (valid(valid'left) = '1') then
dout <= (expc, sign(sign'left), frac);
end if;
end if;
end process;
valid <= valid(valid'left-1 downto 0) & ena when rising_edge(clk);
vld <= valid(valid'left) when rising_edge(clk);
end fp23_fix2float;
|
mit
|
ViniciusLambardozzi/quanta
|
Hardware/quanta/src/vhdl/util/Adder.vhd
|
1
|
2226
|
------------------------------------
-- 32 BIT CARRY LOOK AHEAD ADDER --
-- PORT MAPPING --
-- A : 32 bit input value --
-- B : 32 bit input value --
-- CIN : 1 bit input carry --
------------------------------------
-- C : 32 bit output value A+B --
-- COUT : 1 bit output carry --
------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY adder IS
PORT
(
in_a : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
in_b : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
in_cin : IN STD_LOGIC;
---------------------------------------------
out_c : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
out_cout : OUT STD_LOGIC
);
END adder;
ARCHITECTURE behavioral OF adder IS
-- Sum values without carry
SIGNAL s_sum : STD_LOGIC_VECTOR(31 DOWNTO 0);
-- Carry generators
SIGNAL s_generate : STD_LOGIC_VECTOR(31 DOWNTO 0);
-- Carry propagators
SIGNAL s_propagate : STD_LOGIC_VECTOR(31 DOWNTO 0);
-- Calculated carry values
SIGNAL s_carry : STD_LOGIC_VECTOR(31 DOWNTO 1);
BEGIN
-- Calculate the sum a + b discarding carry
s_sum <= in_a XOR in_b;
-- Calculate carry generators
s_generate <= in_a AND in_b;
-- Calculate carry propagators
s_propagate <= in_a OR in_b;
-- Pre calculate each carry
PROCESS(s_generate, s_propagate, s_carry, in_cin)
BEGIN
-- C(i+1) = G(i) + (P(i)C(i))
-- Calculate base case
s_carry(1) <= s_generate(0) OR (s_propagate(0) AND in_cin);
FOR i IN 1 TO 30 LOOP
-- Recursively calculate all intermediate carries
s_carry(i + 1) <= s_generate(i) OR (s_propagate(i) AND s_carry(i));
END LOOP;
-- Calculate carry out --
out_cout <= s_generate(31) OR (s_propagate(31) AND s_carry(31));
END PROCESS;
-- Calculate final sum --
out_c(0) <= s_sum(0) XOR in_cin;
out_c(31 DOWNTO 1) <= s_sum(31 DOWNTO 1) XOR s_carry(31 DOWNTO 1);
END behavioral;
|
mit
|
capitanov/fp23_logic
|
fp23_rtl/fp23_test/fp23_complex_tst_m1.vhd
|
1
|
7680
|
-------------------------------------------------------------------------------
--
-- Title : fp23_complex_tst_m1
-- Design : fpfftk
-- Author : Kapitanov
-- Company :
--
-------------------------------------------------------------------------------
--
-- Description : floating point multiplier
--
-------------------------------------------------------------------------------
--
-- Version 1.0 19.12.2015
-- Description: Complex floating point multiplier for tests only
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- The MIT License (MIT)
-- Copyright (c) 2016 Kapitanov Alexander
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"),
-- to deal in the Software without restriction, including without limitation
-- the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- and/or sell copies of the Software, and to permit persons to whom the
-- Software is furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-- THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
-- IN THE SOFTWARE.
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
library work;
use work.fp_m1_pkg.all;
entity fp23_complex_tst_m1 is
generic (
td : time:=1ns --! Time delay for simulation
);
port(
ARE : in STD_LOGIC_VECTOR(15 downto 0); --! Real part of A
AIM : in STD_LOGIC_VECTOR(15 downto 0); --! Imag part of A
BRE : in STD_LOGIC_VECTOR(15 downto 0); --! Real part of B
BIM : in STD_LOGIC_VECTOR(15 downto 0); --! Imag part of B
ENA : in STD_LOGIC; --! Input data enable
CRE : out STD_LOGIC_VECTOR(15 downto 0); --! Real part of C
CIM : out STD_LOGIC_VECTOR(15 downto 0); --! Imag part of C
VAL : out STD_LOGIC; --! Output data valid
SCALE : in STD_LOGIC_VECTOR(05 downto 0); --! SCALE for FP converter
RESET : in STD_LOGIC; --! Reset
CLK : in STD_LOGIC --! Clock
);
end fp23_complex_tst_m1;
architecture test_fp23_cm_m1 of fp23_complex_tst_m1 is
signal are_z : std_logic_vector(15 downto 0);
signal aim_z : std_logic_vector(15 downto 0);
signal bre_z : std_logic_vector(15 downto 0);
signal bim_z : std_logic_vector(15 downto 0);
signal ena_z : std_logic_vector(03 downto 0);
signal rst : std_logic_vector(11 downto 0);
signal fp23_aa : fp23_complex;
signal fp23_bb : fp23_complex;
signal fp23_val : std_logic;
signal fp23_are_bre : fp23_data;
signal fp23_are_bim : fp23_data;
signal fp23_aim_bre : fp23_data;
signal fp23_aim_bim : fp23_data;
signal fp23_mult : std_logic;
signal fp23_cc : fp23_complex;
signal fp23_add : std_logic;
signal fix_cc_re : std_logic_vector(15 downto 0);
signal fix_cc_im : std_logic_vector(15 downto 0);
signal fix_val : std_logic;
signal scale_z : std_logic_vector(5 downto 0);
begin
are_z <= ARE after td when rising_edge(clk);
aim_z <= AIM after td when rising_edge(clk);
bre_z <= BRE after td when rising_edge(clk);
bim_z <= BIM after td when rising_edge(clk);
---------------- FIX2FLOAT CONVERTER ----------------
ARE_CONV : entity work.fp23_fix2float
generic map( td => td)
port map (
din => are_z,
ena => ena_z(0),
dout => fp23_aa.re,
vld => fp23_val,
reset => rst(0),
clk => clk
);
AIM_CONV : entity work.fp23_fix2float
generic map( td => td)
port map (
din => aim_z,
ena => ena_z(1),
dout => fp23_aa.im,
vld => open,
reset => rst(1),
clk => clk
);
BRE_CONV : entity work.fp23_fix2float
generic map( td => td)
port map (
din => bre_z,
ena => ena_z(2),
dout => fp23_bb.re,
vld => open,
reset => rst(2),
clk => clk
);
BIM_CONV : entity work.fp23_fix2float
port map (
din => bim_z,
ena => ena_z(3),
dout => fp23_bb.im,
vld => open,
reset => rst(3),
clk => clk
);
---------------- FlOAT MULTIPLY A*B ----------------
ARExBRE : entity work.fp23_mult
generic map( td => td)
port map (
aa => fp23_aa.re,
bb => fp23_bb.re,
cc => fp23_are_bre,
enable => fp23_val,
valid => fp23_mult,
reset => rst(4),
clk => clk
);
AIMxBIM : entity work.fp23_mult
port map(
aa => fp23_aa.im,
bb => fp23_bb.im,
cc => fp23_aim_bim,
enable => fp23_val,
valid => open,
reset => rst(5),
clk => clk
);
ARExBIM : entity work.fp23_mult
generic map( td => td)
port map (
aa => fp23_aa.re,
bb => fp23_bb.im,
cc => fp23_are_bim,
enable => fp23_val,
valid => open,
reset => rst(6),
clk => clk
);
AIMxBRE : entity work.fp23_mult
generic map( td => td)
port map (
aa => fp23_aa.im,
bb => fp23_bb.re,
cc => fp23_aim_bre,
enable => fp23_val,
valid => open,
reset => rst(7),
clk => clk
);
---------------- FlOAT ADD/SUB +/- ----------------
AB_ADD : entity work.fp23_addsub
generic map( td => td)
port map (
aa => fp23_are_bim,
bb => fp23_aim_bre,
cc => fp23_cc.im,
addsub => '0',
enable => fp23_mult,
valid => fp23_add,
reset => rst(8),
clk => clk
);
AB_SUB : entity work.fp23_addsub
generic map( td => td)
port map (
aa => fp23_are_bre,
bb => fp23_aim_bim,
cc => fp23_cc.re,
addsub => '1',
enable => fp23_mult,
valid => open,
reset => rst(9),
clk => clk
);
---------------- FLOAT TO FIX ----------------
scale_z <= scale after td when rising_edge(clk);
FIX_RE : entity work.fp23_float2fix
generic map( td => td)
port map (
din => fp23_cc.re,
ena => fp23_add,
dout => fix_cc_re,
vld => fix_val,
scale => scale_z,
reset => rst(10),
clk => clk,
overflow => open
);
FIX_IM : entity work.fp23_float2fix
generic map( td => td)
port map (
din => fp23_cc.im,
ena => fp23_add,
dout => fix_cc_im,
vld => open,
scale => scale_z,
reset => rst(11),
clk => clk,
overflow => open
);
CRE <= fix_cc_re after td when rising_edge(clk);
CIM <= fix_cc_im after td when rising_edge(clk);
VAL <= fix_val after td when rising_edge(clk);
G_ENA: for ii in 0 to 3 generate
ena_z(ii) <= ENA after td when rising_edge(clk);
end generate;
G_RST: for ii in 0 to 11 generate
rst(ii) <= RESET after td when rising_edge(clk);
end generate;
end test_fp23_cm_m1;
|
mit
|
ViniciusLambardozzi/quanta
|
Hardware/quanta/simulation/qsim/work/quanta_vlg_vec_tst/_primary.vhd
|
1
|
96
|
library verilog;
use verilog.vl_types.all;
entity quanta_vlg_vec_tst is
end quanta_vlg_vec_tst;
|
mit
|
ViniciusLambardozzi/quanta
|
Hardware/quanta/src/vhdl/util/Range.vhd
|
1
|
322
|
LIBRARY ieee;
USE ieee.numeric_std.ALL;
PACKAGE range_util IS
FUNCTION range_start(base, size : POSITIVE) return POSITIVE;
END PACKAGE;
PACKAGE BODY range_util IS
FUNCTION range_start(base, size : POSITIVE) return POSITIVE IS
BEGIN
RETURN base + size - 1;
END FUNCTION;
END PACKAGE BODY;
|
mit
|
ViniciusLambardozzi/quanta
|
Hardware/quanta/simulation/qsim/work/quanta_vlg_check_tst/_primary.vhd
|
1
|
718
|
library verilog;
use verilog.vl_types.all;
entity quanta_vlg_check_tst is
port(
hex0 : in vl_logic_vector(6 downto 0);
hex1 : in vl_logic_vector(6 downto 0);
hex2 : in vl_logic_vector(6 downto 0);
hex3 : in vl_logic_vector(6 downto 0);
hex4 : in vl_logic_vector(6 downto 0);
hex5 : in vl_logic_vector(6 downto 0);
hex6 : in vl_logic_vector(6 downto 0);
hex7 : in vl_logic_vector(6 downto 0);
pc : in vl_logic_vector(31 downto 0);
sampler_rx : in vl_logic
);
end quanta_vlg_check_tst;
|
mit
|
ViniciusLambardozzi/quanta
|
Hardware/quanta/src/vhdl/controllers/io/LCDController.vhd
|
3
|
8014
|
--------------------------------------------------------------------------------
--
-- FileName: lcd_controller.vhd
-- Dependencies: none
-- Design Software: Quartus II 32-bit Version 11.1 Build 173 SJ Full Version
--
-- HDL CODE IS PROVIDED "AS IS." DIGI-KEY EXPRESSLY DISCLAIMS ANY
-- WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
-- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL DIGI-KEY
-- BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL
-- DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF
-- PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS
-- BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF),
-- ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS.
--
-- Version History
-- Version 1.0 6/2/2006 Scott Larson
-- Initial Public Release
-- Version 2.0 6/13/2012 Scott Larson
--
-- CLOCK FREQUENCY: to change system clock frequency, change Line 65
--
-- LCD INITIALIZATION SETTINGS: to change, comment/uncomment lines:
--
-- Function Set
-- 2-line mode, display on Line 93 lcd_data <= "00111100";
-- 1-line mode, display on Line 94 lcd_data <= "00110100";
-- 1-line mode, display off Line 95 lcd_data <= "00110000";
-- 2-line mode, display off Line 96 lcd_data <= "00111000";
-- Display ON/OFF
-- display on, cursor off, blink off Line 104 lcd_data <= "00001100";
-- display on, cursor off, blink on Line 105 lcd_data <= "00001101";
-- display on, cursor on, blink off Line 106 lcd_data <= "00001110";
-- display on, cursor on, blink on Line 107 lcd_data <= "00001111";
-- display off, cursor off, blink off Line 108 lcd_data <= "00001000";
-- display off, cursor off, blink on Line 109 lcd_data <= "00001001";
-- display off, cursor on, blink off Line 110 lcd_data <= "00001010";
-- display off, cursor on, blink on Line 111 lcd_data <= "00001011";
-- Entry Mode Set
-- increment mode, entire shift off Line 127 lcd_data <= "00000110";
-- increment mode, entire shift on Line 128 lcd_data <= "00000111";
-- decrement mode, entire shift off Line 129 lcd_data <= "00000100";
-- decrement mode, entire shift on Line 130 lcd_data <= "00000101";
--
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY lcd_controller IS
PORT(
clk : IN STD_LOGIC; --system clock
reset_n : IN STD_LOGIC; --active low reinitializes lcd
lcd_enable : IN STD_LOGIC; --latches data into lcd controller
lcd_bus : IN STD_LOGIC_VECTOR(9 DOWNTO 0); --data and control signals
busy : OUT STD_LOGIC := '1'; --lcd controller busy/idle feedback
rw, rs, e : OUT STD_LOGIC; --read/write, setup/data, and enable for lcd
lcd_data : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); --data signals for lcd
END lcd_controller;
ARCHITECTURE controller OF lcd_controller IS
TYPE CONTROL IS(power_up, initialize, ready, send);
SIGNAL state : CONTROL;
CONSTANT freq : INTEGER := 50; --system clock frequency in MHz
BEGIN
PROCESS(clk)
VARIABLE clk_count : INTEGER := 0; --event counter for timing
BEGIN
IF(clk'EVENT and clk = '1') THEN
CASE state IS
--wait 50 ms to ensure Vdd has risen and required LCD wait is met
WHEN power_up =>
busy <= '1';
IF(clk_count < (50000 * freq)) THEN --wait 50 ms
clk_count := clk_count + 1;
state <= power_up;
ELSE --power-up complete
clk_count := 0;
rs <= '0';
rw <= '0';
lcd_data <= "00110000";
state <= initialize;
END IF;
--cycle through initialization sequence
WHEN initialize =>
busy <= '1';
clk_count := clk_count + 1;
IF(clk_count < (10 * freq)) THEN --function set
lcd_data <= "00111100"; --2-line mode, display on
--lcd_data <= "00110100"; --1-line mode, display on
--lcd_data <= "00110000"; --1-line mdoe, display off
--lcd_data <= "00111000"; --2-line mode, display off
e <= '1';
state <= initialize;
ELSIF(clk_count < (60 * freq)) THEN --wait 50 us
lcd_data <= "00000000";
e <= '0';
state <= initialize;
ELSIF(clk_count < (70 * freq)) THEN --display on/off control
lcd_data <= "00001100"; --display on, cursor off, blink off
--lcd_data <= "00001101"; --display on, cursor off, blink on
--lcd_data <= "00001110"; --display on, cursor on, blink off
--lcd_data <= "00001111"; --display on, cursor on, blink on
--lcd_data <= "00001000"; --display off, cursor off, blink off
--lcd_data <= "00001001"; --display off, cursor off, blink on
--lcd_data <= "00001010"; --display off, cursor on, blink off
--lcd_data <= "00001011"; --display off, cursor on, blink on
e <= '1';
state <= initialize;
ELSIF(clk_count < (120 * freq)) THEN --wait 50 us
lcd_data <= "00000000";
e <= '0';
state <= initialize;
ELSIF(clk_count < (130 * freq)) THEN --display clear
lcd_data <= "00000001";
e <= '1';
state <= initialize;
ELSIF(clk_count < (2130 * freq)) THEN --wait 2 ms
lcd_data <= "00000000";
e <= '0';
state <= initialize;
ELSIF(clk_count < (2140 * freq)) THEN --entry mode set
lcd_data <= "00000110"; --increment mode, entire shift off
--lcd_data <= "00000111"; --increment mode, entire shift on
--lcd_data <= "00000100"; --decrement mode, entire shift off
--lcd_data <= "00000101"; --decrement mode, entire shift on
e <= '1';
state <= initialize;
ELSIF(clk_count < (2200 * freq)) THEN --wait 60 us
lcd_data <= "00000000";
e <= '0';
state <= initialize;
ELSE --initialization complete
clk_count := 0;
busy <= '0';
state <= ready;
END IF;
--wait for the enable signal and then latch in the instruction
WHEN ready =>
IF(lcd_enable = '1') THEN
busy <= '1';
rs <= lcd_bus(9);
rw <= lcd_bus(8);
lcd_data <= lcd_bus(7 DOWNTO 0);
clk_count := 0;
state <= send;
ELSE
busy <= '0';
rs <= '0';
rw <= '0';
lcd_data <= "00000000";
clk_count := 0;
state <= ready;
END IF;
--send instruction to lcd
WHEN send =>
busy <= '1';
IF(clk_count < (50 * freq)) THEN --do not exit for 50us
busy <= '1';
IF(clk_count < freq) THEN --negative enable
e <= '0';
ELSIF(clk_count < (14 * freq)) THEN --positive enable half-cycle
e <= '1';
ELSIF(clk_count < (27 * freq)) THEN --negative enable half-cycle
e <= '0';
END IF;
clk_count := clk_count + 1;
state <= send;
ELSE
clk_count := 0;
state <= ready;
END IF;
END CASE;
--reset
IF(reset_n = '0') THEN
state <= power_up;
END IF;
END IF;
END PROCESS;
END controller;
|
mit
|
wcandillon/linguist
|
samples/VHDL/foo.vhd
|
91
|
217
|
-- VHDL example file
library ieee;
use ieee.std_logic_1164.all;
entity inverter is
port(a : in std_logic;
b : out std_logic);
end entity;
architecture rtl of inverter is
begin
b <= not a;
end architecture;
|
mit
|
FearlessJojo/COPproject
|
project/RAM.vhd
|
1
|
2599
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:59:33 11/03/2016
-- Design Name:
-- Module Name: RAM - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity RAM is
Port (
CLK : in STD_LOGIC;
ACCMEM : in STD_LOGIC;
MEM_WE : in STD_LOGIC;
addr : inout STD_LOGIC_VECTOR (15 downto 0);
data : inout STD_LOGIC_VECTOR (15 downto 0);
Ram1Addr : out STD_LOGIC_VECTOR (17 downto 0);
Ram1Data : inout STD_LOGIC_VECTOR (15 downto 0);
Ram1OE : out STD_LOGIC;
Ram1WE : out STD_LOGIC;
Ram1EN : out STD_LOGIC;
wrn : out STD_LOGIC;
rdn : out STD_LOGIC);
end RAM;
architecture Behavioral of RAM is
signal state1 : integer range 0 to 3 := 0;
signal state2 : integer range 0 to 10 := 0;
begin
wrn <= '1';
rdn <= '1';
Ram1Addr(17 downto 16) <= "00";
process(CLK)
begin
if (MEM_WE = '0') and (ACCMEM = '1') then
if (CLK'EVENT) and (CLK = '1') then
case state1 is
when 0 =>
state1 <= 1;
Ram1EN <= '1';
when 1 =>
state1 <= 2;
Ram1EN <= '0';
Ram1OE <= '1';
Ram1WE <= '1';
when 2 =>
state1 <= 3;
RAM1Addr(15 downto 0) <= addr;
RAM1Data <= data;
Ram1WE <= '1';
when 3 =>
Ram1WE <= '0';
state1 <= 0;
when others =>
null;
end case;
end if;
end if;
end process;
process(CLK)
begin
if (MEM_WE = '1') and (ACCMEM = '0') then
if (CLK'EVENT) and (CLK = '1') then
case state2 is
when 0 =>
state2 <= 1;
Ram1EN <= '0';
Ram1OE <= '0';
Ram1WE <= '1';
when 1 =>
state2 <= 2;
RAM1Data <= "ZZZZZZZZZZZZZZZZ";
when 2 =>
state2 <= 3;
RAM1Addr(15 downto 0) <= addr;
when 3 =>
data <= Ram1Data;
state2 <= 0;
when others =>
null;
end case;
end if;
end if;
end process;
end Behavioral;
|
mit
|
corywalker/vhdl_fft
|
spi_master_slave/rtl/spi_master_slave/spi_loopback.vhd
|
4
|
5952
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 23:44:37 05/17/2011
-- Design Name:
-- Module Name: spi_loopback - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- This is a simple wrapper for the 'spi_master' and 'spi_slave' cores, to synthesize the 2 cores and
-- test them in the simulator.
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.all;
entity spi_loopback is
Generic (
N : positive := 32; -- 32bit serial word length is default
CPOL : std_logic := '0'; -- SPI mode selection (mode 0 default)
CPHA : std_logic := '1'; -- CPOL = clock polarity, CPHA = clock phase.
PREFETCH : positive := 2; -- prefetch lookahead cycles
SPI_2X_CLK_DIV : positive := 5 -- for a 100MHz sclk_i, yields a 10MHz SCK
);
Port(
----------------MASTER-----------------------
m_clk_i : IN std_logic;
m_rst_i : IN std_logic;
m_spi_ssel_o : OUT std_logic;
m_spi_sck_o : OUT std_logic;
m_spi_mosi_o : OUT std_logic;
m_spi_miso_i : IN std_logic;
m_di_req_o : OUT std_logic;
m_di_i : IN std_logic_vector(N-1 downto 0);
m_wren_i : IN std_logic;
m_do_valid_o : OUT std_logic;
m_do_o : OUT std_logic_vector(N-1 downto 0);
----- debug -----
m_do_transfer_o : OUT std_logic;
m_wren_o : OUT std_logic;
m_wren_ack_o : OUT std_logic;
m_rx_bit_reg_o : OUT std_logic;
m_state_dbg_o : OUT std_logic_vector(5 downto 0);
m_core_clk_o : OUT std_logic;
m_core_n_clk_o : OUT std_logic;
m_sh_reg_dbg_o : OUT std_logic_vector(N-1 downto 0);
----------------SLAVE-----------------------
s_clk_i : IN std_logic;
s_spi_ssel_i : IN std_logic;
s_spi_sck_i : IN std_logic;
s_spi_mosi_i : IN std_logic;
s_spi_miso_o : OUT std_logic;
s_di_req_o : OUT std_logic; -- preload lookahead data request line
s_di_i : IN std_logic_vector (N-1 downto 0) := (others => 'X'); -- parallel load data in (clocked in on rising edge of clk_i)
s_wren_i : IN std_logic := 'X'; -- user data write enable
s_do_valid_o : OUT std_logic; -- do_o data valid strobe, valid during one clk_i rising edge.
s_do_o : OUT std_logic_vector (N-1 downto 0); -- parallel output (clocked out on falling clk_i)
----- debug -----
s_do_transfer_o : OUT std_logic; -- debug: internal transfer driver
s_wren_o : OUT std_logic;
s_wren_ack_o : OUT std_logic;
s_rx_bit_reg_o : OUT std_logic;
s_state_dbg_o : OUT std_logic_vector (5 downto 0) -- debug: internal state register
-- s_sh_reg_dbg_o : OUT std_logic_vector (N-1 downto 0) -- debug: internal shift register
);
end spi_loopback;
architecture Structural of spi_loopback is
begin
--=============================================================================================
-- Component instantiation for the SPI master port
--=============================================================================================
Inst_spi_master: entity work.spi_master(rtl)
generic map (N => N, CPOL => CPOL, CPHA => CPHA, PREFETCH => PREFETCH, SPI_2X_CLK_DIV => SPI_2X_CLK_DIV)
port map(
sclk_i => m_clk_i, -- system clock is used for serial and parallel ports
pclk_i => m_clk_i,
rst_i => m_rst_i,
spi_ssel_o => m_spi_ssel_o,
spi_sck_o => m_spi_sck_o,
spi_mosi_o => m_spi_mosi_o,
spi_miso_i => m_spi_miso_i,
di_req_o => m_di_req_o,
di_i => m_di_i,
wren_i => m_wren_i,
do_valid_o => m_do_valid_o,
do_o => m_do_o,
----- debug -----
do_transfer_o => m_do_transfer_o,
wren_o => m_wren_o,
wren_ack_o => m_wren_ack_o,
rx_bit_reg_o => m_rx_bit_reg_o,
state_dbg_o => m_state_dbg_o,
core_clk_o => m_core_clk_o,
core_n_clk_o => m_core_n_clk_o,
sh_reg_dbg_o => m_sh_reg_dbg_o
);
--=============================================================================================
-- Component instantiation for the SPI slave port
--=============================================================================================
Inst_spi_slave: entity work.spi_slave(rtl)
generic map (N => N, CPOL => CPOL, CPHA => CPHA, PREFETCH => PREFETCH)
port map(
clk_i => s_clk_i,
spi_ssel_i => s_spi_ssel_i,
spi_sck_i => s_spi_sck_i,
spi_mosi_i => s_spi_mosi_i,
spi_miso_o => s_spi_miso_o,
di_req_o => s_di_req_o,
di_i => s_di_i,
wren_i => s_wren_i,
do_valid_o => s_do_valid_o,
do_o => s_do_o,
----- debug -----
do_transfer_o => s_do_transfer_o,
wren_o => s_wren_o,
wren_ack_o => s_wren_ack_o,
rx_bit_reg_o => s_rx_bit_reg_o,
state_dbg_o => s_state_dbg_o
-- sh_reg_dbg_o => s_sh_reg_dbg_o
);
end Structural;
|
mit
|
FearlessJojo/COPproject
|
project/control.vhd
|
1
|
16123
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:13:04 11/19/2016
-- Design Name:
-- Module Name: control - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity control is
Port ( Inst : in STD_LOGIC_VECTOR (15 downto 0);
A : in STD_LOGIC_VECTOR (15 downto 0);
B : in STD_LOGIC_VECTOR (15 downto 0);
Imm : in STD_LOGIC_VECTOR (15 downto 0);
T : in STD_LOGIC;
NPC : in STD_LOGIC_VECTOR (15 downto 0);
OP : out STD_LOGIC_VECTOR (3 downto 0);
PCctrl : out STD_LOGIC_VECTOR (1 downto 0);
RFctrl : out STD_LOGIC_VECTOR (2 downto 0);
Immctrl : out STD_LOGIC_VECTOR (3 downto 0);
Rs : out STD_LOGIC_VECTOR (3 downto 0);
Rt : out STD_LOGIC_VECTOR (3 downto 0);
Rd : out STD_LOGIC_VECTOR (3 downto 0);
AccMEM : out STD_LOGIC;
memWE : out STD_LOGIC;
regWE : out STD_LOGIC;
DataIN : out STD_LOGIC_VECTOR (15 downto 0);
ALUIN1 : out STD_LOGIC_VECTOR (15 downto 0);
ALUIN2 : out STD_LOGIC_VECTOR (15 downto 0);
newT : out STD_LOGIC;
TE : out STD_LOGIC);
end control;
architecture Behavioral of control is
begin
process(Inst, A, B, Imm, T, NPC)
variable tmp : STD_LOGIC_VECTOR (15 downto 0);
begin
case Inst(15 downto 11) is
when "00001" => --NOP
OP <= "1111";
PCctrl <= "00";
RFctrl <= "000";
Immctrl <= "0000";
Rs <= "1111";
Rt <= "1111";
Rd <= "1111";
ALUIN1 <= A;
ALUIN2 <= B;
AccMEM <= '0';
memWE <= '0';
regWE <= '0';
DataIN <= "0000000000000000";
newT <= '0';
TE <= '0';
when "00010" => --B
OP <= "1111";
PCctrl <= "01";
RFctrl <= "000";
Immctrl <= "0011";
Rs <= "1111";
Rt <= "1111";
Rd <= "1111";
ALUIN1 <= A;
ALUIN2 <= B;
AccMEM <= '0';
memWE <= '0';
regWE <= '0';
DataIN <= "0000000000000000";
newT <= '0';
TE <= '0';
when "00100" => --BEQZ
OP <= "1111";
if (A="0000000000000000") then
PCctrl <= "01";
else
PCctrl <= "00";
end if;
RFctrl <= "001";
Immctrl <= "0001";
Rs <= "0" & Inst(10 downto 8);
Rt <= "1111";
Rd <= "1111";
ALUIN1 <= A;
ALUIN2 <= B;
AccMEM <= '0';
memWE <= '0';
regWE <= '0';
DataIN <= "0000000000000000";
newT <= '0';
TE <= '0';
when "00101" => --BNEZ
OP <= "1111";
if (A="0000000000000000") then
PCctrl <= "00";
else
PCctrl <= "01";
end if;
RFctrl <= "001";
Immctrl <= "0001";
Rs <= "0" & Inst(10 downto 8);
Rt <= "1111";
Rd <= "1111";
ALUIN1 <= A;
ALUIN2 <= B;
AccMEM <= '0';
memWE <= '0';
regWE <= '0';
DataIN <= "0000000000000000";
newT <= '0';
TE <= '0';
when "00110" => --SLL|SRA
case Inst(1 downto 0) is
when "00" => --SLL
OP <= "0110";
PCctrl <= "00";
RFctrl <= "011";
Immctrl <= "0111";
Rs <= "0" & Inst(7 downto 5);
Rt <= "1111";
Rd <= "0" & Inst(10 downto 8);
ALUIN1 <= A;
ALUIN2 <= Imm;
AccMEM <= '0';
memWE <= '0';
regWE <= '1';
DataIN <= "0000000000000000";
newT <= '0';
TE <= '0';
when "11" => --SRA
OP <= "1000";
PCctrl <= "00";
RFctrl <= "011";
Immctrl <= "0111";
Rs <= "0" & Inst(7 downto 5);
Rt <= "1111";
Rd <= "0" & Inst(10 downto 8);
ALUIN1 <= A;
ALUIN2 <= Imm;
AccMEM <= '0';
memWE <= '0';
regWE <= '1';
DataIN <= "0000000000000000";
newT <= '0';
TE <= '0';
when others =>
OP <= "1111";
PCctrl <= "00";
RFctrl <= "000";
Immctrl <= "0000";
Rs <= "1111";
Rt <= "1111";
Rd <= "1111";
ALUIN1 <= A;
ALUIN2 <= B;
AccMEM <= '0';
memWE <= '0';
regWE <= '0';
DataIN <= "0000000000000000";
newT <= '0';
TE <= '0';
end case;
when "01000" => --ADDIU3
OP <= "0000";
PCctrl <= "00";
RFctrl <= "001";
Immctrl <= "0010";
Rs <= "0" & Inst(10 downto 8);
Rt <= "1111";
Rd <= "0" & Inst(7 downto 5);
ALUIN1 <= A;
ALUIN2 <= Imm;
AccMEM <= '0';
memWE <= '0';
regWE <= '1';
DataIN <= "0000000000000000";
newT <= '0';
TE <= '0';
when "01001" => --ADDIU
OP <= "0000";
PCctrl <= "00";
RFctrl <= "001";
Immctrl <= "0001";
Rs <= "0" & Inst(10 downto 8);
Rt <= "1111";
Rd <= "0" & Inst(10 downto 8);
ALUIN1 <= A;
ALUIN2 <= Imm;
AccMEM <= '0';
memWE <= '0';
regWE <= '1';
DataIN <= "0000000000000000";
newT <= '0';
TE <= '0';
when "01010" => --SLTI
OP <= "1111";
tmp := A - Imm;
newT <= tmp(15);
PCctrl <= "00";
RFctrl <= "001";
Immctrl <= "0001";
Rs <= "0" & Inst(10 downto 8);
Rt <= "1111";
Rd <= "1111";
ALUIN1 <= A;
ALUIN2 <= B;
AccMEM <= '0';
memWE <= '0';
regWE <= '0';
DataIN <= "0000000000000000";
TE <= '1';
when "01100" => --ADDSP|BTEQZ|MTSP
case Inst(10 downto 8) is
when "011" => --ADDSP
OP <= "0000";
PCctrl <= "00";
RFctrl <= "100";
Immctrl <= "0001";
Rs <= "1000";
Rt <= "1111";
Rd <= "1000";
ALUIN1 <= A;
ALUIN2 <= Imm;
AccMEM <= '0';
memWE <= '0';
regWE <= '1';
DataIN <= "0000000000000000";
newT <= '0';
TE <= '0';
when "000" => --BTEQZ
OP <= "1111";
if (T='0') then
PCctrl <= "01";
else
PCctrl <= "00";
end if;
RFctrl <= "000";
Immctrl <= "0001";
Rs <= "1111";
Rt <= "1111";
Rd <= "1111";
ALUIN1 <= A;
ALUIN2 <= B;
AccMEM <= '0';
memWE <= '0';
regWE <= '0';
DataIN <= "0000000000000000";
newT <= '0';
TE <= '0';
when "100" => --MTSP
OP <= "1010";
PCctrl <= "00";
RFctrl <= "011";
Immctrl <= "0000";
Rs <= "0" & Inst(7 downto 5);
Rt <= "1111";
Rd <= "1000";
ALUIN1 <= A;
ALUIN2 <= B;
AccMEM <= '0';
memWE <= '0';
regWE <= '1';
DataIN <= "0000000000000000";
newT <= '0';
TE <= '0';
when others =>
OP <= "1111";
PCctrl <= "00";
RFctrl <= "000";
Immctrl <= "0000";
Rs <= "1111";
Rt <= "1111";
Rd <= "1111";
ALUIN1 <= A;
ALUIN2 <= B;
AccMEM <= '0';
memWE <= '0';
regWE <= '0';
DataIN <= "0000000000000000";
newT <= '0';
TE <= '0';
end case;
when "01101" => --LI
OP <= "1011";
PCctrl <= "00";
RFctrl <= "000";
Immctrl <= "0100";
Rs <= "1111";
Rt <= "1111";
Rd <= "0" & Inst(10 downto 8);
ALUIN1 <= A;
ALUIN2 <= Imm;
AccMEM <= '0';
memWE <= '0';
regWE <= '1';
DataIN <= "0000000000000000";
newT <= '0';
TE <= '0';
when "01111" => --MOVE
OP <= "1010";
PCctrl <= "00";
RFctrl <= "011";
Immctrl <= "0000";
Rs <= "0" & Inst(7 downto 5);
Rt <= "1111";
Rd <= "0" & Inst(10 downto 8);
ALUIN1 <= A;
ALUIN2 <= B;
AccMEM <= '0';
memWE <= '0';
regWE <= '1';
DataIN <= "0000000000000000";
newT <= '0';
TE <= '0';
when "10010" => --LW_SP
OP <= "0000";
PCctrl <= "00";
RFctrl <= "100";
Immctrl <= "0001";
Rs <= "1000";
Rt <= "1111";
Rd <= "0" & Inst(10 downto 8);
ALUIN1 <= A;
ALUIN2 <= Imm;
AccMEM <= '1';
memWE <= '0';
regWE <= '1';
DataIN <= "0000000000000000";
newT <= '0';
TE <= '0';
when "10011" => --LW
OP <= "0000";
PCctrl <= "00";
RFctrl <= "001";
Immctrl <= "0101";
Rs <= "0" & Inst(10 downto 8);
Rt <= "1111";
Rd <= "0" & Inst(7 downto 5);
ALUIN1 <= A;
ALUIN2 <= Imm;
AccMEM <= '1';
memWE <= '0';
regWE <= '1';
DataIN <= "0000000000000000";
newT <= '0';
TE <= '0';
when "11010" => --SW_SP
OP <= "0000";
PCctrl <= "00";
RFctrl <= "111";
Immctrl <= "0001";
Rs <= "1000";
Rt <= "0" & Inst(10 downto 8);
Rd <= "1111";
ALUIN1 <= A;
ALUIN2 <= Imm;
AccMEM <= '0';
memWE <= '1';
regWE <= '0';
DataIN <= B;
newT <= '0';
TE <= '0';
when "11011" => --SW
OP <= "0000";
PCctrl <= "00";
RFctrl <= "010";
Immctrl <= "0101";
Rs <= "0" & Inst(10 downto 8);
Rt <= "0" & Inst(7 downto 5);
Rd <= "1111";
ALUIN1 <= A;
ALUIN2 <= Imm;
AccMEM <= '0';
memWE <= '1';
regWE <= '0';
DataIN <= B;
newT <= '0';
TE <= '0';
when "11100" => --ADDU|SUBU
case Inst(1 downto 0) is
when "01" => --ADDU
OP <= "0000";
PCctrl <= "00";
RFctrl <= "010";
Immctrl <= "0000";
Rs <= "0" & Inst(10 downto 8);
Rt <= "0" & Inst(7 downto 5);
Rd <= "0" & Inst(4 downto 2);
ALUIN1 <= A;
ALUIN2 <= B;
AccMEM <= '0';
memWE <= '0';
regWE <= '1';
DataIN <= "0000000000000000";
newT <= '0';
TE <= '0';
when "11" => --SUBU
OP <= "0001";
PCctrl <= "00";
RFctrl <= "010";
Immctrl <= "0000";
Rs <= "0" & Inst(10 downto 8);
Rt <= "0" & Inst(7 downto 5);
Rd <= "0" & Inst(4 downto 2);
ALUIN1 <= A;
ALUIN2 <= B;
AccMEM <= '0';
memWE <= '0';
regWE <= '1';
DataIN <= "0000000000000000";
newT <= '0';
TE <= '0';
when others =>
OP <= "1111";
PCctrl <= "00";
RFctrl <= "000";
Immctrl <= "0000";
Rs <= "1111";
Rt <= "1111";
Rd <= "1111";
ALUIN1 <= A;
ALUIN2 <= B;
AccMEM <= '0';
memWE <= '0';
regWE <= '0';
DataIN <= "0000000000000000";
newT <= '0';
TE <= '0';
end case;
when "11101" => --AND|CMP|JR|JALR|JRRA|MFPC|NOT|OR
case Inst(4 downto 0) is
when "01100" => --AND
OP <= "0010";
PCctrl <= "00";
RFctrl <= "010";
Immctrl <= "0000";
Rs <= "0" & Inst(10 downto 8);
Rt <= "0" & Inst(7 downto 5);
Rd <= "0" & Inst(10 downto 8);
ALUIN1 <= A;
ALUIN2 <= B;
AccMEM <= '0';
memWE <= '0';
regWE <= '1';
DataIN <= "0000000000000000";
newT <= '0';
TE <= '0';
when "01010" => --CMP
OP <= "1111";
if (A=B) then
newT <= '0';
else
newT <= '1';
end if;
PCctrl <= "00";
RFctrl <= "010";
Immctrl <= "0000";
Rs <= "0" & Inst(10 downto 8);
Rt <= "0" & Inst(7 downto 5);
Rd <= "1111";
ALUIN1 <= A;
ALUIN2 <= B;
AccMEM <= '0';
memWE <= '0';
regWE <= '0';
DataIN <= "0000000000000000";
TE <= '1';
when "00000" => --JR|JALR|JRRA|MFPC
case Inst(7 downto 5) is
when "000" => --JR
OP <= "1111";
PCctrl <= "11";
RFctrl <= "001";
Immctrl <= "0000";
Rs <= "0" & Inst(10 downto 8);
Rt <= "1111";
Rd <= "1111";
ALUIN1 <= A;
ALUIN2 <= B;
AccMEM <= '0';
memWE <= '0';
regWE <= '0';
DataIN <= "0000000000000000";
newT <= '0';
TE <= '0';
when "110" => --JALR
OP <= "0000";
PCctrl <= "11";
RFctrl <= "001";
Immctrl <= "1000";
Rs <= "0" & Inst(10 downto 8);
Rt <= "1111";
Rd <= "1010";
ALUIN1 <= NPC;
ALUIN2 <= Imm;
AccMEM <= '0';
memWE <= '0';
regWE <= '1';
DataIN <= "0000000000000000";
newT <= '0';
TE <= '0';
when "001" => --JRRA
OP <= "1111";
PCctrl <= "11";
RFctrl <= "101";
Immctrl <= "0000";
Rs <= "1010";
Rt <= "1111";
Rd <= "1111";
ALUIN1 <= A;
ALUIN2 <= B;
AccMEM <= '0';
memWE <= '0';
regWE <= '0';
DataIN <= "0000000000000000";
newT <= '0';
TE <= '0';
when "010" => --MFPC
OP <= "1010";
PCctrl <= "00";
RFctrl <= "000";
Immctrl <= "1000";
Rs <= "1111";
Rt <= "1111";
Rd <= "0" & Inst(10 downto 8);
ALUIN1 <= NPC;
ALUIN2 <= Imm;
AccMEM <= '0';
memWE <= '0';
regWE <= '1';
DataIN <= "0000000000000000";
newT <= '0';
TE <= '0';
when others =>
OP <= "1111";
PCctrl <= "00";
RFctrl <= "000";
Immctrl <= "0000";
Rs <= "1111";
Rt <= "1111";
Rd <= "1111";
ALUIN1 <= A;
ALUIN2 <= B;
AccMEM <= '0';
memWE <= '0';
regWE <= '0';
DataIN <= "0000000000000000";
newT <= '0';
TE <= '0';
end case;
when "01111" => --NOT
OP <= "0101";
PCctrl <= "00";
RFctrl <= "011";
Immctrl <= "0000";
Rs <= "0" & Inst(7 downto 5);
Rt <= "1111";
Rd <= "0" & Inst(10 downto 8);
ALUIN1 <= A;
ALUIN2 <= B;
AccMEM <= '0';
memWE <= '0';
regWE <= '1';
DataIN <= "0000000000000000";
newT <= '0';
TE <= '0';
when "01101" => --OR
OP <= "0011";
PCctrl <= "00";
RFctrl <= "010";
Immctrl <= "0000";
Rs <= "0" & Inst(10 downto 8);
Rt <= "0" & Inst(7 downto 5);
Rd <= "0" & Inst(10 downto 8);
ALUIN1 <= A;
ALUIN2 <= B;
AccMEM <= '0';
memWE <= '0';
regWE <= '1';
DataIN <= "0000000000000000";
newT <= '0';
TE <= '0';
when others =>
OP <= "1111";
PCctrl <= "00";
RFctrl <= "000";
Immctrl <= "0000";
Rs <= "1111";
Rt <= "1111";
Rd <= "1111";
ALUIN1 <= A;
ALUIN2 <= B;
AccMEM <= '0';
memWE <= '0';
regWE <= '0';
DataIN <= "0000000000000000";
newT <= '0';
TE <= '0';
end case;
when "11110" => --MFIH|MTIH
case Inst(0) is
when '0' => --MFIH
OP <= "1010";
PCctrl <= "00";
RFctrl <= "110";
Immctrl <= "0000";
Rs <= "1001";
Rt <= "1111";
Rd <= "0" & Inst(10 downto 8);
ALUIN1 <= A;
ALUIN2 <= B;
AccMEM <= '0';
memWE <= '0';
regWE <= '1';
DataIN <= "0000000000000000";
newT <= '0';
TE <= '0';
when '1' => --MTIH
OP <= "1010";
PCctrl <= "00";
RFctrl <= "001";
Immctrl <= "0000";
Rs <= "0" & Inst(10 downto 8);
Rt <= "1111";
Rd <= "1001";
ALUIN1 <= A;
ALUIN2 <= B;
AccMEM <= '0';
memWE <= '0';
regWE <= '1';
DataIN <= "0000000000000000";
newT <= '0';
TE <= '0';
when others =>
OP <= "1111";
PCctrl <= "00";
RFctrl <= "000";
Immctrl <= "0000";
Rs <= "1111";
Rt <= "1111";
Rd <= "1111";
ALUIN1 <= A;
ALUIN2 <= B;
AccMEM <= '0';
memWE <= '0';
regWE <= '0';
DataIN <= "0000000000000000";
newT <= '0';
TE <= '0';
end case;
when others =>
OP <= "1111";
PCctrl <= "00";
RFctrl <= "000";
Immctrl <= "0000";
Rs <= "1111";
Rt <= "1111";
Rd <= "1111";
ALUIN1 <= A;
ALUIN2 <= B;
AccMEM <= '0';
memWE <= '0';
regWE <= '0';
DataIN <= "0000000000000000";
newT <= '0';
TE <= '0';
end case;
end process;
end Behavioral;
|
mit
|
FearlessJojo/COPproject
|
project/MEM_WB.vhd
|
1
|
1684
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:06:35 11/20/2016
-- Design Name:
-- Module Name: MEM_WB - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity MEM_WB is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
enable : in STD_LOGIC;
MEM_MEMOUT : in STD_LOGIC_VECTOR (15 downto 0);
MEM_Rd : in STD_LOGIC_VECTOR (3 downto 0);
MEM_regWE : in STD_LOGIC;
WB_MEMOUT : out STD_LOGIC_VECTOR (15 downto 0);
WB_Rd : out STD_LOGIC_VECTOR (3 downto 0);
WB_regWE : out STD_LOGIC);
end MEM_WB;
architecture Behavioral of MEM_WB is
begin
process(clk, rst)
begin
if (rst = '0') then
WB_regWE <= '0';
else
if (clk'event and clk = '1') then
if (enable = '1') then
WB_MEMOUT <= MEM_MEMOUT;
WB_Rd <= MEM_Rd;
WB_regWE <= MEM_regWE;
end if;
end if;
end if;
end process;
end Behavioral;
|
mit
|
jchromik/hpi-vhdl-2016
|
pue1/Hasardsimulation/netgen/synthesis/mux2to1_synthesis.vhd
|
1
|
1493
|
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: P.20131013
-- \ \ Application: netgen
-- / / Filename: .vhd
-- /___/ /\ Timestamp: Wed May 25 16:53:52 2016
-- \ \ / \
-- \___\/\___\
--
-- Command : -intstyle ise -ar Structure -tm mux2to1 -w -dir netgen/synthesis -ofmt vhdl -sim mux2to1.ngc mux2to1_synthesis.vhd
-- Device : xc7a100t-1-csg324
-- Input file : mux2to1.ngc
-- Output file : /home/scandic/Documents/hpi-vhdl-2016/pue1/Hasardsimulation/netgen/synthesis/mux2to1_synthesis.vhd
-- # of Entities : 1
-- Design Name : mux2to1
-- Xilinx : /opt/Xilinx/14.7/ISE_DS/ISE/
--
-- Purpose:
-- This VHDL netlist is a verification model and uses simulation
-- primitives which may not represent the true implementation of the
-- device, however the netlist is functionally correct and should not
-- be modified. This file cannot be synthesized and should only be used
-- with supported simulation tools.
--
-- Reference:
-- Command Line Tools User Guide, Chapter 23
-- Synthesis and Simulation Design Guide, Chapter 6
--
--------------------------------------------------------------------------------
|
mit
|
jchromik/hpi-vhdl-2016
|
pue4/Audio/kb_rf_fetch.vhd
|
2
|
1447
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:56:33 07/06/2016
-- Design Name:
-- Module Name: kb_rf_fetch - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity kb_rf_fetch is port (
kbclk : in STD_LOGIC;
reset : in STD_LOGIC;
clk : in STD_LOGIC;
rf : out STD_LOGIC);
end kb_rf_fetch;
architecture Behavioral of kb_rf_fetch is
signal clk_history: STD_LOGIC_VECTOR(1 downto 0);
begin
clk_history_shift: process(kbclk, clk, reset)
begin
if reset = '1' then
clk_history <= "11";
elsif clk'event and clk = '1' then
clk_history(1) <= clk_history(0);
clk_history(0) <= kbclk;
end if;
end process clk_history_shift;
find_rf: process(clk_history)
begin
if clk_history = "10" then
rf <= '1';
else
rf <= '0';
end if;
end process find_rf;
end Behavioral;
|
mit
|
jchromik/hpi-vhdl-2016
|
pue1/Komp/Zelle.vhd
|
1
|
1176
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:14:34 05/19/2016
-- Design Name:
-- Module Name: Zelle - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Zelle is port (
Cin, Xi: in STD_LOGIC;
Cout, Yi: out STD_LOGIC
);
end Zelle;
architecture Behavioral of Zelle is
signal
buendel: std_logic_vector(1 downto 0);
begin
buendel <= (Cin, Xi);
with buendel select
(Cout, Yi) <= std_logic_vector'("00") when "00",
std_logic_vector'("10") when "11",
std_logic_vector'("11") when others;
end Behavioral;
|
mit
|
mjpatter88/fundamentals
|
01-logic_gates/mux/myMux2.vhdl
|
1
|
885
|
library IEEE;
use IEEE.Std_Logic_1164.all;
entity myMux2 is
port(a: in std_logic; b: in std_logic; sel: in std_logic; s: out std_logic);
end myMux2;
architecture behavioral of myMux2 is
component myAnd2
port(a: in std_logic; b: in std_logic; s: out std_logic);
end component;
component myOr2
port(a: in std_logic; b: in std_logic; s: out std_logic);
end component;
component myNot
port(a: in std_logic; s: out std_logic);
end component;
signal selNot: std_logic;
signal aAndNotSelOut: std_logic;
signal bAndSelOut: std_logic;
begin
myNot_1: myNot port map(a => sel, s => selNot);
myAnd2_1: myAnd2 port map(a => a, b => selNot, s => aAndNotSelOut);
myAnd2_2: myAnd2 port map(a => b, b => sel, s => bAndSelOut);
myOr2_1: myOr2 port map(a => aAndNotSelOut, b => bAndSelOut, s => s);
end behavioral;
|
mit
|
jchromik/hpi-vhdl-2016
|
pue4/Audio/project_main.vhd
|
1
|
2080
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:10:49 07/06/2016
-- Design Name:
-- Module Name: project_main - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity project_main is port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
kbclk : in STD_LOGIC;
kbdata : in STD_LOGIC;
audio : out STD_LOGIC;
segments : out STD_LOGIC_VECTOR(14 downto 0));
end project_main;
architecture Behavioral of project_main is
component keyboard_in is port (
clk : in STD_LOGIC;
kbclk : in STD_LOGIC;
kbdata : in STD_LOGIC;
reset : in STD_LOGIC;
ready : out STD_LOGIC;
scancode : out STD_LOGIC_VECTOR(7 downto 0));
end component;
component audio_out is port (
clk : in STD_LOGIC;
ready : in STD_LOGIC;
reset : in STD_LOGIC;
scancode : in STD_LOGIC_VECTOR(7 downto 0);
audio : out STD_LOGIC);
end component;
component segment_out is port (
clk : in STD_LOGIC;
ready : in STD_LOGIC;
reset : in STD_LOGIC;
scancode : in STD_LOGIC_VECTOR(7 downto 0);
segments : out STD_LOGIC_VECTOR(14 downto 0));
end component;
signal scancode: STD_LOGIC_VECTOR(7 downto 0);
signal ready: STD_LOGIC;
begin
keyboard_in0: keyboard_in port map (clk, kbclk, kbdata, reset, ready, scancode);
audio_out0: audio_out port map (clk, ready, reset, scancode, audio);
segment_out0: segment_out port map (clk, ready, reset, scancode, segments);
end Behavioral;
|
mit
|
bertuccio/ARQ
|
Practica2/memoria_simple.vhd
|
3
|
3298
|
library STD;
use STD.textio.all;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.std_logic_textio.all;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity memoria is
generic(
C_ELF_FILENAME : string := "programa";
C_TARGET_SECTION : string := ".text"; -- No se usa
C_BASE_ADDRESS : integer := 16#400000#; -- No se usa
C_MEM_SIZE : integer := 1024;
C_WAIT_STATES : integer := 0 -- No se usa
);
Port ( Addr : in std_logic_vector(31 downto 0);
DataIn : in std_logic_vector(31 downto 0);
RdStb : in std_logic ;
WrStb : in std_logic ;
Clk : in std_logic ;
Reset : in std_logic ; -- No se usa
AddrStb : in std_logic ; -- No se usa
Rdy : out std_logic ; -- No se usa, siempre a '1'
DataOut : out std_logic_vector(31 downto 0));
end memoria;
architecture Behavioral of memoria is
type matriz is array(0 to C_MEM_SIZE-1) of STD_LOGIC_VECTOR(7 downto 0);
signal memo: matriz;
signal aux : STD_LOGIC_VECTOR (31 downto 0):= (others=>'0');
begin
process (clk)
variable cargar : boolean := true;
variable address : STD_LOGIC_VECTOR(31 downto 0);
variable datum : STD_LOGIC_VECTOR(31 downto 0);
file bin_file : text is in C_ELF_FILENAME;
variable current_line : line;
begin
if cargar then
-- primero iniciamos la memoria con ceros
for i in 0 to C_MEM_SIZE-1 loop
memo(i) <= (others => '0');
end loop;
-- luego cargamos el archivo en la misma
while (not endfile (bin_file)) loop
readline (bin_file, current_line);
hread(current_line, address);
hread(current_line, datum);
assert CONV_INTEGER(address(30 downto 0))<C_MEM_SIZE
report "Direccion fuera de rango en el fichero de la memoria"
severity failure;
memo(CONV_INTEGER(address(30 downto 0))) <= datum(31 downto 24);
memo(CONV_INTEGER(address(30 downto 0)+'1')) <= datum(23 downto 16);
memo(CONV_INTEGER(address(30 downto 0)+"10")) <= datum(15 downto 8);
memo(CONV_INTEGER(address(30 downto 0)+"11")) <= datum(7 downto 0);
end loop;
-- por ultimo cerramos el archivo y actualizamos el flag de memoria cargada
file_close (bin_file);
cargar := false;
elsif (Clk'event and Clk = '0') then
if (WrStb = '1') then
memo(CONV_INTEGER(Addr(30 downto 0))) <= DataIn(31 downto 24);
memo(CONV_INTEGER(Addr(30 downto 0)+'1')) <= DataIn(23 downto 16);
memo(CONV_INTEGER(Addr(30 downto 0)+"10")) <= DataIn(15 downto 8);
memo(CONV_INTEGER(Addr(30 downto 0)+"11")) <= DataIn(7 downto 0);
elsif (RdStb = '1')then
aux(31 downto 24) <= memo(conv_integer(Addr(30 downto 0)));
aux(23 downto 16) <= memo(conv_integer(Addr(30 downto 0)+'1'));
aux(15 downto 8) <= memo(conv_integer(Addr(30 downto 0)+"10"));
aux(7 downto 0) <= memo(conv_integer(Addr(30 downto 0)+"11"));
end if;
end if;
end process;
DataOut <= aux;
Rdy <= '1';
end Behavioral;
|
mit
|
UVVM/uvvm_vvc_framework
|
uvvm_util/src/string_methods_pkg.vhd
|
1
|
50359
|
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
use ieee.math_real.all;
use work.types_pkg.all;
use work.adaptations_pkg.all;
package string_methods_pkg is
-- Need a low level "alert" in the form of a simple assertion (as string handling may also fail)
procedure bitvis_assert(
val : boolean;
severeness : severity_level;
msg : string;
scope : string
);
function justify(
val : string;
justified : side;
width : natural;
format_spaces : t_format_spaces;
truncate : t_truncate_string
) return string;
-- DEPRECATED.
-- Function will be removed in future versions of UVVM-Util
function justify(
val : string;
width : natural := 0;
justified : side := RIGHT;
format: t_format_string := AS_IS -- No defaults on 4 first param - to avoid ambiguity with std.textio
) return string;
function justify(
val : string;
justified : t_justify_center;
width : natural;
format_spaces : t_format_spaces;
truncate : t_truncate_string
) return string;
function pos_of_leftmost(
target : character;
vector : string;
result_if_not_found : natural := 1
) return natural;
function pos_of_rightmost(
target : character;
vector : string;
result_if_not_found : natural := 1
) return natural;
function pos_of_leftmost_non_zero(
vector : string;
result_if_not_found : natural := 1
) return natural;
function pos_of_rightmost_non_whitespace(
vector : string;
result_if_not_found : natural := 1
) return natural;
function valid_length( -- of string excluding trailing NULs
vector : string
) return natural;
function get_string_between_delimiters(
val : string;
delim_left : character;
delim_right: character;
start_from : SIDE; -- search from left or right (Only RIGHT implemented so far)
occurrence : positive := 1 -- stop on N'th occurrence of delimeter pair. Default first occurrence
) return string;
function get_procedure_name_from_instance_name(
val : string
) return string;
function get_process_name_from_instance_name(
val : string
) return string;
function get_entity_name_from_instance_name(
val : string
) return string;
function return_string_if_true(
val : string;
return_val : boolean
) return string;
function return_string1_if_true_otherwise_string2(
val1 : string;
val2 : string;
return_val : boolean
) return string;
function to_upper(
val : string
) return string;
function fill_string(
val : character;
width : natural
) return string;
function pad_string(
val : string;
char : character;
width : natural;
side : side := LEFT
) return string;
function replace_backslash_n_with_lf(
source : string
) return string;
function remove_initial_chars(
source : string;
num : natural
) return string;
function wrap_lines(
constant text_string : string;
constant alignment_pos1 : natural; -- Line position of first aligned character in line 1
constant alignment_pos2 : natural; -- Line position of first aligned character in line 2, etc...
constant line_width : natural
) return string;
procedure wrap_lines(
variable text_lines : inout line;
constant alignment_pos1 : natural; -- Line position prior to first aligned character (incl. Prefix)
constant alignment_pos2 : natural;
constant line_width : natural
);
procedure prefix_lines(
variable text_lines : inout line;
constant prefix : string := C_LOG_PREFIX
);
function replace(
val : string;
target_char : character;
exchange_char : character
) return string;
procedure replace(
variable text_line : inout line;
target_char : character;
exchange_char : character
);
--========================================================
-- Handle missing overloads from 'standard_additions'
--========================================================
function to_string(
val : boolean;
width : natural;
justified : side;
format_spaces : t_format_spaces;
truncate : t_truncate_string := DISALLOW_TRUNCATE
) return string;
function to_string(
val : integer;
width : natural;
justified : side;
format_spaces : t_format_spaces;
truncate : t_truncate_string := DISALLOW_TRUNCATE
) return string;
-- This function has been deprecated and will be removed in the next major release
-- DEPRECATED
function to_string(
val : boolean;
width : natural;
justified : side := right;
format: t_format_string := AS_IS
) return string;
-- This function has been deprecated and will be removed in the next major release
-- DEPRECATED
function to_string(
val : integer;
width : natural;
justified : side := right;
format : t_format_string := AS_IS
) return string;
function to_string(
val : std_logic_vector;
radix : t_radix;
format : t_format_zeros := KEEP_LEADING_0; -- | SKIP_LEADING_0
prefix : t_radix_prefix := EXCL_RADIX -- Insert radix prefix in string?
) return string;
function to_string(
val : unsigned;
radix : t_radix;
format : t_format_zeros := KEEP_LEADING_0; -- | SKIP_LEADING_0
prefix : t_radix_prefix := EXCL_RADIX -- Insert radix prefix in string?
) return string;
function to_string(
val : signed;
radix : t_radix;
format : t_format_zeros := KEEP_LEADING_0; -- | SKIP_LEADING_0
prefix : t_radix_prefix := EXCL_RADIX -- Insert radix prefix in string?
) return string;
function to_string(
val : t_byte_array;
radix : t_radix := HEX_BIN_IF_INVALID;
format : t_format_zeros := KEEP_LEADING_0; -- | SKIP_LEADING_0
prefix : t_radix_prefix := EXCL_RADIX -- Insert radix prefix in string?
) return string;
function to_string(
val : t_slv_array;
radix : t_radix := HEX_BIN_IF_INVALID;
format : t_format_zeros := KEEP_LEADING_0; -- | SKIP_LEADING_0
prefix : t_radix_prefix := EXCL_RADIX -- Insert radix prefix in string?
) return string;
function to_string(
val : t_signed_array;
radix : t_radix := HEX_BIN_IF_INVALID;
format : t_format_zeros := KEEP_LEADING_0; -- | SKIP_LEADING_0
prefix : t_radix_prefix := EXCL_RADIX -- Insert radix prefix in string?
) return string;
function to_string(
val : t_unsigned_array;
radix : t_radix := HEX_BIN_IF_INVALID;
format : t_format_zeros := KEEP_LEADING_0; -- | SKIP_LEADING_0
prefix : t_radix_prefix := EXCL_RADIX -- Insert radix prefix in string?
) return string;
--========================================================
-- Handle types defined at lower levels
--========================================================
function to_string(
val : t_alert_level;
width : natural;
justified : side := right
) return string;
function to_string(
val : t_msg_id;
width : natural;
justified : side := right
) return string;
function to_string(
val : t_attention;
width : natural;
justified : side := right
) return string;
procedure to_string(
val : t_alert_attention_counters;
order : t_order := FINAL
);
function ascii_to_char(
ascii_pos : integer range 0 to 255;
ascii_allow : t_ascii_allow := ALLOW_ALL
) return character;
function char_to_ascii(
char : character
) return integer;
-- return string with only valid ascii characters
function to_string(
val : string
) return string;
function add_msg_delimiter(
msg : string
) return string;
end package string_methods_pkg;
package body string_methods_pkg is
-- Need a low level "alert" in the form of a simple assertion (as string handling may also fail)
procedure bitvis_assert(
val : boolean;
severeness : severity_level;
msg : string;
scope : string
) is
begin
assert val
report LF & C_LOG_PREFIX & " *** " & to_string(severeness) & "*** caused by Bitvis Util > string handling > "
& scope & LF & C_LOG_PREFIX & " " & add_msg_delimiter(msg) & LF
severity severeness;
end;
function to_upper(
val : string
) return string is
variable v_result : string (val'range) := val;
variable char : character;
begin
for i in val'range loop
-- NOTE: Illegal characters are allowed and will pass through (check Mentor's std_developers_kit)
if ( v_result(i) >= 'a' and v_result(i) <= 'z') then
v_result(i) := character'val( character'pos(v_result(i)) - character'pos('a') + character'pos('A') );
end if;
end loop;
return v_result;
end to_upper;
function fill_string(
val : character;
width : natural
) return string is
variable v_result : string (1 to maximum(1, width));
begin
if (width = 0) then
return "";
else
for i in 1 to width loop
v_result(i) := val;
end loop;
end if;
return v_result;
end fill_string;
function pad_string(
val : string;
char : character;
width : natural;
side : side := LEFT
) return string is
variable v_result : string (1 to maximum(1, width));
begin
if (width = 0) then
return "";
elsif (width <= val'length) then
return val(1 to width);
else
v_result := (others => char);
if side = LEFT then
v_result(1 to val'length) := val;
else
v_result(v_result'length-val'length+1 to v_result'length) := val;
end if;
end if;
return v_result;
end pad_string;
-- This procedure has been deprecated, and will be removed in the near future.
function justify(
val : string;
width : natural := 0;
justified : side := RIGHT;
format : t_format_string := AS_IS -- No defaults on 4 first param - to avoid ambiguity with std.textio
) return string is
constant val_length : natural := val'length;
variable result : string(1 to width) := (others => ' ');
begin
-- return val if width is too small
if val_length >= width then
if (format = TRUNCATE) then
return val(1 to width);
else
return val;
end if;
end if;
if justified = left then
result(1 to val_length) := val;
elsif justified = right then
result(width - val_length + 1 to width) := val;
end if;
return result;
end function;
function justify(
val : string;
justified : side;
width : natural;
format_spaces : t_format_spaces;
truncate : t_truncate_string
) return string is
variable v_val_length : natural := val'length;
variable v_formatted_val : string (1 to val'length);
variable v_num_leading_space : natural := 0;
variable v_result : string(1 to width) := (others => ' ');
begin
-- Remove leading space if format_spaces is SKIP_LEADING_SPACE
if format_spaces = SKIP_LEADING_SPACE then
-- Find how many leading spaces there are
while( (val(v_num_leading_space+1) = ' ') and (v_num_leading_space < v_val_length)) loop
v_num_leading_space := v_num_leading_space + 1;
end loop;
-- Remove leading space if any
v_formatted_val := remove_initial_chars(val,v_num_leading_space);
v_val_length := v_formatted_val'length;
else
v_formatted_val := val;
end if;
-- Truncate and return if the string is wider that allowed
if v_val_length >= width then
if (truncate = ALLOW_TRUNCATE) then
return v_formatted_val(1 to width);
else
return v_formatted_val;
end if;
end if;
-- Justify if string is within the width specifications
if justified = left then
v_result(1 to v_val_length) := v_formatted_val;
elsif justified = right then
v_result(width - v_val_length + 1 to width) := v_formatted_val;
end if;
return v_result;
end function;
function justify(
val : string;
justified : t_justify_center;
width : natural;
format_spaces : t_format_spaces;
truncate : t_truncate_string
) return string is
variable v_val_length : natural := val'length;
variable v_start_pos : natural;
variable v_formatted_val : string (1 to val'length);
variable v_num_leading_space : natural := 0;
variable v_result : string(1 to width) := (others => ' ');
begin
-- Remove leading space if format_spaces is SKIP_LEADING_SPACE
if format_spaces = SKIP_LEADING_SPACE then
-- Find how many leading spaces there are
while( (val(v_num_leading_space+1) = ' ') and (v_num_leading_space < v_val_length)) loop
v_num_leading_space := v_num_leading_space + 1;
end loop;
-- Remove leading space if any
v_formatted_val := remove_initial_chars(val,v_num_leading_space);
v_val_length := v_formatted_val'length;
else
v_formatted_val := val;
end if;
-- Truncate and return if the string is wider that allowed
if v_val_length >= width then
if (truncate = ALLOW_TRUNCATE) then
return v_formatted_val(1 to width);
else
return v_formatted_val;
end if;
end if;
-- Justify if string is within the width specifications
v_start_pos := natural(ceil((real(width)-real(v_val_length))/real(2))) + 1;
v_result(v_start_pos to v_start_pos + v_val_length-1) := v_formatted_val;
return v_result;
end function;
function pos_of_leftmost(
target : character;
vector : string;
result_if_not_found : natural := 1
) return natural is
alias a_vector : string(1 to vector'length) is vector;
begin
bitvis_assert(vector'length > 0, FAILURE, "String input is empty", "pos_of_leftmost()");
bitvis_assert(vector'ascending, FAILURE, "Only implemented for string(N to M)", "pos_of_leftmost()");
for i in a_vector'left to a_vector'right loop
if (a_vector(i) = target) then
return i;
end if;
end loop;
return result_if_not_found;
end;
function pos_of_rightmost(
target : character;
vector : string;
result_if_not_found : natural := 1
) return natural is
alias a_vector : string(1 to vector'length) is vector;
begin
bitvis_assert(vector'length > 0, FAILURE, "String input is empty", "pos_of_rightmost()");
bitvis_assert(vector'ascending, FAILURE, "Only implemented for string(N to M)", "pos_of_rightmost()");
for i in a_vector'right downto a_vector'left loop
if (a_vector(i) = target) then
return i;
end if;
end loop;
return result_if_not_found;
end;
function pos_of_leftmost_non_zero(
vector : string;
result_if_not_found : natural := 1
) return natural is
alias a_vector : string(1 to vector'length) is vector;
begin
bitvis_assert(vector'length > 0, FAILURE, "String input is empty", "pos_of_leftmost_non_zero()");
for i in a_vector'left to a_vector'right loop
if (a_vector(i) /= '0' and a_vector(i) /= ' ') then
return i;
end if;
end loop;
return result_if_not_found;
end;
function pos_of_rightmost_non_whitespace(
vector : string;
result_if_not_found : natural := 1
) return natural is
alias a_vector : string(1 to vector'length) is vector;
begin
bitvis_assert(vector'length > 0, FAILURE, "String input is empty", "pos_of_rightmost_non_whitespace()");
for i in a_vector'right downto a_vector'left loop
if a_vector(i) /= ' ' then
return i;
end if;
end loop;
return result_if_not_found;
end;
function valid_length( -- of string excluding trailing NULs
vector : string
) return natural is
begin
return pos_of_leftmost(NUL, vector, vector'length) - 1;
end;
function string_contains_char(
val : string;
char : character
) return boolean is
alias a_val : string(1 to val'length) is val;
begin
if (val'length = 0) then
return false;
else
for i in val'left to val'right loop
if (val(i) = char) then
return true;
end if;
end loop;
-- falls through only if not found
return false;
end if;
end;
-- get_*_name
-- Note: for sub-programs the following is given: library:package:procedure:object
-- Note: for design hierachy the following is given: complete hierarchy from sim-object down to process object
-- e.g. 'sbi_tb:i_test_harness:i2_sbi_vvc:p_constructor:v_msg'
-- Attribute instance_name also gives [procedure signature] or @entity-name(architecture name)
function get_string_between_delimiters(
val : string;
delim_left : character;
delim_right: character;
start_from : SIDE; -- search from left or right (Only RIGHT implemented so far)
occurrence : positive := 1 -- stop on N'th occurrence of delimeter pair. Default first occurrence
) return string is
variable v_left : natural := 0;
variable v_right : natural := 0;
variable v_start : natural := val'length;
variable v_occurrence : natural := 0;
alias a_val : string(1 to val'length) is val;
begin
bitvis_assert(a_val'length > 2, FAILURE, "String input is not wide enough (<3)", "get_string_between_delimiters()");
bitvis_assert(start_from = RIGHT, FAILURE, "Only search from RIGHT is implemented so far", "get_string_between_delimiters()");
loop
-- RIGHT
v_left := 0; -- default
v_right := pos_of_rightmost(delim_right, a_val(1 to v_start), 0);
if v_right > 0 then -- i.e. found
L1: for i in v_right-1 downto 1 loop -- searching backwards for delimeter
if (a_val(i) = delim_left) then
v_left := i;
v_start := i; -- Previous end delimeter could also be a start delimeter for next section
v_occurrence := v_occurrence + 1;
exit L1;
end if;
end loop; -- searching backwards
end if;
if v_right = 0 or v_left = 0 then
return ""; -- No delimeter pair found, and none can be found in the rest (with chars in between)
end if;
if v_occurrence = occurrence then
-- Match
if (v_right - v_left) < 2 then
return ""; -- no chars in between delimeters
else
return a_val(v_left+1 to v_right-1);
end if;
end if;
if v_start < 3 then
return ""; -- No delimeter pair found, and none can be found in the rest (with chars in between)
end if;
end loop; -- Will continue until match or not found
end;
-- ':sbi_tb(func):i_test_harness@test_harness(struct):i2_sbi_vvc@sbi_vvc(struct):p_constructor:instance'
-- ':sbi_tb:i_test_harness:i1_sbi_vvc:p_constructor:instance'
-- - Process name: Search for 2nd last param in path name
-- - Entity name: Search for 3nd last param in path name
--':bitvis_vip_sbi:sbi_bfm_pkg:sbi_write[unsigned,std_logic_vector,string,std_logic,std_logic,unsigned,
-- std_logic,std_logic,std_logic,std_logic_vector,time,string,t_msg_id_panel,t_sbi_config]:msg'
-- - Procedure name: Search for 2nd last param in path name and remove all inside []
function get_procedure_name_from_instance_name(
val : string
) return string is
variable v_line : line;
variable v_msg_line : line;
begin
bitvis_assert(val'length > 2, FAILURE, "String input is not wide enough (<3)", "get_procedure_name_from_instance_name()");
write(v_line, get_string_between_delimiters(val, ':', '[', RIGHT));
if (string_contains_char(val, '@')) then
write(v_msg_line, string'("Must be called with <sub-program object>'instance_name"));
else
write(v_msg_line, string'(" "));
end if;
bitvis_assert(v_line'length > 0, ERROR, "No procedure name found. " & v_msg_line.all, "get_procedure_name_from_instance_name()");
return v_line.all;
end;
function get_process_name_from_instance_name(
val : string
) return string is
variable v_line : line;
variable v_msg_line : line;
begin
bitvis_assert(val'length > 2, FAILURE, "String input is not wide enough (<3)", "get_process_name_from_instance_name()");
write(v_line, get_string_between_delimiters(val, ':', ':', RIGHT));
if (string_contains_char(val, '[')) then
write(v_msg_line, string'("Must be called with <process-local object>'instance_name"));
else
write(v_msg_line, string'(" "));
end if;
bitvis_assert(v_line'length > 0, ERROR, "No process name found", "get_process_name_from_instance_name()");
return v_line.all;
end;
function get_entity_name_from_instance_name(
val : string
) return string is
variable v_line : line;
variable v_msg_line : line;
begin
bitvis_assert(val'length > 2, FAILURE, "String input is not wide enough (<3)", "get_entity_name_from_instance_name()");
if string_contains_char(val, '@') then -- for path with instantiations
write(v_line, get_string_between_delimiters(val, '@', '(', RIGHT));
else -- for path with only a single entity
write(v_line, get_string_between_delimiters(val, ':', '(', RIGHT));
end if;
if (string_contains_char(val, '[')) then
write(v_msg_line, string'("Must be called with <Entity/arch-local object>'instance_name"));
else
write(v_msg_line, string'(" "));
end if;
bitvis_assert(v_line'length > 0, ERROR, "No entity name found", "get_entity_name_from_instance_name()");
return v_line.all;
end;
function adjust_leading_0(
val : string;
format : t_format_zeros := SKIP_LEADING_0
) return string is
alias a_val : string(1 to val'length) is val;
constant leftmost_non_zero : natural := pos_of_leftmost_non_zero(a_val, 1);
begin
if val'length <= 1 then
return val;
end if;
if format = SKIP_LEADING_0 then
return a_val(leftmost_non_zero to val'length);
else
return a_val;
end if;
end function;
function return_string_if_true(
val : string;
return_val : boolean
) return string is
begin
if return_val then
return val;
else
return "";
end if;
end function;
function return_string1_if_true_otherwise_string2(
val1 : string;
val2 : string;
return_val : boolean
) return string is
begin
if return_val then
return val1;
else
return val2;
end if;
end function;
function replace_backslash_n_with_lf(
source : string
) return string is
variable v_source_idx : natural := 0;
variable v_dest_idx : natural := 0;
variable v_dest : string(1 to source'length);
begin
if source'length = 0 then
return "";
else
if C_USE_BACKSLASH_N_AS_LF then
loop
v_source_idx := v_source_idx + 1;
v_dest_idx := v_dest_idx + 1;
if (v_source_idx < source'length) then
if (source(v_source_idx to v_source_idx +1) /= "\n") then
v_dest(v_dest_idx) := source(v_source_idx);
else
v_dest(v_dest_idx) := LF;
v_source_idx := v_source_idx + 1; -- Additional increment as two chars (\n) are consumed
if (v_source_idx = source'length) then
exit;
end if;
end if;
else
-- Final character in string
v_dest(v_dest_idx) := source(v_source_idx);
exit;
end if;
end loop;
else
v_dest := source;
v_dest_idx := source'length;
end if;
return v_dest(1 to v_dest_idx);
end if;
end;
function remove_initial_chars(
source : string;
num : natural
) return string is
begin
if source'length <= num then
return "";
else
return source(1 + num to source'right);
end if;
end;
function wrap_lines(
constant text_string : string;
constant alignment_pos1 : natural; -- Line position of first aligned character in line 1
constant alignment_pos2 : natural; -- Line position of first aligned character in line 2
constant line_width : natural
) return string is
variable v_text_lines : line;
variable v_result : string(1 to 2 * text_string'length + alignment_pos1 + 100); -- Margin for aligns and LF insertions
variable v_result_width : natural;
begin
write(v_text_lines, text_string);
wrap_lines(v_text_lines, alignment_pos1, alignment_pos2, line_width);
v_result_width := v_text_lines'length;
bitvis_assert(v_result_width <= v_result'length, FAILURE,
" String is too long after wrapping. Increase v_result string size.", "wrap_lines()");
v_result(1 to v_result_width) := v_text_lines.all;
deallocate(v_text_lines);
return v_result(1 to v_result_width);
end;
procedure wrap_lines(
variable text_lines : inout line;
constant alignment_pos1 : natural; -- Line position of first aligned character in line 1
constant alignment_pos2 : natural; -- Line position of first aligned character in line 2
constant line_width : natural
) is
variable v_string : string(1 to text_lines'length) := text_lines.all;
variable v_string_width : natural := text_lines'length;
variable v_line_no : natural := 0;
variable v_last_string_wrap : natural := 0;
variable v_min_string_wrap : natural;
variable v_max_string_wrap : natural;
begin
deallocate(text_lines); -- empty the line prior to filling it up again
l_line: loop -- For every tekstline found in text_lines
v_line_no := v_line_no + 1;
-- Find position to wrap in v_string
if (v_line_no = 1) then
v_min_string_wrap := 1; -- Minimum 1 character of input line
v_max_string_wrap := minimum(line_width - alignment_pos1 + 1, v_string_width);
write(text_lines, fill_string(' ', alignment_pos1 - 1));
else
v_min_string_wrap := v_last_string_wrap + 1; -- Minimum 1 character further into the inpit line
v_max_string_wrap := minimum(v_last_string_wrap + (line_width - alignment_pos2 + 1), v_string_width);
write(text_lines, fill_string(' ', alignment_pos2 - 1));
end if;
-- 1. First handle any potential explicit line feed in the current maximum text line
-- Search forward for potential LF
for i in (v_last_string_wrap + 1) to minimum(v_max_string_wrap + 1, v_string_width) loop
if (character(v_string(i)) = LF) then
write(text_lines, v_string((v_last_string_wrap + 1) to i)); -- LF now terminates this part
v_last_string_wrap := i;
next l_line; -- next line
end if;
end loop;
-- 2. Then check if remaining text fits into a single text line
if (v_string_width <= v_max_string_wrap) then
-- No (more) wrapping required
write(text_lines, v_string((v_last_string_wrap + 1) to v_string_width));
exit; -- No more lines
end if;
-- 3. Search for blanks from char after max msg width and downwards (in the left direction)
for i in v_max_string_wrap + 1 downto (v_last_string_wrap + 1) loop
if (character(v_string(i)) = ' ') then
write(text_lines, v_string((v_last_string_wrap + 1) to i-1)); -- Exchange last blank with LF
v_last_string_wrap := i;
if (i = v_string_width ) then
exit l_line;
end if;
-- Skip any potential extra blanks in the string
for j in (i+1) to v_string_width loop
if (v_string(j) = ' ') then
v_last_string_wrap := j;
if (j = v_string_width ) then
exit l_line;
end if;
else
write(text_lines, LF); -- Exchange last blanks with LF, provided not at the end of the string
exit;
end if;
end loop;
next l_line; -- next line
end if;
end loop;
-- 4. At this point no LF or blank is found in the searched section of the string.
-- Hence just break the string - and continue.
write(text_lines, v_string((v_last_string_wrap + 1) to v_max_string_wrap) & LF); -- Added LF termination
v_last_string_wrap := v_max_string_wrap;
end loop;
end;
procedure prefix_lines(
variable text_lines : inout line;
constant prefix : string := C_LOG_PREFIX
) is
variable v_string : string(1 to text_lines'length) := text_lines.all;
variable v_string_width : natural := text_lines'length;
constant prefix_width : natural := prefix'length;
variable v_last_string_wrap : natural := 0;
variable i : natural := 0; -- for indexing v_string
begin
deallocate(text_lines); -- empty the line prior to filling it up again
l_line : loop
-- 1. Write prefix
write(text_lines, prefix);
-- 2. Write rest of text line (or rest of input line if no LF)
l_char: loop
i := i + 1;
if (i < v_string_width) then
if (character(v_string(i)) = LF) then
write(text_lines, v_string((v_last_string_wrap + 1) to i));
v_last_string_wrap := i;
exit l_char;
end if;
else
-- 3. Reached end of string. Hence just write the rest.
write(text_lines, v_string((v_last_string_wrap + 1) to v_string_width));
-- But ensure new line with prefix if ending with LF
if (v_string(i) = LF) then
write(text_lines, prefix);
end if;
exit l_char;
end if;
end loop;
if (i = v_string_width) then
exit;
end if;
end loop;
end;
function replace(
val : string;
target_char : character;
exchange_char : character
) return string is
variable result : string(1 to val'length) := val;
begin
for i in val'range loop
if val(i) = target_char then
result(i) := exchange_char;
end if;
end loop;
return result;
end;
procedure replace(
variable text_line : inout line;
target_char : character;
exchange_char : character
) is
variable v_string : string(1 to text_line'length) := text_line.all;
variable v_string_width : natural := text_line'length;
variable i : natural := 0; -- for indexing v_string
begin
if v_string_width > 0 then
deallocate(text_line); -- empty the line prior to filling it up again
-- 1. Loop through string and replace characters
l_char: loop
i := i + 1;
if (i < v_string_width) then
if (character(v_string(i)) = target_char) then
v_string(i) := exchange_char;
end if;
else
-- 2. Reached end of string. Hence just write the new string.
write(text_line, v_string);
exit l_char;
end if;
end loop;
end if;
end;
--========================================================
-- Handle missing overloads from 'standard_additions' + advanced overloads
--========================================================
function to_string(
val : boolean;
width : natural;
justified : side;
format_spaces : t_format_spaces;
truncate : t_truncate_string := DISALLOW_TRUNCATE
) return string is
begin
return justify(to_string(val), justified, width, format_spaces, truncate);
end;
function to_string(
val : integer;
width : natural;
justified : side;
format_spaces : t_format_spaces;
truncate : t_truncate_string := DISALLOW_TRUNCATE
) return string is
begin
return justify(to_string(val), justified, width, format_spaces, truncate);
end;
-- This function has been deprecated and will be removed in the next major release
function to_string(
val : boolean;
width : natural;
justified : side := right;
format : t_format_string := AS_IS
) return string is
begin
return justify(to_string(val), width, justified, format);
end;
-- This function has been deprecated and will be removed in the next major release
function to_string(
val : integer;
width : natural;
justified : side := right;
format : t_format_string := AS_IS
) return string is
begin
return justify(to_string(val), width, justified, format);
end;
function to_string(
val : std_logic_vector;
radix : t_radix;
format : t_format_zeros := KEEP_LEADING_0; -- | SKIP_LEADING_0
prefix : t_radix_prefix := EXCL_RADIX -- Insert radix prefix in string?
) return string is
variable v_line : line;
alias a_val : std_logic_vector(val'length - 1 downto 0) is val;
variable v_result : string(1 to 10 + 2 * val'length); --
variable v_width : natural;
variable v_use_end_char : boolean := false;
begin
if val'length = 0 then
-- Value length is zero,
-- return empty string.
return "";
end if;
if radix = BIN then
if prefix = INCL_RADIX then
write(v_line, string'("b"""));
v_use_end_char := true;
end if;
write(v_line, adjust_leading_0(to_string(val), format));
elsif radix = HEX then
if prefix = INCL_RADIX then
write(v_line, string'("x"""));
v_use_end_char := true;
end if;
write(v_line, adjust_leading_0(to_hstring(val), format));
elsif radix = DEC then
if prefix = INCL_RADIX then
write(v_line, string'("d"""));
v_use_end_char := true;
end if;
-- Assuming that val is not signed
if (val'length > 31) then
write(v_line, to_hstring(val) & " (too wide to be converted to integer)" );
else
write(v_line, adjust_leading_0(to_string(to_integer(unsigned(val))), format));
end if;
elsif radix = HEX_BIN_IF_INVALID then
if prefix = INCL_RADIX then
write(v_line, string'("x"""));
end if;
if is_x(val) then
write(v_line, adjust_leading_0(to_hstring(val), format));
if prefix = INCL_RADIX then
write(v_line, string'("""")); -- terminate hex value
end if;
write(v_line, string'(" (b"""));
write(v_line, adjust_leading_0(to_string(val), format));
write(v_line, string'(""""));
write(v_line, string'(")"));
else
write(v_line, adjust_leading_0(to_hstring(val), format));
if prefix = INCL_RADIX then
write(v_line, string'(""""));
end if;
end if;
end if;
if v_use_end_char then
write(v_line, string'(""""));
end if;
v_width := v_line'length;
v_result(1 to v_width) := v_line.all;
deallocate(v_line);
return v_result(1 to v_width);
end;
function to_string(
val : unsigned;
radix : t_radix;
format : t_format_zeros := KEEP_LEADING_0; -- | SKIP_LEADING_0
prefix : t_radix_prefix := EXCL_RADIX -- Insert radix prefix in string?
) return string is
begin
return to_string(std_logic_vector(val), radix, format, prefix);
end;
function to_string(
val : signed;
radix : t_radix;
format : t_format_zeros := KEEP_LEADING_0; -- | SKIP_LEADING_0
prefix : t_radix_prefix := EXCL_RADIX -- Insert radix prefix in string?
) return string is
variable v_line : line;
variable v_result : string(1 to 10 + 2 * val'length); --
variable v_width : natural;
variable v_use_end_char : boolean := false;
begin
-- Support negative numbers by _not_ using the slv overload when converting to decimal
if radix = DEC then
if val'length = 0 then
-- Value length is zero,
-- return empty string.
return "";
end if;
if prefix = INCL_RADIX then
write(v_line, string'("d"""));
v_use_end_char := true;
end if;
if (val'length > 32) then
write(v_line, to_string(std_logic_vector(val),radix, format, prefix) & " (too wide to be converted to integer)" );
else
write(v_line, adjust_leading_0(to_string(to_integer(signed(val))), format));
end if;
if v_use_end_char then
write(v_line, string'(""""));
end if;
v_width := v_line'length;
v_result(1 to v_width) := v_line.all;
deallocate(v_line);
return v_result(1 to v_width);
else -- No decimal convertion: May be treated as slv, so use the slv overload
return to_string(std_logic_vector(val), radix, format, prefix);
end if;
end;
function to_string(
val : t_byte_array;
radix : t_radix := HEX_BIN_IF_INVALID;
format : t_format_zeros := KEEP_LEADING_0; -- | SKIP_LEADING_0
prefix : t_radix_prefix := EXCL_RADIX -- Insert radix prefix in string?
) return string is
variable v_line : line;
variable v_result : string(1 to 2 + -- parentheses
2*(val'length - 1) + -- commas
26 * val'length); -- 26 is max length of returned value from slv to_string()
variable v_width : natural;
begin
if val'length = 0 then
-- Value length is zero,
-- return empty string.
return "";
elsif val'length = 1 then
-- Value length is 1
-- Return the single value it contains
return to_string(val(val'low), radix, format, prefix);
else
-- Value length more than 1
-- Comma-separate all array members and return
write(v_line, string'("("));
for i in val'range loop
write(v_line, to_string(val(i), radix, format, prefix));
if i < val'right and val'ascending then
write(v_line, string'(", "));
elsif i > val'right and not val'ascending then
write(v_line, string'(", "));
end if;
end loop;
write(v_line, string'(")"));
v_width := v_line'length;
v_result(1 to v_width) := v_line.all;
deallocate(v_line);
return v_result(1 to v_width);
end if;
end;
function to_string(
val : t_slv_array;
radix : t_radix := HEX_BIN_IF_INVALID;
format : t_format_zeros := KEEP_LEADING_0; -- | SKIP_LEADING_0
prefix : t_radix_prefix := EXCL_RADIX -- Insert radix prefix in string?
) return string is
variable v_line : line;
variable v_result : string(1 to 2 + -- parentheses
2*(val'length - 1) + -- commas
26*val'length); -- 26 is max length of returned value from slv to_string()
variable v_width : natural;
begin
if val'length = 0 then
return "";
else
-- Comma-separate all array members and return
write(v_line, string'("("));
for idx in val'range loop
write(v_line, to_string(val(idx), radix, format, prefix));
if (idx < val'right) and (val'ascending) then
write(v_line, string'(", "));
elsif (idx > val'right) and not(val'ascending) then
write(v_line, string'(", "));
end if;
end loop;
write(v_line, string'(")"));
v_width := v_line'length;
v_result(1 to v_width) := v_line.all;
deallocate(v_line);
return v_result(1 to v_width);
end if;
end function;
function to_string(
val : t_signed_array;
radix : t_radix := HEX_BIN_IF_INVALID;
format : t_format_zeros := KEEP_LEADING_0; -- | SKIP_LEADING_0
prefix : t_radix_prefix := EXCL_RADIX -- Insert radix prefix in string?
) return string is
variable v_line : line;
variable v_result : string(1 to 2 + -- parentheses
2*(val'length - 1) + -- commas
26*val'length); -- 26 is max length of returned value from slv to_string()
variable v_width : natural;
begin
if val'length = 0 then
return "";
else
-- Comma-separate all array members and return
write(v_line, string'("("));
for idx in val'range loop
write(v_line, to_string(val(idx), radix, format, prefix));
if (idx < val'right) and (val'ascending) then
write(v_line, string'(", "));
elsif (idx > val'right) and not(val'ascending) then
write(v_line, string'(", "));
end if;
end loop;
write(v_line, string'(")"));
v_width := v_line'length;
v_result(1 to v_width) := v_line.all;
deallocate(v_line);
return v_result(1 to v_width);
end if;
end function;
function to_string(
val : t_unsigned_array;
radix : t_radix := HEX_BIN_IF_INVALID;
format : t_format_zeros := KEEP_LEADING_0; -- | SKIP_LEADING_0
prefix : t_radix_prefix := EXCL_RADIX -- Insert radix prefix in string?
) return string is
variable v_line : line;
variable v_result : string(1 to 2 + -- parentheses
2*(val'length - 1) + -- commas
26*val'length); -- 26 is max length of returned value from slv to_string()
variable v_width : natural;
begin
if val'length = 0 then
return "";
else
-- Comma-separate all array members and return
write(v_line, string'("("));
for idx in val'range loop
write(v_line, to_string(val(idx), radix, format, prefix));
if (idx < val'right) and (val'ascending) then
write(v_line, string'(", "));
elsif (idx > val'right) and not(val'ascending) then
write(v_line, string'(", "));
end if;
end loop;
write(v_line, string'(")"));
v_width := v_line'length;
v_result(1 to v_width) := v_line.all;
deallocate(v_line);
return v_result(1 to v_width);
end if;
end function;
--========================================================
-- Handle types defined at lower levels
--========================================================
function to_string(
val : t_alert_level;
width : natural;
justified : side := right
) return string is
constant inner_string : string := t_alert_level'image(val);
begin
return to_upper(justify(inner_string, justified, width));
end function;
function to_string(
val : t_msg_id;
width : natural;
justified : side := right
) return string is
constant inner_string : string := t_msg_id'image(val);
begin
return to_upper(justify(inner_string, justified, width));
end function;
function to_string(
val : t_attention;
width : natural;
justified : side := right
) return string is
begin
return to_upper(justify(t_attention'image(val), justified, width));
end;
-- function to_string(
-- dummy : t_void
-- ) return string is
-- begin
-- return "VOID";
-- end function;
procedure to_string(
val : t_alert_attention_counters;
order : t_order := FINAL
) is
variable v_line : line;
variable v_line_copy : line;
variable v_more_than_expected_alerts : boolean := false;
variable v_less_than_expected_alerts : boolean := false;
variable v_header : string(1 to 42);
constant prefix : string := C_LOG_PREFIX & " ";
begin
if order = INTERMEDIATE then
v_header := "*** INTERMEDIATE SUMMARY OF ALL ALERTS ***";
else -- order=FINAL
v_header := "*** FINAL SUMMARY OF ALL ALERTS *** ";
end if;
write(v_line,
LF &
fill_string('=', (C_LOG_LINE_WIDTH - prefix'length)) & LF &
v_header & LF &
fill_string('=', (C_LOG_LINE_WIDTH - prefix'length)) & LF &
" REGARDED EXPECTED IGNORED Comment?" & LF);
for i in NOTE to t_alert_level'right loop
write(v_line, " " & to_upper(to_string(i, 13, LEFT)) & ": "); -- Severity
for j in t_attention'left to t_attention'right loop
write(v_line, to_string(integer'(val(i)(j)), 6, RIGHT, KEEP_LEADING_SPACE) & " ");
end loop;
if (val(i)(REGARD) = val(i)(EXPECT)) then
write(v_line, " ok " & LF);
else
write(v_line, " *** " & to_string(i,0) & " *** " & LF);
if (i > MANUAL_CHECK) then
if (val(i)(REGARD) < val(i)(EXPECT)) then
v_less_than_expected_alerts := true;
else
v_more_than_expected_alerts := true;
end if;
end if;
end if;
end loop;
write(v_line, fill_string('=', (C_LOG_LINE_WIDTH - prefix'length)) & LF);
-- Print a conclusion when called from the FINAL part of the test sequencer
-- but not when called from in the middle of the test sequence (order=INTERMEDIATE)
if order = FINAL then
if v_more_than_expected_alerts then
write(v_line, ">> Simulation FAILED, with unexpected serious alert(s)" & LF);
elsif v_less_than_expected_alerts then
write(v_line, ">> Simulation FAILED: Mismatch between counted and expected serious alerts" & LF);
else
write(v_line, ">> Simulation SUCCESS: No mismatch between counted and expected serious alerts" & LF);
end if;
write(v_line, fill_string('=', (C_LOG_LINE_WIDTH - prefix'length)) & LF & LF);
end if;
wrap_lines(v_line, 1, 1, C_LOG_LINE_WIDTH-prefix'length);
prefix_lines(v_line, prefix);
-- Write the info string to the target file
write (v_line_copy, v_line.all & lf); -- copy line
writeline(OUTPUT, v_line);
writeline(LOG_FILE, v_line_copy);
end;
-- Convert from ASCII to character
-- Inputs:
-- ascii_pos (integer) : ASCII number input
-- ascii_allow (t_ascii_allow) : Decide what to do with invisible control characters:
-- - If ascii_allow = ALLOW_ALL (default) : return the character for any ascii_pos
-- - If ascii_allow = ALLOW_PRINTABLE_ONLY : return the character only if it is printable
function ascii_to_char(
ascii_pos : integer range 0 to 255; -- Supporting Extended ASCII
ascii_allow : t_ascii_allow := ALLOW_ALL
) return character is
variable v_printable : boolean := true;
begin
if ascii_pos < 32 or -- NUL, SOH, STX etc
(ascii_pos >= 128 and ascii_pos < 160) then -- C128 to C159
v_printable := false;
end if;
if ascii_allow = ALLOW_ALL or
(ascii_allow = ALLOW_PRINTABLE_ONLY and v_printable) then
return character'val(ascii_pos);
else
return ' '; -- Must return something when invisible control signals
end if;
end;
-- Convert from character to ASCII integer
function char_to_ascii(
char : character
) return integer is
begin
return character'pos(char);
end;
-- return string with only valid ascii characters
function to_string(
val : string
) return string is
variable v_new_string : string(1 to val'length);
variable v_char_idx : natural := 0;
variable v_ascii_pos : natural;
begin
for i in val'range loop
v_ascii_pos := character'pos(val(i));
if (v_ascii_pos < 32 and v_ascii_pos /= 10) or -- NUL, SOH, STX etc, LF(10) is not removed.
(v_ascii_pos >= 128 and v_ascii_pos < 160) then -- C128 to C159
-- illegal char
null;
else
-- legal char
v_char_idx := v_char_idx + 1;
v_new_string(v_char_idx) := val(i);
end if;
end loop;
if v_char_idx = 0 then
return "";
else
return v_new_string(1 to v_char_idx);
end if;
end;
function add_msg_delimiter(
msg : string
) return string is
begin
if msg'length /= 0 then
if valid_length(msg) /= 1 then
if msg(1) = C_MSG_DELIMITER then
return msg;
else
return C_MSG_DELIMITER & msg & C_MSG_DELIMITER;
end if;
end if;
end if;
return "";
end;
end package body string_methods_pkg;
|
mit
|
UVVM/uvvm_vvc_framework
|
bitvis_vip_sbi/src/vvc_methods_pkg.vhd
|
2
|
15838
|
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
use work.sbi_bfm_pkg.all;
use work.vvc_cmd_pkg.all;
use work.td_target_support_pkg.all;
--=================================================================================================
--=================================================================================================
--=================================================================================================
package vvc_methods_pkg is
--===============================================================================================
-- Types and constants for the SBI VVC
--===============================================================================================
constant C_VVC_NAME : string := "SBI_VVC";
signal SBI_VVCT : t_vvc_target_record := set_vvc_target_defaults(C_VVC_NAME);
alias THIS_VVCT : t_vvc_target_record is SBI_VVCT;
alias t_bfm_config is t_sbi_bfm_config;
-- Type found in UVVM-Util types_pkg
constant C_SBI_INTER_BFM_DELAY_DEFAULT : t_inter_bfm_delay := (
delay_type => NO_DELAY,
delay_in_time => 0 ns,
inter_bfm_delay_violation_severity => WARNING
);
type t_vvc_config is
record
inter_bfm_delay : t_inter_bfm_delay;-- Minimum delay between BFM accesses from the VVC. If parameter delay_type is set to NO_DELAY, BFM accesses will be back to back, i.e. no delay.
cmd_queue_count_max : natural; -- Maximum pending number in command queue before queue is full. Adding additional commands will result in an ERROR.
cmd_queue_count_threshold : natural; -- An alert with severity 'cmd_queue_count_threshold_severity' will be issued if command queue exceeds this count. Used for early warning if command queue is almost full. Will be ignored if set to 0.
cmd_queue_count_threshold_severity : t_alert_level; -- Severity of alert to be initiated if exceeding cmd_queue_count_threshold
result_queue_count_max : natural;
result_queue_count_threshold_severity : t_alert_level;
result_queue_count_threshold : natural;
bfm_config : t_sbi_bfm_config; -- Configuration for the BFM. See BFM quick reference
msg_id_panel : t_msg_id_panel; -- VVC dedicated message ID panel
end record;
type t_vvc_config_array is array (natural range <>) of t_vvc_config;
constant C_SBI_VVC_CONFIG_DEFAULT : t_vvc_config := (
inter_bfm_delay => C_SBI_INTER_BFM_DELAY_DEFAULT,
cmd_queue_count_max => C_CMD_QUEUE_COUNT_MAX, -- from adaptation package
cmd_queue_count_threshold => C_CMD_QUEUE_COUNT_THRESHOLD,
cmd_queue_count_threshold_severity => C_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY,
result_queue_count_max => C_RESULT_QUEUE_COUNT_MAX,
result_queue_count_threshold_severity => C_RESULT_QUEUE_COUNT_THRESHOLD_SEVERITY,
result_queue_count_threshold => C_RESULT_QUEUE_COUNT_THRESHOLD,
bfm_config => C_SBI_BFM_CONFIG_DEFAULT,
msg_id_panel => C_VVC_MSG_ID_PANEL_DEFAULT
);
type t_vvc_status is
record
current_cmd_idx : natural;
previous_cmd_idx : natural;
pending_cmd_cnt : natural;
end record;
type t_vvc_status_array is array (natural range <>) of t_vvc_status;
constant C_VVC_STATUS_DEFAULT : t_vvc_status := (
current_cmd_idx => 0,
previous_cmd_idx => 0,
pending_cmd_cnt => 0
);
-- Transaction information to include in the wave view during simulation
type t_transaction_info is
record
operation : t_operation;
addr : unsigned(C_VVC_CMD_ADDR_MAX_LENGTH-1 downto 0);
data : std_logic_vector(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0);
msg : string(1 to C_VVC_CMD_STRING_MAX_LENGTH);
end record;
type t_transaction_info_array is array (natural range <>) of t_transaction_info;
constant C_TRANSACTION_INFO_DEFAULT : t_transaction_info := (
operation => NO_OPERATION,
addr => (others => '0'),
data => (others => '0'),
msg => (others => ' ')
);
shared variable shared_sbi_vvc_config : t_vvc_config_array(0 to C_MAX_VVC_INSTANCE_NUM) := (others => C_SBI_VVC_CONFIG_DEFAULT);
shared variable shared_sbi_vvc_status : t_vvc_status_array(0 to C_MAX_VVC_INSTANCE_NUM) := (others => C_VVC_STATUS_DEFAULT);
shared variable shared_sbi_transaction_info : t_transaction_info_array(0 to C_MAX_VVC_INSTANCE_NUM) := (others => C_TRANSACTION_INFO_DEFAULT);
--==============================================================================
-- Methods dedicated to this VVC
-- - These procedures are called from the testbench in order to queue BFM calls
-- in the VVC command queue. The VVC will store and forward these calls to the
-- SBI BFM when the command is at the from of the VVC command queue.
-- - For details on how the BFM procedures work, see sbi_bfm_pkg.vhd or the
-- quickref.
--==============================================================================
procedure sbi_write(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant addr : in unsigned;
constant data : in std_logic_vector;
constant msg : in string
);
procedure sbi_read(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant addr : in unsigned;
constant msg : in string
);
procedure sbi_check(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant addr : in unsigned;
constant data : in std_logic_vector;
constant msg : in string;
constant alert_level : in t_alert_level := ERROR
);
procedure sbi_poll_until(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant addr : in unsigned;
constant data : in std_logic_vector;
constant msg : in string;
constant max_polls : in integer := 100;
constant timeout : in time := 1 us; -- To assure a given timeout
constant alert_level : in t_alert_level := ERROR
);
end package vvc_methods_pkg;
package body vvc_methods_pkg is
--==============================================================================
-- Methods dedicated to this VVC
-- Notes:
-- - shared_vvc_cmd is initialised to C_VVC_CMD_DEFAULT, and also reset to this after every command
--==============================================================================
procedure sbi_write(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant addr : in unsigned;
constant data : in std_logic_vector;
constant msg : in string
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) -- First part common for all
& ", " & to_string(addr, HEX, AS_IS, INCL_RADIX) & ", " & to_string(data, HEX, AS_IS, INCL_RADIX) & ")";
variable v_normalised_addr : unsigned(shared_vvc_cmd.addr'length-1 downto 0) :=
normalize_and_check(addr, shared_vvc_cmd.addr, ALLOW_WIDER_NARROWER, "addr", "shared_vvc_cmd.addr", proc_call & " called with to wide address. " & add_msg_delimiter(msg));
variable v_normalised_data : std_logic_vector(shared_vvc_cmd.data'length-1 downto 0) :=
normalize_and_check(data, shared_vvc_cmd.data, ALLOW_WIDER_NARROWER, "data", "shared_vvc_cmd.data", proc_call & " called with to wide data. " & add_msg_delimiter(msg));
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, WRITE);
shared_vvc_cmd.addr := v_normalised_addr;
shared_vvc_cmd.data := v_normalised_data;
send_command_to_vvc(VVCT);
end procedure;
procedure sbi_read(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant addr : in unsigned;
constant msg : in string
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) -- First part common for all
& ", " & to_string(addr, HEX, AS_IS, INCL_RADIX) & ")";
variable v_normalised_addr : unsigned(shared_vvc_cmd.addr'length-1 downto 0) :=
normalize_and_check(addr, shared_vvc_cmd.addr, ALLOW_WIDER_NARROWER, "addr", "shared_vvc_cmd.addr", proc_call & " called with to wide address. " & add_msg_delimiter(msg));
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, READ);
shared_vvc_cmd.operation := READ;
shared_vvc_cmd.addr := v_normalised_addr;
send_command_to_vvc(VVCT);
end procedure;
procedure sbi_check(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant addr : in unsigned;
constant data : in std_logic_vector;
constant msg : in string;
constant alert_level : in t_alert_level := ERROR
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) -- First part common for all
& ", " & to_string(addr, HEX, AS_IS, INCL_RADIX) & ", " & to_string(data, HEX, AS_IS, INCL_RADIX) & ")";
variable v_normalised_addr : unsigned(shared_vvc_cmd.addr'length-1 downto 0) :=
normalize_and_check(addr, shared_vvc_cmd.addr, ALLOW_WIDER_NARROWER, "addr", "shared_vvc_cmd.addr", proc_call & " called with to wide address. " & add_msg_delimiter(msg));
variable v_normalised_data : std_logic_vector(shared_vvc_cmd.data'length-1 downto 0) :=
normalize_and_check(data, shared_vvc_cmd.data, ALLOW_WIDER_NARROWER, "data", "shared_vvc_cmd.data", proc_call & " called with to wide data. " & add_msg_delimiter(msg));
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, CHECK);
shared_vvc_cmd.addr := v_normalised_addr;
shared_vvc_cmd.data := v_normalised_data;
shared_vvc_cmd.alert_level := alert_level;
send_command_to_vvc(VVCT);
end procedure;
procedure sbi_poll_until(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant addr : in unsigned;
constant data : in std_logic_vector;
constant msg : in string;
constant max_polls : in integer := 100;
constant timeout : in time := 1 us;
constant alert_level : in t_alert_level := ERROR
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) -- First part common for all
& ", " & to_string(addr, HEX, AS_IS, INCL_RADIX) & ", " & to_string(data, HEX, AS_IS, INCL_RADIX) & ")";
variable v_normalised_addr : unsigned(shared_vvc_cmd.addr'length-1 downto 0) :=
normalize_and_check(addr, shared_vvc_cmd.addr, ALLOW_WIDER_NARROWER, "addr", "shared_vvc_cmd.addr", proc_call & " called with to wide address. " & add_msg_delimiter(msg));
variable v_normalised_data : std_logic_vector(shared_vvc_cmd.data'length-1 downto 0) :=
normalize_and_check(data, shared_vvc_cmd.data, ALLOW_WIDER_NARROWER, "data", "shared_vvc_cmd.data", proc_call & " called with to wide data. " & add_msg_delimiter(msg));
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, POLL_UNTIL);
shared_vvc_cmd.addr := v_normalised_addr;
shared_vvc_cmd.data := v_normalised_data;
shared_vvc_cmd.max_polls := max_polls;
shared_vvc_cmd.timeout := timeout;
shared_vvc_cmd.alert_level := alert_level;
send_command_to_vvc(VVCT);
end procedure;
end package body vvc_methods_pkg;
|
mit
|
UVVM/uvvm_vvc_framework
|
bitvis_vip_scoreboard/demo/sb_uart_sbi_demo_tb.vhd
|
1
|
7650
|
--========================================================================================================================
-- Copyright (c) 2018 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library bitvis_uart;
use bitvis_uart.uart_pif_pkg.all;
library bitvis_vip_sbi;
use bitvis_vip_sbi.sbi_bfm_pkg.all;
library bitvis_vip_uart;
use bitvis_vip_uart.uart_bfm_pkg.all;
library bitvis_vip_scoreboard;
use bitvis_vip_scoreboard.slv_sb_pkg.all;
use bitvis_vip_scoreboard.generic_sb_support_pkg.all;
-- Test harness entity
entity sb_uart_sbi_demo_tb is
end entity sb_uart_sbi_demo_tb;
-- Test harness architecture
architecture func of sb_uart_sbi_demo_tb is
constant C_SCOPE : string := "TB";
constant C_ADDR_WIDTH : integer := 3;
constant C_DATA_WIDTH : integer := 8;
-- DSP interface and general control signals
signal clk : std_logic := '0';
signal clk_ena : boolean := false;
signal arst : std_logic := '0';
-- SBI signals
signal sbi_if : t_sbi_if(addr(C_ADDR_WIDTH-1 downto 0),
wdata(C_DATA_WIDTH-1 downto 0),
rdata(C_DATA_WIDTH-1 downto 0)) := init_sbi_if_signals(addr_width => C_ADDR_WIDTH,
data_width => C_DATA_WIDTH);
signal terminate_loop : std_logic := '0';
-- UART signals
signal uart_rx : std_logic := '1';
signal uart_tx : std_logic := '1';
constant C_CLK_PERIOD : time := 10 ns; -- 100 MHz
-- One SB for each side of the DUT
shared variable v_uart_sb : t_generic_sb;
shared variable v_sbi_sb : t_generic_sb;
begin
-----------------------------------------------------------------------------
-- Instantiate DUT
-----------------------------------------------------------------------------
i_uart: entity bitvis_uart.uart
port map (
-- DSP interface and general control signals
clk => clk,
arst => arst,
-- CPU interface
cs => sbi_if.cs,
addr => sbi_if.addr,
wr => sbi_if.wena,
rd => sbi_if.rena,
wdata => sbi_if.wdata,
rdata => sbi_if.rdata,
-- UART signals
rx_a => uart_tx,
tx => uart_rx
);
-----------------------------------------------------------------------------
-- Clock generator
-----------------------------------------------------------------------------
p_clk: clock_generator(clk, clk_ena, C_CLK_PERIOD, "tb clock");
-- Static '1' ready signal for the SBI VVC
sbi_if.ready <= '1';
-- Toggle the reset after 5 clock periods
p_arst: arst <= '1', '0' after 5 *C_CLK_PERIOD;
-----------------------------------------------------------------------------
-- Sequencer
-----------------------------------------------------------------------------
p_sequencer : process
variable v_data : std_logic_vector(7 downto 0);
variable v_uart_config : t_uart_bfm_config;
begin
set_log_file_name("sb_uart_sbi_demo_log.txt");
set_alert_file_name("sb_uart_sbi_demo_alert.txt");
-- Print the configuration to the log
report_global_ctrl(VOID);
report_msg_id_panel(VOID);
--enable_log_msg(ALL_MESSAGES);
disable_log_msg(ID_POS_ACK);
--disable_log_msg(ID_SEQUENCER_SUB);
log(ID_LOG_HDR_XL, "SCOREBOARD UART-SBI DEMO ", C_SCOPE);
------------------------------------------------------------
clk_ena <= true;
wait for 1 ns;
await_value(arst, '0', 0 ns, 6*C_CLK_PERIOD, TB_ERROR, "await deassertion of arst", C_SCOPE);
wait for C_CLK_PERIOD;
------------------------------------------------------------
-- Config
------------------------------------------------------------
-- Set scope of SBs
v_uart_sb.set_scope("SB UART");
v_sbi_sb.set_scope( "SB SBI");
log(ID_LOG_HDR, "Set configuration", C_SCOPE);
v_uart_sb.config(C_SB_CONFIG_DEFAULT, "Set config for SB UART");
v_sbi_sb.config( C_SB_CONFIG_DEFAULT, "Set config for SB SBI");
log(ID_LOG_HDR, "Enable SBs", C_SCOPE);
v_uart_sb.enable(VOID);
v_sbi_sb.enable(VOID);
-- Enable log msg for data
v_uart_sb.enable_log_msg(ID_DATA);
v_sbi_sb.enable_log_msg( ID_DATA);
v_uart_config := C_UART_BFM_CONFIG_DEFAULT;
v_uart_config.bit_time := C_CLK_PERIOD*16;
------------------------------------------------------------
-- UART --> SBI
------------------------------------------------------------
log(ID_LOG_HDR_LARGE, "Send data UART --> SBI", C_SCOPE);
for i in 1 to 5 loop
for j in 1 to 4 loop
v_data := random(8);
v_sbi_sb.add_expected(v_data);
uart_transmit(v_data, "data to DUT", uart_tx, v_uart_config);
end loop;
for j in 1 to 4 loop
sbi_poll_until(to_unsigned(C_ADDR_RX_DATA_VALID, 3), x"01", 0, 100 ns, "wait on data valid", clk, sbi_if, terminate_loop);
sbi_read(to_unsigned(C_ADDR_RX_DATA, 3), v_data, "read data from DUT", clk, sbi_if);
v_sbi_sb.check_actual(v_data);
end loop;
end loop;
-- print report of counters
v_sbi_sb.report_counters(VOID);
------------------------------------------------------------
-- SBI --> UART
------------------------------------------------------------
log(ID_LOG_HDR_LARGE, "Send data SBI --> UART", C_SCOPE);
for i in 1 to 5 loop
for j in 1 to 4 loop
v_data := random(8);
v_uart_sb.add_expected(v_data);
sbi_poll_until(to_unsigned(C_ADDR_TX_READY, 3), x"01", 0, 100 ns, "wait on TX ready", clk, sbi_if, terminate_loop);
sbi_write(to_unsigned(C_ADDR_TX_DATA, 3), v_data, "write data to DUT", clk, sbi_if);
uart_receive(v_data, "data from DUT", uart_rx, terminate_loop, v_uart_config);
v_uart_sb.check_actual(v_data);
end loop;
end loop;
-- print report of counters
v_uart_sb.report_counters(VOID);
--==================================================================================================
-- Ending the simulation
--------------------------------------------------------------------------------------
wait for 1000 ns; -- to allow some time for completion
report_alert_counters(FINAL); -- Report final counters and print conclusion for simulation (Success/Fail)
log(ID_LOG_HDR, "SIMULATION COMPLETED", C_SCOPE);
std.env.stop;
wait;
end process;
end architecture func;
|
mit
|
UVVM/uvvm_vvc_framework
|
uvvm_vvc_framework/src/ti_uvvm_engine.vhd
|
2
|
2316
|
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
entity ti_uvvm_engine is
end entity;
architecture func of ti_uvvm_engine is
begin
--------------------------------------------------------
-- Initializes the UVVM VVC Framework
--------------------------------------------------------
p_initialize_uvvm : process
begin
-- shared_uvvm_state is initialized to IDLE. Hence it will stay in IDLE if this procedure is not included in the TB
shared_uvvm_state := PHASE_A;
wait for 0 ns; -- A single delta cycle
wait for 0 ns; -- A single delta cycle
if (shared_uvvm_state = PHASE_B) then
tb_failure("ti_uvvm_engine seems to have been instantiated more than once in this testbench system", C_SCOPE);
end if;
shared_uvvm_state := PHASE_B;
wait for 0 ns; -- A single delta cycle
wait for 0 ns; -- A single delta cycle
shared_uvvm_state := INIT_COMPLETED;
wait;
end process p_initialize_uvvm;
end func;
|
mit
|
UVVM/uvvm_vvc_framework
|
uvvm_util/src/alert_hierarchy_pkg.vhd
|
2
|
7612
|
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
use std.env.all;
use work.types_pkg.all;
use work.protected_types_pkg.all;
use work.hierarchy_linked_list_pkg.all;
use work.string_methods_pkg.all;
use work.adaptations_pkg.all;
package alert_hierarchy_pkg is
shared variable global_hierarchy_tree : t_hierarchy_linked_list;
procedure initialize_hierarchy(
constant base_scope : string := C_BASE_HIERARCHY_LEVEL;
constant stop_limit : t_alert_counters := (others => 0)
);
procedure add_to_alert_hierarchy(
constant scope : string;
constant parent_scope : string := C_BASE_HIERARCHY_LEVEL;
constant stop_limit : t_alert_counters := (others => 0)
);
procedure set_hierarchical_alert_top_level_stop_limit(
constant alert_level : t_alert_level;
constant value : natural
);
impure function get_hierarchical_alert_top_level_stop_limit(
constant alert_level : t_alert_level
) return natural;
procedure hierarchical_alert(
constant alert_level: t_alert_level;
constant msg : string;
constant scope : string;
constant attention : t_attention
);
procedure increment_expected_alerts(
constant scope : string;
constant alert_level: t_alert_level;
constant amount : natural := 1
);
procedure set_expected_alerts(
constant scope : string;
constant alert_level: t_alert_level;
constant expected_alerts : natural
);
procedure increment_stop_limit(
constant scope : string;
constant alert_level: t_alert_level;
constant amount : natural := 1
);
procedure set_stop_limit(
constant scope : string;
constant alert_level: t_alert_level;
constant stop_limit : natural
);
procedure print_hierarchical_log(
constant order : t_order := FINAL
);
procedure clear_hierarchy(
constant VOID : t_void
);
end package alert_hierarchy_pkg;
package body alert_hierarchy_pkg is
procedure initialize_hierarchy(
constant base_scope : string := C_BASE_HIERARCHY_LEVEL;
constant stop_limit : t_alert_counters := (others => 0)
) is
begin
global_hierarchy_tree.initialize_hierarchy(justify(base_scope, LEFT, C_HIERARCHY_NODE_NAME_LENGTH), stop_limit);
end procedure;
procedure add_to_alert_hierarchy(
constant scope : string;
constant parent_scope : string := C_BASE_HIERARCHY_LEVEL;
constant stop_limit : t_alert_counters := (others => 0)
) is
variable v_scope : string(1 to C_HIERARCHY_NODE_NAME_LENGTH) := justify(scope, LEFT, C_HIERARCHY_NODE_NAME_LENGTH);
variable v_parent_scope : string(1 to C_HIERARCHY_NODE_NAME_LENGTH) := justify(parent_scope, LEFT, C_HIERARCHY_NODE_NAME_LENGTH);
variable v_hierarchy_node : t_hierarchy_node;
variable v_found : boolean := false;
begin
global_hierarchy_tree.contains_scope_return_data(v_scope, v_found, v_hierarchy_node);
if v_found then
-- Scope already in tree.
-- If the new parent is not C_BASE_HIERARCHY_LEVEL, change parent.
-- The reason is that a child should be able to register itself
-- with C_BASE_HIERARCHY_LEVEL as parent. The actual parent can then
-- override the registration with a new parent_scope. However, the other
-- way should not be possible. I.e., a child registration should not be able
-- to override a parent registration later. That means that parents can't be
-- changed back to base level once another parent_scope has been chosen.
if v_parent_scope /= justify(C_BASE_HIERARCHY_LEVEL, LEFT, C_HIERARCHY_NODE_NAME_LENGTH) then
-- Verify that new parent is in tree. If not, the old parent will be kept.
global_hierarchy_tree.change_parent(v_scope, v_parent_scope);
end if;
else
-- Scope not in tree. Check if parent is in tree. Set node data if
-- parent is in tree.
v_hierarchy_node := (v_scope, (others => (others => 0)), stop_limit, (others => true));
global_hierarchy_tree.insert_in_tree(v_hierarchy_node, v_parent_scope);
end if;
end procedure;
procedure set_hierarchical_alert_top_level_stop_limit(
constant alert_level : t_alert_level;
constant value : natural
) is
begin
global_hierarchy_tree.set_top_level_stop_limit(alert_level, value);
end procedure;
impure function get_hierarchical_alert_top_level_stop_limit(
constant alert_level : t_alert_level
) return natural is
begin
return global_hierarchy_tree.get_top_level_stop_limit(alert_level);
end function;
procedure hierarchical_alert(
constant alert_level: t_alert_level;
constant msg : string;
constant scope : string;
constant attention : t_attention
) is
begin
global_hierarchy_tree.alert(justify(scope, LEFT, C_HIERARCHY_NODE_NAME_LENGTH), alert_level, attention, msg);
end procedure;
procedure increment_expected_alerts(
constant scope : string;
constant alert_level: t_alert_level;
constant amount : natural := 1
) is
begin
global_hierarchy_tree.increment_expected_alerts(justify(scope, LEFT, C_HIERARCHY_NODE_NAME_LENGTH), alert_level, amount);
end procedure;
procedure set_expected_alerts(
constant scope : string;
constant alert_level: t_alert_level;
constant expected_alerts : natural
) is
begin
global_hierarchy_tree.set_expected_alerts(justify(scope, LEFT, C_HIERARCHY_NODE_NAME_LENGTH), alert_level, expected_alerts);
end procedure;
procedure increment_stop_limit(
constant scope : string;
constant alert_level: t_alert_level;
constant amount : natural := 1
) is
begin
global_hierarchy_tree.increment_stop_limit(justify(scope, LEFT, C_HIERARCHY_NODE_NAME_LENGTH), alert_level, amount);
end procedure;
procedure set_stop_limit(
constant scope : string;
constant alert_level: t_alert_level;
constant stop_limit : natural
) is
begin
global_hierarchy_tree.set_stop_limit(justify(scope, LEFT, C_HIERARCHY_NODE_NAME_LENGTH), alert_level, stop_limit);
end procedure;
procedure print_hierarchical_log(
constant order : t_order := FINAL
) is
begin
global_hierarchy_tree.print_hierarchical_log(order);
end procedure;
procedure clear_hierarchy(
constant VOID : t_void
) is
begin
global_hierarchy_tree.clear;
end procedure;
end package body alert_hierarchy_pkg;
|
mit
|
UVVM/uvvm_vvc_framework
|
bitvis_uart/src/uart_pif.vhd
|
3
|
3359
|
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.uart_pif_pkg.all;
entity uart_pif is
port(
arst : in std_logic;
clk : in std_logic;
-- CPU interface
cs : in std_logic;
addr : in unsigned;
wr : in std_logic;
rd : in std_logic;
wdata : in std_logic_vector(7 downto 0);
rdata : out std_logic_vector(7 downto 0) := (others => '0');
--
p2c : out t_p2c;
c2p : in t_c2p
);
end uart_pif;
architecture rtl of uart_pif is
signal p2c_i : t_p2c; -- internal version of output
signal rdata_i : std_logic_vector(7 downto 0) := (others => '0');
begin
-- Assigning internally used signals to outputs
p2c <= p2c_i;
--
-- Auxiliary Register Control.
--
-- Provides read/write/trigger strobes and write data to auxiliary
-- registers and fields, i.e., registers and fields implemented in core.
--
p_aux : process (wdata, addr, cs, wr, rd)
begin
-- Defaults
p2c_i.awo_tx_data <= (others => '0');
p2c_i.awo_tx_data_we <= '0';
p2c_i.aro_rx_data_re <= '0';
-- Write decoding
if wr = '1' and cs = '1' then
case to_integer(addr) is
when C_ADDR_TX_DATA =>
p2c_i.awo_tx_data <= wdata;
p2c_i.awo_tx_data_we <= '1';
when others =>
null;
end case;
end if;
-- Read Enable Decoding
if rd = '1' and cs = '1' then
case to_integer(addr) is
when C_ADDR_RX_DATA =>
p2c_i.aro_rx_data_re <= '1';
when others =>
null;
end case;
end if;
end process p_aux;
p_read_reg : process(cs, addr, rd, c2p, p2c_i)
begin
-- default values
rdata_i <= (others => '0');
if cs = '1' and rd = '1' then
case to_integer(addr) is
when C_ADDR_RX_DATA =>
rdata_i(7 downto 0) <= c2p.aro_rx_data;
when C_ADDR_RX_DATA_VALID =>
rdata_i(0) <= c2p.aro_rx_data_valid;
when C_ADDR_TX_READY =>
rdata_i(0) <= c2p.aro_tx_ready;
when others =>
null;
end case;
end if;
end process p_read_reg;
rdata <= rdata_i;
end rtl;
|
mit
|
UVVM/uvvm_vvc_framework
|
bitvis_uart/src/uart.vhd
|
2
|
3591
|
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.uart_pif_pkg.all;
entity uart is
generic (
GC_START_BIT : std_logic := '0';
GC_STOP_BIT : std_logic := '1';
GC_CLOCKS_PER_BIT : integer := 16;
GC_MIN_EQUAL_SAMPLES_PER_BIT : integer := 15); -- Number of equal samples needed for valid bit, uart samples on every clock
port(
-- DSP interface and general control signals
clk : in std_logic;
arst : in std_logic;
-- CPU interface
cs : in std_logic;
addr : in unsigned(2 downto 0);
wr : in std_logic;
rd : in std_logic;
wdata : in std_logic_vector(7 downto 0);
rdata : out std_logic_vector(7 downto 0) := (others => '0');
-- UART related signals
rx_a : in std_logic;
tx : out std_logic
);
begin
assert GC_MIN_EQUAL_SAMPLES_PER_BIT > GC_CLOCKS_PER_BIT/2 and GC_MIN_EQUAL_SAMPLES_PER_BIT < GC_CLOCKS_PER_BIT
report "GC_MIN_EQUAL_SAMPLES_PER_BIT must be between GC_CLOCKS_PER_BIT/2 and GC_CLOCKS_PER_BIT"
severity FAILURE;
end uart;
architecture rtl of uart is
-- PIF-core interface
signal p2c : t_p2c; --
signal c2p : t_c2p; --
begin
i_uart_pif : entity work.uart_pif
port map (
arst => arst, --
clk => clk, --
-- CPU interface
cs => cs, --
addr => addr, --
wr => wr, --
rd => rd, --
wdata => wdata, --
rdata => rdata, --
--
p2c => p2c, --
c2p => c2p --
);
i_uart_core : entity work.uart_core
generic map(
GC_START_BIT => GC_START_BIT,
GC_STOP_BIT => GC_STOP_BIT,
GC_CLOCKS_PER_BIT => GC_CLOCKS_PER_BIT,
GC_MIN_EQUAL_SAMPLES_PER_BIT => GC_MIN_EQUAL_SAMPLES_PER_BIT
)
port map (
clk => clk, --
arst => arst, --
-- PIF-core interface
p2c => p2c, --
c2p => c2p, --
-- Interrupt related signals
rx_a => rx_a, --
tx => tx
);
end rtl;
|
mit
|
UVVM/uvvm_vvc_framework
|
bitvis_vip_uart/src/vvc_methods_pkg.vhd
|
2
|
12802
|
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
use work.uart_bfm_pkg.all;
use work.vvc_cmd_pkg.all;
use work.td_target_support_pkg.all;
--=================================================================================================
--=================================================================================================
--=================================================================================================
package vvc_methods_pkg is
constant C_VVC_NAME : string := "UART_VVC";
constant C_EXECUTOR_RESULT_ARRAY_DEPTH : natural := 3;
signal UART_VVCT : t_vvc_target_record := set_vvc_target_defaults(C_VVC_NAME);
alias THIS_VVCT : t_vvc_target_record is UART_VVCT;
alias t_bfm_config is t_uart_bfm_config;
-- Type found in UVVM-Util types_pkg
constant C_UART_INTER_BFM_DELAY_DEFAULT : t_inter_bfm_delay := (
delay_type => NO_DELAY,
delay_in_time => 0 ns,
inter_bfm_delay_violation_severity => WARNING
);
type t_vvc_config is
record
inter_bfm_delay : t_inter_bfm_delay; -- Minimum delay between BFM accesses from the VVC. If parameter delay_type is set to NO_DELAY, BFM accesses will be back to back, i.e. no delay.
cmd_queue_count_max : natural; -- Maximum pending number in command queue before queue is full. Adding additional commands will result in an ERROR.
cmd_queue_count_threshold : natural; -- An alert with severity 'cmd_queue_count_threshold_severity' will be issued if command queue exceeds this count. Used for early warning if command queue is almost full. Will be ignored if set to 0.
cmd_queue_count_threshold_severity : t_alert_level; -- Severity of alert to be initiated if exceeding cmd_queue_count_threshold
result_queue_count_max : natural; -- Maximum number of unfetched results before result_queue is full.
result_queue_count_threshold_severity : t_alert_level; -- An alert with severity 'result_queue_count_threshold_severity' will be issued if command queue exceeds this count. Used for early warning if result queue is almost full. Will be ignored if set to 0.
result_queue_count_threshold : natural; -- Severity of alert to be initiated if exceeding result_queue_count_threshold
bfm_config : t_uart_bfm_config; -- Configuration for the BFM. See BFM quick reference
msg_id_panel : t_msg_id_panel; -- VVC dedicated message ID panel
end record;
type t_vvc_config_array is array (t_channel range <>, natural range <>) of t_vvc_config;
constant C_UART_VVC_CONFIG_DEFAULT : t_vvc_config := (
inter_bfm_delay => C_UART_INTER_BFM_DELAY_DEFAULT,
cmd_queue_count_max => C_CMD_QUEUE_COUNT_MAX, -- from adaptation package
cmd_queue_count_threshold => C_CMD_QUEUE_COUNT_THRESHOLD,
cmd_queue_count_threshold_severity => C_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY,
result_queue_count_max => C_RESULT_QUEUE_COUNT_MAX,
result_queue_count_threshold_severity => C_RESULT_QUEUE_COUNT_THRESHOLD_SEVERITY,
result_queue_count_threshold => C_RESULT_QUEUE_COUNT_THRESHOLD,
bfm_config => C_UART_BFM_CONFIG_DEFAULT,
msg_id_panel => C_VVC_MSG_ID_PANEL_DEFAULT
);
type t_vvc_status is
record
current_cmd_idx : natural;
previous_cmd_idx : natural;
pending_cmd_cnt : natural;
end record;
type t_vvc_status_array is array (t_channel range <>, natural range <>) of t_vvc_status;
constant C_VVC_STATUS_DEFAULT : t_vvc_status := (
current_cmd_idx => 0,
previous_cmd_idx => 0,
pending_cmd_cnt => 0
);
-- Transaction information to include in the wave view during simulation
type t_transaction_info is
record
operation : t_operation;
data : std_logic_vector(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0);
msg : string(1 to C_VVC_CMD_STRING_MAX_LENGTH);
end record;
type t_transaction_info_array is array (t_channel range <>, natural range <>) of t_transaction_info;
constant C_TRANSACTION_INFO_DEFAULT : t_transaction_info := (
operation => NO_OPERATION,
data => (others => '0'),
msg => (others => ' ')
);
shared variable shared_uart_vvc_config : t_vvc_config_array(t_channel'left to t_channel'right, 0 to C_MAX_VVC_INSTANCE_NUM) := (others => (others => C_UART_VVC_CONFIG_DEFAULT));
shared variable shared_uart_vvc_status : t_vvc_status_array(t_channel'left to t_channel'right, 0 to C_MAX_VVC_INSTANCE_NUM) := (others => (others => C_VVC_STATUS_DEFAULT));
shared variable shared_uart_transaction_info : t_transaction_info_array(t_channel'left to t_channel'right, 0 to C_MAX_VVC_INSTANCE_NUM) := (others => (others => C_TRANSACTION_INFO_DEFAULT));
--==============================================================================
-- Methods dedicated to this VVC
-- - These procedures are called from the testbench in order to queue BFM calls
-- in the VVC command queue. The VVC will store and forward these calls to the
-- UART BFM when the command is at the from of the VVC command queue.
-- - For details on how the BFM procedures work, see uart_bfm_pkg.vhd.
--==============================================================================
procedure uart_transmit(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant channel : in t_channel;
constant data : in std_logic_vector;
constant msg : in string
);
procedure uart_receive(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant channel : in t_channel;
constant msg : in string;
constant alert_level : in t_alert_level := ERROR
);
procedure uart_expect(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant channel : in t_channel;
constant data : in std_logic_vector;
constant msg : in string;
constant max_receptions : in natural := 1;
constant timeout : in time := -1 ns;
constant alert_level : in t_alert_level := ERROR
);
end package vvc_methods_pkg;
package body vvc_methods_pkg is
procedure uart_transmit(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant channel : in t_channel;
constant data : in std_logic_vector;
constant msg : in string
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx, channel) -- First part common for all
& ", " & to_string(data, HEX, AS_IS, INCL_RADIX) & ")";
variable v_normalised_data : std_logic_vector(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0) :=
normalize_and_check(data, shared_vvc_cmd.data, ALLOW_WIDER_NARROWER, "data", "shared_vvc_cmd.data", proc_call & " called with to wide data. " & add_msg_delimiter(msg));
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, channel, proc_call, msg, QUEUED, TRANSMIT);
shared_vvc_cmd.operation := TRANSMIT;
shared_vvc_cmd.data := v_normalised_data;
send_command_to_vvc(VVCT);
end procedure;
procedure uart_receive(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant channel : in t_channel;
constant msg : in string;
constant alert_level : in t_alert_level := ERROR
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx, channel) -- First part common for all
& ")";
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, channel, proc_call, msg, QUEUED, RECEIVE);
shared_vvc_cmd.operation := RECEIVE;
shared_vvc_cmd.alert_level := alert_level;
send_command_to_vvc(VVCT);
end procedure;
procedure uart_expect(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant channel : in t_channel;
constant data : in std_logic_vector;
constant msg : in string;
constant max_receptions : in natural := 1;
constant timeout : in time := -1 ns;
constant alert_level : in t_alert_level := ERROR
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx, channel) -- First part common for all
& ", " & to_string(data, HEX, AS_IS, INCL_RADIX) & ")";
variable v_normalised_data : std_logic_vector(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0) :=
normalize_and_check(data, shared_vvc_cmd.data, ALLOW_WIDER_NARROWER, "data", "shared_vvc_cmd.data", proc_call & " called with to wide data. " & add_msg_delimiter(msg));
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, channel, proc_call, msg, QUEUED, EXPECT);
shared_vvc_cmd.operation := EXPECT;
shared_vvc_cmd.data := v_normalised_data;
shared_vvc_cmd.alert_level := alert_level;
shared_vvc_cmd.max_receptions := max_receptions;
if timeout = -1 ns then
shared_vvc_cmd.timeout := shared_uart_vvc_config(RX,vvc_instance_idx).bfm_config.timeout;
else
shared_vvc_cmd.timeout := timeout;
end if;
send_command_to_vvc(VVCT);
end procedure;
end package body vvc_methods_pkg;
|
mit
|
UVVM/uvvm_vvc_framework
|
bitvis_vip_clock_generator/src/vvc_cmd_pkg.vhd
|
2
|
6168
|
--========================================================================================================================
-- This VVC was generated with Bitvis VVC Generator
--========================================================================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
--========================================================================================================================
--========================================================================================================================
package vvc_cmd_pkg is
--========================================================================================================================
-- t_operation
-- - VVC and BFM operations
--========================================================================================================================
type t_operation is (
NO_OPERATION,
AWAIT_COMPLETION,
AWAIT_ANY_COMPLETION,
ENABLE_LOG_MSG,
DISABLE_LOG_MSG,
FLUSH_COMMAND_QUEUE,
FETCH_RESULT,
INSERT_DELAY,
TERMINATE_CURRENT_COMMAND,
START_CLOCK,
STOP_CLOCK,
SET_CLOCK_PERIOD,
SET_CLOCK_HIGH_TIME
);
--<USER_INPUT> Create constants for the maximum sizes to use in this VVC.
-- You can create VVCs with smaller sizes than these constants, but not larger.
-- For example, given a VVC with parallel data bus and address bus, constraints should be added for maximum data length
-- and address length
-- Example:
constant C_VVC_CMD_DATA_MAX_LENGTH : natural := 8;
constant C_VVC_CMD_STRING_MAX_LENGTH : natural := 300;
--========================================================================================================================
-- t_vvc_cmd_record
-- - Record type used for communication with the VVC
--========================================================================================================================
type t_vvc_cmd_record is record
-- Common VVC fields
operation : t_operation;
proc_call : string(1 to C_VVC_CMD_STRING_MAX_LENGTH);
msg : string(1 to C_VVC_CMD_STRING_MAX_LENGTH);
cmd_idx : natural;
command_type : t_immediate_or_queued;
msg_id : t_msg_id;
gen_integer_array : t_integer_array(0 to 1); -- Increase array length if needed
gen_boolean : boolean; -- Generic boolean
timeout : time;
alert_level : t_alert_level;
delay : time;
quietness : t_quietness;
-- VVC dedicated fields
clock_period : time;
clock_high_time : time;
end record;
constant C_VVC_CMD_DEFAULT : t_vvc_cmd_record := (
-- Common VVC fields
operation => NO_OPERATION,
proc_call => (others => NUL),
msg => (others => NUL),
cmd_idx => 0,
command_type => NO_COMMAND_TYPE,
msg_id => NO_ID,
gen_integer_array => (others => -1),
gen_boolean => false,
timeout => 0 ns,
alert_level => FAILURE,
delay => 0 ns,
quietness => NON_QUIET,
-- VVC dedicated fields
clock_period => 10 ns,
clock_high_time => 5 ns
);
--========================================================================================================================
-- shared_vvc_cmd
-- - Shared variable used for transmitting VVC commands
--========================================================================================================================
shared variable shared_vvc_cmd : t_vvc_cmd_record := C_VVC_CMD_DEFAULT;
--========================================================================================================================
-- t_vvc_result, t_vvc_result_queue_element, t_vvc_response and shared_vvc_response :
--
-- - Used for storing the result of a BFM procedure called by the VVC,
-- so that the result can be transported from the VVC to for example a sequencer via
-- fetch_result() as described in VVC_Framework_common_methods_QuickRef
--
-- - t_vvc_result includes the return value of the procedure in the BFM.
-- It can also be defined as a record if multiple values shall be transported from the BFM
--========================================================================================================================
subtype t_vvc_result is std_logic_vector(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0);
type t_vvc_result_queue_element is record
cmd_idx : natural; -- from UVVM handshake mechanism
result : t_vvc_result;
end record;
type t_vvc_response is record
fetch_is_accepted : boolean;
transaction_result : t_transaction_result;
result : t_vvc_result;
end record;
shared variable shared_vvc_response : t_vvc_response;
--========================================================================================================================
-- t_last_received_cmd_idx :
-- - Used to store the last queued cmd in vvc interpreter.
--========================================================================================================================
type t_last_received_cmd_idx is array (t_channel range <>,natural range <>) of integer;
--========================================================================================================================
-- shared_vvc_last_received_cmd_idx
-- - Shared variable used to get last queued index from vvc to sequencer
--========================================================================================================================
shared variable shared_vvc_last_received_cmd_idx : t_last_received_cmd_idx(t_channel'left to t_channel'right, 0 to C_MAX_VVC_INSTANCE_NUM) := (others => (others => -1));
end package vvc_cmd_pkg;
package body vvc_cmd_pkg is
end package body vvc_cmd_pkg;
|
mit
|
Digilent/vivado-library
|
ip/usb2device_v1_0/src/ResetBridge.vhd
|
29
|
3734
|
-------------------------------------------------------------------------------
--
-- File: SyncAsyncReset.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 20 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module is a reset-bridge. It takes a reset signal asynchronous to the
-- target clock domain (OutClk) and provides a safe asynchronous or synchronous
-- reset for the OutClk domain (oRst). The signal oRst is asserted immediately
-- as aRst arrives, but is de-asserted synchronously with the OutClk rising
-- edge. This means it can be used to safely reset any FF in the OutClk domain,
-- respecting recovery time specs for FFs.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ResetBridge is
Generic (
kPolarity : std_logic := '1');
Port (
aRst : in STD_LOGIC; -- asynchronous reset; active-high, if kPolarity=1
OutClk : in STD_LOGIC;
oRst : out STD_LOGIC);
end ResetBridge;
architecture Behavioral of ResetBridge is
signal aRst_int : std_logic;
attribute KEEP : string;
attribute KEEP of aRst_int: signal is "TRUE";
begin
aRst_int <= kPolarity xnor aRst; --SyncAsync uses active-high reset
SyncAsyncx: entity work.SyncAsync
generic map (
kResetTo => kPolarity,
kStages => 2) --use double FF synchronizer
port map (
aReset => aRst_int,
aIn => not kPolarity,
OutClk => OutClk,
oOut => oRst);
end Behavioral;
|
mit
|
Digilent/vivado-library
|
ip/dvi2rgb/src/SyncAsyncReset.vhd
|
29
|
3734
|
-------------------------------------------------------------------------------
--
-- File: SyncAsyncReset.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 20 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module is a reset-bridge. It takes a reset signal asynchronous to the
-- target clock domain (OutClk) and provides a safe asynchronous or synchronous
-- reset for the OutClk domain (oRst). The signal oRst is asserted immediately
-- as aRst arrives, but is de-asserted synchronously with the OutClk rising
-- edge. This means it can be used to safely reset any FF in the OutClk domain,
-- respecting recovery time specs for FFs.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ResetBridge is
Generic (
kPolarity : std_logic := '1');
Port (
aRst : in STD_LOGIC; -- asynchronous reset; active-high, if kPolarity=1
OutClk : in STD_LOGIC;
oRst : out STD_LOGIC);
end ResetBridge;
architecture Behavioral of ResetBridge is
signal aRst_int : std_logic;
attribute KEEP : string;
attribute KEEP of aRst_int: signal is "TRUE";
begin
aRst_int <= kPolarity xnor aRst; --SyncAsync uses active-high reset
SyncAsyncx: entity work.SyncAsync
generic map (
kResetTo => kPolarity,
kStages => 2) --use double FF synchronizer
port map (
aReset => aRst_int,
aIn => not kPolarity,
OutClk => OutClk,
oOut => oRst);
end Behavioral;
|
mit
|
Digilent/vivado-library
|
ip/hls_contrast_stretch_1_0/hdl/vhdl/Loop_loop_height_pro.vhd
|
1
|
87115
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Loop_loop_height_pro is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
max_dout : IN STD_LOGIC_VECTOR (7 downto 0);
max_empty_n : IN STD_LOGIC;
max_read : OUT STD_LOGIC;
p_rows_assign_cast_loc_dout : IN STD_LOGIC_VECTOR (11 downto 0);
p_rows_assign_cast_loc_empty_n : IN STD_LOGIC;
p_rows_assign_cast_loc_read : OUT STD_LOGIC;
p_cols_assign_cast_loc_dout : IN STD_LOGIC_VECTOR (11 downto 0);
p_cols_assign_cast_loc_empty_n : IN STD_LOGIC;
p_cols_assign_cast_loc_read : OUT STD_LOGIC;
img2_data_stream_0_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
img2_data_stream_0_V_full_n : IN STD_LOGIC;
img2_data_stream_0_V_write : OUT STD_LOGIC;
img2_data_stream_1_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
img2_data_stream_1_V_full_n : IN STD_LOGIC;
img2_data_stream_1_V_write : OUT STD_LOGIC;
img2_data_stream_2_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
img2_data_stream_2_V_full_n : IN STD_LOGIC;
img2_data_stream_2_V_write : OUT STD_LOGIC;
img1_data_stream_0_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
img1_data_stream_0_V_empty_n : IN STD_LOGIC;
img1_data_stream_0_V_read : OUT STD_LOGIC;
img1_data_stream_1_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
img1_data_stream_1_V_empty_n : IN STD_LOGIC;
img1_data_stream_1_V_read : OUT STD_LOGIC;
img1_data_stream_2_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
img1_data_stream_2_V_empty_n : IN STD_LOGIC;
img1_data_stream_2_V_read : OUT STD_LOGIC;
min_dout : IN STD_LOGIC_VECTOR (7 downto 0);
min_empty_n : IN STD_LOGIC;
min_read : OUT STD_LOGIC;
tmp_3_cast_loc_dout : IN STD_LOGIC_VECTOR (7 downto 0);
tmp_3_cast_loc_empty_n : IN STD_LOGIC;
tmp_3_cast_loc_read : OUT STD_LOGIC );
end;
architecture behav of Loop_loop_height_pro is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (3 downto 0) := "0001";
constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (3 downto 0) := "0010";
constant ap_ST_fsm_pp0_stage0 : STD_LOGIC_VECTOR (3 downto 0) := "0100";
constant ap_ST_fsm_state28 : STD_LOGIC_VECTOR (3 downto 0) := "1000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_boolean_1 : BOOLEAN := true;
constant ap_const_boolean_0 : BOOLEAN := false;
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv11_0 : STD_LOGIC_VECTOR (10 downto 0) := "00000000000";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv8_FF : STD_LOGIC_VECTOR (7 downto 0) := "11111111";
constant ap_const_lv8_0 : STD_LOGIC_VECTOR (7 downto 0) := "00000000";
constant ap_const_lv11_1 : STD_LOGIC_VECTOR (10 downto 0) := "00000000001";
signal ap_done_reg : STD_LOGIC := '0';
signal ap_CS_fsm : STD_LOGIC_VECTOR (3 downto 0) := "0001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_CS_fsm_state1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
signal max_blk_n : STD_LOGIC;
signal p_rows_assign_cast_loc_blk_n : STD_LOGIC;
signal p_cols_assign_cast_loc_blk_n : STD_LOGIC;
signal img2_data_stream_0_V_blk_n : STD_LOGIC;
signal ap_enable_reg_pp0_iter24 : STD_LOGIC := '0';
signal ap_block_pp0_stage0 : BOOLEAN;
signal exitcond_i_i_i_reg_318 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter23_exitcond_i_i_i_reg_318 : STD_LOGIC_VECTOR (0 downto 0);
signal img2_data_stream_1_V_blk_n : STD_LOGIC;
signal img2_data_stream_2_V_blk_n : STD_LOGIC;
signal img1_data_stream_0_V_blk_n : STD_LOGIC;
signal ap_CS_fsm_pp0_stage0 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage0 : signal is "none";
signal ap_enable_reg_pp0_iter1 : STD_LOGIC := '0';
signal img1_data_stream_1_V_blk_n : STD_LOGIC;
signal img1_data_stream_2_V_blk_n : STD_LOGIC;
signal min_blk_n : STD_LOGIC;
signal tmp_3_cast_loc_blk_n : STD_LOGIC;
signal t_V_2_reg_162 : STD_LOGIC_VECTOR (10 downto 0);
signal max_read_reg_279 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_block_state1 : BOOLEAN;
signal min_read_reg_284 : STD_LOGIC_VECTOR (7 downto 0);
signal p_rows_assign_cast_lo_reg_289 : STD_LOGIC_VECTOR (11 downto 0);
signal p_cols_assign_cast_lo_reg_294 : STD_LOGIC_VECTOR (11 downto 0);
signal extLd_fu_189_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal extLd_reg_299 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_8_tr_cast_i_i_ca_fu_203_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_8_tr_cast_i_i_ca_reg_304 : STD_LOGIC_VECTOR (16 downto 0);
signal exitcond51_i_i_i_fu_211_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_state2 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state2 : signal is "none";
signal i_V_fu_216_p2 : STD_LOGIC_VECTOR (10 downto 0);
signal i_V_reg_313 : STD_LOGIC_VECTOR (10 downto 0);
signal exitcond_i_i_i_fu_226_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_block_state3_pp0_stage0_iter0 : BOOLEAN;
signal ap_block_state4_pp0_stage0_iter1 : BOOLEAN;
signal ap_block_state5_pp0_stage0_iter2 : BOOLEAN;
signal ap_block_state6_pp0_stage0_iter3 : BOOLEAN;
signal ap_block_state7_pp0_stage0_iter4 : BOOLEAN;
signal ap_block_state8_pp0_stage0_iter5 : BOOLEAN;
signal ap_block_state9_pp0_stage0_iter6 : BOOLEAN;
signal ap_block_state10_pp0_stage0_iter7 : BOOLEAN;
signal ap_block_state11_pp0_stage0_iter8 : BOOLEAN;
signal ap_block_state12_pp0_stage0_iter9 : BOOLEAN;
signal ap_block_state13_pp0_stage0_iter10 : BOOLEAN;
signal ap_block_state14_pp0_stage0_iter11 : BOOLEAN;
signal ap_block_state15_pp0_stage0_iter12 : BOOLEAN;
signal ap_block_state16_pp0_stage0_iter13 : BOOLEAN;
signal ap_block_state17_pp0_stage0_iter14 : BOOLEAN;
signal ap_block_state18_pp0_stage0_iter15 : BOOLEAN;
signal ap_block_state19_pp0_stage0_iter16 : BOOLEAN;
signal ap_block_state20_pp0_stage0_iter17 : BOOLEAN;
signal ap_block_state21_pp0_stage0_iter18 : BOOLEAN;
signal ap_block_state22_pp0_stage0_iter19 : BOOLEAN;
signal ap_block_state23_pp0_stage0_iter20 : BOOLEAN;
signal ap_block_state24_pp0_stage0_iter21 : BOOLEAN;
signal ap_block_state25_pp0_stage0_iter22 : BOOLEAN;
signal ap_block_state26_pp0_stage0_iter23 : BOOLEAN;
signal ap_block_state27_pp0_stage0_iter24 : BOOLEAN;
signal ap_block_pp0_stage0_11001 : BOOLEAN;
signal ap_reg_pp0_iter1_exitcond_i_i_i_reg_318 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter2_exitcond_i_i_i_reg_318 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter3_exitcond_i_i_i_reg_318 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter4_exitcond_i_i_i_reg_318 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter5_exitcond_i_i_i_reg_318 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter6_exitcond_i_i_i_reg_318 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter7_exitcond_i_i_i_reg_318 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter8_exitcond_i_i_i_reg_318 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter9_exitcond_i_i_i_reg_318 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter10_exitcond_i_i_i_reg_318 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter11_exitcond_i_i_i_reg_318 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter12_exitcond_i_i_i_reg_318 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter13_exitcond_i_i_i_reg_318 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter14_exitcond_i_i_i_reg_318 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter15_exitcond_i_i_i_reg_318 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter16_exitcond_i_i_i_reg_318 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter17_exitcond_i_i_i_reg_318 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter18_exitcond_i_i_i_reg_318 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter19_exitcond_i_i_i_reg_318 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter20_exitcond_i_i_i_reg_318 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter21_exitcond_i_i_i_reg_318 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter22_exitcond_i_i_i_reg_318 : STD_LOGIC_VECTOR (0 downto 0);
signal j_V_fu_231_p2 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_enable_reg_pp0_iter0 : STD_LOGIC := '0';
signal tmp_9_reg_327 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_8_reg_334 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter2_tmp_8_reg_334 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter3_tmp_8_reg_334 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter4_tmp_8_reg_334 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter5_tmp_8_reg_334 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter6_tmp_8_reg_334 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter7_tmp_8_reg_334 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter8_tmp_8_reg_334 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter9_tmp_8_reg_334 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter10_tmp_8_reg_334 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter11_tmp_8_reg_334 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter12_tmp_8_reg_334 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter13_tmp_8_reg_334 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter14_tmp_8_reg_334 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter15_tmp_8_reg_334 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter16_tmp_8_reg_334 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter17_tmp_8_reg_334 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter18_tmp_8_reg_334 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter19_tmp_8_reg_334 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter20_tmp_8_reg_334 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter21_tmp_8_reg_334 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter22_tmp_8_reg_334 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter23_tmp_8_reg_334 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_reg_339 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter2_tmp_reg_339 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter3_tmp_reg_339 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter4_tmp_reg_339 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter5_tmp_reg_339 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter6_tmp_reg_339 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter7_tmp_reg_339 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter8_tmp_reg_339 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter9_tmp_reg_339 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter10_tmp_reg_339 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter11_tmp_reg_339 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter12_tmp_reg_339 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter13_tmp_reg_339 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter14_tmp_reg_339 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter15_tmp_reg_339 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter16_tmp_reg_339 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter17_tmp_reg_339 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter18_tmp_reg_339 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter19_tmp_reg_339 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter20_tmp_reg_339 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter21_tmp_reg_339 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter22_tmp_reg_339 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter23_tmp_reg_339 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_1_i_i_fu_237_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_1_i_i_reg_344 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter3_tmp_1_i_i_reg_344 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter4_tmp_1_i_i_reg_344 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter5_tmp_1_i_i_reg_344 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter6_tmp_1_i_i_reg_344 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter7_tmp_1_i_i_reg_344 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter8_tmp_1_i_i_reg_344 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter9_tmp_1_i_i_reg_344 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter10_tmp_1_i_i_reg_344 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter11_tmp_1_i_i_reg_344 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter12_tmp_1_i_i_reg_344 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter13_tmp_1_i_i_reg_344 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter14_tmp_1_i_i_reg_344 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter15_tmp_1_i_i_reg_344 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter16_tmp_1_i_i_reg_344 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter17_tmp_1_i_i_reg_344 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter18_tmp_1_i_i_reg_344 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter19_tmp_1_i_i_reg_344 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter20_tmp_1_i_i_reg_344 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter21_tmp_1_i_i_reg_344 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter22_tmp_1_i_i_reg_344 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_i_i_fu_241_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_i_i_reg_348 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter3_tmp_i_i_reg_348 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter4_tmp_i_i_reg_348 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter5_tmp_i_i_reg_348 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter6_tmp_i_i_reg_348 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter7_tmp_i_i_reg_348 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter8_tmp_i_i_reg_348 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter9_tmp_i_i_reg_348 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter10_tmp_i_i_reg_348 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter11_tmp_i_i_reg_348 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter12_tmp_i_i_reg_348 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter13_tmp_i_i_reg_348 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter14_tmp_i_i_reg_348 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter15_tmp_i_i_reg_348 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter16_tmp_i_i_reg_348 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter17_tmp_i_i_reg_348 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter18_tmp_i_i_reg_348 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter19_tmp_i_i_reg_348 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter20_tmp_i_i_reg_348 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter21_tmp_i_i_reg_348 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter22_tmp_i_i_reg_348 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_10_i_i_fu_265_p2 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_10_i_i_reg_352 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_7_fu_275_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_block_pp0_stage0_subdone : BOOLEAN;
signal ap_condition_pp0_exit_iter0_state3 : STD_LOGIC;
signal ap_enable_reg_pp0_iter2 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter3 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter4 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter5 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter6 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter7 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter8 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter9 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter10 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter11 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter12 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter13 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter14 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter15 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter16 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter17 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter18 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter19 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter20 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter21 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter22 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter23 : STD_LOGIC := '0';
signal t_V_reg_151 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_CS_fsm_state28 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state28 : signal is "none";
signal ap_phi_reg_pp0_iter0_tmp_2_reg_173 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_phi_reg_pp0_iter1_tmp_2_reg_173 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_phi_reg_pp0_iter2_tmp_2_reg_173 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_phi_reg_pp0_iter3_tmp_2_reg_173 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_phi_reg_pp0_iter4_tmp_2_reg_173 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_phi_reg_pp0_iter5_tmp_2_reg_173 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_phi_reg_pp0_iter6_tmp_2_reg_173 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_phi_reg_pp0_iter7_tmp_2_reg_173 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_phi_reg_pp0_iter8_tmp_2_reg_173 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_phi_reg_pp0_iter9_tmp_2_reg_173 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_phi_reg_pp0_iter10_tmp_2_reg_173 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_phi_reg_pp0_iter11_tmp_2_reg_173 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_phi_reg_pp0_iter12_tmp_2_reg_173 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_phi_reg_pp0_iter13_tmp_2_reg_173 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_phi_reg_pp0_iter14_tmp_2_reg_173 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_phi_reg_pp0_iter15_tmp_2_reg_173 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_phi_reg_pp0_iter16_tmp_2_reg_173 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_phi_reg_pp0_iter17_tmp_2_reg_173 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_phi_reg_pp0_iter18_tmp_2_reg_173 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_phi_reg_pp0_iter19_tmp_2_reg_173 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_phi_reg_pp0_iter20_tmp_2_reg_173 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_phi_reg_pp0_iter21_tmp_2_reg_173 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_phi_reg_pp0_iter22_tmp_2_reg_173 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_phi_reg_pp0_iter23_tmp_2_reg_173 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_phi_reg_pp0_iter24_tmp_2_reg_173 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_block_pp0_stage0_01001 : BOOLEAN;
signal tmp_cast_i_i_fu_193_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_8_tr_i_i_fu_197_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal t_V_cast_i_i_fu_207_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal t_V_1_cast_i_i_fu_222_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal tmp_8_cast_i_i_fu_245_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_9_i_i_fu_248_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal p_shl_i_i_fu_257_p3 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_9_cast_i_i_fu_253_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal grp_fu_271_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal grp_fu_271_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_271_ce : STD_LOGIC;
signal ap_NS_fsm : STD_LOGIC_VECTOR (3 downto 0);
signal ap_idle_pp0 : STD_LOGIC;
signal ap_enable_pp0 : STD_LOGIC;
signal ap_condition_362 : BOOLEAN;
signal ap_condition_490 : BOOLEAN;
component hls_contrast_strefYi IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (16 downto 0);
din1 : IN STD_LOGIC_VECTOR (8 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (7 downto 0) );
end component;
begin
hls_contrast_strefYi_U47 : component hls_contrast_strefYi
generic map (
ID => 1,
NUM_STAGE => 21,
din0_WIDTH => 17,
din1_WIDTH => 9,
dout_WIDTH => 8)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => tmp_10_i_i_reg_352,
din1 => grp_fu_271_p1,
ce => grp_fu_271_ce,
dout => grp_fu_271_p2);
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_fsm_state1;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
ap_done_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_done_reg <= ap_const_logic_0;
else
if ((ap_continue = ap_const_logic_1)) then
ap_done_reg <= ap_const_logic_0;
elsif (((ap_const_logic_1 = ap_CS_fsm_state2) and (exitcond51_i_i_i_fu_211_p2 = ap_const_lv1_1))) then
ap_done_reg <= ap_const_logic_1;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter0_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
else
if (((ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_condition_pp0_exit_iter0_state3))) then
ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
elsif (((exitcond51_i_i_i_fu_211_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state2))) then
ap_enable_reg_pp0_iter0 <= ap_const_logic_1;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter1 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
if ((ap_const_logic_1 = ap_condition_pp0_exit_iter0_state3)) then
ap_enable_reg_pp0_iter1 <= (ap_const_logic_1 xor ap_condition_pp0_exit_iter0_state3);
elsif ((ap_const_boolean_1 = ap_const_boolean_1)) then
ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0;
end if;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter10_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter10 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter10 <= ap_enable_reg_pp0_iter9;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter11_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter11 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter11 <= ap_enable_reg_pp0_iter10;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter12_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter12 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter12 <= ap_enable_reg_pp0_iter11;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter13_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter13 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter13 <= ap_enable_reg_pp0_iter12;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter14_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter14 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter14 <= ap_enable_reg_pp0_iter13;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter15_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter15 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter15 <= ap_enable_reg_pp0_iter14;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter16_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter16 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter16 <= ap_enable_reg_pp0_iter15;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter17_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter17 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter17 <= ap_enable_reg_pp0_iter16;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter18_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter18 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter18 <= ap_enable_reg_pp0_iter17;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter19_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter19 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter19 <= ap_enable_reg_pp0_iter18;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter2_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter2 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter20_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter20 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter20 <= ap_enable_reg_pp0_iter19;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter21_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter21 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter21 <= ap_enable_reg_pp0_iter20;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter22_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter22 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter22 <= ap_enable_reg_pp0_iter21;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter23_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter23 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter23 <= ap_enable_reg_pp0_iter22;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter24_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter24 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter24 <= ap_enable_reg_pp0_iter23;
elsif (((exitcond51_i_i_i_fu_211_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state2))) then
ap_enable_reg_pp0_iter24 <= ap_const_logic_0;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter3_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter3 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter4_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter4 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter5_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter5 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter5 <= ap_enable_reg_pp0_iter4;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter6_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter6 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter6 <= ap_enable_reg_pp0_iter5;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter7_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter7 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter7 <= ap_enable_reg_pp0_iter6;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter8_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter8 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter8 <= ap_enable_reg_pp0_iter7;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter9_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter9 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter9 <= ap_enable_reg_pp0_iter8;
end if;
end if;
end if;
end process;
ap_phi_reg_pp0_iter24_tmp_2_reg_173_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_enable_reg_pp0_iter23 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
if ((ap_const_boolean_1 = ap_condition_362)) then
ap_phi_reg_pp0_iter24_tmp_2_reg_173 <= tmp_7_fu_275_p1;
elsif ((ap_const_boolean_1 = ap_const_boolean_1)) then
ap_phi_reg_pp0_iter24_tmp_2_reg_173 <= ap_phi_reg_pp0_iter23_tmp_2_reg_173;
end if;
end if;
end if;
end process;
ap_phi_reg_pp0_iter3_tmp_2_reg_173_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_enable_reg_pp0_iter2 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
if ((ap_const_boolean_1 = ap_condition_490)) then
ap_phi_reg_pp0_iter3_tmp_2_reg_173 <= ap_const_lv8_0;
elsif (((ap_reg_pp0_iter1_exitcond_i_i_i_reg_318 = ap_const_lv1_0) and (tmp_1_i_i_fu_237_p2 = ap_const_lv1_1))) then
ap_phi_reg_pp0_iter3_tmp_2_reg_173 <= ap_const_lv8_FF;
elsif ((ap_const_boolean_1 = ap_const_boolean_1)) then
ap_phi_reg_pp0_iter3_tmp_2_reg_173 <= ap_phi_reg_pp0_iter2_tmp_2_reg_173;
end if;
end if;
end if;
end process;
t_V_2_reg_162_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((exitcond_i_i_i_fu_226_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
t_V_2_reg_162 <= j_V_fu_231_p2;
elsif (((exitcond51_i_i_i_fu_211_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state2))) then
t_V_2_reg_162 <= ap_const_lv11_0;
end if;
end if;
end process;
t_V_reg_151_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state28)) then
t_V_reg_151 <= i_V_reg_313;
elsif ((not(((ap_start = ap_const_logic_0) or (tmp_3_cast_loc_empty_n = ap_const_logic_0) or (min_empty_n = ap_const_logic_0) or (p_cols_assign_cast_loc_empty_n = ap_const_logic_0) or (p_rows_assign_cast_loc_empty_n = ap_const_logic_0) or (max_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
t_V_reg_151 <= ap_const_lv11_0;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_enable_reg_pp0_iter9 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
ap_phi_reg_pp0_iter10_tmp_2_reg_173 <= ap_phi_reg_pp0_iter9_tmp_2_reg_173;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_enable_reg_pp0_iter10 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
ap_phi_reg_pp0_iter11_tmp_2_reg_173 <= ap_phi_reg_pp0_iter10_tmp_2_reg_173;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_enable_reg_pp0_iter11 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
ap_phi_reg_pp0_iter12_tmp_2_reg_173 <= ap_phi_reg_pp0_iter11_tmp_2_reg_173;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_enable_reg_pp0_iter12 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
ap_phi_reg_pp0_iter13_tmp_2_reg_173 <= ap_phi_reg_pp0_iter12_tmp_2_reg_173;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_enable_reg_pp0_iter13 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
ap_phi_reg_pp0_iter14_tmp_2_reg_173 <= ap_phi_reg_pp0_iter13_tmp_2_reg_173;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_enable_reg_pp0_iter14 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
ap_phi_reg_pp0_iter15_tmp_2_reg_173 <= ap_phi_reg_pp0_iter14_tmp_2_reg_173;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_enable_reg_pp0_iter15 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
ap_phi_reg_pp0_iter16_tmp_2_reg_173 <= ap_phi_reg_pp0_iter15_tmp_2_reg_173;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_enable_reg_pp0_iter16 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
ap_phi_reg_pp0_iter17_tmp_2_reg_173 <= ap_phi_reg_pp0_iter16_tmp_2_reg_173;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_enable_reg_pp0_iter17 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
ap_phi_reg_pp0_iter18_tmp_2_reg_173 <= ap_phi_reg_pp0_iter17_tmp_2_reg_173;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_enable_reg_pp0_iter18 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
ap_phi_reg_pp0_iter19_tmp_2_reg_173 <= ap_phi_reg_pp0_iter18_tmp_2_reg_173;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
ap_phi_reg_pp0_iter1_tmp_2_reg_173 <= ap_phi_reg_pp0_iter0_tmp_2_reg_173;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_enable_reg_pp0_iter19 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
ap_phi_reg_pp0_iter20_tmp_2_reg_173 <= ap_phi_reg_pp0_iter19_tmp_2_reg_173;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_enable_reg_pp0_iter20 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
ap_phi_reg_pp0_iter21_tmp_2_reg_173 <= ap_phi_reg_pp0_iter20_tmp_2_reg_173;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_enable_reg_pp0_iter21 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
ap_phi_reg_pp0_iter22_tmp_2_reg_173 <= ap_phi_reg_pp0_iter21_tmp_2_reg_173;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_enable_reg_pp0_iter22 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
ap_phi_reg_pp0_iter23_tmp_2_reg_173 <= ap_phi_reg_pp0_iter22_tmp_2_reg_173;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
ap_phi_reg_pp0_iter2_tmp_2_reg_173 <= ap_phi_reg_pp0_iter1_tmp_2_reg_173;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_enable_reg_pp0_iter3 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
ap_phi_reg_pp0_iter4_tmp_2_reg_173 <= ap_phi_reg_pp0_iter3_tmp_2_reg_173;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_enable_reg_pp0_iter4 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
ap_phi_reg_pp0_iter5_tmp_2_reg_173 <= ap_phi_reg_pp0_iter4_tmp_2_reg_173;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_enable_reg_pp0_iter5 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
ap_phi_reg_pp0_iter6_tmp_2_reg_173 <= ap_phi_reg_pp0_iter5_tmp_2_reg_173;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_enable_reg_pp0_iter6 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
ap_phi_reg_pp0_iter7_tmp_2_reg_173 <= ap_phi_reg_pp0_iter6_tmp_2_reg_173;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_enable_reg_pp0_iter7 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
ap_phi_reg_pp0_iter8_tmp_2_reg_173 <= ap_phi_reg_pp0_iter7_tmp_2_reg_173;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_enable_reg_pp0_iter8 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
ap_phi_reg_pp0_iter9_tmp_2_reg_173 <= ap_phi_reg_pp0_iter8_tmp_2_reg_173;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_boolean_0 = ap_block_pp0_stage0_11001)) then
ap_reg_pp0_iter10_exitcond_i_i_i_reg_318 <= ap_reg_pp0_iter9_exitcond_i_i_i_reg_318;
ap_reg_pp0_iter10_tmp_1_i_i_reg_344 <= ap_reg_pp0_iter9_tmp_1_i_i_reg_344;
ap_reg_pp0_iter10_tmp_8_reg_334 <= ap_reg_pp0_iter9_tmp_8_reg_334;
ap_reg_pp0_iter10_tmp_i_i_reg_348 <= ap_reg_pp0_iter9_tmp_i_i_reg_348;
ap_reg_pp0_iter10_tmp_reg_339 <= ap_reg_pp0_iter9_tmp_reg_339;
ap_reg_pp0_iter11_exitcond_i_i_i_reg_318 <= ap_reg_pp0_iter10_exitcond_i_i_i_reg_318;
ap_reg_pp0_iter11_tmp_1_i_i_reg_344 <= ap_reg_pp0_iter10_tmp_1_i_i_reg_344;
ap_reg_pp0_iter11_tmp_8_reg_334 <= ap_reg_pp0_iter10_tmp_8_reg_334;
ap_reg_pp0_iter11_tmp_i_i_reg_348 <= ap_reg_pp0_iter10_tmp_i_i_reg_348;
ap_reg_pp0_iter11_tmp_reg_339 <= ap_reg_pp0_iter10_tmp_reg_339;
ap_reg_pp0_iter12_exitcond_i_i_i_reg_318 <= ap_reg_pp0_iter11_exitcond_i_i_i_reg_318;
ap_reg_pp0_iter12_tmp_1_i_i_reg_344 <= ap_reg_pp0_iter11_tmp_1_i_i_reg_344;
ap_reg_pp0_iter12_tmp_8_reg_334 <= ap_reg_pp0_iter11_tmp_8_reg_334;
ap_reg_pp0_iter12_tmp_i_i_reg_348 <= ap_reg_pp0_iter11_tmp_i_i_reg_348;
ap_reg_pp0_iter12_tmp_reg_339 <= ap_reg_pp0_iter11_tmp_reg_339;
ap_reg_pp0_iter13_exitcond_i_i_i_reg_318 <= ap_reg_pp0_iter12_exitcond_i_i_i_reg_318;
ap_reg_pp0_iter13_tmp_1_i_i_reg_344 <= ap_reg_pp0_iter12_tmp_1_i_i_reg_344;
ap_reg_pp0_iter13_tmp_8_reg_334 <= ap_reg_pp0_iter12_tmp_8_reg_334;
ap_reg_pp0_iter13_tmp_i_i_reg_348 <= ap_reg_pp0_iter12_tmp_i_i_reg_348;
ap_reg_pp0_iter13_tmp_reg_339 <= ap_reg_pp0_iter12_tmp_reg_339;
ap_reg_pp0_iter14_exitcond_i_i_i_reg_318 <= ap_reg_pp0_iter13_exitcond_i_i_i_reg_318;
ap_reg_pp0_iter14_tmp_1_i_i_reg_344 <= ap_reg_pp0_iter13_tmp_1_i_i_reg_344;
ap_reg_pp0_iter14_tmp_8_reg_334 <= ap_reg_pp0_iter13_tmp_8_reg_334;
ap_reg_pp0_iter14_tmp_i_i_reg_348 <= ap_reg_pp0_iter13_tmp_i_i_reg_348;
ap_reg_pp0_iter14_tmp_reg_339 <= ap_reg_pp0_iter13_tmp_reg_339;
ap_reg_pp0_iter15_exitcond_i_i_i_reg_318 <= ap_reg_pp0_iter14_exitcond_i_i_i_reg_318;
ap_reg_pp0_iter15_tmp_1_i_i_reg_344 <= ap_reg_pp0_iter14_tmp_1_i_i_reg_344;
ap_reg_pp0_iter15_tmp_8_reg_334 <= ap_reg_pp0_iter14_tmp_8_reg_334;
ap_reg_pp0_iter15_tmp_i_i_reg_348 <= ap_reg_pp0_iter14_tmp_i_i_reg_348;
ap_reg_pp0_iter15_tmp_reg_339 <= ap_reg_pp0_iter14_tmp_reg_339;
ap_reg_pp0_iter16_exitcond_i_i_i_reg_318 <= ap_reg_pp0_iter15_exitcond_i_i_i_reg_318;
ap_reg_pp0_iter16_tmp_1_i_i_reg_344 <= ap_reg_pp0_iter15_tmp_1_i_i_reg_344;
ap_reg_pp0_iter16_tmp_8_reg_334 <= ap_reg_pp0_iter15_tmp_8_reg_334;
ap_reg_pp0_iter16_tmp_i_i_reg_348 <= ap_reg_pp0_iter15_tmp_i_i_reg_348;
ap_reg_pp0_iter16_tmp_reg_339 <= ap_reg_pp0_iter15_tmp_reg_339;
ap_reg_pp0_iter17_exitcond_i_i_i_reg_318 <= ap_reg_pp0_iter16_exitcond_i_i_i_reg_318;
ap_reg_pp0_iter17_tmp_1_i_i_reg_344 <= ap_reg_pp0_iter16_tmp_1_i_i_reg_344;
ap_reg_pp0_iter17_tmp_8_reg_334 <= ap_reg_pp0_iter16_tmp_8_reg_334;
ap_reg_pp0_iter17_tmp_i_i_reg_348 <= ap_reg_pp0_iter16_tmp_i_i_reg_348;
ap_reg_pp0_iter17_tmp_reg_339 <= ap_reg_pp0_iter16_tmp_reg_339;
ap_reg_pp0_iter18_exitcond_i_i_i_reg_318 <= ap_reg_pp0_iter17_exitcond_i_i_i_reg_318;
ap_reg_pp0_iter18_tmp_1_i_i_reg_344 <= ap_reg_pp0_iter17_tmp_1_i_i_reg_344;
ap_reg_pp0_iter18_tmp_8_reg_334 <= ap_reg_pp0_iter17_tmp_8_reg_334;
ap_reg_pp0_iter18_tmp_i_i_reg_348 <= ap_reg_pp0_iter17_tmp_i_i_reg_348;
ap_reg_pp0_iter18_tmp_reg_339 <= ap_reg_pp0_iter17_tmp_reg_339;
ap_reg_pp0_iter19_exitcond_i_i_i_reg_318 <= ap_reg_pp0_iter18_exitcond_i_i_i_reg_318;
ap_reg_pp0_iter19_tmp_1_i_i_reg_344 <= ap_reg_pp0_iter18_tmp_1_i_i_reg_344;
ap_reg_pp0_iter19_tmp_8_reg_334 <= ap_reg_pp0_iter18_tmp_8_reg_334;
ap_reg_pp0_iter19_tmp_i_i_reg_348 <= ap_reg_pp0_iter18_tmp_i_i_reg_348;
ap_reg_pp0_iter19_tmp_reg_339 <= ap_reg_pp0_iter18_tmp_reg_339;
ap_reg_pp0_iter20_exitcond_i_i_i_reg_318 <= ap_reg_pp0_iter19_exitcond_i_i_i_reg_318;
ap_reg_pp0_iter20_tmp_1_i_i_reg_344 <= ap_reg_pp0_iter19_tmp_1_i_i_reg_344;
ap_reg_pp0_iter20_tmp_8_reg_334 <= ap_reg_pp0_iter19_tmp_8_reg_334;
ap_reg_pp0_iter20_tmp_i_i_reg_348 <= ap_reg_pp0_iter19_tmp_i_i_reg_348;
ap_reg_pp0_iter20_tmp_reg_339 <= ap_reg_pp0_iter19_tmp_reg_339;
ap_reg_pp0_iter21_exitcond_i_i_i_reg_318 <= ap_reg_pp0_iter20_exitcond_i_i_i_reg_318;
ap_reg_pp0_iter21_tmp_1_i_i_reg_344 <= ap_reg_pp0_iter20_tmp_1_i_i_reg_344;
ap_reg_pp0_iter21_tmp_8_reg_334 <= ap_reg_pp0_iter20_tmp_8_reg_334;
ap_reg_pp0_iter21_tmp_i_i_reg_348 <= ap_reg_pp0_iter20_tmp_i_i_reg_348;
ap_reg_pp0_iter21_tmp_reg_339 <= ap_reg_pp0_iter20_tmp_reg_339;
ap_reg_pp0_iter22_exitcond_i_i_i_reg_318 <= ap_reg_pp0_iter21_exitcond_i_i_i_reg_318;
ap_reg_pp0_iter22_tmp_1_i_i_reg_344 <= ap_reg_pp0_iter21_tmp_1_i_i_reg_344;
ap_reg_pp0_iter22_tmp_8_reg_334 <= ap_reg_pp0_iter21_tmp_8_reg_334;
ap_reg_pp0_iter22_tmp_i_i_reg_348 <= ap_reg_pp0_iter21_tmp_i_i_reg_348;
ap_reg_pp0_iter22_tmp_reg_339 <= ap_reg_pp0_iter21_tmp_reg_339;
ap_reg_pp0_iter23_exitcond_i_i_i_reg_318 <= ap_reg_pp0_iter22_exitcond_i_i_i_reg_318;
ap_reg_pp0_iter23_tmp_8_reg_334 <= ap_reg_pp0_iter22_tmp_8_reg_334;
ap_reg_pp0_iter23_tmp_reg_339 <= ap_reg_pp0_iter22_tmp_reg_339;
ap_reg_pp0_iter2_exitcond_i_i_i_reg_318 <= ap_reg_pp0_iter1_exitcond_i_i_i_reg_318;
ap_reg_pp0_iter2_tmp_8_reg_334 <= tmp_8_reg_334;
ap_reg_pp0_iter2_tmp_reg_339 <= tmp_reg_339;
ap_reg_pp0_iter3_exitcond_i_i_i_reg_318 <= ap_reg_pp0_iter2_exitcond_i_i_i_reg_318;
ap_reg_pp0_iter3_tmp_1_i_i_reg_344 <= tmp_1_i_i_reg_344;
ap_reg_pp0_iter3_tmp_8_reg_334 <= ap_reg_pp0_iter2_tmp_8_reg_334;
ap_reg_pp0_iter3_tmp_i_i_reg_348 <= tmp_i_i_reg_348;
ap_reg_pp0_iter3_tmp_reg_339 <= ap_reg_pp0_iter2_tmp_reg_339;
ap_reg_pp0_iter4_exitcond_i_i_i_reg_318 <= ap_reg_pp0_iter3_exitcond_i_i_i_reg_318;
ap_reg_pp0_iter4_tmp_1_i_i_reg_344 <= ap_reg_pp0_iter3_tmp_1_i_i_reg_344;
ap_reg_pp0_iter4_tmp_8_reg_334 <= ap_reg_pp0_iter3_tmp_8_reg_334;
ap_reg_pp0_iter4_tmp_i_i_reg_348 <= ap_reg_pp0_iter3_tmp_i_i_reg_348;
ap_reg_pp0_iter4_tmp_reg_339 <= ap_reg_pp0_iter3_tmp_reg_339;
ap_reg_pp0_iter5_exitcond_i_i_i_reg_318 <= ap_reg_pp0_iter4_exitcond_i_i_i_reg_318;
ap_reg_pp0_iter5_tmp_1_i_i_reg_344 <= ap_reg_pp0_iter4_tmp_1_i_i_reg_344;
ap_reg_pp0_iter5_tmp_8_reg_334 <= ap_reg_pp0_iter4_tmp_8_reg_334;
ap_reg_pp0_iter5_tmp_i_i_reg_348 <= ap_reg_pp0_iter4_tmp_i_i_reg_348;
ap_reg_pp0_iter5_tmp_reg_339 <= ap_reg_pp0_iter4_tmp_reg_339;
ap_reg_pp0_iter6_exitcond_i_i_i_reg_318 <= ap_reg_pp0_iter5_exitcond_i_i_i_reg_318;
ap_reg_pp0_iter6_tmp_1_i_i_reg_344 <= ap_reg_pp0_iter5_tmp_1_i_i_reg_344;
ap_reg_pp0_iter6_tmp_8_reg_334 <= ap_reg_pp0_iter5_tmp_8_reg_334;
ap_reg_pp0_iter6_tmp_i_i_reg_348 <= ap_reg_pp0_iter5_tmp_i_i_reg_348;
ap_reg_pp0_iter6_tmp_reg_339 <= ap_reg_pp0_iter5_tmp_reg_339;
ap_reg_pp0_iter7_exitcond_i_i_i_reg_318 <= ap_reg_pp0_iter6_exitcond_i_i_i_reg_318;
ap_reg_pp0_iter7_tmp_1_i_i_reg_344 <= ap_reg_pp0_iter6_tmp_1_i_i_reg_344;
ap_reg_pp0_iter7_tmp_8_reg_334 <= ap_reg_pp0_iter6_tmp_8_reg_334;
ap_reg_pp0_iter7_tmp_i_i_reg_348 <= ap_reg_pp0_iter6_tmp_i_i_reg_348;
ap_reg_pp0_iter7_tmp_reg_339 <= ap_reg_pp0_iter6_tmp_reg_339;
ap_reg_pp0_iter8_exitcond_i_i_i_reg_318 <= ap_reg_pp0_iter7_exitcond_i_i_i_reg_318;
ap_reg_pp0_iter8_tmp_1_i_i_reg_344 <= ap_reg_pp0_iter7_tmp_1_i_i_reg_344;
ap_reg_pp0_iter8_tmp_8_reg_334 <= ap_reg_pp0_iter7_tmp_8_reg_334;
ap_reg_pp0_iter8_tmp_i_i_reg_348 <= ap_reg_pp0_iter7_tmp_i_i_reg_348;
ap_reg_pp0_iter8_tmp_reg_339 <= ap_reg_pp0_iter7_tmp_reg_339;
ap_reg_pp0_iter9_exitcond_i_i_i_reg_318 <= ap_reg_pp0_iter8_exitcond_i_i_i_reg_318;
ap_reg_pp0_iter9_tmp_1_i_i_reg_344 <= ap_reg_pp0_iter8_tmp_1_i_i_reg_344;
ap_reg_pp0_iter9_tmp_8_reg_334 <= ap_reg_pp0_iter8_tmp_8_reg_334;
ap_reg_pp0_iter9_tmp_i_i_reg_348 <= ap_reg_pp0_iter8_tmp_i_i_reg_348;
ap_reg_pp0_iter9_tmp_reg_339 <= ap_reg_pp0_iter8_tmp_reg_339;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
ap_reg_pp0_iter1_exitcond_i_i_i_reg_318 <= exitcond_i_i_i_reg_318;
exitcond_i_i_i_reg_318 <= exitcond_i_i_i_fu_226_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_start = ap_const_logic_0) or (tmp_3_cast_loc_empty_n = ap_const_logic_0) or (min_empty_n = ap_const_logic_0) or (p_cols_assign_cast_loc_empty_n = ap_const_logic_0) or (p_rows_assign_cast_loc_empty_n = ap_const_logic_0) or (max_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
extLd_reg_299(7 downto 0) <= extLd_fu_189_p1(7 downto 0);
max_read_reg_279 <= max_dout;
min_read_reg_284 <= min_dout;
p_cols_assign_cast_lo_reg_294 <= p_cols_assign_cast_loc_dout;
p_rows_assign_cast_lo_reg_289 <= p_rows_assign_cast_loc_dout;
tmp_8_tr_cast_i_i_ca_reg_304 <= tmp_8_tr_cast_i_i_ca_fu_203_p1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state2)) then
i_V_reg_313 <= i_V_fu_216_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_i_i_fu_241_p2 = ap_const_lv1_0) and (tmp_1_i_i_fu_237_p2 = ap_const_lv1_0) and (ap_reg_pp0_iter1_exitcond_i_i_i_reg_318 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
tmp_10_i_i_reg_352 <= tmp_10_i_i_fu_265_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_reg_pp0_iter1_exitcond_i_i_i_reg_318 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
tmp_1_i_i_reg_344 <= tmp_1_i_i_fu_237_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((exitcond_i_i_i_reg_318 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
tmp_8_reg_334 <= img1_data_stream_1_V_dout;
tmp_9_reg_327 <= img1_data_stream_0_V_dout;
tmp_reg_339 <= img1_data_stream_2_V_dout;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_1_i_i_fu_237_p2 = ap_const_lv1_0) and (ap_reg_pp0_iter1_exitcond_i_i_i_reg_318 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
tmp_i_i_reg_348 <= tmp_i_i_fu_241_p2;
end if;
end if;
end process;
extLd_reg_299(8) <= '0';
ap_NS_fsm_assign_proc : process (ap_start, ap_done_reg, ap_CS_fsm, ap_CS_fsm_state1, max_empty_n, p_rows_assign_cast_loc_empty_n, p_cols_assign_cast_loc_empty_n, min_empty_n, tmp_3_cast_loc_empty_n, ap_enable_reg_pp0_iter24, ap_enable_reg_pp0_iter1, exitcond51_i_i_i_fu_211_p2, ap_CS_fsm_state2, exitcond_i_i_i_fu_226_p2, ap_enable_reg_pp0_iter0, ap_block_pp0_stage0_subdone, ap_enable_reg_pp0_iter23)
begin
case ap_CS_fsm is
when ap_ST_fsm_state1 =>
if ((not(((ap_start = ap_const_logic_0) or (tmp_3_cast_loc_empty_n = ap_const_logic_0) or (min_empty_n = ap_const_logic_0) or (p_cols_assign_cast_loc_empty_n = ap_const_logic_0) or (p_rows_assign_cast_loc_empty_n = ap_const_logic_0) or (max_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_NS_fsm <= ap_ST_fsm_state2;
else
ap_NS_fsm <= ap_ST_fsm_state1;
end if;
when ap_ST_fsm_state2 =>
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (exitcond51_i_i_i_fu_211_p2 = ap_const_lv1_1))) then
ap_NS_fsm <= ap_ST_fsm_state1;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
end if;
when ap_ST_fsm_pp0_stage0 =>
if ((not(((ap_enable_reg_pp0_iter1 = ap_const_logic_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (exitcond_i_i_i_fu_226_p2 = ap_const_lv1_1))) and not(((ap_enable_reg_pp0_iter23 = ap_const_logic_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_enable_reg_pp0_iter24 = ap_const_logic_1))))) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
elsif ((((ap_enable_reg_pp0_iter23 = ap_const_logic_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_enable_reg_pp0_iter24 = ap_const_logic_1)) or ((ap_enable_reg_pp0_iter1 = ap_const_logic_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (exitcond_i_i_i_fu_226_p2 = ap_const_lv1_1)))) then
ap_NS_fsm <= ap_ST_fsm_state28;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
end if;
when ap_ST_fsm_state28 =>
ap_NS_fsm <= ap_ST_fsm_state2;
when others =>
ap_NS_fsm <= "XXXX";
end case;
end process;
ap_CS_fsm_pp0_stage0 <= ap_CS_fsm(2);
ap_CS_fsm_state1 <= ap_CS_fsm(0);
ap_CS_fsm_state2 <= ap_CS_fsm(1);
ap_CS_fsm_state28 <= ap_CS_fsm(3);
ap_block_pp0_stage0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage0_01001_assign_proc : process(img2_data_stream_0_V_full_n, img2_data_stream_1_V_full_n, img2_data_stream_2_V_full_n, img1_data_stream_0_V_empty_n, img1_data_stream_1_V_empty_n, img1_data_stream_2_V_empty_n, ap_enable_reg_pp0_iter24, exitcond_i_i_i_reg_318, ap_reg_pp0_iter23_exitcond_i_i_i_reg_318, ap_enable_reg_pp0_iter1)
begin
ap_block_pp0_stage0_01001 <= (((ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (((exitcond_i_i_i_reg_318 = ap_const_lv1_0) and (img1_data_stream_2_V_empty_n = ap_const_logic_0)) or ((exitcond_i_i_i_reg_318 = ap_const_lv1_0) and (img1_data_stream_1_V_empty_n = ap_const_logic_0)) or ((exitcond_i_i_i_reg_318 = ap_const_lv1_0) and (img1_data_stream_0_V_empty_n = ap_const_logic_0)))) or ((ap_enable_reg_pp0_iter24 = ap_const_logic_1) and (((ap_reg_pp0_iter23_exitcond_i_i_i_reg_318 = ap_const_lv1_0) and (img2_data_stream_2_V_full_n = ap_const_logic_0)) or ((ap_reg_pp0_iter23_exitcond_i_i_i_reg_318 = ap_const_lv1_0) and (img2_data_stream_1_V_full_n = ap_const_logic_0)) or ((ap_reg_pp0_iter23_exitcond_i_i_i_reg_318 = ap_const_lv1_0) and (img2_data_stream_0_V_full_n = ap_const_logic_0)))));
end process;
ap_block_pp0_stage0_11001_assign_proc : process(img2_data_stream_0_V_full_n, img2_data_stream_1_V_full_n, img2_data_stream_2_V_full_n, img1_data_stream_0_V_empty_n, img1_data_stream_1_V_empty_n, img1_data_stream_2_V_empty_n, ap_enable_reg_pp0_iter24, exitcond_i_i_i_reg_318, ap_reg_pp0_iter23_exitcond_i_i_i_reg_318, ap_enable_reg_pp0_iter1)
begin
ap_block_pp0_stage0_11001 <= (((ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (((exitcond_i_i_i_reg_318 = ap_const_lv1_0) and (img1_data_stream_2_V_empty_n = ap_const_logic_0)) or ((exitcond_i_i_i_reg_318 = ap_const_lv1_0) and (img1_data_stream_1_V_empty_n = ap_const_logic_0)) or ((exitcond_i_i_i_reg_318 = ap_const_lv1_0) and (img1_data_stream_0_V_empty_n = ap_const_logic_0)))) or ((ap_enable_reg_pp0_iter24 = ap_const_logic_1) and (((ap_reg_pp0_iter23_exitcond_i_i_i_reg_318 = ap_const_lv1_0) and (img2_data_stream_2_V_full_n = ap_const_logic_0)) or ((ap_reg_pp0_iter23_exitcond_i_i_i_reg_318 = ap_const_lv1_0) and (img2_data_stream_1_V_full_n = ap_const_logic_0)) or ((ap_reg_pp0_iter23_exitcond_i_i_i_reg_318 = ap_const_lv1_0) and (img2_data_stream_0_V_full_n = ap_const_logic_0)))));
end process;
ap_block_pp0_stage0_subdone_assign_proc : process(img2_data_stream_0_V_full_n, img2_data_stream_1_V_full_n, img2_data_stream_2_V_full_n, img1_data_stream_0_V_empty_n, img1_data_stream_1_V_empty_n, img1_data_stream_2_V_empty_n, ap_enable_reg_pp0_iter24, exitcond_i_i_i_reg_318, ap_reg_pp0_iter23_exitcond_i_i_i_reg_318, ap_enable_reg_pp0_iter1)
begin
ap_block_pp0_stage0_subdone <= (((ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (((exitcond_i_i_i_reg_318 = ap_const_lv1_0) and (img1_data_stream_2_V_empty_n = ap_const_logic_0)) or ((exitcond_i_i_i_reg_318 = ap_const_lv1_0) and (img1_data_stream_1_V_empty_n = ap_const_logic_0)) or ((exitcond_i_i_i_reg_318 = ap_const_lv1_0) and (img1_data_stream_0_V_empty_n = ap_const_logic_0)))) or ((ap_enable_reg_pp0_iter24 = ap_const_logic_1) and (((ap_reg_pp0_iter23_exitcond_i_i_i_reg_318 = ap_const_lv1_0) and (img2_data_stream_2_V_full_n = ap_const_logic_0)) or ((ap_reg_pp0_iter23_exitcond_i_i_i_reg_318 = ap_const_lv1_0) and (img2_data_stream_1_V_full_n = ap_const_logic_0)) or ((ap_reg_pp0_iter23_exitcond_i_i_i_reg_318 = ap_const_lv1_0) and (img2_data_stream_0_V_full_n = ap_const_logic_0)))));
end process;
ap_block_state1_assign_proc : process(ap_start, ap_done_reg, max_empty_n, p_rows_assign_cast_loc_empty_n, p_cols_assign_cast_loc_empty_n, min_empty_n, tmp_3_cast_loc_empty_n)
begin
ap_block_state1 <= ((ap_start = ap_const_logic_0) or (tmp_3_cast_loc_empty_n = ap_const_logic_0) or (min_empty_n = ap_const_logic_0) or (p_cols_assign_cast_loc_empty_n = ap_const_logic_0) or (p_rows_assign_cast_loc_empty_n = ap_const_logic_0) or (max_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1));
end process;
ap_block_state10_pp0_stage0_iter7 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state11_pp0_stage0_iter8 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state12_pp0_stage0_iter9 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state13_pp0_stage0_iter10 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state14_pp0_stage0_iter11 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state15_pp0_stage0_iter12 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state16_pp0_stage0_iter13 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state17_pp0_stage0_iter14 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state18_pp0_stage0_iter15 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state19_pp0_stage0_iter16 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state20_pp0_stage0_iter17 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state21_pp0_stage0_iter18 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state22_pp0_stage0_iter19 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state23_pp0_stage0_iter20 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state24_pp0_stage0_iter21 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state25_pp0_stage0_iter22 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state26_pp0_stage0_iter23 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state27_pp0_stage0_iter24_assign_proc : process(img2_data_stream_0_V_full_n, img2_data_stream_1_V_full_n, img2_data_stream_2_V_full_n, ap_reg_pp0_iter23_exitcond_i_i_i_reg_318)
begin
ap_block_state27_pp0_stage0_iter24 <= (((ap_reg_pp0_iter23_exitcond_i_i_i_reg_318 = ap_const_lv1_0) and (img2_data_stream_2_V_full_n = ap_const_logic_0)) or ((ap_reg_pp0_iter23_exitcond_i_i_i_reg_318 = ap_const_lv1_0) and (img2_data_stream_1_V_full_n = ap_const_logic_0)) or ((ap_reg_pp0_iter23_exitcond_i_i_i_reg_318 = ap_const_lv1_0) and (img2_data_stream_0_V_full_n = ap_const_logic_0)));
end process;
ap_block_state3_pp0_stage0_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state4_pp0_stage0_iter1_assign_proc : process(img1_data_stream_0_V_empty_n, img1_data_stream_1_V_empty_n, img1_data_stream_2_V_empty_n, exitcond_i_i_i_reg_318)
begin
ap_block_state4_pp0_stage0_iter1 <= (((exitcond_i_i_i_reg_318 = ap_const_lv1_0) and (img1_data_stream_2_V_empty_n = ap_const_logic_0)) or ((exitcond_i_i_i_reg_318 = ap_const_lv1_0) and (img1_data_stream_1_V_empty_n = ap_const_logic_0)) or ((exitcond_i_i_i_reg_318 = ap_const_lv1_0) and (img1_data_stream_0_V_empty_n = ap_const_logic_0)));
end process;
ap_block_state5_pp0_stage0_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state6_pp0_stage0_iter3 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state7_pp0_stage0_iter4 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state8_pp0_stage0_iter5 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state9_pp0_stage0_iter6 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_condition_362_assign_proc : process(ap_reg_pp0_iter22_exitcond_i_i_i_reg_318, ap_reg_pp0_iter22_tmp_1_i_i_reg_344, ap_reg_pp0_iter22_tmp_i_i_reg_348)
begin
ap_condition_362 <= ((ap_reg_pp0_iter22_tmp_i_i_reg_348 = ap_const_lv1_0) and (ap_reg_pp0_iter22_tmp_1_i_i_reg_344 = ap_const_lv1_0) and (ap_reg_pp0_iter22_exitcond_i_i_i_reg_318 = ap_const_lv1_0));
end process;
ap_condition_490_assign_proc : process(ap_reg_pp0_iter1_exitcond_i_i_i_reg_318, tmp_1_i_i_fu_237_p2, tmp_i_i_fu_241_p2)
begin
ap_condition_490 <= ((tmp_1_i_i_fu_237_p2 = ap_const_lv1_0) and (ap_reg_pp0_iter1_exitcond_i_i_i_reg_318 = ap_const_lv1_0) and (tmp_i_i_fu_241_p2 = ap_const_lv1_1));
end process;
ap_condition_pp0_exit_iter0_state3_assign_proc : process(exitcond_i_i_i_fu_226_p2)
begin
if ((exitcond_i_i_i_fu_226_p2 = ap_const_lv1_1)) then
ap_condition_pp0_exit_iter0_state3 <= ap_const_logic_1;
else
ap_condition_pp0_exit_iter0_state3 <= ap_const_logic_0;
end if;
end process;
ap_done_assign_proc : process(ap_done_reg, exitcond51_i_i_i_fu_211_p2, ap_CS_fsm_state2)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (exitcond51_i_i_i_fu_211_p2 = ap_const_lv1_1))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_done_reg;
end if;
end process;
ap_enable_pp0 <= (ap_idle_pp0 xor ap_const_logic_1);
ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
begin
if (((ap_start = ap_const_logic_0) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_idle_pp0_assign_proc : process(ap_enable_reg_pp0_iter24, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter0, ap_enable_reg_pp0_iter2, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter4, ap_enable_reg_pp0_iter5, ap_enable_reg_pp0_iter6, ap_enable_reg_pp0_iter7, ap_enable_reg_pp0_iter8, ap_enable_reg_pp0_iter9, ap_enable_reg_pp0_iter10, ap_enable_reg_pp0_iter11, ap_enable_reg_pp0_iter12, ap_enable_reg_pp0_iter13, ap_enable_reg_pp0_iter14, ap_enable_reg_pp0_iter15, ap_enable_reg_pp0_iter16, ap_enable_reg_pp0_iter17, ap_enable_reg_pp0_iter18, ap_enable_reg_pp0_iter19, ap_enable_reg_pp0_iter20, ap_enable_reg_pp0_iter21, ap_enable_reg_pp0_iter22, ap_enable_reg_pp0_iter23)
begin
if (((ap_enable_reg_pp0_iter1 = ap_const_logic_0) and (ap_enable_reg_pp0_iter24 = ap_const_logic_0) and (ap_enable_reg_pp0_iter23 = ap_const_logic_0) and (ap_enable_reg_pp0_iter22 = ap_const_logic_0) and (ap_enable_reg_pp0_iter21 = ap_const_logic_0) and (ap_enable_reg_pp0_iter20 = ap_const_logic_0) and (ap_enable_reg_pp0_iter19 = ap_const_logic_0) and (ap_enable_reg_pp0_iter18 = ap_const_logic_0) and (ap_enable_reg_pp0_iter17 = ap_const_logic_0) and (ap_enable_reg_pp0_iter16 = ap_const_logic_0) and (ap_enable_reg_pp0_iter15 = ap_const_logic_0) and (ap_enable_reg_pp0_iter14 = ap_const_logic_0) and (ap_enable_reg_pp0_iter13 = ap_const_logic_0) and (ap_enable_reg_pp0_iter12 = ap_const_logic_0) and (ap_enable_reg_pp0_iter11 = ap_const_logic_0) and (ap_enable_reg_pp0_iter10 = ap_const_logic_0) and (ap_enable_reg_pp0_iter9 = ap_const_logic_0) and (ap_enable_reg_pp0_iter8 = ap_const_logic_0) and (ap_enable_reg_pp0_iter7 = ap_const_logic_0) and (ap_enable_reg_pp0_iter6 = ap_const_logic_0) and (ap_enable_reg_pp0_iter5 = ap_const_logic_0) and (ap_enable_reg_pp0_iter4 = ap_const_logic_0) and (ap_enable_reg_pp0_iter3 = ap_const_logic_0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_0))) then
ap_idle_pp0 <= ap_const_logic_1;
else
ap_idle_pp0 <= ap_const_logic_0;
end if;
end process;
ap_phi_reg_pp0_iter0_tmp_2_reg_173 <= "XXXXXXXX";
ap_ready_assign_proc : process(exitcond51_i_i_i_fu_211_p2, ap_CS_fsm_state2)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (exitcond51_i_i_i_fu_211_p2 = ap_const_lv1_1))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
exitcond51_i_i_i_fu_211_p2 <= "1" when (t_V_cast_i_i_fu_207_p1 = p_rows_assign_cast_lo_reg_289) else "0";
exitcond_i_i_i_fu_226_p2 <= "1" when (t_V_1_cast_i_i_fu_222_p1 = p_cols_assign_cast_lo_reg_294) else "0";
extLd_fu_189_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_3_cast_loc_dout),9));
grp_fu_271_ce_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
grp_fu_271_ce <= ap_const_logic_1;
else
grp_fu_271_ce <= ap_const_logic_0;
end if;
end process;
grp_fu_271_p1 <= tmp_8_tr_cast_i_i_ca_reg_304(9 - 1 downto 0);
i_V_fu_216_p2 <= std_logic_vector(unsigned(t_V_reg_151) + unsigned(ap_const_lv11_1));
img1_data_stream_0_V_blk_n_assign_proc : process(img1_data_stream_0_V_empty_n, ap_block_pp0_stage0, exitcond_i_i_i_reg_318, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1)
begin
if (((exitcond_i_i_i_reg_318 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
img1_data_stream_0_V_blk_n <= img1_data_stream_0_V_empty_n;
else
img1_data_stream_0_V_blk_n <= ap_const_logic_1;
end if;
end process;
img1_data_stream_0_V_read_assign_proc : process(exitcond_i_i_i_reg_318, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_11001)
begin
if (((exitcond_i_i_i_reg_318 = ap_const_lv1_0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
img1_data_stream_0_V_read <= ap_const_logic_1;
else
img1_data_stream_0_V_read <= ap_const_logic_0;
end if;
end process;
img1_data_stream_1_V_blk_n_assign_proc : process(img1_data_stream_1_V_empty_n, ap_block_pp0_stage0, exitcond_i_i_i_reg_318, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1)
begin
if (((exitcond_i_i_i_reg_318 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
img1_data_stream_1_V_blk_n <= img1_data_stream_1_V_empty_n;
else
img1_data_stream_1_V_blk_n <= ap_const_logic_1;
end if;
end process;
img1_data_stream_1_V_read_assign_proc : process(exitcond_i_i_i_reg_318, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_11001)
begin
if (((exitcond_i_i_i_reg_318 = ap_const_lv1_0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
img1_data_stream_1_V_read <= ap_const_logic_1;
else
img1_data_stream_1_V_read <= ap_const_logic_0;
end if;
end process;
img1_data_stream_2_V_blk_n_assign_proc : process(img1_data_stream_2_V_empty_n, ap_block_pp0_stage0, exitcond_i_i_i_reg_318, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1)
begin
if (((exitcond_i_i_i_reg_318 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
img1_data_stream_2_V_blk_n <= img1_data_stream_2_V_empty_n;
else
img1_data_stream_2_V_blk_n <= ap_const_logic_1;
end if;
end process;
img1_data_stream_2_V_read_assign_proc : process(exitcond_i_i_i_reg_318, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_11001)
begin
if (((exitcond_i_i_i_reg_318 = ap_const_lv1_0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
img1_data_stream_2_V_read <= ap_const_logic_1;
else
img1_data_stream_2_V_read <= ap_const_logic_0;
end if;
end process;
img2_data_stream_0_V_blk_n_assign_proc : process(img2_data_stream_0_V_full_n, ap_enable_reg_pp0_iter24, ap_block_pp0_stage0, ap_reg_pp0_iter23_exitcond_i_i_i_reg_318)
begin
if (((ap_reg_pp0_iter23_exitcond_i_i_i_reg_318 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter24 = ap_const_logic_1))) then
img2_data_stream_0_V_blk_n <= img2_data_stream_0_V_full_n;
else
img2_data_stream_0_V_blk_n <= ap_const_logic_1;
end if;
end process;
img2_data_stream_0_V_din <= ap_phi_reg_pp0_iter24_tmp_2_reg_173;
img2_data_stream_0_V_write_assign_proc : process(ap_enable_reg_pp0_iter24, ap_reg_pp0_iter23_exitcond_i_i_i_reg_318, ap_block_pp0_stage0_11001)
begin
if (((ap_reg_pp0_iter23_exitcond_i_i_i_reg_318 = ap_const_lv1_0) and (ap_enable_reg_pp0_iter24 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
img2_data_stream_0_V_write <= ap_const_logic_1;
else
img2_data_stream_0_V_write <= ap_const_logic_0;
end if;
end process;
img2_data_stream_1_V_blk_n_assign_proc : process(img2_data_stream_1_V_full_n, ap_enable_reg_pp0_iter24, ap_block_pp0_stage0, ap_reg_pp0_iter23_exitcond_i_i_i_reg_318)
begin
if (((ap_reg_pp0_iter23_exitcond_i_i_i_reg_318 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter24 = ap_const_logic_1))) then
img2_data_stream_1_V_blk_n <= img2_data_stream_1_V_full_n;
else
img2_data_stream_1_V_blk_n <= ap_const_logic_1;
end if;
end process;
img2_data_stream_1_V_din <= ap_reg_pp0_iter23_tmp_8_reg_334;
img2_data_stream_1_V_write_assign_proc : process(ap_enable_reg_pp0_iter24, ap_reg_pp0_iter23_exitcond_i_i_i_reg_318, ap_block_pp0_stage0_11001)
begin
if (((ap_reg_pp0_iter23_exitcond_i_i_i_reg_318 = ap_const_lv1_0) and (ap_enable_reg_pp0_iter24 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
img2_data_stream_1_V_write <= ap_const_logic_1;
else
img2_data_stream_1_V_write <= ap_const_logic_0;
end if;
end process;
img2_data_stream_2_V_blk_n_assign_proc : process(img2_data_stream_2_V_full_n, ap_enable_reg_pp0_iter24, ap_block_pp0_stage0, ap_reg_pp0_iter23_exitcond_i_i_i_reg_318)
begin
if (((ap_reg_pp0_iter23_exitcond_i_i_i_reg_318 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter24 = ap_const_logic_1))) then
img2_data_stream_2_V_blk_n <= img2_data_stream_2_V_full_n;
else
img2_data_stream_2_V_blk_n <= ap_const_logic_1;
end if;
end process;
img2_data_stream_2_V_din <= ap_reg_pp0_iter23_tmp_reg_339;
img2_data_stream_2_V_write_assign_proc : process(ap_enable_reg_pp0_iter24, ap_reg_pp0_iter23_exitcond_i_i_i_reg_318, ap_block_pp0_stage0_11001)
begin
if (((ap_reg_pp0_iter23_exitcond_i_i_i_reg_318 = ap_const_lv1_0) and (ap_enable_reg_pp0_iter24 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
img2_data_stream_2_V_write <= ap_const_logic_1;
else
img2_data_stream_2_V_write <= ap_const_logic_0;
end if;
end process;
j_V_fu_231_p2 <= std_logic_vector(unsigned(t_V_2_reg_162) + unsigned(ap_const_lv11_1));
max_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, max_empty_n)
begin
if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
max_blk_n <= max_empty_n;
else
max_blk_n <= ap_const_logic_1;
end if;
end process;
max_read_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, max_empty_n, p_rows_assign_cast_loc_empty_n, p_cols_assign_cast_loc_empty_n, min_empty_n, tmp_3_cast_loc_empty_n)
begin
if ((not(((ap_start = ap_const_logic_0) or (tmp_3_cast_loc_empty_n = ap_const_logic_0) or (min_empty_n = ap_const_logic_0) or (p_cols_assign_cast_loc_empty_n = ap_const_logic_0) or (p_rows_assign_cast_loc_empty_n = ap_const_logic_0) or (max_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
max_read <= ap_const_logic_1;
else
max_read <= ap_const_logic_0;
end if;
end process;
min_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, min_empty_n)
begin
if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
min_blk_n <= min_empty_n;
else
min_blk_n <= ap_const_logic_1;
end if;
end process;
min_read_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, max_empty_n, p_rows_assign_cast_loc_empty_n, p_cols_assign_cast_loc_empty_n, min_empty_n, tmp_3_cast_loc_empty_n)
begin
if ((not(((ap_start = ap_const_logic_0) or (tmp_3_cast_loc_empty_n = ap_const_logic_0) or (min_empty_n = ap_const_logic_0) or (p_cols_assign_cast_loc_empty_n = ap_const_logic_0) or (p_rows_assign_cast_loc_empty_n = ap_const_logic_0) or (max_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
min_read <= ap_const_logic_1;
else
min_read <= ap_const_logic_0;
end if;
end process;
p_cols_assign_cast_loc_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, p_cols_assign_cast_loc_empty_n)
begin
if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
p_cols_assign_cast_loc_blk_n <= p_cols_assign_cast_loc_empty_n;
else
p_cols_assign_cast_loc_blk_n <= ap_const_logic_1;
end if;
end process;
p_cols_assign_cast_loc_read_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, max_empty_n, p_rows_assign_cast_loc_empty_n, p_cols_assign_cast_loc_empty_n, min_empty_n, tmp_3_cast_loc_empty_n)
begin
if ((not(((ap_start = ap_const_logic_0) or (tmp_3_cast_loc_empty_n = ap_const_logic_0) or (min_empty_n = ap_const_logic_0) or (p_cols_assign_cast_loc_empty_n = ap_const_logic_0) or (p_rows_assign_cast_loc_empty_n = ap_const_logic_0) or (max_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
p_cols_assign_cast_loc_read <= ap_const_logic_1;
else
p_cols_assign_cast_loc_read <= ap_const_logic_0;
end if;
end process;
p_rows_assign_cast_loc_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, p_rows_assign_cast_loc_empty_n)
begin
if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
p_rows_assign_cast_loc_blk_n <= p_rows_assign_cast_loc_empty_n;
else
p_rows_assign_cast_loc_blk_n <= ap_const_logic_1;
end if;
end process;
p_rows_assign_cast_loc_read_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, max_empty_n, p_rows_assign_cast_loc_empty_n, p_cols_assign_cast_loc_empty_n, min_empty_n, tmp_3_cast_loc_empty_n)
begin
if ((not(((ap_start = ap_const_logic_0) or (tmp_3_cast_loc_empty_n = ap_const_logic_0) or (min_empty_n = ap_const_logic_0) or (p_cols_assign_cast_loc_empty_n = ap_const_logic_0) or (p_rows_assign_cast_loc_empty_n = ap_const_logic_0) or (max_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
p_rows_assign_cast_loc_read <= ap_const_logic_1;
else
p_rows_assign_cast_loc_read <= ap_const_logic_0;
end if;
end process;
p_shl_i_i_fu_257_p3 <= (tmp_9_i_i_fu_248_p2 & ap_const_lv8_0);
t_V_1_cast_i_i_fu_222_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(t_V_2_reg_162),12));
t_V_cast_i_i_fu_207_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(t_V_reg_151),12));
tmp_10_i_i_fu_265_p2 <= std_logic_vector(unsigned(p_shl_i_i_fu_257_p3) - unsigned(tmp_9_cast_i_i_fu_253_p1));
tmp_1_i_i_fu_237_p2 <= "1" when (unsigned(tmp_9_reg_327) > unsigned(max_read_reg_279)) else "0";
tmp_3_cast_loc_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, tmp_3_cast_loc_empty_n)
begin
if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
tmp_3_cast_loc_blk_n <= tmp_3_cast_loc_empty_n;
else
tmp_3_cast_loc_blk_n <= ap_const_logic_1;
end if;
end process;
tmp_3_cast_loc_read_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, max_empty_n, p_rows_assign_cast_loc_empty_n, p_cols_assign_cast_loc_empty_n, min_empty_n, tmp_3_cast_loc_empty_n)
begin
if ((not(((ap_start = ap_const_logic_0) or (tmp_3_cast_loc_empty_n = ap_const_logic_0) or (min_empty_n = ap_const_logic_0) or (p_cols_assign_cast_loc_empty_n = ap_const_logic_0) or (p_rows_assign_cast_loc_empty_n = ap_const_logic_0) or (max_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
tmp_3_cast_loc_read <= ap_const_logic_1;
else
tmp_3_cast_loc_read <= ap_const_logic_0;
end if;
end process;
tmp_7_fu_275_p1 <= grp_fu_271_p2(8 - 1 downto 0);
tmp_8_cast_i_i_fu_245_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_9_reg_327),9));
tmp_8_tr_cast_i_i_ca_fu_203_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_8_tr_i_i_fu_197_p2),17));
tmp_8_tr_i_i_fu_197_p2 <= std_logic_vector(unsigned(tmp_cast_i_i_fu_193_p1) - unsigned(extLd_fu_189_p1));
tmp_9_cast_i_i_fu_253_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_9_i_i_fu_248_p2),17));
tmp_9_i_i_fu_248_p2 <= std_logic_vector(unsigned(tmp_8_cast_i_i_fu_245_p1) - unsigned(extLd_reg_299));
tmp_cast_i_i_fu_193_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(max_dout),9));
tmp_i_i_fu_241_p2 <= "1" when (unsigned(tmp_9_reg_327) < unsigned(min_read_reg_284)) else "0";
end behav;
|
mit
|
Digilent/vivado-library
|
ip/MIPI_CSI_2_RX/hdl/MIPI_CSI_2_RX_v1_0_S_AXI_LITE.vhd
|
1
|
15076
|
-------------------------------------------------------------------------------
--
-- File: MIPI_CSI_2_RX_v1_0_S_AXI_LITE.vhd
-- Author: Elod Gyorgy
-- Original Project: MIPI CSI-2 Receiver IP
-- Date: 15 December 2017
--
-------------------------------------------------------------------------------
--MIT License
--
--Copyright (c) 2016 Digilent
--
--Permission is hereby granted, free of charge, to any person obtaining a copy
--of this software and associated documentation files (the "Software"), to deal
--in the Software without restriction, including without limitation the rights
--to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
--copies of the Software, and to permit persons to whom the Software is
--furnished to do so, subject to the following conditions:
--
--The above copyright notice and this permission notice shall be included in all
--copies or substantial portions of the Software.
--
--THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
--IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
--FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
--AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
--LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
--OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
--SOFTWARE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity MIPI_CSI_2_RX_S_AXI_LITE is
generic (
-- Users to add parameters here
kVersionMajor : natural := 0;
kVersionMinor : natural := 0;
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bus
C_S_AXI_ADDR_WIDTH : integer := 4
);
port (
-- Users to add ports here
xEnable : out std_logic;
xRst : out std_logic;
-- User ports ends
-- Do not modify the ports beyond this line
-- Global Clock Signal
S_AXI_ACLK : in std_logic;
-- Global Reset Signal. This Signal is Active LOW
S_AXI_ARESETN : in std_logic;
-- Write address (issued by master, acceped by Slave)
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Write channel Protection type. This signal indicates the
-- privilege and security level of the transaction, and whether
-- the transaction is a data access or an instruction access.
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
-- Write address valid. This signal indicates that the master signaling
-- valid write address and control information.
S_AXI_AWVALID : in std_logic;
-- Write address ready. This signal indicates that the slave is ready
-- to accept an address and associated control signals.
S_AXI_AWREADY : out std_logic;
-- Write data (issued by master, acceped by Slave)
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Write strobes. This signal indicates which byte lanes hold
-- valid data. There is one write strobe bit for each eight
-- bits of the write data bus.
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
-- Write valid. This signal indicates that valid write
-- data and strobes are available.
S_AXI_WVALID : in std_logic;
-- Write ready. This signal indicates that the slave
-- can accept the write data.
S_AXI_WREADY : out std_logic;
-- Write response. This signal indicates the status
-- of the write transaction.
S_AXI_BRESP : out std_logic_vector(1 downto 0);
-- Write response valid. This signal indicates that the channel
-- is signaling a valid write response.
S_AXI_BVALID : out std_logic;
-- Response ready. This signal indicates that the master
-- can accept a write response.
S_AXI_BREADY : in std_logic;
-- Read address (issued by master, acceped by Slave)
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Protection type. This signal indicates the privilege
-- and security level of the transaction, and whether the
-- transaction is a data access or an instruction access.
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
-- Read address valid. This signal indicates that the channel
-- is signaling valid read address and control information.
S_AXI_ARVALID : in std_logic;
-- Read address ready. This signal indicates that the slave is
-- ready to accept an address and associated control signals.
S_AXI_ARREADY : out std_logic;
-- Read data (issued by slave)
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Read response. This signal indicates the status of the
-- read transfer.
S_AXI_RRESP : out std_logic_vector(1 downto 0);
-- Read valid. This signal indicates that the channel is
-- signaling the required read data.
S_AXI_RVALID : out std_logic;
-- Read ready. This signal indicates that the master can
-- accept the read data and response information.
S_AXI_RREADY : in std_logic
);
end MIPI_CSI_2_RX_S_AXI_LITE;
architecture arch_imp of MIPI_CSI_2_RX_S_AXI_LITE is
constant kCTRL_EN : natural := 1;
constant kCTRL_RST : natural := 0;
constant kVersion : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(kVersionMajor,16)) & std_logic_vector(to_unsigned(kVersionMinor,16));
-- AXI4LITE signals
signal axi_awaddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_awready : std_logic;
signal axi_wready : std_logic;
signal axi_bresp : std_logic_vector(1 downto 0);
signal axi_bvalid : std_logic;
signal axi_araddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_arready : std_logic;
signal axi_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal axi_rresp : std_logic_vector(1 downto 0);
signal axi_rvalid : std_logic;
-- Example-specific design signals
-- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
-- ADDR_LSB is used for addressing 32/64 bit registers/memories
-- ADDR_LSB = 2 for 32 bits (n downto 2)
-- ADDR_LSB = 3 for 64 bits (n downto 3)
constant ADDR_LSB : integer := (C_S_AXI_DATA_WIDTH/32)+ 1;
constant OPT_MEM_ADDR_BITS : integer := 1;
------------------------------------------------
---- Signals for user logic register space example
--------------------------------------------------
---- Number of Slave Registers 1
signal control_reg :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg_rden : std_logic;
signal slv_reg_wren : std_logic;
signal reg_data_out :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal byte_index : integer;
begin
-- I/O Connections assignments
S_AXI_AWREADY <= axi_awready;
S_AXI_WREADY <= axi_wready;
S_AXI_BRESP <= axi_bresp;
S_AXI_BVALID <= axi_bvalid;
S_AXI_ARREADY <= axi_arready;
S_AXI_RDATA <= axi_rdata;
S_AXI_RRESP <= axi_rresp;
S_AXI_RVALID <= axi_rvalid;
-- Implement axi_awready generation
-- axi_awready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awready <= '0';
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- slave is ready to accept write address when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_awready <= '1';
else
axi_awready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_awaddr latching
-- This process is used to latch the address when both
-- S_AXI_AWVALID and S_AXI_WVALID are valid.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awaddr <= (others => '0');
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- Write Address latching
axi_awaddr <= S_AXI_AWADDR;
end if;
end if;
end if;
end process;
-- Implement axi_wready generation
-- axi_wready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_wready <= '0';
else
if (axi_wready = '0' and S_AXI_WVALID = '1' and S_AXI_AWVALID = '1') then
-- slave is ready to accept write data when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_wready <= '1';
else
axi_wready <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and write logic generation
-- The write data is accepted and written to memory mapped registers when
-- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
-- select byte enables of slave registers while writing.
-- These registers are cleared when reset (active low) is applied.
-- Slave register write enable is asserted when valid address and data are available
-- and the slave is ready to accept the write address and write data.
slv_reg_wren <= axi_wready and S_AXI_WVALID and axi_awready and S_AXI_AWVALID ;
process (S_AXI_ACLK)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
control_reg <= (kCTRL_RST => '0', kCTRL_EN => '1', others => '0');
else
loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
if (slv_reg_wren = '1') then
case loc_addr is
when b"00" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 0
control_reg(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when others =>
control_reg <= control_reg;
end case;
end if;
end if;
end if;
end process;
-- Implement write response logic generation
-- The write response and response valid signals are asserted by the slave
-- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
-- This marks the acceptance of address and indicates the status of
-- write transaction.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_bvalid <= '0';
axi_bresp <= "00"; --need to work more on the responses
else
if (axi_awready = '1' and S_AXI_AWVALID = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0' ) then
axi_bvalid <= '1';
axi_bresp <= "00";
elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high)
axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high)
end if;
end if;
end if;
end process;
-- Implement axi_arready generation
-- axi_arready is asserted for one S_AXI_ACLK clock cycle when
-- S_AXI_ARVALID is asserted. axi_awready is
-- de-asserted when reset (active low) is asserted.
-- The read address is also latched when S_AXI_ARVALID is
-- asserted. axi_araddr is reset to zero on reset assertion.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_arready <= '0';
axi_araddr <= (others => '1');
else
if (axi_arready = '0' and S_AXI_ARVALID = '1') then
-- indicates that the slave has acceped the valid read address
axi_arready <= '1';
-- Read Address latching
axi_araddr <= S_AXI_ARADDR;
else
axi_arready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_arvalid generation
-- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_ARVALID and axi_arready are asserted. The slave registers
-- data are available on the axi_rdata bus at this instance. The
-- assertion of axi_rvalid marks the validity of read data on the
-- bus and axi_rresp indicates the status of read transaction.axi_rvalid
-- is deasserted on reset (active low). axi_rresp and axi_rdata are
-- cleared to zero on reset (active low).
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_rvalid <= '0';
axi_rresp <= "00";
else
if (axi_arready = '1' and S_AXI_ARVALID = '1' and axi_rvalid = '0') then
-- Valid read data is available at the read data bus
axi_rvalid <= '1';
axi_rresp <= "00"; -- 'OKAY' response
elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then
-- Read data is accepted by the master
axi_rvalid <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and read logic generation
-- Slave register read enable is asserted when valid address is available
-- and the slave is ready to accept the read address.
slv_reg_rden <= axi_arready and S_AXI_ARVALID and (not axi_rvalid) ;
process (control_reg, axi_araddr, S_AXI_ARESETN, slv_reg_rden)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
-- Address decoding for reading registers
loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
case loc_addr is
when b"00" =>
reg_data_out <= control_reg;
when b"11" =>
reg_data_out <= kVersion;
when others =>
reg_data_out <= (others => '0');
end case;
end process;
-- Output register or memory read data
process( S_AXI_ACLK ) is
begin
if (rising_edge (S_AXI_ACLK)) then
if ( S_AXI_ARESETN = '0' ) then
axi_rdata <= (others => '0');
else
if (slv_reg_rden = '1') then
-- When there is a valid read address (S_AXI_ARVALID) with
-- acceptance of read address by the slave (axi_arready),
-- output the read dada
-- Read address mux
axi_rdata <= reg_data_out; -- register read data
end if;
end if;
end if;
end process;
-- Add user logic here
xEnable <= control_reg(kCTRL_EN);
xRst <= control_reg(kCTRL_RST);
-- User logic ends
end arch_imp;
|
mit
|
Digilent/vivado-library
|
ip/dvi2rgb/src/TMDS_Decoder.vhd
|
1
|
10949
|
-------------------------------------------------------------------------------
--
-- File: TMDS_Decoder.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 8 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module connects to one TMDS data channel and decodes TMDS data
-- according to DVI specifications. It phase aligns the data channel,
-- deserializes the stream, eliminates skew between data channels and decodes
-- data in the end.
-- sDataIn_p/n -> buffer -> de-serialize -> channel de-skew -> decode -> pData
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.DVI_Constants.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity TMDS_Decoder is
Generic (
kCtlTknCount : natural := 128; --how many subsequent control tokens make a valid blank detection
kTimeoutMs : natural := 50; --what is the maximum time interval for a blank to be detected
kRefClkFrqMHz : natural := 200; --what is the RefClk frequency
kIDLY_TapValuePs : natural := 78; --delay in ps per tap
kIDLY_TapWidth : natural := 5); --number of bits for IDELAYE2 tap counter
Port (
PixelClk : in std_logic; --Recovered TMDS clock x1 (CLKDIV)
SerialClk : in std_logic; --Recovered TMDS clock x5 (CLK)
RefClk : std_logic; --200 MHz reference clock
aRst : in std_logic; --asynchronous reset; must be reset when PixelClk/SerialClk is not within spec
--Encoded serial data
sDataIn_p : in std_logic; --TMDS data channel positive
sDataIn_n : in std_logic; --TMDS data channel negative
--Decoded parallel data
pDataIn : out std_logic_vector(7 downto 0);
pC0 : out std_logic;
pC1 : out std_logic;
pVde : out std_logic;
-- Channel bonding (three data channels in total)
pOtherChVld : in std_logic_vector(1 downto 0);
pOtherChRdy : in std_logic_vector(1 downto 0);
pMeVld : out std_logic;
pMeRdy : out std_logic;
--Status and debug
pRst : in std_logic; -- Synchronous reset to restart lock procedure
dbg_pAlignErr : out std_logic;
dbg_pEyeSize : out STD_LOGIC_VECTOR(kIDLY_TapWidth-1 downto 0);
dbg_pBitslip : out std_logic
);
end TMDS_Decoder;
architecture Behavioral of TMDS_Decoder is
constant kBitslipDelay : natural := 3; --three-period delay after bitslip
signal pAlignRst, pLockLostRst_n : std_logic;
signal pBitslipCnt : natural range 0 to kBitslipDelay - 1 := kBitslipDelay - 1;
signal pDataIn8b : std_logic_vector(7 downto 0);
signal pDataInBnd : std_logic_vector(9 downto 0);
signal pDataInRaw : std_logic_vector(9 downto 0);
signal pMeRdy_int, pAligned, pAlignErr_int, pAlignErr_q, pBitslip : std_logic;
signal pIDLY_LD, pIDLY_CE, pIDLY_INC : std_logic;
signal pIDLY_CNT : std_logic_vector(kIDLY_TapWidth-1 downto 0);
-- Timeout Counter End
constant kTimeoutEnd : natural := kTimeoutMs * 1000 * kRefClkFrqMHz;
signal rTimeoutCnt : natural range 0 to kTimeoutEnd-1;
signal pTimeoutRst, pTimeoutOvf, rTimeoutRst, rTimeoutOvf : std_logic;
begin
dbg_pAlignErr <= pAlignErr_int;
dbg_pBitslip <= pBitslip;
-- Deserialization block
InputSERDES_X: entity work.InputSERDES
generic map (
kIDLY_TapWidth => kIDLY_TapWidth,
kParallelWidth => 10 -- TMDS uses 1:10 serialization
)
port map (
PixelClk => PixelClk,
SerialClk => SerialClk,
sDataIn_p => sDataIn_p,
sDataIn_n => sDataIn_n,
--Encoded parallel data (raw)
pDataIn => pDataInRaw,
--Control for phase alignment
pBitslip => pBitslip,
pIDLY_LD => pIDLY_LD,
pIDLY_CE => pIDLY_CE,
pIDLY_INC => pIDLY_INC,
pIDLY_CNT => pIDLY_CNT,
aRst => aRst
);
-- reset min two period (ISERDESE2 requirement)
-- de-assert synchronously with CLKDIV, min two period (ISERDESE2 requirement)
--The timeout counter runs on RefClk, because it's a fixed frequency we can measure timeout
--independently of the TMDS Clk
--The xTimeoutRst and xTimeoutOvf signals need to be synchronized back-and-forth
TimeoutCounter: process(RefClk)
begin
if Rising_Edge(RefClk) then
if (rTimeoutRst = '1') then
rTimeoutCnt <= 0;
elsif (rTimeoutOvf = '0') then
rTimeoutCnt <= rTimeoutCnt + 1;
end if;
end if;
end process TimeoutCounter;
rTimeoutOvf <= '0' when rTimeoutCnt /= kTimeoutEnd - 1 else
'1';
SyncBaseOvf: entity work.SyncBase
generic map (
kResetTo => '0',
kStages => 2) --use double FF synchronizer
port map (
aReset => aRst,
InClk => RefClk,
iIn => rTimeoutOvf,
OutClk => PixelClk,
oOut => pTimeoutOvf);
SyncBaseRst: entity work.SyncBase
generic map (
kResetTo => '1',
kStages => 2) --use double FF synchronizer
port map (
aReset => aRst,
InClk => PixelClk,
iIn => pTimeoutRst,
OutClk => RefClk,
oOut => rTimeoutRst);
-- Phase alignment controller to lock onto data stream
PhaseAlignX: entity work.PhaseAlign
generic map (
kUseFastAlgorithm => false,
kCtlTknCount => kCtlTknCount,
kIDLY_TapValuePs => kIDLY_TapValuePs,
kIDLY_TapWidth => kIDLY_TapWidth
)
port map (
pRst => pAlignRst,
PixelClk => PixelClk,
pTimeoutOvf => pTimeoutOvf,
pTimeoutRst => pTimeoutRst,
pData => pDataInRaw,
pIDLY_CE => pIDLY_CE,
pIDLY_INC => pIDLY_INC,
pIDLY_CNT => pIDLY_CNT,
pIDLY_LD => pIDLY_LD,
pAligned => pAligned,
pError => pAlignErr_int,
pEyeSize => dbg_pEyeSize);
pMeVld <= pAligned;
-- Bitslip when phase alignment exhausted the whole tap range and still no lock
Bitslip: process(PixelClk)
begin
if Rising_Edge(PixelClk) then
pAlignErr_q <= pAlignErr_int;
pBitslip <= not pAlignErr_q and pAlignErr_int; -- single pulse bitslip on failed alignment attempt
end if;
end process Bitslip;
ResetAlignment: process(PixelClk, aRst)
begin
if (aRst = '1') then
pAlignRst <= '1';
elsif Rising_Edge(PixelClk) then
if (pRst = '1' or pBitslip = '1') then
pAlignRst <= '1';
elsif (pBitslipCnt = 0) then
pAlignRst <= '0';
end if;
end if;
end process ResetAlignment;
-- Reset phase aligment module after bitslip + 3 CLKDIV cycles (ISERDESE2 requirement)
BitslipDelay: process(PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pBitslip = '1') then
pBitslipCnt <= kBitslipDelay - 1;
elsif (pBitslipCnt /= 0) then
pBitslipCnt <= pBitslipCnt - 1;
end if;
end if;
end process BitslipDelay;
-- Channel de-skew (bonding)
ChannelBondX: entity work.ChannelBond
port map (
PixelClk => PixelClk,
pDataInRaw => pDataInRaw,
pMeVld => pAligned,
pOtherChVld => pOtherChVld,
pOtherChRdy => pOtherChRdy,
pDataInBnd => pDataInBnd,
pMeRdy => pMeRdy_int);
pMeRdy <= pMeRdy_int;
-- Below performs the 10B-8B decoding function
-- DVI Specification: Section 3.3.3, Figure 3-6, page 31.
pDataIn8b <= pDataInBnd(7 downto 0) when pDataInBnd(9) = '0' else
not pDataInBnd(7 downto 0);
TMDS_Decode: process (PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pMeRdy_int = '1' and pOtherChRdy = "11") then
pDataIn <= x"00"; --added for VGA-compatibility (blank pixel needed during blanking)
case (pDataInBnd) is
--Control tokens decode straight to C0, C1 values
when kCtlTkn0 =>
pC0 <= '0';
pC1 <= '0';
pVde <= '0';
when kCtlTkn1 =>
pC0 <= '1';
pC1 <= '0';
pVde <= '0';
when kCtlTkn2 =>
pC0 <= '0';
pC1 <= '1';
pVde <= '0';
when kCtlTkn3 =>
pC0 <= '1';
pC1 <= '1';
pVde <= '0';
--If not control token, it's encoded data
when others =>
pVde <= '1';
pDataIn(0) <= pDataIn8b(0);
for iBit in 1 to 7 loop
if (pDataInBnd(8) = '1') then
pDataIn(iBit) <= pDataIn8b(iBit) xor pDataIn8b(iBit-1);
else
pDataIn(iBit) <= pDataIn8b(iBit) xnor pDataIn8b(iBit-1);
end if;
end loop;
end case;
else --if we are not aligned on all channels, gate outputs
pC0 <= '0';
pC1 <= '0';
pVde <= '0';
pDataIn <= x"00";
end if;
end if;
end process;
end Behavioral;
|
mit
|
Digilent/vivado-library
|
ip/video_scaler/hdl/vhdl/start_for_Resize_U0.vhd
|
1
|
4642
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2018.2
-- Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity start_for_Resize_U0_shiftReg is
generic (
DATA_WIDTH : integer := 1;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end start_for_Resize_U0_shiftReg;
architecture rtl of start_for_Resize_U0_shiftReg is
--constant DEPTH_WIDTH: integer := 16;
type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal SRL_SIG : SRL_ARRAY;
begin
p_shift: process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
end if;
end if;
end process;
q <= SRL_SIG(conv_integer(a));
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity start_for_Resize_U0 is
generic (
MEM_STYLE : string := "shiftreg";
DATA_WIDTH : integer := 1;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of start_for_Resize_U0 is
component start_for_Resize_U0_shiftReg is
generic (
DATA_WIDTH : integer := 1;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal shiftReg_ce : STD_LOGIC;
signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
signal internal_empty_n : STD_LOGIC := '0';
signal internal_full_n : STD_LOGIC := '1';
begin
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
shiftReg_data <= if_din;
if_dout <= shiftReg_q;
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
mOutPtr <= (others => '1');
internal_empty_n <= '0';
internal_full_n <= '1';
else
if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and
((if_write and if_write_ce) = '0' or internal_full_n = '0') then
mOutPtr <= mOutPtr - conv_std_logic_vector(1, 3);
if (mOutPtr = conv_std_logic_vector(0, 3)) then
internal_empty_n <= '0';
end if;
internal_full_n <= '1';
elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and
((if_write and if_write_ce) = '1' and internal_full_n = '1') then
mOutPtr <= mOutPtr + conv_std_logic_vector(1, 3);
internal_empty_n <= '1';
if (mOutPtr = conv_std_logic_vector(DEPTH, 3) - conv_std_logic_vector(2, 3)) then
internal_full_n <= '0';
end if;
end if;
end if;
end if;
end process;
shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
U_start_for_Resize_U0_shiftReg : start_for_Resize_U0_shiftReg
generic map (
DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
DEPTH => DEPTH)
port map (
clk => clk,
data => shiftReg_data,
ce => shiftReg_ce,
a => shiftReg_addr,
q => shiftReg_q);
end rtl;
|
mit
|
Digilent/vivado-library
|
ip/MIPI_CSI_2_RX/hdl/SyncAsync.vhd
|
2
|
3165
|
-------------------------------------------------------------------------------
--
-- File: SyncAsync.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 15 December 2017
--
-------------------------------------------------------------------------------
--MIT License
--
--Copyright (c) 2016 Digilent
--
--Permission is hereby granted, free of charge, to any person obtaining a copy
--of this software and associated documentation files (the "Software"), to deal
--in the Software without restriction, including without limitation the rights
--to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
--copies of the Software, and to permit persons to whom the Software is
--furnished to do so, subject to the following conditions:
--
--The above copyright notice and this permission notice shall be included in all
--copies or substantial portions of the Software.
--
--THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
--IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
--FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
--AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
--LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
--OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
--SOFTWARE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module synchronizes the asynchronous signal (aIn) with the OutClk clock
-- domain and provides it on oOut. The number of FFs in the synchronizer chain
-- can be configured with kStages. The reset value for oOut can be configured
-- with kResetTo. The asynchronous reset (aReset) is always active-high.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity SyncAsync is
Generic (
kResetTo : std_logic := '0'; --value when reset and upon init
kStages : natural := 2; --double sync by default
kResetPolarity : std_logic := '1'); --aReset active-high by default
Port (
aReset : in STD_LOGIC; -- active-high/active-low asynchronous reset
aIn : in STD_LOGIC;
OutClk : in STD_LOGIC;
oOut : out STD_LOGIC);
end SyncAsync;
architecture Behavioral of SyncAsync is
signal oSyncStages : std_logic_vector(kStages-1 downto 0) := (others => kResetTo);
attribute ASYNC_REG : string;
attribute ASYNC_REG of oSyncStages: signal is "TRUE";
begin
Sync: process (OutClk, aReset)
begin
if (aReset = kResetPolarity) then
oSyncStages <= (others => kResetTo);
elsif Rising_Edge(OutClk) then
oSyncStages <= oSyncStages(oSyncStages'high-1 downto 0) & aIn;
end if;
end process Sync;
oOut <= oSyncStages(oSyncStages'high);
end Behavioral;
|
mit
|
Digilent/vivado-library
|
ip/MIPI_CSI_2_RX/hdl/MIPI_CSI2_RxTop.vhd
|
1
|
10367
|
-------------------------------------------------------------------------------
--
-- File: MIPI_CSI2_RxTop.vhd
-- Author: Elod Gyorgy
-- Original Project: MIPI CSI-2 Receiver IP
-- Date: 15 December 2017
--
-------------------------------------------------------------------------------
--MIT License
--
--Copyright (c) 2016 Digilent
--
--Permission is hereby granted, free of charge, to any person obtaining a copy
--of this software and associated documentation files (the "Software"), to deal
--in the Software without restriction, including without limitation the rights
--to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
--copies of the Software, and to permit persons to whom the Software is
--furnished to do so, subject to the following conditions:
--
--The above copyright notice and this permission notice shall be included in all
--copies or substantial portions of the Software.
--
--THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
--IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
--FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
--AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
--LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
--OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
--SOFTWARE.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity mipi_csi2_rx_top is
Generic (
kVersionMajor : natural := 0; -- TCL-propagated from VLNV
kVersionMinor : natural := 0; -- TCL-propagated from VLNV
kTargetDT : string := "RAW10";
kGenerateAXIL : boolean := false;
kDebug : boolean := true;
--PPI
kLaneCount : natural range 1 to 4 := 2; --[1,2,4]
--Video Format
C_M_AXIS_COMPONENT_WIDTH : natural := 10; -- [8,10]
C_M_AXIS_TDATA_WIDTH : natural := 40;
C_M_MAX_SAMPLES_PER_CLOCK : natural := 4;
-- Parameters of Axi Slave Bus Interface S_AXI_LITE
C_S_AXI_LITE_DATA_WIDTH : integer := 32;
C_S_AXI_LITE_ADDR_WIDTH : integer := 4
);
Port (
--PPI
RxByteClkHS : in STD_LOGIC;
aClkStopstate : in std_logic;
aRxClkActiveHS : in std_logic;
RxDataHSD0 : in STD_LOGIC_VECTOR (7 downto 0);
RxSyncHSD0 : in STD_LOGIC;
RxValidHSD0 : in STD_LOGIC;
RxActiveHSD0 : in STD_LOGIC;
aD0Enable : out STD_LOGIC;
RxDataHSD1 : in STD_LOGIC_VECTOR (7 downto 0);
RxSyncHSD1 : in STD_LOGIC;
RxValidHSD1 : in STD_LOGIC;
RxActiveHSD1 : in STD_LOGIC;
aD1Enable : out STD_LOGIC;
RxDataHSD2 : in STD_LOGIC_VECTOR (7 downto 0);
RxSyncHSD2 : in STD_LOGIC;
RxValidHSD2 : in STD_LOGIC;
RxActiveHSD2 : in STD_LOGIC;
aD2Enable : out STD_LOGIC;
RxDataHSD3 : in STD_LOGIC_VECTOR (7 downto 0);
RxSyncHSD3 : in STD_LOGIC;
RxValidHSD3 : in STD_LOGIC;
RxActiveHSD3 : in STD_LOGIC;
aD3Enable : out STD_LOGIC;
aClkEnable : out STD_LOGIC;
--axi stream signals
m_axis_video_tdata : out std_logic_vector(C_M_AXIS_TDATA_WIDTH-1 downto 0);
m_axis_video_tvalid : out std_logic;
m_axis_video_tready : in std_logic;
m_axis_video_tlast : out std_logic;
m_axis_video_tuser : out std_logic_vector(0 downto 0);
video_aresetn : in std_logic; --available when the AXI-Lite interface is disabled
video_aclk : in std_logic;
-- Ports of Axi Slave Bus Interface S_AXI_LITE
s_axi_lite_aclk : in std_logic;
s_axi_lite_aresetn : in std_logic;
s_axi_lite_awaddr : in std_logic_vector(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0);
s_axi_lite_awprot : in std_logic_vector(2 downto 0);
s_axi_lite_awvalid : in std_logic;
s_axi_lite_awready : out std_logic;
s_axi_lite_wdata : in std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
s_axi_lite_wstrb : in std_logic_vector((C_S_AXI_LITE_DATA_WIDTH/8)-1 downto 0);
s_axi_lite_wvalid : in std_logic;
s_axi_lite_wready : out std_logic;
s_axi_lite_bresp : out std_logic_vector(1 downto 0);
s_axi_lite_bvalid : out std_logic;
s_axi_lite_bready : in std_logic;
s_axi_lite_araddr : in std_logic_vector(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0);
s_axi_lite_arprot : in std_logic_vector(2 downto 0);
s_axi_lite_arvalid : in std_logic;
s_axi_lite_arready : out std_logic;
s_axi_lite_rdata : out std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
s_axi_lite_rresp : out std_logic_vector(1 downto 0);
s_axi_lite_rvalid : out std_logic;
s_axi_lite_rready : in std_logic
);
end mipi_csi2_rx_top;
architecture Behavioral of mipi_csi2_rx_top is
constant kMaxLaneCount : natural := 4;
signal rbRxDataHS : STD_LOGIC_VECTOR (8 * kLaneCount - 1 downto 0);
signal rbRxSyncHS : STD_LOGIC_VECTOR (kLaneCount - 1 downto 0);
signal rbRxValidHS : STD_LOGIC_VECTOR (kLaneCount - 1 downto 0);
signal rbRxActiveHS : STD_LOGIC_VECTOR (kLaneCount - 1 downto 0);
signal aDEnable : STD_LOGIC_VECTOR (kLaneCount - 1 downto 0);
signal xSoftEnable, xSoftRst, vSoftEnable, vSoftRst, vRst_n : std_logic;
begin
InputDataGen: for i in 0 to kLaneCount-1 generate
DataLane0: if i = 0 generate
rbRxDataHS(8 * (i + 1) - 1 downto 8 * i) <= RxDataHSD0;
rbRxValidHS(i) <= RxValidHSD0;
rbRxActiveHS(i) <= RxActiveHSD0;
rbRxSyncHS(i) <= RxSyncHSD0;
aD0Enable <= aDEnable(i);
end generate;
DataLane1: if i = 1 generate
rbRxDataHS(8 * (i + 1) - 1 downto 8 * i) <= RxDataHSD1;
rbRxValidHS(i) <= RxValidHSD1;
rbRxActiveHS(i) <= RxActiveHSD1;
rbRxSyncHS(i) <= RxSyncHSD1;
aD1Enable <= aDEnable(i);
end generate;
DataLane2: if i = 2 generate
rbRxDataHS(8 * (i + 1) - 1 downto 8 * i) <= RxDataHSD2;
rbRxValidHS(i) <= RxValidHSD2;
rbRxActiveHS(i) <= RxActiveHSD2;
rbRxSyncHS(i) <= RxSyncHSD2;
aD2Enable <= aDEnable(i);
end generate;
DataLane3: if i = 3 generate
rbRxDataHS(8 * (i + 1) - 1 downto 8 * i) <= RxDataHSD3;
rbRxValidHS(i) <= RxValidHSD3;
rbRxActiveHS(i) <= RxActiveHSD3;
rbRxSyncHS(i) <= RxSyncHSD3;
aD3Enable <= aDEnable(i);
end generate;
end generate InputDataGen;
MIPI_CSI2_Rx_inst: entity work.MIPI_CSI2_Rx
Generic map(
kTargetDT => kTargetDT,
kDebug => kDebug,
--PPI
kLaneCount => kLaneCount, --[1,2,4]
--Video Format
C_M_AXIS_COMPONENT_WIDTH => C_M_AXIS_COMPONENT_WIDTH, -- [8,10]
C_M_AXIS_TDATA_WIDTH => C_M_AXIS_TDATA_WIDTH,
C_M_MAX_SAMPLES_PER_CLOCK => C_M_MAX_SAMPLES_PER_CLOCK
)
Port map(
--PPI
RxByteClkHS => RxByteClkHS,
aClkStopstate => aClkStopstate,
aRxClkActiveHS => aRxClkActiveHS,
rbRxDataHS => rbRxDataHS,
rbRxSyncHS => rbRxSyncHS,
rbRxValidHS => rbRxValidHS,
rbRxActiveHS => rbRxActiveHS,
aDEnable => aDEnable,
aClkEnable => aClkEnable,
--axi stream signals
m_axis_video_tdata => m_axis_video_tdata,
m_axis_video_tvalid => m_axis_video_tvalid,
m_axis_video_tready => m_axis_video_tready,
m_axis_video_tlast => m_axis_video_tlast,
m_axis_video_tuser => m_axis_video_tuser,
video_aresetn => vRst_n,
video_aclk => video_aclk,
vEnable => vSoftEnable
);
-------------------------------------------------------------------------------
-- AXI-Lite interface for control and status
-------------------------------------------------------------------------------
YesAXILITE: if kGenerateAXIL generate
AXI_Lite_Control: entity work.MIPI_CSI_2_RX_S_AXI_LITE
generic map (
kVersionMajor => kVersionMajor,
kVersionMinor => kVersionMinor,
C_S_AXI_DATA_WIDTH => C_S_AXI_LITE_DATA_WIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_LITE_ADDR_WIDTH
)
port map (
xEnable => xSoftEnable,
xRst => xSoftRst,
S_AXI_ACLK => s_axi_lite_aclk,
S_AXI_ARESETN => s_axi_lite_aresetn,
S_AXI_AWADDR => s_axi_lite_awaddr,
S_AXI_AWPROT => s_axi_lite_awprot,
S_AXI_AWVALID => s_axi_lite_awvalid,
S_AXI_AWREADY => s_axi_lite_awready,
S_AXI_WDATA => s_axi_lite_wdata,
S_AXI_WSTRB => s_axi_lite_wstrb,
S_AXI_WVALID => s_axi_lite_wvalid,
S_AXI_WREADY => s_axi_lite_wready,
S_AXI_BRESP => s_axi_lite_bresp,
S_AXI_BVALID => s_axi_lite_bvalid,
S_AXI_BREADY => s_axi_lite_bready,
S_AXI_ARADDR => s_axi_lite_araddr,
S_AXI_ARPROT => s_axi_lite_arprot,
S_AXI_ARVALID => s_axi_lite_arvalid,
S_AXI_ARREADY => s_axi_lite_arready,
S_AXI_RDATA => s_axi_lite_rdata,
S_AXI_RRESP => s_axi_lite_rresp,
S_AXI_RVALID => s_axi_lite_rvalid,
S_AXI_RREADY => s_axi_lite_rready
);
CoreSoftReset: entity work.ResetBridge
generic map (
kPolarity => '1')
port map (
aRst => xSoftRst,
OutClk => video_aclk,
oRst => vSoftRst);
SyncAsyncClkEnable: entity work.SyncAsync
generic map (
kResetTo => '0',
kStages => 2) --use double FF synchronizer
port map (
aReset => '0', --lane-level enable
aIn => xSoftEnable,
OutClk => video_aclk,
oOut => vSoftEnable);
GlitchFreeReset: process(video_aclk)
begin
if Rising_Edge(video_aclk) then
vRst_n <= video_aresetn and not vSoftRst; --combinational logic can produce glitches
end if;
end process;
end generate;
NoAXILITE: if not kGenerateAXIL generate
vSoftEnable <= '1';
vRst_n <= video_aresetn;
end generate;
end Behavioral;
|
mit
|
nussbrot/code-exchange
|
wb_test/src/vhdl/wbs_test_notify.vhd
|
2
|
24514
|
-------------------------------------------------------------------------------
-- COPYRIGHT (c) SOLECTRIX GmbH, Germany, 2017 All rights reserved
--
-- The copyright to the document(s) herein is the property of SOLECTRIX GmbH
-- The document(s) may be used and/or copied only with the written permission
-- from SOLECTRIX GmbH or in accordance with the terms/conditions stipulated
-- in the agreement/contract under which the document(s) have been supplied
-------------------------------------------------------------------------------
-- Project : glb_lib
-- File : wbs_test_notify.vhd
-- Created : 18.05.2017
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
--*
--* @short Wishbone register module
--* Auto-generated by 'export_wbs.tcl' based on '../../../../sxl/tpl/wb_reg_no_rst_notify.tpl.vhd'
--*
--* Needed Libraries and Packages:
--* @li ieee.std_logic_1164 standard multi-value logic package
--* @li ieee.numeric_std
--*
--* @author rhallmen
--* @date 30.06.2016
--* @internal
--/
-------------------------------------------------------------------------------
-- Modification history :
-- Date Author & Description
-- 18.05.2017 rhallmen: Created
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
-------------------------------------------------------------------------------
ENTITY wbs_test_notify IS
GENERIC (
g_addr_bits : INTEGER := 8);
PORT (
-- Wishbone interface
clk : IN STD_LOGIC;
i_wb_cyc : IN STD_LOGIC;
i_wb_stb : IN STD_LOGIC;
i_wb_we : IN STD_LOGIC;
i_wb_sel : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
i_wb_addr : IN STD_LOGIC_VECTOR(g_addr_bits-1 DOWNTO 0);
i_wb_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
o_wb_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
o_wb_ack : OUT STD_LOGIC;
o_wb_rty : OUT STD_LOGIC;
o_wb_err : OUT STD_LOGIC;
-- Custom ports
o_rw_slice0 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
o_rw_slice1 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
o_rw_bit : OUT STD_LOGIC;
i_ro_slice0 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
i_ro_slice1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
i_ro_bit : IN STD_LOGIC;
o_wo_slice0 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
o_wo_slice1 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
o_wo_bit : OUT STD_LOGIC;
o_tr_slice0 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
o_tr_slice1 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
o_tr_bit : OUT STD_LOGIC;
o_en_bit : OUT STD_LOGIC;
o_en_slice : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
o_no_rw_rw_bit : OUT STD_LOGIC;
o_no_rw_rw_slice : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
i_no_rw_ro_bit : IN STD_LOGIC;
i_no_rw_ro_slice : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
o_no_rw_wo_bit : OUT STD_LOGIC;
o_no_rw_wo_slice : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
o_no_rw_tr_bit : OUT STD_LOGIC;
o_no_rw_tr_slice : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
o_notify_rw_trd : OUT STD_LOGIC;
o_notify_rw_twr : OUT STD_LOGIC;
o_no_ro_rw_bit : OUT STD_LOGIC;
o_no_ro_rw_slice : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
i_no_ro_ro_bit : IN STD_LOGIC;
i_no_ro_ro_slice : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
o_no_ro_wo_bit : OUT STD_LOGIC;
o_no_ro_wo_slice : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
o_no_ro_tr_bit : OUT STD_LOGIC;
o_no_ro_tr_slice : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
o_notify_ro_trd : OUT STD_LOGIC;
o_no_wo_rw_bit : OUT STD_LOGIC;
o_no_wo_rw_slice : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
i_no_wo_ro_bit : IN STD_LOGIC;
i_no_wo_ro_slice : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
o_no_wo_wo_bit : OUT STD_LOGIC;
o_no_wo_wo_slice : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
o_no_wo_tr_bit : OUT STD_LOGIC;
o_no_wo_tr_slice : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
o_notify_wo_twr : OUT STD_LOGIC;
o_const_bit0 : OUT STD_LOGIC;
o_const_bit1 : OUT STD_LOGIC;
o_const_slice0 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
o_const_slice1 : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
);
END ENTITY wbs_test_notify;
-------------------------------------------------------------------------------
ARCHITECTURE rtl OF wbs_test_notify IS
-----------------------------------------------------------------------------
-- Procedures
-----------------------------------------------------------------------------
-- Write access to 32bit register
PROCEDURE set_reg (
i_wr_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
i_wr_en : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
i_wr_mask : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL s_reg : INOUT STD_LOGIC_VECTOR) IS
BEGIN
FOR i IN s_reg'RANGE LOOP
IF (i_wr_mask(i) = '1' AND i_wr_en(i/8) = '1') THEN
s_reg(i) <= i_wr_data(i);
END IF;
END LOOP;
END PROCEDURE set_reg;
-- Write access to single bit register.
-- Since the index is lost, we rely on the mask to set the correct value.
PROCEDURE set_reg (
i_wr_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
i_wr_en : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
i_wr_mask : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL s_reg : INOUT STD_LOGIC) IS
BEGIN
FOR i IN i_wr_mask'RANGE LOOP
IF (i_wr_mask(i) = '1' AND i_wr_en(i/8) = '1') THEN
s_reg <= i_wr_data(i);
END IF;
END LOOP;
END PROCEDURE set_reg;
-- Write access to single trigger signal
PROCEDURE set_trg (
i_wr_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
i_wr_en : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
CONSTANT c_wr_mask : IN NATURAL RANGE 0 TO 31;
SIGNAL s_flag : INOUT STD_LOGIC) IS
BEGIN
IF (i_wr_en(c_wr_mask/8) = '1' AND i_wr_data(c_wr_mask) = '1') THEN
s_flag <= '1';
ELSE
s_flag <= '0';
END IF;
END PROCEDURE set_trg;
-- Write access to trigger signal vector
PROCEDURE set_trg (
i_wr_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
i_wr_en : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
CONSTANT c_wr_mask : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL s_flag : INOUT STD_LOGIC_VECTOR) IS
BEGIN
FOR i IN 0 TO 31 LOOP
IF (c_wr_mask(i) = '1') THEN
IF (i_wr_en(i/8) = '1' AND i_wr_data(i) = '1') THEN
s_flag(i) <= '1';
ELSE
s_flag(i) <= '0';
END IF;
END IF;
END LOOP;
END PROCEDURE set_trg;
-- Drive Trigger On Write signal
PROCEDURE set_twr (
i_wr_en : IN STD_LOGIC;
SIGNAL s_flag : OUT STD_LOGIC) IS
BEGIN -- PROCEDURE set_twr
IF (i_wr_en = '1') THEN
s_flag <= '1';
ELSE
s_flag <= '0';
END IF;
END PROCEDURE set_twr;
-- Drive Trigger On Read signal
PROCEDURE set_trd (
i_rd_en : IN STD_LOGIC;
SIGNAL s_flag : OUT STD_LOGIC) IS
BEGIN -- PROCEDURE set_trd
IF (i_rd_en = '1') THEN
s_flag <= '1';
ELSE
s_flag <= '0';
END IF;
END PROCEDURE set_trd;
-- helper to cast integer to slv
FUNCTION f_reset_cast(number : NATURAL; len : POSITIVE)
RETURN STD_LOGIC_VECTOR IS
BEGIN
RETURN STD_LOGIC_VECTOR(to_unsigned(number, len));
END FUNCTION f_reset_cast;
-----------------------------------------------------------------------------
-- Constants
-----------------------------------------------------------------------------
CONSTANT c_addr_read_write : INTEGER := 16#0000#;
CONSTANT c_addr_read_only : INTEGER := 16#0004#;
CONSTANT c_addr_write_only : INTEGER := 16#0008#;
CONSTANT c_addr_trigger : INTEGER := 16#000C#;
CONSTANT c_addr_enum : INTEGER := 16#0010#;
CONSTANT c_addr_notify_rw : INTEGER := 16#0014#;
CONSTANT c_addr_notify_ro : INTEGER := 16#0018#;
CONSTANT c_addr_notify_wo : INTEGER := 16#001C#;
CONSTANT c_addr_const : INTEGER := 16#0020#;
CONSTANT c_has_read_notifies : BOOLEAN := TRUE;
-----------------------------------------------------------------------------
-- WB interface signals
-----------------------------------------------------------------------------
SIGNAL s_wb_ack : STD_LOGIC;
SIGNAL s_wb_err : STD_LOGIC;
SIGNAL s_wb_addr : UNSIGNED(i_wb_addr'HIGH DOWNTO 0);
SIGNAL s_int_addr : UNSIGNED(i_wb_addr'HIGH DOWNTO 0);
SIGNAL s_int_data : STD_LOGIC_VECTOR(i_wb_data'RANGE);
SIGNAL s_int_we : STD_LOGIC_VECTOR(i_wb_sel'RANGE);
SIGNAL s_int_trd : STD_LOGIC;
SIGNAL s_int_twr : STD_LOGIC;
SIGNAL s_int_addr_valid : STD_LOGIC;
SIGNAL s_int_data_rb : STD_LOGIC_VECTOR(i_wb_data'RANGE);
SIGNAL s_wb_data : STD_LOGIC_VECTOR(o_wb_data'RANGE);
TYPE t_wb_state IS (e_idle, e_delay, e_ack);
SIGNAL s_wb_state : t_wb_state := e_idle;
-----------------------------------------------------------------------------
-- Custom registers
-----------------------------------------------------------------------------
SIGNAL s_rw_rw_slice0 : STD_LOGIC_VECTOR(31 DOWNTO 16) := f_reset_cast(0, 16);
SIGNAL s_rw_rw_slice1 : STD_LOGIC_VECTOR(15 DOWNTO 8) := f_reset_cast(0, 8);
SIGNAL s_rw_rw_bit : STD_LOGIC := '0';
SIGNAL s_wo_wo_slice0 : STD_LOGIC_VECTOR(31 DOWNTO 16) := f_reset_cast(0, 16);
SIGNAL s_wo_wo_slice1 : STD_LOGIC_VECTOR(15 DOWNTO 8) := f_reset_cast(0, 8);
SIGNAL s_wo_wo_bit : STD_LOGIC := '0';
SIGNAL s_trg_tr_slice0 : STD_LOGIC_VECTOR(31 DOWNTO 16) := f_reset_cast(0, 16);
SIGNAL s_trg_tr_slice1 : STD_LOGIC_VECTOR(15 DOWNTO 8) := f_reset_cast(0, 8);
SIGNAL s_trg_tr_bit : STD_LOGIC := '0';
SIGNAL s_rw_en_bit : STD_LOGIC := '1';
SIGNAL s_rw_en_slice : STD_LOGIC_VECTOR(13 DOWNTO 12) := f_reset_cast(2, 2);
SIGNAL s_rw_no_rw_rw_bit : STD_LOGIC := '0';
SIGNAL s_rw_no_rw_rw_slice : STD_LOGIC_VECTOR(30 DOWNTO 24) := f_reset_cast(111, 7);
SIGNAL s_wo_no_rw_wo_bit : STD_LOGIC := '0';
SIGNAL s_wo_no_rw_wo_slice : STD_LOGIC_VECTOR(14 DOWNTO 8) := f_reset_cast(111, 7);
SIGNAL s_trg_no_rw_tr_bit : STD_LOGIC := '0';
SIGNAL s_trg_no_rw_tr_slice : STD_LOGIC_VECTOR(6 DOWNTO 0) := f_reset_cast(111, 7);
SIGNAL s_rw_no_ro_rw_bit : STD_LOGIC := '0';
SIGNAL s_rw_no_ro_rw_slice : STD_LOGIC_VECTOR(30 DOWNTO 24) := f_reset_cast(111, 7);
SIGNAL s_wo_no_ro_wo_bit : STD_LOGIC := '0';
SIGNAL s_wo_no_ro_wo_slice : STD_LOGIC_VECTOR(14 DOWNTO 8) := f_reset_cast(111, 7);
SIGNAL s_trg_no_ro_tr_bit : STD_LOGIC := '0';
SIGNAL s_trg_no_ro_tr_slice : STD_LOGIC_VECTOR(6 DOWNTO 0) := f_reset_cast(111, 7);
SIGNAL s_rw_no_wo_rw_bit : STD_LOGIC := '0';
SIGNAL s_rw_no_wo_rw_slice : STD_LOGIC_VECTOR(30 DOWNTO 24) := f_reset_cast(111, 7);
SIGNAL s_wo_no_wo_wo_bit : STD_LOGIC := '0';
SIGNAL s_wo_no_wo_wo_slice : STD_LOGIC_VECTOR(14 DOWNTO 8) := f_reset_cast(111, 7);
SIGNAL s_trg_no_wo_tr_bit : STD_LOGIC := '0';
SIGNAL s_trg_no_wo_tr_slice : STD_LOGIC_VECTOR(6 DOWNTO 0) := f_reset_cast(111, 7);
SIGNAL s_const_const_bit0 : STD_LOGIC := '1';
SIGNAL s_const_const_bit1 : STD_LOGIC := '0';
SIGNAL s_const_const_slice0 : STD_LOGIC_VECTOR(31 DOWNTO 24) := f_reset_cast(113, 8);
SIGNAL s_const_const_slice1 : STD_LOGIC_VECTOR(13 DOWNTO 9) := f_reset_cast(17, 5);
BEGIN -- ARCHITECTURE rtl
-----------------------------------------------------------------------------
--* purpose : Wishbone Bus Control
--* type : sequential, rising edge, no reset
wb_ctrl : PROCESS (clk)
BEGIN
IF rising_edge(clk) THEN
s_wb_ack <= '0';
s_wb_err <= '0';
s_int_data <= i_wb_data;
s_int_addr <= s_wb_addr;
s_int_we <= (OTHERS => '0');
s_int_trd <= '0';
s_int_twr <= '0';
CASE s_wb_state IS
WHEN e_idle =>
-- check if anyone requests access
IF (i_wb_cyc = '1' AND i_wb_stb = '1') THEN
-- ack is delayed because we need 3 cycles
IF (i_wb_we = '1') THEN
s_wb_ack <= s_int_addr_valid;
s_wb_err <= NOT s_int_addr_valid;
s_wb_state <= e_ack;
s_int_we <= i_wb_sel;
s_int_twr <= '1';
ELSE
IF c_has_read_notifies THEN
s_wb_state <= e_delay;
s_int_trd <= '1';
ELSE
s_wb_ack <= s_int_addr_valid;
s_wb_err <= NOT s_int_addr_valid;
s_wb_state <= e_ack;
END IF;
END IF;
END IF;
WHEN e_delay =>
s_wb_ack <= s_int_addr_valid;
s_wb_err <= NOT s_int_addr_valid;
s_wb_state <= e_ack;
WHEN e_ack =>
s_wb_state <= e_idle;
END CASE;
s_wb_data <= s_int_data_rb;
END IF;
END PROCESS wb_ctrl;
s_wb_addr <= UNSIGNED(i_wb_addr);
o_wb_data <= s_wb_data;
o_wb_ack <= s_wb_ack;
o_wb_err <= s_wb_err;
o_wb_rty <= '0';
-----------------------------------------------------------------------------
-- WB address validation
WITH to_integer(s_wb_addr) SELECT
s_int_addr_valid <=
'1' WHEN c_addr_read_write,
'1' WHEN c_addr_read_only,
'1' WHEN c_addr_write_only,
'1' WHEN c_addr_trigger,
'1' WHEN c_addr_enum,
'1' WHEN c_addr_notify_rw,
'1' WHEN c_addr_notify_ro,
'1' WHEN c_addr_notify_wo,
'1' WHEN c_addr_const,
'0' WHEN OTHERS;
-----------------------------------------------------------------------------
--* purpose : register access
--* type : sequential, rising edge, high active synchronous reset
reg_access : PROCESS (clk)
BEGIN -- PROCESS reg_access
IF rising_edge(clk) THEN
-- default values / clear trigger signals
s_trg_tr_slice0 <= (OTHERS => '0');
s_trg_tr_slice1 <= (OTHERS => '0');
s_trg_tr_bit <= '0';
s_trg_no_rw_tr_bit <= '0';
s_trg_no_rw_tr_slice <= (OTHERS => '0');
s_trg_no_ro_tr_bit <= '0';
s_trg_no_ro_tr_slice <= (OTHERS => '0');
s_trg_no_wo_tr_bit <= '0';
s_trg_no_wo_tr_slice <= (OTHERS => '0');
o_notify_rw_trd <= '0';
o_notify_rw_twr <= '0';
o_notify_ro_trd <= '0';
o_notify_wo_twr <= '0';
-- WRITE registers
CASE to_integer(s_int_addr) IS
WHEN c_addr_read_write => set_reg(s_int_data, s_int_we, x"FFFF0000", s_rw_rw_slice0);
set_reg(s_int_data, s_int_we, x"0000FF00", s_rw_rw_slice1);
set_reg(s_int_data, s_int_we, x"00000008", s_rw_rw_bit);
WHEN c_addr_write_only => set_reg(s_int_data, s_int_we, x"FFFF0000", s_wo_wo_slice0);
set_reg(s_int_data, s_int_we, x"0000FF00", s_wo_wo_slice1);
set_reg(s_int_data, s_int_we, x"00000008", s_wo_wo_bit);
WHEN c_addr_trigger => set_trg(s_int_data, s_int_we, x"FFFF0000", s_trg_tr_slice0);
set_trg(s_int_data, s_int_we, x"0000FF00", s_trg_tr_slice1);
set_trg(s_int_data, s_int_we, 3, s_trg_tr_bit);
WHEN c_addr_enum => set_reg(s_int_data, s_int_we, x"80000000", s_rw_en_bit);
set_reg(s_int_data, s_int_we, x"00003000", s_rw_en_slice);
WHEN c_addr_notify_rw => set_reg(s_int_data, s_int_we, x"80000000", s_rw_no_rw_rw_bit);
set_reg(s_int_data, s_int_we, x"7F000000", s_rw_no_rw_rw_slice);
set_reg(s_int_data, s_int_we, x"00008000", s_wo_no_rw_wo_bit);
set_reg(s_int_data, s_int_we, x"00007F00", s_wo_no_rw_wo_slice);
set_trg(s_int_data, s_int_we, 7, s_trg_no_rw_tr_bit);
set_trg(s_int_data, s_int_we, x"0000007F", s_trg_no_rw_tr_slice);
set_trd(s_int_trd, o_notify_rw_trd);
set_twr(s_int_twr, o_notify_rw_twr);
WHEN c_addr_notify_ro => set_reg(s_int_data, s_int_we, x"80000000", s_rw_no_ro_rw_bit);
set_reg(s_int_data, s_int_we, x"7F000000", s_rw_no_ro_rw_slice);
set_reg(s_int_data, s_int_we, x"00008000", s_wo_no_ro_wo_bit);
set_reg(s_int_data, s_int_we, x"00007F00", s_wo_no_ro_wo_slice);
set_trg(s_int_data, s_int_we, 7, s_trg_no_ro_tr_bit);
set_trg(s_int_data, s_int_we, x"0000007F", s_trg_no_ro_tr_slice);
set_trd(s_int_trd, o_notify_ro_trd);
WHEN c_addr_notify_wo => set_reg(s_int_data, s_int_we, x"80000000", s_rw_no_wo_rw_bit);
set_reg(s_int_data, s_int_we, x"7F000000", s_rw_no_wo_rw_slice);
set_reg(s_int_data, s_int_we, x"00008000", s_wo_no_wo_wo_bit);
set_reg(s_int_data, s_int_we, x"00007F00", s_wo_no_wo_wo_slice);
set_trg(s_int_data, s_int_we, 7, s_trg_no_wo_tr_bit);
set_trg(s_int_data, s_int_we, x"0000007F", s_trg_no_wo_tr_slice);
set_twr(s_int_twr, o_notify_wo_twr);
WHEN OTHERS => NULL;
END CASE;
END IF;
END PROCESS reg_access;
-----------------------------------------------------------------------------
p_comb_read_mux : PROCESS(s_wb_addr, s_rw_rw_slice0, s_rw_rw_slice1, s_rw_rw_bit, i_ro_slice0, i_ro_slice1, i_ro_bit, s_rw_en_bit, s_rw_en_slice, s_rw_no_rw_rw_bit, s_rw_no_rw_rw_slice, i_no_rw_ro_bit, i_no_rw_ro_slice, s_rw_no_ro_rw_bit, s_rw_no_ro_rw_slice, i_no_ro_ro_bit, i_no_ro_ro_slice, s_rw_no_wo_rw_bit, s_rw_no_wo_rw_slice, i_no_wo_ro_bit, i_no_wo_ro_slice)
VARIABLE v_tmp_read_write : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
VARIABLE v_tmp_read_only : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
VARIABLE v_tmp_enum : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
VARIABLE v_tmp_notify_rw : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
VARIABLE v_tmp_notify_ro : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
VARIABLE v_tmp_notify_wo : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
VARIABLE v_tmp_const : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
-- helper to ease template generation
PROCEDURE set(
l_input : STD_LOGIC_VECTOR(31 DOWNTO 0);
l_mask : STD_LOGIC_VECTOR(31 DOWNTO 0)) IS
BEGIN
s_int_data_rb <= l_input AND l_mask;
END PROCEDURE;
BEGIN
-- READ registers assignments
v_tmp_read_write(31 DOWNTO 16) := s_rw_rw_slice0;
v_tmp_read_write(15 DOWNTO 8) := s_rw_rw_slice1;
v_tmp_read_write(3) := s_rw_rw_bit;
v_tmp_read_only(31 DOWNTO 16) := i_ro_slice0;
v_tmp_read_only(15 DOWNTO 8) := i_ro_slice1;
v_tmp_read_only(3) := i_ro_bit;
v_tmp_enum(31) := s_rw_en_bit;
v_tmp_enum(13 DOWNTO 12) := s_rw_en_slice;
v_tmp_notify_rw(31) := s_rw_no_rw_rw_bit;
v_tmp_notify_rw(30 DOWNTO 24) := s_rw_no_rw_rw_slice;
v_tmp_notify_rw(23) := i_no_rw_ro_bit;
v_tmp_notify_rw(22 DOWNTO 16) := i_no_rw_ro_slice;
v_tmp_notify_ro(31) := s_rw_no_ro_rw_bit;
v_tmp_notify_ro(30 DOWNTO 24) := s_rw_no_ro_rw_slice;
v_tmp_notify_ro(23) := i_no_ro_ro_bit;
v_tmp_notify_ro(22 DOWNTO 16) := i_no_ro_ro_slice;
v_tmp_notify_wo(31) := s_rw_no_wo_rw_bit;
v_tmp_notify_wo(30 DOWNTO 24) := s_rw_no_wo_rw_slice;
v_tmp_notify_wo(23) := i_no_wo_ro_bit;
v_tmp_notify_wo(22 DOWNTO 16) := i_no_wo_ro_slice;
v_tmp_const(7) := s_const_const_bit0;
v_tmp_const(6) := s_const_const_bit1;
v_tmp_const(31 DOWNTO 24) := s_const_const_slice0;
v_tmp_const(13 DOWNTO 9) := s_const_const_slice1;
-- WB output data multiplexer
CASE to_integer(s_wb_addr) IS
WHEN c_addr_read_write => set(v_tmp_read_write, x"FFFFFF08");
WHEN c_addr_read_only => set(v_tmp_read_only, x"FFFFFF08");
WHEN c_addr_enum => set(v_tmp_enum, x"80003000");
WHEN c_addr_notify_rw => set(v_tmp_notify_rw, x"FFFF0000");
WHEN c_addr_notify_ro => set(v_tmp_notify_ro, x"FFFF0000");
WHEN c_addr_notify_wo => set(v_tmp_notify_wo, x"FFFF0000");
WHEN c_addr_const => set(v_tmp_const, x"FF003EC0");
WHEN OTHERS => set((OTHERS => '0'), (OTHERS => '1'));
END CASE;
END PROCESS p_comb_read_mux;
-----------------------------------------------------------------------------
-- output mappings
o_rw_slice0 <= s_rw_rw_slice0(31 DOWNTO 16);
o_rw_slice1 <= s_rw_rw_slice1(15 DOWNTO 8);
o_rw_bit <= s_rw_rw_bit;
o_wo_slice0 <= s_wo_wo_slice0(31 DOWNTO 16);
o_wo_slice1 <= s_wo_wo_slice1(15 DOWNTO 8);
o_wo_bit <= s_wo_wo_bit;
o_tr_slice0 <= s_trg_tr_slice0(31 DOWNTO 16);
o_tr_slice1 <= s_trg_tr_slice1(15 DOWNTO 8);
o_tr_bit <= s_trg_tr_bit;
o_en_bit <= s_rw_en_bit;
o_en_slice <= s_rw_en_slice(13 DOWNTO 12);
o_no_rw_rw_bit <= s_rw_no_rw_rw_bit;
o_no_rw_rw_slice <= s_rw_no_rw_rw_slice(30 DOWNTO 24);
o_no_rw_wo_bit <= s_wo_no_rw_wo_bit;
o_no_rw_wo_slice <= s_wo_no_rw_wo_slice(14 DOWNTO 8);
o_no_rw_tr_bit <= s_trg_no_rw_tr_bit;
o_no_rw_tr_slice <= s_trg_no_rw_tr_slice(6 DOWNTO 0);
o_no_ro_rw_bit <= s_rw_no_ro_rw_bit;
o_no_ro_rw_slice <= s_rw_no_ro_rw_slice(30 DOWNTO 24);
o_no_ro_wo_bit <= s_wo_no_ro_wo_bit;
o_no_ro_wo_slice <= s_wo_no_ro_wo_slice(14 DOWNTO 8);
o_no_ro_tr_bit <= s_trg_no_ro_tr_bit;
o_no_ro_tr_slice <= s_trg_no_ro_tr_slice(6 DOWNTO 0);
o_no_wo_rw_bit <= s_rw_no_wo_rw_bit;
o_no_wo_rw_slice <= s_rw_no_wo_rw_slice(30 DOWNTO 24);
o_no_wo_wo_bit <= s_wo_no_wo_wo_bit;
o_no_wo_wo_slice <= s_wo_no_wo_wo_slice(14 DOWNTO 8);
o_no_wo_tr_bit <= s_trg_no_wo_tr_bit;
o_no_wo_tr_slice <= s_trg_no_wo_tr_slice(6 DOWNTO 0);
o_const_bit0 <= s_const_const_bit0;
o_const_bit1 <= s_const_const_bit1;
o_const_slice0 <= s_const_const_slice0(31 DOWNTO 24);
o_const_slice1 <= s_const_const_slice1(13 DOWNTO 9);
END ARCHITECTURE rtl;
|
mit
|
YingcaiDong/Shunting-Model-Based-Path-Planning-Algorithm-Accelerator-Using-FPGA
|
System Design Source FIle/ipshared/xilinx.com/axi_datamover_v5_1/3acd8cae/hdl/src/vhdl/axi_datamover_mm2s_full_wrap.vhd
|
5
|
70765
|
-------------------------------------------------------------------------------
-- axi_datamover_mm2s_full_wrap.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_mm2s_full_wrap.vhd
--
-- Description:
-- This file implements the DataMover MM2S Full Wrapper.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-- axi_datamover Library Modules
library axi_datamover_v5_1;
use axi_datamover_v5_1.axi_datamover_reset;
use axi_datamover_v5_1.axi_datamover_cmd_status;
use axi_datamover_v5_1.axi_datamover_pcc;
use axi_datamover_v5_1.axi_datamover_addr_cntl;
use axi_datamover_v5_1.axi_datamover_rddata_cntl;
use axi_datamover_v5_1.axi_datamover_rd_status_cntl;
use axi_datamover_v5_1.axi_datamover_mm2s_dre;
Use axi_datamover_v5_1.axi_datamover_rd_sf;
use axi_datamover_v5_1.axi_datamover_skid_buf;
-------------------------------------------------------------------------------
entity axi_datamover_mm2s_full_wrap is
generic (
C_INCLUDE_MM2S : Integer range 0 to 2 := 1;
-- Specifies the type of MM2S function to include
-- 0 = Omit MM2S functionality
-- 1 = Full MM2S Functionality
-- 2 = Lite MM2S functionality
C_MM2S_ARID : Integer range 0 to 255 := 8;
-- Specifies the constant value to output on
-- the ARID output port
C_MM2S_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the MM2S ID port
C_MM2S_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_MM2S_MDATA_WIDTH : Integer range 32 to 1024 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_MM2S_SDATA_WIDTH : Integer range 8 to 1024 := 32;
-- Specifies the width of the MM2S Master Stream Data
-- Channel data bus
C_INCLUDE_MM2S_STSFIFO : Integer range 0 to 1 := 1;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit MM2S Status FIFO
-- 1 = Include MM2S Status FIFO
C_MM2S_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4;
-- Specifies the depth of the MM2S Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_MM2S_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_MM2S_DRE : Integer range 0 to 1 := 0;
-- Specifies if DRE is to be included in the MM2S function
-- 0 = Omit DRE
-- 1 = Include DRE
C_MM2S_BURST_SIZE : Integer range 2 to 256 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the MM2S function
C_MM2S_BTT_USED : Integer range 8 to 23 := 16;
-- Specifies the number of bits used from the BTT field
-- of the input Command Word of the MM2S Command Interface
C_MM2S_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 3;
-- This parameter specifies the depth of the MM2S internal
-- child command queues in the Read Address Controller and
-- the Read Data Controller. Increasing this value will
-- allow more Read Addresses to be issued to the AXI4 Read
-- Address Channel before receipt of the associated read
-- data on the Read Data Channel.
C_TAG_WIDTH : Integer range 1 to 8 := 4 ;
-- Width of the TAG field
C_INCLUDE_MM2S_GP_SF : Integer range 0 to 1 := 1 ;
-- This parameter specifies the incllusion/omission of the
-- MM2S (Read) Store and Forward function
-- 0 = Omit Store and Forward
-- 1 = Include Store and Forward
C_ENABLE_CACHE_USER : Integer range 0 to 1 := 1;
C_ENABLE_MM2S_TKEEP : integer range 0 to 1 := 1;
C_ENABLE_SKID_BUF : string := "11111";
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA family type
);
port (
-- MM2S Primary Clock input ---------------------------------
mm2s_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- MM2S Primary Reset input --
mm2s_aresetn : in std_logic; --
-- Reset used for the internal master logic --
-------------------------------------------------------------
-- MM2S Halt request input control --------------------------
mm2s_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- MM2S Halt Complete status flag --
mm2s_halt_cmplt : Out std_logic; --
-- Active high soft shutdown complete status --
-------------------------------------------------------------
-- Error discrete output ------------------------------------
mm2s_err : Out std_logic; --
-- Composite Error indication --
-------------------------------------------------------------
-- Optional MM2S Command and Status Clock and Reset ---------
-- Used when C_MM2S_STSCMD_IS_ASYNC = 1 --
mm2s_cmdsts_awclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
mm2s_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
-------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) ----------------------------------------------------
mm2s_cmd_wvalid : in std_logic; --
mm2s_cmd_wready : out std_logic; --
mm2s_cmd_wdata : in std_logic_vector((C_TAG_WIDTH+(8*C_ENABLE_CACHE_USER)+C_MM2S_ADDR_WIDTH+36)-1 downto 0); --
-------------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) -------------------
mm2s_sts_wvalid : out std_logic; --
mm2s_sts_wready : in std_logic; --
mm2s_sts_wdata : out std_logic_vector(7 downto 0); --
mm2s_sts_wstrb : out std_logic_vector(0 downto 0); --
mm2s_sts_wlast : out std_logic; --
---------------------------------------------------------------
-- Address Posting contols ------------------------------------
mm2s_allow_addr_req : in std_logic; --
mm2s_addr_req_posted : out std_logic; --
mm2s_rd_xfer_cmplt : out std_logic; --
---------------------------------------------------------------
-- MM2S AXI Address Channel I/O ---------------------------------------
mm2s_arid : out std_logic_vector(C_MM2S_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
mm2s_araddr : out std_logic_vector(C_MM2S_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
mm2s_arlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
mm2s_arsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
mm2s_arburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
mm2s_arprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
mm2s_arcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel CACHE output --
mm2s_aruser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel CACHE output --
--
mm2s_arvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
mm2s_arready : in std_logic; --
-- AXI Address Channel READY input --
------------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals ------------
-- addr2axi_alock : out std_logic_vector(2 downto 0); --
-- addr2axi_acache : out std_logic_vector(4 downto 0); --
-- addr2axi_aqos : out std_logic_vector(3 downto 0); --
-- addr2axi_aregion : out std_logic_vector(3 downto 0); --
------------------------------------------------------------------------
-- MM2S AXI MMap Read Data Channel I/O -----------------------------------------
mm2s_rdata : In std_logic_vector(C_MM2S_MDATA_WIDTH-1 downto 0); --
mm2s_rresp : In std_logic_vector(1 downto 0); --
mm2s_rlast : In std_logic; --
mm2s_rvalid : In std_logic; --
mm2s_rready : Out std_logic; --
---------------------------------------------------------------------------------
-- MM2S AXI Master Stream Channel I/O -------------------------------------------------
mm2s_strm_wdata : Out std_logic_vector(C_MM2S_SDATA_WIDTH-1 downto 0); --
mm2s_strm_wstrb : Out std_logic_vector((C_MM2S_SDATA_WIDTH/8)-1 downto 0); --
mm2s_strm_wlast : Out std_logic; --
mm2s_strm_wvalid : Out std_logic; --
mm2s_strm_wready : In std_logic; --
----------------------------------------------------------------------------------------
-- Testing Support I/O -------------------------------------------
mm2s_dbg_sel : in std_logic_vector( 3 downto 0); --
mm2s_dbg_data : out std_logic_vector(31 downto 0) --
------------------------------------------------------------------
);
end entity axi_datamover_mm2s_full_wrap;
architecture implementation of axi_datamover_mm2s_full_wrap is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function Declarations ----------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_calc_rdmux_sel_bits
--
-- Function Description:
-- This function calculates the number of address bits needed for
-- the Read data mux select control.
--
-------------------------------------------------------------------
function func_calc_rdmux_sel_bits (mmap_dwidth_value : integer) return integer is
Variable num_addr_bits_needed : Integer range 1 to 7 := 1;
begin
case mmap_dwidth_value is
when 32 =>
num_addr_bits_needed := 2;
when 64 =>
num_addr_bits_needed := 3;
when 128 =>
num_addr_bits_needed := 4;
when 256 =>
num_addr_bits_needed := 5;
when 512 =>
num_addr_bits_needed := 6;
when others => -- 1024 bits
num_addr_bits_needed := 7;
end case;
Return (num_addr_bits_needed);
end function func_calc_rdmux_sel_bits;
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_include_dre
--
-- Function Description:
-- This function desides if conditions are right for allowing DRE
-- inclusion.
--
-------------------------------------------------------------------
function func_include_dre (need_dre : integer;
needed_data_width : integer) return integer is
Variable include_dre : Integer := 0;
begin
If (need_dre = 1 and
needed_data_width < 128 and
needed_data_width > 8) Then
include_dre := 1;
Else
include_dre := 0;
End if;
Return (include_dre);
end function func_include_dre;
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_get_align_width
--
-- Function Description:
-- This function calculates the needed DRE alignment port width\
-- based upon the inclusion of DRE and the needed bit width of the
-- DRE.
--
-------------------------------------------------------------------
function func_get_align_width (dre_included : integer;
dre_data_width : integer) return integer is
Variable align_port_width : Integer := 1;
begin
if (dre_included = 1) then
If (dre_data_width = 64) Then
align_port_width := 3;
Elsif (dre_data_width = 32) Then
align_port_width := 2;
else -- 16 bit data width
align_port_width := 1;
End if;
else -- no DRE
align_port_width := 1;
end if;
Return (align_port_width);
end function func_get_align_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_rnd2pwr_of_2
--
-- Function Description:
-- Rounds the input value up to the nearest power of 2 between
-- 128 and 8192.
--
-------------------------------------------------------------------
function funct_rnd2pwr_of_2 (input_value : integer) return integer is
Variable temp_pwr2 : Integer := 128;
begin
if (input_value <= 128) then
temp_pwr2 := 128;
elsif (input_value <= 256) then
temp_pwr2 := 256;
elsif (input_value <= 512) then
temp_pwr2 := 512;
elsif (input_value <= 1024) then
temp_pwr2 := 1024;
elsif (input_value <= 2048) then
temp_pwr2 := 2048;
elsif (input_value <= 4096) then
temp_pwr2 := 4096;
else
temp_pwr2 := 8192;
end if;
Return (temp_pwr2);
end function funct_rnd2pwr_of_2;
-------------------------------------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_sf_offset_width
--
-- Function Description:
-- This function calculates the address offset width needed by
-- the GP Store and Forward module with data packing.
--
-------------------------------------------------------------------
function funct_get_sf_offset_width (mmap_dwidth : integer;
stream_dwidth : integer) return integer is
Constant FCONST_WIDTH_RATIO : integer := mmap_dwidth/stream_dwidth;
Variable fvar_temp_offset_width : Integer := 1;
begin
case FCONST_WIDTH_RATIO is
when 1 =>
fvar_temp_offset_width := 1;
when 2 =>
fvar_temp_offset_width := 1;
when 4 =>
fvar_temp_offset_width := 2;
when 8 =>
fvar_temp_offset_width := 3;
when 16 =>
fvar_temp_offset_width := 4;
when 32 =>
fvar_temp_offset_width := 5;
when 64 =>
fvar_temp_offset_width := 6;
when others => -- 128 ratio
fvar_temp_offset_width := 7;
end case;
Return (fvar_temp_offset_width);
end function funct_get_sf_offset_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_stream_width2use
--
-- Function Description:
-- This function calculates the Stream width to use for MM2S
-- modules upstream from the downsizing Store and Forward. If
-- Store and Forward is present, then the effective native width
-- is the MMAP data width. If no Store and Forward then the Stream
-- width is the input Native Data width from the User.
--
-------------------------------------------------------------------
function funct_get_stream_width2use (mmap_data_width : integer;
stream_data_width : integer;
sf_enabled : integer) return integer is
Variable fvar_temp_width : Integer := 32;
begin
If (sf_enabled = 1) Then
fvar_temp_width := mmap_data_width;
Else
fvar_temp_width := stream_data_width;
End if;
Return (fvar_temp_width);
end function funct_get_stream_width2use;
-- Constant Declarations ----------------------------------------
Constant SF_UPSIZED_SDATA_WIDTH : integer := funct_get_stream_width2use(C_MM2S_MDATA_WIDTH,
C_MM2S_SDATA_WIDTH,
C_INCLUDE_MM2S_GP_SF);
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant INCLUDE_MM2S : integer range 0 to 2 := C_INCLUDE_MM2S;
Constant IS_MM2S : integer range 0 to 1 := 1;
Constant MM2S_ARID_VALUE : integer range 0 to 255 := C_MM2S_ARID;
Constant MM2S_ARID_WIDTH : integer range 1 to 8 := C_MM2S_ID_WIDTH;
Constant MM2S_ADDR_WIDTH : integer range 32 to 64 := C_MM2S_ADDR_WIDTH;
Constant MM2S_MDATA_WIDTH : integer range 32 to 1024 := C_MM2S_MDATA_WIDTH;
Constant MM2S_SDATA_WIDTH : integer range 8 to 1024 := C_MM2S_SDATA_WIDTH;
Constant MM2S_TAG_WIDTH : integer range 1 to 8 := C_TAG_WIDTH;
Constant MM2S_CMD_WIDTH : integer := (MM2S_TAG_WIDTH+C_MM2S_ADDR_WIDTH+32);
Constant MM2S_STS_WIDTH : integer := 8; -- always 8 for MM2S
Constant INCLUDE_MM2S_STSFIFO : integer range 0 to 1 := C_INCLUDE_MM2S_STSFIFO;
Constant MM2S_STSCMD_FIFO_DEPTH : integer range 1 to 16 := C_MM2S_STSCMD_FIFO_DEPTH;
Constant MM2S_STSCMD_IS_ASYNC : integer range 0 to 1 := C_MM2S_STSCMD_IS_ASYNC;
Constant INCLUDE_MM2S_DRE : integer range 0 to 1 := C_INCLUDE_MM2S_DRE;
Constant MM2S_BURST_SIZE : integer range 2 to 256 := C_MM2S_BURST_SIZE;
Constant ADDR_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_MM2S_ADDR_PIPE_DEPTH;
Constant RD_DATA_CNTL_FIFO_DEPTH : integer range 1 to 30 := ADDR_CNTL_FIFO_DEPTH;
Constant SEL_ADDR_WIDTH : integer range 2 to 7 := func_calc_rdmux_sel_bits(MM2S_MDATA_WIDTH);
Constant MM2S_BTT_USED : integer range 8 to 23 := C_MM2S_BTT_USED;
Constant NO_INDET_BTT : integer range 0 to 1 := 0;
Constant INCLUDE_DRE : integer range 0 to 1 := func_include_dre(C_INCLUDE_MM2S_DRE,
C_MM2S_SDATA_WIDTH);
Constant DRE_ALIGN_WIDTH : integer range 1 to 3 := func_get_align_width(INCLUDE_DRE,
C_MM2S_SDATA_WIDTH);
-- Calculates the minimum needed depth of the Store and Forward FIFO
-- based on the MM2S pipeline depth and the max allowed Burst length
Constant PIPEDEPTH_BURST_LEN_PROD : integer :=
(ADDR_CNTL_FIFO_DEPTH+2) * MM2S_BURST_SIZE;
-- Assigns the depth of the optional Store and Forward FIFO to the nearest
-- power of 2
Constant SF_FIFO_DEPTH : integer range 128 to 8192 :=
funct_rnd2pwr_of_2(PIPEDEPTH_BURST_LEN_PROD);
-- Calculate the width of the Store and Forward Starting Address Offset bus
Constant SF_STRT_OFFSET_WIDTH : integer := funct_get_sf_offset_width(MM2S_MDATA_WIDTH,
MM2S_SDATA_WIDTH);
-- Signal Declarations ------------------------------------------
signal sig_cmd_stat_rst_user : std_logic := '0';
signal sig_cmd_stat_rst_int : std_logic := '0';
signal sig_mmap_rst : std_logic := '0';
signal sig_stream_rst : std_logic := '0';
signal sig_mm2s_cmd_wdata : std_logic_vector(MM2S_CMD_WIDTH-1 downto 0) := (others => '0');
signal sig_cache_data : std_logic_vector(7 downto 0) := (others => '0');
signal sig_cmd2mstr_command : std_logic_vector(MM2S_CMD_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd2mstr_cmd_valid : std_logic := '0';
signal sig_mst2cmd_cmd_ready : std_logic := '0';
signal sig_mstr2addr_addr : std_logic_vector(MM2S_ADDR_WIDTH-1 downto 0) := (others => '0');
signal first_addr : std_logic_vector(MM2S_ADDR_WIDTH-1 downto 0) := (others => '0');
signal last_addr : std_logic_vector(MM2S_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2addr_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_mstr2addr_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_mstr2addr_burst : std_logic_vector(1 downto 0) := (others => '0');
signal sig_mstr2addr_cache : std_logic_vector(3 downto 0) := (others => '0');
signal sig_mstr2addr_user : std_logic_vector(3 downto 0) := (others => '0');
signal sig_mstr2addr_cmd_cmplt : std_logic := '0';
signal sig_mstr2addr_calc_error : std_logic := '0';
signal sig_mstr2addr_cmd_valid : std_logic := '0';
signal sig_addr2mstr_cmd_ready : std_logic := '0';
signal sig_mstr2data_saddr_lsb : std_logic_vector(SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2data_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_mstr2data_strt_strb : std_logic_vector((SF_UPSIZED_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mstr2data_last_strb : std_logic_vector((SF_UPSIZED_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mstr2data_drr : std_logic := '0';
signal sig_mstr2data_eof : std_logic := '0';
signal sig_mstr2data_sequential : std_logic := '0';
signal sig_mstr2data_calc_error : std_logic := '0';
signal sig_mstr2data_cmd_cmplt : std_logic := '0';
signal sig_mstr2data_cmd_valid : std_logic := '0';
signal sig_data2mstr_cmd_ready : std_logic := '0';
signal sig_mstr2data_dre_src_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2data_dre_dest_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_addr2data_addr_posted : std_logic := '0';
signal sig_data2all_dcntlr_halted : std_logic := '0';
signal sig_addr2rsc_calc_error : std_logic := '0';
signal sig_addr2rsc_cmd_fifo_empty : std_logic := '0';
signal sig_data2rsc_tag : std_logic_vector(MM2S_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_data2rsc_calc_err : std_logic := '0';
signal sig_data2rsc_okay : std_logic := '0';
signal sig_data2rsc_decerr : std_logic := '0';
signal sig_data2rsc_slverr : std_logic := '0';
signal sig_data2rsc_cmd_cmplt : std_logic := '0';
signal sig_rsc2data_ready : std_logic := '0';
signal sig_data2rsc_valid : std_logic := '0';
signal sig_calc2dm_calc_err : std_logic := '0';
signal sig_rsc2stat_status : std_logic_vector(MM2S_STS_WIDTH-1 downto 0) := (others => '0');
signal sig_stat2rsc_status_ready : std_logic := '0';
signal sig_rsc2stat_status_valid : std_logic := '0';
signal sig_rsc2mstr_halt_pipe : std_logic := '0';
signal sig_mstr2data_tag : std_logic_vector(MM2S_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2addr_tag : std_logic_vector(MM2S_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_dbg_data_mux_out : std_logic_vector(31 downto 0) := (others => '0');
signal sig_dbg_data_0 : std_logic_vector(31 downto 0) := (others => '0');
signal sig_dbg_data_1 : std_logic_vector(31 downto 0) := (others => '0');
signal sig_sf2rdc_wready : std_logic := '0';
signal sig_rdc2sf_wvalid : std_logic := '0';
signal sig_rdc2sf_wdata : std_logic_vector(SF_UPSIZED_SDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_rdc2sf_wstrb : std_logic_vector((SF_UPSIZED_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_rdc2sf_wlast : std_logic := '0';
signal sig_skid2dre_wready : std_logic := '0';
signal sig_dre2skid_wvalid : std_logic := '0';
signal sig_dre2skid_wdata : std_logic_vector(MM2S_SDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_dre2skid_wstrb : std_logic_vector((MM2S_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_dre2skid_wlast : std_logic := '0';
signal sig_dre2sf_wready : std_logic := '0';
signal sig_sf2dre_wvalid : std_logic := '0';
signal sig_sf2dre_wdata : std_logic_vector(MM2S_SDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_sf2dre_wstrb : std_logic_vector((MM2S_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_sf2dre_wlast : std_logic := '0';
signal sig_rdc2dre_new_align : std_logic := '0';
signal sig_rdc2dre_use_autodest : std_logic := '0';
signal sig_rdc2dre_src_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_rdc2dre_dest_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_rdc2dre_flush : std_logic := '0';
signal sig_sf2dre_new_align : std_logic := '0';
signal sig_sf2dre_use_autodest : std_logic := '0';
signal sig_sf2dre_src_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_sf2dre_dest_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_sf2dre_flush : std_logic := '0';
signal sig_dre_new_align : std_logic := '0';
signal sig_dre_use_autodest : std_logic := '0';
signal sig_dre_src_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_dre_dest_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_dre_flush : std_logic := '0';
signal sig_rst2all_stop_request : std_logic := '0';
signal sig_data2rst_stop_cmplt : std_logic := '0';
signal sig_addr2rst_stop_cmplt : std_logic := '0';
signal sig_data2addr_stop_req : std_logic := '0';
signal sig_data2skid_halt : std_logic := '0';
signal sig_sf_allow_addr_req : std_logic := '0';
signal sig_mm2s_allow_addr_req : std_logic := '0';
signal sig_addr_req_posted : std_logic := '0';
signal sig_rd_xfer_cmplt : std_logic := '0';
signal sig_sf2mstr_cmd_ready : std_logic := '0';
signal sig_mstr2sf_cmd_valid : std_logic := '0';
signal sig_mstr2sf_tag : std_logic_vector(MM2S_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2sf_dre_src_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2sf_dre_dest_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2sf_btt : std_logic_vector(MM2S_BTT_USED-1 downto 0) := (others => '0');
signal sig_mstr2sf_drr : std_logic := '0';
signal sig_mstr2sf_eof : std_logic := '0';
signal sig_mstr2sf_calc_error : std_logic := '0';
signal sig_mstr2sf_strt_offset : std_logic_vector(SF_STRT_OFFSET_WIDTH-1 downto 0) := (others => '0');
signal sig_data2sf_cmd_cmplt : std_logic := '0';
signal sig_cache2mstr_command : std_logic_vector (7 downto 0);
signal mm2s_arcache_int : std_logic_vector (3 downto 0);
signal mm2s_aruser_int : std_logic_vector (3 downto 0);
begin --(architecture implementation)
-- Debug vector output
mm2s_dbg_data <= sig_dbg_data_mux_out;
-- Note that only the mm2s_dbg_sel(0) is used at this time
sig_dbg_data_mux_out <= sig_dbg_data_1
When (mm2s_dbg_sel(0) = '1')
else sig_dbg_data_0 ;
sig_dbg_data_0 <= X"BEEF1111" ; -- 32 bit Constant indicating MM2S Full type
sig_dbg_data_1(0) <= sig_cmd_stat_rst_user ;
sig_dbg_data_1(1) <= sig_cmd_stat_rst_int ;
sig_dbg_data_1(2) <= sig_mmap_rst ;
sig_dbg_data_1(3) <= sig_stream_rst ;
sig_dbg_data_1(4) <= sig_cmd2mstr_cmd_valid ;
sig_dbg_data_1(5) <= sig_mst2cmd_cmd_ready ;
sig_dbg_data_1(6) <= sig_stat2rsc_status_ready;
sig_dbg_data_1(7) <= sig_rsc2stat_status_valid;
sig_dbg_data_1(11 downto 8) <= sig_data2rsc_tag ; -- Current TAG of active data transfer
sig_dbg_data_1(15 downto 12) <= sig_rsc2stat_status(3 downto 0); -- Internal status tag field
sig_dbg_data_1(16) <= sig_rsc2stat_status(4) ; -- Internal error
sig_dbg_data_1(17) <= sig_rsc2stat_status(5) ; -- Decode Error
sig_dbg_data_1(18) <= sig_rsc2stat_status(6) ; -- Slave Error
sig_dbg_data_1(19) <= sig_rsc2stat_status(7) ; -- OKAY
sig_dbg_data_1(20) <= sig_stat2rsc_status_ready ; -- Status Ready Handshake
sig_dbg_data_1(21) <= sig_rsc2stat_status_valid ; -- Status Valid Handshake
-- Spare bits in debug1
sig_dbg_data_1(31 downto 22) <= (others => '0') ; -- spare bits
GEN_CACHE : if (C_ENABLE_CACHE_USER = 0) generate
begin
-- Cache signal tie-off
mm2s_arcache <= "0011"; -- Per Interface-X guidelines for Masters
mm2s_aruser <= "0000"; -- Per Interface-X guidelines for Masters
sig_cache_data <= (others => '0'); --mm2s_cmd_wdata(103 downto 96); -- This is the xUser and xCache values
end generate GEN_CACHE;
GEN_CACHE2 : if (C_ENABLE_CACHE_USER = 1) generate
begin
-- Cache signal tie-off
mm2s_arcache <= mm2s_arcache_int; -- Cache from Desc
mm2s_aruser <= mm2s_aruser_int; -- Cache from Desc
-- sig_cache_data <= mm2s_cmd_wdata(103 downto 96); -- This is the xUser and xCache values
sig_cache_data <= mm2s_cmd_wdata(79 downto 72); -- This is the xUser and xCache values
end generate GEN_CACHE2;
-- Internal error output discrete ------------------------------
mm2s_err <= sig_calc2dm_calc_err;
-- Rip the used portion of the Command Interface Command Data
-- and throw away the padding
sig_mm2s_cmd_wdata <= mm2s_cmd_wdata(MM2S_CMD_WIDTH-1 downto 0);
------------------------------------------------------------
-- Instance: I_RESET
--
-- Description:
-- Reset Block
--
------------------------------------------------------------
I_RESET : entity axi_datamover_v5_1.axi_datamover_reset
generic map (
C_STSCMD_IS_ASYNC => MM2S_STSCMD_IS_ASYNC
)
port map (
primary_aclk => mm2s_aclk ,
primary_aresetn => mm2s_aresetn ,
secondary_awclk => mm2s_cmdsts_awclk ,
secondary_aresetn => mm2s_cmdsts_aresetn ,
halt_req => mm2s_halt ,
halt_cmplt => mm2s_halt_cmplt ,
flush_stop_request => sig_rst2all_stop_request ,
data_cntlr_stopped => sig_data2rst_stop_cmplt ,
addr_cntlr_stopped => sig_addr2rst_stop_cmplt ,
aux1_stopped => LOGIC_HIGH ,
aux2_stopped => LOGIC_HIGH ,
cmd_stat_rst_user => sig_cmd_stat_rst_user ,
cmd_stat_rst_int => sig_cmd_stat_rst_int ,
mmap_rst => sig_mmap_rst ,
stream_rst => sig_stream_rst
);
------------------------------------------------------------
-- Instance: I_CMD_STATUS
--
-- Description:
-- Command and Status Interface Block
--
------------------------------------------------------------
I_CMD_STATUS : entity axi_datamover_v5_1.axi_datamover_cmd_status
generic map (
C_ADDR_WIDTH => MM2S_ADDR_WIDTH ,
C_INCLUDE_STSFIFO => INCLUDE_MM2S_STSFIFO ,
C_STSCMD_FIFO_DEPTH => MM2S_STSCMD_FIFO_DEPTH ,
C_STSCMD_IS_ASYNC => MM2S_STSCMD_IS_ASYNC ,
C_CMD_WIDTH => MM2S_CMD_WIDTH ,
C_STS_WIDTH => MM2S_STS_WIDTH ,
C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => mm2s_aclk ,
secondary_awclk => mm2s_cmdsts_awclk ,
user_reset => sig_cmd_stat_rst_user ,
internal_reset => sig_cmd_stat_rst_int ,
cmd_wvalid => mm2s_cmd_wvalid ,
cmd_wready => mm2s_cmd_wready ,
cmd_wdata => sig_mm2s_cmd_wdata ,
cache_data => sig_cache_data ,
sts_wvalid => mm2s_sts_wvalid ,
sts_wready => mm2s_sts_wready ,
sts_wdata => mm2s_sts_wdata ,
sts_wstrb => mm2s_sts_wstrb ,
sts_wlast => mm2s_sts_wlast ,
cmd2mstr_command => sig_cmd2mstr_command ,
cache2mstr_command => sig_cache2mstr_command ,
mst2cmd_cmd_valid => sig_cmd2mstr_cmd_valid ,
cmd2mstr_cmd_ready => sig_mst2cmd_cmd_ready ,
mstr2stat_status => sig_rsc2stat_status ,
stat2mstr_status_ready => sig_stat2rsc_status_ready ,
mst2stst_status_valid => sig_rsc2stat_status_valid
);
------------------------------------------------------------
-- Instance: I_RD_STATUS_CNTLR
--
-- Description:
-- Read Status Controller Block
--
------------------------------------------------------------
I_RD_STATUS_CNTLR : entity axi_datamover_v5_1.axi_datamover_rd_status_cntl
generic map (
C_STS_WIDTH => MM2S_STS_WIDTH ,
C_TAG_WIDTH => MM2S_TAG_WIDTH
)
port map (
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
calc2rsc_calc_error => sig_calc2dm_calc_err ,
addr2rsc_calc_error => sig_addr2rsc_calc_error ,
addr2rsc_fifo_empty => sig_addr2rsc_cmd_fifo_empty ,
data2rsc_tag => sig_data2rsc_tag ,
data2rsc_calc_error => sig_data2rsc_calc_err ,
data2rsc_okay => sig_data2rsc_okay ,
data2rsc_decerr => sig_data2rsc_decerr ,
data2rsc_slverr => sig_data2rsc_slverr ,
data2rsc_cmd_cmplt => sig_data2rsc_cmd_cmplt ,
rsc2data_ready => sig_rsc2data_ready ,
data2rsc_valid => sig_data2rsc_valid ,
rsc2stat_status => sig_rsc2stat_status ,
stat2rsc_status_ready => sig_stat2rsc_status_ready ,
rsc2stat_status_valid => sig_rsc2stat_status_valid ,
rsc2mstr_halt_pipe => sig_rsc2mstr_halt_pipe
);
------------------------------------------------------------
-- Instance: I_MSTR_PCC
--
-- Description:
-- Predictive Command Calculator Block
--
------------------------------------------------------------
I_MSTR_PCC : entity axi_datamover_v5_1.axi_datamover_pcc
generic map (
C_IS_MM2S => IS_MM2S ,
C_DRE_ALIGN_WIDTH => DRE_ALIGN_WIDTH ,
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_ADDR_WIDTH => MM2S_ADDR_WIDTH ,
C_STREAM_DWIDTH => MM2S_SDATA_WIDTH ,
C_MAX_BURST_LEN => MM2S_BURST_SIZE ,
C_CMD_WIDTH => MM2S_CMD_WIDTH ,
C_TAG_WIDTH => MM2S_TAG_WIDTH ,
C_BTT_USED => MM2S_BTT_USED ,
C_SUPPORT_INDET_BTT => NO_INDET_BTT ,
C_NATIVE_XFER_WIDTH => SF_UPSIZED_SDATA_WIDTH ,
C_STRT_SF_OFFSET_WIDTH => SF_STRT_OFFSET_WIDTH
)
port map (
-- Clock input
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
cmd2mstr_command => sig_cmd2mstr_command ,
cache2mstr_command => sig_cache2mstr_command ,
cmd2mstr_cmd_valid => sig_cmd2mstr_cmd_valid ,
mst2cmd_cmd_ready => sig_mst2cmd_cmd_ready ,
mstr2addr_tag => sig_mstr2addr_tag ,
mstr2addr_addr => sig_mstr2addr_addr ,
mstr2addr_len => sig_mstr2addr_len ,
mstr2addr_size => sig_mstr2addr_size ,
mstr2addr_burst => sig_mstr2addr_burst ,
mstr2addr_cache => sig_mstr2addr_cache ,
mstr2addr_user => sig_mstr2addr_user ,
mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt ,
mstr2addr_calc_error => sig_mstr2addr_calc_error ,
mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid ,
addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready ,
mstr2data_tag => sig_mstr2data_tag ,
mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb ,
mstr2data_len => sig_mstr2data_len ,
mstr2data_strt_strb => sig_mstr2data_strt_strb ,
mstr2data_last_strb => sig_mstr2data_last_strb ,
mstr2data_drr => sig_mstr2data_drr ,
mstr2data_eof => sig_mstr2data_eof ,
mstr2data_sequential => sig_mstr2data_sequential ,
mstr2data_calc_error => sig_mstr2data_calc_error ,
mstr2data_cmd_cmplt => sig_mstr2data_cmd_cmplt ,
mstr2data_cmd_valid => sig_mstr2data_cmd_valid ,
data2mstr_cmd_ready => sig_data2mstr_cmd_ready ,
mstr2data_dre_src_align => sig_mstr2data_dre_src_align ,
mstr2data_dre_dest_align => sig_mstr2data_dre_dest_align ,
calc_error => sig_calc2dm_calc_err ,
dre2mstr_cmd_ready => sig_sf2mstr_cmd_ready ,
mstr2dre_cmd_valid => sig_mstr2sf_cmd_valid ,
mstr2dre_tag => sig_mstr2sf_tag ,
mstr2dre_dre_src_align => sig_mstr2sf_dre_src_align ,
mstr2dre_dre_dest_align => sig_mstr2sf_dre_dest_align ,
mstr2dre_btt => sig_mstr2sf_btt ,
mstr2dre_drr => sig_mstr2sf_drr ,
mstr2dre_eof => sig_mstr2sf_eof ,
mstr2dre_cmd_cmplt => open ,
mstr2dre_calc_error => sig_mstr2sf_calc_error ,
mstr2dre_strt_offset => sig_mstr2sf_strt_offset
);
------------------------------------------------------------
-- Instance: I_ADDR_CNTL
--
-- Description:
-- Address Controller Block
--
------------------------------------------------------------
I_ADDR_CNTL : entity axi_datamover_v5_1.axi_datamover_addr_cntl
generic map (
C_ADDR_FIFO_DEPTH => ADDR_CNTL_FIFO_DEPTH ,
C_ADDR_WIDTH => MM2S_ADDR_WIDTH ,
C_ADDR_ID => MM2S_ARID_VALUE ,
C_ADDR_ID_WIDTH => MM2S_ARID_WIDTH ,
C_TAG_WIDTH => MM2S_TAG_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
addr2axi_aid => mm2s_arid ,
addr2axi_aaddr => mm2s_araddr ,
addr2axi_alen => mm2s_arlen ,
addr2axi_asize => mm2s_arsize ,
addr2axi_aburst => mm2s_arburst ,
addr2axi_aprot => mm2s_arprot ,
addr2axi_avalid => mm2s_arvalid ,
addr2axi_acache => mm2s_arcache_int ,
addr2axi_auser => mm2s_aruser_int ,
axi2addr_aready => mm2s_arready ,
mstr2addr_tag => sig_mstr2addr_tag ,
mstr2addr_addr => sig_mstr2addr_addr ,
mstr2addr_len => sig_mstr2addr_len ,
mstr2addr_size => sig_mstr2addr_size ,
mstr2addr_burst => sig_mstr2addr_burst ,
mstr2addr_cache => sig_mstr2addr_cache ,
mstr2addr_user => sig_mstr2addr_user ,
mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt ,
mstr2addr_calc_error => sig_mstr2addr_calc_error ,
mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid ,
addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready ,
addr2rst_stop_cmplt => sig_addr2rst_stop_cmplt ,
allow_addr_req => sig_mm2s_allow_addr_req ,
addr_req_posted => sig_addr_req_posted ,
addr2data_addr_posted => sig_addr2data_addr_posted ,
data2addr_data_rdy => LOGIC_LOW ,
data2addr_stop_req => sig_data2addr_stop_req ,
addr2stat_calc_error => sig_addr2rsc_calc_error ,
addr2stat_cmd_fifo_empty => sig_addr2rsc_cmd_fifo_empty
);
------------------------------------------------------------
-- Instance: I_RD_DATA_CNTL
--
-- Description:
-- Read Data Controller Block
--
------------------------------------------------------------
I_RD_DATA_CNTL : entity axi_datamover_v5_1.axi_datamover_rddata_cntl
generic map (
C_INCLUDE_DRE => INCLUDE_DRE ,
C_ALIGN_WIDTH => DRE_ALIGN_WIDTH ,
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_DATA_CNTL_FIFO_DEPTH => RD_DATA_CNTL_FIFO_DEPTH ,
C_MMAP_DWIDTH => MM2S_MDATA_WIDTH ,
C_STREAM_DWIDTH => SF_UPSIZED_SDATA_WIDTH ,
C_ENABLE_MM2S_TKEEP => C_ENABLE_MM2S_TKEEP ,
C_TAG_WIDTH => MM2S_TAG_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
-- Clock and Reset -----------------------------------
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
-- Soft Shutdown Interface -----------------------------
rst2data_stop_request => sig_rst2all_stop_request ,
data2addr_stop_req => sig_data2addr_stop_req ,
data2rst_stop_cmplt => sig_data2rst_stop_cmplt ,
-- External Address Pipelining Contol support
mm2s_rd_xfer_cmplt => sig_rd_xfer_cmplt ,
-- AXI Read Data Channel I/O -------------------------------
mm2s_rdata => mm2s_rdata ,
mm2s_rresp => mm2s_rresp ,
mm2s_rlast => mm2s_rlast ,
mm2s_rvalid => mm2s_rvalid ,
mm2s_rready => mm2s_rready ,
-- MM2S DRE Control -----------------------------------
mm2s_dre_new_align => sig_rdc2dre_new_align ,
mm2s_dre_use_autodest => sig_rdc2dre_use_autodest ,
mm2s_dre_src_align => sig_rdc2dre_src_align ,
mm2s_dre_dest_align => sig_rdc2dre_dest_align ,
mm2s_dre_flush => sig_rdc2dre_flush ,
-- AXI Master Stream -----------------------------------
mm2s_strm_wvalid => sig_rdc2sf_wvalid ,
mm2s_strm_wready => sig_sf2rdc_wready ,
mm2s_strm_wdata => sig_rdc2sf_wdata ,
mm2s_strm_wstrb => sig_rdc2sf_wstrb ,
mm2s_strm_wlast => sig_rdc2sf_wlast ,
-- MM2S Store and Forward Supplimental Control ----------
mm2s_data2sf_cmd_cmplt => sig_data2sf_cmd_cmplt ,
-- Command Calculator Interface --------------------------
mstr2data_tag => sig_mstr2data_tag ,
mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb ,
mstr2data_len => sig_mstr2data_len ,
mstr2data_strt_strb => sig_mstr2data_strt_strb ,
mstr2data_last_strb => sig_mstr2data_last_strb ,
mstr2data_drr => sig_mstr2data_drr ,
mstr2data_eof => sig_mstr2data_eof ,
mstr2data_sequential => sig_mstr2data_sequential ,
mstr2data_calc_error => sig_mstr2data_calc_error ,
mstr2data_cmd_cmplt => sig_mstr2data_cmd_cmplt ,
mstr2data_cmd_valid => sig_mstr2data_cmd_valid ,
data2mstr_cmd_ready => sig_data2mstr_cmd_ready ,
mstr2data_dre_src_align => sig_mstr2data_dre_src_align ,
mstr2data_dre_dest_align => sig_mstr2data_dre_dest_align ,
-- Address Controller Interface --------------------------
addr2data_addr_posted => sig_addr2data_addr_posted ,
-- Data Controller Halted Status
data2all_dcntlr_halted => sig_data2all_dcntlr_halted ,
-- Output Stream Skid Buffer Halt control
data2skid_halt => sig_data2skid_halt ,
-- Read Status Controller Interface --------------------------
data2rsc_tag => sig_data2rsc_tag ,
data2rsc_calc_err => sig_data2rsc_calc_err ,
data2rsc_okay => sig_data2rsc_okay ,
data2rsc_decerr => sig_data2rsc_decerr ,
data2rsc_slverr => sig_data2rsc_slverr ,
data2rsc_cmd_cmplt => sig_data2rsc_cmd_cmplt ,
rsc2data_ready => sig_rsc2data_ready ,
data2rsc_valid => sig_data2rsc_valid ,
rsc2mstr_halt_pipe => sig_rsc2mstr_halt_pipe
);
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INCLUDE_MM2S_SF
--
-- If Generate Description:
-- Include the MM2S Store and Forward function
--
--
------------------------------------------------------------
GEN_INCLUDE_MM2S_SF : if (C_INCLUDE_MM2S_GP_SF = 1) generate
begin
-- Merge external address posting control with the
-- Store and Forward address posting control
sig_mm2s_allow_addr_req <= sig_sf_allow_addr_req and
mm2s_allow_addr_req;
-- Address Posting support outputs
mm2s_addr_req_posted <= sig_addr_req_posted ;
mm2s_rd_xfer_cmplt <= sig_rd_xfer_cmplt ;
sig_dre_new_align <= sig_sf2dre_new_align ;
sig_dre_use_autodest <= sig_sf2dre_use_autodest ;
sig_dre_src_align <= sig_sf2dre_src_align ;
sig_dre_dest_align <= sig_sf2dre_dest_align ;
sig_dre_flush <= sig_sf2dre_flush ;
------------------------------------------------------------
-- Instance: I_RD_SF
--
-- Description:
-- Instance for the MM2S Store and Forward module with
-- downsizer support.
--
------------------------------------------------------------
I_RD_SF : entity axi_datamover_v5_1.axi_datamover_rd_sf
generic map (
C_SF_FIFO_DEPTH => SF_FIFO_DEPTH ,
C_MAX_BURST_LEN => MM2S_BURST_SIZE ,
C_DRE_IS_USED => INCLUDE_DRE ,
C_DRE_CNTL_FIFO_DEPTH => RD_DATA_CNTL_FIFO_DEPTH ,
C_DRE_ALIGN_WIDTH => DRE_ALIGN_WIDTH ,
C_MMAP_DWIDTH => MM2S_MDATA_WIDTH ,
C_STREAM_DWIDTH => MM2S_SDATA_WIDTH ,
C_STRT_SF_OFFSET_WIDTH => SF_STRT_OFFSET_WIDTH ,
C_TAG_WIDTH => MM2S_TAG_WIDTH ,
C_ENABLE_MM2S_TKEEP => C_ENABLE_MM2S_TKEEP ,
C_FAMILY => C_FAMILY
)
port map (
-- Clock and Reset inputs -------------------------------
aclk => mm2s_aclk ,
reset => sig_mmap_rst ,
-- DataMover Read Side Address Pipelining Control Interface
ok_to_post_rd_addr => sig_sf_allow_addr_req ,
rd_addr_posted => sig_addr_req_posted ,
rd_xfer_cmplt => sig_rd_xfer_cmplt ,
-- Read Side Stream In from DataMover MM2S Read Data Controller -----
sf2sin_tready => sig_sf2rdc_wready ,
sin2sf_tvalid => sig_rdc2sf_wvalid ,
sin2sf_tdata => sig_rdc2sf_wdata ,
sin2sf_tkeep => sig_rdc2sf_wstrb ,
sin2sf_tlast => sig_rdc2sf_wlast ,
-- RDC Store and Forward Supplimental Controls ----------
data2sf_cmd_cmplt => sig_data2sf_cmd_cmplt ,
data2sf_dre_flush => sig_rdc2dre_flush ,
-- DRE Control Interface from the Command Calculator -----------------------------
dre2mstr_cmd_ready => sig_sf2mstr_cmd_ready ,
mstr2dre_cmd_valid => sig_mstr2sf_cmd_valid ,
mstr2dre_tag => sig_mstr2sf_tag ,
mstr2dre_dre_src_align => sig_mstr2sf_dre_src_align ,
mstr2dre_dre_dest_align => sig_mstr2sf_dre_dest_align ,
mstr2dre_drr => sig_mstr2sf_drr ,
mstr2dre_eof => sig_mstr2sf_eof ,
mstr2dre_calc_error => sig_mstr2sf_calc_error ,
mstr2dre_strt_offset => sig_mstr2sf_strt_offset ,
-- MM2S DRE Control -------------------------------------------------------------
sf2dre_new_align => sig_sf2dre_new_align ,
sf2dre_use_autodest => sig_sf2dre_use_autodest ,
sf2dre_src_align => sig_sf2dre_src_align ,
sf2dre_dest_align => sig_sf2dre_dest_align ,
sf2dre_flush => sig_sf2dre_flush ,
-- Stream Out ----------------------------------
sout2sf_tready => sig_dre2sf_wready ,
sf2sout_tvalid => sig_sf2dre_wvalid ,
sf2sout_tdata => sig_sf2dre_wdata ,
sf2sout_tkeep => sig_sf2dre_wstrb ,
sf2sout_tlast => sig_sf2dre_wlast
);
-- ------------------------------------------------------------
-- -- Instance: I_RD_SF
-- --
-- -- Description:
-- -- Instance for the MM2S Store and Forward module.
-- --
-- ------------------------------------------------------------
-- I_RD_SF : entity axi_datamover_v5_1.axi_datamover_rd_sf
-- generic map (
--
-- C_SF_FIFO_DEPTH => SF_FIFO_DEPTH ,
-- C_MAX_BURST_LEN => MM2S_BURST_SIZE ,
-- C_DRE_IS_USED => INCLUDE_DRE ,
-- C_STREAM_DWIDTH => MM2S_SDATA_WIDTH ,
-- C_FAMILY => C_FAMILY
-- )
-- port map (
--
-- -- Clock and Reset inputs -------------------------------
-- aclk => mm2s_aclk ,
-- reset => sig_mmap_rst ,
--
--
-- -- DataMover Read Side Address Pipelining Control Interface
-- ok_to_post_rd_addr => sig_sf_allow_addr_req ,
-- rd_addr_posted => sig_addr_req_posted ,
-- rd_xfer_cmplt => sig_rd_xfer_cmplt ,
--
--
--
-- -- Read Side Stream In from DataMover MM2S -----
-- sf2sin_tready => sig_sf2dre_wready ,
-- sin2sf_tvalid => sig_dre2sf_wvalid ,
-- sin2sf_tdata => sig_dre2sf_wdata ,
-- sin2sf_tkeep => sig_dre2sf_wstrb ,
-- sin2sf_tlast => sig_dre2sf_wlast ,
--
--
--
-- -- Stream Out ----------------------------------
-- sout2sf_tready => sig_skid2sf_wready ,
-- sf2sout_tvalid => sig_sf2skid_wvalid ,
-- sf2sout_tdata => sig_sf2skid_wdata ,
-- sf2sout_tkeep => sig_sf2skid_wstrb ,
-- sf2sout_tlast => sig_sf2skid_wlast
--
-- );
end generate GEN_INCLUDE_MM2S_SF;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_MM2S_SF
--
-- If Generate Description:
-- Omit the MM2S Store and Forward function
--
--
------------------------------------------------------------
GEN_NO_MM2S_SF : if (C_INCLUDE_MM2S_GP_SF = 0) generate
begin
-- Allow external address posting control
-- Ignore Store and Forward Control
sig_mm2s_allow_addr_req <= mm2s_allow_addr_req ;
sig_sf_allow_addr_req <= '0' ;
-- Address Posting support outputs
mm2s_addr_req_posted <= sig_addr_req_posted ;
mm2s_rd_xfer_cmplt <= sig_rd_xfer_cmplt ;
-- DRE Control Bus (Connect to the Read data Controller)
sig_dre_new_align <= sig_rdc2dre_new_align ;
sig_dre_use_autodest <= sig_rdc2dre_use_autodest ;
sig_dre_src_align <= sig_rdc2dre_src_align ;
sig_dre_dest_align <= sig_rdc2dre_dest_align ;
sig_dre_flush <= sig_rdc2dre_flush ;
-- Just pass stream signals through
sig_sf2rdc_wready <= sig_dre2sf_wready ;
sig_sf2dre_wvalid <= sig_rdc2sf_wvalid ;
sig_sf2dre_wdata <= sig_rdc2sf_wdata ;
sig_sf2dre_wstrb <= sig_rdc2sf_wstrb ;
sig_sf2dre_wlast <= sig_rdc2sf_wlast ;
-- Always enable the DRE Cmd bus for loading to keep from
-- stalling the PCC module
sig_sf2mstr_cmd_ready <= LOGIC_HIGH;
end generate GEN_NO_MM2S_SF;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INCLUDE_MM2S_DRE
--
-- If Generate Description:
-- Include the MM2S DRE
--
--
------------------------------------------------------------
GEN_INCLUDE_MM2S_DRE : if (INCLUDE_DRE = 1) generate
begin
------------------------------------------------------------
-- Instance: I_DRE64
--
-- Description:
-- Instance for the MM2S DRE whach can support widths of
-- 16 bits to 64 bits.
--
------------------------------------------------------------
I_DRE_16_to_64 : entity axi_datamover_v5_1.axi_datamover_mm2s_dre
generic map (
C_DWIDTH => MM2S_SDATA_WIDTH ,
C_ALIGN_WIDTH => DRE_ALIGN_WIDTH
)
port map (
-- Control inputs
dre_clk => mm2s_aclk ,
dre_rst => sig_stream_rst ,
dre_new_align => sig_dre_new_align ,
dre_use_autodest => sig_dre_use_autodest ,
dre_src_align => sig_dre_src_align ,
dre_dest_align => sig_dre_dest_align ,
dre_flush => sig_dre_flush ,
-- Stream Inputs
dre_in_tstrb => sig_sf2dre_wstrb ,
dre_in_tdata => sig_sf2dre_wdata ,
dre_in_tlast => sig_sf2dre_wlast ,
dre_in_tvalid => sig_sf2dre_wvalid ,
dre_in_tready => sig_dre2sf_wready ,
-- Stream Outputs
dre_out_tstrb => sig_dre2skid_wstrb ,
dre_out_tdata => sig_dre2skid_wdata ,
dre_out_tlast => sig_dre2skid_wlast ,
dre_out_tvalid => sig_dre2skid_wvalid ,
dre_out_tready => sig_skid2dre_wready
);
end generate GEN_INCLUDE_MM2S_DRE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_MM2S_DRE
--
-- If Generate Description:
-- Omit the MM2S DRE and housekeep the signals that it
-- needs to output.
--
------------------------------------------------------------
GEN_NO_MM2S_DRE : if (INCLUDE_DRE = 0) generate
begin
-- Just pass stream signals through from the Store
-- and Forward module
sig_dre2sf_wready <= sig_skid2dre_wready ;
sig_dre2skid_wvalid <= sig_sf2dre_wvalid ;
sig_dre2skid_wdata <= sig_sf2dre_wdata ;
sig_dre2skid_wstrb <= sig_sf2dre_wstrb ;
sig_dre2skid_wlast <= sig_sf2dre_wlast ;
end generate GEN_NO_MM2S_DRE;
ENABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(5) = '1' generate
begin
------------------------------------------------------------
-- Instance: I_MM2S_SKID_BUF
--
-- Description:
-- Instance for the MM2S Skid Buffer which provides for
-- registerd Master Stream outputs and supports bi-dir
-- throttling.
--
------------------------------------------------------------
I_MM2S_SKID_BUF : entity axi_datamover_v5_1.axi_datamover_skid_buf
generic map (
C_WDATA_WIDTH => MM2S_SDATA_WIDTH
)
port map (
-- System Ports
aclk => mm2s_aclk ,
arst => sig_stream_rst ,
-- Shutdown control (assert for 1 clk pulse)
skid_stop => sig_data2skid_halt ,
-- Slave Side (Stream Data Input)
s_valid => sig_dre2skid_wvalid ,
s_ready => sig_skid2dre_wready ,
s_data => sig_dre2skid_wdata ,
s_strb => sig_dre2skid_wstrb ,
s_last => sig_dre2skid_wlast ,
-- Master Side (Stream Data Output
m_valid => mm2s_strm_wvalid ,
m_ready => mm2s_strm_wready ,
m_data => mm2s_strm_wdata ,
m_strb => mm2s_strm_wstrb ,
m_last => mm2s_strm_wlast
);
end generate ENABLE_AXIS_SKID;
DISABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(5) = '0' generate
begin
mm2s_strm_wvalid <= sig_dre2skid_wvalid;
sig_skid2dre_wready <= mm2s_strm_wready;
mm2s_strm_wdata <= sig_dre2skid_wdata;
mm2s_strm_wstrb <= sig_dre2skid_wstrb;
mm2s_strm_wlast <= sig_dre2skid_wlast;
end generate DISABLE_AXIS_SKID;
end implementation;
|
mit
|
YingcaiDong/Shunting-Model-Based-Path-Planning-Algorithm-Accelerator-Using-FPGA
|
System Design Source FIle/ipshared/xilinx.com/axi_sg_v4_1/0535f152/hdl/src/vhdl/axi_sg_skid_buf.vhd
|
13
|
18142
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_skid_buf.vhd
--
-- Description:
-- Implements the AXi Skid Buffer in the Option 2 (Registerd outputs) mode.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_sg_skid_buf is
generic (
C_WDATA_WIDTH : INTEGER := 32
-- Width of the Stream Data bus (in bits)
);
port (
-- Clock and Reset Inputs ---------------------------------------------
aclk : In std_logic ; --
arst : In std_logic ; --
-----------------------------------------------------------------------
-- Shutdown control (assert for 1 clk pulse) --------------------------
--
skid_stop : In std_logic ; --
-----------------------------------------------------------------------
-- Slave Side (Stream Data Input) -------------------------------------
s_valid : In std_logic ; --
s_ready : Out std_logic ; --
s_data : In std_logic_vector(C_WDATA_WIDTH-1 downto 0); --
s_strb : In std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0); --
s_last : In std_logic ; --
-----------------------------------------------------------------------
-- Master Side (Stream Data Output ------------------------------------
m_valid : Out std_logic ; --
m_ready : In std_logic ; --
m_data : Out std_logic_vector(C_WDATA_WIDTH-1 downto 0); --
m_strb : Out std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0); --
m_last : Out std_logic --
-----------------------------------------------------------------------
);
end entity axi_sg_skid_buf;
architecture implementation of axi_sg_skid_buf is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Signals decalrations -------------------------
Signal sig_reset_reg : std_logic := '0';
signal sig_spcl_s_ready_set : std_logic := '0';
signal sig_data_skid_reg : std_logic_vector(C_WDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_skid_reg : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_skid_reg : std_logic := '0';
signal sig_skid_reg_en : std_logic := '0';
signal sig_data_skid_mux_out : std_logic_vector(C_WDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_skid_mux_out : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_skid_mux_out : std_logic := '0';
signal sig_skid_mux_sel : std_logic := '0';
signal sig_data_reg_out : std_logic_vector(C_WDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_reg_out : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_reg_out : std_logic := '0';
signal sig_data_reg_out_en : std_logic := '0';
signal sig_m_valid_out : std_logic := '0';
signal sig_m_valid_dup : std_logic := '0';
signal sig_m_valid_comb : std_logic := '0';
signal sig_s_ready_out : std_logic := '0';
signal sig_s_ready_dup : std_logic := '0';
signal sig_s_ready_comb : std_logic := '0';
signal sig_stop_request : std_logic := '0';
signal sig_stopped : std_logic := '0';
signal sig_sready_stop : std_logic := '0';
signal sig_sready_early_stop : std_logic := '0';
signal sig_sready_stop_set : std_logic := '0';
signal sig_sready_stop_reg : std_logic := '0';
signal sig_mvalid_stop_reg : std_logic := '0';
signal sig_mvalid_stop : std_logic := '0';
signal sig_mvalid_early_stop : std_logic := '0';
signal sig_mvalid_stop_set : std_logic := '0';
signal sig_slast_with_stop : std_logic := '0';
signal sig_sstrb_stop_mask : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_sstrb_with_stop : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0');
-- Register duplication attribute assignments to control fanout
-- on handshake output signals
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
Attribute KEEP of sig_m_valid_out : signal is "TRUE"; -- definition
Attribute KEEP of sig_m_valid_dup : signal is "TRUE"; -- definition
Attribute KEEP of sig_s_ready_out : signal is "TRUE"; -- definition
Attribute KEEP of sig_s_ready_dup : signal is "TRUE"; -- definition
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_m_valid_out : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_m_valid_dup : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_out : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_dup : signal is "no";
begin --(architecture implementation)
m_valid <= sig_m_valid_out;
s_ready <= sig_s_ready_out;
m_strb <= sig_strb_reg_out;
m_last <= sig_last_reg_out;
m_data <= sig_data_reg_out;
-- Special shutdown logic version od Slast.
-- A halt request forces a tlast through the skig buffer
sig_slast_with_stop <= s_last or sig_stop_request;
sig_sstrb_with_stop <= s_strb or sig_sstrb_stop_mask;
-- Assign the special s_ready FLOP set signal
sig_spcl_s_ready_set <= sig_reset_reg;
-- Generate the ouput register load enable control
sig_data_reg_out_en <= m_ready or not(sig_m_valid_dup);
-- Generate the skid input register load enable control
sig_skid_reg_en <= sig_s_ready_dup;
-- Generate the skid mux select control
sig_skid_mux_sel <= not(sig_s_ready_dup);
-- Skid Mux
sig_data_skid_mux_out <= sig_data_skid_reg
When (sig_skid_mux_sel = '1')
Else s_data;
sig_strb_skid_mux_out <= sig_strb_skid_reg
When (sig_skid_mux_sel = '1')
Else sig_sstrb_with_stop;
sig_last_skid_mux_out <= sig_last_skid_reg
When (sig_skid_mux_sel = '1')
Else sig_slast_with_stop;
-- m_valid combinational logic
sig_m_valid_comb <= s_valid or
(sig_m_valid_dup and
(not(sig_s_ready_dup) or
not(m_ready)));
-- s_ready combinational logic
sig_s_ready_comb <= m_ready or
(sig_s_ready_dup and
(not(sig_m_valid_dup) or
not(s_valid)));
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_THE_RST
--
-- Process Description:
-- Register input reset
--
-------------------------------------------------------------
REG_THE_RST : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
sig_reset_reg <= ARST;
end if;
end process REG_THE_RST;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: S_READY_FLOP
--
-- Process Description:
-- Registers s_ready handshake signals per Skid Buffer
-- Option 2 scheme
--
-------------------------------------------------------------
S_READY_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1' or
sig_sready_stop = '1' or
sig_sready_early_stop = '1') then -- Special stop condition
sig_s_ready_out <= '0';
sig_s_ready_dup <= '0';
Elsif (sig_spcl_s_ready_set = '1') Then
sig_s_ready_out <= '1';
sig_s_ready_dup <= '1';
else
sig_s_ready_out <= sig_s_ready_comb;
sig_s_ready_dup <= sig_s_ready_comb;
end if;
end if;
end process S_READY_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: M_VALID_FLOP
--
-- Process Description:
-- Registers m_valid handshake signals per Skid Buffer
-- Option 2 scheme
--
-------------------------------------------------------------
M_VALID_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1' or
sig_spcl_s_ready_set = '1' or -- Fix from AXI DMA
sig_mvalid_stop = '1' or
sig_mvalid_stop_set = '1') then -- Special stop condition
sig_m_valid_out <= '0';
sig_m_valid_dup <= '0';
else
sig_m_valid_out <= sig_m_valid_comb;
sig_m_valid_dup <= sig_m_valid_comb;
end if;
end if;
end process M_VALID_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SKID_REG
--
-- Process Description:
-- This process implements the output registers for the
-- Skid Buffer Data signals
--
-------------------------------------------------------------
SKID_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_data_skid_reg <= (others => '0');
sig_strb_skid_reg <= (others => '0');
sig_last_skid_reg <= '0';
elsif (sig_skid_reg_en = '1') then
sig_data_skid_reg <= s_data;
sig_strb_skid_reg <= sig_sstrb_with_stop;
sig_last_skid_reg <= sig_slast_with_stop;
else
null; -- hold current state
end if;
end if;
end process SKID_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: OUTPUT_REG
--
-- Process Description:
-- This process implements the output registers for the
-- Skid Buffer Data signals
--
-------------------------------------------------------------
OUTPUT_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1' or
sig_mvalid_stop_reg = '1') then
sig_data_reg_out <= (others => '0');
sig_strb_reg_out <= (others => '0');
sig_last_reg_out <= '0';
elsif (sig_data_reg_out_en = '1') then
sig_data_reg_out <= sig_data_skid_mux_out;
sig_strb_reg_out <= sig_strb_skid_mux_out;
sig_last_reg_out <= sig_last_skid_mux_out;
else
null; -- hold current state
end if;
end if;
end process OUTPUT_REG;
-------- Special Stop Logic --------------------------------------
sig_sready_stop <= sig_sready_stop_reg;
sig_sready_early_stop <= skid_stop; -- deassert S_READY immediately
sig_sready_stop_set <= sig_sready_early_stop;
sig_mvalid_stop <= sig_mvalid_stop_reg;
sig_mvalid_early_stop <= sig_m_valid_dup and
m_ready and
skid_stop;
sig_mvalid_stop_set <= sig_mvalid_early_stop or
(sig_stop_request and
not(sig_m_valid_dup)) or
(sig_m_valid_dup and
m_ready and
sig_stop_request);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_STOP_REQ_FLOP
--
-- Process Description:
-- This process implements the Stop request flop. It is a
-- sample and hold register that can only be cleared by reset.
--
-------------------------------------------------------------
IMP_STOP_REQ_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_stop_request <= '0';
sig_sstrb_stop_mask <= (others => '0');
elsif (skid_stop = '1') then
sig_stop_request <= '1';
sig_sstrb_stop_mask <= (others => '1');
else
null; -- hold current state
end if;
end if;
end process IMP_STOP_REQ_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CLR_SREADY_FLOP
--
-- Process Description:
-- This process implements the flag to clear the s_ready
-- flop at a stop condition.
--
-------------------------------------------------------------
IMP_CLR_SREADY_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_sready_stop_reg <= '0';
elsif (sig_sready_stop_set = '1') then
sig_sready_stop_reg <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_CLR_SREADY_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CLR_MVALID_FLOP
--
-- Process Description:
-- This process implements the flag to clear the m_valid
-- flop at a stop condition.
--
-------------------------------------------------------------
IMP_CLR_MVALID_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_mvalid_stop_reg <= '0';
elsif (sig_mvalid_stop_set = '1') then
sig_mvalid_stop_reg <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_CLR_MVALID_FLOP;
end implementation;
|
mit
|
UVVM/UVVM_All
|
uvvm_util/src/methods_pkg.vhd
|
1
|
419365
|
--================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
----------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
use ieee.numeric_std.all;
use std.textio.all;
use work.types_pkg.all;
use work.string_methods_pkg.all;
use work.adaptations_pkg.all;
use work.license_pkg.all;
use work.global_signals_and_shared_variables_pkg.all;
use work.alert_hierarchy_pkg.all;
use work.protected_types_pkg.all;
use std.env.all;
package methods_pkg is
constant C_UVVM_VERSION : string := "v2 2021.10.22";
-- -- ============================================================================
-- -- Initialisation and license
-- -- ============================================================================
-- procedure initialise_util(
-- constant dummy : in t_void
-- );
--
-- ============================================================================
-- File handling (that needs to use other utility methods)
-- ============================================================================
procedure check_file_open_status(
constant status : in file_open_status;
constant file_name : in string;
constant scope : in string := C_SCOPE
);
procedure set_alert_file_name(
constant file_name : string := C_ALERT_FILE_NAME
);
-- msg_id is unused. This is a deprecated overload
procedure set_alert_file_name(
constant file_name : string := C_ALERT_FILE_NAME;
constant msg_id : t_msg_id
);
procedure set_log_file_name(
constant file_name : string := C_LOG_FILE_NAME
);
-- msg_id is unused. This is a deprecated overload
procedure set_log_file_name(
constant file_name : string := C_LOG_FILE_NAME;
constant msg_id : t_msg_id
);
-- ============================================================================
-- Log-related
-- ============================================================================
procedure log(
msg_id : t_msg_id;
msg : string;
scope : string := C_TB_SCOPE_DEFAULT;
msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
log_destination : t_log_destination := shared_default_log_destination;
log_file_name : string := C_LOG_FILE_NAME;
open_mode : file_open_kind := append_mode
);
procedure log(
msg : string;
scope : string := C_TB_SCOPE_DEFAULT;
msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
log_destination : t_log_destination := shared_default_log_destination;
log_file_name : string := C_LOG_FILE_NAME;
open_mode : file_open_kind := append_mode
);
procedure log_text_block(
msg_id : t_msg_id;
variable text_block : inout line;
formatting : t_log_format; -- FORMATTED or UNFORMATTED
msg_header : string := "";
scope : string := C_TB_SCOPE_DEFAULT;
msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
log_if_block_empty : t_log_if_block_empty := WRITE_HDR_IF_BLOCK_EMPTY;
log_destination : t_log_destination := shared_default_log_destination;
log_file_name : string := C_LOG_FILE_NAME;
open_mode : file_open_kind := append_mode
);
procedure write_to_file (
file_name : string;
open_mode : file_open_kind;
variable my_line : inout line
);
procedure write_line_to_log_destination(
variable log_line : inout line;
constant log_destination : in t_log_destination := shared_default_log_destination;
constant log_file_name : in string := C_LOG_FILE_NAME;
constant open_mode : in file_open_kind := append_mode
);
procedure enable_log_msg(
constant msg_id : t_msg_id;
variable msg_id_panel : inout t_msg_id_panel;
constant msg : string := "";
constant scope : string := C_TB_SCOPE_DEFAULT;
constant quietness : t_quietness := NON_QUIET
);
procedure enable_log_msg(
msg_id : t_msg_id;
msg : string;
quietness : t_quietness := NON_QUIET;
scope : string := C_TB_SCOPE_DEFAULT
);
procedure enable_log_msg(
msg_id : t_msg_id;
quietness : t_quietness := NON_QUIET;
scope : string := C_TB_SCOPE_DEFAULT
);
procedure disable_log_msg(
constant msg_id : t_msg_id;
variable msg_id_panel : inout t_msg_id_panel;
constant msg : string := "";
constant scope : string := C_TB_SCOPE_DEFAULT;
constant quietness : t_quietness := NON_QUIET
);
procedure disable_log_msg(
msg_id : t_msg_id;
msg : string;
quietness : t_quietness := NON_QUIET;
scope : string := C_TB_SCOPE_DEFAULT
);
procedure disable_log_msg(
msg_id : t_msg_id;
quietness : t_quietness := NON_QUIET;
scope : string := C_TB_SCOPE_DEFAULT
);
impure function is_log_msg_enabled(
msg_id : t_msg_id;
msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) return boolean;
procedure set_log_destination(
constant log_destination : t_log_destination;
constant quietness : t_quietness := NON_QUIET
);
-- ============================================================================
-- Alert-related
-- ============================================================================
procedure alert(
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
);
-- Dedicated alert-procedures all alert levels (less verbose - as 2 rather than 3 parameters...)
procedure note(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure tb_note(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure warning(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure tb_warning(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure manual_check(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure error(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure tb_error(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure failure(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure tb_failure(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure increment_expected_alerts(
constant alert_level : t_alert_level;
constant number : natural := 1;
constant msg : string := "";
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure report_alert_counters(
constant order : in t_order
);
procedure report_alert_counters(
constant dummy : in t_void
);
procedure report_global_ctrl(
constant dummy : in t_void
);
procedure report_msg_id_panel(
constant dummy : in t_void
);
procedure set_alert_attention(
alert_level : t_alert_level;
attention : t_attention;
msg : string := ""
);
impure function get_alert_attention(
alert_level : t_alert_level
) return t_attention;
procedure set_alert_stop_limit(
alert_level : t_alert_level;
value : natural
);
impure function get_alert_stop_limit(
alert_level : t_alert_level
) return natural;
impure function get_alert_counter(
alert_level : t_alert_level;
attention : t_attention := REGARD
) return natural;
procedure increment_alert_counter(
alert_level : t_alert_level;
attention : t_attention := REGARD; -- regard, expect, ignore
number : natural := 1
);
procedure increment_expected_alerts_and_stop_limit(
constant alert_level : t_alert_level;
constant number : natural := 1;
constant msg : string := "";
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure report_check_counters(
constant dummy : in t_void
);
procedure report_check_counters(
constant order : in t_order
);
-- ============================================================================
-- Deprecate message
-- ============================================================================
procedure deprecate(
caller_name : string;
constant msg : string := ""
);
-- ============================================================================
-- Non time consuming checks
-- ============================================================================
-- Matching if same width or only zeros in "extended width"
function matching_widths(
value1 : std_logic_vector;
value2 : std_logic_vector
) return boolean;
function matching_widths(
value1 : unsigned;
value2 : unsigned
) return boolean;
function matching_widths(
value1 : signed;
value2 : signed
) return boolean;
-- function version of check_value (with return value)
impure function check_value(
constant value : boolean;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean;
impure function check_value(
constant value : boolean;
constant exp : boolean;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean;
impure function check_value(
constant value : std_logic;
constant exp : std_logic;
constant match_strictness : t_match_strictness;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean;
impure function check_value(
constant value : std_logic;
constant exp : std_logic;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean;
impure function check_value(
constant value : std_logic_vector;
constant exp : std_logic_vector;
constant match_strictness : t_match_strictness;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "slv"
) return boolean;
impure function check_value(
constant value : std_logic_vector;
constant exp : std_logic_vector;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "slv"
) return boolean;
impure function check_value(
constant value : unsigned;
constant exp : unsigned;
constant match_strictness : t_match_strictness;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "unsigned"
) return boolean;
impure function check_value(
constant value : unsigned;
constant exp : unsigned;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "unsigned"
) return boolean;
impure function check_value(
constant value : signed;
constant exp : signed;
constant match_strictness : t_match_strictness;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "signed"
) return boolean;
impure function check_value(
constant value : signed;
constant exp : signed;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "signed"
) return boolean;
impure function check_value(
constant value : integer;
constant exp : integer;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean;
impure function check_value(
constant value : real;
constant exp : real;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean;
impure function check_value(
constant value : time;
constant exp : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean;
impure function check_value(
constant value : string;
constant exp : string;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean;
impure function check_value(
constant value : t_slv_array;
constant exp : t_slv_array;
constant match_strictness : t_match_strictness;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "t_slv_array"
) return boolean;
impure function check_value(
constant value : t_slv_array;
constant exp : t_slv_array;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "t_slv_array"
) return boolean;
impure function check_value(
constant value : t_signed_array;
constant exp : t_signed_array;
constant match_strictness : t_match_strictness;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "t_signed_array"
) return boolean;
impure function check_value(
constant value : t_signed_array;
constant exp : t_signed_array;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "t_signed_array"
) return boolean;
impure function check_value(
constant value : t_unsigned_array;
constant exp : t_unsigned_array;
constant match_strictness : t_match_strictness;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "t_unsigned_array"
) return boolean;
impure function check_value(
constant value : t_unsigned_array;
constant exp : t_unsigned_array;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "t_unsigned_array"
) return boolean;
-- overloads for function versions of check_value (alert level optional)
impure function check_value(
constant value : boolean;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean;
impure function check_value(
constant value : boolean;
constant exp : boolean;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean;
impure function check_value(
constant value : std_logic;
constant exp : std_logic;
constant match_strictness : t_match_strictness;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean;
impure function check_value(
constant value : std_logic;
constant exp : std_logic;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean;
impure function check_value(
constant value : std_logic_vector;
constant exp : std_logic_vector;
constant match_strictness : t_match_strictness;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "slv"
) return boolean;
impure function check_value(
constant value : std_logic_vector;
constant exp : std_logic_vector;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "slv"
) return boolean;
impure function check_value(
constant value : unsigned;
constant exp : unsigned;
constant match_strictness : t_match_strictness;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "unsigned"
) return boolean;
impure function check_value(
constant value : unsigned;
constant exp : unsigned;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "unsigned"
) return boolean;
impure function check_value(
constant value : signed;
constant exp : signed;
constant match_strictness : t_match_strictness;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "signed"
) return boolean;
impure function check_value(
constant value : signed;
constant exp : signed;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "signed"
) return boolean;
impure function check_value(
constant value : integer;
constant exp : integer;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean;
impure function check_value(
constant value : real;
constant exp : real;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean;
impure function check_value(
constant value : time;
constant exp : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean;
impure function check_value(
constant value : string;
constant exp : string;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean;
impure function check_value(
constant value : t_slv_array;
constant exp : t_slv_array;
constant match_strictness : t_match_strictness;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "t_slv_array"
) return boolean;
impure function check_value(
constant value : t_slv_array;
constant exp : t_slv_array;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "t_slv_array"
) return boolean;
impure function check_value(
constant value : t_signed_array;
constant exp : t_signed_array;
constant match_strictness : t_match_strictness;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "t_signed_array"
) return boolean;
impure function check_value(
constant value : t_signed_array;
constant exp : t_signed_array;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "t_signed_array"
) return boolean;
impure function check_value(
constant value : t_unsigned_array;
constant exp : t_unsigned_array;
constant match_strictness : t_match_strictness;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "t_unsigned_array"
) return boolean;
impure function check_value(
constant value : t_unsigned_array;
constant exp : t_unsigned_array;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "t_unsigned_array"
) return boolean;
-- overloads for procedure version of check_value (no return value)
procedure check_value(
constant value : boolean;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
);
procedure check_value(
constant value : boolean;
constant exp : boolean;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
);
procedure check_value(
constant value : std_logic_vector;
constant exp : std_logic_vector;
constant match_strictness : t_match_strictness;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "slv"
);
procedure check_value(
constant value : std_logic_vector;
constant exp : std_logic_vector;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "slv"
);
procedure check_value(
constant value : unsigned;
constant exp : unsigned;
constant match_strictness : t_match_strictness;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "unsigned"
);
procedure check_value(
constant value : unsigned;
constant exp : unsigned;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "unsigned"
);
procedure check_value(
constant value : signed;
constant exp : signed;
constant match_strictness : t_match_strictness;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "signed"
);
procedure check_value(
constant value : signed;
constant exp : signed;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "signed"
);
procedure check_value(
constant value : std_logic;
constant exp : std_logic;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
);
procedure check_value(
constant value : std_logic;
constant exp : std_logic;
constant match_strictness : t_match_strictness;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
);
procedure check_value(
constant value : integer;
constant exp : integer;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
);
procedure check_value(
constant value : real;
constant exp : real;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
);
procedure check_value(
constant value : time;
constant exp : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
);
procedure check_value(
constant value : string;
constant exp : string;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
);
procedure check_value(
constant value : t_slv_array;
constant exp : t_slv_array;
constant match_strictness : t_match_strictness;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "t_slv_array"
);
procedure check_value(
constant value : t_slv_array;
constant exp : t_slv_array;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "t_slv_array"
);
procedure check_value(
constant value : t_signed_array;
constant exp : t_signed_array;
constant match_strictness : t_match_strictness;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "t_signed_array"
);
procedure check_value(
constant value : t_signed_array;
constant exp : t_signed_array;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "t_signed_array"
);
procedure check_value(
constant value : t_unsigned_array;
constant exp : t_unsigned_array;
constant match_strictness : t_match_strictness;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "t_unsigned_array"
);
procedure check_value(
constant value : t_unsigned_array;
constant exp : t_unsigned_array;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "t_unsigned_array"
);
-- Procedure overloads for check_value without mandatory alert_level
procedure check_value(
constant value : boolean;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
);
procedure check_value(
constant value : boolean;
constant exp : boolean;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
);
procedure check_value(
constant value : std_logic_vector;
constant exp : std_logic_vector;
constant match_strictness : t_match_strictness;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "slv"
);
procedure check_value(
constant value : std_logic_vector;
constant exp : std_logic_vector;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "slv"
);
procedure check_value(
constant value : unsigned;
constant exp : unsigned;
constant match_strictness : t_match_strictness;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "unsigned"
);
procedure check_value(
constant value : unsigned;
constant exp : unsigned;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "unsigned"
);
procedure check_value(
constant value : signed;
constant exp : signed;
constant match_strictness : t_match_strictness;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "signed"
);
procedure check_value(
constant value : signed;
constant exp : signed;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "signed"
);
procedure check_value(
constant value : std_logic;
constant exp : std_logic;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
);
procedure check_value(
constant value : std_logic;
constant exp : std_logic;
constant match_strictness : t_match_strictness;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
);
procedure check_value(
constant value : integer;
constant exp : integer;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
);
procedure check_value(
constant value : real;
constant exp : real;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
);
procedure check_value(
constant value : time;
constant exp : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
);
procedure check_value(
constant value : string;
constant exp : string;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
);
procedure check_value(
constant value : t_slv_array;
constant exp : t_slv_array;
constant match_strictness : t_match_strictness;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "t_slv_array"
);
procedure check_value(
constant value : t_slv_array;
constant exp : t_slv_array;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "t_slv_array"
);
procedure check_value(
constant value : t_signed_array;
constant exp : t_signed_array;
constant match_strictness : t_match_strictness;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "t_signed_array"
);
procedure check_value(
constant value : t_signed_array;
constant exp : t_signed_array;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "t_signed_array"
);
procedure check_value(
constant value : t_unsigned_array;
constant exp : t_unsigned_array;
constant match_strictness : t_match_strictness;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "t_unsigned_array"
);
procedure check_value(
constant value : t_unsigned_array;
constant exp : t_unsigned_array;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "t_unsigned_array"
);
--
-- Check_value_in_range
impure function check_value_in_range (
constant value : integer;
constant min_value : integer;
constant max_value : integer;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()";
constant value_type : string := "integer"
) return boolean;
impure function check_value_in_range (
constant value : unsigned;
constant min_value : unsigned;
constant max_value : unsigned;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()";
constant value_type : string := "unsigned"
) return boolean;
impure function check_value_in_range (
constant value : signed;
constant min_value : signed;
constant max_value : signed;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()";
constant value_type : string := "signed"
) return boolean;
impure function check_value_in_range (
constant value : time;
constant min_value : time;
constant max_value : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
) return boolean;
impure function check_value_in_range (
constant value : real;
constant min_value : real;
constant max_value : real;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
) return boolean;
-- Function overloads for check_value_in_range without mandatory alert_level
impure function check_value_in_range (
constant value : integer;
constant min_value : integer;
constant max_value : integer;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()";
constant value_type : string := "integer"
) return boolean;
impure function check_value_in_range (
constant value : unsigned;
constant min_value : unsigned;
constant max_value : unsigned;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()";
constant value_type : string := "unsigned"
) return boolean;
impure function check_value_in_range (
constant value : signed;
constant min_value : signed;
constant max_value : signed;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()";
constant value_type : string := "signed"
) return boolean;
impure function check_value_in_range (
constant value : time;
constant min_value : time;
constant max_value : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
) return boolean;
impure function check_value_in_range (
constant value : real;
constant min_value : real;
constant max_value : real;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
) return boolean;
-- Procedure overloads for check_value_in_range
procedure check_value_in_range (
constant value : integer;
constant min_value : integer;
constant max_value : integer;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
);
procedure check_value_in_range (
constant value : unsigned;
constant min_value : unsigned;
constant max_value : unsigned;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
);
procedure check_value_in_range (
constant value : signed;
constant min_value : signed;
constant max_value : signed;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
);
procedure check_value_in_range (
constant value : time;
constant min_value : time;
constant max_value : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
);
procedure check_value_in_range (
constant value : real;
constant min_value : real;
constant max_value : real;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
);
-- Procedure overloads for check_value_in_range without mandatory alert_level
procedure check_value_in_range (
constant value : integer;
constant min_value : integer;
constant max_value : integer;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
);
procedure check_value_in_range (
constant value : unsigned;
constant min_value : unsigned;
constant max_value : unsigned;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
);
procedure check_value_in_range (
constant value : signed;
constant min_value : signed;
constant max_value : signed;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
);
procedure check_value_in_range (
constant value : time;
constant min_value : time;
constant max_value : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
);
procedure check_value_in_range (
constant value : real;
constant min_value : real;
constant max_value : real;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
);
-- Check_stable
procedure check_stable(
signal target : boolean;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "boolean"
);
procedure check_stable(
signal target : in std_logic_vector;
constant stable_req : in time;
constant alert_level : in t_alert_level;
variable success : out boolean;
constant msg : in string;
constant scope : in string := C_TB_SCOPE_DEFAULT;
constant msg_id : in t_msg_id := ID_POS_ACK;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant caller_name : in string := "check_stable()";
constant value_type : in string := "slv"
);
procedure check_stable(
signal target : std_logic_vector;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "slv"
);
procedure check_stable(
signal target : unsigned;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "unsigned"
);
procedure check_stable(
signal target : signed;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "signed"
);
procedure check_stable(
signal target : std_logic;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "std_logic"
);
procedure check_stable(
signal target : integer;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "integer"
);
procedure check_stable(
signal target : real;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "real"
);
-- Procedure overloads for check_stable without mandatory alert_level
procedure check_stable(
signal target : boolean;
constant stable_req : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "boolean"
);
procedure check_stable(
signal target : std_logic_vector;
constant stable_req : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "slv"
);
procedure check_stable(
signal target : unsigned;
constant stable_req : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "unsigned"
);
procedure check_stable(
signal target : signed;
constant stable_req : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "signed"
);
procedure check_stable(
signal target : std_logic;
constant stable_req : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "std_logic"
);
procedure check_stable(
signal target : integer;
constant stable_req : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "integer"
);
procedure check_stable(
signal target : real;
constant stable_req : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "real"
);
impure function random (
constant length : integer
) return std_logic_vector;
impure function random (
constant VOID : t_void
) return std_logic;
impure function random (
constant min_value : integer;
constant max_value : integer
) return integer;
impure function random (
constant min_value : real;
constant max_value : real
) return real;
impure function random (
constant min_value : time;
constant max_value : time
) return time;
procedure random (
variable v_seed1 : inout positive;
variable v_seed2 : inout positive;
variable v_target : inout std_logic_vector
);
procedure random (
variable v_seed1 : inout positive;
variable v_seed2 : inout positive;
variable v_target : inout std_logic
);
procedure random (
constant min_value : integer;
constant max_value : integer;
variable v_seed1 : inout positive;
variable v_seed2 : inout positive;
variable v_target : inout integer
);
procedure random (
constant min_value : real;
constant max_value : real;
variable v_seed1 : inout positive;
variable v_seed2 : inout positive;
variable v_target : inout real
);
procedure random (
constant min_value : time;
constant max_value : time;
variable v_seed1 : inout positive;
variable v_seed2 : inout positive;
variable v_target : inout time
);
procedure randomize (
constant seed1 : positive;
constant seed2 : positive;
constant msg : string := "randomizing seeds";
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure randomise (
constant seed1 : positive;
constant seed2 : positive;
constant msg : string := "randomising seeds";
constant scope : string := C_TB_SCOPE_DEFAULT
);
function convert_byte_array_to_slv(
constant byte_array : t_byte_array;
constant byte_endianness : t_byte_endianness
) return std_logic_vector;
function convert_slv_to_byte_array(
constant slv : std_logic_vector;
constant byte_endianness : t_byte_endianness
) return t_byte_array;
function convert_byte_array_to_slv_array(
constant byte_array : t_byte_array;
constant bytes_in_word : natural;
constant byte_endianness : t_byte_endianness := LOWER_BYTE_LEFT
) return t_slv_array;
function convert_slv_array_to_byte_array(
constant slv_array : t_slv_array;
constant byte_endianness : t_byte_endianness := LOWER_BYTE_LEFT
) return t_byte_array;
function convert_slv_array_to_byte_array(
constant slv_array : t_slv_array;
constant ascending : boolean := false;
constant byte_endianness : t_byte_endianness := FIRST_BYTE_LEFT
) return t_byte_array;
function reverse_vector(
constant value : std_logic_vector
) return std_logic_vector;
impure function reverse_vectors_in_array(
constant value : t_slv_array
) return t_slv_array;
function log2(
constant num : positive
) return natural;
-- Warning! This function should NOT be used outside the UVVM library.
-- Function is only included to support internal functionality.
-- The function can be removed without notification.
function matching_values(
constant value1 : in std_logic_vector;
constant value2 : in std_logic_vector;
constant match_strictness : in t_match_strictness := MATCH_STD
) return boolean;
-- ============================================================================
-- Time consuming checks
-- ============================================================================
procedure await_change(
signal target : boolean;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "boolean"
);
procedure await_change(
signal target : std_logic;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "std_logic"
);
procedure await_change(
signal target : std_logic_vector;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "slv"
);
procedure await_change(
signal target : unsigned;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "unsigned"
);
procedure await_change(
signal target : signed;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "signed"
);
procedure await_change(
signal target : integer;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "integer"
);
procedure await_change(
signal target : real;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "real"
);
-- Procedure overloads for await_change without mandatory alert_level
procedure await_change(
signal target : boolean;
constant min_time : time;
constant max_time : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "boolean"
);
procedure await_change(
signal target : std_logic;
constant min_time : time;
constant max_time : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "std_logic"
);
procedure await_change(
signal target : std_logic_vector;
constant min_time : time;
constant max_time : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "slv"
);
procedure await_change(
signal target : unsigned;
constant min_time : time;
constant max_time : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "unsigned"
);
procedure await_change(
signal target : signed;
constant min_time : time;
constant max_time : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "signed"
);
procedure await_change(
signal target : integer;
constant min_time : time;
constant max_time : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "integer"
);
procedure await_change(
signal target : real;
constant min_time : time;
constant max_time : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "real"
);
-- Await Value procedures
procedure await_value (
signal target : boolean;
constant exp : boolean;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_value (
signal target : std_logic;
constant exp : std_logic;
constant match_strictness : t_match_strictness;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_value (
signal target : std_logic;
constant exp : std_logic;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_value (
signal target : in std_logic_vector;
constant exp : in std_logic_vector;
constant match_strictness : in t_match_strictness;
constant min_time : in time;
constant max_time : in time;
constant alert_level : in t_alert_level;
variable success : out boolean;
constant msg : in string;
constant scope : in string := C_TB_SCOPE_DEFAULT;
constant radix : in t_radix := HEX_BIN_IF_INVALID;
constant format : in t_format_zeros := SKIP_LEADING_0;
constant msg_id : in t_msg_id := ID_POS_ACK;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant caller_name : in string := ""
);
procedure await_value (
signal target : std_logic_vector;
constant exp : std_logic_vector;
constant match_strictness : t_match_strictness;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_value (
signal target : std_logic_vector;
constant exp : std_logic_vector;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_value (
signal target : unsigned;
constant exp : unsigned;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_value (
signal target : signed;
constant exp : signed;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_value (
signal target : integer;
constant exp : integer;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_value (
signal target : real;
constant exp : real;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
-- Await Value Overloads without Mandatory Alert_Level
procedure await_value (
signal target : boolean;
constant exp : boolean;
constant min_time : time;
constant max_time : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_value (
signal target : std_logic;
constant exp : std_logic;
constant match_strictness : t_match_strictness;
constant min_time : time;
constant max_time : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_value (
signal target : std_logic;
constant exp : std_logic;
constant min_time : time;
constant max_time : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_value (
signal target : std_logic_vector;
constant exp : std_logic_vector;
constant match_strictness : t_match_strictness;
constant min_time : time;
constant max_time : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_value (
signal target : std_logic_vector;
constant exp : std_logic_vector;
constant min_time : time;
constant max_time : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_value (
signal target : unsigned;
constant exp : unsigned;
constant min_time : time;
constant max_time : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_value (
signal target : signed;
constant exp : signed;
constant min_time : time;
constant max_time : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_value (
signal target : integer;
constant exp : integer;
constant min_time : time;
constant max_time : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_value (
signal target : real;
constant exp : real;
constant min_time : time;
constant max_time : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
-- Await Stable Procedures
procedure await_stable (
signal target : boolean;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_stable (
signal target : std_logic;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_stable (
signal target : in std_logic_vector;
constant stable_req : in time; -- Minimum stable requirement
constant stable_req_from : in t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : in time; -- Timeout if stable_req not achieved
constant timeout_from : in t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : in t_alert_level;
variable success : out boolean;
constant msg : in string;
constant scope : in string := C_TB_SCOPE_DEFAULT;
constant msg_id : in t_msg_id := ID_POS_ACK;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant caller_name : in string := ""
);
procedure await_stable (
signal target : std_logic_vector;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_stable (
signal target : unsigned;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_stable (
signal target : signed;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_stable (
signal target : integer;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_stable (
signal target : real;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
-- Await Stable Procedures without Mandatory Alert_Level
-- Await Stable Procedures
procedure await_stable (
signal target : boolean;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_stable (
signal target : std_logic;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_stable (
signal target : std_logic_vector;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_stable (
signal target : unsigned;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_stable (
signal target : signed;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_stable (
signal target : integer;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_stable (
signal target : real;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
-----------------------------------------------------
-- Pulse Generation Procedures
-----------------------------------------------------
procedure gen_pulse(
signal target : inout std_logic;
constant pulse_value : std_logic;
constant pulse_duration : time;
constant blocking_mode : t_blocking_mode;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout std_logic;
constant pulse_duration : time;
constant blocking_mode : t_blocking_mode;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout std_logic;
constant pulse_value : std_logic;
constant pulse_duration : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout std_logic;
constant pulse_duration : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout std_logic;
constant pulse_value : std_logic;
signal clock_signal : std_logic;
constant num_periods : natural;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout std_logic;
signal clock_signal : std_logic;
constant num_periods : natural;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout boolean;
constant pulse_value : boolean;
constant pulse_duration : time;
constant blocking_mode : t_blocking_mode;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout boolean;
constant pulse_duration : time;
constant blocking_mode : t_blocking_mode;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout boolean;
constant pulse_value : boolean;
constant pulse_duration : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout boolean;
constant pulse_duration : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout boolean;
constant pulse_value : boolean;
signal clock_signal : std_logic;
constant num_periods : natural;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout boolean;
signal clock_signal : std_logic;
constant num_periods : natural;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout std_logic_vector;
constant pulse_value : std_logic_vector;
constant pulse_duration : time;
constant blocking_mode : t_blocking_mode;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout std_logic_vector;
constant pulse_duration : time;
constant blocking_mode : t_blocking_mode;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout std_logic_vector;
constant pulse_value : std_logic_vector;
constant pulse_duration : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout std_logic_vector;
constant pulse_duration : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout std_logic_vector;
constant pulse_value : std_logic_vector;
signal clock_signal : std_logic;
constant num_periods : natural;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout std_logic_vector;
signal clock_signal : std_logic;
constant num_periods : natural;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
-----------------------------------------------------
-- Clock Generator Procedures
-----------------------------------------------------
procedure clock_generator(
signal clock_signal : inout std_logic;
constant clock_period : in time;
constant clock_high_percentage : in natural range 1 to 99 := 50
);
-- Overloaded version with duty cycle in time
procedure clock_generator(
signal clock_signal : inout std_logic;
constant clock_period : in time;
constant clock_high_time : in time
);
-- Overloaded version with clock count
procedure clock_generator(
signal clock_signal : inout std_logic;
signal clock_count : inout natural;
constant clock_period : in time;
constant clock_high_percentage : in natural range 1 to 99 := 50
);
-- Overloaded version with clock count and duty cycle in time
procedure clock_generator(
signal clock_signal : inout std_logic;
signal clock_count : inout natural;
constant clock_period : in time;
constant clock_high_time : in time
);
-- Overloaded version with clock enable and clock name
procedure clock_generator(
signal clock_signal : inout std_logic;
signal clock_ena : in boolean;
constant clock_period : in time;
constant clock_name : in string;
constant clock_high_percentage : in natural range 1 to 99 := 50
);
-- Overloaded version with clock enable, clock name
-- and duty cycle in time.
procedure clock_generator(
signal clock_signal : inout std_logic;
signal clock_ena : in boolean;
constant clock_period : in time;
constant clock_name : in string;
constant clock_high_time : in time
);
-- Overloaded version with clock enable, clock name
-- and clock count
procedure clock_generator(
signal clock_signal : inout std_logic;
signal clock_ena : in boolean;
signal clock_count : out natural;
constant clock_period : in time;
constant clock_name : in string;
constant clock_high_percentage : in natural range 1 to 99 := 50
);
-- Overloaded version with clock enable, clock name,
-- clock count and duty cycle in time.
procedure clock_generator(
signal clock_signal : inout std_logic;
signal clock_ena : in boolean;
signal clock_count : out natural;
constant clock_period : in time;
constant clock_name : in string;
constant clock_high_time : in time
);
-----------------------------------------------------
-- Adjustable Clock Generator Procedures
-----------------------------------------------------
procedure adjustable_clock_generator(
signal clock_signal : inout std_logic;
signal clock_ena : in boolean;
constant clock_period : in time;
signal clock_high_percentage : in natural range 0 to 100
);
procedure adjustable_clock_generator(
signal clock_signal : inout std_logic;
signal clock_ena : in boolean;
constant clock_period : in time;
constant clock_name : in string;
signal clock_high_percentage : in natural range 0 to 100
);
-- Overloaded version with clock enable, clock name
-- and clock count
procedure adjustable_clock_generator(
signal clock_signal : inout std_logic;
signal clock_ena : in boolean;
signal clock_count : out natural;
constant clock_period : in time;
constant clock_name : in string;
signal clock_high_percentage : in natural range 0 to 100
);
procedure deallocate_line_if_exists(
variable line_to_be_deallocated : inout line
);
-- ============================================================================
-- Synchronization methods
-- ============================================================================
-- method to block a global flag with the name flag_name
procedure block_flag(
constant flag_name : in string;
constant msg : in string;
constant already_blocked_severity : in t_alert_level := warning;
constant scope : in string := C_TB_SCOPE_DEFAULT
);
-- method to unblock a global flag with the name flag_name
procedure unblock_flag(
constant flag_name : in string;
constant msg : in string;
signal trigger : inout std_logic; -- Parameter must be global_trigger as method await_unblock_flag() uses that global signal to detect unblocking.
constant scope : in string := C_TB_SCOPE_DEFAULT
);
-- method to wait for the global flag with the name flag_name
procedure await_unblock_flag(
constant flag_name : in string;
constant timeout : in time;
constant msg : in string;
constant flag_returning : in t_flag_returning := KEEP_UNBLOCKED;
constant timeout_severity : in t_alert_level := error;
constant scope : in string := C_TB_SCOPE_DEFAULT
);
procedure await_barrier(
signal barrier_signal : inout std_logic;
constant timeout : in time;
constant msg : in string;
constant timeout_severity : in t_alert_level := error;
constant scope : in string := C_TB_SCOPE_DEFAULT
);
-------------------------------------------
-- await_semaphore_in_delta_cycles
-------------------------------------------
-- tries to lock the semaphore for C_NUM_SEMAPHORE_LOCK_TRIES in adaptations_pkg
procedure await_semaphore_in_delta_cycles(
variable semaphore : inout t_protected_semaphore
);
-------------------------------------------
-- release_semaphore
-------------------------------------------
-- releases the semaphore
procedure release_semaphore(
variable semaphore : inout t_protected_semaphore
);
-- ============================================================================
-- Watchdog-related
-- ============================================================================
procedure watchdog_timer(
signal watchdog_ctrl : in t_watchdog_ctrl;
constant timeout : time;
constant alert_level : t_alert_level := error;
constant msg : string := ""
);
procedure extend_watchdog(
signal watchdog_ctrl : inout t_watchdog_ctrl;
constant time_extend : time := 0 ns
);
procedure reinitialize_watchdog(
signal watchdog_ctrl : inout t_watchdog_ctrl;
constant timeout : time
);
procedure terminate_watchdog(
signal watchdog_ctrl : inout t_watchdog_ctrl
);
-- ============================================================================
-- generate_crc
-- ============================================================================
--
-- This function generate the CRC based on the input values. CRC is generated
-- MSb first.
--
-- Input criteria:
-- - Inputs have to be decending (CRC generated from high to low)
-- - crc_in must be one bit shorter than polynomial
--
-- Return vector is one bit shorter than polynomial
--
---------------------------------------------------------------------------------
impure function generate_crc(
constant data : in std_logic_vector;
constant crc_in : in std_logic_vector;
constant polynomial : in std_logic_vector
) return std_logic_vector;
-- slv array have to be acending
impure function generate_crc(
constant data : in t_slv_array;
constant crc_in : in std_logic_vector;
constant polynomial : in std_logic_vector
) return std_logic_vector;
end package methods_pkg;
--=================================================================================================
--=================================================================================================
--=================================================================================================
package body methods_pkg is
constant C_BURIED_SCOPE : string := "(Util buried)";
-- The following constants are not used. Report statements in the given functions allow elaboration time messages
constant C_BITVIS_LICENSE_INITIALISED : boolean := show_license(VOID);
constant C_BITVIS_LIBRARY_INFO_SHOWN : boolean := show_uvvm_utility_library_info(VOID);
constant C_BITVIS_LIBRARY_RELEASE_INFO_SHOWN : boolean := show_uvvm_utility_library_release_info(VOID);
-- ============================================================================
-- Initialisation and license
-- ============================================================================
-- -- Executed a single time ONLY
-- procedure pot_show_license(
-- constant dummy : in t_void
-- ) is
-- begin
-- if not shared_license_shown then
-- show_license(v_trial_license);
-- shared_license_shown := true;
-- end if;
-- end;
-- -- Executed a single time ONLY
-- procedure initialise_util(
-- constant dummy : in t_void
-- ) is
-- begin
-- set_log_file_name(C_LOG_FILE_NAME);
-- set_alert_file_name(C_ALERT_FILE_NAME);
-- shared_license_shown.set(1);
-- shared_initialised_util.set(true);
-- end;
procedure pot_initialise_util(
constant dummy : in t_void
) is
variable v_minimum_log_line_width : natural := 0;
begin
if not shared_initialised_util then
shared_initialised_util := true;
if not shared_log_file_name_is_set then
set_log_file_name(C_LOG_FILE_NAME);
end if;
if not shared_alert_file_name_is_set then
set_alert_file_name(C_ALERT_FILE_NAME);
end if;
if C_ENABLE_HIERARCHICAL_ALERTS then
initialize_hierarchy;
end if;
-- Check that all log widths are valid
v_minimum_log_line_width := v_minimum_log_line_width + C_LOG_PREFIX_WIDTH + C_LOG_TIME_WIDTH + 5; -- Add 5 for spaces
if not (C_SHOW_LOG_ID or C_SHOW_LOG_SCOPE) then
v_minimum_log_line_width := v_minimum_log_line_width + 10; -- Minimum length in order to wrap lines properly
else
if C_SHOW_LOG_ID then
v_minimum_log_line_width := v_minimum_log_line_width + C_LOG_MSG_ID_WIDTH;
end if;
if C_SHOW_LOG_SCOPE then
v_minimum_log_line_width := v_minimum_log_line_width + C_LOG_SCOPE_WIDTH;
end if;
end if;
bitvis_assert(C_LOG_LINE_WIDTH >= v_minimum_log_line_width, failure, "C_LOG_LINE_WIDTH is too low. Needs to higher than " & to_string(v_minimum_log_line_width) & ". ", C_SCOPE);
--show_license(VOID);
-- if C_SHOW_uvvm_utilITY_LIBRARY_INFO then
-- show_uvvm_utility_library_info(VOID);
-- end if;
-- if C_SHOW_uvvm_utilITY_LIBRARY_RELEASE_INFO then
-- show_uvvm_utility_library_release_info(VOID);
-- end if;
end if;
end;
procedure deallocate_line_if_exists(
variable line_to_be_deallocated : inout line
) is
begin
if line_to_be_deallocated /= null then
deallocate(line_to_be_deallocated);
end if;
end procedure deallocate_line_if_exists;
-- ============================================================================
-- File handling (that needs to use other utility methods)
-- ============================================================================
procedure check_file_open_status(
constant status : in file_open_status;
constant file_name : in string;
constant scope : in string := C_SCOPE
) is
begin
case status is
when open_ok =>
null; --**** logmsg (if log is open for write)
when status_error =>
alert(tb_warning, "File: " & file_name & " is already open", scope);
when name_error =>
alert(tb_error, "Cannot open file: " & file_name, scope);
when mode_error =>
alert(tb_error, "File: " & file_name & " exists, but cannot be opened in write mode", scope);
end case;
end;
procedure set_alert_file_name(
constant file_name : string := C_ALERT_FILE_NAME
) is
variable v_file_open_status : file_open_status;
begin
if C_WARNING_ON_LOG_ALERT_FILE_RUNTIME_RENAME and shared_alert_file_name_is_set then
warning("alert file name already set. Setting new alert file " & file_name);
end if;
shared_alert_file_name_is_set := true;
file_close(ALERT_FILE);
file_open(v_file_open_status, ALERT_FILE, file_name, write_mode);
check_file_open_status(v_file_open_status, file_name);
if now > 0 ns then -- Do not show note if set at the very start.
-- NOTE: We should usually use log() instead of report. However,
-- in this case, there is an issue with log() initialising
-- the log file and therefore blocking subsequent set_log_file_name().
report "alert file name set: " & file_name;
end if;
end;
procedure set_alert_file_name(
constant file_name : string := C_ALERT_FILE_NAME;
constant msg_id : t_msg_id
) is
variable v_file_open_status : file_open_status;
begin
deprecate(get_procedure_name_from_instance_name(file_name'instance_name), "msg_id parameter is no longer in use. Please call this procedure without the msg_id parameter.");
set_alert_file_name(file_name);
end;
procedure set_log_file_name(
constant file_name : string := C_LOG_FILE_NAME
) is
variable v_file_open_status : file_open_status;
begin
if C_WARNING_ON_LOG_ALERT_FILE_RUNTIME_RENAME and shared_log_file_name_is_set then
warning("log file name already set. Setting new log file " & file_name);
end if;
shared_log_file_name_is_set := true;
file_close(LOG_FILE);
file_open(v_file_open_status, LOG_FILE, file_name, write_mode);
check_file_open_status(v_file_open_status, file_name);
if now > 0 ns then -- Do not show note if set at the very start.
-- NOTE: We should usually use log() instead of report. However,
-- in this case, there is an issue with log() initialising
-- the alert file and therefore blocking subsequent set_alert_file_name().
report "log file name set: " & file_name;
end if;
end;
procedure set_log_file_name(
constant file_name : string := C_LOG_FILE_NAME;
constant msg_id : t_msg_id
) is
begin
-- msg_id is no longer in use. However, can not call deprecate() since Util may not
-- have opened a log file yet. Attempting to call deprecate() when there is no open
-- log file will cause a fatal error. Leaving this alone with no message.
set_log_file_name(file_name);
end;
-- ============================================================================
-- Log-related
-- ============================================================================
impure function align_log_time(
value : time
) return string is
variable v_line : line;
variable v_value_width : natural;
variable v_result : string(1 to 50); -- sufficient for any relevant time value
variable v_result_width : natural;
variable v_delimeter_pos : natural;
variable v_time_number_width : natural;
variable v_time_width : natural;
variable v_num_initial_blanks : integer;
variable v_found_decimal_point : boolean;
begin
-- 1. Store normal write (to string) and note width
write(v_line, value, left, 0, C_LOG_TIME_BASE); -- required as width is unknown
v_value_width := v_line'length;
v_result(1 to v_value_width) := v_line.all;
deallocate(v_line);
-- 2. Search for decimal point or space between number and unit
v_found_decimal_point := true; -- default
v_delimeter_pos := pos_of_leftmost('.', v_result(1 to v_value_width), 0);
if v_delimeter_pos = 0 then -- No decimal point found
v_found_decimal_point := false;
v_delimeter_pos := pos_of_leftmost(' ', v_result(1 to v_value_width), 0);
end if;
-- Potentially alert if time stamp is truncated.
if C_LOG_TIME_TRUNC_WARNING then
if not shared_warned_time_stamp_trunc then
if (C_LOG_TIME_DECIMALS < (v_value_width - 3 - v_delimeter_pos)) then
alert(TB_WARNING, "Time stamp has been truncated to " & to_string(C_LOG_TIME_DECIMALS) &
" decimal(s) in the next log message - settable in adaptations_pkg." &
" (Actual time stamp has more decimals than displayed) " &
"\nThis alert is shown once only.",
C_BURIED_SCOPE);
shared_warned_time_stamp_trunc := true;
end if;
end if;
end if;
-- 3. Derive Time number (integer or real)
if C_LOG_TIME_DECIMALS = 0 then
v_time_number_width := v_delimeter_pos - 1;
-- v_result as is
else -- i.e. a decimal value is required
if v_found_decimal_point then
v_result(v_value_width - 2 to v_result'right) := (others => '0'); -- Zero extend
else -- Shift right after integer part and add point
v_result(v_delimeter_pos + 1 to v_result'right) := v_result(v_delimeter_pos to v_result'right - 1);
v_result(v_delimeter_pos) := '.';
v_result(v_value_width - 1 to v_result'right) := (others => '0'); -- Zero extend
end if;
v_time_number_width := v_delimeter_pos + C_LOG_TIME_DECIMALS;
end if;
-- 4. Add time unit for full time specification
v_time_width := v_time_number_width + 3;
if C_LOG_TIME_BASE = ns then
v_result(v_time_number_width + 1 to v_time_width) := " ns";
else
v_result(v_time_number_width + 1 to v_time_width) := " ps";
end if;
-- 5. Prefix
v_num_initial_blanks := maximum(0, (C_LOG_TIME_WIDTH - v_time_width));
if v_num_initial_blanks > 0 then
v_result(v_num_initial_blanks + 1 to v_result'right) := v_result(1 to v_result'right - v_num_initial_blanks);
v_result(1 to v_num_initial_blanks) := fill_string(' ', v_num_initial_blanks);
v_result_width := C_LOG_TIME_WIDTH;
else
-- v_result as is
v_result_width := v_time_width;
end if;
return v_result(1 to v_result_width);
end function align_log_time;
-- Writes Line to a file without modifying the contents of the line
-- Not yet available in VHDL
procedure tee (
file file_handle : text;
variable my_line : inout line
) is
variable v_line : line;
begin
write (v_line, my_line.all);
writeline(file_handle, v_line);
deallocate(v_line);
end procedure tee;
-- Open, append/write to and close file. Also deallocates contents of the line
procedure write_to_file (
file_name : string;
open_mode : file_open_kind;
variable my_line : inout line
) is
file v_specified_file_pointer : text;
begin
file_open(v_specified_file_pointer, file_name, open_mode);
writeline(v_specified_file_pointer, my_line);
file_close(v_specified_file_pointer);
end procedure write_to_file;
procedure write_line_to_log_destination(
variable log_line : inout line;
constant log_destination : in t_log_destination := shared_default_log_destination;
constant log_file_name : in string := C_LOG_FILE_NAME;
constant open_mode : in file_open_kind := append_mode) is
begin
-- Write the info string to the target file
if log_file_name = "" and (log_destination = LOG_ONLY or log_destination = CONSOLE_AND_LOG) then
-- Output file specified, but file name was invalid.
alert(TB_ERROR, "log called with log_destination " & to_upper(to_string(log_destination)) & ", but log file name was empty.");
else
case log_destination is
when CONSOLE_AND_LOG =>
tee(OUTPUT, log_line); -- write to transcript, while keeping the line contents
-- write to file
if log_file_name = C_LOG_FILE_NAME then
-- If the log file is the default file, it is not necessary to open and close it again
writeline(LOG_FILE, log_line);
else
-- If the log file is a custom file name, the file will have to be opened.
write_to_file(log_file_name, open_mode, log_line);
end if;
when CONSOLE_ONLY =>
writeline(OUTPUT, log_line); -- Write to console and deallocate line
when LOG_ONLY =>
if log_file_name = C_LOG_FILE_NAME then
-- If the log file is the default file, it is not necessary to open and close it again
writeline(LOG_FILE, log_line);
else
-- If the log file is a custom file name, the file will have to be opened.
write_to_file(log_file_name, open_mode, log_line);
end if;
end case;
end if;
end procedure;
procedure log(
msg_id : t_msg_id;
msg : string;
scope : string := C_TB_SCOPE_DEFAULT;
msg_id_panel : t_msg_id_panel := shared_msg_id_panel; -- compatible with old code
log_destination : t_log_destination := shared_default_log_destination;
log_file_name : string := C_LOG_FILE_NAME;
open_mode : file_open_kind := append_mode
) is
variable v_msg : line;
variable v_msg_indent : line;
variable v_msg_indent_width : natural;
variable v_info : line;
variable v_info_final : line;
variable v_log_msg_id : string(1 to C_LOG_MSG_ID_WIDTH);
variable v_log_scope : string(1 to C_LOG_SCOPE_WIDTH);
variable v_log_pre_msg_width : natural;
variable v_idx : natural := 1;
begin
-- Check if message ID is enabled
if (msg_id_panel(msg_id) = ENABLED) then
pot_initialise_util(VOID); -- Only executed the first time called
-- Prepare strings for msg_id and scope
v_log_msg_id := to_upper(justify(to_string(msg_id), left, C_LOG_MSG_ID_WIDTH, KEEP_LEADING_SPACE, ALLOW_TRUNCATE));
if (scope = "") then
v_log_scope := justify("(non scoped)", left, C_LOG_SCOPE_WIDTH, KEEP_LEADING_SPACE, ALLOW_TRUNCATE);
else
v_log_scope := justify(to_string(scope), left, C_LOG_SCOPE_WIDTH, KEEP_LEADING_SPACE, ALLOW_TRUNCATE);
end if;
-- Handle actual log info line
-- First write all fields preceeding the actual message - in order to measure their width
-- (Prefix is taken care of later)
write(v_info,
return_string_if_true(v_log_msg_id, C_SHOW_LOG_ID) & -- Optional
" " & align_log_time(now) & " " &
return_string_if_true(v_log_scope, C_SHOW_LOG_SCOPE) & " "); -- Optional
v_log_pre_msg_width := v_info'length; -- Width of string preceeding the actual message
-- Handle \r as potential initial open line
if msg'length > 1 then
if C_USE_BACKSLASH_R_AS_LF then
loop
if (msg(v_idx to v_idx+1) = "\r") then
write(v_info_final, LF); -- Start transcript with an empty line
v_idx := v_idx + 2;
else
write(v_msg, remove_initial_chars(msg, v_idx-1));
exit;
end if;
end loop;
else
write(v_msg, msg);
end if;
end if;
-- Handle dedicated ID indentation.
write(v_msg_indent, to_string(C_MSG_ID_INDENT(msg_id)));
v_msg_indent_width := v_msg_indent'length;
write(v_info, v_msg_indent.all);
deallocate_line_if_exists(v_msg_indent);
-- Then add the message it self (after replacing \n with LF
if msg'length > 1 then
write(v_info, to_string(replace_backslash_n_with_lf(v_msg.all)));
end if;
deallocate_line_if_exists(v_msg);
if not C_SINGLE_LINE_LOG then
-- Modify and align info-string if additional lines are required (after wrapping lines)
wrap_lines(v_info, 1, v_log_pre_msg_width + v_msg_indent_width + 1, C_LOG_LINE_WIDTH-C_LOG_PREFIX_WIDTH);
else
-- Remove line feed character if
-- single line log/alert enabled
replace(v_info, LF, ' ');
end if;
-- Handle potential log header by including info-lines inside the log header format and update of waveview header.
if (msg_id = ID_LOG_HDR) then
write(v_info_final, LF & LF);
-- also update the Log header string
shared_current_log_hdr.normal := justify(msg, left, C_LOG_HDR_FOR_WAVEVIEW_WIDTH, KEEP_LEADING_SPACE, ALLOW_TRUNCATE);
shared_log_hdr_for_waveview := justify(msg, left, C_LOG_HDR_FOR_WAVEVIEW_WIDTH, KEEP_LEADING_SPACE, ALLOW_TRUNCATE);
elsif (msg_id = ID_LOG_HDR_LARGE) then
write(v_info_final, LF & LF);
shared_current_log_hdr.large := justify(msg, left, C_LOG_HDR_FOR_WAVEVIEW_WIDTH, KEEP_LEADING_SPACE, ALLOW_TRUNCATE);
write(v_info_final, fill_string('=', (C_LOG_LINE_WIDTH - C_LOG_PREFIX_WIDTH)) & LF);
elsif (msg_id = ID_LOG_HDR_XL) then
write(v_info_final, LF & LF);
shared_current_log_hdr.xl := justify(msg, left, C_LOG_HDR_FOR_WAVEVIEW_WIDTH, KEEP_LEADING_SPACE, ALLOW_TRUNCATE);
write(v_info_final, LF & fill_string('#', (C_LOG_LINE_WIDTH - C_LOG_PREFIX_WIDTH))& LF & LF);
end if;
write(v_info_final, v_info.all); -- include actual info
deallocate_line_if_exists(v_info);
-- Handle rest of potential log header
if (msg_id = ID_LOG_HDR) then
write(v_info_final, LF & fill_string('-', (C_LOG_LINE_WIDTH - C_LOG_PREFIX_WIDTH)));
elsif (msg_id = ID_LOG_HDR_LARGE) then
write(v_info_final, LF & fill_string('=', (C_LOG_LINE_WIDTH - C_LOG_PREFIX_WIDTH)));
elsif (msg_id = ID_LOG_HDR_XL) then
write(v_info_final, LF & LF & fill_string('#', (C_LOG_LINE_WIDTH - C_LOG_PREFIX_WIDTH)) & LF & LF);
end if;
-- Add prefix to all lines
prefix_lines(v_info_final);
-- Write the info string to the target file
if log_file_name = "" and (log_destination = LOG_ONLY or log_destination = CONSOLE_AND_LOG) then
-- Output file specified, but file name was invalid.
alert(TB_ERROR, "log called with log_destination " & to_upper(to_string(log_destination)) & ", but log file name was empty.");
else
case log_destination is
when CONSOLE_AND_LOG =>
tee(OUTPUT, v_info_final); -- write to transcript, while keeping the line contents
-- write to file
if log_file_name = C_LOG_FILE_NAME then
-- If the log file is the default file, it is not necessary to open and close it again
writeline(LOG_FILE, v_info_final);
else
-- If the log file is a custom file name, the file will have to be opened.
write_to_file(log_file_name, open_mode, v_info_final);
end if;
when CONSOLE_ONLY =>
writeline(OUTPUT, v_info_final); -- Write to console and deallocate line
when LOG_ONLY =>
if log_file_name = C_LOG_FILE_NAME then
-- If the log file is the default file, it is not necessary to open and close it again
writeline(LOG_FILE, v_info_final);
else
-- If the log file is a custom file name, the file will have to be opened.
write_to_file(log_file_name, open_mode, v_info_final);
end if;
end case;
deallocate_line_if_exists(v_info_final);
end if;
end if;
end;
-- Calls overloaded log procedure with default msg_id
procedure log(
msg : string;
scope : string := C_TB_SCOPE_DEFAULT;
msg_id_panel : t_msg_id_panel := shared_msg_id_panel; -- compatible with old code
log_destination : t_log_destination := shared_default_log_destination;
log_file_name : string := C_LOG_FILE_NAME;
open_mode : file_open_kind := append_mode
) is
begin
log(C_TB_MSG_ID_DEFAULT, msg, scope, msg_id_panel, log_destination, log_file_name, open_mode);
end procedure log;
-- Logging for multi line text. Also deallocates the text_block, for consistency.
procedure log_text_block(
msg_id : t_msg_id;
variable text_block : inout line;
formatting : t_log_format; -- FORMATTED or UNFORMATTED
msg_header : string := "";
scope : string := C_TB_SCOPE_DEFAULT;
msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
log_if_block_empty : t_log_if_block_empty := WRITE_HDR_IF_BLOCK_EMPTY;
log_destination : t_log_destination := shared_default_log_destination;
log_file_name : string := C_LOG_FILE_NAME;
open_mode : file_open_kind := append_mode
) is
variable v_text_block_empty_note : string(1 to 26) := "Note: Text block was empty";
variable v_header_line : line;
variable v_log_body : line;
variable v_text_block_is_empty : boolean;
begin
if ((log_file_name = "") and ((log_destination = CONSOLE_AND_LOG) or (log_destination = LOG_ONLY))) then
alert(TB_ERROR, "log_text_block called with log_destination " & to_upper(to_string(log_destination)) & ", but log file name was empty.");
-- Check if message ID is enabled
elsif (msg_id_panel(msg_id) = ENABLED) then
pot_initialise_util(VOID); -- Only executed the first time called
v_text_block_is_empty := (text_block = null);
if(formatting = UNFORMATTED) then
if(not v_text_block_is_empty) then
-- Write the info string to the target file without any header, footer or indentation
case log_destination is
when CONSOLE_AND_LOG =>
tee(OUTPUT, text_block); -- Write to console, but keep text_block
-- Write to log and deallocate text_block. Open specified file if not open.
if log_file_name = C_LOG_FILE_NAME then
writeline(LOG_FILE, text_block);
else
write_to_file(log_file_name, open_mode, text_block);
end if;
when CONSOLE_ONLY =>
writeline(OUTPUT, text_block); -- Write to console and deallocate text_block
when LOG_ONLY =>
-- Write to log and deallocate text_block. Open specified file if not open.
if log_file_name = C_LOG_FILE_NAME then
writeline(LOG_FILE, text_block);
else
write_to_file(log_file_name, open_mode, text_block);
end if;
end case;
end if;
elsif not (v_text_block_is_empty and (log_if_block_empty = SKIP_LOG_IF_BLOCK_EMPTY)) then
-- Add and print header
write(v_header_line, LF & LF & fill_string('*', (C_LOG_LINE_WIDTH - C_LOG_PREFIX_WIDTH)));
prefix_lines(v_header_line);
-- Add header underline, body and footer
write(v_log_body, fill_string('-', (C_LOG_LINE_WIDTH - C_LOG_PREFIX_WIDTH)) & LF);
if v_text_block_is_empty then
if log_if_block_empty = NOTIFY_IF_BLOCK_EMPTY then
write(v_log_body, v_text_block_empty_note); -- Notify that the text block was empty
end if;
else
write(v_log_body, text_block.all); -- include input text
end if;
write(v_log_body, LF & fill_string('*', (C_LOG_LINE_WIDTH - C_LOG_PREFIX_WIDTH)) & LF);
prefix_lines(v_log_body);
case log_destination is
when CONSOLE_AND_LOG =>
-- Write header to console
tee(OUTPUT, v_header_line);
-- Write header to file, and open/close if not default log file
if log_file_name = C_LOG_FILE_NAME then
writeline(LOG_FILE, v_header_line);
else
write_to_file(log_file_name, open_mode, v_header_line);
end if;
-- Write header message to specified destination
log(msg_id, msg_header, scope, msg_id_panel, CONSOLE_AND_LOG, log_file_name, append_mode);
-- Write log body to console
tee(OUTPUT, v_log_body);
-- Write log body to specified file
if log_file_name = C_LOG_FILE_NAME then
writeline(LOG_FILE, v_log_body);
else
write_to_file(log_file_name, append_mode, v_log_body);
end if;
when CONSOLE_ONLY =>
-- Write to console and deallocate all lines
writeline(OUTPUT, v_header_line);
log(msg_id, msg_header, scope, msg_id_panel, CONSOLE_ONLY);
writeline(OUTPUT, v_log_body);
when LOG_ONLY =>
-- Write to log and deallocate text_block. Open specified file if not open.
if log_file_name = C_LOG_FILE_NAME then
writeline(LOG_FILE, v_header_line);
log(msg_id, msg_header, scope, msg_id_panel, LOG_ONLY);
writeline(LOG_FILE, v_log_body);
else
write_to_file(log_file_name, open_mode, v_header_line);
log(msg_id, msg_header, scope, msg_id_panel, LOG_ONLY, log_file_name, append_mode);
write_to_file(log_file_name, append_mode, v_log_body);
end if;
end case;
-- Deallocate text block to give writeline()-like behaviour
-- for formatted output
deallocate(v_header_line);
deallocate(v_log_body);
deallocate(text_block);
end if;
end if;
end;
procedure enable_log_msg(
constant msg_id : t_msg_id;
variable msg_id_panel : inout t_msg_id_panel;
constant msg : string := "";
constant scope : string := C_TB_SCOPE_DEFAULT;
constant quietness : t_quietness := NON_QUIET
) is
begin
case msg_id is
when ID_NEVER =>
null; -- Shall not be possible to enable
tb_warning("enable_log_msg() ignored for " & to_upper(to_string(msg_id)) & " (not allowed). " & add_msg_delimiter(msg), scope);
when ALL_MESSAGES =>
for i in t_msg_id'left to t_msg_id'right loop
msg_id_panel(i) := ENABLED;
end loop;
msg_id_panel(ID_NEVER) := DISABLED;
msg_id_panel(ID_BITVIS_DEBUG) := DISABLED;
if quietness = NON_QUIET then
log(ID_LOG_MSG_CTRL, "enable_log_msg(" & to_upper(to_string(msg_id)) & "). " & add_msg_delimiter(msg), scope);
end if;
when others =>
msg_id_panel(msg_id) := ENABLED;
if quietness = NON_QUIET then
log(ID_LOG_MSG_CTRL, "enable_log_msg(" & to_upper(to_string(msg_id)) & "). " & add_msg_delimiter(msg), scope);
end if;
end case;
end;
procedure enable_log_msg(
msg_id : t_msg_id;
msg : string;
quietness : t_quietness := NON_QUIET;
scope : string := C_TB_SCOPE_DEFAULT
) is
begin
enable_log_msg(msg_id, shared_msg_id_panel, msg, scope, quietness);
end;
procedure enable_log_msg(
msg_id : t_msg_id;
quietness : t_quietness := NON_QUIET;
scope : string := C_TB_SCOPE_DEFAULT
) is
begin
enable_log_msg(msg_id, shared_msg_id_panel, "", scope, quietness);
end;
procedure disable_log_msg(
constant msg_id : t_msg_id;
variable msg_id_panel : inout t_msg_id_panel;
constant msg : string := "";
constant scope : string := C_TB_SCOPE_DEFAULT;
constant quietness : t_quietness := NON_QUIET
) is
begin
case msg_id is
when ALL_MESSAGES =>
if quietness = NON_QUIET then
log(ID_LOG_MSG_CTRL, "disable_log_msg(" & to_upper(to_string(msg_id)) & "). " & add_msg_delimiter(msg), scope);
end if;
for i in t_msg_id'left to t_msg_id'right loop
msg_id_panel(i) := DISABLED;
end loop;
msg_id_panel(ID_LOG_MSG_CTRL) := ENABLED; -- keep
when others =>
msg_id_panel(msg_id) := DISABLED;
if quietness = NON_QUIET then
log(ID_LOG_MSG_CTRL, "disable_log_msg(" & to_upper(to_string(msg_id)) & "). " & add_msg_delimiter(msg), scope);
end if;
end case;
end;
procedure disable_log_msg(
msg_id : t_msg_id;
msg : string;
quietness : t_quietness := NON_QUIET;
scope : string := C_TB_SCOPE_DEFAULT
) is
begin
disable_log_msg(msg_id, shared_msg_id_panel, msg, scope, quietness);
end;
procedure disable_log_msg(
msg_id : t_msg_id;
quietness : t_quietness := NON_QUIET;
scope : string := C_TB_SCOPE_DEFAULT
) is
begin
disable_log_msg(msg_id, shared_msg_id_panel, "", scope, quietness);
end;
impure function is_log_msg_enabled(
msg_id : t_msg_id;
msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) return boolean is
begin
if msg_id_panel(msg_id) = ENABLED then
return true;
else
return false;
end if;
end;
procedure set_log_destination(
constant log_destination : t_log_destination;
constant quietness : t_quietness := NON_QUIET
) is
begin
if quietness = NON_QUIET then
log(ID_LOG_MSG_CTRL, "Changing log destination to " & to_string(log_destination) & ". Was " & to_string(shared_default_log_destination) & ". ", C_TB_SCOPE_DEFAULT);
end if;
shared_default_log_destination := log_destination;
end;
-- ============================================================================
-- Check counters related
-- ============================================================================
-- Shared variable for all the check counters
shared variable protected_check_counters : t_protected_check_counters;
-- ============================================================================
-- Alert-related
-- ============================================================================
-- Shared variable for all the alert counters for different attention
shared variable protected_alert_attention_counters : t_protected_alert_attention_counters;
procedure alert(
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
) is
variable v_msg : line; -- msg after pot. replacement of \n
variable v_info : line;
constant C_ATTENTION : t_attention := get_alert_attention(alert_level);
begin
if alert_level /= NO_ALERT then
pot_initialise_util(VOID); -- Only executed the first time called
if C_ENABLE_HIERARCHICAL_ALERTS then
-- Call the hierarchical alert function
hierarchical_alert(alert_level, to_string(msg), to_string(scope), C_ATTENTION);
else
-- Perform the non-hierarchical alert function
write(v_msg, replace_backslash_n_with_lf(to_string(msg)));
-- 1. Increase relevant alert counter. Exit if ignore is set for this alert type.
if get_alert_attention(alert_level) = IGNORE then
-- protected_alert_counters.increment(alert_level, IGNORE);
increment_alert_counter(alert_level, IGNORE);
else
--protected_alert_counters.increment(alert_level, REGARD);
increment_alert_counter(alert_level, REGARD);
-- 2. Write first part of alert message
-- Serious alerts need more attention - thus more space and lines
if (alert_level > MANUAL_CHECK) then
write(v_info, LF & fill_string('=', C_LOG_INFO_WIDTH));
end if;
write(v_info, LF & "*** ");
-- 3. Remove line feed character (LF)
-- if single line alert enabled.
if not C_SINGLE_LINE_ALERT then
write(v_info, to_upper(to_string(alert_level)) & " #" & to_string(get_alert_counter(alert_level)) & " ***" & LF &
justify(to_string(now, C_LOG_TIME_BASE), right, C_LOG_TIME_WIDTH) & " " & to_string(scope) & LF &
wrap_lines(v_msg.all, C_LOG_TIME_WIDTH + 4, C_LOG_TIME_WIDTH + 4, C_LOG_INFO_WIDTH));
else
replace(v_msg, LF, ' ');
write(v_info, to_upper(to_string(alert_level)) & " #" & to_string(get_alert_counter(alert_level)) & " ***" &
justify(to_string(now, C_LOG_TIME_BASE), right, C_LOG_TIME_WIDTH) & " " & to_string(scope) &
" " & v_msg.all);
end if;
deallocate_line_if_exists(v_msg);
-- 4. Write stop message if stop-limit is reached for number of this alert
if (get_alert_stop_limit(alert_level) /= 0) and
(get_alert_counter(alert_level) >= get_alert_stop_limit(alert_level)) then
write(v_info, LF & LF & "Simulator has been paused as requested after " &
to_string(get_alert_counter(alert_level)) & " " &
to_upper(to_string(alert_level)) & LF);
if (alert_level = MANUAL_CHECK) then
write(v_info, "Carry out above check." & LF &
"Then continue simulation from within simulator." & LF);
else
write(v_info, string'("*** To find the root cause of this alert, " &
"step out the HDL calling stack in your simulator. ***" & LF &
"*** For example, step out until you reach the call from the test sequencer. ***"));
end if;
end if;
-- 5. Write last part of alert message
if (alert_level > MANUAL_CHECK) then
write(v_info, LF & fill_string('=', C_LOG_INFO_WIDTH) & LF & LF);
else
write(v_info, LF);
end if;
prefix_lines(v_info);
tee(OUTPUT, v_info);
tee(ALERT_FILE, v_info);
writeline(LOG_FILE, v_info);
deallocate_line_if_exists(v_info);
-- 6. Stop simulation if stop-limit is reached for number of this alert
if (get_alert_stop_limit(alert_level) /= 0) then
if (get_alert_counter(alert_level) >= get_alert_stop_limit(alert_level)) then
if C_USE_STD_STOP_ON_ALERT_STOP_LIMIT then
std.env.stop(1);
else
assert false report "This single Failure line has been provoked to stop the simulation. See alert-message above" severity failure;
end if;
end if;
end if;
end if;
end if;
end if;
end;
-- Dedicated alert-procedures all alert levels (less verbose - as 2 rather than 3 parameters...)
procedure note(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
alert(note, msg, scope);
end;
procedure tb_note(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
alert(tb_note, msg, scope);
end;
procedure warning(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
alert(warning, msg, scope);
end;
procedure tb_warning(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
alert(tb_warning, msg, scope);
end;
procedure manual_check(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
alert(manual_check, msg, scope);
end;
procedure error(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
alert(error, msg, scope);
end;
procedure tb_error(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
alert(tb_error, msg, scope);
end;
procedure failure(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
alert(failure, msg, scope);
end;
procedure tb_failure(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
alert(tb_failure, msg, scope);
end;
procedure increment_expected_alerts(
constant alert_level : t_alert_level;
constant number : natural := 1;
constant msg : string := "";
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
if alert_level = NO_ALERT then
alert(TB_WARNING, "increment_expected_alerts not allowed for alert_level NO_ALERT. " & add_msg_delimiter(msg), scope);
else
if not C_ENABLE_HIERARCHICAL_ALERTS then
increment_alert_counter(alert_level, EXPECT, number);
log(ID_UTIL_SETUP, "incremented expected " & to_upper(to_string(alert_level)) & "s by " & to_string(number) & ". " & add_msg_delimiter(msg), scope);
else
increment_expected_alerts(C_BASE_HIERARCHY_LEVEL, alert_level, number);
end if;
end if;
end;
-- Arguments:
-- - order = FINAL : print out Simulation Success/Fail
procedure report_alert_counters(
constant order : in t_order
) is
begin
pot_initialise_util(VOID); -- Only executed the first time called
if not C_ENABLE_HIERARCHICAL_ALERTS then
protected_alert_attention_counters.to_string(order);
else
print_hierarchical_log(order);
end if;
end;
-- This version (with the t_void argument) is kept for backwards compatibility
procedure report_alert_counters(
constant dummy : in t_void
) is
begin
report_alert_counters(FINAL); -- Default when calling this old method is order=FINAL
end;
procedure report_global_ctrl(
constant dummy : in t_void
) is
constant prefix : string := C_LOG_PREFIX & " ";
variable v_line : line;
begin
pot_initialise_util(VOID); -- Only executed the first time called
write(v_line,
LF &
fill_string('-', (C_LOG_LINE_WIDTH - prefix'length)) & LF &
"*** REPORT OF GLOBAL CTRL ***" & LF &
fill_string('-', (C_LOG_LINE_WIDTH - prefix'length)) & LF &
" IGNORE STOP_LIMIT" & LF);
for i in note to t_alert_level'right loop
write(v_line, " " & to_upper(to_string(i, 13, left)) & ": "); -- Severity
write(v_line, to_string(get_alert_attention(i), 7, right) & " "); -- column 1
write(v_line, to_string(integer'(get_alert_stop_limit(i)), 6, right, KEEP_LEADING_SPACE) & LF); -- column 2
end loop;
write(v_line, fill_string('-', (C_LOG_LINE_WIDTH - prefix'length)) & LF);
wrap_lines(v_line, 1, 1, C_LOG_LINE_WIDTH-prefix'length);
prefix_lines(v_line, prefix);
-- Write the info string to the target file
tee(OUTPUT, v_line);
writeline(LOG_FILE, v_line);
deallocate(v_line);
end;
procedure report_msg_id_panel(
constant dummy : in t_void
) is
constant prefix : string := C_LOG_PREFIX & " ";
variable v_line : line;
begin
pot_initialise_util(VOID); -- Only executed the first time called
write(v_line,
LF &
fill_string('-', (C_LOG_LINE_WIDTH - prefix'length)) & LF &
"*** REPORT OF MSG ID PANEL ***" & LF &
fill_string('-', (C_LOG_LINE_WIDTH - prefix'length)) & LF &
" " & justify("ID", left, C_LOG_MSG_ID_WIDTH) & " Status" & LF &
" " & fill_string('-', C_LOG_MSG_ID_WIDTH) & " ------" & LF);
for i in t_msg_id'left to t_msg_id'right loop
if ((i /= ALL_MESSAGES) and ((i /= NO_ID) and (i /= ID_NEVER))) then -- report all but ID_NEVER, NO_ID and ALL_MESSAGES
write(v_line, " " & to_upper(to_string(i, C_LOG_MSG_ID_WIDTH+5, left)) & ": "); -- MSG_ID
write(v_line, to_upper(to_string(shared_msg_id_panel(i))) & LF); -- Enabled/disabled
end if;
end loop;
write(v_line, fill_string('-', (C_LOG_LINE_WIDTH - prefix'length)) & LF);
wrap_lines(v_line, 1, 1, C_LOG_LINE_WIDTH-prefix'length);
prefix_lines(v_line, prefix);
-- Write the info string to the target file
tee(OUTPUT, v_line);
writeline(LOG_FILE, v_line);
deallocate(v_line);
end;
procedure set_alert_attention(
alert_level : t_alert_level;
attention : t_attention;
msg : string := ""
) is
begin
if alert_level = NO_ALERT then
tb_warning("set_alert_attention not allowed for alert_level NO_ALERT (always IGNORE).");
else
check_value(attention = IGNORE or attention = REGARD, TB_ERROR,
"set_alert_attention only supported for IGNORE and REGARD", C_BURIED_SCOPE, ID_NEVER);
shared_alert_attention(alert_level) := attention;
log(ID_ALERT_CTRL, "set_alert_attention(" & to_upper(to_string(alert_level)) & ", " & to_string(attention) & "). " & add_msg_delimiter(msg));
end if;
end;
impure function get_alert_attention(
alert_level : t_alert_level
) return t_attention is
begin
if alert_level = NO_ALERT then
return IGNORE;
else
return shared_alert_attention(alert_level);
end if;
end;
procedure set_alert_stop_limit(
alert_level : t_alert_level;
value : natural
) is
begin
if alert_level = NO_ALERT then
tb_warning("set_alert_stop_limit not allowed for alert_level NO_ALERT (stop limit always 0).");
else
if not C_ENABLE_HIERARCHICAL_ALERTS then
shared_stop_limit(alert_level) := value;
-- Evaluate new stop limit in case it is less than or equal to the current alert counter for this alert level
-- If that is the case, a new alert with the same alert level shall be triggered.
if (get_alert_stop_limit(alert_level) /= 0) and
(get_alert_counter(alert_level) >= get_alert_stop_limit(alert_level)) then
alert(alert_level, "Alert stop limit for " & to_upper(to_string(alert_level)) & " set to " & to_string(value) &
", which is lower than the current " & to_upper(to_string(alert_level)) & " count (" & to_string(get_alert_counter(alert_level)) & ").");
end if;
else
-- If hierarchical alerts enabled, update top level
-- alert stop limit.
set_hierarchical_alert_top_level_stop_limit(alert_level, value);
end if;
end if;
end;
impure function get_alert_stop_limit(
alert_level : t_alert_level
) return natural is
begin
if alert_level = NO_ALERT then
return 0;
else
if not C_ENABLE_HIERARCHICAL_ALERTS then
return shared_stop_limit(alert_level);
else
return get_hierarchical_alert_top_level_stop_limit(alert_level);
end if;
end if;
end;
impure function get_alert_counter(
alert_level : t_alert_level;
attention : t_attention := REGARD
) return natural is
begin
return protected_alert_attention_counters.get(alert_level, attention);
end;
procedure increment_alert_counter(
alert_level : t_alert_level;
attention : t_attention := REGARD; -- regard, expect, ignore
number : natural := 1
) is
type alert_array is array (1 to 6) of t_alert_level;
constant alert_check_array : alert_array := (warning, TB_WARNING, error, TB_ERROR, failure, TB_FAILURE);
alias found_unexpected_simulation_warnings_or_worse is shared_uvvm_status.found_unexpected_simulation_warnings_or_worse;
alias found_unexpected_simulation_errors_or_worse is shared_uvvm_status.found_unexpected_simulation_errors_or_worse;
alias mismatch_on_expected_simulation_warnings_or_worse is shared_uvvm_status.mismatch_on_expected_simulation_warnings_or_worse;
alias mismatch_on_expected_simulation_errors_or_worse is shared_uvvm_status.mismatch_on_expected_simulation_errors_or_worse;
begin
protected_alert_attention_counters.increment(alert_level, attention, number);
-- Update simulation status
if (attention = REGARD) or (attention = EXPECT) then
if (alert_level /= NO_ALERT) and (alert_level /= note) and (alert_level /= TB_NOTE) and (alert_level /= MANUAL_CHECK) then
found_unexpected_simulation_warnings_or_worse := 0; -- default
found_unexpected_simulation_errors_or_worse := 0; -- default
mismatch_on_expected_simulation_warnings_or_worse := 0; -- default
mismatch_on_expected_simulation_errors_or_worse := 0; -- default
-- Compare expected and current allerts
for i in 1 to alert_check_array'high loop
if (get_alert_counter(alert_check_array(i), REGARD) /= get_alert_counter(alert_check_array(i), EXPECT)) then
-- MISMATCH
-- warning or worse
mismatch_on_expected_simulation_warnings_or_worse := 1;
-- error or worse
if not(alert_check_array(i) = warning) and not(alert_check_array(i) = TB_WARNING) then
mismatch_on_expected_simulation_errors_or_worse := 1;
end if;
-- FOUND UNEXPECTED ALERT
if (get_alert_counter(alert_check_array(i), REGARD) > get_alert_counter(alert_check_array(i), EXPECT)) then
-- warning and worse
found_unexpected_simulation_warnings_or_worse := 1;
-- error and worse
if not(alert_check_array(i) = warning) and not(alert_check_array(i) = TB_WARNING) then
found_unexpected_simulation_errors_or_worse := 1;
end if;
end if;
end if;
end loop;
end if;
end if;
end;
procedure increment_expected_alerts_and_stop_limit(
constant alert_level : t_alert_level;
constant number : natural := 1;
constant msg : string := "";
constant scope : string := C_TB_SCOPE_DEFAULT
) is
variable v_alert_stop_limit : natural := get_alert_stop_limit(alert_level);
begin
increment_expected_alerts(alert_level, number, msg, scope);
set_alert_stop_limit(alert_level, v_alert_stop_limit + number);
end;
procedure report_check_counters(
constant order : in t_order
) is
begin
protected_check_counters.to_string(order);
end procedure report_check_counters;
procedure report_check_counters(
constant dummy : in t_void
) is
begin
report_check_counters(FINAL);
end procedure report_check_counters;
-- ============================================================================
-- Deprecation message
-- ============================================================================
procedure deprecate(
caller_name : string;
constant msg : string := ""
) is
variable v_found : boolean;
begin
v_found := false;
if C_DEPRECATE_SETTING /= NO_DEPRECATE then -- only perform if deprecation enabled
l_find_caller_name_in_list :
for i in deprecated_subprogram_list'range loop
if deprecated_subprogram_list(i) = justify(caller_name, right, 100) then
v_found := true;
exit l_find_caller_name_in_list;
end if;
end loop;
if v_found then
-- Has already been printed.
if C_DEPRECATE_SETTING = ALWAYS_DEPRECATE then
log(ID_UTIL_SETUP, "Sub-program " & caller_name & " is outdated and has been replaced by another sub-program." & LF & msg);
else -- C_DEPRECATE_SETTING = DEPRECATE_ONCE
null;
end if;
else
-- Has not been printed yet.
l_insert_caller_name_in_first_available :
for i in deprecated_subprogram_list'range loop
if deprecated_subprogram_list(i) = justify("", right, 100) then
deprecated_subprogram_list(i) := justify(caller_name, right, 100);
exit l_insert_caller_name_in_first_available;
end if;
end loop;
log(ID_UTIL_SETUP, "Sub-program " & caller_name & " is outdated and has been replaced by another sub-program." & LF & msg);
end if;
end if;
end;
-- ============================================================================
-- Non time consuming checks
-- ============================================================================
-- NOTE: Index in range N downto 0, with -1 meaning not found
function idx_leftmost_p1_in_p2(
target : std_logic;
vector : std_logic_vector
) return integer is
alias a_vector : std_logic_vector(vector'length - 1 downto 0) is vector;
constant result_if_not_found : integer := -1; -- To indicate not found
begin
bitvis_assert(vector'length > 0, error, "idx_leftmost_p1_in_p2()", "String input is empty");
for i in a_vector'left downto a_vector'right loop
if (a_vector(i) = target) then
return i;
end if;
end loop;
return result_if_not_found;
end;
-- Matching if same width or only zeros in "extended width"
function matching_widths(
value1 : std_logic_vector;
value2 : std_logic_vector
) return boolean is
-- Normalize vectors to (N downto 0)
alias a_value1 : std_logic_vector(value1'length - 1 downto 0) is value1;
alias a_value2 : std_logic_vector(value2'length - 1 downto 0) is value2;
begin
if (a_value1'left >= maximum(idx_leftmost_p1_in_p2('1', a_value2), 0) and
a_value1'left >= maximum(idx_leftmost_p1_in_p2('H', a_value2), 0) and
a_value1'left >= maximum(idx_leftmost_p1_in_p2('Z', a_value2), 0)) and
(a_value2'left >= maximum(idx_leftmost_p1_in_p2('1', a_value1), 0) and
a_value2'left >= maximum(idx_leftmost_p1_in_p2('H', a_value1), 0) and
a_value2'left >= maximum(idx_leftmost_p1_in_p2('Z', a_value1), 0)) then
return true;
else
return false;
end if;
end;
function matching_widths(
value1 : unsigned;
value2 : unsigned
) return boolean is
begin
return matching_widths(std_logic_vector(value1), std_logic_vector(value2));
end;
function matching_widths(
value1 : signed;
value2 : signed
) return boolean is
begin
return matching_widths(std_logic_vector(value1), std_logic_vector(value2));
end;
-- Compare values, but ignore any leading zero's at higher indexes than v_min_length-1.
function matching_values(
constant value1 : in std_logic_vector;
constant value2 : in std_logic_vector;
constant match_strictness : in t_match_strictness := MATCH_STD
) return boolean is
-- Normalize vectors to (N downto 0)
alias a_value1 : std_logic_vector(value1'length - 1 downto 0) is value1;
alias a_value2 : std_logic_vector(value2'length - 1 downto 0) is value2;
variable v_min_length : natural := minimum(a_value1'length, a_value2'length);
variable v_match : boolean := true; -- as default prior to checking
begin
if matching_widths(a_value1, a_value2) then
case match_strictness is
when MATCH_STD =>
if not std_match(a_value1(v_min_length-1 downto 0), a_value2(v_min_length-1 downto 0)) then
v_match := false;
end if;
when MATCH_STD_INCL_Z =>
for i in v_min_length-1 downto 0 loop
if not(std_match(a_value1(i), a_value2(i)) or
(a_value1(i) = 'Z' and a_value2(i) = 'Z') or
(a_value1(i) = '-' or a_value2(i) = '-')) then
v_match := false;
exit;
end if;
end loop;
when MATCH_STD_INCL_ZXUW =>
for i in v_min_length-1 downto 0 loop
if not(std_match(a_value1(i), a_value2(i)) or
(a_value1(i) = 'Z' and a_value2(i) = 'Z') or
(a_value1(i) = 'X' and a_value2(i) = 'X') or
(a_value1(i) = 'U' and a_value2(i) = 'U') or
(a_value1(i) = 'W' and a_value2(i) = 'W') or
(a_value1(i) = '-' or a_value2(i) = '-')) then
v_match := false;
exit;
end if;
end loop;
when others =>
if a_value1(v_min_length-1 downto 0) /= a_value2(v_min_length-1 downto 0) then
v_match := false;
end if;
end case;
else
v_match := false;
end if;
return v_match;
end;
function matching_values(
value1 : unsigned;
value2 : unsigned
) return boolean is
begin
return matching_values(std_logic_vector(value1), std_logic_vector(value2));
end;
function matching_values(
value1 : signed;
value2 : signed
) return boolean is
begin
return matching_values(std_logic_vector(value1), std_logic_vector(value2));
end;
-- Function check_value,
-- returning 'true' if OK
impure function check_value(
constant value : boolean;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean is
begin
protected_check_counters.increment(CHECK_VALUE);
if value then
log(msg_id, caller_name & " => OK, for boolean true. " & add_msg_delimiter(msg), scope, msg_id_panel);
else
alert(alert_level, caller_name & " => Failed. Boolean was false. " & add_msg_delimiter(msg), scope);
end if;
return value;
end;
impure function check_value(
constant value : boolean;
constant exp : boolean;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean is
constant v_value_str : string := to_string(value);
constant v_exp_str : string := to_string(exp);
begin
protected_check_counters.increment(CHECK_VALUE);
if value = exp then
log(msg_id, caller_name & " => OK, for boolean " & v_value_str & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
return true;
else
alert(alert_level, caller_name & " => Failed. Boolean was " & v_value_str & ". Expected " & v_exp_str & ". " & LF & msg, scope);
return false;
end if;
end;
impure function check_value(
constant value : std_logic;
constant exp : std_logic;
constant match_strictness : t_match_strictness;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean is
constant value_type : string := "std_logic";
constant v_value_str : string := to_string(value);
constant v_exp_str : string := to_string(exp);
variable v_failed : boolean := false;
begin
protected_check_counters.increment(CHECK_VALUE);
case match_strictness is
when MATCH_STD =>
if std_match(value, exp) then
log(msg_id, caller_name & " => OK, for " & value_type & " '" & v_value_str & "' (exp: '" & v_exp_str & "'). " & add_msg_delimiter(msg), scope, msg_id_panel);
else
v_failed := true;
end if;
when MATCH_STD_INCL_Z =>
if (value = 'Z' and exp = 'Z') or std_match(value, exp) then
log(msg_id, caller_name & " => OK, for " & value_type & " '" & v_value_str & "' (exp: '" & v_exp_str & "'). " & add_msg_delimiter(msg), scope, msg_id_panel);
else
v_failed := true;
end if;
when MATCH_STD_INCL_ZXUW =>
if (value = 'Z' and exp = 'Z') or (value = 'X' and exp = 'X') or
(value = 'U' and exp = 'U') or (value = 'W' and exp = 'W') or std_match(value, exp)then
log(msg_id, caller_name & " => OK, for " & value_type & " '" & v_value_str & "' (exp: '" & v_exp_str & "'). " & add_msg_delimiter(msg), scope, msg_id_panel);
else
v_failed := true;
end if;
when others =>
if value = exp then
log(msg_id, caller_name & " => OK, for " & value_type & " '" & v_value_str & "'. " & add_msg_delimiter(msg), scope, msg_id_panel);
else
v_failed := true;
end if;
end case;
if v_failed = true then
alert(alert_level, caller_name & " => Failed. " & value_type & " Was '" & v_value_str & "'. Expected '" & v_exp_str & "'" & LF & msg, scope);
return false;
else
return true;
end if;
end;
impure function check_value(
constant value : std_logic;
constant exp : std_logic;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean is
constant value_type : string := "std_logic";
constant v_value_str : string := to_string(value);
constant v_exp_str : string := to_string(exp);
begin
return check_value(value, exp, MATCH_STD, alert_level, msg, scope, msg_id, msg_id_panel, caller_name);
end;
impure function check_value(
constant value : std_logic_vector;
constant exp : std_logic_vector;
constant match_strictness : t_match_strictness;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "slv"
) return boolean is
-- Normalise vectors to (N downto 0)
alias a_value : std_logic_vector(value'length - 1 downto 0) is value;
alias a_exp : std_logic_vector(exp'length - 1 downto 0) is exp;
constant v_value_str : string := to_string(a_value, radix, format, INCL_RADIX);
constant v_exp_str : string := to_string(a_exp, radix, format, INCL_RADIX);
variable v_check_ok : boolean := true; -- as default prior to checking
variable v_trigger_alert : boolean := false; -- trigger alert and log message
-- Match length of short string with long string
function pad_short_string(short, long : string) return string is
variable v_padding : string(1 to (long'length - short'length)) := (others => '0');
begin
-- Include leading 'x"'
return short(1 to 2) & v_padding & short(3 to short'length);
end function pad_short_string;
begin
protected_check_counters.increment(CHECK_VALUE);
-- AS_IS format has been deprecated and will be removed in the near future
if format = AS_IS then
deprecate(get_procedure_name_from_instance_name(value'instance_name), "format 'AS_IS' has been deprecated. Use KEEP_LEADING_0.");
end if;
v_check_ok := matching_values(a_value, a_exp, match_strictness);
if v_check_ok then
if v_value_str = v_exp_str then
log(msg_id, caller_name & " => OK, for " & value_type & " " & v_value_str & "'. " & add_msg_delimiter(msg), scope, msg_id_panel);
else
-- H,L or - is present in v_exp_str
if match_strictness = MATCH_STD then
log(msg_id, caller_name & " => OK, for " & value_type & " " & v_value_str & "' (exp: " & v_exp_str & "'). " & add_msg_delimiter(msg),
scope, msg_id_panel);
else
v_trigger_alert := true; -- alert and log
end if;
end if;
else
v_trigger_alert := true; -- alert and log
end if;
-- trigger alert and log message
if v_trigger_alert then
if v_value_str'length > v_exp_str'length then
if radix = HEX_BIN_IF_INVALID then
alert(alert_level, caller_name & " => Failed. " & value_type & " Was " & v_value_str & ". Expected " & v_exp_str & "." & LF & msg, scope);
else
alert(alert_level, caller_name & " => Failed. " & value_type & " Was " & v_value_str & ". Expected " & pad_short_string(v_exp_str, v_value_str) & "." & LF & msg, scope);
end if;
elsif v_value_str'length < v_exp_str'length then
if radix = HEX_BIN_IF_INVALID then
alert(alert_level, caller_name & " => Failed. " & value_type & " Was " & v_value_str & ". Expected " & v_exp_str & "." & LF & msg, scope);
else
alert(alert_level, caller_name & " => Failed. " & value_type & " Was " & pad_short_string(v_value_str, v_exp_str) & ". Expected " & v_exp_str & "." & LF & msg, scope);
end if;
else
alert(alert_level, caller_name & " => Failed. " & value_type & " Was " & v_value_str & ". Expected " & v_exp_str & "." & LF & msg, scope);
end if;
end if;
return v_check_ok;
end;
impure function check_value(
constant value : std_logic_vector;
constant exp : std_logic_vector;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "slv"
) return boolean is
-- Normalise vectors to (N downto 0)
alias a_value : std_logic_vector(value'length - 1 downto 0) is value;
alias a_exp : std_logic_vector(exp'length - 1 downto 0) is exp;
constant v_value_str : string := to_string(a_value, radix, format);
constant v_exp_str : string := to_string(a_exp, radix, format);
variable v_check_ok : boolean := true; -- as default prior to checking
begin
return check_value(value, exp, MATCH_STD, alert_level, msg, scope, radix, format, msg_id, msg_id_panel, caller_name, value_type);
end;
impure function check_value(
constant value : unsigned;
constant exp : unsigned;
constant match_strictness : t_match_strictness;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "unsigned"
) return boolean is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(std_logic_vector(value), std_logic_vector(exp), match_strictness, alert_level, msg, scope,
radix, format, msg_id, msg_id_panel, caller_name, value_type);
return v_check_ok;
end;
impure function check_value(
constant value : unsigned;
constant exp : unsigned;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "unsigned"
) return boolean is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(std_logic_vector(value), std_logic_vector(exp), MATCH_STD, alert_level, msg, scope,
radix, format, msg_id, msg_id_panel, caller_name, value_type);
return v_check_ok;
end;
impure function check_value(
constant value : signed;
constant exp : signed;
constant match_strictness : t_match_strictness;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "signed"
) return boolean is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(std_logic_vector(value), std_logic_vector(exp), match_strictness, alert_level, msg, scope,
radix, format, msg_id, msg_id_panel, caller_name, value_type);
return v_check_ok;
end;
impure function check_value(
constant value : signed;
constant exp : signed;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "signed"
) return boolean is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(std_logic_vector(value), std_logic_vector(exp), MATCH_STD, alert_level, msg, scope,
radix, format, msg_id, msg_id_panel, caller_name, value_type);
return v_check_ok;
end;
impure function check_value(
constant value : integer;
constant exp : integer;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean is
constant value_type : string := "int";
constant v_value_str : string := to_string(value);
constant v_exp_str : string := to_string(exp);
begin
protected_check_counters.increment(CHECK_VALUE);
if value = exp then
log(msg_id, caller_name & " => OK, for " & value_type & " " & v_value_str & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
return true;
else
alert(alert_level, caller_name & " => Failed. " & value_type & " Was " & v_value_str & ". Expected " & v_exp_str & LF & msg, scope);
return false;
end if;
end;
impure function check_value(
constant value : real;
constant exp : real;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean is
constant value_type : string := "real";
constant v_value_str : string := to_string(value);
constant v_exp_str : string := to_string(exp);
begin
protected_check_counters.increment(CHECK_VALUE);
if value = exp then
log(msg_id, caller_name & " => OK, for " & value_type & " " & v_value_str & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
return true;
else
alert(alert_level, caller_name & " => Failed. " & value_type & " Was " & v_value_str & ". Expected " & v_exp_str & LF & msg, scope);
return false;
end if;
end;
impure function check_value(
constant value : time;
constant exp : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean is
constant value_type : string := "time";
constant v_value_str : string := to_string(value);
constant v_exp_str : string := to_string(exp);
begin
protected_check_counters.increment(CHECK_VALUE);
if value = exp then
log(msg_id, caller_name & " => OK, for " & value_type & " " & v_value_str & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
return true;
else
alert(alert_level, caller_name & " => Failed. " & value_type & " Was " & v_value_str & ". Expected " & v_exp_str & LF & msg, scope);
return false;
end if;
end;
impure function check_value(
constant value : string;
constant exp : string;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean is
constant value_type : string := "string";
begin
protected_check_counters.increment(CHECK_VALUE);
if value = exp then
log(msg_id, caller_name & " => OK, for " & value_type & " '" & value & "'. " & add_msg_delimiter(msg), scope, msg_id_panel);
return true;
else
alert(alert_level, caller_name & " => Failed. " & value_type & " Was '" & value & "'. Expected '" & exp & "'" & LF & msg, scope);
return false;
end if;
end;
impure function check_value(
constant value : t_slv_array;
constant exp : t_slv_array;
constant match_strictness : t_match_strictness;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "t_slv_array"
) return boolean is
variable v_len_check_ok : boolean := (value'length = exp'length);
variable v_dir_check_ok : boolean := (value'ascending = exp'ascending);
-- adjust for array index differences
variable v_adj_idx : integer := (value'low - exp'low);
begin
protected_check_counters.increment(CHECK_VALUE);
check_value(v_dir_check_ok = true, TB_WARNING, "array directions do not match", scope);
check_value(v_len_check_ok = true, TB_ERROR, "array lengths do not match", scope);
if v_len_check_ok and v_dir_check_ok then
for idx in exp'range loop
-- do not count CHECK_VALUE multiple times
protected_check_counters.decrement(CHECK_VALUE);
if not(check_value(value(idx + v_adj_idx), exp(idx), match_strictness, alert_level, msg, scope, radix, format, msg_id, msg_id_panel, caller_name, value_type)) then
return false;
end if;
end loop;
else -- lenght or direction check not ok
return false;
end if;
return true;
end;
impure function check_value(
constant value : t_slv_array;
constant exp : t_slv_array;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "t_slv_array"
) return boolean is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, MATCH_STD, alert_level, msg, scope, radix, format, msg_id, msg_id_panel, caller_name, value_type);
return v_check_ok;
end;
impure function check_value(
constant value : t_signed_array;
constant exp : t_signed_array;
constant match_strictness : t_match_strictness;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "t_signed_array"
) return boolean is
variable v_len_check_ok : boolean := (value'length = exp'length);
variable v_dir_check_ok : boolean := (value'ascending = exp'ascending);
-- adjust for array index differences
variable v_adj_idx : integer := (value'low - exp'low);
begin
protected_check_counters.increment(CHECK_VALUE);
check_value(v_dir_check_ok = true, TB_WARNING, "array directions do not match", scope);
check_value(v_len_check_ok = true, TB_ERROR, "array lengths do not match", scope);
if v_len_check_ok and v_dir_check_ok then
for idx in exp'range loop
-- do not count CHECK_VALUE multiple times
protected_check_counters.decrement(CHECK_VALUE);
if not(check_value(std_logic_vector(value(idx + v_adj_idx)), std_logic_vector(exp(idx)), alert_level, msg, scope, radix, format, msg_id, msg_id_panel, caller_name, value_type)) then
return false;
end if;
end loop;
else -- length or direction check not ok
return false;
end if;
return true;
end;
impure function check_value(
constant value : t_signed_array;
constant exp : t_signed_array;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "t_signed_array"
) return boolean is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, MATCH_STD, alert_level, msg, scope, radix, format, msg_id, msg_id_panel, caller_name, value_type);
return v_check_ok;
end;
impure function check_value(
constant value : t_unsigned_array;
constant exp : t_unsigned_array;
constant match_strictness : t_match_strictness;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "t_unsigned_array"
) return boolean is
variable v_len_check_ok : boolean := (value'length = exp'length);
variable v_dir_check_ok : boolean := (value'ascending = exp'ascending);
-- adjust for array index differences
variable v_adj_idx : integer := (value'low - exp'low);
begin
protected_check_counters.increment(CHECK_VALUE);
check_value(v_dir_check_ok = true, TB_WARNING, "array directions do not match", scope);
check_value(v_len_check_ok = true, TB_ERROR, "array lengths do not match", scope);
for idx in exp'range loop
-- do not count CHECK_VALUE multiple times
protected_check_counters.decrement(CHECK_VALUE);
if not(check_value(std_logic_vector(value(idx + v_adj_idx)), std_logic_vector(exp(idx)), alert_level, msg, scope, radix, format, msg_id, msg_id_panel, caller_name, value_type)) then
return false;
end if;
end loop;
return true;
end;
impure function check_value(
constant value : t_unsigned_array;
constant exp : t_unsigned_array;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "t_unsigned_array"
) return boolean is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, MATCH_STD, alert_level, msg, scope, radix, format, msg_id, msg_id_panel, caller_name, value_type);
return v_check_ok;
end;
----------------------------------------------------------------------
-- Overloads for impure function check_value methods,
-- to allow optional alert_level
----------------------------------------------------------------------
impure function check_value(
constant value : boolean;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, error, msg, scope, msg_id, msg_id_panel, caller_name);
return v_check_ok;
end;
impure function check_value(
constant value : boolean;
constant exp : boolean;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, error, msg, scope, msg_id, msg_id_panel, caller_name);
return v_check_ok;
end;
impure function check_value(
constant value : std_logic;
constant exp : std_logic;
constant match_strictness : t_match_strictness;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean is
variable v_check_ok : boolean := true; -- as default prior to checking
begin
v_check_ok := check_value(value, exp, match_strictness, error, msg, scope, msg_id, msg_id_panel, caller_name);
return v_check_ok;
end;
impure function check_value(
constant value : std_logic;
constant exp : std_logic;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean is
variable v_check_ok : boolean := true; -- as default prior to checking
begin
v_check_ok := check_value(value, exp, MATCH_STD, error, msg, scope, msg_id, msg_id_panel, caller_name);
return v_check_ok;
end;
impure function check_value(
constant value : std_logic_vector;
constant exp : std_logic_vector;
constant match_strictness : t_match_strictness;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "slv"
) return boolean is
variable v_check_ok : boolean := true; -- as default prior to checking
begin
v_check_ok := check_value(value, exp, match_strictness, error, msg, scope, radix, format, msg_id, msg_id_panel, caller_name, value_type);
return v_check_ok;
end;
impure function check_value(
constant value : std_logic_vector;
constant exp : std_logic_vector;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "slv"
) return boolean is
variable v_check_ok : boolean := true; -- as default prior to checking
begin
v_check_ok := check_value(value, exp, MATCH_STD, error, msg, scope, radix, format, msg_id, msg_id_panel, caller_name, value_type);
return v_check_ok;
end;
impure function check_value(
constant value : unsigned;
constant exp : unsigned;
constant match_strictness : t_match_strictness;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "unsigned"
) return boolean is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(std_logic_vector(value), std_logic_vector(exp), match_strictness, error, msg, scope,
radix, format, msg_id, msg_id_panel, caller_name, value_type);
return v_check_ok;
end;
impure function check_value(
constant value : unsigned;
constant exp : unsigned;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "unsigned"
) return boolean is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(std_logic_vector(value), std_logic_vector(exp), MATCH_STD, error, msg, scope,
radix, format, msg_id, msg_id_panel, caller_name, value_type);
return v_check_ok;
end;
impure function check_value(
constant value : signed;
constant exp : signed;
constant match_strictness : t_match_strictness;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "signed"
) return boolean is
variable v_check_ok : boolean := true; -- as default prior to checking
begin
v_check_ok := check_value(std_logic_vector(value), std_logic_vector(exp), match_strictness, error, msg, scope,
radix, format, msg_id, msg_id_panel, caller_name, value_type);
return v_check_ok;
end;
impure function check_value(
constant value : signed;
constant exp : signed;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "signed"
) return boolean is
variable v_check_ok : boolean := true; -- as default prior to checking
begin
v_check_ok := check_value(std_logic_vector(value), std_logic_vector(exp), MATCH_STD, error, msg, scope,
radix, format, msg_id, msg_id_panel, caller_name, value_type);
return v_check_ok;
end;
impure function check_value(
constant value : integer;
constant exp : integer;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean is
variable v_check_ok : boolean := true; -- as default prior to checking
begin
v_check_ok := check_value(value, exp, error, msg, scope, msg_id, msg_id_panel, caller_name);
return v_check_ok;
end;
impure function check_value(
constant value : real;
constant exp : real;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean is
variable v_check_ok : boolean := true; -- as default prior to checking
begin
v_check_ok := check_value(value, exp, error, msg, scope, msg_id, msg_id_panel, caller_name);
return v_check_ok;
end;
impure function check_value(
constant value : time;
constant exp : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean is
variable v_check_ok : boolean := true; -- as default prior to checking
begin
v_check_ok := check_value(value, exp, error, msg, scope, msg_id, msg_id_panel, caller_name);
return v_check_ok;
end;
impure function check_value(
constant value : string;
constant exp : string;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean is
variable v_check_ok : boolean := true; -- as default prior to checking
begin
v_check_ok := check_value(value, exp, error, msg, scope, msg_id, msg_id_panel, caller_name);
return v_check_ok;
end;
impure function check_value(
constant value : t_slv_array;
constant exp : t_slv_array;
constant match_strictness : t_match_strictness;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "t_slv_array"
) return boolean is
variable v_check_ok : boolean := true; -- as default prior to checking
begin
v_check_ok := check_value(value, exp, match_strictness, error, msg, scope, radix, format, msg_id, msg_id_panel, caller_name, value_type);
return v_check_ok;
end;
impure function check_value(
constant value : t_slv_array;
constant exp : t_slv_array;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "t_slv_array"
) return boolean is
variable v_check_ok : boolean := true; -- as default prior to checking
begin
v_check_ok := check_value(value, exp, MATCH_STD, error, msg, scope, radix, format, msg_id, msg_id_panel, caller_name, value_type);
return v_check_ok;
end;
impure function check_value(
constant value : t_signed_array;
constant exp : t_signed_array;
constant match_strictness : t_match_strictness;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "t_signed_array"
) return boolean is
variable v_check_ok : boolean := true; -- as default prior to checking
begin
v_check_ok := check_value(value, exp, match_strictness, error, msg, scope, radix, format, msg_id, msg_id_panel, caller_name, value_type);
return v_check_ok;
end;
impure function check_value(
constant value : t_signed_array;
constant exp : t_signed_array;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "t_signed_array"
) return boolean is
variable v_check_ok : boolean := true; -- as default prior to checking
begin
v_check_ok := check_value(value, exp, MATCH_STD, error, msg, scope, radix, format, msg_id, msg_id_panel, caller_name, value_type);
return v_check_ok;
end;
impure function check_value(
constant value : t_unsigned_array;
constant exp : t_unsigned_array;
constant match_strictness : t_match_strictness;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "t_unsigned_array"
) return boolean is
variable v_check_ok : boolean := true; -- as default prior to checking
begin
v_check_ok := check_value(value, exp, match_strictness, error, msg, scope, radix, format, msg_id, msg_id_panel, caller_name, value_type);
return v_check_ok;
end;
impure function check_value(
constant value : t_unsigned_array;
constant exp : t_unsigned_array;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "t_unsigned_array"
) return boolean is
variable v_check_ok : boolean := true; -- as default prior to checking
begin
v_check_ok := check_value(value, exp, MATCH_STD, error, msg, scope, radix, format, msg_id, msg_id_panel, caller_name, value_type);
return v_check_ok;
end;
----------------------------------------------------------------------
-- Overloads for procedural check_value methods,
-- to allow for no return value
----------------------------------------------------------------------
procedure check_value(
constant value : boolean;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, alert_level, msg, scope, msg_id, msg_id_panel, caller_name);
end;
procedure check_value(
constant value : boolean;
constant exp : boolean;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, alert_level, msg, scope, msg_id, msg_id_panel, caller_name);
end;
procedure check_value(
constant value : std_logic;
constant exp : std_logic;
constant match_strictness : t_match_strictness;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, match_strictness, alert_level, msg, scope, msg_id, msg_id_panel, caller_name);
end;
procedure check_value(
constant value : std_logic;
constant exp : std_logic;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, MATCH_STD, alert_level, msg, scope, msg_id, msg_id_panel, caller_name);
end;
procedure check_value(
constant value : std_logic_vector;
constant exp : std_logic_vector;
constant match_strictness : t_match_strictness;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "slv"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, match_strictness, alert_level, msg, scope, radix, format, msg_id, msg_id_panel, caller_name, value_type);
end;
procedure check_value(
constant value : std_logic_vector;
constant exp : std_logic_vector;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "slv"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, alert_level, msg, scope, radix, format, msg_id, msg_id_panel, caller_name, value_type);
end;
procedure check_value(
constant value : unsigned;
constant exp : unsigned;
constant match_strictness : t_match_strictness;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "unsigned"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, match_strictness, alert_level, msg, scope, radix, format, msg_id, msg_id_panel, caller_name, value_type);
end;
procedure check_value(
constant value : unsigned;
constant exp : unsigned;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "unsigned"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, MATCH_STD, alert_level, msg, scope, radix, format, msg_id, msg_id_panel, caller_name, value_type);
end;
procedure check_value(
constant value : signed;
constant exp : signed;
constant match_strictness : t_match_strictness;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "signed"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, match_strictness, alert_level, msg, scope, radix, format, msg_id, msg_id_panel, caller_name, value_type);
end;
procedure check_value(
constant value : signed;
constant exp : signed;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "signed"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, MATCH_STD, alert_level, msg, scope, radix, format, msg_id, msg_id_panel, caller_name, value_type);
end;
procedure check_value(
constant value : integer;
constant exp : integer;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, alert_level, msg, scope, msg_id, msg_id_panel, caller_name);
end;
procedure check_value(
constant value : real;
constant exp : real;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, alert_level, msg, scope, msg_id, msg_id_panel, caller_name);
end;
procedure check_value(
constant value : time;
constant exp : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, alert_level, msg, scope, msg_id, msg_id_panel, caller_name);
end;
procedure check_value(
constant value : string;
constant exp : string;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, alert_level, msg, scope, msg_id, msg_id_panel, caller_name);
end;
procedure check_value(
constant value : t_slv_array;
constant exp : t_slv_array;
constant match_strictness : t_match_strictness;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "t_slv_array"
) is
variable v_check_ok : boolean;
variable v_len_check_ok : boolean := (value'length = exp'length);
variable v_dir_check_ok : boolean := (value'ascending = exp'ascending);
-- adjust for array index differences
variable v_adj_idx : integer := (value'low - exp'low);
begin
protected_check_counters.increment(CHECK_VALUE);
check_value(v_dir_check_ok = true, TB_WARNING, "array directions do not match", scope);
check_value(v_len_check_ok = true, TB_ERROR, "array lengths do not match", scope);
-- do not count called CHECK_VALUE
protected_check_counters.decrement(CHECK_VALUE, 2);
if v_len_check_ok and v_dir_check_ok then
for idx in exp'range loop
v_check_ok := check_value(value(idx + v_adj_idx), exp(idx), match_strictness, alert_level, msg, scope, radix, format, msg_id, msg_id_panel, caller_name, value_type);
-- do not count called CHECK_VALUE
protected_check_counters.decrement(CHECK_VALUE);
end loop;
end if;
end;
procedure check_value(
constant value : t_slv_array;
constant exp : t_slv_array;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "t_slv_array"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, MATCH_STD, alert_level, msg, scope, radix, format, msg_id, msg_id_panel, caller_name, value_type);
end;
procedure check_value(
constant value : t_signed_array;
constant exp : t_signed_array;
constant match_strictness : t_match_strictness;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "t_signed_array"
) is
variable v_check_ok : boolean;
variable v_len_check_ok : boolean := (value'length = exp'length);
variable v_dir_check_ok : boolean := (value'ascending = exp'ascending);
-- adjust for array index differences
variable v_adj_idx : integer := (value'low - exp'low);
begin
protected_check_counters.increment(CHECK_VALUE);
check_value(v_dir_check_ok = true, warning, "array directions do not match", scope);
check_value(v_len_check_ok = true, warning, "array lengths do not match", scope);
-- do not count called CHECK_VALUE
protected_check_counters.decrement(CHECK_VALUE, 2);
if v_len_check_ok and v_dir_check_ok then
for idx in exp'range loop
v_check_ok := check_value(std_logic_vector(value(idx + v_adj_idx)), std_logic_vector(exp(idx)), match_strictness, alert_level, msg, scope, radix, format, msg_id, msg_id_panel, caller_name, value_type);
-- do not count called CHECK_VALUE
protected_check_counters.decrement(CHECK_VALUE);
end loop;
end if;
end;
procedure check_value(
constant value : t_signed_array;
constant exp : t_signed_array;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "t_signed_array"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, MATCH_STD, alert_level, msg, scope, radix, format, msg_id, msg_id_panel, caller_name, value_type);
end;
procedure check_value(
constant value : t_unsigned_array;
constant exp : t_unsigned_array;
constant match_strictness : t_match_strictness;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "t_unsigned_array"
) is
variable v_check_ok : boolean;
variable v_len_check_ok : boolean := (value'length = exp'length);
variable v_dir_check_ok : boolean := (value'ascending = exp'ascending);
-- adjust for array index differences
variable v_adj_idx : integer := (value'low - exp'low);
begin
protected_check_counters.increment(CHECK_VALUE);
check_value(v_dir_check_ok = true, warning, "array directions do not match", scope);
check_value(v_len_check_ok = true, warning, "array lengths do not match", scope);
-- do not count called CHECK_VALUE
protected_check_counters.decrement(CHECK_VALUE, 2);
if v_len_check_ok and v_dir_check_ok then
for idx in exp'range loop
v_check_ok := check_value(std_logic_vector(value(idx + v_adj_idx)), std_logic_vector(exp(idx)), match_strictness, alert_level, msg, scope, radix, format, msg_id, msg_id_panel, caller_name, value_type);
-- do not count called CHECK_VALUE
protected_check_counters.decrement(CHECK_VALUE);
end loop;
end if;
end;
procedure check_value(
constant value : t_unsigned_array;
constant exp : t_unsigned_array;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "t_unsigned_array"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, MATCH_STD, alert_level, msg, scope, radix, format, msg_id, msg_id_panel, caller_name, value_type);
end;
----------------------------------------------------------------------
-- Overloads to allow check_value to be called without alert_level
----------------------------------------------------------------------
procedure check_value(
constant value : boolean;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) is
begin
check_value(value, error, msg, scope, msg_id, msg_id_panel, caller_name);
end;
procedure check_value(
constant value : boolean;
constant exp : boolean;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) is
begin
check_value(value, exp, error, msg, scope, msg_id, msg_id_panel, caller_name);
end;
procedure check_value(
constant value : std_logic;
constant exp : std_logic;
constant match_strictness : t_match_strictness;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) is
begin
check_value(value, exp, match_strictness, error, msg, scope, msg_id, msg_id_panel, caller_name);
end;
procedure check_value(
constant value : std_logic;
constant exp : std_logic;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) is
begin
check_value(value, exp, MATCH_STD, error, msg, scope, msg_id, msg_id_panel, caller_name);
end;
procedure check_value(
constant value : std_logic_vector;
constant exp : std_logic_vector;
constant match_strictness : t_match_strictness;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "slv"
) is
begin
check_value(value, exp, match_strictness, error, msg, scope, radix, format, msg_id, msg_id_panel, caller_name, value_type);
end;
procedure check_value(
constant value : std_logic_vector;
constant exp : std_logic_vector;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "slv"
) is
begin
check_value(value, exp, MATCH_STD, error, msg, scope, radix, format, msg_id, msg_id_panel, caller_name, value_type);
end;
procedure check_value(
constant value : unsigned;
constant exp : unsigned;
constant match_strictness : t_match_strictness;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "unsigned"
) is
begin
check_value(value, exp, match_strictness, error, msg, scope, radix, format, msg_id, msg_id_panel, caller_name, value_type);
end;
procedure check_value(
constant value : unsigned;
constant exp : unsigned;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "unsigned"
) is
begin
check_value(value, exp, MATCH_STD, error, msg, scope, radix, format, msg_id, msg_id_panel, caller_name, value_type);
end;
procedure check_value(
constant value : signed;
constant exp : signed;
constant match_strictness : t_match_strictness;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "signed"
) is
begin
check_value(value, exp, match_strictness, error, msg, scope, radix, format, msg_id, msg_id_panel, caller_name, value_type);
end;
procedure check_value(
constant value : signed;
constant exp : signed;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "signed"
) is
begin
check_value(value, exp, MATCH_STD, error, msg, scope, radix, format, msg_id, msg_id_panel, caller_name, value_type);
end;
procedure check_value(
constant value : integer;
constant exp : integer;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) is
begin
check_value(value, exp, error, msg, scope, msg_id, msg_id_panel, caller_name);
end;
procedure check_value(
constant value : real;
constant exp : real;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) is
begin
check_value(value, exp, error, msg, scope, msg_id, msg_id_panel, caller_name);
end;
procedure check_value(
constant value : time;
constant exp : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) is
begin
check_value(value, exp, error, msg, scope, msg_id, msg_id_panel, caller_name);
end;
procedure check_value(
constant value : string;
constant exp : string;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) is
begin
check_value(value, exp, error, msg, scope, msg_id, msg_id_panel, caller_name);
end;
procedure check_value(
constant value : t_slv_array;
constant exp : t_slv_array;
constant match_strictness : t_match_strictness;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "t_slv_array"
) is
begin
check_value(value, exp, match_strictness, error, msg, scope, radix, format, msg_id, msg_id_panel, caller_name, value_type);
end;
procedure check_value(
constant value : t_slv_array;
constant exp : t_slv_array;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "t_slv_array"
) is
begin
check_value(value, exp, MATCH_STD, error, msg, scope, radix, format, msg_id, msg_id_panel, caller_name, value_type);
end;
procedure check_value(
constant value : t_signed_array;
constant exp : t_signed_array;
constant match_strictness : t_match_strictness;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "t_signed_array"
) is
begin
check_value(value, exp, match_strictness, error, msg, scope, radix, format, msg_id, msg_id_panel, caller_name, value_type);
end;
procedure check_value(
constant value : t_signed_array;
constant exp : t_signed_array;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "t_signed_array"
) is
begin
check_value(value, exp, MATCH_STD, error, msg, scope, radix, format, msg_id, msg_id_panel, caller_name, value_type);
end;
procedure check_value(
constant value : t_unsigned_array;
constant exp : t_unsigned_array;
constant match_strictness : t_match_strictness;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "t_unsigned_array"
) is
begin
check_value(value, exp, match_strictness, error, msg, scope, radix, format, msg_id, msg_id_panel, caller_name, value_type);
end;
procedure check_value(
constant value : t_unsigned_array;
constant exp : t_unsigned_array;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := KEEP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "t_unsigned_array"
) is
begin
check_value(value, exp, MATCH_STD, error, msg, scope, radix, format, msg_id, msg_id_panel, caller_name, value_type);
end;
------------------------------------------------------------------------
-- check_value_in_range
------------------------------------------------------------------------
impure function check_value_in_range (
constant value : integer;
constant min_value : integer;
constant max_value : integer;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()";
constant value_type : string := "integer"
) return boolean is
constant v_value_str : string := to_string(value);
constant v_min_value_str : string := to_string(min_value);
constant v_max_value_str : string := to_string(max_value);
variable v_check_ok : boolean;
begin
protected_check_counters.increment(CHECK_VALUE_IN_RANGE);
-- Sanity check
check_value(max_value >= min_value, TB_ERROR, scope,
" => min_value (" & v_min_value_str & ") must be less than max_value("& v_max_value_str & ")" & LF & msg, ID_NEVER, msg_id_panel, caller_name);
-- do not count CHECK_VALUE from CHECK_VALUE_IN_RANGE
protected_check_counters.decrement(CHECK_VALUE);
if (value >= min_value and value <= max_value) then
log(msg_id, caller_name & " => OK, for " & value_type & " " & v_value_str & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
return true;
else
alert(alert_level, caller_name & " => Failed. " & value_type & " Was " & v_value_str & ". Expected between " & v_min_value_str & " and " & v_max_value_str & LF & msg, scope);
return false;
end if;
end;
impure function check_value_in_range (
constant value : unsigned;
constant min_value : unsigned;
constant max_value : unsigned;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()";
constant value_type : string := "unsigned"
) return boolean is
constant v_value_str : string := to_string(value);
constant v_min_value_str : string := to_string(min_value);
constant v_max_value_str : string := to_string(max_value);
begin
protected_check_counters.increment(CHECK_VALUE_IN_RANGE);
-- Sanity check
check_value(max_value >= min_value, TB_ERROR, scope,
" => min_value (" & v_min_value_str & ") must be less than max_value("& v_max_value_str & ")" & LF & msg, ID_NEVER, msg_id_panel, caller_name);
-- do not count CHECK_VALUE from CHECK_VALUE_IN_RANGE
protected_check_counters.decrement(CHECK_VALUE);
if (value >= min_value and value <= max_value) then
log(msg_id, caller_name & " => OK, for " & value_type & " " & v_value_str & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
return true;
else
alert(alert_level, caller_name & " => Failed. " & value_type & " Was " & v_value_str & ". Expected between " & v_min_value_str & " and " & v_max_value_str & LF & msg, scope);
return false;
end if;
end;
impure function check_value_in_range (
constant value : signed;
constant min_value : signed;
constant max_value : signed;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()";
constant value_type : string := "signed"
) return boolean is
constant v_value_str : string := to_string(value);
constant v_min_value_str : string := to_string(min_value);
constant v_max_value_str : string := to_string(max_value);
begin
protected_check_counters.increment(CHECK_VALUE_IN_RANGE);
-- Sanity check
check_value(max_value >= min_value, TB_ERROR, scope,
" => min_value (" & v_min_value_str & ") must be less than max_value("& v_max_value_str & ")" & LF & msg, ID_NEVER, msg_id_panel, caller_name);
-- do not count CHECK_VALUE from CHECK_VALUE_IN_RANGE
protected_check_counters.decrement(CHECK_VALUE);
if (value >= min_value and value <= max_value) then
log(msg_id, caller_name & " => OK, for " & value_type & " " & v_value_str & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
return true;
else
alert(alert_level, caller_name & " => Failed. " & value_type & " Was " & v_value_str & ". Expected between " & v_min_value_str & " and " & v_max_value_str & LF & msg, scope);
return false;
end if;
end;
impure function check_value_in_range (
constant value : time;
constant min_value : time;
constant max_value : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
) return boolean is
constant value_type : string := "time";
constant v_value_str : string := to_string(value);
constant v_min_value_str : string := to_string(min_value);
constant v_max_value_str : string := to_string(max_value);
variable v_check_ok : boolean;
begin
protected_check_counters.increment(CHECK_VALUE_IN_RANGE);
-- Sanity check
check_value(max_value >= min_value, TB_ERROR, scope,
" => min_value (" & v_min_value_str & ") must be less than max_value("& v_max_value_str & ")" & LF & msg, ID_NEVER, msg_id_panel, caller_name);
-- do not count CHECK_VALUE from CHECK_VALUE_IN_RANGE
protected_check_counters.decrement(CHECK_VALUE);
if (value >= min_value and value <= max_value) then
log(msg_id, caller_name & " => OK, for " & value_type & " " & v_value_str & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
return true;
else
alert(alert_level, caller_name & " => Failed. " & value_type & " Was " & v_value_str & ". Expected between " & v_min_value_str & " and " & v_max_value_str & LF & msg, scope);
return false;
end if;
end;
impure function check_value_in_range (
constant value : real;
constant min_value : real;
constant max_value : real;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
) return boolean is
constant value_type : string := "real";
constant v_value_str : string := to_string(value);
constant v_min_value_str : string := to_string(min_value);
constant v_max_value_str : string := to_string(max_value);
variable v_check_ok : boolean;
begin
protected_check_counters.increment(CHECK_VALUE_IN_RANGE);
-- Sanity check
check_value(max_value >= min_value, TB_ERROR,
" => min_value (" & v_min_value_str & ") must be less than max_value("& v_max_value_str & ")" & LF & msg, scope,
ID_NEVER, msg_id_panel, caller_name);
-- do not count CHECK_VALUE from CHECK_VALUE_IN_RANGE
protected_check_counters.decrement(CHECK_VALUE);
if (value >= min_value and value <= max_value) then
log(msg_id, caller_name & " => OK, for " & value_type & " " & v_value_str & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
return true;
else
alert(alert_level, caller_name & " => Failed. " & value_type & " Was " & v_value_str & ". Expected between " & v_min_value_str & " and " & v_max_value_str & LF & msg, scope);
return false;
end if;
end;
-- check_value_in_range without mandatory alert_level
impure function check_value_in_range (
constant value : integer;
constant min_value : integer;
constant max_value : integer;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()";
constant value_type : string := "integer"
) return boolean is
variable v_check_ok : boolean;
begin
v_check_ok := check_value_in_range(value, min_value, max_value, error, msg, scope, msg_id, msg_id_panel, caller_name, value_type);
return v_check_ok;
end;
impure function check_value_in_range (
constant value : unsigned;
constant min_value : unsigned;
constant max_value : unsigned;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()";
constant value_type : string := "unsigned"
) return boolean is
variable v_check_ok : boolean;
begin
v_check_ok := check_value_in_range(value, min_value, max_value, error, msg, scope, msg_id, msg_id_panel, caller_name, value_type);
return v_check_ok;
end;
impure function check_value_in_range (
constant value : signed;
constant min_value : signed;
constant max_value : signed;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()";
constant value_type : string := "signed"
) return boolean is
variable v_check_ok : boolean;
begin
v_check_ok := check_value_in_range(value, min_value, max_value, error, msg, scope, msg_id, msg_id_panel, caller_name, value_type);
return v_check_ok;
end;
impure function check_value_in_range (
constant value : time;
constant min_value : time;
constant max_value : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
) return boolean is
variable v_check_ok : boolean;
begin
v_check_ok := check_value_in_range(value, min_value, max_value, error, msg, scope, msg_id, msg_id_panel, caller_name);
return v_check_ok;
end;
impure function check_value_in_range (
constant value : real;
constant min_value : real;
constant max_value : real;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
) return boolean is
variable v_check_ok : boolean;
begin
v_check_ok := check_value_in_range(value, min_value, max_value, error, msg, scope, msg_id, msg_id_panel, caller_name);
return v_check_ok;
end;
--------------------------------------------------------------------------------
-- check_value_in_range procedures :
-- Call the corresponding function and discard the return value
--------------------------------------------------------------------------------
procedure check_value_in_range (
constant value : integer;
constant min_value : integer;
constant max_value : integer;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value_in_range(value, min_value, max_value, alert_level, msg, scope, msg_id, msg_id_panel, caller_name);
end;
procedure check_value_in_range (
constant value : unsigned;
constant min_value : unsigned;
constant max_value : unsigned;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value_in_range(value, min_value, max_value, alert_level, msg, scope, msg_id, msg_id_panel, caller_name);
end;
procedure check_value_in_range (
constant value : signed;
constant min_value : signed;
constant max_value : signed;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value_in_range(value, min_value, max_value, alert_level, msg, scope, msg_id, msg_id_panel, caller_name);
end;
procedure check_value_in_range (
constant value : time;
constant min_value : time;
constant max_value : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value_in_range(value, min_value, max_value, alert_level, msg, scope, msg_id, msg_id_panel, caller_name);
end;
procedure check_value_in_range (
constant value : real;
constant min_value : real;
constant max_value : real;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value_in_range(value, min_value, max_value, alert_level, msg, scope, msg_id, msg_id_panel, caller_name);
end;
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-- check_value_in_range procedures without mandatory alert_level
procedure check_value_in_range (
constant value : integer;
constant min_value : integer;
constant max_value : integer;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
) is
begin
check_value_in_range(value, min_value, max_value, error, msg, scope, msg_id, msg_id_panel, caller_name);
end;
procedure check_value_in_range (
constant value : unsigned;
constant min_value : unsigned;
constant max_value : unsigned;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
) is
begin
check_value_in_range(value, min_value, max_value, error, msg, scope, msg_id, msg_id_panel, caller_name);
end;
procedure check_value_in_range (
constant value : signed;
constant min_value : signed;
constant max_value : signed;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
) is
begin
check_value_in_range(value, min_value, max_value, error, msg, scope, msg_id, msg_id_panel, caller_name);
end;
procedure check_value_in_range (
constant value : time;
constant min_value : time;
constant max_value : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
) is
begin
check_value_in_range(value, min_value, max_value, error, msg, scope, msg_id, msg_id_panel, caller_name);
end;
procedure check_value_in_range (
constant value : real;
constant min_value : real;
constant max_value : real;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
) is
begin
check_value_in_range(value, min_value, max_value, error, msg, scope, msg_id, msg_id_panel, caller_name);
end;
--------------------------------------------------------------------------------
-- check_stable
--------------------------------------------------------------------------------
procedure check_stable(
signal target : boolean;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "boolean"
) is
constant value_string : string := to_string(target);
constant last_value_string : string := to_string(target'last_value);
constant last_change : time := target'last_event;
constant last_change_string : string := to_string(last_change, ns);
begin
protected_check_counters.increment(CHECK_STABLE);
if (last_change >= stable_req) then
log(msg_id, caller_name & " => OK. Stable at " & value_string & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
else
alert(alert_level, caller_name & " => Failed. Switched from " & last_value_string & " to " &
value_string & " " & last_change_string & " ago. Expected stable for " & to_string(stable_req) & LF & msg, scope);
end if;
end;
procedure check_stable(
signal target : in std_logic_vector;
constant stable_req : in time;
constant alert_level : in t_alert_level;
variable success : out boolean;
constant msg : in string;
constant scope : in string := C_TB_SCOPE_DEFAULT;
constant msg_id : in t_msg_id := ID_POS_ACK;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant caller_name : in string := "check_stable()";
constant value_type : in string := "slv"
) is
constant value_string : string := 'x' & to_string(target, HEX);
constant last_value_string : string := 'x' & to_string(target'last_value, HEX);
constant last_change : time := target'last_event;
constant last_change_string : string := to_string(last_change, ns);
begin
protected_check_counters.increment(CHECK_STABLE);
success := true;
if (last_change >= stable_req) then
log(msg_id, caller_name & " => OK. Stable at " & value_string & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
else
alert(alert_level, caller_name & " => Failed. Switched from " & last_value_string & " to " &
value_string & " " & last_change_string & " ago. Expected stable for " & to_string(stable_req) & LF & msg, scope);
success := false;
end if;
end;
procedure check_stable(
signal target : std_logic_vector;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "slv"
) is
variable v_success : boolean;
begin
check_stable(target, stable_req, alert_level, v_success, msg, scope, msg_id, msg_id_panel, caller_name, value_type);
end;
procedure check_stable(
signal target : unsigned;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "unsigned"
) is
constant value_string : string := 'x' & to_string(target, HEX);
constant last_value_string : string := 'x' & to_string(target'last_value, HEX);
constant last_change : time := target'last_event;
constant last_change_string : string := to_string(last_change, ns);
begin
protected_check_counters.increment(CHECK_STABLE);
if (last_change >= stable_req) then
log(msg_id, caller_name & " => OK. Stable at " & value_string & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
else
alert(alert_level, caller_name & " => Failed. Switched from " & last_value_string & " to " &
value_string & " " & last_change_string & " ago. Expected stable for " & to_string(stable_req) & LF & msg, scope);
end if;
end;
procedure check_stable(
signal target : signed;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "signed"
) is
constant value_string : string := 'x' & to_string(target, HEX);
constant last_value_string : string := 'x' & to_string(target'last_value, HEX);
constant last_change : time := target'last_event;
constant last_change_string : string := to_string(last_change, ns);
begin
protected_check_counters.increment(CHECK_STABLE);
if (last_change >= stable_req) then
log(msg_id, caller_name & " => OK. Stable at " & value_string & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
else
alert(alert_level, caller_name & " => Failed. Switched from " & last_value_string & " to " &
value_string & " " & last_change_string & " ago. Expected stable for " & to_string(stable_req) & LF & msg, scope);
end if;
end;
procedure check_stable(
signal target : std_logic;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "std_logic"
) is
constant value_string : string := to_string(target);
constant last_value_string : string := to_string(target'last_value);
constant last_change : time := target'last_event;
constant last_change_string : string := to_string(last_change, ns);
begin
protected_check_counters.increment(CHECK_STABLE);
if (last_change >= stable_req) then
log(msg_id, caller_name & " => OK. Stable at " & value_string & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
else
alert(alert_level, caller_name & " => Failed. Switched from " & last_value_string & " to " &
value_string & " " & last_change_string & " ago. Expected stable for " & to_string(stable_req) & LF & msg, scope);
end if;
end;
procedure check_stable(
signal target : integer;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "integer"
) is
constant value_string : string := to_string(target);
constant last_value_string : string := to_string(target'last_value);
constant last_change : time := target'last_event;
constant last_change_string : string := to_string(last_change, ns);
begin
protected_check_counters.increment(CHECK_STABLE);
if (last_change >= stable_req) then
log(msg_id, caller_name & " => OK." & value_string & " stable at " & value_string & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
else
alert(alert_level, caller_name & " => Failed. Switched from " & last_value_string & " to " &
value_string & " " & last_change_string & " ago. Expected stable for " & to_string(stable_req) & LF & msg, scope);
end if;
end;
procedure check_stable(
signal target : real;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "real"
) is
constant value_string : string := to_string(target);
constant last_value_string : string := to_string(target'last_value);
constant last_change : time := target'last_event;
constant last_change_string : string := to_string(last_change, ns);
begin
protected_check_counters.increment(CHECK_STABLE);
if (last_change >= stable_req) then
log(msg_id, caller_name & " => OK." & value_string & " stable at " & value_string & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
else
alert(alert_level, caller_name & " => Failed. Switched from " & last_value_string & " to " &
value_string & " " & last_change_string & " ago. Expected stable for " & to_string(stable_req) & LF & msg, scope);
end if;
end;
-- check stable overloads without mandatory alert level
procedure check_stable(
signal target : boolean;
constant stable_req : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "boolean"
) is
begin
check_stable(target, stable_req, error, msg, scope, msg_id, msg_id_panel, caller_name, value_type);
end;
procedure check_stable(
signal target : std_logic_vector;
constant stable_req : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "slv"
) is
begin
check_stable(target, stable_req, error, msg, scope, msg_id, msg_id_panel, caller_name, value_type);
end;
procedure check_stable(
signal target : unsigned;
constant stable_req : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "unsigned"
) is
begin
check_stable(target, stable_req, error, msg, scope, msg_id, msg_id_panel, caller_name, value_type);
end;
procedure check_stable(
signal target : signed;
constant stable_req : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "signed"
) is
begin
check_stable(target, stable_req, error, msg, scope, msg_id, msg_id_panel, caller_name, value_type);
end;
procedure check_stable(
signal target : std_logic;
constant stable_req : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "std_logic"
) is
begin
check_stable(target, stable_req, error, msg, scope, msg_id, msg_id_panel, caller_name, value_type);
end;
procedure check_stable(
signal target : integer;
constant stable_req : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "integer"
) is
begin
check_stable(target, stable_req, error, msg, scope, msg_id, msg_id_panel, caller_name, value_type);
end;
procedure check_stable(
signal target : real;
constant stable_req : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "real"
) is
begin
check_stable(target, stable_req, error, msg, scope, msg_id, msg_id_panel, caller_name, value_type);
end;
----------------------------------------------------------------------------
-- check_time_window is used to check if a given condition occurred between
-- min_time and max_time
-- Usage: wait for requested condition until max_time is reached, then call check_time_window().
-- The input 'success' is needed to distinguish between the following cases:
-- - the signal reached success condition at max_time,
-- - max_time was reached with no success condition
----------------------------------------------------------------------------
procedure check_time_window(
constant success : in boolean; -- F.ex target'event, or target=exp
constant elapsed_time : in time;
constant min_time : in time;
constant max_time : in time;
constant alert_level : in t_alert_level;
constant name : in string;
variable check_is_ok : out boolean;
constant msg : in string;
constant scope : in string := C_TB_SCOPE_DEFAULT;
constant msg_id : in t_msg_id := ID_POS_ACK;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel
) is
begin
protected_check_counters.increment(CHECK_TIME_WINDOW);
check_is_ok := true;
-- Sanity check
check_value(max_time >= min_time, TB_ERROR, name & " => min_time must be less than max_time." & LF & msg, scope, ID_NEVER, msg_id_panel, name);
-- do not count CHECK_VALUE from CHECK_TIME_WINDOW
protected_check_counters.decrement(CHECK_VALUE);
if elapsed_time < min_time then
alert(alert_level, name & " => Failed. Condition occurred too early, after " &
to_string(elapsed_time, C_LOG_TIME_BASE) & ". " & add_msg_delimiter(msg), scope);
check_is_ok := false;
elsif success then
log(msg_id, name & " => OK. Condition occurred after " &
to_string(elapsed_time, C_LOG_TIME_BASE) & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
else -- max_time reached with no success
alert(alert_level, name & " => Failed. Timed out after " &
to_string(max_time, C_LOG_TIME_BASE) & ". " & add_msg_delimiter(msg), scope);
check_is_ok := false;
end if;
end;
procedure check_time_window(
constant success : boolean; -- F.ex target'event, or target=exp
constant elapsed_time : time;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant name : string;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
variable v_check_is_ok : boolean;
begin
check_time_window(success, elapsed_time, min_time, max_time, alert_level, name, v_check_is_ok, msg, scope, msg_id, msg_id_panel);
end;
----------------------------------------------------------------------------
-- Random functions
----------------------------------------------------------------------------
-- Return a random std_logic_vector, using overload for the integer version of random()
impure function random (
constant length : integer
) return std_logic_vector is
variable random_vec : std_logic_vector(length-1 downto 0);
begin
-- Iterate through each bit and randomly set to 0 or 1
for i in 0 to length-1 loop
random_vec(i downto i) := std_logic_vector(to_unsigned(random(0, 1), 1));
end loop;
return random_vec;
end;
-- Return a random std_logic, using overload for the SLV version of random()
impure function random (
constant VOID : t_void
) return std_logic is
variable v_random_bit : std_logic_vector(0 downto 0);
begin
-- randomly set bit to 0 or 1
v_random_bit := random(1);
return v_random_bit(0);
end;
-- Return a random integer between min_value and max_value
-- Use global seeds
impure function random (
constant min_value : integer;
constant max_value : integer
) return integer is
variable v_rand_scaled : integer;
variable v_seed1 : positive := shared_seed1;
variable v_seed2 : positive := shared_seed2;
begin
random(min_value, max_value, v_seed1, v_seed2, v_rand_scaled);
-- Write back seeds
shared_seed1 := v_seed1;
shared_seed2 := v_seed2;
return v_rand_scaled;
end;
-- Return a random real between min_value and max_value
-- Use global seeds
impure function random (
constant min_value : real;
constant max_value : real
) return real is
variable v_rand_scaled : real;
variable v_seed1 : positive := shared_seed1;
variable v_seed2 : positive := shared_seed2;
begin
random(min_value, max_value, v_seed1, v_seed2, v_rand_scaled);
-- Write back seeds
shared_seed1 := v_seed1;
shared_seed2 := v_seed2;
return v_rand_scaled;
end;
-- Return a random time between min time and max time
-- Use global seeds
impure function random (
constant min_value : time;
constant max_value : time
) return time is
variable v_rand_scaled : time;
variable v_seed1 : positive := shared_seed1;
variable v_seed2 : positive := shared_seed2;
begin
random(min_value, max_value, v_seed1, v_seed2, v_rand_scaled);
-- Write back seeds
shared_seed1 := v_seed1;
shared_seed2 := v_seed2;
return v_rand_scaled;
end;
--
-- Procedure versions of random(), where seeds can be specified
--
-- Set target to a random SLV, using overload for the integer version of random().
procedure random (
variable v_seed1 : inout positive;
variable v_seed2 : inout positive;
variable v_target : inout std_logic_vector
) is
variable v_length : integer := v_target'length;
variable v_rand : integer;
begin
-- Iterate through each bit and randomly set to 0 or 1
for i in 0 to v_length-1 loop
random(0, 1, v_seed1, v_seed2, v_rand);
v_target(i downto i) := std_logic_vector(to_unsigned(v_rand, 1));
end loop;
end;
-- Set target to a random SL, using overload for the SLV version of random().
procedure random (
variable v_seed1 : inout positive;
variable v_seed2 : inout positive;
variable v_target : inout std_logic
) is
variable v_random_slv : std_logic_vector(0 downto 0);
begin
random(v_seed1, v_seed2, v_random_slv);
v_target := v_random_slv(0);
end;
-- Set target to a random integer between min_value and max_value
procedure random (
constant min_value : integer;
constant max_value : integer;
variable v_seed1 : inout positive;
variable v_seed2 : inout positive;
variable v_target : inout integer
) is
variable v_rand : real;
begin
-- Random real-number value in range 0 to 1.0
uniform(v_seed1, v_seed2, v_rand);
-- Scale to a random integer between min_value and max_value
v_target := integer(real(min_value) + trunc(v_rand*(1.0+real(max_value)-real(min_value))));
end;
-- Set target to a random integer between min_value and max_value
procedure random (
constant min_value : real;
constant max_value : real;
variable v_seed1 : inout positive;
variable v_seed2 : inout positive;
variable v_target : inout real
) is
variable v_rand : real;
begin
-- Random real-number value in range 0 to 1.0
uniform(v_seed1, v_seed2, v_rand);
-- Scale to a random integer between min_value and max_value
v_target := min_value + v_rand*(max_value-min_value);
end;
-- Set target to a random integer between min_value and max_value
procedure random (
constant min_value : time;
constant max_value : time;
variable v_seed1 : inout positive;
variable v_seed2 : inout positive;
variable v_target : inout time
) is
constant time_unit : time := std.env.resolution_limit;
variable v_rand : real;
variable v_rand_int : integer;
begin
-- Random real-number value in range 0 to 1.0
uniform(v_seed1, v_seed2, v_rand);
-- Scale to a random integer between min_value and max_value
v_rand_int := integer(real(min_value/time_unit) + trunc(v_rand*(1.0+real(max_value/time_unit)-real(min_value/time_unit))));
v_target := v_rand_int * time_unit;
end;
-- Set global seeds
procedure randomize (
constant seed1 : positive;
constant seed2 : positive;
constant msg : string := "randomizing seeds";
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
log(ID_UTIL_SETUP, "Setting global seeds to " & to_string(seed1) & ", " & to_string(seed2), scope);
shared_seed1 := seed1;
shared_seed2 := seed2;
end;
-- Set global seeds
procedure randomise (
constant seed1 : positive;
constant seed2 : positive;
constant msg : string := "randomising seeds";
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
deprecate(get_procedure_name_from_instance_name(seed1'instance_name), "Use randomize().");
log(ID_UTIL_SETUP, "Setting global seeds to " & to_string(seed1) & ", " & to_string(seed2), scope);
shared_seed1 := seed1;
shared_seed2 := seed2;
end;
-- Converts a t_byte_array (ascending) to a std_logic_vector
function convert_byte_array_to_slv(
constant byte_array : t_byte_array;
constant byte_endianness : t_byte_endianness
) return std_logic_vector is
constant c_num_bytes : integer := byte_array'length;
alias normalized_byte_array : t_byte_array(0 to c_num_bytes-1) is byte_array;
variable v_slv : std_logic_vector(8*c_num_bytes-1 downto 0);
begin
assert byte_array'ascending report "byte_array must be ascending" severity error;
for byte_idx in 0 to c_num_bytes-1 loop
if (byte_endianness = LOWER_BYTE_LEFT) or (byte_endianness = FIRST_BYTE_LEFT) then
v_slv(8*(c_num_bytes-byte_idx)-1 downto 8*(c_num_bytes-1-byte_idx)) := normalized_byte_array(byte_idx);
else -- LOWER_BYTE_RIGHT or FIRST_BYTE_RIGHT
v_slv(8*(byte_idx+1)-1 downto 8*byte_idx) := normalized_byte_array(byte_idx);
end if;
end loop;
return v_slv;
end function;
-- Converts a std_logic_vector to a t_byte_array (ascending)
function convert_slv_to_byte_array(
constant slv : std_logic_vector;
constant byte_endianness : t_byte_endianness
) return t_byte_array is
variable v_num_bytes : integer := slv'length/8+1; -- +1 in case there's a division remainder
alias normalized_slv : std_logic_vector(slv'length-1 downto 0) is slv;
variable v_byte_array : t_byte_array(0 to v_num_bytes-1);
variable v_slv_idx : integer := normalized_slv'high;
variable v_slv_idx_min : integer;
begin
-- Adjust value if there was no remainder
if (slv'length rem 8) = 0 then
v_num_bytes := v_num_bytes-1;
end if;
for byte_idx in 0 to v_num_bytes-1 loop
for bit_idx in 7 downto 0 loop
if v_slv_idx = -1 then
v_byte_array(byte_idx)(bit_idx) := 'Z'; -- Pads 'Z'
else
if (byte_endianness = LOWER_BYTE_LEFT) or (byte_endianness = FIRST_BYTE_LEFT) then
v_byte_array(byte_idx)(bit_idx) := normalized_slv(v_slv_idx);
else -- LOWER_BYTE_RIGHT or FIRST_BYTE_RIGHT
v_slv_idx_min := MINIMUM(8*byte_idx+bit_idx, normalized_slv'high); -- avoid indexing outside the slv
v_byte_array(byte_idx)(bit_idx) := normalized_slv(v_slv_idx_min);
end if;
v_slv_idx := v_slv_idx-1;
end if;
end loop;
end loop;
return v_byte_array(0 to v_num_bytes-1);
end function;
-- Converts a t_byte_array (any direction) to a t_slv_array (same direction)
function convert_byte_array_to_slv_array(
constant byte_array : t_byte_array;
constant bytes_in_word : natural;
constant byte_endianness : t_byte_endianness := LOWER_BYTE_LEFT
) return t_slv_array is
constant c_num_words : integer := byte_array'length/bytes_in_word;
variable v_ascending_array : t_slv_array(0 to c_num_words-1)((8*bytes_in_word)-1 downto 0);
variable v_descending_array : t_slv_array(c_num_words-1 downto 0)((8*bytes_in_word)-1 downto 0);
variable v_byte_idx : integer := 0;
begin
for slv_idx in 0 to c_num_words-1 loop
if (byte_endianness = LOWER_BYTE_LEFT) or (byte_endianness = FIRST_BYTE_LEFT) then
for byte_in_word in bytes_in_word downto 1 loop
v_ascending_array(slv_idx)((8*byte_in_word)-1 downto (byte_in_word-1)*8) := byte_array(v_byte_idx);
v_descending_array(slv_idx)((8*byte_in_word)-1 downto (byte_in_word-1)*8) := byte_array(v_byte_idx);
v_byte_idx := v_byte_idx + 1;
end loop;
else -- LOWER_BYTE_RIGHT or FIRST_BYTE_RIGHT
for byte_in_word in 1 to bytes_in_word loop
v_ascending_array(slv_idx)((8*byte_in_word)-1 downto (byte_in_word-1)*8) := byte_array(v_byte_idx);
v_descending_array(slv_idx)((8*byte_in_word)-1 downto (byte_in_word-1)*8) := byte_array(v_byte_idx);
v_byte_idx := v_byte_idx + 1;
end loop;
end if;
end loop;
if byte_array'ascending then
return v_ascending_array;
else -- byte array is descending
return v_descending_array;
end if;
end function;
-- Converts a t_slv_array (any direction) to a t_byte_array (same direction)
function convert_slv_array_to_byte_array(
constant slv_array : t_slv_array;
constant byte_endianness : t_byte_endianness := LOWER_BYTE_LEFT
) return t_byte_array is
constant c_num_bytes_in_word : integer := (slv_array(slv_array'low)'length/8);
constant c_byte_array_length : integer := (slv_array'length * c_num_bytes_in_word);
constant c_vector_is_ascending : boolean := slv_array(slv_array'low)'ascending;
variable v_ascending_array : t_byte_array(0 to c_byte_array_length-1);
variable v_descending_array : t_byte_array(c_byte_array_length-1 downto 0);
variable v_byte_idx : integer := 0;
variable v_offset : natural := 0;
begin
-- Use this offset in case the slv_array doesn't start at 0
v_offset := slv_array'low;
for slv_idx in 0 to slv_array'length-1 loop
if (byte_endianness = LOWER_BYTE_LEFT) or (byte_endianness = FIRST_BYTE_LEFT) then
for byte in c_num_bytes_in_word downto 1 loop
if c_vector_is_ascending then
v_ascending_array(v_byte_idx) := slv_array(slv_idx+v_offset)((byte-1)*8 to (8*byte)-1);
v_descending_array(v_byte_idx) := slv_array(slv_idx+v_offset)((byte-1)*8 to (8*byte)-1);
else -- SLV vector is descending
v_ascending_array(v_byte_idx) := slv_array(slv_idx+v_offset)((8*byte)-1 downto (byte-1)*8);
v_descending_array(v_byte_idx) := slv_array(slv_idx+v_offset)((8*byte)-1 downto (byte-1)*8);
end if;
v_byte_idx := v_byte_idx + 1;
end loop;
else -- LOWER_BYTE_RIGHT or FIRST_BYTE_RIGHT
for byte in 1 to c_num_bytes_in_word loop
if c_vector_is_ascending then
v_ascending_array(v_byte_idx) := slv_array(slv_idx+v_offset)((byte-1)*8 to (8*byte)-1);
v_descending_array(v_byte_idx) := slv_array(slv_idx+v_offset)((byte-1)*8 to (8*byte)-1);
else -- SLV vector is descending
v_ascending_array(v_byte_idx) := slv_array(slv_idx+v_offset)((8*byte)-1 downto (byte-1)*8);
v_descending_array(v_byte_idx) := slv_array(slv_idx+v_offset)((8*byte)-1 downto (byte-1)*8);
end if;
v_byte_idx := v_byte_idx + 1;
end loop;
end if;
end loop;
if slv_array'ascending then
return v_ascending_array;
else -- SLV array is descending
return v_descending_array;
end if;
end function;
function convert_slv_array_to_byte_array(
constant slv_array : t_slv_array;
constant ascending : boolean := false;
constant byte_endianness : t_byte_endianness := FIRST_BYTE_LEFT
) return t_byte_array is
variable v_bytes_in_word : integer := (slv_array(0)'length/8);
variable v_byte_array_length : integer := (slv_array'length * v_bytes_in_word);
variable v_ascending_array : t_byte_array(0 to v_byte_array_length-1);
variable v_descending_array : t_byte_array(v_byte_array_length-1 downto 0);
variable v_ascending_vector : boolean := false;
variable v_byte_number : integer := 0;
begin
-- The ascending parameter should match the array direction. We could also just remove the ascending
-- parameter and use the t'ascending attribute.
bitvis_assert((slv_array'ascending and ascending) or (not(slv_array'ascending) and not(ascending)), ERROR,
"convert_slv_array_to_byte_array()", "slv_array direction doesn't match ascending parameter");
v_ascending_vector := slv_array(0)'ascending;
if (byte_endianness = LOWER_BYTE_LEFT) or (byte_endianness = FIRST_BYTE_LEFT) then
for slv_idx in 0 to slv_array'length-1 loop
for byte in v_bytes_in_word downto 1 loop
if v_ascending_vector then
v_ascending_array(v_byte_number) := slv_array(slv_idx)((byte-1)*8 to (8*byte)-1);
v_descending_array(v_byte_number) := slv_array(slv_idx)((byte-1)*8 to (8*byte)-1);
else -- SLV vector is descending
v_ascending_array(v_byte_number) := slv_array(slv_idx)((8*byte)-1 downto (byte-1)*8);
v_descending_array(v_byte_number) := slv_array(slv_idx)((8*byte)-1 downto (byte-1)*8);
end if;
v_byte_number := v_byte_number + 1;
end loop;
end loop;
else -- LOWER_BYTE_RIGHT or FIRST_BYTE_RIGHT
for slv_idx in 0 to slv_array'length-1 loop
for byte in 1 to v_bytes_in_word loop
if v_ascending_vector then
v_ascending_array(v_byte_number) := slv_array(slv_idx)((byte-1)*8 to (8*byte)-1);
v_descending_array(v_byte_number) := slv_array(slv_idx)((byte-1)*8 to (8*byte)-1);
else -- SLV vector is descending
v_ascending_array(v_byte_number) := slv_array(slv_idx)((8*byte)-1 downto (byte-1)*8);
v_descending_array(v_byte_number) := slv_array(slv_idx)((8*byte)-1 downto (byte-1)*8);
end if;
v_byte_number := v_byte_number + 1;
end loop;
end loop;
end if;
if ascending then
return v_ascending_array;
else -- descending
return v_descending_array;
end if;
end function;
function reverse_vector(
constant value : std_logic_vector
) return std_logic_vector is
variable return_val : std_logic_vector(value'range);
begin
for i in 0 to value'length-1 loop
return_val(value'low + i) := value(value'high - i);
end loop;
return return_val;
end function reverse_vector;
impure function reverse_vectors_in_array(
constant value : t_slv_array
) return t_slv_array is
variable return_val : t_slv_array(value'range)(value(value'low)'range);
begin
for i in value'range loop
return_val(i) := reverse_vector(value(i));
end loop;
return return_val;
end function reverse_vectors_in_array;
function log2(
constant num : positive)
return natural is
variable return_val : natural := 0;
begin
while (2**return_val < num) and (return_val < 31) loop
return_val := return_val + 1;
end loop;
return return_val;
end function;
-- ============================================================================
-- Time consuming checks
-- ============================================================================
--------------------------------------------------------------------------------
-- await_change
-- A signal change is required, but may happen already after 1 delta if min_time = 0 ns
--------------------------------------------------------------------------------
procedure await_change(
signal target : boolean;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "boolean"
) is
constant name : string := "await_change(" & value_type & ", " &
to_string(min_time, ns) & ", " &
to_string(max_time, ns) & ")";
constant start_time : time := now;
begin
wait on target for max_time;
check_time_window(target'event, now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
end;
procedure await_change(
signal target : std_logic;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "std_logic"
) is
constant name : string := "await_change(" & value_type & ", " &
to_string(min_time, ns) & ", " &
to_string(max_time, ns) & ")";
constant start_time : time := now;
begin
wait on target for max_time;
check_time_window(target'event, now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
end;
procedure await_change(
signal target : std_logic_vector;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "slv"
) is
constant name : string := "await_change(" & value_type & ", " &
to_string(min_time, ns) & ", " &
to_string(max_time, ns) & ")";
constant start_time : time := now;
begin
wait on target for max_time;
check_time_window(target'event, now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
end;
procedure await_change(
signal target : unsigned;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "unsigned"
) is
constant name : string := "await_change(" & value_type & ", " &
to_string(min_time, ns) & ", " &
to_string(max_time, ns) & ")";
constant start_time : time := now;
begin
-- Note that overloading by casting target to slv without creating a new signal doesn't work
wait on target for max_time;
check_time_window(target'event, now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
end;
procedure await_change(
signal target : signed;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "signed"
) is
constant name : string := "await_change(" & value_type & ", " &
to_string(min_time, ns) & ", " &
to_string(max_time, ns) & ")";
constant start_time : time := now;
begin
wait on target for max_time;
check_time_window(target'event, now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
end;
procedure await_change(
signal target : integer;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "integer"
) is
constant name : string := "await_change(" & value_type & ", " &
to_string(min_time, ns) & ", " & to_string(max_time, ns) & ")";
constant start_time : time := now;
begin
wait on target for max_time;
check_time_window(target'event, now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
end;
procedure await_change(
signal target : real;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "real"
) is
constant name : string := "await_change(" & value_type & ", " &
to_string(min_time, ns) & ", " & to_string(max_time, ns) & ")";
constant start_time : time := now;
begin
wait on target for max_time;
check_time_window(target'event, now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
end;
-- Await Change overloads without mandatory alert level
procedure await_change(
signal target : boolean;
constant min_time : time;
constant max_time : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "boolean"
) is
begin
await_change(target, min_time, max_time, error, msg, scope, msg_id, msg_id_panel, value_type);
end;
procedure await_change(
signal target : std_logic;
constant min_time : time;
constant max_time : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "std_logic"
) is
begin
await_change(target, min_time, max_time, error, msg, scope, msg_id, msg_id_panel, value_type);
end;
procedure await_change(
signal target : std_logic_vector;
constant min_time : time;
constant max_time : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "slv"
) is
begin
await_change(target, min_time, max_time, error, msg, scope, msg_id, msg_id_panel, value_type);
end;
procedure await_change(
signal target : unsigned;
constant min_time : time;
constant max_time : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "unsigned"
) is
begin
await_change(target, min_time, max_time, error, msg, scope, msg_id, msg_id_panel, value_type);
end;
procedure await_change(
signal target : signed;
constant min_time : time;
constant max_time : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "signed"
) is
begin
await_change(target, min_time, max_time, error, msg, scope, msg_id, msg_id_panel, value_type);
end;
procedure await_change(
signal target : integer;
constant min_time : time;
constant max_time : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "integer"
) is
begin
await_change(target, min_time, max_time, error, msg, scope, msg_id, msg_id_panel, value_type);
end;
procedure await_change(
signal target : real;
constant min_time : time;
constant max_time : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "real"
) is
begin
await_change(target, min_time, max_time, error, msg, scope, msg_id, msg_id_panel, value_type);
end;
--------------------------------------------------------------------------------
-- await_value
--------------------------------------------------------------------------------
-- Potential improvements
-- - Adding an option that the signal must last for more than one delta cycle
-- or a specified time
-- - Adding an "AS_IS" option that does not allow the signal to change to other values
-- before it changes to the expected value
--
-- The input signal is allowed to change to other values before ending up on the expected value,
-- as long as it changes to the expected value within the time window (min_time to max_time).
-- Wait for target = expected or timeout after max_time.
-- Then check if (and when) the value changed to the expected
procedure await_value (
signal target : boolean;
constant exp : boolean;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "boolean";
constant start_time : time := now;
constant v_exp_str : string := to_string(exp);
constant name : string := "await_value(" & value_type & " " & v_exp_str & ", " &
to_string(min_time, ns) & ", " & to_string(max_time, ns) & ")";
begin
if (target /= exp) then
wait until (target = exp) for max_time;
end if;
check_time_window((target = exp), now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
end;
procedure await_value (
signal target : std_logic;
constant exp : std_logic;
constant match_strictness : t_match_strictness;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "std_logic";
constant start_time : time := now;
constant v_exp_str : string := to_string(exp);
constant name : string := "await_value(" & value_type & " " & v_exp_str & ", " &
to_string(min_time, ns) & ", " & to_string(max_time, ns) & ")";
variable success : boolean := false;
begin
success := false;
if match_strictness = MATCH_EXACT then
if (target /= exp) then
wait until (target = exp) for max_time;
end if;
if (target = exp) then
success := true;
end if;
elsif match_strictness = MATCH_STD_INCL_Z then
if not(std_match(target, exp) or (target = 'Z' and exp = 'Z')) then
wait until (std_match(target, exp) or (target = 'Z' and exp = 'Z')) for max_time;
end if;
if std_match(target, exp) or (target = 'Z' and exp = 'Z') then
success := true;
end if;
elsif match_strictness = MATCH_STD_INCL_ZXUW then
if not(std_match(target, exp) or (target = 'Z' and exp = 'Z') or
(target = 'X' and exp = 'X') or (target = 'U' and exp = 'U') or
(target = 'W' and exp = 'W')) then
wait until (std_match(target, exp) or (target = 'Z' and exp = 'Z') or
(target = 'X' and exp = 'X') or (target = 'U' and exp = 'U') or
(target = 'W' and exp = 'W')) for max_time;
end if;
if std_match(target, exp) or (target = 'Z' and exp = 'Z') or (target = 'X' and exp = 'X') or
(target = 'U' and exp = 'U') or (target = 'W' and exp = 'W') then
success := true;
end if;
else
if ((exp = '1' or exp = 'H') and (target /= '1') and (target /= 'H')) then
wait until (target = '1' or target = 'H') for max_time;
elsif ((exp = '0' or exp = 'L') and (target /= '0') and (target /= 'L')) then
wait until (target = '0' or target = 'L') for max_time;
end if;
if ((exp = '1' or exp = 'H') and (target = '1' or target = 'H')) then
success := true;
elsif ((exp = '0' or exp = 'L') and (target = '0' or target = 'L')) then
success := true;
end if;
end if;
check_time_window(success, now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
end;
procedure await_value (
signal target : std_logic;
constant exp : std_logic;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "std_logic";
constant start_time : time := now;
constant v_exp_str : string := to_string(exp);
constant name : string := "await_value(" & value_type & " " & v_exp_str & ", " &
to_string(min_time, ns) & ", " & to_string(max_time, ns) & ")";
begin
await_value(target, exp, MATCH_EXACT, min_time, max_time, alert_level, msg, scope, msg_id, msg_id_panel);
end;
procedure await_value (
signal target : in std_logic_vector;
constant exp : in std_logic_vector;
constant match_strictness : in t_match_strictness;
constant min_time : in time;
constant max_time : in time;
constant alert_level : in t_alert_level;
variable success : out boolean;
constant msg : in string;
constant scope : in string := C_TB_SCOPE_DEFAULT;
constant radix : in t_radix := HEX_BIN_IF_INVALID;
constant format : in t_format_zeros := SKIP_LEADING_0;
constant msg_id : in t_msg_id := ID_POS_ACK;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant caller_name : in string := ""
) is
constant value_type : string := "slv";
constant start_time : time := now;
constant v_exp_str : string := to_string(exp, radix, format, INCL_RADIX);
constant name : string := "await_value(" & value_type & " " & v_exp_str & ", " &
to_string(min_time, ns) & ", " & to_string(max_time, ns) & ")";
variable v_proc_call : line;
begin
if caller_name = "" then
write(v_proc_call, name);
else
write(v_proc_call, caller_name);
end if;
-- AS_IS format has been deprecated and will be removed in the near future
if format = AS_IS then
deprecate(get_procedure_name_from_instance_name(target'instance_name), "format 'AS_IS' has been deprecated. Use KEEP_LEADING_0.");
end if;
if matching_widths(target, exp) then
if match_strictness = MATCH_STD then
if not matching_values(target, exp) then
wait until matching_values(target, exp) for max_time;
end if;
check_time_window(matching_values(target, exp), now-start_time, min_time, max_time, alert_level, v_proc_call.all, success, msg, scope, msg_id, msg_id_panel);
elsif match_strictness = MATCH_STD_INCL_Z then
if not matching_values(target, exp, MATCH_STD_INCL_Z) then
wait until matching_values(target, exp, MATCH_STD_INCL_Z) for max_time;
end if;
check_time_window(matching_values(target, exp, MATCH_STD_INCL_Z), now-start_time, min_time, max_time, alert_level, v_proc_call.all, success, msg, scope, msg_id, msg_id_panel);
elsif match_strictness = MATCH_STD_INCL_ZXUW then
if not matching_values(target, exp, MATCH_STD_INCL_ZXUW) then
wait until matching_values(target, exp, MATCH_STD_INCL_ZXUW) for max_time;
end if;
check_time_window(matching_values(target, exp, MATCH_STD_INCL_ZXUW), now-start_time, min_time, max_time, alert_level, v_proc_call.all, success, msg, scope, msg_id, msg_id_panel);
else
if (target /= exp) then
wait until (target = exp) for max_time;
end if;
check_time_window((target = exp), now-start_time, min_time, max_time, alert_level, v_proc_call.all, success, msg, scope, msg_id, msg_id_panel);
end if;
else
alert(alert_level, v_proc_call.all & " => Failed. Widths did not match. " & add_msg_delimiter(msg), scope);
success := false;
end if;
DEALLOCATE(v_proc_call);
end;
procedure await_value (
signal target : std_logic_vector;
constant exp : std_logic_vector;
constant match_strictness : t_match_strictness;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
variable v_success : boolean;
begin
await_value(target, exp, match_strictness, min_time, max_time, alert_level, v_success, msg, scope, radix, format, msg_id, msg_id_panel);
end;
procedure await_value (
signal target : std_logic_vector;
constant exp : std_logic_vector;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "slv";
constant start_time : time := now;
constant v_exp_str : string := to_string(exp, radix, format, INCL_RADIX);
constant name : string := "await_value(" & value_type & " " & v_exp_str & ", " &
to_string(min_time, ns) & ", " & to_string(max_time, ns) & ")";
begin
await_value(target, exp, MATCH_STD, min_time, max_time, alert_level, msg, scope, radix, format, msg_id, msg_id_panel);
end;
procedure await_value (
signal target : unsigned;
constant exp : unsigned;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "unsigned";
constant start_time : time := now;
constant v_exp_str : string := to_string(exp, radix, format, INCL_RADIX);
constant name : string := "await_value(" & value_type & " " & v_exp_str & ", " &
to_string(min_time, ns) & ", " & to_string(max_time, ns) & ")";
begin
-- AS_IS format has been deprecated and will be removed in the near future
if format = AS_IS then
deprecate(get_procedure_name_from_instance_name(target'instance_name), "format 'AS_IS' has been deprecated. Use KEEP_LEADING_0.");
end if;
if matching_widths(target, exp) then
if not matching_values(target, exp) then
wait until matching_values(target, exp) for max_time;
end if;
check_time_window(matching_values(target, exp), now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
else
alert(alert_level, name & " => Failed. Widths did not match. " & add_msg_delimiter(msg), scope);
end if;
end;
procedure await_value (
signal target : signed;
constant exp : signed;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "signed";
constant start_time : time := now;
constant v_exp_str : string := to_string(exp, radix, format, INCL_RADIX);
constant name : string := "await_value(" & value_type & " " & v_exp_str & ", " &
to_string(min_time, ns) & ", " & to_string(max_time, ns) & ")";
begin
-- AS_IS format has been deprecated and will be removed in the near future
if format = AS_IS then
deprecate(get_procedure_name_from_instance_name(target'instance_name), "format 'AS_IS' has been deprecated. Use KEEP_LEADING_0.");
end if;
if matching_widths(target, exp) then
if not matching_values(target, exp) then
wait until matching_values(target, exp) for max_time;
end if;
check_time_window(matching_values(target, exp), now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
else
alert(alert_level, name & " => Failed. Widths did not match. " & add_msg_delimiter(msg), scope);
end if;
end;
procedure await_value (
signal target : integer;
constant exp : integer;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "integer";
constant start_time : time := now;
constant v_exp_str : string := to_string(exp);
constant name : string := "await_value(" & value_type & " " & v_exp_str & ", " &
to_string(min_time, ns) & ", " & to_string(max_time, ns) & ")";
begin
if (target /= exp) then
wait until (target = exp) for max_time;
end if;
check_time_window((target = exp), now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
end;
procedure await_value (
signal target : real;
constant exp : real;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "real";
constant start_time : time := now;
constant v_exp_str : string := to_string(exp);
constant name : string := "await_value(" & value_type & " " & v_exp_str & ", " &
to_string(min_time, ns) & ", " & to_string(max_time, ns) & ")";
begin
if (target /= exp) then
wait until (target = exp) for max_time;
end if;
check_time_window((target = exp), now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
end;
-- Await Value Overloads without alert_level
procedure await_value (
signal target : boolean;
constant exp : boolean;
constant min_time : time;
constant max_time : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
await_value(target, exp, min_time, max_time, error, msg, scope, msg_id, msg_id_panel);
end;
procedure await_value (
signal target : std_logic;
constant exp : std_logic;
constant match_strictness : t_match_strictness;
constant min_time : time;
constant max_time : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
await_value(target, exp, match_strictness, min_time, max_time, error, msg, scope, msg_id, msg_id_panel);
end;
procedure await_value (
signal target : std_logic;
constant exp : std_logic;
constant min_time : time;
constant max_time : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
await_value(target, exp, min_time, max_time, error, msg, scope, msg_id, msg_id_panel);
end;
procedure await_value (
signal target : std_logic_vector;
constant exp : std_logic_vector;
constant match_strictness : t_match_strictness;
constant min_time : time;
constant max_time : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
await_value(target, exp, match_strictness, min_time, max_time, error, msg, scope, radix, format, msg_id, msg_id_panel);
end;
procedure await_value (
signal target : std_logic_vector;
constant exp : std_logic_vector;
constant min_time : time;
constant max_time : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
await_value(target, exp, min_time, max_time, error, msg, scope, radix, format, msg_id, msg_id_panel);
end;
procedure await_value (
signal target : unsigned;
constant exp : unsigned;
constant min_time : time;
constant max_time : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
await_value(target, exp, min_time, max_time, error, msg, scope, radix, format, msg_id, msg_id_panel);
end;
procedure await_value (
signal target : signed;
constant exp : signed;
constant min_time : time;
constant max_time : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
await_value(target, exp, min_time, max_time, error, msg, scope, radix, format, msg_id, msg_id_panel);
end;
procedure await_value (
signal target : integer;
constant exp : integer;
constant min_time : time;
constant max_time : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
await_value(target, exp, min_time, max_time, error, msg, scope, msg_id, msg_id_panel);
end;
procedure await_value (
signal target : real;
constant exp : real;
constant min_time : time;
constant max_time : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
await_value(target, exp, min_time, max_time, error, msg, scope, msg_id, msg_id_panel);
end;
-- Helper procedure:
-- Convert time from 'FROM_LAST_EVENT' to 'FROM_NOW'
procedure await_stable_calc_time (
constant target_last_event : in time;
constant stable_req : in time; -- Minimum stable requirement
constant stable_req_from : in t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : in time; -- Timeout if stable_req not achieved
constant timeout_from : in t_from_point_in_time; -- Which point in time the timeout starts
variable stable_req_from_now : inout time; -- Calculated stable requirement from now
variable timeout_from_await_stable_entry : inout time; -- Calculated timeout from procedure entry
constant alert_level : in t_alert_level;
constant msg : in string;
constant scope : in string := C_TB_SCOPE_DEFAULT;
constant msg_id : in t_msg_id := ID_POS_ACK;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant caller_name : in string := "await_stable_calc_time()";
variable stable_req_met : inout boolean; -- When true, the stable requirement is satisfied
variable stable_req_success : out boolean
) is
begin
stable_req_met := false;
stable_req_success := true;
-- Convert stable_req so that it points to "time_from_now"
if stable_req_from = FROM_NOW then
stable_req_from_now := stable_req;
elsif stable_req_from = FROM_LAST_EVENT then
-- Signal has already been stable for target'last_event,
-- so we can subtract this in the FROM_NOW version.
stable_req_from_now := stable_req - target_last_event;
else
alert(tb_error, caller_name & " => Unknown stable_req_from. " & add_msg_delimiter(msg), scope);
stable_req_success := false;
end if;
-- Convert timeout so that it points to "time_from_now"
if timeout_from = FROM_NOW then
timeout_from_await_stable_entry := timeout;
elsif timeout_from = FROM_LAST_EVENT then
timeout_from_await_stable_entry := timeout - target_last_event;
else
alert(tb_error, caller_name & " => Unknown timeout_from. " & add_msg_delimiter(msg), scope);
stable_req_success := false;
end if;
-- Check if requirement is already OK
if (stable_req_from_now <= 0 ns) then
log(msg_id, caller_name & " => OK. Condition occurred immediately. " & add_msg_delimiter(msg), scope, msg_id_panel);
stable_req_met := true;
end if;
-- Check if it is impossible to achieve stable_req before timeout
if (stable_req_from_now > timeout_from_await_stable_entry) then
alert(alert_level, caller_name & " => Failed immediately: Stable for stable_req = " & to_string(stable_req_from_now, ns) &
" is not possible before timeout = " & to_string(timeout_from_await_stable_entry, ns) &
". " & add_msg_delimiter(msg), scope);
stable_req_met := true;
stable_req_success := false;
end if;
end;
procedure await_stable_calc_time (
constant target_last_event : time;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
variable stable_req_from_now : inout time; -- Calculated stable requirement from now
variable timeout_from_await_stable_entry : inout time; -- Calculated timeout from procedure entry
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "await_stable_calc_time()";
variable stable_req_met : inout boolean -- When true, the stable requirement is satisfied
) is
variable v_stable_req_success : boolean;
begin
await_stable_calc_time(target_last_event, stable_req, stable_req_from, timeout, timeout_from, stable_req_from_now,
timeout_from_await_stable_entry, alert_level, msg, scope, msg_id, msg_id_panel, caller_name, stable_req_met, v_stable_req_success);
end;
-- Helper procedure:
procedure await_stable_checks (
constant start_time : in time; -- Time at await_stable() procedure entry
constant stable_req : in time; -- Minimum stable requirement
variable stable_req_from_now : inout time; -- Minimum stable requirement from now
variable timeout_from_await_stable_entry : inout time; -- Timeout value converted to FROM_NOW
constant time_since_last_event : in time; -- Time since previous event
constant alert_level : in t_alert_level;
constant msg : in string;
constant scope : in string := C_TB_SCOPE_DEFAULT;
constant msg_id : in t_msg_id := ID_POS_ACK;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant caller_name : in string := "await_stable_checks()";
variable stable_req_met : inout boolean; -- When true, the stable requirement is satisfied
variable stable_req_success : out boolean
) is
variable v_time_left : time; -- Remaining time until timeout
variable v_elapsed_time : time := 0 ns; -- Time since procedure entry
begin
stable_req_met := false;
v_elapsed_time := now - start_time;
v_time_left := timeout_from_await_stable_entry - v_elapsed_time;
-- Check if target has been stable for stable_req
if (time_since_last_event >= stable_req_from_now) then
log(msg_id, caller_name & " => OK. Condition occurred after " &
to_string(v_elapsed_time, C_LOG_TIME_BASE) & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
stable_req_met := true;
stable_req_success := true;
end if;
--
-- Prepare for the next iteration in the loop in await_stable() procedure:
--
if not stable_req_met then
-- Now that an event has occurred, the stable requirement is stable_req from now (regardless of stable_req_from)
stable_req_from_now := stable_req;
-- Check if it is impossible to achieve stable_req before timeout
if (stable_req_from_now > v_time_left) then
alert(alert_level, caller_name & " => Failed. After " & to_string(v_elapsed_time, C_LOG_TIME_BASE) &
", stable for stable_req = " & to_string(stable_req_from_now, ns) &
" is not possible before timeout = " & to_string(timeout_from_await_stable_entry, ns) &
"(time since last event = " & to_string(time_since_last_event, ns) &
". " & add_msg_delimiter(msg), scope);
stable_req_met := true;
stable_req_success := false;
end if;
end if;
end;
procedure await_stable_checks (
constant start_time : time; -- Time at await_stable() procedure entry
constant stable_req : time; -- Minimum stable requirement
variable stable_req_from_now : inout time; -- Minimum stable requirement from now
variable timeout_from_await_stable_entry : inout time; -- Timeout value converted to FROM_NOW
constant time_since_last_event : time; -- Time since previous event
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "await_stable_checks()";
variable stable_req_met : inout boolean -- When true, the stable requirement is satisfied
) is
variable v_stable_req_success : boolean;
begin
await_stable_checks(start_time, stable_req, stable_req_from_now, timeout_from_await_stable_entry, time_since_last_event,
alert_level, msg, scope, msg_id, msg_id_panel, caller_name, stable_req_met, v_stable_req_success);
end;
-- Await Stable Procedures
-- Wait until the target signal has been stable for at least 'stable_req'
-- Report an error if this does not occurr within the time specified by 'timeout'.
-- Note : 'Stable' refers to that the signal has not had an event (i.e. not changed value).
-- Description of arguments:
-- stable_req_from = FROM_NOW : Target must be stable 'stable_req' from now
-- stable_req_from = FROM_LAST_EVENT : Target must be stable 'stable_req' from the last event of target.
-- timeout_from = FROM_NOW : The timeout argument is given in time from now
-- timeout_from = FROM_LAST_EVENT : The timeout argument is given in time the last event of target.
procedure await_stable (
signal target : boolean;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "boolean";
constant start_time : time := now;
constant name : string := "await_stable(" & value_type & ", " & to_string(stable_req, ns) &
", " & to_string(timeout, ns) & ")";
variable v_stable_req_from_now : time; -- Stable_req relative to now.
variable v_timeout_from_proc_entry : time; -- Timeout relative to time of procedure entry
variable v_stable_req_met : boolean := false; -- When true, the procedure is done and has logged a conclusion.
begin
-- Use a helper procedure to simplify overloading
await_stable_calc_time(
target_last_event => target'last_event,
stable_req => stable_req,
stable_req_from => stable_req_from,
timeout => timeout,
timeout_from => timeout_from,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
caller_name => name,
stable_req_met => v_stable_req_met);
-- Start waiting for target'event or stable_req time, unless :
-- - stable_req already achieved, or
-- - it is already too late to be stable for stable_req before timeout will occurr
while not v_stable_req_met loop
wait until target'event for v_stable_req_from_now;
-- Use a helper procedure to simplify overloading
await_stable_checks (
start_time => start_time,
stable_req => stable_req,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
time_since_last_event => target'last_event,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
caller_name => name,
stable_req_met => v_stable_req_met);
end loop;
end;
-- Note that the waiting for target'event can't be called from overloaded procedures where 'target' is a different type.
-- Instead, the common code is put in helper procedures
procedure await_stable (
signal target : std_logic;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "std_logic";
constant start_time : time := now;
constant name : string := "await_stable(" & value_type & ", " & to_string(stable_req, ns) &
", " & to_string(timeout, ns) & ")";
variable v_stable_req_from_now : time; -- Stable_req relative to now.
variable v_timeout_from_proc_entry : time; -- Timeout relative to time of procedure entry
variable v_stable_req_met : boolean := false; -- When true, the procedure is done and has logged a conclusion.
begin
-- Use a helper procedure to simplify overloading
await_stable_calc_time(
target_last_event => target'last_event,
stable_req => stable_req,
stable_req_from => stable_req_from,
timeout => timeout,
timeout_from => timeout_from,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
caller_name => name,
stable_req_met => v_stable_req_met);
-- Start waiting for target'event or stable_req time, unless :
-- - stable_req already achieved, or
-- - it is already too late to be stable for stable_req before timeout will occurr
while not v_stable_req_met loop
wait until target'event for v_stable_req_from_now;
-- Use a helper procedure to simplify overloading
await_stable_checks (
start_time => start_time,
stable_req => stable_req,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
time_since_last_event => target'last_event,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
caller_name => name,
stable_req_met => v_stable_req_met);
end loop;
end;
procedure await_stable (
signal target : in std_logic_vector;
constant stable_req : in time; -- Minimum stable requirement
constant stable_req_from : in t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : in time; -- Timeout if stable_req not achieved
constant timeout_from : in t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : in t_alert_level;
variable success : out boolean;
constant msg : in string;
constant scope : in string := C_TB_SCOPE_DEFAULT;
constant msg_id : in t_msg_id := ID_POS_ACK;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant caller_name : in string := ""
) is
constant value_type : string := "std_logic_vector";
constant start_time : time := now;
constant name : string := "await_stable(" & value_type & ", " & to_string(stable_req, ns) &
", " & to_string(timeout, ns) & ")";
variable v_stable_req_from_now : time; -- Stable_req relative to now.
variable v_timeout_from_proc_entry : time; -- Timeout relative to time of procedure entry
variable v_stable_req_met : boolean := false; -- When true, the procedure is done and has logged a conclusion.
variable v_proc_call : line;
begin
if caller_name = "" then
write(v_proc_call, name);
else
write(v_proc_call, caller_name);
end if;
-- Use a helper procedure to simplify overloading
await_stable_calc_time(
target_last_event => target'last_event,
stable_req => stable_req,
stable_req_from => stable_req_from,
timeout => timeout,
timeout_from => timeout_from,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
caller_name => v_proc_call.all,
stable_req_met => v_stable_req_met,
stable_req_success => success);
-- Start waiting for target'event or stable_req time, unless :
-- - stable_req already achieved, or
-- - it is already too late to be stable for stable_req before timeout will occurr
while not v_stable_req_met loop
wait until target'event for v_stable_req_from_now;
-- Use a helper procedure to simplify overloading
await_stable_checks (
start_time => start_time,
stable_req => stable_req,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
time_since_last_event => target'last_event,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
caller_name => v_proc_call.all,
stable_req_met => v_stable_req_met,
stable_req_success => success);
end loop;
DEALLOCATE(v_proc_call);
end;
procedure await_stable (
signal target : std_logic_vector;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
variable v_success : boolean;
begin
await_stable(target, stable_req, stable_req_from, timeout, timeout_from, alert_level, v_success, msg, scope, msg_id, msg_id_panel);
end;
procedure await_stable (
signal target : unsigned;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "unsigned";
constant start_time : time := now;
constant name : string := "await_stable(" & value_type & ", " & to_string(stable_req, ns) &
", " & to_string(timeout, ns) & ")";
variable v_stable_req_from_now : time; -- Stable_req relative to now.
variable v_timeout_from_proc_entry : time; -- Timeout relative to time of procedure entry
variable v_stable_req_met : boolean := false; -- When true, the procedure is done and has logged a conclusion.
begin
-- Use a helper procedure to simplify overloading
await_stable_calc_time(
target_last_event => target'last_event,
stable_req => stable_req,
stable_req_from => stable_req_from,
timeout => timeout,
timeout_from => timeout_from,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
caller_name => name,
stable_req_met => v_stable_req_met);
-- Start waiting for target'event or stable_req time, unless :
-- - stable_req already achieved, or
-- - it is already too late to be stable for stable_req before timeout will occurr
while not v_stable_req_met loop
wait until target'event for v_stable_req_from_now;
-- Use a helper procedure to simplify overloading
await_stable_checks (
start_time => start_time,
stable_req => stable_req,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
time_since_last_event => target'last_event,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
caller_name => name,
stable_req_met => v_stable_req_met);
end loop;
end;
procedure await_stable (
signal target : signed;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "signed";
constant start_time : time := now;
constant name : string := "await_stable(" & value_type & ", " & to_string(stable_req, ns) &
", " & to_string(timeout, ns) & ")";
variable v_stable_req_from_now : time; -- Stable_req relative to now.
variable v_timeout_from_proc_entry : time; -- Timeout relative to time of procedure entry
variable v_stable_req_met : boolean := false; -- When true, the procedure is done and has logged a conclusion.
begin
-- Use a helper procedure to simplify overloading
await_stable_calc_time(
target_last_event => target'last_event,
stable_req => stable_req,
stable_req_from => stable_req_from,
timeout => timeout,
timeout_from => timeout_from,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
caller_name => name,
stable_req_met => v_stable_req_met);
-- Start waiting for target'event or stable_req time, unless :
-- - stable_req already achieved, or
-- - it is already too late to be stable for stable_req before timeout will occurr
while not v_stable_req_met loop
wait until target'event for v_stable_req_from_now;
-- Use a helper procedure to simplify overloading
await_stable_checks (
start_time => start_time,
stable_req => stable_req,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
time_since_last_event => target'last_event,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
caller_name => name,
stable_req_met => v_stable_req_met);
end loop;
end;
procedure await_stable (
signal target : integer;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "integer";
constant start_time : time := now;
constant name : string := "await_stable(" & value_type & ", " & to_string(stable_req, ns) &
", " & to_string(timeout, ns) & ")";
variable v_stable_req_from_now : time; -- Stable_req relative to now.
variable v_timeout_from_proc_entry : time; -- Timeout relative to time of procedure entry
variable v_stable_req_met : boolean := false; -- When true, the procedure is done and has logged a conclusion.
begin
-- Use a helper procedure to simplify overloading
await_stable_calc_time(
target_last_event => target'last_event,
stable_req => stable_req,
stable_req_from => stable_req_from,
timeout => timeout,
timeout_from => timeout_from,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
caller_name => name,
stable_req_met => v_stable_req_met);
-- Start waiting for target'event or stable_req time, unless :
-- - stable_req already achieved, or
-- - it is already too late to be stable for stable_req before timeout will occur
while not v_stable_req_met loop
wait until target'event for v_stable_req_from_now;
-- Use a helper procedure to simplify overloading
await_stable_checks (
start_time => start_time,
stable_req => stable_req,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
time_since_last_event => target'last_event,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
caller_name => name,
stable_req_met => v_stable_req_met);
end loop;
end;
procedure await_stable (
signal target : real;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "real";
constant start_time : time := now;
constant name : string := "await_stable(" & value_type & ", " & to_string(stable_req, ns) &
", " & to_string(timeout, ns) & ")";
variable v_stable_req_from_now : time; -- Stable_req relative to now.
variable v_timeout_from_proc_entry : time; -- Timeout relative to time of procedure entry
variable v_stable_req_met : boolean := false; -- When true, the procedure is done and has logged a conclusion.
begin
-- Use a helper procedure to simplify overloading
await_stable_calc_time(
target_last_event => target'last_event,
stable_req => stable_req,
stable_req_from => stable_req_from,
timeout => timeout,
timeout_from => timeout_from,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
caller_name => name,
stable_req_met => v_stable_req_met);
-- Start waiting for target'event or stable_req time, unless :
-- - stable_req already achieved, or
-- - it is already too late to be stable for stable_req before timeout will occur
while not v_stable_req_met loop
wait until target'event for v_stable_req_from_now;
-- Use a helper procedure to simplify overloading
await_stable_checks (
start_time => start_time,
stable_req => stable_req,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
time_since_last_event => target'last_event,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
caller_name => name,
stable_req_met => v_stable_req_met);
end loop;
end;
-- Procedure overloads for await_stable() without mandatory Alert_Level
procedure await_stable (
signal target : boolean;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
await_stable(target, stable_req, stable_req_from, timeout, timeout_from, error, msg, scope, msg_id, msg_id_panel);
end;
procedure await_stable (
signal target : std_logic;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
await_stable(target, stable_req, stable_req_from, timeout, timeout_from, error, msg, scope, msg_id, msg_id_panel);
end;
procedure await_stable (
signal target : std_logic_vector;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
await_stable(target, stable_req, stable_req_from, timeout, timeout_from, error, msg, scope, msg_id, msg_id_panel);
end;
procedure await_stable (
signal target : unsigned;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
await_stable(target, stable_req, stable_req_from, timeout, timeout_from, error, msg, scope, msg_id, msg_id_panel);
end;
procedure await_stable (
signal target : signed;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
await_stable(target, stable_req, stable_req_from, timeout, timeout_from, error, msg, scope, msg_id, msg_id_panel);
end;
procedure await_stable (
signal target : integer;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
await_stable(target, stable_req, stable_req_from, timeout, timeout_from, error, msg, scope, msg_id, msg_id_panel);
end;
procedure await_stable (
signal target : real;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
await_stable(target, stable_req, stable_req_from, timeout, timeout_from, error, msg, scope, msg_id, msg_id_panel);
end;
-----------------------------------------------------------------------------------
-- gen_pulse(sl)
-- Generate a pulse on a std_logic for a certain amount of time
--
-- If blocking_mode = BLOCKING : Procedure waits until the pulse is done before returning to the caller.
-- If blocking_mode = NON_BLOCKING : Procedure starts the pulse, schedules the end of the pulse, then returns to the caller immediately.
--
procedure gen_pulse(
signal target : inout std_logic;
constant pulse_value : std_logic;
constant pulse_duration : time;
constant blocking_mode : t_blocking_mode;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant init_value : std_logic := target;
begin
check_value(target /= pulse_value, TB_ERROR, "gen_pulse: target was already " & to_string(pulse_value) & ". " & add_msg_delimiter(msg), scope, ID_NEVER);
target <= pulse_value; -- Generate pulse
if (blocking_mode = BLOCKING) then
wait for pulse_duration;
target <= init_value;
else
check_value(pulse_duration /= 0 ns, TB_ERROR, "gen_pulse: The combination of NON_BLOCKING mode and 0 ns pulse duration results in the pulse being ignored.", scope, ID_NEVER);
target <= transport init_value after pulse_duration;
end if;
log(msg_id, "Pulsed to " & to_string(pulse_value) & " for " & to_string(pulse_duration) & ". " & add_msg_delimiter(msg), scope);
wait for 0 ns; -- wait a delta cycle for signal to update
end;
-- Overload to allow excluding the pulse_value argument:
-- Make pulse_value = '1' by default
procedure gen_pulse(
signal target : inout std_logic;
constant pulse_duration : time;
constant blocking_mode : t_blocking_mode;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
gen_pulse(target, '1', pulse_duration, blocking_mode, msg, scope, msg_id, msg_id_panel); -- Blocking mode by default
end;
-- Overload to allow excluding the blocking_mode and pulse_value arguments:
-- Make blocking_mode = BLOCKING and pulse_value = '1' by default
procedure gen_pulse(
signal target : inout std_logic;
constant pulse_duration : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
gen_pulse(target, '1', pulse_duration, BLOCKING, msg, scope, msg_id, msg_id_panel); -- Blocking mode by default
end;
-- Overload to allow excluding the blocking_mode argument:
-- Make blocking_mode = BLOCKING by default
procedure gen_pulse(
signal target : inout std_logic;
constant pulse_value : std_logic;
constant pulse_duration : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
gen_pulse(target, pulse_value, pulse_duration, BLOCKING, msg, scope, msg_id, msg_id_panel); -- Blocking mode by default
end;
-- gen_pulse(sl)
-- Generate a pulse on a std_logic for a certain number of clock cycles
procedure gen_pulse(
signal target : inout std_logic;
constant pulse_value : std_logic;
signal clock_signal : std_logic;
constant num_periods : natural;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant init_value : std_logic := target;
begin
wait until falling_edge(clock_signal);
check_value(target /= pulse_value, TB_ERROR, "gen_pulse: target was already " & to_string(pulse_value) & ". " & add_msg_delimiter(msg), scope, ID_NEVER);
target <= pulse_value; -- Generate pulse
if (num_periods > 0) then
for i in 1 to num_periods loop
wait until falling_edge(clock_signal);
end loop;
end if;
target <= init_value;
log(msg_id, "Pulsed to " & to_string(pulse_value) & " for " & to_string(num_periods) & " clk cycles. " & add_msg_delimiter(msg), scope);
end;
-- Overload to allow excluding the pulse_value argument:
-- Make pulse_value = '1' by default
procedure gen_pulse(
signal target : inout std_logic;
signal clock_signal : std_logic;
constant num_periods : natural;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
gen_pulse(target, '1', clock_signal, num_periods, msg, scope, msg_id, msg_id_panel); -- pulse_value = '1' by default
end;
procedure gen_pulse(
signal target : inout boolean;
constant pulse_value : boolean;
constant pulse_duration : time;
constant blocking_mode : t_blocking_mode;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant init_value : boolean := target;
begin
check_value(target /= pulse_value, TB_ERROR, "gen_pulse: target was already " & to_string(pulse_value) & ". " & add_msg_delimiter(msg), scope, ID_NEVER);
target <= pulse_value; -- Generate pulse
if (blocking_mode = BLOCKING) then
wait for pulse_duration;
target <= init_value;
else
check_value(pulse_duration /= 0 ns, TB_ERROR, "gen_pulse: The combination of NON_BLOCKING mode and 0 ns pulse duration results in the pulse being ignored.", scope, ID_NEVER);
target <= transport init_value after pulse_duration;
end if;
log(msg_id, "Pulsed to " & to_string(pulse_value) & " for " & to_string(pulse_duration) & ". " & add_msg_delimiter(msg), scope);
wait for 0 ns; -- wait a delta cycle for signal to update
end;
-- Overload to allow excluding the pulse_value argument:
-- Make pulse_value = true by default
procedure gen_pulse(
signal target : inout boolean;
constant pulse_duration : time;
constant blocking_mode : t_blocking_mode;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
gen_pulse(target, true, pulse_duration, blocking_mode, msg, scope, msg_id, msg_id_panel); -- Blocking mode by default
end;
-- Overload to allow excluding the blocking_mode and pulse_value arguments:
-- Make blocking_mode = BLOCKING and pulse_value = true by default
procedure gen_pulse(
signal target : inout boolean;
constant pulse_duration : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
gen_pulse(target, true, pulse_duration, BLOCKING, msg, scope, msg_id, msg_id_panel); -- Blocking mode by default
end;
-- Overload to allow excluding the blocking_mode argument:
-- Make blocking_mode = BLOCKING by default
procedure gen_pulse(
signal target : inout boolean;
constant pulse_value : boolean;
constant pulse_duration : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
gen_pulse(target, pulse_value, pulse_duration, BLOCKING, msg, scope, msg_id, msg_id_panel); -- Blocking mode by default
end;
-- Generate a pulse on a boolean for a certain number of clock cycles
procedure gen_pulse(
signal target : inout boolean;
constant pulse_value : boolean;
signal clock_signal : std_logic;
constant num_periods : natural;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant init_value : boolean := target;
begin
wait until falling_edge(clock_signal);
check_value(target /= pulse_value, TB_ERROR, "gen_pulse: target was already " & to_string(pulse_value) & ". " & add_msg_delimiter(msg), scope, ID_NEVER);
target <= pulse_value; -- Generate pulse
if (num_periods > 0) then
for i in 1 to num_periods loop
wait until falling_edge(clock_signal);
end loop;
end if;
target <= init_value;
log(msg_id, "Pulsed to " & to_string(pulse_value) & " for " & to_string(num_periods) & " clk cycles. " & add_msg_delimiter(msg), scope);
end;
-- Overload to allow excluding the pulse_value argument:
-- Make pulse_value = true by default
procedure gen_pulse(
signal target : inout boolean;
signal clock_signal : std_logic;
constant num_periods : natural;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
gen_pulse(target, true, clock_signal, num_periods, msg, scope, msg_id, msg_id_panel); -- pulse_value = '1' by default
end;
-- gen_pulse(slv)
-- Generate a pulse on a std_logic_vector for a certain amount of time
--
-- If blocking_mode = BLOCKING : Procedure waits until the pulse is done before returning to the caller.
-- If blocking_mode = NON_BLOCKING : Procedure starts the pulse, schedules the end of the pulse, then returns to the caller immediately.
--
procedure gen_pulse(
signal target : inout std_logic_vector;
constant pulse_value : std_logic_vector;
constant pulse_duration : time;
constant blocking_mode : t_blocking_mode;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant init_value : std_logic_vector(target'range) := target;
variable v_target : std_logic_vector(target'length-1 downto 0) := target;
variable v_pulse : std_logic_vector(pulse_value'length-1 downto 0) := pulse_value;
begin
check_value(target /= pulse_value, TB_ERROR, "gen_pulse: target was already " & to_string(pulse_value) & ". " & add_msg_delimiter(msg), scope, ID_NEVER);
for i in 0 to (v_target'length-1) loop
if v_pulse(i) /= '-' then
v_target(i) := v_pulse(i); -- Generate pulse
end if;
end loop;
target <= v_target;
if (blocking_mode = BLOCKING) then
wait for pulse_duration;
target <= init_value;
else
check_value(pulse_duration /= 0 ns, TB_ERROR, "gen_pulse: The combination of NON_BLOCKING mode and 0 ns pulse duration results in the pulse being ignored.", scope, ID_NEVER);
target <= transport init_value after pulse_duration;
end if;
log(msg_id, "Pulsed to " & to_string(pulse_value, HEX, AS_IS, INCL_RADIX) & " for " & to_string(pulse_duration) & ". " & add_msg_delimiter(msg), scope);
wait for 0 ns; -- wait a delta cycle for signal to update
end;
-- Overload to allow excluding the pulse_value argument:
-- Make pulse_value = (others => '1') by default
procedure gen_pulse(
signal target : inout std_logic_vector;
constant pulse_duration : time;
constant blocking_mode : t_blocking_mode;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant pulse_value : std_logic_vector(target'range) := (others => '1');
begin
gen_pulse(target, pulse_value, pulse_duration, blocking_mode, msg, scope, msg_id, msg_id_panel); -- Blocking mode by default
end;
-- Overload to allow excluding the blocking_mode and pulse_value arguments:
-- Make blocking_mode = BLOCKING and pulse_value = (others => '1') by default
procedure gen_pulse(
signal target : inout std_logic_vector;
constant pulse_duration : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant pulse_value : std_logic_vector(target'range) := (others => '1');
begin
gen_pulse(target, pulse_value, pulse_duration, BLOCKING, msg, scope, msg_id, msg_id_panel); -- Blocking mode by default
end;
-- Overload to allow excluding the blocking_mode argument:
-- Make blocking_mode = BLOCKING by default
procedure gen_pulse(
signal target : inout std_logic_vector;
constant pulse_value : std_logic_vector;
constant pulse_duration : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
gen_pulse(target, pulse_value, pulse_duration, BLOCKING, msg, scope, msg_id, msg_id_panel); -- Blocking mode by default
end;
-- gen_pulse(slv)
-- Generate a pulse on a std_logic_vector for a certain number of clock cycles
procedure gen_pulse(
signal target : inout std_logic_vector;
constant pulse_value : std_logic_vector;
signal clock_signal : std_logic;
constant num_periods : natural;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant init_value : std_logic_vector(target'range) := target;
constant v_pulse : std_logic_vector(pulse_value'length-1 downto 0) := pulse_value;
variable v_target : std_logic_vector(target'length-1 downto 0) := target;
begin
wait until falling_edge(clock_signal);
check_value(target /= pulse_value, TB_ERROR, "gen_pulse: target was already " & to_string(pulse_value) & ". " & add_msg_delimiter(msg), scope, ID_NEVER);
for i in 0 to (v_target'length-1) loop
if v_pulse(i) /= '-' then
v_target(i) := v_pulse(i); -- Generate pulse
end if;
end loop;
target <= v_target;
if (num_periods > 0) then
for i in 1 to num_periods loop
wait until falling_edge(clock_signal);
end loop;
end if;
target <= init_value;
log(msg_id, "Pulsed to " & to_string(pulse_value, HEX, AS_IS, INCL_RADIX) & " for " & to_string(num_periods) & " clk cycles. " & add_msg_delimiter(msg), scope);
wait for 0 ns; -- wait a delta cycle for signal to update
end;
-- Overload to allow excluding the pulse_value argument:
-- Make pulse_value = (others => '1') by default
procedure gen_pulse(
signal target : inout std_logic_vector;
signal clock_signal : std_logic;
constant num_periods : natural;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant pulse_value : std_logic_vector(target'range) := (others => '1');
begin
gen_pulse(target, pulse_value, clock_signal, num_periods, msg, scope, msg_id, msg_id_panel); -- pulse_value = (others => '1') by default
end;
--------------------------------------------
-- Clock generators :
-- Include this as a concurrent procedure from your test bench.
-- ( Including this procedure call as a concurrent statement directly in your architecture
-- is in fact identical to a process, where the procedure parameters is the sensitivity list )
-- Set duty cycle by setting clock_high_percentage from 1 to 99. Beware of rounding errors.
--------------------------------------------
procedure clock_generator(
signal clock_signal : inout std_logic;
constant clock_period : in time;
constant clock_high_percentage : in natural range 1 to 99 := 50
) is
-- Making sure any rounding error after calculating period/2 is not accumulated.
constant C_FIRST_HALF_CLK_PERIOD : time := clock_period * clock_high_percentage/100;
begin
loop
clock_signal <= '1';
wait for C_FIRST_HALF_CLK_PERIOD;
clock_signal <= '0';
wait for (clock_period - C_FIRST_HALF_CLK_PERIOD);
end loop;
end;
--------------------------------------------
-- Clock generator overload:
-- Include this as a concurrent procedure from your test bench.
-- ( Including this procedure call as a concurrent statement directly in your architecture
-- is in fact identical to a process, where the procedure parameters is the sensitivity list )
-- Set duty cycle by setting clock_high_time.
--------------------------------------------
procedure clock_generator(
signal clock_signal : inout std_logic;
constant clock_period : in time;
constant clock_high_time : in time
) is
begin
check_value(clock_high_time < clock_period, TB_ERROR, "clock_generator: parameter clock_high_time must be lower than parameter clock_period!", C_TB_SCOPE_DEFAULT, ID_NEVER);
loop
clock_signal <= '1';
wait for clock_high_time;
clock_signal <= '0';
wait for (clock_period - clock_high_time);
end loop;
end;
--------------------------------------------
-- Clock generator overload:
-- - Count variable (clock_count) is added as an output. Wraps when reaching max value of
-- natural type.
-- - Set duty cycle by setting clock_high_percentage from 1 to 99. Beware of rounding errors.
--------------------------------------------
procedure clock_generator(
signal clock_signal : inout std_logic;
signal clock_count : inout natural;
constant clock_period : in time;
constant clock_high_percentage : in natural range 1 to 99 := 50
) is
-- Making sure any rounding error after calculating period/2 is not accumulated.
constant C_FIRST_HALF_CLK_PERIOD : time := clock_period * clock_high_percentage/100;
begin
clock_count <= 0;
loop
clock_signal <= '0'; -- Should start on 0
wait for C_FIRST_HALF_CLK_PERIOD;
-- Update clock_count when clock_signal is set to '1'
if clock_count < natural'right then
clock_count <= clock_count + 1;
else -- Wrap when reached max value of natural
clock_count <= 0;
end if;
clock_signal <= '1';
wait for (clock_period - C_FIRST_HALF_CLK_PERIOD);
end loop;
end;
--------------------------------------------
-- Clock generator overload:
-- - Counter clock_count is given as an output. Wraps when reaching max value of
-- natural type.
-- - Set duty cycle by setting clock_high_time.
--------------------------------------------
procedure clock_generator(
signal clock_signal : inout std_logic;
signal clock_count : inout natural;
constant clock_period : in time;
constant clock_high_time : in time
) is
begin
clock_count <= 0;
check_value(clock_high_time < clock_period, TB_ERROR, "clock_generator: parameter clock_high_time must be lower than parameter clock_period!", C_TB_SCOPE_DEFAULT, ID_NEVER);
loop
clock_signal <= '0';
wait for (clock_period - clock_high_time);
if clock_count < natural'right then
clock_count <= clock_count + 1;
else -- Wrap when reached max value of natural
clock_count <= 0;
end if;
clock_signal <= '1';
wait for clock_high_time;
end loop;
end;
--------------------------------------------
-- Clock generator overload:
-- - Enable signal (clock_ena) is added as a parameter
-- - The clock goes to '1' immediately when the clock is enabled (clock_ena = true)
-- - Log when the clock_ena changes. clock_name is used in the log message.
-- - Set duty cycle by setting clock_high_percentage from 1 to 99. Beware of rounding errors.
--------------------------------------------
procedure clock_generator(
signal clock_signal : inout std_logic;
signal clock_ena : in boolean;
constant clock_period : in time;
constant clock_name : in string;
constant clock_high_percentage : in natural range 1 to 99 := 50
) is
-- Making sure any rounding error after calculating period/2 is not accumulated.
constant C_FIRST_HALF_CLK_PERIOD : time := clock_period * clock_high_percentage/100;
begin
loop
if not clock_ena then
if now /= 0 ps then
log(ID_CLOCK_GEN, "Stopping clock " & clock_name);
end if;
clock_signal <= '0';
wait until clock_ena;
log(ID_CLOCK_GEN, "Starting clock " & clock_name);
end if;
clock_signal <= '1';
wait for C_FIRST_HALF_CLK_PERIOD;
clock_signal <= '0';
wait for (clock_period - C_FIRST_HALF_CLK_PERIOD);
end loop;
end;
--------------------------------------------
-- Clock generator overload:
-- - Enable signal (clock_ena) is added as a parameter
-- - The clock goes to '1' immediately when the clock is enabled (clock_ena = true)
-- - Log when the clock_ena changes. clock_name is used in the log message.
-- inferred to be low time.
-- - Set duty cycle by setting clock_high_time.
--------------------------------------------
procedure clock_generator(
signal clock_signal : inout std_logic;
signal clock_ena : in boolean;
constant clock_period : in time;
constant clock_name : in string;
constant clock_high_time : in time
) is
begin
check_value(clock_high_time < clock_period, TB_ERROR, "clock_generator: parameter clock_high_time must be lower than parameter clock_period!", C_TB_SCOPE_DEFAULT, ID_NEVER);
loop
if not clock_ena then
if now /= 0 ps then
log(ID_CLOCK_GEN, "Stopping clock " & clock_name);
end if;
clock_signal <= '0';
wait until clock_ena;
log(ID_CLOCK_GEN, "Starting clock " & clock_name);
end if;
clock_signal <= '1';
wait for clock_high_time;
clock_signal <= '0';
wait for (clock_period - clock_high_time);
end loop;
end;
--------------------------------------------
-- Clock generator overload:
-- - Enable signal (clock_ena) is added as a parameter
-- - The clock goes to '1' immediately when the clock is enabled (clock_ena = true)
-- - Log when the clock_ena changes. clock_name is used in the log message.
-- - Count variable (clock_count) is added as an output. Wraps when reaching max value of
-- natural type.
-- - Set duty cycle by setting clock_high_percentage from 1 to 99. Beware of rounding errors.
--------------------------------------------
procedure clock_generator(
signal clock_signal : inout std_logic;
signal clock_ena : in boolean;
signal clock_count : out natural;
constant clock_period : in time;
constant clock_name : in string;
constant clock_high_percentage : in natural range 1 to 99 := 50
) is
-- Making sure any rounding error after calculating period/2 is not accumulated.
constant C_FIRST_HALF_CLK_PERIOD : time := clock_period * clock_high_percentage/100;
variable v_clock_count : natural := 0;
begin
clock_count <= v_clock_count;
loop
if not clock_ena then
if now /= 0 ps then
log(ID_CLOCK_GEN, "Stopping clock " & clock_name);
end if;
clock_signal <= '0';
wait until clock_ena;
log(ID_CLOCK_GEN, "Starting clock " & clock_name);
end if;
clock_signal <= '1';
wait for C_FIRST_HALF_CLK_PERIOD;
clock_signal <= '0';
wait for (clock_period - C_FIRST_HALF_CLK_PERIOD);
if v_clock_count < natural'right then
v_clock_count := v_clock_count + 1;
else -- Wrap when reached max value of natural
v_clock_count := 0;
end if;
clock_count <= v_clock_count;
end loop;
end;
--------------------------------------------
-- Clock generator overload:
-- - Enable signal (clock_ena) is added as a parameter
-- - The clock goes to '1' immediately when the clock is enabled (clock_ena = true)
-- - Log when the clock_ena changes. clock_name is used in the log message.
-- inferred to be low time.
-- - Count variable (clock_count) is added as an output. Wraps when reaching max value of
-- natural type.
-- - Set duty cycle by setting clock_high_time.
--------------------------------------------
procedure clock_generator(
signal clock_signal : inout std_logic;
signal clock_ena : in boolean;
signal clock_count : out natural;
constant clock_period : in time;
constant clock_name : in string;
constant clock_high_time : in time
) is
variable v_clock_count : natural := 0;
begin
clock_count <= v_clock_count;
check_value(clock_high_time < clock_period, TB_ERROR, "clock_generator: parameter clock_high_time must be lower than parameter clock_period!", C_TB_SCOPE_DEFAULT, ID_NEVER);
loop
if not clock_ena then
if now /= 0 ps then
log(ID_CLOCK_GEN, "Stopping clock " & clock_name);
end if;
clock_signal <= '0';
wait until clock_ena;
log(ID_CLOCK_GEN, "Starting clock " & clock_name);
end if;
clock_signal <= '1';
wait for clock_high_time;
clock_signal <= '0';
wait for (clock_period - clock_high_time);
if v_clock_count < natural'right then
v_clock_count := v_clock_count + 1;
else -- Wrap when reached max value of natural
v_clock_count := 0;
end if;
clock_count <= v_clock_count;
end loop;
end;
--------------------------------------------
-- Adjustable clock generators :
-- Include this as a concurrent procedure from your test bench.
-- ( Including this procedure call as a concurrent statement directly in your architecture
-- is in fact identical to a process, where the procedure parameters is the sensitivity list )
-- Set duty cycle by setting clock_high_percentage from 1 to 99. Beware of rounding errors.
--------------------------------------------
procedure adjustable_clock_generator(
signal clock_signal : inout std_logic;
signal clock_ena : in boolean;
constant clock_period : in time;
constant clock_name : in string;
signal clock_high_percentage : in natural range 0 to 100
) is
-- Making sure any rounding error after calculating period/2 is not accumulated.
variable v_first_half_clk_period : time := clock_period * clock_high_percentage/100;
begin
-- alert if init value is not set
check_value(clock_high_percentage /= 0, TB_ERROR, "clock_generator: parameter clock_high_percentage must be set!", C_TB_SCOPE_DEFAULT, ID_NEVER);
loop
if not clock_ena then
if now /= 0 ps then
log(ID_CLOCK_GEN, "Stopping clock: " & clock_name);
end if;
clock_signal <= '0';
wait until clock_ena;
log(ID_CLOCK_GEN, "Starting clock: " & clock_name);
-- alert if unvalid value is set
check_value_in_range(clock_high_percentage, 1, 99, TB_ERROR, "adjustable_clock_generator: parameter clock_high_percentage must be in range 1 to 99!", C_TB_SCOPE_DEFAULT, ID_NEVER);
end if;
v_first_half_clk_period := clock_period * clock_high_percentage/100;
clock_signal <= '1';
wait for v_first_half_clk_period;
clock_signal <= '0';
wait for (clock_period - v_first_half_clk_period);
end loop;
end procedure;
procedure adjustable_clock_generator(
signal clock_signal : inout std_logic;
signal clock_ena : in boolean;
constant clock_period : in time;
signal clock_high_percentage : in natural range 0 to 100
) is
constant v_clock_name : string := "";
begin
adjustable_clock_generator(clock_signal, clock_ena, clock_period, v_clock_name, clock_high_percentage);
end procedure;
-- Overloaded version with clock enable, clock name
-- and clock count
procedure adjustable_clock_generator(
signal clock_signal : inout std_logic;
signal clock_ena : in boolean;
signal clock_count : out natural;
constant clock_period : in time;
constant clock_name : in string;
signal clock_high_percentage : in natural range 0 to 100
) is
-- Making sure any rounding error after calculating period/2 is not accumulated.
variable v_first_half_clk_period : time := clock_period * clock_high_percentage/100;
variable v_clock_count : natural := 0;
begin
-- alert if init value is not set
check_value(clock_high_percentage /= 0, TB_ERROR, "clock_generator: parameter clock_high_percentage must be set!", C_TB_SCOPE_DEFAULT, ID_NEVER);
clock_count <= v_clock_count;
loop
if not clock_ena then
if now /= 0 ps then
log(ID_CLOCK_GEN, "Stopping clock: " & clock_name);
end if;
clock_signal <= '0';
wait until clock_ena;
log(ID_CLOCK_GEN, "Starting clock: " & clock_name);
-- alert if unvalid value is set
check_value_in_range(clock_high_percentage, 1, 99, TB_ERROR, "adjustable_clock_generator: parameter clock_high_percentage must be in range 1 to 99!", C_TB_SCOPE_DEFAULT, ID_NEVER);
end if;
v_first_half_clk_period := clock_period * clock_high_percentage/100;
clock_signal <= '1';
wait for v_first_half_clk_period;
clock_signal <= '0';
wait for (clock_period - v_first_half_clk_period);
if v_clock_count < natural'right then
v_clock_count := v_clock_count + 1;
else -- Wrap when reached max value of natural
v_clock_count := 0;
end if;
clock_count <= v_clock_count;
end loop;
end procedure;
-- ============================================================================
-- Synchronization methods
-- ============================================================================
-- Local type used in synchronization methods
type t_flag_array_idx_and_status_record is record
flag_idx : integer;
flag_is_new : boolean;
flag_array_full : boolean;
end record;
-- Local function used in synchronization methods to search through shared_flag_array for flag_name or available index
-- Returns:
-- Flag index in the shared array
-- If the flag is new or already in the array
-- If the array is full, and the flag can not be added (alerts an error).
impure function find_or_add_sync_flag(
constant flag_name : string
) return t_flag_array_idx_and_status_record is
variable v_idx : integer := 0;
variable v_is_new : boolean := false;
variable v_is_array_full : boolean := true;
begin
for i in shared_flag_array'range loop
-- Search for empty index. If found add a new flag
if (shared_flag_array(i).flag_name = (shared_flag_array(i).flag_name'range => NUL)) then
shared_flag_array(i).flag_name(flag_name'range) := flag_name;
v_is_new := true;
end if;
-- Check if flag exists in the array
if (shared_flag_array(i).flag_name(flag_name'range) = flag_name) then
v_idx := i;
v_is_array_full := false;
exit;
end if;
end loop;
return (v_idx, v_is_new, v_is_array_full);
end;
procedure block_flag(
constant flag_name : in string;
constant msg : in string;
constant already_blocked_severity : in t_alert_level := warning;
constant scope : in string := C_TB_SCOPE_DEFAULT
) is
variable v_idx : integer := 0;
variable v_is_new : boolean := false;
variable v_is_array_full : boolean := true;
begin
-- Find flag, or add a new provided the array is not full.
(v_idx, v_is_new, v_is_array_full) := find_or_add_sync_flag(flag_name);
if (v_is_array_full = true) then
alert(TB_ERROR, "The flag " & flag_name & " was not found and the maximum number of flags (" & to_string(C_NUM_SYNC_FLAGS) & ") have been used. Configure in adaptations_pkg. " & add_msg_delimiter(msg), scope);
else -- Block flag
if (v_is_new = true) then
log(ID_BLOCKING, flag_name & ": New blocked synchronization flag added. " & add_msg_delimiter(msg), scope);
else
-- Check if the flag to be blocked already is blocked
if (shared_flag_array(v_idx).is_blocked = true) then
alert(already_blocked_severity, "The flag " & flag_name & " was already blocked. " & add_msg_delimiter(msg), scope);
else
log(ID_BLOCKING, flag_name & ": Blocking flag. " & add_msg_delimiter(msg), scope);
end if;
end if;
shared_flag_array(v_idx).is_blocked := true;
end if;
end procedure;
procedure unblock_flag(
constant flag_name : in string;
constant msg : in string;
signal trigger : inout std_logic; -- Parameter must be global_trigger as method await_unblock_flag() uses that global signal to detect unblocking.
constant scope : in string := C_TB_SCOPE_DEFAULT
) is
variable v_idx : integer := 0;
variable v_is_new : boolean := false;
variable v_is_array_full : boolean := true;
begin
-- Find flag, or add a new provided the array is not full.
(v_idx, v_is_new, v_is_array_full) := find_or_add_sync_flag(flag_name);
if (v_is_array_full = true) then
alert(TB_ERROR, "The flag " & flag_name & " was not found and the maximum number of flags (" & to_string(C_NUM_SYNC_FLAGS) & ") have been used. Configure in adaptations_pkg. " & add_msg_delimiter(msg), scope);
else -- Unblock flag
if (v_is_new = true) then
log(ID_BLOCKING, flag_name & ": New unblocked synchronization flag added. " & add_msg_delimiter(msg), scope);
else
log(ID_BLOCKING, flag_name & ": Unblocking flag. " & add_msg_delimiter(msg), scope);
end if;
shared_flag_array(v_idx).is_blocked := false;
-- Triggers a signal to allow await_unblock_flag() to detect unblocking.
gen_pulse(trigger, 0 ns, "pulsing global_trigger. " & add_msg_delimiter(msg), C_TB_SCOPE_DEFAULT, ID_NEVER);
end if;
end procedure;
procedure await_unblock_flag(
constant flag_name : in string;
constant timeout : in time;
constant msg : in string;
constant flag_returning : in t_flag_returning := KEEP_UNBLOCKED;
constant timeout_severity : in t_alert_level := error;
constant scope : in string := C_TB_SCOPE_DEFAULT
) is
variable v_idx : integer := 0;
variable v_is_new : boolean := false;
variable v_is_array_full : boolean := true;
variable v_flag_is_blocked : boolean := true;
constant start_time : time := now;
begin
-- Find flag, or add a new provided the array is not full.
(v_idx, v_is_new, v_is_array_full) := find_or_add_sync_flag(flag_name);
if (v_is_array_full = true) then
alert(TB_ERROR, "The flag " & flag_name & " was not found and the maximum number of flags (" & to_string(C_NUM_SYNC_FLAGS) & ") have been used. Configure in adaptations_pkg. " & add_msg_delimiter(msg), scope);
else -- Waits only if the flag is found and is blocked. Will wait when a new flag is added, as it is default blocked.
v_flag_is_blocked := shared_flag_array(v_idx).is_blocked;
if (v_flag_is_blocked = false) then
if (flag_returning = RETURN_TO_BLOCK) then
-- wait for all sequencer that are waiting for that flag before reseting it
wait for 0 ns;
shared_flag_array(v_idx).is_blocked := true;
log(ID_BLOCKING, flag_name & ": Was already unblocked. Returned to blocked. " & add_msg_delimiter(msg), scope);
else
log(ID_BLOCKING, flag_name & ": Was already unblocked. " & add_msg_delimiter(msg), scope);
end if;
else -- Flag is blocked (or a new flag was added), starts waiting. log before while loop. Otherwise the message will be printed everytime the global_trigger was triggered.
if (v_is_new = true) then
log(ID_BLOCKING, flag_name & ": New blocked synchronization flag added. Waiting to be unblocked. " & add_msg_delimiter(msg), scope);
else
log(ID_BLOCKING, flag_name & ": Waiting to be unblocked. " & add_msg_delimiter(msg), scope);
end if;
end if;
-- Waiting for flag to be unblocked
while v_flag_is_blocked = true loop
if (timeout /= 0 ns) then
wait until rising_edge(global_trigger) for ((start_time + timeout) - now);
check_value(global_trigger = '1', timeout_severity, flag_name & " timed out. " & add_msg_delimiter(msg), scope, ID_NEVER);
if global_trigger /= '1' then
exit;
end if;
else
wait until rising_edge(global_trigger);
end if;
v_flag_is_blocked := shared_flag_array(v_idx).is_blocked;
if (v_flag_is_blocked = false) then
if flag_returning = KEEP_UNBLOCKED then
log(ID_BLOCKING, flag_name & ": Has been unblocked. ", scope);
else
log(ID_BLOCKING, flag_name & ": Has been unblocked. Returned to blocked. ", scope);
-- wait for all sequencer that are waiting for that flag before reseting it
wait for 0 ns;
shared_flag_array(v_idx).is_blocked := true;
end if;
end if;
end loop;
end if;
end procedure;
procedure await_barrier(
signal barrier_signal : inout std_logic;
constant timeout : in time;
constant msg : in string;
constant timeout_severity : in t_alert_level := error;
constant scope : in string := C_TB_SCOPE_DEFAULT
)is
begin
-- set barrier signal to 0
barrier_signal <= '0';
log(ID_BLOCKING, "Waiting for barrier. " & add_msg_delimiter(msg), scope);
-- wait until all sequencer using that barrier_signal wait for it
if timeout = 0 ns then
wait until barrier_signal = '0';
else
wait until barrier_signal = '0' for timeout;
end if;
if barrier_signal /= '0' then
-- timeout
alert(timeout_severity, "Timeout while waiting for barrier signal. " & add_msg_delimiter(msg), scope);
else
log(ID_BLOCKING, "Barrier received. " & add_msg_delimiter(msg), scope);
end if;
barrier_signal <= '1';
end procedure;
procedure await_semaphore_in_delta_cycles(
variable semaphore : inout t_protected_semaphore
) is
variable v_cnt_lock_tries : natural := 0;
begin
while semaphore.get_semaphore = false and v_cnt_lock_tries < C_NUM_SEMAPHORE_LOCK_TRIES loop
wait for 0 ns;
v_cnt_lock_tries := v_cnt_lock_tries + 1;
end loop;
if v_cnt_lock_tries = C_NUM_SEMAPHORE_LOCK_TRIES then
tb_error("Failed to acquire semaphore when sending command to VVC", C_SCOPE);
end if;
end procedure;
procedure release_semaphore(
variable semaphore : inout t_protected_semaphore
) is
begin
semaphore.release_semaphore;
end procedure;
-- ============================================================================
-- General Watchdog-related
-- ============================================================================
-------------------------------------------------------------------------------
-- General Watchdog timer:
-- Include this as a concurrent procedure from your testbench.
-- Use extend_watchdog(), reinitialize_watchdog() or terminate_watchdog() to
-- modify the watchdog timer from the test sequencer.
-------------------------------------------------------------------------------
procedure watchdog_timer(
signal watchdog_ctrl : in t_watchdog_ctrl;
constant timeout : time;
constant alert_level : t_alert_level := error;
constant msg : string := ""
) is
variable v_timeout : time;
variable v_prev_timeout : time;
begin
-- This delta cycle is needed due to a problem with external tools that
-- without it, they wouldn't print the first log message.
wait for 0 ns;
log(ID_WATCHDOG, "Starting general watchdog: " & to_string(timeout) & ". " & msg);
v_prev_timeout := 0 ns;
v_timeout := timeout;
loop
wait until (watchdog_ctrl.extend or watchdog_ctrl.restart or watchdog_ctrl.terminate) for v_timeout;
-- Watchdog was extended
if watchdog_ctrl.extend then
if watchdog_ctrl.extension = 0 ns then
log(ID_WATCHDOG, "Extending general watchdog by default value: " & to_string(timeout) & ". " & msg);
v_timeout := (v_prev_timeout + v_timeout - now) + timeout;
else
log(ID_WATCHDOG, "Extending general watchdog by " & to_string(watchdog_ctrl.extension) & ". " & msg);
v_timeout := (v_prev_timeout + v_timeout - now) + watchdog_ctrl.extension;
end if;
v_prev_timeout := now;
-- Watchdog was reinitialized
elsif watchdog_ctrl.restart then
log(ID_WATCHDOG, "Reinitializing general watchdog: " & to_string(watchdog_ctrl.new_timeout) & ". " & msg);
v_timeout := watchdog_ctrl.new_timeout;
v_prev_timeout := now;
else
-- Watchdog was terminated
if watchdog_ctrl.terminate then
log(ID_WATCHDOG, "Terminating general watchdog. " & msg);
-- Watchdog has timed out
else
alert(alert_level, "General watchdog timer ended! " & msg);
end if;
exit;
end if;
end loop;
wait;
end procedure;
procedure extend_watchdog(
signal watchdog_ctrl : inout t_watchdog_ctrl;
constant time_extend : time := 0 ns
) is
begin
if not watchdog_ctrl.terminate then
watchdog_ctrl.extension <= time_extend;
watchdog_ctrl.extend <= true;
wait for 0 ns; -- delta cycle to propagate signal
watchdog_ctrl.extend <= false;
end if;
end procedure;
procedure reinitialize_watchdog(
signal watchdog_ctrl : inout t_watchdog_ctrl;
constant timeout : time
) is
begin
if not watchdog_ctrl.terminate then
watchdog_ctrl.new_timeout <= timeout;
watchdog_ctrl.restart <= true;
wait for 0 ns; -- delta cycle to propagate signal
watchdog_ctrl.restart <= false;
end if;
end procedure;
procedure terminate_watchdog(
signal watchdog_ctrl : inout t_watchdog_ctrl
) is
begin
watchdog_ctrl.terminate <= true;
wait for 0 ns; -- delta cycle to propagate signal
end procedure;
-- ============================================================================
-- generate_crc
-- ============================================================================
impure function generate_crc(
constant data : in std_logic_vector;
constant crc_in : in std_logic_vector;
constant polynomial : in std_logic_vector
) return std_logic_vector is
variable crc_out : std_logic_vector(crc_in'range) := crc_in;
begin
-- Sanity checks
check_value(not data'ascending, TB_FAILURE, "data have to be decending", C_SCOPE, ID_NEVER);
check_value(not crc_in'ascending, TB_FAILURE, "crc_in have to be decending", C_SCOPE, ID_NEVER);
check_value(not polynomial'ascending, TB_FAILURE, "polynomial have to be decending", C_SCOPE, ID_NEVER);
check_value(crc_in'length, polynomial'length-1, TB_FAILURE, "crc_in have to be one bit shorter than polynomial", C_SCOPE, ID_NEVER);
for i in data'high downto data'low loop
if crc_out(crc_out'high) xor data(i) then
crc_out := crc_out sll 1;
crc_out := crc_out xor polynomial(polynomial'high-1 downto polynomial'low);
else
crc_out := crc_out sll 1;
end if;
end loop;
return crc_out;
end function generate_crc;
impure function generate_crc(
constant data : in t_slv_array;
constant crc_in : in std_logic_vector;
constant polynomial : in std_logic_vector
) return std_logic_vector is
variable crc_out : std_logic_vector(crc_in'range) := crc_in;
begin
-- Sanity checks
check_value(data'ascending, TB_FAILURE, "slv array have to be acending", C_SCOPE, ID_NEVER);
for i in data'low to data'high loop
crc_out := generate_crc(data(i), crc_out, polynomial);
end loop;
return crc_out;
end function generate_crc;
end package body methods_pkg;
|
mit
|
UVVM/UVVM_All
|
bitvis_vip_scoreboard/tb/sb_uart_sbi_demo_tb.vhd
|
1
|
7832
|
--================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
----------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library bitvis_uart;
use bitvis_uart.uart_pif_pkg.all;
library bitvis_vip_sbi;
use bitvis_vip_sbi.sbi_bfm_pkg.all;
library bitvis_vip_uart;
use bitvis_vip_uart.uart_bfm_pkg.all;
library bitvis_vip_scoreboard;
use bitvis_vip_scoreboard.slv8_sb_pkg.all;
use bitvis_vip_scoreboard.generic_sb_support_pkg.all;
--hdlunit:tb
-- Test harness entity
entity sb_uart_sbi_demo_tb is
end entity sb_uart_sbi_demo_tb;
-- Test harness architecture
architecture func of sb_uart_sbi_demo_tb is
constant C_SCOPE : string := "TB";
constant C_ADDR_WIDTH : integer := 3;
constant C_DATA_WIDTH : integer := 8;
-- DSP interface and general control signals
signal clk : std_logic := '0';
signal clk_ena : boolean := false;
signal arst : std_logic := '0';
-- SBI signals
signal sbi_if : t_sbi_if(addr(C_ADDR_WIDTH-1 downto 0),
wdata(C_DATA_WIDTH-1 downto 0),
rdata(C_DATA_WIDTH-1 downto 0)) := init_sbi_if_signals(addr_width => C_ADDR_WIDTH,
data_width => C_DATA_WIDTH);
signal terminate_loop : std_logic := '0';
-- UART signals
signal uart_rx : std_logic := '1';
signal uart_tx : std_logic := '1';
constant C_CLK_PERIOD : time := 10 ns; -- 100 MHz
-- One SB for each side of the DUT
shared variable v_uart_sb : t_generic_sb;
shared variable v_sbi_sb : t_generic_sb;
begin
-----------------------------------------------------------------------------
-- Instantiate DUT
-----------------------------------------------------------------------------
i_uart: entity bitvis_uart.uart
port map (
-- DSP interface and general control signals
clk => clk,
arst => arst,
-- CPU interface
cs => sbi_if.cs,
addr => sbi_if.addr,
wr => sbi_if.wena,
rd => sbi_if.rena,
wdata => sbi_if.wdata,
rdata => sbi_if.rdata,
-- UART signals
rx_a => uart_tx,
tx => uart_rx
);
-----------------------------------------------------------------------------
-- Clock generator
-----------------------------------------------------------------------------
p_clk: clock_generator(clk, clk_ena, C_CLK_PERIOD, "tb clock");
-- Static '1' ready signal for the SBI VVC
sbi_if.ready <= '1';
-- Toggle the reset after 5 clock periods
p_arst: arst <= '1', '0' after 5 *C_CLK_PERIOD;
-----------------------------------------------------------------------------
-- Sequencer
-----------------------------------------------------------------------------
p_sequencer : process
variable v_data : std_logic_vector(7 downto 0);
variable v_uart_config : t_uart_bfm_config;
begin
set_log_file_name("sb_uart_sbi_demo_log.txt");
set_alert_file_name("sb_uart_sbi_demo_alert.txt");
-- Print the configuration to the log
report_global_ctrl(VOID);
report_msg_id_panel(VOID);
--enable_log_msg(ALL_MESSAGES);
disable_log_msg(ID_POS_ACK);
--disable_log_msg(ID_SEQUENCER_SUB);
log(ID_LOG_HDR_XL, "SCOREBOARD UART-SBI DEMO ", C_SCOPE);
------------------------------------------------------------
clk_ena <= true;
wait for 1 ns;
await_value(arst, '0', 0 ns, 6*C_CLK_PERIOD, TB_ERROR, "await deassertion of arst", C_SCOPE);
wait for C_CLK_PERIOD;
------------------------------------------------------------
-- Config
------------------------------------------------------------
-- Set scope of SBs
v_uart_sb.set_scope("SB UART");
v_sbi_sb.set_scope( "SB SBI");
log(ID_LOG_HDR, "Set configuration", C_SCOPE);
v_uart_sb.config(C_SB_CONFIG_DEFAULT, "Set config for SB UART");
v_sbi_sb.config( C_SB_CONFIG_DEFAULT, "Set config for SB SBI");
log(ID_LOG_HDR, "Enable SBs", C_SCOPE);
v_uart_sb.enable(VOID);
v_sbi_sb.enable(VOID);
-- Enable log msg for data
v_uart_sb.enable_log_msg(ID_DATA);
v_sbi_sb.enable_log_msg( ID_DATA);
v_uart_config := C_UART_BFM_CONFIG_DEFAULT;
v_uart_config.bit_time := C_CLK_PERIOD*16;
------------------------------------------------------------
-- UART --> SBI
------------------------------------------------------------
log(ID_LOG_HDR_LARGE, "Send data UART --> SBI", C_SCOPE);
for i in 1 to 5 loop
for j in 1 to 4 loop
v_data := random(8);
v_sbi_sb.add_expected(v_data);
uart_transmit(v_data, "data to DUT", uart_tx, v_uart_config);
end loop;
for j in 1 to 4 loop
sbi_poll_until(to_unsigned(C_ADDR_RX_DATA_VALID, 3), x"01", 0, 100 ns, "wait on data valid", clk, sbi_if, terminate_loop);
sbi_read(to_unsigned(C_ADDR_RX_DATA, 3), v_data, "read data from DUT", clk, sbi_if);
v_sbi_sb.check_received(v_data);
end loop;
end loop;
-- print report of counters
v_sbi_sb.report_counters(VOID);
------------------------------------------------------------
-- SBI --> UART
------------------------------------------------------------
log(ID_LOG_HDR_LARGE, "Send data SBI --> UART", C_SCOPE);
for i in 1 to 5 loop
for j in 1 to 4 loop
v_data := random(8);
v_uart_sb.add_expected(v_data);
sbi_poll_until(to_unsigned(C_ADDR_TX_READY, 3), x"01", 0, 100 ns, "wait on TX ready", clk, sbi_if, terminate_loop);
sbi_write(to_unsigned(C_ADDR_TX_DATA, 3), v_data, "write data to DUT", clk, sbi_if);
uart_receive(v_data, "data from DUT", uart_rx, terminate_loop, v_uart_config);
v_uart_sb.check_received(v_data);
end loop;
end loop;
-- print report of counters
v_uart_sb.report_counters(VOID);
--==================================================================================================
-- Ending the simulation
--------------------------------------------------------------------------------------
wait for 1000 ns; -- to allow some time for completion
report_alert_counters(FINAL); -- Report final counters and print conclusion for simulation (Success/Fail)
log(ID_LOG_HDR, "SIMULATION COMPLETED", C_SCOPE);
std.env.stop;
wait;
end process;
end architecture func;
|
mit
|
YingcaiDong/Shunting-Model-Based-Path-Planning-Algorithm-Accelerator-Using-FPGA
|
System Design Source FIle/ipshared/xilinx.com/axi_datamover_v5_1/3acd8cae/hdl/src/vhdl/axi_datamover_skid2mm_buf.vhd
|
6
|
17324
|
-------------------------------------------------------------------------------
-- axi_datamover_skid2mm_buf.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_skid2mm_buf.vhd
--
-- Description:
-- Implements the AXi Skid Buffer in the Option 2 (Registerd outputs) mode.
--
-- This Module also provides Write Data Bus Mirroring and WSTRB
-- Demuxing to match a narrow Stream to a wider MMap Write
-- Channel. By doing this in the skid buffer, the resource
-- utilization of the skid buffer can be minimized by only
-- having to buffer/mux the Stream data width, not the MMap
-- Data width.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_datamover_v5_1;
use axi_datamover_v5_1.axi_datamover_wr_demux;
-------------------------------------------------------------------------------
entity axi_datamover_skid2mm_buf is
generic (
C_MDATA_WIDTH : INTEGER range 32 to 1024 := 32 ;
-- Width of the MMap Write Data bus (in bits)
C_SDATA_WIDTH : INTEGER range 8 to 1024 := 32 ;
-- Width of the Stream Data bus (in bits)
C_ADDR_LSB_WIDTH : INTEGER range 1 to 8 := 5
-- Width of the LS address bus needed to Demux the WSTRB
);
port (
-- Clock and Reset Inputs -------------------------------------------
--
ACLK : In std_logic ; --
ARST : In std_logic ; --
---------------------------------------------------------------------
-- Slave Side (Wr Data Controller Input Side) -----------------------
--
S_ADDR_LSB : in std_logic_vector(C_ADDR_LSB_WIDTH-1 downto 0); --
S_VALID : In std_logic ; --
S_READY : Out std_logic ; --
S_DATA : In std_logic_vector(C_SDATA_WIDTH-1 downto 0); --
S_STRB : In std_logic_vector((C_SDATA_WIDTH/8)-1 downto 0); --
S_LAST : In std_logic ; --
---------------------------------------------------------------------
-- Master Side (MMap Write Data Output Side) ------------------------
M_VALID : Out std_logic ; --
M_READY : In std_logic ; --
M_DATA : Out std_logic_vector(C_MDATA_WIDTH-1 downto 0); --
M_STRB : Out std_logic_vector((C_MDATA_WIDTH/8)-1 downto 0); --
M_LAST : Out std_logic --
---------------------------------------------------------------------
);
end entity axi_datamover_skid2mm_buf;
architecture implementation of axi_datamover_skid2mm_buf is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
Constant IN_DATA_WIDTH : integer := C_SDATA_WIDTH;
Constant MM2STRM_WIDTH_RATIO : integer := C_MDATA_WIDTH/C_SDATA_WIDTH;
-- Signals decalrations -------------------------
Signal sig_reset_reg : std_logic := '0';
signal sig_spcl_s_ready_set : std_logic := '0';
signal sig_data_skid_reg : std_logic_vector(IN_DATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_skid_reg : std_logic_vector((C_MDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_skid_reg : std_logic := '0';
signal sig_skid_reg_en : std_logic := '0';
signal sig_data_skid_mux_out : std_logic_vector(IN_DATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_skid_mux_out : std_logic_vector((C_MDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_skid_mux_out : std_logic := '0';
signal sig_skid_mux_sel : std_logic := '0';
signal sig_data_reg_out : std_logic_vector(IN_DATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_reg_out : std_logic_vector((C_MDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_reg_out : std_logic := '0';
signal sig_data_reg_out_en : std_logic := '0';
signal sig_m_valid_out : std_logic := '0';
signal sig_m_valid_dup : std_logic := '0';
signal sig_m_valid_comb : std_logic := '0';
signal sig_s_ready_out : std_logic := '0';
signal sig_s_ready_dup : std_logic := '0';
signal sig_s_ready_comb : std_logic := '0';
signal sig_mirror_data_out : std_logic_vector(C_MDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_wstrb_demux_out : std_logic_vector((C_MDATA_WIDTH/8)-1 downto 0) := (others => '0');
-- Register duplication attribute assignments to control fanout
-- on handshake output signals
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
Attribute KEEP of sig_m_valid_out : signal is "TRUE"; -- definition
Attribute KEEP of sig_m_valid_dup : signal is "TRUE"; -- definition
Attribute KEEP of sig_s_ready_out : signal is "TRUE"; -- definition
Attribute KEEP of sig_s_ready_dup : signal is "TRUE"; -- definition
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_m_valid_out : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_m_valid_dup : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_out : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_dup : signal is "no";
begin --(architecture implementation)
M_VALID <= sig_m_valid_out;
S_READY <= sig_s_ready_out;
M_STRB <= sig_strb_reg_out;
M_LAST <= sig_last_reg_out;
M_DATA <= sig_mirror_data_out;
-- Assign the special S_READY FLOP set signal
sig_spcl_s_ready_set <= sig_reset_reg;
-- Generate the ouput register load enable control
sig_data_reg_out_en <= M_READY or not(sig_m_valid_dup);
-- Generate the skid inpit register load enable control
sig_skid_reg_en <= sig_s_ready_dup;
-- Generate the skid mux select control
sig_skid_mux_sel <= not(sig_s_ready_dup);
-- Skid Mux
sig_data_skid_mux_out <= sig_data_skid_reg
When (sig_skid_mux_sel = '1')
Else S_DATA;
sig_strb_skid_mux_out <= sig_strb_skid_reg
When (sig_skid_mux_sel = '1')
--Else S_STRB;
Else sig_wstrb_demux_out;
sig_last_skid_mux_out <= sig_last_skid_reg
When (sig_skid_mux_sel = '1')
Else S_LAST;
-- m_valid combinational logic
sig_m_valid_comb <= S_VALID or
(sig_m_valid_dup and
(not(sig_s_ready_dup) or
not(M_READY)));
-- s_ready combinational logic
sig_s_ready_comb <= M_READY or
(sig_s_ready_dup and
(not(sig_m_valid_dup) or
not(S_VALID)));
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_THE_RST
--
-- Process Description:
-- Register input reset
--
-------------------------------------------------------------
REG_THE_RST : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
sig_reset_reg <= ARST;
end if;
end process REG_THE_RST;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: S_READY_FLOP
--
-- Process Description:
-- Registers S_READY handshake signals per Skid Buffer
-- Option 2 scheme
--
-------------------------------------------------------------
S_READY_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_s_ready_out <= '0';
sig_s_ready_dup <= '0';
Elsif (sig_spcl_s_ready_set = '1') Then
sig_s_ready_out <= '1';
sig_s_ready_dup <= '1';
else
sig_s_ready_out <= sig_s_ready_comb;
sig_s_ready_dup <= sig_s_ready_comb;
end if;
end if;
end process S_READY_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: M_VALID_FLOP
--
-- Process Description:
-- Registers M_VALID handshake signals per Skid Buffer
-- Option 2 scheme
--
-------------------------------------------------------------
M_VALID_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1' or
sig_spcl_s_ready_set = '1') then -- Fix from AXI DMA
sig_m_valid_out <= '0';
sig_m_valid_dup <= '0';
else
sig_m_valid_out <= sig_m_valid_comb;
sig_m_valid_dup <= sig_m_valid_comb;
end if;
end if;
end process M_VALID_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SKID_DATA_REG
--
-- Process Description:
-- This process implements the Skid register for the
-- Skid Buffer Data signals.
--
-------------------------------------------------------------
SKID_DATA_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (sig_skid_reg_en = '1') then
sig_data_skid_reg <= S_DATA;
else
null; -- hold current state
end if;
end if;
end process SKID_DATA_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SKID_CNTL_REG
--
-- Process Description:
-- This process implements the Output registers for the
-- Skid Buffer Control signals
--
-------------------------------------------------------------
SKID_CNTL_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_strb_skid_reg <= (others => '0');
sig_last_skid_reg <= '0';
elsif (sig_skid_reg_en = '1') then
sig_strb_skid_reg <= sig_wstrb_demux_out;
sig_last_skid_reg <= S_LAST;
else
null; -- hold current state
end if;
end if;
end process SKID_CNTL_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: OUTPUT_DATA_REG
--
-- Process Description:
-- This process implements the Output register for the
-- Data signals.
--
-------------------------------------------------------------
OUTPUT_DATA_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (sig_data_reg_out_en = '1') then
sig_data_reg_out <= sig_data_skid_mux_out;
else
null; -- hold current state
end if;
end if;
end process OUTPUT_DATA_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: OUTPUT_CNTL_REG
--
-- Process Description:
-- This process implements the Output registers for the
-- control signals.
--
-------------------------------------------------------------
OUTPUT_CNTL_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_strb_reg_out <= (others => '0');
sig_last_reg_out <= '0';
elsif (sig_data_reg_out_en = '1') then
sig_strb_reg_out <= sig_strb_skid_mux_out;
sig_last_reg_out <= sig_last_skid_mux_out;
else
null; -- hold current state
end if;
end if;
end process OUTPUT_CNTL_REG;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_WR_DATA_MIRROR
--
-- Process Description:
-- Implement the Write Data Mirror structure
--
-- Note that it is required that the Stream Width be less than
-- or equal to the MMap WData width.
--
-------------------------------------------------------------
DO_WR_DATA_MIRROR : process (sig_data_reg_out)
begin
for slice_index in 0 to MM2STRM_WIDTH_RATIO-1 loop
sig_mirror_data_out(((C_SDATA_WIDTH*slice_index)+C_SDATA_WIDTH)-1
downto C_SDATA_WIDTH*slice_index)
<= sig_data_reg_out;
end loop;
end process DO_WR_DATA_MIRROR;
------------------------------------------------------------
-- Instance: I_WSTRB_DEMUX
--
-- Description:
-- Instance for the Write Strobe DeMux.
--
------------------------------------------------------------
I_WSTRB_DEMUX : entity axi_datamover_v5_1.axi_datamover_wr_demux
generic map (
C_SEL_ADDR_WIDTH => C_ADDR_LSB_WIDTH ,
C_MMAP_DWIDTH => C_MDATA_WIDTH ,
C_STREAM_DWIDTH => C_SDATA_WIDTH
)
port map (
wstrb_in => S_STRB ,
demux_wstrb_out => sig_wstrb_demux_out ,
debeat_saddr_lsb => S_ADDR_LSB
);
end implementation;
|
mit
|
UVVM/UVVM_All
|
uvvm_vvc_framework/src_target_dependent/td_vvc_entity_support_pkg.vhd
|
1
|
48563
|
--================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
----------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
use work.td_cmd_queue_pkg.all;
use work.td_result_queue_pkg.all;
use work.vvc_cmd_pkg.all;
use work.vvc_methods_pkg.all;
use work.td_vvc_framework_common_methods_pkg.all;
use work.td_target_support_pkg.all;
--=================================================================================================
--=================================================================================================
--=================================================================================================
package td_vvc_entity_support_pkg is
type t_vvc_labels is record
scope : string(1 to C_LOG_SCOPE_WIDTH);
vvc_name : string(1 to C_LOG_SCOPE_WIDTH-2);
instance_idx : natural;
channel : t_channel;
end record;
-------------------------------------------
-- assign_vvc_labels
-------------------------------------------
-- This function puts common VVC labels into a record - to reduce the number of procedure parameters
function assign_vvc_labels(
scope : string;
vvc_name : string;
instance_idx : integer;
channel : t_channel
) return t_vvc_labels;
-------------------------------------------
-- format_msg
-------------------------------------------
-- Generates a sting containing the command message and index
-- - Format: Message [index]
impure function format_msg(
command : t_vvc_cmd_record
) return string;
-------------------------------------------
-- vvc_constructor
-------------------------------------------
-- Procedure used as concurrent process in the VVCs
-- - Sets up the vvc_config, command queue and result_queue
-- - Verifies that UVVM has been initialized
procedure vvc_constructor(
constant scope : in string;
constant instance_idx : in natural;
variable vvc_config : inout t_vvc_config;
variable command_queue : inout work.td_cmd_queue_pkg.t_generic_queue;
variable result_queue : inout work.td_result_queue_pkg.t_generic_queue;
constant bfm_config : in t_bfm_config;
constant cmd_queue_count_max : in natural;
constant cmd_queue_count_threshold : in natural;
constant cmd_queue_count_threshold_severity : in t_alert_level;
constant result_queue_count_max : in natural;
constant result_queue_count_threshold : in natural;
constant result_queue_count_threshold_severity : in t_alert_level
);
-------------------------------------------
-- initialize_interpreter
-------------------------------------------
-- Initialises the VVC interpreter
-- - Clears terminate_current_cmd.set to '0'
procedure initialize_interpreter (
signal terminate_current_cmd : out t_flag_record;
signal global_awaiting_completion : out std_logic_vector(C_MAX_NUM_SEQUENCERS-1 downto 0)
);
function get_msg_id_panel(
constant command : in t_vvc_cmd_record;
constant vvc_config : in t_vvc_config
) return t_msg_id_panel;
-------------------------------------------
-- await_cmd_from_sequencer
-------------------------------------------
-- Waits for a command from the central sequencer. Continues on matching VVC, Instance, Name and Channel (unless channel = NA)
-- - Log at start using ID_CMD_INTERPRETER_WAIT and at the end using ID_CMD_INTERPRETER
procedure await_cmd_from_sequencer(
constant vvc_labels : in t_vvc_labels;
constant vvc_config : in t_vvc_config;
signal VVCT : in t_vvc_target_record;
signal VVC_BROADCAST : inout std_logic;
signal global_vvc_busy : inout std_logic;
signal vvc_ack : out std_logic;
variable output_vvc_cmd : out t_vvc_cmd_record;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel --UVVM: unused, remove in v3.0
);
-- DEPRECATED
procedure await_cmd_from_sequencer(
constant vvc_labels : in t_vvc_labels;
constant vvc_config : in t_vvc_config;
signal VVCT : in t_vvc_target_record;
signal VVC_BROADCAST : inout std_logic;
signal global_vvc_busy : inout std_logic;
signal vvc_ack : out std_logic;
constant shared_vvc_cmd : in t_vvc_cmd_record;
variable output_vvc_cmd : out t_vvc_cmd_record
);
-------------------------------------------
-- put_command_on_queue
-------------------------------------------
-- Puts the received command (by Interpreter) on the VVC queue (for later retrieval by Executor)
procedure put_command_on_queue(
constant command : in t_vvc_cmd_record;
variable command_queue : inout work.td_cmd_queue_pkg.t_generic_queue;
variable vvc_status : inout t_vvc_status;
signal queue_is_increasing : out boolean
);
-------------------------------------------
-- interpreter_await_completion
-------------------------------------------
-- Immediate command: await_completion (in interpreter)
-- - Command description in Quick reference for UVVM common methods
-- - Will wait until given command(s) is completed by the excutor (if not already completed)
-- - Log using ID_IMMEDIATE_CMD when await completed
-- - Log using ID_IMMEDIATE_CMD_WAIT if waiting is actually needed
procedure interpreter_await_completion(
constant command : in t_vvc_cmd_record;
variable command_queue : inout work.td_cmd_queue_pkg.t_generic_queue;
constant vvc_config : in t_vvc_config;
signal executor_is_busy : in boolean;
constant vvc_labels : in t_vvc_labels;
signal last_cmd_idx_executed : in natural;
constant await_completion_pending_msg_id : in t_msg_id := ID_IMMEDIATE_CMD_WAIT;
constant await_completion_finished_msg_id : in t_msg_id := ID_IMMEDIATE_CMD
);
-------------------------------------------
-- interpreter_await_any_completion
-------------------------------------------
-- Immediate command: await_any_completion() (in interpreter)
-- - This procedure is called by the interpreter if sequencer calls await_any_completion()
-- - It waits for the first of the following :
-- 'await_completion' of this VVC, or
-- until global_awaiting_completion(idx) /= '1' (any of the other involved VVCs completed).
-- - Refer to description in Quick reference for UVVM common methods
-- - Log using ID_IMMEDIATE_CMD when the wait completed
-- - Log using ID_IMMEDIATE_CMD_WAIT if waiting is actually needed
procedure interpreter_await_any_completion(
constant command : in t_vvc_cmd_record;
variable command_queue : inout work.td_cmd_queue_pkg.t_generic_queue;
constant vvc_config : in t_vvc_config;
signal executor_is_busy : in boolean;
constant vvc_labels : in t_vvc_labels;
signal last_cmd_idx_executed : in natural;
signal global_awaiting_completion : inout std_logic_vector; -- Handshake with other VVCs performing await_any_completion
constant await_completion_pending_msg_id : in t_msg_id := ID_IMMEDIATE_CMD_WAIT;
constant await_completion_finished_msg_id : in t_msg_id := ID_IMMEDIATE_CMD
);
-------------------------------------------
-- interpreter_flush_command_queue
-------------------------------------------
-- Immediate command: flush_command_queue (in interpreter)
-- - Command description in Quick reference for UVVM common methods
-- - Log using ID_IMMEDIATE_CMD
procedure interpreter_flush_command_queue(
constant command : in t_vvc_cmd_record;
variable command_queue : inout work.td_cmd_queue_pkg.t_generic_queue;
constant vvc_config : in t_vvc_config;
variable vvc_status : inout t_vvc_status;
constant vvc_labels : in t_vvc_labels
);
-------------------------------------------
-- interpreter_terminate_current_command
-------------------------------------------
-- Immediate command: terminate_current_command (in interpreter)
-- - Command description in Quick reference for UVVM common methods
-- - Log using ID_IMMEDIATE_CMD
procedure interpreter_terminate_current_command(
constant command : in t_vvc_cmd_record;
constant vvc_config : in t_vvc_config;
constant vvc_labels : in t_vvc_labels;
signal terminate_current_cmd : inout t_flag_record;
constant executor_is_busy : in boolean := true
);
-------------------------------------------
-- interpreter_fetch_result
-------------------------------------------
-- Immediate command: interpreter_fetch_result (in interpreter)
-- - Command description in Quick reference for UVVM common methods
-- - Log using ID_IMMEDIATE_CMD
-- t_vvc_response is specific to each VVC,
-- so the BFM can return any type which is then transported from the VVC to the sequencer via a fetch_result() call
procedure interpreter_fetch_result(
variable result_queue : inout work.td_result_queue_pkg.t_generic_queue;
constant command : in t_vvc_cmd_record;
constant vvc_config : in t_vvc_config;
constant vvc_labels : in t_vvc_labels;
constant last_cmd_idx_executed : in natural;
variable shared_vvc_response : inout work.vvc_cmd_pkg.t_vvc_response
);
-------------------------------------------
-- initialize_executor
-------------------------------------------
-- Initialises the VVC executor
-- - Resets terminate_current_cmd.reset flag
procedure initialize_executor (
signal terminate_current_cmd : inout t_flag_record
);
-------------------------------------------
-- fetch_command_and_prepare_executor
-------------------------------------------
-- Fetches a command from the queue (waits until available if needed)
-- - Log command using ID_CMD_EXECUTOR
-- - Log using ID_CMD_EXECUTOR_WAIT if queue is empty
-- - Sets relevant flags
procedure fetch_command_and_prepare_executor(
variable command : inout t_vvc_cmd_record;
variable command_queue : inout work.td_cmd_queue_pkg.t_generic_queue;
constant vvc_config : in t_vvc_config;
variable vvc_status : inout t_vvc_status;
signal queue_is_increasing : in boolean;
signal executor_is_busy : inout boolean;
constant vvc_labels : in t_vvc_labels;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel; --UVVM: unused, remove in v3.0
constant executor_id : in t_msg_id := ID_CMD_EXECUTOR;
constant executor_wait_id : in t_msg_id := ID_CMD_EXECUTOR_WAIT
);
-------------------------------------------
-- store_result
-------------------------------------------
-- Store result from BFM in the VVC's result_queue
-- The result_queue is used to store a generic type that is returned from
-- a read/expect BFM procedure.
-- It can be fetched later using fetch_result() to return it from the VVC to sequencer
procedure store_result(
variable result_queue : inout work.td_result_queue_pkg.t_generic_queue;
constant cmd_idx : in natural;
constant result : in t_vvc_result
);
-------------------------------------------
-- insert_inter_bfm_delay_if_requested
-------------------------------------------
-- Inserts delay of either START2START or FINISH2START in time, given that
-- - vvc_config inter-bfm delay type is not set to NO_DELAY
-- - command_is_bfm_access is set to true
-- - Both timestamps are not set to 0 ns.
-- A log message with ID ID_CMD_EXECUTOR is issued when the delay begins and
-- when it has finished delaying.
procedure insert_inter_bfm_delay_if_requested(
constant vvc_config : in t_vvc_config;
constant command_is_bfm_access : in boolean;
constant timestamp_start_of_last_bfm_access : in time;
constant timestamp_end_of_last_bfm_access : in time;
constant msg_id_panel : in t_msg_id_panel;
constant scope : in string := C_SCOPE
);
procedure insert_inter_bfm_delay_if_requested(
constant vvc_config : in t_vvc_config;
constant command_is_bfm_access : in boolean;
constant timestamp_start_of_last_bfm_access : in time;
constant timestamp_end_of_last_bfm_access : in time;
constant scope : in string := C_SCOPE
);
function broadcast_cmd_to_shared_cmd (
constant broadcast_cmd : t_broadcastable_cmd
) return t_operation;
function get_command_type_from_operation (
constant broadcast_cmd : t_broadcastable_cmd
) return t_immediate_or_queued;
procedure populate_shared_vvc_cmd_with_broadcast (
variable output_vvc_cmd : out t_vvc_cmd_record;
constant scope : in string := C_SCOPE
);
end package td_vvc_entity_support_pkg;
package body td_vvc_entity_support_pkg is
function assign_vvc_labels(
scope : string;
vvc_name : string;
instance_idx : integer;
channel : t_channel
) return t_vvc_labels is
variable vvc_labels : t_vvc_labels;
begin
vvc_labels.scope := pad_string(scope, NUL, vvc_labels.scope'length);
vvc_labels.vvc_name := pad_string(vvc_name, NUL, vvc_labels.vvc_name'length);
vvc_labels.instance_idx := instance_idx;
vvc_labels.channel := channel;
return vvc_labels;
end;
impure function format_msg(
command : t_vvc_cmd_record
) return string is
begin
return add_msg_delimiter(to_string(command.msg)) & " " & format_command_idx(command);
end;
procedure vvc_constructor(
constant scope : in string;
constant instance_idx : in natural;
variable vvc_config : inout t_vvc_config;
variable command_queue : inout work.td_cmd_queue_pkg.t_generic_queue;
variable result_queue : inout work.td_result_queue_pkg.t_generic_queue;
constant bfm_config : in t_bfm_config;
constant cmd_queue_count_max : in natural;
constant cmd_queue_count_threshold : in natural;
constant cmd_queue_count_threshold_severity : in t_alert_level;
constant result_queue_count_max : in natural;
constant result_queue_count_threshold : in natural;
constant result_queue_count_threshold_severity : in t_alert_level
) is
variable v_delta_cycle_counter : natural := 0;
variable v_comma_number : natural := 0;
begin
check_value(instance_idx <= C_MAX_VVC_INSTANCE_NUM-1, TB_FAILURE, "Generic VVC Instance index =" & to_string(instance_idx) &
" cannot exceed C_MAX_VVC_INSTANCE_NUM-1 in UVVM adaptations = " & to_string(C_MAX_VVC_INSTANCE_NUM-1), C_SCOPE, ID_NEVER);
vvc_config.bfm_config := bfm_config;
vvc_config.cmd_queue_count_max := cmd_queue_count_max;
vvc_config.cmd_queue_count_threshold := cmd_queue_count_threshold;
vvc_config.cmd_queue_count_threshold_severity := cmd_queue_count_threshold_severity;
vvc_config.result_queue_count_max := result_queue_count_max;
vvc_config.result_queue_count_threshold := result_queue_count_threshold;
vvc_config.result_queue_count_threshold_severity := result_queue_count_threshold_severity;
-- compose log message based on the number of channels in scope string
if pos_of_leftmost(',', scope, 1) = pos_of_rightmost(',', scope, 1) then
log(ID_CONSTRUCTOR, "VVC instantiated.", scope, vvc_config.msg_id_panel);
else
for idx in scope'range loop
if (scope(idx) = ',') and (v_comma_number < 2) then -- locate 2nd comma in string
v_comma_number := v_comma_number + 1;
end if;
if v_comma_number = 2 then -- rest of string is channel name
log(ID_CONSTRUCTOR, "VVC instantiated for channel " & scope((idx+1) to scope'length) , scope, vvc_config.msg_id_panel);
exit;
end if;
end loop;
end if;
command_queue.set_scope(scope);
command_queue.set_name("cmd_queue");
command_queue.set_queue_count_max(cmd_queue_count_max);
command_queue.set_queue_count_threshold(cmd_queue_count_threshold);
command_queue.set_queue_count_threshold_severity(cmd_queue_count_threshold_severity);
log(ID_CONSTRUCTOR_SUB, "Command queue instantiated and will give a warning when reaching " & to_string(command_queue.get_queue_count_max(VOID))
& " elements in queue.", scope, vvc_config.msg_id_panel);
result_queue.set_scope(scope);
result_queue.set_name("result_queue");
result_queue.set_queue_count_max(result_queue_count_max);
result_queue.set_queue_count_threshold(result_queue_count_threshold);
result_queue.set_queue_count_threshold_severity(result_queue_count_threshold_severity);
log(ID_CONSTRUCTOR_SUB, "Result queue instantiated and will give a warning when reaching " & to_string(result_queue.get_queue_count_max(VOID))
& " elements in queue.", scope, vvc_config.msg_id_panel);
if shared_uvvm_state /= PHASE_A then
loop
wait for 0 ns;
v_delta_cycle_counter := v_delta_cycle_counter + 1;
exit when shared_uvvm_state = PHASE_A;
if shared_uvvm_state /= IDLE then
alert(TB_FAILURE, "UVVM will not work without entity ti_uvvm_engine instantiated in the testbench or test harness.");
end if;
end loop;
end if;
wait; -- show message only once per VVC instance
end procedure;
procedure initialize_interpreter (
signal terminate_current_cmd : out t_flag_record;
signal global_awaiting_completion : out std_logic_vector(C_MAX_NUM_SEQUENCERS-1 downto 0)
) is
begin
terminate_current_cmd <= (set => '0', reset => 'Z', is_active => 'Z'); -- Initialise to avoid undefineds. This process is driving param 1 only.
wait for 0 ns; -- delay by 1 delta cycle to allow constructor to finish first
global_awaiting_completion <= (others => 'Z'); -- Avoid driving until the VVC is involved in await_any_completion()
end procedure;
function broadcast_cmd_to_shared_cmd (
constant broadcast_cmd : t_broadcastable_cmd
) return t_operation is
begin
case broadcast_cmd is
when AWAIT_COMPLETION => return AWAIT_COMPLETION;
when ENABLE_LOG_MSG => return ENABLE_LOG_MSG;
when DISABLE_LOG_MSG => return DISABLE_LOG_MSG;
when FLUSH_COMMAND_QUEUE => return FLUSH_COMMAND_QUEUE;
when INSERT_DELAY => return INSERT_DELAY;
when TERMINATE_CURRENT_COMMAND => return TERMINATE_CURRENT_COMMAND;
when others => return NO_OPERATION;
end case;
end function;
function get_command_type_from_operation (
constant broadcast_cmd : t_broadcastable_cmd
) return t_immediate_or_queued is
begin
case broadcast_cmd is
when AWAIT_COMPLETION => return IMMEDIATE;
when ENABLE_LOG_MSG => return IMMEDIATE;
when DISABLE_LOG_MSG => return IMMEDIATE;
when FLUSH_COMMAND_QUEUE => return IMMEDIATE;
when TERMINATE_CURRENT_COMMAND => return IMMEDIATE;
when INSERT_DELAY => return QUEUED;
when others => return NO_command_type;
end case;
end function;
procedure populate_shared_vvc_cmd_with_broadcast (
variable output_vvc_cmd : out t_vvc_cmd_record;
constant scope : in string := C_SCOPE
) is
begin
-- Increment the shared command index. This is normally done in the CDM, but for broadcast commands it is done by the VVC itself.
check_value((shared_uvvm_state /= IDLE), TB_FAILURE, "UVVM will not work without uvvm_vvc_framework.ti_uvvm_engine instantiated in the test harness", C_SCOPE, ID_NEVER);
await_semaphore_in_delta_cycles(protected_broadcast_semaphore);
-- Populate the shared VVC command record
output_vvc_cmd.operation := broadcast_cmd_to_shared_cmd(shared_vvc_broadcast_cmd.operation);
output_vvc_cmd.msg_id := shared_vvc_broadcast_cmd.msg_id;
output_vvc_cmd.msg := shared_vvc_broadcast_cmd.msg;
output_vvc_cmd.quietness := shared_vvc_broadcast_cmd.quietness;
output_vvc_cmd.delay := shared_vvc_broadcast_cmd.delay;
output_vvc_cmd.timeout := shared_vvc_broadcast_cmd.timeout;
output_vvc_cmd.gen_integer_array(0) := shared_vvc_broadcast_cmd.gen_integer;
output_vvc_cmd.proc_call := shared_vvc_broadcast_cmd.proc_call;
output_vvc_cmd.cmd_idx := shared_cmd_idx;
output_vvc_cmd.command_type := get_command_type_from_operation(shared_vvc_broadcast_cmd.operation);
if global_show_msg_for_uvvm_cmd then
log(ID_UVVM_SEND_CMD, to_string(shared_vvc_broadcast_cmd.proc_call) & ": " & add_msg_delimiter(to_string(shared_vvc_broadcast_cmd.msg))
& format_command_idx(shared_cmd_idx), scope);
else
log(ID_UVVM_SEND_CMD, to_string(shared_vvc_broadcast_cmd.proc_call)
& format_command_idx(shared_cmd_idx), scope);
end if;
release_semaphore(protected_broadcast_semaphore);
end procedure;
function get_msg_id_panel(
constant command : in t_vvc_cmd_record;
constant vvc_config : in t_vvc_config
) return t_msg_id_panel is
begin
-- If the parent_msg_id_panel is set then use it,
-- otherwise use the VVCs msg_id_panel from its config.
--if command.parent_msg_id_panel /= C_UNUSED_MSG_ID_PANEL then
-- return command.parent_msg_id_panel;
--else
-- return vvc_config.msg_id_panel;
--end if;
return vvc_config.msg_id_panel; --UVVM: temporary fix for HVVC, replace for commented code above in v3.0
end function;
procedure await_cmd_from_sequencer(
constant vvc_labels : in t_vvc_labels;
constant vvc_config : in t_vvc_config;
signal VVCT : in t_vvc_target_record;
signal VVC_BROADCAST : inout std_logic;
signal global_vvc_busy : inout std_logic;
signal vvc_ack : out std_logic;
variable output_vvc_cmd : out t_vvc_cmd_record;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel --UVVM: unused, remove in v3.0
) is
variable v_was_broadcast : boolean := false;
variable v_msg_id_panel : t_msg_id_panel;
variable v_vvc_idx_in_activity_register : t_integer_array(0 to C_MAX_TB_VVC_NUM) := (others => -1);
variable v_num_vvc_instances : natural range 0 to C_MAX_TB_VVC_NUM := 0;
variable v_vvc_instance_idx : integer := vvc_labels.instance_idx;
variable v_vvc_channel : t_channel := vvc_labels.channel;
begin
vvc_ack <= 'Z'; -- Do not contribute to the acknowledge unless selected
-- Wait for a new command
log(ID_CMD_INTERPRETER_WAIT, "Interpreter: Waiting for command", to_string(vvc_labels.scope), vvc_config.msg_id_panel);
loop
VVC_BROADCAST <= 'Z';
global_vvc_busy <= 'L';
wait until (VVCT.trigger = '1' or VVC_BROADCAST = '1');
if VVC_BROADCAST'event and VVC_BROADCAST = '1' then
v_was_broadcast := true;
VVC_BROADCAST <= '1';
populate_shared_vvc_cmd_with_broadcast(output_vvc_cmd, vvc_labels.scope);
else
-- set VVC_BROADCAST to 0 to force a broadcast to wait for that VVC
VVC_BROADCAST <= '0';
global_vvc_busy <= '1';
-- copy shared_vvc_cmd to release the semaphore
output_vvc_cmd := shared_vvc_cmd;
end if;
-- Check that the channel is valid
if (not v_was_broadcast) then
if (VVCT.vvc_instance_idx = vvc_labels.instance_idx and
VVCT.vvc_name(1 to valid_length(vvc_labels.vvc_name)) = vvc_labels.vvc_name(1 to valid_length(vvc_labels.vvc_name))) then
if ((VVCT.vvc_channel = NA and vvc_labels.channel /= NA) or
(vvc_labels.channel = NA and (VVCT.vvc_channel /= NA and VVCT.vvc_channel /= ALL_CHANNELS))) then
tb_warning(to_string(output_vvc_cmd.proc_call) & " Channel "& to_string(VVCT.vvc_channel) & " not supported on this VVC " & format_command_idx(output_vvc_cmd), to_string(vvc_labels.scope));
-- only release semaphore and stay in loop forcing a timeout too
release_semaphore(protected_semaphore);
end if;
end if;
end if;
exit when (v_was_broadcast or -- Broadcast, or
(((VVCT.vvc_instance_idx = vvc_labels.instance_idx) or (VVCT.vvc_instance_idx = ALL_INSTANCES)) and -- Index is correct or broadcast index
((VVCT.vvc_channel = ALL_CHANNELS) or (VVCT.vvc_channel = vvc_labels.channel)) and -- Channel is correct or broadcast channel
VVCT.vvc_name(1 to valid_length(vvc_labels.vvc_name)) = vvc_labels.vvc_name(1 to valid_length(vvc_labels.vvc_name)))); -- Name is correct
end loop;
if ((VVCT.vvc_instance_idx = ALL_INSTANCES) or (VVCT.vvc_channel = ALL_CHANNELS) ) then
-- in case of a multicast block the global acknowledge until all vvc receiving the message processed it
vvc_ack <= '0';
end if;
wait for 0 ns;
if v_vvc_instance_idx = -1 then
v_vvc_instance_idx := ALL_INSTANCES;
end if;
if v_vvc_channel = NA then
v_vvc_channel := ALL_CHANNELS;
end if;
-- Get the corresponding index from the vvc activity register
get_vvc_index_in_activity_register(VVCT,
v_vvc_instance_idx,
v_vvc_channel,
v_vvc_idx_in_activity_register,
v_num_vvc_instances);
if not v_was_broadcast then
-- VVCs registered in the VVC activity register have released the
-- semaphore in send_command_to_vvc().
if v_num_vvc_instances = 0 then
-- release the semaphore if it was not a broadcast
release_semaphore(protected_semaphore);
end if;
end if;
v_msg_id_panel := get_msg_id_panel(output_vvc_cmd, vvc_config);
log(ID_CMD_INTERPRETER, to_string(output_vvc_cmd.proc_call) & ". Command received " & format_command_idx(output_vvc_cmd), vvc_labels.scope, v_msg_id_panel); -- Get and ack the new command
end procedure await_cmd_from_sequencer;
-- Overloading procedure - DEPRECATED
procedure await_cmd_from_sequencer(
constant vvc_labels : in t_vvc_labels;
constant vvc_config : in t_vvc_config;
signal VVCT : in t_vvc_target_record;
signal VVC_BROADCAST : inout std_logic;
signal global_vvc_busy : inout std_logic;
signal vvc_ack : out std_logic;
constant shared_vvc_cmd : in t_vvc_cmd_record;
variable output_vvc_cmd : out t_vvc_cmd_record
) is
begin
deprecate(get_procedure_name_from_instance_name(vvc_labels'instance_name), "shared_vvc_cmd parameter is no longer in use. Please call this procedure without the shared_vvc_cmd parameter.");
await_cmd_from_sequencer(vvc_labels, vvc_config, VVCT, VVC_BROADCAST,
global_vvc_busy, vvc_ack, output_vvc_cmd);
end procedure;
procedure put_command_on_queue(
constant command : in t_vvc_cmd_record;
variable command_queue : inout work.td_cmd_queue_pkg.t_generic_queue;
variable vvc_status : inout t_vvc_status;
signal queue_is_increasing : out boolean
) is
begin
command_queue.put(command);
vvc_status.pending_cmd_cnt := command_queue.get_count(VOID);
queue_is_increasing <= true;
wait for 0 ns;
queue_is_increasing <= false;
end procedure;
procedure interpreter_await_completion(
constant command : in t_vvc_cmd_record;
variable command_queue : inout work.td_cmd_queue_pkg.t_generic_queue;
constant vvc_config : in t_vvc_config;
signal executor_is_busy : in boolean;
constant vvc_labels : in t_vvc_labels;
signal last_cmd_idx_executed : in natural;
constant await_completion_pending_msg_id : in t_msg_id := ID_IMMEDIATE_CMD_WAIT;
constant await_completion_finished_msg_id : in t_msg_id := ID_IMMEDIATE_CMD
) is
alias wanted_idx : integer is command.gen_integer_array(0); -- generic integer used as wanted command idx to wait for
constant C_MSG_ID_PANEL : t_msg_id_panel := get_msg_id_panel(command, vvc_config);
begin
if wanted_idx = -1 then
-- await completion of all commands
if not command_queue.is_empty(VOID) or executor_is_busy then
log(await_completion_pending_msg_id, "await_completion() - Pending completion " & to_string(command.msg) & " " & format_command_idx(command), to_string(vvc_labels.scope), C_MSG_ID_PANEL); -- Get and ack the new command
loop
if command.timeout = 0 ns then
wait until executor_is_busy = false;
else
wait until (executor_is_busy = false) for command.timeout;
end if;
if command_queue.is_empty(VOID) or not executor_is_busy'event then
exit;
end if;
end loop;
end if;
log(await_completion_finished_msg_id, "await_completion() => Finished. " & to_string(command.msg) & " " & format_command_idx(command), to_string(vvc_labels.scope), C_MSG_ID_PANEL); -- Get and ack the new command
else -- await specific instruction
if last_cmd_idx_executed < wanted_idx then
log(await_completion_pending_msg_id, "await_completion(" & to_string(wanted_idx) & ") - Pending selected " & to_string(command.msg) & " " & format_command_idx(command), to_string(vvc_labels.scope), C_MSG_ID_PANEL); -- Get and ack the new command
loop
if command.timeout = 0 ns then
wait until executor_is_busy = false;
else
wait until executor_is_busy = false for command.timeout;
end if;
if last_cmd_idx_executed >= wanted_idx or not executor_is_busy'event then
exit;
end if;
end loop;
end if;
log(await_completion_finished_msg_id, "await_completion(" & to_string(wanted_idx) & ") => Finished. " & to_string(command.msg) & " " & format_command_idx(command), to_string(vvc_labels.scope), C_MSG_ID_PANEL); -- Get & ack the new command
end if;
end procedure;
------------------------------------------------------------------------------------------
-- Wait for any of the following :
-- await_completion of this VVC, or
-- until global_awaiting_completion /= '1' (any of the other involved VVCs completed).
------------------------------------------------------------------------------------------
procedure interpreter_await_any_completion(
constant command : in t_vvc_cmd_record;
variable command_queue : inout work.td_cmd_queue_pkg.t_generic_queue;
constant vvc_config : in t_vvc_config;
signal executor_is_busy : in boolean;
constant vvc_labels : in t_vvc_labels;
signal last_cmd_idx_executed : in natural;
signal global_awaiting_completion : inout std_logic_vector; -- Handshake from other VVCs performing await_any_completion
constant await_completion_pending_msg_id : in t_msg_id := ID_IMMEDIATE_CMD_WAIT;
constant await_completion_finished_msg_id : in t_msg_id := ID_IMMEDIATE_CMD
) is
alias wanted_idx : integer is command.gen_integer_array(0); -- generic integer used as wanted command idx to wait for
alias awaiting_completion_idx : integer is command.gen_integer_array(1); -- generic integer used as awaiting_completion_idx
constant C_MSG_ID_PANEL : t_msg_id_panel := get_msg_id_panel(command, vvc_config);
variable v_done : boolean := false; -- Whether we're done waiting
-----------------------------------------------
-- Local function
-- Return whether if this VVC has completed
-----------------------------------------------
impure function this_vvc_completed (
dummy : t_void
) return boolean is
begin
if wanted_idx = -1 then
-- All commands must be completed (i.e. not just a selected command index)
return (executor_is_busy = false and command_queue.is_empty(VOID));
else
-- await a SPECIFIC command in this VVC
return (last_cmd_idx_executed >= wanted_idx);
end if;
end;
begin
--
-- Signal that this VVC is participating in the await_any_completion group by driving global_awaiting_completion
--
if not command.gen_boolean then -- NOT_LAST
-- If this is a NOT_LAST call: Wait for delta cycles until the LAST call sets it to '1',
-- then set it to '1' here.
-- Purpose of waiting : synchronize the LAST VVC with all the NOT_LAST VVCs, so that it doesn't have to wait a magic number of delta cycles
while global_awaiting_completion(awaiting_completion_idx) = 'Z' loop
wait for 0 ns;
end loop;
global_awaiting_completion(awaiting_completion_idx) <= '1';
else
-- If this is a LAST call: Set to '1' for at least one delta cycle, so that all NOT_LAST calls detects it.
global_awaiting_completion(awaiting_completion_idx) <= '1';
wait for 0 ns;
end if;
-- This VVC already completed?
if this_vvc_completed(VOID) then
v_done := true;
end if;
-- Any of the other involved VVCs already completed?
if (global_awaiting_completion(awaiting_completion_idx) = 'X' or global_awaiting_completion(awaiting_completion_idx) = '0') then
v_done := true;
end if;
if not v_done then
-- Start waiting for the first of this VVC or other VVC
log(await_completion_pending_msg_id, to_string(command.proc_call) & " - Pending completion " & to_string(command.msg) & " " & format_command_idx(command), to_string(vvc_labels.scope), C_MSG_ID_PANEL);
loop
wait until ((executor_is_busy = false) or (global_awaiting_completion(awaiting_completion_idx) /= '1')) for command.timeout;
if this_vvc_completed(VOID) then -- This VVC is done
log(await_completion_finished_msg_id, "This VVC initiated completion of " & to_string(command.proc_call), to_string(vvc_labels.scope), C_MSG_ID_PANEL);
-- update shared_uvvm_status with the VVC name and cmd index that initiated the completion
shared_uvvm_status.info_on_finishing_await_any_completion.vvc_name(1 to vvc_labels.vvc_name'length) := vvc_labels.vvc_name;
shared_uvvm_status.info_on_finishing_await_any_completion.vvc_cmd_idx := last_cmd_idx_executed;
shared_uvvm_status.info_on_finishing_await_any_completion.vvc_time_of_completion := now;
exit;
end if;
if global_awaiting_completion(awaiting_completion_idx) = '0' or -- All other involved VVCs are done
global_awaiting_completion(awaiting_completion_idx) = 'X' then -- Some other involved VVCs are done
exit;
end if;
if not ((executor_is_busy'event) or (global_awaiting_completion(awaiting_completion_idx) /= '1')) then -- Indicates timeout
-- When NOT_LAST (command.gen_boolean = false): Timeout must be reported here instead of in send_command_to_vvc()
-- becuase the command is always acknowledged immediately by the VVC to allow the sequencer to continue
if not command.gen_boolean then
tb_error("Timeout during " & to_string(command.proc_call) & "=> " & format_msg(command), to_string(vvc_labels.scope));
end if;
exit;
end if;
end loop;
end if;
global_awaiting_completion(awaiting_completion_idx) <= '0'; -- Signal that we're done waiting
-- Handshake : Wait until every involved VVC notice the value is 'X' or '0', and all agree to being done ('0')
if global_awaiting_completion(awaiting_completion_idx) /= '0' then
wait until (global_awaiting_completion(awaiting_completion_idx) = '0');
end if;
global_awaiting_completion(awaiting_completion_idx) <= 'Z'; -- Idle
log(await_completion_finished_msg_id, to_string(command.proc_call) & "=> Finished. " & format_msg(command), to_string(vvc_labels.scope), C_MSG_ID_PANEL); -- Get & ack the new command
end procedure;
procedure interpreter_flush_command_queue(
constant command : in t_vvc_cmd_record;
variable command_queue : inout work.td_cmd_queue_pkg.t_generic_queue;
constant vvc_config : in t_vvc_config;
variable vvc_status : inout t_vvc_status;
constant vvc_labels : in t_vvc_labels
) is
constant C_MSG_ID_PANEL : t_msg_id_panel := get_msg_id_panel(command, vvc_config);
begin
log(ID_IMMEDIATE_CMD, "Flushing command queue (" & to_string(shared_vvc_cmd.gen_integer_array(0)) & ") " & format_command_idx(shared_vvc_cmd), to_string(vvc_labels.scope), C_MSG_ID_PANEL);
command_queue.flush(VOID);
vvc_status.pending_cmd_cnt := command_queue.get_count(VOID);
end;
procedure interpreter_terminate_current_command(
constant command : in t_vvc_cmd_record;
constant vvc_config : in t_vvc_config;
constant vvc_labels : in t_vvc_labels;
signal terminate_current_cmd : inout t_flag_record;
constant executor_is_busy : in boolean := true
) is
constant C_MSG_ID_PANEL : t_msg_id_panel := get_msg_id_panel(command, vvc_config);
begin
if executor_is_busy then
log(ID_IMMEDIATE_CMD, "Terminating command in executor", to_string(vvc_labels.scope), C_MSG_ID_PANEL);
set_flag(terminate_current_cmd);
end if;
end procedure;
procedure interpreter_fetch_result(
variable result_queue : inout work.td_result_queue_pkg.t_generic_queue;
constant command : in t_vvc_cmd_record;
constant vvc_config : in t_vvc_config;
constant vvc_labels : in t_vvc_labels;
constant last_cmd_idx_executed : in natural;
variable shared_vvc_response : inout work.vvc_cmd_pkg.t_vvc_response
) is
constant C_MSG_ID_PANEL : t_msg_id_panel := get_msg_id_panel(command, vvc_config);
variable v_current_element : work.vvc_cmd_pkg.t_vvc_result_queue_element;
variable v_local_result_queue : work.td_result_queue_pkg.t_generic_queue;
begin
v_local_result_queue.set_scope(to_string(vvc_labels.scope));
shared_vvc_response.fetch_is_accepted := false; -- default
if last_cmd_idx_executed < command.gen_integer_array(0) then
tb_warning(to_string(command.proc_call) & ". Requested result is not yet available. " & format_command_idx(command), to_string(vvc_labels.scope));
else
-- Search for the command idx among the elements of the queue.
-- Easiest method of doing this is to pop elements, and pushing them again
-- if the cmd idx does not match. Not very efficient, but an OK initial implementation.
-- Pop the element. Compare cmd idx. If it does not match, push to local result queue.
-- If an index matches, set shared_vvc_response.result. (Don't push element back to result queue)
while result_queue.get_count(VOID) > 0 loop
v_current_element := result_queue.get(VOID);
if v_current_element.cmd_idx = command.gen_integer_array(0) then
shared_vvc_response.fetch_is_accepted := true;
shared_vvc_response.result := v_current_element.result;
log(ID_IMMEDIATE_CMD, to_string(command.proc_call) & " Requested result is found" & ". " & to_string(command.msg) & " " & format_command_idx(command), to_string(vvc_labels.scope), C_MSG_ID_PANEL); -- Get and ack the new command
exit;
else
-- No match for element: put in local result queue
v_local_result_queue.put(v_current_element);
end if;
end loop;
-- Pop each element of local result queue and push to result queue.
-- This is to clear the local result queue and restore the result
-- queue to its original state (except that the matched element is not put back).
while v_local_result_queue.get_count(VOID) > 0 loop
result_queue.put(v_local_result_queue.get(VOID));
end loop;
if not shared_vvc_response.fetch_is_accepted then
tb_warning(to_string(command.proc_call) & ". Requested result was not found. Given command index is not available in this VVC. " & format_command_idx(command), to_string(vvc_labels.scope));
end if;
end if;
end procedure;
procedure initialize_executor (
signal terminate_current_cmd : inout t_flag_record
) is
begin
reset_flag(terminate_current_cmd);
wait for 0 ns; -- delay by 1 delta cycle to allow constructor to finish first
end procedure;
procedure fetch_command_and_prepare_executor(
variable command : inout t_vvc_cmd_record;
variable command_queue : inout work.td_cmd_queue_pkg.t_generic_queue;
constant vvc_config : in t_vvc_config;
variable vvc_status : inout t_vvc_status;
signal queue_is_increasing : in boolean;
signal executor_is_busy : inout boolean;
constant vvc_labels : in t_vvc_labels;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel; --UVVM: unused, remove in v3.0
constant executor_id : in t_msg_id := ID_CMD_EXECUTOR;
constant executor_wait_id : in t_msg_id := ID_CMD_EXECUTOR_WAIT
) is
variable v_msg_id_panel : t_msg_id_panel;
begin
executor_is_busy <= false;
vvc_status.previous_cmd_idx := command.cmd_idx;
vvc_status.current_cmd_idx := 0;
wait for 0 ns; -- to allow delta updates in other processes.
if command_queue.is_empty(VOID) then
log(executor_wait_id, "Executor: Waiting for command", to_string(vvc_labels.scope), vvc_config.msg_id_panel);
wait until queue_is_increasing;
end if;
-- Queue is now not empty
executor_is_busy <= true;
wait until executor_is_busy;
command := command_queue.get(VOID);
v_msg_id_panel := get_msg_id_panel(command, vvc_config);
log(executor_id, to_string(command.proc_call) & " - Will be executed " & format_command_idx(command), to_string(vvc_labels.scope), v_msg_id_panel); -- Get and ack the new command
vvc_status.pending_cmd_cnt := command_queue.get_count(VOID);
vvc_status.current_cmd_idx := command.cmd_idx;
end procedure;
-- The result_queue is used so that whatever type defined in the VVC can be stored,
-- and later fetched with fetch_result()
procedure store_result(
variable result_queue : inout work.td_result_queue_pkg.t_generic_queue;
constant cmd_idx : in natural;
constant result : in t_vvc_result
) is
variable v_result_queue_element : t_vvc_result_queue_element;
begin
v_result_queue_element.cmd_idx := cmd_idx;
v_result_queue_element.result := result;
result_queue.put(v_result_queue_element);
end procedure;
procedure insert_inter_bfm_delay_if_requested(
constant vvc_config : in t_vvc_config;
constant command_is_bfm_access : in boolean;
constant timestamp_start_of_last_bfm_access : in time;
constant timestamp_end_of_last_bfm_access : in time;
constant msg_id_panel : in t_msg_id_panel;
constant scope : in string := C_SCOPE
) is
begin
-- If both timestamps are at 0 ns we interpret this as the first BFM access, hence no delay shall be applied.
if ((vvc_config.inter_bfm_delay.delay_type /= NO_DELAY) and
command_is_bfm_access and
not ((timestamp_start_of_last_bfm_access = 0 ns) and (timestamp_end_of_last_bfm_access = 0 ns))) then
case vvc_config.inter_bfm_delay.delay_type is
when TIME_FINISH2START =>
if now < (timestamp_end_of_last_bfm_access + vvc_config.inter_bfm_delay.delay_in_time) then
log(ID_INSERTED_DELAY, "Delaying BFM access until time " & to_string(timestamp_end_of_last_bfm_access + vvc_config.inter_bfm_delay.delay_in_time)
& ".", scope, msg_id_panel);
wait for (timestamp_end_of_last_bfm_access + vvc_config.inter_bfm_delay.delay_in_time - now);
end if;
when TIME_START2START =>
if now < (timestamp_start_of_last_bfm_access + vvc_config.inter_bfm_delay.delay_in_time) then
log(ID_INSERTED_DELAY, "Delaying BFM access until time " & to_string(timestamp_start_of_last_bfm_access + vvc_config.inter_bfm_delay.delay_in_time)
& ".", scope, msg_id_panel);
wait for (timestamp_start_of_last_bfm_access + vvc_config.inter_bfm_delay.delay_in_time - now);
end if;
when others =>
tb_error("Delay type " & to_upper(to_string(vvc_config.inter_bfm_delay.delay_type)) & " not supported for this VVC.", scope);
end case;
log(ID_INSERTED_DELAY, "Finished delaying BFM access", scope, msg_id_panel);
end if;
end procedure;
procedure insert_inter_bfm_delay_if_requested(
constant vvc_config : in t_vvc_config;
constant command_is_bfm_access : in boolean;
constant timestamp_start_of_last_bfm_access : in time;
constant timestamp_end_of_last_bfm_access : in time;
constant scope : in string := C_SCOPE
) is
begin
insert_inter_bfm_delay_if_requested(vvc_config, command_is_bfm_access, timestamp_start_of_last_bfm_access,
timestamp_end_of_last_bfm_access, vvc_config.msg_id_panel, scope);
end procedure;
end package body td_vvc_entity_support_pkg;
|
mit
|
YingcaiDong/Shunting-Model-Based-Path-Planning-Algorithm-Accelerator-Using-FPGA
|
System Design Source FIle/ipshared/xilinx.com/axi_sg_v4_1/0535f152/hdl/src/vhdl/axi_sg_cntrl_strm.vhd
|
4
|
25017
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_cntrl_strm.vhd
-- Description: This entity is MM2S control stream logic
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_sg_v4_1;
use axi_sg_v4_1.axi_sg_pkg.all;
library lib_fifo_v1_0;
library lib_cdc_v1_0;
library lib_pkg_v1_0;
use lib_pkg_v1_0.lib_pkg.clog2;
use lib_pkg_v1_0.lib_pkg.max2;
-------------------------------------------------------------------------------
entity axi_sg_cntrl_strm is
generic(
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Primary data path channels (MM2S and S2MM)
-- run asynchronous to AXI Lite, DMA Control,
-- and SG.
C_PRMY_CMDFIFO_DEPTH : integer range 1 to 16 := 1;
-- Depth of DataMover command FIFO
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Control Stream Data Width
C_FAMILY : string := "virtex7"
-- Target FPGA Device Family
);
port (
-- Secondary clock / reset
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Primary clock / reset --
axi_prmry_aclk : in std_logic ; --
p_reset_n : in std_logic ; --
--
-- MM2S Error --
mm2s_stop : in std_logic ; --
--
-- Control Stream FIFO write signals (from axi_dma_mm2s_sg_if) --
cntrlstrm_fifo_wren : in std_logic ; --
cntrlstrm_fifo_din : in std_logic_vector --
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH downto 0); --
cntrlstrm_fifo_full : out std_logic ; --
--
--
-- Memory Map to Stream Control Stream Interface --
m_axis_mm2s_cntrl_tdata : out std_logic_vector --
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0); --
m_axis_mm2s_cntrl_tkeep : out std_logic_vector --
((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0);--
m_axis_mm2s_cntrl_tvalid : out std_logic ; --
m_axis_mm2s_cntrl_tready : in std_logic ; --
m_axis_mm2s_cntrl_tlast : out std_logic --
);
end axi_sg_cntrl_strm;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_cntrl_strm is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Number of words deep fifo needs to be
-- Only 5 app fields, but set to 8 so depth is a power of 2
constant CNTRL_FIFO_DEPTH : integer := max2(16,8 * C_PRMY_CMDFIFO_DEPTH);
-- Width of fifo rd and wr counts - only used for proper fifo operation
constant CNTRL_FIFO_CNT_WIDTH : integer := clog2(CNTRL_FIFO_DEPTH+1);
constant USE_LOGIC_FIFOS : integer := 0; -- Use Logic FIFOs
constant USE_BRAM_FIFOS : integer := 1; -- Use BRAM FIFOs
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- FIFO signals
signal cntrl_fifo_rden : std_logic := '0';
signal cntrl_fifo_empty : std_logic := '0';
signal cntrl_fifo_dout, follower_reg_mm2s : std_logic_vector
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH downto 0) := (others => '0');
signal cntrl_fifo_dvalid: std_logic := '0';
signal cntrl_tdata : std_logic_vector
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0) := (others => '0');
signal cntrl_tkeep : std_logic_vector
((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal follower_full_mm2s, follower_empty_mm2s : std_logic := '0';
signal cntrl_tvalid : std_logic := '0';
signal cntrl_tready : std_logic := '0';
signal cntrl_tlast : std_logic := '0';
signal sinit : std_logic := '0';
signal m_valid : std_logic := '0';
signal m_ready : std_logic := '0';
signal m_data : std_logic_vector(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0) := (others => '0');
signal m_strb : std_logic_vector((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal m_last : std_logic := '0';
signal skid_rst : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- All bytes always valid
cntrl_tkeep <= (others => '1');
-- Primary Clock is synchronous to Secondary Clock therfore
-- instantiate a sync fifo.
GEN_SYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
signal mm2s_stop_d1 : std_logic := '0';
signal mm2s_stop_re : std_logic := '0';
signal xfer_in_progress : std_logic := '0';
begin
-- reset on hard reset or mm2s stop
sinit <= not m_axi_sg_aresetn or mm2s_stop;
-- Generate Synchronous FIFO
I_CNTRL_FIFO : entity lib_fifo_v1_0.sync_fifo_fg
generic map (
C_FAMILY => C_FAMILY ,
C_MEMORY_TYPE => USE_LOGIC_FIFOS,
C_WRITE_DATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH + 1,
C_WRITE_DEPTH => CNTRL_FIFO_DEPTH ,
C_READ_DATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH + 1,
C_READ_DEPTH => CNTRL_FIFO_DEPTH ,
C_PORTS_DIFFER => 0,
C_HAS_DCOUNT => 0, --req for proper fifo operation
C_HAS_ALMOST_FULL => 0,
C_HAS_RD_ACK => 0,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_ERR => 0,
C_RD_ACK_LOW => 0,
C_RD_ERR_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_ERR_LOW => 0,
C_PRELOAD_REGS => 1,-- 1 = first word fall through
C_PRELOAD_LATENCY => 0 -- 0 = first word fall through
-- C_USE_EMBEDDED_REG => 1 -- 0 ;
)
port map (
Clk => m_axi_sg_aclk ,
Sinit => sinit ,
Din => cntrlstrm_fifo_din ,
Wr_en => cntrlstrm_fifo_wren ,
Rd_en => cntrl_fifo_rden ,
Dout => cntrl_fifo_dout ,
Full => cntrlstrm_fifo_full ,
Empty => cntrl_fifo_empty ,
Almost_full => open ,
Data_count => open ,
Rd_ack => open ,
Rd_err => open ,
Wr_ack => open ,
Wr_err => open
);
-- I_UPDT_DATA_FIFO : entity proc_common_srl_fifo_v5_0.srl_fifo_f
-- generic map (
-- C_DWIDTH => 33 ,
-- C_DEPTH => 24 ,
-- C_FAMILY => C_FAMILY
-- )
-- port map (
-- Clk => m_axi_sg_aclk ,
-- Reset => sinit ,
-- FIFO_Write => cntrlstrm_fifo_wren ,
-- Data_In => cntrlstrm_fifo_din ,
-- FIFO_Read => cntrl_fifo_rden ,
-- Data_Out => cntrl_fifo_dout ,
-- FIFO_Empty => cntrl_fifo_empty ,
-- FIFO_Full => cntrlstrm_fifo_full,
-- Addr => open
-- );
cntrl_fifo_rden <= follower_empty_mm2s and (not cntrl_fifo_empty);
VALID_REG_MM2S_ACTIVE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or (cntrl_tready = '1' and follower_full_mm2s = '1'))then
-- follower_reg_mm2s <= (others => '0');
follower_full_mm2s <= '0';
follower_empty_mm2s <= '1';
else
if (cntrl_fifo_rden = '1') then
-- follower_reg_mm2s <= sts_queue_dout;
follower_full_mm2s <= '1';
follower_empty_mm2s <= '0';
end if;
end if;
end if;
end process VALID_REG_MM2S_ACTIVE;
VALID_REG_MM2S_ACTIVE1 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
follower_reg_mm2s <= (others => '0');
else
if (cntrl_fifo_rden = '1') then
follower_reg_mm2s <= cntrl_fifo_dout;
end if;
end if;
end if;
end process VALID_REG_MM2S_ACTIVE1;
-----------------------------------------------------------------------
-- Control Stream OUT Side
-----------------------------------------------------------------------
-- Read if fifo is not empty and target is ready
-- cntrl_fifo_rden <= not cntrl_fifo_empty
-- and cntrl_tready;
-- Drive valid if fifo is not empty or in the middle
-- of transfer and stop issued.
cntrl_tvalid <= follower_full_mm2s --not cntrl_fifo_empty
or (xfer_in_progress and mm2s_stop_re);
-- Pass data out to control channel with MSB driving tlast
cntrl_tlast <= (cntrl_tvalid and follower_reg_mm2s(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH))
or (xfer_in_progress and mm2s_stop_re);
cntrl_tdata <= follower_reg_mm2s(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0);
-- Register stop to create re pulse for cleaning shutting down
-- stream out during soft reset.
REG_STOP : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_stop_d1 <= '0';
else
mm2s_stop_d1 <= mm2s_stop;
end if;
end if;
end process REG_STOP;
mm2s_stop_re <= mm2s_stop and not mm2s_stop_d1;
-------------------------------------------------------------
-- Flag transfer in progress. If xfer in progress then
-- a fake tlast and tvalid need to be asserted during soft
-- reset else no need of tlast.
-------------------------------------------------------------
TRANSFER_IN_PROGRESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(cntrl_tlast = '1' and cntrl_tvalid = '1' and cntrl_tready = '1')then
xfer_in_progress <= '0';
elsif(xfer_in_progress = '0' and cntrl_tvalid = '1')then
xfer_in_progress <= '1';
end if;
end if;
end process TRANSFER_IN_PROGRESS;
skid_rst <= not m_axi_sg_aresetn;
---------------------------------------------------------------------------
-- Buffer AXI Signals
---------------------------------------------------------------------------
-- CNTRL_SKID_BUF_I : entity axi_sg_v4_1.axi_sg_skid_buf
-- generic map(
-- C_WDATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH
-- )
-- port map(
-- -- System Ports
-- ACLK => m_axi_sg_aclk ,
-- ARST => skid_rst ,
-- skid_stop => mm2s_stop_re ,
-- -- Slave Side (Stream Data Input)
-- S_VALID => cntrl_tvalid ,
-- S_READY => cntrl_tready ,
-- S_Data => cntrl_tdata ,
-- S_STRB => cntrl_tkeep ,
-- S_Last => cntrl_tlast ,
-- -- Master Side (Stream Data Output
-- M_VALID => m_axis_mm2s_cntrl_tvalid ,
-- M_READY => m_axis_mm2s_cntrl_tready ,
-- M_Data => m_axis_mm2s_cntrl_tdata ,
-- M_STRB => m_axis_mm2s_cntrl_tkeep ,
-- M_Last => m_axis_mm2s_cntrl_tlast
-- );
m_axis_mm2s_cntrl_tvalid <= cntrl_tvalid;
cntrl_tready <= m_axis_mm2s_cntrl_tready;
m_axis_mm2s_cntrl_tdata <= cntrl_tdata;
m_axis_mm2s_cntrl_tkeep <= cntrl_tkeep;
m_axis_mm2s_cntrl_tlast <= cntrl_tlast;
end generate GEN_SYNC_FIFO;
-- Primary Clock is asynchronous to Secondary Clock therfore
-- instantiate an async fifo.
GEN_ASYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
ATTRIBUTE async_reg : STRING;
signal mm2s_stop_reg : std_logic := '0'; -- CR605883
signal p_mm2s_stop_d1_cdc_tig : std_logic := '0';
signal p_mm2s_stop_d2 : std_logic := '0';
signal p_mm2s_stop_d3 : std_logic := '0';
signal p_mm2s_stop_re : std_logic := '0';
signal xfer_in_progress : std_logic := '0';
-- ATTRIBUTE async_reg OF p_mm2s_stop_d1_cdc_tig : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF p_mm2s_stop_d2 : SIGNAL IS "true";
begin
-- reset on hard reset, soft reset, or mm2s error
sinit <= not p_reset_n or p_mm2s_stop_d2;
-- Generate Asynchronous FIFO
I_CNTRL_STRM_FIFO : entity axi_sg_v4_1.axi_sg_afifo_autord
generic map(
C_DWIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH + 1 ,
-- Temp work around for issue in async fifo model
C_DEPTH => CNTRL_FIFO_DEPTH-1 ,
C_CNT_WIDTH => CNTRL_FIFO_CNT_WIDTH ,
-- C_DEPTH => 31 ,
-- C_CNT_WIDTH => 5 ,
C_USE_BLKMEM => USE_LOGIC_FIFOS ,
C_FAMILY => C_FAMILY
)
port map(
-- Inputs
AFIFO_Ainit => sinit ,
AFIFO_Wr_clk => m_axi_sg_aclk ,
AFIFO_Wr_en => cntrlstrm_fifo_wren ,
AFIFO_Din => cntrlstrm_fifo_din ,
AFIFO_Rd_clk => axi_prmry_aclk ,
AFIFO_Rd_en => cntrl_fifo_rden ,
AFIFO_Clr_Rd_Data_Valid => '0' ,
-- Outputs
AFIFO_DValid => cntrl_fifo_dvalid ,
AFIFO_Dout => cntrl_fifo_dout ,
AFIFO_Full => cntrlstrm_fifo_full ,
AFIFO_Empty => cntrl_fifo_empty ,
AFIFO_Almost_full => open ,
AFIFO_Almost_empty => open ,
AFIFO_Wr_count => open ,
AFIFO_Rd_count => open ,
AFIFO_Corr_Rd_count => open ,
AFIFO_Corr_Rd_count_minus1 => open ,
AFIFO_Rd_ack => open
);
-----------------------------------------------------------------------
-- Control Stream OUT Side
-----------------------------------------------------------------------
-- Read if fifo is not empty and target is ready
cntrl_fifo_rden <= not cntrl_fifo_empty -- fifo has data
and cntrl_tready; -- target ready
-- Drive valid if fifo is not empty or in the middle
-- of transfer and stop issued.
cntrl_tvalid <= cntrl_fifo_dvalid
or (xfer_in_progress and p_mm2s_stop_re);
-- Pass data out to control channel with MSB driving tlast
cntrl_tlast <= cntrl_tvalid and cntrl_fifo_dout(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH);
-- cntrl_tlast <= (cntrl_tvalid and cntrl_fifo_dout(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH))
-- or (xfer_in_progress and p_mm2s_stop_re);
cntrl_tdata <= cntrl_fifo_dout(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0);
-- CR605883
-- Register stop to provide pure FF output for synchronizer
REG_STOP : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_stop_reg <= '0';
else
mm2s_stop_reg <= mm2s_stop;
end if;
end if;
end process REG_STOP;
-- Double/triple register mm2s error into primary clock domain
-- Triple register to give two versions with min double reg for use
-- in rising edge detection.
IMP_SYNC_FLOP : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => 2
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => mm2s_stop_reg,
prmry_vect_in => (others => '0'),
scndry_aclk => axi_prmry_aclk,
scndry_resetn => '0',
scndry_out => p_mm2s_stop_d2,
scndry_vect_out => open
);
REG_ERR2PRMRY : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(p_reset_n = '0')then
-- p_mm2s_stop_d1_cdc_tig <= '0';
-- p_mm2s_stop_d2 <= '0';
p_mm2s_stop_d3 <= '0';
else
--p_mm2s_stop_d1_cdc_tig <= mm2s_stop;
-- p_mm2s_stop_d1_cdc_tig <= mm2s_stop_reg;
-- p_mm2s_stop_d2 <= p_mm2s_stop_d1_cdc_tig;
p_mm2s_stop_d3 <= p_mm2s_stop_d2;
end if;
end if;
end process REG_ERR2PRMRY;
-- Rising edge pulse for use in shutting down stream output
p_mm2s_stop_re <= p_mm2s_stop_d2 and not p_mm2s_stop_d3;
-------------------------------------------------------------
-- Flag transfer in progress. If xfer in progress then
-- a fake tlast needs to be asserted during soft reset.
-- else no need of tlast.
-------------------------------------------------------------
TRANSFER_IN_PROGRESS : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(cntrl_tlast = '1' and cntrl_tvalid = '1' and cntrl_tready = '1')then
xfer_in_progress <= '0';
elsif(xfer_in_progress = '0' and cntrl_tvalid = '1')then
xfer_in_progress <= '1';
end if;
end if;
end process TRANSFER_IN_PROGRESS;
skid_rst <= not p_reset_n;
CNTRL_SKID_BUF_I : entity axi_sg_v4_1.axi_sg_skid_buf
generic map(
C_WDATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH
)
port map(
-- System Ports
ACLK => axi_prmry_aclk ,
ARST => skid_rst ,
skid_stop => p_mm2s_stop_re ,
-- Slave Side (Stream Data Input)
S_VALID => cntrl_tvalid ,
S_READY => cntrl_tready ,
S_Data => cntrl_tdata ,
S_STRB => cntrl_tkeep ,
S_Last => cntrl_tlast ,
-- Master Side (Stream Data Output
M_VALID => m_axis_mm2s_cntrl_tvalid ,
M_READY => m_axis_mm2s_cntrl_tready ,
M_Data => m_axis_mm2s_cntrl_tdata ,
M_STRB => m_axis_mm2s_cntrl_tkeep ,
M_Last => m_axis_mm2s_cntrl_tlast
);
end generate GEN_ASYNC_FIFO;
end implementation;
|
mit
|
UVVM/UVVM_All
|
uvvm_vvc_framework/src/ti_data_stack_pkg.vhd
|
1
|
8830
|
--================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
----------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
-- WARNING! This package will be deprecated and no longer receive updates or bug fixes!
-- The data_stack_pkg in uvvm_util/src/data_stack_pkg.vhd has replaced ti_data_stack_pkg
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_data_queue_pkg.all;
package ti_data_stack_pkg is
shared variable shared_data_stack : t_data_queue;
------------------------------------------
-- uvvm_stack_init
------------------------------------------
-- This function allocates space in the buffer and returns an index that
-- must be used to access the stack.
--
-- - Parameters:
-- - buffer_size_in_bits (natural) - The size of the stack
--
-- - Returns: The index of the initiated stack (natural).
-- Returns 0 on error.
--
impure function uvvm_stack_init(
buffer_size_in_bits : natural
) return natural;
------------------------------------------
-- uvvm_stack_init
------------------------------------------
-- This procedure allocates space in the buffer at the given buffer_idx.
--
-- - Parameters:
-- - buffer_idx - The index of the stack (natural)
-- that shall be initialized.
-- - buffer_size_in_bits (natural) - The size of the stack
--
procedure uvvm_stack_init(
buffer_index : natural;
buffer_size_in_bits : natural
);
------------------------------------------
-- uvvm_stack_push
------------------------------------------
-- This procedure puts data into a stack with index buffer_idx.
-- The size of the data is unconstrained, meaning that
-- it can be any size. Pushing data with a size that is
-- larger than the stack size results in wrapping, i.e.,
-- that when reaching the end the data remaining will over-
-- write the data that was written first.
--
-- - Parameters:
-- - buffer_idx - The index of the stack (natural)
-- that shall be pushed to.
-- - data - The data that shall be pushed (slv)
--
procedure uvvm_stack_push(
buffer_index : natural;
data : std_logic_vector
);
------------------------------------------
-- uvvm_stack_pop
------------------------------------------
-- This function returns the data from the stack
-- and removes the returned data from the stack.
--
-- - Parameters:
-- - buffer_idx - The index of the stack (natural)
-- that shall be read.
-- - entry_size_in_bits - The size of the returned slv (natural)
--
-- - Returns: Data from the stack (slv). The size of the
-- return data is given by the entry_size_in_bits parameter.
-- Attempting to pop from an empty stack is allowed but triggers a
-- TB_WARNING and returns garbage.
-- Attempting to pop a larger value than the stack size is allowed
-- but triggers a TB_WARNING.
--
--
impure function uvvm_stack_pop(
buffer_index : natural;
entry_size_in_bits : natural
) return std_logic_vector;
------------------------------------------
-- uvvm_stack_flush
------------------------------------------
-- This procedure empties the stack given
-- by buffer_idx.
--
-- - Parameters:
-- - buffer_idx - The index of the stack (natural)
-- that shall be flushed.
--
procedure uvvm_stack_flush(
buffer_index : natural
);
------------------------------------------
-- uvvm_stack_peek
------------------------------------------
-- This function returns the data from the stack
-- without removing it.
--
-- - Parameters:
-- - buffer_idx - The index of the stack (natural)
-- that shall be read.
-- - entry_size_in_bits - The size of the returned slv (natural)
--
-- - Returns: Data from the stack. The size of the
-- return data is given by the entry_size_in_bits parameter.
-- Attempting to peek from an empty stack is allowed but triggers a
-- TB_WARNING and returns garbage.
-- Attempting to peek a larger value than the stack size is allowed
-- but triggers a TB_WARNING. Will wrap.
--
--
impure function uvvm_stack_peek(
buffer_index : natural;
entry_size_in_bits : natural
) return std_logic_vector;
------------------------------------------
-- uvvm_stack_get_count
------------------------------------------
-- This function returns a natural indicating the number of elements
-- currently occupying the stack given by buffer_idx.
--
-- - Parameters:
-- - buffer_idx - The index of the stack (natural)
--
-- - Returns: The number of elements occupying the stack (natural).
--
--
impure function uvvm_stack_get_count(
buffer_idx : natural
) return natural;
------------------------------------------
-- uvvm_stack_get_max_count
------------------------------------------
-- This function returns a natural indicating the maximum number
-- of elements that can occupy the stack given by buffer_idx.
--
-- - Parameters:
-- - buffer_idx - The index of the stack (natural)
--
-- - Returns: The maximum number of elements that can be placed
-- in the stack (natural).
--
--
impure function uvvm_stack_get_max_count(
buffer_index : natural
) return natural;
end package ti_data_stack_pkg;
package body ti_data_stack_pkg is
impure function uvvm_stack_init(
buffer_size_in_bits : natural
) return natural is
begin
return shared_data_stack.init_queue(buffer_size_in_bits, "UVVM_STACK");
end function;
procedure uvvm_stack_init(
buffer_index : natural;
buffer_size_in_bits : natural
) is
begin
shared_data_stack.init_queue(buffer_index, buffer_size_in_bits, "UVVM_STACK");
end procedure;
procedure uvvm_stack_push(
buffer_index : natural;
data : std_logic_vector
) is
begin
shared_data_stack.push_back(buffer_index,data);
end procedure;
impure function uvvm_stack_pop(
buffer_index : natural;
entry_size_in_bits : natural
) return std_logic_vector is
begin
return shared_data_stack.pop_back(buffer_index, entry_size_in_bits);
end function;
procedure uvvm_stack_flush(
buffer_index : natural
) is
begin
shared_data_stack.flush(buffer_index);
end procedure;
impure function uvvm_stack_peek(
buffer_index : natural;
entry_size_in_bits : natural
) return std_logic_vector is
begin
return shared_data_stack.peek_back(buffer_index, entry_size_in_bits);
end function;
impure function uvvm_stack_get_count(
buffer_idx : natural
) return natural is
begin
return shared_data_stack.get_count(buffer_idx);
end function;
impure function uvvm_stack_get_max_count(
buffer_index : natural
) return natural is
begin
return shared_data_stack.get_queue_count_max(buffer_index);
end function;
end package body ti_data_stack_pkg;
|
mit
|
YingcaiDong/Shunting-Model-Based-Path-Planning-Algorithm-Accelerator-Using-FPGA
|
System Design Source FIle/ipshared/xilinx.com/lib_fifo_v1_0/ca55fafe/hdl/src/vhdl/async_fifo_fg.vhd
|
11
|
123226
|
-- async_fifo_fg.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008, 2009, 2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: async_fifo_fg.vhd
--
-- Description:
-- This HDL file adapts the legacy CoreGen Async FIFO interface to the new
-- FIFO Generator async FIFO interface. This wrapper facilitates the "on
-- the fly" call of FIFO Generator during design implementation.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- async_fifo_fg.vhd
-- |
-- |-- fifo_generator_v4_3
-- |
-- |-- fifo_generator_v9_3
--
-------------------------------------------------------------------------------
-- Revision History:
--
--
-- Author: DET
-- Revision: $Revision: 1.5.2.68 $
-- Date: $1/15/2008$
--
-- History:
-- DET 1/15/2008 Initial Version
--
-- DET 7/30/2008 for EDK 11.1
-- ~~~~~~
-- - Added parameter C_ALLOW_2N_DEPTH to enable use of FIFO Generator
-- feature of specifing 2**N depth of FIFO, Legacy CoreGen Async FIFOs
-- only allowed (2**N)-1 depth specification. Parameter is defalted to
-- the legacy CoreGen method so current users are not impacted.
-- - Incorporated calculation and assignment corrections for the Read and
-- Write Pointer Widths.
-- - Upgraded to FIFO Generator Version 4.3.
-- - Corrected a swap of the Rd_Err and the Wr_Err connections on the FIFO
-- Generator instance.
-- ^^^^^^
--
-- MSH and DET 3/2/2009 For Lava SP2
-- ~~~~~~
-- - Added FIFO Generator version 5.1 for use with Virtex6 and Spartan6
-- devices.
-- - IfGen used so that legacy FPGA families still use Fifo Generator
-- version 4.3.
-- ^^^^^^
--
-- DET 2/9/2010 for EDK 12.1
-- ~~~~~~
-- - Updated the S6/V6 FIFO Generator version from V5.2 to V5.3.
-- ^^^^^^
--
-- DET 3/10/2010 For EDK 12.x
-- ~~~~~~
-- -- Per CR553307
-- - Updated the S6/V6 FIFO Generator version from V5.3 to 6_1.
-- ^^^^^^
--
-- DET 6/18/2010 EDK_MS2
-- ~~~~~~
-- -- Per IR565916
-- - Added derivative part type checks for S6 or V6.
-- ^^^^^^
--
-- DET 8/30/2010 EDK_MS4
-- ~~~~~~
-- -- Per CR573867
-- - Updated the S6/V6 FIFO Generator version from V6.1 to 7.2.
-- - Added all of the AXI parameters and ports. They are not used
-- in this application.
-- - Updated method for derivative part support using new family
-- aliasing function in family_support.vhd.
-- - Incorporated an implementation to deal with unsupported FPGA
-- parts passed in on the C_FAMILY parameter.
-- ^^^^^^
--
-- DET 10/4/2010 EDK 13.1
-- ~~~~~~
-- - Updated the FIFO Generator version from V7.2 to 7.3.
-- ^^^^^^
--
-- DET 12/8/2010 EDK 13.1
-- ~~~~~~
-- -- Per CR586109
-- - Updated the FIFO Generator version from V7.3 to 8.1.
-- ^^^^^^
--
-- DET 3/2/2011 EDK 13.2
-- ~~~~~~
-- -- Per CR595473
-- - Update to use fifo_generator_v8_2
-- ^^^^^^
--
--
-- RBODDU 08/18/2011 EDK 13.3
-- ~~~~~~
-- - Update to use fifo_generator_v8_3
-- ^^^^^^
--
-- RBODDU 06/07/2012 EDK 14.2
-- ~~~~~~
-- - Update to use fifo_generator_v9_1
-- ^^^^^^
-- RBODDU 06/11/2012 EDK 14.4
-- ~~~~~~
-- - Update to use fifo_generator_v9_2
-- ^^^^^^
-- RBODDU 07/12/2012 EDK 14.5
-- ~~~~~~
-- - Update to use fifo_generator_v9_3
-- ^^^^^^
-- RBODDU 07/12/2012 EDK 14.5
-- ~~~~~~
-- - Update to use fifo_generator_v12_0
-- - Added sleep, wr_rst_busy, and rd_rst_busy signals
-- - Changed FULL_FLAGS_RST_VAL to '1'
-- ^^^^^^
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library fifo_generator_v12_0;
use fifo_generator_v12_0.all;
--library lib_fifo_v1_0;
--use lib_fifo_v1_0.lib_fifo_pkg.all;
--use lib_fifo_v1_0.family_support.all;
-- synopsys translate_off
--library XilinxCoreLib;
--use XilinxCoreLib.all;
-- synopsys translate_on
-------------------------------------------------------------------------------
entity async_fifo_fg is
generic (
C_ALLOW_2N_DEPTH : Integer := 0; -- New paramter to leverage FIFO Gen 2**N depth
C_FAMILY : String := "virtex5"; -- new for FIFO Gen
C_DATA_WIDTH : integer := 16;
C_ENABLE_RLOCS : integer := 0 ; -- not supported in FG
C_FIFO_DEPTH : integer := 15;
C_HAS_ALMOST_EMPTY : integer := 1 ;
C_HAS_ALMOST_FULL : integer := 1 ;
C_HAS_RD_ACK : integer := 0 ;
C_HAS_RD_COUNT : integer := 1 ;
C_HAS_RD_ERR : integer := 0 ;
C_HAS_WR_ACK : integer := 0 ;
C_HAS_WR_COUNT : integer := 1 ;
C_HAS_WR_ERR : integer := 0 ;
C_RD_ACK_LOW : integer := 0 ;
C_RD_COUNT_WIDTH : integer := 3 ;
C_RD_ERR_LOW : integer := 0 ;
C_USE_EMBEDDED_REG : integer := 0 ; -- Valid only for BRAM based FIFO, otherwise needs to be set to 0
C_PRELOAD_REGS : integer := 0 ;
C_PRELOAD_LATENCY : integer := 1 ; -- needs to be set 2 when C_USE_EMBEDDED_REG = 1
C_USE_BLOCKMEM : integer := 1 ; -- 0 = distributed RAM, 1 = BRAM
C_WR_ACK_LOW : integer := 0 ;
C_WR_COUNT_WIDTH : integer := 3 ;
C_WR_ERR_LOW : integer := 0 ;
C_SYNCHRONIZER_STAGE : integer := 2 -- valid values are 0 to 8
);
port (
Din : in std_logic_vector(C_DATA_WIDTH-1 downto 0) := (others => '0');
Wr_en : in std_logic := '1';
Wr_clk : in std_logic := '1';
Rd_en : in std_logic := '0';
Rd_clk : in std_logic := '1';
Ainit : in std_logic := '1';
Dout : out std_logic_vector(C_DATA_WIDTH-1 downto 0);
Full : out std_logic;
Empty : out std_logic;
Almost_full : out std_logic;
Almost_empty : out std_logic;
Wr_count : out std_logic_vector(C_WR_COUNT_WIDTH-1 downto 0);
Rd_count : out std_logic_vector(C_RD_COUNT_WIDTH-1 downto 0);
Rd_ack : out std_logic;
Rd_err : out std_logic;
Wr_ack : out std_logic;
Wr_err : out std_logic
);
end entity async_fifo_fg;
architecture implementation of async_fifo_fg is
-- Function delarations
-------------------------------------------------------------------
-- Function
--
-- Function Name: GetMemType
--
-- Function Description:
-- Generates the required integer value for the FG instance assignment
-- of the C_MEMORY_TYPE parameter. Derived from
-- the input memory type parameter C_USE_BLOCKMEM.
--
-- FIFO Generator values
-- 0 = Any
-- 1 = BRAM
-- 2 = Distributed Memory
-- 3 = Shift Registers
--
-------------------------------------------------------------------
function GetMemType (inputmemtype : integer) return integer is
Variable memtype : Integer := 0;
begin
If (inputmemtype = 0) Then -- distributed Memory
memtype := 2;
else
memtype := 1; -- BRAM
End if;
return(memtype);
end function GetMemType;
function log2(x : natural) return integer is
variable i : integer := 0;
variable val: integer := 1;
begin
if x = 0 then return 0;
else
for j in 0 to 29 loop -- for loop for XST
if val >= x then null;
else
i := i+1;
val := val*2;
end if;
end loop;
-- Fix per CR520627 XST was ignoring this anyway and printing a
-- Warning in SRP file. This will get rid of the warning and not
-- impact simulation.
-- synthesis translate_off
assert val >= x
report "Function log2 received argument larger" &
" than its capability of 2^30. "
severity failure;
-- synthesis translate_on
return i;
end if;
end function log2;
-- Constant Declarations ----------------------------------------------
-- C_FAMILY is directly passed. No need to have family_support function
Constant FAMILY_TO_USE : string := C_FAMILY; -- function from family_support.vhd
-- Constant FAMILY_NOT_SUPPORTED : boolean := (equalIgnoringCase(FAMILY_TO_USE, "nofamily"));
-- Proc_common supports all families
Constant FAMILY_IS_SUPPORTED : boolean := true; --not(FAMILY_NOT_SUPPORTED);
-- Constant FAM_IS_S3_V4_V5 : boolean := (equalIgnoringCase(FAMILY_TO_USE, "spartan3" ) or
-- equalIgnoringCase(FAMILY_TO_USE, "virtex4" ) or
-- equalIgnoringCase(FAMILY_TO_USE, "virtex5")) and
-- FAMILY_IS_SUPPORTED;
-- Changing this to true
Constant FAM_IS_NOT_S3_V4_V5 : boolean := true;
-- Get the integer value for a Block memory type fifo generator call
Constant FG_MEM_TYPE : integer := GetMemType(C_USE_BLOCKMEM);
-- Set the required integer value for the FG instance assignment
-- of the C_IMPLEMENTATION_TYPE parameter. Derived from
-- the input memory type parameter C_MEMORY_TYPE.
--
-- 0 = Common Clock BRAM / Distributed RAM (Synchronous FIFO)
-- 1 = Common Clock Shift Register (Synchronous FIFO)
-- 2 = Independent Clock BRAM/Distributed RAM (Asynchronous FIFO)
-- 3 = Independent/Common Clock V4 Built In Memory -- not used in legacy fifo calls
-- 5 = Independent/Common Clock V5 Built in Memory -- not used in legacy fifo calls
--
Constant FG_IMP_TYPE : integer := 2;
--Signals added to fix MTI and XSIM issues caused by fix for VCS issues not to use "LIBRARY_SCAN = TRUE"
signal PROG_FULL : std_logic;
signal PROG_EMPTY : std_logic;
signal SBITERR : std_logic;
signal DBITERR : std_logic;
signal WR_RST_BUSY : std_logic;
signal RD_RST_BUSY : std_logic;
signal S_AXI_AWREADY : std_logic;
signal S_AXI_WREADY : std_logic;
signal S_AXI_BID : std_logic_vector(3 DOWNTO 0);
signal S_AXI_BRESP : std_logic_vector(2-1 DOWNTO 0);
signal S_AXI_BUSER : std_logic_vector(0 downto 0);
signal S_AXI_BVALID : std_logic;
-- AXI Full/Lite Master Write Channel (Read side)
signal M_AXI_AWID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_AWADDR : std_logic_vector(31 DOWNTO 0);
signal M_AXI_AWLEN : std_logic_vector(8-1 DOWNTO 0);
signal M_AXI_AWSIZE : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_AWBURST : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_AWLOCK : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_AWCACHE : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWPROT : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_AWQOS : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWREGION : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWUSER : std_logic_vector(0 downto 0);
signal M_AXI_AWVALID : std_logic;
signal M_AXI_WID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_WDATA : std_logic_vector(63 DOWNTO 0);
signal M_AXI_WSTRB : std_logic_vector(7 DOWNTO 0);
signal M_AXI_WLAST : std_logic;
signal M_AXI_WUSER : std_logic_vector(0 downto 0);
signal M_AXI_WVALID : std_logic;
signal M_AXI_BREADY : std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
signal S_AXI_ARREADY : std_logic;
signal S_AXI_RID : std_logic_vector(3 DOWNTO 0);
signal S_AXI_RDATA : std_logic_vector(63 DOWNTO 0);
signal S_AXI_RRESP : std_logic_vector(2-1 DOWNTO 0);
signal S_AXI_RLAST : std_logic;
signal S_AXI_RUSER : std_logic_vector(0 downto 0);
signal S_AXI_RVALID : std_logic;
-- AXI Full/Lite Master Read Channel (Read side)
signal M_AXI_ARID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_ARADDR : std_logic_vector(31 DOWNTO 0);
signal M_AXI_ARLEN : std_logic_vector(8-1 DOWNTO 0);
signal M_AXI_ARSIZE : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_ARBURST : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_ARLOCK : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_ARCACHE : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARPROT : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_ARQOS : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARREGION : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARUSER : std_logic_vector(0 downto 0);
signal M_AXI_ARVALID : std_logic;
signal M_AXI_RREADY : std_logic;
-- AXI Streaming Slave Signals (Write side)
signal S_AXIS_TREADY : std_logic;
-- AXI Streaming Master Signals (Read side)
signal M_AXIS_TVALID : std_logic;
signal M_AXIS_TDATA : std_logic_vector(63 DOWNTO 0);
signal M_AXIS_TSTRB : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TKEEP : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TLAST : std_logic;
signal M_AXIS_TID : std_logic_vector(7 DOWNTO 0);
signal M_AXIS_TDEST : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TUSER : std_logic_vector(3 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
signal AXI_AW_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_SBITERR : std_logic;
signal AXI_AW_DBITERR : std_logic;
signal AXI_AW_OVERFLOW : std_logic;
signal AXI_AW_UNDERFLOW : std_logic;
signal AXI_AW_PROG_FULL : STD_LOGIC;
signal AXI_AW_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Write Data Channel Signals
signal AXI_W_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_SBITERR : std_logic;
signal AXI_W_DBITERR : std_logic;
signal AXI_W_OVERFLOW : std_logic;
signal AXI_W_UNDERFLOW : std_logic;
signal AXI_W_PROG_FULL : STD_LOGIC;
signal AXI_W_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Write Response Channel Signals
signal AXI_B_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_SBITERR : std_logic;
signal AXI_B_DBITERR : std_logic;
signal AXI_B_OVERFLOW : std_logic;
signal AXI_B_UNDERFLOW : std_logic;
signal AXI_B_PROG_FULL : STD_LOGIC;
signal AXI_B_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Read Address Channel Signals
signal AXI_AR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_SBITERR : std_logic;
signal AXI_AR_DBITERR : std_logic;
signal AXI_AR_OVERFLOW : std_logic;
signal AXI_AR_UNDERFLOW : std_logic;
signal AXI_AR_PROG_FULL : STD_LOGIC;
signal AXI_AR_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Read Data Channel Signals
signal AXI_R_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_SBITERR : std_logic;
signal AXI_R_DBITERR : std_logic;
signal AXI_R_OVERFLOW : std_logic;
signal AXI_R_UNDERFLOW : std_logic;
signal AXI_R_PROG_FULL : STD_LOGIC;
signal AXI_R_PROG_EMPTY : STD_LOGIC;
-- AXI Streaming FIFO Related Signals
signal AXIS_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_SBITERR : std_logic;
signal AXIS_DBITERR : std_logic;
signal AXIS_OVERFLOW : std_logic;
signal AXIS_UNDERFLOW : std_logic;
signal AXIS_PROG_FULL : STD_LOGIC;
signal AXIS_PROG_EMPTY : STD_LOGIC;
begin --(architecture implementation)
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_FAMILY
--
-- If Generate Description:
-- This IfGen is implemented if an unsupported FPGA family
-- is passed in on the C_FAMILY parameter,
--
------------------------------------------------------------
-- GEN_NO_FAMILY : if (FAMILY_NOT_SUPPORTED) generate
-- begin
-- synthesis translate_off
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_ASSERTION
--
-- Process Description:
-- Generate a simulation error assertion for an unsupported
-- FPGA family string passed in on the C_FAMILY parameter.
--
-------------------------------------------------------------
-- DO_ASSERTION : process
-- begin
-- Wait until second rising wr clock edge to issue assertion
-- Wait until Wr_clk = '1';
-- wait until Wr_clk = '0';
-- Wait until Wr_clk = '1';
-- Report an error in simulation environment
-- assert FALSE report "********* UNSUPPORTED FPGA DEVICE! Check C_FAMILY parameter assignment!"
-- severity ERROR;
-- Wait; -- halt this process
-- end process DO_ASSERTION;
-- synthesis translate_on
-- Tie outputs to logic low or logic high as required
-- Dout <= (others => '0'); -- : out std_logic_vector(C_DATA_WIDTH-1 downto 0);
-- Full <= '0' ; -- : out std_logic;
-- Empty <= '1' ; -- : out std_logic;
-- Almost_full <= '0' ; -- : out std_logic;
-- Almost_empty <= '0' ; -- : out std_logic;
-- Wr_count <= (others => '0'); -- : out std_logic_vector(C_WR_COUNT_WIDTH-1 downto 0);
-- Rd_count <= (others => '0'); -- : out std_logic_vector(C_RD_COUNT_WIDTH-1 downto 0);
-- Rd_ack <= '0' ; -- : out std_logic;
-- Rd_err <= '1' ; -- : out std_logic;
-- Wr_ack <= '0' ; -- : out std_logic;
-- Wr_err <= '1' ; -- : out std_logic
-- end generate GEN_NO_FAMILY;
------------------------------------------------------------
-- If Generate
--
-- Label: LEGACY_COREGEN_DEPTH
--
-- If Generate Description:
-- This IfGen implements the FIFO Generator call where
-- the User specified depth and count widths follow the
-- legacy CoreGen Async FIFO requirements of depth being
-- (2**N)-1 and the count widths set to reflect the (2**N)-1
-- FIFO depth.
--
-- Special Note:
-- The legacy CoreGen Async FIFOs would only support fifo depths of (2**n)-1
-- and the Dcount widths were 1 less than if a full 2**n depth were supported.
-- Thus legacy IP will be calling this wrapper with the (2**n)-1 FIFo depths
-- specified and the Dcount widths smaller by 1 bit.
-- This wrapper file has to account for this since the new FIFO Generator
-- does not follow this convention for Async FIFOs and expects depths to
-- be specified in full 2**n values.
--
------------------------------------------------------------
LEGACY_COREGEN_DEPTH : if (C_ALLOW_2N_DEPTH = 0 and
FAMILY_IS_SUPPORTED) generate
-- IfGen Constant Declarations -------------
-- See Special Note above for reasoning behind
-- this adjustment of the requested FIFO depth and data count
-- widths.
Constant ADJUSTED_AFIFO_DEPTH : integer := C_FIFO_DEPTH+1;
Constant ADJUSTED_RDCNT_WIDTH : integer := C_RD_COUNT_WIDTH;
Constant ADJUSTED_WRCNT_WIDTH : integer := C_WR_COUNT_WIDTH;
-- The programable thresholds are not used so this is housekeeping.
Constant PROG_FULL_THRESH_ASSERT_VAL : integer := ADJUSTED_AFIFO_DEPTH-3;
Constant PROG_FULL_THRESH_NEGATE_VAL : integer := ADJUSTED_AFIFO_DEPTH-4;
-- The parameters C_RD_PNTR_WIDTH and C_WR_PNTR_WIDTH for Fifo_generator_v4_3 core
-- must be in the range of 4 thru 22. The setting is dependant upon the
-- log2 function of the MIN and MAX FIFO DEPTH settings in coregen. Since Async FIFOs
-- previous to development of fifo generator do not support separate read and
-- write fifo widths (and depths dependant upon the widths) both of the pointer value
-- calculations below will use the parameter ADJUSTED_AFIFO_DEPTH. The valid range for
-- the ADJUSTED_AFIFO_DEPTH is 16 to 65536 (the async FIFO range is 15 to 65,535...it
-- must be equal to (2^N-1;, N = 4 to 16) per DS232 November 11, 2004 -
-- Asynchronous FIFO v6.1)
Constant ADJUSTED_RD_PNTR_WIDTH : integer range 4 to 22 := log2(ADJUSTED_AFIFO_DEPTH);
Constant ADJUSTED_WR_PNTR_WIDTH : integer range 4 to 22 := log2(ADJUSTED_AFIFO_DEPTH);
-- Constant zeros for programmable threshold inputs
signal PROG_RDTHRESH_ZEROS : std_logic_vector(ADJUSTED_RD_PNTR_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
signal PROG_WRTHRESH_ZEROS : std_logic_vector(ADJUSTED_WR_PNTR_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
-- IfGen Signal Declarations --------------
Signal sig_full_fifo_rdcnt : std_logic_vector(ADJUSTED_RDCNT_WIDTH-1 DOWNTO 0);
Signal sig_full_fifo_wrcnt : std_logic_vector(ADJUSTED_WRCNT_WIDTH-1 DOWNTO 0);
--Signals added to fix MTI and XSIM issues caused by fix for VCS issues not to use "LIBRARY_SCAN = TRUE"
signal DATA_COUNT : std_logic_vector(ADJUSTED_WRCNT_WIDTH-1 DOWNTO 0);
begin
-- Rip the LS bits of the write data count and assign to Write Count
-- output port
Wr_count <= sig_full_fifo_wrcnt(C_WR_COUNT_WIDTH-1 downto 0);
-- Rip the LS bits of the read data count and assign to Read Count
-- output port
Rd_count <= sig_full_fifo_rdcnt(C_RD_COUNT_WIDTH-1 downto 0);
------------------------------------------------------------
-- If Generate
--
-- Label: V6_S6_AND_LATER
--
-- If Generate Description:
-- This IFGen Implements the FIFO using fifo_generator_v9_3
-- for FPGA Families that are Virtex-6, Spartan-6, and later.
--
------------------------------------------------------------
V6_S6_AND_LATER : if (FAM_IS_NOT_S3_V4_V5) generate
begin
-------------------------------------------------------------------------------
-- Instantiate the generalized FIFO Generator instance
--
-- NOTE:
-- DO NOT CHANGE TO DIRECT ENTITY INSTANTIATION!!!
-- This is a Coregen FIFO Generator Call module for
-- legacy BRAM implementations of an Async FIFo.
--
-------------------------------------------------------------------------------
I_ASYNC_FIFO_BRAM : entity fifo_generator_v12_0.fifo_generator_v12_0
generic map(
C_COMMON_CLOCK => 0,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => ADJUSTED_WRCNT_WIDTH,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => C_DATA_WIDTH,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => C_DATA_WIDTH,
C_ENABLE_RLOCS => C_ENABLE_RLOCS,
C_FAMILY => FAMILY_TO_USE,
C_FULL_FLAGS_RST_VAL => 1,
C_HAS_ALMOST_EMPTY => C_HAS_ALMOST_EMPTY,
C_HAS_ALMOST_FULL => C_HAS_ALMOST_FULL,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => C_HAS_WR_ERR,
C_HAS_RD_DATA_COUNT => C_HAS_RD_COUNT,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_HAS_UNDERFLOW => C_HAS_RD_ERR,
C_HAS_VALID => C_HAS_RD_ACK,
C_HAS_WR_ACK => C_HAS_WR_ACK,
C_HAS_WR_DATA_COUNT => C_HAS_WR_COUNT,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => FG_IMP_TYPE,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => FG_MEM_TYPE,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => C_WR_ERR_LOW,
C_PRELOAD_LATENCY => C_PRELOAD_LATENCY, ----1, Fixed CR#658129
C_PRELOAD_REGS => C_PRELOAD_REGS, ----0, Fixed CR#658129
C_PRIM_FIFO_TYPE => "512x36", -- only used for V5 Hard FIFO
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => PROG_FULL_THRESH_ASSERT_VAL,
C_PROG_FULL_THRESH_NEGATE_VAL => PROG_FULL_THRESH_NEGATE_VAL,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => ADJUSTED_RDCNT_WIDTH,
C_RD_DEPTH => ADJUSTED_AFIFO_DEPTH,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => ADJUSTED_RD_PNTR_WIDTH,
C_UNDERFLOW_LOW => C_RD_ERR_LOW,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => C_USE_EMBEDDED_REG, ----0, Fixed CR#658129
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_WR_DATA_COUNT_WIDTH => ADJUSTED_WRCNT_WIDTH,
C_WR_DEPTH => ADJUSTED_AFIFO_DEPTH,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => ADJUSTED_WR_PNTR_WIDTH,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => C_SYNCHRONIZER_STAGE,
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => 0, -- : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE => 0, -- : integer := 0; -- 0: AXI Stream; 1: AXI Full; 2: AXI Lite
C_HAS_AXI_WR_CHANNEL => 0, -- : integer := 0;
C_HAS_AXI_RD_CHANNEL => 0, -- : integer := 0;
C_HAS_SLAVE_CE => 0, -- : integer := 0;
C_HAS_MASTER_CE => 0, -- : integer := 0;
C_ADD_NGC_CONSTRAINT => 0, -- : integer := 0;
C_USE_COMMON_OVERFLOW => 0, -- : integer := 0;
C_USE_COMMON_UNDERFLOW => 0, -- : integer := 0;
C_USE_DEFAULT_SETTINGS => 0, -- : integer := 0;
-- AXI Full/Lite
C_AXI_ID_WIDTH => 4 , -- : integer := 0;
C_AXI_ADDR_WIDTH => 32, -- : integer := 0;
C_AXI_DATA_WIDTH => 64, -- : integer := 0;
C_AXI_LEN_WIDTH => 8, -- : integer := 8;
C_AXI_LOCK_WIDTH => 2, -- : integer := 2;
C_HAS_AXI_ID => 0, -- : integer := 0;
C_HAS_AXI_AWUSER => 0 , -- : integer := 0;
C_HAS_AXI_WUSER => 0 , -- : integer := 0;
C_HAS_AXI_BUSER => 0 , -- : integer := 0;
C_HAS_AXI_ARUSER => 0 , -- : integer := 0;
C_HAS_AXI_RUSER => 0 , -- : integer := 0;
C_AXI_ARUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_AWUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_WUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_BUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_RUSER_WIDTH => 1 , -- : integer := 0;
-- AXI Streaming
C_HAS_AXIS_TDATA => 0 , -- : integer := 0;
C_HAS_AXIS_TID => 0 , -- : integer := 0;
C_HAS_AXIS_TDEST => 0 , -- : integer := 0;
C_HAS_AXIS_TUSER => 0 , -- : integer := 0;
C_HAS_AXIS_TREADY => 1 , -- : integer := 0;
C_HAS_AXIS_TLAST => 0 , -- : integer := 0;
C_HAS_AXIS_TSTRB => 0 , -- : integer := 0;
C_HAS_AXIS_TKEEP => 0 , -- : integer := 0;
C_AXIS_TDATA_WIDTH => 64, -- : integer := 1;
C_AXIS_TID_WIDTH => 8 , -- : integer := 1;
C_AXIS_TDEST_WIDTH => 4 , -- : integer := 1;
C_AXIS_TUSER_WIDTH => 4 , -- : integer := 1;
C_AXIS_TSTRB_WIDTH => 4 , -- : integer := 1;
C_AXIS_TKEEP_WIDTH => 4 , -- : integer := 1;
-- AXI Channel Type
-- WACH --> Write Address Channel
-- WDCH --> Write Data Channel
-- WRCH --> Write Response Channel
-- RACH --> Read Address Channel
-- RDCH --> Read Data Channel
-- AXIS --> AXI Streaming
C_WACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logic
C_WDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_WRCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_AXIS_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
-- AXI Implementation Type
-- 1 = Common Clock Block RAM FIFO
-- 2 = Common Clock Distributed RAM FIFO
-- 11 = Independent Clock Block RAM FIFO
-- 12 = Independent Clock Distributed RAM FIFO
C_IMPLEMENTATION_TYPE_WACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WRCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_AXIS => 1, -- : integer := 0;
-- AXI FIFO Type
-- 0 = Data FIFO
-- 1 = Packet FIFO
-- 2 = Low Latency Data FIFO
C_APPLICATION_TYPE_WACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WRCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_AXIS => 0, -- : integer := 0;
-- Enable ECC
-- 0 = ECC disabled
-- 1 = ECC enabled
C_USE_ECC_WACH => 0, -- : integer := 0;
C_USE_ECC_WDCH => 0, -- : integer := 0;
C_USE_ECC_WRCH => 0, -- : integer := 0;
C_USE_ECC_RACH => 0, -- : integer := 0;
C_USE_ECC_RDCH => 0, -- : integer := 0;
C_USE_ECC_AXIS => 0, -- : integer := 0;
-- ECC Error Injection Type
-- 0 = No Error Injection
-- 1 = Single Bit Error Injection
-- 2 = Double Bit Error Injection
-- 3 = Single Bit and Double Bit Error Injection
C_ERROR_INJECTION_TYPE_WACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WRCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_AXIS => 0, -- : integer := 0;
-- Input Data Width
-- Accumulation of all AXI input signal's width
C_DIN_WIDTH_WACH => 32, -- : integer := 1;
C_DIN_WIDTH_WDCH => 64, -- : integer := 1;
C_DIN_WIDTH_WRCH => 2 , -- : integer := 1;
C_DIN_WIDTH_RACH => 32, -- : integer := 1;
C_DIN_WIDTH_RDCH => 64, -- : integer := 1;
C_DIN_WIDTH_AXIS => 1 , -- : integer := 1;
C_WR_DEPTH_WACH => 16 , -- : integer := 16;
C_WR_DEPTH_WDCH => 1024, -- : integer := 16;
C_WR_DEPTH_WRCH => 16 , -- : integer := 16;
C_WR_DEPTH_RACH => 16 , -- : integer := 16;
C_WR_DEPTH_RDCH => 1024, -- : integer := 16;
C_WR_DEPTH_AXIS => 1024, -- : integer := 16;
C_WR_PNTR_WIDTH_WACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_WDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_WRCH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_AXIS => 10, -- : integer := 4;
C_HAS_DATA_COUNTS_WACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WRCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_AXIS => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WRCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_AXIS => 0, -- : integer := 0;
C_PROG_FULL_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023, -- : integer := 0;
C_PROG_EMPTY_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022, -- : integer := 0;
C_REG_SLICE_MODE_WACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WRCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_AXIS => 0 -- : integer := 0
)
port map (
backup => '0',
backup_marker => '0',
clk => '0',
rst => Ainit,
srst => '0',
wr_clk => Wr_clk,
wr_rst => Ainit,
rd_clk => Rd_clk,
rd_rst => Ainit,
din => Din,
wr_en => Wr_en,
rd_en => Rd_en,
prog_empty_thresh => PROG_RDTHRESH_ZEROS,
prog_empty_thresh_assert => PROG_RDTHRESH_ZEROS,
prog_empty_thresh_negate => PROG_RDTHRESH_ZEROS,
prog_full_thresh => PROG_WRTHRESH_ZEROS,
prog_full_thresh_assert => PROG_WRTHRESH_ZEROS,
prog_full_thresh_negate => PROG_WRTHRESH_ZEROS,
int_clk => '0',
injectdbiterr => '0', -- new FG 5.1/5.2
injectsbiterr => '0', -- new FG 5.1/5.2
sleep => '0',
dout => Dout,
full => Full,
almost_full => Almost_full,
wr_ack => Wr_ack,
overflow => Wr_err,
empty => Empty,
almost_empty => Almost_empty,
valid => Rd_ack,
underflow => Rd_err,
data_count => DATA_COUNT,
rd_data_count => sig_full_fifo_rdcnt,
wr_data_count => sig_full_fifo_wrcnt,
prog_full => PROG_FULL,
prog_empty => PROG_EMPTY,
sbiterr => SBITERR,
dbiterr => DBITERR,
wr_rst_busy => WR_RST_BUSY,
rd_rst_busy => RD_RST_BUSY,
-- AXI Global Signal
m_aclk => '0', -- : IN std_logic := '0';
s_aclk => '0', -- : IN std_logic := '0';
s_aresetn => '0', -- : IN std_logic := '0';
m_aclk_en => '0', -- : IN std_logic := '0';
s_aclk_en => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Slave Write Channel (write side)
s_axi_awid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awaddr => "00000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlen => "00000000", --(others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awsize => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awburst => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlock => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awcache => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awprot => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awqos => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awregion => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awvalid => '0', -- : IN std_logic := '0';
s_axi_awready => S_AXI_AWREADY, -- : OUT std_logic;
s_axi_wid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wstrb => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wlast => '0', -- : IN std_logic := '0';
s_axi_wuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wvalid => '0', -- : IN std_logic := '0';
s_axi_wready => S_AXI_WREADY, -- : OUT std_logic;
s_axi_bid => S_AXI_BID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_bresp => S_AXI_BRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_buser => S_AXI_BUSER, -- : OUT std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0);
s_axi_bvalid => S_AXI_BVALID, -- : OUT std_logic;
s_axi_bready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Write Channel (Read side)
m_axi_awid => M_AXI_AWID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_awaddr => M_AXI_AWADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_awlen => M_AXI_AWLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_awsize => M_AXI_AWSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awburst => M_AXI_AWBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awlock => M_AXI_AWLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awcache => M_AXI_AWCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awprot => M_AXI_AWPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awqos => M_AXI_AWQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awregion => M_AXI_AWREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awuser => M_AXI_AWUSER, -- : OUT std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0);
m_axi_awvalid => M_AXI_AWVALID, -- : OUT std_logic;
m_axi_awready => '0', -- : IN std_logic := '0';
m_axi_wid => M_AXI_WID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_wdata => M_AXI_WDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
m_axi_wstrb => M_AXI_WSTRB, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0);
m_axi_wlast => M_AXI_WLAST, -- : OUT std_logic;
m_axi_wuser => M_AXI_WUSER, -- : OUT std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0);
m_axi_wvalid => M_AXI_WVALID, -- : OUT std_logic;
m_axi_wready => '0', -- : IN std_logic := '0';
m_axi_bid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_buser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bvalid => '0', -- : IN std_logic := '0';
m_axi_bready => M_AXI_BREADY, -- : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
s_axi_arid => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_araddr => "00000000000000000000000000000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlen => "00000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arsize => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arburst => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlock => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arcache => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arprot => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arqos => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arregion => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_aruser => "0", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arvalid => '0', -- : IN std_logic := '0';
s_axi_arready => S_AXI_ARREADY, -- : OUT std_logic;
s_axi_rid => S_AXI_RID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
s_axi_rdata => S_AXI_RDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
s_axi_rresp => S_AXI_RRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_rlast => S_AXI_RLAST, -- : OUT std_logic;
s_axi_ruser => S_AXI_RUSER, -- : OUT std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0);
s_axi_rvalid => S_AXI_RVALID, -- : OUT std_logic;
s_axi_rready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Read Channel (Read side)
m_axi_arid => M_AXI_ARID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_araddr => M_AXI_ARADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_arlen => M_AXI_ARLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_arsize => M_AXI_ARSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arburst => M_AXI_ARBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arlock => M_AXI_ARLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arcache => M_AXI_ARCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arprot => M_AXI_ARPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arqos => M_AXI_ARQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arregion => M_AXI_ARREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_aruser => M_AXI_ARUSER, -- : OUT std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0);
m_axi_arvalid => M_AXI_ARVALID, -- : OUT std_logic;
m_axi_arready => '0', -- : IN std_logic := '0';
m_axi_rid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rlast => '0', -- : IN std_logic := '0';
m_axi_ruser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rvalid => '0', -- : IN std_logic := '0';
m_axi_rready => M_AXI_RREADY, -- : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
s_axis_tvalid => '0', -- : IN std_logic := '0';
s_axis_tready => S_AXIS_TREADY, -- : OUT std_logic;
s_axis_tdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tstrb => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tkeep => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tlast => '0', -- : IN std_logic := '0';
s_axis_tid => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tdest => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tuser => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
-- AXI Streaming Master Signals (Read side)
m_axis_tvalid => M_AXIS_TVALID, -- : OUT std_logic;
m_axis_tready => '0', -- : IN std_logic := '0';
m_axis_tdata => M_AXIS_TDATA, -- : OUT std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0);
m_axis_tstrb => M_AXIS_TSTRB, -- : OUT std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0);
m_axis_tkeep => M_AXIS_TKEEP, -- : OUT std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0);
m_axis_tlast => M_AXIS_TLAST, -- : OUT std_logic;
m_axis_tid => M_AXIS_TID, -- : OUT std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0);
m_axis_tdest => M_AXIS_TDEST, -- : OUT std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0);
m_axis_tuser => M_AXIS_TUSER, -- : OUT std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
axi_aw_injectsbiterr => '0', -- : IN std_logic := '0';
axi_aw_injectdbiterr => '0', -- : IN std_logic := '0';
axi_aw_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_data_count => AXI_AW_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_wr_data_count => AXI_AW_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_rd_data_count => AXI_AW_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_sbiterr => AXI_AW_SBITERR, -- : OUT std_logic;
axi_aw_dbiterr => AXI_AW_DBITERR, -- : OUT std_logic;
axi_aw_overflow => AXI_AW_OVERFLOW, -- : OUT std_logic;
axi_aw_underflow => AXI_AW_UNDERFLOW, -- : OUT std_logic;
axi_aw_prog_full => AXI_AW_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_aw_prog_empty => AXI_AW_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Data Channel Signals
axi_w_injectsbiterr => '0', -- : IN std_logic := '0';
axi_w_injectdbiterr => '0', -- : IN std_logic := '0';
axi_w_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_data_count => AXI_W_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_wr_data_count => AXI_W_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_rd_data_count => AXI_W_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_sbiterr => AXI_W_SBITERR, -- : OUT std_logic;
axi_w_dbiterr => AXI_W_DBITERR, -- : OUT std_logic;
axi_w_overflow => AXI_W_OVERFLOW, -- : OUT std_logic;
axi_w_underflow => AXI_W_UNDERFLOW, -- : OUT std_logic;
axi_w_prog_full => AXI_W_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_w_prog_empty => AXI_W_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Response Channel Signals
axi_b_injectsbiterr => '0', -- : IN std_logic := '0';
axi_b_injectdbiterr => '0', -- : IN std_logic := '0';
axi_b_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_data_count => AXI_B_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_wr_data_count => AXI_B_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_rd_data_count => AXI_B_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_sbiterr => AXI_B_SBITERR, -- : OUT std_logic;
axi_b_dbiterr => AXI_B_DBITERR, -- : OUT std_logic;
axi_b_overflow => AXI_B_OVERFLOW, -- : OUT std_logic;
axi_b_underflow => AXI_B_UNDERFLOW, -- : OUT std_logic;
axi_b_prog_full => AXI_B_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_b_prog_empty => AXI_B_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Address Channel Signals
axi_ar_injectsbiterr => '0', -- : IN std_logic := '0';
axi_ar_injectdbiterr => '0', -- : IN std_logic := '0';
axi_ar_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_data_count => AXI_AR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_wr_data_count => AXI_AR_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_rd_data_count => AXI_AR_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_sbiterr => AXI_AR_SBITERR, -- : OUT std_logic;
axi_ar_dbiterr => AXI_AR_DBITERR, -- : OUT std_logic;
axi_ar_overflow => AXI_AR_OVERFLOW, -- : OUT std_logic;
axi_ar_underflow => AXI_AR_UNDERFLOW, -- : OUT std_logic;
axi_ar_prog_full => AXI_AR_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_ar_prog_empty => AXI_AR_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Data Channel Signals
axi_r_injectsbiterr => '0', -- : IN std_logic := '0';
axi_r_injectdbiterr => '0', -- : IN std_logic := '0';
axi_r_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_data_count => AXI_R_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_wr_data_count => AXI_R_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_rd_data_count => AXI_R_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_sbiterr => AXI_R_SBITERR, -- : OUT std_logic;
axi_r_dbiterr => AXI_R_DBITERR, -- : OUT std_logic;
axi_r_overflow => AXI_R_OVERFLOW, -- : OUT std_logic;
axi_r_underflow => AXI_R_UNDERFLOW, -- : OUT std_logic;
axi_r_prog_full => AXI_R_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_r_prog_empty => AXI_R_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Streaming FIFO Related Signals
axis_injectsbiterr => '0', -- : IN std_logic := '0';
axis_injectdbiterr => '0', -- : IN std_logic := '0';
axis_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_data_count => AXIS_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_wr_data_count => AXIS_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_rd_data_count => AXIS_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_sbiterr => AXIS_SBITERR, -- : OUT std_logic;
axis_dbiterr => AXIS_DBITERR, -- : OUT std_logic;
axis_overflow => AXIS_OVERFLOW, -- : OUT std_logic;
axis_underflow => AXIS_UNDERFLOW, -- : OUT std_logic
axis_prog_full => AXIS_PROG_FULL, -- : OUT STD_LOGIC := '0';
axis_prog_empty => AXIS_PROG_EMPTY -- : OUT STD_LOGIC := '1';
);
end generate V6_S6_AND_LATER;
end generate LEGACY_COREGEN_DEPTH;
------------------------------------------------------------
-- If Generate
--
-- Label: USE_2N_DEPTH
--
-- If Generate Description:
-- This IfGen implements the FIFO Generator call where
-- the User may specify depth and count widths of 2**N
-- for Async FIFOs The associated count widths are set to
-- reflect the 2**N FIFO depth.
--
------------------------------------------------------------
USE_2N_DEPTH : if (C_ALLOW_2N_DEPTH = 1 and
FAMILY_IS_SUPPORTED) generate
-- The programable thresholds are not used so this is housekeeping.
Constant PROG_FULL_THRESH_ASSERT_VAL : integer := C_FIFO_DEPTH-3;
Constant PROG_FULL_THRESH_NEGATE_VAL : integer := C_FIFO_DEPTH-4;
Constant RD_PNTR_WIDTH : integer range 4 to 22 := log2(C_FIFO_DEPTH);
Constant WR_PNTR_WIDTH : integer range 4 to 22 := log2(C_FIFO_DEPTH);
-- Constant zeros for programmable threshold inputs
signal PROG_RDTHRESH_ZEROS : std_logic_vector(RD_PNTR_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
signal PROG_WRTHRESH_ZEROS : std_logic_vector(WR_PNTR_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
-- Signals Declarations
Signal sig_full_fifo_rdcnt : std_logic_vector(C_RD_COUNT_WIDTH-1 DOWNTO 0);
Signal sig_full_fifo_wrcnt : std_logic_vector(C_WR_COUNT_WIDTH-1 DOWNTO 0);
--Signals added to fix MTI and XSIM issues caused by fix for VCS issues not to use "LIBRARY_SCAN = TRUE"
signal DATA_COUNT : std_logic_vector(C_WR_COUNT_WIDTH-1 DOWNTO 0);
begin
-- Rip the LS bits of the write data count and assign to Write Count
-- output port
Wr_count <= sig_full_fifo_wrcnt(C_WR_COUNT_WIDTH-1 downto 0);
-- Rip the LS bits of the read data count and assign to Read Count
-- output port
Rd_count <= sig_full_fifo_rdcnt(C_RD_COUNT_WIDTH-1 downto 0);
------------------------------------------------------------
-- If Generate
--
-- Label: V6_S6_AND_LATER
--
-- If Generate Description:
-- This IFGen Implements the FIFO using fifo_generator_v9_3
-- for FPGA Families that are Virtex-6, Spartan-6, and later.
--
------------------------------------------------------------
V6_S6_AND_LATER : if (FAM_IS_NOT_S3_V4_V5) generate
begin
-------------------------------------------------------------------------------
-- Instantiate the generalized FIFO Generator instance
--
-- NOTE:
-- DO NOT CHANGE TO DIRECT ENTITY INSTANTIATION!!!
-- This is a Coregen FIFO Generator Call module for
-- legacy BRAM implementations of an Async FIFo.
--
-------------------------------------------------------------------------------
I_ASYNC_FIFO_BRAM : entity fifo_generator_v12_0.fifo_generator_v12_0
generic map(
C_COMMON_CLOCK => 0,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => C_WR_COUNT_WIDTH,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => C_DATA_WIDTH,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => C_DATA_WIDTH,
C_ENABLE_RLOCS => C_ENABLE_RLOCS,
C_FAMILY => FAMILY_TO_USE,
C_FULL_FLAGS_RST_VAL => 1,
C_HAS_ALMOST_EMPTY => C_HAS_ALMOST_EMPTY,
C_HAS_ALMOST_FULL => C_HAS_ALMOST_FULL,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => C_HAS_WR_ERR,
C_HAS_RD_DATA_COUNT => C_HAS_RD_COUNT,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_HAS_UNDERFLOW => C_HAS_RD_ERR,
C_HAS_VALID => C_HAS_RD_ACK,
C_HAS_WR_ACK => C_HAS_WR_ACK,
C_HAS_WR_DATA_COUNT => C_HAS_WR_COUNT,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => FG_IMP_TYPE,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => FG_MEM_TYPE,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => C_WR_ERR_LOW,
C_PRELOAD_LATENCY => C_PRELOAD_LATENCY, ----1, Fixed CR#658129
C_PRELOAD_REGS => C_PRELOAD_REGS, ----0, Fixed CR#658129
C_PRIM_FIFO_TYPE => "512x36", -- only used for V5 Hard FIFO
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => PROG_FULL_THRESH_ASSERT_VAL,
C_PROG_FULL_THRESH_NEGATE_VAL => PROG_FULL_THRESH_NEGATE_VAL,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => C_RD_COUNT_WIDTH,
C_RD_DEPTH => C_FIFO_DEPTH,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => RD_PNTR_WIDTH,
C_UNDERFLOW_LOW => C_RD_ERR_LOW,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => C_USE_EMBEDDED_REG, ----0, Fixed CR#658129
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_WR_DATA_COUNT_WIDTH => C_WR_COUNT_WIDTH,
C_WR_DEPTH => C_FIFO_DEPTH,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => WR_PNTR_WIDTH,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_ERROR_INJECTION_TYPE => 0,
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => 0, -- : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE => 0, -- : integer := 0; -- 0: AXI Stream; 1: AXI Full; 2: AXI Lite
C_HAS_AXI_WR_CHANNEL => 0, -- : integer := 0;
C_HAS_AXI_RD_CHANNEL => 0, -- : integer := 0;
C_HAS_SLAVE_CE => 0, -- : integer := 0;
C_HAS_MASTER_CE => 0, -- : integer := 0;
C_ADD_NGC_CONSTRAINT => 0, -- : integer := 0;
C_USE_COMMON_OVERFLOW => 0, -- : integer := 0;
C_USE_COMMON_UNDERFLOW => 0, -- : integer := 0;
C_USE_DEFAULT_SETTINGS => 0, -- : integer := 0;
-- AXI Full/Lite
C_AXI_ID_WIDTH => 4 , -- : integer := 0;
C_AXI_ADDR_WIDTH => 32, -- : integer := 0;
C_AXI_DATA_WIDTH => 64, -- : integer := 0;
C_HAS_AXI_AWUSER => 0 , -- : integer := 0;
C_HAS_AXI_WUSER => 0 , -- : integer := 0;
C_HAS_AXI_BUSER => 0 , -- : integer := 0;
C_HAS_AXI_ARUSER => 0 , -- : integer := 0;
C_HAS_AXI_RUSER => 0 , -- : integer := 0;
C_AXI_ARUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_AWUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_WUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_BUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_RUSER_WIDTH => 1 , -- : integer := 0;
-- AXI Streaming
C_HAS_AXIS_TDATA => 0 , -- : integer := 0;
C_HAS_AXIS_TID => 0 , -- : integer := 0;
C_HAS_AXIS_TDEST => 0 , -- : integer := 0;
C_HAS_AXIS_TUSER => 0 , -- : integer := 0;
C_HAS_AXIS_TREADY => 1 , -- : integer := 0;
C_HAS_AXIS_TLAST => 0 , -- : integer := 0;
C_HAS_AXIS_TSTRB => 0 , -- : integer := 0;
C_HAS_AXIS_TKEEP => 0 , -- : integer := 0;
C_AXIS_TDATA_WIDTH => 64, -- : integer := 1;
C_AXIS_TID_WIDTH => 8 , -- : integer := 1;
C_AXIS_TDEST_WIDTH => 4 , -- : integer := 1;
C_AXIS_TUSER_WIDTH => 4 , -- : integer := 1;
C_AXIS_TSTRB_WIDTH => 4 , -- : integer := 1;
C_AXIS_TKEEP_WIDTH => 4 , -- : integer := 1;
-- AXI Channel Type
-- WACH --> Write Address Channel
-- WDCH --> Write Data Channel
-- WRCH --> Write Response Channel
-- RACH --> Read Address Channel
-- RDCH --> Read Data Channel
-- AXIS --> AXI Streaming
C_WACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logic
C_WDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_WRCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_AXIS_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
-- AXI Implementation Type
-- 1 = Common Clock Block RAM FIFO
-- 2 = Common Clock Distributed RAM FIFO
-- 11 = Independent Clock Block RAM FIFO
-- 12 = Independent Clock Distributed RAM FIFO
C_IMPLEMENTATION_TYPE_WACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WRCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_AXIS => 1, -- : integer := 0;
-- AXI FIFO Type
-- 0 = Data FIFO
-- 1 = Packet FIFO
-- 2 = Low Latency Data FIFO
C_APPLICATION_TYPE_WACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WRCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_AXIS => 0, -- : integer := 0;
-- Enable ECC
-- 0 = ECC disabled
-- 1 = ECC enabled
C_USE_ECC_WACH => 0, -- : integer := 0;
C_USE_ECC_WDCH => 0, -- : integer := 0;
C_USE_ECC_WRCH => 0, -- : integer := 0;
C_USE_ECC_RACH => 0, -- : integer := 0;
C_USE_ECC_RDCH => 0, -- : integer := 0;
C_USE_ECC_AXIS => 0, -- : integer := 0;
-- ECC Error Injection Type
-- 0 = No Error Injection
-- 1 = Single Bit Error Injection
-- 2 = Double Bit Error Injection
-- 3 = Single Bit and Double Bit Error Injection
C_ERROR_INJECTION_TYPE_WACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WRCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_AXIS => 0, -- : integer := 0;
-- Input Data Width
-- Accumulation of all AXI input signal's width
C_DIN_WIDTH_WACH => 32, -- : integer := 1;
C_DIN_WIDTH_WDCH => 64, -- : integer := 1;
C_DIN_WIDTH_WRCH => 2 , -- : integer := 1;
C_DIN_WIDTH_RACH => 32, -- : integer := 1;
C_DIN_WIDTH_RDCH => 64, -- : integer := 1;
C_DIN_WIDTH_AXIS => 1 , -- : integer := 1;
C_WR_DEPTH_WACH => 16 , -- : integer := 16;
C_WR_DEPTH_WDCH => 1024, -- : integer := 16;
C_WR_DEPTH_WRCH => 16 , -- : integer := 16;
C_WR_DEPTH_RACH => 16 , -- : integer := 16;
C_WR_DEPTH_RDCH => 1024, -- : integer := 16;
C_WR_DEPTH_AXIS => 1024, -- : integer := 16;
C_WR_PNTR_WIDTH_WACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_WDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_WRCH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_AXIS => 10, -- : integer := 4;
C_HAS_DATA_COUNTS_WACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WRCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_AXIS => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WRCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_AXIS => 0, -- : integer := 0;
C_PROG_FULL_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023, -- : integer := 0;
C_PROG_EMPTY_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022, -- : integer := 0;
C_REG_SLICE_MODE_WACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WRCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_AXIS => 0 -- : integer := 0
)
port map (
backup => '0', -- : IN std_logic := '0';
backup_marker => '0', -- : IN std_logic := '0';
clk => '0', -- : IN std_logic := '0';
rst => Ainit, -- : IN std_logic := '0';
srst => '0', -- : IN std_logic := '0';
wr_clk => Wr_clk, -- : IN std_logic := '0';
wr_rst => Ainit, -- : IN std_logic := '0';
rd_clk => Rd_clk, -- : IN std_logic := '0';
rd_rst => Ainit, -- : IN std_logic := '0';
din => Din, -- : IN std_logic_vector(C_DIN_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
wr_en => Wr_en, -- : IN std_logic := '0';
rd_en => Rd_en, -- : IN std_logic := '0';
prog_empty_thresh => PROG_RDTHRESH_ZEROS, -- : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
prog_empty_thresh_assert => PROG_RDTHRESH_ZEROS, -- : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
prog_empty_thresh_negate => PROG_RDTHRESH_ZEROS, -- : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
prog_full_thresh => PROG_WRTHRESH_ZEROS, -- : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
prog_full_thresh_assert => PROG_WRTHRESH_ZEROS, -- : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
prog_full_thresh_negate => PROG_WRTHRESH_ZEROS, -- : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
int_clk => '0', -- : IN std_logic := '0';
injectdbiterr => '0', -- new FG 5.1 -- : IN std_logic := '0';
injectsbiterr => '0', -- new FG 5.1 -- : IN std_logic := '0';
sleep => '0', -- : IN std_logic := '0';
dout => Dout, -- : OUT std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0);
full => Full, -- : OUT std_logic;
almost_full => Almost_full, -- : OUT std_logic;
wr_ack => Wr_ack, -- : OUT std_logic;
overflow => Rd_err, -- : OUT std_logic;
empty => Empty, -- : OUT std_logic;
almost_empty => Almost_empty, -- : OUT std_logic;
valid => Rd_ack, -- : OUT std_logic;
underflow => Wr_err, -- : OUT std_logic;
data_count => DATA_COUNT, -- : OUT std_logic_vector(C_DATA_COUNT_WIDTH-1 DOWNTO 0);
rd_data_count => sig_full_fifo_rdcnt, -- : OUT std_logic_vector(C_RD_DATA_COUNT_WIDTH-1 DOWNTO 0);
wr_data_count => sig_full_fifo_wrcnt, -- : OUT std_logic_vector(C_WR_DATA_COUNT_WIDTH-1 DOWNTO 0);
prog_full => PROG_FULL, -- : OUT std_logic;
prog_empty => PROG_EMPTY, -- : OUT std_logic;
sbiterr => SBITERR, -- : OUT std_logic;
dbiterr => DBITERR, -- : OUT std_logic
wr_rst_busy => WR_RST_BUSY,
rd_rst_busy => RD_RST_BUSY,
-- AXI Global Signal
m_aclk => '0', -- : IN std_logic := '0';
s_aclk => '0', -- : IN std_logic := '0';
s_aresetn => '0', -- : IN std_logic := '0';
m_aclk_en => '0', -- : IN std_logic := '0';
s_aclk_en => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Slave Write Channel (write side)
s_axi_awid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awaddr => "00000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlen => "00000000", --(others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awsize => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awburst => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlock => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awcache => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awprot => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awqos => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awregion => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awvalid => '0', -- : IN std_logic := '0';
s_axi_awready => S_AXI_AWREADY, -- : OUT std_logic;
s_axi_wid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wstrb => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wlast => '0', -- : IN std_logic := '0';
s_axi_wuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wvalid => '0', -- : IN std_logic := '0';
s_axi_wready => S_AXI_WREADY, -- : OUT std_logic;
s_axi_bid => S_AXI_BID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_bresp => S_AXI_BRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_buser => S_AXI_BUSER, -- : OUT std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0);
s_axi_bvalid => S_AXI_BVALID, -- : OUT std_logic;
s_axi_bready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Write Channel (Read side)
m_axi_awid => M_AXI_AWID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_awaddr => M_AXI_AWADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_awlen => M_AXI_AWLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_awsize => M_AXI_AWSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awburst => M_AXI_AWBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awlock => M_AXI_AWLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awcache => M_AXI_AWCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awprot => M_AXI_AWPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awqos => M_AXI_AWQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awregion => M_AXI_AWREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awuser => M_AXI_AWUSER, -- : OUT std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0);
m_axi_awvalid => M_AXI_AWVALID, -- : OUT std_logic;
m_axi_awready => '0', -- : IN std_logic := '0';
m_axi_wid => M_AXI_WID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_wdata => M_AXI_WDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
m_axi_wstrb => M_AXI_WSTRB, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0);
m_axi_wlast => M_AXI_WLAST, -- : OUT std_logic;
m_axi_wuser => M_AXI_WUSER, -- : OUT std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0);
m_axi_wvalid => M_AXI_WVALID, -- : OUT std_logic;
m_axi_wready => '0', -- : IN std_logic := '0';
m_axi_bid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_buser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bvalid => '0', -- : IN std_logic := '0';
m_axi_bready => M_AXI_BREADY, -- : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
s_axi_arid => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_araddr => "00000000000000000000000000000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlen => "00000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arsize => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arburst => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlock => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arcache => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arprot => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arqos => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arregion => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_aruser => "0", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arvalid => '0', -- : IN std_logic := '0';
s_axi_arready => S_AXI_ARREADY, -- : OUT std_logic;
s_axi_rid => S_AXI_RID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
s_axi_rdata => S_AXI_RDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
s_axi_rresp => S_AXI_RRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_rlast => S_AXI_RLAST, -- : OUT std_logic;
s_axi_ruser => S_AXI_RUSER, -- : OUT std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0);
s_axi_rvalid => S_AXI_RVALID, -- : OUT std_logic;
s_axi_rready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Read Channel (Read side)
m_axi_arid => M_AXI_ARID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_araddr => M_AXI_ARADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_arlen => M_AXI_ARLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_arsize => M_AXI_ARSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arburst => M_AXI_ARBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arlock => M_AXI_ARLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arcache => M_AXI_ARCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arprot => M_AXI_ARPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arqos => M_AXI_ARQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arregion => M_AXI_ARREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_aruser => M_AXI_ARUSER, -- : OUT std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0);
m_axi_arvalid => M_AXI_ARVALID, -- : OUT std_logic;
m_axi_arready => '0', -- : IN std_logic := '0';
m_axi_rid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rlast => '0', -- : IN std_logic := '0';
m_axi_ruser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rvalid => '0', -- : IN std_logic := '0';
m_axi_rready => M_AXI_RREADY, -- : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
s_axis_tvalid => '0', -- : IN std_logic := '0';
s_axis_tready => S_AXIS_TREADY, -- : OUT std_logic;
s_axis_tdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tstrb => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tkeep => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tlast => '0', -- : IN std_logic := '0';
s_axis_tid => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tdest => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tuser => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
-- AXI Streaming Master Signals (Read side)
m_axis_tvalid => M_AXIS_TVALID, -- : OUT std_logic;
m_axis_tready => '0', -- : IN std_logic := '0';
m_axis_tdata => M_AXIS_TDATA, -- : OUT std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0);
m_axis_tstrb => M_AXIS_TSTRB, -- : OUT std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0);
m_axis_tkeep => M_AXIS_TKEEP, -- : OUT std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0);
m_axis_tlast => M_AXIS_TLAST, -- : OUT std_logic;
m_axis_tid => M_AXIS_TID, -- : OUT std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0);
m_axis_tdest => M_AXIS_TDEST, -- : OUT std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0);
m_axis_tuser => M_AXIS_TUSER, -- : OUT std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
axi_aw_injectsbiterr => '0', -- : IN std_logic := '0';
axi_aw_injectdbiterr => '0', -- : IN std_logic := '0';
axi_aw_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_data_count => AXI_AW_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_wr_data_count => AXI_AW_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_rd_data_count => AXI_AW_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_sbiterr => AXI_AW_SBITERR, -- : OUT std_logic;
axi_aw_dbiterr => AXI_AW_DBITERR, -- : OUT std_logic;
axi_aw_overflow => AXI_AW_OVERFLOW, -- : OUT std_logic;
axi_aw_underflow => AXI_AW_UNDERFLOW, -- : OUT std_logic;
axi_aw_prog_full => AXI_AW_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_aw_prog_empty => AXI_AW_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Data Channel Signals
axi_w_injectsbiterr => '0', -- : IN std_logic := '0';
axi_w_injectdbiterr => '0', -- : IN std_logic := '0';
axi_w_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_data_count => AXI_W_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_wr_data_count => AXI_W_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_rd_data_count => AXI_W_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_sbiterr => AXI_W_SBITERR, -- : OUT std_logic;
axi_w_dbiterr => AXI_W_DBITERR, -- : OUT std_logic;
axi_w_overflow => AXI_W_OVERFLOW, -- : OUT std_logic;
axi_w_underflow => AXI_W_UNDERFLOW, -- : OUT std_logic;
axi_w_prog_full => AXI_W_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_w_prog_empty => AXI_W_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Response Channel Signals
axi_b_injectsbiterr => '0', -- : IN std_logic := '0';
axi_b_injectdbiterr => '0', -- : IN std_logic := '0';
axi_b_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_data_count => AXI_B_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_wr_data_count => AXI_B_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_rd_data_count => AXI_B_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_sbiterr => AXI_B_SBITERR, -- : OUT std_logic;
axi_b_dbiterr => AXI_B_DBITERR, -- : OUT std_logic;
axi_b_overflow => AXI_B_OVERFLOW, -- : OUT std_logic;
axi_b_underflow => AXI_B_UNDERFLOW, -- : OUT std_logic;
axi_b_prog_full => AXI_B_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_b_prog_empty => AXI_B_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Address Channel Signals
axi_ar_injectsbiterr => '0', -- : IN std_logic := '0';
axi_ar_injectdbiterr => '0', -- : IN std_logic := '0';
axi_ar_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_data_count => AXI_AR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_wr_data_count => AXI_AR_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_rd_data_count => AXI_AR_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_sbiterr => AXI_AR_SBITERR, -- : OUT std_logic;
axi_ar_dbiterr => AXI_AR_DBITERR, -- : OUT std_logic;
axi_ar_overflow => AXI_AR_OVERFLOW, -- : OUT std_logic;
axi_ar_underflow => AXI_AR_UNDERFLOW, -- : OUT std_logic;
axi_ar_prog_full => AXI_AR_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_ar_prog_empty => AXI_AR_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Data Channel Signals
axi_r_injectsbiterr => '0', -- : IN std_logic := '0';
axi_r_injectdbiterr => '0', -- : IN std_logic := '0';
axi_r_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_data_count => AXI_R_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_wr_data_count => AXI_R_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_rd_data_count => AXI_R_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_sbiterr => AXI_R_SBITERR, -- : OUT std_logic;
axi_r_dbiterr => AXI_R_DBITERR, -- : OUT std_logic;
axi_r_overflow => AXI_R_OVERFLOW, -- : OUT std_logic;
axi_r_underflow => AXI_R_UNDERFLOW, -- : OUT std_logic;
axi_r_prog_full => AXI_R_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_r_prog_empty => AXI_R_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Streaming FIFO Related Signals
axis_injectsbiterr => '0', -- : IN std_logic := '0';
axis_injectdbiterr => '0', -- : IN std_logic := '0';
axis_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_data_count => AXIS_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_wr_data_count => AXIS_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_rd_data_count => AXIS_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_sbiterr => AXIS_SBITERR, -- : OUT std_logic;
axis_dbiterr => AXIS_DBITERR, -- : OUT std_logic;
axis_overflow => AXIS_OVERFLOW, -- : OUT std_logic;
axis_underflow => AXIS_UNDERFLOW, -- : OUT std_logic
axis_prog_full => AXIS_PROG_FULL, -- : OUT STD_LOGIC := '0';
axis_prog_empty => AXIS_PROG_EMPTY -- : OUT STD_LOGIC := '1';
);
end generate V6_S6_AND_LATER;
end generate USE_2N_DEPTH;
-----------------------------------------------------------------------
end implementation;
|
mit
|
UVVM/UVVM_All
|
bitvis_vip_uart/tb/uvvm_demo_th.vhd
|
1
|
11085
|
--================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
----------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
library uvvm_util;
context uvvm_util.uvvm_util_context; -- t_channel (RX/TX)
library bitvis_vip_sbi;
context bitvis_vip_sbi.vvc_context;
library bitvis_vip_uart;
context bitvis_vip_uart.vvc_context;
use bitvis_vip_uart.monitor_cmd_pkg.all;
library bitvis_uart;
library bitvis_vip_clock_generator;
library bitvis_vip_scoreboard;
use bitvis_vip_scoreboard.generic_sb_support_pkg.all;
-- Test harness entity
entity uvvm_demo_th is
generic (
-- Clock and bit period settings
GC_CLK_PERIOD : time := 10 ns;
GC_BIT_PERIOD : time := 16 * GC_CLK_PERIOD;
-- DUT addresses
GC_ADDR_RX_DATA : unsigned(2 downto 0) := "000";
GC_ADDR_RX_DATA_VALID : unsigned(2 downto 0) := "001";
GC_ADDR_TX_DATA : unsigned(2 downto 0) := "010";
GC_ADDR_TX_READY : unsigned(2 downto 0) := "011";
-- Activity watchdog setting
GC_ACTIVITY_WATCHDOG_TIMEOUT : time := 50 * GC_BIT_PERIOD
);
end entity uvvm_demo_th;
-- Test harness architecture
architecture struct of uvvm_demo_th is
-- VVC idx
constant C_SBI_VVC : natural := 1;
constant C_UART_TX_VVC : natural := 1;
constant C_UART_RX_VVC : natural := 1;
constant C_CLOCK_GEN_VVC : natural := 1;
-- UART if
constant C_DATA_WIDTH : natural := 8;
constant C_ADDR_WIDTH : natural := 3;
-- Clock and reset signals
signal clk : std_logic := '0';
signal arst : std_logic := '0';
-- SBI VVC signals
signal cs : std_logic;
signal addr : unsigned(2 downto 0);
signal wr : std_logic;
signal rd : std_logic;
signal wdata : std_logic_vector(7 downto 0);
signal rdata : std_logic_vector(7 downto 0);
signal ready : std_logic;
-- UART VVC signals
signal uart_vvc_rx : std_logic := '1';
signal uart_vvc_tx : std_logic := '1';
-- UART Monitor
constant C_UART_MONITOR_INTERFACE_CONFIG : t_uart_interface_config := (
bit_time => GC_BIT_PERIOD,
num_data_bits => 8,
parity => PARITY_ODD,
num_stop_bits => STOP_BITS_ONE
);
constant C_UART_MONITOR_CONFIG : t_uart_monitor_config := (
scope_name => (1 to 12 => "UART Monitor", others => NUL),
msg_id_panel => C_UART_MONITOR_MSG_ID_PANEL_DEFAULT,
interface_config => C_UART_MONITOR_INTERFACE_CONFIG,
transaction_display_time => 0 ns
);
begin
-----------------------------------------------------------------------------
-- Instantiate the concurrent procedure that initializes UVVM
-----------------------------------------------------------------------------
i_ti_uvvm_engine : entity uvvm_vvc_framework.ti_uvvm_engine;
-----------------------------------------------------------------------------
-- Instantiate DUT
-----------------------------------------------------------------------------
i_uart: entity bitvis_uart.uart
port map (
-- DSP interface and general control signals
clk => clk,
arst => arst,
-- CPU interface
cs => cs,
addr => addr,
wr => wr,
rd => rd,
wdata => wdata,
rdata => rdata,
-- UART signals
rx_a => uart_vvc_tx,
tx => uart_vvc_rx
);
-----------------------------------------------------------------------------
-- SBI VVC
-----------------------------------------------------------------------------
i1_sbi_vvc: entity bitvis_vip_sbi.sbi_vvc
generic map(
GC_ADDR_WIDTH => C_ADDR_WIDTH,
GC_DATA_WIDTH => C_DATA_WIDTH,
GC_INSTANCE_IDX => C_SBI_VVC
)
port map(
clk => clk,
sbi_vvc_master_if.cs => cs,
sbi_vvc_master_if.rena => rd,
sbi_vvc_master_if.wena => wr,
sbi_vvc_master_if.addr => addr,
sbi_vvc_master_if.wdata => wdata,
sbi_vvc_master_if.ready => ready,
sbi_vvc_master_if.rdata => rdata
);
-----------------------------------------------------------------------------
-- UART VVC
-----------------------------------------------------------------------------
i1_uart_vvc: entity bitvis_vip_uart.uart_vvc
generic map(
GC_INSTANCE_IDX => 1
)
port map(
uart_vvc_rx => uart_vvc_rx,
uart_vvc_tx => uart_vvc_tx
);
-- Static '1' ready signal for the SBI VVC
ready <= '1';
-----------------------------------------------------------------------------
-- Monitor - UART
--
-- Monitor and validate UART transactions.
--
-----------------------------------------------------------------------------
i1_uart_monitor : entity bitvis_vip_uart.uart_monitor
generic map(
GC_INSTANCE_IDX => 1,
GC_MONITOR_CONFIG => C_UART_MONITOR_CONFIG
)
port map(
uart_dut_tx => uart_vvc_rx,
uart_dut_rx => uart_vvc_tx
);
-----------------------------------------------------------------------------
-- Activity Watchdog
--
-- Monitor VVC activity and alert if no VVC activity is
-- detected before timeout.
--
-----------------------------------------------------------------------------
p_activity_watchdog:
activity_watchdog(timeout => GC_ACTIVITY_WATCHDOG_TIMEOUT,
num_exp_vvc => 4);
-----------------------------------------------------------------------------
-- Model
--
-- Subscribe to SBI and UART transaction infos, and send to Scoreboard or
-- send VVC commands based on transaction info content.
--
-----------------------------------------------------------------------------
p_model: process
-- SBI transaction info
alias sbi_vvc_transaction_info_trigger : std_logic is
global_sbi_vvc_transaction_trigger(C_SBI_VVC);
alias sbi_vvc_transaction_info : bitvis_vip_sbi.transaction_pkg.t_transaction_group is
shared_sbi_vvc_transaction_info(C_SBI_VVC);
-- UART transaction info
alias uart_rx_transaction_info_trigger : std_logic is
global_uart_vvc_transaction_trigger(RX, C_UART_RX_VVC);
alias uart_rx_transaction_info : bitvis_vip_uart.transaction_pkg.t_transaction_group is
shared_uart_vvc_transaction_info(RX, C_UART_RX_VVC);
alias uart_tx_transaction_info_trigger : std_logic is
global_uart_vvc_transaction_trigger(TX, C_UART_TX_VVC);
alias uart_tx_transaction_info : bitvis_vip_uart.transaction_pkg.t_transaction_group is
shared_uart_vvc_transaction_info(TX, C_UART_TX_VVC);
begin
while true loop
-- Wait for transaction info trigger
wait until (sbi_vvc_transaction_info_trigger = '1') or (uart_rx_transaction_info_trigger = '1') or (uart_tx_transaction_info_trigger = '1');
-------------------------------
-- SBI transaction info
-------------------------------
if sbi_vvc_transaction_info_trigger'event then
case sbi_vvc_transaction_info.bt.operation is
when WRITE =>
-- add to UART scoreboard
UART_VVC_SB.add_expected(sbi_vvc_transaction_info.bt.data(C_DATA_WIDTH-1 downto 0));
when READ =>
null;
when others =>
null;
end case;
end if;
-------------------------------
-- UART RX transaction info
-------------------------------
if uart_rx_transaction_info_trigger'event then
-- Send to SB is handled by RX VVC.
null;
end if;
-------------------------------
-- UART TX transaction
-------------------------------
if uart_tx_transaction_info_trigger'event then
case uart_tx_transaction_info.bt.operation is
when TRANSMIT =>
-- Check if transaction is intended valid / free of error
if (uart_tx_transaction_info.bt.error_info.parity_bit_error = false) and
(uart_tx_transaction_info.bt.error_info.stop_bit_error = false) then
-- Add to SBI scoreboard
SBI_VVC_SB.add_expected(pad_sbi_sb(uart_tx_transaction_info.bt.data(C_DATA_WIDTH-1 downto 0)));
-- Wait for UART Transmit to finish before SBI VVC start
insert_delay(SBI_VVCT, 1, 12*GC_BIT_PERIOD, "Wait for UART TX to finish");
-- Request SBI Read
sbi_read(SBI_VVCT, 1, GC_ADDR_RX_DATA, TO_SB, "SBI_READ");
end if;
when others =>
null;
end case;
end if;
end loop;
wait;
end process p_model;
-----------------------------------------------------------------------------
-- Clock Generator VVC
-----------------------------------------------------------------------------
i_clock_generator_vvc : entity bitvis_vip_clock_generator.clock_generator_vvc
generic map(
GC_INSTANCE_IDX => C_CLOCK_GEN_VVC,
GC_CLOCK_NAME => "Clock",
GC_CLOCK_PERIOD => GC_CLK_PERIOD,
GC_CLOCK_HIGH_TIME => GC_CLK_PERIOD / 2
)
port map(
clk => clk
);
-----------------------------------------------------------------------------
-- Reset
-----------------------------------------------------------------------------
-- Toggle the reset after 5 clock periods
p_arst: arst <= '1', '0' after 5 *GC_CLK_PERIOD;
end struct;
|
mit
|
UVVM/UVVM_All
|
uvvm_vvc_framework/src/ti_vvc_framework_support_pkg.vhd
|
1
|
40949
|
--================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
----------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library std;
use std.textio.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_protected_types_pkg.all;
package ti_vvc_framework_support_pkg is
--constant C_VVC_NAME_MAX_LENGTH : natural := 20;
constant C_VVC_NAME_MAX_LENGTH : natural := C_MAX_VVC_NAME_LENGTH;
------------------------------------------------------------------------
-- Common support types for UVVM
------------------------------------------------------------------------
type t_immediate_or_queued is (NO_command_type, IMMEDIATE, QUEUED);
type t_flag_record is record
set : std_logic;
reset : std_logic;
is_active : std_logic;
end record;
type t_uvvm_state is (IDLE, PHASE_A, PHASE_B, INIT_COMPLETED);
type t_lastness is (LAST, NOT_LAST);
type t_broadcastable_cmd is (NO_CMD, ENABLE_LOG_MSG, DISABLE_LOG_MSG, FLUSH_COMMAND_QUEUE, INSERT_DELAY, AWAIT_COMPLETION, TERMINATE_CURRENT_COMMAND);
constant C_BROADCAST_CMD_STRING_MAX_LENGTH : natural := 300;
type t_vvc_broadcast_cmd_record is record
operation : t_broadcastable_cmd;
msg_id : t_msg_id;
msg : string(1 to C_BROADCAST_CMD_STRING_MAX_LENGTH);
proc_call : string(1 to C_BROADCAST_CMD_STRING_MAX_LENGTH);
quietness : t_quietness;
delay : time;
timeout : time;
gen_integer : integer;
end record;
constant C_VVC_BROADCAST_CMD_DEFAULT : t_vvc_broadcast_cmd_record := (
operation => NO_CMD,
msg_id => NO_ID,
msg => (others => NUL),
proc_call => (others => NUL),
quietness => NON_QUIET,
delay => 0 ns,
timeout => 0 ns,
gen_integer => -1
);
------------------------------------------------------------------------
-- Common signals for acknowledging a pending command
------------------------------------------------------------------------
shared variable shared_vvc_broadcast_cmd : t_vvc_broadcast_cmd_record := C_VVC_BROADCAST_CMD_DEFAULT;
signal VVC_BROADCAST : std_logic := 'L';
------------------------------------------------------------------------
-- Common signals for triggering VVC activity in central VVC register
------------------------------------------------------------------------
signal global_trigger_vvc_activity_register : std_logic := 'L';
------------------------------------------------------------------------
-- Common signal for signalling between VVCs, used during await_any_completion()
-- Default (when not active): Z
-- Awaiting: 1:
-- Completed: 0
-- This signal is a vector to support multiple sequencers calling await_any_completion simultaneously:
-- - When calling await_any_completion, each sequencer specifies which bit in this global signal the VVCs shall use.
------------------------------------------------------------------------
signal global_awaiting_completion : std_logic_vector(C_MAX_NUM_SEQUENCERS-1 downto 0); -- ACK on global triggers
------------------------------------------------------------------------
-- Shared variables for UVVM framework
------------------------------------------------------------------------
shared variable shared_cmd_idx : integer := 0;
shared variable shared_uvvm_state : t_uvvm_state := IDLE;
-------------------------------------------
-- flag_handler
-------------------------------------------
-- Flag handler is a general flag/semaphore handling mechanism between two separate processes/threads
-- The idea is to allow one process to set a flag and another to reset it. The flag may then be used by both - or others
-- May be used for a message from process 1 to process 2 with acknowledge; - like do-something & done, or valid & ack
procedure flag_handler(
signal flag : inout t_flag_record
);
-------------------------------------------
-- set_flag
-------------------------------------------
-- Sets reset and is_active to 'Z' and pulses set_flag
procedure set_flag(
signal flag : inout t_flag_record
);
-------------------------------------------
-- reset_flag
-------------------------------------------
-- Sets set and is_active to 'Z' and pulses reset_flag
procedure reset_flag(
signal flag : inout t_flag_record
);
-------------------------------------------
-- await_uvvm_initialization
-------------------------------------------
-- Waits until uvvm has been initialized
procedure await_uvvm_initialization(
constant dummy : in t_void
);
-------------------------------------------
-- format_command_idx
-------------------------------------------
-- Converts the command index to string, enclused by
-- C_CMD_IDX_PREFIX and C_CMD_IDX_SUFFIX
impure function format_command_idx(
command_idx : integer
) return string;
--***********************************************
-- BROADCAST COMMANDS
--***********************************************
-------------------------------------------
-- enable_log_msg (Broadcast)
-------------------------------------------
-- Enables a log message for all VVCs
procedure enable_log_msg(
signal VVC_BROADCAST : inout std_logic;
constant msg_id : in t_msg_id;
constant msg : in string := "";
constant quietness : in t_quietness := NON_QUIET;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT
);
-------------------------------------------
-- disable_log_msg (Broadcast)
-------------------------------------------
-- Disables a log message for all VVCs
procedure disable_log_msg(
signal VVC_BROADCAST : inout std_logic;
constant msg_id : in t_msg_id;
constant msg : in string := "";
constant quietness : in t_quietness := NON_QUIET;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT
);
-------------------------------------------
-- flush_command_queue (Broadcast)
-------------------------------------------
-- Flushes the command queue for all VVCs
procedure flush_command_queue(
signal VVC_BROADCAST : inout std_logic;
constant msg : in string := "";
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT
);
-------------------------------------------
-- insert_delay (Broadcast)
-------------------------------------------
-- Inserts delay into all VVCs (specified as number of clock cycles)
procedure insert_delay(
signal VVC_BROADCAST : inout std_logic;
constant delay : in natural; -- in clock cycles
constant msg : in string := "";
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT
);
-------------------------------------------
-- insert_delay (Broadcast)
-------------------------------------------
-- Inserts delay into all VVCs (specified as time)
procedure insert_delay(
signal VVC_BROADCAST : inout std_logic;
constant delay : in time;
constant msg : in string := "";
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT
);
-------------------------------------------
-- await_completion (Broadcast)
-------------------------------------------
-- Wait for all VVCs to finish (specified as time)
procedure await_completion(
signal VVC_BROADCAST : inout std_logic;
constant timeout : in time;
constant msg : in string := "";
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT
);
-------------------------------------------
-- terminate_current_command (Broadcast)
-------------------------------------------
-- terminates all current tasks
procedure terminate_current_command(
signal VVC_BROADCAST : inout std_logic;
constant msg : in string := "";
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT
);
-------------------------------------------
-- terminate_all_commands (Broadcast)
-------------------------------------------
-- terminates all tasks
procedure terminate_all_commands(
signal VVC_BROADCAST : inout std_logic;
constant msg : in string := "";
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT
);
-------------------------------------------
-- transmit_broadcast
-------------------------------------------
-- Common broadcast transmission routine
procedure transmit_broadcast(
signal VVC_BROADCAST : inout std_logic;
constant operation : in t_broadcastable_cmd;
constant proc_call : in string;
constant msg_id : in t_msg_id;
constant msg : in string := "";
constant quietness : in t_quietness := NON_QUIET;
constant delay : in time := 0 ns;
constant delay_int : in integer := -1;
constant timeout : in time := std.env.resolution_limit;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT
);
-------------------------------------------
-- get_scope_for_log
-------------------------------------------
-- Returns a string with length <= C_LOG_SCOPE_WIDTH.
-- Inputs vvc_name and channel are truncated to match C_LOG_SCOPE_WIDTH if to long.
-- An alert is issued if C_MINIMUM_VVC_NAME_SCOPE_WIDTH and C_MINIMUM_CHANNEL_SCOPE_WIDTH
-- are to long relative to C_LOG_SCOPE_WIDTH.
impure function get_scope_for_log(
constant vvc_name : string;
constant instance_idx : natural;
constant channel : t_channel
) return string;
-------------------------------------------
-- get_scope_for_log
-------------------------------------------
-- Returns a string with length <= C_LOG_SCOPE_WIDTH.
-- Input vvc_name is truncated to match C_LOG_SCOPE_WIDTH if to long.
-- An alert is issued if C_MINIMUM_VVC_NAME_SCOPE_WIDTH
-- is to long relative to C_LOG_SCOPE_WIDTH.
impure function get_scope_for_log(
constant vvc_name : string;
constant instance_idx : natural
) return string;
-------------------------------------------
-- await_completion
-------------------------------------------
-- Awaits completion of any VVC in the list or until timeout.
procedure await_completion(
constant vvc_select : in t_vvc_select;
variable vvc_info_list : inout t_vvc_info_list;
constant timeout : in time;
constant list_action : in t_list_action := CLEAR_LIST;
constant msg : in string := "";
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT
);
-- Awaits completion of all the VVCs in the activity register or until timeout.
procedure await_completion(
constant vvc_select : in t_vvc_select;
constant timeout : in time;
constant list_action : in t_list_action := CLEAR_LIST;
constant msg : in string := "";
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT
);
-- ============================================================================
-- Activity Watchdog
-- ============================================================================
procedure activity_watchdog(
constant num_exp_vvc : natural;
constant timeout : time;
constant alert_level : t_alert_level := TB_ERROR;
constant msg : string := "Activity_Watchdog"
);
-- ============================================================================
-- VVC Activity Register
-- ============================================================================
shared variable shared_vvc_activity_register : t_vvc_activity;
-- ============================================================================
-- Hierarchical VVC (HVVC)
-- ============================================================================
type t_vvc_operation is (TRANSMIT, RECEIVE); -- Type of operation to be executed by the VVC
type t_direction is (TRANSMIT, RECEIVE); -- Direction of the interface (used by the IF field config)
type t_field_position is (FIRST, MIDDLE, LAST, FIRST_AND_LAST); -- Position of a field within a packet
type t_hvvc_to_bridge is record
trigger : boolean; -- Trigger signal
operation : t_vvc_operation; -- Operation of the VVC
num_data_words : positive; -- Number of data words transferred
data_words : t_slv_array; -- Data sent to the VVC
dut_if_field_idx : natural; -- Index of the interface field
dut_if_field_pos : t_field_position; -- Position of the interface field within the packet
msg_id_panel : t_msg_id_panel; -- Message ID panel of the HVVC
end record;
type t_bridge_to_hvvc is record
trigger : boolean; -- Trigger signal
data_words : t_slv_array; -- Data received from the VVC
end record;
type t_dut_if_field_config is record
dut_address : unsigned; -- Address of the DUT IF field
dut_address_increment : integer; -- Incrementation of the address on each access
data_width : positive; -- Width of the data per transfer
use_field : boolean; -- Used by the HVVC to send/request fields to/from the bridge or ignore them when not applicable
field_description : string; -- Description of the DUT IF field
end record;
constant C_DUT_IF_FIELD_CONFIG_DEFAULT : t_dut_if_field_config(dut_address(0 downto 0)) := (
dut_address => (others => '0'),
dut_address_increment => 0,
data_width => 8,
use_field => true,
field_description => "default");
type t_dut_if_field_config_array is array (natural range <>) of t_dut_if_field_config;
type t_dut_if_field_config_direction_array is array (t_direction range <>) of t_dut_if_field_config_array;
constant C_DUT_IF_FIELD_CONFIG_DIRECTION_ARRAY_DEFAULT :
t_dut_if_field_config_direction_array(t_direction'low to t_direction'high)(0 to 0)(dut_address(0 downto 0), field_description(1 to 7))
:= (others => (others => C_DUT_IF_FIELD_CONFIG_DEFAULT));
end package ti_vvc_framework_support_pkg;
package body ti_vvc_framework_support_pkg is
------------------------------------------------------------------------
--
------------------------------------------------------------------------
-- Flag handler is a general flag/semaphore handling mechanism between two separate processes/threads
-- The idea is to allow one process to set a flag and another to reset it. The flag may then be used by both - or others
-- May be used for a message from process 1 to process 2 with acknowledge; - like do-something & done, or valid & ack
procedure flag_handler(
signal flag : inout t_flag_record
) is
begin
flag.reset <= 'Z';
flag.set <= 'Z';
flag.is_active <= '0';
wait until flag.set = '1';
flag.is_active <= '1';
wait until flag.reset = '1';
flag.is_active <= '0';
end procedure;
procedure set_flag(
signal flag : inout t_flag_record
) is
begin
flag.reset <= 'Z';
flag.is_active <= 'Z';
gen_pulse(flag.set, 0 ns, "set flag", C_TB_SCOPE_DEFAULT, ID_NEVER);
end procedure;
procedure reset_flag(
signal flag : inout t_flag_record
) is
begin
flag.set <= 'Z';
flag.is_active <= 'Z';
gen_pulse(flag.reset, 0 ns, "reset flag", C_TB_SCOPE_DEFAULT, ID_NEVER);
end procedure;
-- This procedure checks the shared_uvvm_state on each delta cycle
procedure await_uvvm_initialization(
constant dummy : in t_void) is
begin
while (shared_uvvm_state /= INIT_COMPLETED) loop
wait for 0 ns;
end loop;
end procedure;
impure function format_command_idx(
command_idx : integer
) return string is
begin
return C_CMD_IDX_PREFIX & to_string(command_idx) & C_CMD_IDX_SUFFIX;
end;
procedure enable_log_msg(
signal VVC_BROADCAST : inout std_logic;
constant msg_id : in t_msg_id;
constant msg : in string := "";
constant quietness : in t_quietness := NON_QUIET;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT
) is
constant proc_name : string := "enable_log_msg";
constant proc_call : string := proc_name & "(VVC_BROADCAST, " & to_upper(to_string(msg_id)) & ")";
begin
transmit_broadcast(VVC_BROADCAST, ENABLE_LOG_MSG, proc_call, msg_id, msg, quietness, scope => scope);
end procedure;
procedure disable_log_msg(
signal VVC_BROADCAST : inout std_logic;
constant msg_id : in t_msg_id;
constant msg : in string := "";
constant quietness : in t_quietness := NON_QUIET;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT
) is
constant proc_name : string := "disable_log_msg";
constant proc_call : string := proc_name & "(VVC_BROADCAST, " & to_upper(to_string(msg_id)) & ")";
begin
transmit_broadcast(VVC_BROADCAST, DISABLE_LOG_MSG, proc_call, msg_id, msg, quietness, scope => scope);
end procedure;
procedure flush_command_queue(
signal VVC_BROADCAST : inout std_logic;
constant msg : in string := "";
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT
) is
constant proc_name : string := "flush_command_queue";
constant proc_call : string := proc_name & "(VVC_BROADCAST)";
begin
transmit_broadcast(VVC_BROADCAST, FLUSH_COMMAND_QUEUE, proc_call, NO_ID, msg, scope => scope);
end procedure;
procedure insert_delay(
signal VVC_BROADCAST : inout std_logic;
constant delay : in natural; -- in clock cycles
constant msg : in string := "";
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT
) is
constant proc_name : string := "insert_delay";
constant proc_call : string := proc_name & "(VVC_BROADCAST, " & to_string(delay) & ")";
begin
transmit_broadcast(VVC_BROADCAST, FLUSH_COMMAND_QUEUE, proc_call, NO_ID, msg, NON_QUIET, 0 ns, delay, scope => scope);
end procedure;
procedure insert_delay(
signal VVC_BROADCAST : inout std_logic;
constant delay : in time;
constant msg : in string := "";
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT
) is
constant proc_name : string := "insert_delay";
constant proc_call : string := proc_name & "(VVC_BROADCAST, " & to_string(delay) & ")";
begin
transmit_broadcast(VVC_BROADCAST, INSERT_DELAY, proc_call, NO_ID, msg, NON_QUIET, delay, scope => scope);
end procedure;
procedure await_completion(
signal VVC_BROADCAST : inout std_logic;
constant timeout : in time;
constant msg : in string := "";
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT
) is
constant proc_name : string := "await_completion";
constant proc_call : string := proc_name & "(VVC_BROADCAST)";
begin
log(ID_OLD_AWAIT_COMPLETION, "Procedure is not supporting the VVC activity register.", scope);
transmit_broadcast(VVC_BROADCAST, AWAIT_COMPLETION, proc_call, NO_ID, msg, NON_QUIET, 0 ns, -1, timeout, scope);
end procedure;
procedure terminate_current_command(
signal VVC_BROADCAST : inout std_logic;
constant msg : in string := "";
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT
) is
constant proc_name : string := "terminate_current_command";
constant proc_call : string := proc_name & "(VVC_BROADCAST)";
begin
transmit_broadcast(VVC_BROADCAST, TERMINATE_CURRENT_COMMAND, proc_call, NO_ID, msg, scope => scope);
end procedure;
procedure terminate_all_commands(
signal VVC_BROADCAST : inout std_logic;
constant msg : in string := "";
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT
) is
constant proc_name : string := "terminate_all_commands";
constant proc_call : string := proc_name & "(VVC_BROADCAST)";
begin
flush_command_queue(VVC_BROADCAST, msg);
terminate_current_command(VVC_BROADCAST, msg, scope => scope);
end procedure;
procedure transmit_broadcast(
signal VVC_BROADCAST : inout std_logic;
constant operation : in t_broadcastable_cmd;
constant proc_call : in string;
constant msg_id : in t_msg_id;
constant msg : in string := "";
constant quietness : in t_quietness := NON_QUIET;
constant delay : in time := 0 ns;
constant delay_int : in integer := -1;
constant timeout : in time := std.env.resolution_limit;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT
) is
begin
await_semaphore_in_delta_cycles(protected_semaphore);
-- Increment shared_cmd_idx. It is protected by the protected_semaphore and only one sequencer can access the variable at a time.
shared_cmd_idx := shared_cmd_idx + 1;
if global_show_msg_for_uvvm_cmd then
log(ID_UVVM_SEND_CMD, to_string(proc_call) & ": " & add_msg_delimiter(to_string(msg))
& format_command_idx(shared_cmd_idx), scope);
else
log(ID_UVVM_SEND_CMD, to_string(proc_call)
& format_command_idx(shared_cmd_idx), scope);
end if;
shared_vvc_broadcast_cmd.operation := operation;
shared_vvc_broadcast_cmd.msg_id := msg_id;
shared_vvc_broadcast_cmd.msg := (others => NUL); -- default empty
shared_vvc_broadcast_cmd.msg(1 to msg'length) := msg;
shared_vvc_broadcast_cmd.quietness := quietness;
shared_vvc_broadcast_cmd.timeout := timeout;
shared_vvc_broadcast_cmd.delay := delay;
shared_vvc_broadcast_cmd.gen_integer := delay_int;
shared_vvc_broadcast_cmd.proc_call := (others => NUL); -- default empty
shared_vvc_broadcast_cmd.proc_call(1 to proc_call'length) := proc_call;
if VVC_BROADCAST /= 'L' then
-- a VVC is waiting for example in await_completion
wait until VVC_BROADCAST = 'L';
end if;
-- Trigger the broadcast
VVC_BROADCAST <= '1';
wait for 0 ns;
-- set back to 'L' and wait until all VVCs have set it back
VVC_BROADCAST <= 'L';
wait until VVC_BROADCAST = 'L' for timeout; -- Wait for executor
if not (VVC_BROADCAST'event) and VVC_BROADCAST /= 'L' then -- Indicates timeout
tb_error("Timeout while waiting for the broadcast command to be ACK'ed", scope);
else
log(ID_UVVM_CMD_ACK, "ACK received for broadcast command" & format_command_idx(shared_cmd_idx), scope);
end if;
shared_vvc_broadcast_cmd := C_VVC_BROADCAST_CMD_DEFAULT;
wait for 0 ns;
wait for 0 ns;
wait for 0 ns;
wait for 0 ns;
wait for 0 ns;
release_semaphore(protected_semaphore);
end procedure;
impure function get_scope_for_log(
constant vvc_name : string;
constant instance_idx : natural;
constant channel : t_channel
) return string is
constant C_INSTANCE_IDX_STR : string := to_string(instance_idx);
constant C_CHANNEL_STR : string := to_upper(to_string(channel));
constant C_SCOPE_LENGTH : natural := vvc_name'length + C_INSTANCE_IDX_STR'length + C_CHANNEL_STR'length + 2; -- +2 because of the two added commas
variable v_vvc_name_truncation_value : integer;
variable v_channel_truncation_value : integer;
variable v_vvc_name_truncation_idx : integer;
variable v_channel_truncation_idx : integer;
begin
if (C_MINIMUM_VVC_NAME_SCOPE_WIDTH + C_MINIMUM_CHANNEL_SCOPE_WIDTH + C_INSTANCE_IDX_STR'length + 2) > C_LOG_SCOPE_WIDTH then -- +2 because of the two added commas
alert(TB_WARNING, "The combined width of C_MINIMUM_VVC_NAME_SCOPE_WIDTH and C_MINIMUM_CHANNEL_SCOPE_WIDTH cannot be greater than C_LOG_SCOPE_WIDTH - (number of characters in instance) - 2.", C_SCOPE);
end if;
-- If C_SCOPE_LENGTH is not greater than allowed width, return scope
if C_SCOPE_LENGTH <= C_LOG_SCOPE_WIDTH then
return vvc_name & "," & C_INSTANCE_IDX_STR & "," & C_CHANNEL_STR;
-- If C_SCOPE_LENGTH is greater than allowed width
-- Check if vvc_name is greater than minimum width to truncate
elsif vvc_name'length <= C_MINIMUM_VVC_NAME_SCOPE_WIDTH then
return vvc_name & "," & C_INSTANCE_IDX_STR & "," & C_CHANNEL_STR(1 to (C_CHANNEL_STR'length - (C_SCOPE_LENGTH-C_LOG_SCOPE_WIDTH)));
-- Check if channel is greater than minimum width to truncate
elsif C_CHANNEL_STR'length <= C_MINIMUM_CHANNEL_SCOPE_WIDTH then
return vvc_name(1 to (vvc_name'length - (C_SCOPE_LENGTH-C_LOG_SCOPE_WIDTH))) & "," & C_INSTANCE_IDX_STR & "," & C_CHANNEL_STR;
-- If both vvc_name and channel is to be truncated
else
-- Calculate linear scaling of truncation between vvc_name and channel: (a*x)/(a+b), (b*x)/(a+b)
v_vvc_name_truncation_idx := integer(round(real(vvc_name'length * (C_SCOPE_LENGTH-C_LOG_SCOPE_WIDTH)))/real(vvc_name'length + C_CHANNEL_STR'length));
v_channel_truncation_value := integer(round(real(C_CHANNEL_STR'length * (C_SCOPE_LENGTH-C_LOG_SCOPE_WIDTH)))/real(vvc_name'length + C_CHANNEL_STR'length));
-- In case division ended with .5 and both rounded up
if (v_vvc_name_truncation_idx + v_channel_truncation_value) > (C_SCOPE_LENGTH-C_LOG_SCOPE_WIDTH) then
v_channel_truncation_value := v_channel_truncation_value - 1;
end if;
-- Character index to truncate
v_vvc_name_truncation_idx := vvc_name'length - v_vvc_name_truncation_idx;
v_channel_truncation_idx := C_CHANNEL_STR'length - v_channel_truncation_value;
-- If bellow minimum name width
while v_vvc_name_truncation_idx < C_MINIMUM_VVC_NAME_SCOPE_WIDTH loop
v_vvc_name_truncation_idx := v_vvc_name_truncation_idx + 1;
v_channel_truncation_idx := v_channel_truncation_idx - 1;
end loop;
-- If bellow minimum channel width
while v_channel_truncation_idx < C_MINIMUM_CHANNEL_SCOPE_WIDTH loop
v_channel_truncation_idx := v_channel_truncation_idx + 1;
v_vvc_name_truncation_idx := v_vvc_name_truncation_idx - 1;
end loop;
return vvc_name(1 to v_vvc_name_truncation_idx) & "," & C_INSTANCE_IDX_STR & "," & C_CHANNEL_STR(1 to v_channel_truncation_idx);
end if;
end function;
impure function get_scope_for_log(
constant vvc_name : string;
constant instance_idx : natural
) return string is
constant C_INSTANCE_IDX_STR : string := to_string(instance_idx);
constant C_SCOPE_LENGTH : integer := vvc_name'length + C_INSTANCE_IDX_STR'length + 1; -- +1 because of the added comma
begin
if (C_MINIMUM_VVC_NAME_SCOPE_WIDTH + C_INSTANCE_IDX_STR'length + 1) > C_LOG_SCOPE_WIDTH then -- +1 because of the added comma
alert(TB_WARNING, "The width of C_MINIMUM_VVC_NAME_SCOPE_WIDTH cannot be greater than C_LOG_SCOPE_WIDTH - (number of characters in instance) - 1.", C_SCOPE);
end if;
-- If C_SCOPE_LENGTH is not greater than allowed width, return scope
if C_SCOPE_LENGTH <= C_LOG_SCOPE_WIDTH then
return vvc_name & "," & C_INSTANCE_IDX_STR;
-- If C_SCOPE_LENGTH is greater than allowed width truncate vvc_name
else
return vvc_name(1 to (vvc_name'length - (C_SCOPE_LENGTH-C_LOG_SCOPE_WIDTH))) & "," & C_INSTANCE_IDX_STR;
end if;
end function;
procedure await_completion(
constant vvc_select : in t_vvc_select;
variable vvc_info_list : inout t_vvc_info_list;
constant timeout : in time;
constant list_action : in t_list_action := CLEAR_LIST;
constant msg : in string := "";
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT
) is
constant proc_name : string := "await_completion";
constant proc_call : string := proc_name & "(" & to_string(vvc_select) & "," & vvc_info_list.priv_get_vvc_info_list & "," & to_string(timeout, ns) & ")";
constant proc_call_short : string := proc_name & "(" & to_string(vvc_select) & "," & to_string(timeout, ns) & ")";
constant c_index_not_found : integer := -1;
constant c_vvc_info_list_length : natural := vvc_info_list.priv_get_num_vvc_in_list;
variable v_vvc_idx_in_activity_register : t_integer_array(0 to C_MAX_TB_VVC_NUM) := (others => -1);
variable v_num_vvc_instances : natural := 0;
variable v_tot_vvc_instances : natural range 0 to C_MAX_TB_VVC_NUM:= 0;
variable v_vvc_logged : std_logic_vector(0 to C_MAX_TB_VVC_NUM-1) := (others => '0');
variable v_vvcs_completed : natural := 0;
variable v_local_cmd_idx : integer;
variable v_timestamp : time;
variable v_done : boolean := false;
variable v_first_wait : boolean := true;
variable v_list_idx : natural := 0;
variable v_proc_call : line;
begin
if vvc_select = ALL_VVCS and shared_vvc_activity_register.priv_get_num_registered_vvcs = c_vvc_info_list_length then
v_proc_call := new string'(proc_call_short);
else
v_proc_call := new string'(proc_call);
end if;
-- Increment shared_cmd_idx. It is protected by the protected_semaphore and only one sequencer can access the variable at a time.
-- Store it in a local variable since new commands might be executed from another sequencer.
await_semaphore_in_delta_cycles(protected_semaphore);
shared_cmd_idx := shared_cmd_idx + 1;
v_local_cmd_idx := shared_cmd_idx;
release_semaphore(protected_semaphore);
log(ID_AWAIT_COMPLETION, v_proc_call.all & ": " & add_msg_delimiter(msg) & "." & format_command_idx(v_local_cmd_idx), scope, shared_msg_id_panel);
-- Give a warning for incorrect use of ALL_VVCS
if vvc_select = ALL_VVCS and shared_vvc_activity_register.priv_get_num_registered_vvcs /= c_vvc_info_list_length then
alert(TB_WARNING, v_proc_call.all & add_msg_delimiter(msg) & "=> When using ALL_VVCS with a VVC list, only the VVCs from the list will be checked."
& format_command_idx(v_local_cmd_idx), scope);
end if;
-- Check that list is not empty
if c_vvc_info_list_length = 0 then
v_done := true;
end if;
-- Loop through the VVC list and get the corresponding index from the vvc activity register
for i in 0 to c_vvc_info_list_length-1 loop
if vvc_info_list.priv_get_instance(i) = ALL_INSTANCES or vvc_info_list.priv_get_channel(i) = ALL_CHANNELS then
-- Check how many instances or channels of this VVC are registered in the vvc activity register
v_num_vvc_instances := shared_vvc_activity_register.priv_get_num_registered_vvc_matches(vvc_info_list.priv_get_name(i),
vvc_info_list.priv_get_instance(i), vvc_info_list.priv_get_channel(i));
-- Get the index for every instance or channel of this VVC
for j in 0 to v_num_vvc_instances-1 loop
v_vvc_idx_in_activity_register(v_tot_vvc_instances+j) := shared_vvc_activity_register.priv_get_vvc_idx(j, vvc_info_list.priv_get_name(i),
vvc_info_list.priv_get_instance(i), vvc_info_list.priv_get_channel(i));
end loop;
else
-- Get the index for a specific VVC
v_vvc_idx_in_activity_register(v_tot_vvc_instances) := shared_vvc_activity_register.priv_get_vvc_idx(vvc_info_list.priv_get_name(i),
vvc_info_list.priv_get_instance(i), vvc_info_list.priv_get_channel(i));
v_num_vvc_instances := 0 when v_vvc_idx_in_activity_register(v_tot_vvc_instances) = c_index_not_found else 1;
end if;
-- Update the total number of VVCs in the group
v_tot_vvc_instances := v_tot_vvc_instances + v_num_vvc_instances;
-- Check if the VVC from the list is registered in the vvc activity register, otherwise clean the list and exit procedure
if v_vvc_idx_in_activity_register(v_tot_vvc_instances-v_num_vvc_instances) = c_index_not_found then
alert(TB_ERROR, v_proc_call.all & add_msg_delimiter(msg) & "=> " & vvc_info_list.priv_get_vvc_info(i) &
" does not support this procedure." & format_command_idx(v_local_cmd_idx), scope);
v_done := true;
exit;
end if;
end loop;
v_timestamp := now;
while not(v_done) loop
v_list_idx := 0;
for i in 0 to v_tot_vvc_instances-1 loop
-- Wait for the VVCs in the group to complete (INACTIVE status)
if vvc_info_list.priv_get_cmd_idx(v_list_idx) = -1 then
if shared_vvc_activity_register.priv_get_vvc_activity(v_vvc_idx_in_activity_register(i)) = INACTIVE then
if not(v_vvc_logged(i)) then
log(ID_AWAIT_COMPLETION_END, v_proc_call.all & "=> " & shared_vvc_activity_register.priv_get_vvc_info(v_vvc_idx_in_activity_register(i)) &
" finished. " & add_msg_delimiter(msg) & format_command_idx(v_local_cmd_idx), scope, shared_msg_id_panel);
v_vvc_logged(i) := '1';
v_vvcs_completed := v_vvcs_completed + 1;
end if;
if vvc_select = ANY_OF or v_vvcs_completed = v_tot_vvc_instances then
v_done := true;
end if;
end if;
-- Wait for the VVCs in the group to complete (cmd_idx completed)
else
if shared_vvc_activity_register.priv_get_vvc_last_cmd_idx_executed(v_vvc_idx_in_activity_register(i)) >= vvc_info_list.priv_get_cmd_idx(v_list_idx) then
if not(v_vvc_logged(i)) then
log(ID_AWAIT_COMPLETION_END, v_proc_call.all & "=> " & shared_vvc_activity_register.priv_get_vvc_info(v_vvc_idx_in_activity_register(i)) &
" finished. " & add_msg_delimiter(msg) & format_command_idx(v_local_cmd_idx), scope, shared_msg_id_panel);
v_vvc_logged(i) := '1';
v_vvcs_completed := v_vvcs_completed + 1;
end if;
if vvc_select = ANY_OF or v_vvcs_completed = v_tot_vvc_instances then
v_done := true;
end if;
end if;
end if;
-- Increment the vvc_info_list index (different from the v_vvc_idx_in_activity_register)
if not(vvc_info_list.priv_get_instance(v_list_idx) = ALL_INSTANCES or vvc_info_list.priv_get_channel(v_list_idx) = ALL_CHANNELS) then
v_list_idx := v_list_idx + 1;
end if;
end loop;
if not(v_done) then
if v_first_wait then
log(ID_AWAIT_COMPLETION_WAIT, v_proc_call.all & " - Pending completion. " & add_msg_delimiter(msg) & format_command_idx(v_local_cmd_idx), scope, shared_msg_id_panel);
v_first_wait := false;
end if;
-- Wait for vvc activity trigger pulse
wait on global_trigger_vvc_activity_register for timeout;
-- Check if there was a timeout
if now >= v_timestamp + timeout then
alert(TB_ERROR, v_proc_call.all & "=> Timeout. " & add_msg_delimiter(msg) & format_command_idx(v_local_cmd_idx), scope);
v_done := true;
end if;
end if;
end loop;
if list_action = CLEAR_LIST then
vvc_info_list.priv_clear_list;
log(ID_AWAIT_COMPLETION_LIST, v_proc_call.all & "=> All VVCs removed from the list. " & add_msg_delimiter(msg) &
format_command_idx(v_local_cmd_idx), scope, shared_msg_id_panel);
elsif list_action = KEEP_LIST then
log(ID_AWAIT_COMPLETION_LIST, v_proc_call.all & "=> Keeping all VVCs in the list. " & add_msg_delimiter(msg) &
format_command_idx(v_local_cmd_idx), scope, shared_msg_id_panel);
end if;
end procedure;
procedure await_completion(
constant vvc_select : in t_vvc_select;
constant timeout : in time;
constant list_action : in t_list_action := CLEAR_LIST;
constant msg : in string := "";
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT
) is
constant proc_name : string := "await_completion";
constant proc_call : string := proc_name & "(" & to_string(vvc_select) & "," & to_string(timeout, ns) & ")";
variable v_vvc_info_list : t_vvc_info_list;
begin
if vvc_select = ALL_VVCS then
-- Get all the VVCs from the vvc activity register and put them in the vvc_info_list
for i in 0 to shared_vvc_activity_register.priv_get_num_registered_vvcs-1 loop
v_vvc_info_list.add(shared_vvc_activity_register.priv_get_vvc_name(i),
shared_vvc_activity_register.priv_get_vvc_instance(i),
shared_vvc_activity_register.priv_get_vvc_channel(i));
end loop;
await_completion(vvc_select, v_vvc_info_list, timeout, list_action, msg, scope);
else
alert(TB_ERROR, proc_call & add_msg_delimiter(msg) & "=> A VVC list is required when using " & to_string(vvc_select) & ".", scope);
end if;
end procedure;
-- ============================================================================
-- Activity Watchdog
-- ============================================================================
-------------------------------------------------------------------------------
-- Activity watchdog:
-- Include this as a concurrent procedure from your testbench.
-------------------------------------------------------------------------------
procedure activity_watchdog(
constant num_exp_vvc : natural;
constant timeout : time;
constant alert_level : t_alert_level := TB_ERROR;
constant msg : string := "Activity_Watchdog"
) is
variable v_timeout : time;
begin
wait for 0 ns;
log(ID_WATCHDOG, "Starting activity watchdog , timeout=" & to_string(timeout, C_LOG_TIME_BASE) & ". " & msg);
wait for 0 ns;
-- Check if all expected VVCs are registered
if (num_exp_vvc /= shared_vvc_activity_register.priv_get_num_registered_vvcs) and (num_exp_vvc > 0) then
shared_vvc_activity_register.priv_list_registered_vvc(msg);
alert(TB_WARNING, "Number of VVCs in activity watchdog is not expected, actual=" &
to_string(shared_vvc_activity_register.priv_get_num_registered_vvcs) & ", exp=" & to_string(num_exp_vvc) & ".\n" &
"Note that leaf VVCs (e.g. channels) are counted individually. " & msg);
end if;
loop
wait on global_trigger_vvc_activity_register for timeout;
if not(global_trigger_vvc_activity_register'event) and shared_vvc_activity_register.priv_are_all_vvc_inactive then
alert(alert_level, "Activity watchdog timer ended after " & to_string(timeout, C_LOG_TIME_BASE) & "! " & msg);
end if;
end loop;
wait;
end procedure activity_watchdog;
end package body ti_vvc_framework_support_pkg;
|
mit
|
UVVM/UVVM_All
|
uvvm_util/src/adaptations_pkg.vhd
|
1
|
27827
|
--================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
----------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.types_pkg.all;
package adaptations_pkg is
constant C_ALERT_FILE_NAME : string := "_Alert.txt";
constant C_LOG_FILE_NAME : string := "_Log.txt";
constant C_SHOW_UVVM_UTILITY_LIBRARY_INFO : boolean := true; -- Set this to false when you no longer need the initial info
constant C_SHOW_UVVM_UTILITY_LIBRARY_RELEASE_INFO : boolean := true; -- Set this to false when you no longer need the release info
constant C_UVVM_TIMEOUT : time := 100 us; -- General timeout for UVVM wait statements
--------------------------------------------------------------------------------------------------------------------------------
-- Log format
--------------------------------------------------------------------------------------------------------------------------------
--UVVM: [<ID>] <time> <Scope> Msg
--PPPPPPPPIIIIII TTTTTTTT SSSSSSSSSSSSSS MMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMM
constant C_LOG_PREFIX : string := "UVVM: "; -- Note: ': ' is recommended as final characters
constant C_LOG_PREFIX_WIDTH : natural := C_LOG_PREFIX'length;
constant C_LOG_MSG_ID_WIDTH : natural := 24;
constant C_LOG_TIME_WIDTH : natural := 16; -- 3 chars used for unit eg. " ns"
constant C_LOG_TIME_BASE : time := ns; -- Unit in which time is shown in log (ns | ps)
constant C_LOG_TIME_DECIMALS : natural := 1; -- Decimals to show for given C_LOG_TIME_BASE
constant C_LOG_SCOPE_WIDTH : natural := 30; -- Maximum scope length
constant C_LOG_LINE_WIDTH : natural := 175;
constant C_LOG_INFO_WIDTH : natural := C_LOG_LINE_WIDTH - C_LOG_PREFIX_WIDTH;
constant C_USE_BACKSLASH_N_AS_LF : boolean := true; -- If true interprets '\n' as Line feed
constant C_USE_BACKSLASH_R_AS_LF : boolean := true; -- If true, inserts an empty line if '\r'
-- is the first character of the string.
-- All others '\r' will be printed as is.
constant C_SINGLE_LINE_ALERT : boolean := false; -- If true prints alerts on a single line.
constant C_SINGLE_LINE_LOG : boolean := false; -- If true prints log messages on a single line.
constant C_TB_SCOPE_DEFAULT : string := "TB seq."; -- Default scope in test sequencer
constant C_SCOPE : string := C_TB_SCOPE_DEFAULT & "(uvvm)";
constant C_VVC_CMD_SCOPE_DEFAULT : string := C_TB_SCOPE_DEFAULT & "(uvvm)"; -- Default scope in VVC commands
constant C_LOG_TIME_TRUNC_WARNING : boolean := true; -- Yields a single TB_WARNING if time stamp truncated. Otherwise none
constant C_SHOW_LOG_ID : boolean := true; -- This constant has replaced the global_show_log_id
constant C_SHOW_LOG_SCOPE : boolean := true; -- This constant has replaced the global_show_log_scope
constant C_WARNING_ON_LOG_ALERT_FILE_RUNTIME_RENAME : boolean := false;
constant C_USE_STD_STOP_ON_ALERT_STOP_LIMIT : boolean := true; -- true: break using std.env.stop, false: break using failure
constant C_ENABLE_CHECK_COUNTER : boolean := False; -- enable/disable check_counter to count number of check calls.
shared variable shared_default_log_destination : t_log_destination := CONSOLE_AND_LOG;
--------------------------------------------------------------------------------------------------------------------------------
-- Verbosity control
-- NOTE: Do not enter new IDs without proper evaluation:
-- 1. Is it - or could it be covered by an existing ID
-- 2. Could it be combined with other needs for a more general new ID
-- Feel free to suggest new ID for future versions of UVVM Utility Library ([email protected])
--------------------------------------------------------------------------------------------------------------------------------
type t_msg_id is (
-- Bitvis utility methods
NO_ID, -- Used as default prior to setting actual ID when transfering ID as a field in a record
ID_UTIL_BURIED, -- Used for buried log messages where msg and scope cannot be modified from outside
ID_BITVIS_DEBUG, -- Bitvis internal ID used for UVVM debugging
ID_UTIL_SETUP, -- Used for Utility setup
ID_LOG_MSG_CTRL, -- Used inside Utility library only - when enabling/disabling msg IDs.
ID_ALERT_CTRL, -- Used inside Utility library only - when setting IGNORE or REGARD on various alerts.
ID_NEVER, -- Used for avoiding log entry. Cannot be enabled.
ID_FINISH_OR_STOP, -- Used when terminating the complete simulation - independent of why
ID_CLOCK_GEN, -- Used for logging when clock generators are enabled or disabled
ID_GEN_PULSE, -- Used for logging when a gen_pulse procedure starts pulsing a signal
ID_BLOCKING, -- Used for logging when using synchronisation flags
ID_WATCHDOG, -- Used for logging the activity of the watchdog
ID_RAND_GEN, -- Used for logging "Enhanced Randomization" values returned by rand()\randm()
ID_RAND_CONF, -- Used for logging "Enhanced Randomization" configuration changes, except from name and scope
ID_FUNC_COV_BINS, -- Used for logging functional coverage add_bins() and add_cross() methods
ID_FUNC_COV_BINS_INFO, -- Used for logging functional coverage add_bins() and add_cross() methods detailed information
ID_FUNC_COV_RAND, -- Used for logging functional coverage "Optimized Randomization" values returned by rand()
ID_FUNC_COV_SAMPLE, -- Used for logging functional coverage sampling
ID_FUNC_COV_CONFIG, -- Used for logging functional coverage configuration changes
-- General
ID_POS_ACK, -- To write a positive acknowledge on a check
-- Directly inside test sequencers
ID_LOG_HDR, -- ONLY allowed in test sequencer, Log section headers
ID_LOG_HDR_LARGE, -- ONLY allowed in test sequencer, Large log section headers
ID_LOG_HDR_XL, -- ONLY allowed in test sequencer, Extra large log section headers
ID_SEQUENCER, -- ONLY allowed in test sequencer, Normal log (not log headers)
ID_SEQUENCER_SUB, -- ONLY allowed in test sequencer, Subprograms defined in sequencer
-- BFMs
ID_BFM, -- Used inside a BFM (to log BFM access)
ID_BFM_WAIT, -- Used inside a BFM to indicate that it is waiting for something (e.g. for ready)
ID_BFM_POLL, -- Used inside a BFM when polling until reading a given value. I.e. to show all reads until expected value found (e.g. for sbi_poll_until())
ID_BFM_POLL_SUMMARY, -- Used inside a BFM when showing the summary of data that has been received while waiting for expected data.
ID_CHANNEL_BFM, -- Used inside a BFM when the protocol is split into separate channels
ID_TERMINATE_CMD, -- Typically used inside a loop in a procedure to end the loop (e.g. for sbi_poll_until() or any looped generation of random stimuli
-- Packet related data Ids with three levels of granularity, for differentiating between frames, packets and segments.
-- Segment Ids, finest granularity of packet data
ID_SEGMENT_INITIATE, -- Notify that a segment is about to be transmitted or received
ID_SEGMENT_COMPLETE, -- Notify that a segment has been transmitted or received
ID_SEGMENT_HDR, -- Notify that a segment header has been transmitted or received. It also writes header info
ID_SEGMENT_DATA, -- Notify that a segment data has been transmitted or received. It also writes segment data
-- Packet Ids, medium granularity of packet data
ID_PACKET_INITIATE, -- Notify that a packet is about to be transmitted or received
ID_PACKET_PREAMBLE, -- Notify that a packet preamble has been transmitted or received
ID_PACKET_COMPLETE, -- Notify that a packet has been transmitted or received
ID_PACKET_HDR, -- Notify that a packet header has been transmitted or received. It also writes header info
ID_PACKET_DATA, -- Notify that a packet data has been transmitted or received. It also writes packet data
ID_PACKET_CHECKSUM, -- Notify that a packet checksum has been transmitted or received
ID_PACKET_GAP, -- Notify that an interpacket gap is in process
ID_PACKET_PAYLOAD, -- Notify that a packet payload has been transmitted or received
-- Frame Ids, roughest granularity of packet data
ID_FRAME_INITIATE, -- Notify that a frame is about to be transmitted or received
ID_FRAME_COMPLETE, -- Notify that a frame has been transmitted or received
ID_FRAME_HDR, -- Notify that a frame header has been transmitted or received. It also writes header info
ID_FRAME_DATA, -- Notify that a frame data has been transmitted or received. It also writes frame data
-- Coverage Ids
ID_COVERAGE_MAKEBIN, -- Log messages from MakeBin (IllegalBin/GenBin/IgnoreBin)
ID_COVERAGE_ADDBIN, -- Log messages from AddBin/AddCross
ID_COVERAGE_ICOVER, -- ICover logging, NB: Very low level debugging. Can result in large amount of data.
ID_COVERAGE_CONFIG, -- Logging of configuration in the coverage package
ID_COVERAGE_SUMMARY, -- Report logging : Summary of coverage, with both covered bins and holes
ID_COVERAGE_HOLES, -- Report logging : Holes only
-- Distributed command systems
ID_UVVM_SEND_CMD, -- Logs the commands sent to the VVC
ID_UVVM_CMD_ACK, -- Logs the command's ACKs or timeouts from the VVC
ID_UVVM_CMD_RESULT, -- Logs the fetched results from the VVC
ID_CMD_INTERPRETER, -- Message from VVC interpreter about correctly received and queued/issued command
ID_CMD_INTERPRETER_WAIT, -- Message from VVC interpreter that it is actively waiting for a command
ID_IMMEDIATE_CMD, -- Message from VVC interpreter that an IMMEDIATE command has been executed
ID_IMMEDIATE_CMD_WAIT, -- Message from VVC interpreter that an IMMEDIATE command is waiting for command to complete
ID_CMD_EXECUTOR, -- Message from VVC executor about correctly received command - prior to actual execution
ID_CMD_EXECUTOR_WAIT, -- Message from VVC executor that it is actively waiting for a command
ID_CHANNEL_EXECUTOR, -- Message from a channel specific VVC executor process
ID_CHANNEL_EXECUTOR_WAIT, -- Message from a channel specific VVC executor process that it is actively waiting for a command
ID_NEW_HVVC_CMD_SEQ, -- Message from a lower level VVC which receives a new command sequence from an HVVC
ID_INSERTED_DELAY, -- Message from VVC executor that it is waiting a given delay
-- Await completion
ID_OLD_AWAIT_COMPLETION, -- Temporary log messages related to old await_completion mechanism. Will be removed in v3.0
ID_AWAIT_COMPLETION, -- Used for logging the procedure call waiting for completion
ID_AWAIT_COMPLETION_LIST, -- Used for logging modifications to the list of VVCs waiting for completion
ID_AWAIT_COMPLETION_WAIT, -- Used for logging when the procedure starts waiting for completion
ID_AWAIT_COMPLETION_END, -- Used for logging when the procedure has finished waiting for completion
-- Distributed data
ID_UVVM_DATA_QUEUE, -- Information about UVVM data FIFO/stack (initialization, put, get, etc)
-- VVC system
ID_CONSTRUCTOR, -- Constructor message from VVCs (or other components/process when needed)
ID_CONSTRUCTOR_SUB, -- Constructor message for lower level constructor messages (like Queue-information and other limitations)
ID_VVC_ACTIVITY,
-- Monitors
ID_MONITOR, -- General monitor information
ID_MONITOR_ERROR, -- General monitor errors
-- SB package
ID_DATA, -- To write general handling of data
ID_CTRL, -- To write general control/config information
-- Specification vs Verification IDs
ID_FILE_OPEN_CLOSE, -- Id used when opening / closing file
ID_FILE_PARSER, -- Id used in file parsers
ID_SPEC_COV, -- Messages from the specification coverage methods
-- Special purpose - Not really IDs
ALL_MESSAGES -- Applies to ALL message ID apart from ID_NEVER
);
type t_msg_id_panel is array (t_msg_id'left to t_msg_id'right) of t_enabled;
constant C_TB_MSG_ID_DEFAULT : t_msg_id := ID_SEQUENCER; -- msg ID used when calling the log method without any msg ID switch.
-- Default message Id panel to be used for all message Id panels, except:
-- - VVC message Id panels, see constant C_VVC_MSG_ID_PANEL_DEFAULT
constant C_MSG_ID_PANEL_DEFAULT : t_msg_id_panel := (
ID_NEVER => DISABLED,
ID_UTIL_BURIED => DISABLED,
ID_BITVIS_DEBUG => DISABLED,
ID_COVERAGE_MAKEBIN => DISABLED,
ID_COVERAGE_ADDBIN => DISABLED,
ID_COVERAGE_ICOVER => DISABLED,
ID_RAND_GEN => DISABLED,
ID_RAND_CONF => DISABLED,
ID_FUNC_COV_BINS => DISABLED,
ID_FUNC_COV_BINS_INFO => DISABLED,
ID_FUNC_COV_RAND => DISABLED,
ID_FUNC_COV_SAMPLE => DISABLED,
ID_FUNC_COV_CONFIG => DISABLED,
others => ENABLED
);
type t_msg_id_indent is array (t_msg_id'left to t_msg_id'right) of string(1 to 4);
constant C_MSG_ID_INDENT : t_msg_id_indent := (
ID_IMMEDIATE_CMD_WAIT => " ..",
ID_CMD_INTERPRETER => " " & NUL & NUL,
ID_CMD_INTERPRETER_WAIT => " ..",
ID_CMD_EXECUTOR => " " & NUL & NUL,
ID_CMD_EXECUTOR_WAIT => " ..",
ID_UVVM_SEND_CMD => "->" & NUL & NUL,
ID_UVVM_CMD_ACK => " ",
ID_NEW_HVVC_CMD_SEQ => " " & NUL & NUL,
ID_AWAIT_COMPLETION_WAIT => ".." & NUL & NUL,
ID_AWAIT_COMPLETION_END => " " & NUL & NUL,
ID_FUNC_COV_BINS_INFO => " " & NUL & NUL,
others => "" & NUL & NUL & NUL & NUL
);
constant C_MSG_DELIMITER : character := ''';
--------------------------------------------------------------------------------------------------------------------------------
-- Alert counters
--------------------------------------------------------------------------------------------------------------------------------
-- Default values. These can be overwritten in each sequencer by using
-- set_alert_attention or set_alert_stop_limit (see quick ref).
constant C_DEFAULT_ALERT_ATTENTION : t_alert_attention := (others => REGARD);
-- 0 = Never stop
constant C_DEFAULT_STOP_LIMIT : t_alert_counters := (note to manual_check => 0,
others => 1);
--------------------------------------------------------------------------------------------------------------------------------
-- Hierarchical alerts
--------------------------------------------------------------------------------------------------------------------------------
constant C_ENABLE_HIERARCHICAL_ALERTS : boolean := false;
constant C_BASE_HIERARCHY_LEVEL : string(1 to 5) := "Total";
constant C_HIERARCHY_NODE_NAME_LENGTH : natural := C_LOG_SCOPE_WIDTH;
constant C_EMPTY_NODE : t_hierarchy_node := ((1 to C_HIERARCHY_NODE_NAME_LENGTH => ' '),
(others => (others => 0)),
(others => 0),
(others => true));
--------------------------------------------------------------------------------------------------------------------------------
-- Synchronisation
--------------------------------------------------------------------------------------------------------------------------------
constant C_NUM_SYNC_FLAGS : positive := 100; -- Maximum number of sync flags
--------------------------------------------------------------------------------------------------------------------------------
-- Randomization adaptations
--------------------------------------------------------------------------------------------------------------------------------
constant C_RAND_MAX_NAME_LENGTH : positive := 20; -- Maximum length used for random generator names
constant C_RAND_INIT_SEED_1 : positive := 10; -- Initial randomizaton seed 1
constant C_RAND_INIT_SEED_2 : positive := 100; -- Initial randomizaton seed 2
constant C_RAND_REAL_NUM_DECIMAL_DIGITS : positive := 2; -- Number of decimal digits displayed in randomization logs
-- Maximum number of possible values to be stored in the cyclic list. This limit is due to memory restrictions since some
-- simulators cannot handle more than 2**30 values. When a higher number of values is used, a generic queue is used instead
-- which only stores the generated values. The queue will use less memory, but will be slower than the list.
constant C_RAND_CYCLIC_LIST_MAX_NUM_VALUES : natural := 2**30;
-- When using the generic queue and the number of (different) generated cyclic values reaches this limit, an alert is generated
-- to indicate that simulation might slow down due to the large queue that needs to be parsed.
constant C_RAND_CYCLIC_QUEUE_MAX_ALERT : natural := 10000;
constant C_RAND_CYCLIC_QUEUE_MAX_ALERT_DISABLE : boolean := false; -- Set to true to disable the alert above
constant C_RAND_MM_MAX_LONG_VECTOR_LENGTH : natural := 128; -- Maximum length for unsigned/signed constraints in multi-method approach
--------------------------------------------------------------------------------------------------------------------------------
-- Functional Coverage adaptations
--------------------------------------------------------------------------------------------------------------------------------
constant C_FC_MAX_NUM_NEW_BINS : positive := 1000; -- Maximum number of bins which can be added using a single add_bins() call
constant C_FC_MAX_PROC_CALL_LENGTH : positive := 100; -- Maximum string length used for logging a single bin function
constant C_FC_MAX_NAME_LENGTH : positive := 20; -- Maximum string length used for coverpoint and bin names
constant C_FC_MAX_NUM_BIN_VALUES : positive := 10; -- Maximum number of values that can be given in bin() and bin_transition()
constant C_FC_MAX_NUM_COVERPOINTS : positive := 20; -- Maximum number of coverpoints
constant C_FC_DEFAULT_INITIAL_NUM_BINS_ALLOCATED : positive := 1; -- Default value used for the number of bins allocated when a coverpoint is created
constant C_FC_DEFAULT_NUM_BINS_ALLOCATED_INCREMENT : positive := 10; -- Default value used to increment the number of bins allocated in a coverpoint when the max is reached
--------------------------------------------------------------------------------------------------------------------------------
-- UVVM VVC Framework adaptations
--------------------------------------------------------------------------------------------------------------------------------
signal global_show_msg_for_uvvm_cmd : boolean := true;
constant C_CMD_QUEUE_COUNT_MAX : natural := 20; -- (VVC Command queue) May be overwritten for dedicated VVC
constant C_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY : t_alert_level := WARNING;
constant C_CMD_QUEUE_COUNT_THRESHOLD : natural := 18;
constant C_RESULT_QUEUE_COUNT_MAX : natural := 20; -- (VVC Result queue) May be overwritten for dedicated VVC
constant C_RESULT_QUEUE_COUNT_THRESHOLD_SEVERITY : t_alert_level := WARNING;
constant C_RESULT_QUEUE_COUNT_THRESHOLD : natural := 18;
constant C_MAX_VVC_INSTANCE_NUM : natural := 8;
constant C_MAX_NUM_SEQUENCERS : natural := 10; -- Max number of sequencers
constant C_MAX_TB_VVC_NUM : natural := 20; -- Max number of VVCs in testbench (including all channels)
-- Maximum allowed length of VVC names
constant C_MAX_VVC_NAME_LENGTH : positive := 20;
-- Minimum width of vvc name and channel displayed in scope.
-- These combined + the length of instance + 2 (commas), cannot exceed C_LOG_SCOPE_WIDTH.
constant C_MINIMUM_CHANNEL_SCOPE_WIDTH : natural := 10;
constant C_MINIMUM_VVC_NAME_SCOPE_WIDTH : natural := 10;
constant C_TOTAL_NUMBER_OF_BITS_IN_DATA_BUFFER : natural := 2048;
constant C_NUMBER_OF_DATA_BUFFERS : natural := 10;
-- Default message Id panel intended for use in the VVCs
constant C_VVC_MSG_ID_PANEL_DEFAULT : t_msg_id_panel := (
ID_NEVER => DISABLED,
ID_UTIL_BURIED => DISABLED,
ID_CHANNEL_BFM => DISABLED,
ID_CHANNEL_EXECUTOR => DISABLED,
ID_CHANNEL_EXECUTOR_WAIT => DISABLED,
others => ENABLED
);
-- Deprecated, will be removed.
type t_data_source is (
NA,
FROM_BUFFER,
RANDOM,
RANDOM_TO_BUFFER
);
-- Deprecated, will be removed.
type t_error_injection is (
NA,
RANDOM_BIT_ERROR,
RANDOM_DATA_ERROR,
RANDOM_ADDRESS_ERROR
);
type t_randomisation is (
NA,
RANDOM,
RANDOM_FAVOUR_EDGES
);
type t_channel is (
NA, -- When channel is not relevant
ALL_CHANNELS, -- When command shall be received by all channels
-- UVVM predefined channels.
RX, TX
-- User can add more channels if needed below.
);
constant C_NUM_SEMAPHORE_LOCK_TRIES : natural := 500;
constant C_MAX_QUEUE_INSTANCE_NUM : positive := 100; -- Maximum number of generic queue instances
--------------------------------------------------------------------------------------------------------------------------------
-- Scoreboard adaptations
--------------------------------------------------------------------------------------------------------------------------------
alias C_MAX_SB_INSTANCE_IDX is C_MAX_QUEUE_INSTANCE_NUM; -- Maximum number of SB instances
constant C_SB_TAG_WIDTH : positive := 128; -- Number of characters in SB tag
constant C_SB_SOURCE_WIDTH : positive := 128; -- Number of characters in SB source element
constant C_SB_SLV_WIDTH : positive := 128; -- Width of the SLV in the predefined SLV SB
-- Default message Id panel intended for use in SB
constant C_SB_MSG_ID_PANEL_DEFAULT : t_msg_id_panel := (
ID_CTRL => ENABLED,
ID_DATA => DISABLED,
others => DISABLED
);
--------------------------------------------------------------------------------------------------------------------------------
-- VVC Adaptations
--------------------------------------------------------------------------------------------------------------------------------
constant C_SPI_VVC_DATA_ARRAY_WIDTH : natural := 31; -- Width of SPI VVC data array for SPI VVC and transaction package defaults.
--------------------------------------------------------------------------------------------------------------------------------
-- Hierarchical-VVCs
--------------------------------------------------------------------------------------------------------------------------------
-- HVVC supported interfaces
type t_interface is (SBI, GMII);
-- For frame-based communication
type t_frame_field is (
HEADER,
PAYLOAD,
CHECKSUM
);
-- Message Id panel with all IDs as NA
constant C_UNUSED_MSG_ID_PANEL : t_msg_id_panel := (
others => NA
);
--------------------------------------------------------------------------------------------------------------------------------
-- CRC
--------------------------------------------------------------------------------------------------------------------------------
-- CRC-32 (IEEE 802.3)
constant C_CRC_32_START_VALUE : std_logic_vector(31 downto 0) := x"FFFFFFFF";
constant C_CRC_32_POLYNOMIAL : std_logic_vector(32 downto 0) := (32|26|23|22|16|12|11|10|8|7|5|4|2|1|0 => '1', others => '0'); --0x04C11DB7
constant C_CRC_32_RESIDUE : std_logic_vector(31 downto 0) := x"C704DD7B"; -- using left shifting CRC
--------------------------------------------------------------------------------------------------------------------------------
-- *****************************************************************************************************************************
-- WARNING!
-- The code below is not intended for user modifications!
-- *****************************************************************************************************************************
--------------------------------------------------------------------------------------------------------------------------------
constant C_CMD_IDX_PREFIX : string := " [";
constant C_CMD_IDX_SUFFIX : string := "]";
constant ALL_INSTANCES : integer := -2;
constant ALL_ENABLED_INSTANCES : integer := -3;
type t_vvc_id is record
name : string(1 to C_MAX_VVC_NAME_LENGTH);
instance : natural;
channel : t_channel;
end record;
constant C_VVC_ID_DEFAULT : t_vvc_id := (
name => (others => NUL),
instance => 0,
channel => NA
);
type t_vvc_state is record
activity : t_activity;
last_cmd_idx_executed : integer;
await_selected_supported : boolean;
end record;
constant C_VVC_STATE_DEFAULT : t_vvc_state := (
activity => INACTIVE,
last_cmd_idx_executed => -1,
await_selected_supported => true
);
-- These values are used to indicate outdated sub-programs
constant C_DEPRECATE_SETTING : t_deprecate_setting := DEPRECATE_ONCE;
shared variable deprecated_subprogram_list : t_deprecate_list := (others=>(others => ' '));
end package adaptations_pkg;
package body adaptations_pkg is
end package body adaptations_pkg;
|
mit
|
YingcaiDong/Shunting-Model-Based-Path-Planning-Algorithm-Accelerator-Using-FPGA
|
System Design Source FIle/ipshared/xilinx.com/axi_dma_v7_1/2a047f91/hdl/src/vhdl/axi_dma_mm2s_cntrl_strm.vhd
|
3
|
21779
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_mm2s_cntrl_strm.vhd
-- Description: This entity is MM2S control stream logic
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1;
use axi_dma_v7_1.axi_dma_pkg.all;
library lib_pkg_v1_0;
use lib_pkg_v1_0.lib_pkg.clog2;
use lib_pkg_v1_0.lib_pkg.max2;
library lib_fifo_v1_0;
-------------------------------------------------------------------------------
entity axi_dma_mm2s_cntrl_strm is
generic(
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Primary data path channels (MM2S and S2MM)
-- run asynchronous to AXI Lite, DMA Control,
-- and SG.
C_PRMY_CMDFIFO_DEPTH : integer range 1 to 16 := 1;
-- Depth of DataMover command FIFO
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Control Stream Data Width
C_FAMILY : string := "virtex7"
-- Target FPGA Device Family
);
port (
-- Secondary clock / reset
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Primary clock / reset --
axi_prmry_aclk : in std_logic ; --
p_reset_n : in std_logic ; --
--
-- MM2S Error --
mm2s_stop : in std_logic ; --
--
-- Control Stream FIFO write signals (from axi_dma_mm2s_sg_if) --
cntrlstrm_fifo_wren : in std_logic ; --
cntrlstrm_fifo_din : in std_logic_vector --
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH downto 0); --
cntrlstrm_fifo_full : out std_logic ; --
--
--
-- Memory Map to Stream Control Stream Interface --
m_axis_mm2s_cntrl_tdata : out std_logic_vector --
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0); --
m_axis_mm2s_cntrl_tkeep : out std_logic_vector --
((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0);--
m_axis_mm2s_cntrl_tvalid : out std_logic ; --
m_axis_mm2s_cntrl_tready : in std_logic ; --
m_axis_mm2s_cntrl_tlast : out std_logic --
);
end axi_dma_mm2s_cntrl_strm;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_mm2s_cntrl_strm is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Number of words deep fifo needs to be
-- Only 5 app fields, but set to 8 so depth is a power of 2
constant CNTRL_FIFO_DEPTH : integer := max2(16,8 * C_PRMY_CMDFIFO_DEPTH);
-- Width of fifo rd and wr counts - only used for proper fifo operation
constant CNTRL_FIFO_CNT_WIDTH : integer := clog2(CNTRL_FIFO_DEPTH+1);
constant USE_LOGIC_FIFOS : integer := 0; -- Use Logic FIFOs
constant USE_BRAM_FIFOS : integer := 1; -- Use BRAM FIFOs
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- FIFO signals
signal cntrl_fifo_rden : std_logic := '0';
signal cntrl_fifo_empty : std_logic := '0';
signal cntrl_fifo_dout : std_logic_vector
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH downto 0) := (others => '0');
signal cntrl_fifo_dvalid: std_logic := '0';
signal cntrl_tdata : std_logic_vector
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0) := (others => '0');
signal cntrl_tkeep : std_logic_vector
((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal cntrl_tvalid : std_logic := '0';
signal cntrl_tready : std_logic := '0';
signal cntrl_tlast : std_logic := '0';
signal sinit : std_logic := '0';
signal m_valid : std_logic := '0';
signal m_ready : std_logic := '0';
signal m_data : std_logic_vector(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0) := (others => '0');
signal m_strb : std_logic_vector((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal m_last : std_logic := '0';
signal skid_rst : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- All bytes always valid
cntrl_tkeep <= (others => '1');
-- Primary Clock is synchronous to Secondary Clock therfore
-- instantiate a sync fifo.
GEN_SYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
signal mm2s_stop_d1 : std_logic := '0';
signal mm2s_stop_re : std_logic := '0';
signal xfer_in_progress : std_logic := '0';
begin
-- reset on hard reset or mm2s stop
sinit <= not m_axi_sg_aresetn or mm2s_stop;
-- Generate Synchronous FIFO
I_CNTRL_FIFO : entity lib_fifo_v1_0.sync_fifo_fg
generic map (
C_FAMILY => C_FAMILY ,
C_MEMORY_TYPE => USE_LOGIC_FIFOS,
C_WRITE_DATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH + 1,
C_WRITE_DEPTH => CNTRL_FIFO_DEPTH ,
C_READ_DATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH + 1,
C_READ_DEPTH => CNTRL_FIFO_DEPTH ,
C_PORTS_DIFFER => 0,
C_HAS_DCOUNT => 1, --req for proper fifo operation
C_DCOUNT_WIDTH => CNTRL_FIFO_CNT_WIDTH,
C_HAS_ALMOST_FULL => 0,
C_HAS_RD_ACK => 0,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_ERR => 0,
C_RD_ACK_LOW => 0,
C_RD_ERR_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_ERR_LOW => 0,
C_PRELOAD_REGS => 1,-- 1 = first word fall through
C_PRELOAD_LATENCY => 0 -- 0 = first word fall through
-- C_USE_EMBEDDED_REG => 1 -- 0 ;
)
port map (
Clk => m_axi_sg_aclk ,
Sinit => sinit ,
Din => cntrlstrm_fifo_din ,
Wr_en => cntrlstrm_fifo_wren ,
Rd_en => cntrl_fifo_rden ,
Dout => cntrl_fifo_dout ,
Full => cntrlstrm_fifo_full ,
Empty => cntrl_fifo_empty ,
Almost_full => open ,
Data_count => open ,
Rd_ack => open ,
Rd_err => open ,
Wr_ack => open ,
Wr_err => open
);
-----------------------------------------------------------------------
-- Control Stream OUT Side
-----------------------------------------------------------------------
-- Read if fifo is not empty and target is ready
cntrl_fifo_rden <= not cntrl_fifo_empty
and cntrl_tready;
-- Drive valid if fifo is not empty or in the middle
-- of transfer and stop issued.
cntrl_tvalid <= not cntrl_fifo_empty
or (xfer_in_progress and mm2s_stop_re);
-- Pass data out to control channel with MSB driving tlast
cntrl_tlast <= (cntrl_tvalid and cntrl_fifo_dout(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH))
or (xfer_in_progress and mm2s_stop_re);
cntrl_tdata <= cntrl_fifo_dout(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0);
-- Register stop to create re pulse for cleaning shutting down
-- stream out during soft reset.
REG_STOP : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_stop_d1 <= '0';
else
mm2s_stop_d1 <= mm2s_stop;
end if;
end if;
end process REG_STOP;
mm2s_stop_re <= mm2s_stop and not mm2s_stop_d1;
-------------------------------------------------------------
-- Flag transfer in progress. If xfer in progress then
-- a fake tlast and tvalid need to be asserted during soft
-- reset else no need of tlast.
-------------------------------------------------------------
TRANSFER_IN_PROGRESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(cntrl_tlast = '1' and cntrl_tvalid = '1' and cntrl_tready = '1')then
xfer_in_progress <= '0';
elsif(xfer_in_progress = '0' and cntrl_tvalid = '1')then
xfer_in_progress <= '1';
end if;
end if;
end process TRANSFER_IN_PROGRESS;
skid_rst <= not m_axi_sg_aresetn;
---------------------------------------------------------------------------
-- Buffer AXI Signals
---------------------------------------------------------------------------
CNTRL_SKID_BUF_I : entity axi_dma_v7_1.axi_dma_skid_buf
generic map(
C_WDATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH
)
port map(
-- System Ports
ACLK => m_axi_sg_aclk ,
ARST => skid_rst ,
skid_stop => mm2s_stop_re ,
-- Slave Side (Stream Data Input)
S_VALID => cntrl_tvalid ,
S_READY => cntrl_tready ,
S_Data => cntrl_tdata ,
S_STRB => cntrl_tkeep ,
S_Last => cntrl_tlast ,
-- Master Side (Stream Data Output
M_VALID => m_axis_mm2s_cntrl_tvalid ,
M_READY => m_axis_mm2s_cntrl_tready ,
M_Data => m_axis_mm2s_cntrl_tdata ,
M_STRB => m_axis_mm2s_cntrl_tkeep ,
M_Last => m_axis_mm2s_cntrl_tlast
);
end generate GEN_SYNC_FIFO;
-- Primary Clock is asynchronous to Secondary Clock therfore
-- instantiate an async fifo.
GEN_ASYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
signal mm2s_stop_reg : std_logic := '0'; -- CR605883
signal p_mm2s_stop_d1 : std_logic := '0';
signal p_mm2s_stop_d2 : std_logic := '0';
signal p_mm2s_stop_d3 : std_logic := '0';
signal p_mm2s_stop_re : std_logic := '0';
signal xfer_in_progress : std_logic := '0';
begin
-- reset on hard reset, soft reset, or mm2s error
sinit <= not p_reset_n or p_mm2s_stop_d2;
-- Generate Asynchronous FIFO
I_CNTRL_STRM_FIFO : entity axi_dma_v7_1.axi_dma_afifo_autord
generic map(
C_DWIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH + 1 ,
-- Temp work around for issue in async fifo model
-- C_DEPTH => CNTRL_FIFO_DEPTH ,
-- C_CNT_WIDTH => CNTRL_FIFO_CNT_WIDTH ,
C_DEPTH => 31 ,
C_CNT_WIDTH => 5 ,
C_USE_BLKMEM => USE_LOGIC_FIFOS ,
C_FAMILY => C_FAMILY
)
port map(
-- Inputs
AFIFO_Ainit => sinit ,
AFIFO_Wr_clk => m_axi_sg_aclk ,
AFIFO_Wr_en => cntrlstrm_fifo_wren ,
AFIFO_Din => cntrlstrm_fifo_din ,
AFIFO_Rd_clk => axi_prmry_aclk ,
AFIFO_Rd_en => cntrl_fifo_rden ,
AFIFO_Clr_Rd_Data_Valid => '0' ,
-- Outputs
AFIFO_DValid => cntrl_fifo_dvalid ,
AFIFO_Dout => cntrl_fifo_dout ,
AFIFO_Full => cntrlstrm_fifo_full ,
AFIFO_Empty => cntrl_fifo_empty ,
AFIFO_Almost_full => open ,
AFIFO_Almost_empty => open ,
AFIFO_Wr_count => open ,
AFIFO_Rd_count => open ,
AFIFO_Corr_Rd_count => open ,
AFIFO_Corr_Rd_count_minus1 => open ,
AFIFO_Rd_ack => open
);
-----------------------------------------------------------------------
-- Control Stream OUT Side
-----------------------------------------------------------------------
-- Read if fifo is not empty and target is ready
cntrl_fifo_rden <= not cntrl_fifo_empty -- fifo has data
and cntrl_tready; -- target ready
-- Drive valid if fifo is not empty or in the middle
-- of transfer and stop issued.
cntrl_tvalid <= cntrl_fifo_dvalid
or (xfer_in_progress and p_mm2s_stop_re);
-- Pass data out to control channel with MSB driving tlast
cntrl_tlast <= cntrl_tvalid and cntrl_fifo_dout(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH);
cntrl_tdata <= cntrl_fifo_dout(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0);
-- CR605883
-- Register stop to provide pure FF output for synchronizer
REG_STOP : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_stop_reg <= '0';
else
mm2s_stop_reg <= mm2s_stop;
end if;
end if;
end process REG_STOP;
-- Double/triple register mm2s error into primary clock domain
-- Triple register to give two versions with min double reg for use
-- in rising edge detection.
REG_ERR2PRMRY : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(p_reset_n = '0')then
p_mm2s_stop_d1 <= '0';
p_mm2s_stop_d2 <= '0';
p_mm2s_stop_d3 <= '0';
else
--p_mm2s_stop_d1 <= mm2s_stop;
p_mm2s_stop_d1 <= mm2s_stop_reg;
p_mm2s_stop_d2 <= p_mm2s_stop_d1;
p_mm2s_stop_d3 <= p_mm2s_stop_d2;
end if;
end if;
end process REG_ERR2PRMRY;
-- Rising edge pulse for use in shutting down stream output
p_mm2s_stop_re <= p_mm2s_stop_d2 and not p_mm2s_stop_d3;
-------------------------------------------------------------
-- Flag transfer in progress. If xfer in progress then
-- a fake tlast needs to be asserted during soft reset.
-- else no need of tlast.
-------------------------------------------------------------
TRANSFER_IN_PROGRESS : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(cntrl_tlast = '1' and cntrl_tvalid = '1' and cntrl_tready = '1')then
xfer_in_progress <= '0';
elsif(xfer_in_progress = '0' and cntrl_tvalid = '1')then
xfer_in_progress <= '1';
end if;
end if;
end process TRANSFER_IN_PROGRESS;
skid_rst <= not p_reset_n;
---------------------------------------------------------------------------
-- Buffer AXI Signals
---------------------------------------------------------------------------
CNTRL_SKID_BUF_I : entity axi_dma_v7_1.axi_dma_skid_buf
generic map(
C_WDATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH
)
port map(
-- System Ports
ACLK => axi_prmry_aclk ,
ARST => skid_rst ,
skid_stop => p_mm2s_stop_re ,
-- Slave Side (Stream Data Input)
S_VALID => cntrl_tvalid ,
S_READY => cntrl_tready ,
S_Data => cntrl_tdata ,
S_STRB => cntrl_tkeep ,
S_Last => cntrl_tlast ,
-- Master Side (Stream Data Output
M_VALID => m_axis_mm2s_cntrl_tvalid ,
M_READY => m_axis_mm2s_cntrl_tready ,
M_Data => m_axis_mm2s_cntrl_tdata ,
M_STRB => m_axis_mm2s_cntrl_tkeep ,
M_Last => m_axis_mm2s_cntrl_tlast
);
end generate GEN_ASYNC_FIFO;
end implementation;
|
mit
|
YingcaiDong/Shunting-Model-Based-Path-Planning-Algorithm-Accelerator-Using-FPGA
|
System Design Source FIle/ipshared/xilinx.com/axi_datamover_v5_1/3acd8cae/hdl/src/vhdl/axi_datamover_addr_cntl.vhd
|
6
|
41576
|
----------------------------------------------------------------------------
-- axi_datamover_addr_cntl.vhd
----------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_addr_cntl.vhd
--
-- Description:
-- This file implements the axi_datamover Master Address Controller.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_datamover_v5_1;
Use axi_datamover_v5_1.axi_datamover_fifo;
-------------------------------------------------------------------------------
entity axi_datamover_addr_cntl is
generic (
C_ADDR_FIFO_DEPTH : Integer range 1 to 32 := 4;
-- sets the depth of the Command Queue FIFO
C_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Sets the address bus width
C_ADDR_ID : Integer range 0 to 255 := 0;
-- Sets the value to be on the AxID output
C_ADDR_ID_WIDTH : Integer range 1 to 8 := 4;
-- Sets the width of the AxID output
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Sets the width of the Command Tag field width
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA family
);
port (
-- Clock input ---------------------------------------------
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
------------------------------------------------------------
-- AXI Address Channel I/O --------------------------------------------
addr2axi_aid : out std_logic_vector(C_ADDR_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
addr2axi_aaddr : out std_logic_vector(C_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
addr2axi_alen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
addr2axi_asize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
addr2axi_aburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
addr2axi_acache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel BURST output --
--
addr2axi_auser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel BURST output --
--
addr2axi_aprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
addr2axi_avalid : out std_logic; --
-- AXI Address Channel VALID output --
--
axi2addr_aready : in std_logic; --
-- AXI Address Channel READY input --
------------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -------
-- addr2axi_alock : out std_logic_vector(2 downto 0); --
-- addr2axi_acache : out std_logic_vector(4 downto 0); --
-- addr2axi_aqos : out std_logic_vector(3 downto 0); --
-- addr2axi_aregion : out std_logic_vector(3 downto 0); --
-------------------------------------------------------------------
-- Command Calculation Interface -----------------------------------------
mstr2addr_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2addr_addr : In std_logic_vector(C_ADDR_WIDTH-1 downto 0); --
-- The next command address to put on the AXI MMap ADDR --
--
mstr2addr_len : In std_logic_vector(7 downto 0); --
-- The next command length to put on the AXI MMap LEN --
-- Sized to support 256 data beat bursts --
--
mstr2addr_size : In std_logic_vector(2 downto 0); --
-- The next command size to put on the AXI MMap SIZE --
--
mstr2addr_burst : In std_logic_vector(1 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_cache : In std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_user : In std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_cmd_cmplt : In std_logic; --
-- The indication to the Address Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2addr_calc_error : In std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2addr_cmd_valid : in std_logic; --
-- The next command valid indication to the Address Channel --
-- Controller for the AXI MMap --
--
addr2mstr_cmd_ready : out std_logic; --
-- Indication to the Command Calculator that the --
-- command is being accepted --
--------------------------------------------------------------------------
-- Halted Indication to Reset Module ------------------------------
addr2rst_stop_cmplt : out std_logic; --
-- Output flag indicating the address controller has stopped --
-- posting commands to the Address Channel due to a stop --
-- request vai the data2addr_stop_req input port --
------------------------------------------------------------------
-- Address Generation Control ---------------------------------------
allow_addr_req : in std_logic; --
-- Input used to enable/stall the posting of address requests. --
-- 0 = stall address request generation. --
-- 1 = Enable Address request geneartion --
--
addr_req_posted : out std_logic; --
-- Indication from the Address Channel Controller to external --
-- User logic that an address has been posted to the --
-- AXI Address Channel. --
---------------------------------------------------------------------
-- Data Channel Interface ---------------------------------------------
addr2data_addr_posted : Out std_logic; --
-- Indication from the Address Channel Controller to the --
-- Data Controller that an address has been posted to the --
-- AXI Address Channel. --
--
data2addr_data_rdy : In std_logic; --
-- Indication that the Data Channel is ready to send the first --
-- databeat of the next command on the write data channel. --
-- This is used for the "wait for data" feature which keeps the --
-- address controller from issuing a transfer requset until the --
-- corresponding data is ready. This is expected to be held in --
-- the asserted state until the addr2data_addr_posted signal is --
-- asserted. --
--
data2addr_stop_req : In std_logic; --
-- Indication that the Data Channel has encountered an error --
-- or a soft shutdown request and needs the Address Controller --
-- to stop posting commands to the AXI Address channel --
-----------------------------------------------------------------------
-- Status Module Interface ---------------------------------------
addr2stat_calc_error : out std_logic; --
-- Indication to the Status Module that the Addr Cntl FIFO --
-- is loaded with a Calc error --
--
addr2stat_cmd_fifo_empty : out std_logic --
-- Indication to the Status Module that the Addr Cntl FIFO --
-- is empty --
------------------------------------------------------------------
);
end entity axi_datamover_addr_cntl;
architecture implementation of axi_datamover_addr_cntl is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Constant Declarations --------------------------------------------
Constant APROT_VALUE : std_logic_vector(2 downto 0) := (others => '0');
--'0' & -- bit 2, Normal Access
--'0' & -- bit 1, Nonsecure Access
--'0'; -- bit 0, Data Access
Constant LEN_WIDTH : integer := 8;
Constant SIZE_WIDTH : integer := 3;
Constant BURST_WIDTH : integer := 2;
Constant CMD_CMPLT_WIDTH : integer := 1;
Constant CALC_ERROR_WIDTH : integer := 1;
Constant ADDR_QUAL_WIDTH : integer := C_TAG_WIDTH + -- Cmd Tag field width
C_ADDR_WIDTH + -- Cmd Address field width
LEN_WIDTH + -- Cmd Len field width
SIZE_WIDTH + -- Cmd Size field width
BURST_WIDTH + -- Cmd Burst field width
CMD_CMPLT_WIDTH + -- Cmd Cmplt filed width
CALC_ERROR_WIDTH + -- Cmd Calc Error flag
8; -- Cmd Cache, user fields
Constant USE_SYNC_FIFO : integer := 0;
Constant REG_FIFO_PRIM : integer := 0;
Constant BRAM_FIFO_PRIM : integer := 1;
Constant SRL_FIFO_PRIM : integer := 2;
Constant FIFO_PRIM_TYPE : integer := SRL_FIFO_PRIM;
-- Signal Declarations --------------------------------------------
signal sig_axi_addr : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_axi_alen : std_logic_vector(7 downto 0) := (others => '0');
signal sig_axi_asize : std_logic_vector(2 downto 0) := (others => '0');
signal sig_axi_aburst : std_logic_vector(1 downto 0) := (others => '0');
signal sig_axi_acache : std_logic_vector(3 downto 0) := (others => '0');
signal sig_axi_auser : std_logic_vector(3 downto 0) := (others => '0');
signal sig_axi_avalid : std_logic := '0';
signal sig_axi_aready : std_logic := '0';
signal sig_addr_posted : std_logic := '0';
signal sig_calc_error : std_logic := '0';
signal sig_cmd_fifo_empty : std_logic := '0';
Signal sig_aq_fifo_data_in : std_logic_vector(ADDR_QUAL_WIDTH-1 downto 0) := (others => '0');
Signal sig_aq_fifo_data_out : std_logic_vector(ADDR_QUAL_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_addr : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_fifo_next_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_fifo_next_burst : std_logic_vector(1 downto 0) := (others => '0');
signal sig_fifo_next_user : std_logic_vector(3 downto 0) := (others => '0');
signal sig_fifo_next_cache : std_logic_vector(3 downto 0) := (others => '0');
signal sig_fifo_next_cmd_cmplt : std_logic := '0';
signal sig_fifo_calc_error : std_logic := '0';
signal sig_fifo_wr_cmd_valid : std_logic := '0';
signal sig_fifo_wr_cmd_ready : std_logic := '0';
signal sig_fifo_rd_cmd_valid : std_logic := '0';
signal sig_fifo_rd_cmd_ready : std_logic := '0';
signal sig_next_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_next_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_next_len_reg : std_logic_vector(7 downto 0) := (others => '0');
signal sig_next_size_reg : std_logic_vector(2 downto 0) := (others => '0');
signal sig_next_burst_reg : std_logic_vector(1 downto 0) := (others => '0');
signal sig_next_cache_reg : std_logic_vector(3 downto 0) := (others => '0');
signal sig_next_user_reg : std_logic_vector(3 downto 0) := (others => '0');
signal sig_next_cmd_cmplt_reg : std_logic := '0';
signal sig_addr_valid_reg : std_logic := '0';
signal sig_calc_error_reg : std_logic := '0';
signal sig_pop_addr_reg : std_logic := '0';
signal sig_push_addr_reg : std_logic := '0';
signal sig_addr_reg_empty : std_logic := '0';
signal sig_addr_reg_full : std_logic := '0';
signal sig_posted_to_axi : std_logic := '0';
-- obsoleted signal sig_set_wfd_flop : std_logic := '0';
-- obsoleted signal sig_clr_wfd_flop : std_logic := '0';
-- obsoleted signal sig_wait_for_data : std_logic := '0';
-- obsoleted signal sig_data2addr_data_rdy_reg : std_logic := '0';
signal sig_allow_addr_req : std_logic := '0';
signal sig_posted_to_axi_2 : std_logic := '0';
signal new_cmd_in : std_logic;
signal first_addr_valid : std_logic;
signal first_addr_valid_del : std_logic;
signal first_addr_int : std_logic_vector (C_ADDR_WIDTH-1 downto 0);
signal last_addr_int : std_logic_vector (C_ADDR_WIDTH-1 downto 0);
signal addr2axi_cache_int : std_logic_vector (7 downto 0);
signal addr2axi_cache_int1 : std_logic_vector (7 downto 0);
signal last_one : std_logic;
signal latch : std_logic;
signal first_one : std_logic;
signal latch_n : std_logic;
signal latch_n_del : std_logic;
signal mstr2addr_cache_info_int : std_logic_vector (7 downto 0);
-- Register duplication attribute assignments to control fanout
-- on handshake output signals
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
Attribute KEEP of sig_posted_to_axi : signal is "TRUE"; -- definition
Attribute KEEP of sig_posted_to_axi_2 : signal is "TRUE"; -- definition
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_posted_to_axi : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_posted_to_axi_2 : signal is "no";
begin --(architecture implementation)
-- AXI I/O Port assignments
addr2axi_aid <= STD_LOGIC_VECTOR(TO_UNSIGNED(C_ADDR_ID, C_ADDR_ID_WIDTH));
addr2axi_aaddr <= sig_axi_addr ;
addr2axi_alen <= sig_axi_alen ;
addr2axi_asize <= sig_axi_asize ;
addr2axi_aburst <= sig_axi_aburst;
addr2axi_acache <= sig_axi_acache;
addr2axi_auser <= sig_axi_auser;
addr2axi_aprot <= APROT_VALUE ;
addr2axi_avalid <= sig_axi_avalid;
sig_axi_aready <= axi2addr_aready;
-- Command Calculator Handshake output
sig_fifo_wr_cmd_valid <= mstr2addr_cmd_valid ;
addr2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
-- Data Channel Controller synchro pulse output
addr2data_addr_posted <= sig_addr_posted;
-- Status Module Interface outputs
addr2stat_calc_error <= sig_calc_error ;
addr2stat_cmd_fifo_empty <= sig_addr_reg_empty and
sig_cmd_fifo_empty;
-- Flag Indicating the Address Controller has completed a Stop
addr2rst_stop_cmplt <= (data2addr_stop_req and -- normal shutdown case
sig_addr_reg_empty) or
(data2addr_stop_req and -- shutdown after error trap
sig_calc_error);
-- Assign the address posting control and status
sig_allow_addr_req <= allow_addr_req ;
addr_req_posted <= sig_posted_to_axi_2 ;
-- Internal logic ------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ADDR_FIFO
--
-- If Generate Description:
-- Implements the case where the cmd qualifier depth is
-- greater than 1.
--
------------------------------------------------------------
GEN_ADDR_FIFO : if (C_ADDR_FIFO_DEPTH > 1) generate
begin
-- Format the input FIFO data word
sig_aq_fifo_data_in <= mstr2addr_cache &
mstr2addr_user &
mstr2addr_calc_error &
mstr2addr_cmd_cmplt &
mstr2addr_burst &
mstr2addr_size &
mstr2addr_len &
mstr2addr_addr &
mstr2addr_tag ;
-- Rip fields from FIFO output data word
sig_fifo_next_cache <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
C_TAG_WIDTH +
LEN_WIDTH +
SIZE_WIDTH +
BURST_WIDTH +
CMD_CMPLT_WIDTH +
CALC_ERROR_WIDTH + 7)
downto
(C_ADDR_WIDTH +
C_TAG_WIDTH +
LEN_WIDTH +
SIZE_WIDTH +
BURST_WIDTH +
CMD_CMPLT_WIDTH +
CALC_ERROR_WIDTH + 4)
);
sig_fifo_next_user <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
C_TAG_WIDTH +
LEN_WIDTH +
SIZE_WIDTH +
BURST_WIDTH +
CMD_CMPLT_WIDTH +
CALC_ERROR_WIDTH + 3)
downto
(C_ADDR_WIDTH +
C_TAG_WIDTH +
LEN_WIDTH +
SIZE_WIDTH +
BURST_WIDTH +
CMD_CMPLT_WIDTH +
CALC_ERROR_WIDTH)
);
sig_fifo_calc_error <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
C_TAG_WIDTH +
LEN_WIDTH +
SIZE_WIDTH +
BURST_WIDTH +
CMD_CMPLT_WIDTH +
CALC_ERROR_WIDTH)-1);
sig_fifo_next_cmd_cmplt <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
C_TAG_WIDTH +
LEN_WIDTH +
SIZE_WIDTH +
BURST_WIDTH +
CMD_CMPLT_WIDTH)-1);
sig_fifo_next_burst <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
C_TAG_WIDTH +
LEN_WIDTH +
SIZE_WIDTH +
BURST_WIDTH)-1
downto
C_ADDR_WIDTH +
C_TAG_WIDTH +
LEN_WIDTH +
SIZE_WIDTH) ;
sig_fifo_next_size <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
C_TAG_WIDTH +
LEN_WIDTH +
SIZE_WIDTH)-1
downto
C_ADDR_WIDTH +
C_TAG_WIDTH +
LEN_WIDTH) ;
sig_fifo_next_len <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
C_TAG_WIDTH +
LEN_WIDTH)-1
downto
C_ADDR_WIDTH +
C_TAG_WIDTH) ;
sig_fifo_next_addr <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
C_TAG_WIDTH)-1
downto
C_TAG_WIDTH) ;
sig_fifo_next_tag <= sig_aq_fifo_data_out(C_TAG_WIDTH-1 downto 0);
------------------------------------------------------------
-- Instance: I_ADDR_QUAL_FIFO
--
-- Description:
-- Instance for the Address/Qualifier FIFO
--
------------------------------------------------------------
I_ADDR_QUAL_FIFO : entity axi_datamover_v5_1.axi_datamover_fifo
generic map (
C_DWIDTH => ADDR_QUAL_WIDTH ,
C_DEPTH => C_ADDR_FIFO_DEPTH ,
C_IS_ASYNC => USE_SYNC_FIFO ,
C_PRIM_TYPE => FIFO_PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_fifo_wr_cmd_valid ,
fifo_wr_tready => sig_fifo_wr_cmd_ready ,
fifo_wr_tdata => sig_aq_fifo_data_in ,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_fifo_rd_cmd_valid ,
fifo_rd_tready => sig_fifo_rd_cmd_ready ,
fifo_rd_tdata => sig_aq_fifo_data_out ,
fifo_rd_empty => sig_cmd_fifo_empty
);
end generate GEN_ADDR_FIFO;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_ADDR_FIFO
--
-- If Generate Description:
-- Implements the case where no additional FIFOing is needed
-- on the input command address/qualifiers.
--
------------------------------------------------------------
GEN_NO_ADDR_FIFO : if (C_ADDR_FIFO_DEPTH = 1) generate
begin
-- Bypass FIFO
sig_fifo_next_tag <= mstr2addr_tag ;
sig_fifo_next_addr <= mstr2addr_addr ;
sig_fifo_next_len <= mstr2addr_len ;
sig_fifo_next_size <= mstr2addr_size ;
sig_fifo_next_burst <= mstr2addr_burst ;
sig_fifo_next_cache <= mstr2addr_cache ;
sig_fifo_next_user <= mstr2addr_user ;
sig_fifo_next_cmd_cmplt <= mstr2addr_cmd_cmplt ;
sig_fifo_calc_error <= mstr2addr_calc_error ;
sig_cmd_fifo_empty <= sig_addr_reg_empty ;
sig_fifo_wr_cmd_ready <= sig_fifo_rd_cmd_ready ;
sig_fifo_rd_cmd_valid <= sig_fifo_wr_cmd_valid ;
end generate GEN_NO_ADDR_FIFO;
-- Output Register Logic -------------------------------------------
sig_axi_addr <= sig_next_addr_reg ;
sig_axi_alen <= sig_next_len_reg ;
sig_axi_asize <= sig_next_size_reg ;
sig_axi_aburst <= sig_next_burst_reg ;
sig_axi_acache <= sig_next_cache_reg ;
sig_axi_auser <= sig_next_user_reg ;
sig_axi_avalid <= sig_addr_valid_reg ;
sig_calc_error <= sig_calc_error_reg ;
sig_fifo_rd_cmd_ready <= sig_addr_reg_empty and
sig_allow_addr_req and
-- obsoleted not(sig_wait_for_data) and
not(data2addr_stop_req);
sig_addr_posted <= sig_posted_to_axi ;
-- Internal signals
sig_push_addr_reg <= sig_addr_reg_empty and
sig_fifo_rd_cmd_valid and
sig_allow_addr_req and
-- obsoleted not(sig_wait_for_data) and
not(data2addr_stop_req);
sig_pop_addr_reg <= not(sig_calc_error_reg) and
sig_axi_aready and
sig_addr_reg_full;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ADDR_FIFO_REG
--
-- Process Description:
-- This process implements a register for the Address
-- Control FIFO that operates like a 1 deep Sync FIFO.
--
-------------------------------------------------------------
IMP_ADDR_FIFO_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_pop_addr_reg = '1') then
sig_next_tag_reg <= (others => '0') ;
sig_next_addr_reg <= (others => '0') ;
sig_next_len_reg <= (others => '0') ;
sig_next_size_reg <= (others => '0') ;
sig_next_burst_reg <= (others => '0') ;
sig_next_cache_reg <= (others => '0') ;
sig_next_user_reg <= (others => '0') ;
sig_next_cmd_cmplt_reg <= '0' ;
sig_addr_valid_reg <= '0' ;
sig_calc_error_reg <= '0' ;
sig_addr_reg_empty <= '1' ;
sig_addr_reg_full <= '0' ;
elsif (sig_push_addr_reg = '1') then
sig_next_tag_reg <= sig_fifo_next_tag ;
sig_next_addr_reg <= sig_fifo_next_addr ;
sig_next_len_reg <= sig_fifo_next_len ;
sig_next_size_reg <= sig_fifo_next_size ;
sig_next_burst_reg <= sig_fifo_next_burst ;
sig_next_cache_reg <= sig_fifo_next_cache ;
sig_next_user_reg <= sig_fifo_next_user ;
sig_next_cmd_cmplt_reg <= sig_fifo_next_cmd_cmplt ;
sig_addr_valid_reg <= not(sig_fifo_calc_error);
sig_calc_error_reg <= sig_fifo_calc_error ;
sig_addr_reg_empty <= '0' ;
sig_addr_reg_full <= '1' ;
else
null; -- don't change state
end if;
end if;
end process IMP_ADDR_FIFO_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_POSTED_FLAG
--
-- Process Description:
-- This implements a FLOP that creates a 1 clock wide pulse
-- indicating a new address/qualifier set has been posted to
-- the AXI Addres Channel outputs. This is used to synchronize
-- the Data Channel Controller.
--
-------------------------------------------------------------
IMP_POSTED_FLAG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_posted_to_axi <= '0';
sig_posted_to_axi_2 <= '0';
elsif (sig_push_addr_reg = '1') then
sig_posted_to_axi <= '1';
sig_posted_to_axi_2 <= '1';
else
sig_posted_to_axi <= '0';
sig_posted_to_axi_2 <= '0';
end if;
end if;
end process IMP_POSTED_FLAG;
-- PROC_CMD_DETECT : process (primary_aclk)
-- begin
-- if (mmap_reset = '1') then
-- first_addr_valid_del <= '0';
-- elsif (primary_aclk'event and primary_aclk = '1') then
-- first_addr_valid_del <= first_addr_valid;
-- end if;
-- end process PROC_CMD_DETECT;
--
-- PROC_ADDR_DET : process (primary_aclk)
-- begin
-- if (mmap_reset = '1') then
-- first_addr_valid <= '0';
-- first_addr_int <= (others => '0');
-- last_addr_int <= (others => '0');
-- elsif (primary_aclk'event and primary_aclk = '1') then
-- if (mstr2addr_cmd_valid = '1' and first_addr_valid = '0') then
-- first_addr_valid <= '1';
-- first_addr_int <= mstr2addr_addr;
-- last_addr_int <= last_addr_int;
-- elsif (mstr2addr_cmd_cmplt = '1') then
-- first_addr_valid <= '0';
-- first_addr_int <= first_addr_int;
-- last_addr_int <= mstr2addr_addr;
-- end if;
-- end if;
-- end process PROC_ADDR_DET;
--
-- latch <= first_addr_valid and (not first_addr_valid_del);
-- latch_n <= (not first_addr_valid) and first_addr_valid_del;
--
-- PROC_CACHE1 : process (primary_aclk)
-- begin
-- if (mmap_reset = '1') then
-- mstr2addr_cache_info_int <= (others => '0');
-- latch_n_del <= '0';
-- elsif (primary_aclk'event and primary_aclk = '1') then
-- if (latch_n = '1') then
-- mstr2addr_cache_info_int <= mstr2addr_cache_info;
-- end if;
-- latch_n_del <= latch_n;
-- end if;
-- end process PROC_CACHE1;
--
--
-- PROC_CACHE : process (primary_aclk)
-- begin
-- if (mmap_reset = '1') then
-- addr2axi_cache_int1 <= (others => '0');
-- first_one <= '0';
-- elsif (primary_aclk'event and primary_aclk = '1') then
-- first_one <= '0';
---- if (latch = '1' and first_one = '0') then -- first one
-- if (sig_addr_valid_reg = '0' and first_addr_valid = '0') then
-- addr2axi_cache_int1 <= mstr2addr_cache_info;
---- first_one <= '1';
---- elsif (latch_n_del = '1') then
---- addr2axi_cache_int <= mstr2addr_cache_info_int;
-- elsif ((first_addr_int = sig_next_addr_reg) and (sig_addr_valid_reg = '1')) then
-- addr2axi_cache_int1 <= addr2axi_cache_int1; --mstr2addr_cache_info (7 downto 4);
-- elsif ((last_addr_int >= sig_next_addr_reg) and (sig_addr_valid_reg = '1')) then
-- addr2axi_cache_int1 <= addr2axi_cache_int1; --mstr2addr_cache_info (7 downto 4);
-- end if;
-- end if;
-- end process PROC_CACHE;
--
--
-- PROC_CACHE2 : process (primary_aclk)
-- begin
-- if (mmap_reset = '1') then
-- addr2axi_cache_int <= (others => '0');
-- elsif (primary_aclk'event and primary_aclk = '1') then
-- addr2axi_cache_int <= addr2axi_cache_int1;
-- end if;
-- end process PROC_CACHE2;
--
--addr2axi_cache <= addr2axi_cache_int (3 downto 0);
--addr2axi_user <= addr2axi_cache_int (7 downto 4);
--
end implementation;
|
mit
|
UVVM/UVVM_All
|
bitvis_vip_gpio/src/vvc_cmd_pkg.vhd
|
1
|
6921
|
--================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
----------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
use work.transaction_pkg.all;
--========================================================================================================================
--========================================================================================================================
package vvc_cmd_pkg is
alias t_operation is work.transaction_pkg.t_operation;
--========================================================================================================================
-- t_vvc_cmd_record
-- - Record type used for communication with the VVC
--========================================================================================================================
type t_vvc_cmd_record is record
-- Common UVVM fields (Used by td_vvc_framework_common_methods_pkg procedures, and thus mandatory)
operation : t_operation;
proc_call : string(1 to C_VVC_CMD_STRING_MAX_LENGTH);
msg : string(1 to C_VVC_CMD_STRING_MAX_LENGTH);
data_routing : t_data_routing;
cmd_idx : natural;
command_type : t_immediate_or_queued; -- QUEUED/IMMEDIATE
msg_id : t_msg_id;
gen_integer_array : t_integer_array(0 to 1); -- Increase array length if needed
gen_boolean : boolean; -- Generic boolean
timeout : time;
alert_level : t_alert_level;
delay : time;
quietness : t_quietness;
parent_msg_id_panel : t_msg_id_panel;
-- VVC dedicated fields
data : std_logic_vector(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0);
data_exp : std_logic_vector(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0);
stable_req : time;
stable_req_from : t_from_point_in_time;
end record;
constant C_VVC_CMD_DEFAULT : t_vvc_cmd_record := (
-- Common VVC fields
operation => NO_OPERATION, -- Default unless overwritten by a common operation
alert_level => failure,
proc_call => (others => NUL),
msg => (others => NUL),
data_routing => NA,
cmd_idx => 0,
command_type => NO_command_type,
msg_id => NO_ID,
gen_integer_array => (others => -1),
gen_boolean => false,
timeout => 0 ns,
delay => 0 ns,
quietness => NON_QUIET,
parent_msg_id_panel => C_UNUSED_MSG_ID_PANEL,
-- VVC dedicated fields
data => (others => '0'),
data_exp => (others => '0'),
stable_req => 0 ns,
stable_req_from => FROM_NOW
);
--========================================================================================================================
-- shared_vvc_cmd
-- - Shared variable used for transmitting VVC commands
--========================================================================================================================
shared variable shared_vvc_cmd : t_vvc_cmd_record := C_VVC_CMD_DEFAULT;
--===============================================================================================
-- t_vvc_result, t_vvc_result_queue_element, t_vvc_response and shared_vvc_response :
--
-- - These are used for storing the result of the read/receive BFM commands issued by the VVC,
-- - so that the result can be transported from the VVC to the sequencer via a
-- a fetch_result() call as described in VVC_Framework_common_methods_QuickRef
--
-- - t_vvc_result matches the return value of read/receive procedure in the BFM.
--===============================================================================================
subtype t_vvc_result is std_logic_vector(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0);
type t_vvc_result_queue_element is record
cmd_idx : natural; -- from UVVM handshake mechanism
result : t_vvc_result;
end record;
type t_vvc_response is record
fetch_is_accepted : boolean;
transaction_result : t_transaction_result;
result : t_vvc_result;
end record;
shared variable shared_vvc_response : t_vvc_response;
--===============================================================================================
-- t_last_received_cmd_idx :
-- - Used to store the last queued cmd in vvc interpreter.
--===============================================================================================
type t_last_received_cmd_idx is array (t_channel range <>, natural range <>) of integer;
--===============================================================================================
-- shared_vvc_last_received_cmd_idx
-- - Shared variable used to get last queued index from vvc to sequencer
--===============================================================================================
shared variable shared_vvc_last_received_cmd_idx : t_last_received_cmd_idx(t_channel'left to t_channel'right, 0 to C_MAX_VVC_INSTANCE_NUM-1) := (others => (others => -1));
end package vvc_cmd_pkg;
package body vvc_cmd_pkg is
end package body vvc_cmd_pkg;
|
mit
|
UVVM/UVVM_All
|
bitvis_vip_ethernet/src/ethernet_vvc.vhd
|
1
|
5189
|
--================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
----------------------------------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
---------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
use work.support_pkg.all;
--==========================================================================================
entity ethernet_vvc is
generic (
GC_INSTANCE_IDX : natural;
GC_PHY_INTERFACE : t_interface;
GC_PHY_VVC_INSTANCE_IDX : natural;
GC_PHY_MAX_ACCESS_TIME : time := 1 us;
GC_DUT_IF_FIELD_CONFIG : t_dut_if_field_config_direction_array := C_DUT_IF_FIELD_CONFIG_DIRECTION_ARRAY_DEFAULT;
GC_ETHERNET_PROTOCOL_CONFIG : t_ethernet_protocol_config := C_ETHERNET_PROTOCOL_CONFIG_DEFAULT;
GC_CMD_QUEUE_COUNT_MAX : natural := 1000;
GC_CMD_QUEUE_COUNT_THRESHOLD : natural := 950;
GC_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY : t_alert_level := WARNING;
GC_RESULT_QUEUE_COUNT_MAX : natural := 1000;
GC_RESULT_QUEUE_COUNT_THRESHOLD : natural := 950;
GC_RESULT_QUEUE_COUNT_THRESHOLD_SEVERITY : t_alert_level := WARNING
);
end entity ethernet_vvc;
--==========================================================================================
--==========================================================================================
architecture struct of ethernet_vvc is
begin
-- ETHERNET TX VVC
i_ethernet_tx: entity work.ethernet_tx_vvc
generic map(
GC_INSTANCE_IDX => GC_INSTANCE_IDX,
GC_CHANNEL => TX,
GC_PHY_INTERFACE => GC_PHY_INTERFACE,
GC_PHY_VVC_INSTANCE_IDX => GC_PHY_VVC_INSTANCE_IDX,
GC_PHY_MAX_ACCESS_TIME => GC_PHY_MAX_ACCESS_TIME,
GC_DUT_IF_FIELD_CONFIG => GC_DUT_IF_FIELD_CONFIG,
GC_ETHERNET_PROTOCOL_CONFIG => GC_ETHERNET_PROTOCOL_CONFIG,
GC_CMD_QUEUE_COUNT_MAX => GC_CMD_QUEUE_COUNT_MAX,
GC_CMD_QUEUE_COUNT_THRESHOLD => GC_CMD_QUEUE_COUNT_THRESHOLD,
GC_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY => GC_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY,
GC_RESULT_QUEUE_COUNT_MAX => GC_RESULT_QUEUE_COUNT_MAX,
GC_RESULT_QUEUE_COUNT_THRESHOLD => GC_RESULT_QUEUE_COUNT_THRESHOLD,
GC_RESULT_QUEUE_COUNT_THRESHOLD_SEVERITY => GC_RESULT_QUEUE_COUNT_THRESHOLD_SEVERITY
);
-- ETHERNET RX VVC
i_ethernet_rx: entity work.ethernet_rx_vvc
generic map(
GC_INSTANCE_IDX => GC_INSTANCE_IDX,
GC_CHANNEL => RX,
GC_PHY_INTERFACE => GC_PHY_INTERFACE,
GC_PHY_VVC_INSTANCE_IDX => GC_PHY_VVC_INSTANCE_IDX,
GC_PHY_MAX_ACCESS_TIME => GC_PHY_MAX_ACCESS_TIME,
GC_DUT_IF_FIELD_CONFIG => GC_DUT_IF_FIELD_CONFIG,
GC_ETHERNET_PROTOCOL_CONFIG => GC_ETHERNET_PROTOCOL_CONFIG,
GC_CMD_QUEUE_COUNT_MAX => GC_CMD_QUEUE_COUNT_MAX,
GC_CMD_QUEUE_COUNT_THRESHOLD => GC_CMD_QUEUE_COUNT_THRESHOLD,
GC_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY => GC_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY,
GC_RESULT_QUEUE_COUNT_MAX => GC_RESULT_QUEUE_COUNT_MAX,
GC_RESULT_QUEUE_COUNT_THRESHOLD => GC_RESULT_QUEUE_COUNT_THRESHOLD,
GC_RESULT_QUEUE_COUNT_THRESHOLD_SEVERITY => GC_RESULT_QUEUE_COUNT_THRESHOLD_SEVERITY
);
end struct;
|
mit
|
UVVM/UVVM_All
|
bitvis_vip_spec_cov/src/spec_cov_pkg.vhd
|
1
|
24084
|
--================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
----------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
use std.textio.all;
use work.csv_file_reader_pkg.all;
use work.local_adaptations_pkg.all;
package spec_cov_pkg is
file RESULT_FILE : text;
procedure initialize_req_cov(
constant testcase : string;
constant req_list_file : string;
constant partial_cov_file : string
);
-- Overloading procedure
procedure initialize_req_cov(
constant testcase : string;
constant partial_cov_file : string
);
procedure tick_off_req_cov(
constant requirement : string;
constant test_status : t_test_status := NA;
constant msg : string := "";
constant tickoff_extent : t_extent_tickoff := LIST_SINGLE_TICKOFF;
constant scope : string := C_SCOPE
);
procedure cond_tick_off_req_cov(
constant requirement : string;
constant test_status : t_test_status := NA;
constant msg : string := "";
constant tickoff_extent : t_extent_tickoff := LIST_SINGLE_TICKOFF;
constant scope : string := C_SCOPE
);
procedure disable_cond_tick_off_req_cov(
constant requirement : string
);
procedure enable_cond_tick_off_req_cov(
constant requirement : string
);
procedure finalize_req_cov(
constant VOID : t_void
);
--=================================================================================================
-- Functions and procedures declared below this line are intended as private internal functions
--=================================================================================================
procedure priv_log_entry(
constant index : natural
);
procedure priv_read_and_parse_csv_file(
constant req_list_file : string
);
procedure priv_initialize_result_file(
constant file_name : string
);
impure function priv_get_description(
requirement : string
) return string;
impure function priv_requirement_exists(
requirement : string
) return boolean;
impure function priv_get_num_requirement_tick_offs(
requirement : string
) return natural;
procedure priv_inc_num_requirement_tick_offs(
requirement : string
);
function priv_test_status_to_string(
constant test_status : t_test_status
) return string;
impure function priv_get_summary_string
return string;
procedure priv_set_default_testcase_name(
constant testcase : string
);
impure function priv_get_default_testcase_name
return string;
impure function priv_find_string_length(
constant search_string : string
) return natural;
impure function priv_get_requirement_name_length(
requirement : string)
return natural;
impure function priv_req_listed_in_disabled_tick_off_array(
constant requirement : string
) return boolean;
end package spec_cov_pkg;
--=================================================================================================
--=================================================================================================
--=================================================================================================
package body spec_cov_pkg is
constant C_FAIL_STRING : string := "FAIL";
constant C_PASS_STRING : string := "PASS";
type t_line_vector is array(0 to shared_spec_cov_config.max_testcases_per_req-1) of line;
type t_requirement_entry is record
valid : boolean;
requirement : line;
description : line;
num_tcs : natural;
tc_list : t_line_vector;
num_tickoffs : natural;
end record;
type t_requirement_entry_array is array (natural range <>) of t_requirement_entry;
-- Shared variables used internally in this context
shared variable priv_csv_file : csv_file_reader_type;
shared variable priv_requirement_array : t_requirement_entry_array(0 to shared_spec_cov_config.max_requirements);
shared variable priv_requirements_in_array : natural := 0;
shared variable priv_testcase_name : string(1 to C_CSV_FILE_MAX_LINE_LENGTH) := (others => NUL);
shared variable priv_testcase_passed : boolean;
shared variable priv_requirement_file_exists : boolean;
type t_disabled_tick_off_array is array(0 to shared_spec_cov_config.max_requirements) of string(1 to C_CSV_FILE_MAX_LINE_LENGTH);
shared variable priv_disabled_tick_off_array : t_disabled_tick_off_array := (others => (others => NUL));
--
-- Initialize testcase requirement coverage
--
procedure initialize_req_cov(
constant testcase : string;
constant req_list_file : string;
constant partial_cov_file : string
) is
begin
priv_set_default_testcase_name(testcase);
-- update pkg local variables
priv_testcase_passed := true;
priv_requirement_file_exists := true;
priv_read_and_parse_csv_file(req_list_file);
priv_initialize_result_file(partial_cov_file);
end procedure initialize_req_cov;
-- Overloading procedure
procedure initialize_req_cov(
constant testcase : string;
constant partial_cov_file : string
) is
begin
log(ID_SPEC_COV, "Requirement Coverage initialized with no requirement file.", C_SCOPE);
priv_set_default_testcase_name(testcase);
-- update pkg local variables
priv_testcase_passed := true;
priv_requirement_file_exists := false;
priv_initialize_result_file(partial_cov_file);
end procedure initialize_req_cov;
--
-- Log the requirement and testcase
--
procedure tick_off_req_cov(
constant requirement : string;
constant test_status : t_test_status := NA;
constant msg : string := "";
constant tickoff_extent : t_extent_tickoff := LIST_SINGLE_TICKOFF;
constant scope : string := C_SCOPE
) is
variable v_requirement_to_file_line : line;
variable v_requirement_status : t_test_status;
variable v_prev_test_status : t_test_status;
begin
if priv_requirements_in_array = 0 and priv_requirement_file_exists = true then
alert(TB_ERROR, "Requirements have not been parsed. Please use initialize_req_cov() with a requirement file before calling tick_off_req_cov().", scope);
return;
end if;
-- Check if requirement exists
if (priv_requirement_exists(requirement) = false) and (priv_requirement_file_exists = true) then
alert(shared_spec_cov_config.missing_req_label_severity, "Requirement not found in requirement list: " & to_string(requirement), C_SCOPE);
end if;
-- Save testcase status
if priv_testcase_passed then
v_prev_test_status := PASS;
else
v_prev_test_status := FAIL;
end if;
---- Check if there were any errors globally or testcase was explicit set to FAIL
if (shared_uvvm_status.found_unexpected_simulation_errors_or_worse = 1) or (test_status = FAIL) then
v_requirement_status := FAIL;
-- Set failing testcase for finishing summary line
priv_testcase_passed := false;
else
v_requirement_status := PASS;
end if;
-- Check if requirement tick-off should be written
if (tickoff_extent = LIST_EVERY_TICKOFF) or (priv_get_num_requirement_tick_offs(requirement) = 0) or
(v_prev_test_status = PASS and test_status = FAIL) then
-- Log result to transcript
log(ID_SPEC_COV, "Logging requirement " & requirement & " [" & priv_test_status_to_string(v_requirement_status) & "]. '" &
priv_get_description(requirement) & "'. " & msg, scope);
-- Log to file
write(v_requirement_to_file_line, requirement & C_CSV_DELIMITER & priv_get_default_testcase_name & C_CSV_DELIMITER & priv_test_status_to_string(v_requirement_status));
writeline(RESULT_FILE, v_requirement_to_file_line);
-- Increment number of tick off for this requirement
priv_inc_num_requirement_tick_offs(requirement);
end if;
end procedure tick_off_req_cov;
--
-- Conditional tick_off_req_cov() for selected requirement.
-- If the requirement has been enabled for conditional tick_off_req_cov()
-- with enable_cond_tick_off_req_cov() it will not be ticked off.
procedure cond_tick_off_req_cov(
constant requirement : string;
constant test_status : t_test_status := NA;
constant msg : string := "";
constant tickoff_extent : t_extent_tickoff := LIST_SINGLE_TICKOFF;
constant scope : string := C_SCOPE
) is
begin
-- Check: is requirement listed in the conditional tick off array?
if priv_req_listed_in_disabled_tick_off_array(requirement) = false then
-- requirement was not listed, call tick off method.
tick_off_req_cov(requirement, test_status, msg, tickoff_extent, scope);
end if;
end procedure cond_tick_off_req_cov;
--
-- Disable conditional tick_off_req_cov() setting for
-- selected requirement.
--
procedure disable_cond_tick_off_req_cov(
constant requirement : string
) is
constant c_requirement_length : natural := priv_get_requirement_name_length(requirement);
begin
-- Check: is requirement already tracked?
-- method will also check if the requirement exist in the requirement file.
if priv_req_listed_in_disabled_tick_off_array(requirement) = true then
alert(TB_WARNING, "Requirement " & requirement & " is already listed in the conditional tick off array.", C_SCOPE);
return;
end if;
-- add requirement to conditional tick off array.
for idx in 0 to priv_disabled_tick_off_array'length-1 loop
-- find a free entry, add requirement and exit loop
if priv_disabled_tick_off_array(idx)(1) = NUL then
priv_disabled_tick_off_array(idx)(1 to c_requirement_length) := to_upper(requirement);
exit;
end if;
end loop;
end procedure disable_cond_tick_off_req_cov;
--
-- Enable conditional tick_off_req_cov() setting for
-- selected requirement.
--
procedure enable_cond_tick_off_req_cov(
constant requirement : string
) is
constant c_requirement_length : natural := priv_get_requirement_name_length(requirement);
begin
-- Check: is requirement not tracked?
-- method will also check if the requirement exist in the requirement file.
if priv_req_listed_in_disabled_tick_off_array(requirement) = false then
alert(TB_WARNING, "Requirement " & requirement & " is not listed in the conditional tick off array.", C_SCOPE);
else -- requirement is tracked
-- find the requirement and wipe it out from conditional tick off array
for idx in 0 to priv_disabled_tick_off_array'length-1 loop
-- found requirement, wipe the entry and exit
if priv_disabled_tick_off_array(idx)(1 to c_requirement_length) = to_upper(requirement) then
priv_disabled_tick_off_array(idx) := (others => NUL);
exit;
end if;
end loop;
end if;
end procedure enable_cond_tick_off_req_cov;
--
-- Deallocate memory usage and write summary line to partial_cov file
--
procedure finalize_req_cov(
constant VOID : t_void
) is
variable v_checksum_string : line;
begin
-- Free used memory
log(ID_SPEC_COV, "Freeing stored requirements from memory", C_SCOPE);
for i in 0 to priv_requirements_in_array-1 loop
deallocate(priv_requirement_array(i).requirement);
deallocate(priv_requirement_array(i).description);
for tc in 0 to priv_requirement_array(i).num_tcs-1 loop
deallocate(priv_requirement_array(i).tc_list(tc));
end loop;
priv_requirement_array(i).num_tcs := 0;
priv_requirement_array(i).valid := false;
priv_requirement_array(i).num_tickoffs := 0;
end loop;
priv_requirements_in_array := 0;
-- Add closing line
log(ID_SPEC_COV, "Marking requirement coverage result.", C_SCOPE);
write(v_checksum_string, priv_get_summary_string);
writeline(RESULT_FILE, v_checksum_string);
file_close(RESULT_FILE);
log(ID_SPEC_COV, "Requirement coverage finalized.", C_SCOPE);
end procedure finalize_req_cov;
--=================================================================================================
-- Functions and procedures declared below this line are intended as private internal functions
--=================================================================================================
--
-- Initialize the partial_cov result file
--
procedure priv_initialize_result_file(
constant file_name : string
) is
variable v_file_open_status : FILE_OPEN_STATUS;
variable v_settings_to_file_line : line;
begin
file_open(v_file_open_status, RESULT_FILE, file_name, write_mode);
check_file_open_status(v_file_open_status, file_name);
-- Write info and settings to CSV file for Python post-processing script
log(ID_SPEC_COV, "Adding test and configuration information to coverage file. ", C_SCOPE);
write(v_settings_to_file_line, "NOTE: This coverage file is only valid when the last line is 'SUMMARY, " & priv_get_default_testcase_name & ", PASS'" & LF);
write(v_settings_to_file_line, "TESTCASE_NAME: " & priv_get_default_testcase_name & LF);
write(v_settings_to_file_line, "DELIMITER: " & shared_spec_cov_config.csv_delimiter & LF);
writeline(RESULT_FILE, v_settings_to_file_line);
end procedure priv_initialize_result_file;
--
-- Read requirement CSV file
--
procedure priv_read_and_parse_csv_file(
constant req_list_file : string
) is
variable v_tc_valid : boolean;
variable v_file_ok : boolean;
begin
log(ID_SPEC_COV, "Reading and parsing requirement file, " & req_list_file, C_SCOPE);
if priv_requirements_in_array > 0 then
alert(TB_ERROR, "Requirements have already been read from file, please call finalize_req_cov before starting a new requirement coverage process.", C_SCOPE);
return;
end if;
-- Open file and check status, return if failing
v_file_ok := priv_csv_file.initialize(req_list_file, C_CSV_DELIMITER);
if v_file_ok = false then
return;
end if;
-- File ok, read file
while not priv_csv_file.end_of_file loop
priv_csv_file.readline;
-- Read requirement
priv_requirement_array(priv_requirements_in_array).requirement := new string'(priv_csv_file.read_string);
-- Read description
priv_requirement_array(priv_requirements_in_array).description := new string'(priv_csv_file.read_string);
-- Read testcases
v_tc_valid := true;
priv_requirement_array(priv_requirements_in_array).num_tcs := 0;
while v_tc_valid loop
priv_requirement_array(priv_requirements_in_array).tc_list(priv_requirement_array(priv_requirements_in_array).num_tcs) := new string'(priv_csv_file.read_string);
if (priv_requirement_array(priv_requirements_in_array).tc_list(priv_requirement_array(priv_requirements_in_array).num_tcs).all(1) /= NUL) then
priv_requirement_array(priv_requirements_in_array).num_tcs := priv_requirement_array(priv_requirements_in_array).num_tcs + 1;
else
v_tc_valid := false;
end if;
end loop;
-- Validate entry
priv_requirement_array(priv_requirements_in_array).valid := true;
-- Set number of tickoffs for this requirement to 0
priv_requirement_array(priv_requirements_in_array).num_tickoffs := 0;
priv_log_entry(priv_requirements_in_array);
priv_requirements_in_array := priv_requirements_in_array + 1;
end loop;
log(ID_SPEC_COV, "Closing requirement file", C_SCOPE);
priv_csv_file.dispose;
end procedure priv_read_and_parse_csv_file;
--
-- Log CSV readout to terminal
--
procedure priv_log_entry(
constant index : natural
) is
begin
if priv_requirement_array(index).valid then
-- log requirement and description to terminal
log(ID_SPEC_COV, "Requirement: " & priv_requirement_array(index).requirement.all, C_SCOPE);
log(ID_SPEC_COV, "Description: " & priv_requirement_array(index).description.all, C_SCOPE);
-- log testcases to terminal
for i in 0 to priv_requirement_array(index).num_tcs-1 loop
log(ID_SPEC_COV, " TC: " & priv_requirement_array(index).tc_list(i).all, C_SCOPE);
end loop;
else
log(ID_SPEC_COV, "Requirement entry was not valid", C_SCOPE);
end if;
end procedure priv_log_entry;
--
-- Check if requirement exists, return boolean
--
impure function priv_requirement_exists(
requirement : string
) return boolean is
begin
for i in 0 to priv_requirements_in_array-1 loop
if priv_get_requirement_name_length(priv_requirement_array(i).requirement.all) = requirement'length then
if to_upper(priv_requirement_array(i).requirement.all(1 to requirement'length)) = to_upper(requirement(1 to requirement'length)) then
return true;
end if;
end if;
end loop;
return false;
end function priv_requirement_exists;
--
-- Get number of tick offs for requirement
--
impure function priv_get_num_requirement_tick_offs(
requirement : string
) return natural is
begin
for i in 0 to priv_requirements_in_array-1 loop
if priv_get_requirement_name_length(priv_requirement_array(i).requirement.all) = requirement'length then
if to_upper(priv_requirement_array(i).requirement.all(1 to requirement'length)) = to_upper(requirement(1 to requirement'length)) then
return priv_requirement_array(i).num_tickoffs;
end if;
end if;
end loop;
return 0;
end function priv_get_num_requirement_tick_offs;
--
-- Increment number of tick offs for requirement
--
procedure priv_inc_num_requirement_tick_offs(
requirement : string
) is
begin
for i in 0 to priv_requirements_in_array-1 loop
if priv_get_requirement_name_length(priv_requirement_array(i).requirement.all) = requirement'length then
if to_upper(priv_requirement_array(i).requirement.all(1 to requirement'length)) = to_upper(requirement(1 to requirement'length)) then
priv_requirement_array(i).num_tickoffs := priv_requirement_array(i).num_tickoffs + 1;
end if;
end if;
end loop;
end procedure priv_inc_num_requirement_tick_offs;
--
-- Get description of requirement
--
impure function priv_get_description(
requirement : string
) return string is
begin
for i in 0 to priv_requirements_in_array-1 loop
if priv_requirement_array(i).requirement.all(1 to requirement'length) = requirement(1 to requirement'length) then
-- Found requirement
return priv_requirement_array(i).description.all;
end if;
end loop;
if priv_requirement_file_exists = false then
return "";
else
return "DESCRIPTION NOT FOUND";
end if;
end function priv_get_description;
--
-- Get the t_test_status parameter as string
--
function priv_test_status_to_string(
constant test_status : t_test_status
) return string is
begin
if test_status = PASS then
return C_PASS_STRING;
else -- test_status = FAIL
return C_FAIL_STRING;
end if;
end function priv_test_status_to_string;
--
-- Get a string for finalize summary in the partial_cov CSV file.
--
impure function priv_get_summary_string
return string is
begin
-- Create a CSV coverage file summary string
if (priv_testcase_passed = true) and (shared_uvvm_status.found_unexpected_simulation_errors_or_worse = 0) then
return "SUMMARY, " & priv_get_default_testcase_name & ", " & C_PASS_STRING;
else
return "SUMMARY, " & priv_get_default_testcase_name & ", " & C_FAIL_STRING;
end if;
end function priv_get_summary_string;
--
-- Set the default testcase name.
--
procedure priv_set_default_testcase_name(
constant testcase : string
) is
begin
priv_testcase_name(1 to testcase'length) := testcase;
end procedure priv_set_default_testcase_name;
--
-- Return the default testcase name set when initialize_req_cov() was called.
--
impure function priv_get_default_testcase_name
return string is
variable v_testcase_length : natural := priv_find_string_length(priv_testcase_name);
begin
return priv_testcase_name(1 to v_testcase_length);
end function priv_get_default_testcase_name;
--
-- Find the length of a string which will contain NUL characters.
--
impure function priv_find_string_length(
constant search_string : string
) return natural is
variable v_return : natural := 0;
begin
-- loop string until NUL is found and return idx-1
for idx in 1 to search_string'length loop
if search_string(idx) = NUL then
return idx - 1;
end if;
end loop;
-- NUL was not found, return full length
return search_string'length;
end function priv_find_string_length;
--
-- Get length of requirement name
--
impure function priv_get_requirement_name_length(
requirement : string)
return natural is
variable v_length : natural := 0;
begin
for i in 1 to requirement'length loop
if requirement(i) = NUL then
exit;
else
v_length := v_length + 1;
end if;
end loop;
return v_length;
end function priv_get_requirement_name_length;
--
-- Check if requirement is listed in the priv_disabled_tick_off_array() array.
--
impure function priv_req_listed_in_disabled_tick_off_array(
constant requirement : string
) return boolean is
constant c_requirement_length : natural := priv_get_requirement_name_length(requirement);
begin
-- Check if requirement exists
if (priv_requirement_exists(requirement) = false) and (priv_requirement_file_exists = true) then
alert(shared_spec_cov_config.missing_req_label_severity, "Requirement not found in requirement list: " & to_string(requirement), C_SCOPE);
end if;
-- Check if requirement is listed in priv_disabled_tick_off_array() array
for idx in 0 to priv_disabled_tick_off_array'length-1 loop
-- found
if priv_disabled_tick_off_array(idx)(1 to c_requirement_length) = to_upper(requirement(1 to c_requirement_length)) then
return true;
end if;
end loop;
-- not found
return false;
end function priv_req_listed_in_disabled_tick_off_array;
end package body spec_cov_pkg;
|
mit
|
UVVM/UVVM_All
|
bitvis_vip_i2c/src/vvc_methods_pkg.vhd
|
1
|
48443
|
--================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
----------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
library bitvis_vip_scoreboard;
use bitvis_vip_scoreboard.generic_sb_support_pkg.all;
use work.i2c_bfm_pkg.all;
use work.vvc_cmd_pkg.all;
use work.td_vvc_framework_common_methods_pkg.all;
use work.td_target_support_pkg.all;
use work.transaction_pkg.all;
--=================================================================================================
--=================================================================================================
--=================================================================================================
package vvc_methods_pkg is
--===============================================================================================
-- Types and constants for the I2C VVC
--===============================================================================================
constant C_VVC_NAME : string := "I2C_VVC";
signal I2C_VVCT : t_vvc_target_record := set_vvc_target_defaults(C_VVC_NAME);
alias THIS_VVCT : t_vvc_target_record is I2C_VVCT;
alias t_bfm_config is t_i2c_bfm_config;
constant C_I2C_INTER_BFM_DELAY_DEFAULT : t_inter_bfm_delay := (
delay_type => NO_DELAY,
delay_in_time => 0 ns,
inter_bfm_delay_violation_severity => warning
);
type t_vvc_config is record
inter_bfm_delay : t_inter_bfm_delay; -- Minimum delay between BFM accesses from the VVC. If parameter delay_type is set to NO_DELAY, BFM accesses will be back to back, i.e. no delay.
cmd_queue_count_max : natural; -- Maximum pending number in command queue before queue is full. Adding additional commands will result in an ERROR.
cmd_queue_count_threshold : natural; -- An alert with severity 'cmd_queue_count_threshold_severity' will be issued if command queue exceeds this count.
-- Used for early warning if command queue is almost full. Will be ignored if set to 0.
cmd_queue_count_threshold_severity : t_alert_level; -- Severity of alert to be initiated if exceeding cmd_queue_count_threshold
result_queue_count_max : natural; -- Maximum number of unfetched results before result_queue is full.
result_queue_count_threshold_severity : t_alert_level; -- An alert with severity 'result_queue_count_threshold_severity' will be issued if command queue exceeds this count.
-- Used for early warning if result queue is almost full. Will be ignored if set to 0.
result_queue_count_threshold : natural; -- Severity of alert to be initiated if exceeding result_queue_count_threshold
bfm_config : t_i2c_bfm_config; -- Configuration for the BFM. See BFM quick reference
msg_id_panel : t_msg_id_panel; -- VVC dedicated message ID panel
parent_msg_id_panel : t_msg_id_panel; --UVVM: temporary fix for HVVC, remove in v3.0
end record;
type t_vvc_config_array is array (natural range <>) of t_vvc_config;
constant C_I2C_VVC_CONFIG_DEFAULT : t_vvc_config := (
inter_bfm_delay => C_I2C_INTER_BFM_DELAY_DEFAULT,
cmd_queue_count_max => C_CMD_QUEUE_COUNT_MAX,
cmd_queue_count_threshold => C_CMD_QUEUE_COUNT_THRESHOLD,
cmd_queue_count_threshold_severity => C_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY,
result_queue_count_max => C_RESULT_QUEUE_COUNT_MAX,
result_queue_count_threshold_severity => C_RESULT_QUEUE_COUNT_THRESHOLD_SEVERITY,
result_queue_count_threshold => C_RESULT_QUEUE_COUNT_THRESHOLD,
bfm_config => C_I2C_BFM_CONFIG_DEFAULT,
msg_id_panel => C_VVC_MSG_ID_PANEL_DEFAULT,
parent_msg_id_panel => C_VVC_MSG_ID_PANEL_DEFAULT
);
type t_vvc_status is record
current_cmd_idx : natural;
previous_cmd_idx : natural;
pending_cmd_cnt : natural;
end record;
type t_vvc_status_array is array (natural range <>) of t_vvc_status;
constant C_VVC_STATUS_DEFAULT : t_vvc_status := (
current_cmd_idx => 0,
previous_cmd_idx => 0,
pending_cmd_cnt => 0
);
-- Transaction information for the wave view during simulation
type t_transaction_info is record
operation : t_operation;
msg : string(1 to C_VVC_CMD_STRING_MAX_LENGTH);
addr : unsigned(C_VVC_CMD_ADDR_MAX_LENGTH - 1 downto 0);
data : t_byte_array(0 to C_VVC_CMD_DATA_MAX_LENGTH-1);
num_bytes : natural;
action_when_transfer_is_done : t_action_when_transfer_is_done;
exp_ack : boolean;
end record;
type t_transaction_info_array is array (natural range <>) of t_transaction_info;
constant C_TRANSACTION_INFO_DEFAULT : t_transaction_info := (
addr => (others => '0'),
data => (others => (others => '0')),
num_bytes => 0,
operation => NO_OPERATION,
msg => (others => ' '),
action_when_transfer_is_done => RELEASE_LINE_AFTER_TRANSFER,
exp_ack => true
);
shared variable shared_i2c_vvc_config : t_vvc_config_array(0 to C_MAX_VVC_INSTANCE_NUM-1) := (others => C_I2C_VVC_CONFIG_DEFAULT);
shared variable shared_i2c_vvc_status : t_vvc_status_array(0 to C_MAX_VVC_INSTANCE_NUM-1) := (others => C_VVC_STATUS_DEFAULT);
shared variable shared_i2c_transaction_info : t_transaction_info_array(0 to C_MAX_VVC_INSTANCE_NUM-1) := (others => C_TRANSACTION_INFO_DEFAULT);
-- Scoreboard
package i2c_sb_pkg is new bitvis_vip_scoreboard.generic_sb_pkg
generic map (t_element => std_logic_vector(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0),
element_match => std_match,
to_string_element => to_string);
use i2c_sb_pkg.all;
shared variable I2C_VVC_SB : i2c_sb_pkg.t_generic_sb;
--==========================================================================================
-- Methods dedicated to this VVC
-- - These procedures are called from the testbench in order for the VVC to execute
-- BFM calls towards the given interface. The VVC interpreter will queue these calls
-- and then the VVC executor will fetch the commands from the queue and handle the
-- actual BFM execution.
-- For details on how the BFM procedures work, see the QuickRef.
--==========================================================================================
-- *****************************************************************************
--
-- master transmit
--
-- *****************************************************************************
-- multi-byte
procedure i2c_master_transmit(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant addr : in unsigned;
constant data : in t_byte_array;
constant msg : in string;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
);
-- single byte
procedure i2c_master_transmit(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant addr : in unsigned;
constant data : in std_logic_vector;
constant msg : in string;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
);
-- *****************************************************************************
--
-- slave transmit
--
-- *****************************************************************************
-- multi-byte
procedure i2c_slave_transmit(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data : in t_byte_array;
constant msg : in string;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
);
-- single byte
procedure i2c_slave_transmit(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data : in std_logic_vector;
constant msg : in string;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
);
-- *****************************************************************************
--
-- master receive
--
-- *****************************************************************************
procedure i2c_master_receive(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant addr : in unsigned;
constant num_bytes : in natural;
constant data_routing : in t_data_routing;
constant msg : in string;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
);
procedure i2c_master_receive(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant addr : in unsigned;
constant num_bytes : in natural;
constant msg : in string;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
);
-- *****************************************************************************
--
-- master check
--
-- *****************************************************************************
-- multi-byte
procedure i2c_master_check(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant addr : in unsigned;
constant data : in t_byte_array;
constant msg : in string;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
);
-- single byte
procedure i2c_master_check(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant addr : in unsigned;
constant data : in std_logic_vector;
constant msg : in string;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
);
procedure i2c_master_quick_command(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant addr : in unsigned;
constant msg : in string;
constant rw_bit : in std_logic := C_WRITE_BIT;
constant exp_ack : in boolean := true;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
);
-- *****************************************************************************
--
-- slave receive
--
-- *****************************************************************************
procedure i2c_slave_receive(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant num_bytes : in natural;
constant data_routing : in t_data_routing;
constant msg : in string;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
);
procedure i2c_slave_receive(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant num_bytes : in natural;
constant msg : in string;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
);
-- *****************************************************************************
--
-- slave check
--
-- *****************************************************************************
-- multi-byte
procedure i2c_slave_check(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data : in t_byte_array;
constant msg : in string;
constant alert_level : in t_alert_level := error;
constant rw_bit : in std_logic := '0'; -- Default write bit
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
);
-- single byte
procedure i2c_slave_check(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data : in std_logic_vector;
constant msg : in string;
constant alert_level : in t_alert_level := error;
constant rw_bit : in std_logic := '0'; -- Default write bit
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
);
procedure i2c_slave_check(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant rw_bit : in std_logic;
constant msg : in string;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
);
--==============================================================================
-- Transaction info methods
--==============================================================================
procedure set_global_vvc_transaction_info(
signal vvc_transaction_info_trigger : inout std_logic;
variable vvc_transaction_info_group : inout t_transaction_group;
constant vvc_cmd : in t_vvc_cmd_record;
constant vvc_config : in t_vvc_config;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT);
procedure reset_vvc_transaction_info(
variable vvc_transaction_info_group : inout t_transaction_group;
constant vvc_cmd : in t_vvc_cmd_record);
--==============================================================================
-- VVC Activity
--==============================================================================
procedure update_vvc_activity_register( signal global_trigger_vvc_activity_register : inout std_logic;
variable vvc_status : inout t_vvc_status;
constant activity : in t_activity;
constant entry_num_in_vvc_activity_register : in integer;
constant last_cmd_idx_executed : in natural;
constant command_queue_is_empty : in boolean;
constant scope : in string := C_VVC_NAME);
--==============================================================================
-- VVC Scoreboard helper method
--==============================================================================
function pad_i2c_sb(
constant data : in std_logic_vector
) return std_logic_vector;
end package vvc_methods_pkg;
package body vvc_methods_pkg is
--==============================================================================
-- Methods dedicated to this VVC
-- Notes:
-- - shared_vvc_cmd is initialised to C_VVC_CMD_DEFAULT, and also reset to this after every command
--==============================================================================
-- master transmit
procedure i2c_master_transmit(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant addr : in unsigned;
constant data : in t_byte_array;
constant msg : in string;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) & ")";
-- Normalize to the 10 bit addr width
variable v_normalized_addr : unsigned(C_VVC_CMD_ADDR_MAX_LENGTH - 1 downto 0) :=
normalize_and_check(addr, shared_vvc_cmd.addr, ALLOW_WIDER_NARROWER, "addr", "shared_vvc_cmd.addr", proc_call & " called with to wide address. " & add_msg_delimiter(msg));
variable v_msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, MASTER_TRANSMIT);
shared_vvc_cmd.addr := v_normalized_addr;
shared_vvc_cmd.data(0 to data'length - 1) := data;
shared_vvc_cmd.num_bytes := data'length;
shared_vvc_cmd.action_when_transfer_is_done := action_when_transfer_is_done;
shared_vvc_cmd.parent_msg_id_panel := parent_msg_id_panel;
if parent_msg_id_panel /= C_UNUSED_MSG_ID_PANEL then
v_msg_id_panel := parent_msg_id_panel;
end if;
send_command_to_vvc(VVCT, std.env.resolution_limit, scope, v_msg_id_panel);
end procedure;
procedure i2c_master_transmit(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant addr : in unsigned;
constant data : in std_logic_vector;
constant msg : in string;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) & ")";
variable v_byte : std_logic_vector(7 downto 0) := (others => '0');
-- Normalize to the 8 bit data width
variable v_normalized_data : std_logic_vector(7 downto 0) :=
normalize_and_check(data, v_byte, ALLOW_NARROWER, "data", "v_byte", msg);
variable v_byte_array : t_byte_array(0 to 0) := (0 => v_normalized_data);
begin
i2c_master_transmit(VVCT, vvc_instance_idx, addr, v_byte_array, msg, action_when_transfer_is_done, scope, parent_msg_id_panel);
end procedure;
-- slave transmit
procedure i2c_slave_transmit(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data : in t_byte_array;
constant msg : in string;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) & ")";
variable v_msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, SLAVE_TRANSMIT);
shared_vvc_cmd.data(0 to data'length - 1) := data;
shared_vvc_cmd.num_bytes := data'length;
shared_vvc_cmd.parent_msg_id_panel := parent_msg_id_panel;
if parent_msg_id_panel /= C_UNUSED_MSG_ID_PANEL then
v_msg_id_panel := parent_msg_id_panel;
end if;
send_command_to_vvc(VVCT, std.env.resolution_limit, scope, v_msg_id_panel);
end procedure;
procedure i2c_slave_transmit(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data : in std_logic_vector;
constant msg : in string;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
) is
variable v_byte : std_logic_vector(7 downto 0) := (others => '0');
-- Normalize to the 8 bit data width
variable v_normalized_data : std_logic_vector(7 downto 0) :=
normalize_and_check(data, v_byte, ALLOW_NARROWER, "data", "v_byte", msg);
variable v_byte_array : t_byte_array(0 to 0) := (0 => v_normalized_data);
begin
i2c_slave_transmit(VVCT, vvc_instance_idx, v_byte_array, msg, scope, parent_msg_id_panel);
end procedure;
-- master receive
procedure i2c_master_receive(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant addr : in unsigned;
constant num_bytes : in natural;
constant data_routing : in t_data_routing;
constant msg : in string;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) & ")";
-- Normalize to the 10 bit addr width
variable v_normalized_addr : unsigned(C_VVC_CMD_ADDR_MAX_LENGTH - 1 downto 0) :=
normalize_and_check(addr, shared_vvc_cmd.addr, ALLOW_NARROWER, "addr", "shared_vvc_cmd.addr", msg);
variable v_msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, MASTER_RECEIVE);
shared_vvc_cmd.addr := v_normalized_addr;
shared_vvc_cmd.num_bytes := num_bytes;
shared_vvc_cmd.data_routing := data_routing;
shared_vvc_cmd.action_when_transfer_is_done := action_when_transfer_is_done;
shared_vvc_cmd.parent_msg_id_panel := parent_msg_id_panel;
if parent_msg_id_panel /= C_UNUSED_MSG_ID_PANEL then
v_msg_id_panel := parent_msg_id_panel;
end if;
send_command_to_vvc(VVCT, std.env.resolution_limit, scope, v_msg_id_panel);
end procedure;
procedure i2c_master_receive(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant addr : in unsigned;
constant num_bytes : in natural;
constant msg : in string;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
) is
begin
i2c_master_receive(VVCT, vvc_instance_idx, addr, num_bytes, NA, msg, action_when_transfer_is_done, scope, parent_msg_id_panel);
end procedure;
-- slave receive
procedure i2c_slave_receive(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant num_bytes : in natural;
constant data_routing : in t_data_routing;
constant msg : in string;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) & ")";
variable v_msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, SLAVE_RECEIVE);
shared_vvc_cmd.num_bytes := num_bytes;
shared_vvc_cmd.data_routing := data_routing;
shared_vvc_cmd.parent_msg_id_panel := parent_msg_id_panel;
if parent_msg_id_panel /= C_UNUSED_MSG_ID_PANEL then
v_msg_id_panel := parent_msg_id_panel;
end if;
send_command_to_vvc(VVCT, std.env.resolution_limit, scope, v_msg_id_panel);
end procedure;
procedure i2c_slave_receive(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant num_bytes : in natural;
constant msg : in string;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
) is
begin
i2c_slave_receive(VVCT, vvc_instance_idx, num_bytes, NA, msg, scope, parent_msg_id_panel);
end procedure;
-- master check
procedure i2c_master_check(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant addr : in unsigned;
constant data : in t_byte_array;
constant msg : in string;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) & ")";
-- Normalize to the 10 bit addr width
variable v_normalized_addr : unsigned(C_VVC_CMD_ADDR_MAX_LENGTH - 1 downto 0) :=
normalize_and_check(addr, shared_vvc_cmd.addr, ALLOW_WIDER_NARROWER, "addr", "shared_vvc_cmd.addr", proc_call & " called with to wide address. " & add_msg_delimiter(msg));
variable v_msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, MASTER_CHECK);
shared_vvc_cmd.addr := v_normalized_addr;
shared_vvc_cmd.data(0 to data'length - 1) := data;
shared_vvc_cmd.num_bytes := data'length;
shared_vvc_cmd.alert_level := alert_level;
shared_vvc_cmd.action_when_transfer_is_done := action_when_transfer_is_done;
shared_vvc_cmd.parent_msg_id_panel := parent_msg_id_panel;
if parent_msg_id_panel /= C_UNUSED_MSG_ID_PANEL then
v_msg_id_panel := parent_msg_id_panel;
end if;
send_command_to_vvc(VVCT, std.env.resolution_limit, scope, v_msg_id_panel);
end procedure;
procedure i2c_master_check(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant addr : in unsigned;
constant data : in std_logic_vector;
constant msg : in string;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) & ")";
variable v_byte : std_logic_vector(7 downto 0) := (others => '0');
-- Normalize to the 8 bit data width
variable v_normalized_data : std_logic_vector(7 downto 0) :=
normalize_and_check(data, v_byte, ALLOW_NARROWER, "data", "v_byte", msg);
variable v_byte_array : t_byte_array(0 to 0) := (0 => v_normalized_data);
begin
i2c_master_check(VVCT, vvc_instance_idx, addr, v_byte_array, msg, action_when_transfer_is_done, alert_level, scope, parent_msg_id_panel);
end procedure;
procedure i2c_master_quick_command(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant addr : in unsigned;
constant msg : in string;
constant rw_bit : in std_logic := C_WRITE_BIT;
constant exp_ack : in boolean := true;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) & ")";
-- Normalize to the 10 bit addr width
variable v_normalized_addr : unsigned(C_VVC_CMD_ADDR_MAX_LENGTH - 1 downto 0) :=
normalize_and_check(addr, shared_vvc_cmd.addr, ALLOW_WIDER_NARROWER, "addr", "shared_vvc_cmd.addr", proc_call & " called with to wide address. " & add_msg_delimiter(msg));
variable v_msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, MASTER_QUICK_CMD);
shared_vvc_cmd.addr := v_normalized_addr;
shared_vvc_cmd.exp_ack := exp_ack;
shared_vvc_cmd.alert_level := alert_level;
shared_vvc_cmd.rw_bit := rw_bit;
shared_vvc_cmd.action_when_transfer_is_done := action_when_transfer_is_done;
shared_vvc_cmd.parent_msg_id_panel := parent_msg_id_panel;
if parent_msg_id_panel /= C_UNUSED_MSG_ID_PANEL then
v_msg_id_panel := parent_msg_id_panel;
end if;
send_command_to_vvc(VVCT, std.env.resolution_limit, scope, v_msg_id_panel);
end procedure;
-- slave check
procedure i2c_slave_check(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data : in t_byte_array;
constant msg : in string;
constant alert_level : in t_alert_level := error;
constant rw_bit : in std_logic := '0'; -- Default write bit
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) & ")";
variable v_msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, SLAVE_CHECK);
shared_vvc_cmd.data(0 to data'length - 1) := data;
shared_vvc_cmd.num_bytes := data'length;
shared_vvc_cmd.alert_level := alert_level;
shared_vvc_cmd.rw_bit := rw_bit;
shared_vvc_cmd.parent_msg_id_panel := parent_msg_id_panel;
if parent_msg_id_panel /= C_UNUSED_MSG_ID_PANEL then
v_msg_id_panel := parent_msg_id_panel;
end if;
send_command_to_vvc(VVCT, std.env.resolution_limit, scope, v_msg_id_panel);
end procedure;
procedure i2c_slave_check(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant data : in std_logic_vector;
constant msg : in string;
constant alert_level : in t_alert_level := error;
constant rw_bit : in std_logic := '0'; -- Default write bit
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) & ")";
variable v_byte : std_logic_vector(7 downto 0) := (others => '0');
-- Normalize to the 8 bit data width
variable v_normalized_data : std_logic_vector(7 downto 0) :=
normalize_and_check(data, v_byte, ALLOW_NARROWER, "data", "v_byte", msg);
variable v_byte_array : t_byte_array(0 to 0) := (0 => v_normalized_data);
begin
i2c_slave_check(VVCT, vvc_instance_idx, v_byte_array, msg, alert_level, rw_bit, scope, parent_msg_id_panel);
end procedure;
-- slave check
procedure i2c_slave_check(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant rw_bit : in std_logic;
constant msg : in string;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs
) is
constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name);
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) & ")";
variable v_dummy_byte_array : t_byte_array(0 to -1); -- Empty byte array to indicate that data is not checked
begin
i2c_slave_check(VVCT, vvc_instance_idx, v_dummy_byte_array, msg, alert_level, rw_bit, scope, parent_msg_id_panel);
end procedure;
--==============================================================================
-- Transaction info methods
--==============================================================================
procedure set_global_vvc_transaction_info(
signal vvc_transaction_info_trigger : inout std_logic;
variable vvc_transaction_info_group : inout t_transaction_group;
constant vvc_cmd : in t_vvc_cmd_record;
constant vvc_config : in t_vvc_config;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT) is
begin
case vvc_cmd.operation is
when MASTER_TRANSMIT | MASTER_RECEIVE | MASTER_CHECK |
SLAVE_TRANSMIT | SLAVE_RECEIVE | SLAVE_CHECK | MASTER_QUICK_CMD =>
vvc_transaction_info_group.bt.operation := vvc_cmd.operation;
vvc_transaction_info_group.bt.addr(vvc_cmd.addr'length-1 downto 0) := vvc_cmd.addr;
vvc_transaction_info_group.bt.data := vvc_cmd.data;
vvc_transaction_info_group.bt.num_bytes := vvc_cmd.num_bytes;
vvc_transaction_info_group.bt.action_when_transfer_is_done := vvc_cmd.action_when_transfer_is_done;
vvc_transaction_info_group.bt.exp_ack := vvc_cmd.exp_ack;
vvc_transaction_info_group.bt.rw_bit := vvc_cmd.rw_bit;
vvc_transaction_info_group.bt.vvc_meta.msg(1 to vvc_cmd.msg'length) := vvc_cmd.msg;
vvc_transaction_info_group.bt.vvc_meta.cmd_idx := vvc_cmd.cmd_idx;
vvc_transaction_info_group.bt.transaction_status := IN_PROGRESS;
gen_pulse(vvc_transaction_info_trigger, 0 ns, "pulsing global vvc transaction info trigger", scope, ID_NEVER);
when others =>
alert(TB_ERROR, "VVC operation not recognized");
end case;
wait for 0 ns;
end procedure set_global_vvc_transaction_info;
procedure reset_vvc_transaction_info(
variable vvc_transaction_info_group : inout t_transaction_group;
constant vvc_cmd : in t_vvc_cmd_record) is
begin
case vvc_cmd.operation is
when MASTER_TRANSMIT | MASTER_RECEIVE | MASTER_CHECK |
SLAVE_TRANSMIT | SLAVE_RECEIVE | SLAVE_CHECK | MASTER_QUICK_CMD =>
vvc_transaction_info_group.bt := C_BASE_TRANSACTION_SET_DEFAULT;
when others =>
null;
end case;
wait for 0 ns;
end procedure reset_vvc_transaction_info;
--==============================================================================
-- VVC Activity
--==============================================================================
procedure update_vvc_activity_register( signal global_trigger_vvc_activity_register : inout std_logic;
variable vvc_status : inout t_vvc_status;
constant activity : in t_activity;
constant entry_num_in_vvc_activity_register : in integer;
constant last_cmd_idx_executed : in natural;
constant command_queue_is_empty : in boolean;
constant scope : in string := C_VVC_NAME) is
variable v_activity : t_activity := activity;
begin
-- Update vvc_status after a command has finished (during same delta cycle the activity register is updated)
if activity = INACTIVE then
vvc_status.previous_cmd_idx := last_cmd_idx_executed;
vvc_status.current_cmd_idx := 0;
end if;
if v_activity = INACTIVE and not(command_queue_is_empty) then
v_activity := ACTIVE;
end if;
shared_vvc_activity_register.priv_report_vvc_activity(vvc_idx => entry_num_in_vvc_activity_register,
activity => v_activity,
last_cmd_idx_executed => last_cmd_idx_executed);
if global_trigger_vvc_activity_register /= 'L' then
wait until global_trigger_vvc_activity_register = 'L';
end if;
gen_pulse(global_trigger_vvc_activity_register, 0 ns, "pulsing global trigger for vvc activity register", scope, ID_NEVER);
end procedure;
--==============================================================================
-- VVC Scoreboard helper method
--==============================================================================
function pad_i2c_sb(
constant data : in std_logic_vector
) return std_logic_vector is
begin
return pad_sb_slv(data, C_VVC_CMD_DATA_MAX_LENGTH);
end function pad_i2c_sb;
end package body vvc_methods_pkg;
|
mit
|
UVVM/UVVM_All
|
bitvis_vip_sbi/src/sbi_vvc.vhd
|
1
|
26930
|
--================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
----------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
--
-- NOTE: In addition to being a VVC for the SBI, this module is also used as a template
-- and a well commented example of the VVC structure and functionality
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
library bitvis_vip_scoreboard;
use bitvis_vip_scoreboard.generic_sb_support_pkg.C_SB_CONFIG_DEFAULT;
use work.sbi_bfm_pkg.all;
use work.vvc_methods_pkg.all;
use work.vvc_cmd_pkg.all;
use work.td_target_support_pkg.all;
use work.td_vvc_entity_support_pkg.all;
use work.td_cmd_queue_pkg.all;
use work.td_result_queue_pkg.all;
use work.transaction_pkg.all;
--=================================================================================================
entity sbi_vvc is
generic (
GC_ADDR_WIDTH : integer range 1 to C_VVC_CMD_ADDR_MAX_LENGTH := 8; -- SBI address bus
GC_DATA_WIDTH : integer range 1 to C_VVC_CMD_DATA_MAX_LENGTH := 32; -- SBI data bus
GC_INSTANCE_IDX : natural := 1; -- Instance index for this SBI_VVCT instance
GC_SBI_CONFIG : t_sbi_bfm_config := C_SBI_BFM_CONFIG_DEFAULT; -- Behavior specification for BFM
GC_CMD_QUEUE_COUNT_MAX : natural := 1000;
GC_CMD_QUEUE_COUNT_THRESHOLD : natural := 950;
GC_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY : t_alert_level := warning;
GC_RESULT_QUEUE_COUNT_MAX : natural := 1000;
GC_RESULT_QUEUE_COUNT_THRESHOLD : natural := 950;
GC_RESULT_QUEUE_COUNT_THRESHOLD_SEVERITY : t_alert_level := warning
);
port (
clk : in std_logic;
sbi_vvc_master_if : inout t_sbi_if(addr(GC_ADDR_WIDTH-1 downto 0),
wdata(GC_DATA_WIDTH-1 downto 0),
rdata(GC_DATA_WIDTH-1 downto 0)) := init_sbi_if_signals(GC_ADDR_WIDTH, GC_DATA_WIDTH)
);
begin
-- Check the interface widths to assure that the interface was correctly set up
assert (sbi_vvc_master_if.addr'length = GC_ADDR_WIDTH) report "sbi_vvc_master_if.addr'length =/ GC_ADDR_WIDTH" severity failure;
assert (sbi_vvc_master_if.wdata'length = GC_DATA_WIDTH) report "sbi_vvc_master_if.wdata'length =/ GC_DATA_WIDTH" severity failure;
assert (sbi_vvc_master_if.rdata'length = GC_DATA_WIDTH) report "sbi_vvc_master_if.rdata'length =/ GC_DATA_WIDTH" severity failure;
end entity sbi_vvc;
--=================================================================================================
--=================================================================================================
architecture behave of sbi_vvc is
constant C_SCOPE : string := C_VVC_NAME & "," & to_string(GC_INSTANCE_IDX);
constant C_VVC_LABELS : t_vvc_labels := assign_vvc_labels(C_SCOPE, C_VVC_NAME, GC_INSTANCE_IDX, NA);
signal executor_is_busy : boolean := false;
signal queue_is_increasing : boolean := false;
signal last_cmd_idx_executed : natural := 0;
signal terminate_current_cmd : t_flag_record;
-- Instantiation of the element dedicated Queue
shared variable command_queue : work.td_cmd_queue_pkg.t_generic_queue;
shared variable result_queue : work.td_result_queue_pkg.t_generic_queue;
alias vvc_config : t_vvc_config is shared_sbi_vvc_config(GC_INSTANCE_IDX);
alias vvc_status : t_vvc_status is shared_sbi_vvc_status(GC_INSTANCE_IDX);
alias transaction_info : t_transaction_info is shared_sbi_transaction_info(GC_INSTANCE_IDX);
-- Transaction info
alias vvc_transaction_info_trigger : std_logic is global_sbi_vvc_transaction_trigger(GC_INSTANCE_IDX);
alias vvc_transaction_info : t_transaction_group is shared_sbi_vvc_transaction_info(GC_INSTANCE_IDX);
-- VVC Activity
signal entry_num_in_vvc_activity_register : integer;
--UVVM: temporary fix for HVVC, remove function below in v3.0
function get_msg_id_panel(
constant command : in t_vvc_cmd_record;
constant vvc_config : in t_vvc_config
) return t_msg_id_panel is
begin
-- If the parent_msg_id_panel is set then use it,
-- otherwise use the VVCs msg_id_panel from its config.
if command.msg(1 to 5) = "HVVC:" then
return vvc_config.parent_msg_id_panel;
else
return vvc_config.msg_id_panel;
end if;
end function;
begin
--===============================================================================================
-- Constructor
-- - Set up the defaults and show constructor if enabled
--===============================================================================================
vvc_constructor(C_SCOPE, GC_INSTANCE_IDX, vvc_config, command_queue, result_queue, GC_SBI_CONFIG,
GC_CMD_QUEUE_COUNT_MAX, GC_CMD_QUEUE_COUNT_THRESHOLD, GC_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY,
GC_RESULT_QUEUE_COUNT_MAX, GC_RESULT_QUEUE_COUNT_THRESHOLD, GC_RESULT_QUEUE_COUNT_THRESHOLD_SEVERITY);
--===============================================================================================
--===============================================================================================
-- Command interpreter
-- - Interpret, decode and acknowledge commands from the central sequencer
--===============================================================================================
cmd_interpreter : process
variable v_cmd_has_been_acked : boolean; -- Indicates if acknowledge_cmd() has been called for the current shared_vvc_cmd
variable v_local_vvc_cmd : t_vvc_cmd_record := C_VVC_CMD_DEFAULT;
variable v_msg_id_panel : t_msg_id_panel;
variable v_temp_msg_id_panel : t_msg_id_panel; --UVVM: temporary fix for HVVC, remove in v3.0
begin
-- 0. Initialize the process prior to first command
work.td_vvc_entity_support_pkg.initialize_interpreter(terminate_current_cmd, global_awaiting_completion);
-- initialise shared_vvc_last_received_cmd_idx for channel and instance
shared_vvc_last_received_cmd_idx(NA, GC_INSTANCE_IDX) := 0;
-- Register VVC in vvc activity register
entry_num_in_vvc_activity_register <= shared_vvc_activity_register.priv_register_vvc(name => C_VVC_NAME,
instance => GC_INSTANCE_IDX);
-- Set initial value of v_msg_id_panel to msg_id_panel in config
v_msg_id_panel := vvc_config.msg_id_panel;
-- Then for every single command from the sequencer
loop -- basically as long as new commands are received
-- 1. wait until command targeted at this VVC. Must match VVC name, instance and channel (if applicable)
-- releases global semaphore
-------------------------------------------------------------------------
work.td_vvc_entity_support_pkg.await_cmd_from_sequencer(C_VVC_LABELS, vvc_config, THIS_VVCT, VVC_BROADCAST, global_vvc_busy, global_vvc_ack, v_local_vvc_cmd);
v_cmd_has_been_acked := false; -- Clear flag
-- update shared_vvc_last_received_cmd_idx with received command index
shared_vvc_last_received_cmd_idx(NA, GC_INSTANCE_IDX) := v_local_vvc_cmd.cmd_idx;
-- Select between a provided msg_id_panel via the vvc_cmd_record from a VVC with a higher hierarchy or the
-- msg_id_panel in this VVC's config. This is to correctly handle the logging when using Hierarchical-VVCs.
v_msg_id_panel := get_msg_id_panel(v_local_vvc_cmd, vvc_config);
-- 2a. Put command on the queue if intended for the executor
-------------------------------------------------------------------------
if v_local_vvc_cmd.command_type = QUEUED then
work.td_vvc_entity_support_pkg.put_command_on_queue(v_local_vvc_cmd, command_queue, vvc_status, queue_is_increasing);
-- 2b. Otherwise command is intended for immediate response
-------------------------------------------------------------------------
elsif v_local_vvc_cmd.command_type = IMMEDIATE then
--UVVM: temporary fix for HVVC, remove two lines below in v3.0
if v_local_vvc_cmd.operation /= DISABLE_LOG_MSG and v_local_vvc_cmd.operation /= ENABLE_LOG_MSG then
v_temp_msg_id_panel := vvc_config.msg_id_panel;
vvc_config.msg_id_panel := v_msg_id_panel;
end if;
case v_local_vvc_cmd.operation is
when AWAIT_COMPLETION =>
work.td_vvc_entity_support_pkg.interpreter_await_completion(v_local_vvc_cmd, command_queue, vvc_config, executor_is_busy, C_VVC_LABELS, last_cmd_idx_executed);
when AWAIT_ANY_COMPLETION =>
if not v_local_vvc_cmd.gen_boolean then
-- Called with lastness = NOT_LAST: Acknowledge immediately to let the sequencer continue
work.td_target_support_pkg.acknowledge_cmd(global_vvc_ack,v_local_vvc_cmd.cmd_idx);
v_cmd_has_been_acked := true;
end if;
work.td_vvc_entity_support_pkg.interpreter_await_any_completion(v_local_vvc_cmd, command_queue, vvc_config, executor_is_busy, C_VVC_LABELS, last_cmd_idx_executed, global_awaiting_completion);
when DISABLE_LOG_MSG =>
uvvm_util.methods_pkg.disable_log_msg(v_local_vvc_cmd.msg_id, vvc_config.msg_id_panel, to_string(v_local_vvc_cmd.msg) & format_command_idx(v_local_vvc_cmd), C_SCOPE, v_local_vvc_cmd.quietness);
when ENABLE_LOG_MSG =>
uvvm_util.methods_pkg.enable_log_msg(v_local_vvc_cmd.msg_id, vvc_config.msg_id_panel, to_string(v_local_vvc_cmd.msg) & format_command_idx(v_local_vvc_cmd), C_SCOPE, v_local_vvc_cmd.quietness);
when FLUSH_COMMAND_QUEUE =>
work.td_vvc_entity_support_pkg.interpreter_flush_command_queue(v_local_vvc_cmd, command_queue, vvc_config, vvc_status, C_VVC_LABELS);
when TERMINATE_CURRENT_COMMAND =>
work.td_vvc_entity_support_pkg.interpreter_terminate_current_command(v_local_vvc_cmd, vvc_config, C_VVC_LABELS, terminate_current_cmd);
when FETCH_RESULT =>
work.td_vvc_entity_support_pkg.interpreter_fetch_result(result_queue, v_local_vvc_cmd, vvc_config, C_VVC_LABELS, last_cmd_idx_executed, shared_vvc_response);
when others =>
tb_error("Unsupported command received for IMMEDIATE execution: '" & to_string(v_local_vvc_cmd.operation) & "'", C_SCOPE);
end case;
--UVVM: temporary fix for HVVC, remove line below in v3.0
if v_local_vvc_cmd.operation /= DISABLE_LOG_MSG and v_local_vvc_cmd.operation /= ENABLE_LOG_MSG then
vvc_config.msg_id_panel := v_temp_msg_id_panel;
end if;
else
tb_error("command_type is not IMMEDIATE or QUEUED", C_SCOPE);
end if;
-- 3. Acknowledge command after runing or queuing the command
-------------------------------------------------------------------------
if not v_cmd_has_been_acked then
work.td_target_support_pkg.acknowledge_cmd(global_vvc_ack,v_local_vvc_cmd.cmd_idx);
end if;
end loop;
end process;
--===============================================================================================
--===============================================================================================
-- Command executor
-- - Fetch and execute the commands
--===============================================================================================
cmd_executor : process
variable v_cmd : t_vvc_cmd_record;
variable v_read_data : t_vvc_result; -- See vvc_cmd_pkg
variable v_timestamp_start_of_current_bfm_access : time := 0 ns;
variable v_timestamp_start_of_last_bfm_access : time := 0 ns;
variable v_timestamp_end_of_last_bfm_access : time := 0 ns;
variable v_command_is_bfm_access : boolean := false;
variable v_prev_command_was_bfm_access : boolean := false;
variable v_normalised_addr : unsigned(GC_ADDR_WIDTH-1 downto 0) := (others => '0');
variable v_normalised_data : std_logic_vector(GC_DATA_WIDTH-1 downto 0) := (others => '0');
variable v_msg_id_panel : t_msg_id_panel;
begin
-- 0. Initialize the process prior to first command
-------------------------------------------------------------------------
work.td_vvc_entity_support_pkg.initialize_executor(terminate_current_cmd);
-- Set initial value of v_msg_id_panel to msg_id_panel in config
v_msg_id_panel := vvc_config.msg_id_panel;
-- Setup SBI scoreboard
SBI_VVC_SB.set_scope("SBI_VVC_SB");
SBI_VVC_SB.enable(GC_INSTANCE_IDX, "SBI VVC SB Enabled");
SBI_VVC_SB.config(GC_INSTANCE_IDX, C_SB_CONFIG_DEFAULT);
SBI_VVC_SB.enable_log_msg(GC_INSTANCE_IDX, ID_DATA);
loop
-- update vvc activity
update_vvc_activity_register(global_trigger_vvc_activity_register, vvc_status, INACTIVE, entry_num_in_vvc_activity_register, last_cmd_idx_executed, command_queue.is_empty(VOID), C_SCOPE);
-- 1. Set defaults, fetch command and log
-------------------------------------------------------------------------
work.td_vvc_entity_support_pkg.fetch_command_and_prepare_executor(v_cmd, command_queue, vvc_config, vvc_status, queue_is_increasing, executor_is_busy, C_VVC_LABELS);
-- update vvc activity
update_vvc_activity_register(global_trigger_vvc_activity_register, vvc_status, ACTIVE, entry_num_in_vvc_activity_register, last_cmd_idx_executed, command_queue.is_empty(VOID), C_SCOPE);
-- Set the transaction info for waveview
transaction_info := C_TRANSACTION_INFO_DEFAULT;
transaction_info.operation := v_cmd.operation;
transaction_info.msg := pad_string(to_string(v_cmd.msg), ' ', transaction_info.msg'length);
-- Select between a provided msg_id_panel via the vvc_cmd_record from a VVC with a higher hierarchy or the
-- msg_id_panel in this VVC's config. This is to correctly handle the logging when using Hierarchical-VVCs.
v_msg_id_panel := get_msg_id_panel(v_cmd, vvc_config);
-- Check if command is a BFM access
v_prev_command_was_bfm_access := v_command_is_bfm_access; -- save for inter_bfm_delay
if v_cmd.operation = WRITE or v_cmd.operation = READ or v_cmd.operation = CHECK or v_cmd.operation = POLL_UNTIL then
v_command_is_bfm_access := true;
else
v_command_is_bfm_access := false;
end if;
-- Insert delay if needed
work.td_vvc_entity_support_pkg.insert_inter_bfm_delay_if_requested(vvc_config => vvc_config,
command_is_bfm_access => v_prev_command_was_bfm_access,
timestamp_start_of_last_bfm_access => v_timestamp_start_of_last_bfm_access,
timestamp_end_of_last_bfm_access => v_timestamp_end_of_last_bfm_access,
scope => C_SCOPE,
msg_id_panel => v_msg_id_panel);
if v_command_is_bfm_access then
v_timestamp_start_of_current_bfm_access := now;
end if;
-- 2. Execute the fetched command
-------------------------------------------------------------------------
case v_cmd.operation is -- Only operations in the dedicated record are relevant
-- VVC dedicated operations
--===================================
when WRITE =>
-- Loop the number of words to transmit
for idx in 1 to v_cmd.num_words loop
-- Randomise data if applicable
case v_cmd.randomisation is
when RANDOM =>
v_cmd.data(GC_DATA_WIDTH-1 downto 0) := std_logic_vector(random(GC_DATA_WIDTH));
when RANDOM_FAVOUR_EDGES =>
null; -- Not implemented yet
when others => -- NA
null;
end case;
-- Set VVC Transaction Info
set_global_vvc_transaction_info(vvc_transaction_info_trigger, vvc_transaction_info, v_cmd, vvc_config);
-- Normalise address and data
v_normalised_addr := normalize_and_check(v_cmd.addr, v_normalised_addr, ALLOW_WIDER_NARROWER, "addr", "shared_vvc_cmd.addr", "sbi_write() called with to wide addrress. " & v_cmd.msg);
v_normalised_data := normalize_and_check(v_cmd.data, v_normalised_data, ALLOW_WIDER_NARROWER, "data", "shared_vvc_cmd.data", "sbi_write() called with to wide data. " & v_cmd.msg);
transaction_info.data(GC_DATA_WIDTH - 1 downto 0) := v_normalised_data;
transaction_info.addr(GC_ADDR_WIDTH - 1 downto 0) := v_normalised_addr;
-- Call the corresponding procedure in the BFM package.
sbi_write(addr_value => v_normalised_addr,
data_value => v_normalised_data,
msg => format_msg(v_cmd),
clk => clk,
sbi_if => sbi_vvc_master_if,
scope => C_SCOPE,
msg_id_panel => v_msg_id_panel,
config => vvc_config.bfm_config);
-- Set VVC Transaction Info back to default values
reset_vvc_transaction_info(vvc_transaction_info, v_cmd);
-- exit loop if terminate_current_cmd is requested
if terminate_current_cmd.is_active = '1' then
exit;
end if;
end loop;
when READ =>
-- Set VVC Transaction Info
set_global_vvc_transaction_info(vvc_transaction_info_trigger, vvc_transaction_info, v_cmd, vvc_config);
-- Normalise address and data
v_normalised_addr := normalize_and_check(v_cmd.addr, v_normalised_addr, ALLOW_WIDER_NARROWER, "addr", "shared_vvc_cmd.addr", "sbi_read() called with to wide addrress. " & v_cmd.msg);
v_read_data := (others => '-');
transaction_info.addr(GC_ADDR_WIDTH - 1 downto 0) := v_normalised_addr;
-- Call the corresponding procedure in the BFM package.
sbi_read(addr_value => v_normalised_addr,
data_value => v_read_data(GC_DATA_WIDTH - 1 downto 0),
msg => format_msg(v_cmd),
clk => clk,
sbi_if => sbi_vvc_master_if,
scope => C_SCOPE,
msg_id_panel => v_msg_id_panel,
config => vvc_config.bfm_config);
-- Request SB check result
if v_cmd.data_routing = TO_SB then
-- call SB check_received
SBI_VVC_SB.check_received(GC_INSTANCE_IDX, pad_sbi_sb(v_read_data(GC_DATA_WIDTH-1 downto 0)));
else
work.td_vvc_entity_support_pkg.store_result(result_queue => result_queue,
cmd_idx => v_cmd.cmd_idx,
result => v_read_data);
end if;
when CHECK =>
-- Set VVC Transaction Info
set_global_vvc_transaction_info(vvc_transaction_info_trigger, vvc_transaction_info, v_cmd, vvc_config);
-- Normalise address and data
v_normalised_addr := normalize_and_check(v_cmd.addr, v_normalised_addr, ALLOW_WIDER_NARROWER, "addr", "shared_vvc_cmd.addr", "sbi_check() called with to wide addrress. " & v_cmd.msg);
v_normalised_data := normalize_and_check(v_cmd.data, v_normalised_data, ALLOW_WIDER_NARROWER, "data", "shared_vvc_cmd.data", "sbi_check() called with to wide data. " & v_cmd.msg);
transaction_info.data(GC_DATA_WIDTH - 1 downto 0) := v_normalised_data;
transaction_info.addr(GC_ADDR_WIDTH - 1 downto 0) := v_normalised_addr;
-- Call the corresponding procedure in the BFM package.
sbi_check(addr_value => v_normalised_addr,
data_exp => v_normalised_data,
msg => format_msg(v_cmd),
clk => clk,
sbi_if => sbi_vvc_master_if,
alert_level => v_cmd.alert_level,
scope => C_SCOPE,
msg_id_panel => v_msg_id_panel,
config => vvc_config.bfm_config);
when POLL_UNTIL =>
-- Set VVC Transaction Info
set_global_vvc_transaction_info(vvc_transaction_info_trigger, vvc_transaction_info, v_cmd, vvc_config);
-- Normalise address and data
v_normalised_addr := normalize_and_check(v_cmd.addr, v_normalised_addr, ALLOW_WIDER_NARROWER, "addr", "shared_vvc_cmd.addr", "sbi_poll_until() called with to wide addrress. " & v_cmd.msg);
v_normalised_data := normalize_and_check(v_cmd.data, v_normalised_data, ALLOW_WIDER_NARROWER, "data", "shared_vvc_cmd.data", "sbi_poll_until() called with to wide data. " & v_cmd.msg);
transaction_info.data(GC_DATA_WIDTH - 1 downto 0) := v_normalised_data;
transaction_info.addr(GC_ADDR_WIDTH - 1 downto 0) := v_normalised_addr;
-- Call the corresponding procedure in the BFM package.
sbi_poll_until(addr_value => v_normalised_addr,
data_exp => v_normalised_data,
max_polls => v_cmd.max_polls,
timeout => v_cmd.timeout,
msg => format_msg(v_cmd),
clk => clk,
sbi_if => sbi_vvc_master_if,
terminate_loop => terminate_current_cmd.is_active,
alert_level => v_cmd.alert_level,
scope => C_SCOPE,
msg_id_panel => v_msg_id_panel,
config => vvc_config.bfm_config);
-- UVVM common operations
--===================================
when INSERT_DELAY =>
log(ID_INSERTED_DELAY, "Running: " & to_string(v_cmd.proc_call) & " " & format_command_idx(v_cmd), C_SCOPE, v_msg_id_panel);
if v_cmd.gen_integer_array(0) = -1 then
-- Delay specified using time
wait until terminate_current_cmd.is_active = '1' for v_cmd.delay;
else
-- Delay specified using integer
check_value(vvc_config.bfm_config.clock_period > -1 ns, TB_ERROR, "Check that clock_period is configured when using insert_delay().",
C_SCOPE, ID_NEVER, v_msg_id_panel);
wait until terminate_current_cmd.is_active = '1' for v_cmd.gen_integer_array(0) * vvc_config.bfm_config.clock_period;
end if;
when others =>
tb_error("Unsupported local command received for execution: '" & to_string(v_cmd.operation) & "'", C_SCOPE);
end case;
if v_command_is_bfm_access then
v_timestamp_end_of_last_bfm_access := now;
v_timestamp_start_of_last_bfm_access := v_timestamp_start_of_current_bfm_access;
if ((vvc_config.inter_bfm_delay.delay_type = TIME_START2START) and
((now - v_timestamp_start_of_current_bfm_access) > vvc_config.inter_bfm_delay.delay_in_time)) then
alert(vvc_config.inter_bfm_delay.inter_bfm_delay_violation_severity, "BFM access exceeded specified start-to-start inter-bfm delay, " &
to_string(vvc_config.inter_bfm_delay.delay_in_time) & ".", C_SCOPE);
end if;
end if;
-- Reset terminate flag if any occurred
if (terminate_current_cmd.is_active = '1') then
log(ID_CMD_EXECUTOR, "Termination request received", C_SCOPE, v_msg_id_panel);
uvvm_vvc_framework.ti_vvc_framework_support_pkg.reset_flag(terminate_current_cmd);
end if;
last_cmd_idx_executed <= v_cmd.cmd_idx;
-- Reset the transaction info for waveview
transaction_info := C_TRANSACTION_INFO_DEFAULT;
-- Set VVC Transaction Info back to default values
reset_vvc_transaction_info(vvc_transaction_info, v_cmd);
end loop;
end process;
--===============================================================================================
--===============================================================================================
-- Command termination handler
-- - Handles the termination request record (sets and resets terminate flag on request)
--===============================================================================================
cmd_terminator : uvvm_vvc_framework.ti_vvc_framework_support_pkg.flag_handler(terminate_current_cmd); -- flag: is_active, set, reset
--===============================================================================================
end behave;
|
mit
|
UVVM/UVVM_All
|
bitvis_vip_uart/src/vvc_context.vhd
|
1
|
1686
|
--================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
----------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
context vvc_context is
library bitvis_vip_uart;
use bitvis_vip_uart.transaction_pkg.all;
use bitvis_vip_uart.vvc_methods_pkg.all;
use bitvis_vip_uart.td_vvc_framework_common_methods_pkg.all;
use bitvis_vip_uart.uart_bfm_pkg.t_uart_bfm_config;
use bitvis_vip_uart.uart_bfm_pkg.C_UART_BFM_CONFIG_DEFAULT;
end context;
|
mit
|
UVVM/UVVM_All
|
uvvm_util/src/global_signals_and_shared_variables_pkg.vhd
|
1
|
3133
|
--================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
----------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.types_pkg.all;
use work.adaptations_pkg.all;
use work.protected_types_pkg.all;
package global_signals_and_shared_variables_pkg is
-- Shared variables
shared variable shared_initialised_util : boolean := false;
shared variable shared_msg_id_panel : t_msg_id_panel := C_MSG_ID_PANEL_DEFAULT;
shared variable shared_log_file_name_is_set : boolean := false;
shared variable shared_alert_file_name_is_set : boolean := false;
shared variable shared_warned_time_stamp_trunc : boolean := false;
shared variable shared_alert_attention : t_alert_attention:= C_DEFAULT_ALERT_ATTENTION;
shared variable shared_stop_limit : t_alert_counters := C_DEFAULT_STOP_LIMIT;
shared variable shared_log_hdr_for_waveview : string(1 to C_LOG_HDR_FOR_WAVEVIEW_WIDTH);
shared variable shared_current_log_hdr : t_current_log_hdr;
shared variable shared_seed1 : positive;
shared variable shared_seed2 : positive;
shared variable shared_flag_array : t_sync_flag_record_array(1 to C_NUM_SYNC_FLAGS) := (others => C_SYNC_FLAG_DEFAULT);
shared variable protected_semaphore : t_protected_semaphore;
shared variable protected_broadcast_semaphore : t_protected_semaphore;
shared variable protected_response_semaphore : t_protected_semaphore;
shared variable shared_uvvm_status : t_uvvm_status := C_UVVM_STATUS_DEFAULT;
shared variable protected_covergroup_status : t_protected_covergroup_status;
-- Global signals
signal global_trigger : std_logic := 'L';
signal global_barrier : std_logic := 'X';
end package global_signals_and_shared_variables_pkg;
|
mit
|
UVVM/UVVM_All
|
bitvis_vip_axi/src/axi_channel_handler_pkg.vhd
|
1
|
32993
|
--================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
----------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
-- Description : Package for accessing each AXI channel separately. Used by the VVC
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library work;
use work.axi_bfm_pkg.all;
use work.axi_read_data_queue_pkg.all;
use work.vvc_cmd_pkg.all;
--=================================================================================================
package axi_channel_handler_pkg is
--===============================================================================================
-- Types and constants
--===============================================================================================
constant C_SCOPE : string := "AXI_CHANNEL_HANDLER";
--===============================================================================================
-- Procedures
--===============================================================================================
------------------------------------------
-- write_address_channel_write
------------------------------------------
-- This procedure writes adress on the write address channel
-- - When the write is completed, a log message is issued with ID_CHANNEL_BFM
procedure write_address_channel_write (
constant awid_value : in std_logic_vector;
constant awaddr_value : in unsigned;
constant awlen_value : in unsigned(7 downto 0);
constant awsize_value : in integer range 1 to 128;
constant awburst_value : in t_axburst;
constant awlock_value : in t_axlock;
constant awcache_value : in std_logic_vector(3 downto 0);
constant awprot_value : in t_axprot;
constant awqos_value : in std_logic_vector(3 downto 0);
constant awregion_value : in std_logic_vector(3 downto 0);
constant awuser_value : in std_logic_vector;
constant msg : in string;
signal clk : in std_logic;
signal awid : inout std_logic_vector;
signal awaddr : inout std_logic_vector;
signal awlen : inout std_logic_vector(7 downto 0);
signal awsize : inout std_logic_vector(2 downto 0);
signal awburst : inout std_logic_vector(1 downto 0);
signal awlock : inout std_logic;
signal awcache : inout std_logic_vector(3 downto 0);
signal awprot : inout std_logic_vector(2 downto 0);
signal awqos : inout std_logic_vector(3 downto 0);
signal awregion : inout std_logic_vector(3 downto 0);
signal awuser : inout std_logic_vector;
signal awvalid : inout std_logic;
signal awready : in std_logic;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axi_bfm_config := C_AXI_BFM_CONFIG_DEFAULT
);
------------------------------------------
-- write_data_channel_write
------------------------------------------
-- This procedure writes data on the write data channel
-- - When the write is completed, a log message is issued with ID_CHANNEL_BFM
procedure write_data_channel_write (
constant wdata_value : in t_slv_array;
constant wstrb_value : in t_slv_array;
constant wuser_value : in t_slv_array;
constant awlen_value : in unsigned(7 downto 0);
constant msg : in string;
signal clk : in std_logic;
signal wdata : inout std_logic_vector;
signal wstrb : inout std_logic_vector;
signal wlast : inout std_logic;
signal wuser : inout std_logic_vector;
signal wvalid : inout std_logic;
signal wready : in std_logic;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axi_bfm_config := C_AXI_BFM_CONFIG_DEFAULT
);
------------------------------------------
-- write_response_channel_receive
------------------------------------------
-- This procedure receives the write response on the write response channel
-- and returns the response data
-- - When completed, a log message with ID id_for_bfm is issued.
procedure write_response_channel_receive (
variable bid_value : out std_logic_vector;
variable bresp_value : out t_xresp;
variable buser_value : out std_logic_vector;
constant msg : in string;
signal clk : in std_logic;
signal bid : in std_logic_vector;
signal bresp : in std_logic_vector(1 downto 0);
signal buser : in std_logic_vector;
signal bvalid : in std_logic;
signal bready : inout std_logic;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axi_bfm_config := C_AXI_BFM_CONFIG_DEFAULT;
constant ext_proc_call : in string := "" -- External proc_call. Overwrite if called from another BFM procedure
);
------------------------------------------
-- read_address_channel_write
------------------------------------------
-- This procedure writes adress on the read address channel
-- - When the write is completed, a log message is issued with ID_CHANNEL_BFM
procedure read_address_channel_write (
constant arid_value : in std_logic_vector;
constant araddr_value : in unsigned;
constant arlen_value : in unsigned(7 downto 0);
constant arsize_value : in integer range 1 to 128;
constant arburst_value : in t_axburst;
constant arlock_value : in t_axlock;
constant arcache_value : in std_logic_vector(3 downto 0);
constant arprot_value : in t_axprot;
constant arqos_value : in std_logic_vector(3 downto 0);
constant arregion_value : in std_logic_vector(3 downto 0);
constant aruser_value : in std_logic_vector;
constant msg : in string;
signal clk : in std_logic;
signal arid : inout std_logic_vector;
signal araddr : inout std_logic_vector;
signal arlen : inout std_logic_vector(7 downto 0);
signal arsize : inout std_logic_vector(2 downto 0);
signal arburst : inout std_logic_vector(1 downto 0);
signal arlock : inout std_logic;
signal arcache : inout std_logic_vector(3 downto 0);
signal arprot : inout std_logic_vector(2 downto 0);
signal arqos : inout std_logic_vector(3 downto 0);
signal arregion : inout std_logic_vector(3 downto 0);
signal aruser : inout std_logic_vector;
signal arvalid : inout std_logic;
signal arready : in std_logic;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axi_bfm_config := C_AXI_BFM_CONFIG_DEFAULT
);
------------------------------------------
-- read_data_channel_receive
------------------------------------------
-- This procedure receives read data on the read data channel,
-- and returns the read data
-- - When completed, a log message with ID id_for_bfm is issued.
procedure read_data_channel_receive (
variable read_result : out t_vvc_result;
variable read_data_queue : inout t_axi_read_data_queue;
constant msg : in string;
signal clk : in std_logic;
signal rid : in std_logic_vector;
signal rdata : in std_logic_vector;
signal rresp : in std_logic_vector(1 downto 0);
signal rlast : in std_logic;
signal ruser : in std_logic_vector;
signal rvalid : in std_logic;
signal rready : inout std_logic;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axi_bfm_config := C_AXI_BFM_CONFIG_DEFAULT;
constant ext_proc_call : in string := "" -- External proc_call. Overwrite if called from another BFM procedure
);
end package axi_channel_handler_pkg;
package body axi_channel_handler_pkg is
----------------------------------------------------
-- BFM procedures
----------------------------------------------------
procedure write_address_channel_write (
constant awid_value : in std_logic_vector;
constant awaddr_value : in unsigned;
constant awlen_value : in unsigned(7 downto 0);
constant awsize_value : in integer range 1 to 128;
constant awburst_value : in t_axburst;
constant awlock_value : in t_axlock;
constant awcache_value : in std_logic_vector(3 downto 0);
constant awprot_value : in t_axprot;
constant awqos_value : in std_logic_vector(3 downto 0);
constant awregion_value : in std_logic_vector(3 downto 0);
constant awuser_value : in std_logic_vector;
constant msg : in string;
signal clk : in std_logic;
signal awid : inout std_logic_vector;
signal awaddr : inout std_logic_vector;
signal awlen : inout std_logic_vector(7 downto 0);
signal awsize : inout std_logic_vector(2 downto 0);
signal awburst : inout std_logic_vector(1 downto 0);
signal awlock : inout std_logic;
signal awcache : inout std_logic_vector(3 downto 0);
signal awprot : inout std_logic_vector(2 downto 0);
signal awqos : inout std_logic_vector(3 downto 0);
signal awregion : inout std_logic_vector(3 downto 0);
signal awuser : inout std_logic_vector;
signal awvalid : inout std_logic;
signal awready : in std_logic;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axi_bfm_config := C_AXI_BFM_CONFIG_DEFAULT
) is
constant proc_call : string := "write_address_channel_write(" & to_string(awaddr_value, HEX, AS_IS, INCL_RADIX) & ")";
variable v_await_awready : boolean := true;
-- Normalizing unconstrained inputs
variable v_normalized_awid : std_logic_vector(awid'length-1 downto 0);
variable v_normalized_awaddr : std_logic_vector(awaddr'length-1 downto 0) :=
normalize_and_check(std_logic_vector(awaddr_value), awaddr, ALLOW_WIDER, "awaddr_value", "awaddr", msg);
variable v_normalized_awuser : std_logic_vector(awuser'length-1 downto 0);
-- Helper variables
variable v_time_of_rising_edge : time := -1 ns; -- time stamp for clk period checking
variable v_time_of_falling_edge : time := -1 ns; -- time stamp for clk period checking
begin
if awid'length > 0 then
v_normalized_awid := normalize_and_check(awid_value, awid, ALLOW_WIDER, "awid_value", "awid", msg);
end if;
if awuser'length > 0 then
v_normalized_awuser := normalize_and_check(awuser_value, awuser, ALLOW_WIDER, "awuser_value", "awuser", msg);
end if;
for cycle in 0 to config.max_wait_cycles loop
-- Wait according to config.bfm_sync setup
wait_on_bfm_sync_start(clk, config.bfm_sync, config.setup_time, config.clock_period, v_time_of_falling_edge, v_time_of_rising_edge);
-- Assigning the write data channel outputs
if cycle = config.num_aw_pipe_stages then
awid <= v_normalized_awid;
awaddr <= v_normalized_awaddr;
awlen <= std_logic_vector(awlen_value);
awsize <= bytes_to_axsize(awsize_value);
awburst <= axburst_to_slv(awburst_value);
awlock <= axlock_to_sl(awlock_value);
awcache <= awcache_value;
awprot <= axprot_to_slv(awprot_value);
awqos <= awqos_value;
awregion <= awregion_value;
awuser <= v_normalized_awuser;
awvalid <= '1';
end if;
wait until rising_edge(clk);
-- Checking clock behavior
if v_time_of_rising_edge = -1 ns then
v_time_of_rising_edge := now;
end if;
check_clock_period_margin(clk, config.bfm_sync, v_time_of_falling_edge, v_time_of_rising_edge,
config.clock_period, config.clock_period_margin, config.clock_margin_severity);
-- Checking if the write address channel access is done
if awready = '1' and cycle >= config.num_aw_pipe_stages then
-- Wait according to config.bfm_sync setup
wait_on_bfm_exit(clk, config.bfm_sync, config.hold_time, v_time_of_falling_edge, v_time_of_rising_edge);
awid <= (awid'range => '0');
awaddr <= (awaddr'range => '0');
awlen <= (others=>'0');
awsize <= (others=>'0');
awburst <= (others=>'0');
awlock <= '0';
awcache <= (others=>'0');
awprot <= (others=>'0');
awqos <= (others=>'0');
awregion <= (others=>'0');
awuser <= (awuser'range => '0');
awvalid <= '0';
v_await_awready := false;
exit;
end if;
end loop;
check_value(not v_await_awready, config.max_wait_cycles_severity, ": Timeout waiting for AWREADY", scope, ID_NEVER, msg_id_panel, proc_call);
log(ID_CHANNEL_BFM, proc_call & " completed. " & add_msg_delimiter(msg), scope, msg_id_panel);
end procedure write_address_channel_write;
procedure write_data_channel_write (
constant wdata_value : in t_slv_array;
constant wstrb_value : in t_slv_array;
constant wuser_value : in t_slv_array;
constant awlen_value : in unsigned(7 downto 0);
constant msg : in string;
signal clk : in std_logic;
signal wdata : inout std_logic_vector;
signal wstrb : inout std_logic_vector;
signal wlast : inout std_logic;
signal wuser : inout std_logic_vector;
signal wvalid : inout std_logic;
signal wready : in std_logic;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axi_bfm_config := C_AXI_BFM_CONFIG_DEFAULT
) is
constant proc_call : string := "write_data_channel_write(" & to_string(wdata_value, HEX, AS_IS, INCL_RADIX) &
", " & to_string(wstrb_value, HEX, AS_IS, INCL_RADIX) & ")";
variable v_await_wready : boolean := true;
variable v_normalized_wdata : std_logic_vector(wdata'length-1 downto 0) :=
normalize_and_check(wdata_value(0), wdata, ALLOW_NARROWER, "WDATA", "wdata", msg);
variable v_normalized_wstrb : std_logic_vector(wstrb'length-1 downto 0) :=
normalize_and_check(wstrb_value(0), wstrb, ALLOW_EXACT_ONLY, "WSTRB", "wstrb", msg);
variable v_normalized_wuser : std_logic_vector(wuser'length-1 downto 0);
-- Helper variables
variable v_time_of_rising_edge : time := -1 ns; -- time stamp for clk period checking
variable v_time_of_falling_edge : time := -1 ns; -- time stamp for clk period checking
begin
if wuser'length > 0 then
v_normalized_wuser := normalize_and_check(wuser_value(0), wuser, ALLOW_NARROWER, "WSTRB", "wstrb", msg);
end if;
for write_transfer_num in 0 to to_integer(unsigned(awlen_value)) loop
for cycle in 0 to config.max_wait_cycles loop
-- Wait according to config.bfm_sync setup
wait_on_bfm_sync_start(clk, config.bfm_sync, config.setup_time, config.clock_period, v_time_of_falling_edge, v_time_of_rising_edge);
-- Assigning the write data channel outputs
if cycle = config.num_w_pipe_stages then
v_normalized_wdata := normalize_and_check(wdata_value(write_transfer_num), wdata, ALLOW_NARROWER, "wdata_value", "axi_if.wdata", msg);
v_normalized_wstrb := normalize_and_check(wstrb_value(write_transfer_num), wstrb, ALLOW_EXACT_ONLY, "wstrb_value", "wstrb", msg);
if wuser'length > 0 then
v_normalized_wuser := normalize_and_check(wuser_value(write_transfer_num), wuser, ALLOW_NARROWER, "wuser_value", "wuser", msg);
end if;
wdata <= v_normalized_wdata;
wstrb <= v_normalized_wstrb;
wuser <= v_normalized_wuser;
wvalid <= '1';
if write_transfer_num = unsigned(awlen_value) then
wlast <= '1';
end if;
end if;
wait until rising_edge(clk);
-- Checking clock behavior
if v_time_of_rising_edge = -1 ns then
v_time_of_rising_edge := now;
end if;
check_clock_period_margin(clk, config.bfm_sync, v_time_of_falling_edge, v_time_of_rising_edge,
config.clock_period, config.clock_period_margin, config.clock_margin_severity);
-- Checking if the write data channel access is done
if wready = '1' and cycle >= config.num_w_pipe_stages then
-- Wait according to config.bfm_sync setup
wait_on_bfm_exit(clk, config.bfm_sync, config.hold_time, v_time_of_falling_edge, v_time_of_rising_edge);
wdata <= (wdata'range => '0');
wstrb <= (wstrb'range => '0');
wuser <= (wuser'range => '0');
wlast <= '0';
wvalid <= '0';
v_await_wready := false;
exit;
end if;
end loop;
check_value(not v_await_wready, config.max_wait_cycles_severity, ": Timeout waiting for WREADY", scope, ID_NEVER, msg_id_panel, proc_call);
end loop;
log(ID_CHANNEL_BFM, proc_call & " completed. " & add_msg_delimiter(msg), scope, msg_id_panel);
end procedure write_data_channel_write;
procedure write_response_channel_receive (
variable bid_value : out std_logic_vector;
variable bresp_value : out t_xresp;
variable buser_value : out std_logic_vector;
constant msg : in string;
signal clk : in std_logic;
signal bid : in std_logic_vector;
signal bresp : in std_logic_vector(1 downto 0);
signal buser : in std_logic_vector;
signal bvalid : in std_logic;
signal bready : inout std_logic;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axi_bfm_config := C_AXI_BFM_CONFIG_DEFAULT;
constant ext_proc_call : in string := "" -- External proc_call. Overwrite if called from another BFM procedure
) is
constant local_proc_name : string := "write_response_channel_receive";
constant local_proc_call : string := local_proc_name & "()";
variable v_proc_call : line;
variable v_await_bvalid : boolean := true;
variable v_time_of_rising_edge : time := -1 ns; -- time stamp for clk period checking
variable v_time_of_falling_edge : time := -1 ns; -- time stamp for clk period checking
variable v_alert_radix : t_radix;
begin
-- Setting procedure name for logging
if ext_proc_call = "" then
-- Called directly from sequencer/VVC, log 'axi_read...'
write(v_proc_call, local_proc_call);
else
-- Called from another BFM procedure, log 'ext_proc_call while executing axi_read...'
write(v_proc_call, ext_proc_call & " while executing " & local_proc_name);
end if;
for cycle in 0 to config.max_wait_cycles loop
-- Wait according to config.bfm_sync setup
wait_on_bfm_sync_start(clk, config.bfm_sync, config.setup_time, config.clock_period, v_time_of_falling_edge, v_time_of_rising_edge);
-- Assigning the write response channel ready signal
if cycle = config.num_b_pipe_stages then
bready <= '1';
end if;
wait until rising_edge(clk);
if v_time_of_rising_edge = -1 ns then
v_time_of_rising_edge := now;
end if;
check_clock_period_margin(clk, config.bfm_sync, v_time_of_falling_edge, v_time_of_rising_edge,
config.clock_period, config.clock_period_margin, config.clock_margin_severity);
-- Checking if the write response channel access is done
if bvalid = '1' and cycle >= config.num_b_pipe_stages then
-- Receiving response
if bid'length > 0 then
bid_value := normalize_and_check(bid, bid_value, ALLOW_EXACT_ONLY, "bid", "bid_value", msg);
end if;
if buser'length > 0 then
buser_value := normalize_and_check(buser, buser_value, ALLOW_EXACT_ONLY, "buser", "buser_value", msg);
end if;
bresp_value := slv_to_xresp(bresp);
-- Wait according to config.bfm_sync setup
wait_on_bfm_exit(clk, config.bfm_sync, config.hold_time, v_time_of_falling_edge, v_time_of_rising_edge);
bready <= '0';
v_await_bvalid := false;
end if;
if not v_await_bvalid then
exit;
end if;
end loop;
check_value(not v_await_bvalid, config.max_wait_cycles_severity, ": Timeout waiting for BVALID", scope, ID_NEVER, msg_id_panel, v_proc_call.all);
if ext_proc_call = "" then
log(config.id_for_bfm, v_proc_call.all & " " & add_msg_delimiter(msg), scope, msg_id_panel);
else
-- Log will be handled by calling procedure (e.g. read_data_channel_check)
end if;
DEALLOCATE(v_proc_call);
end procedure write_response_channel_receive;
procedure read_address_channel_write (
constant arid_value : in std_logic_vector;
constant araddr_value : in unsigned;
constant arlen_value : in unsigned(7 downto 0);
constant arsize_value : in integer range 1 to 128;
constant arburst_value : in t_axburst;
constant arlock_value : in t_axlock;
constant arcache_value : in std_logic_vector(3 downto 0);
constant arprot_value : in t_axprot;
constant arqos_value : in std_logic_vector(3 downto 0);
constant arregion_value : in std_logic_vector(3 downto 0);
constant aruser_value : in std_logic_vector;
constant msg : in string;
signal clk : in std_logic;
signal arid : inout std_logic_vector;
signal araddr : inout std_logic_vector;
signal arlen : inout std_logic_vector(7 downto 0);
signal arsize : inout std_logic_vector(2 downto 0);
signal arburst : inout std_logic_vector(1 downto 0);
signal arlock : inout std_logic;
signal arcache : inout std_logic_vector(3 downto 0);
signal arprot : inout std_logic_vector(2 downto 0);
signal arqos : inout std_logic_vector(3 downto 0);
signal arregion : inout std_logic_vector(3 downto 0);
signal aruser : inout std_logic_vector;
signal arvalid : inout std_logic;
signal arready : in std_logic;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axi_bfm_config := C_AXI_BFM_CONFIG_DEFAULT
) is
constant proc_call : string := "read_address_channel_write(" & to_string(araddr_value, HEX, AS_IS, INCL_RADIX) & ")";
variable v_await_arready : boolean := true;
-- Normalizing unconstrained inputs
variable v_normalized_arid : std_logic_vector(arid'length-1 downto 0);
variable v_normalized_araddr : std_logic_vector(araddr'length-1 downto 0) :=
normalize_and_check(std_logic_vector(araddr_value), araddr, ALLOW_WIDER, "araddr_value", "araddr", msg);
variable v_normalized_aruser : std_logic_vector(aruser'length-1 downto 0);
-- Helper variables
variable v_time_of_rising_edge : time := -1 ns; -- time stamp for clk period checking
variable v_time_of_falling_edge : time := -1 ns; -- time stamp for clk period checking
begin
if arid'length > 0 then
v_normalized_arid := normalize_and_check(arid_value, arid, ALLOW_WIDER, "arid_value", "arid", msg);
end if;
if aruser'length > 0 then
v_normalized_aruser := normalize_and_check(aruser_value, aruser, ALLOW_WIDER, "aruser_value", "awuser", msg);
end if;
for cycle in 0 to config.max_wait_cycles loop
-- Wait according to config.bfm_sync setup
wait_on_bfm_sync_start(clk, config.bfm_sync, config.setup_time, config.clock_period, v_time_of_falling_edge, v_time_of_rising_edge);
-- Assigning the write data channel outputs
if cycle = config.num_ar_pipe_stages then
arid <= v_normalized_arid;
araddr <= v_normalized_araddr;
arlen <= std_logic_vector(arlen_value);
arsize <= bytes_to_axsize(arsize_value);
arburst <= axburst_to_slv(arburst_value);
arlock <= axlock_to_sl(arlock_value);
arcache <= arcache_value;
arprot <= axprot_to_slv(arprot_value);
arqos <= arqos_value;
arregion <= arregion_value;
aruser <= v_normalized_aruser;
arvalid <= '1';
end if;
wait until rising_edge(clk);
-- Checking clock behavior
if v_time_of_rising_edge = -1 ns then
v_time_of_rising_edge := now;
end if;
check_clock_period_margin(clk, config.bfm_sync, v_time_of_falling_edge, v_time_of_rising_edge,
config.clock_period, config.clock_period_margin, config.clock_margin_severity);
-- Checking if the write address channel access is done
if arready = '1' and cycle >= config.num_ar_pipe_stages then
-- Wait according to config.bfm_sync setup
wait_on_bfm_exit(clk, config.bfm_sync, config.hold_time, v_time_of_falling_edge, v_time_of_rising_edge);
arid <= (arid'range => '0');
araddr <= (araddr'range => '0');
arlen <= (others=>'0');
arsize <= (others=>'0');
arburst <= (others=>'0');
arlock <= '0';
arcache <= (others=>'0');
arprot <= (others=>'0');
arqos <= (others=>'0');
arregion <= (others=>'0');
aruser <= (aruser'range => '0');
arvalid <= '0';
v_await_arready := false;
exit;
end if;
end loop;
check_value(not v_await_arready, config.max_wait_cycles_severity, ": Timeout waiting for ARREADY", scope, ID_NEVER, msg_id_panel, proc_call);
log(ID_CHANNEL_BFM, proc_call & " completed. " & add_msg_delimiter(msg), scope, msg_id_panel);
end procedure read_address_channel_write;
procedure read_data_channel_receive (
variable read_result : out t_vvc_result;
variable read_data_queue : inout t_axi_read_data_queue;
constant msg : in string;
signal clk : in std_logic;
signal rid : in std_logic_vector;
signal rdata : in std_logic_vector;
signal rresp : in std_logic_vector(1 downto 0);
signal rlast : in std_logic;
signal ruser : in std_logic_vector;
signal rvalid : in std_logic;
signal rready : inout std_logic;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axi_bfm_config := C_AXI_BFM_CONFIG_DEFAULT;
constant ext_proc_call : in string := "" -- External proc_call. Overwrite if called from another BFM procedure
) is
constant local_proc_name : string := "read_data_channel_receive"; -- Local proc_name; used if called from sequncer or VVC
constant local_proc_call : string := local_proc_name & "()"; -- Local proc_call; used if called from sequncer or VVC
variable v_proc_call : line;
variable v_await_rvalid : boolean := true;
variable v_time_of_rising_edge : time := -1 ns; -- time stamp for clk period checking
variable v_time_of_falling_edge : time := -1 ns; -- time stamp for clk period checking
variable v_rlast_detected : boolean := false;
variable v_returning_rid : std_logic_vector(rid'length-1 downto 0);
variable v_read_data : t_vvc_result;
begin
if ext_proc_call = "" then
-- Called directly from sequencer/VVC, log 'axi_read...'
write(v_proc_call, local_proc_call);
else
-- Called from another BFM procedure, log 'ext_proc_call while executing axi_read...'
write(v_proc_call, ext_proc_call & " while executing " & local_proc_name);
end if;
loop
for cycle in 0 to config.max_wait_cycles loop
-- Wait according to config.bfm_sync setup
wait_on_bfm_sync_start(clk, config.bfm_sync, config.setup_time, config.clock_period, v_time_of_falling_edge, v_time_of_rising_edge);
-- Assigning the read data channel ready signal
if cycle = config.num_r_pipe_stages then
rready <= '1';
end if;
wait until rising_edge(clk);
-- Checking clock behavior
if v_time_of_rising_edge = -1 ns then
v_time_of_rising_edge := now;
end if;
check_clock_period_margin(clk, config.bfm_sync, v_time_of_falling_edge, v_time_of_rising_edge,
config.clock_period, config.clock_period_margin, config.clock_margin_severity);
-- Checking if the read data channel access is done
if rvalid = '1' and cycle >= config.num_r_pipe_stages then
v_await_rvalid := false;
-- Storing response
read_data_queue.add_to_queue(rid, rdata, slv_to_xresp(rresp), ruser);
-- Checking if the transfer is done
if rlast = '1' then
v_rlast_detected := true;
v_returning_rid := rid;
end if;
-- Wait according to config.bfm_sync setup
wait_on_bfm_exit(clk, config.bfm_sync, config.hold_time, v_time_of_falling_edge, v_time_of_rising_edge);
rready <= '0';
end if;
if not v_await_rvalid then
exit;
end if;
end loop;
check_value(not v_await_rvalid, config.max_wait_cycles_severity, ": Timeout waiting for RVALID", scope, ID_NEVER, msg_id_panel, v_proc_call.all);
if v_rlast_detected then
read_result := read_data_queue.fetch_from_queue(v_returning_rid);
exit;
end if;
v_await_rvalid := true;
end loop;
if ext_proc_call = "" then
log(config.id_for_bfm, v_proc_call.all & " " & add_msg_delimiter(msg), scope, msg_id_panel);
else
-- Log will be handled by calling procedure (e.g. read_data_channel_check)
end if;
DEALLOCATE(v_proc_call);
end procedure read_data_channel_receive;
end package body axi_channel_handler_pkg;
|
mit
|
YingcaiDong/Shunting-Model-Based-Path-Planning-Algorithm-Accelerator-Using-FPGA
|
System Design Source FIle/bd/system/ip/system_HLS_accel_0_0/hdl/ip/HLS_accel_ap_dmul_4_max_dsp_64.vhd
|
2
|
12927
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.0
-- IP Revision: 7
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_0;
USE floating_point_v7_0.floating_point_v7_0;
ENTITY HLS_accel_ap_dmul_4_max_dsp_64 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
);
END HLS_accel_ap_dmul_4_max_dsp_64;
ARCHITECTURE HLS_accel_ap_dmul_4_max_dsp_64_arch OF HLS_accel_ap_dmul_4_max_dsp_64 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF HLS_accel_ap_dmul_4_max_dsp_64_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_0 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_0;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF HLS_accel_ap_dmul_4_max_dsp_64_arch: ARCHITECTURE IS "floating_point_v7_0,Vivado 2014.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF HLS_accel_ap_dmul_4_max_dsp_64_arch : ARCHITECTURE IS "HLS_accel_ap_dmul_4_max_dsp_64,floating_point_v7_0,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF HLS_accel_ap_dmul_4_max_dsp_64_arch: ARCHITECTURE IS "HLS_accel_ap_dmul_4_max_dsp_64,floating_point_v7_0,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.0,x_ipCoreRevision=7,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=virtex7,C_HAS_ADD=0,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=1,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=64,C_A_FRACTION_WIDTH=53,C_B_WIDTH=64,C_B_FRACTION_WIDTH=53,C_C_WIDTH=64,C_C_FRACTION_WIDTH=53,C_RESULT_WIDTH=64,C_RESULT_FRACTION_WIDTH=53,C_COMPARE_OPERATION=8,C_LATENCY=4,C_OPTIMIZATION=1,C_MULT_USAGE=3,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=64,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=64,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=64,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=64,C_RESULT_TUSER_WIDTH=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_0
GENERIC MAP (
C_XDEVICEFAMILY => "virtex7",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 1,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 64,
C_A_FRACTION_WIDTH => 53,
C_B_WIDTH => 64,
C_B_FRACTION_WIDTH => 53,
C_C_WIDTH => 64,
C_C_FRACTION_WIDTH => 53,
C_RESULT_WIDTH => 64,
C_RESULT_FRACTION_WIDTH => 53,
C_COMPARE_OPERATION => 8,
C_LATENCY => 4,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 3,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 64,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 64,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 64,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 64,
C_RESULT_TUSER_WIDTH => 1
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END HLS_accel_ap_dmul_4_max_dsp_64_arch;
|
mit
|
UVVM/UVVM_All
|
bitvis_vip_clock_generator/src/vvc_methods_pkg.vhd
|
1
|
14865
|
--================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
----------------------------------------------------------------------------------------------------------------------------------
--========================================================================================================================
-- This VVC was generated with Bitvis VVC Generator
--========================================================================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
use work.vvc_cmd_pkg.all;
use work.td_target_support_pkg.all;
--========================================================================================================================
--========================================================================================================================
package vvc_methods_pkg is
--========================================================================================================================
-- Types and constants for the CLOCK_GENERATOR VVC
--========================================================================================================================
constant C_VVC_NAME : string := "CLOCK_GENERATOR_VVC";
signal CLOCK_GENERATOR_VVCT: t_vvc_target_record := set_vvc_target_defaults(C_VVC_NAME);
alias THIS_VVCT : t_vvc_target_record is CLOCK_GENERATOR_VVCT;
alias t_bfm_config is t_void_bfm_config;
-- Type found in UVVM-Util types_pkg
constant C_CLOCK_GENERATOR_INTER_BFM_DELAY_DEFAULT : t_inter_bfm_delay := (
delay_type => NO_DELAY,
delay_in_time => 0 ns,
inter_bfm_delay_violation_severity => WARNING
);
type t_vvc_config is record
inter_bfm_delay : t_inter_bfm_delay;-- Minimum delay between BFM accesses from the VVC. If parameter delay_type is set to NO_DELAY, BFM accesses will be back to back, i.e. no delay.
cmd_queue_count_max : natural; -- Maximum pending number in command executor before executor is full. Adding additional commands will result in an ERROR.
cmd_queue_count_threshold : natural; -- An alert with severity 'cmd_queue_count_threshold_severity' will be issued if command executor exceeds this count. Used for early warning if command executor is almost full. Will be ignored if set to 0.
cmd_queue_count_threshold_severity : t_alert_level; -- Severity of alert to be initiated if exceeding cmd_queue_count_threshold
result_queue_count_max : natural;
result_queue_count_threshold_severity : t_alert_level;
result_queue_count_threshold : natural;
bfm_config : t_bfm_config;
msg_id_panel : t_msg_id_panel; -- VVC dedicated message ID panel
clock_name : string(1 to 30);
clock_period : time;
clock_high_time : time;
end record;
type t_vvc_config_array is array (natural range <>) of t_vvc_config;
constant C_CLOCK_GENERATOR_VVC_CONFIG_DEFAULT : t_vvc_config := (
inter_bfm_delay => C_CLOCK_GENERATOR_INTER_BFM_DELAY_DEFAULT,
cmd_queue_count_max => C_CMD_QUEUE_COUNT_MAX, -- from adaptation package
cmd_queue_count_threshold => C_CMD_QUEUE_COUNT_THRESHOLD,
cmd_queue_count_threshold_severity => C_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY,
result_queue_count_max => C_RESULT_QUEUE_COUNT_MAX,
result_queue_count_threshold_severity => C_RESULT_QUEUE_COUNT_THRESHOLD_SEVERITY,
result_queue_count_threshold => C_RESULT_QUEUE_COUNT_THRESHOLD,
bfm_config => C_VOID_BFM_CONFIG,
msg_id_panel => C_VVC_MSG_ID_PANEL_DEFAULT,
clock_name => ("Set clock name", others => NUL),
clock_period => 10 ns,
clock_high_time => 5 ns
);
type t_vvc_status is record
current_cmd_idx : natural;
previous_cmd_idx : natural;
pending_cmd_cnt : natural;
end record;
type t_vvc_status_array is array (natural range <>) of t_vvc_status;
constant C_VVC_STATUS_DEFAULT : t_vvc_status := (
current_cmd_idx => 0,
previous_cmd_idx => 0,
pending_cmd_cnt => 0
);
-- Transaction information to include in the wave view during simulation
type t_transaction_info is record
operation : t_operation;
msg : string(1 to C_VVC_CMD_STRING_MAX_LENGTH);
--<USER_INPUT> Fields that could be useful to track in the waveview can be placed in this record.
-- Example:
-- addr : unsigned(C_VVC_CMD_ADDR_MAX_LENGTH-1 downto 0);
-- data : std_logic_vector(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0);
end record;
type t_transaction_info_array is array (natural range <>) of t_transaction_info;
constant C_TRANSACTION_INFO_DEFAULT : t_transaction_info := (
--<USER_INPUT> Set the data fields added to the t_transaction_info record to
-- their default values here.
-- Example:
-- addr => (others => '0'),
-- data => (others => '0'),
operation => NO_OPERATION,
msg => (others => ' ')
);
shared variable shared_clock_generator_vvc_config : t_vvc_config_array(0 to C_MAX_VVC_INSTANCE_NUM-1) := (others => C_CLOCK_GENERATOR_VVC_CONFIG_DEFAULT);
shared variable shared_clock_generator_vvc_status : t_vvc_status_array(0 to C_MAX_VVC_INSTANCE_NUM-1) := (others => C_VVC_STATUS_DEFAULT);
shared variable shared_clock_generator_transaction_info : t_transaction_info_array(0 to C_MAX_VVC_INSTANCE_NUM-1) := (others => C_TRANSACTION_INFO_DEFAULT);
--==========================================================================================
-- Methods dedicated to this VVC
-- - These procedures are called from the testbench in order for the VVC to execute
-- BFM calls towards the given interface. The VVC interpreter will queue these calls
-- and then the VVC executor will fetch the commands from the queue and handle the
-- actual BFM execution.
-- For details on how the BFM procedures work, see the QuickRef.
--==========================================================================================
procedure start_clock(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant msg : in string;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT
);
procedure stop_clock(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant msg : in string;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT
);
procedure set_clock_period(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant clock_period : in time;
constant msg : in string;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT
);
procedure set_clock_high_time(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant clock_high_time : in time;
constant msg : in string;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT
);
--==============================================================================
-- VVC Activity
--==============================================================================
procedure update_vvc_activity_register( signal global_trigger_vvc_activity_register : inout std_logic;
variable vvc_status : inout t_vvc_status;
constant activity : in t_activity;
constant entry_num_in_vvc_activity_register : in integer;
constant last_cmd_idx_executed : in natural;
constant command_queue_is_empty : in boolean;
constant scope : in string := C_VVC_NAME);
end package vvc_methods_pkg;
package body vvc_methods_pkg is
--========================================================================================================================
-- Methods dedicated to this VVC
--========================================================================================================================
procedure start_clock(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant msg : in string;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT
) is
constant proc_name : string := "start_clock";
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) -- First part common for all
& ")";
begin
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, START_CLOCK);
send_command_to_vvc(VVCT, scope => scope);
end procedure start_clock;
procedure stop_clock(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant msg : in string;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT
) is
constant proc_name : string := "stop_clock";
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) -- First part common for all
& ")";
begin
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, STOP_CLOCK);
send_command_to_vvc(VVCT, scope => scope);
end procedure stop_clock;
procedure set_clock_period(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant clock_period : in time;
constant msg : in string;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT
) is
constant proc_name : string := "set_clock_period";
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) -- First part common for all
& ", " & to_string(clock_period) & ")";
begin
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, SET_CLOCK_PERIOD);
shared_vvc_cmd.clock_period := clock_period;
send_command_to_vvc(VVCT, scope => scope);
end procedure set_clock_period;
procedure set_clock_high_time(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant clock_high_time : in time;
constant msg : in string;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT
) is
constant proc_name : string := "set_clock_high_time";
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) -- First part common for all
& ", " & to_string(clock_high_time) & ")";
begin
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, SET_CLOCK_HIGH_TIME);
shared_vvc_cmd.clock_high_time := clock_high_time;
send_command_to_vvc(VVCT, scope => scope);
end procedure set_clock_high_time;
--==============================================================================
-- VVC Activity
--==============================================================================
procedure update_vvc_activity_register( signal global_trigger_vvc_activity_register : inout std_logic;
variable vvc_status : inout t_vvc_status;
constant activity : in t_activity;
constant entry_num_in_vvc_activity_register : in integer;
constant last_cmd_idx_executed : in natural;
constant command_queue_is_empty : in boolean;
constant scope : in string := C_VVC_NAME) is
variable v_activity : t_activity := activity;
begin
-- Update vvc_status after a command has finished (during same delta cycle the activity register is updated)
if activity = INACTIVE then
vvc_status.previous_cmd_idx := last_cmd_idx_executed;
vvc_status.current_cmd_idx := 0;
end if;
if v_activity = INACTIVE and not(command_queue_is_empty) then
v_activity := ACTIVE;
end if;
shared_vvc_activity_register.priv_report_vvc_activity(vvc_idx => entry_num_in_vvc_activity_register,
activity => v_activity,
last_cmd_idx_executed => last_cmd_idx_executed);
if global_trigger_vvc_activity_register /= 'L' then
wait until global_trigger_vvc_activity_register = 'L';
end if;
gen_pulse(global_trigger_vvc_activity_register, 0 ns, "pulsing global trigger for vvc activity register", scope, ID_NEVER);
end procedure;
end package body vvc_methods_pkg;
|
mit
|
YingcaiDong/Shunting-Model-Based-Path-Planning-Algorithm-Accelerator-Using-FPGA
|
System Design Source FIle/ipshared/xilinx.com/xbip_bram18k_v3_0/902b235a/hdl/xbip_bram18k_v3_0.vhd
|
2
|
8791
|
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`protect end_protected
|
mit
|
UVVM/UVVM_All
|
bitvis_vip_axilite/src/axilite_vvc.vhd
|
1
|
48206
|
--================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
----------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
library bitvis_vip_scoreboard;
use bitvis_vip_scoreboard.generic_sb_support_pkg.C_SB_CONFIG_DEFAULT;
use work.axilite_bfm_pkg.all;
use work.axilite_channel_handler_pkg.all;
use work.vvc_methods_pkg.all;
use work.vvc_cmd_pkg.all;
use work.td_target_support_pkg.all;
use work.td_vvc_entity_support_pkg.all;
use work.td_cmd_queue_pkg.all;
use work.td_result_queue_pkg.all;
use work.transaction_pkg.all;
--=================================================================================================
entity axilite_vvc is
generic (
GC_ADDR_WIDTH : integer range 1 to C_VVC_CMD_ADDR_MAX_LENGTH := 8;
GC_DATA_WIDTH : integer range 1 to C_VVC_CMD_DATA_MAX_LENGTH := 32;
GC_INSTANCE_IDX : natural := 1; -- Instance index for this AXILITE_VVCT instance
GC_AXILITE_CONFIG : t_axilite_bfm_config := C_AXILITE_BFM_CONFIG_DEFAULT; -- Behavior specification for BFM
GC_CMD_QUEUE_COUNT_MAX : natural := 1000;
GC_CMD_QUEUE_COUNT_THRESHOLD : natural := 950;
GC_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY : t_alert_level := WARNING;
GC_RESULT_QUEUE_COUNT_MAX : natural := 1000;
GC_RESULT_QUEUE_COUNT_THRESHOLD : natural := 950;
GC_RESULT_QUEUE_COUNT_THRESHOLD_SEVERITY : t_alert_level := WARNING
);
port (
clk : in std_logic;
axilite_vvc_master_if : inout t_axilite_if := init_axilite_if_signals(GC_ADDR_WIDTH, GC_DATA_WIDTH)
);
begin
-- Check the interface widths to assure that the interface was correctly set up
assert (axilite_vvc_master_if.write_address_channel.awaddr'length = GC_ADDR_WIDTH) report "axilite_vvc_master_if.write_address_channel.awaddr'length =/ GC_ADDR_WIDTH" severity failure;
assert (axilite_vvc_master_if.read_address_channel.araddr'length = GC_ADDR_WIDTH) report "axilite_vvc_master_if.read_address_channel.araddr'length =/ GC_ADDR_WIDTH" severity failure;
assert (axilite_vvc_master_if.write_data_channel.wdata'length = GC_DATA_WIDTH) report "axilite_vvc_master_if.write_data_channel.wdata'length =/ GC_DATA_WIDTH" severity failure;
assert (axilite_vvc_master_if.write_data_channel.wstrb'length = GC_DATA_WIDTH/8) report "axilite_vvc_master_if.write_data_channel.wstrb'length =/ GC_DATA_WIDTH/8" severity failure;
assert (axilite_vvc_master_if.read_data_channel.rdata'length = GC_DATA_WIDTH) report "axilite_vvc_master_if.read_data_channel.rdata'length =/ GC_DATA_WIDTH" severity failure;
end entity axilite_vvc;
--=================================================================================================
--=================================================================================================
architecture behave of axilite_vvc is
constant C_SCOPE : string := C_VVC_NAME & "," & to_string(GC_INSTANCE_IDX);
constant C_VVC_LABELS : t_vvc_labels := assign_vvc_labels(C_SCOPE, C_VVC_NAME, GC_INSTANCE_IDX, NA);
signal executor_is_busy : boolean := false;
signal write_address_channel_executor_is_busy : boolean := false;
signal write_data_channel_executor_is_busy : boolean := false;
signal write_response_channel_executor_is_busy : boolean := false;
signal read_address_channel_executor_is_busy : boolean := false;
signal read_data_channel_executor_is_busy : boolean := false;
signal any_executors_busy : boolean := false;
signal queue_is_increasing : boolean := false;
signal write_address_channel_queue_is_increasing : boolean := false;
signal write_data_channel_queue_is_increasing : boolean := false;
signal write_response_channel_queue_is_increasing : boolean := false;
signal read_address_channel_queue_is_increasing : boolean := false;
signal read_data_channel_queue_is_increasing : boolean := false;
signal last_cmd_idx_executed : natural := natural'high;
signal last_write_response_channel_idx_executed : natural := 0;
signal last_read_data_channel_idx_executed : natural := 0;
signal terminate_current_cmd : t_flag_record;
-- Instantiation of the element dedicated Queue
shared variable command_queue : work.td_cmd_queue_pkg.t_generic_queue;
shared variable write_address_channel_queue : work.td_cmd_queue_pkg.t_generic_queue;
shared variable write_data_channel_queue : work.td_cmd_queue_pkg.t_generic_queue;
shared variable write_response_channel_queue : work.td_cmd_queue_pkg.t_generic_queue;
shared variable read_address_channel_queue : work.td_cmd_queue_pkg.t_generic_queue;
shared variable read_data_channel_queue : work.td_cmd_queue_pkg.t_generic_queue;
shared variable result_queue : work.td_result_queue_pkg.t_generic_queue;
alias vvc_config : t_vvc_config is shared_axilite_vvc_config(GC_INSTANCE_IDX);
alias vvc_status : t_vvc_status is shared_axilite_vvc_status(GC_INSTANCE_IDX);
-- Transaction info
alias vvc_transaction_info_trigger : std_logic is global_axilite_vvc_transaction_trigger(GC_INSTANCE_IDX);
alias vvc_transaction_info : t_transaction_group is shared_axilite_vvc_transaction_info(GC_INSTANCE_IDX);
-- VVC Activity
signal entry_num_in_vvc_activity_register : integer;
--UVVM: temporary fix for HVVC, remove function below in v3.0
function get_msg_id_panel(
constant command : in t_vvc_cmd_record;
constant vvc_config : in t_vvc_config
) return t_msg_id_panel is
begin
-- If the parent_msg_id_panel is set then use it,
-- otherwise use the VVCs msg_id_panel from its config.
if command.msg(1 to 5) = "HVVC:" then
return vvc_config.parent_msg_id_panel;
else
return vvc_config.msg_id_panel;
end if;
end function;
impure function queues_are_empty(
constant void : t_void
) return boolean is
variable v_return : boolean := false;
begin
return command_queue.is_empty(VOID) and
write_address_channel_queue.is_empty(VOID) and
write_data_channel_queue.is_empty(VOID) and
write_response_channel_queue.is_empty(VOID) and
read_address_channel_queue.is_empty(VOID) and
read_data_channel_queue.is_empty(VOID);
end function;
begin
--===============================================================================================
-- Constructor
-- - Set up the defaults and show constructor if enabled
--===============================================================================================
work.td_vvc_entity_support_pkg.vvc_constructor(C_SCOPE, GC_INSTANCE_IDX, vvc_config, command_queue, result_queue, GC_AXILITE_CONFIG,
GC_CMD_QUEUE_COUNT_MAX, GC_CMD_QUEUE_COUNT_THRESHOLD, GC_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY,
GC_RESULT_QUEUE_COUNT_MAX, GC_RESULT_QUEUE_COUNT_THRESHOLD, GC_RESULT_QUEUE_COUNT_THRESHOLD_SEVERITY);
--===============================================================================================
--===============================================================================================
-- Set if any of the executors are busy
--===============================================================================================
any_executors_busy <= executor_is_busy or
write_address_channel_executor_is_busy or
write_data_channel_executor_is_busy or
write_response_channel_executor_is_busy or
read_address_channel_executor_is_busy or
read_data_channel_executor_is_busy;
--===============================================================================================
--===============================================================================================
-- Command interpreter
-- - Interpret, decode and acknowledge commands from the central sequencer
--===============================================================================================
cmd_interpreter : process
variable v_cmd_has_been_acked : boolean; -- Indicates if acknowledge_cmd() has been called for the current shared_vvc_cmd
variable v_local_vvc_cmd : t_vvc_cmd_record := C_VVC_CMD_DEFAULT;
variable v_msg_id_panel : t_msg_id_panel;
variable v_temp_msg_id_panel : t_msg_id_panel; --UVVM: temporary fix for HVVC, remove in v3.0
begin
-- 0. Initialize the process prior to first command
work.td_vvc_entity_support_pkg.initialize_interpreter(terminate_current_cmd, global_awaiting_completion);
-- initialise shared_vvc_last_received_cmd_idx for channel and instance
shared_vvc_last_received_cmd_idx(NA, GC_INSTANCE_IDX) := 0;
-- Register VVC in vvc activity register
entry_num_in_vvc_activity_register <= shared_vvc_activity_register.priv_register_vvc( name => C_VVC_NAME,
instance => GC_INSTANCE_IDX,
await_selected_supported => false);
-- Set initial value of v_msg_id_panel to msg_id_panel in config
v_msg_id_panel := vvc_config.msg_id_panel;
-- Then for every single command from the sequencer
loop -- basically as long as new commands are received
-- 1. wait until command targeted at this VVC. Must match VVC name, instance and channel (if applicable)
-- releases global semaphore
-------------------------------------------------------------------------
work.td_vvc_entity_support_pkg.await_cmd_from_sequencer(C_VVC_LABELS, vvc_config, THIS_VVCT, VVC_BROADCAST, global_vvc_busy, global_vvc_ack, v_local_vvc_cmd);
v_cmd_has_been_acked := false; -- Clear flag
-- update shared_vvc_last_received_cmd_idx with received command index
shared_vvc_last_received_cmd_idx(NA, GC_INSTANCE_IDX) := v_local_vvc_cmd.cmd_idx;
-- Select between a provided msg_id_panel via the vvc_cmd_record from a VVC with a higher hierarchy or the
-- msg_id_panel in this VVC's config. This is to correctly handle the logging when using Hierarchical-VVCs.
v_msg_id_panel := get_msg_id_panel(v_local_vvc_cmd, vvc_config);
-- 2a. Put command on the queue if intended for the executor
-------------------------------------------------------------------------
if v_local_vvc_cmd.command_type = QUEUED then
work.td_vvc_entity_support_pkg.put_command_on_queue(v_local_vvc_cmd, command_queue, vvc_status, queue_is_increasing);
-- 2b. Otherwise command is intended for immediate response
-------------------------------------------------------------------------
elsif v_local_vvc_cmd.command_type = IMMEDIATE then
--UVVM: temporary fix for HVVC, remove two lines below in v3.0
if v_local_vvc_cmd.operation /= DISABLE_LOG_MSG and v_local_vvc_cmd.operation /= ENABLE_LOG_MSG then
v_temp_msg_id_panel := vvc_config.msg_id_panel;
vvc_config.msg_id_panel := v_msg_id_panel;
end if;
case v_local_vvc_cmd.operation is
when AWAIT_COMPLETION =>
work.td_vvc_entity_support_pkg.interpreter_await_completion(v_local_vvc_cmd, command_queue, vvc_config, any_executors_busy, C_VVC_LABELS, last_cmd_idx_executed);
when AWAIT_ANY_COMPLETION =>
if not v_local_vvc_cmd.gen_boolean then
-- Called with lastness = NOT_LAST: Acknowledge immediately to let the sequencer continue
work.td_target_support_pkg.acknowledge_cmd(global_vvc_ack,v_local_vvc_cmd.cmd_idx);
v_cmd_has_been_acked := true;
end if;
work.td_vvc_entity_support_pkg.interpreter_await_any_completion(v_local_vvc_cmd, command_queue, vvc_config, any_executors_busy, C_VVC_LABELS, last_cmd_idx_executed, global_awaiting_completion);
when DISABLE_LOG_MSG =>
uvvm_util.methods_pkg.disable_log_msg(v_local_vvc_cmd.msg_id, vvc_config.msg_id_panel, to_string(v_local_vvc_cmd.msg) & format_command_idx(v_local_vvc_cmd), C_SCOPE, v_local_vvc_cmd.quietness);
when ENABLE_LOG_MSG =>
uvvm_util.methods_pkg.enable_log_msg(v_local_vvc_cmd.msg_id, vvc_config.msg_id_panel, to_string(v_local_vvc_cmd.msg) & format_command_idx(v_local_vvc_cmd), C_SCOPE, v_local_vvc_cmd.quietness);
when FLUSH_COMMAND_QUEUE =>
work.td_vvc_entity_support_pkg.interpreter_flush_command_queue(v_local_vvc_cmd, command_queue, vvc_config, vvc_status, C_VVC_LABELS);
work.td_vvc_entity_support_pkg.interpreter_flush_command_queue(v_local_vvc_cmd, write_address_channel_queue, vvc_config, vvc_status, C_VVC_LABELS);
work.td_vvc_entity_support_pkg.interpreter_flush_command_queue(v_local_vvc_cmd, write_data_channel_queue, vvc_config, vvc_status, C_VVC_LABELS);
work.td_vvc_entity_support_pkg.interpreter_flush_command_queue(v_local_vvc_cmd, write_response_channel_queue, vvc_config, vvc_status, C_VVC_LABELS);
work.td_vvc_entity_support_pkg.interpreter_flush_command_queue(v_local_vvc_cmd, read_address_channel_queue, vvc_config, vvc_status, C_VVC_LABELS);
work.td_vvc_entity_support_pkg.interpreter_flush_command_queue(v_local_vvc_cmd, read_data_channel_queue, vvc_config, vvc_status, C_VVC_LABELS);
when TERMINATE_CURRENT_COMMAND =>
work.td_vvc_entity_support_pkg.interpreter_terminate_current_command(v_local_vvc_cmd, vvc_config, C_VVC_LABELS, terminate_current_cmd);
when FETCH_RESULT =>
work.td_vvc_entity_support_pkg.interpreter_fetch_result(result_queue, v_local_vvc_cmd, vvc_config, C_VVC_LABELS, last_cmd_idx_executed, shared_vvc_response);
when others =>
tb_error("Unsupported command received for IMMEDIATE execution: '" & to_string(v_local_vvc_cmd.operation) & "'", C_SCOPE);
end case;
--UVVM: temporary fix for HVVC, remove line below in v3.0
if v_local_vvc_cmd.operation /= DISABLE_LOG_MSG and v_local_vvc_cmd.operation /= ENABLE_LOG_MSG then
vvc_config.msg_id_panel := v_temp_msg_id_panel;
end if;
else
tb_error("command_type is not IMMEDIATE or QUEUED", C_SCOPE);
end if;
-- 3. Acknowledge command after runing or queuing the command
-------------------------------------------------------------------------
if not v_cmd_has_been_acked then
work.td_target_support_pkg.acknowledge_cmd(global_vvc_ack,v_local_vvc_cmd.cmd_idx);
end if;
end loop;
end process;
--===============================================================================================
--===============================================================================================
-- Updating the activity register
--===============================================================================================
p_activity_register_update : process
variable v_cmd_queues_are_empty : boolean;
begin
-- Wait until active and set the activity register to ACTIVE
if not any_executors_busy then
wait until any_executors_busy;
end if;
v_cmd_queues_are_empty := queues_are_empty(VOID);
update_vvc_activity_register(global_trigger_vvc_activity_register, vvc_status, ACTIVE, entry_num_in_vvc_activity_register, last_cmd_idx_executed, v_cmd_queues_are_empty, C_SCOPE);
-- Wait until inactive and set the activity register to INACTIVE
if any_executors_busy then
wait until not any_executors_busy;
end if;
v_cmd_queues_are_empty := queues_are_empty(VOID);
update_vvc_activity_register(global_trigger_vvc_activity_register, vvc_status, INACTIVE, entry_num_in_vvc_activity_register, last_cmd_idx_executed, v_cmd_queues_are_empty, C_SCOPE);
end process p_activity_register_update;
--===============================================================================================
-- Command executor
-- - Fetch and execute the commands
--===============================================================================================
cmd_executor : process
variable v_cmd : t_vvc_cmd_record;
variable v_read_data : t_vvc_result; -- See vvc_cmd_pkg
variable v_timestamp_start_of_current_bfm_access : time := 0 ns;
variable v_timestamp_start_of_last_bfm_access : time := 0 ns;
variable v_timestamp_end_of_last_bfm_access : time := 0 ns;
variable v_command_is_bfm_access : boolean := false;
variable v_prev_command_was_bfm_access : boolean := false;
variable v_msg_id_panel : t_msg_id_panel;
variable v_normalised_addr : unsigned(GC_ADDR_WIDTH-1 downto 0) := (others => '0');
variable v_normalised_data : std_logic_vector(GC_DATA_WIDTH-1 downto 0) := (others => '0');
variable v_cmd_queues_are_empty : boolean;
begin
-- 0. Initialize the process prior to first command
-------------------------------------------------------------------------
work.td_vvc_entity_support_pkg.initialize_executor(terminate_current_cmd);
-- Set initial value of v_msg_id_panel to msg_id_panel in config
v_msg_id_panel := vvc_config.msg_id_panel;
-- Setup AXILite scoreboard
AXILITE_VVC_SB.set_scope("AXILITE_VVC_SB");
AXILITE_VVC_SB.enable(GC_INSTANCE_IDX, "AXILITE VVC SB Enabled");
AXILITE_VVC_SB.config(GC_INSTANCE_IDX, C_SB_CONFIG_DEFAULT);
AXILITE_VVC_SB.enable_log_msg(GC_INSTANCE_IDX, ID_DATA);
loop
-- 1. Set defaults, fetch command and log
-------------------------------------------------------------------------
work.td_vvc_entity_support_pkg.fetch_command_and_prepare_executor(v_cmd, command_queue, vvc_config, vvc_status, queue_is_increasing, executor_is_busy, C_VVC_LABELS);
-- Select between a provided msg_id_panel via the vvc_cmd_record from a VVC with a higher hierarchy or the
-- msg_id_panel in this VVC's config. This is to correctly handle the logging when using Hierarchical-VVCs.
v_msg_id_panel := get_msg_id_panel(v_cmd, vvc_config);
-- Check if command is a BFM access
v_prev_command_was_bfm_access := v_command_is_bfm_access; -- save for inter_bfm_delay
if v_cmd.operation = WRITE or v_cmd.operation = READ or v_cmd.operation = CHECK then
v_command_is_bfm_access := true;
else
v_command_is_bfm_access := false;
end if;
-- Insert delay if needed
work.td_vvc_entity_support_pkg.insert_inter_bfm_delay_if_requested(vvc_config => vvc_config,
command_is_bfm_access => v_prev_command_was_bfm_access,
timestamp_start_of_last_bfm_access => v_timestamp_start_of_last_bfm_access,
timestamp_end_of_last_bfm_access => v_timestamp_end_of_last_bfm_access,
msg_id_panel => v_msg_id_panel,
scope => C_SCOPE);
if v_command_is_bfm_access then
v_timestamp_start_of_current_bfm_access := now;
end if;
-- 2. Execute the fetched command
-------------------------------------------------------------------------
case v_cmd.operation is -- Only operations in the dedicated record are relevant
-- VVC dedicated operations
--===================================
when WRITE =>
-- Set vvc transaction info
set_global_vvc_transaction_info(vvc_transaction_info_trigger, vvc_transaction_info, v_cmd, vvc_config);
-- Normalise address and data
v_normalised_addr := normalize_and_check(v_cmd.addr, v_normalised_addr, ALLOW_WIDER_NARROWER, "v_cmd.addr", "v_normalised_addr", "axilite_write() called with to wide address. " & v_cmd.msg);
v_normalised_data := normalize_and_check(v_cmd.data, v_normalised_data, ALLOW_WIDER_NARROWER, "v_cmd.data", "v_normalised_data", "axilite_write() called with to wide data. " & v_cmd.msg);
-- Adding the write command to the write address channel queue , write data channel queue and write response channel queue
work.td_vvc_entity_support_pkg.put_command_on_queue(v_cmd, write_address_channel_queue, vvc_status, write_address_channel_queue_is_increasing);
work.td_vvc_entity_support_pkg.put_command_on_queue(v_cmd, write_data_channel_queue, vvc_status, write_data_channel_queue_is_increasing);
work.td_vvc_entity_support_pkg.put_command_on_queue(v_cmd, write_response_channel_queue, vvc_status, write_response_channel_queue_is_increasing);
when READ =>
-- Set vvc transaction info
set_global_vvc_transaction_info(vvc_transaction_info_trigger, vvc_transaction_info, v_cmd, vvc_config);
-- Normalise address and data
v_normalised_addr := normalize_and_check(v_cmd.addr, v_normalised_addr, ALLOW_WIDER_NARROWER, "v_cmd.addr", "v_normalised_addr", "axilite_read() called with to wide address. " & v_cmd.msg);
-- Adding the read command to the read address channel queue and the read address data queue
work.td_vvc_entity_support_pkg.put_command_on_queue(v_cmd, read_address_channel_queue, vvc_status, read_address_channel_queue_is_increasing);
work.td_vvc_entity_support_pkg.put_command_on_queue(v_cmd, read_data_channel_queue, vvc_status, read_data_channel_queue_is_increasing);
when CHECK =>
-- Set vvc transaction info
set_global_vvc_transaction_info(vvc_transaction_info_trigger, vvc_transaction_info, v_cmd, vvc_config);
-- Normalise address and data
v_normalised_addr := normalize_and_check(v_cmd.addr, v_normalised_addr, ALLOW_WIDER_NARROWER, "v_cmd.addr", "v_normalised_addr", "axilite_check() called with to wide address. " & v_cmd.msg);
v_normalised_data := normalize_and_check(v_cmd.data, v_normalised_data, ALLOW_WIDER_NARROWER, "v_cmd.data", "v_normalised_data", "axilite_check() called with to wide data. " & v_cmd.msg);
-- Adding the check command to the read address channel queue and the read address data queue
work.td_vvc_entity_support_pkg.put_command_on_queue(v_cmd, read_address_channel_queue, vvc_status, read_address_channel_queue_is_increasing);
work.td_vvc_entity_support_pkg.put_command_on_queue(v_cmd, read_data_channel_queue, vvc_status, read_data_channel_queue_is_increasing);
-- UVVM common operations
--===================================
when INSERT_DELAY =>
log(ID_INSERTED_DELAY, "Running: " & to_string(v_cmd.proc_call) & " " & format_command_idx(v_cmd), C_SCOPE, v_msg_id_panel);
if v_cmd.gen_integer_array(0) = -1 then
-- Delay specified using time
wait until terminate_current_cmd.is_active = '1' for v_cmd.delay;
else
-- Delay specified using integer
check_value(vvc_config.bfm_config.clock_period > -1 ns, TB_ERROR, "Check that clock_period is configured when using insert_delay().",
C_SCOPE, ID_NEVER, v_msg_id_panel);
wait until terminate_current_cmd.is_active = '1' for v_cmd.gen_integer_array(0) * vvc_config.bfm_config.clock_period;
end if;
when others =>
tb_error("Unsupported local command received for execution: '" & to_string(v_cmd.operation) & "'", C_SCOPE);
end case;
if v_command_is_bfm_access then
v_timestamp_end_of_last_bfm_access := now;
v_timestamp_start_of_last_bfm_access := v_timestamp_start_of_current_bfm_access;
if ((vvc_config.inter_bfm_delay.delay_type = TIME_START2START) and
((now - v_timestamp_start_of_current_bfm_access) > vvc_config.inter_bfm_delay.delay_in_time)) then
alert(vvc_config.inter_bfm_delay.inter_bfm_delay_violation_severity, "BFM access exceeded specified start-to-start inter-bfm delay, " &
to_string(vvc_config.inter_bfm_delay.delay_in_time) & ".", C_SCOPE);
end if;
end if;
-- Reset terminate flag if any occurred
if (terminate_current_cmd.is_active = '1') then
log(ID_CMD_EXECUTOR, "Termination request received", C_SCOPE, v_msg_id_panel);
uvvm_vvc_framework.ti_vvc_framework_support_pkg.reset_flag(terminate_current_cmd);
end if;
-- In case we only allow a single pending transaction, wait here until every channel is finished.
-- Even though this wait doesn't have a timeout, each of the executors have timeouts.
if vvc_config.force_single_pending_transaction and v_command_is_bfm_access then
wait until not write_address_channel_executor_is_busy and
not write_data_channel_executor_is_busy and
not write_response_channel_executor_is_busy and
not read_address_channel_executor_is_busy and
not read_data_channel_executor_is_busy;
end if;
end loop;
end process;
--===============================================================================================
--===============================================================================================
-- Read address channel executor
-- - Fetch and execute the read address channel transactions
--===============================================================================================
read_address_channel_executor : process
variable v_cmd : t_vvc_cmd_record;
variable v_msg_id_panel : t_msg_id_panel;
variable v_normalised_addr : unsigned(GC_ADDR_WIDTH-1 downto 0) := (others => '0');
variable v_cmd_queues_are_empty : boolean;
constant C_CHANNEL_SCOPE : string := C_VVC_NAME & "_AR" & "," & to_string(GC_INSTANCE_IDX);
constant C_CHANNEL_VVC_LABELS : t_vvc_labels := assign_vvc_labels(C_CHANNEL_SCOPE, C_VVC_NAME, GC_INSTANCE_IDX, NA);
begin
-- Set the command response queue up to the same settings as the command queue
read_address_channel_queue.set_scope(C_CHANNEL_SCOPE & ":Q");
read_address_channel_queue.set_queue_count_max(vvc_config.cmd_queue_count_max);
read_address_channel_queue.set_queue_count_threshold(vvc_config.cmd_queue_count_threshold);
read_address_channel_queue.set_queue_count_threshold_severity(vvc_config.cmd_queue_count_threshold_severity);
-- Wait until VVC is registered in vvc activity register in the interpreter
wait until entry_num_in_vvc_activity_register >= 0;
-- Set initial value of v_msg_id_panel to msg_id_panel in config
v_msg_id_panel := vvc_config.msg_id_panel;
loop
-- Fetch commands
work.td_vvc_entity_support_pkg.fetch_command_and_prepare_executor(v_cmd, read_address_channel_queue, vvc_config, vvc_status, read_address_channel_queue_is_increasing, read_address_channel_executor_is_busy, C_CHANNEL_VVC_LABELS, shared_msg_id_panel, ID_CHANNEL_EXECUTOR, ID_CHANNEL_EXECUTOR_WAIT);
-- Select between a provided msg_id_panel via the vvc_cmd_record from a VVC with a higher hierarchy or the
-- msg_id_panel in this VVC's config. This is to correctly handle the logging when using Hierarchical-VVCs.
v_msg_id_panel := get_msg_id_panel(v_cmd, vvc_config);
-- Normalise address
v_normalised_addr := normalize_and_check(v_cmd.addr, v_normalised_addr, ALLOW_WIDER_NARROWER, "addr", "shared_vvc_cmd.addr", "Function called with to wide address. " & v_cmd.msg);
-- Handling commands
case v_cmd.operation is
when READ | CHECK =>
-- Set vvc transaction info
set_arw_vvc_transaction_info(vvc_transaction_info_trigger, vvc_transaction_info, v_cmd, vvc_config);
-- Start transaction
read_address_channel_write(araddr_value => std_logic_vector(v_normalised_addr),
msg => format_msg(v_cmd),
clk => clk,
araddr => axilite_vvc_master_if.read_address_channel.araddr,
arvalid => axilite_vvc_master_if.read_address_channel.arvalid,
arprot => axilite_vvc_master_if.read_address_channel.arprot,
arready => axilite_vvc_master_if.read_address_channel.arready,
scope => C_CHANNEL_SCOPE,
msg_id_panel => v_msg_id_panel,
config => vvc_config.bfm_config);
when others =>
tb_error("Unsupported local command received for execution: '" & to_string(v_cmd.operation) & "'", C_CHANNEL_SCOPE);
end case;
-- Set vvc transaction info back to default values
reset_arw_vvc_transaction_info(vvc_transaction_info, v_cmd);
end loop;
end process;
--===============================================================================================
--===============================================================================================
-- Read data channel executor
-- - Fetch and execute the read data channel transactions
--===============================================================================================
read_data_channel_executor : process
variable v_cmd : t_vvc_cmd_record;
variable v_msg_id_panel : t_msg_id_panel;
variable v_read_data : t_vvc_result; -- See vvc_cmd_pkg
variable v_normalised_data : std_logic_vector(GC_DATA_WIDTH-1 downto 0) := (others => '0');
variable v_cmd_queues_are_empty : boolean;
constant C_CHANNEL_SCOPE : string := C_VVC_NAME & "_R" & "," & to_string(GC_INSTANCE_IDX);
constant C_CHANNEL_VVC_LABELS : t_vvc_labels := assign_vvc_labels(C_CHANNEL_SCOPE, C_VVC_NAME, GC_INSTANCE_IDX, NA);
begin
-- Set the command response queue up to the same settings as the command queue
read_data_channel_queue.set_scope(C_CHANNEL_SCOPE & ":Q");
read_data_channel_queue.set_queue_count_max(vvc_config.cmd_queue_count_max);
read_data_channel_queue.set_queue_count_threshold(vvc_config.cmd_queue_count_threshold);
read_data_channel_queue.set_queue_count_threshold_severity(vvc_config.cmd_queue_count_threshold_severity);
-- Wait until VVC is registered in vvc activity register in the interpreter
wait until entry_num_in_vvc_activity_register >= 0;
-- Set initial value of v_msg_id_panel to msg_id_panel in config
v_msg_id_panel := vvc_config.msg_id_panel;
loop
-- Fetch commands
work.td_vvc_entity_support_pkg.fetch_command_and_prepare_executor(v_cmd, read_data_channel_queue, vvc_config, vvc_status, read_data_channel_queue_is_increasing, read_data_channel_executor_is_busy, C_CHANNEL_VVC_LABELS, shared_msg_id_panel, ID_CHANNEL_EXECUTOR, ID_CHANNEL_EXECUTOR_WAIT);
-- Select between a provided msg_id_panel via the vvc_cmd_record from a VVC with a higher hierarchy or the
-- msg_id_panel in this VVC's config. This is to correctly handle the logging when using Hierarchical-VVCs.
v_msg_id_panel := get_msg_id_panel(v_cmd, vvc_config);
-- Normalise data
v_normalised_data := normalize_and_check(v_cmd.data, v_normalised_data, ALLOW_WIDER_NARROWER, "data", "shared_vvc_cmd.data", "Function called with to wide data. " & v_cmd.msg);
-- Handling commands
case v_cmd.operation is
when READ =>
-- Set vvc transaction info
set_r_vvc_transaction_info(vvc_transaction_info_trigger, vvc_transaction_info, v_cmd, vvc_config);
-- Start transaction
read_data_channel_receive(rdata_value => v_read_data(GC_DATA_WIDTH-1 downto 0),
msg => format_msg(v_cmd),
clk => clk,
rready => axilite_vvc_master_if.read_data_channel.rready,
rdata => axilite_vvc_master_if.read_data_channel.rdata,
rresp => axilite_vvc_master_if.read_data_channel.rresp,
rvalid => axilite_vvc_master_if.read_data_channel.rvalid,
scope => C_CHANNEL_SCOPE,
msg_id_panel => v_msg_id_panel,
config => vvc_config.bfm_config);
-- Request SB check result
if v_cmd.data_routing = TO_SB then
-- call SB check_received
AXILITE_VVC_SB.check_received(GC_INSTANCE_IDX, pad_axilite_sb(v_read_data(GC_DATA_WIDTH-1 downto 0)));
else
-- Store the result
work.td_vvc_entity_support_pkg.store_result( result_queue => result_queue,
cmd_idx => v_cmd.cmd_idx,
result => v_read_data);
end if;
when CHECK =>
-- Set vvc transaction info
set_r_vvc_transaction_info(vvc_transaction_info_trigger, vvc_transaction_info, v_cmd, vvc_config);
-- Start transaction
read_data_channel_check(rdata_exp => v_normalised_data,
msg => format_msg(v_cmd),
clk => clk,
rready => axilite_vvc_master_if.read_data_channel.rready,
rdata => axilite_vvc_master_if.read_data_channel.rdata,
rresp => axilite_vvc_master_if.read_data_channel.rresp,
rvalid => axilite_vvc_master_if.read_data_channel.rvalid,
alert_level => v_cmd.alert_level,
scope => C_CHANNEL_SCOPE,
msg_id_panel => v_msg_id_panel,
config => vvc_config.bfm_config);
when others =>
tb_error("Unsupported local command received for execution: '" & to_string(v_cmd.operation) & "'", C_CHANNEL_SCOPE);
end case;
last_read_data_channel_idx_executed <= v_cmd.cmd_idx;
-- Set vvc transaction info back to default values
reset_r_vvc_transaction_info(vvc_transaction_info);
reset_vvc_transaction_info(vvc_transaction_info, v_cmd);
end loop;
end process;
--===============================================================================================
--===============================================================================================
-- write address channel executor
-- - Fetch and execute the write address channel transactions
--===============================================================================================
write_address_channel_executor : process
variable v_cmd : t_vvc_cmd_record;
variable v_msg_id_panel : t_msg_id_panel;
variable v_normalised_addr : unsigned(GC_ADDR_WIDTH-1 downto 0) := (others => '0');
variable v_cmd_queues_are_empty : boolean;
constant C_CHANNEL_SCOPE : string := C_VVC_NAME & "_AW" & "," & to_string(GC_INSTANCE_IDX);
constant C_CHANNEL_VVC_LABELS : t_vvc_labels := assign_vvc_labels(C_CHANNEL_SCOPE, C_VVC_NAME, GC_INSTANCE_IDX, NA);
begin
-- Set the command response queue up to the same settings as the command queue
write_address_channel_queue.set_scope(C_CHANNEL_SCOPE & ":Q");
write_address_channel_queue.set_queue_count_max(vvc_config.cmd_queue_count_max);
write_address_channel_queue.set_queue_count_threshold(vvc_config.cmd_queue_count_threshold);
write_address_channel_queue.set_queue_count_threshold_severity(vvc_config.cmd_queue_count_threshold_severity);
-- Wait until VVC is registered in vvc activity register in the interpreter
wait until entry_num_in_vvc_activity_register >= 0;
-- Set initial value of v_msg_id_panel to msg_id_panel in config
v_msg_id_panel := vvc_config.msg_id_panel;
loop
-- Fetch commands
work.td_vvc_entity_support_pkg.fetch_command_and_prepare_executor(v_cmd, write_address_channel_queue, vvc_config, vvc_status, write_address_channel_queue_is_increasing, write_address_channel_executor_is_busy, C_CHANNEL_VVC_LABELS, shared_msg_id_panel, ID_CHANNEL_EXECUTOR, ID_CHANNEL_EXECUTOR_WAIT);
-- Select between a provided msg_id_panel via the vvc_cmd_record from a VVC with a higher hierarchy or the
-- msg_id_panel in this VVC's config. This is to correctly handle the logging when using Hierarchical-VVCs.
v_msg_id_panel := get_msg_id_panel(v_cmd, vvc_config);
-- Normalise address
v_normalised_addr := normalize_and_check(v_cmd.addr, v_normalised_addr, ALLOW_WIDER_NARROWER, "addr", "shared_vvc_cmd.addr", "Function called with to wide address. " & v_cmd.msg);
-- Set vvc transaction info
set_arw_vvc_transaction_info(vvc_transaction_info_trigger, vvc_transaction_info, v_cmd, vvc_config);
-- Start transaction
write_address_channel_write(awaddr_value => std_logic_vector(v_normalised_addr),
msg => format_msg(v_cmd),
clk => clk,
awaddr => axilite_vvc_master_if.write_address_channel.awaddr,
awvalid => axilite_vvc_master_if.write_address_channel.awvalid,
awprot => axilite_vvc_master_if.write_address_channel.awprot,
awready => axilite_vvc_master_if.write_address_channel.awready,
scope => C_CHANNEL_SCOPE,
msg_id_panel => v_msg_id_panel,
config => vvc_config.bfm_config);
-- Set vvc transaction info back to default values
reset_arw_vvc_transaction_info(vvc_transaction_info, v_cmd);
end loop;
end process;
--===============================================================================================
--===============================================================================================
-- write data channel executor
-- - Fetch and execute the write data channel transactions
--===============================================================================================
write_data_channel_executor : process
variable v_cmd : t_vvc_cmd_record;
variable v_msg_id_panel : t_msg_id_panel;
variable v_normalised_data : std_logic_vector(GC_DATA_WIDTH-1 downto 0) := (others => '0');
variable v_cmd_queues_are_empty : boolean;
constant C_CHANNEL_SCOPE : string := C_VVC_NAME & "_W" & "," & to_string(GC_INSTANCE_IDX);
constant C_CHANNEL_VVC_LABELS : t_vvc_labels := assign_vvc_labels(C_CHANNEL_SCOPE, C_VVC_NAME, GC_INSTANCE_IDX, NA);
begin
-- Set the command response queue up to the same settings as the command queue
write_data_channel_queue.set_scope(C_CHANNEL_SCOPE & ":Q");
write_data_channel_queue.set_queue_count_max(vvc_config.cmd_queue_count_max);
write_data_channel_queue.set_queue_count_threshold(vvc_config.cmd_queue_count_threshold);
write_data_channel_queue.set_queue_count_threshold_severity(vvc_config.cmd_queue_count_threshold_severity);
-- Wait until VVC is registered in vvc activity register in the interpreter
wait until entry_num_in_vvc_activity_register >= 0;
-- Set initial value of v_msg_id_panel to msg_id_panel in config
v_msg_id_panel := vvc_config.msg_id_panel;
loop
-- Fetch commands
work.td_vvc_entity_support_pkg.fetch_command_and_prepare_executor(v_cmd, write_data_channel_queue, vvc_config, vvc_status, write_data_channel_queue_is_increasing, write_data_channel_executor_is_busy, C_CHANNEL_VVC_LABELS, shared_msg_id_panel, ID_CHANNEL_EXECUTOR, ID_CHANNEL_EXECUTOR_WAIT);
-- Select between a provided msg_id_panel via the vvc_cmd_record from a VVC with a higher hierarchy or the
-- msg_id_panel in this VVC's config. This is to correctly handle the logging when using Hierarchical-VVCs.
v_msg_id_panel := get_msg_id_panel(v_cmd, vvc_config);
-- Normalise data
v_normalised_data := normalize_and_check(v_cmd.data, v_normalised_data, ALLOW_WIDER_NARROWER, "data", "shared_vvc_cmd.data", "Function called with to wide data. " & v_cmd.msg);
-- Set vvc transaction info
set_w_vvc_transaction_info(vvc_transaction_info_trigger, vvc_transaction_info, v_cmd, vvc_config);
-- Start transaction
write_data_channel_write(wdata_value => v_normalised_data,
wstrb_value => v_cmd.byte_enable((GC_DATA_WIDTH/8-1) downto 0),
msg => format_msg(v_cmd),
clk => clk,
wdata => axilite_vvc_master_if.write_data_channel.wdata,
wstrb => axilite_vvc_master_if.write_data_channel.wstrb,
wvalid => axilite_vvc_master_if.write_data_channel.wvalid,
wready => axilite_vvc_master_if.write_data_channel.wready,
scope => C_CHANNEL_SCOPE,
msg_id_panel => v_msg_id_panel,
config => vvc_config.bfm_config);
-- Set vvc transaction info back to default values
reset_w_vvc_transaction_info(vvc_transaction_info);
end loop;
end process;
--===============================================================================================
--===============================================================================================
-- write response channel executor
-- - Fetch and execute the write response channel transactions
--===============================================================================================
write_response_channel_executor : process
variable v_cmd : t_vvc_cmd_record;
variable v_msg_id_panel : t_msg_id_panel;
variable v_normalised_data : std_logic_vector(GC_DATA_WIDTH-1 downto 0) := (others => '0');
variable v_cmd_queues_are_empty : boolean;
constant C_CHANNEL_SCOPE : string := C_VVC_NAME & "_B" & "," & to_string(GC_INSTANCE_IDX);
constant C_CHANNEL_VVC_LABELS : t_vvc_labels := assign_vvc_labels(C_CHANNEL_SCOPE, C_VVC_NAME, GC_INSTANCE_IDX, NA);
begin
-- Set the command response queue up to the same settings as the command queue
write_response_channel_queue.set_scope(C_CHANNEL_SCOPE & ":Q");
write_response_channel_queue.set_queue_count_max(vvc_config.cmd_queue_count_max);
write_response_channel_queue.set_queue_count_threshold(vvc_config.cmd_queue_count_threshold);
write_response_channel_queue.set_queue_count_threshold_severity(vvc_config.cmd_queue_count_threshold_severity);
-- Wait until VVC is registered in vvc activity register in the interpreter
wait until entry_num_in_vvc_activity_register >= 0;
-- Set initial value of v_msg_id_panel to msg_id_panel in config
v_msg_id_panel := vvc_config.msg_id_panel;
loop
-- Fetch commands
work.td_vvc_entity_support_pkg.fetch_command_and_prepare_executor(v_cmd, write_response_channel_queue, vvc_config, vvc_status, write_response_channel_queue_is_increasing, write_response_channel_executor_is_busy, C_CHANNEL_VVC_LABELS, shared_msg_id_panel, ID_CHANNEL_EXECUTOR, ID_CHANNEL_EXECUTOR_WAIT);
-- Select between a provided msg_id_panel via the vvc_cmd_record from a VVC with a higher hierarchy or the
-- msg_id_panel in this VVC's config. This is to correctly handle the logging when using Hierarchical-VVCs.
v_msg_id_panel := get_msg_id_panel(v_cmd, vvc_config);
-- Set vvc transaction info
set_b_vvc_transaction_info(vvc_transaction_info_trigger, vvc_transaction_info, v_cmd, vvc_config);
-- Receiving a write response
write_response_channel_check(msg => format_msg(v_cmd),
clk => clk,
bready => axilite_vvc_master_if.write_response_channel.bready,
bresp => axilite_vvc_master_if.write_response_channel.bresp,
bvalid => axilite_vvc_master_if.write_response_channel.bvalid,
alert_level => error,
scope => C_CHANNEL_SCOPE,
msg_id_panel => v_msg_id_panel,
config => vvc_config.bfm_config);
last_write_response_channel_idx_executed <= v_cmd.cmd_idx;
-- Set vvc transaction info back to default values
reset_b_vvc_transaction_info(vvc_transaction_info);
reset_vvc_transaction_info(vvc_transaction_info, v_cmd);
end loop;
end process;
--===============================================================================================
--===============================================================================================
-- Command termination handler
-- - Handles the termination request record (sets and resets terminate flag on request)
--===============================================================================================
cmd_terminator : uvvm_vvc_framework.ti_vvc_framework_support_pkg.flag_handler(terminate_current_cmd); -- flag: is_active, set, reset
--===============================================================================================
end behave;
|
mit
|
YingcaiDong/Shunting-Model-Based-Path-Planning-Algorithm-Accelerator-Using-FPGA
|
System Design Source FIle/ipshared/xilinx.com/axi_sg_v4_1/0535f152/hdl/src/vhdl/axi_sg_ftch_cmdsts_if.vhd
|
5
|
13180
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_ftch_cmdsts_if.vhd
-- Description: This entity is the descriptor fetch command and status inteface
-- for the Scatter Gather Engine AXI DataMover.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_sg_v4_1;
use axi_sg_v4_1.axi_sg_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_ftch_cmdsts_if is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Fetch command write interface from fetch sm --
ftch_cmnd_wr : in std_logic ; --
ftch_cmnd_data : in std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
--
-- User Command Interface Ports (AXI Stream) --
s_axis_ftch_cmd_tvalid : out std_logic ; --
s_axis_ftch_cmd_tready : in std_logic ; --
s_axis_ftch_cmd_tdata : out std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
--
-- Read response for detecting slverr, decerr early --
m_axi_sg_rresp : in std_logic_vector(1 downto 0) ; --
m_axi_sg_rvalid : in std_logic ; --
--
-- User Status Interface Ports (AXI Stream) --
m_axis_ftch_sts_tvalid : in std_logic ; --
m_axis_ftch_sts_tready : out std_logic ; --
m_axis_ftch_sts_tdata : in std_logic_vector(7 downto 0) ; --
m_axis_ftch_sts_tkeep : in std_logic_vector(0 downto 0) ; --
--
-- Scatter Gather Fetch Status --
mm2s_err : in std_logic ; --
ftch_done : out std_logic ; --
ftch_error : out std_logic ; --
ftch_interr : out std_logic ; --
ftch_slverr : out std_logic ; --
ftch_decerr : out std_logic ; --
ftch_error_early : out std_logic --
);
end axi_sg_ftch_cmdsts_if;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_ftch_cmdsts_if is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal ftch_slverr_i : std_logic := '0';
signal ftch_decerr_i : std_logic := '0';
signal ftch_interr_i : std_logic := '0';
signal mm2s_error : std_logic := '0';
signal sg_rresp : std_logic_vector(1 downto 0) := (others => '0');
signal sg_rvalid : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
ftch_slverr <= ftch_slverr_i;
ftch_decerr <= ftch_decerr_i;
ftch_interr <= ftch_interr_i;
-------------------------------------------------------------------------------
-- DataMover Command Interface
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- When command by fetch sm, drive descriptor fetch command to data mover.
-- Hold until data mover indicates ready.
-------------------------------------------------------------------------------
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s_axis_ftch_cmd_tvalid <= '0';
-- s_axis_ftch_cmd_tdata <= (others => '0');
elsif(ftch_cmnd_wr = '1')then
s_axis_ftch_cmd_tvalid <= '1';
-- s_axis_ftch_cmd_tdata <= ftch_cmnd_data;
elsif(s_axis_ftch_cmd_tready = '1')then
s_axis_ftch_cmd_tvalid <= '0';
-- s_axis_ftch_cmd_tdata <= (others => '0');
end if;
end if;
end process GEN_DATAMOVER_CMND;
s_axis_ftch_cmd_tdata <= ftch_cmnd_data;
-------------------------------------------------------------------------------
-- DataMover Status Interface
-------------------------------------------------------------------------------
-- Drive ready low during reset to indicate not ready
REG_STS_READY : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
m_axis_ftch_sts_tready <= '0';
else
m_axis_ftch_sts_tready <= '1';
end if;
end if;
end process REG_STS_READY;
-------------------------------------------------------------------------------
-- Log status bits out of data mover.
-------------------------------------------------------------------------------
DATAMOVER_STS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ftch_done <= '0';
ftch_slverr_i <= '0';
ftch_decerr_i <= '0';
ftch_interr_i <= '0';
-- Status valid, therefore capture status
elsif(m_axis_ftch_sts_tvalid = '1')then
ftch_done <= m_axis_ftch_sts_tdata(DATAMOVER_STS_CMDDONE_BIT);
ftch_slverr_i <= m_axis_ftch_sts_tdata(DATAMOVER_STS_SLVERR_BIT);
ftch_decerr_i <= m_axis_ftch_sts_tdata(DATAMOVER_STS_DECERR_BIT);
ftch_interr_i <= m_axis_ftch_sts_tdata(DATAMOVER_STS_INTERR_BIT);
-- Only assert when valid
else
ftch_done <= '0';
ftch_slverr_i <= '0';
ftch_decerr_i <= '0';
ftch_interr_i <= '0';
end if;
end if;
end process DATAMOVER_STS;
-------------------------------------------------------------------------------
-- Early SlvErr and DecErr detections
-- Early detection primarily required for non-queue mode because fetched desc
-- is immediatle fed to DMA controller. Status from SG Datamover arrives
-- too late to stop the insuing transfer on fetch error
-------------------------------------------------------------------------------
REG_MM_RD_SIGNALS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sg_rresp <= (others => '0');
sg_rvalid <= '0';
else
sg_rresp <= m_axi_sg_rresp;
sg_rvalid <= m_axi_sg_rvalid;
end if;
end if;
end process REG_MM_RD_SIGNALS;
REG_ERLY_FTCH_ERROR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ftch_error_early <= '0';
elsif(sg_rvalid = '1' and (sg_rresp = SLVERR_RESP
or sg_rresp = DECERR_RESP))then
ftch_error_early <= '1';
end if;
end if;
end process REG_ERLY_FTCH_ERROR;
-------------------------------------------------------------------------------
-- Register global error from data mover.
-------------------------------------------------------------------------------
mm2s_error <= ftch_slverr_i or ftch_decerr_i or ftch_interr_i;
-- Log errors into a global error output
FETCH_ERROR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ftch_error <= '0';
elsif(mm2s_error = '1')then
ftch_error <= '1';
end if;
end if;
end process FETCH_ERROR_PROCESS;
end implementation;
|
mit
|
YingcaiDong/Shunting-Model-Based-Path-Planning-Algorithm-Accelerator-Using-FPGA
|
System Design Source FIle/bd/system/ip/system_HLS_accel_0_0/hdl/ip/HLS_accel_ap_dadd_3_full_dsp_64.vhd
|
2
|
12938
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.0
-- IP Revision: 7
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_0;
USE floating_point_v7_0.floating_point_v7_0;
ENTITY HLS_accel_ap_dadd_3_full_dsp_64 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
);
END HLS_accel_ap_dadd_3_full_dsp_64;
ARCHITECTURE HLS_accel_ap_dadd_3_full_dsp_64_arch OF HLS_accel_ap_dadd_3_full_dsp_64 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF HLS_accel_ap_dadd_3_full_dsp_64_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_0 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_0;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF HLS_accel_ap_dadd_3_full_dsp_64_arch: ARCHITECTURE IS "floating_point_v7_0,Vivado 2014.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF HLS_accel_ap_dadd_3_full_dsp_64_arch : ARCHITECTURE IS "HLS_accel_ap_dadd_3_full_dsp_64,floating_point_v7_0,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF HLS_accel_ap_dadd_3_full_dsp_64_arch: ARCHITECTURE IS "HLS_accel_ap_dadd_3_full_dsp_64,floating_point_v7_0,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.0,x_ipCoreRevision=7,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=virtex7,C_HAS_ADD=1,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=64,C_A_FRACTION_WIDTH=53,C_B_WIDTH=64,C_B_FRACTION_WIDTH=53,C_C_WIDTH=64,C_C_FRACTION_WIDTH=53,C_RESULT_WIDTH=64,C_RESULT_FRACTION_WIDTH=53,C_COMPARE_OPERATION=8,C_LATENCY=3,C_OPTIMIZATION=1,C_MULT_USAGE=2,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=64,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=64,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=64,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=64,C_RESULT_TUSER_WIDTH=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_0
GENERIC MAP (
C_XDEVICEFAMILY => "virtex7",
C_HAS_ADD => 1,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 64,
C_A_FRACTION_WIDTH => 53,
C_B_WIDTH => 64,
C_B_FRACTION_WIDTH => 53,
C_C_WIDTH => 64,
C_C_FRACTION_WIDTH => 53,
C_RESULT_WIDTH => 64,
C_RESULT_FRACTION_WIDTH => 53,
C_COMPARE_OPERATION => 8,
C_LATENCY => 3,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 2,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 64,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 64,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 64,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 64,
C_RESULT_TUSER_WIDTH => 1
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END HLS_accel_ap_dadd_3_full_dsp_64_arch;
|
mit
|
YingcaiDong/Shunting-Model-Based-Path-Planning-Algorithm-Accelerator-Using-FPGA
|
System Design Source FIle/ipshared/xilinx.com/axi_dma_v7_1/2a047f91/hdl/src/vhdl/axi_dma_s2mm_sts_mngr.vhd
|
3
|
11859
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_s2mm_sts_mngr.vhd
-- Description: This entity mangages 'halt' and 'idle' status for the S2MM
-- channel
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library lib_cdc_v1_0;
library axi_dma_v7_1;
use axi_dma_v7_1.axi_dma_pkg.all;
-------------------------------------------------------------------------------
entity axi_dma_s2mm_sts_mngr is
generic (
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Any one of the 4 clock inputs is not
-- synchronous to the other
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- system state --
s2mm_run_stop : in std_logic ; --
s2mm_ftch_idle : in std_logic ; --
s2mm_updt_idle : in std_logic ; --
s2mm_cmnd_idle : in std_logic ; --
s2mm_sts_idle : in std_logic ; --
--
-- stop and halt control/status --
s2mm_stop : in std_logic ; --
s2mm_halt_cmplt : in std_logic ; --
--
-- system control --
s2mm_all_idle : out std_logic ; --
s2mm_halted_clr : out std_logic ; --
s2mm_halted_set : out std_logic ; --
s2mm_idle_set : out std_logic ; --
s2mm_idle_clr : out std_logic --
);
end axi_dma_s2mm_sts_mngr;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_s2mm_sts_mngr is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
ATTRIBUTE async_reg : STRING;
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal all_is_idle : std_logic := '0';
signal all_is_idle_d1 : std_logic := '0';
signal all_is_idle_re : std_logic := '0';
signal all_is_idle_fe : std_logic := '0';
signal s2mm_datamover_idle : std_logic := '0';
signal s2mm_halt_cmpt_d1_cdc_tig : std_logic := '0';
signal s2mm_halt_cmpt_cdc_d2 : std_logic := '0';
signal s2mm_halt_cmpt_d2 : std_logic := '0';
--ATTRIBUTE async_reg OF s2mm_halt_cmpt_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF s2mm_halt_cmpt_cdc_d2 : SIGNAL IS "true";
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- all is idle when all is idle
all_is_idle <= s2mm_ftch_idle
and s2mm_updt_idle
and s2mm_cmnd_idle
and s2mm_sts_idle;
s2mm_all_idle <= all_is_idle;
-------------------------------------------------------------------------------
-- For data mover halting look at halt complete to determine when halt
-- is done and datamover has completly halted. If datamover not being
-- halted then can ignore flag thus simply flag as idle.
-------------------------------------------------------------------------------
GEN_FOR_ASYNC : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
-- Double register to secondary clock domain. This is sufficient
-- because halt_cmplt will remain asserted until detected in
-- reset module in secondary clock domain.
REG_TO_SECONDARY : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => s2mm_halt_cmplt,
prmry_vect_in => (others => '0'),
scndry_aclk => m_axi_sg_aclk,
scndry_resetn => '0',
scndry_out => s2mm_halt_cmpt_cdc_d2,
scndry_vect_out => open
);
-- REG_TO_SECONDARY : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
---- if(m_axi_sg_aresetn = '0')then
---- s2mm_halt_cmpt_d1_cdc_tig <= '0';
---- s2mm_halt_cmpt_d2 <= '0';
---- else
-- s2mm_halt_cmpt_d1_cdc_tig <= s2mm_halt_cmplt;
-- s2mm_halt_cmpt_cdc_d2 <= s2mm_halt_cmpt_d1_cdc_tig;
---- end if;
-- end if;
-- end process REG_TO_SECONDARY;
s2mm_halt_cmpt_d2 <= s2mm_halt_cmpt_cdc_d2;
end generate GEN_FOR_ASYNC;
GEN_FOR_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
-- No clock crossing required therefore simple pass through
s2mm_halt_cmpt_d2 <= s2mm_halt_cmplt;
end generate GEN_FOR_SYNC;
s2mm_datamover_idle <= '1' when (s2mm_stop = '1' and s2mm_halt_cmpt_d2 = '1')
or (s2mm_stop = '0')
else '0';
-------------------------------------------------------------------------------
-- Set halt bit if run/stop cleared and all processes are idle
-------------------------------------------------------------------------------
HALT_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s2mm_halted_set <= '0';
elsif(s2mm_run_stop = '0' and all_is_idle = '1' and s2mm_datamover_idle = '1')then
s2mm_halted_set <= '1';
else
s2mm_halted_set <= '0';
end if;
end if;
end process HALT_PROCESS;
-------------------------------------------------------------------------------
-- Clear halt bit if run/stop is set and SG engine begins to fetch descriptors
-------------------------------------------------------------------------------
NOT_HALTED_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s2mm_halted_clr <= '0';
elsif(s2mm_run_stop = '1')then
s2mm_halted_clr <= '1';
else
s2mm_halted_clr <= '0';
end if;
end if;
end process NOT_HALTED_PROCESS;
-------------------------------------------------------------------------------
-- Register ALL is Idle to create rising and falling edges on idle flag
-------------------------------------------------------------------------------
IDLE_REG_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
all_is_idle_d1 <= '0';
else
all_is_idle_d1 <= all_is_idle;
end if;
end if;
end process IDLE_REG_PROCESS;
all_is_idle_re <= all_is_idle and not all_is_idle_d1;
all_is_idle_fe <= not all_is_idle and all_is_idle_d1;
-- Set or Clear IDLE bit in DMASR
s2mm_idle_set <= all_is_idle_re and s2mm_run_stop;
s2mm_idle_clr <= all_is_idle_fe;
end implementation;
|
mit
|
YingcaiDong/Shunting-Model-Based-Path-Planning-Algorithm-Accelerator-Using-FPGA
|
System Design Source FIle/ipshared/xilinx.com/axi_datamover_v5_1/3acd8cae/hdl/src/vhdl/axi_datamover_s2mm_realign.vhd
|
6
|
59948
|
-------------------------------------------------------------------------------
-- axi_datamover_s2mm_realign.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_s2mm_realign.vhd
--
-- Description:
-- This file implements the S2MM Data Realignment module. THe S2MM direction is
-- more complex than the MM2S direction since the DRE needs to be upstream from
-- the Write Data Controller. This requires the S2MM DRE to be running 2 to
-- 3 clocks ahead of the Write Data controller to minimize/eliminate xfer
-- bubble insertion.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_datamover_v5_1;
use axi_datamover_v5_1.axi_datamover_fifo;
use axi_datamover_v5_1.axi_datamover_s2mm_dre;
use axi_datamover_v5_1.axi_datamover_s2mm_scatter;
-------------------------------------------------------------------------------
entity axi_datamover_s2mm_realign is
generic (
C_ENABLE_INDET_BTT : Integer range 0 to 1 := 0;
-- Specifies if the IBTT Indeterminate BTT Module is enabled
-- for use (outside of this module)
C_INCLUDE_DRE : Integer range 0 to 1 := 1;
-- Includes/Omits the S2MM DRE
-- 0 = Omit
-- 1 = Include
C_DRE_CNTL_FIFO_DEPTH : Integer range 1 to 32 := 1;
-- Specifies the depth of the internal command queue fifo
C_DRE_ALIGN_WIDTH : Integer range 1 to 3 := 2;
-- Sets the width of the DRE alignment control ports
C_SUPPORT_SCATTER : Integer range 0 to 1 := 1;
-- Includes/Omits the Scatter functionality
-- 0 = omit
-- 1 = include
C_ENABLE_S2MM_TKEEP : integer range 0 to 1 := 1;
C_BTT_USED : Integer range 8 to 23 := 16;
-- Indicates the width of the input command BTT that is actually
-- used
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Sets the width of the Input and Output Stream Data ports
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Sets the width of the input command Tag port
C_STRT_SF_OFFSET_WIDTH : Integer range 1 to 7 := 1 ;
-- Sets the width of the Store and Forward Start offset ports
C_FAMILY : String := "virtex7"
-- specifies the target FPGA familiy
);
port (
-- Clock and Reset Inputs -------------------------------------------
--
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
---------------------------------------------------------------------
-- Write Data Controller or IBTT Indeterminate BTT I/O -------------------------
--
wdc2dre_wready : In std_logic; --
-- Write READY input from WDC or SF --
--
dre2wdc_wvalid : Out std_logic; --
-- Write VALID output to WDC or SF --
--
dre2wdc_wdata : Out std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- Write DATA output to WDC or SF --
--
dre2wdc_wstrb : Out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- Write DATA output to WDC or SF --
--
dre2wdc_wlast : Out std_logic; --
-- Write LAST output to WDC or SF --
--
dre2wdc_eop : Out std_logic; --
-- End of Packet indicator for the Stream input to WDC or SF --
--------------------------------------------------------------------------------
-- Starting offset output for the Store and Forward Modules -------------------
--
dre2sf_strt_offset : Out std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0);--
-- Outputs the starting offset of a transfer. This is used with Store --
-- and Forward Packer/Unpacker logic --
--------------------------------------------------------------------------------
-- AXI Slave Stream In ----------------------------------------------------------
--
s2mm_strm_wready : Out Std_logic; --
-- AXI Stream READY input --
--
s2mm_strm_wvalid : In std_logic; --
-- AXI Stream VALID Output --
--
s2mm_strm_wdata : In std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- AXI Stream data output --
--
s2mm_strm_wstrb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- AXI Stream STRB output --
--
s2mm_strm_wlast : In std_logic; --
-- AXI Stream LAST output --
--------------------------------------------------------------------------------
-- Command Calculator Interface ---------------------------------------------------
--
dre2mstr_cmd_ready : Out std_logic ; --
-- Indication from the DRE that the command is being --
-- accepted from the Command Calculator --
--
mstr2dre_cmd_valid : In std_logic; --
-- The next command valid indication to the DRE --
-- from the Command Calculator --
--
mstr2dre_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2dre_dre_src_align : In std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); --
-- The source (input) alignment for the DRE --
--
mstr2dre_dre_dest_align : In std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); --
-- The destinstion (output) alignment for the DRE --
--
mstr2dre_btt : In std_logic_vector(C_BTT_USED-1 downto 0); --
-- The bytes to transfer value for the input command --
--
mstr2dre_drr : In std_logic; --
-- The starting tranfer of a sequence of transfers --
--
mstr2dre_eof : In std_logic; --
-- The endiing tranfer of a sequence of transfers --
--
mstr2dre_cmd_cmplt : In std_logic; --
-- The last tranfer command of a sequence of transfers --
-- spawned from a single parent command --
--
mstr2dre_calc_error : In std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2dre_strt_offset : In std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0);--
-- Outputs the starting offset of a transfer. This is used with Store --
-- and Forward Packer/Unpacker logic --
-----------------------------------------------------------------------------------
-- Premature TLAST assertion error flag -----------------------------
--
dre2all_tlast_error : Out std_logic; --
-- When asserted, this indicates the DRE detected --
-- a Early/Late TLAST assertion on the incoming data stream. --
---------------------------------------------------------------------
-- DRE Halted Status ------------------------------------------------
--
dre2all_halted : Out std_logic --
-- When asserted, this indicates the DRE has satisfied --
-- all pending transfers queued by the command calculator --
-- and is halted. --
---------------------------------------------------------------------
);
end entity axi_datamover_s2mm_realign;
architecture implementation of axi_datamover_s2mm_realign is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function Declarations --------------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_size_realign_fifo
--
-- Function Description:
-- Assures that the Realigner cmd fifo depth is at least 4 deep else it
-- is equal to the pipe depth.
--
-------------------------------------------------------------------
function funct_size_realign_fifo (pipe_depth : integer) return integer is
Variable temp_fifo_depth : Integer := 4;
begin
If (pipe_depth < 4) Then
temp_fifo_depth := 4;
Else
temp_fifo_depth := pipe_depth;
End if;
Return (temp_fifo_depth);
end function funct_size_realign_fifo;
-- Constant Declarations --------------------------------------------
Constant BYTE_WIDTH : integer := 8; -- bits
Constant STRM_NUM_BYTE_LANES : integer := C_STREAM_DWIDTH/BYTE_WIDTH;
Constant STRM_STRB_WIDTH : integer := STRM_NUM_BYTE_LANES;
Constant SLICE_WIDTH : integer := BYTE_WIDTH+2; -- 8 data bits plus Strobe plus TLAST bit
Constant SLICE_STROBE_INDEX : integer := (BYTE_WIDTH-1)+1;
Constant SLICE_TLAST_INDEX : integer := SLICE_STROBE_INDEX+1;
Constant ZEROED_SLICE : std_logic_vector(SLICE_WIDTH-1 downto 0) := (others => '0');
Constant USE_SYNC_FIFO : integer := 0;
Constant REG_FIFO_PRIM : integer := 0;
Constant BRAM_FIFO_PRIM : integer := 1;
Constant SRL_FIFO_PRIM : integer := 2;
Constant FIFO_PRIM_TYPE : integer := SRL_FIFO_PRIM;
Constant TAG_WIDTH : integer := C_TAG_WIDTH;
Constant SRC_ALIGN_WIDTH : integer := C_DRE_ALIGN_WIDTH;
Constant DEST_ALIGN_WIDTH : integer := C_DRE_ALIGN_WIDTH;
Constant BTT_WIDTH : integer := C_BTT_USED;
Constant DRR_WIDTH : integer := 1;
Constant EOF_WIDTH : integer := 1;
Constant SEQUENTIAL_WIDTH : integer := 1;
Constant CALC_ERR_WIDTH : integer := 1;
Constant SF_OFFSET_WIDTH : integer := C_STRT_SF_OFFSET_WIDTH;
Constant BTT_OF_ZERO : std_logic_vector(BTT_WIDTH-1 downto 0)
:= (others => '0');
Constant DRECTL_FIFO_DEPTH : integer := funct_size_realign_fifo(C_DRE_CNTL_FIFO_DEPTH);
Constant DRECTL_FIFO_WIDTH : Integer := TAG_WIDTH + -- Tag field
SRC_ALIGN_WIDTH + -- Source align field width
DEST_ALIGN_WIDTH + -- Dest align field width
BTT_WIDTH + -- BTT field width
DRR_WIDTH + -- DRE Re-alignment Request Flag Field
EOF_WIDTH + -- EOF flag field
SEQUENTIAL_WIDTH + -- Sequential command flag
CALC_ERR_WIDTH + -- Calc error flag
SF_OFFSET_WIDTH; -- Store and Forward Offset
Constant TAG_STRT_INDEX : integer := 0;
Constant SRC_ALIGN_STRT_INDEX : integer := TAG_STRT_INDEX + TAG_WIDTH;
Constant DEST_ALIGN_STRT_INDEX : integer := SRC_ALIGN_STRT_INDEX + SRC_ALIGN_WIDTH;
Constant BTT_STRT_INDEX : integer := DEST_ALIGN_STRT_INDEX + DEST_ALIGN_WIDTH;
Constant DRR_STRT_INDEX : integer := BTT_STRT_INDEX + BTT_WIDTH;
Constant EOF_STRT_INDEX : integer := DRR_STRT_INDEX + DRR_WIDTH;
Constant SEQUENTIAL_STRT_INDEX : integer := EOF_STRT_INDEX + EOF_WIDTH;
Constant CALC_ERR_STRT_INDEX : integer := SEQUENTIAL_STRT_INDEX+SEQUENTIAL_WIDTH;
Constant SF_OFFSET_STRT_INDEX : integer := CALC_ERR_STRT_INDEX+CALC_ERR_WIDTH;
Constant INCLUDE_DRE : boolean := (C_INCLUDE_DRE = 1 and
C_STREAM_DWIDTH <= 64 and
C_STREAM_DWIDTH >= 16);
Constant OMIT_DRE : boolean := not(INCLUDE_DRE);
-- Type Declarations --------------------------------------------
type TYPE_CMD_CNTL_SM is (
INIT,
LD_DRE_SCATTER_FIRST,
CHK_POP_FIRST ,
LD_DRE_SCATTER_SECOND,
CHK_POP_SECOND,
ERROR_TRAP
);
-- Signal Declarations --------------------------------------------
Signal sig_cmdcntl_sm_state : TYPE_CMD_CNTL_SM := INIT;
Signal sig_cmdcntl_sm_state_ns : TYPE_CMD_CNTL_SM := INIT;
signal sig_sm_ld_dre_cmd_ns : std_logic := '0';
signal sig_sm_ld_dre_cmd : std_logic := '0';
signal sig_sm_ld_scatter_cmd_ns : std_logic := '0';
signal sig_sm_ld_scatter_cmd : std_logic := '0';
signal sig_sm_pop_cmd_fifo_ns : std_logic := '0';
signal sig_sm_pop_cmd_fifo : std_logic := '0';
signal sig_cmd_fifo_data_in : std_logic_vector(DRECTL_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_fifo_data_out : std_logic_vector(DRECTL_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_wr_cmd_valid : std_logic := '0';
signal sig_fifo_wr_cmd_ready : std_logic := '0';
signal sig_curr_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_curr_src_align_reg : std_logic_vector(SRC_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_curr_dest_align_reg : std_logic_vector(DEST_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_curr_btt_reg : std_logic_vector(BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_curr_drr_reg : std_logic := '0';
signal sig_curr_eof_reg : std_logic := '0';
signal sig_curr_cmd_cmplt_reg : std_logic := '0';
signal sig_curr_calc_error_reg : std_logic := '0';
signal sig_dre_align_ready : std_logic := '0';
signal sig_dre_use_autodest : std_logic := '0';
signal sig_dre_src_align : std_logic_vector(SRC_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_dre_dest_align : std_logic_vector(DEST_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_dre_flush : std_logic := '0';
signal sig_dre2wdc_tstrb : std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0) := (others => '0');
signal sig_dre2wdc_tdata : std_logic_vector(C_STREAM_DWIDTH-1 downto 0) := (others => '0');
signal sig_dre2wdc_tlast : std_logic := '0';
signal sig_dre2wdc_tvalid : std_logic := '0';
signal sig_wdc2dre_tready : std_logic := '0';
signal sig_tlast_err0r : std_logic := '0';
signal sig_dre_halted : std_logic := '0';
signal sig_strm2scatter_tstrb : std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0) := (others => '0');
signal sig_strm2scatter_tdata : std_logic_vector(C_STREAM_DWIDTH-1 downto 0) := (others => '0');
signal sig_strm2scatter_tlast : std_logic := '0';
signal sig_strm2scatter_tvalid : std_logic := '0';
signal sig_scatter2strm_tready : std_logic := '0';
signal sig_scatter2dre_tstrb : std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0) := (others => '0');
signal sig_scatter2dre_tdata : std_logic_vector(C_STREAM_DWIDTH-1 downto 0) := (others => '0');
signal sig_scatter2dre_tlast : std_logic := '0';
signal sig_scatter2dre_tvalid : std_logic := '0';
signal sig_dre2scatter_tready : std_logic := '0';
signal sig_scatter2dre_flush : std_logic := '0';
signal sig_scatter2drc_eop : std_logic := '0';
signal sig_scatter2dre_src_align : std_logic_vector(SRC_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_scatter2drc_cmd_ready : std_logic := '0';
signal sig_drc2scatter_push_cmd : std_logic;
signal sig_drc2scatter_btt : std_logic_vector(BTT_WIDTH-1 downto 0);
signal sig_drc2scatter_eof : std_logic;
signal sig_scatter2all_tlast_error : std_logic := '0';
signal sig_need_cmd_flush : std_logic := '0';
signal sig_fifo_rd_cmd_valid : std_logic := '0';
signal sig_curr_strt_offset_reg : std_logic_vector(SF_OFFSET_WIDTH-1 downto 0) := (others => '0');
signal sig_ld_strt_offset : std_logic := '0';
signal sig_output_strt_offset_reg : std_logic_vector(SF_OFFSET_WIDTH-1 downto 0) := (others => '0');
signal sig_dre2sf_strt_offset : std_logic_vector(SF_OFFSET_WIDTH-1 downto 0) := (others => '0');
begin --(architecture implementation)
-------------------------------------------------------------
-- Port connections
-- Input Stream Attachment
s2mm_strm_wready <= sig_scatter2strm_tready ;
sig_strm2scatter_tvalid <= s2mm_strm_wvalid ;
sig_strm2scatter_tdata <= s2mm_strm_wdata ;
sig_strm2scatter_tstrb <= s2mm_strm_wstrb ;
sig_strm2scatter_tlast <= s2mm_strm_wlast ;
-- Write Data Controller Stream Attachment
sig_wdc2dre_tready <= wdc2dre_wready ;
dre2wdc_wvalid <= sig_dre2wdc_tvalid ;
dre2wdc_wdata <= sig_dre2wdc_tdata ;
dre2wdc_wstrb <= sig_dre2wdc_tstrb ;
dre2wdc_wlast <= sig_dre2wdc_tlast ;
-- Status/Error flags
dre2all_tlast_error <= sig_tlast_err0r ;
dre2all_halted <= sig_dre_halted ;
-- Store and Forward Starting Offset Output
dre2sf_strt_offset <= sig_dre2sf_strt_offset ;
-------------------------------------------------------------
-- Internal logic
sig_dre_halted <= sig_dre_align_ready;
-------------------------------------------------------------
-- DRE Handshake signals
sig_dre_src_align <= sig_curr_src_align_reg ;
sig_dre_dest_align <= sig_curr_dest_align_reg;
sig_dre_use_autodest <= '0'; -- not used
sig_dre_flush <= '0'; -- not used
-------------------------------------------------------------------------
-------- Realigner Command FIFO and controls
-------------------------------------------------------------------------
-- Command Calculator Handshake
sig_fifo_wr_cmd_valid <= mstr2dre_cmd_valid ;
dre2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
-- Format the input fifo data word
sig_cmd_fifo_data_in <= mstr2dre_strt_offset &
mstr2dre_calc_error &
mstr2dre_cmd_cmplt &
mstr2dre_eof &
mstr2dre_drr &
mstr2dre_btt &
mstr2dre_dre_dest_align &
mstr2dre_dre_src_align &
mstr2dre_tag ;
-- Rip the output fifo data word
sig_curr_tag_reg <= sig_cmd_fifo_data_out((TAG_STRT_INDEX+TAG_WIDTH)-1 downto TAG_STRT_INDEX);
sig_curr_src_align_reg <= sig_cmd_fifo_data_out((SRC_ALIGN_STRT_INDEX+SRC_ALIGN_WIDTH)-1 downto SRC_ALIGN_STRT_INDEX);
sig_curr_dest_align_reg <= sig_cmd_fifo_data_out((DEST_ALIGN_STRT_INDEX+DEST_ALIGN_WIDTH)-1 downto DEST_ALIGN_STRT_INDEX);
sig_curr_btt_reg <= sig_cmd_fifo_data_out((BTT_STRT_INDEX+BTT_WIDTH)-1 downto BTT_STRT_INDEX);
sig_curr_drr_reg <= sig_cmd_fifo_data_out(DRR_STRT_INDEX);
sig_curr_eof_reg <= sig_cmd_fifo_data_out(EOF_STRT_INDEX);
sig_curr_cmd_cmplt_reg <= sig_cmd_fifo_data_out(SEQUENTIAL_STRT_INDEX);
sig_curr_calc_error_reg <= sig_cmd_fifo_data_out(CALC_ERR_STRT_INDEX);
sig_curr_strt_offset_reg <= sig_cmd_fifo_data_out((SF_OFFSET_STRT_INDEX+SF_OFFSET_WIDTH)-1 downto SF_OFFSET_STRT_INDEX);
------------------------------------------------------------
-- Instance: I_DRE_CNTL_FIFO
--
-- Description:
-- Instance for the DRE Control FIFO
--
------------------------------------------------------------
I_DRE_CNTL_FIFO : entity axi_datamover_v5_1.axi_datamover_fifo
generic map (
C_DWIDTH => DRECTL_FIFO_WIDTH ,
C_DEPTH => DRECTL_FIFO_DEPTH ,
C_IS_ASYNC => USE_SYNC_FIFO ,
C_PRIM_TYPE => FIFO_PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_fifo_wr_cmd_valid ,
fifo_wr_tready => sig_fifo_wr_cmd_ready ,
fifo_wr_tdata => sig_cmd_fifo_data_in ,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_fifo_rd_cmd_valid ,
fifo_rd_tready => sig_sm_pop_cmd_fifo ,
fifo_rd_tdata => sig_cmd_fifo_data_out ,
fifo_rd_empty => open
);
-------------------------------------------------------------------------
-------- DRE and Scatter Command Loader State Machine
-------------------------------------------------------------------------
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CMDCNTL_SM_COMBINATIONAL
--
-- Process Description:
-- Command Controller State Machine combinational implementation
-- The design is based on the premise that for every parent
-- command loaded into the S2MM, the Realigner can be loaded with
-- 1 or 2 commands spawned from it. The first command is used to
-- align ensuing transfers (in MMap space) to a max burst address
-- boundary. Then, if the parent command's BTT value is not satisfied
-- after the first command completes, a second command is generated
-- and loaded in the Realigner for the remaining BTT value. The
-- command complete bit in the Realigner command indicates if the
-- first command the final command or the second command (if needed)
-- is the final command,
-------------------------------------------------------------
CMDCNTL_SM_COMBINATIONAL : process (sig_cmdcntl_sm_state ,
sig_fifo_rd_cmd_valid ,
sig_dre_align_ready ,
sig_scatter2drc_cmd_ready ,
sig_need_cmd_flush ,
sig_curr_cmd_cmplt_reg ,
sig_curr_calc_error_reg
)
begin
-- SM Defaults
sig_cmdcntl_sm_state_ns <= INIT;
sig_sm_ld_dre_cmd_ns <= '0';
sig_sm_ld_scatter_cmd_ns <= '0';
sig_sm_pop_cmd_fifo_ns <= '0';
case sig_cmdcntl_sm_state is
--------------------------------------------
when INIT =>
sig_cmdcntl_sm_state_ns <= LD_DRE_SCATTER_FIRST;
--------------------------------------------
when LD_DRE_SCATTER_FIRST =>
If (sig_fifo_rd_cmd_valid = '1' and
sig_curr_calc_error_reg = '1') Then
sig_cmdcntl_sm_state_ns <= ERROR_TRAP;
elsif (sig_fifo_rd_cmd_valid = '1' and
sig_dre_align_ready = '1' and
sig_scatter2drc_cmd_ready = '1') Then
sig_cmdcntl_sm_state_ns <= CHK_POP_FIRST ;
sig_sm_ld_dre_cmd_ns <= '1';
sig_sm_ld_scatter_cmd_ns <= '1';
sig_sm_pop_cmd_fifo_ns <= '1';
else
sig_cmdcntl_sm_state_ns <= LD_DRE_SCATTER_FIRST;
End if;
--------------------------------------------
when CHK_POP_FIRST =>
If (sig_curr_cmd_cmplt_reg = '1') Then
sig_cmdcntl_sm_state_ns <= LD_DRE_SCATTER_FIRST;
Else
sig_cmdcntl_sm_state_ns <= LD_DRE_SCATTER_SECOND;
End if;
--------------------------------------------
when LD_DRE_SCATTER_SECOND =>
If (sig_fifo_rd_cmd_valid = '1' and
sig_curr_calc_error_reg = '1') Then
sig_cmdcntl_sm_state_ns <= ERROR_TRAP;
elsif (sig_fifo_rd_cmd_valid = '1' and
sig_need_cmd_flush = '1') Then
sig_cmdcntl_sm_state_ns <= CHK_POP_SECOND ;
sig_sm_pop_cmd_fifo_ns <= '1';
elsif (sig_fifo_rd_cmd_valid = '1' and
sig_dre_align_ready = '1' and
sig_scatter2drc_cmd_ready = '1') Then
sig_cmdcntl_sm_state_ns <= CHK_POP_FIRST ;
sig_sm_ld_dre_cmd_ns <= '1';
sig_sm_ld_scatter_cmd_ns <= '1';
sig_sm_pop_cmd_fifo_ns <= '1';
else
sig_cmdcntl_sm_state_ns <= LD_DRE_SCATTER_SECOND;
End if;
--------------------------------------------
when CHK_POP_SECOND =>
sig_cmdcntl_sm_state_ns <= LD_DRE_SCATTER_FIRST ;
--------------------------------------------
when ERROR_TRAP =>
sig_cmdcntl_sm_state_ns <= ERROR_TRAP ;
--------------------------------------------
when others =>
sig_cmdcntl_sm_state_ns <= INIT;
end case;
end process CMDCNTL_SM_COMBINATIONAL;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CMDCNTL_SM_REGISTERED
--
-- Process Description:
-- Command Controller State Machine registered implementation
--
-------------------------------------------------------------
CMDCNTL_SM_REGISTERED : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_cmdcntl_sm_state <= INIT;
sig_sm_ld_dre_cmd <= '0' ;
sig_sm_ld_scatter_cmd <= '0' ;
sig_sm_pop_cmd_fifo <= '0' ;
else
sig_cmdcntl_sm_state <= sig_cmdcntl_sm_state_ns ;
sig_sm_ld_dre_cmd <= sig_sm_ld_dre_cmd_ns ;
sig_sm_ld_scatter_cmd <= sig_sm_ld_scatter_cmd_ns ;
sig_sm_pop_cmd_fifo <= sig_sm_pop_cmd_fifo_ns ;
end if;
end if;
end process CMDCNTL_SM_REGISTERED;
-------------------------------------------------------------------------
-------- DRE Instance and controls
-------------------------------------------------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INCLUDE_DRE
--
-- If Generate Description:
-- Includes the instance for the DRE
--
--
------------------------------------------------------------
GEN_INCLUDE_DRE : if (INCLUDE_DRE) generate
signal lsig_eop_reg : std_logic := '0';
signal lsig_dre_load_beat : std_logic := '0';
signal lsig_dre_tlast_output_beat : std_logic := '0';
signal lsig_set_eop : std_logic := '0';
signal lsig_tlast_err_reg1 : std_logic := '0';
signal lsig_tlast_err_reg2 : std_logic := '0';
signal lsig_push_strt_offset_reg : std_logic_vector(SF_OFFSET_WIDTH-1 downto 0) := (others => '0');
signal lsig_pushreg_full : std_logic := '0';
signal lsig_pushreg_empty : std_logic := '0';
signal lsig_pull_strt_offset_reg : std_logic_vector(SF_OFFSET_WIDTH-1 downto 0) := (others => '0');
signal lsig_pullreg_full : std_logic := '0';
signal lsig_pullreg_empty : std_logic := '0';
signal lsig_pull_new_offset : std_logic := '0';
signal lsig_push_new_offset : std_logic := '0';
begin
------------------------------------------------------------
-- Instance: I_S2MM_DRE_BLOCK
--
-- Description:
-- Instance for the S2MM Data Realignment Engine (DRE)
--
------------------------------------------------------------
I_S2MM_DRE_BLOCK : entity axi_datamover_v5_1.axi_datamover_s2mm_dre
generic map (
C_DWIDTH => C_STREAM_DWIDTH ,
C_ALIGN_WIDTH => C_DRE_ALIGN_WIDTH
)
port map (
-- Clock and Reset
dre_clk => primary_aclk ,
dre_rst => mmap_reset ,
-- Alignment Control (Independent from Stream Input timing)
dre_align_ready => sig_dre_align_ready ,
dre_align_valid => sig_sm_ld_dre_cmd ,
dre_use_autodest => sig_dre_use_autodest ,
dre_src_align => sig_scatter2dre_src_align ,
dre_dest_align => sig_dre_dest_align ,
-- Flush Control (Aligned to input Stream timing)
dre_flush => sig_scatter2dre_flush ,
-- Stream Inputs
dre_in_tstrb => sig_scatter2dre_tstrb ,
dre_in_tdata => sig_scatter2dre_tdata ,
dre_in_tlast => sig_scatter2dre_tlast ,
dre_in_tvalid => sig_scatter2dre_tvalid ,
dre_in_tready => sig_dre2scatter_tready ,
-- Stream Outputs
dre_out_tstrb => sig_dre2wdc_tstrb ,
dre_out_tdata => sig_dre2wdc_tdata ,
dre_out_tlast => sig_dre2wdc_tlast ,
dre_out_tvalid => sig_dre2wdc_tvalid ,
dre_out_tready => sig_wdc2dre_tready
);
lsig_dre_load_beat <= sig_scatter2dre_tvalid and
sig_dre2scatter_tready;
lsig_set_eop <= sig_scatter2drc_eop and
lsig_dre_load_beat ;
lsig_dre_tlast_output_beat <= sig_dre2wdc_tvalid and
sig_wdc2dre_tready and
sig_dre2wdc_tlast;
dre2wdc_eop <= lsig_dre_tlast_output_beat and
lsig_eop_reg;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_EOP_REG
--
-- Process Description:
-- Implements a flop for holding the EOP from the Scatter
-- Engine until the corresponding packet clears out of the DRE.
-- THis is used to transfer the EOP marker to the DRE output
-- stream without the need for the DRE to pass it through.
--
-------------------------------------------------------------
IMP_EOP_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
(lsig_dre_tlast_output_beat = '1' and
lsig_set_eop = '0')) then
lsig_eop_reg <= '0';
elsif (lsig_set_eop = '1') then
lsig_eop_reg <= '1';
else
null; -- Hold current state
end if;
end if;
end process IMP_EOP_REG;
-- Delay TLAST Error by 2 clocks to compensate for DRE minimum
-- delay of 2 clocks for the stream data.
sig_tlast_err0r <= lsig_tlast_err_reg2;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_TLAST_ERR_DELAY
--
-- Process Description:
-- Implements a 2 clock delay to better align the TLAST
-- error detection with the Stream output data to the WDC
-- which has a minimum 2 clock delay through the DRE.
--
-------------------------------------------------------------
IMP_TLAST_ERR_DELAY : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_tlast_err_reg1 <= '0';
lsig_tlast_err_reg2 <= '0';
else
lsig_tlast_err_reg1 <= sig_scatter2all_tlast_error;
lsig_tlast_err_reg2 <= lsig_tlast_err_reg1;
end if;
end if;
end process IMP_TLAST_ERR_DELAY;
-------------------------------------------------------------------------
-- Store and Forward Start Address Offset Registers Logic
-- Push-pull register is used to to time align the starting address
-- offset (ripped from the Realigner command via parsing) to DRE
-- TLAST output timing. The offset output of the pull register must
-- be valid on the first output databeat of the DRE to the Store and
-- Forward module.
-------------------------------------------------------------------------
sig_dre2sf_strt_offset <= lsig_pull_strt_offset_reg;
-- lsig_push_new_offset <= sig_dre_align_ready and
-- sig_gated_dre_align_valid ;
lsig_push_new_offset <= sig_sm_ld_dre_cmd ;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_PUSH_STRT_OFFSET_REG
--
-- Process Description:
-- Implements the input register for holding the starting address
-- offset sent to the external Store and Forward functions.
--
-------------------------------------------------------------
IMP_PUSH_STRT_OFFSET_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_push_strt_offset_reg <= (others => '0');
lsig_pushreg_full <= '0';
lsig_pushreg_empty <= '1';
elsif (lsig_push_new_offset = '1') then
lsig_push_strt_offset_reg <= sig_curr_strt_offset_reg;
lsig_pushreg_full <= '1';
lsig_pushreg_empty <= '0';
elsif (lsig_pull_new_offset = '1') then
lsig_push_strt_offset_reg <= (others => '0');
lsig_pushreg_full <= '0';
lsig_pushreg_empty <= '1';
else
null; -- Hold Current State
end if;
end if;
end process IMP_PUSH_STRT_OFFSET_REG;
-- Pull the next offset (if one exists) into the pull register
-- when the DRE outputs a TLAST. If the pull register is empty
-- and the push register has an offset, then push the new value
-- into the pull register.
lsig_pull_new_offset <= (sig_dre2wdc_tlast and
sig_dre2wdc_tvalid and
sig_wdc2dre_tready) or
(lsig_pushreg_full and
lsig_pullreg_empty);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_PULL_STRT_OFFSET_REG
--
-- Process Description:
-- Implements the output register for holding the starting
-- address offset sent to the Store and Forward modul's upsizer
-- logic.
--
-------------------------------------------------------------
IMP_PULL_STRT_OFFSET_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_pull_strt_offset_reg <= (others => '0');
lsig_pullreg_full <= '0';
lsig_pullreg_empty <= '1';
elsif (lsig_pull_new_offset = '1' and
lsig_pushreg_full = '1') then
lsig_pull_strt_offset_reg <= lsig_push_strt_offset_reg;
lsig_pullreg_full <= '1';
lsig_pullreg_empty <= '0';
elsif (lsig_pull_new_offset = '1' and
lsig_pushreg_full = '0') then
lsig_pull_strt_offset_reg <= (others => '0');
lsig_pullreg_full <= '0';
lsig_pullreg_empty <= '1';
else
null; -- Hold Current State
end if;
end if;
end process IMP_PULL_STRT_OFFSET_REG;
end generate GEN_INCLUDE_DRE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OMIT_DRE
--
-- If Generate Description:
-- Omits the DRE from the Re-aligner.
--
--
------------------------------------------------------------
GEN_OMIT_DRE : if (OMIT_DRE) generate
begin
-- DRE always ready
sig_dre_align_ready <= '1';
-- -- Let the Scatter engine control the Realigner command
-- -- flow.
-- sig_dre_align_ready <= sig_scatter2drc_cmd_ready;
-- Pass through signal connections
sig_dre2wdc_tstrb <= sig_scatter2dre_tstrb ;
sig_dre2wdc_tdata <= sig_scatter2dre_tdata ;
sig_dre2wdc_tlast <= sig_scatter2dre_tlast ;
sig_dre2wdc_tvalid <= sig_scatter2dre_tvalid ;
sig_dre2scatter_tready <= sig_wdc2dre_tready ;
dre2wdc_eop <= sig_scatter2drc_eop ;
-- Just pass TLAST Error through when no DRE is present
sig_tlast_err0r <= sig_scatter2all_tlast_error;
-------------------------------------------------------------------------
-------- Store and Forward Start Address Offset Register Logic
-------------------------------------------------------------------------
sig_dre2sf_strt_offset <= sig_output_strt_offset_reg;
sig_ld_strt_offset <= sig_sm_ld_dre_cmd;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_STRT_OFFSET_OUTPUT
--
-- Process Description:
-- Implements the register for holding the starting address
-- offset sent to the S2MM Store and Forward module's upsizer
-- logic.
--
-------------------------------------------------------------
IMP_STRT_OFFSET_OUTPUT : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_output_strt_offset_reg <= (others => '0');
elsif (sig_ld_strt_offset = '1') then
sig_output_strt_offset_reg <= sig_curr_strt_offset_reg;
else
null; -- Hold Current State
end if;
end if;
end process IMP_STRT_OFFSET_OUTPUT;
end generate GEN_OMIT_DRE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INCLUDE_SCATTER
--
-- If Generate Description:
-- This IfGen implements the Scatter function which is a pre-
-- processor for the S2MM DRE. The scatter function breaks up
-- a continous input stream of data into constituant parts
-- as described by a set of loaded commands that together
-- describe an entire input packet.
--
------------------------------------------------------------
GEN_INCLUDE_SCATTER : if (C_SUPPORT_SCATTER = 1) generate
begin
-- Load the Scatter Engine command when the DRE command
-- is loaded
-- sig_drc2scatter_push_cmd <= sig_dre_align_ready and
-- sig_gated_dre_align_valid;
sig_drc2scatter_push_cmd <= sig_sm_ld_scatter_cmd ;
-- Assign the new Bytes to Transfer (BTT) qualifier for the
-- Scatter Engine
sig_drc2scatter_btt <= sig_curr_btt_reg;
-- Assign the new End of Frame (EOF) qualifier for the
-- Scatter Engine
sig_drc2scatter_eof <= sig_curr_eof_reg;
------------------------------------------------------------
-- Instance: I_S2MM_SCATTER
--
-- Description:
-- Instance for the Scatter Engine. This block breaks up a
-- input stream per commands loaded.
--
------------------------------------------------------------
I_S2MM_SCATTER : entity axi_datamover_v5_1.axi_datamover_s2mm_scatter
generic map (
C_ENABLE_INDET_BTT => C_ENABLE_INDET_BTT ,
C_DRE_ALIGN_WIDTH => C_DRE_ALIGN_WIDTH ,
C_ENABLE_S2MM_TKEEP => C_ENABLE_S2MM_TKEEP ,
C_BTT_USED => BTT_WIDTH ,
C_STREAM_DWIDTH => C_STREAM_DWIDTH ,
C_FAMILY => C_FAMILY
)
port map (
-- Clock input & Reset input
primary_aclk => primary_aclk ,
mmap_reset => mmap_reset ,
-- DRE Realign Controller I/O ----------------------------
scatter2drc_cmd_ready => sig_scatter2drc_cmd_ready ,
drc2scatter_push_cmd => sig_drc2scatter_push_cmd ,
drc2scatter_btt => sig_drc2scatter_btt ,
drc2scatter_eof => sig_drc2scatter_eof ,
-- DRE Source Alignment -----------------------------------
scatter2drc_src_align => sig_scatter2dre_src_align ,
-- AXI Slave Stream In -----------------------------------
s2mm_strm_tready => sig_scatter2strm_tready ,
s2mm_strm_tvalid => sig_strm2scatter_tvalid ,
s2mm_strm_tdata => sig_strm2scatter_tdata ,
s2mm_strm_tstrb => sig_strm2scatter_tstrb ,
s2mm_strm_tlast => sig_strm2scatter_tlast ,
-- Stream Out to S2MM DRE ---------------------------------
drc2scatter_tready => sig_dre2scatter_tready ,
scatter2drc_tvalid => sig_scatter2dre_tvalid ,
scatter2drc_tdata => sig_scatter2dre_tdata ,
scatter2drc_tstrb => sig_scatter2dre_tstrb ,
scatter2drc_tlast => sig_scatter2dre_tlast ,
scatter2drc_flush => sig_scatter2dre_flush ,
scatter2drc_eop => sig_scatter2drc_eop ,
-- Premature TLAST assertion error flag
scatter2drc_tlast_error => sig_scatter2all_tlast_error
);
end generate GEN_INCLUDE_SCATTER;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OMIT_SCATTER
--
-- If Generate Description:
-- This IfGen omits the Scatter pre-processor.
--
--
------------------------------------------------------------
GEN_OMIT_SCATTER : if (C_SUPPORT_SCATTER = 0) generate
begin
-- Just housekeep the signaling
sig_scatter2drc_cmd_ready <= '1' ;
sig_scatter2drc_eop <= sig_strm2scatter_tlast ;
sig_scatter2dre_src_align <= sig_dre_src_align ;
sig_scatter2all_tlast_error <= '0' ;
sig_scatter2dre_flush <= sig_dre_flush ;
sig_scatter2dre_tstrb <= sig_strm2scatter_tstrb ;
sig_scatter2dre_tdata <= sig_strm2scatter_tdata ;
sig_scatter2dre_tlast <= sig_strm2scatter_tlast ;
sig_scatter2dre_tvalid <= sig_strm2scatter_tvalid ;
sig_scatter2strm_tready <= sig_dre2scatter_tready ;
end generate GEN_OMIT_SCATTER;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OMIT_INDET_BTT
--
-- If Generate Description:
-- Omit and special logic for Indeterminate BTT support.
--
--
------------------------------------------------------------
GEN_OMIT_INDET_BTT : if (C_ENABLE_INDET_BTT = 0) generate
begin
sig_need_cmd_flush <= '0' ; -- not needed without Indeterminate BTT
end generate GEN_OMIT_INDET_BTT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ENABLE_INDET_BTT
--
-- If Generate Description:
-- Include logic for the case when Indeterminate BTT is
-- included as part of the S2MM. In this mode, the actual
-- length of input stream packets is not known when the S2MM
-- is loaded with a transfer command.
--
------------------------------------------------------------
GEN_ENABLE_INDET_BTT : if (C_ENABLE_INDET_BTT = 1) generate
signal lsig_clr_cmd_flush : std_logic := '0';
signal lsig_set_cmd_flush : std_logic := '0';
signal lsig_cmd_set_fetch_pause : std_logic := '0';
signal lsig_cmd_clr_fetch_pause : std_logic := '0';
signal lsig_cmd_fetch_pause : std_logic := '0';
begin
lsig_cmd_set_fetch_pause <= sig_drc2scatter_push_cmd and
not(sig_curr_cmd_cmplt_reg) and
not(sig_need_cmd_flush);
lsig_cmd_clr_fetch_pause <= sig_scatter2dre_tvalid and
sig_dre2scatter_tready and
sig_scatter2dre_tlast;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CMD_FETCH_PAUSE
--
-- Process Description:
-- Implements the flop for the flag that causes the command
-- queue manager to pause fetching the next command if the
-- current command does not have the command complete bit set.
-- The pause remains set until the associated TLAST for the
-- command is output from the Scatter Engine. If the Tlast is
-- also accompanied by a EOP and the pause is set, then the
-- ensuing command (which will have the cmd cmplt bit set) must
-- be flushed from the queue and not loaded into the Scatter
-- Engine or DRE, This is normally associated with indeterminate
-- packets that are actually shorter than the intial align to
-- max burst child command sent to the Realigner, The next loaded
-- child command is to finish the remainder of the indeterminate
-- packet up to the full BTT value in the original parent command.
-- This child command becomes stranded in the Realigner command fifo
-- and has to be flushed.
--
-------------------------------------------------------------
IMP_CMD_FETCH_PAUSE : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
lsig_cmd_clr_fetch_pause = '1') then
lsig_cmd_fetch_pause <= '0';
elsif (lsig_cmd_set_fetch_pause = '1') then
lsig_cmd_fetch_pause <= '1';
else
null; -- Hold current state
end if;
end if;
end process IMP_CMD_FETCH_PAUSE;
-- Clear the flush needed flag when the command with the command
-- complete marker is popped off of the command queue.
lsig_clr_cmd_flush <= sig_need_cmd_flush and
sig_sm_pop_cmd_fifo;
-- The command queue has to be flushed if the stream EOP marker
-- is transfered out of the Scatter Engine when the corresponding
-- command being executed does not have the command complete
-- marker set.
lsig_set_cmd_flush <= lsig_cmd_fetch_pause and
sig_scatter2dre_tvalid and
sig_dre2scatter_tready and
sig_scatter2drc_eop;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CMD_FLUSH_FLOP
--
-- Process Description:
-- Implements the flop for holding the command flush flag.
-- This is only needed in Indeterminate BTT mode.
--
-------------------------------------------------------------
IMP_CMD_FLUSH_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
lsig_clr_cmd_flush = '1') then
sig_need_cmd_flush <= '0';
elsif (lsig_set_cmd_flush = '1') then
sig_need_cmd_flush <= '1';
else
null; -- Hold current state
end if;
end if;
end process IMP_CMD_FLUSH_FLOP;
end generate GEN_ENABLE_INDET_BTT;
end implementation;
|
mit
|
UVVM/UVVM_All
|
uvvm_util/src/func_cov_pkg.vhd
|
1
|
167571
|
--================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
-- Inspired by similar functionality in SystemVerilog and OSVVM.
----------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
use work.types_pkg.all;
use work.adaptations_pkg.all;
use work.string_methods_pkg.all;
use work.global_signals_and_shared_variables_pkg.all;
use work.methods_pkg.all;
use work.rand_pkg.all;
package func_cov_pkg is
constant C_MAX_NUM_CROSS_BINS : positive := 16;
------------------------------------------------------------
-- Types
------------------------------------------------------------
type t_report_verbosity is (NON_VERBOSE, VERBOSE, HOLES_ONLY);
type t_rand_weight_visibility is (SHOW_RAND_WEIGHT, HIDE_RAND_WEIGHT);
type t_coverage_type is (BINS, HITS, BINS_AND_HITS);
type t_overall_coverage_type is (COVPTS, BINS, HITS);
type t_rand_sample_cov is (SAMPLE_COV, NO_SAMPLE_COV);
type t_cov_bin_type is (VAL, VAL_IGNORE, VAL_ILLEGAL, RAN, RAN_IGNORE, RAN_ILLEGAL, TRN, TRN_IGNORE, TRN_ILLEGAL);
type t_new_bin is record
contains : t_cov_bin_type;
values : integer_vector(0 to C_FC_MAX_NUM_BIN_VALUES-1);
num_values : natural range 0 to C_FC_MAX_NUM_BIN_VALUES;
end record;
type t_new_bin_vector is array (natural range <>) of t_new_bin;
type t_new_cov_bin is record
bin_vector : t_new_bin_vector(0 to C_FC_MAX_NUM_NEW_BINS-1);
num_bins : natural range 0 to C_FC_MAX_NUM_NEW_BINS;
proc_call : string(1 to C_FC_MAX_PROC_CALL_LENGTH);
end record;
type t_new_bin_array is array (natural range <>) of t_new_cov_bin;
constant C_EMPTY_NEW_BIN_ARRAY : t_new_bin_array(0 to 0) := (0 => ((0 to C_FC_MAX_NUM_NEW_BINS-1 => (VAL, (others => 0), 0)),
0,
(1 to C_FC_MAX_PROC_CALL_LENGTH => NUL)));
type t_bin is record
contains : t_cov_bin_type;
values : integer_vector(0 to C_FC_MAX_NUM_BIN_VALUES-1);
num_values : natural range 0 to C_FC_MAX_NUM_BIN_VALUES;
end record;
type t_bin_vector is array (natural range <>) of t_bin;
type t_cov_bin is record
cross_bins : t_bin_vector(0 to C_MAX_NUM_CROSS_BINS-1);
hits : natural;
min_hits : natural;
rand_weight : integer;
transition_mask : std_logic_vector(C_FC_MAX_NUM_BIN_VALUES-1 downto 0);
name : string(1 to C_FC_MAX_NAME_LENGTH);
end record;
type t_cov_bin_vector is array (natural range <>) of t_cov_bin;
type t_cov_bin_vector_ptr is access t_cov_bin_vector;
------------------------------------------------------------
-- Bin functions
------------------------------------------------------------
-- Creates a bin for a single value
impure function bin(
constant value : integer)
return t_new_bin_array;
-- Creates a bin for multiple values
impure function bin(
constant set_of_values : integer_vector)
return t_new_bin_array;
-- Creates a bin for a range of values. Several bins can be created by dividing the range into num_bins.
-- If num_bins is 0 then a bin is created for each value.
impure function bin_range(
constant min_value : integer;
constant max_value : integer;
constant num_bins : natural := 1)
return t_new_bin_array;
-- Creates a bin for a vector's range. Several bins can be created by dividing the range into num_bins.
-- If num_bins is 0 then a bin is created for each value.
impure function bin_vector(
constant vector : std_logic_vector;
constant num_bins : natural := 1)
return t_new_bin_array;
-- Creates a bin for a transition of values
impure function bin_transition(
constant set_of_values : integer_vector)
return t_new_bin_array;
-- Creates an ignore bin for a single value
impure function ignore_bin(
constant value : integer)
return t_new_bin_array;
-- Creates an ignore bin for a range of values
impure function ignore_bin_range(
constant min_value : integer;
constant max_value : integer)
return t_new_bin_array;
-- Creates an ignore bin for a transition of values
impure function ignore_bin_transition(
constant set_of_values : integer_vector)
return t_new_bin_array;
-- Creates an illegal bin for a single value
impure function illegal_bin(
constant value : integer)
return t_new_bin_array;
-- Creates an illegal bin for a range of values
impure function illegal_bin_range(
constant min_value : integer;
constant max_value : integer)
return t_new_bin_array;
-- Creates an illegal bin for a transition of values
impure function illegal_bin_transition(
constant set_of_values : integer_vector)
return t_new_bin_array;
------------------------------------------------------------
-- Overall coverage
------------------------------------------------------------
procedure fc_set_covpts_coverage_goal(
constant percentage : in positive range 1 to 100;
constant scope : in string := C_TB_SCOPE_DEFAULT;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel);
impure function fc_get_covpts_coverage_goal(
constant VOID : t_void)
return positive;
impure function fc_get_overall_coverage(
constant coverage_type : t_overall_coverage_type)
return real;
impure function fc_overall_coverage_completed(
constant VOID : t_void)
return boolean;
procedure fc_report_overall_coverage(
constant VOID : in t_void);
procedure fc_report_overall_coverage(
constant verbosity : in t_report_verbosity;
constant file_name : in string := "";
constant open_mode : in file_open_kind := append_mode;
constant scope : in string := C_TB_SCOPE_DEFAULT);
------------------------------------------------------------
-- Protected type
------------------------------------------------------------
type t_coverpoint is protected
------------------------------------------------------------
-- Configuration
------------------------------------------------------------
procedure set_name(
constant name : in string);
impure function get_name(
constant VOID : t_void)
return string;
procedure set_scope(
constant scope : in string);
impure function get_scope(
constant VOID : t_void)
return string;
procedure set_overall_coverage_weight(
constant weight : in natural;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel);
impure function get_overall_coverage_weight(
constant VOID : t_void)
return natural;
procedure set_bins_coverage_goal(
constant percentage : in positive range 1 to 100;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel);
impure function get_bins_coverage_goal(
constant VOID : t_void)
return positive;
procedure set_hits_coverage_goal(
constant percentage : in positive;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel);
impure function get_hits_coverage_goal(
constant VOID : t_void)
return positive;
procedure set_illegal_bin_alert_level(
constant alert_level : in t_alert_level;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel);
impure function get_illegal_bin_alert_level(
constant VOID : t_void)
return t_alert_level;
procedure set_bin_overlap_alert_level(
constant alert_level : in t_alert_level;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel);
impure function get_bin_overlap_alert_level(
constant VOID : t_void)
return t_alert_level;
procedure write_coverage_db(
constant file_name : in string;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel);
procedure load_coverage_db(
constant file_name : in string;
constant report_verbosity : in t_report_verbosity := HOLES_ONLY;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel);
procedure clear_coverage(
constant VOID : in t_void);
procedure clear_coverage(
constant msg_id_panel : in t_msg_id_panel);
procedure set_num_allocated_bins(
constant value : in positive;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel);
procedure set_num_allocated_bins_increment(
constant value : in positive);
procedure delete_coverpoint(
constant VOID : in t_void);
procedure delete_coverpoint(
constant msg_id_panel : in t_msg_id_panel);
-- Returns the number of bins crossed in the coverpoint
impure function get_num_bins_crossed(
constant VOID : t_void)
return integer;
-- Returns the number of valid bins in the coverpoint
impure function get_num_valid_bins(
constant VOID : t_void)
return natural;
-- Returns the number of illegal and ignore bins in the coverpoint
impure function get_num_invalid_bins(
constant VOID : t_void)
return natural;
-- Returns a valid bin in the coverpoint
impure function get_valid_bin(
constant bin_idx : natural)
return t_cov_bin;
-- Returns an invalid bin in the coverpoint
impure function get_invalid_bin(
constant bin_idx : natural)
return t_cov_bin;
-- Returns a vector with the valid bins in the coverpoint
impure function get_valid_bins(
constant VOID : t_void)
return t_cov_bin_vector;
-- Returns a vector with the illegal and ignore bins in the coverpoint
impure function get_invalid_bins(
constant VOID : t_void)
return t_cov_bin_vector;
-- Returns a string with all the bins, including illegal and ignore, in the coverpoint
impure function get_all_bins_string(
constant VOID : t_void)
return string;
------------------------------------------------------------
-- Add bins
------------------------------------------------------------
procedure add_bins(
constant bin : in t_new_bin_array;
constant min_hits : in positive;
constant rand_weight : in natural;
constant bin_name : in string := "";
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant ext_proc_call : in string := "");
procedure add_bins(
constant bin : in t_new_bin_array;
constant min_hits : in positive;
constant bin_name : in string := "";
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel);
procedure add_bins(
constant bin : in t_new_bin_array;
constant bin_name : in string := "";
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel);
------------------------------------------------------------
-- Add cross (2 bins)
------------------------------------------------------------
procedure add_cross(
constant bin1 : in t_new_bin_array;
constant bin2 : in t_new_bin_array;
constant min_hits : in positive;
constant rand_weight : in natural;
constant bin_name : in string := "";
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant ext_proc_call : in string := "");
procedure add_cross(
constant bin1 : in t_new_bin_array;
constant bin2 : in t_new_bin_array;
constant min_hits : in positive;
constant bin_name : in string := "";
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel);
procedure add_cross(
constant bin1 : in t_new_bin_array;
constant bin2 : in t_new_bin_array;
constant bin_name : in string := "";
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel);
------------------------------------------------------------
-- Add cross (3 bins)
------------------------------------------------------------
procedure add_cross(
constant bin1 : in t_new_bin_array;
constant bin2 : in t_new_bin_array;
constant bin3 : in t_new_bin_array;
constant min_hits : in positive;
constant rand_weight : in natural;
constant bin_name : in string := "";
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant ext_proc_call : in string := "");
procedure add_cross(
constant bin1 : in t_new_bin_array;
constant bin2 : in t_new_bin_array;
constant bin3 : in t_new_bin_array;
constant min_hits : in positive;
constant bin_name : in string := "";
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel);
procedure add_cross(
constant bin1 : in t_new_bin_array;
constant bin2 : in t_new_bin_array;
constant bin3 : in t_new_bin_array;
constant bin_name : in string := "";
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel);
------------------------------------------------------------
-- Add cross (4 bins)
------------------------------------------------------------
procedure add_cross(
constant bin1 : in t_new_bin_array;
constant bin2 : in t_new_bin_array;
constant bin3 : in t_new_bin_array;
constant bin4 : in t_new_bin_array;
constant min_hits : in positive;
constant rand_weight : in natural;
constant bin_name : in string := "";
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant ext_proc_call : in string := "");
procedure add_cross(
constant bin1 : in t_new_bin_array;
constant bin2 : in t_new_bin_array;
constant bin3 : in t_new_bin_array;
constant bin4 : in t_new_bin_array;
constant min_hits : in positive;
constant bin_name : in string := "";
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel);
procedure add_cross(
constant bin1 : in t_new_bin_array;
constant bin2 : in t_new_bin_array;
constant bin3 : in t_new_bin_array;
constant bin4 : in t_new_bin_array;
constant bin_name : in string := "";
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel);
------------------------------------------------------------
-- Add cross (5 bins)
------------------------------------------------------------
procedure add_cross(
constant bin1 : in t_new_bin_array;
constant bin2 : in t_new_bin_array;
constant bin3 : in t_new_bin_array;
constant bin4 : in t_new_bin_array;
constant bin5 : in t_new_bin_array;
constant min_hits : in positive;
constant rand_weight : in natural;
constant bin_name : in string := "";
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant ext_proc_call : in string := "");
procedure add_cross(
constant bin1 : in t_new_bin_array;
constant bin2 : in t_new_bin_array;
constant bin3 : in t_new_bin_array;
constant bin4 : in t_new_bin_array;
constant bin5 : in t_new_bin_array;
constant min_hits : in positive;
constant bin_name : in string := "";
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel);
procedure add_cross(
constant bin1 : in t_new_bin_array;
constant bin2 : in t_new_bin_array;
constant bin3 : in t_new_bin_array;
constant bin4 : in t_new_bin_array;
constant bin5 : in t_new_bin_array;
constant bin_name : in string := "";
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel);
-- TODO: max 16 dimensions
------------------------------------------------------------
-- Add cross (2 coverpoints)
------------------------------------------------------------
procedure add_cross(
variable coverpoint1 : inout t_coverpoint;
variable coverpoint2 : inout t_coverpoint;
constant min_hits : in positive;
constant rand_weight : in natural;
constant bin_name : in string := "";
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant ext_proc_call : in string := "");
procedure add_cross(
variable coverpoint1 : inout t_coverpoint;
variable coverpoint2 : inout t_coverpoint;
constant min_hits : in positive;
constant bin_name : in string := "";
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel);
procedure add_cross(
variable coverpoint1 : inout t_coverpoint;
variable coverpoint2 : inout t_coverpoint;
constant bin_name : in string := "";
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel);
------------------------------------------------------------
-- Add cross (3 coverpoints)
------------------------------------------------------------
procedure add_cross(
variable coverpoint1 : inout t_coverpoint;
variable coverpoint2 : inout t_coverpoint;
variable coverpoint3 : inout t_coverpoint;
constant min_hits : in positive;
constant rand_weight : in natural;
constant bin_name : in string := "";
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant ext_proc_call : in string := "");
procedure add_cross(
variable coverpoint1 : inout t_coverpoint;
variable coverpoint2 : inout t_coverpoint;
variable coverpoint3 : inout t_coverpoint;
constant min_hits : in positive;
constant bin_name : in string := "";
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel);
procedure add_cross(
variable coverpoint1 : inout t_coverpoint;
variable coverpoint2 : inout t_coverpoint;
variable coverpoint3 : inout t_coverpoint;
constant bin_name : in string := "";
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel);
------------------------------------------------------------
-- Add cross (4 coverpoints)
------------------------------------------------------------
procedure add_cross(
variable coverpoint1 : inout t_coverpoint;
variable coverpoint2 : inout t_coverpoint;
variable coverpoint3 : inout t_coverpoint;
variable coverpoint4 : inout t_coverpoint;
constant min_hits : in positive;
constant rand_weight : in natural;
constant bin_name : in string := "";
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant ext_proc_call : in string := "");
procedure add_cross(
variable coverpoint1 : inout t_coverpoint;
variable coverpoint2 : inout t_coverpoint;
variable coverpoint3 : inout t_coverpoint;
variable coverpoint4 : inout t_coverpoint;
constant min_hits : in positive;
constant bin_name : in string := "";
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel);
procedure add_cross(
variable coverpoint1 : inout t_coverpoint;
variable coverpoint2 : inout t_coverpoint;
variable coverpoint3 : inout t_coverpoint;
variable coverpoint4 : inout t_coverpoint;
constant bin_name : in string := "";
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel);
------------------------------------------------------------
-- Add cross (5 coverpoints)
------------------------------------------------------------
procedure add_cross(
variable coverpoint1 : inout t_coverpoint;
variable coverpoint2 : inout t_coverpoint;
variable coverpoint3 : inout t_coverpoint;
variable coverpoint4 : inout t_coverpoint;
variable coverpoint5 : inout t_coverpoint;
constant min_hits : in positive;
constant rand_weight : in natural;
constant bin_name : in string := "";
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant ext_proc_call : in string := "");
procedure add_cross(
variable coverpoint1 : inout t_coverpoint;
variable coverpoint2 : inout t_coverpoint;
variable coverpoint3 : inout t_coverpoint;
variable coverpoint4 : inout t_coverpoint;
variable coverpoint5 : inout t_coverpoint;
constant min_hits : in positive;
constant bin_name : in string := "";
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel);
procedure add_cross(
variable coverpoint1 : inout t_coverpoint;
variable coverpoint2 : inout t_coverpoint;
variable coverpoint3 : inout t_coverpoint;
variable coverpoint4 : inout t_coverpoint;
variable coverpoint5 : inout t_coverpoint;
constant bin_name : in string := "";
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel);
------------------------------------------------------------
-- Coverage
------------------------------------------------------------
impure function is_defined(
constant VOID : t_void)
return boolean;
procedure sample_coverage(
constant value : in integer;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel);
procedure sample_coverage(
constant values : in integer_vector;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant ext_proc_call : in string := "");
impure function get_coverage(
constant coverage_type : t_coverage_type;
constant percentage_of_goal : boolean := false)
return real;
impure function coverage_completed(
constant coverage_type : t_coverage_type)
return boolean;
procedure report_coverage(
constant VOID : in t_void);
procedure report_coverage(
constant verbosity : in t_report_verbosity;
constant file_name : in string := "";
constant open_mode : in file_open_kind := append_mode;
constant rand_weight_col : in t_rand_weight_visibility := HIDE_RAND_WEIGHT);
procedure report_config(
constant VOID : in t_void);
procedure report_config(
constant file_name : in string;
constant open_mode : in file_open_kind := append_mode);
------------------------------------------------------------
-- Optimized Randomization
------------------------------------------------------------
impure function rand(
constant sampling : t_rand_sample_cov;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel)
return integer;
impure function rand(
constant sampling : t_rand_sample_cov;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant ext_proc_call : string := "")
return integer_vector;
procedure set_rand_seeds(
constant seed1 : in positive;
constant seed2 : in positive);
procedure set_rand_seeds(
constant seeds : in t_positive_vector(0 to 1));
procedure get_rand_seeds(
variable seed1 : out positive;
variable seed2 : out positive);
impure function get_rand_seeds(
constant VOID : t_void)
return t_positive_vector;
end protected t_coverpoint;
end package func_cov_pkg;
package body func_cov_pkg is
-- Generates the correct procedure call to be used for logging or alerts
procedure create_proc_call(
constant proc_call : in string;
constant ext_proc_call : in string;
variable new_proc_call : inout line) is
begin
-- Called directly from sequencer/VVC
if ext_proc_call = "" then
write(new_proc_call, proc_call);
-- Called from another procedure
else
write(new_proc_call, ext_proc_call);
end if;
end procedure;
-- Creates a bin with a single value
impure function create_bin_single(
constant contains : t_cov_bin_type;
constant value : integer;
constant proc_call : string)
return t_new_bin_array is
variable v_ret : t_new_bin_array(0 to 0);
begin
v_ret(0).bin_vector(0).contains := contains;
v_ret(0).bin_vector(0).values(0) := value;
v_ret(0).bin_vector(0).num_values := 1;
v_ret(0).num_bins := 1;
if proc_call'length > C_FC_MAX_PROC_CALL_LENGTH then
v_ret(0).proc_call := proc_call(1 to C_FC_MAX_PROC_CALL_LENGTH-3) & "...";
else
v_ret(0).proc_call(1 to proc_call'length) := proc_call;
end if;
return v_ret;
end function;
-- Creates a bin with multiple values
impure function create_bin_multiple(
constant contains : t_cov_bin_type;
constant set_of_values : integer_vector;
constant proc_call : string)
return t_new_bin_array is
variable v_ret : t_new_bin_array(0 to 0);
begin
v_ret(0).bin_vector(0).contains := contains;
if set_of_values'length <= C_FC_MAX_NUM_BIN_VALUES then
v_ret(0).bin_vector(0).values(0 to set_of_values'length-1) := set_of_values;
v_ret(0).bin_vector(0).num_values := set_of_values'length;
else
v_ret(0).bin_vector(0).values := set_of_values(0 to C_FC_MAX_NUM_BIN_VALUES-1);
v_ret(0).bin_vector(0).num_values := C_FC_MAX_NUM_BIN_VALUES;
alert(TB_WARNING, proc_call & "=> Number of values (" & to_string(set_of_values'length) &
") exceeds C_FC_MAX_NUM_BIN_VALUES.\n Increase C_FC_MAX_NUM_BIN_VALUES in adaptations package.", C_TB_SCOPE_DEFAULT);
end if;
v_ret(0).num_bins := 1;
if proc_call'length > C_FC_MAX_PROC_CALL_LENGTH then
v_ret(0).proc_call := proc_call(1 to C_FC_MAX_PROC_CALL_LENGTH-3) & "...";
else
v_ret(0).proc_call(1 to proc_call'length) := proc_call;
end if;
return v_ret;
end function;
-- Creates a bin or bins from a range of values. If num_bins is 0 then a bin is created for each value.
impure function create_bin_range(
constant contains : t_cov_bin_type;
constant min_value : integer;
constant max_value : integer;
constant num_bins : natural;
constant proc_call : string)
return t_new_bin_array is
constant C_RANGE_WIDTH : integer := abs(max_value - min_value) + 1;
variable v_div_range : integer;
variable v_div_residue : integer := 0;
variable v_div_residue_min : integer := 0;
variable v_div_residue_max : integer := 0;
variable v_num_bins : integer := 0;
variable v_ret : t_new_bin_array(0 to 0);
begin
check_value(contains = RAN or contains = RAN_IGNORE or contains = RAN_ILLEGAL, TB_FAILURE, "This function should only be used with range types.",
C_TB_SCOPE_DEFAULT, ID_NEVER, caller_name => "create_bin_range()");
if min_value <= max_value then
-- Create a bin for each value in the range (when num_bins is not defined or range is smaller than the number of bins)
if num_bins = 0 or C_RANGE_WIDTH <= num_bins then
if C_RANGE_WIDTH > C_FC_MAX_NUM_NEW_BINS then
alert(TB_ERROR, proc_call & "=> Failed. Number of bins (" & to_string(C_RANGE_WIDTH) &
") added in a single procedure call exceeds C_FC_MAX_NUM_NEW_BINS.\n Increase C_FC_MAX_NUM_NEW_BINS in adaptations package.", C_TB_SCOPE_DEFAULT);
return C_EMPTY_NEW_BIN_ARRAY;
end if;
for i in min_value to max_value loop
v_ret(0).bin_vector(i-min_value).contains := VAL when contains = RAN else
VAL_IGNORE when contains = RAN_IGNORE else
VAL_ILLEGAL when contains = RAN_ILLEGAL;
v_ret(0).bin_vector(i-min_value).values(0) := i;
v_ret(0).bin_vector(i-min_value).num_values := 1;
end loop;
v_num_bins := C_RANGE_WIDTH;
-- Create several bins by diving the range
else
if num_bins > C_FC_MAX_NUM_NEW_BINS then
alert(TB_ERROR, proc_call & "=> Failed. Number of bins (" & to_string(num_bins) &
") added in a single procedure call exceeds C_FC_MAX_NUM_NEW_BINS.\n Increase C_FC_MAX_NUM_NEW_BINS in adaptations package.", C_TB_SCOPE_DEFAULT);
return C_EMPTY_NEW_BIN_ARRAY;
end if;
v_div_residue := C_RANGE_WIDTH mod num_bins;
v_div_range := C_RANGE_WIDTH / num_bins;
v_num_bins := num_bins;
for i in 0 to v_num_bins-1 loop
-- Add the residue values to the last bins
if v_div_residue /= 0 and i = v_num_bins-v_div_residue then
v_div_residue_max := v_div_residue_max + 1;
elsif v_div_residue /= 0 and i > v_num_bins-v_div_residue then
v_div_residue_min := v_div_residue_min + 1;
v_div_residue_max := v_div_residue_max + 1;
end if;
v_ret(0).bin_vector(i).contains := contains;
v_ret(0).bin_vector(i).values(0) := min_value + v_div_range*i + v_div_residue_min;
v_ret(0).bin_vector(i).values(1) := min_value + v_div_range*(i+1)-1 + v_div_residue_max;
v_ret(0).bin_vector(i).num_values := 2;
end loop;
end if;
v_ret(0).num_bins := v_num_bins;
if proc_call'length > C_FC_MAX_PROC_CALL_LENGTH then
v_ret(0).proc_call := proc_call(1 to C_FC_MAX_PROC_CALL_LENGTH-3) & "...";
else
v_ret(0).proc_call(1 to proc_call'length) := proc_call;
end if;
else
alert(TB_ERROR, proc_call & "=> Failed. min_value must be less or equal than max_value", C_TB_SCOPE_DEFAULT);
return C_EMPTY_NEW_BIN_ARRAY;
end if;
return v_ret;
end function;
------------------------------------------------------------
-- Bin functions
------------------------------------------------------------
-- Creates a bin for a single value
impure function bin(
constant value : integer)
return t_new_bin_array is
constant C_LOCAL_CALL : string := "bin(" & to_string(value) & ")";
begin
return create_bin_single(VAL, value, C_LOCAL_CALL);
end function;
-- Creates a bin for multiple values
impure function bin(
constant set_of_values : integer_vector)
return t_new_bin_array is
constant C_LOCAL_CALL : string := "bin(" & to_string(set_of_values) & ")";
begin
return create_bin_multiple(VAL, set_of_values, C_LOCAL_CALL);
end function;
-- Creates a bin for a range of values. Several bins can be created by dividing the range into num_bins.
-- If num_bins is 0 then a bin is created for each value.
impure function bin_range(
constant min_value : integer;
constant max_value : integer;
constant num_bins : natural := 1)
return t_new_bin_array is
constant C_LOCAL_CALL : string := "bin_range(" & to_string(min_value) & ", " & to_string(max_value) &
return_string_if_true(", num_bins:" & to_string(num_bins), num_bins /= 1) & ")";
begin
return create_bin_range(RAN, min_value, max_value, num_bins, C_LOCAL_CALL);
end function;
-- Creates a bin for a vector's range. Several bins can be created by dividing the range into num_bins.
-- If num_bins is 0 then a bin is created for each value.
impure function bin_vector(
constant vector : std_logic_vector;
constant num_bins : natural := 1)
return t_new_bin_array is
constant C_LOCAL_CALL : string := "bin_vector(LEN:" & to_string(vector'length) & return_string_if_true(", num_bins:" &
to_string(num_bins), num_bins /= 1) & ")";
begin
return create_bin_range(RAN, 0, 2**vector'length-1, num_bins, C_LOCAL_CALL);
end function;
-- Creates a bin for a transition of values
impure function bin_transition(
constant set_of_values : integer_vector)
return t_new_bin_array is
constant C_LOCAL_CALL : string := "bin_transition(" & to_string(set_of_values) & ")";
begin
return create_bin_multiple(TRN, set_of_values, C_LOCAL_CALL);
end function;
-- Creates an ignore bin for a single value
impure function ignore_bin(
constant value : integer)
return t_new_bin_array is
constant C_LOCAL_CALL : string := "ignore_bin(" & to_string(value) & ")";
begin
return create_bin_single(VAL_IGNORE, value, C_LOCAL_CALL);
end function;
-- Creates an ignore bin for a range of values
impure function ignore_bin_range(
constant min_value : integer;
constant max_value : integer)
return t_new_bin_array is
constant C_LOCAL_CALL : string := "ignore_bin_range(" & to_string(min_value) & "," & to_string(max_value) & ")";
begin
return create_bin_range(RAN_IGNORE, min_value, max_value, 1, C_LOCAL_CALL);
end function;
-- Creates an ignore bin for a transition of values
impure function ignore_bin_transition(
constant set_of_values : integer_vector)
return t_new_bin_array is
constant C_LOCAL_CALL : string := "ignore_bin_transition(" & to_string(set_of_values) & ")";
begin
return create_bin_multiple(TRN_IGNORE, set_of_values, C_LOCAL_CALL);
end function;
-- Creates an illegal bin for a single value
impure function illegal_bin(
constant value : integer)
return t_new_bin_array is
constant C_LOCAL_CALL : string := "illegal_bin(" & to_string(value) & ")";
begin
return create_bin_single(VAL_ILLEGAL, value, C_LOCAL_CALL);
end function;
-- Creates an illegal bin for a range of values
impure function illegal_bin_range(
constant min_value : integer;
constant max_value : integer)
return t_new_bin_array is
constant C_LOCAL_CALL : string := "illegal_bin_range(" & to_string(min_value) & "," & to_string(max_value) & ")";
begin
return create_bin_range(RAN_ILLEGAL, min_value, max_value, 1, C_LOCAL_CALL);
end function;
-- Creates an illegal bin for a transition of values
impure function illegal_bin_transition(
constant set_of_values : integer_vector)
return t_new_bin_array is
constant C_LOCAL_CALL : string := "illegal_bin_transition(" & to_string(set_of_values) & ")";
begin
return create_bin_multiple(TRN_ILLEGAL, set_of_values, C_LOCAL_CALL);
end function;
------------------------------------------------------------
-- Overall coverage
------------------------------------------------------------
procedure fc_set_covpts_coverage_goal(
constant percentage : in positive range 1 to 100;
constant scope : in string := C_TB_SCOPE_DEFAULT;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel) is
constant C_LOCAL_CALL : string := "fc_set_covpts_coverage_goal(" & to_string(percentage) & ")";
begin
log(ID_FUNC_COV_CONFIG, C_LOCAL_CALL, scope, msg_id_panel);
protected_covergroup_status.set_covpts_coverage_goal(percentage);
end procedure;
impure function fc_get_covpts_coverage_goal(
constant VOID : t_void)
return positive is
begin
return protected_covergroup_status.get_covpts_coverage_goal(VOID);
end function;
impure function fc_get_overall_coverage(
constant coverage_type : t_overall_coverage_type)
return real is
begin
if coverage_type = BINS then
return protected_covergroup_status.get_total_bins_coverage(VOID);
elsif coverage_type = HITS then
return protected_covergroup_status.get_total_hits_coverage(VOID);
else -- COVPTS
return protected_covergroup_status.get_total_covpts_coverage(NO_GOAL);
end if;
end function;
impure function fc_overall_coverage_completed(
constant VOID : t_void)
return boolean is
begin
return protected_covergroup_status.get_total_covpts_coverage(GOAL_CAPPED) = 100.0;
end function;
procedure fc_report_overall_coverage(
constant VOID : in t_void) is
begin
fc_report_overall_coverage(NON_VERBOSE);
end procedure;
procedure fc_report_overall_coverage(
constant verbosity : in t_report_verbosity;
constant file_name : in string := "";
constant open_mode : in file_open_kind := append_mode;
constant scope : in string := C_TB_SCOPE_DEFAULT) is
file file_handler : text;
constant C_PREFIX : string := C_LOG_PREFIX & " ";
constant C_HEADER_1 : string := "*** OVERALL COVERAGE REPORT (VERBOSE): " & to_string(scope) & " ***";
constant C_HEADER_2 : string := "*** OVERALL COVERAGE REPORT (NON VERBOSE): " & to_string(scope) & " ***";
constant C_HEADER_3 : string := "*** OVERALL HOLES REPORT: " & to_string(scope) & " ***";
constant C_COLUMN_WIDTH : positive := 20;
constant C_PRINT_GOAL : boolean := protected_covergroup_status.get_covpts_coverage_goal(VOID) /= 100;
variable v_line : line;
variable v_log_extra_space : integer := 0;
begin
-- Calculate how much space we can insert between the columns of the report
v_log_extra_space := (C_LOG_LINE_WIDTH - C_PREFIX'length - C_FC_MAX_NAME_LENGTH - C_COLUMN_WIDTH*5)/7;
if v_log_extra_space < 1 then
alert(TB_WARNING, "C_LOG_LINE_WIDTH is too small or C_FC_MAX_NAME_LENGTH is too big, the report will not be properly aligned.", scope);
v_log_extra_space := 1;
end if;
-- Print report header
write(v_line, LF & fill_string('=', (C_LOG_LINE_WIDTH - C_PREFIX'length)) & LF);
if verbosity = VERBOSE then
write(v_line, timestamp_header(now, justify(C_HEADER_1, LEFT, C_LOG_LINE_WIDTH - C_PREFIX'length, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE)) & LF);
elsif verbosity = NON_VERBOSE then
write(v_line, timestamp_header(now, justify(C_HEADER_2, LEFT, C_LOG_LINE_WIDTH - C_PREFIX'length, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE)) & LF);
elsif verbosity = HOLES_ONLY then
write(v_line, timestamp_header(now, justify(C_HEADER_3, LEFT, C_LOG_LINE_WIDTH - C_PREFIX'length, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE)) & LF);
end if;
write(v_line, fill_string('=', (C_LOG_LINE_WIDTH - C_PREFIX'length)) & LF);
-- Print summary
write(v_line, return_string_if_true("Goal: Covpts: " & to_string(protected_covergroup_status.get_covpts_coverage_goal(VOID)) & "%" & LF, C_PRINT_GOAL) &
return_string_if_true("% of Goal: Covpts: " & to_string(protected_covergroup_status.get_total_covpts_coverage(GOAL_CAPPED),2) & "%" & LF, C_PRINT_GOAL) &
return_string_if_true("% of Goal (uncapped): Covpts: " & to_string(protected_covergroup_status.get_total_covpts_coverage(GOAL_UNCAPPED),2) & "%" & LF, C_PRINT_GOAL) &
"Coverage (for goal 100): " &
justify("Covpts: " & to_string(protected_covergroup_status.get_total_covpts_coverage(NO_GOAL),2) & "%, ", left, 18, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) &
justify("Bins: " & to_string(protected_covergroup_status.get_total_bins_coverage(VOID),2) & "%, ", left, 16, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) &
justify("Hits: " & to_string(protected_covergroup_status.get_total_hits_coverage(VOID),2) & "%", left, 14, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & LF &
fill_string('=', (C_LOG_LINE_WIDTH - C_PREFIX'length)) & LF);
if verbosity = VERBOSE or verbosity = HOLES_ONLY then
-- Print column headers
write(v_line, justify(
fill_string(' ', v_log_extra_space) &
justify("COVERPOINT" , center, C_FC_MAX_NAME_LENGTH, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space) &
justify("COVERAGE WEIGHT" , center, C_COLUMN_WIDTH, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space) &
justify("COVERED BINS" , center, C_COLUMN_WIDTH, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space) &
justify("COVERAGE(BINS|HITS)" , center, C_COLUMN_WIDTH, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space) &
justify("GOAL(BINS|HITS)" , center, C_COLUMN_WIDTH, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space) &
justify("% OF GOAL(BINS|HITS)", center, C_COLUMN_WIDTH, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space),
left, C_LOG_LINE_WIDTH - C_PREFIX'length, KEEP_LEADING_SPACE, DISALLOW_TRUNCATE) & LF);
-- Print coverpoints
for i in 0 to C_FC_MAX_NUM_COVERPOINTS-1 loop
if protected_covergroup_status.is_initialized(i) then
if verbosity /= HOLES_ONLY or not(protected_covergroup_status.get_bins_coverage(i, GOAL_CAPPED) = 100.0 and protected_covergroup_status.get_hits_coverage(i, GOAL_CAPPED) = 100.0) then
write(v_line, justify(
fill_string(' ', v_log_extra_space) &
justify(protected_covergroup_status.get_name(i), center, C_FC_MAX_NAME_LENGTH, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space) &
justify(to_string(protected_covergroup_status.get_coverage_weight(i)), center, C_COLUMN_WIDTH, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space) &
justify(to_string(protected_covergroup_status.get_num_covered_bins(i)) & " / " &
to_string(protected_covergroup_status.get_num_valid_bins(i)), center, C_COLUMN_WIDTH, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space) &
justify(to_string(protected_covergroup_status.get_bins_coverage(i, NO_GOAL),2) & "% | " &
to_string(protected_covergroup_status.get_hits_coverage(i, NO_GOAL),2) & "%", center, C_COLUMN_WIDTH, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space) &
justify(to_string(protected_covergroup_status.get_bins_coverage_goal(i)) & "% | " &
to_string(protected_covergroup_status.get_hits_coverage_goal(i)) & "%", center, C_COLUMN_WIDTH, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space) &
justify(to_string(protected_covergroup_status.get_bins_coverage(i, GOAL_CAPPED),2) & "% | " &
to_string(protected_covergroup_status.get_hits_coverage(i, GOAL_CAPPED),2) & "%", center, C_COLUMN_WIDTH, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space),
left, C_LOG_LINE_WIDTH - C_PREFIX'length, KEEP_LEADING_SPACE, DISALLOW_TRUNCATE) & LF);
end if;
end if;
end loop;
-- Print report bottom line
write(v_line, fill_string('=', (C_LOG_LINE_WIDTH - C_PREFIX'length)) & LF & LF);
end if;
-- Write the info string to transcript
wrap_lines(v_line, 1, 1, C_LOG_LINE_WIDTH-C_PREFIX'length);
prefix_lines(v_line, C_PREFIX);
if file_name /= "" then
file_open(file_handler, file_name, open_mode);
tee(file_handler, v_line); -- write to file, while keeping the line contents
file_close(file_handler);
end if;
write_line_to_log_destination(v_line);
deallocate(v_line);
end procedure;
------------------------------------------------------------
-- Protected type
------------------------------------------------------------
type t_coverpoint is protected body
type t_bin_type_verbosity is (LONG, SHORT, NONE);
type t_samples_vector is array (natural range <>) of integer_vector(C_FC_MAX_NUM_BIN_VALUES-1 downto 0);
-- This means that the randomization weight of the bin will be equal to the min_hits
-- parameter and will be reduced by 1 every time the bin is sampled.
constant C_USE_ADAPTIVE_WEIGHT : integer := -1;
-- Indicates that the coverpoint hasn't been initialized
constant C_DEALLOCATED_ID : integer := -1;
-- Indicates an uninitialized natural value
constant C_UNINITIALIZED : integer := -1;
variable priv_id : integer := C_DEALLOCATED_ID;
variable priv_name : string(1 to C_FC_MAX_NAME_LENGTH);
variable priv_scope : string(1 to C_LOG_SCOPE_WIDTH) := C_TB_SCOPE_DEFAULT & fill_string(NUL, C_LOG_SCOPE_WIDTH-C_TB_SCOPE_DEFAULT'length);
variable priv_bins : t_cov_bin_vector_ptr := new t_cov_bin_vector(0 to C_FC_DEFAULT_INITIAL_NUM_BINS_ALLOCATED-1);
variable priv_bins_idx : natural := 0;
variable priv_invalid_bins : t_cov_bin_vector_ptr := new t_cov_bin_vector(0 to C_FC_DEFAULT_INITIAL_NUM_BINS_ALLOCATED-1);
variable priv_invalid_bins_idx : natural := 0;
variable priv_num_bins_crossed : integer := C_UNINITIALIZED;
variable priv_rand_gen : t_rand;
variable priv_rand_transition_bin_idx : integer := C_UNINITIALIZED;
variable priv_rand_transition_bin_value_idx : t_natural_vector(0 to C_MAX_NUM_CROSS_BINS-1) := (others => 0);
variable priv_bin_sample_shift_reg : t_samples_vector(0 to C_MAX_NUM_CROSS_BINS-1) := (others => (others => 0));
variable priv_illegal_bin_alert_level : t_alert_level := ERROR;
variable priv_bin_overlap_alert_level : t_alert_level := NO_ALERT;
variable priv_num_bins_allocated_increment : positive := C_FC_DEFAULT_NUM_BINS_ALLOCATED_INCREMENT;
------------------------------------------------------------
-- Internal functions and procedures
------------------------------------------------------------
-- Returns a string with all the procedure calls in the array
impure function get_proc_calls(
constant bin_array : t_new_bin_array)
return string is
variable v_line : line;
impure function return_and_deallocate return string is
constant ret : string := v_line.all;
begin
DEALLOCATE(v_line);
return ret;
end function;
begin
for i in bin_array'range loop
write(v_line, bin_array(i).proc_call);
if i < bin_array'length-1 then
write(v_line, ',');
end if;
end loop;
return return_and_deallocate;
end function;
-- Returns a string with all the bin values in the array
impure function get_bin_array_values(
constant bin_array : t_new_bin_array;
constant bin_verbosity : t_bin_type_verbosity := SHORT;
constant bin_delimiter : character := ',')
return string is
variable v_line : line;
impure function return_bin_type(
constant full_name : string;
constant short_name : string;
constant bin_verbosity : t_bin_type_verbosity)
return string is
begin
if bin_verbosity = LONG then
return full_name;
elsif bin_verbosity = SHORT then
return short_name;
else
return "";
end if;
end function;
impure function return_and_deallocate return string is
constant ret : string := v_line.all;
begin
DEALLOCATE(v_line);
return ret;
end function;
begin
for i in bin_array'range loop
for j in 0 to bin_array(i).num_bins-1 loop
case bin_array(i).bin_vector(j).contains is
when VAL | VAL_IGNORE | VAL_ILLEGAL =>
if bin_array(i).bin_vector(j).contains = VAL then
write(v_line, string'(return_bin_type("bin", "", bin_verbosity)));
elsif bin_array(i).bin_vector(j).contains = VAL_IGNORE then
write(v_line, string'(return_bin_type("ignore_bin", "IGN", bin_verbosity)));
else
write(v_line, string'(return_bin_type("illegal_bin", "ILL", bin_verbosity)));
end if;
if bin_array(i).bin_vector(j).num_values = 1 then
write(v_line, '(' & to_string(bin_array(i).bin_vector(j).values(0)) & ')');
else
write(v_line, to_string(bin_array(i).bin_vector(j).values(0 to bin_array(i).bin_vector(j).num_values-1)));
end if;
when RAN | RAN_IGNORE | RAN_ILLEGAL =>
if bin_array(i).bin_vector(j).contains = RAN then
write(v_line, string'(return_bin_type("bin_range", "", bin_verbosity)));
elsif bin_array(i).bin_vector(j).contains = RAN_IGNORE then
write(v_line, string'(return_bin_type("ignore_bin_range", "IGN", bin_verbosity)));
else
write(v_line, string'(return_bin_type("illegal_bin_range", "ILL", bin_verbosity)));
end if;
write(v_line, "(" & to_string(bin_array(i).bin_vector(j).values(0)) & " to " & to_string(bin_array(i).bin_vector(j).values(1)) & ")");
when TRN | TRN_IGNORE | TRN_ILLEGAL =>
if bin_array(i).bin_vector(j).contains = TRN then
write(v_line, string'(return_bin_type("bin_transition", "", bin_verbosity)));
elsif bin_array(i).bin_vector(j).contains = TRN_IGNORE then
write(v_line, string'(return_bin_type("ignore_bin_transition", "IGN", bin_verbosity)));
else
write(v_line, string'(return_bin_type("illegal_bin_transition", "ILL", bin_verbosity)));
end if;
write(v_line, '(');
for k in 0 to bin_array(i).bin_vector(j).num_values-1 loop
write(v_line, to_string(bin_array(i).bin_vector(j).values(k)));
if k < bin_array(i).bin_vector(j).num_values-1 then
write(v_line, string'("->"));
end if;
end loop;
write(v_line, ')');
end case;
if i < bin_array'length-1 or j < bin_array(i).num_bins-1 then
write(v_line, bin_delimiter);
end if;
end loop;
end loop;
if v_line /= NULL then
return return_and_deallocate;
else
return "";
end if;
end function;
-- Returns a string with all the values in the bin. Since it is
-- used in the report, if the string is bigger than the maximum
-- length allowed, the bin name is returned instead.
-- If max_str_length is 0 then the string with the values is
-- always returned.
impure function get_bin_values(
constant bin : t_cov_bin;
constant max_str_length : natural := 0)
return string is
variable v_new_bin_array : t_new_bin_array(0 to 0);
variable v_line : line;
impure function return_and_deallocate return string is
constant ret : string := v_line.all;
begin
DEALLOCATE(v_line);
return ret;
end function;
begin
for i in 0 to priv_num_bins_crossed-1 loop
v_new_bin_array(0).bin_vector(i).contains := bin.cross_bins(i).contains;
v_new_bin_array(0).bin_vector(i).values := bin.cross_bins(i).values;
v_new_bin_array(0).bin_vector(i).num_values := bin.cross_bins(i).num_values;
end loop;
v_new_bin_array(0).num_bins := priv_num_bins_crossed;
-- Used in the report, so the bins in each vector are crossed
write(v_line, get_bin_array_values(v_new_bin_array, NONE, 'x'));
if max_str_length /= 0 and v_line'length > max_str_length then
DEALLOCATE(v_line);
return to_string(bin.name);
else
return return_and_deallocate;
end if;
end function;
-- Returns a string with the bin content
impure function get_bin_info(
constant bin : t_bin)
return string is
variable v_new_bin_array : t_new_bin_array(0 to 0);
begin
v_new_bin_array(0).bin_vector(0).contains := bin.contains;
v_new_bin_array(0).bin_vector(0).values := bin.values;
v_new_bin_array(0).bin_vector(0).num_values := bin.num_values;
v_new_bin_array(0).num_bins := 1;
return get_bin_array_values(v_new_bin_array, LONG);
end function;
-- If the bin_name is empty, it returns a default name based on the bin_idx.
-- Otherwise it returns the bin_name padded to match the C_FC_MAX_NAME_LENGTH.
function get_bin_name(
constant bin_name : string;
constant bin_idx : string)
return string is
begin
if bin_name = "" then
return "bin_" & bin_idx & fill_string(NUL, C_FC_MAX_NAME_LENGTH-4-bin_idx'length);
else
if bin_name'length > C_FC_MAX_NAME_LENGTH then
return bin_name(1 to C_FC_MAX_NAME_LENGTH);
else
return bin_name & fill_string(NUL, C_FC_MAX_NAME_LENGTH-bin_name'length);
end if;
end if;
end function;
-- Returns a string with the coverpoint's name. Used as prefix in log messages
impure function get_name_prefix(
constant VOID : t_void)
return string is
begin
return "[" & to_string(priv_name) & "] ";
end function;
-- Returns true if the bin is ignored
impure function is_bin_ignore(
constant bin : t_cov_bin)
return boolean is
variable v_is_ignore : boolean := false;
begin
for i in 0 to priv_num_bins_crossed-1 loop
v_is_ignore := v_is_ignore or (bin.cross_bins(i).contains = VAL_IGNORE or
bin.cross_bins(i).contains = RAN_IGNORE or
bin.cross_bins(i).contains = TRN_IGNORE);
end loop;
return v_is_ignore;
end function;
-- Returns true if the bin is illegal
impure function is_bin_illegal(
constant bin : t_cov_bin)
return boolean is
variable v_is_illegal : boolean := false;
begin
for i in 0 to priv_num_bins_crossed-1 loop
v_is_illegal := v_is_illegal or (bin.cross_bins(i).contains = VAL_ILLEGAL or
bin.cross_bins(i).contains = RAN_ILLEGAL or
bin.cross_bins(i).contains = TRN_ILLEGAL);
end loop;
return v_is_illegal;
end function;
-- Returns the minimum number of hits multiplied by the hits coverage goal
impure function get_total_min_hits(
constant min_hits : natural)
return natural is
begin
return integer(real(min_hits)*real(protected_covergroup_status.get_hits_coverage_goal(priv_id))/100.0);
end function;
-- Returns the percentage of hits/min_hits in a bin. Note that it saturates at 100%
impure function get_bin_coverage(
constant bin : t_cov_bin)
return real is
variable v_coverage : real;
begin
if bin.hits < bin.min_hits then
v_coverage := real(bin.hits)*100.0/real(bin.min_hits);
else
v_coverage := 100.0;
end if;
return v_coverage;
end function;
-- Initializes a new coverpoint by registering it in the covergroup status register, setting its name and randomization seeds.
procedure initialize_coverpoint(
constant local_call : in string) is
begin
if priv_id = C_DEALLOCATED_ID then
priv_id := protected_covergroup_status.add_coverpoint(VOID);
if priv_id = C_DEALLOCATED_ID then
alert(TB_FAILURE, local_call & "=> Number of coverpoints exceeds C_FC_MAX_NUM_COVERPOINTS.\n Increase C_FC_MAX_NUM_COVERPOINTS in adaptations package.", priv_scope);
return;
end if;
-- Only set the default name if it hasn't been given
if priv_name = fill_string(NUL, priv_name'length) then
set_name(protected_covergroup_status.get_name(priv_id));
end if;
priv_rand_gen.set_rand_seeds(priv_name);
end if;
end procedure;
-- TODO: max 16 dimensions
-- Checks that the number of crossed bins does not change.
-- If the extra parameters are given, it checks that the coverpoints are not empty.
procedure check_num_bins_crossed(
constant num_bins_crossed : in integer;
constant local_call : in string;
constant coverpoint1_num_bins_crossed : in integer := 0;
constant coverpoint2_num_bins_crossed : in integer := 0;
constant coverpoint3_num_bins_crossed : in integer := 0;
constant coverpoint4_num_bins_crossed : in integer := 0;
constant coverpoint5_num_bins_crossed : in integer := 0) is
begin
initialize_coverpoint(local_call);
check_value(coverpoint1_num_bins_crossed /= C_UNINITIALIZED, TB_FAILURE, "Coverpoint 1 is empty", priv_scope, ID_NEVER, caller_name => local_call);
check_value(coverpoint2_num_bins_crossed /= C_UNINITIALIZED, TB_FAILURE, "Coverpoint 2 is empty", priv_scope, ID_NEVER, caller_name => local_call);
check_value(coverpoint3_num_bins_crossed /= C_UNINITIALIZED, TB_FAILURE, "Coverpoint 3 is empty", priv_scope, ID_NEVER, caller_name => local_call);
check_value(coverpoint4_num_bins_crossed /= C_UNINITIALIZED, TB_FAILURE, "Coverpoint 4 is empty", priv_scope, ID_NEVER, caller_name => local_call);
check_value(coverpoint5_num_bins_crossed /= C_UNINITIALIZED, TB_FAILURE, "Coverpoint 5 is empty", priv_scope, ID_NEVER, caller_name => local_call);
-- The number of bins crossed is set on the first call and can't be changed
if priv_num_bins_crossed = C_UNINITIALIZED and num_bins_crossed > 0 then
priv_num_bins_crossed := num_bins_crossed;
elsif priv_num_bins_crossed /= num_bins_crossed and num_bins_crossed > 0 then
alert(TB_FAILURE, local_call & "=> Cannot mix different number of crossed bins.", priv_scope);
end if;
end procedure;
-- Returns true if a bin is already stored in the bin vector
impure function find_duplicate_bin(
constant cov_bin_vector : t_cov_bin_vector;
constant cov_bin_idx : natural;
constant cross_bin_idx : natural)
return boolean is
constant C_CONTAINS : t_cov_bin_type := cov_bin_vector(cov_bin_idx).cross_bins(cross_bin_idx).contains;
constant C_NUM_VALUES : natural := cov_bin_vector(cov_bin_idx).cross_bins(cross_bin_idx).num_values;
constant C_VALUES : integer_vector(0 to C_NUM_VALUES-1) := cov_bin_vector(cov_bin_idx).cross_bins(cross_bin_idx).values(0 to C_NUM_VALUES-1);
begin
for i in 0 to cov_bin_idx-1 loop
if cov_bin_vector(i).cross_bins(cross_bin_idx).contains = C_CONTAINS and
cov_bin_vector(i).cross_bins(cross_bin_idx).num_values = C_NUM_VALUES and
cov_bin_vector(i).cross_bins(cross_bin_idx).values(0 to C_NUM_VALUES-1) = C_VALUES
then
return true;
end if;
end loop;
return false;
end function;
-- Copies all the bins in a bin array to a bin vector.
-- The bin array can contain several bin_vector elements depending on the
-- number of bins created by a single bin function. It can also contain
-- several array elements depending on the number of concatenated bin
-- functions used.
procedure copy_bins_in_bin_array(
constant bin_array : in t_new_bin_array;
variable cov_bin : out t_new_cov_bin;
constant proc_call : in string) is
variable v_num_bins : natural := 0;
begin
for i in bin_array'range loop
if v_num_bins + bin_array(i).num_bins > C_FC_MAX_NUM_NEW_BINS then
alert(TB_ERROR, proc_call & "=> Number of bins added in a single procedure call exceeds C_FC_MAX_NUM_NEW_BINS.\n" &
"Increase C_FC_MAX_NUM_NEW_BINS in adaptations package.", C_TB_SCOPE_DEFAULT);
return;
end if;
cov_bin.bin_vector(v_num_bins to v_num_bins+bin_array(i).num_bins-1) := bin_array(i).bin_vector(0 to bin_array(i).num_bins-1);
v_num_bins := v_num_bins + bin_array(i).num_bins;
end loop;
cov_bin.num_bins := v_num_bins;
end procedure;
-- Copies all the bins in a coverpoint to a bin array (including crossed bins)
-- Duplicate bins are not copied since they are assumed to be the result of a cross
procedure copy_bins_in_coverpoint(
variable coverpoint : inout t_coverpoint;
variable bin_array : out t_new_bin_array) is
variable v_coverpoint_bins : t_cov_bin_vector(0 to coverpoint.get_num_valid_bins(VOID)-1);
variable v_coverpoint_invalid_bins : t_cov_bin_vector(0 to coverpoint.get_num_invalid_bins(VOID)-1);
variable v_num_bins : natural := 0;
begin
v_coverpoint_bins := coverpoint.get_valid_bins(VOID);
v_coverpoint_invalid_bins := coverpoint.get_invalid_bins(VOID);
for cross in 0 to bin_array'length-1 loop
for i in v_coverpoint_bins'range loop
if not find_duplicate_bin(v_coverpoint_bins, i, cross) then
bin_array(cross).bin_vector(v_num_bins).contains := v_coverpoint_bins(i).cross_bins(cross).contains;
bin_array(cross).bin_vector(v_num_bins).values := v_coverpoint_bins(i).cross_bins(cross).values;
bin_array(cross).bin_vector(v_num_bins).num_values := v_coverpoint_bins(i).cross_bins(cross).num_values;
v_num_bins := v_num_bins + 1;
end if;
end loop;
for i in v_coverpoint_invalid_bins'range loop
if not find_duplicate_bin(v_coverpoint_invalid_bins, i, cross) then
bin_array(cross).bin_vector(v_num_bins).contains := v_coverpoint_invalid_bins(i).cross_bins(cross).contains;
bin_array(cross).bin_vector(v_num_bins).values := v_coverpoint_invalid_bins(i).cross_bins(cross).values;
bin_array(cross).bin_vector(v_num_bins).num_values := v_coverpoint_invalid_bins(i).cross_bins(cross).num_values;
v_num_bins := v_num_bins + 1;
end if;
end loop;
bin_array(cross).num_bins := v_num_bins;
v_num_bins := 0;
end loop;
end procedure;
-- Creates a bin array from several bin arrays
procedure create_bin_array(
constant proc_call : in string;
variable bin_array : out t_new_bin_array;
constant bin1 : in t_new_bin_array;
constant bin2 : in t_new_bin_array := C_EMPTY_NEW_BIN_ARRAY;
constant bin3 : in t_new_bin_array := C_EMPTY_NEW_BIN_ARRAY;
constant bin4 : in t_new_bin_array := C_EMPTY_NEW_BIN_ARRAY;
constant bin5 : in t_new_bin_array := C_EMPTY_NEW_BIN_ARRAY) is
begin
copy_bins_in_bin_array(bin1, bin_array(0), proc_call);
if bin2 /= C_EMPTY_NEW_BIN_ARRAY then
copy_bins_in_bin_array(bin2, bin_array(1), proc_call);
end if;
if bin3 /= C_EMPTY_NEW_BIN_ARRAY then
copy_bins_in_bin_array(bin3, bin_array(2), proc_call);
end if;
if bin4 /= C_EMPTY_NEW_BIN_ARRAY then
copy_bins_in_bin_array(bin4, bin_array(3), proc_call);
end if;
if bin5 /= C_EMPTY_NEW_BIN_ARRAY then
copy_bins_in_bin_array(bin5, bin_array(4), proc_call);
end if;
end procedure;
-- Creates a bin array from several coverpoints
procedure create_bin_array(
variable bin_array : out t_new_bin_array;
variable coverpoint1 : inout t_coverpoint;
variable coverpoint2 : inout t_coverpoint) is
variable v_bin_array1 : t_new_bin_array(0 to coverpoint1.get_num_bins_crossed(VOID)-1);
variable v_bin_array2 : t_new_bin_array(0 to coverpoint2.get_num_bins_crossed(VOID)-1);
begin
copy_bins_in_coverpoint(coverpoint1, v_bin_array1);
copy_bins_in_coverpoint(coverpoint2, v_bin_array2);
bin_array := v_bin_array1 & v_bin_array2;
end procedure;
-- Overload
procedure create_bin_array(
variable bin_array : out t_new_bin_array;
variable coverpoint1 : inout t_coverpoint;
variable coverpoint2 : inout t_coverpoint;
variable coverpoint3 : inout t_coverpoint) is
variable v_bin_array1 : t_new_bin_array(0 to coverpoint1.get_num_bins_crossed(VOID)-1);
variable v_bin_array2 : t_new_bin_array(0 to coverpoint2.get_num_bins_crossed(VOID)-1);
variable v_bin_array3 : t_new_bin_array(0 to coverpoint3.get_num_bins_crossed(VOID)-1);
begin
copy_bins_in_coverpoint(coverpoint1, v_bin_array1);
copy_bins_in_coverpoint(coverpoint2, v_bin_array2);
copy_bins_in_coverpoint(coverpoint3, v_bin_array3);
bin_array := v_bin_array1 & v_bin_array2 & v_bin_array3;
end procedure;
-- Overload
procedure create_bin_array(
variable bin_array : out t_new_bin_array;
variable coverpoint1 : inout t_coverpoint;
variable coverpoint2 : inout t_coverpoint;
variable coverpoint3 : inout t_coverpoint;
variable coverpoint4 : inout t_coverpoint) is
variable v_bin_array1 : t_new_bin_array(0 to coverpoint1.get_num_bins_crossed(VOID)-1);
variable v_bin_array2 : t_new_bin_array(0 to coverpoint2.get_num_bins_crossed(VOID)-1);
variable v_bin_array3 : t_new_bin_array(0 to coverpoint3.get_num_bins_crossed(VOID)-1);
variable v_bin_array4 : t_new_bin_array(0 to coverpoint4.get_num_bins_crossed(VOID)-1);
begin
copy_bins_in_coverpoint(coverpoint1, v_bin_array1);
copy_bins_in_coverpoint(coverpoint2, v_bin_array2);
copy_bins_in_coverpoint(coverpoint3, v_bin_array3);
copy_bins_in_coverpoint(coverpoint4, v_bin_array4);
bin_array := v_bin_array1 & v_bin_array2 & v_bin_array3 & v_bin_array4;
end procedure;
-- TODO: create more overloads (16)
-- Overload
procedure create_bin_array(
variable bin_array : out t_new_bin_array;
variable coverpoint1 : inout t_coverpoint;
variable coverpoint2 : inout t_coverpoint;
variable coverpoint3 : inout t_coverpoint;
variable coverpoint4 : inout t_coverpoint;
variable coverpoint5 : inout t_coverpoint) is
variable v_bin_array1 : t_new_bin_array(0 to coverpoint1.get_num_bins_crossed(VOID)-1);
variable v_bin_array2 : t_new_bin_array(0 to coverpoint2.get_num_bins_crossed(VOID)-1);
variable v_bin_array3 : t_new_bin_array(0 to coverpoint3.get_num_bins_crossed(VOID)-1);
variable v_bin_array4 : t_new_bin_array(0 to coverpoint4.get_num_bins_crossed(VOID)-1);
variable v_bin_array5 : t_new_bin_array(0 to coverpoint5.get_num_bins_crossed(VOID)-1);
begin
copy_bins_in_coverpoint(coverpoint1, v_bin_array1);
copy_bins_in_coverpoint(coverpoint2, v_bin_array2);
copy_bins_in_coverpoint(coverpoint3, v_bin_array3);
copy_bins_in_coverpoint(coverpoint4, v_bin_array4);
copy_bins_in_coverpoint(coverpoint5, v_bin_array5);
bin_array := v_bin_array1 & v_bin_array2 & v_bin_array3 & v_bin_array4 & v_bin_array5;
end procedure;
-- Checks that the number of transitions is the same for all elements in a cross
procedure check_cross_num_transitions(
variable num_transitions : inout integer;
constant contains : in t_cov_bin_type;
constant num_values : in natural) is
begin
if contains = TRN or contains = TRN_IGNORE or contains = TRN_ILLEGAL then
if num_transitions = C_UNINITIALIZED then
num_transitions := num_values;
else
check_value(num_values, num_transitions, TB_ERROR, "Number of transition values must be the same in all cross elements", priv_scope, ID_NEVER);
end if;
end if;
end procedure;
-- Resizes the bin vector by creating a new memory structure and deallocating the old one
procedure resize_bin_vector(
variable bin_vector : inout t_cov_bin_vector_ptr;
constant size : in natural := 0) is
variable v_copy_ptr : t_cov_bin_vector_ptr;
begin
v_copy_ptr := bin_vector;
if size = 0 then
bin_vector := new t_cov_bin_vector(0 to v_copy_ptr'length + priv_num_bins_allocated_increment);
else
bin_vector := new t_cov_bin_vector(0 to size-1);
end if;
bin_vector(0 to v_copy_ptr'length-1) := v_copy_ptr.all;
DEALLOCATE(v_copy_ptr);
end procedure;
-- Adds bins in a recursive way
procedure add_bins_recursive(
constant bin_array : in t_new_bin_array;
constant bin_array_idx : in integer;
variable idx_reg : inout integer_vector;
constant min_hits : in positive;
constant rand_weight : in natural;
constant use_rand_weight : in boolean;
constant bin_name : in string) is
constant C_NUM_CROSS_BINS : natural := bin_array'length;
variable v_bin_is_valid : boolean := true;
variable v_bin_is_illegal : boolean := false;
variable v_num_transitions : integer;
begin
check_value(priv_id /= C_DEALLOCATED_ID, TB_FAILURE, "Coverpoint has not been initialized", priv_scope, ID_NEVER);
-- Iterate through the bins in the current array element
for i in 0 to bin_array(bin_array_idx).num_bins-1 loop
-- Store the bin index for the current element of the array
idx_reg(bin_array_idx) := i;
-- Last element of the array has been reached, add bins
if bin_array_idx = C_NUM_CROSS_BINS-1 then
-- Check that all the bins being added are valid
for j in 0 to C_NUM_CROSS_BINS-1 loop
v_bin_is_valid := v_bin_is_valid and (bin_array(j).bin_vector(idx_reg(j)).contains = VAL or
bin_array(j).bin_vector(idx_reg(j)).contains = RAN or
bin_array(j).bin_vector(idx_reg(j)).contains = TRN);
v_bin_is_illegal := v_bin_is_illegal or (bin_array(j).bin_vector(idx_reg(j)).contains = VAL_ILLEGAL or
bin_array(j).bin_vector(idx_reg(j)).contains = RAN_ILLEGAL or
bin_array(j).bin_vector(idx_reg(j)).contains = TRN_ILLEGAL);
end loop;
v_num_transitions := C_UNINITIALIZED;
-- Store valid bins
if v_bin_is_valid then
-- Resize if there's no space in the list
if priv_bins_idx = priv_bins'length then
resize_bin_vector(priv_bins);
end if;
for j in 0 to C_NUM_CROSS_BINS-1 loop
check_cross_num_transitions(v_num_transitions, bin_array(j).bin_vector(idx_reg(j)).contains, bin_array(j).bin_vector(idx_reg(j)).num_values);
priv_bins(priv_bins_idx).cross_bins(j).contains := bin_array(j).bin_vector(idx_reg(j)).contains;
priv_bins(priv_bins_idx).cross_bins(j).values := bin_array(j).bin_vector(idx_reg(j)).values;
priv_bins(priv_bins_idx).cross_bins(j).num_values := bin_array(j).bin_vector(idx_reg(j)).num_values;
end loop;
priv_bins(priv_bins_idx).hits := 0;
priv_bins(priv_bins_idx).min_hits := min_hits;
priv_bins(priv_bins_idx).rand_weight := rand_weight when use_rand_weight else C_USE_ADAPTIVE_WEIGHT;
priv_bins(priv_bins_idx).transition_mask := (others => '0');
priv_bins(priv_bins_idx).name := get_bin_name(bin_name, to_string(priv_bins_idx+priv_invalid_bins_idx));
priv_bins_idx := priv_bins_idx + 1;
-- Update covergroup status register
protected_covergroup_status.increment_valid_bin_count(priv_id);
protected_covergroup_status.increment_min_hits_count(priv_id, min_hits);
-- Store ignore or illegal bins
else
-- Check if there's space in the list
if priv_invalid_bins_idx = priv_invalid_bins'length then
resize_bin_vector(priv_invalid_bins);
end if;
for j in 0 to C_NUM_CROSS_BINS-1 loop
check_cross_num_transitions(v_num_transitions, bin_array(j).bin_vector(idx_reg(j)).contains, bin_array(j).bin_vector(idx_reg(j)).num_values);
priv_invalid_bins(priv_invalid_bins_idx).cross_bins(j).contains := bin_array(j).bin_vector(idx_reg(j)).contains;
priv_invalid_bins(priv_invalid_bins_idx).cross_bins(j).values := bin_array(j).bin_vector(idx_reg(j)).values;
priv_invalid_bins(priv_invalid_bins_idx).cross_bins(j).num_values := bin_array(j).bin_vector(idx_reg(j)).num_values;
end loop;
priv_invalid_bins(priv_invalid_bins_idx).hits := 0;
priv_invalid_bins(priv_invalid_bins_idx).min_hits := 0;
priv_invalid_bins(priv_invalid_bins_idx).rand_weight := 0;
priv_invalid_bins(priv_invalid_bins_idx).transition_mask := (others => '0');
priv_invalid_bins(priv_invalid_bins_idx).name := get_bin_name(bin_name, to_string(priv_bins_idx+priv_invalid_bins_idx));
priv_invalid_bins_idx := priv_invalid_bins_idx + 1;
end if;
-- Go to the next element of the array
else
add_bins_recursive(bin_array, bin_array_idx+1, idx_reg, min_hits, rand_weight, use_rand_weight, bin_name);
end if;
end loop;
end procedure;
------------------------------------------------------------
-- Configuration
------------------------------------------------------------
procedure set_name(
constant name : in string) is
constant C_LOCAL_CALL : string := "set_name(" & name & ")";
begin
if name'length > C_FC_MAX_NAME_LENGTH then
priv_name := name(1 to C_FC_MAX_NAME_LENGTH);
else
priv_name := name & fill_string(NUL, C_FC_MAX_NAME_LENGTH-name'length);
end if;
initialize_coverpoint(C_LOCAL_CALL);
protected_covergroup_status.set_name(priv_id, priv_name);
end procedure;
impure function get_name(
constant VOID : t_void)
return string is
begin
return to_string(priv_name);
end function;
procedure set_scope(
constant scope : in string) is
constant C_LOCAL_CALL : string := "set_scope(" & scope & ")";
begin
initialize_coverpoint(C_LOCAL_CALL);
if scope'length > C_LOG_SCOPE_WIDTH then
priv_scope := scope(1 to C_LOG_SCOPE_WIDTH);
else
priv_scope := scope & fill_string(NUL, C_LOG_SCOPE_WIDTH-scope'length);
end if;
end procedure;
impure function get_scope(
constant VOID : t_void)
return string is
begin
return to_string(priv_scope);
end function;
procedure set_overall_coverage_weight(
constant weight : in natural;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel) is
constant C_LOCAL_CALL : string := "set_overall_coverage_weight(" & to_string(weight) & ")";
begin
initialize_coverpoint(C_LOCAL_CALL);
log(ID_FUNC_COV_CONFIG, get_name_prefix(VOID) & C_LOCAL_CALL, priv_scope, msg_id_panel);
protected_covergroup_status.set_coverage_weight(priv_id, weight);
end procedure;
impure function get_overall_coverage_weight(
constant VOID : t_void)
return natural is
begin
if priv_id /= C_DEALLOCATED_ID then
return protected_covergroup_status.get_coverage_weight(priv_id);
else
return 1;
end if;
end function;
procedure set_bins_coverage_goal(
constant percentage : in positive range 1 to 100;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel) is
constant C_LOCAL_CALL : string := "set_bins_coverage_goal(" & to_string(percentage) & ")";
begin
initialize_coverpoint(C_LOCAL_CALL);
log(ID_FUNC_COV_CONFIG, get_name_prefix(VOID) & C_LOCAL_CALL, priv_scope, msg_id_panel);
protected_covergroup_status.set_bins_coverage_goal(priv_id, percentage);
end procedure;
impure function get_bins_coverage_goal(
constant VOID : t_void)
return positive is
begin
if priv_id /= C_DEALLOCATED_ID then
return protected_covergroup_status.get_bins_coverage_goal(priv_id);
else
return 100;
end if;
end function;
procedure set_hits_coverage_goal(
constant percentage : in positive;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel) is
constant C_LOCAL_CALL : string := "set_hits_coverage_goal(" & to_string(percentage) & ")";
begin
initialize_coverpoint(C_LOCAL_CALL);
log(ID_FUNC_COV_CONFIG, get_name_prefix(VOID) & C_LOCAL_CALL, priv_scope, msg_id_panel);
protected_covergroup_status.set_hits_coverage_goal(priv_id, percentage);
end procedure;
impure function get_hits_coverage_goal(
constant VOID : t_void)
return positive is
begin
if priv_id /= C_DEALLOCATED_ID then
return protected_covergroup_status.get_hits_coverage_goal(priv_id);
else
return 100;
end if;
end function;
procedure set_illegal_bin_alert_level(
constant alert_level : in t_alert_level;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel) is
constant C_LOCAL_CALL : string := "set_illegal_bin_alert_level(" & to_upper(to_string(alert_level)) & ")";
begin
initialize_coverpoint(C_LOCAL_CALL);
log(ID_FUNC_COV_CONFIG, get_name_prefix(VOID) & C_LOCAL_CALL, priv_scope, msg_id_panel);
priv_illegal_bin_alert_level := alert_level;
end procedure;
impure function get_illegal_bin_alert_level(
constant VOID : t_void)
return t_alert_level is
begin
return priv_illegal_bin_alert_level;
end function;
procedure set_bin_overlap_alert_level(
constant alert_level : in t_alert_level;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel) is
constant C_LOCAL_CALL : string := "set_bin_overlap_alert_level(" & to_upper(to_string(alert_level)) & ")";
begin
initialize_coverpoint(C_LOCAL_CALL);
log(ID_FUNC_COV_CONFIG, get_name_prefix(VOID) & C_LOCAL_CALL, priv_scope, msg_id_panel);
priv_bin_overlap_alert_level := alert_level;
end procedure;
impure function get_bin_overlap_alert_level(
constant VOID : t_void)
return t_alert_level is
begin
return priv_bin_overlap_alert_level;
end function;
procedure write_coverage_db(
constant file_name : in string;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel) is
constant C_LOCAL_CALL : string := "write_coverage_db(" & file_name & ")";
file file_handler : text open write_mode is file_name;
variable v_line : line;
procedure write_value(
constant value : in integer) is
begin
write(v_line, value);
writeline(file_handler, v_line);
end procedure;
procedure write_value(
constant value : in integer_vector) is
begin
for i in 0 to value'length-1 loop
write(v_line, value(i));
if i < value'length-1 then
write(v_line, ' ');
end if;
end loop;
writeline(file_handler, v_line);
end procedure;
procedure write_value(
constant value : in string) is
begin
write(v_line, value);
writeline(file_handler, v_line);
end procedure;
--procedure write_value(
-- constant value : in boolean) is
--begin
-- write(v_line, value);
-- writeline(file_handler, v_line);
--end procedure;
procedure write_bins(
constant bin_idx : in natural;
variable bin_vector : in t_cov_bin_vector_ptr) is
begin
write(v_line, bin_idx);
writeline(file_handler, v_line);
for i in 0 to bin_idx-1 loop
write(v_line, bin_vector(i).name);
writeline(file_handler, v_line);
write(v_line, to_string(bin_vector(i).hits) & ' ' &
to_string(bin_vector(i).min_hits) & ' ' &
to_string(bin_vector(i).rand_weight) & ' ' &
to_string(bin_vector(i).transition_mask));
writeline(file_handler, v_line);
for j in 0 to priv_num_bins_crossed-1 loop
write(v_line, to_string(t_cov_bin_type'pos(bin_vector(i).cross_bins(j).contains)) & ' ' &
to_string(bin_vector(i).cross_bins(j).num_values) & ' ');
for k in 0 to bin_vector(i).cross_bins(j).num_values-1 loop
write(v_line, bin_vector(i).cross_bins(j).values(k));
write(v_line, ' ');
end loop;
writeline(file_handler, v_line);
end loop;
end loop;
end procedure;
begin
if priv_id /= C_DEALLOCATED_ID then
log(ID_FUNC_COV_CONFIG, get_name_prefix(VOID) & C_LOCAL_CALL, priv_scope, msg_id_panel);
-- Coverpoint config
write_value(priv_name);
write_value(priv_scope);
write_value(priv_num_bins_crossed);
write_value(integer_vector(priv_rand_gen.get_rand_seeds(VOID)));
write_value(priv_rand_transition_bin_idx);
write_value(integer_vector(priv_rand_transition_bin_value_idx));
for i in 0 to priv_num_bins_crossed-1 loop
write_value(priv_bin_sample_shift_reg(i));
end loop;
write_value(t_alert_level'pos(priv_illegal_bin_alert_level));
write_value(t_alert_level'pos(priv_bin_overlap_alert_level));
-- Covergroup config
write_value(protected_covergroup_status.get_num_valid_bins(priv_id));
write_value(protected_covergroup_status.get_num_covered_bins(priv_id));
write_value(protected_covergroup_status.get_total_bin_min_hits(priv_id));
write_value(protected_covergroup_status.get_total_bin_hits(priv_id));
write_value(protected_covergroup_status.get_total_coverage_bin_hits(priv_id));
write_value(protected_covergroup_status.get_total_goal_bin_hits(priv_id));
write_value(protected_covergroup_status.get_coverage_weight(priv_id));
write_value(protected_covergroup_status.get_bins_coverage_goal(priv_id));
write_value(protected_covergroup_status.get_hits_coverage_goal(priv_id));
write_value(protected_covergroup_status.get_covpts_coverage_goal(VOID));
-- Bin structure
write_bins(priv_bins_idx, priv_bins);
write_bins(priv_invalid_bins_idx, priv_invalid_bins);
else
alert(TB_ERROR, C_LOCAL_CALL & "=> Coverpoint has not been initialized", priv_scope);
end if;
file_close(file_handler);
DEALLOCATE(v_line);
end procedure;
procedure load_coverage_db(
constant file_name : in string;
constant report_verbosity : in t_report_verbosity := HOLES_ONLY;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel) is
constant C_LOCAL_CALL : string := "load_coverage_db(" & file_name & ")";
file file_handler : text;
variable v_open_status : file_open_status;
variable v_line : line;
variable v_value : integer;
variable v_rand_seeds : integer_vector(0 to 1);
variable v_rand_transition_bin_value_idx : integer_vector(0 to C_MAX_NUM_CROSS_BINS-1);
procedure read_value(
variable value : out integer) is
begin
readline(file_handler, v_line);
read(v_line, value);
end procedure;
procedure read_value(
variable value : out integer_vector) is
variable v_idx : natural := 0;
begin
readline(file_handler, v_line);
while v_line.all'length > 0 loop
read(v_line, value(v_idx));
v_idx := v_idx + 1;
exit when v_idx > value'length-1;
end loop;
end procedure;
procedure read_value(
variable value : out string) is
begin
readline(file_handler, v_line);
read(v_line, value);
end procedure;
--procedure read_value(
-- variable value : out boolean) is
--begin
-- readline(file_handler, v_line);
-- read(v_line, value);
--end procedure;
procedure read_bins(
constant bin_idx : in natural;
variable bin_vector : inout t_cov_bin_vector_ptr) is
variable v_contains : integer;
variable v_num_values : integer;
begin
if bin_idx > bin_vector'length-1 then
resize_bin_vector(bin_vector, bin_idx);
end if;
for i in 0 to bin_idx-1 loop
readline(file_handler, v_line);
read(v_line, bin_vector(i).name); -- read() crops the string
readline(file_handler, v_line);
read(v_line, bin_vector(i).hits);
read(v_line, bin_vector(i).min_hits);
read(v_line, bin_vector(i).rand_weight);
read(v_line, bin_vector(i).transition_mask);
for j in 0 to priv_num_bins_crossed-1 loop
readline(file_handler, v_line);
read(v_line, v_contains);
bin_vector(i).cross_bins(j).contains := t_cov_bin_type'val(v_contains);
read(v_line, v_num_values);
check_value(v_num_values <= C_FC_MAX_NUM_BIN_VALUES, TB_FAILURE, "Cannot load the " & to_string(v_num_values) & " bin values. Increase C_FC_MAX_NUM_BIN_VALUES",
priv_scope, ID_NEVER, caller_name => C_LOCAL_CALL);
bin_vector(i).cross_bins(j).num_values := v_num_values;
for k in 0 to v_num_values-1 loop
read(v_line, bin_vector(i).cross_bins(j).values(k));
end loop;
end loop;
end loop;
end procedure;
begin
log(ID_FUNC_COV_CONFIG, get_name_prefix(VOID) & C_LOCAL_CALL, priv_scope, msg_id_panel);
file_open(v_open_status, file_handler, file_name, read_mode);
if v_open_status /= open_ok then
alert(TB_WARNING, C_LOCAL_CALL & "=> Cannot open file: " & file_name, priv_scope);
return;
end if;
-- Add coverpoint to covergroup status register
if priv_id = C_DEALLOCATED_ID then
priv_id := protected_covergroup_status.add_coverpoint(VOID);
check_value(priv_id /= C_DEALLOCATED_ID, TB_FAILURE, "Number of coverpoints exceeds C_FC_MAX_NUM_COVERPOINTS.\n Increase C_FC_MAX_NUM_COVERPOINTS in adaptations package.",
priv_scope, ID_NEVER, caller_name => C_LOCAL_CALL);
else
alert(TB_WARNING, C_LOCAL_CALL & "=> " & to_string(priv_name) & " will be overwritten.", priv_scope);
end if;
-- Coverpoint config
read_value(priv_name); -- read() crops the string
set_name(priv_name);
read_value(priv_scope); -- read() crops the string
set_scope(priv_scope);
read_value(priv_num_bins_crossed);
check_value(priv_num_bins_crossed <= C_MAX_NUM_CROSS_BINS, TB_FAILURE, "Cannot load the " & to_string(priv_num_bins_crossed) & " crossed bins. Increase C_MAX_NUM_CROSS_BINS",
priv_scope, ID_NEVER, caller_name => C_LOCAL_CALL);
read_value(v_rand_seeds);
priv_rand_gen.set_rand_seeds(t_positive_vector(v_rand_seeds));
read_value(priv_rand_transition_bin_idx);
read_value(v_rand_transition_bin_value_idx);
priv_rand_transition_bin_value_idx := t_natural_vector(v_rand_transition_bin_value_idx);
for i in 0 to priv_num_bins_crossed-1 loop
read_value(priv_bin_sample_shift_reg(i));
end loop;
read_value(v_value);
priv_illegal_bin_alert_level := t_alert_level'val(v_value);
read_value(v_value);
priv_bin_overlap_alert_level := t_alert_level'val(v_value);
-- Covergroup config
protected_covergroup_status.set_name(priv_id, priv_name); -- Previously read from the file
read_value(v_value);
protected_covergroup_status.set_num_valid_bins(priv_id, v_value);
read_value(v_value);
protected_covergroup_status.set_num_covered_bins(priv_id, v_value);
read_value(v_value);
protected_covergroup_status.set_total_bin_min_hits(priv_id, v_value);
read_value(v_value);
protected_covergroup_status.set_total_bin_hits(priv_id, v_value);
read_value(v_value);
protected_covergroup_status.set_total_coverage_bin_hits(priv_id, v_value);
read_value(v_value);
protected_covergroup_status.set_total_goal_bin_hits(priv_id, v_value);
read_value(v_value);
protected_covergroup_status.set_coverage_weight(priv_id, v_value);
read_value(v_value);
protected_covergroup_status.set_bins_coverage_goal(priv_id, v_value);
read_value(v_value);
protected_covergroup_status.set_hits_coverage_goal(priv_id, v_value);
read_value(v_value);
protected_covergroup_status.set_covpts_coverage_goal(v_value);
-- Bin structure
read_value(priv_bins_idx);
read_bins(priv_bins_idx, priv_bins);
read_value(priv_invalid_bins_idx);
read_bins(priv_invalid_bins_idx, priv_invalid_bins);
file_close(file_handler);
DEALLOCATE(v_line);
report_coverage(report_verbosity);
end procedure;
procedure clear_coverage(
constant VOID : in t_void) is
begin
clear_coverage(shared_msg_id_panel);
end procedure;
procedure clear_coverage(
constant msg_id_panel : in t_msg_id_panel) is
constant C_LOCAL_CALL : string := "clear_coverage()";
begin
log(ID_FUNC_COV_CONFIG, get_name_prefix(VOID) & C_LOCAL_CALL, priv_scope, msg_id_panel);
for i in 0 to priv_bins_idx-1 loop
priv_bins(i).hits := 0;
priv_bins(i).transition_mask := (others => '0');
end loop;
for i in 0 to priv_invalid_bins_idx-1 loop
priv_invalid_bins(i).hits := 0;
priv_invalid_bins(i).transition_mask := (others => '0');
end loop;
priv_rand_transition_bin_idx := C_UNINITIALIZED;
priv_rand_transition_bin_value_idx := (others => 0);
priv_bin_sample_shift_reg := (others => (others => 0));
if priv_id /= C_DEALLOCATED_ID then
protected_covergroup_status.set_num_covered_bins(priv_id, 0);
protected_covergroup_status.set_total_coverage_bin_hits(priv_id, 0);
protected_covergroup_status.set_total_goal_bin_hits(priv_id, 0);
protected_covergroup_status.set_total_bin_hits(priv_id, 0);
end if;
end procedure;
procedure set_num_allocated_bins(
constant value : in positive;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel) is
constant C_LOCAL_CALL : string := "set_num_allocated_bins(" & to_string(value) & ")";
begin
initialize_coverpoint(C_LOCAL_CALL);
log(ID_FUNC_COV_CONFIG, get_name_prefix(VOID) & C_LOCAL_CALL, priv_scope, msg_id_panel);
if value >= priv_bins_idx then
resize_bin_vector(priv_bins, value);
else
alert(TB_ERROR, C_LOCAL_CALL & "=> Cannot set the allocated size to a value smaller than the actual number of bins", priv_scope);
end if;
end procedure;
procedure set_num_allocated_bins_increment(
constant value : in positive) is
begin
priv_num_bins_allocated_increment := value;
end procedure;
procedure delete_coverpoint(
constant VOID : in t_void) is
begin
delete_coverpoint(shared_msg_id_panel);
end procedure;
procedure delete_coverpoint(
constant msg_id_panel : in t_msg_id_panel) is
constant C_LOCAL_CALL : string := "delete_coverpoint()";
begin
log(ID_FUNC_COV_CONFIG, get_name_prefix(VOID) & C_LOCAL_CALL, priv_scope, msg_id_panel);
if priv_id /= C_DEALLOCATED_ID then
protected_covergroup_status.remove_coverpoint(priv_id);
end if;
priv_id := C_DEALLOCATED_ID;
priv_name := fill_string(NUL, C_FC_MAX_NAME_LENGTH);
priv_scope := C_TB_SCOPE_DEFAULT & fill_string(NUL, C_LOG_SCOPE_WIDTH-C_TB_SCOPE_DEFAULT'length);
DEALLOCATE(priv_bins);
priv_bins := new t_cov_bin_vector(0 to C_FC_DEFAULT_INITIAL_NUM_BINS_ALLOCATED-1);
priv_bins_idx := 0;
DEALLOCATE(priv_invalid_bins);
priv_invalid_bins := new t_cov_bin_vector(0 to C_FC_DEFAULT_INITIAL_NUM_BINS_ALLOCATED-1);
priv_invalid_bins_idx := 0;
priv_num_bins_crossed := C_UNINITIALIZED;
priv_rand_gen.set_rand_seeds(C_RAND_INIT_SEED_1, C_RAND_INIT_SEED_2);
priv_rand_transition_bin_idx := C_UNINITIALIZED;
priv_rand_transition_bin_value_idx := (others => 0);
priv_bin_sample_shift_reg := (others => (others => 0));
priv_illegal_bin_alert_level := ERROR;
priv_bin_overlap_alert_level := NO_ALERT;
priv_num_bins_allocated_increment := C_FC_DEFAULT_NUM_BINS_ALLOCATED_INCREMENT;
end procedure;
-- Returns the number of bins crossed in the coverpoint
impure function get_num_bins_crossed(
constant VOID : t_void)
return integer is
begin
return priv_num_bins_crossed;
end function;
-- Returns the number of valid bins in the coverpoint
impure function get_num_valid_bins(
constant VOID : t_void)
return natural is
begin
return priv_bins_idx;
end function;
-- Returns the number of illegal and ignore bins in the coverpoint
impure function get_num_invalid_bins(
constant VOID : t_void)
return natural is
begin
return priv_invalid_bins_idx;
end function;
-- Returns a valid bin in the coverpoint
impure function get_valid_bin(
constant bin_idx : natural)
return t_cov_bin is
constant C_LOCAL_CALL : string := "get_valid_bin(" & to_string(bin_idx) & ")";
begin
check_value(bin_idx < priv_bins'length, TB_ERROR, "bin_idx is out of range", priv_scope, ID_NEVER, caller_name => C_LOCAL_CALL);
return priv_bins(bin_idx);
end function;
-- Returns an invalid bin in the coverpoint
impure function get_invalid_bin(
constant bin_idx : natural)
return t_cov_bin is
constant C_LOCAL_CALL : string := "get_invalid_bin(" & to_string(bin_idx) & ")";
begin
check_value(bin_idx < priv_invalid_bins'length, TB_ERROR, "bin_idx is out of range", priv_scope, ID_NEVER, caller_name => C_LOCAL_CALL);
return priv_invalid_bins(bin_idx);
end function;
-- Returns a vector with the valid bins in the coverpoint
impure function get_valid_bins(
constant VOID : t_void)
return t_cov_bin_vector is
begin
return priv_bins(0 to priv_bins_idx-1);
end function;
-- Returns a vector with the illegal and ignore bins in the coverpoint
impure function get_invalid_bins(
constant VOID : t_void)
return t_cov_bin_vector is
begin
return priv_invalid_bins(0 to priv_invalid_bins_idx-1);
end function;
-- Returns a string with all the bins in the coverpoint including illegal, ignore and cross
-- Duplicate bins are not printed since they are assumed to be the result of a cross
impure function get_all_bins_string(
constant VOID : t_void)
return string is
variable v_new_bin_array : t_new_bin_array(0 to priv_num_bins_crossed-1);
variable v_line : line;
variable v_num_bins : natural := 0;
impure function return_and_deallocate return string is
constant ret : string := v_line.all;
begin
DEALLOCATE(v_line);
return ret;
end function;
begin
if priv_bins_idx = 0 and priv_invalid_bins_idx = 0 then
return "";
end if;
for cross in v_new_bin_array'range loop
for i in 0 to priv_bins_idx-1 loop
if not find_duplicate_bin(priv_bins.all, i, cross) then
v_new_bin_array(cross).bin_vector(v_num_bins).contains := priv_bins(i).cross_bins(cross).contains;
v_new_bin_array(cross).bin_vector(v_num_bins).values := priv_bins(i).cross_bins(cross).values;
v_new_bin_array(cross).bin_vector(v_num_bins).num_values := priv_bins(i).cross_bins(cross).num_values;
v_num_bins := v_num_bins + 1;
end if;
end loop;
for i in 0 to priv_invalid_bins_idx-1 loop
if not find_duplicate_bin(priv_invalid_bins.all, i, cross) then
v_new_bin_array(cross).bin_vector(v_num_bins).contains := priv_invalid_bins(i).cross_bins(cross).contains;
v_new_bin_array(cross).bin_vector(v_num_bins).values := priv_invalid_bins(i).cross_bins(cross).values;
v_new_bin_array(cross).bin_vector(v_num_bins).num_values := priv_invalid_bins(i).cross_bins(cross).num_values;
v_num_bins := v_num_bins + 1;
end if;
end loop;
v_new_bin_array(cross).num_bins := v_num_bins;
v_num_bins := 0;
write(v_line, get_bin_array_values(v_new_bin_array(cross to cross)));
if cross < v_new_bin_array'length-1 then
write(v_line, string'(" x "));
end if;
end loop;
return return_and_deallocate;
end function;
------------------------------------------------------------
-- Add bins
------------------------------------------------------------
procedure add_bins(
constant bin : in t_new_bin_array;
constant min_hits : in positive;
constant rand_weight : in natural;
constant bin_name : in string := "";
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant ext_proc_call : in string := "") is
constant C_LOCAL_CALL : string := "add_bins(" & get_proc_calls(bin) & ", min_hits:" & to_string(min_hits) &
", rand_weight:" & to_string(rand_weight) & ", """ & bin_name & """)";
constant C_NUM_CROSS_BINS : natural := 1;
constant C_USE_RAND_WEIGHT : boolean := ext_proc_call = ""; -- When procedure is called from the sequencer
variable v_proc_call : line;
variable v_bin_array : t_new_bin_array(0 to C_NUM_CROSS_BINS-1);
variable v_idx_reg : integer_vector(0 to C_NUM_CROSS_BINS-1);
begin
create_proc_call(C_LOCAL_CALL, ext_proc_call, v_proc_call);
check_num_bins_crossed(C_NUM_CROSS_BINS, v_proc_call.all);
log(ID_FUNC_COV_BINS, get_name_prefix(VOID) & v_proc_call.all, priv_scope, msg_id_panel);
log(ID_FUNC_COV_BINS_INFO, get_name_prefix(VOID) & "Adding bins: " & get_bin_array_values(bin) & ", min_hits:" & to_string(min_hits) &
", rand_weight:" & return_string1_if_true_otherwise_string2(to_string(rand_weight), to_string(min_hits), C_USE_RAND_WEIGHT) &
", """ & bin_name & """", priv_scope, msg_id_panel);
-- Copy the bins into an array and use a recursive procedure to add them to the list
create_bin_array(v_proc_call.all, v_bin_array, bin);
add_bins_recursive(v_bin_array, 0, v_idx_reg, min_hits, rand_weight, C_USE_RAND_WEIGHT, bin_name);
DEALLOCATE(v_proc_call);
end procedure;
procedure add_bins(
constant bin : in t_new_bin_array;
constant min_hits : in positive;
constant bin_name : in string := "";
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel) is
constant C_LOCAL_CALL : string := "add_bins(" & get_proc_calls(bin) & ", min_hits:" & to_string(min_hits) &
", """ & bin_name & """)";
begin
add_bins(bin, min_hits, 1, bin_name, msg_id_panel, C_LOCAL_CALL);
end procedure;
procedure add_bins(
constant bin : in t_new_bin_array;
constant bin_name : in string := "";
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel) is
constant C_LOCAL_CALL : string := "add_bins(" & get_proc_calls(bin) & ", """ & bin_name & """)";
begin
add_bins(bin, 1, 1, bin_name, msg_id_panel, C_LOCAL_CALL);
end procedure;
------------------------------------------------------------
-- Add cross (2 bins)
------------------------------------------------------------
procedure add_cross(
constant bin1 : in t_new_bin_array;
constant bin2 : in t_new_bin_array;
constant min_hits : in positive;
constant rand_weight : in natural;
constant bin_name : in string := "";
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant ext_proc_call : in string := "") is
constant C_LOCAL_CALL : string := "add_cross(" & get_proc_calls(bin1) & ", " & get_proc_calls(bin2) &
", min_hits:" & to_string(min_hits) & ", rand_weight:" & to_string(rand_weight) & ", """ & bin_name & """)";
constant C_NUM_CROSS_BINS : natural := 2;
constant C_USE_RAND_WEIGHT : boolean := ext_proc_call = ""; -- When procedure is called from the sequencer
variable v_proc_call : line;
variable v_bin_array : t_new_bin_array(0 to C_NUM_CROSS_BINS-1);
variable v_idx_reg : integer_vector(0 to C_NUM_CROSS_BINS-1);
begin
create_proc_call(C_LOCAL_CALL, ext_proc_call, v_proc_call);
check_num_bins_crossed(C_NUM_CROSS_BINS, v_proc_call.all);
log(ID_FUNC_COV_BINS, get_name_prefix(VOID) & v_proc_call.all, priv_scope, msg_id_panel);
log(ID_FUNC_COV_BINS_INFO, get_name_prefix(VOID) & "Adding cross: " & get_bin_array_values(bin1) & " x " & get_bin_array_values(bin2) &
", min_hits:" & to_string(min_hits) & ", rand_weight:" & return_string1_if_true_otherwise_string2(to_string(rand_weight), to_string(min_hits), C_USE_RAND_WEIGHT) &
", """ & bin_name & """", priv_scope, msg_id_panel);
-- Copy the bins into an array and use a recursive procedure to add them to the list
create_bin_array(v_proc_call.all, v_bin_array, bin1, bin2);
add_bins_recursive(v_bin_array, 0, v_idx_reg, min_hits, rand_weight, C_USE_RAND_WEIGHT, bin_name);
DEALLOCATE(v_proc_call);
end procedure;
procedure add_cross(
constant bin1 : in t_new_bin_array;
constant bin2 : in t_new_bin_array;
constant min_hits : in positive;
constant bin_name : in string := "";
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel) is
constant C_LOCAL_CALL : string := "add_cross(" & get_proc_calls(bin1) & ", " & get_proc_calls(bin2) &
", min_hits:" & to_string(min_hits) & ", """ & bin_name & """)";
begin
add_cross(bin1, bin2, min_hits, 1, bin_name, msg_id_panel, C_LOCAL_CALL);
end procedure;
procedure add_cross(
constant bin1 : in t_new_bin_array;
constant bin2 : in t_new_bin_array;
constant bin_name : in string := "";
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel) is
constant C_LOCAL_CALL : string := "add_cross(" & get_proc_calls(bin1) & ", " & get_proc_calls(bin2) &
", """ & bin_name & """)";
begin
add_cross(bin1, bin2, 1, 1, bin_name, msg_id_panel, C_LOCAL_CALL);
end procedure;
------------------------------------------------------------
-- Add cross (3 bins)
------------------------------------------------------------
procedure add_cross(
constant bin1 : in t_new_bin_array;
constant bin2 : in t_new_bin_array;
constant bin3 : in t_new_bin_array;
constant min_hits : in positive;
constant rand_weight : in natural;
constant bin_name : in string := "";
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant ext_proc_call : in string := "") is
constant C_LOCAL_CALL : string := "add_cross(" & get_proc_calls(bin1) & ", " & get_proc_calls(bin2) & ", " & get_proc_calls(bin3) &
", min_hits:" & to_string(min_hits) & ", rand_weight:" & to_string(rand_weight) & ", """ & bin_name & """)";
constant C_NUM_CROSS_BINS : natural := 3;
constant C_USE_RAND_WEIGHT : boolean := ext_proc_call = ""; -- When procedure is called from the sequencer
variable v_proc_call : line;
variable v_bin_array : t_new_bin_array(0 to C_NUM_CROSS_BINS-1);
variable v_idx_reg : integer_vector(0 to C_NUM_CROSS_BINS-1);
begin
create_proc_call(C_LOCAL_CALL, ext_proc_call, v_proc_call);
check_num_bins_crossed(C_NUM_CROSS_BINS, v_proc_call.all);
log(ID_FUNC_COV_BINS, get_name_prefix(VOID) & v_proc_call.all, priv_scope, msg_id_panel);
log(ID_FUNC_COV_BINS_INFO, get_name_prefix(VOID) & "Adding cross: " & get_bin_array_values(bin1) & " x " & get_bin_array_values(bin2) & " x " & get_bin_array_values(bin3) &
", min_hits:" & to_string(min_hits) & ", rand_weight:" & return_string1_if_true_otherwise_string2(to_string(rand_weight), to_string(min_hits), C_USE_RAND_WEIGHT) &
", """ & bin_name & """", priv_scope, msg_id_panel);
-- Copy the bins into an array and use a recursive procedure to add them to the list
create_bin_array(v_proc_call.all, v_bin_array, bin1, bin2, bin3);
add_bins_recursive(v_bin_array, 0, v_idx_reg, min_hits, rand_weight, C_USE_RAND_WEIGHT, bin_name);
DEALLOCATE(v_proc_call);
end procedure;
procedure add_cross(
constant bin1 : in t_new_bin_array;
constant bin2 : in t_new_bin_array;
constant bin3 : in t_new_bin_array;
constant min_hits : in positive;
constant bin_name : in string := "";
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel) is
constant C_LOCAL_CALL : string := "add_cross(" & get_proc_calls(bin1) & ", " & get_proc_calls(bin2) & ", " & get_proc_calls(bin3) &
", min_hits:" & to_string(min_hits) & ", """ & bin_name & """)";
begin
add_cross(bin1, bin2, bin3, min_hits, 1, bin_name, msg_id_panel, C_LOCAL_CALL);
end procedure;
procedure add_cross(
constant bin1 : in t_new_bin_array;
constant bin2 : in t_new_bin_array;
constant bin3 : in t_new_bin_array;
constant bin_name : in string := "";
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel) is
constant C_LOCAL_CALL : string := "add_cross(" & get_proc_calls(bin1) & ", " & get_proc_calls(bin2) & ", " & get_proc_calls(bin3) &
", """ & bin_name & """)";
begin
add_cross(bin1, bin2, bin3, 1, 1, bin_name, msg_id_panel, C_LOCAL_CALL);
end procedure;
------------------------------------------------------------
-- Add cross (4 bins)
------------------------------------------------------------
procedure add_cross(
constant bin1 : in t_new_bin_array;
constant bin2 : in t_new_bin_array;
constant bin3 : in t_new_bin_array;
constant bin4 : in t_new_bin_array;
constant min_hits : in positive;
constant rand_weight : in natural;
constant bin_name : in string := "";
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant ext_proc_call : in string := "") is
constant C_LOCAL_CALL : string := "add_cross(" & get_proc_calls(bin1) & ", " & get_proc_calls(bin2) & ", " & get_proc_calls(bin3) &
", " & get_proc_calls(bin4) & ", min_hits:" & to_string(min_hits) & ", rand_weight:" & to_string(rand_weight) & ", """ & bin_name & """)";
constant C_NUM_CROSS_BINS : natural := 4;
constant C_USE_RAND_WEIGHT : boolean := ext_proc_call = ""; -- When procedure is called from the sequencer
variable v_proc_call : line;
variable v_bin_array : t_new_bin_array(0 to C_NUM_CROSS_BINS-1);
variable v_idx_reg : integer_vector(0 to C_NUM_CROSS_BINS-1);
begin
create_proc_call(C_LOCAL_CALL, ext_proc_call, v_proc_call);
check_num_bins_crossed(C_NUM_CROSS_BINS, v_proc_call.all);
log(ID_FUNC_COV_BINS, get_name_prefix(VOID) & v_proc_call.all, priv_scope, msg_id_panel);
log(ID_FUNC_COV_BINS_INFO, get_name_prefix(VOID) & "Adding cross: " & get_bin_array_values(bin1) & " x " & get_bin_array_values(bin2) & " x " & get_bin_array_values(bin3) &
" x " & get_bin_array_values(bin4) &
", min_hits:" & to_string(min_hits) & ", rand_weight:" & return_string1_if_true_otherwise_string2(to_string(rand_weight), to_string(min_hits), C_USE_RAND_WEIGHT) &
", """ & bin_name & """", priv_scope, msg_id_panel);
-- Copy the bins into an array and use a recursive procedure to add them to the list
create_bin_array(v_proc_call.all, v_bin_array, bin1, bin2, bin3, bin4);
add_bins_recursive(v_bin_array, 0, v_idx_reg, min_hits, rand_weight, C_USE_RAND_WEIGHT, bin_name);
DEALLOCATE(v_proc_call);
end procedure;
procedure add_cross(
constant bin1 : in t_new_bin_array;
constant bin2 : in t_new_bin_array;
constant bin3 : in t_new_bin_array;
constant bin4 : in t_new_bin_array;
constant min_hits : in positive;
constant bin_name : in string := "";
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel) is
constant C_LOCAL_CALL : string := "add_cross(" & get_proc_calls(bin1) & ", " & get_proc_calls(bin2) & ", " & get_proc_calls(bin3) &
", " & get_proc_calls(bin4) & ", min_hits:" & to_string(min_hits) & ", """ & bin_name & """)";
begin
add_cross(bin1, bin2, bin3, bin4, min_hits, 1, bin_name, msg_id_panel, C_LOCAL_CALL);
end procedure;
procedure add_cross(
constant bin1 : in t_new_bin_array;
constant bin2 : in t_new_bin_array;
constant bin3 : in t_new_bin_array;
constant bin4 : in t_new_bin_array;
constant bin_name : in string := "";
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel) is
constant C_LOCAL_CALL : string := "add_cross(" & get_proc_calls(bin1) & ", " & get_proc_calls(bin2) & ", " & get_proc_calls(bin3) &
", " & get_proc_calls(bin4) & ", """ & bin_name & """)";
begin
add_cross(bin1, bin2, bin3, bin4, 1, 1, bin_name, msg_id_panel, C_LOCAL_CALL);
end procedure;
------------------------------------------------------------
-- Add cross (5 bins)
------------------------------------------------------------
procedure add_cross(
constant bin1 : in t_new_bin_array;
constant bin2 : in t_new_bin_array;
constant bin3 : in t_new_bin_array;
constant bin4 : in t_new_bin_array;
constant bin5 : in t_new_bin_array;
constant min_hits : in positive;
constant rand_weight : in natural;
constant bin_name : in string := "";
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant ext_proc_call : in string := "") is
constant C_LOCAL_CALL : string := "add_cross(" & get_proc_calls(bin1) & ", " & get_proc_calls(bin2) & ", " & get_proc_calls(bin3) &
", " & get_proc_calls(bin4) & ", " & get_proc_calls(bin5) & ", min_hits:" & to_string(min_hits) & ", rand_weight:" & to_string(rand_weight) & ", """ & bin_name & """)";
constant C_NUM_CROSS_BINS : natural := 5;
constant C_USE_RAND_WEIGHT : boolean := ext_proc_call = ""; -- When procedure is called from the sequencer
variable v_proc_call : line;
variable v_bin_array : t_new_bin_array(0 to C_NUM_CROSS_BINS-1);
variable v_idx_reg : integer_vector(0 to C_NUM_CROSS_BINS-1);
begin
create_proc_call(C_LOCAL_CALL, ext_proc_call, v_proc_call);
check_num_bins_crossed(C_NUM_CROSS_BINS, v_proc_call.all);
log(ID_FUNC_COV_BINS, get_name_prefix(VOID) & v_proc_call.all, priv_scope, msg_id_panel);
log(ID_FUNC_COV_BINS_INFO, get_name_prefix(VOID) & "Adding cross: " & get_bin_array_values(bin1) & " x " & get_bin_array_values(bin2) & " x " & get_bin_array_values(bin3) &
" x " & get_bin_array_values(bin4) & " x " & get_bin_array_values(bin5) &
", min_hits:" & to_string(min_hits) & ", rand_weight:" & return_string1_if_true_otherwise_string2(to_string(rand_weight), to_string(min_hits), C_USE_RAND_WEIGHT) &
", """ & bin_name & """", priv_scope, msg_id_panel);
-- Copy the bins into an array and use a recursive procedure to add them to the list
create_bin_array(v_proc_call.all, v_bin_array, bin1, bin2, bin3, bin4, bin5);
add_bins_recursive(v_bin_array, 0, v_idx_reg, min_hits, rand_weight, C_USE_RAND_WEIGHT, bin_name);
DEALLOCATE(v_proc_call);
end procedure;
procedure add_cross(
constant bin1 : in t_new_bin_array;
constant bin2 : in t_new_bin_array;
constant bin3 : in t_new_bin_array;
constant bin4 : in t_new_bin_array;
constant bin5 : in t_new_bin_array;
constant min_hits : in positive;
constant bin_name : in string := "";
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel) is
constant C_LOCAL_CALL : string := "add_cross(" & get_proc_calls(bin1) & ", " & get_proc_calls(bin2) & ", " & get_proc_calls(bin3) &
", " & get_proc_calls(bin4) & ", " & get_proc_calls(bin5) & ", min_hits:" & to_string(min_hits) & ", """ & bin_name & """)";
begin
add_cross(bin1, bin2, bin3, bin4, bin5, min_hits, 1, bin_name, msg_id_panel, C_LOCAL_CALL);
end procedure;
procedure add_cross(
constant bin1 : in t_new_bin_array;
constant bin2 : in t_new_bin_array;
constant bin3 : in t_new_bin_array;
constant bin4 : in t_new_bin_array;
constant bin5 : in t_new_bin_array;
constant bin_name : in string := "";
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel) is
constant C_LOCAL_CALL : string := "add_cross(" & get_proc_calls(bin1) & ", " & get_proc_calls(bin2) & ", " & get_proc_calls(bin3) &
", " & get_proc_calls(bin4) & ", " & get_proc_calls(bin5) & ", """ & bin_name & """)";
begin
add_cross(bin1, bin2, bin3, bin4, bin5, 1, 1, bin_name, msg_id_panel, C_LOCAL_CALL);
end procedure;
------------------------------------------------------------
-- Add cross (2 coverpoints)
------------------------------------------------------------
procedure add_cross(
variable coverpoint1 : inout t_coverpoint;
variable coverpoint2 : inout t_coverpoint;
constant min_hits : in positive;
constant rand_weight : in natural;
constant bin_name : in string := "";
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant ext_proc_call : in string := "") is
constant C_LOCAL_CALL : string := "add_cross(" & coverpoint1.get_name(VOID) & ", " & coverpoint2.get_name(VOID) &
", min_hits:" & to_string(min_hits) & ", rand_weight:" & to_string(rand_weight) & ", """ & bin_name & """)";
constant C_NUM_CROSS_BINS : integer := coverpoint1.get_num_bins_crossed(VOID) + coverpoint2.get_num_bins_crossed(VOID);
constant C_USE_RAND_WEIGHT : boolean := ext_proc_call = ""; -- When procedure is called from the sequencer
variable v_proc_call : line;
variable v_bin_array : t_new_bin_array(0 to C_NUM_CROSS_BINS-1);
variable v_idx_reg : integer_vector(0 to C_NUM_CROSS_BINS-1);
begin
create_proc_call(C_LOCAL_CALL, ext_proc_call, v_proc_call);
check_num_bins_crossed(C_NUM_CROSS_BINS, v_proc_call.all, coverpoint1.get_num_bins_crossed(VOID), coverpoint2.get_num_bins_crossed(VOID));
log(ID_FUNC_COV_BINS, get_name_prefix(VOID) & v_proc_call.all, priv_scope, msg_id_panel);
log(ID_FUNC_COV_BINS_INFO, get_name_prefix(VOID) & "Adding cross: " & coverpoint1.get_all_bins_string(VOID) & " x " & coverpoint2.get_all_bins_string(VOID) &
", min_hits:" & to_string(min_hits) & ", rand_weight:" & return_string1_if_true_otherwise_string2(to_string(rand_weight), to_string(min_hits), C_USE_RAND_WEIGHT) &
", """ & bin_name & """", priv_scope, msg_id_panel);
-- Copy the bins into an array and use a recursive procedure to add them to the list
create_bin_array(v_bin_array, coverpoint1, coverpoint2);
add_bins_recursive(v_bin_array, 0, v_idx_reg, min_hits, rand_weight, C_USE_RAND_WEIGHT, bin_name);
DEALLOCATE(v_proc_call);
end procedure;
procedure add_cross(
variable coverpoint1 : inout t_coverpoint;
variable coverpoint2 : inout t_coverpoint;
constant min_hits : in positive;
constant bin_name : in string := "";
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel) is
constant C_LOCAL_CALL : string := "add_cross(" & coverpoint1.get_name(VOID) & ", " & coverpoint2.get_name(VOID) &
", min_hits:" & to_string(min_hits) & ", """ & bin_name & """)";
begin
add_cross(coverpoint1, coverpoint2, min_hits, 1, bin_name, msg_id_panel, C_LOCAL_CALL);
end procedure;
procedure add_cross(
variable coverpoint1 : inout t_coverpoint;
variable coverpoint2 : inout t_coverpoint;
constant bin_name : in string := "";
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel) is
constant C_LOCAL_CALL : string := "add_cross(" & coverpoint1.get_name(VOID) & ", " & coverpoint2.get_name(VOID) &
", """ & bin_name & """)";
begin
add_cross(coverpoint1, coverpoint2, 1, 1, bin_name, msg_id_panel, C_LOCAL_CALL);
end procedure;
------------------------------------------------------------
-- Add cross (3 coverpoints)
------------------------------------------------------------
procedure add_cross(
variable coverpoint1 : inout t_coverpoint;
variable coverpoint2 : inout t_coverpoint;
variable coverpoint3 : inout t_coverpoint;
constant min_hits : in positive;
constant rand_weight : in natural;
constant bin_name : in string := "";
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant ext_proc_call : in string := "") is
constant C_LOCAL_CALL : string := "add_cross(" & coverpoint1.get_name(VOID) & ", " & coverpoint2.get_name(VOID) & ", " &
coverpoint3.get_name(VOID) & ", min_hits:" & to_string(min_hits) & ", rand_weight:" & to_string(rand_weight) & ", """ & bin_name & """)";
constant C_NUM_CROSS_BINS : integer := coverpoint1.get_num_bins_crossed(VOID) + coverpoint2.get_num_bins_crossed(VOID) +
coverpoint3.get_num_bins_crossed(VOID);
constant C_USE_RAND_WEIGHT : boolean := ext_proc_call = ""; -- When procedure is called from the sequencer
variable v_proc_call : line;
variable v_bin_array : t_new_bin_array(0 to C_NUM_CROSS_BINS-1);
variable v_idx_reg : integer_vector(0 to C_NUM_CROSS_BINS-1);
begin
create_proc_call(C_LOCAL_CALL, ext_proc_call, v_proc_call);
check_num_bins_crossed(C_NUM_CROSS_BINS, v_proc_call.all, coverpoint1.get_num_bins_crossed(VOID), coverpoint2.get_num_bins_crossed(VOID),
coverpoint3.get_num_bins_crossed(VOID));
log(ID_FUNC_COV_BINS, get_name_prefix(VOID) & v_proc_call.all, priv_scope, msg_id_panel);
log(ID_FUNC_COV_BINS_INFO, get_name_prefix(VOID) & "Adding cross: " & coverpoint1.get_all_bins_string(VOID) & " x " & coverpoint2.get_all_bins_string(VOID) &
" x " & coverpoint3.get_all_bins_string(VOID) &
", min_hits:" & to_string(min_hits) & ", rand_weight:" & return_string1_if_true_otherwise_string2(to_string(rand_weight), to_string(min_hits), C_USE_RAND_WEIGHT) &
", """ & bin_name & """", priv_scope, msg_id_panel);
-- Copy the bins into an array and use a recursive procedure to add them to the list
create_bin_array(v_bin_array, coverpoint1, coverpoint2, coverpoint3);
add_bins_recursive(v_bin_array, 0, v_idx_reg, min_hits, rand_weight, C_USE_RAND_WEIGHT, bin_name);
DEALLOCATE(v_proc_call);
end procedure;
procedure add_cross(
variable coverpoint1 : inout t_coverpoint;
variable coverpoint2 : inout t_coverpoint;
variable coverpoint3 : inout t_coverpoint;
constant min_hits : in positive;
constant bin_name : in string := "";
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel) is
constant C_LOCAL_CALL : string := "add_cross(" & coverpoint1.get_name(VOID) & ", " & coverpoint2.get_name(VOID) & ", " &
coverpoint3.get_name(VOID) & ", min_hits:" & to_string(min_hits) & ", """ & bin_name & """)";
begin
add_cross(coverpoint1, coverpoint2, coverpoint3, min_hits, 1, bin_name, msg_id_panel, C_LOCAL_CALL);
end procedure;
procedure add_cross(
variable coverpoint1 : inout t_coverpoint;
variable coverpoint2 : inout t_coverpoint;
variable coverpoint3 : inout t_coverpoint;
constant bin_name : in string := "";
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel) is
constant C_LOCAL_CALL : string := "add_cross(" & coverpoint1.get_name(VOID) & ", " & coverpoint2.get_name(VOID) & ", " &
coverpoint3.get_name(VOID) & ", """ & bin_name & """)";
begin
add_cross(coverpoint1, coverpoint2, coverpoint3, 1, 1, bin_name, msg_id_panel, C_LOCAL_CALL);
end procedure;
------------------------------------------------------------
-- Add cross (4 coverpoints)
------------------------------------------------------------
procedure add_cross(
variable coverpoint1 : inout t_coverpoint;
variable coverpoint2 : inout t_coverpoint;
variable coverpoint3 : inout t_coverpoint;
variable coverpoint4 : inout t_coverpoint;
constant min_hits : in positive;
constant rand_weight : in natural;
constant bin_name : in string := "";
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant ext_proc_call : in string := "") is
constant C_LOCAL_CALL : string := "add_cross(" & coverpoint1.get_name(VOID) & ", " & coverpoint2.get_name(VOID) & ", " &
coverpoint3.get_name(VOID) & ", " & coverpoint4.get_name(VOID) &
", min_hits:" & to_string(min_hits) & ", rand_weight:" & to_string(rand_weight) & ", """ & bin_name & """)";
constant C_NUM_CROSS_BINS : integer := coverpoint1.get_num_bins_crossed(VOID) + coverpoint2.get_num_bins_crossed(VOID) +
coverpoint3.get_num_bins_crossed(VOID) + coverpoint4.get_num_bins_crossed(VOID);
constant C_USE_RAND_WEIGHT : boolean := ext_proc_call = ""; -- When procedure is called from the sequencer
variable v_proc_call : line;
variable v_bin_array : t_new_bin_array(0 to C_NUM_CROSS_BINS-1);
variable v_idx_reg : integer_vector(0 to C_NUM_CROSS_BINS-1);
begin
create_proc_call(C_LOCAL_CALL, ext_proc_call, v_proc_call);
check_num_bins_crossed(C_NUM_CROSS_BINS, v_proc_call.all, coverpoint1.get_num_bins_crossed(VOID), coverpoint2.get_num_bins_crossed(VOID),
coverpoint3.get_num_bins_crossed(VOID), coverpoint4.get_num_bins_crossed(VOID));
log(ID_FUNC_COV_BINS, get_name_prefix(VOID) & v_proc_call.all, priv_scope, msg_id_panel);
log(ID_FUNC_COV_BINS_INFO, get_name_prefix(VOID) & "Adding cross: " & coverpoint1.get_all_bins_string(VOID) & " x " & coverpoint2.get_all_bins_string(VOID) &
" x " & coverpoint3.get_all_bins_string(VOID) & " x " & coverpoint4.get_all_bins_string(VOID) &
", min_hits:" & to_string(min_hits) & ", rand_weight:" & return_string1_if_true_otherwise_string2(to_string(rand_weight), to_string(min_hits), C_USE_RAND_WEIGHT) &
", """ & bin_name & """", priv_scope, msg_id_panel);
-- Copy the bins into an array and use a recursive procedure to add them to the list
create_bin_array(v_bin_array, coverpoint1, coverpoint2, coverpoint3, coverpoint4);
add_bins_recursive(v_bin_array, 0, v_idx_reg, min_hits, rand_weight, C_USE_RAND_WEIGHT, bin_name);
DEALLOCATE(v_proc_call);
end procedure;
procedure add_cross(
variable coverpoint1 : inout t_coverpoint;
variable coverpoint2 : inout t_coverpoint;
variable coverpoint3 : inout t_coverpoint;
variable coverpoint4 : inout t_coverpoint;
constant min_hits : in positive;
constant bin_name : in string := "";
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel) is
constant C_LOCAL_CALL : string := "add_cross(" & coverpoint1.get_name(VOID) & ", " & coverpoint2.get_name(VOID) & ", " &
coverpoint3.get_name(VOID) & ", " & coverpoint4.get_name(VOID) & ", min_hits:" & to_string(min_hits) & ", """ & bin_name & """)";
begin
add_cross(coverpoint1, coverpoint2, coverpoint3, coverpoint4, min_hits, 1, bin_name, msg_id_panel, C_LOCAL_CALL);
end procedure;
procedure add_cross(
variable coverpoint1 : inout t_coverpoint;
variable coverpoint2 : inout t_coverpoint;
variable coverpoint3 : inout t_coverpoint;
variable coverpoint4 : inout t_coverpoint;
constant bin_name : in string := "";
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel) is
constant C_LOCAL_CALL : string := "add_cross(" & coverpoint1.get_name(VOID) & ", " & coverpoint2.get_name(VOID) & ", " &
coverpoint3.get_name(VOID) & ", " & coverpoint4.get_name(VOID) & ", """ & bin_name & """)";
begin
add_cross(coverpoint1, coverpoint2, coverpoint3, coverpoint4, 1, 1, bin_name, msg_id_panel, C_LOCAL_CALL);
end procedure;
------------------------------------------------------------
-- Add cross (5 coverpoints)
------------------------------------------------------------
procedure add_cross(
variable coverpoint1 : inout t_coverpoint;
variable coverpoint2 : inout t_coverpoint;
variable coverpoint3 : inout t_coverpoint;
variable coverpoint4 : inout t_coverpoint;
variable coverpoint5 : inout t_coverpoint;
constant min_hits : in positive;
constant rand_weight : in natural;
constant bin_name : in string := "";
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant ext_proc_call : in string := "") is
constant C_LOCAL_CALL : string := "add_cross(" & coverpoint1.get_name(VOID) & ", " & coverpoint2.get_name(VOID) & ", " &
coverpoint3.get_name(VOID) & ", " & coverpoint4.get_name(VOID) & ", " & coverpoint5.get_name(VOID) &
", min_hits:" & to_string(min_hits) & ", rand_weight:" & to_string(rand_weight) & ", """ & bin_name & """)";
constant C_NUM_CROSS_BINS : integer := coverpoint1.get_num_bins_crossed(VOID) + coverpoint2.get_num_bins_crossed(VOID) +
coverpoint3.get_num_bins_crossed(VOID) + coverpoint4.get_num_bins_crossed(VOID) + coverpoint5.get_num_bins_crossed(VOID);
constant C_USE_RAND_WEIGHT : boolean := ext_proc_call = ""; -- When procedure is called from the sequencer
variable v_proc_call : line;
variable v_bin_array : t_new_bin_array(0 to C_NUM_CROSS_BINS-1);
variable v_idx_reg : integer_vector(0 to C_NUM_CROSS_BINS-1);
begin
create_proc_call(C_LOCAL_CALL, ext_proc_call, v_proc_call);
check_num_bins_crossed(C_NUM_CROSS_BINS, v_proc_call.all, coverpoint1.get_num_bins_crossed(VOID), coverpoint2.get_num_bins_crossed(VOID),
coverpoint3.get_num_bins_crossed(VOID), coverpoint4.get_num_bins_crossed(VOID), coverpoint5.get_num_bins_crossed(VOID));
log(ID_FUNC_COV_BINS, get_name_prefix(VOID) & v_proc_call.all, priv_scope, msg_id_panel);
log(ID_FUNC_COV_BINS_INFO, get_name_prefix(VOID) & "Adding cross: " & coverpoint1.get_all_bins_string(VOID) & " x " & coverpoint2.get_all_bins_string(VOID) &
" x " & coverpoint3.get_all_bins_string(VOID) & " x " & coverpoint4.get_all_bins_string(VOID) & " x " & coverpoint5.get_all_bins_string(VOID) &
", min_hits:" & to_string(min_hits) & ", rand_weight:" & return_string1_if_true_otherwise_string2(to_string(rand_weight), to_string(min_hits), C_USE_RAND_WEIGHT) &
", """ & bin_name & """", priv_scope, msg_id_panel);
-- Copy the bins into an array and use a recursive procedure to add them to the list
create_bin_array(v_bin_array, coverpoint1, coverpoint2, coverpoint3, coverpoint4, coverpoint5);
add_bins_recursive(v_bin_array, 0, v_idx_reg, min_hits, rand_weight, C_USE_RAND_WEIGHT, bin_name);
DEALLOCATE(v_proc_call);
end procedure;
procedure add_cross(
variable coverpoint1 : inout t_coverpoint;
variable coverpoint2 : inout t_coverpoint;
variable coverpoint3 : inout t_coverpoint;
variable coverpoint4 : inout t_coverpoint;
variable coverpoint5 : inout t_coverpoint;
constant min_hits : in positive;
constant bin_name : in string := "";
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel) is
constant C_LOCAL_CALL : string := "add_cross(" & coverpoint1.get_name(VOID) & ", " & coverpoint2.get_name(VOID) & ", " &
coverpoint3.get_name(VOID) & ", " & coverpoint4.get_name(VOID) & ", " & coverpoint5.get_name(VOID) &
", min_hits:" & to_string(min_hits) &", """ & bin_name & """)";
begin
add_cross(coverpoint1, coverpoint2, coverpoint3, coverpoint4, coverpoint5, min_hits, 1, bin_name, msg_id_panel, C_LOCAL_CALL);
end procedure;
procedure add_cross(
variable coverpoint1 : inout t_coverpoint;
variable coverpoint2 : inout t_coverpoint;
variable coverpoint3 : inout t_coverpoint;
variable coverpoint4 : inout t_coverpoint;
variable coverpoint5 : inout t_coverpoint;
constant bin_name : in string := "";
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel) is
constant C_LOCAL_CALL : string := "add_cross(" & coverpoint1.get_name(VOID) & ", " & coverpoint2.get_name(VOID) & ", " &
coverpoint3.get_name(VOID) & ", " & coverpoint4.get_name(VOID) & ", " & coverpoint5.get_name(VOID) & ", """ & bin_name & """)";
begin
add_cross(coverpoint1, coverpoint2, coverpoint3, coverpoint4, coverpoint5, 1, 1, bin_name, msg_id_panel, C_LOCAL_CALL);
end procedure;
------------------------------------------------------------
-- Coverage
------------------------------------------------------------
impure function is_defined(
constant VOID : t_void)
return boolean is
begin
return priv_num_bins_crossed /= C_UNINITIALIZED;
end function;
procedure sample_coverage(
constant value : in integer;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel) is
constant C_LOCAL_CALL : string := "sample_coverage(" & to_string(value) & ")";
variable v_values : integer_vector(0 to 0) := (0 => value);
begin
log(ID_FUNC_COV_SAMPLE, get_name_prefix(VOID) & C_LOCAL_CALL, priv_scope, msg_id_panel);
sample_coverage(v_values, msg_id_panel, C_LOCAL_CALL);
end procedure;
procedure sample_coverage(
constant values : in integer_vector;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant ext_proc_call : in string := "") is
constant C_LOCAL_CALL : string := "sample_coverage(" & to_string(values) & ")";
variable v_proc_call : line;
variable v_invalid_sample : boolean := false;
variable v_value_match : std_logic_vector(0 to priv_num_bins_crossed-1) := (others => '0');
variable v_illegal_match_idx : integer := -1;
variable v_num_occurrences : natural := 0;
begin
create_proc_call(C_LOCAL_CALL, ext_proc_call, v_proc_call);
if priv_num_bins_crossed = C_UNINITIALIZED then
alert(TB_ERROR, v_proc_call.all & "=> Coverpoint does not contain any bins", priv_scope);
DEALLOCATE(v_proc_call);
return;
end if;
if ext_proc_call = "" then -- Do not print log message when being called from another method
log(ID_FUNC_COV_SAMPLE, get_name_prefix(VOID) & v_proc_call.all, priv_scope, msg_id_panel);
end if;
if priv_num_bins_crossed /= values'length then
alert(TB_FAILURE, v_proc_call.all & "=> Number of values does not match the number of crossed bins", priv_scope);
end if;
-- Shift register used to check transition bins
for i in 0 to priv_num_bins_crossed-1 loop
priv_bin_sample_shift_reg(i) := priv_bin_sample_shift_reg(i)(priv_bin_sample_shift_reg(0)'length-2 downto 0) & values(i);
end loop;
-- Check if the values should be ignored or are illegal
for i in 0 to priv_invalid_bins_idx-1 loop
priv_invalid_bins(i).transition_mask := priv_invalid_bins(i).transition_mask(priv_invalid_bins(i).transition_mask'length-2 downto 0) & '1';
for j in 0 to priv_num_bins_crossed-1 loop
case priv_invalid_bins(i).cross_bins(j).contains is
when VAL | VAL_IGNORE | VAL_ILLEGAL =>
for k in 0 to priv_invalid_bins(i).cross_bins(j).num_values-1 loop
if values(j) = priv_invalid_bins(i).cross_bins(j).values(k) then
v_value_match(j) := '1';
v_illegal_match_idx := j when priv_invalid_bins(i).cross_bins(j).contains = VAL_ILLEGAL;
end if;
end loop;
when RAN | RAN_IGNORE | RAN_ILLEGAL =>
if values(j) >= priv_invalid_bins(i).cross_bins(j).values(0) and values(j) <= priv_invalid_bins(i).cross_bins(j).values(1) then
v_value_match(j) := '1';
v_illegal_match_idx := j when priv_invalid_bins(i).cross_bins(j).contains = RAN_ILLEGAL;
end if;
when TRN | TRN_IGNORE | TRN_ILLEGAL =>
-- Check if there are enough valid values in the shift register to compare the transition
if priv_invalid_bins(i).transition_mask(priv_invalid_bins(i).cross_bins(j).num_values-1) = '1' and
priv_bin_sample_shift_reg(j)(priv_invalid_bins(i).cross_bins(j).num_values-1 downto 0) = priv_invalid_bins(i).cross_bins(j).values(0 to priv_invalid_bins(i).cross_bins(j).num_values-1)
then
v_value_match(j) := '1';
v_illegal_match_idx := j when priv_invalid_bins(i).cross_bins(j).contains = TRN_ILLEGAL;
end if;
when others =>
alert(TB_FAILURE, v_proc_call.all & "=> Unexpected error, invalid bin contains " & to_upper(to_string(priv_invalid_bins(i).cross_bins(j).contains)), priv_scope);
end case;
end loop;
if and(v_value_match) = '1' then
v_invalid_sample := true;
priv_invalid_bins(i).transition_mask := (others => '0');
priv_invalid_bins(i).hits := priv_invalid_bins(i).hits + 1;
if v_illegal_match_idx /= -1 then
alert(priv_illegal_bin_alert_level, get_name_prefix(VOID) & v_proc_call.all & "=> Sampled " & get_bin_info(priv_invalid_bins(i).cross_bins(v_illegal_match_idx)), priv_scope);
end if;
end if;
v_value_match := (others => '0');
v_illegal_match_idx := -1;
end loop;
-- Check if the values are in the valid bins
if not(v_invalid_sample) then
for i in 0 to priv_bins_idx-1 loop
priv_bins(i).transition_mask := priv_bins(i).transition_mask(priv_bins(i).transition_mask'length-2 downto 0) & '1';
for j in 0 to priv_num_bins_crossed-1 loop
case priv_bins(i).cross_bins(j).contains is
when VAL =>
for k in 0 to priv_bins(i).cross_bins(j).num_values-1 loop
if values(j) = priv_bins(i).cross_bins(j).values(k) then
v_value_match(j) := '1';
end if;
end loop;
when RAN =>
if values(j) >= priv_bins(i).cross_bins(j).values(0) and values(j) <= priv_bins(i).cross_bins(j).values(1) then
v_value_match(j) := '1';
end if;
when TRN =>
-- Check if there are enough valid values in the shift register to compare the transition
if priv_bins(i).transition_mask(priv_bins(i).cross_bins(j).num_values-1) = '1' and
priv_bin_sample_shift_reg(j)(priv_bins(i).cross_bins(j).num_values-1 downto 0) = priv_bins(i).cross_bins(j).values(0 to priv_bins(i).cross_bins(j).num_values-1)
then
v_value_match(j) := '1';
end if;
when others =>
alert(TB_FAILURE, v_proc_call.all & "=> Unexpected error, valid bin contains " & to_upper(to_string(priv_bins(i).cross_bins(j).contains)), priv_scope);
end case;
end loop;
if and(v_value_match) = '1' then
priv_bins(i).transition_mask := (others => '0');
priv_bins(i).hits := priv_bins(i).hits + 1;
v_num_occurrences := v_num_occurrences + 1;
-- Update covergroup status register
protected_covergroup_status.increment_hits_count(priv_id); -- Count the total hits
if priv_bins(i).hits <= priv_bins(i).min_hits then
protected_covergroup_status.increment_coverage_hits_count(priv_id); -- Count until min_hits has been reached
end if;
if priv_bins(i).hits <= get_total_min_hits(priv_bins(i).min_hits) then
protected_covergroup_status.increment_goal_hits_count(priv_id); -- Count until min_hits x goal has been reached
end if;
if priv_bins(i).hits = priv_bins(i).min_hits and priv_bins(i).min_hits /= 0 then
protected_covergroup_status.increment_covered_bin_count(priv_id); -- Count the covered bins
end if;
end if;
v_value_match := (others => '0');
end loop;
if v_num_occurrences > 1 then
alert(priv_bin_overlap_alert_level, get_name_prefix(VOID) & "There is an overlap between " & to_string(v_num_occurrences) & " bins.", priv_scope);
end if;
else
-- When an ignore or illegal bin is sampled, valid bins won't be sampled so we need to clear all transition masks in the valid bins
for i in 0 to priv_bins_idx-1 loop
priv_bins(i).transition_mask := (others => '0');
end loop;
end if;
DEALLOCATE(v_proc_call);
end procedure;
impure function get_coverage(
constant coverage_type : t_coverage_type;
constant percentage_of_goal : boolean := false)
return real is
constant C_LOCAL_CALL : string := "get_coverage(" & to_upper(to_string(coverage_type)) & ")";
variable v_coverage_representation : t_coverage_representation;
begin
if priv_id /= C_DEALLOCATED_ID then
v_coverage_representation := GOAL_CAPPED when percentage_of_goal else NO_GOAL;
if coverage_type = BINS then
return protected_covergroup_status.get_bins_coverage(priv_id, v_coverage_representation);
elsif coverage_type = HITS then
return protected_covergroup_status.get_hits_coverage(priv_id, v_coverage_representation);
else -- BINS_AND_HITS
alert(TB_ERROR, C_LOCAL_CALL & "=> Use either BINS or HITS.", priv_scope);
return 0.0;
end if;
else
return 0.0;
end if;
end function;
impure function coverage_completed(
constant coverage_type : t_coverage_type)
return boolean is
begin
if priv_id /= C_DEALLOCATED_ID then
if coverage_type = BINS then
return protected_covergroup_status.get_bins_coverage(priv_id, GOAL_CAPPED) = 100.0;
elsif coverage_type = HITS then
return protected_covergroup_status.get_hits_coverage(priv_id, GOAL_CAPPED) = 100.0;
else -- BINS_AND_HITS
return protected_covergroup_status.get_bins_coverage(priv_id, GOAL_CAPPED) = 100.0 and
protected_covergroup_status.get_hits_coverage(priv_id, GOAL_CAPPED) = 100.0;
end if;
else
return false;
end if;
end function;
procedure report_coverage(
constant VOID : in t_void) is
begin
report_coverage(NON_VERBOSE);
end procedure;
procedure report_coverage(
constant verbosity : in t_report_verbosity;
constant file_name : in string := "";
constant open_mode : in file_open_kind := append_mode;
constant rand_weight_col : in t_rand_weight_visibility := HIDE_RAND_WEIGHT) is
file file_handler : text;
constant C_PREFIX : string := C_LOG_PREFIX & " ";
constant C_HEADER_1 : string := "*** COVERAGE SUMMARY REPORT (VERBOSE): " & to_string(priv_scope) & " ***";
constant C_HEADER_2 : string := "*** COVERAGE SUMMARY REPORT (NON VERBOSE): " & to_string(priv_scope) & " ***";
constant C_HEADER_3 : string := "*** COVERAGE HOLES REPORT: " & to_string(priv_scope) & " ***";
constant C_BIN_COLUMN_WIDTH : positive := 40;
constant C_COLUMN_WIDTH : positive := 15;
variable v_line : line;
variable v_log_extra_space : integer := 0;
variable v_print_goal : boolean;
variable v_rand_weight : natural;
begin
-- Calculate how much space we can insert between the columns of the report
v_log_extra_space := (C_LOG_LINE_WIDTH - C_PREFIX'length - C_BIN_COLUMN_WIDTH - C_COLUMN_WIDTH*5 - C_FC_MAX_NAME_LENGTH)/8;
if v_log_extra_space < 1 then
alert(TB_WARNING, "C_LOG_LINE_WIDTH is too small or C_FC_MAX_NAME_LENGTH is too big, the report will not be properly aligned.", priv_scope);
v_log_extra_space := 1;
end if;
-- Print report header
write(v_line, LF & fill_string('=', (C_LOG_LINE_WIDTH - C_PREFIX'length)) & LF);
if verbosity = VERBOSE then
write(v_line, timestamp_header(now, justify(C_HEADER_1, LEFT, C_LOG_LINE_WIDTH - C_PREFIX'length, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE)) & LF);
elsif verbosity = NON_VERBOSE then
write(v_line, timestamp_header(now, justify(C_HEADER_2, LEFT, C_LOG_LINE_WIDTH - C_PREFIX'length, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE)) & LF);
elsif verbosity = HOLES_ONLY then
write(v_line, timestamp_header(now, justify(C_HEADER_3, LEFT, C_LOG_LINE_WIDTH - C_PREFIX'length, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE)) & LF);
end if;
write(v_line, fill_string('=', (C_LOG_LINE_WIDTH - C_PREFIX'length)) & LF);
-- Print summary
if priv_id /= C_DEALLOCATED_ID then
v_print_goal := protected_covergroup_status.get_bins_coverage_goal(priv_id) /= 100 or
protected_covergroup_status.get_hits_coverage_goal(priv_id) /= 100;
write(v_line, "Coverpoint: " & to_string(priv_name) & LF &
return_string_if_true("Goal: " &
justify("Bins: " & to_string(protected_covergroup_status.get_bins_coverage_goal(priv_id)) & "%, ", left, 16, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) &
justify("Hits: " & to_string(protected_covergroup_status.get_hits_coverage_goal(priv_id)) & "%", left, 14, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & LF, v_print_goal) &
return_string_if_true("% of Goal: " &
justify("Bins: " & to_string(protected_covergroup_status.get_bins_coverage(priv_id, GOAL_CAPPED),2) & "%, ", left, 16, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) &
justify("Hits: " & to_string(protected_covergroup_status.get_hits_coverage(priv_id, GOAL_CAPPED),2) & "%", left, 14, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & LF, v_print_goal) &
return_string_if_true("% of Goal (uncapped): " &
justify("Bins: " & to_string(protected_covergroup_status.get_bins_coverage(priv_id, GOAL_UNCAPPED),2) & "%, ", left, 16, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) &
justify("Hits: " & to_string(protected_covergroup_status.get_hits_coverage(priv_id, GOAL_UNCAPPED),2) & "%", left, 14, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & LF, v_print_goal) &
"Coverage (for goal 100): " &
justify("Bins: " & to_string(protected_covergroup_status.get_bins_coverage(priv_id, NO_GOAL),2) & "%, ", left, 16, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) &
justify("Hits: " & to_string(protected_covergroup_status.get_hits_coverage(priv_id, NO_GOAL),2) & "%", left, 14, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & LF &
fill_string('-', (C_LOG_LINE_WIDTH - C_PREFIX'length)) & LF);
else
write(v_line, "Coverpoint: " & to_string(priv_name) & LF &
"Coverage (for goal 100): " &
justify("Bins: 0.0%, ", left, 16, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) &
justify("Hits: 0.0%", left, 14, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & LF &
fill_string('-', (C_LOG_LINE_WIDTH - C_PREFIX'length)) & LF);
end if;
-- Print column headers
write(v_line, justify(
fill_string(' ', v_log_extra_space) &
justify("BINS" , center, C_BIN_COLUMN_WIDTH, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space) &
justify("HITS" , center, C_COLUMN_WIDTH, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space) &
justify("MIN HITS" , center, C_COLUMN_WIDTH, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space) &
justify("HIT COVERAGE" , center, C_COLUMN_WIDTH, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space) &
return_string_if_true(justify("RAND WEIGHT", center, C_COLUMN_WIDTH, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space),rand_weight_col = SHOW_RAND_WEIGHT) &
justify("NAME" , center, C_FC_MAX_NAME_LENGTH, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space) &
justify("ILLEGAL/IGNORE", center, C_COLUMN_WIDTH, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space),
left, C_LOG_LINE_WIDTH - C_PREFIX'length, KEEP_LEADING_SPACE, DISALLOW_TRUNCATE) & LF);
-- Print illegal bins
for i in 0 to priv_invalid_bins_idx-1 loop
if is_bin_illegal(priv_invalid_bins(i)) and (verbosity = VERBOSE or (verbosity = NON_VERBOSE and priv_invalid_bins(i).hits > 0)) then
write(v_line, justify(
fill_string(' ', v_log_extra_space) &
justify(get_bin_values(priv_invalid_bins(i), C_BIN_COLUMN_WIDTH), center, C_BIN_COLUMN_WIDTH, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space) &
justify(to_string(priv_invalid_bins(i).hits) , center, C_COLUMN_WIDTH, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space) &
justify("N/A" , center, C_COLUMN_WIDTH, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space) &
justify("N/A" , center, C_COLUMN_WIDTH, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space) &
return_string_if_true(justify("N/A" , center, C_COLUMN_WIDTH, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space),rand_weight_col = SHOW_RAND_WEIGHT) &
justify(to_string(priv_invalid_bins(i).name) , center, C_FC_MAX_NAME_LENGTH, KEEP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space) &
justify("ILLEGAL" , center, C_COLUMN_WIDTH, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space),
left, C_LOG_LINE_WIDTH - C_PREFIX'length, KEEP_LEADING_SPACE, DISALLOW_TRUNCATE) & LF);
end if;
end loop;
-- Print ignore bins
if verbosity = VERBOSE then
for i in 0 to priv_invalid_bins_idx-1 loop
if is_bin_ignore(priv_invalid_bins(i)) then
write(v_line, justify(
fill_string(' ', v_log_extra_space) &
justify(get_bin_values(priv_invalid_bins(i), C_BIN_COLUMN_WIDTH), center, C_BIN_COLUMN_WIDTH, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space) &
justify(to_string(priv_invalid_bins(i).hits) , center, C_COLUMN_WIDTH, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space) &
justify("N/A" , center, C_COLUMN_WIDTH, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space) &
justify("N/A" , center, C_COLUMN_WIDTH, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space) &
return_string_if_true(justify("N/A" , center, C_COLUMN_WIDTH, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space),rand_weight_col = SHOW_RAND_WEIGHT) &
justify(to_string(priv_invalid_bins(i).name) , center, C_FC_MAX_NAME_LENGTH, KEEP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space) &
justify("IGNORE" , center, C_COLUMN_WIDTH, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space),
left, C_LOG_LINE_WIDTH - C_PREFIX'length, KEEP_LEADING_SPACE, DISALLOW_TRUNCATE) & LF);
end if;
end loop;
end if;
-- Print valid bins
for i in 0 to priv_bins_idx-1 loop
if verbosity = VERBOSE or verbosity = NON_VERBOSE or (verbosity = HOLES_ONLY and priv_bins(i).hits < get_total_min_hits(priv_bins(i).min_hits)) then
v_rand_weight := priv_bins(i).min_hits when priv_bins(i).rand_weight = C_USE_ADAPTIVE_WEIGHT else priv_bins(i).rand_weight;
write(v_line, justify(
fill_string(' ', v_log_extra_space) &
justify(get_bin_values(priv_bins(i), C_BIN_COLUMN_WIDTH) , center, C_BIN_COLUMN_WIDTH, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space) &
justify(to_string(priv_bins(i).hits) , center, C_COLUMN_WIDTH, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space) &
justify(to_string(priv_bins(i).min_hits) , center, C_COLUMN_WIDTH, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space) &
justify(to_string(get_bin_coverage(priv_bins(i)),2) & "%", center, C_COLUMN_WIDTH, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space) &
return_string_if_true(justify(to_string(v_rand_weight) , center, C_COLUMN_WIDTH, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space),rand_weight_col = SHOW_RAND_WEIGHT) &
justify(to_string(priv_bins(i).name) , center, C_FC_MAX_NAME_LENGTH, KEEP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space) &
justify("-" , center, C_COLUMN_WIDTH, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE) & fill_string(' ', v_log_extra_space),
left, C_LOG_LINE_WIDTH - C_PREFIX'length, KEEP_LEADING_SPACE, DISALLOW_TRUNCATE) & LF);
end if;
end loop;
write(v_line, fill_string('-', (C_LOG_LINE_WIDTH - C_PREFIX'length)) & LF);
-- Print bin values that didn't fit in section above
for i in 0 to priv_invalid_bins_idx-1 loop
if is_bin_illegal(priv_invalid_bins(i)) and (verbosity = VERBOSE or (verbosity = NON_VERBOSE and priv_invalid_bins(i).hits > 0)) then
if get_bin_values(priv_invalid_bins(i), C_BIN_COLUMN_WIDTH) = to_string(priv_invalid_bins(i).name) then
write(v_line, to_string(priv_invalid_bins(i).name) & ": " & get_bin_values(priv_invalid_bins(i)) & LF);
end if;
end if;
end loop;
if verbosity = VERBOSE then
for i in 0 to priv_invalid_bins_idx-1 loop
if is_bin_ignore(priv_invalid_bins(i)) then
if get_bin_values(priv_invalid_bins(i), C_BIN_COLUMN_WIDTH) = to_string(priv_invalid_bins(i).name) then
write(v_line, to_string(priv_invalid_bins(i).name) & ": " & get_bin_values(priv_invalid_bins(i)) & LF);
end if;
end if;
end loop;
end if;
for i in 0 to priv_bins_idx-1 loop
if verbosity = VERBOSE or verbosity = NON_VERBOSE or (verbosity = HOLES_ONLY and priv_bins(i).hits < get_total_min_hits(priv_bins(i).min_hits)) then
if get_bin_values(priv_bins(i), C_BIN_COLUMN_WIDTH) = to_string(priv_bins(i).name) then
write(v_line, to_string(priv_bins(i).name) & ": " & get_bin_values(priv_bins(i)) & LF);
end if;
end if;
end loop;
-- Print report bottom line
write(v_line, fill_string('=', (C_LOG_LINE_WIDTH - C_PREFIX'length)) & LF & LF);
-- Write the info string to transcript
wrap_lines(v_line, 1, 1, C_LOG_LINE_WIDTH-C_PREFIX'length);
prefix_lines(v_line, C_PREFIX);
if file_name /= "" then
file_open(file_handler, file_name, open_mode);
tee(file_handler, v_line); -- write to file, while keeping the line contents
file_close(file_handler);
end if;
write_line_to_log_destination(v_line);
DEALLOCATE(v_line);
end procedure;
procedure report_config(
constant VOID : in t_void) is
begin
report_config("");
end procedure;
procedure report_config(
constant file_name : in string;
constant open_mode : in file_open_kind := append_mode) is
file file_handler : text;
constant C_PREFIX : string := C_LOG_PREFIX & " ";
constant C_COLUMN1_WIDTH : positive := 24;
constant C_COLUMN2_WIDTH : positive := MAXIMUM(C_FC_MAX_NAME_LENGTH, C_LOG_SCOPE_WIDTH);
variable v_line : line;
begin
-- Print report header
write(v_line, LF & fill_string('=', (C_LOG_LINE_WIDTH - C_PREFIX'length)) & LF &
"*** COVERPOINT CONFIGURATION REPORT ***" & LF &
fill_string('=', (C_LOG_LINE_WIDTH - C_PREFIX'length)) & LF);
-- Print report config
if priv_id /= C_DEALLOCATED_ID then
write(v_line, " " & justify("NAME", left, C_COLUMN1_WIDTH) & ": " & justify(to_string(priv_name), right, C_COLUMN2_WIDTH) & LF);
else
write(v_line, " " & justify("NAME", left, C_COLUMN1_WIDTH) & ": " & justify("**uninitialized**", right, C_COLUMN2_WIDTH) & LF);
end if;
write(v_line, " " & justify("SCOPE", left, C_COLUMN1_WIDTH) & ": " & justify(to_string(priv_scope), right, C_COLUMN2_WIDTH) & LF);
write(v_line, " " & justify("ILLEGAL BIN ALERT LEVEL", left, C_COLUMN1_WIDTH) & ": " & justify(to_upper(to_string(priv_illegal_bin_alert_level)), right, C_COLUMN2_WIDTH) & LF);
write(v_line, " " & justify("BIN OVERLAP ALERT LEVEL", left, C_COLUMN1_WIDTH) & ": " & justify(to_upper(to_string(priv_bin_overlap_alert_level)), right, C_COLUMN2_WIDTH) & LF);
if priv_id /= C_DEALLOCATED_ID then
write(v_line, " " & justify("COVERAGE WEIGHT", left, C_COLUMN1_WIDTH) & ": " & justify(to_string(protected_covergroup_status.get_coverage_weight(priv_id)), right, C_COLUMN2_WIDTH) & LF);
write(v_line, " " & justify("BINS COVERAGE GOAL", left, C_COLUMN1_WIDTH) & ": " & justify(to_string(protected_covergroup_status.get_bins_coverage_goal(priv_id)), right, C_COLUMN2_WIDTH) & LF);
write(v_line, " " & justify("HITS COVERAGE GOAL", left, C_COLUMN1_WIDTH) & ": " & justify(to_string(protected_covergroup_status.get_hits_coverage_goal(priv_id)), right, C_COLUMN2_WIDTH) & LF);
else
write(v_line, " " & justify("COVERAGE WEIGHT", left, C_COLUMN1_WIDTH) & ": " & justify(to_string(1), right, C_COLUMN2_WIDTH) & LF);
write(v_line, " " & justify("BINS COVERAGE GOAL", left, C_COLUMN1_WIDTH) & ": " & justify(to_string(100), right, C_COLUMN2_WIDTH) & LF);
write(v_line, " " & justify("HITS COVERAGE GOAL", left, C_COLUMN1_WIDTH) & ": " & justify(to_string(100), right, C_COLUMN2_WIDTH) & LF);
end if;
write(v_line, " " & justify("COVERPOINTS GOAL", left, C_COLUMN1_WIDTH) & ": " & justify(to_string(protected_covergroup_status.get_covpts_coverage_goal(VOID)), right, C_COLUMN2_WIDTH) & LF);
write(v_line, " " & justify("NUMBER OF BINS", left, C_COLUMN1_WIDTH) & ": " & justify(to_string(priv_bins_idx+priv_invalid_bins_idx), right, C_COLUMN2_WIDTH) & LF);
write(v_line, " " & justify("CROSS DIMENSIONS", left, C_COLUMN1_WIDTH) & ": " & justify(to_string(priv_num_bins_crossed), right, C_COLUMN2_WIDTH) & LF);
-- Print report bottom line
write(v_line, fill_string('=', (C_LOG_LINE_WIDTH - C_PREFIX'length)) & LF & LF);
-- Write the info string to transcript
wrap_lines(v_line, 1, 1, C_LOG_LINE_WIDTH-C_PREFIX'length);
prefix_lines(v_line, C_PREFIX);
if file_name /= "" then
file_open(file_handler, file_name, open_mode);
tee(file_handler, v_line); -- write to file, while keeping the line contents
file_close(file_handler);
end if;
write_line_to_log_destination(v_line);
DEALLOCATE(v_line);
end procedure;
------------------------------------------------------------
-- Optimized Randomization
------------------------------------------------------------
impure function rand(
constant sampling : t_rand_sample_cov;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel)
return integer is
constant C_LOCAL_CALL : string := "rand(" & to_upper(to_string(sampling)) & ")";
variable v_ret : integer_vector(0 to 0);
begin
v_ret := rand(sampling, msg_id_panel, C_LOCAL_CALL);
if priv_num_bins_crossed /= C_UNINITIALIZED then
log(ID_FUNC_COV_RAND, get_name_prefix(VOID) & C_LOCAL_CALL & "=> " & to_string(v_ret(0)), priv_scope, msg_id_panel);
end if;
return v_ret(0);
end function;
impure function rand(
constant sampling : t_rand_sample_cov;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant ext_proc_call : string := "")
return integer_vector is
constant C_LOCAL_CALL : string := "rand(" & to_upper(to_string(sampling)) & ")";
variable v_bin_weight_list : t_val_weight_int_vec(0 to priv_bins_idx-1);
variable v_acc_weight : natural := 0;
variable v_values_vec : integer_vector(0 to C_FC_MAX_NUM_BIN_VALUES-1);
variable v_bin_idx : natural;
variable v_ret : integer_vector(0 to MAXIMUM(priv_num_bins_crossed,1)-1);
variable v_hits : natural := 0;
variable v_iteration : natural := 0;
begin
if priv_num_bins_crossed = C_UNINITIALIZED then
alert(TB_ERROR, C_LOCAL_CALL & "=> Coverpoint does not contain any bins", priv_scope);
return v_ret;
end if;
-- A transition bin returns all the transition values before allowing to select a different bin value
if priv_rand_transition_bin_idx /= C_UNINITIALIZED then
v_bin_idx := priv_rand_transition_bin_idx;
else
-- Assign each bin a randomization weight
while v_acc_weight = 0 loop
for i in 0 to priv_bins_idx-1 loop
v_bin_weight_list(i).value := i;
v_hits := priv_bins(i).hits - (v_iteration * get_total_min_hits(priv_bins(i).min_hits));
if v_hits < get_total_min_hits(priv_bins(i).min_hits) then
v_bin_weight_list(i).weight := get_total_min_hits(priv_bins(i).min_hits) - v_hits when priv_bins(i).rand_weight = C_USE_ADAPTIVE_WEIGHT else
priv_bins(i).rand_weight;
else
v_bin_weight_list(i).weight := 0;
end if;
v_acc_weight := v_acc_weight + v_bin_weight_list(i).weight;
end loop;
-- When all the bins have reached their min_hits, the accumulated weight will be 0 and
-- a new iteration will be done where all the bins are uncovered again by simulating
-- the number of hits are cleared
v_iteration := v_iteration + 1;
end loop;
-- Choose a random bin index
v_bin_idx := priv_rand_gen.rand_val_weight(v_bin_weight_list, msg_id_panel);
end if;
-- Select the random bin values to return (ignore and illegal bin values are never selected)
for i in 0 to priv_num_bins_crossed-1 loop
v_values_vec := (others => 0);
if priv_bins(v_bin_idx).cross_bins(i).contains = VAL then
if priv_bins(v_bin_idx).cross_bins(i).num_values = 1 then
v_ret(i) := priv_bins(v_bin_idx).cross_bins(i).values(0);
else
for j in 0 to priv_bins(v_bin_idx).cross_bins(i).num_values-1 loop
v_values_vec(j) := priv_bins(v_bin_idx).cross_bins(i).values(j);
end loop;
v_ret(i) := priv_rand_gen.rand(ONLY, v_values_vec(0 to priv_bins(v_bin_idx).cross_bins(i).num_values-1), NON_CYCLIC, msg_id_panel);
end if;
elsif priv_bins(v_bin_idx).cross_bins(i).contains = RAN then
v_ret(i) := priv_rand_gen.rand(priv_bins(v_bin_idx).cross_bins(i).values(0), priv_bins(v_bin_idx).cross_bins(i).values(1), NON_CYCLIC, msg_id_panel);
elsif priv_bins(v_bin_idx).cross_bins(i).contains = TRN then
-- Store the bin index to return the next value in the following rand() call
if priv_rand_transition_bin_idx = C_UNINITIALIZED then
priv_rand_transition_bin_idx := v_bin_idx;
end if;
v_ret(i) := priv_bins(v_bin_idx).cross_bins(i).values(priv_rand_transition_bin_value_idx(i));
if priv_rand_transition_bin_value_idx(i) < priv_bins(v_bin_idx).cross_bins(i).num_values then
priv_rand_transition_bin_value_idx(i) := priv_rand_transition_bin_value_idx(i) + 1;
end if;
else
alert(TB_FAILURE, C_LOCAL_CALL & "=> Unexpected error, bin contains " & to_upper(to_string(priv_bins(v_bin_idx).cross_bins(i).contains)), priv_scope);
end if;
-- Reset transition index variables when all the transitions in a bin have been generated
if i = priv_num_bins_crossed-1 and priv_rand_transition_bin_idx /= C_UNINITIALIZED then
for j in 0 to priv_num_bins_crossed-1 loop
if priv_bins(v_bin_idx).cross_bins(j).contains = TRN and priv_rand_transition_bin_value_idx(j) < priv_bins(v_bin_idx).cross_bins(j).num_values then
exit;
elsif j = priv_num_bins_crossed-1 then
priv_rand_transition_bin_idx := C_UNINITIALIZED;
priv_rand_transition_bin_value_idx := (others => 0);
end if;
end loop;
end if;
end loop;
if sampling = SAMPLE_COV then
sample_coverage(v_ret, msg_id_panel, C_LOCAL_CALL);
end if;
if ext_proc_call = "" then -- Do not print log message when being called from another method
log(ID_FUNC_COV_RAND, get_name_prefix(VOID) & C_LOCAL_CALL & "=> " & to_string(v_ret), priv_scope, msg_id_panel);
end if;
return v_ret;
end function;
procedure set_rand_seeds(
constant seed1 : in positive;
constant seed2 : in positive) is
begin
initialize_coverpoint("set_rand_seeds");
priv_rand_gen.set_rand_seeds(seed1, seed2);
end procedure;
procedure set_rand_seeds(
constant seeds : in t_positive_vector(0 to 1)) is
begin
initialize_coverpoint("set_rand_seeds");
priv_rand_gen.set_rand_seeds(seeds);
end procedure;
procedure get_rand_seeds(
variable seed1 : out positive;
variable seed2 : out positive) is
begin
priv_rand_gen.get_rand_seeds(seed1, seed2);
end procedure;
impure function get_rand_seeds(
constant VOID : t_void)
return t_positive_vector is
begin
return priv_rand_gen.get_rand_seeds(VOID);
end function;
end protected body t_coverpoint;
end package body func_cov_pkg;
|
mit
|
UVVM/UVVM_All
|
bitvis_vip_clock_generator/src/clock_generator_vvc.vhd
|
1
|
17703
|
--================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
----------------------------------------------------------------------------------------------------------------------------------
--========================================================================================================================
-- This VVC was generated with Bitvis VVC Generator
--========================================================================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
use work.vvc_methods_pkg.all;
use work.vvc_cmd_pkg.all;
use work.td_target_support_pkg.all;
use work.td_vvc_entity_support_pkg.all;
use work.td_cmd_queue_pkg.all;
use work.td_result_queue_pkg.all;
--========================================================================================================================
entity clock_generator_vvc is
generic (
GC_INSTANCE_IDX : natural := 1;
GC_CLOCK_NAME : string := "clk";
GC_CLOCK_PERIOD : time := 10 ns;
GC_CLOCK_HIGH_TIME : time := 5 ns;
GC_CMD_QUEUE_COUNT_MAX : natural := 1000;
GC_CMD_QUEUE_COUNT_THRESHOLD : natural := 950;
GC_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY : t_alert_level := WARNING;
GC_RESULT_QUEUE_COUNT_MAX : natural := 1000;
GC_RESULT_QUEUE_COUNT_THRESHOLD : natural := 950;
GC_RESULT_QUEUE_COUNT_THRESHOLD_SEVERITY : t_alert_level := warning
);
port (
clk : out std_logic
);
begin
assert (GC_CLOCK_NAME'length <= C_MAX_VVC_NAME_LENGTH) report "Clock name is too long (max " & to_string(C_MAX_VVC_NAME_LENGTH) & " characters)" severity ERROR;
end entity clock_generator_vvc;
--========================================================================================================================
--========================================================================================================================
architecture behave of clock_generator_vvc is
constant C_SCOPE : string := C_VVC_NAME & "," & to_string(GC_INSTANCE_IDX);
constant C_VVC_LABELS : t_vvc_labels := assign_vvc_labels(C_SCOPE, C_VVC_NAME, GC_INSTANCE_IDX, NA);
signal executor_is_busy : boolean := false;
signal queue_is_increasing : boolean := false;
signal last_cmd_idx_executed : natural := 0;
signal terminate_current_cmd : t_flag_record;
signal clock_ena : boolean := false;
-- VVC Activity
signal entry_num_in_vvc_activity_register : integer;
-- Instantiation of the element dedicated executor
shared variable command_queue : work.td_cmd_queue_pkg.t_generic_queue;
shared variable result_queue : work.td_result_queue_pkg.t_generic_queue;
alias vvc_config : t_vvc_config is shared_clock_generator_vvc_config(GC_INSTANCE_IDX);
alias vvc_status : t_vvc_status is shared_clock_generator_vvc_status(GC_INSTANCE_IDX);
alias transaction_info : t_transaction_info is shared_clock_generator_transaction_info(GC_INSTANCE_IDX);
alias clock_name : string is vvc_config.clock_name;
alias clock_period : time is vvc_config.clock_period;
alias clock_high_time : time is vvc_config.clock_high_time;
impure function get_clock_name
return string is
begin
return clock_name(1 to pos_of_leftmost(NUL, clock_name, clock_name'length));
end function;
begin
--========================================================================================================================
-- Constructor
-- - Set up the defaults and show constructor if enabled
--========================================================================================================================
work.td_vvc_entity_support_pkg.vvc_constructor(C_SCOPE, GC_INSTANCE_IDX, vvc_config, command_queue, result_queue, C_VOID_BFM_CONFIG,
GC_CMD_QUEUE_COUNT_MAX, GC_CMD_QUEUE_COUNT_THRESHOLD, GC_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY,
GC_RESULT_QUEUE_COUNT_MAX, GC_RESULT_QUEUE_COUNT_THRESHOLD, GC_RESULT_QUEUE_COUNT_THRESHOLD_SEVERITY);
--========================================================================================================================
--========================================================================================================================
-- Config initializer
-- - Set up the VVC specific config fields
--========================================================================================================================
config_initializer : process
begin
loop
wait for 0 ns;
exit when shared_uvvm_state = PHASE_B;
end loop;
clock_name := (others => NUL);
clock_name(1 to GC_CLOCK_NAME'length) := GC_CLOCK_NAME;
clock_period := GC_CLOCK_PERIOD;
clock_high_time := GC_CLOCK_HIGH_TIME;
wait;
end process;
--========================================================================================================================
--========================================================================================================================
-- Command interpreter
-- - Interpret, decode and acknowledge commands from the central sequencer
--========================================================================================================================
cmd_interpreter : process
variable v_cmd_has_been_acked : boolean; -- Indicates if acknowledge_cmd() has been called for the current shared_vvc_cmd
variable v_local_vvc_cmd : t_vvc_cmd_record := C_VVC_CMD_DEFAULT;
variable v_msg_id_panel : t_msg_id_panel;
begin
-- 0. Initialize the process prior to first command
work.td_vvc_entity_support_pkg.initialize_interpreter(terminate_current_cmd, global_awaiting_completion);
-- initialise shared_vvc_last_received_cmd_idx for channel and instance
shared_vvc_last_received_cmd_idx(NA, GC_INSTANCE_IDX) := 0;
-- Register VVC in vvc activity register
entry_num_in_vvc_activity_register <= shared_vvc_activity_register.priv_register_vvc(name => C_VVC_NAME,
instance => GC_INSTANCE_IDX);
-- Set initial value of v_msg_id_panel to msg_id_panel in config
v_msg_id_panel := vvc_config.msg_id_panel;
-- Then for every single command from the sequencer
loop -- basically as long as new commands are received
-- 1. wait until command targeted at this VVC. Must match VVC name, instance and channel (if applicable)
-- releases global semaphore
-------------------------------------------------------------------------
work.td_vvc_entity_support_pkg.await_cmd_from_sequencer(C_VVC_LABELS, vvc_config, THIS_VVCT, VVC_BROADCAST, global_vvc_busy, global_vvc_ack, v_local_vvc_cmd);
v_cmd_has_been_acked := false; -- Clear flag
-- update shared_vvc_last_received_cmd_idx with received command index
shared_vvc_last_received_cmd_idx(NA, GC_INSTANCE_IDX) := v_local_vvc_cmd.cmd_idx;
-- Select between a provided msg_id_panel via the vvc_cmd_record from a VVC with a higher hierarchy or the
-- msg_id_panel in this VVC's config. This is to correctly handle the logging when using Hierarchical-VVCs.
v_msg_id_panel := get_msg_id_panel(v_local_vvc_cmd, vvc_config);
-- 2a. Put command on the executor if intended for the executor
-------------------------------------------------------------------------
if v_local_vvc_cmd.command_type = QUEUED then
work.td_vvc_entity_support_pkg.put_command_on_queue(v_local_vvc_cmd, command_queue, vvc_status, queue_is_increasing);
-- 2b. Otherwise command is intended for immediate response
-------------------------------------------------------------------------
elsif v_local_vvc_cmd.command_type = IMMEDIATE then
case v_local_vvc_cmd.operation is
when AWAIT_COMPLETION =>
work.td_vvc_entity_support_pkg.interpreter_await_completion(v_local_vvc_cmd, command_queue, vvc_config, executor_is_busy, C_VVC_LABELS, last_cmd_idx_executed);
when DISABLE_LOG_MSG =>
uvvm_util.methods_pkg.disable_log_msg(v_local_vvc_cmd.msg_id, vvc_config.msg_id_panel, to_string(v_local_vvc_cmd.msg) & format_command_idx(v_local_vvc_cmd), C_SCOPE, v_local_vvc_cmd.quietness);
when ENABLE_LOG_MSG =>
uvvm_util.methods_pkg.enable_log_msg(v_local_vvc_cmd.msg_id, vvc_config.msg_id_panel, to_string(v_local_vvc_cmd.msg) & format_command_idx(v_local_vvc_cmd), C_SCOPE, v_local_vvc_cmd.quietness);
when FLUSH_COMMAND_QUEUE =>
work.td_vvc_entity_support_pkg.interpreter_flush_command_queue(v_local_vvc_cmd, command_queue, vvc_config, vvc_status, C_VVC_LABELS);
when TERMINATE_CURRENT_COMMAND =>
work.td_vvc_entity_support_pkg.interpreter_terminate_current_command(v_local_vvc_cmd, vvc_config, C_VVC_LABELS, terminate_current_cmd);
when others =>
tb_error("Unsupported command received for IMMEDIATE execution: '" & to_string(v_local_vvc_cmd.operation) & "'", C_SCOPE);
end case;
else
tb_error("command_type is not IMMEDIATE or QUEUED", C_SCOPE);
end if;
-- 3. Acknowledge command after runing or queuing the command
-------------------------------------------------------------------------
if not v_cmd_has_been_acked then
work.td_target_support_pkg.acknowledge_cmd(global_vvc_ack,v_local_vvc_cmd.cmd_idx);
end if;
end loop;
end process;
--========================================================================================================================
--========================================================================================================================
-- Command executor
-- - Fetch and execute the commands
--========================================================================================================================
cmd_executor : process
variable v_cmd : t_vvc_cmd_record;
variable v_msg_id_panel : t_msg_id_panel;
begin
-- 0. Initialize the process prior to first command
-------------------------------------------------------------------------
work.td_vvc_entity_support_pkg.initialize_executor(terminate_current_cmd);
-- Set initial value of v_msg_id_panel to msg_id_panel in config
v_msg_id_panel := vvc_config.msg_id_panel;
loop
-- update vvc activity. Note that clock generator VVC activity is not included in the resetting of the VVC activity register!
-- update_vvc_activity_register(global_trigger_vvc_activity_register, vvc_status, INACTIVE, entry_num_in_vvc_activity_register, last_cmd_idx_executed, command_queue.is_empty(VOID), C_SCOPE);
-- 1. Set defaults, fetch command and log
-------------------------------------------------------------------------
work.td_vvc_entity_support_pkg.fetch_command_and_prepare_executor(v_cmd, command_queue, vvc_config, vvc_status, queue_is_increasing, executor_is_busy, C_VVC_LABELS);
-- update vvc activity. Note that clock generator VVC activity is not included in the resetting of the VVC activity register!
-- update_vvc_activity_register(global_trigger_vvc_activity_register, vvc_status, ACTIVE, entry_num_in_vvc_activity_register, last_cmd_idx_executed, command_queue.is_empty(VOID), C_SCOPE);
-- Select between a provided msg_id_panel via the vvc_cmd_record from a VVC with a higher hierarchy or the
-- msg_id_panel in this VVC's config. This is to correctly handle the logging when using Hierarchical-VVCs.
v_msg_id_panel := get_msg_id_panel(v_cmd, vvc_config);
-- 2. Execute the fetched command
-------------------------------------------------------------------------
case v_cmd.operation is -- Only operations in the dedicated record are relevant
-- VVC dedicated operations
--===================================
when START_CLOCK =>
if clock_ena then
tb_error("Clock " & clock_name & " already running. " & format_msg(v_cmd), C_SCOPE);
else
clock_ena <= true;
wait for 0 ns;
log(ID_CLOCK_GEN, "Clock '" & clock_name & "' started", C_SCOPE);
end if;
when STOP_CLOCK =>
if not clock_ena then
tb_error("Clock '" & clock_name & "' already stopped. " & format_msg(v_cmd), C_SCOPE);
else
clock_ena <= false;
if clk then
wait until not clk;
end if;
log(ID_CLOCK_GEN, "Clock '" & clock_name & "' stopped", C_SCOPE);
end if;
when SET_CLOCK_PERIOD =>
clock_period := v_cmd.clock_period;
log(ID_CLOCK_GEN, "Clock '" & clock_name & "' period set to " & to_string(clock_period), C_SCOPE);
when SET_CLOCK_HIGH_TIME =>
clock_high_time := v_cmd.clock_high_time;
log(ID_CLOCK_GEN, "Clock '" & clock_name & "' high time set to " & to_string(clock_high_time), C_SCOPE);
-- UVVM common operations
--===================================
when INSERT_DELAY =>
log(ID_INSERTED_DELAY, "Running: " & to_string(v_cmd.proc_call) & " " & format_command_idx(v_cmd), C_SCOPE, v_msg_id_panel);
if v_cmd.gen_integer_array(0) = -1 then
-- Delay specified using time
wait until terminate_current_cmd.is_active = '1' for v_cmd.delay;
else
-- Delay specified using integer
wait until terminate_current_cmd.is_active = '1' for v_cmd.gen_integer_array(0) * vvc_config.clock_period;
end if;
when others =>
tb_error("Unsupported local command received for execution: '" & to_string(v_cmd.operation) & "'", C_SCOPE);
end case;
-- Reset terminate flag if any occurred
if (terminate_current_cmd.is_active = '1') then
log(ID_CMD_EXECUTOR, "Termination request received", C_SCOPE, v_msg_id_panel);
uvvm_vvc_framework.ti_vvc_framework_support_pkg.reset_flag(terminate_current_cmd);
end if;
last_cmd_idx_executed <= v_cmd.cmd_idx;
-- Reset the transaction info for waveview
transaction_info := C_TRANSACTION_INFO_DEFAULT;
end loop;
end process;
--========================================================================================================================
--========================================================================================================================
-- Command termination handler
-- - Handles the termination request record (sets and resets terminate flag on request)
--========================================================================================================================
cmd_terminator : uvvm_vvc_framework.ti_vvc_framework_support_pkg.flag_handler(terminate_current_cmd); -- flag: is_active, set, reset
--========================================================================================================================
--========================================================================================================================
-- Clock Generator process
-- - Process that generates the clock signal
--========================================================================================================================
clock_generator : process
variable v_clock_period : time;
variable v_clock_high_time : time;
begin
wait for 0 ns; -- wait for clock_ena to be set
loop
if not clock_ena then
clk <= '0';
wait until clock_ena;
end if;
-- Clock period is sampled so it won't change during a clock cycle and potentialy introduce negative time in
-- last wait statement
v_clock_period := clock_period;
v_clock_high_time := clock_high_time;
if v_clock_high_time >= v_clock_period then
tb_error(clock_name & ": clock period must be larger than clock high time; clock period: " & to_string(v_clock_period) & ", clock high time: " & to_string(clock_high_time), C_SCOPE);
end if;
clk <= '1';
wait for v_clock_high_time;
clk <= '0';
wait for (v_clock_period - v_clock_high_time);
end loop;
end process;
--========================================================================================================================
end architecture behave;
|
mit
|
UVVM/UVVM_All
|
bitvis_vip_axilite/src/axilite_bfm_pkg.vhd
|
1
|
33220
|
--================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
----------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
--=================================================================================================
package axilite_bfm_pkg is
--===============================================================================================
-- Types and constants for AXILITE BFMs
--===============================================================================================
constant C_SCOPE : string := "AXILITE_BFM";
-- EXOKAY not supported for AXI-Lite, will raise TB_FAILURE
type t_xresp is (
OKAY,
SLVERR,
DECERR,
EXOKAY
);
type t_axprot is(
UNPRIVILEGED_NONSECURE_DATA,
UNPRIVILEGED_NONSECURE_INSTRUCTION,
UNPRIVILEGED_SECURE_DATA,
UNPRIVILEGED_SECURE_INSTRUCTION,
PRIVILEGED_NONSECURE_DATA,
PRIVILEGED_NONSECURE_INSTRUCTION,
PRIVILEGED_SECURE_DATA,
PRIVILEGED_SECURE_INSTRUCTION
);
-- Configuration record to be assigned in the test harness.
type t_axilite_bfm_config is record
max_wait_cycles : natural; -- Used for setting the maximum cycles to wait before an alert is issued when waiting for ready and valid signals from the DUT.
max_wait_cycles_severity : t_alert_level; -- The above timeout will have this severity
clock_period : time; -- Period of the clock signal.
clock_period_margin : time; -- Input clock period margin to specified clock_period
clock_margin_severity : t_alert_level; -- The above margin will have this severity
setup_time : time; -- Setup time for generated signals, set to clock_period/4
hold_time : time; -- Hold time for generated signals, set to clock_period/4
bfm_sync : t_bfm_sync; -- Synchronisation of the BFM procedures, i.e. using clock signals, using setup_time and hold_time.
match_strictness : t_match_strictness; -- Matching strictness for std_logic values in check procedures.
expected_response : t_xresp; -- Sets the expected response for both read and write transactions.
expected_response_severity : t_alert_level; -- A response mismatch will have this severity.
protection_setting : t_axprot; -- Sets the AXI access permissions (e.g. write to data/instruction, privileged and secure access).
num_aw_pipe_stages : natural; -- Write Address Channel pipeline steps.
num_w_pipe_stages : natural; -- Write Data Channel pipeline steps.
num_ar_pipe_stages : natural; -- Read Address Channel pipeline steps.
num_r_pipe_stages : natural; -- Read Data Channel pipeline steps.
num_b_pipe_stages : natural; -- Response Channel pipeline steps.
id_for_bfm : t_msg_id; -- The message ID used as a general message ID in the AXI-Lite BFM
id_for_bfm_wait : t_msg_id; -- The message ID used for logging waits in the AXI-Lite BFM
id_for_bfm_poll : t_msg_id; -- The message ID used for logging polling in the AXI-Lite BFM
end record;
constant C_AXILITE_BFM_CONFIG_DEFAULT : t_axilite_bfm_config := (
max_wait_cycles => 10,
max_wait_cycles_severity => TB_FAILURE,
clock_period => -1 ns,
clock_period_margin => 0 ns,
clock_margin_severity => TB_ERROR,
setup_time => -1 ns,
hold_time => -1 ns,
bfm_sync => SYNC_ON_CLOCK_ONLY,
match_strictness => MATCH_EXACT,
expected_response => OKAY,
expected_response_severity => TB_FAILURE,
protection_setting => UNPRIVILEGED_NONSECURE_DATA,
num_aw_pipe_stages => 1,
num_w_pipe_stages => 1,
num_ar_pipe_stages => 1,
num_r_pipe_stages => 1,
num_b_pipe_stages => 1,
id_for_bfm => ID_BFM,
id_for_bfm_wait => ID_BFM_WAIT,
id_for_bfm_poll => ID_BFM_POLL
);
-- AXI-Lite Interface signals
type t_axilite_write_address_channel is record
--DUT inputs
awaddr : std_logic_vector;
awvalid : std_logic;
awprot : std_logic_vector(2 downto 0); -- [0: '0' - unpriviliged access, '1' - priviliged access; 1: '0' - secure access, '1' - non-secure access, 2: '0' - Data access, '1' - Instruction accesss]
--DUT outputs
awready : std_logic;
end record;
type t_axilite_write_data_channel is record
--DUT inputs
wdata : std_logic_vector;
wstrb : std_logic_vector;
wvalid : std_logic;
--DUT outputs
wready : std_logic;
end record;
type t_axilite_write_response_channel is record
--DUT inputs
bready : std_logic;
--DUT outputs
bresp : std_logic_vector(1 downto 0);
bvalid : std_logic;
end record;
type t_axilite_read_address_channel is record
--DUT inputs
araddr : std_logic_vector;
arvalid : std_logic;
arprot : std_logic_vector(2 downto 0); -- [0: '0' - unpriviliged access, '1' - priviliged access; 1: '0' - secure access, '1' - non-secure access, 2: '0' - Data access, '1' - Instruction accesss]
--DUT outputs
arready : std_logic;
end record;
type t_axilite_read_data_channel is record
--DUT inputs
rready : std_logic;
--DUT outputs
rdata : std_logic_vector;
rresp : std_logic_vector(1 downto 0);
rvalid : std_logic;
end record;
type t_axilite_if is record
write_address_channel : t_axilite_write_address_channel;
write_data_channel : t_axilite_write_data_channel;
write_response_channel : t_axilite_write_response_channel;
read_address_channel : t_axilite_read_address_channel;
read_data_channel : t_axilite_read_data_channel;
end record;
--===============================================================================================
-- BFM procedures
--===============================================================================================
------------------------------------------
-- init_axilite_if_signals
------------------------------------------
-- - This function returns an AXILITE interface with initialized signals.
-- - All AXILITE input signals are initialized to 0
-- - All AXILITE output signals are initialized to Z
-- - awprot and arprot are initialized to UNPRIVILEGED_NONSECURE_DATA
function init_axilite_if_signals(
addr_width : natural;
data_width : natural
) return t_axilite_if;
------------------------------------------
-- axilite_write
------------------------------------------
-- This procedure writes data to the AXILITE interface specified in axilite_if
-- - The protection setting is set to UNPRIVILEGED_NONSECURE_DATA in this procedure
-- - The byte enable input is set to 1 for all bytes in this procedure
-- - When the write is completed, a log message is issued with log ID id_for_bfm
procedure axilite_write (
constant addr_value : in unsigned;
constant data_value : in std_logic_vector;
constant msg : in string;
signal clk : in std_logic;
signal axilite_if : inout t_axilite_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axilite_bfm_config := C_AXILITE_BFM_CONFIG_DEFAULT
);
------------------------------------------
-- axilite_write
------------------------------------------
-- This procedure writes data to the AXILITE interface specified in axilite_if
-- - When the write is completed, a log message is issued with log ID id_for_bfm
procedure axilite_write (
constant addr_value : in unsigned;
constant data_value : in std_logic_vector;
constant byte_enable : in std_logic_vector;
constant msg : in string;
signal clk : in std_logic;
signal axilite_if : inout t_axilite_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axilite_bfm_config := C_AXILITE_BFM_CONFIG_DEFAULT
);
------------------------------------------
-- axilite_read
------------------------------------------
-- This procedure reads data from the AXILITE interface specified in axilite_if,
-- and returns the read data in data_value.
procedure axilite_read (
constant addr_value : in unsigned;
variable data_value : out std_logic_vector;
constant msg : in string;
signal clk : in std_logic;
signal axilite_if : inout t_axilite_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axilite_bfm_config := C_AXILITE_BFM_CONFIG_DEFAULT;
constant ext_proc_call : in string := "" -- External proc_call. Overwrite if called from another BFM procedure
);
------------------------------------------
-- axilite_check
------------------------------------------
-- This procedure reads data from the AXILITE interface specified in axilite_if,
-- and compares it to the data in data_exp.
-- - If the received data inconsistent with data_exp, an alert with severity
-- alert_level is issued.
-- - If the received data was correct, a log message with ID id_for_bfm is issued.
procedure axilite_check (
constant addr_value : in unsigned;
constant data_exp : in std_logic_vector;
constant msg : in string;
signal clk : in std_logic;
signal axilite_if : inout t_axilite_if;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axilite_bfm_config := C_AXILITE_BFM_CONFIG_DEFAULT
);
function axprot_to_slv(
axprot : t_axprot
) return std_logic_vector;
function xresp_to_slv(
constant axilite_response_status : in t_xresp;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel
) return std_logic_vector;
end package axilite_bfm_pkg;
--=================================================================================================
--=================================================================================================
package body axilite_bfm_pkg is
----------------------------------------------------
-- Support procedures
----------------------------------------------------
function axprot_to_slv(
axprot : t_axprot
) return std_logic_vector is
variable v_axprot_slv : std_logic_vector(2 downto 0);
begin
case axprot is
when UNPRIVILEGED_SECURE_DATA =>
v_axprot_slv := "000";
when PRIVILEGED_SECURE_DATA =>
v_axprot_slv := "001";
when UNPRIVILEGED_NONSECURE_DATA =>
v_axprot_slv := "010";
when PRIVILEGED_NONSECURE_DATA =>
v_axprot_slv := "011";
when UNPRIVILEGED_SECURE_INSTRUCTION =>
v_axprot_slv := "100";
when PRIVILEGED_SECURE_INSTRUCTION =>
v_axprot_slv := "101";
when UNPRIVILEGED_NONSECURE_INSTRUCTION =>
v_axprot_slv := "110";
when PRIVILEGED_NONSECURE_INSTRUCTION =>
v_axprot_slv := "111";
end case;
return v_axprot_slv;
end function axprot_to_slv;
function xresp_to_slv(
constant axilite_response_status : in t_xresp;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel
) return std_logic_vector is
variable v_axilite_response_status_slv : std_logic_vector(1 downto 0);
begin
check_value(axilite_response_status /= EXOKAY, TB_FAILURE, "EXOKAY response status is not supported in AXI-Lite", scope, ID_NEVER, msg_id_panel);
case axilite_response_status is
when OKAY =>
v_axilite_response_status_slv := "00";
when SLVERR =>
v_axilite_response_status_slv := "10";
when DECERR =>
v_axilite_response_status_slv := "11";
when EXOKAY =>
v_axilite_response_status_slv := "01";
end case;
return v_axilite_response_status_slv;
end function;
----------------------------------------------------
-- BFM procedures
----------------------------------------------------
function init_axilite_if_signals(
addr_width : natural;
data_width : natural
) return t_axilite_if is
variable init_if : t_axilite_if( write_address_channel( awaddr( addr_width -1 downto 0)),
write_data_channel( wdata( data_width -1 downto 0),
wstrb(( data_width/8) -1 downto 0)),
read_address_channel( araddr( addr_width -1 downto 0)),
read_data_channel( rdata( data_width -1 downto 0)));
begin
-- Write Address Channel
init_if.write_address_channel.awaddr := (init_if.write_address_channel.awaddr'range => '0');
init_if.write_address_channel.awvalid := '0';
init_if.write_address_channel.awprot := axprot_to_slv(UNPRIVILEGED_NONSECURE_DATA); --"010"
init_if.write_address_channel.awready := 'Z';
-- Write Data Channel
init_if.write_data_channel.wdata := (init_if.write_data_channel.wdata'range => '0');
init_if.write_data_channel.wstrb := (init_if.write_data_channel.wstrb'range => '0');
init_if.write_data_channel.wvalid := '0';
init_if.write_data_channel.wready := 'Z';
-- Write Response Channel
init_if.write_response_channel.bready := '0';
init_if.write_response_channel.bresp := (init_if.write_response_channel.bresp'range => 'Z');
init_if.write_response_channel.bvalid := 'Z';
-- Read Address Channel
init_if.read_address_channel.araddr := (init_if.read_address_channel.araddr'range => '0');
init_if.read_address_channel.arvalid := '0';
init_if.read_address_channel.arprot := axprot_to_slv(UNPRIVILEGED_NONSECURE_DATA); --"010"
init_if.read_address_channel.arready := 'Z';
-- Read Data Channel
init_if.read_data_channel.rready := '0';
init_if.read_data_channel.rdata := (init_if.read_data_channel.rdata'range => 'Z');
init_if.read_data_channel.rresp := (init_if.read_data_channel.rresp'range => 'Z');
init_if.read_data_channel.rvalid := 'Z';
return init_if;
end function;
procedure axilite_write (
constant addr_value : in unsigned;
constant data_value : in std_logic_vector;
constant msg : in string;
signal clk : in std_logic;
signal axilite_if : inout t_axilite_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axilite_bfm_config := C_AXILITE_BFM_CONFIG_DEFAULT
) is
constant C_BYTE_ENABLE : std_logic_vector(axilite_if.write_data_channel.wstrb'length-1 downto 0) := (others => '1');
begin
axilite_write(addr_value, data_value, C_BYTE_ENABLE, msg, clk, axilite_if, scope, msg_id_panel, config);
end procedure axilite_write;
procedure axilite_write (
constant addr_value : in unsigned;
constant data_value : in std_logic_vector;
constant byte_enable : in std_logic_vector;
constant msg : in string;
signal clk : in std_logic;
signal axilite_if : inout t_axilite_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axilite_bfm_config := C_AXILITE_BFM_CONFIG_DEFAULT
) is
constant proc_call : string := "axilite_write(A:" & to_string(addr_value, HEX, AS_IS, INCL_RADIX) &
", " & to_string(data_value, HEX, AS_IS, INCL_RADIX) & ")";
constant max_pipe_stages : integer := maximum(maximum(config.num_w_pipe_stages, config.num_aw_pipe_stages), config.num_b_pipe_stages);
variable v_await_awready : boolean := true;
variable v_await_wready : boolean := true;
variable v_await_bvalid : boolean := true;
-- Normalize to the DUT addr/data widths
variable v_normalized_addr : std_logic_vector(axilite_if.write_address_channel.awaddr'length-1 downto 0) :=
normalize_and_check(std_logic_vector(addr_value), axilite_if.write_address_channel.awaddr, ALLOW_NARROWER, "addr", "axilite_if.write_address_channel.awaddr", msg);
variable v_normalized_data : std_logic_vector(axilite_if.write_data_channel.wdata'length-1 downto 0) :=
normalize_and_check(data_value, axilite_if.write_data_channel.wdata, ALLOW_NARROWER, "data", "axilite_if.write_data_channel.wdata", msg);
-- Helper variables
variable v_time_of_rising_edge : time := -1 ns; -- time stamp for clk period checking
variable v_time_of_falling_edge : time := -1 ns; -- time stamp for clk period checking
variable v_wready : std_logic;
variable v_awready : std_logic;
begin
check_value(v_normalized_data'length = 32 or v_normalized_data'length = 64, TB_ERROR, "AXI-lite data width must be either 32 or 64!", scope, ID_NEVER, msg_id_panel);
if config.bfm_sync = SYNC_WITH_SETUP_AND_HOLD then
check_value(config.clock_period > -1 ns, TB_FAILURE, "Sanity check: Check that clock_period is set.", scope, ID_NEVER, msg_id_panel, proc_call);
check_value(config.setup_time < config.clock_period/2, TB_FAILURE, "Sanity check: Check that setup_time do not exceed clock_period/2.", scope, ID_NEVER, msg_id_panel, proc_call);
check_value(config.hold_time < config.clock_period/2, TB_FAILURE, "Sanity check: Check that hold_time do not exceed clock_period/2.", scope, ID_NEVER, msg_id_panel, proc_call);
end if;
for cycle in 0 to config.max_wait_cycles loop
-- Wait according to config.bfm_sync setup
wait_on_bfm_sync_start(clk, config.bfm_sync, config.setup_time, config.clock_period, v_time_of_falling_edge, v_time_of_rising_edge);
if cycle = config.num_w_pipe_stages then
axilite_if.write_data_channel.wdata <= v_normalized_data;
axilite_if.write_data_channel.wstrb <= byte_enable;
axilite_if.write_data_channel.wvalid <= '1';
end if;
if cycle = config.num_aw_pipe_stages then
axilite_if.write_address_channel.awaddr <= v_normalized_addr;
axilite_if.write_address_channel.awvalid <= '1';
axilite_if.write_address_channel.awprot <= axprot_to_slv(config.protection_setting);
end if;
wait until rising_edge(clk);
if v_time_of_rising_edge = -1 ns then
v_time_of_rising_edge := now;
end if;
check_clock_period_margin(clk, config.bfm_sync, v_time_of_falling_edge, v_time_of_rising_edge,
config.clock_period, config.clock_period_margin, config.clock_margin_severity);
-- Sample ready signals
v_wready := axilite_if.write_data_channel.wready;
v_awready := axilite_if.write_address_channel.awready;
-- Wait according to config.bfm_sync setup
wait_on_bfm_exit(clk, config.bfm_sync, config.hold_time, v_time_of_falling_edge, v_time_of_rising_edge);
if v_wready = '1' and cycle >= config.num_w_pipe_stages then
axilite_if.write_data_channel.wdata <= (axilite_if.write_data_channel.wdata'range => '0');
axilite_if.write_data_channel.wstrb <= (axilite_if.write_data_channel.wstrb'range => '0');
axilite_if.write_data_channel.wvalid <= '0';
v_await_wready := false;
end if;
if v_awready = '1' and cycle >= config.num_aw_pipe_stages then
axilite_if.write_address_channel.awaddr <= (axilite_if.write_address_channel.awaddr'range => '0');
axilite_if.write_address_channel.awvalid <= '0';
v_await_awready := false;
end if;
if not v_await_awready and not v_await_wready then
exit;
end if;
end loop;
check_value(not v_await_wready, config.max_wait_cycles_severity, ": Timeout waiting for WREADY", scope, ID_NEVER, msg_id_panel, proc_call);
check_value(not v_await_awready, config.max_wait_cycles_severity, ": Timeout waiting for AWREADY", scope, ID_NEVER, msg_id_panel, proc_call);
for cycle in 0 to config.max_wait_cycles loop
-- Wait according to config.bfm_sync setup
wait_on_bfm_sync_start(clk, config.bfm_sync, config.setup_time, config.clock_period, v_time_of_falling_edge, v_time_of_rising_edge);
-- Brady - Add support for num_b_pipe_stages
if cycle = config.num_b_pipe_stages then
axilite_if.write_response_channel.bready <= '1';
end if;
wait until rising_edge(clk);
if v_time_of_rising_edge = -1 ns then
v_time_of_rising_edge := now;
end if;
if axilite_if.write_response_channel.bvalid = '1' and cycle >= config.num_b_pipe_stages then
check_value(axilite_if.write_response_channel.bresp, xresp_to_slv(config.expected_response), config.expected_response_severity, ": BRESP detected", scope, BIN, KEEP_LEADING_0, ID_NEVER, msg_id_panel, proc_call);
-- Wait according to config.bfm_sync setup
wait_on_bfm_exit(clk, config.bfm_sync, config.hold_time, v_time_of_falling_edge, v_time_of_rising_edge);
axilite_if.write_response_channel.bready <= '0';
v_await_bvalid := false;
end if;
if not v_await_bvalid then
exit;
end if;
end loop;
check_value(not v_await_bvalid, config.max_wait_cycles_severity, ": Timeout waiting for BVALID", scope, ID_NEVER, msg_id_panel, proc_call);
log(config.id_for_bfm, proc_call & " completed. " & add_msg_delimiter(msg), scope, msg_id_panel);
end procedure axilite_write;
procedure axilite_read (
constant addr_value : in unsigned;
variable data_value : out std_logic_vector;
constant msg : in string;
signal clk : in std_logic;
signal axilite_if : inout t_axilite_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axilite_bfm_config := C_AXILITE_BFM_CONFIG_DEFAULT;
constant ext_proc_call : in string := "" -- External proc_call. Overwrite if called from another BFM procedure
) is
constant local_proc_name : string := "axilite_read"; -- Local proc_name; used if called from sequncer or VVC
constant local_proc_call : string := local_proc_name & "(A:" & to_string(addr_value, HEX, AS_IS, INCL_RADIX) & ")"; -- Local proc_call; used if called from sequncer or VVC
-- Normalize to the DUT addr/data widths
variable v_normalized_addr : std_logic_vector(axilite_if.read_address_channel.araddr'length-1 downto 0) :=
normalize_and_check(std_logic_vector(addr_value), axilite_if.read_address_channel.araddr, ALLOW_NARROWER, "addr", "axilite_if.read_address_channel.araddr", msg);
-- Helper variables
variable v_proc_call : line;
variable v_await_arready : boolean := true;
variable v_await_rvalid : boolean := true;
variable v_data_value : std_logic_vector(axilite_if.read_data_channel.rdata'length-1 downto 0);
variable v_time_of_rising_edge : time := -1 ns; -- time stamp for clk period checking
variable v_time_of_falling_edge : time := -1 ns; -- time stamp for clk period checking
begin
if config.bfm_sync = SYNC_WITH_SETUP_AND_HOLD then
check_value(config.clock_period > -1 ns, TB_FAILURE, "Sanity check: Check that clock_period is set.", scope, ID_NEVER, msg_id_panel, local_proc_call);
check_value(config.setup_time < config.clock_period/2, TB_FAILURE, "Sanity check: Check that setup_time do not exceed clock_period/2.", scope, ID_NEVER, msg_id_panel, local_proc_call);
check_value(config.hold_time < config.clock_period/2, TB_FAILURE, "Sanity check: Check that hold_time do not exceed clock_period/2.", scope, ID_NEVER, msg_id_panel, local_proc_call);
end if;
if ext_proc_call = "" then
-- Called directly from sequencer/VVC, log 'axilite_read...'
write(v_proc_call, local_proc_call);
else
-- Called from another BFM procedure, log 'ext_proc_call while executing axilite_read...'
write(v_proc_call, ext_proc_call & " while executing " & local_proc_name);
end if;
check_value(v_data_value'length = 32 or v_data_value'length = 64, TB_ERROR, "AXI-lite data width must be either 32 or 64!" & add_msg_delimiter(msg), scope, ID_NEVER, msg_id_panel);
for cycle in 0 to config.max_wait_cycles loop
-- Wait according to config.bfm_sync setup
wait_on_bfm_sync_start(clk, config.bfm_sync, config.setup_time, config.clock_period, v_time_of_falling_edge, v_time_of_rising_edge);
-- Brady - Add support for num_ar_pipe_stages
if cycle = config.num_ar_pipe_stages then
axilite_if.read_address_channel.araddr <= v_normalized_addr;
axilite_if.read_address_channel.arprot <= axprot_to_slv(config.protection_setting);
axilite_if.read_address_channel.arvalid <= '1';
end if;
wait until rising_edge(clk);
if v_time_of_rising_edge = -1 ns then
v_time_of_rising_edge := now;
end if;
check_clock_period_margin(clk, config.bfm_sync, v_time_of_falling_edge, v_time_of_rising_edge,
config.clock_period, config.clock_period_margin, config.clock_margin_severity);
if axilite_if.read_address_channel.arready = '1' and cycle >= config.num_ar_pipe_stages then
-- Wait according to config.bfm_sync setup
wait_on_bfm_exit(clk, config.bfm_sync, config.hold_time, v_time_of_falling_edge, v_time_of_rising_edge);
axilite_if.read_address_channel.araddr <= (axilite_if.read_address_channel.araddr'range => '0');
axilite_if.read_address_channel.arprot <= (others=>'0');
axilite_if.read_address_channel.arvalid <= '0';
v_await_arready := false;
end if;
if not v_await_arready then
exit;
end if;
end loop;
check_value(not v_await_arready, config.max_wait_cycles_severity, ": Timeout waiting for ARREADY", scope, ID_NEVER, msg_id_panel, v_proc_call.all);
for cycle in 0 to config.max_wait_cycles loop
-- Wait according to config.bfm_sync setup
wait_on_bfm_sync_start(clk, config.bfm_sync, config.setup_time, config.clock_period, v_time_of_falling_edge, v_time_of_rising_edge);
-- Brady - Add support for num_r_pipe_stages
if cycle = config.num_r_pipe_stages then
axilite_if.read_data_channel.rready <= '1';
end if;
wait until rising_edge(clk);
if v_time_of_rising_edge = -1 ns then
v_time_of_rising_edge := now;
end if;
if axilite_if.read_data_channel.rvalid = '1' and cycle >= config.num_r_pipe_stages then
v_await_rvalid := false;
check_value(axilite_if.read_data_channel.rresp, xresp_to_slv(config.expected_response), config.expected_response_severity, ": RRESP detected", scope, BIN, KEEP_LEADING_0, ID_NEVER, msg_id_panel, v_proc_call.all);
v_data_value := axilite_if.read_data_channel.rdata;
-- Wait according to config.bfm_sync setup
wait_on_bfm_exit(clk, config.bfm_sync, config.hold_time, v_time_of_falling_edge, v_time_of_rising_edge);
axilite_if.read_data_channel.rready <= '0';
end if;
if not v_await_rvalid then
exit;
end if;
end loop;
check_value(not v_await_rvalid, config.max_wait_cycles_severity, ": Timeout waiting for RVALID", scope, ID_NEVER, msg_id_panel, v_proc_call.all);
data_value := v_data_value;
if ext_proc_call = "" then
log(config.id_for_bfm, v_proc_call.all & "=> " & to_string(v_data_value, HEX, SKIP_LEADING_0, INCL_RADIX) & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
else
-- Log will be handled by calling procedure (e.g. axilite_check)
end if;
DEALLOCATE(v_proc_call);
end procedure axilite_read;
procedure axilite_check (
constant addr_value : in unsigned;
constant data_exp : in std_logic_vector;
constant msg : in string;
signal clk : in std_logic;
signal axilite_if : inout t_axilite_if;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axilite_bfm_config := C_AXILITE_BFM_CONFIG_DEFAULT
) is
constant proc_call : string := "axilite_check(A:" & to_string(addr_value, HEX, AS_IS, INCL_RADIX) & ", " & to_string(data_exp, HEX, AS_IS, INCL_RADIX) & ")";
variable v_data_value : std_logic_vector(axilite_if.write_data_channel.wdata'length-1 downto 0) := (others => '0');
variable v_check_ok : boolean := true;
variable v_alert_radix : t_radix;
-- Normalize to the DUT addr/data widths
variable v_normalized_data : std_logic_vector(axilite_if.write_data_channel.wdata'length-1 downto 0) :=
normalize_and_check(data_exp, axilite_if.write_data_channel.wdata, ALLOW_NARROWER, "data", "axilite_if.write_data_channel.wdata", msg);
begin
axilite_read(addr_value, v_data_value, msg, clk, axilite_if, scope, msg_id_panel, config, proc_call);
for i in v_normalized_data'range loop
-- Allow don't care in expected value and use match strictness from config for comparison
if v_normalized_data(i) = '-' or check_value(v_data_value(i), v_normalized_data(i), config.match_strictness, NO_ALERT, msg, scope, ID_NEVER) then
v_check_ok := true;
else
v_check_ok := false;
exit;
end if;
end loop;
if not v_check_ok then
-- Use binary representation when mismatch is due to weak signals
v_alert_radix := BIN when config.match_strictness = MATCH_EXACT and check_value(v_data_value, v_normalized_data, MATCH_STD, NO_ALERT, msg, scope, HEX_BIN_IF_INVALID, KEEP_LEADING_0, ID_NEVER) else HEX;
alert(alert_level, proc_call & "=> Failed. Was " & to_string(v_data_value, v_alert_radix, AS_IS, INCL_RADIX) & ". Expected " & to_string(v_normalized_data, v_alert_radix, AS_IS, INCL_RADIX) & "." & LF & add_msg_delimiter(msg), scope);
else
log(config.id_for_bfm, proc_call & "=> OK, received data = " & to_string(v_normalized_data, HEX, SKIP_LEADING_0, INCL_RADIX) & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
end if;
end procedure axilite_check;
end package body axilite_bfm_pkg;
|
mit
|
YingcaiDong/Shunting-Model-Based-Path-Planning-Algorithm-Accelerator-Using-FPGA
|
System Design Source FIle/ipshared/xilinx.com/axi_datamover_v5_1/3acd8cae/hdl/src/vhdl/axi_datamover_dre_mux2_1_x_n.vhd
|
18
|
5142
|
-------------------------------------------------------------------------------
-- axi_datamover_dre_mux2_1_x_n.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_dre_mux2_1_x_n.vhd
--
-- Description:
--
-- This VHDL file provides a 2 to 1 xn bit wide mux for the AXI Data Realignment
-- Engine (DRE).
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use ieee.STD_LOGIC_UNSIGNED.all;
use ieee.std_logic_arith.all;
-------------------------------------------------------------------------------
-- Start 2 to 1 xN Mux
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
Entity axi_datamover_dre_mux2_1_x_n is
generic (
C_WIDTH : Integer := 8
-- Sets the bit width of the 2x Mux slice
);
port (
Sel : In std_logic;
-- Mux select control
I0 : In std_logic_vector(C_WIDTH-1 downto 0);
-- Select 0 input
I1 : In std_logic_vector(C_WIDTH-1 downto 0);
-- Select 1 inputl
Y : Out std_logic_vector(C_WIDTH-1 downto 0)
-- Mux output value
);
end entity axi_datamover_dre_mux2_1_x_n; --
Architecture implementation of axi_datamover_dre_mux2_1_x_n is
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: SELECT2_1
--
-- Process Description:
-- This process implements an 2 to 1 mux.
--
-------------------------------------------------------------
SELECT2_1 : process (Sel, I0, I1)
begin
case Sel is
when '0' =>
Y <= I0;
when '1' =>
Y <= I1;
when others =>
Y <= I0;
end case;
end process SELECT2_1;
end implementation; -- axi_datamover_dre_mux2_1_x_n
-------------------------------------------------------------------------------
-- End 2 to 1 xN Mux
-------------------------------------------------------------------------------
|
mit
|
UVVM/UVVM_All
|
bitvis_vip_clock_generator/src/vvc_context.vhd
|
1
|
1609
|
--================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
----------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
context vvc_context is
library bitvis_vip_clock_generator;
use bitvis_vip_clock_generator.vvc_cmd_pkg.all;
use bitvis_vip_clock_generator.vvc_methods_pkg.all;
use bitvis_vip_clock_generator.td_vvc_framework_common_methods_pkg.all;
end context;
|
mit
|
UVVM/UVVM_All
|
bitvis_vip_ethernet/src/ethernet_sb_pkg.vhd
|
1
|
1974
|
--================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
----------------------------------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
---------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library bitvis_vip_scoreboard;
use bitvis_vip_scoreboard.generic_sb_pkg;
use work.support_pkg.all;
--==========================================================================================
--==========================================================================================
package ethernet_sb_pkg is new bitvis_vip_scoreboard.generic_sb_pkg
generic map ( t_element => t_ethernet_frame,
element_match => ethernet_match,
to_string_element => to_string);
|
mit
|
YingcaiDong/Shunting-Model-Based-Path-Planning-Algorithm-Accelerator-Using-FPGA
|
System Design Source FIle/ipshared/xilinx.com/axi_sg_v4_1/0535f152/hdl/src/vhdl/axi_sg_updt_queue.vhd
|
3
|
53827
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_updt_queue.vhd
-- Description: This entity is the descriptor fetch queue interface
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library axi_sg_v4_1;
use axi_sg_v4_1.axi_sg_pkg.all;
library lib_srl_fifo_v1_0;
use lib_srl_fifo_v1_0.srl_fifo_f;
library lib_pkg_v1_0;
use lib_pkg_v1_0.lib_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_updt_queue is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_M_AXIS_UPDT_DATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Memory Map Data Width for Scatter Gather R/W Port
C_S_AXIS_UPDPTR_TDATA_WIDTH : integer range 32 to 32 := 32;
-- 32 Update Status Bits
C_S_AXIS_UPDSTS_TDATA_WIDTH : integer range 33 to 33 := 33;
-- 1 IOC bit + 32 Update Status Bits
C_SG_UPDT_DESC2QUEUE : integer range 0 to 8 := 0;
-- Number of descriptors to fetch and queue for each channel.
-- A value of zero excludes the fetch queues.
C_SG_WORDS_TO_UPDATE : integer range 1 to 16 := 8;
-- Number of words to update
C_SG2_WORDS_TO_UPDATE : integer range 1 to 16 := 8;
-- Number of words to update
C_AXIS_IS_ASYNC : integer range 0 to 1 := 0;
-- Channel 1 is async to sg_aclk
-- 0 = Synchronous to SG ACLK
-- 1 = Asynchronous to SG ACLK
C_INCLUDE_MM2S : integer range 0 to 1 := 0;
C_INCLUDE_S2MM : integer range 0 to 1 := 0;
C_FAMILY : string := "virtex7"
-- Device family used for proper BRAM selection
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
s_axis_updt_aclk : in std_logic ; --
--
--********************************-- --
--** Control and Status **-- --
--********************************-- --
updt_curdesc_wren : out std_logic ; --
updt_curdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
updt_active : in std_logic ; --
updt_queue_empty : out std_logic ; --
updt_ioc : out std_logic ; --
updt_ioc_irq_set : in std_logic ; --
--
dma_interr : out std_logic ; --
dma_slverr : out std_logic ; --
dma_decerr : out std_logic ; --
dma_interr_set : in std_logic ; --
dma_slverr_set : in std_logic ; --
dma_decerr_set : in std_logic ; --
updt2_active : in std_logic ; --
updt2_queue_empty : out std_logic ; --
updt2_ioc : out std_logic ; --
updt2_ioc_irq_set : in std_logic ; --
--
dma2_interr : out std_logic ; --
dma2_slverr : out std_logic ; --
dma2_decerr : out std_logic ; --
dma2_interr_set : in std_logic ; --
dma2_slverr_set : in std_logic ; --
dma2_decerr_set : in std_logic ; --
--
--********************************-- --
--** Update Interfaces In **-- --
--********************************-- --
-- Update Pointer Stream --
s_axis_updtptr_tdata : in std_logic_vector --
(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0); --
s_axis_updtptr_tvalid : in std_logic ; --
s_axis_updtptr_tready : out std_logic ; --
s_axis_updtptr_tlast : in std_logic ; --
--
-- Update Status Stream --
s_axis_updtsts_tdata : in std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); --
s_axis_updtsts_tvalid : in std_logic ; --
s_axis_updtsts_tready : out std_logic ; --
s_axis_updtsts_tlast : in std_logic ; --
s_axis2_updtptr_tdata : in std_logic_vector --
(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0); --
s_axis2_updtptr_tvalid : in std_logic ; --
s_axis2_updtptr_tready : out std_logic ; --
s_axis2_updtptr_tlast : in std_logic ; --
--
-- Update Status Stream --
s_axis2_updtsts_tdata : in std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); --
s_axis2_updtsts_tvalid : in std_logic ; --
s_axis2_updtsts_tready : out std_logic ; --
s_axis2_updtsts_tlast : in std_logic ; --
--
--********************************-- --
--** Update Interfaces Out **-- --
--********************************-- --
-- S2MM Stream Out To DataMover --
m_axis_updt_tdata : out std_logic_vector --
(C_M_AXIS_UPDT_DATA_WIDTH-1 downto 0); --
m_axis_updt_tlast : out std_logic ; --
m_axis_updt_tvalid : out std_logic ; --
m_axis_updt_tready : in std_logic --
);
end axi_sg_updt_queue;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_updt_queue is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
attribute mark_debug : string;
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
constant USE_LOGIC_FIFOS : integer := 0; -- Use Logic FIFOs
constant USE_BRAM_FIFOS : integer := 1; -- Use BRAM FIFOs
-- Number of words deep fifo needs to be. Depth required to store 2 word
-- porters for each descriptor is C_SG_UPDT_DESC2QUEUE x 2
--constant UPDATE_QUEUE_DEPTH : integer := max2(16,C_SG_UPDT_DESC2QUEUE * 2);
constant UPDATE_QUEUE_DEPTH : integer := max2(16,pad_power2(C_SG_UPDT_DESC2QUEUE * 2));
-- Width of fifo rd and wr counts - only used for proper fifo operation
constant UPDATE_QUEUE_CNT_WIDTH : integer := clog2(UPDATE_QUEUE_DEPTH+1);
-- Select between BRAM or LOGIC memory type
constant UPD_Q_MEMORY_TYPE : integer := bo2int(UPDATE_QUEUE_DEPTH > 16);
-- Number of words deep fifo needs to be. Depth required to store all update
-- words is C_SG_UPDT_DESC2QUEUE x C_SG_WORDS_TO_UPDATE
constant UPDATE_STS_QUEUE_DEPTH : integer := max2(16,pad_power2(C_SG_UPDT_DESC2QUEUE
* C_SG_WORDS_TO_UPDATE));
constant UPDATE_STS2_QUEUE_DEPTH : integer := max2(16,pad_power2(C_SG_UPDT_DESC2QUEUE
* C_SG2_WORDS_TO_UPDATE));
-- Select between BRAM or LOGIC memory type
constant STS_Q_MEMORY_TYPE : integer := bo2int(UPDATE_STS_QUEUE_DEPTH > 16);
-- Select between BRAM or LOGIC memory type
constant STS2_Q_MEMORY_TYPE : integer := bo2int(UPDATE_STS2_QUEUE_DEPTH > 16);
-- Width of fifo rd and wr counts - only used for proper fifo operation
constant UPDATE_STS_QUEUE_CNT_WIDTH : integer := clog2(C_SG_UPDT_DESC2QUEUE+1);
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- Channel signals
signal write_curdesc_lsb : std_logic := '0';
signal write_curdesc_lsb_sm : std_logic := '0';
signal write_curdesc_msb : std_logic := '0';
signal write_curdesc_lsb1 : std_logic := '0';
signal write_curdesc_msb1 : std_logic := '0';
signal rden_del : std_logic := '0';
signal updt_active_d1 : std_logic := '0';
signal updt_active_d2 : std_logic := '0';
signal updt_active_re1 : std_logic := '0';
signal updt_active_re2 : std_logic := '0';
signal updt_active_re : std_logic := '0';
type PNTR_STATE_TYPE is (IDLE,
READ_CURDESC_LSB,
READ_CURDESC_MSB,
WRITE_STATUS
);
signal pntr_cs : PNTR_STATE_TYPE;
signal pntr_ns : PNTR_STATE_TYPE;
-- State Machine Signal
signal writing_status : std_logic := '0';
signal dataq_rden : std_logic := '0';
signal stsq_rden : std_logic := '0';
-- Pointer Queue FIFO Signals
signal ptr_queue_rden : std_logic := '0';
signal ptr_queue_wren : std_logic := '0';
signal ptr_queue_empty : std_logic := '0';
signal ptr_queue_full : std_logic := '0';
signal ptr_queue_din : std_logic_vector
(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) := (others => '0');
signal ptr_queue_dout : std_logic_vector
(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) := (others => '0');
signal ptr_queue_dout_int : std_logic_vector
(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) := (others => '0');
-- Status Queue FIFO Signals
signal sts_queue_wren : std_logic := '0';
signal sts_queue_rden : std_logic := '0';
signal sts_queue_din : std_logic_vector
(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal sts_queue_dout : std_logic_vector
(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal sts_queue_dout_int : std_logic_vector (3 downto 0) := (others => '0');
signal sts_queue_full : std_logic := '0';
signal sts_queue_empty : std_logic := '0';
signal ptr2_queue_rden : std_logic := '0';
signal ptr2_queue_wren : std_logic := '0';
signal ptr2_queue_empty : std_logic := '0';
signal ptr2_queue_full : std_logic := '0';
signal ptr2_queue_din : std_logic_vector
(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) := (others => '0');
signal ptr2_queue_dout : std_logic_vector
(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) := (others => '0');
-- Status Queue FIFO Signals
signal sts2_queue_wren : std_logic := '0';
signal sts2_queue_rden : std_logic := '0';
signal sts2_queue_din : std_logic_vector
(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal sts2_queue_dout : std_logic_vector
(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal sts2_queue_full : std_logic := '0';
signal sts2_queue_empty : std_logic := '0';
signal sts2_queue_empty_del : std_logic := '0';
signal sts2_dout_valid : std_logic := '0';
signal sts_dout_valid : std_logic := '0';
signal sts2_dout_valid_del : std_logic := '0';
signal valid_new : std_logic := '0';
signal valid_latch : std_logic := '0';
signal valid1_new : std_logic := '0';
signal valid1_latch : std_logic := '0';
signal empty_low : std_logic := '0';
-- Misc Support Signals
signal writing_status_d1 : std_logic := '0';
signal writing_status_re : std_logic := '0';
signal writing_status_re_ch1 : std_logic := '0';
signal writing_status_re_ch2 : std_logic := '0';
signal sinit : std_logic := '0';
signal updt_tvalid : std_logic := '0';
signal updt_tlast : std_logic := '0';
signal updt2_tvalid : std_logic := '0';
signal updt2_tlast : std_logic := '0';
attribute mark_debug of updt_tvalid : signal is "true";
attribute mark_debug of updt2_tvalid : signal is "true";
attribute mark_debug of updt_tlast : signal is "true";
attribute mark_debug of updt2_tlast : signal is "true";
signal status_d1, status_d2 : std_logic := '0';
signal updt_tvalid_int : std_logic := '0';
signal updt_tlast_int : std_logic := '0';
signal ptr_queue_empty_int : std_logic := '0';
signal updt_active_int : std_logic := '0';
signal follower_reg_mm2s : std_logic_vector (33 downto 0) := (others => '0');
attribute mark_debug of follower_reg_mm2s : signal is "true";
signal follower_full_mm2s :std_logic := '0';
signal follower_empty_mm2s : std_logic := '0';
signal follower_reg_s2mm : std_logic_vector (33 downto 0) := (others => '0');
attribute mark_debug of follower_reg_s2mm : signal is "true";
signal follower_full_s2mm :std_logic := '0';
signal follower_empty_s2mm : std_logic := '0';
signal follower_reg, m_axis_updt_tdata_tmp : std_logic_vector (33 downto 0);
signal follower_full :std_logic := '0';
signal follower_empty : std_logic := '0';
signal sts_rden : std_logic := '0';
signal sts2_rden : std_logic := '0';
signal follower_tlast : std_logic := '0';
signal follower_reg_image : std_logic := '0';
signal m_axis_updt_tready_mm2s, m_axis_updt_tready_s2mm : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
m_axis_updt_tdata <= follower_reg_mm2s (C_S_AXIS_UPDSTS_TDATA_WIDTH-2 downto 0) when updt_active = '1'
else follower_reg_s2mm (C_S_AXIS_UPDSTS_TDATA_WIDTH-2 downto 0) ;
m_axis_updt_tvalid <= updt_tvalid when updt_active = '1'
else updt2_tvalid;
m_axis_updt_tlast <= updt_tlast when updt_active = '1'
else updt2_tlast;
m_axis_updt_tready_mm2s <= m_axis_updt_tready when updt_active = '1' else '0';
m_axis_updt_tready_s2mm <= m_axis_updt_tready when updt2_active = '1' else '0';
-- Asset active strobe on rising edge of update active
-- asertion. This kicks off the update process for
-- channel 1
updt_active_re <= updt_active_re1 or updt_active_re2;
-- Current Descriptor Pointer Fetch. This state machine controls
-- reading out the current pointer from the Queue or channel port
-- and writing it to the update manager for use in command
-- generation to the DataMover for Descriptor update.
CURDESC_PNTR_STATE : process(pntr_cs,
updt_active_re,
ptr_queue_empty_int,
m_axis_updt_tready,
updt_tvalid_int,
updt_tlast_int)
begin
write_curdesc_lsb_sm <= '0';
write_curdesc_msb <= '0';
writing_status <= '0';
dataq_rden <= '0';
stsq_rden <= '0';
pntr_ns <= pntr_cs;
case pntr_cs is
when IDLE =>
if(updt_active_re = '1')then
pntr_ns <= READ_CURDESC_LSB;
else
pntr_ns <= IDLE;
end if;
---------------------------------------------------------------
-- Get lower current descriptor pointer
-- Reads one word from data queue fifo
---------------------------------------------------------------
when READ_CURDESC_LSB =>
-- on tvalid from Queue or channel port then register
-- lsb curdesc and setup to register msb curdesc
if(ptr_queue_empty_int = '0')then
write_curdesc_lsb_sm <= '1';
dataq_rden <= '1';
-- pntr_ns <= READ_CURDESC_MSB;
pntr_ns <= WRITE_STATUS; --READ_CURDESC_MSB;
else
-- coverage off
pntr_ns <= READ_CURDESC_LSB;
-- coverage on
end if;
---------------------------------------------------------------
-- Get upper current descriptor
-- Reads one word from data queue fifo
---------------------------------------------------------------
-- when READ_CURDESC_MSB =>
-- On tvalid from Queue or channel port then register
-- msb. This will also write curdesc out to update
-- manager.
-- if(ptr_queue_empty_int = '0')then
-- dataq_rden <= '1';
-- write_curdesc_msb <= '1';
-- pntr_ns <= WRITE_STATUS;
-- else
-- -- coverage off
-- pntr_ns <= READ_CURDESC_MSB;
-- -- coverage on
-- end if;
---------------------------------------------------------------
-- Hold in this state until remainder of descriptor is
-- written out.
when WRITE_STATUS =>
-- De-MUX appropriage tvalid/tlast signals
writing_status <= '1';
-- Enable reading of Status Queue if datamover can
-- accept data
stsq_rden <= m_axis_updt_tready;
-- Hold in the status state until tlast is pulled
-- from status fifo
if(updt_tvalid_int = '1' and m_axis_updt_tready = '1'
and updt_tlast_int = '1')then
-- if(follower_full = '1' and m_axis_updt_tready = '1'
-- and follower_tlast = '1')then
pntr_ns <= IDLE;
else
pntr_ns <= WRITE_STATUS;
end if;
-- coverage off
when others =>
pntr_ns <= IDLE;
-- coverage on
end case;
end process CURDESC_PNTR_STATE;
updt_tvalid_int <= updt_tvalid or updt2_tvalid;
updt_tlast_int <= updt_tlast or updt2_tlast;
ptr_queue_empty_int <= ptr_queue_empty when updt_active = '1' else
ptr2_queue_empty when updt2_active = '1' else
'1';
---------------------------------------------------------------------------
-- Register for CURDESC Pointer state machine
---------------------------------------------------------------------------
REG_PNTR_STATES : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
pntr_cs <= IDLE;
else
pntr_cs <= pntr_ns;
end if;
end if;
end process REG_PNTR_STATES;
GEN_Q_FOR_SYNC : if C_AXIS_IS_ASYNC = 0 generate
begin
MM2S_CHANNEL : if C_INCLUDE_MM2S = 1 generate
updt_tvalid <= follower_full_mm2s and updt_active;
updt_tlast <= follower_reg_mm2s(C_S_AXIS_UPDSTS_TDATA_WIDTH) and updt_active;
sts_rden <= follower_empty_mm2s and (not sts_queue_empty); -- and updt_active;
VALID_REG_MM2S_ACTIVE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or (m_axis_updt_tready_mm2s = '1' and follower_full_mm2s = '1'))then
-- follower_reg_mm2s <= (others => '0');
follower_full_mm2s <= '0';
follower_empty_mm2s <= '1';
else
if (sts_rden = '1') then
-- follower_reg_mm2s <= sts_queue_dout;
follower_full_mm2s <= '1';
follower_empty_mm2s <= '0';
end if;
end if;
end if;
end process VALID_REG_MM2S_ACTIVE;
VALID_REG_MM2S_ACTIVE1 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
follower_reg_mm2s <= (others => '0');
else
if (sts_rden = '1') then
follower_reg_mm2s <= sts_queue_dout;
end if;
end if;
end if;
end process VALID_REG_MM2S_ACTIVE1;
REG_ACTIVE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
updt_active_d1 <= '0';
else
updt_active_d1 <= updt_active;
end if;
end if;
end process REG_ACTIVE;
updt_active_re1 <= updt_active and not updt_active_d1;
-- I_UPDT_DATA_FIFO : entity lib_srl_fifo_v1_0.srl_fifo_f
-- generic map (
-- C_DWIDTH => 32 ,
-- C_DEPTH => 8 ,
-- C_FAMILY => C_FAMILY
-- )
-- port map (
-- Clk => m_axi_sg_aclk ,
-- Reset => sinit ,
-- FIFO_Write => ptr_queue_wren ,
-- Data_In => ptr_queue_din ,
-- FIFO_Read => ptr_queue_rden ,
-- Data_Out => ptr_queue_dout ,
-- FIFO_Empty => ptr_queue_empty ,
-- FIFO_Full => ptr_queue_full,
-- Addr => open
-- );
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (sinit = '1') then
ptr_queue_dout <= (others => '0');
elsif (ptr_queue_wren = '1') then
ptr_queue_dout <= ptr_queue_din;
end if;
end if;
end process;
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (sinit = '1' or ptr_queue_rden = '1') then
ptr_queue_empty <= '1';
ptr_queue_full <= '0';
elsif (ptr_queue_wren = '1') then
ptr_queue_empty <= '0';
ptr_queue_full <= '1';
end if;
end if;
end process;
-- Channel Pointer Queue (Generate Synchronous FIFO)
-- I_UPDT_STS_FIFO : entity lib_srl_fifo_v1_0.srl_fifo_f
-- generic map (
-- C_DWIDTH => 34 ,
-- C_DEPTH => 4 ,
-- C_FAMILY => C_FAMILY
-- )
-- port map (
-- Clk => m_axi_sg_aclk ,
-- Reset => sinit ,
-- FIFO_Write => sts_queue_wren ,
-- Data_In => sts_queue_din ,
-- FIFO_Read => sts_rden, --sts_queue_rden ,
-- Data_Out => sts_queue_dout ,
-- FIFO_Empty => sts_queue_empty ,
-- FIFO_Full => sts_queue_full ,
-- Addr => open
-- );
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (sinit = '1') then
sts_queue_dout <= (others => '0');
elsif (sts_queue_wren = '1') then
sts_queue_dout <= sts_queue_din;
end if;
end if;
end process;
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (sinit = '1' or sts_rden = '1') then
sts_queue_empty <= '1';
sts_queue_full <= '0';
elsif (sts_queue_wren = '1') then
sts_queue_empty <= '0';
sts_queue_full <= '1';
end if;
end if;
end process;
-- Channel Status Queue (Generate Synchronous FIFO)
--*****************************************
--** Channel Data Port Side of Queues
--*****************************************
-- Pointer Queue Update - Descriptor Pointer (32bits)
-- i.e. 2 current descriptor pointers and any app fields
ptr_queue_din(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) <= s_axis_updtptr_tdata( -- DESC DATA
C_S_AXIS_UPDPTR_TDATA_WIDTH-1
downto 0);
-- Data Queue Write Enable - based on tvalid and queue not full
ptr_queue_wren <= s_axis_updtptr_tvalid -- TValid
and not ptr_queue_full; -- Data Queue NOT Full
-- Drive channel port with ready if room in data queue
s_axis_updtptr_tready <= not ptr_queue_full;
--*****************************************
--** Channel Status Port Side of Queues
--*****************************************
-- Status Queue Update - TLAST(1bit) & Includes IOC(1bit) & Descriptor Status(32bits)
-- Note: Type field is stripped off
sts_queue_din(C_S_AXIS_UPDSTS_TDATA_WIDTH) <= s_axis_updtsts_tlast; -- Store with tlast
sts_queue_din(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0) <= s_axis_updtsts_tdata( -- IOC & DESC STS
C_S_AXIS_UPDSTS_TDATA_WIDTH-1
downto 0);
-- Status Queue Write Enable - based on tvalid and queue not full
sts_queue_wren <= s_axis_updtsts_tvalid
and not sts_queue_full;
-- Drive channel port with ready if room in status queue
s_axis_updtsts_tready <= not sts_queue_full;
--*************************************
--** SG Engine Side of Queues
--*************************************
-- Indicate NOT empty if both status queue and data queue are not empty
-- updt_queue_empty <= ptr_queue_empty
-- or (sts_queue_empty and follower_empty and updt_active);
updt_queue_empty <= ptr_queue_empty
or follower_empty_mm2s; -- and updt_active);
-- Data queue read enable
ptr_queue_rden <= '1' when dataq_rden = '1' -- Cur desc read enable
and ptr_queue_empty = '0' -- Data Queue NOT empty
and updt_active = '1'
else '0';
-- Status queue read enable
sts_queue_rden <= '1' when stsq_rden = '1' -- Writing desc status
and sts_queue_empty = '0' -- Status fifo NOT empty
and updt_active = '1'
else '0';
-----------------------------------------------------------------------
-- TVALID - status queue not empty and writing status
-----------------------------------------------------------------------
-----------------------------------------------------------------------
-- TLAST - status queue not empty, writing status, and last asserted
-----------------------------------------------------------------------
-- Drive last as long as tvalid is asserted and last from fifo
-- is asserted
end generate MM2S_CHANNEL;
NO_MM2S_CHANNEL : if C_INCLUDE_MM2S = 0 generate
begin
updt_active_re1 <= '0';
updt_queue_empty <= '0';
s_axis_updtptr_tready <= '0';
s_axis_updtsts_tready <= '0';
sts_queue_dout <= (others => '0');
sts_queue_full <= '0';
sts_queue_empty <= '0';
ptr_queue_dout <= (others => '0');
ptr_queue_empty <= '0';
ptr_queue_full <= '0';
end generate NO_MM2S_CHANNEL;
S2MM_CHANNEL : if C_INCLUDE_S2MM = 1 generate
begin
updt2_tvalid <= follower_full_s2mm and updt2_active;
updt2_tlast <= follower_reg_s2mm(C_S_AXIS_UPDSTS_TDATA_WIDTH) and updt2_active;
sts2_rden <= follower_empty_s2mm and (not sts2_queue_empty); -- and updt2_active;
VALID_REG_S2MM_ACTIVE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or (m_axis_updt_tready_s2mm = '1' and follower_full_s2mm = '1'))then
-- follower_reg_s2mm <= (others => '0');
follower_full_s2mm <= '0';
follower_empty_s2mm <= '1';
else
if (sts2_rden = '1') then
-- follower_reg_s2mm <= sts2_queue_dout;
follower_full_s2mm <= '1';
follower_empty_s2mm <= '0';
end if;
end if;
end if;
end process VALID_REG_S2MM_ACTIVE;
VALID_REG_S2MM_ACTIVE1 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
follower_reg_s2mm <= (others => '0');
else
if (sts2_rden = '1') then
follower_reg_s2mm <= sts2_queue_dout;
end if;
end if;
end if;
end process VALID_REG_S2MM_ACTIVE1;
REG2_ACTIVE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
updt_active_d2 <= '0';
else
updt_active_d2 <= updt2_active;
end if;
end if;
end process REG2_ACTIVE;
updt_active_re2 <= updt2_active and not updt_active_d2;
-- I_UPDT2_DATA_FIFO : entity lib_srl_fifo_v1_0.srl_fifo_f
-- generic map (
-- C_DWIDTH => 32 ,
-- C_DEPTH => 8 ,
-- C_FAMILY => C_FAMILY
-- )
-- port map (
-- Clk => m_axi_sg_aclk ,
-- Reset => sinit ,
-- FIFO_Write => ptr2_queue_wren ,
-- Data_In => ptr2_queue_din ,
-- FIFO_Read => ptr2_queue_rden ,
-- Data_Out => ptr2_queue_dout ,
-- FIFO_Empty => ptr2_queue_empty ,
-- FIFO_Full => ptr2_queue_full,
-- Addr => open
-- );
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (sinit = '1') then
ptr2_queue_dout <= (others => '0');
elsif (ptr2_queue_wren = '1') then
ptr2_queue_dout <= ptr2_queue_din;
end if;
end if;
end process;
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (sinit = '1' or ptr2_queue_rden = '1') then
ptr2_queue_empty <= '1';
ptr2_queue_full <= '0';
elsif (ptr2_queue_wren = '1') then
ptr2_queue_empty <= '0';
ptr2_queue_full <= '1';
end if;
end if;
end process;
APP_UPDATE: if C_SG2_WORDS_TO_UPDATE /= 1 generate
begin
I_UPDT2_STS_FIFO : entity lib_srl_fifo_v1_0.srl_fifo_f
generic map (
C_DWIDTH => 34 ,
C_DEPTH => 12 ,
C_FAMILY => C_FAMILY
)
port map (
Clk => m_axi_sg_aclk ,
Reset => sinit ,
FIFO_Write => sts2_queue_wren ,
Data_In => sts2_queue_din ,
FIFO_Read => sts2_rden,
Data_Out => sts2_queue_dout ,
FIFO_Empty => sts2_queue_empty ,
FIFO_Full => sts2_queue_full ,
Addr => open
);
end generate APP_UPDATE;
NO_APP_UPDATE: if C_SG2_WORDS_TO_UPDATE = 1 generate
begin
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (sinit = '1') then
sts2_queue_dout <= (others => '0');
elsif (sts2_queue_wren = '1') then
sts2_queue_dout <= sts2_queue_din;
end if;
end if;
end process;
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (sinit = '1' or sts2_rden = '1') then
sts2_queue_empty <= '1';
sts2_queue_full <= '0';
elsif (sts2_queue_wren = '1') then
sts2_queue_empty <= '0';
sts2_queue_full <= '1';
end if;
end if;
end process;
end generate NO_APP_UPDATE;
-- Pointer Queue Update - Descriptor Pointer (32bits)
-- i.e. 2 current descriptor pointers and any app fields
ptr2_queue_din(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) <= s_axis2_updtptr_tdata( -- DESC DATA
C_S_AXIS_UPDPTR_TDATA_WIDTH-1
downto 0);
-- Data Queue Write Enable - based on tvalid and queue not full
ptr2_queue_wren <= s_axis2_updtptr_tvalid -- TValid
and not ptr2_queue_full; -- Data Queue NOT Full
-- Drive channel port with ready if room in data queue
s_axis2_updtptr_tready <= not ptr2_queue_full;
--*****************************************
--** Channel Status Port Side of Queues
--*****************************************
-- Status Queue Update - TLAST(1bit) & Includes IOC(1bit) & Descriptor Status(32bits)
-- Note: Type field is stripped off
sts2_queue_din(C_S_AXIS_UPDSTS_TDATA_WIDTH) <= s_axis2_updtsts_tlast; -- Store with tlast
sts2_queue_din(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0) <= s_axis2_updtsts_tdata( -- IOC & DESC STS
C_S_AXIS_UPDSTS_TDATA_WIDTH-1
downto 0);
-- Status Queue Write Enable - based on tvalid and queue not full
sts2_queue_wren <= s_axis2_updtsts_tvalid
and not sts2_queue_full;
-- Drive channel port with ready if room in status queue
s_axis2_updtsts_tready <= not sts2_queue_full;
--*************************************
--** SG Engine Side of Queues
--*************************************
-- Indicate NOT empty if both status queue and data queue are not empty
updt2_queue_empty <= ptr2_queue_empty
or follower_empty_s2mm; --or (sts2_queue_empty and follower_empty and updt2_active);
-- Data queue read enable
ptr2_queue_rden <= '1' when dataq_rden = '1' -- Cur desc read enable
and ptr2_queue_empty = '0' -- Data Queue NOT empty
and updt2_active = '1'
else '0';
-- Status queue read enable
sts2_queue_rden <= '1' when stsq_rden = '1' -- Writing desc status
and sts2_queue_empty = '0' -- Status fifo NOT empty
and updt2_active = '1'
else '0';
end generate S2MM_CHANNEL;
NO_S2MM_CHANNEL : if C_INCLUDE_S2MM = 0 generate
begin
updt_active_re2 <= '0';
updt2_queue_empty <= '0';
s_axis2_updtptr_tready <= '0';
s_axis2_updtsts_tready <= '0';
sts2_queue_dout <= (others => '0');
sts2_queue_full <= '0';
sts2_queue_empty <= '0';
ptr2_queue_dout <= (others => '0');
ptr2_queue_empty <= '0';
ptr2_queue_full <= '0';
end generate NO_S2MM_CHANNEL;
end generate GEN_Q_FOR_SYNC;
-- FIFO Reset is active high
sinit <= not m_axi_sg_aresetn;
-- LSB_PROC : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- if(m_axi_sg_aresetn = '0' )then
-- write_curdesc_lsb <= '0';
-- -- Capture lower pointer from FIFO or channel port
-- else -- if(write_curdesc_lsb = '1' and updt_active_int = '1')then
write_curdesc_lsb <= write_curdesc_lsb_sm;
-- end if;
-- end if;
-- end process LSB_PROC;
--*********************************************************************
--** POINTER CAPTURE LOGIC
--*********************************************************************
ptr_queue_dout_int <= ptr2_queue_dout when (updt2_active = '1') else
ptr_queue_dout;
---------------------------------------------------------------------------
-- Write lower order Next Descriptor Pointer out to pntr_mngr
---------------------------------------------------------------------------
updt_active_int <= updt_active or updt2_active;
REG_LSB_CURPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
updt_curdesc(31 downto 0) <= (others => '0');
-- Capture lower pointer from FIFO or channel port
elsif(write_curdesc_lsb = '1' and updt_active_int = '1')then
updt_curdesc(31 downto 0) <= ptr_queue_dout_int(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0);
end if;
end if;
end process REG_LSB_CURPNTR;
---------------------------------------------------------------------------
-- 64 Bit Scatter Gather addresses enabled
---------------------------------------------------------------------------
GEN_UPPER_MSB_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 64 generate
begin
---------------------------------------------------------------------------
-- Write upper order Next Descriptor Pointer out to pntr_mngr
---------------------------------------------------------------------------
REG_MSB_CURPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
updt_curdesc(63 downto 32) <= (others => '0');
updt_curdesc_wren <= '0';
-- Capture upper pointer from FIFO or channel port
-- and also write curdesc out
elsif(write_curdesc_msb = '1' and updt_active_int = '1')then
updt_curdesc(63 downto 32) <= ptr_queue_dout_int(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0);
updt_curdesc_wren <= '1';
-- Assert tready/wren for only 1 clock
else
updt_curdesc_wren <= '0';
end if;
end if;
end process REG_MSB_CURPNTR;
end generate GEN_UPPER_MSB_CURDESC;
---------------------------------------------------------------------------
-- 32 Bit Scatter Gather addresses enabled
---------------------------------------------------------------------------
GEN_NO_UPR_MSB_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
-----------------------------------------------------------------------
-- No upper order therefore dump fetched word and write pntr lower next
-- pointer to pntr mngr
-----------------------------------------------------------------------
REG_MSB_CURPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
updt_curdesc_wren <= '0';
-- Throw away second word, only write curdesc out with msb
-- set to zero
elsif(write_curdesc_lsb = '1' and updt_active_int = '1')then
--elsif(write_curdesc_msb = '1' and updt_active_int = '1')then
updt_curdesc_wren <= '1';
-- Assert for only 1 clock
else
updt_curdesc_wren <= '0';
end if;
end if;
end process REG_MSB_CURPNTR;
end generate GEN_NO_UPR_MSB_CURDESC;
--*********************************************************************
--** ERROR CAPTURE LOGIC
--*********************************************************************
-----------------------------------------------------------------------
-- Generate rising edge pulse on writing status signal. This will
-- assert at the beginning of the status write. Coupled with status
-- fifo set to first word fall through status will be on dout
-- regardless of target ready.
-----------------------------------------------------------------------
REG_WRITE_STATUS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
writing_status_d1 <= '0';
else
writing_status_d1 <= writing_status;
end if;
end if;
end process REG_WRITE_STATUS;
writing_status_re <= writing_status and not writing_status_d1;
writing_status_re_ch1 <= writing_status_re and updt_active;
writing_status_re_ch2 <= writing_status_re and updt2_active;
-----------------------------------------------------------------------
-- Caputure IOC begin set
-----------------------------------------------------------------------
REG_IOC_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt_ioc_irq_set = '1')then
updt_ioc <= '0';
elsif(writing_status_re_ch1 = '1')then
-- updt_ioc <= sts_queue_dout(DESC_IOC_TAG_BIT) and updt_active;
updt_ioc <= follower_reg_mm2s(DESC_IOC_TAG_BIT);
end if;
end if;
end process REG_IOC_PROCESS;
-----------------------------------------------------------------------
-- Capture DMA Internal Errors
-----------------------------------------------------------------------
CAPTURE_DMAINT_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma_interr_set = '1')then
dma_interr <= '0';
elsif(writing_status_re_ch1 = '1')then
--dma_interr <= sts_queue_dout(DESC_STS_INTERR_BIT) and updt_active;
dma_interr <= follower_reg_mm2s(DESC_STS_INTERR_BIT);
end if;
end if;
end process CAPTURE_DMAINT_ERROR;
-----------------------------------------------------------------------
-- Capture DMA Slave Errors
-----------------------------------------------------------------------
CAPTURE_DMASLV_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma_slverr_set = '1')then
dma_slverr <= '0';
elsif(writing_status_re_ch1 = '1')then
-- dma_slverr <= sts_queue_dout(DESC_STS_SLVERR_BIT) and updt_active;
dma_slverr <= follower_reg_mm2s(DESC_STS_SLVERR_BIT);
end if;
end if;
end process CAPTURE_DMASLV_ERROR;
-----------------------------------------------------------------------
-- Capture DMA Decode Errors
-----------------------------------------------------------------------
CAPTURE_DMADEC_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma_decerr_set = '1')then
dma_decerr <= '0';
elsif(writing_status_re_ch1 = '1')then
-- dma_decerr <= sts_queue_dout(DESC_STS_DECERR_BIT) and updt_active;
dma_decerr <= follower_reg_mm2s(DESC_STS_DECERR_BIT);
end if;
end if;
end process CAPTURE_DMADEC_ERROR;
-----------------------------------------------------------------------
-- Caputure IOC begin set
-----------------------------------------------------------------------
REG_IOC2_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt2_ioc_irq_set = '1')then
updt2_ioc <= '0';
elsif(writing_status_re_ch2 = '1')then
-- updt2_ioc <= sts2_queue_dout(DESC_IOC_TAG_BIT) and updt2_active;
updt2_ioc <= follower_reg_s2mm(DESC_IOC_TAG_BIT);
end if;
end if;
end process REG_IOC2_PROCESS;
-----------------------------------------------------------------------
-- Capture DMA Internal Errors
-----------------------------------------------------------------------
CAPTURE_DMAINT2_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma2_interr_set = '1')then
dma2_interr <= '0';
elsif(writing_status_re_ch2 = '1')then
-- dma2_interr <= sts2_queue_dout(DESC_STS_INTERR_BIT) and updt2_active;
dma2_interr <= follower_reg_s2mm (DESC_STS_INTERR_BIT);
end if;
end if;
end process CAPTURE_DMAINT2_ERROR;
-----------------------------------------------------------------------
-- Capture DMA Slave Errors
-----------------------------------------------------------------------
CAPTURE_DMASLV2_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma2_slverr_set = '1')then
dma2_slverr <= '0';
elsif(writing_status_re_ch2 = '1')then
-- dma2_slverr <= sts2_queue_dout(DESC_STS_SLVERR_BIT) and updt2_active;
dma2_slverr <= follower_reg_s2mm(DESC_STS_SLVERR_BIT);
end if;
end if;
end process CAPTURE_DMASLV2_ERROR;
-----------------------------------------------------------------------
-- Capture DMA Decode Errors
-----------------------------------------------------------------------
CAPTURE_DMADEC2_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma2_decerr_set = '1')then
dma2_decerr <= '0';
elsif(writing_status_re_ch2 = '1')then
-- dma2_decerr <= sts2_queue_dout(DESC_STS_DECERR_BIT) and updt2_active;
dma2_decerr <= follower_reg_s2mm(DESC_STS_DECERR_BIT);
end if;
end if;
end process CAPTURE_DMADEC2_ERROR;
end implementation;
|
mit
|
Bjay1435/capstone
|
Geoff/Geoff.srcs/sources_1/bd/dma_loopback/ipshared/xilinx.com/axi_sg_v4_1/hdl/src/vhdl/axi_sg_updt_sm.vhd
|
1
|
41813
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_updt_sm.vhd
-- Description: This entity manages updating of descriptors.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_sg_v4_1_3;
use axi_sg_v4_1_3.axi_sg_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_updt_sm is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_INCLUDE_CH1 : integer range 0 to 1 := 1;
-- Include or Exclude channel 1 scatter gather engine
-- 0 = Exclude Channel 1 SG Engine
-- 1 = Include Channel 1 SG Engine
C_INCLUDE_CH2 : integer range 0 to 1 := 1;
-- Include or Exclude channel 2 scatter gather engine
-- 0 = Exclude Channel 2 SG Engine
-- 1 = Include Channel 2 SG Engine
C_SG_CH1_WORDS_TO_UPDATE : integer range 1 to 16 := 8;
-- Number of words to fetch
C_SG_CH1_FIRST_UPDATE_WORD : integer range 0 to 15 := 0;
-- Starting update word offset
C_SG_CH2_WORDS_TO_UPDATE : integer range 1 to 16 := 8;
-- Number of words to fetch
C_SG_CH2_FIRST_UPDATE_WORD : integer range 0 to 15 := 0
-- Starting update word offset
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
ftch_error : in std_logic ; --
--
-- Channel 1 Control and Status --
ch1_updt_queue_empty : in std_logic ; --
ch1_updt_curdesc_wren : in std_logic ; --
ch1_updt_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch1_updt_ioc : in std_logic ; --
ch1_dma_interr : in std_logic ; --
ch1_dma_slverr : in std_logic ; --
ch1_dma_decerr : in std_logic ; --
ch1_updt_active : out std_logic ; --
ch1_updt_idle : out std_logic ; --
ch1_updt_interr_set : out std_logic ; --
ch1_updt_slverr_set : out std_logic ; --
ch1_updt_decerr_set : out std_logic ; --
ch1_dma_interr_set : out std_logic ; --
ch1_dma_slverr_set : out std_logic ; --
ch1_dma_decerr_set : out std_logic ; --
ch1_updt_ioc_irq_set : out std_logic ; --
ch1_updt_done : out std_logic ; --
--
-- Channel 2 Control and Status --
ch2_updt_queue_empty : in std_logic ; --
-- ch2_updt_curdesc_wren : in std_logic ; --
-- ch2_updt_curdesc : in std_logic_vector --
-- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch2_updt_ioc : in std_logic ; --
ch2_dma_interr : in std_logic ; --
ch2_dma_slverr : in std_logic ; --
ch2_dma_decerr : in std_logic ; --
ch2_updt_active : out std_logic ; --
ch2_updt_idle : out std_logic ; --
ch2_updt_interr_set : out std_logic ; --
ch2_updt_slverr_set : out std_logic ; --
ch2_updt_decerr_set : out std_logic ; --
ch2_dma_interr_set : out std_logic ; --
ch2_dma_slverr_set : out std_logic ; --
ch2_dma_decerr_set : out std_logic ; --
ch2_updt_ioc_irq_set : out std_logic ; --
ch2_updt_done : out std_logic ; --
--
-- DataMover Command --
updt_cmnd_wr : out std_logic ; --
updt_cmnd_data : out std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH --
+CMD_BASE_WIDTH)-1 downto 0) ; --
-- DataMover Status --
updt_done : in std_logic ; --
updt_error : in std_logic ; --
updt_interr : in std_logic ; --
updt_slverr : in std_logic ; --
updt_decerr : in std_logic ; --
updt_error_addr : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) --
);
end axi_sg_updt_sm;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_updt_sm is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- DataMover Commmand TAG
constant UPDATE_CMD_TAG : std_logic_vector(3 downto 0) := (others => '0');
-- DataMover Command Type
-- Always set to INCR type
constant UPDATE_CMD_TYPE : std_logic := '1';
-- DataMover Cmnd Reserved Bits
constant UPDATE_MSB_IGNORED : std_logic_vector(7 downto 0) := (others => '0');
-- DataMover Cmnd Reserved Bits
constant UPDATE_LSB_IGNORED : std_logic_vector(15 downto 0) := (others => '0');
-- DataMover Cmnd Bytes to Xfer for Channel 1
constant UPDATE_CH1_CMD_BTT : std_logic_vector(SG_BTT_WIDTH-1 downto 0)
:= std_logic_vector(to_unsigned(
(C_SG_CH1_WORDS_TO_UPDATE*4),SG_BTT_WIDTH));
-- DataMover Cmnd Bytes to Xfer for Channel 2
constant UPDATE_CH2_CMD_BTT : std_logic_vector(SG_BTT_WIDTH-1 downto 0)
:= std_logic_vector(to_unsigned(
(C_SG_CH2_WORDS_TO_UPDATE*4),SG_BTT_WIDTH));
-- DataMover Cmnd Reserved Bits
constant UPDATE_CMD_RSVD : std_logic_vector(
DATAMOVER_CMD_RSVMSB_BOFST + C_M_AXI_SG_ADDR_WIDTH downto
DATAMOVER_CMD_RSVLSB_BOFST + C_M_AXI_SG_ADDR_WIDTH)
:= (others => '0');
-- DataMover Cmnd Address Offset for channel 1
constant UPDATE_CH1_ADDR_OFFSET : integer := C_SG_CH1_FIRST_UPDATE_WORD*4;
-- DataMover Cmnd Address Offset for channel 2
constant UPDATE_CH2_ADDR_OFFSET : integer := C_SG_CH2_FIRST_UPDATE_WORD*4;
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
type SG_UPDATE_STATE_TYPE is (
IDLE,
GET_UPDATE_PNTR,
UPDATE_DESCRIPTOR,
UPDATE_STATUS,
UPDATE_ERROR
);
signal updt_cs : SG_UPDATE_STATE_TYPE;
signal updt_ns : SG_UPDATE_STATE_TYPE;
-- State Machine Signals
signal ch1_active_set : std_logic := '0';
signal ch2_active_set : std_logic := '0';
signal write_cmnd_cmb : std_logic := '0';
signal ch1_updt_sm_idle : std_logic := '0';
signal ch2_updt_sm_idle : std_logic := '0';
-- Misc Signals
signal ch1_active_i : std_logic := '0';
signal service_ch1 : std_logic := '0';
signal ch2_active_i : std_logic := '0';
signal service_ch2 : std_logic := '0';
signal update_address : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal update_cmd_btt : std_logic_vector
(SG_BTT_WIDTH-1 downto 0) := (others => '0');
signal update_tag : std_logic_vector (3 downto 0);
signal updt_ioc_irq_set : std_logic := '0';
signal ch1_interr_catch : std_logic := '0';
signal ch2_interr_catch : std_logic := '0';
signal ch1_decerr_catch : std_logic := '0';
signal ch2_decerr_catch : std_logic := '0';
signal ch1_slverr_catch : std_logic := '0';
signal ch2_slverr_catch : std_logic := '0';
signal updt_cmnd_data_int : std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH --
+CMD_BASE_WIDTH)-1 downto 0) ; --
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
ch1_updt_active <= ch1_active_i;
ch2_updt_active <= ch2_active_i;
-------------------------------------------------------------------------------
-- Scatter Gather Fetch State Machine
-------------------------------------------------------------------------------
SG_UPDT_MACHINE : process(updt_cs,
ch1_active_i,
ch2_active_i,
service_ch1,
service_ch2,
ch1_updt_curdesc_wren,
-- ch2_updt_curdesc_wren,
updt_error,
updt_done)
begin
-- Default signal assignment
ch1_active_set <= '0';
ch2_active_set <= '0';
write_cmnd_cmb <= '0';
ch1_updt_sm_idle <= '0';
ch2_updt_sm_idle <= '0';
updt_ns <= updt_cs;
case updt_cs is
-------------------------------------------------------------------
when IDLE =>
ch1_updt_sm_idle <= not service_ch1;
ch2_updt_sm_idle <= not service_ch2;
-- error during update - therefore shut down
if(updt_error = '1')then
updt_ns <= UPDATE_ERROR;
-- If channel 1 is running and not idle and queue is not full
-- then fetch descriptor for channel 1
elsif(service_ch1 = '1')then
ch1_active_set <= '1';
updt_ns <= GET_UPDATE_PNTR;
-- If channel 2 is running and not idle and queue is not full
-- then fetch descriptor for channel 2
elsif(service_ch2 = '1')then
ch2_active_set <= '1';
updt_ns <= GET_UPDATE_PNTR;
else
updt_ns <= IDLE;
end if;
when GET_UPDATE_PNTR =>
if(ch1_updt_curdesc_wren = '1')then
updt_ns <= UPDATE_DESCRIPTOR;
else
updt_ns <= GET_UPDATE_PNTR;
end if;
-- if(ch1_updt_curdesc_wren = '1' or ch2_updt_curdesc_wren = '1')then
-- updt_ns <= UPDATE_DESCRIPTOR;
-- else
-- updt_ns <= GET_UPDATE_PNTR;
-- end if;
-------------------------------------------------------------------
when UPDATE_DESCRIPTOR =>
-- error during update - therefore shut down
if(updt_error = '1')then
-- coverage off
updt_ns <= UPDATE_ERROR;
-- coverage on
-- write command
else
ch1_updt_sm_idle <= not ch1_active_i and not service_ch1;
ch2_updt_sm_idle <= not ch2_active_i and not service_ch2;
write_cmnd_cmb <= '1';
updt_ns <= UPDATE_STATUS;
end if;
-------------------------------------------------------------------
when UPDATE_STATUS =>
ch1_updt_sm_idle <= not ch1_active_i and not service_ch1;
ch2_updt_sm_idle <= not ch2_active_i and not service_ch2;
-- error during update - therefore shut down
if(updt_error = '1')then
-- coverage off
updt_ns <= UPDATE_ERROR;
-- coverage on
-- wait until done with update
elsif(updt_done = '1')then
-- If just finished fethcing for channel 2 then...
if(ch2_active_i = '1')then
-- If ready, update descriptor for channel 1
if(service_ch1 = '1')then
ch1_active_set <= '1';
updt_ns <= GET_UPDATE_PNTR;
-- Otherwise return to IDLE
else
updt_ns <= IDLE;
end if;
-- If just finished fethcing for channel 1 then...
elsif(ch1_active_i = '1')then
-- If ready, update descriptor for channel 2
if(service_ch2 = '1')then
ch2_active_set <= '1';
updt_ns <= GET_UPDATE_PNTR;
-- Otherwise return to IDLE
else
updt_ns <= IDLE;
end if;
else
-- coverage off
updt_ns <= IDLE;
-- coverage on
end if;
else
updt_ns <= UPDATE_STATUS;
end if;
-------------------------------------------------------------------
when UPDATE_ERROR =>
ch1_updt_sm_idle <= '1';
ch2_updt_sm_idle <= '1';
updt_ns <= UPDATE_ERROR;
-------------------------------------------------------------------
-- coverage off
when others =>
updt_ns <= IDLE;
-- coverage on
end case;
end process SG_UPDT_MACHINE;
-------------------------------------------------------------------------------
-- Register states of state machine
-------------------------------------------------------------------------------
REGISTER_STATE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_cs <= IDLE;
else
updt_cs <= updt_ns;
end if;
end if;
end process REGISTER_STATE;
-------------------------------------------------------------------------------
-- Channel included therefore generate fetch logic
-------------------------------------------------------------------------------
GEN_CH1_UPDATE : if C_INCLUDE_CH1 = 1 generate
begin
-------------------------------------------------------------------------------
-- Active channel flag. Indicates which channel is active.
-- 0 = channel active
-- 1 = channel active
-------------------------------------------------------------------------------
CH1_ACTIVE_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_active_i <= '0';
elsif(ch1_active_i = '1' and updt_done = '1')then
ch1_active_i <= '0';
elsif(ch1_active_set = '1')then
ch1_active_i <= '1';
end if;
end if;
end process CH1_ACTIVE_PROCESS;
-------------------------------------------------------------------------------
-- Channel 1 ready to be serviced?
-------------------------------------------------------------------------------
service_ch1 <= '1' when ch1_updt_queue_empty = '0' -- Queue not empty
and ftch_error = '0' -- No SG Fetch Error
else '0';
-------------------------------------------------------------------------------
-- Channel 1 Interrupt On Complete
-------------------------------------------------------------------------------
CH1_INTR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_updt_ioc_irq_set <= '0';
-- Set interrupt on Done and Descriptor IOC set
elsif(updt_done = '1' and ch1_updt_ioc = '1')then
ch1_updt_ioc_irq_set <= '1';
else
ch1_updt_ioc_irq_set <= '0';
end if;
end if;
end process CH1_INTR_PROCESS;
-------------------------------------------------------------------------------
-- Channel 1 DMA Internal Error
-------------------------------------------------------------------------------
CH1_INTERR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_dma_interr_set <= '0';
-- Set internal error on desc updt Done and Internal Error
elsif(updt_done = '1' and ch1_dma_interr = '1')then
ch1_dma_interr_set <= '1';
end if;
end if;
end process CH1_INTERR_PROCESS;
-------------------------------------------------------------------------------
-- Channel 1 DMA Slave Error
-------------------------------------------------------------------------------
CH1_SLVERR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_dma_slverr_set <= '0';
-- Set slave error on desc updt Done and Slave Error
elsif(updt_done = '1' and ch1_dma_slverr = '1')then
ch1_dma_slverr_set <= '1';
end if;
end if;
end process CH1_SLVERR_PROCESS;
-------------------------------------------------------------------------------
-- Channel 1 DMA Decode Error
-------------------------------------------------------------------------------
CH1_DECERR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_dma_decerr_set <= '0';
-- Set decode error on desc updt Done and Decode Error
elsif(updt_done = '1' and ch1_dma_decerr = '1')then
ch1_dma_decerr_set <= '1';
end if;
end if;
end process CH1_DECERR_PROCESS;
-------------------------------------------------------------------------------
-- Log Fetch Errors
-------------------------------------------------------------------------------
-- Log Slave Errors reported during descriptor update
SLV_SET_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_updt_slverr_set <= '0';
elsif(ch1_active_i = '1' and updt_slverr = '1')then
ch1_updt_slverr_set <= '1';
end if;
end if;
end process SLV_SET_PROCESS;
-- Log Internal Errors reported during descriptor update
INT_SET_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_updt_interr_set <= '0';
elsif(ch1_active_i = '1' and updt_interr = '1')then
-- coverage off
ch1_updt_interr_set <= '1';
-- coverage on
end if;
end if;
end process INT_SET_PROCESS;
-- Log Decode Errors reported during descriptor update
DEC_SET_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_updt_decerr_set <= '0';
elsif(ch1_active_i = '1' and updt_decerr = '1')then
ch1_updt_decerr_set <= '1';
end if;
end if;
end process DEC_SET_PROCESS;
-- Indicate update is idle if state machine is idle and update queue is empty
IDLE_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt_error = '1' or ftch_error = '1')then
ch1_updt_idle <= '1';
elsif(service_ch1 = '1')then
ch1_updt_idle <= '0';
elsif(service_ch1 = '0' and ch1_updt_sm_idle = '1')then
ch1_updt_idle <= '1';
end if;
end if;
end process IDLE_PROCESS;
---------------------------------------------------------------------------
-- Indicate update is done to allow fetch of next descriptor
-- This is needed to prevent a partial descriptor being fetched
-- and then axi read is throttled for extended periods until the
-- remainder of the descriptor is fetched.
--
-- Note: Only used when fetch queue not inluded otherwise
-- tools optimize out this process
---------------------------------------------------------------------------
REG_CH1_DONE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_updt_done <= '0';
elsif(updt_done = '1' and ch1_active_i = '1')then
ch1_updt_done <= '1';
else
ch1_updt_done <= '0';
end if;
end if;
end process REG_CH1_DONE;
end generate GEN_CH1_UPDATE;
-------------------------------------------------------------------------------
-- Channel excluded therefore do not generate fetch logic
-------------------------------------------------------------------------------
GEN_NO_CH1_UPDATE : if C_INCLUDE_CH1 = 0 generate
begin
service_ch1 <= '0';
ch1_active_i <= '0';
ch1_updt_idle <= '0';
ch1_updt_interr_set <= '0';
ch1_updt_slverr_set <= '0';
ch1_updt_decerr_set <= '0';
ch1_dma_interr_set <= '0';
ch1_dma_slverr_set <= '0';
ch1_dma_decerr_set <= '0';
ch1_updt_ioc_irq_set <= '0';
ch1_updt_done <= '0';
end generate GEN_NO_CH1_UPDATE;
-------------------------------------------------------------------------------
-- Channel included therefore generate fetch logic
-------------------------------------------------------------------------------
GEN_CH2_UPDATE : if C_INCLUDE_CH2 = 1 generate
begin
-------------------------------------------------------------------------------
-- Active channel flag. Indicates which channel is active.
-- 0 = channel active
-- 1 = channel active
-------------------------------------------------------------------------------
CH2_ACTIVE_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_active_i <= '0';
elsif(ch2_active_i = '1' and updt_done = '1')then
ch2_active_i <= '0';
elsif(ch2_active_set = '1')then
ch2_active_i <= '1';
end if;
end if;
end process CH2_ACTIVE_PROCESS;
-------------------------------------------------------------------------------
-- Channel 2 ready to be serviced?
-------------------------------------------------------------------------------
service_ch2 <= '1' when ch2_updt_queue_empty = '0' -- Queue not empty
and ftch_error = '0' -- No SG Fetch Error
else '0';
-------------------------------------------------------------------------------
-- Channel 2 Interrupt On Complete
-------------------------------------------------------------------------------
CH2_INTR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_updt_ioc_irq_set <= '0';
-- Set interrupt on Done and Descriptor IOC set
elsif(updt_done = '1' and ch2_updt_ioc = '1')then
ch2_updt_ioc_irq_set <= '1';
else
ch2_updt_ioc_irq_set <= '0';
end if;
end if;
end process CH2_INTR_PROCESS;
-------------------------------------------------------------------------------
-- Channel 1 DMA Internal Error
-------------------------------------------------------------------------------
CH2_INTERR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_dma_interr_set <= '0';
-- Set internal error on desc updt Done and Internal Error
elsif(updt_done = '1' and ch2_dma_interr = '1')then
ch2_dma_interr_set <= '1';
end if;
end if;
end process CH2_INTERR_PROCESS;
-------------------------------------------------------------------------------
-- Channel 1 DMA Slave Error
-------------------------------------------------------------------------------
CH2_SLVERR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_dma_slverr_set <= '0';
-- Set slave error on desc updt Done and Slave Error
elsif(updt_done = '1' and ch2_dma_slverr = '1')then
ch2_dma_slverr_set <= '1';
end if;
end if;
end process CH2_SLVERR_PROCESS;
-------------------------------------------------------------------------------
-- Channel 1 DMA Decode Error
-------------------------------------------------------------------------------
CH2_DECERR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_dma_decerr_set <= '0';
-- Set decode error on desc updt Done and Decode Error
elsif(updt_done = '1' and ch2_dma_decerr = '1')then
ch2_dma_decerr_set <= '1';
end if;
end if;
end process CH2_DECERR_PROCESS;
-------------------------------------------------------------------------------
-- Log Fetch Errors
-------------------------------------------------------------------------------
-- Log Slave Errors reported during descriptor update
SLV_SET_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_updt_slverr_set <= '0';
elsif(ch2_active_i = '1' and updt_slverr = '1')then
ch2_updt_slverr_set <= '1';
end if;
end if;
end process SLV_SET_PROCESS;
-- Log Internal Errors reported during descriptor update
INT_SET_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_updt_interr_set <= '0';
elsif(ch2_active_i = '1' and updt_interr = '1')then
-- coverage off
ch2_updt_interr_set <= '1';
-- coverage on
end if;
end if;
end process INT_SET_PROCESS;
-- Log Decode Errors reported during descriptor update
DEC_SET_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_updt_decerr_set <= '0';
elsif(ch2_active_i = '1' and updt_decerr = '1')then
ch2_updt_decerr_set <= '1';
end if;
end if;
end process DEC_SET_PROCESS;
-- Indicate update is idle if state machine is idle and update queue is empty
IDLE_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt_error = '1' or ftch_error = '1')then
ch2_updt_idle <= '1';
elsif(service_ch2 = '1')then
ch2_updt_idle <= '0';
elsif(service_ch2 = '0' and ch2_updt_sm_idle = '1')then
ch2_updt_idle <= '1';
end if;
end if;
end process IDLE_PROCESS;
---------------------------------------------------------------------------
-- Indicate update is done to allow fetch of next descriptor
-- This is needed to prevent a partial descriptor being fetched
-- and then axi read is throttled for extended periods until the
-- remainder of the descriptor is fetched.
--
-- Note: Only used when fetch queue not inluded otherwise
-- tools optimize out this process
---------------------------------------------------------------------------
REG_CH2_DONE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_updt_done <= '0';
elsif(updt_done = '1' and ch2_active_i = '1')then
ch2_updt_done <= '1';
else
ch2_updt_done <= '0';
end if;
end if;
end process REG_CH2_DONE;
end generate GEN_CH2_UPDATE;
-------------------------------------------------------------------------------
-- Channel excluded therefore do not generate fetch logic
-------------------------------------------------------------------------------
GEN_NO_CH2_UPDATE : if C_INCLUDE_CH2 = 0 generate
begin
service_ch2 <= '0';
ch2_active_i <= '0';
ch2_updt_idle <= '0';
ch2_updt_interr_set <= '0';
ch2_updt_slverr_set <= '0';
ch2_updt_decerr_set <= '0';
ch2_dma_interr_set <= '0';
ch2_dma_slverr_set <= '0';
ch2_dma_decerr_set <= '0';
ch2_updt_ioc_irq_set <= '0';
ch2_updt_done <= '0';
end generate GEN_NO_CH2_UPDATE;
---------------------------------------------------------------------------
-- Register Current Update Address. Address captured from channel port
-- or queue by axi_sg_updt_queue
---------------------------------------------------------------------------
REG_UPDATE_ADDRESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
update_address (C_M_AXI_SG_ADDR_WIDTH-1 downto 4) <= (others => '0');
-- update_tag <= "0000";
-- Channel 1 descriptor update pointer
elsif(ch1_updt_curdesc_wren = '1')then
update_address (C_M_AXI_SG_ADDR_WIDTH-1 downto 4) <= std_logic_vector(unsigned(ch1_updt_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto 4))
+ 1);
-- update_tag <= "0001";
-- -- Channel 2 descriptor update pointer
-- elsif(ch2_updt_curdesc_wren = '1')then
-- update_address (C_M_AXI_SG_ADDR_WIDTH-1 downto 4) <= std_logic_vector(unsigned(ch2_updt_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto 4))
-- + 1);
-- update_tag <= "0000";
end if;
end if;
end process REG_UPDATE_ADDRESS;
update_tag <= "0000" when ch2_active_i = '1' else
"0001";
--REG_UPDATE_ADDRESS : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- if(m_axi_sg_aresetn = '0')then
-- update_address (C_M_AXI_SG_ADDR_WIDTH-1 downto 4) <= (others => '0');
-- update_tag <= "0000";
-- -- Channel 1 descriptor update pointer
-- elsif(ch1_updt_curdesc_wren = '1')then
-- update_address (C_M_AXI_SG_ADDR_WIDTH-1 downto 4) <= std_logic_vector(unsigned(ch1_updt_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto 4))
-- + 1);
-- update_tag <= "0001";
-- -- Channel 2 descriptor update pointer
-- elsif(ch2_updt_curdesc_wren = '1')then
-- update_address (C_M_AXI_SG_ADDR_WIDTH-1 downto 4) <= std_logic_vector(unsigned(ch2_updt_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto 4))
-- + 1);
-- update_tag <= "0000";
-- end if;
-- end if;
-- end process REG_UPDATE_ADDRESS;
update_address (3 downto 0) <= "1100";
-- Assigne Bytes to Transfer (BTT)
update_cmd_btt <= UPDATE_CH1_CMD_BTT when ch1_active_i = '1'
else UPDATE_CH2_CMD_BTT;
updt_cmnd_data <= updt_cmnd_data_int;
-------------------------------------------------------------------------------
-- Build DataMover command
-------------------------------------------------------------------------------
-- When command by sm, drive command to updt_cmdsts_if
--GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- if(m_axi_sg_aresetn = '0')then
-- updt_cmnd_wr <= '0';
-- updt_cmnd_data_int <= (others => '0');
-- -- Fetch SM issued a command write
-- elsif(write_cmnd_cmb = '1')then
updt_cmnd_wr <= write_cmnd_cmb; --'1';
updt_cmnd_data_int <= UPDATE_CMD_RSVD
& update_tag --UPDATE_CMD_TAG
& update_address
& UPDATE_MSB_IGNORED
& UPDATE_CMD_TYPE
& UPDATE_LSB_IGNORED
& update_cmd_btt;
-- else
-- updt_cmnd_wr <= '0';
-- end if;
-- end if;
-- end process GEN_DATAMOVER_CMND;
-------------------------------------------------------------------------------
-- Capture and hold fetch address in case an error occurs
-------------------------------------------------------------------------------
LOG_ERROR_ADDR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_error_addr (C_M_AXI_SG_ADDR_WIDTH-1 downto SG_ADDR_LSB) <= (others => '0');
elsif(write_cmnd_cmb = '1')then
updt_error_addr (C_M_AXI_SG_ADDR_WIDTH-1 downto SG_ADDR_LSB) <= update_address(C_M_AXI_SG_ADDR_WIDTH-1 downto SG_ADDR_LSB);
end if;
end if;
end process LOG_ERROR_ADDR;
updt_error_addr (5 downto 0) <= "000000";
end implementation;
|
mit
|
AlessandroSpallina/CalcolatoriElettronici
|
VHDL/28-01-16/28-01-16_compito_last.vhd
|
2
|
4112
|
-- Copyright (C) 2016 by Spallina Ind.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity mariangela is
port (
din : in std_logic_vector(15 downto 0);
start, clk : in std_logic;
dout : out std_logic_vector(15 downto 0);
fine : out std_logic
);
end mariangela;
architecture beh of mariangela is
type stati is (idle, getOP, getA, getB, exe1, exe2, exe3);
signal st : stati;
signal REG, A, B : std_logic_vector(15 downto 0);
signal OP : std_logic_vector(2 downto 0);
signal counter : integer range 2 downto 0;
function next_state (st : stati; start : std_logic; op : std_logic_vector(2 downto 0); counter : integer range 2 downto 0; reg : std_logic_vector(15 downto 0))
return stati is
variable nxt : stati;
begin
case st is
when idle =>
if start = '1' then nxt := getOP;
else nxt := idle;
end if;
when getOP =>
nxt := getA;
when getA =>
case op is
when "101" | "000" | "100" =>
nxt := exe1;
when "110" =>
if conv_integer(REG) = 0 then nxt := exe1;
else nxt := exe3;
end if;
when others =>
nxt := getB;
end case;
when getB =>
case op is
when "001" =>
nxt := exe1;
when "010" =>
nxt := exe3;
when others =>
nxt := exe2;
end case;
when exe1 =>
nxt := idle;
when exe2 =>
if counter < 1 then nxt := exe2;
else nxt := idle;
end if;
when exe3 =>
if counter < 2 then nxt := exe3;
else nxt := idle;
end if;
end case;
return nxt;
end next_state;
-- siccome non ho niente da fare nella vita, mi scrivo sta procedura tanto per D:
procedure return_result (signal REG : inout std_logic_vector(15 downto 0); value_to_return : in std_logic_vector(15 downto 0); signal dout : out std_logic_vector(15 downto 0)) is
begin
REG <= value_to_return;
dout <= REG;
end return_result;
-- anche questa funzione è fatta perchè non ho che fare :D
function min (A : std_logic_vector(15 downto 0); B : std_logic_vector(15 downto 0); REG : std_logic_vector(15 downto 0))
return std_logic_vector is
variable tmp : std_logic_vector(15 downto 0);
begin
if (A < B) then
tmp := A;
else
tmp := B;
end if;
if(tmp > REG) then
tmp := REG;
end if;
return tmp;
end min;
signal enOP, enA, enB, enEXE1, enEXE2, enEXE3 : std_logic;
begin
-- CU
process (clk)
begin
if clk'event and clk = '0' then
st <= next_state (st, start, op, counter, reg);
end if;
end process;
enOP <= '1' when st = getOP else '0';
enA <= '1' when st = getA else '0';
enB <= '1' when st = getB else '0';
enEXE1 <= '1' when st = exe1 else '0';
enEXE2 <= '1' when st = exe2 else '0';
enEXE3 <= '1' when st = exe3 else '0';
-- DATAPATH
process (clk)
begin
if enOP = '1' then
op <= din(2 downto 0);
counter <= 0;
end if;
if enA = '1' then
A <= din;
end if;
if enB = '1' then
B <= din;
end if;
if enEXE1 = '1' then
case op is
when "100" | "000" => -- SET
REG <= A;
when "001" => -- AND (A,B)
return_result(REG, (A and B), dout);
when "101" => -- AND (A,REG)
return_result(REG, (A and REG), dout);
when others => -- "110" ADD => SET
REG <= A;
end case;
end if;
if enEXE2 = '1' then -- MIN
if counter = 1 then
return_result(REG, min(A,B,REG), dout);
else
counter <= counter + 1;
end if;
end if;
if enEXE3 = '1' then
if counter = 2 then
case op is
when "010" => -- ADD (A,B)
return_result(REG, A+B, dout);
when others => -- "110" ADD (A,REG)
return_result(REG, A+REG, dout);
end case;
else
counter <= counter + 1;
end if;
end if;
if enEXE1 = '1' or (enEXE2 = '1' and counter = 1) or (enEXE3 = '1' and counter = 2) then
fine <= '1';
else
fine <= '0';
end if;
end process;
end beh;
|
mit
|
Bjay1435/capstone
|
Geoff/Geoff.srcs/sources_1/bd/dma_loopback/ipshared/xilinx.com/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_wr_sf.vhd
|
5
|
50564
|
-------------------------------------------------------------------------------
-- axi_datamover_wr_sf.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_wr_sf.vhd
--
-- Description:
-- This file implements the AXI DataMover Write (S2MM) Store and Forward module.
-- The design utilizes the AXI DataMover's new address pipelining
-- control function. This module buffers write data and provides status and
-- control features such that the DataMover Write Master is only allowed
-- to post AXI WRite Requests if the associated write data needed to complete
-- the Write Data transfer is present in the Data FIFO. In addition, the Write
-- side logic is such that Write transfer requests can be pipelined to the
-- AXI4 bus based on the Data FIFO contents but ahead of the actual Write Data
-- transfers.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library lib_pkg_v1_0_2;
library lib_srl_fifo_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.all;
use lib_pkg_v1_0_2.lib_pkg.clog2;
use lib_srl_fifo_v1_0_2.srl_fifo_f;
library axi_datamover_v5_1_11;
use axi_datamover_v5_1_11.axi_datamover_sfifo_autord;
-------------------------------------------------------------------------------
entity axi_datamover_wr_sf is
generic (
C_WR_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 4;
-- This parameter indicates the depth of the DataMover
-- write address pipelining queues for the Main data transport
-- channels. The effective address pipelining on the AXI4
-- Write Address Channel will be the value assigned plus 2.
C_SF_FIFO_DEPTH : Integer range 128 to 8192 := 512;
-- Sets the desired depth of the internal Data FIFO.
-- C_MAX_BURST_LEN : Integer range 16 to 256 := 16;
-- -- Indicates the max burst length being used by the external
-- -- AXI4 Master for each AXI4 transfer request.
-- C_DRE_IS_USED : Integer range 0 to 1 := 0;
-- -- Indicates if the external Master is utilizing a DRE on
-- -- the stream input to this module.
C_MMAP_DWIDTH : Integer range 32 to 1024 := 64;
-- Sets the AXI4 Memory Mapped Bus Data Width
C_STREAM_DWIDTH : Integer range 8 to 1024 := 16;
-- Sets the Stream Data Width for the Input and Output
-- Data streams.
C_STRT_OFFSET_WIDTH : Integer range 1 to 7 := 2;
-- Sets the bit width of the starting address offset port
-- This should be set to log2(C_MMAP_DWIDTH/C_STREAM_DWIDTH)
C_FAMILY : String := "virtex7"
-- Indicates the target FPGA Family.
);
port (
-- Clock and Reset inputs -----------------------------------------------
--
aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
reset : in std_logic; --
-- Reset used for the internal syncronization logic --
-------------------------------------------------------------------------
-- Slave Stream Input ------------------------------------------------------------
--
sf2sin_tready : Out Std_logic; --
-- DRE Stream READY input --
--
sin2sf_tvalid : In std_logic; --
-- DRE Stream VALID Output --
--
sin2sf_tdata : In std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- DRE Stream DATA input --
--
sin2sf_tkeep : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- DRE Stream STRB input --
--
sin2sf_tlast : In std_logic; --
-- DRE Xfer LAST input --
--
sin2sf_error : In std_logic; --
-- Stream Underrun/Overrun error input --
-----------------------------------------------------------------------------------
-- Starting Address Offset Input -------------------------------------------------
--
sin2sf_strt_addr_offset : In std_logic_vector(C_STRT_OFFSET_WIDTH-1 downto 0); --
-- Used by Packing logic to set the initial data slice position for the --
-- packing operation. Packing is only needed if the MMap and Stream Data --
-- widths do not match. --
-----------------------------------------------------------------------------------
-- DataMover Write Side Address Pipelining Control Interface ----------------------
--
ok_to_post_wr_addr : Out Std_logic; --
-- Indicates that the internal FIFO has enough data --
-- physically present to supply one more max length --
-- burst transfer or a completion burst --
-- (tlast asserted) --
--
wr_addr_posted : In std_logic; --
-- Indication that a write address has been posted to AXI4 --
--
--
wr_xfer_cmplt : In Std_logic; --
-- Indicates that the Datamover has completed a Write Data --
-- transfer on the AXI4 --
--
--
wr_ld_nxt_len : in std_logic; --
-- Active high pulse indicating a new transfer LEN qualifier --
-- has been queued to the DataMover Write Data Controller --
--
wr_len : in std_logic_vector(7 downto 0); --
-- The actual LEN qualifier value that has been queued to the --
-- DataMover Write Data Controller --
-----------------------------------------------------------------------------------
-- Write Side Stream Out to DataMover S2MM ----------------------------------------
--
sout2sf_tready : In std_logic; --
-- Write READY input from the Stream Master --
--
sf2sout_tvalid : Out std_logic; --
-- Write VALID output to the Stream Master --
--
sf2sout_tdata : Out std_logic_vector(C_MMAP_DWIDTH-1 downto 0); --
-- Write DATA output to the Stream Master --
--
sf2sout_tkeep : Out std_logic_vector((C_MMAP_DWIDTH/8)-1 downto 0); --
-- Write DATA output to the Stream Master --
--
sf2sout_tlast : Out std_logic; --
-- Write LAST output to the Stream Master --
--
sf2sout_error : Out std_logic --
-- Stream Underrun/Overrun error input --
-----------------------------------------------------------------------------------
);
end entity axi_datamover_wr_sf;
architecture implementation of axi_datamover_wr_sf is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Functions ---------------------------------------------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_pwr2_depth
--
-- Function Description:
-- Rounds up to the next power of 2 depth value in an input
-- range of 1 to 8192
--
-------------------------------------------------------------------
function funct_get_pwr2_depth (min_depth : integer) return integer is
Variable var_temp_depth : Integer := 16;
begin
if (min_depth = 1) then
var_temp_depth := 1;
elsif (min_depth = 2) then
var_temp_depth := 2;
elsif (min_depth <= 4) then
var_temp_depth := 4;
elsif (min_depth <= 8) then
var_temp_depth := 8;
elsif (min_depth <= 16) then
var_temp_depth := 16;
elsif (min_depth <= 32) then
var_temp_depth := 32;
elsif (min_depth <= 64) then
var_temp_depth := 64;
elsif (min_depth <= 128) then
var_temp_depth := 128;
elsif (min_depth <= 256) then
var_temp_depth := 256;
elsif (min_depth <= 512) then
var_temp_depth := 512;
elsif (min_depth <= 1024) then
var_temp_depth := 1024;
elsif (min_depth <= 2048) then
var_temp_depth := 2048;
elsif (min_depth <= 4096) then
var_temp_depth := 4096;
else -- assume 8192 depth
var_temp_depth := 8192;
end if;
Return (var_temp_depth);
end function funct_get_pwr2_depth;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_fifo_cnt_width
--
-- Function Description:
-- simple function to set the width of the data fifo read
-- and write count outputs.
-------------------------------------------------------------------
function funct_get_fifo_cnt_width (fifo_depth : integer)
return integer is
Variable temp_width : integer := 8;
begin
if (fifo_depth = 1) then
temp_width := 1;
elsif (fifo_depth = 2) then
temp_width := 2;
elsif (fifo_depth <= 4) then
temp_width := 3;
elsif (fifo_depth <= 8) then
temp_width := 4;
elsif (fifo_depth <= 16) then
temp_width := 5;
elsif (fifo_depth <= 32) then
temp_width := 6;
elsif (fifo_depth <= 64) then
temp_width := 7;
elsif (fifo_depth <= 128) then
temp_width := 8;
elsif (fifo_depth <= 256) then
temp_width := 9;
elsif (fifo_depth <= 512) then
temp_width := 10;
elsif (fifo_depth <= 1024) then
temp_width := 11;
elsif (fifo_depth <= 2048) then
temp_width := 12;
elsif (fifo_depth <= 4096) then
temp_width := 13;
else -- assume 8192 depth
temp_width := 14;
end if;
Return (temp_width);
end function funct_get_fifo_cnt_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_cntr_width
--
-- Function Description:
-- This function calculates the needed counter bit width from the
-- number of count sates needed (input).
--
-------------------------------------------------------------------
function funct_get_cntr_width (num_cnt_values : integer) return integer is
Variable temp_cnt_width : Integer := 0;
begin
if (num_cnt_values <= 2) then
temp_cnt_width := 1;
elsif (num_cnt_values <= 4) then
temp_cnt_width := 2;
elsif (num_cnt_values <= 8) then
temp_cnt_width := 3;
elsif (num_cnt_values <= 16) then
temp_cnt_width := 4;
elsif (num_cnt_values <= 32) then
temp_cnt_width := 5;
elsif (num_cnt_values <= 64) then
temp_cnt_width := 6;
elsif (num_cnt_values <= 128) then
temp_cnt_width := 7;
else
temp_cnt_width := 8;
end if;
Return (temp_cnt_width);
end function funct_get_cntr_width;
-- Constants ---------------------------------------------------------------------------
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant BLK_MEM_FIFO : integer := 1;
Constant SRL_FIFO : integer := 0;
Constant NOT_NEEDED : integer := 0;
Constant WSTB_WIDTH : integer := C_MMAP_DWIDTH/8; -- bits
Constant TLAST_WIDTH : integer := 1; -- bits
Constant EOP_ERR_WIDTH : integer := 1; -- bits
Constant DATA_FIFO_DEPTH : integer := C_SF_FIFO_DEPTH;
Constant DATA_FIFO_CNT_WIDTH : integer := funct_get_fifo_cnt_width(DATA_FIFO_DEPTH);
-- Constant DF_WRCNT_RIP_LS_INDEX : integer := funct_get_wrcnt_lsrip(C_MAX_BURST_LEN);
Constant DATA_FIFO_WIDTH : integer := C_MMAP_DWIDTH +
--WSTB_WIDTH +
TLAST_WIDTH +
EOP_ERR_WIDTH;
Constant DATA_OUT_MSB_INDEX : integer := C_MMAP_DWIDTH-1;
Constant DATA_OUT_LSB_INDEX : integer := 0;
-- Constant TSTRB_OUT_LSB_INDEX : integer := DATA_OUT_MSB_INDEX+1;
-- Constant TSTRB_OUT_MSB_INDEX : integer := (TSTRB_OUT_LSB_INDEX+WSTB_WIDTH)-1;
-- Constant TLAST_OUT_INDEX : integer := TSTRB_OUT_MSB_INDEX+1;
Constant TLAST_OUT_INDEX : integer := DATA_OUT_MSB_INDEX+1;
Constant EOP_ERR_OUT_INDEX : integer := TLAST_OUT_INDEX+1;
Constant WR_LEN_FIFO_DWIDTH : integer := 8;
Constant WR_LEN_FIFO_DEPTH : integer := funct_get_pwr2_depth(C_WR_ADDR_PIPE_DEPTH + 2);
Constant LEN_CNTR_WIDTH : integer := 8;
Constant LEN_CNT_ZERO : Unsigned(LEN_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(0, LEN_CNTR_WIDTH);
Constant LEN_CNT_ONE : Unsigned(LEN_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, LEN_CNTR_WIDTH);
Constant WR_XFER_CNTR_WIDTH : integer := 8;
Constant WR_XFER_CNT_ZERO : Unsigned(WR_XFER_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(0, WR_XFER_CNTR_WIDTH);
Constant WR_XFER_CNT_ONE : Unsigned(WR_XFER_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, WR_XFER_CNTR_WIDTH);
Constant UNCOM_WRCNT_1 : Unsigned(DATA_FIFO_CNT_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, DATA_FIFO_CNT_WIDTH);
Constant UNCOM_WRCNT_0 : Unsigned(DATA_FIFO_CNT_WIDTH-1 downto 0) :=
TO_UNSIGNED(0, DATA_FIFO_CNT_WIDTH);
-- Signals ---------------------------------------------------------------------------
signal sig_good_sin_strm_dbeat : std_logic := '0';
signal sig_strm_sin_ready : std_logic := '0';
signal sig_sout2sf_tready : std_logic := '0';
signal sig_sf2sout_tvalid : std_logic := '0';
signal sig_sf2sout_tdata : std_logic_vector(C_MMAP_DWIDTH-1 downto 0) := (others => '0');
signal sig_sf2sout_tkeep : std_logic_vector(WSTB_WIDTH-1 downto 0) := (others => '0');
signal sig_sf2sout_tlast : std_logic := '0';
signal sig_push_data_fifo : std_logic := '0';
signal sig_pop_data_fifo : std_logic := '0';
signal sig_data_fifo_full : std_logic := '0';
signal sig_data_fifo_data_in : std_logic_vector(DATA_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_data_fifo_dvalid : std_logic := '0';
signal sig_data_fifo_data_out : std_logic_vector(DATA_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_ok_to_post_wr_addr : std_logic := '0';
signal sig_wr_addr_posted : std_logic := '0';
signal sig_wr_xfer_cmplt : std_logic := '0';
signal sig_wr_ld_nxt_len : std_logic := '0';
signal sig_push_len_fifo : std_logic := '0';
signal sig_pop_len_fifo : std_logic := '0';
signal sig_len_fifo_full : std_logic := '0';
signal sig_len_fifo_empty : std_logic := '0';
signal sig_len_fifo_data_in : std_logic_vector(WR_LEN_FIFO_DWIDTH-1 downto 0) := (others => '0');
signal sig_len_fifo_data_out : std_logic_vector(WR_LEN_FIFO_DWIDTH-1 downto 0) := (others => '0');
signal sig_len_fifo_len_out_un : unsigned(WR_LEN_FIFO_DWIDTH-1 downto 0) := (others => '0');
signal sig_uncom_wrcnt : unsigned(DATA_FIFO_CNT_WIDTH-1 downto 0) := (others => '0');
signal sig_sub_len_uncom_wrcnt : std_logic := '0';
signal sig_incr_uncom_wrcnt : std_logic := '0';
signal sig_resized_fifo_len : unsigned(DATA_FIFO_CNT_WIDTH-1 downto 0) := (others => '0');
signal sig_num_wr_dbeats_needed : unsigned(DATA_FIFO_CNT_WIDTH-1 downto 0) := (others => '0');
signal sig_enough_dbeats_rcvd : std_logic := '0';
signal sig_sf2sout_eop_err_out : std_logic := '0';
signal sig_good_fifo_write : std_logic := '0';
begin --(architecture implementation)
-- Write Side (S2MM) Control Flags port connections
ok_to_post_wr_addr <= sig_ok_to_post_wr_addr ;
sig_wr_addr_posted <= wr_addr_posted ;
sig_wr_xfer_cmplt <= wr_xfer_cmplt ;
sig_wr_ld_nxt_len <= wr_ld_nxt_len ;
sig_len_fifo_data_in <= wr_len ;
-- Output Stream Port connections
sig_sout2sf_tready <= sout2sf_tready ;
sf2sout_tvalid <= sig_sf2sout_tvalid ;
sf2sout_tdata <= sig_sf2sout_tdata ;
sf2sout_tkeep <= sig_sf2sout_tkeep ;
sf2sout_tlast <= sig_sf2sout_tlast and
sig_sf2sout_tvalid ;
sf2sout_error <= sig_sf2sout_eop_err_out ;
-- Input Stream port connections
sf2sin_tready <= sig_strm_sin_ready;
sig_good_sin_strm_dbeat <= sin2sf_tvalid and
sig_strm_sin_ready;
----------------------------------------------------------------
-- Packing Logic ------------------------------------------
----------------------------------------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: OMIT_PACKING
--
-- If Generate Description:
-- Omits any packing logic in the Store and Forward module.
-- The Stream and MMap data widths are the same.
--
------------------------------------------------------------
OMIT_PACKING : if (C_MMAP_DWIDTH = C_STREAM_DWIDTH) generate
begin
sig_good_fifo_write <= sig_good_sin_strm_dbeat;
sig_strm_sin_ready <= not(sig_data_fifo_full);
sig_push_data_fifo <= sig_good_sin_strm_dbeat;
-- Concatonate the Stream inputs into the single FIFO data in value
sig_data_fifo_data_in <= sin2sf_error &
sin2sf_tlast &
-- sin2sf_tkeep &
sin2sf_tdata;
end generate OMIT_PACKING;
------------------------------------------------------------
-- If Generate
--
-- Label: INCLUDE_PACKING
--
-- If Generate Description:
-- Includes packing logic in the Store and Forward module.
-- The MMap Data bus is wider than the Stream width.
--
------------------------------------------------------------
INCLUDE_PACKING : if (C_MMAP_DWIDTH > C_STREAM_DWIDTH) generate
Constant MMAP2STRM_WIDTH_RATO : integer := C_MMAP_DWIDTH/C_STREAM_DWIDTH;
Constant DATA_SLICE_WIDTH : integer := C_STREAM_DWIDTH;
Constant FLAG_SLICE_WIDTH : integer := TLAST_WIDTH +
EOP_ERR_WIDTH;
Constant OFFSET_CNTR_WIDTH : integer := funct_get_cntr_width(MMAP2STRM_WIDTH_RATO);
Constant OFFSET_CNT_ONE : unsigned(OFFSET_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, OFFSET_CNTR_WIDTH);
Constant OFFSET_CNT_MAX : unsigned(OFFSET_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(MMAP2STRM_WIDTH_RATO-1, OFFSET_CNTR_WIDTH);
-- Types -----------------------------------------------------------------------------
type lsig_data_slice_type is array(MMAP2STRM_WIDTH_RATO-1 downto 0) of
std_logic_vector(DATA_SLICE_WIDTH-1 downto 0);
type lsig_flag_slice_type is array(MMAP2STRM_WIDTH_RATO-1 downto 0) of
std_logic_vector(FLAG_SLICE_WIDTH-1 downto 0);
-- local signals
signal lsig_data_slice_reg : lsig_data_slice_type;
signal lsig_flag_slice_reg : lsig_flag_slice_type;
signal lsig_reg_segment : std_logic_vector(DATA_SLICE_WIDTH-1 downto 0) := (others => '0');
signal lsig_segment_ld : std_logic_vector(MMAP2STRM_WIDTH_RATO-1 downto 0) := (others => '0');
signal lsig_segment_clr : std_logic_vector(MMAP2STRM_WIDTH_RATO-1 downto 0) := (others => '0');
signal lsig_0ffset_to_to_use : unsigned(OFFSET_CNTR_WIDTH-1 downto 0) := (others => '0');
signal lsig_0ffset_cntr : unsigned(OFFSET_CNTR_WIDTH-1 downto 0) := (others => '0');
signal lsig_ld_offset : std_logic := '0';
signal lsig_incr_offset : std_logic := '0';
signal lsig_offset_cntr_eq_max : std_logic := '0';
signal lsig_combined_data : std_logic_vector(C_MMAP_DWIDTH-1 downto 0) := (others => '0');
signal lsig_tlast_or : std_logic := '0';
signal lsig_eop_err_or : std_logic := '0';
signal lsig_partial_tlast_or : std_logic_vector(MMAP2STRM_WIDTH_RATO downto 0) := (others => '0');
signal lsig_partial_eop_err_or : std_logic_vector(MMAP2STRM_WIDTH_RATO downto 0) := (others => '0');
signal lsig_packer_full : std_logic := '0';
signal lsig_packer_empty : std_logic := '0';
signal lsig_set_packer_full : std_logic := '0';
signal lsig_good_push2fifo : std_logic := '0';
signal lsig_first_dbeat : std_logic := '0';
begin
-- Assign the flag indicating that a fifo write is going
-- to occur at the next rising clock edge.
sig_good_fifo_write <= lsig_good_push2fifo;
-- Generate the stream ready
sig_strm_sin_ready <= not(lsig_packer_full) or
lsig_good_push2fifo ;
-- Format the FIFO input data
sig_data_fifo_data_in <= lsig_eop_err_or & -- MS Bit
lsig_tlast_or &
lsig_combined_data ; -- LS Bits
-- Generate a write to the Data FIFO input
sig_push_data_fifo <= lsig_packer_full;
-- Generate a flag indicating a write to the DataFIFO
-- is going to complete
lsig_good_push2fifo <= lsig_packer_full and
not(sig_data_fifo_full);
-- Generate the control that loads the starting address
-- offset for the next input packet
lsig_ld_offset <= lsig_first_dbeat and
sig_good_sin_strm_dbeat;
-- Generate the control for incrementing the offset counter
lsig_incr_offset <= sig_good_sin_strm_dbeat;
-- Generate a flag indicating the packer input register
-- array is full or has loaded the last data beat of
-- the input paket
lsig_set_packer_full <= sig_good_sin_strm_dbeat and
(sin2sf_tlast or
lsig_offset_cntr_eq_max);
-- Check to see if the offset counter has reached its max
-- value
lsig_offset_cntr_eq_max <= '1'
--when (lsig_0ffset_cntr = OFFSET_CNT_MAX)
when (lsig_0ffset_to_to_use = OFFSET_CNT_MAX)
Else '0';
-- Mux between the input start offset and the offset counter
-- output to use for the packer slice load control.
lsig_0ffset_to_to_use <= UNSIGNED(sin2sf_strt_addr_offset)
when (lsig_first_dbeat = '1')
Else lsig_0ffset_cntr;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_OFFSET_LD_MARKER
--
-- Process Description:
-- Implements the flop indicating the first databeat of
-- an input data packet.
--
-------------------------------------------------------------
IMP_OFFSET_LD_MARKER : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1') then
lsig_first_dbeat <= '1';
elsif (sig_good_sin_strm_dbeat = '1' and
sin2sf_tlast = '0') then
lsig_first_dbeat <= '0';
Elsif (sig_good_sin_strm_dbeat = '1' and
sin2sf_tlast = '1') Then
lsig_first_dbeat <= '1';
else
null; -- Hold Current State
end if;
end if;
end process IMP_OFFSET_LD_MARKER;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_OFFSET_CNTR
--
-- Process Description:
-- Implements the address offset counter that is used to
-- steer the data loads into the packer register slices.
-- Note that the counter has to be loaded with the starting
-- offset plus one to sync up with the data input.
-------------------------------------------------------------
IMP_OFFSET_CNTR : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1') then
lsig_0ffset_cntr <= (others => '0');
Elsif (lsig_ld_offset = '1') Then
lsig_0ffset_cntr <= UNSIGNED(sin2sf_strt_addr_offset) + OFFSET_CNT_ONE;
elsif (lsig_incr_offset = '1') then
lsig_0ffset_cntr <= lsig_0ffset_cntr + OFFSET_CNT_ONE;
else
null; -- Hold Current State
end if;
end if;
end process IMP_OFFSET_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_PACK_REG_FULL
--
-- Process Description:
-- Implements the Packer Register full/empty flags
--
-------------------------------------------------------------
IMP_PACK_REG_FULL : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1') then
lsig_packer_full <= '0';
lsig_packer_empty <= '1';
Elsif (lsig_set_packer_full = '1' and
lsig_packer_full = '0') Then
lsig_packer_full <= '1';
lsig_packer_empty <= '0';
elsif (lsig_set_packer_full = '0' and
lsig_good_push2fifo = '1') then
lsig_packer_full <= '0';
lsig_packer_empty <= '1';
else
null; -- Hold Current State
end if;
end if;
end process IMP_PACK_REG_FULL;
------------------------------------------------------------
-- For Generate
--
-- Label: DO_REG_SLICES
--
-- For Generate Description:
--
-- Implements the Packng Register Slices
--
--
------------------------------------------------------------
DO_REG_SLICES : for slice_index in 0 to MMAP2STRM_WIDTH_RATO-1 generate
begin
-- generate the register load enable for each slice segment based
-- on the address offset count value
lsig_segment_ld(slice_index) <= '1'
when (sig_good_sin_strm_dbeat = '1' and
TO_INTEGER(lsig_0ffset_to_to_use) = slice_index)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_DATA_SLICE
--
-- Process Description:
-- Implement a data register slice for the packer.
--
-------------------------------------------------------------
IMP_DATA_SLICE : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1') then
lsig_data_slice_reg(slice_index) <= (others => '0');
elsif (lsig_segment_ld(slice_index) = '1') then
lsig_data_slice_reg(slice_index) <= sin2sf_tdata;
-- optional clear of slice reg
elsif (lsig_segment_ld(slice_index) = '0' and
lsig_good_push2fifo = '1') then
lsig_data_slice_reg(slice_index) <= (others => '0');
else
null; -- Hold Current State
end if;
end if;
end process IMP_DATA_SLICE;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FLAG_SLICE
--
-- Process Description:
-- Implement a flag register slice for the packer.
--
-------------------------------------------------------------
IMP_FLAG_SLICE : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1') then
lsig_flag_slice_reg(slice_index) <= (others => '0');
elsif (lsig_segment_ld(slice_index) = '1') then
lsig_flag_slice_reg(slice_index) <= sin2sf_tlast & -- bit 1
sin2sf_error; -- bit 0
elsif (lsig_segment_ld(slice_index) = '0' and
lsig_good_push2fifo = '1') then
lsig_flag_slice_reg(slice_index) <= (others => '0');
else
null; -- Hold Current State
end if;
end if;
end process IMP_FLAG_SLICE;
end generate DO_REG_SLICES;
-- Do the OR functions of the Flags -------------------------------------
lsig_tlast_or <= lsig_partial_tlast_or(MMAP2STRM_WIDTH_RATO-1) ;
lsig_eop_err_or <= lsig_partial_eop_err_or(MMAP2STRM_WIDTH_RATO-1);
lsig_partial_tlast_or(0) <= lsig_flag_slice_reg(0)(1);
lsig_partial_eop_err_or(0) <= lsig_flag_slice_reg(0)(0);
------------------------------------------------------------
-- For Generate
--
-- Label: DO_FLAG_OR
--
-- For Generate Description:
-- Implement the OR of the TLAST and EOP Error flags.
--
--
--
------------------------------------------------------------
DO_FLAG_OR : for slice_index in 1 to MMAP2STRM_WIDTH_RATO-1 generate
begin
lsig_partial_tlast_or(slice_index) <= lsig_partial_tlast_or(slice_index-1) or
--lsig_partial_tlast_or(slice_index);
lsig_flag_slice_reg(slice_index)(1);
lsig_partial_eop_err_or(slice_index) <= lsig_partial_eop_err_or(slice_index-1) or
--lsig_partial_eop_err_or(slice_index);
lsig_flag_slice_reg(slice_index)(0);
end generate DO_FLAG_OR;
------------------------------------------------------------
-- For Generate
--
-- Label: DO_DATA_COMBINER
--
-- For Generate Description:
-- Combines the Data Slice register outputs into a single
-- vector for input to the Data FIFO.
--
--
------------------------------------------------------------
DO_DATA_COMBINER : for slice_index in 1 to MMAP2STRM_WIDTH_RATO generate
begin
lsig_combined_data((slice_index*DATA_SLICE_WIDTH)-1 downto
(slice_index-1)*DATA_SLICE_WIDTH) <=
lsig_data_slice_reg(slice_index-1);
end generate DO_DATA_COMBINER;
end generate INCLUDE_PACKING;
----------------------------------------------------------------
-- Data FIFO Logic ------------------------------------------
----------------------------------------------------------------
-- FIFO Input attachments
-- sig_push_data_fifo <= sig_good_sin_strm_dbeat;
-- -- Concatonate the Stream inputs into the single FIFO data in value
-- sig_data_fifo_data_in <= sin2sf_error &
-- sin2sf_tlast &
-- sin2sf_tkeep &
-- sin2sf_tdata;
-- FIFO Output to output stream attachments
sig_sf2sout_tvalid <= sig_data_fifo_dvalid ;
sig_sf2sout_tdata <= sig_data_fifo_data_out(DATA_OUT_MSB_INDEX downto
DATA_OUT_LSB_INDEX);
-- sig_sf2sout_tkeep <= sig_data_fifo_data_out(TSTRB_OUT_MSB_INDEX downto
-- TSTRB_OUT_LSB_INDEX);
-- When this Store and Forward is enabled, the Write Data Controller ignores the
-- TKEEP input so this is not sent through the FIFO.
sig_sf2sout_tkeep <= (others => '1');
sig_sf2sout_tlast <= sig_data_fifo_data_out(TLAST_OUT_INDEX) ;
sig_sf2sout_eop_err_out <= sig_data_fifo_data_out(EOP_ERR_OUT_INDEX) ;
-- FIFO Rd/WR Controls
sig_pop_data_fifo <= sig_sout2sf_tready and
sig_data_fifo_dvalid;
------------------------------------------------------------
-- Instance: I_DATA_FIFO
--
-- Description:
-- Implements the Store and Forward data FIFO (synchronous)
--
------------------------------------------------------------
I_DATA_FIFO : entity axi_datamover_v5_1_11.axi_datamover_sfifo_autord
generic map (
C_DWIDTH => DATA_FIFO_WIDTH ,
C_DEPTH => DATA_FIFO_DEPTH ,
C_DATA_CNT_WIDTH => DATA_FIFO_CNT_WIDTH ,
C_NEED_ALMOST_EMPTY => NOT_NEEDED ,
C_NEED_ALMOST_FULL => NOT_NEEDED ,
C_USE_BLKMEM => BLK_MEM_FIFO ,
C_FAMILY => C_FAMILY
)
port map (
-- Inputs
SFIFO_Sinit => reset ,
SFIFO_Clk => aclk ,
SFIFO_Wr_en => sig_push_data_fifo ,
SFIFO_Din => sig_data_fifo_data_in ,
SFIFO_Rd_en => sig_pop_data_fifo ,
SFIFO_Clr_Rd_Data_Valid => LOGIC_LOW ,
-- Outputs
SFIFO_DValid => sig_data_fifo_dvalid ,
SFIFO_Dout => sig_data_fifo_data_out ,
SFIFO_Full => sig_data_fifo_full ,
SFIFO_Empty => open ,
SFIFO_Almost_full => open ,
SFIFO_Almost_empty => open ,
SFIFO_Rd_count => open ,
SFIFO_Rd_count_minus1 => open ,
SFIFO_Wr_count => open ,
SFIFO_Rd_ack => open
);
--------------------------------------------------------------------
-- Write Side Control Logic
--------------------------------------------------------------------
-- Convert the LEN fifo data output to unsigned
sig_len_fifo_len_out_un <= unsigned(sig_len_fifo_data_out);
-- Resize the unsigned LEN output to the Data FIFO writecount width
sig_resized_fifo_len <= RESIZE(sig_len_fifo_len_out_un , DATA_FIFO_CNT_WIDTH);
-- The actual number of databeats needed for the queued write transfer
-- is the current LEN fifo output plus 1.
sig_num_wr_dbeats_needed <= sig_resized_fifo_len + UNCOM_WRCNT_1;
-- Compare the uncommited receved data beat count to that needed
-- for the next queued write request.
sig_enough_dbeats_rcvd <= '1'
When (sig_num_wr_dbeats_needed <= sig_uncom_wrcnt)
else '0';
-- Increment the uncommited databeat counter on a good input
-- stream databeat (Read Side of SF)
-- sig_incr_uncom_wrcnt <= sig_good_sin_strm_dbeat;
sig_incr_uncom_wrcnt <= sig_good_fifo_write;
-- Subtract the current number of databeats needed from the
-- uncommited databeat counter when the associated transfer
-- address/qualifiers have been posted to the AXI Write
-- Address Channel
sig_sub_len_uncom_wrcnt <= sig_wr_addr_posted;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_UNCOM_DBEAT_CNTR
--
-- Process Description:
-- Implements the counter that keeps track of the received read
-- data beat count that has not been commited to a transfer on
-- the write side with a Write Address posting.
--
-------------------------------------------------------------
IMP_UNCOM_DBEAT_CNTR : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1') then
sig_uncom_wrcnt <= UNCOM_WRCNT_0;
elsif (sig_incr_uncom_wrcnt = '1' and
sig_sub_len_uncom_wrcnt = '1') then
sig_uncom_wrcnt <= sig_uncom_wrcnt - sig_resized_fifo_len;
elsif (sig_incr_uncom_wrcnt = '1' and
sig_sub_len_uncom_wrcnt = '0') then
sig_uncom_wrcnt <= sig_uncom_wrcnt + UNCOM_WRCNT_1;
elsif (sig_incr_uncom_wrcnt = '0' and
sig_sub_len_uncom_wrcnt = '1') then
sig_uncom_wrcnt <= sig_uncom_wrcnt - sig_num_wr_dbeats_needed;
else
null; -- hold current value
end if;
end if;
end process IMP_UNCOM_DBEAT_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_WR_ADDR_POST_FLAG
--
-- Process Description:
-- Implements the flag indicating that the pending write
-- transfer's data beat count has been received on the input
-- side of the Data FIFO. This means the Write side can post
-- the associated write address to the AXI4 bus and the
-- associated write data transfer can complete without CDMA
-- throttling the Write Data Channel.
--
-- The flag is cleared immediately after an address is posted
-- to prohibit a second unauthorized posting while the control
-- logic stabilizes to the next LEN FIFO value
--.
-------------------------------------------------------------
IMP_WR_ADDR_POST_FLAG : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1' or
sig_wr_addr_posted = '1') then
sig_ok_to_post_wr_addr <= '0';
else
sig_ok_to_post_wr_addr <= not(sig_len_fifo_empty) and
sig_enough_dbeats_rcvd;
end if;
end if;
end process IMP_WR_ADDR_POST_FLAG;
-------------------------------------------------------------
-- LEN FIFO logic
-- The LEN FIFO stores the xfer lengths needed for each queued
-- write transfer in the DataMover S2MM Write Data Controller.
sig_push_len_fifo <= sig_wr_ld_nxt_len and
not(sig_len_fifo_full);
sig_pop_len_fifo <= wr_addr_posted and
not(sig_len_fifo_empty);
------------------------------------------------------------
-- Instance: I_WR_LEN_FIFO
--
-- Description:
-- Implement the LEN FIFO using SRL FIFO elements
--
------------------------------------------------------------
I_WR_LEN_FIFO : entity lib_srl_fifo_v1_0_2.srl_fifo_f
generic map (
C_DWIDTH => WR_LEN_FIFO_DWIDTH ,
C_DEPTH => WR_LEN_FIFO_DEPTH ,
C_FAMILY => C_FAMILY
)
port map (
Clk => aclk ,
Reset => reset ,
FIFO_Write => sig_push_len_fifo ,
Data_In => sig_len_fifo_data_in ,
FIFO_Read => sig_pop_len_fifo ,
Data_Out => sig_len_fifo_data_out ,
FIFO_Empty => sig_len_fifo_empty ,
FIFO_Full => sig_len_fifo_full ,
Addr => open
);
end implementation;
|
mit
|
Bjay1435/capstone
|
Geoff/Geoff.srcs/sources_1/bd/dma_loopback/ipshared/xilinx.com/fifo_generator_v13_1/hdl/fifo_generator_v13_1.vhd
|
13
|
91192
|
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2016_05", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 65376)
`protect data_block
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`protect end_protected
|
mit
|
mpvanveldhuizen/16-bit-risc
|
vhdl/fts.vhd
|
4
|
1348
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.lib.all;
ENTITY fts IS
PORT( hexin :IN STD_LOGIC_VECTOR(0 TO 3);
dispout :OUT STD_LOGIC_VECTOR(0 TO 6));
END fts;
ARCHITECTURE Structure OF fts IS
BEGIN
PROCESS(hexin)
BEGIN
IF hexin = "0000" THEN --0
dispout <= "0000001";
END IF;
IF hexin = "0001" THEN --1
dispout <= "1001111";
END IF;
IF hexin = "0010" THEN --2
dispout <= "0010010";
END IF;
IF hexin = "0011" THEN --3
dispout <= "0000110";
END IF;
IF hexin = "0100" THEN --4
dispout <= "1001100";
END IF;
IF hexin = "0101" THEN --5
dispout <= "0100100";
END IF;
IF hexin = "0110" THEN --6
dispout <= "0100000";
END IF;
IF hexin = "0111" THEN --7
dispout <= "0001111";
END IF;
IF hexin = "1000" THEN --8
dispout <= "0000000";
END IF;
IF hexin = "1001" THEN --9
dispout <= "0001100";
END IF;
IF hexin = "1010" THEN --A
dispout <= "0001000";
END IF;
IF hexin = "1011" THEN --B
dispout <= "1100000";
END IF;
IF hexin = "1100" THEN --C
dispout <= "0110001";
END IF;
IF hexin = "1101" THEN --D
dispout <= "1000010";
END IF;
IF hexin = "1110" THEN --E
dispout <= "0110000";
END IF;
IF hexin = "1111" THEN --F
dispout <= "0111000";
END IF;
END PROCESS;
END Structure;
|
mit
|
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