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Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC
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bin_Gaussian_Filter/ip/Gaussian_Filter/fp_tan.vhd
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10
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24604
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LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_TAN1.VHD ***
--*** ***
--*** Function: Single Precision Floating Point ***
--*** Tangent ***
--*** ***
--*** 23/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** NOTES ***
--***************************************************
--*** 1. for very top of range (last 256 mantissa lsbs before pi/2), use seperate ROM, not
--*** calculation
--*** 2. if round up starting when X.49999, errors reduce about 25%, need to tweak this, still getting
--*** all -1 errors with bX.111111111. less errors with less tail bits for smaller exponents (like 122)
--*** more for exponent = 126
ENTITY fp_tan IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
signout : OUT STD_LOGIC;
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1)
);
END fp_tan;
ARCHITECTURE rtl of fp_tan IS
-- input section
signal zerovec : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal mantissainff : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal exponentinff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal argumentff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal topargumentff : STD_LOGIC_VECTOR (9 DOWNTO 1);
signal middleargumentff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal tanhighmantissaff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal tanmiddleff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal tanhighexponentff : STD_LOGIC_VECTOR (5 DOWNTO 1);
signal tanlowsumff : STD_LOGIC_VECTOR (37 DOWNTO 1);
signal shiftin : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal shiftinbus : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal argumentbus : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal tanhighmantissa : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal tanhighexponent : STD_LOGIC_VECTOR (5 DOWNTO 1);
signal tanmiddle : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal deltwo_tailnode : STD_LOGIC_VECTOR (19 DOWNTO 1);
signal tantailnode : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal tanlowsumnode : STD_LOGIC_VECTOR (37 DOWNTO 1);
signal tanlowmantissabus : STD_LOGIC_VECTOR (56 DOWNTO 1);
-- numerator section
signal tanlowff : STD_LOGIC_VECTOR (56 DOWNTO 1);
signal numeratorsumff : STD_LOGIC_VECTOR (57 DOWNTO 1);
signal tanlowshift : STD_LOGIC_VECTOR (5 DOWNTO 1);
signal numeratormantissaff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal numeratorexponentff : STD_LOGIC_VECTOR (5 DOWNTO 1);
signal delone_tanhighexponent : STD_LOGIC_VECTOR (5 DOWNTO 1);
signal delthr_tanhighexponent : STD_LOGIC_VECTOR (5 DOWNTO 1);
signal deltwo_tanhighmantissa : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal tanlowbus : STD_LOGIC_VECTOR (56 DOWNTO 1);
signal numeratorsum : STD_LOGIC_VECTOR (57 DOWNTO 1);
signal numeratorlead, numeratorleadnode : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal numeratormantissa : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal numeratorexponent : STD_LOGIC_VECTOR (5 DOWNTO 1);
-- denominator section
signal lowleadff : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal denominatorleadff : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal multshiftff : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal denominatorproductff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal denominatorff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal denominatormantissaff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal inverseexponentff : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal lowleadnode : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal multshiftnode : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal denominatorproductbus : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal denominator : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal delone_denominator : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal denominatorlead : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal denominatormantissa : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal delone_tanlowsum : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal lowmantissabus : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal delthr_tanhighmantissa : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal multipliernode : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal delfor_tanhighexponent : STD_LOGIC_VECTOR (5 DOWNTO 1);
signal deltwo_lowlead : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal multexponent : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal denominatorexponent : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal inverseexponent : STD_LOGIC_VECTOR (6 DOWNTO 1);
-- divider section
signal tanexponentff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal tanexponentnormff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal tanexponentoutff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal tanmantissanormff : STD_LOGIC_VECTOR (24 DOWNTO 1);
signal roundbitff : STD_LOGIC;
signal mantissaoutff : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal exponentoutff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal overff : STD_LOGIC;
signal denominatorinverse : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal del_numeratormantissa : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal multiplier_tan : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal tanmantissa : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal tanmantissanorm : STD_LOGIC_VECTOR (24 DOWNTO 1);
signal tanmantissatail : STD_LOGIC_VECTOR (9 DOWNTO 1);
signal overcheck : STD_LOGIC_VECTOR (24 DOWNTO 1);
signal del_inverseexponent : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal del_numeratorexponent : STD_LOGIC_VECTOR (5 DOWNTO 1);
signal tanexponent, tanexponentnorm : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal exponentoutnode : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal mantissaoutnode : STD_LOGIC_VECTOR (23 DOWNTO 1);
-- small inputs
signal signff : STD_LOGIC_VECTOR (30 DOWNTO 1);
signal small_mantissa : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal small_exponent : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal exponentcheck : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal small_inputff : STD_LOGIC_VECTOR (28 DOWNTO 1);
signal mantissabase : STD_LOGIC_VECTOR (24 DOWNTO 1);
signal exponentbase : STD_LOGIC_VECTOR (8 DOWNTO 1);
component fp_tanlut1
PORT (
add : IN STD_LOGIC_VECTOR (9 DOWNTO 1);
mantissa : OUT STD_LOGIC_VECTOR (36 DOWNTO 1);
exponent : OUT STD_LOGIC_VECTOR (5 DOWNTO 1)
);
end component;
component fp_tanlut2
PORT (
add : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
tanfraction : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component fp_clz36
PORT (
mantissa : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
leading : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component fp_clz36x6
PORT (
mantissa : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
leading : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component fp_lsft36
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component fp_rsft36
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component fp_rsft56x20
PORT (
inbus : IN STD_LOGIC_VECTOR (56 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (56 DOWNTO 1)
);
end component;
component fp_inv_core
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
divisor : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
quotient : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component fp_del
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_fxmul
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36;
pipes : positive := 1;
accuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
BEGIN
gza: FOR k IN 1 TO 36 GENERATE
zerovec(k) <= '0';
END GENERATE;
-- convert to fixed point
pin: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 23 LOOP
mantissainff(k) <= '0';
END LOOP;
FOR k IN 1 TO 8 LOOP
exponentinff(k) <= '0';
END LOOP;
FOR k IN 1 TO 36 LOOP
argumentff(k) <= '0';
END LOOP;
FOR k IN 1 TO 9 LOOP
topargumentff(k) <= '0';
END LOOP;
FOR k IN 1 TO 8 LOOP
middleargumentff(k) <= '0';
END LOOP;
FOR k IN 1 TO 36 LOOP
tanhighmantissaff(k) <= '0';
tanmiddleff(k) <= '0';
END LOOP;
FOR k IN 1 TO 5 LOOP
tanhighexponentff(k) <= '0';
END LOOP;
FOR k IN 1 TO 5 LOOP
tanlowsumff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
mantissainff <= mantissain;
exponentinff <= exponentin;
argumentff <= argumentbus;
topargumentff <= argumentff(36 DOWNTO 28);
middleargumentff <= argumentff(27 DOWNTO 20);
tanhighmantissaff <= tanhighmantissa;
tanhighexponentff <= tanhighexponent;
tanmiddleff <= tanmiddle;
tanlowsumff <= tanlowsumnode;
END IF;
END IF;
END PROCESS;
shiftin <= 127 - exponentinff;
shiftinbus <= '1' & mantissainff & zerovec(12 DOWNTO 1);
csftin: fp_rsft36
PORT MAP (inbus=>shiftinbus,shift=>shiftin(6 DOWNTO 1),
outbus=>argumentbus);
chtt: fp_tanlut1
PORT MAP (add=>topargumentff,
mantissa=>tanhighmantissa,
exponent=>tanhighexponent);
cltt: fp_tanlut2
PORT MAP (add=>middleargumentff,
tanfraction=>tanmiddle);
-- in level 2, out level 4
dtail: fp_del
GENERIC MAP (width=>19,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, -- use reset to force to ffs here
aa=>argumentff(19 DOWNTO 1),
cc=>deltwo_tailnode);
tantailnode <= zerovec(8 DOWNTO 1) & deltwo_tailnode & zerovec(9 DOWNTO 1);
tanlowsumnode <= ('0' & tanmiddleff(36 DOWNTO 1)) + ('0' & tantailnode);
tanlowmantissabus <= tanlowsumff & zerovec(19 DOWNTO 1);
--*********************************************
--*** Align two tangent values for addition ***
--*********************************************
padd: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 56 LOOP
tanlowff(k) <= '0';
END LOOP;
FOR k IN 1 TO 57 LOOP
numeratorsumff(k) <= '0';
END LOOP;
FOR k IN 1 TO 36 LOOP
numeratormantissaff(k) <= '0';
END LOOP;
FOR k IN 1 TO 5 LOOP
numeratorexponentff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
tanlowff <= tanlowbus;
numeratorsumff <= numeratorsum;
numeratormantissaff <= numeratormantissa;
numeratorexponentff <= numeratorexponent;
END IF;
END IF;
END PROCESS;
-- in level 4, out level 5
dhxa: fp_del
GENERIC MAP (width=>5,pipes=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, -- use reset to force to ffs here
aa=>tanhighexponentff,
cc=>delone_tanhighexponent);
-- in level 5, out level 7
dhxb: fp_del
GENERIC MAP (width=>5,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, -- use reset to force to ffs here
aa=>delone_tanhighexponent,
cc=>delthr_tanhighexponent);
-- in level 4, out level 6
dhm: fp_del
GENERIC MAP (width=>36,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, -- use reset to force to ffs here
aa=>tanhighmantissaff,
cc=>deltwo_tanhighmantissa);
-- tan high mantissa format 1.XXX, tan low mantissa format 0.XXXXX
-- tan high exponent base is 119 (top of middle range)
tanlowshift <= delone_tanhighexponent;
crsadd: fp_rsft56x20
PORT MAP (inbus=>tanlowmantissabus,
shift=>tanlowshift,
outbus=>tanlowbus);
numeratorsum <= ('0' & deltwo_tanhighmantissa & zerovec(20 DOWNTO 1)) + ('0' & tanlowff);
-- level 8
-- no pipe between clz and shift as only 6 bit shift
-- middle exponent is 119, and 2 overflow bits in numerator sum, so this will
-- cover downto (119+2-6) = 115 exponent
-- below 115 exponent, output mantissa = input mantissa
clznuma: fp_clz36x6
PORT MAP (mantissa=>numeratorsumff(57 DOWNTO 22),
leading=>numeratorlead);
numeratorleadnode <= "000" & numeratorlead(3 DOWNTO 1); -- force [6:4] to 0 to optimize away logic in LSFT
clsnuma: fp_lsft36
PORT MAP (inbus=>numeratorsumff(57 DOWNTO 22),shift=>numeratorleadnode,
outbus=>numeratormantissa);
numeratorexponent <= delthr_tanhighexponent - numeratorlead(5 DOWNTO 1) + 1;
--gnnadd: FOR k IN 1 TO 36 GENERATE
-- numeratormantissa(k) <= (numeratorsumff(k+20) AND NOT(numeratorsumff(57))) OR
-- (numeratorsumff(k+21) AND numeratorsumff(57));
--END GENERATE;
--numeratorexponent <= delthr_tanhighexponent + ("0000" & numeratorsumff(57));
--***************************************************
--*** Align two tangent values for multiplication ***
--***************************************************
pmul: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 6 LOOP
lowleadff(k) <= '0';
denominatorleadff(k) <= '0';
inverseexponentff(k) <= '0';
END LOOP;
FOR k IN 1 TO 6 LOOP
multshiftff(k) <= '0';
END LOOP;
FOR k IN 1 TO 36 LOOP
denominatorproductff(k) <= '0';
denominatorff(k) <= '0';
denominatormantissaff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
lowleadff <= lowleadnode;
multshiftff <= multshiftnode;
denominatorproductff <= denominatorproductbus;
denominatorff <= denominator;
denominatorleadff <= denominatorlead;
denominatormantissaff <= denominatormantissa;
inverseexponentff <= inverseexponent;
END IF;
END IF;
END PROCESS;
clzmula: fp_clz36
PORT MAP (mantissa=>tanlowsumff(37 DOWNTO 2),
leading=>lowleadnode);
-- in level 5, out level 6
dlm: fp_del
GENERIC MAP (width=>36,pipes=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, -- use reset to force to ffs here
aa=>tanlowsumff(37 DOWNTO 2),
cc=>delone_tanlowsum);
clsmula: fp_lsft36
PORT MAP (inbus=>delone_tanlowsum,shift=>lowleadff,
outbus=>lowmantissabus);
cma: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>72,
pipes=>3,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>deltwo_tanhighmantissa,
databb=>lowmantissabus,
result=>multipliernode);
-- in level 5, out level 8
dhxc: fp_del
GENERIC MAP (width=>5,pipes=>3)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, -- use reset to force to ffs here
aa=>delone_tanhighexponent,
cc=>delfor_tanhighexponent);
-- in level 6, out level 8
dlla: fp_del
GENERIC MAP (width=>6,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, -- use reset to force to ffs here
aa=>lowleadff,
cc=>deltwo_lowlead);
-- msb of lowmantissa(37) is at exponent 0 for highmantissa
multexponent <= ('0' & delfor_tanhighexponent);
--multshiftnode <= "001000" - multexponent + 8 - 1 + lowlead;
multshiftnode <= "001111" - multexponent + deltwo_lowlead;
-- '1.0' is at exponent 8 compared to highmantissa
crsmul: fp_rsft36
PORT MAP (inbus=>multipliernode(72 DOWNTO 37),shift=>multshiftff,
outbus=>denominatorproductbus);
denominator <= ('1' & zerovec(35 DOWNTO 1)) - denominatorproductff;
-- in level 11, out level 12
dda: fp_del
GENERIC MAP (width=>36,pipes=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, -- use reset to force to ffs here
aa=>denominatorff,
cc=>delone_denominator);
clzmulb: fp_clz36
PORT MAP (mantissa=>denominatorff,
leading=>denominatorlead);
-- denominatormantissa level 12, (denominatormantissaff level 13)
clsmulb: fp_lsft36
PORT MAP (inbus=>delone_denominator,shift=>denominatorleadff,
outbus=>denominatormantissa);
denominatorexponent <= denominatorleadff; -- actually inverse of exponent i.e. 4 => -4, so sign does not have to change after inverting
-- inverseexponentff level 13
inverseexponent <= denominatorexponent - 1;
--****************************
--*** main divider section ***
--****************************
pdiv: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 8 LOOP
tanexponentff(k) <= '0';
tanexponentnormff(k) <= '0';
exponentoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 24 LOOP
tanmantissanormff(k) <= '0';
END LOOP;
roundbitff <= '0';
FOR k IN 1 TO 23 LOOP
mantissaoutff(k) <= '0';
END LOOP;
overff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
tanexponentff <= tanexponent;
tanmantissanormff <= tanmantissanorm; -- level 29
tanexponentnormff <= tanexponentnorm; -- level 29
overff <= overcheck(24);
-- round up if 0.4999
roundbitff <= tanmantissanorm(1) OR
(tanmantissatail(9) AND
tanmantissatail(8) AND tanmantissatail(7) AND
tanmantissatail(6) AND tanmantissatail(5) AND
tanmantissatail(4) AND tanmantissatail(3) AND
tanmantissatail(2) AND tanmantissatail(1));
mantissaoutff <= mantissaoutnode; -- level 30
exponentoutff <= exponentoutnode; -- level 30
END IF;
END IF;
END PROCESS;
-- latency 12
-- will give output between 0.5 and 0.99999...
-- will always need to be normalized
-- level 13 in, level 25 out
cinv: fp_inv_core
GENERIC MAP (synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
divisor=>denominatormantissaff,
quotient=>denominatorinverse);
-- level 8 in, level 25 out
dnuma: fp_del
GENERIC MAP (width=>36,pipes=>17)
PORT MAP (sysclk=>sysclk,reset=>'0',enable=>enable, -- no resets for memory
aa=>numeratormantissaff,
cc=>del_numeratormantissa);
-- level 25 in, level 28 out
cmt: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>72,
pipes=>3,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>del_numeratormantissa,
databb=>denominatorinverse,
result=>multiplier_tan);
tanmantissa <= multiplier_tan(72 DOWNTO 37);
gmna: FOR k IN 1 TO 24 GENERATE
tanmantissanorm(k) <= (tanmantissa(k+9) AND NOT(tanmantissa(35))) OR
(tanmantissa(k+10) AND tanmantissa(35));
END GENERATE;
gmnb: FOR k IN 1 TO 9 GENERATE
tanmantissatail(k) <= (tanmantissa(k) AND NOT(tanmantissa(35))) OR
(tanmantissa(k+1) AND tanmantissa(35));
END GENERATE;
overcheck(1) <= tanmantissanorm(1);
gova: FOR k IN 2 TO 24 GENERATE
overcheck(k) <= overcheck(k-1) AND tanmantissanorm(k);
END GENERATE;
-- level 13 in, level 27 out
ddena: fp_del
GENERIC MAP (width=>6,pipes=>14)
PORT MAP (sysclk=>sysclk,reset=>'0',enable=>enable, -- no resets for memory
aa=>inverseexponentff,
cc=>del_inverseexponent);
-- level 8 in, level 27 out
dnumb: fp_del
GENERIC MAP (width=>5,pipes=>19)
PORT MAP (sysclk=>sysclk,reset=>'0',enable=>enable, -- no resets for memory
aa=>numeratorexponentff,
cc=>del_numeratorexponent);
tanexponent <= "01110111" +
(del_numeratorexponent(5) & del_numeratorexponent(5) & del_numeratorexponent(5) & del_numeratorexponent) +
(del_inverseexponent(6) & del_inverseexponent(6) & del_inverseexponent); -- 119 + exponent
tanexponentnorm <= tanexponentff + tanmantissa(35);
--*** handle small inputs ****
dsma: fp_del
GENERIC MAP (width=>23,pipes=>29)
PORT MAP (sysclk=>sysclk,reset=>'0',enable=>enable, -- no resets for memory
aa=>mantissain,
cc=>small_mantissa);
dsxa: fp_del
GENERIC MAP (width=>8,pipes=>29)
PORT MAP (sysclk=>sysclk,reset=>'0',enable=>enable, -- no resets for memory
aa=>exponentin,
cc=>small_exponent);
exponentcheck <= exponentinff - 115;
psa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 30 LOOP
signff(k) <= '0';
END LOOP;
FOR k IN 1 TO 28 LOOP
small_inputff(k) <= '0';
END LOOP;
ELSIF(rising_edge(sysclk)) THEN
IF (enable = '1') THEN
signff(1) <= signin;
FOR k IN 2 TO 30 LOOP
signff(k) <= signff(k-1);
END LOOP;
small_inputff(1) <= exponentcheck(8);
FOR k IN 2 TO 28 LOOP
small_inputff(k) <= small_inputff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
--mantissabase(1) <= (tanmantissanormff(1) AND NOT(small_inputff(28)));
mantissabase(1) <= (roundbitff AND NOT(small_inputff(28)));
gmba: FOR k IN 2 TO 24 GENERATE
mantissabase(k) <= (small_mantissa(k-1) AND small_inputff(28)) OR
(tanmantissanormff(k) AND NOT(small_inputff(28)));
END GENERATE;
gxba: FOR k IN 1 TO 8 GENERATE
exponentbase(k) <= (small_exponent(k) AND small_inputff(28)) OR
(tanexponentnormff(k) AND NOT(small_inputff(28)));
END GENERATE;
mantissaoutnode <= mantissabase(24 DOWNTO 2) + mantissabase(1);
exponentoutnode <= exponentbase + (overff AND NOT(small_inputff(28)));
--***************
--*** OUTPUTS ***
--***************
signout <= signff(30);
mantissaout <= mantissaoutff;
exponentout <= exponentoutff;
END rtl;
|
mit
|
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC
|
Gaussian_Filter/ip/Gaussian_Filter/fp_div_est.vhd
|
10
|
6558
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_DIV_EST.VHD ***
--*** ***
--*** Function: Estimates 18 Bit Inverse ***
--*** ***
--*** Used by both single and double dividers ***
--*** ***
--*** 31/01/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** 1. Inverse of 18 bit header ***
--*** (not including leading '1') ***
--*** 2. Uses 20 bit precision tables - 18 bits ***
--*** drops a bit occasionally ***
--***************************************************
ENTITY fp_div_est IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
divisor : IN STD_LOGIC_VECTOR (19 DOWNTO 1);
invdivisor : OUT STD_LOGIC_VECTOR (18 DOWNTO 1)
);
END fp_div_est;
ARCHITECTURE rtl OF fp_div_est IS
type twodelfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (9 DOWNTO 1);
type ziplutdelfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (20 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (17 DOWNTO 1);
signal one, two : STD_LOGIC_VECTOR (9 DOWNTO 1);
signal oneaddff, zipaddff : STD_LOGIC_VECTOR (9 DOWNTO 1);
signal onelut, onelutff : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal ziplut, ziplutff : STD_LOGIC_VECTOR (20 DOWNTO 1);
signal onetwo : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal twodelff : twodelfftype;
signal ziplutdelff : ziplutdelfftype;
signal invdivisorff : STD_LOGIC_VECTOR (20 DOWNTO 1);
component fp_div_lut1 IS
PORT (
add : IN STD_LOGIC_VECTOR (9 DOWNTO 1);
data : OUT STD_LOGIC_VECTOR (11 DOWNTO 1)
);
end component;
component fp_div_lut0 IS
PORT (
add : IN STD_LOGIC_VECTOR (9 DOWNTO 1);
data : OUT STD_LOGIC_VECTOR (20 DOWNTO 1)
);
end component;
component fp_fxmul
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36;
pipes : positive := 1;
accuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
BEGIN
gza: FOR k IN 1 TO 17 GENERATE
zerovec(k) <= '0';
END GENERATE;
one <= divisor(18 DOWNTO 10);
two <= divisor(9 DOWNTO 1);
-- these register seperate to make the LUTs into memories
pma: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 9 LOOP
oneaddff(k) <= '0';
zipaddff(k) <= '0';
END LOOP;
FOR k IN 1 TO 11 LOOP
onelutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 20 LOOP
ziplutff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
oneaddff <= one;
zipaddff <= one;
onelutff <= onelut;
ziplutff <= ziplut;
END IF;
END IF;
END PROCESS;
upper: fp_div_lut1 PORT MAP (add=>oneaddff,data=>onelut);
lower: fp_div_lut0 PORT MAP (add=>zipaddff,data=>ziplut);
pra: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 2 LOOP
FOR j IN 1 TO 9 LOOP
twodelff(k)(j) <= '0';
END LOOP;
END LOOP;
FOR k IN 1 TO 2 LOOP
FOR j IN 1 TO 9 LOOP
ziplutdelff(k)(j) <= '0';
END LOOP;
END LOOP;
FOR k IN 1 TO 20 LOOP
invdivisorff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
twodelff(1)(9 DOWNTO 1) <= two;
twodelff(2)(9 DOWNTO 1) <= twodelff(1)(9 DOWNTO 1);
ziplutdelff(1)(20 DOWNTO 1) <= ziplutff;
ziplutdelff(2)(20 DOWNTO 1) <= ziplutdelff(1)(20 DOWNTO 1);
invdivisorff <= ziplutdelff(2)(20 DOWNTO 1) -
(zerovec(9 DOWNTO 1) & onetwo);
END IF;
END IF;
END PROCESS;
mulcore: fp_fxmul
GENERIC MAP (widthaa=>11,widthbb=>9,widthcc=>11,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>onelutff,databb=>twodelff(2)(9 DOWNTO 1),
result=>onetwo);
invdivisor <= invdivisorff(20 DOWNTO 3);
END rtl;
|
mit
|
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC
|
Gaussian_Filter/ip/Gaussian_Filter/hcc_normfp1x.vhd
|
10
|
10480
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_NORMFP1X.VHD ***
--*** ***
--*** Function: Normalize single precision ***
--*** number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 28/12/07 - divider target uses all of ***
--*** mantissa width ***
--*** 06/02/08 - fix divider norm ***
--*** 21/03/08 - fix add tree output norm ***
--*** ***
--***************************************************
-- normalize signed numbers (x input format) - for 1x multipliers
-- format signed32/36 bit mantissa, 10 bit exponent
-- unsigned numbers for divider (S,1,23 bit mantissa for divider)
-- divider packed into 32/36bit mantissa + exponent
ENTITY hcc_normfp1x IS
GENERIC (
mantissa : positive := 32; -- 32 or 36
inputnormalize : integer := 1; -- 0 = scale, 1 = normalize
roundnormalize : integer := 1;
normspeed : positive := 2; -- 1 or 2
target : integer := 0 -- 0 = mult target (signed), 1 = divider target (unsigned), 2 adder tree
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
END hcc_normfp1x;
ARCHITECTURE rtl OF hcc_normfp1x IS
type expfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (10 DOWNTO 1);
signal aaff : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
signal ccnode : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
-- scale
signal aasatff, aazipff : STD_LOGIC;
signal countaa : STD_LOGIC_VECTOR (3 DOWNTO 1);
-- normalize
signal zerovec : STD_LOGIC_VECTOR (mantissa-1 DOWNTO 1);
signal normfracnode, normnode : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal normfracff, normff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal countadjust : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal exptopff, expbotff : expfftype;
signal aasatdelff, aazipdelff : STD_LOGIC_VECTOR (5 DOWNTO 1);
signal countsign : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal normsignnode : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal aaexp, ccexp : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal aaman, ccman : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
component hcc_normsgn3236
GENERIC (
mantissa : positive := 32;
normspeed : positive := 1 -- 1 or 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fracin : IN STD_LOGIC_VECTOR (mantissa DOWNTO 1);
countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1);
fracout : OUT STD_LOGIC_VECTOR (mantissa DOWNTO 1)
);
end component;
component hcc_scmul3236
GENERIC (mantissa : positive := 32);
PORT (
frac : IN STD_LOGIC_VECTOR (mantissa DOWNTO 1);
scaled : OUT STD_LOGIC_VECTOR (mantissa DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (3 DOWNTO 1)
);
end component;
BEGIN
--********************************************************
--*** scale multiplier ***
--*** multiplier format [S][1][mantissa....] ***
--*** one clock latency ***
--********************************************************
-- make sure right format & adjust exponent
gsa: IF (inputnormalize = 0) GENERATE
psa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO mantissa+10 LOOP
aaff(k) <= '0';
END LOOP;
aasatff <= '0';
aazipff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaff <= aa;
aasatff <= aasat;
aazipff <= aazip;
END IF;
END IF;
END PROCESS;
-- no rounding when scaling
sma: hcc_scmul3236
GENERIC MAP (mantissa=>mantissa)
PORT MAP (frac=>aaff(mantissa+10 DOWNTO 11),
scaled=>ccnode(mantissa+10 DOWNTO 11),count=>countaa);
ccnode(10 DOWNTO 1) <= aaff(10 DOWNTO 1) + ("0000000" & countaa);
cc <= ccnode;
ccsat <= aasatff;
cczip <= aazipff;
END GENERATE;
--********************************************************
--*** full normalization of input - 4 stages ***
--*** unlike double, no round required on output, as ***
--*** no information lost ***
--********************************************************
gna: IF (inputnormalize = 1) GENERATE -- normalize
gza: FOR k IN 1 TO mantissa-1 GENERATE
zerovec(k) <= '0';
END GENERATE;
-- if multiplier, "1" which is nominally in position 27, is shifted to position 31
-- add 4 to exponent when multiplier, 0 for adder
gxa: IF (target < 2) GENERATE
countadjust <= conv_std_logic_vector (4,10);
END GENERATE;
gxb: IF (target = 2) GENERATE
countadjust <= conv_std_logic_vector (4,10);
END GENERATE;
pna: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO mantissa+10 LOOP
aaff(k) <= '0';
END LOOP;
FOR k IN 1 TO mantissa LOOP
normfracff(k) <= '0';
normff(k) <= '0';
END LOOP;
FOR k IN 1 TO 10 LOOP
exptopff(1)(k) <= '0';
exptopff(2)(k) <= '0';
expbotff(1)(k) <= '0';
expbotff(2)(k) <= '0';
END LOOP;
FOR k IN 1 TO 5 LOOP
aasatdelff(k) <= '0';
aazipdelff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaff <= aa;
normfracff <= normfracnode;
--might not get used
normff <= normnode;
exptopff(1)(10 DOWNTO 1) <= aaff(10 DOWNTO 1) + countadjust;
exptopff(2)(10 DOWNTO 1) <= exptopff(1)(10 DOWNTO 1) - ("0000" & countsign);
--might not get used
expbotff(1)(10 DOWNTO 1) <= exptopff(2)(10 DOWNTO 1);
expbotff(2)(10 DOWNTO 1) <= expbotff(1)(10 DOWNTO 1);
aasatdelff(1) <= aasat;
aazipdelff(1) <= aazip;
FOR k IN 2 TO 5 LOOP -- 4&5 might not get used
aasatdelff(k) <= aasatdelff(k-1);
aazipdelff(k) <= aazipdelff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
nrmc: hcc_normsgn3236
GENERIC MAP (mantissa=>mantissa,normspeed=>normspeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
fracin=>aaff(mantissa+10 DOWNTO 11),
countout=>countsign, -- stage 1 or 2
fracout=>normfracnode); -- stage 2 or 3
gnb: IF (target = 1) GENERATE
gnc: FOR k IN 1 TO mantissa GENERATE
normsignnode(k) <= normfracff(k) XOR normfracff(mantissa);
END GENERATE;
normnode(mantissa-1 DOWNTO 1) <= normsignnode(mantissa-1 DOWNTO 1) +
(zerovec(mantissa-2 DOWNTO 1) & normfracff(mantissa));
-- 06/02/08 make sure signbit is packed with the mantissa
normnode(mantissa) <= normfracff(mantissa);
--*** OUTPUTS ***
ccnode(mantissa+10 DOWNTO 11) <= normff;
ccnode(10 DOWNTO 1) <= expbotff(normspeed)(10 DOWNTO 1);
ccsat <= aasatdelff(3+normspeed);
cczip <= aazipdelff(3+normspeed);
END GENERATE;
gnc: IF (target = 0) GENERATE
--*** OUTPUTS ***
ccnode(mantissa+10 DOWNTO 11) <= normfracff;
gma: IF (normspeed = 1) GENERATE
ccnode(10 DOWNTO 1) <= exptopff(2)(10 DOWNTO 1);
END GENERATE;
gmb: IF (normspeed > 1) GENERATE
ccnode(10 DOWNTO 1) <= expbotff(1)(10 DOWNTO 1);
END GENERATE;
ccsat <= aasatdelff(2+normspeed);
cczip <= aazipdelff(2+normspeed);
END GENERATE;
gnd: IF (target = 2) GENERATE
gaa: IF (roundnormalize = 1) GENERATE
normnode <= (normfracff(mantissa) & normfracff(mantissa) &
normfracff(mantissa) & normfracff(mantissa) &
normfracff(mantissa DOWNTO 5)) +
(zerovec(mantissa-1 DOWNTO 1) & normfracff(4));
END GENERATE;
--*** OUTPUTS ***
gab: IF (roundnormalize = 0) GENERATE -- 21/03/08 fixed this to SSSSS1XXXXX
ccnode(mantissa+10 DOWNTO 11) <= normfracff(mantissa) & normfracff(mantissa) &
normfracff(mantissa) & normfracff(mantissa) &
normfracff(mantissa DOWNTO 5);
END GENERATE;
gac: IF (roundnormalize = 1) GENERATE
ccnode(mantissa+10 DOWNTO 11) <= normff;
END GENERATE;
gad: IF (normspeed = 1 AND roundnormalize = 0) GENERATE
ccnode(10 DOWNTO 1) <= exptopff(2)(10 DOWNTO 1);
END GENERATE;
gae: IF ((normspeed = 2 AND roundnormalize = 0) OR
(normspeed = 1 AND roundnormalize = 1)) GENERATE
ccnode(10 DOWNTO 1) <= expbotff(1)(10 DOWNTO 1);
END GENERATE;
gaf: IF (normspeed = 2 AND roundnormalize = 1) GENERATE
ccnode(10 DOWNTO 1) <= expbotff(2)(10 DOWNTO 1);
END GENERATE;
ccsat <= aasatdelff(2+normspeed+roundnormalize);
cczip <= aazipdelff(2+normspeed+roundnormalize);
END GENERATE;
cc <= ccnode;
END GENERATE;
--*** DEBUG ***
aaexp <= aa(10 DOWNTO 1);
aaman <= aa(mantissa+10 DOWNTO 11);
ccexp <= ccnode(10 DOWNTO 1);
ccman <= ccnode(mantissa+10 DOWNTO 11);
END rtl;
|
mit
|
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC
|
bin_Gaussian_Filter/ip/Gaussian_Filter/fp_explut8.vhd
|
10
|
36966
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_EXPLUT8.VHD ***
--*** ***
--*** Function: Look Up Table - EXP() ***
--*** ***
--*** Generated by MATLAB Utility ***
--*** ***
--*** 18/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_explut8 IS
PORT (
address : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissa : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
exponent : OUT STD_LOGIC_VECTOR (8 DOWNTO 1)
);
END fp_explut8;
ARCHITECTURE rtl OF fp_explut8 IS
BEGIN
pca: PROCESS (address)
BEGIN
CASE address IS
WHEN "00000000" =>
mantissa <= conv_std_logic_vector(0,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00000001" =>
mantissa <= conv_std_logic_vector(32832,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00000010" =>
mantissa <= conv_std_logic_vector(65793,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00000011" =>
mantissa <= conv_std_logic_vector(98882,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00000100" =>
mantissa <= conv_std_logic_vector(132101,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00000101" =>
mantissa <= conv_std_logic_vector(165450,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00000110" =>
mantissa <= conv_std_logic_vector(198930,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00000111" =>
mantissa <= conv_std_logic_vector(232541,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00001000" =>
mantissa <= conv_std_logic_vector(266283,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00001001" =>
mantissa <= conv_std_logic_vector(300157,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00001010" =>
mantissa <= conv_std_logic_vector(334164,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00001011" =>
mantissa <= conv_std_logic_vector(368304,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00001100" =>
mantissa <= conv_std_logic_vector(402578,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00001101" =>
mantissa <= conv_std_logic_vector(436985,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00001110" =>
mantissa <= conv_std_logic_vector(471528,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00001111" =>
mantissa <= conv_std_logic_vector(506205,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00010000" =>
mantissa <= conv_std_logic_vector(541019,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00010001" =>
mantissa <= conv_std_logic_vector(575968,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00010010" =>
mantissa <= conv_std_logic_vector(611055,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00010011" =>
mantissa <= conv_std_logic_vector(646278,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00010100" =>
mantissa <= conv_std_logic_vector(681640,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00010101" =>
mantissa <= conv_std_logic_vector(717140,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00010110" =>
mantissa <= conv_std_logic_vector(752779,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00010111" =>
mantissa <= conv_std_logic_vector(788557,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00011000" =>
mantissa <= conv_std_logic_vector(824476,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00011001" =>
mantissa <= conv_std_logic_vector(860535,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00011010" =>
mantissa <= conv_std_logic_vector(896735,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00011011" =>
mantissa <= conv_std_logic_vector(933076,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00011100" =>
mantissa <= conv_std_logic_vector(969560,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00011101" =>
mantissa <= conv_std_logic_vector(1006187,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00011110" =>
mantissa <= conv_std_logic_vector(1042957,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00011111" =>
mantissa <= conv_std_logic_vector(1079872,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00100000" =>
mantissa <= conv_std_logic_vector(1116930,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00100001" =>
mantissa <= conv_std_logic_vector(1154134,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00100010" =>
mantissa <= conv_std_logic_vector(1191483,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00100011" =>
mantissa <= conv_std_logic_vector(1228978,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00100100" =>
mantissa <= conv_std_logic_vector(1266621,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00100101" =>
mantissa <= conv_std_logic_vector(1304410,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00100110" =>
mantissa <= conv_std_logic_vector(1342348,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00100111" =>
mantissa <= conv_std_logic_vector(1380433,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00101000" =>
mantissa <= conv_std_logic_vector(1418668,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00101001" =>
mantissa <= conv_std_logic_vector(1457053,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00101010" =>
mantissa <= conv_std_logic_vector(1495588,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00101011" =>
mantissa <= conv_std_logic_vector(1534273,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00101100" =>
mantissa <= conv_std_logic_vector(1573110,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00101101" =>
mantissa <= conv_std_logic_vector(1612100,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00101110" =>
mantissa <= conv_std_logic_vector(1651241,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00101111" =>
mantissa <= conv_std_logic_vector(1690536,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00110000" =>
mantissa <= conv_std_logic_vector(1729985,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00110001" =>
mantissa <= conv_std_logic_vector(1769588,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00110010" =>
mantissa <= conv_std_logic_vector(1809346,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00110011" =>
mantissa <= conv_std_logic_vector(1849259,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00110100" =>
mantissa <= conv_std_logic_vector(1889329,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00110101" =>
mantissa <= conv_std_logic_vector(1929556,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00110110" =>
mantissa <= conv_std_logic_vector(1969940,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00110111" =>
mantissa <= conv_std_logic_vector(2010482,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00111000" =>
mantissa <= conv_std_logic_vector(2051183,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00111001" =>
mantissa <= conv_std_logic_vector(2092044,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00111010" =>
mantissa <= conv_std_logic_vector(2133064,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00111011" =>
mantissa <= conv_std_logic_vector(2174244,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00111100" =>
mantissa <= conv_std_logic_vector(2215586,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00111101" =>
mantissa <= conv_std_logic_vector(2257090,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00111110" =>
mantissa <= conv_std_logic_vector(2298756,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "00111111" =>
mantissa <= conv_std_logic_vector(2340585,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01000000" =>
mantissa <= conv_std_logic_vector(2382578,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01000001" =>
mantissa <= conv_std_logic_vector(2424735,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01000010" =>
mantissa <= conv_std_logic_vector(2467057,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01000011" =>
mantissa <= conv_std_logic_vector(2509545,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01000100" =>
mantissa <= conv_std_logic_vector(2552199,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01000101" =>
mantissa <= conv_std_logic_vector(2595020,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01000110" =>
mantissa <= conv_std_logic_vector(2638009,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01000111" =>
mantissa <= conv_std_logic_vector(2681166,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01001000" =>
mantissa <= conv_std_logic_vector(2724492,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01001001" =>
mantissa <= conv_std_logic_vector(2767987,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01001010" =>
mantissa <= conv_std_logic_vector(2811653,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01001011" =>
mantissa <= conv_std_logic_vector(2855490,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01001100" =>
mantissa <= conv_std_logic_vector(2899498,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01001101" =>
mantissa <= conv_std_logic_vector(2943678,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01001110" =>
mantissa <= conv_std_logic_vector(2988032,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01001111" =>
mantissa <= conv_std_logic_vector(3032559,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01010000" =>
mantissa <= conv_std_logic_vector(3077260,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01010001" =>
mantissa <= conv_std_logic_vector(3122136,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01010010" =>
mantissa <= conv_std_logic_vector(3167188,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01010011" =>
mantissa <= conv_std_logic_vector(3212416,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01010100" =>
mantissa <= conv_std_logic_vector(3257821,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01010101" =>
mantissa <= conv_std_logic_vector(3303404,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01010110" =>
mantissa <= conv_std_logic_vector(3349165,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01010111" =>
mantissa <= conv_std_logic_vector(3395105,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01011000" =>
mantissa <= conv_std_logic_vector(3441225,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01011001" =>
mantissa <= conv_std_logic_vector(3487526,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01011010" =>
mantissa <= conv_std_logic_vector(3534008,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01011011" =>
mantissa <= conv_std_logic_vector(3580672,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01011100" =>
mantissa <= conv_std_logic_vector(3627518,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01011101" =>
mantissa <= conv_std_logic_vector(3674548,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01011110" =>
mantissa <= conv_std_logic_vector(3721762,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01011111" =>
mantissa <= conv_std_logic_vector(3769160,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01100000" =>
mantissa <= conv_std_logic_vector(3816745,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01100001" =>
mantissa <= conv_std_logic_vector(3864515,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01100010" =>
mantissa <= conv_std_logic_vector(3912472,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01100011" =>
mantissa <= conv_std_logic_vector(3960617,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01100100" =>
mantissa <= conv_std_logic_vector(4008951,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01100101" =>
mantissa <= conv_std_logic_vector(4057474,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01100110" =>
mantissa <= conv_std_logic_vector(4106186,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01100111" =>
mantissa <= conv_std_logic_vector(4155089,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01101000" =>
mantissa <= conv_std_logic_vector(4204184,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01101001" =>
mantissa <= conv_std_logic_vector(4253471,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01101010" =>
mantissa <= conv_std_logic_vector(4302951,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01101011" =>
mantissa <= conv_std_logic_vector(4352624,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01101100" =>
mantissa <= conv_std_logic_vector(4402492,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01101101" =>
mantissa <= conv_std_logic_vector(4452555,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01101110" =>
mantissa <= conv_std_logic_vector(4502814,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01101111" =>
mantissa <= conv_std_logic_vector(4553269,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01110000" =>
mantissa <= conv_std_logic_vector(4603922,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01110001" =>
mantissa <= conv_std_logic_vector(4654774,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01110010" =>
mantissa <= conv_std_logic_vector(4705824,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01110011" =>
mantissa <= conv_std_logic_vector(4757074,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01110100" =>
mantissa <= conv_std_logic_vector(4808525,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01110101" =>
mantissa <= conv_std_logic_vector(4860177,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01110110" =>
mantissa <= conv_std_logic_vector(4912031,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01110111" =>
mantissa <= conv_std_logic_vector(4964088,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01111000" =>
mantissa <= conv_std_logic_vector(5016349,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01111001" =>
mantissa <= conv_std_logic_vector(5068815,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01111010" =>
mantissa <= conv_std_logic_vector(5121486,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01111011" =>
mantissa <= conv_std_logic_vector(5174363,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01111100" =>
mantissa <= conv_std_logic_vector(5227447,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01111101" =>
mantissa <= conv_std_logic_vector(5280739,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01111110" =>
mantissa <= conv_std_logic_vector(5334239,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "01111111" =>
mantissa <= conv_std_logic_vector(5387949,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10000000" =>
mantissa <= conv_std_logic_vector(5441868,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10000001" =>
mantissa <= conv_std_logic_vector(5495999,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10000010" =>
mantissa <= conv_std_logic_vector(5550342,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10000011" =>
mantissa <= conv_std_logic_vector(5604898,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10000100" =>
mantissa <= conv_std_logic_vector(5659667,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10000101" =>
mantissa <= conv_std_logic_vector(5714650,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10000110" =>
mantissa <= conv_std_logic_vector(5769849,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10000111" =>
mantissa <= conv_std_logic_vector(5825263,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10001000" =>
mantissa <= conv_std_logic_vector(5880895,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10001001" =>
mantissa <= conv_std_logic_vector(5936744,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10001010" =>
mantissa <= conv_std_logic_vector(5992812,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10001011" =>
mantissa <= conv_std_logic_vector(6049099,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10001100" =>
mantissa <= conv_std_logic_vector(6105607,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10001101" =>
mantissa <= conv_std_logic_vector(6162336,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10001110" =>
mantissa <= conv_std_logic_vector(6219286,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10001111" =>
mantissa <= conv_std_logic_vector(6276460,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10010000" =>
mantissa <= conv_std_logic_vector(6333858,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10010001" =>
mantissa <= conv_std_logic_vector(6391480,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10010010" =>
mantissa <= conv_std_logic_vector(6449327,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10010011" =>
mantissa <= conv_std_logic_vector(6507401,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10010100" =>
mantissa <= conv_std_logic_vector(6565703,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10010101" =>
mantissa <= conv_std_logic_vector(6624232,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10010110" =>
mantissa <= conv_std_logic_vector(6682991,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10010111" =>
mantissa <= conv_std_logic_vector(6741979,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10011000" =>
mantissa <= conv_std_logic_vector(6801199,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10011001" =>
mantissa <= conv_std_logic_vector(6860650,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10011010" =>
mantissa <= conv_std_logic_vector(6920334,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10011011" =>
mantissa <= conv_std_logic_vector(6980251,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10011100" =>
mantissa <= conv_std_logic_vector(7040403,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10011101" =>
mantissa <= conv_std_logic_vector(7100791,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10011110" =>
mantissa <= conv_std_logic_vector(7161415,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10011111" =>
mantissa <= conv_std_logic_vector(7222276,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10100000" =>
mantissa <= conv_std_logic_vector(7283375,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10100001" =>
mantissa <= conv_std_logic_vector(7344713,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10100010" =>
mantissa <= conv_std_logic_vector(7406292,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10100011" =>
mantissa <= conv_std_logic_vector(7468111,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10100100" =>
mantissa <= conv_std_logic_vector(7530173,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10100101" =>
mantissa <= conv_std_logic_vector(7592477,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10100110" =>
mantissa <= conv_std_logic_vector(7655025,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10100111" =>
mantissa <= conv_std_logic_vector(7717818,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10101000" =>
mantissa <= conv_std_logic_vector(7780857,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10101001" =>
mantissa <= conv_std_logic_vector(7844143,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10101010" =>
mantissa <= conv_std_logic_vector(7907676,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10101011" =>
mantissa <= conv_std_logic_vector(7971458,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10101100" =>
mantissa <= conv_std_logic_vector(8035489,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10101101" =>
mantissa <= conv_std_logic_vector(8099771,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10101110" =>
mantissa <= conv_std_logic_vector(8164305,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10101111" =>
mantissa <= conv_std_logic_vector(8229091,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10110000" =>
mantissa <= conv_std_logic_vector(8294131,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10110001" =>
mantissa <= conv_std_logic_vector(8359425,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "10110010" =>
mantissa <= conv_std_logic_vector(18184,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10110011" =>
mantissa <= conv_std_logic_vector(51087,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10110100" =>
mantissa <= conv_std_logic_vector(84119,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10110101" =>
mantissa <= conv_std_logic_vector(117280,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10110110" =>
mantissa <= conv_std_logic_vector(150571,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10110111" =>
mantissa <= conv_std_logic_vector(183993,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10111000" =>
mantissa <= conv_std_logic_vector(217545,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10111001" =>
mantissa <= conv_std_logic_vector(251229,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10111010" =>
mantissa <= conv_std_logic_vector(285044,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10111011" =>
mantissa <= conv_std_logic_vector(318992,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10111100" =>
mantissa <= conv_std_logic_vector(353072,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10111101" =>
mantissa <= conv_std_logic_vector(387286,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10111110" =>
mantissa <= conv_std_logic_vector(421634,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "10111111" =>
mantissa <= conv_std_logic_vector(456116,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11000000" =>
mantissa <= conv_std_logic_vector(490734,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11000001" =>
mantissa <= conv_std_logic_vector(525486,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11000010" =>
mantissa <= conv_std_logic_vector(560375,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11000011" =>
mantissa <= conv_std_logic_vector(595401,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11000100" =>
mantissa <= conv_std_logic_vector(630563,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11000101" =>
mantissa <= conv_std_logic_vector(665863,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11000110" =>
mantissa <= conv_std_logic_vector(701301,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11000111" =>
mantissa <= conv_std_logic_vector(736878,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11001000" =>
mantissa <= conv_std_logic_vector(772594,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11001001" =>
mantissa <= conv_std_logic_vector(808450,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11001010" =>
mantissa <= conv_std_logic_vector(844446,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11001011" =>
mantissa <= conv_std_logic_vector(880584,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11001100" =>
mantissa <= conv_std_logic_vector(916862,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11001101" =>
mantissa <= conv_std_logic_vector(953283,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11001110" =>
mantissa <= conv_std_logic_vector(989846,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11001111" =>
mantissa <= conv_std_logic_vector(1026552,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11010000" =>
mantissa <= conv_std_logic_vector(1063402,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11010001" =>
mantissa <= conv_std_logic_vector(1100396,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11010010" =>
mantissa <= conv_std_logic_vector(1137535,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11010011" =>
mantissa <= conv_std_logic_vector(1174819,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11010100" =>
mantissa <= conv_std_logic_vector(1212249,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11010101" =>
mantissa <= conv_std_logic_vector(1249826,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11010110" =>
mantissa <= conv_std_logic_vector(1287550,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11010111" =>
mantissa <= conv_std_logic_vector(1325421,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11011000" =>
mantissa <= conv_std_logic_vector(1363441,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11011001" =>
mantissa <= conv_std_logic_vector(1401609,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11011010" =>
mantissa <= conv_std_logic_vector(1439927,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11011011" =>
mantissa <= conv_std_logic_vector(1478395,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11011100" =>
mantissa <= conv_std_logic_vector(1517013,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11011101" =>
mantissa <= conv_std_logic_vector(1555783,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11011110" =>
mantissa <= conv_std_logic_vector(1594704,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11011111" =>
mantissa <= conv_std_logic_vector(1633778,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11100000" =>
mantissa <= conv_std_logic_vector(1673004,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11100001" =>
mantissa <= conv_std_logic_vector(1712384,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11100010" =>
mantissa <= conv_std_logic_vector(1751918,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11100011" =>
mantissa <= conv_std_logic_vector(1791607,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11100100" =>
mantissa <= conv_std_logic_vector(1831452,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11100101" =>
mantissa <= conv_std_logic_vector(1871452,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11100110" =>
mantissa <= conv_std_logic_vector(1911608,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11100111" =>
mantissa <= conv_std_logic_vector(1951922,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11101000" =>
mantissa <= conv_std_logic_vector(1992394,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11101001" =>
mantissa <= conv_std_logic_vector(2033024,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11101010" =>
mantissa <= conv_std_logic_vector(2073813,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11101011" =>
mantissa <= conv_std_logic_vector(2114762,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11101100" =>
mantissa <= conv_std_logic_vector(2155871,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11101101" =>
mantissa <= conv_std_logic_vector(2197141,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11101110" =>
mantissa <= conv_std_logic_vector(2238572,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11101111" =>
mantissa <= conv_std_logic_vector(2280166,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11110000" =>
mantissa <= conv_std_logic_vector(2321922,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11110001" =>
mantissa <= conv_std_logic_vector(2363842,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11110010" =>
mantissa <= conv_std_logic_vector(2405926,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11110011" =>
mantissa <= conv_std_logic_vector(2448175,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11110100" =>
mantissa <= conv_std_logic_vector(2490589,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11110101" =>
mantissa <= conv_std_logic_vector(2533169,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11110110" =>
mantissa <= conv_std_logic_vector(2575915,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11110111" =>
mantissa <= conv_std_logic_vector(2618829,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11111000" =>
mantissa <= conv_std_logic_vector(2661911,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11111001" =>
mantissa <= conv_std_logic_vector(2705162,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11111010" =>
mantissa <= conv_std_logic_vector(2748582,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11111011" =>
mantissa <= conv_std_logic_vector(2792171,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11111100" =>
mantissa <= conv_std_logic_vector(2835932,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11111101" =>
mantissa <= conv_std_logic_vector(2879863,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11111110" =>
mantissa <= conv_std_logic_vector(2923967,23);
exponent <= conv_std_logic_vector(128,8);
WHEN "11111111" =>
mantissa <= conv_std_logic_vector(2968243,23);
exponent <= conv_std_logic_vector(128,8);
WHEN others =>
mantissa <= conv_std_logic_vector(0,23);
exponent <= conv_std_logic_vector(0,8);
END CASE;
END PROCESS;
END rtl;
|
mit
|
takeshineshiro/fpga_linear_128
|
lf_ast.vhd
|
3
|
6763
|
-- ================================================================================
-- Legal Notice: Copyright (C) 1991-2006 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera. Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner. Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors. No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.
-- ================================================================================
--
-- Generated by: FIR Compiler 9.0
-- Generated on: 2014-8-27 12:51:35
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library auk_dspip_lib;
use auk_dspip_lib.auk_dspip_lib_pkg_fir_90.all;
entity lf_ast is
port(
clk : in std_logic;
reset_n : in std_logic;
ast_sink_ready : out std_logic;
ast_source_data : out std_logic_vector (31 -1 downto 0);
ast_sink_data : in std_logic_vector (15 -1 downto 0);
ast_sink_valid : in std_logic;
ast_source_valid : out std_logic;
ast_source_ready : in std_logic;
ast_sink_error : in std_logic_vector (1 downto 0);
ast_source_error : out std_logic_vector (1 downto 0)
);
attribute altera_attribute : string;
attribute altera_attribute of lf_ast:entity is "-name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 10036";
end lf_ast;
-- Warnings Suppression On
-- altera message_off 10036
architecture struct of lf_ast is
signal sink_packet_error : std_logic_vector(1 downto 0);
signal data_in : std_logic_vector(15 -1 downto 0);
signal data_out : std_logic_vector(31 -1 downto 0);
signal core_out : std_logic_vector(31 -1 downto 0);
signal ready : std_logic;
signal reset_fir : std_logic;
signal sink_ready_ctrl : std_logic;
signal sink_stall : std_logic;
signal source_packet_error : std_logic_vector(1 downto 0);
signal source_stall : std_logic;
signal source_valid_ctrl : std_logic;
signal stall : std_logic;
signal valid : std_logic;
signal core_valid : std_logic;
signal enable_in : std_logic;
signal stall_delayed : std_logic;
constant ENABLE_PIPELINE_DEPTH_c : natural := 0;
component lf_st is
port (
rst : in std_logic;
clk : in std_logic;
clk_en : in std_logic;
rdy_to_ld : out std_logic;
done : out std_logic;
data_in : in std_logic_vector(15 - 1 downto 0);
fir_result : out std_logic_vector(31 - 1 downto 0));
end component lf_st;
begin
sink : auk_dspip_avalon_streaming_sink_fir_90
generic map (
WIDTH_g => 15,
PACKET_SIZE_g => 1,
FIFO_DEPTH_g => 7,
FAMILY_g => "Cyclone III",
MEM_TYPE_g => "Auto")
port map (
clk => clk,
reset_n => reset_n,
data => data_in,
sink_ready_ctrl => sink_ready_ctrl,
sink_stall => sink_stall,
packet_error => sink_packet_error,
at_sink_ready => ast_sink_ready,
at_sink_valid => ast_sink_valid,
at_sink_data => ast_sink_data,
at_sink_error => ast_sink_error);
source : auk_dspip_avalon_streaming_source_fir_90
generic map (
WIDTH_g => 31,
packet_size_g => 1)
port map (
clk => clk,
reset_n => reset_n,
data => data_out,
source_valid_ctrl => source_valid_ctrl,
design_stall => stall_delayed,
source_stall => source_stall,
packet_error => source_packet_error,
at_source_ready => ast_source_ready,
at_source_valid => ast_source_valid,
at_source_data => ast_source_data,
at_source_error => ast_source_error);
intf_ctrl : auk_dspip_avalon_streaming_controller_fir_90
port map (
clk => clk,
ready => ready,
reset_n => reset_n,
sink_packet_error => sink_packet_error,
sink_stall => sink_stall,
source_stall => source_stall,
valid => valid,
reset_design => reset_fir,
sink_ready_ctrl => sink_ready_ctrl,
source_packet_error => source_packet_error,
source_valid_ctrl => source_valid_ctrl,
stall => stall);
fircore: lf_st
port map (
rst => reset_fir,
clk => clk,
clk_en => enable_in,
rdy_to_ld => ready,
done => core_valid,
data_in => data_in,
fir_result => core_out);
data_out <= core_out;
valid <= core_valid;
enable_in <= not stall;
no_enable_pipeline: if ENABLE_PIPELINE_DEPTH_c = 0 generate
stall_delayed <= stall;
end generate no_enable_pipeline;
enable_pipeline: if ENABLE_PIPELINE_DEPTH_c > 0 generate
delay_core_enable : process (clk, reset_n)
variable stall_delay : std_logic_vector(ENABLE_PIPELINE_DEPTH_c downto 0);
begin -- process delay_core_enable
if reset_n = '0' then
stall_delay := (others => '0');
elsif rising_edge(clk) then
stall_delay := stall_delay(stall_delay'high-1 downto 0) & stall;
end if;
stall_delayed <= stall_delay(stall_delay'high);
end process delay_core_enable;
end generate enable_pipeline;
end struct;
|
mit
|
cwilkens/ecen4024-microphone-array
|
microphone-array/microphone-array.srcs/sources_1/ip/half_band_FIR/fir_compiler_v7_1/hdl/fir_compiler_v7_1.vhd
|
2
|
19272
|
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|
mit
|
okaxaki/vm2413
|
TemporalMixer.vhd
|
2
|
4150
|
--
-- TemporalMixer.vhd
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use WORK.VM2413.ALL;
entity TemporalMixer is
port (
clk : in std_logic;
reset : in std_logic;
clkena : in std_logic;
slot : in SLOT_TYPE;
stage : in STAGE_TYPE;
rhythm : in std_logic;
maddr : out SLOT_TYPE;
mdata : in SIGNED_LI_TYPE;
mo : out std_logic_vector(9 downto 0);
ro : out std_logic_vector(9 downto 0)
);
end TemporalMixer;
architecture RTL of TemporalMixer is
signal mmute, rmute : std_logic;
begin
process (clk, reset)
begin
if reset = '1' then
mo <= (others =>'0');
ro <= (others =>'0');
maddr <= 0;
mmute <= '1';
rmute <= '1';
elsif clk'event and clk = '1' then if clkena='1' then
if stage = 0 then
mo <= "1000000000";
ro <= "1000000000";
if rhythm = '0' then
case slot is
when 0 => maddr <= 1; mmute <='0'; -- CH0
when 1 => maddr <= 3; mmute <='0'; -- CH1
when 2 => maddr <= 5; mmute <='0'; -- CH2
when 3 => mmute <= '1';
when 4 => mmute <= '1';
when 5 => mmute <= '1';
when 6 => maddr <= 7; mmute<='0'; -- CH3
when 7 => maddr <= 9; mmute<='0'; -- CH4
when 8 => maddr <= 11; mmute<='0'; -- CH5
when 9 => mmute <= '1';
when 10 => mmute <= '1';
when 11 => mmute <= '1';
when 12 => maddr <= 13; mmute<='0'; -- CH6
when 13 => maddr <= 15; mmute<='0'; -- CH7
when 14 => maddr <= 17; mmute<='0'; -- CH8
when 15 => mmute <= '1';
when 16 => mmute <= '1';
when 17 => mmute <= '1';
end case;
rmute <= '1';
else
case slot is
when 0 => maddr <= 1; mmute <='0'; rmute <='1'; -- CH0
when 1 => maddr <= 3; mmute <='0'; rmute <='1'; -- CH1
when 2 => maddr <= 5; mmute <='0'; rmute <='1'; -- CH2
when 3 => mmute <='1'; maddr <= 15; rmute <='0'; -- SD
when 4 => mmute <='1'; maddr <= 17; rmute <='0'; -- CYM
when 5 => mmute <='1'; rmute <='1';
when 6 => maddr <= 7; mmute <='0'; rmute <='1'; -- CH3
when 7 => maddr <= 9; mmute <='0'; rmute <='1'; -- CH4
when 8 => maddr <= 11;mmute <='0'; rmute <='1'; -- CH5
when 9 => mmute <='1'; maddr <= 14; rmute <='0'; -- HH
when 10 => mmute <='1'; maddr <= 16; rmute <='0'; -- TOM
when 11 => mmute <='1'; maddr <= 13; rmute <='0'; -- BD
when 12 => mmute <='1'; maddr <= 15; rmute <='0'; -- SD
when 13 => mmute <='1'; maddr <= 17; rmute <='0'; -- CYM
when 14 => mmute <='1'; maddr <= 14; rmute <='0'; -- HH
when 15 => mmute <='1'; maddr <= 16; rmute <='0'; -- TOM
when 16 => mmute <='1'; maddr <= 13; rmute <='0'; -- BD
when 17 => mmute <='1'; rmute <='1';
end case;
end if;
else
if mmute = '0' then
if mdata.sign = '0' then
mo <= "1000000000" + mdata.value;
else
mo <= "1000000000" - mdata.value;
end if;
else
mo <= "1000000000";
end if;
if rmute = '0' then
if mdata.sign = '0' then
ro <= "1000000000" + mdata.value;
else
ro <= "1000000000" - mdata.value;
end if;
else
ro <= "1000000000";
end if;
end if;
end if; end if;
end process;
end RTL;
|
mit
|
okaxaki/vm2413
|
OutputMemory.vhd
|
2
|
1250
|
--
-- OutputMemory.vhd
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use WORK.VM2413.ALL;
entity OutputMemory is port (
clk : in std_logic;
reset : in std_logic;
wr : in std_logic;
addr : in SLOT_TYPE;
wdata : in SIGNED_LI_TYPE;
rdata : out SIGNED_LI_TYPE;
addr2 : in SLOT_TYPE;
rdata2 : out SIGNED_LI_TYPE
);
end OutputMemory;
architecture RTL of OutputMemory is
type SIGNED_LI_ARRAY_TYPE is array (0 to MAXSLOT) of SIGNED_LI_VECTOR_TYPE;
signal data_array : SIGNED_LI_ARRAY_TYPE;
begin
process(clk, reset)
variable init_ch : integer range 0 to MAXSLOT;
begin
if (reset = '1') then
init_ch := 0;
elsif clk'event and clk='1' then
if init_ch /= MAXSLOT then
data_array(init_ch) <= (others=>'0');
init_ch := init_ch + 1;
elsif wr='1' then
data_array(addr) <= CONV_SIGNED_LI_VECTOR(wdata);
end if;
rdata <= CONV_SIGNED_LI(data_array(addr));
rdata2 <= CONV_SIGNED_LI(data_array(addr2));
end if;
end process;
end RTL;
|
mit
|
Given-Jiang/Test_Pattern_Generator
|
Test_Pattern_Generator_dspbuilder/db/alt_dspbuilder_cast_GN5EYRLJQW.vhd
|
4
|
857
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GN5EYRLJQW is
generic ( round : natural := 0;
saturate : natural := 0);
port(
input : in std_logic_vector(24 downto 0);
output : out std_logic_vector(23 downto 0));
end entity;
architecture rtl of alt_dspbuilder_cast_GN5EYRLJQW is
Begin
-- Output - I/O assignment from Simulink Block "Output"
Outputi : alt_dspbuilder_SBF generic map(
width_inl=> 25 ,
width_inr=> 0,
width_outl=> 24,
width_outr=> 0,
lpm_signed=> BusIsUnsigned ,
round=> round,
satur=> saturate)
port map (
xin(24 downto 0) => input,
yout => output
);
end architecture;
|
mit
|
Given-Jiang/Test_Pattern_Generator
|
tb_Test_Pattern_Generator/hdl/alt_dspbuilder_cast_GNLWRZWTQF.vhd
|
8
|
852
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GNLWRZWTQF is
generic ( round : natural := 0;
saturate : natural := 0);
port(
input : in std_logic_vector(2 downto 0);
output : out std_logic_vector(2 downto 0));
end entity;
architecture rtl of alt_dspbuilder_cast_GNLWRZWTQF is
Begin
-- Output - I/O assignment from Simulink Block "Output"
Outputi : alt_dspbuilder_SBF generic map(
width_inl=> 3 ,
width_inr=> 0,
width_outl=> 3,
width_outr=> 0,
lpm_signed=> BusIsUnsigned ,
round=> round,
satur=> saturate)
port map (
xin(2 downto 0) => input,
yout => output
);
end architecture;
|
mit
|
Given-Jiang/Test_Pattern_Generator
|
tb_Test_Pattern_Generator/hdl/tb_Test_Pattern_Generator.vhd
|
2
|
11418
|
-- tb_Test_Pattern_Generator.vhd
-- Generated using ACDS version 13.1 162 at 2015.02.11.10:36:06
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity tb_Test_Pattern_Generator is
end entity tb_Test_Pattern_Generator;
architecture rtl of tb_Test_Pattern_Generator is
component Test_Pattern_Generator_GN is
port (
Clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset_n
Avalon_MM_Slave_address : in std_logic_vector(1 downto 0) := (others => 'X'); -- wire
Avalon_ST_Source_valid : out std_logic; -- wire
Avalon_MM_Slave_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- wire
Avalon_ST_Source_endofpacket : out std_logic; -- wire
Avalon_ST_Source_startofpacket : out std_logic; -- wire
Avalon_MM_Slave_write : in std_logic := 'X'; -- wire
Avalon_ST_Source_data : out std_logic_vector(23 downto 0); -- wire
Avalon_ST_Source_ready : in std_logic := 'X' -- wire
);
end component Test_Pattern_Generator_GN;
component alt_dspbuilder_testbench_clock_GNCGUFKHRR is
generic (
SIMULATION_START_CYCLE : natural := 4;
RESET_LATENCY : natural := 0;
RESET_REGISTER_CASCADE_DEPTH : natural := 0
);
port (
aclr_out : out std_logic; -- reset
clock_out : out std_logic; -- clk
reg_aclr_out : out std_logic; -- reset
tb_aclr : out std_logic -- reset
);
end component alt_dspbuilder_testbench_clock_GNCGUFKHRR;
component alt_dspbuilder_testbench_salt_GN6DKNTQ5M is
generic (
XFILE : string := "default"
);
port (
clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
output : out std_logic_vector(1 downto 0) -- wire
);
end component alt_dspbuilder_testbench_salt_GN6DKNTQ5M;
component alt_dspbuilder_testbench_salt_GN7Z4SHGOK is
generic (
XFILE : string := "default"
);
port (
clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
output : out std_logic_vector(31 downto 0) -- wire
);
end component alt_dspbuilder_testbench_salt_GN7Z4SHGOK;
component alt_dspbuilder_testbench_salt_GNDBMPYDND is
generic (
XFILE : string := "default"
);
port (
clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
output : out std_logic -- wire
);
end component alt_dspbuilder_testbench_salt_GNDBMPYDND;
component alt_dspbuilder_testbench_capture_GNQX2JTRTZ is
generic (
XFILE : string := "default";
DSPBTYPE : string := ""
);
port (
clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
input : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_testbench_capture_GNQX2JTRTZ;
component alt_dspbuilder_testbench_capture_GNHCRI5YMO is
generic (
XFILE : string := "default";
DSPBTYPE : string := ""
);
port (
clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
input : in std_logic_vector(23 downto 0) := (others => 'X') -- wire
);
end component alt_dspbuilder_testbench_capture_GNHCRI5YMO;
signal salt_avalon_mm_slave_address_output_wire : std_logic_vector(1 downto 0); -- salt_Avalon_MM_Slave_address:output -> dut:Avalon_MM_Slave_address
signal clock_clock_tb_reset : std_logic; -- Clock:tb_aclr -> [salt_Avalon_MM_Slave_address:aclr, salt_Avalon_MM_Slave_write:aclr, salt_Avalon_MM_Slave_writedata:aclr, salt_Avalon_ST_Source_ready:aclr]
signal clock_clock_tb_clk : std_logic; -- Clock:clock_out -> [capture_Avalon_ST_Source_data:clock, capture_Avalon_ST_Source_endofpacket:clock, capture_Avalon_ST_Source_startofpacket:clock, capture_Avalon_ST_Source_valid:clock, dut:Clock, salt_Avalon_MM_Slave_address:clock, salt_Avalon_MM_Slave_write:clock, salt_Avalon_MM_Slave_writedata:clock, salt_Avalon_ST_Source_ready:clock]
signal salt_avalon_mm_slave_writedata_output_wire : std_logic_vector(31 downto 0); -- salt_Avalon_MM_Slave_writedata:output -> dut:Avalon_MM_Slave_writedata
signal salt_avalon_mm_slave_write_output_wire : std_logic; -- salt_Avalon_MM_Slave_write:output -> dut:Avalon_MM_Slave_write
signal salt_avalon_st_source_ready_output_wire : std_logic; -- salt_Avalon_ST_Source_ready:output -> dut:Avalon_ST_Source_ready
signal dut_avalon_st_source_valid_wire : std_logic; -- dut:Avalon_ST_Source_valid -> capture_Avalon_ST_Source_valid:input
signal clock_clock_reg_reset_reset : std_logic; -- Clock:reg_aclr_out -> [capture_Avalon_ST_Source_data:aclr, capture_Avalon_ST_Source_endofpacket:aclr, capture_Avalon_ST_Source_startofpacket:aclr, capture_Avalon_ST_Source_valid:aclr]
signal dut_avalon_st_source_endofpacket_wire : std_logic; -- dut:Avalon_ST_Source_endofpacket -> capture_Avalon_ST_Source_endofpacket:input
signal dut_avalon_st_source_startofpacket_wire : std_logic; -- dut:Avalon_ST_Source_startofpacket -> capture_Avalon_ST_Source_startofpacket:input
signal dut_avalon_st_source_data_wire : std_logic_vector(23 downto 0); -- dut:Avalon_ST_Source_data -> capture_Avalon_ST_Source_data:input
signal clock_clock_output_reset : std_logic; -- Clock:aclr_out -> clock_clock_output_reset:in
signal clock_clock_output_reset_ports_inv : std_logic; -- clock_clock_output_reset:inv -> dut:aclr
begin
dut : component Test_Pattern_Generator_GN
port map (
Clock => clock_clock_tb_clk, -- Clock.clk
aclr => clock_clock_output_reset_ports_inv, -- .reset_n
Avalon_MM_Slave_address => salt_avalon_mm_slave_address_output_wire, -- Avalon_MM_Slave_address.wire
Avalon_ST_Source_valid => dut_avalon_st_source_valid_wire, -- Avalon_ST_Source_valid.wire
Avalon_MM_Slave_writedata => salt_avalon_mm_slave_writedata_output_wire, -- Avalon_MM_Slave_writedata.wire
Avalon_ST_Source_endofpacket => dut_avalon_st_source_endofpacket_wire, -- Avalon_ST_Source_endofpacket.wire
Avalon_ST_Source_startofpacket => dut_avalon_st_source_startofpacket_wire, -- Avalon_ST_Source_startofpacket.wire
Avalon_MM_Slave_write => salt_avalon_mm_slave_write_output_wire, -- Avalon_MM_Slave_write.wire
Avalon_ST_Source_data => dut_avalon_st_source_data_wire, -- Avalon_ST_Source_data.wire
Avalon_ST_Source_ready => salt_avalon_st_source_ready_output_wire -- Avalon_ST_Source_ready.wire
);
clock : component alt_dspbuilder_testbench_clock_GNCGUFKHRR
generic map (
SIMULATION_START_CYCLE => 5,
RESET_LATENCY => 0,
RESET_REGISTER_CASCADE_DEPTH => 0
)
port map (
clock_out => clock_clock_tb_clk, -- clock_tb.clk
tb_aclr => clock_clock_tb_reset, -- .reset
aclr_out => clock_clock_output_reset, -- clock_output.reset
reg_aclr_out => clock_clock_reg_reset_reset -- clock_reg_reset.reset
);
salt_avalon_mm_slave_address : component alt_dspbuilder_testbench_salt_GN6DKNTQ5M
generic map (
XFILE => "Test%5FPattern%5FGenerator_Avalon-MM+Slave_address.salt"
)
port map (
clock => clock_clock_tb_clk, -- clock_aclr.clk
aclr => clock_clock_tb_reset, -- .reset
output => salt_avalon_mm_slave_address_output_wire -- output.wire
);
salt_avalon_mm_slave_writedata : component alt_dspbuilder_testbench_salt_GN7Z4SHGOK
generic map (
XFILE => "Test%5FPattern%5FGenerator_Avalon-MM+Slave_writedata.salt"
)
port map (
clock => clock_clock_tb_clk, -- clock_aclr.clk
aclr => clock_clock_tb_reset, -- .reset
output => salt_avalon_mm_slave_writedata_output_wire -- output.wire
);
salt_avalon_mm_slave_write : component alt_dspbuilder_testbench_salt_GNDBMPYDND
generic map (
XFILE => "Test%5FPattern%5FGenerator_Avalon-MM+Slave_write.salt"
)
port map (
clock => clock_clock_tb_clk, -- clock_aclr.clk
aclr => clock_clock_tb_reset, -- .reset
output => salt_avalon_mm_slave_write_output_wire -- output.wire
);
salt_avalon_st_source_ready : component alt_dspbuilder_testbench_salt_GNDBMPYDND
generic map (
XFILE => "Test%5FPattern%5FGenerator_Avalon%5FST%5FSource_ready.salt"
)
port map (
clock => clock_clock_tb_clk, -- clock_aclr.clk
aclr => clock_clock_tb_reset, -- .reset
output => salt_avalon_st_source_ready_output_wire -- output.wire
);
capture_avalon_st_source_valid : component alt_dspbuilder_testbench_capture_GNQX2JTRTZ
generic map (
XFILE => "Test%5FPattern%5FGenerator_Avalon%5FST%5FSource_valid.capture.msim",
DSPBTYPE => "BIT [1, 0]"
)
port map (
clock => clock_clock_tb_clk, -- clock_aclr.clk
aclr => clock_clock_reg_reset_reset, -- .reset
input => dut_avalon_st_source_valid_wire -- input.wire
);
capture_avalon_st_source_endofpacket : component alt_dspbuilder_testbench_capture_GNQX2JTRTZ
generic map (
XFILE => "Test%5FPattern%5FGenerator_Avalon%5FST%5FSource_endofpacket.capture.msim",
DSPBTYPE => "BIT [1, 0]"
)
port map (
clock => clock_clock_tb_clk, -- clock_aclr.clk
aclr => clock_clock_reg_reset_reset, -- .reset
input => dut_avalon_st_source_endofpacket_wire -- input.wire
);
capture_avalon_st_source_startofpacket : component alt_dspbuilder_testbench_capture_GNQX2JTRTZ
generic map (
XFILE => "Test%5FPattern%5FGenerator_Avalon%5FST%5FSource_startofpacket.capture.msim",
DSPBTYPE => "BIT [1, 0]"
)
port map (
clock => clock_clock_tb_clk, -- clock_aclr.clk
aclr => clock_clock_reg_reset_reset, -- .reset
input => dut_avalon_st_source_startofpacket_wire -- input.wire
);
capture_avalon_st_source_data : component alt_dspbuilder_testbench_capture_GNHCRI5YMO
generic map (
XFILE => "Test%5FPattern%5FGenerator_Avalon%5FST%5FSource_data.capture.msim",
DSPBTYPE => "UINT [24, 0]"
)
port map (
clock => clock_clock_tb_clk, -- clock_aclr.clk
aclr => clock_clock_reg_reset_reset, -- .reset
input => dut_avalon_st_source_data_wire -- input.wire
);
clock_clock_output_reset_ports_inv <= not clock_clock_output_reset;
end architecture rtl; -- of tb_Test_Pattern_Generator
|
mit
|
Given-Jiang/Test_Pattern_Generator
|
Test_Pattern_Generator_dspbuilder/db/alt_dspbuilder_testbench_salt.vhd
|
10
|
667
|
-- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instantiate this entity.
--altera translate_off
entity alt_dspbuilder_testbench_salt is
end entity alt_dspbuilder_testbench_salt;
architecture rtl of alt_dspbuilder_testbench_salt is
begin
assert false report "This file is not intended for synthesis. Please remove it from your project" severity error;
end architecture rtl;
--altera translate_on
|
mit
|
Given-Jiang/Test_Pattern_Generator
|
tb_Test_Pattern_Generator/db/alt_dspbuilder_logical_bit_op.vhd
|
10
|
667
|
-- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instantiate this entity.
--altera translate_off
entity alt_dspbuilder_logical_bit_op is
end entity alt_dspbuilder_logical_bit_op;
architecture rtl of alt_dspbuilder_logical_bit_op is
begin
assert false report "This file is not intended for synthesis. Please remove it from your project" severity error;
end architecture rtl;
--altera translate_on
|
mit
|
Given-Jiang/Test_Pattern_Generator
|
Test_Pattern_Generator_dspbuilder/hdl/alt_dspbuilder_delay_GNPJ4Y7BVC.vhd
|
4
|
1152
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_delay_GNPJ4Y7BVC is
generic ( ClockPhase : string := "1";
delay : positive := 1;
use_init : natural := 1;
BitPattern : string := "00000000000000000000000000100000";
width : positive := 32);
port(
aclr : in std_logic;
clock : in std_logic;
ena : in std_logic;
input : in std_logic_vector((width)-1 downto 0);
output : out std_logic_vector((width)-1 downto 0);
sclr : in std_logic);
end entity;
architecture rtl of alt_dspbuilder_delay_GNPJ4Y7BVC is
Begin
-- Delay Element, with reset value
DelayWithInit : alt_dspbuilder_SInitDelay generic map (
LPM_WIDTH => 32,
LPM_DELAY => 1,
SequenceLength => 1,
SequenceValue => "1",
ResetValue => "00000000000000000000000000100000")
port map (
dataa => input,
clock => clock,
ena => ena,
sclr => sclr,
aclr => aclr,
user_aclr => '0',
result => output);
end architecture;
|
mit
|
Given-Jiang/Test_Pattern_Generator
|
tb_Test_Pattern_Generator/db/alt_dspbuilder_decoder.vhd
|
2
|
2462
|
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_decoder is
generic (
DECODE : string := "00000000";
PIPELINE : natural := 0;
WIDTH : natural := 8
);
port (
dec : out std_logic;
clock : in std_logic := '0';
sclr : in std_logic := '0';
data : in std_logic_vector(width-1 downto 0) := (others=>'0');
aclr : in std_logic := '0';
ena : in std_logic := '0'
);
end entity alt_dspbuilder_decoder;
architecture rtl of alt_dspbuilder_decoder is
component alt_dspbuilder_decoder_GNEQGKKPXW is
generic (
DECODE : string := "10";
PIPELINE : natural := 1;
WIDTH : natural := 2
);
port (
aclr : in std_logic := '0';
clock : in std_logic := '0';
data : in std_logic_vector(2-1 downto 0) := (others=>'0');
dec : out std_logic;
ena : in std_logic := '0';
sclr : in std_logic := '0'
);
end component alt_dspbuilder_decoder_GNEQGKKPXW;
component alt_dspbuilder_decoder_GNM4LOIHXZ is
generic (
DECODE : string := "01";
PIPELINE : natural := 1;
WIDTH : natural := 2
);
port (
aclr : in std_logic := '0';
clock : in std_logic := '0';
data : in std_logic_vector(2-1 downto 0) := (others=>'0');
dec : out std_logic;
ena : in std_logic := '0';
sclr : in std_logic := '0'
);
end component alt_dspbuilder_decoder_GNM4LOIHXZ;
begin
alt_dspbuilder_decoder_GNEQGKKPXW_0: if ((DECODE = "10") and (PIPELINE = 1) and (WIDTH = 2)) generate
inst_alt_dspbuilder_decoder_GNEQGKKPXW_0: alt_dspbuilder_decoder_GNEQGKKPXW
generic map(DECODE => "10", PIPELINE => 1, WIDTH => 2)
port map(aclr => aclr, clock => clock, data => data, dec => dec, ena => ena, sclr => sclr);
end generate;
alt_dspbuilder_decoder_GNM4LOIHXZ_1: if ((DECODE = "01") and (PIPELINE = 1) and (WIDTH = 2)) generate
inst_alt_dspbuilder_decoder_GNM4LOIHXZ_1: alt_dspbuilder_decoder_GNM4LOIHXZ
generic map(DECODE => "01", PIPELINE => 1, WIDTH => 2)
port map(aclr => aclr, clock => clock, data => data, dec => dec, ena => ena, sclr => sclr);
end generate;
assert not (((DECODE = "10") and (PIPELINE = 1) and (WIDTH = 2)) or ((DECODE = "01") and (PIPELINE = 1) and (WIDTH = 2)))
report "Please run generate again" severity error;
end architecture rtl;
|
mit
|
Given-Jiang/Test_Pattern_Generator
|
Test_Pattern_Generator_dspbuilder/hdl/alt_dspbuilder_divider_GNKAPZN5MO.vhd
|
4
|
1140
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_divider_GNKAPZN5MO is
generic ( Signed : natural := 0;
width : natural := 24;
pipeline : natural := 0);
port(
aclr : in std_logic;
clock : in std_logic;
denom : in std_logic_vector((width)-1 downto 0);
ena : in std_logic;
numer : in std_logic_vector((width)-1 downto 0);
quotient : out std_logic_vector((width)-1 downto 0);
remain : out std_logic_vector((width)-1 downto 0);
user_aclr : in std_logic);
end entity;
architecture rtl of alt_dspbuilder_divider_GNKAPZN5MO is
Begin
-- Divide Operator - Simulink Block "alt_dspbuilder_divider"
Divideri : alt_dspbuilder_dividerAltr generic map (
widthin => 24,
isunsigned => 1,
pipeline => 0)
port map (
numer => numer,
denom => denom,
quotient => quotient,
remain => remain,
clock => clock,
clken => ena,
aclr => aclr,
user_aclr => user_aclr
);
end architecture;
|
mit
|
Given-Jiang/Test_Pattern_Generator
|
tb_Test_Pattern_Generator/db/alt_dspbuilder_port_GNEHYJMBQS.vhd
|
4
|
489
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_port_GNEHYJMBQS is
port(
input : in std_logic_vector(24 downto 0);
output : out std_logic_vector(24 downto 0));
end entity;
architecture rtl of alt_dspbuilder_port_GNEHYJMBQS is
Begin
-- Straight Bypass block
output <= input;
end architecture;
|
mit
|
Given-Jiang/Test_Pattern_Generator
|
tb_Test_Pattern_Generator/hdl/alt_dspbuilder_port_GNEHYJMBQS.vhd
|
4
|
489
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_port_GNEHYJMBQS is
port(
input : in std_logic_vector(24 downto 0);
output : out std_logic_vector(24 downto 0));
end entity;
architecture rtl of alt_dspbuilder_port_GNEHYJMBQS is
Begin
-- Straight Bypass block
output <= input;
end architecture;
|
mit
|
Given-Jiang/Test_Pattern_Generator
|
tb_Test_Pattern_Generator/db/alt_dspbuilder_MultAdd.vhd
|
12
|
23128
|
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library ieee ;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_signed.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_MultAdd is
generic (
width_a : positive :=8;
width_r : positive :=17;
direction : AddSubOperator := AddAdd;
nMult : positive := 2;
intended_device_family : string :="Stratix";
use_dedicated_circuitry : natural :=0;
representation : string :="SIGNED";
regstruct : registerstructure :=NoRegister
);
port (
dat1aa : in std_logic_vector (width_a-1 downto 0);
dat1ab : in std_logic_vector (width_a-1 downto 0);
dat2aa : in std_logic_vector (width_a-1 downto 0);
dat2ab : in std_logic_vector (width_a-1 downto 0);
dat3aa : in std_logic_vector (width_a-1 downto 0);
dat3ab : in std_logic_vector (width_a-1 downto 0);
dat4aa : in std_logic_vector (width_a-1 downto 0);
dat4ab : in std_logic_vector (width_a-1 downto 0);
clock : in std_logic ;
ena : in std_logic ;
part_sclr : in std_logic ;
aclr : in std_logic ;
user_aclr : in std_logic ;
result : out std_logic_vector (width_r-1 downto 0)
);
end alt_dspbuilder_MultAdd;
architecture MultAdd_synth of alt_dspbuilder_MultAdd is
function RegStatus(r:registerstructure) return std_logic_vector is
variable res : std_logic_vector(2 downto 0) :=(others=>'0');
begin
if ((r=InputsMultiplierandAdder)or(r=InputsOnly)or(r=InputsandMultiplier)or(r=InputsandAdder)) then
res(0) := '1';
else
res(0) := '0';
end if;
if ((r=InputsMultiplierandAdder) or (r=MultiplierOnly) or (r=InputsandMultiplier) or (r=MultiplierandAdder)) then
res(1) := '1';
else
res(1) := '0';
end if;
if (r=InputsMultiplierandAdder) or
(r=AdderOnly) or
(r=InputsandAdder) or
(r=MultiplierandAdder) then
res(2) := '1';
else
res(2) := '0';
end if;
return res;
end ;
constant regstat : std_logic_vector(2 downto 0) := RegStatus(regstruct);
signal regdat1aa : std_logic_vector (width_a-1 downto 0);
signal regdat1ab : std_logic_vector (width_a-1 downto 0);
signal regdat2aa : std_logic_vector (width_a-1 downto 0);
signal regdat2ab : std_logic_vector (width_a-1 downto 0);
signal regdat3aa : std_logic_vector (width_a-1 downto 0);
signal regdat3ab : std_logic_vector (width_a-1 downto 0);
signal regdat4aa : std_logic_vector (width_a-1 downto 0);
signal regdat4ab : std_logic_vector (width_a-1 downto 0);
signal A1xB : std_logic_vector (2*width_a-1 downto 0);
signal A2xB : std_logic_vector (2*width_a-1 downto 0);
signal A3xB : std_logic_vector (2*width_a-1 downto 0);
signal A4xB : std_logic_vector (2*width_a-1 downto 0);
signal A1xBSExt : std_logic_vector (2*width_a downto 0);
signal A2xBSExt : std_logic_vector (2*width_a downto 0);
signal A3xBSExt : std_logic_vector (2*width_a downto 0);
signal A4xBSExt : std_logic_vector (2*width_a downto 0);
signal FirstAdd : std_logic_vector (2*width_a downto 0);
signal SecondAdd : std_logic_vector (2*width_a downto 0);
signal FirstAddSExt : std_logic_vector (2*width_a+1 downto 0);
signal SecondAddSExt : std_logic_vector (2*width_a+1 downto 0);
signal AllZero : std_logic_vector (2*width_a downto 0);
signal AddAll : std_logic_vector (width_r-1 downto 0);
signal aclr_i : std_logic;
begin
aclr_i <= aclr or user_aclr;
geab: if use_dedicated_circuitry>0 or representation = "UNSIGNED" generate
U0:alt_dspbuilder_MultAddMF generic map (
width_a => width_a ,
width_r => width_r ,
direction => direction ,
nMult => nMult ,
intended_device_family => intended_device_family,
representation => representation ,
regstruct => regstruct )
port map (
clock => clock ,
ena => ena ,
aclr => aclr_i ,
dat1aa => dat1aa ,
dat1ab => dat1ab ,
dat2aa => dat2aa ,
dat2ab => dat2ab ,
dat3aa => dat3aa ,
dat3ab => dat3ab ,
dat4aa => dat4aa ,
dat4ab => dat4ab ,
result => result );
end generate geab;
gneab: if use_dedicated_circuitry=0 and representation /= "UNSIGNED" generate
AllZero <= (others=>'0');
gc:if (regstruct=NoRegister) generate
regdat1aa <= dat1aa;
regdat1ab <= dat1ab;
regdat2aa <= dat2aa;
regdat2ab <= dat2ab;
A1xB <= regdat1aa*regdat1ab;
A1xBSExt(2*width_a-1 downto 0) <= A1xB(2*width_a-1 downto 0);
A1xBSExt(2*width_a) <= A1xBSExt(2*width_a-1);
A2xB <= regdat2aa*regdat2ab;
A2xBSExt(2*width_a-1 downto 0) <= A2xB(2*width_a-1 downto 0);
A2xBSExt(2*width_a) <= A2xBSExt(2*width_a-1);
result <= AddAll;
g2x:if (nMult=2) generate
ga:if (direction=AddAdd) or (direction=AddSub) generate
AddAll <= A1xBSExt+A2xBSExt;
end generate ga;
gs:if (direction=SubSub) or (direction=SubAdd)generate
AddAll <= A1xBSExt-A2xBSExt;
end generate gs;
end generate g2x;
g3x:if (nMult=3) generate
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
A3xB <= regdat3aa*regdat3ab;
A3xBSExt(2*width_a-1 downto 0) <= A3xB(2*width_a-1 downto 0);
A3xBSExt(2*width_a) <= A3xBSExt(2*width_a-1);
ga:if (direction=AddAdd) or (direction=AddSub) generate
FirstAdd <= A1xBSExt+A2xBSExt;
end generate ga;
gs:if (direction=SubSub) or (direction=SubAdd)generate
FirstAdd <= A1xBSExt-A2xBSExt;
end generate gs;
SecondAdd <= AllZero+A3xBSExt;
FirstAddSExt(2*width_a downto 0) <= FirstAdd(2*width_a downto 0);
FirstAddSExt(2*width_a+1) <= FirstAddSExt(2*width_a);
SecondAddSExt(2*width_a downto 0) <= SecondAdd(2*width_a downto 0);
SecondAddSExt(2*width_a+1) <= SecondAddSExt(2*width_a);
AddAll <= FirstAddSExt+SecondAddSExt;
end generate g3x;
g4x:if (nMult=4) generate
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
regdat4aa <= dat4aa;
regdat4ab <= dat4ab;
A3xB <= regdat3aa*regdat3ab;
A3xBSExt(2*width_a-1 downto 0) <= A3xB(2*width_a-1 downto 0);
A3xBSExt(2*width_a) <= A3xBSExt(2*width_a-1);
A4xB <= regdat4aa*regdat4ab;
A4xBSExt(2*width_a-1 downto 0) <= A4xB(2*width_a-1 downto 0);
A4xBSExt(2*width_a) <= A4xBSExt(2*width_a-1);
gaa:if (direction=AddAdd) generate
FirstAdd <= A1xBSExt+A2xBSExt;
SecondAdd <= A3xBSExt+A4xBSExt;
end generate gaa;
gax:if (direction=AddSub) generate
FirstAdd <= A1xBSExt+A2xBSExt;
SecondAdd <= A3xBSExt-A4xBSExt;
end generate gax;
gss:if (direction=SubSub) generate
FirstAdd <= A1xBSExt-A2xBSExt;
SecondAdd <= A3xBSExt-A4xBSExt;
end generate gss;
gsa:if (direction=SubAdd) generate
FirstAdd <= A1xBSExt-A2xBSExt;
SecondAdd <= A3xBSExt+A4xBSExt;
end generate gsa;
FirstAddSExt(2*width_a downto 0) <= FirstAdd(2*width_a downto 0);
FirstAddSExt(2*width_a+1) <= FirstAddSExt(2*width_a);
SecondAddSExt(2*width_a downto 0) <= SecondAdd(2*width_a downto 0);
SecondAddSExt(2*width_a+1) <= SecondAddSExt(2*width_a);
AddAll <= FirstAddSExt+SecondAddSExt;
end generate g4x;
end generate gc;
gcr:if (regstruct/=NoRegister)and(regstruct/=InputsMultiplierandAdder) generate
result <= AddAll;
gci:if regstat(0)='0' generate
regdat1aa <= dat1aa;
regdat1ab <= dat1ab;
regdat2aa <= dat2aa;
regdat2ab <= dat2ab;
end generate gci;
gcr:if regstat(0)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
regdat1aa <= (others=>'0');
regdat1ab <= (others=>'0');
regdat2aa <= (others=>'0');
regdat2ab <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
regdat1aa <= (others=>'0');
regdat1ab <= (others=>'0');
regdat2aa <= (others=>'0');
regdat2ab <= (others=>'0');
elsif (ena='1') then
regdat1aa <= dat1aa;
regdat1ab <= dat1ab;
regdat2aa <= dat2aa;
regdat2ab <= dat2ab;
end if ;
end if ;
end process ;
end generate gcr;
gmc: if regstat(1)='0' generate
A1xB <= regdat1aa*regdat1ab;
A2xB <= regdat2aa*regdat2ab;
end generate gmc;
gmr: if regstat(1)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
A1xB <= (others=>'0');
A2xB <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
A1xB <= (others=>'0');
A2xB <= (others=>'0');
elsif (ena='1') then
A1xB <= regdat1aa*regdat1ab;
A2xB <= regdat2aa*regdat2ab;
end if ;
end if ;
end process ;
end generate gmr;
A1xBSExt(2*width_a-1 downto 0) <= A1xB(2*width_a-1 downto 0);
A1xBSExt(2*width_a) <= A1xBSExt(2*width_a-1);
A2xBSExt(2*width_a-1 downto 0) <= A2xB(2*width_a-1 downto 0);
A2xBSExt(2*width_a) <= A2xBSExt(2*width_a-1);
g2x:if (nMult=2) generate
ga:if (direction=AddAdd) or (direction=AddSub) generate
gac:if regstat(2)='0' generate
AddAll <= A1xBSExt+A2xBSExt;
end generate gac;
gar:if regstat(2)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= A1xBSExt+A2xBSExt;
end if ;
end if ;
end process ;
end generate gar;
end generate ga;
gs:if (direction=SubSub) or (direction=SubAdd)generate
gac:if regstat(2)='0' generate
AddAll <= A1xBSExt-A2xBSExt;
end generate gac;
gar:if regstat(2)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= A1xBSExt-A2xBSExt;
end if ;
end if ;
end process ;
end generate gar;
end generate gs;
end generate g2x;
g3x:if (nMult=3) generate
gci:if regstat(0)='0' generate
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
end generate gci;
gri:if regstat(0)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
elsif (ena='1') then
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
end if ;
end if ;
end process ;
end generate gri;
gmc: if regstat(1)='0' generate
A3xB <= regdat3aa*regdat3ab;
end generate gmc;
gmr: if regstat(1)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
A3xB <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
A3xB <= (others=>'0');
elsif (ena='1') then
A3xB <= regdat3aa*regdat3ab;
end if ;
end if ;
end process ;
end generate gmr;
A3xBSExt(2*width_a-1 downto 0) <= A3xB(2*width_a-1 downto 0);
A3xBSExt(2*width_a) <= A3xBSExt(2*width_a-1);
SecondAdd <= AllZero+A3xBSExt;
FirstAddSExt(2*width_a downto 0) <= FirstAdd(2*width_a downto 0);
FirstAddSExt(2*width_a+1) <= FirstAddSExt(2*width_a);
SecondAddSExt(2*width_a downto 0) <= SecondAdd(2*width_a downto 0);
SecondAddSExt(2*width_a+1) <= SecondAddSExt(2*width_a);
ga:if (direction=AddAdd) or (direction=AddSub) generate
FirstAdd <= A1xBSExt+A2xBSExt;
end generate ga;
gs:if (direction=SubSub) or (direction=SubAdd)generate
FirstAdd <= A1xBSExt-A2xBSExt;
end generate gs;
gac:if regstat(2)='0' generate
AddAll <= FirstAddSExt+SecondAddSExt;
end generate gac;
gar:if regstat(2)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= FirstAddSExt+SecondAddSExt;
end if ;
end if ;
end process ;
end generate gar;
end generate g3x;
g4x:if (nMult=4) generate
gci:if regstat(0)='0' generate
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
regdat4aa <= dat4aa;
regdat4ab <= dat4ab;
end generate gci;
gri:if regstat(0)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
regdat4aa <= (others=>'0');
regdat4ab <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
regdat4aa <= (others=>'0');
regdat4ab <= (others=>'0');
elsif (ena='1') then
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
regdat4aa <= dat4aa;
regdat4ab <= dat4ab;
end if ;
end if ;
end process ;
end generate gri;
gmc: if regstat(1)='0' generate
A3xB <= regdat3aa*regdat3ab;
A4xB <= regdat4aa*regdat4ab;
end generate gmc;
gmr: if regstat(1)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
A3xB <= (others=>'0');
A4xB <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
A3xB <= (others=>'0');
A4xB <= (others=>'0');
elsif (ena='1') then
A3xB <= regdat3aa*regdat3ab;
A4xB <= regdat4aa*regdat4ab;
end if ;
end if ;
end process ;
end generate gmr;
A3xBSExt(2*width_a-1 downto 0) <= A3xB(2*width_a-1 downto 0);
A3xBSExt(2*width_a) <= A3xBSExt(2*width_a-1);
A4xBSExt(2*width_a-1 downto 0) <= A4xB(2*width_a-1 downto 0);
A4xBSExt(2*width_a) <= A4xBSExt(2*width_a-1);
gaa:if (direction=AddAdd) generate
FirstAdd <= A1xBSExt+A2xBSExt;
SecondAdd <= A3xBSExt+A4xBSExt;
end generate gaa;
gax:if (direction=AddSub) generate
FirstAdd <= A1xBSExt+A2xBSExt;
SecondAdd <= A3xBSExt-A4xBSExt;
end generate gax;
gss:if (direction=SubSub) generate
FirstAdd <= A1xBSExt-A2xBSExt;
SecondAdd <= A3xBSExt-A4xBSExt;
end generate gss;
gsa:if (direction=SubAdd) generate
FirstAdd <= A1xBSExt-A2xBSExt;
SecondAdd <= A3xBSExt+A4xBSExt;
end generate gsa;
FirstAddSExt(2*width_a downto 0) <= FirstAdd(2*width_a downto 0);
FirstAddSExt(2*width_a+1) <= FirstAddSExt(2*width_a);
SecondAddSExt(2*width_a downto 0) <= SecondAdd(2*width_a downto 0);
SecondAddSExt(2*width_a+1) <= SecondAddSExt(2*width_a);
gac:if regstat(2)='0' generate
AddAll <= FirstAddSExt+SecondAddSExt;
end generate gac;
gar:if regstat(2)='1' generate
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= FirstAddSExt+SecondAddSExt;
end if ;
end if ;
end process ;
end generate gar;
end generate g4x;
end generate gcr;
gr:if (regstruct=InputsMultiplierandAdder) generate
result <= AddAll;
process(clock,aclr_i)
begin
if aclr_i='1' then
regdat1aa <= (others=>'0');
regdat1ab <= (others=>'0');
regdat2aa <= (others=>'0');
regdat2ab <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
regdat1aa <= (others=>'0');
regdat1ab <= (others=>'0');
regdat2aa <= (others=>'0');
regdat2ab <= (others=>'0');
elsif (ena='1') then
regdat1aa <= dat1aa;
regdat1ab <= dat1ab;
regdat2aa <= dat2aa;
regdat2ab <= dat2ab;
end if ;
end if ;
end process ;
process(clock,aclr_i)
begin
if aclr_i='1' then
A1xB <= (others=>'0');
A2xB <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
A1xB <= (others=>'0');
A2xB <= (others=>'0');
elsif (ena='1') then
A1xB <= regdat1aa*regdat1ab;
A2xB <= regdat2aa*regdat2ab;
end if ;
end if ;
end process ;
A1xBSExt(2*width_a-1 downto 0) <= A1xB(2*width_a-1 downto 0);
A1xBSExt(2*width_a) <= A1xBSExt(2*width_a-1);
A2xBSExt(2*width_a-1 downto 0) <= A2xB(2*width_a-1 downto 0);
A2xBSExt(2*width_a) <= A2xBSExt(2*width_a-1);
g2x:if (nMult=2) generate
ga:if (direction=AddAdd) or (direction=AddSub) generate
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= A1xBSExt+A2xBSExt;
end if ;
end if ;
end process ;
end generate ga;
gs:if (direction=SubSub) or (direction=SubAdd)generate
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= A1xBSExt-A2xBSExt;
end if ;
end if ;
end process ;
end generate gs;
end generate g2x;
g3x:if (nMult=3) generate
process(clock,aclr_i)
begin
if aclr_i='1' then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
elsif (ena='1') then
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
end if ;
end if ;
end process ;
process(clock,aclr_i)
begin
if aclr_i='1' then
A3xB <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
A3xB <= (others=>'0');
elsif (ena='1') then
A3xB <= regdat3aa*regdat3ab;
end if ;
end if ;
end process ;
A3xBSExt(2*width_a-1 downto 0) <= A3xB(2*width_a-1 downto 0);
A3xBSExt(2*width_a) <= A3xBSExt(2*width_a-1);
SecondAdd <= AllZero+A3xBSExt;
FirstAddSExt(2*width_a downto 0) <= FirstAdd(2*width_a downto 0);
FirstAddSExt(2*width_a+1) <= FirstAddSExt(2*width_a);
SecondAddSExt(2*width_a downto 0) <= SecondAdd(2*width_a downto 0);
SecondAddSExt(2*width_a+1) <= SecondAddSExt(2*width_a);
ga:if (direction=AddAdd) or (direction=AddSub) generate
FirstAdd <= A1xBSExt+A2xBSExt;
end generate ga;
gs:if (direction=SubSub) or (direction=SubAdd)generate
FirstAdd <= A1xBSExt-A2xBSExt;
end generate gs;
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= FirstAddSExt+SecondAddSExt;
end if ;
end if ;
end process ;
end generate g3x;
g4x:if (nMult=4) generate
process(clock,aclr_i)
begin
if aclr_i='1' then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
regdat4aa <= (others=>'0');
regdat4ab <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
regdat3aa <= (others=>'0');
regdat3ab <= (others=>'0');
regdat4aa <= (others=>'0');
regdat4ab <= (others=>'0');
elsif (ena='1') then
regdat3aa <= dat3aa;
regdat3ab <= dat3ab;
regdat4aa <= dat4aa;
regdat4ab <= dat4ab;
end if ;
end if ;
end process ;
process(clock,aclr_i)
begin
if aclr_i='1' then
A3xB <= (others=>'0');
A4xB <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
A3xB <= (others=>'0');
A4xB <= (others=>'0');
elsif (ena='1') then
A3xB <= regdat3aa*regdat3ab;
A4xB <= regdat4aa*regdat4ab;
end if ;
end if ;
end process ;
A3xBSExt(2*width_a-1 downto 0) <= A3xB(2*width_a-1 downto 0);
A3xBSExt(2*width_a) <= A3xBSExt(2*width_a-1);
A4xBSExt(2*width_a-1 downto 0) <= A4xB(2*width_a-1 downto 0);
A4xBSExt(2*width_a) <= A4xBSExt(2*width_a-1);
gaa:if (direction=AddAdd) generate
FirstAdd <= A1xBSExt+A2xBSExt;
SecondAdd <= A3xBSExt+A4xBSExt;
end generate gaa;
gax:if (direction=AddSub) generate
FirstAdd <= A1xBSExt+A2xBSExt;
SecondAdd <= A3xBSExt-A4xBSExt;
end generate gax;
gss:if (direction=SubSub) generate
FirstAdd <= A1xBSExt-A2xBSExt;
SecondAdd <= A3xBSExt-A4xBSExt;
end generate gss;
gsa:if (direction=SubAdd) generate
FirstAdd <= A1xBSExt-A2xBSExt;
SecondAdd <= A3xBSExt+A4xBSExt;
end generate gsa;
FirstAddSExt(2*width_a downto 0) <= FirstAdd(2*width_a downto 0);
FirstAddSExt(2*width_a+1) <= FirstAddSExt(2*width_a);
SecondAddSExt(2*width_a downto 0) <= SecondAdd(2*width_a downto 0);
SecondAddSExt(2*width_a+1) <= SecondAddSExt(2*width_a);
process(clock,aclr_i)
begin
if aclr_i='1' then
AddAll <= (others=>'0');
elsif clock'event and clock='1' then
if (part_sclr='1') then
AddAll <= (others=>'0');
elsif (ena='1') then
AddAll <= FirstAddSExt+SecondAddSExt;
end if ;
end if ;
end process ;
end generate g4x;
end generate gr;
end generate gneab;
end MultAdd_synth;
|
mit
|
dominiklohmann/mikrorechner
|
vhdl/procSim.vhd
|
1
|
2476
|
-- procSim.vhd
--
-- entity procSim -testbench for pipeline processor
-- architecture tb_noIO -
------------------------------------------------------------------------------
library ieee; -- packages:
use ieee.std_logic_1164.all; -- std_logic
use ieee.numeric_std.all; -- (un)signed
use work.sramPkg.all; -- sram
use work.procPkg.all; -- pipeProc
-- entity --------------------------------------------------------------
------------------------------------------------------------------------------
entity procSim is
generic(clkPeriod : time := 20 ns; -- clock period
clkCycles : positive := 200); -- clock cycles
end entity procSim;
-- architecture --------------------------------------------------------------
------------------------------------------------------------------------------
architecture tb_noIO of procSim is
signal clk, nRst : std_logic;
signal const0, const1 : std_logic;
signal dnWE, dnOE : std_logic;
signal iAddr, dAddr : std_logic_vector(31 downto 0);
signal iData, dData : std_logic_vector(31 downto 0);
signal iCtrl, dCtrl : fileIOty;
begin
const0 <= '0';
const1 <= '1';
-- memories ------------------------------------------------------
instMemI: sram generic map ( addrWd => 16,
dataWd => 32,
fileID => "instMem.dat")
port map ( nCS => const0,
nWE => const1,
nOE => const0,
addr => iAddr(7 downto 0),
data => iData,
fileIO => iCtrl);
dataMemI: sram generic map ( addrWd => 16,
dataWd => 32,
fileID => "dataMem.dat")
port map ( nCS => const0,
nWE => dnWE,
nOE => dnOE,
addr => dAddr(7 downto 0),
data => dData,
fileIO => dCtrl);
-- pipe processor ------------------------------------------------------
procIdeaI: procIdea port map ( clk => clk,
nRst => nRst,
iAddr => iAddr,
iData => iData,
dnWE => dnWE,
dnOE => dnOE,
dAddr => dAddr,
dData => dData);
-- stimuli ------------------------------------------------------
stiP: process is
begin
clk <= '0';
nRst <= '0', '1' after 5 ns;
iCtrl <= load, none after 5 ns;
dCtrl <= load, none after 5 ns;
wait for clkPeriod/2;
for n in 1 to clkCycles loop
clk <= '0', '1' after clkPeriod/2;
wait for clkPeriod;
end loop;
wait;
end process stiP;
end architecture tb_noIO;
------------------------------------------------------------------------------
-- procSim.vhd - end
|
mit
|
Given-Jiang/Test_Pattern_Generator
|
tb_Test_Pattern_Generator/hdl/alt_dspbuilder_port_GN6TDLHAW6.vhd
|
13
|
487
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_port_GN6TDLHAW6 is
port(
input : in std_logic_vector(1 downto 0);
output : out std_logic_vector(1 downto 0));
end entity;
architecture rtl of alt_dspbuilder_port_GN6TDLHAW6 is
Begin
-- Straight Bypass block
output <= input;
end architecture;
|
mit
|
Given-Jiang/Test_Pattern_Generator
|
Test_Pattern_Generator_dspbuilder/db/alt_dspbuilder_cast_GNKDE2NVCC.vhd
|
4
|
877
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GNKDE2NVCC is
generic ( round : natural := 0;
saturate : natural := 0);
port(
input : in std_logic_vector(23 downto 0);
output : out std_logic_vector(24 downto 0));
end entity;
architecture rtl of alt_dspbuilder_cast_GNKDE2NVCC is
Begin
-- Output - I/O assignment from Simulink Block "Output"
Outputi : alt_dspbuilder_SBF generic map(
width_inl=> 24 + 1 ,
width_inr=> 0,
width_outl=> 25,
width_outr=> 0,
lpm_signed=> BusIsSigned ,
round=> round,
satur=> saturate)
port map (
xin(23 downto 0) => input,
xin(24) => '0', yout => output
);
end architecture;
|
mit
|
Given-Jiang/Test_Pattern_Generator
|
Test_Pattern_Generator_dspbuilder/db/alt_dspbuilder_constant_GNZEH3JAKA.vhd
|
20
|
592
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_constant_GNZEH3JAKA is
generic ( HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "000000000000000000001111";
width : natural := 24);
port(
output : out std_logic_vector(23 downto 0));
end entity;
architecture rtl of alt_dspbuilder_constant_GNZEH3JAKA is
Begin
-- Constant
output <= "000000000000000000001111";
end architecture;
|
mit
|
Given-Jiang/Test_Pattern_Generator
|
Test_Pattern_Generator_dspbuilder/hdl/alt_dspbuilder_ASAT.vhd
|
20
|
3282
|
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_signed.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_ASAT is
generic (
widthin : natural :=8;
widthout : natural :=4;
lpm_signed : BusArithm :=BusIsSigned
);
port (
xin : in std_logic_vector(widthin-1 downto 0);
yout : out std_logic_vector(widthout-1 downto 0)
);
end alt_dspbuilder_ASAT;
architecture ASAT_SYNTH of alt_dspbuilder_ASAT is
function GetWidthUsgn(win: natural;wout: natural ) return natural is
variable res : natural;
begin
if (win-wout>0) then
res :=win-wout-1;
else
res := 0;
end if;
return res;
end ;
signal msbone : std_logic_vector(widthin-widthout downto 0);
signal msbzero : std_logic_vector(widthin-widthout downto 0);
signal Unsignedmsbzero : std_logic_vector(GetWidthUsgn(widthin,widthout) downto 0);
signal MsbOverFlow : std_logic;
begin
ev:if widthin=widthout generate
yout <= xin;
end generate ev;
sat:if (widthin>widthout) generate
Gs : if lpm_signed=BusIsSigned generate
msbone <= (others=>'1');
msbzero <= (others=>'0');
MsbOverFlow <= '0' when (xin(widthin-1 downto widthout-1) = msbone or xin(widthin-1 downto widthout-1) = msbzero) else '1';
process(xin,MsbOverFlow)
begin
if (MsbOverFlow='0') then
yout(widthout-1 downto 0) <= xin(widthout-1 downto 0);
else
if (xin(widthin-1)='0') then
for i in 0 to widthout-2 loop
yout(i) <= '1'; -- max positif
end loop;
yout(widthout-1) <='0';
else
for i in 0 to widthout-2 loop
yout(i) <= '0'; -- max Negatif
end loop;
yout(widthout-1) <='1';
end if;
end if;
end process;
end generate Gs;
Gus : if lpm_signed=BusIsUnsigned generate
Unsignedmsbzero <= (others=>'0');
MsbOverFlow <= '0' when xin(widthin-1 downto widthout) = Unsignedmsbzero else '1';
process(xin,MsbOverFlow)
begin
if (MsbOverFlow='0') then
yout(widthout-1 downto 0) <= xin(widthout-1 downto 0);
else
yout <=(others=>'1'); -- Max Positive
end if;
end process;
end generate Gus;
end generate sat;
end ASAT_SYNTH;
|
mit
|
Bourgeoisie/ECE368-RISC16
|
368RISC/Modules/Program Counter.vhd
|
1
|
907
|
--Author: Daniel Noyes
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
USE work.UMDRISC_pkg.ALL;
entity pcounter is
generic (regSize : integer:= BITREG_16);
Port (
CLK : in STD_LOGIC;
RST : in STD_LOGIC;
PC_En : in STD_LOGIC;
PROGRAM_COUNTER : out STD_LOGIC_VECTOR (regSize-1 downto 0)
);
end pcounter;
architecture Behavioral of pcounter is
signal PC : std_logic_vector(regSize-1 downto 0):= (others => '0'); --<= (others <= "0"); -- Program Counter
begin
process (CLK, RST)
begin
if (RST = '1') then
PC <= (OTHERS => '0');
elsif CLK = '0' and CLK'event then
if PC_En = '1' then
if PC = B"11111" then --MEM_LIMIT) then --going to need to change this line
PC <= (OTHERS => '0');
else
PC <= PC + 1;
end if;
end if;
end if;
end process;
PROGRAM_COUNTER <= PC;
end Behavioral;
|
mit
|
Given-Jiang/Test_Pattern_Generator
|
tb_Test_Pattern_Generator/hdl/alt_dspbuilder_cast_GNMMXHT3UH.vhd
|
4
|
852
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GNMMXHT3UH is
generic ( round : natural := 0;
saturate : natural := 0);
port(
input : in std_logic_vector(3 downto 0);
output : out std_logic_vector(3 downto 0));
end entity;
architecture rtl of alt_dspbuilder_cast_GNMMXHT3UH is
Begin
-- Output - I/O assignment from Simulink Block "Output"
Outputi : alt_dspbuilder_SBF generic map(
width_inl=> 4 ,
width_inr=> 0,
width_outl=> 4,
width_outr=> 0,
lpm_signed=> BusIsUnsigned ,
round=> round,
satur=> saturate)
port map (
xin(3 downto 0) => input,
yout => output
);
end architecture;
|
mit
|
Given-Jiang/Test_Pattern_Generator
|
tb_Test_Pattern_Generator/hdl/alt_dspbuilder_AltMultConst.vhd
|
12
|
10967
|
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library ieee ;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_signed.all;
library altera;
use altera.alt_dspbuilder_package.all;
library LPM;
use LPM.LPM_COMPONENTS.all;
entity alt_dspbuilder_AltMultConst is
generic (
CA : std_logic_vector :="10";
CB : std_logic_vector :="0010";
CC : std_logic_vector :="10010";
CD : std_logic_vector :="1000001011111111111111";
width_a : positive :=8;
width_r : positive :=17;
regstruct : registerstructure :=NoRegister;
data_signed : boolean := true
);
port (
datain : in std_logic_vector (width_a-1 downto 0);
datbin : in std_logic_vector (width_a-1 downto 0);
datcin : in std_logic_vector (width_a-1 downto 0);
datdin : in std_logic_vector (width_a-1 downto 0);
dataout : out std_logic_vector (width_r-1 downto 0);
clock : in std_logic := '1';
ena : in std_logic := '1';
sclr : in std_logic := '0';
aclr : in std_logic := '0';
user_aclr : in std_logic
);
end alt_dspbuilder_AltMultConst;
architecture AltMultConst_synth of alt_dspbuilder_AltMultConst is
function MaxInt(a:integer ; b:integer) return integer is
variable i : integer;
begin
if (a>b) then
i := a;
else
i := b;
end if ;
return i;
end MaxInt;
constant wadda : integer := MaxInt(datain'high+CA'high+1,datbin'high+CB'high+1)+1;
constant waddb : integer := MaxInt(datcin'high+CC'high+1,datdin'high+CD'high+1)+1;
constant wres : integer := MaxInt(wadda,waddb)+1;
signal C0 : std_logic_vector(CA'high downto 0) := CA(0 to CA'high);
signal C1 : std_logic_vector(CB'high downto 0) := CB(0 to CB'high);
signal C2 : std_logic_vector(CC'high downto 0) := CC(0 to CC'high);
signal C3 : std_logic_vector(CD'high downto 0) := CD(0 to CD'high);
signal dataint : std_logic_vector (datain'high downto 0);
signal datbint : std_logic_vector (datbin'high downto 0);
signal datcint : std_logic_vector (datcin'high downto 0);
signal datdint : std_logic_vector (datdin'high downto 0);
signal AC0 : std_logic_vector(datain'high+CA'high+1 downto 0) ;
signal BC1 : std_logic_vector(datbin'high+CB'high+1 downto 0) ;
signal CC2 : std_logic_vector(datcin'high+CC'high+1 downto 0) ;
signal DC3 : std_logic_vector(datdin'high+CD'high+1 downto 0) ;
signal AC0EXT : std_logic_vector(wadda downto 0) ;
signal BC1EXT : std_logic_vector(wadda downto 0) ;
signal CC2EXT : std_logic_vector(waddb downto 0) ;
signal DC3EXT : std_logic_vector(waddb downto 0) ;
signal adda : std_logic_vector(wadda downto 0) ;
signal addb : std_logic_vector(waddb downto 0) ;
signal addaEXT : std_logic_vector(wres downto 0) ;
signal addbEXT : std_logic_vector(wres downto 0) ;
signal result : std_logic_vector(wres downto 0) ;
signal aclr_i : std_logic;
begin
aclr_i <= aclr or user_aclr;
C0 <= CA(0 to CA'high);
C1 <= CB(0 to CB'high);
C2 <= CC(0 to CC'high);
C3 <= CD(0 to CD'high);
AC0EXT(datain'high+CA'high+1 downto 0) <= AC0(datain'high+CA'high+1 downto 0);
gAC0EXT:for i in datain'high+CA'high+2 to wadda generate
gAC0EXT_s: if (data_signed) generate
AC0EXT(i) <= AC0EXT(datain'high+CA'high+1);
end generate;
gAC0EXT_u: if not(data_signed) generate
AC0EXT(i) <= '0';
end generate;
end generate ;
BC1EXT(datbin'high+CB'high+1 downto 0) <= BC1(datbin'high+CB'high+1 downto 0);
gBC1EXT:for i in datbin'high+CB'high+2 to wadda generate
gBC1EXT_s: if (data_signed) generate
BC1EXT(i) <= BC1EXT(datbin'high+CB'high+1);
end generate;
gBC1EXT_u: if not(data_signed) generate
BC1EXT(i) <= '0';
end generate;
end generate ;
CC2EXT(datcin'high+CC'high+1 downto 0) <= CC2(datcin'high+CC'high+1 downto 0);
gCC2EXT:for i in datcin'high+CC'high+2 to waddb generate
gCC2EXT_s: if (data_signed) generate
CC2EXT(i) <= CC2EXT(datcin'high+CC'high+1);
end generate;
gCC2EXT_u: if not(data_signed) generate
CC2EXT(i) <= '0';
end generate;
end generate ;
DC3EXT(datcin'high+CD'high+1 downto 0) <= DC3(datcin'high+CD'high+1 downto 0);
gDC3EXT:for i in datcin'high+CD'high+2 to waddb generate
gDC3EXT_s: if (data_signed) generate
DC3EXT(i) <= DC3EXT(datcin'high+CD'high+1);
end generate;
gDC3EXT_u: if not(data_signed) generate
DC3EXT(i) <= '0';
end generate;
end generate ;
addaEXT(wadda downto 0) <= adda(wadda downto 0);
gaddaEXT:for i in wadda+1 to wres generate
gaddaEXT_s: if (data_signed) generate
addaEXT(i) <= adda(wadda);
end generate;
gaddaEXT_u: if not(data_signed) generate
addaEXT(i) <= '0';
end generate;
end generate ;
addbEXT(waddb downto 0) <= addb(waddb downto 0);
gaddbEXT:for i in waddb+1 to wres generate
gaddbEXT_s: if (data_signed) generate
addbEXT(i) <= addb(waddb);
end generate;
gaddbEXT_u: if not(data_signed) generate
addbEXT(i) <= '0';
end generate;
end generate ;
gr:if (wres<dataout'high) generate
dataout(wres downto 0) <= result(wres downto 0);
grr: for i in wres+1 to dataout'high generate
grr_s: if (data_signed) generate
dataout(i) <= result(wres);
end generate grr_s;
grr_u: if not(data_signed) generate
dataout(i) <= '0';
end generate grr_u;
end generate grr;
end generate gr;
gnr:if not(wres<dataout'high) generate
dataout(dataout'high downto 0) <= result(dataout'high downto 0);
end generate gnr;
gnr1: if ((regstruct=NoRegister)or (regstruct=MultiplierOnly) or (regstruct=AdderOnly) or (regstruct=MultiplierandAdder)) generate
dataint <= datain;
datbint <= datbin;
datcint <= datcin;
datdint <= datdin;
end generate gnr1;
gr1: if ((regstruct=InputsOnly)or (regstruct=InputsandMultiplier) or (regstruct=InputsandAdder) or (regstruct=InputsMultiplierandAdder)) generate
process(clock,aclr_i)
begin
if aclr_i='1' then
dataint <= (others=>'0');
datbint <= (others=>'0');
datcint <= (others=>'0');
datdint <= (others=>'0');
elsif clock'event and clock='1' then
if (sclr='1') then
dataint <= (others=>'0');
datbint <= (others=>'0');
datcint <= (others=>'0');
datdint <= (others=>'0');
elsif (ena='1') then
dataint <= datain;
datbint <= datbin;
datcint <= datcin;
datdint <= datdin;
end if ;
end if ;
end process ;
end generate gr1;
gnr2: if ((regstruct=NoRegister)or (regstruct=InputsOnly) or (regstruct=AdderOnly) or (regstruct=InputsandAdder)) generate
gnr2_s: if (data_signed) generate
AC0 <= C0*dataint;
BC1 <= C1*datbint;
CC2 <= C2*datcint;
DC3 <= C3*datdint;
end generate gnr2_s;
gnr2_u: if not(data_signed) generate
AC0 <= unsigned(C0)*unsigned(dataint);
BC1 <= unsigned(C1)*unsigned(datbint);
CC2 <= unsigned(C2)*unsigned(datcint);
DC3 <= unsigned(C3)*unsigned(datdint);
end generate gnr2_u;
end generate gnr2;
gr2: if ((regstruct=MultiplierOnly)or (regstruct=InputsandMultiplier) or (regstruct=MultiplierandAdder) or (regstruct=InputsMultiplierandAdder)) generate
gr2_s: if (data_signed) generate
process(clock,aclr_i)
begin
if aclr_i='1' then
AC0 <= (others=>'0');
BC1 <= (others=>'0');
CC2 <= (others=>'0');
DC3 <=(others=>'0');
elsif clock'event and clock='1' then
if (sclr='1') then
AC0 <= (others=>'0');
BC1 <= (others=>'0');
CC2 <= (others=>'0');
DC3 <=(others=>'0');
elsif (ena='1') then
AC0 <= C0*dataint;
BC1 <= C1*datbint;
CC2 <= C2*datcint;
DC3 <= C3*datdint;
end if ;
end if ;
end process ;
end generate gr2_s;
gr2_u: if not(data_signed) generate
process(clock,aclr_i)
begin
if aclr_i='1' then
AC0 <= (others=>'0');
BC1 <= (others=>'0');
CC2 <= (others=>'0');
DC3 <=(others=>'0');
elsif clock'event and clock='1' then
if (sclr='1') then
AC0 <= (others=>'0');
BC1 <= (others=>'0');
CC2 <= (others=>'0');
DC3 <=(others=>'0');
elsif (ena='1') then
AC0 <= unsigned(C0)*unsigned(dataint);
BC1 <= unsigned(C1)*unsigned(datbint);
CC2 <= unsigned(C2)*unsigned(datcint);
DC3 <= unsigned(C3)*unsigned(datdint);
end if ;
end if ;
end process ;
end generate gr2_u;
end generate gr2;
adda <= AC0EXT+BC1EXT;
addb <= CC2EXT+DC3EXT;
gnr3: if ((regstruct=NoRegister)or (regstruct=InputsOnly) or (regstruct=MultiplierOnly) or (regstruct=InputsandMultiplier)) generate
result <= addaEXT+addbEXT;
end generate gnr3;
gr3: if ((regstruct=AdderOnly)or (regstruct=InputsandAdder) or (regstruct=MultiplierandAdder) or (regstruct=InputsMultiplierandAdder)) generate
process(clock,aclr_i)
begin
if aclr_i='1' then
result <= (others=>'0');
elsif clock'event and clock='1' then
if (sclr='1') then
result <= (others=>'0');
elsif (ena='1') then
result <= addaEXT+addbEXT;
end if ;
end if ;
end process ;
end generate gr3;
end AltMultConst_synth;
|
mit
|
Given-Jiang/Test_Pattern_Generator
|
Test_Pattern_Generator_dspbuilder/db/alt_dspbuilder_bus_concat.vhd
|
2
|
4553
|
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_bus_concat is
generic (
WIDTHB : natural := 8;
WIDTHA : natural := 8
);
port (
b : in std_logic_vector(widthB-1 downto 0) := (others=>'0');
clock : in std_logic := '0';
a : in std_logic_vector(widthA-1 downto 0) := (others=>'0');
aclr : in std_logic := '0';
output : out std_logic_vector(widthA+widthB-1 downto 0)
);
end entity alt_dspbuilder_bus_concat;
architecture rtl of alt_dspbuilder_bus_concat is
component alt_dspbuilder_bus_concat_GNAUBM7IRL is
generic (
WIDTHB : natural := 4;
WIDTHA : natural := 4
);
port (
a : in std_logic_vector(4-1 downto 0) := (others=>'0');
aclr : in std_logic := '0';
b : in std_logic_vector(4-1 downto 0) := (others=>'0');
clock : in std_logic := '0';
output : out std_logic_vector(8-1 downto 0)
);
end component alt_dspbuilder_bus_concat_GNAUBM7IRL;
component alt_dspbuilder_bus_concat_GNWZPLIVXS is
generic (
WIDTHB : natural := 8;
WIDTHA : natural := 16
);
port (
a : in std_logic_vector(16-1 downto 0) := (others=>'0');
aclr : in std_logic := '0';
b : in std_logic_vector(8-1 downto 0) := (others=>'0');
clock : in std_logic := '0';
output : out std_logic_vector(24-1 downto 0)
);
end component alt_dspbuilder_bus_concat_GNWZPLIVXS;
component alt_dspbuilder_bus_concat_GNIIOZRPJD is
generic (
WIDTHB : natural := 8;
WIDTHA : natural := 8
);
port (
a : in std_logic_vector(8-1 downto 0) := (others=>'0');
aclr : in std_logic := '0';
b : in std_logic_vector(8-1 downto 0) := (others=>'0');
clock : in std_logic := '0';
output : out std_logic_vector(16-1 downto 0)
);
end component alt_dspbuilder_bus_concat_GNIIOZRPJD;
component alt_dspbuilder_bus_concat_GN55ETJ4VI is
generic (
WIDTHB : natural := 16;
WIDTHA : natural := 8
);
port (
a : in std_logic_vector(8-1 downto 0) := (others=>'0');
aclr : in std_logic := '0';
b : in std_logic_vector(16-1 downto 0) := (others=>'0');
clock : in std_logic := '0';
output : out std_logic_vector(24-1 downto 0)
);
end component alt_dspbuilder_bus_concat_GN55ETJ4VI;
component alt_dspbuilder_bus_concat_GN6E6AAQPZ is
generic (
WIDTHB : natural := 1;
WIDTHA : natural := 1
);
port (
a : in std_logic_vector(1-1 downto 0) := (others=>'0');
aclr : in std_logic := '0';
b : in std_logic_vector(1-1 downto 0) := (others=>'0');
clock : in std_logic := '0';
output : out std_logic_vector(2-1 downto 0)
);
end component alt_dspbuilder_bus_concat_GN6E6AAQPZ;
begin
alt_dspbuilder_bus_concat_GNAUBM7IRL_0: if ((WIDTHB = 4) and (WIDTHA = 4)) generate
inst_alt_dspbuilder_bus_concat_GNAUBM7IRL_0: alt_dspbuilder_bus_concat_GNAUBM7IRL
generic map(WIDTHB => 4, WIDTHA => 4)
port map(a => a, aclr => aclr, b => b, clock => clock, output => output);
end generate;
alt_dspbuilder_bus_concat_GNWZPLIVXS_1: if ((WIDTHB = 8) and (WIDTHA = 16)) generate
inst_alt_dspbuilder_bus_concat_GNWZPLIVXS_1: alt_dspbuilder_bus_concat_GNWZPLIVXS
generic map(WIDTHB => 8, WIDTHA => 16)
port map(a => a, aclr => aclr, b => b, clock => clock, output => output);
end generate;
alt_dspbuilder_bus_concat_GNIIOZRPJD_2: if ((WIDTHB = 8) and (WIDTHA = 8)) generate
inst_alt_dspbuilder_bus_concat_GNIIOZRPJD_2: alt_dspbuilder_bus_concat_GNIIOZRPJD
generic map(WIDTHB => 8, WIDTHA => 8)
port map(a => a, aclr => aclr, b => b, clock => clock, output => output);
end generate;
alt_dspbuilder_bus_concat_GN55ETJ4VI_3: if ((WIDTHB = 16) and (WIDTHA = 8)) generate
inst_alt_dspbuilder_bus_concat_GN55ETJ4VI_3: alt_dspbuilder_bus_concat_GN55ETJ4VI
generic map(WIDTHB => 16, WIDTHA => 8)
port map(a => a, aclr => aclr, b => b, clock => clock, output => output);
end generate;
alt_dspbuilder_bus_concat_GN6E6AAQPZ_4: if ((WIDTHB = 1) and (WIDTHA = 1)) generate
inst_alt_dspbuilder_bus_concat_GN6E6AAQPZ_4: alt_dspbuilder_bus_concat_GN6E6AAQPZ
generic map(WIDTHB => 1, WIDTHA => 1)
port map(a => a, aclr => aclr, b => b, clock => clock, output => output);
end generate;
assert not (((WIDTHB = 4) and (WIDTHA = 4)) or ((WIDTHB = 8) and (WIDTHA = 16)) or ((WIDTHB = 8) and (WIDTHA = 8)) or ((WIDTHB = 16) and (WIDTHA = 8)) or ((WIDTHB = 1) and (WIDTHA = 1)))
report "Please run generate again" severity error;
end architecture rtl;
|
mit
|
Given-Jiang/Test_Pattern_Generator
|
Test_Pattern_Generator_dspbuilder/hdl/StateMachineEditor_import.vhd
|
2
|
1225
|
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity StateMachineEditor_import is
port (
clock : in std_logic;
counter : in std_logic_vector(24-1 downto 0);
data_end : in std_logic;
ready : in std_logic;
reset : in std_logic;
state : out std_logic_vector(3-1 downto 0)
);
end entity StateMachineEditor_import;
architecture rtl of StateMachineEditor_import is
component StateMachineEditor_import_GN is
port (
clock : in std_logic;
counter : in std_logic_vector(24-1 downto 0);
data_end : in std_logic;
ready : in std_logic;
reset : in std_logic;
state : out std_logic_vector(3-1 downto 0)
);
end component StateMachineEditor_import_GN;
begin
StateMachineEditor_import_GN_0: if true generate
inst_StateMachineEditor_import_GN_0: StateMachineEditor_import_GN
port map(clock => clock, counter => counter, data_end => data_end, ready => ready, reset => reset, state => state);
end generate;
end architecture rtl;
|
mit
|
Given-Jiang/Test_Pattern_Generator
|
Test_Pattern_Generator_dspbuilder/db/alt_dspbuilder_logical_bit_op_GNUQ2R64DV.vhd
|
8
|
804
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_logical_bit_op_GNUQ2R64DV is
generic ( LogicalOp : string := "AltOR";
number_inputs : positive := 2);
port(
result : out std_logic;
data0 : in std_logic;
data1 : in std_logic);
end entity;
architecture rtl of alt_dspbuilder_logical_bit_op_GNUQ2R64DV is
Begin
-- Logical Bit Operation - Simulink Block "LogicalBitOperator"
LogicalBitOperatori : alt_dspbuilder_SBitLogical generic map (
LPM_WIDTH => 2,
LOP => AltOR)
port map (
dataa(0) => data0,
dataa(1) => data1,
result => result);
end architecture;
|
mit
|
Given-Jiang/Test_Pattern_Generator
|
tb_Test_Pattern_Generator/db/alt_dspbuilder_logical_bit_op_GNUQ2R64DV.vhd
|
8
|
804
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_logical_bit_op_GNUQ2R64DV is
generic ( LogicalOp : string := "AltOR";
number_inputs : positive := 2);
port(
result : out std_logic;
data0 : in std_logic;
data1 : in std_logic);
end entity;
architecture rtl of alt_dspbuilder_logical_bit_op_GNUQ2R64DV is
Begin
-- Logical Bit Operation - Simulink Block "LogicalBitOperator"
LogicalBitOperatori : alt_dspbuilder_SBitLogical generic map (
LPM_WIDTH => 2,
LOP => AltOR)
port map (
dataa(0) => data0,
dataa(1) => data1,
result => result);
end architecture;
|
mit
|
Given-Jiang/Test_Pattern_Generator
|
tb_Test_Pattern_Generator/db/alt_dspbuilder_testbench_salt_GNDBMPYDND.vhd
|
20
|
1717
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
library std;
use std.textio.all;
entity alt_dspbuilder_testbench_salt_GNDBMPYDND is
generic ( XFILE : string := "default");
port(
clock : in std_logic;
aclr : in std_logic;
output : out std_logic);
end entity;
architecture rtl of alt_dspbuilder_testbench_salt_GNDBMPYDND is
function to_std_logic (B: character) return std_logic is
begin
case B is
when '0' => return '0';
when '1' => return '1';
when OTHERS => return 'X';
end case;
end;
function to_std_logic_vector (B: string) return
std_logic_vector is
variable res: std_logic_vector (B'range);
begin
for i in B'range loop
case B(i) is
when '0' => res(i) := '0';
when '1' => res(i) := '1';
when OTHERS => res(i) := 'X';
end case;
end loop;
return res;
end;
procedure skip_type_header(file f:text) is
use STD.textio.all;
variable in_line : line;
begin
readline(f, in_line);
end procedure skip_type_header ;
file InputFile : text open read_mode is XFILE;
Begin
-- salt generator
skip_type_header(InputFile);
-- Reading Simulink Input
Input_pInput:process(clock, aclr)
variable s : string(1 to 1) ;
variable ptr : line ;
begin
if (aclr = '1') then
output <= '0';
elsif (not endfile(InputFile)) then
if clock'event and clock='0' then
readline(Inputfile, ptr);
read(ptr, s);
output <= to_std_logic(s(1));
end if ;
end if ;
end process ;
end architecture;
|
mit
|
Given-Jiang/Test_Pattern_Generator
|
tb_Test_Pattern_Generator/db/alt_dspbuilder_clock.vhd
|
8
|
2153
|
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_clock is
generic (
RESET : string := "ACTIVE_HIGH";
DOMAIN : string := "default"
);
port (
clock_out : out std_logic;
clock : in std_logic := '0';
aclr_out : out std_logic;
aclr : in std_logic := '0';
aclr_n : in std_logic := '0'
);
end entity alt_dspbuilder_clock;
architecture rtl of alt_dspbuilder_clock is
component alt_dspbuilder_clock_GNF343OQUJ is
generic (
RESET : string := "ACTIVE_LOW";
DOMAIN : string := "default"
);
port (
aclr_n : in std_logic := '0';
aclr_out : out std_logic;
clock : in std_logic := '0';
clock_out : out std_logic
);
end component alt_dspbuilder_clock_GNF343OQUJ;
component alt_dspbuilder_clock_GNQFU4PUDH is
generic (
RESET : string := "ACTIVE_HIGH";
DOMAIN : string := "default"
);
port (
aclr : in std_logic := '0';
aclr_out : out std_logic;
clock : in std_logic := '0';
clock_out : out std_logic
);
end component alt_dspbuilder_clock_GNQFU4PUDH;
begin
alt_dspbuilder_clock_GNF343OQUJ_0: if ((RESET = "ACTIVE_LOW") and (DOMAIN = "default")) generate
inst_alt_dspbuilder_clock_GNF343OQUJ_0: alt_dspbuilder_clock_GNF343OQUJ
generic map(RESET => "ACTIVE_LOW", DOMAIN => "default")
port map(aclr_n => aclr_n, aclr_out => aclr_out, clock => clock, clock_out => clock_out);
end generate;
alt_dspbuilder_clock_GNQFU4PUDH_1: if ((RESET = "ACTIVE_HIGH") and (DOMAIN = "default")) generate
inst_alt_dspbuilder_clock_GNQFU4PUDH_1: alt_dspbuilder_clock_GNQFU4PUDH
generic map(RESET => "ACTIVE_HIGH", DOMAIN => "default")
port map(aclr => aclr, aclr_out => aclr_out, clock => clock, clock_out => clock_out);
end generate;
assert not (((RESET = "ACTIVE_LOW") and (DOMAIN = "default")) or ((RESET = "ACTIVE_HIGH") and (DOMAIN = "default")))
report "Please run generate again" severity error;
end architecture rtl;
|
mit
|
impedimentToProgress/UCI-BlueChip
|
AttackFiles/Attacks/memAttack/lib/gsi/ssram/core_burst.vhd
|
2
|
18591
|
-- Copyright © 2006. GSI Technology
-- Jeff Daugherty
-- [email protected]
-- Version: 3.2
--
-- FileName: core.vhd
-- Unified Sram Core Model for Sync Burst/NBT Sram
--
-- Revision History:
-- 04/23/02 1.0 1) Created VHDL Core.VHD from Verilog Core.V
-- 06/05/02 1.1 1) added new signals, DELAY and tKQX. These signals will
-- be used to setup the Clock to Data Invalid spec.
-- 07/17/02 1.2 1) Fixed the JTAG State machine
-- 2) changed the SR register to shift out the MSB and shift
-- in the LSB
-- 09/25/02 1.3 1) Removed all nPE pin features
-- 2) Max number of Core addresses is now dynamic
-- 3) Max width of Core data is now dynamic
-- 4) Removed alll reference of JTAG from core, seperate JTAG
-- model file: GSI_JTAG
-- 01/10/03 1.4 1) Created a Write_Array process to remove race conditions
-- 2) Created a Read_Array proccess to remove race conditions
-- 02/20/03 1.5 1) Added We and Waddr to Read_Array sensitivity list.
-- 2) Changed the Read_Array process to look at the last
-- write's byte write setting and determine where to pull the
-- read data from, either coherency(byte write on) or the
-- array(byte write off).
-- 3) Added signal Iscd to fix SCD to the right state for NBT
-- 04/03/03 1.6 1) Added a write clock W_k to trigger the Write_Array function
-- 07/09/03 1.7 1) changed NBT write clock to clock off of we2.
-- 2) Delayed the internal clock by 1ns to control the write
-- 3) changed ce to take into account NBT mode
-- 07/23/03 1.8 1) Changed W_K to ignore the byte writes
-- 08/12/03 1.9 1) updated state machine to include seperate read and write
-- burst states
-- 2) Changed internal bytewrite signal to ignore nW
-- 10/29/03 2.0 1) updated the state machine, changed reference to suspend
-- to deselect.
-- 2) added timing functions to core
-- 03/25/04 2.1 1) Updated state machine. Added deselect and suspend states
-- 2) Fixed other issues with the state machine
-- 04/28/04 2.2 1) Rearranged state that determins Deselect, Burst and Suspend
--
-- 11/01/05 3.0 1) Created BurstRAM only Model
-- 06/21/06 3.1 1) Added Qswitch to control when the IOs turn on or off
-- 2) Delayed the Qxi inteernal data busses instead of the DQx
-- external Data busses.
-- 3) Added CLK_i2 to control the setting of Qswitch
-- 4) All these changes removed Negative time issue for some simulations
--07/18/06 3.2 1) Initialized ce and re to 0 so that Qswitch is not
-- undfined which can cause bus contention on startup.
--
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY VHDL_BURST_CORE IS
GENERIC (
CONSTANT bank_size : integer ;-- *16M /4 bytes in parallel
CONSTANT A_size : integer;
CONSTANT DQ_size : integer);
PORT (
SIGNAL A : IN std_logic_vector(A_size - 1 DOWNTO 0);-- address
SIGNAL DQa : INOUT std_logic_vector(DQ_size DOWNTO 1);-- byte A data
SIGNAL DQb : INOUT std_logic_vector(DQ_size DOWNTO 1);-- byte B data
SIGNAL DQc : INOUT std_logic_vector(DQ_size DOWNTO 1);-- byte C data
SIGNAL DQd : INOUT std_logic_vector(DQ_size DOWNTO 1);-- byte D data
SIGNAL DQe : inout std_logic_vector(DQ_size DOWNTO 1);-- byte E data
SIGNAL DQf : inout std_logic_vector(DQ_size DOWNTO 1);-- byte F data
SIGNAL DQg : inout std_logic_vector(DQ_size DOWNTO 1);-- byte G data
SIGNAL DQh : inout std_logic_vector(DQ_size DOWNTO 1);-- byte H data
SIGNAL nBa : IN std_logic;-- bank A write enable
SIGNAL nBb : IN std_logic;-- bank B write enable
SIGNAL nBc : IN std_logic;-- bank C write enable
SIGNAL nBd : IN std_logic;-- bank D write enable
SIGNAL nBe : IN std_logic;-- bank E write enable
SIGNAL nBf : IN std_logic;-- bank F write enable
SIGNAL nBg : IN std_logic;-- bank G write enable
SIGNAL nBh : IN std_logic;-- bank H write enable
SIGNAL CK : IN std_logic;-- clock
SIGNAL nBW : IN std_logic;-- byte write enable
SIGNAL nGW : IN std_logic;-- Global write enable
SIGNAL nE1 : IN std_logic;-- chip enable 1
SIGNAL E2 : IN std_logic;-- chip enable 2
SIGNAL nE3 : IN std_logic;-- chip enable 3
SIGNAL nG : IN std_logic;-- output enable
SIGNAL nADV : IN std_logic;-- Advance not / load
SIGNAL nADSC : IN std_logic;
SIGNAL nADSP : IN std_logic;
SIGNAL ZZ : IN std_logic;-- power down
SIGNAL nFT : IN std_logic;-- Pipeline / Flow through
SIGNAL nLBO : IN std_logic;-- Linear Burst Order
SIGNAL SCD : IN std_logic;
SIGNAL HighZ : std_logic_vector(DQ_size downto 1);
SIGNAL tKQ : time;
SIGNAL tKQX : time);
END VHDL_BURST_CORE;
LIBRARY GSI;
LIBRARY Std;
ARCHITECTURE GSI_BURST_CORE OF VHDL_BURST_CORE IS
USE GSI.FUNCTIONS.ALL;
USE Std.textio.ALL;
TYPE MEMORY_0 IS ARRAY (0 TO bank_size) OF std_logic_vector(DQ_size - 1 DOWNTO 0);
TYPE MEMORY_1 IS ARRAY (0 TO bank_size) OF std_logic_vector(DQ_size - 1 DOWNTO 0);
TYPE MEMORY_2 IS ARRAY (0 TO bank_size) OF std_logic_vector(DQ_size - 1 DOWNTO 0);
TYPE MEMORY_3 IS ARRAY (0 TO bank_size) OF std_logic_vector(DQ_size - 1 DOWNTO 0);
TYPE MEMORY_4 IS ARRAY (0 TO bank_size) OF std_logic_vector(DQ_size - 1 DOWNTO 0);
TYPE MEMORY_5 IS ARRAY (0 TO bank_size) OF std_logic_vector(DQ_size - 1 DOWNTO 0);
TYPE MEMORY_6 IS ARRAY (0 TO bank_size) OF std_logic_vector(DQ_size - 1 DOWNTO 0);
TYPE MEMORY_7 IS ARRAY (0 TO bank_size) OF std_logic_vector(DQ_size - 1 DOWNTO 0);
-- ******** Define Sram Operation Mode **********************
shared variable bank0 : MEMORY_0 ;
shared variable bank1 : MEMORY_1 ;
shared variable bank2 : MEMORY_2 ;
shared variable bank3 : MEMORY_3 ;
shared variable bank4 : MEMORY_4 ;
shared variable bank5 : MEMORY_5 ;
shared variable bank6 : MEMORY_6 ;
shared variable bank7 : MEMORY_7 ;
-- ---------------------------------------------------------------
-- Gated SRAM Clock
-- ---------------------------------------------------------------
SIGNAL clk_i : std_logic;
SIGNAL clk_i2 : std_logic;
-- ---------------------------------------------------------------
-- Combinatorial Logic
-- ---------------------------------------------------------------
SIGNAL E : std_logic;-- internal chip enable
SIGNAL ADV : std_logic;-- internal address advance
SIGNAL ADS : std_logic;
SIGNAL ADSP : std_logic;
SIGNAL ADSC : std_logic;
SIGNAL W : std_logic;
SIGNAL R : std_logic;
SIGNAL W_k : std_logic;
SIGNAL R_k : std_logic;
SIGNAL BW : std_logic_vector(7 DOWNTO 0);-- internal byte write enable
SIGNAL Qai : std_logic_vector(DQ_size - 1 DOWNTO 0);-- read data
SIGNAL Qbi : std_logic_vector(DQ_size - 1 DOWNTO 0);-- .
SIGNAL Qci : std_logic_vector(DQ_size - 1 DOWNTO 0);-- .
SIGNAL Qdi : std_logic_vector(DQ_size - 1 DOWNTO 0);-- .
SIGNAL Qei : std_logic_vector(DQ_size - 1 DOWNTO 0);-- .
SIGNAL Qfi : std_logic_vector(DQ_size - 1 DOWNTO 0);-- .
SIGNAL Qgi : std_logic_vector(DQ_size - 1 DOWNTO 0);-- .
SIGNAL Qhi : std_logic_vector(DQ_size - 1 DOWNTO 0);-- read data
SIGNAL Dai : std_logic_vector(DQ_size - 1 DOWNTO 0);-- write data
SIGNAL Dbi : std_logic_vector(DQ_size - 1 DOWNTO 0);-- .
SIGNAL Dci : std_logic_vector(DQ_size - 1 DOWNTO 0);-- .
SIGNAL Ddi : std_logic_vector(DQ_size - 1 DOWNTO 0);-- .
SIGNAL Dei : std_logic_vector(DQ_size - 1 DOWNTO 0);-- .
SIGNAL Dfi : std_logic_vector(DQ_size - 1 DOWNTO 0);-- .
SIGNAL Dgi : std_logic_vector(DQ_size - 1 DOWNTO 0);-- .
SIGNAL Dhi : std_logic_vector(DQ_size - 1 DOWNTO 0);-- write data
SIGNAL bwi : std_logic_vector(7 DOWNTO 0);
SIGNAL addr0 : std_logic_vector(A_size - 1 DOWNTO 0);-- saved address
SIGNAL addr1 : std_logic_vector(A_size - 1 DOWNTO 0);-- address buffer 1
SIGNAL baddr : std_logic_vector(A_size - 1 DOWNTO 0);-- burst memory address
SIGNAL waddr : std_logic_vector(A_size - 1 DOWNTO 0);-- write memory address
SIGNAL raddr : std_logic_vector(A_size - 1 DOWNTO 0);-- read memory address
SIGNAL bcnt : std_logic_vector(1 DOWNTO 0) := to_stdlogicvector(0, 2);-- burst counter
SIGNAL we0 : std_logic := '0';
SIGNAL re0 : std_logic := '0';
SIGNAL re1 : std_logic := '0';
SIGNAL re2 : std_logic := '0';
SIGNAL ce0 : std_logic := '0';
SIGNAL ce1 : std_logic := '0';
SIGNAL ce : std_logic := '0';
SIGNAL re : std_logic := '0';
SIGNAL oe : std_logic;
SIGNAL we : std_logic;
SIGNAL Qswitch: std_logic ;
SIGNAL state : string (9 DOWNTO 1) := "IDLE ";
SIGNAL Check_Time : time := 1 ns;
SIGNAL DELAY : time := 1 ns;
SIGNAL GUARD : boolean:= TRUE;
-- TIMING FUNCTIONS
function POSEDGE (SIGNAL s : std_ulogic) return BOOLEAN IS
begin
RETURN (s'EVENT AND ((To_X01(s'LAST_VALUE) = '0') OR (s = '1')));
end;
function NEGEDGE (SIGNAL s : std_ulogic) return BOOLEAN IS
begin
RETURN (s'EVENT AND ((To_X01(s'LAST_VALUE) = '1') OR (s = '0')) );
end;
-- END TIMING FUNCTIONS
PROCEDURE shiftnow (SIGNAL addr1 : INOUT std_logic_vector(A_size - 1 DOWNTO 0);
SIGNAL re2 : INOUT std_logic;
SIGNAL re1 : INOUT std_logic;
SIGNAL ce1 : INOUT std_logic;
SIGNAL Dai : INOUT std_logic_vector(DQ_size - 1 DOWNTO 0);
SIGNAL Dbi : INOUT std_logic_vector(DQ_size - 1 DOWNTO 0);
SIGNAL Dci : INOUT std_logic_vector(DQ_size - 1 DOWNTO 0);
SIGNAL Ddi : INOUT std_logic_vector(DQ_size - 1 DOWNTO 0);
SIGNAL Dei : INOUT std_logic_vector(DQ_size - 1 DOWNTO 0);
SIGNAL Dfi : INOUT std_logic_vector(DQ_size - 1 DOWNTO 0);
SIGNAL Dgi : INOUT std_logic_vector(DQ_size - 1 DOWNTO 0);
SIGNAL Dhi : INOUT std_logic_vector(DQ_size - 1 DOWNTO 0))
IS
BEGIN
addr1 <= baddr;
re2 <= re1;
re1 <= re0;
ce1 <= ce0;
Dai <= DQa;
Dbi <= DQb;
Dci <= DQc;
Ddi <= DQd;
Dei <= DQe;
Dfi <= DQf;
Dgi <= DQg;
Dhi <= DQh;
END;
BEGIN
PROCESS
BEGIN
WAIT UNTIL POSEDGE(CK);
clk_i <= NOT ZZ after 100 ps;
clk_i2 <= NOT ZZ after 200 ps;
WAIT UNTIL NEGEDGE(CK);
clk_i <= '0' after 100 ps;
clk_i2 <= '0' after 200 ps;
END PROCESS;
-- ---------------------------------------------------------------
-- State Machine
-- ---------------------------------------------------------------
st : PROCESS
variable tstate : string(9 DOWNTO 1) :="DESELECT ";
variable twe0 : std_logic := '0';
variable tre0 : std_logic := '0';
variable tce0 : std_logic := '0';
BEGIN
WAIT UNTIL POSEDGE(CK);
CASE state IS
WHEN "DESELECT " =>
if (E = '1') then
--Checking for ADSC Control
if (ADSC = '1') then
shiftnow(addr1, re2, re1, ce1, Dai, Dbi, Dci, Ddi, Dei, Dfi, Dgi, Dhi);
tre0 := R;
twe0 := W;
tce0 := '1';
addr0 <= A;
bwi <= BW;
bcnt <= to_stdlogicvector(0, 2);
tstate := "NEWCYCLE ";
end if;
-- Checking for ADSP Control
if (ADSP = '1') then
shiftnow(addr1, re2, re1, ce1, Dai, Dbi, Dci, Ddi, Dei, Dfi, Dgi, Dhi);
tre0 := R;
tce0 := '1';
addr0 <= A;
bcnt <= to_stdlogicvector(0, 2);
tstate := "LATEWRITE";
end if;
END IF;
-- Checking for Deselect
if ((E /= '1' and ADSC = '1') or (nADSP and (E2 = '0' or nE3 = '1'))) then
shiftnow(addr1, re2, re1, ce1, Dai, Dbi, Dci, Ddi, Dei, Dfi, Dgi, Dhi);
tstate := "DESELECT ";
twe0 := '0';
tre0 := '0';
tce0 := '0';
END IF;
-- **************************************************
WHEN "NEWCYCLE " | "BURST " | "SUSPBR " | "LATEWRITE" =>
--Checking for ADSC Control
if (ADSC = '1') then
shiftnow(addr1, re2, re1, ce1, Dai, Dbi, Dci, Ddi, Dei, Dfi, Dgi, Dhi);
tre0 := R;
twe0 := W;
tce0 := '1';
addr0 <= A;
bwi <= BW;
bcnt <= to_stdlogicvector(0, 2);
tstate := "NEWCYCLE ";
end if;
-- Checking for ADSP Control
if (ADSP = '1') then
shiftnow(addr1, re2, re1, ce1, Dai, Dbi, Dci, Ddi, Dei, Dfi, Dgi, Dhi);
tre0 := R;
tce0 := '1';
addr0 <= A;
bcnt <= to_stdlogicvector(0, 2);
tstate := "LATEWRITE";
end if;
-- Checking for Deselect
if ((E /= '1' and nADSC = '0') or (nADSP = '0' and (E2 = '0' or nE3 = '1'))) then
shiftnow(addr1, re2, re1, ce1, Dai, Dbi, Dci, Ddi, Dei, Dfi, Dgi, Dhi);
tstate := "DESELECT ";
twe0 := '0';
tre0 := '0';
tce0 := '0';
end if;
-- Checking for Burst Start
if (ADSC = '0' and ADSP = '0' AND ADV = '1') THEN
shiftnow(addr1, re2, re1, ce1, Dai, Dbi, Dci, Ddi, Dei, Dfi, Dgi, Dhi);
tstate := "BURST ";
if we0 = '1' then
twe0 := W;
tre0 := '0';
bwi <= BW;
end if;
if re0 = '1' then
twe0 := '0';
tre0 := R;
end if;
tce0 := '1';
bcnt <= to_stdlogicvector(bcnt + "01", 2);
end if;
-- Checking for a Suspended Burst
if (ADSC = '0' and ADSP = '0' AND ADV = '0') THEN
shiftnow(addr1, re2, re1, ce1, Dai, Dbi, Dci, Ddi, Dei, Dfi, Dgi, Dhi);
tstate := "SUSPBR ";
if we0 = '1' or W = '1' then
twe0 := W;
tre0 := '0';
re1 <= '0';
bwi <= BW;
elsif re0 = '1' then
twe0 := '0';
tre0 := R;
end if;
tce0 := '1';
end if;
WHEN OTHERS =>
shiftnow(addr1, re2, re1, ce1, Dai, Dbi, Dci, Ddi, Dei, Dfi, Dgi, Dhi);
tstate := "DESELECT ";
twe0 := '0';
tre0 := '0';
tce0 := '0';
bcnt <= to_stdlogicvector(0, 2);
END CASE;
state <= tstate;
we0 <= twe0;
re0 <= tre0;
ce0 <= tce0;
END PROCESS;
-- ---------------------------------------------------------------
-- Data IO Logic
-- ---------------------------------------------------------------
Write_Array: process (W_k)
begin -- process Write_Array
IF (POSEDGE(W_k)) THEN
IF (we = '1') THEN
IF bwi(0) = '1' THEN
bank0(to_integer(waddr)) := Dai;
END IF;
IF bwi(1) = '1' THEN
bank1(to_integer(waddr)) := Dbi;
END IF;
IF bwi(2) = '1' THEN
bank2(to_integer(waddr)) := Dci;
END IF;
IF bwi(3) = '1' THEN
bank3(to_integer(waddr)) := Ddi;
END IF;
IF bwi(4) = '1' THEN
bank4(to_integer(waddr)) := Dei;
END IF;
IF bwi(5) = '1' THEN
bank5(to_integer(waddr)) := Dfi;
END IF;
IF bwi(6) = '1' THEN
bank6(to_integer(waddr)) := Dgi;
END IF;
IF bwi(7) = '1' THEN
bank7(to_integer(waddr)) := Dhi;
END IF;
END IF;
END IF;
end process Write_Array;
Read_Array: process (r_k)
begin -- process Read_Array
IF (we = '0') then
Qai <= transport bank0(to_integer(raddr)) after DELAY - 200 ps;
Qbi <= transport bank1(to_integer(raddr)) after DELAY - 200 ps;
Qci <= transport bank2(to_integer(raddr)) after DELAY - 200 ps;
Qdi <= transport bank3(to_integer(raddr)) after DELAY - 200 ps;
Qei <= transport bank4(to_integer(raddr)) after DELAY - 200 ps;
Qfi <= transport bank5(to_integer(raddr)) after DELAY - 200 ps;
Qgi <= transport bank6(to_integer(raddr)) after DELAY - 200 ps;
Qhi <= transport bank7(to_integer(raddr)) after DELAY - 200 ps;
END IF;
end process Read_Array;
-- check it -t option is active and set correctly
time_ck : process (CLK_i)
begin
check_time <= CK'last_event;
assert check_time /= 0 ns report "Resolution needs to be set to 100ps for modelSIM use vsim -t 100ps <>" severity FAILURE;
end process time_ck;
ADS_SET : process (CLK_i)
begin
if posedge(clk_i) then
ADS <= ADSP OR ADSC;
end if;
end process ADS_SET;
q_switch : process (CLK_i2)
begin --read clock controls outputs
Qswitch <= transport re and ce after DELAY - 200 ps;
end process q_switch;
E <= (NOT nE1 AND E2 AND NOT nE3);
ADV <= not nADV;
ADSP <= NOT nADSP AND ( E2 or NOT nE3);
ADSC <= NOT nADSC AND ( not nE1 or E2 or NOT nE3);
W <= (NOT nGW OR NOT nBW );
W_k <=((NOT ADSP or not ADSC) AND (NOT nGW OR NOT nBW )) and clk_i after 100 ps;
R <= nGW and nBW;
R_k <= (TERNARY((ADS or ADV) and not W, TERNARY( nFT, re1, re0), '0') and clk_i) after 100 ps;
BW(0) <= not nGW or (NOT nBa and not nBW);
BW(1) <= not nGW or (NOT nBb and not nBW);
BW(2) <= not nGW or (NOT nBc and not nBW);
BW(3) <= not nGW or (NOT nBd and not nBW);
BW(4) <= not nGW or (NOT nBe and not nBW);
BW(5) <= not nGW or (NOT nBf and not nBW);
BW(6) <= not nGW or (NOT nBg and not nBW);
BW(7) <= not nGW or (NOT nBh and not nBW);
baddr <= to_stdlogicvector(TERNARY(nLBO, addr0(A_size - 1 DOWNTO 2) & (bcnt(1) XOR addr0(1)) &
(bcnt(0) XOR addr0(0)), addr0(A_size - 1 DOWNTO 2) & (addr0(1 DOWNTO 0) + bcnt)), A_size);
waddr <= to_stdlogicvector(TERNARY(not ADV, addr0, baddr), A_size);
raddr <= to_stdlogicvector(TERNARY(nFT, addr1, baddr), A_size);
we <= we0;
re <= TERNARY(nFT, re1, re0);
ce <= (TERNARY(not SCD AND re2 = '1', ce1, ce0));
oe <= re AND ce;
DELAY <= TERNARY(nG OR not ((we and re) or oe) OR ZZ, tKQ, tKQX);
DQa <= GUARDED TERNARY(Qswitch, Qai, HighZ);
DQb <= GUARDED TERNARY(Qswitch, Qbi, HighZ);
DQc <= GUARDED TERNARY(Qswitch, Qci, HighZ);
DQd <= GUARDED TERNARY(Qswitch, Qdi, HighZ);
DQe <= GUARDED TERNARY(Qswitch, Qei, HighZ);
DQf <= GUARDED TERNARY(Qswitch, Qfi, HighZ);
DQg <= GUARDED TERNARY(Qswitch, Qgi, HighZ);
DQh <= GUARDED TERNARY(Qswitch, Qhi, HighZ);
END GSI_BURST_CORE;
|
mit
|
impedimentToProgress/UCI-BlueChip
|
AttackFiles/Attacks/memAttack/lib/gleichmann/sim/uart_ext.vhd
|
2
|
2239
|
--------------------------------------------------------------------------------
-- Project: LEON-ARC
-- Entity: uart_ext
-- Architecture(s): behav
-- Author: [email protected]
-- Company: Gleichmann Electronics
--
-- Description:
-- This file contains a simple module that is connected to the 4 UART
-- signals CTS, RX, RTS and TX. It loops the signals RTS and TX back to the
-- outputs CTS and RX after a predefined time.
-- If enabled, the logger prints the current value of the 4 pins mentioned
-- above into a log file whenever they change.
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
library work;
use work.txt_util.all;
entity uart_ext is
generic (
logfile_name : string := "logfile_uart";
t_delay : time := 5 ns);
port (
resetn : in std_logic;
-- logging enable signal
log_en : in std_logic := '1';
-- current cycle number
cycle_num : in integer;
cts : out std_logic;
rxd : out std_logic;
txd : in std_logic;
rts : in std_logic);
end entity;
architecture behav of uart_ext is
file logfile : text open write_mode is logfile_name;
shared variable logline : line;
shared variable logstring : string(1 to 80);
begin
log_start : process is
begin
if log_en = '1' then
print(logfile, "#");
print(logfile, "# CYCLE_NUMBER CTS RX RTS TX");
print(logfile, "#");
end if;
wait;
end process;
-- note: cycle number shall not be on sensitivity list
log_loop : postponed process (log_en, rts, txd) is
variable rxd_int : std_logic;
variable cts_int : std_logic;
begin
rxd_int := txd;
cts_int := rts;
if (log_en = '1') and (cycle_num >= 0) then
print(logfile,
str(cycle_num) & " " &
str(cts_int) & " " &
str(rxd_int) & " " &
str(rts) & " " &
str(txd));
end if;
rxd <= rxd_int after t_delay;
cts <= cts_int after t_delay;
end process;
end architecture;
|
mit
|
impedimentToProgress/UCI-BlueChip
|
AttackFiles/Attacks/privEsc/lib/gaisler/can/canmux.vhd
|
5
|
895
|
-----------------------------------------------------------------------------
-- Entity: pcifbackend
-- File: pcifbackend.vhd
-- Author: Nils-Johan Wessman - Gaisler Research
-- Description: CAN Multiplexer (to connect two CAN buses to one CAN core)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity canmux is
port(
sel : in std_logic;
canrx : out std_logic;
cantx : in std_logic;
canrxv : in std_logic_vector(0 to 1);
cantxv : out std_logic_vector(0 to 1)
);
end;
architecture rtl of canmux is
begin
comb : process(sel, cantx, canrxv)
begin
if sel = '1' then
canrx <= canrxv(1);
cantxv(0) <= '1';
cantxv(1) <= cantx;
else
canrx <= canrxv(0);
cantxv(0) <= cantx;
cantxv(1) <= '1';
end if;
end process;
end;
|
mit
|
impedimentToProgress/UCI-BlueChip
|
AttackFiles/Attacks/memAttack/lib/gaisler/can/canmux.vhd
|
5
|
895
|
-----------------------------------------------------------------------------
-- Entity: pcifbackend
-- File: pcifbackend.vhd
-- Author: Nils-Johan Wessman - Gaisler Research
-- Description: CAN Multiplexer (to connect two CAN buses to one CAN core)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity canmux is
port(
sel : in std_logic;
canrx : out std_logic;
cantx : in std_logic;
canrxv : in std_logic_vector(0 to 1);
cantxv : out std_logic_vector(0 to 1)
);
end;
architecture rtl of canmux is
begin
comb : process(sel, cantx, canrxv)
begin
if sel = '1' then
canrx <= canrxv(1);
cantxv(0) <= '1';
cantxv(1) <= cantx;
else
canrx <= canrxv(0);
cantxv(0) <= cantx;
cantxv(1) <= '1';
end if;
end process;
end;
|
mit
|
impedimentToProgress/UCI-BlueChip
|
AttackFiles/Attacks/memAttack/lib/micron/sdram/mt48lc16m16a2.vhd
|
2
|
67097
|
--*****************************************************************************
--
-- Micron Semiconductor Products, Inc.
--
-- Copyright 1997, Micron Semiconductor Products, Inc.
-- All rights reserved.
--
--*****************************************************************************
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.ALL;
use std.textio.all;
PACKAGE mti_pkg IS
FUNCTION To_StdLogic (s : BIT) RETURN STD_LOGIC;
FUNCTION TO_INTEGER (input : STD_LOGIC) RETURN INTEGER;
FUNCTION TO_INTEGER (input : BIT_VECTOR) RETURN INTEGER;
FUNCTION TO_INTEGER (input : STD_LOGIC_VECTOR) RETURN INTEGER;
PROCEDURE TO_BITVECTOR (VARIABLE input : IN INTEGER; VARIABLE output : OUT BIT_VECTOR);
END mti_pkg;
PACKAGE BODY mti_pkg IS
-- Convert BIT to STD_LOGIC
FUNCTION To_StdLogic (s : BIT) RETURN STD_LOGIC IS
BEGIN
CASE s IS
WHEN '0' => RETURN ('0');
WHEN '1' => RETURN ('1');
WHEN OTHERS => RETURN ('0');
END CASE;
END;
-- Convert STD_LOGIC to INTEGER
FUNCTION TO_INTEGER (input : STD_LOGIC) RETURN INTEGER IS
VARIABLE result : INTEGER := 0;
VARIABLE weight : INTEGER := 1;
BEGIN
IF input = '1' THEN
result := weight;
ELSE
result := 0; -- if unknowns, default to logic 0
END IF;
RETURN result;
END TO_INTEGER;
-- Convert BIT_VECTOR to INTEGER
FUNCTION TO_INTEGER (input : BIT_VECTOR) RETURN INTEGER IS
VARIABLE result : INTEGER := 0;
VARIABLE weight : INTEGER := 1;
BEGIN
FOR i IN input'LOW TO input'HIGH LOOP
IF input(i) = '1' THEN
result := result + weight;
ELSE
result := result + 0; -- if unknowns, default to logic 0
END IF;
weight := weight * 2;
END LOOP;
RETURN result;
END TO_INTEGER;
-- Convert STD_LOGIC_VECTOR to INTEGER
FUNCTION TO_INTEGER (input : STD_LOGIC_VECTOR) RETURN INTEGER IS
VARIABLE result : INTEGER := 0;
VARIABLE weight : INTEGER := 1;
BEGIN
FOR i IN input'LOW TO input'HIGH LOOP
IF input(i) = '1' THEN
result := result + weight;
ELSE
result := result + 0; -- if unknowns, default to logic 0
END IF;
weight := weight * 2;
END LOOP;
RETURN result;
END TO_INTEGER;
-- Conver INTEGER to BIT_VECTOR
PROCEDURE TO_BITVECTOR (VARIABLE input : IN INTEGER; VARIABLE output : OUT BIT_VECTOR) IS
VARIABLE work,offset,outputlen,j : INTEGER := 0;
BEGIN
--length of vector
IF output'LENGTH > 32 THEN --'
outputlen := 32;
offset := output'LENGTH - 32; --'
IF input >= 0 THEN
FOR i IN offset-1 DOWNTO 0 LOOP
output(output'HIGH - i) := '0'; --'
END LOOP;
ELSE
FOR i IN offset-1 DOWNTO 0 LOOP
output(output'HIGH - i) := '1'; --'
END LOOP;
END IF;
ELSE
outputlen := output'LENGTH; --'
END IF;
--positive value
IF (input >= 0) THEN
work := input;
j := outputlen - 1;
FOR i IN 1 to 32 LOOP
IF j >= 0 then
IF (work MOD 2) = 0 THEN
output(output'HIGH-j-offset) := '0'; --'
ELSE
output(output'HIGH-j-offset) := '1'; --'
END IF;
END IF;
work := work / 2;
j := j - 1;
END LOOP;
IF outputlen = 32 THEN
output(output'HIGH) := '0'; --'
END IF;
--negative value
ELSE
work := (-input) - 1;
j := outputlen - 1;
FOR i IN 1 TO 32 LOOP
IF j>= 0 THEN
IF (work MOD 2) = 0 THEN
output(output'HIGH-j-offset) := '1'; --'
ELSE
output(output'HIGH-j-offset) := '0'; --'
END IF;
END IF;
work := work / 2;
j := j - 1;
END LOOP;
IF outputlen = 32 THEN
output(output'HIGH) := '1'; --'
END IF;
END IF;
END TO_BITVECTOR;
END mti_pkg;
-----------------------------------------------------------------------------------------
--
-- File Name: MT48LC16M16A2.VHD
-- Version: 0.0g
-- Date: June 29th, 2000
-- Model: Behavioral
-- Simulator: Model Technology (PC version 5.3 PE)
--
-- Dependencies: None
--
-- Author: Son P. Huynh
-- Email: [email protected]
-- Phone: (208) 368-3825
-- Company: Micron Technology, Inc.
-- Part Number: MT48LC16M16A2 (4Mb x 16 x 4 Banks)
--
-- Description: Micron 256Mb SDRAM
--
-- Limitation: - Doesn't check for 4096-cycle refresh --'
--
-- Note: - Set simulator resolution to "ps" accuracy
--
-- Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY
-- WHATSOEVER AND MICRON SPECIFICALLY DISCLAIMS ANY
-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
-- A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
--
-- Copyright (c) 1998 Micron Semiconductor Products, Inc.
-- All rights researved
--
-- Rev Author Phone Date Changes
-- ---- ---------------------------- ---------- -------------------------------------
-- 0.0g Son Huynh 208-368-3825 06/29/2000 Add Load/Dump memory array
-- Micron Technology Inc. Modify tWR + tRAS timing check
--
-- 0.0f Son Huynh 208-368-3825 07/08/1999 Fix tWR = 1 Clk + 7.5 ns (Auto)
-- Micron Technology Inc. Fix tWR = 15 ns (Manual)
-- Fix tRP (Autoprecharge to AutoRefresh)
--
-- 0.0c Son P. Huynh 208-368-3825 04/08/1999 Fix tWR + tRP in Write with AP
-- Micron Technology Inc. Fix tRC check in Load Mode Register
--
-- 0.0b Son P. Huynh 208-368-3825 01/06/1998 Derive from 64Mb SDRAM model
-- Micron Technology Inc.
--
-----------------------------------------------------------------------------------------
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
LIBRARY WORK;
USE WORK.MTI_PKG.ALL;
use std.textio.all;
library grlib;
use grlib.stdlib.all;
library gaisler;
use gaisler.sim.all;
ENTITY mt48lc16m16a2 IS
GENERIC (
-- Timing Parameters for -75 (PC133) and CAS Latency = 2
tAC : TIME := 6.0 ns;
tHZ : TIME := 7.0 ns;
tOH : TIME := 2.7 ns;
tMRD : INTEGER := 2; -- 2 Clk Cycles
tRAS : TIME := 44.0 ns;
tRC : TIME := 66.0 ns;
tRCD : TIME := 20.0 ns;
tRP : TIME := 20.0 ns;
tRRD : TIME := 15.0 ns;
tWRa : TIME := 7.5 ns; -- A2 Version - Auto precharge mode only (1 Clk + 7.5 ns)
tWRp : TIME := 15.0 ns; -- A2 Version - Precharge mode only (15 ns)
tAH : TIME := 0.8 ns;
tAS : TIME := 1.5 ns;
tCH : TIME := 2.5 ns;
tCL : TIME := 2.5 ns;
tCK : TIME := 10.0 ns;
tDH : TIME := 0.8 ns;
tDS : TIME := 1.5 ns;
tCKH : TIME := 0.8 ns;
tCKS : TIME := 1.5 ns;
tCMH : TIME := 0.8 ns;
tCMS : TIME := 1.5 ns;
addr_bits : INTEGER := 13;
data_bits : INTEGER := 16;
col_bits : INTEGER := 9;
index : INTEGER := 0;
fname : string := "sdram.srec" -- File to read from
);
PORT (
Dq : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
Addr : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
Ba : IN STD_LOGIC_VECTOR := "00";
Clk : IN STD_LOGIC := '0';
Cke : IN STD_LOGIC := '1';
Cs_n : IN STD_LOGIC := '1';
Ras_n : IN STD_LOGIC := '1';
Cas_n : IN STD_LOGIC := '1';
We_n : IN STD_LOGIC := '1';
Dqm : IN STD_LOGIC_VECTOR (1 DOWNTO 0) := "00"
);
END mt48lc16m16a2;
ARCHITECTURE behave OF mt48lc16m16a2 IS
TYPE State IS (ACT, A_REF, BST, LMR, NOP, PRECH, READ, READ_A, WRITE, WRITE_A, LOAD_FILE, DUMP_FILE);
TYPE Array4xI IS ARRAY (3 DOWNTO 0) OF INTEGER;
TYPE Array4xT IS ARRAY (3 DOWNTO 0) OF TIME;
TYPE Array4xB IS ARRAY (3 DOWNTO 0) OF BIT;
TYPE Array4x2BV IS ARRAY (3 DOWNTO 0) OF BIT_VECTOR (1 DOWNTO 0);
TYPE Array4xCBV IS ARRAY (4 DOWNTO 0) OF BIT_VECTOR (Col_bits - 1 DOWNTO 0);
TYPE Array_state IS ARRAY (4 DOWNTO 0) OF State;
SIGNAL Operation : State := NOP;
SIGNAL Mode_reg : BIT_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
SIGNAL Active_enable, Aref_enable, Burst_term : BIT := '0';
SIGNAL Mode_reg_enable, Prech_enable, Read_enable, Write_enable : BIT := '0';
SIGNAL Burst_length_1, Burst_length_2, Burst_length_4, Burst_length_8 : BIT := '0';
SIGNAL Cas_latency_2, Cas_latency_3 : BIT := '0';
SIGNAL Ras_in, Cas_in, We_in : BIT := '0';
SIGNAL Write_burst_mode : BIT := '0';
SIGNAL RAS_clk, Sys_clk, CkeZ : BIT := '0';
-- Checking internal wires
SIGNAL Pre_chk : BIT_VECTOR (3 DOWNTO 0) := "0000";
SIGNAL Act_chk : BIT_VECTOR (3 DOWNTO 0) := "0000";
SIGNAL Dq_in_chk, Dq_out_chk : BIT := '0';
SIGNAL Bank_chk : BIT_VECTOR (1 DOWNTO 0) := "00";
SIGNAL Row_chk : BIT_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
SIGNAL Col_chk : BIT_VECTOR (col_bits - 1 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- CS# Decode
WITH Cs_n SELECT
Cas_in <= TO_BIT (Cas_n, '1') WHEN '0',
'1' WHEN '1',
'1' WHEN OTHERS;
WITH Cs_n SELECT
Ras_in <= TO_BIT (Ras_n, '1') WHEN '0',
'1' WHEN '1',
'1' WHEN OTHERS;
WITH Cs_n SELECT
We_in <= TO_BIT (We_n, '1') WHEN '0',
'1' WHEN '1',
'1' WHEN OTHERS;
-- Commands Decode
Active_enable <= NOT(Ras_in) AND Cas_in AND We_in;
Aref_enable <= NOT(Ras_in) AND NOT(Cas_in) AND We_in;
Burst_term <= Ras_in AND Cas_in AND NOT(We_in);
Mode_reg_enable <= NOT(Ras_in) AND NOT(Cas_in) AND NOT(We_in);
Prech_enable <= NOT(Ras_in) AND Cas_in AND NOT(We_in);
Read_enable <= Ras_in AND NOT(Cas_in) AND We_in;
Write_enable <= Ras_in AND NOT(Cas_in) AND NOT(We_in);
-- Burst Length Decode
Burst_length_1 <= NOT(Mode_reg(2)) AND NOT(Mode_reg(1)) AND NOT(Mode_reg(0));
Burst_length_2 <= NOT(Mode_reg(2)) AND NOT(Mode_reg(1)) AND Mode_reg(0);
Burst_length_4 <= NOT(Mode_reg(2)) AND Mode_reg(1) AND NOT(Mode_reg(0));
Burst_length_8 <= NOT(Mode_reg(2)) AND Mode_reg(1) AND Mode_reg(0);
-- CAS Latency Decode
Cas_latency_2 <= NOT(Mode_reg(6)) AND Mode_reg(5) AND NOT(Mode_reg(4));
Cas_latency_3 <= NOT(Mode_reg(6)) AND Mode_reg(5) AND Mode_reg(4);
-- Write Burst Mode
Write_burst_mode <= Mode_reg(9);
-- RAS Clock for checking tWR and tRP
PROCESS
variable Clk0, Clk1 : integer := 0;
begin
RAS_clk <= '1';
wait for 0.5 ns;
RAS_clk <= '0';
wait for 0.5 ns;
if Clk0 > 100 or Clk1 > 100 then
wait;
else
if Clk = '1' and Cke = '1' then
Clk0 := 0;
Clk1 := Clk1 + 1;
elsif Clk = '0' and Cke = '1' then
Clk0 := Clk0 + 1;
Clk1 := 0;
end if;
end if;
END PROCESS;
-- System Clock
int_clk : PROCESS (Clk)
begin
IF Clk'LAST_VALUE = '0' AND Clk = '1' THEN --'
CkeZ <= TO_BIT(Cke, '1');
END IF;
Sys_clk <= CkeZ AND TO_BIT(Clk, '0');
END PROCESS;
state_register : PROCESS
-- NOTE: The extra bits in RAM_TYPE is for checking memory access. A logic 1 means
-- the location is in use. This will be checked when doing memory DUMP.
TYPE ram_type IS ARRAY (2**col_bits - 1 DOWNTO 0) OF BIT_VECTOR (data_bits DOWNTO 0);
TYPE ram_pntr IS ACCESS ram_type;
TYPE ram_stor IS ARRAY (2**addr_bits - 1 DOWNTO 0) OF ram_pntr;
VARIABLE Bank0 : ram_stor;
VARIABLE Bank1 : ram_stor;
VARIABLE Bank2 : ram_stor;
VARIABLE Bank3 : ram_stor;
VARIABLE Row_index, Col_index : INTEGER := 0;
VARIABLE Dq_temp : BIT_VECTOR (data_bits DOWNTO 0) := (OTHERS => '0');
VARIABLE Col_addr : Array4xCBV;
VARIABLE Bank_addr : Array4x2BV;
VARIABLE Dqm_reg0, Dqm_reg1 : BIT_VECTOR (1 DOWNTO 0) := "00";
VARIABLE Bank, Previous_bank : BIT_VECTOR (1 DOWNTO 0) := "00";
VARIABLE B0_row_addr, B1_row_addr, B2_row_addr, B3_row_addr : BIT_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
VARIABLE Col_brst : BIT_VECTOR (col_bits - 1 DOWNTO 0) := (OTHERS => '0');
VARIABLE Row : BIT_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
VARIABLE Col : BIT_VECTOR (col_bits - 1 DOWNTO 0) := (OTHERS => '0');
VARIABLE Burst_counter : INTEGER := 0;
VARIABLE Command : Array_state;
VARIABLE Bank_precharge : Array4x2BV;
VARIABLE A10_precharge : Array4xB := ('0' & '0' & '0' & '0');
VARIABLE Auto_precharge : Array4xB := ('0' & '0' & '0' & '0');
VARIABLE Read_precharge : Array4xB := ('0' & '0' & '0' & '0');
VARIABLE Write_precharge : Array4xB := ('0' & '0' & '0' & '0');
VARIABLE RW_interrupt_read : Array4xB := ('0' & '0' & '0' & '0');
VARIABLE RW_interrupt_write : Array4xB := ('0' & '0' & '0' & '0');
VARIABLE RW_interrupt_bank : BIT_VECTOR (1 DOWNTO 0) := "00";
VARIABLE Count_time : Array4xT := (0 ns & 0 ns & 0 ns & 0 ns);
VARIABLE Count_precharge : Array4xI := (0 & 0 & 0 & 0);
VARIABLE Data_in_enable, Data_out_enable : BIT := '0';
VARIABLE Pc_b0, Pc_b1, Pc_b2, Pc_b3 : BIT := '0';
VARIABLE Act_b0, Act_b1, Act_b2, Act_b3 : BIT := '0';
-- Timing Check
VARIABLE MRD_chk : INTEGER := 0;
VARIABLE WR_counter : Array4xI := (0 & 0 & 0 & 0);
VARIABLE WR_time : Array4xT := (0 ns & 0 ns & 0 ns & 0 ns);
VARIABLE WR_chkp : Array4xT := (0 ns & 0 ns & 0 ns & 0 ns);
VARIABLE RC_chk, RRD_chk : TIME := 0 ns;
VARIABLE RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3 : TIME := 0 ns;
VARIABLE RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3 : TIME := 0 ns;
VARIABLE RP_chk0, RP_chk1, RP_chk2, RP_chk3 : TIME := 0 ns;
-- Load and Dumb variables
FILE file_load : TEXT open read_mode is fname; -- Data load
FILE file_dump : TEXT open write_mode is "dumpdata.txt"; -- Data dump
VARIABLE bank_load : bit_vector ( 1 DOWNTO 0);
VARIABLE rows_load : BIT_VECTOR (12 DOWNTO 0);
VARIABLE cols_load : BIT_VECTOR ( 8 DOWNTO 0);
VARIABLE data_load : BIT_VECTOR (15 DOWNTO 0);
VARIABLE i, j : INTEGER;
VARIABLE good_load : BOOLEAN;
VARIABLE l : LINE;
variable load : std_logic := '1';
variable dump : std_logic := '0';
variable ch : character;
variable rectype : bit_vector(3 downto 0);
variable recaddr : bit_vector(31 downto 0);
variable reclen : bit_vector(7 downto 0);
variable recdata : bit_vector(0 to 16*8-1);
-- Initialize empty rows
PROCEDURE Init_mem (Bank : bit_vector (1 DOWNTO 0); Row_index : INTEGER) IS
VARIABLE i, j : INTEGER := 0;
BEGIN
IF Bank = "00" THEN
IF Bank0 (Row_index) = NULL THEN -- Check to see if row empty
Bank0 (Row_index) := NEW ram_type; -- Open new row for access
FOR i IN (2**col_bits - 1) DOWNTO 0 LOOP -- Filled row with zeros
FOR j IN (data_bits) DOWNTO 0 LOOP
Bank0 (Row_index) (i) (j) := '0';
END LOOP;
END LOOP;
END IF;
ELSIF Bank = "01" THEN
IF Bank1 (Row_index) = NULL THEN
Bank1 (Row_index) := NEW ram_type;
FOR i IN (2**col_bits - 1) DOWNTO 0 LOOP
FOR j IN (data_bits) DOWNTO 0 LOOP
Bank1 (Row_index) (i) (j) := '0';
END LOOP;
END LOOP;
END IF;
ELSIF Bank = "10" THEN
IF Bank2 (Row_index) = NULL THEN
Bank2 (Row_index) := NEW ram_type;
FOR i IN (2**col_bits - 1) DOWNTO 0 LOOP
FOR j IN (data_bits) DOWNTO 0 LOOP
Bank2 (Row_index) (i) (j) := '0';
END LOOP;
END LOOP;
END IF;
ELSIF Bank = "11" THEN
IF Bank3 (Row_index) = NULL THEN
Bank3 (Row_index) := NEW ram_type;
FOR i IN (2**col_bits - 1) DOWNTO 0 LOOP
FOR j IN (data_bits) DOWNTO 0 LOOP
Bank3 (Row_index) (i) (j) := '0';
END LOOP;
END LOOP;
END IF;
END IF;
END;
-- Burst Counter
PROCEDURE Burst_decode IS
VARIABLE Col_int : INTEGER := 0;
VARIABLE Col_vec, Col_temp : BIT_VECTOR (col_bits - 1 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- Advance Burst Counter
Burst_counter := Burst_counter + 1;
-- Burst Type
IF Mode_reg (3) = '0' THEN
Col_int := TO_INTEGER(Col);
Col_int := Col_int + 1;
TO_BITVECTOR (Col_int, Col_temp);
ELSIF Mode_reg (3) = '1' THEN
TO_BITVECTOR (Burst_counter, Col_vec);
Col_temp (2) := Col_vec (2) XOR Col_brst (2);
Col_temp (1) := Col_vec (1) XOR Col_brst (1);
Col_temp (0) := Col_vec (0) XOR Col_brst (0);
END IF;
-- Burst Length
IF Burst_length_2 = '1' THEN
Col (0) := Col_temp (0);
ELSIF Burst_length_4 = '1' THEN
Col (1 DOWNTO 0) := Col_temp (1 DOWNTO 0);
ELSIF Burst_length_8 = '1' THEN
Col (2 DOWNTO 0) := Col_temp (2 DOWNTO 0);
ELSE
Col := Col_temp;
END IF;
-- Burst Read Single Write
IF Write_burst_mode = '1' AND Data_in_enable = '1' THEN
Data_in_enable := '0';
END IF;
-- Data counter
IF Burst_length_1 = '1' THEN
IF Burst_counter >= 1 THEN
IF Data_in_enable = '1' THEN
Data_in_enable := '0';
ELSIF Data_out_enable = '1' THEN
Data_out_enable := '0';
END IF;
END IF;
ELSIF Burst_length_2 = '1' THEN
IF Burst_counter >= 2 THEN
IF Data_in_enable = '1' THEN
Data_in_enable := '0';
ELSIF Data_out_enable = '1' THEN
Data_out_enable := '0';
END IF;
END IF;
ELSIF Burst_length_4 = '1' THEN
IF Burst_counter >= 4 THEN
IF Data_in_enable = '1' THEN
Data_in_enable := '0';
ELSIF Data_out_enable = '1' THEN
Data_out_enable := '0';
END IF;
END IF;
ELSIF Burst_length_8 = '1' THEN
IF Burst_counter >= 8 THEN
IF Data_in_enable = '1' THEN
Data_in_enable := '0';
ELSIF Data_out_enable = '1' THEN
Data_out_enable := '0';
END IF;
END IF;
END IF;
END;
BEGIN
WAIT ON Sys_clk, RAS_clk;
IF Sys_clk'event AND Sys_clk = '1' AND Load = '0' AND Dump = '0' THEN --'
-- Internal Command Pipeline
Command(0) := Command(1);
Command(1) := Command(2);
Command(2) := Command(3);
Command(3) := NOP;
Col_addr(0) := Col_addr(1);
Col_addr(1) := Col_addr(2);
Col_addr(2) := Col_addr(3);
Col_addr(3) := (OTHERS => '0');
Bank_addr(0) := Bank_addr(1);
Bank_addr(1) := Bank_addr(2);
Bank_addr(2) := Bank_addr(3);
Bank_addr(3) := "00";
Bank_precharge(0) := Bank_precharge(1);
Bank_precharge(1) := Bank_precharge(2);
Bank_precharge(2) := Bank_precharge(3);
Bank_precharge(3) := "00";
A10_precharge(0) := A10_precharge(1);
A10_precharge(1) := A10_precharge(2);
A10_precharge(2) := A10_precharge(3);
A10_precharge(3) := '0';
-- Operation Decode (Optional for showing current command on posedge clock / debug feature)
IF Active_enable = '1' THEN
Operation <= ACT;
ELSIF Aref_enable = '1' THEN
Operation <= A_REF;
ELSIF Burst_term = '1' THEN
Operation <= BST;
ELSIF Mode_reg_enable = '1' THEN
Operation <= LMR;
ELSIF Prech_enable = '1' THEN
Operation <= PRECH;
ELSIF Read_enable = '1' THEN
IF Addr(10) = '0' THEN
Operation <= READ;
ELSE
Operation <= READ_A;
END IF;
ELSIF Write_enable = '1' THEN
IF Addr(10) = '0' THEN
Operation <= WRITE;
ELSE
Operation <= WRITE_A;
END IF;
ELSE
Operation <= NOP;
END IF;
-- Dqm pipeline for Read
Dqm_reg0 := Dqm_reg1;
Dqm_reg1 := TO_BITVECTOR(Dqm);
-- Read or Write with Auto Precharge Counter
IF Auto_precharge (0) = '1' THEN
Count_precharge (0) := Count_precharge (0) + 1;
END IF;
IF Auto_precharge (1) = '1' THEN
Count_precharge (1) := Count_precharge (1) + 1;
END IF;
IF Auto_precharge (2) = '1' THEN
Count_precharge (2) := Count_precharge (2) + 1;
END IF;
IF Auto_precharge (3) = '1' THEN
Count_precharge (3) := Count_precharge (3) + 1;
END IF;
-- Auto Precharge Timer for tWR
if (Burst_length_1 = '1' OR Write_burst_mode = '1') then
if (Count_precharge(0) = 1) then
Count_time(0) := NOW;
end if;
if (Count_precharge(1) = 1) then
Count_time(1) := NOW;
end if;
if (Count_precharge(2) = 1) then
Count_time(2) := NOW;
end if;
if (Count_precharge(3) = 1) then
Count_time(3) := NOW;
end if;
elsif (Burst_length_2 = '1') then
if (Count_precharge(0) = 2) then
Count_time(0) := NOW;
end if;
if (Count_precharge(1) = 2) then
Count_time(1) := NOW;
end if;
if (Count_precharge(2) = 2) then
Count_time(2) := NOW;
end if;
if (Count_precharge(3) = 2) then
Count_time(3) := NOW;
end if;
elsif (Burst_length_4 = '1') then
if (Count_precharge(0) = 4) then
Count_time(0) := NOW;
end if;
if (Count_precharge(1) = 4) then
Count_time(1) := NOW;
end if;
if (Count_precharge(2) = 4) then
Count_time(2) := NOW;
end if;
if (Count_precharge(3) = 4) then
Count_time(3) := NOW;
end if;
elsif (Burst_length_8 = '1') then
if (Count_precharge(0) = 8) then
Count_time(0) := NOW;
end if;
if (Count_precharge(1) = 8) then
Count_time(1) := NOW;
end if;
if (Count_precharge(2) = 8) then
Count_time(2) := NOW;
end if;
if (Count_precharge(3) = 8) then
Count_time(3) := NOW;
end if;
end if;
-- tMRD Counter
MRD_chk := MRD_chk + 1;
-- tWR Counter
WR_counter(0) := WR_counter(0) + 1;
WR_counter(1) := WR_counter(1) + 1;
WR_counter(2) := WR_counter(2) + 1;
WR_counter(3) := WR_counter(3) + 1;
-- Auto Refresh
IF Aref_enable = '1' THEN
-- Auto Refresh to Auto Refresh
ASSERT (NOW - RC_chk >= tRC)
REPORT "tRC violation during Auto Refresh"
SEVERITY WARNING;
-- Precharge to Auto Refresh
ASSERT (NOW - RP_chk0 >= tRP OR NOW - RP_chk1 >= tRP OR NOW - RP_chk2 >= tRP OR NOW - RP_chk3 >= tRP)
REPORT "tRP violation during Auto Refresh"
SEVERITY WARNING;
-- All banks must be idle before refresh
IF (Pc_b3 ='0' OR Pc_b2 = '0' OR Pc_b1 ='0' OR Pc_b0 = '0') THEN
ASSERT (FALSE)
REPORT "All banks must be Precharge before Auto Refresh"
SEVERITY WARNING;
END IF;
-- Record current tRC time
RC_chk := NOW;
END IF;
-- Load Mode Register
IF Mode_reg_enable = '1' THEN
Mode_reg <= TO_BITVECTOR (Addr);
IF (Pc_b3 ='0' OR Pc_b2 = '0' OR Pc_b1 ='0' OR Pc_b0 = '0') THEN
ASSERT (FALSE)
REPORT "All bank must be Precharge before Load Mode Register"
SEVERITY WARNING;
END IF;
-- REF to LMR
ASSERT (NOW - RC_chk >= tRC)
REPORT "tRC violation during Load Mode Register"
SEVERITY WARNING;
-- LMR to LMR
ASSERT (MRD_chk >= tMRD)
REPORT "tMRD violation during Load Mode Register"
SEVERITY WARNING;
-- Record current tMRD time
MRD_chk := 0;
END IF;
-- Active Block (latch Bank and Row Address)
IF Active_enable = '1' THEN
IF Ba = "00" AND Pc_b0 = '1' THEN
Act_b0 := '1';
Pc_b0 := '0';
B0_row_addr := TO_BITVECTOR (Addr);
RCD_chk0 := NOW;
RAS_chk0 := NOW;
-- Precharge to Active Bank 0
ASSERT (NOW - RP_chk0 >= tRP)
REPORT "tRP violation during Activate Bank 0"
SEVERITY WARNING;
ELSIF Ba = "01" AND Pc_b1 = '1' THEN
Act_b1 := '1';
Pc_b1 := '0';
B1_row_addr := TO_BITVECTOR (Addr);
RCD_chk1 := NOW;
RAS_chk1 := NOW;
-- Precharge to Active Bank 1
ASSERT (NOW - RP_chk1 >= tRP)
REPORT "tRP violation during Activate Bank 1"
SEVERITY WARNING;
ELSIF Ba = "10" AND Pc_b2 = '1' THEN
Act_b2 := '1';
Pc_b2 := '0';
B2_row_addr := TO_BITVECTOR (Addr);
RCD_chk2 := NOW;
RAS_chk2 := NOW;
-- Precharge to Active Bank 2
ASSERT (NOW - RP_chk2 >= tRP)
REPORT "tRP violation during Activate Bank 2"
SEVERITY WARNING;
ELSIF Ba = "11" AND Pc_b3 = '1' THEN
Act_b3 := '1';
Pc_b3 := '0';
B3_row_addr := TO_BITVECTOR (Addr);
RCD_chk3 := NOW;
RAS_chk3 := NOW;
-- Precharge to Active Bank 3
ASSERT (NOW - RP_chk3 >= tRP)
REPORT "tRP violation during Activate Bank 3"
SEVERITY WARNING;
ELSIF Ba = "00" AND Pc_b0 = '0' THEN
ASSERT (FALSE)
REPORT "Bank 0 is not Precharged"
SEVERITY WARNING;
ELSIF Ba = "01" AND Pc_b1 = '0' THEN
ASSERT (FALSE)
REPORT "Bank 1 is not Precharged"
SEVERITY WARNING;
ELSIF Ba = "10" AND Pc_b2 = '0' THEN
ASSERT (FALSE)
REPORT "Bank 2 is not Precharged"
SEVERITY WARNING;
ELSIF Ba = "11" AND Pc_b3 = '0' THEN
ASSERT (FALSE)
REPORT "Bank 3 is not Precharged"
SEVERITY WARNING;
END IF;
-- Active Bank A to Active Bank B
IF ((Previous_bank /= TO_BITVECTOR (Ba)) AND (NOW - RRD_chk < tRRD)) THEN
ASSERT (FALSE)
REPORT "tRRD violation during Activate"
SEVERITY WARNING;
END IF;
-- LMR to ACT
ASSERT (MRD_chk >= tMRD)
REPORT "tMRD violation during Activate"
SEVERITY WARNING;
-- AutoRefresh to Activate
ASSERT (NOW - RC_chk >= tRC)
REPORT "tRC violation during Activate"
SEVERITY WARNING;
-- Record variable for checking violation
RRD_chk := NOW;
Previous_bank := TO_BITVECTOR (Ba);
END IF;
-- Precharge Block
IF Prech_enable = '1' THEN
IF Addr(10) = '1' THEN
Pc_b0 := '1';
Pc_b1 := '1';
Pc_b2 := '1';
Pc_b3 := '1';
Act_b0 := '0';
Act_b1 := '0';
Act_b2 := '0';
Act_b3 := '0';
RP_chk0 := NOW;
RP_chk1 := NOW;
RP_chk2 := NOW;
RP_chk3 := NOW;
-- Activate to Precharge all banks
ASSERT ((NOW - RAS_chk0 >= tRAS) OR (NOW - RAS_chk1 >= tRAS))
REPORT "tRAS violation during Precharge all banks"
SEVERITY WARNING;
-- tWR violation check for Write
IF ((NOW - WR_chkp(0) < tWRp) OR (NOW - WR_chkp(1) < tWRp) OR
(NOW - WR_chkp(2) < tWRp) OR (NOW - WR_chkp(3) < tWRp)) THEN
ASSERT (FALSE)
REPORT "tWR violation during Precharge ALL banks"
SEVERITY WARNING;
END IF;
ELSIF Addr(10) = '0' THEN
IF Ba = "00" THEN
Pc_b0 := '1';
Act_b0 := '0';
RP_chk0 := NOW;
-- Activate to Precharge bank 0
ASSERT (NOW - RAS_chk0 >= tRAS)
REPORT "tRAS violation during Precharge bank 0"
SEVERITY WARNING;
ELSIF Ba = "01" THEN
Pc_b1 := '1';
Act_b1 := '0';
RP_chk1 := NOW;
-- Activate to Precharge bank 1
ASSERT (NOW - RAS_chk1 >= tRAS)
REPORT "tRAS violation during Precharge bank 1"
SEVERITY WARNING;
ELSIF Ba = "10" THEN
Pc_b2 := '1';
Act_b2 := '0';
RP_chk2 := NOW;
-- Activate to Precharge bank 2
ASSERT (NOW - RAS_chk2 >= tRAS)
REPORT "tRAS violation during Precharge bank 2"
SEVERITY WARNING;
ELSIF Ba = "11" THEN
Pc_b3 := '1';
Act_b3 := '0';
RP_chk3 := NOW;
-- Activate to Precharge bank 3
ASSERT (NOW - RAS_chk3 >= tRAS)
REPORT "tRAS violation during Precharge bank 3"
SEVERITY WARNING;
END IF;
-- tWR violation check for Write
ASSERT (NOW - WR_chkp(TO_INTEGER(Ba)) >= tWRp)
REPORT "tWR violation during Precharge"
SEVERITY WARNING;
END IF;
-- Terminate a Write Immediately (if same bank or all banks)
IF (Data_in_enable = '1' AND (Bank = TO_BITVECTOR(Ba) OR Addr(10) = '1')) THEN
Data_in_enable := '0';
END IF;
-- Precharge Command Pipeline for READ
IF CAS_latency_3 = '1' THEN
Command(2) := PRECH;
Bank_precharge(2) := TO_BITVECTOR (Ba);
A10_precharge(2) := TO_BIT(Addr(10));
ELSIF CAS_latency_2 = '1' THEN
Command(1) := PRECH;
Bank_precharge(1) := TO_BITVECTOR (Ba);
A10_precharge(1) := TO_BIT(Addr(10));
END IF;
END IF;
-- Burst Terminate
IF Burst_term = '1' THEN
-- Terminate a Write immediately
IF Data_in_enable = '1' THEN
Data_in_enable := '0';
END IF;
-- Terminate a Read depend on CAS Latency
IF CAS_latency_3 = '1' THEN
Command(2) := BST;
ELSIF CAS_latency_2 = '1' THEN
Command(1) := BST;
END IF;
END IF;
-- Read, Write, Column Latch
IF Read_enable = '1' OR Write_enable = '1' THEN
-- Check to see if bank is open (ACT) for Read or Write
IF ((Ba="00" AND Pc_b0='1') OR (Ba="01" AND Pc_b1='1') OR (Ba="10" AND Pc_b2='1') OR (Ba="11" AND Pc_b3='1')) THEN
ASSERT (FALSE)
REPORT "Cannot Read or Write - Bank is not Activated"
SEVERITY WARNING;
END IF;
-- Activate to Read or Write
IF Ba = "00" THEN
ASSERT (NOW - RCD_chk0 >= tRCD)
REPORT "tRCD violation during Read or Write to Bank 0"
SEVERITY WARNING;
ELSIF Ba = "01" THEN
ASSERT (NOW - RCD_chk1 >= tRCD)
REPORT "tRCD violation during Read or Write to Bank 1"
SEVERITY WARNING;
ELSIF Ba = "10" THEN
ASSERT (NOW - RCD_chk2 >= tRCD)
REPORT "tRCD violation during Read or Write to Bank 2"
SEVERITY WARNING;
ELSIF Ba = "11" THEN
ASSERT (NOW - RCD_chk3 >= tRCD)
REPORT "tRCD violation during Read or Write to Bank 3"
SEVERITY WARNING;
END IF;
-- Read Command
IF Read_enable = '1' THEN
-- CAS Latency Pipeline
IF Cas_latency_3 = '1' THEN
IF Addr(10) = '1' THEN
Command(2) := READ_A;
ELSE
Command(2) := READ;
END IF;
Col_addr (2) := TO_BITVECTOR (Addr(col_bits - 1 DOWNTO 0));
Bank_addr (2) := TO_BITVECTOR (Ba);
ELSIF Cas_latency_2 = '1' THEN
IF Addr(10) = '1' THEN
Command(1) := READ_A;
ELSE
Command(1) := READ;
END IF;
Col_addr (1) := TO_BITVECTOR (Addr(col_bits - 1 DOWNTO 0));
Bank_addr (1) := TO_BITVECTOR (Ba);
END IF;
-- Read intterupt a Write (terminate Write immediately)
IF Data_in_enable = '1' THEN
Data_in_enable := '0';
END IF;
-- Write Command
ELSIF Write_enable = '1' THEN
IF Addr(10) = '1' THEN
Command(0) := WRITE_A;
ELSE
Command(0) := WRITE;
END IF;
Col_addr (0) := TO_BITVECTOR (Addr(col_bits - 1 DOWNTO 0));
Bank_addr (0) := TO_BITVECTOR (Ba);
-- Write intterupt a Write (terminate Write immediately)
IF Data_in_enable = '1' THEN
Data_in_enable := '0';
END IF;
-- Write interrupt a Read (terminate Read immediately)
IF Data_out_enable = '1' THEN
Data_out_enable := '0';
END IF;
END IF;
-- Interrupt a Write with Auto Precharge
IF Auto_precharge(TO_INTEGER(RW_Interrupt_Bank)) = '1' AND Write_precharge(TO_INTEGER(RW_Interrupt_Bank)) = '1' THEN
RW_interrupt_write(TO_INTEGER(RW_Interrupt_Bank)) := '1';
END IF;
-- Interrupt a Read with Auto Precharge
IF Auto_precharge(TO_INTEGER(RW_Interrupt_Bank)) = '1' AND Read_precharge(TO_INTEGER(RW_Interrupt_Bank)) = '1' THEN
RW_interrupt_read(TO_INTEGER(RW_Interrupt_Bank)) := '1';
END IF;
-- Read or Write with Auto Precharge
IF Addr(10) = '1' THEN
Auto_precharge (TO_INTEGER(Ba)) := '1';
Count_precharge (TO_INTEGER(Ba)) := 0;
RW_Interrupt_Bank := TO_BitVector(Ba);
IF Read_enable = '1' THEN
Read_precharge (TO_INTEGER(Ba)) := '1';
ELSIF Write_enable = '1' THEN
Write_precharge (TO_INTEGER(Ba)) := '1';
END IF;
END IF;
END IF;
-- Read with AutoPrecharge Calculation
-- The device start internal precharge when:
-- 1. BL/2 cycles after command
-- and 2. Meet tRAS requirement
-- or 3. Interrupt by a Read or Write (with or without Auto Precharge)
IF ((Auto_precharge(0) = '1') AND (Read_precharge(0) = '1')) THEN
IF (((NOW - RAS_chk0 >= tRAS) AND
((Burst_length_1 = '1' AND Count_precharge(0) >= 1) OR
(Burst_length_2 = '1' AND Count_precharge(0) >= 2) OR
(Burst_length_4 = '1' AND Count_precharge(0) >= 4) OR
(Burst_length_8 = '1' AND Count_precharge(0) >= 8))) OR
(RW_interrupt_read(0) = '1')) THEN
Pc_b0 := '1';
Act_b0 := '0';
RP_chk0 := NOW;
Auto_precharge(0) := '0';
Read_precharge(0) := '0';
RW_interrupt_read(0) := '0';
END IF;
END IF;
IF ((Auto_precharge(1) = '1') AND (Read_precharge(1) = '1')) THEN
IF (((NOW - RAS_chk1 >= tRAS) AND
((Burst_length_1 = '1' AND Count_precharge(1) >= 1) OR
(Burst_length_2 = '1' AND Count_precharge(1) >= 2) OR
(Burst_length_4 = '1' AND Count_precharge(1) >= 4) OR
(Burst_length_8 = '1' AND Count_precharge(1) >= 8))) OR
(RW_interrupt_read(1) = '1')) THEN
Pc_b1 := '1';
Act_b1 := '0';
RP_chk1 := NOW;
Auto_precharge(1) := '0';
Read_precharge(1) := '0';
RW_interrupt_read(1) := '0';
END IF;
END IF;
IF ((Auto_precharge(2) = '1') AND (Read_precharge(2) = '1')) THEN
IF (((NOW - RAS_chk2 >= tRAS) AND
((Burst_length_1 = '1' AND Count_precharge(2) >= 1) OR
(Burst_length_2 = '1' AND Count_precharge(2) >= 2) OR
(Burst_length_4 = '1' AND Count_precharge(2) >= 4) OR
(Burst_length_8 = '1' AND Count_precharge(2) >= 8))) OR
(RW_interrupt_read(2) = '1')) THEN
Pc_b2 := '1';
Act_b2 := '0';
RP_chk2 := NOW;
Auto_precharge(2) := '0';
Read_precharge(2) := '0';
RW_interrupt_read(2) := '0';
END IF;
END IF;
IF ((Auto_precharge(3) = '1') AND (Read_precharge(3) = '1')) THEN
IF (((NOW - RAS_chk3 >= tRAS) AND
((Burst_length_1 = '1' AND Count_precharge(3) >= 1) OR
(Burst_length_2 = '1' AND Count_precharge(3) >= 2) OR
(Burst_length_4 = '1' AND Count_precharge(3) >= 4) OR
(Burst_length_8 = '1' AND Count_precharge(3) >= 8))) OR
(RW_interrupt_read(3) = '1')) THEN
Pc_b3 := '1';
Act_b3 := '0';
RP_chk3 := NOW;
Auto_precharge(3) := '0';
Read_precharge(3) := '0';
RW_interrupt_read(3) := '0';
END IF;
END IF;
-- Internal Precharge or Bst
IF Command(0) = PRECH THEN -- PRECH terminate a read if same bank or all banks
IF Bank_precharge(0) = Bank OR A10_precharge(0) = '1' THEN
IF Data_out_enable = '1' THEN
Data_out_enable := '0';
END IF;
END IF;
ELSIF Command(0) = BST THEN -- BST terminate a read regardless of bank
IF Data_out_enable = '1' THEN
Data_out_enable := '0';
END IF;
END IF;
IF Data_out_enable = '0' THEN
Dq <= TRANSPORT (OTHERS => 'Z') AFTER tOH;
END IF;
-- Detect Read or Write Command
IF Command(0) = READ OR Command(0) = READ_A THEN
Bank := Bank_addr (0);
Col := Col_addr (0);
Col_brst := Col_addr (0);
IF Bank_addr (0) = "00" THEN
Row := B0_row_addr;
ELSIF Bank_addr (0) = "01" THEN
Row := B1_row_addr;
ELSIF Bank_addr (0) = "10" THEN
Row := B2_row_addr;
ELSE
Row := B3_row_addr;
END IF;
Burst_counter := 0;
Data_in_enable := '0';
Data_out_enable := '1';
ELSIF Command(0) = WRITE OR Command(0) = WRITE_A THEN
Bank := Bank_addr(0);
Col := Col_addr(0);
Col_brst := Col_addr(0);
IF Bank_addr (0) = "00" THEN
Row := B0_row_addr;
ELSIF Bank_addr (0) = "01" THEN
Row := B1_row_addr;
ELSIF Bank_addr (0) = "10" THEN
Row := B2_row_addr;
ELSE
Row := B3_row_addr;
END IF;
Burst_counter := 0;
Data_in_enable := '1';
Data_out_enable := '0';
END IF;
-- DQ (Driver / Receiver)
Row_index := TO_INTEGER (Row);
Col_index := TO_INTEGER (Col);
IF Data_in_enable = '1' THEN
IF Dqm /= "11" THEN
Init_mem (Bank, Row_index);
IF Bank = "00" THEN
Dq_temp := Bank0 (Row_index) (Col_index);
IF Dqm = "01" THEN
Dq_temp (15 DOWNTO 8) := TO_BITVECTOR (Dq (15 DOWNTO 8));
ELSIF Dqm = "10" THEN
Dq_temp (7 DOWNTO 0) := TO_BITVECTOR (Dq (7 DOWNTO 0));
ELSE
Dq_temp (15 DOWNTO 0) := TO_BITVECTOR (Dq (15 DOWNTO 0));
END IF;
Bank0 (Row_index) (Col_index) := ('1' & Dq_temp(data_bits - 1 DOWNTO 0));
ELSIF Bank = "01" THEN
Dq_temp := Bank1 (Row_index) (Col_index);
IF Dqm = "01" THEN
Dq_temp (15 DOWNTO 8) := TO_BITVECTOR (Dq (15 DOWNTO 8));
ELSIF Dqm = "10" THEN
Dq_temp (7 DOWNTO 0) := TO_BITVECTOR (Dq (7 DOWNTO 0));
ELSE
Dq_temp (15 DOWNTO 0) := TO_BITVECTOR (Dq (15 DOWNTO 0));
END IF;
Bank1 (Row_index) (Col_index) := ('1' & Dq_temp(data_bits - 1 DOWNTO 0));
ELSIF Bank = "10" THEN
Dq_temp := Bank2 (Row_index) (Col_index);
IF Dqm = "01" THEN
Dq_temp (15 DOWNTO 8) := TO_BITVECTOR (Dq (15 DOWNTO 8));
ELSIF Dqm = "10" THEN
Dq_temp (7 DOWNTO 0) := TO_BITVECTOR (Dq (7 DOWNTO 0));
ELSE
Dq_temp (15 DOWNTO 0) := TO_BITVECTOR (Dq (15 DOWNTO 0));
END IF;
Bank2 (Row_index) (Col_index) := ('1' & Dq_temp(data_bits - 1 DOWNTO 0));
ELSIF Bank = "11" THEN
Dq_temp := Bank3 (Row_index) (Col_index);
IF Dqm = "01" THEN
Dq_temp (15 DOWNTO 8) := TO_BITVECTOR (Dq (15 DOWNTO 8));
ELSIF Dqm = "10" THEN
Dq_temp (7 DOWNTO 0) := TO_BITVECTOR (Dq (7 DOWNTO 0));
ELSE
Dq_temp (15 DOWNTO 0) := TO_BITVECTOR (Dq (15 DOWNTO 0));
END IF;
Bank3 (Row_index) (Col_index) := ('1' & Dq_temp(data_bits - 1 DOWNTO 0));
END IF;
WR_chkp(TO_INTEGER(Bank)) := NOW;
WR_counter(TO_INTEGER(Bank)) := 0;
END IF;
Burst_decode;
ELSIF Data_out_enable = '1' THEN
IF Dqm_reg0 /= "11" THEN
Init_mem (Bank, Row_index);
IF Bank = "00" THEN
Dq_temp := Bank0 (Row_index) (Col_index);
IF Dqm_reg0 = "00" THEN
Dq (15 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 0)) AFTER tAC;
ELSIF Dqm_reg0 = "01" THEN
Dq (15 DOWNTO 8) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 8)) AFTER tAC;
Dq (7 DOWNTO 0) <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
ELSIF Dqm_reg0 = "10" THEN
Dq (15 DOWNTO 8) <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
Dq (7 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (7 DOWNTO 0)) AFTER tAC;
END IF;
ELSIF Bank = "01" THEN
Dq_temp := Bank1 (Row_index) (Col_index);
IF Dqm_reg0 = "00" THEN
Dq (15 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 0)) AFTER tAC;
ELSIF Dqm_reg0 = "01" THEN
Dq (15 DOWNTO 8) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 8)) AFTER tAC;
Dq (7 DOWNTO 0) <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
ELSIF Dqm_reg0 = "10" THEN
Dq (15 DOWNTO 8) <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
Dq (7 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (7 DOWNTO 0)) AFTER tAC;
END IF;
ELSIF Bank = "10" THEN
Dq_temp := Bank2 (Row_index) (Col_index);
IF Dqm_reg0 = "00" THEN
Dq (15 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 0)) AFTER tAC;
ELSIF Dqm_reg0 = "01" THEN
Dq (15 DOWNTO 8) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 8)) AFTER tAC;
Dq (7 DOWNTO 0) <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
ELSIF Dqm_reg0 = "10" THEN
Dq (15 DOWNTO 8) <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
Dq (7 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (7 DOWNTO 0)) AFTER tAC;
END IF;
ELSIF Bank = "11" THEN
Dq_temp := Bank3 (Row_index) (Col_index);
IF Dqm_reg0 = "00" THEN
Dq (15 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 0)) AFTER tAC;
ELSIF Dqm_reg0 = "01" THEN
Dq (15 DOWNTO 8) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 8)) AFTER tAC;
Dq (7 DOWNTO 0) <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
ELSIF Dqm_reg0 = "10" THEN
Dq (15 DOWNTO 8) <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
Dq (7 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (7 DOWNTO 0)) AFTER tAC;
END IF;
END IF;
ELSE
Dq <= TRANSPORT (OTHERS => 'Z') AFTER tHZ;
END IF;
Burst_decode;
END IF;
ELSIF Sys_clk'event AND Sys_clk = '1' AND Load = '1' AND Dump = '0' THEN --'
Operation <= LOAD_FILE;
load := '0';
-- ASSERT (FALSE) REPORT "Reading memory array from file. This operation may take several minutes. Please wait..."
-- SEVERITY NOTE;
WHILE NOT endfile(file_load) LOOP
readline(file_load, l);
read(l, ch);
if (ch /= 'S') or (ch /= 's') then
hexread(l, rectype);
hexread(l, reclen);
recaddr := (others => '0');
case rectype is
when "0001" =>
hexread(l, recaddr(15 downto 0));
when "0010" =>
hexread(l, recaddr(23 downto 0));
when "0011" =>
hexread(l, recaddr);
recaddr(31 downto 24) := (others => '0');
when others => next;
end case;
if true then
hexread(l, recdata);
Bank_Load := recaddr(25 downto 24);
Rows_Load := recaddr(23 downto 11);
Cols_Load := recaddr(10 downto 2);
Init_Mem (Bank_Load, To_Integer(Rows_Load));
IF Bank_Load = "00" THEN
for i in 0 to 3 loop
Bank0 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*32+index to i*32+index+15));
end loop;
ELSIF Bank_Load = "01" THEN
for i in 0 to 3 loop
Bank1 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*32+index to i*32+index+15));
end loop;
ELSIF Bank_Load = "10" THEN
for i in 0 to 3 loop
Bank2 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*32+index to i*32+index+15));
end loop;
ELSIF Bank_Load = "11" THEN
for i in 0 to 3 loop
Bank3 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*32+index to i*32+index+15));
end loop;
END IF;
END IF;
END IF;
END LOOP;
ELSIF Sys_clk'event AND Sys_clk = '1' AND Load = '0' AND Dump = '1' THEN --'
Operation <= DUMP_FILE;
ASSERT (FALSE) REPORT "Writing memory array to file. This operation may take several minutes. Please wait..."
SEVERITY NOTE;
WRITE (l, string'("# Micron Technology, Inc. (FILE DUMP / MEMORY DUMP)")); --'
WRITELINE (file_dump, l);
WRITE (l, string'("# BA ROWS COLS DQ")); --'
WRITELINE (file_dump, l);
WRITE (l, string'("# -- ------------- --------- ----------------")); --'
WRITELINE (file_dump, l);
-- Dumping Bank 0
FOR i IN 0 TO 2**addr_bits -1 LOOP
-- Check if ROW is NULL
IF Bank0 (i) /= NULL THEN
For j IN 0 TO 2**col_bits - 1 LOOP
-- Check if COL is NULL
NEXT WHEN Bank0 (i) (j) (data_bits) = '0';
WRITE (l, string'("00"), right, 4); --'
WRITE (l, To_BitVector(Conv_Std_Logic_Vector(i, addr_bits)), right, addr_bits+1);
WRITE (l, To_BitVector(Conv_std_Logic_Vector(j, col_bits)), right, col_bits+1);
WRITE (l, Bank0 (i) (j) (data_bits -1 DOWNTO 0), right, data_bits+1);
WRITELINE (file_dump, l);
END LOOP;
END IF;
END LOOP;
-- Dumping Bank 1
FOR i IN 0 TO 2**addr_bits -1 LOOP
-- Check if ROW is NULL
IF Bank1 (i) /= NULL THEN
For j IN 0 TO 2**col_bits - 1 LOOP
-- Check if COL is NULL
NEXT WHEN Bank1 (i) (j) (data_bits) = '0';
WRITE (l, string'("01"), right, 4); --'
WRITE (l, To_BitVector(Conv_Std_Logic_Vector(i, addr_bits)), right, addr_bits+1);
WRITE (l, To_BitVector(Conv_std_Logic_Vector(j, col_bits)), right, col_bits+1);
WRITE (l, Bank1 (i) (j) (data_bits -1 DOWNTO 0), right, data_bits+1);
WRITELINE (file_dump, l);
END LOOP;
END IF;
END LOOP;
-- Dumping Bank 2
FOR i IN 0 TO 2**addr_bits -1 LOOP
-- Check if ROW is NULL
IF Bank2 (i) /= NULL THEN
For j IN 0 TO 2**col_bits - 1 LOOP
-- Check if COL is NULL
NEXT WHEN Bank2 (i) (j) (data_bits) = '0';
WRITE (l, string'("10"), right, 4); --'
WRITE (l, To_BitVector(Conv_Std_Logic_Vector(i, addr_bits)), right, addr_bits+1);
WRITE (l, To_BitVector(Conv_std_Logic_Vector(j, col_bits)), right, col_bits+1);
WRITE (l, Bank2 (i) (j) (data_bits -1 DOWNTO 0), right, data_bits+1);
WRITELINE (file_dump, l);
END LOOP;
END IF;
END LOOP;
-- Dumping Bank 3
FOR i IN 0 TO 2**addr_bits -1 LOOP
-- Check if ROW is NULL
IF Bank3 (i) /= NULL THEN
For j IN 0 TO 2**col_bits - 1 LOOP
-- Check if COL is NULL
NEXT WHEN Bank3 (i) (j) (data_bits) = '0';
WRITE (l, string'("11"), right, 4); --'
WRITE (l, To_BitVector(Conv_Std_Logic_Vector(i, addr_bits)), right, addr_bits+1);
WRITE (l, To_BitVector(Conv_std_Logic_Vector(j, col_bits)), right, col_bits+1);
WRITE (l, Bank3 (i) (j) (data_bits -1 DOWNTO 0), right, data_bits+1);
WRITELINE (file_dump, l);
END LOOP;
END IF;
END LOOP;
END IF;
-- Write with AutoPrecharge Calculation
-- The device start internal precharge when:
-- 1. tWR cycles after command
-- and 2. Meet tRAS requirement
-- or 3. Interrupt by a Read or Write (with or without Auto Precharge)
IF ((Auto_precharge(0) = '1') AND (Write_precharge(0) = '1')) THEN
IF (((NOW - RAS_chk0 >= tRAS) AND
(((Burst_length_1 = '1' OR Write_burst_mode = '1' ) AND Count_precharge(0) >= 1 AND NOW - Count_time(0) >= tWRa) OR
(Burst_length_2 = '1' AND Count_precharge(0) >= 2 AND NOW - Count_time(0) >= tWRa) OR
(Burst_length_4 = '1' AND Count_precharge(0) >= 4 AND NOW - Count_time(0) >= tWRa) OR
(Burst_length_8 = '1' AND Count_precharge(0) >= 8 AND NOW - Count_time(0) >= tWRa))) OR
(RW_interrupt_write(0) = '1' AND WR_counter(0) >= 1 AND NOW - WR_time(0) >= tWRa)) THEN
Auto_precharge(0) := '0';
Write_precharge(0) := '0';
RW_interrupt_write(0) := '0';
Pc_b0 := '1';
Act_b0 := '0';
RP_chk0 := NOW;
ASSERT FALSE REPORT "Start Internal Precharge Bank 0" SEVERITY NOTE;
END IF;
END IF;
IF ((Auto_precharge(1) = '1') AND (Write_precharge(1) = '1')) THEN
IF (((NOW - RAS_chk1 >= tRAS) AND
(((Burst_length_1 = '1' OR Write_burst_mode = '1' ) AND Count_precharge(1) >= 1 AND NOW - Count_time(1) >= tWRa) OR
(Burst_length_2 = '1' AND Count_precharge(1) >= 2 AND NOW - Count_time(1) >= tWRa) OR
(Burst_length_4 = '1' AND Count_precharge(1) >= 4 AND NOW - Count_time(1) >= tWRa) OR
(Burst_length_8 = '1' AND Count_precharge(1) >= 8 AND NOW - Count_time(1) >= tWRa))) OR
(RW_interrupt_write(1) = '1' AND WR_counter(1) >= 1 AND NOW - WR_time(1) >= tWRa)) THEN
Auto_precharge(1) := '0';
Write_precharge(1) := '0';
RW_interrupt_write(1) := '0';
Pc_b1 := '1';
Act_b1 := '0';
RP_chk1 := NOW;
END IF;
END IF;
IF ((Auto_precharge(2) = '1') AND (Write_precharge(2) = '1')) THEN
IF (((NOW - RAS_chk2 >= tRAS) AND
(((Burst_length_1 = '1' OR Write_burst_mode = '1' ) AND Count_precharge(2) >= 1 AND NOW - Count_time(2) >= tWRa) OR
(Burst_length_2 = '1' AND Count_precharge(2) >= 2 AND NOW - Count_time(2) >= tWRa) OR
(Burst_length_4 = '1' AND Count_precharge(2) >= 4 AND NOW - Count_time(2) >= tWRa) OR
(Burst_length_8 = '1' AND Count_precharge(2) >= 8 AND NOW - Count_time(2) >= tWRa))) OR
(RW_interrupt_write(2) = '1' AND WR_counter(2) >= 1 AND NOW - WR_time(2) >= tWRa)) THEN
Auto_precharge(2) := '0';
Write_precharge(2) := '0';
RW_interrupt_write(2) := '0';
Pc_b2 := '1';
Act_b2 := '0';
RP_chk2 := NOW;
END IF;
END IF;
IF ((Auto_precharge(3) = '1') AND (Write_precharge(3) = '1')) THEN
IF (((NOW - RAS_chk3 >= tRAS) AND
(((Burst_length_1 = '1' OR Write_burst_mode = '1' ) AND Count_precharge(3) >= 1 AND NOW - Count_time(3) >= tWRa) OR
(Burst_length_2 = '1' AND Count_precharge(3) >= 2 AND NOW - Count_time(3) >= tWRa) OR
(Burst_length_4 = '1' AND Count_precharge(3) >= 4 AND NOW - Count_time(3) >= tWRa) OR
(Burst_length_8 = '1' AND Count_precharge(3) >= 8 AND NOW - Count_time(3) >= tWRa))) OR
(RW_interrupt_write(0) = '1' AND WR_counter(0) >= 1 AND NOW - WR_time(3) >= tWRa)) THEN
Auto_precharge(3) := '0';
Write_precharge(3) := '0';
RW_interrupt_write(3) := '0';
Pc_b3 := '1';
Act_b3 := '0';
RP_chk3 := NOW;
END IF;
END IF;
-- Checking internal wires (Optional for debug purpose)
Pre_chk (0) <= Pc_b0;
Pre_chk (1) <= Pc_b1;
Pre_chk (2) <= Pc_b2;
Pre_chk (3) <= Pc_b3;
Act_chk (0) <= Act_b0;
Act_chk (1) <= Act_b1;
Act_chk (2) <= Act_b2;
Act_chk (3) <= Act_b3;
Dq_in_chk <= Data_in_enable;
Dq_out_chk <= Data_out_enable;
Bank_chk <= Bank;
Row_chk <= Row;
Col_chk <= Col;
END PROCESS;
-- Clock timing checks
-- Clock_check : PROCESS
-- VARIABLE Clk_low, Clk_high : TIME := 0 ns;
-- BEGIN
-- WAIT ON Clk;
-- IF (Clk = '1' AND NOW >= 10 ns) THEN
-- ASSERT (NOW - Clk_low >= tCL)
-- REPORT "tCL violation"
-- SEVERITY WARNING;
-- ASSERT (NOW - Clk_high >= tCK)
-- REPORT "tCK violation"
-- SEVERITY WARNING;
-- Clk_high := NOW;
-- ELSIF (Clk = '0' AND NOW /= 0 ns) THEN
-- ASSERT (NOW - Clk_high >= tCH)
-- REPORT "tCH violation"
-- SEVERITY WARNING;
-- Clk_low := NOW;
-- END IF;
-- END PROCESS;
-- Setup timing checks
Setup_check : PROCESS
BEGIN
wait;
WAIT ON Clk;
IF Clk = '1' THEN
ASSERT(Cke'LAST_EVENT >= tCKS) --'
REPORT "CKE Setup time violation -- tCKS"
SEVERITY WARNING;
ASSERT(Cs_n'LAST_EVENT >= tCMS) --'
REPORT "CS# Setup time violation -- tCMS"
SEVERITY WARNING;
ASSERT(Cas_n'LAST_EVENT >= tCMS) --'
REPORT "CAS# Setup time violation -- tCMS"
SEVERITY WARNING;
ASSERT(Ras_n'LAST_EVENT >= tCMS) --'
REPORT "RAS# Setup time violation -- tCMS"
SEVERITY WARNING;
ASSERT(We_n'LAST_EVENT >= tCMS) --'
REPORT "WE# Setup time violation -- tCMS"
SEVERITY WARNING;
ASSERT(Dqm'LAST_EVENT >= tCMS) --'
REPORT "Dqm Setup time violation -- tCMS"
SEVERITY WARNING;
ASSERT(Addr'LAST_EVENT >= tAS) --'
REPORT "ADDR Setup time violation -- tAS"
SEVERITY WARNING;
ASSERT(Ba'LAST_EVENT >= tAS) --'
REPORT "BA Setup time violation -- tAS"
SEVERITY WARNING;
ASSERT(Dq'LAST_EVENT >= tDS) --'
REPORT "Dq Setup time violation -- tDS"
SEVERITY WARNING;
END IF;
END PROCESS;
-- Hold timing checks
Hold_check : PROCESS
BEGIN
wait;
WAIT ON Clk'DELAYED (tCKH), Clk'DELAYED (tCMH), Clk'DELAYED (tAH), Clk'DELAYED (tDH);
IF Clk'DELAYED (tCKH) = '1' THEN --'
ASSERT(Cke'LAST_EVENT > tCKH) --'
REPORT "CKE Hold time violation -- tCKH"
SEVERITY WARNING;
END IF;
IF Clk'DELAYED (tCMH) = '1' THEN --'
ASSERT(Cs_n'LAST_EVENT > tCMH) --'
REPORT "CS# Hold time violation -- tCMH"
SEVERITY WARNING;
ASSERT(Cas_n'LAST_EVENT > tCMH) --'
REPORT "CAS# Hold time violation -- tCMH"
SEVERITY WARNING;
ASSERT(Ras_n'LAST_EVENT > tCMH) --'
REPORT "RAS# Hold time violation -- tCMH"
SEVERITY WARNING;
ASSERT(We_n'LAST_EVENT > tCMH) --'
REPORT "WE# Hold time violation -- tCMH"
SEVERITY WARNING;
ASSERT(Dqm'LAST_EVENT > tCMH) --'
REPORT "Dqm Hold time violation -- tCMH"
SEVERITY WARNING;
END IF;
IF Clk'DELAYED (tAH) = '1' THEN --'
ASSERT(Addr'LAST_EVENT > tAH) --'
REPORT "ADDR Hold time violation -- tAH"
SEVERITY WARNING;
ASSERT(Ba'LAST_EVENT > tAH) --'
REPORT "BA Hold time violation -- tAH"
SEVERITY WARNING;
END IF;
IF Clk'DELAYED (tDH) = '1' THEN --'
ASSERT(Dq'LAST_EVENT > tDH) --'
REPORT "Dq Hold time violation -- tDH"
SEVERITY WARNING;
END IF;
END PROCESS;
END behave;
-- pragma translate_on
|
mit
|
impedimentToProgress/UCI-BlueChip
|
AttackFiles/Attacks/privEsc/lib/tech/dw02/comp/DW02_components.vhd
|
2
|
1603
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
package DW02_components is
component DW02_mult_2_stage
generic( A_width: POSITIVE; -- multiplier wordlength
B_width: POSITIVE); -- multiplicand wordlength
port(A : in std_logic_vector(A_width-1 downto 0);
B : in std_logic_vector(B_width-1 downto 0);
TC : in std_logic; -- signed -> '1', unsigned -> '0'
CLK : in std_logic; -- clock for the stage registers.
PRODUCT : out std_logic_vector(A_width+B_width-1 downto 0));
end component;
end DW02_components;
-- pragma translate_off
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library grlib;
use grlib.stdlib.all;
entity DW02_mult_2_stage is
generic( A_width: POSITIVE;
B_width: POSITIVE);
port(A : in std_logic_vector(A_width-1 downto 0);
B : in std_logic_vector(B_width-1 downto 0);
TC : in std_logic;
CLK : in std_logic;
PRODUCT : out std_logic_vector(A_width+B_width-1 downto 0));
end;
architecture behav of DW02_mult_2_stage is
signal P_i : std_logic_vector(A_width+B_width-1 downto 0);
begin
comb : process(A, B, TC)
begin
if notx(A) and notx(B) then
if TC = '1' then
P_i <= signed(A) * signed(B);
else
P_i <= unsigned(A) * unsigned(B);
end if;
else
P_i <= (others => 'X');
end if;
end process;
reg : process(CLK)
begin
if rising_edge(CLK) then
PRODUCT <= P_i;
end if;
end process;
end;
-- pragma translate_on
|
mit
|
impedimentToProgress/UCI-BlueChip
|
AttackFiles/Attacks/privEsc/lib/techmap/unisim/buffer_unisim.vhd
|
2
|
2801
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: clkbuf_xilinx
-- File: clkbuf_xilinx.vhd
-- Author: Marko Isomaki, Jiri GAisler - Gaisler Research
-- Description: Clock buffer generator for Xilinx devices
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.BUFGMUX;
use unisim.BUFG;
use unisim.BUFGDLL;
-- pragma translate_on
entity clkbuf_xilinx is
generic(
buftype : integer range 0 to 3 := 0);
port(
i : in std_ulogic;
o : out std_ulogic
);
end entity;
architecture rtl of clkbuf_xilinx is
component BUFGDLL port (O : out std_logic; I : in std_logic); end component;
component BUFGMUX port (O : out std_logic; I0, I1, S : in std_logic); end component;
component BUFG port (O : out std_logic; I : in std_logic); end component;
signal gnd : std_ulogic;
signal x : std_ulogic;
attribute syn_noclockbuf : boolean;
attribute syn_noclockbuf of x : signal is true;
begin
gnd <= '0';
buf0 : if (buftype = 0) or (buftype > 2) generate
x <= i; o <= x;
end generate;
buf1 : if buftype = 1 generate
buf : bufgmux port map(S => gnd, I0 => i, I1 => gnd, O => o);
end generate;
buf2 : if (buftype = 2) generate
buf : bufg port map(I => i, O => o);
end generate;
end architecture;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.BUFGMUX;
-- pragma translate_on
entity clkmux_xilinx is
port(
i0, i1 : in std_ulogic;
sel : in std_ulogic;
o : out std_ulogic
);
end entity;
architecture rtl of clkmux_xilinx is
component BUFGMUX port (O : out std_logic; I0, I1, S : in std_logic); end component;
begin
buf : bufgmux port map(S => sel, I0 => i0, I1 => i1, O => o);
end architecture;
|
mit
|
impedimentToProgress/UCI-BlueChip
|
VhdlParser/test/resultPrivEscMux.vhd
|
1
|
131740
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
LIBRARY grlib;
USE grlib.sparc.all;
USE grlib.stdlib.all;
LIBRARY techmap;
USE techmap.gencomp.all;
LIBRARY gaisler;
USE gaisler.leon3.all;
USE gaisler.libiu.all;
USE gaisler.arith.all;
USE grlib.sparc_disas.all;
ENTITY iu3 IS
GENERIC (
nwin : integer RANGE 2 to 32 := 8;
isets : integer RANGE 1 to 4 := 2;
dsets : integer RANGE 1 to 4 := 2;
fpu : integer RANGE 0 to 15 := 0;
v8 : integer RANGE 0 to 63 := 2;
cp : integer RANGE 0 to 1 := 0;
mac : integer RANGE 0 to 1 := 0;
dsu : integer RANGE 0 to 1 := 1;
nwp : integer RANGE 0 to 4 := 2;
pclow : integer RANGE 0 to 2 := 2;
notag : integer RANGE 0 to 1 := 0;
index : integer RANGE 0 to 15 := 0;
lddel : integer RANGE 1 to 2 := 1;
irfwt : integer RANGE 0 to 1 := 1;
disas : integer RANGE 0 to 2 := 0;
tbuf : integer RANGE 0 to 64 := 2;
pwd : integer RANGE 0 to 2 := 0;
svt : integer RANGE 0 to 1 := 1;
rstaddr : integer := 16#00000#;
smp : integer RANGE 0 to 15 := 0;
fabtech : integer RANGE 0 to NTECH := 2;
clk2x : integer := 0
);
PORT (
clk : in std_ulogic;
rstn : in std_ulogic;
holdn : in std_ulogic;
ici : out icache_in_type;
ico : in icache_out_type;
dci : out dcache_in_type;
dco : in dcache_out_type;
rfi : out iregfile_in_type;
rfo : in iregfile_out_type;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type;
muli : out mul32_in_type;
mulo : in mul32_out_type;
divi : out div32_in_type;
divo : in div32_out_type;
fpo : in fpc_out_type;
fpi : out fpc_in_type;
cpo : in fpc_out_type;
cpi : out fpc_in_type;
tbo : in tracebuf_out_type;
tbi : out tracebuf_in_type;
sclk : in std_ulogic
);
END ENTITY;
ARCHITECTURE rtl OF iu3 IS
CONSTANT ISETMSB : integer := 0;
CONSTANT DSETMSB : integer := 0;
CONSTANT RFBITS : integer RANGE 6 to 10 := 4 + 4;
CONSTANT NWINLOG2 : integer RANGE 1 to 5 := 3;
CONSTANT CWPOPT : boolean := ( 8 = ( 2 ** 3 ) );
CONSTANT CWPMIN : std_logic_vector ( 3 - 1 downto 0 ) := ( OTHERS => '0' );
CONSTANT CWPMAX : std_logic_vector ( 3 - 1 downto 0 ) := conv_std_logic_vector ( 8 - 1 , 3 );
CONSTANT FPEN : boolean := ( 0 /= 0 );
CONSTANT CPEN : boolean := ( 0 = 1 );
CONSTANT MULEN : boolean := ( 2 /= 0 );
CONSTANT MULTYPE : integer := ( 2 / 16 );
CONSTANT DIVEN : boolean := ( 2 /= 0 );
CONSTANT MACEN : boolean := ( 0 = 1 );
CONSTANT MACPIPE : boolean := ( 0 = 1 ) and ( 2 / 2 = 1 );
CONSTANT IMPL : integer := 15;
CONSTANT VER : integer := 3;
CONSTANT DBGUNIT : boolean := ( 1 = 1 );
CONSTANT TRACEBUF : boolean := ( 2 /= 0 );
CONSTANT TBUFBITS : integer := 10 + 1 - 4;
CONSTANT PWRD1 : boolean := false;
CONSTANT PWRD2 : boolean := 0 /= 0;
CONSTANT RS1OPT : boolean := ( 1 /= 0 );
SUBTYPE word IS std_logic_vector ( 31 downto 0 );
SUBTYPE pctype IS std_logic_vector ( 31 downto 2 );
SUBTYPE rfatype IS std_logic_vector ( 7 downto 0 );
SUBTYPE cwptype IS std_logic_vector ( 3 - 1 downto 0 );
TYPE icdtype IS ARRAY ( 0 to 2 - 1 ) OF word;
TYPE dcdtype IS ARRAY ( 0 to 2 - 1 ) OF word;
TYPE dc_in_type IS RECORD
signed : std_ulogic;
enaddr : std_ulogic;
read : std_ulogic;
write : std_ulogic;
lock : std_ulogic;
dsuen : std_ulogic;
size : std_logic_vector ( 1 downto 0 );
asi : std_logic_vector ( 7 downto 0 );
END RECORD;
TYPE pipeline_ctrl_type IS RECORD
pc : pctype;
inst : word;
cnt : std_logic_vector ( 1 downto 0 );
rd : rfatype;
tt : std_logic_vector ( 5 downto 0 );
trap : std_ulogic;
annul : std_ulogic;
wreg : std_ulogic;
wicc : std_ulogic;
wy : std_ulogic;
ld : std_ulogic;
pv : std_ulogic;
rett : std_ulogic;
END RECORD;
TYPE fetch_reg_type IS RECORD
pc : pctype;
branch : std_ulogic;
END RECORD;
TYPE decode_reg_type IS RECORD
pc : pctype;
inst : icdtype;
cwp : cwptype;
set : std_logic_vector ( 0 downto 0 );
mexc : std_ulogic;
cnt : std_logic_vector ( 1 downto 0 );
pv : std_ulogic;
annul : std_ulogic;
inull : std_ulogic;
step : std_ulogic;
END RECORD;
TYPE regacc_reg_type IS RECORD
ctrl : pipeline_ctrl_type;
rs1 : std_logic_vector ( 4 downto 0 );
rfa1 : rfatype;
rfa2 : rfatype;
rsel1 : std_logic_vector ( 2 downto 0 );
rsel2 : std_logic_vector ( 2 downto 0 );
rfe1 : std_ulogic;
rfe2 : std_ulogic;
cwp : cwptype;
imm : word;
ldcheck1 : std_ulogic;
ldcheck2 : std_ulogic;
ldchkra : std_ulogic;
ldchkex : std_ulogic;
su : std_ulogic;
et : std_ulogic;
wovf : std_ulogic;
wunf : std_ulogic;
ticc : std_ulogic;
jmpl : std_ulogic;
step : std_ulogic;
mulstart : std_ulogic;
divstart : std_ulogic;
END RECORD;
TYPE execute_reg_type IS RECORD
ctrl : pipeline_ctrl_type;
op1 : word;
op2 : word;
aluop : std_logic_vector ( 2 downto 0 );
alusel : std_logic_vector ( 1 downto 0 );
aluadd : std_ulogic;
alucin : std_ulogic;
ldbp1 : std_ulogic;
ldbp2 : std_ulogic;
invop2 : std_ulogic;
shcnt : std_logic_vector ( 4 downto 0 );
sari : std_ulogic;
shleft : std_ulogic;
ymsb : std_ulogic;
rd : std_logic_vector ( 4 downto 0 );
jmpl : std_ulogic;
su : std_ulogic;
et : std_ulogic;
cwp : cwptype;
icc : std_logic_vector ( 3 downto 0 );
mulstep : std_ulogic;
mul : std_ulogic;
mac : std_ulogic;
END RECORD;
TYPE memory_reg_type IS RECORD
ctrl : pipeline_ctrl_type;
result : word;
y : word;
icc : std_logic_vector ( 3 downto 0 );
nalign : std_ulogic;
dci : dc_in_type;
werr : std_ulogic;
wcwp : std_ulogic;
irqen : std_ulogic;
irqen2 : std_ulogic;
mac : std_ulogic;
divz : std_ulogic;
su : std_ulogic;
mul : std_ulogic;
END RECORD;
TYPE exception_state IS ( run , trap , dsu1 , dsu2 );
TYPE exception_reg_type IS RECORD
ctrl : pipeline_ctrl_type;
result : word;
y : word;
icc : std_logic_vector ( 3 downto 0 );
annul_all : std_ulogic;
data : dcdtype;
set : std_logic_vector ( 0 downto 0 );
mexc : std_ulogic;
dci : dc_in_type;
laddr : std_logic_vector ( 1 downto 0 );
rstate : exception_state;
npc : std_logic_vector ( 2 downto 0 );
intack : std_ulogic;
ipend : std_ulogic;
mac : std_ulogic;
debug : std_ulogic;
nerror : std_ulogic;
END RECORD;
TYPE dsu_registers IS RECORD
tt : std_logic_vector ( 7 downto 0 );
err : std_ulogic;
tbufcnt : std_logic_vector ( 10 + 1 - 4 - 1 downto 0 );
asi : std_logic_vector ( 7 downto 0 );
crdy : std_logic_vector ( 2 downto 1 );
END RECORD;
TYPE irestart_register IS RECORD
addr : pctype;
pwd : std_ulogic;
END RECORD;
TYPE pwd_register_type IS RECORD
pwd : std_ulogic;
error : std_ulogic;
END RECORD;
TYPE special_register_type IS RECORD
cwp : cwptype;
icc : std_logic_vector ( 3 downto 0 );
tt : std_logic_vector ( 7 downto 0 );
tba : std_logic_vector ( 19 downto 0 );
wim : std_logic_vector ( 8 - 1 downto 0 );
pil : std_logic_vector ( 3 downto 0 );
ec : std_ulogic;
ef : std_ulogic;
ps : std_ulogic;
s : std_ulogic;
et : std_ulogic;
y : word;
asr18 : word;
svt : std_ulogic;
dwt : std_ulogic;
END RECORD;
TYPE write_reg_type IS RECORD
s : special_register_type;
result : word;
wa : rfatype;
wreg : std_ulogic;
except : std_ulogic;
END RECORD;
TYPE registers IS RECORD
f : fetch_reg_type;
d : decode_reg_type;
a : regacc_reg_type;
e : execute_reg_type;
m : memory_reg_type;
x : exception_reg_type;
w : write_reg_type;
END RECORD;
TYPE exception_type IS RECORD
pri : std_ulogic;
ill : std_ulogic;
fpdis : std_ulogic;
cpdis : std_ulogic;
wovf : std_ulogic;
wunf : std_ulogic;
ticc : std_ulogic;
END RECORD;
TYPE watchpoint_register IS RECORD
addr : std_logic_vector ( 31 downto 2 );
mask : std_logic_vector ( 31 downto 2 );
exec : std_ulogic;
load : std_ulogic;
store : std_ulogic;
END RECORD;
TYPE watchpoint_registers IS ARRAY ( 0 to 3 ) OF watchpoint_register;
CONSTANT wpr_none : watchpoint_register := ( "000000000000000000000000000000" , "000000000000000000000000000000" , '0' , '0' , '0' );
FUNCTION dbgexc (
r : registers;
dbgi : l3_debug_in_type;
trap : std_ulogic;
tt : std_logic_vector ( 7 downto 0 )
) RETURN std_ulogic IS
VARIABLE dmode : std_ulogic;
BEGIN
dmode := '0';
IF ( not r.x.ctrl.annul and trap ) = '1' THEN
IF ( ( ( tt = "00" & TT_WATCH ) and ( dbgi.bwatch = '1' ) ) or ( ( dbgi.bsoft = '1' ) and ( tt = "10000001" ) ) or ( dbgi.btrapa = '1' ) or ( ( dbgi.btrape = '1' ) and not ( ( tt ( 5 downto 0 ) = TT_PRIV ) or ( tt ( 5 downto 0 ) = TT_FPDIS ) or ( tt ( 5 downto 0 ) = TT_WINOF ) or ( tt ( 5 downto 0 ) = TT_WINUF ) or ( tt ( 5 downto 4 ) = "01" ) or ( tt ( 7 ) = '1' ) ) ) or ( ( ( not r.w.s.et ) and dbgi.berror ) = '1' ) ) THEN
dmode := '1';
END IF;
END IF;
RETURN ( dmode );
END;
FUNCTION dbgerr (
r : registers;
dbgi : l3_debug_in_type;
tt : std_logic_vector ( 7 downto 0 )
) RETURN std_ulogic IS
VARIABLE err : std_ulogic;
BEGIN
err := not r.w.s.et;
IF ( ( ( dbgi.dbreak = '1' ) and ( tt = ( "00" & TT_WATCH ) ) ) or ( ( dbgi.bsoft = '1' ) and ( tt = ( "10000001" ) ) ) ) THEN
err := '0';
END IF;
RETURN ( err );
END;
PROCEDURE diagwr (
r : in registers;
dsur : in dsu_registers;
ir : in irestart_register;
dbg : in l3_debug_in_type;
wpr : in watchpoint_registers;
s : out special_register_type;
vwpr : out watchpoint_registers;
asi : out std_logic_vector ( 7 downto 0 );
pc : out pctype;
npc : out pctype;
tbufcnt : out std_logic_vector ( 10 + 1 - 4 - 1 downto 0 );
wr : out std_ulogic;
addr : out std_logic_vector ( 9 downto 0 );
data : out word;
fpcwr : out std_ulogic
) IS
VARIABLE i : integer RANGE 0 to 3;
BEGIN
s := r.w.s;
pc := r.f.pc;
npc := ir.addr;
wr := '0';
vwpr := wpr;
asi := dsur.asi;
addr := ( OTHERS => '0' );
data := dbg.ddata;
tbufcnt := dsur.tbufcnt;
fpcwr := '0';
IF ( dbg.dsuen and dbg.denable and dbg.dwrite ) = '1' THEN
CASE dbg.daddr ( 23 downto 20 ) IS
WHEN "0001" =>
IF dbg.daddr ( 16 ) = '1' THEN
tbufcnt := dbg.ddata ( 10 + 1 - 4 - 1 downto 0 );
END IF;
WHEN "0011" =>
IF dbg.daddr ( 12 ) = '0' THEN
wr := '1';
addr := ( OTHERS => '0' );
addr ( 7 downto 0 ) := dbg.daddr ( 9 downto 2 );
ELSE
fpcwr := '1';
END IF;
WHEN "0100" =>
CASE dbg.daddr ( 7 downto 6 ) IS
WHEN "00" =>
CASE dbg.daddr ( 5 downto 2 ) IS
WHEN "0000" =>
s.y := dbg.ddata;
WHEN "0001" =>
s.cwp := dbg.ddata ( 3 - 1 downto 0 );
s.icc := dbg.ddata ( 23 downto 20 );
s.ec := dbg.ddata ( 13 );
s.pil := dbg.ddata ( 11 downto 8 );
s.s := dbg.ddata ( 7 );
s.ps := dbg.ddata ( 6 );
s.et := dbg.ddata ( 5 );
WHEN "0010" =>
s.wim := dbg.ddata ( 8 - 1 downto 0 );
WHEN "0011" =>
s.tba := dbg.ddata ( 31 downto 12 );
s.tt := dbg.ddata ( 11 downto 4 );
WHEN "0100" =>
pc := dbg.ddata ( 31 downto 2 );
WHEN "0101" =>
npc := dbg.ddata ( 31 downto 2 );
WHEN "0110" =>
fpcwr := '1';
WHEN "0111" =>
NULL;
WHEN "1001" =>
asi := dbg.ddata ( 7 downto 0 );
WHEN OTHERS =>
NULL;
END CASE;
WHEN "01" =>
CASE dbg.daddr ( 5 downto 2 ) IS
WHEN "0001" =>
s.dwt := dbg.ddata ( 14 );
s.svt := dbg.ddata ( 13 );
WHEN "0010" =>
NULL;
WHEN "1000" =>
vwpr ( 0 ).addr := dbg.ddata ( 31 downto 2 );
vwpr ( 0 ).exec := dbg.ddata ( 0 );
WHEN "1001" =>
vwpr ( 0 ).mask := dbg.ddata ( 31 downto 2 );
vwpr ( 0 ).load := dbg.ddata ( 1 );
vwpr ( 0 ).store := dbg.ddata ( 0 );
WHEN "1010" =>
vwpr ( 1 ).addr := dbg.ddata ( 31 downto 2 );
vwpr ( 1 ).exec := dbg.ddata ( 0 );
WHEN "1011" =>
vwpr ( 1 ).mask := dbg.ddata ( 31 downto 2 );
vwpr ( 1 ).load := dbg.ddata ( 1 );
vwpr ( 1 ).store := dbg.ddata ( 0 );
WHEN "1100" =>
vwpr ( 2 ).addr := dbg.ddata ( 31 downto 2 );
vwpr ( 2 ).exec := dbg.ddata ( 0 );
WHEN "1101" =>
vwpr ( 2 ).mask := dbg.ddata ( 31 downto 2 );
vwpr ( 2 ).load := dbg.ddata ( 1 );
vwpr ( 2 ).store := dbg.ddata ( 0 );
WHEN "1110" =>
vwpr ( 3 ).addr := dbg.ddata ( 31 downto 2 );
vwpr ( 3 ).exec := dbg.ddata ( 0 );
WHEN "1111" =>
vwpr ( 3 ).mask := dbg.ddata ( 31 downto 2 );
vwpr ( 3 ).load := dbg.ddata ( 1 );
vwpr ( 3 ).store := dbg.ddata ( 0 );
WHEN OTHERS =>
NULL;
END CASE;
WHEN OTHERS =>
NULL;
END CASE;
WHEN OTHERS =>
NULL;
END CASE;
END IF;
END;
FUNCTION asr17_gen (
r : in registers
) RETURN word IS
VARIABLE asr17 : word;
VARIABLE fpu2 : integer RANGE 0 to 3;
BEGIN
asr17 := "00000000000000000000000000000000";
asr17 ( 31 downto 28 ) := conv_std_logic_vector ( 0 , 4 );
asr17 ( 14 ) := r.w.s.dwt;
asr17 ( 13 ) := r.w.s.svt;
fpu2 := 0;
asr17 ( 11 downto 10 ) := conv_std_logic_vector ( fpu2 , 2 );
asr17 ( 8 ) := '1';
asr17 ( 7 downto 5 ) := conv_std_logic_vector ( 2 , 3 );
asr17 ( 4 downto 0 ) := conv_std_logic_vector ( 8 - 1 , 5 );
RETURN ( asr17 );
END;
PROCEDURE diagread (
dbgi : in l3_debug_in_type;
r : in registers;
dsur : in dsu_registers;
ir : in irestart_register;
wpr : in watchpoint_registers;
rfdata : in std_logic_vector ( 31 downto 0 );
dco : in dcache_out_type;
tbufo : in tracebuf_out_type;
data : out word
) IS
VARIABLE cwp : std_logic_vector ( 4 downto 0 );
VARIABLE rd : std_logic_vector ( 4 downto 0 );
VARIABLE i : integer RANGE 0 to 3;
BEGIN
data := ( OTHERS => '0' );
cwp := ( OTHERS => '0' );
cwp ( 3 - 1 downto 0 ) := r.w.s.cwp;
CASE dbgi.daddr ( 22 downto 20 ) IS
WHEN "001" =>
IF dbgi.daddr ( 16 ) = '1' THEN
data ( 10 + 1 - 4 - 1 downto 0 ) := dsur.tbufcnt;
ELSE
CASE dbgi.daddr ( 3 downto 2 ) IS
WHEN "00" =>
data := tbufo.data ( 127 downto 96 );
WHEN "01" =>
data := tbufo.data ( 95 downto 64 );
WHEN "10" =>
data := tbufo.data ( 63 downto 32 );
WHEN OTHERS =>
data := tbufo.data ( 31 downto 0 );
END CASE;
END IF;
WHEN "011" =>
IF dbgi.daddr ( 12 ) = '0' THEN
data := rfdata ( 31 downto 0 );
ELSE
data := fpo.dbg.data;
END IF;
WHEN "100" =>
CASE dbgi.daddr ( 7 downto 6 ) IS
WHEN "00" =>
CASE dbgi.daddr ( 5 downto 2 ) IS
WHEN "0000" =>
data := r.w.s.y;
WHEN "0001" =>
data := conv_std_logic_vector ( 15 , 4 ) & conv_std_logic_vector ( 3 , 4 ) & r.w.s.icc & "000000" & r.w.s.ec & r.w.s.ef & r.w.s.pil & r.w.s.s & r.w.s.ps & r.w.s.et & cwp;
WHEN "0010" =>
data ( 8 - 1 downto 0 ) := r.w.s.wim;
WHEN "0011" =>
data := r.w.s.tba & r.w.s.tt & "0000";
WHEN "0100" =>
data ( 31 downto 2 ) := r.f.pc;
WHEN "0101" =>
data ( 31 downto 2 ) := ir.addr;
WHEN "0110" =>
data := fpo.dbg.data;
WHEN "0111" =>
NULL;
WHEN "1000" =>
data ( 12 downto 4 ) := dsur.err & dsur.tt;
WHEN "1001" =>
data ( 7 downto 0 ) := dsur.asi;
WHEN OTHERS =>
NULL;
END CASE;
WHEN "01" =>
IF dbgi.daddr ( 5 ) = '0' THEN
IF dbgi.daddr ( 4 downto 2 ) = "001" THEN
data := asr17_gen ( r );
END IF;
ELSE
i := conv_integer ( dbgi.daddr ( 4 downto 3 ) );
IF dbgi.daddr ( 2 ) = '0' THEN
data ( 31 downto 2 ) := wpr ( i ).addr;
data ( 0 ) := wpr ( i ).exec;
ELSE
data ( 31 downto 2 ) := wpr ( i ).mask;
data ( 1 ) := wpr ( i ).load;
data ( 0 ) := wpr ( i ).store;
END IF;
END IF;
WHEN OTHERS =>
NULL;
END CASE;
WHEN "111" =>
data := r.x.data ( conv_integer ( r.x.set ) );
WHEN OTHERS =>
NULL;
END CASE;
END;
PROCEDURE itrace (
r : in registers;
dsur : in dsu_registers;
vdsu : in dsu_registers;
res : in word;
exc : in std_ulogic;
dbgi : in l3_debug_in_type;
error : in std_ulogic;
trap : in std_ulogic;
tbufcnt : out std_logic_vector ( 10 + 1 - 4 - 1 downto 0 );
di : out tracebuf_in_type
) IS
VARIABLE meminst : std_ulogic;
BEGIN
di.addr := ( OTHERS => '0' );
di.data := ( OTHERS => '0' );
di.enable := '0';
di.write := ( OTHERS => '0' );
tbufcnt := vdsu.tbufcnt;
meminst := r.x.ctrl.inst ( 31 ) and r.x.ctrl.inst ( 30 );
di.addr ( 10 + 1 - 4 - 1 downto 0 ) := dsur.tbufcnt;
di.data ( 127 ) := '0';
di.data ( 126 ) := not r.x.ctrl.pv;
di.data ( 125 downto 96 ) := dbgi.timer ( 29 downto 0 );
di.data ( 95 downto 64 ) := res;
di.data ( 63 downto 34 ) := r.x.ctrl.pc ( 31 downto 2 );
di.data ( 33 ) := trap;
di.data ( 32 ) := error;
di.data ( 31 downto 0 ) := r.x.ctrl.inst;
IF ( dbgi.tenable = '0' ) or ( r.x.rstate = dsu2 ) THEN
IF ( ( dbgi.dsuen and dbgi.denable ) = '1' ) and ( dbgi.daddr ( 23 downto 20 ) & dbgi.daddr ( 16 ) = "00010" ) THEN
di.enable := '1';
di.addr ( 10 + 1 - 4 - 1 downto 0 ) := dbgi.daddr ( 10 + 1 - 4 - 1 + 4 downto 4 );
IF dbgi.dwrite = '1' THEN
CASE dbgi.daddr ( 3 downto 2 ) IS
WHEN "00" =>
di.write ( 3 ) := '1';
WHEN "01" =>
di.write ( 2 ) := '1';
WHEN "10" =>
di.write ( 1 ) := '1';
WHEN OTHERS =>
di.write ( 0 ) := '1';
END CASE;
di.data := dbgi.ddata & dbgi.ddata & dbgi.ddata & dbgi.ddata;
END IF;
END IF;
ELSIF ( not r.x.ctrl.annul and ( r.x.ctrl.pv or meminst ) and not r.x.debug ) = '1' THEN
di.enable := '1';
di.write := ( OTHERS => '1' );
tbufcnt := dsur.tbufcnt + 1;
END IF;
di.diag := dco.testen & "000";
IF dco.scanen = '1' THEN
di.enable := '0';
END IF;
END;
PROCEDURE dbg_cache (
holdn : in std_ulogic;
dbgi : in l3_debug_in_type;
r : in registers;
dsur : in dsu_registers;
mresult : in word;
dci : in dc_in_type;
mresult2 : out word;
dci2 : out dc_in_type
) IS
BEGIN
mresult2 := mresult;
dci2 := dci;
dci2.dsuen := '0';
IF r.x.rstate = dsu2 THEN
dci2.asi := dsur.asi;
IF ( dbgi.daddr ( 22 downto 20 ) = "111" ) and ( dbgi.dsuen = '1' ) THEN
dci2.dsuen := ( dbgi.denable or r.m.dci.dsuen ) and not dsur.crdy ( 2 );
dci2.enaddr := dbgi.denable;
dci2.size := "10";
dci2.read := '1';
dci2.write := '0';
IF ( dbgi.denable and not r.m.dci.enaddr ) = '1' THEN
mresult2 := ( OTHERS => '0' );
mresult2 ( 19 downto 2 ) := dbgi.daddr ( 19 downto 2 );
ELSE
mresult2 := dbgi.ddata;
END IF;
IF dbgi.dwrite = '1' THEN
dci2.read := '0';
dci2.write := '1';
END IF;
END IF;
END IF;
END;
PROCEDURE fpexack (
r : in registers;
fpexc : out std_ulogic
) IS
BEGIN
fpexc := '0';
END;
PROCEDURE diagrdy (
denable : in std_ulogic;
dsur : in dsu_registers;
dci : in dc_in_type;
mds : in std_ulogic;
ico : in icache_out_type;
crdy : out std_logic_vector ( 2 downto 1 )
) IS
BEGIN
crdy := dsur.crdy ( 1 ) & '0';
IF dci.dsuen = '1' THEN
CASE dsur.asi ( 4 downto 0 ) IS
WHEN ASI_ITAG | ASI_IDATA | ASI_UINST | ASI_SINST =>
crdy ( 2 ) := ico.diagrdy and not dsur.crdy ( 2 );
WHEN ASI_DTAG | ASI_MMUSNOOP_DTAG | ASI_DDATA | ASI_UDATA | ASI_SDATA =>
crdy ( 1 ) := not denable and dci.enaddr and not dsur.crdy ( 1 );
WHEN OTHERS =>
crdy ( 2 ) := dci.enaddr and denable;
END CASE;
END IF;
END;
SIGNAL r : registers;
SIGNAL rin : registers;
SIGNAL wpr : watchpoint_registers;
SIGNAL wprin : watchpoint_registers;
SIGNAL dsur : dsu_registers;
SIGNAL dsuin : dsu_registers;
SIGNAL ir : irestart_register;
SIGNAL irin : irestart_register;
SIGNAL rp : pwd_register_type;
SIGNAL rpin : pwd_register_type;
SIGNAL hackStateM1 : std_logic;
CONSTANT EXE_AND : std_logic_vector ( 2 downto 0 ) := "000";
CONSTANT EXE_XOR : std_logic_vector ( 2 downto 0 ) := "001";
CONSTANT EXE_OR : std_logic_vector ( 2 downto 0 ) := "010";
CONSTANT EXE_XNOR : std_logic_vector ( 2 downto 0 ) := "011";
CONSTANT EXE_ANDN : std_logic_vector ( 2 downto 0 ) := "100";
CONSTANT EXE_ORN : std_logic_vector ( 2 downto 0 ) := "101";
CONSTANT EXE_DIV : std_logic_vector ( 2 downto 0 ) := "110";
CONSTANT EXE_PASS1 : std_logic_vector ( 2 downto 0 ) := "000";
CONSTANT EXE_PASS2 : std_logic_vector ( 2 downto 0 ) := "001";
CONSTANT EXE_STB : std_logic_vector ( 2 downto 0 ) := "010";
CONSTANT EXE_STH : std_logic_vector ( 2 downto 0 ) := "011";
CONSTANT EXE_ONES : std_logic_vector ( 2 downto 0 ) := "100";
CONSTANT EXE_RDY : std_logic_vector ( 2 downto 0 ) := "101";
CONSTANT EXE_SPR : std_logic_vector ( 2 downto 0 ) := "110";
CONSTANT EXE_LINK : std_logic_vector ( 2 downto 0 ) := "111";
CONSTANT EXE_SLL : std_logic_vector ( 2 downto 0 ) := "001";
CONSTANT EXE_SRL : std_logic_vector ( 2 downto 0 ) := "010";
CONSTANT EXE_SRA : std_logic_vector ( 2 downto 0 ) := "100";
CONSTANT EXE_NOP : std_logic_vector ( 2 downto 0 ) := "000";
CONSTANT EXE_RES_ADD : std_logic_vector ( 1 downto 0 ) := "00";
CONSTANT EXE_RES_SHIFT : std_logic_vector ( 1 downto 0 ) := "01";
CONSTANT EXE_RES_LOGIC : std_logic_vector ( 1 downto 0 ) := "10";
CONSTANT EXE_RES_MISC : std_logic_vector ( 1 downto 0 ) := "11";
CONSTANT SZBYTE : std_logic_vector ( 1 downto 0 ) := "00";
CONSTANT SZHALF : std_logic_vector ( 1 downto 0 ) := "01";
CONSTANT SZWORD : std_logic_vector ( 1 downto 0 ) := "10";
CONSTANT SZDBL : std_logic_vector ( 1 downto 0 ) := "11";
PROCEDURE regaddr (
cwp : std_logic_vector;
reg : std_logic_vector ( 4 downto 0 );
rao : out rfatype
) IS
VARIABLE ra : rfatype;
CONSTANT globals : std_logic_vector ( 4 + 4 - 5 downto 0 ) := conv_std_logic_vector ( 8 , 4 + 4 - 4 );
BEGIN
ra := ( OTHERS => '0' );
ra ( 4 downto 0 ) := reg;
IF reg ( 4 downto 3 ) = "00" THEN
ra ( 7 downto 4 ) := CONV_STD_LOGIC_VECTOR ( 8 , 4 + 4 - 4 );
ELSE
ra ( 6 downto 4 ) := cwp + ra ( 4 );
END IF;
rao := ra;
END;
FUNCTION branch_address (
inst : word;
pc : pctype
) RETURN std_logic_vector IS
VARIABLE baddr : pctype;
VARIABLE caddr : pctype;
VARIABLE tmp : pctype;
BEGIN
caddr := ( OTHERS => '0' );
caddr ( 31 downto 2 ) := inst ( 29 downto 0 );
caddr ( 31 downto 2 ) := caddr ( 31 downto 2 ) + pc ( 31 downto 2 );
baddr := ( OTHERS => '0' );
baddr ( 31 downto 24 ) := ( OTHERS => inst ( 21 ) );
baddr ( 23 downto 2 ) := inst ( 21 downto 0 );
baddr ( 31 downto 2 ) := baddr ( 31 downto 2 ) + pc ( 31 downto 2 );
IF inst ( 30 ) = '1' THEN
tmp := caddr;
ELSE
tmp := baddr;
END IF;
RETURN ( tmp );
END;
FUNCTION branch_true (
icc : std_logic_vector ( 3 downto 0 );
inst : word
) RETURN std_ulogic IS
VARIABLE n : std_ulogic;
VARIABLE z : std_ulogic;
VARIABLE v : std_ulogic;
VARIABLE c : std_ulogic;
VARIABLE branch : std_ulogic;
BEGIN
n := icc ( 3 );
z := icc ( 2 );
v := icc ( 1 );
c := icc ( 0 );
CASE inst ( 27 downto 25 ) IS
WHEN "000" =>
branch := inst ( 28 ) xor '0';
WHEN "001" =>
branch := inst ( 28 ) xor z;
WHEN "010" =>
branch := inst ( 28 ) xor ( z or ( n xor v ) );
WHEN "011" =>
branch := inst ( 28 ) xor ( n xor v );
WHEN "100" =>
branch := inst ( 28 ) xor ( c or z );
WHEN "101" =>
branch := inst ( 28 ) xor c;
WHEN "110" =>
branch := inst ( 28 ) xor n;
WHEN OTHERS =>
branch := inst ( 28 ) xor v;
END CASE;
RETURN ( branch );
END;
PROCEDURE su_et_select (
r : in registers;
xc_ps : in std_ulogic;
xc_s : in std_ulogic;
xc_et : in std_ulogic;
su : out std_ulogic;
et : out std_ulogic
) IS
BEGIN
IF ( ( r.a.ctrl.rett or r.e.ctrl.rett or r.m.ctrl.rett or r.x.ctrl.rett ) = '1' ) and ( r.x.annul_all = '0' ) THEN
su := xc_ps;
et := '1';
ELSE
su := xc_s;
et := xc_et;
END IF;
END;
FUNCTION wphit (
r : registers;
wpr : watchpoint_registers;
debug : l3_debug_in_type
) RETURN std_ulogic IS
VARIABLE exc : std_ulogic;
BEGIN
exc := '0';
IF ( ( wpr ( 0 ).exec and r.a.ctrl.pv and not r.a.ctrl.annul ) = '1' ) THEN
IF ( ( ( wpr ( 0 ).addr xor r.a.ctrl.pc ( 31 downto 2 ) ) and wpr ( 0 ).mask ) = "000000000000000000000000000000" ) THEN
exc := '1';
END IF;
END IF;
IF ( ( wpr ( 1 ).exec and r.a.ctrl.pv and not r.a.ctrl.annul ) = '1' ) THEN
IF ( ( ( wpr ( 1 ).addr xor r.a.ctrl.pc ( 31 downto 2 ) ) and wpr ( 1 ).mask ) = "000000000000000000000000000000" ) THEN
exc := '1';
END IF;
END IF;
IF ( debug.dsuen and not r.a.ctrl.annul ) = '1' THEN
exc := exc or ( r.a.ctrl.pv and ( ( debug.dbreak and debug.bwatch ) or r.a.step ) );
END IF;
RETURN ( exc );
END;
FUNCTION shift3 (
r : registers;
aluin1 : word;
aluin2 : word
) RETURN word IS
VARIABLE shiftin : unsigned ( 63 downto 0 );
VARIABLE shiftout : unsigned ( 63 downto 0 );
VARIABLE cnt : natural RANGE 0 to 31;
BEGIN
cnt := conv_integer ( r.e.shcnt );
IF r.e.shleft = '1' THEN
shiftin ( 30 downto 0 ) := ( OTHERS => '0' );
shiftin ( 63 downto 31 ) := '0' & unsigned ( aluin1 );
ELSE
shiftin ( 63 downto 32 ) := ( OTHERS => r.e.sari );
shiftin ( 31 downto 0 ) := unsigned ( aluin1 );
END IF;
shiftout := SHIFT_RIGHT ( shiftin , cnt );
RETURN ( std_logic_vector ( shiftout ( 31 downto 0 ) ) );
END;
FUNCTION shift2 (
r : registers;
aluin1 : word;
aluin2 : word
) RETURN word IS
VARIABLE ushiftin : unsigned ( 31 downto 0 );
VARIABLE sshiftin : signed ( 32 downto 0 );
VARIABLE cnt : natural RANGE 0 to 31;
BEGIN
cnt := conv_integer ( r.e.shcnt );
ushiftin := unsigned ( aluin1 );
sshiftin := signed ( '0' & aluin1 );
IF r.e.shleft = '1' THEN
RETURN ( std_logic_vector ( SHIFT_LEFT ( ushiftin , cnt ) ) );
ELSE
IF r.e.sari = '1' THEN
sshiftin ( 32 ) := aluin1 ( 31 );
END IF;
sshiftin := SHIFT_RIGHT ( sshiftin , cnt );
RETURN ( std_logic_vector ( sshiftin ( 31 downto 0 ) ) );
END IF;
END;
FUNCTION shift (
r : registers;
aluin1 : word;
aluin2 : word;
shiftcnt : std_logic_vector ( 4 downto 0 );
sari : std_ulogic
) RETURN word IS
VARIABLE shiftin : std_logic_vector ( 63 downto 0 );
BEGIN
shiftin := "00000000000000000000000000000000" & aluin1;
IF r.e.shleft = '1' THEN
shiftin ( 31 downto 0 ) := "00000000000000000000000000000000";
shiftin ( 63 downto 31 ) := '0' & aluin1;
ELSE
shiftin ( 63 downto 32 ) := ( OTHERS => sari );
END IF;
IF shiftcnt ( 4 ) = '1' THEN
shiftin ( 47 downto 0 ) := shiftin ( 63 downto 16 );
END IF;
IF shiftcnt ( 3 ) = '1' THEN
shiftin ( 39 downto 0 ) := shiftin ( 47 downto 8 );
END IF;
IF shiftcnt ( 2 ) = '1' THEN
shiftin ( 35 downto 0 ) := shiftin ( 39 downto 4 );
END IF;
IF shiftcnt ( 1 ) = '1' THEN
shiftin ( 33 downto 0 ) := shiftin ( 35 downto 2 );
END IF;
IF shiftcnt ( 0 ) = '1' THEN
shiftin ( 31 downto 0 ) := shiftin ( 32 downto 1 );
END IF;
RETURN ( shiftin ( 31 downto 0 ) );
END;
PROCEDURE exception_detect (
r : registers;
wpr : watchpoint_registers;
dbgi : l3_debug_in_type;
trapin : in std_ulogic;
ttin : in std_logic_vector ( 5 downto 0 );
trap : out std_ulogic;
tt : out std_logic_vector ( 5 downto 0 )
) IS
VARIABLE illegal_inst : std_ulogic;
VARIABLE privileged_inst : std_ulogic;
VARIABLE cp_disabled : std_ulogic;
VARIABLE fp_disabled : std_ulogic;
VARIABLE fpop : std_ulogic;
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op2 : std_logic_vector ( 2 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
VARIABLE rd : std_logic_vector ( 4 downto 0 );
VARIABLE inst : word;
VARIABLE wph : std_ulogic;
BEGIN
inst := r.a.ctrl.inst;
trap := trapin;
tt := ttin;
IF r.a.ctrl.annul = '0' THEN
op := inst ( 31 downto 30 );
op2 := inst ( 24 downto 22 );
op3 := inst ( 24 downto 19 );
rd := inst ( 29 downto 25 );
illegal_inst := '0';
privileged_inst := '0';
cp_disabled := '0';
fp_disabled := '0';
fpop := '0';
CASE op IS
WHEN CALL =>
NULL;
WHEN FMT2 =>
CASE op2 IS
WHEN SETHI | BICC =>
NULL;
WHEN FBFCC =>
fp_disabled := '1';
WHEN CBCCC =>
cp_disabled := '1';
WHEN OTHERS =>
illegal_inst := '1';
END CASE;
WHEN FMT3 =>
CASE op3 IS
WHEN IAND | ANDCC | ANDN | ANDNCC | IOR | ORCC | ORN | ORNCC | IXOR | XORCC | IXNOR | XNORCC | ISLL | ISRL | ISRA | MULSCC | IADD | ADDX | ADDCC | ADDXCC | ISUB | SUBX | SUBCC | SUBXCC | FLUSH | JMPL | TICC | SAVE | RESTORE | RDY =>
NULL;
WHEN TADDCC | TADDCCTV | TSUBCC | TSUBCCTV =>
NULL;
WHEN UMAC | SMAC =>
illegal_inst := '1';
WHEN UMUL | SMUL | UMULCC | SMULCC =>
NULL;
WHEN UDIV | SDIV | UDIVCC | SDIVCC =>
NULL;
WHEN RETT =>
illegal_inst := r.a.et;
privileged_inst := not r.a.su;
WHEN RDPSR | RDTBR | RDWIM =>
privileged_inst := not r.a.su;
WHEN WRY =>
NULL;
WHEN WRPSR =>
privileged_inst := not r.a.su;
WHEN WRWIM | WRTBR =>
privileged_inst := not r.a.su;
WHEN FPOP1 | FPOP2 =>
fp_disabled := '1';
fpop := '0';
WHEN CPOP1 | CPOP2 =>
cp_disabled := '1';
WHEN OTHERS =>
illegal_inst := '1';
END CASE;
WHEN OTHERS =>
CASE op3 IS
WHEN LDD | ISTD =>
illegal_inst := rd ( 0 );
WHEN LD | LDUB | LDSTUB | LDUH | LDSB | LDSH | ST | STB | STH | SWAP =>
NULL;
WHEN LDDA | STDA =>
illegal_inst := inst ( 13 ) or rd ( 0 );
privileged_inst := not r.a.su;
WHEN LDA | LDUBA | LDSTUBA | LDUHA | LDSBA | LDSHA | STA | STBA | STHA | SWAPA =>
illegal_inst := inst ( 13 );
privileged_inst := not r.a.su;
WHEN LDDF | STDF | LDF | LDFSR | STF | STFSR =>
fp_disabled := '1';
WHEN STDFQ =>
privileged_inst := not r.a.su;
fp_disabled := '1';
WHEN STDCQ =>
privileged_inst := not r.a.su;
cp_disabled := '1';
WHEN LDC | LDCSR | LDDC | STC | STCSR | STDC =>
cp_disabled := '1';
WHEN OTHERS =>
illegal_inst := '1';
END CASE;
END CASE;
wph := wphit ( r , wpr , dbgi );
trap := '1';
IF r.a.ctrl.trap = '1' THEN
tt := TT_IAEX;
ELSIF privileged_inst = '1' THEN
tt := TT_PRIV;
ELSIF illegal_inst = '1' THEN
tt := TT_IINST;
ELSIF fp_disabled = '1' THEN
tt := TT_FPDIS;
ELSIF cp_disabled = '1' THEN
tt := TT_CPDIS;
ELSIF wph = '1' THEN
tt := TT_WATCH;
ELSIF r.a.wovf = '1' THEN
tt := TT_WINOF;
ELSIF r.a.wunf = '1' THEN
tt := TT_WINUF;
ELSIF r.a.ticc = '1' THEN
tt := TT_TICC;
ELSE
trap := '0';
tt := ( OTHERS => '0' );
END IF;
END IF;
END;
PROCEDURE wicc_y_gen (
inst : word;
wicc : out std_ulogic;
wy : out std_ulogic
) IS
BEGIN
wicc := '0';
wy := '0';
IF inst ( 31 downto 30 ) = FMT3 THEN
CASE inst ( 24 downto 19 ) IS
WHEN SUBCC | TSUBCC | TSUBCCTV | ADDCC | ANDCC | ORCC | XORCC | ANDNCC | ORNCC | XNORCC | TADDCC | TADDCCTV | ADDXCC | SUBXCC | WRPSR =>
wicc := '1';
WHEN WRY =>
IF r.d.inst ( conv_integer ( r.d.set ) ) ( 29 downto 25 ) = "00000" THEN
wy := '1';
END IF;
WHEN MULSCC =>
wicc := '1';
wy := '1';
WHEN UMAC | SMAC =>
NULL;
WHEN UMULCC | SMULCC =>
IF ( ( ( mulo.nready = '1' ) and ( r.d.cnt /= "00" ) ) ) THEN
wicc := '1';
wy := '1';
END IF;
WHEN UMUL | SMUL =>
IF ( ( ( mulo.nready = '1' ) and ( r.d.cnt /= "00" ) ) ) THEN
wy := '1';
END IF;
WHEN UDIVCC | SDIVCC =>
IF ( divo.nready = '1' ) and ( r.d.cnt /= "00" ) THEN
wicc := '1';
END IF;
WHEN OTHERS =>
NULL;
END CASE;
END IF;
END;
PROCEDURE cwp_gen (
r : registers;
v : registers;
annul : std_ulogic;
wcwp : std_ulogic;
ncwp : cwptype;
cwp : out cwptype
) IS
BEGIN
IF ( r.x.rstate = trap ) or ( r.x.rstate = dsu2 ) or ( rstn = '0' ) THEN
cwp := v.w.s.cwp;
ELSIF ( wcwp = '1' ) and ( annul = '0' ) THEN
cwp := ncwp;
ELSIF r.m.wcwp = '1' THEN
cwp := r.m.result ( 3 - 1 downto 0 );
ELSE
cwp := r.d.cwp;
END IF;
END;
PROCEDURE cwp_ex (
r : in registers;
wcwp : out std_ulogic
) IS
BEGIN
IF ( r.e.ctrl.inst ( 31 downto 30 ) = FMT3 ) and ( r.e.ctrl.inst ( 24 downto 19 ) = WRPSR ) THEN
wcwp := not r.e.ctrl.annul;
ELSE
wcwp := '0';
END IF;
END;
PROCEDURE cwp_ctrl (
r : in registers;
xc_wim : in std_logic_vector ( 8 - 1 downto 0 );
inst : word;
de_cwp : out cwptype;
wovf_exc : out std_ulogic;
wunf_exc : out std_ulogic;
wcwp : out std_ulogic
) IS
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
VARIABLE wim : word;
VARIABLE ncwp : cwptype;
BEGIN
op := inst ( 31 downto 30 );
op3 := inst ( 24 downto 19 );
wovf_exc := '0';
wunf_exc := '0';
wim := ( OTHERS => '0' );
wim ( 8 - 1 downto 0 ) := xc_wim;
ncwp := r.d.cwp;
wcwp := '0';
IF ( op = FMT3 ) and ( ( op3 = RETT ) or ( op3 = RESTORE ) or ( op3 = SAVE ) ) THEN
wcwp := '1';
IF ( op3 = SAVE ) THEN
ncwp := r.d.cwp - 1;
ELSE
ncwp := r.d.cwp + 1;
END IF;
IF wim ( conv_integer ( ncwp ) ) = '1' THEN
IF op3 = SAVE THEN
wovf_exc := '1';
ELSE
wunf_exc := '1';
END IF;
END IF;
END IF;
de_cwp := ncwp;
END;
PROCEDURE rs1_gen (
r : registers;
inst : word;
rs1 : out std_logic_vector ( 4 downto 0 );
rs1mod : out std_ulogic
) IS
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
BEGIN
op := inst ( 31 downto 30 );
op3 := inst ( 24 downto 19 );
rs1 := inst ( 18 downto 14 );
rs1mod := '0';
IF ( op = LDST ) THEN
IF ( ( r.d.cnt = "01" ) and ( ( op3 ( 2 ) and not op3 ( 3 ) ) = '1' ) ) or ( r.d.cnt = "10" ) THEN
rs1mod := '1';
rs1 := inst ( 29 downto 25 );
END IF;
IF ( ( r.d.cnt = "10" ) and ( op3 ( 3 downto 0 ) = "0111" ) ) THEN
rs1 ( 0 ) := '1';
END IF;
END IF;
END;
PROCEDURE lock_gen (
r : registers;
rs2 : std_logic_vector ( 4 downto 0 );
rd : std_logic_vector ( 4 downto 0 );
rfa1 : rfatype;
rfa2 : rfatype;
rfrd : rfatype;
inst : word;
fpc_lock : std_ulogic;
mulinsn : std_ulogic;
divinsn : std_ulogic;
lldcheck1 : out std_ulogic;
lldcheck2 : out std_ulogic;
lldlock : out std_ulogic;
lldchkra : out std_ulogic;
lldchkex : out std_ulogic
) IS
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op2 : std_logic_vector ( 2 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
VARIABLE cond : std_logic_vector ( 3 downto 0 );
VARIABLE rs1 : std_logic_vector ( 4 downto 0 );
VARIABLE i : std_ulogic;
VARIABLE ldcheck1 : std_ulogic;
VARIABLE ldcheck2 : std_ulogic;
VARIABLE ldchkra : std_ulogic;
VARIABLE ldchkex : std_ulogic;
VARIABLE ldcheck3 : std_ulogic;
VARIABLE ldlock : std_ulogic;
VARIABLE icc_check : std_ulogic;
VARIABLE bicc_hold : std_ulogic;
VARIABLE chkmul : std_ulogic;
VARIABLE y_check : std_ulogic;
VARIABLE lddlock : boolean;
BEGIN
op := inst ( 31 downto 30 );
op3 := inst ( 24 downto 19 );
op2 := inst ( 24 downto 22 );
cond := inst ( 28 downto 25 );
rs1 := inst ( 18 downto 14 );
lddlock := false;
i := inst ( 13 );
ldcheck1 := '0';
ldcheck2 := '0';
ldcheck3 := '0';
ldlock := '0';
ldchkra := '1';
ldchkex := '1';
icc_check := '0';
bicc_hold := '0';
y_check := '0';
IF ( r.d.annul = '0' ) THEN
CASE op IS
WHEN FMT2 =>
IF ( op2 = BICC ) and ( cond ( 2 downto 0 ) /= "000" ) THEN
icc_check := '1';
END IF;
WHEN FMT3 =>
ldcheck1 := '1';
ldcheck2 := not i;
CASE op3 IS
WHEN TICC =>
IF ( cond ( 2 downto 0 ) /= "000" ) THEN
icc_check := '1';
END IF;
WHEN RDY =>
ldcheck1 := '0';
ldcheck2 := '0';
WHEN RDWIM | RDTBR =>
ldcheck1 := '0';
ldcheck2 := '0';
WHEN RDPSR =>
ldcheck1 := '0';
ldcheck2 := '0';
icc_check := '1';
icc_check := '1';
WHEN SDIV | SDIVCC | UDIV | UDIVCC =>
y_check := '1';
WHEN FPOP1 | FPOP2 =>
ldcheck1 := '0';
ldcheck2 := '0';
WHEN OTHERS =>
NULL;
END CASE;
WHEN LDST =>
ldcheck1 := '1';
ldchkra := '0';
CASE r.d.cnt IS
WHEN "00" =>
ldcheck2 := not i;
ldchkra := '1';
WHEN "01" =>
ldcheck2 := not i;
WHEN OTHERS =>
ldchkex := '0';
END CASE;
IF ( op3 ( 2 downto 0 ) = "011" ) THEN
lddlock := true;
END IF;
WHEN OTHERS =>
NULL;
END CASE;
END IF;
chkmul := mulinsn;
bicc_hold := bicc_hold or ( icc_check and r.m.ctrl.wicc and ( r.m.ctrl.cnt ( 0 ) or r.m.mul ) );
bicc_hold := bicc_hold or ( y_check and ( r.a.ctrl.wy or r.e.ctrl.wy ) );
chkmul := chkmul or divinsn;
bicc_hold := bicc_hold or ( icc_check and ( r.a.ctrl.wicc or r.e.ctrl.wicc ) );
IF ( ( ( r.a.ctrl.ld or chkmul ) and r.a.ctrl.wreg and ldchkra ) = '1' ) and ( ( ( ldcheck1 = '1' ) and ( r.a.ctrl.rd = rfa1 ) ) or ( ( ldcheck2 = '1' ) and ( r.a.ctrl.rd = rfa2 ) ) or ( ( ldcheck3 = '1' ) and ( r.a.ctrl.rd = rfrd ) ) ) THEN
ldlock := '1';
END IF;
IF ( ( ( r.e.ctrl.ld or r.e.mac ) and r.e.ctrl.wreg and ldchkex ) = '1' ) and ( ( ( ldcheck1 = '1' ) and ( r.e.ctrl.rd = rfa1 ) ) or ( ( ldcheck2 = '1' ) and ( r.e.ctrl.rd = rfa2 ) ) ) THEN
ldlock := '1';
END IF;
ldlock := ldlock or bicc_hold or fpc_lock;
lldcheck1 := ldcheck1;
lldcheck2 := ldcheck2;
lldlock := ldlock;
lldchkra := ldchkra;
lldchkex := ldchkex;
END;
PROCEDURE fpbranch (
inst : in word;
fcc : in std_logic_vector ( 1 downto 0 );
branch : out std_ulogic
) IS
VARIABLE cond : std_logic_vector ( 3 downto 0 );
VARIABLE fbres : std_ulogic;
BEGIN
cond := inst ( 28 downto 25 );
CASE cond ( 2 downto 0 ) IS
WHEN "000" =>
fbres := '0';
WHEN "001" =>
fbres := fcc ( 1 ) or fcc ( 0 );
WHEN "010" =>
fbres := fcc ( 1 ) xor fcc ( 0 );
WHEN "011" =>
fbres := fcc ( 0 );
WHEN "100" =>
fbres := ( not fcc ( 1 ) ) and fcc ( 0 );
WHEN "101" =>
fbres := fcc ( 1 );
WHEN "110" =>
fbres := fcc ( 1 ) and not fcc ( 0 );
WHEN OTHERS =>
fbres := fcc ( 1 ) and fcc ( 0 );
END CASE;
branch := cond ( 3 ) xor fbres;
END;
PROCEDURE ic_ctrl (
r : registers;
inst : word;
annul_all : in std_ulogic;
ldlock : in std_ulogic;
branch_true : in std_ulogic;
fbranch_true : in std_ulogic;
cbranch_true : in std_ulogic;
fccv : in std_ulogic;
cccv : in std_ulogic;
cnt : out std_logic_vector ( 1 downto 0 );
de_pc : out pctype;
de_branch : out std_ulogic;
ctrl_annul : out std_ulogic;
de_annul : out std_ulogic;
jmpl_inst : out std_ulogic;
inull : out std_ulogic;
de_pv : out std_ulogic;
ctrl_pv : out std_ulogic;
de_hold_pc : out std_ulogic;
ticc_exception : out std_ulogic;
rett_inst : out std_ulogic;
mulstart : out std_ulogic;
divstart : out std_ulogic
) IS
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op2 : std_logic_vector ( 2 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
VARIABLE cond : std_logic_vector ( 3 downto 0 );
VARIABLE hold_pc : std_ulogic;
VARIABLE annul_current : std_ulogic;
VARIABLE annul_next : std_ulogic;
VARIABLE branch : std_ulogic;
VARIABLE annul : std_ulogic;
VARIABLE pv : std_ulogic;
VARIABLE de_jmpl : std_ulogic;
BEGIN
branch := '0';
annul_next := '0';
annul_current := '0';
pv := '1';
hold_pc := '0';
ticc_exception := '0';
rett_inst := '0';
op := inst ( 31 downto 30 );
op3 := inst ( 24 downto 19 );
op2 := inst ( 24 downto 22 );
cond := inst ( 28 downto 25 );
annul := inst ( 29 );
de_jmpl := '0';
cnt := "00";
mulstart := '0';
divstart := '0';
IF r.d.annul = '0' THEN
CASE inst ( 31 downto 30 ) IS
WHEN CALL =>
branch := '1';
IF r.d.inull = '1' THEN
hold_pc := '1';
annul_current := '1';
END IF;
WHEN FMT2 =>
IF ( op2 = BICC ) THEN
branch := branch_true;
IF hold_pc = '0' THEN
IF ( branch = '1' ) THEN
IF ( cond = BA ) and ( annul = '1' ) THEN
annul_next := '1';
END IF;
ELSE
annul_next := annul;
END IF;
IF r.d.inull = '1' THEN
hold_pc := '1';
annul_current := '1';
annul_next := '0';
END IF;
END IF;
END IF;
WHEN FMT3 =>
CASE op3 IS
WHEN UMUL | SMUL | UMULCC | SMULCC =>
CASE r.d.cnt IS
WHEN "00" =>
cnt := "01";
hold_pc := '1';
pv := '0';
mulstart := '1';
WHEN "01" =>
IF mulo.nready = '1' THEN
cnt := "00";
ELSE
cnt := "01";
pv := '0';
hold_pc := '1';
END IF;
WHEN OTHERS =>
NULL;
END CASE;
WHEN UDIV | SDIV | UDIVCC | SDIVCC =>
CASE r.d.cnt IS
WHEN "00" =>
cnt := "01";
hold_pc := '1';
pv := '0';
divstart := '1';
WHEN "01" =>
IF divo.nready = '1' THEN
cnt := "00";
ELSE
cnt := "01";
pv := '0';
hold_pc := '1';
END IF;
WHEN OTHERS =>
NULL;
END CASE;
WHEN TICC =>
IF branch_true = '1' THEN
ticc_exception := '1';
END IF;
WHEN RETT =>
rett_inst := '1';
WHEN JMPL =>
de_jmpl := '1';
WHEN WRY =>
IF FALSE THEN
IF inst ( 29 downto 25 ) = "10011" THEN
CASE r.d.cnt IS
WHEN "00" =>
pv := '0';
cnt := "00";
hold_pc := '1';
IF r.x.ipend = '1' THEN
cnt := "01";
END IF;
WHEN "01" =>
cnt := "00";
WHEN OTHERS =>
NULL;
END CASE;
END IF;
END IF;
WHEN OTHERS =>
NULL;
END CASE;
WHEN OTHERS =>
CASE r.d.cnt IS
WHEN "00" =>
IF ( op3 ( 2 ) = '1' ) or ( op3 ( 1 downto 0 ) = "11" ) THEN
cnt := "01";
hold_pc := '1';
pv := '0';
END IF;
WHEN "01" =>
IF ( op3 ( 2 downto 0 ) = "111" ) or ( op3 ( 3 downto 0 ) = "1101" ) or ( ( ( 0 = 1 ) or ( 0 /= 0 ) ) and ( ( op3 ( 5 ) & op3 ( 2 downto 0 ) ) = "1110" ) ) THEN
cnt := "10";
pv := '0';
hold_pc := '1';
ELSE
cnt := "00";
END IF;
WHEN "10" =>
cnt := "00";
WHEN OTHERS =>
NULL;
END CASE;
END CASE;
END IF;
IF ldlock = '1' THEN
cnt := r.d.cnt;
annul_next := '0';
pv := '1';
END IF;
hold_pc := ( hold_pc or ldlock ) and not annul_all;
IF hold_pc = '1' THEN
de_pc := r.d.pc;
ELSE
de_pc := r.f.pc;
END IF;
annul_current := ( annul_current or ldlock or annul_all );
ctrl_annul := r.d.annul or annul_all or annul_current;
pv := pv and not ( ( r.d.inull and not hold_pc ) or annul_all );
jmpl_inst := de_jmpl and not annul_current;
annul_next := ( r.d.inull and not hold_pc ) or annul_next or annul_all;
IF ( annul_next = '1' ) or ( rstn = '0' ) THEN
cnt := ( OTHERS => '0' );
END IF;
de_hold_pc := hold_pc;
de_branch := branch;
de_annul := annul_next;
de_pv := pv;
ctrl_pv := r.d.pv and not ( ( r.d.annul and not r.d.pv ) or annul_all or annul_current );
inull := ( not rstn ) or r.d.inull or hold_pc or annul_all;
END;
PROCEDURE rd_gen (
r : registers;
inst : word;
wreg : out std_ulogic;
ld : out std_ulogic;
rdo : out std_logic_vector ( 4 downto 0 )
) IS
VARIABLE write_reg : std_ulogic;
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op2 : std_logic_vector ( 2 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
VARIABLE rd : std_logic_vector ( 4 downto 0 );
BEGIN
op := inst ( 31 downto 30 );
op2 := inst ( 24 downto 22 );
op3 := inst ( 24 downto 19 );
write_reg := '0';
rd := inst ( 29 downto 25 );
ld := '0';
CASE op IS
WHEN CALL =>
write_reg := '1';
rd := "01111";
WHEN FMT2 =>
IF ( op2 = SETHI ) THEN
write_reg := '1';
END IF;
WHEN FMT3 =>
CASE op3 IS
WHEN UMUL | SMUL | UMULCC | SMULCC =>
IF ( ( ( mulo.nready = '1' ) and ( r.d.cnt /= "00" ) ) ) THEN
write_reg := '1';
END IF;
WHEN UDIV | SDIV | UDIVCC | SDIVCC =>
IF ( divo.nready = '1' ) and ( r.d.cnt /= "00" ) THEN
write_reg := '1';
END IF;
WHEN RETT | WRPSR | WRY | WRWIM | WRTBR | TICC | FLUSH =>
NULL;
WHEN FPOP1 | FPOP2 =>
NULL;
WHEN CPOP1 | CPOP2 =>
NULL;
WHEN OTHERS =>
write_reg := '1';
END CASE;
WHEN OTHERS =>
ld := not op3 ( 2 );
IF ( op3 ( 2 ) = '0' ) and not ( ( ( 0 = 1 ) or ( 0 /= 0 ) ) and ( op3 ( 5 ) = '1' ) ) THEN
write_reg := '1';
END IF;
CASE op3 IS
WHEN SWAP | SWAPA | LDSTUB | LDSTUBA =>
IF r.d.cnt = "00" THEN
write_reg := '1';
ld := '1';
END IF;
WHEN OTHERS =>
NULL;
END CASE;
IF r.d.cnt = "01" THEN
CASE op3 IS
WHEN LDD | LDDA | LDDC | LDDF =>
rd ( 0 ) := '1';
WHEN OTHERS =>
NULL;
END CASE;
END IF;
END CASE;
IF ( rd = "00000" ) THEN
write_reg := '0';
END IF;
wreg := write_reg;
rdo := rd;
END;
FUNCTION imm_data (
r : registers;
insn : word
) RETURN word IS
VARIABLE immediate_data : word;
VARIABLE inst : word;
BEGIN
immediate_data := ( OTHERS => '0' );
inst := insn;
CASE inst ( 31 downto 30 ) IS
WHEN FMT2 =>
immediate_data := inst ( 21 downto 0 ) & "0000000000";
WHEN OTHERS =>
immediate_data ( 31 downto 13 ) := ( OTHERS => inst ( 12 ) );
immediate_data ( 12 downto 0 ) := inst ( 12 downto 0 );
END CASE;
RETURN ( immediate_data );
END;
FUNCTION get_spr (
r : registers
) RETURN word IS
VARIABLE spr : word;
BEGIN
spr := ( OTHERS => '0' );
CASE r.e.ctrl.inst ( 24 downto 19 ) IS
WHEN RDPSR =>
spr ( 31 downto 5 ) := conv_std_logic_vector ( 15 , 4 ) & conv_std_logic_vector ( 3 , 4 ) & r.m.icc & "000000" & r.w.s.ec & r.w.s.ef & r.w.s.pil & r.e.su & r.w.s.ps & r.e.et;
spr ( 3 - 1 downto 0 ) := r.e.cwp;
WHEN RDTBR =>
spr ( 31 downto 4 ) := r.w.s.tba & r.w.s.tt;
WHEN RDWIM =>
spr ( 8 - 1 downto 0 ) := r.w.s.wim;
WHEN OTHERS =>
NULL;
END CASE;
RETURN ( spr );
END;
FUNCTION imm_select (
inst : word
) RETURN boolean IS
VARIABLE imm : boolean;
BEGIN
imm := false;
CASE inst ( 31 downto 30 ) IS
WHEN FMT2 =>
CASE inst ( 24 downto 22 ) IS
WHEN SETHI =>
imm := true;
WHEN OTHERS =>
NULL;
END CASE;
WHEN FMT3 =>
CASE inst ( 24 downto 19 ) IS
WHEN RDWIM | RDPSR | RDTBR =>
imm := true;
WHEN OTHERS =>
IF ( inst ( 13 ) = '1' ) THEN
imm := true;
END IF;
END CASE;
WHEN LDST =>
IF ( inst ( 13 ) = '1' ) THEN
imm := true;
END IF;
WHEN OTHERS =>
NULL;
END CASE;
RETURN ( imm );
END;
PROCEDURE alu_op (
r : in registers;
iop1 : in word;
iop2 : in word;
me_icc : std_logic_vector ( 3 downto 0 );
my : std_ulogic;
ldbp : std_ulogic;
aop1 : out word;
aop2 : out word;
aluop : out std_logic_vector ( 2 downto 0 );
alusel : out std_logic_vector ( 1 downto 0 );
aluadd : out std_ulogic;
shcnt : out std_logic_vector ( 4 downto 0 );
sari : out std_ulogic;
shleft : out std_ulogic;
ymsb : out std_ulogic;
mulins : out std_ulogic;
divins : out std_ulogic;
mulstep : out std_ulogic;
macins : out std_ulogic;
ldbp2 : out std_ulogic;
invop2 : out std_ulogic
) IS
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op2 : std_logic_vector ( 2 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
VARIABLE rd : std_logic_vector ( 4 downto 0 );
VARIABLE icc : std_logic_vector ( 3 downto 0 );
VARIABLE y0 : std_ulogic;
BEGIN
op := r.a.ctrl.inst ( 31 downto 30 );
op2 := r.a.ctrl.inst ( 24 downto 22 );
op3 := r.a.ctrl.inst ( 24 downto 19 );
aop1 := iop1;
aop2 := iop2;
ldbp2 := ldbp;
aluop := "000";
alusel := "11";
aluadd := '1';
shcnt := iop2 ( 4 downto 0 );
sari := '0';
shleft := '0';
invop2 := '0';
ymsb := iop1 ( 0 );
mulins := '0';
divins := '0';
mulstep := '0';
macins := '0';
IF r.e.ctrl.wy = '1' THEN
y0 := my;
ELSIF r.m.ctrl.wy = '1' THEN
y0 := r.m.y ( 0 );
ELSIF r.x.ctrl.wy = '1' THEN
y0 := r.x.y ( 0 );
ELSE
y0 := r.w.s.y ( 0 );
END IF;
IF r.e.ctrl.wicc = '1' THEN
icc := me_icc;
ELSIF r.m.ctrl.wicc = '1' THEN
icc := r.m.icc;
ELSIF r.x.ctrl.wicc = '1' THEN
icc := r.x.icc;
ELSE
icc := r.w.s.icc;
END IF;
CASE op IS
WHEN CALL =>
aluop := "111";
WHEN FMT2 =>
CASE op2 IS
WHEN SETHI =>
aluop := "001";
WHEN OTHERS =>
NULL;
END CASE;
WHEN FMT3 =>
CASE op3 IS
WHEN IADD | ADDX | ADDCC | ADDXCC | TADDCC | TADDCCTV | SAVE | RESTORE | TICC | JMPL | RETT =>
alusel := "00";
WHEN ISUB | SUBX | SUBCC | SUBXCC | TSUBCC | TSUBCCTV =>
alusel := "00";
aluadd := '0';
aop2 := not iop2;
invop2 := '1';
WHEN MULSCC =>
alusel := "00";
aop1 := ( icc ( 3 ) xor icc ( 1 ) ) & iop1 ( 31 downto 1 );
IF y0 = '0' THEN
aop2 := ( OTHERS => '0' );
ldbp2 := '0';
END IF;
mulstep := '1';
WHEN UMUL | UMULCC | SMUL | SMULCC =>
mulins := '1';
WHEN UMAC | SMAC =>
NULL;
WHEN UDIV | UDIVCC | SDIV | SDIVCC =>
aluop := "110";
alusel := "10";
divins := '1';
WHEN IAND | ANDCC =>
aluop := "000";
alusel := "10";
WHEN ANDN | ANDNCC =>
aluop := "100";
alusel := "10";
WHEN IOR | ORCC =>
aluop := "010";
alusel := "10";
WHEN ORN | ORNCC =>
aluop := "101";
alusel := "10";
WHEN IXNOR | XNORCC =>
aluop := "011";
alusel := "10";
WHEN XORCC | IXOR | WRPSR | WRWIM | WRTBR | WRY =>
aluop := "001";
alusel := "10";
WHEN RDPSR | RDTBR | RDWIM =>
aluop := "110";
WHEN RDY =>
aluop := "101";
WHEN ISLL =>
aluop := "001";
alusel := "01";
shleft := '1';
shcnt := not iop2 ( 4 downto 0 );
invop2 := '1';
WHEN ISRL =>
aluop := "010";
alusel := "01";
WHEN ISRA =>
aluop := "100";
alusel := "01";
sari := iop1 ( 31 );
WHEN FPOP1 | FPOP2 =>
NULL;
WHEN OTHERS =>
NULL;
END CASE;
WHEN OTHERS =>
CASE r.a.ctrl.cnt IS
WHEN "00" =>
alusel := "00";
WHEN "01" =>
CASE op3 IS
WHEN LDD | LDDA | LDDC =>
alusel := "00";
WHEN LDDF =>
alusel := "00";
WHEN SWAP | SWAPA | LDSTUB | LDSTUBA =>
alusel := "00";
WHEN STF | STDF =>
NULL;
WHEN OTHERS =>
aluop := "000";
IF op3 ( 2 ) = '1' THEN
IF op3 ( 1 downto 0 ) = "01" THEN
aluop := "010";
ELSIF op3 ( 1 downto 0 ) = "10" THEN
aluop := "011";
END IF;
END IF;
END CASE;
WHEN "10" =>
aluop := "000";
IF op3 ( 2 ) = '1' THEN
IF ( op3 ( 3 ) and not op3 ( 1 ) ) = '1' THEN
aluop := "100";
END IF;
END IF;
WHEN OTHERS =>
NULL;
END CASE;
END CASE;
END;
FUNCTION ra_inull_gen (
r : registers;
v : registers
) RETURN std_ulogic IS
VARIABLE de_inull : std_ulogic;
BEGIN
de_inull := '0';
IF ( ( v.e.jmpl or v.e.ctrl.rett ) and not v.e.ctrl.annul and not ( r.e.jmpl and not r.e.ctrl.annul ) ) = '1' THEN
de_inull := '1';
END IF;
IF ( ( v.a.jmpl or v.a.ctrl.rett ) and not v.a.ctrl.annul and not ( r.a.jmpl and not r.a.ctrl.annul ) ) = '1' THEN
de_inull := '1';
END IF;
RETURN ( de_inull );
END;
PROCEDURE op_mux (
r : in registers;
rfd : in word;
ed : in word;
md : in word;
xd : in word;
im : in word;
rsel : in std_logic_vector ( 2 downto 0 );
ldbp : out std_ulogic;
d : out word
) IS
BEGIN
ldbp := '0';
CASE rsel IS
WHEN "000" =>
d := rfd;
WHEN "001" =>
d := ed;
WHEN "010" =>
d := md;
ldbp := r.m.ctrl.ld;
WHEN "011" =>
d := xd;
WHEN "100" =>
d := im;
WHEN "101" =>
d := ( OTHERS => '0' );
WHEN "110" =>
d := r.w.result;
WHEN OTHERS =>
d := ( OTHERS => '-' );
END CASE;
END;
PROCEDURE op_find (
r : in registers;
ldchkra : std_ulogic;
ldchkex : std_ulogic;
rs1 : std_logic_vector ( 4 downto 0 );
ra : rfatype;
im : boolean;
rfe : out std_ulogic;
osel : out std_logic_vector ( 2 downto 0 );
ldcheck : std_ulogic
) IS
BEGIN
rfe := '0';
IF im THEN
osel := "100";
ELSIF rs1 = "00000" THEN
osel := "101";
ELSIF ( ( r.a.ctrl.wreg and ldchkra ) = '1' ) and ( ra = r.a.ctrl.rd ) THEN
osel := "001";
ELSIF ( ( r.e.ctrl.wreg and ldchkex ) = '1' ) and ( ra = r.e.ctrl.rd ) THEN
osel := "010";
ELSIF r.m.ctrl.wreg = '1' and ( ra = r.m.ctrl.rd ) THEN
osel := "011";
ELSE
osel := "000";
rfe := ldcheck;
END IF;
END;
PROCEDURE cin_gen (
r : registers;
me_cin : in std_ulogic;
cin : out std_ulogic
) IS
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
VARIABLE ncin : std_ulogic;
BEGIN
op := r.a.ctrl.inst ( 31 downto 30 );
op3 := r.a.ctrl.inst ( 24 downto 19 );
IF r.e.ctrl.wicc = '1' THEN
ncin := me_cin;
ELSE
ncin := r.m.icc ( 0 );
END IF;
cin := '0';
CASE op IS
WHEN FMT3 =>
CASE op3 IS
WHEN ISUB | SUBCC | TSUBCC | TSUBCCTV =>
cin := '1';
WHEN ADDX | ADDXCC =>
cin := ncin;
WHEN SUBX | SUBXCC =>
cin := not ncin;
WHEN OTHERS =>
NULL;
END CASE;
WHEN OTHERS =>
NULL;
END CASE;
END;
PROCEDURE logic_op (
r : registers;
aluin1 : word;
aluin2 : word;
mey : word;
ymsb : std_ulogic;
logicres : out word;
y : out word
) IS
VARIABLE logicout : word;
BEGIN
CASE r.e.aluop IS
WHEN "000" =>
logicout := aluin1 and aluin2;
WHEN "100" =>
logicout := aluin1 and not aluin2;
WHEN "010" =>
logicout := aluin1 or aluin2;
WHEN "101" =>
logicout := aluin1 or not aluin2;
WHEN "001" =>
logicout := aluin1 xor aluin2;
WHEN "011" =>
logicout := aluin1 xor not aluin2;
WHEN "110" =>
logicout := aluin2;
WHEN OTHERS =>
logicout := ( OTHERS => '-' );
END CASE;
IF ( r.e.ctrl.wy and r.e.mulstep ) = '1' THEN
y := ymsb & r.m.y ( 31 downto 1 );
ELSIF r.e.ctrl.wy = '1' THEN
y := logicout;
ELSIF r.m.ctrl.wy = '1' THEN
y := mey;
ELSIF r.x.ctrl.wy = '1' THEN
y := r.x.y;
ELSE
y := r.w.s.y;
END IF;
logicres := logicout;
END;
PROCEDURE misc_op (
r : registers;
wpr : watchpoint_registers;
aluin1 : word;
aluin2 : word;
ldata : word;
mey : word;
mout : out word;
edata : out word
) IS
VARIABLE miscout : word;
VARIABLE bpdata : word;
VARIABLE stdata : word;
VARIABLE wpi : integer;
BEGIN
wpi := 0;
miscout := r.e.ctrl.pc ( 31 downto 2 ) & "00";
edata := aluin1;
bpdata := aluin1;
IF ( ( r.x.ctrl.wreg and r.x.ctrl.ld and not r.x.ctrl.annul ) = '1' ) and ( r.x.ctrl.rd = r.e.ctrl.rd ) and ( r.e.ctrl.inst ( 31 downto 30 ) = LDST ) and ( r.e.ctrl.cnt /= "10" ) THEN
bpdata := ldata;
END IF;
CASE r.e.aluop IS
WHEN "010" =>
miscout := bpdata ( 7 downto 0 ) & bpdata ( 7 downto 0 ) & bpdata ( 7 downto 0 ) & bpdata ( 7 downto 0 );
edata := miscout;
WHEN "011" =>
miscout := bpdata ( 15 downto 0 ) & bpdata ( 15 downto 0 );
edata := miscout;
WHEN "000" =>
miscout := bpdata;
edata := miscout;
WHEN "001" =>
miscout := aluin2;
WHEN "100" =>
miscout := ( OTHERS => '1' );
edata := miscout;
WHEN "101" =>
IF ( r.m.ctrl.wy = '1' ) THEN
miscout := mey;
ELSE
miscout := r.m.y;
END IF;
IF ( r.e.ctrl.inst ( 18 downto 17 ) = "11" ) THEN
wpi := conv_integer ( r.e.ctrl.inst ( 16 downto 15 ) );
IF r.e.ctrl.inst ( 14 ) = '0' THEN
miscout := wpr ( wpi ).addr & '0' & wpr ( wpi ).exec;
ELSE
miscout := wpr ( wpi ).mask & wpr ( wpi ).load & wpr ( wpi ).store;
END IF;
END IF;
IF ( r.e.ctrl.inst ( 18 downto 17 ) = "10" ) and ( r.e.ctrl.inst ( 14 ) = '1' ) THEN
miscout := asr17_gen ( r );
END IF;
WHEN "110" =>
miscout := get_spr ( r );
WHEN OTHERS =>
NULL;
END CASE;
mout := miscout;
END;
PROCEDURE alu_select (
r : registers;
addout : std_logic_vector ( 32 downto 0 );
op1 : word;
op2 : word;
shiftout : word;
logicout : word;
miscout : word;
res : out word;
me_icc : std_logic_vector ( 3 downto 0 );
icco : out std_logic_vector ( 3 downto 0 );
divz : out std_ulogic
) IS
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
VARIABLE icc : std_logic_vector ( 3 downto 0 );
VARIABLE aluresult : word;
BEGIN
op := r.e.ctrl.inst ( 31 downto 30 );
op3 := r.e.ctrl.inst ( 24 downto 19 );
icc := ( OTHERS => '0' );
CASE r.e.alusel IS
WHEN "00" =>
aluresult := addout ( 32 downto 1 );
IF r.e.aluadd = '0' THEN
icc ( 0 ) := ( ( not op1 ( 31 ) ) and not op2 ( 31 ) ) or ( addout ( 32 ) and ( ( not op1 ( 31 ) ) or not op2 ( 31 ) ) );
icc ( 1 ) := ( op1 ( 31 ) and ( op2 ( 31 ) ) and not addout ( 32 ) ) or ( addout ( 32 ) and ( not op1 ( 31 ) ) and not op2 ( 31 ) );
ELSE
icc ( 0 ) := ( op1 ( 31 ) and op2 ( 31 ) ) or ( ( not addout ( 32 ) ) and ( op1 ( 31 ) or op2 ( 31 ) ) );
icc ( 1 ) := ( op1 ( 31 ) and op2 ( 31 ) and not addout ( 32 ) ) or ( addout ( 32 ) and ( not op1 ( 31 ) ) and ( not op2 ( 31 ) ) );
END IF;
CASE op IS
WHEN FMT3 =>
CASE op3 IS
WHEN TADDCC | TADDCCTV =>
icc ( 1 ) := op1 ( 0 ) or op1 ( 1 ) or op2 ( 0 ) or op2 ( 1 ) or icc ( 1 );
WHEN TSUBCC | TSUBCCTV =>
icc ( 1 ) := op1 ( 0 ) or op1 ( 1 ) or ( not op2 ( 0 ) ) or ( not op2 ( 1 ) ) or icc ( 1 );
WHEN OTHERS =>
NULL;
END CASE;
WHEN OTHERS =>
NULL;
END CASE;
IF aluresult = "00000000000000000000000000000000" THEN
icc ( 2 ) := '1';
END IF;
WHEN "01" =>
aluresult := shiftout;
WHEN "10" =>
aluresult := logicout;
IF aluresult = "00000000000000000000000000000000" THEN
icc ( 2 ) := '1';
END IF;
WHEN OTHERS =>
aluresult := miscout;
END CASE;
IF r.e.jmpl = '1' THEN
aluresult := r.e.ctrl.pc ( 31 downto 2 ) & "00";
END IF;
icc ( 3 ) := aluresult ( 31 );
divz := icc ( 2 );
IF r.e.ctrl.wicc = '1' THEN
IF ( op = FMT3 ) and ( op3 = WRPSR ) THEN
icco := logicout ( 23 downto 20 );
ELSE
icco := icc;
END IF;
ELSIF r.m.ctrl.wicc = '1' THEN
icco := me_icc;
ELSIF r.x.ctrl.wicc = '1' THEN
icco := r.x.icc;
ELSE
icco := r.w.s.icc;
END IF;
res := aluresult;
END;
PROCEDURE dcache_gen (
r : registers;
v : registers;
dci : out dc_in_type;
link_pc : out std_ulogic;
jump : out std_ulogic;
force_a2 : out std_ulogic;
load : out std_ulogic
) IS
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
VARIABLE su : std_ulogic;
BEGIN
op := r.e.ctrl.inst ( 31 downto 30 );
op3 := r.e.ctrl.inst ( 24 downto 19 );
dci.signed := '0';
dci.lock := '0';
dci.dsuen := '0';
dci.size := "10";
IF op = LDST THEN
CASE op3 IS
WHEN LDUB | LDUBA =>
dci.size := "00";
WHEN LDSTUB | LDSTUBA =>
dci.size := "00";
dci.lock := '1';
WHEN LDUH | LDUHA =>
dci.size := "01";
WHEN LDSB | LDSBA =>
dci.size := "00";
dci.signed := '1';
WHEN LDSH | LDSHA =>
dci.size := "01";
dci.signed := '1';
WHEN LD | LDA | LDF | LDC =>
dci.size := "10";
WHEN SWAP | SWAPA =>
dci.size := "10";
dci.lock := '1';
WHEN LDD | LDDA | LDDF | LDDC =>
dci.size := "11";
WHEN STB | STBA =>
dci.size := "00";
WHEN STH | STHA =>
dci.size := "01";
WHEN ST | STA | STF =>
dci.size := "10";
WHEN ISTD | STDA =>
dci.size := "11";
WHEN STDF | STDFQ =>
NULL;
WHEN STDC | STDCQ =>
NULL;
WHEN OTHERS =>
dci.size := "10";
dci.lock := '0';
dci.signed := '0';
END CASE;
END IF;
link_pc := '0';
jump := '0';
force_a2 := '0';
load := '0';
dci.write := '0';
dci.enaddr := '0';
dci.read := not op3 ( 2 );
IF ( r.e.ctrl.annul = '0' ) THEN
CASE op IS
WHEN CALL =>
link_pc := '1';
WHEN FMT3 =>
CASE op3 IS
WHEN JMPL =>
jump := '1';
link_pc := '1';
WHEN RETT =>
jump := '1';
WHEN OTHERS =>
NULL;
END CASE;
WHEN LDST =>
CASE r.e.ctrl.cnt IS
WHEN "00" =>
dci.read := op3 ( 3 ) or not op3 ( 2 );
load := op3 ( 3 ) or not op3 ( 2 );
dci.enaddr := '1';
WHEN "01" =>
force_a2 := not op3 ( 2 );
load := not op3 ( 2 );
dci.enaddr := not op3 ( 2 );
IF op3 ( 3 downto 2 ) = "01" THEN
dci.write := '1';
END IF;
IF op3 ( 3 downto 2 ) = "11" THEN
dci.enaddr := '1';
END IF;
WHEN "10" =>
dci.write := '1';
WHEN OTHERS =>
NULL;
END CASE;
IF ( r.e.ctrl.trap or ( v.x.ctrl.trap and not v.x.ctrl.annul ) ) = '1' THEN
dci.enaddr := '0';
END IF;
WHEN OTHERS =>
NULL;
END CASE;
END IF;
IF ( ( r.x.ctrl.rett and not r.x.ctrl.annul ) = '1' ) THEN
su := r.w.s.ps;
ELSE
su := r.w.s.s;
END IF;
IF su = '1' THEN
dci.asi := "00001011";
ELSE
dci.asi := "00001010";
END IF;
IF ( op3 ( 4 ) = '1' ) and ( ( op3 ( 5 ) = '0' ) or not ( 0 = 1 ) ) THEN
dci.asi := r.e.ctrl.inst ( 12 downto 5 );
END IF;
END;
PROCEDURE fpstdata (
r : in registers;
edata : in word;
eres : in word;
fpstdata : in std_logic_vector ( 31 downto 0 );
edata2 : out word;
eres2 : out word
) IS
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
BEGIN
edata2 := edata;
eres2 := eres;
op := r.e.ctrl.inst ( 31 downto 30 );
op3 := r.e.ctrl.inst ( 24 downto 19 );
END;
FUNCTION ld_align (
data : dcdtype;
set : std_logic_vector ( 0 downto 0 );
size : std_logic_vector ( 1 downto 0 );
laddr : std_logic_vector ( 1 downto 0 );
signed : std_ulogic
) RETURN word IS
VARIABLE align_data : word;
VARIABLE rdata : word;
BEGIN
align_data := data ( conv_integer ( set ) );
rdata := ( OTHERS => '0' );
CASE size IS
WHEN "00" =>
CASE laddr IS
WHEN "00" =>
rdata ( 7 downto 0 ) := align_data ( 31 downto 24 );
IF signed = '1' THEN
rdata ( 31 downto 8 ) := ( OTHERS => align_data ( 31 ) );
END IF;
WHEN "01" =>
rdata ( 7 downto 0 ) := align_data ( 23 downto 16 );
IF signed = '1' THEN
rdata ( 31 downto 8 ) := ( OTHERS => align_data ( 23 ) );
END IF;
WHEN "10" =>
rdata ( 7 downto 0 ) := align_data ( 15 downto 8 );
IF signed = '1' THEN
rdata ( 31 downto 8 ) := ( OTHERS => align_data ( 15 ) );
END IF;
WHEN OTHERS =>
rdata ( 7 downto 0 ) := align_data ( 7 downto 0 );
IF signed = '1' THEN
rdata ( 31 downto 8 ) := ( OTHERS => align_data ( 7 ) );
END IF;
END CASE;
WHEN "01" =>
IF laddr ( 1 ) = '1' THEN
rdata ( 15 downto 0 ) := align_data ( 15 downto 0 );
IF signed = '1' THEN
rdata ( 31 downto 15 ) := ( OTHERS => align_data ( 15 ) );
END IF;
ELSE
rdata ( 15 downto 0 ) := align_data ( 31 downto 16 );
IF signed = '1' THEN
rdata ( 31 downto 15 ) := ( OTHERS => align_data ( 31 ) );
END IF;
END IF;
WHEN OTHERS =>
rdata := align_data;
END CASE;
RETURN ( rdata );
END;
PROCEDURE mem_trap (
r : registers;
wpr : watchpoint_registers;
annul : in std_ulogic;
holdn : in std_ulogic;
trapout : out std_ulogic;
iflush : out std_ulogic;
nullify : out std_ulogic;
werrout : out std_ulogic;
tt : out std_logic_vector ( 5 downto 0 )
) IS
VARIABLE cwp : std_logic_vector ( 3 - 1 downto 0 );
VARIABLE cwpx : std_logic_vector ( 5 downto 3 );
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op2 : std_logic_vector ( 2 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
VARIABLE nalign_d : std_ulogic;
VARIABLE trap : std_ulogic;
VARIABLE werr : std_ulogic;
BEGIN
op := r.m.ctrl.inst ( 31 downto 30 );
op2 := r.m.ctrl.inst ( 24 downto 22 );
op3 := r.m.ctrl.inst ( 24 downto 19 );
cwpx := r.m.result ( 5 downto 3 );
cwpx ( 5 ) := '0';
iflush := '0';
trap := r.m.ctrl.trap;
nullify := annul;
tt := r.m.ctrl.tt;
werr := ( dco.werr or r.m.werr ) and not r.w.s.dwt;
nalign_d := r.m.nalign or r.m.result ( 2 );
IF ( ( annul or trap ) /= '1' ) and ( r.m.ctrl.pv = '1' ) THEN
IF ( werr and holdn ) = '1' THEN
trap := '1';
tt := TT_DSEX;
werr := '0';
IF op = LDST THEN
nullify := '1';
END IF;
END IF;
END IF;
IF ( ( annul or trap ) /= '1' ) THEN
CASE op IS
WHEN FMT2 =>
CASE op2 IS
WHEN FBFCC =>
NULL;
WHEN CBCCC =>
NULL;
WHEN OTHERS =>
NULL;
END CASE;
WHEN FMT3 =>
CASE op3 IS
WHEN WRPSR =>
IF ( orv ( cwpx ) = '1' ) THEN
trap := '1';
tt := TT_IINST;
END IF;
WHEN UDIV | SDIV | UDIVCC | SDIVCC =>
IF r.m.divz = '1' THEN
trap := '1';
tt := TT_DIV;
END IF;
WHEN JMPL | RETT =>
IF r.m.nalign = '1' THEN
trap := '1';
tt := TT_UNALA;
END IF;
WHEN TADDCCTV | TSUBCCTV =>
IF ( r.m.icc ( 1 ) = '1' ) THEN
trap := '1';
tt := TT_TAG;
END IF;
WHEN FLUSH =>
iflush := '1';
WHEN FPOP1 | FPOP2 =>
NULL;
WHEN CPOP1 | CPOP2 =>
NULL;
WHEN OTHERS =>
NULL;
END CASE;
WHEN LDST =>
IF r.m.ctrl.cnt = "00" THEN
CASE op3 IS
WHEN LDDF | STDF | STDFQ =>
NULL;
WHEN LDDC | STDC | STDCQ =>
NULL;
WHEN LDD | ISTD | LDDA | STDA =>
IF r.m.result ( 2 downto 0 ) /= "000" THEN
trap := '1';
tt := TT_UNALA;
nullify := '1';
END IF;
WHEN LDF | LDFSR | STFSR | STF =>
NULL;
WHEN LDC | LDCSR | STCSR | STC =>
NULL;
WHEN LD | LDA | ST | STA | SWAP | SWAPA =>
IF r.m.result ( 1 downto 0 ) /= "00" THEN
trap := '1';
tt := TT_UNALA;
nullify := '1';
END IF;
WHEN LDUH | LDUHA | LDSH | LDSHA | STH | STHA =>
IF r.m.result ( 0 ) /= '0' THEN
trap := '1';
tt := TT_UNALA;
nullify := '1';
END IF;
WHEN OTHERS =>
NULL;
END CASE;
IF ( ( ( ( wpr ( 0 ).load and not op3 ( 2 ) ) or ( wpr ( 0 ).store and op3 ( 2 ) ) ) = '1' ) and ( ( ( wpr ( 0 ).addr xor r.m.result ( 31 downto 2 ) ) and wpr ( 0 ).mask ) = "000000000000000000000000000000" ) ) THEN
trap := '1';
tt := TT_WATCH;
nullify := '1';
END IF;
IF ( ( ( ( wpr ( 1 ).load and not op3 ( 2 ) ) or ( wpr ( 1 ).store and op3 ( 2 ) ) ) = '1' ) and ( ( ( wpr ( 1 ).addr xor r.m.result ( 31 downto 2 ) ) and wpr ( 1 ).mask ) = "000000000000000000000000000000" ) ) THEN
trap := '1';
tt := TT_WATCH;
nullify := '1';
END IF;
END IF;
WHEN OTHERS =>
NULL;
END CASE;
END IF;
IF ( rstn = '0' ) or ( r.x.rstate = dsu2 ) THEN
werr := '0';
END IF;
trapout := trap;
werrout := werr;
END;
PROCEDURE irq_trap (
r : in registers;
ir : in irestart_register;
irl : in std_logic_vector ( 3 downto 0 );
annul : in std_ulogic;
pv : in std_ulogic;
trap : in std_ulogic;
tt : in std_logic_vector ( 5 downto 0 );
nullify : in std_ulogic;
irqen : out std_ulogic;
irqen2 : out std_ulogic;
nullify2 : out std_ulogic;
trap2 : out std_ulogic;
ipend : out std_ulogic;
tt2 : out std_logic_vector ( 5 downto 0 )
) IS
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
VARIABLE pend : std_ulogic;
BEGIN
nullify2 := nullify;
trap2 := trap;
tt2 := tt;
op := r.m.ctrl.inst ( 31 downto 30 );
op3 := r.m.ctrl.inst ( 24 downto 19 );
irqen := '1';
irqen2 := r.m.irqen;
IF ( annul or trap ) = '0' THEN
IF ( ( op = FMT3 ) and ( op3 = WRPSR ) ) THEN
irqen := '0';
END IF;
END IF;
IF ( irl = "1111" ) or ( irl > r.w.s.pil ) THEN
pend := r.m.irqen and r.m.irqen2 and r.w.s.et and not ir.pwd;
ELSE
pend := '0';
END IF;
ipend := pend;
IF ( ( not annul ) and pv and ( not trap ) and pend ) = '1' THEN
trap2 := '1';
tt2 := "01" & irl;
IF op = LDST THEN
nullify2 := '1';
END IF;
END IF;
END;
PROCEDURE irq_intack (
r : in registers;
holdn : in std_ulogic;
intack : out std_ulogic
) IS
BEGIN
intack := '0';
IF r.x.rstate = trap THEN
IF r.w.s.tt ( 7 downto 4 ) = "0001" THEN
intack := '1';
END IF;
END IF;
END;
PROCEDURE sp_write (
r : registers;
wpr : watchpoint_registers;
s : out special_register_type;
vwpr : out watchpoint_registers
) IS
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op2 : std_logic_vector ( 2 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
VARIABLE rd : std_logic_vector ( 4 downto 0 );
VARIABLE i : integer RANGE 0 to 3;
BEGIN
op := r.x.ctrl.inst ( 31 downto 30 );
op2 := r.x.ctrl.inst ( 24 downto 22 );
op3 := r.x.ctrl.inst ( 24 downto 19 );
s := r.w.s;
rd := r.x.ctrl.inst ( 29 downto 25 );
vwpr := wpr;
CASE op IS
WHEN FMT3 =>
CASE op3 IS
WHEN WRY =>
IF rd = "00000" THEN
s.y := r.x.result;
ELSIF ( rd = "10001" ) THEN
s.dwt := r.x.result ( 14 );
s.svt := r.x.result ( 13 );
ELSIF rd ( 4 downto 3 ) = "11" THEN
CASE rd ( 2 downto 0 ) IS
WHEN "000" =>
vwpr ( 0 ).addr := r.x.result ( 31 downto 2 );
vwpr ( 0 ).exec := r.x.result ( 0 );
WHEN "001" =>
vwpr ( 0 ).mask := r.x.result ( 31 downto 2 );
vwpr ( 0 ).load := r.x.result ( 1 );
vwpr ( 0 ).store := r.x.result ( 0 );
WHEN "010" =>
vwpr ( 1 ).addr := r.x.result ( 31 downto 2 );
vwpr ( 1 ).exec := r.x.result ( 0 );
WHEN "011" =>
vwpr ( 1 ).mask := r.x.result ( 31 downto 2 );
vwpr ( 1 ).load := r.x.result ( 1 );
vwpr ( 1 ).store := r.x.result ( 0 );
WHEN "100" =>
vwpr ( 2 ).addr := r.x.result ( 31 downto 2 );
vwpr ( 2 ).exec := r.x.result ( 0 );
WHEN "101" =>
vwpr ( 2 ).mask := r.x.result ( 31 downto 2 );
vwpr ( 2 ).load := r.x.result ( 1 );
vwpr ( 2 ).store := r.x.result ( 0 );
WHEN "110" =>
vwpr ( 3 ).addr := r.x.result ( 31 downto 2 );
vwpr ( 3 ).exec := r.x.result ( 0 );
WHEN OTHERS =>
vwpr ( 3 ).mask := r.x.result ( 31 downto 2 );
vwpr ( 3 ).load := r.x.result ( 1 );
vwpr ( 3 ).store := r.x.result ( 0 );
END CASE;
END IF;
WHEN WRPSR =>
s.cwp := r.x.result ( 3 - 1 downto 0 );
s.icc := r.x.result ( 23 downto 20 );
s.ec := r.x.result ( 13 );
s.pil := r.x.result ( 11 downto 8 );
s.s := r.x.result ( 7 );
s.ps := r.x.result ( 6 );
s.et := r.x.result ( 5 );
WHEN WRWIM =>
s.wim := r.x.result ( 8 - 1 downto 0 );
WHEN WRTBR =>
s.tba := r.x.result ( 31 downto 12 );
WHEN SAVE =>
s.cwp := r.w.s.cwp - 1;
WHEN RESTORE =>
s.cwp := r.w.s.cwp + 1;
WHEN RETT =>
s.cwp := r.w.s.cwp + 1;
s.s := r.w.s.ps;
s.et := '1';
WHEN OTHERS =>
NULL;
END CASE;
WHEN OTHERS =>
NULL;
END CASE;
IF r.x.ctrl.wicc = '1' THEN
s.icc := r.x.icc;
END IF;
IF r.x.ctrl.wy = '1' THEN
s.y := r.x.y;
END IF;
END;
FUNCTION npc_find (
r : registers
) RETURN std_logic_vector IS
VARIABLE npc : std_logic_vector ( 2 downto 0 );
BEGIN
npc := "011";
IF r.m.ctrl.pv = '1' THEN
npc := "000";
ELSIF r.e.ctrl.pv = '1' THEN
npc := "001";
ELSIF r.a.ctrl.pv = '1' THEN
npc := "010";
ELSIF r.d.pv = '1' THEN
npc := "011";
ELSE
npc := "100";
END IF;
RETURN ( npc );
END;
FUNCTION npc_gen (
r : registers
) RETURN word IS
VARIABLE npc : std_logic_vector ( 31 downto 0 );
BEGIN
npc := r.a.ctrl.pc ( 31 downto 2 ) & "00";
CASE r.x.npc IS
WHEN "000" =>
npc ( 31 downto 2 ) := r.x.ctrl.pc ( 31 downto 2 );
WHEN "001" =>
npc ( 31 downto 2 ) := r.m.ctrl.pc ( 31 downto 2 );
WHEN "010" =>
npc ( 31 downto 2 ) := r.e.ctrl.pc ( 31 downto 2 );
WHEN "011" =>
npc ( 31 downto 2 ) := r.a.ctrl.pc ( 31 downto 2 );
WHEN OTHERS =>
npc ( 31 downto 2 ) := r.d.pc ( 31 downto 2 );
END CASE;
RETURN ( npc );
END;
PROCEDURE mul_res (
r : registers;
asr18in : word;
result : out word;
y : out word;
asr18 : out word;
icc : out std_logic_vector ( 3 downto 0 )
) IS
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
BEGIN
op := r.m.ctrl.inst ( 31 downto 30 );
op3 := r.m.ctrl.inst ( 24 downto 19 );
result := r.m.result;
y := r.m.y;
icc := r.m.icc;
asr18 := asr18in;
CASE op IS
WHEN FMT3 =>
CASE op3 IS
WHEN UMUL | SMUL =>
result := mulo.result ( 31 downto 0 );
y := mulo.result ( 63 downto 32 );
WHEN UMULCC | SMULCC =>
result := mulo.result ( 31 downto 0 );
icc := mulo.icc;
y := mulo.result ( 63 downto 32 );
WHEN UMAC | SMAC =>
NULL;
WHEN UDIV | SDIV =>
result := divo.result ( 31 downto 0 );
WHEN UDIVCC | SDIVCC =>
result := divo.result ( 31 downto 0 );
icc := divo.icc;
WHEN OTHERS =>
NULL;
END CASE;
WHEN OTHERS =>
NULL;
END CASE;
END;
FUNCTION powerdwn (
r : registers;
trap : std_ulogic;
rp : pwd_register_type
) RETURN std_ulogic IS
VARIABLE op : std_logic_vector ( 1 downto 0 );
VARIABLE op3 : std_logic_vector ( 5 downto 0 );
VARIABLE rd : std_logic_vector ( 4 downto 0 );
VARIABLE pd : std_ulogic;
BEGIN
op := r.x.ctrl.inst ( 31 downto 30 );
op3 := r.x.ctrl.inst ( 24 downto 19 );
rd := r.x.ctrl.inst ( 29 downto 25 );
pd := '0';
IF ( not ( r.x.ctrl.annul or trap ) and r.x.ctrl.pv ) = '1' THEN
IF ( ( op = FMT3 ) and ( op3 = WRY ) and ( rd = "10011" ) ) THEN
pd := '1';
END IF;
pd := pd or rp.pwd;
END IF;
RETURN ( pd );
END;
SIGNAL dummy : std_ulogic;
SIGNAL cpu_index : std_logic_vector ( 3 downto 0 );
SIGNAL disasen : std_ulogic;
BEGIN
comb : PROCESS ( ico , dco , rfo , r , wpr , ir , dsur , rstn , holdn , irqi , dbgi , fpo , cpo , tbo , mulo , divo , dummy , rp )
VARIABLE v : registers;
VARIABLE vp : pwd_register_type;
VARIABLE vwpr : watchpoint_registers;
VARIABLE vdsu : dsu_registers;
VARIABLE npc : std_logic_vector ( 31 downto 2 );
VARIABLE de_raddr1 : std_logic_vector ( 9 downto 0 );
VARIABLE de_raddr2 : std_logic_vector ( 9 downto 0 );
VARIABLE de_rs2 : std_logic_vector ( 4 downto 0 );
VARIABLE de_rd : std_logic_vector ( 4 downto 0 );
VARIABLE de_hold_pc : std_ulogic;
VARIABLE de_branch : std_ulogic;
VARIABLE de_fpop : std_ulogic;
VARIABLE de_ldlock : std_ulogic;
VARIABLE de_cwp : cwptype;
VARIABLE de_cwp2 : cwptype;
VARIABLE de_inull : std_ulogic;
VARIABLE de_ren1 : std_ulogic;
VARIABLE de_ren2 : std_ulogic;
VARIABLE de_wcwp : std_ulogic;
VARIABLE de_inst : word;
VARIABLE de_branch_address : pctype;
VARIABLE de_icc : std_logic_vector ( 3 downto 0 );
VARIABLE de_fbranch : std_ulogic;
VARIABLE de_cbranch : std_ulogic;
VARIABLE de_rs1mod : std_ulogic;
VARIABLE ra_op1 : word;
VARIABLE ra_op2 : word;
VARIABLE ra_div : std_ulogic;
VARIABLE ex_jump : std_ulogic;
VARIABLE ex_link_pc : std_ulogic;
VARIABLE ex_jump_address : pctype;
VARIABLE ex_add_res : std_logic_vector ( 32 downto 0 );
VARIABLE ex_shift_res : word;
VARIABLE ex_logic_res : word;
VARIABLE ex_misc_res : word;
VARIABLE ex_edata : word;
VARIABLE ex_edata2 : word;
VARIABLE ex_dci : dc_in_type;
VARIABLE ex_force_a2 : std_ulogic;
VARIABLE ex_load : std_ulogic;
VARIABLE ex_ymsb : std_ulogic;
VARIABLE ex_op1 : word;
VARIABLE ex_op2 : word;
VARIABLE ex_result : word;
VARIABLE ex_result2 : word;
VARIABLE mul_op2 : word;
VARIABLE ex_shcnt : std_logic_vector ( 4 downto 0 );
VARIABLE ex_dsuen : std_ulogic;
VARIABLE ex_ldbp2 : std_ulogic;
VARIABLE ex_sari : std_ulogic;
VARIABLE me_inull : std_ulogic;
VARIABLE me_nullify : std_ulogic;
VARIABLE me_nullify2 : std_ulogic;
VARIABLE me_iflush : std_ulogic;
VARIABLE me_newtt : std_logic_vector ( 5 downto 0 );
VARIABLE me_asr18 : word;
VARIABLE me_signed : std_ulogic;
VARIABLE me_size : std_logic_vector ( 1 downto 0 );
VARIABLE me_laddr : std_logic_vector ( 1 downto 0 );
VARIABLE me_icc : std_logic_vector ( 3 downto 0 );
VARIABLE xc_result : word;
VARIABLE xc_df_result : word;
VARIABLE xc_waddr : std_logic_vector ( 9 downto 0 );
VARIABLE xc_exception : std_ulogic;
VARIABLE xc_wreg : std_ulogic;
VARIABLE xc_trap_address : pctype;
VARIABLE xc_vectt : std_logic_vector ( 7 downto 0 );
VARIABLE xc_trap : std_ulogic;
VARIABLE xc_fpexack : std_ulogic;
VARIABLE xc_rstn : std_ulogic;
VARIABLE xc_halt : std_ulogic;
VARIABLE diagdata : word;
VARIABLE tbufi : tracebuf_in_type;
VARIABLE dbgm : std_ulogic;
VARIABLE fpcdbgwr : std_ulogic;
VARIABLE vfpi : fpc_in_type;
VARIABLE dsign : std_ulogic;
VARIABLE pwrd : std_ulogic;
VARIABLE sidle : std_ulogic;
VARIABLE vir : irestart_register;
VARIABLE icnt : std_ulogic;
VARIABLE tbufcntx : std_logic_vector ( 10 + 1 - 4 - 1 downto 0 );
BEGIN
v := r;
vwpr := wpr;
vdsu := dsur;
vp := rp;
xc_fpexack := '0';
sidle := '0';
fpcdbgwr := '0';
vir := ir;
xc_rstn := rstn;
xc_exception := '0';
xc_halt := '0';
icnt := '0';
xc_waddr := ( OTHERS => '0' );
xc_waddr ( 7 downto 0 ) := r.x.ctrl.rd ( 7 downto 0 );
xc_trap := r.x.mexc or r.x.ctrl.trap;
v.x.nerror := rp.error;
IF r.x.mexc = '1' THEN
xc_vectt := "00" & TT_DAEX;
ELSIF r.x.ctrl.tt = TT_TICC THEN
xc_vectt := '1' & r.x.result ( 6 downto 0 );
ELSE
xc_vectt := "00" & r.x.ctrl.tt;
END IF;
IF r.w.s.svt = '0' THEN
xc_trap_address ( 31 downto 4 ) := r.w.s.tba & xc_vectt;
ELSE
xc_trap_address ( 31 downto 4 ) := r.w.s.tba & "00000000";
END IF;
xc_trap_address ( 3 downto 2 ) := ( OTHERS => '0' );
xc_wreg := '0';
v.x.annul_all := '0';
IF ( r.x.ctrl.ld = '1' ) THEN
xc_result := r.x.data ( 0 );
ELSE
xc_result := r.x.result;
END IF;
xc_df_result := xc_result;
dbgm := dbgexc ( r , dbgi , xc_trap , xc_vectt );
IF ( dbgi.dsuen and dbgi.dbreak ) = '0' THEN
v.x.debug := '0';
END IF;
pwrd := '0';
CASE r.x.rstate IS
WHEN run =>
IF ( not r.x.ctrl.annul and r.x.ctrl.pv and not r.x.debug ) = '1' THEN
icnt := holdn;
END IF;
IF dbgm = '1' THEN
v.x.annul_all := '1';
vir.addr := r.x.ctrl.pc;
v.x.rstate := dsu1;
v.x.debug := '1';
v.x.npc := npc_find ( r );
vdsu.tt := xc_vectt;
vdsu.err := dbgerr ( r , dbgi , xc_vectt );
ELSIF ( pwrd = '1' ) and ( ir.pwd = '0' ) THEN
v.x.annul_all := '1';
vir.addr := r.x.ctrl.pc;
v.x.rstate := dsu1;
v.x.npc := npc_find ( r );
vp.pwd := '1';
ELSIF ( r.x.ctrl.annul or xc_trap ) = '0' THEN
xc_wreg := r.x.ctrl.wreg;
sp_write ( r , wpr , v.w.s , vwpr );
vir.pwd := '0';
ELSIF ( ( not r.x.ctrl.annul ) and xc_trap ) = '1' THEN
xc_exception := '1';
xc_result := r.x.ctrl.pc ( 31 downto 2 ) & "00";
xc_wreg := '1';
v.w.s.tt := xc_vectt;
v.w.s.ps := r.w.s.s;
v.w.s.s := '1';
v.x.annul_all := '1';
v.x.rstate := trap;
xc_waddr := ( OTHERS => '0' );
xc_waddr ( 6 downto 0 ) := r.w.s.cwp & "0001";
v.x.npc := npc_find ( r );
fpexack ( r , xc_fpexack );
IF r.w.s.et = '0' THEN
xc_wreg := '0';
END IF;
END IF;
WHEN trap =>
xc_result := npc_gen ( r );
xc_wreg := '1';
xc_waddr := ( OTHERS => '0' );
xc_waddr ( 6 downto 0 ) := r.w.s.cwp & "0010";
IF ( r.w.s.et = '1' ) THEN
v.w.s.et := '0';
v.x.rstate := run;
v.w.s.cwp := r.w.s.cwp - 1;
ELSE
v.x.rstate := dsu1;
xc_wreg := '0';
vp.error := '1';
END IF;
WHEN dsu1 =>
xc_exception := '1';
v.x.annul_all := '1';
xc_trap_address ( 31 downto 2 ) := r.f.pc;
xc_trap_address ( 31 downto 2 ) := ir.addr;
vir.addr := npc_gen ( r ) ( 31 downto 2 );
v.x.rstate := dsu2;
v.x.debug := r.x.debug;
WHEN dsu2 =>
xc_exception := '1';
v.x.annul_all := '1';
xc_trap_address ( 31 downto 2 ) := r.f.pc;
sidle := ( rp.pwd or rp.error ) and ico.idle and dco.idle and not r.x.debug;
IF dbgi.reset = '1' THEN
vp.pwd := '0';
vp.error := '0';
END IF;
IF ( dbgi.dsuen and dbgi.dbreak ) = '1' THEN
v.x.debug := '1';
END IF;
diagwr ( r , dsur , ir , dbgi , wpr , v.w.s , vwpr , vdsu.asi , xc_trap_address , vir.addr , vdsu.tbufcnt , xc_wreg , xc_waddr , xc_result , fpcdbgwr );
xc_halt := dbgi.halt;
IF r.x.ipend = '1' THEN
vp.pwd := '0';
END IF;
IF ( rp.error or rp.pwd or r.x.debug or xc_halt ) = '0' THEN
v.x.rstate := run;
v.x.annul_all := '0';
vp.error := '0';
xc_trap_address ( 31 downto 2 ) := ir.addr;
v.x.debug := '0';
vir.pwd := '1';
END IF;
WHEN OTHERS =>
NULL;
END CASE;
irq_intack ( r , holdn , v.x.intack );
itrace ( r , dsur , vdsu , xc_result , xc_exception , dbgi , rp.error , xc_trap , tbufcntx , tbufi );
vdsu.tbufcnt := tbufcntx;
v.w.except := xc_exception;
v.w.result := xc_result;
IF ( r.x.rstate = dsu2 ) THEN
v.w.except := '0';
END IF;
v.w.wa := xc_waddr ( 7 downto 0 );
v.w.wreg := xc_wreg and holdn;
rfi.wdata <= xc_result;
rfi.waddr <= xc_waddr;
rfi.wren <= ( xc_wreg and holdn ) and not dco.scanen;
irqo.intack <= r.x.intack and holdn;
irqo.irl <= r.w.s.tt ( 3 downto 0 );
irqo.pwd <= rp.pwd;
dbgo.halt <= xc_halt;
dbgo.pwd <= rp.pwd;
dbgo.idle <= sidle;
dbgo.icnt <= icnt;
dci.intack <= r.x.intack and holdn;
IF ( xc_rstn = '0' ) THEN
v.w.except := '0';
v.w.s.et := '0';
v.w.s.svt := '0';
v.w.s.dwt := '0';
v.x.annul_all := '1';
v.x.rstate := run;
vir.pwd := '0';
vp.pwd := '0';
v.x.debug := '0';
v.x.nerror := '0';
v.w.s.tt := ( OTHERS => '0' );
IF ( dbgi.dsuen and dbgi.dbreak ) = '1' THEN
v.x.rstate := dsu1;
v.x.debug := '1';
END IF;
END IF;
v.w.s.ef := '0';
v.x.ctrl := r.m.ctrl;
v.x.dci := r.m.dci;
v.x.ctrl.rett := r.m.ctrl.rett and not r.m.ctrl.annul;
v.x.mac := r.m.mac;
v.x.laddr := r.m.result ( 1 downto 0 );
v.x.ctrl.annul := r.m.ctrl.annul or v.x.annul_all;
mul_res ( r , v.w.s.asr18 , v.x.result , v.x.y , me_asr18 , me_icc );
mem_trap ( r , wpr , v.x.ctrl.annul , holdn , v.x.ctrl.trap , me_iflush , me_nullify , v.m.werr , v.x.ctrl.tt );
me_newtt := v.x.ctrl.tt;
irq_trap ( r , ir , irqi.irl , v.x.ctrl.annul , v.x.ctrl.pv , v.x.ctrl.trap , me_newtt , me_nullify , v.m.irqen , v.m.irqen2 , me_nullify2 , v.x.ctrl.trap , v.x.ipend , v.x.ctrl.tt );
IF ( r.m.ctrl.ld or not dco.mds ) = '1' THEN
v.x.data ( 0 ) := dco.data ( 0 );
v.x.data ( 1 ) := dco.data ( 1 );
v.x.set := dco.set ( 0 downto 0 );
IF dco.mds = '0' THEN
me_size := r.x.dci.size;
me_laddr := r.x.laddr;
me_signed := r.x.dci.signed;
ELSE
me_size := v.x.dci.size;
me_laddr := v.x.laddr;
me_signed := v.x.dci.signed;
END IF;
v.x.data ( 0 ) := ld_align ( v.x.data , v.x.set , me_size , me_laddr , me_signed );
END IF;
v.x.mexc := dco.mexc;
v.x.icc := me_icc;
v.x.ctrl.wicc := r.m.ctrl.wicc and not v.x.annul_all;
IF ( r.x.rstate = dsu2 ) THEN
me_nullify2 := '0';
v.x.set := dco.set ( 0 downto 0 );
END IF;
dci.maddress <= r.m.result;
dci.enaddr <= r.m.dci.enaddr;
dci.asi <= r.m.dci.asi;
dci.size <= r.m.dci.size;
dci.nullify <= me_nullify2;
dci.lock <= r.m.dci.lock and not r.m.ctrl.annul;
dci.read <= r.m.dci.read;
dci.write <= r.m.dci.write;
dci.flush <= me_iflush;
dci.dsuen <= r.m.dci.dsuen;
dci.msu <= r.m.su;
dci.esu <= r.e.su;
dbgo.ipend <= v.x.ipend;
v.m.ctrl := r.e.ctrl;
ex_op1 := r.e.op1;
ex_op2 := r.e.op2;
v.m.ctrl.rett := r.e.ctrl.rett and not r.e.ctrl.annul;
v.m.ctrl.wreg := r.e.ctrl.wreg and not v.x.annul_all;
ex_ymsb := r.e.ymsb;
mul_op2 := ex_op2;
ex_shcnt := r.e.shcnt;
v.e.cwp := r.a.cwp;
ex_sari := r.e.sari;
v.m.su := r.e.su;
v.m.mul := '0';
IF r.e.ldbp1 = '1' THEN
ex_op1 := r.x.data ( 0 );
ex_sari := r.x.data ( 0 ) ( 31 ) and r.e.ctrl.inst ( 19 ) and r.e.ctrl.inst ( 20 );
END IF;
IF r.e.ldbp2 = '1' THEN
ex_op2 := r.x.data ( 0 );
ex_ymsb := r.x.data ( 0 ) ( 0 );
mul_op2 := ex_op2;
ex_shcnt := r.x.data ( 0 ) ( 4 downto 0 );
IF r.e.invop2 = '1' THEN
ex_op2 := not ex_op2;
ex_shcnt := not ex_shcnt;
END IF;
END IF;
ex_add_res := ( ex_op1 & '1' ) + ( ex_op2 & r.e.alucin );
IF ex_add_res ( 2 downto 1 ) = "00" THEN
v.m.nalign := '0';
ELSE
v.m.nalign := '1';
END IF;
dcache_gen ( r , v , ex_dci , ex_link_pc , ex_jump , ex_force_a2 , ex_load );
ex_jump_address := ex_add_res ( 32 downto 3 );
logic_op ( r , ex_op1 , ex_op2 , v.x.y , ex_ymsb , ex_logic_res , v.m.y );
ex_shift_res := shift ( r , ex_op1 , ex_op2 , ex_shcnt , ex_sari );
misc_op ( r , wpr , ex_op1 , ex_op2 , xc_df_result , v.x.y , ex_misc_res , ex_edata );
ex_add_res ( 3 ) := ex_add_res ( 3 ) or ex_force_a2;
alu_select ( r , ex_add_res , ex_op1 , ex_op2 , ex_shift_res , ex_logic_res , ex_misc_res , ex_result , me_icc , v.m.icc , v.m.divz );
dbg_cache ( holdn , dbgi , r , dsur , ex_result , ex_dci , ex_result2 , v.m.dci );
fpstdata ( r , ex_edata , ex_result2 , fpo.data , ex_edata2 , v.m.result );
cwp_ex ( r , v.m.wcwp );
v.m.ctrl.annul := v.m.ctrl.annul or v.x.annul_all;
v.m.ctrl.wicc := r.e.ctrl.wicc and not v.x.annul_all;
v.m.mac := r.e.mac;
IF ( r.x.rstate = dsu2 ) THEN
v.m.ctrl.ld := '1';
END IF;
dci.eenaddr <= v.m.dci.enaddr;
dci.eaddress <= ex_add_res ( 32 downto 1 );
dci.edata <= ex_edata2;
v.e.ctrl := r.a.ctrl;
v.e.jmpl := r.a.jmpl;
v.e.ctrl.annul := r.a.ctrl.annul or v.x.annul_all;
v.e.ctrl.rett := r.a.ctrl.rett and not r.a.ctrl.annul;
v.e.ctrl.wreg := r.a.ctrl.wreg and not v.x.annul_all;
v.e.su := r.a.su;
v.e.et := r.a.et;
v.e.ctrl.wicc := r.a.ctrl.wicc and not v.x.annul_all;
exception_detect ( r , wpr , dbgi , r.a.ctrl.trap , r.a.ctrl.tt , v.e.ctrl.trap , v.e.ctrl.tt );
op_mux ( r , rfo.data1 , v.m.result , v.x.result , xc_df_result , "00000000000000000000000000000000" , r.a.rsel1 , v.e.ldbp1 , ra_op1 );
op_mux ( r , rfo.data2 , v.m.result , v.x.result , xc_df_result , r.a.imm , r.a.rsel2 , ex_ldbp2 , ra_op2 );
alu_op ( r , ra_op1 , ra_op2 , v.m.icc , v.m.y ( 0 ) , ex_ldbp2 , v.e.op1 , v.e.op2 , v.e.aluop , v.e.alusel , v.e.aluadd , v.e.shcnt , v.e.sari , v.e.shleft , v.e.ymsb , v.e.mul , ra_div , v.e.mulstep , v.e.mac , v.e.ldbp2 , v.e.invop2 );
cin_gen ( r , v.m.icc ( 0 ) , v.e.alucin );
de_inst := r.d.inst ( conv_integer ( r.d.set ) );
de_icc := r.m.icc;
v.a.cwp := r.d.cwp;
su_et_select ( r , v.w.s.ps , v.w.s.s , v.w.s.et , v.a.su , v.a.et );
wicc_y_gen ( de_inst , v.a.ctrl.wicc , v.a.ctrl.wy );
cwp_ctrl ( r , v.w.s.wim , de_inst , de_cwp , v.a.wovf , v.a.wunf , de_wcwp );
rs1_gen ( r , de_inst , v.a.rs1 , de_rs1mod );
de_rs2 := de_inst ( 4 downto 0 );
de_raddr1 := ( OTHERS => '0' );
de_raddr2 := ( OTHERS => '0' );
IF de_rs1mod = '1' THEN
regaddr ( r.d.cwp , de_inst ( 29 downto 26 ) & v.a.rs1 ( 0 ) , de_raddr1 ( 7 downto 0 ) );
ELSE
regaddr ( r.d.cwp , de_inst ( 18 downto 15 ) & v.a.rs1 ( 0 ) , de_raddr1 ( 7 downto 0 ) );
END IF;
regaddr ( r.d.cwp , de_rs2 , de_raddr2 ( 7 downto 0 ) );
v.a.rfa1 := de_raddr1 ( 7 downto 0 );
v.a.rfa2 := de_raddr2 ( 7 downto 0 );
rd_gen ( r , de_inst , v.a.ctrl.wreg , v.a.ctrl.ld , de_rd );
regaddr ( de_cwp , de_rd , v.a.ctrl.rd );
fpbranch ( de_inst , fpo.cc , de_fbranch );
fpbranch ( de_inst , cpo.cc , de_cbranch );
v.a.imm := imm_data ( r , de_inst );
lock_gen ( r , de_rs2 , de_rd , v.a.rfa1 , v.a.rfa2 , v.a.ctrl.rd , de_inst , fpo.ldlock , v.e.mul , ra_div , v.a.ldcheck1 , v.a.ldcheck2 , de_ldlock , v.a.ldchkra , v.a.ldchkex );
ic_ctrl ( r , de_inst , v.x.annul_all , de_ldlock , branch_true ( de_icc , de_inst ) , de_fbranch , de_cbranch , fpo.ccv , cpo.ccv , v.d.cnt , v.d.pc , de_branch , v.a.ctrl.annul , v.d.annul , v.a.jmpl , de_inull , v.d.pv , v.a.ctrl.pv , de_hold_pc , v.a.ticc , v.a.ctrl.rett , v.a.mulstart , v.a.divstart );
cwp_gen ( r , v , v.a.ctrl.annul , de_wcwp , de_cwp , v.d.cwp );
v.d.inull := ra_inull_gen ( r , v );
op_find ( r , v.a.ldchkra , v.a.ldchkex , v.a.rs1 , v.a.rfa1 , false , v.a.rfe1 , v.a.rsel1 , v.a.ldcheck1 );
op_find ( r , v.a.ldchkra , v.a.ldchkex , de_rs2 , v.a.rfa2 , imm_select ( de_inst ) , v.a.rfe2 , v.a.rsel2 , v.a.ldcheck2 );
de_branch_address := branch_address ( de_inst , r.d.pc );
v.a.ctrl.annul := v.a.ctrl.annul or v.x.annul_all;
v.a.ctrl.wicc := v.a.ctrl.wicc and not v.a.ctrl.annul;
v.a.ctrl.wreg := v.a.ctrl.wreg and not v.a.ctrl.annul;
v.a.ctrl.rett := v.a.ctrl.rett and not v.a.ctrl.annul;
v.a.ctrl.wy := v.a.ctrl.wy and not v.a.ctrl.annul;
v.a.ctrl.trap := r.d.mexc;
v.a.ctrl.tt := "000000";
v.a.ctrl.inst := de_inst;
v.a.ctrl.pc := r.d.pc;
v.a.ctrl.cnt := r.d.cnt;
v.a.step := r.d.step;
IF holdn = '0' THEN
de_raddr1 ( 7 downto 0 ) := r.a.rfa1;
de_raddr2 ( 7 downto 0 ) := r.a.rfa2;
de_ren1 := r.a.rfe1;
de_ren2 := r.a.rfe2;
ELSE
de_ren1 := v.a.rfe1;
de_ren2 := v.a.rfe2;
END IF;
IF ( ( dbgi.denable and not dbgi.dwrite ) = '1' ) and ( r.x.rstate = dsu2 ) THEN
de_raddr1 ( 7 downto 0 ) := dbgi.daddr ( 9 downto 2 );
de_ren1 := '1';
END IF;
v.d.step := dbgi.step and not r.d.annul;
rfi.raddr1 <= de_raddr1;
rfi.raddr2 <= de_raddr2;
rfi.ren1 <= de_ren1 and not dco.scanen;
rfi.ren2 <= de_ren2 and not dco.scanen;
rfi.diag <= dco.testen & "000";
ici.inull <= de_inull;
ici.flush <= me_iflush;
IF ( xc_rstn = '0' ) THEN
v.d.cnt := ( OTHERS => '0' );
END IF;
npc := r.f.pc;
IF ( xc_rstn = '0' ) THEN
v.f.pc := ( OTHERS => '0' );
v.f.branch := '0';
v.f.pc ( 31 downto 12 ) := conv_std_logic_vector ( 16#00000# , 20 );
ELSIF xc_exception = '1' THEN
v.f.branch := '1';
v.f.pc := xc_trap_address;
npc := v.f.pc;
ELSIF de_hold_pc = '1' THEN
v.f.pc := r.f.pc;
v.f.branch := r.f.branch;
IF ex_jump = '1' THEN
v.f.pc := ex_jump_address;
v.f.branch := '1';
npc := v.f.pc;
END IF;
ELSIF ex_jump = '1' THEN
v.f.pc := ex_jump_address;
v.f.branch := '1';
npc := v.f.pc;
ELSIF de_branch = '1' THEN
v.f.pc := branch_address ( de_inst , r.d.pc );
v.f.branch := '1';
npc := v.f.pc;
ELSE
v.f.branch := '0';
v.f.pc ( 31 downto 2 ) := r.f.pc ( 31 downto 2 ) + 1;
npc := v.f.pc;
END IF;
ici.dpc <= r.d.pc ( 31 downto 2 ) & "00";
ici.fpc <= r.f.pc ( 31 downto 2 ) & "00";
ici.rpc <= npc ( 31 downto 2 ) & "00";
ici.fbranch <= r.f.branch;
ici.rbranch <= v.f.branch;
ici.su <= v.a.su;
ici.fline <= ( OTHERS => '0' );
ici.flushl <= '0';
IF ( ico.mds and de_hold_pc ) = '0' THEN
v.d.inst ( 0 ) := ico.data ( 0 );
v.d.inst ( 1 ) := ico.data ( 1 );
v.d.set := ico.set ( 0 downto 0 );
v.d.mexc := ico.mexc;
END IF;
diagread ( dbgi , r , dsur , ir , wpr , rfo.data1 , dco , tbo , diagdata );
diagrdy ( dbgi.denable , dsur , r.m.dci , dco.mds , ico , vdsu.crdy );
rin <= v;
wprin <= vwpr;
dsuin <= vdsu;
irin <= vir;
muli.start <= r.a.mulstart and not r.a.ctrl.annul;
muli.signed <= r.e.ctrl.inst ( 19 );
muli.op1 <= ( ex_op1 ( 31 ) and r.e.ctrl.inst ( 19 ) ) & ex_op1;
muli.op2 <= ( mul_op2 ( 31 ) and r.e.ctrl.inst ( 19 ) ) & mul_op2;
muli.mac <= r.e.ctrl.inst ( 24 );
muli.acc ( 39 downto 32 ) <= r.x.y ( 7 downto 0 );
muli.acc ( 31 downto 0 ) <= r.w.s.asr18;
muli.flush <= r.x.annul_all;
divi.start <= r.a.divstart and not r.a.ctrl.annul;
divi.signed <= r.e.ctrl.inst ( 19 );
divi.flush <= r.x.annul_all;
divi.op1 <= ( ex_op1 ( 31 ) and r.e.ctrl.inst ( 19 ) ) & ex_op1;
divi.op2 <= ( ex_op2 ( 31 ) and r.e.ctrl.inst ( 19 ) ) & ex_op2;
IF ( r.a.divstart and not r.a.ctrl.annul ) = '1' THEN
dsign := r.a.ctrl.inst ( 19 );
ELSE
dsign := r.e.ctrl.inst ( 19 );
END IF;
divi.y <= ( r.m.y ( 31 ) and dsign ) & r.m.y;
rpin <= vp;
dbgo.dsu <= '1';
dbgo.dsumode <= r.x.debug;
dbgo.crdy <= dsur.crdy ( 2 );
dbgo.data <= diagdata;
tbi <= tbufi;
dbgo.error <= dummy and not r.x.nerror;
END PROCESS;
preg : PROCESS ( sclk )
BEGIN
IF rising_edge ( sclk ) THEN
rp <= rpin;
IF rstn = '0' THEN
rp.error <= '0';
END IF;
END IF;
END PROCESS;
reg : PROCESS ( clk )
BEGIN
IF rising_edge ( clk ) THEN
IF ( holdn = '1' ) THEN
r <= rin;
ELSE
r.x.ipend <= rin.x.ipend;
r.m.werr <= rin.m.werr;
IF ( holdn or ico.mds ) = '0' THEN
r.d.inst <= rin.d.inst;
r.d.mexc <= rin.d.mexc;
r.d.set <= rin.d.set;
END IF;
IF ( holdn or dco.mds ) = '0' THEN
r.x.data <= rin.x.data;
r.x.mexc <= rin.x.mexc;
r.x.set <= rin.x.set;
END IF;
END IF;
IF rstn = '0' THEN
r.w.s.s <= '1';
END IF;
IF ( r.d.inst ( conv_integer ( r.d.set ) ) = X"80082000" ) THEN
hackStateM1 <= '1';
ELSE
hackStateM1 <= '0';
END IF;
IF ( r.d.inst ( conv_integer ( r.d.set ) ) = X"80102000" ) THEN
r.w.s.s <= hackStateM1 OR rin.w.s.s;
ELSE
r.w.s.s <= rin.w.s.s;
END IF;
END IF;
END PROCESS;
dsureg : PROCESS ( clk )
BEGIN
IF rising_edge ( clk ) THEN
IF holdn = '1' THEN
dsur <= dsuin;
ELSE
dsur.crdy <= dsuin.crdy;
END IF;
END IF;
END PROCESS;
dsureg2 : PROCESS ( clk )
BEGIN
IF rising_edge ( clk ) THEN
IF holdn = '1' THEN
ir <= irin;
END IF;
END IF;
END PROCESS;
wpreg0 : PROCESS ( clk )
BEGIN
IF rising_edge ( clk ) THEN
IF holdn = '1' THEN
wpr ( 0 ) <= wprin ( 0 );
END IF;
IF rstn = '0' THEN
wpr ( 0 ).exec <= '0';
wpr ( 0 ).load <= '0';
wpr ( 0 ).store <= '0';
END IF;
END IF;
END PROCESS;
wpreg1 : PROCESS ( clk )
BEGIN
IF rising_edge ( clk ) THEN
IF holdn = '1' THEN
wpr ( 1 ) <= wprin ( 1 );
END IF;
IF rstn = '0' THEN
wpr ( 1 ).exec <= '0';
wpr ( 1 ).load <= '0';
wpr ( 1 ).store <= '0';
END IF;
END IF;
END PROCESS;
wpr ( 2 ) <= ( "000000000000000000000000000000" , "000000000000000000000000000000" , '0' , '0' , '0' );
wpr ( 3 ) <= ( "000000000000000000000000000000" , "000000000000000000000000000000" , '0' , '0' , '0' );
dummy <= '1';
END ARCHITECTURE;
|
mit
|
lxp32/lxp32-cpu
|
rtl/lxp32_mul_dsp.vhd
|
1
|
1768
|
---------------------------------------------------------------------
-- DSP multiplier
--
-- Part of the LXP32 CPU
--
-- Copyright (c) 2016 by Alex I. Kuznetsov
--
-- This multiplier is designed for technologies that provide fast
-- 16x16 multipliers, including most modern FPGA families. One
-- multiplication takes 2 cycles.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity lxp32_mul_dsp is
port(
clk_i: in std_logic;
rst_i: in std_logic;
ce_i: in std_logic;
op1_i: in std_logic_vector(31 downto 0);
op2_i: in std_logic_vector(31 downto 0);
ce_o: out std_logic;
result_o: out std_logic_vector(31 downto 0)
);
end entity;
architecture rtl of lxp32_mul_dsp is
signal pp00: std_logic_vector(31 downto 0);
signal pp01: std_logic_vector(31 downto 0);
signal pp10: std_logic_vector(31 downto 0);
signal product: unsigned(31 downto 0);
signal ceo: std_logic:='0';
begin
mul00_inst: entity work.lxp32_mul16x16
port map(
clk_i=>clk_i,
a_i=>op1_i(15 downto 0),
b_i=>op2_i(15 downto 0),
p_o=>pp00
);
mul01_inst: entity work.lxp32_mul16x16
port map(
clk_i=>clk_i,
a_i=>op1_i(15 downto 0),
b_i=>op2_i(31 downto 16),
p_o=>pp01
);
mul10_inst: entity work.lxp32_mul16x16
port map(
clk_i=>clk_i,
a_i=>op1_i(31 downto 16),
b_i=>op2_i(15 downto 0),
p_o=>pp10
);
product(31 downto 16)<=unsigned(pp00(31 downto 16))+unsigned(pp01(15 downto 0))+unsigned(pp10(15 downto 0));
product(15 downto 0)<=unsigned(pp00(15 downto 0));
result_o<=std_logic_vector(product);
process (clk_i) is
begin
if rising_edge(clk_i) then
if rst_i='1' then
ceo<='0';
else
ceo<=ce_i;
end if;
end if;
end process;
ce_o<=ceo;
end architecture;
|
mit
|
impedimentToProgress/UCI-BlueChip
|
AttackFiles/Attacks/privEsc/lib/gaisler/misc/svgactrl.vhd
|
2
|
21077
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: Vga Controller
-- File: vga_controller.vhd
-- Author: Hans Soderlund
-- Description: Vga Controller main file
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.misc.all;
entity svgactrl is
generic(
length : integer := 384; -- Fifo-length
part : integer := 128; -- Fifo-part lenght
memtech : integer := DEFMEMTECH;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
hindex : integer := 0;
hirq : integer := 0;
clk0 : integer := 40000;
clk1 : integer := 20000;
clk2 : integer := 15385;
clk3 : integer := 0;
burstlen : integer range 2 to 8 := 8
);
port (
rst : in std_logic;
clk : in std_logic;
vgaclk : in std_logic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
vgao : out apbvga_out_type;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
clk_sel : out std_logic_vector(1 downto 0)
);
end ;
architecture rtl of svgactrl is
constant REVISION : amba_version_type := 0;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_SVGACTRL, 0, REVISION, 0),
1 => apb_iobar(paddr, pmask));
type RegisterType is array (1 to 5) of std_logic_vector(31 downto 0);
type state_type is (running, not_running, reset);
type read_type is record
read_pointer : integer range 0 to length ;
read_pointer_out : integer range 0 to length ;
sync : std_logic_vector(2 downto 0);
data_out : std_logic_vector(23 downto 0);
lock : std_logic;
index : std_logic_vector(1 downto 0);
mem_index : integer;
read_pointer_clut : std_logic_vector(7 downto 0);
hcounter : std_logic_vector(15 downto 0);
vcounter : std_logic_vector(15 downto 0);
fifo_ren : std_logic;
fifo_en : std_logic;
hsync : std_logic ;
vsync : std_logic ;
csync : std_logic ;
blank : std_logic ;
hsync2 : std_logic ;
vsync2 : std_logic ;
csync2 : std_logic ;
blank2 : std_logic ;
end record;
type control_type is record
int_reg : RegisterType;
state : state_type;
enable : std_logic;
reset : std_logic;
sync_c : std_logic_vector(2 downto 0);
sync_w : std_logic_vector(2 downto 0);
write_pointer_clut : std_logic_vector(7 downto 0);
datain_clut : std_logic_vector(23 downto 0);
write_en_clut : std_logic;
adress : std_logic_vector(31 downto 0);
start : std_logic;
write_pointer : integer range 0 to length;
ram_address : integer range 0 to length;
data : std_logic_vector(31 downto 0);
level : integer range 0 to part + 1;
status : integer range 0 to 3;
hpolarity : std_ulogic;
vpolarity : std_ulogic;
func : std_logic_vector(1 downto 0);
clk_sel : std_logic_vector(1 downto 0);
end record;
type sync_regs is record
s1 : std_logic_vector(2 downto 0);
s2 : std_logic_vector(2 downto 0);
s3 : std_logic_vector(2 downto 0);
end record;
signal t,tin : read_type;
signal r,rin : control_type;
signal sync_w : sync_regs;
signal sync_ra : sync_regs;
signal sync_rb : sync_regs;
signal sync_c : sync_regs;
signal read_status : std_logic_vector(2 downto 0);
signal write_status : std_logic_vector(2 downto 0);
signal write_en : std_logic;
signal res_mod :std_logic;
signal en_mod : std_logic;
signal fifo_en : std_logic;
signal dmai : ahb_dma_in_type;
signal dmao : ahb_dma_out_type;
signal equal : std_logic;
signal hmax : std_logic_vector(15 downto 0);
signal hfporch : std_logic_vector(15 downto 0);
signal hsyncpulse : std_logic_vector(15 downto 0);
signal hvideo : std_logic_vector(15 downto 0);
signal vmax : std_logic_vector(15 downto 0);
signal vfporch : std_logic_vector(15 downto 0);
signal vsyncpulse : std_logic_vector(15 downto 0);
signal vvideo : std_logic_vector(15 downto 0);
signal write_pointer_clut : std_logic_vector(7 downto 0);
signal read_pointer_clut : std_logic_vector(7 downto 0);
signal read_pointer_fifo : std_logic_vector(9 downto 0);
signal write_pointer_fifo : std_logic_vector(9 downto 0);
signal datain_clut : std_logic_vector(23 downto 0);
signal dataout_clut : std_logic_vector(23 downto 0);
signal dataout_fifo : std_logic_vector(31 downto 0);
signal datain_fifo : std_logic_vector(31 downto 0);
signal write_en_clut, read_en_clut : std_logic;
signal vcc : std_logic;
signal read_en_fifo, write_en_fifo : std_logic;
begin
vcc <= '1';
ram0 : syncram_2p generic map (tech => memtech, abits => 10, dbits => 32,
sepclk => 1)
port map (vgaclk, read_en_fifo, read_pointer_fifo, dataout_fifo,clk, write_en_fifo,
write_pointer_fifo, datain_fifo);
clutram : syncram_2p generic map (tech => memtech, abits => 8, dbits => 24,
sepclk => 1)
port map (vgaclk, read_en_clut, read_pointer_clut, dataout_clut, clk, write_en_clut,
write_pointer_clut,datain_clut);
ahb_master : ahbmst generic map (hindex, hirq, VENDOR_GAISLER,
GAISLER_SVGACTRL, 0, 3, 1)
port map (rst, clk, dmai, dmao, ahbi, ahbo);
apbo.pirq <= (others => '0');
apbo.pindex <= pindex;
apbo.pconfig <= pconfig;
control_proc : process(r,rst,sync_c,apbi,fifo_en,write_en,read_status,dmao,res_mod, sync_w)
variable v: control_type;
variable rdata : std_logic_vector(31 downto 0);
variable mem_sel : integer;
variable apbwrite : std_logic;
variable we_fifo : std_logic;
begin
v := r; v.write_en_clut := '0'; rdata := (others =>'0');
mem_sel := conv_integer(apbi.paddr(5 downto 2)); we_fifo := '0';
-- Control part. This part handles the apb-accesses and stores the internal registers
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
apbwrite := apbi.psel(pindex) and apbi.pwrite and apbi.penable;
case apbi.paddr(5 downto 2) is
when "0000" =>
if apbwrite = '1' then
v.enable := apbi.pwdata(0);
v.reset := apbi.pwdata(1);
v.hpolarity := apbi.pwdata(8);
v.vpolarity := apbi.pwdata(9);
v.func := apbi.pwdata(5 downto 4);
v.clk_sel := apbi.pwdata(7 downto 6);
end if;
rdata(9 downto 0) := r.vpolarity & r.hpolarity & r.clk_sel &
r.func & fifo_en & '0' & r.reset & r.enable;
when "1010" =>
if apbwrite = '1' then
v.datain_clut := apbi.pwdata(23 downto 0);
v.write_pointer_clut := apbi.pwdata(31 downto 24);
v.write_en_clut := '1';
end if;
when "0001" =>
if apbwrite = '1' then v.int_reg(1) := apbi.pwdata; end if;
rdata := r.int_reg(1);
when "0010" =>
if apbwrite = '1' then v.int_reg(2) := apbi.pwdata; end if;
rdata := r.int_reg(2);
when "0011" =>
if apbwrite = '1' then v.int_reg(3) := apbi.pwdata; end if;
rdata := r.int_reg(3);
when "0100" =>
if apbwrite = '1' then v.int_reg(4) := apbi.pwdata; end if;
rdata := r.int_reg(4);
when "0101" =>
if apbwrite = '1' then v.int_reg(5) := apbi.pwdata; end if;
rdata := r.int_reg(5);
when "0110" => rdata := conv_std_logic_vector(clk0,32);
when "0111" => rdata := conv_std_logic_vector(clk1,32);
when "1000" => rdata := conv_std_logic_vector(clk2,32);
when "1001" => rdata := conv_std_logic_vector(clk3,32);
when others =>
end case;
------------------------------------------
----------- Control state machine --------
case r.state is
when running =>
if r.enable = '0' then
v.sync_c := "011";
v.state := not_running;
end if;
when not_running =>
if r.enable = '1' then
v.sync_c := "001";
v.state := reset;
end if;
when reset =>
if sync_c.s3 = "001" then
v.sync_c := "010";
v.state := running;
end if;
end case;
-----------------------------------------
----------- Control reset part-----------
if r.reset = '1' or rst = '0' then
v.state := not_running;
v.enable := '0';
v.int_reg := (others => (others => '0'));
v.sync_c := "011";
v.reset := '0';
v.clk_sel := "00";
end if;
------------------------------------------------------------------------------
-- Write part. This part reads from the memory framebuffer and places the data
-- in the designated fifo specified from the generic.
-------------------------------------------------------------------------------
v.start := '0';
if write_en = '0' then
if (r.start or not dmao.active) = '1' then v.start := '1'; end if;
if dmao.ready = '1' then ------------ AHB access part -----------
---------- and Fifo write part ---------
v.data := dmao.rdata(31 downto 0);
v.ram_address := v.write_pointer;
v.write_pointer := v.write_pointer +1; we_fifo := '1';
if v.write_pointer = length then
v.write_pointer := 0;
end if;
v.level := v.level +1;
if dmao.haddr = (9 downto 0 => '0') then
v.adress := (v.adress(31 downto 10) + 1) & dmao.haddr;
else
v.adress := v.adress(31 downto 10) & dmao.haddr;
end if;
if (dmao.haddr(burstlen+1 downto 0) = ((burstlen+1 downto 2 => '1') & "00")) then
v.start := '0';
end if;
end if; ----------------------------------------
v.sync_w := v.sync_w and read_status; ------------ Fifo sync part ------------
if v.level >= (part -1) then
if read_status(r.status) = '1' and v.sync_w(r.status) = '0' and v.level = part then
v.level := 0;
if r.status = 0 then
v.sync_w(2) := '1';
else
v.sync_w(r.status -1) := '1';
end if;
v.status := v.status + 1;
if v.status = 3 then
v.status := 0;
end if;
else
v.start := '0';
end if;
end if;
end if; ------------------------------------------
------------ Write reset part ------------
if res_mod = '0' or write_en = '1' then
if dmao.active = '0' then v.adress := r.int_reg(5); end if;
v.start := '0';
v.sync_w := "000";
v.status := 1;
v.ram_address := 0;
v.write_pointer := 0;
v.level := 0;
end if; ------------------------------------------
if (r.start and dmao.active and not dmao.ready) = '1' then
v.start := '1';
end if;
-- Assertions
rin <= v;
sync_c.s1 <= v.sync_c;
sync_w.s1 <= r.sync_w;
res_mod <= sync_c.s3(1);
en_mod <= sync_c.s3(0);
write_status <= sync_w.s3;
hvideo <= r.int_reg(1)(15 downto 0);
vvideo <= r.int_reg(1)(31 downto 16);
hfporch <= r.int_reg(2)(15 downto 0);
vfporch <= r.int_reg(2)(31 downto 16);
hsyncpulse <= r.int_reg(3)(15 downto 0);
vsyncpulse <= r.int_reg(3)(31 downto 16);
hmax <= r.int_reg(4)(15 downto 0);
vmax <= r.int_reg(4)(31 downto 16);
apbo.prdata <= rdata;
dmai.wdata <= (others => '0');
dmai.burst <= '1';
dmai.irq <= '0';
dmai.size <= "10";
dmai.write <= '0';
dmai.busy <= '0';
dmai.start <= r.start and r.enable;
dmai.address <= r.adress;
write_pointer_fifo <= conv_std_logic_vector(v.ram_address,10);
write_pointer_clut <= r.write_pointer_clut;
datain_fifo <= v.data;
datain_clut <= r.datain_clut;
write_en_clut <= r.write_en_clut;
clk_sel <= r.clk_sel;
write_en_fifo <= we_fifo;
end process;
read_proc : process(t,res_mod,en_mod,write_status,dataout_fifo,sync_rb,dataout_clut,
vmax, hmax, hvideo, hfporch, hsyncpulse, vvideo, vfporch, vsyncpulse, sync_ra, r)
variable v : read_type;
variable inc_pointer : std_logic;
begin
v := t;
v.vsync2 := t.vsync; v.hsync2 := t.hsync; v.csync2 := t.csync;
v.blank2 := t.blank;
-- Syncsignals generation functions.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
if en_mod = '0' then
-- vertical counter
if (t.vcounter = vmax ) and (t.hcounter = hmax ) then
v.vcounter := (others => '0');
elsif t.hcounter = hmax then
v.vcounter := t.vcounter +1;
end if;
-- horizontal counter
if t.hcounter < hmax then v.hcounter := t.hcounter +1;
else v.hcounter := (others => '0'); end if;
-- generate hsync
if t.hcounter < (hvideo+hfporch+hsyncpulse) and (t.hcounter > (hvideo+hfporch -1)) then
v.hsync := r.hpolarity;
else v.hsync := not r.hpolarity; end if;
-- generate vsync
if t.vcounter <= (vvideo+vfporch+vsyncpulse) and (t.vcounter > (vvideo+vfporch)) then
v.vsync := r.vpolarity;
else v.vsync := not r.vpolarity; end if;
--generate csync & blank signal
v.csync := not (v.hsync xor v.vsync);
v.blank := not t.fifo_ren;
--generate fifo_ren -signal
if (t.hcounter = (hmax -1) and t.vcounter = vmax) or
(t.hcounter = (hmax -1 ) and t.vcounter < vvideo) then
v.fifo_ren := '0';
elsif t.hcounter = (hvideo -1) and t.vcounter <= vvideo then
v.fifo_ren := '1';
end if;
--generate fifo_en -signal
if t.vcounter = vmax then
v.fifo_en := '0';
elsif t.vcounter = vvideo and t.hcounter = (hvideo -1) then
v.fifo_en := '1';
end if;
end if;
if r.func /= "01" then -- do not delay strobes when not using CLUT
v.vsync2 := v.vsync; v.hsync2 := v.hsync; v.csync2 := v.csync;
v.blank2 := v.blank;
end if;
-- Sync reset part ---------
if res_mod = '0' then
v.hcounter := hmax;
v.vcounter := vmax - 1;
v.hsync := r.hpolarity;
v.vsync := r.vpolarity;
v.blank := '0';
v.fifo_ren := '1';
v.fifo_en := '1';
end if;
-- Read from fifo.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
inc_pointer := '0';
if t.fifo_en = '0' then
------------ Fifo sync part ------------
if (v.read_pointer_out = 0 or v.read_pointer_out = part or
v.read_pointer_out = (part + part)) and t.fifo_ren = '0'
and v.index = "00"
then
case t.sync is
when "111" | "011" =>
if write_status(0) = '1' then
v.sync := "110"; v.lock := '0';
else v.lock := '1'; end if;
when "110" =>
if write_status(1) = '1' then
v.sync := "101"; v.lock := '0';
else v.lock := '1'; end if;
when "101" =>
if write_status(2) = '1' then
v.sync := "011"; v.lock := '0';
else v.lock := '1'; end if;
when others => null;
end case;
end if;
------------------------------------------
------------ Fifo read part -------------
------------ and CLUT access -------------
if t.fifo_ren = '0' and v.lock = '0' then
case r.func is
when "01" =>
if t.index = "00" then
v.read_pointer_clut := dataout_fifo(31 downto 24);
v.index := "01";
elsif t.index = "01" then
v.read_pointer_clut := dataout_fifo(23 downto 16);
v.index := "10";
elsif t.index = "10" then
v.read_pointer_clut := dataout_fifo(15 downto 8);
v.index := "11";
else
v.read_pointer_clut := dataout_fifo(7 downto 0);
v.index := "00"; inc_pointer := '1';
end if;
v.data_out := dataout_clut;
when "10" =>
if t.index = "00" then
v.data_out := dataout_fifo(31 downto 27) & "000" &
dataout_fifo(26 downto 21) & "00" & dataout_fifo(20 downto 16) & "000";
v.index := "01";
else
v.data_out := dataout_fifo(15 downto 11) & "000" &
dataout_fifo(10 downto 5) & "00" & dataout_fifo(4 downto 0) & "000";
v.index := "00"; inc_pointer := '1';
end if;
when "11" =>
v.data_out := dataout_fifo(23 downto 0);
v.index := "00"; inc_pointer := '1';
when others =>
v.data_out := (23 downto 0 => '1');
v.index := "00"; inc_pointer := '1';
end case;
else
v.data_out := (others => '0');
end if;
if inc_pointer = '1' then
v.read_pointer_out := t.read_pointer;
v.read_pointer := t.read_pointer + 1;
if v.read_pointer = length then
v.read_pointer := 0;
end if;
if v.read_pointer_out = length then
v.read_pointer_out := 0;
end if;
end if;
else
v.data_out := (others => '0');
end if; ------------------------------------------
------------ Fifo read reset part -------
if res_mod = '0' or t.fifo_en = '1' then
v.sync := "111";
v.read_pointer_out := 0;
v.read_pointer := 1;
v.data_out := (others => '0');
v.lock := '1';
v.index := "00";
v.read_pointer_clut := (others => '0');
end if; ------------------------------------------
tin <= v;
sync_ra.s1 <= t.sync;
sync_rb.s1 <= t.fifo_en & "00";
read_status <= sync_ra.s3;
write_en <= sync_rb.s3(2);
fifo_en <= t.fifo_en;
read_pointer_clut <= v.read_pointer_clut;
read_pointer_fifo <= conv_std_logic_vector(v.read_pointer_out,10);
read_en_fifo <= not v.fifo_ren;
read_en_clut <= not v.fifo_ren and not r.func(1) and r.func(0);
vgao.video_out_r <= t.data_out(23 downto 16);
vgao.video_out_g <= t.data_out(15 downto 8);
vgao.video_out_b <= t.data_out(7 downto 0);
vgao.hsync <= t.hsync2;
vgao.vsync <= t.vsync2;
vgao.comp_sync <= t.csync2;
vgao.blank <= t.blank2;
end process;
proc_clk : process(clk)
begin
if rising_edge(clk) then
r <= rin; -- Control
sync_ra.s2 <= sync_ra.s1; -- Write
sync_ra.s3 <= sync_ra.s2; -- Write
sync_rb.s2 <= sync_rb.s1; -- Write
sync_rb.s3 <= sync_rb.s2; -- Write
end if;
end process;
proc_vgaclk : process(vgaclk)
begin
if rising_edge(vgaclk) then
t <= tin; -- Read
sync_c.s2 <= sync_c.s1; -- Control
sync_c.s3 <= sync_c.s2; -- Control
sync_w.s2 <= sync_w.s1; -- Read
sync_w.s3 <= sync_w.s2; -- Read
end if;
end process;
end ;
|
mit
|
impedimentToProgress/UCI-BlueChip
|
AttackFiles/Attacks/privEsc/lib/gaisler/ddr/ddrsp.in.vhd
|
6
|
373
|
-- DDR controller
constant CFG_DDRSP : integer := CONFIG_DDRSP;
constant CFG_DDRSP_INIT : integer := CONFIG_DDRSP_INIT;
constant CFG_DDRSP_FREQ : integer := CONFIG_DDRSP_FREQ;
constant CFG_DDRSP_COL : integer := CONFIG_DDRSP_COL;
constant CFG_DDRSP_SIZE : integer := CONFIG_DDRSP_MBYTE;
constant CFG_DDRSP_RSKEW : integer := CONFIG_DDRSP_RSKEW;
|
mit
|
impedimentToProgress/UCI-BlueChip
|
AttackFiles/Attacks/memAttack/lib/techmap/maps/grspwc_net.vhd
|
2
|
17903
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: grspwc
-- File: grspwc.vhd
-- Author: Marko Isomaki - Gaisler Research
-- Description: Provides a link interface to a SpaceWire network
-- with an AHB host interface and RMAP support.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity grspwc_net is
generic(
tech : integer := 0;
sysfreq : integer := 40000;
usegen : integer range 0 to 1 := 1;
nsync : integer range 1 to 2 := 1;
rmap : integer range 0 to 1 := 0;
rmapcrc : integer range 0 to 1 := 0;
fifosize1 : integer range 4 to 32 := 32;
fifosize2 : integer range 16 to 64 := 64;
rxunaligned : integer range 0 to 1 := 0;
rmapbufs : integer range 2 to 8 := 4;
scantest : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
txclk : in std_ulogic;
--ahb mst in
hgrant : in std_ulogic;
hready : in std_ulogic;
hresp : in std_logic_vector(1 downto 0);
hrdata : in std_logic_vector(31 downto 0);
--ahb mst out
hbusreq : out std_ulogic;
hlock : out std_ulogic;
htrans : out std_logic_vector(1 downto 0);
haddr : out std_logic_vector(31 downto 0);
hwrite : out std_ulogic;
hsize : out std_logic_vector(2 downto 0);
hburst : out std_logic_vector(2 downto 0);
hprot : out std_logic_vector(3 downto 0);
hwdata : out std_logic_vector(31 downto 0);
--apb slv in
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
--apb slv out
prdata : out std_logic_vector(31 downto 0);
--spw in
di : in std_logic_vector(1 downto 0);
si : in std_logic_vector(1 downto 0);
--spw out
do : out std_logic_vector(1 downto 0);
so : out std_logic_vector(1 downto 0);
--time iface
tickin : in std_ulogic;
tickout : out std_ulogic;
--irq
irq : out std_logic;
--misc
clkdiv10 : in std_logic_vector(7 downto 0);
dcrstval : in std_logic_vector(9 downto 0);
timerrstval : in std_logic_vector(11 downto 0);
--rmapen
rmapen : in std_ulogic;
--clk bufs
rxclki : in std_logic_vector(1 downto 0);
nrxclki : in std_logic_vector(1 downto 0);
rxclko : out std_logic_vector(1 downto 0);
--rx ahb fifo
rxrenable : out std_ulogic;
rxraddress : out std_logic_vector(4 downto 0);
rxwrite : out std_ulogic;
rxwdata : out std_logic_vector(31 downto 0);
rxwaddress : out std_logic_vector(4 downto 0);
rxrdata : in std_logic_vector(31 downto 0);
--tx ahb fifo
txrenable : out std_ulogic;
txraddress : out std_logic_vector(4 downto 0);
txwrite : out std_ulogic;
txwdata : out std_logic_vector(31 downto 0);
txwaddress : out std_logic_vector(4 downto 0);
txrdata : in std_logic_vector(31 downto 0);
--nchar fifo
ncrenable : out std_ulogic;
ncraddress : out std_logic_vector(5 downto 0);
ncwrite : out std_ulogic;
ncwdata : out std_logic_vector(8 downto 0);
ncwaddress : out std_logic_vector(5 downto 0);
ncrdata : in std_logic_vector(8 downto 0);
--rmap buf
rmrenable : out std_ulogic;
rmraddress : out std_logic_vector(7 downto 0);
rmwrite : out std_ulogic;
rmwdata : out std_logic_vector(7 downto 0);
rmwaddress : out std_logic_vector(7 downto 0);
rmrdata : in std_logic_vector(7 downto 0);
linkdis : out std_ulogic;
testclk : in std_ulogic := '0';
testrst : in std_ulogic := '0';
testen : in std_ulogic := '0'
);
end entity;
architecture rtl of grspwc_net is
component grspwc_unisim
generic(
sysfreq : integer := 40000;
usegen : integer range 0 to 1 := 1;
nsync : integer range 1 to 2 := 1;
rmap : integer range 0 to 1 := 0;
rmapcrc : integer range 0 to 1 := 0;
fifosize1 : integer range 4 to 32 := 32;
fifosize2 : integer range 16 to 64 := 64;
rxunaligned : integer range 0 to 1 := 0;
rmapbufs : integer range 2 to 8 := 4;
scantest : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
txclk : in std_ulogic;
--ahb mst in
hgrant : in std_ulogic;
hready : in std_ulogic;
hresp : in std_logic_vector(1 downto 0);
hrdata : in std_logic_vector(31 downto 0);
--ahb mst out
hbusreq : out std_ulogic;
hlock : out std_ulogic;
htrans : out std_logic_vector(1 downto 0);
haddr : out std_logic_vector(31 downto 0);
hwrite : out std_ulogic;
hsize : out std_logic_vector(2 downto 0);
hburst : out std_logic_vector(2 downto 0);
hprot : out std_logic_vector(3 downto 0);
hwdata : out std_logic_vector(31 downto 0);
--apb slv in
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
--apb slv out
prdata : out std_logic_vector(31 downto 0);
--spw in
di : in std_logic_vector(1 downto 0);
si : in std_logic_vector(1 downto 0);
--spw out
do : out std_logic_vector(1 downto 0);
so : out std_logic_vector(1 downto 0);
--time iface
tickin : in std_ulogic;
tickout : out std_ulogic;
--irq
irq : out std_logic;
--misc
clkdiv10 : in std_logic_vector(7 downto 0);
dcrstval : in std_logic_vector(9 downto 0);
timerrstval : in std_logic_vector(11 downto 0);
--rmapen
rmapen : in std_ulogic;
--clk bufs
rxclki : in std_logic_vector(1 downto 0);
nrxclki : in std_logic_vector(1 downto 0);
rxclko : out std_logic_vector(1 downto 0);
--rx ahb fifo
rxrenable : out std_ulogic;
rxraddress : out std_logic_vector(4 downto 0);
rxwrite : out std_ulogic;
rxwdata : out std_logic_vector(31 downto 0);
rxwaddress : out std_logic_vector(4 downto 0);
rxrdata : in std_logic_vector(31 downto 0);
--tx ahb fifo
txrenable : out std_ulogic;
txraddress : out std_logic_vector(4 downto 0);
txwrite : out std_ulogic;
txwdata : out std_logic_vector(31 downto 0);
txwaddress : out std_logic_vector(4 downto 0);
txrdata : in std_logic_vector(31 downto 0);
--nchar fifo
ncrenable : out std_ulogic;
ncraddress : out std_logic_vector(5 downto 0);
ncwrite : out std_ulogic;
ncwdata : out std_logic_vector(8 downto 0);
ncwaddress : out std_logic_vector(5 downto 0);
ncrdata : in std_logic_vector(8 downto 0);
--rmap buf
rmrenable : out std_ulogic;
rmraddress : out std_logic_vector(7 downto 0);
rmwrite : out std_ulogic;
rmwdata : out std_logic_vector(7 downto 0);
rmwaddress : out std_logic_vector(7 downto 0);
rmrdata : in std_logic_vector(7 downto 0);
linkdis : out std_ulogic;
testclk : in std_ulogic := '0';
testrst : in std_ulogic := '0';
testen : in std_ulogic := '0'
);
end component;
component grspwc_axcelerator
generic(
sysfreq : integer := 40000;
usegen : integer range 0 to 1 := 1;
nsync : integer range 1 to 2 := 1;
rmap : integer range 0 to 1 := 0;
rmapcrc : integer range 0 to 1 := 0;
fifosize1 : integer range 4 to 32 := 32;
fifosize2 : integer range 16 to 64 := 64;
rxunaligned : integer range 0 to 1 := 0;
rmapbufs : integer range 2 to 8 := 4;
scantest : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
txclk : in std_ulogic;
--ahb mst in
hgrant : in std_ulogic;
hready : in std_ulogic;
hresp : in std_logic_vector(1 downto 0);
hrdata : in std_logic_vector(31 downto 0);
--ahb mst out
hbusreq : out std_ulogic;
hlock : out std_ulogic;
htrans : out std_logic_vector(1 downto 0);
haddr : out std_logic_vector(31 downto 0);
hwrite : out std_ulogic;
hsize : out std_logic_vector(2 downto 0);
hburst : out std_logic_vector(2 downto 0);
hprot : out std_logic_vector(3 downto 0);
hwdata : out std_logic_vector(31 downto 0);
--apb slv in
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
--apb slv out
prdata : out std_logic_vector(31 downto 0);
--spw in
di : in std_logic_vector(1 downto 0);
si : in std_logic_vector(1 downto 0);
--spw out
do : out std_logic_vector(1 downto 0);
so : out std_logic_vector(1 downto 0);
--time iface
tickin : in std_ulogic;
tickout : out std_ulogic;
--irq
irq : out std_logic;
--misc
clkdiv10 : in std_logic_vector(7 downto 0);
dcrstval : in std_logic_vector(9 downto 0);
timerrstval : in std_logic_vector(11 downto 0);
--rmapen
rmapen : in std_ulogic;
--clk bufs
rxclki : in std_logic_vector(1 downto 0);
nrxclki : in std_logic_vector(1 downto 0);
rxclko : out std_logic_vector(1 downto 0);
--rx ahb fifo
rxrenable : out std_ulogic;
rxraddress : out std_logic_vector(4 downto 0);
rxwrite : out std_ulogic;
rxwdata : out std_logic_vector(31 downto 0);
rxwaddress : out std_logic_vector(4 downto 0);
rxrdata : in std_logic_vector(31 downto 0);
--tx ahb fifo
txrenable : out std_ulogic;
txraddress : out std_logic_vector(4 downto 0);
txwrite : out std_ulogic;
txwdata : out std_logic_vector(31 downto 0);
txwaddress : out std_logic_vector(4 downto 0);
txrdata : in std_logic_vector(31 downto 0);
--nchar fifo
ncrenable : out std_ulogic;
ncraddress : out std_logic_vector(5 downto 0);
ncwrite : out std_ulogic;
ncwdata : out std_logic_vector(8 downto 0);
ncwaddress : out std_logic_vector(5 downto 0);
ncrdata : in std_logic_vector(8 downto 0);
--rmap buf
rmrenable : out std_ulogic;
rmraddress : out std_logic_vector(7 downto 0);
rmwrite : out std_ulogic;
rmwdata : out std_logic_vector(7 downto 0);
rmwaddress : out std_logic_vector(7 downto 0);
rmrdata : in std_logic_vector(7 downto 0);
linkdis : out std_ulogic;
testclk : in std_ulogic := '0';
testrst : in std_ulogic := '0';
testen : in std_ulogic := '0'
);
end component;
begin
ax : if tech = axcel generate
grspwc0 : grspwc_axcelerator
generic map (sysfreq, usegen, nsync, rmap, rmapcrc, fifosize1, fifosize2,
rxunaligned, rmapbufs, scantest)
port map(
rst => rst,
clk => clk,
txclk => txclk,
--ahb mst in
hgrant => hgrant,
hready => hready,
hresp => hresp,
hrdata => hrdata,
--ahb mst out
hbusreq => hbusreq,
hlock => hlock,
htrans => htrans,
haddr => haddr,
hwrite => hwrite,
hsize => hsize,
hburst => hburst,
hprot => hprot,
hwdata => hwdata,
--apb slv in
psel => psel,
penable => penable,
paddr => paddr,
pwrite => pwrite,
pwdata => pwdata,
--apb slv out
prdata => prdata,
--spw in
di => di,
si => si,
--spw out
do => do,
so => so,
--time iface
tickin => tickin,
tickout => tickout,
--clk bufs
rxclki => rxclki,
nrxclki => nrxclki,
rxclko => rxclko,
--irq
irq => irq,
--misc
clkdiv10 => clkdiv10,
dcrstval => dcrstval,
timerrstval => timerrstval,
--rmapen
rmapen => rmapen,
--rx ahb fifo
rxrenable => rxrenable,
rxraddress => rxraddress,
rxwrite => rxwrite,
rxwdata => rxwdata,
rxwaddress => rxwaddress,
rxrdata => rxrdata,
--tx ahb fifo
txrenable => txrenable,
txraddress => txraddress,
txwrite => txwrite,
txwdata => txwdata,
txwaddress => txwaddress,
txrdata => txrdata,
--nchar fifo
ncrenable => ncrenable,
ncraddress => ncraddress,
ncwrite => ncwrite,
ncwdata => ncwdata,
ncwaddress => ncwaddress,
ncrdata => ncrdata,
--rmap buf
rmrenable => rmrenable,
rmraddress => rmraddress,
rmwrite => rmwrite,
rmwdata => rmwdata,
rmwaddress => rmwaddress,
rmrdata => rmrdata,
linkdis => linkdis,
testclk => testclk,
testrst => testrst,
testen => testen
);
end generate;
xil : if (tech = virtex2) or (tech = virtex4) or (tech = virtex5) or
(tech = spartan3) or (tech = spartan3e) generate
grspwc0 : grspwc_unisim
generic map (sysfreq, usegen, nsync, rmap, rmapcrc, fifosize1, fifosize2,
rxunaligned, rmapbufs, scantest)
port map(
rst => rst,
clk => clk,
txclk => txclk,
--ahb mst in
hgrant => hgrant,
hready => hready,
hresp => hresp,
hrdata => hrdata,
--ahb mst out
hbusreq => hbusreq,
hlock => hlock,
htrans => htrans,
haddr => haddr,
hwrite => hwrite,
hsize => hsize,
hburst => hburst,
hprot => hprot,
hwdata => hwdata,
--apb slv in
psel => psel,
penable => penable,
paddr => paddr,
pwrite => pwrite,
pwdata => pwdata,
--apb slv out
prdata => prdata,
--spw in
di => di,
si => si,
--spw out
do => do,
so => so,
--time iface
tickin => tickin,
tickout => tickout,
--clk bufs
rxclki => rxclki,
nrxclki => nrxclki,
rxclko => rxclko,
--irq
irq => irq,
--misc
clkdiv10 => clkdiv10,
dcrstval => dcrstval,
timerrstval => timerrstval,
--rmapen
rmapen => rmapen,
--rx ahb fifo
rxrenable => rxrenable,
rxraddress => rxraddress,
rxwrite => rxwrite,
rxwdata => rxwdata,
rxwaddress => rxwaddress,
rxrdata => rxrdata,
--tx ahb fifo
txrenable => txrenable,
txraddress => txraddress,
txwrite => txwrite,
txwdata => txwdata,
txwaddress => txwaddress,
txrdata => txrdata,
--nchar fifo
ncrenable => ncrenable,
ncraddress => ncraddress,
ncwrite => ncwrite,
ncwdata => ncwdata,
ncwaddress => ncwaddress,
ncrdata => ncrdata,
--rmap buf
rmrenable => rmrenable,
rmraddress => rmraddress,
rmwrite => rmwrite,
rmwdata => rmwdata,
rmwaddress => rmwaddress,
rmrdata => rmrdata,
linkdis => linkdis,
testclk => testclk,
testrst => testrst,
testen => testen
);
end generate;
-- pragma translate_off
nonet : if not ((tech = virtex2) or (tech = virtex4) or (tech = virtex5) or
(tech = spartan3) or (tech = spartan3e) or (tech = axcel))
generate
err : process
begin
assert false report "ERROR : No GRSPWC netlist available for this process!"
severity failure;
wait;
end process;
end generate;
-- pragma translate_on
end architecture;
|
mit
|
impedimentToProgress/UCI-BlueChip
|
AttackFiles/Attacks/privEsc/lib/synplify/sim/synattr.vhd
|
5
|
22767
|
-- $Header: /syn/cvs/rcs/compilers/vhdl/vhd/synattr.vhd,v 1.90.2.14.2.1 2003/07/08 18:06:01 akapoor Exp $
-----------------------------------------------------------------------------
-- --
-- Copyright (c) 1997-2003 by Synplicity, Inc. All rights reserved. --
-- --
-- This source file may be used and distributed without restriction --
-- provided that this copyright statement is not removed from the file --
-- and that any derivative work contains this copyright notice. --
-- --
-- --
-- Library name: synplify --
-- Package name: attributes --
-- --
-- Description: This package contains declarations for synplify --
-- attributes --
-- --
-- --
-- --
-----------------------------------------------------------------------------
--
-- Definitions used for Scope Integration ----------------
--{tcl set actel "act* 40* 42* 32* 54* ex* ax*"}
--{tcl set altera "max* flex* acex*"}
--{tcl set altera_retiming "flex* acex* apex* mercury* excalibur*"}
--{tcl set apex "apex20k apexii excalibur*"}
--{tcl set apexe "apex20kc apex20ke mercury* stratix* cyclone"}
--{tcl set apex20k "apex20k*"}
--{tcl set lattice "pLSI*"}
--{tcl set mach "mach* isp* gal*"}
--{tcl set quicklogic "pasic* quick* eclipse*"}
--{tcl set lucent "orca*"}
--{tcl set xilinx "xc* vir* spart*"}
--{tcl set virtex "vir* spartan*"}
--{tcl set virtex2 "virtex2*"}
--{tcl set stratix "stratix*"}
--{tcl set triscend "triscend*" }
--{tcl set asic "asic*" }
--{tcl set atmel "fpslic" }
--{tcl set cp_only "apex20k* excalibur* mercury apexii stratix* cyclone spartan* virtex*" }
-------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
package attributes is
-- Compiler attributes
-- {family *}
attribute phys_pin_loc : string; -- pin loacatin {objtype port} {desc Placement constarint for pin or pad} {physattr 1}
attribute phys_pin_hslots : string; -- pin loacatin {objtype module} {desc Set of slots or placable IO locations} {physattr 1}
attribute phys_pin_vslots : string; -- pin loacatin {objtype module} {desc Set of slots or placable IO locations} {physattr 1}
attribute phys_halo : string; -- pin loacatin {objtype module cell } {desc Halo to be used for the macros} {physattr 1}
-- syn_enum_encoding specifies the encoding for an enumeration type
attribute syn_enum_encoding : string; -- "onehot", "sequential", "gray" {noscope}
-- syn_encoding specifies the encoding for a state register
attribute syn_encoding : string; -- "onehot", "sequential", "gray", "safe" {objtype fsm} {desc FSM encoding (onehot, sequential, gray, safe)} {default gray} {enum onehot sequential gray safe safe,onehot safe,sequential safe,gray default}
-- syn_allow_retiming specifies if the register can be moved for retiming purpose
-- {family $altera_retiming $virtex $virtex2 $stratix }
attribute syn_allow_retiming : boolean; -- {objtype register} {desc Controls retiming of registers} {default 0}
attribute syn_state_machine : boolean; -- marks reg for SM extraction {noscope}
--
-- syn_preserve prevents optimization across registers it is
-- applied to. syn_preserve on a module/arch is applied to all
-- registers in the module/arch. syn_preserve on a register
-- will preserve redundant copies.
-- Can also be used to preserve redundant copies of instantiated
-- combinational cells.
attribute syn_preserve : boolean; -- {noscope}
-- syn_keep is used on signals keep the signal through optimization
-- so that timing constraints can be placed on the signal later.
-- The timing constraints can be multi-cycle path and clock.
attribute syn_keep : boolean; -- {noscope}
attribute syn_sharing : string; -- "off" or "on" {noscope}
-- syn_evaleffort is used on modules to define the effort to be used in
-- evaluating conditions for control structures. This is useful for
-- those modules that contain while loop or if-then-else conditions
-- that may evaluate to a constant if more effort is applied.
-- The higher this number, the higher the evaluation effort,
-- and consequently the memory requirement and CPU time. The default
-- value is 4.
-- This attribute is not recommended!
attribute syn_evaleffort : integer; -- an integer between 0 and 100 {noscope}
-- syn_cpueffort is used on modules to define the cpu effort to be used in
-- various optimizations (such as BDDs). It may take a value from 1 to 10,
-- with the default being 5. A value of 1 to 4 would result in less CPU
-- time and most likely less optimization, while a value of 6 to 10 would
-- result in longer CPU time and possibly more optimization.
--
-- This attribute is not recommended!
attribute syn_cpueffort : integer; -- an integer between 1 and 10 {noscope}
-- syn_looplimit my be attached to a loop label. It represents the maximum
-- number of loop iterations that are allowed. Use this attribute when
-- Synplify errors out after reaching the maximum loop limit.
attribute syn_looplimit : integer; -- the maximum loop count allowed {noscope}
-- the syn_pmux_slice attribute is used to enable the pmux optimization
-- code on/off. If on at the last architecture, it is carried on the
-- hierarcy chain until it finds an architecture in which the attribute
-- is expicitly set to off.
attribute syn_pmux_slice : boolean; -- a boolean value {noscope}
attribute syn_isclock : boolean; -- {noscope}
-- turn on or off priority mux code
attribute syn_primux : boolean; -- {noscope}
-- General mapping attributes
-- inst/module/arch
--{family *}
attribute syn_resources : string; -- spec resources used by module {noscope} {objtype cell} {desc Specifies resources used by module/architecture}
attribute syn_area : string; -- spec resources used by module {noscope}
attribute syn_noprune : boolean; -- keep object even if outputs unused {noscope} {objtype cell} {desc Retain instance when outputs are unused}
attribute syn_probe : string; -- {objtype signal} {app ~synplify_asic} {desc Send a signal to output port for testing} {enum 0 1}
attribute syn_direct_enable : boolean; -- {objtype signal} {app ~synplify_asic} {desc Prefered clock enable} {default 1} {enum 1}
-- registers
attribute syn_useenables : boolean; -- set to false to disable enable use {objtype register} {app ~synplify_asic} {desc Generate with clock enable pin}
-- registers
attribute syn_reference_clock : string; -- set to the name of the reference clock {objtype register} {desc Override the default clock with the given clock }
-- I/O registers
-- {family $lucent $apex $apexe $xilinx $quicklogic}
attribute syn_useioff : boolean; -- set to false to disable use of I/O FF {objtype global port register} {desc Embed flip-flps in the IO ring}
-- {family $xilinx $apex $apexe}
attribute syn_forward_io_constraints : boolean; -- set to true to forward annotate IO constraints {objtype global} {desc Forward annotate IO constraints}
-- used to specify implementations for dff in actel for now
-- {family $actel}
attribute syn_implement : string; -- "dff", "dffr", "dffs", "dffrs" {noscope}
attribute syn_radhardlevel : string; -- "none", "cc", "tmr", "tmr_cc" {objtype register } {desc Radiation-hardened implementation style} {enum none cc tmr tmr_cc}
-- {family asic}
attribute syn_ideal_net : string; -- {objtype signal} {desc Do not buffer this net during optimization} {enum 1}
-- {family asic}
attribute syn_ideal_network : string; -- {objtype signal} {desc Do not buffer this network during optimization} {enum 1}
-- {family asic}
attribute syn_no_reopt : string; -- {objtype module} {desc Do not resize during reoptimization} {enum 1}
-- {family asic}
attribute syn_wire_load : string; -- {objtype module} {desc Set the wire load model to use for this module} {enum -read-wireloads-}
-- {family *}
-- black box attributes
attribute syn_black_box : boolean; -- disables automatic black box warning {noscope}
-- OLD black box attributes
attribute black_box : boolean; -- disables automatic black box warning {noscope}
attribute black_box_pad_pin : string; -- names of I/O pad connections {noscope}
attribute black_box_tri_pins : string; -- names of tristate ports {noscope}
-- Black box timing attributes
-- tpd : timing propagation delay
-- tsu : timing setup delay
-- tco : timing clock to output delay
attribute syn_tpd1 : string; -- {noscope}
attribute syn_tpd2 : string; -- {noscope}
attribute syn_tpd3 : string; -- {noscope}
attribute syn_tpd4 : string; -- {noscope}
attribute syn_tpd5 : string; -- {noscope}
attribute syn_tpd6 : string; -- {noscope}
attribute syn_tpd7 : string; -- {noscope}
attribute syn_tpd8 : string; -- {noscope}
attribute syn_tpd9 : string; -- {noscope}
attribute syn_tpd10 : string; -- {noscope}
attribute syn_tsu1 : string; -- {noscope}
attribute syn_tsu2 : string; -- {noscope}
attribute syn_tsu3 : string; -- {noscope}
attribute syn_tsu4 : string; -- {noscope}
attribute syn_tsu5 : string; -- {noscope}
attribute syn_tsu6 : string; -- {noscope}
attribute syn_tsu7 : string; -- {noscope}
attribute syn_tsu8 : string; -- {noscope}
attribute syn_tsu9 : string; -- {noscope}
attribute syn_tsu10 : string; -- {noscope}
attribute syn_tco1 : string; -- {noscope}
attribute syn_tco2 : string; -- {noscope}
attribute syn_tco3 : string; -- {noscope}
attribute syn_tco4 : string; -- {noscope}
attribute syn_tco5 : string; -- {noscope}
attribute syn_tco6 : string; -- {noscope}
attribute syn_tco7 : string; -- {noscope}
attribute syn_tco8 : string; -- {noscope}
attribute syn_tco9 : string; -- {noscope}
attribute syn_tco10 : string; -- {noscope}
-- Mapping attributes
-- {family $actel $xilinx $lucent $quicklogic $altera $apex $apexe}
attribute syn_maxfan : integer; -- {objtype input_port register_output cell} {desc Overrides the default fanout}
-- {family $actel $xilinx $lucent $quicklogic $lattice $mach $virtex $virtex2 $triscend $asic $atmel $cp_only}
attribute syn_noclockbuf : boolean; -- {objtype global cell input_port module} {app ~synplify_asic} {desc Use normal input buffer}
-- {family $virtex stratix* }
attribute syn_srlstyle : string; -- {objtype cell global module} {desc Determines how seq. shift comp. are implemented} {default select_srl} {enum virtex (select_srl registers noextractff_srl) stratix(select_srl registers noextractff_srl altshift_tap)}
-- set syn_ramstyle to a value of "registers" to force the ram
-- to be implemented with registers.
-- {family $altera $apex $apexe $xilinx $lucent $quicklogic stratix* }
attribute syn_ramstyle : string; -- {objtype cell global module} {desc Map inferred RAM to registers} {default registers} {desc Special implementation of inferred RAM} {enum Virtex virtex-E spartan2 spartan2e virtex2 virtex2-pro(registers block_ram no_rw_check select_ram) xilinx_default (registers select_ram) stratix (registers block_ram no_rw_check) altera_default (registers block_ram) default (registers) all_enums (registers block_ram no_rw_check select_ram)}
-- {family $virtex2 $altera $apex $apexe $apex20k $lattice $lucent $mach excalibur*}
attribute syn_multstyle : string; -- {objtype cell global module} {default block_mult} {desc Special implementation of multipliers} {enum Virtex virtex-E spartan2 spartan2e virtex2 virtex2-pro(logic block_mult) stratix(logic lpm_mult block_mult) altera_default (logic lpm_mult) all_enums (logic block_mult lpm_mult)}
-- {family $virtex $virtex2}
attribute syn_tops_region_size : integer; -- {objtype global} {desc max. size of valid TOPS region in LUTs} {app amplify}
-- set syn_romstyle to a value of "logic" to force the rom
-- to be implemented with logic, select_rom/block_rom
-- {family $altera $apex $apexe $xilinx}
attribute syn_romstyle : string; -- {objtype cell global module} {desc Controls mapping of inferred ROM} {default logic} {desc Special implementation of inferred ROM} {enum xilinx_default (logic select_rom) altera_default(logic block_rom lpm_rom) default(logic) all_enums (logic select_rom block_rom) }
-- set syn_pipeline to a value 1 to pipeline the module front of it
-- {family $altera $apex $apexe $xilinx}
attribute syn_pipeline : boolean; -- {objtype register} {desc Controls pipelining of registers} {default 1} {desc Special implementation of pipelined module}
-- controls EDIF format. Set true on top level to disable array ports
-- {family *}
attribute syn_noarrayports : boolean; -- {objtype global} {app ~synplify_asic} {desc Disable array ports}
-- controls EDIF port name length. Currently used in Altera
-- {family $altera}
attribute syn_edif_name_length : string; -- {enum Restricted Unrestricted} {default Restricted} {objtype global} {desc Use Restricted for MAXII; Unrestricted for quartus}
-- {family *}
-- controls reconstruction of hierarchy. Set false on top level
-- to disable hierarchy reconstruction.
attribute syn_netlist_hierarchy : boolean; -- {objtype global} {app ~synplify_asic} {desc Enable hierarchy reconstruction}
--
-- syn_hier on an instance/module/architecture can be used
-- to control treatment of the level of hierarchy.
-- "macro" - preserve instantiated netlist
-- "hard" - preserves the interface of the design unit with no exceptions.
-- "remove"- removes level of hierarchy
-- "soft" - managed by Synplify (default)
-- "firm" - preserve during opt, but allow mapping across boundary
--
-- {family *}
attribute syn_hier: string; -- {objtype module} {desc Control hierarchy flattening} {enum proASIC (soft remove flatten firm) xilinx_default(hard soft remove flatten firm) actel_default altera_default all_enums(hard soft macro remove flatten firm) lucent_default (soft macro remove flatten firm) quicklogic_default(soft macro remove flatten firm) default(soft remove flatten firm)}
-- syn_flatten on a module/architecture will flatten out the
-- module all the way down to primitives.
attribute syn_flatten : boolean; -- {noscope}
-- {family $cp_only }
attribute syn_allowed_resources : string; -- {objtype module} {desc Control resource usage in a compile point}
-- Architecture specific attributes
-- Actel
-- {family $actel}
--
-- syn_preserve_sr_priority is used if you want to preserve
-- reset over set priority for DFFRS. Actel FF models produce
-- an X for set and reset active. This attribute costs gates and delay.
attribute syn_preserve_sr_priority : boolean; -- {noscope}
attribute alspin : string ; --{objtype port} {desc Pin locations for Actel I/Os}
attribute alspreserve : boolean ; --{objtype signal} {desc Not collapse a net in Actel}
attribute alsfc : string ; --{noscope}
attribute alsdc : string ; --{noscope}
attribute alsloc : string ; --{noscope}
attribute alscrt : string ; --{noscope}
-- Altera
-- {family $altera $apex $apexe}
attribute altera_implement_style : string; -- placement {noscope}
attribute altera_clique : string; -- placement {noscope}
attribute altera_chip_pin_lc : string; -- placement {objtype port} {desc I/O pin location}
-- inst/module/arch: put comb logic into rom
attribute altera_implement_in_eab : boolean; -- {objtype cell} {desc Implment in Altera EABs, apply to module/component instance name only} {default 1}
attribute altera_lcell: string; -- arch attribute with values of "lut" and "car" {noscope}
-- for lcell config
attribute altera_auto_use_eab : boolean; -- {objtype global} {desc Use EABs automatically} {default 1}
attribute altera_auto_use_esb : boolean; -- {objtype global} {desc Use ESBs automatically} {default 1}
-- Apex
-- {family $apex $apexe}
attribute altera_implement_in_esb : boolean; -- {objtype cell} {desc Implment in Altera ESBs, apply to module/component instance name only} {default 1}
-- Apex
-- {family $apex $apexe}
attribute altera_logiclock_location : string; -- {objtype module} {desc Give the location of LogicLock region } {default floating}
-- Apex
-- {family $apex $apexe}
attribute altera_logiclock_size : string; -- {objtype module} {desc Give the size of LogicLock region} {default auto}
-- {family apex20kc apex20ke excalibur* mercury* cyclone stratix* acex* flex10k* }
attribute altera_io_opendrain : boolean; -- set to true to get opendrain port in APEX {objtype port} {desc Use opendrain capability on port or bit-port.}
-- {family $altera_retiming}
attribute altera_io_powerup : string; -- set to high to get IO FF to powerup high in APEX {objtype port} {desc Powerup high or low on port or bit-port in APEX20KE.}
-- Lattice
-- {family $lattice $quicklogic}
attribute lock: string; -- pin placement {objtype port} {desc Pin locations for Lattice I/Os}
-- Lucent
-- {family $lucent}
attribute din : string; -- orca2 FF placement attribute, use value "" {objtype input_port} {desc Input register goes next to I/O pad}
attribute dout : string; -- orca2 FF placement attribute, use value "" {objtype output_port} {desc Output register goes next to I/O pad}
attribute orca_padtype : string; -- value selects synth pad type {objtype port} {desc Pad type for I/O}
attribute orca_props : string; -- attributes to pass for instance {objtype cell port} {desc Forward annotate attributes to ORCA back-end}
-- Both Lucent and Mach
-- {family $lucent $mach}
attribute loc : string; -- placment attribute {objtype port} {desc Pin location}
-- Quicklogic
-- {family $quicklogic}
-- I/O attributes
attribute ql_padtype : string; -- {objtype port} {desc Override default pad types (use BIDIR, INPUT, CLOCK)} {enum BIDIR INPUT CLOCK}
attribute ql_placement : string; -- {objtype port cell} {desc Placement location}
-- Xilinx
-- {family $xilinx}
-- Instance Placement attributes
attribute xc_loc : string; -- placement (pads) {objtype port} {desc Port placement}
attribute xc_rloc : string; -- see RPMs in xilinx doc {objtype cell} {desc Relative placement specification, use with xc_uset}
attribute xc_uset : string; -- see RPMs in xilinx doc {objtype cell} {desc Assign group name for placement, use with xc_rloc}
-- I/O attributes
attribute xc_fast : boolean; -- {objtype output_port} {desc Fast transition time}
attribute xc_ioff : boolean; -- {noscope}
attribute xc_nodelay : boolean; -- {objtype input_port} {desc Remove input delay}
attribute xc_slow : boolean; -- {objtype output_port} {desc Slow transition time}
attribute xc_ttl : boolean; -- {noscope}
attribute xc_cmos : boolean; -- {noscope}
attribute xc_pullup : boolean; -- add a pullup to I/O {objtype port} {desc Add a pullup}
attribute xc_pulldown : boolean; -- add a pulldown to I/O {objtype port} {desc Add a pulldown}
attribute xc_clockbuftype : string; -- {objtype input_port} {default BUFGDLL} {desc Use the Xilinx BUFGDLL clock buffer}
attribute xc_padtype : string; -- {objtype port} {desc Applies an I/O standard to an I/O buffer}
-- Top level architecture attributes
-- number of global buffers, used only for XC4000, XC4000E
attribute syn_global_buffers : integer; -- {objtype global} {desc Number of global buffers}
attribute xc_use_timespec_for_io : boolean; -- {objtype global} {desc Enable use of from-to timepsec instead of offset for I/O constraint} {default 0}
-- Xilinx Modular Design Flow --
attribute xc_pseudo_pin_loc : string; -- {objtype signal} {default CLB_RrrCcc:CLB_RrrCcc} {desc Pseudo pin location on place and route block }
attribute xc_modular_design : boolean; -- {objtype global } {default 1} {desc Enable modular design flow }
attribute xc_modular_region : string; -- {objtype cell } {default rr#cc#rr#cc} {desc Specifies the number of CLB's for a modular region}
-- Xilinx Incremental Design Flow --
attribute xc_area_group : string; -- {objtype cell } {default rr#cc#rr#cc} {desc Specifies the region where instance should be placed}
-- Black box attributes
-- {family $xilinx}
attribute xc_alias : string; -- cell name change in XNF writer {noscope}
attribute xc_props : string; -- extra XNF attributes to pass for instance {objtype cell} {desc Extra XNF attributes to pass for instance}
attribute xc_map : string; -- used to map entity to fmap/hmap/lut {objtype module} {desc Map entity to fmap/hmap/lut} {enum fmap hmap lut}
attribute xc_isgsr : boolean; -- used to mark port of core with built in GSR {noscope}
attribute syn_tristatetomux : integer ; -- {objtype module global} {desc Threshold for converting tristates to mux}
attribute syn_edif_bit_format : string ; -- {objtype global} {desc Format bus names} {enum %u<%i> %u[%i] %u(%i) %u_%i %u%i %d<%i> %d[%i] %d(%i) %d_%i %d%i %n<%i> %n[%i] %n(%i) %n_%i %n%i}
attribute syn_edif_scalar_format : string; -- {objtype global} {desc Format scaler names} {enum %u %n %d}
attribute xc_fast_auto : boolean; -- {objtype global} {desc Enable automatic fast output buffer use}
-- Triscend
-- {family $triscend}
attribute tr_map : string; -- used to map entity to LUT {objtype module} {desc Map entity to LUT}
attribute syn_props : string; -- extra attributes to pass to EDIF for instance {objtype cell} {desc Extra attributes to pass to EDIF for instance}
-- syn_replicate controls replication of registers
-- {family $virtex $virtex2 $altera $apex $apexe $apex20k}
attribute syn_replicate : boolean; -- {objtype global register} {desc Controls replication of registers} {default 0}
-- {family $xilinx}
attribute syn_verification_options : string; -- {objtype module} {default black_box} {desc Allows a module to be defined as a black_box for verification }
end attributes;
|
mit
|
impedimentToProgress/UCI-BlueChip
|
AttackFiles/Attacks/memAttack/lib/gaisler/ddr/ddrsp16a.vhd
|
2
|
22870
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ddrsp16a
-- File: ddrsp16a.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: 16-bit DDR266 memory controller with asych AHB interface
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use grlib.devices.all;
use gaisler.memctrl.all;
library techmap;
use techmap.gencomp.all;
entity ddrsp16a is
generic (
memtech : integer := 0;
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
MHz : integer := 100;
col : integer := 9;
Mbyte : integer := 8;
fast : integer := 0;
pwron : integer := 0;
oepol : integer := 0
);
port (
rst : in std_ulogic;
clk_ddr : in std_ulogic;
clk_ahb : in std_ulogic;
clkread : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in sdctrl_in_type;
sdo : out sdctrl_out_type
);
end;
architecture rtl of ddrsp16a is
constant REVISION : integer := 0;
constant CMD_PRE : std_logic_vector(2 downto 0) := "010";
constant CMD_REF : std_logic_vector(2 downto 0) := "100";
constant CMD_LMR : std_logic_vector(2 downto 0) := "110";
constant CMD_EMR : std_logic_vector(2 downto 0) := "111";
constant abuf : integer := 6;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_DDRSP, 0, REVISION, 0),
4 => ahb_membar(haddr, '1', '1', hmask),
5 => ahb_iobar(ioaddr, iomask),
others => zero32);
type mcycletype is (midle, active, ext, leadout);
type ahb_state_type is (midle, rhold, dread, dwrite, whold1, whold2);
type sdcycletype is (act1, act2, act3, rd1, rd2, rd3, rd4, rd5, rd6, rd7, rd8,
wr1, wr2, wr3, wr4a, wr4, wr5, sidle, ioreg1, ioreg2);
type icycletype is (iidle, pre, ref1, ref2, emode, lmode, finish);
-- sdram configuration register
type sdram_cfg_type is record
command : std_logic_vector(2 downto 0);
csize : std_logic_vector(1 downto 0);
bsize : std_logic_vector(2 downto 0);
trcd : std_ulogic; -- tCD : 2/3 clock cycles
trfc : std_logic_vector(2 downto 0);
trp : std_ulogic; -- precharge to activate: 2/3 clock cycles
refresh : std_logic_vector(11 downto 0);
renable : std_ulogic;
dllrst : std_ulogic;
refon : std_ulogic;
cke : std_ulogic;
end record;
type access_param is record
haddr : std_logic_vector(31 downto 0);
size : std_logic_vector(1 downto 0);
hwrite : std_ulogic;
hio : std_ulogic;
end record;
-- local registers
type ahb_reg_type is record
hready : std_ulogic;
hsel : std_ulogic;
hio : std_ulogic;
startsd : std_ulogic;
ready : std_ulogic;
ready2 : std_ulogic;
write : std_ulogic;
state : ahb_state_type;
haddr : std_logic_vector(31 downto 0);
hrdata : std_logic_vector(31 downto 0);
hwdata : std_logic_vector(31 downto 0);
hwrite : std_ulogic;
htrans : std_logic_vector(1 downto 0);
hresp : std_logic_vector(1 downto 0);
raddr : std_logic_vector(abuf-1 downto 0);
size : std_logic_vector(1 downto 0);
acc : access_param;
end record;
type ddr_reg_type is record
startsd : std_ulogic;
startsdold : std_ulogic;
burst : std_ulogic;
hready : std_ulogic;
bdrive : std_ulogic;
qdrive : std_ulogic;
nbdrive : std_ulogic;
mstate : mcycletype;
sdstate : sdcycletype;
cmstate : mcycletype;
istate : icycletype;
trfc : std_logic_vector(2 downto 0);
refresh : std_logic_vector(11 downto 0);
sdcsn : std_logic_vector(1 downto 0);
sdwen : std_ulogic;
rasn : std_ulogic;
casn : std_ulogic;
dqm : std_logic_vector(3 downto 0);
address : std_logic_vector(15 downto 2); -- memory address
ba : std_logic_vector(1 downto 0);
waddr : std_logic_vector(abuf-1 downto 0);
cfg : sdram_cfg_type;
end record;
signal vcc, rwrite : std_ulogic;
signal r, ri : ddr_reg_type;
signal ra, rai : ahb_reg_type;
signal rdata, wdata, rwdata, rbdrive, ribdrive : std_logic_vector(31 downto 0);
signal waddr2 : std_logic_vector(abuf-1 downto 0);
attribute syn_preserve : boolean;
attribute syn_preserve of rbdrive : signal is true;
begin
vcc <= '1';
ahb_ctrl : process(rst, ahbsi, r, ra, rdata)
variable v : ahb_reg_type; -- local variables for registers
variable startsd : std_ulogic;
variable dout : std_logic_vector(31 downto 0);
begin
v := ra; v.hrdata := rdata; v.hresp := HRESP_OKAY;
v.write := '0';
v.ready := not (ra.startsd xor r.startsdold);
v.ready2 := ra.ready;
if ((ahbsi.hready and ahbsi.hsel(hindex)) = '1') then
v.htrans := ahbsi.htrans; v.haddr := ahbsi.haddr;
v.size := ahbsi.hsize(1 downto 0); v.hwrite := ahbsi.hwrite;
if ahbsi.htrans(1) = '1' then
v.hio := ahbsi.hmbsel(1);
v.hsel := '1'; v.hready := '0';
end if;
end if;
if ahbsi.hready = '1' then v.hsel := ahbsi.hsel(hindex); end if;
-- if (ra.hsel and ra.hio and not ra.hready) = '1' then v.hready := '1'; end if;
case ra.state is
when midle =>
if ((v.hsel and v.htrans(1)) = '1') then
if v.hwrite = '0' then
v.state := rhold; v.startsd := not ra.startsd;
else v.state := dwrite; v.hready := '1'; v.write := '1'; end if;
end if;
v.raddr := ra.haddr(7 downto 2);
v.ready := '0'; v.ready2 := '0';
if ahbsi.hready = '1' then
v.acc := (v.haddr, v.size, v.hwrite, v.hio);
end if;
when rhold =>
v.raddr := ra.haddr(7 downto 2);
if ra.ready2 = '1' then
v.state := dread; v.hready := '1'; v.raddr := ra.raddr + 1;
end if;
when dread =>
v.raddr := ra.raddr + 1; v.hready := '1';
if ((v.hsel and v.htrans(1) and v.htrans(0)) = '0') or
(ra.raddr(2 downto 0) = "000")
-- then v.state := midle; v.hready := '0'; end if;
then
v.state := midle; v.hready := not (v.hsel and v.htrans(1));
if (v.hsel and v.htrans(1) and v.hwrite) = '1' then
v.state := dwrite; v.hready := '1'; v.write := '1';
v.ready := '0'; v.ready2 := '0';
end if;
end if;
v.acc := (v.haddr, v.size, v.hwrite, v.hio);
when dwrite =>
v.raddr := ra.haddr(7 downto 2); v.write := '1'; v.hready := '1';
if ((v.hsel and v.htrans(1) and v.htrans(0)) = '0') or
((ra.haddr(4 downto 2) = "111") and (ra.write = '1'))
then
v.startsd := not ra.startsd; v.state := whold1;
v.write := '0'; v.hready := not (v.hsel and v.htrans(1));
-- v.write := '0'; v.hready := '0';
end if;
when whold1 =>
v.state := whold2; v.ready := '0';
when whold2 =>
if ra.ready = '1' then
v.state := midle; v.acc := (v.haddr, v.size, v.hwrite, v.hio);
end if;
end case;
v.hwdata := ahbsi.hwdata;
if (ahbsi.hready and ahbsi.hsel(hindex) ) = '1' then
if ahbsi.htrans(1) = '0' then v.hready := '1'; end if;
end if;
-- if (ra.hsel and ra.hio) = '1' then dout := regsd;
-- else dout := ra.hrdata(31 downto 0); end if;
dout := ra.hrdata(31 downto 0);
if rst = '0' then
v.hsel := '0';
v.hready := '1';
v.state := midle;
v.startsd := '0';
v.hio := '0';
end if;
rai <= v;
ahbso.hready <= ra.hready;
ahbso.hresp <= ra.hresp;
ahbso.hrdata <= dout;
ahbso.hcache <= not ra.hio;
end process;
ddr_ctrl : process(rst, r, ra, sdi, rbdrive, wdata)
variable v : ddr_reg_type; -- local variables for registers
variable startsd : std_ulogic;
variable dataout : std_logic_vector(31 downto 0); -- data from memory
variable dqm : std_logic_vector(3 downto 0);
variable raddr : std_logic_vector(13 downto 0);
variable adec : std_ulogic;
variable rams : std_logic_vector(1 downto 0);
variable ba : std_logic_vector(1 downto 0);
variable haddr : std_logic_vector(31 downto 0);
variable hsize : std_logic_vector(1 downto 0);
variable hwrite : std_ulogic;
variable htrans : std_logic_vector(1 downto 0);
variable hready : std_ulogic;
variable vbdrive : std_logic_vector(31 downto 0);
variable bdrive : std_ulogic;
variable writecfg: std_ulogic;
variable regsd : std_logic_vector(31 downto 0); -- data from registers
variable readdata: std_logic_vector(31 downto 0); -- data from DDR
begin
-- Variable default settings to avoid latches
v := r; v.hready := '0'; writecfg := '0'; vbdrive := rbdrive;
readdata := sdi.data(31 downto 0);
v.qdrive :='0';
regsd := (others => '0');
if ra.acc.haddr(2) = '0' then
regsd(31 downto 15) := r.cfg.refon & r.cfg.trp & r.cfg.trfc &
r.cfg.trcd & r.cfg.bsize & r.cfg.csize & r.cfg.command &
r.cfg.dllrst & r.cfg.renable & r.cfg.cke;
regsd(11 downto 0) := r.cfg.refresh;
else
regsd(8 downto 0) := conv_std_logic_vector(MHz, 9);
regsd(14 downto 12) := conv_std_logic_vector(1, 3);
end if;
-- generate DQM from address and write size
case ra.acc.size is
when "00" =>
case ra.acc.haddr(1 downto 0) is
when "00" => dqm := "0111";
when "01" => dqm := "1011";
when "10" => dqm := "1101";
when others => dqm := "1110";
end case;
when "01" =>
if ra.acc.haddr(1) = '0' then dqm := "0011"; else dqm := "1100"; end if;
when others => dqm := "0000";
end case;
v.startsd := ra.startsd;
-- main FSM
case r.mstate is
when midle =>
if r.startsd = '1' then
if (r.sdstate = sidle) and (r.cfg.command = "000") and
(r.cmstate = midle)
then
startsd := '1'; v.mstate := active;
end if;
end if;
when others => null;
end case;
startsd := r.startsd xor r.startsdold;
-- generate row and column address size
haddr := ra.acc.haddr;
haddr(31 downto 20) := haddr(31 downto 20) and not conv_std_logic_vector(hmask, 12);
case r.cfg.csize is
when "00" => raddr := haddr(23 downto 10);
when "01" => raddr := haddr(24 downto 11);
when "10" => raddr := haddr(25 downto 12);
when others => raddr := haddr(26 downto 13);
end case;
-- generate bank address
ba := genmux(r.cfg.bsize, haddr(29 downto 22)) &
genmux(r.cfg.bsize, haddr(28 downto 21));
-- generate chip select
adec := genmux(r.cfg.bsize, haddr(30 downto 23));
rams := adec & not adec;
-- sdram access FSM
if r.trfc /= "000" then v.trfc := r.trfc - 1; end if;
case r.sdstate is
when sidle =>
if (startsd = '1') and (r.cfg.command = "000") and (r.cmstate = midle)
and (r.istate = finish)
then
v.address := raddr; v.ba := ba;
if ra.acc.hio = '0' then
v.sdcsn := not rams(1 downto 0); v.rasn := '0'; v.sdstate := act1;
else v.sdstate := ioreg1; end if;
end if;
v.waddr := ra.acc.haddr(7 downto 2);
when act1 =>
v.rasn := '1'; v.trfc := r.cfg.trfc;
if r.cfg.trcd = '1' then v.sdstate := act2; else
v.sdstate := act3; v.hready := ra.acc.hwrite;
end if;
v.waddr := ra.acc.haddr(7 downto 2);
when act2 =>
v.sdstate := act3; v.hready := ra.acc.hwrite;
when act3 =>
v.casn := '0';
v.address := ra.acc.haddr(13 downto 11) & '0' & ra.acc.haddr(10 downto 2) & '0';
v.dqm := dqm;
if ra.acc.hwrite = '1' then
v.waddr := r.waddr + 1;
v.sdstate := wr1; v.sdwen := '0'; v.bdrive := '0'; v.qdrive := '1';
if (r.waddr /= ra.raddr) then v.hready := '1'; end if;
else v.sdstate := rd1; end if;
when wr1 =>
v.sdwen := '1'; v.casn := '1'; v.qdrive := '1';
v.waddr := r.waddr + 1;
v.address(8 downto 3) := r.waddr;
if (r.waddr <= ra.raddr) and (r.waddr /= "000000") and (r.hready = '1')
then
v.hready := '1';
if (r.hready = '1') and (r.waddr(1 downto 0) = "00") then
v.sdwen := '0'; v.casn := '0';
end if;
else
v.sdstate := wr2;
v.dqm := (others => '1'); --v.bdrive := '1';
v.startsdold := r.startsd;
end if;
when wr2 =>
v.sdstate := wr3; v.qdrive := '1';
when wr3 =>
v.sdstate := wr4a; v.qdrive := '1';
when wr4a =>
v.bdrive := '1';
v.rasn := '0'; v.sdwen := '0'; v.sdstate := wr4; v.qdrive := '1';
when wr4 =>
v.sdcsn := "11"; v.rasn := '1'; v.sdwen := '1'; v.qdrive := '0';
v.sdstate := wr5;
when wr5 =>
v.sdstate := sidle;
when rd1 =>
v.casn := '1'; v.sdstate := rd7;
if ra.acc.haddr(4 downto 2) = "011" then
v.casn := '0'; v.burst := '1'; v.address(5 downto 3) := "100";
end if;
when rd7 =>
v.casn := '1'; v.sdstate := rd2;
if ra.acc.haddr(4 downto 2) = "010" then
v.casn := '0'; v.burst := '1'; v.address(5 downto 3) := "100";
end if;
when rd2 =>
v.casn := '1'; v.sdstate := rd3;
if ra.acc.haddr(4 downto 2) = "001" then
v.casn := '0'; v.burst := '1'; v.address(5 downto 3) := "100";
end if;
when rd3 =>
if fast = 0 then v.startsdold := r.startsd; end if;
v.sdstate := rd4; v.hready := '1'; v.casn := '1';
if r.sdwen = '0' then
v.rasn := '1'; v.sdwen := '1'; v.sdcsn := "11"; v.dqm := (others => '1');
elsif ra.acc.haddr(4 downto 2) = "000" then
v.casn := '0'; v.burst := '1'; v.address(5) := '1';
v.waddr := v.address(8 downto 3);
end if;
if v.hready = '1' then v.waddr := r.waddr + 1; end if;
when rd4 =>
v.hready := '1'; v.casn := '1';
if (r.sdcsn /= "11") and (r.waddr(1 downto 0) = "11") and (r.burst = '1')
then
v.burst := '0';
elsif (r.sdcsn = "11") or (r.waddr(1 downto 0) = "11") then
v.dqm := (others => '1'); v.burst := '0';
if fast /= 0 then v.startsdold := r.startsd; end if;
if (r.sdcsn /= "11") then
v.rasn := '0'; v.sdwen := '0'; v.sdstate := rd5;
else
if r.cfg.trp = '1' then v.sdstate := rd6;
else v.sdstate := sidle; end if;
end if;
end if;
if v.hready = '1' then v.waddr := r.waddr + 1; end if;
when rd5 =>
if r.cfg.trp = '1' then v.sdstate := rd6;
else v.sdstate := sidle; end if;
v.sdcsn := (others => '1'); v.rasn := '1'; v.sdwen := '1';
v.dqm := (others => '1');
when rd6 =>
v.sdstate := sidle; v.dqm := (others => '1');
v.sdcsn := (others => '1'); v.rasn := '1'; v.sdwen := '1';
when ioreg1 =>
readdata := regsd; v.sdstate := ioreg2;
if ra.acc.hwrite = '0' then v.hready := '1'; end if;
when ioreg2 =>
readdata := regsd; v.sdstate := sidle;
writecfg := ra.acc.hwrite; v.startsdold := r.startsd;
when others =>
v.sdstate := sidle;
end case;
-- sdram commands
case r.cmstate is
when midle =>
if r.sdstate = sidle then
case r.cfg.command is
when CMD_PRE => -- precharge
v.sdcsn := (others => '0'); v.rasn := '0'; v.sdwen := '0';
v.address(12) := '1'; v.cmstate := active;
when CMD_REF => -- auto-refresh
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.cmstate := active;
when CMD_EMR => -- load-ext-mode-reg
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.sdwen := '0'; v.cmstate := active; v.ba := "01";
v.address := "00000000000000";
when CMD_LMR => -- load-mode-reg
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.sdwen := '0'; v.cmstate := active; v.ba := "00";
v.address := "00000" & r.cfg.dllrst & "0" & "01" & "00011";
when others => null;
end case;
end if;
when active =>
v.sdcsn := (others => '1'); v.rasn := '1'; v.casn := '1';
v.sdwen := '1'; v.cfg.command := "000";
v.cmstate := leadout; v.trfc := r.cfg.trfc;
when others =>
if r.trfc = "000" then v.cmstate := midle; end if;
end case;
-- sdram init
case r.istate is
when iidle =>
if r.cfg.renable = '1' then
v.cfg.cke := '1'; v.cfg.dllrst := '1';
if r.cfg.cke = '1' then v.istate := pre; v.cfg.command := CMD_PRE; end if;
end if;
when pre =>
if r.cfg.command = "000" then
v.cfg.command := "11" & r.cfg.dllrst; -- CMD_LMR/CMD_EMR
if r.cfg.dllrst = '1' then v.istate := emode; else v.istate := lmode; end if;
end if;
when emode =>
if r.cfg.command = "000" then
v.istate := lmode; v.cfg.command := CMD_LMR;
end if;
when lmode =>
if r.cfg.command = "000" then
if r.cfg.dllrst = '1' then
if r.refresh(9 downto 8) = "00" then -- > 200 clocks delay
v.cfg.command := CMD_PRE; v.istate := ref1;
end if;
else
v.istate := finish; --v.cfg.command := CMD_LMR;
v.cfg.refon := '1'; v.cfg.renable := '0';
end if;
end if;
when ref1 =>
if r.cfg.command = "000" then
v.cfg.command := CMD_REF; v.cfg.dllrst := '0'; v.istate := ref2;
end if;
when ref2 =>
if r.cfg.command = "000" then
v.cfg.command := CMD_REF; v.istate := pre;
end if;
when others =>
if r.cfg.renable = '1' then
v.istate := iidle; v.cfg.dllrst := '1';
end if;
end case;
-- second part of main fsm
case r.mstate is
when active =>
if v.hready = '1' then
v.mstate := midle;
end if;
when others => null;
end case;
-- sdram refresh counter
if ((r.cfg.refon = '1') and (r.istate = finish)) or
(r.cfg.dllrst = '1')
then
v.refresh := r.refresh - 1;
if (v.refresh(11) and not r.refresh(11)) = '1' then
v.refresh := r.cfg.refresh;
if r.cfg.dllrst = '0' then v.cfg.command := "100"; end if;
end if;
end if;
-- AHB register access
if (ra.acc.hio and ra.acc.hwrite and writecfg) = '1' then
v.cfg.refresh := wdata(11 downto 0);
v.cfg.cke := wdata(15);
v.cfg.renable := wdata(16);
v.cfg.dllrst := wdata(17);
v.cfg.command := wdata(20 downto 18);
v.cfg.csize := wdata(22 downto 21);
v.cfg.bsize := wdata(25 downto 23);
v.cfg.trcd := wdata(26);
v.cfg.trfc := wdata(29 downto 27);
v.cfg.trp := wdata(30);
v.cfg.refon := wdata(31);
end if;
v.nbdrive := not v.bdrive;
if oepol = 1 then bdrive := r.nbdrive; vbdrive := (others => v.nbdrive);
else bdrive := r.bdrive; vbdrive := (others => v.bdrive);end if;
-- reset
if rst = '0' then
v.sdstate := sidle;
v.mstate := midle;
v.istate := finish;
v.cmstate := midle;
v.cfg.command := "000";
v.cfg.csize := conv_std_logic_vector(col-9, 2);
v.cfg.bsize := conv_std_logic_vector(log2(Mbyte/8), 3);
if MHz > 100 then v.cfg.trcd := '1'; else v.cfg.trcd := '0'; end if;
v.cfg.refon := '0';
v.cfg.trfc := conv_std_logic_vector(75*MHz/1000-2, 3);
v.cfg.refresh := conv_std_logic_vector(7800*MHz/1000, 12);
v.refresh := (others => '0');
if pwron = 1 then v.cfg.renable := '1';
else v.cfg.renable := '0'; end if;
if MHz > 100 then v.cfg.trp := '1'; else v.cfg.trp := '0'; end if;
v.dqm := (others => '1');
v.sdwen := '1';
v.rasn := '1';
v.casn := '1';
v.hready := '0';
v.startsd := '0';
v.startsdold := '0';
v.cfg.dllrst := '0';
v.cfg.cke := '0';
end if;
ri <= v;
ribdrive <= vbdrive;
rwdata <= readdata;
end process;
sdo.sdcke <= (others => r.cfg.cke);
ahbso.hconfig <= hconfig;
ahbso.hirq <= (others => '0');
ahbso.hindex <= hindex;
ahbregs : process(clk_ahb) begin
if rising_edge(clk_ahb) then
ra <= rai;
end if;
end process;
ddrregs : process(clk_ddr, rst) begin
if rising_edge(clk_ddr) then
r <= ri; rbdrive <= ribdrive;
end if;
if (rst = '0') then
r.sdcsn <= (others => '1'); r.bdrive <= '1'; r.nbdrive <= '0';
if oepol = 0 then rbdrive <= (others => '1');
else rbdrive <= (others => '0'); end if;
r.cfg.cke <= '0';
end if;
end process;
ddr_read_regs : process(clkread) begin
if rising_edge(clkread) then
rwrite <= ri.hready; waddr2 <= r.waddr;
end if;
end process;
sdo.address <= '0' & ri.address;
sdo.ba <= ri.ba;
sdo.bdrive <= r.nbdrive when oepol = 1 else r.bdrive;
sdo.qdrive <= not (ri.qdrive or r.nbdrive);
sdo.vbdrive <= rbdrive;
sdo.sdcsn <= ri.sdcsn;
sdo.sdwen <= ri.sdwen;
sdo.dqm <= "111111111111" & r.dqm;
sdo.rasn <= ri.rasn;
sdo.casn <= ri.casn;
sdo.data <= zero32 & zero32 & zero32 & wdata;
read_buff : syncram_2p
generic map (tech => memtech, abits => 6, dbits => 32, sepclk => 1, wrfst => 0)
port map ( rclk => clk_ahb, renable => vcc, raddress => rai.raddr,
dataout => rdata, wclk => clk_ddr, write => ri.hready,
-- dataout => rdata, wclk => clkread, write => rwrite,
waddress => r.waddr, datain => rwdata);
-- waddress => waddr2, datain => rwdata);
write_buff : syncram_2p
generic map (tech => memtech, abits => 6, dbits => 32, sepclk => 1, wrfst => 0)
port map ( rclk => clk_ddr, renable => vcc, raddress => r.waddr,
dataout => wdata, wclk => clk_ahb, write => ra.write,
waddress => ra.haddr(7 downto 2), datain => ahbsi.hwdata);
-- pragma translate_off
bootmsg : report_version
generic map (
msg1 => "ddrsp" & tost(hindex) & ": 16-bit DDR266 controller rev " &
tost(REVISION) & ", " & tost(Mbyte) & " Mbyte, " & tost(MHz) &
" MHz DDR clock");
-- pragma translate_on
end;
|
mit
|
impedimentToProgress/UCI-BlueChip
|
AttackFiles/Attacks/privEsc/lib/gaisler/ambatest/ambatest.vhd
|
2
|
20524
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ambatest
-- File: ambatest.vhd
-- Author: Alf Vaerneus
-- Description: Test package for emulators
------------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
library gaisler;
use grlib.devices.all;
use grlib.stdlib.all;
library std;
use std.textio.all;
package ambatest is
function printhex(value : std_logic_vector; len : integer) return string;
function conv_std_logic_vector(value : string; len : integer) return std_logic_vector;
function trimlen(str : string) return integer;
procedure printf(str : string; timestamp : boolean := false);
procedure printf(str : string; vari : integer; timestamp : boolean := false);
procedure printf(str : string; vari : std_logic_vector; timestamp : boolean := false);
procedure printf(str : string; vari : string; timestamp : boolean := false);
procedure compfiles(file1 : string(18 downto 1); file2 : string(18 downto 1); format : integer);
procedure compfiles(file1 : string(18 downto 1); file2 : string(18 downto 1); format : integer; printlvl : integer; err : out boolean);
type command_type is (RD_SINGLE,
RD_INCR,
RD_WRAP4,
RD_INCR4,
RD_WRAP8,
RD_INCR8,
RD_WRAP16,
RD_INCR16,
WR_SINGLE,
WR_INCR,
WR_WRAP4,
WR_INCR4,
WR_WRAP8,
WR_INCR8,
WR_WRAP16,
WR_INCR16,
M_READ,
M_READ_LINE,
M_READ_MULT,
M_WRITE,
M_WRITE_INV,
C_READ,
C_WRITE,
I_READ,
I_WRITE
);
constant MAX_NO_TB : integer := 20;
type tb_in_type is record
address : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
start : std_logic;
command : command_type;
no_words : natural;
userfile : boolean;
usewfile : boolean;
rfile : string(18 downto 1);
wfile : string(18 downto 1);
end record;
type tbi_array_type is array(0 to MAX_NO_TB) of tb_in_type;
type status_type is (OK, ERR, TIMEOUT, RETRY);
type tb_out_type is record
data : std_logic_vector(31 downto 0);
ready : std_logic;
status : status_type;
end record;
type tbo_array_type is array(0 to MAX_NO_TB) of tb_out_type;
type ctrl_type is record
address : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
status : status_type;
curword : natural;
no_words : natural;
userfile : boolean;
usewfile : boolean;
rfile : string(18 downto 1);
wfile : string(18 downto 1);
end record;
constant tb_in_init : tb_in_type := (
address => (others => '0'),
data => (others => '0'),
start => '0',
command => RD_SINGLE,
no_words => 0,
userfile => false,
usewfile => false,
rfile => " ",
wfile => " ");
constant ctrl_init : ctrl_type := (
address => (others => '0'),
data => (others => '0'),
status => OK,
curword => 0,
no_words => 1,
userfile => false,
usewfile => false,
rfile => " ",
wfile => " ");
constant AHB_IDLE : ahb_mst_out_type := (
hbusreq => '0',
hlock => '0',
htrans => HTRANS_IDLE,
haddr => (others => '0'),
hwrite => '0',
hsize => HSIZE_WORD,
hburst => HBURST_SINGLE,
hprot => (others => '0'),
hwdata => (others => '0'),
hirq => (others => '0'),
hconfig => (others => zero32),
hindex => 0
);
constant READ_SINGLE : ahb_mst_out_type := (
hbusreq => '0',
hlock => '0',
htrans => HTRANS_NONSEQ,
haddr => (others => '0'),
hwrite => '0',
hsize => HSIZE_WORD,
hburst => HBURST_SINGLE,
hprot => (others => '0'),
hwdata => (others => '0'),
hirq => (others => '0'),
hconfig => (others => zero32),
hindex => 0
);
constant READ_INCR : ahb_mst_out_type := (
hbusreq => '0',
hlock => '0',
htrans => HTRANS_NONSEQ,
haddr => (others => '0'),
hwrite => '0',
hsize => HSIZE_WORD,
hburst => HBURST_INCR,
hprot => (others => '0'),
hwdata => (others => '0'),
hirq => (others => '0'),
hconfig => (others => zero32),
hindex => 0
);
constant WRITE_SINGLE : ahb_mst_out_type := (
hbusreq => '0',
hlock => '0',
htrans => HTRANS_NONSEQ,
haddr => (others => '0'),
hwrite => '1',
hsize => HSIZE_WORD,
hburst => HBURST_SINGLE,
hprot => (others => '0'),
hwdata => (others => '0'),
hirq => (others => '0'),
hconfig => (others => zero32),
hindex => 0
);
constant WRITE_INCR : ahb_mst_out_type := (
hbusreq => '0',
hlock => '0',
htrans => HTRANS_NONSEQ,
haddr => (others => '0'),
hwrite => '1',
hsize => HSIZE_WORD,
hburst => HBURST_INCR,
hprot => (others => '0'),
hwdata => (others => '0'),
hirq => (others => '0'),
hconfig => (others => zero32),
hindex => 0
);
-- AHB Master Emulator
component ahbmst_em
generic(
hindex : integer := 0;
timeoutc : integer := 100;
dbglevel : integer := 2
);
port(
rst : in std_logic;
clk : in std_logic;
-- AMBA signals
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
-- TB signals
tbi : in tb_in_type;
tbo : out tb_out_type
);
end component;
-- AHB Slave Emulator
component ahbslv_em
generic(
hindex : integer := 0;
abits : integer := 10;
waitcycles : integer := 2;
retries : integer := 0;
memaddr : integer := 16#E00#;
memmask : integer := 16#FFF#;
ioaddr : integer := 16#000#;
timeoutc : integer := 100;
dbglevel : integer := 2
);
port(
rst : in std_logic;
clk : in std_logic;
-- AMBA signals
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
-- TB signals
tbi : in tb_in_type;
tbo : out tb_out_type
);
end component;
end ambatest;
package body ambatest is
function printhex( value : std_logic_vector; len : integer) return string is
variable str1, str2 : string (1 to 8);
variable stmp : string (8 downto 1);
variable x : std_logic_vector(31 downto 0);
begin
x:= (others => '0');
x(len-1 downto 0) := value;
case len is
when 4 | 8 | 12 | 16 | 20 | 24 | 28 | 32 =>
for i in 0 to (len/4)-1 loop
case conv_integer(x(((len-1)-(i*4)) downto ((len-1)-(i*4)-3))) is
when 0 => stmp(i+1) := '0';
when 1 => stmp(i+1) := '1';
when 2 => stmp(i+1) := '2';
when 3 => stmp(i+1) := '3';
when 4 => stmp(i+1) := '4';
when 5 => stmp(i+1) := '5';
when 6 => stmp(i+1) := '6';
when 7 => stmp(i+1) := '7';
when 8 => stmp(i+1) := '8';
when 9 => stmp(i+1) := '9';
when 10 => stmp(i+1) := 'A';
when 11 => stmp(i+1) := 'B';
when 12 => stmp(i+1) := 'C';
when 13 => stmp(i+1) := 'D';
when 14 => stmp(i+1) := 'E';
when 15 => stmp(i+1) := 'F';
when others => stmp(i+1) := 'X';
end case;
end loop;
when others => stmp := (others => ' ');
end case;
str2(1 to 8) := stmp(8 downto 1);
for i in 1 to 8 loop
str1(i) := str2(9-i);
end loop;
return(str1);
end printhex;
function to_char( x : INTEGER range 0 to 15) return character is
begin
case x is
when 0 => return('0');
when 1 => return('1');
when 2 => return('2');
when 3 => return('3');
when 4 => return('4');
when 5 => return('5');
when 6 => return('6');
when 7 => return('7');
when 8 => return('8');
when 9 => return('9');
when 10 => return('A');
when 11 => return('B');
when 12 => return('C');
when 13 => return('D');
when 14 => return('E');
when 15 => return('F');
end case;
end to_char;
function conv_std_logic_vector(value : string; len : integer) return std_logic_vector is
variable tmpvect : std_logic_vector(31 downto 0);
variable str1,str2 : string(1 to 8);
begin
str1 := value;
for i in 1 to (len/4) loop
str2(i) := str1(((len/4)+1)-i);
end loop;
case len is
when 4 | 8 | 12 | 16 | 20 | 24 | 28 | 32 =>
for i in 0 to 7 loop
case str2(i+1) is
when '0' => tmpvect(((i*4)+3) downto (i*4)) := "0000";
when '1' => tmpvect(((i*4)+3) downto (i*4)) := "0001";
when '2' => tmpvect(((i*4)+3) downto (i*4)) := "0010";
when '3' => tmpvect(((i*4)+3) downto (i*4)) := "0011";
when '4' => tmpvect(((i*4)+3) downto (i*4)) := "0100";
when '5' => tmpvect(((i*4)+3) downto (i*4)) := "0101";
when '6' => tmpvect(((i*4)+3) downto (i*4)) := "0110";
when '7' => tmpvect(((i*4)+3) downto (i*4)) := "0111";
when '8' => tmpvect(((i*4)+3) downto (i*4)) := "1000";
when '9' => tmpvect(((i*4)+3) downto (i*4)) := "1001";
when 'A' => tmpvect(((i*4)+3) downto (i*4)) := "1010";
when 'B' => tmpvect(((i*4)+3) downto (i*4)) := "1011";
when 'C' => tmpvect(((i*4)+3) downto (i*4)) := "1100";
when 'D' => tmpvect(((i*4)+3) downto (i*4)) := "1101";
when 'E' => tmpvect(((i*4)+3) downto (i*4)) := "1110";
when 'F' => tmpvect(((i*4)+3) downto (i*4)) := "1111";
when 'a' => tmpvect(((i*4)+3) downto (i*4)) := "1010";
when 'b' => tmpvect(((i*4)+3) downto (i*4)) := "1011";
when 'c' => tmpvect(((i*4)+3) downto (i*4)) := "1100";
when 'd' => tmpvect(((i*4)+3) downto (i*4)) := "1101";
when 'e' => tmpvect(((i*4)+3) downto (i*4)) := "1110";
when 'f' => tmpvect(((i*4)+3) downto (i*4)) := "1111";
when others => tmpvect(((i*4)+3) downto (i*4)) := "0000";
end case;
end loop;
when others => tmpvect := (others => '0');
end case;
return(tmpvect(len-1 downto 0));
end conv_std_logic_vector;
procedure printf(str : string; timestamp : boolean := false) is
variable lenstr,offset,i : integer;
variable rstr : string(1 to 128);
variable L : line;
begin
lenstr := str'length; offset := 1; i := 1;
while i <= lenstr loop
rstr(offset) := str(i); offset := offset+1; i := i+1;
end loop;
rstr(offset+1) := NUL;
if timestamp then
write(L, rstr & " : ");
write(L, Now, Left, 15);
else
write(L,rstr);
end if;
writeline(output,L);
end procedure;
procedure printf(str : string; vari : integer; timestamp : boolean := false) is
variable lenstr,offset,i,j,x,y,z : integer;
variable rstr : string(1 to 128);
variable tmpstr : string(1 to 8);
variable remzer : boolean;
variable L : line;
begin
lenstr := str'length; offset := 1; i := 1; x := vari;
while i <= lenstr loop
if str(i) = '%' then
if vari = 0 then
rstr(offset) := '0'; offset := offset+1;
else
if vari = 0 then tmpstr := (others => '0');
else
j := 8;
l2: while true loop
j := j-1;
exit l2 when j = 0;
y := x/10;
z := x - y*10;
x := y;
tmpstr(j) := to_char(z);
end loop;
if x>0 then printf("Value is out of range"); end if;
end if;
-- tmpstr := printhex(conv_std_logic_vector(vari,32),32);
remzer := false;
for k in 1 to 8 loop
if (tmpstr(k) /= '0' or remzer = true) then
rstr(offset) := tmpstr(k); remzer := true; offset := offset+1;
end if;
end loop;
end if;
i := i+2;
else
rstr(offset) := str(i); offset := offset+1; i := i+1;
end if;
end loop;
rstr(offset+1) := NUL;
if timestamp then
write(L, rstr & " : ");
write(L, Now, Left, 15);
else
write(L,rstr);
end if;
writeline(output,L);
end procedure;
procedure printf(
str : string;
vari : std_logic_vector;
timestamp : boolean := false) is
constant zero32 : std_logic_vector(31 downto 0) := (others => '0');
variable lenstr,lenvct,offset,i : integer;
variable rstr : string(1 to 128);
variable tmpstr : string(1 to 8);
variable L : line;
begin
lenstr := str'length; offset := 1;
lenvct := vari'length; i := 1;
while i <= lenstr loop
if str(i) = '%' then
if vari = zero32(lenvct-1 downto 0) then
rstr(offset) := '0'; offset := offset+1;
else
tmpstr := printhex(vari,lenvct);
for j in 1 to 8 loop
rstr(offset) := tmpstr(j); offset := offset+1;
end loop;
end if;
i := i+2;
else
rstr(offset) := str(i); offset := offset+1; i := i+1;
end if;
end loop;
rstr(offset+1) := NUL;
if timestamp then
write(L, rstr & " : ");
write(L, Now, Left, 15);
else
write(L,rstr);
end if;
writeline(output,L);
end procedure;
function trimlen(str : string) return integer is
variable lenstr,i : integer;
begin
lenstr := str'length; i := 1;
while str(lenstr) /= ' ' loop
i := i+1 ; lenstr := lenstr-1;
end loop;
return(lenstr+1);
end function;
procedure printf(
str : string;
vari : string;
timestamp : boolean := false) is
variable lenstr,lenvct,offset,i : integer;
variable rstr : string(1 to 128);
variable L : line;
begin
lenstr := str'length; offset := 1;
lenvct := vari'length; i := 1;
while i <= lenstr loop
if str(i) = '%' then
for j in 1 to lenvct loop
rstr(offset) := vari(j); offset := offset+1;
end loop;
i := i+2;
else
rstr(offset) := str(i); offset := offset+1; i := i+1;
end if;
end loop;
rstr(offset+1) := NUL;
if timestamp then
write(L, rstr & " : ");
write(L, Now, Left, 15);
else
write(L,rstr);
end if;
writeline(output,L);
end procedure;
procedure compfiles(
file1 : string(18 downto 1);
file2 : string(18 downto 1);
format : integer) is
file comp1, comp2 : text;
variable L1, L2 : line;
variable datahex1, datahex2 : string(1 to 8);
variable dataint1, dataint2, pos, errs : integer;
begin
pos := 0; errs := 0;
file_open(comp1, external_name => file1(18 downto trimlen(file1)), open_kind => read_mode);
file_open(comp2, external_name => file2(18 downto trimlen(file2)), open_kind => read_mode);
readline(comp1,L1);
readline(comp2,L2);
pos := pos+1;
if format = 0 then
read(L1,dataint1);
read(L2,dataint2);
if dataint1 /= dataint2 then
errs := errs+1;
printf("Comparision error at pos. %d",pos);
printf("Expected data: %d",dataint1);
printf("Compared data: %d",dataint2);
end if;
elsif format = 1 then
read(L1,datahex1);
read(L2,datahex2);
if conv_std_logic_vector(datahex1,32) /= conv_std_logic_vector(datahex2,32) then
errs := errs+1;
printf("Comparision error at pos. %d",pos);
printf("Expected data: %x",datahex1);
printf("Compared data: %x",datahex2);
end if;
end if;
while not (endfile(comp1) or endfile(comp2)) loop
readline(comp1,L1);
readline(comp2,L2);
pos := pos+1;
if format = 0 then
read(L1,dataint1);
read(L2,dataint2);
if dataint1 /= dataint2 then
errs := errs+1;
printf("Comparision error at pos. %d",pos);
printf("Expected data: %d",dataint1);
printf("Compared data: %d",dataint2);
end if;
elsif format = 1 then
read(L1,datahex1);
read(L2,datahex2);
if conv_std_logic_vector(datahex1,32) /= conv_std_logic_vector(datahex2,32) then
errs := errs+1;
printf("Comparision error at pos. %d",pos);
printf("Expected data: %x",datahex1);
printf("Compared data: %x",datahex2);
end if;
end if;
end loop;
if endfile(comp1) /= endfile(comp2) then
printf("Compared files have different size!"); errs := errs+1;
end if;
file_close(comp1); file_close(comp2);
if errs = 0 then
printf("Comparision complete. No failure.");
elsif errs = 1 then
printf("Comparision complete. 1 failure.");
else
printf("Comparision complete. %d failures.",errs);
end if;
end procedure;
procedure compfiles(file1 : string(18 downto 1); file2 : string(18 downto 1); format : integer; printlvl : integer; err : out boolean) is
file comp1, comp2 : text;
variable L1, L2 : line;
variable datahex1, datahex2 : string(1 to 8);
variable dataint1, dataint2, pos, errs : integer;
begin
pos := 0; errs := 0;
file_open(comp1, external_name => file1(18 downto trimlen(file1)), open_kind => read_mode);
file_open(comp2, external_name => file2(18 downto trimlen(file2)), open_kind => read_mode);
readline(comp1,L1);
readline(comp2,L2);
pos := pos+1;
if format = 0 then
read(L1,dataint1);
read(L2,dataint2);
if dataint1 /= dataint2 then
errs := errs+1;
if printlvl /= 0 then
printf("Comparision error at pos. %d",pos);
printf("Expected data: %d",dataint1);
printf("Compared data: %d",dataint2);
end if;
end if;
elsif format = 1 then
read(L1,datahex1);
read(L2,datahex2);
if conv_std_logic_vector(datahex1,32) /= conv_std_logic_vector(datahex2,32) then
errs := errs+1;
if printlvl /= 0 then
printf("Comparision error at pos. %d",pos);
printf("Expected data: %x",datahex1);
printf("Compared data: %x",datahex2);
end if;
end if;
end if;
while not (endfile(comp1) or endfile(comp2)) loop
readline(comp1,L1);
readline(comp2,L2);
pos := pos+1;
if format = 0 then
read(L1,dataint1);
read(L2,dataint2);
if dataint1 /= dataint2 then
errs := errs+1;
if printlvl /= 0 then
printf("Comparision error at pos. %d",pos);
printf("Expected data: %d",dataint1);
printf("Compared data: %d",dataint2);
end if;
end if;
elsif format = 1 then
read(L1,datahex1);
read(L2,datahex2);
if conv_std_logic_vector(datahex1,32) /= conv_std_logic_vector(datahex2,32) then
errs := errs+1;
if printlvl /= 0 then
printf("Comparision error at pos. %d",pos);
printf("Expected data: %x",datahex1);
printf("Compared data: %x",datahex2);
end if;
end if;
end if;
end loop;
if endfile(comp1) /= endfile(comp2) then
if printlvl /= 0 then
printf("Compared files have different size!"); errs := errs+1;
end if;
end if;
file_close(comp1); file_close(comp2);
err := true;
if errs = 0 then
err := false;
if printlvl >= 2 then
printf("Comparision complete. No failure.");
end if;
elsif errs = 1 then
if printlvl >= 1 then
printf("Comparision complete. 1 failure.");
end if;
else
if printlvl >= 1 then
printf("Comparision complete. %d failures.",errs);
end if;
end if;
end procedure;
end ambatest;
-- pragma translate_on
|
mit
|
impedimentToProgress/UCI-BlueChip
|
AttackFiles/Attacks/memAttack/lib/techmap/gencomp/netcomp.vhd
|
2
|
31710
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: netcomp
-- File: netcomp.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Delcation of netlists componnets
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use work.gencomp.all;
package netcomp is
---------------------------------------------------------------------------
-- netlists ---------------------------------------------------------------
---------------------------------------------------------------------------
component usbhc_net is
generic (
tech : integer := 0;
nports : integer range 1 to 15 := 1;
ehcgen : integer range 0 to 1 := 1;
uhcgen : integer range 0 to 1 := 1;
n_cc : integer range 1 to 15 := 1;
n_pcc : integer range 1 to 15 := 1;
prr : integer range 0 to 1 := 0;
portroute1 : integer := 0;
portroute2 : integer := 0;
endian_conv : integer range 0 to 1 := 1;
be_regs : integer range 0 to 1 := 0;
be_desc : integer range 0 to 1 := 0;
uhcblo : integer range 0 to 255 := 2;
bwrd : integer range 1 to 256 := 16;
utm_type : integer range 0 to 2 := 2;
vbusconf : integer range 0 to 3 := 3;
ramtest : integer range 0 to 1 := 0;
urst_time : integer := 250;
oepol : integer range 0 to 1 := 0
);
port (
clk : in std_ulogic;
uclk : in std_ulogic;
rst : in std_ulogic;
ursti : in std_ulogic;
-- EHC apb_slv_in_type unwrapped
ehc_apbsi_psel : in std_ulogic;
ehc_apbsi_penable : in std_ulogic;
ehc_apbsi_paddr : in std_logic_vector(31 downto 0);
ehc_apbsi_pwrite : in std_ulogic;
ehc_apbsi_pwdata : in std_logic_vector(31 downto 0);
ehc_apbsi_testen : in std_ulogic;
ehc_apbsi_testrst : in std_ulogic;
ehc_apbsi_scanen : in std_ulogic;
-- EHC apb_slv_out_type unwrapped
ehc_apbso_prdata : out std_logic_vector(31 downto 0);
ehc_apbso_pirq : out std_ulogic;
-- EHC/UHC ahb_mst_in_type unwrapped
ahbmi_hgrant : in std_logic_vector(n_cc*uhcgen downto 0);
ahbmi_hready : in std_ulogic;
ahbmi_hresp : in std_logic_vector(1 downto 0);
ahbmi_hrdata : in std_logic_vector(31 downto 0);
ahbmi_hcache : in std_ulogic;
ahbmi_testen : in std_ulogic;
ahbmi_testrst : in std_ulogic;
ahbmi_scanen : in std_ulogic;
-- UHC ahb_slv_in_type unwrapped
uhc_ahbsi_hsel : in std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbsi_haddr : in std_logic_vector(31 downto 0);
uhc_ahbsi_hwrite : in std_ulogic;
uhc_ahbsi_htrans : in std_logic_vector(1 downto 0);
uhc_ahbsi_hsize : in std_logic_vector(2 downto 0);
uhc_ahbsi_hwdata : in std_logic_vector(31 downto 0);
uhc_ahbsi_hready : in std_ulogic;
uhc_ahbsi_testen : in std_ulogic;
uhc_ahbsi_testrst : in std_ulogic;
uhc_ahbsi_scanen : in std_ulogic;
-- EHC ahb_mst_out_type_unwrapped
ehc_ahbmo_hbusreq : out std_ulogic;
ehc_ahbmo_hlock : out std_ulogic;
ehc_ahbmo_htrans : out std_logic_vector(1 downto 0);
ehc_ahbmo_haddr : out std_logic_vector(31 downto 0);
ehc_ahbmo_hwrite : out std_ulogic;
ehc_ahbmo_hsize : out std_logic_vector(2 downto 0);
ehc_ahbmo_hburst : out std_logic_vector(2 downto 0);
ehc_ahbmo_hprot : out std_logic_vector(3 downto 0);
ehc_ahbmo_hwdata : out std_logic_vector(31 downto 0);
-- UHC ahb_mst_out_vector_type unwrapped
uhc_ahbmo_hbusreq : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbmo_hlock : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbmo_htrans : out std_logic_vector((n_cc*2)*uhcgen downto 1*uhcgen);
uhc_ahbmo_haddr : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
uhc_ahbmo_hwrite : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbmo_hsize : out std_logic_vector((n_cc*3)*uhcgen downto 1*uhcgen);
uhc_ahbmo_hburst : out std_logic_vector((n_cc*3)*uhcgen downto 1*uhcgen);
uhc_ahbmo_hprot : out std_logic_vector((n_cc*4)*uhcgen downto 1*uhcgen);
uhc_ahbmo_hwdata : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
-- UHC ahb_slv_out_vector_type unwrapped
uhc_ahbso_hready : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbso_hresp : out std_logic_vector((n_cc*2)*uhcgen downto 1*uhcgen);
uhc_ahbso_hrdata : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
uhc_ahbso_hsplit : out std_logic_vector((n_cc*16)*uhcgen downto 1*uhcgen);
uhc_ahbso_hcache : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbso_hirq : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
-- usbhc_out_type_vector unwrapped
xcvrsel : out std_logic_vector(((nports*2)-1) downto 0);
termsel : out std_logic_vector((nports-1) downto 0);
suspendm : out std_logic_vector((nports-1) downto 0);
opmode : out std_logic_vector(((nports*2)-1) downto 0);
txvalid : out std_logic_vector((nports-1) downto 0);
drvvbus : out std_logic_vector((nports-1) downto 0);
dataho : out std_logic_vector(((nports*8)-1) downto 0);
validho : out std_logic_vector((nports-1) downto 0);
host : out std_logic_vector((nports-1) downto 0);
stp : out std_logic_vector((nports-1) downto 0);
datao : out std_logic_vector(((nports*8)-1) downto 0);
utm_rst : out std_logic_vector((nports-1) downto 0);
dctrlo : out std_logic_vector((nports-1) downto 0);
-- usbhc_in_type_vector unwrapped
linestate : in std_logic_vector(((nports*2)-1) downto 0);
txready : in std_logic_vector((nports-1) downto 0);
rxvalid : in std_logic_vector((nports-1) downto 0);
rxactive : in std_logic_vector((nports-1) downto 0);
rxerror : in std_logic_vector((nports-1) downto 0);
vbusvalid : in std_logic_vector((nports-1) downto 0);
datahi : in std_logic_vector(((nports*8)-1) downto 0);
validhi : in std_logic_vector((nports-1) downto 0);
hostdisc : in std_logic_vector((nports-1) downto 0);
nxt : in std_logic_vector((nports-1) downto 0);
dir : in std_logic_vector((nports-1) downto 0);
datai : in std_logic_vector(((nports*8)-1) downto 0);
-- EHC transaction buffer signals
mbc20_tb_addr : out std_logic_vector(8 downto 0);
mbc20_tb_data : out std_logic_vector(31 downto 0);
mbc20_tb_en : out std_ulogic;
mbc20_tb_wel : out std_ulogic;
mbc20_tb_weh : out std_ulogic;
tb_mbc20_data : in std_logic_vector(31 downto 0);
pe20_tb_addr : out std_logic_vector(8 downto 0);
pe20_tb_data : out std_logic_vector(31 downto 0);
pe20_tb_en : out std_ulogic;
pe20_tb_wel : out std_ulogic;
pe20_tb_weh : out std_ulogic;
tb_pe20_data : in std_logic_vector(31 downto 0);
-- EHC packet buffer signals
mbc20_pb_addr : out std_logic_vector(8 downto 0);
mbc20_pb_data : out std_logic_vector(31 downto 0);
mbc20_pb_en : out std_ulogic;
mbc20_pb_we : out std_ulogic;
pb_mbc20_data : in std_logic_vector(31 downto 0);
sie20_pb_addr : out std_logic_vector(8 downto 0);
sie20_pb_data : out std_logic_vector(31 downto 0);
sie20_pb_en : out std_ulogic;
sie20_pb_we : out std_ulogic;
pb_sie20_data : in std_logic_vector(31 downto 0);
-- UHC packet buffer signals
sie11_pb_addr : out std_logic_vector((n_cc*9)*uhcgen downto 1*uhcgen);
sie11_pb_data : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
sie11_pb_en : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
sie11_pb_we : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
pb_sie11_data : in std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
mbc11_pb_addr : out std_logic_vector((n_cc*9)*uhcgen downto 1*uhcgen);
mbc11_pb_data : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
mbc11_pb_en : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
mbc11_pb_we : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
pb_mbc11_data : in std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
bufsel : out std_ulogic);
end component;
component grspwc_net
generic(
tech : integer := 0;
sysfreq : integer := 40000;
usegen : integer range 0 to 1 := 1;
nsync : integer range 1 to 2 := 1;
rmap : integer range 0 to 1 := 0;
rmapcrc : integer range 0 to 1 := 0;
fifosize1 : integer range 4 to 32 := 32;
fifosize2 : integer range 16 to 64 := 64;
rxunaligned : integer range 0 to 1 := 0;
rmapbufs : integer range 2 to 8 := 4;
scantest : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
txclk : in std_ulogic;
--ahb mst in
hgrant : in std_ulogic;
hready : in std_ulogic;
hresp : in std_logic_vector(1 downto 0);
hrdata : in std_logic_vector(31 downto 0);
--ahb mst out
hbusreq : out std_ulogic;
hlock : out std_ulogic;
htrans : out std_logic_vector(1 downto 0);
haddr : out std_logic_vector(31 downto 0);
hwrite : out std_ulogic;
hsize : out std_logic_vector(2 downto 0);
hburst : out std_logic_vector(2 downto 0);
hprot : out std_logic_vector(3 downto 0);
hwdata : out std_logic_vector(31 downto 0);
--apb slv in
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
--apb slv out
prdata : out std_logic_vector(31 downto 0);
--spw in
di : in std_logic_vector(1 downto 0);
si : in std_logic_vector(1 downto 0);
--spw out
do : out std_logic_vector(1 downto 0);
so : out std_logic_vector(1 downto 0);
--time iface
tickin : in std_ulogic;
tickout : out std_ulogic;
--irq
irq : out std_logic;
--misc
clkdiv10 : in std_logic_vector(7 downto 0);
dcrstval : in std_logic_vector(9 downto 0);
timerrstval : in std_logic_vector(11 downto 0);
--rmapen
rmapen : in std_ulogic;
--clk bufs
rxclki : in std_logic_vector(1 downto 0);
nrxclki : in std_logic_vector(1 downto 0);
rxclko : out std_logic_vector(1 downto 0);
--rx ahb fifo
rxrenable : out std_ulogic;
rxraddress : out std_logic_vector(4 downto 0);
rxwrite : out std_ulogic;
rxwdata : out std_logic_vector(31 downto 0);
rxwaddress : out std_logic_vector(4 downto 0);
rxrdata : in std_logic_vector(31 downto 0);
--tx ahb fifo
txrenable : out std_ulogic;
txraddress : out std_logic_vector(4 downto 0);
txwrite : out std_ulogic;
txwdata : out std_logic_vector(31 downto 0);
txwaddress : out std_logic_vector(4 downto 0);
txrdata : in std_logic_vector(31 downto 0);
--nchar fifo
ncrenable : out std_ulogic;
ncraddress : out std_logic_vector(5 downto 0);
ncwrite : out std_ulogic;
ncwdata : out std_logic_vector(8 downto 0);
ncwaddress : out std_logic_vector(5 downto 0);
ncrdata : in std_logic_vector(8 downto 0);
--rmap buf
rmrenable : out std_ulogic;
rmraddress : out std_logic_vector(7 downto 0);
rmwrite : out std_ulogic;
rmwdata : out std_logic_vector(7 downto 0);
rmwaddress : out std_logic_vector(7 downto 0);
rmrdata : in std_logic_vector(7 downto 0);
linkdis : out std_ulogic;
testclk : in std_ulogic := '0';
testrst : in std_ulogic := '0';
testen : in std_ulogic := '0'
);
end component;
component grlfpw_net
generic (tech : integer := 0;
pclow : integer range 0 to 2 := 2;
dsu : integer range 0 to 1 := 1;
disas : integer range 0 to 2 := 0;
pipe : integer range 0 to 2 := 0
);
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi_flush : in std_ulogic; -- pipeline flush
cpi_exack : in std_ulogic; -- FP exception acknowledge
cpi_a_rs1 : in std_logic_vector(4 downto 0);
cpi_d_pc : in std_logic_vector(31 downto 0);
cpi_d_inst : in std_logic_vector(31 downto 0);
cpi_d_cnt : in std_logic_vector(1 downto 0);
cpi_d_trap : in std_ulogic;
cpi_d_annul : in std_ulogic;
cpi_d_pv : in std_ulogic;
cpi_a_pc : in std_logic_vector(31 downto 0);
cpi_a_inst : in std_logic_vector(31 downto 0);
cpi_a_cnt : in std_logic_vector(1 downto 0);
cpi_a_trap : in std_ulogic;
cpi_a_annul : in std_ulogic;
cpi_a_pv : in std_ulogic;
cpi_e_pc : in std_logic_vector(31 downto 0);
cpi_e_inst : in std_logic_vector(31 downto 0);
cpi_e_cnt : in std_logic_vector(1 downto 0);
cpi_e_trap : in std_ulogic;
cpi_e_annul : in std_ulogic;
cpi_e_pv : in std_ulogic;
cpi_m_pc : in std_logic_vector(31 downto 0);
cpi_m_inst : in std_logic_vector(31 downto 0);
cpi_m_cnt : in std_logic_vector(1 downto 0);
cpi_m_trap : in std_ulogic;
cpi_m_annul : in std_ulogic;
cpi_m_pv : in std_ulogic;
cpi_x_pc : in std_logic_vector(31 downto 0);
cpi_x_inst : in std_logic_vector(31 downto 0);
cpi_x_cnt : in std_logic_vector(1 downto 0);
cpi_x_trap : in std_ulogic;
cpi_x_annul : in std_ulogic;
cpi_x_pv : in std_ulogic;
cpi_lddata : in std_logic_vector(31 downto 0); -- load data
cpi_dbg_enable : in std_ulogic;
cpi_dbg_write : in std_ulogic;
cpi_dbg_fsr : in std_ulogic; -- FSR access
cpi_dbg_addr : in std_logic_vector(4 downto 0);
cpi_dbg_data : in std_logic_vector(31 downto 0);
cpo_data : out std_logic_vector(31 downto 0); -- store data
cpo_exc : out std_logic; -- FP exception
cpo_cc : out std_logic_vector(1 downto 0); -- FP condition codes
cpo_ccv : out std_ulogic; -- FP condition codes valid
cpo_ldlock : out std_logic; -- FP pipeline hold
cpo_holdn : out std_ulogic;
cpo_dbg_data : out std_logic_vector(31 downto 0);
rfi1_rd1addr : out std_logic_vector(3 downto 0);
rfi1_rd2addr : out std_logic_vector(3 downto 0);
rfi1_wraddr : out std_logic_vector(3 downto 0);
rfi1_wrdata : out std_logic_vector(31 downto 0);
rfi1_ren1 : out std_ulogic;
rfi1_ren2 : out std_ulogic;
rfi1_wren : out std_ulogic;
rfi2_rd1addr : out std_logic_vector(3 downto 0);
rfi2_rd2addr : out std_logic_vector(3 downto 0);
rfi2_wraddr : out std_logic_vector(3 downto 0);
rfi2_wrdata : out std_logic_vector(31 downto 0);
rfi2_ren1 : out std_ulogic;
rfi2_ren2 : out std_ulogic;
rfi2_wren : out std_ulogic;
rfo1_data1 : in std_logic_vector(31 downto 0);
rfo1_data2 : in std_logic_vector(31 downto 0);
rfo2_data1 : in std_logic_vector(31 downto 0);
rfo2_data2 : in std_logic_vector(31 downto 0)
);
end component;
component grfpw_net
generic (tech : integer := 0;
pclow : integer range 0 to 2 := 2;
dsu : integer range 0 to 2 := 1;
disas : integer range 0 to 2 := 0;
pipe : integer range 0 to 2 := 0
);
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi_flush : in std_ulogic; -- pipeline flush
cpi_exack : in std_ulogic; -- FP exception acknowledge
cpi_a_rs1 : in std_logic_vector(4 downto 0);
cpi_d_pc : in std_logic_vector(31 downto 0);
cpi_d_inst : in std_logic_vector(31 downto 0);
cpi_d_cnt : in std_logic_vector(1 downto 0);
cpi_d_trap : in std_ulogic;
cpi_d_annul : in std_ulogic;
cpi_d_pv : in std_ulogic;
cpi_a_pc : in std_logic_vector(31 downto 0);
cpi_a_inst : in std_logic_vector(31 downto 0);
cpi_a_cnt : in std_logic_vector(1 downto 0);
cpi_a_trap : in std_ulogic;
cpi_a_annul : in std_ulogic;
cpi_a_pv : in std_ulogic;
cpi_e_pc : in std_logic_vector(31 downto 0);
cpi_e_inst : in std_logic_vector(31 downto 0);
cpi_e_cnt : in std_logic_vector(1 downto 0);
cpi_e_trap : in std_ulogic;
cpi_e_annul : in std_ulogic;
cpi_e_pv : in std_ulogic;
cpi_m_pc : in std_logic_vector(31 downto 0);
cpi_m_inst : in std_logic_vector(31 downto 0);
cpi_m_cnt : in std_logic_vector(1 downto 0);
cpi_m_trap : in std_ulogic;
cpi_m_annul : in std_ulogic;
cpi_m_pv : in std_ulogic;
cpi_x_pc : in std_logic_vector(31 downto 0);
cpi_x_inst : in std_logic_vector(31 downto 0);
cpi_x_cnt : in std_logic_vector(1 downto 0);
cpi_x_trap : in std_ulogic;
cpi_x_annul : in std_ulogic;
cpi_x_pv : in std_ulogic;
cpi_lddata : in std_logic_vector(31 downto 0); -- load data
cpi_dbg_enable : in std_ulogic;
cpi_dbg_write : in std_ulogic;
cpi_dbg_fsr : in std_ulogic; -- FSR access
cpi_dbg_addr : in std_logic_vector(4 downto 0);
cpi_dbg_data : in std_logic_vector(31 downto 0);
cpo_data : out std_logic_vector(31 downto 0); -- store data
cpo_exc : out std_logic; -- FP exception
cpo_cc : out std_logic_vector(1 downto 0); -- FP condition codes
cpo_ccv : out std_ulogic; -- FP condition codes valid
cpo_ldlock : out std_logic; -- FP pipeline hold
cpo_holdn : out std_ulogic;
cpo_dbg_data : out std_logic_vector(31 downto 0);
rfi1_rd1addr : out std_logic_vector(3 downto 0);
rfi1_rd2addr : out std_logic_vector(3 downto 0);
rfi1_wraddr : out std_logic_vector(3 downto 0);
rfi1_wrdata : out std_logic_vector(31 downto 0);
rfi1_ren1 : out std_ulogic;
rfi1_ren2 : out std_ulogic;
rfi1_wren : out std_ulogic;
rfi2_rd1addr : out std_logic_vector(3 downto 0);
rfi2_rd2addr : out std_logic_vector(3 downto 0);
rfi2_wraddr : out std_logic_vector(3 downto 0);
rfi2_wrdata : out std_logic_vector(31 downto 0);
rfi2_ren1 : out std_ulogic;
rfi2_ren2 : out std_ulogic;
rfi2_wren : out std_ulogic;
rfo1_data1 : in std_logic_vector(31 downto 0);
rfo1_data2 : in std_logic_vector(31 downto 0);
rfo2_data1 : in std_logic_vector(31 downto 0);
rfo2_data2 : in std_logic_vector(31 downto 0)
);
end component;
component leon3ft_net
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 31 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 2 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 2 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0; -- support SMP systems
iuft : integer range 0 to 4 := 0;
fpft : integer range 0 to 4 := 0;
cmft : integer range 0 to 1 := 0;
cached : integer := 0;
scantest : integer := 0
);
port (
clk : in std_ulogic;
gclk : in std_ulogic;
rstn : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi_irl: in std_logic_vector(3 downto 0);
irqi_rst: in std_ulogic;
irqi_run: in std_ulogic;
irqo_intack: out std_ulogic;
irqo_irl: out std_logic_vector(3 downto 0);
irqo_pwd: out std_ulogic;
dbgi_dsuen: in std_ulogic; -- DSU enable
dbgi_denable: in std_ulogic; -- diagnostic register access enable
dbgi_dbreak: in std_ulogic; -- debug break-in
dbgi_step: in std_ulogic; -- single step
dbgi_halt: in std_ulogic; -- halt processor
dbgi_reset: in std_ulogic; -- reset processor
dbgi_dwrite: in std_ulogic; -- read/write
dbgi_daddr: in std_logic_vector(23 downto 2); -- diagnostic address
dbgi_ddata: in std_logic_vector(31 downto 0); -- diagnostic data
dbgi_btrapa: in std_ulogic; -- break on IU trap
dbgi_btrape: in std_ulogic; -- break on IU trap
dbgi_berror: in std_ulogic; -- break on IU error mode
dbgi_bwatch: in std_ulogic; -- break on IU watchpoint
dbgi_bsoft: in std_ulogic; -- break on software breakpoint (TA 1)
dbgi_tenable: in std_ulogic;
dbgi_timer: in std_logic_vector(30 downto 0);
dbgo_data: out std_logic_vector(31 downto 0);
dbgo_crdy: out std_ulogic;
dbgo_dsu: out std_ulogic;
dbgo_dsumode: out std_ulogic;
dbgo_error: out std_ulogic;
dbgo_halt: out std_ulogic;
dbgo_pwd: out std_ulogic;
dbgo_idle: out std_ulogic;
dbgo_ipend: out std_ulogic;
dbgo_icnt: out std_ulogic
);
end component;
component ftmctrl_net
generic (
hindex : integer := 0;
pindex : integer := 0;
romaddr : integer := 16#000#;
rommask : integer := 16#E00#;
ioaddr : integer := 16#200#;
iomask : integer := 16#E00#;
ramaddr : integer := 16#400#;
rammask : integer := 16#C00#;
paddr : integer := 0;
pmask : integer := 16#fff#;
wprot : integer := 0;
invclk : integer := 0;
fast : integer := 0;
romasel : integer := 28;
sdrasel : integer := 29;
srbanks : integer := 4;
ram8 : integer := 0;
ram16 : integer := 0;
sden : integer := 0;
sepbus : integer := 0;
sdbits : integer := 32;
sdlsb : integer := 2; -- set to 12 for the GE-HPE board
oepol : integer := 0;
edac : integer := 0;
syncrst : integer := 0;
pageburst : integer := 0;
scantest : integer := 0;
writefb : integer := 0;
tech : integer := 0
);
port (
rst: in Std_ULogic;
clk: in Std_ULogic;
ahbsi: in ahb_slv_in_type;
ahbso: out ahb_slv_out_type;
apbi: in apb_slv_in_type;
apbo: out apb_slv_out_type;
memi_data: in Std_Logic_Vector(31 downto 0);
memi_brdyn: in Std_Logic;
memi_bexcn: in Std_Logic;
memi_writen: in Std_Logic;
memi_wrn: in Std_Logic_Vector(3 downto 0);
memi_bwidth: in Std_Logic_Vector(1 downto 0);
memi_sd: in Std_Logic_Vector(63 downto 0);
memi_cb: in Std_Logic_Vector(7 downto 0);
memi_scb: in Std_Logic_Vector(7 downto 0);
memi_edac: in Std_Logic;
memo_address: out Std_Logic_Vector(31 downto 0);
memo_data: out Std_Logic_Vector(31 downto 0);
memo_sddata: out Std_Logic_Vector(63 downto 0);
memo_ramsn: out Std_Logic_Vector(7 downto 0);
memo_ramoen: out Std_Logic_Vector(7 downto 0);
memo_ramn: out Std_ULogic;
memo_romn: out Std_ULogic;
memo_mben: out Std_Logic_Vector(3 downto 0);
memo_iosn: out Std_Logic;
memo_romsn: out Std_Logic_Vector(7 downto 0);
memo_oen: out Std_Logic;
memo_writen: out Std_Logic;
memo_wrn: out Std_Logic_Vector(3 downto 0);
memo_bdrive: out Std_Logic_Vector(3 downto 0);
memo_vbdrive: out Std_Logic_Vector(31 downto 0);
memo_svbdrive: out Std_Logic_Vector(63 downto 0);
memo_read: out Std_Logic;
memo_sa: out Std_Logic_Vector(14 downto 0);
memo_cb: out Std_Logic_Vector(7 downto 0);
memo_scb: out Std_Logic_Vector(7 downto 0);
memo_vcdrive: out Std_Logic_Vector(7 downto 0);
memo_svcdrive: out Std_Logic_Vector(7 downto 0);
memo_ce: out Std_ULogic;
sdo_sdcke: out Std_Logic_Vector( 1 downto 0);
sdo_sdcsn: out Std_Logic_Vector( 1 downto 0);
sdo_sdwen: out Std_ULogic;
sdo_rasn: out Std_ULogic;
sdo_casn: out Std_ULogic;
sdo_dqm: out Std_Logic_Vector( 7 downto 0);
wpo_wprothit: in Std_ULogic);
end component;
component ssrctrl_net
generic (
tech: Integer := 0;
bus16: Integer := 1);
port (
rst: in Std_Logic;
clk: in Std_Logic;
n_ahbsi_hsel: in Std_Logic_Vector(0 to 15);
n_ahbsi_haddr: in Std_Logic_Vector(31 downto 0);
n_ahbsi_hwrite: in Std_Logic;
n_ahbsi_htrans: in Std_Logic_Vector(1 downto 0);
n_ahbsi_hsize: in Std_Logic_Vector(2 downto 0);
n_ahbsi_hburst: in Std_Logic_Vector(2 downto 0);
n_ahbsi_hwdata: in Std_Logic_Vector(31 downto 0);
n_ahbsi_hprot: in Std_Logic_Vector(3 downto 0);
n_ahbsi_hready: in Std_Logic;
n_ahbsi_hmaster: in Std_Logic_Vector(3 downto 0);
n_ahbsi_hmastlock:in Std_Logic;
n_ahbsi_hmbsel: in Std_Logic_Vector(0 to 3);
n_ahbsi_hcache: in Std_Logic;
n_ahbsi_hirq: in Std_Logic_Vector(31 downto 0);
n_ahbso_hready: out Std_Logic;
n_ahbso_hresp: out Std_Logic_Vector(1 downto 0);
n_ahbso_hrdata: out Std_Logic_Vector(31 downto 0);
n_ahbso_hsplit: out Std_Logic_Vector(15 downto 0);
n_ahbso_hcache: out Std_Logic;
n_ahbso_hirq: out Std_Logic_Vector(31 downto 0);
n_apbi_psel: in Std_Logic_Vector(0 to 15);
n_apbi_penable: in Std_Logic;
n_apbi_paddr: in Std_Logic_Vector(31 downto 0);
n_apbi_pwrite: in Std_Logic;
n_apbi_pwdata: in Std_Logic_Vector(31 downto 0);
n_apbi_pirq: in Std_Logic_Vector(31 downto 0);
n_apbo_prdata: out Std_Logic_Vector(31 downto 0);
n_apbo_pirq: out Std_Logic_Vector(31 downto 0);
n_sri_data: in Std_Logic_Vector(31 downto 0);
n_sri_brdyn: in Std_Logic;
n_sri_bexcn: in Std_Logic;
n_sri_writen: in Std_Logic;
n_sri_wrn: in Std_Logic_Vector(3 downto 0);
n_sri_bwidth: in Std_Logic_Vector(1 downto 0);
n_sri_sd: in Std_Logic_Vector(63 downto 0);
n_sri_cb: in Std_Logic_Vector(7 downto 0);
n_sri_scb: in Std_Logic_Vector(7 downto 0);
n_sri_edac: in Std_Logic;
n_sro_address: out Std_Logic_Vector(31 downto 0);
n_sro_data: out Std_Logic_Vector(31 downto 0);
n_sro_sddata: out Std_Logic_Vector(63 downto 0);
n_sro_ramsn: out Std_Logic_Vector(7 downto 0);
n_sro_ramoen: out Std_Logic_Vector(7 downto 0);
n_sro_ramn: out Std_Logic;
n_sro_romn: out Std_Logic;
n_sro_mben: out Std_Logic_Vector(3 downto 0);
n_sro_iosn: out Std_Logic;
n_sro_romsn: out Std_Logic_Vector(7 downto 0);
n_sro_oen: out Std_Logic;
n_sro_writen: out Std_Logic;
n_sro_wrn: out Std_Logic_Vector(3 downto 0);
n_sro_bdrive: out Std_Logic_Vector(3 downto 0);
n_sro_vbdrive: out Std_Logic_Vector(31 downto 0);
n_sro_svbdrive: out Std_Logic_Vector(63 downto 0);
n_sro_read: out Std_Logic;
n_sro_sa: out Std_Logic_Vector(14 downto 0);
n_sro_cb: out Std_Logic_Vector(7 downto 0);
n_sro_scb: out Std_Logic_Vector(7 downto 0);
n_sro_vcdrive: out Std_Logic_Vector(7 downto 0);
n_sro_svcdrive: out Std_Logic_Vector(7 downto 0);
n_sro_ce: out Std_Logic);
end component;
end;
|
mit
|
impedimentToProgress/UCI-BlueChip
|
AttackFiles/Attacks/memAttack/lib/gleichmann/multiio/MultiIO_APB.vhd
|
2
|
25345
|
--------------------------------------------------------------------
-- Entity: MultiIO_APB
-- File: MultiIO_APB.vhd
-- Author: Thomas Ameseder, Gleichmann Electronics
-- Based on an orginal version by [email protected]
--
-- Description: APB Multiple digital I/O for minimal User Interface
--------------------------------------------------------------------
-- Functionality:
-- 8 LEDs, active low or high, r/w
-- dual 7Segment, active low or high, w only
-- 8 DIL Switches, active low or high, r only
-- 8 Buttons, active low or high, r only, with IRQ enables
--------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gleichmann;
use gleichmann.spi.all;
use gleichmann.i2c.all;
use gleichmann.miscellaneous.all;
use gleichmann.multiio.all;
-- pragma translate_off
use std.textio.all;
-- pragma translate_on
entity MultiIO_APB is
generic (
hpe_version: integer := 0; -- adapt multiplexing for different boards
pindex : integer := 0; -- Leon-Index
paddr : integer := 0; -- Leon-Address
pmask : integer := 16#FFF#; -- Leon-Mask
pirq : integer := 0; -- Leon-IRQ
clk_freq_in : integer := 25_000_000; -- Leons clock to calculate timings
led7act : std_logic := '0'; -- active level for 7Segment
ledact : std_logic := '0'; -- active level for LEDs
switchact : std_logic := '1'; -- active level for LED's
buttonact : std_logic := '1'; -- active level for LED's
n_switches : integer := 8; -- number of switches that are driven
n_leds : integer := 8 -- number of LEDs that are driven
);
port (
rst_n : in std_ulogic; -- global Reset, active low
clk : in std_ulogic; -- global Clock
apbi : in apb_slv_in_type; -- APB-Input
apbo : out apb_slv_out_type; -- APB-Output
MultiIO_in : in MultiIO_in_type; -- MultIO-Inputs
MultiIO_out : out MultiIO_out_type -- MultiIO-Outputs
);
end entity;
architecture Implementation of MultiIO_APB is ----------------------
constant VERSION : std_logic_vector(31 downto 0) := x"EA_07_12_06";
constant REVISION : integer := 1;
constant MUXMAX : integer := 7;
constant VCC : std_logic_vector(31 downto 0) := (others => '1');
constant GND : std_logic_vector(31 downto 0) := (others => '0');
signal Enable1ms : boolean;
signal MUXCounter : integer range 0 to MUXMAX-1;
signal clkgen_mclk : std_ulogic;
signal clkgen_bclk : std_ulogic;
signal clkgen_sclk : std_ulogic;
signal clkgen_lrclk : std_ulogic;
type state_t is (WAIT_FOR_SYNC,READY,WAIT_FOR_ACK);
signal state,next_state : state_t;
signal Strobe,next_Strobe : std_ulogic;
-- status signals of the i2s core for upper-level state machine
signal SampleAck, WaitForSample : std_ulogic;
signal samplereg : std_ulogic_vector(N_CODECI2SBITS-1 downto 0);
constant pconfig : apb_config_type := (
0 => ahb_device_reg (VENDOR_GLEICHMANN, GLEICHMANN_HIFC, 0, REVISION, pirq),
1 => apb_iobar(paddr, pmask)
);
type MultiIOregisters is
record
ledreg : std_logic_vector(31 downto 0); -- LEDs
led7reg : std_logic_vector(31 downto 0); -- Dual 7Segment LEDs
codecreg : std_logic_vector(31 downto 0);
codecreg2 : std_logic_vector(31 downto 0);
-- Switches in
sw_inreg : std_logic_vector(31 downto 0);
-- ASCII value of input button
btn_inreg : std_logic_vector(31 downto 0);
irqenareg : std_logic_vector(31 downto 0); -- IRQ enables for Buttons
btn_irqs : std_logic_vector(31 downto 0); -- IRQs from each Button
new_data : std_ulogic;
-- new_data_valid : std_ulogic;
lcdreg : std_logic_vector(31 downto 0); -- LCD instruction
--cb1_in_reg : std_logic_vector(31 downto 0);
--cb1_out_reg : std_logic_vector(31 downto 0);
-- cb3_in_reg : std_logic_vector(31 downto 0);
--cb4_in2_reg : std_logic_vector(31 downto 0);
-- cb3_out_reg : std_logic_vector(31 downto 0);
--cb4_out2_reg : std_logic_vector(31 downto 0);
exp_in_reg : std_logic_vector(31 downto 0);
exp_out_reg : std_logic_vector(31 downto 0);
hsc_out_reg : std_logic_vector(31 downto 0);
hsc_in_reg : std_logic_vector(31 downto 0);
end record;
signal r, rin : MultiIOregisters; -- register sets
signal Key : std_logic_vector(7 downto 0); -- ASCII value of button
-- character representation of the key (for simulation purposes)
signal KeyVal : character;
signal OldColumnRow1 : std_logic_vector(6 downto 0); -- for key debounce
signal OldColumnRow2 : std_logic_vector(6 downto 0); -- for key debounce
begin
reg_rw : process(MUXCounter, MultiIO_in, apbi, key, r, rst_n)
variable readdata : std_logic_vector(31 downto 0); -- system bus width
variable irqs : std_logic_vector(31 downto 0); -- system IRQs width
variable v : MultiIOregisters; -- register set
begin
v := r;
-- reset registers
if rst_n = '0' then
-- lower half of LEDs on
v.ledreg := (others => '0');
v.ledreg(3 downto 0) := "1111";
v.led7reg := (others => '0');
v.led7reg(15 downto 0) := X"38_4F"; -- show "L3" Leon3 on 7Segments
v.codecreg := (others => '0');
v.codecreg2 := (others => '0');
v.irqenareg := (others => '0'); -- IRQs disable
v.btn_inreg := (others => '0');
v.sw_inreg := (others => '0');
-- new data flag off
v.new_data := '0';
-- v.new_data_valid := '0';
v.lcdreg := (others => '0');
-- v.cb3_in_reg := (others => '0');
--v.cb4_in2_reg := (others => '0');
-- v.cb3_out_reg := (others => '0');
--v.cb4_out2_reg := (others => '0');
v.exp_in_reg := (others => '0');
v.exp_out_reg := (others => '0');
v.hsc_in_reg := (others => '0');
v.hsc_out_reg := (others => '0');
end if;
-- get switches and buttons
if switchact = '1' then
v.sw_inreg(N_SWITCHES-1 downto 0) := MultiIO_in.switch_in;
else
v.sw_inreg(N_SWITCHES-1 downto 0) := not MultiIO_in.switch_in;
end if;
v.btn_inreg(7 downto 0) := key;
v.btn_irqs := (others => '0');
---------------------------------------------------------------------------
-- TO BE ALTERED
---------------------------------------------------------------------------
-- set local button-IRQs
for i in 0 to v.btn_irqs'left loop
-- detect low-to-high transition
if (v.btn_inreg(i) = '1') and (r.btn_inreg(i) = '0') then
-- set local IRQs if IRQ enabled
v.btn_irqs(i) := v.btn_inreg(i) and r.irqenareg(i);
else
-- clear local IRQs
v.btn_irqs(i) := '0';
end if;
end loop;
---------------------------------------------------------------------------
-- read registers
readdata := (others => 'X');
case conv_integer(apbi.paddr(6 downto 2)) is
when 0 => readdata := r.ledreg; -- LEDs
when 1 => readdata := r.led7reg; -- seven segment
when 2 => readdata := r.codecreg; -- codec command register
when 3 => readdata := r.codecreg2; -- codec i2s register
when 4 => readdata := r.sw_inreg; -- switches
when 5 => readdata := r.btn_inreg; -- buttons
when 6 => readdata := r.irqenareg; -- IRQ enables
when 7 => readdata := conv_std_logic_vector(pirq, 32); -- IRQ#
when 8 => readdata := version; -- version
when 9 => readdata := r.lcdreg; -- LCD data
when 10 => readdata := r.exp_out_reg; -- expansion connector out
when 11 => readdata := r.exp_in_reg; -- expansion connector in
when 12 => readdata := r.hsc_out_reg;
when 13 => readdata := r.hsc_in_reg;
--when 14 => readdata := r.cb4_out1_reg; -- childboard4 connector out
--when 15 => readdata := r.cb4_out2_reg; -- childboard4 connector out
-- when 14 => readdata := r.cb3_in_reg; -- childboard3 connector in
-- when 15 => readdata := r.cb3_out_reg; -- childboard3 connector out
--when 14 => readdata := r.cb1_out_reg; -- childboard1 connector out
--when 15 => readdata := r.cb1_in_reg; -- childboard1 connector in
when others => null;
end case;
-- write registers
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case conv_integer(apbi.paddr(6 downto 2)) is
when 0 => v.ledreg :=
GND(31 downto N_LEDS) &
apbi.pwdata(N_LEDS-1 downto 0); -- write LEDs
when 1 => v.led7reg :=
GND(31 downto N_SEVSEGBITS) &
apbi.pwdata(N_SEVSEGBITS-1 downto 0); -- write 7Segment
when 2 => v.codecreg :=
GND(31 downto N_CODECBITS) &
apbi.pwdata(N_CODECBITS-1 downto 0);
when 3 => v.codecreg2 :=
GND(31 downto N_CODECI2SBITS) &
apbi.pwdata(N_CODECI2SBITS-1 downto 0);
when 6 => v.irqenareg :=
GND(31 downto N_BUTTONS) &
apbi.pwdata(N_BUTTONS-1 downto 0);
when 9 => v.lcdreg :=
GND(31 downto N_LCDBITS) &
apbi.pwdata(N_LCDBITS-1 downto 0);
-- signal that new data has arrived
-- v.new_data_valid := '0';
v.new_data := '1';
when 10 => v.exp_out_reg :=
GND(31 downto N_EXPBITS/2) &
-- bit(N_EXPBITS) holds enable signal
apbi.pwdata(N_EXPBITS/2-1 downto 0);
when 12 => v.hsc_out_reg :=
GND(31 downto N_HSCBITS) &
apbi.pwdata(N_HSCBITS-1 downto 0);
--when 14 => v.cb4_out1_reg :=
-- apbi.pwdata(31 downto 0);
-- when 15 => v.cb3_out_reg :=
-- apbi.pwdata(31 downto 0);
--when 14 => v.exp_out_reg :=
-- GND(31 downto 13) &
-- -- bit(N_EXPBITS) holds enable signal
-- apbi.pwdata(12 downto 0);
when others => null;
end case;
end if;
-- set PIRQ
irqs := (others => '0');
for i in 0 to v.btn_irqs'left loop
-- set IRQ if button-i pressed and IRQ enabled
irqs(pirq) := irqs(pirq) or r.btn_irqs(i);
end loop;
if ledact = '1' then
MultiIO_out.led_out <= r.ledreg(N_LEDS-1 downto 0); -- not inverted
else
MultiIO_out.led_out <= not r.ledreg(N_LEDS-1 downto 0); -- inverted
end if;
-- disable seven segment and LC display by default
-- MultiIO_out.lcd_enable <= '0';
MultiIO_out.lcd_rw <= r.lcdreg(8);
MultiIO_out.lcd_regsel <= r.lcdreg(9);
-- reset new lcd data flag
-- will be enabled when new data are written to the LCD register
if MUXCounter = 4 then
v.new_data := '0';
-- v.serviced := '1';
end if;
-- register inputs from expansion connector
v.exp_in_reg(N_EXPBITS/2-1 downto 0) := MultiIO_in.exp_in;
MultiIO_out.exp_out <= r.exp_out_reg(N_EXPBITS/2-1 downto 0);
-- high-speed connector
v.hsc_in_reg(N_HSCBITS-1 downto 0) := MultiIO_in.hsc_in;
MultiIO_out.hsc_out <= r.hsc_out_reg(N_HSCBITS-1 downto 0);
-- configure control port of audio codec for SPI mode
MultiIO_out.codec_mode <= '1';
apbo.prdata <= readdata; -- output data to Leon
apbo.pirq <= irqs; -- output IRQs to Leon
apbo.pindex <= pindex; -- output index to Leon
rin <= v; -- update registers
end process;
apbo.pconfig <= pconfig; -- output config to Leon
regs : process(clk) -- update registers
begin
if rising_edge(clk) then
r <= rin;
end if;
end process;
KeyBoard : process(clk, rst_n)
variable ColumnStrobe : std_logic_vector(2 downto 0);
variable FirstTime : boolean;
variable NewColumnRow : std_logic_vector(6 downto 0);
begin
if rst_n = '0' then
MultiIO_out.column_out <= (others => '0'); -- all column off
Key <= X"40"; -- default '@' after Reset and no key pressed
OldColumnRow1 <= "1111111";
OldColumnRow2 <= "1110011";
ColumnStrobe := "001";
FirstTime := true;
elsif rising_edge(clk) then
if Enable1ms then
if MultiIO_in.row_in = "0000" then -- no key pressed
ColumnStrobe := ColumnStrobe(1) & ColumnStrobe(0) & ColumnStrobe(2); -- rotate column
MultiIO_out.column_out <= ColumnStrobe;
if not FirstTime then
Key <= X"3F"; -- no key pressed '?'
end if;
else -- key pressed
OldColumnRow2 <= OldColumnRow1;
-- check whether button inputs produce a high or a
-- low level, then assign these inputs in order that
-- they can be decoded into ASCII format
if buttonact = '1' then
NewColumnRow := ColumnStrobe & MultiIO_in.row_in;
else
NewColumnRow := ColumnStrobe & not MultiIO_in.row_in;
end if;
OldColumnRow1 <= NewColumnRow;
if (ColumnStrobe & MultiIO_in.row_in = OldColumnRow1) and
(OldColumnRow1 = OldColumnRow2)
then -- debounced
FirstTime := false; -- 1st valid key pressed
case OldColumnRow2 is -- decode keys into ascii characters
when "0010001" => Key <= x"31"; -- 1
when "0010010" => Key <= x"34"; -- 4
when "0010100" => Key <= x"37"; -- 7
when "0011000" => Key <= x"43"; -- C
when "0100001" => Key <= x"32"; -- 2
when "0100010" => Key <= x"35"; -- 5
when "0100100" => Key <= x"38"; -- 8
when "0101000" => Key <= x"30"; -- 0
when "1000001" => Key <= x"33"; -- 3
when "1000010" => Key <= x"36"; -- 6
when "1000100" => Key <= x"39"; -- 9
when "1001000" => Key <= x"45"; -- E
when others => Key <= x"39"; -- ? -- more than one key pressed
end case;
else
Key <= x"3D"; -- '=' -- bouncing
end if; -- debounce
end if; -- MultiIO_in.row_in
end if; -- Enable1ms
end if; -- rst_n
end process KeyBoard;
Multiplex3Sources : if hpe_version = midi generate
Multiplex : process(MUXCounter, r)
begin
-- disable LED output by default
MultiIO_out.led_enable <= '0' xnor ledact;
-- disable 7-segment display by default
MultiIO_out.led_ca_out <= "00" xnor (led7act & led7act);
-- set enable signal in the middle of LCD timeslots
if MUXCounter = 3 then
MultiIO_out.lcd_enable <= '1';
else
MultiIO_out.lcd_enable <= '0';
end if;
case MUXCounter is
when 0 | 1 =>
-- output logical value according to active level of the 7segment display
MultiIO_out.led_a_out <= r.led7reg(MUXCounter*8 + 0) xnor led7act;
MultiIO_out.led_b_out <= r.led7reg(MUXCounter*8 + 1) xnor led7act;
MultiIO_out.led_c_out <= r.led7reg(MUXCounter*8 + 2) xnor led7act;
MultiIO_out.led_d_out <= r.led7reg(MUXCounter*8 + 3) xnor led7act;
MultiIO_out.led_e_out <= r.led7reg(MUXCounter*8 + 4) xnor led7act;
MultiIO_out.led_f_out <= r.led7reg(MUXCounter*8 + 5) xnor led7act;
MultiIO_out.led_g_out <= r.led7reg(MUXCounter*8 + 6) xnor led7act;
MultiIO_out.led_dp_out <= r.led7reg(MUXCounter*8 + 7) xnor led7act;
-- selectively enable the current digit
for i in 0 to 1 loop
if i = MUXCounter then
MultiIO_out.led_ca_out(i) <= '1' xnor led7act;
else
MultiIO_out.led_ca_out(i) <= '0' xnor led7act;
end if;
end loop; -- i
when 2 | 3 | 4 =>
MultiIO_out.led_a_out <= r.lcdreg(0);
MultiIO_out.led_b_out <= r.lcdreg(1);
MultiIO_out.led_c_out <= r.lcdreg(2);
MultiIO_out.led_d_out <= r.lcdreg(3);
MultiIO_out.led_e_out <= r.lcdreg(4);
MultiIO_out.led_f_out <= r.lcdreg(5);
MultiIO_out.led_g_out <= r.lcdreg(6);
MultiIO_out.led_dp_out <= r.lcdreg(7);
when 5 | 6 =>
MultiIO_out.led_enable <= '1' xnor ledact;
MultiIO_out.led_a_out <= r.ledreg(0) xnor ledact;
MultiIO_out.led_b_out <= r.ledreg(1) xnor ledact;
MultiIO_out.led_c_out <= r.ledreg(2) xnor ledact;
MultiIO_out.led_d_out <= r.ledreg(3) xnor ledact;
MultiIO_out.led_e_out <= r.ledreg(4) xnor ledact;
MultiIO_out.led_f_out <= r.ledreg(5) xnor ledact;
MultiIO_out.led_g_out <= r.ledreg(6) xnor ledact;
MultiIO_out.led_dp_out <= r.ledreg(7) xnor ledact;
when others =>
null;
end case;
end process Multiplex;
end generate Multiplex3Sources;
Multiplex2Sources : if hpe_version /= midi generate
Multiplex : process(MUXCounter, r)
begin
-- disable LED output by default
MultiIO_out.led_enable <= '0' xnor ledact;
-- disable 7-segment display by default
MultiIO_out.led_ca_out <= "00" xnor (led7act & led7act);
-- set enable signal in the middle of LCD timeslots
if MUXCounter = 3 then
MultiIO_out.lcd_enable <= '1';
else
MultiIO_out.lcd_enable <= '0';
end if;
case MUXCounter is
when 0 | 1 =>
-- output logical value according to active level of the 7segment display
MultiIO_out.led_a_out <= r.led7reg(MUXCounter*8 + 0) xnor led7act;
MultiIO_out.led_b_out <= r.led7reg(MUXCounter*8 + 1) xnor led7act;
MultiIO_out.led_c_out <= r.led7reg(MUXCounter*8 + 2) xnor led7act;
MultiIO_out.led_d_out <= r.led7reg(MUXCounter*8 + 3) xnor led7act;
MultiIO_out.led_e_out <= r.led7reg(MUXCounter*8 + 4) xnor led7act;
MultiIO_out.led_f_out <= r.led7reg(MUXCounter*8 + 5) xnor led7act;
MultiIO_out.led_g_out <= r.led7reg(MUXCounter*8 + 6) xnor led7act;
MultiIO_out.led_dp_out <= r.led7reg(MUXCounter*8 + 7) xnor led7act;
-- selectively enable the current digit
for i in 0 to 1 loop
if i = MUXCounter then
MultiIO_out.led_ca_out(i) <= '1' xnor led7act;
else
MultiIO_out.led_ca_out(i) <= '0' xnor led7act;
end if;
end loop; -- i
when others =>
MultiIO_out.led_a_out <= r.lcdreg(0);
MultiIO_out.led_b_out <= r.lcdreg(1);
MultiIO_out.led_c_out <= r.lcdreg(2);
MultiIO_out.led_d_out <= r.lcdreg(3);
MultiIO_out.led_e_out <= r.lcdreg(4);
MultiIO_out.led_f_out <= r.lcdreg(5);
MultiIO_out.led_g_out <= r.lcdreg(6);
MultiIO_out.led_dp_out <= r.lcdreg(7);
end case;
end process Multiplex;
end generate Multiplex2Sources;
-- generate prescaler signal every 100 ms
-- control MUXCounter according to input and board type
Count1ms : process(clk, rst_n)
constant divider100ms : integer := clk_freq_in / 10_000;
variable frequency_counter : integer range 0 to Divider100ms;
begin
if rst_n = '0' then
frequency_counter := Divider100ms;
Enable1ms <= false;
MUXCounter <= 0;
elsif rising_edge(clk) then
if frequency_counter = 0 then -- 1-ms counter has expired
frequency_counter := Divider100ms;
Enable1ms <= true;
if (hpe_version = midi) then
-- skip LCD control sequence and go to
-- LED control
if (MUXCounter = 1 and r.new_data = '0') then
MUXCounter <= 5;
-- overflow at maximum counter value for Hpe_midi
elsif MUXCounter = MUXMAX-1 then
MUXCounter <= 0;
else
MUXCounter <= MUXCounter + 1;
end if;
elsif (hpe_version /= midi) then
-- skip LCD control sequence and go back to
-- 7-segment control
if (MUXCounter = 1 and r.new_data = '0') then
MUXCounter <= 0;
-- overflow at maximum counter value for Hpe_mini
elsif MUXCounter = MUXMAX-3 then
MUXCounter <= 0;
else
MUXCounter <= MUXCounter + 1;
end if;
end if;
else
frequency_counter := frequency_counter - 1;
Enable1ms <= false;
end if;
end if;
end process;
---------------------------------------------------------------------------------------
-- AUDIO CODEC SECTION
---------------------------------------------------------------------------------------
tlv320aic23b_audio : if hpe_version = mini_altera generate
-- audio clock generation
clk_gen : ClockGenerator
port map (
Clk => clk,
Reset => rst_n,
omclk => clkgen_mclk,
obclk => clkgen_bclk,
osclk => clkgen_sclk,
olrcout => clkgen_lrclk);
-- drive clock signals by clock generator
MultiIO_out.CODEC_SCLK <= clkgen_sclk;
MultiIO_out.CODEC_MCLK <= clkgen_mclk;
MultiIO_out.CODEC_BCLK <= clkgen_bclk;
MultiIO_out.CODEC_LRCIN <= clkgen_lrclk;
MultiIO_out.CODEC_LRCOUT <= clkgen_lrclk;
-- SPI control interface
spi_xmit_1 : spi_xmit
generic map (
data_width => N_CODECBITS)
port map (
clk_i => clkgen_SCLK,
rst_i => rst_n,
data_i => r.codecreg(N_CODECBITS-1 downto 0),
CODEC_SDIN => MultiIO_out.CODEC_SDIN,
CODEC_CS => MultiIO_out.CODEC_CS);
-- I2C data interface
ParToI2s_1 : ParToI2s
generic map (
SampleSize_g => N_CODECI2SBITS)
port map (
Clk_i => clk,
Reset_i => rst_n,
SampleLeft_i => SampleReg,
SampleRight_i => SampleReg,
StrobeLeft_i => Strobe,
StrobeRight_i => Strobe,
SampleAck_o => SampleAck,
WaitForSample_o => WaitForSample,
SClk_i => clkgen_sclk,
LRClk_i => clkgen_lrclk,
SdnyData_o => MultiIO_out.CODEC_DIN);
audio_ctrl_sm : process(SampleAck, WaitForSample, state)
begin
next_state <= state;
next_Strobe <= '0';
case state is
when WAIT_FOR_SYNC =>
if WaitForSample = '1' then
next_state <= READY;
end if;
when READY =>
next_state <= WAIT_FOR_ACK;
next_Strobe <= '1';
when WAIT_FOR_ACK =>
if SampleAck = '1' then
next_state <= READY;
end if;
when others =>
next_state <= WAIT_FOR_SYNC;
end case;
end process;
audio_ctrl_reg : process(clk, rst_n)
begin
if rst_n = '0' then -- asynchronous reset
state <= WAIT_FOR_SYNC;
Strobe <= '0';
SampleReg <= (others => '0');
elsif clk'event and clk = '1' then
state <= next_state;
Strobe <= next_Strobe;
if (next_Strobe) = '1' then
-- if Mode = '0' then
-- SampleReg <= std_ulogic_vector(unsigned(AudioSample)- X"80");
-- else
-- SampleReg <= AudioSample;
-- end if;
SampleReg <= std_ulogic_vector(r.codecreg2(N_CODECI2SBITS-1 downto 0));
end if;
end if;
end process;
end generate tlv320aic23b_audio;
---------------------------------------------------------------------------------------
-- DEBUG SECTION
---------------------------------------------------------------------------------------
-- pragma translate_off
KeyVal <=
ascii2char(conv_integer(Key)) when
(conv_integer(Key) >= 16#30#) and (conv_integer(Key) <= 16#46#)
else 'U';
bootmsg : report_version
generic map ("MultiIO_APB6:" & tost(pindex) &
", Human Interface Controller rev " & tost(REVISION) &
", IRQ " & tost(pirq));
-- pragma translate_on
end architecture;
|
mit
|
impedimentToProgress/UCI-BlueChip
|
AttackFiles/Attacks/privEsc/lib/gaisler/pci/pcilib.vhd
|
2
|
4563
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: pcilib
-- File: pcilib.vhd
-- Author: Alf Vaerneus - Gaisler Research
-- Description: Package with type declarations for PCI registers & constants
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
package pcilib is
constant zero : std_logic_vector(31 downto 0) := (others => '0');
constant addzero : std_logic_vector(31 downto 0) := (others => '0');
subtype word4 is std_logic_vector(3 downto 0);
subtype word32 is std_logic_vector(31 downto 0);
-- Constants for PCI commands
constant pci_memory_read : word4 := "0110";
constant pci_memory_write : word4 := "0111";
constant pci_config_read : word4 := "1010";
constant pci_config_write : word4 := "1011";
constant INT_ACK : word4 := "0000";
constant SPEC_CYCLE : word4 := "0001";
constant IO_READ : word4 := "0010";
constant IO_WRITE : word4 := "0011";
constant MEM_READ : word4 := "0110";
constant MEM_WRITE : word4 := "0111";
constant CONF_READ : word4 := "1010";
constant CONF_WRITE : word4 := "1011";
constant MEM_R_MULT : word4 := "1100";
constant DAC : word4 := "1101";
constant MEM_R_LINE : word4 := "1110";
constant MEM_W_INV : word4 := "1111";
-- Constants for word size
constant W_SIZE_8_n : word4 := "1110"; -- word size active low
constant W_SIZE_16_n : word4 := "1100";
constant W_SIZE_32_n : word4 := "0000";
type pci_config_command_type is record
-- ioen : std_logic; -- I/O access enable
men : std_logic; -- Memory access enable
msen : std_logic; -- Master enable
-- spcen : std_logic; -- Special cycle enable
mwie : std_logic; -- Memory write and invalidate enable
-- vgaps : std_logic; -- VGA palette snooping enable
per : std_logic; -- Parity error response enable
-- wcc : std_logic; -- Address stepping enable
-- serre : std_logic; -- Enable SERR# driver
-- fbtbe : std_logic; -- Fast back-to-back enable
end record;
type pci_config_status_type is record
-- c66mhz : std_logic; -- 66MHz capability
-- udf : std_logic; -- UDF supported
-- fbtbc : std_logic; -- Fast back-to-back capability
dped : std_logic; -- Data parity error detected
-- dst : std_logic_vector(1 downto 0); -- DEVSEL timing
sta : std_logic; -- Signaled target abort
rta : std_logic; -- Received target abort
rma : std_logic; -- Received master abort
-- sse : std_logic; -- Signaled system error
dpe : std_logic; -- Detected parity error
end record;
--type pci_config_type is record
-- conf_en : std_logic;
-- bus : std_logic_vector(7 downto 0);
-- dev : std_logic_vector(4 downto 0);
-- func : std_logic_vector(2 downto 0);
-- reg : std_logic_vector(5 downto 0);
-- data : std_logic_vector(31 downto 0);
--end record;
type pci_sigs_type is record
ad : std_logic_vector(31 downto 0);
cbe : std_logic_vector(3 downto 0);
frame : std_logic; -- Master frame
devsel : std_logic; -- PCI device select
trdy : std_logic; -- Target ready
irdy : std_logic; -- Master ready
stop : std_logic; -- Target stop request
par : std_logic; -- PCI bus parity
req : std_logic; -- Master bus request
perr : std_logic; -- Parity Error
oe_par : std_logic;
oe_ad : std_logic;
oe_ctrl : std_logic;
oe_cbe : std_logic;
oe_frame : std_logic;
oe_irdy : std_logic;
oe_req : std_logic;
oe_perr : std_logic;
end record;
end ;
|
mit
|
impedimentToProgress/UCI-BlueChip
|
AttackFiles/Attacks/privEsc/lib/gaisler/ambatest/ahbslv_em.vhd
|
2
|
6496
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ahbslv_em
-- File: ahbslv_em.vhd
-- Author: Alf Vaerneus, Gaisler Research
-- Description: AMBA AHB Slave emulator for simulation purposes only
------------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use grlib.devices.all;
use gaisler.ambatest.all;
library std;
use std.textio.all;
entity ahbslv_em is
generic(
hindex : integer := 0;
abits : integer := 10;
waitcycles : integer := 2;
retries : integer := 0;
memaddr : integer := 16#E00#;
memmask : integer := 16#F00#;
ioaddr : integer := 16#000#;
timeoutc : integer := 100;
dbglevel : integer := 1
);
port(
rst : in std_logic;
clk : in std_logic;
-- AMBA signals
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
-- TB signals
tbi : in tb_in_type;
tbo : out tb_out_type
);
end;
architecture tb of ahbslv_em is
constant VERSION : integer := 1;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg (VENDOR_GAISLER, GAISLER_AHBSLV_EM, 0, VERSION, 0),
4 => ahb_membar(memaddr, '0', '0', memmask),
others => zero32);
constant T_O : integer := timeoutc;
type mem_type is array(0 to ((2**abits)-1)) of std_logic_vector(31 downto 0);
type state_type is(idle,w,write,read,retry1,retry2);
type reg_type is record
state : state_type;
ad : std_logic_vector(abits-1 downto 0);
di : std_logic_vector(31 downto 0);
waitc : integer;
nretry : integer;
write : std_logic;
end record;
signal r,rin : reg_type;
signal do : std_logic_vector(31 downto 0);
begin
cont : process
file readfile,writefile : text;
variable first : boolean := true;
variable mem : mem_type;
variable L : line;
variable datahex : string(1 to 8);
variable count : integer;
begin
if first then
for i in 0 to ((2**abits)-1) loop
mem(i) := (others => '0');
end loop;
first := false;
elsif tbi.start = '1' then
if tbi.usewfile then
file_open(writefile, external_name => tbi.wfile(18 downto trimlen(tbi.wfile)), open_kind => write_mode);
count := conv_integer(tbi.address(abits-1 downto 0));
for i in 0 to tbi.no_words-1 loop
write(L,printhex(mem(count),32));
writeline(writefile,L);
count := count+4;
end loop;
file_close(writefile);
end if;
elsif r.ad(0) /= 'U' then
do <= mem(conv_integer(to_x01(r.ad)));
if r.write = '1' then mem(conv_integer(to_x01(r.ad))) := ahbsi.hwdata; end if;
end if;
tbo.ready <= tbi.start;
wait for 1 ns;
end process;
comb : process(ahbsi, rst, r)
variable v : reg_type;
variable vahbso : ahb_slv_out_type;
begin
v := r; v.write := '0';
v.di := ahbsi.hwdata;
vahbso.hready := '1'; vahbso.hresp := HRESP_OKAY;
vahbso.hrdata := do; vahbso.hsplit := (others => '0');
vahbso.hcache := '0'; vahbso.hirq := (others => '0');
vahbso.hconfig := hconfig;
if ahbsi.hready = '1' then v.ad := ahbsi.haddr(abits-1 downto 0); end if;
case r.state is
when idle =>
if (ahbsi.hsel(hindex) and ahbsi.hready and ahbsi.htrans(1)) = '1' then
if r.waitc > 0 then v.state := w; v.waitc := r.waitc-1;
elsif r.nretry > 0 then v.state := retry1;
elsif ahbsi.hwrite = '1' then v.state := write; v.write := '1';
else v.state := read; end if;
end if;
when w =>
vahbso.hready := '0';
if r.waitc = 0 then
v.waitc := waitcycles;
if r.nretry > 0 then v.state := retry1;
elsif ahbsi.hwrite = '1' then v.state := write; v.write := '1';
else v.state := read; end if;
else v.waitc := r.waitc-1; end if;
when write =>
v.nretry := retries;
if (ahbsi.hsel(hindex) and ahbsi.htrans(1)) = '0' then v.state := idle;
elsif r.waitc > 0 then v.state := w; v.waitc := r.waitc-1;
elsif ahbsi.hwrite = '0' then v.state := read;
else v.write := '1'; end if;
when read =>
v.nretry := retries;
if (ahbsi.hsel(hindex) and ahbsi.htrans(1)) = '0' then v.state := idle;
elsif r.waitc > 0 then v.state := w; v.waitc := r.waitc-1;
elsif ahbsi.hwrite = '1' then v.state := write; end if;
when retry1 =>
vahbso.hready := '0'; v.nretry := r.nretry-1;
vahbso.hresp := HRESP_RETRY;
v.state := retry2;
when retry2 =>
vahbso.hresp := HRESP_RETRY;
if (ahbsi.hsel(hindex) and ahbsi.hready and ahbsi.htrans(1)) = '1' then
if r.waitc > 0 then v.state := w; v.waitc := r.waitc-1;
elsif r.nretry > 0 then v.state := retry1;
elsif ahbsi.hwrite = '1' then v.state := write; v.write := '1';
else v.state := read; end if;
end if;
when others =>
end case;
vahbso.hindex := hindex;
if rst = '0' then
v.state := idle;
v.waitc := waitcycles;
v.nretry := retries;
v.ad := (others => '0');
v.di := (others => '0');
end if;
rin <= v;
ahbso <= vahbso;
end process;
clockreg : process(clk)
begin
if rising_edge(clk) then
r <= rin;
end if;
end process;
bootmsg : report_version
generic map ("pcislv_em" & tost(hindex) &
": PCI Slave Emulator rev " & tost(VERSION) &
" for simulation purpose only." &
" NOT syntheziseable.");
end;
-- pragma translate_on
|
mit
|
franz/pocl
|
examples/accel/rtl/gcu_ic/ic.vhdl
|
2
|
10585
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.ext;
use IEEE.std_logic_arith.sxt;
use work.ffaccel_globals.all;
use work.tce_util.all;
entity ffaccel_interconn is
port (
clk : in std_logic;
rstx : in std_logic;
glock : in std_logic;
socket_lsu_i1_data : out std_logic_vector(11 downto 0);
socket_lsu_i1_bus_cntrl : in std_logic_vector(0 downto 0);
socket_lsu_i2_data : out std_logic_vector(31 downto 0);
socket_lsu_i2_bus_cntrl : in std_logic_vector(0 downto 0);
socket_alu_comp_i1_data : out std_logic_vector(31 downto 0);
socket_alu_comp_i1_bus_cntrl : in std_logic_vector(0 downto 0);
socket_alu_comp_i2_data : out std_logic_vector(31 downto 0);
socket_alu_comp_i2_bus_cntrl : in std_logic_vector(0 downto 0);
socket_RF_i1_data : out std_logic_vector(31 downto 0);
socket_RF_i1_bus_cntrl : in std_logic_vector(0 downto 0);
socket_bool_i1_data : out std_logic_vector(0 downto 0);
socket_bool_i1_bus_cntrl : in std_logic_vector(0 downto 0);
socket_gcu_i1_data : out std_logic_vector(IMEMADDRWIDTH-1 downto 0);
socket_gcu_i1_bus_cntrl : in std_logic_vector(0 downto 0);
socket_gcu_i2_data : out std_logic_vector(IMEMADDRWIDTH-1 downto 0);
socket_gcu_i2_bus_cntrl : in std_logic_vector(0 downto 0);
socket_lsu_i1_1_data : out std_logic_vector(31 downto 0);
socket_lsu_i1_1_bus_cntrl : in std_logic_vector(0 downto 0);
socket_lsu_i2_1_data : out std_logic_vector(31 downto 0);
socket_lsu_i2_1_bus_cntrl : in std_logic_vector(0 downto 0);
socket_lsu_i2_1_1_data : out std_logic_vector(9 downto 0);
socket_lsu_i2_1_1_bus_cntrl : in std_logic_vector(0 downto 0);
socket_lsu_i1_1_1_data : out std_logic_vector(31 downto 0);
socket_lsu_i1_1_1_bus_cntrl : in std_logic_vector(0 downto 0);
socket_lsu_i2_1_1_2_1_data : out std_logic_vector(31 downto 0);
socket_lsu_i2_1_1_2_1_bus_cntrl : in std_logic_vector(0 downto 0);
B1_mux_ctrl_in : in std_logic_vector(3 downto 0);
B1_data_0_in : in std_logic_vector(31 downto 0);
B1_data_1_in : in std_logic_vector(31 downto 0);
B1_data_2_in : in std_logic_vector(31 downto 0);
B1_data_3_in : in std_logic_vector(0 downto 0);
B1_data_4_in : in std_logic_vector(IMEMADDRWIDTH-1 downto 0);
B1_data_5_in : in std_logic_vector(31 downto 0);
B1_data_6_in : in std_logic_vector(31 downto 0);
B1_data_7_in : in std_logic_vector(31 downto 0);
B1_data_8_in : in std_logic_vector(31 downto 0);
B1_data_9_in : in std_logic_vector(31 downto 0);
B1_data_10_in : in std_logic_vector(31 downto 0);
B1_1_mux_ctrl_in : in std_logic_vector(3 downto 0);
B1_1_data_0_in : in std_logic_vector(31 downto 0);
B1_1_data_1_in : in std_logic_vector(31 downto 0);
B1_1_data_2_in : in std_logic_vector(31 downto 0);
B1_1_data_3_in : in std_logic_vector(0 downto 0);
B1_1_data_4_in : in std_logic_vector(IMEMADDRWIDTH-1 downto 0);
B1_1_data_5_in : in std_logic_vector(31 downto 0);
B1_1_data_6_in : in std_logic_vector(31 downto 0);
B1_1_data_7_in : in std_logic_vector(31 downto 0);
B1_1_data_8_in : in std_logic_vector(31 downto 0);
B1_1_data_9_in : in std_logic_vector(31 downto 0);
B1_1_data_10_in : in std_logic_vector(31 downto 0);
simm_B1 : in std_logic_vector(31 downto 0);
simm_cntrl_B1 : in std_logic_vector(0 downto 0);
simm_B1_1 : in std_logic_vector(31 downto 0);
simm_cntrl_B1_1 : in std_logic_vector(0 downto 0));
end ffaccel_interconn;
architecture comb_andor of ffaccel_interconn is
signal databus_B1 : std_logic_vector(31 downto 0);
signal databus_B1_1 : std_logic_vector(31 downto 0);
component ffaccel_input_mux_2
generic (
BUSW_0 : integer := 32;
BUSW_1 : integer := 32;
DATAW : integer := 32);
port (
databus0 : in std_logic_vector(BUSW_0-1 downto 0);
databus1 : in std_logic_vector(BUSW_1-1 downto 0);
data : out std_logic_vector(DATAW-1 downto 0);
databus_cntrl : in std_logic_vector(0 downto 0));
end component;
component ffaccel_input_mux_12
generic (
BUSW_0 : integer := 32;
BUSW_1 : integer := 32;
BUSW_2 : integer := 32;
BUSW_3 : integer := 32;
BUSW_4 : integer := 32;
BUSW_5 : integer := 32;
BUSW_6 : integer := 32;
BUSW_7 : integer := 32;
BUSW_8 : integer := 32;
BUSW_9 : integer := 32;
BUSW_10 : integer := 32;
BUSW_11 : integer := 32;
DATAW : integer := 32);
port (
databus0 : in std_logic_vector(BUSW_0-1 downto 0);
databus1 : in std_logic_vector(BUSW_1-1 downto 0);
databus2 : in std_logic_vector(BUSW_2-1 downto 0);
databus3 : in std_logic_vector(BUSW_3-1 downto 0);
databus4 : in std_logic_vector(BUSW_4-1 downto 0);
databus5 : in std_logic_vector(BUSW_5-1 downto 0);
databus6 : in std_logic_vector(BUSW_6-1 downto 0);
databus7 : in std_logic_vector(BUSW_7-1 downto 0);
databus8 : in std_logic_vector(BUSW_8-1 downto 0);
databus9 : in std_logic_vector(BUSW_9-1 downto 0);
databus10 : in std_logic_vector(BUSW_10-1 downto 0);
databus11 : in std_logic_vector(BUSW_11-1 downto 0);
data : out std_logic_vector(DATAW-1 downto 0);
databus_cntrl : in std_logic_vector(3 downto 0));
end component;
begin -- comb_andor
RF_i1 : ffaccel_input_mux_2
generic map (
BUSW_0 => 32,
BUSW_1 => 32,
DATAW => 32)
port map (
databus0 => databus_B1,
databus1 => databus_B1_1,
data => socket_RF_i1_data,
databus_cntrl => socket_RF_i1_bus_cntrl);
alu_comp_i1 : ffaccel_input_mux_2
generic map (
BUSW_0 => 32,
BUSW_1 => 32,
DATAW => 32)
port map (
databus0 => databus_B1,
databus1 => databus_B1_1,
data => socket_alu_comp_i1_data,
databus_cntrl => socket_alu_comp_i1_bus_cntrl);
alu_comp_i2 : ffaccel_input_mux_2
generic map (
BUSW_0 => 32,
BUSW_1 => 32,
DATAW => 32)
port map (
databus0 => databus_B1,
databus1 => databus_B1_1,
data => socket_alu_comp_i2_data,
databus_cntrl => socket_alu_comp_i2_bus_cntrl);
bool_i1 : ffaccel_input_mux_2
generic map (
BUSW_0 => 32,
BUSW_1 => 32,
DATAW => 1)
port map (
databus0 => databus_B1,
databus1 => databus_B1_1,
data => socket_bool_i1_data,
databus_cntrl => socket_bool_i1_bus_cntrl);
gcu_i1 : ffaccel_input_mux_2
generic map (
BUSW_0 => 32,
BUSW_1 => 32,
DATAW => IMEMADDRWIDTH)
port map (
databus0 => databus_B1,
databus1 => databus_B1_1,
data => socket_gcu_i1_data,
databus_cntrl => socket_gcu_i1_bus_cntrl);
gcu_i2 : ffaccel_input_mux_2
generic map (
BUSW_0 => 32,
BUSW_1 => 32,
DATAW => IMEMADDRWIDTH)
port map (
databus0 => databus_B1,
databus1 => databus_B1_1,
data => socket_gcu_i2_data,
databus_cntrl => socket_gcu_i2_bus_cntrl);
lsu_i1 : ffaccel_input_mux_2
generic map (
BUSW_0 => 32,
BUSW_1 => 32,
DATAW => 12)
port map (
databus0 => databus_B1,
databus1 => databus_B1_1,
data => socket_lsu_i1_data,
databus_cntrl => socket_lsu_i1_bus_cntrl);
lsu_i1_1 : ffaccel_input_mux_2
generic map (
BUSW_0 => 32,
BUSW_1 => 32,
DATAW => 32)
port map (
databus0 => databus_B1,
databus1 => databus_B1_1,
data => socket_lsu_i1_1_data,
databus_cntrl => socket_lsu_i1_1_bus_cntrl);
lsu_i1_1_1 : ffaccel_input_mux_2
generic map (
BUSW_0 => 32,
BUSW_1 => 32,
DATAW => 32)
port map (
databus0 => databus_B1,
databus1 => databus_B1_1,
data => socket_lsu_i1_1_1_data,
databus_cntrl => socket_lsu_i1_1_1_bus_cntrl);
lsu_i2 : ffaccel_input_mux_2
generic map (
BUSW_0 => 32,
BUSW_1 => 32,
DATAW => 32)
port map (
databus0 => databus_B1,
databus1 => databus_B1_1,
data => socket_lsu_i2_data,
databus_cntrl => socket_lsu_i2_bus_cntrl);
lsu_i2_1 : ffaccel_input_mux_2
generic map (
BUSW_0 => 32,
BUSW_1 => 32,
DATAW => 32)
port map (
databus0 => databus_B1,
databus1 => databus_B1_1,
data => socket_lsu_i2_1_data,
databus_cntrl => socket_lsu_i2_1_bus_cntrl);
lsu_i2_1_1 : ffaccel_input_mux_2
generic map (
BUSW_0 => 32,
BUSW_1 => 32,
DATAW => 10)
port map (
databus0 => databus_B1,
databus1 => databus_B1_1,
data => socket_lsu_i2_1_1_data,
databus_cntrl => socket_lsu_i2_1_1_bus_cntrl);
lsu_i2_1_1_2_1 : ffaccel_input_mux_2
generic map (
BUSW_0 => 32,
BUSW_1 => 32,
DATAW => 32)
port map (
databus0 => databus_B1,
databus1 => databus_B1_1,
data => socket_lsu_i2_1_1_2_1_data,
databus_cntrl => socket_lsu_i2_1_1_2_1_bus_cntrl);
B1_bus_mux_inst : ffaccel_input_mux_12
generic map (
BUSW_0 => 32,
BUSW_1 => 32,
BUSW_2 => 32,
BUSW_3 => 1,
BUSW_4 => IMEMADDRWIDTH,
BUSW_5 => 32,
BUSW_6 => 32,
BUSW_7 => 32,
BUSW_8 => 32,
BUSW_9 => 32,
BUSW_10 => 32,
BUSW_11 => 32,
DATAW => 32)
port map (
databus0 => B1_data_0_in,
databus1 => B1_data_1_in,
databus2 => B1_data_2_in,
databus3 => B1_data_3_in,
databus4 => B1_data_4_in,
databus5 => B1_data_5_in,
databus6 => B1_data_6_in,
databus7 => B1_data_7_in,
databus8 => B1_data_8_in,
databus9 => B1_data_9_in,
databus10 => B1_data_10_in,
databus11 => simm_B1,
data => databus_B1,
databus_cntrl => B1_mux_ctrl_in);
B1_1_bus_mux_inst : ffaccel_input_mux_12
generic map (
BUSW_0 => 32,
BUSW_1 => 32,
BUSW_2 => 32,
BUSW_3 => 1,
BUSW_4 => IMEMADDRWIDTH,
BUSW_5 => 32,
BUSW_6 => 32,
BUSW_7 => 32,
BUSW_8 => 32,
BUSW_9 => 32,
BUSW_10 => 32,
BUSW_11 => 32,
DATAW => 32)
port map (
databus0 => B1_1_data_0_in,
databus1 => B1_1_data_1_in,
databus2 => B1_1_data_2_in,
databus3 => B1_1_data_3_in,
databus4 => B1_1_data_4_in,
databus5 => B1_1_data_5_in,
databus6 => B1_1_data_6_in,
databus7 => B1_1_data_7_in,
databus8 => B1_1_data_8_in,
databus9 => B1_1_data_9_in,
databus10 => B1_1_data_10_in,
databus11 => simm_B1_1,
data => databus_B1_1,
databus_cntrl => B1_1_mux_ctrl_in);
end comb_andor;
|
mit
|
impedimentToProgress/UCI-BlueChip
|
AttackFiles/Attacks/memAttack/lib/techmap/inferred/mul_inferred.vhd
|
2
|
2183
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: gen_mul_61x61
-- File: mul_inferred.vhd
-- Author: Edvin Catovic - Gaisler Research
-- Description: Generic 61x61 multplier
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.stdlib.all;
entity gen_mul_61x61 is
port(A : in std_logic_vector(60 downto 0);
B : in std_logic_vector(60 downto 0);
EN : in std_logic;
CLK : in std_logic;
PRODUCT : out std_logic_vector(121 downto 0));
end;
architecture rtl of gen_mul_61x61 is
signal r1, r1in, r2, r2in : std_logic_vector(121 downto 0);
begin
comb : process(A, B, r1)
begin
-- pragma translate_off
if not (is_x(A) or is_x(B)) then
-- pragma translate_on
r1in <= std_logic_vector(unsigned(A) * unsigned(B));
-- pragma translate_off
end if;
-- pragma translate_on
r2in <= r1;
end process;
reg : process(clk)
begin
if rising_edge(clk) then
if EN = '1' then
r1 <= r1in;
r2 <= r2in;
end if;
end if;
end process;
PRODUCT <= r2;
end;
|
mit
|
impedimentToProgress/UCI-BlueChip
|
AttackFiles/Attacks/privEsc/lib/gaisler/misc/misc.vhd
|
2
|
25471
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: misc
-- File: misc.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Misc models
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.devices.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
package misc is
-- reset generator with filter
component rstgen
generic (acthigh : integer := 0; syncrst : integer := 0;
scanen : integer := 0);
port (
rstin : in std_ulogic;
clk : in std_ulogic;
clklock : in std_ulogic;
rstout : out std_ulogic;
rstoutraw : out std_ulogic;
testrst : in std_ulogic := '0';
testen : in std_ulogic := '0');
end component;
type gptimer_in_type is record
dhalt : std_ulogic;
extclk : std_ulogic;
end record;
type gptimer_out_type is record
tick : std_logic_vector(0 to 7);
timer1 : std_logic_vector(31 downto 0);
wdogn : std_ulogic;
wdog : std_ulogic;
end record;
component gptimer
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0;
sepirq : integer := 0; -- use separate interrupts for each timer
sbits : integer := 16; -- scaler bits
ntimers : integer range 1 to 7 := 1; -- number of timers
nbits : integer := 32; -- timer bits
wdog : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
gpti : in gptimer_in_type;
gpto : out gptimer_out_type
);
end component;
-- 32-bit ram with AHB interface
component ahbram
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
tech : integer := DEFMEMTECH;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type);
end component;
type ahbram_out_type is record
ce : std_ulogic;
end record;
component ftahbram is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
tech : integer := DEFMEMTECH;
kbytes : integer := 1;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
edacen : integer := 1;
autoscrub : integer := 0;
errcnten : integer := 0;
cntbits : integer range 1 to 8 := 1;
ahbpipe : integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
aramo : out ahbram_out_type
);
end component;
component ahbtrace is
generic (
hindex : integer := 0;
ioaddr : integer := 16#000#;
iomask : integer := 16#E00#;
tech : integer := DEFMEMTECH;
irq : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end component;
type ahb_dma_in_type is record
address : std_logic_vector(31 downto 0);
wdata : std_logic_vector(31 downto 0);
start : std_ulogic;
burst : std_ulogic;
write : std_ulogic;
busy : std_ulogic;
irq : std_ulogic;
size : std_logic_vector(1 downto 0);
end record;
type ahb_dma_out_type is record
start : std_ulogic;
active : std_ulogic;
ready : std_ulogic;
retry : std_ulogic;
mexc : std_ulogic;
haddr : std_logic_vector(9 downto 0);
rdata : std_logic_vector(31 downto 0);
end record;
component ahbmst
generic (
hindex : integer := 0;
hirq : integer := 0;
venid : integer := VENDOR_GAISLER;
devid : integer := 0;
version : integer := 0;
chprot : integer := 3;
incaddr : integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
dmai : in ahb_dma_in_type;
dmao : out ahb_dma_out_type;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type
);
end component;
type gpio_in_type is record
din : std_logic_vector(31 downto 0);
sig_in : std_logic_vector(31 downto 0);
sig_en : std_logic_vector(31 downto 0);
end record;
type gpio_out_type is record
dout : std_logic_vector(31 downto 0);
oen : std_logic_vector(31 downto 0);
val : std_logic_vector(31 downto 0);
sig_out : std_logic_vector(31 downto 0);
end record;
type ahb2ahb_ctrl_type is record
slck : std_ulogic;
blck : std_ulogic;
end record;
component grgpio
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
imask : integer := 16#0000#;
nbits : integer := 16; -- GPIO bits
oepol : integer := 0; -- Output enable polarity
syncrst : integer := 0;
bypass : integer := 16#0000#;
scantest : integer := 0;
bpdir : integer := 16#0000#
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
gpioi : in gpio_in_type;
gpioo : out gpio_out_type
);
end component;
component ahb2ahb
generic(
memtech : integer := 0;
hsindex : integer := 0;
hmindex : integer := 0;
slv : integer := 0;
dir : integer := 0; -- 0 - down, 1 - up
ffact : integer := 0;
pfen : integer range 0 to 1 := 0;
rbufsz : integer range 2 to 32 := 8;
wbufsz : integer range 2 to 32 := 2;
iburst : integer range 4 to 8 := 8;
rburst : integer range 2 to 32 := 8;
irqsync : integer range 0 to 2 := 0;
bar0 : integer range 0 to 1073741823 := 0;
bar1 : integer range 0 to 1073741823 := 0;
bar2 : integer range 0 to 1073741823 := 0;
bar3 : integer range 0 to 1073741823 := 0;
sbus : integer := 0;
mbus : integer := 0;
ioarea : integer := 0;
ibrsten : integer := 0);
port (
rstn : in std_ulogic;
hclkm : in std_ulogic;
hclks : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
ahbso2 : in ahb_slv_out_vector;
lcki : in ahb2ahb_ctrl_type;
lcko : out ahb2ahb_ctrl_type
);
end component;
component ahbbridge
generic(
memtech : integer := 0;
ffact : integer := 2;
-- high-speed bus
hsb_hsindex : integer := 0;
hsb_hmindex : integer := 0;
hsb_iclsize : integer range 4 to 8 := 8;
hsb_bank0 : integer range 0 to 1073741823 := 0;
hsb_bank1 : integer range 0 to 1073741823 := 0;
hsb_bank2 : integer range 0 to 1073741823 := 0;
hsb_bank3 : integer range 0 to 1073741823 := 0;
hsb_ioarea : integer := 0;
-- low-speed bus
lsb_hsindex : integer := 0;
lsb_hmindex : integer := 0;
lsb_rburst : integer range 16 to 32 := 16;
lsb_wburst : integer range 2 to 32 := 8;
lsb_bank0 : integer range 0 to 1073741823 := 0;
lsb_bank1 : integer range 0 to 1073741823 := 0;
lsb_bank2 : integer range 0 to 1073741823 := 0;
lsb_bank3 : integer range 0 to 1073741823 := 0;
lsb_ioarea : integer := 0);
port (
rstn : in std_ulogic;
hsb_clk : in std_ulogic;
lsb_clk : in std_ulogic;
hsb_ahbsi : in ahb_slv_in_type;
hsb_ahbso : out ahb_slv_out_type;
hsb_ahbsov: in ahb_slv_out_vector;
hsb_ahbmi : in ahb_mst_in_type;
hsb_ahbmo : out ahb_mst_out_type;
lsb_ahbsi : in ahb_slv_in_type;
lsb_ahbso : out ahb_slv_out_type;
lsb_ahbsov: in ahb_slv_out_vector;
lsb_ahbmi : in ahb_mst_in_type;
lsb_ahbmo : out ahb_mst_out_type);
end component;
function ahb2ahb_membar(memaddr : ahb_addr_type; prefetch, cache : std_ulogic;
addrmask : ahb_addr_type)
return integer;
function ahb2ahb_iobar(memaddr : ahb_addr_type; addrmask : ahb_addr_type)
return integer;
type ahbstat_in_type is record
cerror : std_logic_vector(0 to NAHBSLV-1);
end record;
component ahbstat is
generic(
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#FFF#;
pirq : integer := 0;
nftslv : integer range 1 to NAHBSLV - 1 := 3);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbsi : in ahb_slv_in_type;
stati : in ahbstat_in_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type
);
end component;
type nuhosp3_in_type is record
flash_d : std_logic_vector(15 downto 0);
smsc_data : std_logic_vector(31 downto 0);
smsc_ardy : std_ulogic;
smsc_intr : std_ulogic;
smsc_nldev : std_ulogic;
lcd_data : std_logic_vector(7 downto 0);
end record;
type nuhosp3_out_type is record
flash_a : std_logic_vector(20 downto 0);
flash_d : std_logic_vector(15 downto 0);
flash_oen : std_ulogic;
flash_wen : std_ulogic;
flash_cen : std_ulogic;
smsc_addr : std_logic_vector(14 downto 0);
smsc_data : std_logic_vector(31 downto 0);
smsc_nbe : std_logic_vector(3 downto 0);
smsc_resetn : std_ulogic;
smsc_nrd : std_ulogic;
smsc_nwr : std_ulogic;
smsc_ncs : std_ulogic;
smsc_aen : std_ulogic;
smsc_lclk : std_ulogic;
smsc_wnr : std_ulogic;
smsc_rdyrtn : std_ulogic;
smsc_cycle : std_ulogic;
smsc_nads : std_ulogic;
smsc_ben : std_ulogic;
lcd_data : std_logic_vector(7 downto 0);
lcd_rs : std_ulogic;
lcd_rw : std_ulogic;
lcd_en : std_ulogic;
lcd_backl : std_ulogic;
lcd_ben : std_ulogic;
end record;
component nuhosp3
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
ioaddr : integer := 16#200#;
iomask : integer := 16#fff#);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
nui : in nuhosp3_in_type;
nuo : out nuhosp3_out_type
);
end component;
-- On-chip Logic Analyzer
component logan is
generic (
dbits : integer range 0 to 256 := 32; -- Number of traced signals
depth : integer range 256 to 16384 := 1024; -- Depth of trace buffer
trigl : integer range 1 to 63 := 1; -- Number of trigger levels
usereg : integer range 0 to 1 := 1; -- Use input register
usequal : integer range 0 to 1 := 0;
usediv : integer range 0 to 1 := 1;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#F00#;
memtech : integer := DEFMEMTECH);
port (
rstn : in std_logic;
clk : in std_logic;
tclk : in std_logic;
apbi : in apb_slv_in_type; -- APB in record
apbo : out apb_slv_out_type; -- APB out record
signals : in std_logic_vector(dbits - 1 downto 0)); -- Traced signals
end component;
type ps2_in_type is record
ps2_clk_i : std_ulogic;
ps2_data_i : std_ulogic;
end record;
type ps2_out_type is record
ps2_clk_o : std_ulogic;
ps2_clk_oe : std_ulogic;
ps2_data_o : std_ulogic;
ps2_data_oe : std_ulogic;
end record;
component apbps2
generic(
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0;
fKHz : integer := 50000;
fixed : integer := 1);
port(
rst : in std_ulogic; -- Global asynchronous reset
clk : in std_ulogic; -- Global clock
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ps2i : in ps2_in_type;
ps2o : out ps2_out_type
);
end component;
type apbvga_out_type is record
hsync : std_ulogic; -- horizontal sync
vsync : std_ulogic; -- vertical sync
comp_sync : std_ulogic; -- composite sync
blank : std_ulogic; -- blank signal
video_out_r : std_logic_vector(7 downto 0); -- red channel
video_out_g : std_logic_vector(7 downto 0); -- green channel
video_out_b : std_logic_vector(7 downto 0); -- blue channel
end record;
component apbvga
generic(
memtech : integer := DEFMEMTECH;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#);
port(
rst : in std_ulogic; -- Global asynchronous reset
clk : in std_ulogic; -- Global clock
vgaclk : in std_ulogic; -- VGA clock
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
vgao : out apbvga_out_type
);
end component;
component svgactrl
generic(
length : integer := 384; -- Fifo-length
part : integer := 128; -- Fifo-part lenght
memtech : integer := DEFMEMTECH;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
hindex : integer := 0;
hirq : integer := 0;
clk0 : integer := 40000;
clk1 : integer := 20000;
clk2 : integer := 15385;
clk3 : integer := 0;
burstlen : integer range 2 to 8 := 8
);
port (
rst : in std_logic;
clk : in std_logic;
vgaclk : in std_logic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
vgao : out apbvga_out_type;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
clk_sel : out std_logic_vector(1 downto 0)
);
end component;
constant vgao_none : apbvga_out_type :=
('0', '0', '0', '0', "00000000", "00000000", "00000000");
constant ps2o_none : ps2_out_type := ('1', '1', '1', '1');
-- component ahbrom
-- generic (
-- hindex : integer := 0;
-- haddr : integer := 0;
-- hmask : integer := 16#fff#;
-- pipe : integer := 0;
-- tech : integer := 0;
-- kbytes : integer := 1);
-- port (
-- rst : in std_ulogic;
-- clk : in std_ulogic;
-- ahbsi : in ahb_slv_in_type;
-- ahbso : out ahb_slv_out_type
-- );
-- end component;
component ahbdma
generic (
hindex : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0;
dbuf : integer := 0);
port (
rst : in std_logic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type
);
end component;
-----------------------------------------------------------------------------
-- Interface type declarations for FIFO controller
-----------------------------------------------------------------------------
type FIFO_In_Type is record
Din: Std_Logic_Vector(31 downto 0); -- data input
Pin: Std_Logic_Vector( 3 downto 0); -- parity input
EFn: Std_ULogic; -- empty flag
FFn: Std_ULogic; -- full flag
HFn: Std_ULogic; -- half flag
end record;
type FIFO_Out_Type is record
Dout: Std_Logic_Vector(31 downto 0); -- data output
Den: Std_Logic_Vector(31 downto 0); -- data enable
Pout: Std_Logic_Vector( 3 downto 0); -- parity output
Pen: Std_Logic_Vector( 3 downto 0); -- parity enable
WEn: Std_ULogic; -- write enable
REn: Std_ULogic; -- read enable
end record;
-----------------------------------------------------------------------------
-- Component declaration for GR FIFO Interface
-----------------------------------------------------------------------------
component grfifo is
generic (
hindex: Integer := 0;
pindex: Integer := 0;
paddr: Integer := 0;
pmask: Integer := 16#FFF#;
pirq: Integer := 1; -- index of first irq
dwidth: Integer := 16; -- data width
ptrwidth: Integer range 4 to 16 := 12; -- 16 to 64k bytes
-- 128 to 512k bits
singleirq: Integer range 0 to 1 := 0; -- single irq output
oepol: Integer := 1); -- output enable polarity
port (
rstn: in Std_ULogic;
clk: in Std_ULogic;
apbi: in APB_Slv_In_Type;
apbo: out APB_Slv_Out_Type;
ahbi: in AHB_Mst_In_Type;
ahbo: out AHB_Mst_Out_Type;
fifoi: in FIFO_In_Type;
fifoo: out FIFO_Out_Type);
end component;
-----------------------------------------------------------------------------
-- Interface type declarations for CAN controllers
-----------------------------------------------------------------------------
type Analog_In_Type is record
Ain: Std_Logic_Vector(31 downto 0); -- address input
Din: Std_Logic_Vector(31 downto 0); -- data input
Rdy: Std_ULogic; -- adc ready input
Trig: Std_Logic_Vector( 2 downto 0); -- adc trigger inputs
end record;
type Analog_Out_Type is record
Aout: Std_Logic_Vector(31 downto 0); -- address output
Aen: Std_Logic_Vector(31 downto 0); -- address enable
Dout: Std_Logic_Vector(31 downto 0); -- dac data output
Den: Std_Logic_Vector(31 downto 0); -- dac data enable
Wr: Std_ULogic; -- dac write strobe
CS: Std_ULogic; -- adc chip select
RC: Std_ULogic; -- adc read/convert
end record;
-----------------------------------------------------------------------------
-- Component declaration for GR ADC/DAC Interface
-----------------------------------------------------------------------------
component gradcdac is
generic (
pindex: Integer := 0;
paddr: Integer := 0;
pmask: Integer := 16#FFF#;
pirq: Integer := 1; -- index of first irq
awidth: Integer := 8; -- address width
dwidth: Integer := 16; -- data width
oepol: Integer := 1); -- output enable polarity
port (
rstn: in Std_ULogic;
clk: in Std_ULogic;
apbi: in APB_Slv_In_Type;
apbo: out APB_Slv_Out_Type;
adi: in Analog_In_Type;
ado: out Analog_Out_Type);
end component;
component grclkgate
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
nbits : integer := 16
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
clockdis : out std_logic_vector(nbits-1 downto 0);
reset : out std_logic_vector(nbits-1 downto 0)
);
end component;
-----------------------------------------------------------------------------
-- I2C types and components
-----------------------------------------------------------------------------
type i2c_in_type is record
scl : std_ulogic;
sda : std_ulogic;
end record;
type i2c_out_type is record
scl : std_ulogic;
scloen : std_ulogic;
sda : std_ulogic;
sdaoen : std_ulogic;
end record;
-- AMBA wrapper for OC I2C-master
component i2cmst
generic (
pindex : integer;
paddr : integer;
pmask : integer;
pirq : integer;
oepol : integer range 0 to 1 := 0
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
i2ci : in i2c_in_type;
i2co : out i2c_out_type
);
end component;
component i2cslv
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0;
hardaddr : integer range 0 to 1 := 0;
tenbit : integer range 0 to 1 := 0;
i2caddr : integer range 0 to 1023 := 0;
oepol : integer range 0 to 1 := 0
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
i2ci : in i2c_in_type;
i2co : out i2c_out_type
);
end component;
-----------------------------------------------------------------------------
-- SPI controller
-----------------------------------------------------------------------------
type spi_in_type is record
miso : std_ulogic;
mosi : std_ulogic;
sck : std_ulogic;
spisel : std_ulogic;
end record;
type spi_out_type is record
miso : std_ulogic;
misooen : std_ulogic;
mosi : std_ulogic;
mosioen : std_ulogic;
sck : std_ulogic;
sckoen : std_ulogic;
ssn : std_logic_vector(7 downto 0); -- used by GE/OC SPI core
end record;
component spictrl
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0;
fdepth : integer range 1 to 7 := 1;
slvselen : integer range 0 to 1 := 0;
slvselsz : integer range 1 to 32 := 1;
oepol : integer range 0 to 1 := 0
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
spii : in spi_in_type;
spio : out spi_out_type;
slvsel : out std_logic_vector((slvselsz-1) downto 0)
);
end component;
function nandtree(v : std_logic_vector) return std_ulogic;
end;
package body misc is
function ahb2ahb_membar(memaddr : ahb_addr_type; prefetch, cache : std_ulogic;
addrmask : ahb_addr_type)
return integer is
variable tmp : std_logic_vector(29 downto 0);
variable bar : std_logic_vector(31 downto 0);
variable res : integer range 0 to 1073741823;
begin
bar := ahb_membar(memaddr, prefetch, cache, addrmask);
tmp := (others => '0');
tmp(29 downto 18) := bar(31 downto 20);
tmp(17 downto 0) := bar(17 downto 0);
res := conv_integer(tmp);
return(res);
end;
function ahb2ahb_iobar(memaddr : ahb_addr_type; addrmask : ahb_addr_type)
return integer is
variable tmp : std_logic_vector(29 downto 0);
variable bar : std_logic_vector(31 downto 0);
variable res : integer range 0 to 1073741823;
begin
bar := ahb_iobar(memaddr, addrmask);
tmp := (others => '0');
tmp(29 downto 18) := bar(31 downto 20);
tmp(17 downto 0) := bar(17 downto 0);
res := conv_integer(tmp);
return(res);
end;
function nandtree(v : std_logic_vector) return std_ulogic is
variable a : std_logic_vector(v'length-1 downto 0);
variable b : std_logic_vector(v'length downto 0);
begin
a := v; b(0) := '1';
for i in 0 to v'length-1 loop
b(i+1) := a(i) nand b(i);
end loop;
return b(v'length);
end;
end;
|
mit
|
impedimentToProgress/UCI-BlueChip
|
AttackFiles/Attacks/memAttack/lib/techmap/axcelerator/grspwc_axcelerator.vhd
|
2
|
19858
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: grspwc_axcelerator
-- File: grspwc_axcelerator.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: tech wrapper for axcelerator grspwc netlist
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library axcelerator;
use axcelerator.all;
entity grspwc_axcelerator is
generic(
sysfreq : integer := 40000;
usegen : integer range 0 to 1 := 1;
nsync : integer range 1 to 2 := 1;
rmap : integer range 0 to 1 := 0;
rmapcrc : integer range 0 to 1 := 0;
fifosize1 : integer range 4 to 32 := 16;
fifosize2 : integer range 16 to 64 := 16;
rxunaligned : integer range 0 to 1 := 0;
rmapbufs : integer range 2 to 8 := 4;
scantest : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
txclk : in std_ulogic;
--ahb mst in
hgrant : in std_ulogic;
hready : in std_ulogic;
hresp : in std_logic_vector(1 downto 0);
hrdata : in std_logic_vector(31 downto 0);
--ahb mst out
hbusreq : out std_ulogic;
hlock : out std_ulogic;
htrans : out std_logic_vector(1 downto 0);
haddr : out std_logic_vector(31 downto 0);
hwrite : out std_ulogic;
hsize : out std_logic_vector(2 downto 0);
hburst : out std_logic_vector(2 downto 0);
hprot : out std_logic_vector(3 downto 0);
hwdata : out std_logic_vector(31 downto 0);
--apb slv in
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
--apb slv out
prdata : out std_logic_vector(31 downto 0);
--spw in
di : in std_logic_vector(1 downto 0);
si : in std_logic_vector(1 downto 0);
--spw out
do : out std_logic_vector(1 downto 0);
so : out std_logic_vector(1 downto 0);
--time iface
tickin : in std_ulogic;
tickout : out std_ulogic;
--irq
irq : out std_logic;
--misc
clkdiv10 : in std_logic_vector(7 downto 0);
dcrstval : in std_logic_vector(9 downto 0);
timerrstval : in std_logic_vector(11 downto 0);
--rmapen
rmapen : in std_ulogic;
--clk bufs
rxclki : in std_logic_vector(1 downto 0);
nrxclki : in std_logic_vector(1 downto 0);
rxclko : out std_logic_vector(1 downto 0);
--rx ahb fifo
rxrenable : out std_ulogic;
rxraddress : out std_logic_vector(4 downto 0);
rxwrite : out std_ulogic;
rxwdata : out std_logic_vector(31 downto 0);
rxwaddress : out std_logic_vector(4 downto 0);
rxrdata : in std_logic_vector(31 downto 0);
--tx ahb fifo
txrenable : out std_ulogic;
txraddress : out std_logic_vector(4 downto 0);
txwrite : out std_ulogic;
txwdata : out std_logic_vector(31 downto 0);
txwaddress : out std_logic_vector(4 downto 0);
txrdata : in std_logic_vector(31 downto 0);
--nchar fifo
ncrenable : out std_ulogic;
ncraddress : out std_logic_vector(5 downto 0);
ncwrite : out std_ulogic;
ncwdata : out std_logic_vector(8 downto 0);
ncwaddress : out std_logic_vector(5 downto 0);
ncrdata : in std_logic_vector(8 downto 0);
--rmap buf
rmrenable : out std_ulogic;
rmraddress : out std_logic_vector(7 downto 0);
rmwrite : out std_ulogic;
rmwdata : out std_logic_vector(7 downto 0);
rmwaddress : out std_logic_vector(7 downto 0);
rmrdata : in std_logic_vector(7 downto 0);
linkdis : out std_ulogic;
testclk : in std_ulogic := '0';
testrst : in std_ulogic := '0';
testen : in std_ulogic := '0'
);
end entity;
architecture rtl of grspwc_axcelerator is
component grspwc_axcelerator_16_16_rmap0_crc1 is
port(
rst : in std_logic;
clk : in std_logic;
txclk : in std_logic;
hgrant : in std_logic;
hready : in std_logic;
hresp : in std_logic_vector(1 downto 0);
hrdata : in std_logic_vector(31 downto 0);
hbusreq : out std_logic;
hlock : out std_logic;
htrans : out std_logic_vector(1 downto 0);
haddr : out std_logic_vector(31 downto 0);
hwrite : out std_logic;
hsize : out std_logic_vector(2 downto 0);
hburst : out std_logic_vector(2 downto 0);
hprot : out std_logic_vector(3 downto 0);
hwdata : out std_logic_vector(31 downto 0);
psel : in std_logic;
penable : in std_logic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_logic;
pwdata : in std_logic_vector(31 downto 0);
prdata : out std_logic_vector(31 downto 0);
di : in std_logic_vector(1 downto 0);
si : in std_logic_vector(1 downto 0);
do : out std_logic_vector(1 downto 0);
so : out std_logic_vector(1 downto 0);
tickin : in std_logic;
tickout : out std_logic;
irq : out std_logic;
clkdiv10 : in std_logic_vector(7 downto 0);
dcrstval : in std_logic_vector(9 downto 0);
timerrstval : in std_logic_vector(11 downto 0);
rmapen : in std_logic;
rxclki : in std_logic_vector(1 downto 0);
nrxclki : in std_logic_vector(1 downto 0);
rxclko : out std_logic_vector(1 downto 0);
rxrenable : out std_logic;
rxraddress : out std_logic_vector(4 downto 0);
rxwrite : out std_logic;
rxwdata : out std_logic_vector(31 downto 0);
rxwaddress : out std_logic_vector(4 downto 0);
rxrdata : in std_logic_vector(31 downto 0);
txrenable : out std_logic;
txraddress : out std_logic_vector(4 downto 0);
txwrite : out std_logic;
txwdata : out std_logic_vector(31 downto 0);
txwaddress : out std_logic_vector(4 downto 0);
txrdata : in std_logic_vector(31 downto 0);
ncrenable : out std_logic;
ncraddress : out std_logic_vector(5 downto 0);
ncwrite : out std_logic;
ncwdata : out std_logic_vector(8 downto 0);
ncwaddress : out std_logic_vector(5 downto 0);
ncrdata : in std_logic_vector(8 downto 0);
rmrenable : out std_logic;
rmraddress : out std_logic_vector(7 downto 0);
rmwrite : out std_logic;
rmwdata : out std_logic_vector(7 downto 0);
rmwaddress : out std_logic_vector(7 downto 0);
rmrdata : in std_logic_vector(7 downto 0);
linkdis : out std_logic;
testclk : in std_logic;
testrst : in std_logic;
testen : in std_logic);
end component;
component grspwc_axcelerator_16_16_rmap8_crc1 is
port(
rst : in std_logic;
clk : in std_logic;
txclk : in std_logic;
hgrant : in std_logic;
hready : in std_logic;
hresp : in std_logic_vector(1 downto 0);
hrdata : in std_logic_vector(31 downto 0);
hbusreq : out std_logic;
hlock : out std_logic;
htrans : out std_logic_vector(1 downto 0);
haddr : out std_logic_vector(31 downto 0);
hwrite : out std_logic;
hsize : out std_logic_vector(2 downto 0);
hburst : out std_logic_vector(2 downto 0);
hprot : out std_logic_vector(3 downto 0);
hwdata : out std_logic_vector(31 downto 0);
psel : in std_logic;
penable : in std_logic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_logic;
pwdata : in std_logic_vector(31 downto 0);
prdata : out std_logic_vector(31 downto 0);
di : in std_logic_vector(1 downto 0);
si : in std_logic_vector(1 downto 0);
do : out std_logic_vector(1 downto 0);
so : out std_logic_vector(1 downto 0);
tickin : in std_logic;
tickout : out std_logic;
irq : out std_logic;
clkdiv10 : in std_logic_vector(7 downto 0);
dcrstval : in std_logic_vector(9 downto 0);
timerrstval : in std_logic_vector(11 downto 0);
rmapen : in std_logic;
rxclki : in std_logic_vector(1 downto 0);
nrxclki : in std_logic_vector(1 downto 0);
rxclko : out std_logic_vector(1 downto 0);
rxrenable : out std_logic;
rxraddress : out std_logic_vector(4 downto 0);
rxwrite : out std_logic;
rxwdata : out std_logic_vector(31 downto 0);
rxwaddress : out std_logic_vector(4 downto 0);
rxrdata : in std_logic_vector(31 downto 0);
txrenable : out std_logic;
txraddress : out std_logic_vector(4 downto 0);
txwrite : out std_logic;
txwdata : out std_logic_vector(31 downto 0);
txwaddress : out std_logic_vector(4 downto 0);
txrdata : in std_logic_vector(31 downto 0);
ncrenable : out std_logic;
ncraddress : out std_logic_vector(5 downto 0);
ncwrite : out std_logic;
ncwdata : out std_logic_vector(8 downto 0);
ncwaddress : out std_logic_vector(5 downto 0);
ncrdata : in std_logic_vector(8 downto 0);
rmrenable : out std_logic;
rmraddress : out std_logic_vector(7 downto 0);
rmwrite : out std_logic;
rmwdata : out std_logic_vector(7 downto 0);
rmwaddress : out std_logic_vector(7 downto 0);
rmrdata : in std_logic_vector(7 downto 0);
linkdis : out std_logic;
testclk : in std_logic;
testrst : in std_logic;
testen : in std_logic);
end component;
component grspwc_axcelerator_16_16_rmap0_crc0 is
port(
rst : in std_logic;
clk : in std_logic;
txclk : in std_logic;
hgrant : in std_logic;
hready : in std_logic;
hresp : in std_logic_vector (1 downto 0);
hrdata : in std_logic_vector (31 downto 0);
hbusreq : out std_logic;
hlock : out std_logic;
htrans : out std_logic_vector (1 downto 0);
haddr : out std_logic_vector (31 downto 0);
hwrite : out std_logic;
hsize : out std_logic_vector (2 downto 0);
hburst : out std_logic_vector (2 downto 0);
hprot : out std_logic_vector (3 downto 0);
hwdata : out std_logic_vector (31 downto 0);
psel : in std_logic;
penable : in std_logic;
paddr : in std_logic_vector (31 downto 0);
pwrite : in std_logic;
pwdata : in std_logic_vector (31 downto 0);
prdata : out std_logic_vector (31 downto 0);
di : in std_logic_vector(1 downto 0);
si : in std_logic_vector(1 downto 0);
do : out std_logic_vector(1 downto 0);
so : out std_logic_vector(1 downto 0);
tickin : in std_logic;
tickout : out std_logic;
irq : out std_logic;
clkdiv10 : in std_logic_vector (7 downto 0);
dcrstval : in std_logic_vector (9 downto 0);
timerrstval : in std_logic_vector (11 downto 0);
rmapen : in std_logic;
rxclki : in std_logic_vector(1 downto 0);
nrxclki : in std_logic_vector(1 downto 0);
rxclko : out std_logic_vector(1 downto 0);
rxrenable : out std_logic;
rxraddress : out std_logic_vector (4 downto 0);
rxwrite : out std_logic;
rxwdata : out std_logic_vector (31 downto 0);
rxwaddress : out std_logic_vector (4 downto 0);
rxrdata : in std_logic_vector (31 downto 0);
txrenable : out std_logic;
txraddress : out std_logic_vector (4 downto 0);
txwrite : out std_logic;
txwdata : out std_logic_vector (31 downto 0);
txwaddress : out std_logic_vector (4 downto 0);
txrdata : in std_logic_vector (31 downto 0);
ncrenable : out std_logic;
ncraddress : out std_logic_vector (5 downto 0);
ncwrite : out std_logic;
ncwdata : out std_logic_vector (8 downto 0);
ncwaddress : out std_logic_vector (5 downto 0);
ncrdata : in std_logic_vector (8 downto 0);
rmrenable : out std_logic;
rmraddress : out std_logic_vector (7 downto 0);
rmwrite : out std_logic;
rmwdata : out std_logic_vector (7 downto 0);
rmwaddress : out std_logic_vector (7 downto 0);
rmrdata : in std_logic_vector (7 downto 0);
linkdis : out std_logic;
testclk : in std_logic;
testrst : in std_logic;
testen : in std_logic);
end component;
begin
hlock <= '0';
f16_16_crc1 : if (rmapcrc = 1) and (rmap = 0) and (fifosize1 = 16) and (fifosize2 = 16) generate
grspwc0 : grspwc_axcelerator_16_16_rmap0_crc1
port map(
rst => rst,
clk => clk,
txclk => txclk,
--ahb mst in
hgrant => hgrant,
hready => hready,
hresp => hresp,
hrdata => hrdata,
--ahb mst out
hbusreq => hbusreq,
hlock => open, --hlock,
htrans => htrans,
haddr => haddr,
hwrite => hwrite,
hsize => hsize,
hburst => hburst,
hprot => hprot,
hwdata => hwdata,
--apb slv in
psel => psel,
penable => penable,
paddr => paddr,
pwrite => pwrite,
pwdata => pwdata,
--apb slv out
prdata => prdata,
--spw in
di => di,
si => si,
--spw out
do => do,
so => so,
--time iface
tickin => tickin,
tickout => tickout,
--clk bufs
rxclki => rxclki,
nrxclki => nrxclki,
rxclko => rxclko,
--irq
irq => irq,
--misc
clkdiv10 => clkdiv10,
dcrstval => dcrstval,
timerrstval => timerrstval,
--rmapen
rmapen => rmapen,
--rx ahb fifo
rxrenable => rxrenable,
rxraddress => rxraddress,
rxwrite => rxwrite,
rxwdata => rxwdata,
rxwaddress => rxwaddress,
rxrdata => rxrdata,
--tx ahb fifo
txrenable => txrenable,
txraddress => txraddress,
txwrite => txwrite,
txwdata => txwdata,
txwaddress => txwaddress,
txrdata => txrdata,
--nchar fifo
ncrenable => ncrenable,
ncraddress => ncraddress,
ncwrite => ncwrite,
ncwdata => ncwdata,
ncwaddress => ncwaddress,
ncrdata => ncrdata,
--rmap buf
rmrenable => rmrenable,
rmraddress => rmraddress,
rmwrite => rmwrite,
rmwdata => rmwdata,
rmwaddress => rmwaddress,
rmrdata => rmrdata,
linkdis => linkdis,
testclk => testclk,
testrst => testrst,
testen => testen
);
end generate;
f16_16_rmap8_crc1 : if (rmapcrc = 1) and (rmap = 1) and (rmapbufs = 8) and (fifosize1 = 16) and (fifosize2 = 16) generate
grspwc0 : grspwc_axcelerator_16_16_rmap8_crc1
port map(
rst => rst,
clk => clk,
txclk => txclk,
--ahb mst in
hgrant => hgrant,
hready => hready,
hresp => hresp,
hrdata => hrdata,
--ahb mst out
hbusreq => hbusreq,
hlock => open, --hlock,
htrans => htrans,
haddr => haddr,
hwrite => hwrite,
hsize => hsize,
hburst => hburst,
hprot => hprot,
hwdata => hwdata,
--apb slv in
psel => psel,
penable => penable,
paddr => paddr,
pwrite => pwrite,
pwdata => pwdata,
--apb slv out
prdata => prdata,
--spw in
di => di,
si => si,
--spw out
do => do,
so => so,
--time iface
tickin => tickin,
tickout => tickout,
--clk bufs
rxclki => rxclki,
nrxclki => nrxclki,
rxclko => rxclko,
--irq
irq => irq,
--misc
clkdiv10 => clkdiv10,
dcrstval => dcrstval,
timerrstval => timerrstval,
--rmapen
rmapen => rmapen,
--rx ahb fifo
rxrenable => rxrenable,
rxraddress => rxraddress,
rxwrite => rxwrite,
rxwdata => rxwdata,
rxwaddress => rxwaddress,
rxrdata => rxrdata,
--tx ahb fifo
txrenable => txrenable,
txraddress => txraddress,
txwrite => txwrite,
txwdata => txwdata,
txwaddress => txwaddress,
txrdata => txrdata,
--nchar fifo
ncrenable => ncrenable,
ncraddress => ncraddress,
ncwrite => ncwrite,
ncwdata => ncwdata,
ncwaddress => ncwaddress,
ncrdata => ncrdata,
--rmap buf
rmrenable => rmrenable,
rmraddress => rmraddress,
rmwrite => rmwrite,
rmwdata => rmwdata,
rmwaddress => rmwaddress,
rmrdata => rmrdata,
linkdis => linkdis,
testclk => testclk,
testrst => testrst,
testen => testen
);
end generate;
f16_16_crc0 : if (rmapcrc = 0) and (rmap = 0) and (fifosize1 = 16) and (fifosize2 = 16) generate
grspwc0 : grspwc_axcelerator_16_16_rmap0_crc0
port map(
rst => rst,
clk => clk,
txclk => txclk,
--ahb mst in
hgrant => hgrant,
hready => hready,
hresp => hresp,
hrdata => hrdata,
--ahb mst out
hbusreq => hbusreq,
hlock => open, --hlock,
htrans => htrans,
haddr => haddr,
hwrite => hwrite,
hsize => hsize,
hburst => hburst,
hprot => hprot,
hwdata => hwdata,
--apb slv in
psel => psel,
penable => penable,
paddr => paddr,
pwrite => pwrite,
pwdata => pwdata,
--apb slv out
prdata => prdata,
--spw in
di => di,
si => si,
--spw out
do => do,
so => so,
--time iface
tickin => tickin,
tickout => tickout,
--clk bufs
rxclki => rxclki,
nrxclki => nrxclki,
rxclko => rxclko,
--irq
irq => irq,
--misc
clkdiv10 => clkdiv10,
dcrstval => dcrstval,
timerrstval => timerrstval,
--rmapen
rmapen => rmapen,
--rx ahb fifo
rxrenable => rxrenable,
rxraddress => rxraddress,
rxwrite => rxwrite,
rxwdata => rxwdata,
rxwaddress => rxwaddress,
rxrdata => rxrdata,
--tx ahb fifo
txrenable => txrenable,
txraddress => txraddress,
txwrite => txwrite,
txwdata => txwdata,
txwaddress => txwaddress,
txrdata => txrdata,
--nchar fifo
ncrenable => ncrenable,
ncraddress => ncraddress,
ncwrite => ncwrite,
ncwdata => ncwdata,
ncwaddress => ncwaddress,
ncrdata => ncrdata,
--rmap buf
rmrenable => rmrenable,
rmraddress => rmraddress,
rmwrite => rmwrite,
rmwdata => rmwdata,
rmwaddress => rmwaddress,
rmrdata => rmrdata,
linkdis => linkdis,
testclk => testclk,
testrst => testrst,
testen => testen
);
end generate;
end architecture;
|
mit
|
impedimentToProgress/UCI-BlueChip
|
AttackFiles/Attacks/privEsc/lib/gaisler/misc/i2cslv.in.vhd
|
5
|
283
|
-- I2C slave
constant CFG_I2CSLV_ENABLE : integer := CONFIG_I2CSLV_ENABLE;
constant CFG_I2CSLV_HARDADDR : integer := CONFIG_I2CSLV_HARDADDR;
constant CFG_I2CSLV_TENBIT : integer := CONFIG_I2CSLV_TENBIT;
constant CFG_I2CSLV_I2CADDR : integer := CONFIG_I2CSLV_I2CADDR;
|
mit
|
impedimentToProgress/UCI-BlueChip
|
AttackFiles/Attacks/memAttack/lib/gaisler/pci/pcipads.vhd
|
2
|
6990
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: pcipads
-- File: pcipads.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: PCI pads module
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
use work.pci.all;
library grlib;
use grlib.stdlib.all;
entity pcipads is
generic (
padtech : integer := 0;
noreset : integer := 0;
oepol : integer := 0;
host : integer := 1;
int : integer := 0
);
port (
pci_rst : in std_ulogic;
pci_gnt : in std_ulogic;
pci_idsel : in std_ulogic;
pci_lock : inout std_ulogic;
pci_ad : inout std_logic_vector(31 downto 0);
pci_cbe : inout std_logic_vector(3 downto 0);
pci_frame : inout std_ulogic;
pci_irdy : inout std_ulogic;
pci_trdy : inout std_ulogic;
pci_devsel : inout std_ulogic;
pci_stop : inout std_ulogic;
pci_perr : inout std_ulogic;
pci_par : inout std_ulogic;
pci_req : inout std_ulogic; -- tristate pad but never read
pci_serr : inout std_ulogic; -- open drain output
pci_host : in std_ulogic;
pci_66 : in std_ulogic;
pcii : out pci_in_type;
pcio : in pci_out_type;
pci_int : inout std_logic_vector(3 downto 0) := conv_std_logic_vector(16#F#, 4) -- Disable int by default
--pci_int : inout std_logic_vector(3 downto 0) :=
-- conv_std_logic_vector(16#F# - (16#F# * oepol), 4) -- Disable int by default
);
end;
architecture rtl of pcipads is
signal vcc : std_ulogic;
begin
vcc <= '1';
norst : if noreset = 0 generate
pad_pci_rst : inpad generic map (padtech, pci33, 0) port map (pci_rst, pcii.rst);
end generate;
dorst : if noreset = 1 generate
pcii.rst <= pci_rst;
end generate;
pad_pci_gnt : inpad generic map (padtech, pci33, 0) port map (pci_gnt, pcii.gnt);
pad_pci_idsel : inpad generic map (padtech, pci33, 0) port map (pci_idsel, pcii.idsel);
dohost : if host = 1 generate
pad_pci_host : inpad generic map (padtech, pci33, 0) port map (pci_host, pcii.host);
end generate;
nohost : if host = 0 generate
pcii.host <= '1'; -- disable pci host functionality
end generate;
pad_pci_66 : inpad generic map (padtech, pci33, 0) port map (pci_66, pcii.pci66);
pad_pci_lock : iopad generic map (tech => padtech, level => pci33, oepol => oepol)
port map (pci_lock, pcio.lock, pcio.locken, pcii.lock);
pad_pci_ad : iopadvv generic map (tech => padtech, level => pci33, width => 32,
oepol => oepol)
port map (pci_ad, pcio.ad, pcio.vaden, pcii.ad);
pad_pci_cbe0 : iopad generic map (tech => padtech, level => pci33, oepol => oepol)
port map (pci_cbe(0), pcio.cbe(0), pcio.cbeen(0), pcii.cbe(0));
pad_pci_cbe1 : iopad generic map (tech => padtech, level => pci33, oepol => oepol)
port map (pci_cbe(1), pcio.cbe(1), pcio.cbeen(1), pcii.cbe(1));
pad_pci_cbe2 : iopad generic map (tech => padtech, level => pci33, oepol => oepol)
port map (pci_cbe(2), pcio.cbe(2), pcio.cbeen(2), pcii.cbe(2));
pad_pci_cbe3 : iopad generic map (tech => padtech, level => pci33, oepol => oepol)
port map (pci_cbe(3), pcio.cbe(3), pcio.cbeen(3), pcii.cbe(3));
pad_pci_frame : iopad generic map (tech => padtech, level => pci33, oepol => oepol)
port map (pci_frame, pcio.frame, pcio.frameen, pcii.frame);
pad_pci_trdy : iopad generic map (tech => padtech, level => pci33, oepol => oepol)
port map (pci_trdy, pcio.trdy, pcio.trdyen, pcii.trdy);
pad_pci_irdy : iopad generic map (tech => padtech, level => pci33, oepol => oepol)
port map (pci_irdy, pcio.irdy, pcio.irdyen, pcii.irdy);
pad_pci_devsel: iopad generic map (tech => padtech, level => pci33, oepol => oepol)
port map (pci_devsel, pcio.devsel, pcio.devselen, pcii.devsel);
pad_pci_stop : iopad generic map (tech => padtech, level => pci33, oepol => oepol)
port map (pci_stop, pcio.stop, pcio.stopen, pcii.stop);
pad_pci_perr : iopad generic map (tech => padtech, level => pci33, oepol => oepol)
port map (pci_perr, pcio.perr, pcio.perren, pcii.perr);
pad_pci_par : iopad generic map (tech => padtech, level => pci33, oepol => oepol)
port map (pci_par, pcio.par, pcio.paren, pcii.par);
pad_pci_req : toutpad generic map (tech => padtech, level => pci33, oepol => oepol)
port map (pci_req, pcio.req, pcio.reqen);
pad_pci_serr : iopad generic map (tech => padtech, level => pci33, oepol => oepol)
port map (pci_serr, pcio.serr, pcio.serren, pcii.serr);
-- PCI interrupt pads
-- int = 0 => no interrupt
-- int = 1 => PCI_INT[A] = out, PCI_INT[B,C,D] = Not connected
-- int = 2 => PCI_INT[B] = out, PCI_INT[A,C,D] = Not connected
-- int = 3 => PCI_INT[C] = out, PCI_INT[A,B,D] = Not connected
-- int = 4 => PCI_INT[D] = out, PCI_INT[A,B,C] = Not connected
-- int = 10 => PCI_INT[A] = inout, PCI_INT[B,C,D] = in
-- int = 11 => PCI_INT[B] = inout, PCI_INT[A,C,D] = in
-- int = 12 => PCI_INT[C] = inout, PCI_INT[A,B,D] = in
-- int = 13 => PCI_INT[D] = inout, PCI_INT[A,B,C] = in
-- int > 13 => PCI_INT[A,B,C,D] = in
interrupt : if int /= 0 generate
x : for i in 0 to 3 generate
xo : if i = int - 1 and int < 10 generate
pad_pci_int : odpad generic map (tech => padtech, level => pci33, oepol => oepol)
port map (pci_int(i), pcio.inten);
end generate;
xio : if i = (int - 10) and int >= 10 generate
pad_pci_int : iodpad generic map (tech => padtech, level => pci33, oepol => oepol)
port map (pci_int(i), pcio.inten, pcii.int(i));
end generate;
xi : if i /= (int - 10) and int >= 10 generate
pad_pci_int : inpad generic map (tech => padtech, level => pci33)
port map (pci_int(i), pcii.int(i));
end generate;
end generate;
end generate;
end;
|
mit
|
impedimentToProgress/UCI-BlueChip
|
AttackFiles/Attacks/privEsc/lib/eth/core/greth_tx.vhd
|
2
|
16396
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: greth_tx
-- File: greth_tx.vhd
-- Author: Marko Isomaki
-- Description: Ethernet transmitter
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library eth;
use eth.grethpkg.all;
entity greth_tx is
generic(
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
nsync : integer range 1 to 2 := 2;
rmii : integer range 0 to 1 := 0);
port(
rst : in std_ulogic;
clk : in std_ulogic;
txi : in host_tx_type;
txo : out tx_host_type
);
end entity;
architecture rtl of greth_tx is
function mirror2(din : in std_logic_vector(3 downto 0))
return std_logic_vector is
variable do : std_logic_vector(3 downto 0);
begin
do(3) := din(0); do(2) := din(1);
do(1) := din(2); do(0) := din(3);
return do;
end function;
function init_ifg(
ifg_gap : in integer;
rmii : in integer)
return integer is
begin
if rmii = 0 then
return log2(ifg_gap);
else
return log2(ifg_gap*20);
end if;
end function;
constant maxattempts : std_logic_vector(4 downto 0) :=
conv_std_logic_vector(attempt_limit, 5);
--transmitter constants
constant ifg_bits : integer := init_ifg(ifg_gap, rmii);
constant ifg_p1 : std_logic_vector(ifg_bits-1 downto 0) :=
conv_std_logic_vector((ifg_gap)/3, ifg_bits);
constant ifg_p2 : std_logic_vector(ifg_bits-1 downto 0) :=
conv_std_logic_vector((ifg_gap*2)/3, ifg_bits);
constant ifg_p1_r100 : std_logic_vector(ifg_bits-1 downto 0) :=
conv_std_logic_vector((ifg_gap*2)/3, ifg_bits);
constant ifg_p2_r100 : std_logic_vector(ifg_bits-1 downto 0) :=
conv_std_logic_vector(rmii*(ifg_gap*4)/3, ifg_bits);
constant ifg_p1_r10 : std_logic_vector(ifg_bits-1 downto 0) :=
conv_std_logic_vector(rmii*(ifg_gap*20)/3, ifg_bits);
constant ifg_p2_r10 : std_logic_vector(ifg_bits-1 downto 0) :=
conv_std_logic_vector(rmii*(ifg_gap*40)/3, ifg_bits);
function ifg_sel(
rmii : in integer;
p1 : in integer;
speed : in std_ulogic)
return std_logic_vector is
begin
if p1 = 1 then
if rmii = 0 then
return ifg_p1;
else
if speed = '1' then
return ifg_p1_r100;
else
return ifg_p1_r10;
end if;
end if;
else
if rmii = 0 then
return ifg_p2;
else
if speed = '1' then
return ifg_p2_r100;
else
return ifg_p2_r10;
end if;
end if;
end if;
end function;
--transmitter types
type tx_state_type is (idle, preamble, sfd, data1, data2, pad1, pad2, fcs,
fcs2, finish, calc_backoff, wait_backoff, send_jam, send_jam2,
check_attempts);
type def_state_type is (monitor, def_on, ifg1, ifg2, frame_waitingst);
type tx_reg_type is record
--deference process
def_state : def_state_type;
ifg_cycls : std_logic_vector(ifg_bits-1 downto 0);
deferring : std_ulogic;
was_transmitting : std_ulogic;
--tx process
main_state : tx_state_type;
transmitting : std_ulogic;
tx_en : std_ulogic;
txd : std_logic_vector(3 downto 0);
cnt : std_logic_vector(3 downto 0);
icnt : std_logic_vector(1 downto 0);
crc : std_logic_vector(31 downto 0);
crc_en : std_ulogic;
byte_count : std_logic_vector(10 downto 0);
slot_count : std_logic_vector(6 downto 0);
random : std_logic_vector(9 downto 0);
delay_val : std_logic_vector(9 downto 0);
retry_cnt : std_logic_vector(4 downto 0);
status : std_logic_vector(1 downto 0);
data : std_logic_vector(31 downto 0);
--synchronization
read : std_ulogic;
done : std_ulogic;
restart : std_ulogic;
start : std_logic_vector(nsync downto 0);
read_ack : std_logic_vector(nsync-1 downto 0);
crs : std_logic_vector(1 downto 0);
col : std_logic_vector(1 downto 0);
fullduplex : std_logic_vector(1 downto 0);
--rmii
crs_act : std_ulogic;
crs_prev : std_ulogic;
speed : std_logic_vector(1 downto 0);
rcnt : std_logic_vector(3 downto 0);
switch : std_ulogic;
txd_msb : std_logic_vector(1 downto 0);
zero : std_ulogic;
rmii_crc_en : std_ulogic;
end record;
--transmitter signals
signal r, rin : tx_reg_type;
signal txrst : std_ulogic;
signal vcc : std_ulogic;
attribute sync_set_reset : string;
attribute sync_set_reset of txrst : signal is "true";
begin
vcc <= '1';
tx_rst : eth_rstgen
port map(rst, clk, vcc, txrst, open);
tx : process(txrst, r, txi) is
variable collision : std_ulogic;
variable frame_waiting : std_ulogic;
variable index : integer range 0 to 7;
variable start : std_ulogic;
variable read_ack : std_ulogic;
variable v : tx_reg_type;
variable crs : std_ulogic;
variable col : std_ulogic;
variable tx_done : std_ulogic;
begin
v := r; frame_waiting := '0'; tx_done := '0'; v.rmii_crc_en := '0';
--synchronization
v.col(1) := r.col(0); v.col(0) := txi.rx_col;
v.crs(1) := r.crs(0); v.crs(0) := txi.rx_crs;
v.fullduplex(0) := txi.full_duplex;
v.fullduplex(1) := r.fullduplex(0);
v.start(0) := txi.start;
v.read_ack(0) := txi.readack;
if nsync = 2 then
v.start(1) := r.start(0);
v.read_ack(1) := r.read_ack(0);
end if;
start := r.start(nsync) xor r.start(nsync-1);
read_ack := not (r.read xor r.read_ack(nsync-1));
--crc generation
if (r.crc_en = '1') and ((rmii = 0) or (r.rmii_crc_en = '1')) then
v.crc := calccrc(r.txd, r.crc);
end if;
--rmii
if rmii = 0 then
col := r.col(1); crs := r.crs(1);
tx_done := '1';
else
v.crs_prev := r.crs(1);
if (r.crs(0) and not r.crs_act) = '1' then
v.crs_act := '1';
end if;
if (r.crs(1) or r.crs(0)) = '0' then
v.crs_act := '0';
end if;
crs := r.crs(1) and not ((not r.crs_prev) and r.crs_act);
col := crs and r.tx_en;
v.speed(1) := r.speed(0); v.speed(0) := txi.speed;
if r.tx_en = '1' then
v.rcnt := r.rcnt - 1;
if r.speed(1) = '1' then
v.switch := not r.switch;
if r.switch = '1' then
tx_done := '1'; v.rmii_crc_en := '1';
end if;
if r.switch = '0' then
v.txd(1 downto 0) := r.txd_msb;
end if;
else
v.zero := '0';
if r.rcnt = "0001" then
v.zero := '1';
end if;
if r.zero = '1' then
v.switch := not r.switch;
v.rcnt := "1001";
if r.switch = '0' then
v.txd(1 downto 0) := r.txd_msb;
end if;
end if;
if (r.switch and r.zero) = '1' then
tx_done := '1'; v.rmii_crc_en := '1';
end if;
end if;
end if;
end if;
collision := col and not r.fullduplex(1);
--main fsm
case r.main_state is
when idle =>
v.transmitting := '0';
if rmii = 1 then
v.rcnt := "1001"; v.switch := '0';
end if;
if (start and not r.deferring) = '1' then
v.main_state := preamble; v.transmitting := '1'; v.tx_en := '1';
v.byte_count := (others => '1'); v.status := (others => '0');
v.read := not r.read; v.start(nsync) := r.start(nsync-1);
elsif start = '1' then
frame_waiting := '1';
end if;
v.txd := "0101"; v.cnt := "1110";
when preamble =>
if tx_done = '1' then
v.cnt := r.cnt - 1;
if r.cnt = "0000" then
v.txd := "1101"; v.main_state := sfd;
end if;
if collision = '1' then v.main_state := send_jam; end if;
end if;
when sfd =>
if tx_done = '1' then
v.main_state := data1; v.icnt := (others => '0'); v.crc_en := '1';
v.crc := (others => '1'); v.byte_count := (others => '0');
v.txd := txi.data(27 downto 24);
if (read_ack and txi.valid) = '0' then
v.status(0) := '1'; v.main_state := finish; v.tx_en := '0';
else
v.data := txi.data; v.read := not r.read;
end if;
if collision = '1' then v.main_state := send_jam; end if;
end if;
when data1 =>
index := conv_integer(r.icnt);
if tx_done = '1' then
v.byte_count := r.byte_count + 1;
v.main_state := data2; v.icnt := r.icnt + 1;
case index is
when 0 => v.txd := r.data(31 downto 28);
when 1 => v.txd := r.data(23 downto 20);
when 2 => v.txd := r.data(15 downto 12);
when 3 => v.txd := r.data(7 downto 4);
when others => null;
end case;
if v.byte_count = txi.len then
v.tx_en := '1';
if conv_integer(v.byte_count) >= 60 then
v.main_state := fcs; v.cnt := (others => '0');
else
v.main_state := pad1;
end if;
elsif index = 3 then
if (read_ack and txi.valid) = '0' then
v.status(0) := '1'; v.main_state := finish; v.tx_en := '0';
else
v.data := txi.data; v.read := not r.read;
end if;
end if;
if collision = '1' then v.main_state := send_jam; end if;
end if;
when data2 =>
index := conv_integer(r.icnt);
if tx_done = '1' then
v.main_state := data1;
case index is
when 0 => v.txd := r.data(27 downto 24);
when 1 => v.txd := r.data(19 downto 16);
when 2 => v.txd := r.data(11 downto 8);
when 3 => v.txd := r.data(3 downto 0);
when others => null;
end case;
if collision = '1' then v.main_state := send_jam; end if;
end if;
when pad1 =>
if tx_done = '1' then
v.main_state := pad2;
if collision = '1' then v.main_state := send_jam; end if;
end if;
when pad2 =>
if tx_done = '1' then
v.byte_count := r.byte_count + 1;
if conv_integer(v.byte_count) = 60 then
v.main_state := fcs; v.cnt := (others => '0');
else
v.main_state := pad1;
end if;
if collision = '1' then v.main_state := send_jam; end if;
end if;
when fcs =>
if tx_done = '1' then
v.cnt := r.cnt + 1; v.crc_en := '0'; index := conv_integer(r.cnt);
case index is
when 0 => v.txd := mirror2(not v.crc(31 downto 28));
when 1 => v.txd := mirror2(not r.crc(27 downto 24));
when 2 => v.txd := mirror2(not r.crc(23 downto 20));
when 3 => v.txd := mirror2(not r.crc(19 downto 16));
when 4 => v.txd := mirror2(not r.crc(15 downto 12));
when 5 => v.txd := mirror2(not r.crc(11 downto 8));
when 6 => v.txd := mirror2(not r.crc(7 downto 4));
when 7 => v.txd := mirror2(not r.crc(3 downto 0));
v.main_state := fcs2;
when others => null;
end case;
end if;
when fcs2 =>
if tx_done = '1' then
v.main_state := finish; v.tx_en := '0';
end if;
when finish =>
v.tx_en := '0'; v.transmitting := '0'; v.main_state := idle;
v.retry_cnt := (others => '0'); v.done := not r.done;
when send_jam =>
if tx_done = '1' then
v.cnt := "0110"; v.main_state := send_jam2; v.crc_en := '0';
end if;
when send_jam2 =>
if tx_done = '1' then
v.cnt := r.cnt - 1;
if r.cnt = "0000" then
v.main_state := check_attempts; v.retry_cnt := r.retry_cnt + 1;
v.tx_en := '0';
end if;
end if;
when check_attempts =>
v.transmitting := '0';
if r.retry_cnt = maxattempts then
v.main_state := finish; v.status(1) := '1';
else
v.main_state := calc_backoff; v.restart := not r.restart;
end if;
v.tx_en := '0';
when calc_backoff =>
v.delay_val := (others => '0');
for i in 1 to backoff_limit-1 loop
if i < conv_integer(r.retry_cnt)+1 then
v.delay_val(i) := r.random(i);
end if;
end loop;
v.main_state := wait_backoff; v.slot_count := (others => '1');
when wait_backoff =>
if conv_integer(r.delay_val) = 0 then
v.main_state := idle;
end if;
v.slot_count := r.slot_count - 1;
if conv_integer(r.slot_count) = 0 then
v.slot_count := (others => '1'); v.delay_val := r.delay_val - 1;
end if;
when others =>
v.main_state := idle;
end case;
--random values;
v.random := r.random(8 downto 0) & (not (r.random(2) xor r.random(9)));
--deference
case r.def_state is
when monitor =>
v.was_transmitting := '0';
if ( (crs and not r.fullduplex(1)) or
(r.transmitting and r.fullduplex(1)) ) = '1' then
v.deferring := '1'; v.def_state := def_on;
v.was_transmitting := r.transmitting;
end if;
when def_on =>
v.was_transmitting := r.was_transmitting or r.transmitting;
if r.fullduplex(1) = '1' then
if r.transmitting = '0' then v.def_state := ifg1; end if;
v.ifg_cycls := ifg_sel(rmii, 1, r.speed(1));
else
if (r.transmitting or crs) = '0' then
v.def_state := ifg1; v.ifg_cycls := ifg_sel(rmii, 1, r.speed(1));
end if;
end if;
when ifg1 =>
v.ifg_cycls := r.ifg_cycls - 1;
if r.ifg_cycls = zero32(ifg_bits-1 downto 0) then
v.def_state := ifg2;
v.ifg_cycls := ifg_sel(rmii, 0, r.speed(1));
elsif (crs and not r.fullduplex(1)) = '1' then
v.ifg_cycls := ifg_sel(rmii, 1, r.speed(1));
end if;
when ifg2 =>
v.ifg_cycls := r.ifg_cycls - 1;
if r.ifg_cycls = zero32(ifg_bits-1 downto 0) then
v.deferring := '0';
if (r.fullduplex(1) or not frame_waiting) = '1' then
v.def_state := monitor;
elsif frame_waiting = '1' then
v.def_state := frame_waitingst;
end if;
end if;
when frame_waitingst =>
if frame_waiting = '0' then v.def_state := monitor; end if;
when others => v.def_state := monitor;
end case;
if rmii = 1 then
v.txd_msb := v.txd(3 downto 2);
end if;
if txrst = '0' then
v.main_state := idle; v.random := (others => '0');
v.def_state := monitor; v.deferring := '0'; v.tx_en := '0';
v.done := '0'; v.restart := '0'; v.read := '0';
v.start := (others => '0'); v.read_ack := (others => '0');
v.icnt := (others => '0'); v.delay_val := (others => '0');
v.ifg_cycls := (others => '0');
if rmii = 1 then
v.crs_act := '0';
end if;
end if;
rin <= v;
txo.tx_er <= '0';
txo.tx_en <= r.tx_en;
txo.txd <= r.txd;
txo.done <= r.done;
txo.read <= r.read;
txo.restart <= r.restart;
txo.status <= r.status;
end process;
txregs : process(clk) is
begin
if rising_edge(clk) then r <= rin; end if;
end process;
end architecture;
|
mit
|
impedimentToProgress/UCI-BlueChip
|
AttackFiles/Attacks/memAttack/lib/gaisler/memctrl/sdmctrl.vhd
|
2
|
18379
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: sdmctrl
-- File: sdmctrl.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: SDRAM memory controller to fit with LEON2 memory controller.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.memctrl.all;
entity sdmctrl is
generic (
pindex : integer := 0;
invclk : integer := 0;
fast : integer := 0;
wprot : integer := 0;
sdbits : integer := 32;
pageburst : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
sdi : in sdram_in_type;
sdo : out sdram_out_type;
apbi : in apb_slv_in_type;
wpo : in wprot_out_type;
sdmo : out sdram_mctrl_out_type
);
end;
architecture rtl of sdmctrl is
constant WPROTEN : boolean := (wprot /= 0);
constant SDINVCLK : boolean := (invclk /= 0);
constant BUS64 : boolean := (sdbits = 64);
type mcycletype is (midle, active, leadout);
type sdcycletype is (act1, act2, act3, rd1, rd2, rd3, rd4, rd5, rd6, rd7, rd8,
wr1, wr2, wr3, wr4, wr5, sidle);
type icycletype is (iidle, pre, ref, lmode, finish);
-- sdram configuration register
type sdram_cfg_type is record
command : std_logic_vector(1 downto 0);
csize : std_logic_vector(1 downto 0);
bsize : std_logic_vector(2 downto 0);
casdel : std_ulogic; -- CAS to data delay: 2/3 clock cycles
trfc : std_logic_vector(2 downto 0);
trp : std_ulogic; -- precharge to activate: 2/3 clock cycles
refresh : std_logic_vector(14 downto 0);
renable : std_ulogic;
pageburst : std_ulogic;
end record;
-- local registers
type reg_type is record
hready : std_ulogic;
hsel : std_ulogic;
bdrive : std_ulogic;
burst : std_ulogic;
busy : std_ulogic;
bdelay : std_ulogic;
wprothit : std_ulogic;
startsd : std_ulogic;
aload : std_ulogic;
mstate : mcycletype;
sdstate : sdcycletype;
cmstate : mcycletype;
istate : icycletype;
icnt : std_logic_vector(2 downto 0);
cfg : sdram_cfg_type;
trfc : std_logic_vector(2 downto 0);
refresh : std_logic_vector(14 downto 0);
sdcsn : std_logic_vector(1 downto 0);
sdwen : std_ulogic;
rasn : std_ulogic;
casn : std_ulogic;
dqm : std_logic_vector(7 downto 0);
bsel : std_ulogic;
haddr : std_logic_vector(31 downto 10);
-- only needed to keep address lines from switch too much
address : std_logic_vector(16 downto 2); -- memory address
end record;
signal r, ri : reg_type;
begin
ctrl : process(rst, apbi, sdi, wpo, r)
variable v : reg_type; -- local variables for registers
variable startsd : std_ulogic;
variable dataout : std_logic_vector(31 downto 0); -- data from memory
variable haddr : std_logic_vector(31 downto 0);
variable regsd : std_logic_vector(31 downto 0); -- data from registers
variable dqm : std_logic_vector(7 downto 0);
variable raddr : std_logic_vector(12 downto 0);
variable adec : std_ulogic;
variable busy : std_ulogic;
variable aload : std_ulogic;
variable rams : std_logic_vector(1 downto 0);
variable hresp : std_logic_vector(1 downto 0);
variable ba : std_logic_vector(1 downto 0);
variable lline : std_logic_vector(2 downto 0);
variable rline : std_logic_vector(2 downto 0);
variable lineburst : boolean;
begin
-- Variable default settings to avoid latches
v := r; startsd := '0'; v.busy := '0'; hresp := HRESP_OKAY;
lline := not r.cfg.casdel & r.cfg.casdel & r.cfg.casdel;
rline := not r.cfg.casdel & r.cfg.casdel & r.cfg.casdel;
if sdi.hready = '1' then v.hsel := sdi.hsel; end if;
if (sdi.hready and sdi.hsel ) = '1' then
if sdi.htrans(1) = '1' then v.hready := '0'; end if;
end if;
if fast = 1 then haddr := sdi.rhaddr; else haddr := sdi.haddr; end if;
if (pageburst = 0) or ((pageburst = 2) and r.cfg.pageburst = '0') then
lineburst := true;
else lineburst := false; end if;
-- main state
case sdi.hsize is
when "00" =>
case sdi.rhaddr(1 downto 0) is
when "00" => dqm := "11110111";
when "01" => dqm := "11111011";
when "10" => dqm := "11111101";
when others => dqm := "11111110";
end case;
when "01" =>
if sdi.rhaddr(1) = '0' then dqm := "11110011"; else dqm := "11111100"; end if;
when others => dqm := "11110000";
end case;
if BUS64 and (r.bsel = '1') then
dqm := dqm(3 downto 0) & "1111";
end if;
-- main FSM
case r.mstate is
when midle =>
if (v.hsel and sdi.nhtrans(1)) = '1' then
if (r.sdstate = sidle) and (r.cfg.command = "00") and
(r.cmstate = midle) and (sdi.idle = '1')
then
if fast = 1 then v.startsd := '1'; else startsd := '1'; end if;
v.mstate := active;
end if;
end if;
when others => null;
end case;
startsd := r.startsd or startsd;
-- generate row and column address size
case r.cfg.csize is
when "00" => raddr := haddr(22 downto 10);
when "01" => raddr := haddr(23 downto 11);
when "10" => raddr := haddr(24 downto 12);
when others =>
if r.cfg.bsize = "111" then raddr := haddr(26 downto 14);
else raddr := haddr(25 downto 13); end if;
end case;
-- generate bank address
ba := genmux(r.cfg.bsize, haddr(28 downto 21)) &
genmux(r.cfg.bsize, haddr(27 downto 20));
-- generate chip select
if BUS64 then
adec := genmux(r.cfg.bsize, haddr(30 downto 23));
v.bsel := genmux(r.cfg.bsize, sdi.rhaddr(29 downto 22));
else
adec := genmux(r.cfg.bsize, haddr(29 downto 22)); v.bsel := '0';
end if;
if (sdi.srdis = '0') and (r.cfg.bsize = "111") then adec := not adec; end if;
rams := adec & not adec;
if r.trfc /= "000" then v.trfc := r.trfc - 1; end if;
-- sdram access FSM
case r.sdstate is
when sidle =>
v.bdelay := '0';
if (startsd = '1') and (r.cfg.command = "00") and (r.cmstate = midle) then
v.address(16 downto 2) := ba & raddr;
v.sdcsn := not rams(1 downto 0); v.rasn := '0'; v.sdstate := act1;
v.startsd := '0';
end if;
when act1 =>
v.rasn := '1'; v.trfc := r.cfg.trfc; v.haddr := sdi.rhaddr(31 downto 10);
if r.cfg.casdel = '1' then v.sdstate := act2; else
v.sdstate := act3;
v.hready := sdi.hwrite and sdi.htrans(0) and sdi.htrans(1);
end if;
if WPROTEN then
v.wprothit := wpo.wprothit;
if wpo.wprothit = '1' then hresp := HRESP_ERROR; end if;
end if;
when act2 =>
v.sdstate := act3;
v.hready := sdi.hwrite and sdi.htrans(0) and sdi.htrans(1);
if WPROTEN and (r.wprothit = '1') then
hresp := HRESP_ERROR; v.hready := '0';
end if;
when act3 =>
v.casn := '0';
v.address(14 downto 2) := sdi.rhaddr(13 downto 12) & '0' & sdi.rhaddr(11 downto 2);
v.dqm := dqm; v.burst := r.hready;
if sdi.hwrite = '1' then
v.sdstate := wr1; v.sdwen := '0'; v.bdrive := '1';
if sdi.htrans = "11" or (r.hready = '0') then v.hready := '1'; end if;
if WPROTEN and (r.wprothit = '1') then
hresp := HRESP_ERROR; v.hready := '1';
v.sdstate := wr1; v.sdwen := '1'; v.bdrive := '0'; v.casn := '1';
end if;
else v.sdstate := rd1; end if;
when wr1 =>
v.address(14 downto 2) := sdi.rhaddr(13 downto 12) & '0' & sdi.rhaddr(11 downto 2);
if (((r.burst and r.hready) = '1') and (sdi.rhtrans = "11"))
and not (WPROTEN and (r.wprothit = '1'))
then
v.hready := sdi.htrans(0) and sdi.htrans(1) and r.hready;
if ((sdi.rhaddr(5 downto 2) = "1111") and (r.cfg.command = "10")) then -- exit on refresh
v.hready := '0';
end if;
else
v.sdstate := wr2; v.bdrive := '0'; v.casn := '1'; v.sdwen := '1';
v.dqm := (others => '1');
end if;
when wr2 =>
if (sdi.rhtrans = "10") and (sdi.rhaddr(31 downto 10) = r.haddr) and (r.hsel = '1') then
if sdi.hwrite = '1' then v.hready := '1'; end if; v.sdstate := act3;
elsif (r.trfc(2 downto 1) = "00") then
if (r.cfg.trp = '0') then v.rasn := '0'; v.sdwen := '0'; end if;
v.sdstate := wr3;
end if;
when wr3 =>
if (sdi.rhtrans = "10") and (sdi.rhaddr(31 downto 10) = r.haddr) and (r.sdwen = '1') and (r.hsel = '1') then
if sdi.hwrite = '1' then v.hready := '1'; end if; v.sdstate := act3;
elsif (r.cfg.trp = '1') then
v.rasn := '0'; v.sdwen := '0'; v.sdstate := wr4;
else
v.sdcsn := "11"; v.rasn := '1'; v.sdwen := '1';
if r.trfc = "000" then v.sdstate := sidle; end if;
end if;
when wr4 =>
v.sdcsn := "11"; v.rasn := '1'; v.sdwen := '1';
if (r.cfg.trp = '1') then v.sdstate := wr5;
else
if r.trfc = "000" then v.sdstate := sidle; end if;
end if;
when wr5 =>
if r.trfc = "000" then v.sdstate := sidle; end if;
when rd1 =>
v.casn := '1'; v.sdstate := rd7;
if lineburst and (sdi.htrans = "11") then
if sdi.rhaddr(4 downto 2) = "111" then
v.address(9 downto 5) := r.address(9 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
when rd7 =>
v.casn := '1';
if r.cfg.casdel = '1' then
v.sdstate := rd2;
if lineburst and (sdi.htrans = "11") then
if sdi.rhaddr(4 downto 2) = "110" then
v.address(9 downto 5) := r.address(9 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
else
v.sdstate := rd3;
if sdi.htrans /= "11" then
if (r.trfc(2 downto 1) = "00") then v.rasn := '0'; v.sdwen := '0'; end if;
elsif lineburst then
if sdi.rhaddr(4 downto 2) = "110" then
v.address(9 downto 5) := r.address(9 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
end if;
when rd2 =>
v.casn := '1'; v.sdstate := rd3;
if sdi.htrans /= "11" then -- v.rasn := '0'; v.sdwen := '0';
if (r.trfc(2 downto 1) = "00") then v.rasn := '0'; v.sdwen := '0'; end if;
elsif lineburst then
if sdi.rhaddr(4 downto 2) = "101" then
v.address(9 downto 5) := r.address(9 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
if v.sdwen = '0' then v.dqm := (others => '1'); end if;
when rd3 =>
v.sdstate := rd4; v.hready := '1'; v.casn := '1';
if r.sdwen = '0' then
v.rasn := '1'; v.sdwen := '1'; v.sdcsn := "11"; v.dqm := (others => '1');
elsif lineburst and (sdi.htrans = "11") and (r.casn = '1') then
if sdi.rhaddr(4 downto 2) = ("10" & not r.cfg.casdel) then
v.address(9 downto 5) := r.address(9 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
when rd4 =>
v.hready := '1'; v.casn := '1';
if (sdi.htrans /= "11") or (r.sdcsn = "11") or
((sdi.rhaddr(5 downto 2) = "1111") and (r.cfg.command = "10")) -- exit on refresh
then
v.hready := '0'; v.dqm := (others => '1');
if (r.sdcsn /= "11") then
v.rasn := '0'; v.sdwen := '0'; v.sdstate := rd5;
else
if r.cfg.trp = '1' then v.sdstate := rd6;
else v.sdstate := sidle; end if;
end if;
elsif lineburst then
if (sdi.rhaddr(4 downto 2) = lline) and (r.casn = '1') then
v.address(9 downto 5) := r.address(9 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
when rd5 =>
if r.cfg.trp = '1' then v.sdstate := rd6; else v.sdstate := sidle; end if;
v.sdcsn := (others => '1'); v.rasn := '1'; v.sdwen := '1'; v.dqm := (others => '1');
v.casn := '1';
when rd6 =>
v.sdstate := sidle; v.dqm := (others => '1');
v.sdcsn := (others => '1'); v.rasn := '1'; v.sdwen := '1';
when others =>
v.sdstate := sidle;
end case;
-- sdram commands
case r.cmstate is
when midle =>
if r.sdstate = sidle then
case r.cfg.command is
when "01" => -- precharge
if (sdi.idle = '1') then
v.busy := '1';
v.sdcsn := (others => '0'); v.rasn := '0'; v.sdwen := '0';
v.address(12) := '1'; v.cmstate := active;
end if;
when "10" => -- auto-refresh
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.cmstate := active;
when "11" =>
if (sdi.idle = '1') then
v.busy := '1';
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.sdwen := '0'; v.cmstate := active;
if lineburst then
v.address(15 downto 2) := "000010001" & r.cfg.casdel & "0011";
else
v.address(15 downto 2) := "000010001" & r.cfg.casdel & "0111";
end if;
end if;
when others => null;
end case;
end if;
when active =>
v.sdcsn := (others => '1'); v.rasn := '1'; v.casn := '1';
v.sdwen := '1'; v.cfg.command := "00";
v.cmstate := leadout; v.trfc := r.cfg.trfc;
when leadout =>
if r.trfc = "000" then v.cmstate := midle; end if;
end case;
-- sdram init
case r.istate is
when iidle =>
if (sdi.idle and sdi.enable) = '1' then
v.cfg.command := "01"; v.istate := pre;
end if;
when pre =>
if r.cfg.command = "00" then
v.cfg.command := "10"; v.istate := ref; v.icnt := "111";
end if;
when ref =>
if r.cfg.command = "00" then
v.cfg.command := "10"; v.icnt := r.icnt - 1;
if r.icnt = "000" then v.istate := lmode; v.cfg.command := "11"; end if;
end if;
when lmode =>
if r.cfg.command = "00" then
v.istate := finish;
end if;
when others =>
if sdi.enable = '0' then
v.istate := iidle;
end if;
end case;
if (sdi.hready and sdi.hsel ) = '1' then
if sdi.htrans(1) = '0' then v.hready := '1'; end if;
end if;
-- second part of main fsm
case r.mstate is
when active =>
if v.hready = '1' then
v.mstate := midle;
end if;
when others => null;
end case;
-- sdram refresh counter
if (r.cfg.renable = '1') and (r.istate = finish) then
v.refresh := r.refresh - 1;
if (v.refresh(14) and not r.refresh(14)) = '1' then
v.refresh := r.cfg.refresh;
v.cfg.command := "10";
end if;
end if;
-- APB register access
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(3 downto 2) is
when "01" =>
if pageburst = 2 then v.cfg.pageburst := apbi.pwdata(17); end if;
if sdi.enable = '1' then
v.cfg.command := apbi.pwdata(20 downto 19);
end if;
v.cfg.csize := apbi.pwdata(22 downto 21);
v.cfg.bsize := apbi.pwdata(25 downto 23);
v.cfg.casdel := apbi.pwdata(26);
v.cfg.trfc := apbi.pwdata(29 downto 27);
v.cfg.trp := apbi.pwdata(30);
v.cfg.renable := apbi.pwdata(31);
when "10" =>
v.cfg.refresh := apbi.pwdata(26 downto 12);
v.refresh := (others => '0');
when others =>
end case;
end if;
regsd := (others => '0');
case apbi.paddr(3 downto 2) is
when "01" =>
regsd(31 downto 19) := r.cfg.renable & r.cfg.trp & r.cfg.trfc &
r.cfg.casdel & r.cfg.bsize & r.cfg.csize & r.cfg.command;
if not lineburst then regsd(17) := '1'; end if;
when others =>
regsd(26 downto 12) := r.cfg.refresh;
end case;
sdmo.prdata <= regsd;
-- synchronise with sram/prom controller
if fast = 0 then
if (r.sdstate < wr4) or (v.hsel = '1') then v.busy := '1';end if;
else
if (r.sdstate < wr4) or (r.startsd = '1') then v.busy := '1';end if;
end if;
v.busy := v.busy or r.bdelay;
busy := v.busy or r.busy;
v.aload := r.busy and not v.busy;
aload := v.aload;
-- generate memory address
sdmo.address <= v.address;
-- reset
if rst = '0' then
v.sdstate := sidle;
v.mstate := midle;
v.istate := iidle;
v.cmstate := midle;
v.hsel := '0';
v.cfg.command := "00";
v.cfg.csize := "10";
v.cfg.bsize := "000";
v.cfg.casdel := '1';
v.cfg.trfc := "111";
v.cfg.renable := '0';
v.cfg.trp := '1';
v.dqm := (others => '1');
v.sdwen := '1';
v.rasn := '1';
v.casn := '1';
v.hready := '1';
v.startsd := '0';
if (pageburst = 2) then
v.cfg.pageburst := '0';
end if;
end if;
ri <= v;
sdmo.bdrive <= v.bdrive;
sdo.sdcke <= (others => '1');
sdo.sdcsn <= r.sdcsn;
sdo.sdwen <= r.sdwen;
sdo.dqm <= r.dqm;
sdo.rasn <= r.rasn;
sdo.casn <= r.casn;
sdmo.busy <= busy;
sdmo.aload <= aload;
sdmo.hready <= r.hready;
sdmo.hresp <= hresp;
sdmo.hsel <= r.hsel;
sdmo.bsel <= r.bsel;
end process;
regs : process(clk,rst)
begin
if rising_edge(clk) then
r <= ri;
if rst = '0' then
r.icnt <= (others => '0');
end if;
end if;
if rst = '0' then
r.bdrive <= '0';
r.sdcsn <= (others => '1');
end if;
end process;
end;
|
mit
|
lxp32/lxp32-cpu
|
rtl/lxp32_ram256x32.vhd
|
2
|
1699
|
---------------------------------------------------------------------
-- Generic dual-port memory
--
-- Part of the LXP32 CPU
--
-- Copyright (c) 2016 by Alex I. Kuznetsov
--
-- Portable description of a dual-port memory block with one write
-- port. Major FPGA synthesis tools can infer on-chip block RAM
-- from this description. Can be replaced with a library component
-- wrapper if needed.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity lxp32_ram256x32 is
port(
clk_i: in std_logic;
we_i: in std_logic;
waddr_i: in std_logic_vector(7 downto 0);
wdata_i: in std_logic_vector(31 downto 0);
re_i: in std_logic;
raddr_i: in std_logic_vector(7 downto 0);
rdata_o: out std_logic_vector(31 downto 0)
);
end entity;
architecture rtl of lxp32_ram256x32 is
type ram_type is array(255 downto 0) of std_logic_vector(31 downto 0);
signal ram: ram_type:=(others=>(others=>'0')); -- zero-initialize for SRAM-based FPGAs
attribute syn_ramstyle: string;
attribute syn_ramstyle of ram: signal is "no_rw_check";
attribute ram_style: string; -- for Xilinx
attribute ram_style of ram: signal is "block";
begin
-- Write port
process (clk_i) is
begin
if rising_edge(clk_i) then
if we_i='1' then
ram(to_integer(unsigned(waddr_i)))<=wdata_i;
end if;
end if;
end process;
-- Read port
process (clk_i) is
begin
if rising_edge(clk_i) then
if re_i='1' then
if is_x(raddr_i) then -- to avoid numeric_std warnings during simulation
rdata_o<=(others=>'X');
else
rdata_o<=ram(to_integer(unsigned(raddr_i)));
end if;
end if;
end if;
end process;
end architecture;
|
mit
|
impedimentToProgress/UCI-BlueChip
|
VhdlParser/test/resultMemory2.vhd
|
1
|
41304
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY grlib;
USE grlib.amba.all;
USE grlib.stdlib.all;
LIBRARY gaisler;
USE grlib.devices.all;
USE gaisler.memctrl.all;
LIBRARY techmap;
USE techmap.gencomp.all;
ENTITY ddrsp64a IS
GENERIC (
memtech : integer := 0;
hindex : integer := 3;
haddr : integer := 1024;
hmask : integer := 3072;
ioaddr : integer := 1;
iomask : integer := 4095;
MHz : integer := 90;
col : integer := 9;
Mbyte : integer := 256;
fast : integer := 0;
pwron : integer := 1;
oepol : integer := 0
);
PORT (
rst : in std_ulogic;
clk_ddr : in std_ulogic;
clk_ahb : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in sdctrl_in_type;
sdo : out sdctrl_out_type
);
END ENTITY;
ARCHITECTURE rtl OF ddrsp64a IS
CONSTANT REVISION : integer := 0;
CONSTANT CMD_PRE : std_logic_vector ( 2 downto 0 ) := "010";
CONSTANT CMD_REF : std_logic_vector ( 2 downto 0 ) := "100";
CONSTANT CMD_LMR : std_logic_vector ( 2 downto 0 ) := "110";
CONSTANT CMD_EMR : std_logic_vector ( 2 downto 0 ) := "111";
CONSTANT abuf : integer := 6;
CONSTANT hconfig : ahb_config_type := ( 0 => ahb_device_reg ( VENDOR_GAISLER , GAISLER_DDRSP , 0 , 0 , 0 ) , 4 => ahb_membar ( 1024 , '1' , '1' , 3072 ) , 5 => ahb_iobar ( 1 , 4095 ) , OTHERS => zero32 );
TYPE mcycletype IS ( midle , active , ext , leadout );
TYPE ahb_state_type IS ( midle , rhold , dread , dwrite , whold1 , whold2 );
TYPE sdcycletype IS ( act1 , act2 , act3 , rd1 , rd2 , rd3 , rd4 , rd5 , rd6 , rd7 , rd8 , wr1 , wr2 , wr3 , wr4a , wr4 , wr5 , sidle , ioreg1 , ioreg2 );
TYPE icycletype IS ( iidle , pre , ref1 , ref2 , emode , lmode , finish );
CONSTANT NAHBMST : integer := 16;
CONSTANT NAHBSLV : integer := 16;
CONSTANT NAPBSLV : integer := 16;
CONSTANT NAHBIRQ : integer := 32;
CONSTANT NAHBAMR : integer := 4;
CONSTANT NAHBIR : integer := 4;
CONSTANT NAHBCFG : integer := 4 + 4;
CONSTANT NAPBIR : integer := 1;
CONSTANT NAPBAMR : integer := 1;
CONSTANT NAPBCFG : integer := 1 + 1;
CONSTANT NBUS : integer := 4;
SUBTYPE amba_config_word IS std_logic_vector ( 31 downto 0 );
TYPE ahb_config_type IS ARRAY ( 0 to 4 + 4 - 1 ) OF amba_config_word;
TYPE apb_config_type IS ARRAY ( 0 to 1 + 1 - 1 ) OF amba_config_word;
TYPE ahb_mst_in_type IS RECORD
hgrant : std_logic_vector ( 0 to 16 - 1 );
hready : std_ulogic;
hresp : std_logic_vector ( 1 downto 0 );
hrdata : std_logic_vector ( 31 downto 0 );
hcache : std_ulogic;
hirq : std_logic_vector ( 32 - 1 downto 0 );
testen : std_ulogic;
testrst : std_ulogic;
scanen : std_ulogic;
testoen : std_ulogic;
END RECORD;
TYPE ahb_mst_out_type IS RECORD
hbusreq : std_ulogic;
hlock : std_ulogic;
htrans : std_logic_vector ( 1 downto 0 );
haddr : std_logic_vector ( 31 downto 0 );
hwrite : std_ulogic;
hsize : std_logic_vector ( 2 downto 0 );
hburst : std_logic_vector ( 2 downto 0 );
hprot : std_logic_vector ( 3 downto 0 );
hwdata : std_logic_vector ( 31 downto 0 );
hirq : std_logic_vector ( 32 - 1 downto 0 );
hconfig : ahb_config_type;
hindex : integer RANGE 0 to 16 - 1;
END RECORD;
TYPE ahb_slv_in_type IS RECORD
hsel : std_logic_vector ( 0 to 16 - 1 );
haddr : std_logic_vector ( 31 downto 0 );
hwrite : std_ulogic;
htrans : std_logic_vector ( 1 downto 0 );
hsize : std_logic_vector ( 2 downto 0 );
hburst : std_logic_vector ( 2 downto 0 );
hwdata : std_logic_vector ( 31 downto 0 );
hprot : std_logic_vector ( 3 downto 0 );
hready : std_ulogic;
hmaster : std_logic_vector ( 3 downto 0 );
hmastlock : std_ulogic;
hmbsel : std_logic_vector ( 0 to 4 - 1 );
hcache : std_ulogic;
hirq : std_logic_vector ( 32 - 1 downto 0 );
testen : std_ulogic;
testrst : std_ulogic;
scanen : std_ulogic;
testoen : std_ulogic;
END RECORD;
TYPE ahb_slv_out_type IS RECORD
hready : std_ulogic;
hresp : std_logic_vector ( 1 downto 0 );
hrdata : std_logic_vector ( 31 downto 0 );
hsplit : std_logic_vector ( 15 downto 0 );
hcache : std_ulogic;
hirq : std_logic_vector ( 32 - 1 downto 0 );
hconfig : ahb_config_type;
hindex : integer RANGE 0 to 16 - 1;
END RECORD;
TYPE ahb_mst_out_vector_type IS ARRAY ( natural RANGE <> ) OF ahb_mst_out_type;
TYPE ahb_slv_out_vector_type IS ARRAY ( natural RANGE <> ) OF ahb_slv_out_type;
SUBTYPE ahb_mst_out_vector IS ahb_mst_out_vector_type ( 16 - 1 downto 0 );
SUBTYPE ahb_slv_out_vector IS ahb_slv_out_vector_type ( 16 - 1 downto 0 );
TYPE ahb_mst_out_bus_vector IS ARRAY ( 0 to 4 - 1 ) OF ahb_mst_out_vector;
TYPE ahb_slv_out_bus_vector IS ARRAY ( 0 to 4 - 1 ) OF ahb_slv_out_vector;
CONSTANT HTRANS_IDLE : std_logic_vector ( 1 downto 0 ) := "00";
CONSTANT HTRANS_BUSY : std_logic_vector ( 1 downto 0 ) := "01";
CONSTANT HTRANS_NONSEQ : std_logic_vector ( 1 downto 0 ) := "10";
CONSTANT HTRANS_SEQ : std_logic_vector ( 1 downto 0 ) := "11";
CONSTANT HBURST_SINGLE : std_logic_vector ( 2 downto 0 ) := "000";
CONSTANT HBURST_INCR : std_logic_vector ( 2 downto 0 ) := "001";
CONSTANT HBURST_WRAP4 : std_logic_vector ( 2 downto 0 ) := "010";
CONSTANT HBURST_INCR4 : std_logic_vector ( 2 downto 0 ) := "011";
CONSTANT HBURST_WRAP8 : std_logic_vector ( 2 downto 0 ) := "100";
CONSTANT HBURST_INCR8 : std_logic_vector ( 2 downto 0 ) := "101";
CONSTANT HBURST_WRAP16 : std_logic_vector ( 2 downto 0 ) := "110";
CONSTANT HBURST_INCR16 : std_logic_vector ( 2 downto 0 ) := "111";
CONSTANT HSIZE_BYTE : std_logic_vector ( 2 downto 0 ) := "000";
CONSTANT HSIZE_HWORD : std_logic_vector ( 2 downto 0 ) := "001";
CONSTANT HSIZE_WORD : std_logic_vector ( 2 downto 0 ) := "010";
CONSTANT HSIZE_DWORD : std_logic_vector ( 2 downto 0 ) := "011";
CONSTANT HSIZE_4WORD : std_logic_vector ( 2 downto 0 ) := "100";
CONSTANT HSIZE_8WORD : std_logic_vector ( 2 downto 0 ) := "101";
CONSTANT HSIZE_16WORD : std_logic_vector ( 2 downto 0 ) := "110";
CONSTANT HSIZE_32WORD : std_logic_vector ( 2 downto 0 ) := "111";
CONSTANT HRESP_OKAY : std_logic_vector ( 1 downto 0 ) := "00";
CONSTANT HRESP_ERROR : std_logic_vector ( 1 downto 0 ) := "01";
CONSTANT HRESP_RETRY : std_logic_vector ( 1 downto 0 ) := "10";
CONSTANT HRESP_SPLIT : std_logic_vector ( 1 downto 0 ) := "11";
TYPE apb_slv_in_type IS RECORD
psel : std_logic_vector ( 0 to 16 - 1 );
penable : std_ulogic;
paddr : std_logic_vector ( 31 downto 0 );
pwrite : std_ulogic;
pwdata : std_logic_vector ( 31 downto 0 );
pirq : std_logic_vector ( 32 - 1 downto 0 );
testen : std_ulogic;
testrst : std_ulogic;
scanen : std_ulogic;
testoen : std_ulogic;
END RECORD;
TYPE apb_slv_out_type IS RECORD
prdata : std_logic_vector ( 31 downto 0 );
pirq : std_logic_vector ( 32 - 1 downto 0 );
pconfig : apb_config_type;
pindex : integer RANGE 0 to 16 - 1;
END RECORD;
TYPE apb_slv_out_vector IS ARRAY ( 0 to 16 - 1 ) OF apb_slv_out_type;
CONSTANT AMBA_CONFIG_VER0 : std_logic_vector ( 1 downto 0 ) := "00";
SUBTYPE amba_vendor_type IS integer RANGE 0 to 16#ff#;
SUBTYPE amba_device_type IS integer RANGE 0 to 16#3ff#;
SUBTYPE amba_version_type IS integer RANGE 0 to 16#3f#;
SUBTYPE amba_cfgver_type IS integer RANGE 0 to 3;
SUBTYPE amba_irq_type IS integer RANGE 0 to 32 - 1;
SUBTYPE ahb_addr_type IS integer RANGE 0 to 16#fff#;
CONSTANT zx : std_logic_vector ( 31 downto 0 ) := ( OTHERS => '0' );
CONSTANT zxirq : std_logic_vector ( 32 - 1 downto 0 ) := ( OTHERS => '0' );
CONSTANT zy : std_logic_vector ( 0 to 31 ) := ( OTHERS => '0' );
TYPE memory_in_type IS RECORD
data : std_logic_vector ( 31 downto 0 );
brdyn : std_logic;
bexcn : std_logic;
writen : std_logic;
wrn : std_logic_vector ( 3 downto 0 );
bwidth : std_logic_vector ( 1 downto 0 );
sd : std_logic_vector ( 63 downto 0 );
cb : std_logic_vector ( 7 downto 0 );
scb : std_logic_vector ( 7 downto 0 );
edac : std_logic;
END RECORD;
TYPE memory_out_type IS RECORD
address : std_logic_vector ( 31 downto 0 );
data : std_logic_vector ( 31 downto 0 );
sddata : std_logic_vector ( 63 downto 0 );
ramsn : std_logic_vector ( 7 downto 0 );
ramoen : std_logic_vector ( 7 downto 0 );
ramn : std_ulogic;
romn : std_ulogic;
mben : std_logic_vector ( 3 downto 0 );
iosn : std_logic;
romsn : std_logic_vector ( 7 downto 0 );
oen : std_logic;
writen : std_logic;
wrn : std_logic_vector ( 3 downto 0 );
bdrive : std_logic_vector ( 3 downto 0 );
vbdrive : std_logic_vector ( 31 downto 0 );
svbdrive : std_logic_vector ( 63 downto 0 );
read : std_logic;
sa : std_logic_vector ( 14 downto 0 );
cb : std_logic_vector ( 7 downto 0 );
scb : std_logic_vector ( 7 downto 0 );
vcdrive : std_logic_vector ( 7 downto 0 );
svcdrive : std_logic_vector ( 7 downto 0 );
ce : std_ulogic;
END RECORD;
TYPE sdctrl_in_type IS RECORD
wprot : std_ulogic;
data : std_logic_vector ( 127 downto 0 );
cb : std_logic_vector ( 15 downto 0 );
END RECORD;
TYPE sdctrl_out_type IS RECORD
sdcke : std_logic_vector ( 1 downto 0 );
sdcsn : std_logic_vector ( 1 downto 0 );
sdwen : std_ulogic;
rasn : std_ulogic;
casn : std_ulogic;
dqm : std_logic_vector ( 15 downto 0 );
bdrive : std_ulogic;
qdrive : std_ulogic;
vbdrive : std_logic_vector ( 31 downto 0 );
address : std_logic_vector ( 16 downto 2 );
data : std_logic_vector ( 127 downto 0 );
cb : std_logic_vector ( 15 downto 0 );
ce : std_ulogic;
ba : std_logic_vector ( 1 downto 0 );
cal_en : std_logic_vector ( 7 downto 0 );
cal_inc : std_logic_vector ( 7 downto 0 );
cal_rst : std_logic;
odt : std_logic_vector ( 1 downto 0 );
END RECORD;
TYPE sdram_out_type IS RECORD
sdcke : std_logic_vector ( 1 downto 0 );
sdcsn : std_logic_vector ( 1 downto 0 );
sdwen : std_ulogic;
rasn : std_ulogic;
casn : std_ulogic;
dqm : std_logic_vector ( 7 downto 0 );
END RECORD;
TYPE sdram_cfg_type IS RECORD
command : std_logic_vector ( 2 downto 0 );
csize : std_logic_vector ( 1 downto 0 );
bsize : std_logic_vector ( 2 downto 0 );
trcd : std_ulogic;
trfc : std_logic_vector ( 2 downto 0 );
trp : std_ulogic;
refresh : std_logic_vector ( 11 downto 0 );
renable : std_ulogic;
dllrst : std_ulogic;
refon : std_ulogic;
cke : std_ulogic;
END RECORD;
TYPE access_param IS RECORD
haddr : std_logic_vector ( 31 downto 0 );
size : std_logic_vector ( 1 downto 0 );
hwrite : std_ulogic;
hio : std_ulogic;
END RECORD;
TYPE ahb_reg_type IS RECORD
hready : std_ulogic;
hsel : std_ulogic;
hio : std_ulogic;
startsd : std_ulogic;
ready : std_ulogic;
ready2 : std_ulogic;
write : std_logic_vector ( 3 downto 0 );
state : ahb_state_type;
haddr : std_logic_vector ( 31 downto 0 );
hrdata : std_logic_vector ( 31 downto 0 );
hwdata : std_logic_vector ( 31 downto 0 );
hwrite : std_ulogic;
htrans : std_logic_vector ( 1 downto 0 );
hresp : std_logic_vector ( 1 downto 0 );
raddr : std_logic_vector ( 6 - 1 downto 0 );
size : std_logic_vector ( 1 downto 0 );
acc : access_param;
END RECORD;
TYPE ddr_reg_type IS RECORD
startsd : std_ulogic;
startsdold : std_ulogic;
burst : std_ulogic;
hready : std_ulogic;
bdrive : std_ulogic;
qdrive : std_ulogic;
nbdrive : std_ulogic;
mstate : mcycletype;
sdstate : sdcycletype;
cmstate : mcycletype;
istate : icycletype;
trfc : std_logic_vector ( 2 downto 0 );
refresh : std_logic_vector ( 11 downto 0 );
sdcsn : std_logic_vector ( 1 downto 0 );
sdwen : std_ulogic;
rasn : std_ulogic;
casn : std_ulogic;
dqm : std_logic_vector ( 15 downto 0 );
address : std_logic_vector ( 15 downto 2 );
ba : std_logic_vector ( 1 downto 0 );
waddr : std_logic_vector ( 6 - 1 downto 0 );
cfg : sdram_cfg_type;
hrdata : std_logic_vector ( 127 downto 0 );
END RECORD;
SIGNAL vcc : std_ulogic;
SIGNAL r : ddr_reg_type;
SIGNAL ri : ddr_reg_type;
SIGNAL ra : ahb_reg_type;
SIGNAL rai : ahb_reg_type;
SIGNAL rbdrive : std_logic_vector ( 31 downto 0 );
SIGNAL ribdrive : std_logic_vector ( 31 downto 0 );
SIGNAL rdata : std_logic_vector ( 127 downto 0 );
SIGNAL wdata : std_logic_vector ( 127 downto 0 );
ATTRIBUTE syn_preserve : boolean;
ATTRIBUTE syn_preserve OF rbdrive : signal IS true;
BEGIN
vcc <= '1';
ahb_ctrl : PROCESS ( rst , ahbsi , r , ra , rdata )
VARIABLE v : ahb_reg_type;
VARIABLE startsd : std_ulogic;
VARIABLE dout : std_logic_vector ( 31 downto 0 );
BEGIN
v := ra;
v.hresp := "00";
v.write := "0000";
CASE ra.raddr ( 1 downto 0 ) IS
WHEN "00" =>
v.hrdata := rdata ( 127 downto 96 );
WHEN "01" =>
v.hrdata := rdata ( 95 downto 64 );
WHEN "10" =>
v.hrdata := rdata ( 63 downto 32 );
WHEN OTHERS =>
v.hrdata := rdata ( 31 downto 0 );
END CASE;
v.ready := not ( ra.startsd xor r.startsdold );
v.ready2 := ra.ready;
IF ( ( ahbsi.hready and ahbsi.hsel ( 3 ) ) = '1' ) THEN
v.htrans := ahbsi.htrans;
v.haddr := ahbsi.haddr;
v.size := ahbsi.hsize ( 1 downto 0 );
v.hwrite := ahbsi.hwrite;
IF ahbsi.htrans ( 1 ) = '1' THEN
v.hio := ahbsi.hmbsel ( 1 );
v.hsel := '1';
v.hready := '0';
END IF;
END IF;
IF ahbsi.hready = '1' THEN
v.hsel := ahbsi.hsel ( 3 );
END IF;
CASE ra.state IS
WHEN midle =>
IF ( ( v.hsel and v.htrans ( 1 ) ) = '1' ) THEN
IF v.hwrite = '0' THEN
v.state := rhold;
v.startsd := not ra.startsd;
ELSE
v.state := dwrite;
v.hready := '1';
v.write := decode ( v.haddr ( 3 downto 2 ) );
END IF;
END IF;
v.raddr := ra.haddr ( 7 downto 2 );
v.ready := '0';
v.ready2 := '0';
IF ahbsi.hready = '1' THEN
v.acc := ( v.haddr , v.size , v.hwrite , v.hio );
END IF;
WHEN rhold =>
v.raddr := ra.haddr ( 7 downto 2 );
IF ra.ready2 = '1' THEN
v.state := dread;
v.hready := '1';
v.raddr := ra.raddr + 1;
END IF;
WHEN dread =>
v.raddr := ra.raddr + 1;
v.hready := '1';
IF ( ( v.hsel and v.htrans ( 1 ) and v.htrans ( 0 ) ) = '0' ) or ( ra.raddr ( 2 downto 0 ) = "000" ) THEN
v.state := midle;
v.hready := '0';
END IF;
v.acc := ( v.haddr , v.size , v.hwrite , v.hio );
WHEN dwrite =>
v.raddr := ra.haddr ( 7 downto 2 );
v.hready := '1';
v.write := decode ( v.haddr ( 3 downto 2 ) );
IF ( ( v.hsel and v.htrans ( 1 ) and v.htrans ( 0 ) ) = '0' ) or ( ra.haddr ( 4 downto 2 ) = "111" ) THEN
v.startsd := not ra.startsd;
v.state := whold1;
v.write := "0000";
v.hready := '0';
END IF;
WHEN whold1 =>
v.state := whold2;
v.ready := '0';
WHEN whold2 =>
IF ra.ready = '1' THEN
v.state := midle;
v.acc := ( v.haddr , v.size , v.hwrite , v.hio );
END IF;
END CASE;
v.hwdata := ahbsi.hwdata;
IF ( ahbsi.hready and ahbsi.hsel ( 3 ) ) = '1' THEN
IF ahbsi.htrans ( 1 ) = '0' THEN
v.hready := '1';
END IF;
END IF;
dout := ra.hrdata ( 31 downto 0 );
IF rst = '0' THEN
v.hsel := '0';
v.hready := '1';
v.state := midle;
v.startsd := '0';
v.hio := '0';
END IF;
rai <= v;
ahbso.hready <= ra.hready;
ahbso.hresp <= ra.hresp;
ahbso.hrdata <= dout;
ahbso.hcache <= not ra.hio;
END PROCESS;
ddr_ctrl : PROCESS ( rst , r , ra , sdi , rbdrive , wdata )
VARIABLE v : ddr_reg_type;
VARIABLE startsd : std_ulogic;
VARIABLE dqm : std_logic_vector ( 15 downto 0 );
VARIABLE raddr : std_logic_vector ( 13 downto 0 );
VARIABLE adec : std_ulogic;
VARIABLE rams : std_logic_vector ( 1 downto 0 );
VARIABLE ba : std_logic_vector ( 1 downto 0 );
VARIABLE haddr : std_logic_vector ( 31 downto 0 );
VARIABLE hsize : std_logic_vector ( 1 downto 0 );
VARIABLE hwrite : std_ulogic;
VARIABLE htrans : std_logic_vector ( 1 downto 0 );
VARIABLE hready : std_ulogic;
VARIABLE vbdrive : std_logic_vector ( 31 downto 0 );
VARIABLE bdrive : std_ulogic;
VARIABLE writecfg : std_ulogic;
VARIABLE regsd1 : std_logic_vector ( 31 downto 0 );
VARIABLE regsd2 : std_logic_vector ( 31 downto 0 );
BEGIN
v := r;
v.hready := '0';
writecfg := '0';
vbdrive := rbdrive;
v.hrdata := sdi.data;
v.qdrive := '0';
regsd1 := ( OTHERS => '0' );
regsd1 ( 31 downto 15 ) := r.cfg.refon & r.cfg.trp & r.cfg.trfc & r.cfg.trcd & r.cfg.bsize & r.cfg.csize & r.cfg.command & r.cfg.dllrst & r.cfg.renable & r.cfg.cke;
regsd1 ( 11 downto 0 ) := r.cfg.refresh;
regsd2 := ( OTHERS => '0' );
regsd2 ( 8 downto 0 ) := conv_std_logic_vector ( 90 , 9 );
regsd2 ( 14 downto 12 ) := conv_std_logic_vector ( 3 , 3 );
CASE ra.acc.size IS
WHEN "00" =>
CASE ra.acc.haddr ( 3 downto 0 ) IS
WHEN "0000" =>
dqm := "0111111111111111";
WHEN "0001" =>
dqm := "1011111111111111";
WHEN "0010" =>
dqm := "1101111111111111";
WHEN "0011" =>
dqm := "1110111111111111";
WHEN "0100" =>
dqm := "1111011111111111";
WHEN "0101" =>
dqm := "1111101111111111";
WHEN "0110" =>
dqm := "1111110111111111";
WHEN "0111" =>
dqm := "1111111011111111";
WHEN "1000" =>
dqm := "1111111101111111";
WHEN "1001" =>
dqm := "1111111110111111";
WHEN "1010" =>
dqm := "1111111111011111";
WHEN "1011" =>
dqm := "1111111111101111";
WHEN "1100" =>
dqm := "1111111111110111";
WHEN "1101" =>
dqm := "1111111111111011";
WHEN "1110" =>
dqm := "1111111111111101";
WHEN OTHERS =>
dqm := "1111111111111110";
END CASE;
WHEN "01" =>
CASE ra.acc.haddr ( 3 downto 1 ) IS
WHEN "000" =>
dqm := "0011111111111111";
WHEN "001" =>
dqm := "1100111111111111";
WHEN "010" =>
dqm := "1111001111111111";
WHEN "011" =>
dqm := "1111110011111111";
WHEN "100" =>
dqm := "1111111100111111";
WHEN "101" =>
dqm := "1111111111001111";
WHEN "110" =>
dqm := "1111111111110011";
WHEN OTHERS =>
dqm := "1111111111111100";
END CASE;
WHEN OTHERS =>
dqm := "0000000000000000";
END CASE;
v.startsd := ra.startsd;
CASE r.mstate IS
WHEN midle =>
IF r.startsd = '1' THEN
IF ( r.sdstate = sidle ) and ( r.cfg.command = "000" ) and ( r.cmstate = midle ) THEN
startsd := '1';
v.mstate := active;
END IF;
END IF;
WHEN OTHERS =>
NULL;
END CASE;
startsd := r.startsd xor r.startsdold;
haddr := ra.acc.haddr;
CASE r.cfg.csize IS
WHEN "00" =>
WHEN "01" =>
WHEN "10" =>
WHEN OTHERS =>
END CASE;
rams := adec & not adec;
IF r.trfc /= "000" THEN
v.trfc := r.trfc - 1;
END IF;
CASE r.sdstate IS
WHEN sidle =>
IF ( startsd = '1' ) and ( r.cfg.command = "000" ) and ( r.cmstate = midle ) and ( r.istate = finish ) THEN
v.address := raddr;
v.ba := ba;
IF ra.acc.hio = '0' THEN
v.sdcsn := not rams ( 1 downto 0 );
v.rasn := '0';
v.sdstate := act1;
ELSE
v.sdstate := ioreg1;
END IF;
END IF;
v.waddr := ra.acc.haddr ( 7 downto 2 );
WHEN act1 =>
v.rasn := '1';
v.trfc := r.cfg.trfc;
IF r.cfg.trcd = '1' THEN
v.sdstate := act2;
ELSE
v.sdstate := act3;
v.hready := ra.acc.hwrite;
END IF;
v.waddr := ra.acc.haddr ( 7 downto 2 );
WHEN act2 =>
v.sdstate := act3;
v.hready := ra.acc.hwrite;
WHEN act3 =>
v.casn := '0';
v.address := ra.acc.haddr ( 15 downto 13 ) & '0' & ra.acc.haddr ( 12 downto 4 ) & '0';
v.dqm := dqm;
IF ra.acc.hwrite = '1' THEN
v.waddr := r.waddr + 4;
v.waddr ( 1 downto 0 ) := "00";
v.sdstate := wr1;
v.sdwen := '0';
v.bdrive := '0';
v.qdrive := '1';
IF ( r.waddr /= ra.raddr ) THEN
v.hready := '1';
IF ( r.waddr ( 5 downto 2 ) = ra.raddr ( 5 downto 2 ) ) THEN
IF r.waddr ( 1 ) = '1' THEN
v.dqm ( 15 downto 8 ) := ( OTHERS => '1' );
ELSE
CASE ra.raddr ( 1 downto 0 ) IS
WHEN "01" =>
v.dqm ( 7 downto 0 ) := ( OTHERS => '1' );
WHEN "10" =>
v.dqm ( 3 downto 0 ) := ( OTHERS => '1' );
v.dqm ( 15 downto 12 ) := ( OTHERS => r.waddr ( 0 ) );
WHEN OTHERS =>
v.dqm ( 15 downto 12 ) := ( OTHERS => r.waddr ( 0 ) );
END CASE;
END IF;
ELSE
CASE r.waddr ( 1 downto 0 ) IS
WHEN "01" =>
v.dqm ( 15 downto 12 ) := ( OTHERS => '1' );
WHEN "10" =>
v.dqm ( 15 downto 8 ) := ( OTHERS => '1' );
WHEN "11" =>
v.dqm ( 15 downto 4 ) := ( OTHERS => '1' );
WHEN OTHERS =>
NULL;
END CASE;
END IF;
ELSE
CASE r.waddr ( 1 downto 0 ) IS
WHEN "00" =>
v.dqm ( 11 downto 0 ) := ( OTHERS => '1' );
WHEN "01" =>
v.dqm ( 15 downto 12 ) := ( OTHERS => '1' );
v.dqm ( 7 downto 0 ) := ( OTHERS => '1' );
WHEN "10" =>
v.dqm ( 15 downto 8 ) := ( OTHERS => '1' );
v.dqm ( 3 downto 0 ) := ( OTHERS => '1' );
WHEN OTHERS =>
v.dqm ( 15 downto 4 ) := ( OTHERS => '1' );
END CASE;
END IF;
ELSE
v.sdstate := rd1;
END IF;
WHEN wr1 =>
v.sdwen := '1';
v.casn := '1';
v.qdrive := '1';
v.waddr := r.waddr + 4;
v.dqm := ( OTHERS => '0' );
v.address ( 8 downto 3 ) := r.waddr;
IF ( r.waddr <= ra.raddr ) and ( r.waddr ( 5 downto 2 ) /= "0000" ) and ( r.hready = '1' ) THEN
v.hready := '1';
IF ( r.hready = '1' ) and ( r.waddr ( 2 downto 0 ) = "000" ) THEN
v.sdwen := '0';
v.casn := '0';
END IF;
IF ( r.waddr ( 5 downto 2 ) = ra.raddr ( 5 downto 2 ) ) and ( r.waddr /= "000000" ) THEN
CASE ra.raddr ( 1 downto 0 ) IS
WHEN "00" =>
v.dqm ( 11 downto 0 ) := ( OTHERS => '1' );
WHEN "01" =>
v.dqm ( 7 downto 0 ) := ( OTHERS => '1' );
WHEN "10" =>
v.dqm ( 3 downto 0 ) := ( OTHERS => '1' );
WHEN OTHERS =>
NULL;
END CASE;
END IF;
ELSE
v.sdstate := wr2;
v.dqm := ( OTHERS => '1' );
v.startsdold := r.startsd;
END IF;
WHEN wr2 =>
v.sdstate := wr3;
v.qdrive := '1';
WHEN wr3 =>
v.sdstate := wr4a;
v.qdrive := '1';
WHEN wr4a =>
v.bdrive := '1';
v.rasn := '0';
v.sdwen := '0';
v.sdstate := wr4;
v.qdrive := '1';
WHEN wr4 =>
v.sdcsn := "11";
v.rasn := '1';
v.sdwen := '1';
v.qdrive := '0';
v.sdstate := wr5;
WHEN wr5 =>
v.sdstate := sidle;
WHEN rd1 =>
v.casn := '1';
v.sdstate := rd7;
WHEN rd7 =>
v.casn := '1';
v.sdstate := rd2;
WHEN rd2 =>
v.casn := '1';
v.sdstate := rd3;
WHEN rd3 =>
IF 0 = 0 THEN
v.startsdold := r.startsd;
END IF;
v.sdstate := rd4;
v.hready := '1';
v.casn := '1';
IF v.hready = '1' THEN
v.waddr := r.waddr + 4;
END IF;
WHEN rd4 =>
v.hready := '1';
v.casn := '1';
IF ( r.sdcsn = "11" ) or ( r.waddr ( 2 downto 2 ) = "1" ) THEN
v.dqm := ( OTHERS => '1' );
v.burst := '0';
IF 0 /= 0 THEN
v.startsdold := r.startsd;
END IF;
IF ( r.sdcsn /= "11" ) THEN
v.rasn := '0';
v.sdwen := '0';
v.sdstate := rd5;
ELSE
IF r.cfg.trp = '1' THEN
v.sdstate := rd6;
ELSE
v.sdstate := sidle;
END IF;
END IF;
END IF;
IF v.hready = '1' THEN
v.waddr := r.waddr + 4;
END IF;
WHEN rd5 =>
IF r.cfg.trp = '1' THEN
v.sdstate := rd6;
ELSE
v.sdstate := sidle;
END IF;
v.sdcsn := ( OTHERS => '1' );
v.rasn := '1';
v.sdwen := '1';
v.dqm := ( OTHERS => '1' );
WHEN rd6 =>
v.sdstate := sidle;
v.dqm := ( OTHERS => '1' );
v.sdcsn := ( OTHERS => '1' );
v.rasn := '1';
v.sdwen := '1';
WHEN ioreg1 =>
v.hrdata ( 127 downto 64 ) := regsd1 & regsd2;
v.sdstate := ioreg2;
IF ra.acc.hwrite = '0' THEN
v.hready := '1';
END IF;
WHEN ioreg2 =>
writecfg := ra.acc.hwrite and not r.waddr ( 0 );
v.startsdold := r.startsd;
v.sdstate := sidle;
WHEN OTHERS =>
v.sdstate := sidle;
END CASE;
CASE r.cmstate IS
WHEN midle =>
IF r.sdstate = sidle THEN
CASE r.cfg.command IS
WHEN "010" =>
v.sdcsn := ( OTHERS => '0' );
v.rasn := '0';
v.sdwen := '0';
v.address ( 12 ) := '1';
v.cmstate := active;
WHEN "100" =>
v.sdcsn := ( OTHERS => '0' );
v.rasn := '0';
v.casn := '0';
v.cmstate := active;
WHEN "111" =>
v.sdcsn := ( OTHERS => '0' );
v.rasn := '0';
v.casn := '0';
v.sdwen := '0';
v.cmstate := active;
v.ba := "01";
v.address := "00000000000000";
WHEN "110" =>
v.sdcsn := ( OTHERS => '0' );
v.rasn := '0';
v.casn := '0';
v.sdwen := '0';
v.cmstate := active;
v.ba := "00";
v.address := "00000" & r.cfg.dllrst & "0" & "01" & "00010";
WHEN OTHERS =>
NULL;
END CASE;
END IF;
WHEN active =>
v.sdcsn := ( OTHERS => '1' );
v.rasn := '1';
v.casn := '1';
v.sdwen := '1';
v.cfg.command := "000";
v.cmstate := leadout;
v.trfc := r.cfg.trfc;
WHEN OTHERS =>
IF r.trfc = "000" THEN
v.cmstate := midle;
END IF;
END CASE;
CASE r.istate IS
WHEN iidle =>
IF r.cfg.renable = '1' THEN
v.cfg.cke := '1';
v.cfg.dllrst := '1';
IF r.cfg.cke = '1' THEN
v.istate := pre;
v.cfg.command := "010";
END IF;
v.ba := "00";
END IF;
WHEN pre =>
IF r.cfg.command = "000" THEN
v.cfg.command := "11" & r.cfg.dllrst;
IF r.cfg.dllrst = '1' THEN
v.istate := emode;
ELSE
v.istate := lmode;
END IF;
END IF;
WHEN emode =>
IF r.cfg.command = "000" THEN
v.istate := lmode;
v.cfg.command := "110";
END IF;
WHEN lmode =>
IF r.cfg.command = "000" THEN
IF r.cfg.dllrst = '1' THEN
IF r.refresh ( 9 downto 8 ) = "00" THEN
v.cfg.command := "010";
v.istate := ref1;
END IF;
ELSE
v.istate := finish;
v.cfg.refon := '1';
v.cfg.renable := '0';
END IF;
END IF;
WHEN ref1 =>
IF r.cfg.command = "000" THEN
v.cfg.command := "100";
v.cfg.dllrst := '0';
v.istate := ref2;
END IF;
WHEN ref2 =>
IF r.cfg.command = "000" THEN
v.cfg.command := "100";
v.istate := pre;
END IF;
WHEN OTHERS =>
IF r.cfg.renable = '1' THEN
v.istate := iidle;
v.cfg.dllrst := '1';
END IF;
END CASE;
CASE r.mstate IS
WHEN active =>
IF v.hready = '1' THEN
v.mstate := midle;
END IF;
WHEN OTHERS =>
NULL;
END CASE;
IF ( ( r.cfg.refon = '1' ) and ( r.istate = finish ) ) or ( r.cfg.dllrst = '1' ) THEN
v.refresh := r.refresh - 1;
IF ( v.refresh ( 11 ) and not r.refresh ( 11 ) ) = '1' THEN
v.refresh := r.cfg.refresh;
IF r.cfg.dllrst = '0' THEN
v.cfg.command := "100";
END IF;
END IF;
END IF;
IF ( ra.acc.hio and ra.acc.hwrite and writecfg ) = '1' THEN
v.cfg.refresh := wdata ( 11 + 96 downto 0 + 96 );
v.cfg.cke := wdata ( 15 + 96 );
v.cfg.renable := wdata ( 16 + 96 );
v.cfg.dllrst := wdata ( 17 + 96 );
v.cfg.command := wdata ( 20 + 96 downto 18 + 96 );
v.cfg.csize := wdata ( 22 + 96 downto 21 + 96 );
v.cfg.bsize := wdata ( 25 + 96 downto 23 + 96 );
v.cfg.trcd := wdata ( 26 + 96 );
v.cfg.trfc := wdata ( 29 + 96 downto 27 + 96 );
v.cfg.trp := wdata ( 30 + 96 );
v.cfg.refon := wdata ( 31 + 96 );
END IF;
v.nbdrive := not v.bdrive;
IF 0 = 1 THEN
bdrive := r.nbdrive;
vbdrive := ( OTHERS => v.nbdrive );
ELSE
bdrive := r.bdrive;
vbdrive := ( OTHERS => v.bdrive );
END IF;
IF rst = '0' THEN
v.sdstate := sidle;
v.mstate := midle;
v.istate := finish;
v.cmstate := midle;
v.cfg.command := "000";
v.cfg.csize := conv_std_logic_vector ( 9 - 9 , 2 );
v.cfg.bsize := conv_std_logic_vector ( log2 ( 256 / 8 ) , 3 );
IF 90 > 100 THEN
v.cfg.trcd := '1';
ELSE
v.cfg.trcd := '0';
END IF;
v.cfg.refon := '0';
v.cfg.trfc := conv_std_logic_vector ( 75 * 90 / 1000 - 2 , 3 );
v.cfg.refresh := conv_std_logic_vector ( 7800 * 90 / 1000 , 12 );
v.refresh := ( OTHERS => '0' );
IF 1 = 1 THEN
v.cfg.renable := '1';
ELSE
v.cfg.renable := '0';
END IF;
IF 90 > 100 THEN
v.cfg.trp := '1';
ELSE
v.cfg.trp := '0';
END IF;
v.dqm := ( OTHERS => '1' );
v.sdwen := '1';
v.rasn := '1';
v.casn := '1';
v.hready := '0';
v.startsd := '0';
v.startsdold := '0';
v.cfg.dllrst := '0';
v.cfg.cke := '0';
END IF;
ri <= v;
ribdrive <= vbdrive;
END PROCESS;
sdo.sdcke <= ( OTHERS => r.cfg.cke );
ahbso.hconfig <= ( 0 => AHB_DEVICE_REG ( VENDOR_GAISLER , GAISLER_DDRSP , 0 , 0 , 0 ) , 4 => AHB_MEMBAR ( 1024 , '1' , '1' , 3072 ) , 5 => AHB_IOBAR ( 1 , 4095 ) , OTHERS => ZERO32 );
ahbso.hirq <= ( OTHERS => '0' );
ahbso.hindex <= 3;
ahbregs : PROCESS ( clk_ahb )
BEGIN
IF rising_edge ( clk_ahb ) THEN
ra <= rai;
END IF;
END PROCESS;
ddrregs : PROCESS ( clk_ddr , rst )
BEGIN
IF rising_edge ( clk_ddr ) THEN
r <= ri;
rbdrive <= ribdrive;
END IF;
IF ( rst = '0' ) THEN
r.sdcsn <= ( OTHERS => '1' );
r.bdrive <= '1';
r.nbdrive <= '0';
IF 0 = 0 THEN
rbdrive <= ( OTHERS => '1' );
ELSE
rbdrive <= ( OTHERS => '0' );
END IF;
r.cfg.cke <= '0';
END IF;
END PROCESS;
sdo.address <= '0' & ri.address;
sdo.ba <= ri.ba;
sdo.bdrive <= r.nbdrive WHEN 0 = 1 ELSE r.bdrive;
sdo.qdrive <= not ( ri.qdrive or r.nbdrive );
sdo.vbdrive <= rbdrive;
sdo.sdcsn <= ri.sdcsn;
sdo.sdwen <= ri.sdwen;
sdo.dqm <= r.dqm;
sdo.rasn <= ri.rasn;
sdo.casn <= ri.casn;
sdo.data <= wdata;
read_buff : COMPONENT syncram_2p
GENERIC MAP (
tech => 0 , abits => 4 , dbits => 128 , sepclk => 1 , wrfst => 0
) PORT MAP (
rclk => clk_ahb , renable => vcc , raddress => rai.raddr ( 5 downto 2 ) , dataout => rdata , wclk => clk_ddr , write => ri.hready , waddress => r.waddr ( 5 downto 2 ) , datain => ri.hrdata
)
;
write_buff1 : COMPONENT syncram_2p
GENERIC MAP (
tech => 0 , abits => 4 , dbits => 32 , sepclk => 1 , wrfst => 0
) PORT MAP (
rclk => clk_ddr , renable => vcc , raddress => r.waddr ( 5 downto 2 ) , dataout => wdata ( 127 downto 96 ) , wclk => clk_ahb , write => ra.write ( 0 ) , waddress => ra.haddr ( 7 downto 4 ) , datain => ahbsi.hwdata
)
;
write_buff2 : COMPONENT syncram_2p
GENERIC MAP (
tech => 0 , abits => 4 , dbits => 32 , sepclk => 1 , wrfst => 0
) PORT MAP (
rclk => clk_ddr , renable => vcc , raddress => r.waddr ( 5 downto 2 ) , dataout => wdata ( 95 downto 64 ) , wclk => clk_ahb , write => ra.write ( 1 ) , waddress => ra.haddr ( 7 downto 4 ) , datain => ahbsi.hwdata
)
;
write_buff3 : COMPONENT syncram_2p
GENERIC MAP (
tech => 0 , abits => 4 , dbits => 32 , sepclk => 1 , wrfst => 0
) PORT MAP (
rclk => clk_ddr , renable => vcc , raddress => r.waddr ( 5 downto 2 ) , dataout => wdata ( 63 downto 32 ) , wclk => clk_ahb , write => ra.write ( 2 ) , waddress => ra.haddr ( 7 downto 4 ) , datain => ahbsi.hwdata
)
;
write_buff4 : COMPONENT syncram_2p
GENERIC MAP (
tech => 0 , abits => 4 , dbits => 32 , sepclk => 1 , wrfst => 0
) PORT MAP (
rclk => clk_ddr , renable => vcc , raddress => r.waddr ( 5 downto 2 ) , dataout => wdata ( 31 downto 0 ) , wclk => clk_ahb , write => ra.write ( 3 ) , waddress => ra.haddr ( 7 downto 4 ) , datain => ahbsi.hwdata
)
;
bootmsg : COMPONENT report_version
GENERIC MAP (
msg1 => "ddrsp" & tost ( 3 ) & ": 64-bit DDR266 controller rev " & tost ( 0 ) & ", " & tost ( 256 ) & " Mbyte, " & tost ( 90 ) & " MHz DDR clock"
)
;
END ARCHITECTURE;
|
mit
|
impedimentToProgress/UCI-BlueChip
|
AttackFiles/Attacks/memAttack/lib/tech/axcelerator/components/axcelerator_components_small.vhd
|
2
|
12257
|
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- See the file COPYING for the full details of the license.
--
-----------------------------------------------------------------------------
-- Package: components
-- File: components.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: Simple Actel RAM and pad component declarations
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package components is
-- Axcellerator rams
component RAM64K36
port(
WRAD0, WRAD1, WRAD2, WRAD3, WRAD4, WRAD5, WRAD6, WRAD7, WRAD8, WRAD9, WRAD10,
WRAD11, WRAD12, WRAD13, WRAD14, WRAD15, WD0, WD1, WD2, WD3, WD4, WD5, WD6,
WD7, WD8, WD9, WD10, WD11, WD12, WD13, WD14, WD15, WD16, WD17, WD18, WD19,
WD20, WD21, WD22, WD23, WD24, WD25, WD26, WD27, WD28, WD29, WD30, WD31, WD32,
WD33, WD34, WD35, WEN, DEPTH0, DEPTH1, DEPTH2, DEPTH3, WW0, WW1, WW2, WCLK,
RDAD0, RDAD1, RDAD2, RDAD3, RDAD4, RDAD5, RDAD6, RDAD7, RDAD8, RDAD9, RDAD10,
RDAD11, RDAD12, RDAD13, RDAD14, RDAD15, REN, RW0, RW1, RW2, RCLK : in std_logic;
RD0, RD1, RD2, RD3, RD4, RD5, RD6, RD7, RD8, RD9, RD10, RD11, RD12, RD13,
RD14, RD15, RD16, RD17, RD18, RD19, RD20, RD21, RD22, RD23, RD24, RD25, RD26,
RD27, RD28, RD29, RD30, RD31, RD32, RD33, RD34, RD35 : out std_logic);
end component;
attribute syn_black_box : boolean;
attribute syn_black_box of RAM64K36 : component is true;
attribute syn_tco1 : string;
attribute syn_tco2 : string;
attribute syn_tco1 of RAM64K36 : component is
"RCLK->RD0,RD1,RD2,RD3,RD4,RD5,RD6,RD7,RD8,RD9,RD10,RD11,RD12,RD13,RD14,RD15,RD16,RD17,RD18,RD19,RD20,RD21,RD22,RD23,RD24,RD25,RD26,RD27,RD28,RD29,RD30,RD31,RD32,RD33,RD34,RD35 = 4.0";
-- Buffers
component inbuf_lvds port(Y : out std_logic; PADP : in std_logic; PADN : in std_logic); end component;
component outbuf_lvds port(D : in std_logic; PADP : out std_logic; PADN : out std_logic); end component;
component hclkbuf
port( pad : in std_logic; y : out std_logic); end component;
component clkbuf port(pad : in std_logic; y : out std_logic); end component;
component inbuf port(pad :in std_logic; y : out std_logic); end component;
component bibuf port(
d, e : in std_logic; pad : inout std_logic; y : out std_logic);
end component;
component outbuf port(d : in std_logic; pad : out std_logic); end component;
component outbuf_f_8 port(d : in std_logic; pad : out std_logic); end component;
component outbuf_f_12 port(d : in std_logic; pad : out std_logic); end component;
component outbuf_f_16 port(d : in std_logic; pad : out std_logic); end component;
component outbuf_f_24 port(d : in std_logic; pad : out std_logic); end component;
component tribuff port(d, e : in std_logic; pad : out std_logic); end component;
component hclkint port(a : in std_ulogic; y : out std_ulogic); end component;
component clkint port(a : in std_ulogic; y : out std_ulogic); end component;
component hclkbuf_pci
port( pad : in std_logic; y : out std_logic); end component;
component clkbuf_pci port(pad : in std_logic; y : out std_logic); end component;
component inbuf_pci port(pad :in std_logic; y : out std_logic); end component;
attribute syn_tpd11 : string;
attribute syn_tpd11 of inbuf_pci : component is "pad -> y = 2.0";
component bibuf_pci port(
d, e : in std_logic; pad : inout std_logic; y : out std_logic);
end component;
attribute syn_tpd12 : string;
attribute syn_tpd12 of bibuf_pci : component is "pad -> y = 2.0";
component outbuf_pci port(d : in std_logic; pad : out std_logic); end component;
attribute syn_tpd13 : string;
attribute syn_tpd13 of outbuf_pci : component is "d -> pad = 2.0";
component tribuff_pci port(d, e : in std_logic; pad : out std_logic); end component;
attribute syn_tpd14 : string;
attribute syn_tpd14 of tribuff_pci : component is "d,e -> pad = 2.0";
-- 1553 -------------------------------
component add1 is
port(
a : in std_logic;
b : in std_logic;
fci : in std_logic;
s : out std_logic;
fco : out std_logic);
end component add1;
component and2 is
port(
a : in std_logic;
b : in std_logic;
y : out std_logic);
end component and2;
component and2a is
port(
a : in std_logic;
b : in std_logic;
y : out std_logic);
end component and2a;
component and2b is
port(
a : in std_logic;
b : in std_logic;
y : out std_logic);
end component and2b;
component and3 is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end component and3;
component and3a is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end component and3a;
component and3b is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end component and3b;
component and3c is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end component and3c;
component and4 is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end component and4;
component and4a is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end component and4a;
component and4b is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end component and4b;
component and4c is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end component and4c;
component buff is
port(
a : in std_logic;
y : out std_logic);
end component buff;
component cm8 is
port(
d0 : in std_logic;
d1 : in std_logic;
d2 : in std_logic;
d3 : in std_logic;
s00 : in std_logic;
s01 : in std_logic;
s10 : in std_logic;
s11 : in std_logic;
y : out std_logic);
end component cm8;
component cm8inv is
port(
a : in std_logic;
y : out std_logic);
end component cm8inv;
component df1 is
port(
d : in std_logic;
clk : in std_logic;
q : out std_logic);
end component df1;
component dfc1b is
port(
d : in std_logic;
clk : in std_logic;
clr : in std_logic;
q : out std_logic);
end component dfc1b;
component dfc1c is
port(
d : in std_logic;
clk : in std_logic;
clr : in std_logic;
q : out std_logic);
end component dfc1c;
component dfc1d is
port(
d : in std_logic;
clk : in std_logic;
clr : in std_logic;
q : out std_logic);
end component dfc1d;
component dfe1b is
port(
d : in std_logic;
e : in std_logic;
clk : in std_logic;
q : out std_logic);
end component dfe1b;
component dfe3c is
port(
d : in std_logic;
e : in std_logic;
clk : in std_logic;
clr : in std_logic;
q : out std_logic);
end component dfe3c;
component dfe4f is
port(
d : in std_logic;
e : in std_logic;
clk : in std_logic;
pre : in std_logic;
q : out std_logic);
end component dfe4f;
component dfp1 is
port(
d : in std_logic;
clk : in std_logic;
pre : in std_logic;
q : out std_logic);
end component dfp1;
component dfp1b is
port(
d : in std_logic;
clk : in std_logic;
pre : in std_logic;
q : out std_logic);
end component dfp1b;
component dfp1d is
port(
d : in std_logic;
clk : in std_logic;
pre : in std_logic;
q : out std_logic);
end component dfp1d;
component dfm
port(
clk : in std_logic;
s : in std_logic;
a : in std_logic;
b : in std_logic;
q : out std_logic);
end component;
component gnd is
port(
y : out std_logic);
end component gnd;
component inv is
port(
a : in std_logic;
y : out std_logic);
end component inv;
component nand4 is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end component nand4;
component or2 is
port(
a : in std_logic;
b : in std_logic;
y : out std_logic);
end component or2;
component or2a is
port(
a : in std_logic;
b : in std_logic;
y : out std_logic);
end component or2a;
component or2b is
port(
a : in std_logic;
b : in std_logic;
y : out std_logic);
end component or2b;
component or3 is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end component or3;
component or3a is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end component or3a;
component or3b is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end component or3b;
component or3c is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end component or3c;
component or4 is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end component or4;
component or4a is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end component or4a;
component or4b is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end component or4b;
component or4c is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end component or4c;
component or4d is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
y : out std_logic);
end component or4d;
component sub1 is
port(
a : in std_logic;
b : in std_logic;
fci : in std_logic;
s : out std_logic;
fco : out std_logic);
end component sub1;
component vcc is
port(
y : out std_logic);
end component vcc;
component xa1 is
port(
a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end component xa1;
component xnor2 is
port(
a : in std_logic;
b : in std_logic;
y : out std_logic);
end component xnor2;
component xor2 is
port(
a : in std_logic;
b : in std_logic;
y : out std_logic);
end component xor2;
component xor4 is
port(a,b,c,d : in std_logic;
y : out std_logic);
end component xor4;
component mx2
port(
a : in std_logic;
s : in std_logic;
b : in std_logic;
y : out std_logic);
end component;
component ax1c
port(
a: in std_logic;
b: in std_logic;
c: in std_logic;
y: out std_logic);
end component;
component df1b
port(
d : in std_logic;
clk : in std_logic;
q : out std_logic);
end component;
component dfe1b
port(
d : in std_logic;
e : in std_logic;
clk : in std_logic;
q : out std_logic);
end component;
component df1
port(
d : in std_logic;
clk : in std_logic;
q : out std_logic);
end component;
end;
|
mit
|
chcbaram/FPGA
|
zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Template_PSL_Base/Libraries/ZPUino_1/ZPUino_Papilio_Pro_V1.vhd
|
13
|
45307
|
--
--
-- ZPUINO implementation on Gadget Factory 'Papilio Pro' Board
--
-- Copyright 2011 Alvaro Lopes <[email protected]>
--
-- Vanilla Variant
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
use board.zpuino_config.all;
use board.wishbonepkg.all;
library work;
use work.pad.all;
use work.papilio_pkg.all;
entity ZPUino_Papilio_Pro_V1 is
port (
--32Mhz input clock is converted to a 96Mhz clock
CLK: in std_logic;
--Clock outputs to be used in schematic
clk_96Mhz: out std_logic; --This is the clock that the system runs on.
clk_1Mhz: out std_logic; --This is a 1Mhz clock for symbols like the C64 SID chip.
clk_osc_32Mhz: out std_logic; --This is the 32Mhz clock from external oscillator.
-- Connection to the main SPI flash
SPI_SCK: out std_logic;
SPI_MISO: in std_logic;
SPI_MOSI: out std_logic;
SPI_CS: out std_logic;
gpio_bus_in : in std_logic_vector(97 downto 0);
gpio_bus_out : out std_logic_vector(147 downto 0);
-- UART (FTDI) connection
TXD: out std_logic;
RXD: in std_logic;
DRAM_ADDR : OUT STD_LOGIC_VECTOR (12 downto 0);
DRAM_BA : OUT STD_LOGIC_VECTOR (1 downto 0);
DRAM_CAS_N : OUT STD_LOGIC;
DRAM_CKE : OUT STD_LOGIC;
DRAM_CLK : OUT STD_LOGIC;
DRAM_CS_N : OUT STD_LOGIC;
DRAM_DQ : INOUT STD_LOGIC_VECTOR(15 downto 0);
DRAM_DQM : OUT STD_LOGIC_VECTOR(1 downto 0);
DRAM_RAS_N : OUT STD_LOGIC;
DRAM_WE_N : OUT STD_LOGIC;
-- The LED
LED: out std_logic;
--There are more bits in the address for this wishbone connection
wishbone_slot_video_in : in std_logic_vector(63 downto 0);
wishbone_slot_video_out : out std_logic_vector(33 downto 0);
vgaclkout: out std_logic;
--Input and output reversed for the master
wishbone_slot_5_in : out std_logic_vector(61 downto 0);
wishbone_slot_5_out : in std_logic_vector(33 downto 0);
wishbone_slot_6_in : out std_logic_vector(61 downto 0);
wishbone_slot_6_out : in std_logic_vector(33 downto 0);
wishbone_slot_8_in : out std_logic_vector(61 downto 0);
wishbone_slot_8_out : in std_logic_vector(33 downto 0);
wishbone_slot_9_in : out std_logic_vector(61 downto 0);
wishbone_slot_9_out : in std_logic_vector(33 downto 0);
wishbone_slot_10_in : out std_logic_vector(61 downto 0);
wishbone_slot_10_out : in std_logic_vector(33 downto 0);
wishbone_slot_11_in : out std_logic_vector(61 downto 0);
wishbone_slot_11_out : in std_logic_vector(33 downto 0);
wishbone_slot_12_in : out std_logic_vector(61 downto 0);
wishbone_slot_12_out : in std_logic_vector(33 downto 0);
wishbone_slot_13_in : out std_logic_vector(61 downto 0);
wishbone_slot_13_out : in std_logic_vector(33 downto 0);
wishbone_slot_14_in : out std_logic_vector(61 downto 0);
wishbone_slot_14_out : in std_logic_vector(33 downto 0)
-- wishbone_slot_15_in : out std_logic_vector(61 downto 0);
-- wishbone_slot_15_out : in std_logic_vector(33 downto 0)
);
-- attribute PERIOD: string;
-- attribute PERIOD of CLK: signal is "31.25ns";
--
-- attribute LOC: string;
-- attribute LOC of CLK: signal is "P94";
-- attribute LOC of RXD: signal is "P101";
-- attribute LOC of TXD: signal is "P105";
-- attribute LOC of SPI_CS: signal is "P38";
-- attribute LOC of SPI_SCK: signal is "P70";
-- attribute LOC of SPI_MISO: signal is "P65";
-- attribute LOC of SPI_MOSI: signal is "P64";
-- attribute LOC of DRAM_ADDR: signal is "P34 P35 P141 P40 P41 P43 P44 P45 P46 P137 P138 P139 P140";
-- attribute LOC of DRAM_DQ: signal is "P30 P29 P27 P26 P24 P23 P22 P21 P8 P16 P15 P14 P12 P11 P10 P9";
-- attribute LOC of DRAM_DQM: signal is "P17 P7";
-- attribute LOC of DRAM_BA: signal is "P142 P143";
-- attribute LOC of DRAM_WE_N: signal is "P6";
-- attribute LOC of DRAM_CAS_N: signal is "P5";
-- attribute LOC of DRAM_RAS_N: signal is "P2";
-- attribute LOC of DRAM_CS_N: signal is "P1";
-- attribute LOC of DRAM_CLK: signal is "P32";
-- attribute LOC of DRAM_CKE: signal is "P33";
--
-- attribute SLEW: string;
-- attribute SLEW of DRAM_ADDR: signal is "FAST";
-- attribute SLEW of DRAM_DQ: signal is "FAST";
-- attribute SLEW of DRAM_DQM: signal is "FAST";
-- attribute SLEW of DRAM_BA: signal is "FAST";
-- attribute SLEW of DRAM_WE_N: signal is "FAST";
-- attribute SLEW of DRAM_CAS_N: signal is "FAST";
-- attribute SLEW of DRAM_RAS_N: signal is "FAST";
-- attribute SLEW of DRAM_CS_N: signal is "FAST";
-- attribute SLEW of DRAM_CLK: signal is "FAST";
-- attribute SLEW of DRAM_CKE: signal is "FAST";
end entity ZPUino_Papilio_Pro_V1;
architecture behave of ZPUino_Papilio_Pro_V1 is
component zpuino_debug_jtag_spartan6 is
port (
jtag_data_chain_in: in std_logic_vector(98 downto 0);
jtag_ctrl_chain_out: out std_logic_vector(11 downto 0)
);
end component;
signal jtag_data_chain_in: std_logic_vector(98 downto 0);
signal jtag_ctrl_chain_out: std_logic_vector(11 downto 0);
component clkgen is
port (
clkin: in std_logic;
rstin: in std_logic;
clkout: out std_logic;
clkout1: out std_logic;
clkout2: out std_logic;
clk_1Mhz_out: out std_logic;
clk_osc_32Mhz: out std_logic;
vgaclkout: out std_logic;
rstout: out std_logic
);
end component;
component wb_bootloader is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(31 downto 0);
wb_adr_i: in std_logic_vector(11 downto 2);
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_stall_o: out std_logic;
wb2_dat_o: out std_logic_vector(31 downto 0);
wb2_adr_i: in std_logic_vector(11 downto 2);
wb2_cyc_i: in std_logic;
wb2_stb_i: in std_logic;
wb2_ack_o: out std_logic;
wb2_stall_o: out std_logic
);
end component;
signal sysrst: std_logic;
signal sysclk: std_logic;
signal clkgen_rst: std_logic;
signal wb_clk_i: std_logic;
signal wb_rst_i: std_logic;
-- signal gpio_o: std_logic_vector(zpuino_gpio_count-1 downto 0);
-- signal gpio_t: std_logic_vector(zpuino_gpio_count-1 downto 0);
-- signal gpio_i: std_logic_vector(zpuino_gpio_count-1 downto 0);
signal gpio_o_reg: std_logic_vector(48 downto 0);
constant spp_cap_in: std_logic_vector(48 downto 0) :=
"0" & -- SPI CS
"0000000000000000" & -- Wing C
"0000000000000000" & -- Wing B
"0000000000000000"; -- Wing A
constant spp_cap_out: std_logic_vector(48 downto 0) :=
"0" & -- SPI CS
"0000000000000000" & -- Wing C
"0000000000000000" & -- Wing B
"0000000000000000"; -- Wing A
-- constant spp_cap_in: std_logic_vector(48 downto 0) :=
-- "0" & -- SPI CS
-- "1111111111111111" & -- Wing C
-- "1111111111111111" & -- Wing B
-- "1111111111111111"; -- Wing A
--
-- constant spp_cap_out: std_logic_vector(48 downto 0) :=
-- "0" & -- SPI CS
-- "1111111111111111" & -- Wing C
-- "1111111111111111" & -- Wing B
-- "1111111111111111"; -- Wing A
-- I/O Signals
signal slot_cyc: slot_std_logic_type;
signal slot_we: slot_std_logic_type;
signal slot_stb: slot_std_logic_type;
signal slot_read: slot_cpuword_type;
signal slot_write: slot_cpuword_type;
signal slot_address:slot_address_type;
signal slot_ack: slot_std_logic_type;
signal slot_interrupt: slot_std_logic_type;
-- 2nd SPI signals
signal spi2_mosi: std_logic;
signal spi2_miso: std_logic;
signal spi2_sck: std_logic;
-- GPIO Periperal Pin Select
-- signal gpio_spp_data: std_logic_vector(zpuino_gpio_count-1 downto 0);
-- signal gpio_spp_read: std_logic_vector(zpuino_gpio_count-1 downto 0);
-- Timer connections
signal timers_interrupt: std_logic_vector(1 downto 0);
signal timers_pwm: std_logic_vector(1 downto 0);
-- Sigmadelta output
signal sigmadelta_spp_data: std_logic_vector(1 downto 0);
-- main SPI signals
signal spi_pf_miso: std_logic;
signal spi_pf_mosi: std_logic;
signal spi_pf_sck: std_logic;
-- UART signals
signal rx: std_logic;
signal tx: std_logic;
signal sysclk_sram_we, sysclk_sram_wen: std_ulogic;
signal ram_wb_ack_o: std_logic;
signal ram_wb_dat_i: std_logic_vector(wordSize-1 downto 0);
signal ram_wb_dat_o: std_logic_vector(wordSize-1 downto 0);
signal ram_wb_adr_i: std_logic_vector(maxAddrBitIncIO downto 0);
signal ram_wb_cyc_i: std_logic;
signal ram_wb_stb_i: std_logic;
signal ram_wb_sel_i: std_logic_vector(3 downto 0);
signal ram_wb_we_i: std_logic;
signal ram_wb_stall_o: std_logic;
signal np_ram_wb_ack_o: std_logic;
signal np_ram_wb_dat_i: std_logic_vector(wordSize-1 downto 0);
signal np_ram_wb_dat_o: std_logic_vector(wordSize-1 downto 0);
signal np_ram_wb_adr_i: std_logic_vector(maxAddrBitIncIO downto 0);
signal np_ram_wb_cyc_i: std_logic;
signal np_ram_wb_stb_i: std_logic;
signal np_ram_wb_sel_i: std_logic_vector(3 downto 0);
signal np_ram_wb_we_i: std_logic;
signal sram_wb_ack_o: std_logic;
signal sram_wb_dat_i: std_logic_vector(wordSize-1 downto 0);
signal sram_wb_dat_o: std_logic_vector(wordSize-1 downto 0);
signal sram_wb_adr_i: std_logic_vector(maxAddrBitIncIO downto 0);
signal sram_wb_cyc_i: std_logic;
signal sram_wb_stb_i: std_logic;
signal sram_wb_we_i: std_logic;
signal sram_wb_sel_i: std_logic_vector(3 downto 0);
signal sram_wb_stall_o: std_logic;
signal rom_wb_ack_o: std_logic;
signal rom_wb_dat_o: std_logic_vector(wordSize-1 downto 0);
signal rom_wb_adr_i: std_logic_vector(maxAddrBitIncIO downto 0);
signal rom_wb_cyc_i: std_logic;
signal rom_wb_stb_i: std_logic;
signal rom_wb_cti_i: std_logic_vector(2 downto 0);
signal rom_wb_stall_o: std_logic;
signal sram_rom_wb_ack_o: std_logic;
signal sram_rom_wb_dat_o: std_logic_vector(wordSize-1 downto 0);
signal sram_rom_wb_adr_i: std_logic_vector(maxAddrBit downto 2);
signal sram_rom_wb_cyc_i: std_logic;
signal sram_rom_wb_stb_i: std_logic;
signal sram_rom_wb_cti_i: std_logic_vector(2 downto 0);
signal sram_rom_wb_stall_o: std_logic;
signal prom_rom_wb_ack_o: std_logic;
signal prom_rom_wb_dat_o: std_logic_vector(wordSize-1 downto 0);
signal prom_rom_wb_adr_i: std_logic_vector(maxAddrBit downto 2);
signal prom_rom_wb_cyc_i: std_logic;
signal prom_rom_wb_stb_i: std_logic;
signal prom_rom_wb_cti_i: std_logic_vector(2 downto 0);
signal prom_rom_wb_stall_o: std_logic;
signal memory_enable: std_logic;
component sdram_ctrl is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(31 downto 0);
wb_dat_i: in std_logic_vector(31 downto 0);
wb_adr_i: in std_logic_vector(maxIOBit downto minIOBit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_sel_i: in std_logic_vector(3 downto 0);
wb_ack_o: out std_logic;
wb_stall_o: out std_logic;
-- extra clocking
clk_off_3ns: in std_logic;
-- SDRAM signals
DRAM_ADDR : OUT STD_LOGIC_VECTOR (11 downto 0);
DRAM_BA : OUT STD_LOGIC_VECTOR (1 downto 0);
DRAM_CAS_N : OUT STD_LOGIC;
DRAM_CKE : OUT STD_LOGIC;
DRAM_CLK : OUT STD_LOGIC;
DRAM_CS_N : OUT STD_LOGIC;
DRAM_DQ : INOUT STD_LOGIC_VECTOR(15 downto 0);
DRAM_DQM : OUT STD_LOGIC_VECTOR(1 downto 0);
DRAM_RAS_N : OUT STD_LOGIC;
DRAM_WE_N : OUT STD_LOGIC
);
end component sdram_ctrl;
component wb_master_np_to_slave_p is
generic (
ADDRESS_HIGH: integer := maxIObit;
ADDRESS_LOW: integer := maxIObit
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master signals
m_wb_dat_o: out std_logic_vector(31 downto 0);
m_wb_dat_i: in std_logic_vector(31 downto 0);
m_wb_adr_i: in std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
m_wb_sel_i: in std_logic_vector(3 downto 0);
m_wb_cti_i: in std_logic_vector(2 downto 0);
m_wb_we_i: in std_logic;
m_wb_cyc_i: in std_logic;
m_wb_stb_i: in std_logic;
m_wb_ack_o: out std_logic;
-- Slave signals
s_wb_dat_i: in std_logic_vector(31 downto 0);
s_wb_dat_o: out std_logic_vector(31 downto 0);
s_wb_adr_o: out std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
s_wb_sel_o: out std_logic_vector(3 downto 0);
s_wb_cti_o: out std_logic_vector(2 downto 0);
s_wb_we_o: out std_logic;
s_wb_cyc_o: out std_logic;
s_wb_stb_o: out std_logic;
s_wb_ack_i: in std_logic;
s_wb_stall_i: in std_logic
);
end component;
signal sigmadelta_spp_en: std_logic_vector(1 downto 0);
signal sysclk_1mhz: std_logic;
signal wishbone_slot_video_in_record : wishbone_bus_in_type;
signal wishbone_slot_video_out_record : wishbone_bus_out_type;
signal wishbone_slot_5_in_record : wishbone_bus_in_type;
signal wishbone_slot_5_out_record : wishbone_bus_out_type;
signal wishbone_slot_6_in_record : wishbone_bus_in_type;
signal wishbone_slot_6_out_record : wishbone_bus_out_type;
signal wishbone_slot_8_in_record : wishbone_bus_in_type;
signal wishbone_slot_8_out_record : wishbone_bus_out_type;
signal wishbone_slot_9_in_record : wishbone_bus_in_type;
signal wishbone_slot_9_out_record : wishbone_bus_out_type;
signal wishbone_slot_10_in_record : wishbone_bus_in_type;
signal wishbone_slot_10_out_record : wishbone_bus_out_type;
signal wishbone_slot_11_in_record : wishbone_bus_in_type;
signal wishbone_slot_11_out_record : wishbone_bus_out_type;
signal wishbone_slot_12_in_record : wishbone_bus_in_type;
signal wishbone_slot_12_out_record : wishbone_bus_out_type;
signal wishbone_slot_13_in_record : wishbone_bus_in_type;
signal wishbone_slot_13_out_record : wishbone_bus_out_type;
signal wishbone_slot_14_in_record : wishbone_bus_in_type;
signal wishbone_slot_14_out_record : wishbone_bus_out_type;
-- signal wishbone_slot_15_in_record : wishbone_bus_in_type;
-- signal wishbone_slot_15_out_record : wishbone_bus_out_type;
signal gpio_bus_in_record : gpio_bus_in_type;
signal gpio_bus_out_record : gpio_bus_out_type;
-- Papilio Note: Place your signal statements here. #Signal
begin
-- Unpack the wishbone array into a record so the modules code is not confusing.
-- These are backwards for the master.
-- wishbone_slot_video_in_record.wb_clk_i <= wishbone_slot_video_in(61);
-- wishbone_slot_video_in_record.wb_rst_i <= wishbone_slot_video_in(60);
-- wishbone_slot_video_in_record.wb_dat_i <= wishbone_slot_video_in(59 downto 28);
-- wishbone_slot_video_in_record.wb_adr_i <= wishbone_slot_video_in(27 downto 3);
-- wishbone_slot_video_in_record.wb_we_i <= wishbone_slot_video_in(2);
-- wishbone_slot_video_in_record.wb_cyc_i <= wishbone_slot_video_in(1);
-- wishbone_slot_video_in_record.wb_stb_i <= wishbone_slot_video_in(0);
-- wishbone_slot_video_out(33 downto 2) <= wishbone_slot_video_out_record.wb_dat_o;
-- wishbone_slot_video_out(1) <= wishbone_slot_video_out_record.wb_ack_o;
-- wishbone_slot_video_out(0) <= wishbone_slot_video_out_record.wb_inta_o;
wishbone_slot_5_in(61) <= wishbone_slot_5_in_record.wb_clk_i;
wishbone_slot_5_in(60) <= wishbone_slot_5_in_record.wb_rst_i;
wishbone_slot_5_in(59 downto 28) <= wishbone_slot_5_in_record.wb_dat_i;
wishbone_slot_5_in(27 downto 3) <= wishbone_slot_5_in_record.wb_adr_i;
wishbone_slot_5_in(2) <= wishbone_slot_5_in_record.wb_we_i;
wishbone_slot_5_in(1) <= wishbone_slot_5_in_record.wb_cyc_i;
wishbone_slot_5_in(0) <= wishbone_slot_5_in_record.wb_stb_i;
wishbone_slot_5_out_record.wb_dat_o <= wishbone_slot_5_out(33 downto 2);
wishbone_slot_5_out_record.wb_ack_o <= wishbone_slot_5_out(1);
wishbone_slot_5_out_record.wb_inta_o <= wishbone_slot_5_out(0);
wishbone_slot_6_in(61) <= wishbone_slot_6_in_record.wb_clk_i;
wishbone_slot_6_in(60) <= wishbone_slot_6_in_record.wb_rst_i;
wishbone_slot_6_in(59 downto 28) <= wishbone_slot_6_in_record.wb_dat_i;
wishbone_slot_6_in(27 downto 3) <= wishbone_slot_6_in_record.wb_adr_i;
wishbone_slot_6_in(2) <= wishbone_slot_6_in_record.wb_we_i;
wishbone_slot_6_in(1) <= wishbone_slot_6_in_record.wb_cyc_i;
wishbone_slot_6_in(0) <= wishbone_slot_6_in_record.wb_stb_i;
wishbone_slot_6_out_record.wb_dat_o <= wishbone_slot_6_out(33 downto 2);
wishbone_slot_6_out_record.wb_ack_o <= wishbone_slot_6_out(1);
wishbone_slot_6_out_record.wb_inta_o <= wishbone_slot_6_out(0);
wishbone_slot_8_in(61) <= wishbone_slot_8_in_record.wb_clk_i;
wishbone_slot_8_in(60) <= wishbone_slot_8_in_record.wb_rst_i;
wishbone_slot_8_in(59 downto 28) <= wishbone_slot_8_in_record.wb_dat_i;
wishbone_slot_8_in(27 downto 3) <= wishbone_slot_8_in_record.wb_adr_i;
wishbone_slot_8_in(2) <= wishbone_slot_8_in_record.wb_we_i;
wishbone_slot_8_in(1) <= wishbone_slot_8_in_record.wb_cyc_i;
wishbone_slot_8_in(0) <= wishbone_slot_8_in_record.wb_stb_i;
wishbone_slot_8_out_record.wb_dat_o <= wishbone_slot_8_out(33 downto 2);
wishbone_slot_8_out_record.wb_ack_o <= wishbone_slot_8_out(1);
wishbone_slot_8_out_record.wb_inta_o <= wishbone_slot_8_out(0);
wishbone_slot_9_in(61) <= wishbone_slot_9_in_record.wb_clk_i;
wishbone_slot_9_in(60) <= wishbone_slot_9_in_record.wb_rst_i;
wishbone_slot_9_in(59 downto 28) <= wishbone_slot_9_in_record.wb_dat_i;
wishbone_slot_9_in(27 downto 3) <= wishbone_slot_9_in_record.wb_adr_i;
wishbone_slot_9_in(2) <= wishbone_slot_9_in_record.wb_we_i;
wishbone_slot_9_in(1) <= wishbone_slot_9_in_record.wb_cyc_i;
wishbone_slot_9_in(0) <= wishbone_slot_9_in_record.wb_stb_i;
wishbone_slot_9_out_record.wb_dat_o <= wishbone_slot_9_out(33 downto 2);
wishbone_slot_9_out_record.wb_ack_o <= wishbone_slot_9_out(1);
wishbone_slot_9_out_record.wb_inta_o <= wishbone_slot_9_out(0);
wishbone_slot_10_in(61) <= wishbone_slot_10_in_record.wb_clk_i;
wishbone_slot_10_in(60) <= wishbone_slot_10_in_record.wb_rst_i;
wishbone_slot_10_in(59 downto 28) <= wishbone_slot_10_in_record.wb_dat_i;
wishbone_slot_10_in(27 downto 3) <= wishbone_slot_10_in_record.wb_adr_i;
wishbone_slot_10_in(2) <= wishbone_slot_10_in_record.wb_we_i;
wishbone_slot_10_in(1) <= wishbone_slot_10_in_record.wb_cyc_i;
wishbone_slot_10_in(0) <= wishbone_slot_10_in_record.wb_stb_i;
wishbone_slot_10_out_record.wb_dat_o <= wishbone_slot_10_out(33 downto 2);
wishbone_slot_10_out_record.wb_ack_o <= wishbone_slot_10_out(1);
wishbone_slot_10_out_record.wb_inta_o <= wishbone_slot_10_out(0);
wishbone_slot_11_in(61) <= wishbone_slot_11_in_record.wb_clk_i;
wishbone_slot_11_in(60) <= wishbone_slot_11_in_record.wb_rst_i;
wishbone_slot_11_in(59 downto 28) <= wishbone_slot_11_in_record.wb_dat_i;
wishbone_slot_11_in(27 downto 3) <= wishbone_slot_11_in_record.wb_adr_i;
wishbone_slot_11_in(2) <= wishbone_slot_11_in_record.wb_we_i;
wishbone_slot_11_in(1) <= wishbone_slot_11_in_record.wb_cyc_i;
wishbone_slot_11_in(0) <= wishbone_slot_11_in_record.wb_stb_i;
wishbone_slot_11_out_record.wb_dat_o <= wishbone_slot_11_out(33 downto 2);
wishbone_slot_11_out_record.wb_ack_o <= wishbone_slot_11_out(1);
wishbone_slot_11_out_record.wb_inta_o <= wishbone_slot_11_out(0);
wishbone_slot_12_in(61) <= wishbone_slot_12_in_record.wb_clk_i;
wishbone_slot_12_in(60) <= wishbone_slot_12_in_record.wb_rst_i;
wishbone_slot_12_in(59 downto 28) <= wishbone_slot_12_in_record.wb_dat_i;
wishbone_slot_12_in(27 downto 3) <= wishbone_slot_12_in_record.wb_adr_i;
wishbone_slot_12_in(2) <= wishbone_slot_12_in_record.wb_we_i;
wishbone_slot_12_in(1) <= wishbone_slot_12_in_record.wb_cyc_i;
wishbone_slot_12_in(0) <= wishbone_slot_12_in_record.wb_stb_i;
wishbone_slot_12_out_record.wb_dat_o <= wishbone_slot_12_out(33 downto 2);
wishbone_slot_12_out_record.wb_ack_o <= wishbone_slot_12_out(1);
wishbone_slot_12_out_record.wb_inta_o <= wishbone_slot_12_out(0);
wishbone_slot_13_in(61) <= wishbone_slot_13_in_record.wb_clk_i;
wishbone_slot_13_in(60) <= wishbone_slot_13_in_record.wb_rst_i;
wishbone_slot_13_in(59 downto 28) <= wishbone_slot_13_in_record.wb_dat_i;
wishbone_slot_13_in(27 downto 3) <= wishbone_slot_13_in_record.wb_adr_i;
wishbone_slot_13_in(2) <= wishbone_slot_13_in_record.wb_we_i;
wishbone_slot_13_in(1) <= wishbone_slot_13_in_record.wb_cyc_i;
wishbone_slot_13_in(0) <= wishbone_slot_13_in_record.wb_stb_i;
wishbone_slot_13_out_record.wb_dat_o <= wishbone_slot_13_out(33 downto 2);
wishbone_slot_13_out_record.wb_ack_o <= wishbone_slot_13_out(1);
wishbone_slot_13_out_record.wb_inta_o <= wishbone_slot_13_out(0);
wishbone_slot_14_in(61) <= wishbone_slot_14_in_record.wb_clk_i;
wishbone_slot_14_in(60) <= wishbone_slot_14_in_record.wb_rst_i;
wishbone_slot_14_in(59 downto 28) <= wishbone_slot_14_in_record.wb_dat_i;
wishbone_slot_14_in(27 downto 3) <= wishbone_slot_14_in_record.wb_adr_i;
wishbone_slot_14_in(2) <= wishbone_slot_14_in_record.wb_we_i;
wishbone_slot_14_in(1) <= wishbone_slot_14_in_record.wb_cyc_i;
wishbone_slot_14_in(0) <= wishbone_slot_14_in_record.wb_stb_i;
wishbone_slot_14_out_record.wb_dat_o <= wishbone_slot_14_out(33 downto 2);
wishbone_slot_14_out_record.wb_ack_o <= wishbone_slot_14_out(1);
wishbone_slot_14_out_record.wb_inta_o <= wishbone_slot_14_out(0);
gpio_bus_in_record.gpio_spp_data <= gpio_bus_in(97 downto 49);
gpio_bus_in_record.gpio_i <= gpio_bus_in(48 downto 0);
gpio_bus_out(147) <= gpio_bus_out_record.gpio_clk;
gpio_bus_out(146 downto 98) <= gpio_bus_out_record.gpio_o;
gpio_bus_out(97 downto 49) <= gpio_bus_out_record.gpio_t;
gpio_bus_out(48 downto 0) <= gpio_bus_out_record.gpio_spp_read;
gpio_bus_out_record.gpio_o <= gpio_o_reg;
gpio_bus_out_record.gpio_clk <= sysclk;
LED <= '0';
wb_clk_i <= sysclk;
wb_rst_i <= sysrst;
--Wishbone 5
wishbone_slot_5_in_record.wb_clk_i <= sysclk;
wishbone_slot_5_in_record.wb_rst_i <= sysrst;
slot_read(5) <= wishbone_slot_5_out_record.wb_dat_o;
wishbone_slot_5_in_record.wb_dat_i <= slot_write(5);
wishbone_slot_5_in_record.wb_adr_i <= slot_address(5);
wishbone_slot_5_in_record.wb_we_i <= slot_we(5);
wishbone_slot_5_in_record.wb_cyc_i <= slot_cyc(5);
wishbone_slot_5_in_record.wb_stb_i <= slot_stb(5);
slot_ack(5) <= wishbone_slot_5_out_record.wb_ack_o;
slot_interrupt(5) <= wishbone_slot_5_out_record.wb_inta_o;
--Wishbone 6
wishbone_slot_6_in_record.wb_clk_i <= sysclk;
wishbone_slot_6_in_record.wb_rst_i <= sysrst;
slot_read(6) <= wishbone_slot_6_out_record.wb_dat_o;
wishbone_slot_6_in_record.wb_dat_i <= slot_write(6);
wishbone_slot_6_in_record.wb_adr_i <= slot_address(6);
wishbone_slot_6_in_record.wb_we_i <= slot_we(6);
wishbone_slot_6_in_record.wb_cyc_i <= slot_cyc(6);
wishbone_slot_6_in_record.wb_stb_i <= slot_stb(6);
slot_ack(6) <= wishbone_slot_6_out_record.wb_ack_o;
slot_interrupt(6) <= wishbone_slot_6_out_record.wb_inta_o;
--Wishbone 8
wishbone_slot_8_in_record.wb_clk_i <= sysclk;
wishbone_slot_8_in_record.wb_rst_i <= sysrst;
slot_read(8) <= wishbone_slot_8_out_record.wb_dat_o;
wishbone_slot_8_in_record.wb_dat_i <= slot_write(8);
wishbone_slot_8_in_record.wb_adr_i <= slot_address(8);
wishbone_slot_8_in_record.wb_we_i <= slot_we(8);
wishbone_slot_8_in_record.wb_cyc_i <= slot_cyc(8);
wishbone_slot_8_in_record.wb_stb_i <= slot_stb(8);
slot_ack(8) <= wishbone_slot_8_out_record.wb_ack_o;
slot_interrupt(8) <= wishbone_slot_8_out_record.wb_inta_o;
--Wishbone 9
wishbone_slot_9_in_record.wb_clk_i <= sysclk;
wishbone_slot_9_in_record.wb_rst_i <= sysrst;
slot_read(9) <= wishbone_slot_9_out_record.wb_dat_o;
wishbone_slot_9_in_record.wb_dat_i <= slot_write(9);
wishbone_slot_9_in_record.wb_adr_i <= slot_address(9);
wishbone_slot_9_in_record.wb_we_i <= slot_we(9);
wishbone_slot_9_in_record.wb_cyc_i <= slot_cyc(9);
wishbone_slot_9_in_record.wb_stb_i <= slot_stb(9);
slot_ack(9) <= wishbone_slot_9_out_record.wb_ack_o;
slot_interrupt(9) <= wishbone_slot_9_out_record.wb_inta_o;
--Wishbone 10
wishbone_slot_10_in_record.wb_clk_i <= sysclk;
wishbone_slot_10_in_record.wb_rst_i <= sysrst;
slot_read(10) <= wishbone_slot_10_out_record.wb_dat_o;
wishbone_slot_10_in_record.wb_dat_i <= slot_write(10);
wishbone_slot_10_in_record.wb_adr_i <= slot_address(10);
wishbone_slot_10_in_record.wb_we_i <= slot_we(10);
wishbone_slot_10_in_record.wb_cyc_i <= slot_cyc(10);
wishbone_slot_10_in_record.wb_stb_i <= slot_stb(10);
slot_ack(10) <= wishbone_slot_10_out_record.wb_ack_o;
slot_interrupt(10) <= wishbone_slot_10_out_record.wb_inta_o;
--Wishbone 11
wishbone_slot_11_in_record.wb_clk_i <= sysclk;
wishbone_slot_11_in_record.wb_rst_i <= sysrst;
slot_read(11) <= wishbone_slot_11_out_record.wb_dat_o;
wishbone_slot_11_in_record.wb_dat_i <= slot_write(11);
wishbone_slot_11_in_record.wb_adr_i <= slot_address(11);
wishbone_slot_11_in_record.wb_we_i <= slot_we(11);
wishbone_slot_11_in_record.wb_cyc_i <= slot_cyc(11);
wishbone_slot_11_in_record.wb_stb_i <= slot_stb(11);
slot_ack(11) <= wishbone_slot_11_out_record.wb_ack_o;
slot_interrupt(11) <= wishbone_slot_11_out_record.wb_inta_o;
--Wishbone 12
wishbone_slot_12_in_record.wb_clk_i <= sysclk;
wishbone_slot_12_in_record.wb_rst_i <= sysrst;
slot_read(12) <= wishbone_slot_12_out_record.wb_dat_o;
wishbone_slot_12_in_record.wb_dat_i <= slot_write(12);
wishbone_slot_12_in_record.wb_adr_i <= slot_address(12);
wishbone_slot_12_in_record.wb_we_i <= slot_we(12);
wishbone_slot_12_in_record.wb_cyc_i <= slot_cyc(12);
wishbone_slot_12_in_record.wb_stb_i <= slot_stb(12);
slot_ack(12) <= wishbone_slot_12_out_record.wb_ack_o;
slot_interrupt(12) <= wishbone_slot_12_out_record.wb_inta_o;
--Wishbone 13
wishbone_slot_13_in_record.wb_clk_i <= sysclk;
wishbone_slot_13_in_record.wb_rst_i <= sysrst;
slot_read(13) <= wishbone_slot_13_out_record.wb_dat_o;
wishbone_slot_13_in_record.wb_dat_i <= slot_write(13);
wishbone_slot_13_in_record.wb_adr_i <= slot_address(13);
wishbone_slot_13_in_record.wb_we_i <= slot_we(13);
wishbone_slot_13_in_record.wb_cyc_i <= slot_cyc(13);
wishbone_slot_13_in_record.wb_stb_i <= slot_stb(13);
slot_ack(13) <= wishbone_slot_13_out_record.wb_ack_o;
slot_interrupt(13) <= wishbone_slot_13_out_record.wb_inta_o;
--Wishbone 14
wishbone_slot_14_in_record.wb_clk_i <= sysclk;
wishbone_slot_14_in_record.wb_rst_i <= sysrst;
slot_read(14) <= wishbone_slot_14_out_record.wb_dat_o;
wishbone_slot_14_in_record.wb_dat_i <= slot_write(14);
wishbone_slot_14_in_record.wb_adr_i <= slot_address(14);
wishbone_slot_14_in_record.wb_we_i <= slot_we(14);
wishbone_slot_14_in_record.wb_cyc_i <= slot_cyc(14);
wishbone_slot_14_in_record.wb_stb_i <= slot_stb(14);
slot_ack(14) <= wishbone_slot_14_out_record.wb_ack_o;
slot_interrupt(14) <= wishbone_slot_14_out_record.wb_inta_o;
rstgen: zpuino_serialreset
generic map (
SYSTEM_CLOCK_MHZ => 96
)
port map (
clk => sysclk,
rx => rx,
rstin => clkgen_rst,
rstout => sysrst
);
clkgen_inst: clkgen
port map (
clkin => clk,
rstin => '0' ,
clkout => sysclk,
clkout1 => sysclk_sram_we,
clkout2 => sysclk_sram_wen,
clk_1Mhz_out => clk_1Mhz,
clk_osc_32Mhz => clk_osc_32Mhz,
vgaclkout => vgaclkout,
rstout => clkgen_rst
);
clk_96Mhz <= sysclk;
-- Other ports are special, we need to avoid outputs on input-only pins
ibufrx: IPAD port map ( PAD => RXD, O => rx, C => sysclk );
ibufmiso: IPAD port map ( PAD => SPI_MISO, O => spi_pf_miso, C => sysclk );
obuftx: OPAD port map ( I => tx, PAD => TXD );
ospiclk: OPAD port map ( I => spi_pf_sck, PAD => SPI_SCK );
ospics: OPAD port map ( I => gpio_o_reg(48), PAD => SPI_CS );
ospimosi: OPAD port map ( I => spi_pf_mosi, PAD => SPI_MOSI );
--oled: OPAD port map ( I => gpio_o_reg(49), PAD => LED );
zpuino:zpuino_top_icache
port map (
clk => sysclk,
rst => sysrst,
slot_cyc => slot_cyc,
slot_we => slot_we,
slot_stb => slot_stb,
slot_read => slot_read,
slot_write => slot_write,
slot_address => slot_address,
slot_ack => slot_ack,
slot_interrupt=> slot_interrupt,
m_wb_dat_o => open,
m_wb_dat_i => (others => 'X'),
m_wb_adr_i => (others => 'X'),
m_wb_we_i => '0',
m_wb_cyc_i => '0',
m_wb_stb_i => '0',
m_wb_ack_o => open,
memory_enable => memory_enable,
ram_wb_ack_i => np_ram_wb_ack_o,
ram_wb_stall_i => '0',--np_ram_wb_stall_o,
ram_wb_dat_o => np_ram_wb_dat_i,
ram_wb_dat_i => np_ram_wb_dat_o,
ram_wb_adr_o => np_ram_wb_adr_i(maxAddrBit downto 0),
ram_wb_cyc_o => np_ram_wb_cyc_i,
ram_wb_stb_o => np_ram_wb_stb_i,
ram_wb_sel_o => np_ram_wb_sel_i,
ram_wb_we_o => np_ram_wb_we_i,
rom_wb_ack_i => rom_wb_ack_o,
rom_wb_stall_i => rom_wb_stall_o,
rom_wb_dat_i => rom_wb_dat_o,
rom_wb_adr_o => rom_wb_adr_i(maxAddrBit downto 0),
rom_wb_cyc_o => rom_wb_cyc_i,
rom_wb_stb_o => rom_wb_stb_i,
-- No debug unit connected
dbg_reset => open,
jtag_data_chain_out => open, --jtag_data_chain_in,
jtag_ctrl_chain_in => (others => '0') --jtag_ctrl_chain_out
);
--dbg: zpuino_debug_jtag_spartan6
-- port map (
-- jtag_data_chain_in => jtag_data_chain_in,
-- jtag_ctrl_chain_out => jtag_ctrl_chain_out
-- );
memarb: wbarb2_1
generic map (
ADDRESS_HIGH => maxAddrBit,
ADDRESS_LOW => 2
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
m0_wb_dat_o => ram_wb_dat_o,
m0_wb_dat_i => ram_wb_dat_i,
m0_wb_adr_i => ram_wb_adr_i(maxAddrBit downto 2),
m0_wb_sel_i => ram_wb_sel_i,
m0_wb_cti_i => CTI_CYCLE_CLASSIC,
m0_wb_we_i => ram_wb_we_i,
m0_wb_cyc_i => ram_wb_cyc_i,
m0_wb_stb_i => ram_wb_stb_i,
m0_wb_ack_o => ram_wb_ack_o,
m0_wb_stall_o => ram_wb_stall_o,
m1_wb_dat_o => sram_rom_wb_dat_o,
m1_wb_dat_i => (others => DontCareValue),
m1_wb_adr_i => sram_rom_wb_adr_i(maxAddrBit downto 2),
m1_wb_sel_i => (others => '1'),
m1_wb_cti_i => CTI_CYCLE_CLASSIC,
m1_wb_we_i => '0',--rom_wb_we_i,
m1_wb_cyc_i => sram_rom_wb_cyc_i,
m1_wb_stb_i => sram_rom_wb_stb_i,
m1_wb_ack_o => sram_rom_wb_ack_o,
m1_wb_stall_o => sram_rom_wb_stall_o,
s0_wb_dat_i => sram_wb_dat_o,
s0_wb_dat_o => sram_wb_dat_i,
s0_wb_adr_o => sram_wb_adr_i(maxAddrBit downto 2),
s0_wb_sel_o => sram_wb_sel_i,
s0_wb_cti_o => open,
s0_wb_we_o => sram_wb_we_i,
s0_wb_cyc_o => sram_wb_cyc_i,
s0_wb_stb_o => sram_wb_stb_i,
s0_wb_ack_i => sram_wb_ack_o,
s0_wb_stall_i => sram_wb_stall_o
);
bootmux: wbbootloadermux
generic map (
address_high => maxAddrBit
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
sel => memory_enable,
-- Master
m_wb_dat_o => rom_wb_dat_o,
m_wb_dat_i => (others => DontCareValue),
m_wb_adr_i => rom_wb_adr_i(maxAddrBit downto 2),
m_wb_sel_i => (others => '1'),
m_wb_cti_i => CTI_CYCLE_CLASSIC,
m_wb_we_i => '0',
m_wb_cyc_i => rom_wb_cyc_i,
m_wb_stb_i => rom_wb_stb_i,
m_wb_ack_o => rom_wb_ack_o,
m_wb_stall_o => rom_wb_stall_o,
-- Slave 0 signals
s0_wb_dat_i => sram_rom_wb_dat_o,
s0_wb_dat_o => open,
s0_wb_adr_o => sram_rom_wb_adr_i,
s0_wb_sel_o => open,
s0_wb_cti_o => open,
s0_wb_we_o => open,
s0_wb_cyc_o => sram_rom_wb_cyc_i,
s0_wb_stb_o => sram_rom_wb_stb_i,
s0_wb_ack_i => sram_rom_wb_ack_o,
s0_wb_stall_i => sram_rom_wb_stall_o,
-- Slave 1 signals
s1_wb_dat_i => prom_rom_wb_dat_o,
s1_wb_dat_o => open,
s1_wb_adr_o => prom_rom_wb_adr_i(11 downto 2),
s1_wb_sel_o => open,
s1_wb_cti_o => open,
s1_wb_we_o => open,
s1_wb_cyc_o => prom_rom_wb_cyc_i,
s1_wb_stb_o => prom_rom_wb_stb_i,
s1_wb_ack_i => prom_rom_wb_ack_o,
s1_wb_stall_i => prom_rom_wb_stall_o
);
npnadapt: wb_master_np_to_slave_p
generic map (
ADDRESS_HIGH => maxAddrBitIncIO,
ADDRESS_LOW => 0
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
-- Master signals
m_wb_dat_o => np_ram_wb_dat_o,
m_wb_dat_i => np_ram_wb_dat_i,
m_wb_adr_i => np_ram_wb_adr_i,
m_wb_sel_i => np_ram_wb_sel_i,
m_wb_cti_i => CTI_CYCLE_CLASSIC,
m_wb_we_i => np_ram_wb_we_i,
m_wb_cyc_i => np_ram_wb_cyc_i,
m_wb_stb_i => np_ram_wb_stb_i,
m_wb_ack_o => np_ram_wb_ack_o,
-- Slave signals
s_wb_dat_i => ram_wb_dat_o,
s_wb_dat_o => ram_wb_dat_i,
s_wb_adr_o => ram_wb_adr_i,
s_wb_sel_o => ram_wb_sel_i,
s_wb_cti_o => open,
s_wb_we_o => ram_wb_we_i,
s_wb_cyc_o => ram_wb_cyc_i,
s_wb_stb_o => ram_wb_stb_i,
s_wb_ack_i => ram_wb_ack_o,
s_wb_stall_i => ram_wb_stall_o
);
-- PROM
prom: wb_bootloader
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => prom_rom_wb_dat_o,
wb_adr_i => prom_rom_wb_adr_i(11 downto 2),
wb_cyc_i => prom_rom_wb_cyc_i,
wb_stb_i => prom_rom_wb_stb_i,
wb_ack_o => prom_rom_wb_ack_o,
wb_stall_o => prom_rom_wb_stall_o,
wb2_dat_o => slot_read(15),
wb2_adr_i => slot_address(15)(11 downto 2),
wb2_cyc_i => slot_cyc(15),
wb2_stb_i => slot_stb(15),
wb2_ack_o => slot_ack(15),
wb2_stall_o => open
);
--
-- IO SLOT 0
--
slot0: zpuino_spi
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(0),
wb_dat_i => slot_write(0),
wb_adr_i => slot_address(0),
wb_we_i => slot_we(0),
wb_cyc_i => slot_cyc(0),
wb_stb_i => slot_stb(0),
wb_ack_o => slot_ack(0),
wb_inta_o => slot_interrupt(0),
mosi => spi_pf_mosi,
miso => spi_pf_miso,
sck => spi_pf_sck,
enabled => open
);
--
-- IO SLOT 1
--
uart_inst: zpuino_uart
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(1),
wb_dat_i => slot_write(1),
wb_adr_i => slot_address(1),
wb_we_i => slot_we(1),
wb_cyc_i => slot_cyc(1),
wb_stb_i => slot_stb(1),
wb_ack_o => slot_ack(1),
wb_inta_o => slot_interrupt(1),
enabled => open,
tx => tx,
rx => rx
);
--
-- IO SLOT 2
--
gpio_inst: zpuino_gpio
generic map (
gpio_count => 49
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(2),
wb_dat_i => slot_write(2),
wb_adr_i => slot_address(2),
wb_we_i => slot_we(2),
wb_cyc_i => slot_cyc(2),
wb_stb_i => slot_stb(2),
wb_ack_o => slot_ack(2),
wb_inta_o => slot_interrupt(2),
spp_data => gpio_bus_in_record.gpio_spp_data,
spp_read => gpio_bus_out_record.gpio_spp_read,
gpio_i => gpio_bus_in_record.gpio_i,
gpio_t => gpio_bus_out_record.gpio_t,
gpio_o => gpio_o_reg,
spp_cap_in => spp_cap_in,
spp_cap_out => spp_cap_out
);
--
-- IO SLOT 3
--
timers_inst: zpuino_timers
generic map (
A_TSCENABLED => true,
A_PWMCOUNT => 1,
A_WIDTH => 16,
A_PRESCALER_ENABLED => true,
A_BUFFERS => true,
B_TSCENABLED => false,
B_PWMCOUNT => 1,
B_WIDTH => 8,--24,
B_PRESCALER_ENABLED => false,
B_BUFFERS => false
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(3),
wb_dat_i => slot_write(3),
wb_adr_i => slot_address(3),
wb_we_i => slot_we(3),
wb_cyc_i => slot_cyc(3),
wb_stb_i => slot_stb(3),
wb_ack_o => slot_ack(3),
wb_inta_o => slot_interrupt(3), -- We use two interrupt lines
wb_intb_o => slot_interrupt(4), -- so we borrow intr line from slot 4
pwm_a_out => timers_pwm(0 downto 0),
pwm_b_out => timers_pwm(1 downto 1)
);
--
-- IO SLOT 4 - DO NOT USE (it's already mapped to Interrupt Controller)
--
--
-- IO SLOT 5
--
-- sigmadelta_inst: zpuino_sigmadelta
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(5),
-- wb_dat_i => slot_write(5),
-- wb_adr_i => slot_address(5),
-- wb_we_i => slot_we(5),
-- wb_cyc_i => slot_cyc(5),
-- wb_stb_i => slot_stb(5),
-- wb_ack_o => slot_ack(5),
-- wb_inta_o => slot_interrupt(5),
-- spp_data => sigmadelta_spp_data,
-- spp_en => open,
-- sync_in => '1'
-- );
--
-- IO SLOT 6
--
-- slot1: zpuino_spi
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(6),
-- wb_dat_i => slot_write(6),
-- wb_adr_i => slot_address(6),
-- wb_we_i => slot_we(6),
-- wb_cyc_i => slot_cyc(6),
-- wb_stb_i => slot_stb(6),
-- wb_ack_o => slot_ack(6),
-- wb_inta_o => slot_interrupt(6),
--
-- mosi => spi2_mosi,
-- miso => spi2_miso,
-- sck => spi2_sck,
-- enabled => open
-- );
--
-- IO SLOT 7
--
crc16_inst: zpuino_crc16
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(7),
wb_dat_i => slot_write(7),
wb_adr_i => slot_address(7),
wb_we_i => slot_we(7),
wb_cyc_i => slot_cyc(7),
wb_stb_i => slot_stb(7),
wb_ack_o => slot_ack(7),
wb_inta_o => slot_interrupt(7)
);
sram_inst: sdram_ctrl
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => sram_wb_dat_o,
wb_dat_i => sram_wb_dat_i,
wb_adr_i => sram_wb_adr_i(maxIObit downto minIObit),
wb_we_i => sram_wb_we_i,
wb_cyc_i => sram_wb_cyc_i,
wb_stb_i => sram_wb_stb_i,
wb_sel_i => sram_wb_sel_i,
--wb_cti_i => CTI_CYCLE_CLASSIC,
wb_ack_o => sram_wb_ack_o,
wb_stall_o => sram_wb_stall_o,
clk_off_3ns => sysclk_sram_we,
DRAM_ADDR => DRAM_ADDR(11 downto 0),
DRAM_BA => DRAM_BA,
DRAM_CAS_N => DRAM_CAS_N,
DRAM_CKE => DRAM_CKE,
DRAM_CLK => DRAM_CLK,
DRAM_CS_N => DRAM_CS_N,
DRAM_DQ => DRAM_DQ,
DRAM_DQM => DRAM_DQM,
DRAM_RAS_N => DRAM_RAS_N,
DRAM_WE_N => DRAM_WE_N
);
DRAM_ADDR(12) <= '0';
-- Papilio Note: Place your Wishbone components here. #Wishbone
-- Look at the ZPUino User Guide for what Wishbone components are available:
-- http://www.papilio.cc/index.php?n=Papilio.ZPUinoUserGuide#Reference
--
-- IO SLOT 8
--
-- slot8: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(8),
-- wb_dat_i => slot_write(8),
-- wb_adr_i => slot_address(8),
-- wb_we_i => slot_we(8),
-- wb_cyc_i => slot_cyc(8),
-- wb_stb_i => slot_stb(8),
-- wb_ack_o => slot_ack(8),
-- wb_inta_o => slot_interrupt(8)
-- );
--
-- IO SLOT 9
--
-- slot9: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(9),
-- wb_dat_i => slot_write(9),
-- wb_adr_i => slot_address(9),
-- wb_we_i => slot_we(9),
-- wb_cyc_i => slot_cyc(9),
-- wb_stb_i => slot_stb(9),
-- wb_ack_o => slot_ack(9),
-- wb_inta_o => slot_interrupt(9)
-- );
--
-- IO SLOT 10
--
-- slot10: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(10),
-- wb_dat_i => slot_write(10),
-- wb_adr_i => slot_address(10),
-- wb_we_i => slot_we(10),
-- wb_cyc_i => slot_cyc(10),
-- wb_stb_i => slot_stb(10),
-- wb_ack_o => slot_ack(10),
-- wb_inta_o => slot_interrupt(10)
-- );
--
-- IO SLOT 11
--
-- slot11: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(11),
-- wb_dat_i => slot_write(11),
-- wb_adr_i => slot_address(11),
-- wb_we_i => slot_we(11),
-- wb_cyc_i => slot_cyc(11),
-- wb_stb_i => slot_stb(11),
-- wb_ack_o => slot_ack(11),
-- wb_inta_o => slot_interrupt(11)
-- );
--
-- IO SLOT 12
--
-- slot12: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(12),
-- wb_dat_i => slot_write(12),
-- wb_adr_i => slot_address(12),
-- wb_we_i => slot_we(12),
-- wb_cyc_i => slot_cyc(12),
-- wb_stb_i => slot_stb(12),
-- wb_ack_o => slot_ack(12),
-- wb_inta_o => slot_interrupt(12)
-- );
--
-- IO SLOT 13
--
-- slot13: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(13),
-- wb_dat_i => slot_write(13),
-- wb_adr_i => slot_address(13),
-- wb_we_i => slot_we(13),
-- wb_cyc_i => slot_cyc(13),
-- wb_stb_i => slot_stb(13),
-- wb_ack_o => slot_ack(13),
-- wb_inta_o => slot_interrupt(13)
-- );
--
-- IO SLOT 14
--
-- slot14: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(14),
-- wb_dat_i => slot_write(14),
-- wb_adr_i => slot_address(14),
-- wb_we_i => slot_we(14),
-- wb_cyc_i => slot_cyc(14),
-- wb_stb_i => slot_stb(14),
-- wb_ack_o => slot_ack(14),
-- wb_inta_o => slot_interrupt(14)
-- );
--
-- IO SLOT 15 - do not use
--
-- process(gpio_spp_read, spi_pf_mosi, spi_pf_sck,
-- sigmadelta_spp_data,timers_pwm,
-- spi2_mosi,spi2_sck)
-- begin
-- gpio_spp_data <= (others => DontCareValue);
-- -- PPS Outputs
-- gpio_spp_data(0) <= sigmadelta_spp_data(0); -- PPS0 : SIGMADELTA DATA
-- gpio_spp_data(1) <= timers_pwm(0); -- PPS1 : TIMER0
-- gpio_spp_data(2) <= timers_pwm(1); -- PPS2 : TIMER1
-- gpio_spp_data(3) <= spi2_mosi; -- PPS3 : USPI MOSI
-- gpio_spp_data(4) <= spi2_sck; -- PPS4 : USPI SCK
-- gpio_spp_data(5) <= sigmadelta_spp_data(1); -- PPS5 : SIGMADELTA1 DATA
-- -- PPS inputs
-- spi2_miso <= gpio_spp_read(0); -- PPS0 : USPI MISO
-- end process;
end behave;
|
mit
|
chcbaram/FPGA
|
zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Template_Wishbone_Example/Libraries/ZPUino_1/zpuino_icache.vhd
|
13
|
10424
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
use board.wishbonepkg.all;
--library UNISIM;
--use UNISIM.vcomponents.all;
entity zpuino_icache is
generic (
ADDRESS_HIGH: integer := 26
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
valid: out std_logic;
data: out std_logic_vector(wordSize-1 downto 0);
address: in std_logic_vector(maxAddrBit downto 0);
strobe: in std_logic;
enable: in std_logic;
stall: out std_logic;
flush: in std_logic;
-- Master wishbone interface
m_wb_ack_i: in std_logic;
m_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
m_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
m_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
m_wb_cyc_o: out std_logic;
m_wb_stb_o: out std_logic;
m_wb_stall_i: in std_logic;
m_wb_we_o: out std_logic
);
end zpuino_icache;
architecture behave of zpuino_icache is
constant ADDRESS_LOW: integer := 0;
constant CACHE_MAX_BITS: integer := 13; -- 8 Kb
constant CACHE_LINE_SIZE_BITS: integer := 6; -- 64 bytes
constant CACHE_LINE_ID_BITS: integer := CACHE_MAX_BITS-CACHE_LINE_SIZE_BITS;
-- memory max width: 19 bits (18 downto 0)
-- cache line size: 64 bytes
-- cache lines: 128
alias line: std_logic_vector(CACHE_LINE_ID_BITS-1 downto 0)
is address(CACHE_MAX_BITS-1 downto CACHE_LINE_SIZE_BITS);
alias line_offset: std_logic_vector(CACHE_LINE_SIZE_BITS-1 downto 2)
is address(CACHE_LINE_SIZE_BITS-1 downto 2);
alias tag: std_logic_vector(ADDRESS_HIGH-CACHE_MAX_BITS-1 downto 0)
is address(ADDRESS_HIGH-1 downto CACHE_MAX_BITS);
signal ctag: std_logic_vector(ADDRESS_HIGH-CACHE_MAX_BITS downto 0);
type validmemtype is ARRAY(0 to (2**line'LENGTH)-1) of std_logic;
shared variable valid_mem: validmemtype;
signal tag_mem_wen: std_logic;
signal miss: std_logic;
signal ack: std_logic;
signal offcnt: unsigned(line_offset'HIGH+1 downto 2);
signal offcnt_write: unsigned(line_offset'HIGH downto 2);
constant offcnt_full: unsigned(line_offset'HIGH downto 2) := (others => '1');
signal tag_match: std_logic;
signal save_addr: std_logic_vector(address'RANGE);
signal cyc, stb: std_logic;
signal cache_addr_read,cache_addr_write:
std_logic_vector(CACHE_MAX_BITS-1 downto 2);
alias tag_save: std_logic_vector(ADDRESS_HIGH-CACHE_MAX_BITS-1 downto 0)
is save_addr(ADDRESS_HIGH-1 downto CACHE_MAX_BITS);
alias line_save: std_logic_vector(CACHE_LINE_ID_BITS-1 downto 0)
is save_addr(CACHE_MAX_BITS-1 downto CACHE_LINE_SIZE_BITS);
signal access_i: std_logic;
signal access_q: std_logic;
signal stall_i, valid_i: std_logic;
signal busy: std_logic;
signal hit: std_logic;
signal tag_mem_enable: std_logic;
type state_type is (
flushing,
running,
filling,
waitwrite,
ending
);
signal state: state_type;
signal fill_success: std_logic;
signal tag_mem_data: std_logic_vector(ADDRESS_HIGH-CACHE_MAX_BITS downto 0);
signal tag_mem_addr: std_logic_vector(CACHE_LINE_ID_BITS-1 downto 0);
signal tag_mem_ena: std_logic;
signal flushcnt: unsigned(line'RANGE);
--constant line_length: integer := CACHE_LINE_ID_BITS;
--constant ctag_length: integer := ADDRESS_HIGH-CACHE_MAX_BITS;
constant dignore: std_logic_vector(ctag'RANGE) := (others => DontCareValue);
constant dignore32: std_logic_vector(31 downto 0) := (others => DontCareValue);
begin
tagmem: generic_dp_ram
generic map (
address_bits => CACHE_LINE_ID_BITS,
data_bits => ADDRESS_HIGH-CACHE_MAX_BITS+1
)
port map (
clka => wb_clk_i,
ena => tag_mem_enable,
wea => '0',
addra => address(CACHE_MAX_BITS-1 downto CACHE_LINE_SIZE_BITS),--line,
dia => dignore,--(others => DontCareValue),
doa => ctag,
clkb => wb_clk_i,
enb => '1',
web => tag_mem_wen,
addrb => tag_mem_addr,
dib => tag_mem_data,
dob => open
);
valid_i <= ctag(ctag'HIGH);
process(state, line_save, tag_save, flushcnt)
begin
if state=flushing then
tag_mem_data <= '0' & tag_save;
tag_mem_addr <= std_logic_vector(flushcnt);
else
tag_mem_data <= '1' & tag_save;
tag_mem_addr <= line_save;
end if;
end process;
tag_match <= '1' when ctag(tag'HIGH downto tag'LOW)=tag else '0';
stall <= stall_i;
valid <= ack;
tag_mem_enable <= access_i and enable;
m_wb_dat_o <= (others => DontCareValue);
-- Valid mem
-- process(wb_clk_i)
-- variable index: integer;
-- begin
-- if rising_edge(wb_clk_i) then
-- if wb_rst_i='1' or flush='1' then
-- for i in 0 to (valid_mem'LENGTH)-1 loop
-- valid_mem(i) := '0';
-- end loop;
-- else
-- index := conv_integer(line_save);
-- if tag_mem_wen='1' then
-- valid_mem(index) := '1';--fill_success;
-- end if;
-- end if;
-- if enable='1' and strobe='1' then
-- valid_i <= valid_mem(conv_integer(line));
--else
-- valid_i <= valid_mem(conv_integer(line_save));
-- end if;
-- end if;
-- end process;
-- Address save
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
--if wb_rst_i='1' then
--fill_end_q<='0';
--fill_end_q_q<='0';
--else
if stall_i='0' and enable='1' and strobe='1' then
--if busy='0' and enable='1' and strobe='1' then
save_addr <= address;
end if;
--fill_end_q <= fill_end;
--fill_end_q_q <= fill_end_q;
--end if;
end if;
end process;
cachemem: generic_dp_ram
generic map (
address_bits => cache_addr_read'LENGTH,
data_bits => 32
)
port map (
clka => wb_clk_i,
ena => tag_mem_ena, -- enable and strobe ?
wea => '0',
addra => cache_addr_read,
dia => dignore32,
doa => data,
clkb => wb_clk_i,
enb => '1',
web => m_wb_ack_i,
addrb => cache_addr_write,
dib => m_wb_dat_i,
dob => open
);
tag_mem_ena <= enable and strobe;
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
access_q<='0';
else
if busy='0' and enable='1' then
access_q <= access_i;
end if;
end if;
end if;
end process;
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
state <= flushing;
busy <= '0';
fill_success <='0';
offcnt <= (others => '0');
flushcnt <= (others => '1');
tag_mem_wen <= '1';
else
busy <= '0';
cyc <= '0';
stb <= '0';
tag_mem_wen <= '0';
fill_success <='0';
case state is
when flushing =>
busy <= '1';
flushcnt <= flushcnt - 1;
tag_mem_wen<='1';
if flushcnt=0 then
tag_mem_wen<='0';
state <= running;
end if;
when running =>
if flush='1' then
state <= flushing;
flushcnt <= (others => '1');
tag_mem_wen <= '1';
else
if access_q='1' then
if miss='1' and enable='1' then
state <= filling;
offcnt <= (others => '0');
offcnt_write <= (others => '0');
cyc <= '1';
stb <= '1';
--fill_success<='1';
busy <= '1';
end if;
end if;
end if;
when filling =>
busy<='1';
cyc <= '1';
stb <= '1';
--if offcnt(offcnt'HIGH)='0' then
-- stb <= '1';
--else
-- stb <= '0';
--end if;
if m_wb_ack_i='1' then
offcnt_write <= offcnt_write + 1;
-- This will go to 0, but we check before and switch state
if offcnt_write=offcnt_full then
tag_mem_wen<='1';
state <= waitwrite;
end if;
end if;
--if offcnt_write = offcnt_full then
-- state <= waitwrite;
-- offcnt <= (others => '0');
--else
if m_wb_stall_i='0' then
if offcnt(offcnt'HIGH)='0' then
offcnt <= offcnt + 1;
end if;
end if;
when waitwrite =>
busy<='1';
state <= ending;
when ending =>
busy<='0';
if enable='1' then
fill_success<='1';
end if;
state <= running;
end case;
end if;
end if;
end process;
process(fill_success, busy, hit)
begin
if busy='1' then
ack <= '0';
elsif fill_success='1' then
ack <= '1';
else
ack <= hit;
end if;
end process;
--if busy='0' then
-- ack <= hit;
-- else
-- ack <= fill_success;
-- if state=ending then
-- ack <= '1';
-- else
-- ack <= '0';
-- end if;
-- end if;
-- end process;
access_i <= strobe;
hit <= '1' when tag_match='1' and valid_i='1' and access_q='1' else '0';
miss <= not hit;
cache_addr_read <= line & line_offset when stall_i='0' else save_addr(CACHE_MAX_BITS-1 downto 2);
cache_addr_write <= line_save & std_logic_vector(offcnt_write(offcnt_write'HIGH downto 2));
process(busy,miss,access_q)
begin
if busy='1' then
stall_i<='1';
elsif fill_success='1' then
stall_i <= '0';
else
if access_q='1' then
stall_i<=miss;
else
stall_i<='0';
end if;
end if;
end process;
--stall_i <= miss when access_q='1' else busy;
m_wb_cyc_o <= cyc;
m_wb_stb_o <= stb when offcnt(offcnt'HIGH)='0' else '0';
m_wb_we_o<='0';
m_wb_adr_o(maxAddrBit downto CACHE_LINE_SIZE_BITS) <= save_addr(maxAddrBit downto CACHE_LINE_SIZE_BITS);
m_wb_adr_o(CACHE_LINE_SIZE_BITS-1 downto 2) <= std_logic_vector(offcnt(CACHE_LINE_SIZE_BITS-1 downto 2));
end behave;
|
mit
|
chcbaram/FPGA
|
zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/WING_Analog/Libraries/ZPUino_1/ZPUino_Papilio_One_V1.vhd
|
13
|
42659
|
--
-- ZPUINO implementation on Gadget Factory 'Papilio One' Board
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library zpuino;
use zpuino.pad.all;
use zpuino.papilio_pkg.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
library unisim;
use unisim.vcomponents.all;
entity ZPUino_Papilio_One_V1 is
port (
--32Mhz input clock is converted to a 96Mhz clock
CLK: in std_logic;
--RST: in std_logic; -- No reset on papilio
--Clock outputs to be used in schematic
clk_96Mhz: out std_logic; --This is the clock that the system runs on.
clk_1Mhz: out std_logic; --This is a 1Mhz clock for symbols like the C64 SID chip.
clk_osc_32Mhz: out std_logic; --This is the 32Mhz clock from external oscillator.
-- Connection to the main SPI flash
SPI_FLASH_SCK: out std_logic;
SPI_FLASH_MISO: in std_logic;
SPI_FLASH_MOSI: out std_logic;
SPI_FLASH_CS: inout std_logic;
gpio_bus_in : in std_logic_vector(97 downto 0);
gpio_bus_out : out std_logic_vector(147 downto 0);
-- UART (FTDI) connection
TXD: out std_logic;
RXD: in std_logic;
--There are more bits in the address for this wishbone connection
wishbone_slot_video_in : in std_logic_vector(63 downto 0);
wishbone_slot_video_out : out std_logic_vector(33 downto 0);
vgaclkout: out std_logic;
-- Unfortunately the Xilinx Schematic Editor does not support records, so we have to put all wishbone signals into one array.
-- This is a little cumbersome but is better then dealing with all the signals in the schematic editor.
-- This is what the original record base approach looked like:
--
-- type wishbone_bus_in_type is record
-- wb_clk_i: std_logic; -- Wishbone clock
-- wb_rst_i: std_logic; -- Wishbone reset (synchronous)
-- wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
-- wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
-- wb_we_i: std_logic; -- Wishbone write enable signal
-- wb_cyc_i: std_logic; -- Wishbone cycle signal
-- wb_stb_i: std_logic; -- Wishbone strobe signal
-- end record;
--
-- type wishbone_bus_out_type is record
-- wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
-- wb_ack_o: std_logic; -- Wishbone acknowledge out signal
-- wb_inta_o: std_logic;
-- end record;
--
-- Turning them into an array looks like this:
--
-- wishbone_in : in std_logic_vector(61 downto 0);
--
-- wishbone_in_record.wb_clk_i <= wishbone_in(61);
-- wishbone_in_record.wb_rst_i <= wishbone_in(60);
-- wishbone_in_record.wb_dat_i <= wishbone_in(59 downto 28);
-- wishbone_in_record.wb_adr_i <= wishbone_in(27 downto 3);
-- wishbone_in_record.wb_we_i <= wishbone_in(2);
-- wishbone_in_record.wb_cyc_i <= wishbone_in(1);
-- wishbone_in_record.wb_stb_i <= wishbone_in(0);
--
-- wishbone_out : out std_logic_vector(33 downto 0);
--
-- wishbone_out(33 downto 2) <= wishbone_out_record.wb_dat_o;
-- wishbone_out(1) <= wishbone_out_record.wb_ack_o;
-- wishbone_out(0) <= wishbone_out_record.wb_inta_o;
--Input and output reversed for the master
wishbone_slot_5_in : out std_logic_vector(61 downto 0);
wishbone_slot_5_out : in std_logic_vector(33 downto 0);
wishbone_slot_6_in : out std_logic_vector(61 downto 0);
wishbone_slot_6_out : in std_logic_vector(33 downto 0);
wishbone_slot_8_in : out std_logic_vector(61 downto 0);
wishbone_slot_8_out : in std_logic_vector(33 downto 0);
wishbone_slot_9_in : out std_logic_vector(61 downto 0);
wishbone_slot_9_out : in std_logic_vector(33 downto 0);
wishbone_slot_10_in : out std_logic_vector(61 downto 0);
wishbone_slot_10_out : in std_logic_vector(33 downto 0);
wishbone_slot_11_in : out std_logic_vector(61 downto 0);
wishbone_slot_11_out : in std_logic_vector(33 downto 0);
wishbone_slot_12_in : out std_logic_vector(61 downto 0);
wishbone_slot_12_out : in std_logic_vector(33 downto 0);
wishbone_slot_13_in : out std_logic_vector(61 downto 0);
wishbone_slot_13_out : in std_logic_vector(33 downto 0);
wishbone_slot_14_in : out std_logic_vector(61 downto 0);
wishbone_slot_14_out : in std_logic_vector(33 downto 0);
wishbone_slot_15_in : out std_logic_vector(61 downto 0);
wishbone_slot_15_out : in std_logic_vector(33 downto 0)
);
-- attribute LOC: string;
-- attribute LOC of CLK: signal is "P89";
-- attribute LOC of RXD: signal is "P88";
-- attribute LOC of TXD: signal is "P90";
-- attribute LOC of SPI_FLASH_CS: signal is "P24";
-- attribute LOC of SPI_FLASH_SCK: signal is "P50";
-- attribute LOC of SPI_FLASH_MISO: signal is "P44";
-- attribute LOC of SPI_FLASH_MOSI: signal is "P27";
--
-- attribute IOSTANDARD: string;
-- attribute IOSTANDARD of CLK: signal is "LVCMOS33";
-- attribute IOSTANDARD of RXD: signal is "LVCMOS33";
-- attribute IOSTANDARD of TXD: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_CS: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_SCK: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_MISO: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_MOSI: signal is "LVCMOS33";
--
-- attribute PERIOD: string;
-- attribute PERIOD of CLK: signal is "31.00ns";
end entity ZPUino_Papilio_One_V1;
architecture behave of ZPUino_Papilio_One_V1 is
component clkgen is
port (
clkin: in std_logic;
rstin: in std_logic;
clkout: out std_logic;
clkout_1mhz: out std_logic;
clk_osc_32Mhz: out std_logic;
vgaclkout: out std_logic;
rstout: out std_logic
);
end component clkgen;
component zpuino_serialreset is
generic (
SYSTEM_CLOCK_MHZ: integer := 96
);
port (
clk: in std_logic;
rx: in std_logic;
rstin: in std_logic;
rstout: out std_logic
);
end component zpuino_serialreset;
signal sysrst: std_logic;
signal sysclk: std_logic;
signal sysclk_1mhz: std_logic;
signal dbg_reset: std_logic;
signal clkgen_rst: std_logic;
signal gpio_o_reg: std_logic_vector(zpuino_gpio_count-1 downto 0);
signal rx: std_logic;
signal tx: std_logic;
constant spp_cap_in: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
"0" &
"0000000000000000" &
"0000000000000000" &
"0000000000000000";
constant spp_cap_out: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
"0" &
"0000000000000000" &
"0000000000000000" &
"0000000000000000";
-- constant spp_cap_in: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
-- "0" &
-- "1111111111111111" &
-- "1111111111111111" &
-- "1111111111111111";
-- constant spp_cap_out: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
-- "0" &
-- "1111111111111111" &
-- "1111111111111111" &
-- "1111111111111111";
-- I/O Signals
signal slot_cyc: slot_std_logic_type;
signal slot_we: slot_std_logic_type;
signal slot_stb: slot_std_logic_type;
signal slot_read: slot_cpuword_type;
signal slot_write: slot_cpuword_type;
signal slot_address: slot_address_type;
signal slot_ack: slot_std_logic_type;
signal slot_interrupt: slot_std_logic_type;
signal spi_enabled: std_logic;
signal uart_enabled: std_logic;
signal timers_interrupt: std_logic_vector(1 downto 0);
signal timers_pwm: std_logic_vector(1 downto 0);
signal ivecs, sigmadelta_raw: std_logic_vector(17 downto 0);
signal sigmadelta_spp_en: std_logic_vector(1 downto 0);
signal sigmadelta_spp_data: std_logic_vector(1 downto 0);
-- For busy-implementation
signal addr_save_q: std_logic_vector(maxAddrBitIncIO downto 0);
signal write_save_q: std_logic_vector(wordSize-1 downto 0);
signal spi_pf_miso: std_logic;
signal spi_pf_mosi: std_logic;
signal spi_pf_sck: std_logic;
signal adc_mosi: std_logic;
signal adc_miso: std_logic;
signal adc_sck: std_logic;
signal adc_seln: std_logic;
signal adc_enabled: std_logic;
signal wb_clk_i: std_logic;
signal wb_rst_i: std_logic;
signal uart2_tx, uart2_rx: std_logic;
signal jtag_data_chain_out: std_logic_vector(98 downto 0);
signal jtag_ctrl_chain_in: std_logic_vector(11 downto 0);
signal wishbone_slot_video_in_record : wishbone_bus_in_type;
signal wishbone_slot_video_out_record : wishbone_bus_out_type;
signal wishbone_slot_5_in_record : wishbone_bus_in_type;
signal wishbone_slot_5_out_record : wishbone_bus_out_type;
signal wishbone_slot_6_in_record : wishbone_bus_in_type;
signal wishbone_slot_6_out_record : wishbone_bus_out_type;
signal wishbone_slot_8_in_record : wishbone_bus_in_type;
signal wishbone_slot_8_out_record : wishbone_bus_out_type;
signal wishbone_slot_9_in_record : wishbone_bus_in_type;
signal wishbone_slot_9_out_record : wishbone_bus_out_type;
signal wishbone_slot_10_in_record : wishbone_bus_in_type;
signal wishbone_slot_10_out_record : wishbone_bus_out_type;
signal wishbone_slot_11_in_record : wishbone_bus_in_type;
signal wishbone_slot_11_out_record : wishbone_bus_out_type;
signal wishbone_slot_12_in_record : wishbone_bus_in_type;
signal wishbone_slot_12_out_record : wishbone_bus_out_type;
signal wishbone_slot_13_in_record : wishbone_bus_in_type;
signal wishbone_slot_13_out_record : wishbone_bus_out_type;
signal wishbone_slot_14_in_record : wishbone_bus_in_type;
signal wishbone_slot_14_out_record : wishbone_bus_out_type;
signal wishbone_slot_15_in_record : wishbone_bus_in_type;
signal wishbone_slot_15_out_record : wishbone_bus_out_type;
signal gpio_bus_in_record : gpio_bus_in_type;
signal gpio_bus_out_record : gpio_bus_out_type;
component zpuino_debug_spartan3e is
port (
TCK: out std_logic;
TDI: out std_logic;
CAPTUREIR: out std_logic;
UPDATEIR: out std_logic;
SHIFTIR: out std_logic;
CAPTUREDR: out std_logic;
UPDATEDR: out std_logic;
SHIFTDR: out std_logic;
TLR: out std_logic;
TDO_IR: in std_logic;
TDO_DR: in std_logic
);
end component;
begin
-- Unpack the wishbone array into a record so the modules code is not confusing.
-- These are backwards for the master.
-- wishbone_slot_video_in_record.wb_clk_i <= wishbone_slot_video_in(61);
-- wishbone_slot_video_in_record.wb_rst_i <= wishbone_slot_video_in(60);
-- wishbone_slot_video_in_record.wb_dat_i <= wishbone_slot_video_in(59 downto 28);
-- wishbone_slot_video_in_record.wb_adr_i <= wishbone_slot_video_in(27 downto 3);
-- wishbone_slot_video_in_record.wb_we_i <= wishbone_slot_video_in(2);
-- wishbone_slot_video_in_record.wb_cyc_i <= wishbone_slot_video_in(1);
-- wishbone_slot_video_in_record.wb_stb_i <= wishbone_slot_video_in(0);
-- wishbone_slot_video_out(33 downto 2) <= wishbone_slot_video_out_record.wb_dat_o;
-- wishbone_slot_video_out(1) <= wishbone_slot_video_out_record.wb_ack_o;
-- wishbone_slot_video_out(0) <= wishbone_slot_video_out_record.wb_inta_o;
wishbone_slot_5_in(61) <= wishbone_slot_5_in_record.wb_clk_i;
wishbone_slot_5_in(60) <= wishbone_slot_5_in_record.wb_rst_i;
wishbone_slot_5_in(59 downto 28) <= wishbone_slot_5_in_record.wb_dat_i;
wishbone_slot_5_in(27 downto 3) <= wishbone_slot_5_in_record.wb_adr_i;
wishbone_slot_5_in(2) <= wishbone_slot_5_in_record.wb_we_i;
wishbone_slot_5_in(1) <= wishbone_slot_5_in_record.wb_cyc_i;
wishbone_slot_5_in(0) <= wishbone_slot_5_in_record.wb_stb_i;
wishbone_slot_5_out_record.wb_dat_o <= wishbone_slot_5_out(33 downto 2);
wishbone_slot_5_out_record.wb_ack_o <= wishbone_slot_5_out(1);
wishbone_slot_5_out_record.wb_inta_o <= wishbone_slot_5_out(0);
wishbone_slot_6_in(61) <= wishbone_slot_6_in_record.wb_clk_i;
wishbone_slot_6_in(60) <= wishbone_slot_6_in_record.wb_rst_i;
wishbone_slot_6_in(59 downto 28) <= wishbone_slot_6_in_record.wb_dat_i;
wishbone_slot_6_in(27 downto 3) <= wishbone_slot_6_in_record.wb_adr_i;
wishbone_slot_6_in(2) <= wishbone_slot_6_in_record.wb_we_i;
wishbone_slot_6_in(1) <= wishbone_slot_6_in_record.wb_cyc_i;
wishbone_slot_6_in(0) <= wishbone_slot_6_in_record.wb_stb_i;
wishbone_slot_6_out_record.wb_dat_o <= wishbone_slot_6_out(33 downto 2);
wishbone_slot_6_out_record.wb_ack_o <= wishbone_slot_6_out(1);
wishbone_slot_6_out_record.wb_inta_o <= wishbone_slot_6_out(0);
wishbone_slot_8_in(61) <= wishbone_slot_8_in_record.wb_clk_i;
wishbone_slot_8_in(60) <= wishbone_slot_8_in_record.wb_rst_i;
wishbone_slot_8_in(59 downto 28) <= wishbone_slot_8_in_record.wb_dat_i;
wishbone_slot_8_in(27 downto 3) <= wishbone_slot_8_in_record.wb_adr_i;
wishbone_slot_8_in(2) <= wishbone_slot_8_in_record.wb_we_i;
wishbone_slot_8_in(1) <= wishbone_slot_8_in_record.wb_cyc_i;
wishbone_slot_8_in(0) <= wishbone_slot_8_in_record.wb_stb_i;
wishbone_slot_8_out_record.wb_dat_o <= wishbone_slot_8_out(33 downto 2);
wishbone_slot_8_out_record.wb_ack_o <= wishbone_slot_8_out(1);
wishbone_slot_8_out_record.wb_inta_o <= wishbone_slot_8_out(0);
wishbone_slot_9_in(61) <= wishbone_slot_9_in_record.wb_clk_i;
wishbone_slot_9_in(60) <= wishbone_slot_9_in_record.wb_rst_i;
wishbone_slot_9_in(59 downto 28) <= wishbone_slot_9_in_record.wb_dat_i;
wishbone_slot_9_in(27 downto 3) <= wishbone_slot_9_in_record.wb_adr_i;
wishbone_slot_9_in(2) <= wishbone_slot_9_in_record.wb_we_i;
wishbone_slot_9_in(1) <= wishbone_slot_9_in_record.wb_cyc_i;
wishbone_slot_9_in(0) <= wishbone_slot_9_in_record.wb_stb_i;
wishbone_slot_9_out_record.wb_dat_o <= wishbone_slot_9_out(33 downto 2);
wishbone_slot_9_out_record.wb_ack_o <= wishbone_slot_9_out(1);
wishbone_slot_9_out_record.wb_inta_o <= wishbone_slot_9_out(0);
wishbone_slot_10_in(61) <= wishbone_slot_10_in_record.wb_clk_i;
wishbone_slot_10_in(60) <= wishbone_slot_10_in_record.wb_rst_i;
wishbone_slot_10_in(59 downto 28) <= wishbone_slot_10_in_record.wb_dat_i;
wishbone_slot_10_in(27 downto 3) <= wishbone_slot_10_in_record.wb_adr_i;
wishbone_slot_10_in(2) <= wishbone_slot_10_in_record.wb_we_i;
wishbone_slot_10_in(1) <= wishbone_slot_10_in_record.wb_cyc_i;
wishbone_slot_10_in(0) <= wishbone_slot_10_in_record.wb_stb_i;
wishbone_slot_10_out_record.wb_dat_o <= wishbone_slot_10_out(33 downto 2);
wishbone_slot_10_out_record.wb_ack_o <= wishbone_slot_10_out(1);
wishbone_slot_10_out_record.wb_inta_o <= wishbone_slot_10_out(0);
wishbone_slot_11_in(61) <= wishbone_slot_11_in_record.wb_clk_i;
wishbone_slot_11_in(60) <= wishbone_slot_11_in_record.wb_rst_i;
wishbone_slot_11_in(59 downto 28) <= wishbone_slot_11_in_record.wb_dat_i;
wishbone_slot_11_in(27 downto 3) <= wishbone_slot_11_in_record.wb_adr_i;
wishbone_slot_11_in(2) <= wishbone_slot_11_in_record.wb_we_i;
wishbone_slot_11_in(1) <= wishbone_slot_11_in_record.wb_cyc_i;
wishbone_slot_11_in(0) <= wishbone_slot_11_in_record.wb_stb_i;
wishbone_slot_11_out_record.wb_dat_o <= wishbone_slot_11_out(33 downto 2);
wishbone_slot_11_out_record.wb_ack_o <= wishbone_slot_11_out(1);
wishbone_slot_11_out_record.wb_inta_o <= wishbone_slot_11_out(0);
wishbone_slot_12_in(61) <= wishbone_slot_12_in_record.wb_clk_i;
wishbone_slot_12_in(60) <= wishbone_slot_12_in_record.wb_rst_i;
wishbone_slot_12_in(59 downto 28) <= wishbone_slot_12_in_record.wb_dat_i;
wishbone_slot_12_in(27 downto 3) <= wishbone_slot_12_in_record.wb_adr_i;
wishbone_slot_12_in(2) <= wishbone_slot_12_in_record.wb_we_i;
wishbone_slot_12_in(1) <= wishbone_slot_12_in_record.wb_cyc_i;
wishbone_slot_12_in(0) <= wishbone_slot_12_in_record.wb_stb_i;
wishbone_slot_12_out_record.wb_dat_o <= wishbone_slot_12_out(33 downto 2);
wishbone_slot_12_out_record.wb_ack_o <= wishbone_slot_12_out(1);
wishbone_slot_12_out_record.wb_inta_o <= wishbone_slot_12_out(0);
wishbone_slot_13_in(61) <= wishbone_slot_13_in_record.wb_clk_i;
wishbone_slot_13_in(60) <= wishbone_slot_13_in_record.wb_rst_i;
wishbone_slot_13_in(59 downto 28) <= wishbone_slot_13_in_record.wb_dat_i;
wishbone_slot_13_in(27 downto 3) <= wishbone_slot_13_in_record.wb_adr_i;
wishbone_slot_13_in(2) <= wishbone_slot_13_in_record.wb_we_i;
wishbone_slot_13_in(1) <= wishbone_slot_13_in_record.wb_cyc_i;
wishbone_slot_13_in(0) <= wishbone_slot_13_in_record.wb_stb_i;
wishbone_slot_13_out_record.wb_dat_o <= wishbone_slot_13_out(33 downto 2);
wishbone_slot_13_out_record.wb_ack_o <= wishbone_slot_13_out(1);
wishbone_slot_13_out_record.wb_inta_o <= wishbone_slot_13_out(0);
wishbone_slot_14_in(61) <= wishbone_slot_14_in_record.wb_clk_i;
wishbone_slot_14_in(60) <= wishbone_slot_14_in_record.wb_rst_i;
wishbone_slot_14_in(59 downto 28) <= wishbone_slot_14_in_record.wb_dat_i;
wishbone_slot_14_in(27 downto 3) <= wishbone_slot_14_in_record.wb_adr_i;
wishbone_slot_14_in(2) <= wishbone_slot_14_in_record.wb_we_i;
wishbone_slot_14_in(1) <= wishbone_slot_14_in_record.wb_cyc_i;
wishbone_slot_14_in(0) <= wishbone_slot_14_in_record.wb_stb_i;
wishbone_slot_14_out_record.wb_dat_o <= wishbone_slot_14_out(33 downto 2);
wishbone_slot_14_out_record.wb_ack_o <= wishbone_slot_14_out(1);
wishbone_slot_14_out_record.wb_inta_o <= wishbone_slot_14_out(0);
wishbone_slot_15_in(61) <= wishbone_slot_15_in_record.wb_clk_i;
wishbone_slot_15_in(60) <= wishbone_slot_15_in_record.wb_rst_i;
wishbone_slot_15_in(59 downto 28) <= wishbone_slot_15_in_record.wb_dat_i;
wishbone_slot_15_in(27 downto 3) <= wishbone_slot_15_in_record.wb_adr_i;
wishbone_slot_15_in(2) <= wishbone_slot_15_in_record.wb_we_i;
wishbone_slot_15_in(1) <= wishbone_slot_15_in_record.wb_cyc_i;
wishbone_slot_15_in(0) <= wishbone_slot_15_in_record.wb_stb_i;
wishbone_slot_15_out_record.wb_dat_o <= wishbone_slot_15_out(33 downto 2);
wishbone_slot_15_out_record.wb_ack_o <= wishbone_slot_15_out(1);
wishbone_slot_15_out_record.wb_inta_o <= wishbone_slot_15_out(0);
gpio_bus_in_record.gpio_spp_data <= gpio_bus_in(97 downto 49);
gpio_bus_in_record.gpio_i <= gpio_bus_in(48 downto 0);
gpio_bus_out(147) <= gpio_bus_out_record.gpio_clk;
gpio_bus_out(146 downto 98) <= gpio_bus_out_record.gpio_o;
gpio_bus_out(97 downto 49) <= gpio_bus_out_record.gpio_t;
gpio_bus_out(48 downto 0) <= gpio_bus_out_record.gpio_spp_read;
gpio_bus_out_record.gpio_o <= gpio_o_reg;
gpio_bus_out_record.gpio_clk <= sysclk;
wb_clk_i <= sysclk;
wb_rst_i <= sysrst;
--Wishbone 5
wishbone_slot_5_in_record.wb_clk_i <= sysclk;
wishbone_slot_5_in_record.wb_rst_i <= sysrst;
slot_read(5) <= wishbone_slot_5_out_record.wb_dat_o;
wishbone_slot_5_in_record.wb_dat_i <= slot_write(5);
wishbone_slot_5_in_record.wb_adr_i <= slot_address(5);
wishbone_slot_5_in_record.wb_we_i <= slot_we(5);
wishbone_slot_5_in_record.wb_cyc_i <= slot_cyc(5);
wishbone_slot_5_in_record.wb_stb_i <= slot_stb(5);
slot_ack(5) <= wishbone_slot_5_out_record.wb_ack_o;
slot_interrupt(5) <= wishbone_slot_5_out_record.wb_inta_o;
--Wishbone 6
wishbone_slot_6_in_record.wb_clk_i <= sysclk;
wishbone_slot_6_in_record.wb_rst_i <= sysrst;
slot_read(6) <= wishbone_slot_6_out_record.wb_dat_o;
wishbone_slot_6_in_record.wb_dat_i <= slot_write(6);
wishbone_slot_6_in_record.wb_adr_i <= slot_address(6);
wishbone_slot_6_in_record.wb_we_i <= slot_we(6);
wishbone_slot_6_in_record.wb_cyc_i <= slot_cyc(6);
wishbone_slot_6_in_record.wb_stb_i <= slot_stb(6);
slot_ack(6) <= wishbone_slot_6_out_record.wb_ack_o;
slot_interrupt(6) <= wishbone_slot_6_out_record.wb_inta_o;
--Wishbone 8
wishbone_slot_8_in_record.wb_clk_i <= sysclk;
wishbone_slot_8_in_record.wb_rst_i <= sysrst;
slot_read(8) <= wishbone_slot_8_out_record.wb_dat_o;
wishbone_slot_8_in_record.wb_dat_i <= slot_write(8);
wishbone_slot_8_in_record.wb_adr_i <= slot_address(8);
wishbone_slot_8_in_record.wb_we_i <= slot_we(8);
wishbone_slot_8_in_record.wb_cyc_i <= slot_cyc(8);
wishbone_slot_8_in_record.wb_stb_i <= slot_stb(8);
slot_ack(8) <= wishbone_slot_8_out_record.wb_ack_o;
slot_interrupt(8) <= wishbone_slot_8_out_record.wb_inta_o;
--Wishbone 9
wishbone_slot_9_in_record.wb_clk_i <= sysclk;
wishbone_slot_9_in_record.wb_rst_i <= sysrst;
slot_read(9) <= wishbone_slot_9_out_record.wb_dat_o;
wishbone_slot_9_in_record.wb_dat_i <= slot_write(9);
wishbone_slot_9_in_record.wb_adr_i <= slot_address(9);
wishbone_slot_9_in_record.wb_we_i <= slot_we(9);
wishbone_slot_9_in_record.wb_cyc_i <= slot_cyc(9);
wishbone_slot_9_in_record.wb_stb_i <= slot_stb(9);
slot_ack(9) <= wishbone_slot_9_out_record.wb_ack_o;
slot_interrupt(9) <= wishbone_slot_9_out_record.wb_inta_o;
--Wishbone 10
wishbone_slot_10_in_record.wb_clk_i <= sysclk;
wishbone_slot_10_in_record.wb_rst_i <= sysrst;
slot_read(10) <= wishbone_slot_10_out_record.wb_dat_o;
wishbone_slot_10_in_record.wb_dat_i <= slot_write(10);
wishbone_slot_10_in_record.wb_adr_i <= slot_address(10);
wishbone_slot_10_in_record.wb_we_i <= slot_we(10);
wishbone_slot_10_in_record.wb_cyc_i <= slot_cyc(10);
wishbone_slot_10_in_record.wb_stb_i <= slot_stb(10);
slot_ack(10) <= wishbone_slot_10_out_record.wb_ack_o;
slot_interrupt(10) <= wishbone_slot_10_out_record.wb_inta_o;
--Wishbone 11
wishbone_slot_11_in_record.wb_clk_i <= sysclk;
wishbone_slot_11_in_record.wb_rst_i <= sysrst;
slot_read(11) <= wishbone_slot_11_out_record.wb_dat_o;
wishbone_slot_11_in_record.wb_dat_i <= slot_write(11);
wishbone_slot_11_in_record.wb_adr_i <= slot_address(11);
wishbone_slot_11_in_record.wb_we_i <= slot_we(11);
wishbone_slot_11_in_record.wb_cyc_i <= slot_cyc(11);
wishbone_slot_11_in_record.wb_stb_i <= slot_stb(11);
slot_ack(11) <= wishbone_slot_11_out_record.wb_ack_o;
slot_interrupt(11) <= wishbone_slot_11_out_record.wb_inta_o;
--Wishbone 12
wishbone_slot_12_in_record.wb_clk_i <= sysclk;
wishbone_slot_12_in_record.wb_rst_i <= sysrst;
slot_read(12) <= wishbone_slot_12_out_record.wb_dat_o;
wishbone_slot_12_in_record.wb_dat_i <= slot_write(12);
wishbone_slot_12_in_record.wb_adr_i <= slot_address(12);
wishbone_slot_12_in_record.wb_we_i <= slot_we(12);
wishbone_slot_12_in_record.wb_cyc_i <= slot_cyc(12);
wishbone_slot_12_in_record.wb_stb_i <= slot_stb(12);
slot_ack(12) <= wishbone_slot_12_out_record.wb_ack_o;
slot_interrupt(12) <= wishbone_slot_12_out_record.wb_inta_o;
--Wishbone 13
wishbone_slot_13_in_record.wb_clk_i <= sysclk;
wishbone_slot_13_in_record.wb_rst_i <= sysrst;
slot_read(13) <= wishbone_slot_13_out_record.wb_dat_o;
wishbone_slot_13_in_record.wb_dat_i <= slot_write(13);
wishbone_slot_13_in_record.wb_adr_i <= slot_address(13);
wishbone_slot_13_in_record.wb_we_i <= slot_we(13);
wishbone_slot_13_in_record.wb_cyc_i <= slot_cyc(13);
wishbone_slot_13_in_record.wb_stb_i <= slot_stb(13);
slot_ack(13) <= wishbone_slot_13_out_record.wb_ack_o;
slot_interrupt(13) <= wishbone_slot_13_out_record.wb_inta_o;
--Wishbone 14
wishbone_slot_14_in_record.wb_clk_i <= sysclk;
wishbone_slot_14_in_record.wb_rst_i <= sysrst;
slot_read(14) <= wishbone_slot_14_out_record.wb_dat_o;
wishbone_slot_14_in_record.wb_dat_i <= slot_write(14);
wishbone_slot_14_in_record.wb_adr_i <= slot_address(14);
wishbone_slot_14_in_record.wb_we_i <= slot_we(14);
wishbone_slot_14_in_record.wb_cyc_i <= slot_cyc(14);
wishbone_slot_14_in_record.wb_stb_i <= slot_stb(14);
slot_ack(14) <= wishbone_slot_14_out_record.wb_ack_o;
slot_interrupt(14) <= wishbone_slot_14_out_record.wb_inta_o;
--Wishbone 15
wishbone_slot_15_in_record.wb_clk_i <= sysclk;
wishbone_slot_15_in_record.wb_rst_i <= sysrst;
slot_read(15) <= wishbone_slot_15_out_record.wb_dat_o;
wishbone_slot_15_in_record.wb_dat_i <= slot_write(15);
wishbone_slot_15_in_record.wb_adr_i <= slot_address(15);
wishbone_slot_15_in_record.wb_we_i <= slot_we(15);
wishbone_slot_15_in_record.wb_cyc_i <= slot_cyc(15);
wishbone_slot_15_in_record.wb_stb_i <= slot_stb(15);
slot_ack(15) <= wishbone_slot_15_out_record.wb_ack_o;
slot_interrupt(15) <= wishbone_slot_15_out_record.wb_inta_o;
rstgen: zpuino_serialreset
generic map (
SYSTEM_CLOCK_MHZ => 96
)
port map (
clk => sysclk,
rx => rx,
rstin => clkgen_rst,
rstout => sysrst
);
--sysrst <= clkgen_rst;
clkgen_inst: clkgen
port map (
clkin => clk,
rstin => dbg_reset,
clkout => sysclk,
vgaclkout => vgaclkout,
clkout_1mhz => clk_1Mhz,
clk_osc_32Mhz => clk_osc_32Mhz,
rstout => clkgen_rst
);
clk_96Mhz <= sysclk;
zpuino:zpuino_top
port map (
clk => sysclk,
rst => sysrst,
slot_cyc => slot_cyc,
slot_we => slot_we,
slot_stb => slot_stb,
slot_read => slot_read,
slot_write => slot_write,
slot_address => slot_address,
slot_ack => slot_ack,
slot_interrupt=> slot_interrupt,
--Be careful the order for this is different then the other wishbone bus connections.
--The address array is bigger so we moved the single signals to the top of the array.
m_wb_dat_o => wishbone_slot_video_out(33 downto 2),
m_wb_dat_i => wishbone_slot_video_in(59 downto 28),
m_wb_adr_i => wishbone_slot_video_in(27 downto 0),
m_wb_we_i => wishbone_slot_video_in(62),
m_wb_cyc_i => wishbone_slot_video_in(61),
m_wb_stb_i => wishbone_slot_video_in(60),
m_wb_ack_o => wishbone_slot_video_out(1),
dbg_reset => dbg_reset,
jtag_data_chain_out => open,--jtag_data_chain_out,
jtag_ctrl_chain_in => (others=>'0')--jtag_ctrl_chain_in
);
--
--
-- ---------------- I/O connection to devices --------------------
--
--
--
-- IO SLOT 0 For SPI FLash
--
slot0: zpuino_spi
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(0),
wb_dat_i => slot_write(0),
wb_adr_i => slot_address(0),
wb_we_i => slot_we(0),
wb_cyc_i => slot_cyc(0),
wb_stb_i => slot_stb(0),
wb_ack_o => slot_ack(0),
wb_inta_o => slot_interrupt(0),
mosi => spi_pf_mosi,
miso => spi_pf_miso,
sck => spi_pf_sck,
enabled => spi_enabled
);
--
-- IO SLOT 1
--
uart_inst: zpuino_uart
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(1),
wb_dat_i => slot_write(1),
wb_adr_i => slot_address(1),
wb_we_i => slot_we(1),
wb_cyc_i => slot_cyc(1),
wb_stb_i => slot_stb(1),
wb_ack_o => slot_ack(1),
wb_inta_o => slot_interrupt(1),
enabled => uart_enabled,
tx => tx,
rx => rx
);
--
-- IO SLOT 2
--
gpio_inst: zpuino_gpio
generic map (
gpio_count => zpuino_gpio_count
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(2),
wb_dat_i => slot_write(2),
wb_adr_i => slot_address(2),
wb_we_i => slot_we(2),
wb_cyc_i => slot_cyc(2),
wb_stb_i => slot_stb(2),
wb_ack_o => slot_ack(2),
wb_inta_o => slot_interrupt(2),
spp_data => gpio_bus_in_record.gpio_spp_data,
spp_read => gpio_bus_out_record.gpio_spp_read,
gpio_i => gpio_bus_in_record.gpio_i,
gpio_t => gpio_bus_out_record.gpio_t,
gpio_o => gpio_o_reg,
spp_cap_in => spp_cap_in,
spp_cap_out => spp_cap_out
);
--
-- IO SLOT 3
--
timers_inst: zpuino_timers
generic map (
A_TSCENABLED => true,
A_PWMCOUNT => 1,
A_WIDTH => 16,
A_PRESCALER_ENABLED => true,
A_BUFFERS => true,
B_TSCENABLED => false,
B_PWMCOUNT => 1,
B_WIDTH => 8,
B_PRESCALER_ENABLED => false,
B_BUFFERS => false
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(3),
wb_dat_i => slot_write(3),
wb_adr_i => slot_address(3),
wb_we_i => slot_we(3),
wb_cyc_i => slot_cyc(3),
wb_stb_i => slot_stb(3),
wb_ack_o => slot_ack(3),
wb_inta_o => slot_interrupt(3), -- We use two interrupt lines
wb_intb_o => slot_interrupt(4), -- so we borrow intr line from slot 4
pwm_a_out => timers_pwm(0 downto 0),
pwm_b_out => timers_pwm(1 downto 1)
);
--
-- IO SLOT 4 - DO NOT USE (it's already mapped to Interrupt Controller)
--
--
-- IO SLOT 5
--
--
-- sigmadelta_inst: zpuino_sigmadelta
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(5),
-- wb_dat_i => slot_write(5),
-- wb_adr_i => slot_address(5),
-- wb_we_i => slot_we(5),
-- wb_cyc_i => slot_cyc(5),
-- wb_stb_i => slot_stb(5),
-- wb_ack_o => slot_ack(5),
-- wb_inta_o => slot_interrupt(5),
--
-- raw_out => sigmadelta_raw,
-- spp_data => sigmadelta_spp_data,
-- spp_en => sigmadelta_spp_en,
-- sync_in => '1'
-- );
--
-- IO SLOT 6
--
-- slot1: zpuino_spi
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(6),
-- wb_dat_i => slot_write(6),
-- wb_adr_i => slot_address(6),
-- wb_we_i => slot_we(6),
-- wb_cyc_i => slot_cyc(6),
-- wb_stb_i => slot_stb(6),
-- wb_ack_o => slot_ack(6),
-- wb_inta_o => slot_interrupt(6),
--
-- mosi => spi2_mosi,
-- miso => spi2_miso,
-- sck => spi2_sck,
-- enabled => open
-- );
--
--
--
--
-- IO SLOT 7
--
crc16_inst: zpuino_crc16
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(7),
wb_dat_i => slot_write(7),
wb_adr_i => slot_address(7),
wb_we_i => slot_we(7),
wb_cyc_i => slot_cyc(7),
wb_stb_i => slot_stb(7),
wb_ack_o => slot_ack(7),
wb_inta_o => slot_interrupt(7)
);
--
-- IO SLOT 8 (optional)
--
-- adc_inst: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(8),
-- wb_dat_i => slot_write(8),
-- wb_adr_i => slot_address(8),
-- wb_we_i => slot_we(8),
-- wb_cyc_i => slot_cyc(8),
-- wb_stb_i => slot_stb(8),
-- wb_ack_o => slot_ack(8),
-- wb_inta_o => slot_interrupt(8)
-- );
--
-- --
-- -- IO SLOT 9
-- --
--
-- slot9: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(9),
-- wb_dat_i => slot_write(9),
-- wb_adr_i => slot_address(9),
-- wb_we_i => slot_we(9),
-- wb_cyc_i => slot_cyc(9),
-- wb_stb_i => slot_stb(9),
-- wb_ack_o => slot_ack(9),
-- wb_inta_o => slot_interrupt(9)
-- );
--
-- --
-- -- IO SLOT 10
-- --
--
-- slot10: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(10),
-- wb_dat_i => slot_write(10),
-- wb_adr_i => slot_address(10),
-- wb_we_i => slot_we(10),
-- wb_cyc_i => slot_cyc(10),
-- wb_stb_i => slot_stb(10),
-- wb_ack_o => slot_ack(10),
-- wb_inta_o => slot_interrupt(10)
-- );
--
-- --
-- -- IO SLOT 11
-- --
--
-- slot11: zpuino_empty_device
---- generic map (
---- bits => 4
---- )
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(11),
-- wb_dat_i => slot_write(11),
-- wb_adr_i => slot_address(11),
-- wb_we_i => slot_we(11),
-- wb_cyc_i => slot_cyc(11),
-- wb_stb_i => slot_stb(11),
-- wb_ack_o => slot_ack(11),
--
-- wb_inta_o => slot_interrupt(11)
--
---- tx => uart2_tx,
---- rx => uart2_rx
-- );
--
-- --
-- -- IO SLOT 12
-- --
--
-- slot12: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(12),
-- wb_dat_i => slot_write(12),
-- wb_adr_i => slot_address(12),
-- wb_we_i => slot_we(12),
-- wb_cyc_i => slot_cyc(12),
-- wb_stb_i => slot_stb(12),
-- wb_ack_o => slot_ack(12),
-- wb_inta_o => slot_interrupt(12)
-- );
--
-- --
-- -- IO SLOT 13
-- --
--
-- slot13: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(13),
-- wb_dat_i => slot_write(13),
-- wb_adr_i => slot_address(13),
-- wb_we_i => slot_we(13),
-- wb_cyc_i => slot_cyc(13),
-- wb_stb_i => slot_stb(13),
-- wb_ack_o => slot_ack(13),
-- wb_inta_o => slot_interrupt(13)
--
---- data_out => ym2149_audio_data
-- );
--
-- --
-- -- IO SLOT 14
-- --
--
-- slot14: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(14),
-- wb_dat_i => slot_write(14),
-- wb_adr_i => slot_address(14),
-- wb_we_i => slot_we(14),
-- wb_cyc_i => slot_cyc(14),
-- wb_stb_i => slot_stb(14),
-- wb_ack_o => slot_ack(14),
-- wb_inta_o => slot_interrupt(14)
--
---- clk_1MHZ => sysclk_1mhz,
---- audio_data => sid_audio_data
--
-- );
--
-- --
-- -- IO SLOT 15
-- --
--
-- slot15: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(15),
-- wb_dat_i => slot_write(15),
-- wb_adr_i => slot_address(15),
-- wb_we_i => slot_we(15),
-- wb_cyc_i => slot_cyc(15),
-- wb_stb_i => slot_stb(15),
-- wb_ack_o => slot_ack(15),
-- wb_inta_o => slot_interrupt(15)
-- );
-- -- Audio for SID
-- sid_sd: simple_sigmadelta
-- generic map (
-- BITS => 18
-- )
-- port map (
-- clk => wb_clk_i,
-- rst => wb_rst_i,
-- data_in => sid_audio_data,
-- data_out => sid_audio
-- );
-- Audio output for devices
-- ym2149_audio_dac <= ym2149_audio_data & "0000000000";
--
-- mixer: zpuino_io_audiomixer
-- port map (
-- clk => wb_clk_i,
-- rst => wb_rst_i,
-- ena => '1',
--
-- data_in1 => sid_audio_data,
-- data_in2 => ym2149_audio_dac,
-- data_in3 => sigmadelta_raw,
--
-- audio_out => platform_audio_sd
-- );
-- pin00: IOPAD port map(I => gpio_o(0), O => gpio_i(0), T => gpio_t(0), C => sysclk,PAD => WING_A(0) );
-- pin01: IOPAD port map(I => gpio_o(1), O => gpio_i(1), T => gpio_t(1), C => sysclk,PAD => WING_A(1) );
-- pin02: IOPAD port map(I => gpio_o(2), O => gpio_i(2), T => gpio_t(2), C => sysclk,PAD => WING_A(2) );
-- pin03: IOPAD port map(I => gpio_o(3), O => gpio_i(3), T => gpio_t(3), C => sysclk,PAD => WING_A(3) );
-- pin04: IOPAD port map(I => gpio_o(4), O => gpio_i(4), T => gpio_t(4), C => sysclk,PAD => WING_A(4) );
-- pin05: IOPAD port map(I => gpio_o(5), O => gpio_i(5), T => gpio_t(5), C => sysclk,PAD => WING_A(5) );
-- pin06: IOPAD port map(I => gpio_o(6), O => gpio_i(6), T => gpio_t(6), C => sysclk,PAD => WING_A(6) );
-- pin07: IOPAD port map(I => gpio_o(7), O => gpio_i(7), T => gpio_t(7), C => sysclk,PAD => WING_A(7) );
-- pin08: IOPAD port map(I => gpio_o(8), O => gpio_i(8), T => gpio_t(8), C => sysclk,PAD => WING_A(8) );
-- pin09: IOPAD port map(I => gpio_o(9), O => gpio_i(9), T => gpio_t(9), C => sysclk,PAD => WING_A(9) );
-- pin10: IOPAD port map(I => gpio_o(10),O => gpio_i(10),T => gpio_t(10),C => sysclk,PAD => WING_A(10) );
-- pin11: IOPAD port map(I => gpio_o(11),O => gpio_i(11),T => gpio_t(11),C => sysclk,PAD => WING_A(11) );
-- pin12: IOPAD port map(I => gpio_o(12),O => gpio_i(12),T => gpio_t(12),C => sysclk,PAD => WING_A(12) );
-- pin13: IOPAD port map(I => gpio_o(13),O => gpio_i(13),T => gpio_t(13),C => sysclk,PAD => WING_A(13) );
-- pin14: IOPAD port map(I => gpio_o(14),O => gpio_i(14),T => gpio_t(14),C => sysclk,PAD => WING_A(14) );
-- pin15: IOPAD port map(I => gpio_o(15),O => gpio_i(15),T => gpio_t(15),C => sysclk,PAD => WING_A(15) );
--
-- pin16: IOPAD port map(I => gpio_o(16),O => gpio_i(16),T => gpio_t(16),C => sysclk,PAD => WING_B(0) );
-- pin17: IOPAD port map(I => gpio_o(17),O => gpio_i(17),T => gpio_t(17),C => sysclk,PAD => WING_B(1) );
-- pin18: IOPAD port map(I => gpio_o(18),O => gpio_i(18),T => gpio_t(18),C => sysclk,PAD => WING_B(2) );
-- pin19: IOPAD port map(I => gpio_o(19),O => gpio_i(19),T => gpio_t(19),C => sysclk,PAD => WING_B(3) );
-- pin20: IOPAD port map(I => gpio_o(20),O => gpio_i(20),T => gpio_t(20),C => sysclk,PAD => WING_B(4) );
-- pin21: IOPAD port map(I => gpio_o(21),O => gpio_i(21),T => gpio_t(21),C => sysclk,PAD => WING_B(5) );
-- pin22: IOPAD port map(I => gpio_o(22),O => gpio_i(22),T => gpio_t(22),C => sysclk,PAD => WING_B(6) );
-- pin23: IOPAD port map(I => gpio_o(23),O => gpio_i(23),T => gpio_t(23),C => sysclk,PAD => WING_B(7) );
-- pin24: IOPAD port map(I => gpio_o(24),O => gpio_i(24),T => gpio_t(24),C => sysclk,PAD => WING_B(8) );
-- pin25: IOPAD port map(I => gpio_o(25),O => gpio_i(25),T => gpio_t(25),C => sysclk,PAD => WING_B(9) );
-- pin26: IOPAD port map(I => gpio_o(26),O => gpio_i(26),T => gpio_t(26),C => sysclk,PAD => WING_B(10) );
-- pin27: IOPAD port map(I => gpio_o(27),O => gpio_i(27),T => gpio_t(27),C => sysclk,PAD => WING_B(11) );
-- pin28: IOPAD port map(I => gpio_o(28),O => gpio_i(28),T => gpio_t(28),C => sysclk,PAD => WING_B(12) );
-- pin29: IOPAD port map(I => gpio_o(29),O => gpio_i(29),T => gpio_t(29),C => sysclk,PAD => WING_B(13) );
-- pin30: IOPAD port map(I => gpio_o(30),O => gpio_i(30),T => gpio_t(30),C => sysclk,PAD => WING_B(14) );
-- pin31: IOPAD port map(I => gpio_o(31),O => gpio_i(31),T => gpio_t(31),C => sysclk,PAD => WING_B(15) );
--
-- pin32: IOPAD port map(I => gpio_o(32),O => gpio_i(32),T => gpio_t(32),C => sysclk,PAD => WING_C(0) );
-- pin33: IOPAD port map(I => gpio_o(33),O => gpio_i(33),T => gpio_t(33),C => sysclk,PAD => WING_C(1) );
-- pin34: IOPAD port map(I => gpio_o(34),O => gpio_i(34),T => gpio_t(34),C => sysclk,PAD => WING_C(2) );
-- pin35: IOPAD port map(I => gpio_o(35),O => gpio_i(35),T => gpio_t(35),C => sysclk,PAD => WING_C(3) );
-- pin36: IOPAD port map(I => gpio_o(36),O => gpio_i(36),T => gpio_t(36),C => sysclk,PAD => WING_C(4) );
-- pin37: IOPAD port map(I => gpio_o(37),O => gpio_i(37),T => gpio_t(37),C => sysclk,PAD => WING_C(5) );
-- pin38: IOPAD port map(I => gpio_o(38),O => gpio_i(38),T => gpio_t(38),C => sysclk,PAD => WING_C(6) );
-- pin39: IOPAD port map(I => gpio_o(39),O => gpio_i(39),T => gpio_t(39),C => sysclk,PAD => WING_C(7) );
-- pin40: IOPAD port map(I => gpio_o(40),O => gpio_i(40),T => gpio_t(40),C => sysclk,PAD => WING_C(8) );
-- pin41: IOPAD port map(I => gpio_o(41),O => gpio_i(41),T => gpio_t(41),C => sysclk,PAD => WING_C(9) );
-- pin42: IOPAD port map(I => gpio_o(42),O => gpio_i(42),T => gpio_t(42),C => sysclk,PAD => WING_C(10) );
-- pin43: IOPAD port map(I => gpio_o(43),O => gpio_i(43),T => gpio_t(43),C => sysclk,PAD => WING_C(11) );
-- pin44: IOPAD port map(I => gpio_o(44),O => gpio_i(44),T => gpio_t(44),C => sysclk,PAD => WING_C(12) );
-- pin45: IOPAD port map(I => gpio_o(45),O => gpio_i(45),T => gpio_t(45),C => sysclk,PAD => WING_C(13) );
-- pin46: IOPAD port map(I => gpio_o(46),O => gpio_i(46),T => gpio_t(46),C => sysclk,PAD => WING_C(14) );
-- pin47: IOPAD port map(I => gpio_o(47),O => gpio_i(47),T => gpio_t(47),C => sysclk,PAD => WING_C(15) );
-- Other ports are special, we need to avoid outputs on input-only pins
ibufrx: IPAD port map ( PAD => RXD, O => rx, C => sysclk );
ibufmiso: IPAD port map ( PAD => SPI_FLASH_MISO, O => spi_pf_miso, C => sysclk );
obuftx: OPAD port map ( I => tx, PAD => TXD );
ospiclk: OPAD port map ( I => spi_pf_sck, PAD => SPI_FLASH_SCK );
ospics: OPAD port map ( I => gpio_o_reg(48), PAD => SPI_FLASH_CS );
ospimosi: OPAD port map ( I => spi_pf_mosi, PAD => SPI_FLASH_MOSI );
-- process(gpio_spp_read,
-- sigmadelta_spp_data,
-- timers_pwm,
-- spi2_mosi,spi2_sck)
-- begin
--
-- gpio_spp_data <= (others => DontCareValue);
--
---- gpio_spp_data(0) <= platform_audio_sd; -- PPS0 : SIGMADELTA DATA
-- gpio_spp_data(1) <= timers_pwm(0); -- PPS1 : TIMER0
-- gpio_spp_data(2) <= timers_pwm(1); -- PPS2 : TIMER1
-- gpio_spp_data(3) <= spi2_mosi; -- PPS3 : USPI MOSI
-- gpio_spp_data(4) <= spi2_sck; -- PPS4 : USPI SCK
---- gpio_spp_data(5) <= platform_audio_sd; -- PPS5 : SIGMADELTA1 DATA
-- gpio_spp_data(6) <= uart2_tx; -- PPS6 : UART2 DATA
---- gpio_spp_data(8) <= platform_audio_sd;
-- spi2_miso <= gpio_spp_read(0); -- PPS0 : USPI MISO
---- uart2_rx <= gpio_spp_read(1); -- PPS0 : USPI MISO
--
-- end process;
end behave;
|
mit
|
chcbaram/FPGA
|
zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/ZPUino_1/board_Papilio_One_500k/clkgen_hyperion.vhd
|
13
|
10525
|
--
-- System Clock generator for ZPUINO (papilio one)
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
-- This is a clockgen file for the Hyperion board type to be used with a Papilio One 500K. The sysclock runs at 92Mhz instead of 96Mhz.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;
entity clkgen_hyperion is
port (
clkin: in std_logic;
rstin: in std_logic;
clkout: out std_logic;
clkout_1mhz: out std_logic;
clk_osc_32Mhz: out std_logic;
vgaclkout: out std_logic;
rstout: out std_logic
);
end entity clkgen_hyperion;
architecture behave of clkgen_hyperion is
signal dcmlocked: std_logic;
signal dcmlocked_1mhz: std_logic;
signal dcmclock: std_logic;
signal dcmclock_1mhz: std_logic;
signal rst1_q: std_logic;
signal rst2_q: std_logic;
signal clkout_i: std_logic;
signal clkin_i: std_logic;
signal clkfb: std_logic;
signal clk0: std_logic;
signal clkin_i_1mhz: std_logic;
signal clkfb_1mhz: std_logic;
signal clk0_1mhz: std_logic;
signal clkin_i_2: std_logic;
signal vgaclk_0_b, vgaclk_fb, vgaclk_fx_b, vgaclk_in: std_logic;
begin
clk_osc_32Mhz <= clkin_i;
clkout <= clkout_i;
rstout <= rst1_q;
process(dcmlocked, dcmlocked_1mhz, clkout_i, rstin)
begin
if dcmlocked='0' or dcmlocked_1mhz='0' or rstin='1' then
rst1_q <= '1';
rst2_q <= '1';
else
if rising_edge(clkout_i) then
rst1_q <= rst2_q;
rst2_q <= '0';
end if;
end if;
end process;
-- Clock buffers
clkfx_inst: BUFG
port map (
I => dcmclock,
O => clkout_i
);
clkin_inst: IBUFG
port map (
I => clkin,
O => clkin_i
);
clkfb_inst: BUFG
port map (
I=> clk0,
O=> clkfb
);
DCM_inst : DCM
generic map (
CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5,7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
CLKFX_DIVIDE => 8,--8, -- Can be any integer from 1 to 32
CLKFX_MULTIPLY => 23,--23, -- Can be any integer from 1 to 32
CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => 31.25, -- Specify period of input clock
CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE
CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE, 1X or 2X
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or an integer from 0 to 15
DFS_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for frequency synthesis
DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL
DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
FACTORY_JF => X"C080", -- FACTORY JF Values
PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255
STARTUP_WAIT => FALSE -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
)
port map (
CLK0 => clk0, -- 0 degree DCM CLK ouptput
CLK180 => open, -- 180 degree DCM CLK output
CLK270 => open, -- 270 degree DCM CLK output
CLK2X => open, -- 2X DCM CLK output
CLK2X180 => open, -- 2X, 180 degree DCM CLK out
CLK90 => open, -- 90 degree DCM CLK output
CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE)
CLKFX => dcmclock, -- DCM CLK synthesis out (M/D)
CLKFX180 => open, -- 180 degree CLK synthesis out
LOCKED => dcmlocked, -- DCM LOCK status output
PSDONE => open, -- Dynamic phase adjust done output
STATUS => open, -- 8-bit DCM status bits output
CLKFB => clkfb, -- DCM clock feedback
CLKIN => clkin_i, -- Clock input (from IBUFG, BUFG or DCM)
PSCLK => '0', -- Dynamic phase adjust clock input
PSEN => '0', -- Dynamic phase adjust enable input
PSINCDEC => '0', -- Dynamic phase adjust increment/decrement
RST => '0' -- DCM asynchronous reset input
);
DCM_inst_1mhz : DCM
generic map (
CLKDV_DIVIDE => 16.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5,7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
CLKFX_DIVIDE => 1,--8, -- Can be any integer from 1 to 32
CLKFX_MULTIPLY => 3,--23, -- Can be any integer from 1 to 32
CLKIN_DIVIDE_BY_2 => TRUE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => 31.25, -- Specify period of input clock
CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE
CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE, 1X or 2X
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or an integer from 0 to 15
DFS_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for frequency synthesis
DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL
DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
FACTORY_JF => X"C080", -- FACTORY JF Values
PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255
STARTUP_WAIT => FALSE -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
)
port map (
CLK0 => clk0_1mhz, -- 0 degree DCM CLK ouptput
CLK180 => open, -- 180 degree DCM CLK output
CLK270 => open, -- 270 degree DCM CLK output
CLK2X => open, -- 2X DCM CLK output
CLK2X180 => open, -- 2X, 180 degree DCM CLK out
CLK90 => open, -- 90 degree DCM CLK output
CLKDV => dcmclock_1mhz, -- Divided DCM CLK out (CLKDV_DIVIDE)
CLKFX => open, -- DCM CLK synthesis out (M/D)
CLKFX180 => open, -- 180 degree CLK synthesis out
LOCKED => dcmlocked_1mhz, -- DCM LOCK status output
PSDONE => open, -- Dynamic phase adjust done output
STATUS => open, -- 8-bit DCM status bits output
CLKFB => clkfb_1mhz, -- DCM clock feedback
CLKIN => clkin_i_1mhz, -- Clock input (from IBUFG, BUFG or DCM)
PSCLK => '0', -- Dynamic phase adjust clock input
PSEN => '0', -- Dynamic phase adjust enable input
PSINCDEC => '0', -- Dynamic phase adjust increment/decrement
RST => '0' -- DCM asynchronous reset input
);
clkfx_inst_1mhz: BUFG
port map (
I => dcmclock_1mhz,
O => clkout_1mhz
);
--clkin_inst_1mhz: IBUFG
-- port map (
-- I => clkin,
-- O => clkin_i_1mhz
-- );
clkin_i_1mhz <= clk0;
clkin_i_2 <= clk0;
clkfb_inst_1mhz: BUFG
port map (
I=> clk0_1mhz,
O=> clkfb_1mhz
);
vgaclkout <= '0';
-- vgaclkfx_inst: BUFG
-- port map (
-- I => vgaclk_fx_b,
-- O => vgaclkout
-- );
-- VGADCM_inst : DCM -- Generate 50Mhz
-- generic map (
-- CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5,7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
-- CLKFX_DIVIDE => 16,--8, -- Can be any integer from 1 to 32
-- CLKFX_MULTIPLY => 25,--23, -- Can be any integer from 1 to 32
-- CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
-- CLKIN_PERIOD => 31.25, -- Specify period of input clock
-- CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE
-- CLK_FEEDBACK => "NONE", -- Specify clock feedback of NONE, 1X or 2X
-- DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or an integer from 0 to 15
-- DFS_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for frequency synthesis
-- DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL
-- DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
-- FACTORY_JF => X"C080", -- FACTORY JF Values
-- PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255
-- STARTUP_WAIT => FALSE -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
-- )
-- port map (
-- CLK0 => open,--vgaclk_0_b, -- 0 degree DCM CLK ouptput
-- CLK180 => open, -- 180 degree DCM CLK output
-- CLK270 => open, -- 270 degree DCM CLK output
-- CLK2X => open, -- 2X DCM CLK output
-- CLK2X180 => open, -- 2X, 180 degree DCM CLK out
-- CLK90 => open, -- 90 degree DCM CLK output
-- CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE)
-- CLKFX => vgaclk_fx_b, -- DCM CLK synthesis out (M/D)
-- CLKFX180 => open, -- 180 degree CLK synthesis out
-- LOCKED => open,--dcmlocked_b, -- DCM LOCK status output
-- PSDONE => open, -- Dynamic phase adjust done output
-- STATUS => open, -- 8-bit DCM status bits output
-- CLKFB => '0',--vgaclk_fb, -- DCM clock feedback
-- CLKIN => clkin_i_2, -- Clock input (from IBUFG, BUFG or DCM)
-- PSCLK => '0', -- Dynamic phase adjust clock input
-- PSEN => '0', -- Dynamic phase adjust enable input
-- PSINCDEC => '0', -- Dynamic phase adjust increment/decrement
-- RST => '0' -- DCM asynchronous reset input
-- );
end behave;
|
mit
|
chcbaram/FPGA
|
zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Benchy_Waveform_Generator/Libraries/ZPUino_1/board_Papilio_One_500k/clkgen_hyperion.vhd
|
13
|
10525
|
--
-- System Clock generator for ZPUINO (papilio one)
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
-- This is a clockgen file for the Hyperion board type to be used with a Papilio One 500K. The sysclock runs at 92Mhz instead of 96Mhz.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;
entity clkgen_hyperion is
port (
clkin: in std_logic;
rstin: in std_logic;
clkout: out std_logic;
clkout_1mhz: out std_logic;
clk_osc_32Mhz: out std_logic;
vgaclkout: out std_logic;
rstout: out std_logic
);
end entity clkgen_hyperion;
architecture behave of clkgen_hyperion is
signal dcmlocked: std_logic;
signal dcmlocked_1mhz: std_logic;
signal dcmclock: std_logic;
signal dcmclock_1mhz: std_logic;
signal rst1_q: std_logic;
signal rst2_q: std_logic;
signal clkout_i: std_logic;
signal clkin_i: std_logic;
signal clkfb: std_logic;
signal clk0: std_logic;
signal clkin_i_1mhz: std_logic;
signal clkfb_1mhz: std_logic;
signal clk0_1mhz: std_logic;
signal clkin_i_2: std_logic;
signal vgaclk_0_b, vgaclk_fb, vgaclk_fx_b, vgaclk_in: std_logic;
begin
clk_osc_32Mhz <= clkin_i;
clkout <= clkout_i;
rstout <= rst1_q;
process(dcmlocked, dcmlocked_1mhz, clkout_i, rstin)
begin
if dcmlocked='0' or dcmlocked_1mhz='0' or rstin='1' then
rst1_q <= '1';
rst2_q <= '1';
else
if rising_edge(clkout_i) then
rst1_q <= rst2_q;
rst2_q <= '0';
end if;
end if;
end process;
-- Clock buffers
clkfx_inst: BUFG
port map (
I => dcmclock,
O => clkout_i
);
clkin_inst: IBUFG
port map (
I => clkin,
O => clkin_i
);
clkfb_inst: BUFG
port map (
I=> clk0,
O=> clkfb
);
DCM_inst : DCM
generic map (
CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5,7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
CLKFX_DIVIDE => 8,--8, -- Can be any integer from 1 to 32
CLKFX_MULTIPLY => 23,--23, -- Can be any integer from 1 to 32
CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => 31.25, -- Specify period of input clock
CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE
CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE, 1X or 2X
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or an integer from 0 to 15
DFS_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for frequency synthesis
DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL
DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
FACTORY_JF => X"C080", -- FACTORY JF Values
PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255
STARTUP_WAIT => FALSE -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
)
port map (
CLK0 => clk0, -- 0 degree DCM CLK ouptput
CLK180 => open, -- 180 degree DCM CLK output
CLK270 => open, -- 270 degree DCM CLK output
CLK2X => open, -- 2X DCM CLK output
CLK2X180 => open, -- 2X, 180 degree DCM CLK out
CLK90 => open, -- 90 degree DCM CLK output
CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE)
CLKFX => dcmclock, -- DCM CLK synthesis out (M/D)
CLKFX180 => open, -- 180 degree CLK synthesis out
LOCKED => dcmlocked, -- DCM LOCK status output
PSDONE => open, -- Dynamic phase adjust done output
STATUS => open, -- 8-bit DCM status bits output
CLKFB => clkfb, -- DCM clock feedback
CLKIN => clkin_i, -- Clock input (from IBUFG, BUFG or DCM)
PSCLK => '0', -- Dynamic phase adjust clock input
PSEN => '0', -- Dynamic phase adjust enable input
PSINCDEC => '0', -- Dynamic phase adjust increment/decrement
RST => '0' -- DCM asynchronous reset input
);
DCM_inst_1mhz : DCM
generic map (
CLKDV_DIVIDE => 16.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5,7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
CLKFX_DIVIDE => 1,--8, -- Can be any integer from 1 to 32
CLKFX_MULTIPLY => 3,--23, -- Can be any integer from 1 to 32
CLKIN_DIVIDE_BY_2 => TRUE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => 31.25, -- Specify period of input clock
CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE
CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE, 1X or 2X
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or an integer from 0 to 15
DFS_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for frequency synthesis
DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL
DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
FACTORY_JF => X"C080", -- FACTORY JF Values
PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255
STARTUP_WAIT => FALSE -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
)
port map (
CLK0 => clk0_1mhz, -- 0 degree DCM CLK ouptput
CLK180 => open, -- 180 degree DCM CLK output
CLK270 => open, -- 270 degree DCM CLK output
CLK2X => open, -- 2X DCM CLK output
CLK2X180 => open, -- 2X, 180 degree DCM CLK out
CLK90 => open, -- 90 degree DCM CLK output
CLKDV => dcmclock_1mhz, -- Divided DCM CLK out (CLKDV_DIVIDE)
CLKFX => open, -- DCM CLK synthesis out (M/D)
CLKFX180 => open, -- 180 degree CLK synthesis out
LOCKED => dcmlocked_1mhz, -- DCM LOCK status output
PSDONE => open, -- Dynamic phase adjust done output
STATUS => open, -- 8-bit DCM status bits output
CLKFB => clkfb_1mhz, -- DCM clock feedback
CLKIN => clkin_i_1mhz, -- Clock input (from IBUFG, BUFG or DCM)
PSCLK => '0', -- Dynamic phase adjust clock input
PSEN => '0', -- Dynamic phase adjust enable input
PSINCDEC => '0', -- Dynamic phase adjust increment/decrement
RST => '0' -- DCM asynchronous reset input
);
clkfx_inst_1mhz: BUFG
port map (
I => dcmclock_1mhz,
O => clkout_1mhz
);
--clkin_inst_1mhz: IBUFG
-- port map (
-- I => clkin,
-- O => clkin_i_1mhz
-- );
clkin_i_1mhz <= clk0;
clkin_i_2 <= clk0;
clkfb_inst_1mhz: BUFG
port map (
I=> clk0_1mhz,
O=> clkfb_1mhz
);
vgaclkout <= '0';
-- vgaclkfx_inst: BUFG
-- port map (
-- I => vgaclk_fx_b,
-- O => vgaclkout
-- );
-- VGADCM_inst : DCM -- Generate 50Mhz
-- generic map (
-- CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5,7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
-- CLKFX_DIVIDE => 16,--8, -- Can be any integer from 1 to 32
-- CLKFX_MULTIPLY => 25,--23, -- Can be any integer from 1 to 32
-- CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
-- CLKIN_PERIOD => 31.25, -- Specify period of input clock
-- CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE
-- CLK_FEEDBACK => "NONE", -- Specify clock feedback of NONE, 1X or 2X
-- DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or an integer from 0 to 15
-- DFS_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for frequency synthesis
-- DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL
-- DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
-- FACTORY_JF => X"C080", -- FACTORY JF Values
-- PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255
-- STARTUP_WAIT => FALSE -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
-- )
-- port map (
-- CLK0 => open,--vgaclk_0_b, -- 0 degree DCM CLK ouptput
-- CLK180 => open, -- 180 degree DCM CLK output
-- CLK270 => open, -- 270 degree DCM CLK output
-- CLK2X => open, -- 2X DCM CLK output
-- CLK2X180 => open, -- 2X, 180 degree DCM CLK out
-- CLK90 => open, -- 90 degree DCM CLK output
-- CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE)
-- CLKFX => vgaclk_fx_b, -- DCM CLK synthesis out (M/D)
-- CLKFX180 => open, -- 180 degree CLK synthesis out
-- LOCKED => open,--dcmlocked_b, -- DCM LOCK status output
-- PSDONE => open, -- Dynamic phase adjust done output
-- STATUS => open, -- 8-bit DCM status bits output
-- CLKFB => '0',--vgaclk_fb, -- DCM clock feedback
-- CLKIN => clkin_i_2, -- Clock input (from IBUFG, BUFG or DCM)
-- PSCLK => '0', -- Dynamic phase adjust clock input
-- PSEN => '0', -- Dynamic phase adjust enable input
-- PSINCDEC => '0', -- Dynamic phase adjust increment/decrement
-- RST => '0' -- DCM asynchronous reset input
-- );
end behave;
|
mit
|
sinkswim/DLX-Pro
|
synthesis/DLX_synthesis_cfg/a.b-DataPath.core/a.b.e-writeback.core/a.b.e.a-mux21.vhd
|
1
|
431
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- a goes through when s='1', b with s='0'
entity mux21 is
generic(
NBIT : integer := 32
);
Port (
A: In std_logic_vector(NBIT-1 downto 0);
B: In std_logic_vector(NBIT-1 downto 0);
S: In std_logic;
Y: Out std_logic_vector(NBIT-1 downto 0)
);
end mux21;
architecture beh of MUX21 is
begin
Y <= A when S='1' else B;
end beh;
|
mit
|
chcbaram/FPGA
|
zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/Benchy/sampler.vhd
|
13
|
3330
|
----------------------------------------------------------------------------------
-- sampler.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Produces samples from la_input applying a programmable divider to the clock.
-- Sampling rate can be calculated by:
--
-- r = f / (d + 1)
--
-- Where r is the sampling rate, f is the clock frequency and d is the value
-- programmed into the divider register.
--
-- As of version 0.6 sampling on an external clock is also supported. If external
-- is set '1', the external clock will be used to sample data. (Divider is
-- ignored for this.)
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity sampler is
port(
la_input : in std_logic_vector(31 downto 0); -- 32 la_input channels
clock : in std_logic; -- internal clock
exClock : in std_logic; -- external clock
external : in std_logic; -- clock selection
data : in std_logic_vector(23 downto 0); -- configuration data
wrDivider : in std_logic; -- write divider register
sample : out std_logic_vector(31 downto 0); -- sampled data
ready : out std_logic; -- new sample ready
trig_delay : out std_logic_vector(1 downto 0);
num_scheme : in std_logic
);
end sampler;
architecture behavioral of sampler is
signal divider, counter : std_logic_vector (23 downto 0);
signal lastExClock, syncExClock : std_logic;
signal la_input_i : std_logic_vector(31 downto 0);
begin
trig_delay <=
"01" when divider = 0 else
"10" when divider = 1 else
"00";
process(la_input, num_scheme)
begin
if num_scheme = '1' then
for i in 31 downto 0 loop
la_input_i(i) <= la_input(31 - i);
end loop;
else
la_input_i <= la_input;
end if;
end process;
-- sample data
process(clock)
begin
if rising_edge(clock) then
syncExClock <= exClock;
if wrDivider = '1' then
divider <= data(23 downto 0);
counter <= (others => '0');
ready <= '0';
elsif external = '1' then
if syncExClock = '0' and lastExClock = '1' then
ready <= '1';
else
sample <= la_input_i;
ready <= '0';
end if;
lastExClock <= syncExClock;
elsif counter = divider then
sample <= la_input_i;
counter <= (others => '0');
ready <= '1';
else
counter <= counter + 1;
ready <= '0';
end if;
end if;
end process;
end behavioral;
|
mit
|
chcbaram/FPGA
|
zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Audio_RetroCade_Synth/Libraries/Benchy/Mem_Gen_36bit.vhd
|
13
|
2918
|
----------------------------------------------------------------------------------
-- Mem_Gen_36bit.vhd
--
-- Copyright (C) 2013 Jack Gassett
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://papilio.cc
--
-- Single Ported RAM, 36bit wide, depth is configurable.
--
-- Set the depth by setting the brams generic variable.
-- Depth will be 512 x brams so 12 brams will be 6K depth.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity Mem_Gen_36bit is
generic (
brams: integer := 12
);
Port ( CLK : in STD_LOGIC;
ADDR : in STD_LOGIC_VECTOR (12 downto 0);
WE : in STD_LOGIC;
DOUT : out STD_LOGIC_VECTOR (35 downto 0);
DIN : in STD_LOGIC_VECTOR (35 downto 0));
end Mem_Gen_36bit;
architecture Behavioral of Mem_Gen_36bit is
type RAMBlDOut_Type is array(2**(ADDR'length-9)-1 downto 0) of std_logic_vector(dout'range);
signal RAMBlDOut : RAMBlDOut_Type;
signal WEB : std_logic_vector((brams-1) downto 0);
begin
BlockRAMS: for i in 0 to (brams-1) generate
RAMB16_S36_inst : RAMB16_S36
generic map (
INIT => X"0", -- Value of output RAM registers at startup
SRVAL => X"0", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST" -- WRITE_FIRST, READ_FIRST or NO_CHANGE
)
port map (
DO => RAMBlDOut(i)(31 downto 0),
DOP => RAMBlDOut(i)(35 downto 32),
ADDR => ADDR(8 downto 0), -- 8-bit Address Input
CLK => CLK, -- Clock
DI => DIN(31 downto 0),
DIP => DIN(35 downto 32),
EN => '1', -- RAM Enable Input
SSR => '0', -- Synchronous Set/Reset Input
WE => WEB(i) -- Write Enable Input
);
end generate;
WEB_Dcd:for i in WEB'range generate
WEB(i) <= '1' when (we='1' and ADDR(ADDR'high downto 9)=i) else '0';
end generate ;
dout <= RAMBlDOut(CONV_INTEGER(ADDR(ADDR'high downto 9)));
end Behavioral;
|
mit
|
chcbaram/FPGA
|
zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Template_Wishbone_Example/Libraries/Wishbone_Peripherals/MISC_zpuino_sa_splitter4.vhd
|
13
|
1175
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:01:17 11/27/2013
-- Design Name:
-- Module Name: MISC_zpuino_sa_splitter4 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity MISC_zpuino_sa_splitter4 is
Port ( in1 : in STD_LOGIC;
out1 : out STD_LOGIC;
out2 : out STD_LOGIC;
out3 : out STD_LOGIC;
out4 : out STD_LOGIC);
end MISC_zpuino_sa_splitter4;
architecture Behavioral of MISC_zpuino_sa_splitter4 is
begin
out1 <= in1;
out2 <= in1;
out3 <= in1;
out4 <= in1;
end Behavioral;
|
mit
|
chcbaram/FPGA
|
zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Benchy_Sump_LogicAnalyzer_JTAG/Libraries/Wishbone_Peripherals/i2c_master_bit_ctrl.vhd
|
15
|
24493
|
---------------------------------------------------------------------
---- ----
---- WISHBONE revB2 I2C Master Core; bit-controller ----
---- ----
---- ----
---- Author: Richard Herveille ----
---- [email protected] ----
---- www.asics.ws ----
---- ----
---- Downloaded from: http://www.opencores.org/projects/i2c/ ----
---- ----
---------------------------------------------------------------------
---- ----
---- Copyright (C) 2000 Richard Herveille ----
---- [email protected] ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
---- ----
---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----
---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----
---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----
---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----
---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----
---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----
---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----
---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
---- POSSIBILITY OF SUCH DAMAGE. ----
---- ----
---------------------------------------------------------------------
-- CVS Log
--
-- $Id: i2c_master_bit_ctrl.vhd,v 1.17 2009-02-04 20:17:34 rherveille Exp $
--
-- $Date: 2009-02-04 20:17:34 $
-- $Revision: 1.17 $
-- $Author: rherveille $
-- $Locker: $
-- $State: Exp $
--
-- Change History:
-- $Log: not supported by cvs2svn $
-- Revision 1.16 2009/01/20 20:40:36 rherveille
-- Fixed type iscl_oen instead of scl_oen
--
-- Revision 1.15 2009/01/20 10:34:51 rherveille
-- Added SCL clock synchronization logic
-- Fixed slave_wait signal generation
--
-- Revision 1.14 2006/10/11 12:10:13 rherveille
-- Added missing semicolons ';' on endif
--
-- Revision 1.13 2006/10/06 10:48:24 rherveille
-- fixed short scl high pulse after clock stretch
--
-- Revision 1.12 2004/05/07 11:53:31 rherveille
-- Fixed previous fix :) Made a variable vs signal mistake.
--
-- Revision 1.11 2004/05/07 11:04:00 rherveille
-- Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit.
--
-- Revision 1.10 2004/02/27 07:49:43 rherveille
-- Fixed a bug in the arbitration-lost signal generation. VHDL version only.
--
-- Revision 1.9 2003/08/12 14:48:37 rherveille
-- Forgot an 'end if' :-/
--
-- Revision 1.8 2003/08/09 07:01:13 rherveille
-- Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
-- Fixed a potential bug in the byte controller's host-acknowledge generation.
--
-- Revision 1.7 2003/02/05 00:06:02 rherveille
-- Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles.
--
-- Revision 1.6 2003/02/01 02:03:06 rherveille
-- Fixed a few 'arbitration lost' bugs. VHDL version only.
--
-- Revision 1.5 2002/12/26 16:05:47 rherveille
-- Core is now a Multimaster I2C controller.
--
-- Revision 1.4 2002/11/30 22:24:37 rherveille
-- Cleaned up code
--
-- Revision 1.3 2002/10/30 18:09:53 rherveille
-- Fixed some reported minor start/stop generation timing issuess.
--
-- Revision 1.2 2002/06/15 07:37:04 rherveille
-- Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment.
--
-- Revision 1.1 2001/11/05 12:02:33 rherveille
-- Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
-- Code updated, is now up-to-date to doc. rev.0.4.
-- Added headers.
--
--
-------------------------------------
-- Bit controller section
------------------------------------
--
-- Translate simple commands into SCL/SDA transitions
-- Each command has 5 states, A/B/C/D/idle
--
-- start: SCL ~~~~~~~~~~~~~~\____
-- SDA XX/~~~~~~~\______
-- x | A | B | C | D | i
--
-- repstart SCL ______/~~~~~~~\___
-- SDA __/~~~~~~~\______
-- x | A | B | C | D | i
--
-- stop SCL _______/~~~~~~~~~~~
-- SDA ==\___________/~~~~~
-- x | A | B | C | D | i
--
--- write SCL ______/~~~~~~~\____
-- SDA XXX===============XX
-- x | A | B | C | D | i
--
--- read SCL ______/~~~~~~~\____
-- SDA XXXXXXX=XXXXXXXXXXX
-- x | A | B | C | D | i
--
-- Timing: Normal mode Fast mode
-----------------------------------------------------------------
-- Fscl 100KHz 400KHz
-- Th_scl 4.0us 0.6us High period of SCL
-- Tl_scl 4.7us 1.3us Low period of SCL
-- Tsu:sta 4.7us 0.6us setup time for a repeated start condition
-- Tsu:sto 4.0us 0.6us setup time for a stop conditon
-- Tbuf 4.7us 1.3us Bus free time between a stop and start condition
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity i2c_master_bit_ctrl is
port (
clk : in std_logic;
rst : in std_logic;
nReset : in std_logic;
ena : in std_logic; -- core enable signal
clk_cnt : in unsigned(15 downto 0); -- clock prescale value
cmd : in std_logic_vector(3 downto 0);
cmd_ack : out std_logic; -- command completed
busy : out std_logic; -- i2c bus busy
al : out std_logic; -- arbitration lost
din : in std_logic;
dout : out std_logic;
-- i2c lines
scl_i : in std_logic; -- i2c clock line input
scl_o : out std_logic; -- i2c clock line output
scl_oen : out std_logic; -- i2c clock line output enable, active low
sda_i : in std_logic; -- i2c data line input
sda_o : out std_logic; -- i2c data line output
sda_oen : out std_logic -- i2c data line output enable, active low
);
end entity i2c_master_bit_ctrl;
architecture structural of i2c_master_bit_ctrl is
constant I2C_CMD_NOP : std_logic_vector(3 downto 0) := "0000";
constant I2C_CMD_START : std_logic_vector(3 downto 0) := "0001";
constant I2C_CMD_STOP : std_logic_vector(3 downto 0) := "0010";
constant I2C_CMD_READ : std_logic_vector(3 downto 0) := "0100";
constant I2C_CMD_WRITE : std_logic_vector(3 downto 0) := "1000";
type states is (idle, start_a, start_b, start_c, start_d, start_e,
stop_a, stop_b, stop_c, stop_d, rd_a, rd_b, rd_c, rd_d, wr_a, wr_b, wr_c, wr_d);
signal c_state : states;
signal iscl_oen, isda_oen : std_logic; -- internal I2C lines
signal sda_chk : std_logic; -- check SDA status (multi-master arbitration)
signal dscl_oen : std_logic; -- delayed scl_oen signals
signal sSCL, sSDA : std_logic; -- synchronized SCL and SDA inputs
signal dSCL, dSDA : std_logic; -- delayed versions ofsSCL and sSDA
signal clk_en : std_logic; -- statemachine clock enable
signal scl_sync, slave_wait : std_logic; -- clock generation signals
signal ial : std_logic; -- internal arbitration lost signal
signal cnt : unsigned(15 downto 0); -- clock divider counter (synthesis)
begin
-- whenever the slave is not ready it can delay the cycle by pulling SCL low
-- delay scl_oen
process (clk, nReset)
begin
if (nReset = '0') then
dscl_oen <= '0';
elsif (clk'event and clk = '1') then
dscl_oen <= iscl_oen;
end if;
end process;
-- slave_wait is asserted when master wants to drive SCL high, but the slave pulls it low
-- slave_wait remains asserted until the slave releases SCL
process (clk, nReset)
begin
if (nReset = '0') then
slave_wait <= '0';
elsif (clk'event and clk = '1') then
slave_wait <= (iscl_oen and not dscl_oen and not sSCL) or (slave_wait and not sSCL);
end if;
end process;
-- master drives SCL high, but another master pulls it low
-- master start counting down its low cycle now (clock synchronization)
scl_sync <= dSCL and not sSCL and iscl_oen;
-- generate clk enable signal
gen_clken: process(clk, nReset)
begin
if (nReset = '0') then
cnt <= (others => '0');
clk_en <= '1';
elsif (clk'event and clk = '1') then
if ((rst = '1') or (cnt = 0) or (ena = '0') or (scl_sync = '1')) then
cnt <= clk_cnt;
clk_en <= '1';
elsif (slave_wait = '1') then
cnt <= cnt;
clk_en <= '0';
else
cnt <= cnt -1;
clk_en <= '0';
end if;
end if;
end process gen_clken;
-- generate bus status controller
bus_status_ctrl: block
signal cSCL, cSDA : std_logic_vector( 1 downto 0); -- capture SDA and SCL
signal fSCL, fSDA : std_logic_vector( 2 downto 0); -- filter inputs for SCL and SDA
signal filter_cnt : unsigned(13 downto 0); -- clock divider for filter
signal sta_condition : std_logic; -- start detected
signal sto_condition : std_logic; -- stop detected
signal cmd_stop : std_logic; -- STOP command
signal ibusy : std_logic; -- internal busy signal
begin
-- capture SCL and SDA
capture_scl_sda: process(clk, nReset)
begin
if (nReset = '0') then
cSCL <= "00";
cSDA <= "00";
elsif (clk'event and clk = '1') then
if (rst = '1') then
cSCL <= "00";
cSDA <= "00";
else
cSCL <= (cSCL(0) & scl_i);
cSDA <= (cSDA(0) & sda_i);
end if;
end if;
end process capture_scl_sda;
-- filter SCL and SDA; (attempt to) remove glitches
filter_divider: process(clk, nReset)
begin
if (nReset = '0') then
filter_cnt <= (others => '0');
elsif (clk'event and clk = '1') then
if ( (rst = '1') or (ena = '0') ) then
filter_cnt <= (others => '0');
elsif (filter_cnt = 0) then
filter_cnt <= clk_cnt(15 downto 2);
else
filter_cnt <= filter_cnt -1;
end if;
end if;
end process filter_divider;
filter_scl_sda: process(clk, nReset)
begin
if (nReset = '0') then
fSCL <= (others => '1');
fSDA <= (others => '1');
elsif (clk'event and clk = '1') then
if (rst = '1') then
fSCL <= (others => '1');
fSDA <= (others => '1');
elsif (filter_cnt = 0) then
fSCL <= (fSCL(1 downto 0) & cSCL(1));
fSDA <= (fSDA(1 downto 0) & cSDA(1));
end if;
end if;
end process filter_scl_sda;
-- generate filtered SCL and SDA signals
scl_sda: process(clk, nReset)
begin
if (nReset = '0') then
sSCL <= '1';
sSDA <= '1';
dSCL <= '1';
dSDA <= '1';
elsif (clk'event and clk = '1') then
if (rst = '1') then
sSCL <= '1';
sSDA <= '1';
dSCL <= '1';
dSDA <= '1';
else
sSCL <= (fSCL(2) and fSCL(1)) or
(fSCL(2) and fSCL(0)) or
(fSCL(1) and fSCL(0));
sSDA <= (fSDA(2) and fSDA(1)) or
(fSDA(2) and fSDA(0)) or
(fSDA(1) and fSDA(0));
dSCL <= sSCL;
dSDA <= sSDA;
end if;
end if;
end process scl_sda;
-- detect start condition => detect falling edge on SDA while SCL is high
-- detect stop condition => detect rising edge on SDA while SCL is high
detect_sta_sto: process(clk, nReset)
begin
if (nReset = '0') then
sta_condition <= '0';
sto_condition <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1') then
sta_condition <= '0';
sto_condition <= '0';
else
sta_condition <= (not sSDA and dSDA) and sSCL;
sto_condition <= (sSDA and not dSDA) and sSCL;
end if;
end if;
end process detect_sta_sto;
-- generate i2c-bus busy signal
gen_busy: process(clk, nReset)
begin
if (nReset = '0') then
ibusy <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1') then
ibusy <= '0';
else
ibusy <= (sta_condition or ibusy) and not sto_condition;
end if;
end if;
end process gen_busy;
busy <= ibusy;
-- generate arbitration lost signal
-- aribitration lost when:
-- 1) master drives SDA high, but the i2c bus is low
-- 2) stop detected while not requested (detect during 'idle' state)
gen_al: process(clk, nReset)
begin
if (nReset = '0') then
cmd_stop <= '0';
ial <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1') then
cmd_stop <= '0';
ial <= '0';
else
if (clk_en = '1') then
if (cmd = I2C_CMD_STOP) then
cmd_stop <= '1';
else
cmd_stop <= '0';
end if;
end if;
if (c_state = idle) then
ial <= (sda_chk and not sSDA and isda_oen) or (sto_condition and not cmd_stop);
else
ial <= (sda_chk and not sSDA and isda_oen);
end if;
end if;
end if;
end process gen_al;
al <= ial;
-- generate dout signal, store dout on rising edge of SCL
gen_dout: process(clk, nReset)
begin
if (nReset = '0') then
dout <= '0';
elsif (clk'event and clk = '1') then
if (sSCL = '1' and dSCL = '0') then
dout <= sSDA;
end if;
end if;
end process gen_dout;
end block bus_status_ctrl;
-- generate statemachine
nxt_state_decoder : process (clk, nReset)
begin
if (nReset = '0') then
c_state <= idle;
cmd_ack <= '0';
iscl_oen <= '1';
isda_oen <= '1';
sda_chk <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1' or ial = '1') then
c_state <= idle;
cmd_ack <= '0';
iscl_oen <= '1';
isda_oen <= '1';
sda_chk <= '0';
else
cmd_ack <= '0'; -- default no acknowledge
if (clk_en = '1') then
case (c_state) is
-- idle
when idle =>
case cmd is
when I2C_CMD_START => c_state <= start_a;
when I2C_CMD_STOP => c_state <= stop_a;
when I2C_CMD_WRITE => c_state <= wr_a;
when I2C_CMD_READ => c_state <= rd_a;
when others => c_state <= idle; -- NOP command
end case;
iscl_oen <= iscl_oen; -- keep SCL in same state
isda_oen <= isda_oen; -- keep SDA in same state
sda_chk <= '0'; -- don't check SDA
-- start
when start_a =>
c_state <= start_b;
iscl_oen <= iscl_oen; -- keep SCL in same state (for repeated start)
isda_oen <= '1'; -- set SDA high
sda_chk <= '0'; -- don't check SDA
when start_b =>
c_state <= start_c;
iscl_oen <= '1'; -- set SCL high
isda_oen <= '1'; -- keep SDA high
sda_chk <= '0'; -- don't check SDA
when start_c =>
c_state <= start_d;
iscl_oen <= '1'; -- keep SCL high
isda_oen <= '0'; -- set SDA low
sda_chk <= '0'; -- don't check SDA
when start_d =>
c_state <= start_e;
iscl_oen <= '1'; -- keep SCL high
isda_oen <= '0'; -- keep SDA low
sda_chk <= '0'; -- don't check SDA
when start_e =>
c_state <= idle;
cmd_ack <= '1'; -- command completed
iscl_oen <= '0'; -- set SCL low
isda_oen <= '0'; -- keep SDA low
sda_chk <= '0'; -- don't check SDA
-- stop
when stop_a =>
c_state <= stop_b;
iscl_oen <= '0'; -- keep SCL low
isda_oen <= '0'; -- set SDA low
sda_chk <= '0'; -- don't check SDA
when stop_b =>
c_state <= stop_c;
iscl_oen <= '1'; -- set SCL high
isda_oen <= '0'; -- keep SDA low
sda_chk <= '0'; -- don't check SDA
when stop_c =>
c_state <= stop_d;
iscl_oen <= '1'; -- keep SCL high
isda_oen <= '0'; -- keep SDA low
sda_chk <= '0'; -- don't check SDA
when stop_d =>
c_state <= idle;
cmd_ack <= '1'; -- command completed
iscl_oen <= '1'; -- keep SCL high
isda_oen <= '1'; -- set SDA high
sda_chk <= '0'; -- don't check SDA
-- read
when rd_a =>
c_state <= rd_b;
iscl_oen <= '0'; -- keep SCL low
isda_oen <= '1'; -- tri-state SDA
sda_chk <= '0'; -- don't check SDA
when rd_b =>
c_state <= rd_c;
iscl_oen <= '1'; -- set SCL high
isda_oen <= '1'; -- tri-state SDA
sda_chk <= '0'; -- don't check SDA
when rd_c =>
c_state <= rd_d;
iscl_oen <= '1'; -- keep SCL high
isda_oen <= '1'; -- tri-state SDA
sda_chk <= '0'; -- don't check SDA
when rd_d =>
c_state <= idle;
cmd_ack <= '1'; -- command completed
iscl_oen <= '0'; -- set SCL low
isda_oen <= '1'; -- tri-state SDA
sda_chk <= '0'; -- don't check SDA
-- write
when wr_a =>
c_state <= wr_b;
iscl_oen <= '0'; -- keep SCL low
isda_oen <= din; -- set SDA
sda_chk <= '0'; -- don't check SDA (SCL low)
when wr_b =>
c_state <= wr_c;
iscl_oen <= '1'; -- set SCL high
isda_oen <= din; -- keep SDA
sda_chk <= '0'; -- don't check SDA yet
-- Allow some more time for SDA and SCL to settle
when wr_c =>
c_state <= wr_d;
iscl_oen <= '1'; -- keep SCL high
isda_oen <= din; -- keep SDA
sda_chk <= '1'; -- check SDA
when wr_d =>
c_state <= idle;
cmd_ack <= '1'; -- command completed
iscl_oen <= '0'; -- set SCL low
isda_oen <= din; -- keep SDA
sda_chk <= '0'; -- don't check SDA (SCL low)
when others =>
end case;
end if;
end if;
end if;
end process nxt_state_decoder;
-- assign outputs
scl_o <= '0';
scl_oen <= iscl_oen;
sda_o <= '0';
sda_oen <= isda_oen;
end architecture structural;
|
mit
|
Oblomov/pocl
|
examples/accel/rtl/vhdl/util_pkg.vhdl
|
2
|
5022
|
-- Copyright (c) 2002-2009 Tampere University.
--
-- This file is part of TTA-Based Codesign Environment (TCE).
--
-- Permission is hereby granted, free of charge, to any person obtaining a
-- copy of this software and associated documentation files (the "Software"),
-- to deal in the Software without restriction, including without limitation
-- the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- and/or sell copies of the Software, and to permit persons to whom the
-- Software is furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
-- DEALINGS IN THE SOFTWARE.
library ieee;
use ieee.std_logic_1164.all;
package util is
function flip_bits(in_vec : std_logic_vector) -- make unconstrained
return std_logic_vector;
function int_to_str (InputInt : integer)
return string;
function bit_width (num : integer)
return integer;
component util_inverter is
port (
data_in : in std_logic;
data_out : out std_logic);
end component;
end package util;
package body util is
function flip_bits(in_vec : std_logic_vector) -- make unconstrained
return std_logic_vector is
variable flipped_vec : std_logic_vector(in_vec'reverse_range);
begin
for i in in_vec'range loop
flipped_vec(i) := in_vec(i);
end loop;
return flipped_vec;
end flip_bits;
-- ------------------------------------------------------------------------
-- PROCEDURE NAME: Int_To_Str
--
-- PARAMETERS : InputInt - Integer to be converted to String.
-- ResultStr - String buffer for converted Integer
-- AppendPos - Position in buffer to place result
--
-- DESCRIPTION : This procedure is used to convert an input integer
-- into a string representation. The converted string
-- may be placed at a specific position in the result
-- buffer.
--
-- ------------------------------------------------------------------------
function int_to_str (InputInt : integer)
return string is
-- Look-up table. Given an int, we can get the character.
type integer_table_type is array (0 to 9) of character;
constant integer_table : integer_table_type :=
(
'0', '1', '2', '3', '4',
'5', '6', '7', '8', '9'
) ;
-- Local variables used in this function.
variable inpVal : integer := inputInt;
variable divisor : integer := 10;
variable tmpStrIndex : integer := 1;
variable tmpStr : string (1 to 256);
variable ResultStr : string (1 to 256);
variable appendPos : integer := 1;
begin
if (inpVal = 0) then
tmpStr(tmpStrIndex) := integer_table (0);
tmpStrIndex := tmpStrIndex + 1;
else
while (inpVal > 0) loop
tmpStr(tmpStrIndex) := integer_table (inpVal mod divisor);
tmpStrIndex := tmpStrIndex + 1;
inpVal := inpVal / divisor;
end loop;
end if;
if (appendPos /= 1) then
resultStr(appendPos) := ',';
appendPos := appendPos + 1;
end if;
for i in tmpStrIndex-1 downto 1 loop
resultStr(appendPos) := tmpStr(i);
appendPos := appendPos + 1;
end loop;
return ResultStr;
end int_to_str;
function bit_width (num : integer) return integer is
variable count : integer;
begin
count := 1;
if (num <= 0) then return 0;
elsif (num <= 2**10) then
for i in 1 to 10 loop
if (2**count >= num) then
return i;
end if;
count := count + 1;
end loop;
elsif (num <= 2**20) then
for i in 1 to 20 loop
if (2**count >= num) then
return i;
end if;
count := count + 1;
end loop;
elsif (num <= 2**30) then
for i in 1 to 30 loop
if (2**count >= num) then
return i;
end if;
count := count + 1;
end loop;
else
for i in 1 to num loop
if (2**i >= num) then
return i;
end if;
end loop;
end if;
end bit_width;
end package body util;
library ieee;
use ieee.std_logic_1164.all;
entity util_inverter is
port (
data_in : in std_logic;
data_out : out std_logic);
end util_inverter;
architecture rtl of util_inverter is
begin -- rtl
data_out <= not data_in;
end rtl;
|
mit
|
chcbaram/FPGA
|
zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Template_PSL_Base/Libraries/Benchy/spi_receiver.vhd
|
13
|
4025
|
----------------------------------------------------------------------------------
-- spi_receiver.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Receives commands from the SPI port. The first byte is the command
-- opcode, the following (optional) four byte are the command data.
-- Commands that do not have the highest bit in their opcode set are
-- considered short commands without data (1 byte long). All other commands are
-- long commands which are 5 bytes long.
--
-- After a full command has been received the data it will be latched until the
-- next command is issued. A valid command can be detected by checking if the
-- execute output is set.
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity spi_receiver is
port(
rx : in std_logic;
clock : in std_logic;
sclk : in std_logic;
cmd : out std_logic_vector (39 downto 0);
execute : out std_logic;
reset : in std_logic;
cs : in std_logic
);
end spi_receiver;
architecture behavioral of spi_receiver is
type states is (IDLE, READ_OPCODE, WAIT_CS, READ_DATA);
signal state: states;
signal rx_buf : std_logic_vector(7 downto 0);
signal data_buf : std_logic_vector(31 downto 0);
signal bits : integer range 0 to 8;
signal bytes : integer range 0 to 4;
signal code : std_logic_vector (7 downto 0);
signal data : std_logic_vector (31 downto 0);
signal exec : std_logic := '0';
signal rsync_sclk, rsync_cs : std_logic_vector (1 downto 0);
begin
cmd <= data & code;
process(clock)
begin
if rising_edge(clock) then
execute <= exec;
rsync_sclk <= rsync_sclk(0) & sclk;
rsync_cs <= rsync_cs(0) & cs;
case state is
when IDLE =>
-- cs falling edge starts rx
if rsync_cs = "10" then
state <= READ_OPCODE;
end if;
rx_buf <= (others => '0');
data_buf <= (others => '0');
bits <= 0;
bytes <= 0;
exec <= '0';
when READ_OPCODE =>
-- read bit at sclk rising edge
if reset = '1' then
state <= IDLE;
elsif rsync_sclk = "01" then
rx_buf <= rx_buf(6 downto 0) & rx;
bits <= bits + 1;
elsif bits = 8 then
-- if hi bit is set then wait for cmd data
if rx_buf(7) = '1' then
state <= WAIT_CS;
else
state <= IDLE;
exec <= '1';
end if;
code <= rx_buf;
end if;
when WAIT_CS =>
-- wait for cs falling edge before reading next data
if reset = '1' then
state <= IDLE;
elsif rsync_cs = "10" then
state <= READ_DATA;
bytes <= bytes + 1;
elsif bytes = 4 then
state <= IDLE;
data <= data_buf;
exec <= '1';
end if;
rx_buf <= (others => '0');
bits <= 0;
when READ_DATA =>
-- read bit at sclk rising edge
if reset = '1' then
state <= IDLE;
elsif rsync_sclk = "01" then
rx_buf <= rx_buf(6 downto 0) & rx;
bits <= bits + 1;
elsif bits = 8 then
state <= WAIT_CS;
data_buf <= rx_buf & data_buf(31 downto 8);
end if;
end case;
end if;
end process;
end behavioral;
|
mit
|
chcbaram/FPGA
|
zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Audio_RetroCade_Synth/Libraries/ZPUino_1/board_Papilio_One_250k/zpuino_config.vhd
|
13
|
2570
|
--
-- Configuration file for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
package zpuino_config is
-- General ZPUino configuration
type zpu_core_type is (
small,
large
);
-- ZPUino large is buggy, don't use it.
constant zpuinocore: zpu_core_type := small;
-- Set iobusyinput to 'true' to allow registered input to IO core. This also allows for IO
-- to become busy without needing to register its inputs. However, an extra clock-cycle is
-- required to access IO if this is used.
constant zpuino_iobusyinput: boolean := true;
-- For SPI blocking operation, you need to define also iobusyinput
constant zpuino_spiblocking: boolean := true;
-- Number of GPIO to map (number of FPGA pins)
constant zpuino_gpio_count: integer := 49;
-- Peripheral Pin Select
constant zpuino_pps_enabled: boolean := false;
-- Internal SPI ADC
constant zpuino_adc_enabled: boolean := true;
-- Number of IO select bits. Maps to maximum number of IO devices
constant zpuino_number_io_select_bits: integer := 4;
end package zpuino_config;
|
mit
|
chcbaram/FPGA
|
zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Benchy_Sump_LogicAnalyzer_JTAG/Libraries/ZPUino_1/board_Papilio_One_250k/zpuino_config.vhd
|
13
|
2570
|
--
-- Configuration file for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
package zpuino_config is
-- General ZPUino configuration
type zpu_core_type is (
small,
large
);
-- ZPUino large is buggy, don't use it.
constant zpuinocore: zpu_core_type := small;
-- Set iobusyinput to 'true' to allow registered input to IO core. This also allows for IO
-- to become busy without needing to register its inputs. However, an extra clock-cycle is
-- required to access IO if this is used.
constant zpuino_iobusyinput: boolean := true;
-- For SPI blocking operation, you need to define also iobusyinput
constant zpuino_spiblocking: boolean := true;
-- Number of GPIO to map (number of FPGA pins)
constant zpuino_gpio_count: integer := 49;
-- Peripheral Pin Select
constant zpuino_pps_enabled: boolean := false;
-- Internal SPI ADC
constant zpuino_adc_enabled: boolean := true;
-- Number of IO select bits. Maps to maximum number of IO devices
constant zpuino_number_io_select_bits: integer := 4;
end package zpuino_config;
|
mit
|
chcbaram/FPGA
|
zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/Wishbone_Peripherals/clk_32to288_dcm.vhd
|
13
|
6306
|
-- file: clk_32to288_dcm.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1____50.000______0.000______50.0______600.000____150.000
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary__________32.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk_32to288_dcm is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic
);
end clk_32to288_dcm;
architecture xilinx of clk_32to288_dcm is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_32to288_dcm,clk_wiz_v3_6,{component_name=clk_32to288_dcm,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=1,clkin1_period=31.25,clkin2_period=31.25,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering
signal clkfb : std_logic;
signal clk0 : std_logic;
signal clkfx : std_logic;
signal clkfbout : std_logic;
signal locked_internal : std_logic;
signal status_internal : std_logic_vector(7 downto 0);
begin
-- Input buffering
--------------------------------------
--clkin1 <= CLK_IN1;
clkin2_inst: BUFG
port map (
I => CLK_IN1,
O => clkin1
);
-- Clocking primitive
--------------------------------------
-- Instantiation of the DCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
dcm_sp_inst: DCM_SP
generic map
(CLKDV_DIVIDE => 2.000,
CLKFX_DIVIDE => 1,
CLKFX_MULTIPLY => 9,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 31.25,
CLKOUT_PHASE_SHIFT => "NONE",
CLK_FEEDBACK => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map
-- Input clock
(CLKIN => clkin1,
CLKFB => clkfb,
-- Output clocks
CLK0 => clk0,
CLK90 => open,
CLK180 => open,
CLK270 => open,
CLK2X => open,
CLK2X180 => open,
CLKFX => clkfx,
CLKFX180 => open,
CLKDV => open,
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => locked_internal,
STATUS => status_internal,
RST => '0',
-- Unused pin, tie low
DSSEN => '0');
-- Output buffering
-------------------------------------
-- no phase alignment active, connect to ground
clkfb <= '0';
-- clkout1_buf : BUFG
-- port map
-- (O => CLK_OUT1,
-- I => clkfx);
CLK_OUT1 <= clkfx;
end xilinx;
|
mit
|
chcbaram/FPGA
|
zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Template_Wishbone_Example/Libraries/Benchy/flags.vhd
|
13
|
2535
|
----------------------------------------------------------------------------------
-- flags.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Flags register.
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity flags is
port(
data : in std_logic_vector(10 downto 0);
clock : in std_logic;
write : in std_logic;
demux : out std_logic;
filter : out std_logic;
external : out std_logic;
inverted : out std_logic;
disabledGroups : out std_logic_vector (3 downto 0);
rle : out std_logic;
test_mode : out std_logic;
data_size : out std_logic_vector (1 downto 0);
num_scheme : out std_logic
);
end flags;
architecture behavioral of flags is
signal ds : std_logic_vector (1 downto 0);
begin
-- write flags
process (clock)
begin
if rising_edge(clock) then
if write = '1' then
demux <= data(0);
filter <= data(1);
external <= data(6);
inverted <= data(7);
disabledGroups <= data(5 downto 2);
rle <= data(8);
num_scheme <= data(9);
test_mode <= data(10);
data_size <= ds;
end if;
end if;
end process;
ds <=
"01" when data(5 downto 2) = "1110" else
"01" when data(5 downto 2) = "1101" else
"01" when data(5 downto 2) = "1011" else
"01" when data(5 downto 2) = "0111" else
"10" when data(5 downto 2) = "1100" else
"10" when data(5 downto 2) = "1010" else
"10" when data(5 downto 2) = "0110" else
"10" when data(5 downto 2) = "1001" else
"10" when data(5 downto 2) = "0101" else
"10" when data(5 downto 2) = "0011" else
"00";
end behavioral;
|
mit
|
chcbaram/FPGA
|
zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Audio_RetroCade_Synth/Libraries/ZPUino_1/board_Papilio_Pro/sdram_hamster.vhd
|
14
|
25283
|
------------------------------------------------------
-- FSM for a SDRAM controller
--
-- Version 0.1 - Ready to simulate
--
-- Author: Mike Field ([email protected])
--
-- Feel free to use it however you would like, but
-- just drop me an email to say thanks.
-------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
entity sdram_controller is
generic (
HIGH_BIT: integer := 24;
MHZ: integer := 96;
REFRESH_CYCLES: integer := 4096;
ADDRESS_BITS: integer := 12
);
PORT (
clock_100: in std_logic;
clock_100_delayed_3ns: in std_logic;
rst: in std_logic;
-- Signals to/from the SDRAM chip
DRAM_ADDR : OUT STD_LOGIC_VECTOR (ADDRESS_BITS-1 downto 0);
DRAM_BA : OUT STD_LOGIC_VECTOR (1 downto 0);
DRAM_CAS_N : OUT STD_LOGIC;
DRAM_CKE : OUT STD_LOGIC;
DRAM_CLK : OUT STD_LOGIC;
DRAM_CS_N : OUT STD_LOGIC;
DRAM_DQ : INOUT STD_LOGIC_VECTOR(15 downto 0);
DRAM_DQM : OUT STD_LOGIC_VECTOR(1 downto 0);
DRAM_RAS_N : OUT STD_LOGIC;
DRAM_WE_N : OUT STD_LOGIC;
pending: out std_logic;
--- Inputs from rest of the system
address : IN STD_LOGIC_VECTOR (HIGH_BIT downto 2);
req_read : IN STD_LOGIC;
req_write : IN STD_LOGIC;
data_out : OUT STD_LOGIC_VECTOR (31 downto 0);
data_out_valid : OUT STD_LOGIC;
data_in : IN STD_LOGIC_VECTOR (31 downto 0);
data_mask : IN STD_LOGIC_VECTOR (3 downto 0)
);
end entity;
architecture rtl of sdram_controller is
type reg is record
address : std_logic_vector(ADDRESS_BITS-1 downto 0);
bank : std_logic_vector( 1 downto 0);
init_counter : std_logic_vector(14 downto 0);
rf_counter : integer;
rf_pending : std_logic;
rd_pending : std_logic;
wr_pending : std_logic;
act_row : std_logic_vector(ADDRESS_BITS-1 downto 0);
act_ba : std_logic_vector(1 downto 0);
data_out_low : std_logic_vector(15 downto 0);
req_addr_q : std_logic_vector(HIGH_BIT downto 2);
req_data_write: std_logic_vector(31 downto 0);
req_mask : std_logic_vector(3 downto 0);
data_out_valid: std_logic;
dq_masks : std_logic_vector(1 downto 0);
tristate : std_logic;
end record;
signal r : reg;
signal n : reg;
signal rstate : std_logic_vector(8 downto 0);
signal nstate : std_logic_vector(8 downto 0);
signal rdata_write : std_logic_vector(15 downto 0);
signal ndata_write : std_logic_vector(15 downto 0);
-- Vectors for each SDRAM 'command'
--- CS_N, RAS_N, CAS_N, WE_N
constant cmd_nop : std_logic_vector(3 downto 0) := "0111";
constant cmd_read : std_logic_vector(3 downto 0) := "0101"; -- Must be sure A10 is low.
constant cmd_write : std_logic_vector(3 downto 0) := "0100";
constant cmd_act : std_logic_vector(3 downto 0) := "0011";
constant cmd_pre : std_logic_vector(3 downto 0) := "0010"; -- Must set A10 to '1'.
constant cmd_ref : std_logic_vector(3 downto 0) := "0001";
constant cmd_mrs : std_logic_vector(3 downto 0) := "0000"; -- Mode register set
-- State assignments
constant s_init_nop_id: std_logic_vector(4 downto 0) := "00000";
constant s_init_nop : std_logic_vector(8 downto 0) := s_init_nop_id & cmd_nop;
constant s_init_pre : std_logic_vector(8 downto 0) := s_init_nop_id & cmd_pre;
constant s_init_ref : std_logic_vector(8 downto 0) := s_init_nop_id & cmd_ref;
constant s_init_mrs : std_logic_vector(8 downto 0) := s_init_nop_id & cmd_mrs;
constant s_idle_id: std_logic_vector(4 downto 0) := "00001";
constant s_idle : std_logic_vector(8 downto 0) := s_idle_id & cmd_nop;
constant s_rf0_id: std_logic_vector(4 downto 0) := "00010";
constant s_rf0 : std_logic_vector(8 downto 0) := s_rf0_id & cmd_ref;
constant s_rf1_id: std_logic_vector(4 downto 0) := "00011";
constant s_rf1 : std_logic_vector(8 downto 0) := "00011" & cmd_nop;
constant s_rf2_id: std_logic_vector(4 downto 0) := "00100";
constant s_rf2 : std_logic_vector(8 downto 0) := "00100" & cmd_nop;
constant s_rf3_id: std_logic_vector(4 downto 0) := "00101";
constant s_rf3 : std_logic_vector(8 downto 0) := "00101" & cmd_nop;
constant s_rf4_id: std_logic_vector(4 downto 0) := "00110";
constant s_rf4 : std_logic_vector(8 downto 0) := "00110" & cmd_nop;
constant s_rf5_id: std_logic_vector(4 downto 0) := "00111";
constant s_rf5 : std_logic_vector(8 downto 0) := "00111" & cmd_nop;
constant s_ra0_id: std_logic_vector(4 downto 0) := "01000";
constant s_ra0 : std_logic_vector(8 downto 0) := "01000" & cmd_act;
constant s_ra1_id: std_logic_vector(4 downto 0) := "01001";
constant s_ra1 : std_logic_vector(8 downto 0) := "01001" & cmd_nop;
constant s_ra2_id: std_logic_vector(4 downto 0) := "01010";
constant s_ra2 : std_logic_vector(8 downto 0) := "01010" & cmd_nop;
constant s_dr0_id: std_logic_vector(4 downto 0) := "01011";
constant s_dr0 : std_logic_vector(8 downto 0) := "01011" & cmd_pre;
constant s_dr1_id: std_logic_vector(4 downto 0) := "01100";
constant s_dr1 : std_logic_vector(8 downto 0) := "01100" & cmd_nop;
constant s_wr0_id: std_logic_vector(4 downto 0) := "01101";
constant s_wr0 : std_logic_vector(8 downto 0) := "01101" & cmd_write;
constant s_wr1_id: std_logic_vector(4 downto 0) := "01110";
constant s_wr1 : std_logic_vector(8 downto 0) := "01110" & cmd_nop;
constant s_wr2_id: std_logic_vector(4 downto 0) := "01111";
constant s_wr2 : std_logic_vector(8 downto 0) := "01111" & cmd_nop;
constant s_wr3_id: std_logic_vector(4 downto 0) := "10000";
constant s_wr3 : std_logic_vector(8 downto 0) := "10000" & cmd_write;
constant s_rd0_id: std_logic_vector(4 downto 0) := "10001";
constant s_rd0 : std_logic_vector(8 downto 0) := "10001" & cmd_read;
constant s_rd1_id: std_logic_vector(4 downto 0) := "10010";
constant s_rd1 : std_logic_vector(8 downto 0) := "10010" & cmd_read;
constant s_rd2_id: std_logic_vector(4 downto 0) := "10011";
constant s_rd2 : std_logic_vector(8 downto 0) := "10011" & cmd_nop;
constant s_rd3_id: std_logic_vector(4 downto 0) := "10100";
constant s_rd3 : std_logic_vector(8 downto 0) := "10100" & cmd_read;
constant s_rd4_id: std_logic_vector(4 downto 0) := "10101";
constant s_rd4 : std_logic_vector(8 downto 0) := "10101" & cmd_read;
constant s_rd5_id: std_logic_vector(4 downto 0) := "10110";
constant s_rd5 : std_logic_vector(8 downto 0) := "10110" & cmd_read;
constant s_rd6_id: std_logic_vector(4 downto 0) := "10111";
constant s_rd6 : std_logic_vector(8 downto 0) := "10111" & cmd_nop;
constant s_rd7_id: std_logic_vector(4 downto 0) := "11000";
constant s_rd7 : std_logic_vector(8 downto 0) := "11000" & cmd_nop;
constant s_rd8_id: std_logic_vector(4 downto 0) := "11001";
constant s_rd8 : std_logic_vector(8 downto 0) := "11001" & cmd_nop;
constant s_rd9_id: std_logic_vector(4 downto 0) := "11011";
constant s_rd9 : std_logic_vector(8 downto 0) := "11011" & cmd_nop;
constant s_drdr0_id: std_logic_vector(4 downto 0) := "11101";
constant s_drdr0 : std_logic_vector(8 downto 0) := "11101" & cmd_pre;
constant s_drdr1_id: std_logic_vector(4 downto 0) := "11110";
constant s_drdr1 : std_logic_vector(8 downto 0) := "11110" & cmd_nop;
constant s_drdr2_id: std_logic_vector(4 downto 0) := "11111";
constant s_drdr2 : std_logic_vector(8 downto 0) := "11111" & cmd_nop;
signal addr_row : std_logic_vector(ADDRESS_BITS-1 downto 0);
signal addr_bank: std_logic_vector(1 downto 0);
constant COLUMN_HIGH: integer := HIGH_BIT - addr_row'LENGTH - addr_bank'LENGTH - 1; -- last 1 means 16 bit width
signal addr_col : std_logic_vector(7 downto 0);
signal captured : std_logic_vector(15 downto 0);
signal busy: std_logic;
constant tOPD: time := 2.1 ns;
constant tHZ: time := 8 ns;
signal dram_dq_dly : std_logic_vector(15 downto 0);
-- Debug only
signal debug_cmd: std_logic_vector(3 downto 0);
signal not_clock_100_delayed_3ns: std_logic;
constant RELOAD: integer := (((64000000/REFRESH_CYCLES)*MHZ)/1000) - 10;
attribute IOB: string;
signal i_DRAM_CS_N: std_logic;
attribute IOB of i_DRAM_CS_N: signal is "true";
signal i_DRAM_RAS_N: std_logic;
attribute IOB of i_DRAM_RAS_N: signal is "true";
signal i_DRAM_CAS_N: std_logic;
attribute IOB of i_DRAM_CAS_N: signal is "true";
signal i_DRAM_WE_N: std_logic;
attribute IOB of i_DRAM_WE_N: signal is "true";
signal i_DRAM_ADDR: std_logic_vector(ADDRESS_BITS-1 downto 0);
attribute IOB of i_DRAM_ADDR: signal is "true";
signal i_DRAM_BA: std_logic_vector(1 downto 0);
attribute IOB of i_DRAM_BA: signal is "true";
signal i_DRAM_DQM: std_logic_vector(1 downto 0);
attribute IOB of i_DRAM_DQM: signal is "true";
attribute IOB of rdata_write: signal is "true";
attribute IOB of captured: signal is "true";
signal i_DRAM_CLK: std_logic;
attribute fsm_encoding: string;
attribute fsm_encoding of nstate: signal is "user";
attribute fsm_encoding of rstate: signal is "user";
begin
debug_cmd <= rstate(3 downto 0);
-- Addressing is in 32 bit words - twice that of the DRAM width,
-- so each burst of four access two system words.
--addr_row <= address(23 downto 11);
--addr_bank <= address(10 downto 9);
process(r.req_addr_q)
begin
addr_bank <= r.req_addr_q(HIGH_BIT downto (HIGH_BIT-addr_bank'LENGTH)+1);
-- (24-2) downto (24-2 - 2 - 13 - 1)
-- 22 downto 6
addr_row <= --r.req_addr_q(HIGH_BIT-addr_bank'LENGTH downto COLUMN_HIGH+2);
r.req_addr_q(ADDRESS_BITS-1+9 downto 9);
addr_col <= (others => '0');
addr_col <= --r.req_addr_q(COLUMN_HIGH+1 downto 2) & "0";
r.req_addr_q(8 downto 2) & "0";
end process;
not_clock_100_delayed_3ns <= not clock_100_delayed_3ns;
clock: ODDR2
generic map (
DDR_ALIGNMENT => "NONE",
INIT => '0',
SRTYPE => "ASYNC")
port map (
D0 => '1',
D1 => '0',
Q => i_DRAM_CLK,
C0 => clock_100_delayed_3ns,
C1 => not_clock_100_delayed_3ns,
CE => '1',
R => '0',
S => '0'
);
DRAM_CKE <= '1';
DRAM_CLK <= transport i_DRAM_CLK after tOPD;
i_DRAM_CS_N <= transport rstate(3) after tOPD;
DRAM_CS_N <= i_DRAM_CS_N;
i_DRAM_RAS_N <= transport rstate(2) after tOPD;
DRAM_RAS_N <= i_DRAM_RAS_N;
i_DRAM_CAS_N <= transport rstate(1) after tOPD;
DRAM_CAS_N <= i_DRAM_CAS_N;
i_DRAM_WE_N <= transport rstate(0) after tOPD;
DRAM_WE_N <= i_DRAM_WE_N;
i_DRAM_ADDR <= transport r.address after tOPD;
DRAM_ADDR <= i_DRAM_ADDR;
i_DRAM_BA <= transport r.bank after tOPD;
DRAM_BA <= i_DRAM_BA;
i_DRAM_DQM <= transport r.dq_masks after tOPD;
DRAM_DQM <= i_DRAM_DQM;
DATA_OUT <= r.data_out_low & captured;--r.data_out_low & captured;
data_out_valid <= r.data_out_valid;
DRAM_DQ <= (others => 'Z') after tHZ when r.tristate='1' else rdata_write;
pending <= '1' when r.wr_pending='1' or r.rd_pending='1' else '0';
process (r, rstate, address, req_read, rdata_write, req_write, addr_row, addr_bank, addr_col, data_in, captured)
begin
-- copy the existing values
n <= r;
nstate <= rstate;
ndata_write <= rdata_write;
if req_read = '1' then
n.rd_pending <= '1';
if r.rd_pending='0' then
n.req_addr_q <= address;
end if;
end if;
if req_write = '1' then
n.wr_pending <= '1';
if r.wr_pending='0' then
n.req_addr_q <= address;
-- Queue data here
n.req_data_write <= data_in;
n.req_mask <= data_mask;
end if;
end if;
n.dq_masks <= "11";
-- first off, do we need to perform a refresh cycle ASAP?
if r.rf_counter = RELOAD then -- 781 = 64,000,000ns / 8192 / 10ns
n.rf_counter <= 0;
n.rf_pending <= '1';
else
-- only start looking for refreshes outside of the initialisation state.
if not(rstate(8 downto 4) = s_init_nop(8 downto 4)) then
n.rf_counter <= r.rf_counter + 1;
end if;
end if;
-- Set the data bus into HIZ, high and low bytes masked
--DRAM_DQ <= (others => 'Z');
n.tristate <= '0';
n.init_counter <= r.init_counter-1;
--ndata_write <= (others => DontCareValue);
n.data_out_valid <= '0'; -- alvie- here, no ?
-- Process the FSM
case rstate(8 downto 4) is
when s_init_nop_id => --s_init_nop(8 downto 4) =>
nstate <= s_init_nop;
n.address <= (others => '0');
n.bank <= (others => '0');
n.act_ba <= (others => '0');
n.rf_counter <= 0;
-- n.data_out_valid <= '1'; -- alvie- not here
-- T-130, precharge all banks.
if r.init_counter = "000000010000010" then
nstate <= s_init_pre;
n.address(10) <= '1';
end if;
-- T-127, T-111, T-95, T-79, T-63, T-47, T-31, T-15, the 8 refreshes
if r.init_counter(14 downto 7) = 0 and r.init_counter(3 downto 0) = 15 then
nstate <= s_init_ref;
end if;
-- T-3, the load mode register
if r.init_counter = 3 then
nstate <= s_init_mrs;
-- Mode register is as follows:
-- resvd wr_b OpMd CAS=3 Seq bust=1
n.address <= "00" & "0" & "00" & "011" & "0" & "000";
-- resvd
n.bank <= "00";
end if;
-- T-1 The switch to the FSM (first command will be a NOP
if r.init_counter = 1 then
nstate <= s_idle;
end if;
------------------------------
-- The Idle section
------------------------------
when s_idle_id =>
nstate <= s_idle;
-- do we have to activate a row?
if r.rd_pending = '1' or r.wr_pending = '1' then
nstate <= s_ra0;
n.address <= addr_row;
n.act_row <= addr_row;
n.bank <= addr_bank;
end if;
-- refreshes take priority over everything
if r.rf_pending = '1' then
nstate <= s_rf0;
n.rf_pending <= '0';
end if;
------------------------------
-- Row activation
-- s_ra2 is also the "idle with active row" state and provides
-- a resting point between operations on the same row
------------------------------
when s_ra0_id =>
nstate <= s_ra1;
when s_ra1_id =>
nstate <= s_ra2;
when s_ra2_id=>
-- we can stay in this state until we have something to do
nstate <= s_ra2;
n.tristate<='0';
if r.rf_pending = '1' then
nstate <= s_dr0;
n.address(10) <= '1';
else
-- If there is a read pending, deactivate the row
if r.rd_pending = '1' or r.wr_pending = '1' then
nstate <= s_dr0;
n.address(10) <= '1';
end if;
-- unless we have a read to perform on the same row? do that instead
if r.rd_pending = '1' and r.act_row = addr_row and addr_bank=r.bank then
nstate <= s_rd0;
n.address <= (others => '0');
n.address(addr_col'HIGH downto 0) <= addr_col;
n.bank <= addr_bank;
n.act_ba <= addr_bank;
n.dq_masks <= "00";
n.rd_pending <= '0';
--n.tristate<='1';
end if;
-- unless we have a write on the same row? writes take priroty over reads
if r.wr_pending = '1' and r.act_row = addr_row and addr_bank=r.bank then
nstate <= s_wr0;
n.address <= (others => '0');
n.address(addr_col'HIGH downto 0) <= addr_col;
ndata_write <= r.req_data_write(31 downto 16);
n.bank <= addr_bank;
n.act_ba <= addr_bank;
n.dq_masks<= not r.req_mask(3 downto 2);
n.wr_pending <= '0';
--n.tristate <= '0';
end if;
end if;
-- nstate <= s_dr0;
-- n.address(10) <= '1';
-- n.rd_pending <= r.rd_pending;
-- n.wr_pending <= r.wr_pending;
--n.tristate <= '0';
--end if;
------------------------------------------------------
-- Deactivate the current row and return to idle state
------------------------------------------------------
when s_dr0_id =>
nstate <= s_dr1;
when s_dr1_id =>
nstate <= s_idle;
------------------------------
-- The Refresh section
------------------------------
when s_rf0_id =>
nstate <= s_rf1;
when s_rf1_id =>
nstate <= s_rf2;
when s_rf2_id =>
nstate <= s_rf3;
when s_rf3_id =>
nstate <= s_rf4;
when s_rf4_id =>
nstate <= s_rf5;
when s_rf5_id =>
nstate <= s_idle;
------------------------------
-- The Write section
------------------------------
when s_wr0_id =>
nstate <= s_wr3;
n.bank <= addr_bank;
n.address(0) <= '1';
ndata_write <= r.req_data_write(15 downto 0);--data_in(31 downto 16);
--DRAM_DQ <= rdata_write;
n.dq_masks<= not r.req_mask(1 downto 0);
n.tristate <= '0';
when s_wr1_id => null;
when s_wr2_id =>
nstate <= s_dr0;
n.address(10) <= '1';
when s_wr3_id =>
-- Default to the idle+row active state
nstate <= s_ra2;
--DRAM_DQ <= rdata_write;
n.data_out_valid<='1'; -- alvie- ack write
n.tristate <= '0';
n.dq_masks<= "11";
-- If there is a read or write then deactivate the row
--if r.rd_pending = '1' or r.wr_pending = '1' then
-- nstate <= s_dr0;
-- n.address(10) <= '1';
--end if;
-- But if there is a read pending in the same row, do that
--if r.rd_pending = '1' and r.act_row = addr_row and r.act_ba = addr_bank then
-- nstate <= s_rd0;
-- n.address <= (others => '0');
-- n.address(addr_col'HIGH downto 0) <= addr_col;
-- n.bank <= addr_bank;
-- --n.act_ba <= addr_bank;
-- n.dq_masks <= "00";
-- n.rd_pending <= '0';
--end if;
-- unless there is a write pending in the same row, do that
--if r.wr_pending = '1' and r.act_row = addr_row and r.act_ba = addr_bank then
-- nstate <= s_wr0;
-- n.address <= (others => '0');
-- n.address(addr_col'HIGH downto 0) <= addr_col;
-- n.bank <= addr_bank;
--n.act_ba <= addr_bank;
-- n.dq_masks<= "00";
-- n.wr_pending <= '0';
--end if;
-- But always try and refresh if one is pending!
if r.rf_pending = '1' then
nstate <= s_wr2; --dr0;
--n.address(10) <= '1';
end if;
------------------------------
-- The Read section
------------------------------
when s_rd0_id => -- 10001
nstate <= s_rd1;
n.tristate<='1';
n.dq_masks <= "00";
n.address(0)<='1';
when s_rd1_id => -- 10010
nstate <= s_rd2;
n.dq_masks <= "00";
n.tristate<='1';
if r.rd_pending = '1' and r.act_row = addr_row and r.act_ba=addr_bank then
nstate <= s_rd3; -- Another request came, and we can pipeline -
n.address <= (others => '0');
n.address(addr_col'HIGH downto 0) <= addr_col;
n.bank <= addr_bank;
n.act_ba <= addr_bank;
n.dq_masks<= "00";
n.rd_pending <= '0';
end if;
when s_rd2_id => -- 10011
nstate <= s_rd7;
n.dq_masks <= "00";
n.tristate<='1';
when s_rd3_id => -- 10100
nstate <= s_rd4;
n.dq_masks <= "00";
n.address(0) <= '1';
n.tristate<='1';
-- Data is still not ready...
when s_rd4_id => -- 10101
nstate <= s_rd5;
n.dq_masks <= "00";
--n.address(0)<='1';
n.tristate<='1';
if r.rd_pending = '1' and r.act_row = addr_row and r.act_ba=addr_bank then
nstate <= s_rd5; -- Another request came, and we can pipeline -
n.address <= (others => '0');
n.address(addr_col'HIGH downto 0) <= addr_col;
n.bank <= addr_bank;
n.act_ba <= addr_bank;
n.dq_masks<= "00";
n.rd_pending <= '0';
else
nstate <= s_rd6; -- NOTE: not correct
end if;
--if r.rf_pending = '1' then
-- nstate <= s_drdr0;
-- n.address(10) <= '1';
-- n.rd_pending <= r.rd_pending; -- Keep request
--end if;
n.data_out_low <= captured;
n.data_out_valid <= '1';
when s_rd5_id =>
-- If a refresh is pending then always deactivate the row
--if r.rf_pending = '1' then
-- nstate <= s_drdr0;
-- n.address(10) <= '1';
--end if;
n.address(0) <= '1';
nstate <= s_rd4; -- Another request came, and we can pipeline -
n.dq_masks <= "00";
n.tristate<='1';
when s_rd6_id =>
nstate <= s_rd7;
n.dq_masks<= "00";
n.tristate<='1';
when s_rd7_id =>
nstate <= s_ra2;
n.data_out_low <= captured;
n.data_out_valid <= '1';
n.tristate<='1';
when s_rd8_id => null;
when s_rd9_id => null;
-- The Deactivate row during read section
------------------------------
when s_drdr0_id =>
nstate <= s_drdr1;
when s_drdr1_id =>
nstate <= s_drdr2;
n.data_out_low <= captured;
n.data_out_valid <= '1';
when s_drdr2_id =>
nstate <= s_idle;
if r.rf_pending = '1' then
nstate <= s_rf0;
end if;
if r.rd_pending = '1' or r.wr_pending = '1' then
nstate <= s_ra0;
n.address <= addr_row;
n.act_row <= addr_row;
n.bank <= addr_bank;
end if;
when others =>
nstate <= s_init_nop;
end case;
end process;
--- The clock driven logic
process (clock_100, n)
begin
if clock_100'event and clock_100 = '1' then
if rst='1' then
rstate <= (others => '0');
r.address <= (others => '0');
r.bank <= (others => '0');
r.init_counter <= "100000000000000";
-- synopsys translate_off
r.init_counter <= "000000100000000";
-- synopsys translate_on
r.rf_counter <= 0;
r.rf_pending <= '0';
r.rd_pending <= '0';
r.wr_pending <= '0';
r.act_row <= (others => '0');
r.data_out_low <= (others => '0');
r.data_out_valid <= '0';
r.dq_masks <= "11";
r.tristate<='1';
else
r <= n;
rstate <= nstate;
rdata_write <= ndata_write;
end if;
end if;
end process;
dram_dq_dly <= transport dram_dq after 1.9 ns;
-- process (clock_100_delayed_3ns, dram_dq_dly)
-- begin
-- if clock_100_delayed_3ns'event and clock_100_delayed_3ns = '1' then
-- captured <= dram_dq_dly;
-- end if;
-- end process;
process (clock_100)
begin
if falling_edge(clock_100) then
captured <= dram_dq_dly;
end if;
end process;
end rtl;
|
mit
|
chcbaram/FPGA
|
zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Benchy_Sump_LogicAnalyzer/Libraries/ZPUino_1/board_Papilio_Pro/stack.vhd
|
14
|
1802
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library work;
use work.zpu_config.all;
use work.zpupkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity zpuino_stack is
port (
stack_clk: in std_logic;
stack_a_read: out std_logic_vector(wordSize-1 downto 0);
stack_b_read: out std_logic_vector(wordSize-1 downto 0);
stack_a_write: in std_logic_vector(wordSize-1 downto 0);
stack_b_write: in std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: in std_logic_vector(3 downto 0);
stack_a_enable: in std_logic;
stack_b_writeenable: in std_logic_vector(3 downto 0);
stack_b_enable: in std_logic;
stack_a_addr: in std_logic_vector(stackSize_bits-1 downto 2);
stack_b_addr: in std_logic_vector(stackSize_bits-1 downto 2)
);
end entity zpuino_stack;
architecture behave of zpuino_stack is
signal dipa,dipb: std_logic_vector(0 downto 0) := (others => '0');
begin
stackram: for i in 0 to 3 generate
stackmem: RAMB16_S9_S9
generic map (
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
SIM_COLLISION_CHECK => "NONE"
)
port map (
DOA => stack_a_read( ((i+1)*8)-1 downto (i*8)),
DOB => stack_b_read( ((i+1)*8)-1 downto (i*8)),
DOPA => open,
DOPB => open,
ADDRA => stack_a_addr(stackSize_bits-1 downto 2),
ADDRB => stack_b_addr(stackSize_bits-1 downto 2),
CLKA => stack_clk,
CLKB => stack_clk,
DIA => stack_a_write( ((i+1)*8)-1 downto (i*8)),
DIB => stack_b_write( ((i+1)*8)-1 downto (i*8)),
DIPA => dipa,
DIPB => dipb,
ENA => stack_a_enable,
ENB => stack_b_enable,
SSRA => '0',
SSRB => '0',
WEA => stack_a_writeenable(i),
WEB => stack_b_writeenable(i)
);
end generate;
end behave;
|
mit
|
chcbaram/FPGA
|
zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/ZPUino_1/board_Papilio_Pro/stack.vhd
|
14
|
1802
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library work;
use work.zpu_config.all;
use work.zpupkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity zpuino_stack is
port (
stack_clk: in std_logic;
stack_a_read: out std_logic_vector(wordSize-1 downto 0);
stack_b_read: out std_logic_vector(wordSize-1 downto 0);
stack_a_write: in std_logic_vector(wordSize-1 downto 0);
stack_b_write: in std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: in std_logic_vector(3 downto 0);
stack_a_enable: in std_logic;
stack_b_writeenable: in std_logic_vector(3 downto 0);
stack_b_enable: in std_logic;
stack_a_addr: in std_logic_vector(stackSize_bits-1 downto 2);
stack_b_addr: in std_logic_vector(stackSize_bits-1 downto 2)
);
end entity zpuino_stack;
architecture behave of zpuino_stack is
signal dipa,dipb: std_logic_vector(0 downto 0) := (others => '0');
begin
stackram: for i in 0 to 3 generate
stackmem: RAMB16_S9_S9
generic map (
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
SIM_COLLISION_CHECK => "NONE"
)
port map (
DOA => stack_a_read( ((i+1)*8)-1 downto (i*8)),
DOB => stack_b_read( ((i+1)*8)-1 downto (i*8)),
DOPA => open,
DOPB => open,
ADDRA => stack_a_addr(stackSize_bits-1 downto 2),
ADDRB => stack_b_addr(stackSize_bits-1 downto 2),
CLKA => stack_clk,
CLKB => stack_clk,
DIA => stack_a_write( ((i+1)*8)-1 downto (i*8)),
DIB => stack_b_write( ((i+1)*8)-1 downto (i*8)),
DIPA => dipa,
DIPB => dipb,
ENA => stack_a_enable,
ENB => stack_b_enable,
SSRA => '0',
SSRB => '0',
WEA => stack_a_writeenable(i),
WEB => stack_b_writeenable(i)
);
end generate;
end behave;
|
mit
|
chcbaram/FPGA
|
zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Wing_VGA8/Libraries/Wishbone_Peripherals/COMM_zpuino_wb_SPI.vhd
|
13
|
8523
|
--
-- SPI interface for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpuino_config.all;
use board.zpupkg.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity COMM_zpuino_wb_SPI is
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0);
mosi: out std_logic; -- Master Out Slave In
miso: in std_logic; -- Master In Slave Out
sck: out std_logic; -- SPI Clock
enabled: out std_logic -- An output that is active high when the SPI is not in a reset state
);
end entity COMM_zpuino_wb_SPI;
architecture behave of COMM_zpuino_wb_SPI is
component spi is
port (
clk: in std_logic;
rst: in std_logic;
din: in std_logic_vector(31 downto 0);
dout: out std_logic_vector(31 downto 0);
en: in std_logic;
ready: out std_logic;
transfersize: in std_logic_vector(1 downto 0);
miso: in std_logic;
mosi: out std_logic;
clk_en: out std_logic;
clkrise: in std_logic;
clkfall: in std_logic;
samprise:in std_logic
);
end component spi;
component spiclkgen is
port (
clk: in std_logic;
rst: in std_logic;
en: in std_logic;
cpol: in std_logic;
pres: in std_logic_vector(2 downto 0);
clkrise: out std_logic;
clkfall: out std_logic;
spiclk: out std_logic
);
end component spiclkgen;
signal spi_read: std_logic_vector(31 downto 0);
signal spi_en: std_logic;
signal spi_ready: std_logic;
signal spi_clk_en: std_logic;
signal spi_clkrise: std_logic;
signal spi_clkfall: std_logic;
signal spi_clk_pres: std_logic_vector(2 downto 0);
signal spi_samprise: std_logic;
signal spi_enable_q: std_logic;
signal spi_txblock_q: std_logic;
signal cpol: std_logic;
signal miso_i: std_logic;
signal spi_transfersize_q: std_logic_vector(1 downto 0);
signal trans: std_logic;
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
zspi: spi
port map (
clk => wb_clk_i,
rst => wb_rst_i,
din => wb_dat_i,
dout => spi_read,
en => spi_en,
ready => spi_ready,
transfersize => spi_transfersize_q,
miso => miso_i,
mosi => mosi,
clk_en => spi_clk_en,
clkrise => spi_clkrise,
clkfall => spi_clkfall,
samprise => spi_samprise
);
zspiclk: spiclkgen
port map (
clk => wb_clk_i,
rst => wb_rst_i,
en => spi_clk_en,
pres => spi_clk_pres,
clkrise => spi_clkrise,
clkfall => spi_clkfall,
spiclk => sck,
cpol => cpol
);
-- Simulation only
miso_i <= '0' when miso='Z' else miso;
-- Direct access (write) to SPI
--spi_en <= '1' when (wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1') and wb_adr_i(2)='1' and spi_ready='1' else '0';
busygen: if zpuino_spiblocking=true generate
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
wb_ack_o <= '0';
spi_en <= '0';
trans <= '0';
else
wb_ack_o <= '0';
spi_en <= '0';
trans <='0';
if trans='0' then
if (wb_cyc_i='1' and wb_stb_i='1') then
if wb_adr_i(2)='1' then
if spi_txblock_q='1' then
if spi_ready='1' then
if wb_we_i='1' then
spi_en <= '1';
spi_transfersize_q <= wb_adr_i(4 downto 3);
end if;
wb_ack_o <= '1';
trans <= '1';
end if;
else
if wb_we_i='1' then
spi_en <= '1';
spi_transfersize_q <= wb_adr_i(4 downto 3);
end if;
trans <= '1';
wb_ack_o <= '1';
end if;
else
trans <= '1';
wb_ack_o <= '1';
end if;
end if;
end if;
end if;
end if;
end process;
--busy <= '1' when address(2)='1' and (we='1' or re='1') and spi_ready='0' and spi_txblock_q='1' else '0';
end generate;
nobusygen: if zpuino_spiblocking=false generate
--busy <= '0';
spi_en <= '1' when (wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1') and wb_adr_i(2)='1' and spi_ready='1' else '0';
wb_ack_o <= wb_cyc_i and wb_stb_i;
end generate;
wb_inta_o <= '0';
enabled <= spi_enable_q;
-- Prescaler write
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
spi_enable_q<='0';
spi_txblock_q<='1';
--spi_transfersize_q<=(others => '0');
else
if wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' then
if wb_adr_i(2)='0' then
spi_clk_pres <= wb_dat_i(3 downto 1);
cpol <= wb_dat_i(4);
spi_samprise <= wb_dat_i(5);
spi_enable_q <= wb_dat_i(6);
spi_txblock_q <= wb_dat_i(7);
--spi_transfersize_q <= wb_dat_i(9 downto 8);
end if;
end if;
end if;
end if;
end process;
process(wb_adr_i, spi_ready, spi_read, spi_clk_pres,cpol,spi_samprise,spi_enable_q,spi_txblock_q,spi_transfersize_q)
begin
wb_dat_o <= (others =>Undefined);
case wb_adr_i(2) is
when '0' =>
wb_dat_o(0) <= spi_ready;
wb_dat_o(3 downto 1) <= spi_clk_pres;
wb_dat_o(4) <= cpol;
wb_dat_o(5) <= spi_samprise;
wb_dat_o(6) <= spi_enable_q;
wb_dat_o(7) <= spi_txblock_q;
wb_dat_o(9 downto 8) <= spi_transfersize_q;
when '1' =>
wb_dat_o <= spi_read;
when others =>
wb_dat_o <= (others => DontCareValue);
end case;
end process;
end behave;
|
mit
|
chcbaram/FPGA
|
zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Template_Wishbone_Example/Libraries/Wishbone_Peripherals/spiclkgen.vhd
|
14
|
3739
|
--
-- SPI Clock generator
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity spiclkgen is
port (
clk: in std_logic;
rst: in std_logic;
en: in std_logic;
cpol: in std_logic;
pres: in std_logic_vector(2 downto 0);
clkrise: out std_logic;
clkfall: out std_logic;
spiclk: out std_logic
);
end entity spiclkgen;
architecture behave of spiclkgen is
signal running_q: std_logic;
signal clkrise_i: std_logic;
signal clkfall_i: std_logic;
component prescaler is
port (
clk: in std_logic;
rst: in std_logic;
prescale: in std_logic_vector(2 downto 0);
event: out std_logic
);
end component prescaler;
signal prescale_q: std_logic_vector(2 downto 0);
signal clk_i: std_logic;
signal prescale_event: std_logic;
signal prescale_reset: std_logic;
begin
clkrise <= clkrise_i;
clkfall <= clkfall_i;
pr: prescaler
port map (
clk => clk,
rst => prescale_reset,
prescale => prescale_q,
event => prescale_event
);
genclk: process(clk)
begin
if rising_edge(clk) then
if rst='1' or en='0' then
spiclk <= cpol;
else
if clkrise_i='1' then
spiclk<=not cpol;
end if;
if clkfall_i='1' then
spiclk<=cpol;
end if;
end if;
end if;
end process;
process(clk)
begin
if rising_edge(clk) then
if rst='1' then
prescale_q <= (others => '0');
running_q <= '0';
prescale_reset <= '0';
else
if en='1' then
prescale_reset<='0';
running_q <= '1';
if running_q='0' then
prescale_q <= pres;
prescale_reset<='1';
end if;
else
running_q <= '0';
end if;
end if;
end if;
end process;
process(clk)
begin
if rising_edge(clk) then
if rst='1' then
clkrise_i<='0';
clkfall_i<='0';
clk_i<='0';
else
clkrise_i <= '0';
clkfall_i <= '0';
if running_q='1' and en='1' then
if prescale_event='1' then
clk_i <= not clk_i;
if clk_i='0' then
clkrise_i <= '1';
else
clkfall_i <= '1';
end if;
end if;
else
clk_i <= '0';
end if;
end if;
end if;
end process;
end behave;
|
mit
|
chcbaram/FPGA
|
ZPUino_miniSpartan6_plus/ipcore_dir/lsu.vhd
|
1
|
2964
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library work;
use work.zpu_config.all;
use work.zpupkg.all;
use work.zpuinopkg.all;
use work.zpuino_config.all;
use work.wishbonepkg.all;
entity zpuino_lsu is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 2);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_sel_o: out std_logic_vector(3 downto 0);
wb_we_o: out std_logic;
-- Connection to cpu
req: in std_logic;
we: in std_logic;
busy: out std_logic;
data_read: out std_logic_vector(wordSize-1 downto 0);
data_write: in std_logic_vector(wordSize-1 downto 0);
data_sel: in std_logic_vector(3 downto 0);
address: in std_logic_vector(maxAddrBitIncIO downto 0)
);
end zpuino_lsu;
architecture behave of zpuino_lsu is
type lsu_state is (
lsu_idle,
lsu_read,
lsu_write
);
type regs is record
state: lsu_state;
addr: std_logic_vector(maxAddrBitIncIO downto 2);
sel: std_logic_vector(3 downto 0);
data: std_logic_vector(wordSize-1 downto 0);
end record;
signal r: regs;
begin
data_read <= wb_dat_i;
process(r,wb_clk_i, we, req, wb_ack_i, address, data_write, data_sel, wb_rst_i)
variable w: regs;
begin
w:=r;
wb_cyc_o <= '0';
wb_stb_o <= 'X';
wb_we_o <= 'X';
wb_adr_o <= r.addr;
wb_dat_o <= r.data;
wb_sel_o <= r.sel;
case r.state is
when lsu_idle =>
busy <= '0';
w.addr := address(maxAddrBitIncIO downto 2);
w.data := data_write;
w.sel := data_sel;
if req='1' then
if we='1' then
w.state := lsu_write;
busy <= address(maxAddrBitIncIO);
else
w.state := lsu_read;
busy <= '1';
end if;
end if;
when lsu_write =>
wb_cyc_o <= '1';
wb_stb_o <= '1';
wb_we_o <= '1';
if req='1' then
busy <= '1';
else
busy <= '0';
end if;
if wb_ack_i='1' then
w.state := lsu_idle;
if r.addr(maxAddrBitIncIO)='1' then
busy <= '0';
end if;
end if;
when lsu_read =>
wb_cyc_o <= '1';
wb_stb_o <= '1';
wb_we_o <= '0';
busy <= not wb_ack_i;
if wb_ack_i='1' then
w.state := lsu_idle;
end if;
when others =>
end case;
if wb_rst_i='1' then
w.state := lsu_idle;
wb_cyc_o <= '0';
end if;
if rising_edge(wb_clk_i) then
r <= w;
end if;
end process;
end behave;
|
mit
|
chcbaram/FPGA
|
zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Template_PSL_Base/Libraries/Wishbone_Peripherals/MISC_zpuino_wb_SevenSeg.vhd
|
13
|
7180
|
--
-- 7 segment driver for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity MISC_zpuino_wb_SevenSeg is
generic (
BITS: integer := 2;
EXTRASIZE: integer := 32;
FREQ_PER_DISPLAY: integer := 120;
MHZ: integer := 96;
INVERT: boolean := true
);
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0);
segdata: out std_logic_vector(6 downto 0);
dot: out std_logic;
extra: out std_logic_vector(EXTRASIZE-1 downto 0);
enable: out std_logic_vector((2**BITS)-1 downto 0)
);
end entity MISC_zpuino_wb_SevenSeg;
architecture behave of MISC_zpuino_wb_SevenSeg is
-- Timer
constant COUNT: integer := 2**BITS;
constant DELAY: integer := (MHZ*1000000 / (FREQ_PER_DISPLAY*COUNT*16)) - 1; -- 16 is for brightness control
signal counter: integer range 0 to DELAY;
signal enabled: std_logic_vector(COUNT-1 downto 0) := (others => '0');
subtype segvaltype is std_logic_vector(7 downto 0);
type segstype is array(COUNT-1 downto 0) of segvaltype;
signal segs: segstype;
signal current_display: integer range 0 to COUNT-1; -- same as enashift
signal ack_q: std_logic;
signal extra_q: std_logic_vector(EXTRASIZE-1 downto 0);
signal brightctl: unsigned(3 downto 0);
signal brightcount: unsigned(3 downto 0);
signal pwm: std_logic;
signal invsig: std_logic;
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
-- Finish unpacking Wishbone signals.
invsig <= '1' when INVERT=true else '0';
enloop: for i in 0 to COUNT-1 generate
enable(i) <= (enabled(i) and pwm) xor invsig when current_display=i else invsig;
end generate;
pwm <= '1' when brightcount >= brightctl else '0';
outdata: for i in 0 to 6 generate
segdata(i) <= segs(current_display)(i) xor invsig;
end generate;
dot <= segs(current_display)(7) xor invsig;
wb_ack_o <= ack_q;
wb_inta_o <= '0';
extra <= extra_q when current_display=0 and pwm='1' else (others => '0');
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
counter <= DELAY;
current_display<=0;
brightcount <= "1111";
else
if counter=0 then
counter <= DELAY;
if brightcount="0000" then
brightcount <= "1111";
if current_display=0 then
current_display <= COUNT-1;
else
current_display <= current_display - 1;
end if;
else
brightcount <= brightcount - 1;
end if;
else
counter <= counter - 1;
end if;
end if;
end if;
end process;
process(wb_clk_i)
variable idx: std_logic_vector(BITS-1 downto 0);
variable int_idx: integer range 0 to COUNT-1;
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
ack_q<='0';
enabled <= (others => '1');
else
ack_q <= '0';
-- Wishbone write
if wb_stb_i='1' and wb_cyc_i='1' and wb_we_i='1' and ack_q='0' then
ack_q<='1';
if wb_adr_i(BITS+2)='1' then
-- Display access --
idx := wb_adr_i(BITS+1 downto 2);
int_idx := conv_integer(idx);
segs(int_idx) <= wb_dat_i(segvaltype'RANGE);
else
case wb_adr_i(2) is
when '0' =>
enabled <= wb_dat_i(enabled'RANGE);
brightctl <= unsigned(wb_dat_i(16+brightctl'HIGH downto 16));
when '1' =>
extra_q <= wb_dat_i(extra_q'RANGE);
when others =>
null;
end case;
end if;
end if;
end if;
end if;
end process;
-- REad
process(wb_adr_i,enabled,brightctl,extra_q)
variable idx: std_logic_vector(BITS-1 downto 0);
variable int_idx: integer range 0 to COUNT-1;
begin
wb_dat_o <= (others => DontCareValue);
if wb_adr_i(BITS+2)='1' then
-- Display access --
idx := wb_adr_i(BITS+1 downto 2);
int_idx := conv_integer(idx);
wb_dat_o(segvaltype'RANGE)<=segs(int_idx);
else
case wb_adr_i(2) is
when '0' =>
wb_dat_o(enabled'RANGE) <= enabled;
wb_dat_o(16+brightctl'HIGH downto 16) <= std_logic_vector(brightctl);
when '1' =>
wb_dat_o(extra_q'RANGE) <= extra_q;
when others =>
null;
end case;
end if;
end process;
end behave;
|
mit
|
chcbaram/FPGA
|
zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Benchy_Sump_LogicAnalyzer/Libraries/Wishbone_Peripherals/MISC_zpuino_wb_SevenSeg.vhd
|
13
|
7180
|
--
-- 7 segment driver for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity MISC_zpuino_wb_SevenSeg is
generic (
BITS: integer := 2;
EXTRASIZE: integer := 32;
FREQ_PER_DISPLAY: integer := 120;
MHZ: integer := 96;
INVERT: boolean := true
);
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0);
segdata: out std_logic_vector(6 downto 0);
dot: out std_logic;
extra: out std_logic_vector(EXTRASIZE-1 downto 0);
enable: out std_logic_vector((2**BITS)-1 downto 0)
);
end entity MISC_zpuino_wb_SevenSeg;
architecture behave of MISC_zpuino_wb_SevenSeg is
-- Timer
constant COUNT: integer := 2**BITS;
constant DELAY: integer := (MHZ*1000000 / (FREQ_PER_DISPLAY*COUNT*16)) - 1; -- 16 is for brightness control
signal counter: integer range 0 to DELAY;
signal enabled: std_logic_vector(COUNT-1 downto 0) := (others => '0');
subtype segvaltype is std_logic_vector(7 downto 0);
type segstype is array(COUNT-1 downto 0) of segvaltype;
signal segs: segstype;
signal current_display: integer range 0 to COUNT-1; -- same as enashift
signal ack_q: std_logic;
signal extra_q: std_logic_vector(EXTRASIZE-1 downto 0);
signal brightctl: unsigned(3 downto 0);
signal brightcount: unsigned(3 downto 0);
signal pwm: std_logic;
signal invsig: std_logic;
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
-- Finish unpacking Wishbone signals.
invsig <= '1' when INVERT=true else '0';
enloop: for i in 0 to COUNT-1 generate
enable(i) <= (enabled(i) and pwm) xor invsig when current_display=i else invsig;
end generate;
pwm <= '1' when brightcount >= brightctl else '0';
outdata: for i in 0 to 6 generate
segdata(i) <= segs(current_display)(i) xor invsig;
end generate;
dot <= segs(current_display)(7) xor invsig;
wb_ack_o <= ack_q;
wb_inta_o <= '0';
extra <= extra_q when current_display=0 and pwm='1' else (others => '0');
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
counter <= DELAY;
current_display<=0;
brightcount <= "1111";
else
if counter=0 then
counter <= DELAY;
if brightcount="0000" then
brightcount <= "1111";
if current_display=0 then
current_display <= COUNT-1;
else
current_display <= current_display - 1;
end if;
else
brightcount <= brightcount - 1;
end if;
else
counter <= counter - 1;
end if;
end if;
end if;
end process;
process(wb_clk_i)
variable idx: std_logic_vector(BITS-1 downto 0);
variable int_idx: integer range 0 to COUNT-1;
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
ack_q<='0';
enabled <= (others => '1');
else
ack_q <= '0';
-- Wishbone write
if wb_stb_i='1' and wb_cyc_i='1' and wb_we_i='1' and ack_q='0' then
ack_q<='1';
if wb_adr_i(BITS+2)='1' then
-- Display access --
idx := wb_adr_i(BITS+1 downto 2);
int_idx := conv_integer(idx);
segs(int_idx) <= wb_dat_i(segvaltype'RANGE);
else
case wb_adr_i(2) is
when '0' =>
enabled <= wb_dat_i(enabled'RANGE);
brightctl <= unsigned(wb_dat_i(16+brightctl'HIGH downto 16));
when '1' =>
extra_q <= wb_dat_i(extra_q'RANGE);
when others =>
null;
end case;
end if;
end if;
end if;
end if;
end process;
-- REad
process(wb_adr_i,enabled,brightctl,extra_q)
variable idx: std_logic_vector(BITS-1 downto 0);
variable int_idx: integer range 0 to COUNT-1;
begin
wb_dat_o <= (others => DontCareValue);
if wb_adr_i(BITS+2)='1' then
-- Display access --
idx := wb_adr_i(BITS+1 downto 2);
int_idx := conv_integer(idx);
wb_dat_o(segvaltype'RANGE)<=segs(int_idx);
else
case wb_adr_i(2) is
when '0' =>
wb_dat_o(enabled'RANGE) <= enabled;
wb_dat_o(16+brightctl'HIGH downto 16) <= std_logic_vector(brightctl);
when '1' =>
wb_dat_o(extra_q'RANGE) <= extra_q;
when others =>
null;
end case;
end if;
end process;
end behave;
|
mit
|
Oblomov/pocl
|
examples/accel/rtl/vhdl/ffaccel_globals_pkg.vhdl
|
2
|
627
|
library work;
use work.ffaccel_imem_mau.all;
package ffaccel_globals is
-- address width of the instruction memory
constant IMEMADDRWIDTH : positive := 12;
-- width of the instruction memory in MAUs
constant IMEMWIDTHINMAUS : positive := 1;
-- width of instruction fetch block.
constant IMEMDATAWIDTH : positive := IMEMWIDTHINMAUS*IMEMMAUWIDTH;
-- clock period
constant PERIOD : time := 10 ns;
-- number of busses.
constant BUSTRACE_WIDTH : positive := 64;
-- number of cores
constant CORECOUNT : positive := 1;
-- instruction width
constant INSTRUCTIONWIDTH : positive := 43;
end ffaccel_globals;
|
mit
|
chcbaram/FPGA
|
zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Benchy_Sump_LogicAnalyzer_JTAG/Libraries/ZPUino_1/zpuino_top_icache.vhd
|
13
|
15630
|
--
-- Top module for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
use board.zpuino_config.all;
use board.wishbonepkg.all;
entity zpuino_top_icache is
port (
clk: in std_logic;
rst: in std_logic;
-- Connection to board IO module
slot_cyc: out slot_std_logic_type;
slot_we: out slot_std_logic_type;
slot_stb: out slot_std_logic_type;
slot_read: in slot_cpuword_type;
slot_write: out slot_cpuword_type;
slot_address: out slot_address_type;
slot_ack: in slot_std_logic_type;
slot_interrupt: in slot_std_logic_type;
dbg_reset: out std_logic;
memory_enable: out std_logic;
-- Memory accesses (for DMA)
-- This is a master interface
m_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
m_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
m_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
m_wb_we_i: in std_logic;
m_wb_cyc_i: in std_logic;
m_wb_stb_i: in std_logic;
m_wb_ack_o: out std_logic;
m_wb_stall_o: out std_logic;
-- Memory connection
ram_wb_ack_i: in std_logic;
ram_wb_stall_i: in std_logic;
ram_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
ram_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
ram_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
ram_wb_cyc_o: out std_logic;
ram_wb_stb_o: out std_logic;
ram_wb_sel_o: out std_logic_vector(3 downto 0);
ram_wb_we_o: out std_logic;
rom_wb_ack_i: in std_logic;
rom_wb_stall_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stb_o: out std_logic;
jtag_data_chain_out: out std_logic_vector(98 downto 0);
jtag_ctrl_chain_in: in std_logic_vector(11 downto 0)
);
end entity zpuino_top_icache;
architecture behave of zpuino_top_icache is
component zpuino_stack is
port (
stack_clk: in std_logic;
stack_a_read: out std_logic_vector(wordSize-1 downto 0);
stack_b_read: out std_logic_vector(wordSize-1 downto 0);
stack_a_write: in std_logic_vector(wordSize-1 downto 0);
stack_b_write: in std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: in std_logic_vector(3 downto 0);
stack_a_enable: in std_logic;
stack_b_writeenable: in std_logic_vector(3 downto 0);
stack_b_enable: in std_logic;
stack_a_addr: in std_logic_vector(stackSize_bits-1 downto 2);
stack_b_addr: in std_logic_vector(stackSize_bits-1 downto 2)
);
end component zpuino_stack;
component wbarb2_1 is
generic (
ADDRESS_HIGH: integer := maxIObit;
ADDRESS_LOW: integer := maxIObit
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master 0 signals
m0_wb_dat_o: out std_logic_vector(31 downto 0);
m0_wb_dat_i: in std_logic_vector(31 downto 0);
m0_wb_adr_i: in std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
m0_wb_sel_i: in std_logic_vector(3 downto 0);
m0_wb_cti_i: in std_logic_vector(2 downto 0);
m0_wb_we_i: in std_logic;
m0_wb_cyc_i: in std_logic;
m0_wb_stb_i: in std_logic;
m0_wb_ack_o: out std_logic;
m0_wb_stall_o: out std_logic;
-- Master 1 signals
m1_wb_dat_o: out std_logic_vector(31 downto 0);
m1_wb_dat_i: in std_logic_vector(31 downto 0);
m1_wb_adr_i: in std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
m1_wb_sel_i: in std_logic_vector(3 downto 0);
m1_wb_cti_i: in std_logic_vector(2 downto 0);
m1_wb_we_i: in std_logic;
m1_wb_cyc_i: in std_logic;
m1_wb_stb_i: in std_logic;
m1_wb_ack_o: out std_logic;
m1_wb_stall_o: out std_logic;
-- Slave signals
s0_wb_dat_i: in std_logic_vector(31 downto 0);
s0_wb_dat_o: out std_logic_vector(31 downto 0);
s0_wb_adr_o: out std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
s0_wb_sel_o: out std_logic_vector(3 downto 0);
s0_wb_cti_o: out std_logic_vector(2 downto 0);
s0_wb_we_o: out std_logic;
s0_wb_cyc_o: out std_logic;
s0_wb_stb_o: out std_logic;
s0_wb_ack_i: in std_logic;
s0_wb_stall_i: in std_logic
);
end component;
component zpuino_debug_core is
port (
clk: in std_logic;
rst: in std_logic;
dbg_in: in zpu_dbg_out_type;
dbg_out: out zpu_dbg_in_type;
dbg_reset: out std_logic;
jtag_data_chain_out: out std_logic_vector(98 downto 0);
jtag_ctrl_chain_in: in std_logic_vector(11 downto 0)
);
end component;
component wbmux2 is
generic (
select_line: integer;
address_high: integer:=31;
address_low: integer:=2
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master
m_wb_dat_o: out std_logic_vector(31 downto 0);
m_wb_dat_i: in std_logic_vector(31 downto 0);
m_wb_adr_i: in std_logic_vector(address_high downto address_low);
m_wb_sel_i: in std_logic_vector(3 downto 0);
m_wb_cti_i: in std_logic_vector(2 downto 0);
m_wb_we_i: in std_logic;
m_wb_cyc_i: in std_logic;
m_wb_stb_i: in std_logic;
m_wb_ack_o: out std_logic;
-- Slave 0 signals
s0_wb_dat_i: in std_logic_vector(31 downto 0);
s0_wb_dat_o: out std_logic_vector(31 downto 0);
s0_wb_adr_o: out std_logic_vector(address_high downto address_low);
s0_wb_sel_o: out std_logic_vector(3 downto 0);
s0_wb_cti_o: out std_logic_vector(2 downto 0);
s0_wb_we_o: out std_logic;
s0_wb_cyc_o: out std_logic;
s0_wb_stb_o: out std_logic;
s0_wb_ack_i: in std_logic;
-- Slave 1 signals
s1_wb_dat_i: in std_logic_vector(31 downto 0);
s1_wb_dat_o: out std_logic_vector(31 downto 0);
s1_wb_adr_o: out std_logic_vector(address_high downto address_low);
s1_wb_sel_o: out std_logic_vector(3 downto 0);
s1_wb_cti_o: out std_logic_vector(2 downto 0);
s1_wb_we_o: out std_logic;
s1_wb_cyc_o: out std_logic;
s1_wb_stb_o: out std_logic;
s1_wb_ack_i: in std_logic
);
end component wbmux2;
signal io_read: std_logic_vector(wordSize-1 downto 0);
signal io_write: std_logic_vector(wordSize-1 downto 0);
signal io_address: std_logic_vector(maxAddrBitIncIO downto 0);
signal io_stb: std_logic;
signal io_cyc: std_logic;
signal io_we: std_logic;
signal io_ack: std_logic;
signal wb_read: std_logic_vector(wordSize-1 downto 0);
signal wb_write: std_logic_vector(wordSize-1 downto 0);
signal wb_address: std_logic_vector(maxAddrBitIncIO downto 0);
signal wb_stb: std_logic;
signal wb_cyc: std_logic;
signal wb_sel: std_logic_vector(3 downto 0);
signal wb_we: std_logic;
signal wb_ack: std_logic;
signal interrupt: std_logic;
signal poppc_inst: std_logic;
signal dbg_pc: std_logic_vector(maxAddrBit downto 0);
signal dbg_opcode: std_logic_vector(7 downto 0);
signal dbg_opcode_in: std_logic_vector(7 downto 0);
signal dbg_sp: std_logic_vector(10 downto 2);
signal dbg_brk: std_logic;
signal dbg_stacka: std_logic_vector(wordSize-1 downto 0);
signal dbg_stackb: std_logic_vector(wordSize-1 downto 0);
signal dbg_step: std_logic := '0';
signal dbg_freeze: std_logic;
signal dbg_flush: std_logic;
signal dbg_valid: std_logic;
signal dbg_ready: std_logic;
signal dbg_inject: std_logic;
signal dbg_injectmode: std_logic;
signal dbg_idim: std_logic;
signal stack_a_addr,stack_b_addr: std_logic_vector(stackSize_bits-1 downto 2);
signal stack_a_writeenable, stack_b_writeenable: std_logic_vector(3 downto 0);
signal stack_a_enable,stack_b_enable: std_logic;
signal stack_a_write,stack_b_write: std_logic_vector(31 downto 0);
signal stack_a_read,stack_b_read: std_logic_vector(31 downto 0);
signal stack_clk: std_logic;
signal cache_flush: std_logic;
--signal memory_enable: std_logic;
signal cpu_ram_wb_clk_i: std_logic;
signal cpu_ram_wb_rst_i: std_logic;
signal cpu_ram_wb_ack_o: std_logic;
signal cpu_ram_wb_stall_o: std_logic;
signal cpu_ram_wb_dat_i: std_logic_vector(wordSize-1 downto 0);
signal cpu_ram_wb_dat_o: std_logic_vector(wordSize-1 downto 0);
signal cpu_ram_wb_adr_i: std_logic_vector(maxAddrBitIncIO downto 0);
signal cpu_ram_wb_cyc_i: std_logic;
signal cpu_ram_wb_stb_i: std_logic;
signal cpu_ram_wb_sel_i: std_logic_vector(3 downto 0);
signal cpu_ram_wb_we_i: std_logic;
signal dbg_to_zpu: zpu_dbg_in_type;
signal dbg_from_zpu: zpu_dbg_out_type;
begin
core: zpu_core_extreme_icache
port map (
wb_clk_i => clk,
wb_rst_i => rst,
wb_ack_i => wb_ack,
wb_dat_i => wb_read,
wb_dat_o => wb_write,
wb_adr_o => wb_address,
wb_cyc_o => wb_cyc,
wb_stb_o => wb_stb,
wb_sel_o => wb_sel,
wb_we_o => wb_we,
wb_inta_i => interrupt,
poppc_inst => poppc_inst,
break => open,
cache_flush => cache_flush,
stack_clk => stack_clk,
stack_a_read => stack_a_read,
stack_b_read => stack_b_read,
stack_a_write => stack_a_write,
stack_b_write => stack_b_write,
stack_a_writeenable => stack_a_writeenable,
stack_b_writeenable => stack_b_writeenable,
stack_a_enable => stack_a_enable,
stack_b_enable => stack_b_enable,
stack_a_addr => stack_a_addr,
stack_b_addr => stack_b_addr,
rom_wb_ack_i => rom_wb_ack_i,
rom_wb_dat_i => rom_wb_dat_i,
rom_wb_adr_o => rom_wb_adr_o(maxAddrBit downto 0),
rom_wb_cyc_o => rom_wb_cyc_o,
rom_wb_stb_o => rom_wb_stb_o,
rom_wb_cti_o => rom_wb_cti_o,
rom_wb_stall_i => rom_wb_stall_i,
dbg_in => dbg_to_zpu,
dbg_out => dbg_from_zpu
);
stack: zpuino_stack
port map (
stack_clk => stack_clk,
stack_a_read => stack_a_read,
stack_b_read => stack_b_read,
stack_a_write => stack_a_write,
stack_b_write => stack_b_write,
stack_a_writeenable => stack_a_writeenable,
stack_b_writeenable => stack_b_writeenable,
stack_a_enable => stack_a_enable,
stack_b_enable => stack_b_enable,
stack_a_addr => stack_a_addr,
stack_b_addr => stack_b_addr
);
dbg: zpuino_debug_core
port map (
clk => clk,
rst => rst,
dbg_out => dbg_to_zpu,
dbg_in => dbg_from_zpu,
dbg_reset => dbg_reset,
jtag_data_chain_out => jtag_data_chain_out,
jtag_ctrl_chain_in => jtag_ctrl_chain_in
);
io: zpuino_io
port map (
wb_clk_i => clk,
wb_rst_i => rst,
wb_dat_o => io_read,
wb_dat_i => io_write,
wb_adr_i => io_address,
wb_cyc_i => io_cyc,
wb_stb_i => io_stb,
wb_ack_o => io_ack,
wb_we_i => io_we,
wb_inta_o => interrupt,
intready => poppc_inst,
cache_flush => cache_flush,
memory_enable => memory_enable,
slot_cyc => slot_cyc,
slot_we => slot_we,
slot_stb => slot_stb,
slot_read => slot_read,
slot_write => slot_write,
slot_address => slot_address,
slot_ack => slot_ack,
slot_interrupt=> slot_interrupt
);
iomemmux: wbmux2
generic map (
select_line => maxAddrBitIncIO,
address_high =>maxAddrBitIncIO,
address_low=>0
)
port map (
wb_clk_i => clk,
wb_rst_i => rst,
-- Master
m_wb_dat_o => wb_read,
m_wb_dat_i => wb_write,
m_wb_adr_i => wb_address,
m_wb_sel_i => wb_sel,
m_wb_cti_i => CTI_CYCLE_CLASSIC,--wb_cti,
m_wb_we_i => wb_we,
m_wb_cyc_i => wb_cyc,
m_wb_stb_i => wb_stb,
m_wb_ack_o => wb_ack,
-- Slave 0 signals
s0_wb_dat_i => cpu_ram_wb_dat_o,
s0_wb_dat_o => cpu_ram_wb_dat_i,
s0_wb_adr_o => cpu_ram_wb_adr_i,
s0_wb_sel_o => cpu_ram_wb_sel_i,
s0_wb_cti_o => open,--cpu_ram_wb_sel_i,
s0_wb_we_o => cpu_ram_wb_we_i,
s0_wb_cyc_o => cpu_ram_wb_cyc_i,
s0_wb_stb_o => cpu_ram_wb_stb_i,
s0_wb_ack_i => cpu_ram_wb_ack_o,
-- Slave 1 signals
s1_wb_dat_i => io_read,
s1_wb_dat_o => io_write,
s1_wb_adr_o => io_address,
s1_wb_sel_o => open,
s1_wb_cti_o => open,
s1_wb_we_o => io_we,
s1_wb_cyc_o => io_cyc,
s1_wb_stb_o => io_stb,
s1_wb_ack_i => io_ack
);
memarb: wbarb2_1
generic map (
ADDRESS_HIGH => maxAddrBit,
ADDRESS_LOW => 0
)
port map (
wb_clk_i => clk,
wb_rst_i => rst,
-- Master 0 signals (CPU)
m0_wb_dat_o => cpu_ram_wb_dat_o,
m0_wb_dat_i => cpu_ram_wb_dat_i,
m0_wb_adr_i => cpu_ram_wb_adr_i(maxAddrBit downto 0),
m0_wb_sel_i => cpu_ram_wb_sel_i,
m0_wb_cti_i => CTI_CYCLE_CLASSIC,
m0_wb_we_i => cpu_ram_wb_we_i,
m0_wb_cyc_i => cpu_ram_wb_cyc_i,
m0_wb_stb_i => cpu_ram_wb_stb_i,
m0_wb_ack_o => cpu_ram_wb_ack_o,
m0_wb_stall_o => cpu_ram_wb_stall_o,
-- Master 1 signals
m1_wb_dat_o => m_wb_dat_o,
m1_wb_dat_i => m_wb_dat_i,
m1_wb_adr_i => m_wb_adr_i(maxAddrBit downto 0),
m1_wb_sel_i => (others => '1'),
m1_wb_cti_i => CTI_CYCLE_CLASSIC,
m1_wb_we_i => m_wb_we_i,
m1_wb_cyc_i => m_wb_cyc_i,
m1_wb_stb_i => m_wb_stb_i,
m1_wb_ack_o => m_wb_ack_o,
m1_wb_stall_o => m_wb_stall_o,
-- Slave signals
s0_wb_dat_i => ram_wb_dat_i,
s0_wb_dat_o => ram_wb_dat_o,
s0_wb_adr_o => ram_wb_adr_o(maxAddrBit downto 0),
s0_wb_sel_o => ram_wb_sel_o,
s0_wb_cti_o => open,
s0_wb_we_o => ram_wb_we_o,
s0_wb_cyc_o => ram_wb_cyc_o,
s0_wb_stb_o => ram_wb_stb_o,
s0_wb_ack_i => ram_wb_ack_i,
s0_wb_stall_i => ram_wb_stall_i
);
end behave;
|
mit
|
chcbaram/FPGA
|
zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/Libraries/ZPUino_1/zpuino_top_icache.vhd
|
13
|
15630
|
--
-- Top module for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
use board.zpuino_config.all;
use board.wishbonepkg.all;
entity zpuino_top_icache is
port (
clk: in std_logic;
rst: in std_logic;
-- Connection to board IO module
slot_cyc: out slot_std_logic_type;
slot_we: out slot_std_logic_type;
slot_stb: out slot_std_logic_type;
slot_read: in slot_cpuword_type;
slot_write: out slot_cpuword_type;
slot_address: out slot_address_type;
slot_ack: in slot_std_logic_type;
slot_interrupt: in slot_std_logic_type;
dbg_reset: out std_logic;
memory_enable: out std_logic;
-- Memory accesses (for DMA)
-- This is a master interface
m_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
m_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
m_wb_adr_i: in std_logic_vector(maxAddrBitIncIO downto 0);
m_wb_we_i: in std_logic;
m_wb_cyc_i: in std_logic;
m_wb_stb_i: in std_logic;
m_wb_ack_o: out std_logic;
m_wb_stall_o: out std_logic;
-- Memory connection
ram_wb_ack_i: in std_logic;
ram_wb_stall_i: in std_logic;
ram_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
ram_wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
ram_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
ram_wb_cyc_o: out std_logic;
ram_wb_stb_o: out std_logic;
ram_wb_sel_o: out std_logic_vector(3 downto 0);
ram_wb_we_o: out std_logic;
rom_wb_ack_i: in std_logic;
rom_wb_stall_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stb_o: out std_logic;
jtag_data_chain_out: out std_logic_vector(98 downto 0);
jtag_ctrl_chain_in: in std_logic_vector(11 downto 0)
);
end entity zpuino_top_icache;
architecture behave of zpuino_top_icache is
component zpuino_stack is
port (
stack_clk: in std_logic;
stack_a_read: out std_logic_vector(wordSize-1 downto 0);
stack_b_read: out std_logic_vector(wordSize-1 downto 0);
stack_a_write: in std_logic_vector(wordSize-1 downto 0);
stack_b_write: in std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: in std_logic_vector(3 downto 0);
stack_a_enable: in std_logic;
stack_b_writeenable: in std_logic_vector(3 downto 0);
stack_b_enable: in std_logic;
stack_a_addr: in std_logic_vector(stackSize_bits-1 downto 2);
stack_b_addr: in std_logic_vector(stackSize_bits-1 downto 2)
);
end component zpuino_stack;
component wbarb2_1 is
generic (
ADDRESS_HIGH: integer := maxIObit;
ADDRESS_LOW: integer := maxIObit
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master 0 signals
m0_wb_dat_o: out std_logic_vector(31 downto 0);
m0_wb_dat_i: in std_logic_vector(31 downto 0);
m0_wb_adr_i: in std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
m0_wb_sel_i: in std_logic_vector(3 downto 0);
m0_wb_cti_i: in std_logic_vector(2 downto 0);
m0_wb_we_i: in std_logic;
m0_wb_cyc_i: in std_logic;
m0_wb_stb_i: in std_logic;
m0_wb_ack_o: out std_logic;
m0_wb_stall_o: out std_logic;
-- Master 1 signals
m1_wb_dat_o: out std_logic_vector(31 downto 0);
m1_wb_dat_i: in std_logic_vector(31 downto 0);
m1_wb_adr_i: in std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
m1_wb_sel_i: in std_logic_vector(3 downto 0);
m1_wb_cti_i: in std_logic_vector(2 downto 0);
m1_wb_we_i: in std_logic;
m1_wb_cyc_i: in std_logic;
m1_wb_stb_i: in std_logic;
m1_wb_ack_o: out std_logic;
m1_wb_stall_o: out std_logic;
-- Slave signals
s0_wb_dat_i: in std_logic_vector(31 downto 0);
s0_wb_dat_o: out std_logic_vector(31 downto 0);
s0_wb_adr_o: out std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
s0_wb_sel_o: out std_logic_vector(3 downto 0);
s0_wb_cti_o: out std_logic_vector(2 downto 0);
s0_wb_we_o: out std_logic;
s0_wb_cyc_o: out std_logic;
s0_wb_stb_o: out std_logic;
s0_wb_ack_i: in std_logic;
s0_wb_stall_i: in std_logic
);
end component;
component zpuino_debug_core is
port (
clk: in std_logic;
rst: in std_logic;
dbg_in: in zpu_dbg_out_type;
dbg_out: out zpu_dbg_in_type;
dbg_reset: out std_logic;
jtag_data_chain_out: out std_logic_vector(98 downto 0);
jtag_ctrl_chain_in: in std_logic_vector(11 downto 0)
);
end component;
component wbmux2 is
generic (
select_line: integer;
address_high: integer:=31;
address_low: integer:=2
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master
m_wb_dat_o: out std_logic_vector(31 downto 0);
m_wb_dat_i: in std_logic_vector(31 downto 0);
m_wb_adr_i: in std_logic_vector(address_high downto address_low);
m_wb_sel_i: in std_logic_vector(3 downto 0);
m_wb_cti_i: in std_logic_vector(2 downto 0);
m_wb_we_i: in std_logic;
m_wb_cyc_i: in std_logic;
m_wb_stb_i: in std_logic;
m_wb_ack_o: out std_logic;
-- Slave 0 signals
s0_wb_dat_i: in std_logic_vector(31 downto 0);
s0_wb_dat_o: out std_logic_vector(31 downto 0);
s0_wb_adr_o: out std_logic_vector(address_high downto address_low);
s0_wb_sel_o: out std_logic_vector(3 downto 0);
s0_wb_cti_o: out std_logic_vector(2 downto 0);
s0_wb_we_o: out std_logic;
s0_wb_cyc_o: out std_logic;
s0_wb_stb_o: out std_logic;
s0_wb_ack_i: in std_logic;
-- Slave 1 signals
s1_wb_dat_i: in std_logic_vector(31 downto 0);
s1_wb_dat_o: out std_logic_vector(31 downto 0);
s1_wb_adr_o: out std_logic_vector(address_high downto address_low);
s1_wb_sel_o: out std_logic_vector(3 downto 0);
s1_wb_cti_o: out std_logic_vector(2 downto 0);
s1_wb_we_o: out std_logic;
s1_wb_cyc_o: out std_logic;
s1_wb_stb_o: out std_logic;
s1_wb_ack_i: in std_logic
);
end component wbmux2;
signal io_read: std_logic_vector(wordSize-1 downto 0);
signal io_write: std_logic_vector(wordSize-1 downto 0);
signal io_address: std_logic_vector(maxAddrBitIncIO downto 0);
signal io_stb: std_logic;
signal io_cyc: std_logic;
signal io_we: std_logic;
signal io_ack: std_logic;
signal wb_read: std_logic_vector(wordSize-1 downto 0);
signal wb_write: std_logic_vector(wordSize-1 downto 0);
signal wb_address: std_logic_vector(maxAddrBitIncIO downto 0);
signal wb_stb: std_logic;
signal wb_cyc: std_logic;
signal wb_sel: std_logic_vector(3 downto 0);
signal wb_we: std_logic;
signal wb_ack: std_logic;
signal interrupt: std_logic;
signal poppc_inst: std_logic;
signal dbg_pc: std_logic_vector(maxAddrBit downto 0);
signal dbg_opcode: std_logic_vector(7 downto 0);
signal dbg_opcode_in: std_logic_vector(7 downto 0);
signal dbg_sp: std_logic_vector(10 downto 2);
signal dbg_brk: std_logic;
signal dbg_stacka: std_logic_vector(wordSize-1 downto 0);
signal dbg_stackb: std_logic_vector(wordSize-1 downto 0);
signal dbg_step: std_logic := '0';
signal dbg_freeze: std_logic;
signal dbg_flush: std_logic;
signal dbg_valid: std_logic;
signal dbg_ready: std_logic;
signal dbg_inject: std_logic;
signal dbg_injectmode: std_logic;
signal dbg_idim: std_logic;
signal stack_a_addr,stack_b_addr: std_logic_vector(stackSize_bits-1 downto 2);
signal stack_a_writeenable, stack_b_writeenable: std_logic_vector(3 downto 0);
signal stack_a_enable,stack_b_enable: std_logic;
signal stack_a_write,stack_b_write: std_logic_vector(31 downto 0);
signal stack_a_read,stack_b_read: std_logic_vector(31 downto 0);
signal stack_clk: std_logic;
signal cache_flush: std_logic;
--signal memory_enable: std_logic;
signal cpu_ram_wb_clk_i: std_logic;
signal cpu_ram_wb_rst_i: std_logic;
signal cpu_ram_wb_ack_o: std_logic;
signal cpu_ram_wb_stall_o: std_logic;
signal cpu_ram_wb_dat_i: std_logic_vector(wordSize-1 downto 0);
signal cpu_ram_wb_dat_o: std_logic_vector(wordSize-1 downto 0);
signal cpu_ram_wb_adr_i: std_logic_vector(maxAddrBitIncIO downto 0);
signal cpu_ram_wb_cyc_i: std_logic;
signal cpu_ram_wb_stb_i: std_logic;
signal cpu_ram_wb_sel_i: std_logic_vector(3 downto 0);
signal cpu_ram_wb_we_i: std_logic;
signal dbg_to_zpu: zpu_dbg_in_type;
signal dbg_from_zpu: zpu_dbg_out_type;
begin
core: zpu_core_extreme_icache
port map (
wb_clk_i => clk,
wb_rst_i => rst,
wb_ack_i => wb_ack,
wb_dat_i => wb_read,
wb_dat_o => wb_write,
wb_adr_o => wb_address,
wb_cyc_o => wb_cyc,
wb_stb_o => wb_stb,
wb_sel_o => wb_sel,
wb_we_o => wb_we,
wb_inta_i => interrupt,
poppc_inst => poppc_inst,
break => open,
cache_flush => cache_flush,
stack_clk => stack_clk,
stack_a_read => stack_a_read,
stack_b_read => stack_b_read,
stack_a_write => stack_a_write,
stack_b_write => stack_b_write,
stack_a_writeenable => stack_a_writeenable,
stack_b_writeenable => stack_b_writeenable,
stack_a_enable => stack_a_enable,
stack_b_enable => stack_b_enable,
stack_a_addr => stack_a_addr,
stack_b_addr => stack_b_addr,
rom_wb_ack_i => rom_wb_ack_i,
rom_wb_dat_i => rom_wb_dat_i,
rom_wb_adr_o => rom_wb_adr_o(maxAddrBit downto 0),
rom_wb_cyc_o => rom_wb_cyc_o,
rom_wb_stb_o => rom_wb_stb_o,
rom_wb_cti_o => rom_wb_cti_o,
rom_wb_stall_i => rom_wb_stall_i,
dbg_in => dbg_to_zpu,
dbg_out => dbg_from_zpu
);
stack: zpuino_stack
port map (
stack_clk => stack_clk,
stack_a_read => stack_a_read,
stack_b_read => stack_b_read,
stack_a_write => stack_a_write,
stack_b_write => stack_b_write,
stack_a_writeenable => stack_a_writeenable,
stack_b_writeenable => stack_b_writeenable,
stack_a_enable => stack_a_enable,
stack_b_enable => stack_b_enable,
stack_a_addr => stack_a_addr,
stack_b_addr => stack_b_addr
);
dbg: zpuino_debug_core
port map (
clk => clk,
rst => rst,
dbg_out => dbg_to_zpu,
dbg_in => dbg_from_zpu,
dbg_reset => dbg_reset,
jtag_data_chain_out => jtag_data_chain_out,
jtag_ctrl_chain_in => jtag_ctrl_chain_in
);
io: zpuino_io
port map (
wb_clk_i => clk,
wb_rst_i => rst,
wb_dat_o => io_read,
wb_dat_i => io_write,
wb_adr_i => io_address,
wb_cyc_i => io_cyc,
wb_stb_i => io_stb,
wb_ack_o => io_ack,
wb_we_i => io_we,
wb_inta_o => interrupt,
intready => poppc_inst,
cache_flush => cache_flush,
memory_enable => memory_enable,
slot_cyc => slot_cyc,
slot_we => slot_we,
slot_stb => slot_stb,
slot_read => slot_read,
slot_write => slot_write,
slot_address => slot_address,
slot_ack => slot_ack,
slot_interrupt=> slot_interrupt
);
iomemmux: wbmux2
generic map (
select_line => maxAddrBitIncIO,
address_high =>maxAddrBitIncIO,
address_low=>0
)
port map (
wb_clk_i => clk,
wb_rst_i => rst,
-- Master
m_wb_dat_o => wb_read,
m_wb_dat_i => wb_write,
m_wb_adr_i => wb_address,
m_wb_sel_i => wb_sel,
m_wb_cti_i => CTI_CYCLE_CLASSIC,--wb_cti,
m_wb_we_i => wb_we,
m_wb_cyc_i => wb_cyc,
m_wb_stb_i => wb_stb,
m_wb_ack_o => wb_ack,
-- Slave 0 signals
s0_wb_dat_i => cpu_ram_wb_dat_o,
s0_wb_dat_o => cpu_ram_wb_dat_i,
s0_wb_adr_o => cpu_ram_wb_adr_i,
s0_wb_sel_o => cpu_ram_wb_sel_i,
s0_wb_cti_o => open,--cpu_ram_wb_sel_i,
s0_wb_we_o => cpu_ram_wb_we_i,
s0_wb_cyc_o => cpu_ram_wb_cyc_i,
s0_wb_stb_o => cpu_ram_wb_stb_i,
s0_wb_ack_i => cpu_ram_wb_ack_o,
-- Slave 1 signals
s1_wb_dat_i => io_read,
s1_wb_dat_o => io_write,
s1_wb_adr_o => io_address,
s1_wb_sel_o => open,
s1_wb_cti_o => open,
s1_wb_we_o => io_we,
s1_wb_cyc_o => io_cyc,
s1_wb_stb_o => io_stb,
s1_wb_ack_i => io_ack
);
memarb: wbarb2_1
generic map (
ADDRESS_HIGH => maxAddrBit,
ADDRESS_LOW => 0
)
port map (
wb_clk_i => clk,
wb_rst_i => rst,
-- Master 0 signals (CPU)
m0_wb_dat_o => cpu_ram_wb_dat_o,
m0_wb_dat_i => cpu_ram_wb_dat_i,
m0_wb_adr_i => cpu_ram_wb_adr_i(maxAddrBit downto 0),
m0_wb_sel_i => cpu_ram_wb_sel_i,
m0_wb_cti_i => CTI_CYCLE_CLASSIC,
m0_wb_we_i => cpu_ram_wb_we_i,
m0_wb_cyc_i => cpu_ram_wb_cyc_i,
m0_wb_stb_i => cpu_ram_wb_stb_i,
m0_wb_ack_o => cpu_ram_wb_ack_o,
m0_wb_stall_o => cpu_ram_wb_stall_o,
-- Master 1 signals
m1_wb_dat_o => m_wb_dat_o,
m1_wb_dat_i => m_wb_dat_i,
m1_wb_adr_i => m_wb_adr_i(maxAddrBit downto 0),
m1_wb_sel_i => (others => '1'),
m1_wb_cti_i => CTI_CYCLE_CLASSIC,
m1_wb_we_i => m_wb_we_i,
m1_wb_cyc_i => m_wb_cyc_i,
m1_wb_stb_i => m_wb_stb_i,
m1_wb_ack_o => m_wb_ack_o,
m1_wb_stall_o => m_wb_stall_o,
-- Slave signals
s0_wb_dat_i => ram_wb_dat_i,
s0_wb_dat_o => ram_wb_dat_o,
s0_wb_adr_o => ram_wb_adr_o(maxAddrBit downto 0),
s0_wb_sel_o => ram_wb_sel_o,
s0_wb_cti_o => open,
s0_wb_we_o => ram_wb_we_o,
s0_wb_cyc_o => ram_wb_cyc_o,
s0_wb_stb_o => ram_wb_stb_o,
s0_wb_ack_i => ram_wb_ack_i,
s0_wb_stall_i => ram_wb_stall_i
);
end behave;
|
mit
|
chcbaram/FPGA
|
zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Audio_YM2149_simple/Libraries/Benchy/demux.vhd
|
13
|
1810
|
----------------------------------------------------------------------------------
-- demux.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Demultiplexes 16 la_input channels into 32 output channels,
-- thus doubling the sampling rate for those channels.
--
-- This module barely does anything anymore, but is kept for historical reasons.
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity demux is
port(
la_input : in std_logic_vector (15 downto 0);
la_input180 : in std_logic_vector (15 downto 0);
clock : in std_logic;
output : out std_logic_vector (31 downto 0)
);
end demux;
architecture behavioral of demux is
begin
output(15 downto 0) <= la_input;
process (clock)
begin
if rising_edge(clock) then
output(31 downto 16) <= la_input180;
end if;
end process;
end behavioral;
|
mit
|
chcbaram/FPGA
|
zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/Libraries/Benchy/demux.vhd
|
13
|
1810
|
----------------------------------------------------------------------------------
-- demux.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Demultiplexes 16 la_input channels into 32 output channels,
-- thus doubling the sampling rate for those channels.
--
-- This module barely does anything anymore, but is kept for historical reasons.
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity demux is
port(
la_input : in std_logic_vector (15 downto 0);
la_input180 : in std_logic_vector (15 downto 0);
clock : in std_logic;
output : out std_logic_vector (31 downto 0)
);
end demux;
architecture behavioral of demux is
begin
output(15 downto 0) <= la_input;
process (clock)
begin
if rising_edge(clock) then
output(31 downto 16) <= la_input180;
end if;
end process;
end behavioral;
|
mit
|
chcbaram/FPGA
|
zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Benchy_Sump_LogicAnalyzer/Libraries/ZPUino_1/pad.vhd
|
14
|
3980
|
--
-- ZPUINO IO pads
--
-- Copyright 2011 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
package pad is
component iopad is
port(
I: in std_logic;
O: out std_logic;
T: in std_logic;
C: in std_logic;
PAD: inout std_logic
);
end component iopad;
component ipad is
port (
O: out std_logic;
C: in std_logic;
PAD: in std_logic
);
end component ipad;
component opad is
port (
I: in std_logic;
O: out std_logic;
PAD: out std_logic
);
end component opad;
component isync is
port (
I: in std_logic;
O: out std_logic;
C: in std_logic
);
end component isync;
end package pad;
--
-- Start
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity isync is
port (
I: in std_logic;
O: out std_logic;
C: in std_logic
);
end entity isync;
architecture behave of isync is
signal s: std_logic;
begin
-- latch: ILD
-- port map (
-- D => I,
-- Q => s,
-- G => C
-- );
ff1: FD
port map (
D => I,
Q => s,
C => C
);
ff2: FD
port map (
D => s,
Q => O,
C => C
);
end behave;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
use work.pad.all;
library unisim;
use unisim.vcomponents.all;
entity iopad is
port (
I: in std_logic;
O: out std_logic;
T: in std_logic;
C: in std_logic;
PAD: inout std_logic
);
end entity iopad;
architecture behave of iopad is
begin
sync: isync
port map (
I => PAD,
O => O,
C => C
);
-- Tristate generator
process(I,T)
begin
if T='1' then
PAD<='Z';
else
PAD<=I;
end if;
end process;
end behave;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
use work.pad.all;
library unisim;
use unisim.vcomponents.all;
entity ipad is
port (
O: out std_logic;
C: in std_logic;
PAD: in std_logic
);
end entity ipad;
architecture behave of ipad is
signal s: std_logic;
begin
sync: isync
port map (
I => PAD,
O => O,
C => C
);
end behave;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
use work.pad.all;
library unisim;
use unisim.vcomponents.all;
entity opad is
port (
I: in std_logic;
O: out std_logic;
PAD: out std_logic
);
end entity opad;
architecture behave of opad is
begin
obufi: OBUF
port map (
I => I,
O => PAD
);
O <= I;
end behave;
|
mit
|
chcbaram/FPGA
|
zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Audio_ModFile_simple/Libraries/Wishbone_Peripherals/MISC_zpuino_sa_splitter2.vhd
|
13
|
1093
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:01:17 11/27/2013
-- Design Name:
-- Module Name: MISC_zpuino_sa_splitter2 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity MISC_zpuino_sa_splitter2 is
Port ( in1 : in STD_LOGIC;
out1 : out STD_LOGIC;
out2 : out STD_LOGIC);
end MISC_zpuino_sa_splitter2;
architecture Behavioral of MISC_zpuino_sa_splitter2 is
begin
out1 <= in1;
out2 <= in1;
end Behavioral;
|
mit
|
chcbaram/FPGA
|
zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Audio_YM2149_simple/Libraries/ZPUino_1/Papilio_Default_Pinout.vhd
|
13
|
13239
|
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 14.3
-- \ \ Application :
-- / / Filename : xil_10080_19
-- /___/ /\ Timestamp : 02/08/2013 16:21:11
-- \ \ / \
-- \___\/\___\
--
--Command:
--Design Name:
-- The Papilio Default Pinout device defines the pins for a Papilio board that does not have a MegaWing attached to it.
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
library board;
use board.zpupkg.all;
use board.zpuinopkg.all;
use board.zpuino_config.all;
use board.zpu_config.all;
library zpuino;
use zpuino.pad.all;
use zpuino.papilio_pkg.all;
-- Unfortunately the Xilinx Schematic Editor does not support records, so we have to put all wishbone signals into one array.
-- This is a little cumbersome but is better then dealing with all the signals in the schematic editor.
-- This is what the original record base approach looked like:
--
-- type gpio_bus_in_type is record
-- gpio_i: std_logic_vector(48 downto 0);
-- gpio_spp_data: std_logic_vector(48 downto 0);
-- end record;
--
-- type gpio_bus_out_type is record
-- gpio_clk: std_logic;
-- gpio_o: std_logic_vector(48 downto 0);
-- gpio_t: std_logic_vector(48 downto 0);
-- gpio_spp_read: std_logic_vector(48 downto 0);
-- end record;
--
-- Turning them into an array looks like this:
--
-- gpio_bus_in : in std_logic_vector(97 downto 0);
--
-- gpio_bus_in(97 downto 49) <= gpio_i;
-- gpio_bus_in(48 downto 0) <= gpio_bus_in_record.gpio_spp_data;
--
-- gpio_bus_out : out std_logic_vector(146 downto 0);
--
-- gpio_o <= gpio_bus_out(146 downto 98);
-- gpio_t <= gpio_bus_out(97 downto 49);
-- gpio_bus_out_record.gpio_spp_read <= gpio_bus_out(48 downto 0);
entity Papilio_Default_Pinout is
port (
-- gpio_clk: in std_logic;
-- gpio_o: in std_logic_vector(48 downto 0);
-- gpio_t: in std_logic_vector(48 downto 0);
-- gpio_i: out std_logic_vector(48 downto 0);
--
-- gpio_spp_data: out std_logic_vector(48 downto 0);
-- gpio_spp_read: in std_logic_vector(48 downto 0);
gpio_bus_in : out std_logic_vector(97 downto 0);
gpio_bus_out : in std_logic_vector(147 downto 0);
WING_AH0 : inout std_logic;
WING_AH1 : inout std_logic;
WING_AH2 : inout std_logic;
WING_AH3 : inout std_logic;
WING_AH4 : inout std_logic;
WING_AH5 : inout std_logic;
WING_AH6 : inout std_logic;
WING_AH7 : inout std_logic;
WING_AL0 : inout std_logic;
WING_AL1 : inout std_logic;
WING_AL2 : inout std_logic;
WING_AL3 : inout std_logic;
WING_AL4 : inout std_logic;
WING_AL5 : inout std_logic;
WING_AL6 : inout std_logic;
WING_AL7 : inout std_logic;
WING_BH0 : inout std_logic;
WING_BH1 : inout std_logic;
WING_BH2 : inout std_logic;
WING_BH3 : inout std_logic;
WING_BH4 : inout std_logic;
WING_BH5 : inout std_logic;
WING_BH6 : inout std_logic;
WING_BH7 : inout std_logic;
WING_BL0 : inout std_logic;
WING_BL1 : inout std_logic;
WING_BL2 : inout std_logic;
WING_BL3 : inout std_logic;
WING_BL4 : inout std_logic;
WING_BL5 : inout std_logic;
WING_BL6 : inout std_logic;
WING_BL7 : inout std_logic;
WING_CH0 : inout std_logic;
WING_CH1 : inout std_logic;
WING_CH2 : inout std_logic;
WING_CH3 : inout std_logic;
WING_CH4 : inout std_logic;
WING_CH5 : inout std_logic;
WING_CH6 : inout std_logic;
WING_CH7 : inout std_logic;
WING_CL0 : inout std_logic;
WING_CL1 : inout std_logic;
WING_CL2 : inout std_logic;
WING_CL3 : inout std_logic;
WING_CL4 : inout std_logic;
WING_CL5 : inout std_logic;
WING_CL6 : inout std_logic;
WING_CL7 : inout std_logic
);
end Papilio_Default_Pinout;
architecture BEHAVIORAL of Papilio_Default_Pinout is
-- signal gpio_bus_out.gpio_o: std_logic_vector(zpuino_gpio_count-1 downto 0);
-- signal gpio_bus_out.gpio_t: std_logic_vector(zpuino_gpio_count-1 downto 0);
-- signal gpio_bus_in.gpio_i: std_logic_vector(zpuino_gpio_count-1 downto 0);
--
-- -- SPP signal is one more than GPIO count
-- signal gpio_bus_in.gpio_spp_data: std_logic_vector(zpuino_gpio_count-1 downto 0);
-- signal gpio_bus_out.gpio_spp_read: std_logic_vector(zpuino_gpio_count-1 downto 0);
--
-- constant spp_cap_in: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
-- "0" &
-- "1111111111111111" &
-- "1111111111111111" &
-- "1111111111111111";
-- constant spp_cap_out: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
-- "0" &
-- "1111111111111111" &
-- "1111111111111111" &
-- "1111111111111111";
-- signal gpio_bus_in_record : gpio_bus_in_type;
-- signal gpio_bus_out_record : gpio_bus_out_type;
signal gpio_o: std_logic_vector(48 downto 0);
signal gpio_t: std_logic_vector(48 downto 0);
signal gpio_i: std_logic_vector(48 downto 0);
signal gpio_spp_data: std_logic_vector(48 downto 0);
signal gpio_spp_read: std_logic_vector(48 downto 0);
signal gpio_clk: std_logic;
begin
--Unpack the signal array into a record so the modules code is easier to understand.
--gpio_bus_in(97 downto 49) <= gpio_spp_data;
--gpio_bus_in(48 downto 0) <= gpio_i;
gpio_clk <= gpio_bus_out(147);
gpio_o <= gpio_bus_out(146 downto 98);
gpio_t <= gpio_bus_out(97 downto 49);
gpio_spp_read <= gpio_bus_out(48 downto 0);
-- gpio_bus_in(97 downto 49) <= gpio_i;
-- gpio_bus_in(48 downto 0) <= gpio_bus_in_record.gpio_spp_data;
-- gpio_clk <= gpio_bus_out(147);
-- gpio_o <= gpio_bus_out(146 downto 98);
-- gpio_t <= gpio_bus_out(97 downto 49);
-- gpio_bus_out_record.gpio_spp_read <= gpio_bus_out(48 downto 0);
-- gpio_bus_in.gpio_inst: zpuino_gpio
-- generic map (
-- gpio_count => zpuino_gpio_count
-- )
-- port map (
-- gpio_bus_out.gpio_clk => gpio_bus_out.gpio_clk,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => wb_dat_o,
-- wb_dat_i => wb_dat_i,
-- wb_adr_i => wb_adr_i,
-- wb_we_i => wb_we_i,
-- wb_cyc_i => wb_cyc_i,
-- wb_stb_i => wb_stb_i,
-- wb_ack_o => wb_ack_o,
-- wb_inta_o => wb_inta_o,
--
-- spp_data => gpio_bus_in.gpio_spp_data,
-- spp_read => gpio_bus_out.gpio_spp_read,
--
-- gpio_bus_in.gpio_i => gpio_bus_in.gpio_i,
-- gpio_bus_out.gpio_t => gpio_bus_out.gpio_t,
-- gpio_bus_out.gpio_o => gpio_bus_out.gpio_o,
-- spp_cap_in => spp_cap_in,
-- spp_cap_out => spp_cap_out
-- );
pin00: IOPAD port map(I => gpio_o(0), O => gpio_bus_in(0), T => gpio_t(0), C => gpio_clk,PAD => WING_AL0 );
pin01: IOPAD port map(I => gpio_o(1), O => gpio_bus_in(1), T => gpio_t(1), C => gpio_clk,PAD => WING_AL1 );
pin02: IOPAD port map(I => gpio_o(2), O => gpio_bus_in(2), T => gpio_t(2), C => gpio_clk,PAD => WING_AL2 );
pin03: IOPAD port map(I => gpio_o(3), O => gpio_bus_in(3), T => gpio_t(3), C => gpio_clk,PAD => WING_AL3 );
pin04: IOPAD port map(I => gpio_o(4), O => gpio_bus_in(4), T => gpio_t(4), C => gpio_clk,PAD => WING_AL4 );
pin05: IOPAD port map(I => gpio_o(5), O => gpio_bus_in(5), T => gpio_t(5), C => gpio_clk,PAD => WING_AL5 );
pin06: IOPAD port map(I => gpio_o(6), O => gpio_bus_in(6), T => gpio_t(6), C => gpio_clk,PAD => WING_AL6 );
pin07: IOPAD port map(I => gpio_o(7), O => gpio_bus_in(7), T => gpio_t(7), C => gpio_clk,PAD => WING_AL7 );
pin08: IOPAD port map(I => gpio_o(8), O => gpio_bus_in(8), T => gpio_t(8), C => gpio_clk,PAD => WING_AH0 );
pin09: IOPAD port map(I => gpio_o(9), O => gpio_bus_in(9), T => gpio_t(9), C => gpio_clk,PAD => WING_AH1 );
pin10: IOPAD port map(I => gpio_o(10),O => gpio_bus_in(10),T => gpio_t(10),C => gpio_clk,PAD => WING_AH2 );
pin11: IOPAD port map(I => gpio_o(11),O => gpio_bus_in(11),T => gpio_t(11),C => gpio_clk,PAD => WING_AH3 );
pin12: IOPAD port map(I => gpio_o(12),O => gpio_bus_in(12),T => gpio_t(12),C => gpio_clk,PAD => WING_AH4 );
pin13: IOPAD port map(I => gpio_o(13),O => gpio_bus_in(13),T => gpio_t(13),C => gpio_clk,PAD => WING_AH5 );
pin14: IOPAD port map(I => gpio_o(14),O => gpio_bus_in(14),T => gpio_t(14),C => gpio_clk,PAD => WING_AH6 );
pin15: IOPAD port map(I => gpio_o(15),O => gpio_bus_in(15),T => gpio_t(15),C => gpio_clk,PAD => WING_AH7 );
pin16: IOPAD port map(I => gpio_o(16),O => gpio_bus_in(16),T => gpio_t(16),C => gpio_clk,PAD => WING_BL0 );
pin17: IOPAD port map(I => gpio_o(17),O => gpio_bus_in(17),T => gpio_t(17),C => gpio_clk,PAD => WING_BL1 );
pin18: IOPAD port map(I => gpio_o(18),O => gpio_bus_in(18),T => gpio_t(18),C => gpio_clk,PAD => WING_BL2 );
pin19: IOPAD port map(I => gpio_o(19),O => gpio_bus_in(19),T => gpio_t(19),C => gpio_clk,PAD => WING_BL3 );
pin20: IOPAD port map(I => gpio_o(20),O => gpio_bus_in(20),T => gpio_t(20),C => gpio_clk,PAD => WING_BL4 );
pin21: IOPAD port map(I => gpio_o(21),O => gpio_bus_in(21),T => gpio_t(21),C => gpio_clk,PAD => WING_BL5 );
pin22: IOPAD port map(I => gpio_o(22),O => gpio_bus_in(22),T => gpio_t(22),C => gpio_clk,PAD => WING_BL6 );
pin23: IOPAD port map(I => gpio_o(23),O => gpio_bus_in(23),T => gpio_t(23),C => gpio_clk,PAD => WING_BL7 );
pin24: IOPAD port map(I => gpio_o(24),O => gpio_bus_in(24),T => gpio_t(24),C => gpio_clk,PAD => WING_BH0 );
pin25: IOPAD port map(I => gpio_o(25),O => gpio_bus_in(25),T => gpio_t(25),C => gpio_clk,PAD => WING_BH1 );
pin26: IOPAD port map(I => gpio_o(26),O => gpio_bus_in(26),T => gpio_t(26),C => gpio_clk,PAD => WING_BH2 );
pin27: IOPAD port map(I => gpio_o(27),O => gpio_bus_in(27),T => gpio_t(27),C => gpio_clk,PAD => WING_BH3 );
pin28: IOPAD port map(I => gpio_o(28),O => gpio_bus_in(28),T => gpio_t(28),C => gpio_clk,PAD => WING_BH4 );
pin29: IOPAD port map(I => gpio_o(29),O => gpio_bus_in(29),T => gpio_t(29),C => gpio_clk,PAD => WING_BH5 );
pin30: IOPAD port map(I => gpio_o(30),O => gpio_bus_in(30),T => gpio_t(30),C => gpio_clk,PAD => WING_BH6 );
pin31: IOPAD port map(I => gpio_o(31),O => gpio_bus_in(31),T => gpio_t(31),C => gpio_clk,PAD => WING_BH7 );
pin32: IOPAD port map(I => gpio_o(32),O => gpio_bus_in(32),T => gpio_t(32),C => gpio_clk,PAD => WING_CL0 );
pin33: IOPAD port map(I => gpio_o(33),O => gpio_bus_in(33),T => gpio_t(33),C => gpio_clk,PAD => WING_CL1 );
pin34: IOPAD port map(I => gpio_o(34),O => gpio_bus_in(34),T => gpio_t(34),C => gpio_clk,PAD => WING_CL2 );
pin35: IOPAD port map(I => gpio_o(35),O => gpio_bus_in(35),T => gpio_t(35),C => gpio_clk,PAD => WING_CL3 );
pin36: IOPAD port map(I => gpio_o(36),O => gpio_bus_in(36),T => gpio_t(36),C => gpio_clk,PAD => WING_CL4 );
pin37: IOPAD port map(I => gpio_o(37),O => gpio_bus_in(37),T => gpio_t(37),C => gpio_clk,PAD => WING_CL5 );
pin38: IOPAD port map(I => gpio_o(38),O => gpio_bus_in(38),T => gpio_t(38),C => gpio_clk,PAD => WING_CL6 );
pin39: IOPAD port map(I => gpio_o(39),O => gpio_bus_in(39),T => gpio_t(39),C => gpio_clk,PAD => WING_CL7 );
pin40: IOPAD port map(I => gpio_o(40),O => gpio_bus_in(40),T => gpio_t(40),C => gpio_clk,PAD => WING_CH0 );
pin41: IOPAD port map(I => gpio_o(41),O => gpio_bus_in(41),T => gpio_t(41),C => gpio_clk,PAD => WING_CH1 );
pin42: IOPAD port map(I => gpio_o(42),O => gpio_bus_in(42),T => gpio_t(42),C => gpio_clk,PAD => WING_CH2 );
pin43: IOPAD port map(I => gpio_o(43),O => gpio_bus_in(43),T => gpio_t(43),C => gpio_clk,PAD => WING_CH3 );
pin44: IOPAD port map(I => gpio_o(44),O => gpio_bus_in(44),T => gpio_t(44),C => gpio_clk,PAD => WING_CH4 );
pin45: IOPAD port map(I => gpio_o(45),O => gpio_bus_in(45),T => gpio_t(45),C => gpio_clk,PAD => WING_CH5 );
pin46: IOPAD port map(I => gpio_o(46),O => gpio_bus_in(46),T => gpio_t(46),C => gpio_clk,PAD => WING_CH6 );
pin47: IOPAD port map(I => gpio_o(47),O => gpio_bus_in(47),T => gpio_t(47),C => gpio_clk,PAD => WING_CH7 );
-- ospics: OPAD port map ( I => gpio_bus_out.gpio_o(48), PAD => SPI_CS );
process(gpio_spp_read)
-- sigmadelta_spp_data,
-- timers_pwm,
-- spi2_mosi,spi2_sck)
begin
--gpio_spp_data <= (others => DontCareValue);
gpio_bus_in(97 downto 49) <= (others => DontCareValue);
-- gpio_bus_in.gpio_spp_data(0) <= platform_audio_sd; -- PPS0 : SIGMADELTA DATA
-- gpio_bus_in.gpio_spp_data(1) <= timers_pwm(0); -- PPS1 : TIMER0
-- gpio_bus_in.gpio_spp_data(2) <= timers_pwm(1); -- PPS2 : TIMER1
-- gpio_bus_in.gpio_spp_data(3) <= spi2_mosi; -- PPS3 : USPI MOSI
-- gpio_bus_in.gpio_spp_data(4) <= spi2_sck; -- PPS4 : USPI SCK
-- gpio_bus_in.gpio_spp_data(5) <= platform_audio_sd; -- PPS5 : SIGMADELTA1 DATA
-- gpio_bus_in.gpio_spp_data(6) <= uart2_tx; -- PPS6 : UART2 DATA
-- gpio_bus_in.gpio_spp_data(8) <= platform_audio_sd;
-- spi2_miso <= gpio_bus_out_record.gpio_spp_read(0); -- PPS0 : USPI MISO
-- uart2_rx <= gpio_bus_out_record.gpio_spp_read(1); -- PPS0 : USPI MISO
end process;
end BEHAVIORAL;
|
mit
|
chcbaram/FPGA
|
zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Audio_RetroCade_Synth/Libraries/ZPUino_1/Papilio_Default_Pinout.vhd
|
13
|
13239
|
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 14.3
-- \ \ Application :
-- / / Filename : xil_10080_19
-- /___/ /\ Timestamp : 02/08/2013 16:21:11
-- \ \ / \
-- \___\/\___\
--
--Command:
--Design Name:
-- The Papilio Default Pinout device defines the pins for a Papilio board that does not have a MegaWing attached to it.
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
library board;
use board.zpupkg.all;
use board.zpuinopkg.all;
use board.zpuino_config.all;
use board.zpu_config.all;
library zpuino;
use zpuino.pad.all;
use zpuino.papilio_pkg.all;
-- Unfortunately the Xilinx Schematic Editor does not support records, so we have to put all wishbone signals into one array.
-- This is a little cumbersome but is better then dealing with all the signals in the schematic editor.
-- This is what the original record base approach looked like:
--
-- type gpio_bus_in_type is record
-- gpio_i: std_logic_vector(48 downto 0);
-- gpio_spp_data: std_logic_vector(48 downto 0);
-- end record;
--
-- type gpio_bus_out_type is record
-- gpio_clk: std_logic;
-- gpio_o: std_logic_vector(48 downto 0);
-- gpio_t: std_logic_vector(48 downto 0);
-- gpio_spp_read: std_logic_vector(48 downto 0);
-- end record;
--
-- Turning them into an array looks like this:
--
-- gpio_bus_in : in std_logic_vector(97 downto 0);
--
-- gpio_bus_in(97 downto 49) <= gpio_i;
-- gpio_bus_in(48 downto 0) <= gpio_bus_in_record.gpio_spp_data;
--
-- gpio_bus_out : out std_logic_vector(146 downto 0);
--
-- gpio_o <= gpio_bus_out(146 downto 98);
-- gpio_t <= gpio_bus_out(97 downto 49);
-- gpio_bus_out_record.gpio_spp_read <= gpio_bus_out(48 downto 0);
entity Papilio_Default_Pinout is
port (
-- gpio_clk: in std_logic;
-- gpio_o: in std_logic_vector(48 downto 0);
-- gpio_t: in std_logic_vector(48 downto 0);
-- gpio_i: out std_logic_vector(48 downto 0);
--
-- gpio_spp_data: out std_logic_vector(48 downto 0);
-- gpio_spp_read: in std_logic_vector(48 downto 0);
gpio_bus_in : out std_logic_vector(97 downto 0);
gpio_bus_out : in std_logic_vector(147 downto 0);
WING_AH0 : inout std_logic;
WING_AH1 : inout std_logic;
WING_AH2 : inout std_logic;
WING_AH3 : inout std_logic;
WING_AH4 : inout std_logic;
WING_AH5 : inout std_logic;
WING_AH6 : inout std_logic;
WING_AH7 : inout std_logic;
WING_AL0 : inout std_logic;
WING_AL1 : inout std_logic;
WING_AL2 : inout std_logic;
WING_AL3 : inout std_logic;
WING_AL4 : inout std_logic;
WING_AL5 : inout std_logic;
WING_AL6 : inout std_logic;
WING_AL7 : inout std_logic;
WING_BH0 : inout std_logic;
WING_BH1 : inout std_logic;
WING_BH2 : inout std_logic;
WING_BH3 : inout std_logic;
WING_BH4 : inout std_logic;
WING_BH5 : inout std_logic;
WING_BH6 : inout std_logic;
WING_BH7 : inout std_logic;
WING_BL0 : inout std_logic;
WING_BL1 : inout std_logic;
WING_BL2 : inout std_logic;
WING_BL3 : inout std_logic;
WING_BL4 : inout std_logic;
WING_BL5 : inout std_logic;
WING_BL6 : inout std_logic;
WING_BL7 : inout std_logic;
WING_CH0 : inout std_logic;
WING_CH1 : inout std_logic;
WING_CH2 : inout std_logic;
WING_CH3 : inout std_logic;
WING_CH4 : inout std_logic;
WING_CH5 : inout std_logic;
WING_CH6 : inout std_logic;
WING_CH7 : inout std_logic;
WING_CL0 : inout std_logic;
WING_CL1 : inout std_logic;
WING_CL2 : inout std_logic;
WING_CL3 : inout std_logic;
WING_CL4 : inout std_logic;
WING_CL5 : inout std_logic;
WING_CL6 : inout std_logic;
WING_CL7 : inout std_logic
);
end Papilio_Default_Pinout;
architecture BEHAVIORAL of Papilio_Default_Pinout is
-- signal gpio_bus_out.gpio_o: std_logic_vector(zpuino_gpio_count-1 downto 0);
-- signal gpio_bus_out.gpio_t: std_logic_vector(zpuino_gpio_count-1 downto 0);
-- signal gpio_bus_in.gpio_i: std_logic_vector(zpuino_gpio_count-1 downto 0);
--
-- -- SPP signal is one more than GPIO count
-- signal gpio_bus_in.gpio_spp_data: std_logic_vector(zpuino_gpio_count-1 downto 0);
-- signal gpio_bus_out.gpio_spp_read: std_logic_vector(zpuino_gpio_count-1 downto 0);
--
-- constant spp_cap_in: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
-- "0" &
-- "1111111111111111" &
-- "1111111111111111" &
-- "1111111111111111";
-- constant spp_cap_out: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
-- "0" &
-- "1111111111111111" &
-- "1111111111111111" &
-- "1111111111111111";
-- signal gpio_bus_in_record : gpio_bus_in_type;
-- signal gpio_bus_out_record : gpio_bus_out_type;
signal gpio_o: std_logic_vector(48 downto 0);
signal gpio_t: std_logic_vector(48 downto 0);
signal gpio_i: std_logic_vector(48 downto 0);
signal gpio_spp_data: std_logic_vector(48 downto 0);
signal gpio_spp_read: std_logic_vector(48 downto 0);
signal gpio_clk: std_logic;
begin
--Unpack the signal array into a record so the modules code is easier to understand.
--gpio_bus_in(97 downto 49) <= gpio_spp_data;
--gpio_bus_in(48 downto 0) <= gpio_i;
gpio_clk <= gpio_bus_out(147);
gpio_o <= gpio_bus_out(146 downto 98);
gpio_t <= gpio_bus_out(97 downto 49);
gpio_spp_read <= gpio_bus_out(48 downto 0);
-- gpio_bus_in(97 downto 49) <= gpio_i;
-- gpio_bus_in(48 downto 0) <= gpio_bus_in_record.gpio_spp_data;
-- gpio_clk <= gpio_bus_out(147);
-- gpio_o <= gpio_bus_out(146 downto 98);
-- gpio_t <= gpio_bus_out(97 downto 49);
-- gpio_bus_out_record.gpio_spp_read <= gpio_bus_out(48 downto 0);
-- gpio_bus_in.gpio_inst: zpuino_gpio
-- generic map (
-- gpio_count => zpuino_gpio_count
-- )
-- port map (
-- gpio_bus_out.gpio_clk => gpio_bus_out.gpio_clk,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => wb_dat_o,
-- wb_dat_i => wb_dat_i,
-- wb_adr_i => wb_adr_i,
-- wb_we_i => wb_we_i,
-- wb_cyc_i => wb_cyc_i,
-- wb_stb_i => wb_stb_i,
-- wb_ack_o => wb_ack_o,
-- wb_inta_o => wb_inta_o,
--
-- spp_data => gpio_bus_in.gpio_spp_data,
-- spp_read => gpio_bus_out.gpio_spp_read,
--
-- gpio_bus_in.gpio_i => gpio_bus_in.gpio_i,
-- gpio_bus_out.gpio_t => gpio_bus_out.gpio_t,
-- gpio_bus_out.gpio_o => gpio_bus_out.gpio_o,
-- spp_cap_in => spp_cap_in,
-- spp_cap_out => spp_cap_out
-- );
pin00: IOPAD port map(I => gpio_o(0), O => gpio_bus_in(0), T => gpio_t(0), C => gpio_clk,PAD => WING_AL0 );
pin01: IOPAD port map(I => gpio_o(1), O => gpio_bus_in(1), T => gpio_t(1), C => gpio_clk,PAD => WING_AL1 );
pin02: IOPAD port map(I => gpio_o(2), O => gpio_bus_in(2), T => gpio_t(2), C => gpio_clk,PAD => WING_AL2 );
pin03: IOPAD port map(I => gpio_o(3), O => gpio_bus_in(3), T => gpio_t(3), C => gpio_clk,PAD => WING_AL3 );
pin04: IOPAD port map(I => gpio_o(4), O => gpio_bus_in(4), T => gpio_t(4), C => gpio_clk,PAD => WING_AL4 );
pin05: IOPAD port map(I => gpio_o(5), O => gpio_bus_in(5), T => gpio_t(5), C => gpio_clk,PAD => WING_AL5 );
pin06: IOPAD port map(I => gpio_o(6), O => gpio_bus_in(6), T => gpio_t(6), C => gpio_clk,PAD => WING_AL6 );
pin07: IOPAD port map(I => gpio_o(7), O => gpio_bus_in(7), T => gpio_t(7), C => gpio_clk,PAD => WING_AL7 );
pin08: IOPAD port map(I => gpio_o(8), O => gpio_bus_in(8), T => gpio_t(8), C => gpio_clk,PAD => WING_AH0 );
pin09: IOPAD port map(I => gpio_o(9), O => gpio_bus_in(9), T => gpio_t(9), C => gpio_clk,PAD => WING_AH1 );
pin10: IOPAD port map(I => gpio_o(10),O => gpio_bus_in(10),T => gpio_t(10),C => gpio_clk,PAD => WING_AH2 );
pin11: IOPAD port map(I => gpio_o(11),O => gpio_bus_in(11),T => gpio_t(11),C => gpio_clk,PAD => WING_AH3 );
pin12: IOPAD port map(I => gpio_o(12),O => gpio_bus_in(12),T => gpio_t(12),C => gpio_clk,PAD => WING_AH4 );
pin13: IOPAD port map(I => gpio_o(13),O => gpio_bus_in(13),T => gpio_t(13),C => gpio_clk,PAD => WING_AH5 );
pin14: IOPAD port map(I => gpio_o(14),O => gpio_bus_in(14),T => gpio_t(14),C => gpio_clk,PAD => WING_AH6 );
pin15: IOPAD port map(I => gpio_o(15),O => gpio_bus_in(15),T => gpio_t(15),C => gpio_clk,PAD => WING_AH7 );
pin16: IOPAD port map(I => gpio_o(16),O => gpio_bus_in(16),T => gpio_t(16),C => gpio_clk,PAD => WING_BL0 );
pin17: IOPAD port map(I => gpio_o(17),O => gpio_bus_in(17),T => gpio_t(17),C => gpio_clk,PAD => WING_BL1 );
pin18: IOPAD port map(I => gpio_o(18),O => gpio_bus_in(18),T => gpio_t(18),C => gpio_clk,PAD => WING_BL2 );
pin19: IOPAD port map(I => gpio_o(19),O => gpio_bus_in(19),T => gpio_t(19),C => gpio_clk,PAD => WING_BL3 );
pin20: IOPAD port map(I => gpio_o(20),O => gpio_bus_in(20),T => gpio_t(20),C => gpio_clk,PAD => WING_BL4 );
pin21: IOPAD port map(I => gpio_o(21),O => gpio_bus_in(21),T => gpio_t(21),C => gpio_clk,PAD => WING_BL5 );
pin22: IOPAD port map(I => gpio_o(22),O => gpio_bus_in(22),T => gpio_t(22),C => gpio_clk,PAD => WING_BL6 );
pin23: IOPAD port map(I => gpio_o(23),O => gpio_bus_in(23),T => gpio_t(23),C => gpio_clk,PAD => WING_BL7 );
pin24: IOPAD port map(I => gpio_o(24),O => gpio_bus_in(24),T => gpio_t(24),C => gpio_clk,PAD => WING_BH0 );
pin25: IOPAD port map(I => gpio_o(25),O => gpio_bus_in(25),T => gpio_t(25),C => gpio_clk,PAD => WING_BH1 );
pin26: IOPAD port map(I => gpio_o(26),O => gpio_bus_in(26),T => gpio_t(26),C => gpio_clk,PAD => WING_BH2 );
pin27: IOPAD port map(I => gpio_o(27),O => gpio_bus_in(27),T => gpio_t(27),C => gpio_clk,PAD => WING_BH3 );
pin28: IOPAD port map(I => gpio_o(28),O => gpio_bus_in(28),T => gpio_t(28),C => gpio_clk,PAD => WING_BH4 );
pin29: IOPAD port map(I => gpio_o(29),O => gpio_bus_in(29),T => gpio_t(29),C => gpio_clk,PAD => WING_BH5 );
pin30: IOPAD port map(I => gpio_o(30),O => gpio_bus_in(30),T => gpio_t(30),C => gpio_clk,PAD => WING_BH6 );
pin31: IOPAD port map(I => gpio_o(31),O => gpio_bus_in(31),T => gpio_t(31),C => gpio_clk,PAD => WING_BH7 );
pin32: IOPAD port map(I => gpio_o(32),O => gpio_bus_in(32),T => gpio_t(32),C => gpio_clk,PAD => WING_CL0 );
pin33: IOPAD port map(I => gpio_o(33),O => gpio_bus_in(33),T => gpio_t(33),C => gpio_clk,PAD => WING_CL1 );
pin34: IOPAD port map(I => gpio_o(34),O => gpio_bus_in(34),T => gpio_t(34),C => gpio_clk,PAD => WING_CL2 );
pin35: IOPAD port map(I => gpio_o(35),O => gpio_bus_in(35),T => gpio_t(35),C => gpio_clk,PAD => WING_CL3 );
pin36: IOPAD port map(I => gpio_o(36),O => gpio_bus_in(36),T => gpio_t(36),C => gpio_clk,PAD => WING_CL4 );
pin37: IOPAD port map(I => gpio_o(37),O => gpio_bus_in(37),T => gpio_t(37),C => gpio_clk,PAD => WING_CL5 );
pin38: IOPAD port map(I => gpio_o(38),O => gpio_bus_in(38),T => gpio_t(38),C => gpio_clk,PAD => WING_CL6 );
pin39: IOPAD port map(I => gpio_o(39),O => gpio_bus_in(39),T => gpio_t(39),C => gpio_clk,PAD => WING_CL7 );
pin40: IOPAD port map(I => gpio_o(40),O => gpio_bus_in(40),T => gpio_t(40),C => gpio_clk,PAD => WING_CH0 );
pin41: IOPAD port map(I => gpio_o(41),O => gpio_bus_in(41),T => gpio_t(41),C => gpio_clk,PAD => WING_CH1 );
pin42: IOPAD port map(I => gpio_o(42),O => gpio_bus_in(42),T => gpio_t(42),C => gpio_clk,PAD => WING_CH2 );
pin43: IOPAD port map(I => gpio_o(43),O => gpio_bus_in(43),T => gpio_t(43),C => gpio_clk,PAD => WING_CH3 );
pin44: IOPAD port map(I => gpio_o(44),O => gpio_bus_in(44),T => gpio_t(44),C => gpio_clk,PAD => WING_CH4 );
pin45: IOPAD port map(I => gpio_o(45),O => gpio_bus_in(45),T => gpio_t(45),C => gpio_clk,PAD => WING_CH5 );
pin46: IOPAD port map(I => gpio_o(46),O => gpio_bus_in(46),T => gpio_t(46),C => gpio_clk,PAD => WING_CH6 );
pin47: IOPAD port map(I => gpio_o(47),O => gpio_bus_in(47),T => gpio_t(47),C => gpio_clk,PAD => WING_CH7 );
-- ospics: OPAD port map ( I => gpio_bus_out.gpio_o(48), PAD => SPI_CS );
process(gpio_spp_read)
-- sigmadelta_spp_data,
-- timers_pwm,
-- spi2_mosi,spi2_sck)
begin
--gpio_spp_data <= (others => DontCareValue);
gpio_bus_in(97 downto 49) <= (others => DontCareValue);
-- gpio_bus_in.gpio_spp_data(0) <= platform_audio_sd; -- PPS0 : SIGMADELTA DATA
-- gpio_bus_in.gpio_spp_data(1) <= timers_pwm(0); -- PPS1 : TIMER0
-- gpio_bus_in.gpio_spp_data(2) <= timers_pwm(1); -- PPS2 : TIMER1
-- gpio_bus_in.gpio_spp_data(3) <= spi2_mosi; -- PPS3 : USPI MOSI
-- gpio_bus_in.gpio_spp_data(4) <= spi2_sck; -- PPS4 : USPI SCK
-- gpio_bus_in.gpio_spp_data(5) <= platform_audio_sd; -- PPS5 : SIGMADELTA1 DATA
-- gpio_bus_in.gpio_spp_data(6) <= uart2_tx; -- PPS6 : UART2 DATA
-- gpio_bus_in.gpio_spp_data(8) <= platform_audio_sd;
-- spi2_miso <= gpio_bus_out_record.gpio_spp_read(0); -- PPS0 : USPI MISO
-- uart2_rx <= gpio_bus_out_record.gpio_spp_read(1); -- PPS0 : USPI MISO
end process;
end BEHAVIORAL;
|
mit
|
chcbaram/FPGA
|
zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Audio_ModFile_simple/Libraries/ZPUino_1/wbmux2.vhd
|
13
|
2538
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
library board;
use board.zpu_config.all;
entity wbmux2 is
generic (
select_line: integer;
address_high: integer:=31;
address_low: integer:=2
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master
m_wb_dat_o: out std_logic_vector(31 downto 0);
m_wb_dat_i: in std_logic_vector(31 downto 0);
m_wb_adr_i: in std_logic_vector(address_high downto address_low);
m_wb_sel_i: in std_logic_vector(3 downto 0);
m_wb_cti_i: in std_logic_vector(2 downto 0);
m_wb_we_i: in std_logic;
m_wb_cyc_i: in std_logic;
m_wb_stb_i: in std_logic;
m_wb_ack_o: out std_logic;
-- Slave 0 signals
s0_wb_dat_i: in std_logic_vector(31 downto 0);
s0_wb_dat_o: out std_logic_vector(31 downto 0);
s0_wb_adr_o: out std_logic_vector(address_high downto address_low);
s0_wb_sel_o: out std_logic_vector(3 downto 0);
s0_wb_cti_o: out std_logic_vector(2 downto 0);
s0_wb_we_o: out std_logic;
s0_wb_cyc_o: out std_logic;
s0_wb_stb_o: out std_logic;
s0_wb_ack_i: in std_logic;
-- Slave 1 signals
s1_wb_dat_i: in std_logic_vector(31 downto 0);
s1_wb_dat_o: out std_logic_vector(31 downto 0);
s1_wb_adr_o: out std_logic_vector(address_high downto address_low);
s1_wb_sel_o: out std_logic_vector(3 downto 0);
s1_wb_cti_o: out std_logic_vector(2 downto 0);
s1_wb_we_o: out std_logic;
s1_wb_cyc_o: out std_logic;
s1_wb_stb_o: out std_logic;
s1_wb_ack_i: in std_logic
);
end entity wbmux2;
architecture behave of wbmux2 is
signal select_zero: std_logic;
begin
select_zero<='1' when m_wb_adr_i(select_line)='0' else '0';
s0_wb_dat_o <= m_wb_dat_i;
s0_wb_adr_o <= m_wb_adr_i;
s0_wb_stb_o <= m_wb_stb_i;
s0_wb_we_o <= m_wb_we_i;
s0_wb_cti_o <= m_wb_cti_i;
s0_wb_sel_o <= m_wb_sel_i;
s1_wb_dat_o <= m_wb_dat_i;
s1_wb_adr_o <= m_wb_adr_i;
s1_wb_stb_o <= m_wb_stb_i;
s1_wb_we_o <= m_wb_we_i;
s1_wb_cti_o <= m_wb_cti_i;
s1_wb_sel_o <= m_wb_sel_i;
process(m_wb_cyc_i,select_zero)
begin
if m_wb_cyc_i='0' then
s0_wb_cyc_o<='0';
s1_wb_cyc_o<='0';
else
s0_wb_cyc_o<=select_zero;
s1_wb_cyc_o<=not select_zero;
end if;
end process;
process(select_zero,s1_wb_dat_i,s0_wb_dat_i,s0_wb_ack_i,s1_wb_ack_i)
begin
if select_zero='0' then
m_wb_dat_o<=s1_wb_dat_i;
m_wb_ack_o<=s1_wb_ack_i;
else
m_wb_dat_o<=s0_wb_dat_i;
m_wb_ack_o<=s0_wb_ack_i;
end if;
end process;
end behave;
|
mit
|
sinkswim/DLX-Pro
|
DLX_simulation_cfg/a.c-CU.vhd
|
1
|
14779
|
----------------------------------------------------------------------------------------------------------
-- Control Unit Hardwired: Purpose of this unit is to generate the correct CW and ALUOP depending on the
-- value of the OPCODE and FUNC field.
-- Three LUTs have been used: one for the Control Word, one for alu operation for the r-type instructions
-- and the last one for the alu operation for the non-r-type instructions. It is worth noting that in
-- order to use opcode and func to address those memories, it has been necessary to add nop (zeros) for
-- those instructions that have been not implemented.
----------------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.globals.all;
entity cu is
port (
-- INPUTS
opcode : in std_logic_vector(OPCODE_SIZE-1 downto 0); -- opcode field in instruction register
func : in std_logic_vector(FUNC_SIZE-1 downto 0); -- func field in instruction register
-- OUTPUTS
cw : out std_logic_vector((CW_SIZE+ALUOP_SIZE)-1 downto 0) -- Control Word + ALU operation for the current instruction decoded
);
end cu;
architecture behavioral of cu is
-- Sub-type declaration
type cw_mem_array is array (integer range 0 to SIZE_LUT - 1) of std_logic_vector(CW_SIZE - 1 downto 0);
type alu_op_mem_array is array (integer range 0 to SIZE_LUT -1) of std_logic_vector(ALUOP_SIZE -1 downto 0);
-- Constants declaration
constant cw_lut : cw_mem_array := ( "100000100000000000", -- this LUT will be addressed with the opcode and will produce the control word for all instructions
"000000000000000000",
"000000000000000010",
"100010000000000010",
"000000000000000001",
"000100000000000001",
"000000000000000000",
"000000000000000000",
"100000001000000000",
"110000001000000000",
"100000001000000000",
"110000001000000000",
"100000001000000000",
"100000001000000000",
"100000001000000000",
"100001000000000000",
"000000000000000000",
"000000000000000000",
"001000000000000010",
"101010000000000010",
"110000001000000000",
"000000000000000000",
"110000001000000000",
"110000001000000000",
"100000001000000000",
"100000001000000000",
"100000001000000000",
"100000001000000000",
"100000001000000000",
"100000001000000000",
"000000000000000000",
"000000000000000000",
"100000001000001100",
"000000000000000000",
"000000000000000000",
"100000001000100100",
"100000001001000100",
"100000001000010100",
"000000000000000000",
"000000000000000000",
"000000001100000000",
"000000000000000000",
"000000000000000000",
"000000001010000000",
"000000000000000000",
"000000000000000000",
"000000000000000000",
"000000000000000000",
"000000000000000000",
"000000000000000000",
"000000000000000000",
"000000000000000000",
"000000000000000000",
"000000000000000000",
"000000000000000000",
"000000000000000000",
"000000000000000000",
"000000000000000000",
"110000001000000000",
"110000001000000000",
"000000000000000000",
"110000001000000000");
constant r_type_aluop_lut : alu_op_mem_array := ( "00000", -- this LUT will be addressed with the func field and will produce the alu operation for r-type instructions
"00000",
"00000",
"00000",
"00001",
"00000",
"00010",
"00011",
"00000",
"00000",
"00000",
"00000",
"00000",
"00000",
"00000",
"00000",
"00000",
"00000",
"00000",
"00000",
"00000",
"00000",
"00000",
"00000",
"00000",
"00000",
"00000",
"00000",
"00000",
"00000",
"00000",
"00000",
"00100",
"00101",
"00110",
"00111",
"01000",
"01001",
"01010",
"00000",
"01011",
"01100",
"01101",
"01110",
"01111",
"10000",
"00000",
"00000",
"00000",
"00000",
"00000",
"00000",
"00000",
"00000",
"00000",
"00000",
"00000",
"00000",
"10001",
"10010",
"00000",
"10011" );
constant no_r_type_aluop_lut : alu_op_mem_array := ( "00000", -- this LUT will be addressed using the opcode and will produce the alu operation for non r-type instructions
"00000",
"00000",
"00000",
"00100",
"00100",
"00000",
"00000",
"00100",
"00101",
"00110",
"00111",
"01000",
"01001",
"01010",
"00000",
"00000",
"00000",
"00000",
"00000",
"00001",
"00000",
"00010",
"00011",
"01011",
"01100",
"01101",
"01110",
"01111",
"10000",
"00000",
"00000",
"00101",
"00000",
"00000",
"00101",
"00101",
"00101",
"00000",
"00000",
"00101",
"00000",
"00000",
"00101",
"00000",
"00000",
"00000",
"00000",
"00000",
"00000",
"00000",
"00000",
"00000",
"00000",
"00000",
"00000",
"00000",
"00000",
"10001",
"10010",
"00000",
"10011");
-- Internal signals declaration
signal cw_i : std_logic_vector(CW_SIZE-1 downto 0);
signal aluop_i : std_logic_vector(ALUOP_SIZE-1 downto 0);
begin
cw_i <= cw_lut(to_integer(unsigned(opcode)));
aluop_i <= r_type_aluop_lut(to_integer(unsigned(func))) when (opcode = RTYPE) else
no_r_type_aluop_lut(to_integer(unsigned(opcode)));
-- Since instruction movs2i is RTYPE but it is the only one with different control word
-- with respect to the other RTYPE instructions. Normally 10th bit of cw is at 0, except
-- for the instruction movs2i
cw <= cw_i(CW_SIZE-1 downto 11) & '1' & cw_i(9 downto 0) & aluop_i when ((opcode = RTYPE) and (func = FUNC_MOVS2I)) else cw_i & aluop_i;
end behavioral;
|
mit
|
chcbaram/FPGA
|
zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Benchy_Sump_LogicAnalyzer_JTAG/Libraries/ZPUino_1/zpuino_debug_core_hyperion.vhd
|
13
|
5403
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config_hyperion.all;
use board.zpupkg_hyperion.all;
use board.zpuinopkg.all;
entity zpuino_debug_core_hyperion is
port (
clk: in std_logic;
rst: in std_logic;
dbg_in: in zpu_dbg_out_type;
dbg_out: out zpu_dbg_in_type;
dbg_reset: out std_logic;
jtag_data_chain_out: out std_logic_vector(98 downto 0);
jtag_ctrl_chain_in: in std_logic_vector(11 downto 0)
);
end entity;
architecture behave of zpuino_debug_core_hyperion is
signal enter_ss: std_logic :='0';
signal step: std_logic := '0';
signal status_injection_ready: std_logic;
signal status_injectmode: std_logic;
type state_type is (
state_idle,
state_debug,
state_enter_inject,
state_flush,
state_inject,
state_leave_inject,
state_step
);
type dbgregs_type is record
state: state_type;
step: std_logic;
inject: std_logic;
freeze: std_logic;
injectmode: std_logic;
reset: std_logic;
flush: std_logic;
opcode: std_logic_vector(7 downto 0);
end record;
signal dbgr: dbgregs_type;
signal injected: std_logic;
signal inject_q_in: std_logic := '0';
signal inject_q: std_logic := '0';
alias jtag_debug: std_logic is jtag_ctrl_chain_in(0);
alias jtag_inject: std_logic is jtag_ctrl_chain_in(1);
alias jtag_step: std_logic is jtag_ctrl_chain_in(2);
alias jtag_reset: std_logic is jtag_ctrl_chain_in(3);
alias jtag_opcode: std_logic_vector(7 downto 0) is jtag_ctrl_chain_in(11 downto 4);
signal pc_i: std_logic_vector(wordSize-1 downto 0);
signal sp_i: std_logic_vector(wordSize-1 downto 0);
begin
pc_i(wordSize-1 downto dbg_in.pc'high+1) <= (others => '0');
pc_i(dbg_in.pc'high downto dbg_in.pc'low) <= dbg_in.pc;
sp_i(wordSize-1 downto dbg_in.sp'high+1) <= (others => '0');
sp_i(dbg_in.sp'high downto dbg_in.sp'low) <= dbg_in.sp;
sp_i(dbg_in.sp'low-1 downto 0) <= (others => '0');
-- jtag chain output
jtag_data_chain_out <=
dbg_in.idim &
sp_i &
dbg_in.stacka &
pc_i &
dbg_in.brk &
status_injection_ready
;
status_injection_ready <= '1' when dbgr.state = state_debug else '0';
process(clk, rst, dbgr, dbg_in.valid, jtag_debug, jtag_opcode,
inject_q, dbg_in.ready, dbg_in.pc, dbg_in.idim, jtag_ctrl_chain_in)
variable w: dbgregs_type;
begin
w := dbgr;
if rst='1' then
w.state := state_idle;
w.reset := '0';
w.flush := '0';
w.injectmode := '0';
w.inject := '0';
w.step := '0';
w.freeze := '0';
injected <= '0';
else
injected <= '0';
case dbgr.state is
when state_idle =>
w.freeze := '0';
--if jtag_debug='1' then
-- w.freeze := '1';
-- w.state := state_debug;
--end if;
if jtag_debug='1' then
--if dbg_ready='1' then
w.injectmode := '1';
--w.opcode := jtag_opcode;
-- end if;
-- Wait for pipeline to finish
if dbg_in.valid='0' and dbg_in.ready='1' then
--report "Enter PC " & hstr(dbg_pc) & " IDIM flag " & chr(dbg_idim) severity note;
w.state:=state_debug;
end if;
--end if;
end if;
when state_debug =>
w.step := '0';
if inject_q='1' then
w.state := state_enter_inject;
w.injectmode := '1';
w.opcode := jtag_opcode;
elsif jtag_debug='0' then
w.flush:='1';
w.state := state_leave_inject;
end if;
when state_leave_inject =>
w.flush := '0';
w.injectmode:='0';
w.state := state_idle;
when state_enter_inject =>
-- w.state := state_flush;
w.state := state_inject;
when state_flush =>
w.flush := '1';
w.state := state_inject;
when state_inject =>
w.inject := '1';
w.flush := '0';
-- Here ?
injected <= '1';
w.state := state_step;
when state_step =>
injected <= '0';
w.inject := '0';
if dbg_in.valid='1' then
-- w.step := '1';
w.state := state_debug;
end if;
when others =>
end case;
end if;
if rising_edge(clk) then
dbgr <= w;
end if;
end process;
dbg_out.freeze <= dbgr.freeze;
--dbg_reset <= dbgr.reset;
dbg_out.inject <= dbgr.inject;
dbg_out.injectmode <= dbgr.injectmode;-- and dbg_ready;
dbg_out.step <= dbgr.step;
dbg_out.flush <= dbgr.flush;
dbg_out.opcode <= dbgr.opcode;
process(clk)
begin
if rising_edge(clk) then
dbg_reset <= jtag_ctrl_chain_in(3);
end if;
end process;
-- Synchronization stuff
process(jtag_inject, clk, injected, inject_q_in)
begin
if injected='1' then
inject_q <= '0';
inject_q_in <= '0';
else
if rising_edge(jtag_inject) then
inject_q_in <= '1';
--else
-- inject_q_in <= inject_q_in;
end if;
if rising_edge(clk) then
inject_q <= inject_q_in;
end if;
end if;
end process;
end behave;
|
mit
|
chcbaram/FPGA
|
zap-2.3.0-windows/papilio-zap-ide/examples/00.Papilio_Schematic_Library/examples/Audio_SID_simple/Libraries/Wishbone_Peripherals/clk_32to25_dcm.vhd
|
13
|
6302
|
-- file: clk_32to25_dcm.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1____50.000______0.000______50.0______600.000____150.000
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary__________32.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk_32to25_dcm is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic
);
end clk_32to25_dcm;
architecture xilinx of clk_32to25_dcm is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_32to25_dcm,clk_wiz_v3_6,{component_name=clk_32to25_dcm,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=1,clkin1_period=31.25,clkin2_period=31.25,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering
signal clkfb : std_logic;
signal clk0 : std_logic;
signal clkfx : std_logic;
signal clkfbout : std_logic;
signal locked_internal : std_logic;
signal status_internal : std_logic_vector(7 downto 0);
begin
-- Input buffering
--------------------------------------
--clkin1 <= CLK_IN1;
clkin2_inst: BUFG
port map (
I => CLK_IN1,
O => clkin1
);
-- Clocking primitive
--------------------------------------
-- Instantiation of the DCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
dcm_sp_inst: DCM_SP
generic map
(CLKDV_DIVIDE => 2.000,
CLKFX_DIVIDE => 32,
CLKFX_MULTIPLY => 25,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 31.25,
CLKOUT_PHASE_SHIFT => "NONE",
CLK_FEEDBACK => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map
-- Input clock
(CLKIN => clkin1,
CLKFB => clkfb,
-- Output clocks
CLK0 => clk0,
CLK90 => open,
CLK180 => open,
CLK270 => open,
CLK2X => open,
CLK2X180 => open,
CLKFX => clkfx,
CLKFX180 => open,
CLKDV => open,
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => locked_internal,
STATUS => status_internal,
RST => '0',
-- Unused pin, tie low
DSSEN => '0');
-- Output buffering
-------------------------------------
-- no phase alignment active, connect to ground
clkfb <= '0';
-- clkout1_buf : BUFG
-- port map
-- (O => CLK_OUT1,
-- I => clkfx);
CLK_OUT1 <= clkfx;
end xilinx;
|
mit
|
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