repo_name
stringlengths 6
79
| path
stringlengths 5
236
| copies
stringclasses 54
values | size
stringlengths 1
8
| content
stringlengths 0
1.04M
⌀ | license
stringclasses 15
values |
|---|---|---|---|---|---|
yunqu/PYNQ
|
boards/ip/dvi2rgb_v1_7/src/InputSERDES.vhd
|
15
|
10056
|
-------------------------------------------------------------------------------
--
-- File: InputSERDES.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 8 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module instantiates the Xilinx 7-series primitives necessary for
-- de-serializing the TMDS data stream.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity InputSERDES is
Generic (
kIDLY_TapWidth : natural := 5; -- number of bits for IDELAYE2 tap counter
kParallelWidth : natural := 10); -- number of parallel bits
Port (
PixelClk : in std_logic; --Recovered TMDS clock x1 (CLKDIV)
SerialClk : in std_logic; --Recovered TMDS clock x5 (CLK)
--Encoded serial data
sDataIn_p : in std_logic; --TMDS data channel positive
sDataIn_n : in std_logic; --TMDS data channel negative
--Encoded parallel data (raw)
pDataIn : out STD_LOGIC_VECTOR (kParallelWidth-1 downto 0);
--Control for phase alignment
pBitslip : in STD_LOGIC; --Bitslip for ISERDESE2
pIDLY_LD : in STD_LOGIC; --IDELAYE2 Load
pIDLY_CE : in STD_LOGIC; --IDELAYE2 CE
pIDLY_INC : in STD_LOGIC; --IDELAYE2 Tap Increment
pIDLY_CNT : out std_logic_vector(kIDLY_TapWidth-1 downto 0); --IDELAYE2 Current Tap Count
aRst : in STD_LOGIC
);
end InputSERDES;
architecture Behavioral of InputSERDES is
signal sDataIn, sDataInDly, icascade1, icascade2, SerialClkInv : std_logic;
signal pDataIn_q : std_logic_vector(13 downto 0); --ISERDESE2 can do 1:14 at most
begin
-- Differential input buffer for TMDS I/O standard
InputBuffer: IBUFDS
generic map (
DIFF_TERM => FALSE,
IOSTANDARD => "TMDS_33")
port map (
I => sDataIn_p,
IB => sDataIn_n,
O => sDataIn);
-- Delay element for phase alignment of serial data
InputDelay: IDELAYE2
generic map (
CINVCTRL_SEL => "FALSE", -- TRUE, FALSE
DELAY_SRC => "IDATAIN", -- IDATAIN, DATAIN
HIGH_PERFORMANCE_MODE => "TRUE", -- TRUE, FALSE
IDELAY_TYPE => "VARIABLE", -- FIXED, VARIABLE, or VAR_LOADABLE
IDELAY_VALUE => 0, -- 0 to 31
REFCLK_FREQUENCY => 200.0,
PIPE_SEL => "FALSE",
SIGNAL_PATTERN => "DATA") -- CLOCK, DATA
port map (
DATAOUT => sDataInDly, -- Delayed signal
DATAIN => '0', -- Not used; IDATAIN instead
C => PixelClk, -- Clock for control signals (CE,INC...)
CE => pIDLY_CE,
INC => pIDLY_INC,
IDATAIN => sDataIn, -- Driven by IOB
LD => pIDLY_LD,
REGRST => '0', --not used in VARIABLE mode
LDPIPEEN => '0',
CNTVALUEIN => "00000", --not used in VARIABLE mode
CNTVALUEOUT => pIDLY_CNT, -- current tap value
CINVCTRL => '0');
--Invert locally for ISERDESE2
SerialClkInv <= not SerialClk;
-- De-serializer, 1:10 (1:5 DDR), master-slave cascaded
DeserializerMaster: ISERDESE2
generic map (
DATA_RATE => "DDR",
DATA_WIDTH => kParallelWidth,
INTERFACE_TYPE => "NETWORKING",
DYN_CLKDIV_INV_EN => "FALSE",
DYN_CLK_INV_EN => "FALSE",
NUM_CE => 2,
OFB_USED => "FALSE",
IOBDELAY => "IFD", -- Use input at DDLY to output the data on Q1-Q6
SERDES_MODE => "MASTER")
port map (
Q1 => pDataIn_q(0),
Q2 => pDataIn_q(1),
Q3 => pDataIn_q(2),
Q4 => pDataIn_q(3),
Q5 => pDataIn_q(4),
Q6 => pDataIn_q(5),
Q7 => pDataIn_q(6),
Q8 => pDataIn_q(7),
SHIFTOUT1 => icascade1, -- Cascade connection to Slave ISERDES
SHIFTOUT2 => icascade2, -- Cascade connection to Slave ISERDES
BITSLIP => pBitslip, -- 1-bit Invoke Bitslip. This can be used with any
CE1 => '1', -- 1-bit Clock enable input
CE2 => '1', -- 1-bit Clock enable input
CLK => SerialClk, -- Fast Source Synchronous SERDES clock from BUFIO
CLKB => SerialClkInv, -- Locally inverted clock
CLKDIV => PixelClk, -- Slow clock driven by BUFR
CLKDIVP => '0', --Not used here
D => '0',
DDLY => sDataInDly, -- 1-bit Input signal from IODELAYE1.
RST => aRst, -- 1-bit Asynchronous reset only.
SHIFTIN1 => '0',
SHIFTIN2 => '0',
-- unused connections
DYNCLKDIVSEL => '0',
DYNCLKSEL => '0',
OFB => '0',
OCLK => '0',
OCLKB => '0',
O => open); -- unregistered output of ISERDESE1
DeserializerSlave: ISERDESE2
generic map (
DATA_RATE => "DDR",
DATA_WIDTH => 10,
INTERFACE_TYPE => "NETWORKING",
DYN_CLKDIV_INV_EN => "FALSE",
DYN_CLK_INV_EN => "FALSE",
NUM_CE => 2,
OFB_USED => "FALSE",
IOBDELAY => "IFD", -- Use input at DDLY to output the data on Q1-Q6
SERDES_MODE => "SLAVE")
port map (
Q1 => open, --not used in cascaded mode
Q2 => open, --not used in cascaded mode
Q3 => pDataIn_q(8),
Q4 => pDataIn_q(9),
Q5 => pDataIn_q(10),
Q6 => pDataIn_q(11),
Q7 => pDataIn_q(12),
Q8 => pDataIn_q(13),
SHIFTOUT1 => open,
SHIFTOUT2 => open,
SHIFTIN1 => icascade1, -- Cascade connections from Master ISERDES
SHIFTIN2 => icascade2,-- Cascade connections from Master ISERDES
BITSLIP => pBitslip, -- 1-bit Invoke Bitslip. This can be used with any
CE1 => '1', -- 1-bit Clock enable input
CE2 => '1', -- 1-bit Clock enable input
CLK => SerialClk, -- Fast Source Synchronous SERDES clock from BUFIO
CLKB => SerialClkInv, -- Locally inverted clock
CLKDIV => PixelClk, -- Slow clock driven by BUFR
CLKDIVP => '0', --Not used here
D => '0',
DDLY => '0', -- not used in cascaded Slave mode
RST => aRst, -- 1-bit Asynchronous reset only.
-- unused connections
DYNCLKDIVSEL => '0',
DYNCLKSEL => '0',
OFB => '0',
OCLK => '0',
OCLKB => '0',
O => open); -- unregistered output of ISERDESE1
-------------------------------------------------------------
-- Concatenate the serdes outputs together. Keep the timesliced
-- bits together, and placing the earliest bits on the right
-- ie, if data comes in 0, 1, 2, 3, 4, 5, 6, 7, ...
-- the output will be 3210, 7654, ...
-------------------------------------------------------------
SliceISERDES_q: for slice_count in 0 to kParallelWidth-1 generate begin
--DVI sends least significant bit first
-- This places the first data in time on the right
pDataIn(slice_count) <= pDataIn_q(kParallelWidth-slice_count-1);
end generate SliceISERDES_q;
end Behavioral;
|
bsd-3-clause
|
yunqu/PYNQ
|
boards/ip/dvi2rgb_v1_7/src/DVI_Constants.vhd
|
26
|
3151
|
-------------------------------------------------------------------------------
--
-- File: DVI_Constants.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 8 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This package defines constants/parameters taken from the DVI specs.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
package DVI_Constants is
-- DVI Control Tokens
constant kCtlTkn0 : std_logic_vector(9 downto 0) := "1101010100";
constant kCtlTkn1 : std_logic_vector(9 downto 0) := "0010101011";
constant kCtlTkn2 : std_logic_vector(9 downto 0) := "0101010100";
constant kCtlTkn3 : std_logic_vector(9 downto 0) := "1010101011";
constant kMinTknCntForBlank : natural := 128; --tB
constant kBlankTimeoutMs : natural := 50;
end DVI_Constants;
package body DVI_Constants is
end DVI_Constants;
|
bsd-3-clause
|
freecores/yavga
|
vhdl/charmaps_ROM.vhd
|
2
|
37331
|
--------------------------------------------------------------------------------
---- ----
---- This file is part of the yaVGA project ----
---- http://www.opencores.org/?do=project&who=yavga ----
---- ----
---- Description ----
---- Implementation of yaVGA IP core ----
---- ----
---- To Do: ----
---- ----
---- ----
---- Author(s): ----
---- Sandro Amato, [email protected] ----
---- ----
--------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2009, Sandro Amato ----
---- All rights reserved. ----
---- ----
---- Redistribution and use in source and binary forms, with or without ----
---- modification, are permitted provided that the following conditions ----
---- are met: ----
---- ----
---- * Redistributions of source code must retain the above ----
---- copyright notice, this list of conditions and the ----
---- following disclaimer. ----
---- * Redistributions in binary form must reproduce the above ----
---- copyright notice, this list of conditions and the ----
---- following disclaimer in the documentation and/or other ----
---- materials provided with the distribution. ----
---- * Neither the name of SANDRO AMATO nor the names of its ----
---- contributors may be used to endorse or promote products ----
---- derived from this software without specific prior written ----
---- permission. ----
---- ----
---- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ----
---- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ----
---- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
---- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ----
---- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, ----
---- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ----
---- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ----
---- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ----
---- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ----
---- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
---- POSSIBILITY OF SUCH DAMAGE. ----
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use work.yavga_pkg.all;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity charmaps_ROM is
port (
i_EN : in std_logic; -- RAM Enable Input
i_clock : in std_logic; -- Clock
i_ADDR : in std_logic_vector(c_INTCHMAP_ADDR_BUS_W - 1 downto 0); -- 11-bit Address Input
o_DO : out std_logic_vector(c_INTCHMAP_DATA_BUS_W - 1 downto 0) -- 8-bit Data Output
);
end charmaps_ROM;
architecture Behavioral of charmaps_ROM is
signal s_EN : std_logic;
constant c_rom_size : natural := 2**c_INTCHMAP_ADDR_BUS_W;
type t_rom is array (c_rom_size-1 downto 0) of
std_logic_vector (c_INTCHMAP_DATA_BUS_W - 1 downto 0);
constant c_rom : t_rom := (
-- AUTOMATICALLY GENERATED... START
0 => X"00", 1 => X"00", 2 => X"00", 3 => X"00",
4 => X"00", 5 => X"00", 6 => X"00", 7 => X"00",
8 => X"00", 9 => X"00", 10 => X"00", 11 => X"00",
12 => X"00", 13 => X"00", 14 => X"00", 15 => X"00",
16 => X"00", 17 => X"00", 18 => X"00", 19 => X"FF",
20 => X"00", 21 => X"00", 22 => X"FF", 23 => X"00",
24 => X"00", 25 => X"FF", 26 => X"00", 27 => X"00",
28 => X"FF", 29 => X"00", 30 => X"00", 31 => X"00",
32 => X"00", 33 => X"00", 34 => X"FF", 35 => X"00",
36 => X"00", 37 => X"FF", 38 => X"00", 39 => X"00",
40 => X"FF", 41 => X"00", 42 => X"00", 43 => X"FF",
44 => X"00", 45 => X"00", 46 => X"00", 47 => X"00",
48 => X"00", 49 => X"00", 50 => X"24", 51 => X"24",
52 => X"24", 53 => X"24", 54 => X"24", 55 => X"24",
56 => X"24", 57 => X"24", 58 => X"24", 59 => X"24",
60 => X"24", 61 => X"24", 62 => X"00", 63 => X"00",
64 => X"00", 65 => X"00", 66 => X"49", 67 => X"49",
68 => X"49", 69 => X"49", 70 => X"49", 71 => X"49",
72 => X"49", 73 => X"49", 74 => X"49", 75 => X"49",
76 => X"49", 77 => X"49", 78 => X"00", 79 => X"00",
80 => X"00", 81 => X"00", 82 => X"92", 83 => X"92",
84 => X"92", 85 => X"92", 86 => X"92", 87 => X"92",
88 => X"92", 89 => X"92", 90 => X"92", 91 => X"92",
92 => X"92", 93 => X"92", 94 => X"00", 95 => X"00",
96 => X"00", 97 => X"00", 98 => X"55", 99 => X"55",
100 => X"55", 101 => X"55", 102 => X"55", 103 => X"55",
104 => X"55", 105 => X"55", 106 => X"55", 107 => X"55",
108 => X"55", 109 => X"55", 110 => X"00", 111 => X"00",
112 => X"00", 113 => X"00", 114 => X"AA", 115 => X"AA",
116 => X"AA", 117 => X"AA", 118 => X"AA", 119 => X"AA",
120 => X"AA", 121 => X"AA", 122 => X"AA", 123 => X"AA",
124 => X"AA", 125 => X"AA", 126 => X"00", 127 => X"00",
128 => X"00", 129 => X"00", 130 => X"00", 131 => X"FF",
132 => X"00", 133 => X"FF", 134 => X"00", 135 => X"FF",
136 => X"00", 137 => X"FF", 138 => X"00", 139 => X"FF",
140 => X"00", 141 => X"FF", 142 => X"00", 143 => X"00",
144 => X"00", 145 => X"00", 146 => X"FC", 147 => X"F3",
148 => X"FC", 149 => X"F3", 150 => X"FC", 151 => X"F3",
152 => X"FC", 153 => X"F3", 154 => X"FC", 155 => X"F3",
156 => X"FC", 157 => X"F3", 158 => X"00", 159 => X"00",
160 => X"00", 161 => X"00", 162 => X"3F", 163 => X"CF",
164 => X"3F", 165 => X"CF", 166 => X"3F", 167 => X"CF",
168 => X"3F", 169 => X"CF", 170 => X"3F", 171 => X"CF",
172 => X"3F", 173 => X"CF", 174 => X"00", 175 => X"00",
176 => X"00", 177 => X"00", 178 => X"03", 179 => X"0C",
180 => X"03", 181 => X"0C", 182 => X"03", 183 => X"0C",
184 => X"03", 185 => X"0C", 186 => X"03", 187 => X"0C",
188 => X"03", 189 => X"0C", 190 => X"00", 191 => X"00",
192 => X"00", 193 => X"00", 194 => X"C0", 195 => X"30",
196 => X"C0", 197 => X"30", 198 => X"C0", 199 => X"30",
200 => X"C0", 201 => X"30", 202 => X"C0", 203 => X"30",
204 => X"C0", 205 => X"30", 206 => X"00", 207 => X"00",
208 => X"00", 209 => X"00", 210 => X"00", 211 => X"66",
212 => X"66", 213 => X"66", 214 => X"66", 215 => X"00",
216 => X"00", 217 => X"66", 218 => X"66", 219 => X"66",
220 => X"66", 221 => X"00", 222 => X"00", 223 => X"00",
224 => X"00", 225 => X"00", 226 => X"FF", 227 => X"99",
228 => X"99", 229 => X"99", 230 => X"99", 231 => X"FF",
232 => X"FF", 233 => X"99", 234 => X"99", 235 => X"99",
236 => X"99", 237 => X"FF", 238 => X"00", 239 => X"00",
240 => X"00", 241 => X"00", 242 => X"0F", 243 => X"0F",
244 => X"0F", 245 => X"0F", 246 => X"0F", 247 => X"0F",
248 => X"0F", 249 => X"0F", 250 => X"0F", 251 => X"0F",
252 => X"0F", 253 => X"0F", 254 => X"00", 255 => X"00",
256 => X"00", 257 => X"00", 258 => X"F0", 259 => X"F0",
260 => X"F0", 261 => X"F0", 262 => X"F0", 263 => X"F0",
264 => X"F0", 265 => X"F0", 266 => X"F0", 267 => X"F0",
268 => X"F0", 269 => X"F0", 270 => X"00", 271 => X"00",
272 => X"00", 273 => X"00", 274 => X"FF", 275 => X"FF",
276 => X"FF", 277 => X"FF", 278 => X"FF", 279 => X"FF",
280 => X"00", 281 => X"00", 282 => X"00", 283 => X"00",
284 => X"00", 285 => X"00", 286 => X"00", 287 => X"00",
288 => X"00", 289 => X"00", 290 => X"00", 291 => X"00",
292 => X"00", 293 => X"00", 294 => X"00", 295 => X"00",
296 => X"FF", 297 => X"FF", 298 => X"FF", 299 => X"FF",
300 => X"FF", 301 => X"FF", 302 => X"00", 303 => X"00",
304 => X"00", 305 => X"00", 306 => X"0F", 307 => X"0F",
308 => X"0F", 309 => X"0F", 310 => X"0F", 311 => X"0F",
312 => X"0F", 313 => X"0F", 314 => X"0F", 315 => X"0F",
316 => X"0F", 317 => X"0F", 318 => X"00", 319 => X"00",
320 => X"00", 321 => X"00", 322 => X"F0", 323 => X"F0",
324 => X"F0", 325 => X"F0", 326 => X"F0", 327 => X"F0",
328 => X"F0", 329 => X"F0", 330 => X"F0", 331 => X"F0",
332 => X"F0", 333 => X"F0", 334 => X"00", 335 => X"00",
336 => X"00", 337 => X"00", 338 => X"00", 339 => X"7E",
340 => X"42", 341 => X"42", 342 => X"42", 343 => X"42",
344 => X"42", 345 => X"42", 346 => X"42", 347 => X"42",
348 => X"7E", 349 => X"00", 350 => X"00", 351 => X"00",
352 => X"00", 353 => X"00", 354 => X"FF", 355 => X"81",
356 => X"81", 357 => X"81", 358 => X"81", 359 => X"81",
360 => X"81", 361 => X"81", 362 => X"81", 363 => X"81",
364 => X"81", 365 => X"FF", 366 => X"00", 367 => X"00",
368 => X"00", 369 => X"00", 370 => X"49", 371 => X"24",
372 => X"49", 373 => X"24", 374 => X"49", 375 => X"24",
376 => X"49", 377 => X"24", 378 => X"49", 379 => X"24",
380 => X"49", 381 => X"24", 382 => X"00", 383 => X"00",
384 => X"00", 385 => X"00", 386 => X"92", 387 => X"24",
388 => X"92", 389 => X"24", 390 => X"92", 391 => X"24",
392 => X"92", 393 => X"24", 394 => X"92", 395 => X"24",
396 => X"92", 397 => X"24", 398 => X"00", 399 => X"00",
400 => X"00", 401 => X"00", 402 => X"92", 403 => X"49",
404 => X"92", 405 => X"49", 406 => X"92", 407 => X"49",
408 => X"92", 409 => X"49", 410 => X"92", 411 => X"49",
412 => X"92", 413 => X"49", 414 => X"00", 415 => X"00",
416 => X"00", 417 => X"00", 418 => X"AA", 419 => X"55",
420 => X"AA", 421 => X"55", 422 => X"AA", 423 => X"55",
424 => X"AA", 425 => X"55", 426 => X"AA", 427 => X"55",
428 => X"AA", 429 => X"55", 430 => X"00", 431 => X"00",
432 => X"00", 433 => X"00", 434 => X"55", 435 => X"AA",
436 => X"55", 437 => X"AA", 438 => X"55", 439 => X"AA",
440 => X"55", 441 => X"AA", 442 => X"55", 443 => X"AA",
444 => X"55", 445 => X"AA", 446 => X"00", 447 => X"00",
448 => X"00", 449 => X"00", 450 => X"B6", 451 => X"DB",
452 => X"B6", 453 => X"DB", 454 => X"B6", 455 => X"DB",
456 => X"B6", 457 => X"DB", 458 => X"B6", 459 => X"DB",
460 => X"B6", 461 => X"DB", 462 => X"00", 463 => X"00",
464 => X"00", 465 => X"00", 466 => X"6D", 467 => X"DB",
468 => X"6D", 469 => X"DB", 470 => X"6D", 471 => X"DB",
472 => X"6D", 473 => X"DB", 474 => X"6D", 475 => X"DB",
476 => X"6D", 477 => X"DB", 478 => X"00", 479 => X"00",
480 => X"00", 481 => X"00", 482 => X"6D", 483 => X"B6",
484 => X"6D", 485 => X"B6", 486 => X"6D", 487 => X"B6",
488 => X"6D", 489 => X"B6", 490 => X"6D", 491 => X"B6",
492 => X"6D", 493 => X"B6", 494 => X"00", 495 => X"00",
496 => X"00", 497 => X"00", 498 => X"FF", 499 => X"FF",
500 => X"FF", 501 => X"FF", 502 => X"FF", 503 => X"FF",
504 => X"FF", 505 => X"FF", 506 => X"FF", 507 => X"FF",
508 => X"FF", 509 => X"FF", 510 => X"00", 511 => X"00",
512 => X"00", 513 => X"00", 514 => X"00", 515 => X"00",
516 => X"00", 517 => X"00", 518 => X"00", 519 => X"00",
520 => X"00", 521 => X"00", 522 => X"00", 523 => X"00",
524 => X"00", 525 => X"00", 526 => X"00", 527 => X"00",
528 => X"00", 529 => X"00", 530 => X"10", 531 => X"10",
532 => X"10", 533 => X"10", 534 => X"10", 535 => X"10",
536 => X"10", 537 => X"10", 538 => X"00", 539 => X"00",
540 => X"10", 541 => X"00", 542 => X"00", 543 => X"00",
544 => X"00", 545 => X"00", 546 => X"44", 547 => X"44",
548 => X"44", 549 => X"44", 550 => X"44", 551 => X"00",
552 => X"00", 553 => X"00", 554 => X"00", 555 => X"00",
556 => X"00", 557 => X"00", 558 => X"00", 559 => X"00",
560 => X"00", 561 => X"00", 562 => X"44", 563 => X"44",
564 => X"FE", 565 => X"44", 566 => X"44", 567 => X"44",
568 => X"44", 569 => X"44", 570 => X"FE", 571 => X"44",
572 => X"44", 573 => X"00", 574 => X"00", 575 => X"00",
576 => X"00", 577 => X"00", 578 => X"7C", 579 => X"92",
580 => X"90", 581 => X"90", 582 => X"90", 583 => X"7C",
584 => X"12", 585 => X"12", 586 => X"12", 587 => X"92",
588 => X"7C", 589 => X"00", 590 => X"00", 591 => X"00",
592 => X"00", 593 => X"00", 594 => X"60", 595 => X"90",
596 => X"92", 597 => X"64", 598 => X"08", 599 => X"10",
600 => X"20", 601 => X"4C", 602 => X"92", 603 => X"12",
604 => X"0C", 605 => X"00", 606 => X"00", 607 => X"00",
608 => X"00", 609 => X"00", 610 => X"30", 611 => X"48",
612 => X"88", 613 => X"88", 614 => X"90", 615 => X"70",
616 => X"50", 617 => X"8A", 618 => X"84", 619 => X"84",
620 => X"7A", 621 => X"00", 622 => X"00", 623 => X"00",
624 => X"00", 625 => X"00", 626 => X"10", 627 => X"10",
628 => X"10", 629 => X"10", 630 => X"10", 631 => X"00",
632 => X"00", 633 => X"00", 634 => X"00", 635 => X"00",
636 => X"00", 637 => X"00", 638 => X"00", 639 => X"00",
640 => X"00", 641 => X"00", 642 => X"10", 643 => X"20",
644 => X"20", 645 => X"40", 646 => X"40", 647 => X"40",
648 => X"40", 649 => X"40", 650 => X"20", 651 => X"20",
652 => X"10", 653 => X"00", 654 => X"00", 655 => X"00",
656 => X"00", 657 => X"00", 658 => X"10", 659 => X"08",
660 => X"08", 661 => X"04", 662 => X"04", 663 => X"04",
664 => X"04", 665 => X"04", 666 => X"08", 667 => X"08",
668 => X"10", 669 => X"00", 670 => X"00", 671 => X"00",
672 => X"00", 673 => X"00", 674 => X"92", 675 => X"92",
676 => X"54", 677 => X"54", 678 => X"38", 679 => X"FE",
680 => X"38", 681 => X"54", 682 => X"54", 683 => X"92",
684 => X"92", 685 => X"00", 686 => X"00", 687 => X"00",
688 => X"00", 689 => X"00", 690 => X"00", 691 => X"10",
692 => X"10", 693 => X"10", 694 => X"10", 695 => X"FE",
696 => X"10", 697 => X"10", 698 => X"10", 699 => X"10",
700 => X"00", 701 => X"00", 702 => X"00", 703 => X"00",
704 => X"00", 705 => X"00", 706 => X"00", 707 => X"00",
708 => X"00", 709 => X"00", 710 => X"00", 711 => X"00",
712 => X"00", 713 => X"08", 714 => X"08", 715 => X"10",
716 => X"20", 717 => X"00", 718 => X"00", 719 => X"00",
720 => X"00", 721 => X"00", 722 => X"00", 723 => X"00",
724 => X"00", 725 => X"00", 726 => X"00", 727 => X"FE",
728 => X"00", 729 => X"00", 730 => X"00", 731 => X"00",
732 => X"00", 733 => X"00", 734 => X"00", 735 => X"00",
736 => X"00", 737 => X"00", 738 => X"00", 739 => X"00",
740 => X"00", 741 => X"00", 742 => X"00", 743 => X"00",
744 => X"00", 745 => X"18", 746 => X"18", 747 => X"00",
748 => X"00", 749 => X"00", 750 => X"00", 751 => X"00",
752 => X"00", 753 => X"00", 754 => X"00", 755 => X"00",
756 => X"02", 757 => X"04", 758 => X"08", 759 => X"10",
760 => X"20", 761 => X"40", 762 => X"80", 763 => X"00",
764 => X"00", 765 => X"00", 766 => X"00", 767 => X"00",
768 => X"00", 769 => X"00", 770 => X"38", 771 => X"44",
772 => X"82", 773 => X"82", 774 => X"8A", 775 => X"92",
776 => X"A2", 777 => X"82", 778 => X"82", 779 => X"44",
780 => X"38", 781 => X"00", 782 => X"00", 783 => X"00",
784 => X"00", 785 => X"00", 786 => X"10", 787 => X"30",
788 => X"50", 789 => X"10", 790 => X"10", 791 => X"10",
792 => X"10", 793 => X"10", 794 => X"10", 795 => X"10",
796 => X"38", 797 => X"00", 798 => X"00", 799 => X"00",
800 => X"00", 801 => X"00", 802 => X"7C", 803 => X"82",
804 => X"02", 805 => X"02", 806 => X"02", 807 => X"7C",
808 => X"80", 809 => X"80", 810 => X"80", 811 => X"80",
812 => X"FE", 813 => X"00", 814 => X"00", 815 => X"00",
816 => X"00", 817 => X"00", 818 => X"7C", 819 => X"82",
820 => X"02", 821 => X"02", 822 => X"02", 823 => X"7C",
824 => X"02", 825 => X"02", 826 => X"02", 827 => X"82",
828 => X"7C", 829 => X"00", 830 => X"00", 831 => X"00",
832 => X"00", 833 => X"00", 834 => X"08", 835 => X"18",
836 => X"28", 837 => X"48", 838 => X"88", 839 => X"88",
840 => X"FE", 841 => X"08", 842 => X"08", 843 => X"08",
844 => X"1C", 845 => X"00", 846 => X"00", 847 => X"00",
848 => X"00", 849 => X"00", 850 => X"FE", 851 => X"80",
852 => X"80", 853 => X"80", 854 => X"80", 855 => X"7C",
856 => X"02", 857 => X"02", 858 => X"02", 859 => X"82",
860 => X"7C", 861 => X"00", 862 => X"00", 863 => X"00",
864 => X"00", 865 => X"00", 866 => X"7E", 867 => X"80",
868 => X"80", 869 => X"80", 870 => X"80", 871 => X"7C",
872 => X"82", 873 => X"82", 874 => X"82", 875 => X"82",
876 => X"7C", 877 => X"00", 878 => X"00", 879 => X"00",
880 => X"00", 881 => X"00", 882 => X"FE", 883 => X"02",
884 => X"02", 885 => X"04", 886 => X"08", 887 => X"10",
888 => X"10", 889 => X"10", 890 => X"10", 891 => X"10",
892 => X"38", 893 => X"00", 894 => X"00", 895 => X"00",
896 => X"00", 897 => X"00", 898 => X"7C", 899 => X"82",
900 => X"82", 901 => X"82", 902 => X"82", 903 => X"7C",
904 => X"82", 905 => X"82", 906 => X"82", 907 => X"82",
908 => X"7C", 909 => X"00", 910 => X"00", 911 => X"00",
912 => X"00", 913 => X"00", 914 => X"7C", 915 => X"82",
916 => X"82", 917 => X"82", 918 => X"82", 919 => X"7C",
920 => X"02", 921 => X"02", 922 => X"02", 923 => X"02",
924 => X"FC", 925 => X"00", 926 => X"00", 927 => X"00",
928 => X"00", 929 => X"00", 930 => X"00", 931 => X"00",
932 => X"18", 933 => X"18", 934 => X"00", 935 => X"00",
936 => X"00", 937 => X"18", 938 => X"18", 939 => X"00",
940 => X"00", 941 => X"00", 942 => X"00", 943 => X"00",
944 => X"00", 945 => X"00", 946 => X"00", 947 => X"00",
948 => X"18", 949 => X"18", 950 => X"00", 951 => X"00",
952 => X"00", 953 => X"08", 954 => X"08", 955 => X"10",
956 => X"20", 957 => X"00", 958 => X"00", 959 => X"00",
960 => X"00", 961 => X"00", 962 => X"00", 963 => X"00",
964 => X"02", 965 => X"0C", 966 => X"30", 967 => X"C0",
968 => X"30", 969 => X"0C", 970 => X"02", 971 => X"00",
972 => X"00", 973 => X"00", 974 => X"00", 975 => X"00",
976 => X"00", 977 => X"00", 978 => X"00", 979 => X"00",
980 => X"FE", 981 => X"00", 982 => X"00", 983 => X"00",
984 => X"00", 985 => X"00", 986 => X"FE", 987 => X"00",
988 => X"00", 989 => X"00", 990 => X"00", 991 => X"00",
992 => X"00", 993 => X"00", 994 => X"00", 995 => X"00",
996 => X"80", 997 => X"60", 998 => X"18", 999 => X"06",
1000 => X"18", 1001 => X"60", 1002 => X"80", 1003 => X"00",
1004 => X"00", 1005 => X"00", 1006 => X"00", 1007 => X"00",
1008 => X"00", 1009 => X"00", 1010 => X"38", 1011 => X"44",
1012 => X"82", 1013 => X"82", 1014 => X"02", 1015 => X"04",
1016 => X"08", 1017 => X"10", 1018 => X"10", 1019 => X"00",
1020 => X"10", 1021 => X"00", 1022 => X"00", 1023 => X"00",
1024 => X"00", 1025 => X"00", 1026 => X"38", 1027 => X"44",
1028 => X"82", 1029 => X"82", 1030 => X"9E", 1031 => X"A2",
1032 => X"A2", 1033 => X"9E", 1034 => X"80", 1035 => X"42",
1036 => X"3C", 1037 => X"00", 1038 => X"00", 1039 => X"00",
1040 => X"00", 1041 => X"00", 1042 => X"10", 1043 => X"28",
1044 => X"28", 1045 => X"28", 1046 => X"44", 1047 => X"7C",
1048 => X"44", 1049 => X"44", 1050 => X"82", 1051 => X"82",
1052 => X"82", 1053 => X"00", 1054 => X"00", 1055 => X"00",
1056 => X"00", 1057 => X"00", 1058 => X"FC", 1059 => X"82",
1060 => X"82", 1061 => X"82", 1062 => X"84", 1063 => X"F8",
1064 => X"84", 1065 => X"82", 1066 => X"82", 1067 => X"82",
1068 => X"FC", 1069 => X"00", 1070 => X"00", 1071 => X"00",
1072 => X"00", 1073 => X"00", 1074 => X"7C", 1075 => X"82",
1076 => X"80", 1077 => X"80", 1078 => X"80", 1079 => X"80",
1080 => X"80", 1081 => X"80", 1082 => X"80", 1083 => X"82",
1084 => X"7C", 1085 => X"00", 1086 => X"00", 1087 => X"00",
1088 => X"00", 1089 => X"00", 1090 => X"F0", 1091 => X"88",
1092 => X"84", 1093 => X"84", 1094 => X"82", 1095 => X"82",
1096 => X"82", 1097 => X"82", 1098 => X"84", 1099 => X"84",
1100 => X"F8", 1101 => X"00", 1102 => X"00", 1103 => X"00",
1104 => X"00", 1105 => X"00", 1106 => X"FE", 1107 => X"80",
1108 => X"80", 1109 => X"80", 1110 => X"80", 1111 => X"FC",
1112 => X"80", 1113 => X"80", 1114 => X"80", 1115 => X"80",
1116 => X"FE", 1117 => X"00", 1118 => X"00", 1119 => X"00",
1120 => X"00", 1121 => X"00", 1122 => X"FE", 1123 => X"80",
1124 => X"80", 1125 => X"80", 1126 => X"80", 1127 => X"FC",
1128 => X"80", 1129 => X"80", 1130 => X"80", 1131 => X"80",
1132 => X"80", 1133 => X"00", 1134 => X"00", 1135 => X"00",
1136 => X"00", 1137 => X"00", 1138 => X"7C", 1139 => X"82",
1140 => X"80", 1141 => X"80", 1142 => X"80", 1143 => X"9E",
1144 => X"82", 1145 => X"82", 1146 => X"82", 1147 => X"82",
1148 => X"7C", 1149 => X"00", 1150 => X"00", 1151 => X"00",
1152 => X"00", 1153 => X"00", 1154 => X"82", 1155 => X"82",
1156 => X"82", 1157 => X"82", 1158 => X"82", 1159 => X"7C",
1160 => X"82", 1161 => X"82", 1162 => X"82", 1163 => X"82",
1164 => X"82", 1165 => X"00", 1166 => X"00", 1167 => X"00",
1168 => X"00", 1169 => X"00", 1170 => X"38", 1171 => X"10",
1172 => X"10", 1173 => X"10", 1174 => X"10", 1175 => X"10",
1176 => X"10", 1177 => X"10", 1178 => X"10", 1179 => X"10",
1180 => X"38", 1181 => X"00", 1182 => X"00", 1183 => X"00",
1184 => X"00", 1185 => X"00", 1186 => X"1C", 1187 => X"08",
1188 => X"08", 1189 => X"08", 1190 => X"08", 1191 => X"08",
1192 => X"08", 1193 => X"08", 1194 => X"88", 1195 => X"88",
1196 => X"70", 1197 => X"00", 1198 => X"00", 1199 => X"00",
1200 => X"00", 1201 => X"00", 1202 => X"82", 1203 => X"82",
1204 => X"84", 1205 => X"84", 1206 => X"88", 1207 => X"F0",
1208 => X"88", 1209 => X"84", 1210 => X"84", 1211 => X"82",
1212 => X"82", 1213 => X"00", 1214 => X"00", 1215 => X"00",
1216 => X"00", 1217 => X"00", 1218 => X"80", 1219 => X"80",
1220 => X"80", 1221 => X"80", 1222 => X"80", 1223 => X"80",
1224 => X"80", 1225 => X"80", 1226 => X"80", 1227 => X"80",
1228 => X"FE", 1229 => X"00", 1230 => X"00", 1231 => X"00",
1232 => X"00", 1233 => X"00", 1234 => X"82", 1235 => X"C6",
1236 => X"AA", 1237 => X"AA", 1238 => X"AA", 1239 => X"92",
1240 => X"92", 1241 => X"82", 1242 => X"82", 1243 => X"82",
1244 => X"82", 1245 => X"00", 1246 => X"00", 1247 => X"00",
1248 => X"00", 1249 => X"00", 1250 => X"82", 1251 => X"C2",
1252 => X"A2", 1253 => X"A2", 1254 => X"A2", 1255 => X"92",
1256 => X"8A", 1257 => X"8A", 1258 => X"8A", 1259 => X"86",
1260 => X"82", 1261 => X"00", 1262 => X"00", 1263 => X"00",
1264 => X"00", 1265 => X"00", 1266 => X"7C", 1267 => X"82",
1268 => X"82", 1269 => X"82", 1270 => X"82", 1271 => X"82",
1272 => X"82", 1273 => X"82", 1274 => X"82", 1275 => X"82",
1276 => X"7C", 1277 => X"00", 1278 => X"00", 1279 => X"00",
1280 => X"00", 1281 => X"00", 1282 => X"7C", 1283 => X"82",
1284 => X"82", 1285 => X"82", 1286 => X"82", 1287 => X"FC",
1288 => X"80", 1289 => X"80", 1290 => X"80", 1291 => X"80",
1292 => X"80", 1293 => X"00", 1294 => X"00", 1295 => X"00",
1296 => X"00", 1297 => X"00", 1298 => X"7C", 1299 => X"82",
1300 => X"82", 1301 => X"82", 1302 => X"82", 1303 => X"82",
1304 => X"82", 1305 => X"B2", 1306 => X"8A", 1307 => X"84",
1308 => X"7A", 1309 => X"00", 1310 => X"00", 1311 => X"00",
1312 => X"00", 1313 => X"00", 1314 => X"7C", 1315 => X"82",
1316 => X"82", 1317 => X"82", 1318 => X"82", 1319 => X"FC",
1320 => X"A0", 1321 => X"90", 1322 => X"88", 1323 => X"84",
1324 => X"82", 1325 => X"00", 1326 => X"00", 1327 => X"00",
1328 => X"00", 1329 => X"00", 1330 => X"7C", 1331 => X"82",
1332 => X"80", 1333 => X"80", 1334 => X"80", 1335 => X"7C",
1336 => X"02", 1337 => X"02", 1338 => X"02", 1339 => X"82",
1340 => X"7C", 1341 => X"00", 1342 => X"00", 1343 => X"00",
1344 => X"00", 1345 => X"00", 1346 => X"FE", 1347 => X"92",
1348 => X"10", 1349 => X"10", 1350 => X"10", 1351 => X"10",
1352 => X"10", 1353 => X"10", 1354 => X"10", 1355 => X"10",
1356 => X"10", 1357 => X"00", 1358 => X"00", 1359 => X"00",
1360 => X"00", 1361 => X"00", 1362 => X"82", 1363 => X"82",
1364 => X"82", 1365 => X"82", 1366 => X"82", 1367 => X"82",
1368 => X"82", 1369 => X"82", 1370 => X"82", 1371 => X"82",
1372 => X"7C", 1373 => X"00", 1374 => X"00", 1375 => X"00",
1376 => X"00", 1377 => X"00", 1378 => X"82", 1379 => X"82",
1380 => X"82", 1381 => X"44", 1382 => X"44", 1383 => X"44",
1384 => X"28", 1385 => X"28", 1386 => X"28", 1387 => X"10",
1388 => X"10", 1389 => X"00", 1390 => X"00", 1391 => X"00",
1392 => X"00", 1393 => X"00", 1394 => X"82", 1395 => X"82",
1396 => X"82", 1397 => X"82", 1398 => X"92", 1399 => X"92",
1400 => X"AA", 1401 => X"AA", 1402 => X"AA", 1403 => X"C6",
1404 => X"82", 1405 => X"00", 1406 => X"00", 1407 => X"00",
1408 => X"00", 1409 => X"00", 1410 => X"82", 1411 => X"82",
1412 => X"44", 1413 => X"44", 1414 => X"28", 1415 => X"38",
1416 => X"28", 1417 => X"44", 1418 => X"44", 1419 => X"82",
1420 => X"82", 1421 => X"00", 1422 => X"00", 1423 => X"00",
1424 => X"00", 1425 => X"00", 1426 => X"82", 1427 => X"82",
1428 => X"44", 1429 => X"44", 1430 => X"28", 1431 => X"28",
1432 => X"10", 1433 => X"10", 1434 => X"10", 1435 => X"10",
1436 => X"10", 1437 => X"00", 1438 => X"00", 1439 => X"00",
1440 => X"00", 1441 => X"00", 1442 => X"FE", 1443 => X"82",
1444 => X"04", 1445 => X"04", 1446 => X"08", 1447 => X"38",
1448 => X"20", 1449 => X"40", 1450 => X"40", 1451 => X"82",
1452 => X"FE", 1453 => X"00", 1454 => X"00", 1455 => X"00",
1456 => X"00", 1457 => X"00", 1458 => X"38", 1459 => X"20",
1460 => X"20", 1461 => X"20", 1462 => X"20", 1463 => X"20",
1464 => X"20", 1465 => X"20", 1466 => X"20", 1467 => X"20",
1468 => X"38", 1469 => X"00", 1470 => X"00", 1471 => X"00",
1472 => X"00", 1473 => X"00", 1474 => X"00", 1475 => X"00",
1476 => X"80", 1477 => X"40", 1478 => X"20", 1479 => X"10",
1480 => X"08", 1481 => X"04", 1482 => X"02", 1483 => X"00",
1484 => X"00", 1485 => X"00", 1486 => X"00", 1487 => X"00",
1488 => X"00", 1489 => X"00", 1490 => X"38", 1491 => X"08",
1492 => X"08", 1493 => X"08", 1494 => X"08", 1495 => X"08",
1496 => X"08", 1497 => X"08", 1498 => X"08", 1499 => X"08",
1500 => X"38", 1501 => X"00", 1502 => X"00", 1503 => X"00",
1504 => X"00", 1505 => X"00", 1506 => X"00", 1507 => X"10",
1508 => X"28", 1509 => X"44", 1510 => X"82", 1511 => X"00",
1512 => X"00", 1513 => X"00", 1514 => X"00", 1515 => X"00",
1516 => X"00", 1517 => X"00", 1518 => X"00", 1519 => X"00",
1520 => X"00", 1521 => X"00", 1522 => X"00", 1523 => X"00",
1524 => X"00", 1525 => X"00", 1526 => X"00", 1527 => X"00",
1528 => X"00", 1529 => X"00", 1530 => X"00", 1531 => X"00",
1532 => X"FE", 1533 => X"00", 1534 => X"00", 1535 => X"00",
1536 => X"00", 1537 => X"00", 1538 => X"20", 1539 => X"20",
1540 => X"10", 1541 => X"10", 1542 => X"08", 1543 => X"00",
1544 => X"00", 1545 => X"00", 1546 => X"00", 1547 => X"00",
1548 => X"00", 1549 => X"00", 1550 => X"00", 1551 => X"00",
1552 => X"00", 1553 => X"00", 1554 => X"00", 1555 => X"00",
1556 => X"00", 1557 => X"00", 1558 => X"3A", 1559 => X"C6",
1560 => X"82", 1561 => X"82", 1562 => X"82", 1563 => X"C6",
1564 => X"3A", 1565 => X"00", 1566 => X"00", 1567 => X"00",
1568 => X"00", 1569 => X"00", 1570 => X"80", 1571 => X"80",
1572 => X"80", 1573 => X"80", 1574 => X"B8", 1575 => X"C6",
1576 => X"82", 1577 => X"82", 1578 => X"82", 1579 => X"C6",
1580 => X"B8", 1581 => X"00", 1582 => X"00", 1583 => X"00",
1584 => X"00", 1585 => X"00", 1586 => X"00", 1587 => X"00",
1588 => X"00", 1589 => X"00", 1590 => X"3C", 1591 => X"C2",
1592 => X"80", 1593 => X"80", 1594 => X"80", 1595 => X"C2",
1596 => X"3C", 1597 => X"00", 1598 => X"00", 1599 => X"00",
1600 => X"00", 1601 => X"00", 1602 => X"02", 1603 => X"02",
1604 => X"02", 1605 => X"02", 1606 => X"3A", 1607 => X"C6",
1608 => X"82", 1609 => X"82", 1610 => X"82", 1611 => X"C6",
1612 => X"3A", 1613 => X"00", 1614 => X"00", 1615 => X"00",
1616 => X"00", 1617 => X"00", 1618 => X"00", 1619 => X"00",
1620 => X"00", 1621 => X"00", 1622 => X"38", 1623 => X"C6",
1624 => X"82", 1625 => X"FC", 1626 => X"80", 1627 => X"C6",
1628 => X"38", 1629 => X"00", 1630 => X"00", 1631 => X"00",
1632 => X"00", 1633 => X"00", 1634 => X"3C", 1635 => X"42",
1636 => X"80", 1637 => X"80", 1638 => X"F8", 1639 => X"80",
1640 => X"80", 1641 => X"80", 1642 => X"80", 1643 => X"80",
1644 => X"80", 1645 => X"00", 1646 => X"00", 1647 => X"00",
1648 => X"00", 1649 => X"00", 1650 => X"00", 1651 => X"00",
1652 => X"00", 1653 => X"00", 1654 => X"38", 1655 => X"C6",
1656 => X"82", 1657 => X"7E", 1658 => X"02", 1659 => X"C6",
1660 => X"38", 1661 => X"00", 1662 => X"00", 1663 => X"00",
1664 => X"00", 1665 => X"00", 1666 => X"80", 1667 => X"80",
1668 => X"80", 1669 => X"80", 1670 => X"B8", 1671 => X"C6",
1672 => X"82", 1673 => X"82", 1674 => X"82", 1675 => X"82",
1676 => X"82", 1677 => X"00", 1678 => X"00", 1679 => X"00",
1680 => X"00", 1681 => X"00", 1682 => X"00", 1683 => X"10",
1684 => X"00", 1685 => X"00", 1686 => X"10", 1687 => X"10",
1688 => X"10", 1689 => X"10", 1690 => X"10", 1691 => X"12",
1692 => X"0C", 1693 => X"00", 1694 => X"00", 1695 => X"00",
1696 => X"00", 1697 => X"00", 1698 => X"00", 1699 => X"04",
1700 => X"00", 1701 => X"00", 1702 => X"04", 1703 => X"04",
1704 => X"04", 1705 => X"04", 1706 => X"04", 1707 => X"88",
1708 => X"70", 1709 => X"00", 1710 => X"00", 1711 => X"00",
1712 => X"00", 1713 => X"00", 1714 => X"00", 1715 => X"80",
1716 => X"80", 1717 => X"80", 1718 => X"86", 1719 => X"B8",
1720 => X"C0", 1721 => X"B0", 1722 => X"88", 1723 => X"84",
1724 => X"82", 1725 => X"00", 1726 => X"00", 1727 => X"00",
1728 => X"00", 1729 => X"00", 1730 => X"20", 1731 => X"20",
1732 => X"20", 1733 => X"20", 1734 => X"20", 1735 => X"20",
1736 => X"20", 1737 => X"20", 1738 => X"20", 1739 => X"10",
1740 => X"0E", 1741 => X"00", 1742 => X"00", 1743 => X"00",
1744 => X"00", 1745 => X"00", 1746 => X"00", 1747 => X"00",
1748 => X"00", 1749 => X"00", 1750 => X"AC", 1751 => X"D2",
1752 => X"92", 1753 => X"92", 1754 => X"92", 1755 => X"92",
1756 => X"92", 1757 => X"00", 1758 => X"00", 1759 => X"00",
1760 => X"00", 1761 => X"00", 1762 => X"00", 1763 => X"00",
1764 => X"00", 1765 => X"00", 1766 => X"B8", 1767 => X"C6",
1768 => X"82", 1769 => X"82", 1770 => X"82", 1771 => X"82",
1772 => X"82", 1773 => X"00", 1774 => X"00", 1775 => X"00",
1776 => X"00", 1777 => X"00", 1778 => X"00", 1779 => X"00",
1780 => X"00", 1781 => X"00", 1782 => X"38", 1783 => X"C6",
1784 => X"82", 1785 => X"82", 1786 => X"82", 1787 => X"C6",
1788 => X"38", 1789 => X"00", 1790 => X"00", 1791 => X"00",
1792 => X"00", 1793 => X"00", 1794 => X"00", 1795 => X"00",
1796 => X"00", 1797 => X"00", 1798 => X"B8", 1799 => X"C6",
1800 => X"82", 1801 => X"FC", 1802 => X"80", 1803 => X"80",
1804 => X"80", 1805 => X"00", 1806 => X"00", 1807 => X"00",
1808 => X"00", 1809 => X"00", 1810 => X"00", 1811 => X"00",
1812 => X"00", 1813 => X"00", 1814 => X"3A", 1815 => X"C6",
1816 => X"82", 1817 => X"7E", 1818 => X"02", 1819 => X"02",
1820 => X"02", 1821 => X"00", 1822 => X"00", 1823 => X"00",
1824 => X"00", 1825 => X"00", 1826 => X"00", 1827 => X"00",
1828 => X"00", 1829 => X"00", 1830 => X"B8", 1831 => X"C6",
1832 => X"80", 1833 => X"80", 1834 => X"80", 1835 => X"80",
1836 => X"80", 1837 => X"00", 1838 => X"00", 1839 => X"00",
1840 => X"00", 1841 => X"00", 1842 => X"00", 1843 => X"00",
1844 => X"00", 1845 => X"00", 1846 => X"7C", 1847 => X"82",
1848 => X"80", 1849 => X"7E", 1850 => X"02", 1851 => X"82",
1852 => X"7C", 1853 => X"00", 1854 => X"00", 1855 => X"00",
1856 => X"00", 1857 => X"00", 1858 => X"80", 1859 => X"80",
1860 => X"80", 1861 => X"80", 1862 => X"F8", 1863 => X"80",
1864 => X"80", 1865 => X"80", 1866 => X"80", 1867 => X"42",
1868 => X"3C", 1869 => X"00", 1870 => X"00", 1871 => X"00",
1872 => X"00", 1873 => X"00", 1874 => X"00", 1875 => X"00",
1876 => X"00", 1877 => X"00", 1878 => X"82", 1879 => X"82",
1880 => X"82", 1881 => X"82", 1882 => X"82", 1883 => X"C6",
1884 => X"3A", 1885 => X"00", 1886 => X"00", 1887 => X"00",
1888 => X"00", 1889 => X"00", 1890 => X"00", 1891 => X"00",
1892 => X"00", 1893 => X"00", 1894 => X"82", 1895 => X"82",
1896 => X"82", 1897 => X"82", 1898 => X"44", 1899 => X"28",
1900 => X"10", 1901 => X"00", 1902 => X"00", 1903 => X"00",
1904 => X"00", 1905 => X"00", 1906 => X"00", 1907 => X"00",
1908 => X"00", 1909 => X"00", 1910 => X"82", 1911 => X"92",
1912 => X"92", 1913 => X"92", 1914 => X"92", 1915 => X"92",
1916 => X"6C", 1917 => X"00", 1918 => X"00", 1919 => X"00",
1920 => X"00", 1921 => X"00", 1922 => X"00", 1923 => X"00",
1924 => X"00", 1925 => X"00", 1926 => X"00", 1927 => X"82",
1928 => X"44", 1929 => X"28", 1930 => X"38", 1931 => X"44",
1932 => X"82", 1933 => X"00", 1934 => X"00", 1935 => X"00",
1936 => X"00", 1937 => X"00", 1938 => X"00", 1939 => X"00",
1940 => X"00", 1941 => X"00", 1942 => X"00", 1943 => X"82",
1944 => X"42", 1945 => X"3C", 1946 => X"08", 1947 => X"08",
1948 => X"30", 1949 => X"00", 1950 => X"00", 1951 => X"00",
1952 => X"00", 1953 => X"00", 1954 => X"00", 1955 => X"00",
1956 => X"00", 1957 => X"00", 1958 => X"00", 1959 => X"FE",
1960 => X"04", 1961 => X"08", 1962 => X"30", 1963 => X"40",
1964 => X"FE", 1965 => X"00", 1966 => X"00", 1967 => X"00",
1968 => X"00", 1969 => X"00", 1970 => X"10", 1971 => X"20",
1972 => X"20", 1973 => X"20", 1974 => X"40", 1975 => X"80",
1976 => X"40", 1977 => X"20", 1978 => X"20", 1979 => X"20",
1980 => X"10", 1981 => X"00", 1982 => X"00", 1983 => X"00",
1984 => X"00", 1985 => X"00", 1986 => X"10", 1987 => X"10",
1988 => X"10", 1989 => X"10", 1990 => X"10", 1991 => X"10",
1992 => X"10", 1993 => X"10", 1994 => X"10", 1995 => X"10",
1996 => X"10", 1997 => X"00", 1998 => X"00", 1999 => X"00",
2000 => X"00", 2001 => X"00", 2002 => X"10", 2003 => X"08",
2004 => X"08", 2005 => X"08", 2006 => X"04", 2007 => X"02",
2008 => X"04", 2009 => X"08", 2010 => X"08", 2011 => X"08",
2012 => X"10", 2013 => X"00", 2014 => X"00", 2015 => X"00",
2016 => X"00", 2017 => X"00", 2018 => X"00", 2019 => X"00",
2020 => X"00", 2021 => X"00", 2022 => X"60", 2023 => X"92",
2024 => X"0C", 2025 => X"00", 2026 => X"00", 2027 => X"00",
2028 => X"00", 2029 => X"00", 2030 => X"00", 2031 => X"00",
2032 => X"00", 2033 => X"00", 2034 => X"00", 2035 => X"00",
2036 => X"00", 2037 => X"00", 2038 => X"00", 2039 => X"00",
2040 => X"00", 2041 => X"00", 2042 => X"00", 2043 => X"00",
2044 => X"00", 2045 => X"00", 2046 => X"00", 2047 => X"00",
others => X"00"
-- AUTOMATICALLY GENERATED... STOP
);
begin
s_EN <= i_EN;
p_rom : process (i_clock)
begin
if rising_edge(i_clock) then
if s_EN = '1' then
o_DO <= c_rom(conv_integer(i_ADDR));
end if;
end if;
end process p_rom;
end Behavioral;
|
bsd-3-clause
|
wende/alchemide
|
demo/kitchen-sink/docs/vhdl.vhd
|
472
|
830
|
library IEEE
user IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity COUNT16 is
port (
cOut :out std_logic_vector(15 downto 0); -- counter output
clkEn :in std_logic; -- count enable
clk :in std_logic; -- clock input
rst :in std_logic -- reset input
);
end entity;
architecture count_rtl of COUNT16 is
signal count :std_logic_vector (15 downto 0);
begin
process (clk, rst) begin
if(rst = '1') then
count <= (others=>'0');
elsif(rising_edge(clk)) then
if(clkEn = '1') then
count <= count + 1;
end if;
end if;
end process;
cOut <= count;
end architecture;
|
bsd-3-clause
|
Rogiel/BananaCore
|
Source/Instruction/Executor/JumpIfCarryInstructionExecutor.vhd
|
1
|
3698
|
--
-- BananaCore - A processor written in VHDL
--
-- Created by Rogiel Sulzbach.
-- Copyright (c) 2014-2015 Rogiel Sulzbach. All rights reserved.
--
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_1164.std_logic;
library BananaCore;
use BananaCore.Core.all;
use BananaCore.Memory.all;
use BananaCore.RegisterPackage.all;
-- The JumpIfCarryInstructionExecutor entity
entity JumpIfCarryInstructionExecutor is
port(
-- the processor main clock
clock: in BananaCore.Core.Clock;
-- enables the instruction
enable: in std_logic;
-- the first register to operate on (argument 0)
arg0_address: in MemoryAddress;
-- a bus indicating if the instruction is ready or not
instruction_ready: out std_logic := '0';
------------------------------------------
-- MEMORY BUS
------------------------------------------
-- the address to read/write memory from/to
memory_address: out MemoryAddress := (others => '0');
-- the memory being read to
memory_data_read: in MemoryData;
-- the memory being written to
memory_data_write: out MemoryData := (others => '0');
-- the operation to perform on the memory
memory_operation: out MemoryOperation := MEMORY_OP_DISABLED;
-- a flag indicating if a memory operation should be performed
memory_enable: out std_logic := '0';
-- a flag indicating if a memory operation has completed
memory_ready: in std_logic;
------------------------------------------
-- REGISTER BUS
------------------------------------------
-- the processor register address bus
register_address: out RegisterAddress := (others => '0');
-- the processor register data bus
register_data_read: in RegisterData;
-- the processor register data bus
register_data_write: out RegisterData := (others => '0');
-- the processor register operation signal
register_operation: out RegisterOperation := OP_REG_DISABLED;
-- the processor register enable signal
register_enable: out std_logic := '0';
-- a flag indicating if a register operation has completed
register_ready: in std_logic;
------------------------------------------
-- PROGRAM COUNTER
------------------------------------------
-- the program counter new value
program_counter: out MemoryAddress;
-- the program counter set flag
program_counter_set: out std_logic := '0'
);
end JumpIfCarryInstructionExecutor;
architecture JumpIfCarryInstructionExecutorImpl of JumpIfCarryInstructionExecutor is
type state_type is (
fetch_control_register,
store_control_register,
execute,
complete
);
signal state: state_type := fetch_control_register;
signal arg0: RegisterData;
begin
process (clock) begin
if clock'event and clock = '1' then
if enable = '1' then
case state is
when fetch_control_register =>
instruction_ready <= '0';
register_address <= SpecialRegister;
register_operation <= OP_REG_GET;
register_enable <= '1';
state <= store_control_register;
when store_control_register =>
if register_ready = '1' then
arg0 <= register_data_read;
register_enable <= '0';
state <= execute;
else
state <= store_control_register;
end if;
when execute =>
if arg0(CarryBit) = '1' then
program_counter <= arg0_address;
program_counter_set <= '1';
end if;
state <= complete;
when complete =>
instruction_ready <= '1';
state <= complete;
end case;
else
instruction_ready <= '0';
program_counter_set <= '0';
state <= fetch_control_register;
end if;
end if;
end process;
end JumpIfCarryInstructionExecutorImpl;
|
bsd-3-clause
|
tau-tao/FPGAIPFilter
|
FPGA_CODE/JTAG_RW_PKT_PROC/counter_div.vhd
|
2
|
685
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter_div is
generic
( OFFSET : integer
; BIT_WIDTH : integer
);
port
( clk : in std_logic
; counter_out : out std_logic_vector((BIT_WIDTH - 1) downto 0)
);
end entity counter_div;
architecture rtl of counter_div is
signal counter_data : std_logic_vector(31 downto 0) := (others => '0');
begin
process(clk)
begin
if rising_edge(clk) then
counter_data <= std_logic_vector(unsigned(counter_data) + 1);
end if;
end process;
counter_out <= counter_data((OFFSET + BIT_WIDTH - 1) downto OFFSET);
end architecture rtl;
|
bsd-3-clause
|
Rogiel/BananaCore
|
Source/Instruction/Executor/BitwiseXorInstructionExecutor.vhd
|
1
|
3970
|
--
-- BananaCore - A processor written in VHDL
--
-- Created by Rogiel Sulzbach.
-- Copyright (c) 2014-2015 Rogiel Sulzbach. All rights reserved.
--
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_1164.std_logic;
library BananaCore;
use BananaCore.Core.all;
use BananaCore.Memory.all;
use BananaCore.RegisterPackage.all;
-- The BitwiseXorInstructionExecutor entity
entity BitwiseXorInstructionExecutor is
port(
-- the processor main clock
clock: in BananaCore.Core.Clock;
-- enables the instruction
enable: in std_logic;
-- the first register to operate on (argument 0)
arg0_address: in RegisterAddress;
-- the first register to operate on (argument 1)
arg1_address: in RegisterAddress;
-- a bus indicating if the instruction is ready or not
instruction_ready: out std_logic := '0';
------------------------------------------
-- MEMORY BUS
------------------------------------------
-- the address to read/write memory from/to
memory_address: out MemoryAddress := (others => '0');
-- the memory being read to
memory_data_read: in MemoryData;
-- the memory being written to
memory_data_write: out MemoryData := (others => '0');
-- the operation to perform on the memory
memory_operation: out MemoryOperation := MEMORY_OP_DISABLED;
-- a flag indicating if a memory operation should be performed
memory_enable: out std_logic;
-- a flag indicating if a memory operation has completed
memory_ready: in std_logic;
------------------------------------------
-- REGISTER BUS
------------------------------------------
-- the processor register address bus
register_address: out RegisterAddress := (others => '0');
-- the processor register data bus
register_data_read: in RegisterData;
-- the processor register data bus
register_data_write: out RegisterData := (others => '0');
-- the processor register operation signal
register_operation: out RegisterOperation := OP_REG_DISABLED;
-- the processor register enable signal
register_enable: out std_logic := '0';
-- a flag indicating if a register operation has completed
register_ready: in std_logic
);
end BitwiseXorInstructionExecutor;
architecture BitwiseXorInstructionExecutorImpl of BitwiseXorInstructionExecutor is
type state_type is (
fetch_arg0,
store_arg0,
fetch_arg1,
store_arg1,
execute,
store_result,
complete
);
signal state: state_type := fetch_arg0;
signal arg0: RegisterData;
signal arg1: RegisterData;
signal result: RegisterData;
begin
process (clock) begin
if clock'event and clock = '1' then
if enable = '1' then
case state is
when fetch_arg0 =>
instruction_ready <= '0';
register_address <= arg0_address;
register_operation <= OP_REG_GET;
register_enable <= '1';
state <= store_arg0;
when store_arg0 =>
if register_ready = '1' then
arg0 <= register_data_read;
register_enable <= '0';
state <= fetch_arg1;
else
state <= store_arg0;
end if;
when fetch_arg1 =>
register_address <= arg1_address;
register_operation <= OP_REG_GET;
register_enable <= '1';
state <= store_arg1;
when store_arg1 =>
if register_ready = '1' then
arg1 <= register_data_read;
register_enable <= '0';
state <= execute;
else
state <= store_arg1;
end if;
when execute =>
result <= arg0 xor arg1;
state <= store_result;
when store_result =>
register_address <= AccumulatorRegister;
register_operation <= OP_REG_SET;
register_data_write <= result;
register_enable <= '1';
instruction_ready <= '1';
state <= complete;
when complete =>
state <= complete;
end case;
else
instruction_ready <= '0';
state <= fetch_arg0;
end if;
end if;
end process;
end BitwiseXorInstructionExecutorImpl;
|
bsd-3-clause
|
tau-tao/FPGAIPFilter
|
FPGA_CODE/JTAG_RW_PKT_PROC/jtagif2.vhd
|
2
|
2474
|
library ieee;
use ieee.std_logic_1164.all;
entity jtagif2 is
generic
( DR_BITS : integer
);
port
( tck : in std_logic
; tdi : in std_logic
; tdo : out std_logic
; aclr : in std_logic
; sdr : in std_logic
; udr : in std_logic
; cdr : in std_logic
; ir_in : in std_logic_vector(2 downto 0)
; vdr_out : out std_logic_vector(DR_BITS - 1 downto 0)
; vdr_out_rdy : out std_logic
; vdr_in : in std_logic_vector(DR_BITS - 1 downto 0)
; vdr_in_rdy : out std_logic
; ir_out : out std_logic_vector(2 downto 0)
);
end entity jtagif2;
architecture rtl of jtagif2 is
constant TOP_BIT : integer := DR_BITS - 1;
-- must match constants in JtagRW.hs
constant READV : std_logic_vector(2 downto 0) := "001";
constant WRITEV : std_logic_vector(2 downto 0) := "010";
signal read_in : std_logic_vector(TOP_BIT downto 0);
signal write_out : std_logic_vector(TOP_BIT downto 0);
signal vdr_out_rdy_1 : std_logic;
signal vdr_out_rdy_2 : std_logic;
begin
process(tck)
begin
if rising_edge(tck) then
if ir_in = WRITEV then
if sdr = '1' then
read_in <= tdi & read_in(TOP_BIT downto 1);
elsif udr = '1' then
vdr_out <= read_in;
end if;
elsif ir_in = READV then
if cdr = '1' then
write_out <= vdr_in;
elsif sdr = '1' then
write_out <= tdi & write_out(TOP_BIT downto 1);
end if;
end if;
end if;
end process;
process(tck)
begin
if rising_edge(tck) then
if ir_in = WRITEV and udr = '1' then
vdr_out_rdy_2 <= '1';
else
vdr_out_rdy_2 <= '0';
end if;
end if;
end process;
process(tck)
begin
if rising_edge(tck) then
vdr_out_rdy_1 <= vdr_out_rdy_2;
vdr_out_rdy <= vdr_out_rdy_2 and not vdr_out_rdy_1;
end if;
end process;
process(tck)
begin
if rising_edge(tck) then
if ir_in = READV and cdr = '1' then
vdr_in_rdy <= '1';
else
vdr_in_rdy <= '0';
end if;
end if;
end process;
with ir_in select
tdo <= write_out(0) when READV, read_in(0) when WRITEV, tdi when others;
end architecture;
|
bsd-3-clause
|
Rogiel/BananaCore
|
Source/Instruction/Executor/LoadInstructionExecutor.vhd
|
1
|
4912
|
--
-- BananaCore - A processor written in VHDL
--
-- Created by Rogiel Sulzbach.
-- Copyright (c) 2014-2015 Rogiel Sulzbach. All rights reserved.
--
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_1164.std_logic;
library BananaCore;
use BananaCore.Core.all;
use BananaCore.Memory.all;
use BananaCore.RegisterPackage.all;
-- The LoadInstructionExecutor entity
entity LoadInstructionExecutor is
port(
-- the processor main clock
clock: in BananaCore.Core.Clock;
-- enables the instruction
enable: in std_logic;
-- the first register to operate on (argument 0)
arg0_address: in RegisterAddress;
-- the first register to operate on (argument 1)
arg1_address: in RegisterAddress;
-- the address to operate on (argument 2)
arg2_address: in MemoryAddress;
-- a bus indicating if the instruction is ready or not
instruction_ready: out std_logic := '0';
------------------------------------------
-- MEMORY BUS
------------------------------------------
-- the address to read/write memory from/to
memory_address: out MemoryAddress := (others => '0');
-- the memory being read to
memory_data_read: in MemoryData;
-- the memory being written to
memory_data_write: out MemoryData := (others => '0');
-- the operation to perform on the memory
memory_operation: out MemoryOperation := MEMORY_OP_DISABLED;
-- a flag indicating if a memory operation should be performed
memory_enable: out std_logic := '0';
-- a flag indicating if a memory operation has completed
memory_ready: in std_logic;
------------------------------------------
-- REGISTER BUS
------------------------------------------
-- the processor register address bus
register_address: out RegisterAddress := (others => '0');
-- the processor register data bus
register_data_read: in RegisterData;
-- the processor register data bus
register_data_write: out RegisterData := (others => '0');
-- the processor register operation signal
register_operation: out RegisterOperation := OP_REG_DISABLED;
-- the processor register enable signal
register_enable: out std_logic := '0';
-- a flag indicating if a register operation has completed
register_ready: in std_logic
);
end LoadInstructionExecutor;
architecture LoadInstructionExecutorImpl of LoadInstructionExecutor is
type state_type is (
check,
fetch_mem0,
store_mem0,
fetch_mem1,
store_mem1,
fetch_register,
store_register,
store_result,
complete
);
signal state: state_type := fetch_mem0;
signal result: RegisterData;
begin
process (clock) begin
if clock'event and clock = '1' then
if enable = '1' then
case state is
when check =>
if arg0_address = "0000" then
state <= fetch_register;
elsif arg0_address = "0001" then
state <= fetch_mem0;
elsif arg0_address = "0010" then
state <= store_result;
result <= std_logic_vector(arg2_address);
else
state <= complete;
end if;
when fetch_mem0 =>
instruction_ready <= '0';
memory_address <= arg2_address;
memory_operation <= MEMORY_OP_READ;
memory_enable <= '1';
state <= store_mem0;
when store_mem0 =>
if memory_ready = '1' then
result(7 downto 0) <= memory_data_read;
memory_enable <= '0';
state <= fetch_mem1;
else
state <= store_mem0;
end if;
when fetch_mem1 =>
instruction_ready <= '0';
memory_address <= arg2_address + 1;
memory_operation <= MEMORY_OP_READ;
memory_enable <= '1';
state <= store_mem1;
when store_mem1 =>
if memory_ready = '1' then
result(8 downto 15) <= memory_data_read;
memory_enable <= '0';
state <= store_result;
else
state <= store_mem1;
end if;
when fetch_register =>
register_address <= arg2_address(11 downto 8);
register_operation <= OP_REG_GET;
register_enable <= '1';
state <= store_register;
when store_register =>
if register_ready = '1' then
result <= register_data_read;
state <= store_result;
register_enable <= '0';
else
state <= store_register;
end if;
when store_result =>
register_address <= arg1_address;
register_operation <= OP_REG_SET;
register_data_write <= result;
register_enable <= '1';
state <= complete;
when complete =>
if register_ready = '1' then
instruction_ready <= '1';
register_enable <= '0';
register_operation <= OP_REG_GET;
end if;
state <= complete;
end case;
else
instruction_ready <= '0';
register_enable <= '0';
register_operation <= OP_REG_GET;
memory_enable <= '0';
state <= check;
end if;
end if;
end process;
end LoadInstructionExecutorImpl;
|
bsd-3-clause
|
tau-tao/FPGAIPFilter
|
FPGA_CODE/JTAG_RW/counter_div.vhd
|
1
|
681
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter_div is
generic ( OFFSET : INTEGER; BIT_WIDTH : INTEGER) ;
port( clk : in std_logic;
counter_out : out std_logic_vector((BIT_WIDTH - 1) downto 0)
);
end entity counter_div;
architecture syn of counter_div is
signal counter_data : std_logic_vector(31 downto 0) := (others => '0');
begin
process(clk)
begin
if rising_edge(clk) then
counter_data <= std_logic_vector(unsigned(counter_data) + 1);
end if;
end process;
counter_out <= counter_data((OFFSET + BIT_WIDTH - 1) downto OFFSET);
end architecture syn;
|
bsd-3-clause
|
Rogiel/BananaCore
|
Source/Instruction/Executor/BitwiseNandInstructionExecutor.vhd
|
1
|
3977
|
--
-- BananaCore - A processor written in VHDL
--
-- Created by Rogiel Sulzbach.
-- Copyright (c) 2014-2015 Rogiel Sulzbach. All rights reserved.
--
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_1164.std_logic;
library BananaCore;
use BananaCore.Core.all;
use BananaCore.Memory.all;
use BananaCore.RegisterPackage.all;
-- The BitwiseNandInstructionExecutor entity
entity BitwiseNandInstructionExecutor is
port(
-- the processor main clock
clock: in BananaCore.Core.Clock;
-- enables the instruction
enable: in std_logic;
-- the first register to operate on (argument 0)
arg0_address: in RegisterAddress;
-- the first register to operate on (argument 1)
arg1_address: in RegisterAddress;
-- a bus indicating if the instruction is ready or not
instruction_ready: out std_logic := '0';
------------------------------------------
-- MEMORY BUS
------------------------------------------
-- the address to read/write memory from/to
memory_address: out MemoryAddress := (others => '0');
-- the memory being read to
memory_data_read: in MemoryData;
-- the memory being written to
memory_data_write: out MemoryData := (others => '0');
-- the operation to perform on the memory
memory_operation: out MemoryOperation := MEMORY_OP_DISABLED;
-- a flag indicating if a memory operation should be performed
memory_enable: out std_logic;
-- a flag indicating if a memory operation has completed
memory_ready: in std_logic;
------------------------------------------
-- REGISTER BUS
------------------------------------------
-- the processor register address bus
register_address: out RegisterAddress := (others => '0');
-- the processor register data bus
register_data_read: in RegisterData;
-- the processor register data bus
register_data_write: out RegisterData := (others => '0');
-- the processor register operation signal
register_operation: out RegisterOperation := OP_REG_DISABLED;
-- the processor register enable signal
register_enable: out std_logic := '0';
-- a flag indicating if a register operation has completed
register_ready: in std_logic
);
end BitwiseNandInstructionExecutor;
architecture BitwiseNandInstructionExecutorImpl of BitwiseNandInstructionExecutor is
type state_type is (
fetch_arg0,
store_arg0,
fetch_arg1,
store_arg1,
execute,
store_result,
complete
);
signal state: state_type := fetch_arg0;
signal arg0: RegisterData;
signal arg1: RegisterData;
signal result: RegisterData;
begin
process (clock) begin
if clock'event and clock = '1' then
if enable = '1' then
case state is
when fetch_arg0 =>
instruction_ready <= '0';
register_address <= arg0_address;
register_operation <= OP_REG_GET;
register_enable <= '1';
state <= store_arg0;
when store_arg0 =>
if register_ready = '1' then
arg0 <= register_data_read;
register_enable <= '0';
state <= fetch_arg1;
else
state <= store_arg0;
end if;
when fetch_arg1 =>
register_address <= arg1_address;
register_operation <= OP_REG_GET;
register_enable <= '1';
state <= store_arg1;
when store_arg1 =>
if register_ready = '1' then
arg1 <= register_data_read;
register_enable <= '0';
state <= execute;
else
state <= store_arg1;
end if;
when execute =>
result <= arg0 nand arg1;
state <= store_result;
when store_result =>
register_address <= AccumulatorRegister;
register_operation <= OP_REG_SET;
register_data_write <= result;
register_enable <= '1';
instruction_ready <= '1';
state <= complete;
when complete =>
state <= complete;
end case;
else
instruction_ready <= '0';
state <= fetch_arg0;
end if;
end if;
end process;
end BitwiseNandInstructionExecutorImpl;
|
bsd-3-clause
|
tau-tao/FPGAIPFilter
|
FPGA_CODE/JTAG_RW_PKT_PROC/PacketProcessorDF/packetprocessordf_topentity.vhdl
|
2
|
3407
|
-- Automatically generated VHDL-93
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.MATH_REAL.ALL;
use std.textio.all;
use work.all;
use work.packetprocessordf_types.all;
entity packetprocessordf_topentity is
port(input_0_0 : in std_logic_vector(28 downto 0);
input_0_1 : in boolean;
-- clock
system1000 : in std_logic;
-- asynchronous reset: active low
system1000_rstn : in std_logic;
output_0_0 : out unsigned(10 downto 0);
output_0_1 : out unsigned(10 downto 0);
output_0_2 : out unsigned(3 downto 0);
output_0_3 : out unsigned(15 downto 0);
output_0_4 : out std_logic_vector(8 downto 0);
output_0_5 : out boolean;
output_0_6_0_0 : out unsigned(10 downto 0);
output_0_6_0_1 : out unsigned(7 downto 0);
output_0_6_0_2 : out unsigned(7 downto 0);
output_0_6_1_0 : out unsigned(10 downto 0);
output_0_6_1_1 : out unsigned(7 downto 0);
output_0_6_1_2 : out unsigned(7 downto 0);
output_0_6_2_0 : out unsigned(10 downto 0);
output_0_6_2_1 : out unsigned(7 downto 0);
output_0_6_2_2 : out unsigned(7 downto 0);
output_0_6_3_0 : out unsigned(10 downto 0);
output_0_6_3_1 : out unsigned(7 downto 0);
output_0_6_3_2 : out unsigned(7 downto 0);
output_0_7 : out unsigned(1 downto 0);
output_0_8 : out boolean);
end;
architecture structural of packetprocessordf_topentity is
signal input_0 : packetprocessordf_types.tup2;
signal output_0 : packetprocessordf_types.counterstate;
signal output_0_6 : packetprocessordf_types.array_of_tup3(0 to 3);
signal output_0_6_0 : packetprocessordf_types.tup3;
signal output_0_6_1 : packetprocessordf_types.tup3;
signal output_0_6_2 : packetprocessordf_types.tup3;
signal output_0_6_3 : packetprocessordf_types.tup3;
begin
input_0 <= (tup2_sel0 => input_0_0
,tup2_sel1 => input_0_1);
packetprocessordf_topentity_0_inst : entity packetprocessordf_topentity_0
port map
(i => input_0
,system1000 => system1000
,system1000_rstn => system1000_rstn
,result => output_0);
output_0_0 <= output_0.counterstate_sel0;
output_0_1 <= output_0.counterstate_sel1;
output_0_2 <= output_0.counterstate_sel2;
output_0_3 <= output_0.counterstate_sel3;
output_0_4 <= output_0.counterstate_sel4;
output_0_5 <= output_0.counterstate_sel5;
output_0_6 <= output_0.counterstate_sel6;
output_0_7 <= output_0.counterstate_sel7;
output_0_8 <= output_0.counterstate_sel8;
output_0_6_0 <= output_0_6(0);
output_0_6_1 <= output_0_6(1);
output_0_6_2 <= output_0_6(2);
output_0_6_3 <= output_0_6(3);
output_0_6_0_0 <= output_0_6_0.tup3_sel0;
output_0_6_0_1 <= output_0_6_0.tup3_sel1;
output_0_6_0_2 <= output_0_6_0.tup3_sel2;
output_0_6_1_0 <= output_0_6_1.tup3_sel0;
output_0_6_1_1 <= output_0_6_1.tup3_sel1;
output_0_6_1_2 <= output_0_6_1.tup3_sel2;
output_0_6_2_0 <= output_0_6_2.tup3_sel0;
output_0_6_2_1 <= output_0_6_2.tup3_sel1;
output_0_6_2_2 <= output_0_6_2.tup3_sel2;
output_0_6_3_0 <= output_0_6_3.tup3_sel0;
output_0_6_3_1 <= output_0_6_3.tup3_sel1;
output_0_6_3_2 <= output_0_6_3.tup3_sel2;
end;
|
bsd-3-clause
|
tau-tao/FPGAIPFilter
|
FPGA_CODE/JTAG_RW_PKT_PROC/clckctrl/simulation/clckctrl.vhd
|
4
|
864
|
-- clckctrl.vhd
-- Generated using ACDS version 16.1 200
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity clckctrl is
port (
inclk : in std_logic := '0'; -- altclkctrl_input.inclk
ena : in std_logic := '0'; -- .ena
outclk : out std_logic -- altclkctrl_output.outclk
);
end entity clckctrl;
architecture rtl of clckctrl is
component clckctrl_altclkctrl_0 is
port (
inclk : in std_logic := 'X'; -- inclk
ena : in std_logic := 'X'; -- ena
outclk : out std_logic -- outclk
);
end component clckctrl_altclkctrl_0;
begin
altclkctrl_0 : component clckctrl_altclkctrl_0
port map (
inclk => inclk, -- altclkctrl_input.inclk
ena => ena, -- .ena
outclk => outclk -- altclkctrl_output.outclk
);
end architecture rtl; -- of clckctrl
|
bsd-3-clause
|
Rogiel/BananaCore
|
Source/Instruction/InstructionDecoder.vhd
|
1
|
3417
|
--
-- BananaCore - A processor written in VHDL
--
-- Created by Rogiel Sulzbach.
-- Copyright (c) 2014-2015 Rogiel Sulzbach. All rights reserved.
--
library ieee;
use ieee.numeric_bit.all;
use ieee.std_logic_1164.all;
library BananaCore;
use BananaCore.Instruction.DecodedInstruction;
use BananaCore.Instruction.all;
use BananaCore.Core.all;
-- Decodes a instruction bit stream into a organized and easy to use instruction record
entity InstructionDecoder is
port(
-- the processor main clock
clock: in BananaCore.Core.Clock;
-- the instruction input byte
instruction_data: in std_logic_vector(23 downto 0);
-- the resulting decoded instruction
instruction: out DecodedInstruction;
enable: in bit;
ready: out bit
);
end InstructionDecoder;
architecture InstructionDecoderImpl of InstructionDecoder is
signal decoded_instruction: DecodedInstruction;
begin
process(clock) begin
if clock'event and clock = '1' then
if enable = '1' then
case instruction_data(7 downto 0) is
when "00000000" =>
decoded_instruction.opcode <= LOAD;
decoded_instruction.size <= 3;
when "00000001" =>
decoded_instruction.opcode <= STORE;
decoded_instruction.size <= 3;
when "00010000" =>
decoded_instruction.opcode <= ADD;
decoded_instruction.size <= 2;
when "00010001" =>
decoded_instruction.opcode <= SUBTRACT;
decoded_instruction.size <= 2;
when "00010010" =>
decoded_instruction.opcode <= MULTIPLY;
decoded_instruction.size <= 2;
when "00010011" =>
decoded_instruction.opcode <= DIVIDE;
decoded_instruction.size <= 2;
when "01000000" =>
decoded_instruction.opcode <= BITWISE_AND;
decoded_instruction.size <= 2;
when "01000001" =>
decoded_instruction.opcode <= BITWISE_OR;
decoded_instruction.size <= 2;
when "01000010" =>
decoded_instruction.opcode <= BITWISE_NAND;
decoded_instruction.size <= 2;
when "01000011" =>
decoded_instruction.opcode <= BITWISE_NOR;
decoded_instruction.size <= 2;
when "01000100" =>
decoded_instruction.opcode <= BITWISE_XOR;
decoded_instruction.size <= 2;
when "01000101" =>
decoded_instruction.opcode <= BITWISE_NOT;
decoded_instruction.size <= 2;
when "00110000" =>
decoded_instruction.opcode <= GREATER_THAN;
decoded_instruction.size <= 2;
when "00110001" =>
decoded_instruction.opcode <= GREATER_OR_EQUAL_THAN;
decoded_instruction.size <= 2;
when "00110010" =>
decoded_instruction.opcode <= LESS_THAN;
decoded_instruction.size <= 2;
when "00110011" =>
decoded_instruction.opcode <= LESS_OR_EQUAL_THAN;
decoded_instruction.size <= 2;
when "00110100" =>
decoded_instruction.opcode <= EQUAL;
decoded_instruction.size <= 2;
when "00110101" =>
decoded_instruction.opcode <= NOT_EQUAL;
decoded_instruction.size <= 2;
when "00100000" =>
decoded_instruction.opcode <= JUMP;
decoded_instruction.size <= 3;
when "00100010" =>
decoded_instruction.opcode <= JUMP_IF_CARRY;
decoded_instruction.size <= 3;
when others =>
decoded_instruction.opcode <= HALT;
decoded_instruction.size <= 1;
end case;
instruction <= decoded_instruction;
ready <='1';
else
ready <= '0';
end if;
end if;
end process;
end InstructionDecoderImpl;
|
bsd-3-clause
|
tau-tao/FPGAIPFilter
|
FPGA_CODE/JTAG_RW_PKT_PROC/dbgram.vhd
|
2
|
6523
|
-- megafunction wizard: %RAM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: dbgram.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 16.1.1 Build 200 11/30/2016 SJ Lite Edition
-- ************************************************************
--Copyright (C) 2016 Intel Corporation. All rights reserved.
--Your use of Intel Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Intel Program License
--Subscription Agreement, the Intel Quartus Prime License Agreement,
--the Intel MegaCore Function License Agreement, or other
--applicable license agreement, including, without limitation,
--that your use is for the sole purpose of programming logic
--devices manufactured by Intel and sold by Intel or its
--authorized distributors. Please refer to the applicable
--agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
ENTITY dbgram IS
PORT
(
address : IN STD_LOGIC_VECTOR (12 DOWNTO 0);
clock : IN STD_LOGIC := '1';
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
wren : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
);
END dbgram;
ARCHITECTURE SYN OF dbgram IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (15 DOWNTO 0);
BEGIN
q <= sub_wire0(15 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
intended_device_family => "Cyclone IV E",
lpm_hint => "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=DBG1",
lpm_type => "altsyncram",
maximum_depth => 8192,
numwords_a => 8192,
operation_mode => "SINGLE_PORT",
outdata_aclr_a => "NONE",
outdata_reg_a => "CLOCK0",
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
widthad_a => 13,
width_a => 16,
width_byteena_a => 1
)
PORT MAP (
address_a => address,
clock0 => clock,
data_a => data,
wren_a => wren,
q_a => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrData NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1"
-- Retrieval info: PRIVATE: JTAG_ID STRING "DBG1"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "8192"
-- Retrieval info: PRIVATE: MIFfilename STRING ""
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "8192"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegData NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
-- Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "13"
-- Retrieval info: PRIVATE: WidthData NUMERIC "16"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=DBG1"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: MAXIMUM_DEPTH NUMERIC "8192"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "8192"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "13"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 13 0 INPUT NODEFVAL "address[12..0]"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]"
-- Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]"
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
-- Retrieval info: CONNECT: @address_a 0 0 13 0 address 0 0 13 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 16 0 @q_a 0 0 16 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL dbgram.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dbgram.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dbgram.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dbgram.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dbgram_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
|
bsd-3-clause
|
tau-tao/FPGAIPFilter
|
FPGA_CODE/JTAG_RW_PKT_PROC_MOORE/clckctrl/unnamed_inst.vhd
|
2
|
414
|
component unnamed is
port (
inclk : in std_logic := 'X'; -- inclk
ena : in std_logic := 'X'; -- ena
outclk : out std_logic -- outclk
);
end component unnamed;
u0 : component unnamed
port map (
inclk => CONNECTED_TO_inclk, -- altclkctrl_input.inclk
ena => CONNECTED_TO_ena, -- .ena
outclk => CONNECTED_TO_outclk -- altclkctrl_output.outclk
);
|
bsd-3-clause
|
plessl/zippy
|
vhdl/testbenches/tb_mux16to1.vhd
|
1
|
7192
|
------------------------------------------------------------------------------
-- Testbench for mux16to1.vhd
--
-- Project :
-- File : tb_mux16to1.vhd
-- Author : Rolf Enzler <[email protected]>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Created : 2002/10/02
-- Last changed: $LastChangedDate: 2004-10-05 17:10:36 +0200 (Tue, 05 Oct 2004) $
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.componentsPkg.all;
use work.auxPkg.all;
entity tb_Mux16to1 is
end tb_Mux16to1;
architecture arch of tb_Mux16to1 is
constant WIDTH : integer := 8;
-- simulation stuff
constant CLK_PERIOD : time := 100 ns;
signal ccount : integer := 1;
type tbstatusType is (rst, idle, sel0, sel1, sel2, sel3, sel4, sel5, sel6, sel7, sel8,
sel9, selA, selB, selC, selD, selE, selF);
signal tbStatus : tbstatusType := idle;
-- general control signals
signal ClkxC : std_logic := '1';
signal RstxRB : std_logic;
-- data and control/status signals
signal SelxS : std_logic_vector(3 downto 0);
signal In0xD : std_logic_vector(WIDTH-1 downto 0);
signal In1xD : std_logic_vector(WIDTH-1 downto 0);
signal In2xD : std_logic_vector(WIDTH-1 downto 0);
signal In3xD : std_logic_vector(WIDTH-1 downto 0);
signal In4xD : std_logic_vector(WIDTH-1 downto 0);
signal In5xD : std_logic_vector(WIDTH-1 downto 0);
signal In6xD : std_logic_vector(WIDTH-1 downto 0);
signal In7xD : std_logic_vector(WIDTH-1 downto 0);
signal In8xD : std_logic_vector(WIDTH-1 downto 0);
signal In9xD : std_logic_vector(WIDTH-1 downto 0);
signal InAxD : std_logic_vector(WIDTH-1 downto 0);
signal InBxD : std_logic_vector(WIDTH-1 downto 0);
signal InCxD : std_logic_vector(WIDTH-1 downto 0);
signal InDxD : std_logic_vector(WIDTH-1 downto 0);
signal InExD : std_logic_vector(WIDTH-1 downto 0);
signal InFxD : std_logic_vector(WIDTH-1 downto 0);
signal OutxD : std_logic_vector(WIDTH-1 downto 0);
begin -- arch
----------------------------------------------------------------------------
-- device under test
----------------------------------------------------------------------------
dut : Mux16to1
generic map (
WIDTH => WIDTH)
port map (
SelxSI => SelxS,
In0xDI => In0xD,
In1xDI => In1xD,
In2xDI => In2xD,
In3xDI => In3xD,
In4xDI => In4xD,
In5xDI => In5xD,
In6xDI => In6xD,
In7xDI => In7xD,
In8xDI => In8xD,
In9xDI => In9xD,
InAxDI => InAxD,
InBxDI => InBxD,
InCxDI => InCxD,
InDxDI => InDxD,
InExDI => InExD,
InFxDI => InFxD,
OutxDO => OutxD);
----------------------------------------------------------------------------
-- stimuli
----------------------------------------------------------------------------
stimuliTb : process
begin -- process stimuliTb
tbStatus <= rst;
SelxS <= "0000";
In0xD <= std_logic_vector(to_unsigned(0, WIDTH));
In1xD <= std_logic_vector(to_unsigned(1, WIDTH));
In2xD <= std_logic_vector(to_unsigned(2, WIDTH));
In3xD <= std_logic_vector(to_unsigned(3, WIDTH));
In4xD <= std_logic_vector(to_unsigned(4, WIDTH));
In5xD <= std_logic_vector(to_unsigned(5, WIDTH));
In6xD <= std_logic_vector(to_unsigned(6, WIDTH));
In7xD <= std_logic_vector(to_unsigned(7, WIDTH));
In8xD <= std_logic_vector(to_unsigned(8, WIDTH));
In9xD <= std_logic_vector(to_unsigned(9, WIDTH));
InAxD <= std_logic_vector(to_unsigned(10, WIDTH));
InBxD <= std_logic_vector(to_unsigned(11, WIDTH));
InCxD <= std_logic_vector(to_unsigned(12, WIDTH));
InDxD <= std_logic_vector(to_unsigned(13, WIDTH));
InExD <= std_logic_vector(to_unsigned(14, WIDTH));
InFxD <= std_logic_vector(to_unsigned(15, WIDTH));
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '0');
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '1');
tbStatus <= idle;
wait for CLK_PERIOD*0.25;
tbStatus <= sel0; -- sel0
SelxS <= "0000";
wait for CLK_PERIOD;
tbStatus <= sel1; -- sel1
SelxS <= "0001";
wait for CLK_PERIOD;
tbStatus <= sel2; -- sel2
SelxS <= "0010";
wait for CLK_PERIOD;
tbStatus <= sel3; -- sel3
SelxS <= "0011";
wait for CLK_PERIOD;
tbStatus <= sel4; -- sel4
SelxS <= "0100";
wait for CLK_PERIOD;
tbStatus <= sel5; -- sel5
SelxS <= "0101";
wait for CLK_PERIOD;
tbStatus <= sel6; -- sel6
SelxS <= "0110";
wait for CLK_PERIOD;
tbStatus <= sel7; -- sel7
SelxS <= "0111";
wait for CLK_PERIOD;
tbStatus <= sel8; -- sel8
SelxS <= "1000";
wait for CLK_PERIOD;
tbStatus <= sel9; -- sel9
SelxS <= "1001";
wait for CLK_PERIOD;
tbStatus <= selA; -- selA
SelxS <= "1010";
wait for CLK_PERIOD;
tbStatus <= selB; -- selB
SelxS <= "1011";
wait for CLK_PERIOD;
tbStatus <= selC; -- selC
SelxS <= "1100";
wait for CLK_PERIOD;
tbStatus <= selD; -- selD
SelxS <= "1101";
wait for CLK_PERIOD;
tbStatus <= selE; -- selE
SelxS <= "1110";
wait for CLK_PERIOD;
tbStatus <= selF; -- selF
SelxS <= "1111";
wait for CLK_PERIOD;
tbStatus <= idle;
SelxS <= "0000";
In0xD <= std_logic_vector(to_unsigned(0, WIDTH));
wait for 2*CLK_PERIOD;
tbStatus <= sel0; -- sel0
SelxS <= "0000";
wait for CLK_PERIOD;
wait for CLK_PERIOD;
In0xD <= std_logic_vector(to_unsigned(30, WIDTH));
wait for CLK_PERIOD;
In0xD <= std_logic_vector(to_unsigned(31, WIDTH));
wait for CLK_PERIOD;
In0xD <= std_logic_vector(to_unsigned(32, WIDTH));
wait for CLK_PERIOD;
tbStatus <= idle;
SelxS <= "0000";
In0xD <= std_logic_vector(to_unsigned(0, WIDTH));
wait for 2*CLK_PERIOD;
-- stop simulation
wait until (ClkxC'event and ClkxC = '1');
assert false
report "stimuli processed; sim. terminated after " & int2str(ccount) &
" cycles"
severity failure;
end process stimuliTb;
----------------------------------------------------------------------------
-- clock and reset generation
----------------------------------------------------------------------------
ClkxC <= not ClkxC after CLK_PERIOD/2;
RstxRB <= '0', '1' after CLK_PERIOD*1.25;
----------------------------------------------------------------------------
-- cycle counter
----------------------------------------------------------------------------
cyclecounter : process (ClkxC)
begin
if (ClkxC'event and ClkxC = '1') then
ccount <= ccount + 1;
end if;
end process cyclecounter;
end arch;
|
bsd-3-clause
|
plessl/zippy
|
vhdl/Scheduler.vhd
|
1
|
1349
|
------------------------------------------------------------------------------
-- Context scheduler
--
-- Project :
-- URL : $URL: $
-- Author : Christian Plessl <[email protected]>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Last changed: $Id: $
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.AuxPkg.all;
use work.archConfigPkg.all;
use work.ZArchPkg.all;
use work.ComponentsPkg.all;
use work.ConfigPkg.all;
entity Scheduler is
port (
ClkxC : in std_logic;
RstxRB : in std_logic;
SchedulerSelectxSI : in std_logic;
SchedContextSequencerxDI : in EngineScheduleControlType;
SchedTemporalPartitioningxDI : in EngineScheduleControlType;
EngineScheduleControlxEO : out EngineScheduleControlType
);
begin
end Scheduler;
architecture arch of Scheduler is
begin -- arch
process (SchedContextSequencerxDI, SchedTemporalPartitioningxDI,
SchedulerSelectxSI)
begin
if (SchedulerSelectxSI = '0') then
EngineScheduleControlxEO <= SchedContextSequencerxDI;
else
EngineScheduleControlxEO <= SchedTemporalPartitioningxDI;
end if;
end process;
end arch;
|
bsd-3-clause
|
plessl/zippy
|
vhdl/engine.vhd
|
1
|
11876
|
------------------------------------------------------------------------------
-- ZIPPY engine: - 2 input ports, 2 output ports (with enables)
-- - interconnect: some neighbours + busses
--
-- Project :
-- File : $Id: engine.vhd 241 2005-04-07 08:50:55Z plessl $
-- Authors : Rolf Enzler <[email protected]>
-- Christian Plessl <[email protected]>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Created : 2002/10/02
-- $Id: engine.vhd 241 2005-04-07 08:50:55Z plessl $
------------------------------------------------------------------------------
-- The engine is the core of the zippy architecture. It combines the cells
-- that form a grid, the local and bus interconnect between the cells, the io
-- ports and the corresponding io port controllers.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.archConfigPkg.all;
use work.ZArchPkg.all;
use work.ComponentsPkg.all;
use work.txt_util.all;
entity Engine is
generic (
DATAWIDTH : integer);
port (
ClkxC : in std_logic;
RstxRB : in std_logic;
CExEI : in std_logic;
ConfigxI : in engineConfigRec;
ClrContextxSI : in std_logic_vector(CNTXTWIDTH-1 downto 0);
ClrContextxEI : in std_logic;
ContextxSI : in std_logic_vector(CNTXTWIDTH-1 downto 0);
CycleDnCntxDI : in std_logic_vector(CCNTWIDTH-1 downto 0);
CycleUpCntxDI : in std_logic_vector(CCNTWIDTH-1 downto 0);
InPortxDI : in engineInoutDataType;
OutPortxDO : out engineInoutDataType;
InPortxEO : out std_logic_vector(N_IOP-1 downto 0);
OutPortxEO : out std_logic_vector(N_IOP-1 downto 0));
end Engine;
architecture simple of Engine is
signal GridInp : gridInputArray; -- GridInp(#row)(#cell).Inp*xD
signal GridOut : gridOutputArray; -- GridOut(#row)(#cell).Out*x{D,Z}
signal HBusNxZ : engineHBusNorthArray; -- all horiz north buses
signal HBusSxZ : engineHBusSouthArray; -- all horiz south buses
signal VBusExZ : engineVBusEastArray; -- all vertical east buses
type gridRomIOArray is array (N_ROWS-1 downto 0) of
data_vector(N_COLS-1 downto 0);
signal cellMemDataxDI : gridRomIOArray;
signal cellMemDataxDO : gridRomIOArray;
signal cellMemAddrxDO : gridRomIOArray;
signal cellMemCtrlxSO : gridRomIOArray;
-- IO signals to attach the ROM blocks, a ROM block is shared betweed all
-- cells in a row
signal RowRomRdAddrxZ : data_vector(N_ROWS-1 downto 0);
--signal RowRomWrDataxZ : data_vector(N_ROWS-1 downto 0);
--signal RowRomCtrlxZ : data_vector(N_ROWS-1 downto 0);
signal RowRomRdDataxZ : data_vector(N_ROWS-1 downto 0);
begin -- simple
-----------------------------------------------------------------------------
-- connect an ioport controller to every input and output of the
-- engine
-----------------------------------------------------------------------------
IOPortCtrlPort_gen : for prt in N_IOP-1 downto 0 generate
InPortCtrl : IOPortCtrl
generic map (
CCNTWIDTH => CCNTWIDTH)
port map (
ClkxC => ClkxC,
RstxRB => RstxRB,
ConfigxI => ConfigxI.inportConf(prt),
CycleDnCntxDI => CycleDnCntxDI,
CycleUpCntxDI => CycleUpCntxDI,
PortxEO => InPortxEO(prt));
OutPortCtrl : IOPortCtrl
generic map (
CCNTWIDTH => CCNTWIDTH)
port map (
ClkxC => ClkxC,
RstxRB => RstxRB,
ConfigxI => ConfigxI.outportConf(prt),
CycleDnCntxDI => CycleDnCntxDI,
CycleUpCntxDI => CycleUpCntxDI,
PortxEO => OutPortxEO(prt));
end generate IOPortCtrlPort_gen;
Gen_Rows : for i in N_ROWS-1 downto 0 generate
row_i : Row
generic map (
DATAWIDTH => DATAWIDTH)
port map (
ClkxC => ClkxC,
RstxRB => RstxRB,
CExEI => CExEI,
ConfigxI => ConfigxI.gridConf(i),
ClrContextxSI => ClrContextxSI,
ClrContextxEI => ClrContextxEI,
ContextxSI => ContextxSI,
InpxI => GridInp(i),
OutxO => GridOut(i),
MemDataxDI => cellMemDataxDI(i), -- input from MEM
MemAddrxDO => cellMemAddrxDO(i), -- addr output to MEM
MemDataxDO => cellMemDataxDO(i), -- data output to MEM
MemCtrlxSO => cellMemCtrlxSO(i) -- ctrl output to MEM
);
end generate Gen_Rows;
Gen_Roms : for r in N_ROWS-1 downto 0 generate
rom_i : Rom
generic map (
DEPTH => N_MEMDEPTH)
port map (
ConfigxI => ConfigxI.memoryConf(r),
RdAddrxDI => RowRomRdAddrxZ(r),
RdDataxDO => RowRomRdDataxZ(r));
end generate Gen_Roms;
-----------------------------------------------------------------------------
-- create tristate buffers for driving the HBusN buses from the input ports,
-- and add tristate buffers for driving the results from the HBusN buses to
-- the output ports
-----------------------------------------------------------------------------
TBufPort_gen : for prt in N_IOP-1 downto 0 generate
TBufrow_gen : for row in N_ROWS-1 downto 0 generate
TBufHBusN_gen : for hbusn in N_HBUSN-1 downto 0 generate
-- connect input ports to HBusN
InpTBuf : TristateBuf
generic map (
WIDTH => DATAWIDTH)
port map (
InxDI => InPortxDI(prt),
OExEI => ConfigxI.inputDriverConf(prt)(row)(hbusn),
OutxZO => HBusNxZ(row)(hbusn));
-- connect HBusN to output ports
OutpTristateBuf : TristateBuf
generic map (
WIDTH => DATAWIDTH)
port map (
InxDI => HBusNxZ(row)(hbusn),
OExEI => ConfigxI.outputDriverConf(prt)(row)(hbusn),
OutxZO => OutPortxDO(prt));
end generate TBufHBusN_gen;
end generate TBufrow_gen;
end generate TBufPort_gen;
-------------------------------------------------------------------------------
-- CELL OUTPUTS
-------------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- create bus drivers the allow to write data from the cells to HBusN, HBusS
-- and VBusE buses.
-----------------------------------------------------------------------------
TBufConHBusRow_gen : for r in N_ROWS-1 downto 0 generate
TBufConHBusCol_gen : for c in N_COLS-1 downto 0 generate
-- output to HBusN
-- cells in row r drive the HBusN of row r+1
TBufConHBusHBusN_gen : for hbusn in N_HBUSN-1 downto 0 generate
HBusNxZ((r+1) mod N_ROWS)(hbusn) <= GridOut(r)(c).HBusNxDZ(hbusn);
end generate TBufConHBusHBusN_gen;
-- output to HBusS
-- cell in row r drive the HBusS of the same row r
TBufConHBusHBusS_gen : for hbuss in N_HBUSS-1 downto 0 generate
HBusSxZ(r)(hbuss) <= GridOut(r)(c).HBusSxDZ(hbuss);
end generate TBufConHBusHBusS_gen;
-- output to VBusE
-- cells in column c drive the VBusE of column the same column c
TBufConHBusVBusE_gen : for vbuse in N_VBUSE-1 downto 0 generate
VBusExZ(c)(vbuse) <= GridOut(r)(c).VBusExDZ(vbuse);
end generate TBufConHBusVBusE_gen;
-- output to memory elements: all cells in a row drive the same bus,
-- since there is just a single shared memory block per ROW
-- arbitration of bus is handled with configuration. If a cell is
-- configured as alu_rom, it drives address data to this bus. Only one
-- cell per row is allowed to be configured as memory cell
RowRomRdAddrxZ(r) <= cellMemAddrxDO(r)(c);
-- for RAM, add other output signals here
end generate TBufConHBusCol_gen;
end generate TBufConHBusRow_gen;
-----------------------------------------------------------------------------
-- CELL INPUTS
-----------------------------------------------------------------------------
CellInpRow_gen : for r in N_ROWS-1 downto 0 generate
CellInpCol_gen : for c in N_COLS-1 downto 0 generate
-- local interconnect
GridInp(r)(c).LocalxDI(LOCAL_NW) <=
GridOut((r-1) mod N_ROWS)((c-1) mod N_COLS).LocalxDO; -- NW
GridInp(r)(c).LocalxDI(LOCAL_N) <=
GridOut((r-1) mod N_ROWS)((c+0) mod N_COLS).LocalxDO; -- N
GridInp(r)(c).LocalxDI(LOCAL_NE) <=
GridOut((r-1) mod N_ROWS)((c+1) mod N_COLS).LocalxDO; -- NE
GridInp(r)(c).LocalxDI(LOCAL_W) <=
GridOut((r+0) mod N_ROWS)((c-1) mod N_COLS).LocalxDO; -- W
GridInp(r)(c).LocalxDI(LOCAL_E) <=
GridOut((r+0) mod N_ROWS)((c+1) mod N_COLS).LocalxDO; -- E
GridInp(r)(c).LocalxDI(LOCAL_SW) <=
GridOut((r+1) mod N_ROWS)((c-1) mod N_COLS).LocalxDO; -- SW
GridInp(r)(c).LocalxDI(LOCAL_S) <=
GridOut((r+1) mod N_ROWS)((c+0) mod N_COLS).LocalxDO; -- S
GridInp(r)(c).LocalxDI(LOCAL_SE) <=
GridOut((r+1) mod N_ROWS)((c+1) mod N_COLS).LocalxDO; -- SE
-- FIXME FIXME FIXME: check feeding of singals to cells. Our testbenches
-- do not test the south and VBusE buses yet. create test for these buses.
-- bus interconnect
-- input from HBusN
CellInpHBusN_gen : for hbusn in N_HBUSN-1 downto 0 generate
GridInp(r)(c).HBusNxDI(hbusn) <= HBusNxZ(r)(hbusn); -- HBusN inputs
end generate CellInpHBusN_gen;
-- input from HBusS
CellInpHBusS_gen : for hbuss in N_HBUSS-1 downto 0 generate
GridInp(r)(c).HBusSxDI(hbuss) <= HBusSxZ(r)(hbuss); -- HBusS inputs
end generate CellInpHBusS_gen;
-- input from VBusE
-- cells in column c read from VBusE of column c-1 (west)
-- VBusE inputs
CellInpVBusE_gen : for vbuse in N_VBUSE-1 downto 0 generate
GridInp(r)(c).VBusExDI(vbuse) <= VBusExZ((c-1) mod N_COLS)(vbuse);
end generate CellInpVBusE_gen;
-- cell input from MEM, drive all cell memory inputs in a row with the
-- same data, since there is a shared memory block per row
cellMemDataxDI(r)(c) <= RowRomRdDataxZ(r);
end generate CellInpCol_gen;
end generate CellInpRow_gen;
-----------------------------------------------------------------------------
-- add pulldowns to all buses (horizontal,vertical, memory);
-----------------------------------------------------------------------------
PullDownRows_gen : for r in N_ROWS-1 downto 0 generate
PullDownHBusN_gen : for hbusn in N_HBUSN-1 downto 0 generate
begin
PullDownHBusN : PullBus
generic map (
WIDTH => DATAWIDTH)
port map (
ModexSI => '0',
BusxZO => HBusNxZ(r)(hbusn));
end generate PullDownHBusN_gen;
PullDownHBusS_gen : for hbuss in N_HBUSS-1 downto 0 generate
begin
PullDownHBusS : PullBus
generic map (
WIDTH => DATAWIDTH)
port map (
ModexSI => '0',
BusxZO => HBusSxZ(r)(hbuss));
end generate PullDownHBusS_gen;
end generate PullDownRows_gen;
PullDownCols_gen : for c in N_COLS-1 downto 0 generate
PullDownVBusE_gen : for vbuse in N_VBUSE-1 downto 0 generate
begin
PullDownVBusE : PullBus
generic map (
WIDTH => DATAWIDTH)
port map (
ModexSI => '0',
BusxZO => VBusExZ(c)(vbuse));
end generate PullDownVBusE_gen;
end generate PullDownCols_gen;
PullDownRowRomIn_gen : for r in N_ROWS-1 downto 0 generate
begin
PullDownRowRomAddrxDI : PullBus
generic map (
WIDTH => DATAWIDTH)
port map (
ModexSI => '0',
BusxZO => RowRomRdAddrxZ(r));
end generate PullDownRowRomIn_gen;
end simple;
|
bsd-3-clause
|
plessl/zippy
|
vhdl/configPkg.vhd
|
1
|
34592
|
------------------------------------------------------------------------------
-- Stuff for handling the ZUnit configuration(s)
--
-- Project :
-- File : $Id: configPkg.vhd 218 2005-01-13 17:02:10Z plessl $
-- Authors : Rolf Enzler <[email protected]>
-- Christian Plessl <[email protected]>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Created : 2002/10/08
-- Last changed: $LastChangedDate: 2005-01-13 18:02:10 +0100 (Thu, 13 Jan 2005) $
------------------------------------------------------------------------------
-- This package provides a number of functions that convert the configuration
-- of the Zippy array from a human readable, hierarchical VHDL-record form
-- to a bitstring representation.
-- The configuration can also be transformed into a C header file. The data
-- from this header file is used to configure the zunit via the host interface.
-------------------------------------------------------------------------------
-- Changes:
-- 2004-10-08 CP added documentation
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
use ieee.std_logic_textio.all;
use work.txt_util.all;
use work.archConfigPkg.all;
use work.ZArchPkg.all;
use work.AuxPkg.all;
package ConfigPkg is
constant PE_CFGLEN : integer := procConfig_length;
constant RE_CFGLEN : integer := routConfig_length;
constant CELL_CFGLEN : integer := cellConfig_length;
constant ROW_CFGLEN : integer := rowConfig_length;
constant GRID_CFGLEN : integer := gridConfig_length;
constant PORT_CFGLEN : integer := ioportConfig_length;
constant INPDRV_CFGLEN : integer := inputDriverConfig_length;
constant OUTPDRV_CFGLEN : integer := outputDriverConfig_length;
constant INPORT_CFGLEN : integer := inportConfig_length;
constant OUTPORT_CFGLEN : integer := outportConfig_length;
constant MEM_CFGLEN : integer := memoryConfig_length;
constant ENGN_CFGLEN : integer := engineConfig_length;
constant NPARTS : integer := num_partitions(ENGN_CFGLEN, PARTWIDTH);
constant CELLROUTINGINPUTCONFIGREC_LEN : integer :=
N_LOCALCON + N_HBUSN + N_HBUSS + N_VBUSE;
subtype cfgPartType is std_logic_vector(PARTWIDTH-1 downto 0);
type cfgPartArray is array (NPARTS-1 downto 0) of cfgPartType;
subtype contextType is std_logic_vector(ENGN_CFGLEN-1 downto 0);
type contextArray is array (N_CONTEXTS-1 downto 0) of contextType;
type contextPartArray is array (N_CONTEXTS-1 downto 0) of cfgPartArray;
-- initializes a procConfig record
function init_procConfig return procConfigRec;
-- initializes a routConfig record
function init_routConfig return routConfigRec;
-- initializes a cellConfig record
function init_cellConfig return cellConfigRec;
-- initializes a cellInputRec record
function init_cellInput return cellInputRec;
-- initializes a rowConfig array
function init_rowConfig return rowConfigArray;
-- initializes a rowInput array
function init_rowInput return rowInputArray;
-- initializes a gridConfig array
function init_gridConfig return gridConfigArray;
-- initializes an ioportConfig record
function init_ioportConfig return ioportConfigRec;
-- initializes an engineInportConfigArray
function init_inportConfig return engineInportConfigArray;
-- initializes an engineOutportConfigArray
function init_outportConfig return engineOutportConfigArray;
-- initializes an engineHBusNorthInputDriver array
function init_inputDriverConfig return engineHBusNorthInputDriverArray;
-- initializes an engineHBusNorthOutputDriver array
function init_outputDriverConfig return engineHBusNorthOutputDriverArray;
-- initializes an engineConfig record
function init_engineConfig return engineConfigRec;
-- converts a procConfig record to a vector
function to_procConfig_vec (Cfg : procConfigRec) return std_logic_vector;
-- converts a procConfig vector to a record
function to_procConfig_rec (CfgxD : std_logic_vector(PE_CFGLEN-1 downto 0))
return procConfigRec;
-- converts a routConfig record to a vector
function to_routConfig_vec (Cfg : routConfigRec) return std_logic_vector;
-- converts a routConfig vector to a record
function to_routConfig_rec (CfgxD : std_logic_vector(RE_CFGLEN-1 downto 0))
return routConfigRec;
-- converts a cellConfig record to a vector
function to_cellConfig_vec (Cfg : cellConfigRec) return std_logic_vector;
-- converts a cellConfig vector to a record
function to_cellConfig_rec (CfgxD : std_logic_vector(CELL_CFGLEN-1 downto 0))
return cellConfigRec;
-- converts a rowConfig array to a vector
function to_rowConfig_vec (Cfg : rowConfigArray) return std_logic_vector;
-- converts a rowConfig vector to an array
function to_rowConfig_arr (CfgxD : std_logic_vector(ROW_CFGLEN-1 downto 0))
return rowConfigArray;
-- converts a gridConfig array to a vector
function to_gridConfig_vec (Cfg : gridConfigArray) return std_logic_vector;
-- converts a gridConfig vector to an array
function to_gridConfig_arr (CfgxD : std_logic_vector(GRID_CFGLEN-1 downto 0))
return gridConfigArray;
-- convert a inputDriverConfig array to a vector
function to_inputDriverConfig_vec (Cfg : engineHBusNorthInputDriverArray)
return std_logic_vector;
-- convert a inputDriverConfig vector to an array
function to_inputDriverConfig_arr (
vec : std_logic_vector(INPDRV_CFGLEN-1 downto 0))
return engineHBusNorthInputDriverArray;
-- convert a outputDriverConfig array to a vector
function to_outputDriverConfig_vec (Cfg : engineHBusNorthOutputDriverArray)
return std_logic_vector;
-- convert a outputDriverConfig vector to an array
function to_outputDriverConfig_arr (
vec : std_logic_vector(INPDRV_CFGLEN-1 downto 0))
return engineHBusNorthOutputDriverArray;
-- converts an ioportConfig record to a vector
function to_ioportConfig_vec (Cfg : ioportConfigRec) return std_logic_vector;
-- converts an ioportConfig vector to a record
function to_ioportConfig_rec (
CfgxD : std_logic_vector(PORT_CFGLEN-1 downto 0))
return ioportConfigRec;
-- convert inportConfig vector to an array of records
function to_inportConfig_arr (
CfgxD : std_logic_vector(INPORT_CFGLEN-1 downto 0))
return engineInportConfigArray;
-- convert inportConfig array of records to vector
function to_inportConfig_vec (Cfg : engineInportConfigArray)
return std_logic_vector;
-- convert outportConfig vector to an array of records
function to_outportConfig_arr (
CfgxD : std_logic_vector(OUTPORT_CFGLEN-1 downto 0))
return engineOutportConfigArray;
-- convert outportConfig array of records to vector
function to_outportConfig_vec (Cfg : engineOutportConfigArray)
return std_logic_vector;
-----------------------------------------------------------------------------
-- memory configuration handling functions
-----------------------------------------------------------------------------
function init_memoryConfig return engineMemoryConfigArray;
function to_memoryConfig_vec (Cfg : engineMemoryConfigArray)
return std_logic_vector;
function to_memoryConfig_arr (CfgxD : std_logic_vector(MEM_CFGLEN-1 downto 0))
return engineMemoryConfigArray;
-- converts an engineConfig record to a vector
function to_engineConfig_vec (Cfg : engineConfigRec) return std_logic_vector;
-- converts an engineConfig vector to a record
function to_engineConfig_rec (
CfgxD : std_logic_vector(ENGN_CFGLEN-1 downto 0))
return engineConfigRec;
-- partitions the configuration into partitions of equal width
function partition_config (
signal CfgxD : std_logic_vector(ENGN_CFGLEN-1 downto 0))
return cfgPartArray;
-- generate .h file for coupled simulation
procedure gen_cfghfile (file hfile : text; CfgArr : in cfgPartArray);
-- generate .h file for coupled simulation (multi-context)
procedure gen_contexthfile2 (file hfile : text; cpArr : in contextPartArray);
end ConfigPkg;
------------------------------------------------------------------------------
-- BODY
------------------------------------------------------------------------------
package body ConfigPkg is
-- initializes a procConfig record
function init_procConfig return procConfigRec is
variable Cfg : procConfigRec;
begin
Cfg.OpMuxS := (others => I_NOREG);
Cfg.OpCtxRegSelxS := (others => (others => '0'));
Cfg.OutMuxS := O_NOREG;
Cfg.OutCtxRegSelxS := (others => '0');
Cfg.AluOpxS := ALU_OP_PASS0;
Cfg.ConstOpxD := (others => '0');
return Cfg;
end init_procConfig;
-- initializes a routConfig record
function init_routConfig return routConfigRec is
variable Cfg : routConfigRec;
begin
for inp in Cfg.i'range loop
Cfg.i(inp).LocalxE := (others => '0');
Cfg.i(inp).HBusNxE := (others => '0');
Cfg.i(inp).HBusSxE := (others => '0');
Cfg.i(inp).VBusExE := (others => '0');
end loop; -- inp
Cfg.o.HBusNxE := (others => '0');
Cfg.o.HBusSxE := (others => '0');
Cfg.o.VBusExE := (others => '0');
return Cfg;
end init_routConfig;
-- initializes a cellConfig record
function init_cellConfig return CellConfigRec is
variable Cfg : CellConfigRec;
begin
Cfg.procConf := init_procConfig;
Cfg.routConf := init_routConfig;
return Cfg;
end init_cellConfig;
-- initializes a cellInputRec record
function init_cellInput return cellInputRec is
variable Inp : cellInputRec;
begin
Inp.LocalxDI := (others => (others => '0'));
Inp.HBusNxDI := (others => (others => '0'));
Inp.HBusSxDI := (others => (others => '0'));
Inp.VBusExDI := (others => (others => '0'));
return Inp;
end init_cellInput;
-- initializes a rowConfig array
function init_rowConfig return rowConfigArray is
variable Cfg : rowConfigArray;
begin
for i in Cfg'range loop
Cfg(i) := init_cellConfig;
end loop; -- i
return Cfg;
end init_rowConfig;
-- initializes a rowInput array
function init_rowInput return rowInputArray is
variable Inp : rowInputArray;
begin
for i in Inp'range loop
Inp(i) := init_cellInput;
end loop; -- i
return Inp;
end init_rowInput;
-- initializes a gridConfig array
function init_gridConfig return gridConfigArray is
variable Cfg : gridConfigArray;
begin
for i in Cfg'range loop
Cfg(i) := init_rowConfig;
end loop; -- i
return Cfg;
end init_gridConfig;
-- initializes an ioportConfig record
function init_ioportConfig return ioportConfigRec is
variable Cfg : ioportConfigRec;
begin
Cfg.Cmp0MuxS := '0';
Cfg.Cmp0ModusxS := '0';
Cfg.Cmp0ConstxD := (others => '0');
Cfg.Cmp1MuxS := '0';
Cfg.Cmp1ModusxS := '0';
Cfg.Cmp1ConstxD := (others => '0');
Cfg.LUT4FunctxD := (others => '0');
return Cfg;
end init_ioportConfig;
-- initializes an engineInportConfigArray
function init_inportConfig return engineInportConfigArray is
variable Cfg : engineInportConfigArray;
begin
for inp in Cfg'range loop
Cfg(inp) := init_ioportConfig;
end loop; -- inp
return Cfg;
end init_inportConfig;
-- initializes an engineOutportConfigArray
function init_outportConfig return engineOutportConfigArray is
variable Cfg : engineOutportConfigArray;
begin
for outp in Cfg'range loop
Cfg(outp) := init_ioportConfig;
end loop; -- outp
return Cfg;
end init_outportConfig;
-----------------------------------------------------------------------------
-- functions for memory configuration handling
-----------------------------------------------------------------------------
-- initializes a memoryConfigArray
function init_memoryConfig return engineMemoryConfigArray is
variable arr : engineMemoryConfigArray;
begin
arr := (others => (others => (others => '0')));
return arr;
end init_memoryConfig;
function to_memoryConfig_vec (Cfg : engineMemoryConfigArray)
return std_logic_vector is
variable vec : std_logic_vector(MEM_CFGLEN-1 downto 0);
variable fromInd, toInd : integer;
constant SINGLEROMLEN : integer := N_MEMDEPTH*DATAWIDTH;
begin
for rom in Cfg'range loop
for i in Cfg(0)'range loop
fromInd := rom*SINGLEROMLEN + (i+1)*DATAWIDTH-1;
toInd := rom*SINGLEROMLEN + i*DATAWIDTH;
vec(fromInd downto toInd) := Cfg(rom)(i);
end loop;
end loop;
return vec;
end to_memoryConfig_vec;
function to_memoryConfig_arr (CfgxD : std_logic_vector(MEM_CFGLEN-1 downto 0))
return engineMemoryConfigArray is
variable Cfg : engineMemoryConfigArray;
variable fromInd, toInd : integer;
constant SINGLEROMLEN : integer := N_MEMDEPTH*DATAWIDTH;
begin
for rom in Cfg'range loop
for i in Cfg(0)'range loop
fromInd := rom*SINGLEROMLEN + (i+1)*DATAWIDTH-1;
toInd := rom*SINGLEROMLEN + i*DATAWIDTH;
Cfg(rom)(i) := CfgxD(fromInd downto toInd);
end loop;
end loop;
return Cfg;
end to_memoryConfig_arr;
-------------------------------------------------------------------------------
-- input and output driver configuration functions
-------------------------------------------------------------------------------
function init_inputDriverConfig return engineHBusNorthInputDriverArray is
variable Cfg : engineHBusNorthInputDriverArray;
begin
Cfg := (others => (others => (others => '0')));
return Cfg;
end init_inputDriverConfig;
function init_outputDriverConfig return engineHBusNorthOutputDriverArray is
variable Cfg : engineHBusNorthOutputDriverArray;
begin
Cfg := (others => (others => (others => '0')));
return Cfg;
end init_outputDriverConfig;
function to_inputDriverConfig_vec (Cfg : engineHBusNorthInputDriverArray)
return std_logic_vector is
variable vec : std_logic_vector(INPDRV_CFGLEN-1 downto 0);
begin
for inp in Cfg'range loop
for row in Cfg(0)'range loop
for p in Cfg(0)(0)'range loop
vec( (inp*Cfg(0)'length + row)*Cfg(0)(0)'length + p) := Cfg(inp)(row)(p);
end loop; -- p
end loop; -- row
end loop; -- inp
return vec;
end to_inputDriverConfig_vec;
function to_outputDriverConfig_vec (Cfg : engineHBusNorthOutputDriverArray)
return std_logic_vector is
variable vec : std_logic_vector(OUTPDRV_CFGLEN-1 downto 0);
begin
for outp in Cfg'range loop
for row in Cfg(0)'range loop
for p in Cfg(0)(0)'range loop
vec( (outp*Cfg(0)'length + row)*Cfg(0)(0)'length + p) := Cfg(outp)(row)(p);
end loop; -- p
end loop; -- row
end loop; -- outp
return vec;
end to_outputDriverConfig_vec;
function to_inputDriverConfig_arr (
vec : std_logic_vector(INPDRV_CFGLEN-1 downto 0))
return engineHBusNorthInputDriverArray is
variable Cfg : engineHBusNorthInputDriverArray;
begin
for inp in Cfg'range loop
for row in Cfg(0)'range loop
for p in Cfg(0)(0)'range loop
Cfg(inp)(row)(p) := vec( (inp*Cfg(0)'length + row)*Cfg(0)(0)'length + p);
end loop; -- p
end loop; -- row
end loop; -- inp
return Cfg;
end to_inputDriverConfig_arr;
function to_outputDriverConfig_arr (
vec : std_logic_vector(INPDRV_CFGLEN-1 downto 0))
return engineHBusNorthOutputDriverArray is
variable Cfg : engineHBusNorthOutputDriverArray;
begin
for outp in Cfg'range loop
for row in Cfg(0)'range loop
for p in Cfg(0)(0)'range loop
Cfg(outp)(row)(p) := vec( (outp*Cfg(0)'length + row)*Cfg(0)(0)'length + p);
end loop; -- p
end loop; -- row
end loop; -- outp
return Cfg;
end to_outputDriverConfig_arr;
-- initializes an engineConfig record
function init_engineConfig return engineConfigRec is
variable Cfg : engineConfigRec;
begin
Cfg.gridConf := init_gridConfig;
Cfg.inputDriverConf := init_inputDriverConfig;
Cfg.outputDriverConf := init_outputDriverConfig;
Cfg.inportConf := init_inportConfig;
Cfg.outportConf := init_outportConfig;
Cfg.memoryConf := init_memoryConfig;
return Cfg;
end init_engineConfig;
-- type procConfigRec is
-- record
-- OpMuxS : procInputMuxArray; -- PE_CFGLEN-1 downto bnd0
-- OpCtxRegSelxS : procInputCtxRegSelectArray; -- bnd0-1 downto bnd1
-- OutMuxS : procOutputMux; -- bnd1-1 downto bnd2
-- OutCtxRegSelxS : procOutputCtxRegSelect; -- bnd2-1 downto bnd3
-- AluOpxS : aluOpType; -- bnd3-1 downto bnd4
-- ConstOpxD : data_word; -- bnd4-1 downto 0
-- end record;
-- converts a procConfig record to a vector
function to_procConfig_vec (Cfg : procConfigRec) return std_logic_vector is
variable vec : std_logic_vector(PE_CFGLEN-1 downto 0);
constant bnd0 : natural := PE_CFGLEN - Cfg.OpMuxS'length*Cfg.OpMuxS(0)'length;
constant bnd1 : natural := bnd0 - Cfg.OpCtxRegSelxS'length*Cfg.OpCtxRegSelxS(0)'length;
constant bnd2 : natural := bnd1 - Cfg.OutMuxS'length;
constant bnd3 : natural := bnd2 - Cfg.OutCtxRegSelxS'length;
constant bnd4 : natural := bnd3 - ALUOPWIDTH;
begin
for inp in Cfg.OpMuxS'range loop
vec((inp+1)*Cfg.OpMuxS(0)'length-1+bnd0 downto
inp*Cfg.OpMuxS(0)'length+bnd0) := Cfg.OpMuxS(inp);
end loop;
for inp in Cfg.OpMuxS'range loop
vec((inp+1)*Cfg.OpCtxRegSelxS(0)'length-1+bnd1
downto inp*Cfg.OpCtxRegSelxS(0)'length+bnd1) := Cfg.OpCtxRegSelxS(inp);
end loop; -- inp
vec(bnd1-1 downto bnd2) := Cfg.OutMuxS;
vec(bnd2-1 downto bnd3) := Cfg.OutCtxRegSelxS;
vec(bnd3-1 downto bnd4) := std_logic_vector(to_unsigned(Cfg.AluOpxS, ALUOPWIDTH));
vec(bnd4-1 downto 0) := Cfg.ConstOpxD;
return vec;
end to_procConfig_vec;
-- converts a procConfig vector to a record
function to_procConfig_rec (CfgxD : std_logic_vector(PE_CFGLEN-1 downto 0))
return procConfigRec
is
variable rec : procConfigRec;
constant bnd0 : natural := PE_CFGLEN - rec.OpMuxS'length*rec.OpMuxS(0)'length;
constant bnd1 : natural := bnd0 - rec.OpCtxRegSelxS'length*rec.OpCtxRegSelxS(0)'length;
constant bnd2 : natural := bnd1 - rec.OutMuxS'length;
constant bnd3 : natural := bnd2 - rec.OutCtxRegSelxS'length;
constant bnd4 : natural := bnd3 - ALUOPWIDTH;
begin
for inp in rec.OpMuxS'range loop
rec.OpMuxS(inp) := CfgxD((inp+1)*rec.OpMuxS(0)'length-1+bnd0 downto
inp*rec.OpMuxS(0)'length+bnd0);
end loop; -- inp
for inp in rec.OpCtxRegSelxS'range loop
rec.OpCtxRegSelxS(inp) := CfgxD((inp+1)*rec.OpCtxRegSelxS(0)'length-1+bnd1
downto inp*rec.OpCtxRegSelxS(0)'length+bnd1);
end loop; -- inp
rec.OutMuxS := CfgxD(bnd1-1 downto bnd2);
rec.OutCtxRegSelxS := CfgxD(bnd2-1 downto bnd3);
rec.AluOpxS := to_integer(unsigned(CfgxD(bnd3-1 downto bnd4)));
rec.ConstOpxD := CfgxD(bnd4-1 downto 0);
return rec;
end to_procConfig_rec;
-- converts a routConfig record to a vector
function to_routConfig_vec (Cfg : routConfigRec) return std_logic_vector is
constant OUTPLEN : integer := Cfg.o.HBusNxE'length +
Cfg.o.HBusSxE'length +
Cfg.o.VBusExE'length;
constant INPLEN : integer := Cfg.i'length*(Cfg.i(0).LocalxE'length +
Cfg.i(0).HBusNxE'length +
Cfg.i(0).HBusSxE'length +
Cfg.i(0).VBusExE'length);
variable vec_inp : std_logic_vector(INPLEN-1 downto 0);
variable vec_outp : std_logic_vector(OUTPLEN-1 downto 0);
variable vec : std_logic_vector(RE_CFGLEN-1 downto 0);
variable start, bnd0, bnd1, bnd2, bnd3, bnd4, bnd5, bnd6 : integer;
begin
-- convert configuration for inputs to vector
for inp in Cfg.i'range loop
start := (inp+1)*CELLROUTINGINPUTCONFIGREC_LEN;
bnd0 := start - N_LOCALCON;
bnd1 := bnd0 - N_HBUSN;
bnd2 := bnd1 - N_HBUSS;
bnd3 := bnd2 - N_VBUSE;
vec_inp(start-1 downto bnd0) := Cfg.i(inp).LocalxE;
vec_inp(bnd0-1 downto bnd1) := Cfg.i(inp).HBusNxE;
vec_inp(bnd1-1 downto bnd2) := Cfg.i(inp).HBusSxE;
vec_inp(bnd2-1 downto bnd3) := Cfg.i(inp).VBusExE;
end loop; -- inp
-- convert configuration for output to vector
bnd4 := OUTPLEN - N_HBUSN;
bnd5 := bnd4 - N_HBUSS;
bnd6 := bnd5 - N_VBUSE;
vec_outp(OUTPLEN-1 downto bnd4) := Cfg.o.HBusNxE;
vec_outp(bnd4-1 downto bnd5) := Cfg.o.HBusSxE;
vec_outp(bnd5-1 downto bnd6) := Cfg.o.VBusExE;
vec := vec_inp & vec_outp;
return vec;
end to_routConfig_vec;
-- converts a routConfig vector to a record
function to_routConfig_rec (CfgxD : std_logic_vector(RE_CFGLEN-1 downto 0))
return routConfigRec
is
variable CfgRec : routConfigRec;
constant OUTPLEN : integer := CfgRec.o.HBusNxE'length +
CfgRec.o.HBusSxE'length +
CfgRec.o.VBusExE'length;
constant INPLEN : integer := CfgRec.i'length*(CfgRec.i(0).LocalxE'length +
CfgRec.i(0).HBusNxE'length +
CfgRec.i(0).HBusSxE'length +
CfgRec.i(0).VBusExE'length);
variable CfgInpxD : std_logic_vector(INPLEN-1 downto 0);
variable CfgOutpxD : std_logic_vector(OUTPLEN-1 downto 0);
variable start, bnd0, bnd1, bnd2, bnd3, bnd4, bnd5, bnd6 : integer;
begin
CfgInpxD := CfgxD(RE_CFGLEN-1 downto RE_CFGLEN-INPLEN);
CfgOutpxD := CfgxD(OUTPLEN-1 downto 0);
-- convert configuration for inputs to record entries
for inp in CfgRec.i'range loop
start := (inp+1)*CELLROUTINGINPUTCONFIGREC_LEN;
bnd0 := start - N_LOCALCON;
bnd1 := bnd0 - N_HBUSN;
bnd2 := bnd1 - N_HBUSS;
bnd3 := bnd2 - N_VBUSE;
CfgRec.i(inp).LocalxE := CfgInpxD(start-1 downto bnd0);
CfgRec.i(inp).HBusNxE := CfgInpxD(bnd0-1 downto bnd1);
CfgRec.i(inp).HBusSxE := CfgInpxD(bnd1-1 downto bnd2);
CfgRec.i(inp).VBusExE := CfgInpxD(bnd2-1 downto bnd3);
end loop; -- inp
-- convert configuration for outputs to record entry
bnd4 := OUTPLEN-N_HBUSN;
bnd5 := bnd4-N_HBUSS;
bnd6 := bnd5-N_VBUSE;
CfgRec.o.HBusNxE := CfgOutpxD(OUTPLEN-1 downto bnd4);
CfgRec.o.HBusSxE := CfgOutpxD(bnd4-1 downto bnd5);
CfgRec.o.VBusExE := CfgOutpxD(bnd5-1 downto bnd6);
return CfgRec;
end to_routConfig_rec;
-- converts a cellConfig record to a vector
function to_cellConfig_vec (Cfg : cellConfigRec) return std_logic_vector is
variable vec : std_logic_vector(CELL_CFGLEN-1 downto 0);
begin
vec := to_procConfig_vec(Cfg.procConf) & to_routConfig_vec(Cfg.routConf);
return vec;
end to_cellConfig_vec;
-- converts a cellConfig vector to a record
function to_cellConfig_rec (CfgxD : std_logic_vector(CELL_CFGLEN-1 downto 0))
return cellConfigRec
is
variable rec : cellConfigRec;
begin
rec.procConf := to_procConfig_rec(CfgxD(CELL_CFGLEN-1 downto RE_CFGLEN));
rec.routConf := to_routConfig_rec(CfgxD(RE_CFGLEN-1 downto 0));
return rec;
end to_cellConfig_rec;
-- converts a rowConfig array to a vector
function to_rowConfig_vec (Cfg : rowConfigArray) return std_logic_vector is
variable vec : std_logic_vector(ROW_CFGLEN-1 downto 0);
begin
for i in Cfg'range loop
vec(CELL_CFGLEN*(i+1)-1 downto CELL_CFGLEN*i) :=
to_cellConfig_vec(Cfg(i));
end loop; -- i
return vec;
end to_rowConfig_vec;
-- converts a rowConfig vector to an array
function to_rowConfig_arr (CfgxD : std_logic_vector(ROW_CFGLEN-1 downto 0))
return rowConfigArray
is
variable arr : rowConfigArray;
begin
for i in arr'range loop
arr(i) :=
to_cellConfig_rec(CfgxD(CELL_CFGLEN*(i+1)-1 downto CELL_CFGLEN*i));
end loop; -- i
return arr;
end to_rowConfig_arr;
-- converts a gridConfig array to a vector
function to_gridConfig_vec (Cfg : gridConfigArray) return std_logic_vector is
variable vec : std_logic_vector(GRID_CFGLEN-1 downto 0);
begin
for i in Cfg'range loop
vec(ROW_CFGLEN*(i+1)-1 downto ROW_CFGLEN*i) := to_rowConfig_vec(Cfg(i));
end loop; -- i
return vec;
end to_gridConfig_vec;
-- converts a gridConfig vector to an array
function to_gridConfig_arr (CfgxD : std_logic_vector(GRID_CFGLEN-1 downto 0))
return gridConfigArray
is
variable arr : gridConfigArray;
begin
for i in arr'range loop
arr(i) :=
to_rowConfig_arr(CfgxD(ROW_CFGLEN*(i+1)-1 downto ROW_CFGLEN*i));
end loop; -- i
return arr;
end to_gridConfig_arr;
-- converts an ioportConfig record to a vector
function to_ioportConfig_vec (Cfg : ioportConfigRec) return std_logic_vector
is
variable vec : std_logic_vector(PORT_CFGLEN-1 downto 0);
begin
vec := Cfg.LUT4FunctxD & Cfg.Cmp0MuxS & Cfg.Cmp1MuxS & Cfg.Cmp0ModusxS &
Cfg.Cmp1ModusxS & Cfg.Cmp0ConstxD & Cfg.Cmp1ConstxD;
return vec;
end to_ioportConfig_vec;
-- converts an ioportConfig vector to a record
function to_ioportConfig_rec (
CfgxD : std_logic_vector(PORT_CFGLEN-1 downto 0))
return ioportConfigRec
is
variable rec : ioportConfigRec;
variable clen : integer := rec.Cmp0ConstxD'length; -- constant length
begin
rec.LUT4FunctxD := CfgxD(PORT_CFGLEN-1 downto PORT_CFGLEN-16);
rec.Cmp0MuxS := CfgxD(PORT_CFGLEN-17);
rec.Cmp1MuxS := CfgxD(PORT_CFGLEN-18);
rec.Cmp0ModusxS := CfgxD(PORT_CFGLEN-19);
rec.Cmp1ModusxS := CfgxD(PORT_CFGLEN-20);
rec.Cmp0ConstxD := CfgxD(2*clen-1 downto clen);
rec.Cmp1ConstxD := CfgxD(clen-1 downto 0);
return rec;
end to_ioportConfig_rec;
function to_inportConfig_vec (Cfg : engineInportConfigArray)
return std_logic_vector
is
variable vec : std_logic_vector(INPORT_CFGLEN-1 downto 0);
begin
for inp in Cfg'range loop
vec((inp+1)*PORT_CFGLEN-1 downto inp*PORT_CFGLEN) :=
to_ioportConfig_vec(Cfg(inp));
end loop; -- inp
return vec;
end to_inportConfig_vec;
function to_outportConfig_vec (Cfg : engineOutportConfigArray)
return std_logic_vector
is
variable vec : std_logic_vector(OUTPORT_CFGLEN-1 downto 0);
begin
for outp in Cfg'range loop
vec((outp+1)*PORT_CFGLEN-1 downto outp*PORT_CFGLEN) :=
to_ioportConfig_vec(Cfg(outp));
end loop; -- outp
return vec;
end to_outportConfig_vec;
--FIXME
--Check code for splitting up vector into chunks of equal size
function to_outportConfig_arr (
CfgxD : std_logic_vector(OUTPORT_CFGLEN-1 downto 0))
return engineOutportConfigArray
is
variable arr : engineOutportConfigArray;
begin
for outp in arr'range loop
arr(outp) := to_ioportConfig_rec(CfgxD((outp+1)*PORT_CFGLEN-1 downto
outp*PORT_CFGLEN));
end loop; -- outp
return arr;
end to_outportConfig_arr;
function to_inportConfig_arr (
CfgxD : std_logic_vector(INPORT_CFGLEN-1 downto 0))
return engineInportConfigArray
is
variable arr : engineInportConfigArray;
begin
for inp in arr'range loop
arr(inp) := to_ioportConfig_rec(CfgxD((inp+1)*PORT_CFGLEN-1 downto
inp*PORT_CFGLEN));
end loop; -- inp
return arr;
end to_inportConfig_arr;
-- converts an engineConfig record to a vector
function to_engineConfig_vec (Cfg : engineConfigRec) return std_logic_vector
is
variable vec : std_logic_vector(ENGN_CFGLEN-1 downto 0);
begin
vec := to_gridConfig_vec(Cfg.gridConf) &
to_inputDriverConfig_vec(Cfg.inputDriverConf) &
to_outputDriverConfig_vec(Cfg.outputDriverConf) &
to_inportConfig_vec(Cfg.inportConf) &
to_outportConfig_vec(Cfg.outportConf) &
to_memoryConfig_vec(Cfg.memoryConf);
return vec;
end to_engineConfig_vec;
-- converts an engineConfig vector to a record
function to_engineConfig_rec (
CfgxD : std_logic_vector(ENGN_CFGLEN-1 downto 0))
return engineConfigRec
is
variable rec : engineConfigRec;
-- note: order is from last engineConfigRec entry to first
variable bnd0 : integer := MEM_CFGLEN;
variable bnd1 : integer := bnd0 + OUTPORT_CFGLEN;
variable bnd2 : integer := bnd1 + INPORT_CFGLEN;
variable bnd3 : integer := bnd2 + OUTPDRV_CFGLEN;
variable bnd4 : integer := bnd3 + INPDRV_CFGLEN;
begin
rec.gridConf := to_gridConfig_arr(CfgxD(ENGN_CFGLEN-1 downto bnd4));
rec.inputDriverConf := to_inputDriverConfig_arr(CfgxD(bnd4-1 downto bnd3));
rec.outputDriverConf := to_outputDriverConfig_arr(CfgxD(bnd3-1 downto bnd2));
rec.inportConf := to_inportConfig_arr(CfgxD(bnd2-1 downto bnd1));
rec.outportConf := to_outportConfig_arr(CfgxD(bnd1-1 downto bnd0));
rec.memoryConf := to_memoryConfig_arr(CfgxD(bnd0-1 downto 0));
return rec;
end to_engineConfig_rec;
-- partitions the configuration into partitions of equal widths
function partition_config (
signal CfgxD : std_logic_vector(ENGN_CFGLEN-1 downto 0))
return cfgPartArray
is
variable parts : cfgPartArray;
variable hi : natural;
variable lo : natural;
function std_resize (arg : std_logic_vector; new_size : natural)
return std_logic_vector
is
variable result : std_logic_vector(new_size downto 0) := (others => '0');
begin
return std_logic_vector(resize(unsigned(arg), new_size));
end std_resize;
begin -- partition_config
for i in parts'low to parts'high-1 loop
lo := PARTWIDTH * i;
hi := lo + PARTWIDTH - 1;
parts(i) := CfgxD(hi downto lo);
end loop; -- i
-- special treatment for the highest, probably shorter partition
lo := parts'high * PARTWIDTH;
hi := CfgxD'high;
parts(parts'high) := std_resize(CfgxD(hi downto lo), PARTWIDTH);
return parts;
end partition_config;
-- generate .h file for coupled simulation
procedure gen_cfghfile (file hfile : text; CfgArr : in cfgPartArray)
is
variable buf : line;
begin -- gen_cfghfile
-- comment
write(buf, string'("/* ZUnit configuration partitions "));
write(buf, string'("(automatically generated) */"));
writeline(hfile, buf);
write(buf, string'(""));
writeline(hfile, buf);
-- PARTWIDTH define
write(buf, string'("#define PARTWIDTH "));
write(buf, PARTWIDTH);
write(buf, string'(" /* partition width (bits) */"));
writeline(hfile, buf);
write(buf, string'(""));
writeline(hfile, buf);
-- NCFGPARTS define
write(buf, string'("#define NCFGPARTS "));
write(buf, CfgArr'length);
write(buf, string'(" /* no. of partitions */"));
writeline(hfile, buf);
write(buf, string'(""));
writeline(hfile, buf);
-- config. array
write(buf, string'("unsigned int config[NCFGPARTS] = {"));
writeline(hfile, buf);
for i in CfgArr'low to CfgArr'high loop
write(buf, string'(" 0X"));
hwrite(buf, std_logic_vector(CfgArr(i)));
if i < CfgArr'high then
write(buf, string'(","));
else
write(buf, string'(" "));
end if;
write(buf, string'(" /* "));
write(buf, CfgArr(i));
write(buf, string'("b, "));
write(buf, to_integer(unsigned(CfgArr(i))), right, 11);
write(buf, string'("d */"));
writeline(hfile, buf);
end loop; -- i
write(buf, string'(" };"));
writeline(hfile, buf);
end gen_cfghfile;
procedure gen_contexthfile2 (file hfile : text; cpArr : in contextPartArray)
is
variable buf : line;
variable cp : cfgPartArray;
begin -- gen_contexthfile2
-- comment
write(buf, string'("/* ZUnit multi-context configuration partitions "));
write(buf, string'("(automatically generated) */"));
writeline(hfile, buf);
write(buf, string'(""));
writeline(hfile, buf);
-- NCONTEXTS define
write(buf, string'("#define NCONTEXTS "));
write(buf, N_CONTEXTS);
write(buf, string'(" /* no. of contexts */"));
writeline(hfile, buf);
write(buf, string'(""));
writeline(hfile, buf);
-- PARTWIDTH define
write(buf, string'("#define PARTWIDTH "));
write(buf, PARTWIDTH);
write(buf, string'(" /* partition width (bits) */"));
writeline(hfile, buf);
write(buf, string'(""));
writeline(hfile, buf);
-- NCFGPARTS define
write(buf, string'("#define NCFGPARTS "));
write(buf, cp'length);
write(buf, string'(" /* no. of partitions */"));
writeline(hfile, buf);
write(buf, string'(""));
writeline(hfile, buf);
-- contexts
write(buf, string'("unsigned int contextdata"));
write(buf, string'("[NCONTEXTS][NCFGPARTS] = {"));
writeline(hfile, buf);
for c in 0 to N_CONTEXTS-1 loop
cp := cpArr(c);
write(buf, string'(" /* context "));
write(buf, c);
write(buf, string'(" */"));
writeline(hfile, buf);
write(buf, string'(" {"));
writeline(hfile, buf);
for i in cp'low to cp'high loop
write(buf, string'(" 0X"));
hwrite(buf, std_logic_vector(cp(i)));
if i < cp'high then
write(buf, string'(","));
else
write(buf, string'(" "));
end if;
write(buf, string'(" /* "));
write(buf, cp(i));
write(buf, string'("b, "));
write(buf, to_integer(unsigned(cp(i))), right, 11);
write(buf, string'("d */"));
writeline(hfile, buf);
end loop; -- i
write(buf, string'(" }"));
if c < N_CONTEXTS-1 then
write(buf, string'(","));
end if;
writeline(hfile, buf);
end loop; -- c
write(buf, string'("};"));
writeline(hfile, buf);
end gen_contexthfile2;
end ConfigPkg;
|
bsd-3-clause
|
plessl/zippy
|
vhdl/testbenches/tb_contextregfile.vhd
|
1
|
6610
|
------------------------------------------------------------------------------
-- Testbench for contextregfile.vhd
--
-- Project :
-- File : tb_contextregfile.vhd
-- Author : Rolf Enzler <[email protected]>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Created : 2003/03/06
-- Last changed: $LastChangedDate: 2004-10-05 17:10:36 +0200 (Tue, 05 Oct 2004) $
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.componentsPkg.all;
use work.auxPkg.all;
entity tb_ContextRegFile is
end tb_ContextRegFile;
architecture arch of tb_ContextRegFile is
constant NCONTEXTS : integer := 8;
constant WIDTH : integer := 16;
-- simulation stuff
constant CLK_PERIOD : time := 100 ns;
signal ccount : integer := 1;
type tbstatusType is (rst, idle, done, reg1, clr3, wrall, rdall, clrall);
signal tbStatus : tbstatusType := idle;
-- general control signals
signal ClkxC : std_logic := '1';
signal RstxRB : std_logic;
-- DUT signals
signal ClrContextxSI : std_logic_vector(log2(NCONTEXTS)-1 downto 0);
signal ClrContextxEI : std_logic;
signal ContextxSI : std_logic_vector(log2(NCONTEXTS)-1 downto 0);
signal EnxEI : std_logic;
signal DinxDI : std_logic_vector(WIDTH-1 downto 0);
signal DoutxDO : std_logic_vector(WIDTH-1 downto 0);
begin -- arch
----------------------------------------------------------------------------
-- device under test
----------------------------------------------------------------------------
dut : ContextRegFile
generic map (
NCONTEXTS => NCONTEXTS,
WIDTH => WIDTH)
port map (
ClkxC => ClkxC,
RstxRB => RstxRB,
ClrContextxSI => ClrContextxSI,
ClrContextxEI => ClrContextxEI,
ContextxSI => ContextxSI,
EnxEI => EnxEI,
DinxDI => DinxDI,
DoutxDO => DoutxDO);
----------------------------------------------------------------------------
-- stimuli
----------------------------------------------------------------------------
stimuliTb : process
procedure init_stimuli (
signal ClrContextxSI : out std_logic_vector(log2(NCONTEXTS)-1 downto 0);
signal ClrContextxEI : out std_logic;
signal ContextxSI : out std_logic_vector(log2(NCONTEXTS)-1 downto 0);
signal EnxEI : out std_logic;
signal DinxDI : out std_logic_vector(WIDTH-1 downto 0)) is
begin
ClrContextxSI <= (others => '0');
ClrContextxEI <= '0';
ContextxSI <= (others => '0');
EnxEI <= '0';
DinxDI <= (others => '0');
end init_stimuli;
begin -- process stimuliTb
tbStatus <= rst;
init_stimuli(ClrContextxSI, ClrContextxEI, ContextxSI, EnxEI, DinxDI);
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '0');
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '1');
tbStatus <= idle;
wait for CLK_PERIOD*0.25;
-- enable and disable register 1
tbStatus <= reg1;
ContextxSI <= std_logic_vector(to_unsigned(1, log2(NCONTEXTS)));
EnxEI <= '1';
DinxDI <= std_logic_vector(to_unsigned(11, WIDTH));
wait for CLK_PERIOD;
EnxEI <= '0';
DinxDI <= std_logic_vector(to_unsigned(12, WIDTH));
wait for CLK_PERIOD;
EnxEI <= '1';
DinxDI <= std_logic_vector(to_unsigned(13, WIDTH));
wait for CLK_PERIOD;
EnxEI <= '0';
DinxDI <= std_logic_vector(to_unsigned(14, WIDTH));
wait for CLK_PERIOD;
EnxEI <= '1';
DinxDI <= std_logic_vector(to_unsigned(15, WIDTH));
wait for CLK_PERIOD;
EnxEI <= '1';
DinxDI <= std_logic_vector(to_unsigned(0, WIDTH));
wait for CLK_PERIOD;
tbStatus <= idle;
init_stimuli(ClrContextxSI, ClrContextxEI, ContextxSI, EnxEI, DinxDI);
wait for CLK_PERIOD;
-- write all
tbStatus <= wrall;
for c in 0 to NCONTEXTS-1 loop
ContextxSI <= std_logic_vector(to_unsigned(c, log2(NCONTEXTS)));
EnxEI <= '1';
DinxDI <= std_logic_vector(to_unsigned(c+10, WIDTH));
wait for CLK_PERIOD;
end loop; -- c
tbStatus <= idle;
init_stimuli(ClrContextxSI, ClrContextxEI, ContextxSI, EnxEI, DinxDI);
wait for CLK_PERIOD;
-- read all
tbStatus <= rdall;
for c in 0 to NCONTEXTS-1 loop
ContextxSI <= std_logic_vector(to_unsigned(c, log2(NCONTEXTS)));
wait for CLK_PERIOD;
end loop; -- c
tbStatus <= idle;
init_stimuli(ClrContextxSI, ClrContextxEI, ContextxSI, EnxEI, DinxDI);
wait for CLK_PERIOD;
-- clear register 3
tbstatus <= clr3;
ContextxSI <= std_logic_vector(to_unsigned(3, log2(NCONTEXTS)));
ClrContextxSI <= std_logic_vector(to_unsigned(3, log2(NCONTEXTS)));
ClrContextxEI <= '1';
wait for CLK_PERIOD;
wait for CLK_PERIOD;
tbStatus <= idle;
init_stimuli(ClrContextxSI, ClrContextxEI, ContextxSI, EnxEI, DinxDI);
wait for CLK_PERIOD;
-- clear all
tbstatus <= clrall;
for c in 0 to NCONTEXTS-1 loop
ClrContextxSI <= std_logic_vector(to_unsigned(c, log2(NCONTEXTS)));
ClrContextxEI <= '1';
wait for CLK_PERIOD;
end loop; -- c
-- read all
tbStatus <= rdall;
for c in 0 to NCONTEXTS-1 loop
ContextxSI <= std_logic_vector(to_unsigned(c, log2(NCONTEXTS)));
wait for CLK_PERIOD;
end loop; -- c
tbStatus <= idle;
init_stimuli(ClrContextxSI, ClrContextxEI, ContextxSI, EnxEI, DinxDI);
wait for CLK_PERIOD;
tbStatus <= done;
init_stimuli(ClrContextxSI, ClrContextxEI, ContextxSI, EnxEI, DinxDI);
wait for CLK_PERIOD;
-- stop simulation
wait until (ClkxC'event and ClkxC = '1');
assert false
report "stimuli processed; sim. terminated after " & int2str(ccount) &
" cycles"
severity failure;
end process stimuliTb;
----------------------------------------------------------------------------
-- clock and reset generation
----------------------------------------------------------------------------
ClkxC <= not ClkxC after CLK_PERIOD/2;
RstxRB <= '0', '1' after CLK_PERIOD*1.25;
----------------------------------------------------------------------------
-- cycle counter
----------------------------------------------------------------------------
cyclecounter : process (ClkxC)
begin
if (ClkxC'event and ClkxC = '1') then
ccount <= ccount + 1;
end if;
end process cyclecounter;
end arch;
|
bsd-3-clause
|
plessl/zippy
|
vhdl/tb_arch/tstpass_virt/tb_tstpass_virt.vhd
|
1
|
11887
|
------------------------------------------------------------------------------
-- Testbench for the tstpass_virt configuration
--
-- Project :
-- File : $Id: $
-- Author : Christian Plessl <[email protected]>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Changed : $LastChangedDate: 2004-10-26 14:50:34 +0200 (Tue, 26 Oct 2004) $
------------------------------------------------------------------------------
-- This testbench tests the tstpass_virt configuration
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
use work.txt_util.all;
use work.AuxPkg.all;
use work.archConfigPkg.all;
use work.ZArchPkg.all;
use work.ComponentsPkg.all;
use work.ConfigPkg.all;
use work.CfgLib_TSTPASS_VIRT.all;
entity tb_tstpass_virt is
end tb_tstpass_virt;
architecture arch of tb_tstpass_virt is
-- simulation stuff
constant CLK_PERIOD : time := 100 ns;
signal cycle : integer := 1;
constant NDATA : integer := 16; -- nr. of data elements
constant DELAY : integer := 1; -- processing delay of circuit,
-- due to pipeliningq
constant CONTEXTS : integer := 2;
constant NRUNCYCLES : integer := NDATA+DELAY; -- nr. of run cycles
type tbstatusType is (tbstart, idle, done, rst, wr_context0, wr_context1,
wr_context2, set_cmptr, set_cntxt,
push_data_fifo0, wr_ncycl, rd_ncycl, running,
outlevel, pop_data, finished);
signal tbStatus : tbstatusType := idle;
-- general control signals
signal ClkxC : std_logic := '1';
signal RstxRB : std_logic;
-- data/control signals
signal WExE : std_logic;
signal RExE : std_logic;
signal AddrxD : std_logic_vector(IFWIDTH-1 downto 0);
signal DataInxD : std_logic_vector(IFWIDTH-1 downto 0);
signal DataOutxD : std_logic_vector(IFWIDTH-1 downto 0);
-- configuration signals
signal Context0Cfg : engineConfigRec := tstpasscfg_p0;
signal Context1Cfg : engineConfigRec := tstpasscfg_p1;
signal Context0xD : std_logic_vector(ENGN_CFGLEN-1 downto 0) :=
to_engineConfig_vec(Context0Cfg);
signal Context1xD : std_logic_vector(ENGN_CFGLEN-1 downto 0) :=
to_engineConfig_vec(Context1Cfg);
signal Context0Prt : cfgPartArray := partition_config(Context0xD);
signal Context1Prt : cfgPartArray := partition_config(Context1xD);
file HFILE : text open write_mode is "tstpass_virt_cfg.h";
type tv_array is array (0 to NDATA-1) of integer;
constant TESTV : tv_array :=
( 1, 2, 3, 5,
7, 11, 13, 17,
19, 23, 29, 31,
37, 41, 43, 47);
constant EXPRES : tv_array :=
( 1, 3, 6, 11,
18, 29, 42, 59,
78, 101, 130, 161,
198, 239, 282, 329);
begin -- arch
----------------------------------------------------------------------------
-- device under test
----------------------------------------------------------------------------
dut : ZUnit
generic map (
IFWIDTH => IFWIDTH,
DATAWIDTH => DATAWIDTH,
CCNTWIDTH => CCNTWIDTH,
FIFODEPTH => FIFODEPTH)
port map (
ClkxC => ClkxC,
RstxRB => RstxRB,
WExEI => WExE,
RExEI => RExE,
AddrxDI => AddrxD,
DataxDI => DataInxD,
DataxDO => DataOutxD);
----------------------------------------------------------------------------
-- generate .h file for coupled simulation
----------------------------------------------------------------------------
hFileGen : process
variable contextArr : contextPartArray :=
(others => (others => (others => '0')));
begin -- process hFileGen
contextArr(0) := Context0Prt;
contextArr(1) := Context1Prt;
-- need only 2 contexts
gen_contexthfile2(HFILE, contextArr);
wait;
end process hFileGen;
----------------------------------------------------------------------------
-- stimuli
----------------------------------------------------------------------------
stimuliTb : process
variable response : integer;
variable expectedresponse : integer;
variable l : line;
begin -- process stimuliTb
tbStatus <= tbstart;
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '0');
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '1');
tbStatus <= idle;
-- wait for CLK_PERIOD*0.25;
wait for CLK_PERIOD*0.1;
tbStatus <= idle; -- idle
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
-------------------------------------------------
-- reset (ZREG_RST:W)
-------------------------------------------------
tbStatus <= rst;
WExE <= '1';
RExE <= '0';
AddrxD <= std_logic_vector(to_unsigned(ZREG_RST, IFWIDTH));
DataInxD <= std_logic_vector(to_signed(0, IFWIDTH));
wait for CLK_PERIOD;
tbStatus <= idle; -- idle
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
wait for CLK_PERIOD;
-- -----------------------------------------------
-- write configuration slices to context mem 0 (ZREG_CFGMEM0:W)
-- -----------------------------------------------
tbStatus <= wr_context0;
WExE <= '1';
RExE <= '0';
AddrxD <= std_logic_vector(to_unsigned(ZREG_CFGMEM0, IFWIDTH));
for i in Context0Prt'low to Context0Prt'high loop
DataInxD <= Context0Prt(i);
wait for CLK_PERIOD;
end loop; -- i
tbStatus <= idle; -- idle
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
wait for CLK_PERIOD;
-- -----------------------------------------------
-- write configuration slices to context mem 1 (ZREG_CFGMEM1:W)
-- -----------------------------------------------
tbStatus <= wr_context1;
WExE <= '1';
RExE <= '0';
AddrxD <= std_logic_vector(to_unsigned(ZREG_CFGMEM1, IFWIDTH));
for i in Context1Prt'low to Context1Prt'high loop
DataInxD <= Context1Prt(i);
wait for CLK_PERIOD;
end loop; -- i
tbStatus <= idle; -- idle
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
wait for CLK_PERIOD;
-------------------------------------------------
-- push data into FIFO0 (ZREG_FIFO0:W)
-------------------------------------------------
tbStatus <= push_data_fifo0;
WExE <= '1';
RExE <= '0';
AddrxD <= std_logic_vector(to_unsigned(ZREG_FIFO0, IFWIDTH));
for i in 0 to NDATA-1 loop
DataInxD <= (others => '0');
DataInxD(DATAWIDTH-1 downto 0) <=
std_logic_vector(to_unsigned(TESTV(i),DATAWIDTH));
-- assert false
-- report "writing to FIFO0:" & hstr(TESTV(i*3))
-- severity note;
wait for CLK_PERIOD;
end loop; -- i
tbStatus <= idle; -- idle
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
wait for CLK_PERIOD;
for runcycle in 0 to NDATA+DELAY-1 loop
for context in 0 to CONTEXTS-1 loop
-- set context select register (ZREG_CONTEXTSEL:W)
tbStatus <= set_cntxt;
WExE <= '1';
RExE <= '0';
AddrxD <= std_logic_vector(to_unsigned(ZREG_CONTEXTSEL, IFWIDTH));
DataInxD <= std_logic_vector(to_signed(context, IFWIDTH));
wait for CLK_PERIOD;
-- write cycle count register (ZREG_CYCLECNT:W)
tbStatus <= wr_ncycl;
WExE <= '1';
RExE <= '0';
AddrxD <= std_logic_vector(to_unsigned(ZREG_CYCLECNT, IFWIDTH));
DataInxD <= std_logic_vector(to_signed(1, IFWIDTH));
wait for CLK_PERIOD;
-- run computation of current context
tbStatus <= running;
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
end loop; -- context
end loop; -- runcycle
-------------------------------------------------
-- pop 1 words from out buffer (ZREG_FIFO1:R)
-- delay of circuit due to registers (pipelining)
-------------------------------------------------
tbStatus <= pop_data;
WExE <= '0';
RExE <= '1';
DataInxD <= (others => '0');
AddrxD <= std_logic_vector(to_unsigned(ZREG_FIFO1, IFWIDTH));
wait for DELAY*CLK_PERIOD;
-------------------------------------------------
-- pop data from out buffer (ZREG_FIFO1:R)
-------------------------------------------------
tbStatus <= pop_data;
WExE <= '0';
RExE <= '1';
DataInxD <= (others => '0');
AddrxD <= std_logic_vector(to_unsigned(ZREG_FIFO1, IFWIDTH));
for i in 0 to NDATA-1 loop
wait for CLK_PERIOD;
response := to_integer(signed(DataOutxD(DATAWIDTH-1 downto 0)));
expectedresponse := EXPRES(i);
assert response = expectedresponse
report "FAILURE--FAILURE--FAILURE--FAILURE--FAILURE--FAILURE" & LF &
"regression test failed, response " & str(response) &
" does NOT match expected response "
& str(expectedresponse) & " tv: " & str(i) & LF &
"FAILURE--FAILURE--FAILURE--FAILURE--FAILURE--FAILURE"
severity failure;
assert not(response = expectedresponse)
report "response " & str(response) & " matches expected " &
"response " & str(expectedresponse) & " tv: " & str(i)
severity note;
end loop; -- i
tbStatus <= idle; -- idle
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
-----------------------------------------------
-- done stop simulation
-----------------------------------------------
tbStatus <= done; -- done
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
---------------------------------------------------------------------------
-- stopping the simulation is done by using the following TCL script
-- in modelsim, since terminating the simulation with an assert failure is
-- a crude hack:
--
-- when {/tbStatus == done} {
-- echo "At Time $now Ending the simulation"
-- quit -f
-- }
---------------------------------------------------------------------------
-- stop simulation
wait until (ClkxC'event and ClkxC = '1');
assert false
report "Testbench successfully terminated after " & str(cycle) &
" cycles, no errors found!"
severity failure;
end process stimuliTb;
----------------------------------------------------------------------------
-- clock and reset generation
----------------------------------------------------------------------------
ClkxC <= not ClkxC after CLK_PERIOD/2;
RstxRB <= '0', '1' after CLK_PERIOD*1.25;
----------------------------------------------------------------------------
-- cycle counter
----------------------------------------------------------------------------
cyclecounter : process (ClkxC)
begin
if (ClkxC'event and ClkxC = '1') then
cycle <= cycle + 1;
end if;
end process cyclecounter;
end arch;
|
bsd-3-clause
|
plessl/zippy
|
vhdl/tb_arch/tstadpcm_virt/tstadpcm_virt_cfg.template.vhd
|
1
|
4934
|
------------------------------------------------------------------------------
-- Configuration for ADPCM application with virtualized execution on a
-- 4x4 zippy array
--
-- Id : $Id: $
-- File : $Url: $
-- Author : Christian Plessl <[email protected]>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Created : 2004/10/27
-- Changed : $LastChangedDate: 2004-10-26 14:50:34 +0200 (Tue, 26 Oct 2004) $
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.ZArchPkg.all;
use work.ConfigPkg.all;
------------------------------------------------------------------------------
-- Package Declaration
------------------------------------------------------------------------------
package CfgLib_TSTADPCM_VIRT is
function tstadpcmcfg_p0 return engineConfigRec;
function tstadpcmcfg_p1 return engineConfigRec;
function tstadpcmcfg_p2 return engineConfigRec;
end CfgLib_TSTADPCM_VIRT;
------------------------------------------------------------------------------
-- Package Body
------------------------------------------------------------------------------
package body CfgLib_TSTADPCM_VIRT is
---------------------------------------------------------------------------
-- ROM DATA
---------------------------------------------------------------------------
type indextable_arr is array (0 to 15) of integer;
constant INDEXTABLE : indextable_arr := (
-1, -1, -1, -1, 2, 4, 6, 8,
-1, -1, -1, -1, 2, 4, 6, 8
);
type stepsizetable_arr is array (0 to 88) of integer;
constant STEPSIZETABLE : stepsizetable_arr := (
7, 8, 9, 10, 11, 12, 13, 14, 16, 17,
19, 21, 23, 25, 28, 31, 34, 37, 41, 45,
50, 55, 60, 66, 73, 80, 88, 97, 107, 118,
130, 143, 157, 173, 190, 209, 230, 253, 279, 307,
337, 371, 408, 449, 494, 544, 598, 658, 724, 796,
876, 963, 1060, 1166, 1282, 1411, 1552, 1707, 1878, 2066,
2272, 2499, 2749, 3024, 3327, 3660, 4026, 4428, 4871, 5358,
5894, 6484, 7132, 7845, 8630, 9493, 10442, 11487, 12635, 13899,
15289, 16818, 18500, 20350, 22385, 24623, 27086, 29794, 32767
);
----------------------------------------------------------------------------
-- tstadpcm partition p0 configuration
----------------------------------------------------------------------------
function tstadpcmcfg_p0 return engineConfigRec is
variable cfg : engineConfigRec := init_engineConfig;
begin
-- ############# begin configuration of partition 0 ###################
-- ############# end configuration of partition 0 ###################
-- initialize ROM
-- ROM index table (op0) is mapped to cell c_3_0
for i in INDEXTABLE'range loop
cfg.memoryConf(3)(i) :=
std_logic_vector(to_signed(INDEXTABLE(i), DATAWIDTH));
end loop; -- i
-- ROM stepsize table (op19) is mapped to cell c_2_1
for i in STEPSIZETABLE'range loop
cfg.memoryConf(2)(i) :=
std_logic_vector(to_signed(STEPSIZETABLE(i), DATAWIDTH));
end loop; -- i
-- IO port configuration
cfg.inportConf(0).LUT4FunctxD := CFG_IOPORT_OFF;
cfg.inportConf(1).LUT4FunctxD := CFG_IOPORT_OFF;
cfg.outportConf(0).LUT4FunctxD := CFG_IOPORT_OFF;
cfg.outportConf(1).LUT4FunctxD := CFG_IOPORT_OFF;
return cfg;
end tstadpcmcfg_p0;
----------------------------------------------------------------------------
-- tstadpcm partition p1 configuration
----------------------------------------------------------------------------
function tstadpcmcfg_p1 return engineConfigRec is
variable cfg : engineConfigRec := init_engineConfig;
begin
-- ############# begin configuration of partition 1 ###################
-- ############# end configuration of partition 1 ###################
-- IO port configuration
cfg.inportConf(0).LUT4FunctxD := CFG_IOPORT_OFF;
cfg.inportConf(1).LUT4FunctxD := CFG_IOPORT_OFF;
cfg.outportConf(0).LUT4FunctxD := CFG_IOPORT_OFF;
cfg.outportConf(1).LUT4FunctxD := CFG_IOPORT_OFF;
return cfg;
end tstadpcmcfg_p1;
----------------------------------------------------------------------------
-- tstadpcm partition p2 configuration
----------------------------------------------------------------------------
function tstadpcmcfg_p2 return engineConfigRec is
variable cfg : engineConfigRec := init_engineConfig;
begin
-- ############# begin configuration of partition 2 ###################
-- ############# end configuration of partition 2 ###################
-- IO port configuration
cfg.inportConf(0).LUT4FunctxD := CFG_IOPORT_ON;
cfg.inportConf(1).LUT4FunctxD := CFG_IOPORT_OFF;
cfg.outportConf(0).LUT4FunctxD := CFG_IOPORT_OFF;
cfg.outportConf(1).LUT4FunctxD := CFG_IOPORT_ON;
return cfg;
end tstadpcmcfg_p2;
end CfgLib_TSTADPCM_VIRT;
|
bsd-3-clause
|
plessl/zippy
|
vhdl/flipflop.vhd
|
1
|
2132
|
------------------------------------------------------------------------------
-- Flip-Flops
--
-- Project :
-- File : $URL: svn+ssh://[email protected]/home/plessl/SVN/simzippy/trunk/vhdl/flipflop.vhd $
-- Authors : Rolf Enzler <[email protected]>
-- Christian Plessl <[email protected]>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Created : 2003/03/07
-- $Id: flipflop.vhd 241 2005-04-07 08:50:55Z plessl $
------------------------------------------------------------------------------
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity FlipFlop is
port (
ClkxC : in std_logic;
RstxRB : in std_logic;
EnxEI : in std_logic;
DinxDI : in std_logic;
DoutxDO : out std_logic);
end FlipFlop;
architecture simple of FlipFlop is
begin -- simple
FF : process (ClkxC, RstxRB)
begin -- process Reg
if RstxRB = '0' then -- asynchronous reset (active low)
DoutxDO <= '0';
elsif ClkxC'event and ClkxC = '1' then -- rising clock edge
if EnxEI = '1' then
DoutxDO <= DinxDI;
end if;
end if;
end process FF;
end simple;
------------------------------------------------------------------------------
-- Flip-Flop with Clear
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity FlipFlop_Clr is
port (
ClkxC : in std_logic;
RstxRB : in std_logic;
ClrxEI : in std_logic;
EnxEI : in std_logic;
DinxDI : in std_logic;
DoutxDO : out std_logic);
end FlipFlop_Clr;
architecture simple of FlipFlop_Clr is
begin -- simple
FF : process (ClkxC, RstxRB)
begin -- process Reg
if RstxRB = '0' then -- asynchronous reset (active low)
DoutxDO <= '0';
elsif ClkxC'event and ClkxC = '1' then -- rising clock edge
if ClrxEI = '1' then -- clear has precedence
DoutxDO <= '0';
elsif EnxEI = '1' then
DoutxDO <= DinxDI;
end if;
end if;
end process FF;
end simple;
|
bsd-3-clause
|
plessl/zippy
|
vhdl/counter.vhd
|
1
|
4130
|
------------------------------------------------------------------------------
-- Up/down counters
--
-- Project :
-- File : $Id: counter.vhd 173 2004-11-17 15:57:19Z plessl $
-- Authors : Rolf Enzler <[email protected]>
-- Christian Plessl <[email protected]>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Created : 2002/10/17
-- Changed : $LastChangedDate: 2004-11-17 16:57:19 +0100 (Wed, 17 Nov 2004) $
------------------------------------------------------------------------------
-- Loadable up counter with enable and reset
-- RstxRB resets the counter to low
-- On assertion of LoadxEI the counter is synchrounously loaded with
-- with CinxDI
-- Counting is enabled when CExEI is asserted
-------------------------------------------------------------------------------
-- Changes:
-- 2004-10-05 CP added documentation
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity UpCounter is
generic (
WIDTH : integer);
port (
ClkxC : in std_logic;
RstxRB : in std_logic;
LoadxEI : in std_logic;
CExEI : in std_logic;
CinxDI : in std_logic_vector(WIDTH-1 downto 0);
CoutxDO : out std_logic_vector(WIDTH-1 downto 0));
end UpCounter;
architecture simple of UpCounter is
signal CountxD : unsigned(WIDTH-1 downto 0);
begin -- simple
Count : process (ClkxC, RstxRB)
begin -- process Count
if RstxRB = '0' then -- asynchronous reset (active low)
CountxD <= (others => '0');
elsif ClkxC'event and ClkxC = '1' then -- rising clock edge
if LoadxEI = '1' then
CountxD <= unsigned(CinxDI);
elsif CExEI = '1' then
CountxD <= CountxD + 1;
end if;
end if;
end process Count;
CoutxDO <= std_logic_vector(CountxD);
end simple;
------------------------------------------------------------------------------
-- Up/down counter
--
-- Project :
-- File : updowncounter.vhd
-- Authors : Rolf Enzler <[email protected]>
-- Christian Plessl <[email protected]>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Created : 2003/01/21
-- Last changed: $LastChangedDate: 2004-11-17 16:57:19 +0100 (Wed, 17 Nov 2004) $
------------------------------------------------------------------------------
-- Loadable up/down counter with enable and reset
-- RstxRB resets the counter to low
-- On assertion of LoadxEI the counter is synchrounously loaded with
-- with CinxDI
-- Counting is enabled when CExEI is asserted
-- ModexSI = 0 enables counting up, ModexSI=1 enables counting down
-------------------------------------------------------------------------------
-- Changes:
-- 2004-10-05 CP added documentation
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity UpDownCounter is
generic (
WIDTH : integer);
port (
ClkxC : in std_logic;
RstxRB : in std_logic;
LoadxEI : in std_logic;
CExEI : in std_logic;
ModexSI : in std_logic;
CinxDI : in std_logic_vector(WIDTH-1 downto 0);
CoutxDO : out std_logic_vector(WIDTH-1 downto 0));
end UpDownCounter;
architecture simple of UpDownCounter is
signal CountxD : signed(WIDTH-1 downto 0);
begin -- simple
Count : process (ClkxC, RstxRB)
begin -- process Count
if RstxRB = '0' then -- asynchronous reset (active low)
CountxD <= (others => '0');
elsif ClkxC'event and ClkxC = '1' then -- rising clock edge
if (LoadxEI = '1') then -- load counter
CountxD <= signed(CinxDI);
elsif (CExEI = '1') then -- enable counter
if (ModexSI = '0') then
CountxD <= CountxD + 1; -- count up
else
CountxD <= CountxD - 1; -- count down
end if;
end if;
end if;
end process Count;
CoutxDO <= std_logic_vector(CountxD);
end simple;
|
bsd-3-clause
|
plessl/zippy
|
vhdl/tb_arch/tstpass_virt/tstpass_virt_archConfigPkg.vhd
|
9
|
1871
|
------------------------------------------------------------------------------
-- Configurable parameters for the ZIPPY architecture
--
-- Project :
-- File : zarchPkg.vhd
-- Authors : Christian Plessl <[email protected]>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Last changed: $LastChangedDate: 2005-01-12 12:28:20 +0100 (Wed, 12 Jan 2005) $
------------------------------------------------------------------------------
-- This file declares the user configurable architecture parameters for the
-- zippy architecture.
-- These parameters can/shall be modified by the user for defining a Zippy
-- architecture variant that is suited for the application at hand.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.auxPkg.all;
package archConfigPkg is
----------------------------------------------------------------------------
-- User configurable architecture parameter
----------------------------------------------------------------------------
constant DATAWIDTH : integer := 24; -- data path width
constant FIFODEPTH : integer := 4096; -- FIFO depth
constant N_CONTEXTS : integer := 8; -- no. of contexts
constant CNTXTWIDTH : integer := log2(N_CONTEXTS);
constant N_COLS : integer := 4; -- no. of columns (cells per row)
constant N_ROWS : integer := 4; -- no. of rows
constant N_HBUSN : integer := 2; -- no. of horizontal north buses
constant N_HBUSS : integer := 2; -- no. of horizontal south buses
constant N_VBUSE : integer := 2; -- no. of vertical east buses
constant N_MEMADDRWIDTH : integer := 7;
constant N_MEMDEPTH : integer := 2**N_MEMADDRWIDTH;
end archConfigPkg;
package body archConfigPkg is
end archConfigPkg;
|
bsd-3-clause
|
plessl/zippy
|
vhdl/tb_arch/tstbitat0/tb_tstbitat0.vhd
|
1
|
12369
|
------------------------------------------------------------------------------
-- Testbench for the tstbitat0 function of the zunit
--
-- Project :
-- File : $URL: svn+ssh://[email protected]/home/plessl/SVN/simzippy/trunk/vhdl/tb_arch/tstbitat0/tb_tstbitat0.vhd $
-- Author : Christian Plessl <[email protected]>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Created : 2004/10/26
-- Last changed: $LastChangedDate: 2005-01-13 17:52:03 +0100 (Thu, 13 Jan 2005) $
-- $Id: tb_tstbitat0.vhd 217 2005-01-13 16:52:03Z plessl $
------------------------------------------------------------------------------
-- This testbench tests the tstbitat0 function of the zunit.
--
-- The primary goal of this testbench is to provide an example of a testbench
-- that can be used for standalone simulation and co-simulation to verify the
-- correct function of the zunit.
--
-- There a 2 main purposes of the testbench:
-- a) specific testing of newly added components and features
-- b) regression testing of the whole architecture
-------------------------------------------------------------------------------
-- Changes:
-- 2004-10-05 CP created (based on the tb_zarch testbench by Rolf Enzler)
-- 2004-10-26 CP extended for automated verification of testvectors
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
use work.txt_util.all;
use work.AuxPkg.all;
use work.archConfigPkg.all;
use work.ZArchPkg.all;
use work.ComponentsPkg.all;
use work.ConfigPkg.all;
use work.CfgLib_TSTBITAT0.all;
entity tb_tstbitat0 is
end tb_tstbitat0;
architecture arch of tb_tstbitat0 is
-- simulation stuff
constant CLK_PERIOD : time := 100 ns;
signal cycle : integer := 1;
constant NDATA : integer := 6; -- nr. of data elements
constant NRUNCYCLES : integer := NDATA+2; -- nr. of run cycles
type tbstatusType is (tbstart, idle, done, rst, wr_cfg, set_cmptr,
push_data_fifo0, push_data_fifo1, inlevel,
wr_ncycl, rd_ncycl, running,
outlevel, pop_data, finished);
signal tbStatus : tbstatusType := idle;
-- general control signals
signal ClkxC : std_logic := '1';
signal RstxRB : std_logic;
-- data/control signals
signal WExE : std_logic;
signal RExE : std_logic;
signal AddrxD : std_logic_vector(IFWIDTH-1 downto 0);
signal DataInxD : std_logic_vector(IFWIDTH-1 downto 0);
signal DataOutxD : std_logic_vector(IFWIDTH-1 downto 0);
-- configuration stuff
signal Cfg : engineConfigRec :=
tstbitat0cfg;
signal CfgxD : std_logic_vector(ENGN_CFGLEN-1 downto 0) :=
to_engineConfig_vec(Cfg);
signal CfgPrt : cfgPartArray := partition_config(CfgxD);
file HFILE : text open write_mode is "tstbitat0_cfg.h";
type fifo_array is array (0 to (3*NDATA)-1) of
std_logic_vector(15 downto 0);
--------------------------------------------------------------------
-- test vectors
-- out = tst_bitsat0(a,b)
-- array contains: contents for fifo0, contents for fifo1, expected
-- result
--------------------------------------------------------------------
constant TESTV : fifo_array :=
(b"0000_0000_0000_0000", -- a 0000
b"0000_1111_0000_1111", -- b 0F0F
b"1111_1111_1111_1111", -- out FFFF
b"0000_0000_0000_0000", -- a 0000
b"0000_0000_0000_0000", -- b 0000
b"1111_1111_1111_1111", -- out FFFF
b"0111_1101_1010_0101", -- a 7DA5
b"1000_0010_0000_1000", -- b 8208
b"1111_1111_1111_1111", -- out FFFF
b"1101_0101_1101_1000", -- a D5D8
b"1011_0000_0010_0000", -- b B020
b"0000_0000_0000_0000", -- out 0000
b"1001_0111_1110_0001", -- a 97E1
b"0010_1100_0000_0000", -- b 2C00
b"0000_0000_0000_0000", -- out 0000
b"1001_0111_1110_0001", -- a 97E1
b"0010_1000_0000_0010", -- b 2802
b"1111_1111_1111_1111" -- out FFFF
);
begin -- arch
----------------------------------------------------------------------------
-- device under test
----------------------------------------------------------------------------
dut : ZUnit
generic map (
IFWIDTH => IFWIDTH,
DATAWIDTH => DATAWIDTH,
CCNTWIDTH => CCNTWIDTH,
FIFODEPTH => FIFODEPTH)
port map (
ClkxC => ClkxC,
RstxRB => RstxRB,
WExEI => WExE,
RExEI => RExE,
AddrxDI => AddrxD,
DataxDI => DataInxD,
DataxDO => DataOutxD);
----------------------------------------------------------------------------
-- generate .h file for coupled simulation
----------------------------------------------------------------------------
hFileGen : process
begin -- process hFileGen
gen_cfghfile(HFILE, CfgPrt);
wait;
end process hFileGen;
----------------------------------------------------------------------------
-- stimuli
----------------------------------------------------------------------------
stimuliTb : process
variable expectedresponse : std_logic_vector(15 downto 0) := (others => '0');
variable response : std_logic_vector(15 downto 0) := (others => '0');
begin -- process stimuliTb
tbStatus <= tbstart;
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '0');
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '1');
tbStatus <= idle;
wait for CLK_PERIOD*0.25;
tbStatus <= idle; -- idle
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
-------------------------------------------------
-- reset (ZREG_RST:W)
-------------------------------------------------
tbStatus <= rst;
WExE <= '1';
RExE <= '0';
AddrxD <= std_logic_vector(to_unsigned(ZREG_RST, IFWIDTH));
DataInxD <= std_logic_vector(to_signed(0, IFWIDTH));
wait for CLK_PERIOD;
tbStatus <= idle; -- idle
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
wait for CLK_PERIOD;
-------------------------------------------------
-- write configuration slices (ZREG_CFGMEM0:W)
-------------------------------------------------
tbStatus <= wr_cfg;
WExE <= '1';
RExE <= '0';
AddrxD <= std_logic_vector(to_unsigned(ZREG_CFGMEM0, IFWIDTH));
for i in CfgPrt'low to CfgPrt'high loop
DataInxD <= CfgPrt(i);
wait for CLK_PERIOD;
end loop; -- i
tbStatus <= idle; -- idle
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
wait for CLK_PERIOD;
-------------------------------------------------
-- push data into FIFO0 (ZREG_FIFO0:W)
-------------------------------------------------
tbStatus <= push_data_fifo0;
WExE <= '1';
RExE <= '0';
AddrxD <= std_logic_vector(to_unsigned(ZREG_FIFO0, IFWIDTH));
for i in 0 to NDATA-1 loop
DataInxD <= (others => '0');
DataInxD(15 downto 0) <= TESTV(i*3);
-- assert false
-- report "writing to FIFO0:" & hstr(TESTV(i*3))
-- severity note;
wait for CLK_PERIOD;
end loop; -- i
tbStatus <= idle; -- idle
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
wait for CLK_PERIOD;
-------------------------------------------------
-- push data into FIFO1 (ZREG_FIFO1:W)
-------------------------------------------------
tbStatus <= push_data_fifo1;
WExE <= '1';
RExE <= '0';
AddrxD <= std_logic_vector(to_unsigned(ZREG_FIFO1, IFWIDTH));
for i in 0 to NDATA-1 loop
DataInxD <= (others => '0');
DataInxD(15 downto 0) <= TESTV(i*3+1);
-- assert false
-- report "writing to FIFO1:" & hstr(TESTV(i*3+1))
-- severity note;
wait for CLK_PERIOD;
end loop; -- i
tbStatus <= idle; -- idle
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
wait for CLK_PERIOD;
-------------------------------------------------
-- write cycle count register (ZREG_CYCLECNT:W)
-------------------------------------------------
tbStatus <= wr_ncycl;
WExE <= '1';
RExE <= '0';
AddrxD <= std_logic_vector(to_unsigned(ZREG_CYCLECNT, IFWIDTH));
DataInxD <= std_logic_vector(to_signed(NRUNCYCLES, IFWIDTH));
wait for CLK_PERIOD;
-------------------------------------------------
-- computation running
-------------------------------------------------
tbStatus <= running;
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
for i in 1 to NRUNCYCLES loop
wait for CLK_PERIOD;
end loop; -- i
-- -----------------------------------------------
-- pop data from out buffer (ZREG_FIFO0:R)
-- -----------------------------------------------
tbStatus <= pop_data;
WExE <= '0';
RExE <= '1';
DataInxD <= (others => '0');
AddrxD <= std_logic_vector(to_unsigned(ZREG_FIFO0, IFWIDTH));
for i in 0 to NDATA-1 loop
wait for CLK_PERIOD;
expectedresponse := TESTV(3*i+2);
response := DataOutxD(15 downto 0);
assert response = expectedresponse
report "FAILURE--FAILURE--FAILURE--FAILURE--FAILURE--FAILURE" & LF &
"regression test failed, response " & hstr(response) &
" does NOT match expected response "
& hstr(expectedresponse) & " tv: " & str(i) & LF &
"FAILURE--FAILURE--FAILURE--FAILURE--FAILURE--FAILURE"
severity failure;
assert not(response = expectedresponse)
report "response " & hstr(response) & " matches expected " &
"response " & hstr(expectedresponse)
severity note;
end loop; -- i
tbStatus <= idle; -- idle
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
-----------------------------------------------
-- done stop simulation
-----------------------------------------------
tbStatus <= done; -- done
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
---------------------------------------------------------------------------
-- stopping the simulation is done by using the following TCL script
-- in modelsim, since terminating the simulation with an assert failure is
-- a crude hack:
--
-- when {/tbStatus == done} {
-- echo "At Time $now Ending the simulation"
-- quit -f
-- }
---------------------------------------------------------------------------
-- stop simulation
wait until (ClkxC'event and ClkxC = '1');
assert false
report "Testbench successfully terminated after " & str(cycle) &
" cycles, no errors found!"
severity failure;
end process stimuliTb;
----------------------------------------------------------------------------
-- clock and reset generation
----------------------------------------------------------------------------
ClkxC <= not ClkxC after CLK_PERIOD/2;
RstxRB <= '0', '1' after CLK_PERIOD*1.25;
----------------------------------------------------------------------------
-- cycle counter
----------------------------------------------------------------------------
cyclecounter : process (ClkxC)
begin
if (ClkxC'event and ClkxC = '1') then
cycle <= cycle + 1;
end if;
end process cyclecounter;
end arch;
|
bsd-3-clause
|
stuarthodgson/cocotb
|
examples/mean/hdl/mean.vhd
|
4
|
1583
|
-------------------------------------------------------------------------------
-- Calculates mean of data input bus
-------------------------------------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mean_pkg.all;
entity mean is
generic (
BUS_WIDTH : natural := 2);
port (
clk : in std_logic;
rst : in std_logic;
i_valid : in std_logic;
i_data : in t_data_array(0 to BUS_WIDTH-1);
o_valid : out std_logic;
o_data : out t_data
);
end mean;
architecture RTL of mean is
signal s_sum : unsigned(DATA_WIDTH + clog2(BUS_WIDTH-1)-1 downto 0) := (others => '0'); -- introduce bug
-- signal s_sum : unsigned(DATA_WIDTH + clog2(BUS_WIDTH)-1 downto 0) := (others => '0');
signal s_valid : std_logic := '0';
begin
assert BUS_WIDTH = 2**(clog2(BUS_WIDTH))
report LF & " BUS_WIDTH = " & integer'image(BUS_WIDTH) & " , should be a power of 2!"
severity Failure;
process(clk)
variable v_sum : unsigned(s_sum'range);
begin
if rising_edge(clk) then
s_valid <= i_valid;
if i_valid = '1' then
v_sum := (others => '0');
for i in i_data'range loop
v_sum := v_sum + resize(i_data(i), v_sum'length);
end loop;
s_sum <= v_sum;
end if;
if rst = '1' then
s_sum <= (others => '0');
s_valid <= '0';
end if;
end if;
end process;
o_valid <= s_valid;
o_data <= resize(shift_right(s_sum, clog2(BUS_WIDTH)), o_data'length);
end rtl;
|
bsd-3-clause
|
pkerling/ethernet_mac
|
xilinx/mii_gmii_io_spartan6.vhd
|
1
|
6802
|
-- This file is part of the ethernet_mac project.
--
-- For the full copyright and license information, please read the
-- LICENSE.md file that was distributed with this source code.
-- IO structure for MII/GMII on Xilinx Spartan-6 devices
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
architecture spartan_6 of mii_gmii_io is
signal gmii_active : std_ulogic := '0';
signal clock_tx : std_ulogic := '0';
signal clock_tx_inv : std_ulogic := '1';
signal clock_mii_rx_io : std_ulogic := '0';
signal clock_mii_rx_div : std_ulogic;
-- IDELAY_VALUE applied to the inputs using IODELAY2
-- This will need fine-tuning depending on the exact device and the location of the IO pins
-- The constraints file can be used to override this default value in the fixed_input_delay
-- instances if needed
constant MII_RX_INPUT_DELAY : natural := 10;
signal clock_mii_rx_ibufg : std_ulogic;
begin
clock_tx_o <= clock_tx;
-- Inverter is absorbed into the IOB FF clock inputs
clock_tx_inv <= not clock_tx;
-- speed_select_i must be registered so no hazards can reach the BUFGMUX
with speed_select_i select gmii_active <=
'1' when SPEED_1000MBPS,
'0' when others;
-- Switch between 125 Mhz reference clock and MII_TX_CLK for TX process and register clocking
-- depending on mode of operation
-- Asynchronous clock switch-over is required: the MII TX_CLK might not be running any more when
-- switching to GMII. This means that glitches can occur on the clock and the complete MAC has to
-- be reset after a speed change.
clock_tx_BUFGMUX_inst : BUFGMUX
generic map(
CLK_SEL_TYPE => "ASYNC" -- Glitchles ("SYNC") or fast ("ASYNC") clock switch-over
)
port map(
O => clock_tx, -- 1-bit output: Clock buffer output
I0 => mii_tx_clk_i, -- 1-bit input: Clock buffer input (S=0)
I1 => clock_125_i, -- 1-bit input: Clock buffer input (S=1)
S => gmii_active -- 1-bit input: Clock buffer select
);
-- Output clock only when running GMII to reduce switching noise
-- and avoid outputting a useless 25 MHz clock in MII mode.
-- Invert clock so that the output values toggle at the falling edge (as seen from the PHY)
-- and are valid when the clock rises.
-- The inverse clock is generated by simple inversion. This is not a problem since inverters
-- are integrated into the ODDR2 clock inputs (no LUT necessary).
-- Clock enable is not synchronous to clock_tx here, but that shouldn't matter as it
-- switches only very seldomly. If the setup/hold time is violated, only one or two clock cyles
-- should be missed.
ODDR2_inst : ODDR2
generic map(
DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1"
INIT => '0', -- Sets initial state of the Q output to '0' or '1'
SRTYPE => "SYNC") -- Specifies "SYNC" or "ASYNC" set/reset
port map(
Q => gmii_gtx_clk_o, -- 1-bit output data
C0 => clock_tx_inv, -- 1-bit clock input
C1 => clock_tx, -- 1-bit clock input
CE => gmii_active, -- 1-bit clock enable input
D0 => '1', -- 1-bit data input (associated with C0)
D1 => '0', -- 1-bit data input (associated with C1)
R => '0', -- 1-bit reset input
S => '0' -- 1-bit set input
);
-- Use FDRE in IOB for output pins to guarantee delay characteristics are identical to the GTX_CLK output.
-- The registers need to be clocked by clock_tx and not clock_125. Metastability would
-- ensure otherwise since the TX state machine is clocked by clock_tx and clock_tx/clock_125
-- have no defined phase relationship.
mii_tx_en_buffer_inst : entity work.output_buffer
port map(
pad_o => mii_tx_en_o,
buffer_i => int_mii_tx_en_i,
clock_i => clock_tx
);
mii_txd_buffer_generate : for i in mii_txd_o'range generate
mii_txd_buffer_inst : entity work.output_buffer
port map(
pad_o => mii_txd_o(i),
buffer_i => int_mii_txd_i(i),
clock_i => clock_tx
);
end generate;
-- Inserting a delay into the clock path should theoretically allow fine-tuning
-- of the clock/data offset, but the timing analyzer doesn't like it as very big
-- IDELAY_VALUE values are necessary that exhibit strong variations. Maybe it works anyway. Try if
-- the current method fails.
-- mii_rx_clk_delay_inst : entity work.fixed_input_delay
-- generic map (
-- IDELAY_VALUE => 0
-- )
-- port map (
-- pin_i => mii_rx_clk_i,
-- delayed_o => mii_rx_clk_delayed
-- );
IBUFG_inst : IBUFG
generic map(
IBUF_LOW_PWR => FALSE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "LVCMOS33")
port map(
O => clock_mii_rx_ibufg, -- Clock buffer output
I => mii_rx_clk_i -- Clock buffer input (connect directly to top-level port)
);
-- Use of a PLL or DCM for RX_CLK is not possible! The clock frequency in 10 Mbps mode (2.5 MHz)
-- is below the minimum input frequency of both the PLL and DCM block.
mii_rx_clk_BUFIO2_inst : BUFIO2
generic map(
DIVIDE => 1, -- DIVCLK divider (1,3-8)
DIVIDE_BYPASS => TRUE, -- Bypass the divider circuitry (TRUE/FALSE)
I_INVERT => FALSE, -- Invert clock (TRUE/FALSE)
USE_DOUBLER => FALSE -- Use doubler circuitry (TRUE/FALSE)
)
port map(
DIVCLK => clock_mii_rx_div, -- 1-bit output: Divided clock output
IOCLK => clock_mii_rx_io, -- 1-bit output: I/O output clock
SERDESSTROBE => open, -- 1-bit output: Output SERDES strobe (connect to ISERDES2/OSERDES2)
I => clock_mii_rx_ibufg -- 1-bit input: Clock input (connect to IBUFG)
);
mii_rx_clk_BUFG_inst : BUFG
port map(
O => clock_rx_o, -- 1-bit output: Clock buffer output
I => clock_mii_rx_div -- 1-bit input: Clock buffer input
);
mii_rx_dv_buffer_inst : entity work.input_buffer
generic map(
HAS_DELAY => TRUE,
IDELAY_VALUE => MII_RX_INPUT_DELAY
)
port map(
pad_i => mii_rx_dv_i,
buffer_o => int_mii_rx_dv_o,
clock_i => clock_mii_rx_io
);
mii_rx_er_buffer_inst : entity work.input_buffer
generic map(
HAS_DELAY => TRUE,
IDELAY_VALUE => MII_RX_INPUT_DELAY
)
port map(
pad_i => mii_rx_er_i,
buffer_o => int_mii_rx_er_o,
clock_i => clock_mii_rx_io
);
mii_rxd_buffer_generate : for i in mii_rxd_i'range generate
mii_rxd_buffer_inst : entity work.input_buffer
generic map(
HAS_DELAY => TRUE,
IDELAY_VALUE => MII_RX_INPUT_DELAY
)
port map(
pad_i => mii_rxd_i(i),
buffer_o => int_mii_rxd_o(i),
clock_i => clock_mii_rx_io
);
end generate;
end architecture;
|
bsd-3-clause
|
pkerling/ethernet_mac
|
framing.vhd
|
1
|
13660
|
-- This file is part of the ethernet_mac project.
--
-- For the full copyright and license information, please read the
-- LICENSE.md file that was distributed with this source code.
-- MAC sublayer functionality (en-/decapsulation, FCS, IPG)
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.ethernet_types.all;
use work.framing_common.all;
use work.crc32.all;
use work.utility.all;
entity framing is
port(
tx_reset_i : in std_ulogic;
tx_clock_i : in std_ulogic;
rx_reset_i : in std_ulogic;
rx_clock_i : in std_ulogic;
-- MAC address of this station
-- Must not change after either reset is deasserted
-- Used for
-- * dropping received packets when the destination address differs from both this one and the broadcast address
-- * inserting as source address in transmitted packets when the first byte of the source address in the data stream is all-ones
mac_address_i : in t_mac_address;
-- For details on the signals, see the port list of mii_gmii
-- TX from client logic
-- The length/type field is considered part of the data!
-- It is not interpreted by the framing layer at all.
tx_enable_i : in std_ulogic;
tx_data_i : in t_ethernet_data;
tx_byte_sent_o : out std_ulogic;
-- Do not start new frames while asserted
-- (continuing the previous one is alright)
tx_busy_o : out std_ulogic;
-- RX to client logic
rx_frame_o : out std_ulogic;
rx_data_o : out t_ethernet_data;
rx_byte_received_o : out std_ulogic;
rx_error_o : out std_ulogic;
-- TX to MII
mii_tx_enable_o : out std_ulogic;
mii_tx_data_o : out t_ethernet_data;
mii_tx_byte_sent_i : in std_ulogic;
mii_tx_gap_o : out std_ulogic;
-- RX from MII
mii_rx_frame_i : in std_ulogic;
mii_rx_data_i : in t_ethernet_data;
mii_rx_byte_received_i : in std_ulogic;
mii_rx_error_i : in std_ulogic
);
end entity;
architecture rtl of framing is
-- Transmission
type t_tx_state is (
TX_IDLE,
-- TX_PREMABLE1 is not needed: first preamble byte is transmitted directly in TX_IDLE when start of transmission
-- is detected.
TX_PREAMBLE2,
TX_PREAMBLE3,
TX_PREAMBLE4,
TX_PREAMBLE5,
TX_PREAMBLE6,
TX_PREAMBLE7,
TX_START_FRAME_DELIMITER,
TX_CLIENT_DATA_WAIT_SOURCE_ADDRESS,
TX_SOURCE_ADDRESS,
TX_CLIENT_DATA,
TX_PAD,
TX_FRAME_CHECK_SEQUENCE2,
TX_FRAME_CHECK_SEQUENCE3,
TX_FRAME_CHECK_SEQUENCE4,
TX_INTERPACKET_GAP
);
signal tx_state : t_tx_state := TX_IDLE;
signal tx_frame_check_sequence : t_crc32;
signal tx_padding_required : natural range 0 to MIN_FRAME_DATA_BYTES + 4 + 1 := 0;
signal tx_interpacket_gap_counter : integer range 0 to INTERPACKET_GAP_BYTES;
signal tx_mac_address_byte : integer range 0 to MAC_ADDRESS_BYTES;
-- Reception
type t_rx_state is (
RX_WAIT_START_FRAME_DELIMITER,
RX_DATA,
RX_ERROR,
RX_SKIP_FRAME
);
signal rx_state : t_rx_state := RX_WAIT_START_FRAME_DELIMITER;
signal rx_frame_check_sequence : t_crc32;
subtype t_rx_frame_size is natural range 0 to MAX_FRAME_DATA_BYTES + CRC32_BYTES + 1;
signal rx_frame_size : t_rx_frame_size;
signal rx_is_group_address : std_ulogic;
signal rx_mac_address_byte : integer range 0 to MAC_ADDRESS_BYTES;
begin
-- Pass mii_tx_byte_sent_i through directly as long as data is being transmitted
-- to avoid having to prefetch data in the synchronous process
tx_byte_sent_o <= '1' when ((tx_state = TX_CLIENT_DATA or tx_state = TX_CLIENT_DATA_WAIT_SOURCE_ADDRESS or tx_state = TX_SOURCE_ADDRESS) and mii_tx_byte_sent_i = '1') else '0';
-- Transmission state machine
tx_fsm_sync : process(tx_reset_i, tx_clock_i)
variable update_fcs : boolean;
variable data_out : t_ethernet_data;
begin
if tx_reset_i = '1' then
tx_state <= TX_IDLE;
mii_tx_enable_o <= '0';
tx_busy_o <= '1';
elsif rising_edge(tx_clock_i) then
mii_tx_enable_o <= '0';
tx_busy_o <= '0';
if tx_state = TX_IDLE then
if tx_enable_i = '1' then
-- Jump straight into preamble to save a clock cycle of latency
tx_state <= TX_PREAMBLE2;
mii_tx_data_o <= PREAMBLE_DATA;
mii_tx_enable_o <= '1';
mii_tx_gap_o <= '0';
tx_busy_o <= '1';
end if;
else
-- Keep TX enable and busy asserted at all times
mii_tx_enable_o <= '1';
tx_busy_o <= '1';
-- Use mii_tx_byte_sent_i as clock enable
if mii_tx_byte_sent_i = '1' then
mii_tx_gap_o <= '0';
data_out := (others => '0');
update_fcs := FALSE;
case tx_state is
when TX_IDLE =>
-- Handled above, cannot happen here
null;
when TX_PREAMBLE2 | TX_PREAMBLE3 | TX_PREAMBLE4 | TX_PREAMBLE5 | TX_PREAMBLE6 =>
tx_state <= t_tx_state'succ(tx_state);
data_out := PREAMBLE_DATA;
when TX_PREAMBLE7 =>
tx_state <= TX_START_FRAME_DELIMITER;
data_out := PREAMBLE_DATA;
when TX_START_FRAME_DELIMITER =>
tx_state <= TX_CLIENT_DATA_WAIT_SOURCE_ADDRESS;
data_out := START_FRAME_DELIMITER_DATA;
-- Load padding register
tx_padding_required <= MIN_FRAME_DATA_BYTES;
-- Load FCS
-- Initial value is 0xFFFFFFFF which is equivalent to inverting the first 32 bits of the frame
-- as required in clause 3.2.9 a
tx_frame_check_sequence <= (others => '1');
-- Load MAC address counter
tx_mac_address_byte <= 0;
when TX_CLIENT_DATA_WAIT_SOURCE_ADDRESS =>
data_out := tx_data_i;
update_fcs := TRUE;
-- Skip destination address
if tx_mac_address_byte < MAC_ADDRESS_BYTES then
tx_mac_address_byte <= tx_mac_address_byte + 1;
else
-- All-ones means that we should insert the source address here
if tx_data_i = x"FF" then
tx_state <= TX_SOURCE_ADDRESS;
-- Override client data with first source address byte
data_out := extract_byte(mac_address_i, 0);
-- Second byte is to be sent in next cycle
tx_mac_address_byte <= 1;
else
-- Transmit as usual, skip TX_SOURCE_ADDRESS
tx_state <= TX_CLIENT_DATA;
end if;
end if;
-- Bail out from here if transmission was aborted
-- Note that this should not happen under normal circumstances as the
-- Ethernet frame would be far too short.
if tx_enable_i = '0' then
tx_state <= TX_PAD;
data_out := PADDING_DATA;
end if;
when TX_SOURCE_ADDRESS =>
data_out := extract_byte(mac_address_i, tx_mac_address_byte);
update_fcs := TRUE;
if tx_mac_address_byte < MAC_ADDRESS_BYTES - 1 then
tx_mac_address_byte <= tx_mac_address_byte + 1;
else
-- Address completely sent when tx_mac_address_byte reaches 5
-- Pass on client data again in next cycle
tx_state <= TX_CLIENT_DATA;
end if;
when TX_CLIENT_DATA =>
data_out := tx_data_i;
update_fcs := TRUE;
if tx_enable_i = '0' then
-- No more user data was available, next value has to be sent
-- in this clock cycle already
if tx_padding_required = 0 then
-- Send FCS byte 1 now, byte 2 in next cycle
tx_state <= TX_FRAME_CHECK_SEQUENCE2;
data_out := fcs_output_byte(tx_frame_check_sequence, 0);
update_fcs := FALSE;
else
tx_state <= TX_PAD;
data_out := PADDING_DATA;
end if;
end if;
when TX_PAD =>
data_out := PADDING_DATA;
update_fcs := TRUE;
if tx_padding_required = 0 then
-- When required=0, previous one was the last one -> send FCS
tx_state <= TX_FRAME_CHECK_SEQUENCE2;
data_out := fcs_output_byte(tx_frame_check_sequence, 0);
update_fcs := FALSE;
end if;
when TX_FRAME_CHECK_SEQUENCE2 =>
tx_state <= t_tx_state'succ(tx_state);
data_out := fcs_output_byte(tx_frame_check_sequence, 1);
when TX_FRAME_CHECK_SEQUENCE3 =>
tx_state <= t_tx_state'succ(tx_state);
data_out := fcs_output_byte(tx_frame_check_sequence, 2);
when TX_FRAME_CHECK_SEQUENCE4 =>
tx_state <= TX_INTERPACKET_GAP;
data_out := fcs_output_byte(tx_frame_check_sequence, 3);
-- Load IPG counter with initial value
tx_interpacket_gap_counter <= 0;
when TX_INTERPACKET_GAP =>
-- Only state where the MAC is still busy but no data is actually sent
mii_tx_gap_o <= '1';
if tx_interpacket_gap_counter = INTERPACKET_GAP_BYTES - 1 then
-- Last IPG byte is transmitted in this cycle
tx_state <= TX_IDLE;
else
tx_interpacket_gap_counter <= tx_interpacket_gap_counter + 1;
end if;
end case;
mii_tx_data_o <= data_out;
if update_fcs then
tx_frame_check_sequence <= update_crc32(tx_frame_check_sequence, data_out);
end if;
if tx_state = TX_CLIENT_DATA_WAIT_SOURCE_ADDRESS or tx_state = TX_SOURCE_ADDRESS or tx_state = TX_CLIENT_DATA or tx_state = TX_PAD then
-- Decrement required padding
if tx_padding_required > 0 then
tx_padding_required <= tx_padding_required - 1;
end if;
end if;
end if;
end if;
end if;
end process;
-- Reception state machine
rx_fsm_sync : process(rx_reset_i, rx_clock_i)
begin
if rx_reset_i = '1' then
rx_state <= RX_WAIT_START_FRAME_DELIMITER;
elsif rising_edge(rx_clock_i) then
rx_error_o <= '0';
rx_data_o <= mii_rx_data_i;
rx_byte_received_o <= '0';
rx_frame_o <= '0';
case rx_state is
when RX_WAIT_START_FRAME_DELIMITER =>
-- Reset MAC address detection
rx_mac_address_byte <= 0;
rx_is_group_address <= '1';
-- Reset frame size and FCS
rx_frame_size <= 0;
-- Initial value is 0xFFFFFFFF which is equivalent to inverting the first 32 bits of the frame
-- as required in clause 3.2.9 a
rx_frame_check_sequence <= (others => '1');
if mii_rx_frame_i = '1' then
if mii_rx_byte_received_i = '1' then
case mii_rx_data_i is
when START_FRAME_DELIMITER_DATA =>
rx_state <= RX_DATA;
when PREAMBLE_DATA =>
-- Do nothing, wait for end of preamble
null;
when others =>
-- The frame needs to be thrown away, but there is no need to
-- inform the higher layer since nothing of value was actually "received" anyway.
rx_state <= RX_SKIP_FRAME;
end case;
end if;
if mii_rx_error_i = '1' then
-- Same here
rx_state <= RX_SKIP_FRAME;
end if;
end if;
when RX_DATA =>
rx_frame_o <= '1';
rx_byte_received_o <= mii_rx_byte_received_i;
if mii_rx_frame_i = '0' then
rx_state <= RX_WAIT_START_FRAME_DELIMITER;
-- Remaining FCS after parsing whole packet + FCS needs to be a specific value
if mii_rx_error_i = '1' or rx_frame_check_sequence /= CRC32_POSTINVERT_MAGIC or rx_frame_size < MIN_FRAME_DATA_BYTES + CRC32_BYTES or rx_frame_size > MAX_FRAME_DATA_BYTES + CRC32_BYTES then
rx_error_o <= '1';
end if;
else
if mii_rx_byte_received_i = '1' then
-- Update FCS check
rx_frame_check_sequence <= update_crc32(rx_frame_check_sequence, mii_rx_data_i);
-- Increase frame size
if rx_frame_size < t_rx_frame_size'high then
rx_frame_size <= rx_frame_size + 1;
end if;
-- Check destination MAC address (first 6 bytes of packet)
if rx_mac_address_byte < MAC_ADDRESS_BYTES then
-- First byte determines whether the address is an individual or group address
if rx_mac_address_byte = 0 then
if mii_rx_data_i(0) = '0' then
-- LSB of the address is zero: packet is destined for an individual entity
rx_is_group_address <= '0';
-- Check first address byte
if mii_rx_data_i /= extract_byte(mac_address_i, rx_mac_address_byte) then
-- Packet is not destined for us -> drop it
rx_state <= RX_ERROR;
end if;
end if;
-- If not: It is a group address packet -> do not drop it and do not check the address further
elsif rx_is_group_address = '0' then
-- Check other MAC address bytes only if we know it doesn't have a group destination address
if mii_rx_data_i /= extract_byte(mac_address_i, rx_mac_address_byte) then
-- Packet is not destined for us -> drop it
rx_state <= RX_ERROR;
end if;
end if;
rx_mac_address_byte <= rx_mac_address_byte + 1;
end if;
end if;
if mii_rx_error_i = '1' then
-- Skip the rest of the frame and tell the higher layer
rx_state <= RX_ERROR;
end if;
end if;
when RX_SKIP_FRAME =>
-- Skip the currently receiving frame without signaling the higher layer
if mii_rx_frame_i = '0' then
rx_state <= RX_WAIT_START_FRAME_DELIMITER;
end if;
when RX_ERROR =>
-- Skip the currently receiving frame and signal the higher layer
rx_frame_o <= '1';
rx_error_o <= '1';
if mii_rx_frame_i = '0' then
rx_state <= RX_WAIT_START_FRAME_DELIMITER;
end if;
end case;
end if;
end process;
end architecture;
|
bsd-3-clause
|
32bitmicro/Malinki
|
fabric/rio/bench/vhdl/TestRioPcsUart.vhd
|
2
|
23992
|
-------------------------------------------------------------------------------
--
-- RapidIO IP Library Core
--
-- This file is part of the RapidIO IP library project
-- http://www.opencores.org/cores/rio/
--
-- Description
-- This file contains a testbench for RioPcsUart.
--
-- To Do:
-- -
--
-- Author(s):
-- - Magnus Rosenius, [email protected]
--
-------------------------------------------------------------------------------
--
-- Copyright (C) 2013 Authors and OPENCORES.ORG
--
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.opencores.org/lgpl.shtml
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- TestRioPcsUart.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
use work.rio_common.all;
-------------------------------------------------------------------------------
-- Entity for TestRioPcsUart.
-------------------------------------------------------------------------------
entity TestRioPcsUart is
end entity;
-------------------------------------------------------------------------------
-- Architecture for TestUart.
-------------------------------------------------------------------------------
architecture TestRioPcsUartImpl of TestRioPcsUart is
component RioFifo1 is
generic(
WIDTH : natural);
port(
clk : in std_logic;
areset_n : in std_logic;
empty_o : out std_logic;
read_i : in std_logic;
data_o : out std_logic_vector(WIDTH-1 downto 0);
full_o : out std_logic;
write_i : in std_logic;
data_i : in std_logic_vector(WIDTH-1 downto 0));
end component;
component RioSymbolConverter is
port(
clk : in std_logic;
areset_n : in std_logic;
portInitialized_o : out std_logic;
outboundSymbolEmpty_i : in std_logic;
outboundSymbolRead_o : out std_logic;
outboundSymbol_i : in std_logic_vector(33 downto 0);
inboundSymbolFull_i : in std_logic;
inboundSymbolWrite_o : out std_logic;
inboundSymbol_o : out std_logic_vector(33 downto 0);
uartEmpty_i : in std_logic;
uartRead_o : out std_logic;
uartData_i : in std_logic_vector(7 downto 0);
uartFull_i : in std_logic;
uartWrite_o : out std_logic;
uartData_o : out std_logic_vector(7 downto 0));
end component;
signal clk : std_logic;
signal areset_n : std_logic;
signal portInitialized : std_logic;
signal outboundSymbolEmpty : std_logic;
signal outboundSymbolRead : std_logic;
signal outboundSymbolReadData : std_logic_vector(33 downto 0);
signal outboundSymbolFull : std_logic;
signal outboundSymbolWrite : std_logic;
signal outboundSymbolWriteData : std_logic_vector(33 downto 0);
signal inboundSymbolFull : std_logic;
signal inboundSymbolWrite : std_logic;
signal inboundSymbolWriteData : std_logic_vector(33 downto 0);
signal uartInboundEmpty : std_logic;
signal uartInboundRead : std_logic;
signal uartInboundReadData : std_logic_vector(7 downto 0);
signal uartInboundFull : std_logic;
signal uartInboundWrite : std_logic;
signal uartInboundWriteData : std_logic_vector(7 downto 0);
signal uartOutboundFull : std_logic;
signal uartOutboundWrite : std_logic;
signal uartOutboundWriteData : std_logic_vector(7 downto 0);
begin
-----------------------------------------------------------------------------
-- Clock generation.
-----------------------------------------------------------------------------
ClockGenerator: process
begin
clk <= '0';
wait for 20 ns;
clk <= '1';
wait for 20 ns;
end process;
-----------------------------------------------------------------------------
-- Serial protocol test driver.
-----------------------------------------------------------------------------
TestDriver: process
---------------------------------------------------------------------------
-- Procedure to read a symbol.
---------------------------------------------------------------------------
procedure ReadSymbol(
constant symbolType : in std_logic_vector(1 downto 0);
constant symbolContent : in std_logic_vector(31 downto 0) := x"00000000") is
begin
inboundSymbolFull <= '0';
wait until inboundSymbolWrite = '1' and clk'event and clk = '1';
inboundSymbolFull <= '1';
assert symbolType = inboundSymbolWriteData(33 downto 32)
report "Missmatching symbol type:expected=" &
integer'image(to_integer(unsigned(symbolType))) &
" got=" &
integer'image(to_integer(unsigned(outboundSymbolWriteData(33 downto 32))))
severity error;
if (symbolType = SYMBOL_CONTROL) then
assert symbolContent(31 downto 8) = inboundSymbolWriteData(31 downto 8)
report "Missmatching symbol content:expected=" &
integer'image(to_integer(unsigned(symbolContent(31 downto 8)))) &
" got=" &
integer'image(to_integer(unsigned(inboundSymbolWriteData(31 downto 8))))
severity error;
elsif (symbolType = SYMBOL_DATA) then
assert symbolContent(31 downto 0) = inboundSymbolWriteData(31 downto 0)
report "Missmatching symbol content:expected=" &
integer'image(to_integer(unsigned(symbolContent(31 downto 0)))) &
" got=" &
integer'image(to_integer(unsigned(inboundSymbolWriteData(31 downto 0))))
severity error;
end if;
end procedure;
---------------------------------------------------------------------------
-- Procedure to write a symbol.
---------------------------------------------------------------------------
procedure WriteSymbol(
constant symbolType : in std_logic_vector(1 downto 0);
constant symbolContent : in std_logic_vector(31 downto 0) := x"00000000") is
begin
wait until outboundSymbolFull = '0' and clk'event and clk = '1';
outboundSymbolWrite <= '1';
outboundSymbolWriteData <= symbolType & symbolContent;
wait until clk'event and clk = '1';
outboundSymbolWrite <= '0';
end procedure;
---------------------------------------------------------------------------
-- Procedure to read an octet.
---------------------------------------------------------------------------
procedure ReadOctet(
constant octet : in std_logic_vector(7 downto 0) := x"00") is
begin
uartOutboundFull <= '0';
wait until uartOutboundWrite = '1' and clk'event and clk = '1';
uartOutboundFull <= '1';
assert uartOutboundWriteData = octet
report "Missmatching octet content:expected=" &
integer'image(to_integer(unsigned(octet))) &
" got=" &
integer'image(to_integer(unsigned(uartOutboundWriteData)))
severity error;
end procedure;
---------------------------------------------------------------------------
-- Procedure to send a symbol.
---------------------------------------------------------------------------
procedure WriteOctet(
constant octet : in std_logic_vector(7 downto 0) := x"00") is
begin
wait until uartInboundFull = '0' and clk'event and clk = '1';
uartInboundWrite <= '1';
uartInboundWriteData <= octet;
wait until clk'event and clk = '1';
uartInboundWrite <= '0';
end procedure;
---------------------------------------------------------------------------
-- Process variables.
---------------------------------------------------------------------------
begin
---------------------------------------------------------------------------
-- Test case initialization.
---------------------------------------------------------------------------
uartOutboundFull <= '1';
uartInboundWrite <= '0';
inboundSymbolFull <= '1';
outboundSymbolWrite <= '0';
-- Generate a startup reset pulse.
areset_n <= '0';
wait until clk'event and clk = '1';
wait until clk'event and clk = '1';
areset_n <= '1';
wait until clk'event and clk = '1';
wait until clk'event and clk = '1';
---------------------------------------------------------------------------
PrintS("-----------------------------------------------------------------");
PrintS("TG_RioPcsUart");
PrintS("-----------------------------------------------------------------");
PrintS("TG_RioPcsUart-TC1");
PrintS("Description: Check initial silence time.");
PrintS("Requirement: XXXXX");
PrintS("-----------------------------------------------------------------");
PrintS("Step 1:");
PrintS("Action: .");
PrintS("Result: .");
---------------------------------------------------------------------------
PrintR("TG_RioPcsUart-TC1-Step1");
---------------------------------------------------------------------------
WriteSymbol(SYMBOL_IDLE);
uartOutboundFull <= '0';
for i in 0 to 4095 loop
wait until clk'event and clk = '1';
assert uartOutboundWrite = '0' report "Sending during silence time."
severity error;
end loop;
ReadOctet(x"7e");
---------------------------------------------------------------------------
PrintS("-----------------------------------------------------------------");
PrintS("TG_RioPcsUart-TC2");
PrintS("Description: Check outbound symbol generation.");
PrintS("Requirement: XXXXX");
PrintS("-----------------------------------------------------------------");
PrintS("Step 1:");
PrintS("Action: .");
PrintS("Result: .");
---------------------------------------------------------------------------
PrintR("TG_RioPcsUart-TC2-Step1");
---------------------------------------------------------------------------
WriteSymbol(SYMBOL_IDLE);
ReadOctet(x"7e");
WriteSymbol(SYMBOL_IDLE);
ReadOctet(x"7e");
WriteSymbol(SYMBOL_IDLE);
ReadOctet(x"7e");
---------------------------------------------------------------------------
PrintS("Step 2:");
PrintS("Action: .");
PrintS("Result: .");
---------------------------------------------------------------------------
PrintR("TG_RioPcsUart-TC2-Step2");
---------------------------------------------------------------------------
WriteSymbol(SYMBOL_CONTROL, x"123456" & "XXXXXXXX");
ReadOctet(x"12");
ReadOctet(x"34");
ReadOctet(x"56");
ReadOctet(x"7e");
---------------------------------------------------------------------------
PrintS("Step 3:");
PrintS("Action: .");
PrintS("Result: .");
---------------------------------------------------------------------------
PrintR("TG_RioPcsUart-TC2-Step3");
---------------------------------------------------------------------------
WriteSymbol(SYMBOL_CONTROL, x"7d7d7d" & "XXXXXXXX");
ReadOctet(x"7d");
ReadOctet(x"5d");
ReadOctet(x"7d");
ReadOctet(x"5d");
ReadOctet(x"7d");
ReadOctet(x"5d");
ReadOctet(x"7e");
---------------------------------------------------------------------------
PrintS("Step 4:");
PrintS("Action: .");
PrintS("Result: .");
---------------------------------------------------------------------------
PrintR("TG_RioPcsUart-TC2-Step4");
---------------------------------------------------------------------------
WriteSymbol(SYMBOL_CONTROL, x"7e7e7e" & "XXXXXXXX");
ReadOctet(x"7d");
ReadOctet(x"5e");
ReadOctet(x"7d");
ReadOctet(x"5e");
ReadOctet(x"7d");
ReadOctet(x"5e");
ReadOctet(x"7e");
---------------------------------------------------------------------------
PrintS("Step 5:");
PrintS("Action: .");
PrintS("Result: .");
---------------------------------------------------------------------------
PrintR("TG_RioPcsUart-TC2-Step5");
---------------------------------------------------------------------------
WriteSymbol(SYMBOL_CONTROL, x"7d7f7e" & "XXXXXXXX");
ReadOctet(x"7d");
ReadOctet(x"5d");
ReadOctet(x"7f");
ReadOctet(x"7d");
ReadOctet(x"5e");
ReadOctet(x"7e");
---------------------------------------------------------------------------
PrintS("Step 6:");
PrintS("Action: .");
PrintS("Result: .");
---------------------------------------------------------------------------
PrintR("TG_RioPcsUart-TC2-Step6");
---------------------------------------------------------------------------
WriteSymbol(SYMBOL_DATA, x"12345678");
ReadOctet(x"12");
ReadOctet(x"34");
ReadOctet(x"56");
ReadOctet(x"78");
---------------------------------------------------------------------------
PrintS("Step 7:");
PrintS("Action: .");
PrintS("Result: .");
---------------------------------------------------------------------------
PrintR("TG_RioPcsUart-TC2-Step7");
---------------------------------------------------------------------------
WriteSymbol(SYMBOL_DATA, x"7d7d7d7d");
ReadOctet(x"7d");
ReadOctet(x"5d");
ReadOctet(x"7d");
ReadOctet(x"5d");
ReadOctet(x"7d");
ReadOctet(x"5d");
ReadOctet(x"7d");
ReadOctet(x"5d");
---------------------------------------------------------------------------
PrintS("Step 8:");
PrintS("Action: .");
PrintS("Result: .");
---------------------------------------------------------------------------
PrintR("TG_RioPcsUart-TC2-Step8");
---------------------------------------------------------------------------
WriteSymbol(SYMBOL_DATA, x"7e7e7e7e");
ReadOctet(x"7d");
ReadOctet(x"5e");
ReadOctet(x"7d");
ReadOctet(x"5e");
ReadOctet(x"7d");
ReadOctet(x"5e");
ReadOctet(x"7d");
ReadOctet(x"5e");
---------------------------------------------------------------------------
PrintS("Step 9:");
PrintS("Action: .");
PrintS("Result: .");
---------------------------------------------------------------------------
PrintR("TG_RioPcsUart-TC2-Step9");
---------------------------------------------------------------------------
WriteSymbol(SYMBOL_DATA, x"7d7f7e7f");
ReadOctet(x"7d");
ReadOctet(x"5d");
ReadOctet(x"7f");
ReadOctet(x"7d");
ReadOctet(x"5e");
ReadOctet(x"7f");
---------------------------------------------------------------------------
PrintS("Step 10:");
PrintS("Action: .");
PrintS("Result: .");
---------------------------------------------------------------------------
PrintR("TG_RioPcsUart-TC2-Step10");
---------------------------------------------------------------------------
WriteSymbol(SYMBOL_IDLE);
ReadOctet(x"7e");
WriteSymbol(SYMBOL_CONTROL, x"123456" & "XXXXXXXX");
ReadOctet(x"12");
ReadOctet(x"34");
ReadOctet(x"56");
ReadOctet(x"7e");
WriteSymbol(SYMBOL_DATA, x"789abcde");
ReadOctet(x"78");
ReadOctet(x"9a");
ReadOctet(x"bc");
ReadOctet(x"de");
WriteSymbol(SYMBOL_CONTROL, x"123456" & "XXXXXXXX");
ReadOctet(x"12");
ReadOctet(x"34");
ReadOctet(x"56");
ReadOctet(x"7e");
WriteSymbol(SYMBOL_DATA, x"789abcde");
ReadOctet(x"78");
ReadOctet(x"9a");
ReadOctet(x"bc");
ReadOctet(x"de");
WriteSymbol(SYMBOL_DATA, x"789abcde");
ReadOctet(x"78");
ReadOctet(x"9a");
ReadOctet(x"bc");
ReadOctet(x"de");
---------------------------------------------------------------------------
PrintS("-----------------------------------------------------------------");
PrintS("TG_RioPcsUart-TC3");
PrintS("Description: Check inbound symbol generation.");
PrintS("Requirement: XXXXX");
PrintS("-----------------------------------------------------------------");
PrintS("Step 1:");
PrintS("Action: .");
PrintS("Result: .");
---------------------------------------------------------------------------
PrintR("TG_RioPcsUart-TC3-Step1");
---------------------------------------------------------------------------
WriteOctet(x"7e");
WriteOctet(x"7e");
ReadSymbol(SYMBOL_IDLE);
---------------------------------------------------------------------------
PrintS("Step :");
PrintS("Action: .");
PrintS("Result: .");
---------------------------------------------------------------------------
PrintR("TG_RioPcsUart-TC3-Step");
---------------------------------------------------------------------------
WriteOctet(x"12");
WriteOctet(x"7e");
ReadSymbol(SYMBOL_IDLE);
---------------------------------------------------------------------------
PrintS("Step :");
PrintS("Action: .");
PrintS("Result: .");
---------------------------------------------------------------------------
PrintR("TG_RioPcsUart-TC3-Step");
---------------------------------------------------------------------------
WriteOctet(x"34");
WriteOctet(x"56");
WriteOctet(x"7e");
ReadSymbol(SYMBOL_IDLE);
---------------------------------------------------------------------------
PrintS("Step :");
PrintS("Action: .");
PrintS("Result: .");
---------------------------------------------------------------------------
PrintR("TG_RioPcsUart-TC3-Step");
---------------------------------------------------------------------------
WriteOctet(x"78");
WriteOctet(x"9a");
WriteOctet(x"bc");
WriteOctet(x"7e");
ReadSymbol(SYMBOL_CONTROL, x"789abc" & "XXXXXXXX");
---------------------------------------------------------------------------
PrintS("Step :");
PrintS("Action: .");
PrintS("Result: .");
---------------------------------------------------------------------------
PrintR("TG_RioPcsUart-TC3-Step");
---------------------------------------------------------------------------
WriteOctet(x"7d");
WriteOctet(x"5d");
WriteOctet(x"7d");
WriteOctet(x"5d");
WriteOctet(x"7d");
WriteOctet(x"5d");
WriteOctet(x"7e");
ReadSymbol(SYMBOL_CONTROL, x"7d7d7d" & "XXXXXXXX");
---------------------------------------------------------------------------
PrintS("Step :");
PrintS("Action: .");
PrintS("Result: .");
---------------------------------------------------------------------------
PrintR("TG_RioPcsUart-TC3-Step");
---------------------------------------------------------------------------
WriteOctet(x"7d");
WriteOctet(x"5e");
WriteOctet(x"7d");
WriteOctet(x"5e");
WriteOctet(x"7d");
WriteOctet(x"5e");
WriteOctet(x"7e");
ReadSymbol(SYMBOL_CONTROL, x"7e7e7e" & "XXXXXXXX");
---------------------------------------------------------------------------
PrintS("Step :");
PrintS("Action: .");
PrintS("Result: .");
---------------------------------------------------------------------------
PrintR("TG_RioPcsUart-TC3-Step");
---------------------------------------------------------------------------
WriteOctet(x"f1");
WriteOctet(x"11");
WriteOctet(x"22");
WriteOctet(x"33");
ReadSymbol(SYMBOL_DATA, x"f1112233");
---------------------------------------------------------------------------
PrintS("Step :");
PrintS("Action: .");
PrintS("Result: .");
---------------------------------------------------------------------------
PrintR("TG_RioPcsUart-TC3-Step");
---------------------------------------------------------------------------
WriteOctet(x"7e");
ReadSymbol(SYMBOL_IDLE);
---------------------------------------------------------------------------
PrintS("Step :");
PrintS("Action: .");
PrintS("Result: .");
---------------------------------------------------------------------------
PrintR("TG_RioPcsUart-TC3-Step");
---------------------------------------------------------------------------
WriteOctet(x"7d");
WriteOctet(x"5d");
WriteOctet(x"7d");
WriteOctet(x"5d");
WriteOctet(x"7d");
WriteOctet(x"5d");
WriteOctet(x"7d");
WriteOctet(x"5d");
ReadSymbol(SYMBOL_DATA, x"7d7d7d7d");
---------------------------------------------------------------------------
PrintS("Step :");
PrintS("Action: .");
PrintS("Result: .");
---------------------------------------------------------------------------
PrintR("TG_RioPcsUart-TC3-Step");
---------------------------------------------------------------------------
WriteOctet(x"7d");
WriteOctet(x"5e");
WriteOctet(x"7d");
WriteOctet(x"5e");
WriteOctet(x"7d");
WriteOctet(x"5e");
WriteOctet(x"7d");
WriteOctet(x"5e");
ReadSymbol(SYMBOL_DATA, x"7e7e7e7e");
---------------------------------------------------------------------------
PrintS("Step :");
PrintS("Action: .");
PrintS("Result: .");
---------------------------------------------------------------------------
PrintR("TG_RioPcsUart-TC3-Step");
---------------------------------------------------------------------------
WriteOctet(x"44");
WriteOctet(x"55");
WriteOctet(x"66");
WriteOctet(x"77");
ReadSymbol(SYMBOL_DATA, x"44556677");
WriteOctet(x"88");
WriteOctet(x"99");
WriteOctet(x"aa");
WriteOctet(x"bb");
ReadSymbol(SYMBOL_DATA, x"8899aabb");
---------------------------------------------------------------------------
-- Test completed.
---------------------------------------------------------------------------
TestEnd;
end process;
-----------------------------------------------------------------------------
--
-----------------------------------------------------------------------------
OutboundSymbolFifo: RioFifo1
generic map(WIDTH=>34)
port map(
clk=>clk, areset_n=>areset_n,
empty_o=>outboundSymbolEmpty, read_i=>outboundSymbolRead, data_o=>outboundSymbolReadData,
full_o=>outboundSymbolFull, write_i=>outboundSymbolWrite, data_i=>outboundSymbolWriteData);
InboundOctetFifo: RioFifo1
generic map(WIDTH=>8)
port map(
clk=>clk, areset_n=>areset_n,
empty_o=>uartInboundEmpty, read_i=>uartInboundRead, data_o=>uartInboundReadData,
full_o=>uartInboundFull, write_i=>uartInboundWrite, data_i=>uartInboundWriteData);
TestSymbolConverter: RioSymbolConverter
port map(
clk=>clk, areset_n=>areset_n,
portInitialized_o=>portInitialized,
outboundSymbolEmpty_i=>outboundSymbolEmpty,
outboundSymbolRead_o=>outboundSymbolRead, outboundSymbol_i=>outboundSymbolReadData,
inboundSymbolFull_i=>inboundSymbolFull,
inboundSymbolWrite_o=>inboundSymbolWrite, inboundSymbol_o=>inboundSymbolWriteData,
uartEmpty_i=>uartInboundEmpty, uartRead_o=>uartInboundRead, uartData_i=>uartInboundReadData,
uartFull_i=>uartOutboundFull, uartWrite_o=>uartOutboundWrite, uartData_o=>uartOutboundWriteData);
end architecture;
|
bsd-3-clause
|
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/usb2device_v1_0/src/axi_dma_0/axi_datamover_v5_1_9/hdl/src/vhdl/axi_datamover_rdmux.vhd
|
18
|
69394
|
-------------------------------------------------------------------------------
-- axi_datamover_rdmux.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_rdmux.vhd
--
-- Description:
-- This file implements the DataMover Master Read Data Multiplexer.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_rdmux is
generic (
C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5;
-- Sets the width of the select control bus
C_MMAP_DWIDTH : Integer range 32 to 1024 := 32;
-- Indicates the width of the AXI4 Data Channel
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32
-- Indicates the width of the AXI Stream Data Channel
);
port (
-- AXI MMap Data Channel Input -----------------------------------------------
--
mmap_read_data_in : In std_logic_vector(C_MMAP_DWIDTH-1 downto 0); --
-- AXI Read data input --
-------------------------------------------------------------------------------
-- AXI Master Stream ---------------------------------------------------------
--
mux_data_out : Out std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
--Mux data output --
-------------------------------------------------------------------------------
-- Command Calculator Interface -----------------------------------------------
--
mstr2data_saddr_lsb : In std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0) --
-- The next command start address LSbs to use for the read data --
-- mux (only used if Stream data width is less than the MMap Data --
-- Width). --
-------------------------------------------------------------------------------
);
end entity axi_datamover_rdmux;
architecture implementation of axi_datamover_rdmux is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function Decalarations -------------------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_mux_sel_width
--
-- Function Description:
-- Calculates the number of needed bits for the Mux Select control
-- based on the number of input channels to the mux.
--
-- Note that the number of input mux channels are always a
-- power of 2.
--
-------------------------------------------------------------------
function func_mux_sel_width (num_channels : integer) return integer is
Variable var_sel_width : integer := 0;
begin
case num_channels is
when 2 =>
var_sel_width := 1;
when 4 =>
var_sel_width := 2;
when 8 =>
var_sel_width := 3;
when 16 =>
var_sel_width := 4;
when 32 =>
var_sel_width := 5;
when 64 =>
var_sel_width := 6;
when 128 =>
var_sel_width := 7;
when others =>
var_sel_width := 0;
end case;
Return (var_sel_width);
end function func_mux_sel_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_sel_ls_index
--
-- Function Description:
-- Calculates the LS index of the select field to rip from the
-- input select bus.
--
-- Note that the number of input mux channels are always a
-- power of 2.
--
-------------------------------------------------------------------
function func_sel_ls_index (channel_width : integer) return integer is
Variable var_sel_ls_index : integer := 0;
begin
case channel_width is
when 8 =>
var_sel_ls_index := 0;
when 16 =>
var_sel_ls_index := 1;
when 32 =>
var_sel_ls_index := 2;
when 64 =>
var_sel_ls_index := 3;
when 128 =>
var_sel_ls_index := 4;
when 256 =>
var_sel_ls_index := 5;
when 512 =>
var_sel_ls_index := 6;
when others => -- 1024-bit channel case
var_sel_ls_index := 7;
end case;
Return (var_sel_ls_index);
end function func_sel_ls_index;
-- Constant Decalarations -------------------------------------------------
Constant CHANNEL_DWIDTH : integer := C_STREAM_DWIDTH;
Constant NUM_MUX_CHANNELS : integer := C_MMAP_DWIDTH/CHANNEL_DWIDTH;
Constant MUX_SEL_WIDTH : integer := func_mux_sel_width(NUM_MUX_CHANNELS);
Constant MUX_SEL_LS_INDEX : integer := func_sel_ls_index(CHANNEL_DWIDTH);
-- Signal Declarations --------------------------------------------
signal sig_rdmux_dout : std_logic_vector(CHANNEL_DWIDTH-1 downto 0) := (others => '0');
begin --(architecture implementation)
-- Assign the Output data port
mux_data_out <= sig_rdmux_dout;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_STRM_EQ_MMAP
--
-- If Generate Description:
-- This IfGen implements the case where the Stream Data Width is
-- the same as the Memory Map read Data width.
--
--
------------------------------------------------------------
GEN_STRM_EQ_MMAP : if (NUM_MUX_CHANNELS = 1) generate
begin
sig_rdmux_dout <= mmap_read_data_in;
end generate GEN_STRM_EQ_MMAP;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_2XN
--
-- If Generate Description:
-- 2 channel input mux case
--
--
------------------------------------------------------------
GEN_2XN : if (NUM_MUX_CHANNELS = 2) generate
-- local signals
signal sig_mux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_mux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_mux_sel_int : integer := 0;
signal sig_mux_sel_int_local : integer := 0;
signal sig_mux_dout : std_logic_vector(CHANNEL_DWIDTH-1 downto 0) := (others => '0');
begin
-- Rip the Mux Select bits needed for the Mux case from the input select bus
sig_mux_sel_slice <= mstr2data_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX);
sig_mux_sel_unsgnd <= UNSIGNED(sig_mux_sel_slice); -- convert to unsigned
sig_mux_sel_int <= TO_INTEGER(sig_mux_sel_unsgnd); -- convert to integer for MTI compile issue
-- with locally static subtype error in each of the
-- Mux IfGens
sig_mux_sel_int_local <= sig_mux_sel_int;
sig_rdmux_dout <= sig_mux_dout;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_2XN_NUX
--
-- Process Description:
-- Implement the 2XN Mux
--
-------------------------------------------------------------
DO_2XN_NUX : process (sig_mux_sel_int_local,
mmap_read_data_in)
begin
case sig_mux_sel_int_local is
when 0 =>
sig_mux_dout <= mmap_read_data_in(CHANNEL_DWIDTH-1 downto 0);
when others => -- 1 case
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*2)-1 downto CHANNEL_DWIDTH*1);
end case;
end process DO_2XN_NUX;
end generate GEN_2XN;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_4XN
--
-- If Generate Description:
-- 4 channel input mux case
--
--
------------------------------------------------------------
GEN_4XN : if (NUM_MUX_CHANNELS = 4) generate
-- local signals
signal sig_mux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_mux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_mux_sel_int : integer := 0;
signal sig_mux_sel_int_local : integer := 0;
signal sig_mux_dout : std_logic_vector(CHANNEL_DWIDTH-1 downto 0) := (others => '0');
begin
-- Rip the Mux Select bits needed for the Mux case from the input select bus
sig_mux_sel_slice <= mstr2data_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX);
sig_mux_sel_unsgnd <= UNSIGNED(sig_mux_sel_slice); -- convert to unsigned
sig_mux_sel_int <= TO_INTEGER(sig_mux_sel_unsgnd); -- convert to integer for MTI compile issue
-- with locally static subtype error in each of the
-- Mux IfGens
sig_mux_sel_int_local <= sig_mux_sel_int;
sig_rdmux_dout <= sig_mux_dout;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_4XN_NUX
--
-- Process Description:
-- Implement the 4XN Mux
--
-------------------------------------------------------------
DO_4XN_NUX : process (sig_mux_sel_int_local,
mmap_read_data_in)
begin
case sig_mux_sel_int_local is
when 0 =>
sig_mux_dout <= mmap_read_data_in(CHANNEL_DWIDTH-1 downto 0);
when 1 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*2)-1 downto CHANNEL_DWIDTH*1);
when 2 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*3)-1 downto CHANNEL_DWIDTH*2);
when others => -- 3 case
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*4)-1 downto CHANNEL_DWIDTH*3);
end case;
end process DO_4XN_NUX;
end generate GEN_4XN;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_8XN
--
-- If Generate Description:
-- 8 channel input mux case
--
--
------------------------------------------------------------
GEN_8XN : if (NUM_MUX_CHANNELS = 8) generate
-- local signals
signal sig_mux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_mux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_mux_sel_int : integer := 0;
signal sig_mux_sel_int_local : integer := 0;
signal sig_mux_dout : std_logic_vector(CHANNEL_DWIDTH-1 downto 0) := (others => '0');
begin
-- Rip the Mux Select bits needed for the Mux case from the input select bus
sig_mux_sel_slice <= mstr2data_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX);
sig_mux_sel_unsgnd <= UNSIGNED(sig_mux_sel_slice); -- convert to unsigned
sig_mux_sel_int <= TO_INTEGER(sig_mux_sel_unsgnd); -- convert to integer for MTI compile issue
-- with locally static subtype error in each of the
-- Mux IfGens
sig_mux_sel_int_local <= sig_mux_sel_int;
sig_rdmux_dout <= sig_mux_dout;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_8XN_NUX
--
-- Process Description:
-- Implement the 8XN Mux
--
-------------------------------------------------------------
DO_8XN_NUX : process (sig_mux_sel_int_local,
mmap_read_data_in)
begin
case sig_mux_sel_int_local is
when 0 =>
sig_mux_dout <= mmap_read_data_in(CHANNEL_DWIDTH-1 downto 0);
when 1 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*2)-1 downto CHANNEL_DWIDTH*1);
when 2 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*3)-1 downto CHANNEL_DWIDTH*2);
when 3 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*4)-1 downto CHANNEL_DWIDTH*3);
when 4 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*5)-1 downto CHANNEL_DWIDTH*4);
when 5 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*6)-1 downto CHANNEL_DWIDTH*5);
when 6 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*7)-1 downto CHANNEL_DWIDTH*6);
when others => -- 7 case
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*8)-1 downto CHANNEL_DWIDTH*7);
end case;
end process DO_8XN_NUX;
end generate GEN_8XN;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_16XN
--
-- If Generate Description:
-- 16 channel input mux case
--
--
------------------------------------------------------------
GEN_16XN : if (NUM_MUX_CHANNELS = 16) generate
-- local signals
signal sig_mux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_mux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_mux_sel_int : integer := 0;
signal sig_mux_sel_int_local : integer := 0;
signal sig_mux_dout : std_logic_vector(CHANNEL_DWIDTH-1 downto 0) := (others => '0');
begin
-- Rip the Mux Select bits needed for the Mux case from the input select bus
sig_mux_sel_slice <= mstr2data_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX);
sig_mux_sel_unsgnd <= UNSIGNED(sig_mux_sel_slice); -- convert to unsigned
sig_mux_sel_int <= TO_INTEGER(sig_mux_sel_unsgnd); -- convert to integer for MTI compile issue
-- with locally static subtype error in each of the
-- Mux IfGens
sig_mux_sel_int_local <= sig_mux_sel_int;
sig_rdmux_dout <= sig_mux_dout;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_16XN_NUX
--
-- Process Description:
-- Implement the 16XN Mux
--
-------------------------------------------------------------
DO_16XN_NUX : process (sig_mux_sel_int_local,
mmap_read_data_in)
begin
case sig_mux_sel_int_local is
when 0 =>
sig_mux_dout <= mmap_read_data_in(CHANNEL_DWIDTH-1 downto 0);
when 1 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*2)-1 downto CHANNEL_DWIDTH*1);
when 2 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*3)-1 downto CHANNEL_DWIDTH*2);
when 3 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*4)-1 downto CHANNEL_DWIDTH*3);
when 4 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*5)-1 downto CHANNEL_DWIDTH*4);
when 5 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*6)-1 downto CHANNEL_DWIDTH*5);
when 6 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*7)-1 downto CHANNEL_DWIDTH*6);
when 7 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*8)-1 downto CHANNEL_DWIDTH*7);
when 8 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*9)-1 downto CHANNEL_DWIDTH*8);
when 9 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*10)-1 downto CHANNEL_DWIDTH*9);
when 10 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*11)-1 downto CHANNEL_DWIDTH*10);
when 11 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*12)-1 downto CHANNEL_DWIDTH*11);
when 12 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*13)-1 downto CHANNEL_DWIDTH*12);
when 13 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*14)-1 downto CHANNEL_DWIDTH*13);
when 14 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*15)-1 downto CHANNEL_DWIDTH*14);
when others => -- 15 case
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*16)-1 downto CHANNEL_DWIDTH*15);
end case;
end process DO_16XN_NUX;
end generate GEN_16XN;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_32XN
--
-- If Generate Description:
-- 32 channel input mux case
--
--
------------------------------------------------------------
GEN_32XN : if (NUM_MUX_CHANNELS = 32) generate
-- local signals
signal sig_mux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_mux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_mux_sel_int : integer := 0;
signal sig_mux_sel_int_local : integer := 0;
signal sig_mux_dout : std_logic_vector(CHANNEL_DWIDTH-1 downto 0) := (others => '0');
begin
-- Rip the Mux Select bits needed for the Mux case from the input select bus
sig_mux_sel_slice <= mstr2data_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX);
sig_mux_sel_unsgnd <= UNSIGNED(sig_mux_sel_slice); -- convert to unsigned
sig_mux_sel_int <= TO_INTEGER(sig_mux_sel_unsgnd); -- convert to integer for MTI compile issue
-- with locally static subtype error in each of the
-- Mux IfGens
sig_mux_sel_int_local <= sig_mux_sel_int;
sig_rdmux_dout <= sig_mux_dout;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_32XN_NUX
--
-- Process Description:
-- Implement the 32XN Mux
--
-------------------------------------------------------------
DO_32XN_NUX : process (sig_mux_sel_int_local,
mmap_read_data_in)
begin
case sig_mux_sel_int_local is
when 0 =>
sig_mux_dout <= mmap_read_data_in(CHANNEL_DWIDTH-1 downto 0);
when 1 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*2)-1 downto CHANNEL_DWIDTH*1);
when 2 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*3)-1 downto CHANNEL_DWIDTH*2);
when 3 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*4)-1 downto CHANNEL_DWIDTH*3);
when 4 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*5)-1 downto CHANNEL_DWIDTH*4);
when 5 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*6)-1 downto CHANNEL_DWIDTH*5);
when 6 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*7)-1 downto CHANNEL_DWIDTH*6);
when 7 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*8)-1 downto CHANNEL_DWIDTH*7);
when 8 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*9)-1 downto CHANNEL_DWIDTH*8);
when 9 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*10)-1 downto CHANNEL_DWIDTH*9);
when 10 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*11)-1 downto CHANNEL_DWIDTH*10);
when 11 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*12)-1 downto CHANNEL_DWIDTH*11);
when 12 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*13)-1 downto CHANNEL_DWIDTH*12);
when 13 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*14)-1 downto CHANNEL_DWIDTH*13);
when 14 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*15)-1 downto CHANNEL_DWIDTH*14);
when 15 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*16)-1 downto CHANNEL_DWIDTH*15);
when 16 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*17)-1 downto CHANNEL_DWIDTH*16);
when 17 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*18)-1 downto CHANNEL_DWIDTH*17);
when 18 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*19)-1 downto CHANNEL_DWIDTH*18);
when 19 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*20)-1 downto CHANNEL_DWIDTH*19);
when 20 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*21)-1 downto CHANNEL_DWIDTH*20);
when 21 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*22)-1 downto CHANNEL_DWIDTH*21);
when 22 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*23)-1 downto CHANNEL_DWIDTH*22);
when 23 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*24)-1 downto CHANNEL_DWIDTH*23);
when 24 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*25)-1 downto CHANNEL_DWIDTH*24);
when 25 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*26)-1 downto CHANNEL_DWIDTH*25);
when 26 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*27)-1 downto CHANNEL_DWIDTH*26);
when 27 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*28)-1 downto CHANNEL_DWIDTH*27);
when 28 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*29)-1 downto CHANNEL_DWIDTH*28);
when 29 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*30)-1 downto CHANNEL_DWIDTH*29);
when 30 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*31)-1 downto CHANNEL_DWIDTH*30);
when others => -- 31 case
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*32)-1 downto CHANNEL_DWIDTH*31);
end case;
end process DO_32XN_NUX;
end generate GEN_32XN;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_64XN
--
-- If Generate Description:
-- 64 channel input mux case
--
--
------------------------------------------------------------
GEN_64XN : if (NUM_MUX_CHANNELS = 64) generate
-- local signals
signal sig_mux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_mux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_mux_sel_int : integer := 0;
signal sig_mux_sel_int_local : integer := 0;
signal sig_mux_dout : std_logic_vector(CHANNEL_DWIDTH-1 downto 0) := (others => '0');
begin
-- Rip the Mux Select bits needed for the Mux case from the input select bus
sig_mux_sel_slice <= mstr2data_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX);
sig_mux_sel_unsgnd <= UNSIGNED(sig_mux_sel_slice); -- convert to unsigned
sig_mux_sel_int <= TO_INTEGER(sig_mux_sel_unsgnd); -- convert to integer for MTI compile issue
-- with locally static subtype error in each of the
-- Mux IfGens
sig_mux_sel_int_local <= sig_mux_sel_int;
sig_rdmux_dout <= sig_mux_dout;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_64XN_NUX
--
-- Process Description:
-- Implement the 64XN Mux
--
-------------------------------------------------------------
DO_64XN_NUX : process (sig_mux_sel_int_local,
mmap_read_data_in)
begin
case sig_mux_sel_int_local is
when 0 =>
sig_mux_dout <= mmap_read_data_in(CHANNEL_DWIDTH-1 downto 0) ;
when 1 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*2)-1 downto CHANNEL_DWIDTH*1) ;
when 2 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*3)-1 downto CHANNEL_DWIDTH*2) ;
when 3 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*4)-1 downto CHANNEL_DWIDTH*3) ;
when 4 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*5)-1 downto CHANNEL_DWIDTH*4) ;
when 5 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*6)-1 downto CHANNEL_DWIDTH*5) ;
when 6 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*7)-1 downto CHANNEL_DWIDTH*6) ;
when 7 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*8)-1 downto CHANNEL_DWIDTH*7) ;
when 8 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*9)-1 downto CHANNEL_DWIDTH*8) ;
when 9 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*10)-1 downto CHANNEL_DWIDTH*9) ;
when 10 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*11)-1 downto CHANNEL_DWIDTH*10);
when 11 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*12)-1 downto CHANNEL_DWIDTH*11);
when 12 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*13)-1 downto CHANNEL_DWIDTH*12);
when 13 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*14)-1 downto CHANNEL_DWIDTH*13);
when 14 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*15)-1 downto CHANNEL_DWIDTH*14);
when 15 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*16)-1 downto CHANNEL_DWIDTH*15);
when 16 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*17)-1 downto CHANNEL_DWIDTH*16);
when 17 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*18)-1 downto CHANNEL_DWIDTH*17);
when 18 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*19)-1 downto CHANNEL_DWIDTH*18);
when 19 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*20)-1 downto CHANNEL_DWIDTH*19);
when 20 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*21)-1 downto CHANNEL_DWIDTH*20);
when 21 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*22)-1 downto CHANNEL_DWIDTH*21);
when 22 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*23)-1 downto CHANNEL_DWIDTH*22);
when 23 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*24)-1 downto CHANNEL_DWIDTH*23);
when 24 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*25)-1 downto CHANNEL_DWIDTH*24);
when 25 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*26)-1 downto CHANNEL_DWIDTH*25);
when 26 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*27)-1 downto CHANNEL_DWIDTH*26);
when 27 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*28)-1 downto CHANNEL_DWIDTH*27);
when 28 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*29)-1 downto CHANNEL_DWIDTH*28);
when 29 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*30)-1 downto CHANNEL_DWIDTH*29);
when 30 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*31)-1 downto CHANNEL_DWIDTH*30);
when 31 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*32)-1 downto CHANNEL_DWIDTH*31);
when 32 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*33)-1 downto CHANNEL_DWIDTH*32);
when 33 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*34)-1 downto CHANNEL_DWIDTH*33);
when 34 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*35)-1 downto CHANNEL_DWIDTH*34);
when 35 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*36)-1 downto CHANNEL_DWIDTH*35);
when 36 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*37)-1 downto CHANNEL_DWIDTH*36);
when 37 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*38)-1 downto CHANNEL_DWIDTH*37);
when 38 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*39)-1 downto CHANNEL_DWIDTH*38);
when 39 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*40)-1 downto CHANNEL_DWIDTH*39);
when 40 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*41)-1 downto CHANNEL_DWIDTH*40);
when 41 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*42)-1 downto CHANNEL_DWIDTH*41);
when 42 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*43)-1 downto CHANNEL_DWIDTH*42);
when 43 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*44)-1 downto CHANNEL_DWIDTH*43);
when 44 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*45)-1 downto CHANNEL_DWIDTH*44);
when 45 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*46)-1 downto CHANNEL_DWIDTH*45);
when 46 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*47)-1 downto CHANNEL_DWIDTH*46);
when 47 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*48)-1 downto CHANNEL_DWIDTH*47);
when 48 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*49)-1 downto CHANNEL_DWIDTH*48);
when 49 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*50)-1 downto CHANNEL_DWIDTH*49);
when 50 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*51)-1 downto CHANNEL_DWIDTH*50);
when 51 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*52)-1 downto CHANNEL_DWIDTH*51);
when 52 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*53)-1 downto CHANNEL_DWIDTH*52);
when 53 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*54)-1 downto CHANNEL_DWIDTH*53);
when 54 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*55)-1 downto CHANNEL_DWIDTH*54);
when 55 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*56)-1 downto CHANNEL_DWIDTH*55);
when 56 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*57)-1 downto CHANNEL_DWIDTH*56);
when 57 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*58)-1 downto CHANNEL_DWIDTH*57);
when 58 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*59)-1 downto CHANNEL_DWIDTH*58);
when 59 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*60)-1 downto CHANNEL_DWIDTH*59);
when 60 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*61)-1 downto CHANNEL_DWIDTH*60);
when 61 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*62)-1 downto CHANNEL_DWIDTH*61);
when 62 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*63)-1 downto CHANNEL_DWIDTH*62);
when others => -- 63 case
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*64)-1 downto CHANNEL_DWIDTH*63);
end case;
end process DO_64XN_NUX;
end generate GEN_64XN;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_128XN
--
-- If Generate Description:
-- 128 channel input mux case
--
--
------------------------------------------------------------
GEN_128XN : if (NUM_MUX_CHANNELS = 128) generate
-- local signals
signal sig_mux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_mux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_mux_sel_int : integer := 0;
signal sig_mux_sel_int_local : integer := 0;
signal sig_mux_dout : std_logic_vector(CHANNEL_DWIDTH-1 downto 0) := (others => '0');
begin
-- Rip the Mux Select bits needed for the Mux case from the input select bus
sig_mux_sel_slice <= mstr2data_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX);
sig_mux_sel_unsgnd <= UNSIGNED(sig_mux_sel_slice); -- convert to unsigned
sig_mux_sel_int <= TO_INTEGER(sig_mux_sel_unsgnd); -- convert to integer for MTI compile issue
-- with locally static subtype error in each of the
-- Mux IfGens
sig_mux_sel_int_local <= sig_mux_sel_int;
sig_rdmux_dout <= sig_mux_dout;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_128XN_NUX
--
-- Process Description:
-- Implement the 64XN Mux
--
-------------------------------------------------------------
DO_128XN_NUX : process (sig_mux_sel_int_local,
mmap_read_data_in)
begin
case sig_mux_sel_int_local is
when 0 =>
sig_mux_dout <= mmap_read_data_in(CHANNEL_DWIDTH-1 downto 0) ;
when 1 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*2)-1 downto CHANNEL_DWIDTH*1) ;
when 2 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*3)-1 downto CHANNEL_DWIDTH*2) ;
when 3 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*4)-1 downto CHANNEL_DWIDTH*3) ;
when 4 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*5)-1 downto CHANNEL_DWIDTH*4) ;
when 5 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*6)-1 downto CHANNEL_DWIDTH*5) ;
when 6 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*7)-1 downto CHANNEL_DWIDTH*6) ;
when 7 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*8)-1 downto CHANNEL_DWIDTH*7) ;
when 8 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*9)-1 downto CHANNEL_DWIDTH*8) ;
when 9 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*10)-1 downto CHANNEL_DWIDTH*9) ;
when 10 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*11)-1 downto CHANNEL_DWIDTH*10);
when 11 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*12)-1 downto CHANNEL_DWIDTH*11);
when 12 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*13)-1 downto CHANNEL_DWIDTH*12);
when 13 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*14)-1 downto CHANNEL_DWIDTH*13);
when 14 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*15)-1 downto CHANNEL_DWIDTH*14);
when 15 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*16)-1 downto CHANNEL_DWIDTH*15);
when 16 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*17)-1 downto CHANNEL_DWIDTH*16);
when 17 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*18)-1 downto CHANNEL_DWIDTH*17);
when 18 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*19)-1 downto CHANNEL_DWIDTH*18);
when 19 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*20)-1 downto CHANNEL_DWIDTH*19);
when 20 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*21)-1 downto CHANNEL_DWIDTH*20);
when 21 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*22)-1 downto CHANNEL_DWIDTH*21);
when 22 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*23)-1 downto CHANNEL_DWIDTH*22);
when 23 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*24)-1 downto CHANNEL_DWIDTH*23);
when 24 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*25)-1 downto CHANNEL_DWIDTH*24);
when 25 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*26)-1 downto CHANNEL_DWIDTH*25);
when 26 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*27)-1 downto CHANNEL_DWIDTH*26);
when 27 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*28)-1 downto CHANNEL_DWIDTH*27);
when 28 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*29)-1 downto CHANNEL_DWIDTH*28);
when 29 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*30)-1 downto CHANNEL_DWIDTH*29);
when 30 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*31)-1 downto CHANNEL_DWIDTH*30);
when 31 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*32)-1 downto CHANNEL_DWIDTH*31);
when 32 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*33)-1 downto CHANNEL_DWIDTH*32);
when 33 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*34)-1 downto CHANNEL_DWIDTH*33);
when 34 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*35)-1 downto CHANNEL_DWIDTH*34);
when 35 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*36)-1 downto CHANNEL_DWIDTH*35);
when 36 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*37)-1 downto CHANNEL_DWIDTH*36);
when 37 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*38)-1 downto CHANNEL_DWIDTH*37);
when 38 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*39)-1 downto CHANNEL_DWIDTH*38);
when 39 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*40)-1 downto CHANNEL_DWIDTH*39);
when 40 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*41)-1 downto CHANNEL_DWIDTH*40);
when 41 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*42)-1 downto CHANNEL_DWIDTH*41);
when 42 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*43)-1 downto CHANNEL_DWIDTH*42);
when 43 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*44)-1 downto CHANNEL_DWIDTH*43);
when 44 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*45)-1 downto CHANNEL_DWIDTH*44);
when 45 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*46)-1 downto CHANNEL_DWIDTH*45);
when 46 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*47)-1 downto CHANNEL_DWIDTH*46);
when 47 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*48)-1 downto CHANNEL_DWIDTH*47);
when 48 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*49)-1 downto CHANNEL_DWIDTH*48);
when 49 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*50)-1 downto CHANNEL_DWIDTH*49);
when 50 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*51)-1 downto CHANNEL_DWIDTH*50);
when 51 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*52)-1 downto CHANNEL_DWIDTH*51);
when 52 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*53)-1 downto CHANNEL_DWIDTH*52);
when 53 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*54)-1 downto CHANNEL_DWIDTH*53);
when 54 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*55)-1 downto CHANNEL_DWIDTH*54);
when 55 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*56)-1 downto CHANNEL_DWIDTH*55);
when 56 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*57)-1 downto CHANNEL_DWIDTH*56);
when 57 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*58)-1 downto CHANNEL_DWIDTH*57);
when 58 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*59)-1 downto CHANNEL_DWIDTH*58);
when 59 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*60)-1 downto CHANNEL_DWIDTH*59);
when 60 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*61)-1 downto CHANNEL_DWIDTH*60);
when 61 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*62)-1 downto CHANNEL_DWIDTH*61);
when 62 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*63)-1 downto CHANNEL_DWIDTH*62);
when 63 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*64)-1 downto CHANNEL_DWIDTH*63);
when 64 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*65)-1 downto CHANNEL_DWIDTH*64) ;
when 65 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*66)-1 downto CHANNEL_DWIDTH*65) ;
when 66 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*67)-1 downto CHANNEL_DWIDTH*66) ;
when 67 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*68)-1 downto CHANNEL_DWIDTH*67) ;
when 68 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*69)-1 downto CHANNEL_DWIDTH*68) ;
when 69 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*70)-1 downto CHANNEL_DWIDTH*69) ;
when 70 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*71)-1 downto CHANNEL_DWIDTH*70) ;
when 71 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*72)-1 downto CHANNEL_DWIDTH*71) ;
when 72 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*73)-1 downto CHANNEL_DWIDTH*72) ;
when 73 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*74)-1 downto CHANNEL_DWIDTH*73) ;
when 74 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*75)-1 downto CHANNEL_DWIDTH*74) ;
when 75 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*76)-1 downto CHANNEL_DWIDTH*75) ;
when 76 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*77)-1 downto CHANNEL_DWIDTH*76) ;
when 77 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*78)-1 downto CHANNEL_DWIDTH*77) ;
when 78 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*79)-1 downto CHANNEL_DWIDTH*78) ;
when 79 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*80)-1 downto CHANNEL_DWIDTH*79) ;
when 80 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*81)-1 downto CHANNEL_DWIDTH*80) ;
when 81 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*82)-1 downto CHANNEL_DWIDTH*81) ;
when 82 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*83)-1 downto CHANNEL_DWIDTH*82) ;
when 83 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*84)-1 downto CHANNEL_DWIDTH*83) ;
when 84 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*85)-1 downto CHANNEL_DWIDTH*84) ;
when 85 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*86)-1 downto CHANNEL_DWIDTH*85) ;
when 86 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*87)-1 downto CHANNEL_DWIDTH*86) ;
when 87 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*88)-1 downto CHANNEL_DWIDTH*87) ;
when 88 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*89)-1 downto CHANNEL_DWIDTH*88) ;
when 89 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*90)-1 downto CHANNEL_DWIDTH*89) ;
when 90 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*91)-1 downto CHANNEL_DWIDTH*90) ;
when 91 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*92)-1 downto CHANNEL_DWIDTH*91) ;
when 92 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*93)-1 downto CHANNEL_DWIDTH*92) ;
when 93 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*94)-1 downto CHANNEL_DWIDTH*93) ;
when 94 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*95)-1 downto CHANNEL_DWIDTH*94) ;
when 95 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*96)-1 downto CHANNEL_DWIDTH*95) ;
when 96 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*97 )-1 downto CHANNEL_DWIDTH*96 ) ;
when 97 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*98 )-1 downto CHANNEL_DWIDTH*97 ) ;
when 98 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*99 )-1 downto CHANNEL_DWIDTH*98 ) ;
when 99 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*100)-1 downto CHANNEL_DWIDTH*99 ) ;
when 100 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*101)-1 downto CHANNEL_DWIDTH*100) ;
when 101 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*102)-1 downto CHANNEL_DWIDTH*101) ;
when 102 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*103)-1 downto CHANNEL_DWIDTH*102) ;
when 103 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*104)-1 downto CHANNEL_DWIDTH*103) ;
when 104 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*105)-1 downto CHANNEL_DWIDTH*104) ;
when 105 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*106)-1 downto CHANNEL_DWIDTH*105) ;
when 106 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*107)-1 downto CHANNEL_DWIDTH*106) ;
when 107 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*108)-1 downto CHANNEL_DWIDTH*107) ;
when 108 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*109)-1 downto CHANNEL_DWIDTH*108) ;
when 109 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*110)-1 downto CHANNEL_DWIDTH*109) ;
when 110 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*111)-1 downto CHANNEL_DWIDTH*110) ;
when 111 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*112)-1 downto CHANNEL_DWIDTH*111) ;
when 112 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*113)-1 downto CHANNEL_DWIDTH*112) ;
when 113 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*114)-1 downto CHANNEL_DWIDTH*113) ;
when 114 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*115)-1 downto CHANNEL_DWIDTH*114) ;
when 115 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*116)-1 downto CHANNEL_DWIDTH*115) ;
when 116 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*117)-1 downto CHANNEL_DWIDTH*116) ;
when 117 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*118)-1 downto CHANNEL_DWIDTH*117) ;
when 118 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*119)-1 downto CHANNEL_DWIDTH*118) ;
when 119 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*120)-1 downto CHANNEL_DWIDTH*119) ;
when 120 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*121)-1 downto CHANNEL_DWIDTH*120) ;
when 121 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*122)-1 downto CHANNEL_DWIDTH*121) ;
when 122 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*123)-1 downto CHANNEL_DWIDTH*122) ;
when 123 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*124)-1 downto CHANNEL_DWIDTH*123) ;
when 124 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*125)-1 downto CHANNEL_DWIDTH*124) ;
when 125 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*126)-1 downto CHANNEL_DWIDTH*125) ;
when 126 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*127)-1 downto CHANNEL_DWIDTH*126) ;
when others => -- 127 case
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*128)-1 downto CHANNEL_DWIDTH*127) ;
end case;
end process DO_128XN_NUX;
end generate GEN_128XN;
end implementation;
|
bsd-3-clause
|
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/Pmods/PmodMTDS_v1_0/ipshared/xilinx.com/axi_quad_spi_v3_2/hdl/src/vhdl/qspi_receive_transmit_reg.vhd
|
2
|
16493
|
-------------------------------------------------------------------------------
-- qspi_receive_reg.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- ** (c) Copyright [2010] - [2012] Xilinx, Inc. All rights reserved.*
-- ** *
-- ** This file contains confidential and proprietary information *
-- ** of Xilinx, Inc. and is protected under U.S. and *
-- ** international copyright and other intellectual property *
-- ** laws. *
-- ** *
-- ** DISCLAIMER *
-- ** This disclaimer is not a license and does not grant any *
-- ** rights to the materials distributed herewith. Except as *
-- ** otherwise provided in a valid license issued to you by *
-- ** Xilinx, and to the maximum extent permitted by applicable *
-- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- ** including negligence, or under any other theory of *
-- ** liability) for any loss or damage of any kind or nature *
-- ** related to, arising under or in connection with these *
-- ** materials, including for any direct, or any indirect, *
-- ** special, incidental, or consequential loss or damage *
-- ** (including loss of data, profits, goodwill, or any type of *
-- ** loss or damage suffered as a result of any action brought *
-- ** by a third party) even if such damage or loss was *
-- ** reasonably foreseeable or Xilinx had been advised of the *
-- ** possibility of the same. *
-- ** *
-- ** CRITICAL APPLICATIONS *
-- ** Xilinx products are not designed or intended to be fail- *
-- ** safe, or for use in any application requiring fail-safe *
-- ** performance, such as life-support or safety devices or *
-- ** systems, Class III medical devices, nuclear facilities, *
-- ** applications related to the deployment of airbags, or any *
-- ** other applications that could lead to death, personal *
-- ** injury, or severe property or environmental damage *
-- ** (individually and collectively, "Critical *
-- ** Applications"). Customer assumes the sole risk and *
-- ** liability of any use of Xilinx products in Critical *
-- ** Applications, subject only to applicable laws and *
-- ** regulations governing limitations on product liability. *
-- ** *
-- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename: qspi_receive_reg.vhd
-- Version: v3.0
-- Description: Quad Serial Peripheral Interface (SPI) Module for interfacing
-- with a 32-bit AXI4 Bus.
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.all;
use lib_pkg_v1_0_2.lib_pkg.RESET_ACTIVE;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_NUM_TRANSFER_BITS -- SPI Serial transfer width.
-- Can be 8, 16 or 32 bit wide
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- SYSTEM
-- Bus2IP_Clk -- Bus to IP clock
-- Soft_Reset_op -- Soft_Reset_op Signal
-- SLAVE ATTACHMENT INTERFACE
-- Bus2IP_Reg_RdCE -- Read CE for receive register
-- IP2Bus_RdAck_sa -- IP2Bus read acknowledgement
-- IP2Bus_Receive_Reg_Data -- Data to be send on the bus
-- Receive_ip2bus_error -- Receive register error signal
-- SPI MODULE INTERFACE
-- DRR_Overrun -- DRR Overrun bit
-- SR_7_Rx_Empty -- Receive register empty signal
-- SPI_Received_Data -- Data received from receive register
-- SPIXfer_done -- SPI transfer done flag
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity Declaration
-------------------------------------------------------------------------------
entity qspi_receive_transmit_reg is
generic
(
C_S_AXI_DATA_WIDTH : integer; -- 32 bits
---------------------
C_NUM_TRANSFER_BITS : integer -- Number of bits to be transferred
---------------------
);
port
(
Bus2IP_Clk : in std_logic;
Soft_Reset_op : in std_logic;
------------------------------------
-- RECEIVER RELATED SIGNALS
--=========================
Bus2IP_Receive_Reg_RdCE : in std_logic;
Receive_ip2bus_error : out std_logic;
IP2Bus_Receive_Reg_Data : out std_logic_vector
(0 to (C_NUM_TRANSFER_BITS-1));
-- SPI module ports
SPIXfer_done : in std_logic;
SPI_Received_Data : in std_logic_vector
(0 to (C_NUM_TRANSFER_BITS-1));
-- receive & transmit reg signals
-- DRR_Overrun : out std_logic;
SR_7_Rx_Empty : out std_logic;
------------------------------------
-- TRANSMITTER RELATED SIGNALS
--============================
-- Slave attachment ports
Bus2IP_Transmit_Reg_Data : in std_logic_vector(0 to (C_S_AXI_DATA_WIDTH-1));
Bus2IP_Transmit_Reg_WrCE : in std_logic;
Wr_ce_reduce_ack_gen : in std_logic;
Rd_ce_reduce_ack_gen : in std_logic;
--SPI Transmitter signals
Transmit_ip2bus_error : out std_logic;
-- SPI module ports
DTR_underrun : in std_logic;
SR_5_Tx_Empty : out std_logic;
tx_empty_signal_handshake_req : out std_logic;
tx_empty_signal_handshake_gnt : in std_logic;
DTR_Underrun_strobe : out std_logic;
Transmit_Reg_Data_Out : out std_logic_vector
(0 to (C_NUM_TRANSFER_BITS-1))
);
end qspi_receive_transmit_reg;
-------------------------------------------------------------------------------
-- Architecture
---------------
architecture imp of qspi_receive_transmit_reg is
---------------------------------------------------
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-- Signal Declarations
----------------------
signal Received_register_Data : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
signal sr_7_Rx_Empty_reg : std_logic;
signal drr_Overrun_strobe : std_logic;
--------------------------------------------
signal sr_5_Tx_Empty_i : std_logic;
signal tx_empty_signal_handshake_req_i : std_logic;
signal tx_Reg_Soft_Reset_op : std_logic;
signal dtr_Underrun_strobe_i : std_logic;
signal dtr_underrun_d1 : std_logic;
signal SPIXfer_done_delay : std_logic;
constant RESET_ACTIVE : std_logic := '1';
--------------------------------------------
begin
-----
-- RECEIVER LOGIC
--=================
-- Combinatorial operations
----------------------------
SR_7_Rx_Empty <= sr_7_Rx_Empty_reg;
-- DRR_Overrun <= drr_Overrun_strobe;
DELAY_XFER_DONE_P:process(Bus2IP_Clk)
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Soft_Reset_op = RESET_ACTIVE) then
SPIXfer_done_delay <= '0';
else
SPIXfer_done_delay <= SPIXfer_done;
end if;
end if;
end process DELAY_XFER_DONE_P;
-------------------------------------------------------------------------------
-- RECEIVE_REG_GENERATE : Receive Register Read Operation from SPI_Received_Data
-- register
--------------------------
RECEIVE_REG_GENERATE: for i in 0 to C_NUM_TRANSFER_BITS-1 generate
begin
-----
RECEIVE_REG_PROCESS_P:process(Bus2IP_Clk)
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Soft_Reset_op = RESET_ACTIVE) then
Received_register_Data(i) <= '0';
elsif (SPIXfer_done_delay = '1') then--((sr_7_Rx_Empty_reg and SPIXfer_done) = '1') then
Received_register_Data(i) <= SPI_Received_Data(i);
end if;
end if;
end process RECEIVE_REG_PROCESS_P;
-----
end generate RECEIVE_REG_GENERATE;
-------------------------------------------------------------------------------
-- RECEIVE_REG_RD_GENERATE : Receive Register Read Operation
-----------------------------
RECEIVE_REG_RD_GENERATE: for i in 0 to C_NUM_TRANSFER_BITS-1 generate
begin
IP2Bus_Receive_Reg_Data(i) <= Received_register_Data(i) and
Bus2IP_Receive_Reg_RdCE;
end generate RECEIVE_REG_RD_GENERATE;
-------------------------------------------------------------------------------
-- RX_ERROR_ACK_REG_PROCESS_P : Strobe error when receive register is empty
--------------------------------
RX_ERROR_ACK_REG_PROCESS_P:process(Bus2IP_Clk)
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
Receive_ip2bus_error <= sr_7_Rx_Empty_reg and
Bus2IP_Receive_Reg_RdCE;
end if;
end process RX_ERROR_ACK_REG_PROCESS_P;
-------------------------------------------------------------------------------
-- SR_7_RX_EMPTY_REG_PROCESS_P : SR_7_Rx_Empty register
-------------------------------
SR_7_RX_EMPTY_REG_PROCESS_P:process(Bus2IP_Clk)
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Soft_Reset_op = RESET_ACTIVE) then
sr_7_Rx_Empty_reg <= '1';
elsif (SPIXfer_done = '1') then
sr_7_Rx_Empty_reg <= '0';
elsif ((rd_ce_reduce_ack_gen and Bus2IP_Receive_Reg_RdCE) = '1') then
sr_7_Rx_Empty_reg <= '1';
end if;
end if;
end process SR_7_RX_EMPTY_REG_PROCESS_P;
----******************************************************************************
-- TRANSMITTER LOGIC
--==================
-- Combinatorial operations
----------------------------
tx_empty_signal_handshake_req <= tx_empty_signal_handshake_req_i;
SR_5_Tx_Empty <= sr_5_Tx_Empty_i;
DTR_Underrun_strobe <= dtr_Underrun_strobe_i;
tx_Reg_Soft_Reset_op <= SPIXfer_done or Soft_Reset_op;
--------------------------------------
-------------------------------------------------------------------------------
-- TRANSMIT_REG_GENERATE : Transmit Register Write
---------------------------
TRANSMIT_REG_GENERATE: for i in 0 to C_NUM_TRANSFER_BITS-1 generate
begin
-----
TRANSMIT_REG_PROCESS_P:process(Bus2IP_Clk)
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (tx_Reg_Soft_Reset_op = RESET_ACTIVE) then
Transmit_Reg_Data_Out(i) <= '0';
elsif ((wr_ce_reduce_ack_gen and Bus2IP_Transmit_Reg_WrCE) = '1')then
Transmit_Reg_Data_Out(i) <=
Bus2IP_Transmit_Reg_Data
(C_S_AXI_DATA_WIDTH-C_NUM_TRANSFER_BITS+i) after 100 ps;
end if;
end if;
end process TRANSMIT_REG_PROCESS_P;
-----
end generate TRANSMIT_REG_GENERATE;
-----------------------------------
-- TX_ERROR_ACK_REG_PROCESS_P : Strobe error when transmit register is full
--------------------------------
TX_ERROR_ACK_REG_PROCESS_P:process(Bus2IP_Clk)
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
Transmit_ip2bus_error <= not(sr_5_Tx_Empty_i) and
Bus2IP_Transmit_Reg_WrCE;
end if;
end process TX_ERROR_ACK_REG_PROCESS_P;
-------------------------------------------------------------------------------
-- SR_5_TX_EMPTY_REG_PROCESS_P : Tx Empty generate
-------------------------------
SR_5_TX_EMPTY_REG_PROCESS_P:process(Bus2IP_Clk)
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Soft_Reset_op = RESET_ACTIVE) then
sr_5_Tx_Empty_i <= '1';
elsif ((wr_ce_reduce_ack_gen and Bus2IP_Transmit_Reg_WrCE) = '1') then
sr_5_Tx_Empty_i <= '0';
elsif (SPIXfer_done = '1') then
sr_5_Tx_Empty_i <= '1';
end if;
end if;
end process SR_5_TX_EMPTY_REG_PROCESS_P;
-------------------------------------------------------------------------------
-- tx_empty_signal_handshake_req_i
-------------------------------
process(Bus2IP_Clk)
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Soft_Reset_op = RESET_ACTIVE) then
tx_empty_signal_handshake_req_i <= '1';
elsif (sr_5_Tx_Empty_i = '1') then
tx_empty_signal_handshake_req_i <= '1';
elsif (sr_5_Tx_Empty_i = '0' and tx_empty_signal_handshake_gnt = '1') then
tx_empty_signal_handshake_req_i <= '0';
end if;
end if;
end process ;
-------------------------------------------------------------------------------
-- DTR_UNDERRUN_REG_PROCESS_P : Strobe to interrupt for transmit data underrun
-- which happens only in slave mode
-----------------------------
DTR_UNDERRUN_REG_PROCESS_P:process(Bus2IP_Clk)
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Soft_Reset_op = RESET_ACTIVE) then
dtr_underrun_d1 <= '0';
else
dtr_underrun_d1 <= DTR_underrun;
end if;
end if;
end process DTR_UNDERRUN_REG_PROCESS_P;
---------------------------------------
dtr_Underrun_strobe_i <= DTR_underrun and (not dtr_underrun_d1);
--******************************************************************************
end imp;
--------------------------------------------------------------------------------
|
bsd-3-clause
|
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/usb2device_v1_0/src/axi_dma_0/axi_sg_v4_1_2/hdl/src/vhdl/axi_sg_ftch_noqueue.vhd
|
7
|
24940
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_ftch_noqueue.vhd
-- Description: This entity is the no queue version
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library axi_sg_v4_1_2;
use axi_sg_v4_1_2.axi_sg_pkg.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_ftch_noqueue is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width
C_M_AXIS_SG_TDATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Stream Data Width
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0;
C_AXIS_IS_ASYNC : integer range 0 to 1 := 0;
C_ASYNC : integer range 0 to 1 := 0;
C_SG_WORDS_TO_FETCH : integer range 8 to 13 := 8;
C_ENABLE_CDMA : integer range 0 to 1 := 0;
C_ENABLE_CH1 : integer range 0 to 1 := 0;
C_FAMILY : string := "virtex7"
-- Device family used for proper BRAM selection
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_primary_aclk : in std_logic ;
m_axi_sg_aresetn : in std_logic ; --
p_reset_n : in std_logic ;
--
-- Channel Control --
desc_flush : in std_logic ; --
ch1_cntrl_strm_stop : in std_logic ;
ftch_active : in std_logic ; --
ftch_queue_empty : out std_logic ; --
ftch_queue_full : out std_logic ; --
sof_ftch_desc : in std_logic ;
desc2_flush : in std_logic ; --
ftch2_active : in std_logic ; --
ftch2_queue_empty : out std_logic ; --
ftch2_queue_full : out std_logic ; --
--
writing_nxtdesc_in : in std_logic ; --
writing_curdesc_out : out std_logic ; --
writing2_curdesc_out : out std_logic ; --
-- DataMover Command --
ftch_cmnd_wr : in std_logic ; --
ftch_cmnd_data : in std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
--
-- MM2S Stream In from DataMover --
m_axis_mm2s_tdata : in std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
m_axis_mm2s_tlast : in std_logic ; --
m_axis_mm2s_tvalid : in std_logic ; --
m_axis_mm2s_tready : out std_logic ; --
m_axis2_mm2s_tready : out std_logic ; --
data_concat : in std_logic_vector --
(95 downto 0) ; --
data_concat_64 : in std_logic_vector --
(31 downto 0) ; --
data_concat_mcdma : in std_logic_vector --
(63 downto 0) ; --
next_bd : in std_logic_vector (C_M_AXI_SG_ADDR_WIDTH-1 downto 0);
data_concat_tlast : in std_logic ; --
data_concat_valid : in std_logic ; --
--
-- Channel 1 AXI Fetch Stream Out --
m_axis_ftch_tdata : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
m_axis_ftch_tvalid : out std_logic ; --
m_axis_ftch_tready : in std_logic ; --
m_axis_ftch_tlast : out std_logic ; --
m_axis_ftch_tdata_new : out std_logic_vector --
(96+31*C_ENABLE_CDMA+(2+C_ENABLE_CDMA)*(C_M_AXI_SG_ADDR_WIDTH-32) downto 0); --
m_axis_ftch_tdata_mcdma_new : out std_logic_vector --
(63 downto 0); --
m_axis_ftch_tvalid_new : out std_logic ; --
m_axis_ftch_desc_available : out std_logic ;
m_axis2_ftch_tdata : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
m_axis2_ftch_tvalid : out std_logic ; --
m_axis2_ftch_tready : in std_logic ; --
m_axis2_ftch_tlast : out std_logic ; --
m_axis2_ftch_tdata_new : out std_logic_vector --
(96+31*C_ENABLE_CDMA+(2+C_ENABLE_CDMA)*(C_M_AXI_SG_ADDR_WIDTH-32) downto 0); --
m_axis2_ftch_tdata_mcdma_new : out std_logic_vector --
(63 downto 0); --
m_axis2_ftch_tdata_mcdma_nxt : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
m_axis2_ftch_tvalid_new : out std_logic ; --
m_axis2_ftch_desc_available : out std_logic ;
m_axis_mm2s_cntrl_tdata : out std_logic_vector --
(31 downto 0); --
m_axis_mm2s_cntrl_tkeep : out std_logic_vector --
(3 downto 0); --
m_axis_mm2s_cntrl_tvalid : out std_logic ; --
m_axis_mm2s_cntrl_tready : in std_logic := '0'; --
m_axis_mm2s_cntrl_tlast : out std_logic --
);
end axi_sg_ftch_noqueue;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_ftch_noqueue is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- Channel 1 internal signals
signal curdesc_tdata : std_logic_vector
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc_tvalid : std_logic := '0';
signal ftch_tvalid : std_logic := '0';
signal ftch_tdata : std_logic_vector
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal ftch_tlast : std_logic := '0';
signal ftch_tready : std_logic := '0';
-- Misc Signals
signal writing_curdesc : std_logic := '0';
signal writing_nxtdesc : std_logic := '0';
signal msb_curdesc : std_logic_vector(31 downto 0) := (others => '0');
signal ftch_tdata_new_64 : std_logic_vector (C_M_AXI_SG_ADDR_WIDTH-1 downto 0);
signal writing_lsb : std_logic := '0';
signal writing_msb : std_logic := '0';
signal ftch_active_int : std_logic := '0';
signal ftch_tvalid_mult : std_logic := '0';
signal ftch_tdata_mult : std_logic_vector
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal ftch_tlast_mult : std_logic := '0';
signal counter : std_logic_vector (3 downto 0) := (others => '0');
signal wr_cntl : std_logic := '0';
signal ftch_tdata_new : std_logic_vector (96+31*C_ENABLE_CDMA downto 0);
signal queue_wren, queue_rden : std_logic := '0';
signal queue_din : std_logic_vector (32 downto 0);
signal queue_dout : std_logic_vector (32 downto 0);
signal queue_empty, queue_full : std_logic := '0';
signal sof_ftch_desc_del, sof_ftch_desc_pulse : std_logic := '0';
signal sof_ftch_desc_del1 : std_logic := '0';
signal queue_sinit : std_logic := '0';
signal data_concat_mcdma_nxt : std_logic_vector (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal current_bd : std_logic_vector (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
queue_sinit <= not m_axi_sg_aresetn;
ftch_active_int <= ftch_active or ftch2_active;
ftch_tdata_new (64 downto 0) <= data_concat (95) & data_concat (63 downto 0);-- when (ftch_active = '1') else (others =>'0');
ftch_tdata_new (96 downto 65) <= current_bd (31 downto 0);
ADDR641 : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
ftch_tdata_new_64 <= data_concat_64 & current_bd (C_M_AXI_SG_ADDR_WIDTH-1 downto 32);
end generate ADDR641;
---------------------------------------------------------------------------
-- Write current descriptor to FIFO or out channel port
---------------------------------------------------------------------------
NXT_BD_MCDMA : if C_ENABLE_MULTI_CHANNEL = 1 generate
begin
NEXT_BD_S2MM : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
data_concat_mcdma_nxt <= (others => '0');
elsif (ftch2_active = '1') then
data_concat_mcdma_nxt <= next_bd;
end if;
end if;
end process NEXT_BD_S2MM;
end generate NXT_BD_MCDMA;
WRITE_CURDESC_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
current_bd <= (others => '0');
--
-- -- Write LSB Address on command write
elsif(ftch_cmnd_wr = '1' and ftch_active_int = '1')then
current_bd <= ftch_cmnd_data((C_M_AXI_SG_ADDR_WIDTH-32)+DATAMOVER_CMD_ADDRMSB_BOFST
+ DATAMOVER_CMD_ADDRLSB_BIT
downto DATAMOVER_CMD_ADDRLSB_BIT);
end if;
end if;
end process WRITE_CURDESC_PROCESS;
GEN_MULT_CHANNEL : if C_ENABLE_MULTI_CHANNEL = 1 generate
begin
ftch_tvalid_mult <= m_axis_mm2s_tvalid;
ftch_tdata_mult <= m_axis_mm2s_tdata;
ftch_tlast_mult <= m_axis_mm2s_tlast;
wr_cntl <= m_axis_mm2s_tvalid;
m_axis_mm2s_cntrl_tdata <= (others => '0');
m_axis_mm2s_cntrl_tkeep <= "0000";
m_axis_mm2s_cntrl_tvalid <= '0';
m_axis_mm2s_cntrl_tlast <= '0';
end generate GEN_MULT_CHANNEL;
GEN_NOMULT_CHANNEL : if C_ENABLE_MULTI_CHANNEL = 0 generate
begin
ftch_tvalid_mult <= '0'; --m_axis_mm2s_tvalid;
ftch_tdata_mult <= (others => '0'); --m_axis_mm2s_tdata;
ftch_tlast_mult <= '0'; --m_axis_mm2s_tlast;
CONTROL_STREAM : if C_SG_WORDS_TO_FETCH = 13 and C_ENABLE_CH1 = 1 generate
begin
SOF_DEL_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sof_ftch_desc_del <= '0';
else
sof_ftch_desc_del <= sof_ftch_desc;
end if;
end if;
end process SOF_DEL_PROCESS;
SOF_DEL1_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or m_axis_mm2s_tlast = '1')then
sof_ftch_desc_del1 <= '0';
elsif (m_axis_mm2s_tvalid = '1') then
sof_ftch_desc_del1 <= sof_ftch_desc;
end if;
end if;
end process SOF_DEL1_PROCESS;
sof_ftch_desc_pulse <= sof_ftch_desc and (not sof_ftch_desc_del1);
queue_wren <= not queue_full
and sof_ftch_desc
and m_axis_mm2s_tvalid
and ftch_active;
queue_rden <= not queue_empty
and m_axis_mm2s_cntrl_tready;
queue_din(C_M_AXIS_SG_TDATA_WIDTH) <= m_axis_mm2s_tlast;
queue_din(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) <= x"A0000000" when (sof_ftch_desc_pulse = '1') else m_axis_mm2s_tdata;
I_MM2S_CNTRL_STREAM : entity axi_sg_v4_1_2.axi_sg_cntrl_strm
generic map(
C_PRMRY_IS_ACLK_ASYNC => C_ASYNC ,
C_PRMY_CMDFIFO_DEPTH => 16, --FETCH_QUEUE_DEPTH ,
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH => C_M_AXIS_SG_TDATA_WIDTH ,
C_FAMILY => C_FAMILY
)
port map(
-- Secondary clock / reset
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Primary clock / reset
axi_prmry_aclk => m_axi_primary_aclk ,
p_reset_n => p_reset_n ,
-- MM2S Error
mm2s_stop => ch1_cntrl_strm_stop ,
-- Control Stream input
cntrlstrm_fifo_wren => queue_wren ,
cntrlstrm_fifo_full => queue_full ,
cntrlstrm_fifo_din => queue_din ,
-- Memory Map to Stream Control Stream Interface
m_axis_mm2s_cntrl_tdata => m_axis_mm2s_cntrl_tdata ,
m_axis_mm2s_cntrl_tkeep => m_axis_mm2s_cntrl_tkeep ,
m_axis_mm2s_cntrl_tvalid => m_axis_mm2s_cntrl_tvalid ,
m_axis_mm2s_cntrl_tready => m_axis_mm2s_cntrl_tready ,
m_axis_mm2s_cntrl_tlast => m_axis_mm2s_cntrl_tlast
);
end generate CONTROL_STREAM;
NO_CONTROL_STREAM : if C_SG_WORDS_TO_FETCH /= 13 or C_ENABLE_CH1 = 0 generate
begin
m_axis_mm2s_cntrl_tdata <= (others => '0');
m_axis_mm2s_cntrl_tkeep <= "0000";
m_axis_mm2s_cntrl_tvalid <= '0';
m_axis_mm2s_cntrl_tlast <= '0';
end generate NO_CONTROL_STREAM;
end generate GEN_NOMULT_CHANNEL;
---------------------------------------------------------------------------
-- Map internal stream to external
---------------------------------------------------------------------------
ftch_tready <= (m_axis_ftch_tready and ftch_active) or
(m_axis2_ftch_tready and ftch2_active);
ADDR64 : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
m_axis_ftch_tdata_new <= ftch_tdata_new_64 & ftch_tdata_new;
end generate ADDR64;
ADDR32 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
m_axis_ftch_tdata_new <= ftch_tdata_new;
end generate ADDR32;
m_axis_ftch_tdata_mcdma_new <= data_concat_mcdma;
m_axis_ftch_tvalid_new <= data_concat_valid and ftch_active;
m_axis_ftch_desc_available <= data_concat_tlast and ftch_active;
REG_FOR_STS_CNTRL : if C_SG_WORDS_TO_FETCH = 13 generate
begin
LATCH_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
m_axis2_ftch_tvalid_new <= '0';
m_axis2_ftch_desc_available <= '0';
else
m_axis2_ftch_tvalid_new <= data_concat_valid and ftch2_active;
m_axis2_ftch_desc_available <= data_concat_valid and ftch2_active;
end if;
end if;
end process LATCH_PROCESS;
LATCH2_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
m_axis2_ftch_tdata_new <= (others => '0');
elsif (data_concat_valid = '1' and ftch2_active = '1') then
m_axis2_ftch_tdata_new <= ftch_tdata_new;
end if;
end if;
end process LATCH2_PROCESS;
end generate REG_FOR_STS_CNTRL;
NO_REG_FOR_STS_CNTRL : if C_SG_WORDS_TO_FETCH /= 13 generate
begin
ADDR64 : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
m_axis2_ftch_tdata_new <= ftch_tdata_new_64 & ftch_tdata_new;
end generate ADDR64;
ADDR32 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
m_axis2_ftch_tdata_new <= ftch_tdata_new;
end generate ADDR32;
m_axis2_ftch_tvalid_new <= data_concat_valid and ftch2_active;
m_axis2_ftch_desc_available <= data_concat_valid and ftch2_active;
m_axis2_ftch_tdata_mcdma_new <= data_concat_mcdma;
m_axis2_ftch_tdata_mcdma_nxt <= data_concat_mcdma_nxt;
end generate NO_REG_FOR_STS_CNTRL;
m_axis_mm2s_tready <= ftch_tready;
m_axis2_mm2s_tready <= ftch_tready;
---------------------------------------------------------------------------
-- generate psuedo empty flag for Idle generation
---------------------------------------------------------------------------
Q_EMPTY_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk='1')then
if(m_axi_sg_aresetn = '0' or desc_flush = '1')then
ftch_queue_empty <= '1';
-- Else on valid and ready modify empty flag
elsif(ftch_tvalid = '1' and m_axis_ftch_tready = '1' and ftch_active = '1')then
-- On last mark as empty
if(ftch_tlast = '1' )then
ftch_queue_empty <= '1';
-- Otherwise mark as not empty
else
ftch_queue_empty <= '0';
end if;
end if;
end if;
end process Q_EMPTY_PROCESS;
Q2_EMPTY_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk='1')then
if(m_axi_sg_aresetn = '0' or desc2_flush = '1')then
ftch2_queue_empty <= '1';
-- Else on valid and ready modify empty flag
elsif(ftch_tvalid = '1' and m_axis2_ftch_tready = '1' and ftch2_active = '1')then
-- On last mark as empty
if(ftch_tlast = '1' )then
ftch2_queue_empty <= '1';
-- Otherwise mark as not empty
else
ftch2_queue_empty <= '0';
end if;
end if;
end if;
end process Q2_EMPTY_PROCESS;
-- do not need to indicate full to axi_sg_ftch_sm. Only
-- needed for queue case to allow other channel to be serviced
-- if it had queue room
ftch_queue_full <= '0';
ftch2_queue_full <= '0';
-- If writing curdesc out then flag for proper mux selection
writing_curdesc <= curdesc_tvalid;
-- Map intnal signal to port
writing_curdesc_out <= writing_curdesc and ftch_active;
writing2_curdesc_out <= writing_curdesc and ftch2_active;
-- Map port to internal signal
writing_nxtdesc <= writing_nxtdesc_in;
end implementation;
|
bsd-3-clause
|
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/rgb2dvi_v1_2/src/TMDS_Encoder.vhd
|
10
|
7863
|
-------------------------------------------------------------------------------
--
-- File: TMDS_Encoder.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI output on 7-series Xilinx FPGA
-- Date: 30 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module implements the encoding algorithm outlined in the
-- DVI 1.0 specifications and instantiates the serializer block. The 8-bit data
-- and 3 control signals are encoded and transmitted over the data channel.
-- The sDataOut_p/n ports must connect to top-level ports.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.DVI_Constants.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity TMDS_Encoder is
Port (
PixelClk : in std_logic; --Recovered TMDS clock x1 (CLKDIV)
SerialClk : in std_logic; --Recovered TMDS clock x5 (CLK)
aRst : in std_logic; --asynchronous reset; must be reset when PixelClk/SerialClk is not within spec
--Encoded parallel data
pDataOutRaw : out std_logic_vector(9 downto 0);
--Unencoded parallel data
pDataOut : in std_logic_vector(7 downto 0);
pC0 : in std_logic;
pC1 : in std_logic;
pVde : in std_logic
);
end TMDS_Encoder;
architecture Behavioral of TMDS_Encoder is
signal pDataOut_1 : std_logic_vector(7 downto 0);
signal q_m_1, q_m_xor_1, q_m_xnor_1, q_m_2: std_logic_vector(8 downto 0);
signal control_token_2, q_out_2: std_logic_vector(9 downto 0);
signal n1d_1, n1q_m_2, n0q_m_2, n1q_m_1 : unsigned(3 downto 0); --range 0-8
signal dc_bias_2, cnt_t_3, cnt_t_2 : signed(4 downto 0) := "00000"; --range -8 - +8 + sign
signal pC0_1, pC1_1, pVde_1, pC0_2, pC1_2, pVde_2 : std_logic;
signal cond_not_balanced_2, cond_balanced_2 : std_logic;
function sum_bits(u : std_logic_vector) return unsigned is
variable sum : unsigned(3 downto 0);
begin
assert u'length < 16 report "sum_bits error";
sum := to_unsigned(0,4);
for i in u'range loop
sum := sum + unsigned(u(i downto i));
end loop;
return sum;
end sum_bits;
begin
----------------------------------------------------------------------------------
-- DVI 1.0 Specs Figure 3-5
-- Pipeline stage 1, minimise transitions
----------------------------------------------------------------------------------
Stage1: process(PixelClk)
begin
if Rising_Edge(PixelClk) then
pVde_1 <= pVde;
n1d_1 <= sum_bits(pDataOut(7 downto 0));
pDataOut_1 <= pDataOut; --insert data into the pipeline;
pC0_1 <= pC0; --insert control into the pipeline;
pC1_1 <= pC1;
end if;
end process Stage1;
----------------------------------------------------------------------------------
-- Choose one of the two encoding options based on n1d_1
----------------------------------------------------------------------------------
q_m_xor_1(0) <= pDataOut_1(0);
encode1: for i in 1 to 7 generate
q_m_xor_1(i) <= q_m_xor_1(i-1) xor pDataOut_1(i);
end generate encode1;
q_m_xor_1(8) <= '1';
q_m_xnor_1(0) <= pDataOut_1(0);
encode2: for i in 1 to 7 generate
q_m_xnor_1(i) <= q_m_xnor_1(i-1) xnor pDataOut_1(i);
end generate encode2;
q_m_xnor_1(8) <= '0';
q_m_1 <= q_m_xnor_1 when n1d_1 > 4 or (n1d_1 = 4 and pDataOut_1(0) = '0') else
q_m_xor_1;
n1q_m_1 <= sum_bits(q_m_1(7 downto 0));
----------------------------------------------------------------------------------
-- Pipeline stage 2, balance DC
----------------------------------------------------------------------------------
Stage2: process(PixelClk)
begin
if Rising_Edge(PixelClk) then
n1q_m_2 <= n1q_m_1;
n0q_m_2 <= 8 - n1q_m_1;
q_m_2 <= q_m_1;
pC0_2 <= pC0_1;
pC1_2 <= pC1_1;
pVde_2 <= pVde_1;
end if;
end process Stage2;
cond_balanced_2 <= '1' when cnt_t_3 = 0 or n1q_m_2 = 4 else -- DC balanced output
'0';
cond_not_balanced_2 <= '1' when (cnt_t_3 > 0 and n1q_m_2 > 4) or -- too many 1's
(cnt_t_3 < 0 and n1q_m_2 < 4) else -- too many 0's
'0';
control_token_2 <= kCtlTkn0 when pC1_2 = '0' and pC0_2 = '0' else
kCtlTkn1 when pC1_2 = '0' and pC0_2 = '1' else
kCtlTkn2 when pC1_2 = '1' and pC0_2 = '0' else
kCtlTkn3;
q_out_2 <= control_token_2 when pVde_2 = '0' else --control period
not q_m_2(8) & q_m_2(8) & not q_m_2(7 downto 0) when cond_balanced_2 = '1' and q_m_2(8) = '0' else
not q_m_2(8) & q_m_2(8) & q_m_2(7 downto 0) when cond_balanced_2 = '1' and q_m_2(8) = '1' else
'1' & q_m_2(8) & not q_m_2(7 downto 0) when cond_not_balanced_2 = '1' else
'0' & q_m_2(8) & q_m_2(7 downto 0); --DC balanced
dc_bias_2 <= signed('0' & n0q_m_2) - signed('0' & n1q_m_2);
cnt_t_2 <= to_signed(0, cnt_t_2'length) when pVde_2 = '0' else --control period
cnt_t_3 + dc_bias_2 when cond_balanced_2 = '1' and q_m_2(8) = '0' else
cnt_t_3 - dc_bias_2 when cond_balanced_2 = '1' and q_m_2(8) = '1' else
cnt_t_3 + signed('0' & q_m_2(8 downto 8) & '0') + dc_bias_2 when cond_not_balanced_2 = '1' else
cnt_t_3 - signed('0' & not q_m_2(8 downto 8) & '0') - dc_bias_2;
----------------------------------------------------------------------------------
-- Pipeline stage 3, registered output
----------------------------------------------------------------------------------
Stage3: process(PixelClk)
begin
if Rising_Edge(PixelClk) then
cnt_t_3 <= cnt_t_2;
pDataOutRaw <= q_out_2; --encoded, ready to be serialized
end if;
end process Stage3;
end Behavioral;
|
bsd-3-clause
|
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/usb2device_v1_0/src/ULPI.vhd
|
2
|
25696
|
-------------------------------------------------------------------------------
--
-- File: ULPI.vhd
-- Author: Gherman Tudor
-- Original Project: USB Device IP on 7-series Xilinx FPGA
-- Date: 2 May 2016
--
-------------------------------------------------------------------------------
-- (c) 2016 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module handles ULPI transmissions (NOPID, PID, EXTW, REGW, EXTR, REGR)
-- and reception
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity ULPI is
Port (
Ulpi_Clk : in STD_LOGIC; --ULPI input clock. Generated by the USB PHY
reset : in STD_LOGIC; -- Reset siganl from upper layers. Resets all logic in this module
--ULPI Bus
u_Ulpi_Data : inout STD_LOGIC_VECTOR(7 downto 0);
u_Ulpi_Dir : in STD_LOGIC;
u_Ulpi_Nxt : in STD_LOGIC;
u_Ulpi_Stp : out STD_LOGIC;
u_Ulpi_Reset : out STD_LOGIC;
--Command signals for ULPI State machine
u_Send_NOOP_CMD : in STD_LOGIC;
u_Send_NOPID_CMD : in STD_LOGIC;
u_Send_PID_CMD : in STD_LOGIC;
u_Send_EXTW_CMD : in STD_LOGIC;
u_Send_REGW_CMD : in STD_LOGIC;
u_Send_EXTR_CMD : in STD_LOGIC;
u_Send_REGR_CMD : in STD_LOGIC;
u_Send_STP_CMD : in STD_LOGIC;
u_Send_Last : in STD_LOGIC;
u_Send_Err : in STD_LOGIC;
u_USB_Mode : in STD_LOGIC;
--Interface with upper layers
u_Tx_Data : in STD_LOGIC_VECTOR (7 downto 0); -- packet data to be transmitted
u_Tx_Data_En : out STD_LOGIC; -- data strobe; indicates to the upper layers when to place valid data on tx_data
u_Tx_Pid : in STD_LOGIC_VECTOR (3 downto 0); -- PID field associated with transmit packet (PID) commands
u_Tx_Regw_Data : in STD_LOGIC_VECTOR (7 downto 0); --Register data associated with the REGW, EXTW commands
u_Tx_Reg_Addr : in STD_LOGIC_VECTOR (7 downto 0); --Immediate address associated with the REGW, EXTW commands
u_Tx_Cmd_Done : out STD_LOGIC; --NOPID, NOOP, PID, EXTW, REGW, REGR, EXTR command completed, ready for next command
u_Tx_Pid_Phase_Done : out STD_LOGIC;
u_CRC16_En : out STD_LOGIC; --indicates to upper layers to consider the current byte as part of the sequence on which CRC16 is computed
u_Ulpi_Dir_Out : out STD_LOGIC;
u_Rx_Data : out STD_LOGIC_VECTOR (7 downto 0); --data received on the ULPI bus
u_Rx_Packet_Received : out STD_LOGIC; --indicates if u_Rx_Data is packet data
u_Rx_Cmd_Received : out STD_LOGIC; --indicates if u_Rx_Data is packet data
u_Rx_Register_Data : out STD_LOGIC_VECTOR (7 downto 0); --Data received in turn of REGR_CMD or EXTW_CMD
u_Rx_Register_Data_Received : out STD_LOGIC; -- indicates if u_Rx_Register_Data is valid
--UTMI+ signals
u_LineState : out STD_LOGIC_VECTOR (1 downto 0);
u_Vbus : out STD_LOGIC_VECTOR (1 downto 0);
u_RxEvent : out STD_LOGIC_VECTOR (1 downto 0);
u_RxActive : out STD_LOGIC;
u_ID : out STD_LOGIC;
u_Alt_Int : out STD_LOGIC;
state_ind : out STD_LOGIC_VECTOR(5 downto 0) --for debug purposes
);
end ULPI;
architecture Behavioral of ULPI is
constant TXCMD_NOOP : STD_LOGIC_VECTOR (7 downto 0) := "00000000";
constant TXCMD_NOPID : STD_LOGIC_VECTOR (7 downto 0) := "01000000";
constant TXCMD_PID : STD_LOGIC_VECTOR (3 downto 0) := "0100";
constant TXCMD_REGR : STD_LOGIC_VECTOR (7 downto 0) := "11101110";
constant TXCMD_REGW : STD_LOGIC_VECTOR (7 downto 0) := "10101110";
constant TXCMD_EXTR : STD_LOGIC_VECTOR (7 downto 0) := "11101111";
constant TXCMD_EXTW : STD_LOGIC_VECTOR (7 downto 0) := "10101111";
type state_type is (IDLE, SEND_STP, REGR_END, FSM_ERROR, ABORT, RECEIVE, PID_CMD, PID_DATA, PID_DATA_LAST, PID_STP, PID_DATA_ERR, PID_WAIT_J1, PID_WAIT_J2, PID_WAIT_FSEOP1, PID_WAIT_FSEOP2, PID_WAIT_HSEOP1, PID_WAIT_HSEOP2, PID_WAIT_EOP, NOPID_CMD, NOPID_DATA, NOPID_DATA_LAST, NOPID_STP, REGR_CMD1, REGR_CMD2, REGR_TURN, REGR_DATA, REGW_CMD, REGW_DATA, REGW_STP, EXTW_CMD, EXTW_ADDR, EXTW_DATA, EXTW_STP, EXTR_CMD1, EXTR_CMD2, EXTR_ADDR, EXTR_TURN, EXTR_DATA, EXTR_STP);
signal u_Ulpi_State, u_Ulpi_Next_State : state_type;
signal u_Ulpi_Dir_q : STD_LOGIC;
signal u_Ulpi_Dir_qq : STD_LOGIC;
signal u_Ulpi_Stp_Fsm : STD_LOGIC;
signal u_Txmux_Out_Data : STD_LOGIC_VECTOR (7 downto 0);
signal u_Txmux_Out_Data_q : STD_LOGIC_VECTOR (7 downto 0);
signal t_data_debug : STD_LOGIC_VECTOR (7 downto 0);
signal u_Txcmd_Code : STD_LOGIC_VECTOR (7 downto 0);
signal u_Txmux_Ctrl_8b_Commands : STD_LOGIC; --used to select TX_CMDs made up of 8 constant bits : NOPID, EXTW, EXTR on ULPI bus
signal u_Txmux_Ctrl_Extreg_Addr : STD_LOGIC; --used to select the extended register address on the ULPI bus
signal u_Txmux_Ctrl_Register_Commands : STD_LOGIC; --used to select REGW and REGR commands on the ULPI bus
signal u_Txmux_Ctrl_Data : STD_LOGIC; --used to select data bytes on ULPI bus
signal u_Txmux_Ctrl_Reg_Data : STD_LOGIC; --used to select the register data to be written on the ULPI bus
signal u_Txmux_Ctrl_PID_Command : STD_LOGIC; --used to select PID commands : 4 constant bits (0100) + 4PID bits on ULPI bus
--signal idle_state : STD_LOGIC;
signal u_Receive_Data : STD_LOGIC_VECTOR (7 downto 0);
signal u_Rx_CMD : STD_LOGIC;
signal u_Rx_CMD_Fsm : STD_LOGIC;
signal u_Reg_Data_Latch: STD_LOGIC;
signal u_Packet_Received: STD_LOGIC;
signal u_Rxdemux_Register_Data : STD_LOGIC_VECTOR (7 downto 0);
signal u_Receive_Data_q : STD_LOGIC_VECTOR (7 downto 0);
signal u_Rxdemux_LineState : STD_LOGIC_VECTOR (1 downto 0);
signal u_Rxdemux_Vbus : STD_LOGIC_VECTOR (1 downto 0);
signal u_Rxdemux_RxEvent : STD_LOGIC_VECTOR (1 downto 0);
signal u_Rxdemux_RxEvent_q : STD_LOGIC_VECTOR (1 downto 0);
signal u_Rxdemux_ID : STD_LOGIC;
signal u_Rxdemux_Alt_Int : STD_LOGIC;
signal state_ind_fsm : STD_LOGIC_VECTOR(5 downto 0);
signal debug_clk : STD_LOGIC := '0';
--attribute mark_debug : string;
--attribute keep : string;
--attribute mark_debug of state_ind : signal is "true";
--attribute keep of state_ind : signal is "true";
--attribute mark_debug of u_Ulpi_Dir : signal is "true";
--attribute keep of u_Ulpi_Dir : signal is "true";
--attribute mark_debug of u_Ulpi_Nxt : signal is "true";
--attribute keep of u_Ulpi_Nxt : signal is "true";
--attribute mark_debug of u_Ulpi_Stp : signal is "true";
--attribute keep of u_Ulpi_Stp : signal is "true";
--attribute mark_debug of u_Receive_Data_q : signal is "true";
--attribute keep of u_Receive_Data_q : signal is "true";
--attribute mark_debug of u_Txmux_Out_Data_q : signal is "true";
--attribute keep of u_Txmux_Out_Data_q : signal is "true";
--attribute mark_debug of u_Ulpi_Stp_Fsm : signal is "true";
--attribute keep of u_Ulpi_Stp_Fsm : signal is "true";
--attribute mark_debug of debug_clk : signal is "true";
--attribute keep of debug_clk : signal is "true";
begin
u_Ulpi_Reset <= reset;
u_Ulpi_Dir_Out <= u_Ulpi_Dir_q;
u_Rx_Register_Data_Received <= u_Reg_Data_Latch;
u_Rx_Data <= u_Receive_Data_q;
u_Rx_Register_Data <= u_Rxdemux_Register_Data;
--rx_en <= rx_data_en;
u_Rxdemux_LineState <= u_Receive_Data(1 downto 0);
u_Rxdemux_Vbus <= u_Receive_Data(3 downto 2);
u_Rxdemux_RxEvent <= u_Receive_Data(5 downto 4);
u_RxEvent <= u_Rxdemux_RxEvent_q;
u_Rxdemux_ID <= u_Receive_Data(6);
u_Rxdemux_Alt_Int <= u_Receive_Data(7);
bidirbuf: for i in 0 to 7 generate
IOBUF_inst : IOBUF
generic map (
DRIVE => 12,
IOSTANDARD => "DEFAULT",
SLEW => "SLOW")
port map (
O => u_Receive_Data(i), -- Buffer output
IO => u_Ulpi_Data(i), -- Buffer inout port (connect directly to top-level port)
I => u_Txmux_Out_Data_q(i), -- Buffer input
T => u_Ulpi_Dir_q -- 3-state enable input, high=input, low=output
);
end generate;
--decide if rx_data carries data/RXCMD
u_Packet_Received <= u_Ulpi_Dir and u_Ulpi_Nxt;
u_Rx_CMD <= (u_Ulpi_Dir_q and u_Ulpi_Dir) and (not u_Ulpi_Nxt);
RXACTIVE_PROC: process (Ulpi_Clk, u_Packet_Received, u_Rxdemux_RxEvent_q, u_Ulpi_Dir_q)
begin
if (Ulpi_Clk' event and Ulpi_Clk = '1') then
if (reset = '0' or u_Ulpi_Dir = '0') then
u_RxActive <= '0';
elsif (u_Ulpi_Dir_q = '1' and u_Packet_Received = '1') then
u_RxActive <= '1';
end if;
end if;
end process;
STATE_CHANGE: process (Ulpi_Clk) --For debug purposes
begin
if (Ulpi_Clk' event and Ulpi_Clk = '1') then
debug_clk <= not debug_clk;
end if;
end process;
--ULPI output signals are registered
DATA_STP_Q_PROC: process (Ulpi_Clk)
begin
if (Ulpi_Clk' event and Ulpi_Clk = '1') then
if (reset = '0') then
u_Txmux_Out_Data_q <= (others => '0');
u_Ulpi_Stp <= '0';
else
u_Ulpi_Stp <= u_Ulpi_Stp_Fsm;
u_Txmux_Out_Data_q <= u_Txmux_Out_Data;
end if;
end if;
end process;
--register receive data/control signals (outputs to upper layers)
RX_Q_PROC: process(Ulpi_Clk)
begin
if(Ulpi_Clk' event and Ulpi_Clk = '1') then
if (reset = '0') then
u_Rx_Cmd_Received <= '0';
u_Ulpi_Dir_q <= '0';
u_Ulpi_Dir_qq <= '0';
u_Rx_Packet_Received <= '0';
u_Receive_Data_q <= (others => '0');
u_LineState <= (others => '0');
u_Vbus <= (others => '0');
u_Rxdemux_RxEvent_q <= (others => '0');
u_ID <= '0';
u_Alt_Int <= '0';
u_Rxdemux_Register_Data <= (others => '0');
t_data_debug <= (others => '0');
else
t_data_debug <= u_Txmux_Out_Data;
u_Rx_Cmd_Received <= u_Rx_CMD;
u_Ulpi_Dir_q <= u_Ulpi_Dir;
u_Ulpi_Dir_qq <= u_Ulpi_Dir_q;
u_Rx_Packet_Received <= u_Packet_Received;
u_Receive_Data_q <= u_Receive_Data;
if((u_Rx_CMD = '1') and (u_Rx_CMD_Fsm = '1')) then
u_LineState <= u_Rxdemux_LineState;
u_Vbus <= u_Rxdemux_Vbus;
u_Rxdemux_RxEvent_q <= u_Rxdemux_RxEvent;
u_ID <= u_Rxdemux_ID;
u_Alt_Int <= u_Rxdemux_Alt_Int;
elsif ( u_Reg_Data_Latch = '1') then
u_Rxdemux_Register_Data <= u_Receive_Data;
end if;
end if;
end if;
end process;
--Combinational process that selects the byte to be placed on the ULPI data bus
--It can be a TX Command, Packet Data, PID, Register Address, Register Data
TXMUX_PROC: process(Ulpi_Clk, u_Txmux_Ctrl_Data, u_Txmux_Ctrl_Extreg_Addr, u_Txmux_Ctrl_PID_Command, u_Txmux_Ctrl_8b_Commands, u_Txmux_Ctrl_Register_Commands, u_Tx_Data, u_Tx_Pid, u_Txcmd_Code, u_Tx_Reg_Addr, u_Txmux_Ctrl_Reg_Data, u_Tx_Regw_Data)
begin
if(u_Txmux_Ctrl_Data = '1') then
u_Txmux_Out_Data <= u_Tx_Data;
elsif (u_Txmux_Ctrl_PID_Command = '1') then
u_Txmux_Out_Data(3 downto 0) <= u_Tx_Pid;
u_Txmux_Out_Data(7 downto 4) <= TXCMD_PID;
elsif (u_Txmux_Ctrl_8b_Commands = '1') then
u_Txmux_Out_Data <= u_Txcmd_Code;
elsif (u_Txmux_Ctrl_Register_Commands = '1') then
u_Txmux_Out_Data(7 downto 6) <= u_Txcmd_Code(7 downto 6);
u_Txmux_Out_Data(5 downto 0) <= u_Tx_Reg_Addr(5 downto 0);
elsif (u_Txmux_Ctrl_Extreg_Addr = '1') then
u_Txmux_Out_Data <= u_Tx_Reg_Addr;
elsif (u_Txmux_Ctrl_Reg_Data = '1') then
u_Txmux_Out_Data <= u_Tx_Regw_Data;
else
u_Txmux_Out_Data <= (others => '0');
end if;
end process;
-- ULPI State Machine. Implements the framework required for transmit commands( NOPID,
-- PID, EXTW, REGW, EXTR, REGR) and decodes received data
SYNC_PROC: process (Ulpi_Clk)
begin
if (Ulpi_Clk' event and Ulpi_Clk = '1') then
if (reset = '0') then
u_Ulpi_State <= IDLE;
state_ind <= (others => '0');
else
u_Ulpi_State <= u_Ulpi_Next_State;
state_ind <= state_ind_fsm;
end if;
end if;
end process;
NEXT_STATE_DECODE: process (u_Ulpi_State, u_Ulpi_Dir_q, u_Receive_Data_q ,u_Rx_CMD, u_Send_Last, u_Send_Err, u_Ulpi_Dir, u_Ulpi_Dir_qq, u_USB_Mode, u_Receive_Data, u_Ulpi_Nxt, u_Send_NOPID_CMD, u_Send_PID_CMD,u_Send_REGW_CMD,u_Send_EXTW_CMD,u_Send_REGR_CMD,u_Send_EXTR_CMD,u_Send_NOOP_CMD, u_Send_STP_CMD)
begin
--declare default state for next_state to avoid latches
u_Ulpi_Next_State <= u_Ulpi_State;
state_ind_fsm <= "000000";
u_Ulpi_Stp_Fsm <= '0';
u_Txmux_Ctrl_Data <= '0';
u_Txmux_Ctrl_Reg_Data <= '0';
u_Txmux_Ctrl_8b_Commands <= '0';
u_Txmux_Ctrl_Register_Commands <= '0';
u_Tx_Data_En <= '0';
u_Txmux_Ctrl_PID_Command <= '0';
u_Txcmd_Code <= (others => '0');
u_Rx_CMD_Fsm <= '0';
u_Tx_Cmd_Done <= '0';
u_CRC16_En <= '0';
u_Txmux_Ctrl_Extreg_Addr <= '0';
u_Reg_Data_Latch <= '0';
u_Tx_Pid_Phase_Done <= '0';
case (u_Ulpi_State) is
when IDLE =>
state_ind_fsm <= "000000";
u_Txmux_Ctrl_8b_Commands <= '1';
u_Txcmd_Code <= (others => '0');
if ( u_Ulpi_Dir = '0') then
if(u_Send_NOPID_CMD = '1') then
u_Ulpi_Next_State <= NOPID_CMD;
elsif (u_Send_PID_CMD = '1') then
u_Ulpi_Next_State <= PID_CMD;
elsif (u_Send_REGW_CMD = '1') then
u_Ulpi_Next_State <= REGW_CMD;
elsif (u_Send_EXTW_CMD = '1') then
u_Ulpi_Next_State <= EXTW_CMD;
elsif (u_Send_REGR_CMD = '1') then
u_Ulpi_Next_State <= REGR_CMD1;
elsif (u_Send_EXTR_CMD = '1') then
u_Ulpi_Next_State <= EXTR_CMD1;
elsif (u_Send_NOOP_CMD = '1') then
u_Ulpi_Next_State <= IDLE;
else
u_Ulpi_Next_State <= IDLE;
end if;
else
u_Ulpi_Next_State <= RECEIVE;
end if;
--SEND PID_CMD -- No support for packet abort
when PID_CMD =>
state_ind_fsm <= "000001";
u_Txmux_Ctrl_PID_Command <= '1';
if (u_Ulpi_Nxt = '1') then
u_Txmux_Ctrl_PID_Command <= '0';
u_Txmux_Ctrl_Data <= '1';
u_Tx_Data_En <= '1';
u_CRC16_En <= '1';
if (u_Send_Last = '1') then
u_Ulpi_Stp_Fsm <= '1';
u_Ulpi_Next_State <= PID_STP;
else
u_Tx_Pid_Phase_Done <= '1';
u_Ulpi_Next_State <= PID_DATA;
end if;
end if;
when PID_DATA =>
state_ind_fsm <= "000010";
u_Txmux_Ctrl_Data <= '1';
if(u_Ulpi_Nxt = '1') then
u_CRC16_En <= '1';
u_Tx_Data_En <= '1';
if (u_Send_Last = '1') then
if (u_Send_Err = '0') then
u_Ulpi_Next_State <= PID_DATA_LAST;
else
u_Ulpi_Next_State <= PID_DATA_ERR;
end if;
end if;
else
u_Tx_Data_En <= '0';
end if;
when PID_DATA_LAST =>
state_ind_fsm <= "000011";
u_Txmux_Ctrl_Data <= '1';
if(u_Ulpi_Nxt = '1') then
u_Txmux_Ctrl_Data <= '0';
u_Ulpi_Stp_Fsm <= '1';
u_Ulpi_Next_State <= PID_STP;
end if;
when PID_STP =>
state_ind_fsm <= "000100";
u_Ulpi_Next_State <= PID_WAIT_EOP;
when PID_WAIT_EOP =>
state_ind_fsm <= "000101";
--if(ulpi_dir = '1') then
if(u_USB_Mode = '1') then
u_Ulpi_Next_State <= PID_WAIT_HSEOP1;
else
u_Ulpi_Next_State <= PID_WAIT_FSEOP1;
end if;
--end if;
when PID_WAIT_HSEOP1 =>
if (u_Ulpi_Dir = '1') then
u_Ulpi_Next_State <= PID_WAIT_HSEOP2;
end if;
when PID_WAIT_HSEOP2 =>
state_ind_fsm <= "000110";
if(u_Ulpi_Dir = '1') then
u_Rx_CMD_Fsm <= '1';
if(u_Receive_Data(1 downto 0) = "00") then
u_Tx_Cmd_Done <= '1';
u_Ulpi_Next_State <= IDLE;
else
u_Ulpi_Next_State <= PID_WAIT_HSEOP1;
end if;
end if;
when PID_WAIT_FSEOP1 =>
state_ind_fsm <= "000111";
if(u_Ulpi_Dir = '1') then
u_Rx_CMD_Fsm <= '1';
u_Ulpi_Next_State <= PID_WAIT_FSEOP2;
end if;
when PID_WAIT_FSEOP2 =>
state_ind_fsm <= "001000";
if(u_Ulpi_Dir_qq = '1') then
u_Rx_CMD_Fsm <= '1';
if(u_Receive_Data_q(1 downto 0) = "00") then
u_Ulpi_Next_State <= PID_WAIT_J1;
else
u_Ulpi_Next_State <= FSM_ERROR;
end if;
end if;
when PID_WAIT_J1 =>
state_ind_fsm <= "001001";
if (u_Ulpi_Dir = '1') then
u_Rx_CMD_Fsm <= '1';
u_Ulpi_Next_State <= PID_WAIT_J2;
end if;
when PID_WAIT_J2 =>
state_ind_fsm <= "001010";
if(u_Receive_Data_q(1 downto 0) = "01") then
u_Tx_Cmd_Done <= '1';
u_Ulpi_Next_State <= IDLE;
else
u_Ulpi_Next_State <= FSM_ERROR;
end if;
when PID_DATA_ERR =>
state_ind_fsm <= "001011";
u_Tx_Cmd_Done <= '1';
u_Ulpi_Stp_Fsm <= '1';
u_Txcmd_Code <= (others => '1');
u_Txmux_Ctrl_8b_Commands <= '1';
u_Ulpi_Next_State <= IDLE; --The link must wait for an RX_CMD indicating a SE0 to J transition before transmitting another packet : Not implemented
--SEND NOPID
when NOPID_CMD =>
if (u_Ulpi_Dir = '0') then
state_ind_fsm <= "001100";
u_Txcmd_Code <= TXCMD_NOPID;
u_Txmux_Ctrl_8b_Commands <= '1';
if (u_Ulpi_Nxt = '1') then
u_Txmux_Ctrl_8b_Commands <= '0';
u_Txmux_Ctrl_Data <= '1';
u_Ulpi_Next_State <= NOPID_DATA;
end if;
else
u_Ulpi_Next_State <= IDLE;
end if;
when NOPID_DATA =>
if (u_Ulpi_Dir = '0') then
state_ind_fsm <= "001101";
u_Txmux_Ctrl_Data <= '1';
if (u_Ulpi_Nxt = '1') then
if (u_Send_Last = '1') then
u_Ulpi_Next_State <= NOPID_DATA_LAST;
end if;
end if;
else
u_Ulpi_Next_State <= ABORT;
end if;
when NOPID_DATA_LAST =>
if (u_Ulpi_Dir = '0') then
state_ind_fsm <= "001110";
u_Txmux_Ctrl_Data <= '1';
u_Ulpi_Stp_Fsm <= '1';
u_Ulpi_Next_State <= NOPID_STP;
else
u_Ulpi_Next_State <= ABORT;
end if;
when NOPID_STP =>
if (u_Ulpi_Dir = '0') then
state_ind_fsm <= "001111";
u_Tx_Cmd_Done <= '1';
u_Ulpi_Next_State <= IDLE;
else
u_Ulpi_Next_State <= ABORT;
end if;
--SEND REGW
when REGW_CMD =>
state_ind_fsm <= "010000";
u_Txcmd_Code <= TXCMD_REGW;
u_Txmux_Ctrl_Register_Commands <= '1';
if (u_Ulpi_Dir = '0') then
if (u_Ulpi_Nxt = '1') then
u_Txmux_Ctrl_Register_Commands <= '0';
u_Txmux_Ctrl_Reg_Data <= '1';
u_Ulpi_Next_State <= REGW_DATA;
end if;
else
u_Ulpi_Next_State <= RECEIVE;
end if;
when REGW_DATA =>
state_ind_fsm <= "010001";
if (u_Ulpi_Dir = '0') then
if (u_Ulpi_Nxt = '1') then
u_Ulpi_Stp_Fsm <= '1';
u_Ulpi_Next_State <= REGW_STP;
end if;
else
u_Ulpi_Next_State <= RECEIVE;
end if;
when REGW_STP =>
state_ind_fsm <= "010010";
u_Tx_Cmd_Done <= '1';
u_Ulpi_Next_State <= IDLE;
--SEND EXTW Not Working!
when EXTW_CMD =>
state_ind_fsm <= "010011";
u_Txcmd_Code <= TXCMD_EXTW;
u_Txmux_Ctrl_8b_Commands <= '1';
if (u_Ulpi_Dir = '0') then
if(u_Ulpi_Nxt = '1') then
u_Ulpi_Next_State <= EXTW_ADDR;
end if;
else
u_Ulpi_Next_State <= ABORT;
end if;
when EXTW_ADDR =>
state_ind_fsm <= "010100";
u_Txmux_Ctrl_Extreg_Addr <= '1';
if (u_Ulpi_Dir = '0') then
u_Ulpi_Next_State <= EXTW_DATA;
else
u_Ulpi_Next_State <= ABORT;
end if;
when EXTW_DATA =>
state_ind_fsm <= "010101";
if (u_Ulpi_Dir = '0') then
u_Txmux_Ctrl_Reg_Data <= '1';
u_Ulpi_Next_State <= EXTW_STP;
else
u_Ulpi_Next_State <= ABORT;
end if;
when EXTW_STP =>
state_ind_fsm <= "010110";
if (u_Ulpi_Dir = '0') then
u_Tx_Cmd_Done <= '1';
u_Ulpi_Next_State <= IDLE;
u_Ulpi_Stp_Fsm <= '1';
else
u_Ulpi_Next_State <= ABORT;
end if;
--SEND REGR
when REGR_CMD1 =>
state_ind_fsm <= "010111";
u_Txcmd_Code <= TXCMD_REGR;
u_Txmux_Ctrl_Register_Commands <= '1';
if (u_Ulpi_Dir = '0') then
if(u_Ulpi_Nxt = '1') then
u_Txmux_Ctrl_Register_Commands <= '0';
u_Ulpi_Next_State <= REGR_TURN;
end if;
else
u_Ulpi_Next_State <= RECEIVE;
end if;
when REGR_TURN =>
state_ind_fsm <= "011000";
if(u_Ulpi_Dir = '1') then
if(u_Ulpi_Nxt = '0') then
u_Reg_Data_Latch <= '1';
u_Ulpi_Next_State <= REGR_DATA;
else
u_Ulpi_Next_State <= RECEIVE;
end if;
end if;
when REGR_DATA =>
state_ind_fsm <= "011010";
if(u_Ulpi_Dir = '0') then
u_Ulpi_Next_State <= REGR_END;
else
u_Ulpi_Next_State <= RECEIVE;
end if;
when REGR_END =>
u_Tx_Cmd_Done <= '1';
if (u_Ulpi_Dir = '1') then
u_Ulpi_Next_State <= RECEIVE;
else
u_Ulpi_Next_State <= IDLE;
end if;
--SEND EXTR Not Working!
when EXTR_CMD1 =>
state_ind_fsm <= "011011";
u_Txmux_Ctrl_8b_Commands <= '1';
u_Txcmd_Code <= TXCMD_EXTR;
if (u_Ulpi_Dir = '0') then
if(u_Ulpi_Nxt = '1') then
u_Ulpi_Next_State <= EXTR_ADDR;
end if;
else
u_Ulpi_Next_State <= RECEIVE;
end if;
when EXTR_ADDR =>
state_ind_fsm <= "011101";
u_Txmux_Ctrl_Extreg_Addr <= '1';
if (u_Ulpi_Dir = '0') then
u_Ulpi_Next_State <= EXTR_TURN;
else
u_Ulpi_Next_State <= RECEIVE;
end if;
when EXTR_TURN =>
state_ind_fsm <= "011110";
if (u_Ulpi_Dir = '1') then
u_Ulpi_Next_State <= EXTR_DATA;
end if;
when EXTR_DATA =>
state_ind_fsm <= "011111";
u_Tx_Cmd_Done <= '1';
u_Reg_Data_Latch <= '1';
if (u_Ulpi_Nxt = '0') then
if (u_Ulpi_Dir = '1') then
u_Ulpi_Next_State <= RECEIVE;
else
u_Ulpi_Next_State <= IDLE;
end if;
end if;
--ABORT
when ABORT =>
state_ind_fsm <= "100000";
u_Ulpi_Next_State <= IDLE;
when SEND_STP =>
state_ind_fsm <= "100010";
u_Ulpi_Stp_Fsm <= '1';
if (u_Ulpi_Dir_q = '0') then
u_Ulpi_Next_State <= IDLE;
end if;
--RECEIVE
when RECEIVE =>
state_ind_fsm <= "100001";
if(u_Ulpi_Dir = '1') then
if (u_Send_STP_CMD = '1') then
u_Ulpi_Stp_Fsm <= '1';
u_Ulpi_Next_State <= SEND_STP;
elsif(u_Rx_CMD = '1') then
u_Rx_CMD_Fsm <= '1';
end if;
else
u_Ulpi_Next_State <= IDLE;
end if;
when others =>
u_Ulpi_Next_State <= IDLE;
end case;
end process;
end Behavioral;
|
bsd-3-clause
|
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/axi_i2s_adi_1.2/hdl/adi_common/axi_streaming_dma_tx_fifo.vhd
|
7
|
1587
|
library ieee;
use ieee.std_logic_1164.all;
library adi_common_v1_00_a;
use adi_common_v1_00_a.dma_fifo;
entity axi_streaming_dma_tx_fifo is
generic (
RAM_ADDR_WIDTH : integer := 3;
FIFO_DWIDTH : integer := 32
);
port (
clk : in std_logic;
resetn : in std_logic;
fifo_reset : in std_logic;
-- Enable DMA interface
enable : in Boolean;
-- Write port
S_AXIS_ACLK : in std_logic;
S_AXIS_TREADY : out std_logic;
S_AXIS_TDATA : in std_logic_vector(FIFO_DWIDTH-1 downto 0);
S_AXIS_TLAST : in std_logic;
S_AXIS_TVALID : in std_logic;
-- Read port
out_stb : out std_logic;
out_ack : in std_logic;
out_data : out std_logic_vector(FIFO_DWIDTH-1 downto 0)
);
end;
architecture imp of axi_streaming_dma_tx_fifo is
signal in_ack : std_logic;
signal drain_dma : Boolean;
begin
fifo: entity dma_fifo
generic map (
RAM_ADDR_WIDTH => RAM_ADDR_WIDTH,
FIFO_DWIDTH => FIFO_DWIDTH
)
port map (
clk => clk,
resetn => resetn,
fifo_reset => fifo_reset,
in_stb => S_AXIS_TVALID,
in_ack => in_ack,
in_data => S_AXIS_TDATA,
out_stb => out_stb,
out_ack => out_ack,
out_data => out_data
);
drain_process: process (S_AXIS_ACLK) is
variable enable_d1 : Boolean;
begin
if rising_edge(S_AXIS_ACLK) then
if resetn = '0' then
drain_dma <= False;
else
if S_AXIS_TLAST = '1' then
drain_dma <= False;
elsif enable_d1 and enable then
drain_dma <= True;
end if;
enable_d1 := enable;
end if;
end if;
end process;
S_AXIS_TREADY <= '1' when in_ack = '1' or drain_dma else '0';
end;
|
bsd-3-clause
|
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/Pmods/PmodMTDS_v1_0/ipshared/xilinx.com/axi_quad_spi_v3_2/hdl/src/vhdl/qspi_occupancy_reg.vhd
|
3
|
7186
|
-------------------------------------------------------------------------------
-- qspi_occupancy_reg.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- ** (c) Copyright [2010] - [2012] Xilinx, Inc. All rights reserved.*
-- ** *
-- ** This file contains confidential and proprietary information *
-- ** of Xilinx, Inc. and is protected under U.S. and *
-- ** international copyright and other intellectual property *
-- ** laws. *
-- ** *
-- ** DISCLAIMER *
-- ** This disclaimer is not a license and does not grant any *
-- ** rights to the materials distributed herewith. Except as *
-- ** otherwise provided in a valid license issued to you by *
-- ** Xilinx, and to the maximum extent permitted by applicable *
-- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- ** including negligence, or under any other theory of *
-- ** liability) for any loss or damage of any kind or nature *
-- ** related to, arising under or in connection with these *
-- ** materials, including for any direct, or any indirect, *
-- ** special, incidental, or consequential loss or damage *
-- ** (including loss of data, profits, goodwill, or any type of *
-- ** loss or damage suffered as a result of any action brought *
-- ** by a third party) even if such damage or loss was *
-- ** reasonably foreseeable or Xilinx had been advised of the *
-- ** possibility of the same. *
-- ** *
-- ** CRITICAL APPLICATIONS *
-- ** Xilinx products are not designed or intended to be fail- *
-- ** safe, or for use in any application requiring fail-safe *
-- ** performance, such as life-support or safety devices or *
-- ** systems, Class III medical devices, nuclear facilities, *
-- ** applications related to the deployment of airbags, or any *
-- ** other applications that could lead to death, personal *
-- ** injury, or severe property or environmental damage *
-- ** (individually and collectively, "Critical *
-- ** Applications"). Customer assumes the sole risk and *
-- ** liability of any use of Xilinx products in Critical *
-- ** Applications, subject only to applicable laws and *
-- ** regulations governing limitations on product liability. *
-- ** *
-- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename: qspi_occupancy_reg.vhd
-- Version: v3.0
-- Description: Serial Peripheral Interface (SPI) Module for interfacing
-- with a 32-bit AXI4 Bus.Defines logic for occupancy regist
-- -er.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_DBUS_WIDTH -- Width of the slave data bus
-- C_OCCUPANCY_NUM_BITS -- Number of bits in occupancy count
-- C_NUM_BITS_REG -- Width of SPI registers
-- C_NUM_TRANSFER_BITS -- SPI Serial transfer width.
-- Can be 8, 16 or 32 bit wide
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- SYSTEM
-- Bus2IP_Clk -- Bus to IP clock
-- Reset -- Reset Signal
-- SLAVE ATTACHMENT INTERFACE
--===========================
-- Bus2IP_OCC_REG_RdCE -- Read CE for occupancy register
-- SPIXfer_done -- SPI transfer done flag
-- FIFO INTERFACE
-- IP2Reg_OCC_Data -- Occupancy data read from FIFO
-- IP2Bus_OCC_REG_Data -- Data to be send on the bus
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity Declaration
-------------------------------------------------------------------------------
entity qspi_occupancy_reg is
generic
(
C_OCCUPANCY_NUM_BITS: integer-- --Number of bits in occupancy count
);
port
(
-- Slave attachment ports
Bus2IP_OCC_REG_RdCE : in std_logic;
IP2Reg_OCC_Data : in std_logic_vector(0 to (C_OCCUPANCY_NUM_BITS-1));
IP2Bus_OCC_REG_Data : out std_logic_vector(0 to (C_OCCUPANCY_NUM_BITS-1))
);
end qspi_occupancy_reg;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture imp of qspi_occupancy_reg is
-------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-- Signal Declarations
----------------------
begin
-----
-- OCCUPANCY_REG_RD_GENERATE : Occupancy Register Read Generate
-------------------------------
OCCUPANCY_REG_RD_GENERATE: for j in 0 to C_OCCUPANCY_NUM_BITS-1 generate
begin
IP2Bus_OCC_REG_Data(j) <= IP2Reg_OCC_Data(C_OCCUPANCY_NUM_BITS-1-j) and
Bus2IP_OCC_REG_RdCE;
end generate OCCUPANCY_REG_RD_GENERATE;
end imp;
--------------------------------------------------------------------------------
|
bsd-3-clause
|
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/usb2device_v1_0/src/axi_dma_0/axi_sg_v4_1_2/hdl/src/vhdl/axi_sg_scc_wr.vhd
|
13
|
44376
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_scc_wr.vhd
--
-- Description:
-- This file implements the DataMover Lite Master Simple Command Calculator (SCC).
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_sg_scc_wr is
generic (
C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5;
-- Sets the width of the LS address bus used for
-- Muxing/Demuxing data to/from a wider AXI4 data bus
C_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Sets the width of the AXi Address Channel
C_STREAM_DWIDTH : Integer range 8 to 64 := 32;
-- Sets the width of the Native Data width that
-- is being supported by the PCC
C_MAX_BURST_LEN : Integer range 16 to 64 := 16;
-- Indicates the max allowed burst length to use for
-- AXI4 transfer calculations
C_CMD_WIDTH : Integer := 68;
-- Sets the width of the input command port
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Sets the width of the Tag field in the input command
C_ENABLE_EXTRA_FIELD : Integer range 0 to 1 := 1
);
port (
-- Clock and Reset inputs -------------------------------------
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
---------------------------------------------------------------
-- Command Input Interface ---------------------------------------------------------
--
cmd2mstr_command : in std_logic_vector(C_CMD_WIDTH-1 downto 0); --
-- The next command value available from the Command FIFO/Register --
--
cache2mstr_command : in std_logic_vector(7 downto 0); --
-- The next command value available from the Command FIFO/Register --
--
cmd2mstr_cmd_valid : in std_logic; --
-- Handshake bit indicating if the Command FIFO/Register has at leasdt 1 entry --
--
mst2cmd_cmd_ready : out std_logic; --
-- Handshake bit indicating the Command Calculator is ready to accept --
-- another command --
------------------------------------------------------------------------------------
-- Address Channel Controller Interface --------------------------------------------
--
mstr2addr_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2addr_addr : out std_logic_vector(C_ADDR_WIDTH-1 downto 0); --
-- The next command address to put on the AXI MMap ADDR --
--
mstr2addr_len : out std_logic_vector(7 downto 0); --
-- The next command length to put on the AXI MMap LEN --
--
mstr2addr_size : out std_logic_vector(2 downto 0); --
-- The next command size to put on the AXI MMap SIZE --
--
mstr2addr_burst : out std_logic_vector(1 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_cache : out std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_user : out std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_cmd_cmplt : out std_logic; --
-- The indication to the Address Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2addr_calc_error : out std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calcualtion error --
--
mstr2addr_cmd_valid : out std_logic; --
-- The next command valid indication to the Address Channel --
-- Controller for the AXI MMap --
--
addr2mstr_cmd_ready : In std_logic; --
-- Indication from the Address Channel Controller that the --
-- command is being accepted --
------------------------------------------------------------------------------------
-- Data Channel Controller Interface ----------------------------------------------
--
mstr2data_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2data_saddr_lsb : out std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); --
-- The next command start address LSbs to use for the read data --
-- mux (only used if Stream data width is 8 or 16 bits). --
--
mstr2data_len : out std_logic_vector(7 downto 0); --
-- The LEN value output to the Address Channel --
--
mstr2data_strt_strb : out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The starting strobe value to use for the data transfer --
--
mstr2data_last_strb : out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The endiing (LAST) strobe value to use for the data transfer --
--
mstr2data_sof : out std_logic; --
-- The starting tranfer of a sequence of transfers --
--
mstr2data_eof : out std_logic; --
-- The endiing tranfer of a sequence of parent transfer commands --
--
mstr2data_calc_error : out std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2data_cmd_cmplt : out std_logic; --
-- The indication to the Data Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2data_cmd_valid : out std_logic; --
-- The next command valid indication to the Data Channel --
-- Controller for the AXI MMap --
--
data2mstr_cmd_ready : In std_logic ; --
-- Indication from the Data Channel Controller that the --
-- command is being accepted on the AXI Address --
-- Channel --
--
calc_error : Out std_logic --
-- Indication from the Command Calculator that a calculation --
-- error has occured. --
------------------------------------------------------------------------------------
);
end entity axi_sg_scc_wr;
architecture implementation of axi_sg_scc_wr is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_slice_width
--
-- Function Description:
-- Calculates the bits to rip from the Command BTT field to calculate
-- the LEN value output to the AXI Address Channel.
--
-------------------------------------------------------------------
function funct_get_slice_width (max_burst_len : integer) return integer is
Variable temp_slice_width : Integer := 0;
begin
case max_burst_len is
-- coverage off
when 64 =>
temp_slice_width := 7;
when 32 =>
temp_slice_width := 6;
when others => -- assume 16 dbeats is max LEN
temp_slice_width := 5;
-- coverage on
end case;
Return (temp_slice_width);
end function funct_get_slice_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_residue_width
--
-- Function Description:
-- Calculates the number of Least significant bits of the BTT field
-- that are unused for the LEN calculation
--
-------------------------------------------------------------------
function funct_get_btt_ls_unused (transfer_width : integer) return integer is
Variable temp_btt_ls_unused : Integer := 0; -- 8-bit stream
begin
case transfer_width is
-- coverage off
when 64 =>
temp_btt_ls_unused := 3;
-- coverage on
when 32 =>
temp_btt_ls_unused := 2;
-- coverage off
when 16 =>
temp_btt_ls_unused := 1;
when others => -- assume 8-bit transfers
temp_btt_ls_unused := 0;
-- coverage on
end case;
Return (temp_btt_ls_unused);
end function funct_get_btt_ls_unused;
-- Constant Declarations ----------------------------------------
Constant BASE_CMD_WIDTH : integer := 32; -- Bit Width of Command LS (no address)
Constant CMD_TYPE_INDEX : integer := 23;
Constant CMD_ADDR_LS_INDEX : integer := BASE_CMD_WIDTH;
Constant CMD_ADDR_MS_INDEX : integer := (C_ADDR_WIDTH+BASE_CMD_WIDTH)-1;
Constant CMD_TAG_WIDTH : integer := C_TAG_WIDTH;
Constant CMD_TAG_LS_INDEX : integer := C_ADDR_WIDTH+BASE_CMD_WIDTH;
Constant CMD_TAG_MS_INDEX : integer := (CMD_TAG_LS_INDEX+CMD_TAG_WIDTH)-1;
Constant AXI_BURST_FIXED : std_logic_vector(1 downto 0) := "00";
Constant AXI_BURST_INCR : std_logic_vector(1 downto 0) := "01";
Constant AXI_BURST_WRAP : std_logic_vector(1 downto 0) := "10";
Constant AXI_BURST_RESVD : std_logic_vector(1 downto 0) := "11";
Constant AXI_SIZE_1BYTE : std_logic_vector(2 downto 0) := "000";
Constant AXI_SIZE_2BYTE : std_logic_vector(2 downto 0) := "001";
Constant AXI_SIZE_4BYTE : std_logic_vector(2 downto 0) := "010";
Constant AXI_SIZE_8BYTE : std_logic_vector(2 downto 0) := "011";
Constant AXI_SIZE_16BYTE : std_logic_vector(2 downto 0) := "100";
Constant AXI_SIZE_32BYTE : std_logic_vector(2 downto 0) := "101";
Constant AXI_SIZE_64BYTE : std_logic_vector(2 downto 0) := "110";
Constant AXI_SIZE_128BYTE : std_logic_vector(2 downto 0) := "111";
Constant BTT_SLICE_SIZE : integer := funct_get_slice_width(C_MAX_BURST_LEN);
Constant MAX_BURST_LEN_US : unsigned(BTT_SLICE_SIZE-1 downto 0) :=
TO_UNSIGNED(C_MAX_BURST_LEN-1, BTT_SLICE_SIZE);
Constant BTT_LS_UNUSED_WIDTH : integer := funct_get_btt_ls_unused(C_STREAM_DWIDTH);
Constant CMD_BTT_WIDTH : integer := BTT_SLICE_SIZE+BTT_LS_UNUSED_WIDTH;
Constant CMD_BTT_LS_INDEX : integer := 0;
Constant CMD_BTT_MS_INDEX : integer := CMD_BTT_WIDTH-1;
Constant BTT_ZEROS : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
Constant BTT_RESIDUE_ZEROS : unsigned(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
Constant BTT_SLICE_ONE : unsigned(BTT_SLICE_SIZE-1 downto 0) := TO_UNSIGNED(1, BTT_SLICE_SIZE);
Constant STRB_WIDTH : integer := C_STREAM_DWIDTH/8; -- Number of bytes in the Stream
Constant LEN_WIDTH : integer := 8;
-- Type Declarations --------------------------------------------
type SCC_SM_STATE_TYPE is (
INIT,
POP_RECOVER,
GET_NXT_CMD,
CHK_AND_CALC,
PUSH_TO_AXI,
ERROR_TRAP
);
-- Signal Declarations --------------------------------------------
signal sm_scc_state : SCC_SM_STATE_TYPE := INIT;
signal sm_scc_state_ns : SCC_SM_STATE_TYPE := INIT;
signal sm_pop_input_cmd : std_logic := '0';
signal sm_pop_input_cmd_ns : std_logic := '0';
signal sm_set_push2axi : std_logic := '0';
signal sm_set_push2axi_ns : std_logic := '0';
signal sm_set_error : std_logic := '0';
signal sm_set_error_ns : std_logic := '0';
Signal sm_scc_sm_ready : std_logic := '0';
Signal sm_scc_sm_ready_ns : std_logic := '0';
signal sig_cmd2data_valid : std_logic := '0';
signal sig_clr_cmd2data_valid : std_logic := '0';
signal sig_cmd2addr_valid : std_logic := '0';
signal sig_cmd2addr_valid1 : std_logic := '0';
signal sig_clr_cmd2addr_valid : std_logic := '0';
signal sig_addr_data_rdy_pending : std_logic := '0';
signal sig_cmd_btt_slice : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_load_input_cmd : std_logic := '0';
signal sig_cmd_reg_empty : std_logic := '0';
signal sig_cmd_reg_full : std_logic := '0';
signal sig_cmd_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_btt_reg : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_type_reg : std_logic := '0';
signal sig_cmd_burst_reg : std_logic_vector (1 downto 0) := "00";
signal sig_cmd_tag_reg : std_logic_vector(CMD_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_data_rdy4cmd : std_logic := '0';
signal sig_btt_raw : std_logic := '0';
signal sig_btt_is_zero : std_logic := '0';
signal sig_btt_is_zero_reg : std_logic := '0';
signal sig_next_tag : std_logic_vector(CMD_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_next_addr : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_next_len : std_logic_vector(LEN_WIDTH-1 downto 0) := (others => '0');
signal sig_next_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_next_burst : std_logic_vector(1 downto 0) := (others => '0');
signal sig_next_cache : std_logic_vector(3 downto 0) := (others => '0');
signal sig_next_user : std_logic_vector(3 downto 0) := (others => '0');
signal sig_next_strt_strb : std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0) := (others => '0');
signal sig_next_end_strb : std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0) := (others => '0');
begin --(architecture implementation)
-- Assign calculation error output
calc_error <= sm_set_error;
-- Assign the ready output to the Command FIFO
mst2cmd_cmd_ready <= sig_cmd_reg_empty and addr2mstr_cmd_ready; --sm_scc_sm_ready;
-- Assign the Address Channel Controller Qualifiers
mstr2addr_tag <= sig_next_tag ;
mstr2addr_addr <= sig_next_addr ;
mstr2addr_len <= sig_next_len ;
mstr2addr_size <= sig_next_size ;
mstr2addr_burst <= sig_cmd_burst_reg;
mstr2addr_cache <= sig_next_cache;
mstr2addr_user <= sig_next_user;
mstr2addr_cmd_valid <= sig_cmd2addr_valid1;
mstr2addr_calc_error <= sm_set_error ;
mstr2addr_cmd_cmplt <= '1' ; -- Lite mode is always 1
-- Assign the Data Channel Controller Qualifiers
mstr2data_tag <= sig_next_tag ;
mstr2data_saddr_lsb <= sig_cmd_addr_reg(C_SEL_ADDR_WIDTH-1 downto 0);
mstr2data_len <= sig_next_len ;
mstr2data_strt_strb <= (others => '1'); --sig_next_strt_strb; -- always F
mstr2data_last_strb <= (others => '1'); --sig_next_end_strb; -- always F
mstr2data_sof <= '1'; -- Lite mode is always 1 cmd
mstr2data_eof <= '1'; -- Lite mode is always 1 cmd
mstr2data_cmd_cmplt <= '1'; -- Lite mode is always 1 cmd
-- mstr2data_cmd_valid <= sig_cmd2data_valid;
mstr2data_cmd_valid <= sig_cmd2addr_valid1; --sig_cmd2data_valid;
mstr2data_calc_error <= sm_set_error;
-- Internal logic ------------------------------
sig_addr_data_rdy_pending <= sig_cmd2addr_valid or
sig_cmd2data_valid;
sig_clr_cmd2data_valid <= sig_cmd2data_valid and data2mstr_cmd_ready;
sig_clr_cmd2addr_valid <= sig_cmd2addr_valid and addr2mstr_cmd_ready;
sig_load_input_cmd <= cmd2mstr_cmd_valid and
sig_cmd_reg_empty;-- and
-- sm_scc_sm_ready;
sig_next_tag <= sig_cmd_tag_reg;
sig_next_addr <= sig_cmd_addr_reg;
sig_addr_data_rdy4cmd <= addr2mstr_cmd_ready and data2mstr_cmd_ready;
sig_cmd_btt_slice <= cmd2mstr_command(CMD_BTT_MS_INDEX downto CMD_BTT_LS_INDEX);
sig_btt_is_zero <= '1'
when (sig_cmd_btt_slice = BTT_ZEROS)
Else '0';
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_RESIDUE_BITS
--
-- If Generate Description:
--
--
--
------------------------------------------------------------
GEN_NO_RESIDUE_BITS : if (BTT_LS_UNUSED_WIDTH = 0) generate
-- signals
signal sig_len_btt_slice : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
signal sig_len_btt_slice_minus_1 : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
signal sig_len2use : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
begin
-- LEN Calculation logic ------------------------------------------
sig_next_len <= STD_LOGIC_VECTOR(RESIZE(sig_len2use, LEN_WIDTH));
sig_len_btt_slice <= UNSIGNED(sig_cmd_btt_reg(CMD_BTT_MS_INDEX downto 0));
sig_len_btt_slice_minus_1 <= sig_len_btt_slice-BTT_SLICE_ONE
when sig_btt_is_zero_reg = '0'
else (others => '0'); -- clip at zero
-- If most significant bit of BTT set then limit to
-- Max Burst Len, else rip it from the BTT value,
-- otheriwse subtract 1 from the BTT ripped value
-- 1 from the BTT ripped value
sig_len2use <= MAX_BURST_LEN_US
When (sig_cmd_btt_reg(CMD_BTT_MS_INDEX) = '1')
Else sig_len_btt_slice_minus_1;
end generate GEN_NO_RESIDUE_BITS;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_HAS_RESIDUE_BITS
--
-- If Generate Description:
--
--
--
------------------------------------------------------------
GEN_HAS_RESIDUE_BITS : if (BTT_LS_UNUSED_WIDTH > 0) generate
-- signals
signal sig_btt_len_residue : unsigned(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
signal sig_len_btt_slice : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
signal sig_len_btt_slice_minus_1 : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
signal sig_len2use : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
begin
-- LEN Calculation logic ------------------------------------------
WR_EXTRA_FIELDS : if (C_ENABLE_EXTRA_FIELD = 1) generate
sig_next_len <= "00000000" when sig_cmd_tag_reg (0) = '1'
else "00000101"; --STD_LOGIC_VECTOR(RESIZE(sig_len2use, LEN_WIDTH));
end generate WR_EXTRA_FIELDS;
NOWR_EXTRA_FIELDS : if (C_ENABLE_EXTRA_FIELD = 0) generate
sig_next_len <= "00000000";
end generate NOWR_EXTRA_FIELDS;
-- sig_next_len <= STD_LOGIC_VECTOR(RESIZE(sig_len2use, LEN_WIDTH));
sig_len_btt_slice <= UNSIGNED(sig_cmd_btt_reg(CMD_BTT_MS_INDEX downto BTT_LS_UNUSED_WIDTH));
sig_len_btt_slice_minus_1 <= sig_len_btt_slice-BTT_SLICE_ONE
when sig_btt_is_zero_reg = '0'
else (others => '0'); -- clip at zero
sig_btt_len_residue <= UNSIGNED(sig_cmd_btt_reg(BTT_LS_UNUSED_WIDTH-1 downto 0));
-- If most significant bit of BTT set then limit to
-- Max Burst Len, else rip it from the BTT value
-- However if residue bits are zeroes then subtract
-- 1 from the BTT ripped value
sig_len2use <= MAX_BURST_LEN_US
When (sig_cmd_btt_reg(CMD_BTT_MS_INDEX) = '1')
Else sig_len_btt_slice_minus_1
when (sig_btt_len_residue = BTT_RESIDUE_ZEROS)
Else sig_len_btt_slice;
end generate GEN_HAS_RESIDUE_BITS;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_INPUT_CMD
--
-- Process Description:
-- Implements the input command holding registers
--
-------------------------------------------------------------
REG_INPUT_CMD : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
addr2mstr_cmd_ready = '0') then
-- sm_pop_input_cmd = '1') then
sig_cmd_btt_reg <= (others => '0');
sig_cmd_type_reg <= '0';
sig_cmd_addr_reg <= (others => '0');
sig_cmd_tag_reg <= (others => '0');
sig_btt_is_zero_reg <= '0';
sig_cmd_reg_empty <= '1';
sig_cmd_reg_full <= '0';
sig_cmd_burst_reg <= "00";
sig_cmd2addr_valid1 <= '0';
elsif (sig_load_input_cmd = '1') then
sig_cmd_btt_reg <= sig_cmd_btt_slice;
sig_cmd_type_reg <= cmd2mstr_command(CMD_TYPE_INDEX);
sig_cmd_addr_reg <= cmd2mstr_command(CMD_ADDR_MS_INDEX downto CMD_ADDR_LS_INDEX);
sig_cmd_tag_reg <= cmd2mstr_command(CMD_TAG_MS_INDEX downto CMD_TAG_LS_INDEX);
sig_btt_is_zero_reg <= sig_btt_is_zero;
sig_cmd_reg_empty <= '0';
sig_cmd_reg_full <= '1';
sig_cmd2addr_valid1 <= '1';
sig_cmd_burst_reg <= sig_next_burst;
else
null; -- Hold current State
end if;
end if;
end process REG_INPUT_CMD;
-- Only Incrementing Burst type supported (per Interface_X guidelines)
sig_next_burst <= AXI_BURST_INCR when (cmd2mstr_command(CMD_TYPE_INDEX) = '1') else
AXI_BURST_FIXED;
sig_next_user <= cache2mstr_command (7 downto 4);
sig_next_cache <= cache2mstr_command (3 downto 0);
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LEN_SDWIDTH_64
--
-- If Generate Description:
-- This IfGen implements the AXI LEN qualifier calculation
-- and the Stream data channel start/end STRB value.
--
-- This IfGen is for the 64-bit Stream data Width case.
--
------------------------------------------------------------
GEN_LEN_SDWIDTH_64 : if (C_STREAM_DWIDTH = 64) generate
-- Local Constants
Constant AXI_SIZE2USE : std_logic_vector(2 downto 0) := AXI_SIZE_8BYTE;
Constant RESIDUE_BIT_WIDTH : integer := 3;
-- local signals
signal sig_last_strb2use : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
Signal sig_btt_ms_bit_value : std_logic := '0';
signal lsig_btt_len_residue : std_logic_vector(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_len_residue_composite : std_logic_vector(RESIDUE_BIT_WIDTH downto 0) := (others => '0');
-- note 1 extra bit implied
begin
-- Assign the Address Channel Controller Size Qualifier Value
sig_next_size <= AXI_SIZE2USE;
-- Assign the Strobe Values
sig_next_strt_strb <= (others => '1'); -- always aligned on first databeat for LITE DataMover
sig_next_end_strb <= sig_last_strb;
-- Local calculations ------------------------------
lsig_btt_len_residue <= sig_cmd_btt_reg(BTT_LS_UNUSED_WIDTH-1 downto 0);
sig_btt_ms_bit_value <= sig_cmd_btt_reg(CMD_BTT_MS_INDEX);
sig_btt_len_residue_composite <= sig_btt_ms_bit_value &
lsig_btt_len_residue;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_LAST_STRB_8bit
--
-- Process Description:
-- Generates the Strobe values for the LAST databeat of the
-- Burst to MMap when the Stream is 64 bits wide and 8 strobe
-- bits are required.
--
-------------------------------------------------------------
IMP_LAST_STRB_8bit : process (sig_btt_len_residue_composite)
begin
case sig_btt_len_residue_composite is
when "0001" =>
sig_last_strb <= "00000001";
when "0010" =>
sig_last_strb <= "00000011";
when "0011" =>
sig_last_strb <= "00000111";
when "0100" =>
sig_last_strb <= "00001111";
when "0101" =>
sig_last_strb <= "00011111";
when "0110" =>
sig_last_strb <= "00111111";
when "0111" =>
sig_last_strb <= "01111111";
when others =>
sig_last_strb <= "11111111";
end case;
end process IMP_LAST_STRB_8bit;
end generate GEN_LEN_SDWIDTH_64;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LEN_SDWIDTH_32
--
-- If Generate Description:
-- This IfGen implements the AXI LEN qualifier calculation
-- and the Stream data channel start/end STRB value.
--
-- This IfGen is for the 32-bit Stream data Width case.
--
------------------------------------------------------------
GEN_LEN_SDWIDTH_32 : if (C_STREAM_DWIDTH = 32) generate
-- Local Constants
Constant AXI_SIZE2USE : std_logic_vector(2 downto 0) := AXI_SIZE_4BYTE;
Constant RESIDUE_BIT_WIDTH : integer := 2;
-- local signals
signal sig_last_strb2use : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
Signal sig_btt_ms_bit_value : std_logic := '0';
signal sig_btt_len_residue_composite : std_logic_vector(RESIDUE_BIT_WIDTH downto 0) := (others => '0'); -- 1 extra bit
signal lsig_btt_len_residue : std_logic_vector(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
begin
-- Assign the Address Channel Controller Size Qualifier Value
sig_next_size <= AXI_SIZE2USE;
-- Assign the Strobe Values
sig_next_strt_strb <= (others => '1'); -- always aligned on first databeat for LITE DataMover
sig_next_end_strb <= sig_last_strb;
-- Local calculations ------------------------------
lsig_btt_len_residue <= sig_cmd_btt_reg(BTT_LS_UNUSED_WIDTH-1 downto 0);
sig_btt_ms_bit_value <= sig_cmd_btt_reg(CMD_BTT_MS_INDEX);
sig_btt_len_residue_composite <= sig_btt_ms_bit_value &
lsig_btt_len_residue;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_LAST_STRB_4bit
--
-- Process Description:
-- Generates the Strobe values for the LAST databeat of the
-- Burst to MMap when the Stream is 32 bits wide and 4 strobe
-- bits are required.
--
-------------------------------------------------------------
IMP_LAST_STRB_4bit : process (sig_btt_len_residue_composite)
begin
case sig_btt_len_residue_composite is
-- coverage off
when "001" =>
sig_last_strb <= "0001";
when "010" =>
sig_last_strb <= "0011";
when "011" =>
sig_last_strb <= "0111";
-- coverage on
when others =>
sig_last_strb <= "1111";
end case;
end process IMP_LAST_STRB_4bit;
end generate GEN_LEN_SDWIDTH_32;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LEN_SDWIDTH_16
--
-- If Generate Description:
-- This IfGen implements the AXI LEN qualifier calculation
-- and the Stream data channel start/end STRB value.
--
-- This IfGen is for the 16-bit Stream data Width case.
--
------------------------------------------------------------
GEN_LEN_SDWIDTH_16 : if (C_STREAM_DWIDTH = 16) generate
-- Local Constants
Constant AXI_SIZE2USE : std_logic_vector(2 downto 0) := AXI_SIZE_2BYTE;
Constant RESIDUE_BIT_WIDTH : integer := 1;
-- local signals
signal sig_last_strb2use : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
Signal sig_btt_ms_bit_value : std_logic := '0';
signal sig_btt_len_residue_composite : std_logic_vector(RESIDUE_BIT_WIDTH downto 0) := (others => '0'); -- 1 extra bit
signal lsig_btt_len_residue : std_logic_vector(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
begin
-- Assign the Address Channel Controller Size Qualifier Value
sig_next_size <= AXI_SIZE2USE;
-- Assign the Strobe Values
sig_next_strt_strb <= (others => '1'); -- always aligned on first databeat for LITE DataMover
sig_next_end_strb <= sig_last_strb;
-- Local calculations ------------------------------
lsig_btt_len_residue <= sig_cmd_btt_reg(BTT_LS_UNUSED_WIDTH-1 downto 0);
sig_btt_ms_bit_value <= sig_cmd_btt_reg(CMD_BTT_MS_INDEX);
sig_btt_len_residue_composite <= sig_btt_ms_bit_value &
lsig_btt_len_residue;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_LAST_STRB_2bit
--
-- Process Description:
-- Generates the Strobe values for the LAST databeat of the
-- Burst to MMap when the Stream is 16 bits wide and 2 strobe
-- bits are required.
--
-------------------------------------------------------------
IMP_LAST_STRB_2bit : process (sig_btt_len_residue_composite)
begin
case sig_btt_len_residue_composite is
when "01" =>
sig_last_strb <= "01";
when others =>
sig_last_strb <= "11";
end case;
end process IMP_LAST_STRB_2bit;
end generate GEN_LEN_SDWIDTH_16;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LEN_SDWIDTH_8
--
-- If Generate Description:
-- This IfGen implements the AXI LEN qualifier calculation
-- and the Stream data channel start/end STRB value.
--
-- This IfGen is for the 8-bit Stream data Width case.
--
------------------------------------------------------------
GEN_LEN_SDWIDTH_8 : if (C_STREAM_DWIDTH = 8) generate
-- Local Constants
Constant AXI_SIZE2USE : std_logic_vector(2 downto 0) := AXI_SIZE_1BYTE;
begin
-- Assign the Address Channel Controller Qualifiers
sig_next_size <= AXI_SIZE2USE;
-- Assign the Data Channel Controller Qualifiers
sig_next_strt_strb <= (others => '1');
sig_next_end_strb <= (others => '1');
end generate GEN_LEN_SDWIDTH_8;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CMD2DATA_VALID_FLOP
--
-- Process Description:
-- Implements the set/reset flop for the Command Ready control
-- to the Data Controller Module.
--
-------------------------------------------------------------
CMD2DATA_VALID_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_clr_cmd2data_valid = '1') then
sig_cmd2data_valid <= '0';
elsif (sm_set_push2axi_ns = '1') then
sig_cmd2data_valid <= '1';
else
null; -- hold current state
end if;
end if;
end process CMD2DATA_VALID_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CMD2ADDR_VALID_FLOP
--
-- Process Description:
-- Implements the set/reset flop for the Command Ready control
-- to the Address Controller Module.
--
-------------------------------------------------------------
CMD2ADDR_VALID_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_clr_cmd2addr_valid = '1') then
sig_cmd2addr_valid <= '0';
elsif (sm_set_push2axi_ns = '1') then
sig_cmd2addr_valid <= '1';
else
null; -- hold current state
end if;
end if;
end process CMD2ADDR_VALID_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SCC_SM_REG
--
-- Process Description:
-- Implements registered portion of state machine
--
-------------------------------------------------------------
SCC_SM_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
-- sm_scc_state <= INIT;
-- sm_pop_input_cmd <= '0' ;
-- sm_set_push2axi <= '0' ;
sm_set_error <= '0' ;
-- sm_scc_sm_ready <= '0' ;
elsif (sig_btt_is_zero_reg = '1') then
sm_set_error <= '1';
-- sm_scc_state <= sm_scc_state_ns ;
-- sm_pop_input_cmd <= sm_pop_input_cmd_ns ;
-- sm_set_push2axi <= sm_set_push2axi_ns ;
-- sm_set_error <= sm_set_error_ns ;
-- sm_scc_sm_ready <= sm_scc_sm_ready_ns ;
end if;
end if;
end process SCC_SM_REG;
end implementation;
|
bsd-3-clause
|
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/Video_PR_1.0/hdl/Video_PR_v1_0_S_AXI.vhd
|
1
|
16260
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
Library UNISIM;
use UNISIM.vcomponents.all;
entity Video_PR_v1_0_S_AXI is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bus
C_S_AXI_ADDR_WIDTH : integer := 11
);
port (
-- Users to add ports here
-- Users to add ports here
RGB_IN : in std_logic_vector(23 downto 0); -- Parallel video data (required)
VDE_IN : in std_logic; -- Active video Flag (optional)
HS_IN : in std_logic; -- Horizontal sync signal (optional)
VS_IN : in std_logic; -- Veritcal sync signal (optional)
-- additional ports here
RGB_OUT : out std_logic_vector(23 downto 0); -- Parallel video data (required)
VDE_OUT : out std_logic; -- Active video Flag (optional)
HS_OUT : out std_logic; -- Horizontal sync signal (optional)
VS_OUT : out std_logic; -- Veritcal sync signal (optional)
PIXEL_CLK : in std_logic;
-- User ports ends
-- Do not modify the ports beyond this line
-- Global Clock Signal
S_AXI_ACLK : in std_logic;
-- Global Reset Signal. This Signal is Active LOW
S_AXI_ARESETN : in std_logic;
-- Write address (issued by master, acceped by Slave)
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Write channel Protection type. This signal indicates the
-- privilege and security level of the transaction, and whether
-- the transaction is a data access or an instruction access.
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
-- Write address valid. This signal indicates that the master signaling
-- valid write address and control information.
S_AXI_AWVALID : in std_logic;
-- Write address ready. This signal indicates that the slave is ready
-- to accept an address and associated control signals.
S_AXI_AWREADY : out std_logic;
-- Write data (issued by master, acceped by Slave)
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Write strobes. This signal indicates which byte lanes hold
-- valid data. There is one write strobe bit for each eight
-- bits of the write data bus.
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
-- Write valid. This signal indicates that valid write
-- data and strobes are available.
S_AXI_WVALID : in std_logic;
-- Write ready. This signal indicates that the slave
-- can accept the write data.
S_AXI_WREADY : out std_logic;
-- Write response. This signal indicates the status
-- of the write transaction.
S_AXI_BRESP : out std_logic_vector(1 downto 0);
-- Write response valid. This signal indicates that the channel
-- is signaling a valid write response.
S_AXI_BVALID : out std_logic;
-- Response ready. This signal indicates that the master
-- can accept a write response.
S_AXI_BREADY : in std_logic;
-- Read address (issued by master, acceped by Slave)
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Protection type. This signal indicates the privilege
-- and security level of the transaction, and whether the
-- transaction is a data access or an instruction access.
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
-- Read address valid. This signal indicates that the channel
-- is signaling valid read address and control information.
S_AXI_ARVALID : in std_logic;
-- Read address ready. This signal indicates that the slave is
-- ready to accept an address and associated control signals.
S_AXI_ARREADY : out std_logic;
-- Read data (issued by slave)
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Read response. This signal indicates the status of the
-- read transfer.
S_AXI_RRESP : out std_logic_vector(1 downto 0);
-- Read valid. This signal indicates that the channel is
-- signaling the required read data.
S_AXI_RVALID : out std_logic;
-- Read ready. This signal indicates that the master can
-- accept the read data and response information.
S_AXI_RREADY : in std_logic
);
end Video_PR_v1_0_S_AXI;
architecture arch_imp of Video_PR_v1_0_S_AXI is
component pixel_counter is
port(
clk : in std_logic;
hs : in std_logic;
vs : in std_logic;
vde : in std_logic;
pixel_x : out std_logic_vector(15 downto 0);
pixel_y : out std_logic_vector(15 downto 0)
);
end component pixel_counter;
component Video_Box is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bus
C_S_AXI_ADDR_WIDTH : integer := 11
);
port (
S_AXI_ARESETN : in std_logic;
slv_reg_wren : in std_logic;
slv_reg_rden : in std_logic;
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
axi_awaddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
axi_araddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
reg_data_out : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
--Bus Clock
S_AXI_ACLK : in std_logic;
--Video
RGB_IN : in std_logic_vector(23 downto 0); -- Parallel video data (required)
VDE_IN : in std_logic; -- Active video Flag (optional)
HS_IN : in std_logic; -- Horizontal sync signal (optional)
VS_IN : in std_logic; -- Veritcal sync signal (optional)
-- additional ports here
RGB_OUT : out std_logic_vector(23 downto 0); -- Parallel video data (required)
VDE_OUT : out std_logic; -- Active video Flag (optional)
HS_OUT : out std_logic; -- Horizontal sync signal (optional)
VS_OUT : out std_logic; -- Veritcal sync signal (optional)
PIXEL_CLK : in std_logic;
X_Coord : in std_logic_vector(15 downto 0);
Y_Coord : in std_logic_vector(15 downto 0)
);
end component Video_Box;
-- AXI4LITE signals
signal axi_awaddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_awready : std_logic;
signal axi_wready : std_logic;
signal axi_bresp : std_logic_vector(1 downto 0);
signal axi_bvalid : std_logic;
signal axi_araddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_arready : std_logic;
signal axi_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal axi_rresp : std_logic_vector(1 downto 0);
signal axi_rvalid : std_logic;
-- Example-specific design signals
-- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
-- ADDR_LSB is used for addressing 32/64 bit registers/memories
-- ADDR_LSB = 2 for 32 bits (n downto 2)
-- ADDR_LSB = 3 for 64 bits (n downto 3)
constant ADDR_LSB : integer := (C_S_AXI_DATA_WIDTH/32)+ 1;
--constant OPT_MEM_ADDR_BITS : integer := 2;
------------------------------------------------
signal slv_reg_rden : std_logic;
signal slv_reg_wren : std_logic;
signal reg_data_out :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal byte_index : integer;
signal x_coord,y_coord : std_logic_vector(15 downto 0);
signal RGB_IN_reg, RGB_OUT_reg,RGB_OUT_next: std_logic_vector(23 downto 0):= (others=>'0');
signal X_Coord_reg,Y_Coord_reg : std_logic_vector(15 downto 0):= (others=>'0');
signal VDE_IN_reg,VDE_OUT_reg,HS_IN_reg,HS_OUT_reg,VS_IN_reg,VS_OUT_reg : std_logic := '0';
signal VDE_OUT_next,HS_OUT_next,VS_OUT_next : std_logic ;
begin
Pixel_Counter_0 : Pixel_Counter
port map(
clk => PIXEL_CLK,
hs => HS_IN,
vs => VS_IN,
vde => VDE_IN,
pixel_x => x_coord,
pixel_y => y_coord
);
Video_Box_0: Video_Box
generic map(
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH
)
port map(
S_AXI_ARESETN => S_AXI_ARESETN,
slv_reg_wren => slv_reg_wren,
slv_reg_rden => slv_reg_rden,
S_AXI_WSTRB => S_AXI_WSTRB,
axi_awaddr => axi_awaddr,
S_AXI_WDATA => S_AXI_WDATA,
axi_araddr => axi_araddr,
reg_data_out => reg_data_out,
--Bus Clock
S_AXI_ACLK => S_AXI_ACLK,
--Video
RGB_IN => RGB_IN_reg,
VDE_IN => VDE_IN_reg,
HS_IN => HS_IN_reg,
VS_IN => VS_IN_reg,
-- additional ports here
RGB_OUT => RGB_OUT_next,
VDE_OUT => VDE_OUT_next,
HS_OUT => HS_OUT_next,
VS_OUT =>VS_OUT_next,
PIXEL_CLK => PIXEL_CLK,
X_Coord => X_Coord_reg,
Y_Coord => Y_Coord_reg
);
process(PIXEL_CLK) is
begin
if (rising_edge (PIXEL_CLK)) then
-- Video Input Signals
RGB_IN_reg <= RGB_IN;
X_Coord_reg <= X_Coord;
Y_Coord_reg <= Y_Coord;
VDE_IN_reg <= VDE_IN;
HS_IN_reg <= HS_IN;
VS_IN_reg <= VS_IN;
-- Video Output Signals
RGB_OUT_reg <= RGB_OUT_next;
VDE_OUT_reg <= VDE_OUT_next;
HS_OUT_reg <= HS_OUT_next;
VS_OUT_reg <= VS_OUT_next;
end if;
end process;
RGB_OUT <= RGB_OUT_reg;
VDE_OUT <= VDE_OUT_reg;
HS_OUT <= HS_OUT_reg;
VS_OUT <= VS_OUT_reg;
-- I/O Connections assignments
S_AXI_AWREADY <= axi_awready;
S_AXI_WREADY <= axi_wready;
S_AXI_BRESP <= axi_bresp;
S_AXI_BVALID <= axi_bvalid;
S_AXI_ARREADY <= axi_arready;
S_AXI_RDATA <= axi_rdata;
S_AXI_RRESP <= axi_rresp;
S_AXI_RVALID <= axi_rvalid;
-- Implement axi_awready generation
-- axi_awready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awready <= '0';
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- slave is ready to accept write address when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_awready <= '1';
else
axi_awready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_awaddr latching
-- This process is used to latch the address when both
-- S_AXI_AWVALID and S_AXI_WVALID are valid.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awaddr <= (others => '0');
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- Write Address latching
axi_awaddr <= S_AXI_AWADDR;
end if;
end if;
end if;
end process;
-- Implement axi_wready generation
-- axi_wready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_wready <= '0';
else
if (axi_wready = '0' and S_AXI_WVALID = '1' and S_AXI_AWVALID = '1') then
-- slave is ready to accept write data when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_wready <= '1';
else
axi_wready <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and write logic generation
-- The write data is accepted and written to memory mapped registers when
-- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
-- select byte enables of slave registers while writing.
-- These registers are cleared when reset (active low) is applied.
-- Slave register write enable is asserted when valid address and data are available
-- and the slave is ready to accept the write address and write data.
slv_reg_wren <= axi_wready and S_AXI_WVALID and axi_awready and S_AXI_AWVALID ;
-- Implement write response logic generation
-- The write response and response valid signals are asserted by the slave
-- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
-- This marks the acceptance of address and indicates the status of
-- write transaction.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_bvalid <= '0';
axi_bresp <= "00"; --need to work more on the responses
else
if (axi_awready = '1' and S_AXI_AWVALID = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0' ) then
axi_bvalid <= '1';
axi_bresp <= "00";
elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high)
axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high)
end if;
end if;
end if;
end process;
-- Implement axi_arready generation
-- axi_arready is asserted for one S_AXI_ACLK clock cycle when
-- S_AXI_ARVALID is asserted. axi_awready is
-- de-asserted when reset (active low) is asserted.
-- The read address is also latched when S_AXI_ARVALID is
-- asserted. axi_araddr is reset to zero on reset assertion.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_arready <= '0';
axi_araddr <= (others => '1');
else
if (axi_arready = '0' and S_AXI_ARVALID = '1') then
-- indicates that the slave has acceped the valid read address
axi_arready <= '1';
-- Read Address latching
axi_araddr <= S_AXI_ARADDR;
else
axi_arready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_arvalid generation
-- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_ARVALID and axi_arready are asserted. The slave registers
-- data are available on the axi_rdata bus at this instance. The
-- assertion of axi_rvalid marks the validity of read data on the
-- bus and axi_rresp indicates the status of read transaction.axi_rvalid
-- is deasserted on reset (active low). axi_rresp and axi_rdata are
-- cleared to zero on reset (active low).
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_rvalid <= '0';
axi_rresp <= "00";
else
if (axi_arready = '1' and S_AXI_ARVALID = '1' and axi_rvalid = '0') then
-- Valid read data is available at the read data bus
axi_rvalid <= '1';
axi_rresp <= "00"; -- 'OKAY' response
elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then
-- Read data is accepted by the master
axi_rvalid <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and read logic generation
-- Slave register read enable is asserted when valid address is available
-- and the slave is ready to accept the read address.
slv_reg_rden <= axi_arready and S_AXI_ARVALID and (not axi_rvalid) ;
-- Output register or memory read data
process( S_AXI_ACLK ) is
begin
if (rising_edge (S_AXI_ACLK)) then
if ( S_AXI_ARESETN = '0' ) then
axi_rdata <= (others => '0');
else
if (slv_reg_rden = '1') then
-- When there is a valid read address (S_AXI_ARVALID) with
-- acceptance of read address by the slave (axi_arready),
-- output the read dada
-- Read address mux
axi_rdata <= reg_data_out; -- register read data
end if;
end if;
end if;
end process;
-- Add user logic here
-- User logic ends
end arch_imp;
|
bsd-3-clause
|
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/usb2device_v1_0/src/fifo_generator_input_buffer/sim/fifo_generator_input_buffer.vhd
|
1
|
33811
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fifo_generator:13.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fifo_generator_v13_0_1;
USE fifo_generator_v13_0_1.fifo_generator_v13_0_1;
ENTITY fifo_generator_input_buffer IS
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC
);
END fifo_generator_input_buffer;
ARCHITECTURE fifo_generator_input_buffer_arch OF fifo_generator_input_buffer IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF fifo_generator_input_buffer_arch: ARCHITECTURE IS "yes";
COMPONENT fifo_generator_v13_0_1 IS
GENERIC (
C_COMMON_CLOCK : INTEGER;
C_COUNT_TYPE : INTEGER;
C_DATA_COUNT_WIDTH : INTEGER;
C_DEFAULT_VALUE : STRING;
C_DIN_WIDTH : INTEGER;
C_DOUT_RST_VAL : STRING;
C_DOUT_WIDTH : INTEGER;
C_ENABLE_RLOCS : INTEGER;
C_FAMILY : STRING;
C_FULL_FLAGS_RST_VAL : INTEGER;
C_HAS_ALMOST_EMPTY : INTEGER;
C_HAS_ALMOST_FULL : INTEGER;
C_HAS_BACKUP : INTEGER;
C_HAS_DATA_COUNT : INTEGER;
C_HAS_INT_CLK : INTEGER;
C_HAS_MEMINIT_FILE : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_RD_DATA_COUNT : INTEGER;
C_HAS_RD_RST : INTEGER;
C_HAS_RST : INTEGER;
C_HAS_SRST : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_VALID : INTEGER;
C_HAS_WR_ACK : INTEGER;
C_HAS_WR_DATA_COUNT : INTEGER;
C_HAS_WR_RST : INTEGER;
C_IMPLEMENTATION_TYPE : INTEGER;
C_INIT_WR_PNTR_VAL : INTEGER;
C_MEMORY_TYPE : INTEGER;
C_MIF_FILE_NAME : STRING;
C_OPTIMIZATION_MODE : INTEGER;
C_OVERFLOW_LOW : INTEGER;
C_PRELOAD_LATENCY : INTEGER;
C_PRELOAD_REGS : INTEGER;
C_PRIM_FIFO_TYPE : STRING;
C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER;
C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER;
C_PROG_EMPTY_TYPE : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER;
C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER;
C_PROG_FULL_TYPE : INTEGER;
C_RD_DATA_COUNT_WIDTH : INTEGER;
C_RD_DEPTH : INTEGER;
C_RD_FREQ : INTEGER;
C_RD_PNTR_WIDTH : INTEGER;
C_UNDERFLOW_LOW : INTEGER;
C_USE_DOUT_RST : INTEGER;
C_USE_ECC : INTEGER;
C_USE_EMBEDDED_REG : INTEGER;
C_USE_PIPELINE_REG : INTEGER;
C_POWER_SAVING_MODE : INTEGER;
C_USE_FIFO16_FLAGS : INTEGER;
C_USE_FWFT_DATA_COUNT : INTEGER;
C_VALID_LOW : INTEGER;
C_WR_ACK_LOW : INTEGER;
C_WR_DATA_COUNT_WIDTH : INTEGER;
C_WR_DEPTH : INTEGER;
C_WR_FREQ : INTEGER;
C_WR_PNTR_WIDTH : INTEGER;
C_WR_RESPONSE_LATENCY : INTEGER;
C_MSGON_VAL : INTEGER;
C_ENABLE_RST_SYNC : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_ERROR_INJECTION_TYPE : INTEGER;
C_SYNCHRONIZER_STAGE : INTEGER;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_HAS_AXI_WR_CHANNEL : INTEGER;
C_HAS_AXI_RD_CHANNEL : INTEGER;
C_HAS_SLAVE_CE : INTEGER;
C_HAS_MASTER_CE : INTEGER;
C_ADD_NGC_CONSTRAINT : INTEGER;
C_USE_COMMON_OVERFLOW : INTEGER;
C_USE_COMMON_UNDERFLOW : INTEGER;
C_USE_DEFAULT_SETTINGS : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_AXI_ADDR_WIDTH : INTEGER;
C_AXI_DATA_WIDTH : INTEGER;
C_AXI_LEN_WIDTH : INTEGER;
C_AXI_LOCK_WIDTH : INTEGER;
C_HAS_AXI_ID : INTEGER;
C_HAS_AXI_AWUSER : INTEGER;
C_HAS_AXI_WUSER : INTEGER;
C_HAS_AXI_BUSER : INTEGER;
C_HAS_AXI_ARUSER : INTEGER;
C_HAS_AXI_RUSER : INTEGER;
C_AXI_ARUSER_WIDTH : INTEGER;
C_AXI_AWUSER_WIDTH : INTEGER;
C_AXI_WUSER_WIDTH : INTEGER;
C_AXI_BUSER_WIDTH : INTEGER;
C_AXI_RUSER_WIDTH : INTEGER;
C_HAS_AXIS_TDATA : INTEGER;
C_HAS_AXIS_TID : INTEGER;
C_HAS_AXIS_TDEST : INTEGER;
C_HAS_AXIS_TUSER : INTEGER;
C_HAS_AXIS_TREADY : INTEGER;
C_HAS_AXIS_TLAST : INTEGER;
C_HAS_AXIS_TSTRB : INTEGER;
C_HAS_AXIS_TKEEP : INTEGER;
C_AXIS_TDATA_WIDTH : INTEGER;
C_AXIS_TID_WIDTH : INTEGER;
C_AXIS_TDEST_WIDTH : INTEGER;
C_AXIS_TUSER_WIDTH : INTEGER;
C_AXIS_TSTRB_WIDTH : INTEGER;
C_AXIS_TKEEP_WIDTH : INTEGER;
C_WACH_TYPE : INTEGER;
C_WDCH_TYPE : INTEGER;
C_WRCH_TYPE : INTEGER;
C_RACH_TYPE : INTEGER;
C_RDCH_TYPE : INTEGER;
C_AXIS_TYPE : INTEGER;
C_IMPLEMENTATION_TYPE_WACH : INTEGER;
C_IMPLEMENTATION_TYPE_WDCH : INTEGER;
C_IMPLEMENTATION_TYPE_WRCH : INTEGER;
C_IMPLEMENTATION_TYPE_RACH : INTEGER;
C_IMPLEMENTATION_TYPE_RDCH : INTEGER;
C_IMPLEMENTATION_TYPE_AXIS : INTEGER;
C_APPLICATION_TYPE_WACH : INTEGER;
C_APPLICATION_TYPE_WDCH : INTEGER;
C_APPLICATION_TYPE_WRCH : INTEGER;
C_APPLICATION_TYPE_RACH : INTEGER;
C_APPLICATION_TYPE_RDCH : INTEGER;
C_APPLICATION_TYPE_AXIS : INTEGER;
C_PRIM_FIFO_TYPE_WACH : STRING;
C_PRIM_FIFO_TYPE_WDCH : STRING;
C_PRIM_FIFO_TYPE_WRCH : STRING;
C_PRIM_FIFO_TYPE_RACH : STRING;
C_PRIM_FIFO_TYPE_RDCH : STRING;
C_PRIM_FIFO_TYPE_AXIS : STRING;
C_USE_ECC_WACH : INTEGER;
C_USE_ECC_WDCH : INTEGER;
C_USE_ECC_WRCH : INTEGER;
C_USE_ECC_RACH : INTEGER;
C_USE_ECC_RDCH : INTEGER;
C_USE_ECC_AXIS : INTEGER;
C_ERROR_INJECTION_TYPE_WACH : INTEGER;
C_ERROR_INJECTION_TYPE_WDCH : INTEGER;
C_ERROR_INJECTION_TYPE_WRCH : INTEGER;
C_ERROR_INJECTION_TYPE_RACH : INTEGER;
C_ERROR_INJECTION_TYPE_RDCH : INTEGER;
C_ERROR_INJECTION_TYPE_AXIS : INTEGER;
C_DIN_WIDTH_WACH : INTEGER;
C_DIN_WIDTH_WDCH : INTEGER;
C_DIN_WIDTH_WRCH : INTEGER;
C_DIN_WIDTH_RACH : INTEGER;
C_DIN_WIDTH_RDCH : INTEGER;
C_DIN_WIDTH_AXIS : INTEGER;
C_WR_DEPTH_WACH : INTEGER;
C_WR_DEPTH_WDCH : INTEGER;
C_WR_DEPTH_WRCH : INTEGER;
C_WR_DEPTH_RACH : INTEGER;
C_WR_DEPTH_RDCH : INTEGER;
C_WR_DEPTH_AXIS : INTEGER;
C_WR_PNTR_WIDTH_WACH : INTEGER;
C_WR_PNTR_WIDTH_WDCH : INTEGER;
C_WR_PNTR_WIDTH_WRCH : INTEGER;
C_WR_PNTR_WIDTH_RACH : INTEGER;
C_WR_PNTR_WIDTH_RDCH : INTEGER;
C_WR_PNTR_WIDTH_AXIS : INTEGER;
C_HAS_DATA_COUNTS_WACH : INTEGER;
C_HAS_DATA_COUNTS_WDCH : INTEGER;
C_HAS_DATA_COUNTS_WRCH : INTEGER;
C_HAS_DATA_COUNTS_RACH : INTEGER;
C_HAS_DATA_COUNTS_RDCH : INTEGER;
C_HAS_DATA_COUNTS_AXIS : INTEGER;
C_HAS_PROG_FLAGS_WACH : INTEGER;
C_HAS_PROG_FLAGS_WDCH : INTEGER;
C_HAS_PROG_FLAGS_WRCH : INTEGER;
C_HAS_PROG_FLAGS_RACH : INTEGER;
C_HAS_PROG_FLAGS_RDCH : INTEGER;
C_HAS_PROG_FLAGS_AXIS : INTEGER;
C_PROG_FULL_TYPE_WACH : INTEGER;
C_PROG_FULL_TYPE_WDCH : INTEGER;
C_PROG_FULL_TYPE_WRCH : INTEGER;
C_PROG_FULL_TYPE_RACH : INTEGER;
C_PROG_FULL_TYPE_RDCH : INTEGER;
C_PROG_FULL_TYPE_AXIS : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_PROG_EMPTY_TYPE_WACH : INTEGER;
C_PROG_EMPTY_TYPE_WDCH : INTEGER;
C_PROG_EMPTY_TYPE_WRCH : INTEGER;
C_PROG_EMPTY_TYPE_RACH : INTEGER;
C_PROG_EMPTY_TYPE_RDCH : INTEGER;
C_PROG_EMPTY_TYPE_AXIS : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_REG_SLICE_MODE_WACH : INTEGER;
C_REG_SLICE_MODE_WDCH : INTEGER;
C_REG_SLICE_MODE_WRCH : INTEGER;
C_REG_SLICE_MODE_RACH : INTEGER;
C_REG_SLICE_MODE_RDCH : INTEGER;
C_REG_SLICE_MODE_AXIS : INTEGER
);
PORT (
backup : IN STD_LOGIC;
backup_marker : IN STD_LOGIC;
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
srst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
prog_full_thresh_assert : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
prog_full_thresh_negate : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
int_clk : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
injectsbiterr : IN STD_LOGIC;
sleep : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
wr_ack : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
rd_data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
wr_data_count : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
wr_rst_busy : OUT STD_LOGIC;
rd_rst_busy : OUT STD_LOGIC;
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
m_aclk_en : IN STD_LOGIC;
s_aclk_en : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awvalid : OUT STD_LOGIC;
m_axi_awready : IN STD_LOGIC;
m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_wlast : OUT STD_LOGIC;
m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wvalid : OUT STD_LOGIC;
m_axi_wready : IN STD_LOGIC;
m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bvalid : IN STD_LOGIC;
m_axi_bready : OUT STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arvalid : OUT STD_LOGIC;
m_axi_arready : IN STD_LOGIC;
m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_rlast : IN STD_LOGIC;
m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rvalid : IN STD_LOGIC;
m_axi_rready : OUT STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tstrb : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_injectsbiterr : IN STD_LOGIC;
axi_aw_injectdbiterr : IN STD_LOGIC;
axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_sbiterr : OUT STD_LOGIC;
axi_aw_dbiterr : OUT STD_LOGIC;
axi_aw_overflow : OUT STD_LOGIC;
axi_aw_underflow : OUT STD_LOGIC;
axi_aw_prog_full : OUT STD_LOGIC;
axi_aw_prog_empty : OUT STD_LOGIC;
axi_w_injectsbiterr : IN STD_LOGIC;
axi_w_injectdbiterr : IN STD_LOGIC;
axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_sbiterr : OUT STD_LOGIC;
axi_w_dbiterr : OUT STD_LOGIC;
axi_w_overflow : OUT STD_LOGIC;
axi_w_underflow : OUT STD_LOGIC;
axi_w_prog_full : OUT STD_LOGIC;
axi_w_prog_empty : OUT STD_LOGIC;
axi_b_injectsbiterr : IN STD_LOGIC;
axi_b_injectdbiterr : IN STD_LOGIC;
axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_sbiterr : OUT STD_LOGIC;
axi_b_dbiterr : OUT STD_LOGIC;
axi_b_overflow : OUT STD_LOGIC;
axi_b_underflow : OUT STD_LOGIC;
axi_b_prog_full : OUT STD_LOGIC;
axi_b_prog_empty : OUT STD_LOGIC;
axi_ar_injectsbiterr : IN STD_LOGIC;
axi_ar_injectdbiterr : IN STD_LOGIC;
axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_sbiterr : OUT STD_LOGIC;
axi_ar_dbiterr : OUT STD_LOGIC;
axi_ar_overflow : OUT STD_LOGIC;
axi_ar_underflow : OUT STD_LOGIC;
axi_ar_prog_full : OUT STD_LOGIC;
axi_ar_prog_empty : OUT STD_LOGIC;
axi_r_injectsbiterr : IN STD_LOGIC;
axi_r_injectdbiterr : IN STD_LOGIC;
axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_sbiterr : OUT STD_LOGIC;
axi_r_dbiterr : OUT STD_LOGIC;
axi_r_overflow : OUT STD_LOGIC;
axi_r_underflow : OUT STD_LOGIC;
axi_r_prog_full : OUT STD_LOGIC;
axi_r_prog_empty : OUT STD_LOGIC;
axis_injectsbiterr : IN STD_LOGIC;
axis_injectdbiterr : IN STD_LOGIC;
axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_sbiterr : OUT STD_LOGIC;
axis_dbiterr : OUT STD_LOGIC;
axis_overflow : OUT STD_LOGIC;
axis_underflow : OUT STD_LOGIC;
axis_prog_full : OUT STD_LOGIC;
axis_prog_empty : OUT STD_LOGIC
);
END COMPONENT fifo_generator_v13_0_1;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF wr_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 write_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF rd_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 read_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF din: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA";
ATTRIBUTE X_INTERFACE_INFO OF wr_en: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN";
ATTRIBUTE X_INTERFACE_INFO OF rd_en: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN";
ATTRIBUTE X_INTERFACE_INFO OF dout: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA";
ATTRIBUTE X_INTERFACE_INFO OF full: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL";
ATTRIBUTE X_INTERFACE_INFO OF empty: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY";
BEGIN
U0 : fifo_generator_v13_0_1
GENERIC MAP (
C_COMMON_CLOCK => 0,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => 12,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => 8,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => 32,
C_ENABLE_RLOCS => 0,
C_FAMILY => "kintex7",
C_FULL_FLAGS_RST_VAL => 1,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => 0,
C_HAS_RD_DATA_COUNT => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_HAS_UNDERFLOW => 0,
C_HAS_VALID => 1,
C_HAS_WR_ACK => 0,
C_HAS_WR_DATA_COUNT => 0,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => 2,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => 1,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => 1,
C_PRELOAD_REGS => 0,
C_PRIM_FIFO_TYPE => "4kx9",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 4093,
C_PROG_FULL_THRESH_NEGATE_VAL => 4092,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => 10,
C_RD_DEPTH => 1024,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => 10,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => 0,
C_USE_PIPELINE_REG => 0,
C_POWER_SAVING_MODE => 0,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => 12,
C_WR_DEPTH => 4096,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => 12,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_EN_SAFETY_CKT => 0,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => 2,
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_HAS_AXI_WR_CHANNEL => 1,
C_HAS_AXI_RD_CHANNEL => 1,
C_HAS_SLAVE_CE => 0,
C_HAS_MASTER_CE => 0,
C_ADD_NGC_CONSTRAINT => 0,
C_USE_COMMON_OVERFLOW => 0,
C_USE_COMMON_UNDERFLOW => 0,
C_USE_DEFAULT_SETTINGS => 0,
C_AXI_ID_WIDTH => 1,
C_AXI_ADDR_WIDTH => 32,
C_AXI_DATA_WIDTH => 64,
C_AXI_LEN_WIDTH => 8,
C_AXI_LOCK_WIDTH => 1,
C_HAS_AXI_ID => 0,
C_HAS_AXI_AWUSER => 0,
C_HAS_AXI_WUSER => 0,
C_HAS_AXI_BUSER => 0,
C_HAS_AXI_ARUSER => 0,
C_HAS_AXI_RUSER => 0,
C_AXI_ARUSER_WIDTH => 1,
C_AXI_AWUSER_WIDTH => 1,
C_AXI_WUSER_WIDTH => 1,
C_AXI_BUSER_WIDTH => 1,
C_AXI_RUSER_WIDTH => 1,
C_HAS_AXIS_TDATA => 1,
C_HAS_AXIS_TID => 0,
C_HAS_AXIS_TDEST => 0,
C_HAS_AXIS_TUSER => 1,
C_HAS_AXIS_TREADY => 1,
C_HAS_AXIS_TLAST => 0,
C_HAS_AXIS_TSTRB => 0,
C_HAS_AXIS_TKEEP => 0,
C_AXIS_TDATA_WIDTH => 8,
C_AXIS_TID_WIDTH => 1,
C_AXIS_TDEST_WIDTH => 1,
C_AXIS_TUSER_WIDTH => 4,
C_AXIS_TSTRB_WIDTH => 1,
C_AXIS_TKEEP_WIDTH => 1,
C_WACH_TYPE => 0,
C_WDCH_TYPE => 0,
C_WRCH_TYPE => 0,
C_RACH_TYPE => 0,
C_RDCH_TYPE => 0,
C_AXIS_TYPE => 0,
C_IMPLEMENTATION_TYPE_WACH => 1,
C_IMPLEMENTATION_TYPE_WDCH => 1,
C_IMPLEMENTATION_TYPE_WRCH => 1,
C_IMPLEMENTATION_TYPE_RACH => 1,
C_IMPLEMENTATION_TYPE_RDCH => 1,
C_IMPLEMENTATION_TYPE_AXIS => 1,
C_APPLICATION_TYPE_WACH => 0,
C_APPLICATION_TYPE_WDCH => 0,
C_APPLICATION_TYPE_WRCH => 0,
C_APPLICATION_TYPE_RACH => 0,
C_APPLICATION_TYPE_RDCH => 0,
C_APPLICATION_TYPE_AXIS => 0,
C_PRIM_FIFO_TYPE_WACH => "512x36",
C_PRIM_FIFO_TYPE_WDCH => "1kx36",
C_PRIM_FIFO_TYPE_WRCH => "512x36",
C_PRIM_FIFO_TYPE_RACH => "512x36",
C_PRIM_FIFO_TYPE_RDCH => "1kx36",
C_PRIM_FIFO_TYPE_AXIS => "1kx18",
C_USE_ECC_WACH => 0,
C_USE_ECC_WDCH => 0,
C_USE_ECC_WRCH => 0,
C_USE_ECC_RACH => 0,
C_USE_ECC_RDCH => 0,
C_USE_ECC_AXIS => 0,
C_ERROR_INJECTION_TYPE_WACH => 0,
C_ERROR_INJECTION_TYPE_WDCH => 0,
C_ERROR_INJECTION_TYPE_WRCH => 0,
C_ERROR_INJECTION_TYPE_RACH => 0,
C_ERROR_INJECTION_TYPE_RDCH => 0,
C_ERROR_INJECTION_TYPE_AXIS => 0,
C_DIN_WIDTH_WACH => 32,
C_DIN_WIDTH_WDCH => 64,
C_DIN_WIDTH_WRCH => 2,
C_DIN_WIDTH_RACH => 32,
C_DIN_WIDTH_RDCH => 64,
C_DIN_WIDTH_AXIS => 1,
C_WR_DEPTH_WACH => 16,
C_WR_DEPTH_WDCH => 1024,
C_WR_DEPTH_WRCH => 16,
C_WR_DEPTH_RACH => 16,
C_WR_DEPTH_RDCH => 1024,
C_WR_DEPTH_AXIS => 1024,
C_WR_PNTR_WIDTH_WACH => 4,
C_WR_PNTR_WIDTH_WDCH => 10,
C_WR_PNTR_WIDTH_WRCH => 4,
C_WR_PNTR_WIDTH_RACH => 4,
C_WR_PNTR_WIDTH_RDCH => 10,
C_WR_PNTR_WIDTH_AXIS => 10,
C_HAS_DATA_COUNTS_WACH => 0,
C_HAS_DATA_COUNTS_WDCH => 0,
C_HAS_DATA_COUNTS_WRCH => 0,
C_HAS_DATA_COUNTS_RACH => 0,
C_HAS_DATA_COUNTS_RDCH => 0,
C_HAS_DATA_COUNTS_AXIS => 0,
C_HAS_PROG_FLAGS_WACH => 0,
C_HAS_PROG_FLAGS_WDCH => 0,
C_HAS_PROG_FLAGS_WRCH => 0,
C_HAS_PROG_FLAGS_RACH => 0,
C_HAS_PROG_FLAGS_RDCH => 0,
C_HAS_PROG_FLAGS_AXIS => 0,
C_PROG_FULL_TYPE_WACH => 0,
C_PROG_FULL_TYPE_WDCH => 0,
C_PROG_FULL_TYPE_WRCH => 0,
C_PROG_FULL_TYPE_RACH => 0,
C_PROG_FULL_TYPE_RDCH => 0,
C_PROG_FULL_TYPE_AXIS => 0,
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023,
C_PROG_EMPTY_TYPE_WACH => 0,
C_PROG_EMPTY_TYPE_WDCH => 0,
C_PROG_EMPTY_TYPE_WRCH => 0,
C_PROG_EMPTY_TYPE_RACH => 0,
C_PROG_EMPTY_TYPE_RDCH => 0,
C_PROG_EMPTY_TYPE_AXIS => 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022,
C_REG_SLICE_MODE_WACH => 0,
C_REG_SLICE_MODE_WDCH => 0,
C_REG_SLICE_MODE_WRCH => 0,
C_REG_SLICE_MODE_RACH => 0,
C_REG_SLICE_MODE_RDCH => 0,
C_REG_SLICE_MODE_AXIS => 0
)
PORT MAP (
backup => '0',
backup_marker => '0',
clk => '0',
rst => rst,
srst => '0',
wr_clk => wr_clk,
wr_rst => '0',
rd_clk => rd_clk,
rd_rst => '0',
din => din,
wr_en => wr_en,
rd_en => rd_en,
prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
int_clk => '0',
injectdbiterr => '0',
injectsbiterr => '0',
sleep => '0',
dout => dout,
full => full,
empty => empty,
valid => valid,
m_aclk => '0',
s_aclk => '0',
s_aresetn => '0',
m_aclk_en => '0',
s_aclk_en => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awvalid => '0',
s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wlast => '0',
s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wvalid => '0',
s_axi_bready => '0',
m_axi_awready => '0',
m_axi_wready => '0',
m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bvalid => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arvalid => '0',
s_axi_rready => '0',
m_axi_arready => '0',
m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_rlast => '0',
m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rvalid => '0',
s_axis_tvalid => '0',
s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tlast => '0',
s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
m_axis_tready => '0',
axi_aw_injectsbiterr => '0',
axi_aw_injectdbiterr => '0',
axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_w_injectsbiterr => '0',
axi_w_injectdbiterr => '0',
axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_b_injectsbiterr => '0',
axi_b_injectdbiterr => '0',
axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_injectsbiterr => '0',
axi_ar_injectdbiterr => '0',
axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_r_injectsbiterr => '0',
axi_r_injectdbiterr => '0',
axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_injectsbiterr => '0',
axis_injectdbiterr => '0',
axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10))
);
END fifo_generator_input_buffer_arch;
|
bsd-3-clause
|
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/Pmods/PmodNAV_v1_0/ipshared/xilinx.com/axi_quad_spi_v3_2/hdl/src/vhdl/counter_f.vhd
|
3
|
10385
|
-------------------------------------------------------------------------------
-- counter_f - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2006-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: counter_f.vhd
--
-- Description: Implements a parameterizable N-bit counter_f
-- Up/Down Counter
-- Count Enable
-- Parallel Load
-- Synchronous Reset
-- The structural implementation has incremental cost
-- of one LUT per bit.
-- Precedence of operations when simultaneous:
-- reset, load, count
--
-- A default inferred-RTL implementation is provided and
-- is used if the user explicitly specifies C_FAMILY=nofamily
-- or ommits C_FAMILY (allowing it to default to nofamily).
-- The default implementation is also used
-- if needed primitives are not available in FPGAs of the
-- type given by C_FAMILY.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.unsigned;
use IEEE.numeric_std."+";
use IEEE.numeric_std."-";
library unisim;
use unisim.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity counter_f is
generic(
C_NUM_BITS : integer := 9;
C_FAMILY : string := "nofamily"
);
port(
Clk : in std_logic;
Rst : in std_logic;
Load_In : in std_logic_vector(C_NUM_BITS - 1 downto 0);
Count_Enable : in std_logic;
Count_Load : in std_logic;
Count_Down : in std_logic;
Count_Out : out std_logic_vector(C_NUM_BITS - 1 downto 0);
Carry_Out : out std_logic
);
end entity counter_f;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of counter_f is
---------------------------------------------------------------------
-- Component declarations
---------------------------------------------------------------------
component MUXCY_L is
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
LO : out std_logic);
end component MUXCY_L;
component XORCY is
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component XORCY;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDRE;
signal icount_out : unsigned(C_NUM_BITS downto 0);
signal icount_out_x : unsigned(C_NUM_BITS downto 0);
signal load_in_x : unsigned(C_NUM_BITS downto 0);
---------------------------------------------------------------------
-- Constant declarations
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------
begin
---------------------------------------------------------------------
-- Generate Inferred code
---------------------------------------------------------------------
--INFERRED_GEN : if USE_INFERRED generate
load_in_x <= unsigned('0' & Load_In);
-- Mask out carry position to retain legacy self-clear on next enable.
-- icount_out_x <= ('0' & icount_out(C_NUM_BITS-1 downto 0)); -- Echeck WA
icount_out_x <= unsigned('0' & std_logic_vector(icount_out(C_NUM_BITS-1 downto 0)));
-----------------------------------------------------------------
-- Process to generate counter with - synchronous reset, load,
-- counter enable, count down / up features.
-----------------------------------------------------------------
CNTR_PROC : process(Clk)
begin
if Clk'event and Clk = '1' then
if Rst = '1' then
icount_out <= (others => '0');
elsif Count_Load = '1' then
icount_out <= load_in_x;
elsif Count_Down = '1' and Count_Enable = '1' then
icount_out <= icount_out_x - 1;
elsif Count_Enable = '1' then
icount_out <= icount_out_x + 1;
end if;
end if;
end process CNTR_PROC;
Carry_Out <= icount_out(C_NUM_BITS);
Count_Out <= std_logic_vector(icount_out(C_NUM_BITS-1 downto 0));
end architecture imp;
---------------------------------------------------------------
-- End of file counter_f.vhd
---------------------------------------------------------------
|
bsd-3-clause
|
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/usb2device_v1_0/src/axi_dma_0/axi_sg_v4_1_2/hdl/src/vhdl/axi_sg_updt_queue.vhd
|
7
|
53326
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_updt_queue.vhd
-- Description: This entity is the descriptor fetch queue interface
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library axi_sg_v4_1_2;
use axi_sg_v4_1_2.axi_sg_pkg.all;
library lib_srl_fifo_v1_0_2;
use lib_srl_fifo_v1_0_2.srl_fifo_f;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_updt_queue is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_M_AXIS_UPDT_DATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Memory Map Data Width for Scatter Gather R/W Port
C_S_AXIS_UPDPTR_TDATA_WIDTH : integer range 32 to 32 := 32;
-- 32 Update Status Bits
C_S_AXIS_UPDSTS_TDATA_WIDTH : integer range 33 to 33 := 33;
-- 1 IOC bit + 32 Update Status Bits
C_SG_UPDT_DESC2QUEUE : integer range 0 to 8 := 0;
-- Number of descriptors to fetch and queue for each channel.
-- A value of zero excludes the fetch queues.
C_SG_WORDS_TO_UPDATE : integer range 1 to 16 := 8;
-- Number of words to update
C_SG2_WORDS_TO_UPDATE : integer range 1 to 16 := 8;
-- Number of words to update
C_AXIS_IS_ASYNC : integer range 0 to 1 := 0;
-- Channel 1 is async to sg_aclk
-- 0 = Synchronous to SG ACLK
-- 1 = Asynchronous to SG ACLK
C_INCLUDE_MM2S : integer range 0 to 1 := 0;
C_INCLUDE_S2MM : integer range 0 to 1 := 0;
C_FAMILY : string := "virtex7"
-- Device family used for proper BRAM selection
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
s_axis_updt_aclk : in std_logic ; --
--
--********************************-- --
--** Control and Status **-- --
--********************************-- --
updt_curdesc_wren : out std_logic ; --
updt_curdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
updt_active : in std_logic ; --
updt_queue_empty : out std_logic ; --
updt_ioc : out std_logic ; --
updt_ioc_irq_set : in std_logic ; --
--
dma_interr : out std_logic ; --
dma_slverr : out std_logic ; --
dma_decerr : out std_logic ; --
dma_interr_set : in std_logic ; --
dma_slverr_set : in std_logic ; --
dma_decerr_set : in std_logic ; --
updt2_active : in std_logic ; --
updt2_queue_empty : out std_logic ; --
updt2_ioc : out std_logic ; --
updt2_ioc_irq_set : in std_logic ; --
--
dma2_interr : out std_logic ; --
dma2_slverr : out std_logic ; --
dma2_decerr : out std_logic ; --
dma2_interr_set : in std_logic ; --
dma2_slverr_set : in std_logic ; --
dma2_decerr_set : in std_logic ; --
--
--********************************-- --
--** Update Interfaces In **-- --
--********************************-- --
-- Update Pointer Stream --
s_axis_updtptr_tdata : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
s_axis_updtptr_tvalid : in std_logic ; --
s_axis_updtptr_tready : out std_logic ; --
s_axis_updtptr_tlast : in std_logic ; --
--
-- Update Status Stream --
s_axis_updtsts_tdata : in std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); --
s_axis_updtsts_tvalid : in std_logic ; --
s_axis_updtsts_tready : out std_logic ; --
s_axis_updtsts_tlast : in std_logic ; --
s_axis2_updtptr_tdata : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
s_axis2_updtptr_tvalid : in std_logic ; --
s_axis2_updtptr_tready : out std_logic ; --
s_axis2_updtptr_tlast : in std_logic ; --
--
-- Update Status Stream --
s_axis2_updtsts_tdata : in std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); --
s_axis2_updtsts_tvalid : in std_logic ; --
s_axis2_updtsts_tready : out std_logic ; --
s_axis2_updtsts_tlast : in std_logic ; --
--
--********************************-- --
--** Update Interfaces Out **-- --
--********************************-- --
-- S2MM Stream Out To DataMover --
m_axis_updt_tdata : out std_logic_vector --
(C_M_AXIS_UPDT_DATA_WIDTH-1 downto 0); --
m_axis_updt_tlast : out std_logic ; --
m_axis_updt_tvalid : out std_logic ; --
m_axis_updt_tready : in std_logic --
);
end axi_sg_updt_queue;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_updt_queue is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
constant USE_LOGIC_FIFOS : integer := 0; -- Use Logic FIFOs
constant USE_BRAM_FIFOS : integer := 1; -- Use BRAM FIFOs
-- Number of words deep fifo needs to be. Depth required to store 2 word
-- porters for each descriptor is C_SG_UPDT_DESC2QUEUE x 2
--constant UPDATE_QUEUE_DEPTH : integer := max2(16,C_SG_UPDT_DESC2QUEUE * 2);
constant UPDATE_QUEUE_DEPTH : integer := max2(16,pad_power2(C_SG_UPDT_DESC2QUEUE * 2));
-- Width of fifo rd and wr counts - only used for proper fifo operation
constant UPDATE_QUEUE_CNT_WIDTH : integer := clog2(UPDATE_QUEUE_DEPTH+1);
-- Select between BRAM or LOGIC memory type
constant UPD_Q_MEMORY_TYPE : integer := bo2int(UPDATE_QUEUE_DEPTH > 16);
-- Number of words deep fifo needs to be. Depth required to store all update
-- words is C_SG_UPDT_DESC2QUEUE x C_SG_WORDS_TO_UPDATE
constant UPDATE_STS_QUEUE_DEPTH : integer := max2(16,pad_power2(C_SG_UPDT_DESC2QUEUE
* C_SG_WORDS_TO_UPDATE));
constant UPDATE_STS2_QUEUE_DEPTH : integer := max2(16,pad_power2(C_SG_UPDT_DESC2QUEUE
* C_SG2_WORDS_TO_UPDATE));
-- Select between BRAM or LOGIC memory type
constant STS_Q_MEMORY_TYPE : integer := bo2int(UPDATE_STS_QUEUE_DEPTH > 16);
-- Select between BRAM or LOGIC memory type
constant STS2_Q_MEMORY_TYPE : integer := bo2int(UPDATE_STS2_QUEUE_DEPTH > 16);
-- Width of fifo rd and wr counts - only used for proper fifo operation
constant UPDATE_STS_QUEUE_CNT_WIDTH : integer := clog2(C_SG_UPDT_DESC2QUEUE+1);
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- Channel signals
signal write_curdesc_lsb : std_logic := '0';
signal write_curdesc_lsb_sm : std_logic := '0';
signal write_curdesc_msb : std_logic := '0';
signal write_curdesc_lsb1 : std_logic := '0';
signal write_curdesc_msb1 : std_logic := '0';
signal rden_del : std_logic := '0';
signal updt_active_d1 : std_logic := '0';
signal updt_active_d2 : std_logic := '0';
signal updt_active_re1 : std_logic := '0';
signal updt_active_re2 : std_logic := '0';
signal updt_active_re : std_logic := '0';
type PNTR_STATE_TYPE is (IDLE,
READ_CURDESC_LSB,
READ_CURDESC_MSB,
WRITE_STATUS
);
signal pntr_cs : PNTR_STATE_TYPE;
signal pntr_ns : PNTR_STATE_TYPE;
-- State Machine Signal
signal writing_status : std_logic := '0';
signal dataq_rden : std_logic := '0';
signal stsq_rden : std_logic := '0';
-- Pointer Queue FIFO Signals
signal ptr_queue_rden : std_logic := '0';
signal ptr_queue_wren : std_logic := '0';
signal ptr_queue_empty : std_logic := '0';
signal ptr_queue_full : std_logic := '0';
signal ptr_queue_din : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal ptr_queue_dout : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal ptr_queue_dout_int : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
-- Status Queue FIFO Signals
signal sts_queue_wren : std_logic := '0';
signal sts_queue_rden : std_logic := '0';
signal sts_queue_din : std_logic_vector
(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal sts_queue_dout : std_logic_vector
(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal sts_queue_dout_int : std_logic_vector (3 downto 0) := (others => '0');
signal sts_queue_full : std_logic := '0';
signal sts_queue_empty : std_logic := '0';
signal ptr2_queue_rden : std_logic := '0';
signal ptr2_queue_wren : std_logic := '0';
signal ptr2_queue_empty : std_logic := '0';
signal ptr2_queue_full : std_logic := '0';
signal ptr2_queue_din : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal ptr2_queue_dout : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
-- Status Queue FIFO Signals
signal sts2_queue_wren : std_logic := '0';
signal sts2_queue_rden : std_logic := '0';
signal sts2_queue_din : std_logic_vector
(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal sts2_queue_dout : std_logic_vector
(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal sts2_queue_full : std_logic := '0';
signal sts2_queue_empty : std_logic := '0';
signal sts2_queue_empty_del : std_logic := '0';
signal sts2_dout_valid : std_logic := '0';
signal sts_dout_valid : std_logic := '0';
signal sts2_dout_valid_del : std_logic := '0';
signal valid_new : std_logic := '0';
signal valid_latch : std_logic := '0';
signal valid1_new : std_logic := '0';
signal valid1_latch : std_logic := '0';
signal empty_low : std_logic := '0';
-- Misc Support Signals
signal writing_status_d1 : std_logic := '0';
signal writing_status_re : std_logic := '0';
signal writing_status_re_ch1 : std_logic := '0';
signal writing_status_re_ch2 : std_logic := '0';
signal sinit : std_logic := '0';
signal updt_tvalid : std_logic := '0';
signal updt_tlast : std_logic := '0';
signal updt2_tvalid : std_logic := '0';
signal updt2_tlast : std_logic := '0';
signal status_d1, status_d2 : std_logic := '0';
signal updt_tvalid_int : std_logic := '0';
signal updt_tlast_int : std_logic := '0';
signal ptr_queue_empty_int : std_logic := '0';
signal updt_active_int : std_logic := '0';
signal follower_reg_mm2s : std_logic_vector (33 downto 0) := (others => '0');
signal follower_full_mm2s :std_logic := '0';
signal follower_empty_mm2s : std_logic := '0';
signal follower_reg_s2mm : std_logic_vector (33 downto 0) := (others => '0');
signal follower_full_s2mm :std_logic := '0';
signal follower_empty_s2mm : std_logic := '0';
signal follower_reg, m_axis_updt_tdata_tmp : std_logic_vector (33 downto 0);
signal follower_full :std_logic := '0';
signal follower_empty : std_logic := '0';
signal sts_rden : std_logic := '0';
signal sts2_rden : std_logic := '0';
signal follower_tlast : std_logic := '0';
signal follower_reg_image : std_logic := '0';
signal m_axis_updt_tready_mm2s, m_axis_updt_tready_s2mm : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
m_axis_updt_tdata <= follower_reg_mm2s (C_S_AXIS_UPDSTS_TDATA_WIDTH-2 downto 0) when updt_active = '1'
else follower_reg_s2mm (C_S_AXIS_UPDSTS_TDATA_WIDTH-2 downto 0) ;
m_axis_updt_tvalid <= updt_tvalid when updt_active = '1'
else updt2_tvalid;
m_axis_updt_tlast <= updt_tlast when updt_active = '1'
else updt2_tlast;
m_axis_updt_tready_mm2s <= m_axis_updt_tready when updt_active = '1' else '0';
m_axis_updt_tready_s2mm <= m_axis_updt_tready when updt2_active = '1' else '0';
-- Asset active strobe on rising edge of update active
-- asertion. This kicks off the update process for
-- channel 1
updt_active_re <= updt_active_re1 or updt_active_re2;
-- Current Descriptor Pointer Fetch. This state machine controls
-- reading out the current pointer from the Queue or channel port
-- and writing it to the update manager for use in command
-- generation to the DataMover for Descriptor update.
CURDESC_PNTR_STATE : process(pntr_cs,
updt_active_re,
ptr_queue_empty_int,
m_axis_updt_tready,
updt_tvalid_int,
updt_tlast_int)
begin
write_curdesc_lsb_sm <= '0';
write_curdesc_msb <= '0';
writing_status <= '0';
dataq_rden <= '0';
stsq_rden <= '0';
pntr_ns <= pntr_cs;
case pntr_cs is
when IDLE =>
if(updt_active_re = '1')then
pntr_ns <= READ_CURDESC_LSB;
else
pntr_ns <= IDLE;
end if;
---------------------------------------------------------------
-- Get lower current descriptor pointer
-- Reads one word from data queue fifo
---------------------------------------------------------------
when READ_CURDESC_LSB =>
-- on tvalid from Queue or channel port then register
-- lsb curdesc and setup to register msb curdesc
if(ptr_queue_empty_int = '0')then
write_curdesc_lsb_sm <= '1';
dataq_rden <= '1';
-- pntr_ns <= READ_CURDESC_MSB;
pntr_ns <= WRITE_STATUS; --READ_CURDESC_MSB;
else
-- coverage off
pntr_ns <= READ_CURDESC_LSB;
-- coverage on
end if;
---------------------------------------------------------------
-- Get upper current descriptor
-- Reads one word from data queue fifo
---------------------------------------------------------------
-- when READ_CURDESC_MSB =>
-- On tvalid from Queue or channel port then register
-- msb. This will also write curdesc out to update
-- manager.
-- if(ptr_queue_empty_int = '0')then
-- dataq_rden <= '1';
-- write_curdesc_msb <= '1';
-- pntr_ns <= WRITE_STATUS;
-- else
-- -- coverage off
-- pntr_ns <= READ_CURDESC_MSB;
-- -- coverage on
-- end if;
---------------------------------------------------------------
-- Hold in this state until remainder of descriptor is
-- written out.
when WRITE_STATUS =>
-- De-MUX appropriage tvalid/tlast signals
writing_status <= '1';
-- Enable reading of Status Queue if datamover can
-- accept data
stsq_rden <= m_axis_updt_tready;
-- Hold in the status state until tlast is pulled
-- from status fifo
if(updt_tvalid_int = '1' and m_axis_updt_tready = '1'
and updt_tlast_int = '1')then
-- if(follower_full = '1' and m_axis_updt_tready = '1'
-- and follower_tlast = '1')then
pntr_ns <= IDLE;
else
pntr_ns <= WRITE_STATUS;
end if;
-- coverage off
when others =>
pntr_ns <= IDLE;
-- coverage on
end case;
end process CURDESC_PNTR_STATE;
updt_tvalid_int <= updt_tvalid or updt2_tvalid;
updt_tlast_int <= updt_tlast or updt2_tlast;
ptr_queue_empty_int <= ptr_queue_empty when updt_active = '1' else
ptr2_queue_empty when updt2_active = '1' else
'1';
---------------------------------------------------------------------------
-- Register for CURDESC Pointer state machine
---------------------------------------------------------------------------
REG_PNTR_STATES : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
pntr_cs <= IDLE;
else
pntr_cs <= pntr_ns;
end if;
end if;
end process REG_PNTR_STATES;
GEN_Q_FOR_SYNC : if C_AXIS_IS_ASYNC = 0 generate
begin
MM2S_CHANNEL : if C_INCLUDE_MM2S = 1 generate
updt_tvalid <= follower_full_mm2s and updt_active;
updt_tlast <= follower_reg_mm2s(C_S_AXIS_UPDSTS_TDATA_WIDTH) and updt_active;
sts_rden <= follower_empty_mm2s and (not sts_queue_empty); -- and updt_active;
VALID_REG_MM2S_ACTIVE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or (m_axis_updt_tready_mm2s = '1' and follower_full_mm2s = '1'))then
-- follower_reg_mm2s <= (others => '0');
follower_full_mm2s <= '0';
follower_empty_mm2s <= '1';
else
if (sts_rden = '1') then
-- follower_reg_mm2s <= sts_queue_dout;
follower_full_mm2s <= '1';
follower_empty_mm2s <= '0';
end if;
end if;
end if;
end process VALID_REG_MM2S_ACTIVE;
VALID_REG_MM2S_ACTIVE1 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
follower_reg_mm2s <= (others => '0');
else
if (sts_rden = '1') then
follower_reg_mm2s <= sts_queue_dout;
end if;
end if;
end if;
end process VALID_REG_MM2S_ACTIVE1;
REG_ACTIVE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
updt_active_d1 <= '0';
else
updt_active_d1 <= updt_active;
end if;
end if;
end process REG_ACTIVE;
updt_active_re1 <= updt_active and not updt_active_d1;
-- I_UPDT_DATA_FIFO : entity lib_srl_fifo_v1_0_2.srl_fifo_f
-- generic map (
-- C_DWIDTH => 32 ,
-- C_DEPTH => 8 ,
-- C_FAMILY => C_FAMILY
-- )
-- port map (
-- Clk => m_axi_sg_aclk ,
-- Reset => sinit ,
-- FIFO_Write => ptr_queue_wren ,
-- Data_In => ptr_queue_din ,
-- FIFO_Read => ptr_queue_rden ,
-- Data_Out => ptr_queue_dout ,
-- FIFO_Empty => ptr_queue_empty ,
-- FIFO_Full => ptr_queue_full,
-- Addr => open
-- );
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (sinit = '1') then
ptr_queue_dout <= (others => '0');
elsif (ptr_queue_wren = '1') then
ptr_queue_dout <= ptr_queue_din;
end if;
end if;
end process;
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (sinit = '1' or ptr_queue_rden = '1') then
ptr_queue_empty <= '1';
ptr_queue_full <= '0';
elsif (ptr_queue_wren = '1') then
ptr_queue_empty <= '0';
ptr_queue_full <= '1';
end if;
end if;
end process;
-- Channel Pointer Queue (Generate Synchronous FIFO)
-- I_UPDT_STS_FIFO : entity lib_srl_fifo_v1_0_2.srl_fifo_f
-- generic map (
-- C_DWIDTH => 34 ,
-- C_DEPTH => 4 ,
-- C_FAMILY => C_FAMILY
-- )
-- port map (
-- Clk => m_axi_sg_aclk ,
-- Reset => sinit ,
-- FIFO_Write => sts_queue_wren ,
-- Data_In => sts_queue_din ,
-- FIFO_Read => sts_rden, --sts_queue_rden ,
-- Data_Out => sts_queue_dout ,
-- FIFO_Empty => sts_queue_empty ,
-- FIFO_Full => sts_queue_full ,
-- Addr => open
-- );
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (sinit = '1') then
sts_queue_dout <= (others => '0');
elsif (sts_queue_wren = '1') then
sts_queue_dout <= sts_queue_din;
end if;
end if;
end process;
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (sinit = '1' or sts_rden = '1') then
sts_queue_empty <= '1';
sts_queue_full <= '0';
elsif (sts_queue_wren = '1') then
sts_queue_empty <= '0';
sts_queue_full <= '1';
end if;
end if;
end process;
-- Channel Status Queue (Generate Synchronous FIFO)
--*****************************************
--** Channel Data Port Side of Queues
--*****************************************
-- Pointer Queue Update - Descriptor Pointer (32bits)
-- i.e. 2 current descriptor pointers and any app fields
ptr_queue_din(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) <= s_axis_updtptr_tdata( -- DESC DATA
C_M_AXI_SG_ADDR_WIDTH-1
downto 0);
-- Data Queue Write Enable - based on tvalid and queue not full
ptr_queue_wren <= s_axis_updtptr_tvalid -- TValid
and not ptr_queue_full; -- Data Queue NOT Full
-- Drive channel port with ready if room in data queue
s_axis_updtptr_tready <= not ptr_queue_full;
--*****************************************
--** Channel Status Port Side of Queues
--*****************************************
-- Status Queue Update - TLAST(1bit) & Includes IOC(1bit) & Descriptor Status(32bits)
-- Note: Type field is stripped off
sts_queue_din(C_S_AXIS_UPDSTS_TDATA_WIDTH) <= s_axis_updtsts_tlast; -- Store with tlast
sts_queue_din(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0) <= s_axis_updtsts_tdata( -- IOC & DESC STS
C_S_AXIS_UPDSTS_TDATA_WIDTH-1
downto 0);
-- Status Queue Write Enable - based on tvalid and queue not full
sts_queue_wren <= s_axis_updtsts_tvalid
and not sts_queue_full;
-- Drive channel port with ready if room in status queue
s_axis_updtsts_tready <= not sts_queue_full;
--*************************************
--** SG Engine Side of Queues
--*************************************
-- Indicate NOT empty if both status queue and data queue are not empty
-- updt_queue_empty <= ptr_queue_empty
-- or (sts_queue_empty and follower_empty and updt_active);
updt_queue_empty <= ptr_queue_empty
or follower_empty_mm2s; -- and updt_active);
-- Data queue read enable
ptr_queue_rden <= '1' when dataq_rden = '1' -- Cur desc read enable
and ptr_queue_empty = '0' -- Data Queue NOT empty
and updt_active = '1'
else '0';
-- Status queue read enable
sts_queue_rden <= '1' when stsq_rden = '1' -- Writing desc status
and sts_queue_empty = '0' -- Status fifo NOT empty
and updt_active = '1'
else '0';
-----------------------------------------------------------------------
-- TVALID - status queue not empty and writing status
-----------------------------------------------------------------------
-----------------------------------------------------------------------
-- TLAST - status queue not empty, writing status, and last asserted
-----------------------------------------------------------------------
-- Drive last as long as tvalid is asserted and last from fifo
-- is asserted
end generate MM2S_CHANNEL;
NO_MM2S_CHANNEL : if C_INCLUDE_MM2S = 0 generate
begin
updt_active_re1 <= '0';
updt_queue_empty <= '0';
s_axis_updtptr_tready <= '0';
s_axis_updtsts_tready <= '0';
sts_queue_dout <= (others => '0');
sts_queue_full <= '0';
sts_queue_empty <= '0';
ptr_queue_dout <= (others => '0');
ptr_queue_empty <= '0';
ptr_queue_full <= '0';
end generate NO_MM2S_CHANNEL;
S2MM_CHANNEL : if C_INCLUDE_S2MM = 1 generate
begin
updt2_tvalid <= follower_full_s2mm and updt2_active;
updt2_tlast <= follower_reg_s2mm(C_S_AXIS_UPDSTS_TDATA_WIDTH) and updt2_active;
sts2_rden <= follower_empty_s2mm and (not sts2_queue_empty); -- and updt2_active;
VALID_REG_S2MM_ACTIVE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or (m_axis_updt_tready_s2mm = '1' and follower_full_s2mm = '1'))then
-- follower_reg_s2mm <= (others => '0');
follower_full_s2mm <= '0';
follower_empty_s2mm <= '1';
else
if (sts2_rden = '1') then
-- follower_reg_s2mm <= sts2_queue_dout;
follower_full_s2mm <= '1';
follower_empty_s2mm <= '0';
end if;
end if;
end if;
end process VALID_REG_S2MM_ACTIVE;
VALID_REG_S2MM_ACTIVE1 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
follower_reg_s2mm <= (others => '0');
else
if (sts2_rden = '1') then
follower_reg_s2mm <= sts2_queue_dout;
end if;
end if;
end if;
end process VALID_REG_S2MM_ACTIVE1;
REG2_ACTIVE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
updt_active_d2 <= '0';
else
updt_active_d2 <= updt2_active;
end if;
end if;
end process REG2_ACTIVE;
updt_active_re2 <= updt2_active and not updt_active_d2;
-- I_UPDT2_DATA_FIFO : entity lib_srl_fifo_v1_0_2.srl_fifo_f
-- generic map (
-- C_DWIDTH => 32 ,
-- C_DEPTH => 8 ,
-- C_FAMILY => C_FAMILY
-- )
-- port map (
-- Clk => m_axi_sg_aclk ,
-- Reset => sinit ,
-- FIFO_Write => ptr2_queue_wren ,
-- Data_In => ptr2_queue_din ,
-- FIFO_Read => ptr2_queue_rden ,
-- Data_Out => ptr2_queue_dout ,
-- FIFO_Empty => ptr2_queue_empty ,
-- FIFO_Full => ptr2_queue_full,
-- Addr => open
-- );
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (sinit = '1') then
ptr2_queue_dout <= (others => '0');
elsif (ptr2_queue_wren = '1') then
ptr2_queue_dout <= ptr2_queue_din;
end if;
end if;
end process;
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (sinit = '1' or ptr2_queue_rden = '1') then
ptr2_queue_empty <= '1';
ptr2_queue_full <= '0';
elsif (ptr2_queue_wren = '1') then
ptr2_queue_empty <= '0';
ptr2_queue_full <= '1';
end if;
end if;
end process;
APP_UPDATE: if C_SG2_WORDS_TO_UPDATE /= 1 generate
begin
I_UPDT2_STS_FIFO : entity lib_srl_fifo_v1_0_2.srl_fifo_f
generic map (
C_DWIDTH => 34 ,
C_DEPTH => 12 ,
C_FAMILY => C_FAMILY
)
port map (
Clk => m_axi_sg_aclk ,
Reset => sinit ,
FIFO_Write => sts2_queue_wren ,
Data_In => sts2_queue_din ,
FIFO_Read => sts2_rden,
Data_Out => sts2_queue_dout ,
FIFO_Empty => sts2_queue_empty ,
FIFO_Full => sts2_queue_full ,
Addr => open
);
end generate APP_UPDATE;
NO_APP_UPDATE: if C_SG2_WORDS_TO_UPDATE = 1 generate
begin
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (sinit = '1') then
sts2_queue_dout <= (others => '0');
elsif (sts2_queue_wren = '1') then
sts2_queue_dout <= sts2_queue_din;
end if;
end if;
end process;
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (sinit = '1' or sts2_rden = '1') then
sts2_queue_empty <= '1';
sts2_queue_full <= '0';
elsif (sts2_queue_wren = '1') then
sts2_queue_empty <= '0';
sts2_queue_full <= '1';
end if;
end if;
end process;
end generate NO_APP_UPDATE;
-- Pointer Queue Update - Descriptor Pointer (32bits)
-- i.e. 2 current descriptor pointers and any app fields
ptr2_queue_din(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) <= s_axis2_updtptr_tdata( -- DESC DATA
C_M_AXI_SG_ADDR_WIDTH-1
downto 0);
-- Data Queue Write Enable - based on tvalid and queue not full
ptr2_queue_wren <= s_axis2_updtptr_tvalid -- TValid
and not ptr2_queue_full; -- Data Queue NOT Full
-- Drive channel port with ready if room in data queue
s_axis2_updtptr_tready <= not ptr2_queue_full;
--*****************************************
--** Channel Status Port Side of Queues
--*****************************************
-- Status Queue Update - TLAST(1bit) & Includes IOC(1bit) & Descriptor Status(32bits)
-- Note: Type field is stripped off
sts2_queue_din(C_S_AXIS_UPDSTS_TDATA_WIDTH) <= s_axis2_updtsts_tlast; -- Store with tlast
sts2_queue_din(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0) <= s_axis2_updtsts_tdata( -- IOC & DESC STS
C_S_AXIS_UPDSTS_TDATA_WIDTH-1
downto 0);
-- Status Queue Write Enable - based on tvalid and queue not full
sts2_queue_wren <= s_axis2_updtsts_tvalid
and not sts2_queue_full;
-- Drive channel port with ready if room in status queue
s_axis2_updtsts_tready <= not sts2_queue_full;
--*************************************
--** SG Engine Side of Queues
--*************************************
-- Indicate NOT empty if both status queue and data queue are not empty
updt2_queue_empty <= ptr2_queue_empty
or follower_empty_s2mm; --or (sts2_queue_empty and follower_empty and updt2_active);
-- Data queue read enable
ptr2_queue_rden <= '1' when dataq_rden = '1' -- Cur desc read enable
and ptr2_queue_empty = '0' -- Data Queue NOT empty
and updt2_active = '1'
else '0';
-- Status queue read enable
sts2_queue_rden <= '1' when stsq_rden = '1' -- Writing desc status
and sts2_queue_empty = '0' -- Status fifo NOT empty
and updt2_active = '1'
else '0';
end generate S2MM_CHANNEL;
NO_S2MM_CHANNEL : if C_INCLUDE_S2MM = 0 generate
begin
updt_active_re2 <= '0';
updt2_queue_empty <= '0';
s_axis2_updtptr_tready <= '0';
s_axis2_updtsts_tready <= '0';
sts2_queue_dout <= (others => '0');
sts2_queue_full <= '0';
sts2_queue_empty <= '0';
ptr2_queue_dout <= (others => '0');
ptr2_queue_empty <= '0';
ptr2_queue_full <= '0';
end generate NO_S2MM_CHANNEL;
end generate GEN_Q_FOR_SYNC;
-- FIFO Reset is active high
sinit <= not m_axi_sg_aresetn;
-- LSB_PROC : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- if(m_axi_sg_aresetn = '0' )then
-- write_curdesc_lsb <= '0';
-- -- Capture lower pointer from FIFO or channel port
-- else -- if(write_curdesc_lsb = '1' and updt_active_int = '1')then
write_curdesc_lsb <= write_curdesc_lsb_sm;
-- end if;
-- end if;
-- end process LSB_PROC;
--*********************************************************************
--** POINTER CAPTURE LOGIC
--*********************************************************************
ptr_queue_dout_int <= ptr2_queue_dout when (updt2_active = '1') else
ptr_queue_dout;
---------------------------------------------------------------------------
-- Write lower order Next Descriptor Pointer out to pntr_mngr
---------------------------------------------------------------------------
updt_active_int <= updt_active or updt2_active;
REG_LSB_CURPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
updt_curdesc(31 downto 0) <= (others => '0');
-- Capture lower pointer from FIFO or channel port
elsif(write_curdesc_lsb = '1' and updt_active_int = '1')then
updt_curdesc(31 downto 0) <= ptr_queue_dout_int(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0);
end if;
end if;
end process REG_LSB_CURPNTR;
---------------------------------------------------------------------------
-- 64 Bit Scatter Gather addresses enabled
---------------------------------------------------------------------------
GEN_UPPER_MSB_CURDESC : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
---------------------------------------------------------------------------
-- Write upper order Next Descriptor Pointer out to pntr_mngr
---------------------------------------------------------------------------
REG_MSB_CURPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
updt_curdesc(C_M_AXI_SG_ADDR_WIDTH-1 downto 32) <= (others => '0');
-- updt_curdesc_wren <= '0';
-- Capture upper pointer from FIFO or channel port
-- and also write curdesc out
elsif(write_curdesc_lsb = '1' and updt_active_int = '1')then
updt_curdesc(C_M_AXI_SG_ADDR_WIDTH-1 downto 32) <= ptr_queue_dout_int(C_M_AXI_SG_ADDR_WIDTH-1 downto 32);
-- updt_curdesc_wren <= '1';
-- Assert tready/wren for only 1 clock
else
-- updt_curdesc_wren <= '0';
end if;
end if;
end process REG_MSB_CURPNTR;
end generate GEN_UPPER_MSB_CURDESC;
---------------------------------------------------------------------------
-- 32 Bit Scatter Gather addresses enabled
---------------------------------------------------------------------------
-----------------------------------------------------------------------
-- No upper order therefore dump fetched word and write pntr lower next
-- pointer to pntr mngr
-----------------------------------------------------------------------
REG_MSB_CURPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
updt_curdesc_wren <= '0';
-- Throw away second word, only write curdesc out with msb
-- set to zero
elsif(write_curdesc_lsb = '1' and updt_active_int = '1')then
--elsif(write_curdesc_msb = '1' and updt_active_int = '1')then
updt_curdesc_wren <= '1';
-- Assert for only 1 clock
else
updt_curdesc_wren <= '0';
end if;
end if;
end process REG_MSB_CURPNTR;
--*********************************************************************
--** ERROR CAPTURE LOGIC
--*********************************************************************
-----------------------------------------------------------------------
-- Generate rising edge pulse on writing status signal. This will
-- assert at the beginning of the status write. Coupled with status
-- fifo set to first word fall through status will be on dout
-- regardless of target ready.
-----------------------------------------------------------------------
REG_WRITE_STATUS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
writing_status_d1 <= '0';
else
writing_status_d1 <= writing_status;
end if;
end if;
end process REG_WRITE_STATUS;
writing_status_re <= writing_status and not writing_status_d1;
writing_status_re_ch1 <= writing_status_re and updt_active;
writing_status_re_ch2 <= writing_status_re and updt2_active;
-----------------------------------------------------------------------
-- Caputure IOC begin set
-----------------------------------------------------------------------
REG_IOC_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt_ioc_irq_set = '1')then
updt_ioc <= '0';
elsif(writing_status_re_ch1 = '1')then
-- updt_ioc <= sts_queue_dout(DESC_IOC_TAG_BIT) and updt_active;
updt_ioc <= follower_reg_mm2s(DESC_IOC_TAG_BIT);
end if;
end if;
end process REG_IOC_PROCESS;
-----------------------------------------------------------------------
-- Capture DMA Internal Errors
-----------------------------------------------------------------------
CAPTURE_DMAINT_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma_interr_set = '1')then
dma_interr <= '0';
elsif(writing_status_re_ch1 = '1')then
--dma_interr <= sts_queue_dout(DESC_STS_INTERR_BIT) and updt_active;
dma_interr <= follower_reg_mm2s(DESC_STS_INTERR_BIT);
end if;
end if;
end process CAPTURE_DMAINT_ERROR;
-----------------------------------------------------------------------
-- Capture DMA Slave Errors
-----------------------------------------------------------------------
CAPTURE_DMASLV_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma_slverr_set = '1')then
dma_slverr <= '0';
elsif(writing_status_re_ch1 = '1')then
-- dma_slverr <= sts_queue_dout(DESC_STS_SLVERR_BIT) and updt_active;
dma_slverr <= follower_reg_mm2s(DESC_STS_SLVERR_BIT);
end if;
end if;
end process CAPTURE_DMASLV_ERROR;
-----------------------------------------------------------------------
-- Capture DMA Decode Errors
-----------------------------------------------------------------------
CAPTURE_DMADEC_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma_decerr_set = '1')then
dma_decerr <= '0';
elsif(writing_status_re_ch1 = '1')then
-- dma_decerr <= sts_queue_dout(DESC_STS_DECERR_BIT) and updt_active;
dma_decerr <= follower_reg_mm2s(DESC_STS_DECERR_BIT);
end if;
end if;
end process CAPTURE_DMADEC_ERROR;
-----------------------------------------------------------------------
-- Caputure IOC begin set
-----------------------------------------------------------------------
REG_IOC2_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt2_ioc_irq_set = '1')then
updt2_ioc <= '0';
elsif(writing_status_re_ch2 = '1')then
-- updt2_ioc <= sts2_queue_dout(DESC_IOC_TAG_BIT) and updt2_active;
updt2_ioc <= follower_reg_s2mm(DESC_IOC_TAG_BIT);
end if;
end if;
end process REG_IOC2_PROCESS;
-----------------------------------------------------------------------
-- Capture DMA Internal Errors
-----------------------------------------------------------------------
CAPTURE_DMAINT2_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma2_interr_set = '1')then
dma2_interr <= '0';
elsif(writing_status_re_ch2 = '1')then
-- dma2_interr <= sts2_queue_dout(DESC_STS_INTERR_BIT) and updt2_active;
dma2_interr <= follower_reg_s2mm (DESC_STS_INTERR_BIT);
end if;
end if;
end process CAPTURE_DMAINT2_ERROR;
-----------------------------------------------------------------------
-- Capture DMA Slave Errors
-----------------------------------------------------------------------
CAPTURE_DMASLV2_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma2_slverr_set = '1')then
dma2_slverr <= '0';
elsif(writing_status_re_ch2 = '1')then
-- dma2_slverr <= sts2_queue_dout(DESC_STS_SLVERR_BIT) and updt2_active;
dma2_slverr <= follower_reg_s2mm(DESC_STS_SLVERR_BIT);
end if;
end if;
end process CAPTURE_DMASLV2_ERROR;
-----------------------------------------------------------------------
-- Capture DMA Decode Errors
-----------------------------------------------------------------------
CAPTURE_DMADEC2_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma2_decerr_set = '1')then
dma2_decerr <= '0';
elsif(writing_status_re_ch2 = '1')then
-- dma2_decerr <= sts2_queue_dout(DESC_STS_DECERR_BIT) and updt2_active;
dma2_decerr <= follower_reg_s2mm(DESC_STS_DECERR_BIT);
end if;
end if;
end process CAPTURE_DMADEC2_ERROR;
end implementation;
|
bsd-3-clause
|
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/Pmods/PmodMTDS_v1_0/ipshared/xilinx.com/axi_quad_spi_v3_2/hdl/src/vhdl/qspi_cntrl_reg.vhd
|
2
|
18476
|
-------------------------------------------------------------------------------
-- qspi_cntrl_reg.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- ** (c) Copyright [2010] - [2012] Xilinx, Inc. All rights reserved.*
-- ** *
-- ** This file contains confidential and proprietary information *
-- ** of Xilinx, Inc. and is protected under U.S. and *
-- ** international copyright and other intellectual property *
-- ** laws. *
-- ** *
-- ** DISCLAIMER *
-- ** This disclaimer is not a license and does not grant any *
-- ** rights to the materials distributed herewith. Except as *
-- ** otherwise provided in a valid license issued to you by *
-- ** Xilinx, and to the maximum extent permitted by applicable *
-- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- ** including negligence, or under any other theory of *
-- ** liability) for any loss or damage of any kind or nature *
-- ** related to, arising under or in connection with these *
-- ** materials, including for any direct, or any indirect, *
-- ** special, incidental, or consequential loss or damage *
-- ** (including loss of data, profits, goodwill, or any type of *
-- ** loss or damage suffered as a result of any action brought *
-- ** by a third party) even if such damage or loss was *
-- ** reasonably foreseeable or Xilinx had been advised of the *
-- ** possibility of the same. *
-- ** *
-- ** CRITICAL APPLICATIONS *
-- ** Xilinx products are not designed or intended to be fail- *
-- ** safe, or for use in any application requiring fail-safe *
-- ** performance, such as life-support or safety devices or *
-- ** systems, Class III medical devices, nuclear facilities, *
-- ** applications related to the deployment of airbags, or any *
-- ** other applications that could lead to death, personal *
-- ** injury, or severe property or environmental damage *
-- ** (individually and collectively, "Critical *
-- ** Applications"). Customer assumes the sole risk and *
-- ** liability of any use of Xilinx products in Critical *
-- ** Applications, subject only to applicable laws and *
-- ** regulations governing limitations on product liability. *
-- ** *
-- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename: qspi_cntrl_reg.vhd
-- Version: v3.0
-- Description: control register module for axi quad spi. This module decides the
-- behavior of the core in master/slave, CPOL/CPHA etc modes.
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.all;
use lib_pkg_v1_0_2.lib_pkg.RESET_ACTIVE;
library unisim;
use unisim.vcomponents.FDRE;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_S_AXI_DATA_WIDTH -- Width of the slave data bus
-- C_SPI_NUM_BITS_REG -- Width of SPI registers
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- SYSTEM
-- Bus2IP_Clk -- Bus to IP clock
-- Soft_Reset_op -- Soft_Reset_op Signal
-- SLAVE ATTACHMENT INTERFACE
-- Wr_ce_reduce_ack_gen -- common write ack generation logic input
-- Bus2IP_SPICR_data -- Data written from the PLB bus
-- Bus2IP_SPICR_WrCE -- Write CE for control register
-- Bus2IP_SPICR_RdCE -- Read CE for control register
-- IP2Bus_SPICR_Data -- Data to be send on the bus
-- SPI MODULE INTERFACE
-- Control_Register_Data -- Data to be send on the bus
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity Declaration
-------------------------------------------------------------------------------
entity qspi_cntrl_reg is
generic
(
----------------------------
C_S_AXI_DATA_WIDTH : integer; -- 32 bits
----------------------------
-- Number of bits in register, 10 for control reg - to match old version
C_SPI_NUM_BITS_REG : integer;
----------------------------
C_SPICR_REG_WIDTH : integer;
----------------------------
C_SPI_MODE : integer
----------------------------
);
port
(
Bus2IP_Clk : in std_logic;
Soft_Reset_op : in std_logic;
-- Slave attachment ports
Wr_ce_reduce_ack_gen : in std_logic;
Bus2IP_SPICR_WrCE : in std_logic;
Bus2IP_SPICR_RdCE : in std_logic;
Bus2IP_SPICR_data : in std_logic_vector(0 to (C_S_AXI_DATA_WIDTH-1));
-- SPI module ports
SPICR_0_LOOP : out std_logic;
SPICR_1_SPE : out std_logic;
SPICR_2_MASTER_N_SLV : out std_logic;
SPICR_3_CPOL : out std_logic;
SPICR_4_CPHA : out std_logic;
SPICR_5_TXFIFO_RST : out std_logic;
SPICR_6_RXFIFO_RST : out std_logic;
SPICR_7_SS : out std_logic;
SPICR_8_TR_INHIBIT : out std_logic;
SPICR_9_LSB : out std_logic;
--------------------------
-- to Status Register
SPISR_1_LOOP_Back_Error : out std_logic;
SPISR_2_MSB_Error : out std_logic;
SPISR_3_Slave_Mode_Error : out std_logic;
-- SPISR_4_XIP_Mode_On : out std_logic;
SPISR_4_CPOL_CPHA_Error : out std_logic;
IP2Bus_SPICR_Data : out std_logic_vector(0 to (C_SPICR_REG_WIDTH-1));
Control_bit_7_8 : out std_logic_vector(0 to 1) --(7 to 8)
);
end qspi_cntrl_reg;
-------------------------------------------------------------------------------
-- Architecture
--------------------------------------
architecture imp of qspi_cntrl_reg is
-------------------------------------
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-- Signal Declarations
----------------------
signal SPICR_data_int : std_logic_vector(0 to (C_SPICR_REG_WIDTH-1));
signal SPICR_3_4_Reset : std_logic;
signal Control_bit_7_8_int : std_logic_vector(7 to 8);
signal temp_wr_ce : std_logic;
-----
begin
-----
----------------------------
-- Combinatorial operations
----------------------------
-- Control_Register_Data <= SPICR_data_int;
-------------------------------------------------------
SPICR_0_LOOP <= SPICR_data_int(C_SPICR_REG_WIDTH-1); -- as per the SPICR Fig 3 in DS this bit is @ 0th position
SPICR_1_SPE <= SPICR_data_int(C_SPICR_REG_WIDTH-2); -- as per the SPICR Fig 3 in DS this bit is @ 1st position
SPICR_2_MASTER_N_SLV <= SPICR_data_int(C_SPICR_REG_WIDTH-3); -- as per the SPICR Fig 3 in DS this bit is @ 2nd position
SPICR_3_CPOL <= SPICR_data_int(C_SPICR_REG_WIDTH-4); -- as per the SPICR Fig 3 in DS this bit is @ 3rd position
SPICR_4_CPHA <= SPICR_data_int(C_SPICR_REG_WIDTH-5); -- as per the SPICR Fig 3 in DS this bit is @ 4th position
SPICR_5_TXFIFO_RST <= SPICR_data_int(C_SPICR_REG_WIDTH-6); -- as per the SPICR Fig 3 in DS this bit is @ 5th position
SPICR_6_RXFIFO_RST <= SPICR_data_int(C_SPICR_REG_WIDTH-7); -- as per the SPICR Fig 3 in DS this bit is @ 6th position
SPICR_7_SS <= SPICR_data_int(C_SPICR_REG_WIDTH-8); -- as per the SPICR Fig 3 in DS this bit is @ 7th position
SPICR_8_TR_INHIBIT <= SPICR_data_int(C_SPICR_REG_WIDTH-9); -- as per the SPICR Fig 3 in DS this bit is @ 8th position
SPICR_9_LSB <= SPICR_data_int(C_SPICR_REG_WIDTH-10);-- as per the SPICR Fig 3 in DS this bit is @ 9th position
-------------------------------------------------------
SPISR_DUAL_MODE_STATUS_GEN : if C_SPI_MODE = 1 or C_SPI_MODE = 2 generate
----------------------------
--signal ored_SPICR_7_12 : std_logic;
begin
-----
--ored_SPICR_7_12 <= or_reduce(SPICR_data_int(7 to 12));
-- C_SPICR_REG_WIDTH is of 10 bit wide
SPISR_1_LOOP_Back_Error <= SPICR_data_int(C_SPICR_REG_WIDTH-1);-- 9th bit in present SPICR
SPISR_2_MSB_Error <= SPICR_data_int(C_SPICR_REG_WIDTH-C_SPICR_REG_WIDTH); -- 0th LSB bit in present SPICR
SPISR_3_Slave_Mode_Error <= not SPICR_data_int(C_SPICR_REG_WIDTH-3); -- Mst_n_Slv 7th bit in control register - default is slave mode of operation
SPISR_4_CPOL_CPHA_Error <= SPICR_data_int(C_SPICR_REG_WIDTH-5) xor -- bit 5-CPHA and 6-CPOL in present SPICR
SPICR_data_int(C_SPICR_REG_WIDTH-4);-- CPOL-CPHA = 01 or 10 in control register
end generate SPISR_DUAL_MODE_STATUS_GEN;
----------------------------------------
SPISR_NO_DUAL_MODE_STATUS_GEN : if C_SPI_MODE = 0 generate
-------------------------------
begin
-----
SPISR_1_LOOP_Back_Error <= '0';
SPISR_2_MSB_Error <= '0';
SPISR_3_Slave_Mode_Error <= '0';
SPISR_4_CPOL_CPHA_Error <= '0';
end generate SPISR_NO_DUAL_MODE_STATUS_GEN;
-------------------------------------------
SPICR_REG_RD_GENERATE: for i in 0 to C_SPICR_REG_WIDTH-1 generate
-----
begin
-----
IP2Bus_SPICR_Data(i) <= SPICR_data_int(i) and Bus2IP_SPICR_RdCE;
end generate SPICR_REG_RD_GENERATE;
-----------------------------------
---------------------------------------------------------------
-- Bus2IP Data bit mapping - 0 to 21 - NA
-- 22 23 24 25 26 27 28 29 30 31
--
-- Control Register - 0 to 22 bit mapping
-- 0 1 2 3 4 5 6 7 8 9
-- LSB TRAN MANUAL RX FIFO TX FIFO CPHA CPOL MASTER SPE LOOP
-- INHI SLAVE RST RST
-- '0' '1' '1' '0' '0' '0' '0' '0' '0' '0'
-----------------------------------------------------
-- AXI Data 31 downto 0 |
-- valid bits in AXI start from LSB i.e. 0 |
-- Bus2IP_Data 0 to 31 |
-- **** IMP Starts **** |
-- This is 1 is to 1 mapping with reverse bit order.|
-- **** IMP Ends **** |
-- Bus2IP_Data 0 1 2 3 4 5 6 7 21 22--->31 |
-- Control Bits<-------NA--------> 0---->9 |
-----------------------------------------------------
--SPICR_NO_DUAL_MODE_WR_GEN: if C_SPI_MODE = 0 generate
---------------------------------
--begin
-----
-- SPICR_data_int(0 to 12) <= (others => '0');
--end generate SPICR_NO_DUAL_MODE_WR_GEN;
----------------------------------------------
temp_wr_ce <= wr_ce_reduce_ack_gen and Bus2IP_SPICR_WrCE;
-- -- SPICR_REG_0_PROCESS : Control Register Write Operation for bit 0 - LSB
-- -----------------------------
-- Behavioral Code **
SPICR_REG_0_PROCESS:process(Bus2IP_Clk)
-----
begin
-----
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Soft_Reset_op = RESET_ACTIVE) then
SPICR_data_int(0) <= '0';
elsif ((wr_ce_reduce_ack_gen and Bus2IP_SPICR_WrCE)='1') then
SPICR_data_int(0) <=
Bus2IP_SPICR_data(C_S_AXI_DATA_WIDTH-C_SPICR_REG_WIDTH);-- after 100 ps;
end if;
end if;
end process SPICR_REG_0_PROCESS;
--------------------------------
CONTROL_REG_1_2_GENERATE: for i in 1 to 2 generate
------------------------
begin
-----
-- SPICR_REG_1_2_PROCESS : Control Register Write Operation for bit 1_2 - TRAN_INHI and MANUAL_SLAVE
-----------------------------
SPICR_REG_1_2_PROCESS:process(Bus2IP_Clk)
-----
begin
-----
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Soft_Reset_op = RESET_ACTIVE) then
SPICR_data_int(i) <= '1';
elsif((wr_ce_reduce_ack_gen and Bus2IP_SPICR_WrCE)='1') then
SPICR_data_int(i) <=
Bus2IP_SPICR_data(C_S_AXI_DATA_WIDTH-C_SPICR_REG_WIDTH+i);-- after 100 ps;
end if;
end if;
end process SPICR_REG_1_2_PROCESS;
----------------------------------
end generate CONTROL_REG_1_2_GENERATE;
--------------------------------------
-- the below reset signal is needed to de-assert the Tx/Rx FIFO reset signals.
SPICR_3_4_Reset <= (not Bus2IP_SPICR_WrCE) or Soft_Reset_op;
-- CONTROL_REG_3_4_GENERATE : Control Register Write Operation for bit 3_4 - Receive FIFO Reset and Transmit FIFO Reset
-----------------------------
CONTROL_REG_3_4_GENERATE: for i in 3 to 4 generate
-----
begin
-----
SPICR_REG_3_4_PROCESS:process(Bus2IP_Clk)
-----
begin
-----
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (SPICR_3_4_Reset = RESET_ACTIVE) then
SPICR_data_int(i) <= '0';
elsif ((wr_ce_reduce_ack_gen and Bus2IP_SPICR_WrCE)='1') then
SPICR_data_int(i) <=
Bus2IP_SPICR_data(C_S_AXI_DATA_WIDTH-C_SPICR_REG_WIDTH+i);-- after 100 ps;
end if;
end if;
end process SPICR_REG_3_4_PROCESS;
----------------------------------
end generate CONTROL_REG_3_4_GENERATE;
--------------------------------------
-- CONTROL_REG_5_9_GENERATE : Control Register Write Operation for bit 5:9 - CPHA, CPOL, MASTER, SPE, LOOP
-----------------------------
CONTROL_REG_5_9_GENERATE: for i in 5 to C_SPICR_REG_WIDTH-1 generate
-----
begin
-----
SPICR_REG_5_9_PROCESS:process(Bus2IP_Clk)
-----
begin
-----
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Soft_Reset_op = RESET_ACTIVE) then
SPICR_data_int(i) <= '0';
elsif ((wr_ce_reduce_ack_gen and Bus2IP_SPICR_WrCE)='1') then
SPICR_data_int(i) <=
Bus2IP_SPICR_data(C_S_AXI_DATA_WIDTH-C_SPICR_REG_WIDTH+i);-- after 100 ps;
end if;
end if;
end process SPICR_REG_5_9_PROCESS;
----------------------------------
end generate CONTROL_REG_5_9_GENERATE;
--------------------------------------
--
-- SPICR_REG_78_GENERATE: This logic is newly added to register _T signals
-- ------------------------ in IOB. This logic simplifies the register method
-- for _T in IOB, without affecting functionality.
SPICR_REG_78_GENERATE: for i in 7 to 8 generate
-----
begin
-----
SPI_TRISTATE_CONTROL_I: component FDRE
port map
(
Q => Control_bit_7_8_int(i) ,-- out:
C => Bus2IP_Clk ,--: in
CE => Bus2IP_SPICR_WrCE ,--: in
R => Soft_Reset_op ,-- : in
D => Bus2IP_SPICR_data(C_S_AXI_DATA_WIDTH-C_SPICR_REG_WIDTH+i) --: in
);
end generate SPICR_REG_78_GENERATE;
-----------------------------------
Control_bit_7_8 <= Control_bit_7_8_int;
---------------------------------------
end imp;
--------------------------------------------------------------------------------
|
bsd-3-clause
|
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/usb2device_v1_0/src/fifo_generator_input_buffer/fifo_generator_v13_0_1/hdl/fifo_generator_v13_0.vhd
|
10
|
91022
|
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`protect end_protected
|
bsd-3-clause
|
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/usb2device_v1_0/src/axi_dma_0/axi_datamover_v5_1_9/hdl/src/vhdl/axi_datamover_s2mm_full_wrap.vhd
|
4
|
92853
|
-------------------------------------------------------------------------------
-- axi_datamover_s2mm_full_wrap.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_s2mm_full_wrap.vhd
--
-- Description:
-- This file implements the DataMover S2MM FULL Wrapper.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all ;
-- axi_datamover Library Modules
library axi_datamover_v5_1_9;
use axi_datamover_v5_1_9.axi_datamover_reset ;
use axi_datamover_v5_1_9.axi_datamover_cmd_status ;
use axi_datamover_v5_1_9.axi_datamover_pcc ;
use axi_datamover_v5_1_9.axi_datamover_ibttcc ;
use axi_datamover_v5_1_9.axi_datamover_indet_btt ;
use axi_datamover_v5_1_9.axi_datamover_s2mm_realign ;
use axi_datamover_v5_1_9.axi_datamover_addr_cntl ;
use axi_datamover_v5_1_9.axi_datamover_wrdata_cntl ;
use axi_datamover_v5_1_9.axi_datamover_wr_status_cntl;
Use axi_datamover_v5_1_9.axi_datamover_skid2mm_buf ;
Use axi_datamover_v5_1_9.axi_datamover_skid_buf ;
Use axi_datamover_v5_1_9.axi_datamover_wr_sf ;
-------------------------------------------------------------------------------
entity axi_datamover_s2mm_full_wrap is
generic (
C_INCLUDE_S2MM : Integer range 0 to 2 := 1;
-- Specifies the type of S2MM function to include
-- 0 = Omit S2MM functionality
-- 1 = Full S2MM Functionality
-- 2 = Lite S2MM functionality
C_S2MM_AWID : Integer range 0 to 255 := 9;
-- Specifies the constant value to output on
-- the ARID output port
C_S2MM_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the S2MM ID port
C_S2MM_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_S2MM_MDATA_WIDTH : Integer range 32 to 1024 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_S2MM_SDATA_WIDTH : Integer range 8 to 1024 := 32;
-- Specifies the width of the S2MM Master Stream Data
-- Channel data bus
C_INCLUDE_S2MM_STSFIFO : Integer range 0 to 1 := 1;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit S2MM Status FIFO
-- 1 = Include S2MM Status FIFO
C_S2MM_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4;
-- Specifies the depth of the S2MM Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_S2MM_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_S2MM_DRE : Integer range 0 to 1 := 0;
-- Specifies if DRE is to be included in the S2MM function
-- 0 = Omit DRE
-- 1 = Include DRE
C_S2MM_BURST_SIZE : Integer range 2 to 256 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the S2MM function
C_S2MM_BTT_USED : Integer range 8 to 23 := 16;
-- Specifies the number of bits used from the BTT field
-- of the input Command Word of the S2MM Command Interface
C_S2MM_SUPPORT_INDET_BTT : Integer range 0 to 1 := 0;
-- Specifies if support for indeterminate packet lengths
-- are to be received on the input Stream interface
-- 0 = Omit support (User MUST transfer the exact number of
-- bytes on the Stream interface as specified in the BTT
-- field of the Corresponding DataMover Command)
-- 1 = Include support for indeterminate packet lengths
-- This causes FIFOs to be added and "Store and Forward"
-- behavior of the S2MM function
C_S2MM_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 3;
-- This parameter specifies the depth of the S2MM internal
-- address pipeline queues in the Write Address Controller
-- and the Write Data Controller. Increasing this value will
-- allow more Write Addresses to be issued to the AXI4 Write
-- Address Channel before transmission of the associated
-- write data on the Write Data Channel.
C_TAG_WIDTH : Integer range 1 to 8 := 4 ;
-- Width of the TAG field
C_INCLUDE_S2MM_GP_SF : Integer range 0 to 1 := 1 ;
-- This parameter specifies the inclusion/omission of the
-- S2MM (Write) General Purpose Store and Forward function
-- 0 = Omit GP Store and Forward
-- 1 = Include GP Store and Forward
C_ENABLE_CACHE_USER : Integer range 0 to 1 := 1;
C_ENABLE_S2MM_TKEEP : integer range 0 to 1 := 1;
C_ENABLE_SKID_BUF : string := "11111";
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA family type
);
port (
-- S2MM Primary Clock and Reset inputs ----------------------------
s2mm_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
-------------------------------------------------------------------
-- S2MM Primary Reset input ---------------------------------------
s2mm_aresetn : in std_logic; --
-- Reset used for the internal master logic --
-------------------------------------------------------------------
-- S2MM Halt request input control --------------------------------
s2mm_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- S2MM Halt Complete status flag --
s2mm_halt_cmplt : Out std_logic; --
-- Active high soft shutdown complete status --
-------------------------------------------------------------------
-- S2MM Error discrete output -------------------------------------
s2mm_err : Out std_logic; --
-- Composite Error indication --
-------------------------------------------------------------------
-- Optional Command and Status Clock and Reset -------------------
-- Only used when C_S2MM_STSCMD_IS_ASYNC = 1 --
--
s2mm_cmdsts_awclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
s2mm_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
------------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) -----------------------------------------------------
s2mm_cmd_wvalid : in std_logic; --
s2mm_cmd_wready : out std_logic; --
s2mm_cmd_wdata : in std_logic_vector((C_TAG_WIDTH+(8*C_ENABLE_CACHE_USER)+C_S2MM_ADDR_WIDTH+36)-1 downto 0); --
--------------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) --------------------------------------------------------
s2mm_sts_wvalid : out std_logic; --
s2mm_sts_wready : in std_logic; --
s2mm_sts_wdata : out std_logic_vector(((C_S2MM_SUPPORT_INDET_BTT*24)+8)-1 downto 0); --
s2mm_sts_wstrb : out std_logic_vector((((C_S2MM_SUPPORT_INDET_BTT*24)+8)/8)-1 downto 0); --
s2mm_sts_wlast : out std_logic; --
----------------------------------------------------------------------------------------------------
-- Address posting controls ---------------------------------------
s2mm_allow_addr_req : in std_logic; --
s2mm_addr_req_posted : out std_logic; --
s2mm_wr_xfer_cmplt : out std_logic; --
s2mm_ld_nxt_len : out std_logic; --
s2mm_wr_len : out std_logic_vector(7 downto 0); --
-------------------------------------------------------------------
-- S2MM AXI Address Channel I/O --------------------------------------
s2mm_awid : out std_logic_vector(C_S2MM_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
s2mm_awaddr : out std_logic_vector(C_S2MM_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
s2mm_awlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
s2mm_awsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
s2mm_awburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
s2mm_awprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
s2mm_awcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel PROT output --
s2mm_awuser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel PROT output --
--
s2mm_awvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
s2mm_awready : in std_logic; --
-- AXI Address Channel READY input --
-----------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -----------
-- s2mm__awlock : out std_logic_vector(2 downto 0); --
-- s2mm__awcache : out std_logic_vector(4 downto 0); --
-- s2mm__awqos : out std_logic_vector(3 downto 0); --
-- s2mm__awregion : out std_logic_vector(3 downto 0); --
-----------------------------------------------------------------------
-- S2MM AXI MMap Write Data Channel I/O ---------------------------------------------
s2mm_wdata : Out std_logic_vector(C_S2MM_MDATA_WIDTH-1 downto 0); --
s2mm_wstrb : Out std_logic_vector((C_S2MM_MDATA_WIDTH/8)-1 downto 0); --
s2mm_wlast : Out std_logic; --
s2mm_wvalid : Out std_logic; --
s2mm_wready : In std_logic; --
--------------------------------------------------------------------------------------
-- S2MM AXI MMap Write response Channel I/O -----------------------------------------
s2mm_bresp : In std_logic_vector(1 downto 0); --
s2mm_bvalid : In std_logic; --
s2mm_bready : Out std_logic; --
--------------------------------------------------------------------------------------
-- S2MM AXI Master Stream Channel I/O -----------------------------------------------
s2mm_strm_wdata : In std_logic_vector(C_S2MM_SDATA_WIDTH-1 downto 0); --
s2mm_strm_wstrb : In std_logic_vector((C_S2MM_SDATA_WIDTH/8)-1 downto 0); --
s2mm_strm_wlast : In std_logic; --
s2mm_strm_wvalid : In std_logic; --
s2mm_strm_wready : Out std_logic; --
--------------------------------------------------------------------------------------
-- Testing Support I/O ------------------------------------------
s2mm_dbg_sel : in std_logic_vector( 3 downto 0); --
s2mm_dbg_data : out std_logic_vector(31 downto 0) --
-----------------------------------------------------------------
);
end entity axi_datamover_s2mm_full_wrap;
architecture implementation of axi_datamover_s2mm_full_wrap is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function Declarations ----------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_calc_wdemux_sel_bits
--
-- Function Description:
-- This function calculates the number of address bits needed for
-- the Write Strobe demux select control.
--
-------------------------------------------------------------------
function func_calc_wdemux_sel_bits (mmap_dwidth_value : integer) return integer is
Variable num_addr_bits_needed : Integer range 1 to 7 := 1;
begin
case mmap_dwidth_value is
when 32 =>
num_addr_bits_needed := 2;
when 64 =>
num_addr_bits_needed := 3;
when 128 =>
num_addr_bits_needed := 4;
when 256 =>
num_addr_bits_needed := 5;
when 512 =>
num_addr_bits_needed := 6;
when others => -- 1024 bits
num_addr_bits_needed := 7;
end case;
Return (num_addr_bits_needed);
end function func_calc_wdemux_sel_bits;
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_include_dre
--
-- Function Description:
-- This function desides if conditions are right for allowing DRE
-- inclusion.
--
-------------------------------------------------------------------
function func_include_dre (need_dre : integer;
needed_data_width : integer) return integer is
Variable include_dre : Integer := 0;
begin
if (need_dre = 1 and
needed_data_width < 128 and
needed_data_width > 8) Then
include_dre := 1;
Else
include_dre := 0;
End if;
Return (include_dre);
end function func_include_dre;
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_get_align_width
--
-- Function Description:
-- This function calculates the needed DRE alignment port width\
-- based upon the inclusion of DRE and the needed bit width of the
-- DRE.
--
-------------------------------------------------------------------
function func_get_align_width (dre_included : integer;
dre_data_width : integer) return integer is
Variable align_port_width : Integer := 1;
begin
if (dre_included = 1) then
If (dre_data_width = 64) Then
align_port_width := 3;
Elsif (dre_data_width = 32) Then
align_port_width := 2;
else -- 16 bit data width
align_port_width := 1;
End if;
else
align_port_width := 1;
end if;
Return (align_port_width);
end function func_get_align_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_set_status_width
--
-- Function Description:
-- This function sets the width of the Status pipe depending on the
-- Store and Forward inclusion or ommision.
--
-------------------------------------------------------------------
function funct_set_status_width (store_forward_enabled : integer)
return integer is
Variable temp_status_bit_width : Integer := 8;
begin
If (store_forward_enabled = 1) Then
temp_status_bit_width := 32;
Else
temp_status_bit_width := 8;
End if;
Return (temp_status_bit_width);
end function funct_set_status_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_bits_needed
--
-- Function Description:
--
--
-------------------------------------------------------------------
function get_bits_needed (max_bytes : integer) return integer is
Variable fvar_temp_bit_width : Integer := 1;
begin
if (max_bytes <= 1) then
fvar_temp_bit_width := 1;
elsif (max_bytes <= 3) then
fvar_temp_bit_width := 2;
elsif (max_bytes <= 7) then
fvar_temp_bit_width := 3;
elsif (max_bytes <= 15) then
fvar_temp_bit_width := 4;
elsif (max_bytes <= 31) then
fvar_temp_bit_width := 5;
elsif (max_bytes <= 63) then
fvar_temp_bit_width := 6;
elsif (max_bytes <= 127) then
fvar_temp_bit_width := 7;
elsif (max_bytes <= 255) then
fvar_temp_bit_width := 8;
elsif (max_bytes <= 511) then
fvar_temp_bit_width := 9;
elsif (max_bytes <= 1023) then
fvar_temp_bit_width := 10;
elsif (max_bytes <= 2047) then
fvar_temp_bit_width := 11;
elsif (max_bytes <= 4095) then
fvar_temp_bit_width := 12;
elsif (max_bytes <= 8191) then
fvar_temp_bit_width := 13;
else -- 8k - 16K
fvar_temp_bit_width := 14;
end if;
Return (fvar_temp_bit_width);
end function get_bits_needed;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_rnd2pwr_of_2
--
-- Function Description:
-- Rounds the input value up to the nearest power of 2 between
-- 128 and 8192.
--
-------------------------------------------------------------------
function funct_rnd2pwr_of_2 (input_value : integer) return integer is
Variable temp_pwr2 : Integer := 128;
begin
if (input_value <= 128) then
temp_pwr2 := 128;
elsif (input_value <= 256) then
temp_pwr2 := 256;
elsif (input_value <= 512) then
temp_pwr2 := 512;
elsif (input_value <= 1024) then
temp_pwr2 := 1024;
elsif (input_value <= 2048) then
temp_pwr2 := 2048;
elsif (input_value <= 4096) then
temp_pwr2 := 4096;
else
temp_pwr2 := 8192;
end if;
Return (temp_pwr2);
end function funct_rnd2pwr_of_2;
-------------------------------------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_need_realigner
--
-- Function Description:
-- Determines if the Realigner module needs to be included.
--
-------------------------------------------------------------------
function funct_need_realigner (indet_btt_enabled : integer;
dre_included : integer;
gp_sf_included : integer) return integer is
Variable temp_val : Integer := 0;
begin
If ((indet_btt_enabled = 1) or
(dre_included = 1) or
(gp_sf_included = 1)) Then
temp_val := 1;
else
temp_val := 0;
End if;
Return (temp_val);
end function funct_need_realigner;
-------------------------------------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_sf_offset_width
--
-- Function Description:
-- This function calculates the address offset width needed by
-- the GP Store and Forward module with data packing.
--
-------------------------------------------------------------------
function funct_get_sf_offset_width (mmap_dwidth : integer;
stream_dwidth : integer) return integer is
Constant FCONST_WIDTH_RATIO : integer := mmap_dwidth/stream_dwidth;
Variable fvar_temp_offset_width : Integer := 1;
begin
case FCONST_WIDTH_RATIO is
when 1 =>
fvar_temp_offset_width := 1;
when 2 =>
fvar_temp_offset_width := 1;
when 4 =>
fvar_temp_offset_width := 2;
when 8 =>
fvar_temp_offset_width := 3;
when 16 =>
fvar_temp_offset_width := 4;
when 32 =>
fvar_temp_offset_width := 5;
when 64 =>
fvar_temp_offset_width := 6;
when others =>
fvar_temp_offset_width := 7;
end case;
Return (fvar_temp_offset_width);
end function funct_get_sf_offset_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_stream_width2use
--
-- Function Description:
-- This function calculates the Stream width to use for S2MM
-- modules downstream from the upsizing Store and Forward. If
-- Store and forward is present, then the effective Stream width
-- is the MMAP data width. If no Store and Forward then the Stream
-- width is the input Stream width from the User.
--
-------------------------------------------------------------------
function funct_get_stream_width2use (mmap_data_width : integer;
stream_data_width : integer;
sf_enabled : integer) return integer is
Variable fvar_temp_width : Integer := 32;
begin
If (sf_enabled > 0) Then
fvar_temp_width := mmap_data_width;
Else
fvar_temp_width := stream_data_width;
End if;
Return (fvar_temp_width);
end function funct_get_stream_width2use;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_bytes_per_dbeat
--
-- Function Description:
-- This function calculates the number of bytes transfered per
-- databeat on the MMap AXI4 Write Data Channel by the S2MM. The
-- value is based on input parameterization of included functions
-- in the S2MM block.
--
-------------------------------------------------------------------
function funct_get_bytes_per_dbeat (ibtt_enabled : integer ;
gpsf_enabled : integer ;
stream_dwidth : integer ;
mmap_dwidth : integer ) return integer is
Variable fvar_temp_bytes_per_xfer : Integer := 4;
begin
If (ibtt_enabled > 0 or
gpsf_enabled > 0) Then -- transfers will be upsized to mmap data width
fvar_temp_bytes_per_xfer := mmap_dwidth/8;
Else -- transfers will be in stream data widths (may be narrow transfers on mmap)
fvar_temp_bytes_per_xfer := stream_dwidth/8;
End if;
Return (fvar_temp_bytes_per_xfer);
end function funct_get_bytes_per_dbeat;
-- Constant Declarations ----------------------------------------
Constant SF_ENABLED : integer := C_INCLUDE_S2MM_GP_SF + C_S2MM_SUPPORT_INDET_BTT;
Constant SF_UPSIZED_SDATA_WIDTH : integer := funct_get_stream_width2use(C_S2MM_MDATA_WIDTH,
C_S2MM_SDATA_WIDTH,
SF_ENABLED);
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant IS_NOT_MM2S : integer range 0 to 1 := 0;
Constant S2MM_AWID_VALUE : integer range 0 to 255 := C_S2MM_AWID;
Constant S2MM_AWID_WIDTH : integer range 1 to 8 := C_S2MM_ID_WIDTH;
Constant S2MM_ADDR_WIDTH : integer range 32 to 64 := C_S2MM_ADDR_WIDTH;
Constant S2MM_MDATA_WIDTH : integer range 32 to 1024 := C_S2MM_MDATA_WIDTH;
Constant S2MM_SDATA_WIDTH : integer range 8 to 1024 := C_S2MM_SDATA_WIDTH;
Constant S2MM_TAG_WIDTH : integer range 1 to 8 := C_TAG_WIDTH;
Constant S2MM_CMD_WIDTH : integer := (S2MM_TAG_WIDTH+S2MM_ADDR_WIDTH+32);
Constant INCLUDE_S2MM_STSFIFO : integer range 0 to 1 := C_INCLUDE_S2MM_STSFIFO;
Constant S2MM_STSCMD_FIFO_DEPTH : integer range 1 to 16 := C_S2MM_STSCMD_FIFO_DEPTH;
Constant S2MM_STSCMD_IS_ASYNC : integer range 0 to 1 := C_S2MM_STSCMD_IS_ASYNC;
Constant S2MM_BURST_SIZE : integer range 2 to 256 := C_S2MM_BURST_SIZE;
Constant ADDR_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_S2MM_ADDR_PIPE_DEPTH;
Constant WR_DATA_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_S2MM_ADDR_PIPE_DEPTH;
Constant SEL_ADDR_WIDTH : integer range 2 to 7 := func_calc_wdemux_sel_bits(S2MM_MDATA_WIDTH);
Constant S2MM_BTT_USED : integer range 8 to 23 := C_S2MM_BTT_USED;
Constant BITS_PER_BYTE : integer := 8;
Constant INCLUDE_S2MM_DRE : integer range 0 to 1 := func_include_dre(C_INCLUDE_S2MM_DRE,
S2MM_SDATA_WIDTH);
Constant DRE_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_S2MM_ADDR_PIPE_DEPTH;
Constant S2MM_DRE_ALIGN_WIDTH : integer range 1 to 3 := func_get_align_width(INCLUDE_S2MM_DRE,
S2MM_SDATA_WIDTH);
Constant DRE_SUPPORT_SCATTER : integer range 0 to 1 := 1;
Constant ENABLE_INDET_BTT_SF : integer range 0 to 1 := C_S2MM_SUPPORT_INDET_BTT;
Constant ENABLE_GP_SF : integer range 0 to 1 := C_INCLUDE_S2MM_GP_SF ;
Constant BYTES_PER_MMAP_DBEAT : integer := funct_get_bytes_per_dbeat(ENABLE_INDET_BTT_SF ,
ENABLE_GP_SF ,
S2MM_SDATA_WIDTH ,
S2MM_MDATA_WIDTH);
Constant MAX_BYTES_PER_BURST : integer := BYTES_PER_MMAP_DBEAT*S2MM_BURST_SIZE;
Constant IBTT_XFER_BYTES_WIDTH : integer := get_bits_needed(MAX_BYTES_PER_BURST);
Constant WR_STATUS_CNTL_FIFO_DEPTH : integer range 1 to 32 := WR_DATA_CNTL_FIFO_DEPTH+2; -- 2 added for going
-- full thresholding
-- in WSC
Constant WSC_STATUS_WIDTH : integer range 8 to 32 :=
funct_set_status_width(ENABLE_INDET_BTT_SF);
Constant WSC_BYTES_RCVD_WIDTH : integer range 8 to 32 := S2MM_BTT_USED;
Constant ADD_REALIGNER : integer := funct_need_realigner(ENABLE_INDET_BTT_SF ,
INCLUDE_S2MM_DRE ,
ENABLE_GP_SF);
-- Calculates the minimum needed depth of the GP Store and Forward FIFO
-- based on the S2MM pipeline depth and the max allowed Burst length
Constant PIPEDEPTH_BURST_LEN_PROD : integer :=
(ADDR_CNTL_FIFO_DEPTH+2) * S2MM_BURST_SIZE;
-- Assigns the depth of the optional GP Store and Forward FIFO to the nearest
-- power of 2
Constant SF_FIFO_DEPTH : integer range 128 to 8192 :=
funct_rnd2pwr_of_2(PIPEDEPTH_BURST_LEN_PROD);
-- Calculate the width of the Store and Forward Starting Address Offset bus
Constant SF_STRT_OFFSET_WIDTH : integer := funct_get_sf_offset_width(S2MM_MDATA_WIDTH,
S2MM_SDATA_WIDTH);
-- Signal Declarations ------------------------------------------
signal sig_cmd_stat_rst_user : std_logic := '0';
signal sig_cmd_stat_rst_int : std_logic := '0';
signal sig_mmap_rst : std_logic := '0';
signal sig_stream_rst : std_logic := '0';
signal sig_s2mm_cmd_wdata : std_logic_vector(S2MM_CMD_WIDTH-1 downto 0) := (others => '0');
signal sig_s2mm_cache_data : std_logic_vector(7 downto 0) := (others => '0');
signal sig_cmd2mstr_command : std_logic_vector(S2MM_CMD_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd2mstr_cmd_valid : std_logic := '0';
signal sig_mst2cmd_cmd_ready : std_logic := '0';
signal sig_mstr2addr_addr : std_logic_vector(S2MM_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2addr_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_mstr2addr_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_mstr2addr_burst : std_logic_vector(1 downto 0) := (others => '0');
signal sig_mstr2addr_cache : std_logic_vector(3 downto 0) := (others => '0');
signal sig_mstr2addr_user : std_logic_vector(3 downto 0) := (others => '0');
signal sig_mstr2addr_cmd_cmplt : std_logic := '0';
signal sig_mstr2addr_calc_error : std_logic := '0';
signal sig_mstr2addr_cmd_valid : std_logic := '0';
signal sig_addr2mstr_cmd_ready : std_logic := '0';
signal sig_mstr2data_saddr_lsb : std_logic_vector(SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2data_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_mstr2data_strt_strb : std_logic_vector((SF_UPSIZED_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mstr2data_last_strb : std_logic_vector((SF_UPSIZED_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mstr2data_drr : std_logic := '0';
signal sig_mstr2data_eof : std_logic := '0';
signal sig_mstr2data_sequential : std_logic := '0';
signal sig_mstr2data_calc_error : std_logic := '0';
signal sig_mstr2data_cmd_last : std_logic := '0';
signal sig_mstr2data_cmd_valid : std_logic := '0';
signal sig_data2mstr_cmd_ready : std_logic := '0';
signal sig_addr2data_addr_posted : std_logic := '0';
signal sig_data2addr_data_rdy : std_logic := '0';
signal sig_data2all_tlast_error : std_logic := '0';
signal sig_data2all_dcntlr_halted : std_logic := '0';
signal sig_addr2wsc_calc_error : std_logic := '0';
signal sig_addr2wsc_cmd_fifo_empty : std_logic := '0';
signal sig_data2wsc_rresp : std_logic_vector(1 downto 0) := (others => '0');
signal sig_data2wsc_cmd_empty : std_logic := '0';
signal sig_data2wsc_calc_err : std_logic := '0';
signal sig_data2wsc_cmd_cmplt : std_logic := '0';
signal sig_data2wsc_last_err : std_logic := '0';
signal sig_calc2dm_calc_err : std_logic := '0';
signal sig_wsc2stat_status : std_logic_vector(WSC_STATUS_WIDTH-1 downto 0) := (others => '0');
signal sig_stat2wsc_status_ready : std_logic := '0';
signal sig_wsc2stat_status_valid : std_logic := '0';
signal sig_wsc2mstr_halt_pipe : std_logic := '0';
signal sig_data2wsc_tag : std_logic_vector(S2MM_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2data_tag : std_logic_vector(S2MM_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2addr_tag : std_logic_vector(S2MM_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_data2skid_addr_lsb : std_logic_vector(SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_data2skid_wvalid : std_logic := '0';
signal sig_skid2data_wready : std_logic := '0';
signal sig_data2skid_wdata : std_logic_vector(SF_UPSIZED_SDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_data2skid_wstrb : std_logic_vector((SF_UPSIZED_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_data2skid_wlast : std_logic := '0';
signal sig_skid2axi_wvalid : std_logic := '0';
signal sig_axi2skid_wready : std_logic := '0';
signal sig_skid2axi_wdata : std_logic_vector(S2MM_MDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_skid2axi_wstrb : std_logic_vector((S2MM_MDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_skid2axi_wlast : std_logic := '0';
signal sig_data2wsc_sof : std_logic := '0';
signal sig_data2wsc_eof : std_logic := '0';
signal sig_data2wsc_valid : std_logic := '0';
signal sig_wsc2data_ready : std_logic := '0';
signal sig_data2wsc_eop : std_logic := '0';
signal sig_data2wsc_bytes_rcvd : std_logic_vector(WSC_BYTES_RCVD_WIDTH-1 downto 0) := (others => '0');
signal sig_dbg_data_mux_out : std_logic_vector(31 downto 0) := (others => '0');
signal sig_dbg_data_0 : std_logic_vector(31 downto 0) := (others => '0');
signal sig_dbg_data_1 : std_logic_vector(31 downto 0) := (others => '0');
signal sig_sf2pcc_xfer_valid : std_logic := '0';
signal sig_pcc2sf_xfer_ready : std_logic := '0';
signal sig_sf2pcc_cmd_cmplt : std_logic := '0';
signal sig_sf2pcc_packet_eop : std_logic := '0';
signal sig_sf2pcc_xfer_bytes : std_logic_vector(IBTT_XFER_BYTES_WIDTH-1 downto 0) := (others => '0');
signal sig_ibtt2wdc_tvalid : std_logic := '0';
signal sig_wdc2ibtt_tready : std_logic := '0';
signal sig_ibtt2wdc_tdata : std_logic_vector(SF_UPSIZED_SDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_ibtt2wdc_tstrb : std_logic_vector((SF_UPSIZED_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_ibtt2wdc_tlast : std_logic := '0';
signal sig_ibtt2wdc_eop : std_logic := '0';
signal sig_ibtt2wdc_stbs_asserted : std_logic_vector(7 downto 0) := (others => '0');
signal sig_dre2ibtt_tvalid : std_logic := '0';
signal sig_ibtt2dre_tready : std_logic := '0';
signal sig_dre2ibtt_tdata : std_logic_vector(S2MM_SDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_dre2ibtt_tstrb : std_logic_vector((S2MM_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_dre2ibtt_tlast : std_logic := '0';
signal sig_dre2ibtt_eop : std_logic := '0';
signal sig_dre2mstr_cmd_ready : std_logic := '0';
signal sig_mstr2dre_cmd_valid : std_logic := '0';
signal sig_mstr2dre_tag : std_logic_vector(S2MM_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2dre_dre_src_align : std_logic_vector(S2MM_DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2dre_dre_dest_align : std_logic_vector(S2MM_DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2dre_btt : std_logic_vector(S2MM_BTT_USED-1 downto 0) := (others => '0');
signal sig_mstr2dre_drr : std_logic := '0';
signal sig_mstr2dre_eof : std_logic := '0';
signal sig_mstr2dre_cmd_cmplt : std_logic := '0';
signal sig_mstr2dre_calc_error : std_logic := '0';
signal sig_realign2wdc_eop_error : std_logic := '0';
signal sig_dre2all_halted : std_logic := '0';
signal sig_rst2all_stop_request : std_logic := '0';
signal sig_data2rst_stop_cmplt : std_logic := '0';
signal sig_addr2rst_stop_cmplt : std_logic := '0';
signal sig_data2addr_stop_req : std_logic := '0';
signal sig_wsc2rst_stop_cmplt : std_logic := '0';
signal sig_data2skid_halt : std_logic := '0';
signal skid2dre_wvalid : std_logic := '0';
signal dre2skid_wready : std_logic := '0';
signal skid2dre_wdata : std_logic_vector(S2MM_SDATA_WIDTH-1 downto 0) := (others => '0');
signal skid2dre_wstrb : std_logic_vector((S2MM_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal skid2dre_wlast : std_logic := '0';
signal sig_s2mm_allow_addr_req : std_logic := '0';
signal sig_ok_to_post_wr_addr : std_logic := '0';
signal sig_s2mm_addr_req_posted : std_logic := '0';
signal sig_s2mm_wr_xfer_cmplt : std_logic := '0';
signal sig_s2mm_ld_nxt_len : std_logic := '0';
signal sig_s2mm_wr_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_ibtt2wdc_error : std_logic := '0';
signal sig_sf_strt_addr_offset : std_logic_vector(SF_STRT_OFFSET_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2dre_sf_strt_offset : std_logic_vector(SF_STRT_OFFSET_WIDTH-1 downto 0) := (others => '0');
signal sig_cache2mstr_command : std_logic_vector (7 downto 0);
signal s2mm_awcache_int : std_logic_vector (3 downto 0);
signal s2mm_awuser_int : std_logic_vector (3 downto 0);
begin --(architecture implementation)
-- Debug/Test Port Assignments
s2mm_dbg_data <= sig_dbg_data_mux_out;
-- Note that only the s2mm_dbg_sel(0) is used at this time
sig_dbg_data_mux_out <= sig_dbg_data_1
When (s2mm_dbg_sel(0) = '1')
else sig_dbg_data_0 ;
sig_dbg_data_0 <= X"CAFE1111" ; -- 32 bit Constant indicating S2MM FULL type
sig_dbg_data_1(0) <= sig_cmd_stat_rst_user ;
sig_dbg_data_1(1) <= sig_cmd_stat_rst_int ;
sig_dbg_data_1(2) <= sig_mmap_rst ;
sig_dbg_data_1(3) <= sig_stream_rst ;
sig_dbg_data_1(4) <= sig_cmd2mstr_cmd_valid ;
sig_dbg_data_1(5) <= sig_mst2cmd_cmd_ready ;
sig_dbg_data_1(6) <= sig_stat2wsc_status_ready;
sig_dbg_data_1(7) <= sig_wsc2stat_status_valid;
sig_dbg_data_1(11 downto 8) <= sig_data2wsc_tag ; -- Current TAG of active data transfer
sig_dbg_data_1(15 downto 12) <= sig_wsc2stat_status(3 downto 0); -- Internal status tag field
sig_dbg_data_1(16) <= sig_wsc2stat_status(4) ; -- Internal error
sig_dbg_data_1(17) <= sig_wsc2stat_status(5) ; -- Decode Error
sig_dbg_data_1(18) <= sig_wsc2stat_status(6) ; -- Slave Error
--sig_dbg_data_1(19) <= sig_wsc2stat_status(7) ; -- OKAY
sig_dbg_data_1(20) <= sig_stat2wsc_status_ready ; -- Status Ready Handshake
sig_dbg_data_1(21) <= sig_wsc2stat_status_valid ; -- Status Valid Handshake
sig_dbg_data_1(29 downto 22) <= sig_mstr2data_len ; -- WDC Cmd FIFO LEN input
sig_dbg_data_1(30) <= sig_mstr2data_cmd_valid ; -- WDC Cmd FIFO Valid Inpute
sig_dbg_data_1(31) <= sig_data2mstr_cmd_ready ; -- WDC Cmd FIFO Ready Output
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ADD_DEBUG_EOP
--
-- If Generate Description:
--
-- This IfGen adds in the EOP status marker to the debug
-- vector data when Indet BTT Store and Forward is enabled.
--
------------------------------------------------------------
GEN_ADD_DEBUG_EOP : if (ENABLE_INDET_BTT_SF = 1) generate
begin
sig_dbg_data_1(19) <= sig_wsc2stat_status(31) ; -- EOP Marker
end generate GEN_ADD_DEBUG_EOP;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_DEBUG_EOP
--
-- If Generate Description:
--
-- This IfGen zeros the debug vector bit used for the EOP
-- status marker when Indet BTT Store and Forward is not
-- enabled.
--
------------------------------------------------------------
GEN_NO_DEBUG_EOP : if (ENABLE_INDET_BTT_SF = 0) generate
begin
sig_dbg_data_1(19) <= '0' ; -- EOP Marker
end generate GEN_NO_DEBUG_EOP;
---- End of Debug/Test Support --------------------------------
-- Assign the Address posting control outputs
s2mm_addr_req_posted <= sig_s2mm_addr_req_posted ;
s2mm_wr_xfer_cmplt <= sig_s2mm_wr_xfer_cmplt ;
s2mm_ld_nxt_len <= sig_s2mm_ld_nxt_len ;
s2mm_wr_len <= sig_s2mm_wr_len ;
-- Write Data Channel I/O
s2mm_wvalid <= sig_skid2axi_wvalid;
sig_axi2skid_wready <= s2mm_wready ;
s2mm_wdata <= sig_skid2axi_wdata ;
s2mm_wlast <= sig_skid2axi_wlast ;
GEN_S2MM_TKEEP_ENABLE2 : if C_ENABLE_S2MM_TKEEP = 1 generate
begin
s2mm_wstrb <= sig_skid2axi_wstrb ;
end generate GEN_S2MM_TKEEP_ENABLE2;
GEN_S2MM_TKEEP_DISABLE2 : if C_ENABLE_S2MM_TKEEP = 0 generate
begin
s2mm_wstrb <= (others => '1');
end generate GEN_S2MM_TKEEP_DISABLE2;
GEN_CACHE : if (C_ENABLE_CACHE_USER = 0) generate
begin
-- Cache signal tie-off
s2mm_awcache <= "0011"; -- pre Interface-X guidelines for Masters
s2mm_awuser <= "0000"; -- pre Interface-X guidelines for Masters
sig_s2mm_cache_data <= (others => '0'); --s2mm_cmd_wdata(103 downto 96);
end generate GEN_CACHE;
GEN_CACHE2 : if (C_ENABLE_CACHE_USER = 1) generate
begin
-- Cache signal tie-off
s2mm_awcache <= s2mm_awcache_int; -- pre Interface-X guidelines for Masters
s2mm_awuser <= s2mm_awuser_int; -- pre Interface-X guidelines for Masters
sig_s2mm_cache_data <= s2mm_cmd_wdata(79+(C_S2MM_ADDR_WIDTH-32) downto 72+(C_S2MM_ADDR_WIDTH-32));
-- sig_s2mm_cache_data <= s2mm_cmd_wdata(103 downto 96);
end generate GEN_CACHE2;
-- Internal error output discrete
s2mm_err <= sig_calc2dm_calc_err or sig_data2all_tlast_error;
-- Rip the used portion of the Command Interface Command Data
-- and throw away the padding
sig_s2mm_cmd_wdata <= s2mm_cmd_wdata(S2MM_CMD_WIDTH-1 downto 0);
------------------------------------------------------------
-- Instance: I_RESET
--
-- Description:
-- Reset Block
--
------------------------------------------------------------
I_RESET : entity axi_datamover_v5_1_9.axi_datamover_reset
generic map (
C_STSCMD_IS_ASYNC => S2MM_STSCMD_IS_ASYNC
)
port map (
primary_aclk => s2mm_aclk ,
primary_aresetn => s2mm_aresetn ,
secondary_awclk => s2mm_cmdsts_awclk ,
secondary_aresetn => s2mm_cmdsts_aresetn ,
halt_req => s2mm_halt ,
halt_cmplt => s2mm_halt_cmplt ,
flush_stop_request => sig_rst2all_stop_request ,
data_cntlr_stopped => sig_data2rst_stop_cmplt ,
addr_cntlr_stopped => sig_addr2rst_stop_cmplt ,
aux1_stopped => sig_wsc2rst_stop_cmplt ,
aux2_stopped => LOGIC_HIGH ,
cmd_stat_rst_user => sig_cmd_stat_rst_user ,
cmd_stat_rst_int => sig_cmd_stat_rst_int ,
mmap_rst => sig_mmap_rst ,
stream_rst => sig_stream_rst
);
------------------------------------------------------------
-- Instance: I_CMD_STATUS
--
-- Description:
-- Command and Status Interface Block
--
------------------------------------------------------------
I_CMD_STATUS : entity axi_datamover_v5_1_9.axi_datamover_cmd_status
generic map (
C_ADDR_WIDTH => S2MM_ADDR_WIDTH ,
C_INCLUDE_STSFIFO => INCLUDE_S2MM_STSFIFO ,
C_STSCMD_FIFO_DEPTH => S2MM_STSCMD_FIFO_DEPTH ,
C_STSCMD_IS_ASYNC => S2MM_STSCMD_IS_ASYNC ,
C_CMD_WIDTH => S2MM_CMD_WIDTH ,
C_STS_WIDTH => WSC_STATUS_WIDTH ,
C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => s2mm_aclk ,
secondary_awclk => s2mm_cmdsts_awclk ,
user_reset => sig_cmd_stat_rst_user ,
internal_reset => sig_cmd_stat_rst_int ,
cmd_wvalid => s2mm_cmd_wvalid ,
cmd_wready => s2mm_cmd_wready ,
cmd_wdata => sig_s2mm_cmd_wdata ,
cache_data => sig_s2mm_cache_data ,
sts_wvalid => s2mm_sts_wvalid ,
sts_wready => s2mm_sts_wready ,
sts_wdata => s2mm_sts_wdata ,
sts_wstrb => s2mm_sts_wstrb ,
sts_wlast => s2mm_sts_wlast ,
cmd2mstr_command => sig_cmd2mstr_command ,
cache2mstr_command => sig_cache2mstr_command ,
mst2cmd_cmd_valid => sig_cmd2mstr_cmd_valid ,
cmd2mstr_cmd_ready => sig_mst2cmd_cmd_ready ,
mstr2stat_status => sig_wsc2stat_status ,
stat2mstr_status_ready => sig_stat2wsc_status_ready ,
mst2stst_status_valid => sig_wsc2stat_status_valid
);
------------------------------------------------------------
-- Instance: I_WR_STATUS_CNTLR
--
-- Description:
-- Write Status Controller Block
--
------------------------------------------------------------
I_WR_STATUS_CNTLR : entity axi_datamover_v5_1_9.axi_datamover_wr_status_cntl
generic map (
C_ENABLE_INDET_BTT => ENABLE_INDET_BTT_SF ,
C_SF_BYTES_RCVD_WIDTH => WSC_BYTES_RCVD_WIDTH ,
C_STS_FIFO_DEPTH => WR_STATUS_CNTL_FIFO_DEPTH ,
C_STS_WIDTH => WSC_STATUS_WIDTH ,
C_TAG_WIDTH => S2MM_TAG_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => s2mm_aclk ,
mmap_reset => sig_mmap_rst ,
rst2wsc_stop_request => sig_rst2all_stop_request ,
wsc2rst_stop_cmplt => sig_wsc2rst_stop_cmplt ,
addr2wsc_addr_posted => sig_addr2data_addr_posted ,
s2mm_bresp => s2mm_bresp ,
s2mm_bvalid => s2mm_bvalid ,
s2mm_bready => s2mm_bready ,
calc2wsc_calc_error => sig_calc2dm_calc_err ,
addr2wsc_calc_error => sig_addr2wsc_calc_error ,
addr2wsc_fifo_empty => sig_addr2wsc_cmd_fifo_empty ,
data2wsc_tag => sig_data2wsc_tag ,
data2wsc_calc_error => sig_data2wsc_calc_err ,
data2wsc_last_error => sig_data2wsc_last_err ,
data2wsc_cmd_cmplt => sig_data2wsc_cmd_cmplt ,
data2wsc_valid => sig_data2wsc_valid ,
wsc2data_ready => sig_wsc2data_ready ,
data2wsc_eop => sig_data2wsc_eop ,
data2wsc_bytes_rcvd => sig_data2wsc_bytes_rcvd ,
wsc2stat_status => sig_wsc2stat_status ,
stat2wsc_status_ready => sig_stat2wsc_status_ready ,
wsc2stat_status_valid => sig_wsc2stat_status_valid ,
wsc2mstr_halt_pipe => sig_wsc2mstr_halt_pipe
);
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INCLUDE_PCC
--
-- If Generate Description:
-- Include the normal Predictive Command Calculator function,
-- Store and Forward is not an included feature.
--
--
------------------------------------------------------------
GEN_INCLUDE_PCC : if (ENABLE_INDET_BTT_SF = 0) generate
begin
------------------------------------------------------------
-- Instance: I_MSTR_PCC
--
-- Description:
-- Predictive Command Calculator Block
--
------------------------------------------------------------
I_MSTR_PCC : entity axi_datamover_v5_1_9.axi_datamover_pcc
generic map (
C_IS_MM2S => IS_NOT_MM2S ,
C_DRE_ALIGN_WIDTH => S2MM_DRE_ALIGN_WIDTH ,
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_ADDR_WIDTH => S2MM_ADDR_WIDTH ,
C_STREAM_DWIDTH => S2MM_SDATA_WIDTH ,
C_MAX_BURST_LEN => S2MM_BURST_SIZE ,
C_CMD_WIDTH => S2MM_CMD_WIDTH ,
C_TAG_WIDTH => S2MM_TAG_WIDTH ,
C_BTT_USED => S2MM_BTT_USED ,
C_SUPPORT_INDET_BTT => ENABLE_INDET_BTT_SF ,
C_NATIVE_XFER_WIDTH => SF_UPSIZED_SDATA_WIDTH ,
C_STRT_SF_OFFSET_WIDTH => SF_STRT_OFFSET_WIDTH
)
port map (
-- Clock input
primary_aclk => s2mm_aclk ,
mmap_reset => sig_mmap_rst ,
cmd2mstr_command => sig_cmd2mstr_command ,
cache2mstr_command => sig_cache2mstr_command ,
cmd2mstr_cmd_valid => sig_cmd2mstr_cmd_valid ,
mst2cmd_cmd_ready => sig_mst2cmd_cmd_ready ,
mstr2addr_tag => sig_mstr2addr_tag ,
mstr2addr_addr => sig_mstr2addr_addr ,
mstr2addr_len => sig_mstr2addr_len ,
mstr2addr_size => sig_mstr2addr_size ,
mstr2addr_burst => sig_mstr2addr_burst ,
mstr2addr_cache => sig_mstr2addr_cache ,
mstr2addr_user => sig_mstr2addr_user ,
mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt ,
mstr2addr_calc_error => sig_mstr2addr_calc_error ,
mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid ,
addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready ,
mstr2data_tag => sig_mstr2data_tag ,
mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb ,
mstr2data_len => sig_mstr2data_len ,
mstr2data_strt_strb => sig_mstr2data_strt_strb ,
mstr2data_last_strb => sig_mstr2data_last_strb ,
mstr2data_drr => sig_mstr2data_drr ,
mstr2data_eof => sig_mstr2data_eof ,
mstr2data_sequential => sig_mstr2data_sequential ,
mstr2data_calc_error => sig_mstr2data_calc_error ,
mstr2data_cmd_cmplt => sig_mstr2data_cmd_last ,
mstr2data_cmd_valid => sig_mstr2data_cmd_valid ,
data2mstr_cmd_ready => sig_data2mstr_cmd_ready ,
mstr2data_dre_src_align => open ,
mstr2data_dre_dest_align => open ,
calc_error => sig_calc2dm_calc_err ,
dre2mstr_cmd_ready => sig_dre2mstr_cmd_ready ,
mstr2dre_cmd_valid => sig_mstr2dre_cmd_valid ,
mstr2dre_tag => sig_mstr2dre_tag ,
mstr2dre_dre_src_align => sig_mstr2dre_dre_src_align ,
mstr2dre_dre_dest_align => sig_mstr2dre_dre_dest_align ,
mstr2dre_btt => sig_mstr2dre_btt ,
mstr2dre_drr => sig_mstr2dre_drr ,
mstr2dre_eof => sig_mstr2dre_eof ,
mstr2dre_cmd_cmplt => sig_mstr2dre_cmd_cmplt ,
mstr2dre_calc_error => sig_mstr2dre_calc_error ,
mstr2dre_strt_offset => sig_mstr2dre_sf_strt_offset
);
end generate GEN_INCLUDE_PCC;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INCLUDE_IBTTCC
--
-- If Generate Description:
-- Include the Indeterminate BTT Command Calculator function,
-- Store and Forward is enabled in the S2MM.
--
--
------------------------------------------------------------
GEN_INCLUDE_IBTTCC : if (ENABLE_INDET_BTT_SF = 1) generate
begin
------------------------------------------------------------
-- Instance: I_S2MM_MSTR_SFCC
--
-- Description:
-- Instantiates the Store and Forward Command Calculator
-- Block.
--
------------------------------------------------------------
I_S2MM_MSTR_IBTTCC : entity axi_datamover_v5_1_9.axi_datamover_ibttcc
generic map (
C_SF_XFER_BYTES_WIDTH => IBTT_XFER_BYTES_WIDTH ,
C_DRE_ALIGN_WIDTH => S2MM_DRE_ALIGN_WIDTH ,
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_ADDR_WIDTH => S2MM_ADDR_WIDTH ,
C_STREAM_DWIDTH => S2MM_SDATA_WIDTH ,
C_MAX_BURST_LEN => S2MM_BURST_SIZE ,
C_CMD_WIDTH => S2MM_CMD_WIDTH ,
C_TAG_WIDTH => S2MM_TAG_WIDTH ,
C_BTT_USED => S2MM_BTT_USED ,
C_NATIVE_XFER_WIDTH => SF_UPSIZED_SDATA_WIDTH ,
C_STRT_SF_OFFSET_WIDTH => SF_STRT_OFFSET_WIDTH
)
port map (
-- Clock input
primary_aclk => s2mm_aclk ,
mmap_reset => sig_mmap_rst ,
cmd2mstr_command => sig_cmd2mstr_command ,
cache2mstr_command => sig_cache2mstr_command ,
cmd2mstr_cmd_valid => sig_cmd2mstr_cmd_valid ,
mst2cmd_cmd_ready => sig_mst2cmd_cmd_ready ,
sf2pcc_xfer_valid => sig_sf2pcc_xfer_valid ,
pcc2sf_xfer_ready => sig_pcc2sf_xfer_ready ,
sf2pcc_cmd_cmplt => sig_sf2pcc_cmd_cmplt ,
sf2pcc_packet_eop => sig_sf2pcc_packet_eop ,
sf2pcc_xfer_bytes => sig_sf2pcc_xfer_bytes ,
mstr2addr_tag => sig_mstr2addr_tag ,
mstr2addr_addr => sig_mstr2addr_addr ,
mstr2addr_len => sig_mstr2addr_len ,
mstr2addr_size => sig_mstr2addr_size ,
mstr2addr_burst => sig_mstr2addr_burst ,
mstr2addr_cache => sig_mstr2addr_cache ,
mstr2addr_user => sig_mstr2addr_user ,
mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt ,
mstr2addr_calc_error => sig_mstr2addr_calc_error ,
mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid ,
addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready ,
mstr2data_tag => sig_mstr2data_tag ,
mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb ,
mstr2data_len => sig_mstr2data_len ,
mstr2data_strt_strb => sig_mstr2data_strt_strb ,
mstr2data_last_strb => sig_mstr2data_last_strb ,
mstr2data_drr => sig_mstr2data_drr ,
mstr2data_eof => sig_mstr2data_eof ,
mstr2data_sequential => sig_mstr2data_sequential ,
mstr2data_calc_error => sig_mstr2data_calc_error ,
mstr2data_cmd_cmplt => sig_mstr2data_cmd_last ,
mstr2data_cmd_valid => sig_mstr2data_cmd_valid ,
data2mstr_cmd_ready => sig_data2mstr_cmd_ready ,
calc_error => sig_calc2dm_calc_err ,
dre2mstr_cmd_ready => sig_dre2mstr_cmd_ready ,
mstr2dre_cmd_valid => sig_mstr2dre_cmd_valid ,
mstr2dre_tag => sig_mstr2dre_tag ,
mstr2dre_dre_src_align => sig_mstr2dre_dre_src_align ,
mstr2dre_dre_dest_align => sig_mstr2dre_dre_dest_align ,
mstr2dre_btt => sig_mstr2dre_btt ,
mstr2dre_drr => sig_mstr2dre_drr ,
mstr2dre_eof => sig_mstr2dre_eof ,
mstr2dre_cmd_cmplt => sig_mstr2dre_cmd_cmplt ,
mstr2dre_calc_error => sig_mstr2dre_calc_error ,
mstr2dre_strt_offset => sig_mstr2dre_sf_strt_offset
);
end generate GEN_INCLUDE_IBTTCC;
ENABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(4) = '1' generate
begin
------------------------------------------------------------
-- Instance: I_S2MM_STRM_SKID_BUF
--
-- Description:
-- Instance for the S2MM Skid Buffer which provides for
-- registerd Slave Stream inputs and supports bi-dir
-- throttling.
--
------------------------------------------------------------
I_S2MM_STRM_SKID_BUF : entity axi_datamover_v5_1_9.axi_datamover_skid_buf
generic map (
C_WDATA_WIDTH => S2MM_SDATA_WIDTH
)
port map (
-- System Ports
aclk => s2mm_aclk ,
arst => sig_mmap_rst ,
-- Shutdown control (assert for 1 clk pulse)
skid_stop => sig_data2skid_halt ,
-- Slave Side (Stream Data Input)
s_valid => s2mm_strm_wvalid ,
s_ready => s2mm_strm_wready ,
s_data => s2mm_strm_wdata ,
s_strb => s2mm_strm_wstrb ,
s_last => s2mm_strm_wlast ,
-- Master Side (Stream Data Output
m_valid => skid2dre_wvalid ,
m_ready => dre2skid_wready ,
m_data => skid2dre_wdata ,
m_strb => skid2dre_wstrb ,
m_last => skid2dre_wlast
);
end generate ENABLE_AXIS_SKID;
DISABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(4) = '0' generate
begin
skid2dre_wvalid <= s2mm_strm_wvalid;
s2mm_strm_wready <= dre2skid_wready;
skid2dre_wdata <= s2mm_strm_wdata;
skid2dre_wstrb <= s2mm_strm_wstrb;
skid2dre_wlast <= s2mm_strm_wlast;
end generate DISABLE_AXIS_SKID;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_REALIGNER
--
-- If Generate Description:
-- Omit the S2MM Realignment Engine
--
--
------------------------------------------------------------
GEN_NO_REALIGNER : if (ADD_REALIGNER = 0) generate
begin
-- Set to Always ready for DRE to PCC Command Interface
sig_dre2mstr_cmd_ready <= LOGIC_HIGH;
-- Without DRE and Scatter, the end of packet is the TLAST
--sig_dre2ibtt_eop <= skid2dre_wlast ;
sig_dre2ibtt_eop <= sig_dre2ibtt_tlast ; -- use skid buffered version
-- Cant't detect undrrun/overrun here
sig_realign2wdc_eop_error <= '0';
ENABLE_NOREALIGNER_SKID : if C_ENABLE_SKID_BUF(3) = '1' generate
begin
------------------------------------------------------------
-- Instance: I_NO_REALIGN_SKID_BUF
--
-- Description:
-- Instance for a Skid Buffer which provides for
-- Fmax timing improvement between the Null Absorber and
-- the Write Data controller when the Realigner is not
-- present (no DRE and no Store and Forward case).
--
------------------------------------------------------------
I_NO_REALIGN_SKID_BUF : entity axi_datamover_v5_1_9.axi_datamover_skid_buf
generic map (
C_WDATA_WIDTH => S2MM_SDATA_WIDTH
)
port map (
-- System Ports
aclk => s2mm_aclk ,
arst => sig_mmap_rst ,
-- Shutdown control (assert for 1 clk pulse)
skid_stop => LOGIC_LOW ,
-- Slave Side (Null Absorber Input)
s_valid => skid2dre_wvalid ,
s_ready => dre2skid_wready ,
s_data => skid2dre_wdata ,
s_strb => skid2dre_wstrb ,
s_last => skid2dre_wlast ,
-- Master Side (Stream Data Output to WData Cntlr)
m_valid => sig_dre2ibtt_tvalid ,
m_ready => sig_ibtt2dre_tready ,
m_data => sig_dre2ibtt_tdata ,
m_strb => sig_dre2ibtt_tstrb ,
m_last => sig_dre2ibtt_tlast
);
end generate ENABLE_NOREALIGNER_SKID;
DISABLE_NOREALIGNER_SKID : if C_ENABLE_SKID_BUF(3) = '0' generate
begin
sig_dre2ibtt_tvalid <= skid2dre_wvalid;
dre2skid_wready <= sig_ibtt2dre_tready;
sig_dre2ibtt_tdata <= skid2dre_wdata;
sig_dre2ibtt_tstrb <= skid2dre_wstrb;
sig_dre2ibtt_tlast <= skid2dre_wlast;
end generate DISABLE_NOREALIGNER_SKID;
end generate GEN_NO_REALIGNER;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INCLUDE_REALIGNER
--
-- If Generate Description:
-- Include the S2MM realigner Module. It hosts the S2MM DRE
-- and the Scatter Block.
--
-- Note that the General Purpose Store and Forward Module
-- needs the Scatter function to detect input overrun and
-- underrun events on the AXI Stream input. Thus the Realigner
-- is included whenever the GP Store and Forward is enabled.
--
------------------------------------------------------------
GEN_INCLUDE_REALIGNER : if (ADD_REALIGNER = 1) generate
begin
------------------------------------------------------------
-- Instance: I_S2MM_REALIGNER
--
-- Description:
-- Instance for the S2MM Data Realignment Module.
--
------------------------------------------------------------
I_S2MM_REALIGNER : entity axi_datamover_v5_1_9.axi_datamover_s2mm_realign
generic map (
C_ENABLE_INDET_BTT => ENABLE_INDET_BTT_SF ,
C_INCLUDE_DRE => INCLUDE_S2MM_DRE ,
C_DRE_CNTL_FIFO_DEPTH => DRE_CNTL_FIFO_DEPTH ,
C_DRE_ALIGN_WIDTH => S2MM_DRE_ALIGN_WIDTH ,
C_SUPPORT_SCATTER => DRE_SUPPORT_SCATTER ,
C_BTT_USED => S2MM_BTT_USED ,
C_STREAM_DWIDTH => S2MM_SDATA_WIDTH ,
C_ENABLE_S2MM_TKEEP => C_ENABLE_S2MM_TKEEP ,
C_TAG_WIDTH => S2MM_TAG_WIDTH ,
C_STRT_SF_OFFSET_WIDTH => SF_STRT_OFFSET_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
-- Clock and Reset
primary_aclk => s2mm_aclk ,
mmap_reset => sig_mmap_rst ,
-- Write Data Controller or Store and Forward I/O -------
wdc2dre_wready => sig_ibtt2dre_tready ,
dre2wdc_wvalid => sig_dre2ibtt_tvalid ,
dre2wdc_wdata => sig_dre2ibtt_tdata ,
dre2wdc_wstrb => sig_dre2ibtt_tstrb ,
dre2wdc_wlast => sig_dre2ibtt_tlast ,
dre2wdc_eop => sig_dre2ibtt_eop ,
-- Starting offset output -------------------------------
dre2sf_strt_offset => sig_sf_strt_addr_offset ,
-- AXI Slave Stream In -----------------------------------
s2mm_strm_wready => dre2skid_wready ,
s2mm_strm_wvalid => skid2dre_wvalid ,
s2mm_strm_wdata => skid2dre_wdata ,
s2mm_strm_wstrb => skid2dre_wstrb ,
s2mm_strm_wlast => skid2dre_wlast ,
-- Command Calculator Interface --------------------------
dre2mstr_cmd_ready => sig_dre2mstr_cmd_ready ,
mstr2dre_cmd_valid => sig_mstr2dre_cmd_valid ,
mstr2dre_tag => sig_mstr2dre_tag ,
mstr2dre_dre_src_align => sig_mstr2dre_dre_src_align ,
mstr2dre_dre_dest_align => sig_mstr2dre_dre_dest_align ,
mstr2dre_btt => sig_mstr2dre_btt ,
mstr2dre_drr => sig_mstr2dre_drr ,
mstr2dre_eof => sig_mstr2dre_eof ,
mstr2dre_cmd_cmplt => sig_mstr2dre_cmd_cmplt ,
mstr2dre_calc_error => sig_mstr2dre_calc_error ,
mstr2dre_strt_offset => sig_mstr2dre_sf_strt_offset ,
-- Premature TLAST assertion error flag
dre2all_tlast_error => sig_realign2wdc_eop_error ,
-- DRE Halted Status
dre2all_halted => sig_dre2all_halted
);
end generate GEN_INCLUDE_REALIGNER;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ENABLE_INDET_BTT_SF
--
-- If Generate Description:
-- Include the Indeterminate BTT Logic with specialized
-- Store and Forward function, This also requires the
-- Scatter Engine in the Realigner module.
--
--
------------------------------------------------------------
GEN_ENABLE_INDET_BTT_SF : if (ENABLE_INDET_BTT_SF = 1) generate
begin
-- Pass the Realigner EOP error through
sig_ibtt2wdc_error <= sig_realign2wdc_eop_error;
-- Use only external address posting enable
sig_s2mm_allow_addr_req <= s2mm_allow_addr_req ;
------------------------------------------------------------
-- Instance: I_INDET_BTT
--
-- Description:
-- Instance for the Indeterminate BTT with Store and Forward
-- module.
--
------------------------------------------------------------
I_INDET_BTT : entity axi_datamover_v5_1_9.axi_datamover_indet_btt
generic map (
C_SF_FIFO_DEPTH => SF_FIFO_DEPTH ,
C_IBTT_XFER_BYTES_WIDTH => IBTT_XFER_BYTES_WIDTH ,
C_STRT_OFFSET_WIDTH => SF_STRT_OFFSET_WIDTH ,
C_MAX_BURST_LEN => S2MM_BURST_SIZE ,
C_MMAP_DWIDTH => S2MM_MDATA_WIDTH ,
C_STREAM_DWIDTH => S2MM_SDATA_WIDTH ,
C_ENABLE_SKID_BUF => C_ENABLE_SKID_BUF ,
C_ENABLE_S2MM_TKEEP => C_ENABLE_S2MM_TKEEP ,
C_ENABLE_DRE => INCLUDE_S2MM_DRE ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => s2mm_aclk ,
mmap_reset => sig_mmap_rst ,
ibtt2wdc_stbs_asserted => sig_ibtt2wdc_stbs_asserted,
ibtt2wdc_eop => sig_ibtt2wdc_eop ,
ibtt2wdc_tdata => sig_ibtt2wdc_tdata ,
ibtt2wdc_tstrb => sig_ibtt2wdc_tstrb ,
ibtt2wdc_tlast => sig_ibtt2wdc_tlast ,
ibtt2wdc_tvalid => sig_ibtt2wdc_tvalid ,
wdc2ibtt_tready => sig_wdc2ibtt_tready ,
dre2ibtt_tvalid => sig_dre2ibtt_tvalid ,
ibtt2dre_tready => sig_ibtt2dre_tready ,
dre2ibtt_tdata => sig_dre2ibtt_tdata ,
dre2ibtt_tstrb => sig_dre2ibtt_tstrb ,
dre2ibtt_tlast => sig_dre2ibtt_tlast ,
dre2ibtt_eop => sig_dre2ibtt_eop ,
dre2ibtt_strt_addr_offset => sig_sf_strt_addr_offset ,
sf2pcc_xfer_valid => sig_sf2pcc_xfer_valid ,
pcc2sf_xfer_ready => sig_pcc2sf_xfer_ready ,
sf2pcc_cmd_cmplt => sig_sf2pcc_cmd_cmplt ,
sf2pcc_packet_eop => sig_sf2pcc_packet_eop ,
sf2pcc_xfer_bytes => sig_sf2pcc_xfer_bytes
);
end generate GEN_ENABLE_INDET_BTT_SF;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_SF
--
-- If Generate Description:
-- Bypasses any store and Forward functions.
--
--
------------------------------------------------------------
GEN_NO_SF : if (ENABLE_INDET_BTT_SF = 0 and
ENABLE_GP_SF = 0) generate
begin
-- Use only external address posting enable
sig_s2mm_allow_addr_req <= s2mm_allow_addr_req ;
-- Housekeep unused signal in this case
sig_ok_to_post_wr_addr <= '0' ;
-- SFCC Interface Signals that are not used
sig_pcc2sf_xfer_ready <= '0' ;
sig_sf2pcc_xfer_valid <= '0' ;
sig_sf2pcc_cmd_cmplt <= '0' ;
sig_sf2pcc_packet_eop <= '0' ;
sig_sf2pcc_xfer_bytes <= (others => '0') ;
-- Just pass DRE signals through
sig_ibtt2dre_tready <= sig_wdc2ibtt_tready ;
sig_ibtt2wdc_tvalid <= sig_dre2ibtt_tvalid ;
sig_ibtt2wdc_tdata <= sig_dre2ibtt_tdata ;
sig_ibtt2wdc_tstrb <= sig_dre2ibtt_tstrb ;
sig_ibtt2wdc_tlast <= sig_dre2ibtt_tlast ;
sig_ibtt2wdc_eop <= sig_dre2ibtt_eop ;
sig_ibtt2wdc_stbs_asserted <= (others => '0') ;
-- Pass the Realigner EOP error through
sig_ibtt2wdc_error <= sig_realign2wdc_eop_error;
end generate GEN_NO_SF;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INCLUDE_GP_SF
--
-- If Generate Description:
-- Include the General Purpose Store and Forward module.
-- This If Generate can only be enabled when
-- Indeterminate BTT mode is not enabled. The General Purpose
-- Store and Forward is instantiated in place of the Indet
-- BTT Store and Forward.
--
------------------------------------------------------------
GEN_INCLUDE_GP_SF : if (ENABLE_INDET_BTT_SF = 0 and
ENABLE_GP_SF = 1) generate
begin
-- Merge the external address posting control with the
-- SF address posting control.
sig_s2mm_allow_addr_req <= s2mm_allow_addr_req and
sig_ok_to_post_wr_addr ;
-- Zero these out since Indet BTT is not enabled, they
-- are only used by the WDC in that mode
sig_ibtt2wdc_stbs_asserted <= (others => '0') ;
sig_ibtt2wdc_eop <= '0' ;
-- SFCC Interface Signals that are not used
sig_pcc2sf_xfer_ready <= '0' ;
sig_sf2pcc_xfer_valid <= '0' ;
sig_sf2pcc_cmd_cmplt <= '0' ;
sig_sf2pcc_packet_eop <= '0' ;
sig_sf2pcc_xfer_bytes <= (others => '0') ;
------------------------------------------------------------
-- Instance: I_S2MM_GP_SF
--
-- Description:
-- Instance for the S2MM (Write) General Purpose Store and
-- Forward Module. This module can only be enabled when
-- Indeterminate BTT mode is not enabled. It is connected
-- in place of the IBTT Module when GP SF is enabled.
--
------------------------------------------------------------
I_S2MM_GP_SF : entity axi_datamover_v5_1_9.axi_datamover_wr_sf
generic map (
C_WR_ADDR_PIPE_DEPTH => ADDR_CNTL_FIFO_DEPTH ,
C_SF_FIFO_DEPTH => SF_FIFO_DEPTH ,
C_MMAP_DWIDTH => S2MM_MDATA_WIDTH ,
C_STREAM_DWIDTH => S2MM_SDATA_WIDTH ,
C_STRT_OFFSET_WIDTH => SF_STRT_OFFSET_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
-- Clock and Reset inputs -----------------------------
aclk => s2mm_aclk ,
reset => sig_mmap_rst ,
-- Slave Stream Input --------------------------------
sf2sin_tready => sig_ibtt2dre_tready ,
sin2sf_tvalid => sig_dre2ibtt_tvalid ,
sin2sf_tdata => sig_dre2ibtt_tdata ,
sin2sf_tkeep => sig_dre2ibtt_tstrb ,
sin2sf_tlast => sig_dre2ibtt_tlast ,
sin2sf_error => sig_realign2wdc_eop_error ,
-- Starting Address Offset Input ---------------------
sin2sf_strt_addr_offset => sig_sf_strt_addr_offset ,
-- DataMover Write Side Address Pipelining Control Interface --------
ok_to_post_wr_addr => sig_ok_to_post_wr_addr ,
wr_addr_posted => sig_s2mm_addr_req_posted ,
wr_xfer_cmplt => sig_s2mm_wr_xfer_cmplt ,
wr_ld_nxt_len => sig_s2mm_ld_nxt_len ,
wr_len => sig_s2mm_wr_len ,
-- Write Side Stream Out to DataMover S2MM -------------
sout2sf_tready => sig_wdc2ibtt_tready ,
sf2sout_tvalid => sig_ibtt2wdc_tvalid ,
sf2sout_tdata => sig_ibtt2wdc_tdata ,
sf2sout_tkeep => sig_ibtt2wdc_tstrb ,
sf2sout_tlast => sig_ibtt2wdc_tlast ,
sf2sout_error => sig_ibtt2wdc_error
);
end generate GEN_INCLUDE_GP_SF;
------------------------------------------------------------
-- Instance: I_ADDR_CNTL
--
-- Description:
-- Address Controller Block
--
------------------------------------------------------------
I_ADDR_CNTL : entity axi_datamover_v5_1_9.axi_datamover_addr_cntl
generic map (
C_ADDR_FIFO_DEPTH => ADDR_CNTL_FIFO_DEPTH ,
C_ADDR_WIDTH => S2MM_ADDR_WIDTH ,
C_ADDR_ID => S2MM_AWID_VALUE ,
C_ADDR_ID_WIDTH => S2MM_AWID_WIDTH ,
C_TAG_WIDTH => S2MM_TAG_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => s2mm_aclk ,
mmap_reset => sig_mmap_rst ,
addr2axi_aid => s2mm_awid ,
addr2axi_aaddr => s2mm_awaddr ,
addr2axi_alen => s2mm_awlen ,
addr2axi_asize => s2mm_awsize ,
addr2axi_aburst => s2mm_awburst ,
addr2axi_aprot => s2mm_awprot ,
addr2axi_avalid => s2mm_awvalid ,
addr2axi_acache => s2mm_awcache_int ,
addr2axi_auser => s2mm_awuser_int ,
axi2addr_aready => s2mm_awready ,
mstr2addr_tag => sig_mstr2addr_tag ,
mstr2addr_addr => sig_mstr2addr_addr ,
-- mstr2addr_cache_info => sig_cache2mstr_command ,
mstr2addr_len => sig_mstr2addr_len ,
mstr2addr_size => sig_mstr2addr_size ,
mstr2addr_burst => sig_mstr2addr_burst ,
mstr2addr_cache => sig_mstr2addr_cache ,
mstr2addr_user => sig_mstr2addr_user ,
mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt ,
mstr2addr_calc_error => sig_mstr2addr_calc_error ,
mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid ,
addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready ,
addr2rst_stop_cmplt => sig_addr2rst_stop_cmplt ,
allow_addr_req => sig_s2mm_allow_addr_req ,
addr_req_posted => sig_s2mm_addr_req_posted ,
addr2data_addr_posted => sig_addr2data_addr_posted ,
data2addr_data_rdy => sig_data2addr_data_rdy ,
data2addr_stop_req => sig_data2addr_stop_req ,
addr2stat_calc_error => sig_addr2wsc_calc_error ,
addr2stat_cmd_fifo_empty => sig_addr2wsc_cmd_fifo_empty
);
------------------------------------------------------------
-- Instance: I_WR_DATA_CNTL
--
-- Description:
-- Write Data Controller Block
--
------------------------------------------------------------
I_WR_DATA_CNTL : entity axi_datamover_v5_1_9.axi_datamover_wrdata_cntl
generic map (
C_REALIGNER_INCLUDED => ADD_REALIGNER ,
C_ENABLE_INDET_BTT => ENABLE_INDET_BTT_SF ,
C_SF_BYTES_RCVD_WIDTH => WSC_BYTES_RCVD_WIDTH ,
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_DATA_CNTL_FIFO_DEPTH => WR_DATA_CNTL_FIFO_DEPTH ,
C_MMAP_DWIDTH => S2MM_MDATA_WIDTH ,
C_STREAM_DWIDTH => SF_UPSIZED_SDATA_WIDTH ,
C_TAG_WIDTH => S2MM_TAG_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => s2mm_aclk ,
mmap_reset => sig_mmap_rst ,
rst2data_stop_request => sig_rst2all_stop_request ,
data2addr_stop_req => sig_data2addr_stop_req ,
data2rst_stop_cmplt => sig_data2rst_stop_cmplt ,
wr_xfer_cmplt => sig_s2mm_wr_xfer_cmplt ,
s2mm_ld_nxt_len => sig_s2mm_ld_nxt_len ,
s2mm_wr_len => sig_s2mm_wr_len ,
data2skid_saddr_lsb => sig_data2skid_addr_lsb ,
data2skid_wdata => sig_data2skid_wdata ,
data2skid_wstrb => sig_data2skid_wstrb ,
data2skid_wlast => sig_data2skid_wlast ,
data2skid_wvalid => sig_data2skid_wvalid ,
skid2data_wready => sig_skid2data_wready ,
s2mm_strm_wvalid => sig_ibtt2wdc_tvalid ,
s2mm_strm_wready => sig_wdc2ibtt_tready ,
s2mm_strm_wdata => sig_ibtt2wdc_tdata ,
s2mm_strm_wstrb => sig_ibtt2wdc_tstrb ,
s2mm_strm_wlast => sig_ibtt2wdc_tlast ,
s2mm_strm_eop => sig_ibtt2wdc_eop ,
s2mm_stbs_asserted => sig_ibtt2wdc_stbs_asserted,
realign2wdc_eop_error => sig_ibtt2wdc_error ,
mstr2data_tag => sig_mstr2data_tag ,
mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb ,
mstr2data_len => sig_mstr2data_len ,
mstr2data_strt_strb => sig_mstr2data_strt_strb ,
mstr2data_last_strb => sig_mstr2data_last_strb ,
mstr2data_drr => sig_mstr2data_drr ,
mstr2data_eof => sig_mstr2data_eof ,
mstr2data_sequential => sig_mstr2data_sequential ,
mstr2data_calc_error => sig_mstr2data_calc_error ,
mstr2data_cmd_cmplt => sig_mstr2data_cmd_last ,
mstr2data_cmd_valid => sig_mstr2data_cmd_valid ,
data2mstr_cmd_ready => sig_data2mstr_cmd_ready ,
addr2data_addr_posted => sig_addr2data_addr_posted ,
data2addr_data_rdy => sig_data2addr_data_rdy ,
data2all_tlast_error => sig_data2all_tlast_error ,
data2all_dcntlr_halted => sig_data2all_dcntlr_halted,
data2skid_halt => sig_data2skid_halt ,
data2wsc_tag => sig_data2wsc_tag ,
data2wsc_calc_err => sig_data2wsc_calc_err ,
data2wsc_last_err => sig_data2wsc_last_err ,
data2wsc_cmd_cmplt => sig_data2wsc_cmd_cmplt ,
wsc2data_ready => sig_wsc2data_ready ,
data2wsc_valid => sig_data2wsc_valid ,
data2wsc_eop => sig_data2wsc_eop ,
data2wsc_bytes_rcvd => sig_data2wsc_bytes_rcvd ,
wsc2mstr_halt_pipe => sig_wsc2mstr_halt_pipe
);
--ENABLE_AXIMMAP_SKID : if C_ENABLE_SKID_BUF(4) = '1' generate
--begin
------------------------------------------------------------
-- Instance: I_S2MM_MMAP_SKID_BUF
--
-- Description:
-- Instance for the S2MM Skid Buffer which provides for
-- registered outputs and supports bi-dir throttling.
--
-- This Module also provides Write Data Bus Mirroring and WSTRB
-- Demuxing to match a narrow Stream to a wider MMap Write
-- Channel. By doing this in the skid buffer, the resource
-- utilization of the skid buffer can be minimized by only
-- having to buffer/mux the Stream data width, not the MMap
-- Data width.
--
------------------------------------------------------------
I_S2MM_MMAP_SKID_BUF : entity axi_datamover_v5_1_9.axi_datamover_skid2mm_buf
generic map (
C_MDATA_WIDTH => S2MM_MDATA_WIDTH ,
C_SDATA_WIDTH => SF_UPSIZED_SDATA_WIDTH ,
C_ADDR_LSB_WIDTH => SEL_ADDR_WIDTH
)
port map (
-- System Ports
ACLK => s2mm_aclk ,
ARST => sig_stream_rst ,
-- Slave Side (Wr Data Controller Input Side )
S_ADDR_LSB => sig_data2skid_addr_lsb,
S_VALID => sig_data2skid_wvalid ,
S_READY => sig_skid2data_wready ,
S_Data => sig_data2skid_wdata ,
S_STRB => sig_data2skid_wstrb ,
S_Last => sig_data2skid_wlast ,
-- Master Side (MMap Write Data Output Side)
M_VALID => sig_skid2axi_wvalid ,
M_READY => sig_axi2skid_wready ,
M_Data => sig_skid2axi_wdata ,
M_STRB => sig_skid2axi_wstrb ,
M_Last => sig_skid2axi_wlast
);
--end generate ENABLE_AXIMMAP_SKID;
end implementation;
|
bsd-3-clause
|
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/Pmods/PmodMTDS_v1_0/ipshared/xilinx.com/axi_quad_spi_v3_2/hdl/src/vhdl/comp_defs.vhd
|
2
|
17530
|
--
---- comp_defs - package
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- ** (c) Copyright [2010] - [2012] Xilinx, Inc. All rights reserved.*
-- ** *
-- ** This file contains confidential and proprietary information *
-- ** of Xilinx, Inc. and is protected under U.S. and *
-- ** international copyright and other intellectual property *
-- ** laws. *
-- ** *
-- ** DISCLAIMER *
-- ** This disclaimer is not a license and does not grant any *
-- ** rights to the materials distributed herewith. Except as *
-- ** otherwise provided in a valid license issued to you by *
-- ** Xilinx, and to the maximum extent permitted by applicable *
-- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- ** including negligence, or under any other theory of *
-- ** liability) for any loss or damage of any kind or nature *
-- ** related to, arising under or in connection with these *
-- ** materials, including for any direct, or any indirect, *
-- ** special, incidental, or consequential loss or damage *
-- ** (including loss of data, profits, goodwill, or any type of *
-- ** loss or damage suffered as a result of any action brought *
-- ** by a third party) even if such damage or loss was *
-- ** reasonably foreseeable or Xilinx had been advised of the *
-- ** possibility of the same. *
-- ** *
-- ** CRITICAL APPLICATIONS *
-- ** Xilinx products are not designed or intended to be fail- *
-- ** safe, or for use in any application requiring fail-safe *
-- ** performance, such as life-support or safety devices or *
-- ** systems, Class III medical devices, nuclear facilities, *
-- ** applications related to the deployment of airbags, or any *
-- ** other applications that could lead to death, personal *
-- ** injury, or severe property or environmental damage *
-- ** (individually and collectively, "Critical *
-- ** Applications"). Customer assumes the sole risk and *
-- ** liability of any use of Xilinx products in Critical *
-- ** Applications, subject only to applicable laws and *
-- ** regulations governing limitations on product liability. *
-- ** *
-- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
---- Filename: comp_defs.vhd
---- Version: v3.0
-- Description: Component declarations for all black box netlists generated by
-- running COREGEN when XST elaborated the client core
----
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synopsys translate_off
--library XilinxCoreLib;
--use XilinxCoreLib.all;
-- synopsys translate_on
--library dist_mem_gen_v6_3;
-- use dist_mem_gen_v6_3.all;
--
--library dist_mem_gen_v6_4;
-- use dist_mem_gen_v6_4.all;
library dist_mem_gen_v8_0_10;
use dist_mem_gen_v8_0_10.all;
package comp_defs is
--
-- -- component declaration
-- component dist_mem_gen_v6_3
-- -------------------
-- generic(
-- c_has_clk : integer := 1;
-- c_read_mif : integer := 0;
-- c_has_qspo : integer := 0;
-- c_addr_width : integer := 8;
-- c_width : integer := 15;
-- c_family : string := "virtex7"; -- "virtex6";
-- c_sync_enable : integer := 1;
-- c_depth : integer := 256;
-- c_has_qspo_srst : integer := 1;
-- c_mem_init_file : string := "null.mif";
-- c_default_data : string := "0";
-- ------------------------
-- c_has_qdpo_clk : integer := 0;
-- c_has_qdpo_ce : integer := 0;
-- c_parser_type : integer := 1;
-- c_has_d : integer := 0;
-- c_has_spo : integer := 0;
-- c_reg_a_d_inputs : integer := 0;
-- c_has_we : integer := 0;
-- c_pipeline_stages : integer := 0;
-- c_has_qdpo_rst : integer := 0;
-- c_reg_dpra_input : integer := 0;
-- c_qualify_we : integer := 0;
-- c_has_qdpo_srst : integer := 0;
-- c_has_dpra : integer := 0;
-- c_qce_joined : integer := 0;
-- c_mem_type : integer := 0;
-- c_has_i_ce : integer := 0;
-- c_has_dpo : integer := 0;
-- c_has_spra : integer := 0;
-- c_has_qspo_ce : integer := 0;
-- c_has_qspo_rst : integer := 0;
-- c_has_qdpo : integer := 0
-- -------------------------
-- );
-- port(
-- a : in std_logic_vector(c_addr_width-1-(4*c_has_spra*boolean'pos(c_addr_width > 4)) downto 0) := (others => '0');
-- d : in std_logic_vector(c_width-1 downto 0) := (others => '0');
-- dpra : in std_logic_vector(c_addr_width-1 downto 0) := (others => '0');
-- spra : in std_logic_vector(c_addr_width-1 downto 0) := (others => '0');
-- clk : in std_logic := '0';
-- we : in std_logic := '0';
-- i_ce : in std_logic := '1';
-- qspo_ce : in std_logic := '1';
-- qdpo_ce : in std_logic := '1';
-- qdpo_clk : in std_logic := '0';
-- qspo_rst : in std_logic := '0';
-- qdpo_rst : in std_logic := '0';
-- qspo_srst : in std_logic := '0';
-- qdpo_srst : in std_logic := '0';
-- spo : out std_logic_vector(c_width-1 downto 0);
-- dpo : out std_logic_vector(c_width-1 downto 0);
-- qspo : out std_logic_vector(c_width-1 downto 0);
-- qdpo : out std_logic_vector(c_width-1 downto 0)
-- );
-- end component;
--
-- -- The following tells XST that dist_mem_gen_v6_2 is a black box which
-- -- should be generated. The command given by the value of this attribute
-- -- Note the fully qualified SIM (JAVA class) name that forms the
-- -- basis of the core
--
-- --xcc exclude
--
-- -- attribute box_type : string;
-- -- attribute GENERATOR_DEFAULT : string;
-- --
-- -- attribute box_type of dist_mem_gen_v6_3 : component is "black_box";
-- -- attribute GENERATOR_DEFAULT of dist_mem_gen_v6_3 : component is "generatecore com.xilinx.ip.dist_mem_gen_v6_3.dist_mem_gen_v6_3";
-- --xcc include
--
-- -- component declaration for dist_mem_gen_v6_4
-- component dist_mem_gen_v6_4
-- -------------------
-- generic(
-- c_has_clk : integer := 1;
-- c_read_mif : integer := 0;
-- c_has_qspo : integer := 0;
-- c_addr_width : integer := 8;
-- c_width : integer := 15;
-- c_family : string := "virtex7"; -- "virtex6";
-- c_sync_enable : integer := 1;
-- c_depth : integer := 256;
-- c_has_qspo_srst : integer := 1;
-- c_mem_init_file : string := "null.mif";
-- c_default_data : string := "0";
-- ------------------------
-- c_has_qdpo_clk : integer := 0;
-- c_has_qdpo_ce : integer := 0;
-- c_parser_type : integer := 1;
-- c_has_d : integer := 0;
-- c_has_spo : integer := 0;
-- c_reg_a_d_inputs : integer := 0;
-- c_has_we : integer := 0;
-- c_pipeline_stages : integer := 0;
-- c_has_qdpo_rst : integer := 0;
-- c_reg_dpra_input : integer := 0;
-- c_qualify_we : integer := 0;
-- c_has_qdpo_srst : integer := 0;
-- c_has_dpra : integer := 0;
-- c_qce_joined : integer := 0;
-- c_mem_type : integer := 0;
-- c_has_i_ce : integer := 0;
-- c_has_dpo : integer := 0;
-- c_has_spra : integer := 0;
-- c_has_qspo_ce : integer := 0;
-- c_has_qspo_rst : integer := 0;
-- c_has_qdpo : integer := 0
-- -------------------------
-- );
-- port(
-- a : in std_logic_vector(c_addr_width-1-(4*c_has_spra*boolean'pos(c_addr_width > 4)) downto 0) := (others => '0');
-- d : in std_logic_vector(c_width-1 downto 0) := (others => '0');
-- dpra : in std_logic_vector(c_addr_width-1 downto 0) := (others => '0');
-- spra : in std_logic_vector(c_addr_width-1 downto 0) := (others => '0');
-- clk : in std_logic := '0';
-- we : in std_logic := '0';
-- i_ce : in std_logic := '1';
-- qspo_ce : in std_logic := '1';
-- qdpo_ce : in std_logic := '1';
-- qdpo_clk : in std_logic := '0';
-- qspo_rst : in std_logic := '0';
-- qdpo_rst : in std_logic := '0';
-- qspo_srst : in std_logic := '0';
-- qdpo_srst : in std_logic := '0';
-- spo : out std_logic_vector(c_width-1 downto 0);
-- dpo : out std_logic_vector(c_width-1 downto 0);
-- qspo : out std_logic_vector(c_width-1 downto 0);
-- qdpo : out std_logic_vector(c_width-1 downto 0)
-- );
-- end component;
--
-- -- The following tells XST that dist_mem_gen_v6_4 is a black box which
-- -- should be generated. The command given by the value of this attribute
-- -- Note the fully qualified SIM (JAVA class) name that forms the
-- -- basis of the core
--
-- --xcc exclude
--
-- -- attribute box_type of dist_mem_gen_v6_4 : component is "black_box";
-- -- attribute GENERATOR_DEFAULT of dist_mem_gen_v6_4 : component is "generatecore com.xilinx.ip.dist_mem_gen_v6_4.dist_mem_gen_v6_4";
--
-- --xcc include
-- 1/8/2013 added the latest version of dist_mem_gen_v8_0_10
-- component declaration for dist_mem_gen_v8_0_10
component dist_mem_gen_v8_0_10
-------------------
generic(
C_HAS_CLK : integer := 1;
C_READ_MIF : integer := 0;
C_HAS_QSPO : integer := 0;
C_ADDR_WIDTH : integer := 8;
C_WIDTH : integer := 15;
C_FAMILY : string := "virtex7"; -- "virtex6";
C_SYNC_ENABLE : integer := 1;
C_DEPTH : integer := 256;
C_HAS_QSPO_SRST : integer := 1;
C_MEM_INIT_FILE : string := "null.mif";
C_DEFAULT_DATA : string := "0";
------------------------
C_HAS_QDPO_CLK : integer := 0;
C_HAS_QDPO_CE : integer := 0;
C_PARSER_TYPE : integer := 1;
C_HAS_D : integer := 0;
C_HAS_SPO : integer := 0;
C_REG_A_D_INPUTS : integer := 0;
C_HAS_WE : integer := 0;
C_PIPELINE_STAGES : integer := 0;
C_HAS_QDPO_RST : integer := 0;
C_REG_DPRA_INPUT : integer := 0;
C_QUALIFY_WE : integer := 0;
C_HAS_QDPO_SRST : integer := 0;
C_HAS_DPRA : integer := 0;
C_QCE_JOINED : integer := 0;
C_MEM_TYPE : integer := 0;
C_HAS_I_CE : integer := 0;
C_HAS_DPO : integer := 0;
-- C_HAS_SPRA : integer := 0; -- removed from dist mem gen core
C_HAS_QSPO_CE : integer := 0;
C_HAS_QSPO_RST : integer := 0;
C_HAS_QDPO : integer := 0
-------------------------
);
port(
a : in std_logic_vector(c_addr_width-1 downto 0) := (others => '0');
d : in std_logic_vector(c_width-1 downto 0) := (others => '0');
dpra : in std_logic_vector(c_addr_width-1 downto 0) := (others => '0');
-- spra : in std_logic_vector(c_addr_width-1 downto 0) := (others => '0'); -- 2/12/2013
clk : in std_logic := '0';
we : in std_logic := '0';
i_ce : in std_logic := '1';
qspo_ce : in std_logic := '1';
qdpo_ce : in std_logic := '1';
qdpo_clk : in std_logic := '0';
qspo_rst : in std_logic := '0';
qdpo_rst : in std_logic := '0';
qspo_srst : in std_logic := '0';
qdpo_srst : in std_logic := '0';
spo : out std_logic_vector(c_width-1 downto 0);
dpo : out std_logic_vector(c_width-1 downto 0);
qspo : out std_logic_vector(c_width-1 downto 0);
qdpo : out std_logic_vector(c_width-1 downto 0)
);
end component;
-- The following tells XST that dist_mem_gen_v8_0_10 is a black box which
-- should be generated. The command given by the value of this attribute
-- Note the fully qualified SIM (JAVA class) name that forms the
-- basis of the core
--xcc exclude
-- attribute box_type of dist_mem_gen_v8_0_10 : component is "black_box";
-- attribute GENERATOR_DEFAULT of dist_mem_gen_v8_0_10 : component is "generatecore com.xilinx.ip.dist_mem_gen_v8_0_10.dist_mem_gen_v8_0_10";
--xcc include
end comp_defs;
|
bsd-3-clause
|
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/usb2device_v1_0/src/axi_dma_0/axi_sg_v4_1_2/hdl/src/vhdl/axi_sg_intrpt.vhd
|
7
|
28217
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_intrpt.vhd
-- Description: This entity handles interrupt coalescing
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_sg_v4_1_2;
use axi_sg_v4_1_2.axi_sg_pkg.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.clog2;
use lib_pkg_v1_0_2.lib_pkg.max2;
-------------------------------------------------------------------------------
entity axi_sg_intrpt is
generic(
C_INCLUDE_CH1 : integer range 0 to 1 := 1 ;
-- Include or exclude MM2S primary data path
-- 0 = Exclude MM2S primary data path
-- 1 = Include MM2S primary data path
C_INCLUDE_CH2 : integer range 0 to 1 := 1 ;
-- Include or exclude S2MM primary data path
-- 0 = Exclude S2MM primary data path
-- 1 = Include S2MM primary data path
C_INCLUDE_DLYTMR : integer range 0 to 1 := 1 ;
-- Include/Exclude interrupt delay timer
-- 0 = Exclude Delay timer
-- 1 = Include Delay timer
C_DLYTMR_RESOLUTION : integer range 1 to 100000 := 125
-- Interrupt Delay Timer resolution in usec
);
port (
-- Secondary Clock and Reset
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
ch1_irqthresh_decr : in std_logic ;-- CR567661 --
ch1_irqthresh_rstdsbl : in std_logic ;-- CR572013 --
ch1_dlyirq_dsble : in std_logic ; --
ch1_irqdelay_wren : in std_logic ; --
ch1_irqdelay : in std_logic_vector(7 downto 0) ; --
ch1_irqthresh_wren : in std_logic ; --
ch1_irqthresh : in std_logic_vector(7 downto 0) ; --
ch1_packet_sof : in std_logic ; --
ch1_packet_eof : in std_logic ; --
ch1_ioc_irq_set : out std_logic ; --
ch1_dly_irq_set : out std_logic ; --
ch1_irqdelay_status : out std_logic_vector(7 downto 0) ; --
ch1_irqthresh_status : out std_logic_vector(7 downto 0) ; --
--
ch2_irqthresh_decr : in std_logic ;-- CR567661 --
ch2_irqthresh_rstdsbl : in std_logic ;-- CR572013 --
ch2_dlyirq_dsble : in std_logic ; --
ch2_irqdelay_wren : in std_logic ; --
ch2_irqdelay : in std_logic_vector(7 downto 0) ; --
ch2_irqthresh_wren : in std_logic ; --
ch2_irqthresh : in std_logic_vector(7 downto 0) ; --
ch2_packet_sof : in std_logic ; --
ch2_packet_eof : in std_logic ; --
ch2_ioc_irq_set : out std_logic ; --
ch2_dly_irq_set : out std_logic ; --
ch2_irqdelay_status : out std_logic_vector(7 downto 0) ; --
ch2_irqthresh_status : out std_logic_vector(7 downto 0) --
);
end axi_sg_intrpt;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_intrpt is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Delay interrupt fast counter width
constant FAST_COUNT_WIDTH : integer := clog2(C_DLYTMR_RESOLUTION+1);
-- Delay interrupt fast counter terminal count
constant FAST_COUNT_TC : std_logic_vector(FAST_COUNT_WIDTH-1 downto 0)
:= std_logic_vector(to_unsigned(
(C_DLYTMR_RESOLUTION-1),FAST_COUNT_WIDTH));
-- Delay interrupt fast counter zero value
constant ZERO_FAST_COUNT : std_logic_vector(FAST_COUNT_WIDTH-1 downto 0)
:= (others => '0');
constant ZERO_VALUE : std_logic_vector(7 downto 0) := (others => '0');
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal ch1_thresh_count : std_logic_vector(7 downto 0) := ONE_THRESHOLD;
signal ch1_dly_irq_set_i : std_logic := '0';
signal ch1_ioc_irq_set_i : std_logic := '0';
signal ch1_delay_count : std_logic_vector(7 downto 0) := (others => '0');
signal ch1_delay_cnt_en : std_logic := '0';
signal ch1_dly_fast_cnt : std_logic_vector(FAST_COUNT_WIDTH-1 downto 0) := (others => '0');
signal ch1_dly_fast_incr : std_logic := '0';
signal ch1_delay_zero : std_logic := '0';
signal ch1_delay_tc : std_logic := '0';
signal ch1_disable_delay : std_logic := '0';
signal ch2_thresh_count : std_logic_vector(7 downto 0) := ONE_THRESHOLD;
signal ch2_dly_irq_set_i : std_logic := '0';
signal ch2_ioc_irq_set_i : std_logic := '0';
signal ch2_delay_count : std_logic_vector(7 downto 0) := (others => '0');
signal ch2_delay_cnt_en : std_logic := '0';
signal ch2_dly_fast_cnt : std_logic_vector(FAST_COUNT_WIDTH-1 downto 0) := (others => '0');
signal ch2_dly_fast_incr : std_logic := '0';
signal ch2_delay_zero : std_logic := '0';
signal ch2_delay_tc : std_logic := '0';
signal ch2_disable_delay : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Transmit channel included therefore generate transmit interrupt logic
GEN_INCLUDE_MM2S : if C_INCLUDE_CH1 = 1 generate
begin
REG_THRESH_COUNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_thresh_count <= ONE_THRESHOLD;
ch1_ioc_irq_set_i <= '0';
-- New Threshold set by CPU OR delay interrupt event occured.
-- CR572013 - added ability to disable threshold count reset on delay timeout
-- elsif(ch1_irqthresh_wren = '1' or ch1_dly_irq_set_i = '1') then
elsif( (ch1_irqthresh_wren = '1')
or (ch1_dly_irq_set_i = '1' and ch1_irqthresh_rstdsbl = '0')) then
ch1_thresh_count <= ch1_irqthresh;
ch1_ioc_irq_set_i <= '0';
-- IOC event then...
elsif(ch1_irqthresh_decr = '1')then --CR567661
-- Threshold at zero, reload threshold and drive ioc
-- interrupt.
if(ch1_thresh_count = ONE_THRESHOLD)then
ch1_thresh_count <= ch1_irqthresh;
ch1_ioc_irq_set_i <= '1';
else
ch1_thresh_count <= std_logic_vector(unsigned(ch1_thresh_count(7 downto 0)) - 1);
ch1_ioc_irq_set_i <= '0';
end if;
else
ch1_thresh_count <= ch1_thresh_count;
ch1_ioc_irq_set_i <= '0';
end if;
end if;
end process REG_THRESH_COUNT;
-- Pass current threshold count out to DMASR
ch1_irqthresh_status <= ch1_thresh_count;
ch1_ioc_irq_set <= ch1_ioc_irq_set_i;
---------------------------------------------------------------------------
-- Generate Delay Interrupt Timers
---------------------------------------------------------------------------
GEN_CH1_DELAY_INTERRUPT : if C_INCLUDE_DLYTMR = 1 generate
begin
GEN_CH1_FAST_COUNTER : if C_DLYTMR_RESOLUTION /= 1 generate
begin
---------------------------------------------------------------------------
-- Delay interrupt high resolution timer
---------------------------------------------------------------------------
REG_DLY_FAST_CNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- CR565366 - need to reset on sof due to chanes for CR
-- if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1')then
-- CR570398 - need to reset delay timer each time a new delay value is written.
-- if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1' or ch1_packet_sof = '1')then
if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1'
or ch1_packet_sof = '1' or ch1_irqdelay_wren = '1')then
ch1_dly_fast_cnt <= FAST_COUNT_TC;
ch1_dly_fast_incr <= '0';
elsif(ch1_dly_fast_cnt = ZERO_FAST_COUNT)then
ch1_dly_fast_cnt <= FAST_COUNT_TC;
ch1_dly_fast_incr <= '1';
else
ch1_dly_fast_cnt <= std_logic_vector(unsigned(ch1_dly_fast_cnt(FAST_COUNT_WIDTH-1 downto 0)) - 1);
ch1_dly_fast_incr <= '0';
end if;
end if;
end process REG_DLY_FAST_CNT;
end generate GEN_CH1_FAST_COUNTER;
GEN_CH1_NO_FAST_COUNTER : if C_DLYTMR_RESOLUTION = 1 generate
REG_DLY_FAST_CNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- CR565366 - need to reset on sof due to chanes for CR
-- if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1')then
-- CR570398 - need to reset delay timer each time a new delay value is written.
-- if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1' or ch1_packet_sof = '1')then
if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1'
or ch1_packet_sof = '1' or ch1_irqdelay_wren = '1')then
ch1_dly_fast_incr <= '0';
else
ch1_dly_fast_incr <= '1';
end if;
end if;
end process REG_DLY_FAST_CNT;
end generate GEN_CH1_NO_FAST_COUNTER;
-- DMACR Delay value set to zero - disable delay interrupt
ch1_delay_zero <= '1' when ch1_irqdelay = ZERO_DELAY
else '0';
-- Delay Terminal Count reached (i.e. Delay count = DMACR delay value)
ch1_delay_tc <= '1' when ch1_delay_count = ch1_irqdelay
and ch1_delay_zero = '0'
and ch1_packet_sof = '0'
else '0';
-- 1 clock earlier delay counter disable to prevent count
-- increment on TC hit.
ch1_disable_delay <= '1' when ch1_delay_zero = '1'
or ch1_dlyirq_dsble = '1'
or ch1_dly_irq_set_i = '1'
else '0';
---------------------------------------------------------------------------
-- Delay interrupt low resolution timer
---------------------------------------------------------------------------
REG_DELAY_COUNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- CR565366 need to reset on SOF now due to CR change
-- if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1')then
-- CR570398 - need to reset delay timer each time a new delay value is written.
-- if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1' or ch1_packet_sof = '1')then
if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1'
or ch1_packet_sof = '1' or ch1_irqdelay_wren = '1')then
ch1_delay_count <= (others => '0');
ch1_dly_irq_set_i <= '0';
elsif(ch1_dly_fast_incr = '1' and ch1_delay_tc = '1')then
ch1_delay_count <= (others => '0');
ch1_dly_irq_set_i <= '1';
elsif(ch1_dly_fast_incr = '1')then
ch1_delay_count <= std_logic_vector(unsigned(ch1_delay_count(7 downto 0)) + 1);
ch1_dly_irq_set_i <= '0';
else
ch1_delay_count <= ch1_delay_count;
ch1_dly_irq_set_i <= '0';
end if;
end if;
end process REG_DELAY_COUNT;
-- Pass current delay count to DMASR
ch1_irqdelay_status <= ch1_delay_count;
ch1_dly_irq_set <= ch1_dly_irq_set_i;
-- Enable control for delay counter
REG_DELAY_CNT_ENABLE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or ch1_disable_delay = '1')then
ch1_delay_cnt_en <= '0';
-- CR565366 simulatenous sof/eof which occurs for small packets causes delay timer
-- to not enable
-- elsif(ch1_packet_sof = '1')then
-- stop counting if already counting and receive an sof and
-- not end of another packet
elsif(ch1_delay_cnt_en = '1' and ch1_packet_sof = '1'
and ch1_packet_eof = '0')then
ch1_delay_cnt_en <= '0';
elsif(ch1_packet_eof = '1')then
ch1_delay_cnt_en <= '1';
end if;
end if;
end process REG_DELAY_CNT_ENABLE;
end generate GEN_CH1_DELAY_INTERRUPT;
---------------------------------------------------------------------------
-- Delay interrupt NOT included
---------------------------------------------------------------------------
GEN_NO_CH1_DELAY_INTR : if C_INCLUDE_DLYTMR = 0 generate
begin
ch1_dly_irq_set <= '0';
ch1_dly_irq_set_i <= '0';
ch1_irqdelay_status <= (others => '0');
end generate GEN_NO_CH1_DELAY_INTR;
end generate GEN_INCLUDE_MM2S;
-- Receive channel included therefore generate receive interrupt logic
GEN_INCLUDE_S2MM : if C_INCLUDE_CH2 = 1 generate
begin
REG_THRESH_COUNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_thresh_count <= ONE_THRESHOLD;
ch2_ioc_irq_set_i <= '0';
-- New Threshold set by CPU OR delay interrupt event occured.
-- CR572013 - added ability to disable threshold count reset on delay timeout
-- elsif(ch2_irqthresh_wren = '1' or ch2_dly_irq_set_i = '1') then
elsif( (ch2_irqthresh_wren = '1')
or (ch2_dly_irq_set_i = '1' and ch2_irqthresh_rstdsbl = '0')) then
ch2_thresh_count <= ch2_irqthresh;
ch2_ioc_irq_set_i <= '0';
-- IOC event then...
elsif(ch2_irqthresh_decr = '1')then --CR567661
-- Threshold at zero, reload threshold and drive ioc
-- interrupt.
if(ch2_thresh_count = ONE_THRESHOLD)then
ch2_thresh_count <= ch2_irqthresh;
ch2_ioc_irq_set_i <= '1';
else
ch2_thresh_count <= std_logic_vector(unsigned(ch2_thresh_count(7 downto 0)) - 1);
ch2_ioc_irq_set_i <= '0';
end if;
else
ch2_thresh_count <= ch2_thresh_count;
ch2_ioc_irq_set_i <= '0';
end if;
end if;
end process REG_THRESH_COUNT;
-- Pass current threshold count out to DMASR
ch2_irqthresh_status <= ch2_thresh_count;
ch2_ioc_irq_set <= ch2_ioc_irq_set_i;
---------------------------------------------------------------------------
-- Generate Delay Interrupt Timers
---------------------------------------------------------------------------
GEN_CH2_DELAY_INTERRUPT : if C_INCLUDE_DLYTMR = 1 generate
begin
---------------------------------------------------------------------------
-- Delay interrupt high resolution timer
---------------------------------------------------------------------------
GEN_CH2_FAST_COUNTER : if C_DLYTMR_RESOLUTION /= 1 generate
begin
REG_DLY_FAST_CNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- CR565366 - need to reset on sof due to chanes for CR
-- if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1')then
-- CR570398 - need to reset delay timer each time a new delay value is written.
-- if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1' or ch2_packet_sof = '1')then
if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1'
or ch2_packet_sof = '1' or ch2_irqdelay_wren = '1')then
ch2_dly_fast_cnt <= FAST_COUNT_TC;
ch2_dly_fast_incr <= '0';
elsif(ch2_dly_fast_cnt = ZERO_FAST_COUNT)then
ch2_dly_fast_cnt <= FAST_COUNT_TC;
ch2_dly_fast_incr <= '1';
else
ch2_dly_fast_cnt <= std_logic_vector(unsigned(ch2_dly_fast_cnt(FAST_COUNT_WIDTH-1 downto 0)) - 1);
ch2_dly_fast_incr <= '0';
end if;
end if;
end process REG_DLY_FAST_CNT;
end generate GEN_CH2_FAST_COUNTER;
GEN_CH2_NO_FAST_COUNTER : if C_DLYTMR_RESOLUTION = 1 generate
REG_DLY_FAST_CNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- CR565366 - need to reset on sof due to chanes for CR
-- if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1')then
-- CR570398 - need to reset delay timer each time a new delay value is written.
-- if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1' or ch2_packet_sof = '1')then
if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1'
or ch2_packet_sof = '1' or ch2_irqdelay_wren = '1')then
ch2_dly_fast_incr <= '0';
else
ch2_dly_fast_incr <= '1';
end if;
end if;
end process REG_DLY_FAST_CNT;
end generate GEN_CH2_NO_FAST_COUNTER;
-- DMACR Delay value set to zero - disable delay interrupt
ch2_delay_zero <= '1' when ch2_irqdelay = ZERO_DELAY
else '0';
-- Delay Terminal Count reached (i.e. Delay count = DMACR delay value)
ch2_delay_tc <= '1' when ch2_delay_count = ch2_irqdelay
and ch2_delay_zero = '0'
and ch2_packet_sof = '0'
else '0';
-- 1 clock earlier delay counter disable to prevent count
-- increment on TC hit.
ch2_disable_delay <= '1' when ch2_delay_zero = '1'
or ch2_dlyirq_dsble = '1'
or ch2_dly_irq_set_i = '1'
else '0';
---------------------------------------------------------------------------
-- Delay interrupt low resolution timer
---------------------------------------------------------------------------
REG_DELAY_COUNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- CR565366 need to reset on SOF now due to CR change
-- if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1')then
-- CR570398 - need to reset delay timer each time a new delay value is written.
-- if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1' or ch2_packet_sof = '1')then
if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1'
or ch2_packet_sof = '1' or ch2_irqdelay_wren = '1')then
ch2_delay_count <= (others => '0');
ch2_dly_irq_set_i <= '0';
elsif(ch2_dly_fast_incr = '1' and ch2_delay_tc = '1')then
ch2_delay_count <= (others => '0');
ch2_dly_irq_set_i <= '1';
elsif(ch2_dly_fast_incr = '1')then
ch2_delay_count <= std_logic_vector(unsigned(ch2_delay_count(7 downto 0)) + 1);
ch2_dly_irq_set_i <= '0';
else
ch2_delay_count <= ch2_delay_count;
ch2_dly_irq_set_i <= '0';
end if;
end if;
end process REG_DELAY_COUNT;
-- Pass current delay count to DMASR
ch2_irqdelay_status <= ch2_delay_count;
ch2_dly_irq_set <= ch2_dly_irq_set_i;
-- Enable control for delay counter
REG_DELAY_CNT_ENABLE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or ch2_disable_delay = '1')then
ch2_delay_cnt_en <= '0';
-- CR565366 simulatenous sof/eof which occurs for small packets causes delay timer
-- to not enable
-- elsif(ch2_packet_sof = '1')then
-- stop counting if already counting and receive an sof and
-- not end of another packet
elsif(ch2_delay_cnt_en = '1' and ch2_packet_sof = '1'
and ch2_packet_eof = '0')then
ch2_delay_cnt_en <= '0';
elsif(ch2_packet_eof = '1')then
ch2_delay_cnt_en <= '1';
end if;
end if;
end process REG_DELAY_CNT_ENABLE;
end generate GEN_CH2_DELAY_INTERRUPT;
---------------------------------------------------------------------------
-- Delay interrupt NOT included
---------------------------------------------------------------------------
GEN_NO_CH2_DELAY_INTR : if C_INCLUDE_DLYTMR = 0 generate
begin
ch2_dly_irq_set <= '0';
ch2_dly_irq_set_i <= '0';
ch2_irqdelay_status <= (others => '0');
end generate GEN_NO_CH2_DELAY_INTR;
end generate GEN_INCLUDE_S2MM;
-- Transmit channel not included therefore associated outputs to zero
GEN_EXCLUDE_MM2S : if C_INCLUDE_CH1 = 0 generate
begin
ch1_ioc_irq_set <= '0';
ch1_dly_irq_set <= '0';
ch1_irqdelay_status <= (others => '0');
ch1_irqthresh_status <= (others => '0');
end generate GEN_EXCLUDE_MM2S;
-- Receive channel not included therefore associated outputs to zero
GEN_EXCLUDE_S2MM : if C_INCLUDE_CH2 = 0 generate
begin
ch2_ioc_irq_set <= '0';
ch2_dly_irq_set <= '0';
ch2_irqdelay_status <= (others => '0');
ch2_irqthresh_status <= (others => '0');
end generate GEN_EXCLUDE_S2MM;
end implementation;
|
bsd-3-clause
|
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/usb2device_v1_0/src/axi_dma_0/axi_sg_v4_1_2/hdl/src/vhdl/axi_sg_ftch_mngr.vhd
|
7
|
25964
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_ftch_mngr.vhd
-- Description: This entity manages fetching of descriptors.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_sg_v4_1_2;
use axi_sg_v4_1_2.axi_sg_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_ftch_mngr is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0;
C_INCLUDE_CH1 : integer range 0 to 1 := 1;
-- Include or Exclude channel 1 scatter gather engine
-- 0 = Exclude Channel 1 SG Engine
-- 1 = Include Channel 1 SG Engine
C_INCLUDE_CH2 : integer range 0 to 1 := 1;
-- Include or Exclude channel 2 scatter gather engine
-- 0 = Exclude Channel 2 SG Engine
-- 1 = Include Channel 2 SG Engine
C_SG_CH1_WORDS_TO_FETCH : integer range 4 to 16 := 8;
-- Number of words to fetch for channel 1
C_SG_CH2_WORDS_TO_FETCH : integer range 4 to 16 := 8;
-- Number of words to fetch for channel 1
C_SG_FTCH_DESC2QUEUE : integer range 0 to 8 := 0;
-- Number of descriptors to fetch and queue for each channel.
-- A value of zero excludes the fetch queues.
C_SG_CH1_ENBL_STALE_ERROR : integer range 0 to 1 := 1;
-- Enable or disable stale descriptor check
-- 0 = Disable stale descriptor error check
-- 1 = Enable stale descriptor error check
C_SG_CH2_ENBL_STALE_ERROR : integer range 0 to 1 := 1
-- Enable or disable stale descriptor check
-- 0 = Disable stale descriptor error check
-- 1 = Enable stale descriptor error check
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Channel 1 Control and Status --
ch1_run_stop : in std_logic ; --
ch1_desc_flush : in std_logic ; --
ch1_updt_done : in std_logic ; --
ch1_ftch_idle : out std_logic ; --
ch1_ftch_active : out std_logic ; --
ch1_ftch_interr_set : out std_logic ; --
ch1_ftch_slverr_set : out std_logic ; --
ch1_ftch_decerr_set : out std_logic ; --
ch1_ftch_err_early : out std_logic ; --
ch1_ftch_stale_desc : out std_logic ; --
ch1_tailpntr_enabled : in std_logic ; --
ch1_taildesc_wren : in std_logic ; --
ch1_taildesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch1_nxtdesc_wren : in std_logic ; --
ch1_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch1_ftch_queue_empty : in std_logic ; --
ch1_ftch_queue_full : in std_logic ; --
ch1_ftch_pause : in std_logic ; --
--
-- Channel 2 Control and Status --
ch2_run_stop : in std_logic ; --
ch2_updt_done : in std_logic ; --
ch2_desc_flush : in std_logic ; --
ch2_ftch_idle : out std_logic ; --
ch2_ftch_active : out std_logic ; --
ch2_ftch_interr_set : out std_logic ; --
ch2_ftch_slverr_set : out std_logic ; --
ch2_ftch_decerr_set : out std_logic ; --
ch2_ftch_err_early : out std_logic ; --
ch2_ftch_stale_desc : out std_logic ; --
ch2_tailpntr_enabled : in std_logic ; --
ch2_taildesc_wren : in std_logic ; --
ch2_taildesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch2_nxtdesc_wren : in std_logic ; --
ch2_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch2_ftch_queue_empty : in std_logic ; --
ch2_ftch_queue_full : in std_logic ; --
ch2_ftch_pause : in std_logic ; --
ch2_eof_detected : in std_logic ;
tail_updt : in std_logic ;
tail_updt_latch : out std_logic ;
ch2_sg_idle : out std_logic ;
--
nxtdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
--
-- Read response for detecting slverr, decerr early --
m_axi_sg_rresp : in std_logic_vector(1 downto 0) ; --
m_axi_sg_rvalid : in std_logic ; --
--
-- User Command Interface Ports (AXI Stream) --
s_axis_ftch_cmd_tvalid : out std_logic ; --
s_axis_ftch_cmd_tready : in std_logic ; --
s_axis_ftch_cmd_tdata : out std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
--
-- User Status Interface Ports (AXI Stream) --
m_axis_ftch_sts_tvalid : in std_logic ; --
m_axis_ftch_sts_tready : out std_logic ; --
m_axis_ftch_sts_tdata : in std_logic_vector(7 downto 0) ; --
m_axis_ftch_sts_tkeep : in std_logic_vector(0 downto 0) ; --
mm2s_err : in std_logic ; --
--
--
ftch_cmnd_wr : out std_logic ; --
ftch_cmnd_data : out std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
ftch_stale_desc : in std_logic ; --
updt_error : in std_logic ; --
ftch_error : out std_logic ; --
ftch_error_addr : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
bd_eq : out std_logic
);
end axi_sg_ftch_mngr;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_ftch_mngr is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal ftch_cmnd_wr_i : std_logic := '0';
signal ftch_cmnd_data_i : std_logic_vector
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0)
:= (others => '0');
signal ch1_sg_idle : std_logic := '0';
signal ch1_fetch_address : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0)
:= (others => '0');
signal ch2_sg_idle_int : std_logic := '0';
signal ch2_fetch_address : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0)
:= (others => '0');
signal ftch_done : std_logic := '0';
signal ftch_error_i : std_logic := '0';
signal ftch_interr : std_logic := '0';
signal ftch_slverr : std_logic := '0';
signal ftch_decerr : std_logic := '0';
signal ftch_error_early : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
ftch_cmnd_wr <= ftch_cmnd_wr_i;
ftch_cmnd_data <= ftch_cmnd_data_i;
ftch_error <= ftch_error_i;
ch2_sg_idle <= ch2_sg_idle_int;
-------------------------------------------------------------------------------
-- Scatter Gather Fetch State Machine
-------------------------------------------------------------------------------
I_FTCH_SG : entity axi_sg_v4_1_2.axi_sg_ftch_sm
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL ,
C_INCLUDE_CH1 => C_INCLUDE_CH1 ,
C_INCLUDE_CH2 => C_INCLUDE_CH2 ,
C_SG_CH1_WORDS_TO_FETCH => C_SG_CH1_WORDS_TO_FETCH ,
C_SG_CH2_WORDS_TO_FETCH => C_SG_CH2_WORDS_TO_FETCH ,
C_SG_FTCH_DESC2QUEUE => C_SG_FTCH_DESC2QUEUE ,
C_SG_CH1_ENBL_STALE_ERROR => C_SG_CH1_ENBL_STALE_ERROR ,
C_SG_CH2_ENBL_STALE_ERROR => C_SG_CH2_ENBL_STALE_ERROR
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
updt_error => updt_error ,
-- Channel 1 Control and Status
ch1_run_stop => ch1_run_stop ,
ch1_updt_done => ch1_updt_done ,
ch1_desc_flush => ch1_desc_flush ,
ch1_sg_idle => ch1_sg_idle ,
ch1_tailpntr_enabled => ch1_tailpntr_enabled ,
ch1_ftch_queue_empty => ch1_ftch_queue_empty ,
ch1_ftch_queue_full => ch1_ftch_queue_full ,
ch1_fetch_address => ch1_fetch_address ,
ch1_ftch_active => ch1_ftch_active ,
ch1_ftch_idle => ch1_ftch_idle ,
ch1_ftch_interr_set => ch1_ftch_interr_set ,
ch1_ftch_slverr_set => ch1_ftch_slverr_set ,
ch1_ftch_decerr_set => ch1_ftch_decerr_set ,
ch1_ftch_err_early => ch1_ftch_err_early ,
ch1_ftch_stale_desc => ch1_ftch_stale_desc ,
ch1_ftch_pause => ch1_ftch_pause ,
-- Channel 2 Control and Status
ch2_run_stop => ch2_run_stop ,
ch2_updt_done => ch2_updt_done ,
ch2_desc_flush => ch2_desc_flush ,
ch2_sg_idle => ch2_sg_idle_int ,
ch2_tailpntr_enabled => ch2_tailpntr_enabled ,
ch2_ftch_queue_empty => ch2_ftch_queue_empty ,
ch2_ftch_queue_full => ch2_ftch_queue_full ,
ch2_fetch_address => ch2_fetch_address ,
ch2_ftch_active => ch2_ftch_active ,
ch2_ftch_idle => ch2_ftch_idle ,
ch2_ftch_interr_set => ch2_ftch_interr_set ,
ch2_ftch_slverr_set => ch2_ftch_slverr_set ,
ch2_ftch_decerr_set => ch2_ftch_decerr_set ,
ch2_ftch_err_early => ch2_ftch_err_early ,
ch2_ftch_stale_desc => ch2_ftch_stale_desc ,
ch2_ftch_pause => ch2_ftch_pause ,
-- Transfer Request
ftch_cmnd_wr => ftch_cmnd_wr_i ,
ftch_cmnd_data => ftch_cmnd_data_i ,
-- Transfer Status
ftch_done => ftch_done ,
ftch_error => ftch_error_i ,
ftch_interr => ftch_interr ,
ftch_slverr => ftch_slverr ,
ftch_decerr => ftch_decerr ,
ftch_stale_desc => ftch_stale_desc ,
ftch_error_addr => ftch_error_addr ,
ftch_error_early => ftch_error_early
);
-------------------------------------------------------------------------------
-- Scatter Gather Fetch Pointer Manager
-------------------------------------------------------------------------------
I_FTCH_PNTR_MNGR : entity axi_sg_v4_1_2.axi_sg_ftch_pntr
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_INCLUDE_CH1 => C_INCLUDE_CH1 ,
C_INCLUDE_CH2 => C_INCLUDE_CH2
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
nxtdesc => nxtdesc ,
-------------------------------
-- CHANNEL 1
-------------------------------
ch1_run_stop => ch1_run_stop ,
ch1_desc_flush => ch1_desc_flush ,--CR568950
-- CURDESC update on run/stop assertion (from ftch_sm)
ch1_curdesc => ch1_curdesc ,
-- TAILDESC update on CPU write (from axi_dma_reg_module)
ch1_tailpntr_enabled => ch1_tailpntr_enabled ,
ch1_taildesc_wren => ch1_taildesc_wren ,
ch1_taildesc => ch1_taildesc ,
-- NXTDESC update on descriptor fetch (from axi_sg_ftchq_if)
ch1_nxtdesc_wren => ch1_nxtdesc_wren ,
-- Current address of descriptor to fetch
ch1_fetch_address => ch1_fetch_address ,
ch1_sg_idle => ch1_sg_idle ,
-------------------------------
-- CHANNEL 2
-------------------------------
ch2_run_stop => ch2_run_stop ,
ch2_desc_flush => ch2_desc_flush ,--CR568950
ch2_eof_detected => ch2_eof_detected ,
-- CURDESC update on run/stop assertion (from ftch_sm)
ch2_curdesc => ch2_curdesc ,
-- TAILDESC update on CPU write (from axi_dma_reg_module)
ch2_tailpntr_enabled => ch2_tailpntr_enabled ,
ch2_taildesc_wren => ch2_taildesc_wren ,
ch2_taildesc => ch2_taildesc ,
tail_updt_latch => tail_updt_latch ,
tail_updt => tail_updt ,
ch2_updt_done => ch2_updt_done ,
-- NXTDESC update on descriptor fetch (from axi_sg_ftchq_if)
ch2_nxtdesc_wren => ch2_nxtdesc_wren ,
-- Current address of descriptor to fetch
ch2_fetch_address => ch2_fetch_address ,
ch2_sg_idle => ch2_sg_idle_int ,
bd_eq => bd_eq
);
-------------------------------------------------------------------------------
-- Scatter Gather Fetch Command / Status Interface
-------------------------------------------------------------------------------
I_FTCH_CMDSTS_IF : entity axi_sg_v4_1_2.axi_sg_ftch_cmdsts_if
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Fetch command write interface from fetch sm
ftch_cmnd_wr => ftch_cmnd_wr_i ,
ftch_cmnd_data => ftch_cmnd_data_i ,
-- Read response for detecting slverr, decerr early
m_axi_sg_rresp => m_axi_sg_rresp ,
m_axi_sg_rvalid => m_axi_sg_rvalid ,
-- User Command Interface Ports (AXI Stream)
s_axis_ftch_cmd_tvalid => s_axis_ftch_cmd_tvalid ,
s_axis_ftch_cmd_tready => s_axis_ftch_cmd_tready ,
s_axis_ftch_cmd_tdata => s_axis_ftch_cmd_tdata ,
-- User Status Interface Ports (AXI Stream)
m_axis_ftch_sts_tvalid => m_axis_ftch_sts_tvalid ,
m_axis_ftch_sts_tready => m_axis_ftch_sts_tready ,
m_axis_ftch_sts_tdata => m_axis_ftch_sts_tdata ,
m_axis_ftch_sts_tkeep => m_axis_ftch_sts_tkeep ,
-- Scatter Gather Fetch Status
mm2s_err => mm2s_err ,
ftch_done => ftch_done ,
ftch_error => ftch_error_i ,
ftch_interr => ftch_interr ,
ftch_slverr => ftch_slverr ,
ftch_decerr => ftch_decerr ,
ftch_error_early => ftch_error_early
);
end implementation;
|
bsd-3-clause
|
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/rgb2dpvid_v1_0/src/rgb2dpvid.vhd
|
2
|
4161
|
-------------------------------------------------------------------------------
--
-- File: rgb2dpvid.vhd
-- Author: Mihaita Nagy
-- Original Project: RGB to Displayport Video
-- Date: 12 November 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- Converts a kDataWidth-bit RGB interface (VGA compatible) given as input to a
-- Displayport Video interface
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity rgb2dpvid is
generic(
-- Width of the input data bus
kDataWidth : integer := 24
);
port(
-- RGB interface
PixelClk : in std_logic;
pData : in std_logic_vector((kDataWidth-1) downto 0);
pHSync : in std_logic;
pVSync : in std_logic;
pVde : in std_logic;
-- Displayport Video interface
pVidClk : out std_logic;
pVidPixel0 : out std_logic_vector(47 downto 0);
pVidHSync : out std_logic;
pVidVSync : out std_logic;
pVidOddEven : out std_logic;
pVidRst : out std_logic;
pVidEnable : out std_logic
);
end rgb2dpvid;
architecture rtl of rgb2dpvid is
begin
-- Video clock the same as the pixel clock
pVidClk <= PixelClk;
-- Odd/Even qualifier not used
pVidOddEven <= '0';
-- Also reset is not used
pVidRst <= '0';
-- Synchronous process to distribute the video data
SyncIns: process(PixelClk)
begin
if rising_edge(PixelClk) then
pVidHSync <= pHSync;
pVidVSync <= pVSync;
pVidEnable <= pVde;
-- Red component
pVidPixel0(47 downto 47-((kDataWidth/3)-1)) <= pData((kDataWidth-1) downto (kDataWidth-kDataWidth/3));
pVidPixel0(39 downto 32) <= (others => '0');
-- Green component
pVidPixel0(31 downto 31-((kDataWidth/3)-1)) <= pData(((kDataWidth-2*kDataWidth/3)-1) downto 0);
pVidPixel0(23 downto 16) <= (others => '0');
-- Blue component
pVidPixel0(15 downto 15-((kDataWidth/3)-1)) <= pData(((kDataWidth-kDataWidth/3)-1) downto (kDataWidth-2*kDataWidth/3));
pVidPixel0(7 downto 0) <= (others => '0');
end if;
end process SyncIns;
end rtl;
|
bsd-3-clause
|
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/Pmods/PmodMTDS_v1_0/ipshared/xilinx.com/axi_quad_spi_v3_2/hdl/src/vhdl/soft_reset.vhd
|
3
|
13266
|
--soft_reset.vhd v1.01a
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2006-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: soft_reset.vhd
-- Version: v1_00_a
-- Description: This VHDL design file is the Soft Reset Service
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- Library definitions
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
-------------------------------------------------------------------------------
entity soft_reset is
generic (
C_SIPIF_DWIDTH : integer := 32;
-- Width of the write data bus
C_RESET_WIDTH : integer := 4
-- Width of triggered reset in Bus Clocks
);
port (
-- Inputs From the IPIF Bus
Bus2IP_Reset : in std_logic;
Bus2IP_Clk : in std_logic;
Bus2IP_WrCE : in std_logic;
Bus2IP_Data : in std_logic_vector(0 to C_SIPIF_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to (C_SIPIF_DWIDTH/8)-1);
-- Final Device Reset Output
Reset2IP_Reset : out std_logic;
-- Status Reply Outputs to the Bus
Reset2Bus_WrAck : out std_logic;
Reset2Bus_Error : out std_logic;
Reset2Bus_ToutSup : out std_logic
);
end soft_reset ;
-------------------------------------------------------------------------------
architecture implementation of soft_reset is
-------------------------------------------------------------------------------
-- Function Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Type Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- Module Software Reset screen value for write data
-- This requires a Hex 'A' to be written to ativate the S/W reset port
constant RESET_MATCH : std_logic_vector(0 to 3) := "1010";
-- Required BE index to be active during Reset activation
constant BE_MATCH : integer := 3;
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
signal sm_reset : std_logic;
signal error_reply : std_logic;
signal reset_wrack : std_logic;
signal reset_error : std_logic;
signal reset_trig : std_logic;
signal wrack : std_logic;
signal wrack_ff_chain : std_logic;
signal flop_q_chain : std_logic_vector(0 to C_RESET_WIDTH);
--signal bus2ip_wrce_d1 : std_logic;
signal data_is_non_reset_match : std_logic;
signal sw_rst_cond : std_logic;
signal sw_rst_cond_d1 : std_logic;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
begin
-- Misc assignments
Reset2Bus_WrAck <= reset_wrack;
Reset2Bus_Error <= reset_error;
Reset2Bus_ToutSup <= sm_reset; -- Suppress a data phase timeout when
-- a commanded reset is active.
reset_wrack <= (reset_error or wrack);-- and Bus2IP_WrCE;
reset_error <= data_is_non_reset_match and Bus2IP_WrCE;
Reset2IP_Reset <= Bus2IP_Reset or sm_reset;
---------------------------------------------------------------------------------
---- Register WRCE for use in creating a strobe pulse
---------------------------------------------------------------------------------
--REG_WRCE : process(Bus2IP_Clk)
-- begin
-- if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1')then
-- if(Bus2IP_Reset = '1')then
-- bus2ip_wrce_d1 <= '0';
-- else
-- bus2ip_wrce_d1 <= Bus2IP_WrCE;
-- end if;
-- end if;
-- end process REG_WRCE;
--
-------------------------------------------------------------------------------
-- Start the S/W reset state machine as a result of an IPIF Bus write to
-- the Reset port and the data on the DBus inputs matching the Reset
-- match value. If the value on the data bus input does not match the
-- designated reset key, an error acknowledge is generated.
-------------------------------------------------------------------------------
--DETECT_SW_RESET : process (Bus2IP_Clk)
-- begin
-- if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') then
-- if (Bus2IP_Reset = '1') then
-- error_reply <= '0';
-- reset_trig <= '0';
-- elsif (Bus2IP_WrCE = '1'
-- and Bus2IP_BE(BE_MATCH) = '1'
-- and Bus2IP_Data(28 to 31) = RESET_MATCH) then
-- error_reply <= '0';
-- reset_trig <= Bus2IP_WrCE and not bus2ip_wrce_d1;
-- elsif (Bus2IP_WrCE = '1') then
-- error_reply <= '1';
-- reset_trig <= '0';
-- else
-- error_reply <= '0';
-- reset_trig <= '0';
-- end if;
-- end if;
-- end process DETECT_SW_RESET;
data_is_non_reset_match <=
'0' when (Bus2IP_Data(C_SIPIF_DWIDTH-4 to C_SIPIF_DWIDTH-1) = RESET_MATCH
and Bus2IP_BE(BE_MATCH) = '1')
else '1';
--------------------------------------------------------------------------------
-- SW Reset
--------------------------------------------------------------------------------
----------------------------------------------------------------------------
sw_rst_cond <= Bus2IP_WrCE and not data_is_non_reset_match;
--
RST_PULSE_PROC : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') Then
if (Bus2IP_Reset = '1') Then
sw_rst_cond_d1 <= '0';
reset_trig <= '0';
else
sw_rst_cond_d1 <= sw_rst_cond;
reset_trig <= sw_rst_cond and not sw_rst_cond_d1;
end if;
end if;
End process;
-------------------------------------------------------------------------------
-- RESET_FLOPS:
-- This FORGEN implements the register chain used to create
-- the parameterizable reset pulse width.
-------------------------------------------------------------------------------
RESET_FLOPS : for index in 0 to C_RESET_WIDTH-1 generate
flop_q_chain(0) <= '0';
RST_FLOPS : FDRSE
port map(
Q => flop_q_chain(index+1), -- : out std_logic;
C => Bus2IP_Clk, -- : in std_logic;
CE => '1', -- : in std_logic;
D => flop_q_chain(index), -- : in std_logic;
R => Bus2IP_Reset, -- : in std_logic;
S => reset_trig -- : in std_logic
);
end generate RESET_FLOPS;
-- Use the last flop output for the commanded reset pulse
sm_reset <= flop_q_chain(C_RESET_WIDTH);
wrack_ff_chain <= flop_q_chain(C_RESET_WIDTH) and
not(flop_q_chain(C_RESET_WIDTH-1));
-- Register the Write Acknowledge for the Reset write
-- This is generated at the end of the reset pulse. This
-- keeps the Slave busy until the commanded reset completes.
FF_WRACK : FDRSE
port map(
Q => wrack, -- : out std_logic;
C => Bus2IP_Clk, -- : in std_logic;
CE => '1', -- : in std_logic;
D => wrack_ff_chain, -- : in std_logic;
R => Bus2IP_Reset, -- : in std_logic;
S => '0' -- : in std_logic
);
end implementation;
|
bsd-3-clause
|
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/rgb2dvi/src/ClockGen.vhd
|
9
|
8885
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11/03/2014 06:27:16 PM
-- Design Name:
-- Module Name: ClockGen - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity ClockGen is
Generic (
kClkRange : natural := 1; -- MULT_F = kClkRange*5 (choose >=120MHz=1, >=60MHz=2, >=40MHz=3, >=30MHz=4, >=25MHz=5
kClkPrimitive : string := "MMCM"); -- "MMCM" or "PLL" to instantiate, if kGenerateSerialClk true
Port (
PixelClkIn : in STD_LOGIC;
PixelClkOut : out STD_LOGIC;
SerialClk : out STD_LOGIC;
aRst : in STD_LOGIC;
aLocked : out STD_LOGIC);
end ClockGen;
architecture Behavioral of ClockGen is
component SyncAsync is
Generic (
kResetTo : std_logic := '0'; --value when reset and upon init
kStages : natural := 2); --double sync by default
Port (
aReset : in STD_LOGIC; -- active-high asynchronous reset
aIn : in STD_LOGIC;
OutClk : in STD_LOGIC;
oOut : out STD_LOGIC);
end component SyncAsync;
component ResetBridge is
Generic (
kPolarity : std_logic := '1');
Port (
aRst : in STD_LOGIC; -- asynchronous reset; active-high, if kPolarity=1
OutClk : in STD_LOGIC;
oRst : out STD_LOGIC);
end component ResetBridge;
signal PixelClkInX1, PixelClkInX5, FeedbackClk : std_logic;
signal aLocked_int, pLocked, pRst, pLockWasLost : std_logic;
signal pLocked_q : std_logic_vector(2 downto 0) := (others => '1');
begin
-- We need a reset bridge to use the asynchronous aRst signal to reset our circuitry
-- and decrease the chance of metastability. The signal pRst can be used as
-- asynchronous reset for any flip-flop in the PixelClkIn domain, since it will be de-asserted
-- synchronously.
LockLostReset: ResetBridge
generic map (
kPolarity => '1')
port map (
aRst => aRst,
OutClk => PixelClkIn,
oRst => pRst);
PLL_LockSyncAsync: SyncAsync
port map (
aReset => '0',
aIn => aLocked_int,
OutClk => PixelClkIn,
oOut => pLocked);
PLL_LockLostDetect: process(PixelClkIn)
begin
if (pRst = '1') then
pLocked_q <= (others => '1');
pLockWasLost <= '1';
elsif Rising_Edge(PixelClkIn) then
pLocked_q <= pLocked_q(pLocked_q'high-1 downto 0) & pLocked;
pLockWasLost <= (not pLocked_q(0) or not pLocked_q(1)) and pLocked_q(2); --two-pulse
end if;
end process;
-- The TMDS Clk channel carries a character-rate frequency reference
-- In a single Clk period a whole character (10 bits) is transmitted
-- on each data channel. For deserialization of data channel a faster,
-- serial clock needs to be generated. In 7-series architecture an
-- OSERDESE2 primitive doing a 10:1 deserialization in DDR mode needs
-- a fast 5x clock and a slow 1x clock. These two clocks are generated
-- below with an MMCME2_ADV/PLLE2_ADV.
-- Caveats:
-- 1. The primitive uses a multiply-by-5 and divide-by-1 to generate
-- a 5x fast clock.
-- While changes in the frequency of the TMDS Clk are tracked by the
-- MMCM, for some TMDS Clk frequencies the datasheet specs for the VCO
-- frequency limits are not met. In other words, there is no single
-- set of MMCM multiply and divide values that can work for the whole
-- range of resolutions and pixel clock frequencies.
-- For example: MMCM_FVCOMIN = 600 MHz
-- MMCM_FVCOMAX = 1200 MHz for Artix-7 -1 speed grade
-- while FVCO = FIN * MULT_F
-- The TMDS Clk for 720p resolution in 74.25 MHz
-- FVCO = 74.25 * 10 = 742.5 MHz, which is between FVCOMIN and FVCOMAX
-- However, the TMDS Clk for 1080p resolution in 148.5 MHz
-- FVCO = 148.5 * 10 = 1480 MHZ, which is above FVCOMAX
-- In the latter case, MULT_F = 5, DIVIDE_F = 5, DIVIDE = 1 would result
-- in a correct VCO frequency, while still generating 5x and 1x clocks
-- 2. The MMCM+BUFIO+BUFR combination results in the highest possible
-- frequencies. PLLE2_ADV could work only with BUFGs, which limits
-- the maximum achievable frequency. The reason is that only the MMCM
-- has dedicated route to BUFIO.
-- If a PLLE2_ADV with BUFGs are used a second CLKOUTx can be used to
-- generate the 1x clock.
GenMMCM: if kClkPrimitive = "MMCM" generate
DVI_ClkGenerator: MMCME2_ADV
generic map
(BANDWIDTH => "OPTIMIZED",
CLKOUT4_CASCADE => FALSE,
COMPENSATION => "ZHOLD",
STARTUP_WAIT => FALSE,
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT_F => real(kClkRange) * 5.0,
CLKFBOUT_PHASE => 0.000,
CLKFBOUT_USE_FINE_PS => FALSE,
CLKOUT0_DIVIDE_F => real(kClkRange) * 1.0,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT0_USE_FINE_PS => FALSE,
CLKOUT1_DIVIDE => kClkRange * 5,
CLKOUT1_DUTY_CYCLE => 0.5,
CLKOUT1_PHASE => 0.0,
CLKOUT1_USE_FINE_PS => FALSE,
CLKIN1_PERIOD => real(kClkRange) * 6.0,
REF_JITTER1 => 0.010)
port map
-- Output clocks
(
CLKFBOUT => FeedbackClk,
CLKFBOUTB => open,
CLKOUT0 => PixelClkInX5,
CLKOUT0B => open,
CLKOUT1 => PixelClkInX1,
CLKOUT1B => open,
CLKOUT2 => open,
CLKOUT2B => open,
CLKOUT3 => open,
CLKOUT3B => open,
CLKOUT4 => open,
CLKOUT5 => open,
CLKOUT6 => open,
-- Input clock control
CLKFBIN => FeedbackClk,
CLKIN1 => PixelClkIn,
CLKIN2 => '0',
-- Tied to always select the primary input clock
CLKINSEL => '1',
-- Ports for dynamic reconfiguration
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DO => open,
DRDY => open,
DWE => '0',
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => aLocked_int,
CLKINSTOPPED => open,
CLKFBSTOPPED => open,
PWRDWN => '0',
RST => pLockWasLost);
end generate;
GenPLL: if kClkPrimitive /= "MMCM" generate
DVI_ClkGenerator: PLLE2_ADV
generic map (
BANDWIDTH => "OPTIMIZED",
CLKFBOUT_MULT => (kClkRange + 1) * 5,
CLKFBOUT_PHASE => 0.000,
CLKIN1_PERIOD => real(kClkRange) * 6.25,
COMPENSATION => "ZHOLD",
DIVCLK_DIVIDE => 1,
REF_JITTER1 => 0.010,
STARTUP_WAIT => "FALSE",
CLKOUT0_DIVIDE => (kClkRange + 1) * 1,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => (kClkRange + 1) * 5,
CLKOUT1_DUTY_CYCLE => 0.5,
CLKOUT1_PHASE => 0.0)
port map
-- Output clocks
(
CLKFBOUT => FeedbackClk,
CLKOUT0 => PixelClkInX5,
CLKOUT1 => PixelClkInX1,
CLKOUT2 => open,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
-- Input clock control
CLKFBIN => FeedbackClk,
CLKIN1 => PixelClkIn,
CLKIN2 => '0',
-- Tied to always select the primary input clock
CLKINSEL => '1',
-- Ports for dynamic reconfiguration
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DO => open,
DRDY => open,
DWE => '0',
-- Other control and status signals
LOCKED => aLocked_int,
PWRDWN => '0',
RST => pLockWasLost);
end generate;
--No buffering used
--These clocks will only drive the OSERDESE2 primitives
SerialClk <= PixelClkInX5;
PixelClkOut <= PixelClkInX1;
aLocked <= aLocked_int;
end Behavioral;
|
bsd-3-clause
|
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/Pmods/PmodMTDS_v1_0/ipshared/xilinx.com/axi_quad_spi_v3_2/hdl/src/vhdl/axi_quad_spi.vhd
|
2
|
82124
|
-------------------------------------------------------------------------------
-- axi_quad_spi.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- ** (c) Copyright [2010] - [2012] Xilinx, Inc. All rights reserved.*
-- ** *
-- ** This file contains confidential and proprietary information *
-- ** of Xilinx, Inc. and is protected under U.S. and *
-- ** international copyright and other intellectual property *
-- ** laws. *
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-- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_quad_spi.vhd
-- Version: v3.0
-- Description: This is the top-level design file for the AXI Quad SPI core.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.conv_std_logic_vector;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
use ieee.std_logic_misc.all;
-- library unsigned is used for overloading of "=" which allows integer to
-- be compared to std_logic_vector
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.FD;
use unisim.vcomponents.FDRE;
use UNISIM.vcomponents.all;
library axi_lite_ipif_v3_0_4;
use axi_lite_ipif_v3_0_4.axi_lite_ipif;
use axi_lite_ipif_v3_0_4.ipif_pkg.all;
library axi_quad_spi_v3_2_8;
use axi_quad_spi_v3_2_8.all;
-------------------------------------------------------------------------------
entity axi_quad_spi is
generic(
-- Async_Clk parameter is added only for Vivado, it is not used in the design, this is
-- NON HDL parameter
Async_Clk : integer := 0;
-- General Parameters
C_FAMILY : string := "virtex7";
C_SELECT_XPM : integer := 1;
C_SUB_FAMILY : string := "virtex7";
C_INSTANCE : string := "axi_quad_spi_inst";
-------------------------
C_SPI_MEM_ADDR_BITS : integer := 24; -- allowed values are 24 or 32 only and used in XIP mode
C_TYPE_OF_AXI4_INTERFACE : integer range 0 to 1 := 0;--default AXI4 Lite Legacy mode
C_XIP_MODE : integer range 0 to 1 := 0;--default NON XIP Mode
C_UC_FAMILY : integer range 0 to 1 := 0;--default NON XIP Mode
--C_AXI4_CLK_PS : integer := 10000;--AXI clock period
--C_EXT_SPI_CLK_PS : integer := 10000;--ext clock period
C_FIFO_DEPTH : integer := 256;-- allowed 0,16,256.
C_SCK_RATIO : integer := 16;--default in legacy mode
C_NUM_SS_BITS : integer range 1 to 32:= 1;
C_NUM_TRANSFER_BITS : integer := 8; -- allowed 8, 16, 32
-------------------------
C_SPI_MODE : integer range 0 to 2 := 0; -- used for differentiating
-- Standard, Dual or Quad mode
-- in Ports as well as internal
-- functionality
C_USE_STARTUP : integer range 0 to 1 := 1; --
C_SPI_MEMORY : integer range 0 to 3 := 1; -- 0 - mixed mode,
-- 1 - winbond,
-- 2 - numonyx
-- 3 - spansion
-- used to differentiate
-- internal look up table
-- for commands.
-------------------------
-- AXI4 Lite Interface Parameters *as max address is 7c, only 7 address bits are used
C_S_AXI_ADDR_WIDTH : integer range 7 to 7 := 7;
C_S_AXI_DATA_WIDTH : integer range 32 to 32 := 32;
-------------------------
--*C_BASEADDR : std_logic_vector := x"FFFFFFFF";
--*C_HIGHADDR : std_logic_vector := x"00000000";
-------------------------
-- AXI4 Full Interface Parameters *as max 24 bits of address are supported on SPI interface, only 24 address bits are used
C_S_AXI4_ADDR_WIDTH : integer ;--range 24 to 24 := 24;
C_S_AXI4_DATA_WIDTH : integer range 32 to 32 := 32;
C_S_AXI4_ID_WIDTH : integer range 1 to 16 := 4 ;
C_SHARED_STARTUP : integer range 0 to 1 := 0;
-------------------------
-- To FIX CR# 685366, below lines are added again in RTL (Vivado Requirement), but these parameters are not used in the core RTL
C_S_AXI4_BASEADDR : std_logic_vector := x"FFFFFFFF";
C_S_AXI4_HIGHADDR : std_logic_vector := x"00000000";
-------------------------
C_LSB_STUP : integer range 0 to 1 := 0
);
port(
-- external async clock for SPI interface logic
ext_spi_clk : in std_logic;
-- axi4 lite interface clk and reset signals
s_axi_aclk : in std_logic;
s_axi_aresetn : in std_logic;
-- axi4 full interface clk and reset signals
s_axi4_aclk : in std_logic;
s_axi4_aresetn : in std_logic;
-------------------------------
-------------------------------
--*axi4 lite port interface* --
-------------------------------
-------------------------------
-- axi write address channel signals
---------------
s_axi_awaddr : in std_logic_vector (6 downto 0);--((C_S_AXI_ADDR_WIDTH-1) downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
---------------
-- axi write data channel signals
---------------
s_axi_wdata : in std_logic_vector(31 downto 0); -- ((C_S_AXI_DATA_WIDTH-1) downto 0);
s_axi_wstrb : in std_logic_vector(3 downto 0); -- (((C_S_AXI_DATA_WIDTH/8)-1) downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
---------------
-- axi write response channel signals
---------------
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
---------------
-- axi read address channel signals
---------------
s_axi_araddr : in std_logic_vector(6 downto 0); -- ((C_S_AXI_ADDR_WIDTH-1) downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
---------------
-- axi read address channel signals
---------------
s_axi_rdata : out std_logic_vector(31 downto 0); -- ((C_S_AXI_DATA_WIDTH-1) downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
-------------------------------
-------------------------------
--*axi4 full port interface* --
-------------------------------
------------------------------------
-- axi write address Channel Signals
------------------------------------
s_axi4_awid : in std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0);
s_axi4_awaddr : in std_logic_vector((C_SPI_MEM_ADDR_BITS-1) downto 0); --((C_S_AXI4_ADDR_WIDTH-1) downto 0);
s_axi4_awlen : in std_logic_vector(7 downto 0);
s_axi4_awsize : in std_logic_vector(2 downto 0);
s_axi4_awburst : in std_logic_vector(1 downto 0);
s_axi4_awlock : in std_logic; -- not supported in design
s_axi4_awcache : in std_logic_vector(3 downto 0);-- not supported in design
s_axi4_awprot : in std_logic_vector(2 downto 0);-- not supported in design
s_axi4_awvalid : in std_logic;
s_axi4_awready : out std_logic;
---------------------------------------
-- axi4 full write Data Channel Signals
---------------------------------------
s_axi4_wdata : in std_logic_vector(31 downto 0); -- ((C_S_AXI4_DATA_WIDTH-1)downto 0);
s_axi4_wstrb : in std_logic_vector(3 downto 0); -- (((C_S_AXI4_DATA_WIDTH/8)-1) downto 0);
s_axi4_wlast : in std_logic;
s_axi4_wvalid : in std_logic;
s_axi4_wready : out std_logic;
-------------------------------------------
-- axi4 full write Response Channel Signals
-------------------------------------------
s_axi4_bid : out std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0);
s_axi4_bresp : out std_logic_vector(1 downto 0);
s_axi4_bvalid : out std_logic;
s_axi4_bready : in std_logic;
-----------------------------------
-- axi read address Channel Signals
-----------------------------------
s_axi4_arid : in std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0);
s_axi4_araddr : in std_logic_vector((C_SPI_MEM_ADDR_BITS-1) downto 0);--((C_S_AXI4_ADDR_WIDTH-1) downto 0);
s_axi4_arlen : in std_logic_vector(7 downto 0);
s_axi4_arsize : in std_logic_vector(2 downto 0);
s_axi4_arburst : in std_logic_vector(1 downto 0);
s_axi4_arlock : in std_logic; -- not supported in design
s_axi4_arcache : in std_logic_vector(3 downto 0);-- not supported in design
s_axi4_arprot : in std_logic_vector(2 downto 0);-- not supported in design
s_axi4_arvalid : in std_logic;
s_axi4_arready : out std_logic;
--------------------------------
-- axi read data Channel Signals
--------------------------------
s_axi4_rid : out std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0);
s_axi4_rdata : out std_logic_vector(31 downto 0);--((C_S_AXI4_DATA_WIDTH-1) downto 0);
s_axi4_rresp : out std_logic_vector(1 downto 0);
s_axi4_rlast : out std_logic;
s_axi4_rvalid : out std_logic;
s_axi4_rready : in std_logic;
--------------------------------
-------------------------------
--*SPI port interface * --
-------------------------------
io0_i : in std_logic; -- MOSI signal in standard SPI
io0_o : out std_logic;
io0_t : out std_logic;
-------------------------------
io1_i : in std_logic; -- MISO signal in standard SPI
io1_o : out std_logic;
io1_t : out std_logic;
-----------------
-- quad mode pins
-----------------
io2_i : in std_logic;
io2_o : out std_logic;
io2_t : out std_logic;
---------------
io3_i : in std_logic;
io3_o : out std_logic;
io3_t : out std_logic;
---------------------------------
-- common pins
----------------
spisel : in std_logic;
-----
sck_i : in std_logic;
sck_o : out std_logic;
sck_t : out std_logic;
-----
ss_i : in std_logic_vector((C_NUM_SS_BITS-1) downto C_LSB_STUP);
ss_o : out std_logic_vector((C_NUM_SS_BITS-1) downto C_LSB_STUP);
ss_t : out std_logic;
------------------------
-- STARTUP INTERFACE
------------------------
cfgclk : out std_logic; -- FGCLK , -- 1-bit output: Configuration main clock output
cfgmclk : out std_logic; -- FGMCLK , -- 1-bit output: Configuration internal oscillator clock output
eos : out std_logic; -- OS , -- 1-bit output: Active high output signal indicating the End Of Startup.
preq : out std_logic; -- REQ , -- 1-bit output: PROGRAM request to fabric output
clk : in std_logic; -- input
gsr : in std_logic; -- input
gts : in std_logic; -- input
keyclearb : in std_logic; -- input
usrcclkts : in std_logic; -- input
usrdoneo : in std_logic; -- input
usrdonets : in std_logic; -- input
pack : in std_logic; -- input
----------------------
-- INTERRUPT INTERFACE
----------------------
ip2intc_irpt : out std_logic
---------------------------------
);
-------------------------------
-- Fan-out attributes for XST
attribute MAX_FANOUT : string;
attribute MAX_FANOUT of S_AXI_ACLK : signal is "10000";
attribute MAX_FANOUT of S_AXI4_ACLK : signal is "10000";
attribute MAX_FANOUT of EXT_SPI_CLK : signal is "10000";
attribute MAX_FANOUT of S_AXI_ARESETN : signal is "10000";
attribute MAX_FANOUT of S_AXI4_ARESETN : signal is "10000";
attribute INITIALVAL : string;
attribute INITIALVAL of SPISEL : signal is "VCC";
-------------------------------
end entity axi_quad_spi;
--------------------------------------------------------------------------------
architecture imp of axi_quad_spi is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
---------------------------------------------------------------------------------
---- constant added for webtalk information
---------------------------------------------------------------------------------
-- constant C_CORE_GENERATION_INFO : string := C_INSTANCE & ",axi_quad_spi,{"
-- & "C_FAMILY = " & C_FAMILY
-- & ",C_SUB_FAMILY = " & C_SUB_FAMILY
-- & ",C_INSTANCE = " & C_INSTANCE
-- & ",C_S_AXI_ADDR_WIDTH = " & integer'image(C_S_AXI_ADDR_WIDTH)
-- & ",C_S_AXI_DATA_WIDTH = " & integer'image(C_S_AXI_DATA_WIDTH)
-- & ",C_S_AXI4_ADDR_WIDTH = " & integer'image(C_S_AXI4_ADDR_WIDTH)
-- & ",C_S_AXI4_DATA_WIDTH = " & integer'image(C_S_AXI4_DATA_WIDTH)
-- & ",C_S_AXI4_ID_WIDTH = " & integer'image(C_S_AXI4_ID_WIDTH)
-- & ",C_FIFO_DEPTH = " & integer'image(C_FIFO_DEPTH)
-- & ",C_SCK_RATIO = " & integer'image(C_SCK_RATIO)
-- & ",C_NUM_SS_BITS = " & integer'image(C_NUM_SS_BITS)
-- & ",C_NUM_TRANSFER_BITS = " & integer'image(C_NUM_TRANSFER_BITS)
-- & ",C_USE_STARTUP = " & integer'image(C_USE_STARTUP)
-- & ",C_SPI_MODE = " & integer'image(C_SPI_MODE)
-- & ",C_SPI_MEMORY = " & integer'image(C_SPI_MEMORY)
-- & ",C_TYPE_OF_AXI4_INTERFACE = " & integer'image(C_TYPE_OF_AXI4_INTERFACE)
-- & ",C_XIP_MODE = " & integer'image(C_XIP_MODE)
-- & "}";
--
-- attribute CORE_GENERATION_INFO : string;
-- attribute CORE_GENERATION_INFO of imp : architecture is C_CORE_GENERATION_INFO;
-------------------------------------------------------------
-------------------------------------------------------------
-- Function Declaration
-------------------------------------------------------------
-- get_fifo_presence - This function returns the 0 or 1 based upon the FIFO Depth.
--
function get_fifo_presence(C_FIFO_DEPTH: integer) return integer is
-----
begin
-----
if(C_FIFO_DEPTH = 0)then
return 0;
else
return 1;
end if;
end function get_fifo_presence;
function get_fifo_depth(C_FIFO_EXIST: integer; C_FIFO_DEPTH : integer) return integer is
-----
begin
-----
if(C_FIFO_EXIST = 1)then
return C_FIFO_DEPTH;
else
return 64; -- to ensure that log2 functions does not become invalid
end if;
end function get_fifo_depth;
------------------------------
function get_fifo_occupancy_count(C_FIFO_DEPTH: integer) return integer is
-----
variable j : integer := 0;
variable k : integer := 0;
-----
begin
-----
if (C_FIFO_DEPTH = 0) then
return 4;
else
for i in 0 to 11 loop
if(2**i >= C_FIFO_DEPTH) then
if(k = 0) then
j := i;
end if;
k := 1;
end if;
end loop;
return j;
end if;
-------
end function get_fifo_occupancy_count;
------------------------------
-- Constant declarations
------------------------------
--------------------- ******************* ------------------------------------
-- Core Parameters
--------------------- ******************* ------------------------------------
--
constant C_FIFO_EXIST : integer := get_fifo_presence(C_FIFO_DEPTH);
constant C_FIFO_DEPTH_UPDATED : integer := get_fifo_depth(C_FIFO_EXIST, C_FIFO_DEPTH);
-- width of control register
constant C_SPICR_REG_WIDTH : integer := 10;-- refer DS
-- width of status register
constant C_SPISR_REG_WIDTH : integer := 11;-- refer DS
-- count the counter width for calculating FIFO occupancy
constant C_OCCUPANCY_NUM_BITS : integer := get_fifo_occupancy_count(C_FIFO_DEPTH_UPDATED);
-- width of spi shift register
constant C_SPI_NUM_BITS_REG : integer := 8;-- this is fixed
constant C_NUM_SPI_REGS : integer := 8;-- this is fixed
constant C_IPISR_IPIER_BITS : integer := 14;-- total 14 interrupts - 0 to 13
--------------------- ******************* ------------------------------------
-- AXI lite parameters
--------------------- ******************* ------------------------------------
constant C_S_AXI_SPI_MIN_SIZE : std_logic_vector(31 downto 0):= X"0000007c";
constant C_USE_WSTRB : integer := 1;
constant C_DPHASE_TIMEOUT : integer := 20;
-- interupt mode
constant IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE(0 to (C_IPISR_IPIER_BITS-1)):=
(
others => INTR_REG_EVENT
-- when C_SPI_MODE = 0
-- Seven interrupts if C_FIFO_DEPTH_UPDATED = 0
-- OR
-- Eight interrupts if C_FIFO_DEPTH_UPDATED = 0 and slave mode
----------------------- OR ---------------------------
-- Nine interrupts if C_FIFO_DEPTH_UPDATED = 16 and slave mode
-- OR
-- Seven interrupts if C_FIFO_DEPTH_UPDATED = 16 and master mode
-- when C_SPI_MODE = 1 or 2
-- Thirteen interrupts if C_FIFO_DEPTH_UPDATED = 16 and master mode
);
constant ZEROES : std_logic_vector(31 downto 0):= X"00000000";
-- this constant is defined as the start of SPI register addresses.
constant C_IP_REG_ADDR_OFFSET : std_logic_vector := X"00000060";
-- Address range array
constant C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE :=
(
-- interrupt address base & high range
--ZEROES & C_BASEADDR,
--ZEROES & (C_BASEADDR or X"0000003F"),--interrupt address higher range
ZEROES & X"00000000",
ZEROES & X"0000003F",--interrupt address higher range
-- soft reset register base & high addr
--ZEROES & (C_BASEADDR or X"00000040"),
--ZEROES & (C_BASEADDR or X"00000043"),--soft reset register high addr
ZEROES & X"00000040",
-- ZEROES & X"00000043",--soft reset register high addr
ZEROES & X"0000005C",--soft reset register NEW high addr for addressing holes
-- SPI registers Base & High Address
-- Range is 60 to 78 -- for internal registers
--ZEROES & (C_BASEADDR or C_IP_REG_ADDR_OFFSET),
--ZEROES & (C_BASEADDR or C_IP_REG_ADDR_OFFSET or X"00000018")
ZEROES & C_IP_REG_ADDR_OFFSET,
ZEROES & (C_IP_REG_ADDR_OFFSET or X"00000018")
);
-- AXI4 Address range array
constant C_ARD_ADDR_RANGE_ARRAY_AXI4_FULL: SLV64_ARRAY_TYPE :=
(
-- interrupt address base & high range
--*ZEROES & C_S_AXI4_BASEADDR,
--*ZEROES & (C_S_AXI4_BASEADDR or X"0000003F"),--interrupt address higher range
ZEROES & X"00000000",
ZEROES & X"0000003F",--soft reset register high addr
-- soft reset register base & high addr
--*ZEROES & (C_S_AXI4_BASEADDR or X"00000040"),
--*ZEROES & (C_S_AXI4_BASEADDR or X"00000043"),--soft reset register high addr
ZEROES & X"00000040",
-- ZEROES & X"00000043",--soft reset register high addr
ZEROES & X"0000005C",--soft reset register NEW high addr for addressing holes
-- SPI registers Base & High Address
-- Range is 60 to 78 -- for internal registers
ZEROES & (C_IP_REG_ADDR_OFFSET),
ZEROES & (C_IP_REG_ADDR_OFFSET or X"00000018")
);
-- No. of CE's required per address range
constant C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 16 , -- 16 CEs required for interrupt
--1 => 1, -- 1 CE required for soft reset
1 => 8, -- 8 CE required for Addressing Holes in soft reset
2 => C_NUM_SPI_REGS
);
-- no. of Chip Enable Signals
constant C_NUM_CE_SIGNALS : integer := calc_num_ce(C_ARD_NUM_CE_ARRAY);
-- no. of Chip Select Signals
constant C_NUM_CS_SIGNALS : integer := (C_ARD_ADDR_RANGE_ARRAY'LENGTH/2);
-----------------------------
----------------------- ******************* ------------------------------------
---- XIP Mode parameters
----------------------- ******************* ------------------------------------
-- No. of XIP SPI registers
constant C_NUM_XIP_SPI_REGS : integer := 2;-- this is fixed
-- width of XIP control register
constant C_XIP_SPICR_REG_WIDTH: integer := 2;-- refer DS
-- width of XIP status register
constant C_XIP_SPISR_REG_WIDTH: integer := 5;-- refer DS
-- Address range array
constant C_XIP_LITE_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE :=
(
-- XIP SPI registers Base & High Address
-- Range is 60 to 64 -- for internal registers
--*ZEROES & (C_BASEADDR or C_IP_REG_ADDR_OFFSET),
--*ZEROES & (C_BASEADDR or C_IP_REG_ADDR_OFFSET or X"00000004")
ZEROES & (C_IP_REG_ADDR_OFFSET),
ZEROES & (C_IP_REG_ADDR_OFFSET or X"00000004")
);
-- No. of CE's required per address range
constant C_XIP_LITE_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => C_NUM_XIP_SPI_REGS -- 2 CEs required for XIP lite interface
);
-- no. of Chip Enable Signals
constant C_NUM_XIP_CE_SIGNALS : integer :=
calc_num_ce(C_XIP_LITE_ARD_NUM_CE_ARRAY);
function assign_addr_bits (addr_bits_info : integer) return string is
variable addr_width_24 : integer:= 24;
variable addr_width_32 : integer:= 32;
begin
if addr_bits_info = 24 then -- old logic for 24 bit addressing
return X"00FFFFFF";--addr_width_24;
else
return X"FFFFFFFF";--addr_width_32;
end if;
end function assign_addr_bits;
constant C_XIP_ADDR_OFFSET : std_logic_vector := X"FFFFFFFF";--assign_addr_bits(C_SPI_MEM_ADDR_BITS); -- X"00FFFFFF";
-- XIP Full Interface Address range array
constant C_XIP_FULL_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE :=
(
-- XIP SPI registers Base & High Address
-- Range is 60 to 64 -- for internal registers
--*ZEROES & (C_S_AXI4_BASEADDR),
--*ZEROES & (C_S_AXI4_BASEADDR or C_24_BIT_ADDR_OFFSET)
ZEROES & X"00000000",
ZEROES & C_XIP_ADDR_OFFSET
);
-- No. of CE's required per address range
constant C_XIP_FULL_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => C_NUM_XIP_SPI_REGS -- 0 CEs required for XIP Full interface
);
---------------------------------------------------------------------------------
constant C_XIP_FIFO_DEPTH : integer := 264;
-------------------------------------------------------------------------------
----Startup Signals
signal di_int : std_logic_vector(3 downto 0); -- output
signal di_int_sync : std_logic_vector(3 downto 0); -- output
signal dts_int : std_logic_vector(3 downto 0); -- input
signal do_int : std_logic_vector(3 downto 0); -- input
-- signal declaration
signal bus2ip_clk : std_logic;
signal bus2ip_be_int : std_logic_vector
(((C_S_AXI_DATA_WIDTH/8)-1)downto 0);
signal bus2ip_rdce_int : std_logic_vector
((C_NUM_CE_SIGNALS-1)downto 0);
signal bus2ip_wrce_int : std_logic_vector
((C_NUM_CE_SIGNALS-1)downto 0);
signal bus2ip_data_int : std_logic_vector
((C_S_AXI_DATA_WIDTH-1)downto 0);
signal ip2bus_data_int : std_logic_vector
((C_S_AXI_DATA_WIDTH-1)downto 0 )
:= (others => '0');
signal ip2bus_wrack_int : std_logic := '0';
signal ip2bus_rdack_int : std_logic := '0';
signal ip2bus_error_int : std_logic := '0';
signal bus2ip_reset_int : std_logic;
signal bus2ip_reset_ipif_inverted: std_logic;
-- XIP signals
signal bus2ip_xip_rdce_int: std_logic_vector(0 to C_NUM_XIP_CE_SIGNALS-1);
signal bus2ip_xip_wrce_int: std_logic_vector(0 to C_NUM_XIP_CE_SIGNALS-1);
signal io0_i_sync : std_logic;
signal io1_i_sync : std_logic;
signal io2_i_sync : std_logic;
signal io3_i_sync : std_logic;
signal io0_i_sync_int : std_logic;
signal io1_i_sync_int : std_logic;
signal io2_i_sync_int : std_logic;
signal io3_i_sync_int : std_logic;
signal io0_i_int : std_logic;
signal io1_i_int : std_logic;
signal io2_i_int : std_logic;
signal io3_i_int : std_logic;
signal io0_o_int : std_logic;
signal io1_o_int : std_logic;
signal io2_o_int : std_logic;
signal io3_o_int : std_logic;
signal io0_t_int : std_logic;
signal io1_t_int : std_logic;
signal io2_t_int : std_logic;
signal io3_t_int : std_logic;
signal burst_tr_int : std_logic;
signal rready_int : std_logic;
signal bus2ip_reset_ipif4_inverted : std_logic;
signal fcsbo_int : std_logic;
signal ss_o_int : std_logic_vector((C_NUM_SS_BITS-1) downto 0);
signal ss_t_int : std_logic;
signal ss_i_int : std_logic_vector((C_NUM_SS_BITS-1) downto 0);
signal fcsbts_int : std_logic;
signal startup_di : std_logic_vector(1 downto 0); -- output
signal startup_do : std_logic_vector(1 downto 0) := (others => '1'); -- output
signal startup_dts : std_logic_vector(1 downto 0) := (others => '0'); -- output
-----
begin
-----
--------STUP and XIP mode
STARTUP_USED_1: if (C_USE_STARTUP = 1 and C_UC_FAMILY = 1) generate
begin
DI_INT_IO3_I_REG: component FD
generic map
(
INIT => '0'
)
port map
(
Q => di_int_sync(3),
C => EXT_SPI_CLK,
D => di_int(3) --MOSI_I
);
DI_INT_IO2_I_REG: component FD
generic map
(
INIT => '0'
)
port map
(
Q => di_int_sync(2),
C => EXT_SPI_CLK,
D => di_int(2) -- MISO_I
);
DI_INT_IO1_I_REG: component FD
generic map
(
INIT => '0'
)
port map
(
Q => di_int_sync(1),
C => EXT_SPI_CLK,
D => di_int(1)
);
-----------------------
DI_INT_IO0_I_REG: component FD
generic map
(
INIT => '0'
)
port map
(
Q => di_int_sync(0),
C => EXT_SPI_CLK,
D => di_int(0)
);
io0_i_sync_int <= di_int_sync(0);
io1_i_sync_int <= di_int_sync(1);
io2_i_sync_int <= di_int_sync(2);
io3_i_sync_int <= di_int_sync(3);
end generate STARTUP_USED_1;
DATA_STARTUP_EN : if (C_USE_STARTUP = 1 and C_UC_FAMILY = 1 and C_XIP_MODE = 1)
generate
-----
begin
-----
do_int(0) <= io0_o_int;
dts_int(0) <= io0_t_int ;
do_int(1) <= io1_o_int;
dts_int(1) <= io1_t_int ;
fcsbo_int <= ss_o_int(0);
fcsbts_int <= ss_t_int;
NUM_SS : if (C_NUM_SS_BITS = 1) generate
begin
ss_o <= (others => '0');
ss_t <= '0';
end generate NUM_SS;
NUM_SS_G1 : if (C_NUM_SS_BITS > 1) generate
begin
ss_i_int <= ss_i((C_NUM_SS_BITS-1) downto 1) & '1';
ss_o <= ss_o_int((C_NUM_SS_BITS-1) downto 1);-- & '0';
ss_t <= ss_t_int;
end generate NUM_SS_G1;
DATA_OUT_NQUAD: if C_SPI_MODE = 0 or C_SPI_MODE = 1 generate
begin
startup_di <= di_int_sync(3) & di_int_sync(2);
do_int(2) <= startup_do(0);
do_int(3) <= startup_do(1);
dts_int(2) <= startup_dts(0);
dts_int(3) <= startup_dts(1);
--do <= do_int(3) & do_int(1);
--dts <= dts_int(3) & dts_int(1);
end generate DATA_OUT_NQUAD;
DATA_OUT_QUAD: if C_SPI_MODE = 2 generate
begin
--di <= "00";--di_int(3) & di_int(2);
do_int(2) <= io2_o_int;--do(2);
do_int(3) <= io3_o_int;--do(1);
--do <= do_int(3) & do_int(1);
dts_int(2) <= io2_t_int;--dts_int(3) & dts_int(1);
dts_int(3) <= io3_t_int;--dts_int(3) & dts_int(1);
end generate DATA_OUT_QUAD;
end generate DATA_STARTUP_EN;
DATA_STARTUP_DIS : if ((C_USE_STARTUP = 0 or (C_USE_STARTUP = 1 and C_UC_FAMILY = 0)) and C_XIP_MODE = 1)
generate
-----
begin
-----
io0_o <= io0_o_int;
io0_t <= io0_t_int;
io1_t <= io1_t_int;
io1_o <= io1_o_int;
io2_o <= io2_o_int;
io2_t <= io2_t_int;
io3_t <= io3_t_int;
io3_o <= io3_o_int;
ss_i_int <= ss_i;
ss_o <= ss_o_int;-- & '0';
ss_t <= ss_t_int;
end generate DATA_STARTUP_DIS;
--------STUP and XIP mode off
STARTUP_USED: if (C_USE_STARTUP = 0 or C_UC_FAMILY = 0) generate
begin
io0_i_sync_int <= io0_i_sync;
io1_i_sync_int <= io1_i_sync;
io2_i_sync_int <= io2_i_sync;
io3_i_sync_int <= io3_i_sync;
end generate STARTUP_USED;
IO0_I_REG: component FD
generic map
(
INIT => '0'
)
port map
(
Q => io0_i_sync,
C => ext_spi_clk,
D => io0_i --MOSI_I
);
IO1_I_REG: component FD
generic map
(
INIT => '0'
)
port map
(
Q => io1_i_sync,
C => ext_spi_clk,
D => io1_i -- MISO_I
);
IO2_I_REG: component FD
generic map
(
INIT => '0'
)
port map
(
Q => io2_i_sync,
C => ext_spi_clk,
D => io2_i
);
-----------------------
IO3_I_REG: component FD
generic map
(
INIT => '0'
)
port map
(
Q => io3_i_sync,
C => ext_spi_clk,
D => io3_i
);
-----------------------
-------------------------------------------------------------------------------
---------------
-- AXI_QUAD_SPI_LEGACY_MODE: This logic is legacy AXI4 Lite interface based design
---------------
QSPI_LEGACY_MD_GEN : if C_TYPE_OF_AXI4_INTERFACE = 0 generate
---------------
begin
-----
AXI_LITE_IPIF_I : entity axi_lite_ipif_v3_0_4.axi_lite_ipif
generic map
(
----------------------------------------------------
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH ,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH ,
----------------------------------------------------
C_S_AXI_MIN_SIZE => C_S_AXI_SPI_MIN_SIZE ,
C_USE_WSTRB => C_USE_WSTRB ,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT ,
----------------------------------------------------
C_ARD_ADDR_RANGE_ARRAY => C_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY ,
C_FAMILY => C_FAMILY
----------------------------------------------------
)
port map
(
---------------------------------------------------------
S_AXI_ACLK => s_axi_aclk, -- in
S_AXI_ARESETN => s_axi_aresetn, -- in
---------------------------------------------------------
S_AXI_AWADDR => s_axi_awaddr, -- in
S_AXI_AWVALID => s_axi_awvalid, -- in
S_AXI_AWREADY => s_axi_awready, -- out
S_AXI_WDATA => s_axi_wdata, -- in
S_AXI_WSTRB => s_axi_wstrb, -- in
S_AXI_WVALID => s_axi_wvalid, -- in
S_AXI_WREADY => s_axi_wready, -- out
S_AXI_BRESP => s_axi_bresp, -- out
S_AXI_BVALID => s_axi_bvalid, -- out
S_AXI_BREADY => s_axi_bready, -- in
S_AXI_ARADDR => s_axi_araddr, -- in
S_AXI_ARVALID => s_axi_arvalid, -- in
S_AXI_ARREADY => s_axi_arready, -- out
S_AXI_RDATA => s_axi_rdata, -- out
S_AXI_RRESP => s_axi_rresp, -- out
S_AXI_RVALID => s_axi_rvalid, -- out
S_AXI_RREADY => s_axi_rready, -- in
----------------------------------------------------------
-- IP Interconnect (IPIC) port signals
Bus2IP_Clk => bus2ip_clk, -- out
Bus2IP_Resetn => bus2ip_reset_int, -- out
----------------------------------------------------------
Bus2IP_Addr => open, -- out -- not used signal
Bus2IP_RNW => open, -- out
Bus2IP_BE => bus2ip_be_int, -- out
Bus2IP_CS => open, -- out -- not used signal
Bus2IP_RdCE => bus2ip_rdce_int, -- out -- little endian
Bus2IP_WrCE => bus2ip_wrce_int, -- out -- little endian
Bus2IP_Data => bus2ip_data_int, -- out -- little endian
----------------------------------------------------------
IP2Bus_Data => ip2bus_data_int, -- in -- little endian
IP2Bus_WrAck => ip2bus_wrack_int, -- in
IP2Bus_RdAck => ip2bus_rdack_int, -- in
IP2Bus_Error => ip2bus_error_int -- in
----------------------------------------------------------
);
----------------------
--REG_RST_FRM_IPIF: convert active low to active hig reset to rest of
-- the core.
----------------------
REG_RST_FRM_IPIF: process (S_AXI_ACLK) is
begin
if(S_AXI_ACLK'event and S_AXI_ACLK = '1') then
bus2ip_reset_ipif_inverted <= not(bus2ip_reset_int);
end if;
end process REG_RST_FRM_IPIF;
-- ----------------------------------------------------------------------
-- -- Instansiating the SPI core
-- ----------------------------------------------------------------------
QSPI_CORE_INTERFACE_I : entity axi_quad_spi_v3_2_8.qspi_core_interface
generic map
(
------------------------------------------------
-- AXI parameters
C_LSB_STUP => C_LSB_STUP,
C_FAMILY => C_FAMILY ,
Async_Clk => Async_Clk ,
C_SUB_FAMILY => C_FAMILY ,
C_UC_FAMILY => C_UC_FAMILY ,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
------------------------------------------------
-- local constants
C_NUM_CE_SIGNALS => C_NUM_CE_SIGNALS ,
------------------------------------------------
-- SPI parameters
--C_AXI4_CLK_PS => C_AXI4_CLK_PS ,
--C_EXT_SPI_CLK_PS => C_EXT_SPI_CLK_PS ,
C_FIFO_DEPTH => C_FIFO_DEPTH_UPDATED ,
C_SCK_RATIO => C_SCK_RATIO ,
C_NUM_SS_BITS => C_NUM_SS_BITS ,
C_NUM_TRANSFER_BITS => C_NUM_TRANSFER_BITS,
C_SPI_MODE => C_SPI_MODE ,
C_USE_STARTUP => C_USE_STARTUP ,
C_SPI_MEMORY => C_SPI_MEMORY ,
C_SELECT_XPM => C_SELECT_XPM ,
C_TYPE_OF_AXI4_INTERFACE => C_TYPE_OF_AXI4_INTERFACE,
------------------------------------------------
-- local constants
C_FIFO_EXIST => C_FIFO_EXIST ,
C_SPI_NUM_BITS_REG => C_SPI_NUM_BITS_REG,
C_OCCUPANCY_NUM_BITS => C_OCCUPANCY_NUM_BITS,
C_SHARED_STARTUP => C_SHARED_STARTUP,
------------------------------------------------
-- local constants
C_IP_INTR_MODE_ARRAY => IP_INTR_MODE_ARRAY,
------------------------------------------------
-- local constants
C_SPICR_REG_WIDTH => C_SPICR_REG_WIDTH ,
C_SPISR_REG_WIDTH => C_SPISR_REG_WIDTH
)
port map
(
EXT_SPI_CLK => ext_spi_clk, -- in
---------------------------------------------------
-- IP Interconnect (IPIC) port signals
Bus2IP_Clk => bus2ip_clk, -- in
Bus2IP_Reset => bus2ip_reset_ipif_inverted, -- in
---------------------------------------------------
Bus2IP_BE => bus2ip_be_int, -- in vector
-- Bus2IP_CS => bus2ip_cs_int,
Bus2IP_RdCE => bus2ip_rdce_int, -- in vector
Bus2IP_WrCE => bus2ip_wrce_int, -- in vector
Bus2IP_Data => bus2ip_data_int, -- in vector
---------------------------------------------------
IP2Bus_Data => ip2bus_data_int, -- out vector
IP2Bus_WrAck => ip2bus_wrack_int, -- out
IP2Bus_RdAck => ip2bus_rdack_int, -- out
IP2Bus_Error => ip2bus_error_int, -- out
---------------------------------------------------
burst_tr => burst_tr_int,
rready => '0',
WVALID => '0',
---------------------------------------------------
--SPI Ports
IO0_I => io0_i_sync,-- mosi
IO0_O => io0_o,
IO0_T => io0_t,
-----
IO1_I => io1_i_sync,-- miso
IO1_O => io1_o,
IO1_T => io1_t,
-----
IO2_I => io2_i_sync,
IO2_O => io2_o,
IO2_T => io2_t,
-----
IO3_I => io3_i_sync,
IO3_O => io3_o,
IO3_T => io3_t,
-----
SCK_I => sck_i,
SCK_O => sck_o,
SCK_T => sck_t,
-----
SPISEL => spisel,
-----
SS_I => ss_i,
SS_O => ss_o,
SS_T => ss_t,
-----
IP2INTC_Irpt => ip2intc_irpt,
CFGCLK => cfgclk, -- FGCLK , -- 1-bit output: Configuration main clock output
CFGMCLK => cfgmclk, -- FGMCLK , -- 1-bit output: Configuration internal oscillator clock output
EOS => eos, -- OS , -- 1-bit output: Active high output signal indicating the End Of Startup.
PREQ => preq, -- REQ , -- 1-bit output: PROGRAM request to fabric output
DI => startup_di, -- output
DO => startup_do, -- 4-bit input
DTS => startup_dts, -- 4-bit input
GSR => gsr, -- 1-bit input, SetReset
CLK => clk, -- 1-bit input, SetReset
GTS => gts, -- 1-bit input
KEYCLEARB => keyclearb, --1-bit input
USRCCLKTS => usrcclkts, -- SRCCLKTS , -- 1-bit input
USRDONEO => usrdoneo, -- SRDONEO , -- 1-bit input
USRDONETS => usrdonets, -- SRDONETS -- 1-bit input
PACK => pack
-----
);
burst_tr_int <= '0';
end generate QSPI_LEGACY_MD_GEN;
------------------------------------------------------------------------------
QSPI_ENHANCED_MD_GEN: if C_TYPE_OF_AXI4_INTERFACE = 1 and C_XIP_MODE = 0 generate
---------------
begin
-----
-- AXI_QUAD_SPI_I: core instance
QSPI_ENHANCED_MD_IPIF_I : entity axi_quad_spi_v3_2_8.axi_qspi_enhanced_mode
generic map(
-- General Parameters
C_FAMILY => C_FAMILY , -- : string := "virtex7";
C_SUB_FAMILY => C_FAMILY , -- : string := "virtex7";
-------------------------
--C_TYPE_OF_AXI4_INTERFACE => C_TYPE_OF_AXI4_INTERFACE, -- : integer range 0 to 1 := 0;--default AXI4 Lite Legacy mode
--C_XIP_MODE => C_XIP_MODE , -- : integer range 0 to 1 := 0;--default NON XIP Mode
--C_AXI4_CLK_PS => C_AXI4_CLK_PS , -- : integer := 10000;--AXI clock period
--C_EXT_SPI_CLK_PS => C_EXT_SPI_CLK_PS , -- : integer := 10000;--ext clock period
C_FIFO_DEPTH => C_FIFO_DEPTH_UPDATED , -- : integer := 16;-- allowed 0,16,256.
C_SCK_RATIO => C_SCK_RATIO , -- : integer := 16;--default in legacy mode
C_NUM_SS_BITS => C_NUM_SS_BITS , -- : integer range 1 to 32:= 1;
C_NUM_TRANSFER_BITS => C_NUM_TRANSFER_BITS , -- : integer := 8; -- allowed 8, 16, 32
-------------------------
C_SPI_MODE => C_SPI_MODE , -- : integer range 0 to 2 := 0; -- used for differentiating
C_USE_STARTUP => C_USE_STARTUP , -- : integer range 0 to 1 := 1; --
C_SPI_MEMORY => C_SPI_MEMORY , -- : integer range 0 to 2 := 1; -- 0 - mixed mode,
-------------------------
-- AXI4 Full Interface Parameters
C_S_AXI4_ADDR_WIDTH => C_S_AXI4_ADDR_WIDTH , -- : integer range 32 to 32 := 32;
C_S_AXI4_DATA_WIDTH => C_S_AXI4_DATA_WIDTH , -- : integer range 32 to 32 := 32;
C_S_AXI4_ID_WIDTH => C_S_AXI4_ID_WIDTH , -- : integer range 1 to 16 := 4;
-------------------------
--*C_AXI4_BASEADDR => C_S_AXI4_BASEADDR , -- : std_logic_vector := x"FFFFFFFF";
--*C_AXI4_HIGHADDR => C_S_AXI4_HIGHADDR , -- : std_logic_vector := x"00000000"
-------------------------
C_S_AXI_SPI_MIN_SIZE => C_S_AXI_SPI_MIN_SIZE ,
-------------------------
C_ARD_ADDR_RANGE_ARRAY => C_ARD_ADDR_RANGE_ARRAY_AXI4_FULL ,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY ,
C_SPI_MEM_ADDR_BITS => C_SPI_MEM_ADDR_BITS -- newly added
)
port map(
-- external async clock for SPI interface logic
EXT_SPI_CLK => ext_spi_clk , -- : in std_logic;
-----------------------------------
S_AXI4_ACLK => s_axi4_aclk , -- : in std_logic;
S_AXI4_ARESETN => s_axi4_aresetn , -- : in std_logic;
-------------------------------
-------------------------------
--*AXI4 Full port interface* --
-------------------------------
------------------------------------
-- AXI Write Address channel signals
------------------------------------
S_AXI4_AWID => s_axi4_awid , -- : in std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0);
S_AXI4_AWADDR => s_axi4_awaddr , -- : in std_logic_vector((C_S_AXI4_ADDR_WIDTH-1) downto 0);
S_AXI4_AWLEN => s_axi4_awlen , -- : in std_logic_vector(7 downto 0);
S_AXI4_AWSIZE => s_axi4_awsize , -- : in std_logic_vector(2 downto 0);
S_AXI4_AWBURST => s_axi4_awburst, -- : in std_logic_vector(1 downto 0);
S_AXI4_AWLOCK => s_axi4_awlock , -- : in std_logic; -- not supported in design
S_AXI4_AWCACHE => s_axi4_awcache, -- : in std_logic_vector(3 downto 0);-- not supported in design
S_AXI4_AWPROT => s_axi4_awprot , -- : in std_logic_vector(2 downto 0);-- not supported in design
S_AXI4_AWVALID => s_axi4_awvalid, -- : in std_logic;
S_AXI4_AWREADY => s_axi4_awready, -- : out std_logic;
---------------------------------------
-- AXI4 Full Write data channel signals
---------------------------------------
S_AXI4_WDATA => s_axi4_wdata , -- : in std_logic_vector((C_S_AXI4_DATA_WIDTH-1)downto 0);
S_AXI4_WSTRB => s_axi4_wstrb , -- : in std_logic_vector(((C_S_AXI4_DATA_WIDTH/8)-1) downto 0);
S_AXI4_WLAST => s_axi4_wlast , -- : in std_logic;
S_AXI4_WVALID => s_axi4_wvalid, -- : in std_logic;
S_AXI4_WREADY => s_axi4_wready, -- : out std_logic;
-------------------------------------------
-- AXI4 Full Write response channel Signals
-------------------------------------------
S_AXI4_BID => s_axi4_bid , -- : out std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0);
S_AXI4_BRESP => s_axi4_bresp , -- : out std_logic_vector(1 downto 0);
S_AXI4_BVALID => s_axi4_bvalid, -- : out std_logic;
S_AXI4_BREADY => s_axi4_bready, -- : in std_logic;
-----------------------------------
-- AXI Read Address channel signals
-----------------------------------
S_AXI4_ARID => s_axi4_arid , -- : in std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0);
S_AXI4_ARADDR => s_axi4_araddr , -- : in std_logic_vector((C_S_AXI4_ADDR_WIDTH-1) downto 0);
S_AXI4_ARLEN => s_axi4_arlen , -- : in std_logic_vector(7 downto 0);
S_AXI4_ARSIZE => s_axi4_arsize , -- : in std_logic_vector(2 downto 0);
S_AXI4_ARBURST => s_axi4_arburst, -- : in std_logic_vector(1 downto 0);
S_AXI4_ARLOCK => s_axi4_arlock , -- : in std_logic; -- not supported in design
S_AXI4_ARCACHE => s_axi4_arcache, -- : in std_logic_vector(3 downto 0);-- not supported in design
S_AXI4_ARPROT => s_axi4_arprot , -- : in std_logic_vector(2 downto 0);-- not supported in design
S_AXI4_ARVALID => s_axi4_arvalid, -- : in std_logic;
S_AXI4_ARREADY => s_axi4_arready, -- : out std_logic;
--------------------------------
-- AXI Read Data Channel signals
--------------------------------
S_AXI4_RID => s_axi4_rid , -- : out std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0);
S_AXI4_RDATA => s_axi4_rdata , -- : out std_logic_vector((C_S_AXI4_DATA_WIDTH-1) downto 0);
S_AXI4_RRESP => s_axi4_rresp , -- : out std_logic_vector(1 downto 0);
S_AXI4_RLAST => s_axi4_rlast , -- : out std_logic;
S_AXI4_RVALID => s_axi4_rvalid, -- : out std_logic;
S_AXI4_RREADY => s_axi4_rready, -- : in std_logic;
----------------------------------------------------------
-- IP Interconnect (IPIC) port signals
Bus2IP_Clk => bus2ip_clk, -- out
Bus2IP_Reset => bus2ip_reset_ipif_inverted , -- out
----------------------------------------------------------
-- Bus2IP_Addr => open, -- out -- not used signal
Bus2IP_RNW => open, -- out
Bus2IP_BE => bus2ip_be_int, -- out
Bus2IP_CS => open, -- out -- not used signal
Bus2IP_RdCE => bus2ip_rdce_int, -- out -- little endian
Bus2IP_WrCE => bus2ip_wrce_int, -- out -- little endian
Bus2IP_Data => bus2ip_data_int, -- out -- little endian
----------------------------------------------------------
IP2Bus_Data => ip2bus_data_int, -- in -- little endian
IP2Bus_WrAck => ip2bus_wrack_int, -- in
IP2Bus_RdAck => ip2bus_rdack_int, -- in
IP2Bus_Error => ip2bus_error_int, -- in
----------------------------------------------------------
burst_tr => burst_tr_int, -- in
rready => rready_int
);
-- ----------------------------------------------------------------------
-- -- Instansiating the SPI core
-- ----------------------------------------------------------------------
QSPI_CORE_INTERFACE_I : entity axi_quad_spi_v3_2_8.qspi_core_interface
generic map
(
------------------------------------------------
-- AXI parameters
C_LSB_STUP => C_LSB_STUP,
C_FAMILY => C_FAMILY ,
Async_Clk => Async_Clk ,
C_SELECT_XPM => C_SELECT_XPM ,
C_SUB_FAMILY => C_FAMILY ,
C_UC_FAMILY => C_UC_FAMILY ,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
------------------------------------------------
-- local constants
C_NUM_CE_SIGNALS => C_NUM_CE_SIGNALS ,
------------------------------------------------
-- SPI parameters
--C_AXI4_CLK_PS => C_AXI4_CLK_PS ,
--C_EXT_SPI_CLK_PS => C_EXT_SPI_CLK_PS ,
C_FIFO_DEPTH => C_FIFO_DEPTH_UPDATED ,
C_SCK_RATIO => C_SCK_RATIO ,
C_NUM_SS_BITS => C_NUM_SS_BITS ,
C_NUM_TRANSFER_BITS => C_NUM_TRANSFER_BITS,
C_SPI_MODE => C_SPI_MODE ,
C_USE_STARTUP => C_USE_STARTUP ,
C_SPI_MEMORY => C_SPI_MEMORY ,
C_TYPE_OF_AXI4_INTERFACE => C_TYPE_OF_AXI4_INTERFACE,
------------------------------------------------
-- local constants
C_FIFO_EXIST => C_FIFO_EXIST ,
C_SPI_NUM_BITS_REG => C_SPI_NUM_BITS_REG,
C_OCCUPANCY_NUM_BITS => C_OCCUPANCY_NUM_BITS,
C_SHARED_STARTUP => C_SHARED_STARTUP,
------------------------------------------------
-- local constants
C_IP_INTR_MODE_ARRAY => IP_INTR_MODE_ARRAY,
------------------------------------------------
-- local constants
C_SPICR_REG_WIDTH => C_SPICR_REG_WIDTH ,
C_SPISR_REG_WIDTH => C_SPISR_REG_WIDTH
)
port map
(
EXT_SPI_CLK => EXT_SPI_CLK, -- in
---------------------------------------------------
-- IP Interconnect (IPIC) port signals
Bus2IP_Clk => bus2ip_clk, -- in
Bus2IP_Reset => bus2ip_reset_ipif_inverted, -- in
---------------------------------------------------
Bus2IP_BE => bus2ip_be_int, -- in vector
-- Bus2IP_CS => bus2ip_cs_int,
Bus2IP_RdCE => bus2ip_rdce_int, -- in vector
Bus2IP_WrCE => bus2ip_wrce_int, -- in vector
Bus2IP_Data => bus2ip_data_int, -- in vector
---------------------------------------------------
IP2Bus_Data => ip2bus_data_int, -- out vector
IP2Bus_WrAck => ip2bus_wrack_int, -- out
IP2Bus_RdAck => ip2bus_rdack_int, -- out
IP2Bus_Error => ip2bus_error_int, -- out
---------------------------------------------------
burst_tr => burst_tr_int,
rready => rready_int,
WVALID => S_AXI4_WVALID,
--SPI Ports
IO0_I => io0_i_sync,-- mosi
IO0_O => io0_o,
IO0_T => io0_t,
-----
IO1_I => io1_i_sync,-- miso
IO1_O => io1_o,
IO1_T => io1_t,
-----
IO2_I => io2_i_sync,
IO2_O => io2_o,
IO2_T => io2_t,
-----
IO3_I => io3_i_sync,
IO3_O => io3_o,
IO3_T => io3_t,
-----
SCK_I => sck_i,
SCK_O => sck_o,
SCK_T => sck_t,
-----
SPISEL => spisel,
-----
SS_I => ss_i,
SS_O => ss_o,
SS_T => ss_t,
-----
IP2INTC_Irpt => ip2intc_irpt,
CFGCLK => cfgclk, -- FGCLK , -- 1-bit output: Configuration main clock output
CFGMCLK => cfgmclk, -- FGMCLK , -- 1-bit output: Configuration internal oscillator clock output
EOS => eos, -- OS , -- 1-bit output: Active high output signal indicating the End Of Startup.
PREQ => preq, -- REQ , -- 1-bit output: PROGRAM request to fabric output
DI => startup_di, -- output
DO => startup_do, -- 4-bit input
DTS => startup_dts, -- 4-bit input
CLK => clk, -- 1-bit input, SetReset
GSR => gsr, -- 1-bit input, SetReset
GTS => gts, -- 1-bit input
KEYCLEARB => keyclearb, --1-bit input
USRCCLKTS => usrcclkts, -- SRCCLKTS , -- 1-bit input
USRDONEO => usrdoneo, -- SRDONEO , -- 1-bit input
USRDONETS => usrdonets, -- SRDONETS -- 1-bit input
PACK => pack
-----
);
end generate QSPI_ENHANCED_MD_GEN;
--------------------------------------------------------------------------------
-----------------
-- XIP_MODE: This logic is used in XIP mode where AXI4 Lite & AXI4 Full interface
-- used in the design
---------------
XIP_MODE_GEN : if C_TYPE_OF_AXI4_INTERFACE = 1 and C_XIP_MODE = 1 generate
---------------
constant XIPCR : natural := 0; -- at address C_BASEADDR + 60 h
constant XIPSR : natural := 1;
--
signal bus2ip_reset_int : std_logic;
signal bus2ip_clk_int : std_logic;
signal bus2ip_data_int : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal ip2bus_data_int : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal ip2bus_wrack_int : std_logic;
signal ip2bus_rdack_int : std_logic;
signal ip2bus_error_int : std_logic;
signal bus2ip_reset_ipif_inverted: std_logic;
signal IP2Bus_XIPCR_WrAck : std_logic;
signal IP2Bus_XIPCR_RdAck : std_logic;
signal XIPCR_1_CPOL_int : std_logic;
signal XIPCR_0_CPHA_int : std_logic;
signal IP2Bus_XIPCR_Data_int : std_logic_vector((C_XIP_SPICR_REG_WIDTH-1) downto 0);
signal IP2Bus_XIPSR_Data_int : std_logic_vector((C_XIP_SPISR_REG_WIDTH-1) downto 0);
signal TO_XIPSR_AXI_TR_ERR_int : std_logic;
signal TO_XIPSR_mst_modf_err_int : std_logic;
signal TO_XIPSR_axi_rx_full_int : std_logic;
signal TO_XIPSR_axi_rx_empty_int : std_logic;
signal xipsr_cpha_cpol_err_int :std_logic;
signal xipsr_cmd_err_int :std_logic;
signal ip2bus_xipsr_wrack :std_logic;
signal ip2bus_xipsr_rdack :std_logic;
signal xipsr_axi_tr_err_int :std_logic;
signal xipsr_axi_tr_done_int :std_logic;
signal ip2bus_xipsr_rdack_int :std_logic;
signal ip2bus_xipsr_wrack_int :std_logic;
signal MISO_I_int :std_logic;
signal SCK_O_int :std_logic;
signal TO_XIPSR_trans_error_int :std_logic;
signal TO_XIPSR_CPHA_CPOL_ERR_int :std_logic;
signal ip2bus_wrack_core_reg_d1 :std_logic;
signal ip2bus_wrack_core_reg :std_logic;
signal ip2bus_rdack_core_reg_d1 :std_logic;
signal ip2bus_rdack_core_reg_d2 :std_logic;
signal ip2Bus_RdAck_core_reg_d3 :std_logic;
signal Rst_to_spi_int :std_logic;
begin
-----
---- AXI4 Lite interface instance and interface with the port list
AXI_LITE_IPIF_I : entity axi_lite_ipif_v3_0_4.axi_lite_ipif
generic map
(
----------------------------------------------------
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH ,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH ,
----------------------------------------------------
C_S_AXI_MIN_SIZE => C_S_AXI_SPI_MIN_SIZE ,
C_USE_WSTRB => C_USE_WSTRB ,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT ,
----------------------------------------------------
C_ARD_ADDR_RANGE_ARRAY => C_XIP_LITE_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => C_XIP_LITE_ARD_NUM_CE_ARRAY ,
C_FAMILY => C_FAMILY
----------------------------------------------------
)
port map
( -- AXI4 Lite interface
---------------------------------------------------------
S_AXI_ACLK => s_axi_aclk, -- in
S_AXI_ARESETN => s_axi_aresetn, -- in
---------------------------------------------------------
S_AXI_AWADDR => s_axi_awaddr, -- in
S_AXI_AWVALID => s_axi_awvalid, -- in
S_AXI_AWREADY => s_axi_awready, -- out
S_AXI_WDATA => s_axi_wdata, -- in
S_AXI_WSTRB => s_axi_wstrb, -- in
S_AXI_WVALID => s_axi_wvalid, -- in
S_AXI_WREADY => s_axi_wready, -- out
S_AXI_BRESP => s_axi_bresp, -- out
S_AXI_BVALID => s_axi_bvalid, -- out
S_AXI_BREADY => s_axi_bready, -- in
S_AXI_ARADDR => s_axi_araddr, -- in
S_AXI_ARVALID => s_axi_arvalid, -- in
S_AXI_ARREADY => s_axi_arready, -- out
S_AXI_RDATA => s_axi_rdata, -- out
S_AXI_RRESP => s_axi_rresp, -- out
S_AXI_RVALID => s_axi_rvalid, -- out
S_AXI_RREADY => s_axi_rready, -- in
----------------------------------------------------------
-- IP Interconnect (IPIC) port signals
Bus2IP_Clk => bus2ip_clk_int , -- out
Bus2IP_Resetn => bus2ip_reset_int, -- out
----------------------------------------------------------
Bus2IP_Addr => open, -- out -- not used signal
Bus2IP_RNW => open, -- out
Bus2IP_BE => open, -- bus2ip_be_int, -- out
Bus2IP_CS => open, -- out -- not used signal
Bus2IP_RdCE => bus2ip_xip_rdce_int, -- out -- little endian
Bus2IP_WrCE => bus2ip_xip_wrce_int, -- out -- little endian
Bus2IP_Data => bus2ip_data_int, -- out -- little endian
----------------------------------------------------------
IP2Bus_Data => ip2bus_data_int, -- in -- little endian
IP2Bus_WrAck => ip2bus_wrack_int, -- in
IP2Bus_RdAck => ip2bus_rdack_int, -- in
IP2Bus_Error => ip2bus_error_int -- in
----------------------------------------------------------
);
--------------------------------------------------------------------------
ip2bus_error_int <= '0'; -- there is no error in this mode
----------------------
--REG_RST_FRM_IPIF: convert active low to active hig reset to rest of
-- the core.
----------------------
REG_RST_FRM_IPIF: process (S_AXI_ACLK) is
begin
if(S_AXI_ACLK'event and S_AXI_ACLK = '1') then
bus2ip_reset_ipif_inverted <= not(S_AXI_ARESETN);
end if;
end process REG_RST_FRM_IPIF;
--------------------------------------------------------------------------
XIP_CR_I : entity axi_quad_spi_v3_2_8.xip_cntrl_reg
generic map
(
C_XIP_SPICR_REG_WIDTH => C_XIP_SPICR_REG_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH ,
C_SPI_MODE => C_SPI_MODE
)
port map(
Bus2IP_Clk => S_AXI_ACLK, -- : in std_logic;
Soft_Reset_op => bus2ip_reset_ipif_inverted, -- : in std_logic;
------------------------
Bus2IP_XIPCR_WrCE => bus2ip_xip_wrce_int(XIPCR), -- : in std_logic;
Bus2IP_XIPCR_RdCE => bus2ip_xip_rdce_int(XIPCR), -- : in std_logic;
Bus2IP_XIPCR_data => bus2ip_data_int , -- : in std_logic_vector(0 to (C_S_AXI_DATA_WIDTH-1));
------------------------
ip2Bus_RdAck_core => ip2Bus_RdAck_core_reg_d2, -- IP2Bus_XIPCR_WrAck,
ip2Bus_WrAck_core => ip2Bus_WrAck_core_reg, -- IP2Bus_XIPCR_RdAck,
------------------------
--XIPCR_7_0_CMD => XIPCR_7_0_CMD, -- out std_logic_vector;
XIPCR_1_CPOL => XIPCR_1_CPOL_int , -- out std_logic;
XIPCR_0_CPHA => XIPCR_0_CPHA_int , -- out std_logic;
------------------------
IP2Bus_XIPCR_Data => IP2Bus_XIPCR_Data_int, -- out std_logic;
------------------------
TO_XIPSR_CPHA_CPOL_ERR=> TO_XIPSR_CPHA_CPOL_ERR_int -- out std_logic
);
--------------------------------------------------------------------------
REG_WR_ACK_P:process(S_AXI_ACLK)is
begin
-----
if(S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if(bus2ip_reset_ipif_inverted = '1')then
ip2Bus_WrAck_core_reg_d1 <= '0';
ip2Bus_WrAck_core_reg <= '0';
else
ip2Bus_WrAck_core_reg_d1 <= bus2ip_xip_wrce_int(XIPCR) or
bus2ip_xip_wrce_int(XIPSR);
ip2Bus_WrAck_core_reg <= (bus2ip_xip_wrce_int(XIPCR) or
bus2ip_xip_wrce_int(XIPSR)) and
(not ip2Bus_WrAck_core_reg_d1);
end if;
end if;
end process REG_WR_ACK_P;
-------------------------
ip2bus_wrack_int <= ip2Bus_WrAck_core_reg;
-------------------------
REG_RD_ACK_P:process(S_AXI_ACLK)is
begin
-----
if(S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if(bus2ip_reset_ipif_inverted = '1')then
ip2Bus_RdAck_core_reg_d1 <= '0';
ip2Bus_RdAck_core_reg_d2 <= '0';
ip2Bus_RdAck_core_reg_d3 <= '0';
else
ip2Bus_RdAck_core_reg_d1 <= bus2ip_xip_rdce_int(XIPCR) or
bus2ip_xip_rdce_int(XIPSR);
ip2Bus_RdAck_core_reg_d2 <= (bus2ip_xip_rdce_int(XIPCR) or
bus2ip_xip_rdce_int(XIPSR)) and
(not ip2Bus_RdAck_core_reg_d1);
ip2Bus_RdAck_core_reg_d3 <= ip2Bus_RdAck_core_reg_d2;
end if;
end if;
end process REG_RD_ACK_P;
-------------------------
ip2bus_rdack_int <= ip2Bus_RdAck_core_reg_d3;
-------------------------
REG_IP2BUS_DATA_P:process(S_AXI_ACLK)is
begin
-----
if(S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if(bus2ip_reset_ipif_inverted = '1')then
ip2bus_data_int <= (others => '0');
elsif(ip2Bus_RdAck_core_reg_d2 = '1') then
ip2bus_data_int <= ("000000000000000000000000000000" & IP2Bus_XIPCR_Data_int) or
("000000000000000000000000000" & IP2Bus_XIPSR_Data_int);
end if;
end if;
end process REG_IP2BUS_DATA_P;
-------------------------
--------------------------------------------------------------------------
XIP_SR_I : entity axi_quad_spi_v3_2_8.xip_status_reg
generic map
(
C_XIP_SPISR_REG_WIDTH => C_XIP_SPISR_REG_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH
)
port map(
Bus2IP_Clk => S_AXI_ACLK, -- : in std_logic;
Soft_Reset_op => bus2ip_reset_ipif_inverted, -- : in std_logic;
------------------------
XIPSR_AXI_TR_ERR => TO_XIPSR_AXI_TR_ERR_int, -- : in std_logic;
XIPSR_CPHA_CPOL_ERR => TO_XIPSR_CPHA_CPOL_ERR_int, -- : in std_logic;
XIPSR_MST_MODF_ERR => TO_XIPSR_mst_modf_err_int, -- : in std_logic;
XIPSR_AXI_RX_FULL => TO_XIPSR_axi_rx_full_int, -- : in std_logic;
XIPSR_AXI_RX_EMPTY => TO_XIPSR_axi_rx_empty_int, -- : in std_logic;
------------------------
Bus2IP_XIPSR_WrCE => bus2ip_xip_wrce_int(XIPSR),
Bus2IP_XIPSR_RdCE => bus2ip_xip_rdce_int(XIPSR),
-------------------
IP2Bus_XIPSR_Data => IP2Bus_XIPSR_Data_int ,
ip2Bus_RdAck => ip2Bus_RdAck_core_reg_d3
);
---------------------------------------------------------------------------
--REG_RST4_FRM_IPIF: convert active low to active hig reset to rest of
-- the core.
----------------------
REG_RST4_FRM_IPIF: process (S_AXI4_ACLK) is
begin
if(S_AXI4_ACLK'event and S_AXI4_ACLK = '1') then
bus2ip_reset_ipif4_inverted <= not(S_AXI4_ARESETN);
end if;
end process REG_RST4_FRM_IPIF;
-------------------------------------------------------------------------
RESET_SYNC_AXI_SPI_CLK_INST:entity axi_quad_spi_v3_2_8.reset_sync_module
port map(
EXT_SPI_CLK => EXT_SPI_CLK ,-- in std_logic;
Soft_Reset_frm_axi => bus2ip_reset_ipif4_inverted ,-- in std_logic;
Rst_to_spi => Rst_to_spi_int -- out std_logic;
);
--------------------------------------------------------------------------
AXI_QSPI_XIP_I : entity axi_quad_spi_v3_2_8.axi_qspi_xip_if
generic map
(
C_FAMILY => C_FAMILY ,
Async_Clk => Async_Clk ,
C_SUB_FAMILY => C_FAMILY ,
-------------------------
--C_TYPE_OF_AXI4_INTERFACE => C_TYPE_OF_AXI4_INTERFACE,
--C_XIP_MODE => C_XIP_MODE ,
--C_AXI4_CLK_PS => C_AXI4_CLK_PS ,
--C_EXT_SPI_CLK_PS => C_EXT_SPI_CLK_PS ,
--C_FIFO_DEPTH => C_FIFO_DEPTH_UPDATED ,
C_SPI_MEM_ADDR_BITS => C_SPI_MEM_ADDR_BITS ,
C_SCK_RATIO => C_SCK_RATIO ,
C_NUM_SS_BITS => C_NUM_SS_BITS ,
C_NUM_TRANSFER_BITS => C_NUM_TRANSFER_BITS ,
-------------------------
C_SPI_MODE => C_SPI_MODE ,
C_USE_STARTUP => C_USE_STARTUP ,
C_SPI_MEMORY => C_SPI_MEMORY ,
-------------------------
-- AXI4 Full Interface Parameters
C_S_AXI4_ADDR_WIDTH => C_S_AXI4_ADDR_WIDTH ,
C_S_AXI4_DATA_WIDTH => C_S_AXI4_DATA_WIDTH ,
C_S_AXI4_ID_WIDTH => C_S_AXI4_ID_WIDTH ,
-------------------------
--*C_AXI4_BASEADDR => C_S_AXI4_BASEADDR ,
--*C_AXI4_HIGHADDR => C_S_AXI4_HIGHADDR ,
-------------------------
--C_XIP_SPICR_REG_WIDTH => C_XIP_SPICR_REG_WIDTH ,
--C_XIP_SPISR_REG_WIDTH => C_XIP_SPISR_REG_WIDTH ,
-------------------------
C_XIP_FULL_ARD_ADDR_RANGE_ARRAY => C_XIP_FULL_ARD_ADDR_RANGE_ARRAY,
C_XIP_FULL_ARD_NUM_CE_ARRAY => C_XIP_FULL_ARD_NUM_CE_ARRAY
)
port map
(
-- external async clock for SPI interface logic
EXT_SPI_CLK => ext_spi_clk , -- : in std_logic;
Rst_to_spi => Rst_to_spi_int,
----------------------------------
S_AXI_ACLK => s_axi_aclk , -- : in std_logic;
S_AXI_ARESETN => bus2ip_reset_ipif_inverted, -- : in std_logic;
----------------------------------
S_AXI4_ACLK => s_axi4_aclk , -- : in std_logic;
S_AXI4_ARESET => bus2ip_reset_ipif4_inverted, -- : in std_logic;
-------------------------------
--*AXI4 Full port interface* --
-------------------------------
------------------------------------
-- AXI Write Address Channel Signals
------------------------------------
S_AXI4_AWID => s_axi4_awid , -- : in std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0);
S_AXI4_AWADDR => s_axi4_awaddr , -- : in std_logic_vector((C_S_AXI4_ADDR_WIDTH-1) downto 0);
S_AXI4_AWLEN => s_axi4_awlen , -- : in std_logic_vector(7 downto 0);
S_AXI4_AWSIZE => s_axi4_awsize , -- : in std_logic_vector(2 downto 0);
S_AXI4_AWBURST => s_axi4_awburst, -- : in std_logic_vector(1 downto 0);
S_AXI4_AWLOCK => s_axi4_awlock , -- : in std_logic; -- not supported in design
S_AXI4_AWCACHE => s_axi4_awcache, -- : in std_logic_vector(3 downto 0);-- not supported in design
S_AXI4_AWPROT => s_axi4_awprot , -- : in std_logic_vector(2 downto 0);-- not supported in design
S_AXI4_AWVALID => s_axi4_awvalid, -- : in std_logic;
S_AXI4_AWREADY => s_axi4_awready, -- : out std_logic;
---------------------------------------
-- AXI4 Full Write data channel Signals
---------------------------------------
S_AXI4_WDATA => s_axi4_wdata , -- : in std_logic_vector((C_S_AXI4_DATA_WIDTH-1)downto 0);
S_AXI4_WSTRB => s_axi4_wstrb , -- : in std_logic_vector(((C_S_AXI4_DATA_WIDTH/8)-1) downto 0);
S_AXI4_WLAST => s_axi4_wlast , -- : in std_logic;
S_AXI4_WVALID => s_axi4_wvalid , -- : in std_logic;
S_AXI4_WREADY => s_axi4_wready , -- : out std_logic;
-------------------------------------------
-- AXI4 Full Write response channel Signals
-------------------------------------------
S_AXI4_BID => s_axi4_bid , -- : out std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0);
S_AXI4_BRESP => s_axi4_bresp , -- : out std_logic_vector(1 downto 0);
S_AXI4_BVALID => s_axi4_bvalid , -- : out std_logic;
S_AXI4_BREADY => s_axi4_bready , -- : in std_logic;
-----------------------------------
-- AXI Read Address channel signals
-----------------------------------
S_AXI4_ARID => s_axi4_arid , -- : in std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0);
S_AXI4_ARADDR => s_axi4_araddr , -- : in std_logic_vector((C_S_AXI4_ADDR_WIDTH-1) downto 0);
S_AXI4_ARLEN => s_axi4_arlen , -- : in std_logic_vector(7 downto 0);
S_AXI4_ARSIZE => s_axi4_arsize , -- : in std_logic_vector(2 downto 0);
S_AXI4_ARBURST => s_axi4_arburst, -- : in std_logic_vector(1 downto 0);
S_AXI4_ARLOCK => s_axi4_arlock , -- : in std_logic; -- not supported in design
S_AXI4_ARCACHE => s_axi4_arcache, -- : in std_logic_vector(3 downto 0);-- not supported in design
S_AXI4_ARPROT => s_axi4_arprot , -- : in std_logic_vector(2 downto 0);-- not supported in design
S_AXI4_ARVALID => s_axi4_arvalid, -- : in std_logic;
S_AXI4_ARREADY => s_axi4_arready, -- : out std_logic;
--------------------------------
-- AXI Read Data Channel signals
--------------------------------
S_AXI4_RID => s_axi4_rid , -- : out std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0);
S_AXI4_RDATA => s_axi4_rdata , -- : out std_logic_vector((C_S_AXI4_DATA_WIDTH-1) downto 0);
S_AXI4_RRESP => s_axi4_rresp , -- : out std_logic_vector(1 downto 0);
S_AXI4_RLAST => s_axi4_rlast , -- : out std_logic;
S_AXI4_RVALID => s_axi4_rvalid, -- : out std_logic;
S_AXI4_RREADY => s_axi4_rready, -- : in std_logic;
--------------------------------
XIPSR_CPHA_CPOL_ERR => TO_XIPSR_CPHA_CPOL_ERR_int , -- in std_logic
-------------------------------
TO_XIPSR_trans_error => TO_XIPSR_AXI_TR_ERR_int , -- out std_logic
TO_XIPSR_mst_modf_err => TO_XIPSR_mst_modf_err_int,
TO_XIPSR_axi_rx_full => TO_XIPSR_axi_rx_full_int ,
TO_XIPSR_axi_rx_empty => TO_XIPSR_axi_rx_empty_int,
-------------------------------
XIPCR_1_CPOL => XIPCR_1_CPOL_int , -- out std_logic;
XIPCR_0_CPHA => XIPCR_0_CPHA_int , -- out std_logic;
--*SPI port interface * --
-------------------------------
IO0_I => io0_i_sync_int, -- : in std_logic; -- MOSI signal in standard SPI
IO0_O => io0_o_int, -- : out std_logic;
IO0_T => io0_t_int, -- : out std_logic;
-------------------------------
IO1_I => io1_i_sync_int, -- : in std_logic; -- MISO signal in standard SPI
IO1_O => io1_o_int, -- : out std_logic;
IO1_T => io1_t_int, -- : out std_logic;
-----------------
-- quad mode pins
-----------------
IO2_I => io2_i_sync_int, -- : in std_logic;
IO2_O => io2_o_int, -- : out std_logic;
IO2_T => io2_t_int, -- : out std_logic;
---------------
IO3_I => io3_i_sync_int, -- : in std_logic;
IO3_O => io3_o_int, -- : out std_logic;
IO3_T => io3_t_int, -- : out std_logic;
---------------------------------
-- common pins
----------------
SPISEL => spisel, -- : in std_logic;
-----
SCK_I => sck_i , -- : in std_logic;
SCK_O_reg => SCK_O_int , -- : out std_logic;
SCK_T => sck_t , -- : out std_logic;
-----
SS_I => ss_i_int , -- : in std_logic_vector((C_NUM_SS_BITS-1) downto 0);
SS_O => ss_o_int , -- : out std_logic_vector((C_NUM_SS_BITS-1) downto 0);
SS_T => ss_t_int -- : out std_logic;
----------------------
);
-- no interrupt from this mode of core
IP2INTC_Irpt <= '0';
-------------------------------------------------------
-------------------------------------------------------
SCK_MISO_NO_STARTUP_USED: if C_USE_STARTUP = 0 generate
-----
begin
-----
SCK_O <= SCK_O_int; -- output from the core
MISO_I_int <= io1_i_sync; -- input to the core
end generate SCK_MISO_NO_STARTUP_USED;
-------------------------------------------------------
SCK_MISO_STARTUP_USED: if C_USE_STARTUP = 1 generate
-----
begin
-----
QSPI_STARTUP_BLOCK_I: entity axi_quad_spi_v3_2_8.qspi_startup_block
---------------------
generic map
(
C_SUB_FAMILY => C_FAMILY , -- support for V6/V7/K7/A7 families only
-----------------
C_USE_STARTUP => C_USE_STARTUP,
-----------------
C_SHARED_STARTUP => C_SHARED_STARTUP,
C_SPI_MODE => C_SPI_MODE
-----------------
)
port map
(
SCK_O => SCK_O_int, -- : in std_logic; -- input from the qspi_mode_0_module
IO1_I_startup => io1_i_sync, -- : in std_logic; -- input from the top level port list
IO1_Int => MISO_I_int,-- : out std_logic
Bus2IP_Clk => Bus2IP_Clk,
reset2ip_reset => bus2ip_reset_ipif4_inverted,
CFGCLK => cfgclk, -- FGCLK , -- 1-bit output: Configuration main clock output
CFGMCLK => cfgmclk, -- FGMCLK , -- 1-bit output: Configuration internal oscillator clock output
EOS => eos, -- OS , -- 1-bit output: Active high output signal indicating the End Of Startup.
PREQ => preq, -- REQ , -- 1-bit output: PROGRAM request to fabric output
DI => di_int, -- output
DO => do_int, -- 4-bit input
DTS => dts_int, -- 4-bit input
FCSBO => fcsbo_int, -- 1-bit input
FCSBTS => fcsbts_int,-- 1-bit input
CLK => clk, -- 1-bit input, SetReset
GSR => gsr, -- 1-bit input, SetReset
GTS => gts, -- 1-bit input
KEYCLEARB => keyclearb, --1-bit input
USRCCLKTS => usrcclkts, -- SRCCLKTS , -- 1-bit input
USRDONEO => usrdoneo, -- SRDONEO , -- 1-bit input
USRDONETS => usrdonets, -- SRDONETS -- 1-bit input
PACK => pack
);
--------------------
end generate SCK_MISO_STARTUP_USED;
end generate XIP_MODE_GEN;
------------------------------------------------------------------------------
end architecture imp;
------------------------------------------------------------------------------
|
bsd-3-clause
|
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/usb2device_v1_0/src/Context.vhd
|
2
|
16973
|
-------------------------------------------------------------------------------
--
-- File: Context.vhd
-- Author: Gherman Tudor
-- Original Project: USB Device IP on 7-series Xilinx FPGA
-- Date: 2 May 2016
--
-------------------------------------------------------------------------------
-- (c) 2016 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module implements the context memory (Queue Heads, Transfer Descriptors)
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Context is
generic (
MAX_NR_ENDP : integer := 1
);
Port ( CLK : in STD_LOGIC;
RESETN : in STD_LOGIC;
ENDPT_NR : in integer range 0 to (MAX_NR_ENDP*2+1);
-- ENDPT_NR_PD : in integer range 0 to 22;
RD_EN : in STD_LOGIC;
WR_EN : in STD_LOGIC;
dTD_TOTAL_BYTES_WR_EN : in STD_LOGIC;
dTD_STATUS_WR_EN : in STD_LOGIC;
dQH_CURRENT_dTD_POINTER_wr_EN : in STD_LOGIC;
dQH_NEXT_dTD_POINTER_wr_EN : in STD_LOGIC;
dQH_SETUP_BUFFER_wr_EN : in STD_LOGIC;
--READ
dQH_MULT_rd : out STD_LOGIC_VECTOR (1 downto 0);
dQH_ZLT_rd : out STD_LOGIC;
-- pe_dQH_ZLT_rd : out STD_LOGIC;
dQH_MAX_PACKET_LENGTH_rd : out STD_LOGIC_VECTOR (10 downto 0);
-- dQH_MAX_PACKET_LENGTH_rd_pd : out STD_LOGIC_VECTOR (10 downto 0);
dQH_IOS_rd : out STD_LOGIC;
dQH_CURRENT_dTD_POINTER_rd : out STD_LOGIC_VECTOR (26 downto 0);
dQH_NEXT_dTD_POINTER_rd : out STD_LOGIC_VECTOR (26 downto 0);
dQH_T_rd : out STD_LOGIC;
dQH_SETUP_BUFFER_BYTES_3_0_rd : out STD_LOGIC_VECTOR (31 downto 0);
dQH_SETUP_BUFFER_BYTES_7_4_rd : out STD_LOGIC_VECTOR (31 downto 0);
dTD_TOTAL_BYTES_rd : out STD_LOGIC_VECTOR (14 downto 0);
dTD_IOC_rd : out STD_LOGIC;
dTD_C_PAGE_rd : out STD_LOGIC_VECTOR (2 downto 0);
dTD_MULT_rd : out STD_LOGIC_VECTOR (1 downto 0);
dTD_STATUS_rd : out STD_LOGIC_VECTOR (7 downto 0);
dTD_PAGE0_rd : out STD_LOGIC_VECTOR (19 downto 0);
dTD_PAGE1_rd : out STD_LOGIC_VECTOR (19 downto 0);
dTD_PAGE2_rd : out STD_LOGIC_VECTOR (19 downto 0);
dTD_PAGE3_rd : out STD_LOGIC_VECTOR (19 downto 0);
dTD_PAGE4_rd : out STD_LOGIC_VECTOR (19 downto 0);
dTD_CURRENT_OFFSET_rd : out STD_LOGIC_VECTOR (11 downto 0);
--WRITE
dQH_MULT_wr : in STD_LOGIC_VECTOR (1 downto 0);
dQH_ZLT_wr : in STD_LOGIC;
dQH_MAX_PACKET_LENGTH_wr : in STD_LOGIC_VECTOR (10 downto 0);
dQH_IOS_wr : in STD_LOGIC;
dQH_CURRENT_dTD_POINTER_wr : in STD_LOGIC_VECTOR (26 downto 0);
dQH_NEXT_dTD_POINTER_wr : in STD_LOGIC_VECTOR (26 downto 0);
dQH_T_wr : in STD_LOGIC;
dQH_SETUP_BUFFER_BYTES_3_0_wr : in STD_LOGIC_VECTOR (31 downto 0);
dQH_SETUP_BUFFER_BYTES_7_4_wr : in STD_LOGIC_VECTOR (31 downto 0);
dTD_TOTAL_BYTES_wr : in STD_LOGIC_VECTOR (14 downto 0);
dTD_IOC_wr : in STD_LOGIC;
dTD_C_PAGE_wr : in STD_LOGIC_VECTOR (2 downto 0);
dTD_MULT_wr : in STD_LOGIC_VECTOR (1 downto 0);
dTD_STATUS_wr : in STD_LOGIC_VECTOR (7 downto 0);
dTD_PAGE0_wr : in STD_LOGIC_VECTOR (19 downto 0);
dTD_PAGE1_wr : in STD_LOGIC_VECTOR (19 downto 0);
dTD_PAGE2_wr : in STD_LOGIC_VECTOR (19 downto 0);
dTD_PAGE3_wr : in STD_LOGIC_VECTOR (19 downto 0);
dTD_PAGE4_wr : in STD_LOGIC_VECTOR (19 downto 0);
dTD_CURRENT_OFFSET_wr : in STD_LOGIC_VECTOR (11 downto 0)
);
end Context;
architecture Behavioral of Context is
type dQH is
record
dQH_MULT : STD_LOGIC_VECTOR (1 downto 0);
dQH_ZLT : STD_LOGIC;
dQH_MAX_PACKET_LENGTH : STD_LOGIC_VECTOR (10 downto 0);
dQH_IOS : STD_LOGIC;
dQH_CURRENT_dTD_POINTER : STD_LOGIC_VECTOR (26 downto 0);
dQH_NEXT_dTD_POINTER : STD_LOGIC_VECTOR (26 downto 0);
dQH_T : STD_LOGIC;
dQH_SETUP_BUFFER_BYTES_3_0 : STD_LOGIC_VECTOR (31 downto 0);
dQH_SETUP_BUFFER_BYTES_7_4 : STD_LOGIC_VECTOR (31 downto 0);
dTD_TOTAL_BYTES : STD_LOGIC_VECTOR (14 downto 0);
dTD_IOC : STD_LOGIC;
dTD_C_PAGE : STD_LOGIC_VECTOR (2 downto 0);
dTD_MULT : STD_LOGIC_VECTOR (1 downto 0);
dTD_STATUS : STD_LOGIC_VECTOR (7 downto 0);
dTD_PAGE0 : STD_LOGIC_VECTOR (19 downto 0);
dTD_PAGE1 : STD_LOGIC_VECTOR (19 downto 0);
dTD_PAGE2 : STD_LOGIC_VECTOR (19 downto 0);
dTD_PAGE3 : STD_LOGIC_VECTOR (19 downto 0);
dTD_PAGE4 : STD_LOGIC_VECTOR (19 downto 0);
dTD_CURRENT_OFFSET : STD_LOGIC_VECTOR (11 downto 0);
end record;
type array_DQH is array ((MAX_NR_ENDP*2+1) downto 0) of dQH;
signal dQH_reg : array_DQH;
signal byte_index : integer;
signal dQH_MULT_rd_mux : STD_LOGIC_VECTOR (1 downto 0);
signal dQH_ZLT_rd_mux : STD_LOGIC;
signal dQH_MAX_PACKET_LENGTH_rd_mux : STD_LOGIC_VECTOR (10 downto 0);
signal dQH_IOS_rd_mux : STD_LOGIC;
signal dQH_CURRENT_dTD_POINTER_rd_mux : STD_LOGIC_VECTOR (26 downto 0);
signal dQH_NEXT_dTD_POINTER_rd_mux : STD_LOGIC_VECTOR (26 downto 0);
signal dQH_T_rd_mux : STD_LOGIC;
signal dQH_SETUP_BUFFER_BYTES_3_0_rd_mux : STD_LOGIC_VECTOR (31 downto 0);
signal dQH_SETUP_BUFFER_BYTES_7_4_rd_mux : STD_LOGIC_VECTOR (31 downto 0);
signal dTD_TOTAL_BYTES_rd_mux : STD_LOGIC_VECTOR (14 downto 0);
signal dTD_IOC_rd_mux : STD_LOGIC;
signal dTD_C_PAGE_rd_mux : STD_LOGIC_VECTOR (2 downto 0);
signal dTD_MULT_rd_mux : STD_LOGIC_VECTOR (1 downto 0);
signal dTD_STATUS_rd_mux : STD_LOGIC_VECTOR (7 downto 0);
signal dTD_PAGE0_rd_mux : STD_LOGIC_VECTOR (19 downto 0);
signal dTD_PAGE1_rd_mux : STD_LOGIC_VECTOR (19 downto 0);
signal dTD_PAGE2_rd_mux : STD_LOGIC_VECTOR (19 downto 0);
signal dTD_PAGE3_rd_mux : STD_LOGIC_VECTOR (19 downto 0);
signal dTD_PAGE4_rd_mux : STD_LOGIC_VECTOR (19 downto 0);
signal dTD_CURRENT_OFFSET_rd_mux : STD_LOGIC_VECTOR (11 downto 0);
-- attribute mark_debug : string;
-- attribute keep : string;
-- attribute mark_debug of dQH_reg : signal is "true";
-- attribute keep of dQH_reg : signal is "true";
begin
dQH_MULT_rd <= dQH_MULT_rd_mux;
dQH_ZLT_rd <= dQH_ZLT_rd_mux;
dQH_MAX_PACKET_LENGTH_rd <= dQH_MAX_PACKET_LENGTH_rd_mux;
dQH_IOS_rd <= dQH_IOS_rd_mux;
dQH_CURRENT_dTD_POINTER_rd <= dQH_CURRENT_dTD_POINTER_rd_mux;
dQH_NEXT_dTD_POINTER_rd <= dQH_NEXT_dTD_POINTER_rd_mux;
dQH_T_rd <= dQH_T_rd_mux;
dQH_SETUP_BUFFER_BYTES_3_0_rd <= dQH_SETUP_BUFFER_BYTES_3_0_rd_mux;
dQH_SETUP_BUFFER_BYTES_7_4_rd <= dQH_SETUP_BUFFER_BYTES_7_4_rd_mux;
dTD_TOTAL_BYTES_rd <= dTD_TOTAL_BYTES_rd_mux;
dTD_IOC_rd <= dTD_IOC_rd_mux;
dTD_C_PAGE_rd <= dTD_C_PAGE_rd_mux;
dTD_MULT_rd <= dTD_MULT_rd_mux;
dTD_STATUS_rd <= dTD_STATUS_rd_mux;
dTD_PAGE0_rd <= dTD_PAGE0_rd_mux;
dTD_PAGE1_rd <= dTD_PAGE1_rd_mux;
dTD_PAGE2_rd <= dTD_PAGE2_rd_mux;
dTD_PAGE3_rd <= dTD_PAGE3_rd_mux;
dTD_PAGE4_rd <= dTD_PAGE4_rd_mux;
dTD_CURRENT_OFFSET_rd <= dTD_CURRENT_OFFSET_rd_mux;
process(CLK)
begin
if (rising_edge (CLK)) then
if (RESETN = '0') then
dQH_MULT_rd_mux <= (others => '0');
dQH_ZLT_rd_mux <= '0';
dQH_MAX_PACKET_LENGTH_rd_mux <= (others => '0');
dQH_IOS_rd_mux <= '0';
dQH_CURRENT_dTD_POINTER_rd_mux <= (others => '0');
dQH_NEXT_dTD_POINTER_rd_mux <= (others => '0');
dQH_T_rd_mux <= '0';
dQH_SETUP_BUFFER_BYTES_3_0_rd_mux <= (others => '0');
dQH_SETUP_BUFFER_BYTES_7_4_rd_mux <= (others => '0');
dTD_TOTAL_BYTES_rd_mux <= (others => '0');
dTD_IOC_rd_mux <= '0';
dTD_C_PAGE_rd_mux <= (others => '0');
dTD_MULT_rd_mux <= (others => '0');
dTD_STATUS_rd_mux <= (others => '0');
dTD_PAGE0_rd_mux <= (others => '0');
dTD_PAGE1_rd_mux <= (others => '0');
dTD_PAGE2_rd_mux <= (others => '0');
dTD_PAGE3_rd_mux <= (others => '0');
dTD_PAGE4_rd_mux <= (others => '0');
dTD_CURRENT_OFFSET_rd_mux <= (others => '0');
-- pe_dQH_ZLT_rd <= '0';
-- dQH_MAX_PACKET_LENGTH_rd_pd <= (others => '0');
else
dQH_MULT_rd_mux <= dQH_reg(ENDPT_NR).dQH_MULT;
dQH_ZLT_rd_mux <= dQH_reg(ENDPT_NR). dQH_ZLT;
dQH_MAX_PACKET_LENGTH_rd_mux <= dQH_reg(ENDPT_NR). dQH_MAX_PACKET_LENGTH;
dQH_IOS_rd_mux <= dQH_reg(ENDPT_NR). dQH_IOS;
dQH_CURRENT_dTD_POINTER_rd_mux <= dQH_reg(ENDPT_NR). dQH_CURRENT_dTD_POINTER;
dQH_NEXT_dTD_POINTER_rd_mux <= dQH_reg(ENDPT_NR). dQH_NEXT_dTD_POINTER;
dQH_T_rd_mux <= dQH_reg(ENDPT_NR). dQH_T;
dQH_SETUP_BUFFER_BYTES_3_0_rd_mux <= dQH_reg(ENDPT_NR). dQH_SETUP_BUFFER_BYTES_3_0;
dQH_SETUP_BUFFER_BYTES_7_4_rd_mux <= dQH_reg(ENDPT_NR). dQH_SETUP_BUFFER_BYTES_7_4;
dTD_TOTAL_BYTES_rd_mux <= dQH_reg(ENDPT_NR). dTD_TOTAL_BYTES;
dTD_IOC_rd_mux <= dQH_reg(ENDPT_NR). dTD_IOC;
dTD_C_PAGE_rd_mux <= dQH_reg(ENDPT_NR). dTD_C_PAGE;
dTD_MULT_rd_mux <= dQH_reg(ENDPT_NR). dTD_MULT;
dTD_STATUS_rd_mux <= dQH_reg(ENDPT_NR). dTD_STATUS;
dTD_PAGE0_rd_mux <= dQH_reg(ENDPT_NR). dTD_PAGE0;
dTD_PAGE1_rd_mux <= dQH_reg(ENDPT_NR). dTD_PAGE1;
dTD_PAGE2_rd_mux <= dQH_reg(ENDPT_NR). dTD_PAGE2;
dTD_PAGE3_rd_mux <= dQH_reg(ENDPT_NR). dTD_PAGE3;
dTD_PAGE4_rd_mux <= dQH_reg(ENDPT_NR). dTD_PAGE4;
dTD_CURRENT_OFFSET_rd_mux <= dQH_reg(ENDPT_NR). dTD_CURRENT_OFFSET;
-- pe_dQH_ZLT_rd <= dQH_reg(ENDPT_NR_PD). dQH_ZLT;
-- dQH_MAX_PACKET_LENGTH_rd_pd <= dQH_reg(ENDPT_NR_PD). dQH_MAX_PACKET_LENGTH;
end if;
end if;
end process;
process(CLK)
begin
if (rising_edge (CLK)) then
if (RESETN = '0') then
for index in 0 to (MAX_NR_ENDP*2+1) loop
dQH_reg(index). dQH_MULT <= (others => '0');
dQH_reg(index). dQH_ZLT <= '0';
dQH_reg(index). dQH_MAX_PACKET_LENGTH <= (others => '0');
dQH_reg(index). dQH_IOS <= '0';
dQH_reg(index). dQH_CURRENT_dTD_POINTER <= (others => '0');
dQH_reg(index). dQH_NEXT_dTD_POINTER <= (others => '0');
dQH_reg(index). dQH_T <= '0';
dQH_reg(index). dQH_SETUP_BUFFER_BYTES_3_0 <= (others => '0');
dQH_reg(index). dQH_SETUP_BUFFER_BYTES_7_4 <= (others => '0');
dQH_reg(index). dTD_TOTAL_BYTES <= (others => '0');
dQH_reg(index). dTD_IOC <= '0';
dQH_reg(index). dTD_C_PAGE <= (others => '0');
dQH_reg(index). dTD_MULT <= (others => '0');
dQH_reg(index). dTD_STATUS <= (others => '0');
dQH_reg(index). dTD_PAGE0 <= (others => '0');
dQH_reg(index). dTD_PAGE1 <= (others => '0');
dQH_reg(index). dTD_PAGE2 <= (others => '0');
dQH_reg(index). dTD_PAGE3 <= (others => '0');
dQH_reg(index). dTD_PAGE4 <= (others => '0');
dQH_reg(index). dTD_CURRENT_OFFSET <= (others => '0');
end loop;
elsif (WR_EN = '1') then
dQH_reg(ENDPT_NR). dQH_MULT <= dQH_MULT_wr;
dQH_reg(ENDPT_NR). dQH_ZLT <= dQH_ZLT_wr;
dQH_reg(ENDPT_NR). dQH_MAX_PACKET_LENGTH <= dQH_MAX_PACKET_LENGTH_wr;
dQH_reg(ENDPT_NR). dQH_IOS <= dQH_IOS_wr;
--dQH_reg(ENDPT_NR). dQH_CURRENT_dTD_POINTER <= dQH_CURRENT_dTD_POINTER_wr;
dQH_reg(ENDPT_NR). dQH_NEXT_dTD_POINTER <= dQH_NEXT_dTD_POINTER_wr;
dQH_reg(ENDPT_NR). dQH_T <= dQH_T_wr;
dQH_reg(ENDPT_NR). dQH_SETUP_BUFFER_BYTES_3_0 <= dQH_SETUP_BUFFER_BYTES_3_0_wr;
dQH_reg(ENDPT_NR). dQH_SETUP_BUFFER_BYTES_7_4 <= dQH_SETUP_BUFFER_BYTES_7_4_wr;
dQH_reg(ENDPT_NR). dTD_TOTAL_BYTES <= dTD_TOTAL_BYTES_wr;
dQH_reg(ENDPT_NR). dTD_IOC <= dTD_IOC_wr;
dQH_reg(ENDPT_NR). dTD_C_PAGE <= dTD_C_PAGE_wr;
dQH_reg(ENDPT_NR). dTD_MULT <= dTD_MULT_wr;
dQH_reg(ENDPT_NR). dTD_STATUS <= dTD_STATUS_wr;
dQH_reg(ENDPT_NR). dTD_PAGE0 <= dTD_PAGE0_wr;
dQH_reg(ENDPT_NR). dTD_PAGE1 <= dTD_PAGE1_wr;
dQH_reg(ENDPT_NR). dTD_PAGE2 <= dTD_PAGE2_wr;
dQH_reg(ENDPT_NR). dTD_PAGE3 <= dTD_PAGE3_wr;
dQH_reg(ENDPT_NR). dTD_PAGE4 <= dTD_PAGE4_wr;
dQH_reg(ENDPT_NR). dTD_CURRENT_OFFSET <= dTD_CURRENT_OFFSET_wr;
elsif (dTD_TOTAL_BYTES_WR_EN = '1') then
dQH_reg(ENDPT_NR). dTD_TOTAL_BYTES <= dTD_TOTAL_BYTES_wr;
elsif (dQH_CURRENT_dTD_POINTER_wr_EN = '1') then
dQH_reg(ENDPT_NR). dQH_CURRENT_dTD_POINTER <= dQH_CURRENT_dTD_POINTER_wr;
elsif (dQH_NEXT_dTD_POINTER_wr_EN = '1') then
dQH_reg(ENDPT_NR). dQH_NEXT_dTD_POINTER <= dQH_NEXT_dTD_POINTER_wr;
elsif (dTD_STATUS_WR_EN = '1') then
dQH_reg(ENDPT_NR). dTD_STATUS <= dTD_STATUS_wr;
elsif (dQH_SETUP_BUFFER_wr_EN = '1') then
dQH_reg(ENDPT_NR). dQH_SETUP_BUFFER_BYTES_3_0 <= dQH_SETUP_BUFFER_BYTES_3_0_wr;
dQH_reg(ENDPT_NR). dQH_SETUP_BUFFER_BYTES_7_4 <= dQH_SETUP_BUFFER_BYTES_7_4_wr;
end if;
end if;
end process;
end Behavioral;
|
bsd-3-clause
|
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/usb2device_v1_0/src/axi_dma_0/axi_sg_v4_1_2/hdl/src/vhdl/axi_sg_skid2mm_buf.vhd
|
7
|
17071
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_skid2mm_buf.vhd
--
-- Description:
-- Implements the AXi Skid Buffer in the Option 2 (Registerd outputs) mode.
--
-- This Module also provides Write Data Bus Mirroring and WSTRB
-- Demuxing to match a narrow Stream to a wider MMap Write
-- Channel. By doing this in the skid buffer, the resource
-- utilization of the skid buffer can be minimized by only
-- having to buffer/mux the Stream data width, not the MMap
-- Data width.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_sg_v4_1_2;
use axi_sg_v4_1_2.axi_sg_wr_demux;
-------------------------------------------------------------------------------
entity axi_sg_skid2mm_buf is
generic (
C_MDATA_WIDTH : INTEGER range 32 to 1024 := 32 ;
-- Width of the MMap Write Data bus (in bits)
C_SDATA_WIDTH : INTEGER range 8 to 1024 := 32 ;
-- Width of the Stream Data bus (in bits)
C_ADDR_LSB_WIDTH : INTEGER range 1 to 8 := 5
-- Width of the LS address bus needed to Demux the WSTRB
);
port (
-- Clock and Reset Inputs -------------------------------------------
--
ACLK : In std_logic ; --
ARST : In std_logic ; --
---------------------------------------------------------------------
-- Slave Side (Wr Data Controller Input Side) -----------------------
--
S_ADDR_LSB : in std_logic_vector(C_ADDR_LSB_WIDTH-1 downto 0); --
S_VALID : In std_logic ; --
S_READY : Out std_logic ; --
S_DATA : In std_logic_vector(C_SDATA_WIDTH-1 downto 0); --
S_STRB : In std_logic_vector((C_SDATA_WIDTH/8)-1 downto 0); --
S_LAST : In std_logic ; --
---------------------------------------------------------------------
-- Master Side (MMap Write Data Output Side) ------------------------
M_VALID : Out std_logic ; --
M_READY : In std_logic ; --
M_DATA : Out std_logic_vector(C_MDATA_WIDTH-1 downto 0); --
M_STRB : Out std_logic_vector((C_MDATA_WIDTH/8)-1 downto 0); --
M_LAST : Out std_logic --
---------------------------------------------------------------------
);
end entity axi_sg_skid2mm_buf;
architecture implementation of axi_sg_skid2mm_buf is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
Constant IN_DATA_WIDTH : integer := C_SDATA_WIDTH;
Constant MM2STRM_WIDTH_RATIO : integer := C_MDATA_WIDTH/C_SDATA_WIDTH;
-- Signals decalrations -------------------------
Signal sig_reset_reg : std_logic := '0';
signal sig_spcl_s_ready_set : std_logic := '0';
signal sig_data_skid_reg : std_logic_vector(IN_DATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_skid_reg : std_logic_vector((C_MDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_skid_reg : std_logic := '0';
signal sig_skid_reg_en : std_logic := '0';
signal sig_data_skid_mux_out : std_logic_vector(IN_DATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_skid_mux_out : std_logic_vector((C_MDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_skid_mux_out : std_logic := '0';
signal sig_skid_mux_sel : std_logic := '0';
signal sig_data_reg_out : std_logic_vector(IN_DATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_reg_out : std_logic_vector((C_MDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_reg_out : std_logic := '0';
signal sig_data_reg_out_en : std_logic := '0';
signal sig_m_valid_out : std_logic := '0';
signal sig_m_valid_dup : std_logic := '0';
signal sig_m_valid_comb : std_logic := '0';
signal sig_s_ready_out : std_logic := '0';
signal sig_s_ready_dup : std_logic := '0';
signal sig_s_ready_comb : std_logic := '0';
signal sig_mirror_data_out : std_logic_vector(C_MDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_wstrb_demux_out : std_logic_vector((C_MDATA_WIDTH/8)-1 downto 0) := (others => '0');
-- Register duplication attribute assignments to control fanout
-- on handshake output signals
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
Attribute KEEP of sig_m_valid_out : signal is "TRUE"; -- definition
Attribute KEEP of sig_m_valid_dup : signal is "TRUE"; -- definition
Attribute KEEP of sig_s_ready_out : signal is "TRUE"; -- definition
Attribute KEEP of sig_s_ready_dup : signal is "TRUE"; -- definition
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_m_valid_out : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_m_valid_dup : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_out : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_dup : signal is "no";
begin --(architecture implementation)
M_VALID <= sig_m_valid_out;
S_READY <= sig_s_ready_out;
M_STRB <= sig_strb_reg_out;
M_LAST <= sig_last_reg_out;
M_DATA <= sig_mirror_data_out;
-- Assign the special S_READY FLOP set signal
sig_spcl_s_ready_set <= sig_reset_reg;
-- Generate the ouput register load enable control
sig_data_reg_out_en <= M_READY or not(sig_m_valid_dup);
-- Generate the skid inpit register load enable control
sig_skid_reg_en <= sig_s_ready_dup;
-- Generate the skid mux select control
sig_skid_mux_sel <= not(sig_s_ready_dup);
-- Skid Mux
sig_data_skid_mux_out <= sig_data_skid_reg
When (sig_skid_mux_sel = '1')
Else S_DATA;
sig_strb_skid_mux_out <= sig_strb_skid_reg
When (sig_skid_mux_sel = '1')
--Else S_STRB;
Else sig_wstrb_demux_out;
sig_last_skid_mux_out <= sig_last_skid_reg
When (sig_skid_mux_sel = '1')
Else S_LAST;
-- m_valid combinational logic
sig_m_valid_comb <= S_VALID or
(sig_m_valid_dup and
(not(sig_s_ready_dup) or
not(M_READY)));
-- s_ready combinational logic
sig_s_ready_comb <= M_READY or
(sig_s_ready_dup and
(not(sig_m_valid_dup) or
not(S_VALID)));
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_THE_RST
--
-- Process Description:
-- Register input reset
--
-------------------------------------------------------------
REG_THE_RST : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
sig_reset_reg <= ARST;
end if;
end process REG_THE_RST;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: S_READY_FLOP
--
-- Process Description:
-- Registers S_READY handshake signals per Skid Buffer
-- Option 2 scheme
--
-------------------------------------------------------------
S_READY_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_s_ready_out <= '0';
sig_s_ready_dup <= '0';
Elsif (sig_spcl_s_ready_set = '1') Then
sig_s_ready_out <= '1';
sig_s_ready_dup <= '1';
else
sig_s_ready_out <= sig_s_ready_comb;
sig_s_ready_dup <= sig_s_ready_comb;
end if;
end if;
end process S_READY_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: M_VALID_FLOP
--
-- Process Description:
-- Registers M_VALID handshake signals per Skid Buffer
-- Option 2 scheme
--
-------------------------------------------------------------
M_VALID_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1' or
sig_spcl_s_ready_set = '1') then -- Fix from AXI DMA
sig_m_valid_out <= '0';
sig_m_valid_dup <= '0';
else
sig_m_valid_out <= sig_m_valid_comb;
sig_m_valid_dup <= sig_m_valid_comb;
end if;
end if;
end process M_VALID_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SKID_DATA_REG
--
-- Process Description:
-- This process implements the Skid register for the
-- Skid Buffer Data signals.
--
-------------------------------------------------------------
SKID_DATA_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (sig_skid_reg_en = '1') then
sig_data_skid_reg <= S_DATA;
else
null; -- hold current state
end if;
end if;
end process SKID_DATA_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SKID_CNTL_REG
--
-- Process Description:
-- This process implements the Output registers for the
-- Skid Buffer Control signals
--
-------------------------------------------------------------
SKID_CNTL_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_strb_skid_reg <= (others => '0');
sig_last_skid_reg <= '0';
elsif (sig_skid_reg_en = '1') then
sig_strb_skid_reg <= sig_wstrb_demux_out;
sig_last_skid_reg <= S_LAST;
else
null; -- hold current state
end if;
end if;
end process SKID_CNTL_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: OUTPUT_DATA_REG
--
-- Process Description:
-- This process implements the Output register for the
-- Data signals.
--
-------------------------------------------------------------
OUTPUT_DATA_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (sig_data_reg_out_en = '1') then
sig_data_reg_out <= sig_data_skid_mux_out;
else
null; -- hold current state
end if;
end if;
end process OUTPUT_DATA_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: OUTPUT_CNTL_REG
--
-- Process Description:
-- This process implements the Output registers for the
-- control signals.
--
-------------------------------------------------------------
OUTPUT_CNTL_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_strb_reg_out <= (others => '0');
sig_last_reg_out <= '0';
elsif (sig_data_reg_out_en = '1') then
sig_strb_reg_out <= sig_strb_skid_mux_out;
sig_last_reg_out <= sig_last_skid_mux_out;
else
null; -- hold current state
end if;
end if;
end process OUTPUT_CNTL_REG;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_WR_DATA_MIRROR
--
-- Process Description:
-- Implement the Write Data Mirror structure
--
-- Note that it is required that the Stream Width be less than
-- or equal to the MMap WData width.
--
-------------------------------------------------------------
DO_WR_DATA_MIRROR : process (sig_data_reg_out)
begin
for slice_index in 0 to MM2STRM_WIDTH_RATIO-1 loop
sig_mirror_data_out(((C_SDATA_WIDTH*slice_index)+C_SDATA_WIDTH)-1
downto C_SDATA_WIDTH*slice_index)
<= sig_data_reg_out;
end loop;
end process DO_WR_DATA_MIRROR;
------------------------------------------------------------
-- Instance: I_WSTRB_DEMUX
--
-- Description:
-- Instance for the Write Strobe DeMux.
--
------------------------------------------------------------
I_WSTRB_DEMUX : entity axi_sg_v4_1_2.axi_sg_wr_demux
generic map (
C_SEL_ADDR_WIDTH => C_ADDR_LSB_WIDTH ,
C_MMAP_DWIDTH => C_MDATA_WIDTH ,
C_STREAM_DWIDTH => C_SDATA_WIDTH
)
port map (
wstrb_in => S_STRB ,
demux_wstrb_out => sig_wstrb_demux_out ,
debeat_saddr_lsb => S_ADDR_LSB
);
end implementation;
|
bsd-3-clause
|
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/rgb2dvi_v1_2/src/SyncAsyncReset.vhd
|
29
|
3734
|
-------------------------------------------------------------------------------
--
-- File: SyncAsyncReset.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 20 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module is a reset-bridge. It takes a reset signal asynchronous to the
-- target clock domain (OutClk) and provides a safe asynchronous or synchronous
-- reset for the OutClk domain (oRst). The signal oRst is asserted immediately
-- as aRst arrives, but is de-asserted synchronously with the OutClk rising
-- edge. This means it can be used to safely reset any FF in the OutClk domain,
-- respecting recovery time specs for FFs.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ResetBridge is
Generic (
kPolarity : std_logic := '1');
Port (
aRst : in STD_LOGIC; -- asynchronous reset; active-high, if kPolarity=1
OutClk : in STD_LOGIC;
oRst : out STD_LOGIC);
end ResetBridge;
architecture Behavioral of ResetBridge is
signal aRst_int : std_logic;
attribute KEEP : string;
attribute KEEP of aRst_int: signal is "TRUE";
begin
aRst_int <= kPolarity xnor aRst; --SyncAsync uses active-high reset
SyncAsyncx: entity work.SyncAsync
generic map (
kResetTo => kPolarity,
kStages => 2) --use double FF synchronizer
port map (
aReset => aRst_int,
aIn => not kPolarity,
OutClk => OutClk,
oOut => oRst);
end Behavioral;
|
bsd-3-clause
|
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/dvi2rgb_v1_7/src/SyncAsyncReset.vhd
|
29
|
3734
|
-------------------------------------------------------------------------------
--
-- File: SyncAsyncReset.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 20 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module is a reset-bridge. It takes a reset signal asynchronous to the
-- target clock domain (OutClk) and provides a safe asynchronous or synchronous
-- reset for the OutClk domain (oRst). The signal oRst is asserted immediately
-- as aRst arrives, but is de-asserted synchronously with the OutClk rising
-- edge. This means it can be used to safely reset any FF in the OutClk domain,
-- respecting recovery time specs for FFs.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ResetBridge is
Generic (
kPolarity : std_logic := '1');
Port (
aRst : in STD_LOGIC; -- asynchronous reset; active-high, if kPolarity=1
OutClk : in STD_LOGIC;
oRst : out STD_LOGIC);
end ResetBridge;
architecture Behavioral of ResetBridge is
signal aRst_int : std_logic;
attribute KEEP : string;
attribute KEEP of aRst_int: signal is "TRUE";
begin
aRst_int <= kPolarity xnor aRst; --SyncAsync uses active-high reset
SyncAsyncx: entity work.SyncAsync
generic map (
kResetTo => kPolarity,
kStages => 2) --use double FF synchronizer
port map (
aReset => aRst_int,
aIn => not kPolarity,
OutClk => OutClk,
oOut => oRst);
end Behavioral;
|
bsd-3-clause
|
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/clock_forwarder_1.0/hdl/clock_forwarder_v1_0.vhd
|
3
|
881
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
Library UNISIM;
use UNISIM.vcomponents.all;
entity clock_forwarder_v1_0 is
port (
aRst : in std_logic;
InClk : in std_logic;
iCE : in std_logic;
OutClk : out std_logic
);
end clock_forwarder_v1_0;
architecture arch_imp of clock_forwarder_v1_0 is
begin
ODDR_inst : ODDR
generic map(
DDR_CLK_EDGE => "OPPOSITE_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE"
INIT => '0', -- Initial value for Q port ('1' or '0')
SRTYPE => "ASYNC") -- Reset Type ("ASYNC" or "SYNC")
port map (
Q => OutClk, -- 1-bit DDR output
C => InClk, -- 1-bit clock input
CE => iCE, -- 1-bit clock enable input
D1 => '1', -- 1-bit data input (positive edge)
D2 => '0', -- 1-bit data input (negative edge)
R => aRst, -- 1-bit reset input
S => '0' -- 1-bit set input
);
end arch_imp;
|
bsd-3-clause
|
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/Partial_Designs/Source/sobel_filter/sobel_filter.vhd
|
1
|
5844
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 02/07/2017 02:26:58 PM
-- Design Name:
-- Module Name: blur - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library work;
use work.filter_lib.all;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity sobel_filter is
port (
vid_i : in rgb_interface_t;
vid_o : out rgb_interface_t;
x_position : in std_logic_vector(15 downto 0);
threshold : in std_logic_vector(7 downto 0);
sensitivity : in std_logic_vector(3 downto 0);
invert : in std_logic;
split_line : in std_logic_vector(15 downto 0);
rotoscope : in std_logic;
PIXEL_CLK : in std_logic
);
end sobel_filter;
architecture Behavioral of sobel_filter is
-- We need to convert the image to grayscale before processing it.
signal pixel_in : pixel_t;
-- Size of the filter
constant FILTER_WIDTH : natural := 3;
constant FILTER_HEIGHT : natural := 3;
-- Output of the linebuffer / Input to the filters
signal window : pixel2d_t(FILTER_WIDTH - 1 downto 0, FILTER_HEIGHT - 1 downto 0);
-- Kernels for our filters
constant sobel_x_kernel : kernel_matrix_t(FILTER_WIDTH - 1 downto 0, FILTER_HEIGHT - 1 downto 0) := (
(-1, 0, 1),
(-2, 0, 2),
(-1, 0, 1)
);
constant sobel_y_kernel : kernel_matrix_t(FILTER_WIDTH - 1 downto 0, FILTER_HEIGHT - 1 downto 0) := (
(-1,-2,-1),
( 0, 0, 0),
( 1, 2, 1)
);
-- Results of the two filter kernels
signal sobel_x, sobel_y : signed(21 downto 0) := (others => '0');
-- Post-filter computations and results (thresholding, truncation, saturation, inversion, etc.)
signal sobel_mag, sobel_shift : signed(21 downto 0);
signal sobel_trunc, sobel_sat, sobel_inv : std_logic_vector(7 downto 0);
signal roto_rgb, roto_combined, rgb_buf, rgb_buf_reg : std_logic_vector(23 downto 0);
-- Buffered output
signal vid_buf, vid_buf_reg, vid_out : rgb_interface_t;
begin
-- Convert input to grayscale
pixel_in <=
std_logic_vector(
resize(unsigned( vid_i.RGB(23 downto 16) ), 10) +
resize(unsigned( vid_i.RGB(15 downto 8) ), 10) +
resize(unsigned( vid_i.RGB( 7 downto 0) ), 10)
);
-- Parameterizable pixel buffer
pixel_buf: entity work.pixel_buffer(Behavioral)
generic map (
WIDTH => FILTER_WIDTH,
HEIGHT => FILTER_HEIGHT,
LINE_LENGTH => 2048
)
port map (
-- Clock
CLK => PIXEL_CLK,
-- Inputs
data_in => pixel_in,
vde_in => vid_i.vde,
hs_in => vid_i.hs,
vs_in => vid_i.vs,
-- Outputs
data_out => window,
vde_out => vid_buf.vde,
hs_out => vid_buf.hs,
vs_out => vid_buf.vs
);
vid_buf.rgb <= vid_i.rgb;
-- Filter kernels
sobel_x_filter : entity work.filter_kernel(Combinational)
generic map (
WIDTH => FILTER_WIDTH,
HEIGHT => FILTER_HEIGHT,
kernel => sobel_x_kernel
)
port map (
data_in => window,
data_out => sobel_x
);
sobel_y_filter : entity work.filter_kernel(Combinational)
generic map (
WIDTH => FILTER_WIDTH,
HEIGHT => FILTER_HEIGHT,
kernel => sobel_y_kernel
)
port map (
data_in => window,
data_out => sobel_y
);
-- Process the outputs of the filters
-- Approximate magnitude
sobel_mag <= abs(sobel_x) + abs(sobel_y);
-- Move the radix point
sobel_shift <= sobel_mag srl to_integer(unsigned(sensitivity));
-- Truncate
sobel_trunc <= std_logic_vector(sobel_shift(7 downto 0));
-- Threshold and Saturate
sobel_sat <= (others=>'0') when unsigned(sobel_shift) < unsigned(threshold) else
(others=>'1') when unsigned(sobel_shift) > 255 else
sobel_trunc;
-- Invert
sobel_inv <= sobel_sat when invert = '0' else
not(sobel_sat);
-- Rotoscoping Logic
-- Give the color a nice "palettized" look
roto_rgb <= vid_i.RGB(23 downto 20) & vid_i.RGB(23 downto 20) -- R
& vid_i.RGB(15 downto 12) & vid_i.RGB(15 downto 12) -- G
& vid_i.RGB(7 downto 4) & vid_i.RGB(7 downto 4); -- B
roto_combined <= (sobel_inv & sobel_inv & sobel_inv) when unsigned(sobel_shift) > 255 else
roto_rgb;
-- Select Rotoscope
rgb_buf <= roto_combined when (rotoscope = '1') else
(sobel_inv & sobel_inv & sobel_inv);
-- Buffer stage
process(PIXEL_CLK)
begin
if (rising_edge(PIXEL_CLK)) then
-- Buffer stage
rgb_buf_reg <= rgb_buf;
vid_buf_reg <= vid_buf;
-- Do splitscreen and buffer the output
if (unsigned(x_position) < unsigned(split_line)) then
vid_out.rgb <= rgb_buf_reg;
else
vid_out.rgb <= vid_buf_reg.rgb;
end if;
vid_out.vde <= vid_buf_reg.vde;
vid_out.hs <= vid_buf_reg.hs;
vid_out.vs <= vid_buf_reg.vs;
end if;
end process;
-- Output
vid_o <= vid_out;
end Behavioral;
|
bsd-3-clause
|
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/usb2device_v1_0/src/DMA_Transfer_Manager.vhd
|
2
|
77140
|
-------------------------------------------------------------------------------
--
-- File: DMA_Transfer_Manager.vhd
-- Author: Gherman Tudor
-- Original Project: USB Device IP on 7-series Xilinx FPGA
-- Date: 2 May 2016
--
-------------------------------------------------------------------------------
-- (c) 2016 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module manages all transfers from main memory to local buffers through
-- DMA, both control data (Queue Heads, Transfer Descriptors)and packet data.
-- Control registers are visible to this module.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.numeric_std.all;
entity DMA_Transfer_Manager is
generic (
-- The master will start generating data from the C_M_START_DATA_VALUE value
C_M_START_DATA_VALUE : std_logic_vector := x"AA000000";
-- The master requires a target slave base address.
-- The master will initiate read and write transactions on the slave with base address specified here as a parameter.
C_M_TARGET_SLAVE_BASE_ADDR : std_logic_vector := "0100000000";
-- Width of M_AXI address bus.
-- The master generates the read and write addresses of width specified as C_M_AXI_ADDR_WIDTH.
C_M_AXI_ADDR_WIDTH : integer := 10;
-- Width of M_AXI data bus.
-- The master issues write data and accept read data where the width of the data bus is C_M_AXI_DATA_WIDTH
C_M_AXI_DATA_WIDTH : integer := 32;
-- Transaction number is the number of write
-- and read transactions the master will perform as a part of this example memory test.
C_M_TRANSACTIONS_NUM : integer := 4;
C_FIFO_SIZE : integer := 64
);
port (
Axi_Clk : IN std_logic;
Axi_Resetn : IN std_logic;
state_ind_dma : out STD_LOGIC_VECTOR(4 downto 0); --debug purposes
state_ind_arb : out std_logic_vector(5 downto 0); --debug purposes
DEBUG_REG_DATA : OUT std_logic_vector(31 downto 0); --debug purposes
ind_statte_axistream : out std_logic_vector(4 downto 0); --debug purposes
--AXI Lite Master for DMA control
a_M_Axi_Awaddr : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
a_M_Axi_Awprot : out std_logic_vector(2 downto 0);
a_M_Axi_Awvalid : out std_logic;
a_M_Axi_Awready : in std_logic;
a_M_Axi_Wdata : out std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
a_M_Axi_Wstrb : out std_logic_vector(C_M_AXI_DATA_WIDTH/8-1 downto 0);
a_M_Axi_Wvalid : out std_logic;
a_M_Axi_Wready : in std_logic;
a_M_Axi_Bresp : in std_logic_vector(1 downto 0);
a_M_Axi_Bvalid : in std_logic;
a_M_Axi_Bready : out std_logic;
a_M_Axi_Araddr : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
a_M_Axi_Arprot : out std_logic_vector(2 downto 0);
a_M_Axi_Arvalid : out std_logic;
a_M_Axi_Arready : in std_logic;
a_M_Axi_Rdata : in std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
a_M_Axi_Rresp : in std_logic_vector(1 downto 0);
a_M_Axi_Rvalid : in std_logic;
a_M_Axi_Rready : out std_logic;
--AXI Stream interface taht enables the DMA to write/read to/from the Context Memory
a_S_Axis_MM2S_Tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
a_S_Axis_MM2S_Tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
a_S_Axis_MM2S_Tvalid : IN STD_LOGIC;
a_S_Axis_MM2S_Tready : OUT STD_LOGIC;
a_S_Axis_MM2S_Tlast : IN STD_LOGIC;
a_M_Axis_S2MM_Tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
a_M_Axis_S2MM_Tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
a_M_Axis_S2MM_Tvalid : OUT STD_LOGIC;
a_M_Axis_S2MM_Tready : IN STD_LOGIC;
a_M_Axis_S2MM_Tlast : OUT STD_LOGIC;
--Command FIFO; used to keep track of received OUT transactions
RX_COMMAND_FIFO_RD_EN : OUT std_logic;
RX_COMMAND_FIFO_DOUT : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
RX_COMMAND_FIFO_EMPTY : IN std_logic;
RX_COMMAND_FIFO_VALID : IN std_logic;
--FIFO control signals
arb_tx_fifo_s_aresetn : OUT std_logic;
--multiplex between FIFO access and Context memory access
a_Axis_MM2S_Mux_Ctrl : OUT STD_LOGIC;
a_Axis_S2MM_Mux_Ctrl : OUT STD_LOGIC;
--Protocol_Engine interface
a_Send_Zero_Length_Packet_Set : OUT STD_LOGIC_VECTOR(31 downto 0); --ZLP Hanshake between Packet_Decoder and DMA_Transfer_Manager
a_Send_Zero_Length_Packet_Set_En : OUT STD_LOGIC; --ZLP Hanshake between Packet_Decoder and DMA_Transfer_Manager
a_Send_Zero_Length_Packet_Ack_Rd : IN STD_LOGIC_VECTOR(31 downto 0); --ZLP Hanshake between Packet_Decoder and DMA_Transfer_Manager
a_Send_Zero_Length_Packet_Ack_Clear : OUT STD_LOGIC_VECTOR(31 downto 0); --ZLP Hanshake between Packet_Decoder and DMA_Transfer_Manager
a_Send_Zero_Length_Packet_Ack_Clear_En : OUT STD_LOGIC; --ZLP Hanshake between Packet_Decoder and DMA_Transfer_Manager
a_Arb_dQH_Setup_Buffer_Bytes_3_0_Wr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); --Setup packets are stored in these registers before being copied into the dQH
a_Arb_dQH_Setup_Buffer_Bytes_7_4_Wr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); --Setup packets are stored in these registers before being copied into the dQH
a_In_Packet_Complete_Rd : IN STD_LOGIC_VECTOR(31 downto 0); --a bit is set when the corresponding endpoint has completed an IN transaction
a_In_Packet_Complete_Clear : OUT STD_LOGIC_VECTOR(31 downto 0); --In_Packet_Complete Hanshake between DMA_Transfer_Manager and Packet_Decoder
a_In_Packet_Complete_Clear_En : OUT STD_LOGIC; --In_Packet_Complete Hanshake between DMA_Transfer_Manager and Packet_Decoder
a_In_Token_Received_Rd : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- a bit is set when the corresponding endpoint has received an IN token
a_In_Token_Received_Clear : OUT STD_LOGIC_VECTOR(31 downto 0); --In_Token_Received_Clear Hanshake between DMA_Transfer_Manager and Packet_Decoder
a_In_Token_Received_Clear_En : OUT STD_LOGIC; --In_Token_Received_Clear Hanshake between DMA_Transfer_Manager and Packet_Decoder
a_Cnt_Bytes_Sent : in std_logic_vector(12 downto 0); --number of bytes sent in response to an IN token
a_Cnt_Bytes_Sent_oValid : IN std_logic;
a_Resend : IN STD_LOGIC_VECTOR(31 DOWNTO 0); --indicates that the endpoint corresponding to set bits need to resend a packet
a_Resend_Clear : OUT STD_LOGIC_VECTOR(31 downto 0); --Resend Hanshake between DMA_Transfer_Manager and Packet_Decoder
a_Resend_Clear_En : OUT STD_LOGIC; --Resend Hanshake between DMA_Transfer_Manager and Packet_Decoder
a_Pe_Endpt_Nr : IN STD_LOGIC_VECTOR(4 DOWNTO 0); --endpoint accessed by the lower layers (ULPI, Packet_Decoder)
a_Arb_Endpt_Nr : OUT std_logic_vector(4 downto 0); --endpoint accessed by the DMA_Transfer_Manager
--Control_Registers interface
a_USBSTS_Wr_UI : OUT std_logic;
a_USBSTS_Wr_en_UI : OUT std_logic;
a_USBMODE_Rd : in std_logic_vector(31 downto 0);
a_USBCMD_SUTW_Wr : out std_logic;
a_USBCMD_SUTW_Wr_En : out std_logic;
a_USBCMD_ATDTW_Wr : out std_logic;
a_USBCMD_ATDTW_Wr_En : out std_logic;
a_EMDPTFLUSH_Rd : in std_logic_vector(31 downto 0);
a_EMDPTFLUSH_Set : out std_logic_vector(31 downto 0);
a_EMDPTFLUSH_Set_En : out std_logic;
a_ENDPTPRIME_Rd : in std_logic_vector(31 downto 0);
a_ENDPTPRIME_Clear : out std_logic_vector(31 downto 0);
a_ENDPTPRIME_Clear_En : out std_logic;
a_ENDPTPRIME_Set : out std_logic_vector(31 downto 0);
a_ENDPTPRIME_Set_En : out std_logic;
a_ENDPTSTAT_Wr : out std_logic_vector(31 downto 0);
a_ENDPTCOMPLETE_Wr : out std_logic_vector(31 downto 0);
a_ENDPTCOMPLETE_Wr_En : out std_logic;
a_ENDPTSETUPSTAT_Wr : out std_logic_vector(31 downto 0);
a_ENDPTSETUPSTAT_Wr_En : out std_logic;
a_Arb_ENDPTSETUP_RECEIVED_Rd : in std_logic_vector(31 downto 0);
a_Arb_ENDPTSETUP_RECEIVED_Clear : out std_logic_vector(31 downto 0);
a_Arb_ENDPTSETUP_RECEIVED_Clear_En : out std_logic;
a_Arb_ENDPTSETUP_RECEIVED_Ack : in std_logic;
a_ENDPOINTLISTADDR_Rd : in std_logic_vector(31 downto 0)
);
end DMA_Transfer_Manager;
architecture implementation of DMA_Transfer_Manager is
COMPONENT DMA_Operations
PORT(
CLK : in STD_LOGIC;
RESETN : in STD_LOGIC;
DEBUG_REG_DATA : OUT std_logic_vector(31 downto 0);
state_ind_dma : out STD_LOGIC_VECTOR(4 downto 0);
M_AXI_AWREADY : IN std_logic;
M_AXI_WREADY : IN std_logic;
M_AXI_BRESP : IN std_logic_vector(1 downto 0);
M_AXI_BVALID : IN std_logic;
M_AXI_ARREADY : IN std_logic;
M_AXI_RDATA : IN std_logic_vector(31 downto 0);
M_AXI_RRESP : IN std_logic_vector(1 downto 0);
M_AXI_RVALID : IN std_logic;
M_AXI_AWADDR : OUT std_logic_vector(9 downto 0);
M_AXI_AWPROT : OUT std_logic_vector(2 downto 0);
M_AXI_AWVALID : OUT std_logic;
M_AXI_WDATA : OUT std_logic_vector(31 downto 0);
M_AXI_WSTRB : OUT std_logic_vector(3 downto 0);
M_AXI_WVALID : OUT std_logic;
M_AXI_BREADY : OUT std_logic;
M_AXI_ARADDR : OUT std_logic_vector(9 downto 0);
M_AXI_ARPROT : OUT std_logic_vector(2 downto 0);
M_AXI_ARVALID : OUT std_logic;
M_AXI_RREADY : OUT std_logic;
dma_transfer_complete : OUT std_logic;
start_dma_s2mm : IN std_logic;
start_dma_mm2s : IN std_logic;
dma_transfer_length : in STD_LOGIC_VECTOR(31 downto 0);
dma_source_dest_address : IN std_logic_vector(31 downto 0)
);
END COMPONENT;
COMPONENT Context
PORT(
CLK : IN std_logic;
RESETN : IN std_logic;
ENDPT_NR : in integer range 0 to 22;
-- ENDPT_NR_PD : in integer range 0 to 22;
RD_EN : IN std_logic;
WR_EN : IN std_logic;
dTD_TOTAL_BYTES_WR_EN : IN std_logic;
dTD_STATUS_WR_EN : IN std_logic;
dQH_CURRENT_dTD_POINTER_wr_EN : in STD_LOGIC;
dQH_NEXT_dTD_POINTER_wr_EN : in STD_LOGIC;
dQH_SETUP_BUFFER_wr_EN : in STD_LOGIC;
dQH_MULT_wr : IN std_logic_vector(1 downto 0);
dQH_ZLT_wr : IN std_logic;
dQH_MAX_PACKET_LENGTH_wr : IN std_logic_vector(10 downto 0);
dQH_IOS_wr : IN std_logic;
dQH_CURRENT_dTD_POINTER_wr : IN std_logic_vector(26 downto 0);
dQH_NEXT_dTD_POINTER_wr : IN std_logic_vector(26 downto 0);
dQH_T_wr : IN std_logic;
dQH_SETUP_BUFFER_BYTES_3_0_wr : IN std_logic_vector(31 downto 0);
dQH_SETUP_BUFFER_BYTES_7_4_wr : IN std_logic_vector(31 downto 0);
dTD_TOTAL_BYTES_wr : IN std_logic_vector(14 downto 0);
dTD_IOC_wr : IN std_logic;
dTD_C_PAGE_wr : IN std_logic_vector(2 downto 0);
dTD_MULT_wr : IN std_logic_vector(1 downto 0);
dTD_STATUS_wr : IN std_logic_vector(7 downto 0);
dTD_PAGE0_wr : IN std_logic_vector(19 downto 0);
dTD_PAGE1_wr : IN std_logic_vector(19 downto 0);
dTD_PAGE2_wr : IN std_logic_vector(19 downto 0);
dTD_PAGE3_wr : IN std_logic_vector(19 downto 0);
dTD_PAGE4_wr : IN std_logic_vector(19 downto 0);
dTD_CURRENT_OFFSET_wr : IN std_logic_vector(11 downto 0);
dQH_MULT_rd : OUT std_logic_vector(1 downto 0);
dQH_ZLT_rd : OUT std_logic;
-- pe_dQH_ZLT_rd : OUT STD_LOGIC;
dQH_MAX_PACKET_LENGTH_rd : OUT std_logic_vector(10 downto 0);
dQH_IOS_rd : OUT std_logic;
dQH_CURRENT_dTD_POINTER_rd : OUT std_logic_vector(26 downto 0);
dQH_NEXT_dTD_POINTER_rd : OUT std_logic_vector(26 downto 0);
dQH_T_rd : OUT std_logic;
dQH_SETUP_BUFFER_BYTES_3_0_rd : OUT std_logic_vector(31 downto 0);
dQH_SETUP_BUFFER_BYTES_7_4_rd : OUT std_logic_vector(31 downto 0);
dTD_TOTAL_BYTES_rd : OUT std_logic_vector(14 downto 0);
dTD_IOC_rd : OUT std_logic;
dTD_C_PAGE_rd : OUT std_logic_vector(2 downto 0);
dTD_MULT_rd : OUT std_logic_vector(1 downto 0);
dTD_STATUS_rd : OUT std_logic_vector(7 downto 0);
dTD_PAGE0_rd : OUT std_logic_vector(19 downto 0);
dTD_PAGE1_rd : OUT std_logic_vector(19 downto 0);
dTD_PAGE2_rd : OUT std_logic_vector(19 downto 0);
dTD_PAGE3_rd : OUT std_logic_vector(19 downto 0);
dTD_PAGE4_rd : OUT std_logic_vector(19 downto 0);
dTD_CURRENT_OFFSET_rd : OUT std_logic_vector(11 downto 0)
);
END COMPONENT;
COMPONENT Context_to_Stream
PORT(
CLK : IN std_logic;
RESETN : IN std_logic;
ind_statte_axistream : out std_logic_vector(4 downto 0);
dQH_RD : IN std_logic;
dQH_WR : IN std_logic;
dTD_RD : IN std_logic;
dTD_WR : IN std_logic;
SETUP_WR : IN STD_LOGIC;
dQH_WR_EN : out STD_LOGIC;
s_axis_mm2s_tdata : IN std_logic_vector(31 downto 0);
s_axis_mm2s_tkeep : IN std_logic_vector(3 downto 0);
s_axis_mm2s_tvalid : IN std_logic;
s_axis_mm2s_tlast : IN std_logic;
m_axis_s2mm_tready : IN std_logic;
dQH_MULT_rd : IN std_logic_vector(1 downto 0);
dQH_ZLT_rd : IN std_logic;
dQH_MAX_PACKET_LENGTH_rd : IN std_logic_vector(10 downto 0);
dQH_IOS_rd : IN std_logic;
dQH_CURRENT_dTD_POINTER_rd : IN std_logic_vector(26 downto 0);
dQH_NEXT_dTD_POINTER_rd : IN std_logic_vector(26 downto 0);
dQH_T_rd : IN std_logic;
dQH_SETUP_BUFFER_BYTES_3_0_rd : IN std_logic_vector(31 downto 0);
dQH_SETUP_BUFFER_BYTES_7_4_rd : IN std_logic_vector(31 downto 0);
dTD_TOTAL_BYTES_rd : IN std_logic_vector(14 downto 0);
dTD_IOC_rd : IN std_logic;
dTD_C_PAGE_rd : IN std_logic_vector(2 downto 0);
dTD_MULT_rd : IN std_logic_vector(1 downto 0);
dTD_STATUS_rd : IN std_logic_vector(7 downto 0);
dTD_PAGE0_rd : IN std_logic_vector(19 downto 0);
dTD_PAGE1_rd : IN std_logic_vector(19 downto 0);
dTD_PAGE2_rd : IN std_logic_vector(19 downto 0);
dTD_PAGE3_rd : IN std_logic_vector(19 downto 0);
dTD_PAGE4_rd : IN std_logic_vector(19 downto 0);
dTD_CURRENT_OFFSET_rd : IN std_logic_vector(11 downto 0);
s_axis_mm2s_tready : OUT std_logic;
m_axis_s2mm_tdata : OUT std_logic_vector(31 downto 0);
m_axis_s2mm_tkeep : OUT std_logic_vector(3 downto 0);
m_axis_s2mm_tvalid : OUT std_logic;
m_axis_s2mm_tlast : OUT std_logic;
dQH_MULT_wr : OUT std_logic_vector(1 downto 0);
dQH_ZLT_wr : OUT std_logic;
dQH_MAX_PACKET_LENGTH_wr : OUT std_logic_vector(10 downto 0);
dQH_IOS_wr : OUT std_logic;
dQH_CURRENT_dTD_POINTER_wr : OUT std_logic_vector(26 downto 0);
dQH_NEXT_dTD_POINTER_wr : OUT std_logic_vector(26 downto 0);
dQH_T_wr : OUT std_logic;
dQH_SETUP_BUFFER_BYTES_3_0_wr : OUT std_logic_vector(31 downto 0);
dQH_SETUP_BUFFER_BYTES_7_4_wr : OUT std_logic_vector(31 downto 0);
dTD_TOTAL_BYTES_wr : OUT std_logic_vector(14 downto 0);
dTD_IOC_wr : OUT std_logic;
dTD_C_PAGE_wr : OUT std_logic_vector(2 downto 0);
dTD_MULT_wr : OUT std_logic_vector(1 downto 0);
dTD_STATUS_wr : OUT std_logic_vector(7 downto 0);
dTD_PAGE0_wr : OUT std_logic_vector(19 downto 0);
dTD_PAGE1_wr : OUT std_logic_vector(19 downto 0);
dTD_PAGE2_wr : OUT std_logic_vector(19 downto 0);
dTD_PAGE3_wr : OUT std_logic_vector(19 downto 0);
dTD_PAGE4_wr : OUT std_logic_vector(19 downto 0);
dTD_CURRENT_OFFSET_wr : OUT std_logic_vector(11 downto 0)
);
END COMPONENT;
constant ATDTW : integer := 14;
constant SUTW : integer := 13;
constant SLOM : integer := 3;
type state_type is (IDLE, PRIME_MM2S_DQH, PRIME_WAIT0, PRIME_MM2S_DTD, PRIME_WAIT1, PRIME_WAIT2, PRIME_FILL_FIFO, PRIME_FILL_FIFO_1, IN_HANDSHAKE, PRIME_FILL_FIFO_2, SETUP_LOCKOUT_TRIPWIRE, SETUP_UPDATE_SETUP_BYTES, SETUP_WAIT1, SETUP_S2MM, SETUP_UPDATE_ENDPTSETUP_RECEIVED, SETUP_WAIT2, START_OUT_FRAMEWORK, OUT_START_TRANSFER, OUT_TRANSFER_S2MM, OUT_WAIT1, OUT_CHECK_COMPLETE, OUT_TRANSFER_COMPLETE, OUT_FETCH_NEXT_DTD, OUT_WAIT2,START_IN_FRAMEWORK, IN_TRANSFER_MM2S, IN_RELOAD_BUFFER, IN_WAIT0, IN_WAIT1, IN_CHECK_COMPLETE, IN_TRANSACTION_COMPLETE, IN_FETCH_NEXT_DTD, IN_WAIT2);
signal state, next_state : state_type;
type DMA_CURRENT_TRANSFER_ADDRESS is array (11 downto 0) of std_logic_vector(31 downto 0);
signal a_DMA_Current_Transfer_Addr_Array, a_DMA_Current_Transfer_Addr_Array_q : DMA_CURRENT_TRANSFER_ADDRESS;
signal a_Context_Mux_Ctrl : std_logic;
signal a_Read_dQH : std_logic;
signal a_Read_dQH_Fsm : std_logic;
signal a_Read_dQH_q : std_logic;
signal a_Write_dQH : std_logic;
signal a_Write_dQH_Fsm : std_logic;
signal a_Write_dQH_q : std_logic;
signal a_Read_dTD : std_logic;
signal a_Read_dTD_Fsm : std_logic;
signal a_Read_dTD_q : std_logic;
signal write_dTD : std_logic;
signal a_Write_Setup_Bytes, a_Write_Setup_Bytes_q, a_Write_Setup_Bytes_FSM : std_logic;
signal a_dQH_Wr_En_Mux_Stream : std_logic;
signal a_dQH_Wr_En_Mux_Out : std_logic;
signal a_dQH_Wr_En_Mux_Arb : std_logic;
signal a_Start_DMA_S2MM : std_logic;
signal a_Start_DMA_MM2S : std_logic;
signal a_DMA_Source_Dest_Addr : std_logic_vector(31 downto 0);
signal a_DMA_Transfer_Length : std_logic_vector(31 downto 0);
signal a_DMA_Current_Transfer_Addr_Fsm : std_logic_vector (31 downto 0);
signal a_DMA_Current_Transfer_Addr_Le : std_logic;
signal a_DMA_Transfer_Complete : STD_LOGIC;
signal a_Aux_Addr_Register : std_logic_vector (31 downto 0);
signal a_DMA_In_Transfer_Length : std_logic_vector (31 downto 0);
signal a_DMA_In_Transfer_Length_Le : std_logic;
signal a_Axis_MM2S_Mux_Ctrl_Fsm , a_Axis_S2MM_Mux_Ctrl_Fsm : STD_LOGIC;
signal a_Arb_dQH_MULT_Wr : STD_LOGIC_VECTOR (1 downto 0); --not used
signal a_Arb_dQH_ZLT_Wr : STD_LOGIC; --not used
signal a_Arb_dQH_Max_Packet_Length_Wr : STD_LOGIC_VECTOR (10 downto 0); --not used
signal a_Arb_dQH_IOS_Wr : STD_LOGIC; --not used
signal a_Arb_dQH_Current_dTD_Pointer_Wr : STD_LOGIC_VECTOR (26 downto 0);
signal a_Arb_dQH_Current_dTD_Pointer_Wr_En : STD_LOGIC;
signal a_Arb_dQH_Next_dTD_Pointer_Wr : STD_LOGIC_VECTOR (26 downto 0); --not used
signal a_Arb_dQH_Next_dTD_Pointer_Wr_En : STD_LOGIC; --not used
signal a_Arb_dQH_T_Wr : STD_LOGIC; --not used
signal a_Arb_dTD_Total_Bytes_Wr : STD_LOGIC_VECTOR (14 downto 0);
signal a_Arb_dTD_Total_Bytes_Wr_En : STD_LOGIC;
signal a_Arb_dTD_IOC_Wr : STD_LOGIC; --not used
signal a_Arb_dTD_C_Page_Wr : STD_LOGIC_VECTOR (2 downto 0); --not used
signal a_Arb_dTD_Mult_Wr : STD_LOGIC_VECTOR (1 downto 0); --not used
signal a_Arb_dTD_Status_Wr : STD_LOGIC_VECTOR (7 downto 0); --not used
signal a_Arb_dTD_Page0_Wr : STD_LOGIC_VECTOR (19 downto 0); --not used
signal a_Arb_dTD_Page1_Wr : STD_LOGIC_VECTOR (19 downto 0); --not used
signal a_Arb_dTD_Page2_Wr : STD_LOGIC_VECTOR (19 downto 0); --not used
signal a_Arb_dTD_Page3_Wr : STD_LOGIC_VECTOR (19 downto 0); --not used
signal a_Arb_dTD_Page4_wr : STD_LOGIC_VECTOR (19 downto 0); --not used
signal a_Arb_dTD_Current_Offset_Wr : STD_LOGIC_VECTOR (11 downto 0); --not used
signal a_Stream_dQH_Mult_Wr : STD_LOGIC_VECTOR (1 downto 0);
signal a_Stream_dQH_Zlt_Wr : STD_LOGIC;
signal a_Stream_dQH_Max_Packet_Length_Wr : STD_LOGIC_VECTOR (10 downto 0);
signal a_Stream_dQH_IOS_Wr : STD_LOGIC;
signal a_Stream_dQH_Current_dTD_Pointer_Wr : STD_LOGIC_VECTOR (26 downto 0);
signal a_Stream_dQH_Next_dTD_Pointer_wr : STD_LOGIC_VECTOR (26 downto 0);
signal a_Stream_dQH_T_Wr : STD_LOGIC;
signal a_Stream_dQH_Setup_Buffer_Bytes_3_0_Wr : STD_LOGIC_VECTOR (31 downto 0);
signal a_Stream_dQH_Setup_Buffer_Bytes_7_4_Wr : STD_LOGIC_VECTOR (31 downto 0);
signal a_Stream_dTD_Total_Bytes_Wr : STD_LOGIC_VECTOR (14 downto 0);
signal a_Stream_dTD_IOC_Wr : STD_LOGIC;
signal a_Stream_dTD_C_Page_Wr : STD_LOGIC_VECTOR (2 downto 0);
signal a_Stream_dTD_Mult_Wr : STD_LOGIC_VECTOR (1 downto 0);
signal a_Stream_dTD_Status_Wr : STD_LOGIC_VECTOR (7 downto 0);
signal a_Stream_dTD_Page0_Wr : STD_LOGIC_VECTOR (19 downto 0);
signal a_Stream_dTD_Page1_Wr : STD_LOGIC_VECTOR (19 downto 0);
signal a_Stream_dTD_Page2_Wr : STD_LOGIC_VECTOR (19 downto 0);
signal a_Stream_dTD_Page3_Wr : STD_LOGIC_VECTOR (19 downto 0);
signal a_Stream_dTD_Page4_Wr : STD_LOGIC_VECTOR (19 downto 0);
signal a_Stream_dTD_Current_Offset_Wr : STD_LOGIC_VECTOR (11 downto 0);
signal a_dQH_Mult_Wr : STD_LOGIC_VECTOR (1 downto 0);
signal a_dQH_ZLT_Wr : STD_LOGIC;
signal a_dQH_Max_Packet_Length_Wr : STD_LOGIC_VECTOR (10 downto 0);
signal a_dQH_IOS_Wr : STD_LOGIC;
signal a_dQH_Current_dTD_Pointer_Wr : STD_LOGIC_VECTOR (26 downto 0);
signal a_dQH_Next_dTD_Pointer_Wr : STD_LOGIC_VECTOR (26 downto 0);
signal a_dQH_T_Wr : STD_LOGIC;
signal a_dQH_Setup_Buffer_Bytes_3_0_Wr : STD_LOGIC_VECTOR (31 downto 0);
signal a_dQH_Setup_Buffer_Bytes_7_4_Wr : STD_LOGIC_VECTOR (31 downto 0);
signal a_dTD_Total_Bytes_Wr : STD_LOGIC_VECTOR (14 downto 0);
signal a_dTD_IOC_Wr : STD_LOGIC;
signal a_dTD_C_Page_Wr : STD_LOGIC_VECTOR (2 downto 0);
signal a_dTD_Mult_Wr : STD_LOGIC_VECTOR (1 downto 0);
signal a_dTD_Status_Wr : STD_LOGIC_VECTOR (7 downto 0);
signal a_dTD_Page0_Wr : STD_LOGIC_VECTOR (19 downto 0);
signal a_dTD_Page1_Wr : STD_LOGIC_VECTOR (19 downto 0);
signal a_dTD_Page2_Wr : STD_LOGIC_VECTOR (19 downto 0);
signal a_dTD_Page3_Wr : STD_LOGIC_VECTOR (19 downto 0);
signal a_dTD_Page4_Wr : STD_LOGIC_VECTOR (19 downto 0);
signal a_dTD_Current_Offset_Wr : STD_LOGIC_VECTOR (11 downto 0);
signal a_dQH_Setup_Buffer_Wr_En : std_logic;
signal a_dTD_Status_Wr_En : STD_LOGIC;
signal a_dQH_MULT_Rd : STD_LOGIC_VECTOR (1 downto 0);
signal a_dQH_ZLT_Rd : STD_LOGIC;
signal a_dQH_Max_Packet_Length_Rd : STD_LOGIC_VECTOR (10 downto 0);
signal a_dQH_IOS_Rd : STD_LOGIC;
signal a_dQH_Current_dTD_Pointer_Rd : STD_LOGIC_VECTOR (26 downto 0);
signal a_dQH_Next_dTD_Pointer_Rd : STD_LOGIC_VECTOR (26 downto 0);
signal a_dQH_T_Rd : STD_LOGIC;
signal a_dQH_Setup_Buffer_Bytes_3_0_Rd : STD_LOGIC_VECTOR (31 downto 0);
signal a_dQH_Setup_Buffer_Bytes_7_4_Rd : STD_LOGIC_VECTOR (31 downto 0);
signal a_dTD_Total_Bytes_Rd : STD_LOGIC_VECTOR (14 downto 0);
signal a_dTD_IOC_Rd : STD_LOGIC;
signal a_dTD_C_Page_Rd : STD_LOGIC_VECTOR (2 downto 0);
signal a_dTD_Mult_Rd : STD_LOGIC_VECTOR (1 downto 0);
signal a_dTD_Status_Rd : STD_LOGIC_VECTOR (7 downto 0);
signal a_dTD_Page0_Rd : STD_LOGIC_VECTOR (19 downto 0);
signal a_dTD_Page1_Rd : STD_LOGIC_VECTOR (19 downto 0);
signal a_dTD_Page2_Rd : STD_LOGIC_VECTOR (19 downto 0);
signal a_dTD_Page3_Rd : STD_LOGIC_VECTOR (19 downto 0);
signal a_dTD_Page4_Rd : STD_LOGIC_VECTOR (19 downto 0);
signal a_dTD_Current_Offset_Rd : STD_LOGIC_VECTOR (11 downto 0);
signal a_Out_Transfer_Byte_Count_Le1 : STD_LOGIC;
signal a_Out_Transfer_Byte_Count_Le2 : STD_LOGIC;
signal a_Out_Transfer_Byte_Count : std_logic_vector (12 downto 0);
signal a_Endpointlistaddr_Loc : std_logic_vector(20 downto 0);
signal a_ENDPTSETUPSTAT_Wr_En_Fsm : std_logic;
signal a_ENDPTSETUPSTAT_Wr_Fsm : std_logic_vector(31 downto 0);
signal a_USBSTS_Wr_UI_Fsm : std_logic;
signal a_USBSTS_Wr_En_UI_Fsm : std_logic;
signal a_ENDPTSTAT_Set : std_logic_vector(31 downto 0);
signal a_ENDPTSTAT_Set_En : std_logic;
signal a_ENDPTSTAT_clear : std_logic_vector(31 downto 0);
signal a_ENDPTSTAT_Clear_En : std_logic;
signal a_ENDPTSTAT_Wr_Loc : std_logic_vector(31 downto 0);
signal tx_fifo_resetn : std_logic;
signal a_Prime : STD_LOGIC;
signal a_Setup_Received : STD_LOGIC;
signal a_In_Token_Received : STD_LOGIC;
signal a_Endpt_Nr_Int : integer range 0 to 23;
signal a_Endpt_Nr_Fsm : integer range 0 to 23;
signal a_Endpt_Nr_Le : STD_LOGIC;
signal a_Endpt_Nr : std_logic_vector(4 downto 0);
signal a_Endpt_Nr_4b : integer range 0 to 27;
signal a_Endpt_Nr_Prime : integer range 0 to 23;
signal a_Endpt_Nr_Setup : integer range 0 to 23;
signal a_Endpt_Nr_In_Token : integer range 0 to 23;
signal a_Endpt_In_Out : STD_LOGIC;
signal a_Bit_Index : integer range 0 to 27;
signal a_Cnt_Bytes_Sent_Loc : std_logic_vector (12 downto 0);
-- attribute mark_debug : string;
-- attribute keep : string;
-- attribute mark_debug of state_ind_arb : signal is "true";
-- attribute keep of state_ind_arb : signal is "true";
-- attribute mark_debug of a_ENDPTCOMPLETE_Wr_En : signal is "true";
-- attribute keep of a_ENDPTCOMPLETE_Wr_En : signal is "true";
-- attribute mark_debug of a_ENDPTCOMPLETE_Wr : signal is "true";
-- attribute keep of a_ENDPTCOMPLETE_Wr : signal is "true";
-- attribute mark_debug of a_Setup_Received : signal is "true";
-- attribute keep of a_Setup_Received : signal is "true";
-- attribute mark_debug of a_Cnt_Bytes_Sent_Loc : signal is "true";
-- attribute keep of a_Cnt_Bytes_Sent_Loc : signal is "true";
-- attribute mark_debug of a_In_Packet_Complete_Rd : signal is "true";
-- attribute keep of a_In_Packet_Complete_Rd : signal is "true";
-- attribute mark_debug of a_In_Token_Received : signal is "true";
-- attribute keep of a_In_Token_Received : signal is "true";
-- attribute mark_debug of a_Arb_ENDPTSETUP_RECEIVED_Rd : signal is "true";
-- attribute keep of a_Arb_ENDPTSETUP_RECEIVED_Rd : signal is "true";
-- attribute mark_debug of a_Bit_Index : signal is "true";
-- attribute keep of a_Bit_Index : signal is "true";
-- attribute mark_debug of a_Endpt_Nr_Prime : signal is "true";
-- attribute keep of a_Endpt_Nr_Prime : signal is "true";
-- attribute mark_debug of a_Endpt_Nr : signal is "true";
-- attribute keep of a_Endpt_Nr : signal is "true";
-- attribute mark_debug of a_Endpt_In_Out : signal is "true";
-- attribute keep of a_Endpt_In_Out : signal is "true";
-- attribute mark_debug of a_In_Token_Received_Rd : signal is "true";
-- attribute keep of a_In_Token_Received_Rd : signal is "true";
-- attribute mark_debug of a_dTD_Total_Bytes_Rd : signal is "true";
-- attribute keep of a_dTD_Total_Bytes_Rd : signal is "true";
-- attribute mark_debug of a_Prime : signal is "true";
-- attribute keep of a_Prime : signal is "true";
-- attribute mark_debug of a_ENDPTSTAT_Wr_Loc : signal is "true";
-- attribute keep of a_ENDPTSTAT_Wr_Loc : signal is "true";
-- attribute mark_debug of a_ENDPTSTAT_Set_En : signal is "true";
-- attribute keep of a_ENDPTSTAT_Set_En : signal is "true";
-- attribute mark_debug of a_ENDPTSTAT_Set : signal is "true";
-- attribute keep of a_ENDPTSTAT_Set : signal is "true";
-- attribute mark_debug of a_EMDPTFLUSH_Rd : signal is "true";
-- attribute keep of a_EMDPTFLUSH_Rd : signal is "true";
-- attribute mark_debug of a_Endpt_Nr_Int : signal is "true";
-- attribute keep of a_Endpt_Nr_Int : signal is "true";
begin
a_Aux_Addr_Register <= a_dTD_Page0_Rd & a_dTD_Current_Offset_Rd;
arb_tx_fifo_s_aresetn <= tx_fifo_resetn;
a_Axis_MM2S_Mux_Ctrl <= a_Axis_MM2S_Mux_Ctrl_Fsm;
a_Axis_S2MM_Mux_Ctrl <= a_Axis_S2MM_Mux_Ctrl_Fsm;
a_Endpointlistaddr_Loc <= a_ENDPOINTLISTADDR_Rd(31 downto 11);
-- This module is responsible with implementing the S2MM and MM2S frameworks for the DMA engine
Inst_DMA_Operations: DMA_Operations PORT MAP(
CLK => Axi_Clk,
RESETN => Axi_Resetn,
state_ind_dma => state_ind_dma,
DEBUG_REG_DATA => DEBUG_REG_DATA,
M_AXI_AWADDR => a_M_Axi_Awaddr,
M_AXI_AWPROT => a_M_Axi_Awprot,
M_AXI_AWVALID => a_M_Axi_Awvalid,
M_AXI_AWREADY => a_M_Axi_Awready,
M_AXI_WDATA => a_M_Axi_Wdata,
M_AXI_WSTRB => a_M_Axi_Wstrb,
M_AXI_WVALID => a_M_Axi_Wvalid,
M_AXI_WREADY => a_M_Axi_Wready,
M_AXI_BRESP => a_M_Axi_Bresp,
M_AXI_BVALID => a_M_Axi_Bvalid,
M_AXI_BREADY => a_M_Axi_Bready,
M_AXI_ARADDR => a_M_Axi_Araddr,
M_AXI_ARPROT => a_M_Axi_Arprot,
M_AXI_ARVALID => a_M_Axi_Arvalid,
M_AXI_ARREADY => a_M_Axi_Arready,
M_AXI_RDATA => a_M_Axi_Rdata,
M_AXI_RRESP => a_M_Axi_Rresp,
M_AXI_RVALID => a_M_Axi_Rvalid,
M_AXI_RREADY => a_M_Axi_Rready,
dma_transfer_complete => a_DMA_Transfer_Complete,
start_dma_s2mm => a_Start_DMA_S2MM,
start_dma_mm2s => a_Start_DMA_MM2S,
dma_source_dest_address => a_DMA_Source_Dest_Addr,
dma_transfer_length => a_DMA_Transfer_Length
);
-- This module implements the context memory (Queue Heads, Transfer Descriptors)
Inst_Context: Context PORT MAP(
CLK => Axi_Clk,
RESETN => Axi_Resetn,
ENDPT_NR => a_Endpt_Nr_Int,
RD_EN => '0',
WR_EN => a_dQH_Wr_En_Mux_Out,
dQH_CURRENT_dTD_POINTER_wr_EN => a_Arb_dQH_Current_dTD_Pointer_Wr_En,
dQH_NEXT_dTD_POINTER_wr_en => a_Arb_dQH_Next_dTD_Pointer_Wr_En,
dTD_TOTAL_BYTES_WR_EN => a_Arb_dTD_Total_Bytes_Wr_En,
dTD_STATUS_WR_EN => a_dTD_Status_Wr_En,
dQH_SETUP_BUFFER_wr_EN => a_dQH_Setup_Buffer_Wr_En,
dQH_MULT_rd => a_dQH_MULT_Rd,
dQH_ZLT_rd => a_dQH_ZLT_Rd,
dQH_MAX_PACKET_LENGTH_rd => a_dQH_Max_Packet_Length_Rd,
dQH_IOS_rd => a_dQH_IOS_Rd,
dQH_CURRENT_dTD_POINTER_rd => a_dQH_Current_dTD_Pointer_Rd,
dQH_NEXT_dTD_POINTER_rd => a_dQH_Next_dTD_Pointer_Rd,
dQH_T_rd => a_dQH_T_Rd,
dQH_SETUP_BUFFER_BYTES_3_0_rd => a_dQH_Setup_Buffer_Bytes_3_0_Rd,
dQH_SETUP_BUFFER_BYTES_7_4_rd => a_dQH_Setup_Buffer_Bytes_7_4_Rd,
dTD_TOTAL_BYTES_rd => a_dTD_Total_Bytes_Rd,
dTD_IOC_rd => a_dTD_IOC_Rd,
dTD_C_PAGE_rd => a_dTD_C_Page_Rd,
dTD_MULT_rd => a_dTD_Mult_Rd,
dTD_STATUS_rd => a_dTD_Status_Rd,
dTD_PAGE0_rd => a_dTD_Page0_Rd ,
dTD_PAGE1_rd => a_dTD_Page1_Rd,
dTD_PAGE2_rd => a_dTD_Page2_Rd,
dTD_PAGE3_rd => a_dTD_Page3_Rd,
dTD_PAGE4_rd => a_dTD_Page4_Rd,
dTD_CURRENT_OFFSET_rd => a_dTD_Current_Offset_Rd,
dQH_MULT_wr => a_dQH_Mult_Wr,
dQH_ZLT_wr => a_dQH_ZLT_Wr,
dQH_MAX_PACKET_LENGTH_wr => a_dQH_Max_Packet_Length_Wr,
dQH_IOS_wr => a_dQH_IOS_Wr,
dQH_CURRENT_dTD_POINTER_wr => a_dQH_Current_dTD_Pointer_Wr,
dQH_NEXT_dTD_POINTER_wr => a_dQH_Next_dTD_Pointer_Wr,
dQH_T_wr => a_dQH_T_Wr,
dQH_SETUP_BUFFER_BYTES_3_0_wr => a_dQH_Setup_Buffer_Bytes_3_0_Wr,
dQH_SETUP_BUFFER_BYTES_7_4_wr => a_dQH_Setup_Buffer_Bytes_7_4_Wr,
dTD_TOTAL_BYTES_wr => a_dTD_Total_Bytes_Wr,
dTD_IOC_wr => a_dTD_IOC_Wr,
dTD_C_PAGE_wr => a_dTD_C_Page_Wr,
dTD_MULT_wr => a_dTD_Mult_Wr,
dTD_STATUS_wr => a_dTD_Status_Wr,
dTD_PAGE0_wr => a_dTD_Page0_Wr,
dTD_PAGE1_wr => a_dTD_Page1_Wr,
dTD_PAGE2_wr => a_dTD_Page2_Wr,
dTD_PAGE3_wr => a_dTD_Page3_Wr,
dTD_PAGE4_wr => a_dTD_Page4_Wr,
dTD_CURRENT_OFFSET_wr => a_dTD_Current_Offset_Wr
);
-- This module handles control data transfers (Setup packets, dTD, dQH, Status) through the DMA module
Inst_Context_to_Stream: Context_to_Stream PORT MAP(
CLK => Axi_Clk,
RESETN => Axi_Resetn,
ind_statte_axistream => ind_statte_axistream,
dQH_RD => a_Read_dQH,
dQH_WR => a_Write_dQH,
dTD_RD => a_Read_dTD,
dTD_WR => write_dTD,
SETUP_WR => a_Write_Setup_Bytes,
dQH_WR_EN => a_dQH_Wr_En_Mux_Stream,
s_axis_mm2s_tdata => a_S_Axis_MM2S_Tdata,
s_axis_mm2s_tkeep => a_S_Axis_MM2S_Tkeep,
s_axis_mm2s_tvalid => a_S_Axis_MM2S_Tvalid,
s_axis_mm2s_tready => a_S_Axis_MM2S_Tready,
s_axis_mm2s_tlast => a_S_Axis_MM2S_Tlast,
m_axis_s2mm_tdata => a_M_Axis_S2MM_Tdata,
m_axis_s2mm_tkeep => a_M_Axis_S2MM_Tkeep,
m_axis_s2mm_tvalid => a_M_Axis_S2MM_Tvalid,
m_axis_s2mm_tready => a_M_Axis_S2MM_Tready,
m_axis_s2mm_tlast => a_M_Axis_S2MM_Tlast,
dQH_MULT_rd => a_dQH_MULT_Rd,
dQH_ZLT_rd => a_dQH_ZLT_Rd,
dQH_MAX_PACKET_LENGTH_rd => a_dQH_Max_Packet_Length_Rd,
dQH_IOS_rd => a_dQH_IOS_Rd,
dQH_CURRENT_dTD_POINTER_rd => a_dQH_Current_dTD_Pointer_Rd,
dQH_NEXT_dTD_POINTER_rd => a_dQH_Next_dTD_Pointer_Rd,
dQH_T_rd => a_dQH_T_Rd,
dQH_SETUP_BUFFER_BYTES_3_0_rd => a_dQH_Setup_Buffer_Bytes_3_0_Rd,
dQH_SETUP_BUFFER_BYTES_7_4_rd => a_dQH_Setup_Buffer_Bytes_7_4_Rd,
dTD_TOTAL_BYTES_rd => a_dTD_Total_Bytes_Rd,
dTD_IOC_rd => a_dTD_IOC_Rd,
dTD_C_PAGE_rd => a_dTD_C_Page_Rd,
dTD_MULT_rd => a_dTD_Mult_Rd,
dTD_STATUS_rd => a_dTD_Status_Rd,
dTD_PAGE0_rd => a_dTD_Page0_Rd,
dTD_PAGE1_rd => a_dTD_Page1_Rd,
dTD_PAGE2_rd => a_dTD_Page2_Rd,
dTD_PAGE3_rd => a_dTD_Page3_Rd,
dTD_PAGE4_rd => a_dTD_Page4_Rd,
dTD_CURRENT_OFFSET_rd => a_dTD_Current_Offset_Rd,
dQH_MULT_wr => a_Stream_dQH_Mult_Wr,
dQH_ZLT_wr => a_Stream_dQH_Zlt_Wr,
dQH_MAX_PACKET_LENGTH_wr => a_Stream_dQH_Max_Packet_Length_Wr,
dQH_IOS_wr => a_Stream_dQH_IOS_Wr,
dQH_CURRENT_dTD_POINTER_wr => a_Stream_dQH_Current_dTD_Pointer_Wr,
dQH_NEXT_dTD_POINTER_wr => a_Stream_dQH_Next_dTD_Pointer_wr,
dQH_T_wr => a_Stream_dQH_T_Wr,
dQH_SETUP_BUFFER_BYTES_3_0_wr => a_Stream_dQH_Setup_Buffer_Bytes_3_0_Wr,
dQH_SETUP_BUFFER_BYTES_7_4_wr => a_Stream_dQH_Setup_Buffer_Bytes_7_4_Wr,
dTD_TOTAL_BYTES_wr => a_Stream_dTD_Total_Bytes_Wr,
dTD_IOC_wr => a_Stream_dTD_IOC_Wr,
dTD_C_PAGE_wr => a_Stream_dTD_C_Page_Wr,
dTD_MULT_wr => a_Stream_dTD_Mult_Wr,
dTD_STATUS_wr => a_Stream_dTD_Status_Wr,
dTD_PAGE0_wr => a_Stream_dTD_Page0_Wr,
dTD_PAGE1_wr => a_Stream_dTD_Page1_Wr,
dTD_PAGE2_wr => a_Stream_dTD_Page2_Wr,
dTD_PAGE3_wr => a_Stream_dTD_Page3_Wr,
dTD_PAGE4_wr => a_Stream_dTD_Page4_Wr,
dTD_CURRENT_OFFSET_wr => a_Stream_dTD_Current_Offset_Wr
);
--Both DMA Engine and the DMA_Transfer_MAnager can read/write to the context memory. The MUX is implemented below
--DMA_Transfer_MAnager controls this MUX
a_dQH_Mult_Wr <= a_Stream_dQH_Mult_Wr when (a_Context_Mux_Ctrl = '0') else
a_Arb_dQH_MULT_Wr ;
a_dQH_ZLT_Wr <= a_Stream_dQH_Zlt_Wr when (a_Context_Mux_Ctrl = '0') else
a_Arb_dQH_ZLT_Wr;
a_dQH_Max_Packet_Length_Wr <= a_Stream_dQH_Max_Packet_Length_Wr when (a_Context_Mux_Ctrl = '0') else
a_Arb_dQH_Max_Packet_Length_Wr;
a_dQH_IOS_Wr <= a_Stream_dQH_IOS_Wr when (a_Context_Mux_Ctrl = '0') else
a_Arb_dQH_IOS_Wr;
a_dQH_Current_dTD_Pointer_Wr <= a_Stream_dQH_Current_dTD_Pointer_Wr when (a_Context_Mux_Ctrl = '0') else
a_Arb_dQH_Current_dTD_Pointer_Wr;
a_dQH_Next_dTD_Pointer_Wr <= a_Stream_dQH_Next_dTD_Pointer_wr when (a_Context_Mux_Ctrl = '0') else
a_Arb_dQH_Next_dTD_Pointer_Wr;
a_dQH_T_Wr <= a_Stream_dQH_T_Wr when (a_Context_Mux_Ctrl = '0') else
a_Arb_dQH_T_Wr;
a_dQH_Setup_Buffer_Bytes_3_0_Wr <= a_Stream_dQH_Setup_Buffer_Bytes_3_0_Wr when (a_Context_Mux_Ctrl = '0') else
a_Arb_dQH_Setup_Buffer_Bytes_3_0_Wr;
a_dQH_Setup_Buffer_Bytes_7_4_Wr <= a_Stream_dQH_Setup_Buffer_Bytes_7_4_Wr when (a_Context_Mux_Ctrl = '0') else
a_Arb_dQH_Setup_Buffer_Bytes_7_4_Wr;
a_dTD_Total_Bytes_Wr <= a_Stream_dTD_Total_Bytes_Wr when (a_Context_Mux_Ctrl = '0') else
a_Arb_dTD_Total_Bytes_Wr;
a_dTD_IOC_Wr <= a_Stream_dTD_IOC_Wr when (a_Context_Mux_Ctrl = '0') else
a_Arb_dTD_IOC_Wr;
a_dTD_C_Page_Wr <= a_Stream_dTD_C_Page_Wr when (a_Context_Mux_Ctrl = '0') else
a_Arb_dTD_C_Page_Wr;
a_dTD_Mult_Wr <= a_Stream_dTD_Mult_Wr when (a_Context_Mux_Ctrl = '0') else
a_Arb_dTD_Mult_Wr;
a_dTD_Status_Wr <= a_Stream_dTD_Status_Wr when (a_Context_Mux_Ctrl = '0') else
a_Arb_dTD_Status_Wr;
a_dTD_Page0_Wr <= a_Stream_dTD_Page0_Wr when (a_Context_Mux_Ctrl = '0') else
a_Arb_dTD_Page0_Wr;
a_dTD_Page1_Wr <= a_Stream_dTD_Page1_Wr when (a_Context_Mux_Ctrl = '0') else
a_Arb_dTD_Page1_Wr;
a_dTD_Page2_Wr <= a_Stream_dTD_Page2_Wr when (a_Context_Mux_Ctrl = '0') else
a_Arb_dTD_Page2_Wr;
a_dTD_Page3_Wr <= a_Stream_dTD_Page3_Wr when (a_Context_Mux_Ctrl = '0') else
a_Arb_dTD_Page3_Wr;
a_dTD_Page4_Wr <= a_Stream_dTD_Page4_Wr when (a_Context_Mux_Ctrl = '0') else
a_Arb_dTD_Page4_wr;
a_dTD_Current_Offset_Wr <= a_Stream_dTD_Current_Offset_Wr when (a_Context_Mux_Ctrl = '0') else
a_Arb_dTD_Current_Offset_Wr;
a_dQH_Wr_En_Mux_Out <= a_dQH_Wr_En_Mux_Stream when (a_Context_Mux_Ctrl = '0') else
a_dQH_Wr_En_Mux_Arb;
--Generate control signals for Context_to_Stream module. Control signals
--must be pulses
IMPULSE_WRITE_DQH: process (Axi_Clk, a_Write_dQH_Fsm)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (Axi_Resetn = '0') then
a_Write_dQH <= '0';
a_Write_dQH_q <= '0';
else
a_Write_dQH_q <= a_Write_dQH_Fsm;
a_Write_dQH <= a_Write_dQH_Fsm and (not a_Write_dQH_q);
end if;
end if;
end process;
IMPULSE_WRITE_SETUP: process (Axi_Clk, a_Write_Setup_Bytes_FSM)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (Axi_Resetn = '0') then
a_Write_Setup_Bytes <= '0';
a_Write_Setup_Bytes_q <= '0';
else
a_Write_Setup_Bytes_q <= a_Write_Setup_Bytes_FSM;
a_Write_Setup_Bytes <= a_Write_Setup_Bytes_FSM and (not a_Write_Setup_Bytes_q);
end if;
end if;
end process;
IMPULSE_READ_DQH: process (Axi_Clk, a_Read_dQH_Fsm)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (Axi_Resetn = '0') then
a_Read_dQH <= '0';
a_Read_dQH_q <= '0';
else
a_Read_dQH_q <= a_Read_dQH_Fsm;
a_Read_dQH <= a_Read_dQH_Fsm and (not a_Read_dQH_q);
end if;
end if;
end process;
IMPULSE_READ_DTD_PROC: process (Axi_Clk, a_Read_dTD_Fsm)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (Axi_Resetn = '0') then
a_Read_dTD <= '0';
a_Read_dTD_q <= '0';
else
a_Read_dTD_q <= a_Read_dTD_Fsm;
a_Read_dTD <= a_Read_dTD_Fsm and (not a_Read_dTD_q);
end if;
end if;
end process;
--combinational signals generated by the state machine are registered
REGISTER_Q_PROC: process (Axi_Clk)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (Axi_Resetn = '0') then
a_ENDPTSETUPSTAT_Wr_En <= '0';
a_ENDPTSETUPSTAT_Wr <= (others => '0');
a_USBSTS_Wr_UI <= '0';
a_USBSTS_Wr_en_UI <= '0';
else
a_ENDPTSETUPSTAT_Wr_En <= a_ENDPTSETUPSTAT_Wr_En_Fsm;
a_ENDPTSETUPSTAT_Wr <= a_ENDPTSETUPSTAT_Wr_Fsm;
a_USBSTS_Wr_UI <= a_USBSTS_Wr_UI_Fsm;
a_USBSTS_Wr_en_UI <= a_USBSTS_Wr_En_UI_Fsm;
end if;
end if;
end process;
a_ENDPTSTAT_Wr <= a_ENDPTSTAT_Wr_Loc;
--generate the ENDPTSTAT register
ENDPTSTAT_PROC: process (Axi_Clk)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (Axi_Resetn = '0') then
a_ENDPTSTAT_Wr_Loc <= (others => '0');
elsif (a_ENDPTSTAT_Set_En = '1') then
a_ENDPTSTAT_Wr_Loc <= a_ENDPTSTAT_Wr_Loc or a_ENDPTSTAT_Set;
elsif (a_ENDPTSTAT_Clear_En = '1') then
a_ENDPTSTAT_Wr_Loc <= a_ENDPTSTAT_Wr_Loc and a_ENDPTSTAT_clear;
elsif (a_EMDPTFLUSH_Rd /= "00000000000000000000000000000000") then
a_ENDPTSTAT_Wr_Loc <= a_ENDPTSTAT_Wr_Loc and (not(a_EMDPTFLUSH_Rd));
end if;
end if;
end process;
a_Cnt_Bytes_Sent_Loc <= a_Cnt_Bytes_Sent;
-- a_Arb_Endpt_Nr is the endpoint the DMA_Transfer_Manager work on in integer format
ENDPT_NR_INT_PROC: process (Axi_Clk)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (Axi_Resetn = '0') then
a_Endpt_Nr_Int <= 0;
elsif (a_Endpt_Nr_Le = '1') then
a_Endpt_Nr_Int <= a_Endpt_Nr_Fsm;
end if;
end if;
end process;
a_Endpt_Nr <= std_logic_vector(to_unsigned(a_Endpt_Nr_Int,5));
-- a_Arb_Endpt_Nr is the endpoint the DMA_Transfer_Manager work on. Lower layers need to be aware of this
ARB_ENDPT_NR_PROC: process (Axi_Clk)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (Axi_Resetn = '0') then
a_Arb_Endpt_Nr <= (others => '0');
else
a_Arb_Endpt_Nr <= a_Endpt_Nr;
end if;
end if;
end process;
--determin the endpoint type
DET_ENDPTTYPE: process (Axi_Resetn, a_Endpt_Nr)
begin
if (a_Endpt_Nr(0) = '0') then
a_Endpt_In_Out <= '0';
else
a_Endpt_In_Out <= '1';
end if;
end process;
a_Endpt_Nr_4b <= to_integer(unsigned(a_Endpt_Nr(4 downto 1)));
-- Control registers usually have bits [27:16] referring to IN endpoints asnd bits[11:0] referring to OUT endpoint
DET_INDEX: process (Axi_Resetn, a_Endpt_Nr_4b, a_Endpt_In_Out)
begin
if (a_Endpt_In_Out = '0') then
a_Bit_Index <= a_Endpt_Nr_4b;
else
a_Bit_Index <= a_Endpt_Nr_4b + 16;
end if;
end process;
-- Determin the endpoint selected for priming from endptprime register
DET_PRIME_ENDPTNR_PROC: process (Axi_Clk, a_ENDPTPRIME_Rd)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (Axi_Resetn = '0') then
a_Endpt_Nr_Prime <= 0;
a_Prime <= '0';
elsif(a_ENDPTPRIME_Rd /= "00000000000000000000000000000000") then
a_Prime <= '1';
for endptprime_index in 0 to 27 loop
if (endptprime_index < 12) then
if (a_ENDPTPRIME_Rd(endptprime_index) = '1') then
a_Endpt_Nr_Prime <= endptprime_index * 2; --OUT endpoints (0, 2, 4, ... ,20)
end if;
elsif (endptprime_index >= 16) then
if (a_ENDPTPRIME_Rd(endptprime_index) = '1') then
a_Endpt_Nr_Prime <= (endptprime_index - 16) * 2 + 1; -- IN endpoints (1, 3, ..., 21)
end if;
end if;
end loop;
else
a_Endpt_Nr_Prime <= 0;
a_Prime <= '0';
end if;
end if;
end process;
--Determin the endpoint number from setup_received register
DET_SETUP_ENDPTNR_PROC: process (Axi_Clk)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (Axi_Resetn = '0') then
a_Endpt_Nr_Setup <= 0;
a_Setup_Received <= '0';
elsif(a_Arb_ENDPTSETUP_RECEIVED_Rd /= "00000000000000000000000000000000") then
a_Setup_Received <= '1';
for setup_index in 0 to 27 loop
if (setup_index < 12) then
if (a_Arb_ENDPTSETUP_RECEIVED_Rd(setup_index) = '1') then
a_Endpt_Nr_Setup <= setup_index * 2; --OUT endpoints (0, 2, 4, ... ,20)
end if;
elsif (setup_index >= 16) then
if (a_Arb_ENDPTSETUP_RECEIVED_Rd(setup_index) = '1') then
a_Endpt_Nr_Setup <= (setup_index - 16) * 2 + 1; -- IN endpoints (1, 3, ..., 21)
end if;
end if;
end loop;
else
a_Endpt_Nr_Setup <= 0;
a_Setup_Received <= '0';
end if;
end if;
end process;
--Determin the endpoint number from token_in_received register
DET_TOKEN_IN_ENDPTNR_PROC: process (Axi_Clk, a_In_Token_Received_Rd)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (Axi_Resetn = '0') then
a_Endpt_Nr_In_Token <= 0;
a_In_Token_Received <= '0';
elsif((a_In_Token_Received_Rd and a_ENDPTSTAT_Wr_Loc) /= "00000000000000000000000000000000") then
a_In_Token_Received <= '1';
for token_in_index in 0 to 27 loop
if (token_in_index < 12) then
if (a_In_Token_Received_Rd(token_in_index) = '1') then
a_Endpt_Nr_In_Token <= token_in_index * 2; --OUT endpoints (0, 2, 4, ... ,20)
end if;
elsif (token_in_index >= 16) then
if (a_In_Token_Received_Rd(token_in_index) = '1') then
a_Endpt_Nr_In_Token <= (token_in_index - 16) * 2 + 1; -- IN endpoints (1, 3, ..., 21)
end if;
end if;
end loop;
else
a_Endpt_Nr_In_Token <= 0;
a_In_Token_Received <= '0';
end if;
end if;
end process;
OUT_TRANSFER_BYTE_COUNT_PROC: process (Axi_Clk)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (Axi_Resetn = '0') then
a_Out_Transfer_Byte_Count <= (others => '0');
elsif (a_Out_Transfer_Byte_Count_Le1 = '1') then
a_Out_Transfer_Byte_Count <= RX_COMMAND_FIFO_DOUT(23 downto 11);
elsif (a_Out_Transfer_Byte_Count_Le2 = '1') then
a_Out_Transfer_Byte_Count <= std_logic_vector( to_unsigned((to_integer(unsigned(RX_COMMAND_FIFO_DOUT(23 downto 11))) - to_integer(unsigned(a_dTD_Total_Bytes_Rd))),13) );
end if;
end if;
end process;
DMA_TRANSFER_ADDR_PROC: process (Axi_Clk)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (Axi_Resetn = '0') then
a_DMA_Current_Transfer_Addr_Array <= (others =>(others => '0'));
a_DMA_Current_Transfer_Addr_Array_q <= (others =>(others => '0'));
elsif (a_DMA_Current_Transfer_Addr_Le = '1') then
a_DMA_Current_Transfer_Addr_Array(a_Endpt_Nr_4b) <= a_DMA_Current_Transfer_Addr_Fsm;
a_DMA_Current_Transfer_Addr_Array_q(a_Endpt_Nr_4b) <= a_DMA_Current_Transfer_Addr_Array(a_Endpt_Nr_4b);
end if;
end if;
end process;
------------------------------------------------------------------------------------------------------
DECIDE_LENGTH_PROC: process (Axi_Clk)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (Axi_Resetn = '0') then
a_DMA_In_Transfer_Length <= (others => '0');
else
if (a_DMA_In_Transfer_Length_Le = '1') then
if (to_integer(unsigned(a_dTD_Total_Bytes_Rd)) < C_FIFO_SIZE) then
a_DMA_In_Transfer_Length <= "00000000000000000" & a_dTD_Total_Bytes_Rd;
else
a_DMA_In_Transfer_Length <= std_logic_vector(to_unsigned(C_FIFO_SIZE,32));
end if;
end if;
end if;
end if;
end process;
--DMA_Transfer_Manager State Machine
SYNC_PROC: process (Axi_Clk)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (Axi_Resetn = '0') then
state <= IDLE;
else
state <= next_state;
end if;
end if;
end process;
NEXT_STATE_DECODE: process (state, a_dQH_Next_dTD_Pointer_Rd, a_Arb_ENDPTSETUP_RECEIVED_Ack, a_Cnt_Bytes_Sent_oValid, a_Send_Zero_Length_Packet_Ack_Rd, a_DMA_Current_Transfer_Addr_Array, a_Prime, RX_COMMAND_FIFO_VALID, a_dTD_Page0_Rd, a_dTD_Current_Offset_Rd,a_Endpt_Nr_4b, a_Endpt_Nr_Int, a_Aux_Addr_Register, a_In_Packet_Complete_Rd, a_Endpt_Nr_In_Token, RX_COMMAND_FIFO_EMPTY, a_Endpt_Nr_Setup, a_USBMODE_Rd, a_Bit_Index, RX_COMMAND_FIFO_DOUT, a_Out_Transfer_Byte_Count, a_Cnt_Bytes_Sent_Loc, a_dTD_Total_Bytes_Rd, a_dQH_Current_dTD_Pointer_Rd, a_dQH_T_Rd, a_Endpt_Nr_Prime, a_In_Token_Received, a_Endpt_In_Out, a_Setup_Received, a_DMA_Transfer_Complete, a_Endpointlistaddr_Loc)
begin
--declare default state for next_state to avoid latches
next_state <= state;
state_ind_arb <= "000000";
a_Context_Mux_Ctrl <= '0';
a_dQH_Wr_En_Mux_Arb <= '0';
a_Arb_dQH_Current_dTD_Pointer_Wr_En <= '0';
a_Arb_dTD_Total_Bytes_Wr_En <= '0';
a_Arb_dQH_Next_dTD_Pointer_Wr_En <= '0';
a_dQH_Setup_Buffer_Wr_En <= '0';
a_dTD_Status_Wr_En <= '0';
a_Read_dQH_Fsm <= '0';
a_Write_dQH_Fsm <= '0';
a_Read_dTD_Fsm <= '0';
write_dTD <= '0';
a_Write_Setup_Bytes_FSM <= '0';
a_Axis_MM2S_Mux_Ctrl_Fsm <= '1'; -- context memory connected to DMA stream port, not FIFO as a DEFAULT; FIFO connected to DMA only when data ready
a_Axis_S2MM_Mux_Ctrl_Fsm <= '1';
a_Start_DMA_S2MM <= '0';
a_Start_DMA_MM2S <= '0';
a_DMA_Source_Dest_Addr <= (others => '0');
a_DMA_Transfer_Length <= (others => '0');
tx_fifo_resetn <= '1';
a_Endpt_Nr_Fsm <= 0;
a_Endpt_Nr_Le <= '0';
RX_COMMAND_FIFO_RD_EN <= '0';
a_Out_Transfer_Byte_Count_Le1 <= '0';
a_Out_Transfer_Byte_Count_Le2 <= '0';
a_DMA_Current_Transfer_Addr_Fsm <= (others => '0');
a_DMA_Current_Transfer_Addr_Le <= '0';
-- pe_setup_received_rst <= '1';
a_Arb_dQH_MULT_Wr <= (others => '0');
a_Arb_dQH_ZLT_Wr <= '0';
a_Arb_dQH_Max_Packet_Length_Wr <= (others => '0');
a_Arb_dQH_IOS_Wr <= '0';
a_Arb_dQH_Current_dTD_Pointer_Wr <= (others => '0');
a_Arb_dQH_Next_dTD_Pointer_Wr <= (others => '0');
a_Arb_dQH_T_Wr <= '0';
a_Arb_dTD_Total_Bytes_Wr <= (others => '0');
a_Arb_dTD_IOC_Wr <= '0';
a_Arb_dTD_C_Page_Wr <= (others => '0');
a_Arb_dTD_Mult_Wr <= (others => '0');
a_Arb_dTD_Status_Wr <= (others => '0');
a_Arb_dTD_Page0_Wr <= (others => '0');
a_Arb_dTD_Page1_Wr <= (others => '0');
a_Arb_dTD_Page2_Wr <= (others => '0');
a_Arb_dTD_Page3_Wr <= (others => '0');
a_Arb_dTD_Page4_wr <= (others => '0');
a_Arb_dTD_Current_Offset_Wr <= (others => '0');
a_USBSTS_Wr_UI_Fsm <= '0';
a_USBSTS_Wr_En_UI_Fsm <= '0';
a_USBCMD_SUTW_Wr <= '0';
a_USBCMD_SUTW_Wr_En <= '0';
a_USBCMD_ATDTW_Wr <= '0';
a_USBCMD_ATDTW_Wr_En <= '0';
a_ENDPTPRIME_Clear <= (others => '1');
a_ENDPTPRIME_Clear_En <= '0';
a_ENDPTPRIME_Set <= (others => '0');
a_ENDPTPRIME_Set_En <= '0';
a_ENDPTCOMPLETE_Wr <= (others => '0');
a_ENDPTCOMPLETE_Wr_En <= '0';
a_ENDPTSETUPSTAT_Wr_Fsm <= (others => '0');
a_ENDPTSETUPSTAT_Wr_En_Fsm <= '0';
a_Arb_ENDPTSETUP_RECEIVED_Clear <= (others => '1');
a_Arb_ENDPTSETUP_RECEIVED_Clear_En <= '0';
a_ENDPTSTAT_Set <= (others => '0');
a_ENDPTSTAT_Set_En <= '0';
a_ENDPTSTAT_clear <= (others => '1');
a_ENDPTSTAT_Clear_En <= '0';
a_EMDPTFLUSH_Set <= (others => '0');
a_EMDPTFLUSH_Set_En <= '0';
a_In_Packet_Complete_Clear_En <= '0';
a_In_Packet_Complete_Clear <= (others => '1');
a_Send_Zero_Length_Packet_Set <= (others => '0');
a_Send_Zero_Length_Packet_Set_En <= '0';
a_Send_Zero_Length_Packet_Ack_Clear <= (others => '1');
a_Send_Zero_Length_Packet_Ack_Clear_En <= '0';
a_In_Token_Received_Clear <= (others => '1');
a_In_Token_Received_Clear_En <= '0';
a_Resend_Clear_En <= '0';
a_Resend_Clear <= (others => '1');
a_DMA_In_Transfer_Length_Le <= '0';
case state is -- state machine triggered by 2 conditions: priming of an endpoint or setup packet arrival; setup packets processed separately; OUT framework not tested
when IDLE =>
state_ind_arb <= "000000";
if (a_Prime = '1') then
a_Endpt_Nr_Fsm <= a_Endpt_Nr_Prime;
a_Context_Mux_Ctrl <= '0'; -- DMA writes Context
a_Endpt_Nr_Le <= '1';
next_state <= PRIME_MM2S_DQH;
elsif (a_Setup_Received = '1') then
a_Context_Mux_Ctrl <= '1';
a_Endpt_Nr_Fsm <= a_Endpt_Nr_Setup;
a_Endpt_Nr_Le <= '1';
next_state <= SETUP_LOCKOUT_TRIPWIRE;
elsif (a_In_Token_Received = '1') then
a_Context_Mux_Ctrl <= '0'; -- DMA writes Context
a_Endpt_Nr_Fsm <= a_Endpt_Nr_In_Token;
a_Endpt_Nr_Le <= '1';
next_state <= START_IN_FRAMEWORK;
elsif (RX_COMMAND_FIFO_EMPTY /= '1' and RX_COMMAND_FIFO_VALID = '1') then
RX_COMMAND_FIFO_RD_EN <= '1';
next_state <= START_OUT_FRAMEWORK;
end if;
------------------SETUP PACKET PROCESSING--------------------------
when SETUP_LOCKOUT_TRIPWIRE =>
state_ind_arb <= "000001";
a_Context_Mux_Ctrl <= '1';
if (a_USBMODE_Rd(SLOM) = '0') then
next_state <= IDLE;
else
a_USBCMD_SUTW_Wr <= '0';
a_USBCMD_SUTW_Wr_En <= '1';
a_In_Token_Received_Clear(a_Bit_Index + 16) <= '0';
a_In_Token_Received_Clear_En <= '1';
a_EMDPTFLUSH_Set(a_Bit_Index + 16) <= '1';
a_EMDPTFLUSH_Set_En <= '1';
next_state <= SETUP_UPDATE_SETUP_BYTES;
end if;
when SETUP_UPDATE_SETUP_BYTES =>
state_ind_arb <= "000010";
a_USBCMD_SUTW_Wr <= '0';
a_USBCMD_SUTW_Wr_En <= '1';
a_Axis_MM2S_Mux_Ctrl_Fsm <= '1'; -- context memory connected to DMA stream port, not FIFO
a_Context_Mux_Ctrl <= '1'; -- DMA_Transfer_Manager writes Context
a_dQH_Setup_Buffer_Wr_En <= '1';
next_state <= SETUP_WAIT1;
when SETUP_WAIT1 => --wait for dqh to be updated in context memory
state_ind_arb <= "000011";
a_USBCMD_SUTW_Wr <= '0';
a_USBCMD_SUTW_Wr_En <= '1';
next_state <= SETUP_S2MM;
when SETUP_S2MM =>
state_ind_arb <= "000100";
a_USBCMD_SUTW_Wr <= '0';
a_USBCMD_SUTW_Wr_En <= '1';
a_Axis_MM2S_Mux_Ctrl_Fsm <= '1'; -- context memory connected to DMA stream port, not FIFO
a_Context_Mux_Ctrl <= '0'; -- DMA writes Context
a_Start_DMA_S2MM <= '1';
a_Write_Setup_Bytes_FSM <= '1';
a_DMA_Source_Dest_Addr <= a_Endpointlistaddr_Loc & std_logic_vector(to_unsigned(((a_Endpt_Nr_Int*64)+40),11));
a_DMA_Transfer_Length <= std_logic_vector(to_unsigned(8,32)); --dQH = 2*4 Bytes
if (a_DMA_Transfer_Complete = '1') then
a_Write_Setup_Bytes_FSM <= '0';
a_ENDPTSETUPSTAT_Wr_Fsm(a_Bit_Index) <= '1';
a_ENDPTSETUPSTAT_Wr_En_Fsm <= '1';
a_USBSTS_Wr_UI_Fsm <= '1';
a_USBSTS_Wr_En_UI_Fsm <= '1';
next_state <= SETUP_UPDATE_ENDPTSETUP_RECEIVED;
end if;
when SETUP_UPDATE_ENDPTSETUP_RECEIVED =>
state_ind_arb <= "000101";
a_Arb_ENDPTSETUP_RECEIVED_Clear(a_Bit_Index) <= '0';
a_Arb_ENDPTSETUP_RECEIVED_Clear_En <= '1';
if (a_Arb_ENDPTSETUP_RECEIVED_Ack = '1') then
next_state <= SETUP_WAIT2;
end if;
when SETUP_WAIT2 =>
next_state <= IDLE;
------------------------------ PRIME FRAMEWORK -----------------------------------------
when PRIME_MM2S_DQH => --read DQH from main memory
state_ind_arb <= "000110";
a_Axis_MM2S_Mux_Ctrl_Fsm <= '1'; -- context memory connected to DMA stream port, not FIFO
a_Context_Mux_Ctrl <= '0'; -- DMA writes Context
a_DMA_Source_Dest_Addr <= a_Endpointlistaddr_Loc & std_logic_vector(to_unsigned((a_Endpt_Nr_Int*64),11));
a_DMA_Transfer_Length <= std_logic_vector(to_unsigned(48,32)); --dQH = 48 Bytes
a_Start_DMA_MM2S <= '1';
a_Read_dQH_Fsm <= '1';
if (a_DMA_Transfer_Complete = '1') then
next_state <= PRIME_WAIT0;
end if;
when PRIME_WAIT0 =>
state_ind_arb <= "000000";
a_Axis_MM2S_Mux_Ctrl_Fsm <= '1'; -- context memory connected to DMA stream port, not FIFO
a_Context_Mux_Ctrl <= '0'; -- DMA writes Context
next_state <= PRIME_MM2S_DTD;
when PRIME_MM2S_DTD => --read DQH from main memory
state_ind_arb <= "100110";
a_Axis_MM2S_Mux_Ctrl_Fsm <= '1'; -- context memory connected to DMA stream port, not FIFO
a_Context_Mux_Ctrl <= '0'; -- DMA writes Context
a_DMA_Source_Dest_Addr <= a_dQH_Next_dTD_Pointer_Rd & "00000";
a_DMA_Transfer_Length <= std_logic_vector(to_unsigned(28,32)); --dTD = 7*4 Bytes
a_Start_DMA_MM2S <= '1';
a_Read_dTD_Fsm <= '1';
if (a_DMA_Transfer_Complete = '1') then
a_Arb_dQH_Current_dTD_Pointer_Wr <= a_dQH_Next_dTD_Pointer_Rd;
a_Arb_dQH_Current_dTD_Pointer_Wr_En <= '1';
a_DMA_Current_Transfer_Addr_Fsm <= a_dTD_Page0_Rd & a_dTD_Current_Offset_Rd; --initialize the transfer address with PAGE0
a_DMA_Current_Transfer_Addr_Le <= '1';
if (a_Endpt_In_Out = '1') then --IN endpoint, FIFO needs to be prepared with transmit data
tx_fifo_resetn <= '0'; -- flush fifo;
a_Axis_MM2S_Mux_Ctrl_Fsm <= '0'; -- FIFO connected to DMA stream port, not context memory
next_state <= PRIME_FILL_FIFO;
else --OUT endpoint
a_ENDPTPRIME_Clear(a_Bit_Index) <= '0';
a_ENDPTPRIME_Clear_En <= '1';
a_ENDPTSTAT_Set(a_Bit_Index) <= '1';
a_ENDPTSTAT_Set_En <= '1';
next_state <= PRIME_WAIT1;
end if;
end if;
when PRIME_FILL_FIFO => --extract necessary data to fill TX fifo
state_ind_arb <= "000111";
a_Context_Mux_Ctrl <= '1'; -- DMA_Transfer_Manager writes Context
a_Axis_MM2S_Mux_Ctrl_Fsm <= '0'; -- FIFO connected to DMA stream port, not context memory
if (a_dTD_Total_Bytes_Rd = "000000000000000") then
a_ENDPTPRIME_Clear(a_Bit_Index) <= '0';
a_ENDPTPRIME_Clear_En <= '1';
a_ENDPTSTAT_Set(a_Bit_Index) <= '1';
a_ENDPTSTAT_Set_En <= '1';
a_Send_Zero_Length_Packet_Set(a_Bit_Index) <= '1';
a_Send_Zero_Length_Packet_Set_En <= '1';
next_state <= PRIME_WAIT1;
else
if (to_integer(unsigned(a_dTD_Total_Bytes_Rd)) < C_FIFO_SIZE) then
next_state <= PRIME_FILL_FIFO_1;
else
next_state <= PRIME_FILL_FIFO_2;
end if;
end if;
when PRIME_FILL_FIFO_1 =>
state_ind_arb <= "001000";
a_Axis_MM2S_Mux_Ctrl_Fsm <= '0'; -- FIFO connected to DMA stream port, not context memory
a_Context_Mux_Ctrl <= '1'; -- DMA_Transfer_Manager writes Context
a_DMA_Transfer_Length <= "00000000000000000" & a_dTD_Total_Bytes_Rd;
a_DMA_Source_Dest_Addr <= a_DMA_Current_Transfer_Addr_Array(a_Endpt_Nr_4b);
a_Start_DMA_MM2S <= '1';
if (a_DMA_Transfer_Complete = '1') then
a_ENDPTPRIME_Clear(a_Bit_Index) <= '0';
a_ENDPTPRIME_Clear_En <= '1';
a_ENDPTSTAT_Set(a_Bit_Index) <= '1';
a_ENDPTSTAT_Set_En <= '1';
a_Arb_dQH_Current_dTD_Pointer_Wr <= std_logic_vector(unsigned(a_dQH_Current_dTD_Pointer_Rd) + unsigned(a_dTD_Total_Bytes_Rd)); --update the memory address for the s2mm transfer
a_Arb_dQH_Current_dTD_Pointer_Wr_En <= '1';
next_state <= PRIME_WAIT1;
end if;
when PRIME_FILL_FIFO_2 =>
state_ind_arb <= "001001";
a_Axis_MM2S_Mux_Ctrl_Fsm <= '0'; -- FIFO connected to DMA stream port, not context memory
a_Context_Mux_Ctrl <= '1'; -- DMA_Transfer_Manager writes Context
a_DMA_Source_Dest_Addr <= a_DMA_Current_Transfer_Addr_Array(a_Endpt_Nr_4b);
a_DMA_Transfer_Length <= std_logic_vector(to_unsigned(C_FIFO_SIZE,32));
a_Start_DMA_MM2S <= '1';
if (a_DMA_Transfer_Complete = '1') then
a_DMA_Current_Transfer_Addr_Fsm <= std_logic_vector(unsigned(a_Aux_Addr_Register) + (C_FIFO_SIZE));
a_DMA_Current_Transfer_Addr_Le <= '1';
a_ENDPTPRIME_Clear(a_Bit_Index) <= '0';
a_ENDPTPRIME_Clear_En <= '1';
a_ENDPTSTAT_Set(a_Bit_Index) <= '1';
a_ENDPTSTAT_Set_En <= '1';
a_Arb_dQH_Current_dTD_Pointer_Wr <= std_logic_vector(unsigned(a_dQH_Current_dTD_Pointer_Rd) + (C_FIFO_SIZE)); --update the memory address for the s2mm transfer
a_Arb_dQH_Current_dTD_Pointer_Wr_En <= '1';
next_state <= PRIME_WAIT1;
end if;
when PRIME_WAIT1 =>
state_ind_arb <= "001010";
next_state <= PRIME_WAIT2;
when PRIME_WAIT2 =>
state_ind_arb <= "001011";
next_state <= IDLE;
---------OUT_TOKEN_FRAMEWORK (RX_PACKET)---------------------------------------------------------------------------
when START_OUT_FRAMEWORK =>
state_ind_arb <= "001100";
a_Axis_MM2S_Mux_Ctrl_Fsm <= '0'; -- FIFO connected to DMA stream port, not context memory
a_Context_Mux_Ctrl <= '1'; -- DMA_Transfer_Manager writes Context
a_Out_Transfer_Byte_Count_Le1 <= '1';
a_Endpt_Nr_Fsm <= to_integer(unsigned(RX_COMMAND_FIFO_DOUT(10 downto 7)));
a_Endpt_Nr_Le <= '1';
next_state <= OUT_START_TRANSFER;
when OUT_START_TRANSFER =>
state_ind_arb <= "001101";
a_Axis_MM2S_Mux_Ctrl_Fsm <= '0'; -- FIFO connected to DMA stream port, not context memory
a_Context_Mux_Ctrl <= '1'; -- DMA_Transfer_Manager writes Context
if (a_Out_Transfer_Byte_Count <= a_dTD_Total_Bytes_Rd)then
next_state <= OUT_TRANSFER_S2MM;
else
next_state <= IDLE; --ERROR
end if;
when OUT_TRANSFER_S2MM =>
state_ind_arb <= "001110";
a_Axis_S2MM_Mux_Ctrl_Fsm <= '0'; -- FIFO connected to DMA stream port, not context memory
a_Context_Mux_Ctrl <= '1'; -- DMA_Transfer_Manager writes Context
a_DMA_Source_Dest_Addr <= a_DMA_Current_Transfer_Addr_Array(a_Endpt_Nr_4b);
a_DMA_Transfer_Length <= "0000000000000000000" & a_Out_Transfer_Byte_Count; --transfer the received packet in main memory
a_Start_DMA_S2MM <= '1';
if (a_DMA_Transfer_Complete = '1') then
a_Arb_dTD_Total_Bytes_Wr <= std_logic_vector(unsigned(a_dTD_Total_Bytes_Rd)- unsigned(a_Out_Transfer_Byte_Count)); --update the number of bytes left to transfer
a_Arb_dTD_Total_Bytes_Wr_En <= '1'; -- update dTD_TOTAL_BYTES
a_DMA_Current_Transfer_Addr_Fsm <= std_logic_vector(unsigned(a_DMA_Current_Transfer_Addr_Array(a_Endpt_Nr_4b)) + unsigned(a_Out_Transfer_Byte_Count)); --update the memory address for the s2mm transfer
a_DMA_Current_Transfer_Addr_Le <= '1';
next_state <= OUT_WAIT1;
end if;
when OUT_WAIT1 =>
state_ind_arb <= "001111";
next_state <= OUT_CHECK_COMPLETE;
when OUT_CHECK_COMPLETE =>
state_ind_arb <= "010000";
if (a_dTD_Total_Bytes_Rd = "000000000000000") then
a_Axis_MM2S_Mux_Ctrl_Fsm <= '1'; -- context memory connected to DMA stream port, not FIFO
a_Context_Mux_Ctrl <= '0'; -- DMA writes Context
a_ENDPTPRIME_Set(a_Bit_Index) <= '1';
a_ENDPTPRIME_Set_En <= '1';
next_state <= OUT_TRANSFER_COMPLETE;
else
next_state <= IDLE;
end if;
when OUT_TRANSFER_COMPLETE =>
state_ind_arb <= "010001";
a_Axis_MM2S_Mux_Ctrl_Fsm <= '1'; -- context memory connected to DMA stream port, not FIFO
a_Context_Mux_Ctrl <= '0'; -- DMA writes Context
a_Start_DMA_S2MM <= '1';
a_Write_dQH_Fsm <= '1';
a_DMA_Source_Dest_Addr <= a_Endpointlistaddr_Loc & std_logic_vector(to_unsigned((a_Endpt_Nr_Int*64),11));
a_DMA_Transfer_Length <= std_logic_vector(to_unsigned(48,32)); --dQH = 48 Bytes
if (a_DMA_Transfer_Complete = '1') then
a_Write_dQH_Fsm <= '0';
if (a_dQH_T_Rd = '0') then
a_USBCMD_ATDTW_Wr <= '0';
a_USBCMD_ATDTW_Wr_En <= '1';
a_USBSTS_Wr_UI_Fsm <= '1';
a_USBSTS_Wr_En_UI_Fsm <= '1';
next_state <= OUT_FETCH_NEXT_DTD;
else
a_ENDPTCOMPLETE_Wr(a_Bit_Index) <= '1';
a_ENDPTCOMPLETE_Wr_En <= '1';
next_state <= IDLE;
end if;
end if;
when OUT_FETCH_NEXT_DTD =>
state_ind_arb <= "010010";
a_Axis_MM2S_Mux_Ctrl_Fsm <= '1'; -- context memory connected to DMA stream port, not FIFO
a_Context_Mux_Ctrl <= '0'; -- DMA writes Context
a_DMA_Source_Dest_Addr <= a_dQH_Next_dTD_Pointer_Rd & "00000";
a_DMA_Transfer_Length <= std_logic_vector(to_unsigned(28,32)); --dQH = 7*4 Bytes
a_Start_DMA_MM2S <= '1';
a_Read_dTD_Fsm <= '1';
if (a_DMA_Transfer_Complete = '1') then
a_Arb_dQH_Current_dTD_Pointer_Wr <= a_dQH_Next_dTD_Pointer_Rd;
a_Arb_dQH_Current_dTD_Pointer_Wr_En <= '1';
a_ENDPTPRIME_Clear(a_Bit_Index) <= '0';
a_ENDPTPRIME_Clear_En <= '1';
next_state <= OUT_WAIT2;
end if;
when OUT_WAIT2 =>
state_ind_arb <= "010011";
next_state <= IDLE;
---------IN_TOKEN_FRAMEWORK (TX_PACKET)---------------------------------------------------------------------------
when START_IN_FRAMEWORK =>
state_ind_arb <= "010100";
a_Axis_MM2S_Mux_Ctrl_Fsm <= '1'; --context memory connected to DMA stream port, not FIFO if 0 fifo will assert tvalid for 1 ck cycle
a_Context_Mux_Ctrl <= '0';
a_In_Token_Received_Clear(a_Bit_Index) <= '0';
a_In_Token_Received_Clear_En <= '1';
if (a_In_Packet_Complete_Rd(a_Bit_Index) = '1') then
a_In_Packet_Complete_Clear(a_Bit_Index) <= '0';
a_In_Packet_Complete_Clear_En <= '1';
next_state <= IN_HANDSHAKE;
elsif (a_Resend(a_Bit_Index) = '1') then
tx_fifo_resetn <= '0'; -- flush fifo;
next_state <= IN_HANDSHAKE;
end if;
when IN_HANDSHAKE =>
state_ind_arb <= "010101";
a_Axis_MM2S_Mux_Ctrl_Fsm <= '1'; -- context memory connected to DMA stream port, not FIFO
a_Context_Mux_Ctrl <= '1';
if (a_Cnt_Bytes_Sent_oValid = '1') then
if (a_Resend(a_Bit_Index) = '0') then
a_Arb_dTD_Total_Bytes_Wr <= std_logic_vector(unsigned(a_dTD_Total_Bytes_Rd)- unsigned(a_Cnt_Bytes_Sent_Loc)); --update the number of bytes left to transfer
a_Arb_dTD_Total_Bytes_Wr_En <= '1'; -- update dTD_TOTAL_BYTES
end if;
next_state <= IN_WAIT0;
end if;
when IN_WAIT0 =>
a_Axis_MM2S_Mux_Ctrl_Fsm <= '1'; -- context memory connected to DMA stream port, not FIFO
state_ind_arb <= "010111";
if (a_Resend(a_Bit_Index) = '0') then
next_state <= IN_CHECK_COMPLETE;
else
a_Resend_Clear(a_Bit_Index) <= '0';
a_Resend_Clear_En <= '1';
next_state <= IN_RELOAD_BUFFER;
end if;
when IN_CHECK_COMPLETE =>
state_ind_arb <= "011000";
a_DMA_In_Transfer_Length_Le <= '1';
if (a_dTD_Total_Bytes_Rd = "000000000000000") then
a_dTD_Status_Wr_En <= '1'; --write 0 to active bit
next_state <= IN_TRANSACTION_COMPLETE;
else
next_state <= IN_TRANSFER_MM2S;
end if;
when IN_TRANSFER_MM2S =>
state_ind_arb <= "010110";
a_Axis_MM2S_Mux_Ctrl_Fsm <= '0'; -- FIFO connected to DMA stream port, not context memory
a_Context_Mux_Ctrl <= '1'; -- DMA_Transfer_Manager writes Context
a_DMA_Transfer_Length <= a_DMA_In_Transfer_Length;
a_DMA_Source_Dest_Addr <= a_DMA_Current_Transfer_Addr_Array(a_Endpt_Nr_4b);
a_Start_DMA_MM2S <= '1';
if (a_DMA_Transfer_Complete = '1') then
next_state <= IN_WAIT1;
a_DMA_Current_Transfer_Addr_Fsm <= std_logic_vector(unsigned(a_Aux_Addr_Register) + unsigned(a_Cnt_Bytes_Sent_Loc));
a_DMA_Current_Transfer_Addr_Le <= '1';
a_Arb_dQH_Current_dTD_Pointer_Wr <= std_logic_vector(unsigned(a_dQH_Current_dTD_Pointer_Rd) + unsigned(a_Cnt_Bytes_Sent_Loc)); --update the memory address for the s2mm transfer
a_Arb_dQH_Current_dTD_Pointer_Wr_En <= '1';
end if;
when IN_RELOAD_BUFFER =>
state_ind_arb <= "111011";
a_Axis_MM2S_Mux_Ctrl_Fsm <= '0'; -- FIFO connected to DMA stream port, not context memory
a_Context_Mux_Ctrl <= '1'; -- DMA_Transfer_Manager writes Context
a_DMA_Transfer_Length <= a_DMA_In_Transfer_Length;
a_DMA_Source_Dest_Addr <= a_DMA_Current_Transfer_Addr_Array_q(a_Endpt_Nr_4b);
a_Start_DMA_MM2S <= '1';
if (a_DMA_Transfer_Complete = '1') then
next_state <= IN_WAIT1;
end if;
when IN_WAIT1 =>
a_Axis_MM2S_Mux_Ctrl_Fsm <= '1'; -- context memory connected to DMA stream port, not FIFO
state_ind_arb <= "010111";
next_state <= IDLE;
when IN_TRANSACTION_COMPLETE => --copy dQH back to main memory with status updated
state_ind_arb <= "011001";
a_Axis_MM2S_Mux_Ctrl_Fsm <= '1'; -- context memory connected to DMA stream port, not FIFO
a_Context_Mux_Ctrl <= '0'; -- DMA writes Context
a_Start_DMA_S2MM <= '1';
a_Write_dQH_Fsm <= '1';
a_DMA_Source_Dest_Addr <= a_Endpointlistaddr_Loc & std_logic_vector(to_unsigned((a_Endpt_Nr_Int*64),11));
a_DMA_Transfer_Length <= std_logic_vector(to_unsigned(48,32)); --dQH = 48 Bytes
if (a_DMA_Transfer_Complete = '1' or a_Send_Zero_Length_Packet_Ack_Rd(a_Bit_Index) = '1') then
a_Write_dQH_Fsm <= '0';
a_Send_Zero_Length_Packet_Ack_Clear(a_Bit_Index) <= '1';
a_Send_Zero_Length_Packet_Ack_Clear_En <= '1';
if (a_dQH_T_Rd = '1') then
a_ENDPTCOMPLETE_Wr(a_Bit_Index) <= '1';
a_ENDPTCOMPLETE_Wr_En <= '1';
a_ENDPTSTAT_clear(a_Bit_Index) <= '0';
a_ENDPTSTAT_Clear_En <= '1';
a_USBSTS_Wr_UI_Fsm <= '1';
a_USBSTS_Wr_En_UI_Fsm <= '1';
next_state <= IDLE;
else
a_USBCMD_ATDTW_Wr <= '0';
a_USBCMD_ATDTW_Wr_En <= '1';
a_ENDPTPRIME_Set(a_Bit_Index) <= '1';
a_ENDPTPRIME_Set_En <= '1';
next_state <= IN_FETCH_NEXT_DTD;
end if;
end if;
when IN_FETCH_NEXT_DTD =>
state_ind_arb <= "011010";
a_Axis_MM2S_Mux_Ctrl_Fsm <= '1'; -- context memory connected to DMA stream port, not FIFO
a_Context_Mux_Ctrl <= '0'; -- DMA writes Context
a_DMA_Source_Dest_Addr <= a_dQH_Next_dTD_Pointer_Rd & "00000";
a_DMA_Transfer_Length <= std_logic_vector(to_unsigned(28,32)); --dQH = 7*4 Bytes
a_Start_DMA_MM2S <= '1';
a_Read_dTD_Fsm <= '1';
if (a_DMA_Transfer_Complete = '1') then
a_Arb_dQH_Current_dTD_Pointer_Wr <= a_dQH_Next_dTD_Pointer_Rd;
a_Arb_dQH_Current_dTD_Pointer_Wr_En <= '1';
a_ENDPTPRIME_Clear(a_Bit_Index) <= '0';
a_ENDPTPRIME_Clear_En <= '1';
next_state <= IN_WAIT2;
end if;
when IN_WAIT2 =>
state_ind_arb <= "011011";
next_state <= IDLE;
when others =>
state_ind_arb <= "011100";
next_state <= IDLE;
end case;
end process;
end implementation;
|
bsd-3-clause
|
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/usb2device_v1_0/src/axi_dma_0/synth/axi_dma_0.vhd
|
1
|
26023
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_dma:7.1
-- IP Revision: 8
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_dma_v7_1_8;
USE axi_dma_v7_1_8.axi_dma;
ENTITY axi_dma_0 IS
PORT (
s_axi_lite_aclk : IN STD_LOGIC;
m_axi_mm2s_aclk : IN STD_LOGIC;
m_axi_s2mm_aclk : IN STD_LOGIC;
axi_resetn : IN STD_LOGIC;
s_axi_lite_awvalid : IN STD_LOGIC;
s_axi_lite_awready : OUT STD_LOGIC;
s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
s_axi_lite_wvalid : IN STD_LOGIC;
s_axi_lite_wready : OUT STD_LOGIC;
s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_lite_bvalid : OUT STD_LOGIC;
s_axi_lite_bready : IN STD_LOGIC;
s_axi_lite_arvalid : IN STD_LOGIC;
s_axi_lite_arready : OUT STD_LOGIC;
s_axi_lite_araddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
s_axi_lite_rvalid : OUT STD_LOGIC;
s_axi_lite_rready : IN STD_LOGIC;
s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_arvalid : OUT STD_LOGIC;
m_axi_mm2s_arready : IN STD_LOGIC;
m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_rlast : IN STD_LOGIC;
m_axi_mm2s_rvalid : IN STD_LOGIC;
m_axi_mm2s_rready : OUT STD_LOGIC;
mm2s_prmry_reset_out_n : OUT STD_LOGIC;
m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_tvalid : OUT STD_LOGIC;
m_axis_mm2s_tready : IN STD_LOGIC;
m_axis_mm2s_tlast : OUT STD_LOGIC;
m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awvalid : OUT STD_LOGIC;
m_axi_s2mm_awready : IN STD_LOGIC;
m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_wlast : OUT STD_LOGIC;
m_axi_s2mm_wvalid : OUT STD_LOGIC;
m_axi_s2mm_wready : IN STD_LOGIC;
m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_bvalid : IN STD_LOGIC;
m_axi_s2mm_bready : OUT STD_LOGIC;
s2mm_prmry_reset_out_n : OUT STD_LOGIC;
s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_tvalid : IN STD_LOGIC;
s_axis_s2mm_tready : OUT STD_LOGIC;
s_axis_s2mm_tlast : IN STD_LOGIC;
mm2s_introut : OUT STD_LOGIC;
s2mm_introut : OUT STD_LOGIC;
axi_dma_tstvec : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END axi_dma_0;
ARCHITECTURE axi_dma_0_arch OF axi_dma_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF axi_dma_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_dma IS
GENERIC (
C_S_AXI_LITE_ADDR_WIDTH : INTEGER;
C_S_AXI_LITE_DATA_WIDTH : INTEGER;
C_DLYTMR_RESOLUTION : INTEGER;
C_PRMRY_IS_ACLK_ASYNC : INTEGER;
C_ENABLE_MULTI_CHANNEL : INTEGER;
C_NUM_MM2S_CHANNELS : INTEGER;
C_NUM_S2MM_CHANNELS : INTEGER;
C_INCLUDE_SG : INTEGER;
C_SG_INCLUDE_STSCNTRL_STRM : INTEGER;
C_SG_USE_STSAPP_LENGTH : INTEGER;
C_SG_LENGTH_WIDTH : INTEGER;
C_M_AXI_SG_ADDR_WIDTH : INTEGER;
C_M_AXI_SG_DATA_WIDTH : INTEGER;
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH : INTEGER;
C_S_AXIS_S2MM_STS_TDATA_WIDTH : INTEGER;
C_MICRO_DMA : INTEGER;
C_INCLUDE_MM2S : INTEGER;
C_INCLUDE_MM2S_SF : INTEGER;
C_MM2S_BURST_SIZE : INTEGER;
C_M_AXI_MM2S_ADDR_WIDTH : INTEGER;
C_M_AXI_MM2S_DATA_WIDTH : INTEGER;
C_M_AXIS_MM2S_TDATA_WIDTH : INTEGER;
C_INCLUDE_MM2S_DRE : INTEGER;
C_INCLUDE_S2MM : INTEGER;
C_INCLUDE_S2MM_SF : INTEGER;
C_S2MM_BURST_SIZE : INTEGER;
C_M_AXI_S2MM_ADDR_WIDTH : INTEGER;
C_M_AXI_S2MM_DATA_WIDTH : INTEGER;
C_S_AXIS_S2MM_TDATA_WIDTH : INTEGER;
C_INCLUDE_S2MM_DRE : INTEGER;
C_FAMILY : STRING
);
PORT (
s_axi_lite_aclk : IN STD_LOGIC;
m_axi_sg_aclk : IN STD_LOGIC;
m_axi_mm2s_aclk : IN STD_LOGIC;
m_axi_s2mm_aclk : IN STD_LOGIC;
axi_resetn : IN STD_LOGIC;
s_axi_lite_awvalid : IN STD_LOGIC;
s_axi_lite_awready : OUT STD_LOGIC;
s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
s_axi_lite_wvalid : IN STD_LOGIC;
s_axi_lite_wready : OUT STD_LOGIC;
s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_lite_bvalid : OUT STD_LOGIC;
s_axi_lite_bready : IN STD_LOGIC;
s_axi_lite_arvalid : IN STD_LOGIC;
s_axi_lite_arready : OUT STD_LOGIC;
s_axi_lite_araddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
s_axi_lite_rvalid : OUT STD_LOGIC;
s_axi_lite_rready : IN STD_LOGIC;
s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_sg_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_awuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_awvalid : OUT STD_LOGIC;
m_axi_sg_awready : IN STD_LOGIC;
m_axi_sg_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_wlast : OUT STD_LOGIC;
m_axi_sg_wvalid : OUT STD_LOGIC;
m_axi_sg_wready : IN STD_LOGIC;
m_axi_sg_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_bvalid : IN STD_LOGIC;
m_axi_sg_bready : OUT STD_LOGIC;
m_axi_sg_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_sg_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_aruser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_arvalid : OUT STD_LOGIC;
m_axi_sg_arready : IN STD_LOGIC;
m_axi_sg_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_rlast : IN STD_LOGIC;
m_axi_sg_rvalid : IN STD_LOGIC;
m_axi_sg_rready : OUT STD_LOGIC;
m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_aruser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_arvalid : OUT STD_LOGIC;
m_axi_mm2s_arready : IN STD_LOGIC;
m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_rlast : IN STD_LOGIC;
m_axi_mm2s_rvalid : IN STD_LOGIC;
m_axi_mm2s_rready : OUT STD_LOGIC;
mm2s_prmry_reset_out_n : OUT STD_LOGIC;
m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_tvalid : OUT STD_LOGIC;
m_axis_mm2s_tready : IN STD_LOGIC;
m_axis_mm2s_tlast : OUT STD_LOGIC;
m_axis_mm2s_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_tid : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
m_axis_mm2s_tdest : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
mm2s_cntrl_reset_out_n : OUT STD_LOGIC;
m_axis_mm2s_cntrl_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_mm2s_cntrl_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_cntrl_tvalid : OUT STD_LOGIC;
m_axis_mm2s_cntrl_tready : IN STD_LOGIC;
m_axis_mm2s_cntrl_tlast : OUT STD_LOGIC;
m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awvalid : OUT STD_LOGIC;
m_axi_s2mm_awready : IN STD_LOGIC;
m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_wlast : OUT STD_LOGIC;
m_axi_s2mm_wvalid : OUT STD_LOGIC;
m_axi_s2mm_wready : IN STD_LOGIC;
m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_bvalid : IN STD_LOGIC;
m_axi_s2mm_bready : OUT STD_LOGIC;
s2mm_prmry_reset_out_n : OUT STD_LOGIC;
s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_tvalid : IN STD_LOGIC;
s_axis_s2mm_tready : OUT STD_LOGIC;
s_axis_s2mm_tlast : IN STD_LOGIC;
s_axis_s2mm_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_tid : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axis_s2mm_tdest : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s2mm_sts_reset_out_n : OUT STD_LOGIC;
s_axis_s2mm_sts_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_s2mm_sts_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_sts_tvalid : IN STD_LOGIC;
s_axis_s2mm_sts_tready : OUT STD_LOGIC;
s_axis_s2mm_sts_tlast : IN STD_LOGIC;
mm2s_introut : OUT STD_LOGIC;
s2mm_introut : OUT STD_LOGIC;
axi_dma_tstvec : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_dma;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF axi_dma_0_arch: ARCHITECTURE IS "axi_dma,Vivado 2015.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF axi_dma_0_arch : ARCHITECTURE IS "axi_dma_0,axi_dma,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF axi_dma_0_arch: ARCHITECTURE IS "axi_dma_0,axi_dma,{x_ipProduct=Vivado 2015.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_dma,x_ipVersion=7.1,x_ipCoreRevision=8,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_S_AXI_LITE_ADDR_WIDTH=10,C_S_AXI_LITE_DATA_WIDTH=32,C_DLYTMR_RESOLUTION=125,C_PRMRY_IS_ACLK_ASYNC=0,C_ENABLE_MULTI_CHANNEL=0,C_NUM_MM2S_CHANNELS=1,C_NUM_S2MM_CHANNELS=1,C_INCLUDE_SG=0,C_SG_INCLUDE_STSCNTRL_STRM=0,C_SG_USE_STSAPP_LENGTH=0,C_SG_LENGTH_WIDTH=14,C_M_AXI_SG_ADDR_WIDTH=32,C_M_AXI_SG_DATA_WIDTH=32,C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH=32,C_S_AXIS_S2MM_STS_TDATA_WIDTH=32,C_MICRO_DMA=0,C_INCLUDE_MM2S=1,C_INCLUDE_MM2S_SF=1,C_MM2S_BURST_SIZE=16,C_M_AXI_MM2S_ADDR_WIDTH=32,C_M_AXI_MM2S_DATA_WIDTH=32,C_M_AXIS_MM2S_TDATA_WIDTH=32,C_INCLUDE_MM2S_DRE=1,C_INCLUDE_S2MM=1,C_INCLUDE_S2MM_SF=1,C_S2MM_BURST_SIZE=16,C_M_AXI_S2MM_ADDR_WIDTH=32,C_M_AXI_S2MM_DATA_WIDTH=32,C_S_AXIS_S2MM_TDATA_WIDTH=32,C_INCLUDE_S2MM_DRE=1,C_FAMILY=kintex7}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_LITE_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXI_MM2S_CLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXI_S2MM_CLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF axi_resetn: SIGNAL IS "xilinx.com:signal:reset:1.0 AXI_RESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RREADY";
ATTRIBUTE X_INTERFACE_INFO OF mm2s_prmry_reset_out_n: SIGNAL IS "xilinx.com:signal:reset:1.0 MM2S_PRMRY_RESET_OUT_N RST";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TKEEP";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWLEN";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWSIZE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWBURST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWCACHE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s2mm_prmry_reset_out_n: SIGNAL IS "xilinx.com:signal:reset:1.0 S2MM_PRMRY_RESET_OUT_N RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TKEEP";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TLAST";
ATTRIBUTE X_INTERFACE_INFO OF mm2s_introut: SIGNAL IS "xilinx.com:signal:interrupt:1.0 MM2S_INTROUT INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF s2mm_introut: SIGNAL IS "xilinx.com:signal:interrupt:1.0 S2MM_INTROUT INTERRUPT";
BEGIN
U0 : axi_dma
GENERIC MAP (
C_S_AXI_LITE_ADDR_WIDTH => 10,
C_S_AXI_LITE_DATA_WIDTH => 32,
C_DLYTMR_RESOLUTION => 125,
C_PRMRY_IS_ACLK_ASYNC => 0,
C_ENABLE_MULTI_CHANNEL => 0,
C_NUM_MM2S_CHANNELS => 1,
C_NUM_S2MM_CHANNELS => 1,
C_INCLUDE_SG => 0,
C_SG_INCLUDE_STSCNTRL_STRM => 0,
C_SG_USE_STSAPP_LENGTH => 0,
C_SG_LENGTH_WIDTH => 14,
C_M_AXI_SG_ADDR_WIDTH => 32,
C_M_AXI_SG_DATA_WIDTH => 32,
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH => 32,
C_S_AXIS_S2MM_STS_TDATA_WIDTH => 32,
C_MICRO_DMA => 0,
C_INCLUDE_MM2S => 1,
C_INCLUDE_MM2S_SF => 1,
C_MM2S_BURST_SIZE => 16,
C_M_AXI_MM2S_ADDR_WIDTH => 32,
C_M_AXI_MM2S_DATA_WIDTH => 32,
C_M_AXIS_MM2S_TDATA_WIDTH => 32,
C_INCLUDE_MM2S_DRE => 1,
C_INCLUDE_S2MM => 1,
C_INCLUDE_S2MM_SF => 1,
C_S2MM_BURST_SIZE => 16,
C_M_AXI_S2MM_ADDR_WIDTH => 32,
C_M_AXI_S2MM_DATA_WIDTH => 32,
C_S_AXIS_S2MM_TDATA_WIDTH => 32,
C_INCLUDE_S2MM_DRE => 1,
C_FAMILY => "kintex7"
)
PORT MAP (
s_axi_lite_aclk => s_axi_lite_aclk,
m_axi_sg_aclk => '0',
m_axi_mm2s_aclk => m_axi_mm2s_aclk,
m_axi_s2mm_aclk => m_axi_s2mm_aclk,
axi_resetn => axi_resetn,
s_axi_lite_awvalid => s_axi_lite_awvalid,
s_axi_lite_awready => s_axi_lite_awready,
s_axi_lite_awaddr => s_axi_lite_awaddr,
s_axi_lite_wvalid => s_axi_lite_wvalid,
s_axi_lite_wready => s_axi_lite_wready,
s_axi_lite_wdata => s_axi_lite_wdata,
s_axi_lite_bresp => s_axi_lite_bresp,
s_axi_lite_bvalid => s_axi_lite_bvalid,
s_axi_lite_bready => s_axi_lite_bready,
s_axi_lite_arvalid => s_axi_lite_arvalid,
s_axi_lite_arready => s_axi_lite_arready,
s_axi_lite_araddr => s_axi_lite_araddr,
s_axi_lite_rvalid => s_axi_lite_rvalid,
s_axi_lite_rready => s_axi_lite_rready,
s_axi_lite_rdata => s_axi_lite_rdata,
s_axi_lite_rresp => s_axi_lite_rresp,
m_axi_sg_awready => '0',
m_axi_sg_wready => '0',
m_axi_sg_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_sg_bvalid => '0',
m_axi_sg_arready => '0',
m_axi_sg_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
m_axi_sg_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_sg_rlast => '0',
m_axi_sg_rvalid => '0',
m_axi_mm2s_araddr => m_axi_mm2s_araddr,
m_axi_mm2s_arlen => m_axi_mm2s_arlen,
m_axi_mm2s_arsize => m_axi_mm2s_arsize,
m_axi_mm2s_arburst => m_axi_mm2s_arburst,
m_axi_mm2s_arprot => m_axi_mm2s_arprot,
m_axi_mm2s_arcache => m_axi_mm2s_arcache,
m_axi_mm2s_arvalid => m_axi_mm2s_arvalid,
m_axi_mm2s_arready => m_axi_mm2s_arready,
m_axi_mm2s_rdata => m_axi_mm2s_rdata,
m_axi_mm2s_rresp => m_axi_mm2s_rresp,
m_axi_mm2s_rlast => m_axi_mm2s_rlast,
m_axi_mm2s_rvalid => m_axi_mm2s_rvalid,
m_axi_mm2s_rready => m_axi_mm2s_rready,
mm2s_prmry_reset_out_n => mm2s_prmry_reset_out_n,
m_axis_mm2s_tdata => m_axis_mm2s_tdata,
m_axis_mm2s_tkeep => m_axis_mm2s_tkeep,
m_axis_mm2s_tvalid => m_axis_mm2s_tvalid,
m_axis_mm2s_tready => m_axis_mm2s_tready,
m_axis_mm2s_tlast => m_axis_mm2s_tlast,
m_axis_mm2s_cntrl_tready => '0',
m_axi_s2mm_awaddr => m_axi_s2mm_awaddr,
m_axi_s2mm_awlen => m_axi_s2mm_awlen,
m_axi_s2mm_awsize => m_axi_s2mm_awsize,
m_axi_s2mm_awburst => m_axi_s2mm_awburst,
m_axi_s2mm_awprot => m_axi_s2mm_awprot,
m_axi_s2mm_awcache => m_axi_s2mm_awcache,
m_axi_s2mm_awvalid => m_axi_s2mm_awvalid,
m_axi_s2mm_awready => m_axi_s2mm_awready,
m_axi_s2mm_wdata => m_axi_s2mm_wdata,
m_axi_s2mm_wstrb => m_axi_s2mm_wstrb,
m_axi_s2mm_wlast => m_axi_s2mm_wlast,
m_axi_s2mm_wvalid => m_axi_s2mm_wvalid,
m_axi_s2mm_wready => m_axi_s2mm_wready,
m_axi_s2mm_bresp => m_axi_s2mm_bresp,
m_axi_s2mm_bvalid => m_axi_s2mm_bvalid,
m_axi_s2mm_bready => m_axi_s2mm_bready,
s2mm_prmry_reset_out_n => s2mm_prmry_reset_out_n,
s_axis_s2mm_tdata => s_axis_s2mm_tdata,
s_axis_s2mm_tkeep => s_axis_s2mm_tkeep,
s_axis_s2mm_tvalid => s_axis_s2mm_tvalid,
s_axis_s2mm_tready => s_axis_s2mm_tready,
s_axis_s2mm_tlast => s_axis_s2mm_tlast,
s_axis_s2mm_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_s2mm_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
s_axis_s2mm_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
s_axis_s2mm_sts_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_s2mm_sts_tkeep => X"F",
s_axis_s2mm_sts_tvalid => '0',
s_axis_s2mm_sts_tlast => '0',
mm2s_introut => mm2s_introut,
s2mm_introut => s2mm_introut,
axi_dma_tstvec => axi_dma_tstvec
);
END axi_dma_0_arch;
|
bsd-3-clause
|
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/usb2device_v1_0/src/fifo_generator_0/fifo_generator_v13_0_1/simulation/fifo_generator_vhdl_beh.vhd
|
15
|
465879
|
-------------------------------------------------------------------------------
--
-- FIFO Generator - VHDL Behavioral Model
--
-------------------------------------------------------------------------------
-- (c) Copyright 1995 - 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- Filename: fifo_generator_vhdl_beh.vhd
--
-- Author : Xilinx
--
-------------------------------------------------------------------------------
-- Structure:
--
-- fifo_generator_vhdl_beh.vhd
-- |
-- +-fifo_generator_v13_0_1_conv
-- |
-- +-fifo_generator_v13_0_1_bhv_as
-- |
-- +-fifo_generator_v13_0_1_bhv_ss
-- |
-- +-fifo_generator_v13_0_1_bhv_preload0
--
-------------------------------------------------------------------------------
-- Description:
--
-- The VHDL behavioral model for the FIFO Generator.
--
-- The behavioral model has three parts:
-- - The behavioral model for independent clocks FIFOs (_as)
-- - The behavioral model for common clock FIFOs (_ss)
-- - The "preload logic" block which implements First-word Fall-through
--
-------------------------------------------------------------------------------
--#############################################################################
--#############################################################################
-- Independent Clocks FIFO Behavioral Model
--#############################################################################
--#############################################################################
-------------------------------------------------------------------------------
-- Library Declaration
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
-------------------------------------------------------------------------------
-- Independent Clocks Entity Declaration - This is NOT the top-level entity
-------------------------------------------------------------------------------
ENTITY fifo_generator_v13_0_1_bhv_as IS
GENERIC (
---------------------------------------------------------------------------
-- Generic Declarations
---------------------------------------------------------------------------
C_FAMILY : string := "virtex7";
C_DIN_WIDTH : integer := 8;
C_DOUT_RST_VAL : string := "";
C_DOUT_WIDTH : integer := 8;
C_FULL_FLAGS_RST_VAL : integer := 1;
C_HAS_ALMOST_EMPTY : integer := 0;
C_HAS_ALMOST_FULL : integer := 0;
C_HAS_OVERFLOW : integer := 0;
C_HAS_RD_DATA_COUNT : integer := 2;
C_HAS_RST : integer := 1;
C_HAS_UNDERFLOW : integer := 0;
C_HAS_VALID : integer := 0;
C_HAS_WR_ACK : integer := 0;
C_HAS_WR_DATA_COUNT : integer := 2;
C_MEMORY_TYPE : integer := 1;
C_OVERFLOW_LOW : integer := 0;
C_PRELOAD_LATENCY : integer := 1;
C_PRELOAD_REGS : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL : integer := 0;
C_PROG_EMPTY_THRESH_NEGATE_VAL : integer := 0;
C_PROG_EMPTY_TYPE : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL : integer := 0;
C_PROG_FULL_THRESH_NEGATE_VAL : integer := 0;
C_PROG_FULL_TYPE : integer := 0;
C_RD_DATA_COUNT_WIDTH : integer := 0;
C_RD_DEPTH : integer := 256;
C_RD_PNTR_WIDTH : integer := 8;
C_UNDERFLOW_LOW : integer := 0;
C_USE_DOUT_RST : integer := 0;
C_USE_ECC : integer := 0;
C_EN_SAFETY_CKT : integer := 0;
C_USE_EMBEDDED_REG : integer := 0;
C_USE_FWFT_DATA_COUNT : integer := 0;
C_VALID_LOW : integer := 0;
C_WR_ACK_LOW : integer := 0;
C_WR_DATA_COUNT_WIDTH : integer := 0;
C_WR_DEPTH : integer := 256;
C_WR_PNTR_WIDTH : integer := 8;
C_TCQ : time := 100 ps;
C_ENABLE_RST_SYNC : integer := 1;
C_ERROR_INJECTION_TYPE : integer := 0;
C_FIFO_TYPE : integer := 0;
C_SYNCHRONIZER_STAGE : integer := 2
);
PORT(
---------------------------------------------------------------------------
-- Input and Output Declarations
---------------------------------------------------------------------------
RST : IN std_logic;
RST_FULL_GEN : IN std_logic := '0';
RST_FULL_FF : IN std_logic := '0';
WR_RST : IN std_logic;
RD_RST : IN std_logic;
DIN : IN std_logic_vector(C_DIN_WIDTH-1 DOWNTO 0);
RD_CLK : IN std_logic;
RD_EN : IN std_logic;
RD_EN_USER : IN std_logic;
WR_CLK : IN std_logic;
WR_EN : IN std_logic;
PROG_EMPTY_THRESH : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0);
PROG_EMPTY_THRESH_ASSERT : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0);
PROG_EMPTY_THRESH_NEGATE : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0);
PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0);
PROG_FULL_THRESH_ASSERT : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0);
PROG_FULL_THRESH_NEGATE : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0);
INJECTDBITERR : IN std_logic := '0';
INJECTSBITERR : IN std_logic := '0';
USER_EMPTY_FB : IN std_logic := '1';
EMPTY : OUT std_logic := '1';
FULL : OUT std_logic := '0';
ALMOST_EMPTY : OUT std_logic := '1';
ALMOST_FULL : OUT std_logic := '0';
PROG_EMPTY : OUT std_logic := '1';
PROG_FULL : OUT std_logic := '0';
DOUT : OUT std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
VALID : OUT std_logic := '0';
WR_ACK : OUT std_logic := '0';
UNDERFLOW : OUT std_logic := '0';
OVERFLOW : OUT std_logic := '0';
RD_DATA_COUNT : OUT std_logic_vector(C_RD_DATA_COUNT_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
WR_DATA_COUNT : OUT std_logic_vector(C_WR_DATA_COUNT_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
SBITERR : OUT std_logic := '0';
DBITERR : OUT std_logic := '0'
);
END fifo_generator_v13_0_1_bhv_as;
-------------------------------------------------------------------------------
-- Architecture Heading
-------------------------------------------------------------------------------
ARCHITECTURE behavioral OF fifo_generator_v13_0_1_bhv_as IS
-----------------------------------------------------------------------------
-- FUNCTION actual_fifo_depth
-- Returns the actual depth of the FIFO (may differ from what the user
-- specified)
--
-- The FIFO depth is always represented as 2^n (16,32,64,128,256)
-- However, the ACTUAL fifo depth may be 2^n+1 or 2^n-1 depending on certain
-- options. This function returns the actual depth of the fifo, as seen by
-- the user.
-------------------------------------------------------------------------------
FUNCTION actual_fifo_depth(
C_FIFO_DEPTH : integer;
C_PRELOAD_REGS : integer;
C_PRELOAD_LATENCY : integer)
RETURN integer IS
BEGIN
RETURN C_FIFO_DEPTH - 1;
END actual_fifo_depth;
-----------------------------------------------------------------------------
-- FUNCTION div_roundup
-- Returns data_value / divisor, with the result rounded-up (if fractional)
-------------------------------------------------------------------------------
FUNCTION divroundup (
data_value : integer;
divisor : integer)
RETURN integer IS
VARIABLE div : integer;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
-----------------------------------------------------------------------------
-- FUNCTION int_2_std_logic
-- Returns a single bit (as std_logic) from an integer 1/0 value.
-------------------------------------------------------------------------------
FUNCTION int_2_std_logic(value : integer) RETURN std_logic IS
BEGIN
IF (value=1) THEN
RETURN '1';
ELSE
RETURN '0';
END IF;
END int_2_std_logic;
-----------------------------------------------------------------------------
-- FUNCTION if_then_else
-- Returns a true case or flase case based on the condition
-------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : boolean;
true_case : integer;
false_case : integer)
RETURN integer IS
VARIABLE retval : integer := 0;
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
FUNCTION if_then_else (
condition : boolean;
true_case : std_logic;
false_case : std_logic)
RETURN std_logic IS
VARIABLE retval : std_logic := '0';
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-----------------------------------------------------------------------------
-- FUNCTION hexstr_to_std_logic_vec
-- Returns a std_logic_vector for a hexadecimal string
-------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
-----------------------------------------------------------------------------
-- FUNCTION get_lesser
-- Returns a minimum value
-------------------------------------------------------------------------------
FUNCTION get_lesser(a: INTEGER; b: INTEGER) RETURN INTEGER IS
BEGIN
IF (a < b) THEN
RETURN a;
ELSE
RETURN b;
END IF;
END FUNCTION;
-----------------------------------------------------------------------------
-- Derived Constants
-----------------------------------------------------------------------------
CONSTANT C_FIFO_WR_DEPTH : integer
:= actual_fifo_depth(C_WR_DEPTH, C_PRELOAD_REGS, C_PRELOAD_LATENCY);
CONSTANT C_FIFO_RD_DEPTH : integer
:= actual_fifo_depth(C_RD_DEPTH, C_PRELOAD_REGS, C_PRELOAD_LATENCY);
CONSTANT C_SMALLER_DATA_WIDTH : integer
:= get_lesser(C_DIN_WIDTH, C_DOUT_WIDTH);
CONSTANT C_DEPTH_RATIO_WR : integer
:= if_then_else( (C_WR_DEPTH > C_RD_DEPTH), (C_WR_DEPTH/C_RD_DEPTH), 1);
CONSTANT C_DEPTH_RATIO_RD : integer
:= if_then_else( (C_RD_DEPTH > C_WR_DEPTH), (C_RD_DEPTH/C_WR_DEPTH), 1);
-- "Extra Words" is the number of write words which fit into the two
-- first-word fall-through output register stages (if using FWFT).
-- For ratios of 1:4 and 1:8, the fractional result is rounded up to 1.
-- This value is used to calculate the adjusted PROG_FULL threshold
-- value for FWFT.
-- EXTRA_WORDS = 2 * C_DEPTH_RATIO_WR / C_DEPTH_RATIO_RD
-- WR_DEPTH : RD_DEPTH = 1:2 => EXTRA_WORDS = 1
-- WR_DEPTH : RD_DEPTH = 1:4 => EXTRA_WORDS = 1 (rounded to ceiling)
-- WR_DEPTH : RD_DEPTH = 2:1 => EXTRA_WORDS = 4
-- WR_DEPTH : RD_DEPTH = 4:1 => EXTRA_WORDS = 8
CONSTANT EXTRA_WORDS : integer := divroundup(2 * C_DEPTH_RATIO_WR, C_DEPTH_RATIO_RD);
-- "Extra words dc" is used for calculating the adjusted WR_DATA_COUNT
-- value for the core when using FWFT.
-- extra_words_dc = 2 * C_DEPTH_RATIO_WR / C_DEPTH_RATIO_RD
-- C_DEPTH_RATIO_WR | C_DEPTH_RATIO_RD | C_PNTR_WIDTH | EXTRA_WORDS_DC
-- -----------------|------------------|-----------------|---------------
-- 1 | 8 | C_RD_PNTR_WIDTH | 2
-- 1 | 4 | C_RD_PNTR_WIDTH | 2
-- 1 | 2 | C_RD_PNTR_WIDTH | 2
-- 1 | 1 | C_WR_PNTR_WIDTH | 2
-- 2 | 1 | C_WR_PNTR_WIDTH | 4
-- 4 | 1 | C_WR_PNTR_WIDTH | 8
-- 8 | 1 | C_WR_PNTR_WIDTH | 16
CONSTANT EXTRA_WORDS_DC : integer
:= if_then_else ((C_DEPTH_RATIO_WR = 1),2,
(2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD));
CONSTANT C_PE_THR_ASSERT_ADJUSTED : integer
:=if_then_else((C_PRELOAD_REGS=1 and C_PRELOAD_LATENCY=0),
C_PROG_EMPTY_THRESH_ASSERT_VAL - 2, --FWFT
C_PROG_EMPTY_THRESH_ASSERT_VAL ); --NO FWFT
CONSTANT C_PE_THR_NEGATE_ADJUSTED : integer
:=if_then_else((C_PRELOAD_REGS=1 and C_PRELOAD_LATENCY=0),
C_PROG_EMPTY_THRESH_NEGATE_VAL - 2, --FWFT
C_PROG_EMPTY_THRESH_NEGATE_VAL); --NO FWFT
CONSTANT C_PE_THR_ASSERT_VAL_I : integer := C_PE_THR_ASSERT_ADJUSTED;
CONSTANT C_PE_THR_NEGATE_VAL_I : integer := C_PE_THR_NEGATE_ADJUSTED;
CONSTANT C_PF_THR_ASSERT_ADJUSTED : integer
:=if_then_else((C_PRELOAD_REGS=1 and C_PRELOAD_LATENCY=0),
C_PROG_FULL_THRESH_ASSERT_VAL - EXTRA_WORDS_DC, --FWFT
C_PROG_FULL_THRESH_ASSERT_VAL ); --NO FWFT
CONSTANT C_PF_THR_NEGATE_ADJUSTED : integer
:=if_then_else((C_PRELOAD_REGS=1 and C_PRELOAD_LATENCY=0),
C_PROG_FULL_THRESH_NEGATE_VAL - EXTRA_WORDS_DC, --FWFT
C_PROG_FULL_THRESH_NEGATE_VAL); --NO FWFT
-- NO_ERR_INJECTION will be 1 if ECC is OFF or ECC is ON but no error
-- injection is selected.
CONSTANT NO_ERR_INJECTION : integer
:= if_then_else(C_USE_ECC = 0,1,
if_then_else(C_ERROR_INJECTION_TYPE = 0,1,0));
-- SBIT_ERR_INJECTION will be 1 if ECC is ON and single bit error injection
-- is selected.
CONSTANT SBIT_ERR_INJECTION : integer
:= if_then_else((C_USE_ECC > 0 AND C_ERROR_INJECTION_TYPE = 1),1,0);
-- DBIT_ERR_INJECTION will be 1 if ECC is ON and double bit error injection
-- is selected.
CONSTANT DBIT_ERR_INJECTION : integer
:= if_then_else((C_USE_ECC > 0 AND C_ERROR_INJECTION_TYPE = 2),1,0);
-- BOTH_ERR_INJECTION will be 1 if ECC is ON and both single and double bit
-- error injection are selected.
CONSTANT BOTH_ERR_INJECTION : integer
:= if_then_else((C_USE_ECC > 0 AND C_ERROR_INJECTION_TYPE = 3),1,0);
CONSTANT C_DATA_WIDTH : integer := if_then_else(NO_ERR_INJECTION = 1, C_DIN_WIDTH, C_DIN_WIDTH+2);
CONSTANT OF_INIT_VAL : std_logic := if_then_else((C_HAS_OVERFLOW = 1 AND C_OVERFLOW_LOW = 1),'1','0');
CONSTANT UF_INIT_VAL : std_logic := if_then_else((C_HAS_UNDERFLOW = 1 AND C_UNDERFLOW_LOW = 1),'1','0');
TYPE wr_sync_array IS ARRAY (C_SYNCHRONIZER_STAGE-1 DOWNTO 0) OF std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0);
TYPE rd_sync_array IS ARRAY (C_SYNCHRONIZER_STAGE-1 DOWNTO 0) OF std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0);
SIGNAL wr_pntr_q : wr_sync_array := (OTHERS => (OTHERS => '0'));
SIGNAL rd_pntr_q : rd_sync_array := (OTHERS => (OTHERS => '0'));
-------------------------------------------------------------------------------
-- Signals Declaration
-------------------------------------------------------------------------------
SIGNAL wr_point : integer := 0;
SIGNAL rd_point : integer := 0;
SIGNAL wr_point_d1 : integer := 0;
SIGNAL rd_point_d1 : integer := 0;
SIGNAL num_wr_words : integer := 0;
SIGNAL num_rd_words : integer := 0;
SIGNAL adj_wr_point : integer := 0;
SIGNAL adj_rd_point : integer := 0;
SIGNAL adj_wr_point_d1: integer := 0;
SIGNAL adj_rd_point_d1: integer := 0;
SIGNAL wr_rst_i : std_logic := '0';
SIGNAL rd_rst_i : std_logic := '0';
SIGNAL wr_rst_d1 : std_logic := '0';
SIGNAL wr_ack_i : std_logic := '0';
SIGNAL overflow_i : std_logic := OF_INIT_VAL;
SIGNAL valid_i : std_logic := '0';
SIGNAL valid_d1 : std_logic := '0';
SIGNAL valid_out : std_logic := '0';
SIGNAL underflow_i : std_logic := UF_INIT_VAL;
SIGNAL prog_full_reg : std_logic := '0';
SIGNAL prog_empty_reg : std_logic := '1';
SIGNAL dout_i : std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
SIGNAL width_gt1 : std_logic := '0';
SIGNAL sbiterr_i : std_logic := '0';
SIGNAL dbiterr_i : std_logic := '0';
SIGNAL wr_pntr : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL wr_pntr_rd1 : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL wr_pntr_rd2 : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL wr_pntr_rd3 : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL wr_pntr_rd : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL adj_wr_pntr_rd : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL wr_data_count_int : std_logic_vector(C_WR_PNTR_WIDTH DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL wdc_fwft_ext_as : std_logic_vector(C_WR_PNTR_WIDTH DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL rdc_fwft_ext_as : std_logic_vector (C_RD_PNTR_WIDTH DOWNTO 0)
:= (OTHERS => '0');
SIGNAL rd_pntr : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL rd_pntr_wr_d1 : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL rd_pntr_wr_d2 : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL rd_pntr_wr_d3 : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL rd_pntr_wr_d4 : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL rd_pntr_wr : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL adj_rd_pntr_wr : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL rd_data_count_int : std_logic_vector(C_RD_PNTR_WIDTH DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL empty_int : boolean := TRUE;
SIGNAL empty_comb : std_logic := '1';
SIGNAL ram_rd_en : std_logic := '0';
SIGNAL ram_rd_en_d1 : std_logic := '0';
SIGNAL empty_comb_d1 : std_logic := '1';
SIGNAL almost_empty_int : boolean := TRUE;
SIGNAL full_int : boolean := FALSE;
SIGNAL full_comb : std_logic := int_2_std_logic(C_FULL_FLAGS_RST_VAL);
SIGNAL ram_wr_en : std_logic := '0';
SIGNAL almost_full_int : boolean := FALSE;
SIGNAL rd_fwft_cnt : std_logic_vector(3 downto 0) := (others=>'0');
SIGNAL stage1_valid : std_logic := '0';
SIGNAL stage2_valid : std_logic := '0';
SIGNAL diff_pntr_wr : integer := 0;
SIGNAL diff_pntr_rd : integer := 0;
SIGNAL pf_input_thr_assert_val : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS=>'0');
SIGNAL pf_input_thr_negate_val : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS=>'0');
-------------------------------------------------------------------------------
--Linked List types
-------------------------------------------------------------------------------
TYPE listtyp;
TYPE listptr IS ACCESS listtyp;
TYPE listtyp IS RECORD
data : std_logic_vector(C_SMALLER_DATA_WIDTH + 1 DOWNTO 0);
older : listptr;
newer : listptr;
END RECORD;
-------------------------------------------------------------------------------
--Processes for linked list implementation. The functions are
--1. "newlist" - Create a new linked list
--2. "add" - Add a data element to a linked list
--3. "read" - Read the data from the tail of the linked list
--4. "remove" - Remove the tail from the linked list
--5. "sizeof" - Calculate the size of the linked list
-------------------------------------------------------------------------------
--1. Create a new linked list
PROCEDURE newlist (
head : INOUT listptr;
tail : INOUT listptr;
cntr : INOUT integer) IS
BEGIN
head := NULL;
tail := NULL;
cntr := 0;
END;
--2. Add a data element to a linked list
PROCEDURE add (
head : INOUT listptr;
tail : INOUT listptr;
data : IN std_logic_vector;
cntr : INOUT integer;
inj_err : IN std_logic_vector(2 DOWNTO 0)
) IS
VARIABLE oldhead : listptr;
VARIABLE newhead : listptr;
VARIABLE corrupted_data : std_logic_vector(1 DOWNTO 0);
BEGIN
--------------------------------------------------------------------------
--a. Create a pointer to the existing head, if applicable
--b. Create a new node for the list
--c. Make the new node point to the old head
--d. Make the old head point back to the new node (for doubly-linked list)
--e. Put the data into the new head node
--f. If the new head we just created is the only node in the list,
-- make the tail point to it
--g. Return the new head pointer
--------------------------------------------------------------------------
IF (head /= NULL) THEN
oldhead := head;
END IF;
newhead := NEW listtyp;
newhead.older := oldhead;
IF (head /= NULL) THEN
oldhead.newer := newhead;
END IF;
CASE inj_err(1 DOWNTO 0) IS
-- For both error injection, pass only the double bit error injection
-- as dbit error has priority over single bit error injection
WHEN "11" => newhead.data := inj_err(1) & '0' & data;
WHEN "10" => newhead.data := inj_err(1) & '0' & data;
WHEN "01" => newhead.data := '0' & inj_err(0) & data;
WHEN OTHERS => newhead.data := '0' & '0' & data;
END CASE;
-- Increment the counter when data is added to the list
cntr := cntr + 1;
IF (newhead.older = NULL) THEN
tail := newhead;
END IF;
head := newhead;
END;
--3. Read the data from the tail of the linked list
PROCEDURE read (
tail : INOUT listptr;
data : OUT std_logic_vector;
err_type : OUT std_logic_vector(1 DOWNTO 0)
) IS
VARIABLE data_int : std_logic_vector(C_SMALLER_DATA_WIDTH + 1 DOWNTO 0) := (OTHERS => '0');
VARIABLE err_type_int : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
BEGIN
data_int := tail.data;
-- MSB two bits carry the error injection type.
err_type_int := data_int(data_int'high DOWNTO C_SMALLER_DATA_WIDTH);
IF (err_type_int(1) = '0') THEN
data := data_int(C_SMALLER_DATA_WIDTH - 1 DOWNTO 0);
ELSIF (C_DOUT_WIDTH = 2) THEN
data := NOT data_int(C_SMALLER_DATA_WIDTH - 1 DOWNTO 0);
ELSIF (C_DOUT_WIDTH > 2) THEN
data := NOT data_int(data_int'high-2) & NOT data_int(data_int'high-3) &
data_int(data_int'high-4 DOWNTO 0);
ELSE
data := data_int(C_SMALLER_DATA_WIDTH - 1 DOWNTO 0);
END IF;
err_type := err_type_int;
END;
--4. Remove the tail from the linked list
PROCEDURE remove (
head : INOUT listptr;
tail : INOUT listptr;
cntr : INOUT integer) IS
VARIABLE oldtail : listptr;
VARIABLE newtail : listptr;
BEGIN
--------------------------------------------------------------------------
--Make a copy of the old tail pointer
--a. If there is no newer node, then set the tail pointer to nothing
-- (list is empty)
-- otherwise, make the next newer node the new tail, and make it point
-- to nothing older
--b. Clean up the memory for the old tail node
--c. If the new tail is nothing, then we have an empty list, and head
-- should also be set to nothing
--d. Return the new tail
--------------------------------------------------------------------------
oldtail := tail;
IF (oldtail.newer = NULL) THEN
newtail := NULL;
ELSE
newtail := oldtail.newer;
newtail.older := NULL;
END IF;
DEALLOCATE(oldtail);
IF (newtail = NULL) THEN
head := NULL;
END IF;
tail := newtail;
-- Decrement the counter when data is removed from the list
cntr := cntr - 1;
END;
--5. Calculate the size of the linked list
PROCEDURE sizeof (head : INOUT listptr; size : OUT integer) IS
VARIABLE curlink : listptr;
VARIABLE tmpsize : integer := 0;
BEGIN
--------------------------------------------------------------------------
--a. If head is null, then there is nothing in the list to traverse
-- start with the head node (which implies at least one node exists)
-- Loop through each node until you find the one that points to nothing
-- (the tail)
--b. Return the number of nodes
--------------------------------------------------------------------------
IF (head /= NULL) THEN
curlink := head;
tmpsize := 1;
WHILE (curlink.older /= NULL) LOOP
tmpsize := tmpsize + 1;
curlink := curlink.older;
END LOOP;
END IF;
size := tmpsize;
END;
-----------------------------------------------------------------------------
-- converts integer to specified length std_logic_vector : dropping least
-- significant bits if integer is bigger than what can be represented by
-- the vector
-----------------------------------------------------------------------------
FUNCTION count(
fifo_count : IN integer;
pointer_width : IN integer;
counter_width : IN integer)
RETURN std_logic_vector IS
VARIABLE temp : std_logic_vector(pointer_width-1 DOWNTO 0)
:= (OTHERS => '0');
VARIABLE output : std_logic_vector(counter_width - 1 DOWNTO 0)
:= (OTHERS => '0');
BEGIN
temp := CONV_STD_LOGIC_VECTOR(fifo_count, pointer_width);
IF (counter_width <= pointer_width) THEN
output := temp(pointer_width - 1 DOWNTO pointer_width - counter_width);
ELSE
output := temp(counter_width - 1 DOWNTO 0);
END IF;
RETURN output;
END count;
-------------------------------------------------------------------------------
-- architecture begins here
-------------------------------------------------------------------------------
BEGIN
-------------------------------------------------------------------------------
-- Asynchronous FIFO
-------------------------------------------------------------------------------
gnll_afifo: IF (C_FIFO_TYPE /= 3) GENERATE
wr_pntr <= conv_std_logic_vector(wr_point,C_WR_PNTR_WIDTH);
rd_pntr <= conv_std_logic_vector(rd_point,C_RD_PNTR_WIDTH);
wr_rst_i <= WR_RST;
rd_rst_i <= RD_RST;
-------------------------------------------------------------------------------
-- calculate number of words in wr and rd domain according to the deepest port
--
-- These steps circumvent the linked-list data structure and keep track of
-- wr_point and rd_point pointers much like the core itself does. The behavioral
-- model uses these to calculate WR_DATA_COUNT and RD_DATA_COUNT. This was done
-- because the sizeof() function always returns the exact number of words in
-- the linked list, and can not account for delays when crossing clock domains.
-------------------------------------------------------------------------------
adj_wr_point <= wr_point * C_DEPTH_RATIO_RD;
adj_rd_point <= rd_point * C_DEPTH_RATIO_WR;
adj_wr_point_d1<= wr_point_d1 * C_DEPTH_RATIO_RD;
adj_rd_point_d1<= rd_point_d1 * C_DEPTH_RATIO_WR;
width_gt1 <= '1' WHEN (C_DIN_WIDTH = 2) ELSE '0';
PROCESS (adj_wr_point, adj_wr_point_d1, adj_rd_point, adj_rd_point_d1)
BEGIN
IF (adj_wr_point >= adj_rd_point_d1) THEN
num_wr_words <= adj_wr_point - adj_rd_point_d1;
ELSE
num_wr_words <= C_WR_DEPTH*C_DEPTH_RATIO_RD + adj_wr_point - adj_rd_point_d1;
END IF;
IF (adj_wr_point_d1 >= adj_rd_point) THEN
num_rd_words <= adj_wr_point_d1 - adj_rd_point;
ELSE
num_rd_words <= C_RD_DEPTH*C_DEPTH_RATIO_WR + adj_wr_point_d1 - adj_rd_point;
END IF;
END PROCESS;
-------------------------------------------------------------------------------
--Calculate WR_ACK based on C_WR_ACK_LOW parameters
-------------------------------------------------------------------------------
gwalow : IF (C_WR_ACK_LOW = 0) GENERATE
WR_ACK <= wr_ack_i;
END GENERATE gwalow;
gwahgh : IF (C_WR_ACK_LOW = 1) GENERATE
WR_ACK <= NOT wr_ack_i;
END GENERATE gwahgh;
-------------------------------------------------------------------------------
--Calculate OVERFLOW based on C_OVERFLOW_LOW parameters
-------------------------------------------------------------------------------
govlow : IF (C_OVERFLOW_LOW = 0) GENERATE
OVERFLOW <= overflow_i;
END GENERATE govlow;
govhgh : IF (C_OVERFLOW_LOW = 1) GENERATE
OVERFLOW <= NOT overflow_i;
END GENERATE govhgh;
-------------------------------------------------------------------------------
--Calculate VALID based on C_VALID_LOW
-------------------------------------------------------------------------------
gnvl : IF (C_VALID_LOW = 0) GENERATE
VALID <= valid_out;
END GENERATE gnvl;
gnvh : IF (C_VALID_LOW = 1) GENERATE
VALID <= NOT valid_out;
END GENERATE gnvh;
-------------------------------------------------------------------------------
--Calculate UNDERFLOW based on C_UNDERFLOW_LOW
-------------------------------------------------------------------------------
gnul : IF (C_UNDERFLOW_LOW = 0) GENERATE
UNDERFLOW <= underflow_i;
END GENERATE gnul;
gnuh : IF (C_UNDERFLOW_LOW = 1) GENERATE
UNDERFLOW <= NOT underflow_i;
END GENERATE gnuh;
-------------------------------------------------------------------------------
--Assign PROG_FULL and PROG_EMPTY
-------------------------------------------------------------------------------
PROG_FULL <= prog_full_reg;
PROG_EMPTY <= prog_empty_reg;
-------------------------------------------------------------------------------
--Assign RD_DATA_COUNT and WR_DATA_COUNT
-------------------------------------------------------------------------------
rdc: IF (C_HAS_RD_DATA_COUNT=1) GENERATE
grdc_fwft_ext: IF (C_USE_FWFT_DATA_COUNT = 1) GENERATE
RD_DATA_COUNT <= rdc_fwft_ext_as(C_RD_PNTR_WIDTH DOWNTO C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH);
END GENERATE grdc_fwft_ext;
gnrdc_fwft_ext: IF (C_USE_FWFT_DATA_COUNT = 0) GENERATE
RD_DATA_COUNT <= rd_data_count_int(C_RD_PNTR_WIDTH DOWNTO C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH);
END GENERATE gnrdc_fwft_ext;
END GENERATE rdc;
nrdc: IF (C_HAS_RD_DATA_COUNT=0) GENERATE
RD_DATA_COUNT <= (OTHERS=>'0');
END GENERATE nrdc;
wdc: IF (C_HAS_WR_DATA_COUNT = 1) GENERATE
gwdc_fwft_ext: IF (C_USE_FWFT_DATA_COUNT = 1) GENERATE
WR_DATA_COUNT <= wdc_fwft_ext_as(C_WR_PNTR_WIDTH DOWNTO C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH);
END GENERATE gwdc_fwft_ext;
gnwdc_fwft_ext: IF (C_USE_FWFT_DATA_COUNT = 0) GENERATE
WR_DATA_COUNT <= wr_data_count_int(C_WR_PNTR_WIDTH DOWNTO C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH);
END GENERATE gnwdc_fwft_ext;
END GENERATE wdc;
nwdc: IF (C_HAS_WR_DATA_COUNT=0) GENERATE
WR_DATA_COUNT <= (OTHERS=>'0');
END GENERATE nwdc;
-------------------------------------------------------------------------------
-- Write data count calculation if Use Extra Logic option is used
-------------------------------------------------------------------------------
wdc_fwft_ext: IF (C_HAS_WR_DATA_COUNT = 1 AND C_USE_FWFT_DATA_COUNT = 1) GENERATE
CONSTANT C_PNTR_WIDTH : integer
:= if_then_else ((C_WR_PNTR_WIDTH>=C_RD_PNTR_WIDTH),
C_WR_PNTR_WIDTH, C_RD_PNTR_WIDTH);
SIGNAL adjusted_wr_pntr : std_logic_vector (C_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
SIGNAL adjusted_rd_pntr : std_logic_vector (C_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
CONSTANT EXTRA_WORDS : std_logic_vector (C_PNTR_WIDTH DOWNTO 0)
:= conv_std_logic_vector(
if_then_else ((C_DEPTH_RATIO_WR=1),2
,(2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD))
,C_PNTR_WIDTH+1);
SIGNAL diff_wr_rd_tmp : std_logic_vector (C_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
SIGNAL diff_wr_rd : std_logic_vector (C_PNTR_WIDTH DOWNTO 0)
:= (OTHERS => '0');
SIGNAL wr_data_count_i : std_logic_vector (C_PNTR_WIDTH DOWNTO 0)
:= (OTHERS => '0');
BEGIN
-----------------------------------------------------------------------------
--Adjust write and read pointer to the deepest port width
-----------------------------------------------------------------------------
--C_PNTR_WIDTH=C_WR_PNTR_WIDTH
gpadr: IF (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) GENERATE
adjusted_wr_pntr <= wr_pntr;
adjusted_rd_pntr(C_PNTR_WIDTH-1 DOWNTO C_PNTR_WIDTH-C_RD_PNTR_WIDTH)
<= rd_pntr_wr;
adjusted_rd_pntr(C_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 DOWNTO 0)<=(OTHERS=>'0');
END GENERATE gpadr;
--C_PNTR_WIDTH=C_RD_PNTR_WIDTH
gpadw: IF (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) GENERATE
adjusted_wr_pntr(C_PNTR_WIDTH-1 DOWNTO C_PNTR_WIDTH-C_WR_PNTR_WIDTH)
<= wr_pntr;
adjusted_wr_pntr(C_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 DOWNTO 0)<=(OTHERS=>'0');
adjusted_rd_pntr <= rd_pntr_wr;
END GENERATE gpadw;
--C_PNTR_WIDTH=C_WR_PNTR_WIDTH=C_RD_PNTR_WIDTH
ngpad: IF (C_WR_PNTR_WIDTH = C_RD_PNTR_WIDTH) GENERATE
adjusted_wr_pntr <= wr_pntr;
adjusted_rd_pntr <= rd_pntr_wr;
END GENERATE ngpad;
-----------------------------------------------------------------------------
--Calculate words in write domain
-----------------------------------------------------------------------------
--Subtract the pointers to get the number of words in the RAM, *THEN* pad
--the result
diff_wr_rd_tmp <= adjusted_wr_pntr - adjusted_rd_pntr;
diff_wr_rd <= '0' & diff_wr_rd_tmp;
pwdc : PROCESS (WR_CLK, wr_rst_i)
BEGIN
IF (wr_rst_i = '1') THEN
wr_data_count_i <= (OTHERS=>'0');
ELSIF (WR_CLK'event AND WR_CLK = '1') THEN
wr_data_count_i <= diff_wr_rd + extra_words;
END IF;
END PROCESS pwdc;
gdc0: IF (C_WR_PNTR_WIDTH >= C_RD_PNTR_WIDTH) GENERATE
wdc_fwft_ext_as
<= wr_data_count_i(C_PNTR_WIDTH DOWNTO 0);
END GENERATE gdc0;
gdc1: IF (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) GENERATE
wdc_fwft_ext_as
<= wr_data_count_i(C_PNTR_WIDTH DOWNTO C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH);
END GENERATE gdc1;
END GENERATE wdc_fwft_ext;
-------------------------------------------------------------------------------
-- Read data count calculation if Use Extra Logic option is used
-------------------------------------------------------------------------------
rdc_fwft_ext: IF (C_HAS_RD_DATA_COUNT = 1 AND C_USE_FWFT_DATA_COUNT = 1) GENERATE
SIGNAL diff_wr_rd_tmp : std_logic_vector (C_RD_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
SIGNAL diff_wr_rd : std_logic_vector (C_RD_PNTR_WIDTH DOWNTO 0)
:= (OTHERS => '0');
SIGNAL zero : std_logic_vector (C_RD_PNTR_WIDTH DOWNTO 0)
:= (OTHERS => '0');
SIGNAL one : std_logic_vector (C_RD_PNTR_WIDTH DOWNTO 0)
:= conv_std_logic_vector(1, C_RD_PNTR_WIDTH+1);
SIGNAL two : std_logic_vector (C_RD_PNTR_WIDTH DOWNTO 0)
:= conv_std_logic_vector(2, C_RD_PNTR_WIDTH+1);
SIGNAL adjusted_wr_pntr_r : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
BEGIN
----------------------------------------------------------------------------
-- If write depth is smaller than read depth, pad write pointer.
-- If write depth is bigger than read depth, trim write pointer.
----------------------------------------------------------------------------
gpad : IF (C_RD_PNTR_WIDTH>C_WR_PNTR_WIDTH) GENERATE
adjusted_wr_pntr_r(C_RD_PNTR_WIDTH-1 DOWNTO C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH)
<= WR_PNTR_RD;
adjusted_wr_pntr_r(C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 DOWNTO 0)
<= (OTHERS => '0');
END GENERATE gpad;
gtrim : IF (C_RD_PNTR_WIDTH<=C_WR_PNTR_WIDTH) GENERATE
adjusted_wr_pntr_r
<= WR_PNTR_RD(C_WR_PNTR_WIDTH-1 DOWNTO C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH);
END GENERATE gtrim;
-----------------------------------------------------------------------------
-- This accounts for preload 0 by explicitly handling the preload states
-- which do not have both output stages filled. As a result, the rd_data_count
-- produced will always accurately reflect the number of READABLE words at
-- a given time.
-----------------------------------------------------------------------------
diff_wr_rd_tmp <= adjusted_wr_pntr_r - RD_PNTR;
diff_wr_rd <= '0' & diff_wr_rd_tmp;
prdc : PROCESS (RD_CLK, rd_rst_i)
BEGIN
IF (rd_rst_i = '1') THEN
rdc_fwft_ext_as <= zero;
ELSIF (RD_CLK'event AND RD_CLK = '1') THEN
IF (stage2_valid = '0') THEN
rdc_fwft_ext_as <= zero;
ELSIF (stage2_valid = '1' AND stage1_valid = '0') THEN
rdc_fwft_ext_as <= one;
ELSE
rdc_fwft_ext_as <= diff_wr_rd + two;
END IF;
END IF;
END PROCESS prdc;
END GENERATE rdc_fwft_ext;
-------------------------------------------------------------------------------
-- Write pointer adjustment based on pointers width for EMPTY/ALMOST_EMPTY generation
-------------------------------------------------------------------------------
gpad : IF (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) GENERATE
adj_wr_pntr_rd(C_RD_PNTR_WIDTH-1 DOWNTO C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH)
<= wr_pntr_rd;
adj_wr_pntr_rd(C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 DOWNTO 0)
<= (OTHERS => '0');
END GENERATE gpad;
gtrim : IF (C_RD_PNTR_WIDTH<=C_WR_PNTR_WIDTH) GENERATE
adj_wr_pntr_rd
<= wr_pntr_rd(C_WR_PNTR_WIDTH-1 DOWNTO C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH);
END GENERATE gtrim;
-------------------------------------------------------------------------------
-- Generate Empty
-------------------------------------------------------------------------------
-- ram_rd_en used to determine EMPTY should depend on the EMPTY.
ram_rd_en <= RD_EN AND (NOT empty_comb);
empty_int <= ((adj_wr_pntr_rd = rd_pntr) OR (ram_rd_en = '1' AND
(adj_wr_pntr_rd = conv_std_logic_vector((conv_integer(rd_pntr)+1),C_RD_PNTR_WIDTH))));
-------------------------------------------------------------------------------
-- Generate Almost Empty
-------------------------------------------------------------------------------
almost_empty_int <= ((adj_wr_pntr_rd = conv_std_logic_vector((conv_integer(rd_pntr)+1),C_RD_PNTR_WIDTH)) OR (ram_rd_en = '1' AND
(adj_wr_pntr_rd = conv_std_logic_vector((conv_integer(rd_pntr)+2),C_RD_PNTR_WIDTH))));
-------------------------------------------------------------------------------
-- Registering Empty & Almost Empty
-- Generate read data count if Use Extra Logic is not selected.
-------------------------------------------------------------------------------
empty_proc : PROCESS (RD_CLK, rd_rst_i)
BEGIN
IF (rd_rst_i = '1') THEN
empty_comb <= '1' AFTER C_TCQ;
empty_comb_d1 <= '1' AFTER C_TCQ;
ALMOST_EMPTY <= '1' AFTER C_TCQ;
rd_data_count_int <= (OTHERS => '0') AFTER C_TCQ;
ELSIF (RD_CLK'event AND RD_CLK = '1') THEN
rd_data_count_int <= ((adj_wr_pntr_rd(C_RD_PNTR_WIDTH-1 DOWNTO 0) -
rd_pntr(C_RD_PNTR_WIDTH-1 DOWNTO 0)) & '0') AFTER C_TCQ;
empty_comb_d1 <= empty_comb AFTER C_TCQ;
IF (empty_int) THEN
empty_comb <= '1' AFTER C_TCQ;
ELSE
empty_comb <= '0' AFTER C_TCQ;
END IF;
IF (empty_comb = '0') THEN
IF (almost_empty_int) THEN
ALMOST_EMPTY <= '1' AFTER C_TCQ;
ELSE
ALMOST_EMPTY <= '0' AFTER C_TCQ;
END IF;
END IF;
END IF;
END PROCESS empty_proc;
-------------------------------------------------------------------------------
-- Read pointer adjustment based on pointers width for FULL/ALMOST_FULL generation
-------------------------------------------------------------------------------
gfpad : IF (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) GENERATE
adj_rd_pntr_wr
(C_WR_PNTR_WIDTH-1 DOWNTO C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH)
<= rd_pntr_wr;
adj_rd_pntr_wr(C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 DOWNTO 0)
<= (OTHERS => '0');
END GENERATE gfpad;
gftrim : IF (C_WR_PNTR_WIDTH <= C_RD_PNTR_WIDTH) GENERATE
adj_rd_pntr_wr
<= rd_pntr_wr(C_RD_PNTR_WIDTH-1 DOWNTO C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH);
END GENERATE gftrim;
-------------------------------------------------------------------------------
-- Generate Full
-------------------------------------------------------------------------------
-- ram_wr_en used to determine FULL should depend on the FULL.
ram_wr_en <= WR_EN AND (NOT full_comb);
full_int <= ((adj_rd_pntr_wr = conv_std_logic_vector((conv_integer(wr_pntr)+1),C_WR_PNTR_WIDTH)) OR (ram_wr_en = '1' AND
(adj_rd_pntr_wr = conv_std_logic_vector((conv_integer(wr_pntr)+2),C_WR_PNTR_WIDTH))));
-------------------------------------------------------------------------------
-- Generate Almost Full
-------------------------------------------------------------------------------
almost_full_int <= ((adj_rd_pntr_wr = conv_std_logic_vector((conv_integer(wr_pntr)+2),C_WR_PNTR_WIDTH)) OR (ram_wr_en = '1' AND
(adj_rd_pntr_wr = conv_std_logic_vector((conv_integer(wr_pntr)+3),C_WR_PNTR_WIDTH))));
-------------------------------------------------------------------------------
-- Registering Full & Almost Full
-- Generate write data count if Use Extra Logic is not selected.
-------------------------------------------------------------------------------
full_proc : PROCESS (WR_CLK, RST_FULL_FF)
BEGIN
IF (RST_FULL_FF = '1') THEN
full_comb <= int_2_std_logic(C_FULL_FLAGS_RST_VAL) AFTER C_TCQ;
ALMOST_FULL <= int_2_std_logic(C_FULL_FLAGS_RST_VAL) AFTER C_TCQ;
ELSIF (WR_CLK'event AND WR_CLK = '1') THEN
IF (full_int) THEN
full_comb <= '1' AFTER C_TCQ;
ELSE
full_comb <= '0' AFTER C_TCQ;
END IF;
IF (RST_FULL_GEN = '1') THEN
ALMOST_FULL <= '0' AFTER C_TCQ;
ELSIF (full_comb = '0') THEN
IF (almost_full_int) THEN
ALMOST_FULL <= '1' AFTER C_TCQ;
ELSE
ALMOST_FULL <= '0' AFTER C_TCQ;
END IF;
END IF;
END IF;
END PROCESS full_proc;
wdci_proc : PROCESS (WR_CLK, wr_rst_i)
BEGIN
IF (wr_rst_i = '1') THEN
wr_data_count_int <= (OTHERS => '0') AFTER C_TCQ;
ELSIF (WR_CLK'event AND WR_CLK = '1') THEN
wr_data_count_int <= ((wr_pntr(C_WR_PNTR_WIDTH-1 DOWNTO 0) -
adj_rd_pntr_wr(C_WR_PNTR_WIDTH-1 DOWNTO 0)) & '0') AFTER C_TCQ;
END IF;
END PROCESS wdci_proc;
-------------------------------------------------------------------------------
-- Counter that determines the FWFT read duration.
-------------------------------------------------------------------------------
-- C_PRELOAD_LATENCY will be 0 for Non-Built-in FIFO with FWFT.
grd_fwft: IF (C_PRELOAD_LATENCY = 0) GENERATE
SIGNAL user_empty_fb_d1 : std_logic := '1';
BEGIN
grd_fwft_proc : PROCESS (RD_CLK, rd_rst_i)
BEGIN
IF (rd_rst_i = '1') THEN
rd_fwft_cnt <= (others => '0');
user_empty_fb_d1 <= '1';
stage1_valid <= '0';
stage2_valid <= '0';
ELSIF (RD_CLK'event AND RD_CLK = '1') THEN
user_empty_fb_d1 <= USER_EMPTY_FB;
IF (user_empty_fb_d1 = '0' AND USER_EMPTY_FB = '1') THEN
rd_fwft_cnt <= (others => '0') AFTER C_TCQ;
ELSIF (empty_comb = '0') THEN
IF (RD_EN = '1' AND rd_fwft_cnt < X"5") THEN
rd_fwft_cnt <= rd_fwft_cnt + "1" AFTER C_TCQ;
END IF;
END IF;
IF (stage1_valid = '0' AND stage2_valid = '0') THEN
IF (empty_comb = '0') THEN
stage1_valid <= '1' AFTER C_TCQ;
ELSE
stage1_valid <= '0' AFTER C_TCQ;
END IF;
ELSIF (stage1_valid = '1' AND stage2_valid = '0') THEN
IF (empty_comb = '1') THEN
stage1_valid <= '0' AFTER C_TCQ;
stage2_valid <= '1' AFTER C_TCQ;
ELSE
stage1_valid <= '1' AFTER C_TCQ;
stage2_valid <= '1' AFTER C_TCQ;
END IF;
ELSIF (stage1_valid = '0' AND stage2_valid = '1') THEN
IF (empty_comb = '1' AND RD_EN_USER = '1') THEN
stage1_valid <= '0' AFTER C_TCQ;
stage2_valid <= '0' AFTER C_TCQ;
ELSIF (empty_comb = '0' AND RD_EN_USER = '1') THEN
stage1_valid <= '1' AFTER C_TCQ;
stage2_valid <= '0' AFTER C_TCQ;
ELSIF (empty_comb = '0' AND RD_EN_USER = '0') THEN
stage1_valid <= '1' AFTER C_TCQ;
stage2_valid <= '1' AFTER C_TCQ;
ELSE
stage1_valid <= '0' AFTER C_TCQ;
stage2_valid <= '1' AFTER C_TCQ;
END IF;
ELSIF (stage1_valid = '1' AND stage2_valid = '1') THEN
IF (empty_comb = '1' AND RD_EN_USER = '1') THEN
stage1_valid <= '0' AFTER C_TCQ;
stage2_valid <= '1' AFTER C_TCQ;
ELSE
stage1_valid <= '1' AFTER C_TCQ;
stage2_valid <= '1' AFTER C_TCQ;
END IF;
ELSE
stage1_valid <= '0' AFTER C_TCQ;
stage2_valid <= '0' AFTER C_TCQ;
END IF;
END IF;
END PROCESS grd_fwft_proc;
END GENERATE grd_fwft;
gnrd_fwft: IF (C_PRELOAD_LATENCY > 0) GENERATE
rd_fwft_cnt <= X"2";
END GENERATE gnrd_fwft;
-------------------------------------------------------------------------------
-- Assign FULL, EMPTY, ALMOST_FULL and ALMOST_EMPTY
-------------------------------------------------------------------------------
FULL <= full_comb;
EMPTY <= empty_comb;
-------------------------------------------------------------------------------
-- Asynchronous FIFO using linked lists
-------------------------------------------------------------------------------
FIFO_PROC : PROCESS (WR_CLK, RD_CLK, rd_rst_i, wr_rst_i)
--Declare the linked-list head/tail pointers and the size value
VARIABLE head : listptr;
VARIABLE tail : listptr;
VARIABLE size : integer := 0;
VARIABLE cntr : integer := 0;
VARIABLE cntr_size_var_int : integer := 0;
--Data is the internal version of the DOUT bus
VARIABLE data : std_logic_vector(c_dout_width - 1 DOWNTO 0)
:= hexstr_to_std_logic_vec( C_DOUT_RST_VAL, c_dout_width);
VARIABLE err_type : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
--Temporary values for calculating adjusted prog_empty/prog_full thresholds
VARIABLE prog_empty_actual_assert_thresh : integer := 0;
VARIABLE prog_empty_actual_negate_thresh : integer := 0;
VARIABLE prog_full_actual_assert_thresh : integer := 0;
VARIABLE prog_full_actual_negate_thresh : integer := 0;
VARIABLE diff_pntr : integer := 0;
BEGIN
-- Calculate the current contents of the FIFO (size)
-- Warning: This value should only be calculated once each time this
-- process is entered.
-- It is updated instantaneously for both write and read operations,
-- so it is not ideal to use for signals which must consider the
-- latency of crossing clock domains.
-- cntr_size_var_int is updated only once when the process is entered
-- This variable is used in the conditions instead of cntr which has the
-- latest value.
cntr_size_var_int := cntr;
-- RESET CONDITIONS
IF wr_rst_i = '1' THEN
wr_point <= 0 after C_TCQ;
wr_point_d1 <= 0 after C_TCQ;
wr_pntr_rd1 <= (OTHERS => '0') after C_TCQ;
rd_pntr_wr <= (OTHERS => '0') after C_TCQ;
rd_pntr_q <= (OTHERS => (OTHERS => '0')) after C_TCQ;
--Create new linked list
newlist(head, tail,cntr);
diff_pntr := 0;
---------------------------------------------------------------------------
-- Write to FIFO
---------------------------------------------------------------------------
ELSIF WR_CLK'event AND WR_CLK = '1' THEN
rd_pntr_q <= rd_pntr_q(C_SYNCHRONIZER_STAGE-2 downto 0) & rd_pntr_wr_d1;
-- Delay the write pointer before passing to RD_CLK domain to accommodate
-- the binary to gray converion
wr_pntr_rd1 <= wr_pntr after C_TCQ;
rd_pntr_wr <= rd_pntr_q(C_SYNCHRONIZER_STAGE-1) after C_TCQ;
wr_point_d1 <= wr_point after C_TCQ;
--The following IF statement setup default values of full_i and almost_full_i.
--The values might be overwritten in the next IF statement.
--If writing, then it is not possible to predict how many
--words will actually be in the FIFO after the write concludes
--(because the number of reads which happen in this time can
-- not be determined).
--Therefore, treat it pessimistically and always assume that
-- the write will happen without a read (assume the FIFO is
-- C_DEPTH_RATIO_RD fuller than it is).
--Note:
--1. cntr_size_var_int is the deepest depth between write depth and read depth
-- cntr_size_var_int/C_DEPTH_RATIO_RD is number of words in the write domain.
--2. cntr_size_var_int+C_DEPTH_RATIO_RD: number of write words in the next clock cycle
-- if wr_en=1 (C_DEPTH_RATIO_RD=one write word)
--3. For asymmetric FIFO, if write width is narrower than read width. Don't
-- have to consider partial words.
--4. For asymmetric FIFO, if read width is narrower than write width,
-- the worse case that FIFO is going to full is depicted in the following
-- diagram. Both rd_pntr_a and rd_pntr_b will cause FIFO full. rd_pntr_a
-- is the worse case. Therefore, in the calculation, actual FIFO depth is
-- substarcted to one write word and added one read word.
-- -------
-- | | |
-- wr_pntr-->| |---
-- | | |
-- ---|---
-- | | |
-- | |---
-- | | |
-- ---|---
-- | | |<--rd_pntr_a
-- | |---
-- | | |<--rd_pntr_b
-- ---|---
-- Update full_i and almost_full_i if user is writing to the FIFO.
-- Assign overflow and wr_ack.
IF WR_EN = '1' THEN
IF full_comb /= '1' THEN
-- User is writing to a FIFO which is NOT reporting FULL
IF cntr_size_var_int/C_DEPTH_RATIO_RD = C_FIFO_WR_DEPTH THEN
-- FIFO really is Full
--Report Overflow and do not acknowledge the write
ELSIF cntr_size_var_int/C_DEPTH_RATIO_RD + 1 = C_FIFO_WR_DEPTH THEN
-- FIFO is almost full
-- This write will succeed, and FIFO will go FULL
FOR h IN C_DEPTH_RATIO_RD DOWNTO 1 LOOP
add(head, tail,
DIN((C_SMALLER_DATA_WIDTH*h)-1 DOWNTO C_SMALLER_DATA_WIDTH*(h-1)),cntr,
(width_gt1 & INJECTDBITERR & INJECTSBITERR));
END LOOP;
wr_point <= (wr_point + 1) MOD C_WR_DEPTH after C_TCQ;
ELSIF cntr_size_var_int/C_DEPTH_RATIO_RD + 2 = C_FIFO_WR_DEPTH THEN
-- FIFO is one away from almost full
-- This write will succeed, and FIFO will go almost_full_i
FOR h IN C_DEPTH_RATIO_RD DOWNTO 1 LOOP
add(head, tail,
DIN((C_SMALLER_DATA_WIDTH*h)-1 DOWNTO C_SMALLER_DATA_WIDTH*(h-1)),cntr,
(width_gt1 & INJECTDBITERR & INJECTSBITERR));
END LOOP;
wr_point <= (wr_point + 1) MOD C_WR_DEPTH after C_TCQ;
ELSE
-- FIFO is no where near FULL
--Write will succeed, no change in status
FOR h IN C_DEPTH_RATIO_RD DOWNTO 1 LOOP
add(head, tail,
DIN((C_SMALLER_DATA_WIDTH*h)-1 DOWNTO C_SMALLER_DATA_WIDTH*(h-1)),cntr,
(width_gt1 & INJECTDBITERR & INJECTSBITERR));
END LOOP;
wr_point <= (wr_point + 1) MOD C_WR_DEPTH after C_TCQ;
END IF;
ELSE --IF full_i = '1'
-- User is writing to a FIFO which IS reporting FULL
--Write will fail
END IF; --full_i
ELSE --WR_EN/='1'
--No write attempted, so neither overflow or acknowledge
END IF; --WR_EN
END IF; --WR_CLK
---------------------------------------------------------------------------
-- Read from FIFO
---------------------------------------------------------------------------
IF rd_rst_i = '1' THEN
-- Whenever user is attempting to read from
-- an EMPTY FIFO, the core should report an underflow error, even if
-- the core is in a RESET condition.
rd_point <= 0 after C_TCQ;
rd_point_d1 <= 0 after C_TCQ;
rd_pntr_wr_d1 <= (OTHERS => '0') after C_TCQ;
wr_pntr_rd <= (OTHERS => '0') after C_TCQ;
wr_pntr_q <= (OTHERS => (OTHERS => '0')) after C_TCQ;
-- DRAM resets asynchronously
IF (C_MEMORY_TYPE = 2 AND C_USE_DOUT_RST = 1) THEN
data := hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH);
END IF;
-- BRAM resets synchronously
IF (C_MEMORY_TYPE < 2 AND C_USE_DOUT_RST = 1) THEN
IF (RD_CLK'event AND RD_CLK = '1') THEN
data := hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH);
END IF;
END IF;
-- Reset only if ECC is not selected as ECC does not support reset.
IF (C_USE_ECC = 0) THEN
err_type := (OTHERS => '0');
END IF ;
ELSIF RD_CLK'event AND RD_CLK = '1' THEN
wr_pntr_q <= wr_pntr_q(C_SYNCHRONIZER_STAGE-2 downto 0) & wr_pntr_rd1;
-- Delay the read pointer before passing to WR_CLK domain to accommodate
-- the binary to gray converion
rd_pntr_wr_d1 <= rd_pntr after C_TCQ;
wr_pntr_rd <= wr_pntr_q(C_SYNCHRONIZER_STAGE-1) after C_TCQ;
rd_point_d1 <= rd_point after C_TCQ;
---------------------------------------------------------------------------
-- Read Latency 1
---------------------------------------------------------------------------
--The following IF statement setup default values of empty_i and
--almost_empty_i. The values might be overwritten in the next IF statement.
--Note:
--cntr_size_var_int/C_DEPTH_RATIO_WR : number of words in read domain.
IF (ram_rd_en = '1') THEN
IF empty_comb /= '1' THEN
IF cntr_size_var_int/C_DEPTH_RATIO_WR = 2 THEN
--FIFO is going almost empty
FOR h IN C_DEPTH_RATIO_WR DOWNTO 1 LOOP
read(tail,
data((C_SMALLER_DATA_WIDTH*h)-1 DOWNTO C_SMALLER_DATA_WIDTH*(h-1)),
err_type);
remove(head, tail,cntr);
END LOOP;
rd_point <= (rd_point + 1) MOD C_RD_DEPTH after C_TCQ;
ELSIF cntr_size_var_int/C_DEPTH_RATIO_WR = 1 THEN
--FIFO is going empty
FOR h IN C_DEPTH_RATIO_WR DOWNTO 1 LOOP
read(tail,
data((C_SMALLER_DATA_WIDTH*h)-1 DOWNTO C_SMALLER_DATA_WIDTH*(h-1)),
err_type);
remove(head, tail,cntr);
END LOOP;
rd_point <= (rd_point + 1) MOD C_RD_DEPTH after C_TCQ;
ELSIF cntr_size_var_int/C_DEPTH_RATIO_WR = 0 THEN
--FIFO is empty
ELSE
--FIFO is not empty
FOR h IN C_DEPTH_RATIO_WR DOWNTO 1 LOOP
read(tail,
data((C_SMALLER_DATA_WIDTH*h)-1 DOWNTO C_SMALLER_DATA_WIDTH*(h-1)),
err_type);
remove(head, tail,cntr);
END LOOP;
rd_point <= (rd_point + 1) MOD C_RD_DEPTH after C_TCQ;
END IF;
ELSE
--FIFO is empty
END IF;
END IF; --RD_EN
END IF; --RD_CLK
dout_i <= data after C_TCQ;
sbiterr_i <= err_type(0) after C_TCQ;
dbiterr_i <= err_type(1) after C_TCQ;
END PROCESS;
-----------------------------------------------------------------------------
-- Programmable FULL flags
-----------------------------------------------------------------------------
proc_pf_input: PROCESS(PROG_FULL_THRESH, PROG_FULL_THRESH_ASSERT,PROG_FULL_THRESH_NEGATE)
BEGIN
IF (C_PRELOAD_REGS = 1 AND C_PRELOAD_LATENCY = 0) THEN -- FWFT
IF (C_PROG_FULL_TYPE = 3) THEN -- Single threshold input
pf_input_thr_assert_val <= PROG_FULL_THRESH - conv_integer(EXTRA_WORDS_DC);
ELSE -- Multiple threshold inputs
pf_input_thr_assert_val <= PROG_FULL_THRESH_ASSERT - conv_std_logic_vector(EXTRA_WORDS_DC,C_WR_PNTR_WIDTH);
pf_input_thr_negate_val <= PROG_FULL_THRESH_NEGATE - conv_std_logic_vector(EXTRA_WORDS_DC,C_WR_PNTR_WIDTH);
END IF;
ELSE -- STD
IF (C_PROG_FULL_TYPE = 3) THEN -- Single threshold input
pf_input_thr_assert_val <= PROG_FULL_THRESH;
ELSE -- Multiple threshold inputs
pf_input_thr_assert_val <= PROG_FULL_THRESH_ASSERT;
pf_input_thr_negate_val <= PROG_FULL_THRESH_NEGATE;
END IF;
END IF;
END PROCESS proc_pf_input;
proc_wdc: PROCESS(WR_CLK, wr_rst_i)
BEGIN
IF (wr_rst_i = '1') THEN
diff_pntr_wr <= 0;
ELSIF (WR_CLK'event AND WR_CLK = '1') THEN
IF (ram_wr_en = '0') THEN
diff_pntr_wr <= conv_integer(wr_pntr - adj_rd_pntr_wr) after C_TCQ;
ELSIF (ram_wr_en = '1') THEN
diff_pntr_wr <= conv_integer(wr_pntr - adj_rd_pntr_wr) + 1 after C_TCQ;
END IF;
END IF; -- WR_CLK
END PROCESS proc_wdc;
proc_pf: PROCESS(WR_CLK, RST_FULL_FF)
BEGIN
IF (RST_FULL_FF = '1') THEN
prog_full_reg <= int_2_std_logic(C_FULL_FLAGS_RST_VAL);
ELSIF (WR_CLK'event AND WR_CLK = '1') THEN
IF (RST_FULL_GEN = '1') THEN
prog_full_reg <= '0' after C_TCQ;
ELSIF (C_PROG_FULL_TYPE = 1) THEN
IF (full_comb = '0') THEN
IF (diff_pntr_wr >= C_PF_THR_ASSERT_ADJUSTED) THEN
prog_full_reg <= '1' after C_TCQ;
ELSE
prog_full_reg <= '0' after C_TCQ;
END IF;
ELSE
prog_full_reg <= prog_full_reg after C_TCQ;
END IF;
ELSIF (C_PROG_FULL_TYPE = 2) THEN
IF (full_comb = '0') THEN
IF (diff_pntr_wr >= C_PF_THR_ASSERT_ADJUSTED) THEN
prog_full_reg <= '1' after C_TCQ;
ELSIF (diff_pntr_wr < C_PF_THR_NEGATE_ADJUSTED) THEN
prog_full_reg <= '0' after C_TCQ;
ELSE
prog_full_reg <= prog_full_reg after C_TCQ;
END IF;
ELSE
prog_full_reg <= prog_full_reg after C_TCQ;
END IF;
ELSIF (C_PROG_FULL_TYPE = 3) THEN
IF (full_comb = '0') THEN
IF (diff_pntr_wr >= conv_integer(pf_input_thr_assert_val)) THEN
prog_full_reg <= '1' after C_TCQ;
ELSE
prog_full_reg <= '0' after C_TCQ;
END IF;
ELSE
prog_full_reg <= prog_full_reg after C_TCQ;
END IF;
ELSIF (C_PROG_FULL_TYPE = 4) THEN
IF (full_comb = '0') THEN
IF (diff_pntr_wr >= conv_integer(pf_input_thr_assert_val)) THEN
prog_full_reg <= '1' after C_TCQ;
ELSIF (diff_pntr_wr < conv_integer(pf_input_thr_negate_val)) THEN
prog_full_reg <= '0' after C_TCQ;
ELSE
prog_full_reg <= prog_full_reg after C_TCQ;
END IF;
ELSE
prog_full_reg <= prog_full_reg after C_TCQ;
END IF;
END IF; --C_PROG_FULL_TYPE
END IF; -- WR_CLK
END PROCESS proc_pf;
---------------------------------------------------------------------------
-- Programmable EMPTY Flags
---------------------------------------------------------------------------
proc_pe: PROCESS(RD_CLK, rd_rst_i)
VARIABLE pe_thr_assert_val : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE pe_thr_negate_val : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
IF (rd_rst_i = '1') THEN
diff_pntr_rd <= 0;
prog_empty_reg <= '1';
pe_thr_assert_val := (OTHERS => '0');
pe_thr_negate_val := (OTHERS => '0');
ELSIF (RD_CLK'event AND RD_CLK = '1') THEN
IF (ram_rd_en = '0') THEN
diff_pntr_rd <= conv_integer(adj_wr_pntr_rd - rd_pntr) after C_TCQ;
ELSIF (ram_rd_en = '1') THEN
diff_pntr_rd <= conv_integer(adj_wr_pntr_rd - rd_pntr) - 1 after C_TCQ;
ELSE
diff_pntr_rd <= diff_pntr_rd after C_TCQ;
END IF;
IF (C_PROG_EMPTY_TYPE = 1) THEN
IF (empty_comb = '0') THEN
IF (diff_pntr_rd <= C_PE_THR_ASSERT_VAL_I) THEN
prog_empty_reg <= '1' after C_TCQ;
ELSE
prog_empty_reg <= '0' after C_TCQ;
END IF;
ELSE
prog_empty_reg <= prog_empty_reg after C_TCQ;
END IF;
ELSIF (C_PROG_EMPTY_TYPE = 2) THEN
IF (empty_comb = '0') THEN
IF (diff_pntr_rd <= C_PE_THR_ASSERT_VAL_I) THEN
prog_empty_reg <= '1' after C_TCQ;
ELSIF (diff_pntr_rd > C_PE_THR_NEGATE_VAL_I) THEN
prog_empty_reg <= '0' after C_TCQ;
ELSE
prog_empty_reg <= prog_empty_reg after C_TCQ;
END IF;
ELSE
prog_empty_reg <= prog_empty_reg after C_TCQ;
END IF;
ELSIF (C_PROG_EMPTY_TYPE = 3) THEN
-- If empty input threshold is selected, then subtract 2 for FWFT to
-- compensate the FWFT stage, otherwise assign the input value.
IF (C_PRELOAD_REGS = 1 AND C_PRELOAD_LATENCY = 0) THEN -- FWFT
pe_thr_assert_val := PROG_EMPTY_THRESH - "10";
ELSE
pe_thr_assert_val := PROG_EMPTY_THRESH;
END IF;
IF (empty_comb = '0') THEN
IF (diff_pntr_rd <= pe_thr_assert_val) THEN
prog_empty_reg <= '1' after C_TCQ;
ELSE
prog_empty_reg <= '0' after C_TCQ;
END IF;
ELSE
prog_empty_reg <= prog_empty_reg after C_TCQ;
END IF;
ELSIF (C_PROG_EMPTY_TYPE = 4) THEN
-- If empty input threshold is selected, then subtract 2 for FWFT to
-- compensate the FWFT stage, otherwise assign the input value.
IF (C_PRELOAD_REGS = 1 AND C_PRELOAD_LATENCY = 0) THEN -- FWFT
pe_thr_assert_val := PROG_EMPTY_THRESH_ASSERT - "10";
pe_thr_negate_val := PROG_EMPTY_THRESH_NEGATE - "10";
ELSE
pe_thr_assert_val := PROG_EMPTY_THRESH_ASSERT;
pe_thr_negate_val := PROG_EMPTY_THRESH_NEGATE;
END IF;
IF (empty_comb = '0') THEN
IF (diff_pntr_rd <= conv_integer(pe_thr_assert_val)) THEN
prog_empty_reg <= '1' after C_TCQ;
ELSIF (diff_pntr_rd > conv_integer(pe_thr_negate_val)) THEN
prog_empty_reg <= '0' after C_TCQ;
ELSE
prog_empty_reg <= prog_empty_reg after C_TCQ;
END IF;
ELSE
prog_empty_reg <= prog_empty_reg after C_TCQ;
END IF;
END IF; --C_PROG_EMPTY_TYPE
END IF; -- RD_CLK
END PROCESS proc_pe;
-----------------------------------------------------------------------------
-- overflow_i generation: Asynchronous FIFO
-----------------------------------------------------------------------------
govflw: IF (C_HAS_OVERFLOW = 1) GENERATE
g7s_ovflw: IF (NOT (C_FAMILY = "virtexu" OR C_FAMILY = "kintexu" OR C_FAMILY = "artixu" OR C_FAMILY = "virtexuplus" OR C_FAMILY = "zynquplus" OR C_FAMILY = "kintexuplus")) GENERATE
povflw: PROCESS (WR_CLK)
BEGIN
IF WR_CLK'event AND WR_CLK = '1' THEN
overflow_i <= full_comb AND WR_EN after C_TCQ;
END IF;
END PROCESS povflw;
END GENERATE g7s_ovflw;
g8s_ovflw: IF ((C_FAMILY = "virtexu" OR C_FAMILY = "kintexu" OR C_FAMILY = "artixu" OR C_FAMILY = "virtexuplus" OR C_FAMILY = "zynquplus" OR C_FAMILY = "kintexuplus")) GENERATE
povflw: PROCESS (WR_CLK)
BEGIN
IF WR_CLK'event AND WR_CLK = '1' THEN
--overflow_i <= (wr_rst_i OR full_comb) AND WR_EN after C_TCQ;
overflow_i <= (full_comb) AND WR_EN after C_TCQ;
END IF;
END PROCESS povflw;
END GENERATE g8s_ovflw;
END GENERATE govflw;
-----------------------------------------------------------------------------
-- underflow_i generation: Asynchronous FIFO
-----------------------------------------------------------------------------
gunflw: IF (C_HAS_UNDERFLOW = 1) GENERATE
g7s_unflw: IF (NOT (C_FAMILY = "virtexu" OR C_FAMILY = "kintexu" OR C_FAMILY = "artixu" OR C_FAMILY = "virtexuplus" OR C_FAMILY = "zynquplus" OR C_FAMILY = "kintexuplus")) GENERATE
punflw: PROCESS (RD_CLK)
BEGIN
IF RD_CLK'event AND RD_CLK = '1' THEN
underflow_i <= empty_comb and RD_EN after C_TCQ;
END IF;
END PROCESS punflw;
END GENERATE g7s_unflw;
g8s_unflw: IF ((C_FAMILY = "virtexu" OR C_FAMILY = "kintexu" OR C_FAMILY = "artixu" OR C_FAMILY = "virtexuplus" OR C_FAMILY = "zynquplus" OR C_FAMILY = "kintexuplus")) GENERATE
punflw: PROCESS (RD_CLK)
BEGIN
IF RD_CLK'event AND RD_CLK = '1' THEN
--underflow_i <= (rd_rst_i OR empty_comb) and RD_EN after C_TCQ;
underflow_i <= (empty_comb) and RD_EN after C_TCQ;
END IF;
END PROCESS punflw;
END GENERATE g8s_unflw;
END GENERATE gunflw;
-----------------------------------------------------------------------------
-- wr_ack_i generation: Asynchronous FIFO
-----------------------------------------------------------------------------
gwack: IF (C_HAS_WR_ACK = 1) GENERATE
pwack: PROCESS (WR_CLK,wr_rst_i)
BEGIN
IF wr_rst_i = '1' THEN
wr_ack_i <= '0' after C_TCQ;
ELSIF WR_CLK'event AND WR_CLK = '1' THEN
wr_ack_i <= '0' after C_TCQ;
IF WR_EN = '1' THEN
IF full_comb /= '1' THEN
wr_ack_i <= '1' after C_TCQ;
END IF;
END IF;
END IF;
END PROCESS pwack;
END GENERATE gwack;
----------------------------------------------------------------------------
-- valid_i generation: Asynchronous FIFO
----------------------------------------------------------------------------
gvld_i: IF (C_HAS_VALID = 1) GENERATE
PROCESS (rd_rst_i , RD_CLK )
BEGIN
IF rd_rst_i = '1' THEN
valid_i <= '0' after C_TCQ;
ELSIF RD_CLK'event AND RD_CLK = '1' THEN
valid_i <= '0' after C_TCQ;
IF RD_EN = '1' THEN
IF empty_comb /= '1' THEN
valid_i <= '1' after C_TCQ;
END IF;
END IF;
END IF;
END PROCESS;
-----------------------------------------------------------------
-- Delay valid_d1
--if C_MEMORY_TYPE=0 or 1, C_USE_EMBEDDED_REG=1
-----------------------------------------------------------------
gv0_as: IF (C_USE_EMBEDDED_REG>0
AND (C_MEMORY_TYPE=0 OR C_MEMORY_TYPE=1)) GENERATE
PROCESS (rd_rst_i , RD_CLK )
BEGIN
IF rd_rst_i = '1' THEN
valid_d1 <= '0' after C_TCQ;
ELSIF RD_CLK'event AND RD_CLK = '1' THEN
valid_d1 <= valid_i after C_TCQ;
END IF;
END PROCESS;
END GENERATE gv0_as;
gv1_as: IF NOT (C_USE_EMBEDDED_REG>0
AND (C_MEMORY_TYPE=0 OR C_MEMORY_TYPE=1)) GENERATE
valid_d1 <= valid_i;
END GENERATE gv1_as;
END GENERATE gvld_i;
-----------------------------------------------------------------------------
--Use delayed Valid AND DOUT if we have a LATENCY=2 configurations
-- ( if C_MEMORY_TYPE=0 or 1, C_PRELOAD_REGS=0, C_USE_EMBEDDED_REG=1 )
--Otherwise, connect the valid and DOUT values up directly, with no
--additional latency.
-----------------------------------------------------------------------------
gv0: IF (C_PRELOAD_LATENCY=2
AND (C_MEMORY_TYPE=0 OR C_MEMORY_TYPE=1)AND C_EN_SAFETY_CKT =0) GENERATE
gv1: IF (C_HAS_VALID = 1) GENERATE
valid_out <= valid_d1;
END GENERATE gv1;
PROCESS (rd_rst_i , RD_CLK )
BEGIN
IF (rd_rst_i = '1') THEN
-- BRAM resets synchronously
IF (C_USE_DOUT_RST = 1) THEN
IF (RD_CLK 'event AND RD_CLK = '1') THEN
DOUT <= hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH) after C_TCQ;
END IF;
END IF;
IF (C_USE_ECC = 0) THEN
SBITERR <= '0' after C_TCQ;
DBITERR <= '0' after C_TCQ;
END IF;
ram_rd_en_d1 <= '0' after C_TCQ;
ELSIF (RD_CLK 'event AND RD_CLK = '1') THEN
ram_rd_en_d1 <= ram_rd_en after C_TCQ;
IF (ram_rd_en_d1 = '1') THEN
DOUT <= dout_i after C_TCQ;
SBITERR <= sbiterr_i after C_TCQ;
DBITERR <= dbiterr_i after C_TCQ;
END IF;
END IF;
END PROCESS;
END GENERATE gv0;
gv0_safety: IF (C_PRELOAD_LATENCY=2
AND (C_MEMORY_TYPE=0 OR C_MEMORY_TYPE=1) AND C_EN_SAFETY_CKT =1) GENERATE
SIGNAL dout_rst_val_d1 : std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL dout_rst_val_d2 : std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_delayed_sft1 : std_logic := '1';
SIGNAL rst_delayed_sft2 : std_logic := '1';
SIGNAL rst_delayed_sft3 : std_logic := '1';
SIGNAL rst_delayed_sft4 : std_logic := '1';
BEGIN
gv1: IF (C_HAS_VALID = 1) GENERATE
valid_out <= valid_d1;
END GENERATE gv1;
PROCESS ( RD_CLK )
BEGIN
rst_delayed_sft1 <= rd_rst_i;
rst_delayed_sft2 <= rst_delayed_sft1;
rst_delayed_sft3 <= rst_delayed_sft2;
rst_delayed_sft4 <= rst_delayed_sft3;
END PROCESS;
PROCESS (rst_delayed_sft4 ,rd_rst_i, RD_CLK )
BEGIN
IF (rst_delayed_sft4 = '1' OR rd_rst_i = '1') THEN
ram_rd_en_d1 <= '0' after C_TCQ;
ELSIF (RD_CLK 'event AND RD_CLK = '1') THEN
ram_rd_en_d1 <= ram_rd_en after C_TCQ;
END IF;
END PROCESS;
PROCESS (rst_delayed_sft4 , RD_CLK )
BEGIN
IF (rst_delayed_sft4 = '1' ) THEN
-- BRAM resets synchronously
IF (C_USE_DOUT_RST = 1) THEN
IF (RD_CLK 'event AND RD_CLK = '1') THEN
DOUT <= hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH) after C_TCQ;
END IF;
END IF;
IF (C_USE_ECC = 0) THEN
SBITERR <= '0' after C_TCQ;
DBITERR <= '0' after C_TCQ;
END IF;
--ram_rd_en_d1 <= '0' after C_TCQ;
ELSIF (RD_CLK 'event AND RD_CLK = '1') THEN
--ram_rd_en_d1 <= ram_rd_en after C_TCQ;
IF (ram_rd_en_d1 = '1') THEN
DOUT <= dout_i after C_TCQ;
SBITERR <= sbiterr_i after C_TCQ;
DBITERR <= dbiterr_i after C_TCQ;
END IF;
END IF;
END PROCESS;
END GENERATE gv0_safety;
gv1_nsafety: IF (NOT (C_PRELOAD_LATENCY=2
AND (C_MEMORY_TYPE=0 OR C_MEMORY_TYPE=1)) ) GENERATE
gv2a: IF (C_HAS_VALID = 1) GENERATE
valid_out <= valid_i;
END GENERATE gv2a;
DOUT <= dout_i;
SBITERR <= sbiterr_i after C_TCQ;
DBITERR <= dbiterr_i after C_TCQ;
END GENERATE gv1_nsafety;
END GENERATE gnll_afifo;
-------------------------------------------------------------------------------
-- Low Latency Asynchronous FIFO
-------------------------------------------------------------------------------
gll_afifo: IF (C_FIFO_TYPE = 3) GENERATE
TYPE mem_array IS ARRAY (0 TO C_WR_DEPTH-1) OF STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
SIGNAL memory : mem_array := (OTHERS => (OTHERS => '0'));
SIGNAL write_allow : std_logic := '0';
SIGNAL read_allow : std_logic := '0';
SIGNAL wr_pntr_ll_afifo : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS=>'0');
SIGNAL rd_pntr_ll_afifo : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS=>'0');
SIGNAL rd_pntr_ll_afifo_q : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS=>'0');
SIGNAL ll_afifo_full : std_logic := '0';
SIGNAL ll_afifo_empty : std_logic := '1';
SIGNAL wr_pntr_eq_rd_pntr : std_logic := '0';
SIGNAL wr_pntr_eq_rd_pntr_plus1 : std_logic := '0';
SIGNAL rd_pntr_eq_wr_pntr_plus1 : std_logic := '0';
SIGNAL rd_pntr_eq_wr_pntr_plus2 : std_logic := '0';
BEGIN
wr_rst_i <= WR_RST;
rd_rst_i <= RD_RST;
write_allow <= WR_EN AND (NOT ll_afifo_full);
read_allow <= RD_EN AND (NOT ll_afifo_empty);
wrptr_proc : PROCESS (WR_CLK,wr_rst_i)
BEGIN
IF (wr_rst_i = '1') THEN
wr_pntr_ll_afifo <= (OTHERS => '0');
ELSIF (WR_CLK'event AND WR_CLK = '1') THEN
IF (write_allow = '1') THEN
wr_pntr_ll_afifo <= wr_pntr_ll_afifo + "1" AFTER C_TCQ;
END IF;
END IF;
END PROCESS wrptr_proc;
-------------------------------------------------------------------------------
-- Fill the Memory
-------------------------------------------------------------------------------
wr_mem : PROCESS (WR_CLK)
BEGIN
IF (WR_CLK'event AND WR_CLK = '1') THEN
IF (write_allow = '1') THEN
memory(conv_integer(wr_pntr_ll_afifo)) <= DIN AFTER C_TCQ;
END IF;
END IF;
END PROCESS wr_mem;
rdptr_proc : PROCESS (RD_CLK, rd_rst_i)
BEGIN
IF (rd_rst_i = '1') THEN
rd_pntr_ll_afifo_q <= (OTHERS => '0');
ELSIF (RD_CLK'event AND RD_CLK = '1') THEN
rd_pntr_ll_afifo_q <= rd_pntr_ll_afifo AFTER C_TCQ;
END IF;
END PROCESS rdptr_proc;
rd_pntr_ll_afifo <= rd_pntr_ll_afifo_q + "1" WHEN (read_allow = '1') ELSE rd_pntr_ll_afifo_q;
-------------------------------------------------------------------------------
-- Generate DOUT for DRAM
-------------------------------------------------------------------------------
rd_mem : PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK = '1') THEN
DOUT <= memory(conv_integer(rd_pntr_ll_afifo)) AFTER C_TCQ;
END IF;
END PROCESS rd_mem;
-------------------------------------------------------------------------------
-- Generate EMPTY
-------------------------------------------------------------------------------
wr_pntr_eq_rd_pntr <= '1' WHEN (wr_pntr_ll_afifo = rd_pntr_ll_afifo_q) ELSE '0';
wr_pntr_eq_rd_pntr_plus1 <= '1' WHEN (wr_pntr_ll_afifo = conv_std_logic_vector(
(conv_integer(rd_pntr_ll_afifo_q)+1),
C_RD_PNTR_WIDTH)) ELSE '0';
proc_empty : PROCESS (RD_CLK, rd_rst_i)
BEGIN
IF (rd_rst_i = '1') THEN
ll_afifo_empty <= '1';
ELSIF (RD_CLK'event AND RD_CLK = '1') THEN
ll_afifo_empty <= wr_pntr_eq_rd_pntr OR (read_allow AND wr_pntr_eq_rd_pntr_plus1) AFTER C_TCQ;
END IF;
END PROCESS proc_empty;
-------------------------------------------------------------------------------
-- Generate FULL
-------------------------------------------------------------------------------
rd_pntr_eq_wr_pntr_plus1 <= '1' WHEN (rd_pntr_ll_afifo_q = conv_std_logic_vector(
(conv_integer(wr_pntr_ll_afifo)+1),
C_WR_PNTR_WIDTH)) ELSE '0';
rd_pntr_eq_wr_pntr_plus2 <= '1' WHEN (rd_pntr_ll_afifo_q = conv_std_logic_vector(
(conv_integer(wr_pntr_ll_afifo)+2),
C_WR_PNTR_WIDTH)) ELSE '0';
proc_full : PROCESS (WR_CLK, wr_rst_i)
BEGIN
IF (wr_rst_i = '1') THEN
ll_afifo_full <= '1';
ELSIF (WR_CLK'event AND WR_CLK = '1') THEN
ll_afifo_full <= rd_pntr_eq_wr_pntr_plus1 OR (write_allow AND rd_pntr_eq_wr_pntr_plus2) AFTER C_TCQ;
END IF;
END PROCESS proc_full;
EMPTY <= ll_afifo_empty;
FULL <= ll_afifo_full;
END GENERATE gll_afifo;
END behavioral;
--#############################################################################
--#############################################################################
-- Common Clock FIFO Behavioral Model
--#############################################################################
--#############################################################################
-------------------------------------------------------------------------------
-- Library Declaration
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.std_logic_misc.ALL;
-------------------------------------------------------------------------------
-- Common-Clock Entity Declaration - This is NOT the top-level entity
-------------------------------------------------------------------------------
ENTITY fifo_generator_v13_0_1_bhv_ss IS
GENERIC (
--------------------------------------------------------------------------------
-- Generic Declarations (alphabetical)
--------------------------------------------------------------------------------
C_FAMILY : string := "virtex7";
C_DATA_COUNT_WIDTH : integer := 2;
C_DIN_WIDTH : integer := 8;
C_DOUT_RST_VAL : string := "";
C_DOUT_WIDTH : integer := 8;
C_FULL_FLAGS_RST_VAL : integer := 1;
C_HAS_ALMOST_EMPTY : integer := 0;
C_HAS_ALMOST_FULL : integer := 0;
C_HAS_DATA_COUNT : integer := 0;
C_HAS_OVERFLOW : integer := 0;
C_HAS_RD_DATA_COUNT : integer := 2;
C_HAS_RST : integer := 0;
C_HAS_SRST : integer := 0;
C_HAS_UNDERFLOW : integer := 0;
C_HAS_VALID : integer := 0;
C_HAS_WR_ACK : integer := 0;
C_HAS_WR_DATA_COUNT : integer := 2;
C_MEMORY_TYPE : integer := 1;
C_OVERFLOW_LOW : integer := 0;
C_PRELOAD_LATENCY : integer := 1;
C_PRELOAD_REGS : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL : integer := 0;
C_PROG_EMPTY_THRESH_NEGATE_VAL : integer := 0;
C_PROG_EMPTY_TYPE : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL : integer := 0;
C_PROG_FULL_THRESH_NEGATE_VAL : integer := 0;
C_PROG_FULL_TYPE : integer := 0;
C_RD_DATA_COUNT_WIDTH : integer := 0;
C_RD_DEPTH : integer := 256;
C_RD_PNTR_WIDTH : integer := 8;
C_UNDERFLOW_LOW : integer := 0;
C_USE_DOUT_RST : integer := 0;
C_USE_ECC : integer := 0;
C_USE_EMBEDDED_REG : integer := 0;
C_EN_SAFETY_CKT : integer := 0;
C_USE_FWFT_DATA_COUNT : integer := 0;
C_VALID_LOW : integer := 0;
C_WR_ACK_LOW : integer := 0;
C_WR_DATA_COUNT_WIDTH : integer := 0;
C_WR_DEPTH : integer := 256;
C_WR_PNTR_WIDTH : integer := 8;
C_TCQ : time := 100 ps;
C_ENABLE_RST_SYNC : integer := 1;
C_ERROR_INJECTION_TYPE : integer := 0;
C_FIFO_TYPE : integer := 0
);
PORT(
--------------------------------------------------------------------------------
-- Input and Output Declarations
--------------------------------------------------------------------------------
CLK : IN std_logic := '0';
RST : IN std_logic := '0';
SRST : IN std_logic := '0';
RST_FULL_GEN : IN std_logic := '0';
RST_FULL_FF : IN std_logic := '0';
DIN : IN std_logic_vector(C_DIN_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
RD_EN : IN std_logic := '0';
RD_EN_USER : IN std_logic;
WR_EN : IN std_logic := '0';
PROG_EMPTY_THRESH : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
PROG_EMPTY_THRESH_ASSERT : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
PROG_EMPTY_THRESH_NEGATE : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
PROG_FULL_THRESH_ASSERT : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
PROG_FULL_THRESH_NEGATE : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
WR_RST_BUSY : IN std_logic := '0';
RD_RST_BUSY : IN std_logic := '0';
INJECTDBITERR : IN std_logic := '0';
INJECTSBITERR : IN std_logic := '0';
USER_EMPTY_FB : IN std_logic := '1';
DOUT : OUT std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
EMPTY : OUT std_logic := '1';
FULL : OUT std_logic := '0';
ALMOST_EMPTY : OUT std_logic := '1';
ALMOST_FULL : OUT std_logic := '0';
PROG_EMPTY : OUT std_logic := '1';
PROG_FULL : OUT std_logic := '0';
OVERFLOW : OUT std_logic := '0';
WR_ACK : OUT std_logic := '0';
VALID : OUT std_logic := '0';
UNDERFLOW : OUT std_logic := '0';
DATA_COUNT : OUT std_logic_vector(C_DATA_COUNT_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
RD_DATA_COUNT : OUT std_logic_vector(C_RD_DATA_COUNT_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
WR_DATA_COUNT : OUT std_logic_vector(C_WR_DATA_COUNT_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
SBITERR : OUT std_logic := '0';
DBITERR : OUT std_logic := '0'
);
END fifo_generator_v13_0_1_bhv_ss;
-------------------------------------------------------------------------------
-- Architecture Heading
-------------------------------------------------------------------------------
ARCHITECTURE behavioral OF fifo_generator_v13_0_1_bhv_ss IS
-----------------------------------------------------------------------------
-- FUNCTION actual_fifo_depth
-- Returns the actual depth of the FIFO (may differ from what the user
-- specified)
--
-- The FIFO depth is always represented as 2^n (16,32,64,128,256)
-- However, the ACTUAL fifo depth may be 2^n+1 or 2^n-1 depending on certain
-- options. This function returns the actual depth of the fifo, as seen by
-- the user.
-------------------------------------------------------------------------------
FUNCTION actual_fifo_depth(
C_FIFO_DEPTH : integer;
C_PRELOAD_REGS : integer;
C_PRELOAD_LATENCY : integer;
C_COMMON_CLOCK : integer)
RETURN integer IS
BEGIN
RETURN C_FIFO_DEPTH;
END actual_fifo_depth;
-----------------------------------------------------------------------------
-- FUNCTION int_2_std_logic
-- Returns a single bit (as std_logic) from an integer 1/0 value.
-------------------------------------------------------------------------------
FUNCTION int_2_std_logic(value : integer) RETURN std_logic IS
BEGIN
IF (value=1) THEN
RETURN '1';
ELSE
RETURN '0';
END IF;
END int_2_std_logic;
-----------------------------------------------------------------------------
-- FUNCTION hexstr_to_std_logic_vec
-- Returns a std_logic_vector for a hexadecimal string
-------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
-----------------------------------------------------------------------------
-- FUNCTION get_lesser
-- Returns a minimum value
-------------------------------------------------------------------------------
FUNCTION get_lesser(a: INTEGER; b: INTEGER) RETURN INTEGER IS
BEGIN
IF (a < b) THEN
RETURN a;
ELSE
RETURN b;
END IF;
END FUNCTION;
-----------------------------------------------------------------------------
-- FUNCTION if_then_else
-- Returns a true case or flase case based on the condition
-------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : boolean;
true_case : integer;
false_case : integer)
RETURN integer IS
VARIABLE retval : integer := 0;
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
FUNCTION if_then_else (
condition : boolean;
true_case : std_logic;
false_case : std_logic)
RETURN std_logic IS
VARIABLE retval : std_logic := '0';
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
FUNCTION if_then_else (
condition : boolean;
true_case : std_logic_vector;
false_case : std_logic_vector)
RETURN std_logic_vector IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
FUNCTION int_2_std_logic_vector(
value, bitwidth : integer )
RETURN std_logic_vector IS
VARIABLE running_value : integer := value;
VARIABLE running_result : std_logic_vector(bitwidth-1 DOWNTO 0);
BEGIN
running_result := conv_std_logic_vector(value,bitwidth);
RETURN running_result;
END int_2_std_logic_vector;
--------------------------------------------------------------------------------
-- Constant Declaration
--------------------------------------------------------------------------------
CONSTANT C_FIFO_WR_DEPTH : integer
:= actual_fifo_depth(C_WR_DEPTH, C_PRELOAD_REGS, C_PRELOAD_LATENCY, 1);
CONSTANT C_SMALLER_DATA_WIDTH : integer := get_lesser(C_DIN_WIDTH, C_DOUT_WIDTH);
CONSTANT C_FIFO_DEPTH : integer := C_WR_DEPTH;
CONSTANT C_DEPTH_RATIO_WR : integer
:= if_then_else( (C_WR_DEPTH > C_RD_DEPTH), (C_WR_DEPTH/C_RD_DEPTH), 1);
CONSTANT C_DEPTH_RATIO_RD : integer
:= if_then_else( (C_RD_DEPTH > C_WR_DEPTH), (C_RD_DEPTH/C_WR_DEPTH), 1);
CONSTANT C_DATA_WIDTH : integer := if_then_else((C_USE_ECC > 0 AND C_ERROR_INJECTION_TYPE /= 0),
C_DIN_WIDTH+2, C_DIN_WIDTH);
CONSTANT OF_INIT_VAL : std_logic := if_then_else((C_HAS_OVERFLOW = 1 AND C_OVERFLOW_LOW = 1),'1','0');
CONSTANT UF_INIT_VAL : std_logic := if_then_else((C_HAS_UNDERFLOW = 1 AND C_UNDERFLOW_LOW = 1),'1','0');
CONSTANT DO_ALL_ZERO : std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
CONSTANT RST_VAL : std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0) := hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH);
CONSTANT RST_VALUE : std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0)
:= if_then_else(C_USE_DOUT_RST = 1, RST_VAL, DO_ALL_ZERO);
CONSTANT IS_ASYMMETRY : integer :=if_then_else((C_WR_PNTR_WIDTH /= C_RD_PNTR_WIDTH),1,0);
CONSTANT C_GRTR_PNTR_WIDTH : integer :=if_then_else((C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH),C_WR_PNTR_WIDTH,C_RD_PNTR_WIDTH);
CONSTANT LESSER_WIDTH : integer
:=if_then_else((C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH),
C_WR_PNTR_WIDTH,
C_RD_PNTR_WIDTH);
CONSTANT DIFF_MAX_RD : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '1');
CONSTANT DIFF_MAX_WR : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '1');
TYPE mem_array IS ARRAY (0 TO C_FIFO_DEPTH-1) OF STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
-------------------------------------------------------------------------------
-- Internal Signals
-------------------------------------------------------------------------------
SIGNAL memory : mem_array := (OTHERS => (OTHERS => '0'));
SIGNAL wr_pntr : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_pntr : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL write_allow : std_logic := '0';
SIGNAL read_allow : std_logic := '0';
SIGNAL read_allow_dc : std_logic := '0';
SIGNAL empty_i : std_logic := '1';
SIGNAL full_i : std_logic := int_2_std_logic(C_FULL_FLAGS_RST_VAL);
SIGNAL almost_empty_i : std_logic := '1';
SIGNAL almost_full_i : std_logic := '0';
SIGNAL rst_asreg : std_logic := '0';
SIGNAL rst_asreg_d1 : std_logic := '0';
SIGNAL rst_asreg_d2 : std_logic := '0';
SIGNAL rst_comb : std_logic := '0';
SIGNAL rst_reg : std_logic := '0';
SIGNAL rst_i : std_logic := '0';
SIGNAL srst_i : std_logic := '0';
SIGNAL srst_wrst_busy : std_logic := '0';
SIGNAL srst_rrst_busy : std_logic := '0';
SIGNAL diff_count : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
SIGNAL wr_ack_i : std_logic := '0';
SIGNAL overflow_i : std_logic := OF_INIT_VAL;
SIGNAL valid_i : std_logic := '0';
SIGNAL valid_d1 : std_logic := '0';
SIGNAL underflow_i : std_logic := UF_INIT_VAL;
--The delayed reset is used to deassert prog_full
SIGNAL rst_q : std_logic := '0';
SIGNAL prog_full_reg : std_logic := '0';
SIGNAL prog_full_noreg : std_logic := '0';
SIGNAL prog_empty_reg : std_logic := '1';
SIGNAL prog_empty_noreg: std_logic := '1';
SIGNAL dout_i : std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0) := RST_VALUE;
SIGNAL sbiterr_i : std_logic := '0';
SIGNAL dbiterr_i : std_logic := '0';
SIGNAL ram_rd_en_d1 : std_logic := '0';
SIGNAL mem_pntr : integer := 0;
SIGNAL ram_wr_en_i : std_logic := '0';
SIGNAL ram_rd_en_i : std_logic := '0';
SIGNAL comp1 : std_logic := '0';
SIGNAL comp0 : std_logic := '0';
SIGNAL going_full : std_logic := '0';
SIGNAL leaving_full : std_logic := '0';
SIGNAL ram_full_comb : std_logic := '0';
SIGNAL ecomp1 : std_logic := '0';
SIGNAL ecomp0 : std_logic := '0';
SIGNAL going_empty : std_logic := '0';
SIGNAL leaving_empty : std_logic := '0';
SIGNAL ram_empty_comb : std_logic := '0';
SIGNAL wr_point : integer := 0;
SIGNAL rd_point : integer := 0;
SIGNAL wr_point_d1 : integer := 0;
SIGNAL wr_point_d2 : integer := 0;
SIGNAL rd_point_d1 : integer := 0;
SIGNAL num_wr_words : integer := 0;
SIGNAL num_rd_words : integer := 0;
SIGNAL adj_wr_point : integer := 0;
SIGNAL adj_rd_point : integer := 0;
SIGNAL adj_wr_point_d1: integer := 0;
SIGNAL adj_rd_point_d1: integer := 0;
SIGNAL wr_pntr_temp : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL wr_pntr_rd1 : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL wr_pntr_rd2 : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL wr_pntr_rd3 : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL wr_pntr_rd : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL adj_wr_pntr_rd : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL wr_data_count_int : std_logic_vector(C_WR_PNTR_WIDTH DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL wdc_fwft_ext_as : std_logic_vector(C_WR_PNTR_WIDTH DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL rdc_fwft_ext_as : std_logic_vector (C_RD_PNTR_WIDTH DOWNTO 0)
:= (OTHERS => '0');
SIGNAL rd_pntr_wr_d1 : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL rd_pntr_wr_d2 : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL rd_pntr_wr_d3 : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL rd_pntr_wr_d4 : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL rd_pntr_wr : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL adj_rd_pntr_wr : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL rd_data_count_int : std_logic_vector(C_RD_PNTR_WIDTH DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL width_gt1 : std_logic := '0';
-------------------------------------------------------------------------------
--Used in computing AE and AF
-------------------------------------------------------------------------------
SIGNAL fcomp2 : std_logic := '0';
SIGNAL going_afull : std_logic := '0';
SIGNAL leaving_afull : std_logic := '0';
SIGNAL ram_afull_comb : std_logic := '0';
SIGNAL ecomp2 : std_logic := '0';
SIGNAL going_aempty : std_logic := '0';
SIGNAL leaving_aempty : std_logic := '0';
SIGNAL ram_aempty_comb : std_logic := '1';
SIGNAL rd_fwft_cnt : std_logic_vector(3 downto 0) := (others=>'0');
SIGNAL stage1_valid : std_logic := '0';
SIGNAL stage2_valid : std_logic := '0';
-------------------------------------------------------------------------------
--Used in computing RD_DATA_COUNT WR_DATA_COUNT
-------------------------------------------------------------------------------
SIGNAL count_dc : std_logic_vector(C_GRTR_PNTR_WIDTH DOWNTO 0) := int_2_std_logic_vector(0,C_GRTR_PNTR_WIDTH+1);
SIGNAL one : std_logic_vector(C_GRTR_PNTR_WIDTH DOWNTO 0);
SIGNAL ratio : std_logic_vector(C_GRTR_PNTR_WIDTH DOWNTO 0);
-------------------------------------------------------------------------------
--Linked List types
-------------------------------------------------------------------------------
TYPE listtyp;
TYPE listptr IS ACCESS listtyp;
TYPE listtyp IS RECORD
data : std_logic_vector(C_SMALLER_DATA_WIDTH + 1 DOWNTO 0);
older : listptr;
newer : listptr;
END RECORD;
-------------------------------------------------------------------------------
--Processes for linked list implementation. The functions are
--1. "newlist" - Create a new linked list
--2. "add" - Add a data element to a linked list
--3. "read" - Read the data from the tail of the linked list
--4. "remove" - Remove the tail from the linked list
--5. "sizeof" - Calculate the size of the linked list
-------------------------------------------------------------------------------
--1. Create a new linked list
PROCEDURE newlist (
head : INOUT listptr;
tail : INOUT listptr;
cntr : INOUT integer) IS
BEGIN
head := NULL;
tail := NULL;
cntr := 0;
END;
--2. Add a data element to a linked list
PROCEDURE add (
head : INOUT listptr;
tail : INOUT listptr;
data : IN std_logic_vector;
cntr : INOUT integer;
inj_err : IN std_logic_vector(2 DOWNTO 0)
) IS
VARIABLE oldhead : listptr;
VARIABLE newhead : listptr;
VARIABLE corrupted_data : std_logic_vector(1 DOWNTO 0);
BEGIN
--------------------------------------------------------------------------
--a. Create a pointer to the existing head, if applicable
--b. Create a new node for the list
--c. Make the new node point to the old head
--d. Make the old head point back to the new node (for doubly-linked list)
--e. Put the data into the new head node
--f. If the new head we just created is the only node in the list,
-- make the tail point to it
--g. Return the new head pointer
--------------------------------------------------------------------------
IF (head /= NULL) THEN
oldhead := head;
END IF;
newhead := NEW listtyp;
newhead.older := oldhead;
IF (head /= NULL) THEN
oldhead.newer := newhead;
END IF;
CASE inj_err(1 DOWNTO 0) IS
-- For both error injection, pass only the double bit error injection
-- as dbit error has priority over single bit error injection
WHEN "11" => newhead.data := inj_err(1) & '0' & data;
WHEN "10" => newhead.data := inj_err(1) & '0' & data;
WHEN "01" => newhead.data := '0' & inj_err(0) & data;
WHEN OTHERS => newhead.data := '0' & '0' & data;
END CASE;
-- Increment the counter when data is added to the list
cntr := cntr + 1;
IF (newhead.older = NULL) THEN
tail := newhead;
END IF;
head := newhead;
END;
--3. Read the data from the tail of the linked list
PROCEDURE read (
tail : INOUT listptr;
data : OUT std_logic_vector;
err_type : OUT std_logic_vector(1 DOWNTO 0)
) IS
VARIABLE data_int : std_logic_vector(C_SMALLER_DATA_WIDTH + 1 DOWNTO 0) := (OTHERS => '0');
VARIABLE err_type_int : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
BEGIN
data_int := tail.data;
-- MSB two bits carry the error injection type.
err_type_int := data_int(data_int'high DOWNTO C_SMALLER_DATA_WIDTH);
IF (err_type_int(1) = '0') THEN
data := data_int(C_SMALLER_DATA_WIDTH - 1 DOWNTO 0);
ELSIF (C_DOUT_WIDTH = 2) THEN
data := NOT data_int(C_SMALLER_DATA_WIDTH - 1 DOWNTO 0);
ELSIF (C_DOUT_WIDTH > 2) THEN
data := NOT data_int(data_int'high-2) & NOT data_int(data_int'high-3) &
data_int(data_int'high-4 DOWNTO 0);
ELSE
data := data_int(C_SMALLER_DATA_WIDTH - 1 DOWNTO 0);
END IF;
err_type := err_type_int;
END;
--4. Remove the tail from the linked list
PROCEDURE remove (
head : INOUT listptr;
tail : INOUT listptr;
cntr : INOUT integer) IS
VARIABLE oldtail : listptr;
VARIABLE newtail : listptr;
BEGIN
--------------------------------------------------------------------------
--Make a copy of the old tail pointer
--a. If there is no newer node, then set the tail pointer to nothing
-- (list is empty)
-- otherwise, make the next newer node the new tail, and make it point
-- to nothing older
--b. Clean up the memory for the old tail node
--c. If the new tail is nothing, then we have an empty list, and head
-- should also be set to nothing
--d. Return the new tail
--------------------------------------------------------------------------
oldtail := tail;
IF (oldtail.newer = NULL) THEN
newtail := NULL;
ELSE
newtail := oldtail.newer;
newtail.older := NULL;
END IF;
DEALLOCATE(oldtail);
IF (newtail = NULL) THEN
head := NULL;
END IF;
tail := newtail;
-- Decrement the counter when data is removed from the list
cntr := cntr - 1;
END;
--5. Calculate the size of the linked list
PROCEDURE sizeof (head : INOUT listptr; size : OUT integer) IS
VARIABLE curlink : listptr;
VARIABLE tmpsize : integer := 0;
BEGIN
--------------------------------------------------------------------------
--a. If head is null, then there is nothing in the list to traverse
-- start with the head node (which implies at least one node exists)
-- Loop through each node until you find the one that points to nothing
-- (the tail)
--b. Return the number of nodes
--------------------------------------------------------------------------
IF (head /= NULL) THEN
curlink := head;
tmpsize := 1;
WHILE (curlink.older /= NULL) LOOP
tmpsize := tmpsize + 1;
curlink := curlink.older;
END LOOP;
END IF;
size := tmpsize;
END;
-----------------------------------------------------------------------------
-- converts integer to specified length std_logic_vector : dropping least
-- significant bits if integer is bigger than what can be represented by
-- the vector
-----------------------------------------------------------------------------
FUNCTION count(
fifo_count : IN integer;
pointer_width : IN integer;
counter_width : IN integer)
RETURN std_logic_vector IS
VARIABLE temp : std_logic_vector(pointer_width-1 DOWNTO 0)
:= (OTHERS => '0');
VARIABLE output : std_logic_vector(counter_width - 1 DOWNTO 0)
:= (OTHERS => '0');
BEGIN
temp := CONV_STD_LOGIC_VECTOR(fifo_count, pointer_width);
IF (counter_width <= pointer_width) THEN
output := temp(pointer_width - 1 DOWNTO pointer_width - counter_width);
ELSE
output := temp(counter_width - 1 DOWNTO 0);
END IF;
RETURN output;
END count;
-------------------------------------------------------------------------------
-- architecture begins here
-------------------------------------------------------------------------------
BEGIN
--gnll_fifo: IF (C_FIFO_TYPE /= 2) GENERATE
rst_i <= RST;
--SRST
gsrst : IF (C_HAS_SRST=1) GENERATE
srst_i <= SRST;
srst_rrst_busy <= SRST OR RD_RST_BUSY;
srst_wrst_busy <= SRST OR WR_RST_BUSY;
END GENERATE gsrst;
--No SRST
nosrst : IF (C_HAS_SRST=0) GENERATE
srst_i <= '0';
srst_rrst_busy <= '0';
srst_wrst_busy <= '0';
END GENERATE nosrst;
gdc : IF (C_HAS_DATA_COUNT = 1) GENERATE
SIGNAL diff_count : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
diff_count <= wr_pntr - rd_pntr;
gdcb : IF (C_DATA_COUNT_WIDTH > C_RD_PNTR_WIDTH) GENERATE
DATA_COUNT(C_RD_PNTR_WIDTH-1 DOWNTO 0) <= diff_count;
DATA_COUNT(C_DATA_COUNT_WIDTH-1) <= '0' ;
END GENERATE;
gdcs : IF (C_DATA_COUNT_WIDTH <= C_RD_PNTR_WIDTH) GENERATE
DATA_COUNT <=
diff_count(C_RD_PNTR_WIDTH-1 DOWNTO C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH);
END GENERATE;
END GENERATE gdc;
gndc : IF (C_HAS_DATA_COUNT = 0) GENERATE
DATA_COUNT <= (OTHERS => '0');
END GENERATE gndc;
-------------------------------------------------------------------------------
--Calculate WR_ACK based on C_WR_ACK_LOW parameters
-------------------------------------------------------------------------------
gwalow : IF (C_WR_ACK_LOW = 0) GENERATE
WR_ACK <= wr_ack_i;
END GENERATE gwalow;
gwahgh : IF (C_WR_ACK_LOW = 1) GENERATE
WR_ACK <= NOT wr_ack_i;
END GENERATE gwahgh;
-------------------------------------------------------------------------------
--Calculate OVERFLOW based on C_OVERFLOW_LOW parameters
-------------------------------------------------------------------------------
govlow : IF (C_OVERFLOW_LOW = 0) GENERATE
OVERFLOW <= overflow_i;
END GENERATE govlow;
govhgh : IF (C_OVERFLOW_LOW = 1) GENERATE
OVERFLOW <= NOT overflow_i;
END GENERATE govhgh;
-------------------------------------------------------------------------------
--Calculate VALID based on C_PRELOAD_LATENCY and C_VALID_LOW settings
-------------------------------------------------------------------------------
gvlat1 : IF (C_PRELOAD_LATENCY = 1 OR C_PRELOAD_LATENCY=2) GENERATE
gnvl : IF (C_VALID_LOW = 0) GENERATE
VALID <= valid_d1;
END GENERATE gnvl;
gnvh : IF (C_VALID_LOW = 1) GENERATE
VALID <= NOT valid_d1;
END GENERATE gnvh;
END GENERATE gvlat1;
-------------------------------------------------------------------------------
-- Calculate UNDERFLOW based on C_PRELOAD_LATENCY and C_UNDERFLOW_LOW settings
-------------------------------------------------------------------------------
guflat1 : IF (C_PRELOAD_LATENCY = 1 OR C_PRELOAD_LATENCY=2) GENERATE
gnul : IF (C_UNDERFLOW_LOW = 0) GENERATE
UNDERFLOW <= underflow_i;
END GENERATE gnul;
gnuh : IF (C_UNDERFLOW_LOW = 1) GENERATE
UNDERFLOW <= NOT underflow_i;
END GENERATE gnuh;
END GENERATE guflat1;
FULL <= full_i;
gaf_ss: IF (C_HAS_ALMOST_FULL = 1 OR C_PROG_FULL_TYPE > 2 OR C_PROG_EMPTY_TYPE > 2) GENERATE
BEGIN
ALMOST_FULL <= almost_full_i;
END GENERATE gaf_ss;
gafn_ss: IF (C_HAS_ALMOST_FULL = 0 AND C_PROG_FULL_TYPE <= 2 AND C_PROG_EMPTY_TYPE <= 2) GENERATE
BEGIN
ALMOST_FULL <= '0';
END GENERATE gafn_ss;
EMPTY <= empty_i;
gae_ss: IF (C_HAS_ALMOST_EMPTY = 1) GENERATE
BEGIN
ALMOST_EMPTY <= almost_empty_i;
END GENERATE gae_ss;
gaen_ss: IF (C_HAS_ALMOST_EMPTY = 0) GENERATE
BEGIN
ALMOST_EMPTY <= '0';
END GENERATE gaen_ss;
write_allow <= WR_EN AND (NOT full_i);
read_allow <= RD_EN AND (NOT empty_i);
gen_read_allow_for_dc_fwft: IF(C_PRELOAD_REGS =1 AND C_PRELOAD_LATENCY =0) GENERATE
read_allow_dc <= RD_EN_USER AND (NOT USER_EMPTY_FB);
END GENERATE gen_read_allow_for_dc_fwft;
gen_read_allow_for_dc_std: IF(NOT(C_PRELOAD_REGS =1 AND C_PRELOAD_LATENCY =0)) GENERATE
read_allow_dc <= read_allow;
END GENERATE gen_read_allow_for_dc_std;
wrptr_proc : PROCESS (CLK, rst_i)
BEGIN
IF (rst_i = '1') THEN
wr_pntr <= (OTHERS => '0');
ELSIF (CLK'event AND CLK = '1') THEN
IF (srst_wrst_busy = '1') THEN
wr_pntr <= (OTHERS => '0') AFTER C_TCQ;
ELSIF (write_allow = '1') THEN
wr_pntr <= wr_pntr + "1" AFTER C_TCQ;
END IF;
END IF;
END PROCESS wrptr_proc;
gecc_mem: IF (C_USE_ECC > 0 AND C_ERROR_INJECTION_TYPE /= 0) GENERATE
wr_mem : PROCESS (CLK)
BEGIN
IF (CLK'event AND CLK = '1') THEN
IF (write_allow = '1') THEN
memory(conv_integer(wr_pntr)) <= INJECTDBITERR & INJECTSBITERR & DIN AFTER C_TCQ;
END IF;
END IF;
END PROCESS wr_mem;
END GENERATE gecc_mem;
gnecc_mem: IF NOT (C_USE_ECC > 0 AND C_ERROR_INJECTION_TYPE /= 0) GENERATE
wr_mem : PROCESS (CLK)
BEGIN
IF (CLK'event AND CLK = '1') THEN
IF (write_allow = '1') THEN
memory(conv_integer(wr_pntr)) <= DIN AFTER C_TCQ;
END IF;
END IF;
END PROCESS wr_mem;
END GENERATE gnecc_mem;
rdptr_proc : PROCESS (CLK, rst_i)
BEGIN
IF (rst_i = '1') THEN
rd_pntr <= (OTHERS => '0');
ELSIF (CLK'event AND CLK = '1') THEN
IF (srst_rrst_busy = '1') THEN
rd_pntr <= (OTHERS => '0') AFTER C_TCQ;
ELSIF (read_allow = '1') THEN
rd_pntr <= rd_pntr + "1" AFTER C_TCQ;
END IF;
END IF;
END PROCESS rdptr_proc;
-------------------------------------------------------------------------------
--Assign RD_DATA_COUNT and WR_DATA_COUNT
-------------------------------------------------------------------------------
rdc: IF (C_HAS_RD_DATA_COUNT=1 AND C_USE_FWFT_DATA_COUNT = 1) GENERATE
RD_DATA_COUNT <= rd_data_count_int(C_RD_PNTR_WIDTH DOWNTO C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH);
END GENERATE rdc;
nrdc: IF (C_HAS_RD_DATA_COUNT=0) GENERATE
RD_DATA_COUNT <= (OTHERS=>'0');
END GENERATE nrdc;
wdc: IF (C_HAS_WR_DATA_COUNT = 1 AND C_USE_FWFT_DATA_COUNT = 1) GENERATE
WR_DATA_COUNT <= wr_data_count_int(C_WR_PNTR_WIDTH DOWNTO C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH);
END GENERATE wdc;
nwdc: IF (C_HAS_WR_DATA_COUNT=0) GENERATE
WR_DATA_COUNT <= (OTHERS=>'0');
END GENERATE nwdc;
-------------------------------------------------------------------------------
-- Counter that determines the FWFT read duration.
-------------------------------------------------------------------------------
-- C_PRELOAD_LATENCY will be 0 for Non-Built-in FIFO with FWFT.
grd_fwft: IF (C_PRELOAD_LATENCY = 0) GENERATE
SIGNAL user_empty_fb_d1 : std_logic := '1';
BEGIN
grd_fwft_proc : PROCESS (CLK, rst_i)
BEGIN
IF (rst_i = '1') THEN
rd_fwft_cnt <= (others => '0');
user_empty_fb_d1 <= '1';
stage1_valid <= '0';
stage2_valid <= '0';
ELSIF (CLK'event AND CLK = '1') THEN
-- user_empty_fb_d1 <= USER_EMPTY_FB;
user_empty_fb_d1 <= empty_i;
IF (user_empty_fb_d1 = '0' AND empty_i = '1') THEN
rd_fwft_cnt <= (others => '0') AFTER C_TCQ;
ELSIF (empty_i = '0') THEN
IF (RD_EN = '1' AND rd_fwft_cnt < X"5") THEN
rd_fwft_cnt <= rd_fwft_cnt + "1" AFTER C_TCQ;
END IF;
END IF;
IF (stage1_valid = '0' AND stage2_valid = '0') THEN
IF (empty_i = '0') THEN
stage1_valid <= '1' AFTER C_TCQ;
ELSE
stage1_valid <= '0' AFTER C_TCQ;
END IF;
ELSIF (stage1_valid = '1' AND stage2_valid = '0') THEN
IF (empty_i = '1') THEN
stage1_valid <= '0' AFTER C_TCQ;
stage2_valid <= '1' AFTER C_TCQ;
ELSE
stage1_valid <= '1' AFTER C_TCQ;
stage2_valid <= '1' AFTER C_TCQ;
END IF;
ELSIF (stage1_valid = '0' AND stage2_valid = '1') THEN
IF (empty_i = '1' AND RD_EN_USER = '1') THEN
stage1_valid <= '0' AFTER C_TCQ;
stage2_valid <= '0' AFTER C_TCQ;
ELSIF (empty_i = '0' AND RD_EN_USER = '1') THEN
stage1_valid <= '1' AFTER C_TCQ;
stage2_valid <= '0' AFTER C_TCQ;
ELSIF (empty_i = '0' AND RD_EN_USER = '0') THEN
stage1_valid <= '1' AFTER C_TCQ;
stage2_valid <= '1' AFTER C_TCQ;
ELSE
stage1_valid <= '0' AFTER C_TCQ;
stage2_valid <= '1' AFTER C_TCQ;
END IF;
ELSIF (stage1_valid = '1' AND stage2_valid = '1') THEN
IF (empty_i = '1' AND RD_EN_USER = '1') THEN
stage1_valid <= '0' AFTER C_TCQ;
stage2_valid <= '1' AFTER C_TCQ;
ELSE
stage1_valid <= '1' AFTER C_TCQ;
stage2_valid <= '1' AFTER C_TCQ;
END IF;
ELSE
stage1_valid <= '0' AFTER C_TCQ;
stage2_valid <= '0' AFTER C_TCQ;
END IF;
END IF;
END PROCESS grd_fwft_proc;
END GENERATE grd_fwft;
-------------------------------------------------------------------------------
-- Generate DOUT for common clock low latency FIFO
-------------------------------------------------------------------------------
gll_dout: IF(C_FIFO_TYPE = 2) GENERATE
SIGNAL dout_q : STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
dout_i <= memory(conv_integer(rd_pntr)) when (read_allow = '1') else dout_q;
dout_reg : PROCESS (CLK)
BEGIN
IF (CLK'event AND CLK = '1') THEN
dout_q <= dout_i AFTER C_TCQ;
END IF;
END PROCESS dout_reg;
END GENERATE gll_dout;
-------------------------------------------------------------------------------
-- Generate FULL flag
-------------------------------------------------------------------------------
gpad : IF (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) GENERATE
adj_rd_pntr_wr (C_WR_PNTR_WIDTH-1 DOWNTO C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH) <= rd_pntr;
adj_rd_pntr_wr(C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 DOWNTO 0) <= (OTHERS => '0');
END GENERATE gpad;
gtrim : IF (C_WR_PNTR_WIDTH <= C_RD_PNTR_WIDTH) GENERATE
adj_rd_pntr_wr <= rd_pntr(C_RD_PNTR_WIDTH-1 DOWNTO C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH);
END GENERATE gtrim;
comp1 <= '1' WHEN (adj_rd_pntr_wr = (wr_pntr + "1")) ELSE '0';
comp0 <= '1' WHEN (adj_rd_pntr_wr = wr_pntr) ELSE '0';
gf_wp_eq_rp: IF (C_WR_PNTR_WIDTH = C_RD_PNTR_WIDTH) GENERATE
going_full <= (comp1 AND write_allow AND NOT read_allow);
leaving_full <= (comp0 AND read_allow) OR RST_FULL_GEN;
END GENERATE gf_wp_eq_rp;
-- Write data width is bigger than read data width
-- Write depth is smaller than read depth
-- One write could be equal to 2 or 4 or 8 reads
gf_asym: IF (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) GENERATE
going_full <= comp1 AND write_allow AND (NOT (read_allow AND AND_REDUCE(rd_pntr(C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 DOWNTO 0))));
leaving_full <= (comp0 AND read_allow AND AND_REDUCE(rd_pntr(C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 DOWNTO 0))) OR RST_FULL_GEN;
END GENERATE gf_asym;
gf_wp_gt_rp: IF (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) GENERATE
going_full <= (comp1 AND write_allow AND NOT read_allow);
leaving_full <= (comp0 AND read_allow) OR RST_FULL_GEN;
END GENERATE gf_wp_gt_rp;
ram_full_comb <= going_full OR (NOT leaving_full AND full_i);
full_proc : PROCESS (CLK, RST_FULL_FF)
BEGIN
IF (RST_FULL_FF = '1') THEN
full_i <= int_2_std_logic(C_FULL_FLAGS_RST_VAL);
ELSIF (CLK'event AND CLK = '1') THEN
IF (srst_wrst_busy = '1') THEN
full_i <= int_2_std_logic(C_FULL_FLAGS_RST_VAL) AFTER C_TCQ;
ELSE
full_i <= ram_full_comb AFTER C_TCQ;
END IF;
END IF;
END PROCESS full_proc;
-------------------------------------------------------------------------------
-- Generate ALMOST_FULL flag
-------------------------------------------------------------------------------
fcomp2 <= '1' WHEN (adj_rd_pntr_wr = (wr_pntr + "10")) ELSE '0';
gaf_wp_eq_rp: IF (C_WR_PNTR_WIDTH = C_RD_PNTR_WIDTH) GENERATE
going_afull <= (fcomp2 AND write_allow AND NOT read_allow);
leaving_afull <= (comp1 AND read_allow AND NOT write_allow) OR RST_FULL_GEN;
END GENERATE gaf_wp_eq_rp;
gaf_wp_lt_rp: IF (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) GENERATE
going_afull <= fcomp2 AND write_allow AND (NOT (read_allow AND AND_REDUCE(rd_pntr(C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 DOWNTO 0))));
leaving_afull <= (comp1 AND (NOT write_allow) AND read_allow AND AND_REDUCE(rd_pntr(C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 DOWNTO 0))) OR RST_FULL_GEN;
END GENERATE gaf_wp_lt_rp;
gaf_wp_gt_rp: IF (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) GENERATE
going_afull <= (fcomp2 AND write_allow AND NOT read_allow);
leaving_afull <= ((comp0 OR comp1 OR fcomp2) AND read_allow) OR RST_FULL_GEN;
END GENERATE gaf_wp_gt_rp;
ram_afull_comb <= going_afull OR (NOT leaving_afull AND almost_full_i);
af_proc : PROCESS (CLK, RST_FULL_FF)
BEGIN
IF (RST_FULL_FF = '1') THEN
almost_full_i <= int_2_std_logic(C_FULL_FLAGS_RST_VAL);
ELSIF (CLK'event AND CLK = '1') THEN
IF (srst_wrst_busy = '1') THEN
almost_full_i <= int_2_std_logic(C_FULL_FLAGS_RST_VAL) AFTER C_TCQ;
ELSE
almost_full_i <= ram_afull_comb AFTER C_TCQ;
END IF;
END IF;
END PROCESS af_proc;
-------------------------------------------------------------------------------
-- Generate EMPTY flag
-------------------------------------------------------------------------------
pad : IF (C_RD_PNTR_WIDTH>C_WR_PNTR_WIDTH) GENERATE
adj_wr_pntr_rd(C_RD_PNTR_WIDTH-1 DOWNTO C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH)
<= wr_pntr;
adj_wr_pntr_rd(C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 DOWNTO 0)
<= (OTHERS => '0');
END GENERATE pad;
trim : IF (C_RD_PNTR_WIDTH<=C_WR_PNTR_WIDTH) GENERATE
adj_wr_pntr_rd
<= wr_pntr(C_WR_PNTR_WIDTH-1 DOWNTO C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH);
END GENERATE trim;
ecomp1 <= '1' WHEN (adj_wr_pntr_rd = (rd_pntr + "1")) ELSE '0';
ecomp0 <= '1' WHEN (adj_wr_pntr_rd = rd_pntr) ELSE '0';
ge_wp_eq_rp: IF (C_WR_PNTR_WIDTH = C_RD_PNTR_WIDTH) GENERATE
going_empty <= (ecomp1 AND (NOT write_allow) AND read_allow);
leaving_empty <= (ecomp0 AND write_allow);
END GENERATE ge_wp_eq_rp;
ge_wp_lt_rp: IF (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) GENERATE
going_empty <= (ecomp1 AND (NOT write_allow) AND read_allow);
leaving_empty <= (ecomp0 AND write_allow);
END GENERATE ge_wp_lt_rp;
ge_wp_gt_rp: IF (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) GENERATE
going_empty <= ecomp1 AND read_allow AND (NOT(write_allow AND AND_REDUCE(wr_pntr(C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 DOWNTO 0))));
leaving_empty <= ecomp0 AND write_allow AND AND_REDUCE(wr_pntr(C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 DOWNTO 0));
END GENERATE ge_wp_gt_rp;
ram_empty_comb <= going_empty OR (NOT leaving_empty AND empty_i);
empty_proc : PROCESS (CLK, rst_i)
BEGIN
IF (rst_i = '1') THEN
empty_i <= '1';
ELSIF (CLK'event AND CLK = '1') THEN
IF (srst_rrst_busy = '1') THEN
empty_i <= '1' AFTER C_TCQ;
ELSE
empty_i <= ram_empty_comb AFTER C_TCQ;
END IF;
END IF;
END PROCESS empty_proc;
-------------------------------------------------------------------------------
-- Generate data_count_int flags for RD_DATA_COUNT and WR_DATA_COUNT
-------------------------------------------------------------------------------
rd_depth_gt_wr: IF (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) GENERATE
SIGNAL decr_by_one : std_logic := '0';
SIGNAL incr_by_ratio : std_logic := '0';
BEGIN
ratio <= int_2_std_logic_vector(if_then_else(C_DEPTH_RATIO_RD > C_DEPTH_RATIO_WR, C_DEPTH_RATIO_RD, C_DEPTH_RATIO_WR), C_GRTR_PNTR_WIDTH+1);
one <= int_2_std_logic_vector(1, C_GRTR_PNTR_WIDTH+1);
decr_by_one <= read_allow_dc;
incr_by_ratio <= write_allow;
cntr: PROCESS (CLK, rst_i)
BEGIN
IF (rst_i = '1') THEN
count_dc <= int_2_std_logic_vector(0,C_GRTR_PNTR_WIDTH+1);
ELSIF CLK'event AND CLK = '1' THEN
IF (srst_wrst_busy = '1') THEN
count_dc <= int_2_std_logic_vector(0,C_GRTR_PNTR_WIDTH+1)
AFTER C_TCQ;
ELSE
IF decr_by_one = '1' THEN
IF incr_by_ratio = '0' THEN
count_dc <= count_dc - one AFTER C_TCQ;
ELSE
count_dc <= count_dc - one + ratio AFTER C_TCQ;
END IF;
ELSE
IF incr_by_ratio = '0' THEN
count_dc <= count_dc AFTER C_TCQ;
ELSE
count_dc <= count_dc + ratio AFTER C_TCQ;
END IF;
END IF;
END IF;
END IF;
END PROCESS cntr;
rd_data_count_int <= count_dc;
wr_data_count_int <= count_dc(C_RD_PNTR_WIDTH DOWNTO C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH);
END GENERATE rd_depth_gt_wr;
wr_depth_gt_rd: IF (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) GENERATE
SIGNAL incr_by_one : std_logic := '0';
SIGNAL decr_by_ratio : std_logic := '0';
BEGIN
ratio <= int_2_std_logic_vector(if_then_else(C_DEPTH_RATIO_RD > C_DEPTH_RATIO_WR, C_DEPTH_RATIO_RD, C_DEPTH_RATIO_WR), C_GRTR_PNTR_WIDTH+1);
one <= int_2_std_logic_vector(1, C_GRTR_PNTR_WIDTH+1);
incr_by_one <= write_allow;
decr_by_ratio <= read_allow_dc;
cntr: PROCESS (CLK, RST)
BEGIN
IF (rst_i = '1' ) THEN
count_dc <= int_2_std_logic_vector(0,C_GRTR_PNTR_WIDTH+1);
ELSIF CLK'event AND CLK = '1' THEN
IF (srst_wrst_busy='1') THEN
count_dc <= int_2_std_logic_vector(0,C_GRTR_PNTR_WIDTH+1)
AFTER C_TCQ;
ELSE
IF incr_by_one = '1' THEN
IF decr_by_ratio = '0' THEN
count_dc <= count_dc + one AFTER C_TCQ;
ELSE
count_dc <= count_dc + one - ratio AFTER C_TCQ;
END IF;
ELSE
IF decr_by_ratio = '0' THEN
count_dc <= count_dc AFTER C_TCQ;
ELSE
count_dc <= count_dc - ratio AFTER C_TCQ;
END IF;
END IF;
END IF;
END IF;
END PROCESS cntr;
wr_data_count_int <= count_dc;
rd_data_count_int <= count_dc(C_WR_PNTR_WIDTH DOWNTO C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH);
END GENERATE wr_depth_gt_rd;
-------------------------------------------------------------------------------
-- Generate ALMOST_EMPTY flag
-------------------------------------------------------------------------------
ecomp2 <= '1' WHEN (adj_wr_pntr_rd = (rd_pntr + "10")) ELSE '0';
gae_wp_eq_rp: IF (C_WR_PNTR_WIDTH = C_RD_PNTR_WIDTH) GENERATE
going_aempty <= (ecomp2 AND (NOT write_allow) AND read_allow);
leaving_aempty <= (ecomp1 AND write_allow AND (NOT read_allow));
END GENERATE gae_wp_eq_rp;
gae_wp_lt_rp: IF (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) GENERATE
going_aempty <= (ecomp2 AND (NOT write_allow) AND read_allow);
leaving_aempty <= ((ecomp0 OR ecomp1 OR ecomp2) AND write_allow);
END GENERATE gae_wp_lt_rp;
gae_wp_gt_rp: IF (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) GENERATE
going_aempty <= ecomp2 AND read_allow AND (NOT(write_allow AND AND_REDUCE(wr_pntr(C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 DOWNTO 0))));
leaving_aempty <= ecomp1 AND (NOT read_allow) AND write_allow AND AND_REDUCE(wr_pntr(C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 DOWNTO 0));
END GENERATE gae_wp_gt_rp;
ram_aempty_comb <= going_aempty OR (NOT leaving_aempty AND almost_empty_i);
ae_proc : PROCESS (CLK, rst_i)
BEGIN
IF (rst_i = '1') THEN
almost_empty_i <= '1';
ELSIF (CLK'event AND CLK = '1') THEN
IF (srst_rrst_busy = '1') THEN
almost_empty_i <= '1' AFTER C_TCQ;
ELSE
almost_empty_i <= ram_aempty_comb AFTER C_TCQ;
END IF;
END IF;
END PROCESS ae_proc;
-------------------------------------------------------------------------------
-- synchronous FIFO using linked lists
-------------------------------------------------------------------------------
gnll_cc_fifo: IF (C_FIFO_TYPE /= 2) GENERATE
FIFO_PROC : PROCESS (CLK, rst_i, wr_pntr)
--Declare the linked-list head/tail pointers and the size value
VARIABLE head : listptr;
VARIABLE tail : listptr;
VARIABLE size : integer := 0;
VARIABLE cntr : integer := 0;
VARIABLE cntr_size_var_int : integer := 0;
--Data is the internal version of the DOUT bus
VARIABLE data : std_logic_vector(c_dout_width - 1 DOWNTO 0)
:= hexstr_to_std_logic_vec( C_DOUT_RST_VAL, c_dout_width);
VARIABLE err_type : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
--Temporary values for calculating adjusted prog_empty/prog_full thresholds
VARIABLE prog_empty_actual_assert_thresh : integer := 0;
VARIABLE prog_empty_actual_negate_thresh : integer := 0;
VARIABLE prog_full_actual_assert_thresh : integer := 0;
VARIABLE prog_full_actual_negate_thresh : integer := 0;
VARIABLE diff_pntr : integer := 0;
BEGIN
-- Calculate the current contents of the FIFO (size)
-- Warning: This value should only be calculated once each time this
-- process is entered.
-- It is updated instantaneously for both write and read operations,
-- so it is not ideal to use for signals which must consider the
-- latency of crossing clock domains.
-- cntr_size_var_int is updated only once when the process is entered
-- This variable is used in the conditions instead of cntr which has the
-- latest value.
cntr_size_var_int := cntr;
-- RESET CONDITIONS
IF rst_i = '1' THEN
wr_point <= 0 after C_TCQ;
wr_point_d1 <= 0 after C_TCQ;
wr_point_d2 <= 0 after C_TCQ;
wr_pntr_rd1 <= (OTHERS => '0') after C_TCQ;
rd_pntr_wr <= (OTHERS => '0') after C_TCQ;
--Create new linked list
newlist(head, tail,cntr);
diff_pntr := 0;
---------------------------------------------------------------------------
-- Write to FIFO
---------------------------------------------------------------------------
ELSIF CLK'event AND CLK = '1' THEN
IF srst_wrst_busy = '1' THEN
wr_point <= 0 after C_TCQ;
wr_point_d1 <= 0 after C_TCQ;
wr_point_d2 <= 0 after C_TCQ;
wr_pntr_rd1 <= (OTHERS => '0') after C_TCQ;
rd_pntr_wr <= (OTHERS => '0') after C_TCQ;
--Create new linked list
newlist(head, tail,cntr);
diff_pntr := 0;
ELSE
-- the binary to gray converion
wr_pntr_rd1 <= wr_pntr after C_TCQ;
rd_pntr_wr <= rd_pntr_wr_d1 after C_TCQ;
wr_point_d1 <= wr_point after C_TCQ;
wr_point_d2 <= wr_point_d1 after C_TCQ;
--The following IF statement setup default values of full_i and almost_full_i.
--The values might be overwritten in the next IF statement.
--If writing, then it is not possible to predict how many
--words will actually be in the FIFO after the write concludes
--(because the number of reads which happen in this time can
-- not be determined).
--Therefore, treat it pessimistically and always assume that
-- the write will happen without a read (assume the FIFO is
-- C_DEPTH_RATIO_RD fuller than it is).
--Note:
--1. cntr_size_var_int is the deepest depth between write depth and read depth
-- cntr_size_var_int/C_DEPTH_RATIO_RD is number of words in the write domain.
--2. cntr_size_var_int+C_DEPTH_RATIO_RD: number of write words in the next clock cycle
-- if wr_en=1 (C_DEPTH_RATIO_RD=one write word)
--3. For asymmetric FIFO, if write width is narrower than read width. Don't
-- have to consider partial words.
--4. For asymmetric FIFO, if read width is narrower than write width,
-- the worse case that FIFO is going to full is depicted in the following
-- diagram. Both rd_pntr_a and rd_pntr_b will cause FIFO full. rd_pntr_a
-- is the worse case. Therefore, in the calculation, actual FIFO depth is
-- substarcted to one write word and added one read word.
-- -------
-- | | |
-- wr_pntr-->| |---
-- | | |
-- ---|---
-- | | |
-- | |---
-- | | |
-- ---|---
-- | | |<--rd_pntr_a
-- | |---
-- | | |<--rd_pntr_b
-- ---|---
-- Update full_i and almost_full_i if user is writing to the FIFO.
-- Assign overflow and wr_ack.
IF WR_EN = '1' THEN
IF full_i /= '1' THEN
-- User is writing to a FIFO which is NOT reporting FULL
IF cntr_size_var_int/C_DEPTH_RATIO_RD = C_FIFO_WR_DEPTH THEN
-- FIFO really is Full
--Report Overflow and do not acknowledge the write
ELSIF cntr_size_var_int/C_DEPTH_RATIO_RD + 1 = C_FIFO_WR_DEPTH THEN
-- FIFO is almost full
-- This write will succeed, and FIFO will go FULL
FOR h IN C_DEPTH_RATIO_RD DOWNTO 1 LOOP
add(head, tail,
DIN((C_SMALLER_DATA_WIDTH*h)-1 DOWNTO C_SMALLER_DATA_WIDTH*(h-1)),cntr,
(width_gt1 & INJECTDBITERR & INJECTSBITERR));
END LOOP;
wr_point <= (wr_point + 1) MOD C_WR_DEPTH after C_TCQ;
ELSIF cntr_size_var_int/C_DEPTH_RATIO_RD + 2 = C_FIFO_WR_DEPTH THEN
-- FIFO is one away from almost full
-- This write will succeed, and FIFO will go almost_full_i
FOR h IN C_DEPTH_RATIO_RD DOWNTO 1 LOOP
add(head, tail,
DIN((C_SMALLER_DATA_WIDTH*h)-1 DOWNTO C_SMALLER_DATA_WIDTH*(h-1)),cntr,
(width_gt1 & INJECTDBITERR & INJECTSBITERR));
END LOOP;
wr_point <= (wr_point + 1) MOD C_WR_DEPTH after C_TCQ;
ELSE
-- FIFO is no where near FULL
--Write will succeed, no change in status
FOR h IN C_DEPTH_RATIO_RD DOWNTO 1 LOOP
add(head, tail,
DIN((C_SMALLER_DATA_WIDTH*h)-1 DOWNTO C_SMALLER_DATA_WIDTH*(h-1)),cntr,
(width_gt1 & INJECTDBITERR & INJECTSBITERR));
END LOOP;
wr_point <= (wr_point + 1) MOD C_WR_DEPTH after C_TCQ;
END IF;
ELSE --IF full_i = '1'
-- User is writing to a FIFO which IS reporting FULL
--Write will fail
END IF; --full_i
ELSE --WR_EN/='1'
--No write attempted, so neither overflow or acknowledge
END IF; --WR_EN
END IF; --srst
END IF; --CLK
---------------------------------------------------------------------------
-- Read from FIFO
---------------------------------------------------------------------------
IF (C_FIFO_TYPE < 2 AND C_MEMORY_TYPE < 2 AND C_USE_DOUT_RST = 1) THEN
IF (CLK'event AND CLK = '1') THEN
IF (rst_i = '1' OR srst_rrst_busy = '1') THEN
data := hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH);
END IF;
END IF;
END IF;
IF rst_i = '1' THEN
-- Whenever user is attempting to read from
-- an EMPTY FIFO, the core should report an underflow error, even if
-- the core is in a RESET condition.
rd_point <= 0 after C_TCQ;
rd_point_d1 <= 0 after C_TCQ;
rd_pntr_wr_d1 <= (OTHERS => '0') after C_TCQ;
wr_pntr_rd <= (OTHERS => '0') after C_TCQ;
-- DRAM resets asynchronously
IF (C_FIFO_TYPE < 2 AND (C_MEMORY_TYPE = 2 OR C_MEMORY_TYPE = 3 )AND C_USE_DOUT_RST = 1) THEN
data := hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH);
END IF;
-- Reset only if ECC is not selected as ECC does not support reset.
IF (C_USE_ECC = 0) THEN
err_type := (OTHERS => '0');
END IF ;
ELSIF CLK'event AND CLK = '1' THEN
-- ELSE
IF (srst_rrst_busy= '1') THEN
IF (C_FIFO_TYPE < 2 AND (C_MEMORY_TYPE = 2 OR C_MEMORY_TYPE = 3 ) AND C_USE_DOUT_RST = 1) THEN
data := hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH);
END IF;
END IF;
IF srst_rrst_busy = '1' THEN
-- Whenever user is attempting to read from
-- an EMPTY FIFO, the core should report an underflow error, even if
-- the core is in a RESET condition.
rd_point <= 0 after C_TCQ;
rd_point_d1 <= 0 after C_TCQ;
rd_pntr_wr_d1 <= (OTHERS => '0') after C_TCQ;
wr_pntr_rd <= (OTHERS => '0') after C_TCQ;
-- DRAM resets asynchronously
IF (C_FIFO_TYPE < 2 AND C_MEMORY_TYPE = 2 AND C_USE_DOUT_RST = 1) THEN
data := hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH);
END IF;
-- Reset only if ECC is not selected as ECC does not support reset.
IF (C_USE_ECC = 0) THEN
err_type := (OTHERS => '0');
END IF ;
ELSE
-- Delay the read pointer before passing to CLK domain to accommodate
-- the binary to gray converion
rd_pntr_wr_d1 <= rd_pntr after C_TCQ;
wr_pntr_rd <= wr_pntr_rd1 after C_TCQ;
rd_point_d1 <= rd_point after C_TCQ;
---------------------------------------------------------------------------
-- Read Latency 1
---------------------------------------------------------------------------
--The following IF statement setup default values of empty_i and
--almost_empty_i. The values might be overwritten in the next IF statement.
--Note:
--cntr_size_var_int/C_DEPTH_RATIO_WR : number of words in read domain.
IF (RD_EN = '1') THEN
IF empty_i /= '1' THEN
IF cntr_size_var_int/C_DEPTH_RATIO_WR = 2 THEN
--FIFO is going almost empty
FOR h IN C_DEPTH_RATIO_WR DOWNTO 1 LOOP
read(tail,
data((C_SMALLER_DATA_WIDTH*h)-1 DOWNTO C_SMALLER_DATA_WIDTH*(h-1)),
err_type);
remove(head, tail,cntr);
END LOOP;
rd_point <= (rd_point + 1) MOD C_RD_DEPTH after C_TCQ;
ELSIF cntr_size_var_int/C_DEPTH_RATIO_WR = 1 THEN
--FIFO is going empty
FOR h IN C_DEPTH_RATIO_WR DOWNTO 1 LOOP
read(tail,
data((C_SMALLER_DATA_WIDTH*h)-1 DOWNTO C_SMALLER_DATA_WIDTH*(h-1)),
err_type);
remove(head, tail,cntr);
END LOOP;
rd_point <= (rd_point + 1) MOD C_RD_DEPTH after C_TCQ;
ELSIF cntr_size_var_int/C_DEPTH_RATIO_WR = 0 THEN
--FIFO is empty
ELSE
--FIFO is not empty
FOR h IN C_DEPTH_RATIO_WR DOWNTO 1 LOOP
read(tail,
data((C_SMALLER_DATA_WIDTH*h)-1 DOWNTO C_SMALLER_DATA_WIDTH*(h-1)),
err_type);
remove(head, tail,cntr);
END LOOP;
rd_point <= (rd_point + 1) MOD C_RD_DEPTH after C_TCQ;
END IF;
ELSE
--FIFO is empty
END IF;
END IF; --RD_EN
END IF; --srst
END IF; --CLK
dout_i <= data after C_TCQ;
sbiterr_i <= err_type(0) after C_TCQ;
dbiterr_i <= err_type(1) after C_TCQ;
END PROCESS;
END GENERATE gnll_cc_fifo;
-------------------------------------------------------------------------------
-- Generate PROG_FULL and PROG_EMPTY flags
-------------------------------------------------------------------------------
gpf_pe: IF (C_PROG_FULL_TYPE /= 0 OR C_PROG_EMPTY_TYPE /= 0) GENERATE
SIGNAL diff_pntr : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL diff_pntr_max : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL diff_pntr_pe : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL diff_pntr_pe_asym : std_logic_vector(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL adj_wr_pntr_rd_asym : std_logic_vector(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_pntr_asym : std_logic_vector(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL diff_pntr_pe_max : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL diff_pntr_reg1 : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL diff_pntr_pe_reg1 : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL diff_pntr_reg2 : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL diff_pntr_pe_reg2 : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL write_allow_q : std_logic := '0';
SIGNAL read_allow_q : std_logic := '0';
SIGNAL write_only : std_logic := '0';
SIGNAL write_only_q : std_logic := '0';
SIGNAL read_only : std_logic := '0';
SIGNAL read_only_q : std_logic := '0';
SIGNAL prog_full_i : std_logic := int_2_std_logic(C_FULL_FLAGS_RST_VAL);
SIGNAL prog_empty_i : std_logic := '1';
SIGNAL full_reg : std_logic := '0';
SIGNAL rst_full_ff_reg1 : std_logic := '0';
SIGNAL rst_full_ff_reg2 : std_logic := '0';
SIGNAL carry : std_logic := '0';
CONSTANT WR_RD_RATIO_I_PF : integer := if_then_else((C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH), (C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH), 0);
CONSTANT WR_RD_RATIO_PF : integer := 2**WR_RD_RATIO_I_PF;
-- CONSTANT WR_RD_RATIO_I_PE : integer := if_then_else((C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH), (C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH), 0);
-- CONSTANT WR_RD_RATIO_PE : integer := 2**WR_RD_RATIO_I_PE;
-- EXTRA_WORDS = 2 * C_DEPTH_RATIO_WR / C_DEPTH_RATIO_RD
-- WR_DEPTH : RD_DEPTH = 1:2 => EXTRA_WORDS = 1
-- WR_DEPTH : RD_DEPTH = 1:4 => EXTRA_WORDS = 1 (rounded to ceiling)
-- WR_DEPTH : RD_DEPTH = 2:1 => EXTRA_WORDS = 4
-- WR_DEPTH : RD_DEPTH = 4:1 => EXTRA_WORDS = 8
--CONSTANT EXTRA_WORDS : integer := if_then_else ((C_DEPTH_RATIO_WR = 1),2,
-- (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD));
CONSTANT EXTRA_WORDS_PF : integer := 2*WR_RD_RATIO_PF;
--CONSTANT EXTRA_WORDS_PE : integer := 2*WR_RD_RATIO_PE;
CONSTANT C_PF_ASSERT_VAL : integer := if_then_else(C_PRELOAD_LATENCY = 0,
C_PROG_FULL_THRESH_ASSERT_VAL - EXTRA_WORDS_PF, -- FWFT
C_PROG_FULL_THRESH_ASSERT_VAL); -- STD
CONSTANT C_PF_NEGATE_VAL : integer := if_then_else(C_PRELOAD_LATENCY = 0,
C_PROG_FULL_THRESH_NEGATE_VAL - EXTRA_WORDS_PF, -- FWFT
C_PROG_FULL_THRESH_NEGATE_VAL); -- STD
CONSTANT C_PE_ASSERT_VAL : integer := if_then_else(C_PRELOAD_LATENCY = 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL - 2,
C_PROG_EMPTY_THRESH_ASSERT_VAL);
CONSTANT C_PE_NEGATE_VAL : integer := if_then_else(C_PRELOAD_LATENCY = 0,
C_PROG_EMPTY_THRESH_NEGATE_VAL - 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL);
BEGIN
diff_pntr_pe_max <= DIFF_MAX_RD;
dif_pntr_sym: IF (IS_ASYMMETRY = 0) GENERATE
write_only <= write_allow AND NOT read_allow;
read_only <= read_allow AND NOT write_allow;
END GENERATE dif_pntr_sym;
dif_pntr_asym: IF (IS_ASYMMETRY = 1) GENERATE
gpf_wp_lt_rp: IF (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) GENERATE
read_only <= read_allow AND AND_REDUCE(rd_pntr(C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 DOWNTO 0)) AND NOT(write_allow);
write_only <= write_allow AND NOT (read_allow AND AND_REDUCE(rd_pntr(C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 DOWNTO 0)));
END GENERATE gpf_wp_lt_rp;
gpf_wp_gt_rp: IF (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) GENERATE
read_only <= read_allow AND NOT(write_allow AND AND_REDUCE(wr_pntr(C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 DOWNTO 0)));
write_only<= write_allow AND AND_REDUCE(wr_pntr(C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 DOWNTO 0)) AND NOT(read_allow);
END GENERATE gpf_wp_gt_rp;
END GENERATE dif_pntr_asym;
dif_cal_pntr_sym: IF (IS_ASYMMETRY = 0) GENERATE
wr_rd_q_proc : PROCESS (CLK)
BEGIN
IF (rst_i = '1') THEN
write_only_q <= '0';
read_only_q <= '0';
diff_pntr_reg1 <= (OTHERS => '0');
diff_pntr_pe_reg1 <= (OTHERS => '0');
diff_pntr_reg2 <= (OTHERS => '0');
diff_pntr_pe_reg2 <= (OTHERS => '0');
ELSIF (CLK'event AND CLK = '1') THEN
IF (srst_i = '1' OR srst_rrst_busy = '1' OR srst_wrst_busy = '1' ) THEN
IF (srst_rrst_busy = '1') THEN
read_only_q <= '0' AFTER C_TCQ;
diff_pntr_pe_reg1 <= (OTHERS => '0') AFTER C_TCQ;
diff_pntr_pe_reg2 <= (OTHERS => '0');
END IF;
IF (srst_wrst_busy = '1') THEN
write_only_q <= '0' AFTER C_TCQ;
diff_pntr_reg1 <= (OTHERS => '0') AFTER C_TCQ;
diff_pntr_reg2 <= (OTHERS => '0');
END IF;
ELSE
write_only_q <= write_only AFTER C_TCQ;
read_only_q <= read_only AFTER C_TCQ;
diff_pntr_reg2 <= diff_pntr_reg1 AFTER C_TCQ;
diff_pntr_pe_reg2 <= diff_pntr_pe_reg1 AFTER C_TCQ;
-- Add 1 to the difference pointer value when only write happens.
IF (write_only = '1') THEN
diff_pntr_reg1 <= wr_pntr - adj_rd_pntr_wr + "1" AFTER C_TCQ;
ELSE
diff_pntr_reg1 <= wr_pntr - adj_rd_pntr_wr AFTER C_TCQ;
END IF;
-- Add 1 to the difference pointer value when write or both write & read or no write & read happen.
IF (read_only = '1') THEN
diff_pntr_pe_reg1 <= adj_wr_pntr_rd - rd_pntr - "1" AFTER C_TCQ;
ELSE
diff_pntr_pe_reg1 <= adj_wr_pntr_rd - rd_pntr AFTER C_TCQ;
END IF;
END IF;
END IF;
END PROCESS wr_rd_q_proc;
diff_pntr <= diff_pntr_reg1(C_WR_PNTR_WIDTH-1 downto 0);
diff_pntr_pe <= diff_pntr_pe_reg1(C_RD_PNTR_WIDTH-1 downto 0);
END GENERATE dif_cal_pntr_sym;
dif_cal_pntr_asym: IF (IS_ASYMMETRY = 1) GENERATE
adj_wr_pntr_rd_asym(C_RD_PNTR_WIDTH downto 1) <= adj_wr_pntr_rd;
adj_wr_pntr_rd_asym(0) <= '1';
rd_pntr_asym(C_RD_PNTR_WIDTH downto 1) <= not(rd_pntr);
rd_pntr_asym(0) <= '1';
wr_rd_q_proc : PROCESS (CLK)
BEGIN
IF (rst_i = '1') THEN
diff_pntr_pe_asym <= (OTHERS => '0');
full_reg <= '0';
rst_full_ff_reg1 <= '1';
rst_full_ff_reg2 <= '1';
diff_pntr <= (OTHERS => '0');
ELSIF (CLK'event AND CLK = '1') THEN
IF (srst_i = '1' OR srst_rrst_busy = '1' OR srst_wrst_busy = '1' ) THEN
IF (srst_rrst_busy = '1') THEN
rst_full_ff_reg1 <= '1' AFTER C_TCQ;
rst_full_ff_reg2 <= '1' AFTER C_TCQ;
full_reg <= '0' AFTER C_TCQ;
diff_pntr_pe_asym <= (OTHERS => '0') AFTER C_TCQ;
END IF;
IF (srst_wrst_busy = '1') THEN
diff_pntr <= (OTHERS => '0') AFTER C_TCQ;
END IF;
ELSE
write_only_q <= write_only AFTER C_TCQ;
read_only_q <= read_only AFTER C_TCQ;
diff_pntr_reg2 <= diff_pntr_reg1 AFTER C_TCQ;
diff_pntr_pe_reg2 <= diff_pntr_pe_reg1 AFTER C_TCQ;
rst_full_ff_reg1 <= RST_FULL_FF AFTER C_TCQ;
rst_full_ff_reg2 <= rst_full_ff_reg1 AFTER C_TCQ;
full_reg <= full_i AFTER C_TCQ;
diff_pntr_pe_asym <= adj_wr_pntr_rd_asym + rd_pntr_asym AFTER C_TCQ;
IF (full_i = '0') THEN
diff_pntr <= wr_pntr - adj_rd_pntr_wr AFTER C_TCQ;
END IF;
END IF;
END IF;
END PROCESS wr_rd_q_proc;
carry <= (NOT(OR_REDUCE(diff_pntr_pe_asym (C_RD_PNTR_WIDTH downto 1))));
diff_pntr_pe <= diff_pntr_pe_max when (full_reg = '1' AND rst_full_ff_reg2 = '0' AND carry = '1' ) else diff_pntr_pe_asym (C_RD_PNTR_WIDTH downto 1);
END GENERATE dif_cal_pntr_asym;
-------------------------------------------------------------------------------
-- Generate PROG_FULL flag
-------------------------------------------------------------------------------
gpf: IF (C_PROG_FULL_TYPE /= 0) GENERATE
-------------------------------------------------------------------------------
-- Generate PROG_FULL for single programmable threshold constant
-------------------------------------------------------------------------------
gpf1: IF (C_PROG_FULL_TYPE = 1) GENERATE
pf1_proc : PROCESS (CLK, RST_FULL_FF)
BEGIN
IF (RST_FULL_FF = '1') THEN
prog_full_i <= int_2_std_logic(C_FULL_FLAGS_RST_VAL);
ELSIF (CLK'event AND CLK = '1') THEN
IF (srst_wrst_busy = '1') THEN
prog_full_i <= int_2_std_logic(C_FULL_FLAGS_RST_VAL) AFTER C_TCQ;
ELSIF (IS_ASYMMETRY = 0) THEN
IF (RST_FULL_GEN = '1') THEN
prog_full_i <= '0' AFTER C_TCQ;
ELSIF ((conv_integer(diff_pntr) = C_PF_ASSERT_VAL) AND write_only_q = '1') THEN
prog_full_i <= '1' AFTER C_TCQ;
ELSIF ((conv_integer(diff_pntr) = C_PF_ASSERT_VAL) AND read_only_q = '1') THEN
prog_full_i <= '0' AFTER C_TCQ;
ELSE
prog_full_i <= prog_full_i AFTER C_TCQ;
END IF;
ELSE
IF (RST_FULL_GEN = '1') THEN
prog_full_i <= '0' AFTER C_TCQ;
ELSIF (RST_FULL_GEN = '0') THEN
IF ((diff_pntr) >= C_PF_ASSERT_VAL ) THEN
prog_full_i <= '1' AFTER C_TCQ;
ELSIF ((diff_pntr) < C_PF_ASSERT_VAL ) THEN
prog_full_i <= '0' AFTER C_TCQ;
ELSE
prog_full_i <= '0' AFTER C_TCQ;
END IF;
ELSE
prog_full_i <= prog_full_i AFTER C_TCQ;
END IF;
END IF;
END IF;
END PROCESS pf1_proc;
END GENERATE gpf1;
-------------------------------------------------------------------------------
-- Generate PROG_FULL for multiple programmable threshold constants
-------------------------------------------------------------------------------
gpf2: IF (C_PROG_FULL_TYPE = 2) GENERATE
pf2_proc : PROCESS (CLK, RST_FULL_FF)
BEGIN
IF (RST_FULL_FF = '1' AND C_HAS_RST = 1) THEN
prog_full_i <= int_2_std_logic(C_FULL_FLAGS_RST_VAL);
ELSIF (CLK'event AND CLK = '1') THEN
IF (srst_wrst_busy = '1') THEN
prog_full_i <= int_2_std_logic(C_FULL_FLAGS_RST_VAL) AFTER C_TCQ;
ELSIF (IS_ASYMMETRY = 0) THEN
IF (RST_FULL_GEN = '1') THEN
prog_full_i <= '0' AFTER C_TCQ;
ELSIF ((conv_integer(diff_pntr) = C_PF_ASSERT_VAL) AND write_only_q = '1') THEN
prog_full_i <= '1' AFTER C_TCQ;
ELSIF ((conv_integer(diff_pntr) = C_PF_NEGATE_VAL) AND read_only_q = '1') THEN
prog_full_i <= '0' AFTER C_TCQ;
ELSE
prog_full_i <= prog_full_i AFTER C_TCQ;
END IF;
ELSE
IF (RST_FULL_GEN = '1') THEN
prog_full_i <= '0' AFTER C_TCQ;
ELSIF (RST_FULL_GEN='0') THEN
IF (conv_integer(diff_pntr) >= C_PF_ASSERT_VAL ) THEN
prog_full_i <= '1' AFTER C_TCQ;
ELSIF (conv_integer(diff_pntr) < C_PF_NEGATE_VAL) THEN
prog_full_i <= '0' AFTER C_TCQ;
ELSE
prog_full_i <= prog_full_i AFTER C_TCQ;
END IF;
ELSE
prog_full_i <= prog_full_i AFTER C_TCQ;
END IF;
END IF;
END IF;
END PROCESS pf2_proc;
END GENERATE gpf2;
-------------------------------------------------------------------------------
-- Generate PROG_FULL for single programmable threshold input port
-------------------------------------------------------------------------------
gpf3: IF (C_PROG_FULL_TYPE = 3) GENERATE
SIGNAL pf_assert_val : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
pf_assert_val <= PROG_FULL_THRESH -int_2_std_logic_vector(EXTRA_WORDS_PF,C_WR_PNTR_WIDTH)WHEN (C_PRELOAD_LATENCY = 0) ELSE PROG_FULL_THRESH;
pf3_proc : PROCESS (CLK, RST_FULL_FF)
BEGIN
IF (RST_FULL_FF = '1') THEN
prog_full_i <= int_2_std_logic(C_FULL_FLAGS_RST_VAL);
ELSIF (CLK'event AND CLK = '1') THEN
IF (srst_wrst_busy = '1') THEN
prog_full_i <= int_2_std_logic(C_FULL_FLAGS_RST_VAL) AFTER C_TCQ;
ELSIF (IS_ASYMMETRY = 0) THEN
IF (RST_FULL_GEN = '1') THEN
prog_full_i <= '0' AFTER C_TCQ;
ELSIF (almost_full_i = '0') THEN
IF (conv_integer(diff_pntr) > pf_assert_val) THEN
prog_full_i <= '1' AFTER C_TCQ;
ELSIF (conv_integer(diff_pntr) = pf_assert_val) THEN
IF (read_only_q = '1') THEN
prog_full_i <= '0' AFTER C_TCQ;
ELSE
prog_full_i <= '1' AFTER C_TCQ;
END IF;
ELSE
prog_full_i <= '0' AFTER C_TCQ;
END IF;
ELSE
prog_full_i <= prog_full_i AFTER C_TCQ;
END IF;
ELSE
IF (RST_FULL_GEN = '1') THEN
prog_full_i <= '0' AFTER C_TCQ;
ELSIF (full_i='0') THEN
IF (conv_integer(diff_pntr) >= pf_assert_val) THEN
prog_full_i <= '1' AFTER C_TCQ;
ELSIF (conv_integer(diff_pntr) < pf_assert_val) THEN
prog_full_i <= '0' AFTER C_TCQ;
END IF;
ELSE
prog_full_i <= prog_full_i AFTER C_TCQ;
END IF;
END IF;
END IF;
END PROCESS pf3_proc;
END GENERATE gpf3;
-------------------------------------------------------------------------------
-- Generate PROG_FULL for multiple programmable threshold input ports
-------------------------------------------------------------------------------
gpf4: IF (C_PROG_FULL_TYPE = 4) GENERATE
SIGNAL pf_assert_val : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL pf_negate_val : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
pf_assert_val <= PROG_FULL_THRESH_ASSERT -int_2_std_logic_vector(EXTRA_WORDS_PF,C_WR_PNTR_WIDTH) WHEN (C_PRELOAD_LATENCY = 0) ELSE PROG_FULL_THRESH_ASSERT;
pf_negate_val <= PROG_FULL_THRESH_NEGATE -int_2_std_logic_vector(EXTRA_WORDS_PF,C_WR_PNTR_WIDTH) WHEN (C_PRELOAD_LATENCY = 0) ELSE PROG_FULL_THRESH_NEGATE;
pf4_proc : PROCESS (CLK, RST_FULL_FF)
BEGIN
IF (RST_FULL_FF = '1') THEN
prog_full_i <= int_2_std_logic(C_FULL_FLAGS_RST_VAL);
ELSIF (CLK'event AND CLK = '1') THEN
IF (srst_wrst_busy = '1') THEN
prog_full_i <= int_2_std_logic(C_FULL_FLAGS_RST_VAL) AFTER C_TCQ;
ELSIF (IS_ASYMMETRY = 0) THEN
IF (RST_FULL_GEN = '1') THEN
prog_full_i <= '0' AFTER C_TCQ;
ELSIF (almost_full_i = '0') THEN
IF (conv_integer(diff_pntr) >= pf_assert_val) THEN
prog_full_i <= '1' AFTER C_TCQ;
ELSIF (((conv_integer(diff_pntr) = pf_negate_val) AND read_only_q = '1') OR
(conv_integer(diff_pntr) < pf_negate_val)) THEN
prog_full_i <= '0' AFTER C_TCQ;
ELSE
prog_full_i <= prog_full_i AFTER C_TCQ;
END IF;
ELSE
prog_full_i <= prog_full_i AFTER C_TCQ;
END IF;
ELSE
IF (RST_FULL_GEN = '1') THEN
prog_full_i <= '0' AFTER C_TCQ;
ELSIF (full_i='0') THEN
IF (conv_integer(diff_pntr) >= pf_assert_val) THEN
prog_full_i <= '1' AFTER C_TCQ;
ELSIF(conv_integer(diff_pntr) < pf_negate_val) THEN
prog_full_i <= '0' AFTER C_TCQ;
ELSE
prog_full_i <= prog_full_i AFTER C_TCQ;
END IF;
ELSE
prog_full_i <= prog_full_i AFTER C_TCQ;
END IF;
END IF;
END IF;
END PROCESS pf4_proc;
END GENERATE gpf4;
PROG_FULL <= prog_full_i;
END GENERATE gpf;
-------------------------------------------------------------------------------
-- Generate PROG_EMPTY flag
-------------------------------------------------------------------------------
gpe: IF (C_PROG_EMPTY_TYPE /= 0) GENERATE
-------------------------------------------------------------------------------
-- Generate PROG_EMPTY for single programmable threshold constant
-------------------------------------------------------------------------------
gpe1: IF (C_PROG_EMPTY_TYPE = 1) GENERATE
pe1_proc : PROCESS (CLK, rst_i)
BEGIN
IF (rst_i = '1') THEN
prog_empty_i <= '1';
ELSIF (CLK'event AND CLK = '1') THEN
IF (srst_rrst_busy = '1') THEN
prog_empty_i <= '1' AFTER C_TCQ;
ELSE
IF (IS_ASYMMETRY = 0) THEN
IF ((conv_integer(diff_pntr_pe) = C_PE_ASSERT_VAL) AND read_only_q = '1') THEN
prog_empty_i <= '1' AFTER C_TCQ;
ELSIF ((conv_integer(diff_pntr_pe) = C_PE_ASSERT_VAL) AND write_only_q = '1') THEN
prog_empty_i <= '0' AFTER C_TCQ;
ELSE
prog_empty_i <= prog_empty_i AFTER C_TCQ;
END IF;
ELSE
IF (rst_i = '0') THEN
IF (diff_pntr_pe <= (C_PE_ASSERT_VAL)) THEN
prog_empty_i <= '1' AFTER C_TCQ;
ELSIF (diff_pntr_pe > (C_PE_ASSERT_VAL)) THEN
prog_empty_i <= '0' AFTER C_TCQ;
END IF;
ELSE
prog_empty_i <= prog_empty_i AFTER C_TCQ;
END IF;
END IF;
END IF;
END IF;
END PROCESS pe1_proc;
END GENERATE gpe1;
-------------------------------------------------------------------------------
-- Generate PROG_EMPTY for multiple programmable threshold constants
-------------------------------------------------------------------------------
gpe2: IF (C_PROG_EMPTY_TYPE = 2) GENERATE
pe2_proc : PROCESS (CLK, rst_i)
BEGIN
IF (rst_i = '1') THEN
prog_empty_i <= '1';
ELSIF (CLK'event AND CLK = '1') THEN
IF (srst_rrst_busy = '1') THEN
prog_empty_i <= '1' AFTER C_TCQ;
ELSE
IF (IS_ASYMMETRY = 0) THEN
IF ((conv_integer(diff_pntr_pe) = C_PE_ASSERT_VAL) AND read_only_q = '1') THEN
prog_empty_i <= '1' AFTER C_TCQ;
ELSIF ((conv_integer(diff_pntr_pe) = C_PE_NEGATE_VAL) AND write_only_q = '1') THEN
prog_empty_i <= '0' AFTER C_TCQ;
ELSE
prog_empty_i <= prog_empty_i AFTER C_TCQ;
END IF;
ELSE
IF (rst_i = '0') THEN
IF (conv_integer(diff_pntr_pe) <= (C_PE_ASSERT_VAL)) THEN
prog_empty_i <= '1' AFTER C_TCQ;
ELSIF (conv_integer(diff_pntr_pe) > (C_PE_NEGATE_VAL) ) THEN
prog_empty_i <= '0' AFTER C_TCQ;
ELSE
prog_empty_i <= prog_empty_i AFTER C_TCQ;
END IF;
ELSE
prog_empty_i <= prog_empty_i AFTER C_TCQ;
END IF;
END IF;
END IF;
END IF;
END PROCESS pe2_proc;
END GENERATE gpe2;
-------------------------------------------------------------------------------
-- Generate PROG_EMPTY for single programmable threshold input port
-------------------------------------------------------------------------------
gpe3: IF (C_PROG_EMPTY_TYPE = 3) GENERATE
SIGNAL pe_assert_val : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
pe_assert_val <= PROG_EMPTY_THRESH - "10" WHEN (C_PRELOAD_LATENCY = 0) ELSE PROG_EMPTY_THRESH;
pe3_proc : PROCESS (CLK, rst_i)
BEGIN
IF (rst_i = '1') THEN
prog_empty_i <= '1';
ELSIF (CLK'event AND CLK = '1') THEN
IF (srst_rrst_busy = '1') THEN
prog_empty_i <= '1' AFTER C_TCQ;
ELSIF (IS_ASYMMETRY = 0) THEN
IF (almost_full_i = '0') THEN
IF (conv_integer(diff_pntr_pe) < pe_assert_val) THEN
prog_empty_i <= '1' AFTER C_TCQ;
ELSIF (conv_integer(diff_pntr_pe) = pe_assert_val) THEN
IF (write_only_q = '1') THEN
prog_empty_i <= '0' AFTER C_TCQ;
ELSE
prog_empty_i <= '1' AFTER C_TCQ;
END IF;
ELSE
prog_empty_i <= '0' AFTER C_TCQ;
END IF;
ELSE
prog_empty_i <= prog_empty_i AFTER C_TCQ;
END IF;
ELSE
IF (conv_integer(diff_pntr_pe) <= pe_assert_val) THEN
prog_empty_i <= '1' AFTER C_TCQ;
ELSIF (conv_integer(diff_pntr_pe) > pe_assert_val) THEN
prog_empty_i <= '0' AFTER C_TCQ;
ELSE
prog_empty_i <= prog_empty_i AFTER C_TCQ;
END IF;
END IF;
END IF;
END PROCESS pe3_proc;
END GENERATE gpe3;
-------------------------------------------------------------------------------
-- Generate PROG_EMPTY for multiple programmable threshold input ports
-------------------------------------------------------------------------------
gpe4: IF (C_PROG_EMPTY_TYPE = 4) GENERATE
SIGNAL pe_assert_val : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL pe_negate_val : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
pe_assert_val <= PROG_EMPTY_THRESH_ASSERT - "10" WHEN (C_PRELOAD_LATENCY = 0) ELSE PROG_EMPTY_THRESH_ASSERT;
pe_negate_val <= PROG_EMPTY_THRESH_NEGATE - "10" WHEN (C_PRELOAD_LATENCY = 0) ELSE PROG_EMPTY_THRESH_NEGATE;
pe4_proc : PROCESS (CLK, rst_i)
BEGIN
IF (rst_i = '1') THEN
prog_empty_i <= '1';
ELSIF (CLK'event AND CLK = '1') THEN
IF (srst_rrst_busy = '1') THEN
prog_empty_i <= '1' AFTER C_TCQ;
ELSIF (IS_ASYMMETRY = 0) THEN
IF (almost_full_i = '0') THEN
IF (conv_integer(diff_pntr_pe) <= pe_assert_val) THEN
prog_empty_i <= '1' AFTER C_TCQ;
ELSIF (((conv_integer(diff_pntr_pe) = pe_negate_val) AND write_only_q = '1') OR
(conv_integer(diff_pntr_pe) > pe_negate_val)) THEN
prog_empty_i <= '0' AFTER C_TCQ;
ELSE
prog_empty_i <= prog_empty_i AFTER C_TCQ;
END IF;
ELSE
prog_empty_i <= prog_empty_i AFTER C_TCQ;
END IF;
ELSE
IF (conv_integer(diff_pntr_pe) <= (pe_assert_val)) THEN
prog_empty_i <= '1' AFTER C_TCQ;
ELSIF (conv_integer(diff_pntr_pe) > pe_negate_val) THEN
prog_empty_i <= '0' AFTER C_TCQ;
ELSE
prog_empty_i <= prog_empty_i AFTER C_TCQ;
END IF;
END IF;
END IF;
END PROCESS pe4_proc;
END GENERATE gpe4;
PROG_EMPTY <= prog_empty_i;
END GENERATE gpe;
END GENERATE gpf_pe;
-------------------------------------------------------------------------------
-- overflow_i generation: Synchronous FIFO
-------------------------------------------------------------------------------
govflw: IF (C_HAS_OVERFLOW = 1) GENERATE
g7s_ovflw: IF (NOT (C_FAMILY = "virtexu" OR C_FAMILY = "kintexu" OR C_FAMILY = "artixu" OR C_FAMILY = "virtexuplus" OR C_FAMILY = "zynquplus" OR C_FAMILY = "kintexuplus")) GENERATE
povflw: PROCESS (CLK)
BEGIN
IF CLK'event AND CLK = '1' THEN
overflow_i <= full_i AND WR_EN after C_TCQ;
END IF;
END PROCESS povflw;
END GENERATE g7s_ovflw;
g8s_ovflw: IF ((C_FAMILY = "virtexu" OR C_FAMILY = "kintexu" OR C_FAMILY = "artixu" OR C_FAMILY = "virtexuplus" OR C_FAMILY = "zynquplus" OR C_FAMILY = "kintexuplus")) GENERATE
povflw: PROCESS (CLK)
BEGIN
IF CLK'event AND CLK = '1' THEN
overflow_i <= (WR_RST_BUSY OR full_i) AND WR_EN after C_TCQ;
END IF;
END PROCESS povflw;
END GENERATE g8s_ovflw;
END GENERATE govflw;
-------------------------------------------------------------------------------
-- underflow_i generation: Synchronous FIFO
-------------------------------------------------------------------------------
gunflw: IF (C_HAS_UNDERFLOW = 1) GENERATE
g7s_unflw: IF (NOT (C_FAMILY = "virtexu" OR C_FAMILY = "kintexu" OR C_FAMILY = "artixu" OR C_FAMILY = "virtexuplus" OR C_FAMILY = "zynquplus" OR C_FAMILY = "kintexuplus")) GENERATE
punflw: PROCESS (CLK)
BEGIN
IF CLK'event AND CLK = '1' THEN
underflow_i <= empty_i and RD_EN after C_TCQ;
END IF;
END PROCESS punflw;
END GENERATE g7s_unflw;
g8s_unflw: IF ((C_FAMILY = "virtexu" OR C_FAMILY = "kintexu" OR C_FAMILY = "artixu" OR C_FAMILY = "virtexuplus" OR C_FAMILY = "zynquplus" OR C_FAMILY = "kintexuplus")) GENERATE
punflw: PROCESS (CLK)
BEGIN
IF CLK'event AND CLK = '1' THEN
underflow_i <= (RD_RST_BUSY OR empty_i) and RD_EN after C_TCQ;
END IF;
END PROCESS punflw;
END GENERATE g8s_unflw;
END GENERATE gunflw;
-------------------------------------------------------------------------------
-- wr_ack_i generation: Synchronous FIFO
-------------------------------------------------------------------------------
gwack: IF (C_HAS_WR_ACK = 1) GENERATE
pwack: PROCESS (CLK,rst_i)
BEGIN
IF rst_i = '1' THEN
wr_ack_i <= '0' after C_TCQ;
ELSIF CLK'event AND CLK = '1' THEN
wr_ack_i <= '0' after C_TCQ;
IF srst_wrst_busy = '1' THEN
wr_ack_i <= '0' after C_TCQ;
ELSIF WR_EN = '1' THEN
IF full_i /= '1' THEN
wr_ack_i <= '1' after C_TCQ;
END IF;
END IF;
END IF;
END PROCESS pwack;
END GENERATE gwack;
-----------------------------------------------------------------------------
-- valid_i generation: Synchronous FIFO
-----------------------------------------------------------------------------
gvld_i: IF (C_HAS_VALID = 1) GENERATE
PROCESS (rst_i , CLK )
BEGIN
IF rst_i = '1' THEN
valid_i <= '0' after C_TCQ;
ELSIF CLK'event AND CLK = '1' THEN
IF srst_rrst_busy = '1' THEN
valid_i <= '0' after C_TCQ;
ELSE --srst_i=0
-- Setup default value for underflow and valid
valid_i <= '0' after C_TCQ;
IF RD_EN = '1' THEN
IF empty_i /= '1' THEN
valid_i <= '1' after C_TCQ;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE gvld_i;
-----------------------------------------------------------------------------
--Delay Valid AND DOUT
--if C_MEMORY_TYPE=0 or 1, C_USE_EMBEDDED_REG=1, STD
-----------------------------------------------------------------------------
gnll_fifo1: IF (C_FIFO_TYPE < 2) GENERATE
gv0: IF (C_USE_EMBEDDED_REG>0 AND (NOT (C_PRELOAD_REGS = 1 AND C_PRELOAD_LATENCY = 0))
AND (C_MEMORY_TYPE=0 OR C_MEMORY_TYPE=1) AND C_EN_SAFETY_CKT = 0) GENERATE
PROCESS (rst_i , CLK )
BEGIN
IF (rst_i = '1') THEN
IF (C_USE_DOUT_RST = 1) THEN
IF (CLK'event AND CLK = '1') THEN
DOUT <= hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH) after C_TCQ;
END IF;
END IF;
IF (C_USE_ECC = 0) THEN
SBITERR <= '0' after C_TCQ;
DBITERR <= '0' after C_TCQ;
END IF;
ram_rd_en_d1 <= '0' after C_TCQ;
valid_d1 <= '0' after C_TCQ;
ELSIF (CLK 'event AND CLK = '1') THEN
ram_rd_en_d1 <= RD_EN AND (NOT empty_i) after C_TCQ;
valid_d1 <= valid_i after C_TCQ;
IF (srst_rrst_busy = '1') THEN
IF (C_USE_DOUT_RST = 1) THEN
DOUT <= hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH) after C_TCQ;
END IF;
ram_rd_en_d1 <= '0' after C_TCQ;
valid_d1 <= '0' after C_TCQ;
ELSIF (ram_rd_en_d1 = '1') THEN
DOUT <= dout_i after C_TCQ;
SBITERR <= sbiterr_i after C_TCQ;
DBITERR <= dbiterr_i after C_TCQ;
END IF;
END IF;
END PROCESS;
END GENERATE gv0;
gv1: IF (C_USE_EMBEDDED_REG>0 AND (NOT (C_PRELOAD_REGS = 1 AND C_PRELOAD_LATENCY = 0))
AND (C_MEMORY_TYPE=0 OR C_MEMORY_TYPE=1) AND C_EN_SAFETY_CKT = 1) GENERATE
SIGNAL dout_rst_val_d2 : std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL dout_rst_val_d1 : std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_delayed_sft1 : std_logic := '1';
SIGNAL rst_delayed_sft2 : std_logic := '1';
SIGNAL rst_delayed_sft3 : std_logic := '1';
SIGNAL rst_delayed_sft4 : std_logic := '1';
BEGIN
PROCESS ( CLK )
BEGIN
rst_delayed_sft1 <= rst_i;
rst_delayed_sft2 <= rst_delayed_sft1;
rst_delayed_sft3 <= rst_delayed_sft2;
rst_delayed_sft4 <= rst_delayed_sft3;
END PROCESS;
PROCESS (rst_delayed_sft4 ,rst_i, CLK )
BEGIN
IF (rst_delayed_sft4 = '1' OR rst_i = '1') THEN
valid_d1 <= '0' after C_TCQ;
ram_rd_en_d1 <= '0' after C_TCQ;
ELSIF (CLK 'event AND CLK = '1') THEN
valid_d1 <= valid_i after C_TCQ;
ram_rd_en_d1 <= RD_EN AND (NOT empty_i) after C_TCQ;
END IF;
END PROCESS;
PROCESS (rst_delayed_sft4 , CLK )
BEGIN
IF (rst_delayed_sft4 = '1') THEN
IF (C_USE_DOUT_RST = 1) THEN
IF (CLK'event AND CLK = '1') THEN
DOUT <= hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH) after C_TCQ;
END IF;
END IF;
IF (C_USE_ECC = 0) THEN
SBITERR <= '0' after C_TCQ;
DBITERR <= '0' after C_TCQ;
END IF;
--ram_rd_en_d1 <= '0' after C_TCQ;
--valid_d1 <= '0' after C_TCQ;
ELSIF (CLK 'event AND CLK = '1') THEN
--ram_rd_en_d1 <= RD_EN AND (NOT empty_i) after C_TCQ;
--valid_d1 <= valid_i after C_TCQ;
IF (srst_rrst_busy = '1') THEN
IF (C_USE_DOUT_RST = 1) THEN
DOUT <= hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH) after C_TCQ;
END IF;
--ram_rd_en_d1 <= '0' after C_TCQ;
--valid_d1 <= '0' after C_TCQ;
ELSIF (ram_rd_en_d1 = '1') THEN
DOUT <= dout_i after C_TCQ;
SBITERR <= sbiterr_i after C_TCQ;
DBITERR <= dbiterr_i after C_TCQ;
END IF;
END IF;
END PROCESS;
END GENERATE gv1;
END GENERATE gnll_fifo1;
gv1: IF (C_FIFO_TYPE = 2 OR (NOT(C_USE_EMBEDDED_REG>0 AND (NOT (C_PRELOAD_REGS = 1 AND C_PRELOAD_LATENCY = 0))
AND (C_MEMORY_TYPE=0 OR C_MEMORY_TYPE=1)))) GENERATE
valid_d1 <= valid_i;
DOUT <= dout_i;
SBITERR <= sbiterr_i;
DBITERR <= dbiterr_i;
END GENERATE gv1;
--END GENERATE gnll_fifo;
END behavioral;
--#############################################################################
--#############################################################################
-- Preload Latency 0 (First-Word Fall-Through) Module
--#############################################################################
--#############################################################################
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY fifo_generator_v13_0_1_bhv_preload0 IS
GENERIC (
C_DOUT_RST_VAL : string := "";
C_DOUT_WIDTH : integer := 8;
C_HAS_RST : integer := 0;
C_HAS_SRST : integer := 0;
C_USE_DOUT_RST : integer := 0;
C_USE_ECC : integer := 0;
C_USERVALID_LOW : integer := 0;
C_USERUNDERFLOW_LOW : integer := 0;
C_EN_SAFETY_CKT : integer := 0;
C_TCQ : time := 100 ps;
C_ENABLE_RST_SYNC : integer := 1;
C_ERROR_INJECTION_TYPE : integer := 0;
C_MEMORY_TYPE : integer := 0;
C_FIFO_TYPE : integer := 0
);
PORT (
RD_CLK : IN std_logic;
RD_RST : IN std_logic;
SRST : IN std_logic;
WR_RST_BUSY : IN std_logic;
RD_RST_BUSY : IN std_logic;
RD_EN : IN std_logic;
FIFOEMPTY : IN std_logic;
FIFODATA : IN std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0);
FIFOSBITERR : IN std_logic;
FIFODBITERR : IN std_logic;
USERDATA : OUT std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0);
USERVALID : OUT std_logic;
USERUNDERFLOW : OUT std_logic;
USEREMPTY : OUT std_logic;
USERALMOSTEMPTY : OUT std_logic;
RAMVALID : OUT std_logic;
FIFORDEN : OUT std_logic;
USERSBITERR : OUT std_logic := '0';
USERDBITERR : OUT std_logic := '0';
STAGE2_REG_EN : OUT std_logic;
VALID_STAGES : OUT std_logic_vector(1 DOWNTO 0) := (OTHERS => '0')
);
END fifo_generator_v13_0_1_bhv_preload0;
ARCHITECTURE behavioral OF fifo_generator_v13_0_1_bhv_preload0 IS
-----------------------------------------------------------------------------
-- FUNCTION hexstr_to_std_logic_vec
-- Returns a std_logic_vector for a hexadecimal string
-------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
SIGNAL USERDATA_int : std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0) := hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH);
SIGNAL preloadstage1 : std_logic := '0';
SIGNAL preloadstage2 : std_logic := '0';
SIGNAL ram_valid_i : std_logic := '0';
SIGNAL read_data_valid_i : std_logic := '0';
SIGNAL ram_regout_en : std_logic := '0';
SIGNAL ram_rd_en : std_logic := '0';
SIGNAL empty_i : std_logic := '1';
SIGNAL empty_q : std_logic := '1';
SIGNAL rd_en_q : std_logic := '0';
SIGNAL almost_empty_i : std_logic := '1';
SIGNAL almost_empty_q : std_logic := '1';
SIGNAL rd_rst_i : std_logic := '0';
SIGNAL srst_i : std_logic := '0';
BEGIN -- behavioral
grst: IF (C_HAS_RST = 1 OR C_ENABLE_RST_SYNC = 0) GENERATE
rd_rst_i <= RD_RST;
end generate grst;
ngrst: IF (C_HAS_RST = 0 AND C_ENABLE_RST_SYNC = 1) GENERATE
rd_rst_i <= '0';
END GENERATE ngrst;
--SRST
gsrst : IF (C_HAS_SRST=1) GENERATE
srst_i <= SRST OR WR_RST_BUSY OR RD_RST_BUSY;
END GENERATE gsrst;
--SRST
ngsrst : IF (C_HAS_SRST=0) GENERATE
srst_i <= '0';
END GENERATE ngsrst;
gnll_fifo: IF (C_FIFO_TYPE /= 2) GENERATE
CONSTANT INVALID : std_logic_vector (1 downto 0) := "00";
CONSTANT STAGE1_VALID : std_logic_vector (1 downto 0) := "10";
CONSTANT STAGE2_VALID : std_logic_vector (1 downto 0) := "01";
CONSTANT BOTH_STAGES_VALID : std_logic_vector (1 downto 0) := "11";
SIGNAL curr_fwft_state : std_logic_vector (1 DOWNTO 0) := INVALID;
SIGNAL next_fwft_state : std_logic_vector (1 DOWNTO 0) := INVALID;
BEGIN
proc_fwft_fsm : PROCESS ( curr_fwft_state, RD_EN, FIFOEMPTY)
BEGIN
CASE curr_fwft_state IS
WHEN INVALID =>
IF (FIFOEMPTY = '0') THEN
next_fwft_state <= STAGE1_VALID;
ELSE --FIFOEMPTY = '1'
next_fwft_state <= INVALID;
END IF;
WHEN STAGE1_VALID =>
IF (FIFOEMPTY = '1') THEN
next_fwft_state <= STAGE2_VALID;
ELSE -- FIFOEMPTY = '0'
next_fwft_state <= BOTH_STAGES_VALID;
END IF;
WHEN STAGE2_VALID =>
IF (FIFOEMPTY = '1' AND RD_EN = '1') THEN
next_fwft_state <= INVALID;
ELSIF (FIFOEMPTY = '0' AND RD_EN = '1') THEN
next_fwft_state <= STAGE1_VALID;
ELSIF (FIFOEMPTY = '0' AND RD_EN = '0') THEN
next_fwft_state <= BOTH_STAGES_VALID;
ELSE -- FIFOEMPTY = '1' AND RD_EN = '0'
next_fwft_state <= STAGE2_VALID;
END IF;
WHEN BOTH_STAGES_VALID =>
IF (FIFOEMPTY = '1' AND RD_EN = '1') THEN
next_fwft_state <= STAGE2_VALID;
ELSIF (FIFOEMPTY = '0' AND RD_EN = '1') THEN
next_fwft_state <= BOTH_STAGES_VALID;
ELSE -- RD_EN = '0'
next_fwft_state <= BOTH_STAGES_VALID;
END IF;
WHEN OTHERS =>
next_fwft_state <= INVALID;
END CASE;
END PROCESS proc_fwft_fsm;
proc_fsm_reg: PROCESS (rd_rst_i, RD_CLK)
BEGIN
IF (rd_rst_i = '1') THEN
curr_fwft_state <= INVALID;
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF (srst_i = '1') THEN
curr_fwft_state <= INVALID AFTER C_TCQ;
ELSE
curr_fwft_state <= next_fwft_state AFTER C_TCQ;
END IF;
END IF;
END PROCESS proc_fsm_reg;
proc_regen: PROCESS (curr_fwft_state, FIFOEMPTY, RD_EN)
BEGIN
CASE curr_fwft_state IS
WHEN INVALID =>
STAGE2_REG_EN <= '0';
WHEN STAGE1_VALID =>
STAGE2_REG_EN <= '1';
WHEN STAGE2_VALID =>
STAGE2_REG_EN <= '0';
WHEN BOTH_STAGES_VALID =>
IF (RD_EN = '1') THEN
STAGE2_REG_EN <= '1';
ELSE
STAGE2_REG_EN <= '0';
END IF;
WHEN OTHERS =>
STAGE2_REG_EN <= '0';
END CASE;
END PROCESS proc_regen;
VALID_STAGES <= curr_fwft_state;
--------------------------------------------------------------------------------
-- preloadstage2 indicates that stage2 needs to be updated. This is true
-- whenever read_data_valid is false, and RAM_valid is true.
--------------------------------------------------------------------------------
preloadstage2 <= ram_valid_i AND (NOT read_data_valid_i OR RD_EN);
--------------------------------------------------------------------------------
-- preloadstage1 indicates that stage1 needs to be updated. This is true
-- whenever the RAM has data (RAM_EMPTY is false), and either RAM_Valid is
-- false (indicating that Stage1 needs updating), or preloadstage2 is active
-- (indicating that Stage2 is going to update, so Stage1, therefore, must
-- also be updated to keep it valid.
--------------------------------------------------------------------------------
preloadstage1 <= (((NOT ram_valid_i) OR preloadstage2) AND (NOT FIFOEMPTY));
--------------------------------------------------------------------------------
-- Calculate RAM_REGOUT_EN
-- The output registers are controlled by the ram_regout_en signal.
-- These registers should be updated either when the output in Stage2 is
-- invalid (preloadstage2), OR when the user is reading, in which case the
-- Stage2 value will go invalid unless it is replenished.
--------------------------------------------------------------------------------
ram_regout_en <= preloadstage2;
--------------------------------------------------------------------------------
-- Calculate RAM_RD_EN
-- RAM_RD_EN will be asserted whenever the RAM needs to be read in order to
-- update the value in Stage1.
-- One case when this happens is when preloadstage1=true, which indicates
-- that the data in Stage1 or Stage2 is invalid, and needs to automatically
-- be updated.
-- The other case is when the user is reading from the FIFO, which guarantees
-- that Stage1 or Stage2 will be invalid on the next clock cycle, unless it is
-- replinished by data from the memory. So, as long as the RAM has data in it,
-- a read of the RAM should occur.
--------------------------------------------------------------------------------
ram_rd_en <= (RD_EN AND NOT FIFOEMPTY) OR preloadstage1;
END GENERATE gnll_fifo;
gll_fifo: IF (C_FIFO_TYPE = 2) GENERATE
SIGNAL empty_d1 : STD_LOGIC := '1';
SIGNAL fe_of_empty : STD_LOGIC := '0';
SIGNAL curr_state : STD_LOGIC := '0';
SIGNAL next_state : STD_LOGIC := '0';
SIGNAL leaving_empty_fwft : STD_LOGIC := '0';
SIGNAL going_empty_fwft : STD_LOGIC := '0';
BEGIN
fsm_proc: PROCESS (curr_state, FIFOEMPTY, RD_EN)
BEGIN
CASE curr_state IS
WHEN '0' =>
IF (FIFOEMPTY = '0') THEN
next_state <= '1';
ELSE
next_state <= '0';
END IF;
WHEN '1' =>
IF (FIFOEMPTY = '1' AND RD_EN = '1') THEN
next_state <= '0';
ELSE
next_state <= '1';
END IF;
WHEN OTHERS =>
next_state <= '0';
END CASE;
END PROCESS fsm_proc;
empty_reg: PROCESS (RD_CLK, rd_rst_i)
BEGIN
IF (rd_rst_i = '1') THEN
empty_d1 <= '1';
empty_i <= '1';
ram_valid_i <= '0';
curr_state <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF (srst_i = '1') THEN
empty_d1 <= '1' AFTER C_TCQ;
empty_i <= '1' AFTER C_TCQ;
ram_valid_i <= '0' AFTER C_TCQ;
curr_state <= '0' AFTER C_TCQ;
ELSE
empty_d1 <= FIFOEMPTY AFTER C_TCQ;
curr_state <= next_state AFTER C_TCQ;
empty_i <= going_empty_fwft OR (NOT leaving_empty_fwft AND empty_i) AFTER C_TCQ;
ram_valid_i <= next_state AFTER C_TCQ;
END IF;
END IF;
END PROCESS empty_reg;
fe_of_empty <= empty_d1 AND (NOT FIFOEMPTY);
prege: PROCESS (curr_state, FIFOEMPTY, RD_EN)
BEGIN
CASE curr_state IS
WHEN '0' =>
IF (FIFOEMPTY = '0') THEN
ram_regout_en <= '1';
ram_rd_en <= '1';
ELSE
ram_regout_en <= '0';
ram_rd_en <= '0';
END IF;
WHEN '1' =>
IF (FIFOEMPTY = '0' AND RD_EN = '1') THEN
ram_regout_en <= '1';
ram_rd_en <= '1';
ELSE
ram_regout_en <= '0';
ram_rd_en <= '0';
END IF;
WHEN OTHERS =>
ram_regout_en <= '0';
ram_rd_en <= '0';
END CASE;
END PROCESS prege;
ple: PROCESS (curr_state, fe_of_empty) -- Leaving Empty
BEGIN
CASE curr_state IS
WHEN '0' =>
leaving_empty_fwft <= fe_of_empty;
WHEN '1' =>
leaving_empty_fwft <= '1';
WHEN OTHERS =>
leaving_empty_fwft <= '0';
END CASE;
END PROCESS ple;
pge: PROCESS (curr_state, FIFOEMPTY, RD_EN) -- Going Empty
BEGIN
CASE curr_state IS
WHEN '1' =>
IF (FIFOEMPTY = '1' AND RD_EN = '1') THEN
going_empty_fwft <= '1';
ELSE
going_empty_fwft <= '0';
END IF;
WHEN OTHERS =>
going_empty_fwft <= '0';
END CASE;
END PROCESS pge;
END GENERATE gll_fifo;
--------------------------------------------------------------------------------
-- Calculate ram_valid
-- ram_valid indicates that the data in Stage1 is valid.
--
-- If the RAM is being read from on this clock cycle (ram_rd_en=1), then
-- ram_valid is certainly going to be true.
-- If the RAM is not being read from, but the output registers are being
-- updated to fill Stage2 (ram_regout_en=1), then Stage1 will be emptying,
-- therefore causing ram_valid to be false.
-- Otherwise, ram_valid will remain unchanged.
--------------------------------------------------------------------------------
gvalid: IF (C_FIFO_TYPE < 2) GENERATE
regout_valid: PROCESS (RD_CLK, rd_rst_i)
BEGIN -- PROCESS regout_valid
IF rd_rst_i = '1' THEN -- asynchronous reset (active high)
ram_valid_i <= '0' after C_TCQ;
ELSIF RD_CLK'event AND RD_CLK = '1' THEN -- rising clock edge
IF srst_i = '1' THEN -- synchronous reset (active high)
ram_valid_i <= '0' after C_TCQ;
ELSE
IF ram_rd_en = '1' THEN
ram_valid_i <= '1' after C_TCQ;
ELSE
IF ram_regout_en = '1' THEN
ram_valid_i <= '0' after C_TCQ;
ELSE
ram_valid_i <= ram_valid_i after C_TCQ;
END IF;
END IF;
END IF;
END IF;
END PROCESS regout_valid;
END GENERATE gvalid;
--------------------------------------------------------------------------------
-- Calculate READ_DATA_VALID
-- READ_DATA_VALID indicates whether the value in Stage2 is valid or not.
-- Stage2 has valid data whenever Stage1 had valid data and ram_regout_en_i=1,
-- such that the data in Stage1 is propogated into Stage2.
--------------------------------------------------------------------------------
regout_dvalid : PROCESS (RD_CLK, rd_rst_i)
BEGIN
IF (rd_rst_i='1') THEN
read_data_valid_i <= '0' after C_TCQ;
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF (srst_i='1') THEN
read_data_valid_i <= '0' after C_TCQ;
ELSE
read_data_valid_i <= ram_valid_i OR (read_data_valid_i AND NOT RD_EN) after C_TCQ;
END IF;
END IF; --RD_CLK
END PROCESS regout_dvalid;
-------------------------------------------------------------------------------
-- Calculate EMPTY
-- Defined as the inverse of READ_DATA_VALID
--
-- Description:
--
-- If read_data_valid_i indicates that the output is not valid,
-- and there is no valid data on the output of the ram to preload it
-- with, then we will report empty.
--
-- If there is no valid data on the output of the ram and we are
-- reading, then the FIFO will go empty.
--
-------------------------------------------------------------------------------
gempty: IF (C_FIFO_TYPE < 2) GENERATE
regout_empty : PROCESS (RD_CLK, rd_rst_i) --This is equivalent to (NOT read_data_valid_i)
BEGIN
IF (rd_rst_i='1') THEN
empty_i <= '1' after C_TCQ;
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF (srst_i='1') THEN
empty_i <= '1' after C_TCQ;
ELSE
empty_i <= (NOT ram_valid_i AND NOT read_data_valid_i) OR (NOT ram_valid_i AND RD_EN) after C_TCQ;
END IF;
END IF; --RD_CLK
END PROCESS regout_empty;
END GENERATE gempty;
regout_empty_q: PROCESS (RD_CLK)
BEGIN -- PROCESS regout_rd_en
IF RD_CLK'event AND RD_CLK = '1' THEN --
empty_q <= empty_i after C_TCQ;
END IF;
END PROCESS regout_empty_q;
regout_rd_en: PROCESS (RD_CLK)
BEGIN -- PROCESS regout_rd_en
IF RD_CLK'event AND RD_CLK = '1' THEN -- rising clock edge
rd_en_q <= RD_EN after C_TCQ;
END IF;
END PROCESS regout_rd_en;
-------------------------------------------------------------------------------
-- Calculate user_almost_empty
-- user_almost_empty is defined such that, unless more words are written
-- to the FIFO, the next read will cause the FIFO to go EMPTY.
--
-- In most cases, whenever the output registers are updated (due to a user
-- read or a preload condition), then user_almost_empty will update to
-- whatever RAM_EMPTY is.
--
-- The exception is when the output is valid, the user is not reading, and
-- Stage1 is not empty. In this condition, Stage1 will be preloaded from the
-- memory, so we need to make sure user_almost_empty deasserts properly under
-- this condition.
-------------------------------------------------------------------------------
regout_aempty: PROCESS (RD_CLK, rd_rst_i)
BEGIN -- PROCESS regout_empty
IF rd_rst_i = '1' THEN -- asynchronous reset (active high)
almost_empty_i <= '1' after C_TCQ;
almost_empty_q <= '1' after C_TCQ;
ELSIF RD_CLK'event AND RD_CLK = '1' THEN -- rising clock edge
IF srst_i = '1' THEN -- synchronous reset (active high)
almost_empty_i <= '1' after C_TCQ;
almost_empty_q <= '1' after C_TCQ;
ELSE
IF ((ram_regout_en = '1') OR (FIFOEMPTY = '0' AND read_data_valid_i = '1' AND RD_EN='0')) THEN
almost_empty_i <= FIFOEMPTY after C_TCQ;
END IF;
almost_empty_q <= almost_empty_i after C_TCQ;
END IF;
END IF;
END PROCESS regout_aempty;
USEREMPTY <= empty_i;
USERALMOSTEMPTY <= almost_empty_i;
FIFORDEN <= ram_rd_en;
RAMVALID <= ram_valid_i;
guvh: IF C_USERVALID_LOW=0 GENERATE
USERVALID <= read_data_valid_i;
END GENERATE guvh;
guvl: if C_USERVALID_LOW=1 GENERATE
USERVALID <= NOT read_data_valid_i;
END GENERATE guvl;
gufh: IF C_USERUNDERFLOW_LOW=0 GENERATE
USERUNDERFLOW <= empty_q AND rd_en_q;
END GENERATE gufh;
gufl: if C_USERUNDERFLOW_LOW=1 GENERATE
USERUNDERFLOW <= NOT (empty_q AND rd_en_q);
END GENERATE gufl;
glat0_nsafety: if C_EN_SAFETY_CKT=0 GENERATE
regout_lat0: PROCESS (RD_CLK, rd_rst_i)
BEGIN -- PROCESS regout_lat0
IF (rd_rst_i = '1') THEN -- asynchronous reset (active high)
IF (C_USE_ECC = 0) THEN -- Reset S/DBITERR only if ECC is OFF
USERSBITERR <= '0' after C_TCQ;
USERDBITERR <= '0' after C_TCQ;
END IF;
-- DRAM resets asynchronously
IF (C_USE_DOUT_RST = 1 AND C_MEMORY_TYPE = 2) THEN
USERDATA_int <= hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH) after C_TCQ;
END IF;
-- BRAM resets synchronously
IF (C_USE_DOUT_RST = 1 AND C_MEMORY_TYPE < 2) THEN
IF (RD_CLK'event AND RD_CLK = '1') THEN
USERDATA_int <= hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH) after C_TCQ;
END IF;
END IF;
ELSIF RD_CLK'event AND RD_CLK = '1' THEN -- rising clock edge
IF (srst_i = '1') THEN -- synchronous reset (active high)
IF (C_USE_ECC = 0) THEN -- Reset S/DBITERR only if ECC is OFF
USERSBITERR <= '0' after C_TCQ;
USERDBITERR <= '0' after C_TCQ;
END IF;
IF (C_USE_DOUT_RST = 1) THEN -- synchronous reset (active high)
USERDATA_int <= hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH) after C_TCQ;
END IF;
ELSE
IF (ram_regout_en = '1') THEN
USERDATA_int <= FIFODATA after C_TCQ;
USERSBITERR <= FIFOSBITERR after C_TCQ;
USERDBITERR <= FIFODBITERR after C_TCQ;
END IF;
END IF;
END IF;
END PROCESS regout_lat0;
USERDATA <= USERDATA_int ; -- rle, fixed bug R62
END GENERATE glat0_nsafety;
glat0_safety: if C_EN_SAFETY_CKT=1 GENERATE
SIGNAL rst_delayed_sft1 : std_logic := '1';
SIGNAL rst_delayed_sft2 : std_logic := '1';
SIGNAL rst_delayed_sft3 : std_logic := '1';
SIGNAL rst_delayed_sft4 : std_logic := '1';
BEGIN -- PROCESS regout_lat0
PROCESS ( RD_CLK )
BEGIN
rst_delayed_sft1 <= rd_rst_i;
rst_delayed_sft2 <= rst_delayed_sft1;
rst_delayed_sft3 <= rst_delayed_sft2;
rst_delayed_sft4 <= rst_delayed_sft3;
END PROCESS;
regout_lat0: PROCESS (RD_CLK, rd_rst_i)
BEGIN -- PROCESS regout_lat0
IF (rd_rst_i = '1') THEN -- asynchronous reset (active high)
IF (C_USE_ECC = 0) THEN -- Reset S/DBITERR only if ECC is OFF
USERSBITERR <= '0' after C_TCQ;
USERDBITERR <= '0' after C_TCQ;
END IF;
-- DRAM resets asynchronously
IF (C_USE_DOUT_RST = 1 AND C_MEMORY_TYPE = 2 ) THEN
USERDATA_int <= hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH) after C_TCQ;
END IF;
-- BRAM resets synchronously
IF (C_USE_DOUT_RST = 1 AND C_MEMORY_TYPE < 2 AND rst_delayed_sft4 = '1') THEN
IF (RD_CLK'event AND RD_CLK = '1') THEN
USERDATA_int <= hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH) after C_TCQ;
END IF;
END IF;
ELSIF RD_CLK'event AND RD_CLK = '1' THEN -- rising clock edge
IF (srst_i = '1') THEN -- synchronous reset (active high)
IF (C_USE_ECC = 0) THEN -- Reset S/DBITERR only if ECC is OFF
USERSBITERR <= '0' after C_TCQ;
USERDBITERR <= '0' after C_TCQ;
END IF;
IF (C_USE_DOUT_RST = 1) THEN -- synchronous reset (active high)
USERDATA_int <= hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH) after C_TCQ;
END IF;
ELSE
IF (ram_regout_en = '1' and rd_rst_i = '0') THEN
USERDATA_int <= FIFODATA after C_TCQ;
USERSBITERR <= FIFOSBITERR after C_TCQ;
USERDBITERR <= FIFODBITERR after C_TCQ;
END IF;
END IF;
END IF;
END PROCESS regout_lat0;
USERDATA <= USERDATA_int ; -- rle, fixed bug R62
END GENERATE glat0_safety;
END behavioral;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Top-level Behavioral Model for Conventional FIFO
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY fifo_generator_v13_0_1;
USE fifo_generator_v13_0_1.fifo_generator_v13_0_1_bhv_as;
USE fifo_generator_v13_0_1.fifo_generator_v13_0_1_bhv_ss;
-------------------------------------------------------------------------------
-- Top-level Entity Declaration - This is the top-level of the conventional
-- FIFO Bhv Model
-------------------------------------------------------------------------------
ENTITY fifo_generator_v13_0_1_conv IS
GENERIC (
---------------------------------------------------------------------------
-- Generic Declarations
---------------------------------------------------------------------------
C_COMMON_CLOCK : integer := 0;
C_INTERFACE_TYPE : integer := 0;
C_COUNT_TYPE : integer := 0; --not used
C_DATA_COUNT_WIDTH : integer := 2;
C_DEFAULT_VALUE : string := ""; --not used
C_DIN_WIDTH : integer := 8;
C_DOUT_RST_VAL : string := "";
C_DOUT_WIDTH : integer := 8;
C_ENABLE_RLOCS : integer := 0; --not used
C_FAMILY : string := ""; --not used in bhv model
C_FULL_FLAGS_RST_VAL : integer := 0;
C_HAS_ALMOST_EMPTY : integer := 0;
C_HAS_ALMOST_FULL : integer := 0;
C_HAS_BACKUP : integer := 0; --not used
C_HAS_DATA_COUNT : integer := 0;
C_HAS_INT_CLK : integer := 0; --not used in bhv model
C_HAS_MEMINIT_FILE : integer := 0; --not used
C_HAS_OVERFLOW : integer := 0;
C_HAS_RD_DATA_COUNT : integer := 0;
C_HAS_RD_RST : integer := 0; --not used
C_HAS_RST : integer := 1;
C_HAS_SRST : integer := 0;
C_HAS_UNDERFLOW : integer := 0;
C_HAS_VALID : integer := 0;
C_HAS_WR_ACK : integer := 0;
C_HAS_WR_DATA_COUNT : integer := 0;
C_HAS_WR_RST : integer := 0; --not used
C_IMPLEMENTATION_TYPE : integer := 0;
C_INIT_WR_PNTR_VAL : integer := 0; --not used
C_MEMORY_TYPE : integer := 1;
C_MIF_FILE_NAME : string := ""; --not used
C_OPTIMIZATION_MODE : integer := 0; --not used
C_OVERFLOW_LOW : integer := 0;
C_PRELOAD_LATENCY : integer := 1;
C_PRELOAD_REGS : integer := 0;
C_PRIM_FIFO_TYPE : string := "4kx4"; --not used in bhv model
C_PROG_EMPTY_THRESH_ASSERT_VAL: integer := 0;
C_PROG_EMPTY_THRESH_NEGATE_VAL: integer := 0;
C_PROG_EMPTY_TYPE : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL : integer := 0;
C_PROG_FULL_THRESH_NEGATE_VAL : integer := 0;
C_PROG_FULL_TYPE : integer := 0;
C_RD_DATA_COUNT_WIDTH : integer := 2;
C_RD_DEPTH : integer := 256;
C_RD_FREQ : integer := 1; --not used in bhv model
C_RD_PNTR_WIDTH : integer := 8;
C_UNDERFLOW_LOW : integer := 0;
C_USE_DOUT_RST : integer := 0;
C_USE_ECC : integer := 0;
C_USE_EMBEDDED_REG : integer := 0;
C_USE_FIFO16_FLAGS : integer := 0; --not used in bhv model
C_USE_FWFT_DATA_COUNT : integer := 0;
C_VALID_LOW : integer := 0;
C_WR_ACK_LOW : integer := 0;
C_WR_DATA_COUNT_WIDTH : integer := 2;
C_WR_DEPTH : integer := 256;
C_WR_FREQ : integer := 1; --not used in bhv model
C_WR_PNTR_WIDTH : integer := 8;
C_WR_RESPONSE_LATENCY : integer := 1; --not used
C_MSGON_VAL : integer := 1; --not used in bhv model
C_ENABLE_RST_SYNC : integer := 1;
C_EN_SAFETY_CKT : integer := 0;
C_ERROR_INJECTION_TYPE : integer := 0;
C_FIFO_TYPE : integer := 0;
C_SYNCHRONIZER_STAGE : integer := 2;
C_AXI_TYPE : integer := 0
);
PORT(
--------------------------------------------------------------------------------
-- Input and Output Declarations
--------------------------------------------------------------------------------
BACKUP : IN std_logic := '0';
BACKUP_MARKER : IN std_logic := '0';
CLK : IN std_logic := '0';
RST : IN std_logic := '0';
SRST : IN std_logic := '0';
WR_CLK : IN std_logic := '0';
WR_RST : IN std_logic := '0';
RD_CLK : IN std_logic := '0';
RD_RST : IN std_logic := '0';
DIN : IN std_logic_vector(C_DIN_WIDTH-1 DOWNTO 0); --
WR_EN : IN std_logic; --Mandatory input
RD_EN : IN std_logic; --Mandatory input
--Mandatory input
PROG_EMPTY_THRESH : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_EMPTY_THRESH_ASSERT : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_EMPTY_THRESH_NEGATE : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH_ASSERT : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH_NEGATE : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
INT_CLK : IN std_logic := '0';
INJECTDBITERR : IN std_logic := '0';
INJECTSBITERR : IN std_logic := '0';
DOUT : OUT std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0);
FULL : OUT std_logic;
ALMOST_FULL : OUT std_logic;
WR_ACK : OUT std_logic;
OVERFLOW : OUT std_logic;
EMPTY : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
VALID : OUT std_logic;
UNDERFLOW : OUT std_logic;
DATA_COUNT : OUT std_logic_vector(C_DATA_COUNT_WIDTH-1 DOWNTO 0);
RD_DATA_COUNT : OUT std_logic_vector(C_RD_DATA_COUNT_WIDTH-1 DOWNTO 0);
WR_DATA_COUNT : OUT std_logic_vector(C_WR_DATA_COUNT_WIDTH-1 DOWNTO 0);
PROG_FULL : OUT std_logic;
PROG_EMPTY : OUT std_logic;
SBITERR : OUT std_logic := '0';
DBITERR : OUT std_logic := '0';
WR_RST_BUSY : OUT std_logic := '0';
RD_RST_BUSY : OUT std_logic := '0';
WR_RST_I_OUT : OUT std_logic := '0';
RD_RST_I_OUT : OUT std_logic := '0'
);
END fifo_generator_v13_0_1_conv;
-------------------------------------------------------------------------------
-- Definition of Parameters
-------------------------------------------------------------------------------
-- C_COMMON_CLOCK : Common Clock (1), Independent Clocks (0)
-- C_COUNT_TYPE : --not used
-- C_DATA_COUNT_WIDTH : Width of DATA_COUNT bus
-- C_DEFAULT_VALUE : --not used
-- C_DIN_WIDTH : Width of DIN bus
-- C_DOUT_RST_VAL : Reset value of DOUT
-- C_DOUT_WIDTH : Width of DOUT bus
-- C_ENABLE_RLOCS : --not used
-- C_FAMILY : not used in bhv model
-- C_FULL_FLAGS_RST_VAL : Full flags rst val (0 or 1)
-- C_HAS_ALMOST_EMPTY : 1=Core has ALMOST_EMPTY flag
-- C_HAS_ALMOST_FULL : 1=Core has ALMOST_FULL flag
-- C_HAS_BACKUP : --not used
-- C_HAS_DATA_COUNT : 1=Core has DATA_COUNT bus
-- C_HAS_INT_CLK : not used in bhv model
-- C_HAS_MEMINIT_FILE : --not used
-- C_HAS_OVERFLOW : 1=Core has OVERFLOW flag
-- C_HAS_RD_DATA_COUNT : 1=Core has RD_DATA_COUNT bus
-- C_HAS_RD_RST : --not used
-- C_HAS_RST : 1=Core has Async Rst
-- C_HAS_SRST : 1=Core has Sync Rst
-- C_HAS_UNDERFLOW : 1=Core has UNDERFLOW flag
-- C_HAS_VALID : 1=Core has VALID flag
-- C_HAS_WR_ACK : 1=Core has WR_ACK flag
-- C_HAS_WR_DATA_COUNT : 1=Core has WR_DATA_COUNT bus
-- C_HAS_WR_RST : --not used
-- C_IMPLEMENTATION_TYPE : 0=Common-Clock Bram/Dram
-- 1=Common-Clock ShiftRam
-- 2=Indep. Clocks Bram/Dram
-- 3=Virtex-4 Built-in
-- 4=Virtex-5 Built-in
-- C_INIT_WR_PNTR_VAL : --not used
-- C_MEMORY_TYPE : 1=Block RAM
-- 2=Distributed RAM
-- 3=Shift RAM
-- 4=Built-in FIFO
-- C_MIF_FILE_NAME : --not used
-- C_OPTIMIZATION_MODE : --not used
-- C_OVERFLOW_LOW : 1=OVERFLOW active low
-- C_PRELOAD_LATENCY : Latency of read: 0, 1, 2
-- C_PRELOAD_REGS : 1=Use output registers
-- C_PRIM_FIFO_TYPE : not used in bhv model
-- C_PROG_EMPTY_THRESH_ASSERT_VAL: PROG_EMPTY assert threshold
-- C_PROG_EMPTY_THRESH_NEGATE_VAL: PROG_EMPTY negate threshold
-- C_PROG_EMPTY_TYPE : 0=No programmable empty
-- 1=Single prog empty thresh constant
-- 2=Multiple prog empty thresh constants
-- 3=Single prog empty thresh input
-- 4=Multiple prog empty thresh inputs
-- C_PROG_FULL_THRESH_ASSERT_VAL : PROG_FULL assert threshold
-- C_PROG_FULL_THRESH_NEGATE_VAL : PROG_FULL negate threshold
-- C_PROG_FULL_TYPE : 0=No prog full
-- 1=Single prog full thresh constant
-- 2=Multiple prog full thresh constants
-- 3=Single prog full thresh input
-- 4=Multiple prog full thresh inputs
-- C_RD_DATA_COUNT_WIDTH : Width of RD_DATA_COUNT bus
-- C_RD_DEPTH : Depth of read interface (2^N)
-- C_RD_FREQ : not used in bhv model
-- C_RD_PNTR_WIDTH : always log2(C_RD_DEPTH)
-- C_UNDERFLOW_LOW : 1=UNDERFLOW active low
-- C_USE_DOUT_RST : 1=Resets DOUT on RST
-- C_USE_ECC : not used in bhv model
-- C_USE_EMBEDDED_REG : 1=Use BRAM embedded output register
-- C_USE_FIFO16_FLAGS : not used in bhv model
-- C_USE_FWFT_DATA_COUNT : 1=Use extra logic for FWFT data count
-- C_VALID_LOW : 1=VALID active low
-- C_WR_ACK_LOW : 1=WR_ACK active low
-- C_WR_DATA_COUNT_WIDTH : Width of WR_DATA_COUNT bus
-- C_WR_DEPTH : Depth of write interface (2^N)
-- C_WR_FREQ : not used in bhv model
-- C_WR_PNTR_WIDTH : always log2(C_WR_DEPTH)
-- C_WR_RESPONSE_LATENCY : --not used
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- BACKUP : Not used
-- BACKUP_MARKER: Not used
-- CLK : Clock
-- DIN : Input data bus
-- PROG_EMPTY_THRESH : Threshold for Programmable Empty Flag
-- PROG_EMPTY_THRESH_ASSERT: Threshold for Programmable Empty Flag
-- PROG_EMPTY_THRESH_NEGATE: Threshold for Programmable Empty Flag
-- PROG_FULL_THRESH : Threshold for Programmable Full Flag
-- PROG_FULL_THRESH_ASSERT : Threshold for Programmable Full Flag
-- PROG_FULL_THRESH_NEGATE : Threshold for Programmable Full Flag
-- RD_CLK : Read Domain Clock
-- RD_EN : Read enable
-- RD_RST : Not used
-- RST : Asynchronous Reset
-- SRST : Synchronous Reset
-- WR_CLK : Write Domain Clock
-- WR_EN : Write enable
-- WR_RST : Not used
-- INT_CLK : Internal Clock
-- ALMOST_EMPTY : One word remaining in FIFO
-- ALMOST_FULL : One empty space remaining in FIFO
-- DATA_COUNT : Number of data words in fifo( synchronous to CLK)
-- DOUT : Output data bus
-- EMPTY : Empty flag
-- FULL : Full flag
-- OVERFLOW : Last write rejected
-- PROG_EMPTY : Programmable Empty Flag
-- PROG_FULL : Programmable Full Flag
-- RD_DATA_COUNT: Number of data words in fifo (synchronous to RD_CLK)
-- UNDERFLOW : Last read rejected
-- VALID : Last read acknowledged, DOUT bus VALID
-- WR_ACK : Last write acknowledged
-- WR_DATA_COUNT: Number of data words in fifo (synchronous to WR_CLK)
-- SBITERR : Single Bit ECC Error Detected
-- DBITERR : Double Bit ECC Error Detected
-------------------------------------------------------------------------------
ARCHITECTURE behavioral OF fifo_generator_v13_0_1_conv IS
-----------------------------------------------------------------------------
-- FUNCTION two_comp
-- Returns a 2's complement value
-------------------------------------------------------------------------------
FUNCTION two_comp(
vect : std_logic_vector)
RETURN std_logic_vector IS
VARIABLE local_vect : std_logic_vector(vect'high DOWNTO 0);
VARIABLE toggle : integer := 0;
BEGIN
FOR i IN 0 TO vect'high LOOP
IF (toggle = 1) THEN
IF (vect(i) = '0') THEN
local_vect(i) := '1';
ELSE
local_vect(i) := '0';
END IF;
ELSE
local_vect(i) := vect(i);
IF (vect(i) = '1') THEN
toggle := 1;
END IF;
END IF;
END LOOP;
RETURN local_vect;
END two_comp;
-----------------------------------------------------------------------------
-- FUNCTION int_2_std_logic_vector
-- Returns a std_logic_vector for an integer value for a given width.
-------------------------------------------------------------------------------
FUNCTION int_2_std_logic_vector(
value, bitwidth : integer )
RETURN std_logic_vector IS
VARIABLE running_value : integer := value;
VARIABLE running_result : std_logic_vector(bitwidth-1 DOWNTO 0);
BEGIN
IF (value < 0) THEN
running_value := -1 * value;
END IF;
FOR i IN 0 TO bitwidth-1 LOOP
IF running_value MOD 2 = 0 THEN
running_result(i) := '0';
ELSE
running_result(i) := '1';
END IF;
running_value := running_value/2;
END LOOP;
IF (value < 0) THEN -- find the 2s complement
RETURN two_comp(running_result);
ELSE
RETURN running_result;
END IF;
END int_2_std_logic_vector;
COMPONENT fifo_generator_v13_0_1_bhv_as
GENERIC (
--------------------------------------------------------------------------------
-- Generic Declarations
--------------------------------------------------------------------------------
C_FAMILY : string := "virtex7";
C_DIN_WIDTH : integer := 8;
C_DOUT_RST_VAL : string := "";
C_DOUT_WIDTH : integer := 8;
C_FULL_FLAGS_RST_VAL : integer := 1;
C_HAS_ALMOST_EMPTY : integer := 0;
C_HAS_ALMOST_FULL : integer := 0;
C_HAS_OVERFLOW : integer := 0;
C_HAS_RD_DATA_COUNT : integer := 2;
C_HAS_RST : integer := 1;
C_HAS_UNDERFLOW : integer := 0;
C_HAS_VALID : integer := 0;
C_HAS_WR_ACK : integer := 0;
C_HAS_WR_DATA_COUNT : integer := 2;
C_MEMORY_TYPE : integer := 1;
C_OVERFLOW_LOW : integer := 0;
C_PRELOAD_LATENCY : integer := 1;
C_PRELOAD_REGS : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL : integer := 0;
C_PROG_EMPTY_THRESH_NEGATE_VAL : integer := 0;
C_PROG_EMPTY_TYPE : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL : integer := 0;
C_PROG_FULL_THRESH_NEGATE_VAL : integer := 0;
C_PROG_FULL_TYPE : integer := 0;
C_RD_DATA_COUNT_WIDTH : integer := 0;
C_RD_DEPTH : integer := 256;
C_RD_PNTR_WIDTH : integer := 8;
C_UNDERFLOW_LOW : integer := 0;
C_USE_DOUT_RST : integer := 0;
C_USE_ECC : integer := 0;
C_EN_SAFETY_CKT : integer := 0;
C_USE_EMBEDDED_REG : integer := 0;
C_USE_FWFT_DATA_COUNT : integer := 0;
C_VALID_LOW : integer := 0;
C_WR_ACK_LOW : integer := 0;
C_WR_DATA_COUNT_WIDTH : integer := 0;
C_WR_DEPTH : integer := 256;
C_WR_PNTR_WIDTH : integer := 8;
C_TCQ : time := 100 ps;
C_ENABLE_RST_SYNC : integer := 1;
C_ERROR_INJECTION_TYPE : integer := 0;
C_SYNCHRONIZER_STAGE : integer := 2;
C_FIFO_TYPE : integer := 0
);
PORT(
--------------------------------------------------------------------------------
-- Input and Output Declarations
--------------------------------------------------------------------------------
DIN : IN std_logic_vector(C_DIN_WIDTH-1 DOWNTO 0);
PROG_EMPTY_THRESH : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0);
PROG_EMPTY_THRESH_ASSERT : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0);
PROG_EMPTY_THRESH_NEGATE : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0);
PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0);
PROG_FULL_THRESH_ASSERT : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0);
PROG_FULL_THRESH_NEGATE : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0);
RD_CLK : IN std_logic;
RD_EN : IN std_logic;
RD_EN_USER : IN std_logic;
RST : IN std_logic;
RST_FULL_GEN : IN std_logic := '0';
RST_FULL_FF : IN std_logic := '0';
WR_RST : IN std_logic;
RD_RST : IN std_logic;
WR_CLK : IN std_logic;
WR_EN : IN std_logic;
INJECTDBITERR : IN std_logic := '0';
INJECTSBITERR : IN std_logic := '0';
USER_EMPTY_FB : IN std_logic := '1';
ALMOST_EMPTY : OUT std_logic;
ALMOST_FULL : OUT std_logic;
DOUT : OUT std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0);
EMPTY : OUT std_logic;
FULL : OUT std_logic;
OVERFLOW : OUT std_logic;
PROG_EMPTY : OUT std_logic;
PROG_FULL : OUT std_logic;
VALID : OUT std_logic;
RD_DATA_COUNT : OUT std_logic_vector(C_RD_DATA_COUNT_WIDTH-1 DOWNTO 0);
UNDERFLOW : OUT std_logic;
WR_ACK : OUT std_logic;
WR_DATA_COUNT : OUT std_logic_vector(C_WR_DATA_COUNT_WIDTH-1 DOWNTO 0);
DBITERR : OUT std_logic := '0';
SBITERR : OUT std_logic := '0'
);
END COMPONENT;
COMPONENT fifo_generator_v13_0_1_bhv_ss
GENERIC (
--------------------------------------------------------------------------------
-- Generic Declarations (alphabetical)
--------------------------------------------------------------------------------
C_FAMILY : string := "virtex7";
C_DATA_COUNT_WIDTH : integer := 2;
C_DIN_WIDTH : integer := 8;
C_DOUT_RST_VAL : string := "";
C_DOUT_WIDTH : integer := 8;
C_FULL_FLAGS_RST_VAL : integer := 1;
C_HAS_ALMOST_EMPTY : integer := 0;
C_HAS_ALMOST_FULL : integer := 0;
C_HAS_DATA_COUNT : integer := 0;
C_HAS_OVERFLOW : integer := 0;
C_HAS_RD_DATA_COUNT : integer := 2;
C_HAS_RST : integer := 0;
C_HAS_SRST : integer := 0;
C_HAS_UNDERFLOW : integer := 0;
C_HAS_VALID : integer := 0;
C_HAS_WR_ACK : integer := 0;
C_HAS_WR_DATA_COUNT : integer := 2;
C_MEMORY_TYPE : integer := 1;
C_OVERFLOW_LOW : integer := 0;
C_PRELOAD_LATENCY : integer := 1;
C_PRELOAD_REGS : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL : integer := 0;
C_PROG_EMPTY_THRESH_NEGATE_VAL : integer := 0;
C_PROG_EMPTY_TYPE : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL : integer := 0;
C_PROG_FULL_THRESH_NEGATE_VAL : integer := 0;
C_PROG_FULL_TYPE : integer := 0;
C_RD_DATA_COUNT_WIDTH : integer := 0;
C_RD_DEPTH : integer := 256;
C_RD_PNTR_WIDTH : integer := 8;
C_UNDERFLOW_LOW : integer := 0;
C_USE_ECC : integer := 0;
C_EN_SAFETY_CKT : integer := 0;
C_USE_DOUT_RST : integer := 0;
C_USE_EMBEDDED_REG : integer := 0;
C_USE_FWFT_DATA_COUNT : integer := 0;
C_VALID_LOW : integer := 0;
C_WR_ACK_LOW : integer := 0;
C_WR_DATA_COUNT_WIDTH : integer := 0;
C_WR_DEPTH : integer := 256;
C_WR_PNTR_WIDTH : integer := 8;
C_TCQ : time := 100 ps;
C_ENABLE_RST_SYNC : integer := 1;
C_ERROR_INJECTION_TYPE : integer := 0;
C_FIFO_TYPE : integer := 0
);
PORT(
--------------------------------------------------------------------------------
-- Input and Output Declarations
--------------------------------------------------------------------------------
CLK : IN std_logic := '0';
DIN : IN std_logic_vector(C_DIN_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_EMPTY_THRESH : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_EMPTY_THRESH_ASSERT : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_EMPTY_THRESH_NEGATE : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH_ASSERT : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH_NEGATE : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
RD_EN : IN std_logic := '0';
RD_EN_USER : IN std_logic;
RST : IN std_logic := '0';
RST_FULL_GEN : IN std_logic := '0';
RST_FULL_FF : IN std_logic := '0';
SRST : IN std_logic := '0';
WR_EN : IN std_logic := '0';
WR_RST_BUSY : IN std_logic := '0';
RD_RST_BUSY : IN std_logic := '0';
INJECTDBITERR : IN std_logic := '0';
INJECTSBITERR : IN std_logic := '0';
USER_EMPTY_FB : IN std_logic := '1';
ALMOST_EMPTY : OUT std_logic;
ALMOST_FULL : OUT std_logic;
DATA_COUNT : OUT std_logic_vector(C_DATA_COUNT_WIDTH-1 DOWNTO 0);
DOUT : OUT std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0);
EMPTY : OUT std_logic;
FULL : OUT std_logic;
OVERFLOW : OUT std_logic;
PROG_EMPTY : OUT std_logic;
PROG_FULL : OUT std_logic;
VALID : OUT std_logic;
UNDERFLOW : OUT std_logic;
RD_DATA_COUNT : OUT std_logic_vector(C_RD_DATA_COUNT_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
WR_DATA_COUNT : OUT std_logic_vector(C_WR_DATA_COUNT_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
WR_ACK : OUT std_logic;
DBITERR : OUT std_logic := '0';
SBITERR : OUT std_logic := '0'
);
END COMPONENT;
COMPONENT fifo_generator_v13_0_1_bhv_preload0
GENERIC (
C_DOUT_RST_VAL : string;
C_DOUT_WIDTH : integer;
C_HAS_RST : integer;
C_HAS_SRST : integer;
C_USE_DOUT_RST : integer := 0;
C_USE_ECC : integer := 0;
C_USERVALID_LOW : integer := 0;
C_EN_SAFETY_CKT : integer := 0;
C_USERUNDERFLOW_LOW : integer := 0;
C_TCQ : time := 100 ps;
C_ENABLE_RST_SYNC : integer := 1;
C_ERROR_INJECTION_TYPE : integer := 0;
C_MEMORY_TYPE : integer := 0;
C_FIFO_TYPE : integer := 0
);
PORT (
RD_CLK : IN std_logic;
RD_RST : IN std_logic;
SRST : IN std_logic;
WR_RST_BUSY : IN std_logic;
RD_RST_BUSY : IN std_logic;
RD_EN : IN std_logic;
FIFOEMPTY : IN std_logic;
FIFODATA : IN std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0);
FIFOSBITERR : IN std_logic;
FIFODBITERR : IN std_logic;
USERDATA : OUT std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0);
USERVALID : OUT std_logic;
USERUNDERFLOW : OUT std_logic;
USEREMPTY : OUT std_logic;
USERALMOSTEMPTY : OUT std_logic;
RAMVALID : OUT std_logic;
FIFORDEN : OUT std_logic;
USERSBITERR : OUT std_logic;
USERDBITERR : OUT std_logic;
STAGE2_REG_EN : OUT std_logic;
VALID_STAGES : OUT std_logic_vector(1 DOWNTO 0)
);
END COMPONENT;
-- Constant to have clock to register delay
CONSTANT C_TCQ : time := 100 ps;
SIGNAL zero : std_logic := '0';
SIGNAL CLK_INT : std_logic := '0';
-----------------------------------------------------------------------------
-- Internal Signals for delayed input signals
-- All the input signals except Clock are delayed by 100 ps and then given to
-- the models.
-----------------------------------------------------------------------------
SIGNAL rst_delayed : std_logic := '0';
SIGNAL srst_delayed : std_logic := '0';
SIGNAL wr_rst_delayed : std_logic := '0';
SIGNAL rd_rst_delayed : std_logic := '0';
SIGNAL din_delayed : std_logic_vector(C_DIN_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL wr_en_delayed : std_logic := '0';
SIGNAL rd_en_delayed : std_logic := '0';
SIGNAL prog_empty_thresh_delayed : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL prog_empty_thresh_assert_delayed : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL prog_empty_thresh_negate_delayed : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL prog_full_thresh_delayed : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL prog_full_thresh_assert_delayed : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL prog_full_thresh_negate_delayed : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL injectdbiterr_delayed : std_logic := '0';
SIGNAL injectsbiterr_delayed : std_logic := '0';
SIGNAL wr_rst_busy_i : std_logic := '0';
SIGNAL rd_rst_busy_i : std_logic := '0';
-----------------------------------------------------------------------------
-- Internal Signals
-- In the normal case, these signals tie directly to the FIFO's inputs and
-- outputs.
-- In the case of Preload Latency 0 or 1, these are the intermediate
-- signals between the internal FIFO and the preload logic.
-----------------------------------------------------------------------------
SIGNAL rd_en_fifo_in : std_logic;
SIGNAL dout_fifo_out : std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0);
SIGNAL empty_fifo_out : std_logic;
SIGNAL almost_empty_fifo_out : std_logic;
SIGNAL valid_fifo_out : std_logic;
SIGNAL underflow_fifo_out : std_logic;
SIGNAL rd_data_count_fifo_out : std_logic_vector(C_RD_DATA_COUNT_WIDTH-1 DOWNTO 0);
SIGNAL wr_data_count_fifo_out : std_logic_vector(C_WR_DATA_COUNT_WIDTH-1 DOWNTO 0);
SIGNAL data_count_fifo_out : std_logic_vector(C_DATA_COUNT_WIDTH-1 DOWNTO 0);
SIGNAL DATA_COUNT_FWFT : std_logic_vector(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL SS_FWFT_RD : std_logic := '0' ;
SIGNAL SS_FWFT_WR : std_logic := '0' ;
SIGNAL FULL_int : std_logic ;
SIGNAL almost_full_i : std_logic ;
SIGNAL prog_full_i : std_logic ;
SIGNAL dout_p0_out : std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0);
signal valid_p0_out : std_logic;
signal empty_p0_out : std_logic;
signal underflow_p0_out : std_logic;
signal almost_empty_p0_out : std_logic;
signal empty_p0_out_q : std_logic;
signal almost_empty_p0_out_q : std_logic;
SIGNAL ram_valid : std_logic; --Internal signal used to monitor the
--ram_valid state
signal rst_fwft : std_logic;
signal sbiterr_fifo_out : std_logic;
signal dbiterr_fifo_out : std_logic;
signal wr_rst_i : std_logic := '0';
signal rd_rst_i : std_logic := '0';
signal rst_i : std_logic := '0';
signal rst_full_gen_i : std_logic := '0';
signal rst_full_ff_i : std_logic := '0';
signal rst_2_sync : std_logic := '0';
signal rst_2_sync_safety : std_logic := '0';
signal clk_2_sync : std_logic := '0';
signal clk_2_sync_safety : std_logic := '0';
-----------------------------------------------------------------------------
-- FUNCTION if_then_else
-- Returns a true case or flase case based on the condition
-------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : boolean;
true_case : integer;
false_case : integer)
RETURN integer IS
VARIABLE retval : integer := 0;
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-----------------------------------------------------------------------------
-- FUNCTION log2roundup
-- Returns a log2 of the input value
-----------------------------------------------------------------------------
FUNCTION log2roundup (
data_value : integer)
RETURN integer IS
VARIABLE width : integer := 0;
VARIABLE cnt : integer := 1;
BEGIN
IF (data_value <= 1) THEN
width := 0;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
CONSTANT FULL_FLAGS_RST_VAL : integer := if_then_else((C_HAS_SRST = 1),0,C_FULL_FLAGS_RST_VAL);
CONSTANT IS_WR_PNTR_WIDTH_CORRECT : integer := if_then_else((C_WR_PNTR_WIDTH = log2roundup(C_WR_DEPTH)),1,0);
CONSTANT IS_RD_PNTR_WIDTH_CORRECT : integer := if_then_else((C_RD_PNTR_WIDTH = log2roundup(C_RD_DEPTH)),1,0);
BEGIN
rst_delayed <= RST AFTER C_TCQ;
srst_delayed <= SRST AFTER C_TCQ;
wr_rst_delayed <= WR_RST AFTER C_TCQ;
rd_rst_delayed <= RD_RST AFTER C_TCQ;
din_delayed <= DIN AFTER C_TCQ;
wr_en_delayed <= WR_EN AFTER C_TCQ;
rd_en_delayed <= RD_EN AFTER C_TCQ;
prog_empty_thresh_delayed <= PROG_EMPTY_THRESH AFTER C_TCQ;
prog_empty_thresh_assert_delayed <= PROG_EMPTY_THRESH_ASSERT AFTER C_TCQ;
prog_empty_thresh_negate_delayed <= PROG_EMPTY_THRESH_NEGATE AFTER C_TCQ;
prog_full_thresh_delayed <= PROG_FULL_THRESH AFTER C_TCQ;
prog_full_thresh_assert_delayed <= PROG_FULL_THRESH_ASSERT AFTER C_TCQ;
prog_full_thresh_negate_delayed <= PROG_FULL_THRESH_NEGATE AFTER C_TCQ;
injectdbiterr_delayed <= INJECTDBITERR AFTER C_TCQ;
injectsbiterr_delayed <= INJECTSBITERR AFTER C_TCQ;
--Assign Ground Signal
zero <= '0';
ASSERT (C_MEMORY_TYPE /= 4) REPORT "FAILURE : Behavioral models do not support built-in FIFO configurations. Please use post-synthesis or post-implement simulation in Vivado." SEVERITY FAILURE;
--
ASSERT (C_IMPLEMENTATION_TYPE /= 2) REPORT "WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information." SEVERITY NOTE;
ASSERT (IS_WR_PNTR_WIDTH_CORRECT /= 0) REPORT "FAILURE : C_WR_PNTR_WIDTH is not log2 of C_WR_DEPTH." SEVERITY FAILURE;
ASSERT (IS_RD_PNTR_WIDTH_CORRECT /= 0) REPORT "FAILURE : C_RD_PNTR_WIDTH is not log2 of C_RD_DEPTH." SEVERITY FAILURE;
gen_ss : IF ((C_IMPLEMENTATION_TYPE = 0) OR (C_IMPLEMENTATION_TYPE = 1) OR (C_MEMORY_TYPE = 4)) GENERATE
fgss : fifo_generator_v13_0_1_bhv_ss
GENERIC MAP (
C_FAMILY => C_FAMILY,
C_DATA_COUNT_WIDTH => C_DATA_COUNT_WIDTH,
C_DIN_WIDTH => C_DIN_WIDTH,
C_DOUT_RST_VAL => C_DOUT_RST_VAL,
C_DOUT_WIDTH => C_DOUT_WIDTH,
C_FULL_FLAGS_RST_VAL => FULL_FLAGS_RST_VAL,
C_HAS_ALMOST_EMPTY => C_HAS_ALMOST_EMPTY,
C_HAS_ALMOST_FULL => if_then_else((C_AXI_TYPE = 0 AND C_FIFO_TYPE = 1), 1, C_HAS_ALMOST_FULL),
C_HAS_DATA_COUNT => C_HAS_DATA_COUNT,
C_HAS_OVERFLOW => C_HAS_OVERFLOW,
C_HAS_RD_DATA_COUNT => C_HAS_RD_DATA_COUNT,
C_HAS_RST => C_HAS_RST,
C_HAS_SRST => C_HAS_SRST,
C_HAS_UNDERFLOW => C_HAS_UNDERFLOW,
C_HAS_VALID => C_HAS_VALID,
C_HAS_WR_ACK => C_HAS_WR_ACK,
C_HAS_WR_DATA_COUNT => C_HAS_WR_DATA_COUNT,
C_MEMORY_TYPE => if_then_else(C_MEMORY_TYPE = 4, 1, C_MEMORY_TYPE),
C_OVERFLOW_LOW => C_OVERFLOW_LOW,
C_PRELOAD_LATENCY => C_PRELOAD_LATENCY,
C_PRELOAD_REGS => C_PRELOAD_REGS,
C_PROG_EMPTY_THRESH_ASSERT_VAL => C_PROG_EMPTY_THRESH_ASSERT_VAL,
C_PROG_EMPTY_THRESH_NEGATE_VAL => C_PROG_EMPTY_THRESH_NEGATE_VAL,
C_PROG_EMPTY_TYPE => C_PROG_EMPTY_TYPE,
C_PROG_FULL_THRESH_ASSERT_VAL => C_PROG_FULL_THRESH_ASSERT_VAL,
C_PROG_FULL_THRESH_NEGATE_VAL => C_PROG_FULL_THRESH_NEGATE_VAL,
C_PROG_FULL_TYPE => C_PROG_FULL_TYPE,
C_RD_DATA_COUNT_WIDTH => C_RD_DATA_COUNT_WIDTH,
C_RD_DEPTH => C_RD_DEPTH,
C_RD_PNTR_WIDTH => C_RD_PNTR_WIDTH,
C_UNDERFLOW_LOW => C_UNDERFLOW_LOW,
C_USE_ECC => C_USE_ECC,
C_EN_SAFETY_CKT => C_EN_SAFETY_CKT,
C_USE_DOUT_RST => C_USE_DOUT_RST,
C_USE_EMBEDDED_REG => C_USE_EMBEDDED_REG,
C_USE_FWFT_DATA_COUNT => C_USE_FWFT_DATA_COUNT,
C_VALID_LOW => C_VALID_LOW,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_WR_DATA_COUNT_WIDTH => C_WR_DATA_COUNT_WIDTH,
C_WR_DEPTH => C_WR_DEPTH,
C_WR_PNTR_WIDTH => C_WR_PNTR_WIDTH,
C_TCQ => C_TCQ,
C_ENABLE_RST_SYNC => C_ENABLE_RST_SYNC,
C_ERROR_INJECTION_TYPE => C_ERROR_INJECTION_TYPE,
C_FIFO_TYPE => C_FIFO_TYPE
)
PORT MAP(
--Inputs
CLK => CLK,
DIN => din_delayed,
PROG_EMPTY_THRESH => prog_empty_thresh_delayed,
PROG_EMPTY_THRESH_ASSERT => prog_empty_thresh_assert_delayed,
PROG_EMPTY_THRESH_NEGATE => prog_empty_thresh_negate_delayed,
PROG_FULL_THRESH => prog_full_thresh_delayed,
PROG_FULL_THRESH_ASSERT => prog_full_thresh_assert_delayed,
PROG_FULL_THRESH_NEGATE => prog_full_thresh_negate_delayed,
RD_EN => rd_en_fifo_in,
RD_EN_USER => rd_en_delayed,
RST => rst_i,
SRST => srst_delayed,
RST_FULL_GEN => rst_full_gen_i,
RST_FULL_FF => rst_full_ff_i,
WR_EN => wr_en_delayed,
WR_RST_BUSY => wr_rst_busy_i,
RD_RST_BUSY => rd_rst_busy_i,
INJECTDBITERR => injectdbiterr_delayed,
INJECTSBITERR => injectsbiterr_delayed,
USER_EMPTY_FB => empty_p0_out,
--Outputs
ALMOST_EMPTY => almost_empty_fifo_out,
ALMOST_FULL => almost_full_i,
DATA_COUNT => data_count_fifo_out,
DOUT => dout_fifo_out,
EMPTY => empty_fifo_out,
FULL => FULL_int,
OVERFLOW => OVERFLOW,
PROG_EMPTY => PROG_EMPTY,
PROG_FULL => prog_full_i,
UNDERFLOW => underflow_fifo_out,
RD_DATA_COUNT => rd_data_count_fifo_out,
WR_DATA_COUNT => wr_data_count_fifo_out,
VALID => valid_fifo_out,
WR_ACK => WR_ACK,
DBITERR => dbiterr_fifo_out,
SBITERR => sbiterr_fifo_out
);
END GENERATE gen_ss;
gen_as : IF (C_IMPLEMENTATION_TYPE = 2 OR C_FIFO_TYPE = 3) GENERATE
fgas : fifo_generator_v13_0_1_bhv_as
GENERIC MAP (
C_FAMILY => C_FAMILY,
C_DIN_WIDTH => C_DIN_WIDTH,
C_DOUT_RST_VAL => C_DOUT_RST_VAL,
C_DOUT_WIDTH => C_DOUT_WIDTH,
C_FULL_FLAGS_RST_VAL => C_FULL_FLAGS_RST_VAL,
C_HAS_ALMOST_EMPTY => C_HAS_ALMOST_EMPTY,
C_HAS_ALMOST_FULL => if_then_else((C_AXI_TYPE = 0 AND C_FIFO_TYPE = 1), 1, C_HAS_ALMOST_FULL),
C_HAS_OVERFLOW => C_HAS_OVERFLOW,
C_HAS_RD_DATA_COUNT => C_HAS_RD_DATA_COUNT,
C_HAS_RST => C_HAS_RST,
C_HAS_UNDERFLOW => C_HAS_UNDERFLOW,
C_HAS_VALID => C_HAS_VALID,
C_HAS_WR_ACK => C_HAS_WR_ACK,
C_HAS_WR_DATA_COUNT => C_HAS_WR_DATA_COUNT,
C_MEMORY_TYPE => C_MEMORY_TYPE,
C_OVERFLOW_LOW => C_OVERFLOW_LOW,
C_PRELOAD_LATENCY => C_PRELOAD_LATENCY,
C_PRELOAD_REGS => C_PRELOAD_REGS,
C_PROG_EMPTY_THRESH_ASSERT_VAL => C_PROG_EMPTY_THRESH_ASSERT_VAL,
C_PROG_EMPTY_THRESH_NEGATE_VAL => C_PROG_EMPTY_THRESH_NEGATE_VAL,
C_PROG_EMPTY_TYPE => C_PROG_EMPTY_TYPE,
C_PROG_FULL_THRESH_ASSERT_VAL => C_PROG_FULL_THRESH_ASSERT_VAL,
C_PROG_FULL_THRESH_NEGATE_VAL => C_PROG_FULL_THRESH_NEGATE_VAL,
C_PROG_FULL_TYPE => C_PROG_FULL_TYPE,
C_RD_DATA_COUNT_WIDTH => C_RD_DATA_COUNT_WIDTH,
C_RD_DEPTH => C_RD_DEPTH,
C_RD_PNTR_WIDTH => C_RD_PNTR_WIDTH,
C_UNDERFLOW_LOW => C_UNDERFLOW_LOW,
C_USE_ECC => C_USE_ECC,
C_EN_SAFETY_CKT => C_EN_SAFETY_CKT,
C_USE_DOUT_RST => C_USE_DOUT_RST,
C_USE_EMBEDDED_REG => C_USE_EMBEDDED_REG,
C_USE_FWFT_DATA_COUNT => C_USE_FWFT_DATA_COUNT,
C_VALID_LOW => C_VALID_LOW,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_WR_DATA_COUNT_WIDTH => C_WR_DATA_COUNT_WIDTH,
C_WR_DEPTH => C_WR_DEPTH,
C_WR_PNTR_WIDTH => C_WR_PNTR_WIDTH,
C_TCQ => C_TCQ,
C_ENABLE_RST_SYNC => C_ENABLE_RST_SYNC,
C_ERROR_INJECTION_TYPE => C_ERROR_INJECTION_TYPE,
C_SYNCHRONIZER_STAGE => C_SYNCHRONIZER_STAGE,
C_FIFO_TYPE => C_FIFO_TYPE
)
PORT MAP(
--Inputs
WR_CLK => WR_CLK,
RD_CLK => RD_CLK,
RST => rst_i,
RST_FULL_GEN => rst_full_gen_i,
RST_FULL_FF => rst_full_ff_i,
WR_RST => wr_rst_i,
RD_RST => rd_rst_i,
DIN => din_delayed,
RD_EN => rd_en_fifo_in,
WR_EN => wr_en_delayed,
RD_EN_USER => rd_en_delayed,
PROG_FULL_THRESH => prog_full_thresh_delayed,
PROG_EMPTY_THRESH_ASSERT => prog_empty_thresh_assert_delayed,
PROG_EMPTY_THRESH_NEGATE => prog_empty_thresh_negate_delayed,
PROG_EMPTY_THRESH => prog_empty_thresh_delayed,
PROG_FULL_THRESH_ASSERT => prog_full_thresh_assert_delayed,
PROG_FULL_THRESH_NEGATE => prog_full_thresh_negate_delayed,
INJECTDBITERR => injectdbiterr_delayed,
INJECTSBITERR => injectsbiterr_delayed,
USER_EMPTY_FB => empty_p0_out,
--Outputs
DOUT => dout_fifo_out,
FULL => FULL_int,
ALMOST_FULL => almost_full_i,
WR_ACK => WR_ACK,
OVERFLOW => OVERFLOW,
EMPTY => empty_fifo_out,
ALMOST_EMPTY => almost_empty_fifo_out,
VALID => valid_fifo_out,
UNDERFLOW => underflow_fifo_out,
RD_DATA_COUNT => rd_data_count_fifo_out,
WR_DATA_COUNT => wr_data_count_fifo_out,
PROG_FULL => prog_full_i,
PROG_EMPTY => PROG_EMPTY,
DBITERR => dbiterr_fifo_out,
SBITERR => sbiterr_fifo_out
);
END GENERATE gen_as;
ALMOST_FULL <= almost_full_i;
PROG_FULL <= prog_full_i;
WR_RST_I_OUT <= wr_rst_i;
RD_RST_I_OUT <= rd_rst_i;
-------------------------------------------------------------------------
-- Connect internal clock used for FWFT logic based on C_COMMON_CLOCK ---
-------------------------------------------------------------------------
clock_fwft_common: IF (C_COMMON_CLOCK=1 ) GENERATE
CLK_INT <= CLK;
END GENERATE clock_fwft_common;
clock_fwft: IF (C_COMMON_CLOCK= 0 ) GENERATE
CLK_INT <= RD_CLK;
END GENERATE clock_fwft;
-----------------------------------------------------------------------------
-- Connect Internal Signals
-- In the normal case, these signals tie directly to the FIFO's inputs and
-- outputs.
-- In the case of Preload Latency 0 or 1, these are the intermediate
-- signals between the internal FIFO and the preload logic.
-----------------------------------------------------------------------------
latnrm: IF (C_PRELOAD_LATENCY=1 OR C_PRELOAD_LATENCY=2 OR C_FIFO_TYPE = 3) GENERATE
rd_en_fifo_in <= rd_en_delayed;
DOUT <= dout_fifo_out;
VALID <= valid_fifo_out;
EMPTY <= empty_fifo_out;
ALMOST_EMPTY <= almost_empty_fifo_out;
UNDERFLOW <= underflow_fifo_out;
RD_DATA_COUNT <= rd_data_count_fifo_out;
WR_DATA_COUNT <= wr_data_count_fifo_out;
SBITERR <= sbiterr_fifo_out;
DBITERR <= dbiterr_fifo_out;
END GENERATE latnrm;
lat0: IF ((C_PRELOAD_REGS = 1) AND (C_PRELOAD_LATENCY = 0) AND C_FIFO_TYPE /= 3) GENERATE
SIGNAL sbiterr_fwft : STD_LOGIC := '0';
SIGNAL dbiterr_fwft : STD_LOGIC := '0';
SIGNAL rd_en_to_fwft_fifo : STD_LOGIC := '0';
SIGNAL dout_fwft : std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0);
SIGNAL empty_fwft : STD_LOGIC := '0';
SIGNAL valid_stages_i : STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL stage2_reg_en_i : STD_LOGIC := '0';
BEGIN
rst_fwft <= rd_rst_i WHEN (C_COMMON_CLOCK = 0) ELSE rst_i WHEN (C_HAS_RST = 1) ELSE '0';
lat0logic : fifo_generator_v13_0_1_bhv_preload0
GENERIC MAP (
C_DOUT_RST_VAL => C_DOUT_RST_VAL,
C_DOUT_WIDTH => C_DOUT_WIDTH,
C_HAS_RST => C_HAS_RST,
C_HAS_SRST => C_HAS_SRST,
C_USE_DOUT_RST => C_USE_DOUT_RST,
C_USE_ECC => C_USE_ECC,
C_USERVALID_LOW => C_VALID_LOW,
C_EN_SAFETY_CKT => C_EN_SAFETY_CKT,
C_USERUNDERFLOW_LOW => C_UNDERFLOW_LOW,
C_ENABLE_RST_SYNC => C_ENABLE_RST_SYNC,
C_ERROR_INJECTION_TYPE => C_ERROR_INJECTION_TYPE,
C_MEMORY_TYPE => C_MEMORY_TYPE,
C_FIFO_TYPE => C_FIFO_TYPE
)
PORT MAP (
RD_CLK => CLK_INT,
RD_RST => rst_fwft,
SRST => srst_delayed,
WR_RST_BUSY => wr_rst_busy_i,
RD_RST_BUSY => rd_rst_busy_i,
RD_EN => rd_en_to_fwft_fifo,
FIFOEMPTY => empty_fifo_out,
FIFODATA => dout_fifo_out,
FIFOSBITERR => sbiterr_fifo_out,
FIFODBITERR => dbiterr_fifo_out,
USERDATA => dout_fwft,
USERVALID => valid_p0_out,
USEREMPTY => empty_fwft,
USERALMOSTEMPTY => almost_empty_p0_out,
USERUNDERFLOW => underflow_p0_out,
RAMVALID => ram_valid, --Used for observing the state of the ram_valid
FIFORDEN => rd_en_fifo_in,
USERSBITERR => sbiterr_fwft,
USERDBITERR => dbiterr_fwft,
STAGE2_REG_EN => stage2_reg_en_i,
VALID_STAGES => valid_stages_i
);
gberr_non_pkt_fifo: IF (C_FIFO_TYPE /= 1) GENERATE
VALID <= valid_p0_out;
ALMOST_EMPTY <= almost_empty_p0_out;
UNDERFLOW <= underflow_p0_out;
SBITERR <= sbiterr_fwft;
DBITERR <= dbiterr_fwft;
dout_p0_out <= dout_fwft;
rd_en_to_fwft_fifo <= rd_en_delayed;
empty_p0_out <= empty_fwft;
END GENERATE gberr_non_pkt_fifo;
rdcg: IF (C_USE_FWFT_DATA_COUNT=1 AND (C_RD_DATA_COUNT_WIDTH > C_RD_PNTR_WIDTH) AND C_COMMON_CLOCK = 0) GENERATE
eclk: PROCESS (CLK_INT,rst_fwft)
BEGIN -- process eclk
IF (rst_fwft='1') THEN
empty_p0_out_q <= '1' after C_TCQ;
almost_empty_p0_out_q <= '1' after C_TCQ;
ELSIF CLK_INT'event AND CLK_INT = '1' THEN -- rising clock edge
empty_p0_out_q <= empty_p0_out after C_TCQ;
almost_empty_p0_out_q <= almost_empty_p0_out after C_TCQ;
END IF;
END PROCESS eclk;
rcsproc: PROCESS (rd_data_count_fifo_out, empty_p0_out_q,
almost_empty_p0_out_q,rst_fwft)
BEGIN -- process rcsproc
IF (empty_p0_out_q='1' OR rst_fwft='1') THEN
RD_DATA_COUNT <= int_2_std_logic_vector(0, C_RD_DATA_COUNT_WIDTH);
ELSIF (almost_empty_p0_out_q='1') THEN
RD_DATA_COUNT <= int_2_std_logic_vector(1, C_RD_DATA_COUNT_WIDTH);
ELSE
RD_DATA_COUNT <= rd_data_count_fifo_out ;
END IF;
END PROCESS rcsproc;
END GENERATE rdcg;
rdcg1: IF (C_USE_FWFT_DATA_COUNT=1 AND (C_RD_DATA_COUNT_WIDTH <= C_RD_PNTR_WIDTH) AND C_COMMON_CLOCK = 0) GENERATE
eclk1: PROCESS (CLK_INT,rst_fwft)
BEGIN -- process eclk
IF (rst_fwft='1') THEN
empty_p0_out_q <= '1' after C_TCQ;
almost_empty_p0_out_q <= '1' after C_TCQ;
ELSIF CLK_INT'event AND CLK_INT = '1' THEN -- rising clock edge
empty_p0_out_q <= empty_p0_out after C_TCQ;
almost_empty_p0_out_q <= almost_empty_p0_out after C_TCQ;
END IF;
END PROCESS eclk1;
rcsproc1: PROCESS (rd_data_count_fifo_out, empty_p0_out_q,
almost_empty_p0_out_q,rst_fwft)
BEGIN -- process rcsproc
IF (empty_p0_out_q='1' OR rst_fwft='1') THEN
RD_DATA_COUNT <= int_2_std_logic_vector(0, C_RD_DATA_COUNT_WIDTH);
ELSIF (almost_empty_p0_out_q='1') THEN
RD_DATA_COUNT <= int_2_std_logic_vector(0, C_RD_DATA_COUNT_WIDTH);
ELSE
RD_DATA_COUNT <= rd_data_count_fifo_out ;
END IF;
END PROCESS rcsproc1;
END GENERATE rdcg1;
nrdcg: IF (C_USE_FWFT_DATA_COUNT=0) GENERATE
RD_DATA_COUNT <= rd_data_count_fifo_out;
END GENERATE nrdcg;
WR_DATA_COUNT <= wr_data_count_fifo_out;
RD_DATA_COUNT <= rd_data_count_fifo_out;
---------------------------------------------------
-- logics for common-clock data count with fwft
-- For common-clock FIFOs with FWFT, data count
-- is calculated as an up-down counter to maintain
-- accuracy.
---------------------------------------------------
grd_en_npkt: IF (C_FIFO_TYPE /= 1) GENERATE
gfwft_rd: IF (C_VALID_LOW = 0) GENERATE
SS_FWFT_RD <= rd_en_delayed AND valid_p0_out ;
END GENERATE gfwft_rd;
ngfwft_rd: IF (C_VALID_LOW = 1) GENERATE
SS_FWFT_RD <= rd_en_delayed AND NOT valid_p0_out ;
END GENERATE ngfwft_rd;
END GENERATE grd_en_npkt;
grd_en_pkt: IF (C_FIFO_TYPE = 1) GENERATE
gfwft_rd: IF (C_VALID_LOW = 0) GENERATE
SS_FWFT_RD <= (NOT empty_p0_out) AND rd_en_delayed AND valid_p0_out ;
END GENERATE gfwft_rd;
ngfwft_rd: IF (C_VALID_LOW = 1) GENERATE
SS_FWFT_RD <= (NOT empty_p0_out) AND rd_en_delayed AND (NOT valid_p0_out);
END GENERATE ngfwft_rd;
END GENERATE grd_en_pkt;
SS_FWFT_WR <= wr_en_delayed AND (NOT FULL_int) ;
cc_data_cnt: IF (C_HAS_DATA_COUNT = 1 AND C_USE_FWFT_DATA_COUNT = 1) GENERATE
count_fwft: PROCESS (CLK, rst_fwft)
BEGIN
IF (rst_fwft = '1' AND C_HAS_RST=1) THEN
DATA_COUNT_FWFT <= (OTHERS=>'0') after C_TCQ;
ELSIF CLK'event AND CLK = '1' THEN
IF ((srst_delayed='1' OR wr_rst_busy_i='1' OR rd_rst_busy_i='1') AND C_HAS_SRST=1) THEN
DATA_COUNT_FWFT <= (OTHERS=>'0') after C_TCQ;
ELSE
IF (SS_FWFT_WR = '0' and SS_FWFT_RD ='0') THEN
DATA_COUNT_FWFT <= DATA_COUNT_FWFT after C_TCQ;
ELSIF (SS_FWFT_WR = '0' and SS_FWFT_RD ='1') THEN
DATA_COUNT_FWFT <= DATA_COUNT_FWFT - 1 after C_TCQ;
ELSIF (SS_FWFT_WR = '1' and SS_FWFT_RD ='0') THEN
DATA_COUNT_FWFT <= DATA_COUNT_FWFT + 1 after C_TCQ;
ELSE
DATA_COUNT_FWFT <= DATA_COUNT_FWFT after C_TCQ;
END IF ;
END IF;
END IF;
END PROCESS count_fwft;
END GENERATE cc_data_cnt;
----------------------------------------------
DOUT <= dout_p0_out;
EMPTY <= empty_p0_out;
gpkt_fifo_fwft: IF (C_FIFO_TYPE = 1) GENERATE
SIGNAL wr_pkt_count : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_pkt_count : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_pkt_count_plus1 : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_pkt_count_reg : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL eop_at_stage2 : STD_LOGIC := '0';
SIGNAL ram_pkt_empty : STD_LOGIC := '0';
SIGNAL ram_pkt_empty_d1 : STD_LOGIC := '0';
SIGNAL pkt_ready_to_read : STD_LOGIC := '0';
SIGNAL fwft_stage1_valid : STD_LOGIC := '0';
SIGNAL fwft_stage2_valid : STD_LOGIC := '0';
SIGNAL rd_en_2_stage2 : STD_LOGIC := '0';
SIGNAL ram_wr_en_pkt_fifo : STD_LOGIC := '0';
SIGNAL wr_eop : STD_LOGIC := '0';
SIGNAL dummy_wr_eop : STD_LOGIC := '0';
SIGNAL ram_rd_en_compare : STD_LOGIC := '0';
SIGNAL partial_packet : STD_LOGIC := '0';
SIGNAL wr_rst_fwft_pkt_fifo : STD_LOGIC := '0';
SIGNAL stage1_eop : STD_LOGIC := '0';
SIGNAL stage1_eop_d1 : STD_LOGIC := '0';
SIGNAL rd_en_fifo_in_d1 : STD_LOGIC := '0';
BEGIN
wr_rst_fwft_pkt_fifo <= wr_rst_i WHEN (C_COMMON_CLOCK = 0) ELSE rst_i WHEN (C_HAS_RST = 1) ELSE '0';
-- Generate Dummy WR_EOP for partial packet (Only for AXI Streaming)
-- When Packet EMPTY is high, and FIFO is full, then generate the dummy WR_EOP
-- When dummy WR_EOP is high, mask the actual EOP to avoid double increment of
-- write packet count
gdummy_wr_eop: IF (C_AXI_TYPE = 0) GENERATE
SIGNAL packet_empty_wr : std_logic := '1';
BEGIN
proc_dummy_wr_eop: PROCESS (wr_rst_fwft_pkt_fifo, WR_CLK)
BEGIN
IF (wr_rst_fwft_pkt_fifo = '1') THEN
partial_packet <= '0';
ELSIF (WR_CLK'event AND WR_CLK = '1') THEN
IF (srst_delayed = '1' OR wr_rst_busy_i='1' OR rd_rst_busy_i='1') THEN
partial_packet <= '0' AFTER C_TCQ;
ELSE
IF (almost_full_i = '1' AND ram_wr_en_pkt_fifo = '1' AND packet_empty_wr = '1' AND din_delayed(0) = '0') THEN
partial_packet <= '1' AFTER C_TCQ;
ELSE
IF (partial_packet = '1' AND din_delayed(0) = '1' AND ram_wr_en_pkt_fifo = '1') THEN
partial_packet <= '0' AFTER C_TCQ;
END IF;
END IF;
END IF;
END IF;
END PROCESS proc_dummy_wr_eop;
dummy_wr_eop <= almost_full_i AND ram_wr_en_pkt_fifo AND packet_empty_wr AND (NOT din_delayed(0)) AND (NOT partial_packet);
-- Synchronize the packet EMPTY in WR clock domain to generate the dummy WR_EOP
gpkt_empty_sync: IF (C_COMMON_CLOCK = 0) GENERATE
TYPE pkt_empty_array IS ARRAY (0 TO C_SYNCHRONIZER_STAGE-1) OF STD_LOGIC;
SIGNAL pkt_empty_sync : pkt_empty_array := (OTHERS => '1');
BEGIN
proc_empty_sync: PROCESS (wr_rst_fwft_pkt_fifo, WR_CLK)
BEGIN
IF (wr_rst_fwft_pkt_fifo = '1') THEN
pkt_empty_sync <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK = '1') THEN
pkt_empty_sync <= pkt_empty_sync(1 to C_SYNCHRONIZER_STAGE-1) & empty_p0_out AFTER C_TCQ;
END IF;
END PROCESS proc_empty_sync;
packet_empty_wr <= pkt_empty_sync(0);
END GENERATE gpkt_empty_sync;
gnpkt_empty_sync: IF (C_COMMON_CLOCK = 1) GENERATE
packet_empty_wr <= empty_p0_out;
END GENERATE gnpkt_empty_sync;
END GENERATE gdummy_wr_eop;
proc_stage1_eop: PROCESS (rst_fwft, CLK_INT)
BEGIN
IF (rst_fwft = '1') THEN
stage1_eop_d1 <= '0';
rd_en_fifo_in_d1 <= '0';
ELSIF (CLK_INT'event AND CLK_INT = '1') THEN
IF (srst_delayed = '1' OR wr_rst_busy_i='1' OR rd_rst_busy_i='1') THEN
stage1_eop_d1 <= '0' AFTER C_TCQ;
rd_en_fifo_in_d1 <= '0' AFTER C_TCQ;
ELSE
stage1_eop_d1 <= stage1_eop AFTER C_TCQ;
rd_en_fifo_in_d1 <= rd_en_fifo_in AFTER C_TCQ;
END IF;
END IF;
END PROCESS proc_stage1_eop;
stage1_eop <= dout_fifo_out(0) WHEN (rd_en_fifo_in_d1 = '1') ELSE stage1_eop_d1;
ram_wr_en_pkt_fifo <= wr_en_delayed AND (NOT FULL_int);
wr_eop <= ram_wr_en_pkt_fifo AND ((din_delayed(0) AND (NOT partial_packet)) OR dummy_wr_eop);
ram_rd_en_compare <= stage2_reg_en_i AND stage1_eop;
pkt_fifo_fwft : fifo_generator_v13_0_1_bhv_preload0
GENERIC MAP (
C_DOUT_RST_VAL => C_DOUT_RST_VAL,
C_DOUT_WIDTH => C_DOUT_WIDTH,
C_HAS_RST => C_HAS_RST,
C_HAS_SRST => C_HAS_SRST,
C_USE_DOUT_RST => C_USE_DOUT_RST,
C_USE_ECC => C_USE_ECC,
C_USERVALID_LOW => C_VALID_LOW,
C_USERUNDERFLOW_LOW => C_UNDERFLOW_LOW,
C_ENABLE_RST_SYNC => C_ENABLE_RST_SYNC,
C_ERROR_INJECTION_TYPE => C_ERROR_INJECTION_TYPE,
C_MEMORY_TYPE => C_MEMORY_TYPE,
C_FIFO_TYPE => 2 -- Enable low latency fwft logic
)
PORT MAP (
RD_CLK => CLK_INT,
RD_RST => rst_fwft,
SRST => srst_delayed,
WR_RST_BUSY => wr_rst_busy_i,
RD_RST_BUSY => rd_rst_busy_i,
RD_EN => rd_en_delayed,
FIFOEMPTY => pkt_ready_to_read,
FIFODATA => dout_fwft,
FIFOSBITERR => sbiterr_fwft,
FIFODBITERR => dbiterr_fwft,
USERDATA => dout_p0_out,
USERVALID => OPEN,
USEREMPTY => empty_p0_out,
USERALMOSTEMPTY => OPEN,
USERUNDERFLOW => OPEN,
RAMVALID => OPEN, --Used for observing the state of the ram_valid
FIFORDEN => rd_en_2_stage2,
USERSBITERR => SBITERR,
USERDBITERR => DBITERR,
STAGE2_REG_EN => OPEN,
VALID_STAGES => OPEN
);
pkt_ready_to_read <= NOT ((ram_pkt_empty NOR empty_fwft) AND ((valid_stages_i(0) AND valid_stages_i(1)) OR eop_at_stage2));
rd_en_to_fwft_fifo <= NOT empty_fwft AND rd_en_2_stage2;
pregsm : PROCESS (CLK_INT, rst_fwft)
BEGIN
IF (rst_fwft = '1') THEN
eop_at_stage2 <= '0';
ELSIF (CLK_INT'event AND CLK_INT = '1') THEN
IF (stage2_reg_en_i = '1') THEN
eop_at_stage2 <= stage1_eop AFTER C_TCQ;
END IF;
END IF;
END PROCESS pregsm;
-----------------------------------------------------------------------------
-- Write and Read Packet Count
-----------------------------------------------------------------------------
proc_wr_pkt_cnt: PROCESS (WR_CLK, wr_rst_fwft_pkt_fifo)
BEGIN
IF (wr_rst_fwft_pkt_fifo = '1') THEN
wr_pkt_count <= (OTHERS => '0');
ELSIF (WR_CLK'event AND WR_CLK = '1') THEN
IF (srst_delayed='1' OR wr_rst_busy_i='1' OR rd_rst_busy_i='1') THEN
wr_pkt_count <= (OTHERS => '0') AFTER C_TCQ;
ELSIF (wr_eop = '1') THEN
wr_pkt_count <= wr_pkt_count + int_2_std_logic_vector(1,C_WR_PNTR_WIDTH) AFTER C_TCQ;
END IF;
END IF;
END PROCESS proc_wr_pkt_cnt;
grss_pkt_cnt : IF C_COMMON_CLOCK = 1 GENERATE
proc_rd_pkt_cnt: PROCESS (CLK_INT, rst_fwft)
BEGIN
IF (rst_fwft = '1') THEN
rd_pkt_count <= (OTHERS => '0');
rd_pkt_count_plus1 <= int_2_std_logic_vector(1,C_RD_PNTR_WIDTH);
ELSIF (CLK_INT'event AND CLK_INT = '1') THEN
IF (srst_delayed='1' OR wr_rst_busy_i='1' OR rd_rst_busy_i='1') THEN
rd_pkt_count <= (OTHERS => '0') AFTER C_TCQ;
rd_pkt_count_plus1 <= int_2_std_logic_vector(1,C_RD_PNTR_WIDTH) AFTER C_TCQ;
ELSIF (stage2_reg_en_i = '1' AND stage1_eop = '1') THEN
rd_pkt_count <= rd_pkt_count + int_2_std_logic_vector(1,C_RD_PNTR_WIDTH) AFTER C_TCQ;
rd_pkt_count_plus1 <= rd_pkt_count_plus1 + int_2_std_logic_vector(1,C_RD_PNTR_WIDTH) AFTER C_TCQ;
END IF;
END IF;
END PROCESS proc_rd_pkt_cnt;
proc_pkt_empty : PROCESS (CLK_INT, rst_fwft)
BEGIN
IF (rst_fwft = '1') THEN
ram_pkt_empty <= '1';
ram_pkt_empty_d1 <= '1';
ELSIF (CLK_INT'event AND CLK_INT = '1') THEN
IF (SRST='1' OR wr_rst_busy_i='1' OR rd_rst_busy_i='1') THEN
ram_pkt_empty <= '1' AFTER C_TCQ;
ram_pkt_empty_d1 <= '1' AFTER C_TCQ;
ELSE
IF ((rd_pkt_count = wr_pkt_count) AND wr_eop = '1') THEN
ram_pkt_empty <= '0' AFTER C_TCQ;
ram_pkt_empty_d1 <= '0' AFTER C_TCQ;
ELSIF (ram_pkt_empty_d1 = '1' AND rd_en_to_fwft_fifo = '1') THEN
ram_pkt_empty <= '1' AFTER C_TCQ;
ELSIF ((rd_pkt_count_plus1 = wr_pkt_count) AND wr_eop = '0' AND almost_full_i = '0' AND ram_rd_en_compare = '1') THEN
ram_pkt_empty_d1 <= '1' AFTER C_TCQ;
END IF;
END IF;
END IF;
END PROCESS proc_pkt_empty;
END GENERATE grss_pkt_cnt;
gras_pkt_cnt : IF C_COMMON_CLOCK = 0 GENERATE
TYPE wr_pkt_cnt_sync_array IS ARRAY (C_SYNCHRONIZER_STAGE-1 DOWNTO 0) OF std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0);
SIGNAL wr_pkt_count_q : wr_pkt_cnt_sync_array := (OTHERS => (OTHERS => '0'));
SIGNAL wr_pkt_count_b2g : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL wr_pkt_count_rd : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- Delay the write packet count in write clock domain to accomodate the binary to gray conversion delay
proc_wr_pkt_cnt_b2g: PROCESS (WR_CLK, wr_rst_fwft_pkt_fifo)
BEGIN
IF (wr_rst_fwft_pkt_fifo = '1') THEN
wr_pkt_count_b2g <= (OTHERS => '0');
ELSIF (WR_CLK'event AND WR_CLK = '1') THEN
wr_pkt_count_b2g <= wr_pkt_count AFTER C_TCQ;
END IF;
END PROCESS proc_wr_pkt_cnt_b2g;
-- Synchronize the delayed write packet count in read domain, and also compensate the gray to binay conversion delay
proc_wr_pkt_cnt_rd: PROCESS (CLK_INT, rst_fwft)
BEGIN
IF (wr_rst_fwft_pkt_fifo = '1') THEN
wr_pkt_count_q <= (OTHERS => (OTHERS => '0'));
wr_pkt_count_rd <= (OTHERS => '0');
ELSIF (CLK_INT'event AND CLK_INT = '1') THEN
wr_pkt_count_q <= wr_pkt_count_q(C_SYNCHRONIZER_STAGE-2 DOWNTO 0) & wr_pkt_count_b2g AFTER C_TCQ;
wr_pkt_count_rd <= wr_pkt_count_q(C_SYNCHRONIZER_STAGE-1) AFTER C_TCQ;
END IF;
END PROCESS proc_wr_pkt_cnt_rd;
rd_pkt_count <= rd_pkt_count_reg + int_2_std_logic_vector(1,C_RD_PNTR_WIDTH)
WHEN (stage1_eop = '1') ELSE rd_pkt_count_reg;
proc_rd_pkt_cnt: PROCESS (CLK_INT, rst_fwft)
BEGIN
IF (rst_fwft = '1') THEN
rd_pkt_count_reg <= (OTHERS => '0');
ELSIF (RD_CLK'event AND RD_CLK = '1') THEN
IF (rd_en_fifo_in = '1') THEN
rd_pkt_count_reg <= rd_pkt_count AFTER C_TCQ;
END IF;
END IF;
END PROCESS proc_rd_pkt_cnt;
proc_pkt_empty_as : PROCESS (CLK_INT, rst_fwft)
BEGIN
IF (rst_fwft = '1') THEN
ram_pkt_empty <= '1';
ram_pkt_empty_d1 <= '1';
ELSIF (CLK_INT'event AND CLK_INT = '1') THEN
IF (rd_pkt_count /= wr_pkt_count_rd) THEN
ram_pkt_empty <= '0' AFTER C_TCQ;
ram_pkt_empty_d1 <= '0' AFTER C_TCQ;
ELSIF (ram_pkt_empty_d1 = '1' AND rd_en_to_fwft_fifo = '1') THEN
ram_pkt_empty <= '1' AFTER C_TCQ;
ELSIF ((rd_pkt_count = wr_pkt_count_rd) AND stage2_reg_en_i = '1') THEN
ram_pkt_empty_d1 <= '1' AFTER C_TCQ;
END IF;
END IF;
END PROCESS proc_pkt_empty_as;
END GENERATE gras_pkt_cnt;
END GENERATE gpkt_fifo_fwft;
END GENERATE lat0;
gdc_fwft: IF (C_HAS_DATA_COUNT = 1) GENERATE
begin
ss_count: IF ((NOT ((C_PRELOAD_REGS = 1) AND (C_PRELOAD_LATENCY = 0)) ) OR
(C_USE_FWFT_DATA_COUNT = 0) )GENERATE
begin
DATA_COUNT <= data_count_fifo_out ;
end generate ss_count ;
ss_count_fwft1: IF ((C_PRELOAD_REGS = 1) AND (C_PRELOAD_LATENCY = 0) AND
(C_DATA_COUNT_WIDTH > C_RD_PNTR_WIDTH) AND
(C_USE_FWFT_DATA_COUNT = 1) ) GENERATE
begin
DATA_COUNT <= DATA_COUNT_FWFT(C_RD_PNTR_WIDTH DOWNTO 0) ;
end generate ss_count_fwft1 ;
ss_count_fwft2: IF ((C_PRELOAD_REGS = 1) AND (C_PRELOAD_LATENCY = 0) AND
(C_DATA_COUNT_WIDTH <= C_RD_PNTR_WIDTH) AND
(C_USE_FWFT_DATA_COUNT = 1)) GENERATE
begin
DATA_COUNT <= DATA_COUNT_FWFT(C_RD_PNTR_WIDTH DOWNTO C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH+1) ;
end generate ss_count_fwft2 ;
end generate gdc_fwft;
FULL <= FULL_int;
-------------------------------------------------------------------------------
-- If there is a reset input, generate internal reset signals
-- The latency of reset will match the core behavior
-------------------------------------------------------------------------------
--Single RST
grst_sync : IF (C_ENABLE_RST_SYNC = 1 OR C_FIFO_TYPE = 3) GENERATE
grst : IF (C_HAS_RST = 1) GENERATE
gic_rst : IF (C_COMMON_CLOCK = 0 OR C_FIFO_TYPE = 3) GENERATE
SIGNAL rd_rst_asreg : std_logic:= '0';
SIGNAL rd_rst_asreg_d1 : std_logic:= '0';
SIGNAL rd_rst_asreg_d2 : std_logic:= '0';
SIGNAL rd_rst_comb : std_logic:= '0';
SIGNAL rd_rst_reg : std_logic:= '0';
SIGNAL wr_rst_asreg : std_logic:= '0';
SIGNAL wr_rst_asreg_d1 : std_logic:= '0';
SIGNAL wr_rst_asreg_d2 : std_logic:= '0';
SIGNAL wr_rst_comb : std_logic:= '0';
SIGNAL wr_rst_reg : std_logic:= '0';
SIGNAL rst_active : STD_LOGIC := '0';
SIGNAL rst_active_i : STD_LOGIC := '1';
SIGNAL rst_delayed_d1 : STD_LOGIC := '1';
SIGNAL rst_delayed_d2 : STD_LOGIC := '1';
BEGIN
PROCESS (WR_CLK, rst_delayed)
BEGIN
IF (rst_delayed = '1') THEN
wr_rst_asreg <= '1' after C_TCQ;
ELSIF (WR_CLK'event and WR_CLK = '1') THEN
IF (wr_rst_asreg_d1 = '1') THEN
wr_rst_asreg <= '0' after C_TCQ;
END IF;
END IF;
IF (WR_CLK'event and WR_CLK = '1') THEN
wr_rst_asreg_d1 <= wr_rst_asreg after C_TCQ;
wr_rst_asreg_d2 <= wr_rst_asreg_d1 after C_TCQ;
END IF;
END PROCESS;
PROCESS (wr_rst_asreg, wr_rst_asreg_d2)
BEGIN
wr_rst_comb <= NOT wr_rst_asreg_d2 AND wr_rst_asreg;
END PROCESS;
PROCESS (WR_CLK, wr_rst_comb)
BEGIN
IF (wr_rst_comb = '1') THEN
wr_rst_reg <= '1' after C_TCQ;
ELSIF (WR_CLK'event and WR_CLK = '1') THEN
wr_rst_reg <= '0' after C_TCQ;
END IF;
END PROCESS;
PROCESS (WR_CLK)
BEGIN
IF (WR_CLK'event and WR_CLK = '1') THEN
rst_delayed_d1 <= rst_delayed after C_TCQ;
rst_delayed_d2 <= rst_delayed_d1 after C_TCQ;
IF (wr_rst_reg = '1' OR rst_delayed_d2 = '1') THEN
rst_active_i <= '1' after C_TCQ;
ELSE
rst_active_i <= rst_active after C_TCQ;
END IF;
END IF;
END PROCESS;
PROCESS (RD_CLK, rst_delayed)
BEGIN
IF (rst_delayed = '1') THEN
rd_rst_asreg <= '1' after C_TCQ;
ELSIF (RD_CLK'event and RD_CLK = '1') THEN
IF (rd_rst_asreg_d1 = '1') THEN
rd_rst_asreg <= '0' after C_TCQ;
END IF;
END IF;
IF (RD_CLK'event and RD_CLK = '1') THEN
rd_rst_asreg_d1 <= rd_rst_asreg after C_TCQ;
rd_rst_asreg_d2 <= rd_rst_asreg_d1 after C_TCQ;
END IF;
END PROCESS;
PROCESS (rd_rst_asreg, rd_rst_asreg_d2)
BEGIN
rd_rst_comb <= NOT rd_rst_asreg_d2 AND rd_rst_asreg;
END PROCESS;
PROCESS (RD_CLK, rd_rst_comb)
BEGIN
IF (rd_rst_comb = '1') THEN
rd_rst_reg <= '1' after C_TCQ;
ELSIF (RD_CLK'event and RD_CLK = '1') THEN
rd_rst_reg <= '0' after C_TCQ;
END IF;
END PROCESS;
wr_rst_i <= wr_rst_reg;
rd_rst_i <= rd_rst_reg;
wr_rst_busy <= '0';
wr_rst_busy_i <= '0';
rd_rst_busy <= '0';
rd_rst_busy_i <= '0';
END GENERATE gic_rst;
gcc_rst : IF (C_COMMON_CLOCK = 1) GENERATE
SIGNAL rst_asreg : std_logic := '0';
SIGNAL rst_active_i : STD_LOGIC := '1';
SIGNAL rst_delayed_d1 : STD_LOGIC := '1';
SIGNAL rst_delayed_d2 : STD_LOGIC := '1';
SIGNAL rst_asreg_d1 : std_logic := '0';
SIGNAL rst_asreg_d2 : std_logic := '0';
SIGNAL rst_comb : std_logic := '0';
SIGNAL rst_reg : std_logic := '0';
BEGIN
PROCESS (CLK, rst_delayed)
BEGIN
IF (rst_delayed = '1') THEN
rst_asreg <= '1' after C_TCQ;
ELSIF (CLK'event and CLK = '1') THEN
IF (rst_asreg_d1 = '1') THEN
rst_asreg <= '0' after C_TCQ;
ELSE
rst_asreg <= rst_asreg after C_TCQ;
END IF;
END IF;
IF (CLK'event and CLK = '1') THEN
rst_asreg_d1 <= rst_asreg after C_TCQ;
rst_asreg_d2 <= rst_asreg_d1 after C_TCQ;
END IF;
END PROCESS;
PROCESS (rst_asreg, rst_asreg_d2)
BEGIN
rst_comb <= NOT rst_asreg_d2 AND rst_asreg;
END PROCESS;
PROCESS (CLK, rst_comb)
BEGIN
IF (rst_comb = '1') THEN
rst_reg <= '1' after C_TCQ;
ELSIF (CLK'event and CLK = '1') THEN
rst_reg <= '0' after C_TCQ;
END IF;
END PROCESS;
rst_i <= rst_reg;
wr_rst_busy <= '0';
wr_rst_busy_i <= '0';
rd_rst_busy <= '0';
rd_rst_busy_i <= '0';
PROCESS (CLK)
BEGIN
IF (CLK'event and CLK = '1') THEN
rst_delayed_d1 <= rst_delayed after C_TCQ;
rst_delayed_d2 <= rst_delayed_d1 after C_TCQ;
IF (rst_reg = '1' OR rst_delayed_d2 = '1') THEN
rst_active_i <= '1' after C_TCQ;
ELSE
rst_active_i <= rst_reg after C_TCQ;
END IF;
END IF;
END PROCESS;
END GENERATE gcc_rst;
END GENERATE grst;
gnrst : IF (C_HAS_RST = 0) GENERATE
wr_rst_i <= '0';
rd_rst_i <= '0';
rst_i <= '0';
END GENERATE gnrst;
gsrst : IF (C_HAS_SRST = 1) GENERATE
gcc_srst : IF (C_COMMON_CLOCK = 1) GENERATE
SIGNAL rst_asreg : std_logic := '0';
SIGNAL rst_asreg_d1 : std_logic := '0';
SIGNAL rst_asreg_d2 : std_logic := '0';
SIGNAL rst_comb : std_logic := '0';
SIGNAL rst_reg : std_logic := '0';
BEGIN
g8s_cc_srst: IF (C_FAMILY = "virtexu" OR C_FAMILY = "kintexu" OR C_FAMILY = "artixu" OR C_FAMILY = "virtexuplus" OR C_FAMILY = "zynquplus" OR C_FAMILY = "kintexuplus") GENERATE
SIGNAL wr_rst_reg : STD_LOGIC := '0';
SIGNAL rst_active_i : STD_LOGIC := '1';
SIGNAL rst_delayed_d1 : STD_LOGIC := '1';
SIGNAL rst_delayed_d2 : STD_LOGIC := '1';
BEGIN
prst: PROCESS (CLK)
BEGIN
IF (CLK'event AND CLK = '1') THEN
IF (wr_rst_reg = '0' AND srst_delayed = '1') THEN
wr_rst_reg <= '1';
ELSE
IF (wr_rst_reg = '1') THEN
wr_rst_reg <= '0';
ELSE
wr_rst_reg <= wr_rst_reg;
END IF;
END IF;
END IF;
END PROCESS;
rst_i <= wr_rst_reg;
rd_rst_busy <= wr_rst_reg;
rd_rst_busy_i <= wr_rst_reg;
wr_rst_busy <= wr_rst_reg WHEN (C_MEMORY_TYPE /= 4) ELSE rst_active_i;
wr_rst_busy_i <= wr_rst_reg WHEN (C_MEMORY_TYPE /= 4) ELSE rst_active_i;
rst_full_ff_i <= wr_rst_reg;
rst_full_gen_i <= rst_active_i WHEN (C_FULL_FLAGS_RST_VAL = 1) ELSE '0';
PROCESS (CLK)
BEGIN
IF (CLK'event and CLK = '1') THEN
rst_delayed_d1 <= srst_delayed after C_TCQ;
rst_delayed_d2 <= rst_delayed_d1 after C_TCQ;
IF (wr_rst_reg = '1' OR rst_delayed_d2 = '1') THEN
rst_active_i <= '1' after C_TCQ;
ELSE
rst_active_i <= wr_rst_reg after C_TCQ;
END IF;
END IF;
END PROCESS;
END GENERATE g8s_cc_srst;
END GENERATE gcc_srst;
END GENERATE gsrst;
END GENERATE grst_sync;
gnrst_sync : IF (C_ENABLE_RST_SYNC = 0) GENERATE
wr_rst_i <= wr_rst_delayed;
rd_rst_i <= rd_rst_delayed;
rst_i <= '0';
END GENERATE gnrst_sync;
rst_2_sync <= rst_delayed WHEN (C_ENABLE_RST_SYNC = 1) ELSE wr_rst_delayed;
rst_2_sync_safety <= RST WHEN (C_ENABLE_RST_SYNC = 1) ELSE RD_RST;
clk_2_sync <= CLK WHEN (C_COMMON_CLOCK = 1) ELSE WR_CLK;
clk_2_sync_safety <= CLK WHEN (C_COMMON_CLOCK = 1) ELSE RD_CLK;
grst_safety_ckt: IF (C_EN_SAFETY_CKT = 1 AND C_INTERFACE_TYPE = 0) GENERATE
SIGNAL rst_d1_safety : STD_LOGIC := '1';
SIGNAL rst_d2_safety : STD_LOGIC := '1';
SIGNAL rst_d3_safety : STD_LOGIC := '1';
SIGNAL rst_d4_safety : STD_LOGIC := '1';
SIGNAL rst_d5_safety : STD_LOGIC := '1';
SIGNAL rst_d6_safety : STD_LOGIC := '1';
SIGNAL rst_d7_safety : STD_LOGIC := '1';
BEGIN
prst: PROCESS (rst_2_sync_safety, clk_2_sync_safety)
BEGIN
IF (rst_2_sync_safety = '1') THEN
rst_d1_safety <= '1';
rst_d2_safety <= '1';
rst_d3_safety <= '1';
rst_d4_safety <= '1';
rst_d5_safety <= '1';
rst_d6_safety <= '1';
rst_d7_safety <= '1';
ELSIF (clk_2_sync_safety'event AND clk_2_sync_safety = '1') THEN
rst_d1_safety <= '0' AFTER C_TCQ;
rst_d2_safety <= rst_d1_safety AFTER C_TCQ;
rst_d3_safety <= rst_d2_safety AFTER C_TCQ;
rst_d4_safety <= rst_d3_safety AFTER C_TCQ;
rst_d5_safety <= rst_d4_safety AFTER C_TCQ;
rst_d6_safety <= rst_d5_safety AFTER C_TCQ;
rst_d7_safety <= rst_d6_safety AFTER C_TCQ;
END IF;
END PROCESS prst;
assert_safety: PROCESS (rst_d7_safety, wr_en)
BEGIN
IF(rst_d7_safety = '1' AND wr_en = '1') THEN
assert false
report "A write attempt has been made within the 7 clock cycles of reset de-assertion. This can lead to data discrepancy when safety circuit is enabled"
severity warning;
END IF;
END PROCESS assert_safety;
END GENERATE grst_safety_ckt;
grstd1 : IF ((C_HAS_RST = 1 OR C_HAS_SRST = 1 OR C_ENABLE_RST_SYNC = 0)) GENERATE
-- RST_FULL_GEN replaces the reset falling edge detection used to de-assert
-- FULL, ALMOST_FULL & PROG_FULL flags if C_FULL_FLAGS_RST_VAL = 1.
-- RST_FULL_FF goes to the reset pin of the final flop of FULL, ALMOST_FULL &
-- PROG_FULL
grst_full: IF (C_FULL_FLAGS_RST_VAL = 1) GENERATE
SIGNAL rst_d1 : STD_LOGIC := '1';
SIGNAL rst_d2 : STD_LOGIC := '1';
SIGNAL rst_d3 : STD_LOGIC := '1';
SIGNAL rst_d4 : STD_LOGIC := '1';
SIGNAL rst_d5 : STD_LOGIC := '1';
BEGIN
grst_f: IF (C_HAS_SRST = 0) GENERATE
prst: PROCESS (rst_2_sync, clk_2_sync)
BEGIN
IF (rst_2_sync = '1') THEN
rst_d1 <= '1';
rst_d2 <= '1';
rst_d3 <= '1';
rst_d4 <= '1';
rst_d5 <= '1';
ELSIF (clk_2_sync'event AND clk_2_sync = '1') THEN
rst_d1 <= '0' AFTER C_TCQ;
rst_d2 <= rst_d1 AFTER C_TCQ;
rst_d3 <= rst_d2 AFTER C_TCQ;
rst_d4 <= rst_d3 AFTER C_TCQ;
rst_d5 <= rst_d4 AFTER C_TCQ;
END IF;
END PROCESS prst;
g_nsafety_ckt: IF ((C_EN_SAFETY_CKT = 0) ) GENERATE
rst_full_gen_i <= rst_d3;
END GENERATE g_nsafety_ckt;
g_safety_ckt: IF (C_EN_SAFETY_CKT = 1 ) GENERATE
rst_full_gen_i <= rst_d5;
END GENERATE g_safety_ckt;
rst_full_ff_i <= rst_d2;
END GENERATE grst_f;
ngrst_f: IF (C_HAS_SRST = 1) GENERATE
prst: PROCESS (clk_2_sync)
BEGIN
IF (clk_2_sync'event AND clk_2_sync = '1') THEN
IF (srst_delayed = '1') THEN
rst_d1 <= '1' AFTER C_TCQ;
rst_d2 <= '1' AFTER C_TCQ;
rst_d3 <= '1' AFTER C_TCQ;
rst_full_gen_i <= '0' AFTER C_TCQ;
ELSE
rst_d1 <= '0' AFTER C_TCQ;
rst_d2 <= rst_d1 AFTER C_TCQ;
rst_d3 <= rst_d2 AFTER C_TCQ;
rst_full_gen_i <= rst_d3 AFTER C_TCQ;
END IF;
END IF;
END PROCESS prst;
rst_full_ff_i <= '0';
END GENERATE ngrst_f;
END GENERATE grst_full;
gnrst_full: IF (C_FULL_FLAGS_RST_VAL = 0) GENERATE
rst_full_gen_i <= '0';
rst_full_ff_i <= wr_rst_i WHEN (C_COMMON_CLOCK = 0) ELSE rst_i;
END GENERATE gnrst_full;
END GENERATE grstd1;
END behavioral;
-------------------------------------------------------------------------------
--
-- Register Slice
-- Register one AXI channel on forward and/or reverse signal path
--
----------------------------------------------------------------------------
--
-- Structure:
-- reg_slice
--
----------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY fifo_generator_v13_0_1_axic_reg_slice IS
GENERIC (
C_FAMILY : string := "";
C_DATA_WIDTH : integer := 32;
C_REG_CONFIG : integer := 0
);
PORT (
-- System Signals
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
-- Slave side
S_PAYLOAD_DATA : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
S_VALID : IN STD_LOGIC;
S_READY : OUT STD_LOGIC := '0';
-- Master side
M_PAYLOAD_DATA : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_VALID : OUT STD_LOGIC := '0';
M_READY : IN STD_LOGIC
);
END fifo_generator_v13_0_1_axic_reg_slice;
ARCHITECTURE xilinx OF fifo_generator_v13_0_1_axic_reg_slice IS
SIGNAL storage_data1 : STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_ready_i : STD_LOGIC := '0'; -- local signal of output
SIGNAL m_valid_i : STD_LOGIC := '0'; -- local signal of output
SIGNAL areset_d1 : STD_LOGIC := '0'; -- Reset delay register
SIGNAL rst_asreg : std_logic := '0';
SIGNAL rst_asreg_d1 : std_logic := '0';
SIGNAL rst_asreg_d2 : std_logic := '0';
SIGNAL rst_comb : std_logic := '0';
-- Constant to have clock to register delay
CONSTANT TFF : time := 100 ps;
BEGIN
--------------------------------------------------------------------
--
-- Both FWD and REV mode
--
--------------------------------------------------------------------
gfwd_rev: IF (C_REG_CONFIG = 0) GENERATE
CONSTANT ZERO : STD_LOGIC_VECTOR(1 DOWNTO 0) := "10";
CONSTANT ONE : STD_LOGIC_VECTOR(1 DOWNTO 0) := "11";
CONSTANT TWO : STD_LOGIC_VECTOR(1 DOWNTO 0) := "01";
SIGNAL state : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL storage_data2 : STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL load_s1 : STD_LOGIC;
SIGNAL load_s2 : STD_LOGIC;
SIGNAL load_s1_from_s2 : BOOLEAN;
BEGIN
-- assign local signal to its output signal
S_READY <= s_ready_i;
M_VALID <= m_valid_i;
-- Reset delay register
PROCESS(ACLK)
BEGIN
IF (ACLK'event AND ACLK = '1') THEN
areset_d1 <= ARESET AFTER TFF;
END IF;
END PROCESS;
-- Load storage1 with either slave side data or from storage2
PROCESS(ACLK)
BEGIN
IF (ACLK'event AND ACLK = '1') THEN
IF (load_s1 = '1') THEN
IF (load_s1_from_s2) THEN
storage_data1 <= storage_data2 AFTER TFF;
ELSE
storage_data1 <= S_PAYLOAD_DATA AFTER TFF;
END IF;
END IF;
END IF;
END PROCESS;
-- Load storage2 with slave side data
PROCESS(ACLK)
BEGIN
IF (ACLK'event AND ACLK = '1') THEN
IF (load_s2 = '1') THEN
storage_data2 <= S_PAYLOAD_DATA AFTER TFF;
END IF;
END IF;
END PROCESS;
M_PAYLOAD_DATA <= storage_data1;
-- Always load s2 on a valid transaction even if it's unnecessary
load_s2 <= S_VALID AND s_ready_i;
-- Loading s1
PROCESS(state,S_VALID,M_READY)
BEGIN
IF ((state = ZERO AND S_VALID = '1') OR -- Load when empty on slave transaction
-- Load when ONE if we both have read and write at the same time
(state = ONE AND S_VALID = '1' AND M_READY = '1') OR
-- Load when TWO and we have a transaction on Master side
(state = TWO AND M_READY = '1')) THEN
load_s1 <= '1';
ELSE
load_s1 <= '0';
END IF;
END PROCESS;
load_s1_from_s2 <= (state = TWO);
-- State Machine for handling output signals
PROCESS(ACLK)
BEGIN
IF (ACLK'event AND ACLK = '1') THEN
IF (ARESET = '1') THEN
s_ready_i <= '0' AFTER TFF;
state <= ZERO AFTER TFF;
ELSIF (areset_d1 = '1') THEN
s_ready_i <= '1' AFTER TFF;
ELSE
CASE state IS
WHEN ZERO => -- No transaction stored locally
IF (S_VALID = '1') THEN -- Got one so move to ONE
state <= ONE AFTER TFF;
END IF;
WHEN ONE => -- One transaction stored locally
IF (M_READY = '1' AND S_VALID = '0') THEN -- Read out one so move to ZERO
state <= ZERO AFTER TFF;
END IF;
IF (M_READY = '0' AND S_VALID = '1') THEN -- Got another one so move to TWO
state <= TWO AFTER TFF;
s_ready_i <= '0' AFTER TFF;
END IF;
WHEN TWO => -- TWO transaction stored locally
IF (M_READY = '1') THEN -- Read out one so move to ONE
state <= ONE AFTER TFF;
s_ready_i <= '1' AFTER TFF;
END IF;
WHEN OTHERS =>
state <= state AFTER TFF;
END CASE;
END IF;
END IF;
END PROCESS;
m_valid_i <= state(0);
END GENERATE gfwd_rev;
--------------------------------------------------------------------
--
-- C_REG_CONFIG = 1
-- Light-weight mode.
-- 1-stage pipeline register with bubble cycle, both FWD and REV pipelining
-- Operates same as 1-deep FIFO
--
--------------------------------------------------------------------
gfwd_rev_pipeline1: IF (C_REG_CONFIG = 1) GENERATE
-- assign local signal to its output signal
S_READY <= s_ready_i;
M_VALID <= m_valid_i;
-- Reset delay register
PROCESS(ACLK)
BEGIN
IF (ACLK'event AND ACLK = '1') THEN
areset_d1 <= ARESET AFTER TFF;
END IF;
END PROCESS;
-- Load storage1 with slave side data
PROCESS(ACLK)
BEGIN
IF (ACLK'event AND ACLK = '1') THEN
IF (ARESET = '1') THEN
s_ready_i <= '0' AFTER TFF;
m_valid_i <= '0' AFTER TFF;
ELSIF (areset_d1 = '1') THEN
s_ready_i <= '1' AFTER TFF;
ELSIF (m_valid_i = '1' AND M_READY = '1') THEN
s_ready_i <= '1' AFTER TFF;
m_valid_i <= '0' AFTER TFF;
ELSIF (S_VALID = '1' AND s_ready_i = '1') THEN
s_ready_i <= '0' AFTER TFF;
m_valid_i <= '1' AFTER TFF;
END IF;
IF (m_valid_i = '0') THEN
storage_data1 <= S_PAYLOAD_DATA AFTER TFF;
END IF;
END IF;
END PROCESS;
M_PAYLOAD_DATA <= storage_data1;
END GENERATE gfwd_rev_pipeline1;
end xilinx;-- reg_slice
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Top-level Behavioral Model for AXI
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_misc.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY fifo_generator_v13_0_1;
USE fifo_generator_v13_0_1.fifo_generator_v13_0_1_conv;
-------------------------------------------------------------------------------
-- Top-level Entity Declaration - This is the top-level of the AXI FIFO Bhv Model
-------------------------------------------------------------------------------
ENTITY fifo_generator_vhdl_beh IS
GENERIC (
-------------------------------------------------------------------------
-- Generic Declarations
-------------------------------------------------------------------------
C_COMMON_CLOCK : integer := 0;
C_COUNT_TYPE : integer := 0;
C_DATA_COUNT_WIDTH : integer := 2;
C_DEFAULT_VALUE : string := "";
C_DIN_WIDTH : integer := 8;
C_DOUT_RST_VAL : string := "";
C_DOUT_WIDTH : integer := 8;
C_ENABLE_RLOCS : integer := 0;
C_FAMILY : string := "virtex7";
C_FULL_FLAGS_RST_VAL : integer := 1;
C_HAS_ALMOST_EMPTY : integer := 0;
C_HAS_ALMOST_FULL : integer := 0;
C_HAS_BACKUP : integer := 0;
C_HAS_DATA_COUNT : integer := 0;
C_HAS_INT_CLK : integer := 0;
C_HAS_MEMINIT_FILE : integer := 0;
C_HAS_OVERFLOW : integer := 0;
C_HAS_RD_DATA_COUNT : integer := 0;
C_HAS_RD_RST : integer := 0;
C_HAS_RST : integer := 1;
C_HAS_SRST : integer := 0;
C_HAS_UNDERFLOW : integer := 0;
C_HAS_VALID : integer := 0;
C_HAS_WR_ACK : integer := 0;
C_HAS_WR_DATA_COUNT : integer := 0;
C_HAS_WR_RST : integer := 0;
C_IMPLEMENTATION_TYPE : integer := 0;
C_INIT_WR_PNTR_VAL : integer := 0;
C_MEMORY_TYPE : integer := 1;
C_MIF_FILE_NAME : string := "";
C_OPTIMIZATION_MODE : integer := 0;
C_OVERFLOW_LOW : integer := 0;
C_PRELOAD_LATENCY : integer := 1;
C_PRELOAD_REGS : integer := 0;
C_PRIM_FIFO_TYPE : string := "4kx4";
C_PROG_EMPTY_THRESH_ASSERT_VAL : integer := 0;
C_PROG_EMPTY_THRESH_NEGATE_VAL : integer := 0;
C_PROG_EMPTY_TYPE : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL : integer := 0;
C_PROG_FULL_THRESH_NEGATE_VAL : integer := 0;
C_PROG_FULL_TYPE : integer := 0;
C_RD_DATA_COUNT_WIDTH : integer := 2;
C_RD_DEPTH : integer := 256;
C_RD_FREQ : integer := 1;
C_RD_PNTR_WIDTH : integer := 8;
C_UNDERFLOW_LOW : integer := 0;
C_USE_DOUT_RST : integer := 0;
C_USE_ECC : integer := 0;
C_USE_EMBEDDED_REG : integer := 0;
C_USE_PIPELINE_REG : integer := 0;
C_POWER_SAVING_MODE : integer := 0;
C_USE_FIFO16_FLAGS : integer := 0;
C_USE_FWFT_DATA_COUNT : integer := 0;
C_VALID_LOW : integer := 0;
C_WR_ACK_LOW : integer := 0;
C_WR_DATA_COUNT_WIDTH : integer := 2;
C_WR_DEPTH : integer := 256;
C_WR_FREQ : integer := 1;
C_WR_PNTR_WIDTH : integer := 8;
C_WR_RESPONSE_LATENCY : integer := 1;
C_MSGON_VAL : integer := 1;
C_ENABLE_RST_SYNC : integer := 1;
C_EN_SAFETY_CKT : integer := 0;
C_ERROR_INJECTION_TYPE : integer := 0;
C_SYNCHRONIZER_STAGE : integer := 2;
-- AXI Interface related parameters start here
C_INTERFACE_TYPE : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE : integer := 0; -- 0: AXI Stream; 1: AXI Full; 2: AXI Lite
C_HAS_AXI_WR_CHANNEL : integer := 0;
C_HAS_AXI_RD_CHANNEL : integer := 0;
C_HAS_SLAVE_CE : integer := 0;
C_HAS_MASTER_CE : integer := 0;
C_ADD_NGC_CONSTRAINT : integer := 0;
C_USE_COMMON_OVERFLOW : integer := 0;
C_USE_COMMON_UNDERFLOW : integer := 0;
C_USE_DEFAULT_SETTINGS : integer := 0;
-- AXI Full/Lite
C_AXI_ID_WIDTH : integer := 4;
C_AXI_ADDR_WIDTH : integer := 32;
C_AXI_DATA_WIDTH : integer := 64;
C_AXI_LEN_WIDTH : integer := 8;
C_AXI_LOCK_WIDTH : integer := 2;
C_HAS_AXI_ID : integer := 0;
C_HAS_AXI_AWUSER : integer := 0;
C_HAS_AXI_WUSER : integer := 0;
C_HAS_AXI_BUSER : integer := 0;
C_HAS_AXI_ARUSER : integer := 0;
C_HAS_AXI_RUSER : integer := 0;
C_AXI_ARUSER_WIDTH : integer := 1;
C_AXI_AWUSER_WIDTH : integer := 1;
C_AXI_WUSER_WIDTH : integer := 1;
C_AXI_BUSER_WIDTH : integer := 1;
C_AXI_RUSER_WIDTH : integer := 1;
-- AXI Streaming
C_HAS_AXIS_TDATA : integer := 0;
C_HAS_AXIS_TID : integer := 0;
C_HAS_AXIS_TDEST : integer := 0;
C_HAS_AXIS_TUSER : integer := 0;
C_HAS_AXIS_TREADY : integer := 1;
C_HAS_AXIS_TLAST : integer := 0;
C_HAS_AXIS_TSTRB : integer := 0;
C_HAS_AXIS_TKEEP : integer := 0;
C_AXIS_TDATA_WIDTH : integer := 64;
C_AXIS_TID_WIDTH : integer := 8;
C_AXIS_TDEST_WIDTH : integer := 4;
C_AXIS_TUSER_WIDTH : integer := 4;
C_AXIS_TSTRB_WIDTH : integer := 4;
C_AXIS_TKEEP_WIDTH : integer := 4;
-- AXI Channel Type
-- WACH --> Write Address Channel
-- WDCH --> Write Data Channel
-- WRCH --> Write Response Channel
-- RACH --> Read Address Channel
-- RDCH --> Read Data Channel
-- AXIS --> AXI Streaming
C_WACH_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logic
C_WDCH_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_WRCH_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RACH_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RDCH_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_AXIS_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
-- AXI Implementation Type
-- 1 = Common Clock Block RAM FIFO
-- 2 = Common Clock Distributed RAM FIFO
-- 5 = Common Clock Built-in FIFO
-- 11 = Independent Clock Block RAM FIFO
-- 12 = Independent Clock Distributed RAM FIFO
C_IMPLEMENTATION_TYPE_WACH : integer := 1;
C_IMPLEMENTATION_TYPE_WDCH : integer := 1;
C_IMPLEMENTATION_TYPE_WRCH : integer := 1;
C_IMPLEMENTATION_TYPE_RACH : integer := 1;
C_IMPLEMENTATION_TYPE_RDCH : integer := 1;
C_IMPLEMENTATION_TYPE_AXIS : integer := 1;
-- AXI FIFO Type
-- 0 = Data FIFO
-- 1 = Packet FIFO
-- 2 = Low Latency Sync FIFO
-- 3 = Low Latency Async FIFO
C_APPLICATION_TYPE_WACH : integer := 0;
C_APPLICATION_TYPE_WDCH : integer := 0;
C_APPLICATION_TYPE_WRCH : integer := 0;
C_APPLICATION_TYPE_RACH : integer := 0;
C_APPLICATION_TYPE_RDCH : integer := 0;
C_APPLICATION_TYPE_AXIS : integer := 0;
-- AXI Built-in FIFO Primitive Type
-- 512x36, 1kx18, 2kx9, 4kx4, etc
C_PRIM_FIFO_TYPE_WACH : string := "512x36";
C_PRIM_FIFO_TYPE_WDCH : string := "512x36";
C_PRIM_FIFO_TYPE_WRCH : string := "512x36";
C_PRIM_FIFO_TYPE_RACH : string := "512x36";
C_PRIM_FIFO_TYPE_RDCH : string := "512x36";
C_PRIM_FIFO_TYPE_AXIS : string := "512x36";
-- Enable ECC
-- 0 = ECC disabled
-- 1 = ECC enabled
C_USE_ECC_WACH : integer := 0;
C_USE_ECC_WDCH : integer := 0;
C_USE_ECC_WRCH : integer := 0;
C_USE_ECC_RACH : integer := 0;
C_USE_ECC_RDCH : integer := 0;
C_USE_ECC_AXIS : integer := 0;
-- ECC Error Injection Type
-- 0 = No Error Injection
-- 1 = Single Bit Error Injection
-- 2 = Double Bit Error Injection
-- 3 = Single Bit and Double Bit Error Injection
C_ERROR_INJECTION_TYPE_WACH : integer := 0;
C_ERROR_INJECTION_TYPE_WDCH : integer := 0;
C_ERROR_INJECTION_TYPE_WRCH : integer := 0;
C_ERROR_INJECTION_TYPE_RACH : integer := 0;
C_ERROR_INJECTION_TYPE_RDCH : integer := 0;
C_ERROR_INJECTION_TYPE_AXIS : integer := 0;
-- Input Data Width
-- Accumulation of all AXI input signal's width
C_DIN_WIDTH_WACH : integer := 32;
C_DIN_WIDTH_WDCH : integer := 64;
C_DIN_WIDTH_WRCH : integer := 2;
C_DIN_WIDTH_RACH : integer := 32;
C_DIN_WIDTH_RDCH : integer := 64;
C_DIN_WIDTH_AXIS : integer := 1;
C_WR_DEPTH_WACH : integer := 16;
C_WR_DEPTH_WDCH : integer := 1024;
C_WR_DEPTH_WRCH : integer := 16;
C_WR_DEPTH_RACH : integer := 16;
C_WR_DEPTH_RDCH : integer := 1024;
C_WR_DEPTH_AXIS : integer := 1024;
C_WR_PNTR_WIDTH_WACH : integer := 4;
C_WR_PNTR_WIDTH_WDCH : integer := 10;
C_WR_PNTR_WIDTH_WRCH : integer := 4;
C_WR_PNTR_WIDTH_RACH : integer := 4;
C_WR_PNTR_WIDTH_RDCH : integer := 10;
C_WR_PNTR_WIDTH_AXIS : integer := 10;
C_HAS_DATA_COUNTS_WACH : integer := 0;
C_HAS_DATA_COUNTS_WDCH : integer := 0;
C_HAS_DATA_COUNTS_WRCH : integer := 0;
C_HAS_DATA_COUNTS_RACH : integer := 0;
C_HAS_DATA_COUNTS_RDCH : integer := 0;
C_HAS_DATA_COUNTS_AXIS : integer := 0;
C_HAS_PROG_FLAGS_WACH : integer := 0;
C_HAS_PROG_FLAGS_WDCH : integer := 0;
C_HAS_PROG_FLAGS_WRCH : integer := 0;
C_HAS_PROG_FLAGS_RACH : integer := 0;
C_HAS_PROG_FLAGS_RDCH : integer := 0;
C_HAS_PROG_FLAGS_AXIS : integer := 0;
-- 0: No Programmable FULL
-- 1: Single Programmable FULL Threshold Constant
-- 3: Single Programmable FULL Threshold Input Port
C_PROG_FULL_TYPE_WACH : integer := 5;
C_PROG_FULL_TYPE_WDCH : integer := 5;
C_PROG_FULL_TYPE_WRCH : integer := 5;
C_PROG_FULL_TYPE_RACH : integer := 5;
C_PROG_FULL_TYPE_RDCH : integer := 5;
C_PROG_FULL_TYPE_AXIS : integer := 5;
-- Single Programmable FULL Threshold Constant Assert Value
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer := 1023;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer := 1023;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer := 1023;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer := 1023;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer := 1023;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer := 1023;
-- 0: No Programmable EMPTY
-- 1: Single Programmable EMPTY Threshold Constant
-- 3: Single Programmable EMPTY Threshold Input Port
C_PROG_EMPTY_TYPE_WACH : integer := 5;
C_PROG_EMPTY_TYPE_WDCH : integer := 5;
C_PROG_EMPTY_TYPE_WRCH : integer := 5;
C_PROG_EMPTY_TYPE_RACH : integer := 5;
C_PROG_EMPTY_TYPE_RDCH : integer := 5;
C_PROG_EMPTY_TYPE_AXIS : integer := 5;
-- Single Programmable EMPTY Threshold Constant Assert Value
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer := 1022;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer := 1022;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer := 1022;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer := 1022;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer := 1022;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer := 1022;
C_REG_SLICE_MODE_WACH : integer := 0;
C_REG_SLICE_MODE_WDCH : integer := 0;
C_REG_SLICE_MODE_WRCH : integer := 0;
C_REG_SLICE_MODE_RACH : integer := 0;
C_REG_SLICE_MODE_RDCH : integer := 0;
C_REG_SLICE_MODE_AXIS : integer := 0
);
PORT(
------------------------------------------------------------------------------
-- Input and Output Declarations
------------------------------------------------------------------------------
-- Conventional FIFO Interface Signals
BACKUP : IN std_logic := '0';
BACKUP_MARKER : IN std_logic := '0';
CLK : IN std_logic := '0';
RST : IN std_logic := '0';
SRST : IN std_logic := '0';
WR_CLK : IN std_logic := '0';
WR_RST : IN std_logic := '0';
RD_CLK : IN std_logic := '0';
RD_RST : IN std_logic := '0';
DIN : IN std_logic_vector(C_DIN_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
WR_EN : IN std_logic := '0';
RD_EN : IN std_logic := '0';
-- Optional inputs
PROG_EMPTY_THRESH : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_EMPTY_THRESH_ASSERT : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_EMPTY_THRESH_NEGATE : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH_ASSERT : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH_NEGATE : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
INT_CLK : IN std_logic := '0';
INJECTDBITERR : IN std_logic := '0';
INJECTSBITERR : IN std_logic := '0';
SLEEP : IN std_logic := '0';
DOUT : OUT std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
FULL : OUT std_logic := '0';
ALMOST_FULL : OUT std_logic := '0';
WR_ACK : OUT std_logic := '0';
OVERFLOW : OUT std_logic := '0';
EMPTY : OUT std_logic := '1';
ALMOST_EMPTY : OUT std_logic := '1';
VALID : OUT std_logic := '0';
UNDERFLOW : OUT std_logic := '0';
DATA_COUNT : OUT std_logic_vector(C_DATA_COUNT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
RD_DATA_COUNT : OUT std_logic_vector(C_RD_DATA_COUNT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
WR_DATA_COUNT : OUT std_logic_vector(C_WR_DATA_COUNT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL : OUT std_logic := '0';
PROG_EMPTY : OUT std_logic := '1';
SBITERR : OUT std_logic := '0';
DBITERR : OUT std_logic := '0';
WR_RST_BUSY : OUT std_logic := '0';
RD_RST_BUSY : OUT std_logic := '0';
-- AXI Global Signal
M_ACLK : IN std_logic := '0';
S_ACLK : IN std_logic := '0';
S_ARESETN : IN std_logic := '1'; -- Active low reset, default value set to 1
M_ACLK_EN : IN std_logic := '0';
S_ACLK_EN : IN std_logic := '0';
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWADDR : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWLEN : IN std_logic_vector(C_AXI_LEN_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWSIZE : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWBURST : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWLOCK : IN std_logic_vector(C_AXI_LOCK_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWCACHE : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWPROT : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWQOS : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWREGION : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWUSER : IN std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWVALID : IN std_logic := '0';
S_AXI_AWREADY : OUT std_logic := '0';
S_AXI_WID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_WDATA : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_WSTRB : IN std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_WLAST : IN std_logic := '0';
S_AXI_WUSER : IN std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_WVALID : IN std_logic := '0';
S_AXI_WREADY : OUT std_logic := '0';
S_AXI_BID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_BRESP : OUT std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_BUSER : OUT std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_BVALID : OUT std_logic := '0';
S_AXI_BREADY : IN std_logic := '0';
-- AXI Full/Lite Master Write Channel (Read side)
M_AXI_AWID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWADDR : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWLEN : OUT std_logic_vector(C_AXI_LEN_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWSIZE : OUT std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWBURST : OUT std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWLOCK : OUT std_logic_vector(C_AXI_LOCK_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWCACHE : OUT std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWPROT : OUT std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWQOS : OUT std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWREGION : OUT std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWUSER : OUT std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWVALID : OUT std_logic := '0';
M_AXI_AWREADY : IN std_logic := '0';
M_AXI_WID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_WDATA : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_WSTRB : OUT std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_WLAST : OUT std_logic := '0';
M_AXI_WUSER : OUT std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_WVALID : OUT std_logic := '0';
M_AXI_WREADY : IN std_logic := '0';
M_AXI_BID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_BRESP : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_BUSER : IN std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_BVALID : IN std_logic := '0';
M_AXI_BREADY : OUT std_logic := '0';
-- AXI Full/Lite Slave Read Channel (Write side)
S_AXI_ARID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARADDR : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARLEN : IN std_logic_vector(C_AXI_LEN_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARSIZE : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARBURST : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARLOCK : IN std_logic_vector(C_AXI_LOCK_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARCACHE : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARPROT : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARQOS : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARREGION : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARUSER : IN std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARVALID : IN std_logic := '0';
S_AXI_ARREADY : OUT std_logic := '0';
S_AXI_RID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_RDATA : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_RRESP : OUT std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_RLAST : OUT std_logic := '0';
S_AXI_RUSER : OUT std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_RVALID : OUT std_logic := '0';
S_AXI_RREADY : IN std_logic := '0';
-- AXI Full/Lite Master Read Channel (Read side)
M_AXI_ARID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARADDR : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARLEN : OUT std_logic_vector(C_AXI_LEN_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARSIZE : OUT std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARBURST : OUT std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARLOCK : OUT std_logic_vector(C_AXI_LOCK_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARCACHE : OUT std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARPROT : OUT std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARQOS : OUT std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARREGION : OUT std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARUSER : OUT std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARVALID : OUT std_logic := '0';
M_AXI_ARREADY : IN std_logic := '0';
M_AXI_RID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_RDATA : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_RRESP : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_RLAST : IN std_logic := '0';
M_AXI_RUSER : IN std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_RVALID : IN std_logic := '0';
M_AXI_RREADY : OUT std_logic := '0';
-- AXI Streaming Slave Signals (Write side)
S_AXIS_TVALID : IN std_logic := '0';
S_AXIS_TREADY : OUT std_logic := '0';
S_AXIS_TDATA : IN std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXIS_TSTRB : IN std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXIS_TKEEP : IN std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXIS_TLAST : IN std_logic := '0';
S_AXIS_TID : IN std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXIS_TDEST : IN std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXIS_TUSER : IN std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
-- AXI Streaming Master Signals (Read side)
M_AXIS_TVALID : OUT std_logic := '0';
M_AXIS_TREADY : IN std_logic := '0';
M_AXIS_TDATA : OUT std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXIS_TSTRB : OUT std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXIS_TKEEP : OUT std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXIS_TLAST : OUT std_logic := '0';
M_AXIS_TID : OUT std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXIS_TDEST : OUT std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXIS_TUSER : OUT std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
-- AXI Full/Lite Write Address Channel Signals
AXI_AW_INJECTSBITERR : IN std_logic := '0';
AXI_AW_INJECTDBITERR : IN std_logic := '0';
AXI_AW_PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
AXI_AW_PROG_EMPTY_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
AXI_AW_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0) := (OTHERS => '0');
AXI_AW_WR_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0) := (OTHERS => '0');
AXI_AW_RD_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0) := (OTHERS => '0');
AXI_AW_SBITERR : OUT std_logic := '0';
AXI_AW_DBITERR : OUT std_logic := '0';
AXI_AW_OVERFLOW : OUT std_logic := '0';
AXI_AW_UNDERFLOW : OUT std_logic := '0';
AXI_AW_PROG_FULL : OUT STD_LOGIC := '0';
AXI_AW_PROG_EMPTY : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Data Channel Signals
AXI_W_INJECTSBITERR : IN std_logic := '0';
AXI_W_INJECTDBITERR : IN std_logic := '0';
AXI_W_PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_W_PROG_EMPTY_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_W_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0) := (OTHERS => '0');
AXI_W_WR_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0) := (OTHERS => '0');
AXI_W_RD_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0) := (OTHERS => '0');
AXI_W_SBITERR : OUT std_logic := '0';
AXI_W_DBITERR : OUT std_logic := '0';
AXI_W_OVERFLOW : OUT std_logic := '0';
AXI_W_UNDERFLOW : OUT std_logic := '0';
AXI_W_PROG_FULL : OUT STD_LOGIC := '0';
AXI_W_PROG_EMPTY : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Response Channel Signals
AXI_B_INJECTSBITERR : IN std_logic := '0';
AXI_B_INJECTDBITERR : IN std_logic := '0';
AXI_B_PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_B_PROG_EMPTY_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_B_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0) := (OTHERS => '0');
AXI_B_WR_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0) := (OTHERS => '0');
AXI_B_RD_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0) := (OTHERS => '0');
AXI_B_SBITERR : OUT std_logic := '0';
AXI_B_DBITERR : OUT std_logic := '0';
AXI_B_OVERFLOW : OUT std_logic := '0';
AXI_B_UNDERFLOW : OUT std_logic := '0';
AXI_B_PROG_FULL : OUT STD_LOGIC := '0';
AXI_B_PROG_EMPTY : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Address Channel Signals
AXI_AR_INJECTSBITERR : IN std_logic := '0';
AXI_AR_INJECTDBITERR : IN std_logic := '0';
AXI_AR_PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
AXI_AR_PROG_EMPTY_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
AXI_AR_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0) := (OTHERS => '0');
AXI_AR_WR_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0) := (OTHERS => '0');
AXI_AR_RD_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0) := (OTHERS => '0');
AXI_AR_SBITERR : OUT std_logic := '0';
AXI_AR_DBITERR : OUT std_logic := '0';
AXI_AR_OVERFLOW : OUT std_logic := '0';
AXI_AR_UNDERFLOW : OUT std_logic := '0';
AXI_AR_PROG_FULL : OUT STD_LOGIC := '0';
AXI_AR_PROG_EMPTY : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Data Channel Signals
AXI_R_INJECTSBITERR : IN std_logic := '0';
AXI_R_INJECTDBITERR : IN std_logic := '0';
AXI_R_PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_R_PROG_EMPTY_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_R_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0) := (OTHERS => '0');
AXI_R_WR_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0) := (OTHERS => '0');
AXI_R_RD_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0) := (OTHERS => '0');
AXI_R_SBITERR : OUT std_logic := '0';
AXI_R_DBITERR : OUT std_logic := '0';
AXI_R_OVERFLOW : OUT std_logic := '0';
AXI_R_UNDERFLOW : OUT std_logic := '0';
AXI_R_PROG_FULL : OUT STD_LOGIC := '0';
AXI_R_PROG_EMPTY : OUT STD_LOGIC := '1';
-- AXI Streaming FIFO Related Signals
AXIS_INJECTSBITERR : IN std_logic := '0';
AXIS_INJECTDBITERR : IN std_logic := '0';
AXIS_PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
AXIS_PROG_EMPTY_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
AXIS_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0) := (OTHERS => '0');
AXIS_WR_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0) := (OTHERS => '0');
AXIS_RD_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0) := (OTHERS => '0');
AXIS_SBITERR : OUT std_logic := '0';
AXIS_DBITERR : OUT std_logic := '0';
AXIS_OVERFLOW : OUT std_logic := '0';
AXIS_UNDERFLOW : OUT std_logic := '0';
AXIS_PROG_FULL : OUT STD_LOGIC := '0';
AXIS_PROG_EMPTY : OUT STD_LOGIC := '1'
);
END fifo_generator_vhdl_beh;
ARCHITECTURE behavioral OF fifo_generator_vhdl_beh IS
COMPONENT fifo_generator_v13_0_1_conv IS
GENERIC (
---------------------------------------------------------------------------
-- Generic Declarations
---------------------------------------------------------------------------
C_COMMON_CLOCK : integer := 0;
C_INTERFACE_TYPE : integer := 0;
C_COUNT_TYPE : integer := 0; --not used
C_DATA_COUNT_WIDTH : integer := 2;
C_DEFAULT_VALUE : string := ""; --not used
C_DIN_WIDTH : integer := 8;
C_DOUT_RST_VAL : string := "";
C_DOUT_WIDTH : integer := 8;
C_ENABLE_RLOCS : integer := 0; --not used
C_FAMILY : string := ""; --not used in bhv model
C_FULL_FLAGS_RST_VAL : integer := 0;
C_HAS_ALMOST_EMPTY : integer := 0;
C_HAS_ALMOST_FULL : integer := 0;
C_HAS_BACKUP : integer := 0; --not used
C_HAS_DATA_COUNT : integer := 0;
C_HAS_INT_CLK : integer := 0; --not used in bhv model
C_HAS_MEMINIT_FILE : integer := 0; --not used
C_HAS_OVERFLOW : integer := 0;
C_HAS_RD_DATA_COUNT : integer := 0;
C_HAS_RD_RST : integer := 0; --not used
C_HAS_RST : integer := 1;
C_HAS_SRST : integer := 0;
C_HAS_UNDERFLOW : integer := 0;
C_HAS_VALID : integer := 0;
C_HAS_WR_ACK : integer := 0;
C_HAS_WR_DATA_COUNT : integer := 0;
C_HAS_WR_RST : integer := 0; --not used
C_IMPLEMENTATION_TYPE : integer := 0;
C_INIT_WR_PNTR_VAL : integer := 0; --not used
C_MEMORY_TYPE : integer := 1;
C_MIF_FILE_NAME : string := ""; --not used
C_OPTIMIZATION_MODE : integer := 0; --not used
C_OVERFLOW_LOW : integer := 0;
C_PRELOAD_LATENCY : integer := 1;
C_PRELOAD_REGS : integer := 0;
C_PRIM_FIFO_TYPE : string := "4kx4"; --not used in bhv model
C_PROG_EMPTY_THRESH_ASSERT_VAL: integer := 0;
C_PROG_EMPTY_THRESH_NEGATE_VAL: integer := 0;
C_PROG_EMPTY_TYPE : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL : integer := 0;
C_PROG_FULL_THRESH_NEGATE_VAL : integer := 0;
C_PROG_FULL_TYPE : integer := 0;
C_RD_DATA_COUNT_WIDTH : integer := 2;
C_RD_DEPTH : integer := 256;
C_RD_FREQ : integer := 1; --not used in bhv model
C_RD_PNTR_WIDTH : integer := 8;
C_UNDERFLOW_LOW : integer := 0;
C_USE_DOUT_RST : integer := 0;
C_USE_ECC : integer := 0;
C_USE_EMBEDDED_REG : integer := 0;
C_USE_FIFO16_FLAGS : integer := 0; --not used in bhv model
C_USE_FWFT_DATA_COUNT : integer := 0;
C_VALID_LOW : integer := 0;
C_WR_ACK_LOW : integer := 0;
C_WR_DATA_COUNT_WIDTH : integer := 2;
C_WR_DEPTH : integer := 256;
C_WR_FREQ : integer := 1; --not used in bhv model
C_WR_PNTR_WIDTH : integer := 8;
C_WR_RESPONSE_LATENCY : integer := 1; --not used
C_MSGON_VAL : integer := 1; --not used in bhv model
C_ENABLE_RST_SYNC : integer := 1;
C_EN_SAFETY_CKT : integer := 0;
C_ERROR_INJECTION_TYPE : integer := 0;
C_FIFO_TYPE : integer := 0;
C_SYNCHRONIZER_STAGE : integer := 2;
C_AXI_TYPE : integer := 0
);
PORT(
--------------------------------------------------------------------------------
-- Input and Output Declarations
--------------------------------------------------------------------------------
BACKUP : IN std_logic := '0';
BACKUP_MARKER : IN std_logic := '0';
CLK : IN std_logic := '0';
RST : IN std_logic := '0';
SRST : IN std_logic := '0';
WR_CLK : IN std_logic := '0';
WR_RST : IN std_logic := '0';
RD_CLK : IN std_logic := '0';
RD_RST : IN std_logic := '0';
DIN : IN std_logic_vector(C_DIN_WIDTH-1 DOWNTO 0); --
WR_EN : IN std_logic; --Mandatory input
RD_EN : IN std_logic; --Mandatory input
--Mandatory input
PROG_EMPTY_THRESH : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_EMPTY_THRESH_ASSERT : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_EMPTY_THRESH_NEGATE : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH_ASSERT : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH_NEGATE : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
INT_CLK : IN std_logic := '0';
INJECTDBITERR : IN std_logic := '0';
INJECTSBITERR : IN std_logic := '0';
DOUT : OUT std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0);
FULL : OUT std_logic;
ALMOST_FULL : OUT std_logic;
WR_ACK : OUT std_logic;
OVERFLOW : OUT std_logic;
EMPTY : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
VALID : OUT std_logic;
UNDERFLOW : OUT std_logic;
DATA_COUNT : OUT std_logic_vector(C_DATA_COUNT_WIDTH-1 DOWNTO 0);
RD_DATA_COUNT : OUT std_logic_vector(C_RD_DATA_COUNT_WIDTH-1 DOWNTO 0);
WR_DATA_COUNT : OUT std_logic_vector(C_WR_DATA_COUNT_WIDTH-1 DOWNTO 0);
PROG_FULL : OUT std_logic;
PROG_EMPTY : OUT std_logic;
SBITERR : OUT std_logic := '0';
DBITERR : OUT std_logic := '0';
WR_RST_BUSY : OUT std_logic := '0';
RD_RST_BUSY : OUT std_logic := '0';
WR_RST_I_OUT : OUT std_logic := '0';
RD_RST_I_OUT : OUT std_logic := '0'
);
END COMPONENT;
COMPONENT fifo_generator_v13_0_1_axic_reg_slice IS
GENERIC (
C_FAMILY : string := "";
C_DATA_WIDTH : integer := 32;
C_REG_CONFIG : integer := 0
);
PORT (
-- System Signals
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
-- Slave side
S_PAYLOAD_DATA : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
S_VALID : IN STD_LOGIC;
S_READY : OUT STD_LOGIC := '0';
-- Master side
M_PAYLOAD_DATA : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_VALID : OUT STD_LOGIC := '0';
M_READY : IN STD_LOGIC
);
END COMPONENT;
-- CONSTANT C_AXI_LEN_WIDTH : integer := 8;
CONSTANT C_AXI_SIZE_WIDTH : integer := 3;
CONSTANT C_AXI_BURST_WIDTH : integer := 2;
-- CONSTANT C_AXI_LOCK_WIDTH : integer := 2;
CONSTANT C_AXI_CACHE_WIDTH : integer := 4;
CONSTANT C_AXI_PROT_WIDTH : integer := 3;
CONSTANT C_AXI_QOS_WIDTH : integer := 4;
CONSTANT C_AXI_REGION_WIDTH : integer := 4;
CONSTANT C_AXI_BRESP_WIDTH : integer := 2;
CONSTANT C_AXI_RRESP_WIDTH : integer := 2;
CONSTANT TFF : time := 100 ps;
-----------------------------------------------------------------------------
-- FUNCTION if_then_else
-- Returns a true case or flase case based on the condition
-------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : boolean;
true_case : integer;
false_case : integer)
RETURN integer IS
VARIABLE retval : integer := 0;
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
------------------------------------------------------------------------------
-- This function is used to implement an IF..THEN when such a statement is not
-- allowed and returns string.
------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : boolean;
true_case : string;
false_case : string)
RETURN string IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
---------------------------------------------------------------------------
-- FUNCTION : log2roundup
---------------------------------------------------------------------------
FUNCTION log2roundup (
data_value : integer)
RETURN integer IS
VARIABLE width : integer := 0;
VARIABLE cnt : integer := 1;
CONSTANT lower_limit : integer := 1;
CONSTANT upper_limit : integer := 8;
BEGIN
IF (data_value <= 1) THEN
width := 0;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
-----------------------------------------------------------------------------
-- FUNCTION : bin2gray
-----------------------------------------------------------------------------
-- This function receives a binary value, and returns the associated
-- graycoded value.
FUNCTION bin2gray (
indata : std_logic_vector;
length : integer)
RETURN std_logic_vector IS
VARIABLE tmp_value : std_logic_vector(length-1 DOWNTO 0);
BEGIN
tmp_value(length-1) := indata(length-1);
gray_loop : FOR I IN length-2 DOWNTO 0 LOOP
tmp_value(I) := indata(I) XOR indata(I+1);
END LOOP;
RETURN tmp_value;
END bin2gray;
-----------------------------------------------------------------------------
-- FUNCTION : gray2bin
-----------------------------------------------------------------------------
-- This function receives a gray-coded value, and returns the associated
-- binary value.
FUNCTION gray2bin (
indata : std_logic_vector;
length : integer)
RETURN std_logic_vector IS
VARIABLE tmp_value : std_logic_vector(length-1 DOWNTO 0);
BEGIN
tmp_value(length-1) := indata(length-1);
gray_loop : FOR I IN length-2 DOWNTO 0 LOOP
tmp_value(I) := XOR_REDUCE(indata(length-1 DOWNTO I));
END LOOP;
RETURN tmp_value;
END gray2bin;
--------------------------------------------------------
-- FUNCION : map_ready_valid
-- Returns the READY signal that is mapped out of FULL or ALMOST_FULL or PROG_FULL
-- Returns the VALID signal that is mapped out of EMPTY or ALMOST_EMPTY or PROG_EMPTY
--------------------------------------------------------
FUNCTION map_ready_valid(
pf_pe_type : integer;
full_empty : std_logic;
af_ae : std_logic;
pf_pe : std_logic)
RETURN std_logic IS
BEGIN
IF (pf_pe_type = 5) THEN
RETURN NOT full_empty;
ELSIF (pf_pe_type = 6) THEN
RETURN NOT af_ae;
ELSE
RETURN NOT pf_pe;
END IF;
END map_ready_valid;
SIGNAL inverted_reset : std_logic := '0';
SIGNAL axi_rs_rst : std_logic := '0';
CONSTANT IS_V8 : INTEGER := if_then_else((C_FAMILY = "virtexu"),1,0);
CONSTANT IS_K8 : INTEGER := if_then_else((C_FAMILY = "kintexu"),1,0);
CONSTANT IS_A8 : INTEGER := if_then_else((C_FAMILY = "artixu"),1,0);
CONSTANT IS_VM : INTEGER := if_then_else((C_FAMILY = "virtexuplus"),1,0);
CONSTANT IS_KM : INTEGER := if_then_else((C_FAMILY = "kintexuplus"),1,0);
CONSTANT IS_ZNQU : INTEGER := if_then_else((C_FAMILY = "zynquplus"),1,0);
CONSTANT IS_8SERIES : INTEGER := if_then_else((IS_V8 = 1 OR IS_K8 = 1 OR IS_A8 = 1 OR IS_VM = 1 OR IS_ZNQU = 1 OR IS_KM = 1),1,0);
BEGIN
inverted_reset <= NOT S_ARESETN;
gaxi_rs_rst: IF (C_INTERFACE_TYPE > 0 AND (C_AXIS_TYPE = 1 OR C_WACH_TYPE = 1 OR
C_WDCH_TYPE = 1 OR C_WRCH_TYPE = 1 OR C_RACH_TYPE = 1 OR C_RDCH_TYPE = 1)) GENERATE
SIGNAL rst_d1 : STD_LOGIC := '1';
SIGNAL rst_d2 : STD_LOGIC := '1';
BEGIN
prst: PROCESS (inverted_reset, S_ACLK)
BEGIN
IF (inverted_reset = '1') THEN
rst_d1 <= '1';
rst_d2 <= '1';
ELSIF (S_ACLK'event AND S_ACLK = '1') THEN
rst_d1 <= '0' AFTER TFF;
rst_d2 <= rst_d1 AFTER TFF;
END IF;
END PROCESS prst;
axi_rs_rst <= rst_d2;
END GENERATE gaxi_rs_rst;
---------------------------------------------------------------------------
-- Top level instance for Conventional FIFO.
---------------------------------------------------------------------------
gconvfifo: IF (C_INTERFACE_TYPE = 0) GENERATE
SIGNAL wr_data_count_in : std_logic_vector (C_WR_DATA_COUNT_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
signal full_i : std_logic := '0';
signal empty_i : std_logic := '0';
signal WR_RST_INT : std_logic := '0';
signal RD_RST_INT : std_logic := '0';
begin
inst_conv_fifo: fifo_generator_v13_0_1_conv
GENERIC map(
C_COMMON_CLOCK => C_COMMON_CLOCK,
C_INTERFACE_TYPE => C_INTERFACE_TYPE,
C_COUNT_TYPE => C_COUNT_TYPE,
C_DATA_COUNT_WIDTH => C_DATA_COUNT_WIDTH,
C_DEFAULT_VALUE => C_DEFAULT_VALUE,
C_DIN_WIDTH => C_DIN_WIDTH,
C_DOUT_RST_VAL => if_then_else(C_USE_DOUT_RST = 1, C_DOUT_RST_VAL, "0"),
C_DOUT_WIDTH => C_DOUT_WIDTH,
C_ENABLE_RLOCS => C_ENABLE_RLOCS,
C_FAMILY => C_FAMILY,
C_FULL_FLAGS_RST_VAL => C_FULL_FLAGS_RST_VAL,
C_HAS_ALMOST_EMPTY => C_HAS_ALMOST_EMPTY,
C_HAS_ALMOST_FULL => C_HAS_ALMOST_FULL,
C_HAS_BACKUP => C_HAS_BACKUP,
C_HAS_DATA_COUNT => C_HAS_DATA_COUNT,
C_HAS_INT_CLK => C_HAS_INT_CLK,
C_HAS_MEMINIT_FILE => C_HAS_MEMINIT_FILE,
C_HAS_OVERFLOW => C_HAS_OVERFLOW,
C_HAS_RD_DATA_COUNT => C_HAS_RD_DATA_COUNT,
C_HAS_RD_RST => C_HAS_RD_RST,
C_HAS_RST => C_HAS_RST,
C_HAS_SRST => C_HAS_SRST,
C_HAS_UNDERFLOW => C_HAS_UNDERFLOW,
C_HAS_VALID => C_HAS_VALID,
C_HAS_WR_ACK => C_HAS_WR_ACK,
C_HAS_WR_DATA_COUNT => C_HAS_WR_DATA_COUNT,
C_HAS_WR_RST => C_HAS_WR_RST,
C_IMPLEMENTATION_TYPE => C_IMPLEMENTATION_TYPE,
C_INIT_WR_PNTR_VAL => C_INIT_WR_PNTR_VAL,
C_MEMORY_TYPE => C_MEMORY_TYPE,
C_MIF_FILE_NAME => C_MIF_FILE_NAME,
C_OPTIMIZATION_MODE => C_OPTIMIZATION_MODE,
C_OVERFLOW_LOW => C_OVERFLOW_LOW,
C_PRELOAD_LATENCY => C_PRELOAD_LATENCY,
C_PRELOAD_REGS => C_PRELOAD_REGS,
C_PRIM_FIFO_TYPE => C_PRIM_FIFO_TYPE,
C_PROG_EMPTY_THRESH_ASSERT_VAL => C_PROG_EMPTY_THRESH_ASSERT_VAL,
C_PROG_EMPTY_THRESH_NEGATE_VAL => C_PROG_EMPTY_THRESH_NEGATE_VAL,
C_PROG_EMPTY_TYPE => C_PROG_EMPTY_TYPE,
C_PROG_FULL_THRESH_ASSERT_VAL => C_PROG_FULL_THRESH_ASSERT_VAL,
C_PROG_FULL_THRESH_NEGATE_VAL => C_PROG_FULL_THRESH_NEGATE_VAL,
C_PROG_FULL_TYPE => C_PROG_FULL_TYPE,
C_RD_DATA_COUNT_WIDTH => C_RD_DATA_COUNT_WIDTH,
C_RD_DEPTH => C_RD_DEPTH,
C_RD_FREQ => C_RD_FREQ,
C_RD_PNTR_WIDTH => C_RD_PNTR_WIDTH,
C_UNDERFLOW_LOW => C_UNDERFLOW_LOW,
C_USE_DOUT_RST => C_USE_DOUT_RST,
C_USE_ECC => C_USE_ECC,
C_USE_EMBEDDED_REG => C_USE_EMBEDDED_REG,
C_USE_FIFO16_FLAGS => C_USE_FIFO16_FLAGS,
C_USE_FWFT_DATA_COUNT => C_USE_FWFT_DATA_COUNT,
C_VALID_LOW => C_VALID_LOW,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_WR_DATA_COUNT_WIDTH => C_WR_DATA_COUNT_WIDTH,
C_WR_DEPTH => C_WR_DEPTH,
C_WR_FREQ => C_WR_FREQ,
C_WR_PNTR_WIDTH => C_WR_PNTR_WIDTH,
C_WR_RESPONSE_LATENCY => C_WR_RESPONSE_LATENCY,
C_MSGON_VAL => C_MSGON_VAL,
C_ENABLE_RST_SYNC => C_ENABLE_RST_SYNC,
C_EN_SAFETY_CKT => C_EN_SAFETY_CKT,
C_ERROR_INJECTION_TYPE => C_ERROR_INJECTION_TYPE,
C_AXI_TYPE => C_AXI_TYPE,
C_SYNCHRONIZER_STAGE => C_SYNCHRONIZER_STAGE
)
PORT MAP(
--Inputs
BACKUP => BACKUP,
BACKUP_MARKER => BACKUP_MARKER,
CLK => CLK,
RST => RST,
SRST => SRST,
WR_CLK => WR_CLK,
WR_RST => WR_RST,
RD_CLK => RD_CLK,
RD_RST => RD_RST,
DIN => DIN,
WR_EN => WR_EN,
RD_EN => RD_EN,
PROG_EMPTY_THRESH => PROG_EMPTY_THRESH,
PROG_EMPTY_THRESH_ASSERT => PROG_EMPTY_THRESH_ASSERT,
PROG_EMPTY_THRESH_NEGATE => PROG_EMPTY_THRESH_NEGATE,
PROG_FULL_THRESH => PROG_FULL_THRESH,
PROG_FULL_THRESH_ASSERT => PROG_FULL_THRESH_ASSERT,
PROG_FULL_THRESH_NEGATE => PROG_FULL_THRESH_NEGATE,
INT_CLK => INT_CLK,
INJECTDBITERR => INJECTDBITERR,
INJECTSBITERR => INJECTSBITERR,
--Outputs
DOUT => DOUT,
FULL => full_i,
ALMOST_FULL => ALMOST_FULL,
WR_ACK => WR_ACK,
OVERFLOW => OVERFLOW,
EMPTY => empty_i,
ALMOST_EMPTY => ALMOST_EMPTY,
VALID => VALID,
UNDERFLOW => UNDERFLOW,
DATA_COUNT => DATA_COUNT,
RD_DATA_COUNT => RD_DATA_COUNT,
WR_DATA_COUNT => wr_data_count_in,
PROG_FULL => PROG_FULL,
PROG_EMPTY => PROG_EMPTY,
SBITERR => SBITERR,
DBITERR => DBITERR,
WR_RST_BUSY => WR_RST_BUSY,
RD_RST_BUSY => RD_RST_BUSY,
WR_RST_I_OUT => WR_RST_INT,
RD_RST_I_OUT => RD_RST_INT
);
FULL <= full_i;
EMPTY <= empty_i;
fifo_ic_adapter: IF (C_HAS_DATA_COUNTS_AXIS = 3) GENERATE
SIGNAL wr_eop : STD_LOGIC := '0';
SIGNAL rd_eop : STD_LOGIC := '0';
SIGNAL data_read : STD_LOGIC := '0';
SIGNAL w_cnt : STD_LOGIC_VECTOR(log2roundup(C_WR_DEPTH)-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL r_cnt : STD_LOGIC_VECTOR(log2roundup(C_WR_DEPTH)-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL w_cnt_gc : STD_LOGIC_VECTOR(log2roundup(C_WR_DEPTH)-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL w_cnt_gc_asreg_last : STD_LOGIC_VECTOR(log2roundup(C_WR_DEPTH)-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL w_cnt_rd : STD_LOGIC_VECTOR(log2roundup(C_WR_DEPTH)-1 DOWNTO 0) := (OTHERS => '0');
--SIGNAL axis_wr_rst : STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
--SIGNAL axis_rd_rst : STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL d_cnt : std_logic_vector(log2roundup(C_WR_DEPTH)-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL d_cnt_pad : std_logic_vector(log2roundup(C_WR_DEPTH) DOWNTO 0) := (OTHERS => '0');
SIGNAL adj_w_cnt_rd_pad : std_logic_vector(log2roundup(C_WR_DEPTH) DOWNTO 0) := (others => '0');
SIGNAL r_inv_pad : std_logic_vector(log2roundup(C_WR_DEPTH) DOWNTO 0) := (others => '0');
-- Defined to connect data output of one FIFO to data input of another
TYPE w_sync_array IS ARRAY (0 TO C_SYNCHRONIZER_STAGE) OF std_logic_vector(log2roundup(C_WR_DEPTH)-1 DOWNTO 0);
SIGNAL w_q : w_sync_array := (OTHERS => (OTHERS => '0'));
TYPE axis_af_array IS ARRAY (0 TO C_SYNCHRONIZER_STAGE) OF std_logic_vector(0 DOWNTO 0);
BEGIN
wr_eop <= WR_EN AND not(full_i);
rd_eop <= RD_EN AND not(empty_i);
-- Write Packet count logic
proc_w_cnt: PROCESS (WR_CLK, WR_RST_INT)
BEGIN
IF (WR_RST_INT = '1') THEN
w_cnt <= (OTHERS => '0');
ELSIF (WR_CLK = '1' AND WR_CLK'EVENT) THEN
IF (wr_eop = '1') THEN
w_cnt <= w_cnt + "1" AFTER TFF;
END IF;
END IF;
END PROCESS proc_w_cnt;
-- Convert Write Packet count to Grey
pw_gc : PROCESS (WR_CLK, WR_RST_INT)
BEGIN
if (WR_RST_INT = '1') then
w_cnt_gc <= (OTHERS => '0');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
w_cnt_gc <= bin2gray(w_cnt, log2roundup(C_WR_DEPTH)) AFTER TFF;
END IF;
END PROCESS pw_gc;
-- Synchronize the Write Packet count in read domain
-- Synchronize the axis_almost_full in read domain
gpkt_cnt_sync_stage: FOR I IN 1 TO C_SYNCHRONIZER_STAGE GENERATE
BEGIN
-- pkt_rd_stg_inst: ENTITY fifo_generator_v13_0_1.synchronizer_ff
-- GENERIC MAP (
-- C_HAS_RST => C_HAS_RST,
-- C_WIDTH => log2roundup(C_WR_DEPTH_AXIS)
-- )
-- PORT MAP (
-- RST => axis_rd_rst(0),
-- CLK => M_ACLK,
-- D => wpkt_q(i-1),
-- Q => wpkt_q(i)
-- );
PROCESS (RD_CLK, RD_RST_INT)
BEGIN
IF (RD_RST_INT = '1' AND C_HAS_RST = 1) THEN
w_q(i) <= (OTHERS => '0');
ELSIF RD_CLK'EVENT AND RD_CLK = '1' THEN
w_q(i) <= w_q(i-1) AFTER TFF;
END IF;
END PROCESS;
END GENERATE gpkt_cnt_sync_stage;
w_q(0) <= w_cnt_gc;
w_cnt_gc_asreg_last <= w_q(C_SYNCHRONIZER_STAGE);
-- Convert synchronized Write Packet count grey value to binay
pw_rd_bin : PROCESS (RD_CLK, RD_RST_INT)
BEGIN
if (RD_RST_INT = '1') then
w_cnt_rd <= (OTHERS => '0');
ELSIF (RD_CLK'event AND RD_CLK = '1') THEN
w_cnt_rd <= gray2bin(w_cnt_gc_asreg_last, log2roundup(C_WR_DEPTH)) AFTER TFF;
END IF;
END PROCESS pw_rd_bin;
-- Read Packet count logic
proc_r_cnt: PROCESS (RD_CLK, RD_RST_INT)
BEGIN
IF (RD_RST_INT = '1') THEN
r_cnt <= (OTHERS => '0');
ELSIF (RD_CLK = '1' AND RD_CLK'EVENT) THEN
IF (rd_eop = '1') THEN
r_cnt <= r_cnt + "1" AFTER TFF;
END IF;
END IF;
END PROCESS proc_r_cnt;
-- Take the difference of write and read packet count
-- Logic is similar to rd_pe_as
adj_w_cnt_rd_pad(log2roundup(C_WR_DEPTH) DOWNTO 1) <= w_cnt_rd;
r_inv_pad(log2roundup(C_WR_DEPTH) DOWNTO 1) <= not r_cnt;
p_cry: PROCESS (rd_eop)
BEGIN
IF (rd_eop = '0') THEN
adj_w_cnt_rd_pad(0) <= '1';
r_inv_pad(0) <= '1';
ELSE
adj_w_cnt_rd_pad(0) <= '0';
r_inv_pad(0) <= '0';
END IF;
END PROCESS p_cry;
p_sub: PROCESS (RD_CLK, RD_RST_INT)
BEGIN
IF (RD_RST_INT = '1') THEN
d_cnt_pad <= (OTHERS=>'0');
ELSIF RD_CLK'event AND RD_CLK = '1' THEN
d_cnt_pad <= adj_w_cnt_rd_pad + r_inv_pad AFTER TFF;
END IF;
END PROCESS p_sub;
d_cnt <= d_cnt_pad(log2roundup(C_WR_DEPTH) DOWNTO 1);
WR_DATA_COUNT <= d_cnt;
END GENERATE fifo_ic_adapter;
fifo_icn_adapter: IF (C_HAS_DATA_COUNTS_AXIS /= 3) GENERATE
WR_DATA_COUNT <= wr_data_count_in;
END GENERATE fifo_icn_adapter;
END GENERATE gconvfifo; -- End of conventional FIFO
---------------------------------------------------------------------------
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Top level instance for ramfifo in AXI Streaming FIFO core. It implements:
-- * BRAM based FIFO
-- * Dist RAM based FIFO
---------------------------------------------------------------------------
---------------------------------------------------------------------------
---------------------------------------------------------------------------
gaxis_fifo: IF ((C_INTERFACE_TYPE = 1) AND (C_AXIS_TYPE < 2)) GENERATE
SIGNAL axis_din : std_logic_vector(C_DIN_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL axis_dout : std_logic_vector(C_DIN_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL axis_full : std_logic := '0';
SIGNAL axis_almost_full : std_logic := '0';
SIGNAL axis_empty : std_logic := '0';
SIGNAL axis_s_axis_tready : std_logic := '0';
SIGNAL axis_m_axis_tvalid : std_logic := '0';
SIGNAL axis_wr_en : std_logic := '0';
SIGNAL axis_rd_en : std_logic := '0';
SIGNAL axis_dc : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH_AXIS DOWNTO 0) := (OTHERS => '0');
SIGNAL wr_rst_busy_axis : STD_LOGIC := '0';
SIGNAL rd_rst_busy_axis : STD_LOGIC := '0';
CONSTANT TDATA_OFFSET : integer := if_then_else(C_HAS_AXIS_TDATA = 1,C_DIN_WIDTH_AXIS-C_AXIS_TDATA_WIDTH,C_DIN_WIDTH_AXIS);
CONSTANT TSTRB_OFFSET : integer := if_then_else(C_HAS_AXIS_TSTRB = 1,TDATA_OFFSET-C_AXIS_TSTRB_WIDTH,TDATA_OFFSET);
CONSTANT TKEEP_OFFSET : integer := if_then_else(C_HAS_AXIS_TKEEP = 1,TSTRB_OFFSET-C_AXIS_TKEEP_WIDTH,TSTRB_OFFSET);
CONSTANT TID_OFFSET : integer := if_then_else(C_HAS_AXIS_TID = 1,TKEEP_OFFSET-C_AXIS_TID_WIDTH,TKEEP_OFFSET);
CONSTANT TDEST_OFFSET : integer := if_then_else(C_HAS_AXIS_TDEST = 1,TID_OFFSET-C_AXIS_TDEST_WIDTH,TID_OFFSET);
CONSTANT TUSER_OFFSET : integer := if_then_else(C_HAS_AXIS_TUSER = 1,TDEST_OFFSET-C_AXIS_TUSER_WIDTH,TDEST_OFFSET);
BEGIN
-- Generate the DIN to FIFO by concatinating the AXIS optional ports
gdin1: IF (C_HAS_AXIS_TDATA = 1) GENERATE
axis_din(C_DIN_WIDTH_AXIS-1 DOWNTO TDATA_OFFSET) <= S_AXIS_TDATA;
M_AXIS_TDATA <= axis_dout(C_DIN_WIDTH_AXIS-1 DOWNTO TDATA_OFFSET);
END GENERATE gdin1;
gdin2: IF (C_HAS_AXIS_TSTRB = 1) GENERATE
axis_din(TDATA_OFFSET-1 DOWNTO TSTRB_OFFSET) <= S_AXIS_TSTRB;
M_AXIS_TSTRB <= axis_dout(TDATA_OFFSET-1 DOWNTO TSTRB_OFFSET);
END GENERATE gdin2;
gdin3: IF (C_HAS_AXIS_TKEEP = 1) GENERATE
axis_din(TSTRB_OFFSET-1 DOWNTO TKEEP_OFFSET) <= S_AXIS_TKEEP;
M_AXIS_TKEEP <= axis_dout(TSTRB_OFFSET-1 DOWNTO TKEEP_OFFSET);
END GENERATE gdin3;
gdin4: IF (C_HAS_AXIS_TID = 1) GENERATE
axis_din(TKEEP_OFFSET-1 DOWNTO TID_OFFSET) <= S_AXIS_TID;
M_AXIS_TID <= axis_dout(TKEEP_OFFSET-1 DOWNTO TID_OFFSET);
END GENERATE gdin4;
gdin5: IF (C_HAS_AXIS_TDEST = 1) GENERATE
axis_din(TID_OFFSET-1 DOWNTO TDEST_OFFSET) <= S_AXIS_TDEST;
M_AXIS_TDEST <= axis_dout(TID_OFFSET-1 DOWNTO TDEST_OFFSET);
END GENERATE gdin5;
gdin6: IF (C_HAS_AXIS_TUSER = 1) GENERATE
axis_din(TDEST_OFFSET-1 DOWNTO TUSER_OFFSET) <= S_AXIS_TUSER;
M_AXIS_TUSER <= axis_dout(TDEST_OFFSET-1 DOWNTO TUSER_OFFSET);
END GENERATE gdin6;
gdin7: IF (C_HAS_AXIS_TLAST = 1) GENERATE
axis_din(0) <= S_AXIS_TLAST;
M_AXIS_TLAST <= axis_dout(0);
END GENERATE gdin7;
-- Write protection
-- When FULL is high, pass VALID as a WR_EN to the FIFO to get OVERFLOW interrupt
gaxis_wr_en1: IF (C_PROG_FULL_TYPE_AXIS = 0) GENERATE
gwe_pkt: IF (C_APPLICATION_TYPE_AXIS = 1) GENERATE
axis_wr_en <= S_AXIS_TVALID AND axis_s_axis_tready;
END GENERATE gwe_pkt;
gwe: IF (C_APPLICATION_TYPE_AXIS /= 1) GENERATE
axis_wr_en <= S_AXIS_TVALID;
END GENERATE gwe;
END GENERATE gaxis_wr_en1;
-- When ALMOST_FULL or PROG_FULL is high, then shield the FIFO from becoming FULL
gaxis_wr_en2: IF (C_PROG_FULL_TYPE_AXIS /= 0) GENERATE
axis_wr_en <= axis_s_axis_tready AND S_AXIS_TVALID;
END GENERATE gaxis_wr_en2;
-- Read protection
-- When EMPTY is low, pass READY as a RD_EN to the FIFO to get UNDERFLOW interrupt
gaxis_rd_en1: IF (C_PROG_EMPTY_TYPE_AXIS = 0) GENERATE
gre_pkt: IF (C_APPLICATION_TYPE_AXIS = 1) GENERATE
axis_rd_en <= M_AXIS_TREADY AND axis_m_axis_tvalid;
END GENERATE gre_pkt;
gre_npkt: IF (C_APPLICATION_TYPE_AXIS /= 1) GENERATE
axis_rd_en <= M_AXIS_TREADY;
END GENERATE gre_npkt;
END GENERATE gaxis_rd_en1;
-- When ALMOST_EMPTY or PROG_EMPTY is low, then shield the FIFO from becoming EMPTY
gaxis_rd_en2: IF (C_PROG_EMPTY_TYPE_AXIS /= 0) GENERATE
axis_rd_en <= axis_m_axis_tvalid AND M_AXIS_TREADY;
END GENERATE gaxis_rd_en2;
gaxisf: IF (C_AXIS_TYPE = 0) GENERATE
SIGNAL axis_we : STD_LOGIC := '0';
SIGNAL axis_re : STD_LOGIC := '0';
SIGNAL axis_wr_rst : STD_LOGIC := '0';
SIGNAL axis_rd_rst : STD_LOGIC := '0';
BEGIN
axis_we <= axis_wr_en WHEN (C_HAS_SLAVE_CE = 0) ELSE axis_wr_en AND S_ACLK_EN;
axis_re <= axis_rd_en WHEN (C_HAS_MASTER_CE = 0) ELSE axis_rd_en AND M_ACLK_EN;
axisf : fifo_generator_v13_0_1_conv
GENERIC MAP (
C_FAMILY => C_FAMILY,
C_COMMON_CLOCK => C_COMMON_CLOCK,
C_INTERFACE_TYPE => C_INTERFACE_TYPE,
C_MEMORY_TYPE => if_then_else((C_IMPLEMENTATION_TYPE_AXIS = 1 OR C_IMPLEMENTATION_TYPE_AXIS = 11),1,
if_then_else((C_IMPLEMENTATION_TYPE_AXIS = 2 OR C_IMPLEMENTATION_TYPE_AXIS = 12),2,4)),
C_IMPLEMENTATION_TYPE => if_then_else((C_IMPLEMENTATION_TYPE_AXIS = 1 OR C_IMPLEMENTATION_TYPE_AXIS = 2),0,
if_then_else((C_IMPLEMENTATION_TYPE_AXIS = 11 OR C_IMPLEMENTATION_TYPE_AXIS = 12),2,6)),
C_PRELOAD_REGS => 1, -- Always FWFT for AXI
C_PRELOAD_LATENCY => 0, -- Always FWFT for AXI
C_DIN_WIDTH => C_DIN_WIDTH_AXIS,
C_WR_DEPTH => C_WR_DEPTH_AXIS,
C_WR_PNTR_WIDTH => C_WR_PNTR_WIDTH_AXIS,
C_DOUT_WIDTH => C_DIN_WIDTH_AXIS,
C_RD_DEPTH => C_WR_DEPTH_AXIS,
C_RD_PNTR_WIDTH => C_WR_PNTR_WIDTH_AXIS,
C_PROG_FULL_TYPE => C_PROG_FULL_TYPE_AXIS,
C_PROG_FULL_THRESH_ASSERT_VAL => C_PROG_FULL_THRESH_ASSERT_VAL_AXIS,
C_PROG_EMPTY_TYPE => C_PROG_EMPTY_TYPE_AXIS,
C_PROG_EMPTY_THRESH_ASSERT_VAL => C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS,
C_USE_ECC => C_USE_ECC_AXIS,
C_ERROR_INJECTION_TYPE => C_ERROR_INJECTION_TYPE_AXIS,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => if_then_else(C_APPLICATION_TYPE_AXIS = 1,1,0),
-- Enable Low Latency Sync FIFO for Common Clock Built-in FIFO
C_FIFO_TYPE => if_then_else(C_APPLICATION_TYPE_AXIS = 1,0,C_APPLICATION_TYPE_AXIS),
C_SYNCHRONIZER_STAGE => C_SYNCHRONIZER_STAGE,
C_AXI_TYPE => if_then_else(C_INTERFACE_TYPE = 1, 0, C_AXI_TYPE),
C_HAS_WR_RST => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_DOUT_RST_VAL => "0",
C_HAS_VALID => 0,
C_VALID_LOW => C_VALID_LOW,
C_HAS_UNDERFLOW => C_HAS_UNDERFLOW,
C_UNDERFLOW_LOW => C_UNDERFLOW_LOW,
C_HAS_WR_ACK => 0,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_HAS_OVERFLOW => C_HAS_OVERFLOW,
C_OVERFLOW_LOW => C_OVERFLOW_LOW,
C_HAS_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 1 AND C_HAS_DATA_COUNTS_AXIS = 1), 1, 0),
C_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_AXIS+1,
C_HAS_RD_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 0 AND C_HAS_DATA_COUNTS_AXIS = 1), 1, 0),
C_RD_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_AXIS+1,
C_USE_FWFT_DATA_COUNT => 1, -- use extra logic is always true
C_HAS_WR_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 0 AND C_HAS_DATA_COUNTS_AXIS = 1), 1, 0),
C_WR_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_AXIS+1,
C_FULL_FLAGS_RST_VAL => 1,
C_USE_EMBEDDED_REG => C_USE_EMBEDDED_REG,
C_USE_DOUT_RST => 0,
C_MSGON_VAL => C_MSGON_VAL,
C_ENABLE_RST_SYNC => 1,
C_EN_SAFETY_CKT => 1,
C_COUNT_TYPE => C_COUNT_TYPE,
C_DEFAULT_VALUE => C_DEFAULT_VALUE,
C_ENABLE_RLOCS => C_ENABLE_RLOCS,
C_HAS_BACKUP => C_HAS_BACKUP,
C_HAS_INT_CLK => C_HAS_INT_CLK,
C_HAS_MEMINIT_FILE => C_HAS_MEMINIT_FILE,
C_INIT_WR_PNTR_VAL => C_INIT_WR_PNTR_VAL,
C_MIF_FILE_NAME => C_MIF_FILE_NAME,
C_OPTIMIZATION_MODE => C_OPTIMIZATION_MODE,
C_RD_FREQ => C_RD_FREQ,
C_USE_FIFO16_FLAGS => C_USE_FIFO16_FLAGS,
C_WR_FREQ => C_WR_FREQ,
C_WR_RESPONSE_LATENCY => C_WR_RESPONSE_LATENCY
)
PORT MAP(
--Inputs
BACKUP => BACKUP,
BACKUP_MARKER => BACKUP_MARKER,
INT_CLK => INT_CLK,
CLK => S_ACLK,
WR_CLK => S_ACLK,
RD_CLK => M_ACLK,
RST => inverted_reset,
SRST => '0',
WR_RST => inverted_reset,
RD_RST => inverted_reset,
WR_EN => axis_we,
RD_EN => axis_re,
PROG_FULL_THRESH => AXIS_PROG_FULL_THRESH,
PROG_FULL_THRESH_ASSERT => (OTHERS => '0'),
PROG_FULL_THRESH_NEGATE => (OTHERS => '0'),
PROG_EMPTY_THRESH => AXIS_PROG_EMPTY_THRESH,
PROG_EMPTY_THRESH_ASSERT => (OTHERS => '0'),
PROG_EMPTY_THRESH_NEGATE => (OTHERS => '0'),
INJECTDBITERR => AXIS_INJECTDBITERR,
INJECTSBITERR => AXIS_INJECTSBITERR,
DIN => axis_din,
DOUT => axis_dout,
FULL => axis_full,
EMPTY => axis_empty,
ALMOST_FULL => axis_almost_full,
PROG_FULL => AXIS_PROG_FULL,
ALMOST_EMPTY => OPEN,
PROG_EMPTY => AXIS_PROG_EMPTY,
WR_ACK => OPEN,
OVERFLOW => AXIS_OVERFLOW,
VALID => OPEN,
UNDERFLOW => AXIS_UNDERFLOW,
DATA_COUNT => axis_dc,
RD_DATA_COUNT => AXIS_RD_DATA_COUNT,
WR_DATA_COUNT => AXIS_WR_DATA_COUNT,
SBITERR => AXIS_SBITERR,
DBITERR => AXIS_DBITERR,
WR_RST_BUSY => wr_rst_busy_axis,
RD_RST_BUSY => rd_rst_busy_axis,
WR_RST_I_OUT => axis_wr_rst,
RD_RST_I_OUT => axis_rd_rst
);
g8s_axis_rdy: IF (IS_8SERIES = 1) GENERATE
g8s_bi_axis_rdy: IF (C_IMPLEMENTATION_TYPE_AXIS = 5 OR C_IMPLEMENTATION_TYPE_AXIS = 13) GENERATE
axis_s_axis_tready <= NOT (axis_full OR wr_rst_busy_axis);
END GENERATE g8s_bi_axis_rdy;
g8s_nbi_axis_rdy: IF (NOT (C_IMPLEMENTATION_TYPE_AXIS = 5 OR C_IMPLEMENTATION_TYPE_AXIS = 13)) GENERATE
axis_s_axis_tready <= NOT (axis_full);
END GENERATE g8s_nbi_axis_rdy;
END GENERATE g8s_axis_rdy;
g7s_axis_rdy: IF (IS_8SERIES = 0) GENERATE
axis_s_axis_tready <= NOT (axis_full);
END GENERATE g7s_axis_rdy;
--axis_m_axis_tvalid <= NOT axis_empty WHEN (C_APPLICATION_TYPE_AXIS /= 1) ELSE NOT axis_empty AND axis_pkt_read;
gnaxis_pkt_fifo: IF (C_APPLICATION_TYPE_AXIS /= 1) GENERATE
axis_m_axis_tvalid <= NOT axis_empty;
END GENERATE gnaxis_pkt_fifo;
S_AXIS_TREADY <= axis_s_axis_tready;
M_AXIS_TVALID <= axis_m_axis_tvalid;
gaxis_pkt_fifo_cc: IF (C_APPLICATION_TYPE_AXIS = 1 AND C_COMMON_CLOCK = 1) GENERATE
SIGNAL axis_wr_eop : STD_LOGIC := '0';
SIGNAL axis_wr_eop_d1 : STD_LOGIC := '0';
SIGNAL axis_rd_eop : STD_LOGIC := '0';
SIGNAL axis_pkt_cnt : INTEGER := 0;
SIGNAL axis_pkt_read : STD_LOGIC := '0';
BEGIN
axis_m_axis_tvalid <= NOT axis_empty AND axis_pkt_read;
axis_wr_eop <= axis_we AND S_AXIS_TLAST;
axis_rd_eop <= axis_re AND axis_dout(0);
-- Packet Read Generation logic
PROCESS (S_ACLK, inverted_reset)
BEGIN
IF (inverted_reset = '1') THEN
axis_pkt_read <= '0';
axis_wr_eop_d1 <= '0';
ELSIF (S_ACLK = '1' AND S_ACLK'EVENT) THEN
axis_wr_eop_d1 <= axis_wr_eop;
IF (axis_rd_eop = '1' AND (axis_pkt_cnt = 1) AND axis_wr_eop_d1 = '0') THEN
axis_pkt_read <= '0' AFTER TFF;
ELSIF ((axis_pkt_cnt > 0) OR (axis_almost_full = '1' AND axis_empty = '0')) THEN
axis_pkt_read <= '1' AFTER TFF;
END IF;
END IF;
END PROCESS;
-- Packet count logic
PROCESS (S_ACLK, inverted_reset)
BEGIN
IF (inverted_reset = '1') THEN
axis_pkt_cnt <= 0;
ELSIF (S_ACLK = '1' AND S_ACLK'EVENT) THEN
IF (axis_wr_eop_d1 = '1' AND axis_rd_eop = '0') THEN
axis_pkt_cnt <= axis_pkt_cnt + 1 AFTER TFF;
ELSIF (axis_rd_eop = '1' AND axis_wr_eop_d1 = '0') THEN
axis_pkt_cnt <= axis_pkt_cnt - 1 AFTER TFF;
END IF;
END IF;
END PROCESS;
END GENERATE gaxis_pkt_fifo_cc;
gaxis_pkt_fifo_ic: IF (C_APPLICATION_TYPE_AXIS = 1 AND C_COMMON_CLOCK = 0) GENERATE
SIGNAL axis_wr_eop : STD_LOGIC := '0';
SIGNAL axis_rd_eop : STD_LOGIC := '0';
SIGNAL axis_pkt_read : STD_LOGIC := '0';
SIGNAL axis_wpkt_cnt : STD_LOGIC_VECTOR(log2roundup(C_WR_DEPTH_AXIS)-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL axis_rpkt_cnt : STD_LOGIC_VECTOR(log2roundup(C_WR_DEPTH_AXIS)-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL axis_wpkt_cnt_gc : STD_LOGIC_VECTOR(log2roundup(C_WR_DEPTH_AXIS)-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL axis_wpkt_cnt_gc_asreg_last : STD_LOGIC_VECTOR(log2roundup(C_WR_DEPTH_AXIS)-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL axis_wpkt_cnt_rd : STD_LOGIC_VECTOR(log2roundup(C_WR_DEPTH_AXIS)-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL diff_pkt_cnt : std_logic_vector(log2roundup(C_WR_DEPTH_AXIS)-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL diff_pkt_cnt_pad : std_logic_vector(log2roundup(C_WR_DEPTH_AXIS) DOWNTO 0) := (OTHERS => '0');
SIGNAL adj_axis_wpkt_cnt_rd_pad : std_logic_vector(log2roundup(C_WR_DEPTH_AXIS) DOWNTO 0) := (others => '0');
SIGNAL rpkt_inv_pad : std_logic_vector(log2roundup(C_WR_DEPTH_AXIS) DOWNTO 0) := (others => '0');
-- Defined to connect data output of one FIFO to data input of another
TYPE wpkt_sync_array IS ARRAY (0 TO C_SYNCHRONIZER_STAGE) OF std_logic_vector(log2roundup(C_WR_DEPTH_AXIS)-1 DOWNTO 0);
SIGNAL wpkt_q : wpkt_sync_array := (OTHERS => (OTHERS => '0'));
TYPE axis_af_array IS ARRAY (0 TO C_SYNCHRONIZER_STAGE) OF std_logic_vector(0 DOWNTO 0);
SIGNAL axis_af_q : axis_af_array := (OTHERS => (OTHERS => '0'));
SIGNAL axis_af_rd : std_logic_vector(0 DOWNTO 0) := (others => '0');
BEGIN
axis_wr_eop <= axis_we AND S_AXIS_TLAST;
axis_rd_eop <= axis_re AND axis_dout(0);
-- Packet Read Generation logic
PROCESS (M_ACLK, axis_rd_rst)
BEGIN
IF (axis_rd_rst = '1') THEN
axis_pkt_read <= '0';
ELSIF (M_ACLK = '1' AND M_ACLK'EVENT) THEN
IF (axis_rd_eop = '1' AND (conv_integer(diff_pkt_cnt) = 1)) THEN
axis_pkt_read <= '0' AFTER TFF;
-- Asserting packet read at the same time when the packet is written is not considered because it causes
-- packet FIFO handshake violation when the packet size is just 2 data beat and each write is separated
-- by more than 2 clocks. This causes the first data to come out at the FWFT stage making the actual FIFO
-- empty and leaving the first stage FWFT stage with no data, and when the last data is written, it
-- actually makes the valid to be high for a clock and de-asserts immediately as the written data will
-- take two clocks to appear at the FWFT output. This situation is a violation of packet FIFO, where
-- TVALID should not get de-asserted in between the packet transfer.
ELSIF ((conv_integer(diff_pkt_cnt) > 0) OR (axis_af_rd(0) = '1' AND axis_empty = '0')) THEN
axis_pkt_read <= '1' AFTER TFF;
END IF;
END IF;
END PROCESS;
axis_m_axis_tvalid <= (NOT axis_empty) AND axis_pkt_read;
-- Write Packet count logic
proc_wpkt_cnt: PROCESS (S_ACLK, axis_wr_rst)
BEGIN
IF (axis_wr_rst = '1') THEN
axis_wpkt_cnt <= (OTHERS => '0');
ELSIF (S_ACLK = '1' AND S_ACLK'EVENT) THEN
IF (axis_wr_eop = '1') THEN
axis_wpkt_cnt <= axis_wpkt_cnt + "1" AFTER TFF;
END IF;
END IF;
END PROCESS proc_wpkt_cnt;
-- Convert Write Packet count to Grey
pwpkt_gc : PROCESS (S_ACLK, axis_wr_rst)
BEGIN
if (axis_wr_rst = '1') then
axis_wpkt_cnt_gc <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
axis_wpkt_cnt_gc <= bin2gray(axis_wpkt_cnt, log2roundup(C_WR_DEPTH_AXIS)) AFTER TFF;
END IF;
END PROCESS pwpkt_gc;
-- Synchronize the Write Packet count in read domain
-- Synchronize the axis_almost_full in read domain
gpkt_cnt_sync_stage: FOR I IN 1 TO C_SYNCHRONIZER_STAGE GENERATE
BEGIN
-- pkt_rd_stg_inst: ENTITY fifo_generator_v13_0_1.synchronizer_ff
-- GENERIC MAP (
-- C_HAS_RST => C_HAS_RST,
-- C_WIDTH => log2roundup(C_WR_DEPTH_AXIS)
-- )
-- PORT MAP (
-- RST => axis_rd_rst(0),
-- CLK => M_ACLK,
-- D => wpkt_q(i-1),
-- Q => wpkt_q(i)
-- );
PROCESS (M_ACLK, axis_rd_rst)
BEGIN
IF (axis_rd_rst = '1' AND C_HAS_RST = 1) THEN
wpkt_q(i) <= (OTHERS => '0');
ELSIF M_ACLK'EVENT AND M_ACLK = '1' THEN
wpkt_q(i) <= wpkt_q(i-1) AFTER TFF;
END IF;
END PROCESS;
-- af_rd_stg_inst: ENTITY fifo_generator_v13_0_1.synchronizer_ff
-- GENERIC MAP (
-- C_HAS_RST => C_HAS_RST,
-- C_WIDTH => 1
-- )
-- PORT MAP (
-- RST => axis_rd_rst(0),
-- CLK => M_ACLK,
-- D => axis_af_q(i-1),
-- Q => axis_af_q(i)
-- );
PROCESS (M_ACLK, axis_rd_rst)
BEGIN
IF (axis_rd_rst = '1' AND C_HAS_RST = 1) THEN
axis_af_q(i) <= (OTHERS => '0');
ELSIF M_ACLK'EVENT AND M_ACLK = '1' THEN
axis_af_q(i) <= axis_af_q(i-1) AFTER TFF;
END IF;
END PROCESS;
END GENERATE gpkt_cnt_sync_stage;
wpkt_q(0) <= axis_wpkt_cnt_gc;
axis_wpkt_cnt_gc_asreg_last <= wpkt_q(C_SYNCHRONIZER_STAGE);
axis_af_q(0)(0) <= axis_almost_full;
axis_af_rd <= axis_af_q(C_SYNCHRONIZER_STAGE);
-- Convert synchronized Write Packet count grey value to binay
pwpkt_rd_bin : PROCESS (M_ACLK, axis_rd_rst)
BEGIN
if (axis_rd_rst = '1') then
axis_wpkt_cnt_rd <= (OTHERS => '0');
ELSIF (M_ACLK'event AND M_ACLK = '1') THEN
axis_wpkt_cnt_rd <= gray2bin(axis_wpkt_cnt_gc_asreg_last, log2roundup(C_WR_DEPTH_AXIS)) AFTER TFF;
END IF;
END PROCESS pwpkt_rd_bin;
-- Read Packet count logic
proc_rpkt_cnt: PROCESS (M_ACLK, axis_rd_rst)
BEGIN
IF (axis_rd_rst = '1') THEN
axis_rpkt_cnt <= (OTHERS => '0');
ELSIF (M_ACLK = '1' AND M_ACLK'EVENT) THEN
IF (axis_rd_eop = '1') THEN
axis_rpkt_cnt <= axis_rpkt_cnt + "1" AFTER TFF;
END IF;
END IF;
END PROCESS proc_rpkt_cnt;
-- Take the difference of write and read packet count
-- Logic is similar to rd_pe_as
adj_axis_wpkt_cnt_rd_pad(log2roundup(C_WR_DEPTH_AXIS) DOWNTO 1) <= axis_wpkt_cnt_rd;
rpkt_inv_pad(log2roundup(C_WR_DEPTH_AXIS) DOWNTO 1) <= not axis_rpkt_cnt;
pkt_cry: PROCESS (axis_rd_eop)
BEGIN
IF (axis_rd_eop = '0') THEN
adj_axis_wpkt_cnt_rd_pad(0) <= '1';
rpkt_inv_pad(0) <= '1';
ELSE
adj_axis_wpkt_cnt_rd_pad(0) <= '0';
rpkt_inv_pad(0) <= '0';
END IF;
END PROCESS pkt_cry;
pkt_sub: PROCESS (M_ACLK, axis_rd_rst)
BEGIN
IF (axis_rd_rst = '1') THEN
diff_pkt_cnt_pad <= (OTHERS=>'0');
ELSIF M_ACLK'event AND M_ACLK = '1' THEN
diff_pkt_cnt_pad <= adj_axis_wpkt_cnt_rd_pad + rpkt_inv_pad AFTER TFF;
END IF;
END PROCESS pkt_sub;
diff_pkt_cnt <= diff_pkt_cnt_pad(log2roundup(C_WR_DEPTH_AXIS) DOWNTO 1);
END GENERATE gaxis_pkt_fifo_ic;
gdc_pkt: IF (C_HAS_DATA_COUNTS_AXIS = 1 AND C_APPLICATION_TYPE_AXIS = 1) GENERATE
SIGNAL axis_dc_pkt_fifo : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH_AXIS DOWNTO 0) := (OTHERS => '0');
BEGIN
PROCESS (S_ACLK, inverted_reset)
BEGIN
IF (inverted_reset = '1') THEN
axis_dc_pkt_fifo <= (OTHERS => '0');
ELSIF (S_ACLK = '1' AND S_ACLK'EVENT) THEN
IF (axis_we = '1' AND axis_re = '0') THEN
axis_dc_pkt_fifo <= axis_dc_pkt_fifo + "1" AFTER TFF;
ELSIF (axis_we = '0' AND axis_re = '1') THEN
axis_dc_pkt_fifo <= axis_dc_pkt_fifo - "1" AFTER TFF;
END IF;
END IF;
END PROCESS;
AXIS_DATA_COUNT <= axis_dc_pkt_fifo;
END GENERATE gdc_pkt;
gndc_pkt: IF (C_HAS_DATA_COUNTS_AXIS = 0 AND C_APPLICATION_TYPE_AXIS = 1) GENERATE
AXIS_DATA_COUNT <= (OTHERS => '0');
END GENERATE gndc_pkt;
gdc: IF (C_APPLICATION_TYPE_AXIS /= 1) GENERATE
AXIS_DATA_COUNT <= axis_dc;
END GENERATE gdc;
END GENERATE gaxisf;
-- Register Slice for AXI Streaming
gaxis_reg_slice: IF (C_AXIS_TYPE = 1) GENERATE
SIGNAL axis_we : STD_LOGIC := '0';
SIGNAL axis_re : STD_LOGIC := '0';
BEGIN
axis_we <= S_AXIS_TVALID WHEN (C_HAS_SLAVE_CE = 0) ELSE S_AXIS_TVALID AND S_ACLK_EN;
axis_re <= M_AXIS_TREADY WHEN (C_HAS_MASTER_CE = 0) ELSE M_AXIS_TREADY AND M_ACLK_EN;
axis_reg_slice: fifo_generator_v13_0_1_axic_reg_slice
GENERIC MAP (
C_FAMILY => C_FAMILY,
C_DATA_WIDTH => C_DIN_WIDTH_AXIS,
C_REG_CONFIG => C_REG_SLICE_MODE_AXIS
)
PORT MAP(
-- System Signals
ACLK => S_ACLK,
ARESET => axi_rs_rst,
-- Slave side
S_PAYLOAD_DATA => axis_din,
S_VALID => axis_we,
S_READY => S_AXIS_TREADY,
-- Master side
M_PAYLOAD_DATA => axis_dout,
M_VALID => M_AXIS_TVALID,
M_READY => axis_re
);
END GENERATE gaxis_reg_slice;
END GENERATE gaxis_fifo;
gaxifull: IF (C_INTERFACE_TYPE = 2) GENERATE
SIGNAL axi_rd_underflow_i : std_logic := '0';
SIGNAL axi_rd_overflow_i : std_logic := '0';
SIGNAL axi_wr_underflow_i : std_logic := '0';
SIGNAL axi_wr_overflow_i : std_logic := '0';
BEGIN
gwrch: IF (C_HAS_AXI_WR_CHANNEL = 1) GENERATE
SIGNAL wach_din : std_logic_vector(C_DIN_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL wach_dout : std_logic_vector(C_DIN_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL wach_dout_pkt : std_logic_vector(C_DIN_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL wach_full : std_logic := '0';
SIGNAL wach_almost_full : std_logic := '0';
SIGNAL wach_prog_full : std_logic := '0';
SIGNAL wach_empty : std_logic := '0';
SIGNAL wach_almost_empty : std_logic := '0';
SIGNAL wach_prog_empty : std_logic := '0';
SIGNAL wdch_din : std_logic_vector(C_DIN_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL wdch_dout : std_logic_vector(C_DIN_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL wdch_full : std_logic := '0';
SIGNAL wdch_almost_full : std_logic := '0';
SIGNAL wdch_prog_full : std_logic := '0';
SIGNAL wdch_empty : std_logic := '0';
SIGNAL wdch_almost_empty : std_logic := '0';
SIGNAL wdch_prog_empty : std_logic := '0';
SIGNAL wrch_din : std_logic_vector(C_DIN_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL wrch_dout : std_logic_vector(C_DIN_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL wrch_full : std_logic := '0';
SIGNAL wrch_almost_full : std_logic := '0';
SIGNAL wrch_prog_full : std_logic := '0';
SIGNAL wrch_empty : std_logic := '0';
SIGNAL wrch_almost_empty : std_logic := '0';
SIGNAL wrch_prog_empty : std_logic := '0';
SIGNAL axi_aw_underflow_i : std_logic := '0';
SIGNAL axi_w_underflow_i : std_logic := '0';
SIGNAL axi_b_underflow_i : std_logic := '0';
SIGNAL axi_aw_overflow_i : std_logic := '0';
SIGNAL axi_w_overflow_i : std_logic := '0';
SIGNAL axi_b_overflow_i : std_logic := '0';
SIGNAL wach_s_axi_awready : std_logic := '0';
SIGNAL wach_m_axi_awvalid : std_logic := '0';
SIGNAL wach_wr_en : std_logic := '0';
SIGNAL wach_rd_en : std_logic := '0';
SIGNAL wdch_s_axi_wready : std_logic := '0';
SIGNAL wdch_m_axi_wvalid : std_logic := '0';
SIGNAL wdch_wr_en : std_logic := '0';
SIGNAL wdch_rd_en : std_logic := '0';
SIGNAL wrch_s_axi_bvalid : std_logic := '0';
SIGNAL wrch_m_axi_bready : std_logic := '0';
SIGNAL wrch_wr_en : std_logic := '0';
SIGNAL wrch_rd_en : std_logic := '0';
SIGNAL awvalid_en : std_logic := '0';
SIGNAL awready_pkt : std_logic := '0';
SIGNAL wdch_we : STD_LOGIC := '0';
SIGNAL wr_rst_busy_wach : std_logic := '0';
SIGNAL wr_rst_busy_wdch : std_logic := '0';
SIGNAL wr_rst_busy_wrch : std_logic := '0';
SIGNAL rd_rst_busy_wach : std_logic := '0';
SIGNAL rd_rst_busy_wdch : std_logic := '0';
SIGNAL rd_rst_busy_wrch : std_logic := '0';
CONSTANT AWID_OFFSET : integer := if_then_else(C_AXI_TYPE /= 2 AND C_HAS_AXI_ID = 1,C_DIN_WIDTH_WACH - C_AXI_ID_WIDTH,C_DIN_WIDTH_WACH);
CONSTANT AWADDR_OFFSET : integer := AWID_OFFSET - C_AXI_ADDR_WIDTH;
CONSTANT AWLEN_OFFSET : integer := if_then_else(C_AXI_TYPE /= 2,AWADDR_OFFSET - C_AXI_LEN_WIDTH,AWADDR_OFFSET);
CONSTANT AWSIZE_OFFSET : integer := if_then_else(C_AXI_TYPE /= 2,AWLEN_OFFSET - C_AXI_SIZE_WIDTH,AWLEN_OFFSET);
CONSTANT AWBURST_OFFSET : integer := if_then_else(C_AXI_TYPE /= 2,AWSIZE_OFFSET - C_AXI_BURST_WIDTH,AWSIZE_OFFSET);
CONSTANT AWLOCK_OFFSET : integer := if_then_else(C_AXI_TYPE /= 2,AWBURST_OFFSET - C_AXI_LOCK_WIDTH,AWBURST_OFFSET);
CONSTANT AWCACHE_OFFSET : integer := if_then_else(C_AXI_TYPE /= 2,AWLOCK_OFFSET - C_AXI_CACHE_WIDTH,AWLOCK_OFFSET);
CONSTANT AWPROT_OFFSET : integer := AWCACHE_OFFSET - C_AXI_PROT_WIDTH;
CONSTANT AWQOS_OFFSET : integer := AWPROT_OFFSET - C_AXI_QOS_WIDTH;
CONSTANT AWREGION_OFFSET : integer := if_then_else(C_AXI_TYPE = 1,AWQOS_OFFSET - C_AXI_REGION_WIDTH, AWQOS_OFFSET);
CONSTANT AWUSER_OFFSET : integer := if_then_else(C_HAS_AXI_AWUSER = 1,AWREGION_OFFSET-C_AXI_AWUSER_WIDTH,AWREGION_OFFSET);
CONSTANT WID_OFFSET : integer := if_then_else(C_AXI_TYPE = 3 AND C_HAS_AXI_ID = 1,C_DIN_WIDTH_WDCH - C_AXI_ID_WIDTH,C_DIN_WIDTH_WDCH);
CONSTANT WDATA_OFFSET : integer := WID_OFFSET - C_AXI_DATA_WIDTH;
CONSTANT WSTRB_OFFSET : integer := WDATA_OFFSET - C_AXI_DATA_WIDTH/8;
CONSTANT WUSER_OFFSET : integer := if_then_else(C_HAS_AXI_WUSER = 1,WSTRB_OFFSET-C_AXI_WUSER_WIDTH,WSTRB_OFFSET);
CONSTANT BID_OFFSET : integer := if_then_else(C_AXI_TYPE /= 2 AND C_HAS_AXI_ID = 1,C_DIN_WIDTH_WRCH - C_AXI_ID_WIDTH,C_DIN_WIDTH_WRCH);
CONSTANT BRESP_OFFSET : integer := BID_OFFSET - C_AXI_BRESP_WIDTH;
CONSTANT BUSER_OFFSET : integer := if_then_else(C_HAS_AXI_BUSER = 1,BRESP_OFFSET-C_AXI_BUSER_WIDTH,BRESP_OFFSET);
BEGIN
-- Form the DIN to FIFO by concatinating the AXI Full Write Address Channel optional ports
axi_full_din_wr_ch: IF (C_AXI_TYPE /= 2) GENERATE
gwach1: IF (C_WACH_TYPE < 2) GENERATE
gwach_din1: IF (C_HAS_AXI_AWUSER = 1) GENERATE
wach_din(AWREGION_OFFSET-1 DOWNTO AWUSER_OFFSET) <= S_AXI_AWUSER;
M_AXI_AWUSER <= wach_dout(AWREGION_OFFSET-1 DOWNTO AWUSER_OFFSET);
END GENERATE gwach_din1;
gwach_din2: IF (C_HAS_AXI_AWUSER = 0) GENERATE
M_AXI_AWUSER <= (OTHERS => '0');
END GENERATE gwach_din2;
gwach_din3: IF (C_HAS_AXI_ID = 1) GENERATE
wach_din(C_DIN_WIDTH_WACH-1 DOWNTO AWID_OFFSET) <= S_AXI_AWID;
M_AXI_AWID <= wach_dout(C_DIN_WIDTH_WACH-1 DOWNTO AWID_OFFSET);
END GENERATE gwach_din3;
gwach_din4: IF (C_HAS_AXI_ID = 0) GENERATE
M_AXI_AWID <= (OTHERS => '0');
END GENERATE gwach_din4;
gwach_din5: IF (C_AXI_TYPE = 1) GENERATE
wach_din(AWQOS_OFFSET-1 DOWNTO AWREGION_OFFSET) <= S_AXI_AWREGION;
M_AXI_AWREGION <= wach_dout(AWQOS_OFFSET-1 DOWNTO AWREGION_OFFSET);
END GENERATE gwach_din5;
gwach_din6: IF (C_AXI_TYPE = 0) GENERATE
M_AXI_AWREGION <= (OTHERS => '0');
END GENERATE gwach_din6;
wach_din(AWID_OFFSET-1 DOWNTO AWADDR_OFFSET) <= S_AXI_AWADDR;
wach_din(AWADDR_OFFSET-1 DOWNTO AWLEN_OFFSET) <= S_AXI_AWLEN;
wach_din(AWLEN_OFFSET-1 DOWNTO AWSIZE_OFFSET) <= S_AXI_AWSIZE;
wach_din(AWSIZE_OFFSET-1 DOWNTO AWBURST_OFFSET) <= S_AXI_AWBURST;
wach_din(AWBURST_OFFSET-1 DOWNTO AWLOCK_OFFSET) <= S_AXI_AWLOCK;
wach_din(AWLOCK_OFFSET-1 DOWNTO AWCACHE_OFFSET) <= S_AXI_AWCACHE;
wach_din(AWCACHE_OFFSET-1 DOWNTO AWPROT_OFFSET) <= S_AXI_AWPROT;
wach_din(AWPROT_OFFSET-1 DOWNTO AWQOS_OFFSET) <= S_AXI_AWQOS;
M_AXI_AWADDR <= wach_dout(AWID_OFFSET-1 DOWNTO AWADDR_OFFSET);
M_AXI_AWLEN <= wach_dout(AWADDR_OFFSET-1 DOWNTO AWLEN_OFFSET);
M_AXI_AWSIZE <= wach_dout(AWLEN_OFFSET-1 DOWNTO AWSIZE_OFFSET);
M_AXI_AWBURST <= wach_dout(AWSIZE_OFFSET-1 DOWNTO AWBURST_OFFSET);
M_AXI_AWLOCK <= wach_dout(AWBURST_OFFSET-1 DOWNTO AWLOCK_OFFSET);
M_AXI_AWCACHE <= wach_dout(AWLOCK_OFFSET-1 DOWNTO AWCACHE_OFFSET);
M_AXI_AWPROT <= wach_dout(AWCACHE_OFFSET-1 DOWNTO AWPROT_OFFSET);
M_AXI_AWQOS <= wach_dout(AWPROT_OFFSET-1 DOWNTO AWQOS_OFFSET);
END GENERATE gwach1;
-- Generate the DIN to FIFO by concatinating the AXI Full Write Data Channel optional ports
gwdch1: IF (C_WDCH_TYPE < 2) GENERATE
gwdch_din1: IF (C_HAS_AXI_WUSER = 1) GENERATE
wdch_din(WSTRB_OFFSET-1 DOWNTO WUSER_OFFSET) <= S_AXI_WUSER;
M_AXI_WUSER <= wdch_dout(WSTRB_OFFSET-1 DOWNTO WUSER_OFFSET);
END GENERATE gwdch_din1;
gwdch_din2: IF (C_HAS_AXI_WUSER = 0) GENERATE
M_AXI_WUSER <= (OTHERS => '0');
END GENERATE gwdch_din2;
gwdch_din3: IF (C_HAS_AXI_ID = 1 AND C_AXI_TYPE = 3) GENERATE
wdch_din(C_DIN_WIDTH_WDCH-1 DOWNTO WID_OFFSET) <= S_AXI_WID;
M_AXI_WID <= wdch_dout(C_DIN_WIDTH_WDCH-1 DOWNTO WID_OFFSET);
END GENERATE gwdch_din3;
gwdch_din4: IF NOT (C_HAS_AXI_ID = 1 AND C_AXI_TYPE = 3) GENERATE
M_AXI_WID <= (OTHERS => '0');
END GENERATE gwdch_din4;
wdch_din(WID_OFFSET-1 DOWNTO WDATA_OFFSET) <= S_AXI_WDATA;
wdch_din(WDATA_OFFSET-1 DOWNTO WSTRB_OFFSET) <= S_AXI_WSTRB;
wdch_din(0) <= S_AXI_WLAST;
M_AXI_WDATA <= wdch_dout(WID_OFFSET-1 DOWNTO WDATA_OFFSET);
M_AXI_WSTRB <= wdch_dout(WDATA_OFFSET-1 DOWNTO WSTRB_OFFSET);
M_AXI_WLAST <= wdch_dout(0);
END GENERATE gwdch1;
-- Generate the DIN to FIFO by concatinating the AXI Full Write Response Channel optional ports
gwrch1: IF (C_WRCH_TYPE < 2) GENERATE
gwrch_din1: IF (C_HAS_AXI_BUSER = 1) GENERATE
wrch_din(BRESP_OFFSET-1 DOWNTO BUSER_OFFSET) <= M_AXI_BUSER;
S_AXI_BUSER <= wrch_dout(BRESP_OFFSET-1 DOWNTO BUSER_OFFSET);
END GENERATE gwrch_din1;
gwrch_din2: IF (C_HAS_AXI_BUSER = 0) GENERATE
S_AXI_BUSER <= (OTHERS => '0');
END GENERATE gwrch_din2;
gwrch_din3: IF (C_HAS_AXI_ID = 1) GENERATE
wrch_din(C_DIN_WIDTH_WRCH-1 DOWNTO BID_OFFSET) <= M_AXI_BID;
S_AXI_BID <= wrch_dout(C_DIN_WIDTH_WRCH-1 DOWNTO BID_OFFSET);
END GENERATE gwrch_din3;
gwrch_din4: IF (C_HAS_AXI_ID = 0) GENERATE
S_AXI_BID <= (OTHERS => '0');
END GENERATE gwrch_din4;
wrch_din(BID_OFFSET-1 DOWNTO BRESP_OFFSET) <= M_AXI_BRESP;
S_AXI_BRESP <= wrch_dout(BID_OFFSET-1 DOWNTO BRESP_OFFSET);
END GENERATE gwrch1;
END GENERATE axi_full_din_wr_ch;
-- Form the DIN to FIFO by concatinating the AXI Lite Write Address Channel optional ports
axi_lite_din_wr_ch: IF (C_AXI_TYPE = 2) GENERATE
gwach1: IF (C_WACH_TYPE < 2) GENERATE
wach_din <= S_AXI_AWADDR & S_AXI_AWPROT;
M_AXI_AWADDR <= wach_dout(C_DIN_WIDTH_WACH-1 DOWNTO AWADDR_OFFSET);
M_AXI_AWPROT <= wach_dout(AWADDR_OFFSET-1 DOWNTO AWPROT_OFFSET);
END GENERATE gwach1;
gwdch1: IF (C_WDCH_TYPE < 2) GENERATE
wdch_din <= S_AXI_WDATA & S_AXI_WSTRB;
M_AXI_WDATA <= wdch_dout(C_DIN_WIDTH_WDCH-1 DOWNTO WDATA_OFFSET);
M_AXI_WSTRB <= wdch_dout(WDATA_OFFSET-1 DOWNTO WSTRB_OFFSET);
END GENERATE gwdch1;
gwrch1: IF (C_WRCH_TYPE < 2) GENERATE
wrch_din <= M_AXI_BRESP;
S_AXI_BRESP <= wrch_dout(C_DIN_WIDTH_WRCH-1 DOWNTO BRESP_OFFSET);
END GENERATE gwrch1;
END GENERATE axi_lite_din_wr_ch;
-- Write protection for Write Address Channel
-- When FULL is high, pass VALID as a WR_EN to the FIFO to get OVERFLOW interrupt
gwach_wr_en1: IF (C_PROG_FULL_TYPE_WACH = 0) GENERATE
wach_wr_en <= S_AXI_AWVALID;
END GENERATE gwach_wr_en1;
-- When ALMOST_FULL or PROG_FULL is high, then shield the FIFO from becoming FULL
gwach_wr_en2: IF (C_PROG_FULL_TYPE_WACH /= 0) GENERATE
wach_wr_en <= wach_s_axi_awready AND S_AXI_AWVALID;
END GENERATE gwach_wr_en2;
-- Write protection for Write Data Channel
-- When FULL is high, pass VALID as a WR_EN to the FIFO to get OVERFLOW interrupt
gwdch_wr_en1: IF (C_PROG_FULL_TYPE_WDCH = 0) GENERATE
wdch_wr_en <= S_AXI_WVALID;
END GENERATE gwdch_wr_en1;
-- When ALMOST_FULL or PROG_FULL is high, then shield the FIFO from becoming FULL
gwdch_wr_en2: IF (C_PROG_FULL_TYPE_WDCH /= 0) GENERATE
wdch_wr_en <= wdch_s_axi_wready AND S_AXI_WVALID;
END GENERATE gwdch_wr_en2;
-- Write protection for Write Response Channel
-- When FULL is high, pass VALID as a WR_EN to the FIFO to get OVERFLOW interrupt
gwrch_wr_en1: IF (C_PROG_FULL_TYPE_WRCH = 0) GENERATE
wrch_wr_en <= M_AXI_BVALID;
END GENERATE gwrch_wr_en1;
-- When ALMOST_FULL or PROG_FULL is high, then shield the FIFO from becoming FULL
gwrch_wr_en2: IF (C_PROG_FULL_TYPE_WRCH /= 0) GENERATE
wrch_wr_en <= wrch_m_axi_bready AND M_AXI_BVALID;
END GENERATE gwrch_wr_en2;
-- Read protection for Write Address Channel
-- When EMPTY is low, pass READY as a RD_EN to the FIFO to get UNDERFLOW interrupt
gwach_rd_en1: IF (C_PROG_EMPTY_TYPE_WACH = 0) GENERATE
gpkt_mm_wach_rd_en1: IF (C_APPLICATION_TYPE_WACH = 1) GENERATE
wach_rd_en <= awready_pkt AND awvalid_en;
END GENERATE;
gnpkt_mm_wach_rd_en1: IF (C_APPLICATION_TYPE_WACH /= 1) GENERATE
wach_rd_en <= M_AXI_AWREADY;
END GENERATE;
END GENERATE gwach_rd_en1;
-- When ALMOST_EMPTY or PROG_EMPTY is low, then shield the FIFO from becoming EMPTY
gwach_rd_en2: IF (C_PROG_EMPTY_TYPE_WACH /= 0) GENERATE
gaxi_mm_wach_rd_en2: IF (C_APPLICATION_TYPE_WACH = 1) GENERATE
wach_rd_en <= wach_m_axi_awvalid AND awready_pkt AND awvalid_en;
END GENERATE gaxi_mm_wach_rd_en2;
gnaxi_mm_wach_rd_en2: IF (C_APPLICATION_TYPE_WACH /= 1) GENERATE
wach_rd_en <= wach_m_axi_awvalid AND M_AXI_AWREADY;
END GENERATE gnaxi_mm_wach_rd_en2;
END GENERATE gwach_rd_en2;
-- Read protection for Write Data Channel
-- When EMPTY is low, pass READY as a RD_EN to the FIFO to get UNDERFLOW interrupt
gwdch_rd_en1: IF (C_PROG_EMPTY_TYPE_WDCH = 0) GENERATE
wdch_rd_en <= M_AXI_WREADY;
END GENERATE gwdch_rd_en1;
-- When ALMOST_EMPTY or PROG_EMPTY is low, then shield the FIFO from becoming EMPTY
gwdch_rd_en2: IF (C_PROG_EMPTY_TYPE_WDCH /= 0) GENERATE
wdch_rd_en <= wdch_m_axi_wvalid AND M_AXI_WREADY;
END GENERATE gwdch_rd_en2;
-- Read protection for Write Response Channel
-- When EMPTY is low, pass READY as a RD_EN to the FIFO to get UNDERFLOW interrupt
gwrch_rd_en1: IF (C_PROG_EMPTY_TYPE_WRCH = 0) GENERATE
wrch_rd_en <= S_AXI_BREADY;
END GENERATE gwrch_rd_en1;
-- When ALMOST_EMPTY or PROG_EMPTY is low, then shield the FIFO from becoming EMPTY
gwrch_rd_en2: IF (C_PROG_EMPTY_TYPE_WRCH /= 0) GENERATE
wrch_rd_en <= wrch_s_axi_bvalid AND S_AXI_BREADY;
END GENERATE gwrch_rd_en2;
gwach2: IF (C_WACH_TYPE = 0) GENERATE
SIGNAL wach_we : STD_LOGIC := '0';
SIGNAL wach_re : STD_LOGIC := '0';
BEGIN
wach_we <= wach_wr_en WHEN (C_HAS_SLAVE_CE = 0) ELSE wach_wr_en AND S_ACLK_EN;
wach_re <= wach_rd_en WHEN (C_HAS_MASTER_CE = 0) ELSE wach_rd_en AND M_ACLK_EN;
axi_wach : fifo_generator_v13_0_1_conv
GENERIC MAP (
C_FAMILY => C_FAMILY,
C_COMMON_CLOCK => C_COMMON_CLOCK,
C_INTERFACE_TYPE => C_INTERFACE_TYPE,
C_MEMORY_TYPE => if_then_else((C_IMPLEMENTATION_TYPE_WACH = 1 OR C_IMPLEMENTATION_TYPE_WACH = 11),1,
if_then_else((C_IMPLEMENTATION_TYPE_WACH = 2 OR C_IMPLEMENTATION_TYPE_WACH = 12),2,4)),
C_IMPLEMENTATION_TYPE => if_then_else((C_IMPLEMENTATION_TYPE_WACH = 1 OR C_IMPLEMENTATION_TYPE_WACH = 2),0,
if_then_else((C_IMPLEMENTATION_TYPE_WACH = 11 OR C_IMPLEMENTATION_TYPE_WACH = 12),2,6)),
C_PRELOAD_REGS => 1, -- Always FWFT for AXI
C_PRELOAD_LATENCY => 0, -- Always FWFT for AXI
C_DIN_WIDTH => C_DIN_WIDTH_WACH,
C_WR_DEPTH => C_WR_DEPTH_WACH,
C_WR_PNTR_WIDTH => C_WR_PNTR_WIDTH_WACH,
C_DOUT_WIDTH => C_DIN_WIDTH_WACH,
C_RD_DEPTH => C_WR_DEPTH_WACH,
C_RD_PNTR_WIDTH => C_WR_PNTR_WIDTH_WACH,
C_PROG_FULL_TYPE => C_PROG_FULL_TYPE_WACH,
C_PROG_FULL_THRESH_ASSERT_VAL => C_PROG_FULL_THRESH_ASSERT_VAL_WACH,
C_PROG_EMPTY_TYPE => C_PROG_EMPTY_TYPE_WACH,
C_PROG_EMPTY_THRESH_ASSERT_VAL => C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH,
C_USE_ECC => C_USE_ECC_WACH,
C_ERROR_INJECTION_TYPE => C_ERROR_INJECTION_TYPE_WACH,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
-- Enable Low Latency Sync FIFO for Common Clock Built-in FIFO
C_FIFO_TYPE => if_then_else((C_APPLICATION_TYPE_WACH = 1),0,C_APPLICATION_TYPE_WACH),
C_SYNCHRONIZER_STAGE => C_SYNCHRONIZER_STAGE,
C_AXI_TYPE => if_then_else(C_INTERFACE_TYPE = 1, 0, C_AXI_TYPE),
C_HAS_WR_RST => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_DOUT_RST_VAL => "0",
C_HAS_VALID => C_HAS_VALID,
C_VALID_LOW => C_VALID_LOW,
C_HAS_UNDERFLOW => C_HAS_UNDERFLOW,
C_UNDERFLOW_LOW => C_UNDERFLOW_LOW,
C_HAS_WR_ACK => C_HAS_WR_ACK,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_HAS_OVERFLOW => C_HAS_OVERFLOW,
C_OVERFLOW_LOW => C_OVERFLOW_LOW,
C_HAS_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 1 AND C_HAS_DATA_COUNTS_WACH = 1), 1, 0),
C_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_WACH+1,
C_HAS_RD_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 0 AND C_HAS_DATA_COUNTS_WACH = 1), 1, 0),
C_RD_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_WACH+1,
C_USE_FWFT_DATA_COUNT => 1, -- use extra logic is always true
C_HAS_WR_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 0 AND C_HAS_DATA_COUNTS_WACH = 1), 1, 0),
C_WR_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_WACH+1,
C_FULL_FLAGS_RST_VAL => 1,
C_USE_EMBEDDED_REG => 0,
C_USE_DOUT_RST => 0,
C_MSGON_VAL => C_MSGON_VAL,
C_ENABLE_RST_SYNC => 1,
C_EN_SAFETY_CKT => 1,
C_COUNT_TYPE => C_COUNT_TYPE,
C_DEFAULT_VALUE => C_DEFAULT_VALUE,
C_ENABLE_RLOCS => C_ENABLE_RLOCS,
C_HAS_BACKUP => C_HAS_BACKUP,
C_HAS_INT_CLK => C_HAS_INT_CLK,
C_HAS_MEMINIT_FILE => C_HAS_MEMINIT_FILE,
C_INIT_WR_PNTR_VAL => C_INIT_WR_PNTR_VAL,
C_MIF_FILE_NAME => C_MIF_FILE_NAME,
C_OPTIMIZATION_MODE => C_OPTIMIZATION_MODE,
C_RD_FREQ => C_RD_FREQ,
C_USE_FIFO16_FLAGS => C_USE_FIFO16_FLAGS,
C_WR_FREQ => C_WR_FREQ,
C_WR_RESPONSE_LATENCY => C_WR_RESPONSE_LATENCY
)
PORT MAP(
--Inputs
BACKUP => BACKUP,
BACKUP_MARKER => BACKUP_MARKER,
INT_CLK => INT_CLK,
CLK => S_ACLK,
WR_CLK => S_ACLK,
RD_CLK => M_ACLK,
RST => inverted_reset,
SRST => '0',
WR_RST => inverted_reset,
RD_RST => inverted_reset,
WR_EN => wach_we,
RD_EN => wach_re,
PROG_FULL_THRESH => AXI_AW_PROG_FULL_THRESH,
PROG_FULL_THRESH_ASSERT => (OTHERS => '0'),
PROG_FULL_THRESH_NEGATE => (OTHERS => '0'),
PROG_EMPTY_THRESH => AXI_AW_PROG_EMPTY_THRESH,
PROG_EMPTY_THRESH_ASSERT => (OTHERS => '0'),
PROG_EMPTY_THRESH_NEGATE => (OTHERS => '0'),
INJECTDBITERR => AXI_AW_INJECTDBITERR,
INJECTSBITERR => AXI_AW_INJECTSBITERR,
DIN => wach_din,
DOUT => wach_dout_pkt,
FULL => wach_full,
EMPTY => wach_empty,
ALMOST_FULL => OPEN,
PROG_FULL => AXI_AW_PROG_FULL,
ALMOST_EMPTY => OPEN,
PROG_EMPTY => AXI_AW_PROG_EMPTY,
WR_ACK => OPEN,
OVERFLOW => axi_aw_overflow_i,
VALID => OPEN,
UNDERFLOW => axi_aw_underflow_i,
DATA_COUNT => AXI_AW_DATA_COUNT,
RD_DATA_COUNT => AXI_AW_RD_DATA_COUNT,
WR_DATA_COUNT => AXI_AW_WR_DATA_COUNT,
SBITERR => AXI_AW_SBITERR,
DBITERR => AXI_AW_DBITERR,
WR_RST_BUSY => wr_rst_busy_wach,
RD_RST_BUSY => rd_rst_busy_wach,
WR_RST_I_OUT => OPEN,
RD_RST_I_OUT => OPEN
);
g8s_wach_rdy: IF (IS_8SERIES = 1) GENERATE
g8s_bi_wach_rdy: IF (C_IMPLEMENTATION_TYPE_WACH = 5 OR C_IMPLEMENTATION_TYPE_WACH = 13) GENERATE
wach_s_axi_awready <= NOT (wach_full OR wr_rst_busy_wach);
END GENERATE g8s_bi_wach_rdy;
g8s_nbi_wach_rdy: IF (NOT (C_IMPLEMENTATION_TYPE_WACH = 5 OR C_IMPLEMENTATION_TYPE_WACH = 13)) GENERATE
wach_s_axi_awready <= NOT (wach_full);
END GENERATE g8s_nbi_wach_rdy;
END GENERATE g8s_wach_rdy;
g7s_wach_rdy: IF (IS_8SERIES = 0) GENERATE
wach_s_axi_awready <= NOT (wach_full);
END GENERATE g7s_wach_rdy;
wach_m_axi_awvalid <= NOT wach_empty;
S_AXI_AWREADY <= wach_s_axi_awready;
gawvld_pkt_fifo: IF (C_APPLICATION_TYPE_WACH = 1) GENERATE
SIGNAL awvalid_pkt : STD_LOGIC := '0';
BEGIN
awvalid_pkt <= wach_m_axi_awvalid AND awvalid_en;
wach_pkt_reg_slice: fifo_generator_v13_0_1_axic_reg_slice
GENERIC MAP (
C_FAMILY => C_FAMILY,
C_DATA_WIDTH => C_DIN_WIDTH_WACH,
C_REG_CONFIG => 1
)
PORT MAP(
-- System Signals
ACLK => S_ACLK,
ARESET => inverted_reset,
-- Slave side
S_PAYLOAD_DATA => wach_dout_pkt,
S_VALID => awvalid_pkt,
S_READY => awready_pkt,
-- Master side
M_PAYLOAD_DATA => wach_dout,
M_VALID => M_AXI_AWVALID,
M_READY => M_AXI_AWREADY
);
END GENERATE gawvld_pkt_fifo;
gnawvld_pkt_fifo: IF (C_APPLICATION_TYPE_WACH /= 1) GENERATE
M_AXI_AWVALID <= wach_m_axi_awvalid;
wach_dout <= wach_dout_pkt;
END GENERATE gnawvld_pkt_fifo;
gaxi_wr_ch_uf1: IF (C_USE_COMMON_UNDERFLOW = 0) GENERATE
AXI_AW_UNDERFLOW <= axi_aw_underflow_i;
END GENERATE gaxi_wr_ch_uf1;
gaxi_wr_ch_of1: IF (C_USE_COMMON_OVERFLOW = 0) GENERATE
AXI_AW_OVERFLOW <= axi_aw_overflow_i;
END GENERATE gaxi_wr_ch_of1;
END GENERATE gwach2;
-- Register Slice for Write Address Channel
gwach_reg_slice: IF (C_WACH_TYPE = 1) GENERATE
wach_reg_slice: fifo_generator_v13_0_1_axic_reg_slice
GENERIC MAP (
C_FAMILY => C_FAMILY,
C_DATA_WIDTH => C_DIN_WIDTH_WACH,
C_REG_CONFIG => C_REG_SLICE_MODE_WACH
)
PORT MAP(
-- System Signals
ACLK => S_ACLK,
ARESET => axi_rs_rst,
-- Slave side
S_PAYLOAD_DATA => wach_din,
S_VALID => S_AXI_AWVALID,
S_READY => S_AXI_AWREADY,
-- Master side
M_PAYLOAD_DATA => wach_dout,
M_VALID => M_AXI_AWVALID,
M_READY => M_AXI_AWREADY
);
END GENERATE gwach_reg_slice;
gwdch2: IF (C_WDCH_TYPE = 0) GENERATE
SIGNAL wdch_re : STD_LOGIC := '0';
BEGIN
wdch_we <= wdch_wr_en WHEN (C_HAS_SLAVE_CE = 0) ELSE wdch_wr_en AND S_ACLK_EN;
wdch_re <= wdch_rd_en WHEN (C_HAS_MASTER_CE = 0) ELSE wdch_rd_en AND M_ACLK_EN;
axi_wdch : fifo_generator_v13_0_1_conv
GENERIC MAP (
C_FAMILY => C_FAMILY,
C_COMMON_CLOCK => C_COMMON_CLOCK,
C_INTERFACE_TYPE => C_INTERFACE_TYPE,
C_MEMORY_TYPE => if_then_else((C_IMPLEMENTATION_TYPE_WDCH = 1 OR C_IMPLEMENTATION_TYPE_WDCH = 11),1,
if_then_else((C_IMPLEMENTATION_TYPE_WDCH = 2 OR C_IMPLEMENTATION_TYPE_WDCH = 12),2,4)),
C_IMPLEMENTATION_TYPE => if_then_else((C_IMPLEMENTATION_TYPE_WDCH = 1 OR C_IMPLEMENTATION_TYPE_WDCH = 2),0,
if_then_else((C_IMPLEMENTATION_TYPE_WDCH = 11 OR C_IMPLEMENTATION_TYPE_WDCH = 12),2,6)),
C_PRELOAD_REGS => 1, -- Always FWFT for AXI
C_PRELOAD_LATENCY => 0, -- Always FWFT for AXI
C_DIN_WIDTH => C_DIN_WIDTH_WDCH,
C_WR_DEPTH => C_WR_DEPTH_WDCH,
C_WR_PNTR_WIDTH => C_WR_PNTR_WIDTH_WDCH,
C_DOUT_WIDTH => C_DIN_WIDTH_WDCH,
C_RD_DEPTH => C_WR_DEPTH_WDCH,
C_RD_PNTR_WIDTH => C_WR_PNTR_WIDTH_WDCH,
C_PROG_FULL_TYPE => C_PROG_FULL_TYPE_WDCH,
C_PROG_FULL_THRESH_ASSERT_VAL => C_PROG_FULL_THRESH_ASSERT_VAL_WDCH,
C_PROG_EMPTY_TYPE => C_PROG_EMPTY_TYPE_WDCH,
C_PROG_EMPTY_THRESH_ASSERT_VAL => C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH,
C_USE_ECC => C_USE_ECC_WDCH,
C_ERROR_INJECTION_TYPE => C_ERROR_INJECTION_TYPE_WDCH,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
-- Enable Low Latency Sync FIFO for Common Clock Built-in FIFO
C_FIFO_TYPE => C_APPLICATION_TYPE_WDCH,
C_SYNCHRONIZER_STAGE => C_SYNCHRONIZER_STAGE,
C_AXI_TYPE => if_then_else(C_INTERFACE_TYPE = 1, 0, C_AXI_TYPE),
C_HAS_WR_RST => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_DOUT_RST_VAL => "0",
C_HAS_VALID => C_HAS_VALID,
C_VALID_LOW => C_VALID_LOW,
C_HAS_UNDERFLOW => C_HAS_UNDERFLOW,
C_UNDERFLOW_LOW => C_UNDERFLOW_LOW,
C_HAS_WR_ACK => C_HAS_WR_ACK,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_HAS_OVERFLOW => C_HAS_OVERFLOW,
C_OVERFLOW_LOW => C_OVERFLOW_LOW,
C_HAS_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 1 AND C_HAS_DATA_COUNTS_WDCH = 1), 1, 0),
C_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_WDCH+1,
C_HAS_RD_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 0 AND C_HAS_DATA_COUNTS_WDCH = 1), 1, 0),
C_RD_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_WDCH+1,
C_USE_FWFT_DATA_COUNT => 1, -- use extra logic is always true
C_HAS_WR_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 0 AND C_HAS_DATA_COUNTS_WDCH = 1), 1, 0),
C_WR_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_WDCH+1,
C_FULL_FLAGS_RST_VAL => 1,
C_USE_EMBEDDED_REG => 0,
C_USE_DOUT_RST => 0,
C_MSGON_VAL => C_MSGON_VAL,
C_ENABLE_RST_SYNC => 1,
C_EN_SAFETY_CKT => 1,
C_COUNT_TYPE => C_COUNT_TYPE,
C_DEFAULT_VALUE => C_DEFAULT_VALUE,
C_ENABLE_RLOCS => C_ENABLE_RLOCS,
C_HAS_BACKUP => C_HAS_BACKUP,
C_HAS_INT_CLK => C_HAS_INT_CLK,
C_HAS_MEMINIT_FILE => C_HAS_MEMINIT_FILE,
C_INIT_WR_PNTR_VAL => C_INIT_WR_PNTR_VAL,
C_MIF_FILE_NAME => C_MIF_FILE_NAME,
C_OPTIMIZATION_MODE => C_OPTIMIZATION_MODE,
C_RD_FREQ => C_RD_FREQ,
C_USE_FIFO16_FLAGS => C_USE_FIFO16_FLAGS,
C_WR_FREQ => C_WR_FREQ,
C_WR_RESPONSE_LATENCY => C_WR_RESPONSE_LATENCY
)
PORT MAP(
--Inputs
BACKUP => BACKUP,
BACKUP_MARKER => BACKUP_MARKER,
INT_CLK => INT_CLK,
CLK => S_ACLK,
WR_CLK => S_ACLK,
RD_CLK => M_ACLK,
RST => inverted_reset,
SRST => '0',
WR_RST => inverted_reset,
RD_RST => inverted_reset,
WR_EN => wdch_we,
RD_EN => wdch_re,
PROG_FULL_THRESH => AXI_W_PROG_FULL_THRESH,
PROG_FULL_THRESH_ASSERT => (OTHERS => '0'),
PROG_FULL_THRESH_NEGATE => (OTHERS => '0'),
PROG_EMPTY_THRESH => AXI_W_PROG_EMPTY_THRESH,
PROG_EMPTY_THRESH_ASSERT => (OTHERS => '0'),
PROG_EMPTY_THRESH_NEGATE => (OTHERS => '0'),
INJECTDBITERR => AXI_W_INJECTDBITERR,
INJECTSBITERR => AXI_W_INJECTSBITERR,
DIN => wdch_din,
DOUT => wdch_dout,
FULL => wdch_full,
EMPTY => wdch_empty,
ALMOST_FULL => OPEN,
PROG_FULL => AXI_W_PROG_FULL,
ALMOST_EMPTY => OPEN,
PROG_EMPTY => AXI_W_PROG_EMPTY,
WR_ACK => OPEN,
OVERFLOW => axi_w_overflow_i,
VALID => OPEN,
UNDERFLOW => axi_w_underflow_i,
DATA_COUNT => AXI_W_DATA_COUNT,
RD_DATA_COUNT => AXI_W_RD_DATA_COUNT,
WR_DATA_COUNT => AXI_W_WR_DATA_COUNT,
SBITERR => AXI_W_SBITERR,
DBITERR => AXI_W_DBITERR,
WR_RST_BUSY => wr_rst_busy_wdch,
RD_RST_BUSY => rd_rst_busy_wdch,
WR_RST_I_OUT => OPEN,
RD_RST_I_OUT => OPEN
);
g8s_wdch_rdy: IF (IS_8SERIES = 1) GENERATE
g8s_bi_wdch_rdy: IF (C_IMPLEMENTATION_TYPE_WDCH = 5 OR C_IMPLEMENTATION_TYPE_WDCH = 13) GENERATE
wdch_s_axi_wready <= NOT (wdch_full OR wr_rst_busy_wdch);
END GENERATE g8s_bi_wdch_rdy;
g8s_nbi_wdch_rdy: IF (NOT (C_IMPLEMENTATION_TYPE_WDCH = 5 OR C_IMPLEMENTATION_TYPE_WDCH = 13)) GENERATE
wdch_s_axi_wready <= NOT (wdch_full);
END GENERATE g8s_nbi_wdch_rdy;
END GENERATE g8s_wdch_rdy;
g7s_wdch_rdy: IF (IS_8SERIES = 0) GENERATE
wdch_s_axi_wready <= NOT (wdch_full);
END GENERATE g7s_wdch_rdy;
wdch_m_axi_wvalid <= NOT wdch_empty;
S_AXI_WREADY <= wdch_s_axi_wready;
M_AXI_WVALID <= wdch_m_axi_wvalid;
gaxi_wr_ch_uf2: IF (C_USE_COMMON_UNDERFLOW = 0) GENERATE
AXI_W_UNDERFLOW <= axi_w_underflow_i;
END GENERATE gaxi_wr_ch_uf2;
gaxi_wr_ch_of2: IF (C_USE_COMMON_OVERFLOW = 0) GENERATE
AXI_W_OVERFLOW <= axi_w_overflow_i;
END GENERATE gaxi_wr_ch_of2;
END GENERATE gwdch2;
-- Register Slice for Write Data Channel
gwdch_reg_slice: IF (C_WDCH_TYPE = 1) GENERATE
wdch_reg_slice: fifo_generator_v13_0_1_axic_reg_slice
GENERIC MAP (
C_FAMILY => C_FAMILY,
C_DATA_WIDTH => C_DIN_WIDTH_WDCH,
C_REG_CONFIG => C_REG_SLICE_MODE_WDCH
)
PORT MAP(
-- System Signals
ACLK => S_ACLK,
ARESET => axi_rs_rst,
-- Slave side
S_PAYLOAD_DATA => wdch_din,
S_VALID => S_AXI_WVALID,
S_READY => S_AXI_WREADY,
-- Master side
M_PAYLOAD_DATA => wdch_dout,
M_VALID => M_AXI_WVALID,
M_READY => M_AXI_WREADY
);
END GENERATE gwdch_reg_slice;
gwrch2: IF (C_WRCH_TYPE = 0) GENERATE
SIGNAL wrch_we : STD_LOGIC := '0';
SIGNAL wrch_re : STD_LOGIC := '0';
BEGIN
wrch_we <= wrch_wr_en WHEN (C_HAS_MASTER_CE = 0) ELSE wrch_wr_en AND M_ACLK_EN;
wrch_re <= wrch_rd_en WHEN (C_HAS_SLAVE_CE = 0) ELSE wrch_rd_en AND S_ACLK_EN;
axi_wrch : fifo_generator_v13_0_1_conv -- Write Response Channel
GENERIC MAP (
C_FAMILY => C_FAMILY,
C_COMMON_CLOCK => C_COMMON_CLOCK,
C_INTERFACE_TYPE => C_INTERFACE_TYPE,
C_MEMORY_TYPE => if_then_else((C_IMPLEMENTATION_TYPE_WRCH = 1 OR C_IMPLEMENTATION_TYPE_WRCH = 11),1,
if_then_else((C_IMPLEMENTATION_TYPE_WRCH = 2 OR C_IMPLEMENTATION_TYPE_WRCH = 12),2,4)),
C_IMPLEMENTATION_TYPE => if_then_else((C_IMPLEMENTATION_TYPE_WRCH = 1 OR C_IMPLEMENTATION_TYPE_WRCH = 2),0,
if_then_else((C_IMPLEMENTATION_TYPE_WRCH = 11 OR C_IMPLEMENTATION_TYPE_WRCH = 12),2,6)),
C_PRELOAD_REGS => 1, -- Always FWFT for AXI
C_PRELOAD_LATENCY => 0, -- Always FWFT for AXI
C_DIN_WIDTH => C_DIN_WIDTH_WRCH,
C_WR_DEPTH => C_WR_DEPTH_WRCH,
C_WR_PNTR_WIDTH => C_WR_PNTR_WIDTH_WRCH,
C_DOUT_WIDTH => C_DIN_WIDTH_WRCH,
C_RD_DEPTH => C_WR_DEPTH_WRCH,
C_RD_PNTR_WIDTH => C_WR_PNTR_WIDTH_WRCH,
C_PROG_FULL_TYPE => C_PROG_FULL_TYPE_WRCH,
C_PROG_FULL_THRESH_ASSERT_VAL => C_PROG_FULL_THRESH_ASSERT_VAL_WRCH,
C_PROG_EMPTY_TYPE => C_PROG_EMPTY_TYPE_WRCH,
C_PROG_EMPTY_THRESH_ASSERT_VAL => C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH,
C_USE_ECC => C_USE_ECC_WRCH,
C_ERROR_INJECTION_TYPE => C_ERROR_INJECTION_TYPE_WRCH,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
-- Enable Low Latency Sync FIFO for Common Clock Built-in FIFO
C_FIFO_TYPE => C_APPLICATION_TYPE_WRCH,
C_SYNCHRONIZER_STAGE => C_SYNCHRONIZER_STAGE,
C_AXI_TYPE => if_then_else(C_INTERFACE_TYPE = 1, 0, C_AXI_TYPE),
C_HAS_WR_RST => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_DOUT_RST_VAL => "0",
C_HAS_VALID => C_HAS_VALID,
C_VALID_LOW => C_VALID_LOW,
C_HAS_UNDERFLOW => C_HAS_UNDERFLOW,
C_UNDERFLOW_LOW => C_UNDERFLOW_LOW,
C_HAS_WR_ACK => C_HAS_WR_ACK,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_HAS_OVERFLOW => C_HAS_OVERFLOW,
C_OVERFLOW_LOW => C_OVERFLOW_LOW,
C_HAS_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 1 AND C_HAS_DATA_COUNTS_WRCH = 1), 1, 0),
C_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_WRCH+1,
C_HAS_RD_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 0 AND C_HAS_DATA_COUNTS_WRCH = 1), 1, 0),
C_RD_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_WRCH+1,
C_USE_FWFT_DATA_COUNT => 1, -- use extra logic is always true
C_HAS_WR_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 0 AND C_HAS_DATA_COUNTS_WRCH = 1), 1, 0),
C_WR_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_WRCH+1,
C_FULL_FLAGS_RST_VAL => 1,
C_USE_EMBEDDED_REG => 0,
C_USE_DOUT_RST => 0,
C_MSGON_VAL => C_MSGON_VAL,
C_ENABLE_RST_SYNC => 1,
C_EN_SAFETY_CKT => 1,
C_COUNT_TYPE => C_COUNT_TYPE,
C_DEFAULT_VALUE => C_DEFAULT_VALUE,
C_ENABLE_RLOCS => C_ENABLE_RLOCS,
C_HAS_BACKUP => C_HAS_BACKUP,
C_HAS_INT_CLK => C_HAS_INT_CLK,
C_HAS_MEMINIT_FILE => C_HAS_MEMINIT_FILE,
C_INIT_WR_PNTR_VAL => C_INIT_WR_PNTR_VAL,
C_MIF_FILE_NAME => C_MIF_FILE_NAME,
C_OPTIMIZATION_MODE => C_OPTIMIZATION_MODE,
C_RD_FREQ => C_RD_FREQ,
C_USE_FIFO16_FLAGS => C_USE_FIFO16_FLAGS,
C_WR_FREQ => C_WR_FREQ,
C_WR_RESPONSE_LATENCY => C_WR_RESPONSE_LATENCY
)
PORT MAP(
--Inputs
BACKUP => BACKUP,
BACKUP_MARKER => BACKUP_MARKER,
INT_CLK => INT_CLK,
CLK => S_ACLK,
WR_CLK => M_ACLK,
RD_CLK => S_ACLK,
RST => inverted_reset,
SRST => '0',
WR_RST => inverted_reset,
RD_RST => inverted_reset,
WR_EN => wrch_we,
RD_EN => wrch_re,
PROG_FULL_THRESH => AXI_B_PROG_FULL_THRESH,
PROG_FULL_THRESH_ASSERT => (OTHERS => '0'),
PROG_FULL_THRESH_NEGATE => (OTHERS => '0'),
PROG_EMPTY_THRESH => AXI_B_PROG_EMPTY_THRESH,
PROG_EMPTY_THRESH_ASSERT => (OTHERS => '0'),
PROG_EMPTY_THRESH_NEGATE => (OTHERS => '0'),
INJECTDBITERR => AXI_B_INJECTDBITERR,
INJECTSBITERR => AXI_B_INJECTSBITERR,
DIN => wrch_din,
DOUT => wrch_dout,
FULL => wrch_full,
EMPTY => wrch_empty,
ALMOST_FULL => OPEN,
PROG_FULL => AXI_B_PROG_FULL,
ALMOST_EMPTY => OPEN,
PROG_EMPTY => AXI_B_PROG_EMPTY,
WR_ACK => OPEN,
OVERFLOW => axi_b_overflow_i,
VALID => OPEN,
UNDERFLOW => axi_b_underflow_i,
DATA_COUNT => AXI_B_DATA_COUNT,
RD_DATA_COUNT => AXI_B_RD_DATA_COUNT,
WR_DATA_COUNT => AXI_B_WR_DATA_COUNT,
SBITERR => AXI_B_SBITERR,
DBITERR => AXI_B_DBITERR,
WR_RST_BUSY => wr_rst_busy_wrch,
RD_RST_BUSY => rd_rst_busy_wrch,
WR_RST_I_OUT => OPEN,
RD_RST_I_OUT => OPEN
);
wrch_s_axi_bvalid <= NOT wrch_empty;
g8s_wrch_rdy: IF (IS_8SERIES = 1) GENERATE
g8s_bi_wrch_rdy: IF (C_IMPLEMENTATION_TYPE_WRCH = 5 OR C_IMPLEMENTATION_TYPE_WRCH = 13) GENERATE
wrch_m_axi_bready <= NOT (wrch_full OR wr_rst_busy_wrch);
END GENERATE g8s_bi_wrch_rdy;
g8s_nbi_wrch_rdy: IF (NOT (C_IMPLEMENTATION_TYPE_WRCH = 5 OR C_IMPLEMENTATION_TYPE_WRCH = 13)) GENERATE
wrch_m_axi_bready <= NOT (wrch_full);
END GENERATE g8s_nbi_wrch_rdy;
END GENERATE g8s_wrch_rdy;
g7s_wrch_rdy: IF (IS_8SERIES = 0) GENERATE
wrch_m_axi_bready <= NOT (wrch_full);
END GENERATE g7s_wrch_rdy;
S_AXI_BVALID <= wrch_s_axi_bvalid;
M_AXI_BREADY <= wrch_m_axi_bready;
gaxi_wr_ch_uf3: IF (C_USE_COMMON_UNDERFLOW = 0) GENERATE
AXI_B_UNDERFLOW <= axi_b_underflow_i;
END GENERATE gaxi_wr_ch_uf3;
gaxi_wr_ch_of3: IF (C_USE_COMMON_OVERFLOW = 0) GENERATE
AXI_B_OVERFLOW <= axi_b_overflow_i;
END GENERATE gaxi_wr_ch_of3;
END GENERATE gwrch2;
-- Register Slice for Write Response Channel
gwrch_reg_slice: IF (C_WRCH_TYPE = 1) GENERATE
wrch_reg_slice: fifo_generator_v13_0_1_axic_reg_slice
GENERIC MAP (
C_FAMILY => C_FAMILY,
C_DATA_WIDTH => C_DIN_WIDTH_WRCH,
C_REG_CONFIG => C_REG_SLICE_MODE_WRCH
)
PORT MAP(
-- System Signals
ACLK => S_ACLK,
ARESET => axi_rs_rst,
-- Slave side
S_PAYLOAD_DATA => wrch_din,
S_VALID => M_AXI_BVALID,
S_READY => M_AXI_BREADY,
-- Master side
M_PAYLOAD_DATA => wrch_dout,
M_VALID => S_AXI_BVALID,
M_READY => S_AXI_BREADY
);
END GENERATE gwrch_reg_slice;
gaxi_wr_ch_uf4: IF (C_USE_COMMON_UNDERFLOW = 1) GENERATE
axi_wr_underflow_i <= axi_aw_underflow_i OR axi_w_underflow_i OR axi_b_underflow_i;
END GENERATE gaxi_wr_ch_uf4;
gaxi_wr_ch_of4: IF (C_USE_COMMON_OVERFLOW = 1) GENERATE
axi_wr_overflow_i <= axi_aw_overflow_i OR axi_w_overflow_i OR axi_b_overflow_i;
END GENERATE gaxi_wr_ch_of4;
gaxi_pkt_fifo_wr: IF (C_APPLICATION_TYPE_WACH = 1) GENERATE
SIGNAL wr_pkt_count : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH_WDCH DOWNTO 0) := (OTHERS => '0');
SIGNAL txn_count_en_up : STD_LOGIC := '0';
SIGNAL txn_count_en_down : STD_LOGIC := '0';
BEGIN
txn_count_en_up <= wdch_s_axi_wready AND wdch_we AND wdch_din(0);
txn_count_en_down <= wach_m_axi_awvalid AND awready_pkt AND awvalid_en;
gaxi_mm_cc_pkt_wr: IF (C_COMMON_CLOCK = 1) GENERATE
proc_wr_txn_cnt: PROCESS (S_ACLK, inverted_reset)
BEGIN
IF (inverted_reset = '1') THEN
wr_pkt_count <= (OTHERS => '0');
ELSIF (S_ACLK'EVENT AND S_ACLK = '1') THEN
IF (txn_count_en_up = '1' AND txn_count_en_down = '0') THEN
wr_pkt_count <= wr_pkt_count + conv_std_logic_vector(1,C_WR_PNTR_WIDTH_WDCH+1);
ELSIF (txn_count_en_down = '1' AND txn_count_en_up = '0') THEN
wr_pkt_count <= wr_pkt_count - conv_std_logic_vector(1,C_WR_PNTR_WIDTH_WDCH+1);
END IF;
END IF;
END PROCESS proc_wr_txn_cnt;
awvalid_en <= '1' WHEN (wr_pkt_count > conv_std_logic_vector(0,C_WR_PNTR_WIDTH_WDCH)) ELSE '0';
END GENERATE gaxi_mm_cc_pkt_wr;
END GENERATE gaxi_pkt_fifo_wr;
END GENERATE gwrch;
grdch: IF (C_HAS_AXI_RD_CHANNEL = 1) GENERATE
SIGNAL rach_din : std_logic_vector(C_DIN_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL rach_dout : std_logic_vector(C_DIN_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL rach_dout_pkt : std_logic_vector(C_DIN_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL rach_full : std_logic := '0';
SIGNAL rach_almost_full : std_logic := '0';
SIGNAL rach_prog_full : std_logic := '0';
SIGNAL rach_empty : std_logic := '0';
SIGNAL rach_almost_empty : std_logic := '0';
SIGNAL rach_prog_empty : std_logic := '0';
SIGNAL rdch_din : std_logic_vector(C_DIN_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL rdch_dout : std_logic_vector(C_DIN_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL rdch_full : std_logic := '0';
SIGNAL rdch_almost_full : std_logic := '0';
SIGNAL rdch_prog_full : std_logic := '0';
SIGNAL rdch_empty : std_logic := '0';
SIGNAL rdch_almost_empty : std_logic := '0';
SIGNAL rdch_prog_empty : std_logic := '0';
SIGNAL axi_ar_underflow_i : std_logic := '0';
SIGNAL axi_ar_overflow_i : std_logic := '0';
SIGNAL axi_r_underflow_i : std_logic := '0';
SIGNAL axi_r_overflow_i : std_logic := '0';
SIGNAL rach_s_axi_arready : std_logic := '0';
SIGNAL rach_m_axi_arvalid : std_logic := '0';
SIGNAL rach_wr_en : std_logic := '0';
SIGNAL rach_rd_en : std_logic := '0';
SIGNAL rdch_m_axi_rready : std_logic := '0';
SIGNAL rdch_s_axi_rvalid : std_logic := '0';
SIGNAL rdch_wr_en : std_logic := '0';
SIGNAL rdch_rd_en : std_logic := '0';
SIGNAL arvalid_en : std_logic := '0';
SIGNAL arready_pkt : std_logic := '0';
SIGNAL rdch_re : STD_LOGIC := '0';
SIGNAL wr_rst_busy_rach : STD_LOGIC := '0';
SIGNAL wr_rst_busy_rdch : STD_LOGIC := '0';
SIGNAL rd_rst_busy_rach : STD_LOGIC := '0';
SIGNAL rd_rst_busy_rdch : STD_LOGIC := '0';
CONSTANT ARID_OFFSET : integer := if_then_else(C_AXI_TYPE /= 2 AND C_HAS_AXI_ID = 1,C_DIN_WIDTH_RACH - C_AXI_ID_WIDTH,C_DIN_WIDTH_RACH);
CONSTANT ARADDR_OFFSET : integer := ARID_OFFSET - C_AXI_ADDR_WIDTH;
CONSTANT ARLEN_OFFSET : integer := if_then_else(C_AXI_TYPE /= 2,ARADDR_OFFSET - C_AXI_LEN_WIDTH,ARADDR_OFFSET);
CONSTANT ARSIZE_OFFSET : integer := if_then_else(C_AXI_TYPE /= 2,ARLEN_OFFSET - C_AXI_SIZE_WIDTH,ARLEN_OFFSET);
CONSTANT ARBURST_OFFSET : integer := if_then_else(C_AXI_TYPE /= 2,ARSIZE_OFFSET - C_AXI_BURST_WIDTH,ARSIZE_OFFSET);
CONSTANT ARLOCK_OFFSET : integer := if_then_else(C_AXI_TYPE /= 2,ARBURST_OFFSET - C_AXI_LOCK_WIDTH,ARBURST_OFFSET);
CONSTANT ARCACHE_OFFSET : integer := if_then_else(C_AXI_TYPE /= 2,ARLOCK_OFFSET - C_AXI_CACHE_WIDTH,ARLOCK_OFFSET);
CONSTANT ARPROT_OFFSET : integer := ARCACHE_OFFSET - C_AXI_PROT_WIDTH;
CONSTANT ARQOS_OFFSET : integer := ARPROT_OFFSET - C_AXI_QOS_WIDTH;
CONSTANT ARREGION_OFFSET : integer := if_then_else(C_AXI_TYPE = 1,ARQOS_OFFSET - C_AXI_REGION_WIDTH,ARQOS_OFFSET);
CONSTANT ARUSER_OFFSET : integer := if_then_else(C_HAS_AXI_ARUSER = 1,ARREGION_OFFSET-C_AXI_ARUSER_WIDTH,ARREGION_OFFSET);
CONSTANT RID_OFFSET : integer := if_then_else(C_AXI_TYPE /= 2 AND C_HAS_AXI_ID = 1,C_DIN_WIDTH_RDCH - C_AXI_ID_WIDTH,C_DIN_WIDTH_RDCH);
CONSTANT RDATA_OFFSET : integer := RID_OFFSET - C_AXI_DATA_WIDTH;
CONSTANT RRESP_OFFSET : integer := RDATA_OFFSET - C_AXI_RRESP_WIDTH;
CONSTANT RUSER_OFFSET : integer := if_then_else(C_HAS_AXI_RUSER = 1,RRESP_OFFSET-C_AXI_RUSER_WIDTH,RRESP_OFFSET);
BEGIN
-- Form the DIN to FIFO by concatinating the AXI Full Write Address Channel optional ports
axi_full_din_rd_ch: IF (C_AXI_TYPE /= 2) GENERATE
grach1: IF (C_RACH_TYPE < 2) GENERATE
grach_din1: IF (C_HAS_AXI_ARUSER = 1) GENERATE
rach_din(ARREGION_OFFSET-1 DOWNTO ARUSER_OFFSET) <= S_AXI_ARUSER;
M_AXI_ARUSER <= rach_dout(ARREGION_OFFSET-1 DOWNTO ARUSER_OFFSET);
END GENERATE grach_din1;
grach_din2: IF (C_HAS_AXI_ARUSER = 0) GENERATE
M_AXI_ARUSER <= (OTHERS => '0');
END GENERATE grach_din2;
grach_din3: IF (C_HAS_AXI_ID = 1) GENERATE
rach_din(C_DIN_WIDTH_RACH-1 DOWNTO ARID_OFFSET) <= S_AXI_ARID;
M_AXI_ARID <= rach_dout(C_DIN_WIDTH_RACH-1 DOWNTO ARID_OFFSET);
END GENERATE grach_din3;
grach_din4: IF (C_HAS_AXI_ID = 0) GENERATE
M_AXI_ARID <= (OTHERS => '0');
END GENERATE grach_din4;
grach_din5: IF (C_AXI_TYPE = 1) GENERATE
rach_din(ARQOS_OFFSET-1 DOWNTO ARREGION_OFFSET) <= S_AXI_ARREGION;
M_AXI_ARREGION <= rach_dout(ARQOS_OFFSET-1 DOWNTO ARREGION_OFFSET);
END GENERATE grach_din5;
grach_din6: IF (C_AXI_TYPE = 0) GENERATE
M_AXI_ARREGION <= (OTHERS => '0');
END GENERATE grach_din6;
rach_din(ARID_OFFSET-1 DOWNTO ARADDR_OFFSET) <= S_AXI_ARADDR;
rach_din(ARADDR_OFFSET-1 DOWNTO ARLEN_OFFSET) <= S_AXI_ARLEN;
rach_din(ARLEN_OFFSET-1 DOWNTO ARSIZE_OFFSET) <= S_AXI_ARSIZE;
rach_din(ARSIZE_OFFSET-1 DOWNTO ARBURST_OFFSET) <= S_AXI_ARBURST;
rach_din(ARBURST_OFFSET-1 DOWNTO ARLOCK_OFFSET) <= S_AXI_ARLOCK;
rach_din(ARLOCK_OFFSET-1 DOWNTO ARCACHE_OFFSET) <= S_AXI_ARCACHE;
rach_din(ARCACHE_OFFSET-1 DOWNTO ARPROT_OFFSET) <= S_AXI_ARPROT;
rach_din(ARPROT_OFFSET-1 DOWNTO ARQOS_OFFSET) <= S_AXI_ARQOS;
M_AXI_ARADDR <= rach_dout(ARID_OFFSET-1 DOWNTO ARADDR_OFFSET);
M_AXI_ARLEN <= rach_dout(ARADDR_OFFSET-1 DOWNTO ARLEN_OFFSET);
M_AXI_ARSIZE <= rach_dout(ARLEN_OFFSET-1 DOWNTO ARSIZE_OFFSET);
M_AXI_ARBURST <= rach_dout(ARSIZE_OFFSET-1 DOWNTO ARBURST_OFFSET);
M_AXI_ARLOCK <= rach_dout(ARBURST_OFFSET-1 DOWNTO ARLOCK_OFFSET);
M_AXI_ARCACHE <= rach_dout(ARLOCK_OFFSET-1 DOWNTO ARCACHE_OFFSET);
M_AXI_ARPROT <= rach_dout(ARCACHE_OFFSET-1 DOWNTO ARPROT_OFFSET);
M_AXI_ARQOS <= rach_dout(ARPROT_OFFSET-1 DOWNTO ARQOS_OFFSET);
END GENERATE grach1;
-- Generate the DIN to FIFO by concatinating the AXI Full Write Data Channel optional ports
grdch1: IF (C_RDCH_TYPE < 2) GENERATE
grdch_din1: IF (C_HAS_AXI_RUSER = 1) GENERATE
rdch_din(RRESP_OFFSET-1 DOWNTO RUSER_OFFSET) <= M_AXI_RUSER;
S_AXI_RUSER <= rdch_dout(RRESP_OFFSET-1 DOWNTO RUSER_OFFSET);
END GENERATE grdch_din1;
grdch_din2: IF (C_HAS_AXI_RUSER = 0) GENERATE
S_AXI_RUSER <= (OTHERS => '0');
END GENERATE grdch_din2;
grdch_din3: IF (C_HAS_AXI_ID = 1) GENERATE
rdch_din(C_DIN_WIDTH_RDCH-1 DOWNTO RID_OFFSET) <= M_AXI_RID;
S_AXI_RID <= rdch_dout(C_DIN_WIDTH_RDCH-1 DOWNTO RID_OFFSET);
END GENERATE grdch_din3;
grdch_din4: IF (C_HAS_AXI_ID = 0) GENERATE
S_AXI_RID <= (OTHERS => '0');
END GENERATE grdch_din4;
rdch_din(RID_OFFSET-1 DOWNTO RDATA_OFFSET) <= M_AXI_RDATA;
rdch_din(RDATA_OFFSET-1 DOWNTO RRESP_OFFSET) <= M_AXI_RRESP;
rdch_din(0) <= M_AXI_RLAST;
S_AXI_RDATA <= rdch_dout(RID_OFFSET-1 DOWNTO RDATA_OFFSET);
S_AXI_RRESP <= rdch_dout(RDATA_OFFSET-1 DOWNTO RRESP_OFFSET);
S_AXI_RLAST <= rdch_dout(0);
END GENERATE grdch1;
END GENERATE axi_full_din_rd_ch;
-- Form the DIN to FIFO by concatinating the AXI Lite Read Address Channel optional ports
axi_lite_din_rd_ch: IF (C_AXI_TYPE = 2) GENERATE
grach1: IF (C_RACH_TYPE < 2) GENERATE
rach_din <= S_AXI_ARADDR & S_AXI_ARPROT;
M_AXI_ARADDR <= rach_dout(C_DIN_WIDTH_RACH-1 DOWNTO ARADDR_OFFSET);
M_AXI_ARPROT <= rach_dout(ARADDR_OFFSET-1 DOWNTO ARPROT_OFFSET);
END GENERATE grach1;
grdch1: IF (C_RDCH_TYPE < 2) GENERATE
rdch_din <= M_AXI_RDATA & M_AXI_RRESP;
S_AXI_RDATA <= rdch_dout(C_DIN_WIDTH_RDCH-1 DOWNTO RDATA_OFFSET);
S_AXI_RRESP <= rdch_dout(RDATA_OFFSET-1 DOWNTO RRESP_OFFSET);
END GENERATE grdch1;
END GENERATE axi_lite_din_rd_ch;
-- Write protection for Read Address Channel
-- When FULL is high, pass VALID as a WR_EN to the FIFO to get OVERFLOW interrupt
grach_wr_en1: IF (C_PROG_FULL_TYPE_RACH = 0) GENERATE
rach_wr_en <= S_AXI_ARVALID;
END GENERATE grach_wr_en1;
-- When ALMOST_FULL or PROG_FULL is high, then shield the FIFO from becoming FULL
grach_wr_en2: IF (C_PROG_FULL_TYPE_RACH /= 0) GENERATE
rach_wr_en <= rach_s_axi_arready AND S_AXI_ARVALID;
END GENERATE grach_wr_en2;
-- Write protection for Read Data Channel
-- When FULL is high, pass VALID as a WR_EN to the FIFO to get OVERFLOW interrupt
grdch_wr_en1: IF (C_PROG_FULL_TYPE_RDCH = 0) GENERATE
rdch_wr_en <= M_AXI_RVALID;
END GENERATE grdch_wr_en1;
-- When ALMOST_FULL or PROG_FULL is high, then shield the FIFO from becoming FULL
grdch_wr_en2: IF (C_PROG_FULL_TYPE_RDCH /= 0) GENERATE
rdch_wr_en <= rdch_m_axi_rready AND M_AXI_RVALID;
END GENERATE grdch_wr_en2;
-- Read protection for Read Address Channel
-- When EMPTY is low, pass READY as a RD_EN to the FIFO to get UNDERFLOW interrupt
grach_rd_en1: IF (C_PROG_EMPTY_TYPE_RACH = 0) GENERATE
gpkt_mm_rach_rd_en1: IF (C_APPLICATION_TYPE_RACH = 1) GENERATE
rach_rd_en <= arready_pkt AND arvalid_en;
END GENERATE;
gnpkt_mm_rach_rd_en1: IF (C_APPLICATION_TYPE_RACH /= 1) GENERATE
rach_rd_en <= M_AXI_ARREADY;
END GENERATE;
END GENERATE grach_rd_en1;
-- When ALMOST_EMPTY or PROG_EMPTY is low, then shield the FIFO from becoming EMPTY
grach_rd_en2: IF (C_PROG_EMPTY_TYPE_RACH /= 0) GENERATE
gaxi_mm_rach_rd_en2: IF (C_APPLICATION_TYPE_RACH = 1) GENERATE
rach_rd_en <= rach_m_axi_arvalid AND arready_pkt AND arvalid_en;
END GENERATE gaxi_mm_rach_rd_en2;
gnaxi_mm_rach_rd_en2: IF (C_APPLICATION_TYPE_RACH /= 1) GENERATE
rach_rd_en <= rach_m_axi_arvalid AND M_AXI_ARREADY;
END GENERATE gnaxi_mm_rach_rd_en2;
END GENERATE grach_rd_en2;
-- Read protection for Read Data Channel
-- When EMPTY is low, pass READY as a RD_EN to the FIFO to get UNDERFLOW interrupt
grdch_rd_en1: IF (C_PROG_EMPTY_TYPE_RDCH = 0) GENERATE
rdch_rd_en <= S_AXI_RREADY;
END GENERATE grdch_rd_en1;
-- When ALMOST_EMPTY or PROG_EMPTY is low, then shield the FIFO from becoming EMPTY
grdch_rd_en2: IF (C_PROG_EMPTY_TYPE_RDCH /= 0) GENERATE
rdch_rd_en <= rdch_s_axi_rvalid AND S_AXI_RREADY;
END GENERATE grdch_rd_en2;
grach2: IF (C_RACH_TYPE = 0) GENERATE
SIGNAL rach_we : STD_LOGIC := '0';
SIGNAL rach_re : STD_LOGIC := '0';
BEGIN
rach_we <= rach_wr_en WHEN (C_HAS_SLAVE_CE = 0) ELSE rach_wr_en AND S_ACLK_EN;
rach_re <= rach_rd_en WHEN (C_HAS_MASTER_CE = 0) ELSE rach_rd_en AND M_ACLK_EN;
axi_rach : fifo_generator_v13_0_1_conv
GENERIC MAP (
C_FAMILY => C_FAMILY,
C_COMMON_CLOCK => C_COMMON_CLOCK,
C_INTERFACE_TYPE => C_INTERFACE_TYPE,
C_MEMORY_TYPE => if_then_else((C_IMPLEMENTATION_TYPE_RACH = 1 OR C_IMPLEMENTATION_TYPE_RACH = 11),1,
if_then_else((C_IMPLEMENTATION_TYPE_RACH = 2 OR C_IMPLEMENTATION_TYPE_RACH = 12),2,4)),
C_IMPLEMENTATION_TYPE => if_then_else((C_IMPLEMENTATION_TYPE_RACH = 1 OR C_IMPLEMENTATION_TYPE_RACH = 2),0,
if_then_else((C_IMPLEMENTATION_TYPE_RACH = 11 OR C_IMPLEMENTATION_TYPE_RACH = 12),2,6)),
C_PRELOAD_REGS => 1, -- Always FWFT for AXI
C_PRELOAD_LATENCY => 0, -- Always FWFT for AXI
C_DIN_WIDTH => C_DIN_WIDTH_RACH,
C_WR_DEPTH => C_WR_DEPTH_RACH,
C_WR_PNTR_WIDTH => C_WR_PNTR_WIDTH_RACH,
C_DOUT_WIDTH => C_DIN_WIDTH_RACH,
C_RD_DEPTH => C_WR_DEPTH_RACH,
C_RD_PNTR_WIDTH => C_WR_PNTR_WIDTH_RACH,
C_PROG_FULL_TYPE => C_PROG_FULL_TYPE_RACH,
C_PROG_FULL_THRESH_ASSERT_VAL => C_PROG_FULL_THRESH_ASSERT_VAL_RACH,
C_PROG_EMPTY_TYPE => C_PROG_EMPTY_TYPE_RACH,
C_PROG_EMPTY_THRESH_ASSERT_VAL => C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH,
C_USE_ECC => C_USE_ECC_RACH,
C_ERROR_INJECTION_TYPE => C_ERROR_INJECTION_TYPE_RACH,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
-- Enable Low Latency Sync FIFO for Common Clock Built-in FIFO
C_FIFO_TYPE => if_then_else((C_APPLICATION_TYPE_RACH = 1),0,C_APPLICATION_TYPE_RACH),
C_SYNCHRONIZER_STAGE => C_SYNCHRONIZER_STAGE,
C_AXI_TYPE => if_then_else(C_INTERFACE_TYPE = 1, 0, C_AXI_TYPE),
C_HAS_WR_RST => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_DOUT_RST_VAL => "0",
C_HAS_VALID => C_HAS_VALID,
C_VALID_LOW => C_VALID_LOW,
C_HAS_UNDERFLOW => C_HAS_UNDERFLOW,
C_UNDERFLOW_LOW => C_UNDERFLOW_LOW,
C_HAS_WR_ACK => C_HAS_WR_ACK,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_HAS_OVERFLOW => C_HAS_OVERFLOW,
C_OVERFLOW_LOW => C_OVERFLOW_LOW,
C_HAS_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 1 AND C_HAS_DATA_COUNTS_RACH = 1), 1, 0),
C_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_RACH+1,
C_HAS_RD_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 0 AND C_HAS_DATA_COUNTS_RACH = 1), 1, 0),
C_RD_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_RACH+1,
C_USE_FWFT_DATA_COUNT => 1, -- use extra logic is always true
C_HAS_WR_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 0 AND C_HAS_DATA_COUNTS_RACH = 1), 1, 0),
C_WR_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_RACH+1,
C_FULL_FLAGS_RST_VAL => 1,
C_USE_EMBEDDED_REG => 0,
C_USE_DOUT_RST => 0,
C_MSGON_VAL => C_MSGON_VAL,
C_ENABLE_RST_SYNC => 1,
C_EN_SAFETY_CKT => 1,
C_COUNT_TYPE => C_COUNT_TYPE,
C_DEFAULT_VALUE => C_DEFAULT_VALUE,
C_ENABLE_RLOCS => C_ENABLE_RLOCS,
C_HAS_BACKUP => C_HAS_BACKUP,
C_HAS_INT_CLK => C_HAS_INT_CLK,
C_HAS_MEMINIT_FILE => C_HAS_MEMINIT_FILE,
C_INIT_WR_PNTR_VAL => C_INIT_WR_PNTR_VAL,
C_MIF_FILE_NAME => C_MIF_FILE_NAME,
C_OPTIMIZATION_MODE => C_OPTIMIZATION_MODE,
C_WR_FREQ => C_WR_FREQ,
C_USE_FIFO16_FLAGS => C_USE_FIFO16_FLAGS,
C_RD_FREQ => C_RD_FREQ,
C_WR_RESPONSE_LATENCY => C_WR_RESPONSE_LATENCY
)
PORT MAP(
--Inputs
BACKUP => BACKUP,
BACKUP_MARKER => BACKUP_MARKER,
INT_CLK => INT_CLK,
CLK => S_ACLK,
WR_CLK => S_ACLK,
RD_CLK => M_ACLK,
RST => inverted_reset,
SRST => '0',
WR_RST => inverted_reset,
RD_RST => inverted_reset,
WR_EN => rach_we,
RD_EN => rach_re,
PROG_FULL_THRESH => AXI_AR_PROG_FULL_THRESH,
PROG_FULL_THRESH_ASSERT => (OTHERS => '0'),
PROG_FULL_THRESH_NEGATE => (OTHERS => '0'),
PROG_EMPTY_THRESH => AXI_AR_PROG_EMPTY_THRESH,
PROG_EMPTY_THRESH_ASSERT => (OTHERS => '0'),
PROG_EMPTY_THRESH_NEGATE => (OTHERS => '0'),
INJECTDBITERR => AXI_AR_INJECTDBITERR,
INJECTSBITERR => AXI_AR_INJECTSBITERR,
DIN => rach_din,
DOUT => rach_dout_pkt,
FULL => rach_full,
EMPTY => rach_empty,
ALMOST_FULL => OPEN,
PROG_FULL => AXI_AR_PROG_FULL,
ALMOST_EMPTY => OPEN,
PROG_EMPTY => AXI_AR_PROG_EMPTY,
WR_ACK => OPEN,
OVERFLOW => axi_ar_overflow_i,
VALID => OPEN,
UNDERFLOW => axi_ar_underflow_i,
DATA_COUNT => AXI_AR_DATA_COUNT,
RD_DATA_COUNT => AXI_AR_RD_DATA_COUNT,
WR_DATA_COUNT => AXI_AR_WR_DATA_COUNT,
SBITERR => AXI_AR_SBITERR,
DBITERR => AXI_AR_DBITERR,
WR_RST_BUSY => wr_rst_busy_rach,
RD_RST_BUSY => rd_rst_busy_rach,
WR_RST_I_OUT => OPEN,
RD_RST_I_OUT => OPEN
);
g8s_rach_rdy: IF (IS_8SERIES = 1) GENERATE
g8s_bi_rach_rdy: IF (C_IMPLEMENTATION_TYPE_RACH = 5 OR C_IMPLEMENTATION_TYPE_RACH = 13) GENERATE
rach_s_axi_arready <= NOT (rach_full OR wr_rst_busy_rach);
END GENERATE g8s_bi_rach_rdy;
g8s_nbi_rach_rdy: IF (NOT (C_IMPLEMENTATION_TYPE_RACH = 5 OR C_IMPLEMENTATION_TYPE_RACH = 13)) GENERATE
rach_s_axi_arready <= NOT (rach_full);
END GENERATE g8s_nbi_rach_rdy;
END GENERATE g8s_rach_rdy;
g7s_rach_rdy: IF (IS_8SERIES = 0) GENERATE
rach_s_axi_arready <= NOT (rach_full);
END GENERATE g7s_rach_rdy;
rach_m_axi_arvalid <= NOT rach_empty;
S_AXI_ARREADY <= rach_s_axi_arready;
gaxi_arvld: IF (C_APPLICATION_TYPE_RACH = 1) GENERATE
SIGNAL arvalid_pkt : STD_LOGIC := '0';
BEGIN
arvalid_pkt <= rach_m_axi_arvalid AND arvalid_en;
rach_pkt_reg_slice: fifo_generator_v13_0_1_axic_reg_slice
GENERIC MAP (
C_FAMILY => C_FAMILY,
C_DATA_WIDTH => C_DIN_WIDTH_RACH,
C_REG_CONFIG => 1
)
PORT MAP(
-- System Signals
ACLK => S_ACLK,
ARESET => inverted_reset,
-- Slave side
S_PAYLOAD_DATA => rach_dout_pkt,
S_VALID => arvalid_pkt,
S_READY => arready_pkt,
-- Master side
M_PAYLOAD_DATA => rach_dout,
M_VALID => M_AXI_ARVALID,
M_READY => M_AXI_ARREADY
);
END GENERATE gaxi_arvld;
gnaxi_arvld: IF (C_APPLICATION_TYPE_RACH /= 1) GENERATE
M_AXI_ARVALID <= rach_m_axi_arvalid;
rach_dout <= rach_dout_pkt;
END GENERATE gnaxi_arvld;
gaxi_rd_ch_uf1: IF (C_USE_COMMON_UNDERFLOW = 0) GENERATE
AXI_AR_UNDERFLOW <= axi_ar_underflow_i;
END GENERATE gaxi_rd_ch_uf1;
gaxi_rd_ch_of1: IF (C_USE_COMMON_OVERFLOW = 0) GENERATE
AXI_AR_OVERFLOW <= axi_ar_overflow_i;
END GENERATE gaxi_rd_ch_of1;
END GENERATE grach2;
-- Register Slice for Read Address Channel
grach_reg_slice: IF (C_RACH_TYPE = 1) GENERATE
rach_reg_slice: fifo_generator_v13_0_1_axic_reg_slice
GENERIC MAP (
C_FAMILY => C_FAMILY,
C_DATA_WIDTH => C_DIN_WIDTH_RACH,
C_REG_CONFIG => C_REG_SLICE_MODE_RACH
)
PORT MAP(
-- System Signals
ACLK => S_ACLK,
ARESET => axi_rs_rst,
-- Slave side
S_PAYLOAD_DATA => rach_din,
S_VALID => S_AXI_ARVALID,
S_READY => S_AXI_ARREADY,
-- Master side
M_PAYLOAD_DATA => rach_dout,
M_VALID => M_AXI_ARVALID,
M_READY => M_AXI_ARREADY
);
END GENERATE grach_reg_slice;
grdch2: IF (C_RDCH_TYPE = 0) GENERATE
SIGNAL rdch_we : STD_LOGIC := '0';
BEGIN
rdch_we <= rdch_wr_en WHEN (C_HAS_MASTER_CE = 0) ELSE rdch_wr_en AND M_ACLK_EN;
rdch_re <= rdch_rd_en WHEN (C_HAS_SLAVE_CE = 0) ELSE rdch_rd_en AND S_ACLK_EN;
axi_rdch : fifo_generator_v13_0_1_conv
GENERIC MAP (
C_FAMILY => C_FAMILY,
C_COMMON_CLOCK => C_COMMON_CLOCK,
C_INTERFACE_TYPE => C_INTERFACE_TYPE,
C_MEMORY_TYPE => if_then_else((C_IMPLEMENTATION_TYPE_RDCH = 1 OR C_IMPLEMENTATION_TYPE_RDCH = 11),1,
if_then_else((C_IMPLEMENTATION_TYPE_RDCH = 2 OR C_IMPLEMENTATION_TYPE_RDCH = 12),2,4)),
C_IMPLEMENTATION_TYPE => if_then_else((C_IMPLEMENTATION_TYPE_RDCH = 1 OR C_IMPLEMENTATION_TYPE_RDCH = 2),0,
if_then_else((C_IMPLEMENTATION_TYPE_RDCH = 11 OR C_IMPLEMENTATION_TYPE_RDCH = 12),2,6)),
C_PRELOAD_REGS => 1, -- Always FWFT for AXI
C_PRELOAD_LATENCY => 0, -- Always FWFT for AXI
C_DIN_WIDTH => C_DIN_WIDTH_RDCH,
C_WR_DEPTH => C_WR_DEPTH_RDCH,
C_WR_PNTR_WIDTH => C_WR_PNTR_WIDTH_RDCH,
C_DOUT_WIDTH => C_DIN_WIDTH_RDCH,
C_RD_DEPTH => C_WR_DEPTH_RDCH,
C_RD_PNTR_WIDTH => C_WR_PNTR_WIDTH_RDCH,
C_PROG_FULL_TYPE => C_PROG_FULL_TYPE_RDCH,
C_PROG_FULL_THRESH_ASSERT_VAL => C_PROG_FULL_THRESH_ASSERT_VAL_RDCH,
C_PROG_EMPTY_TYPE => C_PROG_EMPTY_TYPE_RDCH,
C_PROG_EMPTY_THRESH_ASSERT_VAL => C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH,
C_USE_ECC => C_USE_ECC_RDCH,
C_ERROR_INJECTION_TYPE => C_ERROR_INJECTION_TYPE_RDCH,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
-- Enable Low Latency Sync FIFO for Common Clock Built-in FIFO
C_FIFO_TYPE => C_APPLICATION_TYPE_RDCH,
C_SYNCHRONIZER_STAGE => C_SYNCHRONIZER_STAGE,
C_AXI_TYPE => if_then_else(C_INTERFACE_TYPE = 1, 0, C_AXI_TYPE),
C_HAS_WR_RST => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_DOUT_RST_VAL => "0",
C_HAS_VALID => C_HAS_VALID,
C_VALID_LOW => C_VALID_LOW,
C_HAS_UNDERFLOW => C_HAS_UNDERFLOW,
C_UNDERFLOW_LOW => C_UNDERFLOW_LOW,
C_HAS_WR_ACK => C_HAS_WR_ACK,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_HAS_OVERFLOW => C_HAS_OVERFLOW,
C_OVERFLOW_LOW => C_OVERFLOW_LOW,
C_HAS_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 1 AND C_HAS_DATA_COUNTS_RDCH = 1), 1, 0),
C_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_RDCH+1,
C_HAS_RD_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 0 AND C_HAS_DATA_COUNTS_RDCH = 1), 1, 0),
C_RD_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_RDCH+1,
C_USE_FWFT_DATA_COUNT => 1, -- use extra logic is always true
C_HAS_WR_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 0 AND C_HAS_DATA_COUNTS_RDCH = 1), 1, 0),
C_WR_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_RDCH+1,
C_FULL_FLAGS_RST_VAL => 1,
C_USE_EMBEDDED_REG => 0,
C_USE_DOUT_RST => 0,
C_MSGON_VAL => C_MSGON_VAL,
C_ENABLE_RST_SYNC => 1,
C_EN_SAFETY_CKT => 1,
C_COUNT_TYPE => C_COUNT_TYPE,
C_DEFAULT_VALUE => C_DEFAULT_VALUE,
C_ENABLE_RLOCS => C_ENABLE_RLOCS,
C_HAS_BACKUP => C_HAS_BACKUP,
C_HAS_INT_CLK => C_HAS_INT_CLK,
C_HAS_MEMINIT_FILE => C_HAS_MEMINIT_FILE,
C_INIT_WR_PNTR_VAL => C_INIT_WR_PNTR_VAL,
C_MIF_FILE_NAME => C_MIF_FILE_NAME,
C_OPTIMIZATION_MODE => C_OPTIMIZATION_MODE,
C_WR_FREQ => C_WR_FREQ,
C_USE_FIFO16_FLAGS => C_USE_FIFO16_FLAGS,
C_RD_FREQ => C_RD_FREQ,
C_WR_RESPONSE_LATENCY => C_WR_RESPONSE_LATENCY
)
PORT MAP(
--Inputs
BACKUP => BACKUP,
BACKUP_MARKER => BACKUP_MARKER,
INT_CLK => INT_CLK,
CLK => S_ACLK,
WR_CLK => M_ACLK,
RD_CLK => S_ACLK,
RST => inverted_reset,
SRST => '0',
WR_RST => inverted_reset,
RD_RST => inverted_reset,
WR_EN => rdch_we,
RD_EN => rdch_re,
PROG_FULL_THRESH => AXI_R_PROG_FULL_THRESH,
PROG_FULL_THRESH_ASSERT => (OTHERS => '0'),
PROG_FULL_THRESH_NEGATE => (OTHERS => '0'),
PROG_EMPTY_THRESH => AXI_R_PROG_EMPTY_THRESH,
PROG_EMPTY_THRESH_ASSERT => (OTHERS => '0'),
PROG_EMPTY_THRESH_NEGATE => (OTHERS => '0'),
INJECTDBITERR => AXI_R_INJECTDBITERR,
INJECTSBITERR => AXI_R_INJECTSBITERR,
DIN => rdch_din,
DOUT => rdch_dout,
FULL => rdch_full,
EMPTY => rdch_empty,
ALMOST_FULL => OPEN,
PROG_FULL => AXI_R_PROG_FULL,
ALMOST_EMPTY => OPEN,
PROG_EMPTY => AXI_R_PROG_EMPTY,
WR_ACK => OPEN,
OVERFLOW => axi_r_overflow_i,
VALID => OPEN,
UNDERFLOW => axi_r_underflow_i,
DATA_COUNT => AXI_R_DATA_COUNT,
RD_DATA_COUNT => AXI_R_RD_DATA_COUNT,
WR_DATA_COUNT => AXI_R_WR_DATA_COUNT,
SBITERR => AXI_R_SBITERR,
DBITERR => AXI_R_DBITERR,
WR_RST_BUSY => wr_rst_busy_rdch,
RD_RST_BUSY => rd_rst_busy_rdch,
WR_RST_I_OUT => OPEN,
RD_RST_I_OUT => OPEN
);
rdch_s_axi_rvalid <= NOT rdch_empty;
g8s_rdch_rdy: IF (IS_8SERIES = 1) GENERATE
g8s_bi_rdch_rdy: IF (C_IMPLEMENTATION_TYPE_RDCH = 5 OR C_IMPLEMENTATION_TYPE_RDCH = 13) GENERATE
rdch_m_axi_rready <= NOT (rdch_full OR wr_rst_busy_rdch);
END GENERATE g8s_bi_rdch_rdy;
g8s_nbi_rdch_rdy: IF (NOT (C_IMPLEMENTATION_TYPE_RDCH = 5 OR C_IMPLEMENTATION_TYPE_RDCH = 13)) GENERATE
rdch_m_axi_rready <= NOT (rdch_full);
END GENERATE g8s_nbi_rdch_rdy;
END GENERATE g8s_rdch_rdy;
g7s_rdch_rdy: IF (IS_8SERIES = 0) GENERATE
rdch_m_axi_rready <= NOT (rdch_full);
END GENERATE g7s_rdch_rdy;
S_AXI_RVALID <= rdch_s_axi_rvalid;
M_AXI_RREADY <= rdch_m_axi_rready;
gaxi_rd_ch_uf2: IF (C_USE_COMMON_UNDERFLOW = 0) GENERATE
AXI_R_UNDERFLOW <= axi_r_underflow_i;
END GENERATE gaxi_rd_ch_uf2;
gaxi_rd_ch_of2: IF (C_USE_COMMON_OVERFLOW = 0) GENERATE
AXI_R_OVERFLOW <= axi_r_overflow_i;
END GENERATE gaxi_rd_ch_of2;
END GENERATE grdch2;
-- Register Slice for Read Data Channel
grdch_reg_slice: IF (C_RDCH_TYPE = 1) GENERATE
rdch_reg_slice: fifo_generator_v13_0_1_axic_reg_slice
GENERIC MAP (
C_FAMILY => C_FAMILY,
C_DATA_WIDTH => C_DIN_WIDTH_RDCH,
C_REG_CONFIG => C_REG_SLICE_MODE_RDCH
)
PORT MAP(
-- System Signals
ACLK => S_ACLK,
ARESET => axi_rs_rst,
-- Slave side
S_PAYLOAD_DATA => rdch_din,
S_VALID => M_AXI_RVALID,
S_READY => M_AXI_RREADY,
-- Master side
M_PAYLOAD_DATA => rdch_dout,
M_VALID => S_AXI_RVALID,
M_READY => S_AXI_RREADY
);
END GENERATE grdch_reg_slice;
gaxi_rd_ch_uf3: IF (C_USE_COMMON_UNDERFLOW = 1) GENERATE
axi_rd_underflow_i <= axi_ar_underflow_i OR axi_r_underflow_i;
END GENERATE gaxi_rd_ch_uf3;
gaxi_rd_ch_of3: IF (C_USE_COMMON_OVERFLOW = 1) GENERATE
axi_rd_overflow_i <= axi_ar_overflow_i OR axi_r_overflow_i;
END GENERATE gaxi_rd_ch_of3;
gaxi_pkt_fifo_rd: IF (C_APPLICATION_TYPE_RACH = 1) GENERATE
SIGNAL rd_burst_length : STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_fifo_free_space : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH_RDCH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_fifo_committed_space : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH_RDCH DOWNTO 0) := (OTHERS => '0');
SIGNAL txn_count_en_up : STD_LOGIC := '0';
SIGNAL txn_count_en_down : STD_LOGIC := '0';
SIGNAL rdch_rd_ok : STD_LOGIC := '0';
SIGNAL accept_next_pkt : STD_LOGIC := '0';
SIGNAL decrement_val : INTEGER := 0;
BEGIN
rd_burst_length <= ('0' & rach_dout_pkt(ARADDR_OFFSET-1 DOWNTO ARLEN_OFFSET)) + conv_std_logic_vector(1,9);
accept_next_pkt <= rach_m_axi_arvalid AND arready_pkt AND arvalid_en;
rdch_rd_ok <= rdch_re AND rdch_s_axi_rvalid;
arvalid_en <= '1' WHEN (rd_fifo_free_space >= rd_burst_length) ELSE '0';
gaxi_mm_cc_pkt_rd: IF (C_COMMON_CLOCK = 1) GENERATE
rd_fifo_free_space <= conv_std_logic_vector(C_WR_DEPTH_RDCH-conv_integer(rd_fifo_committed_space),C_WR_PNTR_WIDTH_RDCH+1);
decrement_val <= 1 WHEN (rdch_rd_ok = '1') ELSE 0;
proc_rd_txn_cnt: PROCESS (S_ACLK, inverted_reset)
BEGIN
IF (inverted_reset = '1') THEN
rd_fifo_committed_space <= (OTHERS => '0');
ELSIF (S_ACLK'EVENT AND S_ACLK = '1') THEN
IF (accept_next_pkt = '1') THEN
-- Subtract 1 if read happens on read data FIFO while adding ARLEN
rd_fifo_committed_space <= rd_fifo_committed_space + conv_std_logic_vector((conv_integer(rd_burst_length) - decrement_val), C_WR_PNTR_WIDTH_RDCH+1);
ELSIF (rdch_rd_ok = '1') THEN
-- Subtract 1 whenever read happens on read data FIFO
rd_fifo_committed_space <= rd_fifo_committed_space - conv_std_logic_vector(1,C_WR_PNTR_WIDTH_RDCH+1);
END IF;
END IF;
END PROCESS proc_rd_txn_cnt;
END GENERATE gaxi_mm_cc_pkt_rd;
END GENERATE gaxi_pkt_fifo_rd;
END GENERATE grdch;
gaxi_comm_uf: IF (C_USE_COMMON_UNDERFLOW = 1) GENERATE
grdwr_uf1: IF (C_HAS_AXI_WR_CHANNEL = 1 AND C_HAS_AXI_RD_CHANNEL = 1) GENERATE
UNDERFLOW <= axi_wr_underflow_i OR axi_rd_underflow_i;
END GENERATE grdwr_uf1;
grdwr_uf2: IF (C_HAS_AXI_WR_CHANNEL = 1 AND C_HAS_AXI_RD_CHANNEL = 0) GENERATE
UNDERFLOW <= axi_wr_underflow_i;
END GENERATE grdwr_uf2;
grdwr_uf3: IF (C_HAS_AXI_WR_CHANNEL = 0 AND C_HAS_AXI_RD_CHANNEL = 1) GENERATE
UNDERFLOW <= axi_rd_underflow_i;
END GENERATE grdwr_uf3;
END GENERATE gaxi_comm_uf;
gaxi_comm_of: IF (C_USE_COMMON_OVERFLOW = 1) GENERATE
grdwr_of1: IF (C_HAS_AXI_WR_CHANNEL = 1 AND C_HAS_AXI_RD_CHANNEL = 1) GENERATE
OVERFLOW <= axi_wr_overflow_i OR axi_rd_overflow_i;
END GENERATE grdwr_of1;
grdwr_of2: IF (C_HAS_AXI_WR_CHANNEL = 1 AND C_HAS_AXI_RD_CHANNEL = 0) GENERATE
OVERFLOW <= axi_wr_overflow_i;
END GENERATE grdwr_of2;
grdwr_of3: IF (C_HAS_AXI_WR_CHANNEL = 0 AND C_HAS_AXI_RD_CHANNEL = 1) GENERATE
OVERFLOW <= axi_rd_overflow_i;
END GENERATE grdwr_of3;
END GENERATE gaxi_comm_of;
END GENERATE gaxifull;
---------------------------------------------------------------------------
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Pass Through Logic or Wiring Logic
---------------------------------------------------------------------------
---------------------------------------------------------------------------
---------------------------------------------------------------------------
gaxi_pass_through: IF (C_WACH_TYPE = 2 OR C_WDCH_TYPE = 2 OR C_WRCH_TYPE = 2 OR
C_RACH_TYPE = 2 OR C_RDCH_TYPE = 2 OR C_AXIS_TYPE = 2) GENERATE
gwach_pass_through: IF (C_WACH_TYPE = 2) GENERATE -- Wiring logic for Write Address Channel
M_AXI_AWID <= S_AXI_AWID;
M_AXI_AWADDR <= S_AXI_AWADDR;
M_AXI_AWLEN <= S_AXI_AWLEN;
M_AXI_AWSIZE <= S_AXI_AWSIZE;
M_AXI_AWBURST <= S_AXI_AWBURST;
M_AXI_AWLOCK <= S_AXI_AWLOCK;
M_AXI_AWCACHE <= S_AXI_AWCACHE;
M_AXI_AWPROT <= S_AXI_AWPROT;
M_AXI_AWQOS <= S_AXI_AWQOS;
M_AXI_AWREGION <= S_AXI_AWREGION;
M_AXI_AWUSER <= S_AXI_AWUSER;
S_AXI_AWREADY <= M_AXI_AWREADY;
M_AXI_AWVALID <= S_AXI_AWVALID;
END GENERATE gwach_pass_through;
-- Wiring logic for Write Data Channel
gwdch_pass_through: IF (C_WDCH_TYPE = 2) GENERATE
M_AXI_WID <= S_AXI_WID;
M_AXI_WDATA <= S_AXI_WDATA;
M_AXI_WSTRB <= S_AXI_WSTRB;
M_AXI_WLAST <= S_AXI_WLAST;
M_AXI_WUSER <= S_AXI_WUSER;
S_AXI_WREADY <= M_AXI_WREADY;
M_AXI_WVALID <= S_AXI_WVALID;
END GENERATE gwdch_pass_through;
-- Wiring logic for Write Response Channel
gwrch_pass_through: IF (C_WRCH_TYPE = 2) GENERATE
S_AXI_BID <= M_AXI_BID;
S_AXI_BRESP <= M_AXI_BRESP;
S_AXI_BUSER <= M_AXI_BUSER;
M_AXI_BREADY <= S_AXI_BREADY;
S_AXI_BVALID <= M_AXI_BVALID;
END GENERATE gwrch_pass_through;
-- Pass Through Logic for Read Channel
grach_pass_through: IF (C_RACH_TYPE = 2) GENERATE -- Wiring logic for Read Address Channel
M_AXI_ARID <= S_AXI_ARID;
M_AXI_ARADDR <= S_AXI_ARADDR;
M_AXI_ARLEN <= S_AXI_ARLEN;
M_AXI_ARSIZE <= S_AXI_ARSIZE;
M_AXI_ARBURST <= S_AXI_ARBURST;
M_AXI_ARLOCK <= S_AXI_ARLOCK;
M_AXI_ARCACHE <= S_AXI_ARCACHE;
M_AXI_ARPROT <= S_AXI_ARPROT;
M_AXI_ARQOS <= S_AXI_ARQOS;
M_AXI_ARREGION <= S_AXI_ARREGION;
M_AXI_ARUSER <= S_AXI_ARUSER;
S_AXI_ARREADY <= M_AXI_ARREADY;
M_AXI_ARVALID <= S_AXI_ARVALID;
END GENERATE grach_pass_through;
grdch_pass_through: IF (C_RDCH_TYPE = 2) GENERATE -- Wiring logic for Read Data Channel
S_AXI_RID <= M_AXI_RID;
S_AXI_RLAST <= M_AXI_RLAST;
S_AXI_RUSER <= M_AXI_RUSER;
S_AXI_RDATA <= M_AXI_RDATA;
S_AXI_RRESP <= M_AXI_RRESP;
S_AXI_RVALID <= M_AXI_RVALID;
M_AXI_RREADY <= S_AXI_RREADY;
END GENERATE grdch_pass_through;
gaxis_pass_through: IF (C_AXIS_TYPE = 2) GENERATE -- Wiring logic for AXI Streaming
M_AXIS_TDATA <= S_AXIS_TDATA;
M_AXIS_TSTRB <= S_AXIS_TSTRB;
M_AXIS_TKEEP <= S_AXIS_TKEEP;
M_AXIS_TID <= S_AXIS_TID;
M_AXIS_TDEST <= S_AXIS_TDEST;
M_AXIS_TUSER <= S_AXIS_TUSER;
M_AXIS_TLAST <= S_AXIS_TLAST;
S_AXIS_TREADY <= M_AXIS_TREADY;
M_AXIS_TVALID <= S_AXIS_TVALID;
END GENERATE gaxis_pass_through;
END GENERATE gaxi_pass_through;
END behavioral;
|
bsd-3-clause
|
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/usb2device_v1_0/src/axi_dma_0/axi_datamover_v5_1_9/hdl/src/vhdl/axi_datamover_dre_mux2_1_x_n.vhd
|
18
|
5142
|
-------------------------------------------------------------------------------
-- axi_datamover_dre_mux2_1_x_n.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_dre_mux2_1_x_n.vhd
--
-- Description:
--
-- This VHDL file provides a 2 to 1 xn bit wide mux for the AXI Data Realignment
-- Engine (DRE).
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use ieee.STD_LOGIC_UNSIGNED.all;
use ieee.std_logic_arith.all;
-------------------------------------------------------------------------------
-- Start 2 to 1 xN Mux
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
Entity axi_datamover_dre_mux2_1_x_n is
generic (
C_WIDTH : Integer := 8
-- Sets the bit width of the 2x Mux slice
);
port (
Sel : In std_logic;
-- Mux select control
I0 : In std_logic_vector(C_WIDTH-1 downto 0);
-- Select 0 input
I1 : In std_logic_vector(C_WIDTH-1 downto 0);
-- Select 1 inputl
Y : Out std_logic_vector(C_WIDTH-1 downto 0)
-- Mux output value
);
end entity axi_datamover_dre_mux2_1_x_n; --
Architecture implementation of axi_datamover_dre_mux2_1_x_n is
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: SELECT2_1
--
-- Process Description:
-- This process implements an 2 to 1 mux.
--
-------------------------------------------------------------
SELECT2_1 : process (Sel, I0, I1)
begin
case Sel is
when '0' =>
Y <= I0;
when '1' =>
Y <= I1;
when others =>
Y <= I0;
end case;
end process SELECT2_1;
end implementation; -- axi_datamover_dre_mux2_1_x_n
-------------------------------------------------------------------------------
-- End 2 to 1 xN Mux
-------------------------------------------------------------------------------
|
bsd-3-clause
|
AEW2015/PYNQ_PR_Overlay
|
Pynq-Z1/vivado/ip/axi_i2s_adi_1.2/hdl/axi_i2s_adi_v1_2.vhd
|
2
|
13948
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library axi_i2s_adi_v1_00_a;
use axi_i2s_adi_v1_00_a.i2s_controller;
library adi_common_v1_00_a;
use adi_common_v1_00_a.axi_streaming_dma_rx_fifo;
use adi_common_v1_00_a.axi_streaming_dma_tx_fifo;
use adi_common_v1_00_a.pl330_dma_fifo;
use adi_common_v1_00_a.axi_ctrlif;
entity axi_i2s_adi_v1_2 is
generic (
-- Users to add parameters here
C_SLOT_WIDTH : integer := 24;
C_LRCLK_POL : integer := 0; -- LRCLK Polarity (0 - Falling edge, 1 - Rising edge)
C_BCLK_POL : integer := 0; -- BCLK Polarity (0 - Falling edge, 1 - Rising edge)
C_DMA_TYPE : integer := 0;
C_NUM_CH : integer := 1;
C_HAS_TX : integer := 1;
C_HAS_RX : integer := 1;
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Parameters of Axi Slave Bus Interface S00_AXI
C_S00_AXI_DATA_WIDTH : integer := 32;
C_S00_AXI_ADDR_WIDTH : integer := 6
);
port (
-- Users to add ports here
-- Serial Data interface
DATA_CLK_I : in std_logic;
BCLK_O : out std_logic_vector(C_NUM_CH - 1 downto 0);
LRCLK_O : out std_logic_vector(C_NUM_CH - 1 downto 0);
SDATA_O : out std_logic_vector(C_NUM_CH - 1 downto 0);
SDATA_I : in std_logic_vector(C_NUM_CH - 1 downto 0);
MUTEN_O : out std_logic;
-- AXI Streaming DMA TX interface
S_AXIS_ACLK : in std_logic;
S_AXIS_TREADY : out std_logic;
S_AXIS_TDATA : in std_logic_vector(31 downto 0);
S_AXIS_TLAST : in std_logic;
S_AXIS_TVALID : in std_logic;
-- AXI Streaming DMA RX interface
M_AXIS_ACLK : in std_logic;
M_AXIS_TREADY : in std_logic;
M_AXIS_TDATA : out std_logic_vector(31 downto 0);
M_AXIS_TLAST : out std_logic;
M_AXIS_TVALID : out std_logic;
M_AXIS_TKEEP : out std_logic_vector(3 downto 0);
--PL330 DMA TX interface
DMA_REQ_TX_ACLK : in std_logic;
DMA_REQ_TX_RSTN : in std_logic;
DMA_REQ_TX_DAVALID : in std_logic;
DMA_REQ_TX_DATYPE : in std_logic_vector(1 downto 0);
DMA_REQ_TX_DAREADY : out std_logic;
DMA_REQ_TX_DRVALID : out std_logic;
DMA_REQ_TX_DRTYPE : out std_logic_vector(1 downto 0);
DMA_REQ_TX_DRLAST : out std_logic;
DMA_REQ_TX_DRREADY : in std_logic;
-- PL330 DMA RX interface
DMA_REQ_RX_ACLK : in std_logic;
DMA_REQ_RX_RSTN : in std_logic;
DMA_REQ_RX_DAVALID : in std_logic;
DMA_REQ_RX_DATYPE : in std_logic_vector(1 downto 0);
DMA_REQ_RX_DAREADY : out std_logic;
DMA_REQ_RX_DRVALID : out std_logic;
DMA_REQ_RX_DRTYPE : out std_logic_vector(1 downto 0);
DMA_REQ_RX_DRLAST : out std_logic;
DMA_REQ_RX_DRREADY : in std_logic;
-- User ports ends
-- Do not modify the ports beyond this line
-- Ports of Axi Slave Bus Interface S00_AXI
s00_axi_aclk : in std_logic;
s00_axi_aresetn : in std_logic;
s00_axi_awaddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
s00_axi_awprot : in std_logic_vector(2 downto 0);
s00_axi_awvalid : in std_logic;
s00_axi_awready : out std_logic;
s00_axi_wdata : in std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
s00_axi_wstrb : in std_logic_vector((C_S00_AXI_DATA_WIDTH/8)-1 downto 0);
s00_axi_wvalid : in std_logic;
s00_axi_wready : out std_logic;
s00_axi_bresp : out std_logic_vector(1 downto 0);
s00_axi_bvalid : out std_logic;
s00_axi_bready : in std_logic;
s00_axi_araddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
s00_axi_arprot : in std_logic_vector(2 downto 0);
s00_axi_arvalid : in std_logic;
s00_axi_arready : out std_logic;
s00_axi_rdata : out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
s00_axi_rresp : out std_logic_vector(1 downto 0);
s00_axi_rvalid : out std_logic;
s00_axi_rready : in std_logic
);
end axi_i2s_adi_v1_2;
architecture arch_imp of axi_i2s_adi_v1_2 is
-- component declaration
component axi_i2s_adi_S_AXI is
generic (
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 6
);
port (
rd_addr : out integer range 0 to 12 - 1;
rd_data : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
rd_ack : out std_logic;
wr_addr : out integer range 0 to 12 - 1;
wr_data : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
wr_stb : out std_logic;
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic
);
end component axi_i2s_adi_S_AXI;
signal i2s_reset : std_logic;
signal tx_fifo_reset : std_logic;
signal tx_enable : Boolean;
signal tx_data : std_logic_vector(C_SLOT_WIDTH - 1 downto 0);
signal tx_ack : std_logic;
signal tx_stb : std_logic;
signal tx_fifo_full : std_logic;
signal tx_fifo_empty : std_logic;
signal tx_in_ack : std_logic;
signal rx_enable : Boolean;
signal rx_fifo_reset : std_logic;
signal rx_data : std_logic_vector(C_SLOT_WIDTH - 1 downto 0);
signal rx_ack : std_logic;
signal rx_stb : std_logic;
signal rx_fifo_full : std_logic;
signal rx_fifo_empty : std_logic;
signal rx_out_stb : std_logic;
signal bclk_div_rate : natural range 0 to 255;
signal lrclk_div_rate : natural range 0 to 255;
signal period_len : integer range 0 to 65535;
signal I2S_RESET_REG : std_logic_vector(31 downto 0);
signal I2S_CONTROL_REG : std_logic_vector(31 downto 0);
signal I2S_CLK_CONTROL_REG : std_logic_vector(31 downto 0);
signal PERIOD_LEN_REG : std_logic_vector(31 downto 0);
constant FIFO_AWIDTH : integer := integer(ceil(log2(real(C_NUM_CH * 8))));
-- Audio samples FIFO
constant RAM_ADDR_WIDTH : integer := 7;
type RAM_TYPE is array (0 to (2**RAM_ADDR_WIDTH - 1)) of std_logic_vector(31 downto 0);
-- RX FIFO signals
signal audio_fifo_rx : RAM_TYPE;
signal audio_fifo_rx_wr_addr : integer range 0 to 2**RAM_ADDR_WIDTH-1;
signal audio_fifo_rx_rd_addr : integer range 0 to 2**RAM_ADDR_WIDTH-1;
signal tvalid : std_logic := '0';
signal rx_tlast : std_logic;
signal drain_tx_dma : std_logic;
signal rx_sample : std_logic_vector(23 downto 0);
signal wr_data : std_logic_vector(31 downto 0);
signal rd_data : std_logic_vector(31 downto 0);
signal wr_addr : integer range 0 to 11;
signal rd_addr : integer range 0 to 11;
signal wr_stb : std_logic;
signal rd_ack : std_logic;
signal tx_fifo_stb : std_logic;
signal rx_fifo_ack : std_logic;
signal cnt : integer range 0 to 2**16-1;
begin
-- Instantiation of Axi Bus Interface S00_AXI
axi_i2s_adi_S_AXI_inst : axi_i2s_adi_S_AXI
generic map (
C_S_AXI_DATA_WIDTH => C_S00_AXI_DATA_WIDTH,
C_S_AXI_ADDR_WIDTH => C_S00_AXI_ADDR_WIDTH
)
port map (
rd_addr => rd_addr,
rd_data => rd_data,
rd_ack => rd_ack,
wr_addr => wr_addr,
wr_data => wr_data,
wr_stb => wr_stb,
S_AXI_ACLK => s00_axi_aclk,
S_AXI_ARESETN => s00_axi_aresetn,
S_AXI_AWADDR => s00_axi_awaddr,
S_AXI_AWPROT => s00_axi_awprot,
S_AXI_AWVALID => s00_axi_awvalid,
S_AXI_AWREADY => s00_axi_awready,
S_AXI_WDATA => s00_axi_wdata,
S_AXI_WSTRB => s00_axi_wstrb,
S_AXI_WVALID => s00_axi_wvalid,
S_AXI_WREADY => s00_axi_wready,
S_AXI_BRESP => s00_axi_bresp,
S_AXI_BVALID => s00_axi_bvalid,
S_AXI_BREADY => s00_axi_bready,
S_AXI_ARADDR => s00_axi_araddr,
S_AXI_ARPROT => s00_axi_arprot,
S_AXI_ARVALID => s00_axi_arvalid,
S_AXI_ARREADY => s00_axi_arready,
S_AXI_RDATA => s00_axi_rdata,
S_AXI_RRESP => s00_axi_rresp,
S_AXI_RVALID => s00_axi_rvalid,
S_AXI_RREADY => s00_axi_rready
);
-- Add user logic here
process (s00_axi_aclk)
begin
if rising_edge(s00_axi_aclk) then
if s00_axi_aresetn = '0' then
cnt <= 0;
else
cnt <= (cnt + 1) mod 2**16;
end if;
end if;
end process;
streaming_dma_tx_gen: if C_DMA_TYPE = 0 and C_HAS_TX = 1 generate
tx_fifo : entity axi_streaming_dma_tx_fifo
generic map(
RAM_ADDR_WIDTH => FIFO_AWIDTH,
FIFO_DWIDTH => 24
)
port map(
clk => s00_axi_aclk,
resetn => s00_axi_aresetn,
fifo_reset => tx_fifo_reset,
enable => tx_enable,
S_AXIS_ACLK => S_AXIS_ACLK,
S_AXIS_TREADY => S_AXIS_TREADY,
S_AXIS_TDATA => S_AXIS_TDATA(31 downto 8),
S_AXIS_TLAST => S_AXIS_TLAST,
S_AXIS_TVALID => S_AXIS_TVALID,
out_stb => tx_stb,
out_ack => tx_ack,
out_data => tx_data
);
end generate;
streaming_dma_rx_gen: if C_DMA_TYPE = 0 and C_HAS_RX = 1 generate
rx_fifo : entity axi_streaming_dma_rx_fifo
generic map(
RAM_ADDR_WIDTH => FIFO_AWIDTH,
FIFO_DWIDTH => 24
)
port map(
clk => s00_axi_aclk,
resetn => s00_axi_aresetn,
fifo_reset => tx_fifo_reset,
enable => tx_enable,
period_len => period_len,
in_stb => rx_stb,
in_ack => rx_ack,
in_data => rx_data,
M_AXIS_ACLK => M_AXIS_ACLK,
M_AXIS_TREADY => M_AXIS_TREADY,
M_AXIS_TDATA => M_AXIS_TDATA(31 downto 8),
M_AXIS_TLAST => M_AXIS_TLAST,
M_AXIS_TVALID => M_AXIS_TVALID,
M_AXIS_TKEEP => M_AXIS_TKEEP
);
M_AXIS_TDATA(7 downto 0) <= (others => '0');
end generate;
pl330_dma_tx_gen: if C_DMA_TYPE = 1 and C_HAS_TX = 1 generate
tx_fifo_stb <= '1' when wr_addr = 11 and wr_stb = '1' else '0';
tx_fifo: entity pl330_dma_fifo
generic map(
RAM_ADDR_WIDTH => FIFO_AWIDTH,
FIFO_DWIDTH => 24,
FIFO_DIRECTION => 0
)
port map (
clk => s00_axi_aclk,
resetn => s00_axi_aresetn,
fifo_reset => tx_fifo_reset,
enable => tx_enable,
in_data => wr_data(31 downto 8),
in_stb => tx_fifo_stb,
in_ack => tx_in_ack,
out_ack => tx_ack,
out_stb => tx_stb,
out_data => tx_data,
dclk => DMA_REQ_TX_ACLK,
dresetn => DMA_REQ_TX_RSTN,
davalid => DMA_REQ_TX_DAVALID,
daready => DMA_REQ_TX_DAREADY,
datype => DMA_REQ_TX_DATYPE,
drvalid => DMA_REQ_TX_DRVALID,
drready => DMA_REQ_TX_DRREADY,
drtype => DMA_REQ_TX_DRTYPE,
drlast => DMA_REQ_TX_DRLAST
);
end generate;
pl330_dma_rx_gen: if C_DMA_TYPE = 1 and C_HAS_RX = 1 generate
rx_fifo_ack <= '1' when rd_addr = 10 and rd_ack = '1' else '0';
rx_fifo: entity pl330_dma_fifo
generic map(
RAM_ADDR_WIDTH => FIFO_AWIDTH,
FIFO_DWIDTH => 24,
FIFO_DIRECTION => 1
)
port map (
clk => s00_axi_aclk,
resetn => s00_axi_aresetn,
fifo_reset => rx_fifo_reset,
enable => rx_enable,
in_ack => rx_ack,
in_stb => rx_stb,
in_data => rx_data,
out_data => rx_sample,
out_ack => rx_fifo_ack,
out_stb => rx_out_stb,
dclk => DMA_REQ_RX_ACLK,
dresetn => DMA_REQ_RX_RSTN,
davalid => DMA_REQ_RX_DAVALID,
daready => DMA_REQ_RX_DAREADY,
datype => DMA_REQ_RX_DATYPE,
drvalid => DMA_REQ_RX_DRVALID,
drready => DMA_REQ_RX_DRREADY,
drtype => DMA_REQ_RX_DRTYPE,
drlast => DMA_REQ_RX_DRLAST
);
end generate;
ctrl : entity i2s_controller
generic map (
C_SLOT_WIDTH => C_SLOT_WIDTH,
C_BCLK_POL => C_BCLK_POL,
C_LRCLK_POL => C_LRCLK_POL,
C_NUM_CH => C_NUM_CH,
C_HAS_TX => C_HAS_TX,
C_HAS_RX => C_HAS_RX
)
port map (
clk => s00_axi_aclk,
resetn => s00_axi_aresetn,
data_clk => DATA_CLK_I,
BCLK_O => BCLK_O,
LRCLK_O => LRCLK_O,
SDATA_O => SDATA_O,
SDATA_I => SDATA_I,
tx_enable => tx_enable,
tx_ack => tx_ack,
tx_stb => tx_stb,
tx_data => tx_data,
rx_enable => rx_enable,
rx_ack => rx_ack,
rx_stb => rx_stb,
rx_data => rx_data,
bclk_div_rate => bclk_div_rate,
lrclk_div_rate => lrclk_div_rate
);
tx_fifo_full <= not(tx_in_ack);
tx_fifo_empty <= not(tx_stb);
rx_fifo_full <= not(rx_ack);
rx_fifo_empty <= not(rx_out_stb);
i2s_reset <= I2S_RESET_REG(0);
tx_fifo_reset <= I2S_RESET_REG(1);
rx_fifo_reset <= I2S_RESET_REG(2);
tx_enable <= I2S_CONTROL_REG(0) = '1';
rx_enable <= I2S_CONTROL_REG(1) = '1';
MUTEN_O <= not(I2S_CONTROL_REG(2));
bclk_div_rate <= to_integer(unsigned(I2S_CLK_CONTROL_REG(7 downto 0)));
lrclk_div_rate <= to_integer(unsigned(I2S_CLK_CONTROL_REG(23 downto 16)));
period_len <= to_integer(unsigned(PERIOD_LEN_REG(15 downto 0)));
process(rd_addr)
begin
case rd_addr is
when 1 => rd_data <= I2S_CONTROL_REG and x"00000007";
when 2 => rd_data <= I2S_CLK_CONTROL_REG and x"00ff00ff";
when 6 => rd_data <= PERIOD_LEN_REG and x"0000ffff";
when 8 => rd_data <= x"0000000" & rx_fifo_full & rx_fifo_empty & tx_fifo_full & tx_fifo_empty;
when 10 => rd_data <= rx_sample & std_logic_vector(to_unsigned(cnt, 8));
when others => rd_data <= (others => '0');
end case;
end process;
process(s00_axi_aclk) is
begin
if rising_edge(s00_axi_aclk) then
if s00_axi_aresetn = '0' then
I2S_RESET_REG <= (others => '0');
I2S_CONTROL_REG <= (others => '0');
I2S_CLK_CONTROL_REG <= (others => '0');
PERIOD_LEN_REG <= (others => '0');
else
-- Auto-clear the Reset Register bits
I2S_RESET_REG(0) <= '0';
I2S_RESET_REG(1) <= '0';
I2S_RESET_REG(2) <= '0';
if wr_stb = '1' then
case wr_addr is
when 0 => I2S_RESET_REG <= wr_data;
when 1 => I2S_CONTROL_REG <= wr_data;
when 2 => I2S_CLK_CONTROL_REG <= wr_data;
when 6 => PERIOD_LEN_REG <= wr_data;
when others => null;
end case;
end if;
end if;
end if;
end process;
-- User logic ends
end arch_imp;
|
bsd-3-clause
|
2947721120/ACE
|
demo/kitchen-sink/docs/vhdl.vhd
|
472
|
830
|
library IEEE
user IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity COUNT16 is
port (
cOut :out std_logic_vector(15 downto 0); -- counter output
clkEn :in std_logic; -- count enable
clk :in std_logic; -- clock input
rst :in std_logic -- reset input
);
end entity;
architecture count_rtl of COUNT16 is
signal count :std_logic_vector (15 downto 0);
begin
process (clk, rst) begin
if(rst = '1') then
count <= (others=>'0');
elsif(rising_edge(clk)) then
if(clkEn = '1') then
count <= count + 1;
end if;
end if;
end process;
cOut <= count;
end architecture;
|
bsd-3-clause
|
ymei/TMSPlane
|
Firmware/src/ten_gig_eth/TE07412C1/fifo/ten_gig_eth_mac_0_fifo_ram.vhd
|
3
|
5184
|
----------------------------------------------------------------------------
-- Title : FIFO BRAM
-- Project : Ten Gigabit Ethernet MAC core
----------------------------------------------------------------------------
-- File : fifo_ram.vhd
-- Author : Xilinx, Inc.
----------------------------------------------------------------------------
-- Description: BRAM used by tx and rx FIFOs
-------------------------------------------------------------------------------
-- (c) Copyright 2004-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity ten_gig_eth_mac_0_fifo_ram is
generic (
ADDR_WIDTH : integer := 9);
port (
wr_clk : in std_logic;
wr_addr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
data_in : in std_logic_vector(63 downto 0);
ctrl_in : in std_logic_vector(3 downto 0);
wr_allow : in std_logic;
rd_clk : in std_logic;
rd_sreset : in std_logic;
rd_addr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
data_out : out std_logic_vector(63 downto 0);
ctrl_out : out std_logic_vector(3 downto 0);
rd_allow : in std_logic);
end ten_gig_eth_mac_0_fifo_ram;
library ieee;
use ieee.numeric_std.all;
architecture rtl of ten_gig_eth_mac_0_fifo_ram is
constant RAM_DEPTH : integer := 2 ** ADDR_WIDTH;
type ram_typ is array (RAM_DEPTH-1 downto 0)
of std_logic_vector(67 downto 0);
signal ram : ram_typ;
signal wr_data : std_logic_vector(67 downto 0);
signal rd_data : std_logic_vector(67 downto 0);
signal rd_addr_int, wr_addr_int : unsigned(ADDR_WIDTH-1 downto 0);
signal rd_allow_int : std_logic;
attribute ram_style : string;
attribute ram_style of ram : signal is "block";
begin
wr_data(63 downto 0) <= data_in;
wr_data(67 downto 64) <= ctrl_in;
data_out <= rd_data(63 downto 0);
ctrl_out <= rd_data(67 downto 64);
-- Type conversion to allow RAM indexing to work
rd_addr_int <= unsigned(rd_addr);
wr_addr_int <= unsigned(wr_addr);
--Block RAM must be enabled for synchronous reset to work.
rd_allow_int <= rd_allow or rd_sreset;
------------------------------------------------------------------------
-- Infer BRAMs and connect them
-- appropriately.
------------------------------------------------------------------------
p_write_ram : process (wr_clk)
begin
if rising_edge(wr_clk) then
if wr_allow = '1' then
ram(TO_INTEGER(wr_addr_int)) <= wr_data;
end if;
end if;
end process p_write_ram;
p_read_ram : process (rd_clk)
begin
if rising_edge(rd_clk) then
if rd_allow_int = '1' then
if rd_sreset = '1' then
rd_data <= (others => '0');
else
rd_data <= ram(TO_INTEGER(rd_addr_int));
end if;
end if;
end if;
end process p_read_ram;
end rtl;
|
bsd-3-clause
|
ymei/TMSPlane
|
Firmware/src/uartio.vhd
|
2
|
6348
|
-- Modified based on Eric Bainville, Mar 2013
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE ieee.math_real.ALL;
ENTITY uartio IS
GENERIC (
-- tick repetition frequency is (input freq) / (2**COUNTER_WIDTH / DIVISOR)
COUNTER_WIDTH : positive := 16;
DIVISOR : positive := 1208
);
PORT (
CLK : IN std_logic; -- clock
RESET : IN std_logic; -- reset
-- Client interface
RX_DATA : OUT std_logic_vector(7 DOWNTO 0); -- received byte
RX_RDY : OUT std_logic; -- validates received byte (1 system clock spike)
TX_DATA : IN std_logic_vector(7 DOWNTO 0); -- byte to send
TX_EN : IN std_logic; -- validates byte to send if tx_rdy is '1'
TX_RDY : OUT std_logic; -- if '1', we can send a new byte, otherwise we won't take it
-- Physical interface
RX_PIN : IN std_logic;
TX_PIN : OUT std_logic
);
END uartio;
ARCHITECTURE Behavioral OF uartio IS
COMPONENT tickgen
GENERIC (
-- tick repetition frequency is (input freq) / (2**COUNTER_WIDTH / DIVISOR)
COUNTER_WIDTH : positive;
DIVISOR : positive
);
PORT (
CLK : IN std_logic;
RESET : IN std_logic;
TICK : OUT std_logic;
TICK1CLK : OUT std_logic
);
END COMPONENT;
-- CONSTANT COUNTER_BITS : natural := integer(ceil(log2(real(DIVISOR))));
TYPE fsm_state_t IS (idle, active); -- common to both RX and TX FSM
TYPE rx_state_t IS
RECORD
fsm_state : fsm_state_t; -- FSM state
counter : unsigned(3 DOWNTO 0); -- tick count
bits : std_logic_vector(7 DOWNTO 0); -- received bits
nbits : unsigned(3 DOWNTO 0); -- number of received bits (includes start bit)
enable : std_logic; -- signal we received a new byte
END RECORD;
TYPE tx_state_t IS
RECORD
fsm_state : fsm_state_t; -- FSM state
counter : unsigned(3 DOWNTO 0); -- tick count
bits : std_logic_vector(8 DOWNTO 0); -- bits to emit, includes start bit
nbits : unsigned(3 DOWNTO 0); -- number of bits left to send
ready : std_logic; -- signal we are accepting a new byte
END RECORD;
SIGNAL rx_state, rx_state_next : rx_state_t;
SIGNAL tx_state, tx_state_next : tx_state_t;
SIGNAL sample : std_logic; -- 1 clk spike at 16x baud rate
BEGIN
tickgen_inst : tickgen
GENERIC MAP (
-- tick repetition frequency is (input freq) / (2**COUNTER_WIDTH / DIVISOR)
COUNTER_WIDTH => COUNTER_WIDTH,
DIVISOR => DIVISOR
)
PORT MAP (
CLK => CLK,
RESET => RESET,
TICK => OPEN,
TICK1CLK => sample
);
-- RX, TX state registers update at each CLK, and RESET
reg_process : PROCESS (CLK, RESET) IS
BEGIN
IF RESET = '1' THEN
rx_state.fsm_state <= idle;
rx_state.bits <= (OTHERS => '0');
rx_state.nbits <= (OTHERS => '0');
rx_state.enable <= '0';
tx_state.fsm_state <= idle;
tx_state.bits <= (OTHERS => '1');
tx_state.nbits <= (OTHERS => '0');
tx_state.ready <= '1';
ELSIF rising_edge(CLK) THEN
rx_state <= rx_state_next;
tx_state <= tx_state_next;
END IF;
END PROCESS;
-- RX FSM
rx_process : PROCESS (rx_state, sample, RX_PIN) IS
BEGIN
CASE rx_state.fsm_state IS
WHEN idle =>
rx_state_next.counter <= (OTHERS => '0');
rx_state_next.bits <= (OTHERS => '0');
rx_state_next.nbits <= (OTHERS => '0');
rx_state_next.enable <= '0';
IF RX_PIN = '0' THEN
-- start a new byte
rx_state_next.fsm_state <= active;
ELSE
-- keep idle
rx_state_next.fsm_state <= idle;
END IF;
WHEN active =>
rx_state_next <= rx_state;
IF sample = '1' THEN
IF rx_state.counter = 8 THEN
-- sample next RX bit (at the middle of the counter cycle)
IF rx_state.nbits = 9 THEN
rx_state_next.fsm_state <= idle; -- back to idle state to wait for next start bit
rx_state_next.enable <= RX_PIN; -- OK if stop bit is '1'
ELSE
rx_state_next.bits <= RX_PIN & rx_state.bits(7 DOWNTO 1);
rx_state_next.nbits <= rx_state.nbits + 1;
END IF;
END IF;
rx_state_next.counter <= rx_state.counter + 1;
END IF;
END CASE;
END PROCESS;
-- RX output
rx_output : PROCESS (rx_state) IS
BEGIN
RX_DATA <= rx_state.bits;
RX_RDY <= rx_state.enable;
END PROCESS;
-- TX FSM
tx_process : PROCESS (tx_state, sample, TX_EN) IS
BEGIN
CASE tx_state.fsm_state IS
WHEN idle =>
IF TX_EN = '1' THEN
-- start a new bit
tx_state_next.bits <= TX_DATA & '0'; -- data & start
tx_state_next.nbits <= x"a"; -- send 10 bits (includes '1' stop bit)
tx_state_next.counter <= (OTHERS => '0');
tx_state_next.fsm_state <= active;
tx_state_next.ready <= '0';
ELSE
-- keep idle
tx_state_next.bits <= (OTHERS => '1');
tx_state_next.nbits <= (OTHERS => '0');
tx_state_next.counter <= (OTHERS => '0');
tx_state_next.fsm_state <= idle;
tx_state_next.ready <= '1';
END IF;
WHEN active =>
tx_state_next <= tx_state;
IF sample = '1' THEN
IF tx_state.counter = 15 THEN
-- send next bit
IF tx_state.nbits = 0 THEN
-- turn idle
tx_state_next.bits <= (OTHERS => '1');
tx_state_next.nbits <= (OTHERS => '0');
tx_state_next.counter <= (OTHERS => '0');
tx_state_next.fsm_state <= idle;
tx_state_next.ready <= '1';
ELSE
tx_state_next.bits <= '1' & tx_state.bits(8 DOWNTO 1);
tx_state_next.nbits <= tx_state.nbits - 1;
END IF;
END IF;
tx_state_next.counter <= tx_state.counter + 1;
END IF;
END CASE;
END PROCESS;
-- TX output
tx_output : PROCESS (tx_state) IS
BEGIN
TX_RDY <= tx_state.ready;
TX_PIN <= tx_state.bits(0);
END PROCESS;
END Behavioral;
|
bsd-3-clause
|
ymei/TMSPlane
|
Firmware/src/gig_eth/KC705/support/tri_mode_ethernet_mac_0_support_resets.vhd
|
3
|
8683
|
--------------------------------------------------------------------------------
-- File : tri_mode_ethernet_mac_0_support_resets.vhd
-- Author : Xilinx Inc.
-- -----------------------------------------------------------------------------
-- (c) Copyright 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-- -----------------------------------------------------------------------------
-- Description: This module holds the shared resets for the IDELAYCTRL
-- and the MMCM
--------------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
entity tri_mode_ethernet_mac_0_support_resets is
port (
glbl_rstn : in std_logic;
refclk : in std_logic;
idelayctrl_ready : in std_logic;
idelayctrl_reset_out : out std_logic ;
gtx_clk : in std_logic;
gtx_dcm_locked : in std_logic;
gtx_mmcm_rst_out : out std_logic -- The reset pulse for the MMCM.
);
end tri_mode_ethernet_mac_0_support_resets;
architecture xilinx of tri_mode_ethernet_mac_0_support_resets is
------------------------------------------------------------------------------
-- Component declaration for the synchronisation flip-flop pair
------------------------------------------------------------------------------
component tri_mode_ethernet_mac_0_sync_block
port (
clk : in std_logic; -- clock to be sync'ed to
data_in : in std_logic; -- Data to be 'synced'
data_out : out std_logic -- synced data
);
end component;
------------------------------------------------------------------------------
-- Component declaration for the reset synchroniser
------------------------------------------------------------------------------
component tri_mode_ethernet_mac_0_reset_sync
port (
reset_in : in std_logic; -- Active high asynchronous reset
enable : in std_logic;
clk : in std_logic; -- clock to be sync'ed to
reset_out : out std_logic -- "Synchronised" reset signal
);
end component;
signal glbl_rst : std_logic;
signal idelayctrl_reset_in : std_logic; -- Used to trigger reset_sync generation in refclk domain.
signal idelayctrl_reset_sync : std_logic; -- Used to create a reset pulse in the IDELAYCTRL refclk domain.
signal idelay_reset_cnt : std_logic_vector(3 downto 0); -- Counter to create a long IDELAYCTRL reset pulse.
signal idelayctrl_reset : std_logic;
signal gtx_mmcm_rst_in : std_logic;
signal gtx_dcm_locked_int : std_logic;
signal gtx_dcm_locked_sync : std_logic;
signal gtx_dcm_locked_reg : std_logic := '1';
signal gtx_dcm_locked_edge : std_logic := '1';
begin
glbl_rst <= not glbl_rstn;
----------------------------------------------------------------
-- Reset circuitry associated with the IDELAYCTRL
-----------------------------------------------------------------
idelayctrl_reset_out <= idelayctrl_reset;
idelayctrl_reset_in <= glbl_rst or not idelayctrl_ready;
-- Create a synchronous reset in the IDELAYCTRL refclk clock domain.
idelayctrl_reset_gen : tri_mode_ethernet_mac_0_reset_sync
port map(
clk => refclk,
enable => '1',
reset_in => idelayctrl_reset_in,
reset_out => idelayctrl_reset_sync
);
-- Reset circuitry for the IDELAYCTRL reset.
-- The IDELAYCTRL must experience a pulse which is at least 50 ns in
-- duration. This is ten clock cycles of the 200MHz refclk. Here we
-- drive the reset pulse for 12 clock cycles.
process (refclk)
begin
if refclk'event and refclk = '1' then
if idelayctrl_reset_sync = '1' then
idelay_reset_cnt <= "0000";
idelayctrl_reset <= '1';
else
idelayctrl_reset <= '1';
case idelay_reset_cnt is
when "0000" => idelay_reset_cnt <= "0001";
when "0001" => idelay_reset_cnt <= "0010";
when "0010" => idelay_reset_cnt <= "0011";
when "0011" => idelay_reset_cnt <= "0100";
when "0100" => idelay_reset_cnt <= "0101";
when "0101" => idelay_reset_cnt <= "0110";
when "0110" => idelay_reset_cnt <= "0111";
when "0111" => idelay_reset_cnt <= "1000";
when "1000" => idelay_reset_cnt <= "1001";
when "1001" => idelay_reset_cnt <= "1010";
when "1010" => idelay_reset_cnt <= "1011";
when "1011" => idelay_reset_cnt <= "1100";
when "1100" => idelay_reset_cnt <= "1101";
when "1101" => idelay_reset_cnt <= "1110";
when others => idelay_reset_cnt <= "1110";
idelayctrl_reset <= '0';
end case;
end if;
end if;
end process;
----------------------------------------------------------------
-- Reset circuitry associated with the MMCM
----------------------------------------------------------------
gtx_mmcm_rst_in <= glbl_rst or gtx_dcm_locked_edge;
-- Synchronise the async dcm_locked into the gtx_clk clock domain
lock_sync : tri_mode_ethernet_mac_0_sync_block
port map (
clk => gtx_clk,
data_in => gtx_dcm_locked,
data_out => gtx_dcm_locked_sync
);
-- for the falling edge detect we want to force this at power on so init the flop to 1
gtx_dcm_lock_detect : process(gtx_clk)
begin
if gtx_clk'event and gtx_clk = '1' then
gtx_dcm_locked_reg <= gtx_dcm_locked_sync;
gtx_dcm_locked_edge <= gtx_dcm_locked_reg and not gtx_dcm_locked_sync;
end if;
end process gtx_dcm_lock_detect;
-- the MMCM reset should be at least 5ns - that is one cycle of the input clock -
-- since the source of the input reset is unknown (a push switch in board design)
-- this needs to be debounced
gtx_mmcm_reset_gen : tri_mode_ethernet_mac_0_reset_sync
port map (
clk => gtx_clk,
enable => '1',
reset_in => gtx_mmcm_rst_in,
reset_out => gtx_mmcm_rst_out
);
end xilinx;
|
bsd-3-clause
|
ymei/TMSPlane
|
Firmware/src/ten_gig_eth/TE07412C1/pcs_pma/ten_gig_eth_pcs_pma_0_gt_common.vhd
|
3
|
10216
|
-------------------------------------------------------------------------------
-- Title : GT Common wrapper
-- Project : 10GBASE-R
-------------------------------------------------------------------------------
-- File : ten_gig_eth_pcs_pma_0_gt_common.vhd
-------------------------------------------------------------------------------
-- Description: This file contains the
-- 10GBASE-R Transceiver GT Common block.
-------------------------------------------------------------------------------
-- (c) Copyright 2009 - 2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ten_gig_eth_pcs_pma_0_gt_common is
generic
(
WRAPPER_SIM_GTRESET_SPEEDUP : string := "false" --Does not affect hardware
);
port
(
refclk : in std_logic;
qpllreset : in std_logic;
qplllock : out std_logic;
qplloutclk : out std_logic;
qplloutrefclk : out std_logic
);
end entity ten_gig_eth_pcs_pma_0_gt_common;
architecture wrapper of ten_gig_eth_pcs_pma_0_gt_common is
-- ground and tied_to_vcc_i signals
signal tied_to_ground_i : std_logic;
signal tied_to_ground_vec_i : std_logic_vector(63 downto 0);
signal tied_to_vcc_i : std_logic;
-- List of signals to connect to GT Common block
signal gt0_gtrefclk0_common_in : std_logic;
signal gt0_qpllreset_in : std_logic;
signal gt0_qplllock_out : std_logic;
signal gt0_qplloutclk_i : std_logic;
signal gt0_qplloutrefclk_i : std_logic;
--*************************Logic to set Attribute QPLL_FB_DIV*****************************
impure function conv_qpll_fbdiv_top (qpllfbdiv_top : in integer) return bit_vector is
begin
if (qpllfbdiv_top = 16) then
return "0000100000";
elsif (qpllfbdiv_top = 20) then
return "0000110000" ;
elsif (qpllfbdiv_top = 32) then
return "0001100000" ;
elsif (qpllfbdiv_top = 40) then
return "0010000000" ;
elsif (qpllfbdiv_top = 64) then
return "0011100000" ;
elsif (qpllfbdiv_top = 66) then
return "0101000000" ;
elsif (qpllfbdiv_top = 80) then
return "0100100000" ;
elsif (qpllfbdiv_top = 100) then
return "0101110000" ;
else
return "0000000000" ;
end if;
end function;
impure function conv_qpll_fbdiv_ratio (qpllfbdiv_top : in integer) return bit is
begin
if (qpllfbdiv_top = 16) then
return '1';
elsif (qpllfbdiv_top = 20) then
return '1' ;
elsif (qpllfbdiv_top = 32) then
return '1' ;
elsif (qpllfbdiv_top = 40) then
return '1' ;
elsif (qpllfbdiv_top = 64) then
return '1' ;
elsif (qpllfbdiv_top = 66) then
return '0' ;
elsif (qpllfbdiv_top = 80) then
return '1' ;
elsif (qpllfbdiv_top = 100) then
return '1' ;
else
return '1' ;
end if;
end function;
constant QPLL_FBDIV_TOP : integer := 66;
constant QPLL_FBDIV_IN : bit_vector(9 downto 0) := conv_qpll_fbdiv_top(QPLL_FBDIV_TOP);
constant QPLL_FBDIV_RATIO : bit := conv_qpll_fbdiv_ratio(QPLL_FBDIV_TOP);
begin
tied_to_ground_i <= '0';
tied_to_ground_vec_i(63 downto 0) <= (others => '0');
tied_to_vcc_i <= '1';
gt0_gtrefclk0_common_in <= refclk;
gt0_qpllreset_in <= qpllreset;
qplllock <= gt0_qplllock_out;
qplloutclk <= gt0_qplloutclk_i;
qplloutrefclk <= gt0_qplloutrefclk_i;
gtxe2_common_0_i : GTXE2_COMMON
generic map
(
-- Simulation attributes
SIM_RESET_SPEEDUP => WRAPPER_SIM_GTRESET_SPEEDUP,
SIM_QPLLREFCLK_SEL => ("001"),
SIM_VERSION => "4.0",
------------------COMMON BLOCK Attributes---------------
BIAS_CFG => (x"0000040000001000"),
COMMON_CFG => (x"00000000"),
QPLL_CFG => (x"0680181"),
QPLL_CLKOUT_CFG => ("0000"),
QPLL_COARSE_FREQ_OVRD => ("010000"),
QPLL_COARSE_FREQ_OVRD_EN => ('0'),
QPLL_CP => ("0000011111"),
QPLL_CP_MONITOR_EN => ('0'),
QPLL_DMONITOR_SEL => ('0'),
QPLL_FBDIV => (QPLL_FBDIV_IN),
QPLL_FBDIV_MONITOR_EN => ('0'),
QPLL_FBDIV_RATIO => (QPLL_FBDIV_RATIO),
QPLL_INIT_CFG => (x"000006"),
QPLL_LOCK_CFG => (x"21E8"),
QPLL_LPF => ("1111"),
QPLL_REFCLK_DIV => (1)
)
port map
(
------------- Common Block - Dynamic Reconfiguration Port (DRP) -----------
DRPADDR => tied_to_ground_vec_i(7 downto 0),
DRPCLK => tied_to_ground_i,
DRPDI => tied_to_ground_vec_i(15 downto 0),
DRPDO => open,
DRPEN => tied_to_ground_i,
DRPRDY => open,
DRPWE => tied_to_ground_i,
---------------------- Common Block - Ref Clock Ports ---------------------
GTGREFCLK => tied_to_ground_i,
GTNORTHREFCLK0 => tied_to_ground_i,
GTNORTHREFCLK1 => tied_to_ground_i,
GTREFCLK0 => gt0_gtrefclk0_common_in,
GTREFCLK1 => tied_to_ground_i,
GTSOUTHREFCLK0 => tied_to_ground_i,
GTSOUTHREFCLK1 => tied_to_ground_i,
----------------------- Common Block - Clocking Ports ----------------------
QPLLOUTCLK => gt0_qplloutclk_i,
QPLLOUTREFCLK => gt0_qplloutrefclk_i,
REFCLKOUTMONITOR => open,
------------------------- Common Block - QPLL Ports ------------------------
QPLLDMONITOR => open,
QPLLFBCLKLOST => open,
QPLLLOCK => gt0_qplllock_out,
QPLLLOCKDETCLK => '0',
QPLLLOCKEN => tied_to_vcc_i,
QPLLOUTRESET => tied_to_ground_i,
QPLLPD => tied_to_ground_i,
QPLLREFCLKLOST => open,
QPLLREFCLKSEL => "001",
QPLLRESET => gt0_qpllreset_in,
QPLLRSVD1 => "0000000000000000",
QPLLRSVD2 => "11111",
--------------------------------- QPLL Ports -------------------------------
BGBYPASSB => tied_to_vcc_i,
BGMONITORENB => tied_to_vcc_i,
BGPDB => tied_to_vcc_i,
BGRCALOVRD => "11111",
PMARSVD => "00000000",
RCALENB => tied_to_vcc_i
);
end wrapper;
|
bsd-3-clause
|
ymei/TMSPlane
|
Firmware/src/top_TMS1mmX19_KC705.vhd
|
1
|
67792
|
--------------------------------------------------------------------------------
--! @file top.vhd
--! @brief Toplevel module for KC705 eval board.
--! @author Yuan Mei
--!
--! Target Devices: Kintex-7 XC7K325T-FFG900-2
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
LIBRARY UNISIM;
USE UNISIM.VComponents.ALL;
LIBRARY work;
USE work.utility.ALL;
ENTITY top IS
GENERIC (
ENABLE_DEBUG : boolean := false;
ENABLE_GIG_ETH : boolean := true;
ENABLE_TEN_GIG_ETH : boolean := false
);
PORT (
SYS_RST : IN std_logic;
SYS_CLK_P : IN std_logic;
SYS_CLK_N : IN std_logic;
USER_CLK_P : IN std_logic; --! 156.250 MHz
USER_CLK_N : IN std_logic;
SGMIICLK_Q0_P : IN std_logic; --! 125 MHz, for GTP/GTH/GTX
SGMIICLK_Q0_N : IN std_logic;
SI5324CLK_P : IN std_logic; --! programmable, for GTX ref
SI5324CLK_N : IN std_logic;
--
LED8Bit : OUT std_logic_vector(7 DOWNTO 0);
DIPSw4Bit : IN std_logic_vector(3 DOWNTO 0);
BTN5Bit : IN std_logic_vector(4 DOWNTO 0);
USER_SMA_CLOCK_P : OUT std_logic;
USER_SMA_CLOCK_N : OUT std_logic;
USER_SMA_GPIO_P : IN std_logic;
USER_SMA_GPIO_N : OUT std_logic;
SI5324_RSTn : OUT std_logic;
-- UART via usb
USB_RX : OUT std_logic;
USB_TX : IN std_logic;
-- SFP
SFP_TX_P : OUT std_logic;
SFP_TX_N : OUT std_logic;
SFP_RX_P : IN std_logic;
SFP_RX_N : IN std_logic;
SFP_LOS_LS : IN std_logic;
SFP_TX_DISABLE_N : OUT std_logic;
-- SMA MGT
SMA_MGT_TX_P : OUT std_logic;
SMA_MGT_TX_N : OUT std_logic;
SMA_MGT_RX_P : IN std_logic;
SMA_MGT_RX_N : IN std_logic;
-- Gigbit eth interface (RGMII)
PHY_RESET_N : OUT std_logic;
RGMII_TXD : OUT std_logic_vector(3 DOWNTO 0);
RGMII_TX_CTL : OUT std_logic;
RGMII_TXC : OUT std_logic;
RGMII_RXD : IN std_logic_vector(3 DOWNTO 0);
RGMII_RX_CTL : IN std_logic;
RGMII_RXC : IN std_logic;
MDIO : INOUT std_logic;
MDC : OUT std_logic;
-- SDRAM
DDR3_DQ : INOUT std_logic_vector(63 DOWNTO 0);
DDR3_DQS_P : INOUT std_logic_vector(7 DOWNTO 0);
DDR3_DQS_N : INOUT std_logic_vector(7 DOWNTO 0);
-- Outputs
DDR3_ADDR : OUT std_logic_vector(13 DOWNTO 0);
DDR3_BA : OUT std_logic_vector(2 DOWNTO 0);
DDR3_RAS_N : OUT std_logic;
DDR3_CAS_N : OUT std_logic;
DDR3_WE_N : OUT std_logic;
DDR3_RESET_N : OUT std_logic;
DDR3_CK_P : OUT std_logic_vector(0 DOWNTO 0);
DDR3_CK_N : OUT std_logic_vector(0 DOWNTO 0);
DDR3_CKE : OUT std_logic_vector(0 DOWNTO 0);
DDR3_CS_N : OUT std_logic_vector(0 DOWNTO 0);
DDR3_DM : OUT std_logic_vector(7 DOWNTO 0);
DDR3_ODT : OUT std_logic_vector(0 DOWNTO 0);
--
I2C_SCL : INOUT std_logic;
I2C_SDA : INOUT std_logic;
-- FMC HPC
FMC_HPC_HA_P :INOUT std_logic_vector(23 DOWNTO 0);
FMC_HPC_HA_N :INOUT std_logic_vector(23 DOWNTO 0);
FMC_HPC_LA_P :INOUT std_logic_vector(33 DOWNTO 0);
FMC_HPC_LA_N :INOUT std_logic_vector(33 DOWNTO 0);
-- FMC LPC
FMC_LPC_LA_P :INOUT std_logic_vector(33 DOWNTO 0);
FMC_LPC_LA_N :INOUT std_logic_vector(33 DOWNTO 0)
);
END top;
ARCHITECTURE Behavioral OF top IS
-- Components
COMPONENT global_clock_reset
PORT (
SYS_CLK_P : IN std_logic;
SYS_CLK_N : IN std_logic;
FORCE_RST : IN std_logic;
-- output
GLOBAL_RST : OUT std_logic;
SYS_CLK : OUT std_logic;
LOCKED : OUT std_logic;
CLK_OUT1 : OUT std_logic;
CLK_OUT2 : OUT std_logic;
CLK_OUT3 : OUT std_logic;
CLK_OUT4 : OUT std_logic
);
END COMPONENT;
---------------------------------------------< ten_gig_eth
COMPONENT ten_gig_eth
PORT (
REFCLK_P : IN std_logic; -- 156.25MHz for transceiver
REFCLK_N : IN std_logic;
RESET : IN std_logic;
SFP_TX_P : OUT std_logic;
SFP_TX_N : OUT std_logic;
SFP_RX_P : IN std_logic;
SFP_RX_N : IN std_logic;
SFP_LOS : IN std_logic; -- loss of receiver signal
SFP_TX_DISABLE : OUT std_logic;
-- clk156.25 domain, clock generated by the core
CLK156p25 : OUT std_logic;
PCS_PMA_CORE_STATUS : OUT std_logic_vector(7 DOWNTO 0);
TX_STATISTICS_VECTOR : OUT std_logic_vector(25 DOWNTO 0);
TX_STATISTICS_VALID : OUT std_logic;
RX_STATISTICS_VECTOR : OUT std_logic_vector(29 DOWNTO 0);
RX_STATISTICS_VALID : OUT std_logic;
PAUSE_VAL : IN std_logic_vector(15 DOWNTO 0);
PAUSE_REQ : IN std_logic;
TX_IFG_DELAY : IN std_logic_vector(7 DOWNTO 0);
-- emac control interface
S_AXI_ACLK : IN std_logic;
S_AXI_ARESETN : IN std_logic;
S_AXI_AWADDR : IN std_logic_vector(10 DOWNTO 0);
S_AXI_AWVALID : IN std_logic;
S_AXI_AWREADY : OUT std_logic;
S_AXI_WDATA : IN std_logic_vector(31 DOWNTO 0);
S_AXI_WVALID : IN std_logic;
S_AXI_WREADY : OUT std_logic;
S_AXI_BRESP : OUT std_logic_vector(1 DOWNTO 0);
S_AXI_BVALID : OUT std_logic;
S_AXI_BREADY : IN std_logic;
S_AXI_ARADDR : IN std_logic_vector(10 DOWNTO 0);
S_AXI_ARVALID : IN std_logic;
S_AXI_ARREADY : OUT std_logic;
S_AXI_RDATA : OUT std_logic_vector(31 DOWNTO 0);
S_AXI_RRESP : OUT std_logic_vector(1 DOWNTO 0);
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic;
-- tx_wr_clk domain
TX_AXIS_FIFO_ARESETN : IN std_logic;
TX_AXIS_FIFO_ACLK : IN std_logic;
TX_AXIS_FIFO_TDATA : IN std_logic_vector(63 DOWNTO 0);
TX_AXIS_FIFO_TKEEP : IN std_logic_vector(7 DOWNTO 0);
TX_AXIS_FIFO_TVALID : IN std_logic;
TX_AXIS_FIFO_TLAST : IN std_logic;
TX_AXIS_FIFO_TREADY : OUT std_logic;
-- rx_rd_clk domain
RX_AXIS_FIFO_ARESETN : IN std_logic;
RX_AXIS_FIFO_ACLK : IN std_logic;
RX_AXIS_FIFO_TDATA : OUT std_logic_vector(63 DOWNTO 0);
RX_AXIS_FIFO_TKEEP : OUT std_logic_vector(7 DOWNTO 0);
RX_AXIS_FIFO_TVALID : OUT std_logic;
RX_AXIS_FIFO_TLAST : OUT std_logic;
RX_AXIS_FIFO_TREADY : IN std_logic
);
END COMPONENT;
COMPONENT ten_gig_eth_packet_gen
PORT (
RESET : IN std_logic;
MEM_CLK : IN std_logic;
MEM_WE : IN std_logic; -- memory write enable
MEM_ADDR : IN std_logic_vector(31 DOWNTO 0);
MEM_D : IN std_logic_vector(31 DOWNTO 0); -- memory data
--
TX_AXIS_ACLK : IN std_logic;
TX_START : IN std_logic;
TX_BYTES : IN std_logic_vector(15 DOWNTO 0); -- number of bytes to send
TX_AXIS_TDATA : OUT std_logic_vector(63 DOWNTO 0);
TX_AXIS_TKEEP : OUT std_logic_vector(7 DOWNTO 0);
TX_AXIS_TVALID : OUT std_logic;
TX_AXIS_TLAST : OUT std_logic;
TX_AXIS_TREADY : IN std_logic
);
END COMPONENT;
COMPONENT ten_gig_eth_rx_parser
PORT (
RESET : IN std_logic;
RX_AXIS_FIFO_ARESETN : OUT std_logic;
-- Everything internal to this module is synchronous to this clock `ACLK'
RX_AXIS_FIFO_ACLK : IN std_logic;
RX_AXIS_FIFO_TDATA : IN std_logic_vector(63 DOWNTO 0);
RX_AXIS_FIFO_TKEEP : IN std_logic_vector(7 DOWNTO 0);
RX_AXIS_FIFO_TVALID : IN std_logic;
RX_AXIS_FIFO_TLAST : IN std_logic;
RX_AXIS_FIFO_TREADY : OUT std_logic;
-- Constants
SRC_MAC : IN std_logic_vector(47 DOWNTO 0);
SRC_IP : IN std_logic_vector(31 DOWNTO 0);
SRC_PORT : IN std_logic_vector(15 DOWNTO 0);
-- Command output fifo interface AFTER parsing the packet
-- dstMAC(48) dstIP(32) dstPort(16) opcode(32)
CMD_FIFO_Q : OUT std_logic_vector(127 DOWNTO 0);
CMD_FIFO_EMPTY : OUT std_logic;
CMD_FIFO_RDREQ : IN std_logic;
CMD_FIFO_RDCLK : IN std_logic
);
END COMPONENT;
---------------------------------------------> ten_gig_eth
---------------------------------------------< gtx / aurora
COMPONENT aurora_64b66b
PORT (
RESET : IN std_logic;
SYS_CLK : IN std_logic;
MGT_REFCLK_P : IN std_logic;
MGT_REFCLK_N : IN std_logic;
-- Data interfaces are synchronous to USER_CLK
USER_CLK : OUT std_logic;
MGT_REFCLK_BUFG_OUT : OUT std_logic;
-- TX AXI4 interface
S_AXI_TX_TDATA : IN std_logic_vector(0 TO 63);
S_AXI_TX_TVALID : IN std_logic;
S_AXI_TX_TREADY : OUT std_logic;
-- RX AXI4 interface
M_AXI_RX_TDATA : OUT std_logic_vector(0 TO 63);
M_AXI_RX_TVALID : OUT std_logic;
-- User flow control (UFC) TX
UFC_TX_REQ : IN std_logic;
S_AXI_UFC_TX_TDATA : IN std_logic_vector(0 TO 63);
UFC_TX_MS : IN std_logic_vector(0 TO 7);
S_AXI_UFC_TX_TVALID : IN std_logic;
S_AXI_UFC_TX_TREADY : OUT std_logic;
-- UFC RX
M_AXI_UFC_RX_TDATA : OUT std_logic_vector(0 TO 63);
M_AXI_UFC_RX_TKEEP : OUT std_logic_vector(0 TO 7);
M_AXI_UFC_RX_TLAST : OUT std_logic;
M_AXI_UFC_RX_TVALID : OUT std_logic;
UFC_IN_PROGRESSn : OUT std_logic;
-- GTX pins
RXP : IN std_logic;
RXN : IN std_logic;
TXP : OUT std_logic;
TXN : OUT std_logic;
-- Status
STATUS : OUT std_logic_vector(15 DOWNTO 0)
);
END COMPONENT;
COMPONENT fifo_over_ufc
GENERIC (
FIFO_DATA_WIDTH : positive := 32;
AURORA_DATA_WIDTH : positive := 64
);
PORT (
RESET : IN std_logic;
AURORA_USER_CLK : IN std_logic;
AURORA_TX_REQ : OUT std_logic;
AURORA_TX_MS : OUT std_logic_vector(7 DOWNTO 0);
AURORA_TX_TREADY : IN std_logic;
AURORA_TX_TDATA : OUT std_logic_vector(AURORA_DATA_WIDTH-1 DOWNTO 0);
AURORA_TX_TVALID : OUT std_logic;
AURORA_RX_TDATA : IN std_logic_vector(AURORA_DATA_WIDTH-1 DOWNTO 0);
AURORA_RX_TVALID : IN std_logic;
FIFO_CLK : OUT std_logic;
TX_FIFO_Q : OUT std_logic_vector(FIFO_DATA_WIDTH-1 DOWNTO 0);
TX_FIFO_WREN : OUT std_logic;
TX_FIFO_FULL : IN std_logic;
RX_FIFO_Q : IN std_logic_vector(FIFO_DATA_WIDTH-1 DOWNTO 0);
RX_FIFO_RDEN : OUT std_logic;
RX_FIFO_EMPTY : IN std_logic;
ERR : OUT std_logic
);
END COMPONENT;
---------------------------------------------> gtx / aurora
---------------------------------------------< gig_eth
COMPONENT gig_eth
PORT (
-- asynchronous reset
GLBL_RST : IN std_logic;
-- clocks
GTX_CLK : IN std_logic; -- 125MHz
REF_CLK : IN std_logic; -- 200MHz for IODELAY
-- PHY interface
PHY_RESETN : OUT std_logic;
-- RGMII Interface
RGMII_TXD : OUT std_logic_vector(3 DOWNTO 0);
RGMII_TX_CTL : OUT std_logic;
RGMII_TXC : OUT std_logic;
RGMII_RXD : IN std_logic_vector(3 DOWNTO 0);
RGMII_RX_CTL : IN std_logic;
RGMII_RXC : IN std_logic;
-- MDIO Interface
MDIO : INOUT std_logic;
MDC : OUT std_logic;
-- TCP
MAC_ADDR : IN std_logic_vector(47 DOWNTO 0);
IPv4_ADDR : IN std_logic_vector(31 DOWNTO 0);
IPv6_ADDR : IN std_logic_vector(127 DOWNTO 0);
SUBNET_MASK : IN std_logic_vector(31 DOWNTO 0);
GATEWAY_IP_ADDR : IN std_logic_vector(31 DOWNTO 0);
TCP_CONNECTION_RESET : IN std_logic;
TX_TDATA : IN std_logic_vector(7 DOWNTO 0);
TX_TVALID : IN std_logic;
TX_TREADY : OUT std_logic;
RX_TDATA : OUT std_logic_vector(7 DOWNTO 0);
RX_TVALID : OUT std_logic;
RX_TREADY : IN std_logic;
-- FIFO
TCP_USE_FIFO : IN std_logic;
TX_FIFO_WRCLK : IN std_logic;
TX_FIFO_Q : IN std_logic_vector(31 DOWNTO 0);
TX_FIFO_WREN : IN std_logic;
TX_FIFO_FULL : OUT std_logic;
RX_FIFO_RDCLK : IN std_logic;
RX_FIFO_Q : OUT std_logic_vector(31 DOWNTO 0);
RX_FIFO_RDEN : IN std_logic;
RX_FIFO_EMPTY : OUT std_logic;
--
TX_FIFO1_WRCLK : IN std_logic;
TX_FIFO1_Q : IN std_logic_vector(31 downto 0);
TX_FIFO1_WREN : IN std_logic;
TX_FIFO1_FULL : OUT std_logic;
RX_FIFO1_RDCLK : IN std_logic;
RX_FIFO1_Q : OUT std_logic_vector(31 downto 0);
RX_FIFO1_RDEN : IN std_logic;
RX_FIFO1_EMPTY : OUT std_logic
);
END COMPONENT;
---------------------------------------------> gig_eth
---------------------------------------------< UART/RS232
COMPONENT control_interface
PORT (
RESET : IN std_logic;
CLK : IN std_logic; -- system clock
-- From FPGA to PC
FIFO_Q : OUT std_logic_vector(35 DOWNTO 0); -- interface fifo data output port
FIFO_EMPTY : OUT std_logic; -- interface fifo "emtpy" signal
FIFO_RDREQ : IN std_logic; -- interface fifo read request
FIFO_RDCLK : IN std_logic; -- interface fifo read clock
-- From PC to FPGA, FWFT
CMD_FIFO_Q : IN std_logic_vector(35 DOWNTO 0); -- interface command fifo data out port
CMD_FIFO_EMPTY : IN std_logic; -- interface command fifo "emtpy" signal
CMD_FIFO_RDREQ : OUT std_logic; -- interface command fifo read request
-- Digital I/O
CONFIG_REG : OUT std_logic_vector(511 DOWNTO 0); -- thirtytwo 16bit registers
PULSE_REG : OUT std_logic_vector(15 DOWNTO 0); -- 16bit pulse register
STATUS_REG : IN std_logic_vector(175 DOWNTO 0); -- eleven 16bit registers
-- Memory interface
MEM_WE : OUT std_logic; -- memory write enable
MEM_ADDR : OUT std_logic_vector(31 DOWNTO 0);
MEM_DIN : OUT std_logic_vector(31 DOWNTO 0); -- memory data input
MEM_DOUT : IN std_logic_vector(31 DOWNTO 0); -- memory data output
-- Data FIFO interface, FWFT
DATA_FIFO_Q : IN std_logic_vector(31 DOWNTO 0);
DATA_FIFO_EMPTY : IN std_logic;
DATA_FIFO_RDREQ : OUT std_logic;
DATA_FIFO_RDCLK : OUT std_logic
);
END COMPONENT;
COMPONENT data_sampler_fifo
GENERIC (
DIN_WIDTH : positive := 512;
DOUT_WIDTH : positive := 32
);
PORT (
RESET : IN std_logic;
CLK : IN std_logic;
TRIG : IN std_logic;
DIN : IN std_logic_vector(DIN_WIDTH-1 DOWNTO 0);
DIN_VALID : IN std_logic;
DIN_CLK : IN std_logic;
DOUT : OUT std_logic_vector(DOUT_WIDTH-1 DOWNTO 0);
DOUT_EMPTY : OUT std_logic;
DOUT_RDEN : IN std_logic
);
END COMPONENT;
---------------------------------------------> UART/RS232
---------------------------------------------< SDRAM
COMPONENT sdram_ddr3
GENERIC (
INDATA_WIDTH : positive := 256;
OUTDATA_WIDTH : positive := 32;
APP_ADDR_WIDTH : positive := 28;
APP_DATA_WIDTH : positive := 512;
APP_MASK_WIDTH : positive := 64;
APP_ADDR_BURST : positive := 8
);
PORT (
CLK : IN std_logic; -- system clock, must be the same as intended in MIG
REFCLK : IN std_logic; -- 200MHz for iodelay
RESET : IN std_logic;
-- SDRAM_DDR3
-- Inouts
DDR3_DQ : INOUT std_logic_vector(63 DOWNTO 0);
DDR3_DQS_P : INOUT std_logic_vector(7 DOWNTO 0);
DDR3_DQS_N : INOUT std_logic_vector(7 DOWNTO 0);
-- Outputs
DDR3_ADDR : OUT std_logic_vector(13 DOWNTO 0);
DDR3_BA : OUT std_logic_vector(2 DOWNTO 0);
DDR3_RAS_N : OUT std_logic;
DDR3_CAS_N : OUT std_logic;
DDR3_WE_N : OUT std_logic;
DDR3_RESET_N : OUT std_logic;
DDR3_CK_P : OUT std_logic_vector(0 DOWNTO 0);
DDR3_CK_N : OUT std_logic_vector(0 DOWNTO 0);
DDR3_CKE : OUT std_logic_vector(0 DOWNTO 0);
DDR3_CS_N : OUT std_logic_vector(0 DOWNTO 0);
DDR3_DM : OUT std_logic_vector(7 DOWNTO 0);
DDR3_ODT : OUT std_logic_vector(0 DOWNTO 0);
-- Status Outputs
INIT_CALIB_COMPLETE : OUT std_logic;
-- Internal data r/w interface
UI_CLK : OUT std_logic;
--
CTRL_RESET : IN std_logic;
WR_START : IN std_logic;
WR_ADDR_BEGIN : IN std_logic_vector(APP_ADDR_WIDTH-1 DOWNTO 0);
WR_STOP : IN std_logic;
WR_WRAP_AROUND : IN std_logic;
POST_TRIGGER : IN std_logic_vector(APP_ADDR_WIDTH-1 DOWNTO 0);
WR_BUSY : OUT std_logic;
WR_POINTER : OUT std_logic_vector(APP_ADDR_WIDTH-1 DOWNTO 0);
TRIGGER_POINTER : OUT std_logic_vector(APP_ADDR_WIDTH-1 DOWNTO 0);
WR_WRAPPED : OUT std_logic;
RD_START : IN std_logic;
RD_ADDR_BEGIN : IN std_logic_vector(APP_ADDR_WIDTH-1 DOWNTO 0);
RD_ADDR_END : IN std_logic_vector(APP_ADDR_WIDTH-1 DOWNTO 0);
RD_BUSY : OUT std_logic;
--
DATA_FIFO_RESET : IN std_logic;
INDATA_FIFO_WRCLK : IN std_logic;
INDATA_FIFO_Q : IN std_logic_vector(INDATA_WIDTH-1 DOWNTO 0);
INDATA_FIFO_FULL : OUT std_logic;
INDATA_FIFO_WREN : IN std_logic;
--
OUTDATA_FIFO_RDCLK : IN std_logic;
OUTDATA_FIFO_Q : OUT std_logic_vector(OUTDATA_WIDTH-1 DOWNTO 0);
OUTDATA_FIFO_EMPTY : OUT std_logic;
OUTDATA_FIFO_RDEN : IN std_logic;
--
DBG_APP_ADDR : OUT std_logic_vector(APP_ADDR_WIDTH-1 DOWNTO 0);
DBG_APP_EN : OUT std_logic;
DBG_APP_RDY : OUT std_logic;
DBG_APP_WDF_DATA : OUT std_logic_vector(APP_DATA_WIDTH-1 DOWNTO 0);
DBG_APP_WDF_END : OUT std_logic;
DBG_APP_WDF_WREN : OUT std_logic;
DBG_APP_WDF_RDY : OUT std_logic;
DBG_APP_RD_DATA : OUT std_logic_vector(APP_DATA_WIDTH-1 DOWNTO 0);
DBG_APP_RD_DATA_VALID : OUT std_logic
);
END COMPONENT;
---------------------------------------------> SDRAM
---------------------------------------------< I2C
COMPONENT i2c_write_regmap
GENERIC (
REGMAP_FNAME : string;
INPUT_CLK_FREQENCY : integer := 100_000_000;
-- BUS CLK freqency should be divided by multiples of 4 from input frequency
BUS_CLK_FREQUENCY : integer := 100_000;
START_DELAY_CYCLE : integer := 100_000_000; -- ext_rst to happen # of clk cycles after START
EXT_RST_WIDTH_CYCLE : integer := 1000; -- pulse width of ext_rst in clk cycles
EXT_RST_DELAY_CYCLE : integer := 100_000 -- 1st reg write to happen clk cycles after ext_rst
);
PORT (
CLK : IN std_logic; -- system clock 50Mhz
RESET : IN std_logic; -- active high reset
START : IN std_logic; -- rising edge triggers r/w; synchronous to CLK
EXT_RSTn : OUT std_logic; -- active low for resetting the slave
BUSY : OUT std_logic; -- indicates transaction in progress
ACK_ERROR : OUT std_logic; -- i2c has unexpected ack
SDA_in : IN std_logic; -- serial data input from i2c bus
SDA_out : OUT std_logic; -- serial data output to i2c bus
SDA_t : OUT std_logic; -- serial data direction to/from i2c bus, '1' is read-in
SCL : OUT std_logic -- serial clock output to i2c bus
);
END COMPONENT;
---------------------------------------------> I2C
---------------------------------------------< TMS
COMPONENT sdm_adc_data_aurora_recv
GENERIC (
NCH_ADC : positive := 20;
ADC_CYC : positive := 20;
NCH_SDM : positive := 19;
SDM_CYC : positive := 4
);
PORT (
RESET : IN std_logic;
CLK : IN std_logic;
USER_CLK : IN std_logic;
M_AXI_RX_TDATA : IN std_logic_vector(63 DOWNTO 0);
M_AXI_RX_TVALID : IN std_logic;
DOUT : OUT std_logic_vector(511 DOWNTO 0);
DOUT_VALID : OUT std_logic;
FIFO_FULL : OUT std_logic
);
END COMPONENT;
---------------------------------------------> TMS
---------------------------------------------< debug : ILA and VIO (`Chipscope')
COMPONENT dbg_ila
PORT (
CLK : IN std_logic;
PROBE0 : IN std_logic_vector(63 DOWNTO 0);
PROBE1 : IN std_logic_vector(79 DOWNTO 0);
PROBE2 : IN std_logic_vector(79 DOWNTO 0);
PROBE3 : IN std_logic_vector(2047 DOWNTO 0)
);
END COMPONENT;
COMPONENT dbg_ila1
PORT (
CLK : IN std_logic;
PROBE0 : IN std_logic_vector(15 DOWNTO 0);
PROBE1 : IN std_logic_vector(15 DOWNTO 0)
);
END COMPONENT;
COMPONENT dbg_vio
PORT (
CLK : IN std_logic;
PROBE_IN0 : IN std_logic_vector(63 DOWNTO 0);
PROBE_IN1 : IN std_logic_vector(63 DOWNTO 0);
PROBE_IN2 : IN std_logic_vector(63 DOWNTO 0);
PROBE_IN3 : IN std_logic_vector(63 DOWNTO 0);
PROBE_IN4 : IN std_logic_vector(63 DOWNTO 0);
PROBE_IN5 : IN std_logic_vector(63 DOWNTO 0);
PROBE_IN6 : IN std_logic_vector(63 DOWNTO 0);
PROBE_IN7 : IN std_logic_vector(63 DOWNTO 0);
PROBE_IN8 : IN std_logic_vector(35 DOWNTO 0);
PROBE_OUT0 : OUT std_logic_vector(63 DOWNTO 0)
);
END COMPONENT;
---------------------------------------------> debug : ILA and VIO (`Chipscope')
-- Signals
SIGNAL reset : std_logic;
SIGNAL sys_clk : std_logic;
SIGNAL global_clk_locked : std_logic;
SIGNAL clk_50MHz : std_logic;
SIGNAL clk_100MHz : std_logic;
SIGNAL clk_125MHz : std_logic;
SIGNAL clk_200MHz : std_logic;
SIGNAL clk_250MHz : std_logic;
SIGNAL clk_sgmii_i : std_logic;
SIGNAL clk_sgmii : std_logic;
SIGNAL clk156p25 : std_logic;
SIGNAL clk_user : std_logic;
---------------------------------------------< UART/RS232
SIGNAL uart_rx_data : std_logic_vector(7 DOWNTO 0);
SIGNAL uart_rx_rdy : std_logic;
SIGNAL control_clk : std_logic;
SIGNAL control_fifo_q : std_logic_vector(35 DOWNTO 0);
SIGNAL control_fifo_rdreq : std_logic;
SIGNAL control_fifo_empty : std_logic;
SIGNAL control_fifo_rdclk : std_logic;
SIGNAL cmd_fifo_q : std_logic_vector(35 DOWNTO 0);
SIGNAL cmd_fifo_empty : std_logic;
SIGNAL cmd_fifo_rdreq : std_logic;
-- thirtytwo 16bit registers
SIGNAL config_reg : std_logic_vector(511 DOWNTO 0);
-- 16bit pulse register
SIGNAL pulse_reg : std_logic_vector(15 DOWNTO 0);
-- eleven 16bit registers
SIGNAL status_reg : std_logic_vector(175 DOWNTO 0) := (OTHERS => '0');
SIGNAL control_mem_we : std_logic;
SIGNAL control_mem_addr : std_logic_vector(31 DOWNTO 0);
SIGNAL control_mem_din : std_logic_vector(31 DOWNTO 0);
SIGNAL control_data_fifo_q : std_logic_vector(31 DOWNTO 0);
SIGNAL control_data_fifo_empty : std_logic;
SIGNAL control_data_fifo_rdreq : std_logic;
SIGNAL control_data_fifo_rdclk : std_logic;
SIGNAL control_data_fifo_reset : std_logic;
---------------------------------------------> UART/RS232
---------------------------------------------< gtx / aurora
SIGNAL aurora_reset : std_logic;
SIGNAL aurora_status : std_logic_vector(15 DOWNTO 0);
SIGNAL aurora_user_clk : std_logic;
SIGNAL aurora_ufc_tx_req : std_logic;
SIGNAL aurora_ufc_tx_tdata : std_logic_vector(63 DOWNTO 0);
SIGNAL aurora_ufc_tx_ms : std_logic_vector(7 DOWNTO 0);
SIGNAL aurora_ufc_tx_tvalid : std_logic;
SIGNAL aurora_ufc_tx_tready : std_logic;
SIGNAL aurora_ufc_rx_tdata : std_logic_vector(63 DOWNTO 0);
SIGNAL aurora_ufc_rx_tkeep : std_logic_vector(7 DOWNTO 0);
SIGNAL aurora_ufc_rx_tlast : std_logic;
SIGNAL aurora_ufc_rx_tvalid : std_logic;
SIGNAL aurora_ufc_in_progress_n : std_logic;
SIGNAL aurora_tx_tdata : std_logic_vector(63 DOWNTO 0);
SIGNAL aurora_tx_tvalid : std_logic;
SIGNAL aurora_tx_tready : std_logic;
SIGNAL aurora_rx_tdata : std_logic_vector(63 DOWNTO 0);
SIGNAL aurora_rx_tvalid : std_logic;
---------------------------------------------> gtx / aurora
---------------------------------------------< ten_gig_eth
SIGNAL sfp_tx_disable_i : std_logic;
SIGNAL sPcs_pma_core_status : std_logic_vector(7 DOWNTO 0);
SIGNAL sEmac_status_vector : std_logic_vector(1 DOWNTO 0);
SIGNAL sTx_axis_fifo_aresetn : std_logic;
SIGNAL sTx_axis_fifo_aclk : std_logic;
SIGNAL sTx_axis_fifo_tdata : std_logic_vector(63 DOWNTO 0);
SIGNAL sTx_axis_fifo_tkeep : std_logic_vector(7 DOWNTO 0);
SIGNAL sTx_axis_fifo_tvalid : std_logic;
SIGNAL sTx_axis_fifo_tlast : std_logic;
SIGNAL sTx_axis_fifo_tready : std_logic;
SIGNAL sRx_axis_fifo_aresetn : std_logic;
SIGNAL sRx_axis_fifo_aclk : std_logic;
SIGNAL sRx_axis_fifo_tdata : std_logic_vector(63 DOWNTO 0);
SIGNAL sRx_axis_fifo_tkeep : std_logic_vector(7 DOWNTO 0);
SIGNAL sRx_axis_fifo_tvalid : std_logic;
SIGNAL sRx_axis_fifo_tlast : std_logic;
SIGNAL sRx_axis_fifo_tready : std_logic;
-- control interface
SIGNAL s_axi_aclk : std_logic;
SIGNAL s_axi_aresetn : std_logic;
SIGNAL s_axi_awaddr : std_logic_vector(10 DOWNTO 0);
SIGNAL s_axi_awvalid : std_logic;
SIGNAL s_axi_awready : std_logic;
SIGNAL s_axi_wdata : std_logic_vector(31 DOWNTO 0);
SIGNAL s_axi_wvalid : std_logic;
SIGNAL s_axi_wready : std_logic;
SIGNAL s_axi_bresp : std_logic_vector(1 DOWNTO 0);
SIGNAL s_axi_bvalid : std_logic;
SIGNAL s_axi_bready : std_logic;
SIGNAL s_axi_araddr : std_logic_vector(10 DOWNTO 0);
SIGNAL s_axi_arvalid : std_logic;
SIGNAL s_axi_arready : std_logic;
SIGNAL s_axi_rdata : std_logic_vector(31 DOWNTO 0);
SIGNAL s_axi_rresp : std_logic_vector(1 DOWNTO 0);
SIGNAL s_axi_rvalid : std_logic;
SIGNAL s_axi_rready : std_logic;
-- packets
SIGNAL ten_gig_eth_tx_start : std_logic;
SIGNAL tge_cmd_fifo_q : std_logic_vector(127 DOWNTO 0);
SIGNAL tge_cmd_fifo_empty : std_logic;
SIGNAL tge_cmd_fifo_rdreq : std_logic;
---------------------------------------------> ten_gig_eth
SIGNAL usr_data_output : std_logic_vector (7 DOWNTO 0);
---------------------------------------------< gig_eth
SIGNAL gig_eth_mac_addr : std_logic_vector(47 DOWNTO 0);
SIGNAL gig_eth_ipv4_addr : std_logic_vector(31 DOWNTO 0);
SIGNAL gig_eth_subnet_mask : std_logic_vector(31 DOWNTO 0);
SIGNAL gig_eth_gateway_ip_addr : std_logic_vector(31 DOWNTO 0);
SIGNAL gig_eth_tx_tdata : std_logic_vector(7 DOWNTO 0);
SIGNAL gig_eth_tx_tvalid : std_logic;
SIGNAL gig_eth_tx_tready : std_logic;
SIGNAL gig_eth_rx_tdata : std_logic_vector(7 DOWNTO 0);
SIGNAL gig_eth_rx_tvalid : std_logic;
SIGNAL gig_eth_rx_tready : std_logic;
SIGNAL gig_eth_tcp_use_fifo : std_logic;
SIGNAL gig_eth_tx_fifo_wrclk : std_logic;
SIGNAL gig_eth_tx_fifo_q : std_logic_vector(31 DOWNTO 0);
SIGNAL gig_eth_tx_fifo_wren : std_logic;
SIGNAL gig_eth_tx_fifo_full : std_logic;
SIGNAL gig_eth_rx_fifo_rdclk : std_logic;
SIGNAL gig_eth_rx_fifo_q : std_logic_vector(31 DOWNTO 0);
SIGNAL gig_eth_rx_fifo_rden : std_logic;
SIGNAL gig_eth_rx_fifo_empty : std_logic;
SIGNAL gig_eth_tx_fifo1_wrclk : std_logic;
SIGNAL gig_eth_tx_fifo1_q : std_logic_vector(31 DOWNTO 0);
SIGNAL gig_eth_tx_fifo1_wren : std_logic;
SIGNAL gig_eth_tx_fifo1_full : std_logic;
SIGNAL gig_eth_rx_fifo1_rdclk : std_logic;
SIGNAL gig_eth_rx_fifo1_q : std_logic_vector(31 DOWNTO 0);
SIGNAL gig_eth_rx_fifo1_rden : std_logic;
SIGNAL gig_eth_rx_fifo1_empty : std_logic;
---------------------------------------------> gig_eth
---------------------------------------------< SDRAM
SIGNAL sdram_app_addr : std_logic_vector(28-1 DOWNTO 0);
SIGNAL sdram_app_en : std_logic;
SIGNAL sdram_app_rdy : std_logic;
SIGNAL sdram_app_wdf_data : std_logic_vector(512-1 DOWNTO 0);
SIGNAL sdram_app_wdf_end : std_logic;
SIGNAL sdram_app_wdf_wren : std_logic;
SIGNAL sdram_app_wdf_rdy : std_logic;
SIGNAL sdram_app_rd_data : std_logic_vector(512-1 DOWNTO 0);
SIGNAL sdram_app_rd_data_valid : std_logic;
---------------------------------------------> SDRAM
---------------------------------------------< IDATA
SIGNAL TRIG_OUT_0 : std_logic;
SIGNAL idata_cmd_out : std_logic_vector(63 DOWNTO 0);
SIGNAL idata_cmd_out_val : std_logic;
SIGNAL idata_cmd_in : std_logic_vector(63 DOWNTO 0);
SIGNAL idata_cmd_in_val : std_logic;
SIGNAL idata_adc_data_clk : std_logic;
SIGNAL idata_adc_refout_clkdiv : std_logic;
SIGNAL idata_adc_data0 : std_logic_vector(15 DOWNTO 0);
SIGNAL idata_adc_data1 : std_logic_vector(15 DOWNTO 0);
SIGNAL idata_adc_data2 : std_logic_vector(15 DOWNTO 0);
SIGNAL idata_adc_data3 : std_logic_vector(15 DOWNTO 0);
SIGNAL idata_adc_data4 : std_logic_vector(15 DOWNTO 0);
SIGNAL idata_adc_data5 : std_logic_vector(15 DOWNTO 0);
SIGNAL idata_adc_data6 : std_logic_vector(15 DOWNTO 0);
SIGNAL idata_adc_data7 : std_logic_vector(15 DOWNTO 0);
SIGNAL idata_adc_data8 : std_logic_vector(15 DOWNTO 0);
SIGNAL idata_adc_data9 : std_logic_vector(15 DOWNTO 0);
SIGNAL idata_adc_data10 : std_logic_vector(15 DOWNTO 0);
SIGNAL idata_adc_data11 : std_logic_vector(15 DOWNTO 0);
SIGNAL idata_data_fifo_reset : std_logic;
SIGNAL idata_data_fifo_rdclk : std_logic;
SIGNAL idata_data_fifo_din : std_logic_vector(255 DOWNTO 0);
SIGNAL idata_channel_avg_outdata_q : std_logic_vector(255 DOWNTO 0);
SIGNAL idata_channel_avg_outvalid : std_logic;
SIGNAL idata_data_fifo_wren : std_logic;
SIGNAL idata_data_fifo_rden : std_logic;
SIGNAL idata_data_fifo_dout : std_logic_vector(31 DOWNTO 0);
SIGNAL idata_data_fifo_full : std_logic;
SIGNAL idata_data_fifo_empty : std_logic;
SIGNAL idata_idata_fifo_q : std_logic_vector(255 DOWNTO 0);
SIGNAL idata_idata_fifo_wren : std_logic;
SIGNAL idata_idata_fifo_rden : std_logic;
SIGNAL idata_idata_fifo_full : std_logic;
SIGNAL idata_idata_fifo_empty : std_logic;
SIGNAL idata_trig_allow : std_logic;
SIGNAL idata_trig_in : std_logic;
SIGNAL idata_trig_synced : std_logic;
SIGNAL idata_data_wr_start : std_logic;
SIGNAL idata_data_wr_busy : std_logic;
SIGNAL idata_data_wr_wrapped : std_logic;
---------------------------------------------> IDATA
---------------------------------------------< I2C
SIGNAL i2c_sda_out : std_logic;
SIGNAL i2c_sda_in : std_logic;
SIGNAL i2c_sda_t : std_logic;
SIGNAL i2c_scl_out : std_logic;
---------------------------------------------> I2C
---------------------------------------------< TMS
SIGNAL tms_sdm_adc_dout : std_logic_vector(511 DOWNTO 0);
SIGNAL tms_sdm_adc_dout_valid : std_logic;
---------------------------------------------< TMS
---------------------------------------------< debug
SIGNAL dbg_ila_probe0 : std_logic_vector (63 DOWNTO 0);
SIGNAL dbg_ila_probe1 : std_logic_vector (79 DOWNTO 0);
SIGNAL dbg_ila_probe2 : std_logic_vector (79 DOWNTO 0);
SIGNAL dbg_ila_probe3 : std_logic_vector (2047 DOWNTO 0);
SIGNAL dbg_vio_probe_out0 : std_logic_vector (63 DOWNTO 0);
SIGNAL dbg_ila1_probe0 : std_logic_vector (15 DOWNTO 0);
SIGNAL dbg_ila1_probe1 : std_logic_vector (15 DOWNTO 0);
ATTRIBUTE mark_debug : string;
ATTRIBUTE keep : string;
ATTRIBUTE mark_debug OF USB_TX : SIGNAL IS "true";
ATTRIBUTE mark_debug OF uart_rx_data : SIGNAL IS "true";
ATTRIBUTE mark_debug OF uart_rx_rdy : SIGNAL IS "true";
ATTRIBUTE mark_debug OF cmd_fifo_q : SIGNAL IS "true";
ATTRIBUTE mark_debug OF cmd_fifo_empty : SIGNAL IS "true";
ATTRIBUTE mark_debug OF cmd_fifo_rdreq : SIGNAL IS "true";
ATTRIBUTE mark_debug OF config_reg : SIGNAL IS "true";
--ATTRIBUTE mark_debug OF status_reg : SIGNAL IS "true";
--ATTRIBUTE mark_debug OF pulse_reg : SIGNAL IS "true";
ATTRIBUTE mark_debug OF control_mem_we : SIGNAL IS "true";
ATTRIBUTE mark_debug OF control_mem_addr : SIGNAL IS "true";
ATTRIBUTE mark_debug OF control_mem_din : SIGNAL IS "true";
--
ATTRIBUTE mark_debug OF sPcs_pma_core_status : SIGNAL IS "true";
ATTRIBUTE mark_debug OF sEmac_status_vector : SIGNAL IS "true";
ATTRIBUTE mark_debug OF sTx_axis_fifo_aresetn : SIGNAL IS "true";
ATTRIBUTE mark_debug OF sTx_axis_fifo_aclk : SIGNAL IS "true";
ATTRIBUTE mark_debug OF sTx_axis_fifo_tdata : SIGNAL IS "true";
ATTRIBUTE mark_debug OF sTx_axis_fifo_tkeep : SIGNAL IS "true";
ATTRIBUTE mark_debug OF sTx_axis_fifo_tvalid : SIGNAL IS "true";
ATTRIBUTE mark_debug OF sTx_axis_fifo_tlast : SIGNAL IS "true";
ATTRIBUTE mark_debug OF sTx_axis_fifo_tready : SIGNAL IS "true";
ATTRIBUTE mark_debug OF sRx_axis_fifo_aresetn : SIGNAL IS "true";
ATTRIBUTE mark_debug OF sRx_axis_fifo_aclk : SIGNAL IS "true";
ATTRIBUTE mark_debug OF sRx_axis_fifo_tdata : SIGNAL IS "true";
ATTRIBUTE mark_debug OF sRx_axis_fifo_tkeep : SIGNAL IS "true";
ATTRIBUTE mark_debug OF sRx_axis_fifo_tvalid : SIGNAL IS "true";
ATTRIBUTE mark_debug OF sRx_axis_fifo_tlast : SIGNAL IS "true";
ATTRIBUTE mark_debug OF sRx_axis_fifo_tready : SIGNAL IS "true";
--ATTRIBUTE mark_debug OF ten_gig_eth_tx_start : SIGNAL IS "true";
ATTRIBUTE mark_debug OF tge_cmd_fifo_q : SIGNAL IS "true";
ATTRIBUTE mark_debug OF tge_cmd_fifo_empty : SIGNAL IS "true";
ATTRIBUTE mark_debug OF tge_cmd_fifo_rdreq : SIGNAL IS "true";
--
ATTRIBUTE mark_debug OF gig_eth_tx_tdata : SIGNAL IS "true";
ATTRIBUTE mark_debug OF gig_eth_tx_tvalid : SIGNAL IS "true";
ATTRIBUTE mark_debug OF gig_eth_tx_tready : SIGNAL IS "true";
ATTRIBUTE mark_debug OF gig_eth_rx_tdata : SIGNAL IS "true";
ATTRIBUTE mark_debug OF gig_eth_rx_tvalid : SIGNAL IS "true";
ATTRIBUTE mark_debug OF gig_eth_rx_tready : SIGNAL IS "true";
ATTRIBUTE mark_debug OF gig_eth_tx_fifo_q : SIGNAL IS "true";
ATTRIBUTE mark_debug OF gig_eth_rx_fifo_q : SIGNAL IS "true";
--
ATTRIBUTE mark_debug OF sdram_app_addr : SIGNAL IS "true";
ATTRIBUTE mark_debug OF sdram_app_en : SIGNAL IS "true";
ATTRIBUTE mark_debug OF sdram_app_rdy : SIGNAL IS "true";
ATTRIBUTE mark_debug OF sdram_app_wdf_data : SIGNAL IS "true";
ATTRIBUTE mark_debug OF sdram_app_wdf_end : SIGNAL IS "true";
ATTRIBUTE mark_debug OF sdram_app_wdf_wren : SIGNAL IS "true";
ATTRIBUTE mark_debug OF sdram_app_wdf_rdy : SIGNAL IS "true";
ATTRIBUTE mark_debug OF sdram_app_rd_data : SIGNAL IS "true";
ATTRIBUTE mark_debug OF sdram_app_rd_data_valid : SIGNAL IS "true";
---------------------------------------------> debug
BEGIN
---------------------------------------------< Clock
global_clock_reset_inst : global_clock_reset
PORT MAP (
SYS_CLK_P => SYS_CLK_P,
SYS_CLK_N => SYS_CLK_N,
FORCE_RST => SYS_RST,
-- output
GLOBAL_RST => reset,
SYS_CLK => sys_clk,
LOCKED => global_clk_locked,
CLK_OUT1 => clk_50MHz,
CLK_OUT2 => clk_100MHz,
CLK_OUT3 => OPEN,
CLK_OUT4 => clk_250MHz
);
user_clk_ibufds_inst : IBUFDS
GENERIC MAP (
DIFF_TERM => true, -- Differential Termination
IBUF_LOW_PWR => false, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "LVDS"
)
PORT MAP (
O => clk_user, -- Buffer output
I => USER_CLK_P, -- Diff_p buffer input (connect directly to top-level port)
IB => USER_CLK_N -- Diff_n buffer input (connect directly to top-level port)
);
-- gtx/gth reference clock can be used as general purpose clock this way
-- sgmiiclk_ibufds_inst : IBUFDS_GTE2
-- PORT MAP (
-- O => clk_sgmii_i,
-- ODIV2 => OPEN,
-- CEB => '0',
-- I => SGMIICLK_Q0_P,
-- IB => SGMIICLK_Q0_N
-- );
-- sgmiiclk_bufg_inst : BUFG
-- PORT MAP (
-- I => clk_sgmii_i,
-- O => clk_sgmii
-- );
clk_125MHz <= clk_sgmii;
---------------------------------------------> Clock
---------------------------------------------< debug : ILA and VIO (`Chipscope')
dbg_cores : IF ENABLE_DEBUG GENERATE
dbg_ila_inst : dbg_ila
PORT MAP (
CLK => sys_clk,
PROBE0 => dbg_ila_probe0,
PROBE1 => dbg_ila_probe1,
PROBE2 => dbg_ila_probe2,
PROBE3 => dbg_ila_probe3
);
dbg_vio_inst : dbg_vio
PORT MAP (
CLK => sys_clk,
PROBE_IN0 => config_reg(64*1-1 DOWNTO 64*0),
PROBE_IN1 => config_reg(64*2-1 DOWNTO 64*1),
PROBE_IN2 => config_reg(64*3-1 DOWNTO 64*2),
PROBE_IN3 => config_reg(64*4-1 DOWNTO 64*3),
PROBE_IN4 => config_reg(64*5-1 DOWNTO 64*4),
PROBE_IN5 => config_reg(64*6-1 DOWNTO 64*5),
PROBE_IN6 => config_reg(64*7-1 DOWNTO 64*6),
PROBE_IN7 => x"00000000000000" & sPcs_pma_core_status, -- config_reg(64*8-1 DOWNTO 64*7),
PROBE_IN8 => cmd_fifo_q,
PROBE_OUT0 => dbg_vio_probe_out0
);
--dbg_ila1_inst : dbg_ila1
-- PORT MAP (
-- CLK => sys_clk,
-- PROBE0 => dbg_ila1_probe0,
-- PROBE1 => dbg_ila1_probe1
-- );
END GENERATE dbg_cores;
---------------------------------------------> debug : ILA and VIO (`Chipscope')
---------------------------------------------< UART/RS232
uart_cores : IF false GENERATE
uartio_inst : uartio
GENERIC MAP (
-- tick repetition frequency is (input freq) / (2**COUNTER_WIDTH / DIVISOR)
COUNTER_WIDTH => 16,
DIVISOR => 1208*2
)
PORT MAP (
CLK => clk_50MHz,
RESET => reset,
RX_DATA => uart_rx_data,
RX_RDY => uart_rx_rdy,
TX_DATA => "0000" & DIPSw4Bit,
TX_EN => '1',
TX_RDY => dbg_ila_probe0(2),
-- serial lines
RX_PIN => USB_TX, -- notice the pin swap
TX_PIN => USB_RX
);
--dbg_ila1_probe0(7 DOWNTO 0) <= uart_rx_data;
--dbg_ila1_probe0(8) <= uart_rx_rdy;
--dbg_ila1_probe0(9) <= USB_TX;
-- dbg_ila_probe0(63 DOWNTO 32) <= cmd_fifo_q(31 DOWNTO 0);
dbg_ila_probe0(31) <= cmd_fifo_empty;
dbg_ila_probe0(30) <= cmd_fifo_rdreq;
byte2cmd_inst : byte2cmd
PORT MAP (
CLK => clk_50MHz,
RESET => reset,
-- byte in
RX_DATA => uart_rx_data,
RX_RDY => uart_rx_rdy,
-- cmd out
CMD_FIFO_Q => OPEN,-- cmd_fifo_q,
CMD_FIFO_EMPTY => OPEN,-- cmd_fifo_empty,
CMD_FIFO_RDCLK => control_clk,
CMD_FIFO_RDREQ => '0' -- cmd_fifo_rdreq
);
END GENERATE uart_cores;
control_clk <= clk_100MHz;
control_interface_inst : control_interface
PORT MAP (
RESET => reset,
CLK => control_clk,
-- From FPGA to PC
FIFO_Q => control_fifo_q,
FIFO_EMPTY => control_fifo_empty,
FIFO_RDREQ => control_fifo_rdreq,
FIFO_RDCLK => control_fifo_rdclk,
-- From PC to FPGA, FWFT
CMD_FIFO_Q => cmd_fifo_q,
CMD_FIFO_EMPTY => cmd_fifo_empty,
CMD_FIFO_RDREQ => cmd_fifo_rdreq,
-- Digital I/O
CONFIG_REG => config_reg,
PULSE_REG => pulse_reg,
STATUS_REG => status_reg,
-- Memory interface
MEM_WE => control_mem_we,
MEM_ADDR => control_mem_addr,
MEM_DIN => control_mem_din,
MEM_DOUT => (OTHERS => '0'),
-- Data FIFO interface, FWFT
DATA_FIFO_Q => control_data_fifo_q,
DATA_FIFO_EMPTY => control_data_fifo_empty,
DATA_FIFO_RDREQ => control_data_fifo_rdreq,
DATA_FIFO_RDCLK => control_data_fifo_rdclk
);
dbg_ila_probe0(18 DOWNTO 3) <= pulse_reg;
---------------------------------------------> UART/RS232
---------------------------------------------< ten_gig_eth
ten_gig_eth_cores : IF ENABLE_TEN_GIG_ETH GENERATE
ten_gig_eth_inst : ten_gig_eth
PORT MAP (
REFCLK_P => SI5324CLK_P, -- 156.25MHz for transceiver
REFCLK_N => SI5324CLK_N,
RESET => reset,
SFP_TX_P => SFP_TX_P,
SFP_TX_N => SFP_TX_N,
SFP_RX_P => SFP_RX_P,
SFP_RX_N => SFP_RX_N,
SFP_LOS => SFP_LOS_LS, -- loss of receiver signal
SFP_TX_DISABLE => sfp_tx_disable_i,
-- clk156.25 domain, clock generated by the core
CLK156p25 => clk156p25,
PCS_PMA_CORE_STATUS => sPcs_pma_core_status,
TX_STATISTICS_VECTOR => OPEN,
TX_STATISTICS_VALID => OPEN,
RX_STATISTICS_VECTOR => OPEN,
RX_STATISTICS_VALID => OPEN,
PAUSE_VAL => (OTHERS => '0'),
PAUSE_REQ => '0',
TX_IFG_DELAY => x"ff",
-- emac control interface
S_AXI_ACLK => s_axi_aclk,
S_AXI_ARESETN => s_axi_aresetn,
S_AXI_AWADDR => s_axi_awaddr,
S_AXI_AWVALID => s_axi_awvalid,
S_AXI_AWREADY => s_axi_awready,
S_AXI_WDATA => s_axi_wdata,
S_AXI_WVALID => s_axi_wvalid,
S_AXI_WREADY => s_axi_wready,
S_AXI_BRESP => s_axi_bresp,
S_AXI_BVALID => s_axi_bvalid,
S_AXI_BREADY => s_axi_bready,
S_AXI_ARADDR => s_axi_araddr,
S_AXI_ARVALID => s_axi_arvalid,
S_AXI_ARREADY => s_axi_arready,
S_AXI_RDATA => s_axi_rdata,
S_AXI_RRESP => s_axi_rresp,
S_AXI_RVALID => s_axi_rvalid,
S_AXI_RREADY => s_axi_rready,
-- tx_wr_clk domain
TX_AXIS_FIFO_ARESETN => sTx_axis_fifo_aresetn,
Tx_AXIS_FIFO_ACLK => sTx_axis_fifo_aclk,
TX_AXIS_FIFO_TDATA => sTx_axis_fifo_tdata,
TX_AXIS_FIFO_TKEEP => sTx_axis_fifo_tkeep,
TX_AXIS_FIFO_TVALID => sTx_axis_fifo_tvalid,
TX_AXIS_FIFO_TLAST => sTx_axis_fifo_tlast,
TX_AXIS_FIFO_TREADY => sTx_axis_fifo_tready,
-- rx_rd_clk domain
RX_AXIS_FIFO_ARESETN => sRx_axis_fifo_aresetn,
RX_AXIS_FIFO_ACLK => sRx_axis_fifo_aclk,
RX_AXIS_FIFO_TDATA => sRx_axis_fifo_tdata,
RX_AXIS_FIFO_TKEEP => sRx_axis_fifo_tkeep,
RX_AXIS_FIFO_TVALID => sRx_axis_fifo_tvalid,
RX_AXIS_FIFO_TLAST => sRx_axis_fifo_tlast,
RX_AXIS_FIFO_TREADY => sRx_axis_fifo_tready
);
SFP_TX_DISABLE_N <= NOT sfp_tx_disable_i;
LED8Bit(7) <= sPcs_pma_core_status(0);
LED8Bit(6) <= NOT sfp_tx_disable_i;
LED8Bit(5) <= NOT SFP_LOS_LS;
s_axi_aclk <= clk_50MHz;
sTx_axis_fifo_aclk <= clk_200MHz;
sRx_axis_fifo_aclk <= sTx_axis_fifo_aclk;
s_axi_aresetn <= '1';
sTx_axis_fifo_aresetn <= '1';
-- sRx_axis_fifo_aresetn <= '1';
ten_gig_eth_packet_gen_inst : ten_gig_eth_packet_gen
PORT MAP (
RESET => reset,
MEM_CLK => control_clk,
MEM_WE => control_mem_we,
MEM_ADDR => control_mem_addr,
MEM_D => control_mem_din,
--
TX_AXIS_ACLK => sTx_axis_fifo_aclk,
TX_START => ten_gig_eth_tx_start,
TX_BYTES => config_reg(15 DOWNTO 0),
TX_AXIS_TDATA => OPEN, -- sTx_axis_fifo_tdata,
TX_AXIS_TKEEP => sTx_axis_fifo_tkeep,
TX_AXIS_TVALID => sTx_axis_fifo_tvalid,
TX_AXIS_TLAST => sTx_axis_fifo_tlast,
TX_AXIS_TREADY => sTx_axis_fifo_tready
);
ten_gig_eth_rx_parser_inst : ten_gig_eth_rx_parser
PORT MAP (
RESET => reset,
RX_AXIS_FIFO_ARESETN => sRx_axis_fifo_aresetn,
-- Everything internal to this module is synchronous to this clock `ACLK'
RX_AXIS_FIFO_ACLK => sRx_axis_fifo_aclk,
RX_AXIS_FIFO_TDATA => sRx_axis_fifo_tdata,
RX_AXIS_FIFO_TKEEP => sRx_axis_fifo_tkeep,
RX_AXIS_FIFO_TVALID => sRx_axis_fifo_tvalid,
RX_AXIS_FIFO_TLAST => sRx_axis_fifo_tlast,
RX_AXIS_FIFO_TREADY => sRx_axis_fifo_tready,
-- Constants
SRC_MAC => x"000a3502a759",
SRC_IP => x"c0a80302",
SRC_PORT => x"ea62",
-- Command output fifo interface AFTER parsing the packet
-- dstMAC(48) dstIP(32) dstPort(16) opcode(32)
CMD_FIFO_Q => tge_cmd_fifo_q,
CMD_FIFO_EMPTY => tge_cmd_fifo_empty,
CMD_FIFO_RDREQ => '1',
CMD_FIFO_RDCLK => clk_200MHz
);
ten_gig_eth_tx_start <= pulse_reg(0);
dbg_ila_probe0(0) <= clk156p25;
dbg_ila_probe0(1) <= ten_gig_eth_tx_start;
dbg_ila_probe1(79 DOWNTO 16) <= sTx_axis_fifo_tdata;
dbg_ila_probe1(15 DOWNTO 8) <= sTx_axis_fifo_tkeep;
dbg_ila_probe1(7) <= sTx_axis_fifo_tvalid;
dbg_ila_probe1(6) <= sTx_axis_fifo_tlast;
dbg_ila_probe1(5) <= sTx_axis_fifo_tready;
--dbg_ila_probe2(79 DOWNTO 16) <= sRx_axis_fifo_tdata;
--dbg_ila_probe2(79 DOWNTO 48) <= control_mem_addr;
--dbg_ila_probe2(47 DOWNTO 16) <= control_mem_din;
--dbg_ila_probe2(15 DOWNTO 8) <= sRx_axis_fifo_tkeep;
dbg_ila_probe2(7) <= sRx_axis_fifo_tvalid;
dbg_ila_probe2(6) <= sRx_axis_fifo_tlast;
dbg_ila_probe2(5) <= sRx_axis_fifo_tready;
dbg_ila_probe2(4) <= control_mem_we;
--
--dbg_ila_probe3(127 DOWNTO 0) <= tge_cmd_fifo_q;
--dbg_ila_probe3(128) <= tge_cmd_fifo_empty;
END GENERATE ten_gig_eth_cores;
---------------------------------------------> ten_gig_eth
---------------------------------------------< gtx / aurora
SFP_TX_DISABLE_N <= '1';
LED8Bit(0) <= NOT SFP_LOS_LS; -- SFP is plugged in.
LED8Bit(1) <= aurora_status(0); -- link up.
aurora_64b66b_inst : aurora_64b66b
PORT MAP (
RESET => aurora_reset,
SYS_CLK => clk_100MHz,
MGT_REFCLK_P => SGMIICLK_Q0_P,
MGT_REFCLK_N => SGMIICLK_Q0_N,
-- Data interfaces are synchronous to USER_CLK
USER_CLK => aurora_user_clk,
MGT_REFCLK_BUFG_OUT => clk_sgmii,
-- TX AXI4 interface
S_AXI_TX_TDATA => aurora_tx_tdata,
S_AXI_TX_TVALID => aurora_tx_tvalid,
S_AXI_TX_TREADY => aurora_tx_tready,
-- RX AXI4 interface
M_AXI_RX_TDATA => aurora_rx_tdata,
M_AXI_RX_TVALID => aurora_rx_tvalid,
-- User flow control (UFC) TX
UFC_TX_REQ => aurora_ufc_tx_req,
S_AXI_UFC_TX_TDATA => aurora_ufc_tx_tdata,
UFC_TX_MS => aurora_ufc_tx_ms,
S_AXI_UFC_TX_TVALID => aurora_ufc_tx_tvalid,
S_AXI_UFC_TX_TREADY => aurora_ufc_tx_tready,
-- UFC RX
M_AXI_UFC_RX_TDATA => aurora_ufc_rx_tdata,
M_AXI_UFC_RX_TKEEP => aurora_ufc_rx_tkeep,
M_AXI_UFC_RX_TLAST => aurora_ufc_rx_tlast,
M_AXI_UFC_RX_TVALID => aurora_ufc_rx_tvalid,
UFC_IN_PROGRESSn => aurora_ufc_in_progress_n,
-- GTX pins
RXP => SMA_MGT_RX_P,
RXN => SMA_MGT_RX_N,
TXP => SMA_MGT_TX_P,
TXN => SMA_MGT_TX_N,
-- Status
STATUS => aurora_status
);
aurora_reset <= reset OR pulse_reg(1);
fifo_over_ufc_inst : fifo_over_ufc
PORT MAP (
RESET => reset,
AURORA_USER_CLK => aurora_user_clk,
AURORA_TX_REQ => aurora_ufc_tx_req,
AURORA_TX_MS => aurora_ufc_tx_ms,
AURORA_TX_TREADY => aurora_ufc_tx_tready,
AURORA_TX_TDATA => aurora_ufc_tx_tdata,
AURORA_TX_TVALID => aurora_ufc_tx_tvalid,
AURORA_RX_TDATA => aurora_ufc_rx_tdata,
AURORA_RX_TVALID => aurora_ufc_rx_tvalid,
FIFO_CLK => gig_eth_tx_fifo1_wrclk,
TX_FIFO_Q => gig_eth_tx_fifo1_q,
TX_FIFO_WREN => gig_eth_tx_fifo1_wren,
TX_FIFO_FULL => gig_eth_tx_fifo1_full,
RX_FIFO_Q => gig_eth_rx_fifo1_q,
RX_FIFO_RDEN => gig_eth_rx_fifo1_rden,
RX_FIFO_EMPTY => gig_eth_rx_fifo1_empty,
ERR => LED8Bit(2)
);
gig_eth_rx_fifo1_rdclk <= gig_eth_tx_fifo1_wrclk;
sdm_adc_data_aurora_recv_inst : sdm_adc_data_aurora_recv
GENERIC MAP (
NCH_ADC => 20,
ADC_CYC => 20,
NCH_SDM => 19,
SDM_CYC => 4
)
PORT MAP (
RESET => reset,
CLK => control_clk,
USER_CLK => aurora_user_clk,
M_AXI_RX_TDATA => aurora_rx_tdata,
M_AXI_RX_TVALID => aurora_rx_tvalid,
DOUT => tms_sdm_adc_dout,
DOUT_VALID => tms_sdm_adc_dout_valid,
FIFO_FULL => OPEN
);
data_sampler_fifo_inst : data_sampler_fifo
GENERIC MAP (
DIN_WIDTH => 512,
DOUT_WIDTH => 32
)
PORT MAP (
RESET => control_data_fifo_reset,
CLK => control_clk,
TRIG => idata_trig_in,
DIN => tms_sdm_adc_dout,
DIN_VALID => tms_sdm_adc_dout_valid,
DIN_CLK => aurora_user_clk,
DOUT => control_data_fifo_q,
DOUT_EMPTY => control_data_fifo_empty,
DOUT_RDEN => control_data_fifo_rdreq
);
control_data_fifo_reset <= reset OR idata_data_fifo_reset;
-- -- debug
-- aurora_ufc_tx_req <= pulse_reg(8);
-- ufc_tx_tvalid_edge_sync_inst : edge_sync
-- GENERIC MAP (
-- EDGE => '0'
-- )
-- PORT MAP (
-- RESET => reset,
-- CLK => aurora_user_clk,
-- EI => aurora_ufc_tx_req,
-- SO => aurora_ufc_tx_tvalid
-- );
-- aurora_ufc_tx_tdata <= x"0000_0000_0000" & config_reg(30*16+15 DOWNTO 30*16);
-- aurora_ufc_tx_ms <= config_reg(29*16+7 DOWNTO 29*16); -- don't reverse bit-order here
--
dbg_ila1_inst : dbg_ila1
PORT MAP (
CLK => aurora_user_clk,
PROBE0 => dbg_ila1_probe0,
PROBE1 => dbg_ila1_probe1
);
-- dbg_ila1_probe0 <=
-- "0000" & gig_eth_rx_fifo_empty & aurora_status(2) & aurora_status(1) & aurora_status(0)
-- & aurora_reset & aurora_ufc_in_progress_n & aurora_ufc_rx_tlast & aurora_ufc_rx_tvalid
-- & aurora_ufc_tx_req & aurora_ufc_tx_tready & aurora_ufc_tx_tvalid & aurora_tx_tready;
-- dbg_ila1_probe1 <= aurora_ufc_rx_tdata(7 DOWNTO 0) & aurora_ufc_tx_tdata(7 DOWNTO 0);
PROCESS (aurora_user_clk, reset) IS
BEGIN -- PROCESS
IF reset = '1' THEN
dbg_ila1_probe0 <= (OTHERS => '0');
ELSIF rising_edge(aurora_user_clk) THEN -- rising clock edge
IF tms_sdm_adc_dout_valid = '1' THEN
dbg_ila1_probe0 <= tms_sdm_adc_dout(16*19+15 DOWNTO 16*19);
END IF;
END IF;
END PROCESS;
dbg_ila1_probe1 <= aurora_rx_tdata(63 DOWNTO 63-13) & aurora_rx_tvalid & control_data_fifo_reset;
---------------------------------------------> gtx / aurora
---------------------------------------------< gig_eth
gig_eth_cores : IF ENABLE_GIG_ETH GENERATE
gig_eth_mac_addr(gig_eth_mac_addr'length-1 DOWNTO 4) <= x"000a3502a75";
gig_eth_mac_addr(3 DOWNTO 0) <= DIPSw4Bit;
gig_eth_ipv4_addr(gig_eth_ipv4_addr'length-1 DOWNTO 4) <= x"c0a8020";
gig_eth_ipv4_addr(3 DOWNTO 0) <= DIPSw4Bit;
gig_eth_subnet_mask <= x"ffffff00";
gig_eth_gateway_ip_addr <= x"c0a80201";
gig_eth_inst : gig_eth
PORT MAP (
-- asynchronous reset
GLBL_RST => reset,
-- clocks
GTX_CLK => clk_125MHz,
REF_CLK => sys_clk, -- 200MHz for IODELAY
-- PHY interface
PHY_RESETN => PHY_RESET_N,
-- RGMII Interface
RGMII_TXD => RGMII_TXD,
RGMII_TX_CTL => RGMII_TX_CTL,
RGMII_TXC => RGMII_TXC,
RGMII_RXD => RGMII_RXD,
RGMII_RX_CTL => RGMII_RX_CTL,
RGMII_RXC => RGMII_RXC,
-- MDIO Interface
MDIO => MDIO,
MDC => MDC,
-- TCP
MAC_ADDR => gig_eth_mac_addr,
IPv4_ADDR => gig_eth_ipv4_addr,
IPv6_ADDR => (OTHERS => '0'),
SUBNET_MASK => gig_eth_subnet_mask,
GATEWAY_IP_ADDR => gig_eth_gateway_ip_addr,
TCP_CONNECTION_RESET => '0',
TX_TDATA => gig_eth_tx_tdata,
TX_TVALID => gig_eth_tx_tvalid,
TX_TREADY => gig_eth_tx_tready,
RX_TDATA => gig_eth_rx_tdata,
RX_TVALID => gig_eth_rx_tvalid,
RX_TREADY => gig_eth_rx_tready,
-- FIFO
TCP_USE_FIFO => gig_eth_tcp_use_fifo,
TX_FIFO_WRCLK => gig_eth_tx_fifo_wrclk,
TX_FIFO_Q => gig_eth_tx_fifo_q,
TX_FIFO_WREN => gig_eth_tx_fifo_wren,
TX_FIFO_FULL => gig_eth_tx_fifo_full,
RX_FIFO_RDCLK => gig_eth_rx_fifo_rdclk,
RX_FIFO_Q => gig_eth_rx_fifo_q,
RX_FIFO_RDEN => gig_eth_rx_fifo_rden,
RX_FIFO_EMPTY => gig_eth_rx_fifo_empty,
--
TX_FIFO1_WRCLK => gig_eth_tx_fifo1_wrclk,
TX_FIFO1_Q => gig_eth_tx_fifo1_q,
TX_FIFO1_WREN => gig_eth_tx_fifo1_wren,
TX_FIFO1_FULL => gig_eth_tx_fifo1_full,
RX_FIFO1_RDCLK => gig_eth_rx_fifo1_rdclk,
RX_FIFO1_Q => gig_eth_rx_fifo1_q,
RX_FIFO1_RDEN => gig_eth_rx_fifo1_rden,
RX_FIFO1_EMPTY => gig_eth_rx_fifo1_empty
);
dbg_ila_probe0(26 DOWNTO 19) <= gig_eth_rx_tdata;
dbg_ila_probe0(27) <= gig_eth_rx_tvalid;
dbg_ila_probe0(28) <= gig_eth_rx_tready;
-- loopback
--gig_eth_tx_tdata <= gig_eth_rx_tdata;
--gig_eth_tx_tvalid <= gig_eth_rx_tvalid;
--gig_eth_rx_tready <= gig_eth_tx_tready;
-- receive to cmd_fifo
gig_eth_tcp_use_fifo <= '1';
gig_eth_rx_fifo_rdclk <= control_clk;
cmd_fifo_q(31 DOWNTO 0) <= gig_eth_rx_fifo_q;
dbg_ila_probe0(63 DOWNTO 32) <= gig_eth_rx_fifo_q;
cmd_fifo_empty <= gig_eth_rx_fifo_empty;
gig_eth_rx_fifo_rden <= cmd_fifo_rdreq;
-- send control_fifo data through gig_eth_tx_fifo
gig_eth_tx_fifo_wrclk <= clk_125MHz;
-- connect FWFT fifo interface
control_fifo_rdclk <= gig_eth_tx_fifo_wrclk;
gig_eth_tx_fifo_q <= control_fifo_q(31 DOWNTO 0);
gig_eth_tx_fifo_wren <= NOT control_fifo_empty;
control_fifo_rdreq <= NOT gig_eth_tx_fifo_full;
END GENERATE gig_eth_cores;
---------------------------------------------> gig_eth
---------------------------------------------< SDRAM
sdram_ddr3_inst : sdram_ddr3
PORT MAP (
CLK => sys_clk, -- system clock, must be the same as intended in MIG
REFCLK => sys_clk, -- 200MHz for iodelay
RESET => reset,
-- SDRAM_DDR3
-- Inouts
DDR3_DQ => DDR3_DQ,
DDR3_DQS_P => DDR3_DQS_P,
DDR3_DQS_N => DDR3_DQS_N,
-- Outputs
DDR3_ADDR => DDR3_ADDR,
DDR3_BA => DDR3_BA,
DDR3_RAS_N => DDR3_RAS_N,
DDR3_CAS_N => DDR3_CAS_N,
DDR3_WE_N => DDR3_WE_N,
DDR3_RESET_N => DDR3_RESET_N,
DDR3_CK_P => DDR3_CK_P,
DDR3_CK_N => DDR3_CK_N,
DDR3_CKE => DDR3_CKE,
DDR3_CS_N => DDR3_CS_N,
DDR3_DM => DDR3_DM,
DDR3_ODT => DDR3_ODT,
-- Status Outputs
INIT_CALIB_COMPLETE => LED8Bit(4),
-- Internal data r/w interface
UI_CLK => clk_200MHz,
--
CTRL_RESET => pulse_reg(6),
WR_START => idata_data_wr_start,
WR_ADDR_BEGIN => config_reg(32*4+27 DOWNTO 32*4),
WR_STOP => pulse_reg(4),
WR_WRAP_AROUND => config_reg(32*4+28),
POST_TRIGGER => config_reg(32*5+27 DOWNTO 32*5),
WR_BUSY => idata_data_wr_busy,
WR_POINTER => OPEN,
TRIGGER_POINTER => status_reg(64*2+27 DOWNTO 64*2),
WR_WRAPPED => idata_data_wr_wrapped,
RD_START => pulse_reg(5),
RD_ADDR_BEGIN => (OTHERS => '0'),
RD_ADDR_END => config_reg(32*6+27 DOWNTO 32*6),
RD_BUSY => status_reg(64*2+30),
--
DATA_FIFO_RESET => idata_data_fifo_reset,
INDATA_FIFO_WRCLK => idata_adc_data_clk,
INDATA_FIFO_Q => idata_idata_fifo_q,
INDATA_FIFO_FULL => idata_idata_fifo_full,
INDATA_FIFO_WREN => idata_idata_fifo_wren,
--
OUTDATA_FIFO_RDCLK => idata_data_fifo_rdclk,
OUTDATA_FIFO_Q => idata_data_fifo_dout,
OUTDATA_FIFO_EMPTY => idata_data_fifo_empty,
OUTDATA_FIFO_RDEN => idata_data_fifo_rden,
--
DBG_APP_ADDR => sdram_app_addr,
DBG_APP_EN => sdram_app_en,
DBG_APP_RDY => sdram_app_rdy,
DBG_APP_WDF_DATA => sdram_app_wdf_data,
DBG_APP_WDF_END => sdram_app_wdf_end,
DBG_APP_WDF_WREN => sdram_app_wdf_wren,
DBG_APP_WDF_RDY => sdram_app_wdf_rdy,
DBG_APP_RD_DATA => sdram_app_rd_data,
DBG_APP_RD_DATA_VALID => sdram_app_rd_data_valid
);
idata_adc_data_clk <= clk_125MHz;
idata_data_fifo_reset <= pulse_reg(2);
status_reg(64*2+28) <= idata_data_wr_busy;
status_reg(64*2+29) <= idata_data_wr_wrapped;
--
channel_sel_inst : channel_sel
PORT MAP (
CLK => idata_adc_data_clk, -- fifo wrclk
RESET => reset,
SEL => config_reg(32*7+7 DOWNTO 32*7),
--
DATA_FIFO_RESET => idata_data_fifo_reset,
--
INDATA_Q => idata_channel_avg_outdata_q,
DATA_FIFO_WREN => idata_data_fifo_wren,
DATA_FIFO_FULL => idata_data_fifo_full,
--
OUTDATA_FIFO_Q => idata_idata_fifo_q,
DATA_FIFO_RDEN => idata_idata_fifo_rden,
DATA_FIFO_EMPTY => idata_idata_fifo_empty
);
idata_idata_fifo_rden <= NOT idata_idata_fifo_full;
idata_idata_fifo_wren <= NOT idata_idata_fifo_empty;
idata_data_fifo_wren <= config_reg(32*6+31) AND idata_channel_avg_outvalid;
--
channel_avg_inst : channel_avg
PORT MAP (
RESET => reset,
CLK => idata_adc_data_clk,
-- high 4-bit is offset, 2**(low 4-bit) is number of points to average
CONFIG => config_reg(32*7+15 DOWNTO 32*7+8),
TRIG => idata_data_wr_start,
INDATA_Q => idata_data_fifo_din,
OUTVALID => idata_channel_avg_outvalid,
OUTDATA_Q => idata_channel_avg_outdata_q
);
--
dbg_ila_probe3(27 DOWNTO 0) <= sdram_app_addr;
dbg_ila_probe3(28) <= sdram_app_en;
dbg_ila_probe3(29) <= sdram_app_rdy;
dbg_ila_probe3(30) <= sdram_app_wdf_wren;
dbg_ila_probe3(31) <= sdram_app_wdf_rdy;
dbg_ila_probe3(32) <= sdram_app_wdf_end;
dbg_ila_probe3(1023 DOWNTO 512) <= sdram_app_wdf_data;
dbg_ila_probe3(1024+1023 DOWNTO 1024+512) <= sdram_app_rd_data;
dbg_ila_probe3(33) <= sdram_app_rd_data_valid;
dbg_ila_probe3(511 DOWNTO 336) <= status_reg;
---------------------------------------------> SDRAM
---------------------------------------------< I2C
i2c_write_regmap_inst : i2c_write_regmap
GENERIC MAP (
-- file not used, see actual code.
REGMAP_FNAME => "../../../config/Si5324_156.25MHz_regmap.txt",
INPUT_CLK_FREQENCY => 100_000_000,
BUS_CLK_FREQUENCY => 100_000
)
PORT MAP (
CLK => control_clk,
RESET => reset,
START => pulse_reg(15),
EXT_RSTn => SI5324_RSTn,
BUSY => status_reg(16*10+7),
ACK_ERROR => status_reg(16*10+6),
SDA_in => i2c_sda_in,
SDA_out => i2c_sda_out,
SDA_t => i2c_sda_t,
SCL => i2c_scl_out
);
i2c_sda_iobuf_inst : IOBUF
GENERIC MAP(
DRIVE => 12,
SLEW => "SLOW"
)
PORT MAP(
O => i2c_sda_in,
IO => I2C_SDA,
I => i2c_sda_out,
T => i2c_sda_t
);
i2c_scl_iobuf_inst : IOBUF
GENERIC MAP(
DRIVE => 12,
SLEW => "SLOW"
)
PORT MAP(
O => OPEN,
IO => I2C_SCL,
I => i2c_scl_out,
T => '0'
);
-- External clock IC
si5324_clk_div_inst : clk_div
GENERIC MAP (
WIDTH => 32,
PBITS => 8
)
PORT MAP (
RESET => reset,
CLK => clk156p25,
DIV => x"1b",
CLK_DIV => LED8Bit(3)
);
---------------------------------------------> I2C
-- clock output
refout_clk_div_inst : clk_div
PORT MAP (
RESET => reset,
CLK => idata_adc_data_clk,
DIV => config_reg(16*15+3 DOWNTO 16*15),
CLK_DIV => idata_adc_refout_clkdiv
);
clk_fwd_inst : clk_fwd -- idata_adc_refout_clkdiv
PORT MAP (R => reset, I => clk156p25, O => USER_SMA_CLOCK_P);
clk_fwd_inst1 : clk_fwd GENERIC MAP (INV => true)
PORT MAP (R => reset, I => clk156p25, O => USER_SMA_CLOCK_N);
clk_fwd_inst2 : clk_fwd GENERIC MAP (INV => true)
PORT MAP (R => reset, I => idata_adc_data_clk, O => USER_SMA_GPIO_N);
-- capture the rising edge of trigger
trig_edge_sync_inst : edge_sync
PORT MAP (
RESET => reset,
CLK => control_clk,
EI => idata_trig_in,
SO => idata_trig_synced
);
idata_trig_in <= USER_SMA_GPIO_P;
idata_trig_allow <= config_reg(32*6+30);
idata_data_wr_start <= pulse_reg(3) OR (idata_trig_synced AND idata_trig_allow
AND (NOT idata_data_wr_busy)
AND (NOT idata_data_wr_wrapped));
--led_obufs : FOR i IN 0 TO 7 GENERATE
-- led_obuf : OBUF
-- PORT MAP (
-- I => usr_data_output(i),
-- O => LED8Bit(i)
-- );
--END GENERATE led_obufs;
--LED8Bit(5 DOWNTO 1) <= (OTHERS => '0');
END Behavioral;
|
bsd-3-clause
|
ymei/TMSPlane
|
Firmware/src/ten_gig_eth/TE07412C1/pcs_pma/ten_gig_eth_pcs_pma_0_shared_clock_and_reset.vhd
|
2
|
8108
|
-------------------------------------------------------------------------------
-- Title : Shared clocking and resets
-- Project : 10GBASE-R
-------------------------------------------------------------------------------
-- File : ten_gig_eth_pcs_pma_0_shared_clock_and_reset.vhd
-------------------------------------------------------------------------------
-- Description: This file contains the
-- 10GBASE-R clocking and reset logic which can be shared between multiple cores
-------------------------------------------------------------------------------
-- (c) Copyright 2009 - 2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ten_gig_eth_pcs_pma_0_shared_clock_and_reset is
port
(
areset : in std_logic;
refclk_p : in std_logic;
refclk_n : in std_logic;
refclk : out std_logic;
txoutclk : in std_logic;
coreclk : out std_logic;
dclk : out std_logic; -- ymei
qplllock : in std_logic;
areset_coreclk : out std_logic;
gttxreset : out std_logic;
gtrxreset : out std_logic;
txuserrdy : out std_logic := '0';
txusrclk : out std_logic;
txusrclk2 : out std_logic;
qpllreset : out std_logic;
reset_counter_done : out std_logic
);
end entity ten_gig_eth_pcs_pma_0_shared_clock_and_reset;
architecture wrapper of ten_gig_eth_pcs_pma_0_shared_clock_and_reset is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of wrapper : architecture is "yes";
component ten_gig_eth_pcs_pma_0_ff_synchronizer_rst2
generic
(
C_NUM_SYNC_REGS : integer := 3;
C_RVAL : std_logic := '0'
);
port
(
clk : in std_logic;
rst : in std_logic;
data_in : in std_logic;
data_out : out std_logic
);
end component;
signal coreclk_buf : std_logic;
signal coreclk_int : std_logic;
signal refclk_i : std_logic;
signal txusrclk_i : std_logic;
signal txusrclk2_i : std_logic;
signal gttxreset_i : std_logic;
signal reset_i : std_logic;
signal areset_coreclk_i : std_logic;
signal qplllock_txusrclk2_rst : std_logic;
signal qplllock_txusrclk2_i : std_logic;
signal gttxreset_txusrclk2_i : std_logic;
signal reset_counter : std_logic_vector(8 downto 0) := "000000000";
signal reset_pulse : std_logic_vector(3 downto 0) := "1110";
begin
reset_counter_done <= reset_counter(8);
-- ymei
-- ibufds_inst : IBUFDS
-- GENERIC MAP (
-- DIFF_TERM => true, -- Differential Termination
-- IBUF_LOW_PWR => false, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
-- IOSTANDARD => "LVDS"
-- )
-- PORT MAP (
-- O => refclk_i, -- Buffer output
-- I => refclk_p, -- Diff_p buffer input (connect directly to top-level port)
-- IB => refclk_n -- Diff_n buffer input (connect directly to top-level port)
-- );
ibufds_inst : IBUFDS_GTE2
port map
(
O => refclk_i,
ODIV2 => open,
CEB => '0',
I => refclk_p,
IB => refclk_n
);
refclk <= refclk_i;
txoutclk_bufg_i : BUFG
port map
(
I => txoutclk,
O => txusrclk_i
);
coreclk_bufg_i : BUFG
port map
(
I => refclk_i,
O => coreclk_int
);
dclk <= coreclk_int; -- ymei
txusrclk2 <= txusrclk_i;
txusrclk2_i <= txusrclk_i;
coreclk <= coreclk_int;
txusrclk <= txusrclk_i;
reset_i <= not qplllock ;
areset_coreclk <= areset_coreclk_i;
-- Asynch reset synchronizers...
areset_coreclk_sync_i : ten_gig_eth_pcs_pma_0_ff_synchronizer_rst2
generic map(
C_NUM_SYNC_REGS => 5,
C_RVAL => '1')
port map(
clk => coreclk_int,
rst => areset,
data_in => '0',
data_out => areset_coreclk_i
);
qplllock_txusrclk2_rst <= not(qplllock);
qplllock_txusrclk2_sync_i : ten_gig_eth_pcs_pma_0_ff_synchronizer_rst2
generic map(
C_NUM_SYNC_REGS => 5,
C_RVAL => '0')
port map(
clk => txusrclk2_i,
rst => qplllock_txusrclk2_rst,
data_in => '1',
data_out => qplllock_txusrclk2_i
);
gttxreset_txusrclk2_sync_i : ten_gig_eth_pcs_pma_0_ff_synchronizer_rst2
generic map(
C_NUM_SYNC_REGS => 5,
C_RVAL => '1')
port map(
clk => txusrclk2_i,
rst => gttxreset_i,
data_in => '0',
data_out => gttxreset_txusrclk2_i
);
-- Hold off release the GT resets until 500ns after configuration.
-- 256 ticks at the minimum possible 2.56ns period (390MHz) will be >> 500 ns.
reset_proc1: process (coreclk_int)
begin
if(coreclk_int'event and coreclk_int = '1') then
if(reset_counter(8) = '0') then
reset_counter <= reset_counter + 1;
else
reset_counter <= reset_counter;
end if;
end if;
end process;
reset_proc2: process (coreclk_int)
begin
if(coreclk_int'event and coreclk_int = '1') then
if(areset_coreclk_i = '1') then
reset_pulse <= "1110";
elsif(reset_counter(8) = '1') then
reset_pulse(3) <= '0';
reset_pulse(2 downto 0) <= reset_pulse(3 downto 1);
end if;
end if;
end process;
gttxreset_i <= reset_pulse(0);
gttxreset <= gttxreset_i;
gtrxreset <= reset_pulse(0);
qpllreset <= reset_pulse(0);
reset_proc5 : process (txusrclk2_i, gttxreset_txusrclk2_i)
begin
if(gttxreset_txusrclk2_i = '1') then
txuserrdy <= '0';
elsif(txusrclk2_i'event and txusrclk2_i = '1') then
txuserrdy <= qplllock_txusrclk2_i;
end if;
end process;
end wrapper;
|
bsd-3-clause
|
ymei/TMSPlane
|
Firmware/src/gig_eth/KC705/fifo/tri_mode_ethernet_mac_0_rx_client_fifo.vhd
|
4
|
33545
|
--------------------------------------------------------------------------------
-- Title : Receiver FIFO with AxiStream interfaces
-- Version : 1.3
-- Project : Tri-Mode Ethernet MAC
--------------------------------------------------------------------------------
-- File : tri_mode_ethernet_mac_0_rx_client_fifo.vhd
-- Author : Xilinx Inc.
-- -----------------------------------------------------------------------------
-- (c) Copyright 2004-2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-- -----------------------------------------------------------------------------
-- Description: This is the receiver side FIFO for the design example
-- of the Tri-Mode Ethernet MAC core. AxiStream interfaces are used.
--
-- The FIFO is built around an Inferred Dual Port RAM,
-- giving a total memory capacity of 4096 bytes.
--
-- Frame data received from the MAC receiver is written into the
-- FIFO on the rx_mac_aclk. An end-of-frame marker is written to
-- the BRAM parity bit on the last byte of data stored for a frame.
-- This acts as frame deliniation.
--
-- The rx_axis_mac_tvalid, rx_axis_mac_tlast, and rx_axis_mac_tuser signals
-- qualify the frame. A frame which ends with rx_axis_mac_tuser asserted
-- indicates a bad frame and will cause the FIFO write address
-- pointer to be reset to the base address of that frame. In this
-- way the bad frame will be overwritten with the next received
-- frame and is therefore dropped from the FIFO.
--
-- Frames will also be dropped from the FIFO if an overflow occurs.
-- If there is not enough memory capacity in the FIFO to store the
-- whole of an incoming frame, the write address pointer will be
-- reset and the overflow signal asserted.
--
-- When there is at least one complete frame in the FIFO,
-- the 8-bit AxiStream read interface's rx_axis_fifo_tvalid signal will
-- be enabled allowing data to be read from the FIFO.
--
-- The FIFO has been designed to operate with different clocks
-- on the write and read sides. The read clock (user side) should
-- always operate at an equal or faster frequency than the write
-- clock (MAC side).
--
-- The FIFO is designed to work with a minimum frame length of 8
-- bytes.
--
-- The FIFO memory size can be increased by expanding the rd_addr
-- and wr_addr signal widths, to address further BRAMs.
--
-- Requirements :
-- * Minimum frame size of 8 bytes
-- * Spacing between good/bad frame signaling (encoded by
-- rx_axis_mac_tvalid, rx_axis_mac_tlast, rx_axis_mac_tuser), is at least 64
-- clock cycles
-- * Write AxiStream clock is 125MHz downto 1.25MHz
-- * Read AxiStream clock equal to or faster than write clock,
-- and downto 20MHz
--
--------------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--------------------------------------------------------------------------------
-- The entity declaration for the Receiver FIFO
--------------------------------------------------------------------------------
entity tri_mode_ethernet_mac_0_rx_client_fifo is
port (
-- User-side (read-side) AxiStream interface
rx_fifo_aclk : in std_logic;
rx_fifo_resetn : in std_logic;
rx_axis_fifo_tdata : out std_logic_vector(7 downto 0) := (others => '0');
rx_axis_fifo_tvalid : out std_logic;
rx_axis_fifo_tlast : out std_logic;
rx_axis_fifo_tready : in std_logic;
-- MAC-side (write-side) AxiStream interface
rx_mac_aclk : in std_logic;
rx_mac_resetn : in std_logic;
rx_axis_mac_tdata : in std_logic_vector(7 downto 0);
rx_axis_mac_tvalid : in std_logic;
rx_axis_mac_tlast : in std_logic;
rx_axis_mac_tuser : in std_logic;
-- FIFO status and overflow indication,
-- synchronous to write-side (rx_mac_aclk) interface
fifo_status : out std_logic_vector(3 downto 0);
fifo_overflow : out std_logic
);
end tri_mode_ethernet_mac_0_rx_client_fifo;
architecture RTL of tri_mode_ethernet_mac_0_rx_client_fifo is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
------------------------------------------------------------------------------
-- Component declaration for the synchronisation flip-flop pair
------------------------------------------------------------------------------
component tri_mode_ethernet_mac_0_sync_block
port (
clk : in std_logic;
data_in : in std_logic;
data_out : out std_logic
);
end component;
------------------------------------------------------------------------------
-- Component declaration for the block RAM
------------------------------------------------------------------------------
component tri_mode_ethernet_mac_0_bram_tdp
generic (
DATA_WIDTH : integer := 8;
ADDR_WIDTH : integer := 12
);
port (
-- Port A
a_clk : in std_logic;
a_rst : in std_logic;
a_wr : in std_logic;
a_addr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
a_din : in std_logic_vector(DATA_WIDTH-1 downto 0);
-- Port B
b_clk : in std_logic;
b_en : in std_logic;
b_rst : in std_logic;
b_addr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
b_dout : out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end component;
------------------------------------------------------------------------------
-- Define internal signals
------------------------------------------------------------------------------
-- Encoded read state machine states
type rd_state_typ is (WAIT_s,
QUEUE1_s,
QUEUE2_s,
QUEUE3_s,
QUEUE_SOF_s,
SOF_s,
DATA_s,
EOF_s);
signal rd_state : rd_state_typ;
signal rd_nxt_state : rd_state_typ;
-- Encoded write state machine states
type wr_state_typ is (IDLE_s,
FRAME_s,
GF_s,
BF_s,
OVFLOW_s);
signal wr_state : wr_state_typ;
signal wr_nxt_state : wr_state_typ;
type data_pipe is array (0 to 1) of std_logic_vector(7 downto 0);
type cntl_pipe_long is array(0 to 2) of std_logic;
type cntl_pipe_short is array(0 to 1) of std_logic;
signal wr_en : std_logic;
signal wr_addr : unsigned(11 downto 0) := (others => '0');
signal wr_addr_inc : std_logic;
signal wr_start_addr_load : std_logic;
signal wr_addr_reload : std_logic;
signal wr_start_addr : unsigned(11 downto 0) := (others => '0');
signal wr_eof_data_bram : std_logic_vector(8 downto 0);
signal wr_data_bram : std_logic_vector(7 downto 0);
signal wr_data_pipe : data_pipe;
signal wr_dv_pipe : cntl_pipe_long;
signal wr_gfbf_pipe : cntl_pipe_short;
signal wr_gf : std_logic;
signal wr_bf : std_logic;
signal wr_eof_bram_pipe : cntl_pipe_short;
signal wr_eof_bram : std_logic;
signal frame_in_fifo : std_logic;
signal rd_addr : unsigned(11 downto 0) := (others => '0');
signal rd_addr_inc : std_logic;
signal rd_addr_reload : std_logic;
signal rd_eof_data_bram : std_logic_vector(8 downto 0);
signal rd_data_bram : std_logic_vector(7 downto 0);
signal rd_data_pipe : std_logic_vector(7 downto 0) := (others => '0');
signal rd_data_delay : std_logic_vector(7 downto 0) := (others => '0');
signal rd_valid_pipe : std_logic_vector(1 downto 0);
signal rd_eof_bram : std_logic_vector(0 downto 0);
signal rd_en : std_logic;
signal rd_pull_frame : std_logic;
signal rd_eof : std_logic;
signal wr_store_frame_tog : std_logic := '0';
signal rd_store_frame_sync : std_logic;
signal rd_store_frame_delay : std_logic := '0';
signal rd_store_frame : std_logic;
signal rd_frames : unsigned(8 downto 0) := (others => '0');
signal wr_fifo_full : std_logic;
signal old_rd_addr : std_logic_vector(1 downto 0);
signal update_addr_tog : std_logic;
signal update_addr_tog_sync : std_logic;
signal update_addr_tog_sync_reg : std_logic;
signal wr_rd_addr : unsigned(11 downto 0) := (others => '0');
signal wr_addr_diff_in : unsigned(12 downto 0) := (others => '0');
signal wr_addr_diff : unsigned(11 downto 0) := (others => '0');
signal wr_fifo_status : unsigned(3 downto 0) := (others => '0');
signal rx_axis_fifo_tlast_int : std_logic;
signal doa_l_unused : std_logic_vector(8 downto 0);
signal doa_u_unused : std_logic_vector(8 downto 0);
signal rx_fifo_reset : std_logic;
signal rx_mac_reset : std_logic;
--------------------------------------------------------------------------------
-- Begin FIFO architecture
--------------------------------------------------------------------------------
begin
-- invert reset sense as architecture is optimised for active high resets
rx_fifo_reset <= not rx_fifo_resetn;
rx_mac_reset <= not rx_mac_resetn;
------------------------------------------------------------------------------
-- Read state machines and control
------------------------------------------------------------------------------
-- Read state machine.
-- States are WAIT, QUEUE1, QUEUE2, QUEUE3, QUEUE_SOF, SOF, DATA, EOF.
-- Clock state to next state.
clock_rds_p : process(rx_fifo_aclk)
begin
if (rx_fifo_aclk'event and rx_fifo_aclk = '1') then
if rx_fifo_reset = '1' then
rd_state <= WAIT_s;
else
rd_state <= rd_nxt_state;
end if;
end if;
end process clock_rds_p;
rx_axis_fifo_tlast <= rx_axis_fifo_tlast_int;
-- Decode next state, combinatorial.
next_rds_p : process(rd_state, frame_in_fifo, rd_eof, rx_axis_fifo_tready,
rx_axis_fifo_tlast_int, rd_valid_pipe)
begin
case rd_state is
when WAIT_s =>
-- Wait until there is a full frame in the FIFO, then
-- start to load the pipeline.
if frame_in_fifo = '1' and rx_axis_fifo_tlast_int = '0' then
rd_nxt_state <= QUEUE1_s;
else
rd_nxt_state <= WAIT_s;
end if;
-- Load the output pipeline, which takes three clock cycles.
when QUEUE1_s =>
rd_nxt_state <= QUEUE2_s;
when QUEUE2_s =>
rd_nxt_state <= QUEUE3_s;
when QUEUE3_s =>
rd_nxt_state <= QUEUE_SOF_s;
when QUEUE_SOF_s =>
-- The pipeline is full and the frame output starts now.
rd_nxt_state <= DATA_s;
when SOF_s =>
-- A new frame begins immediately following end of last frame.
if rx_axis_fifo_tready = '1' then
rd_nxt_state <= DATA_s;
else
rd_nxt_state <= SOF_s;
end if;
when DATA_s =>
-- Read data from the FIFO. When the EOF marker is detected from
-- the BRAM output, move to the EOF state.
if rx_axis_fifo_tready = '1' and rd_eof = '1' then
rd_nxt_state <= EOF_s;
else
rd_nxt_state <= DATA_s;
end if;
when EOF_s =>
-- Hold in this state until tready is asserted and the EOF
-- marker (tlast) is accepted on interface.
-- If there is another frame in the FIFO, then it will already be
-- queued into the pipeline so so move straight to SOF state.
if rx_axis_fifo_tready = '1' then
if rd_valid_pipe(1) = '1' then
rd_nxt_state <= SOF_s;
else
rd_nxt_state <= WAIT_s;
end if;
else
rd_nxt_state <= EOF_s;
end if;
when others =>
rd_nxt_state <= WAIT_s;
end case;
end process next_rds_p;
-- Detect if frame_in_fifo was high 3 reads ago.
-- This is used to ensure we only treat data in the pipeline as valid if
-- frame_in_fifo goes high at or before the EOF marker of the current frame.
-- It may be that there is valid data (i.e a partial frame has been written)
-- but until the end of that frame we do not know if it is a good frame.
rd_valid_pipe_p : process(rx_fifo_aclk)
begin
if (rx_fifo_aclk'event and rx_fifo_aclk = '1') then
if (rx_axis_fifo_tready = '1') then
rd_valid_pipe <= rd_valid_pipe(0) & frame_in_fifo;
end if;
end if;
end process rd_valid_pipe_p;
-- Decode tlast signal from EOF marker.
rd_ll_decode_p : process(rx_fifo_aclk)
begin
if (rx_fifo_aclk'event and rx_fifo_aclk = '1') then
if rx_fifo_reset = '1' then
rx_axis_fifo_tlast_int <= '0';
elsif rx_axis_fifo_tready = '1' then
-- Assert tlast signal when the EOF marker has been detected, and
-- continue to drive it until it has been accepted on the interface.
case rd_state is
when EOF_s =>
rx_axis_fifo_tlast_int <= '1';
when others =>
rx_axis_fifo_tlast_int <= '0';
end case;
end if;
end if;
end process rd_ll_decode_p;
-- Decode the tvalid output based on state.
rd_ll_src_p : process(rx_fifo_aclk)
begin
if (rx_fifo_aclk'event and rx_fifo_aclk = '1') then
if rx_fifo_reset = '1' then
rx_axis_fifo_tvalid <= '0';
else
case rd_state is
when QUEUE_SOF_s =>
rx_axis_fifo_tvalid <= '1';
when SOF_s =>
rx_axis_fifo_tvalid <= '1';
when DATA_s =>
rx_axis_fifo_tvalid <= '1';
when EOF_s =>
rx_axis_fifo_tvalid <= '1';
when others =>
if rx_axis_fifo_tready = '1' then
rx_axis_fifo_tvalid <= '0';
end if;
end case;
end if;
end if;
end process rd_ll_src_p;
-- Decode internal control signals.
-- rd_en is used to enable the BRAM read and load the output pipeline.
rd_en_p : process(rd_state, rx_axis_fifo_tready)
begin
case rd_state is
when WAIT_s =>
rd_en <= '0';
when QUEUE1_s =>
rd_en <= '1';
when QUEUE2_s =>
rd_en <= '1';
when QUEUE3_s =>
rd_en <= '1';
when QUEUE_SOF_s =>
rd_en <= '1';
when others =>
rd_en <= rx_axis_fifo_tready;
end case;
end process rd_en_p;
-- When the BRAM is being read, enable the read address to be incremented.
rd_addr_inc <= rd_en;
-- When the current frame is done, and if there is no frame in the FIFO, then
-- the FIFO must wait until a new frame is written in. This requires the read
-- address to be moved back to where the new frame will be written. The
-- pipeline is then reloaded using the QUEUE states.
p_rd_addr_reload : process (rx_fifo_aclk)
begin
if rx_fifo_aclk'event and rx_fifo_aclk = '1' then
if rx_fifo_reset = '1' then
rd_addr_reload <= '0';
else
if rd_state = EOF_s and rd_nxt_state = WAIT_s then
rd_addr_reload <= '1';
else
rd_addr_reload <= '0';
end if;
end if;
end if;
end process p_rd_addr_reload;
-- Data is available if there is at least one frame stored in the FIFO.
p_rd_avail : process (rx_fifo_aclk)
begin
if rx_fifo_aclk'event and rx_fifo_aclk = '1' then
if rx_fifo_reset = '1' then
frame_in_fifo <= '0';
else
if rd_frames /= (rd_frames'range => '0') then
frame_in_fifo <= '1';
else
frame_in_fifo <= '0';
end if;
end if;
end if;
end process p_rd_avail;
-- When a frame has been stored we need to synchronize that event to the
-- read clock domain for frame count store.
resync_wr_store_frame_tog : tri_mode_ethernet_mac_0_sync_block
port map (
clk => rx_fifo_aclk,
data_in => wr_store_frame_tog,
data_out => rd_store_frame_sync
);
p_delay_rd_store : process (rx_fifo_aclk)
begin
if rx_fifo_aclk'event and rx_fifo_aclk = '1' then
rd_store_frame_delay <= rd_store_frame_sync;
end if;
end process p_delay_rd_store;
-- Edge detect of the resynchronized frame count. This creates a pulse
-- when a new frame has been stored.
p_sync_rd_store : process (rx_fifo_aclk)
begin
if rx_fifo_aclk'event and rx_fifo_aclk = '1' then
if rx_fifo_reset = '1' then
rd_store_frame <= '0';
else
-- Edge detector
if (rd_store_frame_delay xor rd_store_frame_sync) = '1' then
rd_store_frame <= '1';
else
rd_store_frame <= '0';
end if;
end if;
end if;
end process p_sync_rd_store;
-- This creates a pulse when a new frame has begun to be output.
p_rd_pull_frame : process (rx_fifo_aclk)
begin
if rx_fifo_aclk'event and rx_fifo_aclk = '1' then
if rx_fifo_reset = '1' then
rd_pull_frame <= '0';
else
if rd_state = SOF_s and rd_nxt_state /= SOF_s then
rd_pull_frame <= '1';
elsif rd_state = QUEUE_SOF_s and rd_nxt_state /= QUEUE_SOF_s then
rd_pull_frame <= '1';
else
rd_pull_frame <= '0';
end if;
end if;
end if;
end process p_rd_pull_frame;
-- Up/down counter to monitor the number of frames stored within the FIFO.
-- Note:
-- * increments at the end of a frame write cycle
-- * decrements at the beginning of a frame read cycle
p_rd_frames : process (rx_fifo_aclk)
begin
if rx_fifo_aclk'event and rx_fifo_aclk = '1' then
if rx_fifo_reset = '1' then
rd_frames <= (others => '0');
else
-- A frame is written to the FIFO in this cycle, and no frame is being
-- read out on the same cycle.
if rd_store_frame = '1' and rd_pull_frame = '0' then
rd_frames <= rd_frames + 1;
-- A frame is being read out on this cycle and no frame is being
-- written on the same cycle.
elsif rd_store_frame = '0' and rd_pull_frame = '1' then
rd_frames <= rd_frames - 1;
end if;
end if;
end if;
end process p_rd_frames;
------------------------------------------------------------------------------
-- Write state machines and control
------------------------------------------------------------------------------
-- Write state machine.
-- States are IDLE, FRAME, GF, BF, OVFLOW.
-- Clock state to next state.
clock_wrs_p : process(rx_mac_aclk)
begin
if (rx_mac_aclk'event and rx_mac_aclk = '1') then
if rx_mac_reset = '1' then
wr_state <= IDLE_s;
else
wr_state <= wr_nxt_state;
end if;
end if;
end process clock_wrs_p;
-- Decode next state, combinatorial.
next_wrs_p : process(wr_state, wr_dv_pipe(1), wr_gf, wr_bf, wr_fifo_full)
begin
case wr_state is
when IDLE_s =>
-- There is data in incoming pipeline when dv_pipe(1) goes high.
if wr_dv_pipe(1) = '1' then
wr_nxt_state <= FRAME_s;
else
wr_nxt_state <= IDLE_s;
end if;
when FRAME_s =>
-- If FIFO is full then go to overflow state.
-- If the good or bad flag is detected, then the end of the frame
-- has been reached and the gf or bf state is visited before idle.
-- Otherwise remain in frame state while data is written to FIFO.
if wr_fifo_full = '1' then
wr_nxt_state <= OVFLOW_s;
elsif wr_gf = '1' then
wr_nxt_state <= GF_s;
elsif wr_bf = '1' then
wr_nxt_state <= BF_s;
else
wr_nxt_state <= FRAME_s;
end if;
when GF_s =>
-- Return to idle and wait for next frame.
wr_nxt_state <= IDLE_s;
when BF_s =>
-- Return to idle and wait for next frame.
wr_nxt_state <= IDLE_s;
when OVFLOW_s =>
-- Wait until the good or bad flag received.
if wr_gf = '1' or wr_bf = '1' then
wr_nxt_state <= IDLE_s;
else
wr_nxt_state <= OVFLOW_s;
end if;
when others =>
wr_nxt_state <= IDLE_s;
end case;
end process next_wrs_p;
-- Decode control signals, combinatorial.
-- wr_en is used to enable the BRAM write and loading of the input pipeline.
wr_en <= wr_dv_pipe(2) when wr_state = FRAME_s else '0';
-- Increment the write address when we are receiving valid frame data.
wr_addr_inc <= wr_dv_pipe(2) when wr_state = FRAME_s else '0';
-- If the FIFO overflows or a frame is to be dropped, we need to move the
-- write address back to the start of the frame. This allows the data to be
-- overwritten.
wr_addr_reload <= '1' when wr_state = BF_s or wr_state = OVFLOW_s else '0';
-- The start address is saved when in the idle state.
wr_start_addr_load <= '1' when wr_state = IDLE_s else '0';
-- We need to know when a frame is stored, in order to increment the count of
-- frames stored in the FIFO.
p_wr_store_tog : process (rx_mac_aclk)
begin
if (rx_mac_aclk'event and rx_mac_aclk = '1') then
if wr_state = GF_s then
wr_store_frame_tog <= not wr_store_frame_tog;
end if;
end if;
end process;
------------------------------------------------------------------------------
-- Address counters
------------------------------------------------------------------------------
-- Write address is incremented when data is being written into the FIFO.
wr_addr_p : process(rx_mac_aclk)
begin
if (rx_mac_aclk'event and rx_mac_aclk = '1') then
if rx_mac_reset = '1' then
wr_addr <= (others => '0');
else
if wr_addr_reload = '1' then
wr_addr <= wr_start_addr;
elsif wr_addr_inc = '1' then
wr_addr <= wr_addr + 1;
end if;
end if;
end if;
end process wr_addr_p;
-- Store the start address.
wr_staddr_p : process(rx_mac_aclk)
begin
if (rx_mac_aclk'event and rx_mac_aclk = '1') then
if rx_mac_reset = '1' then
wr_start_addr <= (others => '0');
else
if wr_start_addr_load = '1' then
wr_start_addr <= wr_addr;
end if;
end if;
end if;
end process wr_staddr_p;
-- Read address is incremented when data is being read from the FIFO.
rd_addr_p : process(rx_fifo_aclk)
begin
if (rx_fifo_aclk'event and rx_fifo_aclk = '1') then
if rx_fifo_reset = '1' then
rd_addr <= (others => '0');
else
if rd_addr_reload = '1' then
rd_addr <= rd_addr - 3;
elsif rd_addr_inc = '1' then
rd_addr <= rd_addr + 1;
end if;
end if;
end if;
end process rd_addr_p;
------------------------------------------------------------------------------
-- Data pipelines
------------------------------------------------------------------------------
-- Register data inputs to BRAM.
-- No resets to allow for SRL16 target.
reg_din_p : process(rx_mac_aclk)
begin
if (rx_mac_aclk'event and rx_mac_aclk = '1') then
wr_data_pipe(0) <= rx_axis_mac_tdata;
wr_data_pipe(1) <= wr_data_pipe(0);
wr_data_bram <= wr_data_pipe(1);
end if;
end process reg_din_p;
-- The valid input enables BRAM write and is a condition for other signals.
reg_dv_p : process(rx_mac_aclk)
begin
if (rx_mac_aclk'event and rx_mac_aclk = '1') then
wr_dv_pipe(0) <= rx_axis_mac_tvalid;
wr_dv_pipe(1) <= wr_dv_pipe(0);
wr_dv_pipe(2) <= wr_dv_pipe(1);
end if;
end process reg_dv_p;
-- End of frame flag set when tlast and tvalid are asserted together.
reg_eof_p : process(rx_mac_aclk)
begin
if (rx_mac_aclk'event and rx_mac_aclk = '1') then
wr_eof_bram_pipe(0) <= rx_axis_mac_tlast;
wr_eof_bram_pipe(1) <= wr_eof_bram_pipe(0);
wr_eof_bram <= wr_eof_bram_pipe(1) and wr_dv_pipe(1);
end if;
end process reg_eof_p;
-- Upon arrival of EOF flag, the frame is good if tuser signal
-- is low, and bad if tuser signal is high.
reg_gf_p : process(rx_mac_aclk)
begin
if (rx_mac_aclk'event and rx_mac_aclk = '1') then
wr_gfbf_pipe(0) <= rx_axis_mac_tuser;
wr_gfbf_pipe(1) <= wr_gfbf_pipe(0);
wr_gf <= (not wr_gfbf_pipe(1)) and wr_eof_bram_pipe(1) and wr_dv_pipe(1);
wr_bf <= wr_gfbf_pipe(1) and wr_eof_bram_pipe(1) and wr_dv_pipe(1);
end if;
end process reg_gf_p;
-- Register data outputs from BRAM.
-- No resets to allow for SRL16 target.
reg_dout_p : process(rx_fifo_aclk)
begin
if (rx_fifo_aclk'event and rx_fifo_aclk = '1') then
if rd_en = '1' then
rd_data_delay <= rd_data_bram;
rd_data_pipe <= rd_data_delay;
rx_axis_fifo_tdata <= rd_data_pipe;
end if;
end if;
end process reg_dout_p;
reg_eofout_p : process(rx_fifo_aclk)
begin
if (rx_fifo_aclk'event and rx_fifo_aclk = '1') then
if rd_en = '1' then
rd_eof <= rd_eof_bram(0);
end if;
end if;
end process reg_eofout_p;
------------------------------------------------------------------------------
-- Overflow functionality
------------------------------------------------------------------------------
-- to minimise the number of read address updates the bottom 6 bits of the
-- read address are not passed across and the write domain will only sample
-- them when bits 5 and 4 of the read address transition from 01 to 10.
-- Since this is for full detection this just means that if the read stops
-- the write will hit full up to 64 locations early
-- need to use two bits and look for an increment transition as reload can cause
-- a decrement on this boundary (decrement is only by 3 so above bit 2 should be safe)
p_rd_addr_tog : process (rx_fifo_aclk)
begin
if rx_fifo_aclk'event and rx_fifo_aclk = '1' then
if rx_fifo_reset = '1' then
old_rd_addr <= (others => '0');
update_addr_tog <= '0';
else
old_rd_addr <= std_logic_vector(rd_addr(5 downto 4));
if rd_addr(5 downto 4) = "10" and old_rd_addr = "01" then
update_addr_tog <= not update_addr_tog;
end if;
end if;
end if;
end process p_rd_addr_tog;
sync_rd_addr_tog: tri_mode_ethernet_mac_0_sync_block
port map (
clk => rx_mac_aclk,
data_in => update_addr_tog,
data_out => update_addr_tog_sync
);
-- Obtain the difference between write and read pointers.
p_sample_addr : process (rx_mac_aclk)
begin
if rx_mac_aclk'event and rx_mac_aclk = '1' then
if rx_mac_reset = '1' then
update_addr_tog_sync_reg <= '0';
wr_rd_addr(11 downto 6) <= (others => '0');
else
update_addr_tog_sync_reg <= update_addr_tog_sync;
if update_addr_tog_sync_reg /= update_addr_tog_sync then
wr_rd_addr(11 downto 6) <= rd_addr(11 downto 6);
end if;
end if;
end if;
end process p_sample_addr;
wr_rd_addr(5 downto 0) <= "000000";
wr_addr_diff_in <= ('0' & wr_rd_addr) - ('0' & wr_addr);
-- Obtain the difference between write and read pointers.
p_addr_diff : process (rx_mac_aclk)
begin
if rx_mac_aclk'event and rx_mac_aclk = '1' then
if rx_mac_reset = '1' then
wr_addr_diff <= (others => '0');
else
wr_addr_diff <= wr_addr_diff_in(11 downto 0);
end if;
end if;
end process p_addr_diff;
-- Detect when the FIFO is full.
-- The FIFO is considered to be full if the write address pointer is
-- within 0 to 3 of the read address pointer.
p_wr_full : process (rx_mac_aclk)
begin
if rx_mac_aclk'event and rx_mac_aclk = '1' then
if rx_mac_reset = '1' then
wr_fifo_full <= '0';
else
if wr_addr_diff(11 downto 4) = 0
and wr_addr_diff(3 downto 2) /= "00" then
wr_fifo_full <= '1';
else
wr_fifo_full <= '0';
end if;
end if;
end if;
end process p_wr_full;
-- Decode the overflow indicator output.
fifo_overflow <= '1' when wr_state = OVFLOW_s else '0';
------------------------------------------------------------------------------
-- FIFO status signals
------------------------------------------------------------------------------
-- The FIFO status is four bits which represents the occupancy of the FIFO
-- in sixteenths. To generate this signal we therefore only need to compare
-- the 4 most significant bits of the write address pointer with the 4 most
-- significant bits of the read address pointer.
p_wr_fifo_status : process (rx_mac_aclk)
begin
if rx_mac_aclk'event and rx_mac_aclk = '1' then
if rx_mac_reset = '1' then
wr_fifo_status <= "0000";
else
if wr_addr_diff = (wr_addr_diff'range => '0') then
wr_fifo_status <= "0000";
else
wr_fifo_status(3) <= not wr_addr_diff(11);
wr_fifo_status(2) <= not wr_addr_diff(10);
wr_fifo_status(1) <= not wr_addr_diff(9);
wr_fifo_status(0) <= not wr_addr_diff(8);
end if;
end if;
end if;
end process p_wr_fifo_status;
fifo_status <= std_logic_vector(wr_fifo_status);
------------------------------------------------------------------------------
-- Instantiate FIFO block memory
------------------------------------------------------------------------------
wr_eof_data_bram(8) <= wr_eof_bram;
wr_eof_data_bram(7 downto 0) <= wr_data_bram;
rd_eof_bram(0) <= rd_eof_data_bram(8);
rd_data_bram <= rd_eof_data_bram(7 downto 0);
rx_ramgen_i : tri_mode_ethernet_mac_0_bram_tdp
generic map (
DATA_WIDTH => 9,
ADDR_WIDTH => 12
)
port map (
b_dout => rd_eof_data_bram,
a_addr => std_logic_vector(wr_addr(11 downto 0)),
b_addr => std_logic_vector(rd_addr(11 downto 0)),
a_clk => rx_mac_aclk,
b_clk => rx_fifo_aclk,
a_din => wr_eof_data_bram,
b_en => rd_en,
a_rst => rx_mac_reset,
b_rst => rx_fifo_reset,
a_wr => wr_en
);
end RTL;
|
bsd-3-clause
|
ymei/TMSPlane
|
Firmware/src/sdram/sdram_buffer.vhd
|
2
|
14906
|
----------------------------------------------------------------------------------
-- Company: LBNL
-- Engineer: Yuan Mei
--
-- Create Date: 12/17/2013 07:22:25 PM
-- Design Name:
-- Module Name: sdram_buffer - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Interface to Xilinx MIG UI to use external sdram as a circular buffer for
-- stream data input and packet output
-- Currently read and write are not allowed to happen simultaneously.
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- At the 1-clk wide WR_START pulse, RD_POINTER is loaded to be the first
-- address to write to. Afterwards, as writes advances, WR_POINTER increments
-- accordingly. NBURST was loaded at WR_START to control the write burst size.
-- When WR_POINTER wraps around and hits the original RD_POINTER, COLLISION
-- asserts. Writes will continue (overwritting previous data) until WR_STOP
-- (1-clk) asserts. WR_STOP can be considered as a stop trigger.
--
-- AT RD_START (1-clk), RD_ADDR is loaded and a packet of NBURST is loaded into
-- the read buffer. Then RD_VALID asserts.
----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
LIBRARY UNISIM;
USE UNISIM.VComponents.ALL;
ENTITY sdram_buffer IS
GENERIC (
INDATA_WIDTH : positive := 256;
OUTDATA_WIDTH : positive := 64;
NBURST_WIDTH : positive := 8;
APP_ADDR_WIDTH : positive := 28;
APP_DATA_WIDTH : positive := 512;
APP_MASK_WIDTH : positive := 64
);
PORT (
CLK : IN std_logic; -- MIG UI_CLK
RESET : IN std_logic;
--
APP_ADDR : OUT std_logic_vector(APP_ADDR_WIDTH-1 DOWNTO 0);
APP_CMD : OUT std_logic_vector(2 DOWNTO 0);
APP_EN : OUT std_logic;
APP_RDY : IN std_logic;
APP_WDF_DATA : OUT std_logic_vector(APP_DATA_WIDTH-1 DOWNTO 0);
APP_WDF_END : OUT std_logic;
APP_WDF_MASK : OUT std_logic_vector(APP_MASK_WIDTH-1 DOWNTO 0);
APP_WDF_WREN : OUT std_logic;
APP_WDF_RDY : IN std_logic;
APP_RD_DATA : IN std_logic_vector(APP_DATA_WIDTH-1 DOWNTO 0);
APP_RD_DATA_END : IN std_logic;
APP_RD_DATA_VALID : IN std_logic;
--
RD_POINTER : IN std_logic_vector(APP_ADDR_WIDTH-1 DOWNTO 0);
WR_POINTER : OUT std_logic_vector(APP_ADDR_WIDTH-1 DOWNTO 0);
COLLISION : OUT std_logic;
NBURST : IN std_logic_vector(NBURST_WIDTH-1 DOWNTO 0);
RD_ADDR : IN std_logic_vector(APP_ADDR_WIDTH-1 DOWNTO 0);
RD_START : IN std_logic;
RD_VALID : OUT std_logic;
WR_START : IN std_logic;
WR_STOP : IN std_logic;
WR_BUSY : OUT std_logic;
--
INDATA_FIFO_WRCLK : IN std_logic;
INDATA_FIFO_Q : IN std_logic_vector(INDATA_WIDTH-1 DOWNTO 0);
INDATA_FIFO_FULL : OUT std_logic;
INDATA_FIFO_WREN : IN std_logic;
--
OUTDATA_BRAM_CLKB : IN std_logic;
OUTDATA_BRAM_ADDRB : IN std_logic_vector(NBURST_WIDTH+3-1 DOWNTO 0);
OUTDATA_BRAM_DOUTB : OUT std_logic_vector(OUTDATA_WIDTH-1 DOWNTO 0)
);
END sdram_buffer;
ARCHITECTURE Behavioral OF sdram_buffer IS
COMPONENT fifo256to512
PORT (
RST : IN std_logic;
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
DIN : IN std_logic_vector(255 DOWNTO 0);
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DOUT : OUT std_logic_vector(511 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic;
PROG_EMPTY : OUT std_logic
);
END COMPONENT;
COMPONENT sdram_buffer_bram
PORT (
CLKA : IN std_logic;
WEA : IN std_logic_vector(0 DOWNTO 0);
ADDRA : IN std_logic_vector(7 DOWNTO 0);
DINA : IN std_logic_vector(511 DOWNTO 0);
CLKB : IN std_logic;
ADDRB : IN std_logic_vector(10 DOWNTO 0);
DOUTB : OUT std_logic_vector(63 DOWNTO 0)
);
END COMPONENT;
CONSTANT DDR3_CMD_WRITE : std_logic_vector(2 DOWNTO 0) := "000";
CONSTANT DDR3_CMD_READ : std_logic_vector(2 DOWNTO 0) := "001";
SIGNAL rd_pointer_reg : unsigned(RD_POINTER'length-1 DOWNTO 0);
SIGNAL rd_addr_reg : unsigned(RD_ADDR'length-1 DOWNTO 0);
SIGNAL rd_start_pulse : std_logic := '0';
SIGNAL rd_cmd_busy : std_logic := '0';
SIGNAL rd_data_busy : std_logic := '0';
SIGNAL rd_burst_start : std_logic := '0';
SIGNAL rd_burst_start_i : std_logic := '0';
--
SIGNAL wr_start_pulse : std_logic := '0';
SIGNAL wr_stop_pulse : std_logic := '0';
SIGNAL writing_reg : std_logic := '0';
SIGNAL wr_burst_start : std_logic := '0';
SIGNAL wr_burst_start_i : std_logic := '0';
SIGNAL wr_wdf_end : std_logic := '0';
SIGNAL wr_wdf_wren : std_logic := '0';
SIGNAL wr_cmd_busy : std_logic := '0';
SIGNAL wr_data_busy : std_logic := '0';
--
SIGNAL nburst_reg : unsigned(NBURST'length-1 DOWNTO 0);
--
SIGNAL indata_fifo_rdclk : std_logic;
SIGNAL indata_fifo_rden : std_logic;
SIGNAL indata_fifo_dout : std_logic_vector(APP_DATA_WIDTH-1 DOWNTO 0);
SIGNAL indata_fifo_empty : std_logic;
SIGNAL indata_fifo_prog_empty : std_logic;
--
SIGNAL bram_clka : std_logic;
SIGNAL bram_wea : std_logic_vector(0 DOWNTO 0);
SIGNAL bram_we : std_logic;
SIGNAL bram_addra : std_logic_vector(7 DOWNTO 0);
SIGNAL bram_dina : std_logic_vector(511 DOWNTO 0);
SIGNAL reading : std_logic;
TYPE read_state_type IS (R0, R1, R2, R3, R4);
SIGNAL read_state : read_state_type := R0;
SIGNAL read_data_state : read_state_type := R0;
TYPE write_state_type IS (W0, W1, W2, W3, W4);
SIGNAL write_state : write_state_type := W0;
SIGNAL write_data_state : write_state_type := W0;
SIGNAL rd_addr_i : unsigned(APP_ADDR'length-1 DOWNTO 0);
SIGNAL rd_app_en : std_logic;
SIGNAL rd_app_cmd : std_logic_vector(2 DOWNTO 0);
SIGNAL wr_addr_i : unsigned(APP_ADDR'length-1 DOWNTO 0);
SIGNAL wr_app_en : std_logic;
SIGNAL wr_app_cmd : std_logic_vector(2 DOWNTO 0);
BEGIN
indata_fifo_inst : fifo256to512
PORT MAP (
RST => RESET,
WR_CLK => INDATA_FIFO_WRCLK,
RD_CLK => indata_fifo_rdclk,
DIN => INDATA_FIFO_Q,
WR_EN => INDATA_FIFO_WREN,
RD_EN => indata_fifo_rden,
DOUT => indata_fifo_dout,
FULL => INDATA_FIFO_FULL,
EMPTY => indata_fifo_empty,
PROG_EMPTY => indata_fifo_prog_empty
);
indata_fifo_rdclk <= CLK;
APP_WDF_DATA <= indata_fifo_dout;
APP_WDF_MASK <= (OTHERS => '0');
sdram_buffer_bram_inst : sdram_buffer_bram
PORT MAP (
CLKA => bram_clka,
WEA => bram_wea,
ADDRA => bram_addra,
DINA => bram_dina,
CLKB => OUTDATA_BRAM_CLKB,
ADDRB => OUTDATA_BRAM_ADDRB,
DOUTB => OUTDATA_BRAM_DOUTB
);
bram_wea <= (OTHERS => bram_we);
PROCESS (bram_clka)
BEGIN
IF falling_edge(bram_clka) THEN
bram_dina <= APP_RD_DATA;
END IF;
END PROCESS;
bram_clka <= CLK;
-- make sure _pulse's are 1-clk wide
PROCESS (CLK)
VARIABLE prev : std_logic := '0';
VARIABLE prev1 : std_logic := '0';
VARIABLE prev2 : std_logic := '0';
BEGIN
IF rising_edge(CLK) THEN
rd_start_pulse <= RD_START AND (NOT prev);
wr_start_pulse <= WR_START AND (NOT prev1);
wr_stop_pulse <= WR_STOP AND (NOT prev2);
prev := RD_START;
prev1 := WR_START;
prev2 := WR_STOP;
END IF;
END PROCESS;
-- register addresses and status
PROCESS (CLK, RESET)
BEGIN
IF RESET = '1' THEN
rd_pointer_reg <= (OTHERS => '0');
rd_addr_reg <= (OTHERS => '0');
nburst_reg <= (OTHERS => '0');
writing_reg <= '0';
ELSIF falling_edge(CLK) THEN
IF wr_start_pulse = '1' THEN
rd_pointer_reg <= unsigned(RD_POINTER);
nburst_reg <= unsigned(NBURST);
writing_reg <= '1';
END IF;
IF wr_stop_pulse = '1' THEN
writing_reg <= '0';
END IF;
IF rd_start_pulse = '1' THEN
rd_addr_reg <= unsigned(RD_ADDR);
nburst_reg <= unsigned(NBURST);
END IF;
END IF;
END PROCESS;
-- write command
PROCESS (CLK, RESET)
VARIABLE burst_counter : signed(NBURST'length DOWNTO 0);
BEGIN
IF RESET = '1' THEN
wr_addr_i <= (OTHERS => '0');
write_state <= W0;
COLLISION <= '0';
ELSIF falling_edge(CLK) THEN
wr_app_en <= '0';
wr_app_cmd <= (OTHERS => '0');
wr_burst_start <= '0';
wr_cmd_busy <= '1';
write_state <= W0;
CASE write_state IS
WHEN W0 =>
wr_cmd_busy <= '0';
IF wr_start_pulse = '1' THEN
wr_cmd_busy <= '1';
wr_addr_i <= rd_pointer_reg;
COLLISION <= '0';
write_state <= W1;
END IF;
WHEN W1 =>
IF indata_fifo_prog_empty = '0' THEN
burst_counter := signed('0' & nburst_reg);
wr_burst_start <= '1';
write_state <= W2;
ELSE
write_state <= W1;
END IF;
WHEN W2 =>
wr_app_cmd <= DDR3_CMD_WRITE;
wr_app_en <= '1';
write_state <= W3;
WHEN W3 =>
wr_app_cmd <= DDR3_CMD_WRITE;
wr_app_en <= '1';
write_state <= W3;
IF APP_RDY = '1' THEN
wr_addr_i <= wr_addr_i + 8;
burst_counter := burst_counter - 1;
END IF;
IF burst_counter < 1 THEN
wr_app_en <= '0';
IF writing_reg = '1' THEN
write_state <= W1;
ELSE
write_state <= W0;
END IF;
END IF;
IF rd_pointer_reg - wr_addr_i <= 8 THEN
COLLISION <= '1';
END IF;
WHEN OTHERS =>
write_state <= W0;
END CASE;
END IF;
END PROCESS;
-- write data
PROCESS (CLK, RESET)
VARIABLE burst_counter : signed(NBURST'length DOWNTO 0);
BEGIN
IF RESET = '1' THEN
write_data_state <= W0;
ELSIF falling_edge(CLK) THEN
indata_fifo_rden <= '0';
wr_wdf_end <= '0';
wr_wdf_wren <= '0';
wr_data_busy <= '1';
write_data_state <= W0;
CASE write_data_state IS
WHEN W0 =>
wr_data_busy <= '0';
IF wr_burst_start_i = '1' THEN
wr_wdf_end <= '1';
wr_wdf_wren <= '1';
burst_counter := signed('0' & nburst_reg);
wr_data_busy <= '1';
write_data_state <= W1;
END IF;
WHEN W1 =>
wr_wdf_end <= '1';
wr_wdf_wren <= '1';
write_data_state <= W1;
IF APP_WDF_RDY = '1' THEN
indata_fifo_rden <= '1';
burst_counter := burst_counter - 1;
END IF;
IF burst_counter < 1 THEN
wr_wdf_wren <= '0';
wr_wdf_end <= '0';
write_data_state <= W0;
END IF;
WHEN OTHERS =>
write_data_state <= W0;
END CASE;
END IF;
END PROCESS;
-- read command
PROCESS (CLK, RESET)
VARIABLE burst_counter : signed(NBURST'length DOWNTO 0);
BEGIN
IF RESET = '1' THEN
rd_addr_i <= (OTHERS => '0');
read_state <= R0;
ELSIF falling_edge(CLK) THEN
rd_app_en <= '0';
rd_app_cmd <= (OTHERS => '0');
rd_burst_start <= '0';
rd_cmd_busy <= '1';
read_state <= R0;
CASE read_state IS
WHEN R0 =>
rd_cmd_busy <= '0';
IF rd_start_pulse = '1' THEN
rd_cmd_busy <= '1';
rd_addr_i <= unsigned(RD_ADDR);
burst_counter := signed('0' & nburst_reg);
rd_burst_start <= '1';
read_state <= R1;
END IF;
WHEN R1 =>
rd_app_cmd <= DDR3_CMD_READ;
rd_app_en <= '1';
read_state <= R2;
WHEN R2 =>
rd_app_cmd <= DDR3_CMD_READ;
rd_app_en <= '1';
read_state <= R2;
IF APP_RDY = '1' THEN
rd_addr_i <= rd_addr_i + 8;
burst_counter := burst_counter - 1;
END IF;
IF burst_counter < 1 THEN
rd_app_en <= '0';
read_state <= R0;
END IF;
WHEN OTHERS =>
read_state <= R0;
END CASE;
END IF;
END PROCESS;
-- read data
PROCESS (CLK, RESET)
VARIABLE burst_counter : signed(NBURST'length DOWNTO 0);
BEGIN
IF RESET = '1' THEN
read_data_state <= R0;
ELSIF falling_edge(CLK) THEN
bram_we <= '0';
read_data_state <= R0;
CASE read_data_state IS
WHEN R0 =>
rd_data_busy <= '0';
IF rd_burst_start_i = '1' THEN
bram_addra <= (OTHERS => '0');
burst_counter := signed('0' & nburst_reg);
rd_data_busy <= '1';
read_data_state <= R1;
END IF;
WHEN R1 =>
read_data_state <= R1;
IF APP_RD_DATA_VALID = '1' THEN
bram_we <= '1';
bram_addra <= std_logic_vector(unsigned(bram_addra)+1);
burst_counter := burst_counter - 1;
END IF;
IF burst_counter < 1 THEN
read_data_state <= R0;
END IF;
WHEN OTHERS =>
read_data_state <= R0;
END CASE;
END IF;
END PROCESS;
-- buffer out and delay half CLK
PROCESS (CLK, RESET)
BEGIN
IF RESET = '1' THEN
ELSIF rising_edge(CLK) THEN
IF wr_app_en = '1' THEN
APP_ADDR <= std_logic_vector(wr_addr_i);
ELSE
APP_ADDR <= std_logic_vector(rd_addr_i);
END IF;
APP_CMD <= wr_app_cmd OR rd_app_cmd;
APP_EN <= wr_app_en OR rd_app_en;
APP_WDF_END <= wr_wdf_end;
APP_WDF_WREN <= wr_wdf_wren;
WR_POINTER <= std_logic_vector(wr_addr_i);
WR_BUSY <= wr_cmd_busy OR wr_data_busy;
RD_VALID <= NOT (rd_cmd_busy OR rd_data_busy);
--
rd_burst_start_i <= rd_burst_start;
wr_burst_start_i <= wr_burst_start;
END IF;
END PROCESS;
END Behavioral;
|
bsd-3-clause
|
Stackato-Apps/ace
|
demo/kitchen-sink/docs/vhdl.vhd
|
472
|
830
|
library IEEE
user IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity COUNT16 is
port (
cOut :out std_logic_vector(15 downto 0); -- counter output
clkEn :in std_logic; -- count enable
clk :in std_logic; -- clock input
rst :in std_logic -- reset input
);
end entity;
architecture count_rtl of COUNT16 is
signal count :std_logic_vector (15 downto 0);
begin
process (clk, rst) begin
if(rst = '1') then
count <= (others=>'0');
elsif(rising_edge(clk)) then
if(clkEn = '1') then
count <= count + 1;
end if;
end if;
end process;
cOut <= count;
end architecture;
|
bsd-3-clause
|
Bluefinch/ace-builds
|
kitchen-sink/docs/vhdl.vhd
|
472
|
830
|
library IEEE
user IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity COUNT16 is
port (
cOut :out std_logic_vector(15 downto 0); -- counter output
clkEn :in std_logic; -- count enable
clk :in std_logic; -- clock input
rst :in std_logic -- reset input
);
end entity;
architecture count_rtl of COUNT16 is
signal count :std_logic_vector (15 downto 0);
begin
process (clk, rst) begin
if(rst = '1') then
count <= (others=>'0');
elsif(rising_edge(clk)) then
if(clkEn = '1') then
count <= count + 1;
end if;
end if;
end process;
cOut <= count;
end architecture;
|
bsd-3-clause
|
schelleg/PYNQ
|
boards/ip/axi_dynclk_v1_0/src/axi_dynclk_S00_AXI.vhd
|
11
|
18625
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity axi_dynclk_S00_AXI is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bus
C_S_AXI_ADDR_WIDTH : integer := 5
);
port (
-- Users to add ports here
CTRL_REG :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
STAT_REG :in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
CLK_O_REG :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
CLK_FB_REG :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
CLK_FRAC_REG :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
CLK_DIV_REG :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
CLK_LOCK_REG :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
CLK_FLTR_REG :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- User ports ends
-- Do not modify the ports beyond this line
-- Global Clock Signal
S_AXI_ACLK : in std_logic;
-- Global Reset Signal. This Signal is Active LOW
S_AXI_ARESETN : in std_logic;
-- Write address (issued by master, acceped by Slave)
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Write channel Protection type. This signal indicates the
-- privilege and security level of the transaction, and whether
-- the transaction is a data access or an instruction access.
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
-- Write address valid. This signal indicates that the master signaling
-- valid write address and control information.
S_AXI_AWVALID : in std_logic;
-- Write address ready. This signal indicates that the slave is ready
-- to accept an address and associated control signals.
S_AXI_AWREADY : out std_logic;
-- Write data (issued by master, acceped by Slave)
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Write strobes. This signal indicates which byte lanes hold
-- valid data. There is one write strobe bit for each eight
-- bits of the write data bus.
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
-- Write valid. This signal indicates that valid write
-- data and strobes are available.
S_AXI_WVALID : in std_logic;
-- Write ready. This signal indicates that the slave
-- can accept the write data.
S_AXI_WREADY : out std_logic;
-- Write response. This signal indicates the status
-- of the write transaction.
S_AXI_BRESP : out std_logic_vector(1 downto 0);
-- Write response valid. This signal indicates that the channel
-- is signaling a valid write response.
S_AXI_BVALID : out std_logic;
-- Response ready. This signal indicates that the master
-- can accept a write response.
S_AXI_BREADY : in std_logic;
-- Read address (issued by master, acceped by Slave)
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Protection type. This signal indicates the privilege
-- and security level of the transaction, and whether the
-- transaction is a data access or an instruction access.
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
-- Read address valid. This signal indicates that the channel
-- is signaling valid read address and control information.
S_AXI_ARVALID : in std_logic;
-- Read address ready. This signal indicates that the slave is
-- ready to accept an address and associated control signals.
S_AXI_ARREADY : out std_logic;
-- Read data (issued by slave)
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Read response. This signal indicates the status of the
-- read transfer.
S_AXI_RRESP : out std_logic_vector(1 downto 0);
-- Read valid. This signal indicates that the channel is
-- signaling the required read data.
S_AXI_RVALID : out std_logic;
-- Read ready. This signal indicates that the master can
-- accept the read data and response information.
S_AXI_RREADY : in std_logic
);
end axi_dynclk_S00_AXI;
architecture arch_imp of axi_dynclk_S00_AXI is
-- AXI4LITE signals
signal axi_awaddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_awready : std_logic;
signal axi_wready : std_logic;
signal axi_bresp : std_logic_vector(1 downto 0);
signal axi_bvalid : std_logic;
signal axi_araddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_arready : std_logic;
signal axi_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal axi_rresp : std_logic_vector(1 downto 0);
signal axi_rvalid : std_logic;
-- Example-specific design signals
-- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
-- ADDR_LSB is used for addressing 32/64 bit registers/memories
-- ADDR_LSB = 2 for 32 bits (n downto 2)
-- ADDR_LSB = 3 for 64 bits (n downto 3)
constant ADDR_LSB : integer := (C_S_AXI_DATA_WIDTH/32)+ 1;
constant OPT_MEM_ADDR_BITS : integer := 2;
------------------------------------------------
---- Signals for user logic register space example
--------------------------------------------------
---- Number of Slave Registers 8
signal slv_reg0 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg1 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg2 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg3 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg4 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg5 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg6 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg7 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg_rden : std_logic;
signal slv_reg_wren : std_logic;
signal reg_data_out :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal byte_index : integer;
begin
-- I/O Connections assignments
S_AXI_AWREADY <= axi_awready;
S_AXI_WREADY <= axi_wready;
S_AXI_BRESP <= axi_bresp;
S_AXI_BVALID <= axi_bvalid;
S_AXI_ARREADY <= axi_arready;
S_AXI_RDATA <= axi_rdata;
S_AXI_RRESP <= axi_rresp;
S_AXI_RVALID <= axi_rvalid;
-- Implement axi_awready generation
-- axi_awready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awready <= '0';
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- slave is ready to accept write address when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_awready <= '1';
else
axi_awready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_awaddr latching
-- This process is used to latch the address when both
-- S_AXI_AWVALID and S_AXI_WVALID are valid.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awaddr <= (others => '0');
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- Write Address latching
axi_awaddr <= S_AXI_AWADDR;
end if;
end if;
end if;
end process;
-- Implement axi_wready generation
-- axi_wready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_wready <= '0';
else
if (axi_wready = '0' and S_AXI_WVALID = '1' and S_AXI_AWVALID = '1') then
-- slave is ready to accept write data when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_wready <= '1';
else
axi_wready <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and write logic generation
-- The write data is accepted and written to memory mapped registers when
-- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
-- select byte enables of slave registers while writing.
-- These registers are cleared when reset (active low) is applied.
-- Slave register write enable is asserted when valid address and data are available
-- and the slave is ready to accept the write address and write data.
slv_reg_wren <= axi_wready and S_AXI_WVALID and axi_awready and S_AXI_AWVALID ;
process (S_AXI_ACLK)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
slv_reg0 <= (others => '0');
--slv_reg1 <= (others => '0');
slv_reg2 <= (others => '0');
slv_reg3 <= (others => '0');
slv_reg4 <= (others => '0');
slv_reg5 <= (others => '0');
slv_reg6 <= (others => '0');
slv_reg7 <= (others => '0');
else
loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
if (slv_reg_wren = '1') then
case loc_addr is
when b"000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 0
slv_reg0(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
-- when b"001" =>
-- for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-- if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 1
-- slv_reg1(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
when b"010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 2
slv_reg2(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 3
slv_reg3(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 4
slv_reg4(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 5
slv_reg5(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 6
slv_reg6(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 7
slv_reg7(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when others =>
slv_reg0 <= slv_reg0;
--slv_reg1 <= slv_reg1;
slv_reg2 <= slv_reg2;
slv_reg3 <= slv_reg3;
slv_reg4 <= slv_reg4;
slv_reg5 <= slv_reg5;
slv_reg6 <= slv_reg6;
slv_reg7 <= slv_reg7;
end case;
end if;
end if;
end if;
end process;
-- Implement write response logic generation
-- The write response and response valid signals are asserted by the slave
-- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
-- This marks the acceptance of address and indicates the status of
-- write transaction.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_bvalid <= '0';
axi_bresp <= "00"; --need to work more on the responses
else
if (axi_awready = '1' and S_AXI_AWVALID = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0' ) then
axi_bvalid <= '1';
axi_bresp <= "00";
elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high)
axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high)
end if;
end if;
end if;
end process;
-- Implement axi_arready generation
-- axi_arready is asserted for one S_AXI_ACLK clock cycle when
-- S_AXI_ARVALID is asserted. axi_awready is
-- de-asserted when reset (active low) is asserted.
-- The read address is also latched when S_AXI_ARVALID is
-- asserted. axi_araddr is reset to zero on reset assertion.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_arready <= '0';
axi_araddr <= (others => '1');
else
if (axi_arready = '0' and S_AXI_ARVALID = '1') then
-- indicates that the slave has acceped the valid read address
axi_arready <= '1';
-- Read Address latching
axi_araddr <= S_AXI_ARADDR;
else
axi_arready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_arvalid generation
-- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_ARVALID and axi_arready are asserted. The slave registers
-- data are available on the axi_rdata bus at this instance. The
-- assertion of axi_rvalid marks the validity of read data on the
-- bus and axi_rresp indicates the status of read transaction.axi_rvalid
-- is deasserted on reset (active low). axi_rresp and axi_rdata are
-- cleared to zero on reset (active low).
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_rvalid <= '0';
axi_rresp <= "00";
else
if (axi_arready = '1' and S_AXI_ARVALID = '1' and axi_rvalid = '0') then
-- Valid read data is available at the read data bus
axi_rvalid <= '1';
axi_rresp <= "00"; -- 'OKAY' response
elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then
-- Read data is accepted by the master
axi_rvalid <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and read logic generation
-- Slave register read enable is asserted when valid address is available
-- and the slave is ready to accept the read address.
slv_reg_rden <= axi_arready and S_AXI_ARVALID and (not axi_rvalid) ;
process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, axi_araddr, S_AXI_ARESETN, slv_reg_rden)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
-- Address decoding for reading registers
loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
case loc_addr is
when b"000" =>
reg_data_out <= slv_reg0;
when b"001" =>
reg_data_out <= slv_reg1;
when b"010" =>
reg_data_out <= slv_reg2;
when b"011" =>
reg_data_out <= slv_reg3;
when b"100" =>
reg_data_out <= slv_reg4;
when b"101" =>
reg_data_out <= slv_reg5;
when b"110" =>
reg_data_out <= slv_reg6;
when b"111" =>
reg_data_out <= slv_reg7;
when others =>
reg_data_out <= (others => '0');
end case;
end process;
-- Output register or memory read data
process( S_AXI_ACLK ) is
begin
if (rising_edge (S_AXI_ACLK)) then
if ( S_AXI_ARESETN = '0' ) then
axi_rdata <= (others => '0');
else
if (slv_reg_rden = '1') then
-- When there is a valid read address (S_AXI_ARVALID) with
-- acceptance of read address by the slave (axi_arready),
-- output the read dada
-- Read address mux
axi_rdata <= reg_data_out; -- register read data
end if;
end if;
end if;
end process;
-- Add user logic here
-- Users to add ports here
CTRL_REG <= slv_reg0;
slv_reg1 <= STAT_REG;
CLK_O_REG <= slv_reg2;
CLK_FB_REG <= slv_reg3;
CLK_FRAC_REG <= slv_reg4;
CLK_DIV_REG <= slv_reg5;
CLK_LOCK_REG <= slv_reg6;
CLK_FLTR_REG <= slv_reg7;
-- User logic ends
end arch_imp;
|
bsd-3-clause
|
schelleg/PYNQ
|
boards/ip/audio_codec_ctrl_v1.0/src/family_support.vhd
|
11
|
407201
|
--------------------------------------------------------------------------------
-- $Id: family_support.vhd,v 1.5.2.55 2010/12/16 15:10:57 ostlerf Exp $
--------------------------------------------------------------------------------
-- family_support.vhd - package
--------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2005-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
--------------------------------------------------------------------------------
-- Filename: family_support.vhd
--
-- Description:
--
-- FAMILIES, PRIMITIVES and PRIMITIVE AVAILABILITY GUARDS
--
-- This package allows to determine whether a given primitive
-- or set of primitives is available in an FPGA family of interest.
--
-- The key element is the function, 'supported', which is
-- available in four variants (overloads). Here are examples
-- of each:
--
-- supported(virtex2, u_RAMB16_S2)
--
-- supported("Virtex2", u_RAMB16_S2)
--
-- supported(spartan3, (u_MUXCY, u_XORCY, u_FD))
--
-- supported("spartan3", (u_MUXCY, u_XORCY, u_FD))
--
-- The 'supported' function returns true if and only
-- if all of the primitives being tested, as given in the
-- second argument, are available in the FPGA family that
-- is given in the first argument.
--
-- The first argument can be either one of the FPGA family
-- names from the enumeration type, 'families_type', or a
-- (case insensitive) string giving the same information.
-- The family name 'nofamily' is special and supports
-- none of the primitives.
--
-- The second argument is either a primitive or a list of
-- primitives. The set of primitive names that can be
-- tested is defined by the declaration of the
-- enumeration type, 'primitives_type'. The names are
-- the UNISIM-library names for the primitives, prefixed
-- by "u_". (The prefix avoids introducing a name that
-- conflicts with the component declaration for the primitive.)
--
-- The array type, 'primitive_array_type' is the basis for
-- forming lists of primitives. Typically, a fixed list
-- of primitves is expressed as a VHDL aggregate, a
-- comma separated list of primitives enclosed in
-- parentheses. (See the last two examples, above.)
--
-- The 'supported' function can be used as a guard
-- condition for a piece of code that depends on primitives
-- (primitive availability guard). Here is an example:
--
--
-- GEN : if supported(C_FAMILY, (u_MUXCY, u_XORCY)) generate
-- begin
-- ... Here, an implementation that depends on
-- ... MUXCY and XORCY.
-- end generate;
--
--
-- It can also be used in an assertion statement
-- to give warnings about problems that can arise from
-- attempting to implement into a family that does not
-- support all of the required primitives:
--
--
-- assert supported(C_FAMILY, <primtive list>)
-- report "This module cannot be implemnted " &
-- "into family, " & C_FAMILY &
-- ", because one or more of the primitives, " &
-- "<primitive_list>" & ", is not supported."
-- severity error;
--
--
-- A NOTE ON USAGE
--
-- It is probably best to take an exception to the coding
-- guidelines and make the names that are needed
-- from this package visible to a VHDL compilation unit by
--
-- library <libname>;
-- use <libname>.family_support.all;
--
-- rather than by calling out individual names in use clauses.
-- (VHDL tools do not have a common interpretation at present
-- on whether
--
-- use <libname>.family_support.primitives_type"
--
-- makes the enumeration literals visible.)
--
-- ADDITIONAL FEATURES
--
-- - A function, native_lut_size, is available to allow
-- the caller to query the largest sized LUT available in a given
-- FPGA family.
--
-- - A function, equalIgnoringCase, is available to compare strings
-- with case insensitivity. While this can be used to establish
-- whether the target family is some particular family, such
-- usage is discouraged and should be limited to legacy
-- situations or the rare situations where primitive
-- availability guards will not suffice.
--
--------------------------------------------------------------------------------
-- Author: FLO
-- History:
-- FLO 2005Mar24 - First Version
--
-- FLO 11/30/05
-- ^^^^^^
-- Virtex5 added.
-- ~~~~~~
-- TK 03/17/06 Corrected a Spartan3e issue in myimage
-- ~~~~~~
-- FLO 04/26/06
-- ^^^^^^
-- Added the native_lut_size function.
-- ~~~~~~
-- FLO 08/10/06
-- ^^^^^^
-- Added support for families virtex, spartan2 and spartan2e.
-- ~~~~~~
-- FLO 08/25/06
-- ^^^^^^
-- Enhanced the warning in function str2fam. Now when a string that is
-- passed in the call as a parameter does not correspond to a supported fpga
-- family, the string value of the passed string is mentioned in the warning
-- and it is explicitly stated that the returned value is 'nofamily'.
-- ~~~~~~
-- FLO 08/26/06
-- ^^^^^^
-- - Updated the virtex5 primitive set to a more recent list and
-- removed primitives (TEMAC, PCIE, etc.) that are not present
-- in all virtex5 family members.
-- - Added function equalIgnoringCase and an admonition to use it
-- as little as possible.
-- - Made some improvements to descriptions inside comments.
-- ~~~~~~
-- FLO 08/28/06
-- ^^^^^^
-- Added support for families spartan3a and spartan3an. These are initially
-- taken to have the same primitives as spartan3e.
-- ~~~~~~
-- FLO 10/28/06
-- ^^^^^^
-- Changed function str2fam so that it no longer depends on the VHDL
-- attribute, 'VAL. This is an XST workaround.
-- ~~~~~~
-- FLO 03/08/07
-- ^^^^^^
-- Updated spartan3a and sparan3an.
-- Added spartan3adsp.
-- ~~~~~~
-- FLO 08/31/07
-- ^^^^^^
-- A performance XST workaround was implemented to address slowness
-- associated with primitive availability guards. The workaround changes
-- the way that the fam_has_prim constant is initialized (aggregate
-- rather than a system of function and procedure calls).
-- ~~~~~~
-- FLO 04/11/08
-- ^^^^^^
-- Added these families: aspartan3e, aspartan3a, aspartan3an, aspartan3adsp
-- ~~~~~~
-- FLO 04/14/08
-- ^^^^^^
-- Removed family: aspartan3an
-- ~~~~~~
-- FLO 06/25/08
-- ^^^^^^
-- Added these families: qvirtex4, qrvirtex4
-- ~~~~~~
-- FLO 07/26/08
-- ^^^^^^
-- The BSCAN primitive for spartan3e is now BSCAN_SPARTAN3 instead
-- of BSCAN_SPARTAN3E.
-- ~~~~~~
-- FLO 09/02/06
-- ^^^^^^
-- Added an initial approximation of primitives for spartan6 and virtex6.
-- ~~~~~~
-- FLO 09/04/28
-- ^^^^^^
-- -Removed primitive u_BSCAN_SPARTAN3A from spartan6.
-- -Added the 5 and 6 LUTs to spartan6.
-- ~~~~~~
-- FLO 02/09/10 (back to MM/DD/YY)
-- ^^^^^^
-- -Removed primitive u_BSCAN_VIRTEX5 from virtex6.
-- -Added families spartan6l, qspartan6, aspartan6 and virtex6l.
-- ~~~~~~
-- FLO 04/26/10 (MM/DD/YY)
-- ^^^^^^
-- -Added families qspartan6l, qvirtex5 and qvirtex6.
-- ~~~~~~
-- FLO 06/21/10 (MM/DD/YY)
-- ^^^^^^
-- -Added family qrvirtex5.
-- ~~~~~~
--
-- DET 9/7/2010 For 12.4
-- ~~~~~~
-- -- Per CR573867
-- - Added the function get_root_family() as part of the derivative part
-- support improvements.
-- - Added the Virtex7 and Kintex7 device families
-- ^^^^^^
-- ~~~~~~
-- FLO 10/28/10 (MM/DD/YY)
-- ^^^^^^
-- -Added u_SRLC32E as supported for spartan6 (and its derivatives). (CR 575828)
-- ~~~~~~
-- FLO 12/15/10 (MM/DD/YY)
-- ^^^^^^
-- -Changed virtex6cx to be equal to virtex6 (instead of virtex5)
-- -Move kintex7 and virtex7 to the primitives in the Rodin unisim.btl file
-- -Added artix7 from the primitives in the Rodin unisim.btl file
-- ~~~~~~
--
-- DET 3/2/2011 EDk 13.2
-- ~~~~~~
-- -- Per CR595477
-- - Added zynq support in the get_root_family function.
-- ^^^^^^
--
-- DET 03/18/2011
-- ^^^^^^
-- Per CR602290
-- - Added u_RAMB16_S4_S36 for kintex7, virtex7, artix7 to grandfather axi_ethernetlite_v1_00_a.
-- - This change was lost from 13.1 O.40d to 13.2 branch.
-- - Copied the Virtex7 primitive info to zynq primitive entry (instead of the artix7 info)
-- ~~~~~~
--
-- DET 4/4/2011 EDK 13.2
-- ~~~~~~
-- -- Per CR604652
-- - Added kintex7l and virtex7l
-- ^^^^^^
--
--------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinational signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports:- Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
--------------------------------------------------------------------------------
package family_support is
type families_type is
(
nofamily
, virtex
, spartan2
, spartan2e
, virtexe
, virtex2
, qvirtex2 -- Taken to be identical to the virtex2 primitive set.
, qrvirtex2 -- Taken to be identical to the virtex2 primitive set.
, virtex2p
, spartan3
, aspartan3
, virtex4
, virtex4lx
, virtex4fx
, virtex4sx
, spartan3e
, virtex5
, spartan3a
, spartan3an
, spartan3adsp
, aspartan3e
, aspartan3a
, aspartan3adsp
, qvirtex4
, qrvirtex4
, spartan6
, virtex6
, spartan6l
, qspartan6
, aspartan6
, virtex6l
, qspartan6l
, qvirtex5
, qvirtex6
, qrvirtex5
, virtex5tx
, virtex5fx
, virtex6cx
, kintex7
, kintex7l
, qkintex7
, qkintex7l
, virtex7
, virtex7l
, qvirtex7
, qvirtex7l
, artix7
, aartix7
, artix7l
, qartix7
, qartix7l
, zynq
, azynq
, qzynq
);
type primitives_type is range 0 to 798;
constant u_AND2: primitives_type := 0;
constant u_AND2B1L: primitives_type := u_AND2 + 1;
constant u_AND3: primitives_type := u_AND2B1L + 1;
constant u_AND4: primitives_type := u_AND3 + 1;
constant u_AUTOBUF: primitives_type := u_AND4 + 1;
constant u_BSCAN_SPARTAN2: primitives_type := u_AUTOBUF + 1;
constant u_BSCAN_SPARTAN3: primitives_type := u_BSCAN_SPARTAN2 + 1;
constant u_BSCAN_SPARTAN3A: primitives_type := u_BSCAN_SPARTAN3 + 1;
constant u_BSCAN_SPARTAN3E: primitives_type := u_BSCAN_SPARTAN3A + 1;
constant u_BSCAN_SPARTAN6: primitives_type := u_BSCAN_SPARTAN3E + 1;
constant u_BSCAN_VIRTEX: primitives_type := u_BSCAN_SPARTAN6 + 1;
constant u_BSCAN_VIRTEX2: primitives_type := u_BSCAN_VIRTEX + 1;
constant u_BSCAN_VIRTEX4: primitives_type := u_BSCAN_VIRTEX2 + 1;
constant u_BSCAN_VIRTEX5: primitives_type := u_BSCAN_VIRTEX4 + 1;
constant u_BSCAN_VIRTEX6: primitives_type := u_BSCAN_VIRTEX5 + 1;
constant u_BUF: primitives_type := u_BSCAN_VIRTEX6 + 1;
constant u_BUFCF: primitives_type := u_BUF + 1;
constant u_BUFE: primitives_type := u_BUFCF + 1;
constant u_BUFG: primitives_type := u_BUFE + 1;
constant u_BUFGCE: primitives_type := u_BUFG + 1;
constant u_BUFGCE_1: primitives_type := u_BUFGCE + 1;
constant u_BUFGCTRL: primitives_type := u_BUFGCE_1 + 1;
constant u_BUFGDLL: primitives_type := u_BUFGCTRL + 1;
constant u_BUFGMUX: primitives_type := u_BUFGDLL + 1;
constant u_BUFGMUX_1: primitives_type := u_BUFGMUX + 1;
constant u_BUFGMUX_CTRL: primitives_type := u_BUFGMUX_1 + 1;
constant u_BUFGMUX_VIRTEX4: primitives_type := u_BUFGMUX_CTRL + 1;
constant u_BUFGP: primitives_type := u_BUFGMUX_VIRTEX4 + 1;
constant u_BUFH: primitives_type := u_BUFGP + 1;
constant u_BUFHCE: primitives_type := u_BUFH + 1;
constant u_BUFIO: primitives_type := u_BUFHCE + 1;
constant u_BUFIO2: primitives_type := u_BUFIO + 1;
constant u_BUFIO2_2CLK: primitives_type := u_BUFIO2 + 1;
constant u_BUFIO2FB: primitives_type := u_BUFIO2_2CLK + 1;
constant u_BUFIO2FB_2CLK: primitives_type := u_BUFIO2FB + 1;
constant u_BUFIODQS: primitives_type := u_BUFIO2FB_2CLK + 1;
constant u_BUFPLL: primitives_type := u_BUFIODQS + 1;
constant u_BUFPLL_MCB: primitives_type := u_BUFPLL + 1;
constant u_BUFR: primitives_type := u_BUFPLL_MCB + 1;
constant u_BUFT: primitives_type := u_BUFR + 1;
constant u_CAPTURE_SPARTAN2: primitives_type := u_BUFT + 1;
constant u_CAPTURE_SPARTAN3: primitives_type := u_CAPTURE_SPARTAN2 + 1;
constant u_CAPTURE_SPARTAN3A: primitives_type := u_CAPTURE_SPARTAN3 + 1;
constant u_CAPTURE_SPARTAN3E: primitives_type := u_CAPTURE_SPARTAN3A + 1;
constant u_CAPTURE_VIRTEX: primitives_type := u_CAPTURE_SPARTAN3E + 1;
constant u_CAPTURE_VIRTEX2: primitives_type := u_CAPTURE_VIRTEX + 1;
constant u_CAPTURE_VIRTEX4: primitives_type := u_CAPTURE_VIRTEX2 + 1;
constant u_CAPTURE_VIRTEX5: primitives_type := u_CAPTURE_VIRTEX4 + 1;
constant u_CAPTURE_VIRTEX6: primitives_type := u_CAPTURE_VIRTEX5 + 1;
constant u_CARRY4: primitives_type := u_CAPTURE_VIRTEX6 + 1;
constant u_CFGLUT5: primitives_type := u_CARRY4 + 1;
constant u_CLKDLL: primitives_type := u_CFGLUT5 + 1;
constant u_CLKDLLE: primitives_type := u_CLKDLL + 1;
constant u_CLKDLLHF: primitives_type := u_CLKDLLE + 1;
constant u_CRC32: primitives_type := u_CLKDLLHF + 1;
constant u_CRC64: primitives_type := u_CRC32 + 1;
constant u_DCIRESET: primitives_type := u_CRC64 + 1;
constant u_DCM: primitives_type := u_DCIRESET + 1;
constant u_DCM_ADV: primitives_type := u_DCM + 1;
constant u_DCM_BASE: primitives_type := u_DCM_ADV + 1;
constant u_DCM_CLKGEN: primitives_type := u_DCM_BASE + 1;
constant u_DCM_PS: primitives_type := u_DCM_CLKGEN + 1;
constant u_DNA_PORT: primitives_type := u_DCM_PS + 1;
constant u_DSP48: primitives_type := u_DNA_PORT + 1;
constant u_DSP48A: primitives_type := u_DSP48 + 1;
constant u_DSP48A1: primitives_type := u_DSP48A + 1;
constant u_DSP48E: primitives_type := u_DSP48A1 + 1;
constant u_DSP48E1: primitives_type := u_DSP48E + 1;
constant u_DUMMY_INV: primitives_type := u_DSP48E1 + 1;
constant u_DUMMY_NOR2: primitives_type := u_DUMMY_INV + 1;
constant u_EFUSE_USR: primitives_type := u_DUMMY_NOR2 + 1;
constant u_EMAC: primitives_type := u_EFUSE_USR + 1;
constant u_FD: primitives_type := u_EMAC + 1;
constant u_FD_1: primitives_type := u_FD + 1;
constant u_FDC: primitives_type := u_FD_1 + 1;
constant u_FDC_1: primitives_type := u_FDC + 1;
constant u_FDCE: primitives_type := u_FDC_1 + 1;
constant u_FDCE_1: primitives_type := u_FDCE + 1;
constant u_FDCP: primitives_type := u_FDCE_1 + 1;
constant u_FDCP_1: primitives_type := u_FDCP + 1;
constant u_FDCPE: primitives_type := u_FDCP_1 + 1;
constant u_FDCPE_1: primitives_type := u_FDCPE + 1;
constant u_FDDRCPE: primitives_type := u_FDCPE_1 + 1;
constant u_FDDRRSE: primitives_type := u_FDDRCPE + 1;
constant u_FDE: primitives_type := u_FDDRRSE + 1;
constant u_FDE_1: primitives_type := u_FDE + 1;
constant u_FDP: primitives_type := u_FDE_1 + 1;
constant u_FDP_1: primitives_type := u_FDP + 1;
constant u_FDPE: primitives_type := u_FDP_1 + 1;
constant u_FDPE_1: primitives_type := u_FDPE + 1;
constant u_FDR: primitives_type := u_FDPE_1 + 1;
constant u_FDR_1: primitives_type := u_FDR + 1;
constant u_FDRE: primitives_type := u_FDR_1 + 1;
constant u_FDRE_1: primitives_type := u_FDRE + 1;
constant u_FDRS: primitives_type := u_FDRE_1 + 1;
constant u_FDRS_1: primitives_type := u_FDRS + 1;
constant u_FDRSE: primitives_type := u_FDRS_1 + 1;
constant u_FDRSE_1: primitives_type := u_FDRSE + 1;
constant u_FDS: primitives_type := u_FDRSE_1 + 1;
constant u_FDS_1: primitives_type := u_FDS + 1;
constant u_FDSE: primitives_type := u_FDS_1 + 1;
constant u_FDSE_1: primitives_type := u_FDSE + 1;
constant u_FIFO16: primitives_type := u_FDSE_1 + 1;
constant u_FIFO18: primitives_type := u_FIFO16 + 1;
constant u_FIFO18_36: primitives_type := u_FIFO18 + 1;
constant u_FIFO18E1: primitives_type := u_FIFO18_36 + 1;
constant u_FIFO36: primitives_type := u_FIFO18E1 + 1;
constant u_FIFO36_72: primitives_type := u_FIFO36 + 1;
constant u_FIFO36E1: primitives_type := u_FIFO36_72 + 1;
constant u_FMAP: primitives_type := u_FIFO36E1 + 1;
constant u_FRAME_ECC_VIRTEX4: primitives_type := u_FMAP + 1;
constant u_FRAME_ECC_VIRTEX5: primitives_type := u_FRAME_ECC_VIRTEX4 + 1;
constant u_FRAME_ECC_VIRTEX6: primitives_type := u_FRAME_ECC_VIRTEX5 + 1;
constant u_GND: primitives_type := u_FRAME_ECC_VIRTEX6 + 1;
constant u_GT10_10GE_4: primitives_type := u_GND + 1;
constant u_GT10_10GE_8: primitives_type := u_GT10_10GE_4 + 1;
constant u_GT10_10GFC_4: primitives_type := u_GT10_10GE_8 + 1;
constant u_GT10_10GFC_8: primitives_type := u_GT10_10GFC_4 + 1;
constant u_GT10_AURORA_1: primitives_type := u_GT10_10GFC_8 + 1;
constant u_GT10_AURORA_2: primitives_type := u_GT10_AURORA_1 + 1;
constant u_GT10_AURORA_4: primitives_type := u_GT10_AURORA_2 + 1;
constant u_GT10_AURORAX_4: primitives_type := u_GT10_AURORA_4 + 1;
constant u_GT10_AURORAX_8: primitives_type := u_GT10_AURORAX_4 + 1;
constant u_GT10_CUSTOM: primitives_type := u_GT10_AURORAX_8 + 1;
constant u_GT10_INFINIBAND_1: primitives_type := u_GT10_CUSTOM + 1;
constant u_GT10_INFINIBAND_2: primitives_type := u_GT10_INFINIBAND_1 + 1;
constant u_GT10_INFINIBAND_4: primitives_type := u_GT10_INFINIBAND_2 + 1;
constant u_GT10_OC192_4: primitives_type := u_GT10_INFINIBAND_4 + 1;
constant u_GT10_OC192_8: primitives_type := u_GT10_OC192_4 + 1;
constant u_GT10_OC48_1: primitives_type := u_GT10_OC192_8 + 1;
constant u_GT10_OC48_2: primitives_type := u_GT10_OC48_1 + 1;
constant u_GT10_OC48_4: primitives_type := u_GT10_OC48_2 + 1;
constant u_GT10_PCI_EXPRESS_1: primitives_type := u_GT10_OC48_4 + 1;
constant u_GT10_PCI_EXPRESS_2: primitives_type := u_GT10_PCI_EXPRESS_1 + 1;
constant u_GT10_PCI_EXPRESS_4: primitives_type := u_GT10_PCI_EXPRESS_2 + 1;
constant u_GT10_XAUI_1: primitives_type := u_GT10_PCI_EXPRESS_4 + 1;
constant u_GT10_XAUI_2: primitives_type := u_GT10_XAUI_1 + 1;
constant u_GT10_XAUI_4: primitives_type := u_GT10_XAUI_2 + 1;
constant u_GT11CLK: primitives_type := u_GT10_XAUI_4 + 1;
constant u_GT11CLK_MGT: primitives_type := u_GT11CLK + 1;
constant u_GT11_CUSTOM: primitives_type := u_GT11CLK_MGT + 1;
constant u_GT_AURORA_1: primitives_type := u_GT11_CUSTOM + 1;
constant u_GT_AURORA_2: primitives_type := u_GT_AURORA_1 + 1;
constant u_GT_AURORA_4: primitives_type := u_GT_AURORA_2 + 1;
constant u_GT_CUSTOM: primitives_type := u_GT_AURORA_4 + 1;
constant u_GT_ETHERNET_1: primitives_type := u_GT_CUSTOM + 1;
constant u_GT_ETHERNET_2: primitives_type := u_GT_ETHERNET_1 + 1;
constant u_GT_ETHERNET_4: primitives_type := u_GT_ETHERNET_2 + 1;
constant u_GT_FIBRE_CHAN_1: primitives_type := u_GT_ETHERNET_4 + 1;
constant u_GT_FIBRE_CHAN_2: primitives_type := u_GT_FIBRE_CHAN_1 + 1;
constant u_GT_FIBRE_CHAN_4: primitives_type := u_GT_FIBRE_CHAN_2 + 1;
constant u_GT_INFINIBAND_1: primitives_type := u_GT_FIBRE_CHAN_4 + 1;
constant u_GT_INFINIBAND_2: primitives_type := u_GT_INFINIBAND_1 + 1;
constant u_GT_INFINIBAND_4: primitives_type := u_GT_INFINIBAND_2 + 1;
constant u_GTPA1_DUAL: primitives_type := u_GT_INFINIBAND_4 + 1;
constant u_GT_XAUI_1: primitives_type := u_GTPA1_DUAL + 1;
constant u_GT_XAUI_2: primitives_type := u_GT_XAUI_1 + 1;
constant u_GT_XAUI_4: primitives_type := u_GT_XAUI_2 + 1;
constant u_GTXE1: primitives_type := u_GT_XAUI_4 + 1;
constant u_IBUF: primitives_type := u_GTXE1 + 1;
constant u_IBUF_AGP: primitives_type := u_IBUF + 1;
constant u_IBUF_CTT: primitives_type := u_IBUF_AGP + 1;
constant u_IBUF_DLY_ADJ: primitives_type := u_IBUF_CTT + 1;
constant u_IBUFDS: primitives_type := u_IBUF_DLY_ADJ + 1;
constant u_IBUFDS_DIFF_OUT: primitives_type := u_IBUFDS + 1;
constant u_IBUFDS_DLY_ADJ: primitives_type := u_IBUFDS_DIFF_OUT + 1;
constant u_IBUFDS_GTXE1: primitives_type := u_IBUFDS_DLY_ADJ + 1;
constant u_IBUFG: primitives_type := u_IBUFDS_GTXE1 + 1;
constant u_IBUFG_AGP: primitives_type := u_IBUFG + 1;
constant u_IBUFG_CTT: primitives_type := u_IBUFG_AGP + 1;
constant u_IBUFGDS: primitives_type := u_IBUFG_CTT + 1;
constant u_IBUFGDS_DIFF_OUT: primitives_type := u_IBUFGDS + 1;
constant u_IBUFG_GTL: primitives_type := u_IBUFGDS_DIFF_OUT + 1;
constant u_IBUFG_GTLP: primitives_type := u_IBUFG_GTL + 1;
constant u_IBUFG_HSTL_I: primitives_type := u_IBUFG_GTLP + 1;
constant u_IBUFG_HSTL_III: primitives_type := u_IBUFG_HSTL_I + 1;
constant u_IBUFG_HSTL_IV: primitives_type := u_IBUFG_HSTL_III + 1;
constant u_IBUFG_LVCMOS18: primitives_type := u_IBUFG_HSTL_IV + 1;
constant u_IBUFG_LVCMOS2: primitives_type := u_IBUFG_LVCMOS18 + 1;
constant u_IBUFG_LVDS: primitives_type := u_IBUFG_LVCMOS2 + 1;
constant u_IBUFG_LVPECL: primitives_type := u_IBUFG_LVDS + 1;
constant u_IBUFG_PCI33_3: primitives_type := u_IBUFG_LVPECL + 1;
constant u_IBUFG_PCI33_5: primitives_type := u_IBUFG_PCI33_3 + 1;
constant u_IBUFG_PCI66_3: primitives_type := u_IBUFG_PCI33_5 + 1;
constant u_IBUFG_PCIX66_3: primitives_type := u_IBUFG_PCI66_3 + 1;
constant u_IBUFG_SSTL2_I: primitives_type := u_IBUFG_PCIX66_3 + 1;
constant u_IBUFG_SSTL2_II: primitives_type := u_IBUFG_SSTL2_I + 1;
constant u_IBUFG_SSTL3_I: primitives_type := u_IBUFG_SSTL2_II + 1;
constant u_IBUFG_SSTL3_II: primitives_type := u_IBUFG_SSTL3_I + 1;
constant u_IBUF_GTL: primitives_type := u_IBUFG_SSTL3_II + 1;
constant u_IBUF_GTLP: primitives_type := u_IBUF_GTL + 1;
constant u_IBUF_HSTL_I: primitives_type := u_IBUF_GTLP + 1;
constant u_IBUF_HSTL_III: primitives_type := u_IBUF_HSTL_I + 1;
constant u_IBUF_HSTL_IV: primitives_type := u_IBUF_HSTL_III + 1;
constant u_IBUF_LVCMOS18: primitives_type := u_IBUF_HSTL_IV + 1;
constant u_IBUF_LVCMOS2: primitives_type := u_IBUF_LVCMOS18 + 1;
constant u_IBUF_LVDS: primitives_type := u_IBUF_LVCMOS2 + 1;
constant u_IBUF_LVPECL: primitives_type := u_IBUF_LVDS + 1;
constant u_IBUF_PCI33_3: primitives_type := u_IBUF_LVPECL + 1;
constant u_IBUF_PCI33_5: primitives_type := u_IBUF_PCI33_3 + 1;
constant u_IBUF_PCI66_3: primitives_type := u_IBUF_PCI33_5 + 1;
constant u_IBUF_PCIX66_3: primitives_type := u_IBUF_PCI66_3 + 1;
constant u_IBUF_SSTL2_I: primitives_type := u_IBUF_PCIX66_3 + 1;
constant u_IBUF_SSTL2_II: primitives_type := u_IBUF_SSTL2_I + 1;
constant u_IBUF_SSTL3_I: primitives_type := u_IBUF_SSTL2_II + 1;
constant u_IBUF_SSTL3_II: primitives_type := u_IBUF_SSTL3_I + 1;
constant u_ICAP_SPARTAN3A: primitives_type := u_IBUF_SSTL3_II + 1;
constant u_ICAP_SPARTAN6: primitives_type := u_ICAP_SPARTAN3A + 1;
constant u_ICAP_VIRTEX2: primitives_type := u_ICAP_SPARTAN6 + 1;
constant u_ICAP_VIRTEX4: primitives_type := u_ICAP_VIRTEX2 + 1;
constant u_ICAP_VIRTEX5: primitives_type := u_ICAP_VIRTEX4 + 1;
constant u_ICAP_VIRTEX6: primitives_type := u_ICAP_VIRTEX5 + 1;
constant u_IDDR: primitives_type := u_ICAP_VIRTEX6 + 1;
constant u_IDDR2: primitives_type := u_IDDR + 1;
constant u_IDDR_2CLK: primitives_type := u_IDDR2 + 1;
constant u_IDELAY: primitives_type := u_IDDR_2CLK + 1;
constant u_IDELAYCTRL: primitives_type := u_IDELAY + 1;
constant u_IFDDRCPE: primitives_type := u_IDELAYCTRL + 1;
constant u_IFDDRRSE: primitives_type := u_IFDDRCPE + 1;
constant u_INV: primitives_type := u_IFDDRRSE + 1;
constant u_IOBUF: primitives_type := u_INV + 1;
constant u_IOBUF_AGP: primitives_type := u_IOBUF + 1;
constant u_IOBUF_CTT: primitives_type := u_IOBUF_AGP + 1;
constant u_IOBUFDS: primitives_type := u_IOBUF_CTT + 1;
constant u_IOBUFDS_DIFF_OUT: primitives_type := u_IOBUFDS + 1;
constant u_IOBUF_F_12: primitives_type := u_IOBUFDS_DIFF_OUT + 1;
constant u_IOBUF_F_16: primitives_type := u_IOBUF_F_12 + 1;
constant u_IOBUF_F_2: primitives_type := u_IOBUF_F_16 + 1;
constant u_IOBUF_F_24: primitives_type := u_IOBUF_F_2 + 1;
constant u_IOBUF_F_4: primitives_type := u_IOBUF_F_24 + 1;
constant u_IOBUF_F_6: primitives_type := u_IOBUF_F_4 + 1;
constant u_IOBUF_F_8: primitives_type := u_IOBUF_F_6 + 1;
constant u_IOBUF_GTL: primitives_type := u_IOBUF_F_8 + 1;
constant u_IOBUF_GTLP: primitives_type := u_IOBUF_GTL + 1;
constant u_IOBUF_HSTL_I: primitives_type := u_IOBUF_GTLP + 1;
constant u_IOBUF_HSTL_III: primitives_type := u_IOBUF_HSTL_I + 1;
constant u_IOBUF_HSTL_IV: primitives_type := u_IOBUF_HSTL_III + 1;
constant u_IOBUF_LVCMOS18: primitives_type := u_IOBUF_HSTL_IV + 1;
constant u_IOBUF_LVCMOS2: primitives_type := u_IOBUF_LVCMOS18 + 1;
constant u_IOBUF_LVDS: primitives_type := u_IOBUF_LVCMOS2 + 1;
constant u_IOBUF_LVPECL: primitives_type := u_IOBUF_LVDS + 1;
constant u_IOBUF_PCI33_3: primitives_type := u_IOBUF_LVPECL + 1;
constant u_IOBUF_PCI33_5: primitives_type := u_IOBUF_PCI33_3 + 1;
constant u_IOBUF_PCI66_3: primitives_type := u_IOBUF_PCI33_5 + 1;
constant u_IOBUF_PCIX66_3: primitives_type := u_IOBUF_PCI66_3 + 1;
constant u_IOBUF_S_12: primitives_type := u_IOBUF_PCIX66_3 + 1;
constant u_IOBUF_S_16: primitives_type := u_IOBUF_S_12 + 1;
constant u_IOBUF_S_2: primitives_type := u_IOBUF_S_16 + 1;
constant u_IOBUF_S_24: primitives_type := u_IOBUF_S_2 + 1;
constant u_IOBUF_S_4: primitives_type := u_IOBUF_S_24 + 1;
constant u_IOBUF_S_6: primitives_type := u_IOBUF_S_4 + 1;
constant u_IOBUF_S_8: primitives_type := u_IOBUF_S_6 + 1;
constant u_IOBUF_SSTL2_I: primitives_type := u_IOBUF_S_8 + 1;
constant u_IOBUF_SSTL2_II: primitives_type := u_IOBUF_SSTL2_I + 1;
constant u_IOBUF_SSTL3_I: primitives_type := u_IOBUF_SSTL2_II + 1;
constant u_IOBUF_SSTL3_II: primitives_type := u_IOBUF_SSTL3_I + 1;
constant u_IODELAY: primitives_type := u_IOBUF_SSTL3_II + 1;
constant u_IODELAY2: primitives_type := u_IODELAY + 1;
constant u_IODELAYE1: primitives_type := u_IODELAY2 + 1;
constant u_IODRP2: primitives_type := u_IODELAYE1 + 1;
constant u_IODRP2_MCB: primitives_type := u_IODRP2 + 1;
constant u_ISERDES: primitives_type := u_IODRP2_MCB + 1;
constant u_ISERDES2: primitives_type := u_ISERDES + 1;
constant u_ISERDESE1: primitives_type := u_ISERDES2 + 1;
constant u_ISERDES_NODELAY: primitives_type := u_ISERDESE1 + 1;
constant u_JTAGPPC: primitives_type := u_ISERDES_NODELAY + 1;
constant u_JTAG_SIM_SPARTAN6: primitives_type := u_JTAGPPC + 1;
constant u_JTAG_SIM_VIRTEX6: primitives_type := u_JTAG_SIM_SPARTAN6 + 1;
constant u_KEEPER: primitives_type := u_JTAG_SIM_VIRTEX6 + 1;
constant u_KEY_CLEAR: primitives_type := u_KEEPER + 1;
constant u_LD: primitives_type := u_KEY_CLEAR + 1;
constant u_LD_1: primitives_type := u_LD + 1;
constant u_LDC: primitives_type := u_LD_1 + 1;
constant u_LDC_1: primitives_type := u_LDC + 1;
constant u_LDCE: primitives_type := u_LDC_1 + 1;
constant u_LDCE_1: primitives_type := u_LDCE + 1;
constant u_LDCP: primitives_type := u_LDCE_1 + 1;
constant u_LDCP_1: primitives_type := u_LDCP + 1;
constant u_LDCPE: primitives_type := u_LDCP_1 + 1;
constant u_LDCPE_1: primitives_type := u_LDCPE + 1;
constant u_LDE: primitives_type := u_LDCPE_1 + 1;
constant u_LDE_1: primitives_type := u_LDE + 1;
constant u_LDP: primitives_type := u_LDE_1 + 1;
constant u_LDP_1: primitives_type := u_LDP + 1;
constant u_LDPE: primitives_type := u_LDP_1 + 1;
constant u_LDPE_1: primitives_type := u_LDPE + 1;
constant u_LUT1: primitives_type := u_LDPE_1 + 1;
constant u_LUT1_D: primitives_type := u_LUT1 + 1;
constant u_LUT1_L: primitives_type := u_LUT1_D + 1;
constant u_LUT2: primitives_type := u_LUT1_L + 1;
constant u_LUT2_D: primitives_type := u_LUT2 + 1;
constant u_LUT2_L: primitives_type := u_LUT2_D + 1;
constant u_LUT3: primitives_type := u_LUT2_L + 1;
constant u_LUT3_D: primitives_type := u_LUT3 + 1;
constant u_LUT3_L: primitives_type := u_LUT3_D + 1;
constant u_LUT4: primitives_type := u_LUT3_L + 1;
constant u_LUT4_D: primitives_type := u_LUT4 + 1;
constant u_LUT4_L: primitives_type := u_LUT4_D + 1;
constant u_LUT5: primitives_type := u_LUT4_L + 1;
constant u_LUT5_D: primitives_type := u_LUT5 + 1;
constant u_LUT5_L: primitives_type := u_LUT5_D + 1;
constant u_LUT6: primitives_type := u_LUT5_L + 1;
constant u_LUT6_D: primitives_type := u_LUT6 + 1;
constant u_LUT6_L: primitives_type := u_LUT6_D + 1;
constant u_MCB: primitives_type := u_LUT6_L + 1;
constant u_MMCM_ADV: primitives_type := u_MCB + 1;
constant u_MMCM_BASE: primitives_type := u_MMCM_ADV + 1;
constant u_MULT18X18: primitives_type := u_MMCM_BASE + 1;
constant u_MULT18X18S: primitives_type := u_MULT18X18 + 1;
constant u_MULT18X18SIO: primitives_type := u_MULT18X18S + 1;
constant u_MULT_AND: primitives_type := u_MULT18X18SIO + 1;
constant u_MUXCY: primitives_type := u_MULT_AND + 1;
constant u_MUXCY_D: primitives_type := u_MUXCY + 1;
constant u_MUXCY_L: primitives_type := u_MUXCY_D + 1;
constant u_MUXF5: primitives_type := u_MUXCY_L + 1;
constant u_MUXF5_D: primitives_type := u_MUXF5 + 1;
constant u_MUXF5_L: primitives_type := u_MUXF5_D + 1;
constant u_MUXF6: primitives_type := u_MUXF5_L + 1;
constant u_MUXF6_D: primitives_type := u_MUXF6 + 1;
constant u_MUXF6_L: primitives_type := u_MUXF6_D + 1;
constant u_MUXF7: primitives_type := u_MUXF6_L + 1;
constant u_MUXF7_D: primitives_type := u_MUXF7 + 1;
constant u_MUXF7_L: primitives_type := u_MUXF7_D + 1;
constant u_MUXF8: primitives_type := u_MUXF7_L + 1;
constant u_MUXF8_D: primitives_type := u_MUXF8 + 1;
constant u_MUXF8_L: primitives_type := u_MUXF8_D + 1;
constant u_NAND2: primitives_type := u_MUXF8_L + 1;
constant u_NAND3: primitives_type := u_NAND2 + 1;
constant u_NAND4: primitives_type := u_NAND3 + 1;
constant u_NOR2: primitives_type := u_NAND4 + 1;
constant u_NOR3: primitives_type := u_NOR2 + 1;
constant u_NOR4: primitives_type := u_NOR3 + 1;
constant u_OBUF: primitives_type := u_NOR4 + 1;
constant u_OBUF_AGP: primitives_type := u_OBUF + 1;
constant u_OBUF_CTT: primitives_type := u_OBUF_AGP + 1;
constant u_OBUFDS: primitives_type := u_OBUF_CTT + 1;
constant u_OBUF_F_12: primitives_type := u_OBUFDS + 1;
constant u_OBUF_F_16: primitives_type := u_OBUF_F_12 + 1;
constant u_OBUF_F_2: primitives_type := u_OBUF_F_16 + 1;
constant u_OBUF_F_24: primitives_type := u_OBUF_F_2 + 1;
constant u_OBUF_F_4: primitives_type := u_OBUF_F_24 + 1;
constant u_OBUF_F_6: primitives_type := u_OBUF_F_4 + 1;
constant u_OBUF_F_8: primitives_type := u_OBUF_F_6 + 1;
constant u_OBUF_GTL: primitives_type := u_OBUF_F_8 + 1;
constant u_OBUF_GTLP: primitives_type := u_OBUF_GTL + 1;
constant u_OBUF_HSTL_I: primitives_type := u_OBUF_GTLP + 1;
constant u_OBUF_HSTL_III: primitives_type := u_OBUF_HSTL_I + 1;
constant u_OBUF_HSTL_IV: primitives_type := u_OBUF_HSTL_III + 1;
constant u_OBUF_LVCMOS18: primitives_type := u_OBUF_HSTL_IV + 1;
constant u_OBUF_LVCMOS2: primitives_type := u_OBUF_LVCMOS18 + 1;
constant u_OBUF_LVDS: primitives_type := u_OBUF_LVCMOS2 + 1;
constant u_OBUF_LVPECL: primitives_type := u_OBUF_LVDS + 1;
constant u_OBUF_PCI33_3: primitives_type := u_OBUF_LVPECL + 1;
constant u_OBUF_PCI33_5: primitives_type := u_OBUF_PCI33_3 + 1;
constant u_OBUF_PCI66_3: primitives_type := u_OBUF_PCI33_5 + 1;
constant u_OBUF_PCIX66_3: primitives_type := u_OBUF_PCI66_3 + 1;
constant u_OBUF_S_12: primitives_type := u_OBUF_PCIX66_3 + 1;
constant u_OBUF_S_16: primitives_type := u_OBUF_S_12 + 1;
constant u_OBUF_S_2: primitives_type := u_OBUF_S_16 + 1;
constant u_OBUF_S_24: primitives_type := u_OBUF_S_2 + 1;
constant u_OBUF_S_4: primitives_type := u_OBUF_S_24 + 1;
constant u_OBUF_S_6: primitives_type := u_OBUF_S_4 + 1;
constant u_OBUF_S_8: primitives_type := u_OBUF_S_6 + 1;
constant u_OBUF_SSTL2_I: primitives_type := u_OBUF_S_8 + 1;
constant u_OBUF_SSTL2_II: primitives_type := u_OBUF_SSTL2_I + 1;
constant u_OBUF_SSTL3_I: primitives_type := u_OBUF_SSTL2_II + 1;
constant u_OBUF_SSTL3_II: primitives_type := u_OBUF_SSTL3_I + 1;
constant u_OBUFT: primitives_type := u_OBUF_SSTL3_II + 1;
constant u_OBUFT_AGP: primitives_type := u_OBUFT + 1;
constant u_OBUFT_CTT: primitives_type := u_OBUFT_AGP + 1;
constant u_OBUFTDS: primitives_type := u_OBUFT_CTT + 1;
constant u_OBUFT_F_12: primitives_type := u_OBUFTDS + 1;
constant u_OBUFT_F_16: primitives_type := u_OBUFT_F_12 + 1;
constant u_OBUFT_F_2: primitives_type := u_OBUFT_F_16 + 1;
constant u_OBUFT_F_24: primitives_type := u_OBUFT_F_2 + 1;
constant u_OBUFT_F_4: primitives_type := u_OBUFT_F_24 + 1;
constant u_OBUFT_F_6: primitives_type := u_OBUFT_F_4 + 1;
constant u_OBUFT_F_8: primitives_type := u_OBUFT_F_6 + 1;
constant u_OBUFT_GTL: primitives_type := u_OBUFT_F_8 + 1;
constant u_OBUFT_GTLP: primitives_type := u_OBUFT_GTL + 1;
constant u_OBUFT_HSTL_I: primitives_type := u_OBUFT_GTLP + 1;
constant u_OBUFT_HSTL_III: primitives_type := u_OBUFT_HSTL_I + 1;
constant u_OBUFT_HSTL_IV: primitives_type := u_OBUFT_HSTL_III + 1;
constant u_OBUFT_LVCMOS18: primitives_type := u_OBUFT_HSTL_IV + 1;
constant u_OBUFT_LVCMOS2: primitives_type := u_OBUFT_LVCMOS18 + 1;
constant u_OBUFT_LVDS: primitives_type := u_OBUFT_LVCMOS2 + 1;
constant u_OBUFT_LVPECL: primitives_type := u_OBUFT_LVDS + 1;
constant u_OBUFT_PCI33_3: primitives_type := u_OBUFT_LVPECL + 1;
constant u_OBUFT_PCI33_5: primitives_type := u_OBUFT_PCI33_3 + 1;
constant u_OBUFT_PCI66_3: primitives_type := u_OBUFT_PCI33_5 + 1;
constant u_OBUFT_PCIX66_3: primitives_type := u_OBUFT_PCI66_3 + 1;
constant u_OBUFT_S_12: primitives_type := u_OBUFT_PCIX66_3 + 1;
constant u_OBUFT_S_16: primitives_type := u_OBUFT_S_12 + 1;
constant u_OBUFT_S_2: primitives_type := u_OBUFT_S_16 + 1;
constant u_OBUFT_S_24: primitives_type := u_OBUFT_S_2 + 1;
constant u_OBUFT_S_4: primitives_type := u_OBUFT_S_24 + 1;
constant u_OBUFT_S_6: primitives_type := u_OBUFT_S_4 + 1;
constant u_OBUFT_S_8: primitives_type := u_OBUFT_S_6 + 1;
constant u_OBUFT_SSTL2_I: primitives_type := u_OBUFT_S_8 + 1;
constant u_OBUFT_SSTL2_II: primitives_type := u_OBUFT_SSTL2_I + 1;
constant u_OBUFT_SSTL3_I: primitives_type := u_OBUFT_SSTL2_II + 1;
constant u_OBUFT_SSTL3_II: primitives_type := u_OBUFT_SSTL3_I + 1;
constant u_OCT_CALIBRATE: primitives_type := u_OBUFT_SSTL3_II + 1;
constant u_ODDR: primitives_type := u_OCT_CALIBRATE + 1;
constant u_ODDR2: primitives_type := u_ODDR + 1;
constant u_OFDDRCPE: primitives_type := u_ODDR2 + 1;
constant u_OFDDRRSE: primitives_type := u_OFDDRCPE + 1;
constant u_OFDDRTCPE: primitives_type := u_OFDDRRSE + 1;
constant u_OFDDRTRSE: primitives_type := u_OFDDRTCPE + 1;
constant u_OR2: primitives_type := u_OFDDRTRSE + 1;
constant u_OR2L: primitives_type := u_OR2 + 1;
constant u_OR3: primitives_type := u_OR2L + 1;
constant u_OR4: primitives_type := u_OR3 + 1;
constant u_ORCY: primitives_type := u_OR4 + 1;
constant u_OSERDES: primitives_type := u_ORCY + 1;
constant u_OSERDES2: primitives_type := u_OSERDES + 1;
constant u_OSERDESE1: primitives_type := u_OSERDES2 + 1;
constant u_PCIE_2_0: primitives_type := u_OSERDESE1 + 1;
constant u_PCIE_A1: primitives_type := u_PCIE_2_0 + 1;
constant u_PLL_ADV: primitives_type := u_PCIE_A1 + 1;
constant u_PLL_BASE: primitives_type := u_PLL_ADV + 1;
constant u_PMCD: primitives_type := u_PLL_BASE + 1;
constant u_POST_CRC_INTERNAL: primitives_type := u_PMCD + 1;
constant u_PPC405: primitives_type := u_POST_CRC_INTERNAL + 1;
constant u_PPC405_ADV: primitives_type := u_PPC405 + 1;
constant u_PPR_FRAME: primitives_type := u_PPC405_ADV + 1;
constant u_PULLDOWN: primitives_type := u_PPR_FRAME + 1;
constant u_PULLUP: primitives_type := u_PULLDOWN + 1;
constant u_RAM128X1D: primitives_type := u_PULLUP + 1;
constant u_RAM128X1S: primitives_type := u_RAM128X1D + 1;
constant u_RAM128X1S_1: primitives_type := u_RAM128X1S + 1;
constant u_RAM16X1D: primitives_type := u_RAM128X1S_1 + 1;
constant u_RAM16X1D_1: primitives_type := u_RAM16X1D + 1;
constant u_RAM16X1S: primitives_type := u_RAM16X1D_1 + 1;
constant u_RAM16X1S_1: primitives_type := u_RAM16X1S + 1;
constant u_RAM16X2S: primitives_type := u_RAM16X1S_1 + 1;
constant u_RAM16X4S: primitives_type := u_RAM16X2S + 1;
constant u_RAM16X8S: primitives_type := u_RAM16X4S + 1;
constant u_RAM256X1S: primitives_type := u_RAM16X8S + 1;
constant u_RAM32M: primitives_type := u_RAM256X1S + 1;
constant u_RAM32X1D: primitives_type := u_RAM32M + 1;
constant u_RAM32X1D_1: primitives_type := u_RAM32X1D + 1;
constant u_RAM32X1S: primitives_type := u_RAM32X1D_1 + 1;
constant u_RAM32X1S_1: primitives_type := u_RAM32X1S + 1;
constant u_RAM32X2S: primitives_type := u_RAM32X1S_1 + 1;
constant u_RAM32X4S: primitives_type := u_RAM32X2S + 1;
constant u_RAM32X8S: primitives_type := u_RAM32X4S + 1;
constant u_RAM64M: primitives_type := u_RAM32X8S + 1;
constant u_RAM64X1D: primitives_type := u_RAM64M + 1;
constant u_RAM64X1D_1: primitives_type := u_RAM64X1D + 1;
constant u_RAM64X1S: primitives_type := u_RAM64X1D_1 + 1;
constant u_RAM64X1S_1: primitives_type := u_RAM64X1S + 1;
constant u_RAM64X2S: primitives_type := u_RAM64X1S_1 + 1;
constant u_RAMB16: primitives_type := u_RAM64X2S + 1;
constant u_RAMB16BWE: primitives_type := u_RAMB16 + 1;
constant u_RAMB16BWER: primitives_type := u_RAMB16BWE + 1;
constant u_RAMB16BWE_S18: primitives_type := u_RAMB16BWER + 1;
constant u_RAMB16BWE_S18_S18: primitives_type := u_RAMB16BWE_S18 + 1;
constant u_RAMB16BWE_S18_S9: primitives_type := u_RAMB16BWE_S18_S18 + 1;
constant u_RAMB16BWE_S36: primitives_type := u_RAMB16BWE_S18_S9 + 1;
constant u_RAMB16BWE_S36_S18: primitives_type := u_RAMB16BWE_S36 + 1;
constant u_RAMB16BWE_S36_S36: primitives_type := u_RAMB16BWE_S36_S18 + 1;
constant u_RAMB16BWE_S36_S9: primitives_type := u_RAMB16BWE_S36_S36 + 1;
constant u_RAMB16_S1: primitives_type := u_RAMB16BWE_S36_S9 + 1;
constant u_RAMB16_S18: primitives_type := u_RAMB16_S1 + 1;
constant u_RAMB16_S18_S18: primitives_type := u_RAMB16_S18 + 1;
constant u_RAMB16_S18_S36: primitives_type := u_RAMB16_S18_S18 + 1;
constant u_RAMB16_S1_S1: primitives_type := u_RAMB16_S18_S36 + 1;
constant u_RAMB16_S1_S18: primitives_type := u_RAMB16_S1_S1 + 1;
constant u_RAMB16_S1_S2: primitives_type := u_RAMB16_S1_S18 + 1;
constant u_RAMB16_S1_S36: primitives_type := u_RAMB16_S1_S2 + 1;
constant u_RAMB16_S1_S4: primitives_type := u_RAMB16_S1_S36 + 1;
constant u_RAMB16_S1_S9: primitives_type := u_RAMB16_S1_S4 + 1;
constant u_RAMB16_S2: primitives_type := u_RAMB16_S1_S9 + 1;
constant u_RAMB16_S2_S18: primitives_type := u_RAMB16_S2 + 1;
constant u_RAMB16_S2_S2: primitives_type := u_RAMB16_S2_S18 + 1;
constant u_RAMB16_S2_S36: primitives_type := u_RAMB16_S2_S2 + 1;
constant u_RAMB16_S2_S4: primitives_type := u_RAMB16_S2_S36 + 1;
constant u_RAMB16_S2_S9: primitives_type := u_RAMB16_S2_S4 + 1;
constant u_RAMB16_S36: primitives_type := u_RAMB16_S2_S9 + 1;
constant u_RAMB16_S36_S36: primitives_type := u_RAMB16_S36 + 1;
constant u_RAMB16_S4: primitives_type := u_RAMB16_S36_S36 + 1;
constant u_RAMB16_S4_S18: primitives_type := u_RAMB16_S4 + 1;
constant u_RAMB16_S4_S36: primitives_type := u_RAMB16_S4_S18 + 1;
constant u_RAMB16_S4_S4: primitives_type := u_RAMB16_S4_S36 + 1;
constant u_RAMB16_S4_S9: primitives_type := u_RAMB16_S4_S4 + 1;
constant u_RAMB16_S9: primitives_type := u_RAMB16_S4_S9 + 1;
constant u_RAMB16_S9_S18: primitives_type := u_RAMB16_S9 + 1;
constant u_RAMB16_S9_S36: primitives_type := u_RAMB16_S9_S18 + 1;
constant u_RAMB16_S9_S9: primitives_type := u_RAMB16_S9_S36 + 1;
constant u_RAMB18: primitives_type := u_RAMB16_S9_S9 + 1;
constant u_RAMB18E1: primitives_type := u_RAMB18 + 1;
constant u_RAMB18SDP: primitives_type := u_RAMB18E1 + 1;
constant u_RAMB32_S64_ECC: primitives_type := u_RAMB18SDP + 1;
constant u_RAMB36: primitives_type := u_RAMB32_S64_ECC + 1;
constant u_RAMB36E1: primitives_type := u_RAMB36 + 1;
constant u_RAMB36_EXP: primitives_type := u_RAMB36E1 + 1;
constant u_RAMB36SDP: primitives_type := u_RAMB36_EXP + 1;
constant u_RAMB36SDP_EXP: primitives_type := u_RAMB36SDP + 1;
constant u_RAMB4_S1: primitives_type := u_RAMB36SDP_EXP + 1;
constant u_RAMB4_S16: primitives_type := u_RAMB4_S1 + 1;
constant u_RAMB4_S16_S16: primitives_type := u_RAMB4_S16 + 1;
constant u_RAMB4_S1_S1: primitives_type := u_RAMB4_S16_S16 + 1;
constant u_RAMB4_S1_S16: primitives_type := u_RAMB4_S1_S1 + 1;
constant u_RAMB4_S1_S2: primitives_type := u_RAMB4_S1_S16 + 1;
constant u_RAMB4_S1_S4: primitives_type := u_RAMB4_S1_S2 + 1;
constant u_RAMB4_S1_S8: primitives_type := u_RAMB4_S1_S4 + 1;
constant u_RAMB4_S2: primitives_type := u_RAMB4_S1_S8 + 1;
constant u_RAMB4_S2_S16: primitives_type := u_RAMB4_S2 + 1;
constant u_RAMB4_S2_S2: primitives_type := u_RAMB4_S2_S16 + 1;
constant u_RAMB4_S2_S4: primitives_type := u_RAMB4_S2_S2 + 1;
constant u_RAMB4_S2_S8: primitives_type := u_RAMB4_S2_S4 + 1;
constant u_RAMB4_S4: primitives_type := u_RAMB4_S2_S8 + 1;
constant u_RAMB4_S4_S16: primitives_type := u_RAMB4_S4 + 1;
constant u_RAMB4_S4_S4: primitives_type := u_RAMB4_S4_S16 + 1;
constant u_RAMB4_S4_S8: primitives_type := u_RAMB4_S4_S4 + 1;
constant u_RAMB4_S8: primitives_type := u_RAMB4_S4_S8 + 1;
constant u_RAMB4_S8_S16: primitives_type := u_RAMB4_S8 + 1;
constant u_RAMB4_S8_S8: primitives_type := u_RAMB4_S8_S16 + 1;
constant u_RAMB8BWER: primitives_type := u_RAMB4_S8_S8 + 1;
constant u_ROM128X1: primitives_type := u_RAMB8BWER + 1;
constant u_ROM16X1: primitives_type := u_ROM128X1 + 1;
constant u_ROM256X1: primitives_type := u_ROM16X1 + 1;
constant u_ROM32X1: primitives_type := u_ROM256X1 + 1;
constant u_ROM64X1: primitives_type := u_ROM32X1 + 1;
constant u_SLAVE_SPI: primitives_type := u_ROM64X1 + 1;
constant u_SPI_ACCESS: primitives_type := u_SLAVE_SPI + 1;
constant u_SRL16: primitives_type := u_SPI_ACCESS + 1;
constant u_SRL16_1: primitives_type := u_SRL16 + 1;
constant u_SRL16E: primitives_type := u_SRL16_1 + 1;
constant u_SRL16E_1: primitives_type := u_SRL16E + 1;
constant u_SRLC16: primitives_type := u_SRL16E_1 + 1;
constant u_SRLC16_1: primitives_type := u_SRLC16 + 1;
constant u_SRLC16E: primitives_type := u_SRLC16_1 + 1;
constant u_SRLC16E_1: primitives_type := u_SRLC16E + 1;
constant u_SRLC32E: primitives_type := u_SRLC16E_1 + 1;
constant u_STARTBUF_SPARTAN2: primitives_type := u_SRLC32E + 1;
constant u_STARTBUF_SPARTAN3: primitives_type := u_STARTBUF_SPARTAN2 + 1;
constant u_STARTBUF_SPARTAN3E: primitives_type := u_STARTBUF_SPARTAN3 + 1;
constant u_STARTBUF_VIRTEX: primitives_type := u_STARTBUF_SPARTAN3E + 1;
constant u_STARTBUF_VIRTEX2: primitives_type := u_STARTBUF_VIRTEX + 1;
constant u_STARTBUF_VIRTEX4: primitives_type := u_STARTBUF_VIRTEX2 + 1;
constant u_STARTUP_SPARTAN2: primitives_type := u_STARTBUF_VIRTEX4 + 1;
constant u_STARTUP_SPARTAN3: primitives_type := u_STARTUP_SPARTAN2 + 1;
constant u_STARTUP_SPARTAN3A: primitives_type := u_STARTUP_SPARTAN3 + 1;
constant u_STARTUP_SPARTAN3E: primitives_type := u_STARTUP_SPARTAN3A + 1;
constant u_STARTUP_SPARTAN6: primitives_type := u_STARTUP_SPARTAN3E + 1;
constant u_STARTUP_VIRTEX: primitives_type := u_STARTUP_SPARTAN6 + 1;
constant u_STARTUP_VIRTEX2: primitives_type := u_STARTUP_VIRTEX + 1;
constant u_STARTUP_VIRTEX4: primitives_type := u_STARTUP_VIRTEX2 + 1;
constant u_STARTUP_VIRTEX5: primitives_type := u_STARTUP_VIRTEX4 + 1;
constant u_STARTUP_VIRTEX6: primitives_type := u_STARTUP_VIRTEX5 + 1;
constant u_SUSPEND_SYNC: primitives_type := u_STARTUP_VIRTEX6 + 1;
constant u_SYSMON: primitives_type := u_SUSPEND_SYNC + 1;
constant u_TEMAC_SINGLE: primitives_type := u_SYSMON + 1;
constant u_TOC: primitives_type := u_TEMAC_SINGLE + 1;
constant u_TOCBUF: primitives_type := u_TOC + 1;
constant u_USR_ACCESS_VIRTEX4: primitives_type := u_TOCBUF + 1;
constant u_USR_ACCESS_VIRTEX5: primitives_type := u_USR_ACCESS_VIRTEX4 + 1;
constant u_USR_ACCESS_VIRTEX6: primitives_type := u_USR_ACCESS_VIRTEX5 + 1;
constant u_VCC: primitives_type := u_USR_ACCESS_VIRTEX6 + 1;
constant u_XNOR2: primitives_type := u_VCC + 1;
constant u_XNOR3: primitives_type := u_XNOR2 + 1;
constant u_XNOR4: primitives_type := u_XNOR3 + 1;
constant u_XOR2: primitives_type := u_XNOR4 + 1;
constant u_XOR3: primitives_type := u_XOR2 + 1;
constant u_XOR4: primitives_type := u_XOR3 + 1;
constant u_XORCY: primitives_type := u_XOR4 + 1;
constant u_XORCY_D: primitives_type := u_XORCY + 1;
constant u_XORCY_L: primitives_type := u_XORCY_D + 1;
-- Primitives added for artix7, kintex6, virtex7, and zynq
constant u_AND2B1: primitives_type := u_XORCY_L + 1;
constant u_AND2B2: primitives_type := u_AND2B1 + 1;
constant u_AND3B1: primitives_type := u_AND2B2 + 1;
constant u_AND3B2: primitives_type := u_AND3B1 + 1;
constant u_AND3B3: primitives_type := u_AND3B2 + 1;
constant u_AND4B1: primitives_type := u_AND3B3 + 1;
constant u_AND4B2: primitives_type := u_AND4B1 + 1;
constant u_AND4B3: primitives_type := u_AND4B2 + 1;
constant u_AND4B4: primitives_type := u_AND4B3 + 1;
constant u_AND5: primitives_type := u_AND4B4 + 1;
constant u_AND5B1: primitives_type := u_AND5 + 1;
constant u_AND5B2: primitives_type := u_AND5B1 + 1;
constant u_AND5B3: primitives_type := u_AND5B2 + 1;
constant u_AND5B4: primitives_type := u_AND5B3 + 1;
constant u_AND5B5: primitives_type := u_AND5B4 + 1;
constant u_BSCANE2: primitives_type := u_AND5B5 + 1;
constant u_BUFMR: primitives_type := u_BSCANE2 + 1;
constant u_BUFMRCE: primitives_type := u_BUFMR + 1;
constant u_CAPTUREE2: primitives_type := u_BUFMRCE + 1;
constant u_CFG_IO_ACCESS: primitives_type := u_CAPTUREE2 + 1;
constant u_FRAME_ECCE2: primitives_type := u_CFG_IO_ACCESS + 1;
constant u_GTXE2_CHANNEL: primitives_type := u_FRAME_ECCE2 + 1;
constant u_GTXE2_COMMON: primitives_type := u_GTXE2_CHANNEL + 1;
constant u_IBUF_DCIEN: primitives_type := u_GTXE2_COMMON + 1;
constant u_IBUFDS_BLVDS_25: primitives_type := u_IBUF_DCIEN + 1;
constant u_IBUFDS_DCIEN: primitives_type := u_IBUFDS_BLVDS_25 + 1;
constant u_IBUFDS_DIFF_OUT_DCIEN: primitives_type := u_IBUFDS_DCIEN + 1;
constant u_IBUFDS_GTE2: primitives_type := u_IBUFDS_DIFF_OUT_DCIEN + 1;
constant u_IBUFDS_LVDS_25: primitives_type := u_IBUFDS_GTE2 + 1;
constant u_IBUFGDS_BLVDS_25: primitives_type := u_IBUFDS_LVDS_25 + 1;
constant u_IBUFGDS_LVDS_25: primitives_type := u_IBUFGDS_BLVDS_25 + 1;
constant u_IBUFG_HSTL_I_18: primitives_type := u_IBUFGDS_LVDS_25 + 1;
constant u_IBUFG_HSTL_I_DCI: primitives_type := u_IBUFG_HSTL_I_18 + 1;
constant u_IBUFG_HSTL_I_DCI_18: primitives_type := u_IBUFG_HSTL_I_DCI + 1;
constant u_IBUFG_HSTL_II: primitives_type := u_IBUFG_HSTL_I_DCI_18 + 1;
constant u_IBUFG_HSTL_II_18: primitives_type := u_IBUFG_HSTL_II + 1;
constant u_IBUFG_HSTL_II_DCI: primitives_type := u_IBUFG_HSTL_II_18 + 1;
constant u_IBUFG_HSTL_II_DCI_18: primitives_type := u_IBUFG_HSTL_II_DCI + 1;
constant u_IBUFG_HSTL_III_18: primitives_type := u_IBUFG_HSTL_II_DCI_18 + 1;
constant u_IBUFG_HSTL_III_DCI: primitives_type := u_IBUFG_HSTL_III_18 + 1;
constant u_IBUFG_HSTL_III_DCI_18: primitives_type := u_IBUFG_HSTL_III_DCI + 1;
constant u_IBUFG_LVCMOS12: primitives_type := u_IBUFG_HSTL_III_DCI_18 + 1;
constant u_IBUFG_LVCMOS15: primitives_type := u_IBUFG_LVCMOS12 + 1;
constant u_IBUFG_LVCMOS25: primitives_type := u_IBUFG_LVCMOS15 + 1;
constant u_IBUFG_LVCMOS33: primitives_type := u_IBUFG_LVCMOS25 + 1;
constant u_IBUFG_LVDCI_15: primitives_type := u_IBUFG_LVCMOS33 + 1;
constant u_IBUFG_LVDCI_18: primitives_type := u_IBUFG_LVDCI_15 + 1;
constant u_IBUFG_LVDCI_DV2_15: primitives_type := u_IBUFG_LVDCI_18 + 1;
constant u_IBUFG_LVDCI_DV2_18: primitives_type := u_IBUFG_LVDCI_DV2_15 + 1;
constant u_IBUFG_LVTTL: primitives_type := u_IBUFG_LVDCI_DV2_18 + 1;
constant u_IBUFG_SSTL18_I: primitives_type := u_IBUFG_LVTTL + 1;
constant u_IBUFG_SSTL18_I_DCI: primitives_type := u_IBUFG_SSTL18_I + 1;
constant u_IBUFG_SSTL18_II: primitives_type := u_IBUFG_SSTL18_I_DCI + 1;
constant u_IBUFG_SSTL18_II_DCI: primitives_type := u_IBUFG_SSTL18_II + 1;
constant u_IBUF_HSTL_I_18: primitives_type := u_IBUFG_SSTL18_II_DCI + 1;
constant u_IBUF_HSTL_I_DCI: primitives_type := u_IBUF_HSTL_I_18 + 1;
constant u_IBUF_HSTL_I_DCI_18: primitives_type := u_IBUF_HSTL_I_DCI + 1;
constant u_IBUF_HSTL_II: primitives_type := u_IBUF_HSTL_I_DCI_18 + 1;
constant u_IBUF_HSTL_II_18: primitives_type := u_IBUF_HSTL_II + 1;
constant u_IBUF_HSTL_II_DCI: primitives_type := u_IBUF_HSTL_II_18 + 1;
constant u_IBUF_HSTL_II_DCI_18: primitives_type := u_IBUF_HSTL_II_DCI + 1;
constant u_IBUF_HSTL_III_18: primitives_type := u_IBUF_HSTL_II_DCI_18 + 1;
constant u_IBUF_HSTL_III_DCI: primitives_type := u_IBUF_HSTL_III_18 + 1;
constant u_IBUF_HSTL_III_DCI_18: primitives_type := u_IBUF_HSTL_III_DCI + 1;
constant u_IBUF_LVCMOS12: primitives_type := u_IBUF_HSTL_III_DCI_18 + 1;
constant u_IBUF_LVCMOS15: primitives_type := u_IBUF_LVCMOS12 + 1;
constant u_IBUF_LVCMOS25: primitives_type := u_IBUF_LVCMOS15 + 1;
constant u_IBUF_LVCMOS33: primitives_type := u_IBUF_LVCMOS25 + 1;
constant u_IBUF_LVDCI_15: primitives_type := u_IBUF_LVCMOS33 + 1;
constant u_IBUF_LVDCI_18: primitives_type := u_IBUF_LVDCI_15 + 1;
constant u_IBUF_LVDCI_DV2_15: primitives_type := u_IBUF_LVDCI_18 + 1;
constant u_IBUF_LVDCI_DV2_18: primitives_type := u_IBUF_LVDCI_DV2_15 + 1;
constant u_IBUF_LVTTL: primitives_type := u_IBUF_LVDCI_DV2_18 + 1;
constant u_IBUF_SSTL18_I: primitives_type := u_IBUF_LVTTL + 1;
constant u_IBUF_SSTL18_I_DCI: primitives_type := u_IBUF_SSTL18_I + 1;
constant u_IBUF_SSTL18_II: primitives_type := u_IBUF_SSTL18_I_DCI + 1;
constant u_IBUF_SSTL18_II_DCI: primitives_type := u_IBUF_SSTL18_II + 1;
constant u_ICAPE2: primitives_type := u_IBUF_SSTL18_II_DCI + 1;
constant u_IDELAYE2: primitives_type := u_ICAPE2 + 1;
constant u_IN_FIFO: primitives_type := u_IDELAYE2 + 1;
constant u_IOBUFDS_BLVDS_25: primitives_type := u_IN_FIFO + 1;
constant u_IOBUFDS_DIFF_OUT_DCIEN: primitives_type := u_IOBUFDS_BLVDS_25 + 1;
constant u_IOBUF_HSTL_I_18: primitives_type := u_IOBUFDS_DIFF_OUT_DCIEN + 1;
constant u_IOBUF_HSTL_II: primitives_type := u_IOBUF_HSTL_I_18 + 1;
constant u_IOBUF_HSTL_II_18: primitives_type := u_IOBUF_HSTL_II + 1;
constant u_IOBUF_HSTL_II_DCI: primitives_type := u_IOBUF_HSTL_II_18 + 1;
constant u_IOBUF_HSTL_II_DCI_18: primitives_type := u_IOBUF_HSTL_II_DCI + 1;
constant u_IOBUF_HSTL_III_18: primitives_type := u_IOBUF_HSTL_II_DCI_18 + 1;
constant u_IOBUF_LVCMOS12: primitives_type := u_IOBUF_HSTL_III_18 + 1;
constant u_IOBUF_LVCMOS15: primitives_type := u_IOBUF_LVCMOS12 + 1;
constant u_IOBUF_LVCMOS25: primitives_type := u_IOBUF_LVCMOS15 + 1;
constant u_IOBUF_LVCMOS33: primitives_type := u_IOBUF_LVCMOS25 + 1;
constant u_IOBUF_LVDCI_15: primitives_type := u_IOBUF_LVCMOS33 + 1;
constant u_IOBUF_LVDCI_18: primitives_type := u_IOBUF_LVDCI_15 + 1;
constant u_IOBUF_LVDCI_DV2_15: primitives_type := u_IOBUF_LVDCI_18 + 1;
constant u_IOBUF_LVDCI_DV2_18: primitives_type := u_IOBUF_LVDCI_DV2_15 + 1;
constant u_IOBUF_LVTTL: primitives_type := u_IOBUF_LVDCI_DV2_18 + 1;
constant u_IOBUF_SSTL18_I: primitives_type := u_IOBUF_LVTTL + 1;
constant u_IOBUF_SSTL18_II: primitives_type := u_IOBUF_SSTL18_I + 1;
constant u_IOBUF_SSTL18_II_DCI: primitives_type := u_IOBUF_SSTL18_II + 1;
constant u_ISERDESE2: primitives_type := u_IOBUF_SSTL18_II_DCI + 1;
constant u_JTAG_SIME2: primitives_type := u_ISERDESE2 + 1;
constant u_LUT6_2: primitives_type := u_JTAG_SIME2 + 1;
constant u_MMCME2_ADV: primitives_type := u_LUT6_2 + 1;
constant u_MMCME2_BASE: primitives_type := u_MMCME2_ADV + 1;
constant u_NAND2B1: primitives_type := u_MMCME2_BASE + 1;
constant u_NAND2B2: primitives_type := u_NAND2B1 + 1;
constant u_NAND3B1: primitives_type := u_NAND2B2 + 1;
constant u_NAND3B2: primitives_type := u_NAND3B1 + 1;
constant u_NAND3B3: primitives_type := u_NAND3B2 + 1;
constant u_NAND4B1: primitives_type := u_NAND3B3 + 1;
constant u_NAND4B2: primitives_type := u_NAND4B1 + 1;
constant u_NAND4B3: primitives_type := u_NAND4B2 + 1;
constant u_NAND4B4: primitives_type := u_NAND4B3 + 1;
constant u_NAND5: primitives_type := u_NAND4B4 + 1;
constant u_NAND5B1: primitives_type := u_NAND5 + 1;
constant u_NAND5B2: primitives_type := u_NAND5B1 + 1;
constant u_NAND5B3: primitives_type := u_NAND5B2 + 1;
constant u_NAND5B4: primitives_type := u_NAND5B3 + 1;
constant u_NAND5B5: primitives_type := u_NAND5B4 + 1;
constant u_NOR2B1: primitives_type := u_NAND5B5 + 1;
constant u_NOR2B2: primitives_type := u_NOR2B1 + 1;
constant u_NOR3B1: primitives_type := u_NOR2B2 + 1;
constant u_NOR3B2: primitives_type := u_NOR3B1 + 1;
constant u_NOR3B3: primitives_type := u_NOR3B2 + 1;
constant u_NOR4B1: primitives_type := u_NOR3B3 + 1;
constant u_NOR4B2: primitives_type := u_NOR4B1 + 1;
constant u_NOR4B3: primitives_type := u_NOR4B2 + 1;
constant u_NOR4B4: primitives_type := u_NOR4B3 + 1;
constant u_NOR5: primitives_type := u_NOR4B4 + 1;
constant u_NOR5B1: primitives_type := u_NOR5 + 1;
constant u_NOR5B2: primitives_type := u_NOR5B1 + 1;
constant u_NOR5B3: primitives_type := u_NOR5B2 + 1;
constant u_NOR5B4: primitives_type := u_NOR5B3 + 1;
constant u_NOR5B5: primitives_type := u_NOR5B4 + 1;
constant u_OBUFDS_BLVDS_25: primitives_type := u_NOR5B5 + 1;
constant u_OBUFDS_DUAL_BUF: primitives_type := u_OBUFDS_BLVDS_25 + 1;
constant u_OBUFDS_LVDS_25: primitives_type := u_OBUFDS_DUAL_BUF + 1;
constant u_OBUF_HSTL_I_18: primitives_type := u_OBUFDS_LVDS_25 + 1;
constant u_OBUF_HSTL_I_DCI: primitives_type := u_OBUF_HSTL_I_18 + 1;
constant u_OBUF_HSTL_I_DCI_18: primitives_type := u_OBUF_HSTL_I_DCI + 1;
constant u_OBUF_HSTL_II: primitives_type := u_OBUF_HSTL_I_DCI_18 + 1;
constant u_OBUF_HSTL_II_18: primitives_type := u_OBUF_HSTL_II + 1;
constant u_OBUF_HSTL_II_DCI: primitives_type := u_OBUF_HSTL_II_18 + 1;
constant u_OBUF_HSTL_II_DCI_18: primitives_type := u_OBUF_HSTL_II_DCI + 1;
constant u_OBUF_HSTL_III_18: primitives_type := u_OBUF_HSTL_II_DCI_18 + 1;
constant u_OBUF_HSTL_III_DCI: primitives_type := u_OBUF_HSTL_III_18 + 1;
constant u_OBUF_HSTL_III_DCI_18: primitives_type := u_OBUF_HSTL_III_DCI + 1;
constant u_OBUF_LVCMOS12: primitives_type := u_OBUF_HSTL_III_DCI_18 + 1;
constant u_OBUF_LVCMOS15: primitives_type := u_OBUF_LVCMOS12 + 1;
constant u_OBUF_LVCMOS25: primitives_type := u_OBUF_LVCMOS15 + 1;
constant u_OBUF_LVCMOS33: primitives_type := u_OBUF_LVCMOS25 + 1;
constant u_OBUF_LVDCI_15: primitives_type := u_OBUF_LVCMOS33 + 1;
constant u_OBUF_LVDCI_18: primitives_type := u_OBUF_LVDCI_15 + 1;
constant u_OBUF_LVDCI_DV2_15: primitives_type := u_OBUF_LVDCI_18 + 1;
constant u_OBUF_LVDCI_DV2_18: primitives_type := u_OBUF_LVDCI_DV2_15 + 1;
constant u_OBUF_LVTTL: primitives_type := u_OBUF_LVDCI_DV2_18 + 1;
constant u_OBUF_SSTL18_I: primitives_type := u_OBUF_LVTTL + 1;
constant u_OBUF_SSTL18_I_DCI: primitives_type := u_OBUF_SSTL18_I + 1;
constant u_OBUF_SSTL18_II: primitives_type := u_OBUF_SSTL18_I_DCI + 1;
constant u_OBUF_SSTL18_II_DCI: primitives_type := u_OBUF_SSTL18_II + 1;
constant u_OBUFT_DCIEN: primitives_type := u_OBUF_SSTL18_II_DCI + 1;
constant u_OBUFTDS_BLVDS_25: primitives_type := u_OBUFT_DCIEN + 1;
constant u_OBUFTDS_DCIEN: primitives_type := u_OBUFTDS_BLVDS_25 + 1;
constant u_OBUFTDS_DCIEN_DUAL_BUF: primitives_type := u_OBUFTDS_DCIEN + 1;
constant u_OBUFTDS_DUAL_BUF: primitives_type := u_OBUFTDS_DCIEN_DUAL_BUF + 1;
constant u_OBUFTDS_LVDS_25: primitives_type := u_OBUFTDS_DUAL_BUF + 1;
constant u_OBUFT_HSTL_I_18: primitives_type := u_OBUFTDS_LVDS_25 + 1;
constant u_OBUFT_HSTL_I_DCI: primitives_type := u_OBUFT_HSTL_I_18 + 1;
constant u_OBUFT_HSTL_I_DCI_18: primitives_type := u_OBUFT_HSTL_I_DCI + 1;
constant u_OBUFT_HSTL_II: primitives_type := u_OBUFT_HSTL_I_DCI_18 + 1;
constant u_OBUFT_HSTL_II_18: primitives_type := u_OBUFT_HSTL_II + 1;
constant u_OBUFT_HSTL_II_DCI: primitives_type := u_OBUFT_HSTL_II_18 + 1;
constant u_OBUFT_HSTL_II_DCI_18: primitives_type := u_OBUFT_HSTL_II_DCI + 1;
constant u_OBUFT_HSTL_III_18: primitives_type := u_OBUFT_HSTL_II_DCI_18 + 1;
constant u_OBUFT_HSTL_III_DCI: primitives_type := u_OBUFT_HSTL_III_18 + 1;
constant u_OBUFT_HSTL_III_DCI_18: primitives_type := u_OBUFT_HSTL_III_DCI + 1;
constant u_OBUFT_LVCMOS12: primitives_type := u_OBUFT_HSTL_III_DCI_18 + 1;
constant u_OBUFT_LVCMOS15: primitives_type := u_OBUFT_LVCMOS12 + 1;
constant u_OBUFT_LVCMOS25: primitives_type := u_OBUFT_LVCMOS15 + 1;
constant u_OBUFT_LVCMOS33: primitives_type := u_OBUFT_LVCMOS25 + 1;
constant u_OBUFT_LVDCI_15: primitives_type := u_OBUFT_LVCMOS33 + 1;
constant u_OBUFT_LVDCI_18: primitives_type := u_OBUFT_LVDCI_15 + 1;
constant u_OBUFT_LVDCI_DV2_15: primitives_type := u_OBUFT_LVDCI_18 + 1;
constant u_OBUFT_LVDCI_DV2_18: primitives_type := u_OBUFT_LVDCI_DV2_15 + 1;
constant u_OBUFT_LVTTL: primitives_type := u_OBUFT_LVDCI_DV2_18 + 1;
constant u_OBUFT_SSTL18_I: primitives_type := u_OBUFT_LVTTL + 1;
constant u_OBUFT_SSTL18_I_DCI: primitives_type := u_OBUFT_SSTL18_I + 1;
constant u_OBUFT_SSTL18_II: primitives_type := u_OBUFT_SSTL18_I_DCI + 1;
constant u_OBUFT_SSTL18_II_DCI: primitives_type := u_OBUFT_SSTL18_II + 1;
constant u_ODELAYE2: primitives_type := u_OBUFT_SSTL18_II_DCI + 1;
constant u_OR2B1: primitives_type := u_ODELAYE2 + 1;
constant u_OR2B2: primitives_type := u_OR2B1 + 1;
constant u_OR3B1: primitives_type := u_OR2B2 + 1;
constant u_OR3B2: primitives_type := u_OR3B1 + 1;
constant u_OR3B3: primitives_type := u_OR3B2 + 1;
constant u_OR4B1: primitives_type := u_OR3B3 + 1;
constant u_OR4B2: primitives_type := u_OR4B1 + 1;
constant u_OR4B3: primitives_type := u_OR4B2 + 1;
constant u_OR4B4: primitives_type := u_OR4B3 + 1;
constant u_OR5: primitives_type := u_OR4B4 + 1;
constant u_OR5B1: primitives_type := u_OR5 + 1;
constant u_OR5B2: primitives_type := u_OR5B1 + 1;
constant u_OR5B3: primitives_type := u_OR5B2 + 1;
constant u_OR5B4: primitives_type := u_OR5B3 + 1;
constant u_OR5B5: primitives_type := u_OR5B4 + 1;
constant u_OSERDESE2: primitives_type := u_OR5B5 + 1;
constant u_OUT_FIFO: primitives_type := u_OSERDESE2 + 1;
constant u_PCIE_2_1: primitives_type := u_OUT_FIFO + 1;
constant u_PHASER_IN: primitives_type := u_PCIE_2_1 + 1;
constant u_PHASER_IN_PHY: primitives_type := u_PHASER_IN + 1;
constant u_PHASER_OUT: primitives_type := u_PHASER_IN_PHY + 1;
constant u_PHASER_OUT_PHY: primitives_type := u_PHASER_OUT + 1;
constant u_PHASER_REF: primitives_type := u_PHASER_OUT_PHY + 1;
constant u_PHY_CONTROL: primitives_type := u_PHASER_REF + 1;
constant u_PLLE2_ADV: primitives_type := u_PHY_CONTROL + 1;
constant u_PLLE2_BASE: primitives_type := u_PLLE2_ADV + 1;
constant u_PSS: primitives_type := u_PLLE2_BASE + 1;
constant u_RAMD32: primitives_type := u_PSS + 1;
constant u_RAMD64E: primitives_type := u_RAMD32 + 1;
constant u_RAMS32: primitives_type := u_RAMD64E + 1;
constant u_RAMS64E: primitives_type := u_RAMS32 + 1;
constant u_SIM_CONFIGE2: primitives_type := u_RAMS64E + 1;
constant u_STARTUPE2: primitives_type := u_SIM_CONFIGE2 + 1;
constant u_USR_ACCESSE2: primitives_type := u_STARTUPE2 + 1;
constant u_XADC: primitives_type := u_USR_ACCESSE2 + 1;
constant u_XNOR5: primitives_type := u_XADC + 1;
constant u_XOR5: primitives_type := u_XNOR5 + 1;
constant u_ZHOLD_DELAY: primitives_type := u_XOR5 + 1;
type primitive_array_type is array (natural range <>) of primitives_type;
----------------------------------------------------------------------------
-- Returns true if primitive is available in family.
--
-- Examples:
--
-- supported(virtex2, u_RAMB16_S2) returns true because the RAMB16_S2
-- primitive is available in the
-- virtex2 family.
--
-- supported(spartan3, u_RAM4B_S4) returns false because the RAMB4_S4
-- primitive is not available in the
-- spartan3 family.
----------------------------------------------------------------------------
function supported( family : families_type;
primitive : primitives_type
) return boolean;
----------------------------------------------------------------------------
-- This is an overload of function 'supported' (see above). It allows a list
-- of primitives to be tested.
--
-- Returns true if all of primitives in the list are available in family.
--
-- Example: supported(spartan3, (u_MUXCY, u_XORCY, u_FD))
-- is
-- equivalent to: supported(spartan3, u_MUXCY) and
-- supported(spartan3, u_XORCY) and
-- supported(spartan3, u_FD);
----------------------------------------------------------------------------
function supported( family : families_type;
primitives : primitive_array_type
) return boolean;
----------------------------------------------------------------------------
-- Below, are overloads of function 'supported' that allow the family
-- parameter to be passed as a string. These correspond to the above two
-- functions otherwise.
----------------------------------------------------------------------------
function supported( fam_as_str : string;
primitive : primitives_type
) return boolean;
function supported( fam_as_str : string;
primitives : primitive_array_type
) return boolean;
----------------------------------------------------------------------------
-- Conversions from/to STRING to/from families_type.
-- These are convenience functions that are not normally needed when
-- using the 'supported' functions.
----------------------------------------------------------------------------
function str2fam( fam_as_string : string ) return families_type;
function fam2str( fam : families_type ) return string;
----------------------------------------------------------------------------
-- Function: native_lut_size
--
-- Returns the largest LUT size available in FPGA family, fam.
-- If no LUT is available in fam, then returns zero by default, unless
-- the call specifies a no_lut_return_val, in which case this value
-- is returned.
--
-- The function is available in two overload versions, one for each
-- way of passing the fam argument.
----------------------------------------------------------------------------
function native_lut_size( fam : families_type;
no_lut_return_val : natural := 0
) return natural;
function native_lut_size( fam_as_string : string;
no_lut_return_val : natural := 0
) return natural;
----------------------------------------------------------------------------
-- Function: equalIgnoringCase
--
-- Compare one string against another for equality with case insensitivity.
-- Can be used to test see if a family, C_FAMILY, is equal to some
-- family. However such usage is discouraged. Use instead availability
-- primitive guards based on the function, 'supported', wherever possible.
----------------------------------------------------------------------------
function equalIgnoringCase( str1, str2 : string ) return boolean;
----------------------------------------------------------------------------
-- Function: get_root_family
--
-- This function takes in the string for the desired FPGA family type and
-- returns the root FPGA family type. This is used for derivative part
-- aliasing to the root family.
----------------------------------------------------------------------------
function get_root_family( family_in : string ) return string;
end package family_support;
package body family_support is
type prim_status_type is (
n -- no
, y -- yes
, u -- unknown, not used. However, we use
-- an enumeration to allow for
-- possible future enhancement.
);
type fam_prim_status is array (primitives_type) of prim_status_type;
type fam_has_prim_type is array (families_type) of fam_prim_status;
-- Performance workaround (XST procedure and function handling).
-- The fam_has_prim constant is initialized by an aggregate rather than by the
-- following function. A version of this file with this function not
-- commented was employed in building the aggregate. So, what is below still
-- defines the family-primitive matirix.
--# ----------------------------------------------------------------------------
--# -- This function is used to populate the matrix of family/primitive values.
--# ----------------------------------------------------------------------------
--# ---(
--# function prim_population return fam_has_prim_type is
--# variable pp : fam_has_prim_type := (others => (others => n));
--#
--# procedure set_to( stat : prim_status_type
--# ; fam : families_type
--# ; prim_list : primitive_array_type
--# ) is
--# begin
--# for i in prim_list'range loop
--# pp(fam)(prim_list(i)) := stat;
--# end loop;
--# end set_to;
--#
--# begin
--# set_to(y, virtex, (
--# u_AND2
--# , u_AND3
--# , u_AND4
--# , u_BSCAN_VIRTEX
--# , u_BUF
--# , u_BUFCF
--# , u_BUFE
--# , u_BUFG
--# , u_BUFGDLL
--# , u_BUFGP
--# , u_BUFT
--# , u_CAPTURE_VIRTEX
--# , u_CLKDLL
--# , u_CLKDLLHF
--# , u_FD
--# , u_FDC
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDCP_1
--# , u_FDC_1
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDP_1
--# , u_FDR
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDRS_1
--# , u_FDR_1
--# , u_FDS
--# , u_FDSE
--# , u_FDSE_1
--# , u_FDS_1
--# , u_FD_1
--# , u_FMAP
--# , u_GND
--# , u_IBUF
--# , u_IBUFG
--# , u_IBUFG_AGP
--# , u_IBUFG_CTT
--# , u_IBUFG_GTL
--# , u_IBUFG_GTLP
--# , u_IBUFG_HSTL_I
--# , u_IBUFG_HSTL_III
--# , u_IBUFG_HSTL_IV
--# , u_IBUFG_LVCMOS2
--# , u_IBUFG_PCI33_3
--# , u_IBUFG_PCI33_5
--# , u_IBUFG_PCI66_3
--# , u_IBUFG_SSTL2_I
--# , u_IBUFG_SSTL2_II
--# , u_IBUFG_SSTL3_I
--# , u_IBUFG_SSTL3_II
--# , u_IBUF_AGP
--# , u_IBUF_CTT
--# , u_IBUF_GTL
--# , u_IBUF_GTLP
--# , u_IBUF_HSTL_I
--# , u_IBUF_HSTL_III
--# , u_IBUF_HSTL_IV
--# , u_IBUF_LVCMOS2
--# , u_IBUF_PCI33_3
--# , u_IBUF_PCI33_5
--# , u_IBUF_PCI66_3
--# , u_IBUF_SSTL2_I
--# , u_IBUF_SSTL2_II
--# , u_IBUF_SSTL3_I
--# , u_IBUF_SSTL3_II
--# , u_INV
--# , u_IOBUF
--# , u_IOBUF_AGP
--# , u_IOBUF_CTT
--# , u_IOBUF_F_12
--# , u_IOBUF_F_16
--# , u_IOBUF_F_2
--# , u_IOBUF_F_24
--# , u_IOBUF_F_4
--# , u_IOBUF_F_6
--# , u_IOBUF_F_8
--# , u_IOBUF_GTL
--# , u_IOBUF_GTLP
--# , u_IOBUF_HSTL_I
--# , u_IOBUF_HSTL_III
--# , u_IOBUF_HSTL_IV
--# , u_IOBUF_LVCMOS2
--# , u_IOBUF_PCI33_3
--# , u_IOBUF_PCI33_5
--# , u_IOBUF_PCI66_3
--# , u_IOBUF_SSTL2_I
--# , u_IOBUF_SSTL2_II
--# , u_IOBUF_SSTL3_I
--# , u_IOBUF_SSTL3_II
--# , u_IOBUF_S_12
--# , u_IOBUF_S_16
--# , u_IOBUF_S_2
--# , u_IOBUF_S_24
--# , u_IOBUF_S_4
--# , u_IOBUF_S_6
--# , u_IOBUF_S_8
--# , u_KEEPER
--# , u_LD
--# , u_LDC
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDCP_1
--# , u_LDC_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDPE
--# , u_LDPE_1
--# , u_LDP_1
--# , u_LD_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_NAND2
--# , u_NAND3
--# , u_NAND4
--# , u_NOR2
--# , u_NOR3
--# , u_NOR4
--# , u_OBUF
--# , u_OBUFT
--# , u_OBUFT_AGP
--# , u_OBUFT_CTT
--# , u_OBUFT_F_12
--# , u_OBUFT_F_16
--# , u_OBUFT_F_2
--# , u_OBUFT_F_24
--# , u_OBUFT_F_4
--# , u_OBUFT_F_6
--# , u_OBUFT_F_8
--# , u_OBUFT_GTL
--# , u_OBUFT_GTLP
--# , u_OBUFT_HSTL_I
--# , u_OBUFT_HSTL_III
--# , u_OBUFT_HSTL_IV
--# , u_OBUFT_LVCMOS2
--# , u_OBUFT_PCI33_3
--# , u_OBUFT_PCI33_5
--# , u_OBUFT_PCI66_3
--# , u_OBUFT_SSTL2_I
--# , u_OBUFT_SSTL2_II
--# , u_OBUFT_SSTL3_I
--# , u_OBUFT_SSTL3_II
--# , u_OBUFT_S_12
--# , u_OBUFT_S_16
--# , u_OBUFT_S_2
--# , u_OBUFT_S_24
--# , u_OBUFT_S_4
--# , u_OBUFT_S_6
--# , u_OBUFT_S_8
--# , u_OBUF_AGP
--# , u_OBUF_CTT
--# , u_OBUF_F_12
--# , u_OBUF_F_16
--# , u_OBUF_F_2
--# , u_OBUF_F_24
--# , u_OBUF_F_4
--# , u_OBUF_F_6
--# , u_OBUF_F_8
--# , u_OBUF_GTL
--# , u_OBUF_GTLP
--# , u_OBUF_HSTL_I
--# , u_OBUF_HSTL_III
--# , u_OBUF_HSTL_IV
--# , u_OBUF_LVCMOS2
--# , u_OBUF_PCI33_3
--# , u_OBUF_PCI33_5
--# , u_OBUF_PCI66_3
--# , u_OBUF_SSTL2_I
--# , u_OBUF_SSTL2_II
--# , u_OBUF_SSTL3_I
--# , u_OBUF_SSTL3_II
--# , u_OBUF_S_12
--# , u_OBUF_S_16
--# , u_OBUF_S_2
--# , u_OBUF_S_24
--# , u_OBUF_S_4
--# , u_OBUF_S_6
--# , u_OBUF_S_8
--# , u_OR2
--# , u_OR3
--# , u_OR4
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAMB4_S1
--# , u_RAMB4_S16
--# , u_RAMB4_S16_S16
--# , u_RAMB4_S1_S1
--# , u_RAMB4_S1_S16
--# , u_RAMB4_S1_S2
--# , u_RAMB4_S1_S4
--# , u_RAMB4_S1_S8
--# , u_RAMB4_S2
--# , u_RAMB4_S2_S16
--# , u_RAMB4_S2_S2
--# , u_RAMB4_S2_S4
--# , u_RAMB4_S2_S8
--# , u_RAMB4_S4
--# , u_RAMB4_S4_S16
--# , u_RAMB4_S4_S4
--# , u_RAMB4_S4_S8
--# , u_RAMB4_S8
--# , u_RAMB4_S8_S16
--# , u_RAMB4_S8_S8
--# , u_ROM16X1
--# , u_ROM32X1
--# , u_SRL16
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRL16_1
--# , u_STARTBUF_VIRTEX
--# , u_STARTUP_VIRTEX
--# , u_TOC
--# , u_TOCBUF
--# , u_VCC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# )
--# );
--# set_to(y, spartan2, (
--# u_AND2
--# , u_AND3
--# , u_AND4
--# , u_BSCAN_SPARTAN2
--# , u_BUF
--# , u_BUFCF
--# , u_BUFE
--# , u_BUFG
--# , u_BUFGDLL
--# , u_BUFGP
--# , u_BUFT
--# , u_CAPTURE_SPARTAN2
--# , u_CLKDLL
--# , u_CLKDLLHF
--# , u_FD
--# , u_FDC
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDCP_1
--# , u_FDC_1
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDP_1
--# , u_FDR
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDRS_1
--# , u_FDR_1
--# , u_FDS
--# , u_FDSE
--# , u_FDSE_1
--# , u_FDS_1
--# , u_FD_1
--# , u_FMAP
--# , u_GND
--# , u_IBUF
--# , u_IBUFG
--# , u_IBUFG_AGP
--# , u_IBUFG_CTT
--# , u_IBUFG_GTL
--# , u_IBUFG_GTLP
--# , u_IBUFG_HSTL_I
--# , u_IBUFG_HSTL_III
--# , u_IBUFG_HSTL_IV
--# , u_IBUFG_LVCMOS2
--# , u_IBUFG_PCI33_3
--# , u_IBUFG_PCI33_5
--# , u_IBUFG_PCI66_3
--# , u_IBUFG_SSTL2_I
--# , u_IBUFG_SSTL2_II
--# , u_IBUFG_SSTL3_I
--# , u_IBUFG_SSTL3_II
--# , u_IBUF_AGP
--# , u_IBUF_CTT
--# , u_IBUF_GTL
--# , u_IBUF_GTLP
--# , u_IBUF_HSTL_I
--# , u_IBUF_HSTL_III
--# , u_IBUF_HSTL_IV
--# , u_IBUF_LVCMOS2
--# , u_IBUF_PCI33_3
--# , u_IBUF_PCI33_5
--# , u_IBUF_PCI66_3
--# , u_IBUF_SSTL2_I
--# , u_IBUF_SSTL2_II
--# , u_IBUF_SSTL3_I
--# , u_IBUF_SSTL3_II
--# , u_INV
--# , u_IOBUF
--# , u_IOBUF_AGP
--# , u_IOBUF_CTT
--# , u_IOBUF_F_12
--# , u_IOBUF_F_16
--# , u_IOBUF_F_2
--# , u_IOBUF_F_24
--# , u_IOBUF_F_4
--# , u_IOBUF_F_6
--# , u_IOBUF_F_8
--# , u_IOBUF_GTL
--# , u_IOBUF_GTLP
--# , u_IOBUF_HSTL_I
--# , u_IOBUF_HSTL_III
--# , u_IOBUF_HSTL_IV
--# , u_IOBUF_LVCMOS2
--# , u_IOBUF_PCI33_3
--# , u_IOBUF_PCI33_5
--# , u_IOBUF_PCI66_3
--# , u_IOBUF_SSTL2_I
--# , u_IOBUF_SSTL2_II
--# , u_IOBUF_SSTL3_I
--# , u_IOBUF_SSTL3_II
--# , u_IOBUF_S_12
--# , u_IOBUF_S_16
--# , u_IOBUF_S_2
--# , u_IOBUF_S_24
--# , u_IOBUF_S_4
--# , u_IOBUF_S_6
--# , u_IOBUF_S_8
--# , u_KEEPER
--# , u_LD
--# , u_LDC
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDCP_1
--# , u_LDC_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDPE
--# , u_LDPE_1
--# , u_LDP_1
--# , u_LD_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_NAND2
--# , u_NAND3
--# , u_NAND4
--# , u_NOR2
--# , u_NOR3
--# , u_NOR4
--# , u_OBUF
--# , u_OBUFT
--# , u_OBUFT_AGP
--# , u_OBUFT_CTT
--# , u_OBUFT_F_12
--# , u_OBUFT_F_16
--# , u_OBUFT_F_2
--# , u_OBUFT_F_24
--# , u_OBUFT_F_4
--# , u_OBUFT_F_6
--# , u_OBUFT_F_8
--# , u_OBUFT_GTL
--# , u_OBUFT_GTLP
--# , u_OBUFT_HSTL_I
--# , u_OBUFT_HSTL_III
--# , u_OBUFT_HSTL_IV
--# , u_OBUFT_LVCMOS2
--# , u_OBUFT_PCI33_3
--# , u_OBUFT_PCI33_5
--# , u_OBUFT_PCI66_3
--# , u_OBUFT_SSTL2_I
--# , u_OBUFT_SSTL2_II
--# , u_OBUFT_SSTL3_I
--# , u_OBUFT_SSTL3_II
--# , u_OBUFT_S_12
--# , u_OBUFT_S_16
--# , u_OBUFT_S_2
--# , u_OBUFT_S_24
--# , u_OBUFT_S_4
--# , u_OBUFT_S_6
--# , u_OBUFT_S_8
--# , u_OBUF_AGP
--# , u_OBUF_CTT
--# , u_OBUF_F_12
--# , u_OBUF_F_16
--# , u_OBUF_F_2
--# , u_OBUF_F_24
--# , u_OBUF_F_4
--# , u_OBUF_F_6
--# , u_OBUF_F_8
--# , u_OBUF_GTL
--# , u_OBUF_GTLP
--# , u_OBUF_HSTL_I
--# , u_OBUF_HSTL_III
--# , u_OBUF_HSTL_IV
--# , u_OBUF_LVCMOS2
--# , u_OBUF_PCI33_3
--# , u_OBUF_PCI33_5
--# , u_OBUF_PCI66_3
--# , u_OBUF_SSTL2_I
--# , u_OBUF_SSTL2_II
--# , u_OBUF_SSTL3_I
--# , u_OBUF_SSTL3_II
--# , u_OBUF_S_12
--# , u_OBUF_S_16
--# , u_OBUF_S_2
--# , u_OBUF_S_24
--# , u_OBUF_S_4
--# , u_OBUF_S_6
--# , u_OBUF_S_8
--# , u_OR2
--# , u_OR3
--# , u_OR4
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAMB4_S1
--# , u_RAMB4_S16
--# , u_RAMB4_S16_S16
--# , u_RAMB4_S1_S1
--# , u_RAMB4_S1_S16
--# , u_RAMB4_S1_S2
--# , u_RAMB4_S1_S4
--# , u_RAMB4_S1_S8
--# , u_RAMB4_S2
--# , u_RAMB4_S2_S16
--# , u_RAMB4_S2_S2
--# , u_RAMB4_S2_S4
--# , u_RAMB4_S2_S8
--# , u_RAMB4_S4
--# , u_RAMB4_S4_S16
--# , u_RAMB4_S4_S4
--# , u_RAMB4_S4_S8
--# , u_RAMB4_S8
--# , u_RAMB4_S8_S16
--# , u_RAMB4_S8_S8
--# , u_ROM16X1
--# , u_ROM32X1
--# , u_SRL16
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRL16_1
--# , u_STARTBUF_SPARTAN2
--# , u_STARTUP_SPARTAN2
--# , u_TOC
--# , u_TOCBUF
--# , u_VCC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# )
--# );
--# set_to(y, spartan2e, (
--# u_AND2
--# , u_AND3
--# , u_AND4
--# , u_BSCAN_SPARTAN2
--# , u_BUF
--# , u_BUFCF
--# , u_BUFE
--# , u_BUFG
--# , u_BUFGDLL
--# , u_BUFGP
--# , u_BUFT
--# , u_CAPTURE_SPARTAN2
--# , u_CLKDLL
--# , u_CLKDLLE
--# , u_CLKDLLHF
--# , u_FD
--# , u_FDC
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDCP_1
--# , u_FDC_1
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDP_1
--# , u_FDR
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDRS_1
--# , u_FDR_1
--# , u_FDS
--# , u_FDSE
--# , u_FDSE_1
--# , u_FDS_1
--# , u_FD_1
--# , u_FMAP
--# , u_GND
--# , u_IBUF
--# , u_IBUFG
--# , u_IBUFG_AGP
--# , u_IBUFG_CTT
--# , u_IBUFG_GTL
--# , u_IBUFG_GTLP
--# , u_IBUFG_HSTL_I
--# , u_IBUFG_HSTL_III
--# , u_IBUFG_HSTL_IV
--# , u_IBUFG_LVCMOS18
--# , u_IBUFG_LVCMOS2
--# , u_IBUFG_LVDS
--# , u_IBUFG_LVPECL
--# , u_IBUFG_PCI33_3
--# , u_IBUFG_PCI66_3
--# , u_IBUFG_PCIX66_3
--# , u_IBUFG_SSTL2_I
--# , u_IBUFG_SSTL2_II
--# , u_IBUFG_SSTL3_I
--# , u_IBUFG_SSTL3_II
--# , u_IBUF_AGP
--# , u_IBUF_CTT
--# , u_IBUF_GTL
--# , u_IBUF_GTLP
--# , u_IBUF_HSTL_I
--# , u_IBUF_HSTL_III
--# , u_IBUF_HSTL_IV
--# , u_IBUF_LVCMOS18
--# , u_IBUF_LVCMOS2
--# , u_IBUF_LVDS
--# , u_IBUF_LVPECL
--# , u_IBUF_PCI33_3
--# , u_IBUF_PCI66_3
--# , u_IBUF_PCIX66_3
--# , u_IBUF_SSTL2_I
--# , u_IBUF_SSTL2_II
--# , u_IBUF_SSTL3_I
--# , u_IBUF_SSTL3_II
--# , u_INV
--# , u_IOBUF
--# , u_IOBUF_AGP
--# , u_IOBUF_CTT
--# , u_IOBUF_F_12
--# , u_IOBUF_F_16
--# , u_IOBUF_F_2
--# , u_IOBUF_F_24
--# , u_IOBUF_F_4
--# , u_IOBUF_F_6
--# , u_IOBUF_F_8
--# , u_IOBUF_GTL
--# , u_IOBUF_GTLP
--# , u_IOBUF_HSTL_I
--# , u_IOBUF_HSTL_III
--# , u_IOBUF_HSTL_IV
--# , u_IOBUF_LVCMOS18
--# , u_IOBUF_LVCMOS2
--# , u_IOBUF_LVDS
--# , u_IOBUF_LVPECL
--# , u_IOBUF_PCI33_3
--# , u_IOBUF_PCI66_3
--# , u_IOBUF_PCIX66_3
--# , u_IOBUF_SSTL2_I
--# , u_IOBUF_SSTL2_II
--# , u_IOBUF_SSTL3_I
--# , u_IOBUF_SSTL3_II
--# , u_IOBUF_S_12
--# , u_IOBUF_S_16
--# , u_IOBUF_S_2
--# , u_IOBUF_S_24
--# , u_IOBUF_S_4
--# , u_IOBUF_S_6
--# , u_IOBUF_S_8
--# , u_KEEPER
--# , u_LD
--# , u_LDC
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDCP_1
--# , u_LDC_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDPE
--# , u_LDPE_1
--# , u_LDP_1
--# , u_LD_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_NAND2
--# , u_NAND3
--# , u_NAND4
--# , u_NOR2
--# , u_NOR3
--# , u_NOR4
--# , u_OBUF
--# , u_OBUFT
--# , u_OBUFT_AGP
--# , u_OBUFT_CTT
--# , u_OBUFT_F_12
--# , u_OBUFT_F_16
--# , u_OBUFT_F_2
--# , u_OBUFT_F_24
--# , u_OBUFT_F_4
--# , u_OBUFT_F_6
--# , u_OBUFT_F_8
--# , u_OBUFT_GTL
--# , u_OBUFT_GTLP
--# , u_OBUFT_HSTL_I
--# , u_OBUFT_HSTL_III
--# , u_OBUFT_HSTL_IV
--# , u_OBUFT_LVCMOS18
--# , u_OBUFT_LVCMOS2
--# , u_OBUFT_LVDS
--# , u_OBUFT_LVPECL
--# , u_OBUFT_PCI33_3
--# , u_OBUFT_PCI66_3
--# , u_OBUFT_PCIX66_3
--# , u_OBUFT_SSTL2_I
--# , u_OBUFT_SSTL2_II
--# , u_OBUFT_SSTL3_I
--# , u_OBUFT_SSTL3_II
--# , u_OBUFT_S_12
--# , u_OBUFT_S_16
--# , u_OBUFT_S_2
--# , u_OBUFT_S_24
--# , u_OBUFT_S_4
--# , u_OBUFT_S_6
--# , u_OBUFT_S_8
--# , u_OBUF_AGP
--# , u_OBUF_CTT
--# , u_OBUF_F_12
--# , u_OBUF_F_16
--# , u_OBUF_F_2
--# , u_OBUF_F_24
--# , u_OBUF_F_4
--# , u_OBUF_F_6
--# , u_OBUF_F_8
--# , u_OBUF_GTL
--# , u_OBUF_GTLP
--# , u_OBUF_HSTL_I
--# , u_OBUF_HSTL_III
--# , u_OBUF_HSTL_IV
--# , u_OBUF_LVCMOS18
--# , u_OBUF_LVCMOS2
--# , u_OBUF_LVDS
--# , u_OBUF_LVPECL
--# , u_OBUF_PCI33_3
--# , u_OBUF_PCI66_3
--# , u_OBUF_PCIX66_3
--# , u_OBUF_SSTL2_I
--# , u_OBUF_SSTL2_II
--# , u_OBUF_SSTL3_I
--# , u_OBUF_SSTL3_II
--# , u_OBUF_S_12
--# , u_OBUF_S_16
--# , u_OBUF_S_2
--# , u_OBUF_S_24
--# , u_OBUF_S_4
--# , u_OBUF_S_6
--# , u_OBUF_S_8
--# , u_OR2
--# , u_OR3
--# , u_OR4
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAMB4_S1
--# , u_RAMB4_S16
--# , u_RAMB4_S16_S16
--# , u_RAMB4_S1_S1
--# , u_RAMB4_S1_S16
--# , u_RAMB4_S1_S2
--# , u_RAMB4_S1_S4
--# , u_RAMB4_S1_S8
--# , u_RAMB4_S2
--# , u_RAMB4_S2_S16
--# , u_RAMB4_S2_S2
--# , u_RAMB4_S2_S4
--# , u_RAMB4_S2_S8
--# , u_RAMB4_S4
--# , u_RAMB4_S4_S16
--# , u_RAMB4_S4_S4
--# , u_RAMB4_S4_S8
--# , u_RAMB4_S8
--# , u_RAMB4_S8_S16
--# , u_RAMB4_S8_S8
--# , u_ROM16X1
--# , u_ROM32X1
--# , u_SRL16
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRL16_1
--# , u_STARTBUF_SPARTAN2
--# , u_STARTUP_SPARTAN2
--# , u_TOC
--# , u_TOCBUF
--# , u_VCC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# )
--# );
--# set_to(y, virtexe, (
--# u_AND2
--# , u_AND3
--# , u_AND4
--# , u_BSCAN_VIRTEX
--# , u_BUF
--# , u_BUFCF
--# , u_BUFE
--# , u_BUFG
--# , u_BUFGDLL
--# , u_BUFGP
--# , u_BUFT
--# , u_CAPTURE_VIRTEX
--# , u_CLKDLL
--# , u_CLKDLLE
--# , u_CLKDLLHF
--# , u_FD
--# , u_FDC
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDCP_1
--# , u_FDC_1
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDP_1
--# , u_FDR
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDRS_1
--# , u_FDR_1
--# , u_FDS
--# , u_FDSE
--# , u_FDSE_1
--# , u_FDS_1
--# , u_FD_1
--# , u_FMAP
--# , u_GND
--# , u_IBUF
--# , u_IBUFG
--# , u_INV
--# , u_IOBUF
--# , u_KEEPER
--# , u_LD
--# , u_LDC
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDCP_1
--# , u_LDC_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDPE
--# , u_LDPE_1
--# , u_LDP_1
--# , u_LD_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_NAND2
--# , u_NAND3
--# , u_NAND4
--# , u_NOR2
--# , u_NOR3
--# , u_NOR4
--# , u_OBUF
--# , u_OBUFT
--# , u_OR2
--# , u_OR3
--# , u_OR4
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAMB4_S1
--# , u_RAMB4_S16
--# , u_RAMB4_S16_S16
--# , u_RAMB4_S1_S1
--# , u_RAMB4_S1_S16
--# , u_RAMB4_S1_S2
--# , u_RAMB4_S1_S4
--# , u_RAMB4_S1_S8
--# , u_RAMB4_S2
--# , u_RAMB4_S2_S16
--# , u_RAMB4_S2_S2
--# , u_RAMB4_S2_S4
--# , u_RAMB4_S2_S8
--# , u_RAMB4_S4
--# , u_RAMB4_S4_S16
--# , u_RAMB4_S4_S4
--# , u_RAMB4_S4_S8
--# , u_RAMB4_S8
--# , u_RAMB4_S8_S16
--# , u_RAMB4_S8_S8
--# , u_ROM16X1
--# , u_ROM32X1
--# , u_SRL16
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRL16_1
--# , u_STARTBUF_VIRTEX
--# , u_STARTUP_VIRTEX
--# , u_TOC
--# , u_TOCBUF
--# , u_VCC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# )
--# );
--# --
--# set_to(y, virtex2, (
--# u_AND2
--# , u_AND3
--# , u_AND4
--# , u_BSCAN_VIRTEX2
--# , u_BUF
--# , u_BUFCF
--# , u_BUFE
--# , u_BUFG
--# , u_BUFGCE
--# , u_BUFGCE_1
--# , u_BUFGDLL
--# , u_BUFGMUX
--# , u_BUFGMUX_1
--# , u_BUFGP
--# , u_BUFT
--# , u_CAPTURE_VIRTEX2
--# , u_CLKDLL
--# , u_CLKDLLE
--# , u_CLKDLLHF
--# , u_DCM
--# , u_DUMMY_INV
--# , u_DUMMY_NOR2
--# , u_FD
--# , u_FDC
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDCP_1
--# , u_FDC_1
--# , u_FDDRCPE
--# , u_FDDRRSE
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDP_1
--# , u_FDR
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDRS_1
--# , u_FDR_1
--# , u_FDS
--# , u_FDSE
--# , u_FDSE_1
--# , u_FDS_1
--# , u_FD_1
--# , u_FMAP
--# , u_GND
--# , u_IBUF
--# , u_IBUFDS
--# , u_IBUFDS_DIFF_OUT
--# , u_IBUFG
--# , u_IBUFGDS
--# , u_IBUFGDS_DIFF_OUT
--# , u_ICAP_VIRTEX2
--# , u_IFDDRCPE
--# , u_IFDDRRSE
--# , u_INV
--# , u_IOBUF
--# , u_IOBUFDS
--# , u_KEEPER
--# , u_LD
--# , u_LDC
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDCP_1
--# , u_LDC_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDPE
--# , u_LDPE_1
--# , u_LDP_1
--# , u_LD_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_MULT18X18
--# , u_MULT18X18S
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_MUXF7
--# , u_MUXF7_D
--# , u_MUXF7_L
--# , u_MUXF8
--# , u_MUXF8_D
--# , u_MUXF8_L
--# , u_NAND2
--# , u_NAND3
--# , u_NAND4
--# , u_NOR2
--# , u_NOR3
--# , u_NOR4
--# , u_OBUF
--# , u_OBUFDS
--# , u_OBUFT
--# , u_OBUFTDS
--# , u_OFDDRCPE
--# , u_OFDDRRSE
--# , u_OFDDRTCPE
--# , u_OFDDRTRSE
--# , u_OR2
--# , u_OR3
--# , u_OR4
--# , u_ORCY
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM128X1S
--# , u_RAM128X1S_1
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM16X2S
--# , u_RAM16X4S
--# , u_RAM16X8S
--# , u_RAM32X1D
--# , u_RAM32X1D_1
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAM32X2S
--# , u_RAM32X4S
--# , u_RAM32X8S
--# , u_RAM64X1D
--# , u_RAM64X1D_1
--# , u_RAM64X1S
--# , u_RAM64X1S_1
--# , u_RAM64X2S
--# , u_RAMB16_S1
--# , u_RAMB16_S18
--# , u_RAMB16_S18_S18
--# , u_RAMB16_S18_S36
--# , u_RAMB16_S1_S1
--# , u_RAMB16_S1_S18
--# , u_RAMB16_S1_S2
--# , u_RAMB16_S1_S36
--# , u_RAMB16_S1_S4
--# , u_RAMB16_S1_S9
--# , u_RAMB16_S2
--# , u_RAMB16_S2_S18
--# , u_RAMB16_S2_S2
--# , u_RAMB16_S2_S36
--# , u_RAMB16_S2_S4
--# , u_RAMB16_S2_S9
--# , u_RAMB16_S36
--# , u_RAMB16_S36_S36
--# , u_RAMB16_S4
--# , u_RAMB16_S4_S18
--# , u_RAMB16_S4_S36
--# , u_RAMB16_S4_S4
--# , u_RAMB16_S4_S9
--# , u_RAMB16_S9
--# , u_RAMB16_S9_S18
--# , u_RAMB16_S9_S36
--# , u_RAMB16_S9_S9
--# , u_ROM128X1
--# , u_ROM16X1
--# , u_ROM256X1
--# , u_ROM32X1
--# , u_ROM64X1
--# , u_SRL16
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRL16_1
--# , u_SRLC16
--# , u_SRLC16E
--# , u_SRLC16E_1
--# , u_SRLC16_1
--# , u_STARTBUF_VIRTEX2
--# , u_STARTUP_VIRTEX2
--# , u_TOC
--# , u_TOCBUF
--# , u_VCC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# )
--# );
--# --
--# pp(qvirtex2) := pp(virtex2);
--# --
--# pp(qrvirtex2) := pp(virtex2);
--# --
--# set_to(y, virtex2p,
--# (
--# u_AND2
--# , u_AND3
--# , u_AND4
--# , u_BSCAN_VIRTEX2
--# , u_BUF
--# , u_BUFCF
--# , u_BUFE
--# , u_BUFG
--# , u_BUFGCE
--# , u_BUFGCE_1
--# , u_BUFGDLL
--# , u_BUFGMUX
--# , u_BUFGMUX_1
--# , u_BUFGP
--# , u_BUFT
--# , u_CAPTURE_VIRTEX2
--# , u_CLKDLL
--# , u_CLKDLLE
--# , u_CLKDLLHF
--# , u_DCM
--# , u_DUMMY_INV
--# , u_DUMMY_NOR2
--# , u_FD
--# , u_FDC
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDCP_1
--# , u_FDC_1
--# , u_FDDRCPE
--# , u_FDDRRSE
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDP_1
--# , u_FDR
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDRS_1
--# , u_FDR_1
--# , u_FDS
--# , u_FDSE
--# , u_FDSE_1
--# , u_FDS_1
--# , u_FD_1
--# , u_FMAP
--# , u_GND
--# , u_GT10_10GE_4
--# , u_GT10_10GE_8
--# , u_GT10_10GFC_4
--# , u_GT10_10GFC_8
--# , u_GT10_AURORAX_4
--# , u_GT10_AURORAX_8
--# , u_GT10_AURORA_1
--# , u_GT10_AURORA_2
--# , u_GT10_AURORA_4
--# , u_GT10_CUSTOM
--# , u_GT10_INFINIBAND_1
--# , u_GT10_INFINIBAND_2
--# , u_GT10_INFINIBAND_4
--# , u_GT10_OC192_4
--# , u_GT10_OC192_8
--# , u_GT10_OC48_1
--# , u_GT10_OC48_2
--# , u_GT10_OC48_4
--# , u_GT10_PCI_EXPRESS_1
--# , u_GT10_PCI_EXPRESS_2
--# , u_GT10_PCI_EXPRESS_4
--# , u_GT10_XAUI_1
--# , u_GT10_XAUI_2
--# , u_GT10_XAUI_4
--# , u_GT_AURORA_1
--# , u_GT_AURORA_2
--# , u_GT_AURORA_4
--# , u_GT_CUSTOM
--# , u_GT_ETHERNET_1
--# , u_GT_ETHERNET_2
--# , u_GT_ETHERNET_4
--# , u_GT_FIBRE_CHAN_1
--# , u_GT_FIBRE_CHAN_2
--# , u_GT_FIBRE_CHAN_4
--# , u_GT_INFINIBAND_1
--# , u_GT_INFINIBAND_2
--# , u_GT_INFINIBAND_4
--# , u_GT_XAUI_1
--# , u_GT_XAUI_2
--# , u_GT_XAUI_4
--# , u_IBUF
--# , u_IBUFDS
--# , u_IBUFDS_DIFF_OUT
--# , u_IBUFG
--# , u_IBUFGDS
--# , u_IBUFGDS_DIFF_OUT
--# , u_ICAP_VIRTEX2
--# , u_IFDDRCPE
--# , u_IFDDRRSE
--# , u_INV
--# , u_IOBUF
--# , u_IOBUFDS
--# , u_JTAGPPC
--# , u_KEEPER
--# , u_LD
--# , u_LDC
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDCP_1
--# , u_LDC_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDPE
--# , u_LDPE_1
--# , u_LDP_1
--# , u_LD_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_MULT18X18
--# , u_MULT18X18S
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_MUXF7
--# , u_MUXF7_D
--# , u_MUXF7_L
--# , u_MUXF8
--# , u_MUXF8_D
--# , u_MUXF8_L
--# , u_NAND2
--# , u_NAND3
--# , u_NAND4
--# , u_NOR2
--# , u_NOR3
--# , u_NOR4
--# , u_OBUF
--# , u_OBUFDS
--# , u_OBUFT
--# , u_OBUFTDS
--# , u_OFDDRCPE
--# , u_OFDDRRSE
--# , u_OFDDRTCPE
--# , u_OFDDRTRSE
--# , u_OR2
--# , u_OR3
--# , u_OR4
--# , u_ORCY
--# , u_PPC405
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM128X1S
--# , u_RAM128X1S_1
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM16X2S
--# , u_RAM16X4S
--# , u_RAM16X8S
--# , u_RAM32X1D
--# , u_RAM32X1D_1
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAM32X2S
--# , u_RAM32X4S
--# , u_RAM32X8S
--# , u_RAM64X1D
--# , u_RAM64X1D_1
--# , u_RAM64X1S
--# , u_RAM64X1S_1
--# , u_RAM64X2S
--# , u_RAMB16_S1
--# , u_RAMB16_S18
--# , u_RAMB16_S18_S18
--# , u_RAMB16_S18_S36
--# , u_RAMB16_S1_S1
--# , u_RAMB16_S1_S18
--# , u_RAMB16_S1_S2
--# , u_RAMB16_S1_S36
--# , u_RAMB16_S1_S4
--# , u_RAMB16_S1_S9
--# , u_RAMB16_S2
--# , u_RAMB16_S2_S18
--# , u_RAMB16_S2_S2
--# , u_RAMB16_S2_S36
--# , u_RAMB16_S2_S4
--# , u_RAMB16_S2_S9
--# , u_RAMB16_S36
--# , u_RAMB16_S36_S36
--# , u_RAMB16_S4
--# , u_RAMB16_S4_S18
--# , u_RAMB16_S4_S36
--# , u_RAMB16_S4_S4
--# , u_RAMB16_S4_S9
--# , u_RAMB16_S9
--# , u_RAMB16_S9_S18
--# , u_RAMB16_S9_S36
--# , u_RAMB16_S9_S9
--# , u_ROM128X1
--# , u_ROM16X1
--# , u_ROM256X1
--# , u_ROM32X1
--# , u_ROM64X1
--# , u_SRL16
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRL16_1
--# , u_SRLC16
--# , u_SRLC16E
--# , u_SRLC16E_1
--# , u_SRLC16_1
--# , u_STARTBUF_VIRTEX2
--# , u_STARTUP_VIRTEX2
--# , u_TOC
--# , u_TOCBUF
--# , u_VCC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# )
--# );
--# --
--# set_to(y, spartan3,
--# (
--# u_AND2
--# , u_AND3
--# , u_AND4
--# , u_BSCAN_SPARTAN3
--# , u_BUF
--# , u_BUFCF
--# , u_BUFG
--# , u_BUFGCE
--# , u_BUFGCE_1
--# , u_BUFGDLL
--# , u_BUFGMUX
--# , u_BUFGMUX_1
--# , u_BUFGP
--# , u_CAPTURE_SPARTAN3
--# , u_DCM
--# , u_DUMMY_INV
--# , u_DUMMY_NOR2
--# , u_FD
--# , u_FDC
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDCP_1
--# , u_FDC_1
--# , u_FDDRCPE
--# , u_FDDRRSE
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDP_1
--# , u_FDR
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDRS_1
--# , u_FDR_1
--# , u_FDS
--# , u_FDSE
--# , u_FDSE_1
--# , u_FDS_1
--# , u_FD_1
--# , u_FMAP
--# , u_GND
--# , u_IBUF
--# , u_IBUFDS
--# , u_IBUFDS_DIFF_OUT
--# , u_IBUFG
--# , u_IBUFGDS
--# , u_IBUFGDS_DIFF_OUT
--# , u_IFDDRCPE
--# , u_IFDDRRSE
--# , u_INV
--# , u_IOBUF
--# , u_IOBUFDS
--# , u_KEEPER
--# , u_LD
--# , u_LDC
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDCP_1
--# , u_LDC_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDPE
--# , u_LDPE_1
--# , u_LDP_1
--# , u_LD_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_MULT18X18
--# , u_MULT18X18S
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_MUXF7
--# , u_MUXF7_D
--# , u_MUXF7_L
--# , u_MUXF8
--# , u_MUXF8_D
--# , u_MUXF8_L
--# , u_NAND2
--# , u_NAND3
--# , u_NAND4
--# , u_NOR2
--# , u_NOR3
--# , u_NOR4
--# , u_OBUF
--# , u_OBUFDS
--# , u_OBUFT
--# , u_OBUFTDS
--# , u_OFDDRCPE
--# , u_OFDDRRSE
--# , u_OFDDRTCPE
--# , u_OFDDRTRSE
--# , u_OR2
--# , u_OR3
--# , u_OR4
--# , u_ORCY
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM16X2S
--# , u_RAM16X4S
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAM32X2S
--# , u_RAM64X1S
--# , u_RAM64X1S_1
--# , u_RAMB16_S1
--# , u_RAMB16_S18
--# , u_RAMB16_S18_S18
--# , u_RAMB16_S18_S36
--# , u_RAMB16_S1_S1
--# , u_RAMB16_S1_S18
--# , u_RAMB16_S1_S2
--# , u_RAMB16_S1_S36
--# , u_RAMB16_S1_S4
--# , u_RAMB16_S1_S9
--# , u_RAMB16_S2
--# , u_RAMB16_S2_S18
--# , u_RAMB16_S2_S2
--# , u_RAMB16_S2_S36
--# , u_RAMB16_S2_S4
--# , u_RAMB16_S2_S9
--# , u_RAMB16_S36
--# , u_RAMB16_S36_S36
--# , u_RAMB16_S4
--# , u_RAMB16_S4_S18
--# , u_RAMB16_S4_S36
--# , u_RAMB16_S4_S4
--# , u_RAMB16_S4_S9
--# , u_RAMB16_S9
--# , u_RAMB16_S9_S18
--# , u_RAMB16_S9_S36
--# , u_RAMB16_S9_S9
--# , u_ROM128X1
--# , u_ROM16X1
--# , u_ROM256X1
--# , u_ROM32X1
--# , u_ROM64X1
--# , u_SRL16
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRL16_1
--# , u_SRLC16
--# , u_SRLC16E
--# , u_SRLC16E_1
--# , u_SRLC16_1
--# , u_STARTBUF_SPARTAN3
--# , u_STARTUP_SPARTAN3
--# , u_TOC
--# , u_TOCBUF
--# , u_VCC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# )
--# );
--# --
--# pp(aspartan3) := pp(spartan3);
--# --
--# set_to(y, spartan3e,
--# (
--# u_AND2
--# , u_AND3
--# , u_AND4
--# , u_BSCAN_SPARTAN3
--# , u_BUF
--# , u_BUFCF
--# , u_BUFG
--# , u_BUFGCE
--# , u_BUFGCE_1
--# , u_BUFGDLL
--# , u_BUFGMUX
--# , u_BUFGMUX_1
--# , u_BUFGP
--# , u_CAPTURE_SPARTAN3E
--# , u_DCM
--# , u_DUMMY_INV
--# , u_DUMMY_NOR2
--# , u_FD
--# , u_FDC
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDCP_1
--# , u_FDC_1
--# , u_FDDRCPE
--# , u_FDDRRSE
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDP_1
--# , u_FDR
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDRS_1
--# , u_FDR_1
--# , u_FDS
--# , u_FDSE
--# , u_FDSE_1
--# , u_FDS_1
--# , u_FD_1
--# , u_FMAP
--# , u_GND
--# , u_IBUF
--# , u_IBUFDS
--# , u_IBUFDS_DIFF_OUT
--# , u_IBUFG
--# , u_IBUFGDS
--# , u_IBUFGDS_DIFF_OUT
--# , u_IDDR2
--# , u_IFDDRCPE
--# , u_IFDDRRSE
--# , u_INV
--# , u_IOBUF
--# , u_IOBUFDS
--# , u_KEEPER
--# , u_LD
--# , u_LDC
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDCP_1
--# , u_LDC_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDPE
--# , u_LDPE_1
--# , u_LDP_1
--# , u_LD_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_MULT18X18
--# , u_MULT18X18S
--# , u_MULT18X18SIO
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_MUXF7
--# , u_MUXF7_D
--# , u_MUXF7_L
--# , u_MUXF8
--# , u_MUXF8_D
--# , u_MUXF8_L
--# , u_NAND2
--# , u_NAND3
--# , u_NAND4
--# , u_NOR2
--# , u_NOR3
--# , u_NOR4
--# , u_OBUF
--# , u_OBUFDS
--# , u_OBUFT
--# , u_OBUFTDS
--# , u_ODDR2
--# , u_OFDDRCPE
--# , u_OFDDRRSE
--# , u_OFDDRTCPE
--# , u_OFDDRTRSE
--# , u_OR2
--# , u_OR3
--# , u_OR4
--# , u_ORCY
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM16X2S
--# , u_RAM16X4S
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAM32X2S
--# , u_RAM64X1S
--# , u_RAM64X1S_1
--# , u_RAMB16_S1
--# , u_RAMB16_S18
--# , u_RAMB16_S18_S18
--# , u_RAMB16_S18_S36
--# , u_RAMB16_S1_S1
--# , u_RAMB16_S1_S18
--# , u_RAMB16_S1_S2
--# , u_RAMB16_S1_S36
--# , u_RAMB16_S1_S4
--# , u_RAMB16_S1_S9
--# , u_RAMB16_S2
--# , u_RAMB16_S2_S18
--# , u_RAMB16_S2_S2
--# , u_RAMB16_S2_S36
--# , u_RAMB16_S2_S4
--# , u_RAMB16_S2_S9
--# , u_RAMB16_S36
--# , u_RAMB16_S36_S36
--# , u_RAMB16_S4
--# , u_RAMB16_S4_S18
--# , u_RAMB16_S4_S36
--# , u_RAMB16_S4_S4
--# , u_RAMB16_S4_S9
--# , u_RAMB16_S9
--# , u_RAMB16_S9_S18
--# , u_RAMB16_S9_S36
--# , u_RAMB16_S9_S9
--# , u_ROM128X1
--# , u_ROM16X1
--# , u_ROM256X1
--# , u_ROM32X1
--# , u_ROM64X1
--# , u_SRL16
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRL16_1
--# , u_SRLC16
--# , u_SRLC16E
--# , u_SRLC16E_1
--# , u_SRLC16_1
--# , u_STARTBUF_SPARTAN3E
--# , u_STARTUP_SPARTAN3E
--# , u_TOC
--# , u_TOCBUF
--# , u_VCC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# )
--# );
--# --
--# pp(aspartan3e) := pp(spartan3e);
--# --
--# set_to(y, virtex4fx,
--# (
--# u_AND2
--# , u_AND3
--# , u_AND4
--# , u_BSCAN_VIRTEX4
--# , u_BUF
--# , u_BUFCF
--# , u_BUFG
--# , u_BUFGCE
--# , u_BUFGCE_1
--# , u_BUFGCTRL
--# , u_BUFGMUX
--# , u_BUFGMUX_1
--# , u_BUFGMUX_VIRTEX4
--# , u_BUFGP
--# , u_BUFGP
--# , u_BUFIO
--# , u_BUFR
--# , u_CAPTURE_VIRTEX4
--# , u_DCIRESET
--# , u_DCM
--# , u_DCM_ADV
--# , u_DCM_BASE
--# , u_DCM_PS
--# , u_DSP48
--# , u_EMAC
--# , u_FD
--# , u_FDC
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDCP_1
--# , u_FDC_1
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDP_1
--# , u_FDR
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDRS_1
--# , u_FDR_1
--# , u_FDS
--# , u_FDSE
--# , u_FDSE_1
--# , u_FDS_1
--# , u_FD_1
--# , u_FIFO16
--# , u_FMAP
--# , u_FRAME_ECC_VIRTEX4
--# , u_GND
--# , u_GT11CLK
--# , u_GT11CLK_MGT
--# , u_GT11_CUSTOM
--# , u_IBUF
--# , u_IBUFDS
--# , u_IBUFDS_DIFF_OUT
--# , u_IBUFG
--# , u_IBUFGDS
--# , u_IBUFGDS_DIFF_OUT
--# , u_ICAP_VIRTEX4
--# , u_IDDR
--# , u_IDELAY
--# , u_IDELAYCTRL
--# , u_INV
--# , u_IOBUF
--# , u_IOBUFDS
--# , u_ISERDES
--# , u_JTAGPPC
--# , u_KEEPER
--# , u_LD
--# , u_LDC
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDCP_1
--# , u_LDC_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDPE
--# , u_LDPE_1
--# , u_LDP_1
--# , u_LD_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_MULT18X18
--# , u_MULT18X18S
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_MUXF7
--# , u_MUXF7_D
--# , u_MUXF7_L
--# , u_MUXF8
--# , u_MUXF8_D
--# , u_MUXF8_L
--# , u_NAND2
--# , u_NAND3
--# , u_NAND4
--# , u_NOR2
--# , u_NOR3
--# , u_NOR4
--# , u_OBUF
--# , u_OBUFDS
--# , u_OBUFT
--# , u_OBUFTDS
--# , u_ODDR
--# , u_OR2
--# , u_OR3
--# , u_OR4
--# , u_OSERDES
--# , u_PMCD
--# , u_PPC405
--# , u_PPC405_ADV
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM16X2S
--# , u_RAM16X4S
--# , u_RAM16X8S
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAM32X2S
--# , u_RAM32X4S
--# , u_RAM32X8S
--# , u_RAM64X1S
--# , u_RAM64X1S_1
--# , u_RAM64X2S
--# , u_RAMB16
--# , u_RAMB16_S1
--# , u_RAMB16_S18
--# , u_RAMB16_S18_S18
--# , u_RAMB16_S18_S36
--# , u_RAMB16_S1_S1
--# , u_RAMB16_S1_S18
--# , u_RAMB16_S1_S2
--# , u_RAMB16_S1_S36
--# , u_RAMB16_S1_S4
--# , u_RAMB16_S1_S9
--# , u_RAMB16_S2
--# , u_RAMB16_S2_S18
--# , u_RAMB16_S2_S2
--# , u_RAMB16_S2_S36
--# , u_RAMB16_S2_S4
--# , u_RAMB16_S2_S9
--# , u_RAMB16_S36
--# , u_RAMB16_S36_S36
--# , u_RAMB16_S4
--# , u_RAMB16_S4_S18
--# , u_RAMB16_S4_S36
--# , u_RAMB16_S4_S4
--# , u_RAMB16_S4_S9
--# , u_RAMB16_S9
--# , u_RAMB16_S9_S18
--# , u_RAMB16_S9_S36
--# , u_RAMB16_S9_S9
--# , u_RAMB32_S64_ECC
--# , u_ROM128X1
--# , u_ROM16X1
--# , u_ROM256X1
--# , u_ROM32X1
--# , u_ROM64X1
--# , u_SRL16
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRL16_1
--# , u_SRLC16
--# , u_SRLC16E
--# , u_SRLC16E_1
--# , u_SRLC16_1
--# , u_STARTBUF_VIRTEX4
--# , u_STARTUP_VIRTEX4
--# , u_TOC
--# , u_TOCBUF
--# , u_USR_ACCESS_VIRTEX4
--# , u_VCC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# )
--# );
--# --
--# pp(virtex4sx) := pp(virtex4fx);
--# --
--# pp(virtex4lx) := pp(virtex4fx);
--# set_to(n, virtex4lx, (u_EMAC,
--# u_GT11CLK, u_GT11CLK_MGT, u_GT11_CUSTOM,
--# u_JTAGPPC, u_PPC405, u_PPC405_ADV
--# ) );
--# --
--# pp(virtex4) := pp(virtex4lx); -- virtex4 is defined as the largest set
--# -- of primitives that EVERY virtex4
--# -- device supports, i.e.. a design that uses
--# -- the virtex4 subset of primitives
--# -- is compatible with any variant of
--# -- the virtex4 family.
--# --
--# pp(qvirtex4) := pp(virtex4);
--# --
--# pp(qrvirtex4) := pp(virtex4);
--# --
--# set_to(y, virtex5,
--# (
--# u_AND2
--# , u_AND3
--# , u_AND4
--# , u_BSCAN_VIRTEX5
--# , u_BUF
--# , u_BUFCF
--# , u_BUFG
--# , u_BUFGCE
--# , u_BUFGCE_1
--# , u_BUFGCTRL
--# , u_BUFGMUX
--# , u_BUFGMUX_1
--# , u_BUFGMUX_CTRL
--# , u_BUFGP
--# , u_BUFIO
--# , u_BUFR
--# , u_CAPTURE_VIRTEX5
--# , u_CARRY4
--# , u_CFGLUT5
--# , u_CRC32
--# , u_CRC64
--# , u_DCIRESET
--# , u_DCM
--# , u_DCM_ADV
--# , u_DCM_BASE
--# , u_DCM_PS
--# , u_DSP48
--# , u_DSP48E
--# , u_EMAC
--# , u_FD
--# , u_FDC
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDCP_1
--# , u_FDC_1
--# , u_FDDRCPE
--# , u_FDDRRSE
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDP_1
--# , u_FDR
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDRS_1
--# , u_FDR_1
--# , u_FDS
--# , u_FDSE
--# , u_FDSE_1
--# , u_FDS_1
--# , u_FD_1
--# , u_FIFO16
--# , u_FIFO18
--# , u_FIFO18_36
--# , u_FIFO36
--# , u_FIFO36_72
--# , u_FMAP
--# , u_FRAME_ECC_VIRTEX5
--# , u_GND
--# , u_GT11CLK
--# , u_GT11CLK_MGT
--# , u_GT11_CUSTOM
--# , u_IBUF
--# , u_IBUFDS
--# , u_IBUFDS_DIFF_OUT
--# , u_IBUFG
--# , u_IBUFGDS
--# , u_IBUFGDS_DIFF_OUT
--# , u_ICAP_VIRTEX5
--# , u_IDDR
--# , u_IDDR_2CLK
--# , u_IDELAY
--# , u_IDELAYCTRL
--# , u_IFDDRCPE
--# , u_IFDDRRSE
--# , u_INV
--# , u_IOBUF
--# , u_IOBUFDS
--# , u_IODELAY
--# , u_ISERDES
--# , u_ISERDES_NODELAY
--# , u_KEEPER
--# , u_KEY_CLEAR
--# , u_LD
--# , u_LDC
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDCP_1
--# , u_LDC_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDPE
--# , u_LDPE_1
--# , u_LDP_1
--# , u_LD_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_LUT5
--# , u_LUT5_D
--# , u_LUT5_L
--# , u_LUT6
--# , u_LUT6_D
--# , u_LUT6_L
--# , u_MULT18X18
--# , u_MULT18X18S
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_MUXF7
--# , u_MUXF7_D
--# , u_MUXF7_L
--# , u_MUXF8
--# , u_MUXF8_D
--# , u_MUXF8_L
--# , u_NAND2
--# , u_NAND3
--# , u_NAND4
--# , u_NOR2
--# , u_NOR3
--# , u_NOR4
--# , u_OBUF
--# , u_OBUFDS
--# , u_OBUFT
--# , u_OBUFTDS
--# , u_ODDR
--# , u_OFDDRCPE
--# , u_OFDDRRSE
--# , u_OFDDRTCPE
--# , u_OFDDRTRSE
--# , u_OR2
--# , u_OR3
--# , u_OR4
--# , u_OSERDES
--# , u_PLL_ADV
--# , u_PLL_BASE
--# , u_PMCD
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM128X1D
--# , u_RAM128X1S
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM16X2S
--# , u_RAM16X4S
--# , u_RAM16X8S
--# , u_RAM256X1S
--# , u_RAM32M
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAM32X2S
--# , u_RAM32X4S
--# , u_RAM32X8S
--# , u_RAM64M
--# , u_RAM64X1D
--# , u_RAM64X1S
--# , u_RAM64X1S_1
--# , u_RAM64X2S
--# , u_RAMB16
--# , u_RAMB16_S1
--# , u_RAMB16_S18
--# , u_RAMB16_S18_S18
--# , u_RAMB16_S18_S36
--# , u_RAMB16_S1_S1
--# , u_RAMB16_S1_S18
--# , u_RAMB16_S1_S2
--# , u_RAMB16_S1_S36
--# , u_RAMB16_S1_S4
--# , u_RAMB16_S1_S9
--# , u_RAMB16_S2
--# , u_RAMB16_S2_S18
--# , u_RAMB16_S2_S2
--# , u_RAMB16_S2_S36
--# , u_RAMB16_S2_S4
--# , u_RAMB16_S2_S9
--# , u_RAMB16_S36
--# , u_RAMB16_S36_S36
--# , u_RAMB16_S4
--# , u_RAMB16_S4_S18
--# , u_RAMB16_S4_S36
--# , u_RAMB16_S4_S4
--# , u_RAMB16_S4_S9
--# , u_RAMB16_S9
--# , u_RAMB16_S9_S18
--# , u_RAMB16_S9_S36
--# , u_RAMB16_S9_S9
--# , u_RAMB18
--# , u_RAMB18SDP
--# , u_RAMB32_S64_ECC
--# , u_RAMB36
--# , u_RAMB36SDP
--# , u_RAMB36SDP_EXP
--# , u_RAMB36_EXP
--# , u_ROM128X1
--# , u_ROM16X1
--# , u_ROM256X1
--# , u_ROM32X1
--# , u_ROM64X1
--# , u_SRL16
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRL16_1
--# , u_SRLC16
--# , u_SRLC16E
--# , u_SRLC16E_1
--# , u_SRLC16_1
--# , u_SRLC32E
--# , u_STARTUP_VIRTEX5
--# , u_SYSMON
--# , u_TOC
--# , u_TOCBUF
--# , u_USR_ACCESS_VIRTEX5
--# , u_VCC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# )
--# );
--# --
--# pp(spartan3a) := pp(spartan3e); -- Populate spartan3a by taking
--# -- differences from spartan3e.
--# set_to(n, spartan3a, (
--# u_BSCAN_SPARTAN3
--# , u_CAPTURE_SPARTAN3E
--# , u_DUMMY_INV
--# , u_DUMMY_NOR2
--# , u_STARTBUF_SPARTAN3E
--# , u_STARTUP_SPARTAN3E
--# ) );
--# set_to(y, spartan3a, (
--# u_BSCAN_SPARTAN3A
--# , u_CAPTURE_SPARTAN3A
--# , u_DCM_PS
--# , u_DNA_PORT
--# , u_IBUF_DLY_ADJ
--# , u_IBUFDS_DLY_ADJ
--# , u_ICAP_SPARTAN3A
--# , u_RAMB16BWE
--# , u_RAMB16BWE_S18
--# , u_RAMB16BWE_S18_S18
--# , u_RAMB16BWE_S18_S9
--# , u_RAMB16BWE_S36
--# , u_RAMB16BWE_S36_S18
--# , u_RAMB16BWE_S36_S36
--# , u_RAMB16BWE_S36_S9
--# , u_SPI_ACCESS
--# , u_STARTUP_SPARTAN3A
--# ) );
--#
--# --
--# pp(aspartan3a) := pp(spartan3a);
--# --
--# pp(spartan3an) := pp(spartan3a);
--# --
--# pp(spartan3adsp) := pp(spartan3a);
--# set_to(y, spartan3adsp, (
--# u_DSP48A
--# , u_RAMB16BWER
--# ) );
--# --
--# pp(aspartan3adsp) := pp(spartan3adsp);
--# --
--# set_to(y, spartan6, (
--# u_AND2
--# , u_AND2B1L
--# , u_AND3
--# , u_AND4
--# , u_AUTOBUF
--# , u_BSCAN_SPARTAN6
--# , u_BUF
--# , u_BUFCF
--# , u_BUFG
--# , u_BUFGCE
--# , u_BUFGCE_1
--# , u_BUFGDLL
--# , u_BUFGMUX
--# , u_BUFGMUX
--# , u_BUFGMUX_1
--# , u_BUFGMUX_1
--# , u_BUFGP
--# , u_BUFH
--# , u_BUFIO2
--# , u_BUFIO2_2CLK
--# , u_BUFIO2FB
--# , u_BUFIO2FB_2CLK
--# , u_BUFPLL
--# , u_BUFPLL_MCB
--# , u_CAPTURE_SPARTAN3A
--# , u_DCM
--# , u_DCM_CLKGEN
--# , u_DCM_PS
--# , u_DNA_PORT
--# , u_DSP48A1
--# , u_FD
--# , u_FD_1
--# , u_FDC
--# , u_FDC_1
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCP_1
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDDRCPE
--# , u_FDDRRSE
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDP_1
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDR
--# , u_FDR_1
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRS_1
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDS
--# , u_FDS_1
--# , u_FDSE
--# , u_FDSE_1
--# , u_FMAP
--# , u_GND
--# , u_GTPA1_DUAL
--# , u_IBUF
--# , u_IBUF_DLY_ADJ
--# , u_IBUFDS
--# , u_IBUFDS_DIFF_OUT
--# , u_IBUFDS_DLY_ADJ
--# , u_IBUFG
--# , u_IBUFGDS
--# , u_IBUFGDS_DIFF_OUT
--# , u_ICAP_SPARTAN3A
--# , u_ICAP_SPARTAN6
--# , u_IDDR2
--# , u_IFDDRCPE
--# , u_IFDDRRSE
--# , u_INV
--# , u_IOBUF
--# , u_IOBUFDS
--# , u_IODELAY2
--# , u_IODRP2
--# , u_IODRP2_MCB
--# , u_ISERDES2
--# , u_JTAG_SIM_SPARTAN6
--# , u_KEEPER
--# , u_LD
--# , u_LD_1
--# , u_LDC
--# , u_LDC_1
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCP_1
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDP_1
--# , u_LDPE
--# , u_LDPE_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_LUT5
--# , u_LUT5_D
--# , u_LUT5_L
--# , u_LUT6
--# , u_LUT6_D
--# , u_LUT6_L
--# , u_MCB
--# , u_MULT18X18
--# , u_MULT18X18S
--# , u_MULT18X18SIO
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_MUXF7
--# , u_MUXF7_D
--# , u_MUXF7_L
--# , u_MUXF8
--# , u_MUXF8_D
--# , u_MUXF8_L
--# , u_NAND2
--# , u_NAND3
--# , u_NAND4
--# , u_NOR2
--# , u_NOR3
--# , u_NOR4
--# , u_OBUF
--# , u_OBUFDS
--# , u_OBUFT
--# , u_OBUFTDS
--# , u_OCT_CALIBRATE
--# , u_ODDR2
--# , u_OFDDRCPE
--# , u_OFDDRRSE
--# , u_OFDDRTCPE
--# , u_OFDDRTRSE
--# , u_OR2
--# , u_OR2L
--# , u_OR3
--# , u_OR4
--# , u_ORCY
--# , u_OSERDES2
--# , u_PCIE_A1
--# , u_PLL_ADV
--# , u_POST_CRC_INTERNAL
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM16X2S
--# , u_RAM16X4S
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAM32X2S
--# , u_RAM64X1S
--# , u_RAM64X1S_1
--# , u_RAMB16BWE
--# , u_RAMB16BWE_S18
--# , u_RAMB16BWE_S18_S18
--# , u_RAMB16BWE_S18_S9
--# , u_RAMB16BWE_S36
--# , u_RAMB16BWE_S36_S18
--# , u_RAMB16BWE_S36_S36
--# , u_RAMB16BWE_S36_S9
--# , u_RAMB16_S1
--# , u_RAMB16_S18
--# , u_RAMB16_S18_S18
--# , u_RAMB16_S18_S36
--# , u_RAMB16_S1_S1
--# , u_RAMB16_S1_S18
--# , u_RAMB16_S1_S2
--# , u_RAMB16_S1_S36
--# , u_RAMB16_S1_S4
--# , u_RAMB16_S1_S9
--# , u_RAMB16_S2
--# , u_RAMB16_S2_S18
--# , u_RAMB16_S2_S2
--# , u_RAMB16_S2_S36
--# , u_RAMB16_S2_S4
--# , u_RAMB16_S2_S9
--# , u_RAMB16_S36
--# , u_RAMB16_S36_S36
--# , u_RAMB16_S4
--# , u_RAMB16_S4_S18
--# , u_RAMB16_S4_S36
--# , u_RAMB16_S4_S4
--# , u_RAMB16_S4_S9
--# , u_RAMB16_S9
--# , u_RAMB16_S9_S18
--# , u_RAMB16_S9_S36
--# , u_RAMB16_S9_S9
--# , u_RAMB8BWER
--# , u_ROM128X1
--# , u_ROM16X1
--# , u_ROM256X1
--# , u_ROM32X1
--# , u_ROM64X1
--# , u_SLAVE_SPI
--# , u_SPI_ACCESS
--# , u_SRL16
--# , u_SRL16_1
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRLC16
--# , u_SRLC16_1
--# , u_SRLC16E
--# , u_SRLC16E_1
--# , u_SRLC32E
--# , u_STARTUP_SPARTAN3A
--# , u_STARTUP_SPARTAN6
--# , u_SUSPEND_SYNC
--# , u_TOC
--# , u_TOCBUF
--# , u_VCC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# ) );
--# --
--# --
--# set_to(y, virtex6, (
--# u_AND2
--# , u_AND2B1L
--# , u_AND3
--# , u_AND4
--# , u_AUTOBUF
--# , u_BSCAN_VIRTEX6
--# , u_BUF
--# , u_BUFCF
--# , u_BUFG
--# , u_BUFGCE
--# , u_BUFGCE_1
--# , u_BUFGCTRL
--# , u_BUFGMUX
--# , u_BUFGMUX_1
--# , u_BUFGMUX_CTRL
--# , u_BUFGP
--# , u_BUFH
--# , u_BUFHCE
--# , u_BUFIO
--# , u_BUFIODQS
--# , u_BUFR
--# , u_CAPTURE_VIRTEX5
--# , u_CAPTURE_VIRTEX6
--# , u_CARRY4
--# , u_CFGLUT5
--# , u_CRC32
--# , u_CRC64
--# , u_DCIRESET
--# , u_DCIRESET
--# , u_DCM
--# , u_DCM_ADV
--# , u_DCM_BASE
--# , u_DCM_PS
--# , u_DSP48
--# , u_DSP48E
--# , u_DSP48E1
--# , u_EFUSE_USR
--# , u_EMAC
--# , u_FD
--# , u_FD_1
--# , u_FDC
--# , u_FDC_1
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCP_1
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDDRCPE
--# , u_FDDRRSE
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDP_1
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDR
--# , u_FDR_1
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRS_1
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDS
--# , u_FDS_1
--# , u_FDSE
--# , u_FDSE_1
--# , u_FIFO16
--# , u_FIFO18
--# , u_FIFO18_36
--# , u_FIFO18E1
--# , u_FIFO36
--# , u_FIFO36_72
--# , u_FIFO36E1
--# , u_FMAP
--# , u_FRAME_ECC_VIRTEX5
--# , u_FRAME_ECC_VIRTEX6
--# , u_GND
--# , u_GT11CLK
--# , u_GT11CLK_MGT
--# , u_GT11_CUSTOM
--# , u_GTXE1
--# , u_IBUF
--# , u_IBUF
--# , u_IBUFDS
--# , u_IBUFDS
--# , u_IBUFDS_DIFF_OUT
--# , u_IBUFDS_GTXE1
--# , u_IBUFG
--# , u_IBUFG
--# , u_IBUFGDS
--# , u_IBUFGDS
--# , u_IBUFGDS_DIFF_OUT
--# , u_ICAP_VIRTEX5
--# , u_ICAP_VIRTEX6
--# , u_IDDR
--# , u_IDDR_2CLK
--# , u_IDELAY
--# , u_IDELAYCTRL
--# , u_IFDDRCPE
--# , u_IFDDRRSE
--# , u_INV
--# , u_IOBUF
--# , u_IOBUF
--# , u_IOBUFDS
--# , u_IOBUFDS
--# , u_IOBUFDS_DIFF_OUT
--# , u_IODELAY
--# , u_IODELAYE1
--# , u_ISERDES
--# , u_ISERDESE1
--# , u_ISERDES_NODELAY
--# , u_JTAG_SIM_VIRTEX6
--# , u_KEEPER
--# , u_KEY_CLEAR
--# , u_LD
--# , u_LD_1
--# , u_LDC
--# , u_LDC_1
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCP_1
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDP_1
--# , u_LDPE
--# , u_LDPE_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_LUT5
--# , u_LUT5_D
--# , u_LUT5_L
--# , u_LUT6
--# , u_LUT6_D
--# , u_LUT6_L
--# , u_MMCM_ADV
--# , u_MMCM_BASE
--# , u_MULT18X18
--# , u_MULT18X18S
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_MUXF7
--# , u_MUXF7_D
--# , u_MUXF7_L
--# , u_MUXF8
--# , u_MUXF8_D
--# , u_MUXF8_L
--# , u_NAND2
--# , u_NAND3
--# , u_NAND4
--# , u_NOR2
--# , u_NOR3
--# , u_NOR4
--# , u_OBUF
--# , u_OBUFDS
--# , u_OBUFT
--# , u_OBUFTDS
--# , u_ODDR
--# , u_OFDDRCPE
--# , u_OFDDRRSE
--# , u_OFDDRTCPE
--# , u_OFDDRTRSE
--# , u_OR2
--# , u_OR2L
--# , u_OR3
--# , u_OR4
--# , u_OSERDES
--# , u_OSERDESE1
--# , u_PCIE_2_0
--# , u_PLL_ADV
--# , u_PLL_BASE
--# , u_PMCD
--# , u_PPR_FRAME
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM128X1D
--# , u_RAM128X1S
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM16X2S
--# , u_RAM16X4S
--# , u_RAM16X8S
--# , u_RAM256X1S
--# , u_RAM32M
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAM32X2S
--# , u_RAM32X4S
--# , u_RAM32X8S
--# , u_RAM64M
--# , u_RAM64X1D
--# , u_RAM64X1S
--# , u_RAM64X1S_1
--# , u_RAM64X2S
--# , u_RAMB16
--# , u_RAMB16_S1
--# , u_RAMB16_S18
--# , u_RAMB16_S18_S18
--# , u_RAMB16_S18_S36
--# , u_RAMB16_S1_S1
--# , u_RAMB16_S1_S18
--# , u_RAMB16_S1_S2
--# , u_RAMB16_S1_S36
--# , u_RAMB16_S1_S4
--# , u_RAMB16_S1_S9
--# , u_RAMB16_S2
--# , u_RAMB16_S2_S18
--# , u_RAMB16_S2_S2
--# , u_RAMB16_S2_S36
--# , u_RAMB16_S2_S4
--# , u_RAMB16_S2_S9
--# , u_RAMB16_S36
--# , u_RAMB16_S36_S36
--# , u_RAMB16_S4
--# , u_RAMB16_S4_S18
--# , u_RAMB16_S4_S36
--# , u_RAMB16_S4_S4
--# , u_RAMB16_S4_S9
--# , u_RAMB16_S9
--# , u_RAMB16_S9_S18
--# , u_RAMB16_S9_S36
--# , u_RAMB16_S9_S9
--# , u_RAMB18
--# , u_RAMB18E1
--# , u_RAMB18SDP
--# , u_RAMB32_S64_ECC
--# , u_RAMB36
--# , u_RAMB36E1
--# , u_RAMB36_EXP
--# , u_RAMB36SDP
--# , u_RAMB36SDP_EXP
--# , u_ROM128X1
--# , u_ROM16X1
--# , u_ROM256X1
--# , u_ROM32X1
--# , u_ROM64X1
--# , u_SRL16
--# , u_SRL16_1
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRLC16
--# , u_SRLC16_1
--# , u_SRLC16E
--# , u_SRLC16E_1
--# , u_SRLC32E
--# , u_STARTUP_VIRTEX5
--# , u_STARTUP_VIRTEX6
--# , u_SYSMON
--# , u_SYSMON
--# , u_TEMAC_SINGLE
--# , u_TOC
--# , u_TOCBUF
--# , u_USR_ACCESS_VIRTEX5
--# , u_USR_ACCESS_VIRTEX6
--# , u_VCC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# ) );
--# --
--# pp(spartan6l) := pp(spartan6);
--# --
--# pp(qspartan6) := pp(spartan6);
--# --
--# pp(aspartan6) := pp(spartan6);
--# --
--# pp(virtex6l) := pp(virtex6);
--# --
--# pp(qspartan6l) := pp(spartan6);
--# --
--# pp(qvirtex5) := pp(virtex5);
--# --
--# pp(qvirtex6) := pp(virtex6);
--# --
--# pp(qrvirtex5) := pp(virtex5);
--# --
--# pp(virtex5tx) := pp(virtex5);
--# --
--# pp(virtex5fx) := pp(virtex5);
--# --
--# pp(virtex6cx) := pp(virtex6);
--# --
--# set_to(y, kintex7, (
--# u_AND2
--# , u_AND2B1
--# , u_AND2B1L
--# , u_AND2B2
--# , u_AND3
--# , u_AND3B1
--# , u_AND3B2
--# , u_AND3B3
--# , u_AND4
--# , u_AND4B1
--# , u_AND4B2
--# , u_AND4B3
--# , u_AND4B4
--# , u_AND5
--# , u_AND5B1
--# , u_AND5B2
--# , u_AND5B3
--# , u_AND5B4
--# , u_AND5B5
--# , u_AUTOBUF
--# , u_BSCANE2
--# , u_BUF
--# , u_BUFCF
--# , u_BUFG
--# , u_BUFGCE
--# , u_BUFGCE_1
--# , u_BUFGCTRL
--# , u_BUFGMUX
--# , u_BUFGMUX_1
--# , u_BUFGP
--# , u_BUFH
--# , u_BUFHCE
--# , u_BUFIO
--# , u_BUFMR
--# , u_BUFMRCE
--# , u_BUFR
--# , u_BUFT
--# , u_CAPTUREE2
--# , u_CARRY4
--# , u_CFGLUT5
--# , u_DCIRESET
--# , u_DNA_PORT
--# , u_DSP48E1
--# , u_EFUSE_USR
--# , u_FD
--# , u_FD_1
--# , u_FDC
--# , u_FDC_1
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCP_1
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDP_1
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDR
--# , u_FDR_1
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRS_1
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDS
--# , u_FDS_1
--# , u_FDSE
--# , u_FDSE_1
--# , u_FIFO18E1
--# , u_FIFO36E1
--# , u_FMAP
--# , u_FRAME_ECCE2
--# , u_GND
--# , u_GTXE2_CHANNEL
--# , u_GTXE2_COMMON
--# , u_IBUF
--# , u_IBUF_DCIEN
--# , u_IBUFDS
--# , u_IBUFDS_BLVDS_25
--# , u_IBUFDS_DCIEN
--# , u_IBUFDS_DIFF_OUT
--# , u_IBUFDS_DIFF_OUT_DCIEN
--# , u_IBUFDS_GTE2
--# , u_IBUFDS_LVDS_25
--# , u_IBUFG
--# , u_IBUFGDS
--# , u_IBUFGDS_BLVDS_25
--# , u_IBUFGDS_DIFF_OUT
--# , u_IBUFGDS_LVDS_25
--# , u_IBUFG_HSTL_I
--# , u_IBUFG_HSTL_I_18
--# , u_IBUFG_HSTL_I_DCI
--# , u_IBUFG_HSTL_I_DCI_18
--# , u_IBUFG_HSTL_II
--# , u_IBUFG_HSTL_II_18
--# , u_IBUFG_HSTL_II_DCI
--# , u_IBUFG_HSTL_II_DCI_18
--# , u_IBUFG_HSTL_III
--# , u_IBUFG_HSTL_III_18
--# , u_IBUFG_HSTL_III_DCI
--# , u_IBUFG_HSTL_III_DCI_18
--# , u_IBUFG_LVCMOS12
--# , u_IBUFG_LVCMOS15
--# , u_IBUFG_LVCMOS18
--# , u_IBUFG_LVCMOS25
--# , u_IBUFG_LVCMOS33
--# , u_IBUFG_LVDCI_15
--# , u_IBUFG_LVDCI_18
--# , u_IBUFG_LVDCI_DV2_15
--# , u_IBUFG_LVDCI_DV2_18
--# , u_IBUFG_LVDS
--# , u_IBUFG_LVPECL
--# , u_IBUFG_LVTTL
--# , u_IBUFG_PCI33_3
--# , u_IBUFG_PCI66_3
--# , u_IBUFG_PCIX66_3
--# , u_IBUFG_SSTL18_I
--# , u_IBUFG_SSTL18_I_DCI
--# , u_IBUFG_SSTL18_II
--# , u_IBUFG_SSTL18_II_DCI
--# , u_IBUF_HSTL_I
--# , u_IBUF_HSTL_I_18
--# , u_IBUF_HSTL_I_DCI
--# , u_IBUF_HSTL_I_DCI_18
--# , u_IBUF_HSTL_II
--# , u_IBUF_HSTL_II_18
--# , u_IBUF_HSTL_II_DCI
--# , u_IBUF_HSTL_II_DCI_18
--# , u_IBUF_HSTL_III
--# , u_IBUF_HSTL_III_18
--# , u_IBUF_HSTL_III_DCI
--# , u_IBUF_HSTL_III_DCI_18
--# , u_IBUF_LVCMOS12
--# , u_IBUF_LVCMOS15
--# , u_IBUF_LVCMOS18
--# , u_IBUF_LVCMOS25
--# , u_IBUF_LVCMOS33
--# , u_IBUF_LVDCI_15
--# , u_IBUF_LVDCI_18
--# , u_IBUF_LVDCI_DV2_15
--# , u_IBUF_LVDCI_DV2_18
--# , u_IBUF_LVDS
--# , u_IBUF_LVPECL
--# , u_IBUF_LVTTL
--# , u_IBUF_PCI33_3
--# , u_IBUF_PCI66_3
--# , u_IBUF_PCIX66_3
--# , u_IBUF_SSTL18_I
--# , u_IBUF_SSTL18_I_DCI
--# , u_IBUF_SSTL18_II
--# , u_IBUF_SSTL18_II_DCI
--# , u_ICAPE2
--# , u_IDDR
--# , u_IDDR_2CLK
--# , u_IDELAY
--# , u_IDELAYCTRL
--# , u_IDELAYE2
--# , u_IN_FIFO
--# , u_INV
--# , u_IOBUF
--# , u_IOBUFDS
--# , u_IOBUFDS_BLVDS_25
--# , u_IOBUFDS_DIFF_OUT
--# , u_IOBUFDS_DIFF_OUT_DCIEN
--# , u_IOBUF_F_12
--# , u_IOBUF_F_16
--# , u_IOBUF_F_2
--# , u_IOBUF_F_24
--# , u_IOBUF_F_4
--# , u_IOBUF_F_6
--# , u_IOBUF_F_8
--# , u_IOBUF_HSTL_I
--# , u_IOBUF_HSTL_I_18
--# , u_IOBUF_HSTL_II
--# , u_IOBUF_HSTL_II_18
--# , u_IOBUF_HSTL_II_DCI
--# , u_IOBUF_HSTL_II_DCI_18
--# , u_IOBUF_HSTL_III
--# , u_IOBUF_HSTL_III_18
--# , u_IOBUF_LVCMOS12
--# , u_IOBUF_LVCMOS15
--# , u_IOBUF_LVCMOS18
--# , u_IOBUF_LVCMOS25
--# , u_IOBUF_LVCMOS33
--# , u_IOBUF_LVDCI_15
--# , u_IOBUF_LVDCI_18
--# , u_IOBUF_LVDCI_DV2_15
--# , u_IOBUF_LVDCI_DV2_18
--# , u_IOBUF_LVDS
--# , u_IOBUF_LVPECL
--# , u_IOBUF_LVTTL
--# , u_IOBUF_PCI33_3
--# , u_IOBUF_PCI66_3
--# , u_IOBUF_PCIX66_3
--# , u_IOBUF_S_12
--# , u_IOBUF_S_16
--# , u_IOBUF_S_2
--# , u_IOBUF_S_24
--# , u_IOBUF_S_4
--# , u_IOBUF_S_6
--# , u_IOBUF_S_8
--# , u_IOBUF_SSTL18_I
--# , u_IOBUF_SSTL18_II
--# , u_IOBUF_SSTL18_II_DCI
--# , u_IODELAY
--# , u_IODELAYE1
--# , u_ISERDESE2
--# , u_JTAG_SIME2
--# , u_KEEPER
--# , u_LD
--# , u_LD_1
--# , u_LDC
--# , u_LDC_1
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCP_1
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDP_1
--# , u_LDPE
--# , u_LDPE_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_LUT5
--# , u_LUT5_D
--# , u_LUT5_L
--# , u_LUT6
--# , u_LUT6_2
--# , u_LUT6_D
--# , u_LUT6_L
--# , u_MMCME2_ADV
--# , u_MMCME2_BASE
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_MUXF7
--# , u_MUXF7_D
--# , u_MUXF7_L
--# , u_MUXF8
--# , u_MUXF8_D
--# , u_MUXF8_L
--# , u_NAND2
--# , u_NAND2B1
--# , u_NAND2B2
--# , u_NAND3
--# , u_NAND3B1
--# , u_NAND3B2
--# , u_NAND3B3
--# , u_NAND4
--# , u_NAND4B1
--# , u_NAND4B2
--# , u_NAND4B3
--# , u_NAND4B4
--# , u_NAND5
--# , u_NAND5B1
--# , u_NAND5B2
--# , u_NAND5B3
--# , u_NAND5B4
--# , u_NAND5B5
--# , u_NOR2
--# , u_NOR2B1
--# , u_NOR2B2
--# , u_NOR3
--# , u_NOR3B1
--# , u_NOR3B2
--# , u_NOR3B3
--# , u_NOR4
--# , u_NOR4B1
--# , u_NOR4B2
--# , u_NOR4B3
--# , u_NOR4B4
--# , u_NOR5
--# , u_NOR5B1
--# , u_NOR5B2
--# , u_NOR5B3
--# , u_NOR5B4
--# , u_NOR5B5
--# , u_OBUF
--# , u_OBUFDS
--# , u_OBUFDS_BLVDS_25
--# , u_OBUFDS_DUAL_BUF
--# , u_OBUFDS_LVDS_25
--# , u_OBUF_F_12
--# , u_OBUF_F_16
--# , u_OBUF_F_2
--# , u_OBUF_F_24
--# , u_OBUF_F_4
--# , u_OBUF_F_6
--# , u_OBUF_F_8
--# , u_OBUF_HSTL_I
--# , u_OBUF_HSTL_I_18
--# , u_OBUF_HSTL_I_DCI
--# , u_OBUF_HSTL_I_DCI_18
--# , u_OBUF_HSTL_II
--# , u_OBUF_HSTL_II_18
--# , u_OBUF_HSTL_II_DCI
--# , u_OBUF_HSTL_II_DCI_18
--# , u_OBUF_HSTL_III
--# , u_OBUF_HSTL_III_18
--# , u_OBUF_HSTL_III_DCI
--# , u_OBUF_HSTL_III_DCI_18
--# , u_OBUF_LVCMOS12
--# , u_OBUF_LVCMOS15
--# , u_OBUF_LVCMOS18
--# , u_OBUF_LVCMOS25
--# , u_OBUF_LVCMOS33
--# , u_OBUF_LVDCI_15
--# , u_OBUF_LVDCI_18
--# , u_OBUF_LVDCI_DV2_15
--# , u_OBUF_LVDCI_DV2_18
--# , u_OBUF_LVDS
--# , u_OBUF_LVPECL
--# , u_OBUF_LVTTL
--# , u_OBUF_PCI33_3
--# , u_OBUF_PCI66_3
--# , u_OBUF_PCIX66_3
--# , u_OBUF_S_12
--# , u_OBUF_S_16
--# , u_OBUF_S_2
--# , u_OBUF_S_24
--# , u_OBUF_S_4
--# , u_OBUF_S_6
--# , u_OBUF_S_8
--# , u_OBUF_SSTL18_I
--# , u_OBUF_SSTL18_I_DCI
--# , u_OBUF_SSTL18_II
--# , u_OBUF_SSTL18_II_DCI
--# , u_OBUFT
--# , u_OBUFT_DCIEN
--# , u_OBUFTDS
--# , u_OBUFTDS_BLVDS_25
--# , u_OBUFTDS_DCIEN
--# , u_OBUFTDS_DCIEN_DUAL_BUF
--# , u_OBUFTDS_DUAL_BUF
--# , u_OBUFTDS_LVDS_25
--# , u_OBUFT_F_12
--# , u_OBUFT_F_16
--# , u_OBUFT_F_2
--# , u_OBUFT_F_24
--# , u_OBUFT_F_4
--# , u_OBUFT_F_6
--# , u_OBUFT_F_8
--# , u_OBUFT_HSTL_I
--# , u_OBUFT_HSTL_I_18
--# , u_OBUFT_HSTL_I_DCI
--# , u_OBUFT_HSTL_I_DCI_18
--# , u_OBUFT_HSTL_II
--# , u_OBUFT_HSTL_II_18
--# , u_OBUFT_HSTL_II_DCI
--# , u_OBUFT_HSTL_II_DCI_18
--# , u_OBUFT_HSTL_III
--# , u_OBUFT_HSTL_III_18
--# , u_OBUFT_HSTL_III_DCI
--# , u_OBUFT_HSTL_III_DCI_18
--# , u_OBUFT_LVCMOS12
--# , u_OBUFT_LVCMOS15
--# , u_OBUFT_LVCMOS18
--# , u_OBUFT_LVCMOS25
--# , u_OBUFT_LVCMOS33
--# , u_OBUFT_LVDCI_15
--# , u_OBUFT_LVDCI_18
--# , u_OBUFT_LVDCI_DV2_15
--# , u_OBUFT_LVDCI_DV2_18
--# , u_OBUFT_LVDS
--# , u_OBUFT_LVPECL
--# , u_OBUFT_LVTTL
--# , u_OBUFT_PCI33_3
--# , u_OBUFT_PCI66_3
--# , u_OBUFT_PCIX66_3
--# , u_OBUFT_S_12
--# , u_OBUFT_S_16
--# , u_OBUFT_S_2
--# , u_OBUFT_S_24
--# , u_OBUFT_S_4
--# , u_OBUFT_S_6
--# , u_OBUFT_S_8
--# , u_OBUFT_SSTL18_I
--# , u_OBUFT_SSTL18_I_DCI
--# , u_OBUFT_SSTL18_II
--# , u_OBUFT_SSTL18_II_DCI
--# , u_ODDR
--# , u_ODELAYE2
--# , u_OR2
--# , u_OR2B1
--# , u_OR2B2
--# , u_OR2L
--# , u_OR3
--# , u_OR3B1
--# , u_OR3B2
--# , u_OR3B3
--# , u_OR4
--# , u_OR4B1
--# , u_OR4B2
--# , u_OR4B3
--# , u_OR4B4
--# , u_OR5
--# , u_OR5B1
--# , u_OR5B2
--# , u_OR5B3
--# , u_OR5B4
--# , u_OR5B5
--# , u_OSERDESE2
--# , u_OUT_FIFO
--# , u_PCIE_2_1
--# , u_PHASER_IN
--# , u_PHASER_IN_PHY
--# , u_PHASER_OUT
--# , u_PHASER_OUT_PHY
--# , u_PHASER_REF
--# , u_PHY_CONTROL
--# , u_PLLE2_ADV
--# , u_PLLE2_BASE
--# , u_PSS
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM128X1D
--# , u_RAM128X1S
--# , u_RAM128X1S_1
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM16X2S
--# , u_RAM16X4S
--# , u_RAM16X8S
--# , u_RAM256X1S
--# , u_RAM32M
--# , u_RAM32X1D
--# , u_RAM32X1D_1
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAM32X2S
--# , u_RAM32X4S
--# , u_RAM32X8S
--# , u_RAM64M
--# , u_RAM64X1D
--# , u_RAM64X1D_1
--# , u_RAM64X1S
--# , u_RAM64X1S_1
--# , u_RAM64X2S
--# , u_RAMB16_S4_S36
--# , u_RAMB18E1
--# , u_RAMB36E1
--# , u_RAMD32
--# , u_RAMD64E
--# , u_RAMS32
--# , u_RAMS64E
--# , u_ROM128X1
--# , u_ROM16X1
--# , u_ROM256X1
--# , u_ROM32X1
--# , u_ROM64X1
--# , u_SIM_CONFIGE2
--# , u_SRL16
--# , u_SRL16_1
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRLC16
--# , u_SRLC16_1
--# , u_SRLC16E
--# , u_SRLC16E_1
--# , u_SRLC32E
--# , u_STARTUPE2
--# , u_USR_ACCESSE2
--# , u_VCC
--# , u_XADC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XNOR5
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XOR5
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# , u_ZHOLD_DELAY
--# ) );
--# --
--# set_to(y, virtex7, (
--# u_AND2
--# , u_AND2B1
--# , u_AND2B1L
--# , u_AND2B2
--# , u_AND3
--# , u_AND3B1
--# , u_AND3B2
--# , u_AND3B3
--# , u_AND4
--# , u_AND4B1
--# , u_AND4B2
--# , u_AND4B3
--# , u_AND4B4
--# , u_AND5
--# , u_AND5B1
--# , u_AND5B2
--# , u_AND5B3
--# , u_AND5B4
--# , u_AND5B5
--# , u_AUTOBUF
--# , u_BSCANE2
--# , u_BUF
--# , u_BUFCF
--# , u_BUFG
--# , u_BUFGCE
--# , u_BUFGCE_1
--# , u_BUFGCTRL
--# , u_BUFGMUX
--# , u_BUFGMUX_1
--# , u_BUFGP
--# , u_BUFH
--# , u_BUFHCE
--# , u_BUFIO
--# , u_BUFMR
--# , u_BUFMRCE
--# , u_BUFR
--# , u_BUFT
--# , u_CAPTUREE2
--# , u_CARRY4
--# , u_CFG_IO_ACCESS
--# , u_CFGLUT5
--# , u_DCIRESET
--# , u_DNA_PORT
--# , u_DSP48E1
--# , u_EFUSE_USR
--# , u_FD
--# , u_FD_1
--# , u_FDC
--# , u_FDC_1
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCP_1
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDP_1
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDR
--# , u_FDR_1
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRS_1
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDS
--# , u_FDS_1
--# , u_FDSE
--# , u_FDSE_1
--# , u_FIFO18E1
--# , u_FIFO36E1
--# , u_FMAP
--# , u_FRAME_ECCE2
--# , u_GND
--# , u_GTXE2_CHANNEL
--# , u_GTXE2_COMMON
--# , u_IBUF
--# , u_IBUF_DCIEN
--# , u_IBUFDS
--# , u_IBUFDS_BLVDS_25
--# , u_IBUFDS_DCIEN
--# , u_IBUFDS_DIFF_OUT
--# , u_IBUFDS_DIFF_OUT_DCIEN
--# , u_IBUFDS_GTE2
--# , u_IBUFDS_LVDS_25
--# , u_IBUFG
--# , u_IBUFGDS
--# , u_IBUFGDS_BLVDS_25
--# , u_IBUFGDS_DIFF_OUT
--# , u_IBUFGDS_LVDS_25
--# , u_IBUFG_HSTL_I
--# , u_IBUFG_HSTL_I_18
--# , u_IBUFG_HSTL_I_DCI
--# , u_IBUFG_HSTL_I_DCI_18
--# , u_IBUFG_HSTL_II
--# , u_IBUFG_HSTL_II_18
--# , u_IBUFG_HSTL_II_DCI
--# , u_IBUFG_HSTL_II_DCI_18
--# , u_IBUFG_HSTL_III
--# , u_IBUFG_HSTL_III_18
--# , u_IBUFG_HSTL_III_DCI
--# , u_IBUFG_HSTL_III_DCI_18
--# , u_IBUFG_LVCMOS12
--# , u_IBUFG_LVCMOS15
--# , u_IBUFG_LVCMOS18
--# , u_IBUFG_LVCMOS25
--# , u_IBUFG_LVCMOS33
--# , u_IBUFG_LVDCI_15
--# , u_IBUFG_LVDCI_18
--# , u_IBUFG_LVDCI_DV2_15
--# , u_IBUFG_LVDCI_DV2_18
--# , u_IBUFG_LVDS
--# , u_IBUFG_LVPECL
--# , u_IBUFG_LVTTL
--# , u_IBUFG_PCI33_3
--# , u_IBUFG_PCI66_3
--# , u_IBUFG_PCIX66_3
--# , u_IBUFG_SSTL18_I
--# , u_IBUFG_SSTL18_I_DCI
--# , u_IBUFG_SSTL18_II
--# , u_IBUFG_SSTL18_II_DCI
--# , u_IBUF_HSTL_I
--# , u_IBUF_HSTL_I_18
--# , u_IBUF_HSTL_I_DCI
--# , u_IBUF_HSTL_I_DCI_18
--# , u_IBUF_HSTL_II
--# , u_IBUF_HSTL_II_18
--# , u_IBUF_HSTL_II_DCI
--# , u_IBUF_HSTL_II_DCI_18
--# , u_IBUF_HSTL_III
--# , u_IBUF_HSTL_III_18
--# , u_IBUF_HSTL_III_DCI
--# , u_IBUF_HSTL_III_DCI_18
--# , u_IBUF_LVCMOS12
--# , u_IBUF_LVCMOS15
--# , u_IBUF_LVCMOS18
--# , u_IBUF_LVCMOS25
--# , u_IBUF_LVCMOS33
--# , u_IBUF_LVDCI_15
--# , u_IBUF_LVDCI_18
--# , u_IBUF_LVDCI_DV2_15
--# , u_IBUF_LVDCI_DV2_18
--# , u_IBUF_LVDS
--# , u_IBUF_LVPECL
--# , u_IBUF_LVTTL
--# , u_IBUF_PCI33_3
--# , u_IBUF_PCI66_3
--# , u_IBUF_PCIX66_3
--# , u_IBUF_SSTL18_I
--# , u_IBUF_SSTL18_I_DCI
--# , u_IBUF_SSTL18_II
--# , u_IBUF_SSTL18_II_DCI
--# , u_ICAPE2
--# , u_IDDR
--# , u_IDDR_2CLK
--# , u_IDELAY
--# , u_IDELAYCTRL
--# , u_IDELAYE2
--# , u_IN_FIFO
--# , u_INV
--# , u_IOBUF
--# , u_IOBUFDS
--# , u_IOBUFDS_BLVDS_25
--# , u_IOBUFDS_DIFF_OUT
--# , u_IOBUFDS_DIFF_OUT_DCIEN
--# , u_IOBUF_F_12
--# , u_IOBUF_F_16
--# , u_IOBUF_F_2
--# , u_IOBUF_F_24
--# , u_IOBUF_F_4
--# , u_IOBUF_F_6
--# , u_IOBUF_F_8
--# , u_IOBUF_HSTL_I
--# , u_IOBUF_HSTL_I_18
--# , u_IOBUF_HSTL_II
--# , u_IOBUF_HSTL_II_18
--# , u_IOBUF_HSTL_II_DCI
--# , u_IOBUF_HSTL_II_DCI_18
--# , u_IOBUF_HSTL_III
--# , u_IOBUF_HSTL_III_18
--# , u_IOBUF_LVCMOS12
--# , u_IOBUF_LVCMOS15
--# , u_IOBUF_LVCMOS18
--# , u_IOBUF_LVCMOS25
--# , u_IOBUF_LVCMOS33
--# , u_IOBUF_LVDCI_15
--# , u_IOBUF_LVDCI_18
--# , u_IOBUF_LVDCI_DV2_15
--# , u_IOBUF_LVDCI_DV2_18
--# , u_IOBUF_LVDS
--# , u_IOBUF_LVPECL
--# , u_IOBUF_LVTTL
--# , u_IOBUF_PCI33_3
--# , u_IOBUF_PCI66_3
--# , u_IOBUF_PCIX66_3
--# , u_IOBUF_S_12
--# , u_IOBUF_S_16
--# , u_IOBUF_S_2
--# , u_IOBUF_S_24
--# , u_IOBUF_S_4
--# , u_IOBUF_S_6
--# , u_IOBUF_S_8
--# , u_IOBUF_SSTL18_I
--# , u_IOBUF_SSTL18_II
--# , u_IOBUF_SSTL18_II_DCI
--# , u_IODELAY
--# , u_IODELAYE1
--# , u_ISERDESE2
--# , u_JTAG_SIME2
--# , u_KEEPER
--# , u_LD
--# , u_LD_1
--# , u_LDC
--# , u_LDC_1
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCP_1
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDP_1
--# , u_LDPE
--# , u_LDPE_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_LUT5
--# , u_LUT5_D
--# , u_LUT5_L
--# , u_LUT6
--# , u_LUT6_2
--# , u_LUT6_D
--# , u_LUT6_L
--# , u_MMCME2_ADV
--# , u_MMCME2_BASE
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_MUXF7
--# , u_MUXF7_D
--# , u_MUXF7_L
--# , u_MUXF8
--# , u_MUXF8_D
--# , u_MUXF8_L
--# , u_NAND2
--# , u_NAND2B1
--# , u_NAND2B2
--# , u_NAND3
--# , u_NAND3B1
--# , u_NAND3B2
--# , u_NAND3B3
--# , u_NAND4
--# , u_NAND4B1
--# , u_NAND4B2
--# , u_NAND4B3
--# , u_NAND4B4
--# , u_NAND5
--# , u_NAND5B1
--# , u_NAND5B2
--# , u_NAND5B3
--# , u_NAND5B4
--# , u_NAND5B5
--# , u_NOR2
--# , u_NOR2B1
--# , u_NOR2B2
--# , u_NOR3
--# , u_NOR3B1
--# , u_NOR3B2
--# , u_NOR3B3
--# , u_NOR4
--# , u_NOR4B1
--# , u_NOR4B2
--# , u_NOR4B3
--# , u_NOR4B4
--# , u_NOR5
--# , u_NOR5B1
--# , u_NOR5B2
--# , u_NOR5B3
--# , u_NOR5B4
--# , u_NOR5B5
--# , u_OBUF
--# , u_OBUFDS
--# , u_OBUFDS_BLVDS_25
--# , u_OBUFDS_DUAL_BUF
--# , u_OBUFDS_LVDS_25
--# , u_OBUF_F_12
--# , u_OBUF_F_16
--# , u_OBUF_F_2
--# , u_OBUF_F_24
--# , u_OBUF_F_4
--# , u_OBUF_F_6
--# , u_OBUF_F_8
--# , u_OBUF_HSTL_I
--# , u_OBUF_HSTL_I_18
--# , u_OBUF_HSTL_I_DCI
--# , u_OBUF_HSTL_I_DCI_18
--# , u_OBUF_HSTL_II
--# , u_OBUF_HSTL_II_18
--# , u_OBUF_HSTL_II_DCI
--# , u_OBUF_HSTL_II_DCI_18
--# , u_OBUF_HSTL_III
--# , u_OBUF_HSTL_III_18
--# , u_OBUF_HSTL_III_DCI
--# , u_OBUF_HSTL_III_DCI_18
--# , u_OBUF_LVCMOS12
--# , u_OBUF_LVCMOS15
--# , u_OBUF_LVCMOS18
--# , u_OBUF_LVCMOS25
--# , u_OBUF_LVCMOS33
--# , u_OBUF_LVDCI_15
--# , u_OBUF_LVDCI_18
--# , u_OBUF_LVDCI_DV2_15
--# , u_OBUF_LVDCI_DV2_18
--# , u_OBUF_LVDS
--# , u_OBUF_LVPECL
--# , u_OBUF_LVTTL
--# , u_OBUF_PCI33_3
--# , u_OBUF_PCI66_3
--# , u_OBUF_PCIX66_3
--# , u_OBUF_S_12
--# , u_OBUF_S_16
--# , u_OBUF_S_2
--# , u_OBUF_S_24
--# , u_OBUF_S_4
--# , u_OBUF_S_6
--# , u_OBUF_S_8
--# , u_OBUF_SSTL18_I
--# , u_OBUF_SSTL18_I_DCI
--# , u_OBUF_SSTL18_II
--# , u_OBUF_SSTL18_II_DCI
--# , u_OBUFT
--# , u_OBUFT_DCIEN
--# , u_OBUFTDS
--# , u_OBUFTDS_BLVDS_25
--# , u_OBUFTDS_DCIEN
--# , u_OBUFTDS_DCIEN_DUAL_BUF
--# , u_OBUFTDS_DUAL_BUF
--# , u_OBUFTDS_LVDS_25
--# , u_OBUFT_F_12
--# , u_OBUFT_F_16
--# , u_OBUFT_F_2
--# , u_OBUFT_F_24
--# , u_OBUFT_F_4
--# , u_OBUFT_F_6
--# , u_OBUFT_F_8
--# , u_OBUFT_HSTL_I
--# , u_OBUFT_HSTL_I_18
--# , u_OBUFT_HSTL_I_DCI
--# , u_OBUFT_HSTL_I_DCI_18
--# , u_OBUFT_HSTL_II
--# , u_OBUFT_HSTL_II_18
--# , u_OBUFT_HSTL_II_DCI
--# , u_OBUFT_HSTL_II_DCI_18
--# , u_OBUFT_HSTL_III
--# , u_OBUFT_HSTL_III_18
--# , u_OBUFT_HSTL_III_DCI
--# , u_OBUFT_HSTL_III_DCI_18
--# , u_OBUFT_LVCMOS12
--# , u_OBUFT_LVCMOS15
--# , u_OBUFT_LVCMOS18
--# , u_OBUFT_LVCMOS25
--# , u_OBUFT_LVCMOS33
--# , u_OBUFT_LVDCI_15
--# , u_OBUFT_LVDCI_18
--# , u_OBUFT_LVDCI_DV2_15
--# , u_OBUFT_LVDCI_DV2_18
--# , u_OBUFT_LVDS
--# , u_OBUFT_LVPECL
--# , u_OBUFT_LVTTL
--# , u_OBUFT_PCI33_3
--# , u_OBUFT_PCI66_3
--# , u_OBUFT_PCIX66_3
--# , u_OBUFT_S_12
--# , u_OBUFT_S_16
--# , u_OBUFT_S_2
--# , u_OBUFT_S_24
--# , u_OBUFT_S_4
--# , u_OBUFT_S_6
--# , u_OBUFT_S_8
--# , u_OBUFT_SSTL18_I
--# , u_OBUFT_SSTL18_I_DCI
--# , u_OBUFT_SSTL18_II
--# , u_OBUFT_SSTL18_II_DCI
--# , u_ODDR
--# , u_ODELAYE2
--# , u_OR2
--# , u_OR2B1
--# , u_OR2B2
--# , u_OR2L
--# , u_OR3
--# , u_OR3B1
--# , u_OR3B2
--# , u_OR3B3
--# , u_OR4
--# , u_OR4B1
--# , u_OR4B2
--# , u_OR4B3
--# , u_OR4B4
--# , u_OR5
--# , u_OR5B1
--# , u_OR5B2
--# , u_OR5B3
--# , u_OR5B4
--# , u_OR5B5
--# , u_OSERDESE2
--# , u_OUT_FIFO
--# , u_PCIE_2_1
--# , u_PHASER_IN
--# , u_PHASER_IN_PHY
--# , u_PHASER_OUT
--# , u_PHASER_OUT_PHY
--# , u_PHASER_REF
--# , u_PHY_CONTROL
--# , u_PLLE2_ADV
--# , u_PLLE2_BASE
--# , u_PSS
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM128X1D
--# , u_RAM128X1S
--# , u_RAM128X1S_1
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM16X2S
--# , u_RAM16X4S
--# , u_RAM16X8S
--# , u_RAM256X1S
--# , u_RAM32M
--# , u_RAM32X1D
--# , u_RAM32X1D_1
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAM32X2S
--# , u_RAM32X4S
--# , u_RAM32X8S
--# , u_RAM64M
--# , u_RAM64X1D
--# , u_RAM64X1D_1
--# , u_RAM64X1S
--# , u_RAM64X1S_1
--# , u_RAM64X2S
--# , u_RAMB16_S4_S36
--# , u_RAMB36E1
--# , u_RAMB36E1
--# , u_RAMD32
--# , u_RAMD64E
--# , u_RAMS32
--# , u_RAMS64E
--# , u_ROM128X1
--# , u_ROM16X1
--# , u_ROM256X1
--# , u_ROM32X1
--# , u_ROM64X1
--# , u_SIM_CONFIGE2
--# , u_SRL16
--# , u_SRL16_1
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRLC16
--# , u_SRLC16_1
--# , u_SRLC16E
--# , u_SRLC16E_1
--# , u_SRLC32E
--# , u_STARTUPE2
--# , u_USR_ACCESSE2
--# , u_VCC
--# , u_XADC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XNOR5
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XOR5
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# , u_ZHOLD_DELAY
--# ) );
--# --
--# set_to(y, artix7, (
--# u_AND2
--# , u_AND2B1
--# , u_AND2B1L
--# , u_AND2B2
--# , u_AND3
--# , u_AND3B1
--# , u_AND3B2
--# , u_AND3B3
--# , u_AND4
--# , u_AND4B1
--# , u_AND4B2
--# , u_AND4B3
--# , u_AND4B4
--# , u_AND5
--# , u_AND5B1
--# , u_AND5B2
--# , u_AND5B3
--# , u_AND5B4
--# , u_AND5B5
--# , u_AUTOBUF
--# , u_BSCANE2
--# , u_BUF
--# , u_BUFCF
--# , u_BUFG
--# , u_BUFGCE
--# , u_BUFGCE_1
--# , u_BUFGCTRL
--# , u_BUFGMUX
--# , u_BUFGMUX_1
--# , u_BUFGP
--# , u_BUFH
--# , u_BUFHCE
--# , u_BUFIO
--# , u_BUFMR
--# , u_BUFMRCE
--# , u_BUFR
--# , u_BUFT
--# , u_CAPTUREE2
--# , u_CARRY4
--# , u_CFGLUT5
--# , u_DCIRESET
--# , u_DNA_PORT
--# , u_DSP48E1
--# , u_EFUSE_USR
--# , u_FD
--# , u_FD_1
--# , u_FDC
--# , u_FDC_1
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCP_1
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDP_1
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDR
--# , u_FDR_1
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRS_1
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDS
--# , u_FDS_1
--# , u_FDSE
--# , u_FDSE_1
--# , u_FIFO18E1
--# , u_FIFO36E1
--# , u_FMAP
--# , u_FRAME_ECCE2
--# , u_GND
--# , u_IBUF
--# , u_IBUF_DCIEN
--# , u_IBUFDS
--# , u_IBUFDS_DCIEN
--# , u_IBUFDS_DIFF_OUT
--# , u_IBUFDS_DIFF_OUT_DCIEN
--# , u_IBUFDS_GTE2
--# , u_IBUFG
--# , u_IBUFGDS
--# , u_IBUFGDS_DIFF_OUT
--# , u_IBUFG_LVDS
--# , u_IBUFG_LVPECL
--# , u_IBUFG_PCIX66_3
--# , u_IBUF_LVDS
--# , u_IBUF_LVPECL
--# , u_IBUF_PCIX66_3
--# , u_ICAPE2
--# , u_IDDR
--# , u_IDDR_2CLK
--# , u_IDELAY
--# , u_IDELAYCTRL
--# , u_IDELAYE2
--# , u_IN_FIFO
--# , u_INV
--# , u_IOBUF
--# , u_IOBUFDS
--# , u_IOBUFDS_DIFF_OUT
--# , u_IOBUFDS_DIFF_OUT_DCIEN
--# , u_IOBUF_F_12
--# , u_IOBUF_F_16
--# , u_IOBUF_F_2
--# , u_IOBUF_F_24
--# , u_IOBUF_F_4
--# , u_IOBUF_F_6
--# , u_IOBUF_F_8
--# , u_IOBUF_LVDS
--# , u_IOBUF_LVPECL
--# , u_IOBUF_PCIX66_3
--# , u_IOBUF_S_12
--# , u_IOBUF_S_16
--# , u_IOBUF_S_2
--# , u_IOBUF_S_24
--# , u_IOBUF_S_4
--# , u_IOBUF_S_6
--# , u_IOBUF_S_8
--# , u_IODELAY
--# , u_IODELAYE1
--# , u_ISERDESE2
--# , u_JTAG_SIME2
--# , u_KEEPER
--# , u_LD
--# , u_LD_1
--# , u_LDC
--# , u_LDC_1
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCP_1
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDP_1
--# , u_LDPE
--# , u_LDPE_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_LUT5
--# , u_LUT5_D
--# , u_LUT5_L
--# , u_LUT6
--# , u_LUT6_2
--# , u_LUT6_D
--# , u_LUT6_L
--# , u_MMCME2_ADV
--# , u_MMCME2_BASE
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_MUXF7
--# , u_MUXF7_D
--# , u_MUXF7_L
--# , u_MUXF8
--# , u_MUXF8_D
--# , u_MUXF8_L
--# , u_NAND2
--# , u_NAND2B1
--# , u_NAND2B2
--# , u_NAND3
--# , u_NAND3B1
--# , u_NAND3B2
--# , u_NAND3B3
--# , u_NAND4
--# , u_NAND4B1
--# , u_NAND4B2
--# , u_NAND4B3
--# , u_NAND4B4
--# , u_NAND5
--# , u_NAND5B1
--# , u_NAND5B2
--# , u_NAND5B3
--# , u_NAND5B4
--# , u_NAND5B5
--# , u_NOR2
--# , u_NOR2B1
--# , u_NOR2B2
--# , u_NOR3
--# , u_NOR3B1
--# , u_NOR3B2
--# , u_NOR3B3
--# , u_NOR4
--# , u_NOR4B1
--# , u_NOR4B2
--# , u_NOR4B3
--# , u_NOR4B4
--# , u_NOR5
--# , u_NOR5B1
--# , u_NOR5B2
--# , u_NOR5B3
--# , u_NOR5B4
--# , u_NOR5B5
--# , u_OBUF
--# , u_OBUFDS
--# , u_OBUFDS_DUAL_BUF
--# , u_OBUF_F_12
--# , u_OBUF_F_16
--# , u_OBUF_F_2
--# , u_OBUF_F_24
--# , u_OBUF_F_4
--# , u_OBUF_F_6
--# , u_OBUF_F_8
--# , u_OBUF_LVDS
--# , u_OBUF_LVPECL
--# , u_OBUF_PCIX66_3
--# , u_OBUF_S_12
--# , u_OBUF_S_16
--# , u_OBUF_S_2
--# , u_OBUF_S_24
--# , u_OBUF_S_4
--# , u_OBUF_S_6
--# , u_OBUF_S_8
--# , u_OBUFT
--# , u_OBUFT_DCIEN
--# , u_OBUFTDS
--# , u_OBUFTDS_DCIEN
--# , u_OBUFTDS_DCIEN_DUAL_BUF
--# , u_OBUFTDS_DUAL_BUF
--# , u_OBUFT_F_12
--# , u_OBUFT_F_16
--# , u_OBUFT_F_2
--# , u_OBUFT_F_24
--# , u_OBUFT_F_4
--# , u_OBUFT_F_6
--# , u_OBUFT_F_8
--# , u_OBUFT_LVDS
--# , u_OBUFT_LVPECL
--# , u_OBUFT_PCIX66_3
--# , u_OBUFT_S_12
--# , u_OBUFT_S_16
--# , u_OBUFT_S_2
--# , u_OBUFT_S_24
--# , u_OBUFT_S_4
--# , u_OBUFT_S_6
--# , u_OBUFT_S_8
--# , u_ODDR
--# , u_ODELAYE2
--# , u_OR2
--# , u_OR2B1
--# , u_OR2B2
--# , u_OR2L
--# , u_OR3
--# , u_OR3B1
--# , u_OR3B2
--# , u_OR3B3
--# , u_OR4
--# , u_OR4B1
--# , u_OR4B2
--# , u_OR4B3
--# , u_OR4B4
--# , u_OR5
--# , u_OR5B1
--# , u_OR5B2
--# , u_OR5B3
--# , u_OR5B4
--# , u_OR5B5
--# , u_OSERDESE2
--# , u_OUT_FIFO
--# , u_PCIE_2_1
--# , u_PHASER_IN
--# , u_PHASER_IN_PHY
--# , u_PHASER_OUT
--# , u_PHASER_OUT_PHY
--# , u_PHASER_REF
--# , u_PHY_CONTROL
--# , u_PLLE2_ADV
--# , u_PLLE2_BASE
--# , u_PSS
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM128X1D
--# , u_RAM128X1S
--# , u_RAM128X1S_1
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM16X2S
--# , u_RAM16X4S
--# , u_RAM16X8S
--# , u_RAM256X1S
--# , u_RAM32M
--# , u_RAM32X1D
--# , u_RAM32X1D_1
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAM32X2S
--# , u_RAM32X4S
--# , u_RAM32X8S
--# , u_RAM64M
--# , u_RAM64X1D
--# , u_RAM64X1D_1
--# , u_RAM64X1S
--# , u_RAM64X1S_1
--# , u_RAM64X2S
--# , u_RAMB16_S4_S36
--# , u_RAMB18E1
--# , u_RAMB36E1
--# , u_RAMD32
--# , u_RAMD64E
--# , u_RAMS32
--# , u_RAMS64E
--# , u_ROM128X1
--# , u_ROM16X1
--# , u_ROM256X1
--# , u_ROM32X1
--# , u_ROM64X1
--# , u_SIM_CONFIGE2
--# , u_SRL16
--# , u_SRL16_1
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRLC16
--# , u_SRLC16_1
--# , u_SRLC16E
--# , u_SRLC16E_1
--# , u_SRLC32E
--# , u_STARTUPE2
--# , u_USR_ACCESSE2
--# , u_VCC
--# , u_XADC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XNOR5
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XOR5
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# , u_ZHOLD_DELAY
--# ) );
--# --
--# return pp;
--# end prim_population;
--# ---)
--#
--#constant fam_has_prim : fam_has_prim_type := prim_population;
constant fam_has_prim : fam_has_prim_type :=
(
nofamily => (
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
virtex => (
y, n, y, y, n, n, n, n, n, n, y, n, n, n, n, y, y, y, y, n, n, n, y, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, y, n, n, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, n, n, n, n, y, y, y, n, n, y, y, y, y, y, n, y, n, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, y, n, n, y, y, y, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, n, y, n, n, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, n, y, n, n, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, n, y, n, n, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, y, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
spartan2 => (
y, n, y, y, n, y, n, n, n, n, n, n, n, n, n, y, y, y, y, n, n, n, y, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, n, n, n, n, y, y, y, n, n, y, y, y, y, y, n, y, n, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, y, n, n, y, y, y, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, n, y, n, n, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, n, y, n, n, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, n, y, n, n, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, y, n, n, n, y, y, y, y, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
spartan2e => (
y, n, y, y, n, y, n, n, n, n, n, n, n, n, n, y, y, y, y, n, n, n, y, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, n, n, n, n, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, y, n, n, n, y, y, y, y, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
virtexe => (
y, n, y, y, n, n, n, n, n, n, y, n, n, n, n, y, y, y, y, n, n, n, y, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, y, n, n, n, n, n, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, y, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
virtex2 => (
y, n, y, y, n, n, n, n, n, n, n, y, n, n, n, y, y, y, y, y, y, n, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, n, y, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, n, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
qvirtex2 => (
y, n, y, y, n, n, n, n, n, n, n, y, n, n, n, y, y, y, y, y, y, n, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, n, y, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, n, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
qrvirtex2 => (
y, n, y, y, n, n, n, n, n, n, n, y, n, n, n, y, y, y, y, y, y, n, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, n, y, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, n, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
virtex2p => (
y, n, y, y, n, n, n, n, n, n, n, y, n, n, n, y, y, y, y, y, y, n, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, n, y, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, y, n, n, y, y, n, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, n, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
spartan3 => (
y, n, y, y, n, n, y, n, n, n, n, n, n, n, n, y, y, n, y, y, y, n, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, n, n, n, n, n, y, y, y, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
aspartan3 => (
y, n, y, y, n, n, y, n, n, n, n, n, n, n, n, y, y, n, y, y, y, n, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, n, n, n, n, n, y, y, y, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
virtex4 => (
y, n, y, y, n, n, n, n, n, n, n, n, y, n, n, y, y, n, y, y, y, y, n, y, y, n, y, y, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, y, y, y, y, n, y, n, y, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, y, y, n, n, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, y, n, y, y, n, y, n, n, n, n, n, n, y, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, n, n, n, n, y, y, y, y, y, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
virtex4lx => (
y, n, y, y, n, n, n, n, n, n, n, n, y, n, n, y, y, n, y, y, y, y, n, y, y, n, y, y, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, y, y, y, y, n, y, n, y, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, y, y, n, n, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, y, n, y, y, n, y, n, n, n, n, n, n, y, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, n, n, n, n, y, y, y, y, y, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
virtex4fx => (
y, n, y, y, n, n, n, n, n, n, n, n, y, n, n, y, y, n, y, y, y, y, n, y, y, n, y, y, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, y, y, y, y, n, y, n, y, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, y, y, n, n, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, y, n, y, y, n, y, n, n, n, n, n, n, y, n, y, y, n, y, y, n, n, n, y, y, y, y, y, y, y, n, n, n, n, y, y, y, y, y, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
virtex4sx => (
y, n, y, y, n, n, n, n, n, n, n, n, y, n, n, y, y, n, y, y, y, y, n, y, y, n, y, y, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, y, y, y, y, n, y, n, y, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, y, y, n, n, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, y, n, y, y, n, y, n, n, n, n, n, n, y, n, y, y, n, y, y, n, n, n, y, y, y, y, y, y, y, n, n, n, n, y, y, y, y, y, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
spartan3e => (
y, n, y, y, n, n, y, n, n, n, n, n, n, n, n, y, y, n, y, y, y, n, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, n, n, n, n, n, y, y, y, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, n, y, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
virtex5 => (
y, n, y, y, n, n, n, n, n, n, n, n, n, y, n, y, y, n, y, y, y, y, n, y, y, y, n, y, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, y, n, y, y, n, n, n, y, y, y, y, y, y, n, y, n, y, n, n, y, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, n, y, n, y, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, n, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, n, y, y, n, y, n, n, n, n, y, y, y, n, n, n, n, y, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, n, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, y, y, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
spartan3a => (
y, n, y, y, n, n, n, y, n, n, n, n, n, n, n, y, y, n, y, y, y, n, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, y, y, y, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, y, n, n, n, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, n, n, n, n, n, y, y, y, n, n, n, n, n, y, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
spartan3an => (
y, n, y, y, n, n, n, y, n, n, n, n, n, n, n, y, y, n, y, y, y, n, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, y, y, y, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, y, n, n, n, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, n, n, n, n, n, y, y, y, n, n, n, n, n, y, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
spartan3adsp => (
y, n, y, y, n, n, n, y, n, n, n, n, n, n, n, y, y, n, y, y, y, n, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, y, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, y, y, y, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, y, n, n, n, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, n, n, n, n, n, y, y, y, n, n, n, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
aspartan3e => (
y, n, y, y, n, n, y, n, n, n, n, n, n, n, n, y, y, n, y, y, y, n, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, n, n, n, n, n, y, y, y, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, n, y, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
aspartan3a => (
y, n, y, y, n, n, n, y, n, n, n, n, n, n, n, y, y, n, y, y, y, n, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, y, y, y, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, y, n, n, n, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, n, n, n, n, n, y, y, y, n, n, n, n, n, y, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
aspartan3adsp => (
y, n, y, y, n, n, n, y, n, n, n, n, n, n, n, y, y, n, y, y, y, n, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, y, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, y, y, y, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, y, n, n, n, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, n, n, n, n, n, y, y, y, n, n, n, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
qvirtex4 => (
y, n, y, y, n, n, n, n, n, n, n, n, y, n, n, y, y, n, y, y, y, y, n, y, y, n, y, y, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, y, y, y, y, n, y, n, y, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, y, y, n, n, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, y, n, y, y, n, y, n, n, n, n, n, n, y, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, n, n, n, n, y, y, y, y, y, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
qrvirtex4 => (
y, n, y, y, n, n, n, n, n, n, n, n, y, n, n, y, y, n, y, y, y, y, n, y, y, n, y, y, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, y, y, y, y, n, y, n, y, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, y, y, n, n, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, y, n, y, y, n, y, n, n, n, n, n, n, y, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, n, n, n, n, y, y, y, y, y, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
spartan6 => (
y, y, y, y, y, n, n, n, n, y, n, n, n, n, n, y, y, n, y, y, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, n, y, y, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, y, y, n, n, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, y, n, n, y, y, y, y, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, n, n, y, n, n, n, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, n, y, n, n, n, y, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, y, n, n, y, y, n, n, y, n, n, n, y, y, n, n, n, y, y, y, y, y, y, n, n, n, n, n, y, y, y, n, n, n, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, y, n, y, n, n, n, n, n, y, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
virtex6 => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, n, y, y, y, y, n, y, y, y, n, y, y, y, y, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, y, y, y, y, n, n, n, y, y, y, y, y, y, n, y, n, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, n, y, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, y, y, y, y, y, y, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, n, n, y, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, n, y, n, y, y, n, y, y, y, n, n, n, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, n, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
spartan6l => (
y, y, y, y, y, n, n, n, n, y, n, n, n, n, n, y, y, n, y, y, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, n, y, y, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, y, y, n, n, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, y, n, n, y, y, y, y, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, n, n, y, n, n, n, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, n, y, n, n, n, y, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, y, n, n, y, y, n, n, y, n, n, n, y, y, n, n, n, y, y, y, y, y, y, n, n, n, n, n, y, y, y, n, n, n, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, y, n, y, n, n, n, n, n, y, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
qspartan6 => (
y, y, y, y, y, n, n, n, n, y, n, n, n, n, n, y, y, n, y, y, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, n, y, y, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, y, y, n, n, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, y, n, n, y, y, y, y, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, n, n, y, n, n, n, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, n, y, n, n, n, y, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, y, n, n, y, y, n, n, y, n, n, n, y, y, n, n, n, y, y, y, y, y, y, n, n, n, n, n, y, y, y, n, n, n, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, y, n, y, n, n, n, n, n, y, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
aspartan6 => (
y, y, y, y, y, n, n, n, n, y, n, n, n, n, n, y, y, n, y, y, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, n, y, y, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, y, y, n, n, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, y, n, n, y, y, y, y, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, n, n, y, n, n, n, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, n, y, n, n, n, y, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, y, n, n, y, y, n, n, y, n, n, n, y, y, n, n, n, y, y, y, y, y, y, n, n, n, n, n, y, y, y, n, n, n, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, y, n, y, n, n, n, n, n, y, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
virtex6l => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, n, y, y, y, y, n, y, y, y, n, y, y, y, y, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, y, y, y, y, n, n, n, y, y, y, y, y, y, n, y, n, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, n, y, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, y, y, y, y, y, y, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, n, n, y, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, n, y, n, y, y, n, y, y, y, n, n, n, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, n, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
qspartan6l => (
y, y, y, y, y, n, n, n, n, y, n, n, n, n, n, y, y, n, y, y, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, n, y, y, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, y, y, n, n, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, y, n, n, y, y, y, y, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, n, n, y, n, n, n, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, n, y, n, n, n, y, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, y, n, n, y, y, n, n, y, n, n, n, y, y, n, n, n, y, y, y, y, y, y, n, n, n, n, n, y, y, y, n, n, n, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, y, n, y, n, n, n, n, n, y, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
qvirtex5 => (
y, n, y, y, n, n, n, n, n, n, n, n, n, y, n, y, y, n, y, y, y, y, n, y, y, y, n, y, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, y, n, y, y, n, n, n, y, y, y, y, y, y, n, y, n, y, n, n, y, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, n, y, n, y, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, n, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, n, y, y, n, y, n, n, n, n, y, y, y, n, n, n, n, y, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, n, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, y, y, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
qvirtex6 => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, n, y, y, y, y, n, y, y, y, n, y, y, y, y, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, y, y, y, y, n, n, n, y, y, y, y, y, y, n, y, n, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, n, y, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, y, y, y, y, y, y, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, n, n, y, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, n, y, n, y, y, n, y, y, y, n, n, n, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, n, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
qrvirtex5 => (
y, n, y, y, n, n, n, n, n, n, n, n, n, y, n, y, y, n, y, y, y, y, n, y, y, y, n, y, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, y, n, y, y, n, n, n, y, y, y, y, y, y, n, y, n, y, n, n, y, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, n, y, n, y, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, n, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, n, y, y, n, y, n, n, n, n, y, y, y, n, n, n, n, y, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, n, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, y, y, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
virtex5tx => (
y, n, y, y, n, n, n, n, n, n, n, n, n, y, n, y, y, n, y, y, y, y, n, y, y, y, n, y, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, y, n, y, y, n, n, n, y, y, y, y, y, y, n, y, n, y, n, n, y, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, n, y, n, y, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, n, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, n, y, y, n, y, n, n, n, n, y, y, y, n, n, n, n, y, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, n, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, y, y, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
virtex5fx => (
y, n, y, y, n, n, n, n, n, n, n, n, n, y, n, y, y, n, y, y, y, y, n, y, y, y, n, y, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, y, n, y, y, n, n, n, y, y, y, y, y, y, n, y, n, y, n, n, y, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, n, y, n, y, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, n, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, n, y, y, n, y, n, n, n, n, y, y, y, n, n, n, n, y, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, n, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, y, y, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
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virtex6cx => (
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n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
kintex7 => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y, y, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, n, n, n, n, n, n, y, y, n, y, n, y, y, y, n, y, y, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, y, n, n, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y),
kintex7l => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y, y, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, n, n, n, n, n, n, y, y, n, y, n, y, y, y, n, y, y, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, y, n, n, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y),
qkintex7 => (
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y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y),
qkintex7l => (
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artix7 => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y, y, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, n, n, n, n, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, y, n, n, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, n, n, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, y, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y),
aartix7 => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y, y, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, n, n, n, n, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, y, n, n, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, n, n, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, y, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y),
artix7l => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y, y, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, n, n, n, n, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, y, n, n, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, n, n, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, y, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y),
qartix7 => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y, y, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, n, n, n, n, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, y, n, n, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, n, n, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, y, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y),
qartix7l => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y, y, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, n, n, n, n, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, y, n, n, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, n, n, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, y, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y),
zynq => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y, y, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, n, n, n, n, n, n, y, y, n, y, n, y, y, y, n, y, y, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, y, n, n, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y),
azynq => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y, y, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, n, n, n, n, n, n, y, y, n, y, n, y, y, y, n, y, y, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, y, n, n, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y),
qzynq => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y, y, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, n, n, n, n, n, n, y, y, n, y, n, y, y, y, n, y, y, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, y, n, n, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y)
);
function supported( family : families_type;
primitive : primitives_type
) return boolean is
begin
return fam_has_prim(family)(primitive) = y;
end supported;
function supported( family : families_type;
primitives : primitive_array_type
) return boolean is
begin
for i in primitives'range loop
if fam_has_prim(family)(primitives(i)) /= y then
return false;
end if;
end loop;
return true;
end supported;
----------------------------------------------------------------------------
-- This function is used as alternative to the 'IMAGE attribute, which
-- is not correctly interpretted by some vhdl tools.
----------------------------------------------------------------------------
function myimage (fam_type : families_type) return string is
variable temp : families_type :=fam_type;
begin
case temp is
when nofamily => return "nofamily" ;
when virtex => return "virtex" ;
when spartan2 => return "spartan2" ;
when spartan2e => return "spartan2e" ;
when virtexe => return "virtexe" ;
when virtex2 => return "virtex2" ;
when qvirtex2 => return "qvirtex2" ;
when qrvirtex2 => return "qrvirtex2" ;
when virtex2p => return "virtex2p" ;
when spartan3 => return "spartan3" ;
when aspartan3 => return "aspartan3" ;
when spartan3e => return "spartan3e" ;
when virtex4 => return "virtex4" ;
when virtex4lx => return "virtex4lx" ;
when virtex4fx => return "virtex4fx" ;
when virtex4sx => return "virtex4sx" ;
when virtex5 => return "virtex5" ;
when spartan3a => return "spartan3a" ;
when spartan3an => return "spartan3an" ;
when spartan3adsp => return "spartan3adsp" ;
when aspartan3e => return "aspartan3e" ;
when aspartan3a => return "aspartan3a" ;
when aspartan3adsp => return "aspartan3adsp";
when qvirtex4 => return "qvirtex4" ;
when qrvirtex4 => return "qrvirtex4" ;
when spartan6 => return "spartan6" ;
when virtex6 => return "virtex6" ;
when spartan6l => return "spartan6l" ;
when qspartan6 => return "qspartan6" ;
when aspartan6 => return "aspartan6" ;
when virtex6l => return "virtex6l" ;
when qspartan6l => return "qspartan6l" ;
when qvirtex5 => return "qvirtex5" ;
when qvirtex6 => return "qvirtex6" ;
when qrvirtex5 => return "qrvirtex5" ;
when virtex5tx => return "virtex5tx" ;
when virtex5fx => return "virtex5fx" ;
when virtex6cx => return "virtex6cx" ;
when virtex7 => return "virtex7" ;
when virtex7l => return "virtex7l" ;
when qvirtex7 => return "qvirtex7" ;
when qvirtex7l => return "qvirtex7l" ;
when kintex7 => return "kintex7" ;
when kintex7l => return "kintex7l" ;
when qkintex7 => return "qkintex7" ;
when qkintex7l => return "qkintex7l" ;
when artix7 => return "artix7" ;
when aartix7 => return "aartix7" ;
when artix7l => return "artix7l" ;
when qartix7 => return "qartix7" ;
when qartix7l => return "qartix7l" ;
when zynq => return "zynq" ;
when azynq => return "azynq" ;
when qzynq => return "qzynq" ;
end case;
end myimage;
----------------------------------------------------------------------------
-- Function: get_root_family
--
-- This function takes in the string for the desired FPGA family type and
-- returns the root FPGA family type string. This is used for derivative part
-- aliasing to the root family. This is primarily for fifo_generator and
-- blk_mem_gen calls that need the root family passed to the call.
----------------------------------------------------------------------------
function get_root_family(family_in : string) return string is
begin
-- spartan3 Root family
if (equalIgnoringCase(family_in, "spartan3" )) Then return "spartan3" ;
Elsif (equalIgnoringCase(family_in, "spartan3a" )) Then return "spartan3" ;
Elsif (equalIgnoringCase(family_in, "spartan3an" )) Then return "spartan3" ;
Elsif (equalIgnoringCase(family_in, "spartan3adsp" )) Then return "spartan3" ;
Elsif (equalIgnoringCase(family_in, "aspartan3" )) Then return "spartan3" ;
Elsif (equalIgnoringCase(family_in, "aspartan3a" )) Then return "spartan3" ;
Elsif (equalIgnoringCase(family_in, "aspartan3adsp" )) Then return "spartan3" ;
Elsif (equalIgnoringCase(family_in, "spartan3e" )) Then return "spartan3" ;
Elsif (equalIgnoringCase(family_in, "aspartan3e" )) Then return "spartan3" ;
-- virtex4 Root family
Elsif (equalIgnoringCase(family_in, "virtex4" )) Then return "virtex4" ;
Elsif (equalIgnoringCase(family_in, "virtex4lx" )) Then return "virtex4" ;
Elsif (equalIgnoringCase(family_in, "virtex4fx" )) Then return "virtex4" ;
Elsif (equalIgnoringCase(family_in, "virtex4sx" )) Then return "virtex4" ;
Elsif (equalIgnoringCase(family_in, "qvirtex4" )) Then return "virtex4" ;
Elsif (equalIgnoringCase(family_in, "qrvirtex4" )) Then return "virtex4" ;
-- virtex5 Root family
Elsif (equalIgnoringCase(family_in, "virtex5" )) Then return "virtex5" ;
Elsif (equalIgnoringCase(family_in, "qvirtex5" )) Then return "virtex5" ;
Elsif (equalIgnoringCase(family_in, "qrvirtex5" )) Then return "virtex5" ;
Elsif (equalIgnoringCase(family_in, "virtex5tx" )) Then return "virtex5" ;
Elsif (equalIgnoringCase(family_in, "virtex5fx" )) Then return "virtex5" ;
-- virtex6 Root family
Elsif (equalIgnoringCase(family_in, "virtex6" )) Then return "virtex6" ;
Elsif (equalIgnoringCase(family_in, "virtex6l" )) Then return "virtex6" ;
Elsif (equalIgnoringCase(family_in, "qvirtex6" )) Then return "virtex6" ;
Elsif (equalIgnoringCase(family_in, "virtex6cx" )) Then return "virtex6" ;
-- spartan6 Root family
Elsif (equalIgnoringCase(family_in, "spartan6" )) Then return "spartan6" ;
Elsif (equalIgnoringCase(family_in, "spartan6l" )) Then return "spartan6" ;
Elsif (equalIgnoringCase(family_in, "qspartan6" )) Then return "spartan6" ;
Elsif (equalIgnoringCase(family_in, "aspartan6" )) Then return "spartan6" ;
Elsif (equalIgnoringCase(family_in, "qspartan6l" )) Then return "spartan6" ;
-- Virtex7 Root family
Elsif (equalIgnoringCase(family_in, "virtex7" )) Then return "virtex7" ;
Elsif (equalIgnoringCase(family_in, "virtex7l" )) Then return "virtex7" ;
Elsif (equalIgnoringCase(family_in, "qvirtex7" )) Then return "virtex7" ;
Elsif (equalIgnoringCase(family_in, "qvirtex7l" )) Then return "virtex7" ;
-- Kintex7 Root family
Elsif (equalIgnoringCase(family_in, "kintex7" )) Then return "kintex7" ;
Elsif (equalIgnoringCase(family_in, "kintex7l" )) Then return "kintex7" ;
Elsif (equalIgnoringCase(family_in, "qkintex7" )) Then return "kintex7" ;
Elsif (equalIgnoringCase(family_in, "qkintex7l" )) Then return "kintex7" ;
-- artix7 Root family
Elsif (equalIgnoringCase(family_in, "artix7" )) Then return "artix7" ;
Elsif (equalIgnoringCase(family_in, "aartix7" )) Then return "artix7" ;
Elsif (equalIgnoringCase(family_in, "artix7l" )) Then return "artix7" ;
Elsif (equalIgnoringCase(family_in, "qartix7" )) Then return "artix7" ;
Elsif (equalIgnoringCase(family_in, "qartix7l" )) Then return "artix7" ;
-- zynq Root family
Elsif (equalIgnoringCase(family_in, "zynq" )) Then return "zynq" ;
Elsif (equalIgnoringCase(family_in, "azynq" )) Then return "zynq" ;
Elsif (equalIgnoringCase(family_in, "qzynq" )) Then return "zynq" ;
-- No Match to supported families and derivatives
Else return "nofamily";
End if;
end get_root_family;
function toLowerCaseChar( char : character ) return character is
begin
-- If char is not an upper case letter then return char
if char < 'A' OR char > 'Z' then
return char;
end if;
-- Otherwise map char to its corresponding lower case character and
-- return that
case char is
when 'A' => return 'a';
when 'B' => return 'b';
when 'C' => return 'c';
when 'D' => return 'd';
when 'E' => return 'e';
when 'F' => return 'f';
when 'G' => return 'g';
when 'H' => return 'h';
when 'I' => return 'i';
when 'J' => return 'j';
when 'K' => return 'k';
when 'L' => return 'l';
when 'M' => return 'm';
when 'N' => return 'n';
when 'O' => return 'o';
when 'P' => return 'p';
when 'Q' => return 'q';
when 'R' => return 'r';
when 'S' => return 's';
when 'T' => return 't';
when 'U' => return 'u';
when 'V' => return 'v';
when 'W' => return 'w';
when 'X' => return 'x';
when 'Y' => return 'y';
when 'Z' => return 'z';
when others => return char;
end case;
end toLowerCaseChar;
----------------------------------------------------------------------------
-- Function: equalIgnoringCase
--
-- Compare one string against another for equality with case insensitivity.
-- Can be used to test see if a family, C_FAMILY, is equal to some
-- family. However such usage is discouraged. Use instead availability
-- primitive guards based on the function, 'supported', wherever possible.
----------------------------------------------------------------------------
function equalIgnoringCase( str1, str2 : string ) return boolean is
constant LEN1 : integer := str1'length;
constant LEN2 : integer := str2'length;
variable equal : boolean := TRUE;
begin
if not (LEN1 = LEN2) then
equal := FALSE;
else
for i in str1'range loop
if not (toLowerCaseChar(str1(i)) = toLowerCaseChar(str2(i))) then
equal := FALSE;
end if;
end loop;
end if;
return equal;
end equalIgnoringCase;
----------------------------------------------------------------------------
-- Conversions from/to STRING to/from families_type.
-- These are convenience functions that are not normally needed when
-- using the 'supported' functions.
----------------------------------------------------------------------------
function str2fam( fam_as_string : string ) return families_type is
--
variable fas : string(1 to fam_as_string'length) := fam_as_string;
variable fam : families_type;
--
begin
-- Search for and return the corresponding family.
for fam in families_type'low to families_type'high loop
if equalIgnoringCase(fas, myimage(fam)) then return fam; end if;
end loop;
-- If there is no matching family, report a warning and return nofamily.
assert false
report "Package family_support: Function str2fam called" &
" with string parameter, " & fam_as_string &
", that does not correspond" &
" to a supported family. Returning nofamily."
severity warning;
return nofamily;
end str2fam;
function fam2str( fam : families_type) return string is
begin
--return families_type'IMAGE(fam);
return myimage(fam);
end fam2str;
function supported( fam_as_str : string;
primitive : primitives_type
) return boolean is
begin
return supported(str2fam(fam_as_str), primitive);
end supported;
function supported( fam_as_str : string;
primitives : primitive_array_type
) return boolean is
begin
return supported(str2fam(fam_as_str), primitives);
end supported;
----------------------------------------------------------------------------
-- Function: native_lut_size, two overloads.
----------------------------------------------------------------------------
function native_lut_size( fam : families_type;
no_lut_return_val : natural := 0
) return natural is
begin
if supported(fam, u_LUT6) then return 6;
elsif supported(fam, u_LUT5) then return 5;
elsif supported(fam, u_LUT4) then return 4;
elsif supported(fam, u_LUT3) then return 3;
elsif supported(fam, u_LUT2) then return 2;
elsif supported(fam, u_LUT1) then return 1;
else return no_lut_return_val;
end if;
end;
function native_lut_size( fam_as_string : string;
no_lut_return_val : natural := 0
) return natural is
begin
return native_lut_size( fam => str2fam(fam_as_string),
no_lut_return_val => no_lut_return_val
);
end;
end package body family_support;
|
bsd-3-clause
|
schelleg/PYNQ
|
boards/ip/dvi2rgb_v1_7/src/TWI_SlaveCtl.vhd
|
15
|
11349
|
-------------------------------------------------------------------------------
--
-- File: TWI_SlaveCtl.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 22 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module is a two-wire (I2C compatible) slave controller responding
-- to the address defined in SLAVE_ADDRESS. It samples the bus and
-- deserializes data. The module needs to be controlled in turn by a
-- high-level controller.
-- Status signals:
-- DONE_O active-high pulsed when the slave is addressed by a master,
-- or when a data byte is either sent or received
-- END_O active-high pulsed when the master ended the transfer
-- RD_WRN_O high when transfer is read, low when write
-- Control signals:
-- STB_I needs to be held high when the current byte needs to be
-- acknowledged; this is the case for the device address, as
-- well as every byte written to-slave
-- D_I data needs to be provided on this bus when read transaction
-- occurs; needs to be held until DONE_O
-- D_O data will appear on D_O when a write transaction occurs;
-- valid on DONE_O
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
entity TWI_SlaveCtl is
generic (
SLAVE_ADDRESS : std_logic_vector(7 downto 0) := x"A0"; -- TWI Slave address
kSampleClkFreqInMHz : natural := 100
);
Port ( D_I : in STD_LOGIC_VECTOR (7 downto 0);
D_O : out STD_LOGIC_VECTOR (7 downto 0);
RD_WRN_O : out STD_LOGIC;
END_O : out STD_LOGIC;
DONE_O : out STD_LOGIC;
STB_I : in STD_LOGIC;
SampleClk : in STD_LOGIC;
SRST : in STD_LOGIC;
--two-wire bus
SDA_I : in STD_LOGIC;
SDA_O : out STD_LOGIC;
SDA_T : out STD_LOGIC;
SCL_I : in STD_LOGIC;
SCL_O : out STD_LOGIC;
SCL_T : out STD_LOGIC
);
end TWI_SlaveCtl;
architecture Behavioral of TWI_SlaveCtl is
constant kGlitchDurationInNs : natural := 50; --tSP in I2C specs
constant kNoOfPeriodsToFilter : natural := natural(ceil(real(kGlitchDurationInNs * kSampleClkFreqInMHz) / 1000.0));
attribute fsm_encoding: string;
type state_type is (stIdle, stAddress, stRead, stWrite, stSAck, stMAck, stTurnAround);
signal state, nstate : state_type;
attribute fsm_encoding of state: signal is "gray";
signal dSda, ddSda, dScl, ddScl : std_logic;
signal fStart, fStop, fSCLFalling, fSCLRising : std_logic;
signal dataByte : std_logic_vector(7 downto 0); --shift register and parallel load
signal iEnd, iDone, latchData, dataBitOut, shiftBitIn, shiftBitOut : std_logic;
signal rd_wrn, drive : std_logic;
signal bitCount : natural range 0 to 7 := 7;
signal sSda, sScl, sSdaFtr, sSclFtr : std_logic;
begin
-- Synchronize SDA and SCL inputs
SyncSDA: entity work.SyncAsync
generic map (
kResetTo => '1',
kStages => 2)
port map (
aReset => '0',
aIn => SDA_I,
OutClk => SampleClk,
oOut => sSda);
SyncSCL: entity work.SyncAsync
generic map (
kResetTo => '1',
kStages => 2)
port map (
aReset => '0',
aIn => SCL_I,
OutClk => SampleClk,
oOut => sScl);
-- Glitch filter as required by I2C Fast-mode specs
GlitchF_SDA: entity work.GlitchFilter
Generic map (kNoOfPeriodsToFilter)
Port map (
SampleClk => SampleClk,
sIn => sSda,
sOut => sSdaFtr,
sRst => SRST);
GlitchF_SCL: entity work.GlitchFilter
Generic map (kNoOfPeriodsToFilter)
Port map (
SampleClk => SampleClk,
sIn => sScl,
sOut => sSclFtr,
sRst => SRST);
----------------------------------------------------------------------------------
--Bus State detection
----------------------------------------------------------------------------------
EdgeDetect: process(SampleClk)
begin
if Rising_Edge(SampleClk) then
dSda <= sSdaFtr;
ddSda <= dSda;
dScl <= sSclFtr;
ddScl <= dScl;
end if;
end process;
fStart <= dSCL and not dSda and ddSda; --if SCL high while SDA falling, start condition
fStop <= dSCL and dSda and not ddSda; --if SCL high while SDA rising, stop condition
fSCLFalling <= ddSCL and not dScl; -- SCL falling
fSCLRising <= not ddSCL and dScl; -- SCL rising
----------------------------------------------------------------------------------
-- Open-drain outputs for bi-directional SDA and SCL
----------------------------------------------------------------------------------
SDA_T <= '1' when dataBitOut = '1' or drive = '0' else -- high-Z
'0'; --drive
SDA_O <= '0';
SCL_T <= '1'; -- input 4eva
SCL_O <= '0';
----------------------------------------------------------------------------------
-- Title: Data byte shift register
-- Description: Stores the byte to be written or the byte read depending on the
-- transfer direction.
----------------------------------------------------------------------------------
DATABYTE_SHREG: process (SampleClk)
begin
if Rising_Edge(SampleClk) then
if ((latchData = '1' and fSCLFalling = '1') or state = stIdle or fStart = '1') then
dataByte <= D_I; --latch data
bitCount <= 7;
elsif (shiftBitOut = '1' and fSCLFalling = '1') then
dataByte <= dataByte(dataByte'high-1 downto 0) & dSDA;
bitCount <= bitCount - 1;
elsif (shiftBitIn = '1' and fSCLRising = '1') then
dataByte <= dataByte(dataByte'high-1 downto 0) & dSDA;
bitCount <= bitCount - 1;
end if;
end if;
end process;
dataBitOut <= '0' when state = stSAck else
dataByte(dataByte'high);
D_O <= dataByte;
RD_WRN_O <= rd_wrn;
RDWRN_BIT_REG: process (SampleClk)
begin
if Rising_Edge(SampleClk) then
if (state = stAddress and bitCount = 0 and fSCLRising = '1') then
rd_wrn <= dSDA;
end if;
end if;
end process;
SYNC_PROC: process (SampleClk)
begin
if Rising_Edge(SampleClk) then
state <= nstate;
END_O <= iEnd;
DONE_O <= iDone;
end if;
end process;
OUTPUT_DECODE: process (nstate, state, fSCLRising, fSCLFalling, ddSDA, bitCount, rd_wrn, dataByte, fStop, fStart)
begin
iDone <= '0';
iEnd <= '0';
shiftBitIn <= '0';
shiftBitOut <= '0';
latchData <= '0';
drive <= '0';
if (state = stRead or state = stSAck) then
drive <= '1';
end if;
if (state = stAddress or state = stWrite) then
shiftBitIn <= '1';
end if;
if (state = stRead) then
shiftBitOut <= '1';
end if;
if ((state = stSAck and rd_wrn = '1') or
(state = stMAck and ddSda = '0')) then --get the data byte for the next read
latchData <= '1';
end if;
if ((state = stAddress and bitCount = 0 and fSCLRising = '1' and dataByte(6 downto 0) = SLAVE_ADDRESS(7 downto 1)) or
(state = stWrite and bitCount = 0 and fSCLRising = '1') or
(state = stRead and bitCount = 0 and fSCLFalling = '1')) then
iDone <= '1';
end if;
if (fStop = '1' or fStart = '1' or
(state = stMAck and fSCLRising = '1' and ddSDA = '1')) then
iEnd <= '1';
end if;
end process;
NEXT_STATE_DECODE: process (state, fStart, STB_I, fSCLRising, fSCLFalling, bitCount, ddSDA, rd_wrn, dataByte, fStop)
begin
nstate <= state; --default is to stay in current state
case (state) is
when stIdle =>
if (fStart = '1') then -- start condition received
nstate <= stAddress;
end if;
when stAddress =>
if (fStop = '1') then
nstate <= stIdle;
elsif (bitCount = 0 and fSCLRising = '1') then
if (dataByte(6 downto 0) = SLAVE_ADDRESS(7 downto 1)) then
nstate <= stTurnAround;
else
nstate <= stIdle;
end if;
end if;
when stTurnAround =>
if (fStop = '1') then
nstate <= stIdle;
elsif (fStart = '1') then
nstate <= stAddress;
elsif (fSCLFalling = '1') then
if (STB_I = '1') then
nstate <= stSAck; --we acknowledge and continue
else
nstate <= stIdle; --don't ack and stop
end if;
end if;
when stSAck =>
if (fStop = '1') then
nstate <= stIdle;
elsif (fStart = '1') then
nstate <= stAddress;
elsif fSCLFalling = '1' then
if (rd_wrn = '1') then
nstate <= stRead;
else
nstate <= stWrite;
end if;
end if;
when stWrite =>
if (fStop = '1') then
nstate <= stIdle;
elsif (fStart = '1') then
nstate <= stAddress;
elsif (bitCount = 0 and fSCLRising = '1') then
nstate <= stTurnAround;
end if;
when stMAck =>
if (fStop = '1') then
nstate <= stIdle;
elsif (fStart = '1') then
nstate <= stAddress;
elsif (fSCLFalling = '1') then
if (ddSDA = '1') then
nstate <= stIdle;
else
nstate <= stRead;
end if;
end if;
when stRead =>
if (fStop = '1') then
nstate <= stIdle;
elsif (fStart = '1') then
nstate <= stAddress;
elsif (bitCount = 0 and fSCLFalling = '1') then
nstate <= stMAck;
end if;
when others =>
nstate <= stIdle;
end case;
end process;
end Behavioral;
|
bsd-3-clause
|
schelleg/PYNQ
|
boards/ip/dvi2rgb_v1_7/src/ChannelBond.vhd
|
15
|
6809
|
-------------------------------------------------------------------------------
--
-- File: ChannelBond.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 8 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module de-skews data channels relative to each other. TMDS specs
-- allow 0.2 Tcharacter + 1.78ns skew between channels. To re-align the
-- channels all are buffered in FIFOs until a special marker (the beginning
-- of a blanking period) is found on all the channels.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.DVI_Constants.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ChannelBond is
Port (
PixelClk : in std_logic;
pDataInRaw : in std_logic_vector(9 downto 0);
pMeVld : in std_logic;
pOtherChVld : in std_logic_vector(1 downto 0);
pOtherChRdy : in std_logic_vector(1 downto 0);
pDataInBnd : out std_logic_vector(9 downto 0);
pMeRdy : out std_logic
);
end ChannelBond;
architecture Behavioral of ChannelBond is
constant kFIFO_Depth : natural := 32;
type FIFO_t is array (0 to kFIFO_Depth-1) of std_logic_vector(9 downto 0);
signal pFIFO : FIFO_t;
signal pDataFIFO : std_logic_vector(9 downto 0);
signal pRdA, pWrA : natural range 0 to kFIFO_Depth-1;
signal pRdEn : std_logic;
signal pAllVld, pAllVld_q, pMeRdy_int: std_logic;
signal pBlnkBgnFlag, pTokenFlag, pTokenFlag_q, pAllVldBgnFlag : std_logic;
begin
pAllVld <= pMeVld and pOtherChVld(0) and pOtherChVld(1);
pDataInBnd <= pDataFIFO; -- raw data with skew removed
pMeRdy <= pMeRdy_int; -- data is de-skewed and valid
-- The process below should result in a dual-port distributed RAM with registered output
FIFO: process (PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pAllVld = '1') then -- begin writing in FIFO as soon as all the channels have valid data
pFIFO(pWrA) <= pDataInRaw;
end if;
pDataFIFO <= pFIFO(pRdA); -- register FIFO output
end if;
end process FIFO;
-- FIFO address counters
FIFO_WrA: process (PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pAllVld = '1') then
pWrA <= pWrA + 1;
else -- when invalid data, go back to the beginning
pWrA <= 0;
end if;
end if;
end process FIFO_WrA;
FIFO_RdA: process (PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pAllVld = '0') then
pRdA <= 0;
elsif (pRdEn = '1') then
pRdA <= pRdA + 1;
end if;
end if;
end process FIFO_RdA;
DataValidFlag: process(PixelClk)
begin
if Rising_Edge(PixelClk) then
pAllVld_q <= pAllVld;
pAllVldBgnFlag <= not pAllVld_q and pAllVld; -- this flag used below delays enabling read, thus making sure data is written first before being read
end if;
end process DataValidFlag;
-------------------------------------------------------------------------------
-- Channel bonding is done here:
-- 1 When all the channels have valid data (ie. alignment lock), FIFO is flow-through
-- 2 When marker is found on this channel, FIFO read is paused, thus holding data
-- 3 When all channels report the marker, FIFO read begins again, thus syncing markers
-------------------------------------------------------------------------------
FIFO_RdEn: process(PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pAllVld = '0') then
pRdEn <= '0';
elsif (pAllVldBgnFlag = '1' or (pMeRdy_int = '1' and pOtherChRdy = "11")) then
pRdEn <= '1';
elsif (pBlnkBgnFlag = '1' and not (pMeRdy_int = '1' and pOtherChRdy = "11")) then
pRdEn <= '0';
end if;
end if;
end process FIFO_RdEn;
-- Detect blanking period begin
TokenDetect: process(PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pRdEn = '0' or pDataFIFO = kCtlTkn0 or pDataFIFO = kCtlTkn1 or pDataFIFO = kCtlTkn2 or pDataFIFO = kCtlTkn3) then
pTokenFlag <= '1'; --token flag activates on invalid data, which avoids a BlnkBgn pulse if the valid signal goes up in the middle of a blanking period
else
pTokenFlag <= '0';
end if;
pTokenFlag_q <= pTokenFlag;
pBlnkBgnFlag <= not pTokenFlag_q and pTokenFlag;
end if;
end process TokenDetect;
-- Ready signal when marker is received
IAmReady: process(PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pAllVld = '0') then -- if not all channels are valid, we are not ready either
pMeRdy_int <= '0';
elsif (pBlnkBgnFlag = '1') then
pMeRdy_int <= '1';
end if;
end if;
end process IAmReady;
end Behavioral;
|
bsd-3-clause
|
sigasi/SigasiProjectCreator
|
tests/test-files/tree/clock_generator.vhd
|
2
|
448
|
library IEEE;
use IEEE.std_logic_1164.all;
-- Generate a clock signal.
-- Duty cycle is 50%.
-- Frequency = 1/PERIOD
entity clock_generator is
generic(
PERIOD : time := 25 ns
);
port(
clk : out std_logic
);
end entity clock_generator;
architecture BEH of clock_generator is
begin
CLOCK_DRIVER : process is
begin
clk <= '0';
wait for PERIOD / 2;
clk <= '1';
wait for PERIOD / 2;
end process CLOCK_DRIVER;
end architecture BEH;
|
bsd-3-clause
|
sigasi/SigasiProjectCreator
|
tests/test-files/tree/dut.vhd
|
2
|
940
|
library IEEE;
use IEEE.std_logic_1164.all;
entity dut is
port(
data_out : out std_logic_vector(7 downto 0);
data_in : in std_logic_vector(7 downto 0);
valid : out std_logic;
start : in std_logic;
clk : in std_logic;
rst : in std_logic
);
end entity dut;
architecture RTL of dut is
constant MIN_COUNT : integer := 0;
constant MAX_COUNT : integer := 5;
signal count : integer range 0 to MAX_COUNT;
begin
OUTPUT_GENERATOR : process(count, data_in) is
begin
if count = MAX_COUNT then
valid <= '1';
data_out <= data_in;
else
valid <= '0';
data_out <=(others => '0');
end if;
end process OUTPUT_GENERATOR;
COUNTER : process(clk, rst) is
begin
if rst = '1' then
count <= 0;
elsif rising_edge(clk) then
if start = '1' then
count <= 0;
elsif count < MAX_COUNT then
count <= count + 1;
end if;
end if;
end process COUNTER;
end architecture RTL;
|
bsd-3-clause
|
sigasi/SigasiProjectCreator
|
tests/test-files/extra-sources/notMapped.vhd
|
12226531
|
0
|
bsd-3-clause
|
|
masson2013/heterogeneous_hthreads
|
src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/ipif_common_v1_00_c/hdl/vhdl/ipif_pkg.vhd
|
2
|
49682
|
-------------------------------------------------------------------------------
-- $Id: ipif_pkg.vhd,v 1.3 2003/04/28 20:47:23 ostlerf Exp $
-------------------------------------------------------------------------------
-- IPIF Common Library Package
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: ipif_pkg.vhd
-- Version: Intital
-- Description: This file contains the constants and functions used in the
-- ipif common library components.
--
-------------------------------------------------------------------------------
-- Structure:
--
-------------------------------------------------------------------------------
-- Author: DET
-- History:
-- DET 02/21/02 -- Created from proc_common_pkg.vhd
--
-- DET 03/13/02 -- PLB IPIF development updates
-- ^^^^^^
-- - Commented out string types and string functions due to an XST
-- problem with string arrays and functions. THe string array
-- processing functions were replaced with comperable functions
-- operating on integer arrays.
-- ~~~~~~
--
--
-- DET 4/30/2002 Initial
-- ~~~~~~
-- - Added three functions: rebuild_slv32_array, rebuild_slv64_array, and
-- rebuild_int_array to support removal of unused elements from the
-- ARD arrays.
-- ^^^^^^ --
--
-- FLO 8/12/2002
-- ~~~~~~
-- - Added three functions: bits_needed_for_vac, bits_needed_for_occ,
-- and get_id_index_iboe.
-- (Removed provisional functions bits_needed_for_vacancy,
-- bits needed_for_occupancy, and bits_needed_for.)
-- ^^^^^^
--
-- FLO 3/24/2003
-- ~~~~~~
-- - Added dependent property paramters for channelized DMA.
-- - Added common property parameter array type.
-- - Definded the KEYHOLD_BURST common-property parameter.
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- need conversion function to convert reals/integers to std logic vectors
use ieee.std_logic_arith.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
package ipif_pkg is
-------------------------------------------------------------------------------
-- Type Declarations
-------------------------------------------------------------------------------
Type SLV32_ARRAY_TYPE is array (natural range <>) of std_logic_vector(0 to 31);
subtype SLV64_TYPE is std_logic_vector(0 to 63);
Type SLV64_ARRAY_TYPE is array (natural range <>) of SLV64_TYPE;
Type INTEGER_ARRAY_TYPE is array (natural range <>) of integer;
-- xst work around!!! Type ARD_NAME_TYPE is array (natural range <>) of string(1 to 32);
--ToDo, at some time when this file is otherwise stable, remove the
-- "xst work around!!!" stuff. The work arounds are permanent, now.
-------------------------------------------------------------------------------
-- Function and Procedure Declarations
-------------------------------------------------------------------------------
function "=" (s1: in string; s2: in string) return boolean;
function equaluseCase( str1, str2 : STRING ) RETURN BOOLEAN;
function calc_num_ce (ce_num_array : INTEGER_ARRAY_TYPE) return integer;
-- xst work around!!! function find_ard_name (name_array : ARD_NAME_TYPE;
-- xst work around!!! name : string) return boolean;
-- xst work around!!! function get_name_index (name_array :ARD_NAME_TYPE;
-- xst work around!!! name : string) return integer;
function calc_start_ce_index (ce_num_array : INTEGER_ARRAY_TYPE;
index : integer) return integer;
function get_min_dwidth (dwidth_array: INTEGER_ARRAY_TYPE) return integer;
function get_max_dwidth (dwidth_array: INTEGER_ARRAY_TYPE) return integer;
-- xst work around!!! function find_a_dwidth (name_array : ARD_NAME_TYPE;
-- xst work around!!! dwidth_array: INTEGER_ARRAY_TYPE;
-- xst work around!!! name : string;
-- xst work around!!! default : integer) return integer;
function S32 (in_string : string) return string;
-- xst work around!!! function cnt_ipif_blks (name_array : ARD_NAME_TYPE) return integer;
-- xst work around!!! function get_ipif_dbus_index (name_array: ARD_NAME_TYPE;
-- xst work around!!! name : string)
-- xst work around!!! return integer ;
--/////////////////////////////////////////////////////////////////////////////
-- xst debug!!!
-- Hopefully temporary functions that use an array of integers to identify
-- functions specified in the ARD arrays
function get_id_index (id_array :INTEGER_ARRAY_TYPE;
id : integer)
return integer;
function get_id_index_iboe (id_array :INTEGER_ARRAY_TYPE;
id : integer)
return integer;
function find_ard_id (id_array : INTEGER_ARRAY_TYPE;
id : integer) return boolean;
function find_id_dwidth (id_array : INTEGER_ARRAY_TYPE;
dwidth_array: INTEGER_ARRAY_TYPE;
id : integer;
default : integer)
return integer;
function cnt_ipif_id_blks (id_array : INTEGER_ARRAY_TYPE) return integer;
function get_ipif_id_dbus_index (id_array : INTEGER_ARRAY_TYPE;
id : integer)
return integer ;
function rebuild_slv32_array (slv32_array : SLV32_ARRAY_TYPE;
num_valid_pairs : integer)
return SLV32_ARRAY_TYPE;
function rebuild_slv64_array (slv64_array : SLV64_ARRAY_TYPE;
num_valid_pairs : integer)
return SLV64_ARRAY_TYPE;
function rebuild_int_array (int_array : INTEGER_ARRAY_TYPE;
num_valid_entry : integer)
return INTEGER_ARRAY_TYPE;
--/////////////////////////////////////////////////////////////////////////////
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- xst debug!!! -- constant declarations of ARD Name array reserved words of IPIF modules
-- xst debug!!! Constant IPIF_WRFIFO_REG : string := "ipif_wrfifo_reg ";
-- xst debug!!! Constant IPIF_WRFIFO_DATA : string := "ipif_wrfifo_data ";
-- xst debug!!! Constant IPIF_RDFIFO_REG : string := "ipif_rdfifo_reg ";
-- xst debug!!! Constant IPIF_RDFIFO_DATA : string := "ipif_rdfifo_data ";
-- xst debug!!! Constant IPIF_RST : string := "ipif_reset ";
-- xst debug!!! Constant IPIF_INTR : string := "ipif_interrupt ";
-- xst debug!!! Constant IPIF_DMA_SG : string := "ipif_dma_sg ";
-- xst debug!!! Constant IPIF_SESR_SEAR : string := "ipif_sear_sesr ";
--/////////////////////////////////////////////////////////////////////////////
-- xst debug!!!
-- temporary integer aliases of ARD ID (in place of strings)
-- IPIF Module aliases
Constant IPIF_INTR : integer := 1;
Constant IPIF_RST : integer := 2;
Constant IPIF_SESR_SEAR : integer := 3;
Constant IPIF_DMA_SG : integer := 4;
Constant IPIF_WRFIFO_REG : integer := 5;
Constant IPIF_WRFIFO_DATA : integer := 6;
Constant IPIF_RDFIFO_REG : integer := 7;
Constant IPIF_RDFIFO_DATA : integer := 8;
Constant IPIF_CHDMA_CHANNELS : integer := 9;
Constant IPIF_CHDMA_EVENT_FIFO : integer := 10;
Constant CHDMA_STATUS_FIFO : integer := 90;
-- Some predefined user module aliases
Constant USER_00 : integer := 100;
Constant USER_01 : integer := 101;
Constant USER_02 : integer := 102;
Constant USER_03 : integer := 103;
Constant USER_04 : integer := 104;
Constant USER_05 : integer := 105;
Constant USER_06 : integer := 106;
Constant USER_07 : integer := 107;
Constant USER_08 : integer := 108;
Constant USER_09 : integer := 109;
Constant USER_10 : integer := 110;
Constant USER_11 : integer := 111;
Constant USER_12 : integer := 112;
Constant USER_13 : integer := 113;
Constant USER_14 : integer := 114;
Constant USER_15 : integer := 115;
Constant USER_16 : integer := 116;
--/////////////////////////////////////////////////////////////////////////////
--------------------------------------------------------------------------------
-- Declarations for Dependent Properties (properties that depend on the type of
-- the address range). There is one property, i.e. one parameter, encoded as
-- an integer at each index of the properties array. There is one properties
-- array for each address range.
--------------------------------------------------------------------------------
constant DEPENDENT_PROPS_SIZE : integer := 6;
subtype DEPENDENT_PROPS_TYPE
is INTEGER_ARRAY_TYPE(0 to DEPENDENT_PROPS_SIZE-1);
type DEPENDENT_PROPS_ARRAY_TYPE
is array (natural range <>) of DEPENDENT_PROPS_TYPE;
--------------------------------------------------------------------------------
-- Below are the indices of dependent properties for the different types of
-- address ranges.
--
-- Example: Let C_ARD_DEPENDENT_PROPS_ARRAY hold the dependent properites
-- for a set of address ranges. Then, e.g.,
--
-- C_ARD_DEPENDENT_PROPS_ARRAY(i)(FIFO_CAPACITY_BITS)
--
-- gives the fifo capacity in bits, provided that the i'th address range
-- is of type IPIF_WRFIFO_DATA or IPIF_RDFIFO_DATA.
--
-- These indices should be referenced only by the names below and never
-- by numerical literals. (The right to change numerical index assignments
-- is reserved; applications using the names will not be affected by such
-- reassignments.)
--------------------------------------------------------------------------------
--
--ToDo, if the interrupt controller parameterization is ever moved to
-- C_ARD_DEPENDENT_PROPS_ARRAY, then the following declarations
-- could be uncommented and used.
---- IPIF_INTR IDX
------------------------------------------------------------------------------ ---
--constant EXCLUDE_DEV_ISC : integer := 0;
-- -- 1 specifies that only the global interrupt
-- -- enable is present in the device interrupt source
-- -- controller and that the only source of interrupts
-- -- in the device is the IP interrupt source controller.
-- -- 0 specifies that the full device interrupt
-- -- source controller structure will be included.
--constant INCLUDE_DEV_PENCODER : integer := 1;
---- -- 1 will include the Device IID in the device interrupt
---- -- source controller, 0 will exclude it.
--
-- IPIF_WRFIFO_DATA or IPIF_RDFIFO_DATA IDX
---------------------------------------------------------------------------- ---
constant FIFO_CAPACITY_BITS : integer := 0;
constant WR_WIDTH_BITS : integer := 1;
constant RD_WIDTH_BITS : integer := 2;
constant EXCLUDE_PACKET_MODE : integer := 3;
-- 1 Don't include packet mode features
-- 0 Include packet mode features
constant EXCLUDE_VACANCY : integer := 4;
-- 1 Don't include vacancy calculation
-- 0 Include vacancy calculation
--------------------------------------------------------------------------------
-- IPIF_CHDMA_CHANNELS IDX
---------------------------------------------------------------------------- ---
constant NUM_CHANNELS : integer := 0;
constant INTR_COALESCE : integer := 1;
-- 0 Interrupt coalescing is disabled
-- 1 Interrupt coalescing is enabled
constant CLK_PERIOD_PS : integer := 2;
-- The period of the OPB Bus clock in ps.
-- The default value of 0 is a special value that
-- is synonymous with 10000 ps (10 ns).
-- Relevant only if (INTR_COALESCE = 1).
constant PACKET_WAIT_UNIT_NS : integer := 3;
-- Gives the unit for used for timing pack-wait bounds.
-- The default value of 0 is a special value that
-- is synonymous with 1,000,000 ps (1 ms).
-- Relevant only if (INTR_COALESCE = 1).
constant DISALLOW_BURST : integer := 4;
-- 0 allows DMA to initiate burst transfers
-- 1 inhibits DMA initiated burst transfers
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Calculates the number of bits needed to convey the vacancy (emptiness) of
-- the fifo described by dependent_props, if fifo_present. If not fifo_present,
-- returns 0 (or the smallest value allowed by tool limitations on null arrays)
-- without making reference to dependent_props.
--------------------------------------------------------------------------------
function bits_needed_for_vac(
fifo_present: boolean;
dependent_props : DEPENDENT_PROPS_TYPE
) return integer;
--------------------------------------------------------------------------------
-- Calculates the number of bits needed to convey the occupancy (fullness) of
-- the fifo described by dependent_props, if fifo_present. If not fifo_present,
-- returns 0 (or the smallest value allowed by tool limitations on null arrays)
-- without making reference to dependent_props.
--------------------------------------------------------------------------------
function bits_needed_for_occ(
fifo_present: boolean;
dependent_props : DEPENDENT_PROPS_TYPE
) return integer;
--------------------------------------------------------------------------------
-- Declarations for Common Properties (properties that apply regardless of the
-- type of the address range). Structurally, these work the same as
-- the dependent properties.
--------------------------------------------------------------------------------
constant COMMON_PROPS_SIZE : integer := 2;
subtype COMMON_PROPS_TYPE
is INTEGER_ARRAY_TYPE(0 to COMMON_PROPS_SIZE-1);
type COMMON_PROPS_ARRAY_TYPE
is array (natural range <>) of COMMON_PROPS_TYPE;
--------------------------------------------------------------------------------
-- Below are the indices of the common properties.
--
-- These indices should be referenced only by the names below and never
-- by numerical literals.
-- IDX
---------------------------------------------------------------------------- ---
constant KEYHOLE_BURST : integer := 0;
-- 1 All addresses of a burst are forced to the initial
-- address of the burst.
-- 0 Burst addresses follow the bus protocol.
-- IP interrupt mode array constants
Constant INTR_PASS_THRU : integer := 1;
Constant INTR_PASS_THRU_INV : integer := 2;
Constant INTR_REG_EVENT : integer := 3;
Constant INTR_REG_EVENT_INV : integer := 4;
Constant INTR_POS_EDGE_DETECT : integer := 5;
Constant INTR_NEG_EDGE_DETECT : integer := 6;
end ipif_pkg;
library proc_common_v1_00_b;
use proc_common_v1_00_b.proc_common_pkg.log2;
package body ipif_pkg is
-------------------------------------------------------------------------------
-- Function Definitions
-------------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Function "="
--
-- This function is used to overload the "=" operator when comparing
-- strings.
-----------------------------------------------------------------------------
function "=" (s1: in string; s2: in string) return boolean is
constant tc: character := ' '; -- string termination character
variable i: integer := 1;
variable v1 : string(1 to s1'length) := s1;
variable v2 : string(1 to s2'length) := s2;
begin
while (i <= v1'length) and (v1(i) /= tc) and
(i <= v2'length) and (v2(i) /= tc) and
(v1(i) = v2(i))
loop
i := i+1;
end loop;
return ((i > v1'length) or (v1(i) = tc)) and
((i > v2'length) or (v2(i) = tc));
end;
----------------------------------------------------------------------------
-- Function equaluseCase
--
-- This function returns true if case sensitive string comparison determines
-- that str1 and str2 are the same.
-----------------------------------------------------------------------------
FUNCTION equaluseCase( str1, str2 : STRING ) RETURN BOOLEAN IS
CONSTANT len1 : INTEGER := str1'length;
CONSTANT len2 : INTEGER := str2'length;
VARIABLE equal : BOOLEAN := TRUE;
BEGIN
IF NOT (len1=len2) THEN
equal := FALSE;
ELSE
FOR i IN str1'range LOOP
IF NOT (str1(i) = str2(i)) THEN
equal := FALSE;
END IF;
END LOOP;
END IF;
RETURN equal;
END equaluseCase;
-----------------------------------------------------------------------------
-- Function calc_num_ce
--
-- This function is used to process the array specifying the number of Chip
-- Enables required for a Base Address specification. The array is input to
-- the function and an integer is returned reflecting the total number of
-- Chip Enables required for the CE, RdCE, and WrCE Buses
-----------------------------------------------------------------------------
function calc_num_ce (ce_num_array : INTEGER_ARRAY_TYPE) return integer is
Variable ce_num_sum : integer := 0;
begin
for i in 0 to (ce_num_array'length)-1 loop
ce_num_sum := ce_num_sum + ce_num_array(i);
End loop;
return(ce_num_sum);
end function calc_num_ce;
-- xst work around!!! -----------------------------------------------------------------------------
-- xst work around!!! -- Function find_ard_name
-- xst work around!!! --
-- xst work around!!! -- This function is used to process the array specifying the target function
-- xst work around!!! -- assigned to a Base Address pair address range. The dest_name_array and a
-- xst work around!!! -- string name is input to the function. A boolean is returned reflecting the
-- xst work around!!! -- presence (or not) of a string matching the name input string.
-- xst work around!!! -----------------------------------------------------------------------------
-- xst work around!!! function find_ard_name (name_array : ARD_NAME_TYPE;
-- xst work around!!! name : string) return boolean is
-- xst work around!!!
-- xst work around!!! Variable match : Boolean := false;
-- xst work around!!! Variable temp_string : string(1 to 32);
-- xst work around!!!
-- xst work around!!! begin
-- xst work around!!!
-- xst work around!!! for array_index in 0 to name_array'length-1 loop
-- xst work around!!!
-- xst work around!!! temp_string := name_array(array_index);
-- xst work around!!! If (match = true) Then -- match already found so do nothing
-- xst work around!!!
-- xst work around!!! null;
-- xst work around!!!
-- xst work around!!! else -- compare string characters one by one
-- xst work around!!!
-- xst work around!!! match := equaluseCase(temp_string, name);
-- xst work around!!!
-- xst work around!!! End if;
-- xst work around!!!
-- xst work around!!! End loop;
-- xst work around!!!
-- xst work around!!! return(match);
-- xst work around!!!
-- xst work around!!! end function find_ard_name;
-- optional implementation -----------------------------------------------------------------------------
-- optional implementation -- Function find_ard_name
-- optional implementation --
-- optional implementation -- This function is used to process the array specifying the target function
-- optional implementation -- assigned to a Base Address pair address range. The dest_name_array and a
-- optional implementation -- string name is input to the function. A boolean is returned reflecting the
-- optional implementation -- presence (or not) of a string matching the name input string.
-- optional implementation -----------------------------------------------------------------------------
-- optional implementation function find_ard_name (name_array : ARD_NAME_TYPE;
-- optional implementation name : string) return boolean is
-- optional implementation
-- optional implementation Variable match : Boolean := false;
-- optional implementation Variable temp_string : string(1 to 32);
-- optional implementation
-- optional implementation begin
-- optional implementation
-- optional implementation --for array_index in 0 to name_array'length-1 loop
-- optional implementation for array_index in 0 to name_array'length-1 loop
-- optional implementation
-- optional implementation temp_string := name_array(array_index);
-- optional implementation
-- optional implementation If (match = true) Then -- match already found so do nothing
-- optional implementation
-- optional implementation null;
-- optional implementation
-- optional implementation else -- compare the strings using "=" overload function
-- optional implementation
-- optional implementation If (temp_string = name) Then
-- optional implementation match := true;
-- optional implementation else
-- optional implementation null;
-- optional implementation End if;
-- optional implementation
-- optional implementation End if;
-- optional implementation
-- optional implementation End loop;
-- optional implementation
-- optional implementation return(match);
-- optional implementation
-- optional implementation end function find_ard_name;
-- optional implementation
-- xst work around!!! -----------------------------------------------------------------------------
-- xst work around!!! -- Function get_name_index
-- xst work around!!! --
-- xst work around!!! -- This function is used to process the array specifying the target function
-- xst work around!!! -- assigned to a Base Address pair address range. The dest_name_array and a
-- xst work around!!! -- string name is input to the function. A integer is returned reflecting the
-- xst work around!!! -- array index of the string matching the name input string. This function
-- xst work around!!! -- should only be called if the compare string is known to exist in the
-- xst work around!!! -- name_array input. This can be detirmined by using the find_ard_name
-- xst work around!!! -- function.
-- xst work around!!! -----------------------------------------------------------------------------
-- xst work around!!! function get_name_index (name_array :ARD_NAME_TYPE;
-- xst work around!!! name : string) return integer is
-- xst work around!!!
-- xst work around!!! Variable match : Boolean := false;
-- xst work around!!! Variable match_index : Integer := 0;
-- xst work around!!! Variable temp_string : string(1 to 32);
-- xst work around!!!
-- xst work around!!!
-- xst work around!!! begin
-- xst work around!!!
-- xst work around!!! for array_index in 0 to name_array'length-1 loop
-- xst work around!!!
-- xst work around!!!
-- xst work around!!! temp_string := name_array(array_index);
-- xst work around!!!
-- xst work around!!! If (match = true) Then -- match already found so do nothing
-- xst work around!!!
-- xst work around!!! null;
-- xst work around!!!
-- xst work around!!! else -- compare string characters one by one
-- xst work around!!!
-- xst work around!!! match := equaluseCase(temp_string, name);
-- xst work around!!! match_index := array_index;
-- xst work around!!!
-- xst work around!!! End if;
-- xst work around!!!
-- xst work around!!! End loop;
-- xst work around!!!
-- xst work around!!! return(match_index);
-- xst work around!!!
-- xst work around!!! end function get_name_index;
-----------------------------------------------------------------------------
-- Function calc_start_ce_index
--
-- This function is used to process the array specifying the number of Chip
-- Enables required for a Base Address specification. The CE Size array is
-- input to the function and an integer index representing the index of the
-- target module in the ce_num_array. An integer is returned reflecting the
-- starting index of the assigned Chip Enables within the CE, RdCE, and
-- WrCE Buses.
-----------------------------------------------------------------------------
function calc_start_ce_index (ce_num_array : INTEGER_ARRAY_TYPE;
index : integer) return integer is
Variable ce_num_sum : integer := 0;
begin
If (index = 0) Then
ce_num_sum := 0;
else
for i in 0 to index-1 loop
ce_num_sum := ce_num_sum + ce_num_array(i);
End loop;
End if;
return(ce_num_sum);
end function calc_start_ce_index;
-----------------------------------------------------------------------------
-- Function get_min_dwidth
--
-- This function is used to process the array specifying the data bus width
-- for each of the target modules. The dwidth_array is input to the function
-- and an integer is returned that is the smallest value found of all the
-- entries in the array.
-----------------------------------------------------------------------------
function get_min_dwidth (dwidth_array: INTEGER_ARRAY_TYPE) return integer is
Variable temp_min : Integer := 1024;
begin
for i in 0 to dwidth_array'length-1 loop
If (dwidth_array(i) < temp_min) Then
temp_min := dwidth_array(i);
else
null;
End if;
End loop;
return(temp_min);
end function get_min_dwidth;
-----------------------------------------------------------------------------
-- Function get_max_dwidth
--
-- This function is used to process the array specifying the data bus width
-- for each of the target modules. The dwidth_array is input to the function
-- and an integer is returned that is the largest value found of all the
-- entries in the array.
-----------------------------------------------------------------------------
function get_max_dwidth (dwidth_array: INTEGER_ARRAY_TYPE) return integer is
Variable temp_max : Integer := 0;
begin
for i in 0 to dwidth_array'length-1 loop
If (dwidth_array(i) > temp_max) Then
temp_max := dwidth_array(i);
else
null;
End if;
End loop;
return(temp_max);
end function get_max_dwidth;
-- xst work around!!! -----------------------------------------------------------------------------
-- xst work around!!! -- Function find_a_dwidth
-- xst work around!!! --
-- xst work around!!! -- This function is used to find the data width of a target module. If the
-- xst work around!!! -- target module exists, the data width is extracted from the input dwidth
-- xst work around!!! -- array. If the module is not in the name array, the default input is
-- xst work around!!! -- returned. This function is needed to assign data port size constraints.
-- xst work around!!! -----------------------------------------------------------------------------
-- xst work around!!! function find_a_dwidth (name_array : ARD_NAME_TYPE;
-- xst work around!!! dwidth_array: INTEGER_ARRAY_TYPE;
-- xst work around!!! name : string;
-- xst work around!!! default : integer) return integer is
-- xst work around!!!
-- xst work around!!!
-- xst work around!!! Variable name_present : Boolean := false;
-- xst work around!!! Variable array_index: Integer := 0;
-- xst work around!!! Variable dwidth : Integer := default;
-- xst work around!!!
-- xst work around!!! begin
-- xst work around!!!
-- xst work around!!! name_present := find_ard_name(name_array, name);
-- xst work around!!!
-- xst work around!!! If (name_present) Then
-- xst work around!!! array_index := get_name_index (name_array, name);
-- xst work around!!! dwidth := dwidth_array(array_index);
-- xst work around!!! else
-- xst work around!!! null; -- use default input
-- xst work around!!! End if;
-- xst work around!!!
-- xst work around!!!
-- xst work around!!! Return (dwidth);
-- xst work around!!!
-- xst work around!!! end function find_a_dwidth;
-----------------------------------------------------------------------------
-- Function S32
--
-- This function is used to expand an input string to 32 characters by
-- padding with spaces. If the input string is larger than 32 characters,
-- it will truncate to 32 characters.
-----------------------------------------------------------------------------
function S32 (in_string : string) return string is
constant OUTPUT_STRING_LENGTH : integer := 32;
Constant space : character := ' ';
variable new_string : string(1 to 32);
Variable start_index : Integer := in_string'length+1;
begin
If (in_string'length < OUTPUT_STRING_LENGTH) Then
for i in 1 to in_string'length loop
new_string(i) := in_string(i);
End loop;
for j in start_index to OUTPUT_STRING_LENGTH loop
new_string(j) := space;
End loop;
else -- use first 32 chars of in_string (truncate the rest)
for k in 1 to OUTPUT_STRING_LENGTH loop
new_string(k) := in_string(k);
End loop;
End if;
return(new_string);
end function S32;
-- xst work around!!! function cnt_ipif_blks (name_array : ARD_NAME_TYPE) return integer is
-- xst work around!!!
-- xst work around!!! Variable blk_count : integer := 0;
-- xst work around!!! Variable temp_string : string(1 to 32);
-- xst work around!!!
-- xst work around!!! begin
-- xst work around!!!
-- xst work around!!! for array_index in 0 to name_array'length-1 loop
-- xst work around!!!
-- xst work around!!! temp_string := name_array(array_index);
-- xst work around!!!
-- xst work around!!! If (temp_string = IPIF_WRFIFO_DATA or
-- xst work around!!! temp_string = IPIF_RDFIFO_DATA or
-- xst work around!!! temp_string = IPIF_RST or
-- xst work around!!! temp_string = IPIF_INTR or
-- xst work around!!! temp_string = IPIF_DMA_SG or
-- xst work around!!! temp_string = IPIF_SESR_SEAR
-- xst work around!!! ) Then -- IPIF block found
-- xst work around!!!
-- xst work around!!! blk_count := blk_count+1;
-- xst work around!!!
-- xst work around!!! else -- go to next loop iteration
-- xst work around!!!
-- xst work around!!! null;
-- xst work around!!!
-- xst work around!!! End if;
-- xst work around!!!
-- xst work around!!! End loop;
-- xst work around!!!
-- xst work around!!! return(blk_count);
-- xst work around!!!
-- xst work around!!! end function cnt_ipif_blks;
-- xst work around!!! function get_ipif_dbus_index (name_array: ARD_NAME_TYPE;
-- xst work around!!! name : string)
-- xst work around!!! return integer is
-- xst work around!!!
-- xst work around!!! Variable blk_index : integer := 0;
-- xst work around!!! Variable temp_string : string(1 to 32);
-- xst work around!!! Variable name_found : Boolean := false;
-- xst work around!!!
-- xst work around!!! begin
-- xst work around!!!
-- xst work around!!! for array_index in 0 to name_array'length-1 loop
-- xst work around!!!
-- xst work around!!! temp_string := name_array(array_index);
-- xst work around!!!
-- xst work around!!! If (name_found) then
-- xst work around!!!
-- xst work around!!! null;
-- xst work around!!!
-- xst work around!!! elsif (temp_string = name) then
-- xst work around!!!
-- xst work around!!! name_found := true;
-- xst work around!!!
-- xst work around!!! elsif (temp_string = IPIF_WRFIFO_DATA or
-- xst work around!!! temp_string = IPIF_RDFIFO_DATA or
-- xst work around!!! temp_string = IPIF_RST or
-- xst work around!!! temp_string = IPIF_INTR or
-- xst work around!!! temp_string = IPIF_DMA_SG or
-- xst work around!!! temp_string = IPIF_SESR_SEAR
-- xst work around!!! ) Then -- IPIF block found
-- xst work around!!!
-- xst work around!!! blk_index := blk_index+1;
-- xst work around!!!
-- xst work around!!! else -- user block so do nothing
-- xst work around!!!
-- xst work around!!! null;
-- xst work around!!!
-- xst work around!!! End if;
-- xst work around!!!
-- xst work around!!! End loop;
-- xst work around!!!
-- xst work around!!! return(blk_index);
-- xst work around!!!
-- xst work around!!!
-- xst work around!!! end function get_ipif_dbus_index;
--/////////////////////////////////////////////////////////////////////////////
-- xst debug!!!
-- Hopefully temporary functions
-----------------------------------------------------------------------------
-- Function get_id_index
--
-- This function is used to process the array specifying the target function
-- assigned to a Base Address pair address range. The id_array and a
-- id number is input to the function. A integer is returned reflecting the
-- array index of the id matching the id input number. This function
-- should only be called if the id number is known to exist in the
-- name_array input. This can be detirmined by using the find_ard_id
-- function.
-----------------------------------------------------------------------------
function get_id_index (id_array :INTEGER_ARRAY_TYPE;
id : integer) return integer is
Variable match : Boolean := false;
Variable match_index : Integer := 10000; -- a really big number!
begin
for array_index in 0 to id_array'length-1 loop
If (match = true) Then -- match already found so do nothing
null;
else -- compare the numbers one by one
match := (id_array(array_index) = id);
If (match) Then
match_index := array_index;
else
null;
End if;
End if;
End loop;
return(match_index);
end function get_id_index;
--------------------------------------------------------------------------------
-- get_id_index but return a value in bounds on error (iboe).
--
-- This function is the same as get_id_index, except that when id does
-- not exist in id_array, the value returned is any index that is
-- within the index range of id_array.
--
-- This function would normally only be used where function find_ard_id
-- is used to establish the existence of id but, even when non-existent,
-- an element of one of the ARD arrays will be computed from the
-- returned get_id_index_iboe value. See, e.g., function bits_needed_for_vac
-- and the example call, below
--
-- bits_needed_for_vac(
-- find_ard_id(C_ARD_ID_ARRAY, IPIF_RDFIFO_DATA),
-- C_ARD_DEPENDENT_PROPS_ARRAY(get_id_index_iboe(C_ARD_ID_ARRAY,
-- IPIF_RDFIFO_DATA))
-- )
--------------------------------------------------------------------------------
function get_id_index_iboe (id_array :INTEGER_ARRAY_TYPE;
id : integer) return integer is
Variable match : Boolean := false;
Variable match_index : Integer := id_array'left; -- any valid array index
begin
for array_index in 0 to id_array'length-1 loop
If (match = true) Then -- match already found so do nothing
null;
else -- compare the numbers one by one
match := (id_array(array_index) = id);
If (match) Then match_index := array_index;
else null;
End if;
End if;
End loop;
return(match_index);
end function get_id_index_iboe;
-----------------------------------------------------------------------------
-- Function find_ard_id
--
-- This function is used to process the array specifying the target function
-- assigned to a Base Address pair address range. The id_array and a
-- integer id is input to the function. A boolean is returned reflecting the
-- presence (or not) of a number in the array matching the id input number.
-----------------------------------------------------------------------------
function find_ard_id (id_array : INTEGER_ARRAY_TYPE;
id : integer) return boolean is
Variable match : Boolean := false;
begin
for array_index in 0 to id_array'length-1 loop
If (match = true) Then -- match already found so do nothing
null;
else -- compare the numbers one by one
match := (id_array(array_index) = id);
End if;
End loop;
return(match);
end function find_ard_id;
-----------------------------------------------------------------------------
-- Function find_id_dwidth
--
-- This function is used to find the data width of a target module. If the
-- target module exists, the data width is extracted from the input dwidth
-- array. If the module is not in the ID array, the default input is
-- returned. This function is needed to assign data port size constraints on
-- unconstrained port widths.
-----------------------------------------------------------------------------
function find_id_dwidth (id_array : INTEGER_ARRAY_TYPE;
dwidth_array: INTEGER_ARRAY_TYPE;
id : integer;
default : integer) return integer is
Variable id_present : Boolean := false;
Variable array_index : Integer := 0;
Variable dwidth : Integer := default;
begin
id_present := find_ard_id(id_array, id);
If (id_present) Then
array_index := get_id_index (id_array, id);
dwidth := dwidth_array(array_index);
else
null; -- use default input
End if;
Return (dwidth);
end function find_id_dwidth;
-----------------------------------------------------------------------------
-- Function cnt_ipif_id_blks
--
-- This function is used to detirmine the number of IPIF components specified
-- in the ARD ID Array. An integer is returned representing the number
-- of elements counted. User IDs are ignored in the counting process.
-----------------------------------------------------------------------------
function cnt_ipif_id_blks (id_array : INTEGER_ARRAY_TYPE)
return integer is
Variable blk_count : integer := 0;
Variable temp_id : integer;
begin
for array_index in 0 to id_array'length-1 loop
temp_id := id_array(array_index);
If (temp_id = IPIF_WRFIFO_DATA or
temp_id = IPIF_RDFIFO_DATA or
temp_id = IPIF_RST or
temp_id = IPIF_INTR or
temp_id = IPIF_DMA_SG or
temp_id = IPIF_SESR_SEAR
) Then -- IPIF block found
blk_count := blk_count+1;
else -- go to next loop iteration
null;
End if;
End loop;
return(blk_count);
end function cnt_ipif_id_blks;
-----------------------------------------------------------------------------
-- Function get_ipif_id_dbus_index
--
-- This function is used to detirmine the IPIF relative index of a given
-- ID value. User IDs are ignored in the index detirmination.
-----------------------------------------------------------------------------
function get_ipif_id_dbus_index (id_array : INTEGER_ARRAY_TYPE;
id : integer)
return integer is
Variable blk_index : integer := 0;
Variable temp_id : integer;
Variable id_found : Boolean := false;
begin
for array_index in 0 to id_array'length-1 loop
temp_id := id_array(array_index);
If (id_found) then
null;
elsif (temp_id = id) then
id_found := true;
elsif (temp_id = IPIF_WRFIFO_DATA or
temp_id = IPIF_RDFIFO_DATA or
temp_id = IPIF_RST or
temp_id = IPIF_INTR or
temp_id = IPIF_DMA_SG or
temp_id = IPIF_SESR_SEAR
) Then -- IPIF block found
blk_index := blk_index+1;
else -- user block so do nothing
null;
End if;
End loop;
return(blk_index);
end function get_ipif_id_dbus_index;
-- End of xst debug functions
--/////////////////////////////////////////////////////////////////////////////
------------------------------------------------------------------------------
-- Function: rebuild_slv32_array
--
-- Description:
-- This function takes an input slv32 array and rebuilds an output slv32
-- array composed of the first "num_valid_entry" elements from the input
-- array.
------------------------------------------------------------------------------
function rebuild_slv32_array (slv32_array : SLV32_ARRAY_TYPE;
num_valid_pairs : integer)
return SLV32_ARRAY_TYPE is
--Constants
constant num_elements : Integer := num_valid_pairs * 2;
-- Variables
variable temp_baseaddr32_array : SLV32_ARRAY_TYPE( 0 to num_elements-1);
begin
for array_index in 0 to num_elements-1 loop
temp_baseaddr32_array(array_index) := slv32_array(array_index);
end loop;
return(temp_baseaddr32_array);
end function rebuild_slv32_array;
------------------------------------------------------------------------------
-- Function: rebuild_slv64_array
--
-- Description:
-- This function takes an input slv64 array and rebuilds an output slv64
-- array composed of the first "num_valid_entry" elements from the input
-- array.
------------------------------------------------------------------------------
function rebuild_slv64_array (slv64_array : SLV64_ARRAY_TYPE;
num_valid_pairs : integer)
return SLV64_ARRAY_TYPE is
--Constants
constant num_elements : Integer := num_valid_pairs * 2;
-- Variables
variable temp_baseaddr64_array : SLV64_ARRAY_TYPE( 0 to num_elements-1);
begin
for array_index in 0 to num_elements-1 loop
temp_baseaddr64_array(array_index) := slv64_array(array_index);
end loop;
return(temp_baseaddr64_array);
end function rebuild_slv64_array;
------------------------------------------------------------------------------
-- Function: rebuild_int_array
--
-- Description:
-- This function takes an input integer array and rebuilds an output integer
-- array composed of the first "num_valid_entry" elements from the input
-- array.
------------------------------------------------------------------------------
function rebuild_int_array (int_array : INTEGER_ARRAY_TYPE;
num_valid_entry : integer)
return INTEGER_ARRAY_TYPE is
-- Variables
variable temp_int_array : INTEGER_ARRAY_TYPE( 0 to num_valid_entry-1);
begin
for array_index in 0 to num_valid_entry-1 loop
temp_int_array(array_index) := int_array(array_index);
end loop;
return(temp_int_array);
end function rebuild_int_array;
function bits_needed_for_vac(
fifo_present: boolean;
dependent_props : DEPENDENT_PROPS_TYPE
) return integer is
begin
if not fifo_present then
return 1; -- Zero would be better but leads to "0 to -1" null
-- ranges that are not handled by XST Flint or earlier
-- because of the negative index.
else
return
log2(1 + dependent_props(FIFO_CAPACITY_BITS) /
dependent_props(RD_WIDTH_BITS)
);
end if;
end function bits_needed_for_vac;
function bits_needed_for_occ(
fifo_present: boolean;
dependent_props : DEPENDENT_PROPS_TYPE
) return integer is
begin
if not fifo_present then
return 1; -- Zero would be better but leads to "0 to -1" null
-- ranges that are not handled by XST Flint or earlier
-- because of the negative index.
else
return
log2(1 + dependent_props(FIFO_CAPACITY_BITS) /
dependent_props(WR_WIDTH_BITS)
);
end if;
end function bits_needed_for_occ;
end package body ipif_pkg;
|
bsd-3-clause
|
masson2013/heterogeneous_hthreads
|
src/platforms/xilinx/smp3_opbhwti/design/pcores/opb_ipif_v2_00_h/hdl/vhdl/opb_ipif.vhd
|
3
|
77157
|
-------------------------------------------------------------------------------
-- $Id: opb_ipif.vhd,v 1.18 2004/11/23 01:04:03 jcanaris Exp $
-------------------------------------------------------------------------------
-- opb_ipif.vhd
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: opb_ipif.vhd
--
-- Description: This is the top level design file for the OPB IPIF.
-- It provides a standardized interface between the
-- IP and the OPB Bus. It also provides data transfer support
-- via DMA, Scatter/Gather, and fifo buffering.
--
--
-------------------------------------------------------------------------------
-- Structure:
--
--
-- opb_ipif.vhd
-- \
-- \-- reset_control.vhd
-- \ ipif_reset.vhd
-- \
-- \
-- \-- interrupt_control.vhd
-- \
-- \-- bus2ip_amux.vhd
-- \
-- \-- ip2bus_dmux.vhd
-- \ ip2bus_dmux.vhd
-- \
-- \-- ip2bus_srmux.vhd
-- \ ip2bus_srmux.vhd
-- \
-- \-- address_decoder.vhd
-- \
-- \-- slave_attachment.vhd
-- \
-- \-- ipif_steer
-- \
-- \-- master_attachment.vhd
-- \ mst_attach.vhd
-- \
-- \ dma_sg_pkg.vhd
-- \ dma_sg_cmp.vhd
-- \-- dma_sg.vhd
-- \ dma_sg_sim.vhd
-- \ srl_fifo.vhd
-- \ ctrl_reg.vhd
-- \ ld_arith_reg.vhd
-- \
-- \-- rdfifo.vhd
-- \ rpfifo_top.vhd
-- \ ipif_control_rd.vhd
-- \ rdpfifo_dp_cntl.vhd
-- \
-- \ dp512x32_v3_2_rden_ve.edn
-- \ or
-- \ dp512x32_v3_2_rden_vii.edn
-- \
-- \
-- \-- wrfifo.vhd
-- \ wpfifo_top.vhd
-- \ ipif_control_wr.vhd
-- \ wrpfifo_dp_cntl.vhd
-- \
-- \ dp512x32_v3_2_rden_ve.edn
-- \ or
-- \ dp512x32_v3_2_rden_vii.edn
--
--
-------------------------------------------------------------------------------
-- @BEGIN_CHANGELOG EDK_Gm_SP2
--
-- FPGA families qvirtex2, qrvirtex2 and virtex4 supported.
--
-- Fixed problem with Mn_BE generation for mastered reads when both DMA
-- and IP masters are present.
--
-- Fixed problem where local master write data could get driven to OPB
-- during a slave write.
--
-- Added IPIC timeout for the local read phase of locally mastered write
-- transactions.
--
-- Drive the low-order two Mn_Abus bits to match the numerically lowest
-- Mn_BE bit that is asserted.
--
-- @END_CHANGELOG
-------------------------------------------------------------------------------
-- Author: <Farrell Ostler, Mike Lovejoy, and Doug Thorpe>
--
-- History:
--
-- D. Thorpe Aug-16-2001 -- Version v1.22a
--
-- DET Aug-23-2001 -- no version change
-- - corrected some file header errors
-- - corrected some generic default values
--
-- DET Aug-29-2001 -- no version change
-- - corrected the spelling of the C_VIRTEX_II parameter
--
-- FO Sep-26-2001
-- - Adapted to the wrapper-removed, generic-adjusted
-- versions of slave_attachment and addr_decode generated
-- by AS.
--
-- ALS Sep-27-2001
-- - added ipif_pkg which contains log2 function
-- - changed the address widths of SRAM, WRFIFO, and RDFIFO to
-- log2 of their size
-- - changed the data widths of SRAM, WRFIFO, and RDFIFO to
-- represent the number of bits instead of the number of bytes
-- and made these constants set to the C_IPIF_DBUS_WIDTH generic
--
-- FO Oct-15-2001
-- - Simplified address calculations for generics.
-- - Removed dependency of arithmetic into msb to get past XST.
--
-- FO Oct-16-2001
-- - Fixed assertion checking low-order zeroes for C_DEV_BASEADDR.
--
-- FO Dec-03-2001
-- - Added a commented-out chipscope ILA at the bottom.
--
-- FO Jan-02-2002
-- - General cleanup
-- - Removal of un-needed comments.
-- - Elimination Bus_Reset_i in favor of Reset.
-- - Where possible made lower-level signal same as top-level
-- signal.
-- - Elimination of C_SL_ATT_ADDR_SEL_WIDTH parameter for sa.
--
-- FO Apr-08-2002
-- - v2.00a version; has
-- - Considerable signal renaming in ipif and submodules to
-- improve naming consistency and remove some synonymous
-- names.
-- - Rework of the generics:
-- - Address Range Definition (ARD) parameters
-- implement the notion of generalized address
-- ranges and properties.
-- - DMA_SG generics now allow n channels of any of the
-- four types.
-- - Several other generic changes, also. See current
-- generic set.
-- - Bus2IP_Reg_rdCE, Bus2IP_Reg_WrCE and Bus2IP_SRAM_CE
-- signals eliminated in favor of Bus2IP_CS, Bus2IP_CE,
-- Bus2IP_RdCE and Bus2IP_WrCE, which are the decode
-- signals for generalized Address Range Definitions.
-- - Addr_decode replaced by address_decode, which handles
-- the generalized address ranges.
-- - Revised interrupt_control module instantiated, allow
-- now for level interrrupts and general edge detect
-- interrupts. Along with original pulse-detect interrupt
-- signal type and true or complement polarity for
-- each type, there are now 6 kinds of interrupt signals
-- that can be specified for the IP2Bus_IntrEvent
-- signals.
-- - ipif_steer module added to allow for multiple IPIF
-- dwidth sizes.
--
-- FO Apr-08-2002 Synplify 6.2 workaround.
-- Removal of 'length and function calls
-- in component port declarations.
--
-- FO Jun-04-2002
-- - Added generic C_ARD_DEPENDENT_PROPS_ARRAY and signal
-- IP2Bus_PostedWrInh. The function associated with
-- the signal is not yet implemented, however.
--
-- FO Jun-06-2002
-- - Corrected WFIFO2IP_Occupancy and RFIFO2IP_Vacancy
-- to adjust their vector widths to the FIFO parameters
-- passed in through C_ARD_DEPENDENT_PROPS_ARRAY.
--
-- FO Jun-07-2002
-- - Corrected the various vacancy and occupancy signals
-- to be compatible with FIFO capacity and read and
-- write width parameters.
--
-- FO Jun-24-2002
-- - Added FIFO parameters for INCLUDE_PACKET_MODE
-- and INCLUDE_VACANCY.
-- - Implemented dynamic byte-enable capability.
--
-- FO Aug-08-2002
-- - Fixed to set C_VIRTEX_II generic for FIFOs to true when
-- C_FAMILY is virtex2p.
--
-- FLO (FO) Aug-12-2002
-- - Using bits_needed_for_vac and bits_needed_for_occ now
-- for vacancy and occupancy vecter-width calculations.
--
-- FLO Aug-29-2002
-- - Up to now, the OPB_IPIF implementation has had a
-- wrapper that mapped a handful of boolean generics to
-- integers used as booleans. This was to comply with
-- some CoreGen restrictions on generics. The wrapper
-- was opb_ipif.vhd and it wrapped the implementation
-- in ipif.vhd.
--
-- Now, leaving opb_ipif.vhd as the top-level interface, the
-- extra level is removed and ipif.vhd is subsumed into
-- opb_ipif.vhd. This includes replacing the opb_ipif.vhd
-- file header--of which this is a part--with the ipif.vhd
-- file header, edited to replace "ipif" by "opb_ipif".
--
-- FLO Sep-05-2002
-- - Added default values for input ports.
-- - Added signal OPB_timeout to the port list of the
-- instantiation of the slave_attachment.
--
-- ~~~~~~
-- FLO 09/10/02
-- ^^^^^^
-- Added port signal Bus2IP_LocalMstTrans. This signal is a qualifier
-- valid during any IPIC transfer. It is asserted during an IPIC
-- transfer if and only if the transfer is taking place as part of
-- a locally initiated master transaction. Local master transactions
-- can be initiated either by an IPIF DMA[SG] engine or a IP-core
-- master, if either or both are present. If there is no IPIC
-- transfer in progress, the value of Bus2IP_LocalMstTrans may be
-- arbitrary.
-- ~~~~~~
-- FLO 09/23/02
-- ^^^^^^
-- - Substituted the port signal Bus2IP_IPMstTrans for the
-- recently added Bus2IP_LocalMstTrans. The replaced signal
-- qualified the IPIC transaction as being due to either the
-- IP-core master or the DMA master. The new signal qualifies
-- the IPIC transaction as being due to the IP-core master, only.
--
-- - Added qualification by "not(Mstr_sel_ma)" to signals
-- Bus2IP_MstRetry, Bus2IP_MstTimeOut and Bus2IP_MstLastAck.
-- ~~~~~~
-- FLO 10/30/02
-- ^^^^^^
-- - Bus2IP_RdReq signal to the read fifo is gated off for the
-- cycle following the falling edge of opb_seqaddr. This is needed
-- because Bus2IP_RdReq was generalized to handle cases where
-- the IP2Bus_RdAck signal throttles and doesn't complete a read
-- on every cycle of a burst.
-- ~~~~~~
-- FLO 11/19/02
-- ^^^^^^
-- Added signal SA2MA_PostedWrInh, from slave_attachment to
-- master_attachment.
-- ~~~~~~
-- FLO 11/19/02
-- ^^^^^^
-- Added generic C_MASTER_ARB_MODEL, which allows for user-parameterized
-- arbitration behavior when there are both DMA and IP masters. Supports
-- fair, DMA-priority and IP-priority modes.
-- ~~~~~~
-- FLO 05/15/03
-- ^^^^^^
-- Now passing the C_ARD_ADDR_RANGE_ARRAY generic to the slave attachment.
-- ~~~~~~
-- FLO 05/18/03
-- ^^^^^^
-- Replaced the C_DMA_ALLOW_BURST parameter by C_DMA_BURST_SIZE.
-- This parameter can be set to 1 to disable burst or to some power
-- of two to enable DMA to use bursts of that size.
-- The default is for DMA to use bursts of 16.
-- Also added parameter C_DMA_SHORT_BURST_REMAINDER, which controls
-- whether DMA remainders are transferred as a short burst or as
-- a sequence of single transactions.
-- ~~~~~~
-- FO May-22-2003
-- ^^^^^^
-- - Fixed to set C_VIRTEX_II generic for FIFOs to true when
-- C_FAMILY is spartan3.
-- ~~~~~~
-- GAB April-28-2004
-- ^^^^^^
-- - Updated C_VIRTEX_II to support VIRTEX4, QVIRTEX2, and QRVIRTEX2
-- - Added change log
-- ~~~~~~
-- FLO 05/26/2004
-- ^^^^^^
-- - An IPIC read timeout function was added to the slave_attachment, its
-- use was added in the master attachment, and the connection of the
-- corresponding new signal SA2MA_TimeOut to master and slave
-- attachments is done here in opb_ipif. The timeout can detect a hung
-- IPIC read occurring as the slave attachment reads into its read
-- buffer in support of a local master write OPB transaction. When
-- SA2MA_TimeOut asserts, the master_attachment terminates the
-- local master transaction with Bus2IP_MstTimeOut. The timeout
-- function can be supressed by assertion of IP2Bus_ToutSup.
-- ~~~~~~
-- FLO 08/11/2004
-- ^^^^^^
-- Added signal MA2SA_RSRA (retained_state_retry_active).
-- Inhibit the slave attachement from reseting its count of transfers
-- left to complete a burst if in retained-state retry.
-- Fixes bug that could manifest as spurious writes in the local
-- device under a certain pattern of unrelated OPB activity.
-- ~~~~~~
-- FLO 08/20/2004
-- ^^^^^^
-- Fixed bug wherein unrelated OPB activity could cause an erroneous delay
-- in generation of the Bus2IP_DeviceSel during locally mastered write
-- transactions. An observed failure mode was the CE for a single IPIC read
-- being correspondingly delayed and, therefore, not being asserted
-- concurrently with the RdReq pulse.
-- ~~~~~~
-- FLO 08/25/2004
-- ^^^^^^
-- Changed bus2ip_rdreq_rfifo to be qualified by opb_busy. Because
-- opb_busy is only available in the slave_attachment, moved
-- generation bus2ip_rdreq_rfifo to the slave_attachment.
-- ~~~~~~
-- FLO 09/24/2004
-- ^^^^^^
-- -Added signal SA2MA_BufOccMinus1 and connected it to master and
-- slave attachments. This signal is used to help implement allowance of
-- arbitrary IPIC read retries when getting locally mastered write data
-- ready.
-- ~~~~~~
-- LCW Nov 8, 2004 -- updated for NCSim
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.Std_Logic_1164.all;
use ieee.STD_LOGIC_UNSIGNED.all;
library unisim;
use unisim.vcomponents.all;
library opb_ipif_v2_00_h;
library proc_common_v1_00_b;
use proc_common_v1_00_b.proc_common_pkg.log2;
use proc_common_v1_00_b.family.virtex2;
use proc_common_v1_00_b.family.derived;
library ipif_common_v1_00_d;
use ipif_common_v1_00_d.ipif_pkg.INTEGER_ARRAY_TYPE;
use ipif_common_v1_00_d.ipif_pkg.SLV64_ARRAY_TYPE;
use ipif_common_v1_00_d.ipif_pkg.IPIF_RST;
use ipif_common_v1_00_d.ipif_pkg.IPIF_INTR;
use ipif_common_v1_00_d.ipif_pkg.IPIF_DMA_SG;
use ipif_common_v1_00_d.ipif_pkg.IPIF_WRFIFO_DATA;
use ipif_common_v1_00_d.ipif_pkg.IPIF_WRFIFO_REG;
use ipif_common_v1_00_d.ipif_pkg.IPIF_RDFIFO_DATA;
use ipif_common_v1_00_d.ipif_pkg.IPIF_RDFIFO_REG;
use ipif_common_v1_00_d.ipif_pkg.USER_00;
use ipif_common_v1_00_d.ipif_pkg.calc_num_ce;
use ipif_common_v1_00_d.ipif_pkg.calc_start_ce_index;
use ipif_common_v1_00_d.ipif_pkg.find_ard_id;
use ipif_common_v1_00_d.ipif_pkg.get_id_index;
use ipif_common_v1_00_d.ipif_pkg.get_min_dwidth;
use ipif_common_v1_00_d.ipif_pkg.DEPENDENT_PROPS_ARRAY_TYPE;
use ipif_common_v1_00_d.ipif_pkg.FIFO_CAPACITY_BITS;
use ipif_common_v1_00_d.ipif_pkg.WR_WIDTH_BITS;
use ipif_common_v1_00_d.ipif_pkg.RD_WIDTH_BITS;
use ipif_common_v1_00_d.ipif_pkg.EXCLUDE_PACKET_MODE;
use ipif_common_v1_00_d.ipif_pkg.EXCLUDE_VACANCY;
use ipif_common_v1_00_d.ipif_pkg.bits_needed_for_vac;
use ipif_common_v1_00_d.ipif_pkg.bits_needed_for_occ;
use ipif_common_v1_00_d.ipif_pkg.get_id_index_iboe;
use ipif_common_v1_00_d.dma_sg_pkg.all;
use ipif_common_v1_00_d.dma_sg_cmp.all;
entity opb_ipif is
generic (
C_ARD_ID_ARRAY : INTEGER_ARRAY_TYPE
:= ( IPIF_RST, -- 2
USER_00 -- 100
);
C_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE
:= ( x"0000_0000_6000_0040", -- IPIF_RST
x"0000_0000_6000_0043",
--
x"0000_0000_6000_1100", -- USER_00
x"0000_0000_6000_11FF"
);
C_ARD_DWIDTH_ARRAY : INTEGER_ARRAY_TYPE
:= ( 32, -- IPIF_RST
32 -- USER_00
);
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE
:= ( 1, -- IPIF_RST
17 -- USER_00
);
C_ARD_DEPENDENT_PROPS_ARRAY : DEPENDENT_PROPS_ARRAY_TYPE
:= ( 0 => (others => 0),
1 => (others => 0)
);
-- Properties depending on the address range (AR) type.
--
-- AR Type Properties (use these index constants, de-
-- ------- ---------- fined in ipif_pkg, in aggregates).
--
-- IPIF_WRFIFO_DATA or FIFO_CAPACITY_BITS
-- IPIF_RDFIFO_DATA WR_WIDTH_BITS
-- RD_WIDTH_BITS
C_DEV_BLK_ID : INTEGER := 1;
-- Platform Builder Assiged Device ID number (unique
-- for each device)
C_DEV_MIR_ENABLE : integer := 0;
-- Used to Enable/Disable Module ID functions
C_DEV_BURST_ENABLE : INTEGER := 0;
-- Burst Enable for IPIF Interface
C_DEV_MAX_BURST_SIZE : INTEGER := 64;
-- Maximum burst size to be supported (in bytes)
C_INCLUDE_DEV_ISC : INTEGER := 1;
-- 'true' specifies that the full device interrupt
-- source controller structure will be included;
-- 'false' specifies that only the global interrupt
-- enable is present in the device interrupt source
-- controller and that the only source of interrupts
-- in the device is the IP interrupt source controller
C_INCLUDE_DEV_PENCODER : integer := 0;
-- 'true' will include the Device IID in the IPIF Interrupt
-- function
C_IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE :=
(
1, -- pass through (non-inverting)
2, -- pass through (inverting)
3, -- registered level (non-inverting)
4, -- registered level (inverting)
5, -- positive edge detect
6 -- negative edge detect
);
-- One entry for each IP interrupt signal, with the
-- signal type for each signal given by the value
-- in the corresponding position. (See above.)
C_IP_MASTER_PRESENT : integer := 0;
-- 'true' specifies that the IP has Bus Master capability
C_MASTER_ARB_MODEL : integer := 0;
-- Arbitration scheme if both DMA and IP masters are present.
-- 0:FAIR 1:DMA_PRIORITY 2:IP_PRIORITY
-----------------------------------------------------------------------------
-- The parameters with names starting with 'C_DMA' need only be specified if
-- one of the address ranges is for the optional DMA[SG] controller, i.e. one
-- range of type IPIF_DMA_SG is included in C_ARD_ID_ARRAY (see above).
-- If DMA[SG] is included, then the number of channels and the
-- parameterizeable properties of each Channel are specified in the arrays,
-- below.
-----------------------------------------------------------------------------
C_DMA_CHAN_TYPE_ARRAY : INTEGER_ARRAY_TYPE := (2,
3
);
-- One entry in the array for each channel, encoded as
-- 0 = simple DMA, 1 = simple sg, 2 = pkt tx SG, 3 = pkt rx SG
C_DMA_LENGTH_WIDTH_ARRAY : INTEGER_ARRAY_TYPE := (11,
11
);
-- One entry in the array for each channel.
-- Gives the number of bits needed to specify the maximum DMA transfer
-- length, in bytes, for the channel.
C_DMA_PKT_LEN_FIFO_ADDR_ARRAY : SLV64_ARRAY_TYPE := (x"00000000_00000000",
x"00000000_00000000"
);
-- One entry in the array for each channel.
-- If the channel type is 0 or 1, the value should be "zero".
-- If the channel type is 2 or 3 (packet channel),
-- the value should give the address of the packet-length FIFO associated
-- with the channel.
C_DMA_PKT_STAT_FIFO_ADDR_ARRAY : SLV64_ARRAY_TYPE :=(x"00000000_00000000",
x"00000000_00000000"
);
-- One entry in the array for each channel.
-- If the channel type is 0 or 1, the value should be "zero".
-- If the channel type is 2 or 3 (packet channel),
-- the value should give the address of the packet-status FIFO associated
-- with the channel.
C_DMA_INTR_COALESCE_ARRAY : INTEGER_ARRAY_TYPE :=(0,
0
);
-- One entry in the array for each channel.
-- If the channel type is 0 or 1, the value should be 0 for the
-- channel.
-- If the channel type is 2 or 3, the channel is a packet channel and
-- the value 1 specifies that interrupt-coalescing features are
-- to be implemented for the channel. The value 0 declines the features.
C_DMA_BURST_SIZE: integer := 16; -- Must be a power of 2
-- Gives the size of burst that DMA uses to tranfer data on the bus.
-- A value of one causes DMA to use single transactions (burst disabled).
C_DMA_SHORT_BURST_REMAINDER: integer := 0;
-- When 0, any DMA data remaining that is less than a burst size will be
-- transferred as a series of single transactions.
-- When 1, remaining data is tranferred as a short burst.
C_DMA_PACKET_WAIT_UNIT_NS : INTEGER := 1000000;
-- Gives the unit for timing pack-wait bounds for all channels
-- with interrupt coalescing. (Usually left at default value.);
-- Needs to be specified only if at least one channel is of type
-- 2 or 3 with interrupt coalescing and there is a need
-- to deviate from the nominal unit of 1 ms (for example,
-- to facilitate testing by simulation).
C_OPB_AWIDTH : INTEGER := 32;
-- width of OPB Address Bus (in bits)
C_OPB_DWIDTH : INTEGER := 32;
-- Width of the OPB Data Bus (in bits)
C_OPB_CLK_PERIOD_PS : INTEGER := 10000;
-- The period of the OPB Bus clock in ps (10000 = 10ns)
C_IPIF_DWIDTH : INTEGER := 32;
-- Set this equal to C_OPB_DWIDTH
C_FAMILY : string := "virtexe"
);
port (
OPB_ABus : in std_logic_vector(0 to C_OPB_AWIDTH - 1 ) := (others => '0');
OPB_DBus : in std_logic_vector(0 to C_OPB_DWIDTH - 1 ) := (others => '0');
Sln_DBus : out std_logic_vector(0 to C_OPB_DWIDTH - 1 );
Mn_ABus : out std_logic_vector(0 to C_OPB_AWIDTH - 1 );
IP2Bus_Addr : in std_logic_vector(0 to C_OPB_AWIDTH - 1 ) := (others => '0');
Bus2IP_Addr : out std_logic_vector(0 to C_OPB_AWIDTH - 1 );
Bus2IP_Data : out std_logic_vector(0 to C_IPIF_DWIDTH - 1 );
Bus2IP_RNW : out std_logic;
Bus2IP_CS : Out std_logic_vector(0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
Bus2IP_CE : out std_logic_vector(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
Bus2IP_RdCE : out std_logic_vector(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
Bus2IP_WrCE : out std_logic_vector(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
IP2Bus_Data : in std_logic_vector(0 to C_IPIF_DWIDTH - 1 ) := (others => '0');
IP2Bus_WrAck : in std_logic := '0';
IP2Bus_RdAck : in std_logic := '0';
IP2Bus_Retry : in std_logic := '0';
IP2Bus_Error : in std_logic := '0';
IP2Bus_ToutSup : in std_logic := '0';
IP2Bus_PostedWrInh : in std_logic := '0';
IP2DMA_RxLength_Empty : in std_logic := '0';
IP2DMA_RxStatus_Empty : in std_logic := '0';
IP2DMA_TxLength_Full : in std_logic := '0';
IP2DMA_TxStatus_Empty : in std_logic := '0';
IP2IP_Addr : in std_logic_vector(0 to C_OPB_AWIDTH - 1 )
:= (others => '0');
IP2RFIFO_Data : in std_logic_vector(0 to 31 ) := (others => '0');
IP2RFIFO_WrMark : in std_logic := '0';
IP2RFIFO_WrRelease : in std_logic := '0';
IP2RFIFO_WrReq : in std_logic := '0';
IP2RFIFO_WrRestore : in std_logic := '0';
IP2WFIFO_RdMark : in std_logic := '0';
IP2WFIFO_RdRelease : in std_logic := '0';
IP2WFIFO_RdReq : in std_logic := '0';
IP2WFIFO_RdRestore : in std_logic := '0';
IP2Bus_MstBE : in std_logic_vector(0 to C_OPB_DWIDTH/8 - 1 ) := (others => '0');
IP2Bus_MstWrReq : in std_logic := '0';
IP2Bus_MstRdReq : in std_logic := '0';
IP2Bus_MstBurst : in std_logic := '0';
IP2Bus_MstBusLock : in std_logic := '0';
Bus2IP_MstWrAck : out std_logic;
Bus2IP_MstRdAck : out std_logic;
Bus2IP_MstRetry : out std_logic;
Bus2IP_MstError : out std_logic;
Bus2IP_MstTimeOut : out std_logic;
Bus2IP_MstLastAck : out std_logic;
Bus2IP_BE : out std_logic_vector(0 to C_IPIF_DWIDTH/8 - 1 );
Bus2IP_WrReq : out std_logic;
Bus2IP_RdReq : out std_logic;
Bus2IP_IPMstTrans : out std_logic;
Bus2IP_Burst : out std_logic;
Mn_request : out std_logic;
Mn_busLock : out std_logic;
Mn_select : out std_logic;
Mn_RNW : out std_logic;
Mn_BE : out std_logic_vector(0 to C_OPB_DWIDTH/8 - 1 );
Mn_seqAddr : out std_logic;
OPB_MnGrant : in std_logic := '0';
OPB_xferAck : in std_logic := '0';
OPB_errAck : in std_logic := '0';
OPB_retry : in std_logic := '0';
OPB_timeout : in std_logic := '0';
Freeze : in std_logic := '0';
RFIFO2IP_AlmostFull : out std_logic;
RFIFO2IP_Full : out std_logic;
RFIFO2IP_Vacancy : out
std_logic_vector (
0 to
bits_needed_for_vac(
find_ard_id(C_ARD_ID_ARRAY, IPIF_RDFIFO_DATA),
C_ARD_DEPENDENT_PROPS_ARRAY(
get_id_index_iboe(C_ARD_ID_ARRAY, IPIF_RDFIFO_DATA)
)
) - 1
);
RFIFO2IP_WrAck : out std_logic;
OPB_select : in std_logic := '0';
OPB_RNW : in std_logic := '0';
OPB_seqAddr : in std_logic := '0';
OPB_BE : in std_logic_vector(0 to C_OPB_DWIDTH/8 - 1 ) := (others => '0');
Sln_xferAck : out std_logic;
Sln_errAck : out std_logic;
Sln_toutSup : out std_logic;
Sln_retry : out std_logic;
WFIFO2IP_AlmostEmpty : out std_logic;
WFIFO2IP_Data : out std_logic_vector(0 to 31 );
WFIFO2IP_Empty : out std_logic;
WFIFO2IP_Occupancy : out
std_logic_vector (
0 to
bits_needed_for_occ(
find_ard_id(C_ARD_ID_ARRAY, IPIF_WRFIFO_DATA),
C_ARD_DEPENDENT_PROPS_ARRAY(
get_id_index_iboe(C_ARD_ID_ARRAY, IPIF_WRFIFO_DATA)
)
) - 1
);
WFIFO2IP_RdAck : out std_logic;
Bus2IP_Clk : out std_logic;
Bus2IP_DMA_Ack : out std_logic;
Bus2IP_Freeze : out std_logic;
Bus2IP_Reset : out std_logic;
IP2Bus_Clk : in std_logic := '0';
IP2Bus_DMA_Req : in std_logic := '0';
IP2Bus_IntrEvent : in std_logic_vector(0 to C_IP_INTR_MODE_ARRAY'length-1 )
:= (others => '0');
IP2INTC_Irpt : out std_logic;
OPB_Clk : in std_logic := '0';
Reset : in std_logic := '0'
);
end opb_ipif;
library unisim;
use unisim.all;
library ieee;
use ieee.numeric_std.UNSIGNED;
use ieee.numeric_std."+";
architecture implementation of opb_ipif is
constant ZEROES : std_logic_vector(0 to 256) := (others => '0');
-- MIR Constants
constant IPIF_MAJOR_VERSION : INTEGER range 0 to 15 := 2;
-- set Major Version of this IPIF here (reflected in IPIF MIR)
-- Now set to Major Version 2 for v2.00d
constant IPIF_MINOR_VERSION : INTEGER range 0 to 127:= 0;
-- set Minor Version of this IPIF here (reflected in IPIF MIR)
-- Now set to 00
constant IPIF_REVISION : INTEGER := 7;
-- set Revision of this IPIF here (reflected in IPIF MIR)
-- 0 = a, 1 = b, 2 = c, etc.
constant IPIF_TYPE : INTEGER := 1;
-- set interface type for this IPIF here (reflected in IPIF MIR)
-- Always '1' for OPB ipif interface type
function num_CEs(ard_id: integer) return integer is
variable id_included: boolean;
begin
id_included := find_ard_id(C_ARD_ID_ARRAY, ard_id);
if id_included then
return C_ARD_NUM_CE_ARRAY(get_id_index(C_ARD_ID_ARRAY, ard_id));
else return 0;
end if;
end num_CEs;
type SLV_OF_BUS_SIZE is array(0 to C_OPB_AWIDTH-1) of std_logic;
function base_address(ard_id: integer)
return SLV_OF_BUS_SIZE is
variable result : SLV_OF_BUS_SIZE
:= (others => '0');
variable id_included: boolean;
variable ar_index: integer;
begin
id_included := find_ard_id(C_ARD_ID_ARRAY, ard_id);
ar_index := 2*get_id_index(C_ARD_ID_ARRAY, ard_id);
if id_included then
result := SLV_OF_BUS_SIZE(
C_ARD_ADDR_RANGE_ARRAY(ar_index)
( C_ARD_ADDR_RANGE_ARRAY(0)'length - C_OPB_AWIDTH
to C_ARD_ADDR_RANGE_ARRAY(0)'length - 1
)
)
;
end if;
return result;
end base_address;
function num_common_high_order_addr_bits(ara: SLV64_ARRAY_TYPE)
return integer is
variable n : integer := C_OPB_AWIDTH;
-- Maximum number of common high-order bits for
-- the ranges starting at an index less than i.
variable i, j: integer;
variable old_base: std_logic_vector(0 to C_OPB_AWIDTH-1)
:= ara(0)( ara(0)'length-C_OPB_AWIDTH
to ara(0)'length-1
);
variable new_base, new_high: std_logic_vector(0 to C_OPB_AWIDTH-1);
begin
i := 0;
while i < ara'length loop
new_base := ara(i )(ara(0)'length-C_OPB_AWIDTH to ara(0)'length-1);
new_high := ara(i+1)(ara(0)'length-C_OPB_AWIDTH to ara(0)'length-1);
j := 0;
while j < n -- Limited by earlier value.
and new_base(j) = old_base(j) -- High-order addr diff found
-- with a previous range.
and (new_base(j) xor new_high(j))='0' -- Addr-range boundary found
-- for current range.
loop
j := j+1;
end loop;
n := j;
i := i+2;
end loop;
return n;
end num_common_high_order_addr_bits;
-- Other constants
constant K_DEV_ADDR_DECODE_WIDTH
: integer
:= num_common_high_order_addr_bits(C_ARD_ADDR_RANGE_ARRAY);
constant LOW_ADDR_DECODE_WIDTH : INTEGER
:= C_OPB_AWIDTH - K_DEV_ADDR_DECODE_WIDTH;
constant LOGIC_LOW : std_logic := '0';
constant ZERO_ADDR_PREFIX
: std_logic_vector(0 to 64 - C_OPB_AWIDTH-1)
:= (others => '0');
constant RESET_PRESENT : boolean
:= find_ard_id(C_ARD_ID_ARRAY, IPIF_RST);
constant INTERRUPT_PRESENT : boolean
:= find_ard_id(C_ARD_ID_ARRAY, IPIF_INTR);
constant WRFIFO_PRESENT : boolean
:= find_ard_id(C_ARD_ID_ARRAY, IPIF_WRFIFO_REG)
and find_ard_id(C_ARD_ID_ARRAY, IPIF_WRFIFO_DATA);
constant RDFIFO_PRESENT : boolean
:= find_ard_id(C_ARD_ID_ARRAY, IPIF_RDFIFO_REG)
and find_ard_id(C_ARD_ID_ARRAY, IPIF_RDFIFO_DATA);
constant DMA_PRESENT : boolean
:= find_ard_id(C_ARD_ID_ARRAY, IPIF_DMA_SG);
constant INTERRUPT_REG_NUM : INTEGER := num_CEs(IPIF_INTR);
constant DMA_BASEADDR : std_logic_vector(0 to C_OPB_AWIDTH - 1 )
:= std_logic_vector(base_address(IPIF_DMA_SG));
constant DEV_IS_SLAVE_ONLY : BOOLEAN := not(DMA_PRESENT or
(C_IP_MASTER_PRESENT /= 0));
constant VIRTEX_II : boolean := derived(C_FAMILY, virtex2);
--constant DMA_USE_BURST : BOOLEAN := (C_DMA_ALLOW_BURST /= 0) and
-- (C_DEV_BURST_ENABLE /= 0);
function gate_burst_size(bool: boolean; posit: integer) return positive is
begin
if bool then return posit; else return 1; end if;
end gate_burst_size;
--
constant DMA_BURST_SIZE : positive := gate_burst_size(C_DEV_BURST_ENABLE=1,
C_DMA_BURST_SIZE);
constant NUM_CE : integer := calc_num_ce(C_ARD_NUM_CE_ARRAY);
-- signal used as a constant (when constant fails to be a globally
-- static expression).
signal CONST_ALL_IP_BYTES_ENABLED :
std_logic_vector(0 to C_IPIF_DWIDTH/8 -1) := (others => '1');
-- Signal declarations
signal Addr_Cntr_ClkEN : std_logic;
signal Addr_Sel : std_logic_vector(0 to 1 );
signal Bus2IP_Addr_i : std_logic_vector(0 to C_OPB_AWIDTH - 1 );
signal Bus2IP_Addr_sa : std_logic_vector(0 to C_OPB_AWIDTH - 1 );
signal Bus2IP_BE_sa : std_logic_vector(0 to C_IPIF_DWIDTH/8 - 1 );
signal Bus2IP_BE_amx : std_logic_vector(0 to C_IPIF_DWIDTH/8 - 1 );
signal Bus2IP_BE_i : std_logic_vector(0 to C_IPIF_DWIDTH/8 - 1 );
signal Bus2IP_Burst_i : std_logic;
signal Bus2IP_Clk_i : std_logic;
signal Bus2IP_Data_sa : std_logic_vector(0 to C_OPB_DWIDTH - 1 );
signal Bus2IP_Data_i : std_logic_vector(0 to C_OPB_DWIDTH - 1 );
signal Bus2IP_Freeze_i : std_logic;
signal Bus2IP_MstError_i : std_logic;
signal Bus2IP_MstLastAck_i : std_logic;
signal Bus2IP_MstRdAck_ma : std_logic;
signal Bus2IP_MstRetry_i : std_logic;
signal Bus2IP_MstTimeOut_i : std_logic;
signal Bus2IP_MstWrAck_ma : std_logic;
signal Bus2IP_DeviceSel : std_logic;
signal Bus2IP_RdReq_i : std_logic;
signal Bus2IP_Reset_i : std_logic;
signal Bus2IP_RNW_i : std_logic;
signal Bus2IP_WrReq_i : std_logic;
signal Bus_MnGrant : std_logic;
signal const_zero : std_logic := '0';
signal DMA2Bus_Addr : std_logic_vector(0 to C_OPB_AWIDTH - 1 );
signal DMA2Bus_Data : std_logic_vector(0 to C_OPB_DWIDTH - 1 );
signal DMA2Intr_Intr : std_logic_vector(0 to 1 );
signal DMA2IP_Addr : std_logic_vector(0 to C_OPB_AWIDTH - 1 );
signal DMA2Bus_MstBE : std_logic_vector(0 to C_OPB_DWIDTH/8 - 1 );
signal DMA2Bus_MstNum : STD_LOGIC_VECTOR(0 to
log2(C_DEV_MAX_BURST_SIZE/4+1)-1);
signal DMA2Bus_MstBurst : std_logic;
signal DMA2Bus_MstBusLock : std_logic;
signal DMA2Bus_MstRdReq : std_logic;
signal DMA2Bus_MstWrReq : std_logic;
signal DMA2Bus_Error : std_logic;
signal DMA2Bus_RdAck : std_logic;
signal DMA2Bus_Retry : std_logic;
signal DMA2Bus_ToutSup : std_logic;
signal DMA2Bus_WrAck : std_logic;
signal Intr2Bus_DBus : std_logic_vector(0 to C_OPB_DWIDTH - 1 );
signal Intr2Bus_DevIntr : std_logic;
signal Intr2Bus_Error : std_logic;
signal Intr2Bus_RdAck : std_logic;
signal Intr2Bus_Retry : std_logic;
signal Intr2Bus_ToutSup : std_logic;
signal Intr2Bus_WrAck : std_logic;
signal IP2Bus_Data_mx : std_logic_vector(0 to C_OPB_DWIDTH - 1 );
signal IP2Bus_Data_steer : std_logic_vector(0 to C_OPB_DWIDTH - 1 );
signal IP2Bus_Error_mx : std_logic;
signal IP2Bus_RdAck_mx : std_logic;
signal IP2Bus_Retry_mx : std_logic;
signal IP2Bus_ToutSup_mx : std_logic;
signal IP2Bus_WrAck_mx : std_logic;
signal IPIF_Lvl_Interrupts : std_logic_vector(0 to 3 );
signal IPIF_Reg_Interrupts : std_logic_vector(0 to 1 );
signal MA2SA_Num : std_logic_vector(0 to log2(C_DEV_MAX_BURST_SIZE/4+1)-1);
signal MA2SA_Rd : std_logic;
signal MA2SA_Select : std_logic;
signal MA2SA_XferAck : std_logic;
signal MA2SA_Retry : std_logic;
signal MA2SA_RSRA : std_logic;
signal Mstr_sel_ma : std_logic;
signal RdFIFO2Bus_Data : std_logic_vector(0 to C_OPB_DWIDTH - 1 );
signal RdFIFO2Intr_DeadLock : std_logic;
signal Reset2Bus_DBus : std_logic_vector(0 to C_OPB_DWIDTH - 1 );
signal RFIFO2DMA_AlmostEmpty : std_logic;
signal RFIFO2DMA_Empty : std_logic;
signal RFIFO2DMA_Occupancy :
std_logic_vector (
0 to
bits_needed_for_occ(
find_ard_id(C_ARD_ID_ARRAY, IPIF_RDFIFO_DATA),
C_ARD_DEPENDENT_PROPS_ARRAY(
get_id_index_iboe(C_ARD_ID_ARRAY, IPIF_RDFIFO_DATA)
)
) - 1
);
signal RFIFO_Error : std_logic;
signal RFIFO_RdAck : std_logic;
signal RFIFO_Retry : std_logic;
signal RFIFO_ToutSup : std_logic;
signal RFIFO_WrAck : std_logic;
signal Rst2Bus_Error : std_logic;
signal Rst2Bus_RdAck : std_logic;
signal Rst2Bus_Retry : std_logic;
signal Rst2Bus_ToutSup : std_logic;
signal Rst2Bus_WrAck : std_logic;
signal SA2MA_RdRdy : std_logic;
signal SA2MA_WrAck : std_ulogic;
signal SA2MA_Retry : std_logic;
signal SA2MA_Error : std_logic;
signal SA2MA_FifoRd: std_logic;
signal SA2MA_FifoWr: std_logic;
signal SA2MA_FifoBu: std_logic;
signal SA2MA_PostedWrInh: std_logic;
signal SA2MA_TimeOut: std_logic;
signal SA2MA_BufOccMinus1 : std_logic_vector(0 to 4);
signal WFIFO2DMA_AlmostFull : std_logic;
signal WFIFO2DMA_Full : std_logic;
signal WFIFO2DMA_vacancy :
std_logic_vector (
0 to
bits_needed_for_vac(
find_ard_id(C_ARD_ID_ARRAY, IPIF_WRFIFO_DATA),
C_ARD_DEPENDENT_PROPS_ARRAY(
get_id_index_iboe(C_ARD_ID_ARRAY, IPIF_WRFIFO_DATA)
)
) - 1
);
signal WFIFO_Error : std_logic;
signal WFIFO_RdAck : std_logic;
signal WFIFO_Retry : std_logic;
signal WFIFO_ToutSup : std_logic;
signal WFIFO_WrAck : std_logic;
signal WrFIFO2Bus_Data : std_logic_vector(0 to C_OPB_DWIDTH - 1 );
signal WrFIFO2Intr_DeadLock : std_logic;
signal CS_Out : std_logic_vector(0 to (C_ARD_ADDR_RANGE_ARRAY'length)/2 - 1);
signal CE_Out : std_logic_vector(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
signal RdCE_Out : std_logic_vector(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
signal WrCE_Out : std_logic_vector(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
signal cs_dwidth: std_logic_vector(0 to 2);
signal bus2ip_localmsttrans: std_logic;
signal devicesel_inh_opb : std_logic;
signal devicesel_inh_mstr : std_logic;
signal bus2ip_rdreq_rfifo: std_logic;
-------------------------------------------------------------------------------
-- components
constant NUM_CE_NEEDED : integer := calc_num_ce(C_ARD_NUM_CE_ARRAY);
constant NUM_CS_NEEDED : integer := C_ARD_ADDR_RANGE_ARRAY'LENGTH/2;
constant NUM_IP_INTR_SIGS : integer := C_IP_INTR_MODE_ARRAY'length;
-------------------------------------------------------------------------------
-- Instantiate the components
-------------------------------------------------------------------------------
begin
-- Perform consistency checks
-- synthesis translate_off
-- Any parameter consistency checks should be implemented here.
-- synthesis translate_on
------------------------------------------------------------------------------
INCLUDE_MASTER : if (DEV_IS_SLAVE_ONLY = false) generate
I_MASTER_ATTACHMENT: entity opb_ipif_v2_00_h.master_attachment
generic map (C_OPB_ABUS_WIDTH => C_OPB_AWIDTH,
C_OPB_DBUS_WIDTH => C_OPB_DWIDTH,
C_MA2SA_NUM_WIDTH => log2(C_DEV_MAX_BURST_SIZE/4 + 1),
C_DMA_ONLY => DMA_PRESENT and not (C_IP_MASTER_PRESENT /= 0),
C_IP_MSTR_ONLY => not DMA_PRESENT and (C_IP_MASTER_PRESENT /= 0),
C_MASTER_ARB_MODEL => C_MASTER_ARB_MODEL)
port map (
Reset => Reset,
--OPB ports
OPB_Clk => Bus2IP_Clk_i,
OPB_MnGrant => OPB_MnGrant,
OPB_xferAck => OPB_xferAck,
OPB_errAck => OPB_errAck,
OPB_timeout => OPB_timeout,
OPB_retry => OPB_retry,
--Master Attachment to OPB ports
Mn_request => Mn_request,
Mn_select => Mn_select,
Mn_RNW => Mn_RNW,
Mn_seqAddr => Mn_seqAddr,
Mn_busLock => Mn_busLock,
Mn_BE => Mn_BE,
Mn_ABus => Mn_ABus,
--Master Attachment to SA ports
Bus_MnGrant => Bus_MnGrant,
MA2SA_Select => MA2SA_Select,
MA2SA_XferAck => MA2SA_XferAck,
MA2SA_Retry => MA2SA_Retry,
MA2SA_RSRA => MA2SA_RSRA,
MA2SA_Rd => MA2SA_Rd,
MA2SA_Num => MA2SA_Num,
SA2MA_RdRdy => SA2MA_RdRdy,
SA2MA_WrAck => SA2MA_WrAck,
SA2MA_Retry => SA2MA_Retry,
SA2MA_Error => SA2MA_Error,
SA2MA_FifoRd => SA2MA_FifoRd,
SA2MA_FifoWr => SA2MA_FifoWr,
SA2MA_FifoBu => SA2MA_FifoBu,
SA2MA_PostedWrInh => SA2MA_PostedWrInh,
SA2MA_TimeOut => SA2MA_TimeOut,
SA2MA_BufOccMinus1 => SA2MA_BufOccMinus1,
--Master Attachment from IP ports
Mstr_sel_ma => Mstr_sel_ma,
--Master Attachment from IP ports
IP2Bus_Addr => IP2Bus_Addr,
IP2Bus_MstBE => IP2Bus_MstBE,
IP2Bus_MstWrReq => IP2Bus_MstWrReq,
IP2Bus_MstRdReq => IP2Bus_MstRdReq,
IP2Bus_MstBurst => IP2Bus_MstBurst,
IP2Bus_MstBusLock => IP2Bus_MstBusLock,
--Master Attachment to IP ports
Bus2IP_MstWrAck_ma => Bus2IP_MstWrAck_ma,
Bus2IP_MstRdAck_ma => Bus2IP_MstRdAck_ma,
Bus2IP_MstRetry => Bus2IP_MstRetry_i,
Bus2IP_MstError => Bus2IP_MstError_i,
Bus2IP_MstTimeOut => Bus2IP_MstTimeOut_i,
Bus2IP_MstLastAck => Bus2IP_MstLastAck_i,
--Master Attachment from DMA ports
DMA2Bus_Addr => DMA2Bus_Addr,
DMA2Bus_MstBE => DMA2Bus_MstBE,
DMA2Bus_MstWrReq => DMA2Bus_MstWrReq,
DMA2Bus_MstRdReq => DMA2Bus_MstRdReq,
DMA2Bus_MstNum => DMA2Bus_MstNum,
DMA2Bus_MstBurst => DMA2Bus_MstBurst,
DMA2Bus_MstBusLock => DMA2Bus_MstBusLock );
end generate INCLUDE_MASTER;
REMOVE_MASTER : if (DEV_IS_SLAVE_ONLY = true) generate
Bus2IP_MstError_i <= '0';
Bus2IP_MstLastAck_i <= '0';
Bus2IP_MstRdAck_ma <= '0';
Bus2IP_MstRetry_i <= '0';
Bus2IP_MstTimeOut_i <= '0';
Bus2IP_MstWrAck_ma <= '0';
Bus_MnGrant <= '0';
MA2SA_Num <= (others => '0');
MA2SA_Rd <= '0';
MA2SA_Select <= '0';
MA2SA_XferAck <= '0';
MA2SA_Retry <= '0';
MA2SA_RSRA <= '0';
Mn_ABus <= (others => '0');
Mn_BE <= (others => '0');
Mn_busLock <= '0';
Mn_request <= '0';
Mn_RNW <= '0';
Mn_select <= '0';
Mn_seqAddr <= '0';
Mstr_sel_ma <= '0';
end generate REMOVE_MASTER;
------------------------------------------------------------------------------
I_ADDRESS_DECODER: entity opb_ipif_v2_00_h.address_decoder
generic map (
C_BUS_AWIDTH => LOW_ADDR_DECODE_WIDTH,
C_USE_REG_OUTPUTS => true,
C_ARD_ADDR_RANGE_ARRAY => C_ARD_ADDR_RANGE_ARRAY,
C_ARD_DWIDTH_ARRAY => C_ARD_DWIDTH_ARRAY,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY
)
port map (
Bus_clk => Bus2IP_Clk_i,
Bus_rst => Reset,
Address_In => Bus2IP_Addr_i( C_OPB_AWIDTH-LOW_ADDR_DECODE_WIDTH
to C_OPB_AWIDTH-1
),
Address_Valid => Bus2IP_DeviceSel,
Bus_RNW => Bus2IP_RNW_i,
IP2Bus_RdAck_mx => IP2Bus_RdAck_mx,
IP2Bus_WrAck_mx => IP2Bus_WrAck_mx,
Bus2IP_Burst => Bus2IP_Burst_i,
Addr_Match => open,
CS_Out => CS_Out,
CS_Size => cs_dwidth,
CE_Out => CE_Out,
RdCE_Out => RdCE_Out,
WrCE_Out => WrCE_Out,
Devicesel_inh_opb => devicesel_inh_opb,
Devicesel_inh_mstr => devicesel_inh_mstr
);
Bus2IP_CS <= CS_Out;
Bus2IP_CE <= CE_Out;
Bus2IP_RdCE <= RdCE_Out;
Bus2IP_WrCE <= WrCE_Out;
I_IP2BUS_SRMUX: entity opb_ipif_v2_00_h.ip2bus_srmux_blk
port map (
DMA2Bus_Error => DMA2Bus_Error,
DMA2Bus_RdAck => DMA2Bus_RdAck,
DMA2Bus_Retry => DMA2Bus_Retry,
DMA2Bus_ToutSup => DMA2Bus_ToutSup,
DMA2Bus_WrAck => DMA2Bus_WrAck,
Intr2Bus_Error => Intr2Bus_Error,
Intr2Bus_RdAck => Intr2Bus_RdAck,
Intr2Bus_Retry => Intr2Bus_Retry,
Intr2Bus_ToutSup => Intr2Bus_ToutSup,
Intr2Bus_WrAck => Intr2Bus_WrAck,
IP2Bus_Error => IP2Bus_Error,
IP2Bus_Error_mx => IP2Bus_Error_mx,
IP2Bus_RdAck => IP2Bus_RdAck,
IP2Bus_RdAck_mx => IP2Bus_RdAck_mx,
IP2Bus_Retry => IP2Bus_Retry,
IP2Bus_Retry_mx => IP2Bus_Retry_mx,
IP2Bus_ToutSup => IP2Bus_ToutSup,
IP2Bus_ToutSup_mx => IP2Bus_ToutSup_mx,
IP2Bus_WrAck => IP2Bus_WrAck,
IP2Bus_WrAck_mx => IP2Bus_WrAck_mx,
RFIFO_Error => RFIFO_Error,
RFIFO_RdAck => RFIFO_RdAck,
RFIFO_Retry => RFIFO_Retry,
RFIFO_ToutSup => RFIFO_ToutSup,
RFIFO_WrAck => RFIFO_WrAck,
Rst2Bus_Error => Rst2Bus_Error,
Rst2Bus_RdAck => Rst2Bus_RdAck,
Rst2Bus_Retry => Rst2Bus_Retry,
Rst2Bus_ToutSup => Rst2Bus_ToutSup,
Rst2Bus_WrAck => Rst2Bus_WrAck,
WFIFO_Error => WFIFO_Error,
WFIFO_RdAck => WFIFO_RdAck,
WFIFO_Retry => WFIFO_Retry,
WFIFO_ToutSup => WFIFO_ToutSup,
WFIFO_WrAck => WFIFO_WrAck);
I_BUS2IP_AMUX: entity opb_ipif_v2_00_h.bus2ip_amux
generic map (
C_IPIF_ABUS_WIDTH => C_OPB_AWIDTH,
C_IPIF_DBUS_WIDTH => C_IPIF_DWIDTH)
port map (
Bus2IP_Reset_i => Reset,
Bus2IP_Clk_i => Bus2IP_Clk_i,
Mstr_sel_ma => Mstr_sel_ma,
Addr_Cntr_ClkEN => Addr_Cntr_ClkEN,
Addr_Sel => Addr_Sel,
Bus2IP_Addr_sa => Bus2IP_Addr_sa,
IP2IP_Addr => IP2IP_Addr,
DMA2IP_Addr => DMA2IP_Addr,
Bus2IP_Addr_i => Bus2IP_Addr_i,
Bus2IP_BE_sa => Bus2IP_BE_sa,
IP2IP_BE => CONST_ALL_IP_BYTES_ENABLED,
DMA2IP_BE => CONST_ALL_IP_BYTES_ENABLED,
Bus2IP_BE_i => Bus2IP_BE_amx
);
I_IP2BUS_DMUX: entity opb_ipif_v2_00_h.ip2bus_dmux_blk
generic map (C_DBUS_WIDTH => C_OPB_DWIDTH)
port map (
DMA2Bus_Data => DMA2Bus_Data(0 to C_OPB_DWIDTH - 1),
Intr2Bus_DBus => Intr2Bus_DBus(0 to C_OPB_DWIDTH - 1),
IP2Bus_Data => IP2Bus_Data(0 to C_IPIF_DWIDTH - 1),
IP2Bus_Data_mx => IP2Bus_Data_mx(0 to C_OPB_DWIDTH - 1),
Reset2Bus_Data => Reset2Bus_DBus(0 to C_OPB_DWIDTH - 1),
RFIFO2Bus_Data => RdFIFO2Bus_Data(0 to C_OPB_DWIDTH - 1),
WFIFO2Bus_Data => WrFIFO2Bus_Data(0 to C_OPB_DWIDTH - 1));
I_SLAVE_ATTACHMENT: entity opb_ipif_v2_00_h.slave_attachment
generic map (
C_OPB_ABUS_WIDTH => C_OPB_AWIDTH,
C_OPB_DBUS_WIDTH => C_OPB_DWIDTH,
C_IPIF_ABUS_WIDTH => C_OPB_AWIDTH,
C_IPIF_DBUS_WIDTH => C_IPIF_DWIDTH,
C_DEV_ADDR_DECODE_WIDTH => K_DEV_ADDR_DECODE_WIDTH,
C_DEV_BASEADDR => C_ARD_ADDR_RANGE_ARRAY(0)
( C_ARD_ADDR_RANGE_ARRAY(0)'length
- C_OPB_AWIDTH
to C_ARD_ADDR_RANGE_ARRAY(0)'length -1
), -- Any baseaddr from array will serve to
-- supply the K_DEV_ADDR_DECODE_WIDTH
-- high-order bits.
C_DEV_BURST_ENABLE => (C_DEV_BURST_ENABLE /= 0),
C_DEV_IS_SLAVE_ONLY => DEV_IS_SLAVE_ONLY,
C_MA2SA_NUM_WIDTH => log2(C_DEV_MAX_BURST_SIZE/4 + 1),
C_ARD_ADDR_RANGE_ARRAY => C_ARD_ADDR_RANGE_ARRAY
)
port map (
Reset => Reset,
OPB_Clk => Bus2IP_Clk_i,
OPB_select => OPB_select,
OPB_RNW => OPB_RNW,
OPB_SeqAddr => OPB_SeqAddr,
OPB_BE => OPB_BE(0 to C_OPB_DWIDTH/8 - 1),
OPB_ABus => OPB_ABus(0 to C_OPB_AWIDTH - 1),
OPB_DBus => OPB_DBus(0 to C_OPB_DWIDTH - 1),
OPB_timeout => OPB_timeout,
Sln_DBus => Sln_DBus(0 to C_OPB_DWIDTH - 1),
Sln_xferAck => Sln_xferAck,
Sln_errAck => Sln_errAck,
Sln_toutSup => Sln_toutSup,
Sln_retry => Sln_retry,
Bus_MnGrant => Bus_MnGrant,
MA2SA_Select => MA2SA_Select,
MA2SA_XferAck => MA2SA_XferAck,
MA2SA_Retry => MA2SA_Retry,
MA2SA_RSRA => MA2SA_RSRA,
MA2SA_Rd => MA2SA_Rd,
MA2SA_Num => MA2SA_Num,
SA2MA_RdRdy => SA2MA_RdRdy,
SA2MA_WrAck => SA2MA_WrAck,
SA2MA_Retry => SA2MA_Retry,
SA2MA_Error => SA2MA_Error,
SA2MA_FifoRd => SA2MA_FifoRd,
SA2MA_FifoWr => SA2MA_FifoWr,
SA2MA_FifoBu => SA2MA_FifoBu,
SA2MA_PostedWrInh => SA2MA_PostedWrInh,
SA2MA_TimeOut => SA2MA_TimeOut,
SA2MA_BufOccMinus1 => SA2MA_BufOccMinus1,
Addr_Sel => Addr_Sel(0 to 1),
Addr_Cntr_ClkEn => Addr_Cntr_ClkEN,
Bus2IP_Burst => Bus2IP_Burst_i ,
Bus2IP_RNW => Bus2IP_RNW_i ,
Bus2IP_BE_sa => Bus2IP_BE_sa(0 to C_IPIF_DWIDTH/8 - 1),
Bus2IP_Addr_sa => Bus2IP_Addr_sa,
Bus2IP_Data => Bus2IP_Data_sa(0 to C_IPIF_DWIDTH - 1),
Bus2IP_DeviceSel=> Bus2IP_DeviceSel,
Bus2IP_WrReq => Bus2IP_WrReq_i,
Bus2IP_RdReq => Bus2IP_RdReq_i,
Bus2IP_RdReq_rfifo => bus2ip_rdreq_rfifo,
Bus2IP_LocalMstTrans => bus2ip_localmsttrans,
IP2Bus_Data_mx => IP2Bus_Data_steer(0 to C_IPIF_DWIDTH - 1),
IP2Bus_WrAck_mx => IP2Bus_WrAck_mx,
IP2Bus_RdAck_mx => IP2Bus_RdAck_mx,
IP2Bus_Error_mx => IP2Bus_Error_mx,
IP2Bus_ToutSup_mx => IP2Bus_ToutSup_mx,
IP2Bus_Retry_mx => IP2Bus_Retry_mx,
IP2Bus_PostedWrInh => IP2Bus_PostedWrInh,
Devicesel_inh_opb_out => devicesel_inh_opb,
Devicesel_inh_mstr_out => devicesel_inh_mstr
);
Bus2IP_IPMstTrans <= bus2ip_localmsttrans and not(Mstr_sel_ma);
I_IPIF_STEER : entity ipif_common_v1_00_d.IPIF_Steer
generic map (
C_DWIDTH => C_OPB_DWIDTH,
C_SMALLEST => get_min_dwidth(C_ARD_DWIDTH_ARRAY),
C_AWIDTH => C_OPB_AWIDTH
)
port map (
Wr_Data_In => Bus2IP_Data_sa, -- in std_logic_vector(0 to C_DWIDTH-1)
Rd_Data_In => IP2Bus_Data_mx, -- in std_logic_vector(0 to C_DWIDTH-1)
Addr => Bus2IP_Addr_i, -- in std_logic_vector(0 to C_AWIDTH-1)
BE_In => Bus2IP_BE_amx, -- in std_logic_vector(0 to C_DWIDTH/8-1)
Decode_size => cs_dwidth, -- in std_logic_vector(0 to 2)
Wr_Data_Out => Bus2IP_Data_i, -- out std_logic_vector(0 to C_DWIDTH-1)
Rd_Data_Out => IP2Bus_Data_steer, -- out std_logic_vector(0 to C_DWIDTH-1)
BE_Out => Bus2IP_BE_i -- out std_logic_vector(0 to C_DWIDTH/8-1)
);
--------------------------------------------------------------------------------
INCLUDE_RESET : if (RESET_PRESENT) generate
Constant RESET_NAME_INDEX : integer := get_id_index(
C_ARD_ID_ARRAY,
IPIF_RST
);
Constant RESET_REG_CE_INDEX : integer := calc_start_ce_index(
C_ARD_NUM_CE_ARRAY,
RESET_NAME_INDEX
);
begin
I_RESET_CONTROL: entity opb_ipif_v2_00_h.reset_control
generic map (C_IPIF_MIR_ENABLE => (C_DEV_MIR_ENABLE /= 0),
C_IPIF_TYPE => IPIF_TYPE,
C_IPIF_BLK_ID => C_DEV_BLK_ID,
C_IPIF_REVISION => IPIF_REVISION,
C_IPIF_MINOR_VERSION => IPIF_MINOR_VERSION,
C_IPIF_MAJOR_VERSION => IPIF_MAJOR_VERSION,
C_OPB_DBUS_WIDTH => C_OPB_DWIDTH)
port map (
Bus2IP_Clk_i => Bus2IP_Clk_i,
Bus_DBus => Bus2IP_Data_i(0 to C_OPB_DWIDTH - 1),
IP_Reset_RdCE => RdCE_Out(RESET_REG_CE_INDEX),
IP_Reset_WrCE => WrCE_Out(RESET_REG_CE_INDEX),
Reset => Reset,
Reset2Bus_DBus => Reset2Bus_DBus(0 to C_OPB_DWIDTH - 1),
Reset2Bus_Error => Rst2Bus_Error,
Reset2Bus_RdAck => Rst2Bus_RdAck,
Reset2Bus_Retry => Rst2Bus_Retry,
Reset2Bus_ToutSup => Rst2Bus_ToutSup,
Reset2Bus_WrAck => Rst2Bus_WrAck,
Reset2IP_Reset => bus2ip_reset_i);
end generate INCLUDE_RESET;
REMOVE_RESET : if (not RESET_PRESENT) generate
Reset2Bus_DBus <= (others => '0') ;
Rst2Bus_Error <= '0';
Rst2Bus_RdAck <= '0';
Rst2Bus_Retry <= '0';
Rst2Bus_ToutSup <= '0';
Rst2Bus_WrAck <= '0';
Bus2IP_Reset_i <= Reset; -- No sw reset capability since
-- reset_control is excluded.
end generate REMOVE_RESET;
-------------------------------------------------------------------------------
INCLUDE_INTERRUPT : if (INTERRUPT_PRESENT) generate
Constant INDEX : integer := get_id_index(C_ARD_ID_ARRAY,IPIF_INTR);
Constant CE_INDEX : integer := calc_start_ce_index(C_ARD_NUM_CE_ARRAY,
INDEX);
begin
I_INTERRUPT_CONTROL: entity ipif_common_v1_00_d.interrupt_control
generic map (C_INTERRUPT_REG_NUM => INTERRUPT_REG_NUM,
C_NUM_IPIF_IRPT_SRC => 4,
C_IP_INTR_MODE_ARRAY => C_IP_INTR_MODE_ARRAY,
C_INCLUDE_DEV_PENCODER => (C_INCLUDE_DEV_PENCODER /= 0) and
(C_INCLUDE_DEV_ISC /= 0),
C_INCLUDE_DEV_ISC => (C_INCLUDE_DEV_ISC /= 0),
C_IRPT_DBUS_WIDTH => C_IPIF_DWIDTH)
port map (
Bus2IP_Clk_i => Bus2IP_Clk_i,
Bus2IP_Data_sa => Bus2IP_Data_i(0 to C_OPB_DWIDTH - 1),
Bus2IP_RdReq_sa => Bus2IP_RdReq_i,
Bus2IP_Reset_i => Bus2IP_Reset_i,
Bus2IP_WrReq_sa => Bus2IP_WrReq_i,
Interrupt_RdCE => RdCE_Out(CE_INDEX to CE_INDEX+INTERRUPT_REG_NUM - 1),
Interrupt_WrCE => WrCE_Out(CE_INDEX to CE_INDEX+INTERRUPT_REG_NUM - 1),
Intr2Bus_DBus => Intr2Bus_DBus(0 to C_OPB_DWIDTH - 1),
Intr2Bus_DevIntr => Intr2Bus_DevIntr,
Intr2Bus_Error => Intr2Bus_Error,
Intr2Bus_RdAck => Intr2Bus_RdAck,
Intr2Bus_Retry => Intr2Bus_Retry,
Intr2Bus_ToutSup => Intr2Bus_ToutSup,
Intr2Bus_WrAck => Intr2Bus_WrAck,
IP2Bus_IntrEvent => IP2Bus_IntrEvent,
IPIF_Lvl_Interrupts => IPIF_Lvl_Interrupts(0 to 3),
IPIF_Reg_Interrupts => IPIF_Reg_Interrupts(0 to 1));
end generate INCLUDE_INTERRUPT;
REMOVE_INTERRUPT : if (not INTERRUPT_PRESENT) generate
Intr2Bus_DBus <= (others => '0');
Intr2Bus_DevIntr <= IP2Bus_IntrEvent(0);
Intr2Bus_Error <= '0';
Intr2Bus_RdAck <= '0';
Intr2Bus_Retry <= '0';
Intr2Bus_ToutSup <= '0';
Intr2Bus_WrAck <= '0';
end generate REMOVE_INTERRUPT;
------------------------------------------------------------------------------
INCLUDE_RDFIFO : if (RDFIFO_PRESENT) generate
constant DATA_INDEX: integer := get_id_index(C_ARD_ID_ARRAY,
IPIF_RDFIFO_DATA);
constant DATA_CE_INDEX : integer := calc_start_ce_index(C_ARD_NUM_CE_ARRAY,
DATA_INDEX);
constant REG_INDEX: integer := get_id_index(C_ARD_ID_ARRAY,
IPIF_RDFIFO_REG);
constant REG_CE_INDEX : integer := calc_start_ce_index(C_ARD_NUM_CE_ARRAY,
REG_INDEX);
signal opb_seqaddr_d1 : std_logic;
begin
assert C_ARD_DEPENDENT_PROPS_ARRAY(DATA_INDEX)(WR_WIDTH_BITS) =
C_ARD_DEPENDENT_PROPS_ARRAY(DATA_INDEX)(RD_WIDTH_BITS)
report "This implementation of the OPB IPIF requires the read " &
" width to be equal to the write width for the RDFIFO."
severity FAILURE;
OPB_SEQADDR_DN_PROC : process (Bus2IP_Clk_i) is
begin
if Bus2IP_Clk_i'event and Bus2IP_Clk_i = '1' then
opb_seqaddr_d1 <= OPB_seqAddr;
end if;
end process;
I_RDFIFO: entity opb_ipif_v2_00_h.rdpfifo_top
Generic map(
C_MIR_ENABLE => (C_DEV_MIR_ENABLE /= 0),
C_BLOCK_ID => C_DEV_BLK_ID,
C_FIFO_DEPTH_LOG2X => log2(
C_ARD_DEPENDENT_PROPS_ARRAY
(DATA_INDEX)
(FIFO_CAPACITY_BITS) /
C_ARD_DEPENDENT_PROPS_ARRAY
(DATA_INDEX)
(WR_WIDTH_BITS)
),
C_FIFO_WIDTH => C_ARD_DEPENDENT_PROPS_ARRAY
(DATA_INDEX)
(WR_WIDTH_BITS),
C_INCLUDE_PACKET_MODE => C_ARD_DEPENDENT_PROPS_ARRAY
(DATA_INDEX)
(EXCLUDE_PACKET_MODE)=0,
C_INCLUDE_VACANCY => C_ARD_DEPENDENT_PROPS_ARRAY
(DATA_INDEX)
(EXCLUDE_VACANCY)=0,
C_SUPPORT_BURST => true,
C_IPIF_DBUS_WIDTH => C_IPIF_DWIDTH,
C_VIRTEX_II => VIRTEX_II
)
port map(
-- Inputs From the IPIF Bus
Bus_rst => Bus2IP_Reset_i,
Bus_Clk => Bus2IP_Clk_i,
Bus_RdReq => bus2ip_rdreq_rfifo,
Bus_WrReq => Bus2IP_WrReq_i,
Bus2FIFO_RdCE1 => RdCE_Out(REG_CE_INDEX),
Bus2FIFO_RdCE2 => RdCE_Out(REG_CE_INDEX+1),
Bus2FIFO_RdCE3 => RdCE_Out(DATA_CE_INDEX),
Bus2FIFO_WrCE1 => WrCE_Out(REG_CE_INDEX),
Bus2FIFO_WrCE2 => WrCE_Out(REG_CE_INDEX+1),
Bus2FIFO_WrCE3 => WrCE_Out(DATA_CE_INDEX),
Bus_DBus => Bus2IP_Data_i,
-- Inputs from the IP
IP2RFIFO_WrReq => IP2RFIFO_WrReq,
IP2RFIFO_WrMark => IP2RFIFO_WrMark,
IP2RFIFO_WrRestore => IP2RFIFO_WrRestore,
IP2RFIFO_WrRelease => IP2RFIFO_WrRelease,
IP2RFIFO_Data => IP2RFIFO_Data,
-- Outputs to the IP
RFIFO2IP_WrAck => RFIFO2IP_WrAck,
RFIFO2IP_AlmostFull => RFIFO2IP_AlmostFull,
RFIFO2IP_Full => RFIFO2IP_Full,
RFIFO2IP_Vacancy => RFIFO2IP_Vacancy,
-- Outputs to the IPIF DMA/SG function
RFIFO2DMA_AlmostEmpty => RFIFO2DMA_AlmostEmpty,
RFIFO2DMA_Empty => RFIFO2DMA_Empty,
RFIFO2DMA_Occupancy => RFIFO2DMA_Occupancy,
-- Interrupt Output to IPIF Interrupt Register
FIFO2IRPT_DeadLock => RdFIFO2Intr_DeadLock,
-- Outputs to the IPIF Bus
FIFO2Bus_DBus => RdFIFO2Bus_Data,
FIFO2Bus_WrAck => RFIFO_WrAck,
FIFO2Bus_RdAck => RFIFO_RdAck,
FIFO2Bus_Error => RFIFO_Error,
FIFO2Bus_Retry => RFIFO_Retry,
FIFO2Bus_ToutSup => RFIFO_ToutSup
);
end generate INCLUDE_RDFIFO;
REMOVE_RDFIFO : if (not RDFIFO_PRESENT) generate
RdFIFO2Bus_Data <= (others => '0');
RdFIFO2Intr_DeadLock <= '0';
RFIFO2DMA_AlmostEmpty <= '0';
RFIFO2DMA_Empty <= '0';
RFIFO2DMA_Occupancy <= (others => '0');
RFIFO2IP_AlmostFull <= '0';
RFIFO2IP_Full <= '0';
RFIFO2IP_Vacancy <= (others => '0');
RFIFO2IP_WrAck <= '0';
RFIFO_Error <= '0';
RFIFO_RdAck <= '0';
RFIFO_Retry <= '0';
RFIFO_ToutSup <= '0';
RFIFO_WrAck <= '0';
end generate REMOVE_RDFIFO;
--------------------------------------------------------------------------------
INCLUDE_WRFIFO : if (WRFIFO_PRESENT) generate
constant DATA_INDEX: integer := get_id_index(C_ARD_ID_ARRAY,
IPIF_WRFIFO_DATA);
constant DATA_CE_INDEX : integer := calc_start_ce_index(C_ARD_NUM_CE_ARRAY,
DATA_INDEX);
constant REG_INDEX: integer := get_id_index(C_ARD_ID_ARRAY,
IPIF_WRFIFO_REG);
constant REG_CE_INDEX : integer := calc_start_ce_index(C_ARD_NUM_CE_ARRAY,
REG_INDEX);
begin
assert C_ARD_DEPENDENT_PROPS_ARRAY(DATA_INDEX)(WR_WIDTH_BITS) =
C_ARD_DEPENDENT_PROPS_ARRAY(DATA_INDEX)(RD_WIDTH_BITS)
report "This implementation of the OPB IPIF requires the read " &
" width to be equal to the write width for the RDFIFO."
severity FAILURE;
I_WRPFIFO_TOP: entity opb_ipif_v2_00_h.wrpfifo_top
Generic map(
C_MIR_ENABLE => (C_DEV_MIR_ENABLE /= 0),
C_BLOCK_ID => C_DEV_BLK_ID,
C_FIFO_DEPTH_LOG2X => log2(
C_ARD_DEPENDENT_PROPS_ARRAY
(DATA_INDEX)
(FIFO_CAPACITY_BITS) /
C_ARD_DEPENDENT_PROPS_ARRAY
(DATA_INDEX)
(WR_WIDTH_BITS)
),
C_FIFO_WIDTH => C_ARD_DEPENDENT_PROPS_ARRAY
(DATA_INDEX)
(WR_WIDTH_BITS),
C_INCLUDE_PACKET_MODE => C_ARD_DEPENDENT_PROPS_ARRAY
(DATA_INDEX)
(EXCLUDE_PACKET_MODE)=0,
C_INCLUDE_VACANCY => C_ARD_DEPENDENT_PROPS_ARRAY
(DATA_INDEX)
(EXCLUDE_VACANCY)=0,
C_SUPPORT_BURST => true,
C_IPIF_DBUS_WIDTH => C_IPIF_DWIDTH,
C_VIRTEX_II => VIRTEX_II
)
port map(
-- Inputs From the IPIF Bus
Bus_rst => Bus2IP_Reset_i, -- In std_logic;
Bus_clk => Bus2IP_Clk_i, -- In std_logic;
Bus_RdReq => Bus2IP_RdReq_i, -- In std_logic;
Bus_WrReq => Bus2IP_WrReq_i, -- In std_logic;
Bus2FIFO_RdCE1 => RdCE_Out(REG_CE_INDEX),
Bus2FIFO_RdCE2 => RdCE_Out(REG_CE_INDEX+1),
Bus2FIFO_RdCE3 => RdCE_Out(DATA_CE_INDEX),
Bus2FIFO_WrCE1 => WrCE_Out(REG_CE_INDEX),
Bus2FIFO_WrCE2 => WrCE_Out(REG_CE_INDEX+1),
Bus2FIFO_WrCE3 => WrCE_Out(DATA_CE_INDEX),
Bus_DBus => Bus2IP_Data_i, -- In std_logic_vector(0 to C_IPIF_DWIDTH-1);
-- Inputs from the IP
IP2WFIFO_RdReq => IP2WFIFO_RdReq, -- In std_logic;
IP2WFIFO_RdMark => IP2WFIFO_RdMark, -- In std_logic;
IP2WFIFO_RdRestore => IP2WFIFO_RdRestore, -- In std_logic;
IP2WFIFO_RdRelease => IP2WFIFO_RdRelease, -- In std_logic;
-- Outputs to the IP
WFIFO2IP_Data => WFIFO2IP_Data, -- Out std_logic_vector(0 to C_FIFO_WIDTH-1);
WFIFO2IP_RdAck => WFIFO2IP_RdAck, -- Out std_logic;
WFIFO2IP_AlmostEmpty => WFIFO2IP_AlmostEmpty, -- Out std_logic;
WFIFO2IP_Empty => WFIFO2IP_Empty, -- Out std_logic;
WFIFO2IP_Occupancy => WFIFO2IP_Occupancy,
-- Outputs to the IPIF DMA/SG function
WFIFO2DMA_AlmostFull => WFIFO2DMA_AlmostFull, -- Out std_logic;
WFIFO2DMA_Full => WFIFO2DMA_Full, -- Out std_logic;
WFIFO2DMA_Vacancy => WFIFO2DMA_Vacancy,
-- Interrupt Output to IPIF Interrupt Register
FIFO2IRPT_DeadLock => WrFIFO2Intr_DeadLock, -- Out std_logic;
-- Outputs to the IPIF Bus
FIFO2Bus_DBus => WrFIFO2Bus_Data, -- Out std_logic_vector(0 to C_IPIF_DWIDTH-1);
FIFO2Bus_WrAck => WFIFO_WrAck, -- Out std_logic;
FIFO2Bus_RdAck => WFIFO_RdAck, -- Out std_logic;
FIFO2Bus_Error => WFIFO_Error, -- Out std_logic;
FIFO2Bus_Retry => WFIFO_Retry, -- Out std_logic;
FIFO2Bus_ToutSup => WFIFO_ToutSup -- Out std_logic
);
end generate INCLUDE_WRFIFO;
REMOVE_WRFIFO : if (not WRFIFO_PRESENT) generate
WFIFO2DMA_Full <= '0';
WFIFO2DMA_Vacancy <= (others => '0');
WFIFO2IP_AlmostEmpty <= '0';
WFIFO2IP_Data <= (others => '0');
WFIFO2IP_Empty <= '0';
WFIFO2IP_Occupancy <= (others => '0');
WFIFO2IP_RdAck <= '0';
WFIFO_Error <= '0';
WFIFO_RdAck <= '0';
WFIFO_Retry <= '0';
WFIFO_ToutSup <= '0';
WFIFO_WrAck <= '0';
WrFIFO2Bus_Data <= (others => '0');
WrFIFO2Intr_DeadLock <= '0';
end generate REMOVE_WRFIFO;
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Include DMA in the IPIF
------------------------------------------------------------------------------
INCLUDE_DMA : if (DMA_PRESENT) generate
Constant DMA_INDEX : integer := get_id_index(C_ARD_ID_ARRAY,IPIF_DMA_SG);
Constant DMA_CE_INDEX : integer := calc_start_ce_index(C_ARD_NUM_CE_ARRAY, DMA_INDEX);
begin
dma_sg_i1 : dma_sg
generic map (
C_OPB_DWIDTH => C_OPB_DWIDTH,
C_OPB_AWIDTH => C_OPB_AWIDTH,
C_IPIF_ABUS_WIDTH => C_OPB_AWIDTH,
C_CLK_PERIOD_PS => C_OPB_CLK_PERIOD_PS,
C_PACKET_WAIT_UNIT_NS => C_DMA_PACKET_WAIT_UNIT_NS,
C_DMA_CHAN_TYPE => C_DMA_CHAN_TYPE_ARRAY,
C_DMA_LENGTH_WIDTH => C_DMA_LENGTH_WIDTH_ARRAY,
C_LEN_FIFO_ADDR => C_DMA_PKT_LEN_FIFO_ADDR_ARRAY,
C_STAT_FIFO_ADDR => C_DMA_PKT_STAT_FIFO_ADDR_ARRAY,
C_INTR_COALESCE => C_DMA_INTR_COALESCE_ARRAY,
C_DEV_BLK_ID => C_DEV_BLK_ID,
C_DMA_BASEADDR => ZERO_ADDR_PREFIX & DMA_BASEADDR,
C_DMA_BURST_SIZE => DMA_BURST_SIZE,
C_DMA_SHORT_BURST_REMAINDER => C_DMA_SHORT_BURST_REMAINDER,
C_MA2SA_NUM_WIDTH => log2(C_DEV_MAX_BURST_SIZE/4 + 1),
C_WFIFO_VACANCY_WIDTH =>
bits_needed_for_vac(
find_ard_id(C_ARD_ID_ARRAY, IPIF_WRFIFO_DATA),
C_ARD_DEPENDENT_PROPS_ARRAY(
get_id_index_iboe(C_ARD_ID_ARRAY, IPIF_WRFIFO_DATA)
)
)
)
port map (
DMA2Bus_Data => DMA2Bus_Data,
DMA2Bus_Addr => DMA2Bus_Addr,
DMA2Bus_MstBE => DMA2Bus_MstBE,
DMA2Bus_MstWrReq => DMA2Bus_MstWrReq,
DMA2Bus_MstRdReq => DMA2Bus_MstRdReq,
DMA2Bus_MstNum => DMA2Bus_MstNum,
DMA2Bus_MstBurst => DMA2Bus_MstBurst,
DMA2Bus_MstBusLock => DMA2Bus_MstBusLock,
DMA2IP_Addr => DMA2IP_Addr(0 to C_OPB_AWIDTH-3),
DMA2Bus_WrAck => DMA2Bus_WrAck,
DMA2Bus_RdAck => DMA2Bus_RdAck,
DMA2Bus_Retry => DMA2Bus_Retry,
DMA2Bus_Error => DMA2Bus_Error,
DMA2Bus_ToutSup => DMA2Bus_ToutSup,
Bus2IP_MstWrAck => Bus2IP_MstWrAck_ma,
Bus2IP_MstRdAck => Bus2IP_MstRdAck_ma,
Mstr_sel_ma => Mstr_sel_ma,
Bus2IP_MstRetry => Bus2IP_MstRetry_i,
Bus2IP_MstError => Bus2IP_MstError_i,
Bus2IP_MstTimeOut => Bus2IP_MstTimeOut_i,
Bus2IP_BE => Bus2IP_BE_i,
Bus2IP_WrReq => Bus2IP_WrReq_i,
Bus2IP_RdReq => Bus2IP_RdReq_i,
Bus2IP_Clk => Bus2IP_Clk_i,
Bus2IP_Reset => Bus2IP_Reset_i,
Bus2IP_Freeze => Bus2IP_Freeze_i,
Bus2IP_Addr => Bus2IP_Addr_i(0 to C_OPB_AWIDTH-3),
Bus2IP_Data => Bus2IP_Data_i,
Bus2IP_Burst => Bus2IP_Burst_i,
WFIFO2DMA_Vacancy => WFIFO2DMA_Vacancy,
Bus2IP_MstLastAck => Bus2IP_MstLastAck_i,
DMA_RdCE => RdCE_Out(DMA_CE_INDEX),
DMA_WrCE => WrCE_Out(DMA_CE_INDEX),
IP2DMA_RxStatus_Empty => IP2DMA_RxStatus_Empty,
IP2DMA_RxLength_Empty => IP2DMA_RxLength_Empty,
IP2DMA_TxStatus_Empty => IP2DMA_TxStatus_Empty,
IP2DMA_TxLength_Full => IP2DMA_TxLength_Full,
IP2Bus_DMA_Req => IP2Bus_DMA_Req,
Bus2IP_DMA_Ack => Bus2IP_DMA_Ack,
DMA2Intr_Intr => DMA2Intr_Intr
);
DMA2IP_Addr(C_OPB_AWIDTH-2 to C_OPB_AWIDTH-1) <= (others => '0');
end generate INCLUDE_DMA;
------------------------------------------------------------------------------
-- Don't include DMA in the IPIF . Drive all outputs to zero.
------------------------------------------------------------------------------
REMOVE_DMA : if (not DMA_PRESENT) generate
Bus2IP_DMA_Ack <= '0';
DMA2Bus_Addr <= (others => '0');
DMA2Bus_Data <= (others => '0');
DMA2Intr_Intr <= (others => '0');
DMA2IP_Addr <= (others => '0');
DMA2Bus_MstBE <= (others => '0');
DMA2Bus_MstBurst <= '0';
DMA2Bus_MstBusLock <= '0';
DMA2Bus_MstRdReq <= '0';
DMA2Bus_MstWrReq <= '0';
DMA2Bus_Error <= '0';
DMA2Bus_RdAck <= '0';
DMA2Bus_Retry <= '0';
DMA2Bus_ToutSup <= '0';
DMA2Bus_WrAck <= '0';
end generate REMOVE_DMA;
-------------------------------------------------------------------------------
-- Misc logic assignments
Bus2IP_Addr <= Bus2IP_Addr_i;
Bus2IP_Data <= Bus2IP_Data_i(0 to C_IPIF_DWIDTH-1);
Bus2IP_BE <= Bus2IP_BE_i;
Bus2IP_WrReq <= Bus2IP_WrReq_i;
Bus2IP_RdReq <= Bus2IP_RdReq_i;
Bus2IP_Burst <= Bus2IP_Burst_i ;
Bus2IP_MstWrAck <= Bus2IP_MstWrAck_ma and not(Mstr_sel_ma);
Bus2IP_MstRdAck <= Bus2IP_MstRdAck_ma and not(Mstr_sel_ma);
Bus2IP_MstRetry <= Bus2IP_MstRetry_i and not(Mstr_sel_ma);
Bus2IP_MstError <= Bus2IP_MstError_i;
Bus2IP_MstTimeOut <= Bus2IP_MstTimeOut_i and not(Mstr_sel_ma);
Bus2IP_MstLastAck <= Bus2IP_MstLastAck_i and not(Mstr_sel_ma);
Bus2IP_Clk_i <= OPB_Clk;
Bus2IP_Clk <= OPB_Clk;
Bus2IP_Freeze_i <= Freeze;
Bus2IP_Freeze <= Freeze;
IP2INTC_Irpt <= Intr2Bus_DevIntr;
IPIF_Lvl_Interrupts(0) <= DMA2Intr_Intr(0);
IPIF_Lvl_Interrupts(1) <= DMA2Intr_Intr(1);
IPIF_Lvl_Interrupts(2) <= RdFIFO2Intr_DeadLock;
IPIF_Lvl_Interrupts(3) <= WrFIFO2Intr_DeadLock;
IPIF_Reg_Interrupts(0) <= IP2Bus_Error_mx;
IPIF_Reg_Interrupts(1) <= const_zero;
Bus2IP_Reset <= Bus2IP_Reset_i; -- hw or sw reset; if no sw reset
-- function is included, then this
-- is set equal to the hw reset, Reset.
Bus2IP_RNW <= Bus2IP_RNW_i;
const_zero <= LOGIC_LOW;
end implementation;
|
bsd-3-clause
|
masson2013/heterogeneous_hthreads
|
src/hardware/MyRepository/pcores/axi_hthread_cores/axi_sync_manager_v1_00_a/hdl/vhdl/slave.vhd
|
10
|
27202
|
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use work.common.all;
entity slave is
generic
(
C_NUM_THREADS : integer := 256;
C_NUM_MUTEXES : integer := 64;
C_AWIDTH : integer := 32;
C_DWIDTH : integer := 32;
C_MAX_AR_DWIDTH : integer := 32;
C_NUM_ADDR_RNG : integer := 7;
C_NUM_CE : integer := 1
);
port
(
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Addr : in std_logic_vector(0 to C_AWIDTH-1);
Bus2IP_Data : in std_logic_vector(0 to C_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_DWIDTH/8-1);
Bus2IP_CS : in std_logic_vector(0 to C_NUM_ADDR_RNG-1);
Bus2IP_RNW : in std_logic;
IP2Bus_Data : out std_logic_vector(0 to C_DWIDTH-1);
IP2Bus_Error : out std_logic;
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
system_reset : in std_logic;
system_resetdone : out std_logic;
send_ena : out std_logic;
send_id : out std_logic_vector(0 to log2(C_NUM_THREADS)-1);
send_ack : in std_logic;
siaddr : in std_logic_vector(0 to log2(C_NUM_THREADS)-1);
siena : in std_logic;
siwea : in std_logic;
sinext : in std_logic_vector(0 to log2(C_NUM_THREADS)-1);
sonext : out std_logic_vector(0 to log2(C_NUM_THREADS)-1)
);
end slave;
architecture behavioral of slave is
-- Declare constants for bits needed for threads, mutexes, commands, and kinds
constant MTX_BIT : integer := log2( C_NUM_MUTEXES );
constant THR_BIT : integer := log2( C_NUM_THREADS );
constant CMD_BIT : integer := 3;
constant CNT_BIT : integer := 8;
constant KND_BIT : integer := 2;
-- Declare signals for clock, reset, rnw, and data input
signal clk : std_logic;
signal rst : std_logic;
signal rnw : std_logic;
signal datain : std_logic_vector(0 to C_DWIDTH-1);
-- Declare finish signals for the state machines
signal IP2Bus_RdAck_internal, IP2Bus_WrAck_internal : std_logic;
signal lock_finish : std_logic;
signal unlock_finish : std_logic;
signal trylock_finish : std_logic;
signal count_finish : std_logic;
signal kind_finish : std_logic;
signal owner_finish : std_logic;
signal result_finish : std_logic;
-- Declare data signals for the state machines
signal lock_data : std_logic_vector(0 to C_DWIDTH-1);
signal unlock_data : std_logic_vector(0 to C_DWIDTH-1);
signal trylock_data : std_logic_vector(0 to C_DWIDTH-1);
signal count_data : std_logic_vector(0 to C_DWIDTH-1);
signal kind_data : std_logic_vector(0 to C_DWIDTH-1);
signal owner_data : std_logic_vector(0 to C_DWIDTH-1);
signal result_data : std_logic_vector(0 to C_DWIDTH-1);
-- Declare mutex address signals for the state machines
signal lock_maddr : std_logic_vector(0 to MTX_BIT-1);
signal unlock_maddr : std_logic_vector(0 to MTX_BIT-1);
signal trylock_maddr : std_logic_vector(0 to MTX_BIT-1);
signal count_maddr : std_logic_vector(0 to MTX_BIT-1);
signal kind_maddr : std_logic_vector(0 to MTX_BIT-1);
signal owner_maddr : std_logic_vector(0 to MTX_BIT-1);
-- Declare mutex enable signals for the state machines
signal lock_mena : std_logic;
signal unlock_mena : std_logic;
signal trylock_mena : std_logic;
signal count_mena : std_logic;
signal kind_mena : std_logic;
signal owner_mena : std_logic;
-- Declare mutex write enable signals for the state machines
signal lock_mwea : std_logic;
signal unlock_mwea : std_logic;
signal trylock_mwea : std_logic;
signal count_mwea : std_logic;
signal kind_mwea : std_logic;
signal owner_mwea : std_logic;
-- Declare mutex owner signals for the state machies
signal lock_mowner : std_logic_vector(0 to THR_BIT-1);
signal unlock_mowner : std_logic_vector(0 to THR_BIT-1);
signal trylock_mowner : std_logic_vector(0 to THR_BIT-1);
signal count_mowner : std_logic_vector(0 to THR_BIT-1);
signal kind_mowner : std_logic_vector(0 to THR_BIT-1);
signal owner_mowner : std_logic_vector(0 to THR_BIT-1);
-- Declare mutex next signals for the state machines
signal lock_mnext : std_logic_vector(0 to THR_BIT-1);
signal unlock_mnext : std_logic_vector(0 to THR_BIT-1);
signal trylock_mnext : std_logic_vector(0 to THR_BIT-1);
signal count_mnext : std_logic_vector(0 to THR_BIT-1);
signal kind_mnext : std_logic_vector(0 to THR_BIT-1);
signal owner_mnext : std_logic_vector(0 to THR_BIT-1);
-- Declare mutex last signals for the state machines
signal lock_mlast : std_logic_vector(0 to THR_BIT-1);
signal unlock_mlast : std_logic_vector(0 to THR_BIT-1);
signal trylock_mlast : std_logic_vector(0 to THR_BIT-1);
signal count_mlast : std_logic_vector(0 to THR_BIT-1);
signal kind_mlast : std_logic_vector(0 to THR_BIT-1);
signal owner_mlast : std_logic_vector(0 to THR_BIT-1);
-- Declare mutex count signals for the state machines
signal lock_mcount : std_logic_vector(0 to CNT_BIT-1);
signal unlock_mcount : std_logic_vector(0 to CNT_BIT-1);
signal trylock_mcount : std_logic_vector(0 to CNT_BIT-1);
signal count_mcount : std_logic_vector(0 to CNT_BIT-1);
signal kind_mcount : std_logic_vector(0 to CNT_BIT-1);
signal owner_mcount : std_logic_vector(0 to CNT_BIT-1);
-- Declare mutex kind signals for the state machines
signal lock_mkind : std_logic_vector(0 to KND_BIT-1);
signal unlock_mkind : std_logic_vector(0 to KND_BIT-1);
signal trylock_mkind : std_logic_vector(0 to KND_BIT-1);
signal count_mkind : std_logic_vector(0 to KND_BIT-1);
signal kind_mkind : std_logic_vector(0 to KND_BIT-1);
signal owner_mkind : std_logic_vector(0 to KND_BIT-1);
-- Declare thread address signals for the state machines
signal lock_taddr : std_logic_vector(0 to THR_BIT-1);
signal unlock_taddr : std_logic_vector(0 to THR_BIT-1);
signal trylock_taddr : std_logic_vector(0 to THR_BIT-1);
signal count_taddr : std_logic_vector(0 to THR_BIT-1);
signal kind_taddr : std_logic_vector(0 to THR_BIT-1);
signal owner_taddr : std_logic_vector(0 to THR_BIT-1);
-- Declare thread enable signals for the state machines
signal lock_tena : std_logic;
signal unlock_tena : std_logic;
signal trylock_tena : std_logic;
signal count_tena : std_logic;
signal kind_tena : std_logic;
signal owner_tena : std_logic;
-- Declare thread write enable signals for the state machines
signal lock_twea : std_logic;
signal unlock_twea : std_logic;
signal trylock_twea : std_logic;
signal count_twea : std_logic;
signal kind_twea : std_logic;
signal owner_twea : std_logic;
-- Declare thread next signals for the state machines
signal lock_tnext : std_logic_vector(0 to THR_BIT-1);
signal unlock_tnext : std_logic_vector(0 to THR_BIT-1);
signal trylock_tnext : std_logic_vector(0 to THR_BIT-1);
signal count_tnext : std_logic_vector(0 to THR_BIT-1);
signal kind_tnext : std_logic_vector(0 to THR_BIT-1);
signal owner_tnext : std_logic_vector(0 to THR_BIT-1);
-- Declare send enable signals for the state machines
signal unlock_sena : std_logic;
-- Declare send identifier signals for the state machines
signal unlock_sid : std_logic_vector(0 to THR_BIT-1);
-- Declare signals for the mutex store
signal miaddr : std_logic_vector(0 to MTX_BIT-1);
signal miena : std_logic;
signal miwea : std_logic;
signal miowner : std_logic_vector(0 to THR_BIT-1);
signal minext : std_logic_vector(0 to THR_BIT-1);
signal milast : std_logic_vector(0 to THR_BIT-1);
signal micount : std_logic_vector(0 to CNT_BIT-1);
signal mikind : std_logic_vector(0 to KND_BIT-1);
signal moowner : std_logic_vector(0 to THR_BIT-1);
signal monext : std_logic_vector(0 to THR_BIT-1);
signal molast : std_logic_vector(0 to THR_BIT-1);
signal mocount : std_logic_vector(0 to CNT_BIT-1);
signal mokind : std_logic_vector(0 to KND_BIT-1);
-- Declare signals for the thread store
signal tiaddr : std_logic_vector(0 to THR_BIT-1);
signal tiena : std_logic;
signal tiwea : std_logic;
signal tinext : std_logic_vector(0 to THR_BIT-1);
signal tonext : std_logic_vector(0 to THR_BIT-1);
-- Declare signals for the system reset
signal lock_resetdone : std_logic;
signal unlock_resetdone : std_logic;
signal trylock_resetdone : std_logic;
signal owner_resetdone : std_logic;
signal kind_resetdone : std_logic;
signal count_resetdone : std_logic;
signal result_resetdone : std_logic;
signal thread_resetdone : std_logic;
signal send_resetdone : std_logic;
signal mutex_resetdone : std_logic;
-- Declare aliases for the start signals
alias lock_start : std_logic is Bus2IP_CS(0);
alias unlock_start : std_logic is Bus2IP_CS(1);
alias trylock_start : std_logic is Bus2IP_CS(2);
alias owner_start : std_logic is Bus2IP_CS(3);
alias kind_start : std_logic is Bus2IP_CS(4);
alias count_start : std_logic is Bus2IP_CS(5);
alias result_start : std_logic is Bus2IP_CS(6);
-- Declare constants for the bit index positions
constant KND_SRT : integer := C_AWIDTH - 2;
constant KND_END : integer := C_AWIDTH - 1;
constant MTX_SRT : integer := KND_SRT - MTX_BIT;
constant MTX_END : integer := KND_SRT - 1;
constant THR_SRT : integer := MTX_SRT - THR_BIT;
constant THR_END : integer := MTX_SRT - 1;
constant CMD_SRT : integer := THR_SRT - CMD_BIT;
constant CMD_END : integer := THR_SRT - 1;
-- Declare aliases for the encoded parameters
alias knd_number : std_logic_vector(0 to KND_BIT-1) is
Bus2IP_Data(KND_SRT to KND_END);
alias mtx_number : std_logic_vector(0 to MTX_BIT-1) is
Bus2IP_Addr(MTX_SRT to MTX_END);
alias thr_number : std_logic_vector(0 to THR_BIT-1) is
Bus2IP_Addr(THR_SRT to THR_END);
alias cmd_number : std_logic_vector(0 to CMD_BIT-1) is
Bus2IP_Addr(CMD_SRT to CMD_END);
begin
clk <= Bus2IP_Clk; -- Use the bus clock for the core clock
rst <= Bus2IP_Reset; -- Use the bus reset for the core reset
rnw <= Bus2IP_RNW; -- Use the bus rnw for the core rnw
datain <= Bus2IP_Data; -- Use the bus data for the core data
send_ena <= unlock_sena; -- Output the send enable signal
send_id <= unlock_sid; -- Output the send identifier
--IP2Bus_Data <= (others => '0'); -- Never use bus data lines (see ArData)
IP2Bus_Error <= '0'; -- Never cause a bus error
system_resetdone <= lock_resetdone and
unlock_resetdone and
trylock_resetdone and
owner_resetdone and
count_resetdone and
kind_resetdone and
result_resetdone and
thread_resetdone and
send_resetdone and
mutex_resetdone;
-- **********************
-- Ack router
-- **********************
IP2Bus_RdAck <= IP2Bus_RdAck_internal when rnw = '1' else '0';
IP2Bus_WrAck <= IP2Bus_WrAck_internal when rnw = '0' else '0';
-- **********************
IP2Bus_RdAck_internal <= lock_finish or
unlock_finish or
trylock_finish or
owner_finish or
count_finish or
kind_finish or
result_finish;
IP2Bus_WrAck_internal <= lock_finish or
unlock_finish or
trylock_finish or
owner_finish or
count_finish or
kind_finish or
result_finish;
IP2Bus_Data <= lock_data or
unlock_data or
trylock_data or
owner_data or
count_data or
kind_data or
result_data;
miaddr <= lock_maddr or
unlock_maddr or
trylock_maddr or
owner_maddr or
count_maddr or
kind_maddr;
miena <= lock_mena or
unlock_mena or
trylock_mena or
owner_mena or
count_mena or
kind_mena;
miwea <= lock_mwea or
unlock_mwea or
trylock_mwea or
owner_mwea or
count_mwea or
kind_mwea;
miowner <= lock_mowner or
unlock_mowner or
trylock_mowner or
owner_mowner or
count_mowner or
kind_mowner;
minext <= lock_mnext or
unlock_mnext or
trylock_mnext or
owner_mnext or
count_mnext or
kind_mnext;
milast <= lock_mlast or
unlock_mlast or
trylock_mlast or
owner_mlast or
count_mlast or
kind_mlast;
micount <= lock_mcount or
unlock_mcount or
trylock_mcount or
owner_mcount or
count_mcount or
kind_mcount;
mikind <= lock_mkind or
unlock_mkind or
trylock_mkind or
owner_mkind or
count_mkind or
kind_mkind;
tiaddr <= lock_taddr or
unlock_taddr or
trylock_taddr or
owner_taddr or
count_taddr or
kind_taddr;
tiena <= lock_tena or
unlock_tena or
trylock_tena or
owner_tena or
count_tena or
kind_tena;
tiwea <= lock_twea or
unlock_twea or
trylock_twea or
owner_twea or
count_twea or
kind_twea;
tinext <= lock_tnext or
unlock_tnext or
trylock_tnext or
owner_tnext or
count_tnext or
kind_tnext;
mutex_i : entity work.mutex_store
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
miaddr => miaddr,
miena => miena,
miwea => miwea,
miowner => miowner,
minext => minext,
milast => milast,
mikind => mikind,
micount => micount,
moowner => moowner,
monext => monext,
molast => molast,
mokind => mokind,
mocount => mocount,
sysrst => system_reset,
rstdone => mutex_resetdone
);
thread_i : entity work.thread_store
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
tiaddr => tiaddr,
tiena => tiena,
tiwea => tiwea,
tinext => tinext,
tonext => tonext,
sysrst => system_reset,
rstdone => thread_resetdone
);
send_i : entity work.send_store
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
siaddr => siaddr,
siena => siena,
siwea => siwea,
sinext => sinext,
sonext => sonext,
sysrst => system_reset,
rstdone => send_resetdone
);
lock_i : entity work.lock_fsm
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
start => lock_start,
finish => lock_finish,
data => lock_data,
mutex => mtx_number,
thread => thr_number,
miowner => moowner,
minext => monext,
milast => molast,
micount => mocount,
mikind => mokind,
tinext => tonext,
moaddr => lock_maddr,
moena => lock_mena,
mowea => lock_mwea,
moowner => lock_mowner,
monext => lock_mnext,
molast => lock_mlast,
mocount => lock_mcount,
mokind => lock_mkind,
toaddr => lock_taddr,
toena => lock_tena,
towea => lock_twea,
tonext => lock_tnext,
sysrst => system_reset,
rstdone => lock_resetdone
);
unlock_i : entity work.unlock_fsm
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
start => unlock_start,
finish => unlock_finish,
data => unlock_data,
mutex => mtx_number,
thread => thr_number,
miowner => moowner,
minext => monext,
milast => molast,
micount => mocount,
mikind => mokind,
tinext => tonext,
moaddr => unlock_maddr,
moena => unlock_mena,
mowea => unlock_mwea,
moowner => unlock_mowner,
monext => unlock_mnext,
molast => unlock_mlast,
mocount => unlock_mcount,
mokind => unlock_mkind,
toaddr => unlock_taddr,
toena => unlock_tena,
towea => unlock_twea,
tonext => unlock_tnext,
sena => unlock_sena,
sid => unlock_sid,
sack => send_ack,
sysrst => system_reset,
rstdone => unlock_resetdone
);
trylock_i : entity work.trylock_fsm
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
start => trylock_start,
finish => trylock_finish,
data => trylock_data,
mutex => mtx_number,
thread => thr_number,
miowner => moowner,
minext => monext,
milast => molast,
micount => mocount,
mikind => mokind,
tinext => tonext,
moaddr => trylock_maddr,
moena => trylock_mena,
mowea => trylock_mwea,
moowner => trylock_mowner,
monext => trylock_mnext,
molast => trylock_mlast,
mocount => trylock_mcount,
mokind => trylock_mkind,
toaddr => trylock_taddr,
toena => trylock_tena,
towea => trylock_twea,
tonext => trylock_tnext,
sysrst => system_reset,
rstdone => trylock_resetdone
);
count_i : entity work.count_fsm
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
start => count_start,
finish => count_finish,
data => count_data,
mutex => mtx_number,
thread => thr_number,
miowner => moowner,
minext => monext,
milast => molast,
micount => mocount,
mikind => mokind,
tinext => tonext,
moaddr => count_maddr,
moena => count_mena,
mowea => count_mwea,
moowner => count_mowner,
monext => count_mnext,
molast => count_mlast,
mocount => count_mcount,
mokind => count_mkind,
toaddr => count_taddr,
toena => count_tena,
towea => count_twea,
tonext => count_tnext,
sysrst => system_reset,
rstdone => count_resetdone
);
kind_i : entity work.kind_fsm
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
start => kind_start,
finish => kind_finish,
data => kind_data,
datain => datain,
mutex => mtx_number,
thread => thr_number,
miowner => moowner,
minext => monext,
milast => molast,
micount => mocount,
mikind => mokind,
tinext => tonext,
moaddr => kind_maddr,
moena => kind_mena,
mowea => kind_mwea,
moowner => kind_mowner,
monext => kind_mnext,
molast => kind_mlast,
mocount => kind_mcount,
mokind => kind_mkind,
toaddr => kind_taddr,
toena => kind_tena,
towea => kind_twea,
tonext => kind_tnext,
rnw => rnw,
sysrst => system_reset,
rstdone => kind_resetdone
);
owner_i : entity work.owner_fsm
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
start => owner_start,
finish => owner_finish,
data => owner_data,
mutex => mtx_number,
thread => thr_number,
miowner => moowner,
minext => monext,
milast => molast,
micount => mocount,
mikind => mokind,
tinext => tonext,
moaddr => owner_maddr,
moena => owner_mena,
mowea => owner_mwea,
moowner => owner_mowner,
monext => owner_mnext,
molast => owner_mlast,
mocount => owner_mcount,
mokind => owner_mkind,
toaddr => owner_taddr,
toena => owner_tena,
towea => owner_twea,
tonext => owner_tnext,
sysrst => system_reset,
rstdone => owner_resetdone
);
result_i : entity work.result_fsm
generic map
(
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_TWIDTH => THR_BIT,
C_MWIDTH => MTX_BIT,
C_CWIDTH => CNT_BIT
)
port map
(
clk => clk,
rst => rst,
start => result_start,
finish => result_finish,
data => result_data,
datain => datain,
rnw => rnw,
sysrst => system_reset,
rstdone => result_resetdone
);
end behavioral;
|
bsd-3-clause
|
masson2013/heterogeneous_hthreads
|
src/platforms/xilinx/numa3_hwti/design/pcores/plb_sync_manager_v1_00_a/hdl/vhdl/unlock_fsm.vhd
|
11
|
8349
|
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use work.common.all;
entity unlock_fsm is
generic
(
C_AWIDTH : integer := 32;
C_DWIDTH : integer := 32;
C_TWIDTH : integer := 8;
C_MWIDTH : integer := 6;
C_CWIDTH : integer := 8
);
port
(
clk : in std_logic;
rst : in std_logic;
start : in std_logic;
finish : out std_logic;
data : out std_logic_vector(0 to C_DWIDTH-1);
mutex : in std_logic_vector(0 to C_MWIDTH-1);
thread : in std_logic_vector(0 to C_TWIDTH-1);
miowner : in std_logic_vector(0 to C_TWIDTH-1);
minext : in std_logic_vector(0 to C_TWIDTH-1);
milast : in std_logic_vector(0 to C_TWIDTH-1);
micount : in std_logic_vector(0 to C_CWIDTH-1);
mikind : in std_logic_vector(0 to 1);
tinext : in std_logic_vector(0 to C_TWIDTH-1);
moaddr : out std_logic_vector(0 to C_MWIDTH-1);
moena : out std_logic;
mowea : out std_logic;
moowner : out std_logic_vector(0 to C_TWIDTH-1);
monext : out std_logic_vector(0 to C_TWIDTH-1);
molast : out std_logic_vector(0 to C_TWIDTH-1);
mocount : out std_logic_vector(0 to C_CWIDTH-1);
mokind : out std_logic_vector(0 to 1);
toaddr : out std_logic_vector(0 to C_TWIDTH-1);
toena : out std_logic;
towea : out std_logic;
tonext : out std_logic_vector(0 to C_TWIDTH-1);
sysrst : in std_logic;
rstdone : out std_logic;
sena : out std_logic;
sid : out std_logic_vector(0 to C_TWIDTH-1);
sack : in std_logic
);
end unlock_fsm;
architecture behavioral of unlock_fsm is
-- A type for the states in the unlock fsm
type unlock_state is
(
IDLE,
READ_MUTEX,
DONE_MUTEX,
READ_THREAD,
DONE_THREAD
);
-- Declare signals for the unlock fsm
signal unlock_cs : unlock_state;
signal unlock_ns : unlock_state;
signal hold_minext : std_logic_vector(0 to C_TWIDTH-1);
signal hold_minext_nxt : std_logic_vector(0 to C_TWIDTH-1);
begin
-- This core resets in one clock cycle so it is always "done"
rstdone <= '1';
unlock_update : process (clk,rst,sysrst,unlock_ns) is
begin
if( rising_edge(clk) ) then
if( rst = '1' or sysrst = '1' ) then
unlock_cs <= IDLE;
hold_minext <= (others => '0');
else
unlock_cs <= unlock_ns;
hold_minext <= hold_minext_nxt;
end if;
end if;
end process unlock_update;
unlock_controller : process (unlock_cs,start,mutex,micount,mikind,miowner,milast,minext,tinext,hold_minext) is
begin
unlock_ns <= unlock_cs;
hold_minext_nxt <= (others => '0');
finish <= '0';
data <= (others => '0');
moaddr <= (others => '0');
moena <= '0';
mowea <= '0';
moowner <= (others => '0');
monext <= (others => '0');
molast <= (others => '0');
mokind <= (others => '0');
mocount <= (others => '0');
toaddr <= (others => '0');
toena <= '0';
towea <= '0';
tonext <= (others => '0');
sena <= '0';
sid <= (others => '0');
case unlock_cs is
when IDLE =>
if( start = '1' ) then
moaddr <= mutex;
moena <= '1';
mowea <= '0';
unlock_ns <= READ_MUTEX;
end if;
when READ_MUTEX =>
unlock_ns <= DONE_MUTEX;
when DONE_MUTEX =>
if( mikind = SYNCH_RECURS and micount /= one(C_CWIDTH) and micount /= zero(C_CWIDTH) ) then
moaddr <= mutex;
moena <= '1';
mowea <= '1';
moowner <= miowner;
mocount <= micount - 1;
mokind <= mikind;
monext <= minext;
molast <= milast;
finish <= '1';
unlock_ns <= IDLE;
elsif( micount = one(C_CWIDTH) ) then
if( milast = miowner ) then
moaddr <= mutex;
moena <= '1';
mowea <= '1';
moowner <= (others => '0');
mocount <= (others => '0');
mokind <= mikind;
monext <= (others => '0');
molast <= (others => '0');
finish <= '1';
unlock_ns <= IDLE;
else
toaddr <= minext;
toena <= '1';
towea <= '0';
unlock_ns <= READ_THREAD;
hold_minext_nxt <= minext;
end if;
else
data(0) <= '1';
finish <= '1';
unlock_ns <= IDLE;
end if;
when READ_THREAD =>
hold_minext_nxt <= hold_minext;
unlock_ns <= DONE_THREAD;
when DONE_THREAD =>
moaddr <= mutex;
moena <= '1';
mowea <= '1';
moowner <= hold_minext;
mocount <= one(C_CWIDTH);
mokind <= mikind;
molast <= milast;
monext <= tinext;
sena <= '1';
sid <= hold_minext;
finish <= '1';
unlock_ns <= IDLE;
end case;
end process unlock_controller;
end behavioral;
|
bsd-3-clause
|
masson2013/heterogeneous_hthreads
|
src/platforms/xilinx/smp1/design/pcores/plb_sync_manager_v1_00_a/hdl/vhdl/unlock_fsm.vhd
|
11
|
8349
|
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use work.common.all;
entity unlock_fsm is
generic
(
C_AWIDTH : integer := 32;
C_DWIDTH : integer := 32;
C_TWIDTH : integer := 8;
C_MWIDTH : integer := 6;
C_CWIDTH : integer := 8
);
port
(
clk : in std_logic;
rst : in std_logic;
start : in std_logic;
finish : out std_logic;
data : out std_logic_vector(0 to C_DWIDTH-1);
mutex : in std_logic_vector(0 to C_MWIDTH-1);
thread : in std_logic_vector(0 to C_TWIDTH-1);
miowner : in std_logic_vector(0 to C_TWIDTH-1);
minext : in std_logic_vector(0 to C_TWIDTH-1);
milast : in std_logic_vector(0 to C_TWIDTH-1);
micount : in std_logic_vector(0 to C_CWIDTH-1);
mikind : in std_logic_vector(0 to 1);
tinext : in std_logic_vector(0 to C_TWIDTH-1);
moaddr : out std_logic_vector(0 to C_MWIDTH-1);
moena : out std_logic;
mowea : out std_logic;
moowner : out std_logic_vector(0 to C_TWIDTH-1);
monext : out std_logic_vector(0 to C_TWIDTH-1);
molast : out std_logic_vector(0 to C_TWIDTH-1);
mocount : out std_logic_vector(0 to C_CWIDTH-1);
mokind : out std_logic_vector(0 to 1);
toaddr : out std_logic_vector(0 to C_TWIDTH-1);
toena : out std_logic;
towea : out std_logic;
tonext : out std_logic_vector(0 to C_TWIDTH-1);
sysrst : in std_logic;
rstdone : out std_logic;
sena : out std_logic;
sid : out std_logic_vector(0 to C_TWIDTH-1);
sack : in std_logic
);
end unlock_fsm;
architecture behavioral of unlock_fsm is
-- A type for the states in the unlock fsm
type unlock_state is
(
IDLE,
READ_MUTEX,
DONE_MUTEX,
READ_THREAD,
DONE_THREAD
);
-- Declare signals for the unlock fsm
signal unlock_cs : unlock_state;
signal unlock_ns : unlock_state;
signal hold_minext : std_logic_vector(0 to C_TWIDTH-1);
signal hold_minext_nxt : std_logic_vector(0 to C_TWIDTH-1);
begin
-- This core resets in one clock cycle so it is always "done"
rstdone <= '1';
unlock_update : process (clk,rst,sysrst,unlock_ns) is
begin
if( rising_edge(clk) ) then
if( rst = '1' or sysrst = '1' ) then
unlock_cs <= IDLE;
hold_minext <= (others => '0');
else
unlock_cs <= unlock_ns;
hold_minext <= hold_minext_nxt;
end if;
end if;
end process unlock_update;
unlock_controller : process (unlock_cs,start,mutex,micount,mikind,miowner,milast,minext,tinext,hold_minext) is
begin
unlock_ns <= unlock_cs;
hold_minext_nxt <= (others => '0');
finish <= '0';
data <= (others => '0');
moaddr <= (others => '0');
moena <= '0';
mowea <= '0';
moowner <= (others => '0');
monext <= (others => '0');
molast <= (others => '0');
mokind <= (others => '0');
mocount <= (others => '0');
toaddr <= (others => '0');
toena <= '0';
towea <= '0';
tonext <= (others => '0');
sena <= '0';
sid <= (others => '0');
case unlock_cs is
when IDLE =>
if( start = '1' ) then
moaddr <= mutex;
moena <= '1';
mowea <= '0';
unlock_ns <= READ_MUTEX;
end if;
when READ_MUTEX =>
unlock_ns <= DONE_MUTEX;
when DONE_MUTEX =>
if( mikind = SYNCH_RECURS and micount /= one(C_CWIDTH) and micount /= zero(C_CWIDTH) ) then
moaddr <= mutex;
moena <= '1';
mowea <= '1';
moowner <= miowner;
mocount <= micount - 1;
mokind <= mikind;
monext <= minext;
molast <= milast;
finish <= '1';
unlock_ns <= IDLE;
elsif( micount = one(C_CWIDTH) ) then
if( milast = miowner ) then
moaddr <= mutex;
moena <= '1';
mowea <= '1';
moowner <= (others => '0');
mocount <= (others => '0');
mokind <= mikind;
monext <= (others => '0');
molast <= (others => '0');
finish <= '1';
unlock_ns <= IDLE;
else
toaddr <= minext;
toena <= '1';
towea <= '0';
unlock_ns <= READ_THREAD;
hold_minext_nxt <= minext;
end if;
else
data(0) <= '1';
finish <= '1';
unlock_ns <= IDLE;
end if;
when READ_THREAD =>
hold_minext_nxt <= hold_minext;
unlock_ns <= DONE_THREAD;
when DONE_THREAD =>
moaddr <= mutex;
moena <= '1';
mowea <= '1';
moowner <= hold_minext;
mocount <= one(C_CWIDTH);
mokind <= mikind;
molast <= milast;
monext <= tinext;
sena <= '1';
sid <= hold_minext;
finish <= '1';
unlock_ns <= IDLE;
end case;
end process unlock_controller;
end behavioral;
|
bsd-3-clause
|
masson2013/heterogeneous_hthreads
|
src/platforms/xilinx/smp3_opbhwti/design/pcores/plb_sync_manager_v1_00_a/hdl/vhdl/unlock_fsm.vhd
|
11
|
8349
|
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use work.common.all;
entity unlock_fsm is
generic
(
C_AWIDTH : integer := 32;
C_DWIDTH : integer := 32;
C_TWIDTH : integer := 8;
C_MWIDTH : integer := 6;
C_CWIDTH : integer := 8
);
port
(
clk : in std_logic;
rst : in std_logic;
start : in std_logic;
finish : out std_logic;
data : out std_logic_vector(0 to C_DWIDTH-1);
mutex : in std_logic_vector(0 to C_MWIDTH-1);
thread : in std_logic_vector(0 to C_TWIDTH-1);
miowner : in std_logic_vector(0 to C_TWIDTH-1);
minext : in std_logic_vector(0 to C_TWIDTH-1);
milast : in std_logic_vector(0 to C_TWIDTH-1);
micount : in std_logic_vector(0 to C_CWIDTH-1);
mikind : in std_logic_vector(0 to 1);
tinext : in std_logic_vector(0 to C_TWIDTH-1);
moaddr : out std_logic_vector(0 to C_MWIDTH-1);
moena : out std_logic;
mowea : out std_logic;
moowner : out std_logic_vector(0 to C_TWIDTH-1);
monext : out std_logic_vector(0 to C_TWIDTH-1);
molast : out std_logic_vector(0 to C_TWIDTH-1);
mocount : out std_logic_vector(0 to C_CWIDTH-1);
mokind : out std_logic_vector(0 to 1);
toaddr : out std_logic_vector(0 to C_TWIDTH-1);
toena : out std_logic;
towea : out std_logic;
tonext : out std_logic_vector(0 to C_TWIDTH-1);
sysrst : in std_logic;
rstdone : out std_logic;
sena : out std_logic;
sid : out std_logic_vector(0 to C_TWIDTH-1);
sack : in std_logic
);
end unlock_fsm;
architecture behavioral of unlock_fsm is
-- A type for the states in the unlock fsm
type unlock_state is
(
IDLE,
READ_MUTEX,
DONE_MUTEX,
READ_THREAD,
DONE_THREAD
);
-- Declare signals for the unlock fsm
signal unlock_cs : unlock_state;
signal unlock_ns : unlock_state;
signal hold_minext : std_logic_vector(0 to C_TWIDTH-1);
signal hold_minext_nxt : std_logic_vector(0 to C_TWIDTH-1);
begin
-- This core resets in one clock cycle so it is always "done"
rstdone <= '1';
unlock_update : process (clk,rst,sysrst,unlock_ns) is
begin
if( rising_edge(clk) ) then
if( rst = '1' or sysrst = '1' ) then
unlock_cs <= IDLE;
hold_minext <= (others => '0');
else
unlock_cs <= unlock_ns;
hold_minext <= hold_minext_nxt;
end if;
end if;
end process unlock_update;
unlock_controller : process (unlock_cs,start,mutex,micount,mikind,miowner,milast,minext,tinext,hold_minext) is
begin
unlock_ns <= unlock_cs;
hold_minext_nxt <= (others => '0');
finish <= '0';
data <= (others => '0');
moaddr <= (others => '0');
moena <= '0';
mowea <= '0';
moowner <= (others => '0');
monext <= (others => '0');
molast <= (others => '0');
mokind <= (others => '0');
mocount <= (others => '0');
toaddr <= (others => '0');
toena <= '0';
towea <= '0';
tonext <= (others => '0');
sena <= '0';
sid <= (others => '0');
case unlock_cs is
when IDLE =>
if( start = '1' ) then
moaddr <= mutex;
moena <= '1';
mowea <= '0';
unlock_ns <= READ_MUTEX;
end if;
when READ_MUTEX =>
unlock_ns <= DONE_MUTEX;
when DONE_MUTEX =>
if( mikind = SYNCH_RECURS and micount /= one(C_CWIDTH) and micount /= zero(C_CWIDTH) ) then
moaddr <= mutex;
moena <= '1';
mowea <= '1';
moowner <= miowner;
mocount <= micount - 1;
mokind <= mikind;
monext <= minext;
molast <= milast;
finish <= '1';
unlock_ns <= IDLE;
elsif( micount = one(C_CWIDTH) ) then
if( milast = miowner ) then
moaddr <= mutex;
moena <= '1';
mowea <= '1';
moowner <= (others => '0');
mocount <= (others => '0');
mokind <= mikind;
monext <= (others => '0');
molast <= (others => '0');
finish <= '1';
unlock_ns <= IDLE;
else
toaddr <= minext;
toena <= '1';
towea <= '0';
unlock_ns <= READ_THREAD;
hold_minext_nxt <= minext;
end if;
else
data(0) <= '1';
finish <= '1';
unlock_ns <= IDLE;
end if;
when READ_THREAD =>
hold_minext_nxt <= hold_minext;
unlock_ns <= DONE_THREAD;
when DONE_THREAD =>
moaddr <= mutex;
moena <= '1';
mowea <= '1';
moowner <= hold_minext;
mocount <= one(C_CWIDTH);
mokind <= mikind;
molast <= milast;
monext <= tinext;
sena <= '1';
sid <= hold_minext;
finish <= '1';
unlock_ns <= IDLE;
end case;
end process unlock_controller;
end behavioral;
|
bsd-3-clause
|
masson2013/heterogeneous_hthreads
|
src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/opb_v20_v1_10_d/hdl/vhdl/opb_arbiter_core.vhd
|
3
|
24936
|
-------------------------------------------------------------------------------
-- $Id: opb_arbiter_core.vhd,v 1.1.2.1 2009/10/06 21:15:01 gburch Exp $
-------------------------------------------------------------------------------
-- opb_arbiter_core.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: opb_arbiter_core.vhd
-- Version: v1.02e
-- Description: This is the top-level design file for the OPB Arbiter core.
-- It supports 1-16 masters and both fixed and dynamic priority
-- algorithms via user-configurable parameters. The user can
-- also include support for bus parking and the OPB slave
-- interface by setting parameters.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- opb_arbiter.vhd
-- --opb_arbiter_core.vhd
-- -- ipif_regonly_slave.vhd
-- -- priority_register_logic.vhd
-- -- priority_reg.vhd
-- -- onehot2encoded.vhd
-- -- or_bits.vhd
-- -- control_register.vhd
-- -- arb2bus_data_mux.vhd
-- -- mux_onehot.vhd
-- -- or_bits.vhd
-- -- watchdog_timer.vhd
-- -- arbitration_logic.vhd
-- -- or_bits.vhd
-- -- park_lock_logic.vhd
-- -- or_bits.vhd
-- -- or_gate.vhd
-- -- or_muxcy.vhd
-------------------------------------------------------------------------------
-- Author: ALS
-- History:
-- ALS 08/28/01 -- Version 1.01a creation to include IPIF v1.22a
-- ALS 10/04/01 -- Version 1.02a creation to include IPIF v1.23a
-- ALS 11/27/01
-- ^^^^^^
-- Version 1.02b created to fix registered grant problem.
-- ~~~~~~
-- ALS 01/26/02
-- ^^^^^^
-- Created version 1.02c to fix problem with registered grants, and buslock when
-- the buslock master is holding request high and performing conversion cycles.
-- ~~~~~~
-- ALS 01/09/03
-- ^^^^^^
-- Created version 1.02d to register OPB_timeout to improve timing
-- ~~~~~~
-- bsbrao 09/27/04
-- ^^^^^^
-- Created version 1.02e to upgrade IPIF from opb_ipif_v1_23_a to
-- opb_ipif_v3_01_a
-- ~~~~~~
-- GAB 07/05/05
-- ^^^^^^
-- Fixed XST issue in ipif_regonly_slave.vhd. This fixes CR211277.
-- ~~~~~~
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.STD_LOGIC_SIGNED.all;
-- OPB_ARB_PKG contains the necessary constants and functions for the
-- OPB Arbiter
library opb_v20_v1_10_d;
use opb_v20_v1_10_d.opb_arb_pkg.all;
use opb_v20_v1_10_d.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_BASEADDR -- OPB Arbiter base address
-- C_HIGHADDR -- OPB Arbiter high address
-- C_NUM_MASTERS -- number of OPB masters
-- C_OPBDATA_WIDTH -- width of OPB data bus
-- C_OPBADDR_WIDTH -- width of OPB address bus
-- C_DYNAM_PRIORITY -- dynamic or fixed priority
-- C_REG_GRANTS -- registered or combinational grant outputs
-- C_PARK -- bus parking
-- C_PROC_INTRFCE -- OPB slave interface
-- C_DEV_BLK_ID -- device block id
-- C_DEV_MIR_ENABLE -- IPIF mirror capability enable
--
-- Definition of Ports:
--
-- output ARB_DBus -- Arbiter's data bus to OPB
-- output ARB_ErrAck -- Arbiter's error acknowledge - unused
-- output ARB_Retry -- Arbiter's retry signal - unused
-- output ARB_XferAck -- Arbiter's xfer acknowledge
-- input OPB_Clk -- Clock
-- input M_request -- Masters' request signals
-- input OPB_Abus -- OPB Address bus
-- input OPB_BE -- OPB Byte Enables
-- input OPB_buslock -- Bus lock
-- input OPB_Dbus -- OPB Data bus
-- output OPB_MGrant -- Masters' grant signals
-- input OPB_retry -- Retry
-- input OPB_RNW -- Read not Write
-- input OPB_select -- Master has control of bus
-- input OPB_seqAddr -- Sequential Address
-- output OPB_timeout -- Timeout
-- input OPB_toutSup -- Timeout suppress
-- input OPB_xferAck -- OPB xfer acknowledge
-- input OPB_Rst -- Reset
--
-------------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity opb_arbiter_core is
generic (
C_BASEADDR : std_logic_vector;
C_HIGHADDR : std_logic_vector;
C_NUM_MASTERS : integer := 4;
C_OPBDATA_WIDTH : integer := 32;
C_OPBADDR_WIDTH : integer := 32;
C_DYNAM_PRIORITY : boolean := False;
C_REG_GRANTS : boolean := True;
C_PARK : boolean := False;
C_PROC_INTRFCE : boolean := False;
C_DEV_BLK_ID : integer := 0;
C_DEV_MIR_ENABLE : integer := 0
);
port (
ARB_DBus : out std_logic_vector(0 to C_OPBDATA_WIDTH-1);
ARB_ErrAck : out std_logic;
ARB_Retry : out std_logic;
ARB_ToutSup : out std_logic;
ARB_XferAck : out std_logic;
OPB_Clk : in std_logic;
M_request : in std_logic_vector(0 to C_NUM_MASTERS-1);
OPB_Abus : in std_logic_vector(0 to C_OPBADDR_WIDTH-1);
OPB_BE : in std_logic_vector(0 to C_OPBDATA_WIDTH/8-1);
OPB_buslock : in std_logic;
OPB_Dbus : in std_logic_vector(0 to C_OPBDATA_WIDTH-1);
OPB_MGrant : out std_logic_vector(0 to C_NUM_MASTERS-1);
OPB_retry : in std_logic;
OPB_RNW : in std_logic;
OPB_select : in std_logic;
OPB_seqAddr : in std_logic;
OPB_timeout : out std_logic;
OPB_toutSup : in std_logic;
OPB_xferAck : in std_logic;
OPB_Rst : in std_logic
);
end opb_arbiter_core;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of opb_arbiter_core is
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant NUM_MID_BITS : integer := max2(1,log2(C_NUM_MASTERS));
constant PMID_START_LOC : integer := C_OPBDATA_WIDTH - NUM_MID_BITS;
constant DEV_ADDR_DECODE_WIDTH : integer :=
Addr_Bits(C_BASEADDR,C_HIGHADDR,C_OPBADDR_WIDTH);
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
-- internal connections
signal arb2bus_data : std_logic_vector(0 to C_OPBDATA_WIDTH-1);
signal arb2bus_rdack : std_logic;
signal arb2bus_wrack : std_logic;
signal arb_cycle : std_logic;
signal any_mgrant : std_logic;
signal bus2ip_data : std_logic_vector(0 to C_OPBDATA_WIDTH-1);
signal bus2ip_reg_rdce : std_logic_vector(0 to C_NUM_MASTERS);
signal bus2ip_reg_wrce : std_logic_vector(0 to C_NUM_MASTERS);
signal bus_park : std_logic;
signal ctrl_reg : std_logic_vector(0 to C_OPBDATA_WIDTH-1);
signal grant : std_logic_vector(0 to C_NUM_MASTERS-1);
signal mgrant : std_logic_vector(0 to C_NUM_MASTERS-1);
signal mgrant_n : std_logic_vector(0 to C_NUM_MASTERS-1);
signal opb_mgrant_i : std_logic_vector(0 to C_NUM_MASTERS-1);
signal opb_timeout_i : std_logic;
signal priority_IDs : std_logic_vector(0 to C_NUM_MASTERS * NUM_MID_BITS-1);
signal priority_register: std_logic_vector(0 to C_NUM_MASTERS * C_OPBDATA_WIDTH-1);
signal clk : std_logic;
signal rst : std_logic;
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
-- none
-----------------------------------------------------------------------------
-- Begin architecture
-----------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Assign internal grant signals to output port
-------------------------------------------------------------------------------
OPB_MGrant <= opb_mgrant_i;
OPB_timeout <= opb_timeout_i;
-------------------------------------------------------------------------------
-- Instantiate logic as determined by parameter values. Note that the
-- OPB Arbiter will always contain a watchdog timer, regardless of the number
-- of masters on the bus or the other features specified.
-------------------------------------------------------------------------------
WATCHDOG_TIMER_I: entity opb_v20_v1_10_d.watchdog_timer
port map (
OPB_select => OPB_select,
OPB_xferAck => OPB_xferAck,
OPB_retry => OPB_retry,
OPB_toutSup => OPB_toutSup,
OPB_timeout => opb_timeout_i,
Clk => clk,
Rst => rst);
-------------------------------------------------------------------------------
-- Number of Masters
-- If the number of masters is 1, then simply assign the OPB_MGrant output of
-- the OPB Arbiter to '1'.
-------------------------------------------------------------------------------
SINGLE_MASTER_GEN: if C_NUM_MASTERS = 1 generate
opb_mgrant_i <= (others => '1');
ARB_DBus <= (others => '0');
ARB_ErrAck <= '0';
ARB_Retry <= '0';
ARB_ToutSup <= '0';
ARB_XferAck <= '0';
clk <= OPB_Clk;
rst <= OPB_Rst;
end generate SINGLE_MASTER_GEN;
-------------------------------------------------------------------------------
-- Number of Masters
-- If the number of masters is > 1, then the arbiter needs the logic components
-- define below.
-------------------------------------------------------------------------------
MULTI_MASTER_GEN: if C_NUM_MASTERS > 1 generate
---------------------------------------------------------------------------
-- CONTROL_REGISTER_LOGIC contains the control register
---------------------------------------------------------------------------
CTRLREG_I: entity opb_v20_v1_10_d.control_register_logic
generic map (C_OPBDATA_WIDTH => C_OPBDATA_WIDTH,
C_NUM_MID_BITS => NUM_MID_BITS,
C_DYNAM_PRIORITY => C_DYNAM_PRIORITY,
C_PARK => C_PARK,
C_PROC_INTRFCE => C_PROC_INTRFCE)
port map (
Ctrlreg_wrce => bus2ip_reg_wrce(0),
Bus2Ip_Data => bus2ip_data(0 to C_OPBDATA_WIDTH - 1),
Ctrl_reg => ctrl_reg(0 to C_OPBDATA_WIDTH - 1),
Clk => clk,
Rst => rst);
---------------------------------------------------------------------------
-- PRIORITY_REGISTER_LOGIC contains the priority register and update logic
---------------------------------------------------------------------------
PRIORITY_REGS_I: entity opb_v20_v1_10_d.priority_register_logic
generic map (C_NUM_MASTERS => C_NUM_MASTERS,
C_OPBDATA_WIDTH => C_OPBDATA_WIDTH,
C_NUM_MID_BITS => NUM_MID_BITS,
C_DYNAM_PRIORITY => C_DYNAM_PRIORITY)
port map (
MGrant => mgrant(0 to C_NUM_MASTERS-1),
MGrant_n => mgrant_n(0 to C_NUM_MASTERS-1),
Bus2IP_Data => bus2ip_data(0 to C_OPBDATA_WIDTH-1),
Bus2IP_Reg_WrCE => bus2ip_reg_wrce(1 to C_NUM_MASTERS),
Dpen => ctrl_reg(DPEN_LOC),
Prv => ctrl_reg(PRV_LOC),
Priority_register => priority_register,
Priority_IDs => Priority_IDs,
Clk => clk,
Rst => rst);
---------------------------------------------------------------------------
-- Only instantiate the OPB Bus slave components if the design has been
-- parameterized to support a processor interface
-- Otherwise, set ports and interface signals to GND
---------------------------------------------------------------------------
OPBSLAVE_GEN: if C_PROC_INTRFCE generate
IPIF_I: entity opb_v20_v1_10_d.ipif_regonly_slave
generic map (C_OPB_ABUS_WIDTH => C_OPBADDR_WIDTH,
C_OPB_DBUS_WIDTH => C_OPBDATA_WIDTH,
C_BASEADDR => C_BASEADDR,
C_NUM_MASTERS => C_NUM_MASTERS,
C_NUM_MID_BITS => NUM_MID_BITS,
C_DEV_BLK_ID => C_DEV_BLK_ID,
C_DEV_MIR_ENABLE => C_DEV_MIR_ENABLE,
C_DEV_ADDR_DECODE_WIDTH => DEV_ADDR_DECODE_WIDTH)
port map (
Bus2IP_Data => bus2ip_data,
Bus2IP_Reg_RdCE => bus2ip_reg_rdce,
Bus2IP_Reg_WrCE => bus2ip_reg_wrce,
Bus2IP_Clk => clk,
Bus2IP_Reset => rst,
IP2Bus_Data => arb2bus_data,
IP2Bus_RdAck => arb2bus_rdack,
IP2Bus_WrAck => arb2bus_wrack,
OPB_ABus => OPB_Abus,
OPB_BE => OPB_BE,
OPB_Clk => OPB_Clk,
OPB_DBus => OPB_Dbus,
OPB_RNW => OPB_RNW,
OPB_Select => OPB_select,
OPB_seqAddr => OPB_seqAddr,
Rst => OPB_Rst,
Sln_DBus => ARB_DBus,
Sln_ErrAck => ARB_ErrAck,
Sln_Retry => ARB_Retry,
Sln_ToutSup => ARB_ToutSup,
Sln_XferAck => ARB_XferAck);
ARB2BUS_DATAMUX_I: entity opb_v20_v1_10_d.arb2bus_data_mux
generic map (C_NUM_MASTERS => C_NUM_MASTERS,
C_OPBDATA_WIDTH=> C_OPBDATA_WIDTH)
port map (
Bus2IP_Reg_RdCE => bus2ip_reg_rdce(0 to C_NUM_MASTERS),
Bus2IP_Reg_WrCE => bus2ip_reg_wrce(0 to C_NUM_MASTERS),
Ctrl_reg => ctrl_reg,
Priority_regs => priority_register,
Arb2bus_wrack => arb2bus_wrack,
Arb2bus_rdack => arb2bus_rdack,
Arb2bus_data => arb2bus_data);
end generate OPBSLAVE_GEN;
NO_OPBSLAVE_GEN: if not(C_PROC_INTRFCE) generate
bus2ip_data <= (others => '0');
bus2ip_reg_rdce <= (others => '0');
bus2ip_reg_wrce <= (others => '0');
ARB_DBus <= (others => '0');
ARB_ErrAck <= '0';
ARB_Retry <= '0';
ARB_ToutSup <= '0';
ARB_XferAck <= '0';
clk <= OPB_Clk;
rst <= OPB_Rst;
end generate NO_OPBSLAVE_GEN;
------------------------------------------------------------------------
-- ARBITRATION_LOGIC determines the priority level of each recieved
-- Master's request and determines the intermediate grant signal for
-- each Master.
------------------------------------------------------------------------
ARB_LOGIC_I: entity opb_v20_v1_10_d.arbitration_logic
generic map (C_NUM_MASTERS => C_NUM_MASTERS,
C_NUM_MID_BITS => NUM_MID_BITS,
C_OPBDATA_WIDTH => C_OPBDATA_WIDTH,
C_DYNAM_PRIORITY => C_DYNAM_PRIORITY,
C_REG_GRANTS => C_REG_GRANTS)
port map (
OPB_select => OPB_select,
OPB_xferAck => OPB_xferAck,
M_request => M_request(0 to C_NUM_MASTERS-1),
Bus_park => bus_park,
Any_mgrant => any_mgrant,
OPB_buslock => OPB_buslock,
Priority_ids => Priority_IDs(0 to
C_NUM_MASTERS * NUM_MID_BITS-1),
Arb_cycle => arb_cycle,
Grant => grant(0 to C_NUM_MASTERS-1),
Clk => clk,
Rst => rst);
---------------------------------------------------------------------------
-- PARK_LOCK_LOGIC determines which Master has locked the bus (if any) and
-- which Master the bus should park on (if enabled). It then determines the
-- final grant signal for each Master based on the intermediate grants from
-- the arbitration logic and the park/lock status of the bus. If parking is
-- not supported, this block eliminates the park logic.
---------------------------------------------------------------------------
PARK_LOCK_I: entity opb_v20_v1_10_d.park_lock_logic
generic map (C_NUM_MASTERS => C_NUM_MASTERS,
C_NUM_MID_BITS => NUM_MID_BITS,
C_PARK => C_PARK,
C_REG_GRANTS => C_REG_GRANTS)
port map (
Arb_cycle => arb_cycle,
OPB_buslock => OPB_buslock,
Park_master_notlast => ctrl_reg(PMN_LOC),
Park_master_id => ctrl_reg(PMID_START_LOC to C_OPBDATA_WIDTH-1),
Park_enable => ctrl_reg(PEN_LOC),
Grant => grant(0 to C_NUM_MASTERS-1),
M_request => M_request(0 to C_NUM_MASTERS-1),
Bus_park => bus_park,
Any_mgrant => any_mgrant,
OPB_Mgrant => opb_mgrant_i(0 to C_NUM_MASTERS-1),
Mgrant => mgrant(0 to C_NUM_MASTERS-1),
MGrant_n => mgrant_n(0 to C_NUM_MASTERS-1),
Clk => clk,
Rst => rst);
end generate MULTI_MASTER_GEN;
end implementation;
|
bsd-3-clause
|
masson2013/heterogeneous_hthreads
|
src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/opb_ipif_v2_00_h/hdl/vhdl/pf_occ_counter.vhd
|
3
|
6847
|
-------------------------------------------------------------------------------
-- $Id: pf_occ_counter.vhd,v 1.2 2004/11/23 01:04:03 jcanaris Exp $
-------------------------------------------------------------------------------
-- pf_occ_counter - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: pf_occ_counter.vhd
--
-- Description: Implements packet fifo occupancy counter. This special
-- counter provides these functions:
-- - up/down count control
-- - pre-increment/pre-decrement of input load value
-- - count by 2
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pf_occ_counter.vhd
--
-------------------------------------------------------------------------------
-- Author: B.L. Tise
-- Revision: $Revision: 1.2 $
-- Date: $Date: 2004/11/23 01:04:03 $
--
-- History:
-- D. Thorpe 2001-09-07 First Version
-- - adapted from B Tise MicroBlaze counters
--
-- DET 2001-09-11
-- - Added the Rst signal connect to the pf_counter_bit module
-- LCW Nov 8, 2004 -- updated for NCSim
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
library opb_ipif_v2_00_h;
use opb_ipif_v2_00_h.pf_counter_bit;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity pf_occ_counter is
generic (
C_COUNT_WIDTH : integer := 9
);
port (
Clk : in std_logic;
Rst : in std_logic;
Carry_Out : out std_logic;
Load_In : in std_logic_vector(0 to C_COUNT_WIDTH-1);
Count_Enable : in std_logic;
Count_Load : in std_logic;
Count_Down : in std_logic;
Cnt_by_2 : In std_logic;
Count_Out : out std_logic_vector(0 to C_COUNT_WIDTH-1)
);
end entity pf_occ_counter;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of pf_occ_counter is
constant CY_START : integer := 1;
signal alu_cy : std_logic_vector(0 to C_COUNT_WIDTH-1);
signal iCount_Out : std_logic_vector(0 to C_COUNT_WIDTH-2);
signal i_mux_Count_Out : std_logic_vector(0 to C_COUNT_WIDTH-2);
signal count_clock_en : std_logic;
signal carry_out_lsb : std_logic;
signal carry_in_lsb : std_logic;
signal count_out_lsb : std_logic;
Signal mux_cnt_in_lsb : std_logic;
Signal carry_out_select_di: std_logic;
Signal carry_start : std_logic;
Signal carry_start_select : std_logic;
Signal by_2_carry_start : std_logic;
begin -- VHDL_RTL
-----------------------------------------------------------------------------
-- Generate the Counter bits
-----------------------------------------------------------------------------
count_clock_en <= Count_Enable or Count_Load;
MUX_THE_LSB_INPUT : process (count_out_lsb, Load_In, Count_Load)
Begin
If (Count_Load = '0') Then
mux_cnt_in_lsb <= count_out_lsb;
else
mux_cnt_in_lsb <= Load_In(C_COUNT_WIDTH-1);
End if;
End process MUX_THE_LSB_INPUT;
carry_start <= Count_Down xor Count_Enable;
by_2_carry_start <= Cnt_by_2 and Count_Down;
carry_start_select <= not(Cnt_by_2);
I_MUXCY_LSB_IN : MUXCY_L
port map (
DI => by_2_carry_start,
CI => carry_start,
S => carry_start_select,
LO => carry_in_lsb);
I_COUNTER_BIT_LSB : entity opb_ipif_v2_00_h.pf_counter_bit
port map (
Clk => Clk,
Rst => Rst,
Count_In => mux_cnt_in_lsb,
Load_In => '0',
Count_Load => '0',
Count_Down => Count_Down,
Carry_In => carry_in_lsb,
Clock_Enable => count_clock_en,
Result => count_out_lsb,
Carry_Out => carry_out_lsb);
carry_out_select_di <= Count_Down xor Cnt_by_2;
I_MUXCY_LSB_OUT : MUXCY_L
port map (
DI => carry_out_select_di,
CI => carry_out_lsb,
S => carry_start_select,
LO => alu_cy(C_COUNT_WIDTH-1));
I_ADDSUB_GEN : for i in 0 to C_COUNT_WIDTH-2 generate
begin
MUX_THE_INPUT : process (iCount_Out, Load_In, Count_Load)
Begin
If (Count_Load = '0') Then
i_mux_Count_Out(i) <= iCount_Out(i);
else
i_mux_Count_Out(i) <= Load_In(i);
End if;
End process MUX_THE_INPUT;
Counter_Bit_I : entity opb_ipif_v2_00_h.pf_counter_bit
port map (
Clk => Clk,
Rst => Rst,
Count_In => i_mux_Count_Out(i),
Load_In => '0',
Count_Load => '0',
Count_Down => Count_Down,
Carry_In => alu_cy(i+1),
Clock_Enable => count_clock_en,
Result => iCount_Out(i),
Carry_Out => alu_cy(i));
end generate I_ADDSUB_GEN;
Count_Out <= iCount_Out & count_out_lsb;
Carry_Out <= '0';
end architecture implementation;
|
bsd-3-clause
|
masson2013/heterogeneous_hthreads
|
src/platforms/xilinx/numa3_hwti/design/pcores/plb_scheduler_v1_00_a/hdl/vhdl/infer_bram.vhd
|
12
|
4270
|
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
-- *************************************************************************
-- File: infer_bram.vhd
-- Date: 06/15/05
-- Purpose: File used to instantiate an inferred BRAM (single port)
-- Author: Jason Agron
-- *************************************************************************
-- *************************************************************************
-- Library declarations
-- *************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_misc.all;
use IEEE.numeric_std.all;
library Unisim;
use Unisim.all;
library Unisim;
use Unisim.all;
-- *************************************************************************
-- Entity declaration
-- *************************************************************************
entity infer_bram is
generic (
ADDRESS_BITS : integer := 9;
DATA_BITS : integer := 32
);
port (
CLKA : in std_logic;
ENA : in std_logic;
WEA : in std_logic;
ADDRA : in std_logic_vector(0 to ADDRESS_BITS - 1);
DIA : in std_logic_vector(0 to DATA_BITS - 1);
DOA : out std_logic_vector(0 to DATA_BITS - 1)
);
end entity infer_bram;
-- *************************************************************************
-- Architecture declaration
-- *************************************************************************
architecture implementation of infer_bram is
-- Constant declarations
constant BRAM_SIZE : integer := 2 **ADDRESS_BITS; -- # of entries in the inferred BRAM
-- BRAM data storage (array)
type bram_storage is array( 0 to BRAM_SIZE - 1 ) of std_logic_vector( 0 to DATA_BITS - 1 );
signal BRAM_DATA : bram_storage;
begin
-- *************************************************************************
-- Process: BRAM_CONTROLLER_A
-- Purpose: Controller for inferred BRAM, BRAM_DATA
-- *************************************************************************
BRAM_CONTROLLER_A : process(CLKA) is
begin
if( CLKA'event and CLKA = '1' ) then
if( ENA = '1' ) then
if( WEA = '1' ) then
BRAM_DATA( conv_integer(ADDRA) ) <= DIA;
end if;
DOA <= BRAM_DATA( conv_integer(ADDRA) );
end if;
end if;
end process BRAM_CONTROLLER_A;
end architecture implementation;
|
bsd-3-clause
|
masson2013/heterogeneous_hthreads
|
src/hardware/MyRepository/pcores/axi_hthread_cores/fsl_v20_v2_11_f/hdl/vhdl/fsl_v20.vhd
|
2
|
17211
|
-------------------------------------------------------------------------------
-- $Id: fsl_v20.vhd,v 1.1.2.1 2010/10/28 11:17:56 goran Exp $
-------------------------------------------------------------------------------
-- fsl_v20.vhd - Entity and architecture
--
-- (c) Copyright [2003] - [2010] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES
--
-------------------------------------------------------------------------------
-- Filename: fsl_v20.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- fsl_v20.vhdenv\Databases\ip2\processor\hardware\doc\bram_block\bram_block_v1_00_a
--
-------------------------------------------------------------------------------
-- Author: satish
-- Revision: $Revision: 1.1.2.1 $
-- Date: $Date: 2010/10/28 11:17:56 $
--
-- History:
-- satish 2003-02-13 First Version
-- satish 2004-03-03 New Version
-- rolandp 2006-08-20 BRAM in asynch mode
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library Unisim;
use Unisim.vcomponents.all;
library fsl_v20_v2_11_f;
use fsl_v20_v2_11_f.sync_fifo;
use fsl_v20_v2_11_f.async_fifo;
entity fsl_v20 is
generic (
C_EXT_RESET_HIGH : integer := 1;
C_ASYNC_CLKS : integer := 0;
C_IMPL_STYLE : integer := 0;
C_USE_CONTROL : integer := 1;
C_FSL_DWIDTH : integer := 32;
C_FSL_DEPTH : integer := 16;
C_READ_CLOCK_PERIOD : integer := 0
);
port (
-- Clock and reset signals
FSL_Clk : in std_logic;
SYS_Rst : in std_logic;
FSL_Rst : out std_logic;
-- FSL master signals
FSL_M_Clk : in std_logic;
FSL_M_Data : in std_logic_vector(0 to C_FSL_DWIDTH-1);
FSL_M_Control : in std_logic;
FSL_M_Write : in std_logic;
FSL_M_Full : out std_logic;
-- FSL slave signals
FSL_S_Clk : in std_logic;
FSL_S_Data : out std_logic_vector(0 to C_FSL_DWIDTH-1);
FSL_S_Control : out std_logic;
FSL_S_Read : in std_logic;
FSL_S_Exists : out std_logic;
-- FIFO status signals
FSL_Full : out std_logic;
FSL_Has_Data : out std_logic;
FSL_Control_IRQ : out std_logic
);
end entity fsl_v20;
architecture IMP of fsl_v20 is
component Sync_FIFO is
generic (
C_IMPL_STYLE : Integer;
WordSize : Integer;
MemSize : Integer);
port (
Reset : in Std_Logic;
Clk : in Std_Logic;
WE : in Std_Logic;
DataIn : in Std_Logic_Vector(WordSize-1 downto 0);
Full : out Std_Logic;
RD : in Std_Logic;
DataOut : out Std_Logic_Vector(WordSize-1 downto 0);
Exists : out Std_Logic);
end component Sync_FIFO;
component Async_FIFO is
generic (
WordSize : Integer;
MemSize : Integer;
Protect : Boolean);
port (
Reset : in Std_Logic;
-- Clock region WrClk
WrClk : in Std_Logic;
WE : in Std_Logic;
DataIn : in Std_Logic_Vector(WordSize-1 downto 0);
Full : out Std_Logic;
-- Clock region RdClk
RdClk : in Std_Logic;
RD : in Std_Logic;
DataOut : out Std_Logic_Vector(WordSize-1 downto 0);
Exists : out Std_Logic);
end component Async_FIFO;
component Async_FIFO_BRAM is
generic (
WordSize : Integer;
MemSize : Integer;
Protect : Boolean);
port (
Reset : in Std_Logic;
-- Clock region WrClk
WrClk : in Std_Logic;
WE : in Std_Logic;
DataIn : in Std_Logic_Vector(WordSize-1 downto 0);
Full : out Std_Logic;
-- Clock region RdClk
RdClk : in Std_Logic;
RD : in Std_Logic;
DataOut : out Std_Logic_Vector(WordSize-1 downto 0);
Exists : out Std_Logic);
end component Async_FIFO_BRAM;
signal sys_rst_i : std_logic;
signal srl_time_out : std_logic;
signal fsl_rst_i : std_logic;
signal Data_In : std_logic_vector(0 to C_FSL_DWIDTH);
signal Data_Out : std_logic_vector(0 to C_FSL_DWIDTH);
signal fifo_full : std_logic;
-- signal fifo_half_full : std_logic;
-- signal fifo_half_empty : std_logic;
signal fifo_has_data : std_logic;
signal fsl_s_control_i : std_logic;
signal srl_clk : std_logic;
begin -- architecture IMP
SYS_RST_PROC : process (SYS_Rst) is
variable sys_rst_input : std_logic;
begin
if C_EXT_RESET_HIGH = 0 then
sys_rst_i <= not SYS_Rst;
else
sys_rst_i <= SYS_Rst;
end if;
end process SYS_RST_PROC;
Rst_Delay_Async: if (C_ASYNC_CLKS /= 0) generate
srl_clk <= FSL_M_Clk;
end generate Rst_Delay_Async;
Rst_Delay_Sync: if (C_ASYNC_CLKS = 0) generate
srl_clk <= FSL_Clk;
end generate Rst_Delay_Sync;
POR_SRL_I : SRL16
generic map (
INIT => X"FFFF")
port map (
D => '0',
CLK => srl_Clk,
A0 => '1',
A1 => '1',
A2 => '1',
A3 => '1',
Q => srl_time_out);
POR_FF_I : FDS
port map (
Q => fsl_rst_i,
D => srl_time_out,
C => srl_Clk,
S => sys_rst_i);
FSL_Rst <= fsl_rst_i;
-----------------------------------------------------------------------------
-- Width is 1, so implement a registers
-----------------------------------------------------------------------------
Only_Register : if (C_FSL_DEPTH = 1) generate
signal fsl_s_exists_i : std_logic;
signal fsl_m_full_i : std_logic;
begin
-- FSL_S_Clk and FSL_M_Clk are the same
Sync_Clocks: if (C_ASYNC_CLKS = 0) generate
FIFO : process (FSL_Clk) is
variable fifo_full : std_logic;
begin -- process FIFO
if FSL_Clk'event and FSL_Clk = '1' then -- rising clock edge
if fsl_rst_i = '1' then -- synchronous reset (active high)
fifo_full := '0';
Fsl_m_full_i <= '1';
Fsl_s_exists_i <= '0';
else
if (fifo_full = '0') then -- Empty
if (FSL_M_Write = '1') then
fifo_full := '1';
FSL_S_Data <= FSL_M_Data;
fsl_s_control_i <= FSL_M_Control;
end if;
end if;
if (fifo_full = '1') then -- Has data
if (FSL_S_Read = '1') then
fifo_full := '0';
end if;
end if;
Fsl_m_full_i <= fifo_full;
Fsl_s_exists_i <= fifo_full;
end if;
end if;
end process FIFO;
end generate Sync_Clocks;
FSL_S_Exists <= fsl_s_exists_i;
FSL_Has_Data <= fsl_s_exists_i;
FSL_M_Full <= fsl_m_full_i;
FSL_Full <= fsl_m_full_i;
FSL_S_Control <= fsl_s_control_i when C_USE_CONTROL /= 0 else '0';
FSL_Control_IRQ <= fsl_s_control_i and fsl_s_exists_i when C_USE_CONTROL /= 0 else '0';
end generate Only_Register;
Using_FIFO: if (C_FSL_DEPTH > 1) generate
begin
-- Map Master Data/Control signal
Data_In(0 to C_FSL_DWIDTH-1) <= FSL_M_Data;
-- Map Slave Data/Control signal
FSL_S_Data <= Data_Out(0 to C_FSL_DWIDTH-1);
-- SRL FIFO BASED IMPLEMENTATION
Sync_FIFO_Gen : if (C_ASYNC_CLKS = 0) generate
Use_Control: if (C_USE_CONTROL /= 0) generate
Data_In(C_FSL_DWIDTH) <= FSL_M_Control;
fsl_s_control_i <= Data_Out(C_FSL_DWIDTH);
Sync_FIFO_I1 : Sync_FIFO
generic map (
C_IMPL_STYLE => C_IMPL_STYLE,
WordSize => C_FSL_DWIDTH + 1,
MemSize => C_FSL_DEPTH)
port map (
Reset => fsl_rst_i,
Clk => FSL_Clk,
WE => FSL_M_Write,
DataIn => Data_In,
Full => fifo_full,
RD => FSL_S_Read,
DataOut => Data_Out,
Exists => fifo_has_data);
end generate Use_Control;
Use_Data: if (C_USE_CONTROL = 0) generate
fsl_s_control_i <= '0';
Sync_FIFO_I1 : Sync_FIFO
generic map (
C_IMPL_STYLE => C_IMPL_STYLE,
WordSize => C_FSL_DWIDTH,
MemSize => C_FSL_DEPTH)
port map (
Reset => fsl_rst_i,
Clk => FSL_Clk,
WE => FSL_M_Write,
DataIn => Data_In(0 to C_FSL_DWIDTH-1),
Full => fifo_full,
RD => FSL_S_Read,
DataOut => Data_Out(0 to C_FSL_DWIDTH-1),
Exists => fifo_has_data);
end generate Use_Data;
end generate Sync_FIFO_Gen;
Async_FIFO_Gen: if (C_ASYNC_CLKS /= 0) generate
Use_Control: if (C_USE_CONTROL /= 0) generate
Data_In(C_FSL_DWIDTH) <= FSL_M_Control;
fsl_s_control_i <= Data_Out(C_FSL_DWIDTH);
Use_DPRAM1: if (C_IMPL_STYLE = 0) generate
-- LUT RAM implementation
Async_FIFO_I1: Async_FIFO
generic map (
WordSize => C_FSL_DWIDTH + 1, -- [Integer]
MemSize => C_FSL_DEPTH, -- [Integer]
Protect => true) -- [Boolean]
port map (
Reset => fsl_rst_i, -- [in Std_Logic]
-- Clock region WrClk
WrClk => FSL_M_Clk, -- [in Std_Logic]
WE => FSL_M_Write, -- [in Std_Logic]
DataIn => Data_In, -- [in Std_Logic_Vector(WordSize-1 downto 0)]
Full => fifo_full, -- [out Std_Logic]
-- Clock region RdClk
RdClk => FSL_S_Clk, -- [in Std_Logic]
RD => FSL_S_Read, -- [in Std_Logic]
DataOut => Data_Out, -- [out Std_Logic_Vector(WordSize-1 downto 0)]
Exists => fifo_has_data); -- [out Std_Logic]
end generate Use_DPRAM1;
Use_BRAM1: if (C_IMPL_STYLE /= 0) generate
-- BRAM implementation
Async_FIFO_BRAM_I1 : Async_FIFO_BRAM
generic map (
WordSize => C_FSL_DWIDTH + 1, -- [Integer]
MemSize => C_FSL_DEPTH, -- [Integer]
Protect => true) -- [Boolean]
port map (
Reset => fsl_rst_i, -- [in Std_Logic]
-- Clock region WrClk
WrClk => FSL_M_Clk, -- [in Std_Logic]
WE => FSL_M_Write, -- [in Std_Logic]
DataIn => Data_In, -- [in Std_Logic_Vector(WordSize-1 downto 0)]
Full => fifo_full, -- [out Std_Logic]
-- Clock region RdClk
RdClk => FSL_S_Clk, -- [in Std_Logic]
RD => FSL_S_Read, -- [in Std_Logic]
DataOut => Data_Out, -- [out Std_Logic_Vector(WordSize-1 downto 0)]
Exists => fifo_has_data); -- [out Std_Logic]
end generate Use_BRAM1;
end generate Use_Control;
Use_Data: if (C_USE_CONTROL = 0) generate
fsl_s_control_i <= '0';
Use_DPRAM0: if (C_IMPL_STYLE = 0) generate
-- LUT RAM implementation
Async_FIFO_I1 : Async_FIFO
generic map (
WordSize => C_FSL_DWIDTH, -- [Integer]
MemSize => C_FSL_DEPTH, -- [Integer]
Protect => true) -- [Boolean]
port map (
Reset => fsl_rst_i, -- [in Std_Logic]
-- Clock region WrClk
WrClk => FSL_M_Clk, -- [in Std_Logic]
WE => FSL_M_Write, -- [in Std_Logic]
DataIn => Data_In(0 to C_FSL_DWIDTH-1), -- [in Std_Logic_Vector(WordSize-1 downto 0)]
Full => fifo_full, -- [out Std_Logic]
-- Clock region RdClk
RdClk => FSL_S_Clk, -- [in Std_Logic]
RD => FSL_S_Read, -- [in Std_Logic]
DataOut => Data_Out(0 to C_FSL_DWIDTH-1), -- [out Std_Logic_Vector(WordSize-1 downto 0)]
Exists => fifo_has_data); -- [out Std_Logic]
end generate Use_DPRAM0;
Use_BRAM0: if (C_IMPL_STYLE /= 0) generate
-- BRAM implementation
Async_FIFO_BRAM_I1 : Async_FIFO_BRAM
generic map (
WordSize => C_FSL_DWIDTH, -- [Integer]
MemSize => C_FSL_DEPTH, -- [Integer]
Protect => true) -- [Boolean]
port map (
Reset => fsl_rst_i, -- [in Std_Logic]
-- Clock region WrClk
WrClk => FSL_M_Clk, -- [in Std_Logic]
WE => FSL_M_Write, -- [in Std_Logic]
DataIn => Data_In(0 to C_FSL_DWIDTH-1), -- [in Std_Logic_Vector(WordSize-1 downto 0)]
Full => fifo_full, -- [out Std_Logic]
-- Clock region RdClk
RdClk => FSL_S_Clk, -- [in Std_Logic]
RD => FSL_S_Read, -- [in Std_Logic]
DataOut => Data_Out(0 to C_FSL_DWIDTH-1), -- [out Std_Logic_Vector(WordSize-1 downto 0)]
Exists => fifo_has_data); -- [out Std_Logic]
end generate Use_BRAM0;
end generate Use_Data;
end generate Async_FIFO_Gen;
FSL_M_Full <= fifo_full or fsl_rst_i; -- Inhibit writes during reset by
-- forcing full to '1'
FSL_S_Exists <= fifo_has_data;
FSL_Full <= fifo_full;
FSL_Has_Data <= fifo_has_data;
FSL_S_Control <= fsl_s_control_i;
FSL_Control_IRQ <= fsl_s_control_i and fifo_has_data;
end generate Using_FIFO;
end architecture IMP;
|
bsd-3-clause
|
masson2013/heterogeneous_hthreads
|
src/platforms/xilinx/smp1/design/pcores/plb_cond_vars_v1_00_a/hdl/vhdl/abc.vhd
|
9
|
24027
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library fsl_v20_v2_11_a;
use fsl_v20_v2_11_a.all;
-- Definition of Generics:
-- C_SLV_DWIDTH -- Slave interface data bus width
-- C_MST_AWIDTH -- Master interface address bus width
-- C_MST_DWIDTH -- Master interface data bus width
-- C_NUM_REG -- Number of software accessible registers
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Reset -- Bus to IP reset
-- Bus2IP_Addr -- Bus to IP address bus
-- Bus2IP_Data -- Bus to IP data bus
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- IP2Bus_Data -- IP to Bus data bus
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- IP2Bus_Error -- IP to Bus error response
-- IP2Bus_MstRd_Req -- IP to Bus master read request
-- IP2Bus_MstWr_Req -- IP to Bus master write request
-- IP2Bus_Mst_Addr -- IP to Bus master address bus
-- IP2Bus_Mst_BE -- IP to Bus master byte enables
-- IP2Bus_Mst_Lock -- IP to Bus master lock
-- IP2Bus_Mst_Reset -- IP to Bus master reset
-- Bus2IP_Mst_CmdAck -- Bus to IP master command acknowledgement
-- Bus2IP_Mst_Cmplt -- Bus to IP master transfer completion
-- Bus2IP_Mst_Error -- Bus to IP master error response
-- Bus2IP_Mst_Rearbitrate -- Bus to IP master re-arbitrate
-- Bus2IP_Mst_Cmd_Timeout -- Bus to IP master command timeout
-- Bus2IP_MstRd_d -- Bus to IP master read data bus
-- Bus2IP_MstRd_src_rdy_n -- Bus to IP master read source ready
-- IP2Bus_MstWr_d -- IP to Bus master write data bus
-- Bus2IP_MstWr_dst_rdy_n -- Bus to IP master write destination ready
entity user_logic is
generic
(
C_THREAD_MANAGER_BASEADDR : std_logic_vector := x"11000000";
C_SLV_DWIDTH : integer := 32;
C_MST_AWIDTH : integer := 32;
C_MST_DWIDTH : integer := 32;
C_NUM_REG : integer := 5
);
port
(
Soft_Reset : in std_logic;
Reset_Done : out std_logic;
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Addr : in std_logic_vector(0 to 31);
Bus2IP_Data : in std_logic_vector(0 to C_SLV_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_SLV_DWIDTH/8-1);
Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_REG-1);
Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_REG-1);
IP2Bus_Data : out std_logic_vector(0 to C_SLV_DWIDTH-1);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic;
IP2Bus_MstRd_Req : out std_logic;
IP2Bus_MstWr_Req : out std_logic;
IP2Bus_Mst_Addr : out std_logic_vector(0 to C_MST_AWIDTH-1);
IP2Bus_Mst_BE : out std_logic_vector(0 to C_MST_DWIDTH/8-1);
IP2Bus_Mst_Lock : out std_logic;
IP2Bus_Mst_Reset : out std_logic;
Bus2IP_Mst_CmdAck : in std_logic;
Bus2IP_Mst_Cmplt : in std_logic;
Bus2IP_Mst_Error : in std_logic;
Bus2IP_Mst_Rearbitrate : in std_logic;
Bus2IP_Mst_Cmd_Timeout : in std_logic;
Bus2IP_MstRd_d : in std_logic_vector(0 to C_MST_DWIDTH-1);
Bus2IP_MstRd_src_rdy_n : in std_logic;
IP2Bus_MstWr_d : out std_logic_vector(0 to C_MST_DWIDTH-1);
Bus2IP_MstWr_dst_rdy_n : in std_logic
);
end entity user_logic;
architecture IMP of user_logic is
-- Define the memory map for each command register, Address[13 to 14], This value is the offset from the base address assigned to this module
constant OPCODE_ENQUEUE : std_logic_vector(0 to 2-1) := "10"; --conv_std_logic_vector(2, 2); -- Opcode for "wait" enqueue
constant OPCODE_DEQUEUE : std_logic_vector(0 to 2-1) := "01"; --conv_std_logic_vector(1, 2); -- Opcode for "signal" dequeue
constant OPCODE_DEQUEUE_ALL : std_logic_vector(0 to 2-1) := "11"; --conv_std_logic_vector(3, 2); -- Opcode for "broadcast" dequeue
-- ACK signal
signal IP2Bus_Ack : std_logic;
-- CE concatenation signals
signal Bus2IP_RdCE_concat : std_logic;
signal Bus2IP_WrCE_concat : std_logic;
-- Bus Output Controller signals
signal bus_data_ready : std_logic;
signal bus_ack_ready : std_logic;
signal bus_data_out : std_logic_vector (0 to 31);
-- Reset Signals, FIXME: It would be nice to eliminate the default values here
signal inside_reset : std_logic := '0';
signal inside_reset_next : std_logic := '0';
-- Signals for each event type
signal Enqueue_Request : std_logic;
signal Dequeue_Request : std_logic;
signal Dequeue_All_Request : std_logic;
signal Error_Request : std_logic;
-- signal and type for MASTER FSM
type master_state_type is
(
idle, -- idle states
wait_trans_done, -- wait for bus transaction to complete
reset, -- reset states
reset_core,
reset_wait_4_ack,
enqueue_begin,
enqueue_finish,
dequeue_begin,
dequeue_finish,
dequeueAll_begin,
dequeueAll_finish
);
signal current_state, next_state : master_state_type := idle;
--cvCore Inputs
signal msg_chan_channelDataOut : std_logic_vector(0 to 7) := (others => '0');
signal msg_chan_exists : std_logic := '0';
signal msg_chan_full : std_logic := '0';
signal cmd : std_logic := '0';
signal opcode : std_logic_vector(0 to 1) := (others => '0');
signal cvar : std_logic_vector(0 to 7) := (others => '0');
signal tid : std_logic_vector(0 to 7) := (others => '0');
signal reset_sig : std_logic := '0';
-- cvCore Outputs
signal msg_chan_channelDataIn : std_logic_vector(0 to 7);
signal msg_chan_channelRead : std_logic;
signal msg_chan_channelWrite : std_logic;
signal ack : std_logic;
-- Message channels signals
signal FSL_S_Read : std_logic;
signal FSL_S_Exists : std_logic;
signal FSL_Has_Data : std_logic;
signal FSL_Data : std_logic_vector(0 to 7);
-- signals for master model control/status registers write/read
signal mst_ip2bus_data : std_logic_vector(0 to C_SLV_DWIDTH-1);
-- signals for master model control/status registers
type BYTE_REG_TYPE is array(0 to 15) of std_logic_vector(0 to 7);
signal mst_go, IP2Bus_MstRdReq : std_logic;
-- signals for master model command interface state machine
type CMD_CNTL_SM_TYPE is (CMD_IDLE, CMD_RUN, CMD_WAIT_FOR_DATA, CMD_DONE);
signal mst_cmd_sm_state : CMD_CNTL_SM_TYPE;
signal mst_cmd_sm_set_done : std_logic;
signal mst_cmd_sm_set_error : std_logic;
signal mst_cmd_sm_set_timeout : std_logic;
signal mst_cmd_sm_busy : std_logic;
signal mst_cmd_sm_clr_go : std_logic;
signal mst_cmd_sm_rd_req : std_logic;
signal mst_cmd_sm_wr_req : std_logic;
signal mst_cmd_sm_reset : std_logic;
signal mst_cmd_sm_bus_lock : std_logic;
signal IP2Bus_Addr, mst_cmd_sm_ip2bus_addr : std_logic_vector(0 to C_MST_AWIDTH-1);
signal mst_cmd_sm_ip2bus_be : std_logic_vector(0 to C_MST_DWIDTH/8-1);
signal mst_fifo_valid_write_xfer : std_logic;
signal mst_fifo_valid_read_xfer : std_logic;
component fsl_v20 is
generic (
C_EXT_RESET_HIGH : integer;
C_ASYNC_CLKS : integer;
C_IMPL_STYLE : integer;
C_USE_CONTROL : integer;
C_FSL_DWIDTH : integer;
C_FSL_DEPTH : integer;
C_READ_CLOCK_PERIOD : integer
);
port (
FSL_Clk : in std_logic;
SYS_Rst : in std_logic;
FSL_Rst : out std_logic;
FSL_M_Clk : in std_logic;
FSL_M_Data : in std_logic_vector(0 to C_FSL_DWIDTH-1);
FSL_M_Control : in std_logic;
FSL_M_Write : in std_logic;
FSL_M_Full : out std_logic;
FSL_S_Clk : in std_logic;
FSL_S_Data : out std_logic_vector(0 to C_FSL_DWIDTH-1);
FSL_S_Control : out std_logic;
FSL_S_Read : in std_logic;
FSL_S_Exists : out std_logic;
FSL_Full : out std_logic;
FSL_Has_Data : out std_logic;
FSL_Control_IRQ : out std_logic
);
end component;
component condvar is
generic(
G_ADDR_WIDTH : integer := 11;
G_OP_WIDTH : integer := 2;
G_TID_WIDTH : integer := 8
);
port
(
msg_chan_channelDataIn : out std_logic_vector(0 to (G_TID_WIDTH - 1));
msg_chan_channelDataOut : in std_logic_vector(0 to (G_TID_WIDTH - 1));
msg_chan_exists : in std_logic;
msg_chan_full : in std_logic;
msg_chan_channelRead : out std_logic;
msg_chan_channelWrite : out std_logic;
cmd : in std_logic;
opcode : in std_logic_vector(0 to G_OP_WIDTH - 1);
cvar : in std_logic_vector(0 to G_TID_WIDTH - 1);
tid : in std_logic_vector(0 to G_TID_WIDTH - 1);
ack : out std_logic;
clock_sig : in std_logic;
reset_sig : in std_logic
);
end component condvar;
---------------------------------------------------
-- bit_set()
-- *******************
-- Determine if any bit in the array is set.
-- If any of the bits are set then '1' is returned,
-- otherwise '0' is returned.
---------------------------------------------------
function bit_set( data : in std_logic_vector ) return std_logic is
begin
for i in data'range loop
if( data(i) = '1' ) then
return '1';
end if;
end loop;
return '0';
end function;
---------------------------------------------------
function getCVAR( addr : in std_logic_vector(0 to 31)) return std_logic_vector is
begin
return "00" & addr(24 to 29);
end function;
function getTID( addr : in std_logic_vector(0 to 31)) return std_logic_vector is
begin
return addr(16 to 23);
end function;
function form_tm_addr( tid : in std_logic_vector(0 to 7)) return std_logic_vector is
variable mask : std_logic_vector(0 to 31);
begin
mask := x"00001" & "00" & tid & "00";
return C_THREAD_MANAGER_BASEADDR or mask;
end function;
begin
-- Instantiate the CV Core
cvCore: condvar PORT MAP (
msg_chan_channelDataIn => msg_chan_channelDataIn,
msg_chan_channelDataOut => msg_chan_channelDataOut,
msg_chan_exists => msg_chan_exists,
msg_chan_full => msg_chan_full,
msg_chan_channelRead => msg_chan_channelRead,
msg_chan_channelWrite => msg_chan_channelWrite,
cmd => cmd,
opcode => opcode,
cvar => cvar,
tid => tid,
ack => ack,
clock_sig => Bus2IP_Clk,
reset_sig => reset_sig
);
message_channel : fsl_v20
generic map (
C_EXT_RESET_HIGH => 1,
C_ASYNC_CLKS => 0,
C_IMPL_STYLE => 1,
C_USE_CONTROL => 0,
C_FSL_DWIDTH => 8,
C_FSL_DEPTH => 256,
C_READ_CLOCK_PERIOD => 0
)
port map (
FSL_Clk => Bus2IP_Clk,
SYS_Rst => Bus2IP_Reset,
FSL_Rst => open,
FSL_M_Clk => Bus2IP_Clk,
FSL_M_Data => msg_chan_channelDataIn,
FSL_M_Control => '0',
FSL_M_Write => msg_chan_channelWrite,
FSL_M_Full => msg_chan_full,
FSL_S_Clk => Bus2IP_Clk,
FSL_S_Data => FSL_Data,
FSL_S_Control => open,
FSL_S_Read => FSL_S_Read,
FSL_S_Exists => FSL_S_Exists,
FSL_Full => open,
FSL_Has_Data => FSL_Has_Data,
FSL_Control_IRQ => open
);
-- user logic master command interface assignments
IP2Bus_MstRd_Req <= mst_cmd_sm_rd_req;
IP2Bus_MstWr_Req <= mst_cmd_sm_wr_req;
IP2Bus_Mst_Addr <= mst_cmd_sm_ip2bus_addr;
IP2Bus_Mst_BE <= mst_cmd_sm_ip2bus_be;
IP2Bus_Mst_Lock <= mst_cmd_sm_bus_lock;
IP2Bus_Mst_Reset <= mst_cmd_sm_reset;
--implement master command interface state machine
mst_go <= FSL_S_Exists; -- Start master transaction when data exists in the FSL
MASTER_CMD_SM_PROC : process( Bus2IP_Clk ) is
begin
if ( Bus2IP_Clk'event and Bus2IP_Clk = '1' ) then
if ( Bus2IP_Reset = '1' ) then
-- reset condition
mst_cmd_sm_state <= CMD_IDLE;
mst_cmd_sm_clr_go <= '0';
mst_cmd_sm_rd_req <= '0';
mst_cmd_sm_wr_req <= '0';
mst_cmd_sm_bus_lock <= '0';
mst_cmd_sm_reset <= '0';
mst_cmd_sm_ip2bus_addr <= (others => '0');
mst_cmd_sm_ip2bus_be <= (others => '0');
mst_cmd_sm_set_done <= '0';
mst_cmd_sm_set_error <= '0';
mst_cmd_sm_set_timeout <= '0';
mst_cmd_sm_busy <= '0';
else
-- default condition
mst_cmd_sm_clr_go <= '0';
mst_cmd_sm_rd_req <= '0';
mst_cmd_sm_wr_req <= '0';
mst_cmd_sm_bus_lock <= '0';
mst_cmd_sm_reset <= '0';
mst_cmd_sm_ip2bus_addr <= (others => '0');
mst_cmd_sm_ip2bus_be <= (others => '0');
mst_cmd_sm_set_done <= '0';
mst_cmd_sm_set_error <= '0';
mst_cmd_sm_set_timeout <= '0';
mst_cmd_sm_busy <= '1';
FSL_S_Read <= '0';
-- state transition
case mst_cmd_sm_state is
when CMD_IDLE =>
if ( mst_go = '1' ) then
mst_cmd_sm_state <= CMD_RUN;
mst_cmd_sm_clr_go <= '1';
else
mst_cmd_sm_state <= CMD_IDLE;
mst_cmd_sm_busy <= '0';
end if;
when CMD_RUN =>
if ( Bus2IP_Mst_CmdAck = '1' and Bus2IP_Mst_Cmplt = '0' ) then
-- Signal a read on the FSL to pop off the element
FSL_S_Read <= '1';
mst_cmd_sm_state <= CMD_WAIT_FOR_DATA;
elsif ( Bus2IP_Mst_Cmplt = '1' ) then
-- Signal a read on the FSL to pop off the element
FSL_S_Read <= '1';
mst_cmd_sm_state <= CMD_DONE;
if ( Bus2IP_Mst_Cmd_Timeout = '1' ) then
-- PLB address phase timeout
mst_cmd_sm_set_error <= '1';
mst_cmd_sm_set_timeout <= '1';
elsif ( Bus2IP_Mst_Error = '1' ) then
-- PLB data transfer error
mst_cmd_sm_set_error <= '1';
end if;
else
mst_cmd_sm_state <= CMD_RUN;
mst_cmd_sm_rd_req <= '1'; -- Perform a write (rd = '1', wr = '0')
mst_cmd_sm_wr_req <= '0';
mst_cmd_sm_ip2bus_addr <= form_tm_addr(FSL_Data); -- Setup address
mst_cmd_sm_ip2bus_be <= (others => '1'); -- Use all byte lanes
mst_cmd_sm_bus_lock <= '0'; -- De-assert bus lock
end if;
when CMD_WAIT_FOR_DATA =>
if ( Bus2IP_Mst_Cmplt = '1' ) then
mst_cmd_sm_state <= CMD_DONE;
else
mst_cmd_sm_state <= CMD_WAIT_FOR_DATA;
end if;
when CMD_DONE =>
mst_cmd_sm_state <= CMD_IDLE;
mst_cmd_sm_set_done <= '1';
mst_cmd_sm_busy <= '0';
when others =>
mst_cmd_sm_state <= CMD_IDLE;
mst_cmd_sm_busy <= '0';
end case;
end if;
end if;
end process MASTER_CMD_SM_PROC;
-- Create concatenation signals
Bus2IP_RdCE_concat <= bit_set(Bus2IP_RdCE);
Bus2IP_WrCE_concat <= bit_set(Bus2IP_WrCE);
-- *************************************************************************
-- Process: BUS_OUTPUT_CONTROLLER
-- Purpose: Control output from IP to Bus
-- * Can be controlled using bus_data_ready, bus_ack_ready, and bus_data_out signals.
-- *************************************************************************
BUS_OUTPUT_CONTROLLER : process( Bus2IP_Clk, bus_data_ready, bus_ack_ready ) is
begin
if( Bus2IP_Clk'event and Bus2IP_Clk = '1' ) then
if( bus_data_ready = '1' and bus_ack_ready = '1' ) then
IP2Bus_Data <= bus_data_out; -- put data on bus
IP2Bus_Ack <= '1'; -- ACK bus
elsif (bus_data_ready = '1' and bus_ack_ready = '0') then
IP2Bus_Data <= bus_data_out; -- put data on bus
IP2Bus_Ack <= '0'; -- turn off ACK
else
IP2Bus_Data <= (others => '0'); -- output 0's on bus
IP2Bus_Ack <= '0'; -- turn off ACK
end if;
end if;
end process BUS_OUTPUT_CONTROLLER;
ACK_ROUTER : process (IP2Bus_Ack, Bus2IP_RdCE_concat, Bus2IP_WrCE_concat) is
begin
-- Turn an "ACK" into a specific ACK (read or write ACK)
if (Bus2IP_RdCE_concat = '1') then
IP2Bus_RdAck <= IP2Bus_Ack;
IP2Bus_WrAck <= '0';
else
IP2Bus_RdAck <= '0';
IP2Bus_WrAck <= IP2Bus_Ack;
end if;
end process;
-- *************************************************************************
-- Process: BUS_CMD_PROC
-- Purpose: Controller and decoder for incoming bus operations (reads and writes)
-- *************************************************************************
BUS_CMD_PROC : process (Bus2IP_Clk, Bus2IP_RdCE_concat, Bus2IP_WrCE_concat, Bus2IP_Addr ) is
begin
if( Bus2IP_Clk'event and Bus2IP_Clk = '1' ) then
Enqueue_Request <= '0';
Dequeue_Request <= '0';
Dequeue_All_Request <= '0';
Error_Request <= '0';
if( Bus2IP_WrCE_concat = '1' ) then
Error_Request <= '1';
elsif( Bus2IP_RdCE_concat = '1' ) then
case Bus2IP_Addr(13 to 14) is
when OPCODE_ENQUEUE => Enqueue_Request <= '1';
when OPCODE_DEQUEUE => Dequeue_Request <= '1';
when OPCODE_DEQUEUE_ALL => Dequeue_All_Request <= '1';
when others => Error_Request <= '1';
end case;
end if;
end if;
end process BUS_CMD_PROC;
-- *************************************************************************
-- Process: MASTER_FSM_STATE_PROC
-- Purpose: Synchronous FSM controller for the master state machine
-- *************************************************************************
MASTER_FSM_STATE_PROC: process(
Bus2IP_Clk, Soft_Reset, inside_reset, inside_reset_next, next_state) is
begin
if ( Bus2IP_Clk'event and Bus2IP_Clk = '1' ) then
if( Soft_Reset = '1' and inside_reset = '0' ) then
-- Initialize all signals...
current_state <= reset;
inside_reset <= '1';
else
-- Assign all signals to their next state...
current_state <= next_state;
inside_reset <= inside_reset_next;
end if;
end if;
end process MASTER_FSM_STATE_PROC;
-- *************************************************************************
-- Process: MASTER_FSM_LOGIC_PROC
-- Purpose: Combinational process that contains all state machine logic and
-- state transitions for the master state machine
-- *************************************************************************
MASTER_FSM_LOGIC_PROC: process (
current_state, inside_reset, Enqueue_Request, Dequeue_Request,
Dequeue_All_Request, Error_Request, Bus2IP_Data, Bus2IP_RdCE_concat, Bus2IP_WrCE_concat, Soft_Reset, Bus2IP_Addr, ack ) is
-- Idle Variable, concatenation of all request signals
variable idle_concat : std_logic_vector(0 to 3);
begin
IP2Bus_Error <= '0'; -- no error
IP2Bus_Addr <= (others => '0');
IP2Bus_MstRdReq <= '0';
IP2Bus_MstWr_d <= (others => '0');
Reset_Done <= '0'; -- reset is done unless we override it later
next_state <= current_state;
inside_reset_next <= inside_reset;
bus_data_out <= (others => '0');
bus_data_ready <= '0';
bus_ack_ready <= '0';
cmd <= '0';
opcode <= (others => '0');
cvar <= (others => '0');
tid <= (others => '0');
reset_sig <= '0';
case current_state is
when idle =>
-- Assign to variable for case statement
idle_concat := (Enqueue_Request & Dequeue_Request & Dequeue_All_Request & Error_Request);
-- Decode request
case (idle_concat) is
when "1000" => next_state <= enqueue_begin; -- Enqueue
when "0100" => next_state <= dequeue_begin; -- Dequeue
when "0010" => next_state <= dequeueAll_begin; -- DequeueAll
when "0001" => bus_data_out <= (others => '1'); -- Error!!!
bus_data_ready <= '1';
bus_ack_ready <= '1';
next_state <= wait_trans_done;
when others => next_state <= idle; -- Others, stay in idle state
end case;
when wait_trans_done =>
-- Goal of this state is to return to the idle state ONLY (iff) the bus transaction has COMPLETELY ended!
bus_data_ready <= '0'; -- de-assert bus transaction signals
bus_ack_ready <= '0';
if( Bus2IP_RdCE_concat = '0' and Bus2IP_WrCE_concat = '0' ) then
next_state <= idle;
end if;
when reset =>
reset_sig <= '1'; -- begin reset on cvCore
Reset_Done <= '0'; -- De-assert Reset_Done
next_state <= reset_core;
when reset_core =>
if (ack = '1') then
next_state <= reset_wait_4_ack;
else
next_state <= reset_core;
end if;
when reset_wait_4_ack =>
Reset_Done <= '1'; -- Assert that reset has completed
if( Soft_Reset = '0' ) then -- if reset is complete
Reset_Done <= '0'; -- de-assert that reset is complete
inside_reset_next <= '0'; -- de-assert to signal that process is no longer in reset
next_state <= idle; -- return to idle stage
end if;
when enqueue_begin =>
-- Setup Command
cmd <= '1';
opcode <= OPCODE_ENQUEUE;
cvar <= getCVAR(Bus2IP_Addr);
tid <= getTID(Bus2IP_Addr);
-- Persist with command until ACK is received
if (ack = '1') then
-- De-assert request and continue
cmd <= '0';
opcode <= (others => '0');
cvar <= (others => '0');
tid <= (others => '0');
next_state <= enqueue_finish;
else
-- Persist with request and remain
next_state <= enqueue_begin;
end if;
when enqueue_finish =>
-- Finish transaction
bus_data_out <= (others => '0');
bus_data_ready <= '1';
bus_ack_ready <= '1';
next_state <= wait_trans_done;
when dequeue_begin =>
-- Setup Command
cmd <= '1';
opcode <= OPCODE_DEQUEUE;
cvar <= getCVAR(Bus2IP_Addr);
tid <= getTID(Bus2IP_Addr);
-- Persist with command until ACK is received
if (ack = '1') then
-- De-assert request and continue
cmd <= '0';
opcode <= (others => '0');
cvar <= (others => '0');
tid <= (others => '0');
next_state <= dequeue_finish;
else
-- Persist with request and remain
next_state <= dequeue_begin;
end if;
when dequeue_finish =>
-- Finish transaction
bus_data_out <= (others => '0');
bus_data_ready <= '1';
bus_ack_ready <= '1';
next_state <= wait_trans_done;
when dequeueAll_begin =>
-- Setup Command
cmd <= '1';
opcode <= OPCODE_DEQUEUE_ALL;
cvar <= getCVAR(Bus2IP_Addr);
tid <= getTID(Bus2IP_Addr);
-- Persist with command until ACK is received
if (ack = '1') then
-- De-assert request and continue
cmd <= '0';
opcode <= (others => '0');
cvar <= (others => '0');
tid <= (others => '0');
next_state <= dequeueAll_finish;
else
-- Persist with request and remain
next_state <= dequeueAll_begin;
end if;
when dequeueAll_finish =>
-- Finish transaction
bus_data_out <= (others => '0');
bus_data_ready <= '1';
bus_ack_ready <= '1';
next_state <= wait_trans_done;
when others =>
next_state <= idle;
end case; -- END CASE (current_state)
end process MASTER_FSM_LOGIC_PROC;
end architecture IMP;
|
bsd-3-clause
|
masson2013/heterogeneous_hthreads
|
src/platforms/xilinx/ml605_pr_smp1_14_7/design/pcores/plb_cond_vars_v1_00_a/hdl/vhdl/abc.vhd
|
9
|
24027
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library fsl_v20_v2_11_a;
use fsl_v20_v2_11_a.all;
-- Definition of Generics:
-- C_SLV_DWIDTH -- Slave interface data bus width
-- C_MST_AWIDTH -- Master interface address bus width
-- C_MST_DWIDTH -- Master interface data bus width
-- C_NUM_REG -- Number of software accessible registers
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Reset -- Bus to IP reset
-- Bus2IP_Addr -- Bus to IP address bus
-- Bus2IP_Data -- Bus to IP data bus
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- IP2Bus_Data -- IP to Bus data bus
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- IP2Bus_Error -- IP to Bus error response
-- IP2Bus_MstRd_Req -- IP to Bus master read request
-- IP2Bus_MstWr_Req -- IP to Bus master write request
-- IP2Bus_Mst_Addr -- IP to Bus master address bus
-- IP2Bus_Mst_BE -- IP to Bus master byte enables
-- IP2Bus_Mst_Lock -- IP to Bus master lock
-- IP2Bus_Mst_Reset -- IP to Bus master reset
-- Bus2IP_Mst_CmdAck -- Bus to IP master command acknowledgement
-- Bus2IP_Mst_Cmplt -- Bus to IP master transfer completion
-- Bus2IP_Mst_Error -- Bus to IP master error response
-- Bus2IP_Mst_Rearbitrate -- Bus to IP master re-arbitrate
-- Bus2IP_Mst_Cmd_Timeout -- Bus to IP master command timeout
-- Bus2IP_MstRd_d -- Bus to IP master read data bus
-- Bus2IP_MstRd_src_rdy_n -- Bus to IP master read source ready
-- IP2Bus_MstWr_d -- IP to Bus master write data bus
-- Bus2IP_MstWr_dst_rdy_n -- Bus to IP master write destination ready
entity user_logic is
generic
(
C_THREAD_MANAGER_BASEADDR : std_logic_vector := x"11000000";
C_SLV_DWIDTH : integer := 32;
C_MST_AWIDTH : integer := 32;
C_MST_DWIDTH : integer := 32;
C_NUM_REG : integer := 5
);
port
(
Soft_Reset : in std_logic;
Reset_Done : out std_logic;
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Addr : in std_logic_vector(0 to 31);
Bus2IP_Data : in std_logic_vector(0 to C_SLV_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_SLV_DWIDTH/8-1);
Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_REG-1);
Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_REG-1);
IP2Bus_Data : out std_logic_vector(0 to C_SLV_DWIDTH-1);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic;
IP2Bus_MstRd_Req : out std_logic;
IP2Bus_MstWr_Req : out std_logic;
IP2Bus_Mst_Addr : out std_logic_vector(0 to C_MST_AWIDTH-1);
IP2Bus_Mst_BE : out std_logic_vector(0 to C_MST_DWIDTH/8-1);
IP2Bus_Mst_Lock : out std_logic;
IP2Bus_Mst_Reset : out std_logic;
Bus2IP_Mst_CmdAck : in std_logic;
Bus2IP_Mst_Cmplt : in std_logic;
Bus2IP_Mst_Error : in std_logic;
Bus2IP_Mst_Rearbitrate : in std_logic;
Bus2IP_Mst_Cmd_Timeout : in std_logic;
Bus2IP_MstRd_d : in std_logic_vector(0 to C_MST_DWIDTH-1);
Bus2IP_MstRd_src_rdy_n : in std_logic;
IP2Bus_MstWr_d : out std_logic_vector(0 to C_MST_DWIDTH-1);
Bus2IP_MstWr_dst_rdy_n : in std_logic
);
end entity user_logic;
architecture IMP of user_logic is
-- Define the memory map for each command register, Address[13 to 14], This value is the offset from the base address assigned to this module
constant OPCODE_ENQUEUE : std_logic_vector(0 to 2-1) := "10"; --conv_std_logic_vector(2, 2); -- Opcode for "wait" enqueue
constant OPCODE_DEQUEUE : std_logic_vector(0 to 2-1) := "01"; --conv_std_logic_vector(1, 2); -- Opcode for "signal" dequeue
constant OPCODE_DEQUEUE_ALL : std_logic_vector(0 to 2-1) := "11"; --conv_std_logic_vector(3, 2); -- Opcode for "broadcast" dequeue
-- ACK signal
signal IP2Bus_Ack : std_logic;
-- CE concatenation signals
signal Bus2IP_RdCE_concat : std_logic;
signal Bus2IP_WrCE_concat : std_logic;
-- Bus Output Controller signals
signal bus_data_ready : std_logic;
signal bus_ack_ready : std_logic;
signal bus_data_out : std_logic_vector (0 to 31);
-- Reset Signals, FIXME: It would be nice to eliminate the default values here
signal inside_reset : std_logic := '0';
signal inside_reset_next : std_logic := '0';
-- Signals for each event type
signal Enqueue_Request : std_logic;
signal Dequeue_Request : std_logic;
signal Dequeue_All_Request : std_logic;
signal Error_Request : std_logic;
-- signal and type for MASTER FSM
type master_state_type is
(
idle, -- idle states
wait_trans_done, -- wait for bus transaction to complete
reset, -- reset states
reset_core,
reset_wait_4_ack,
enqueue_begin,
enqueue_finish,
dequeue_begin,
dequeue_finish,
dequeueAll_begin,
dequeueAll_finish
);
signal current_state, next_state : master_state_type := idle;
--cvCore Inputs
signal msg_chan_channelDataOut : std_logic_vector(0 to 7) := (others => '0');
signal msg_chan_exists : std_logic := '0';
signal msg_chan_full : std_logic := '0';
signal cmd : std_logic := '0';
signal opcode : std_logic_vector(0 to 1) := (others => '0');
signal cvar : std_logic_vector(0 to 7) := (others => '0');
signal tid : std_logic_vector(0 to 7) := (others => '0');
signal reset_sig : std_logic := '0';
-- cvCore Outputs
signal msg_chan_channelDataIn : std_logic_vector(0 to 7);
signal msg_chan_channelRead : std_logic;
signal msg_chan_channelWrite : std_logic;
signal ack : std_logic;
-- Message channels signals
signal FSL_S_Read : std_logic;
signal FSL_S_Exists : std_logic;
signal FSL_Has_Data : std_logic;
signal FSL_Data : std_logic_vector(0 to 7);
-- signals for master model control/status registers write/read
signal mst_ip2bus_data : std_logic_vector(0 to C_SLV_DWIDTH-1);
-- signals for master model control/status registers
type BYTE_REG_TYPE is array(0 to 15) of std_logic_vector(0 to 7);
signal mst_go, IP2Bus_MstRdReq : std_logic;
-- signals for master model command interface state machine
type CMD_CNTL_SM_TYPE is (CMD_IDLE, CMD_RUN, CMD_WAIT_FOR_DATA, CMD_DONE);
signal mst_cmd_sm_state : CMD_CNTL_SM_TYPE;
signal mst_cmd_sm_set_done : std_logic;
signal mst_cmd_sm_set_error : std_logic;
signal mst_cmd_sm_set_timeout : std_logic;
signal mst_cmd_sm_busy : std_logic;
signal mst_cmd_sm_clr_go : std_logic;
signal mst_cmd_sm_rd_req : std_logic;
signal mst_cmd_sm_wr_req : std_logic;
signal mst_cmd_sm_reset : std_logic;
signal mst_cmd_sm_bus_lock : std_logic;
signal IP2Bus_Addr, mst_cmd_sm_ip2bus_addr : std_logic_vector(0 to C_MST_AWIDTH-1);
signal mst_cmd_sm_ip2bus_be : std_logic_vector(0 to C_MST_DWIDTH/8-1);
signal mst_fifo_valid_write_xfer : std_logic;
signal mst_fifo_valid_read_xfer : std_logic;
component fsl_v20 is
generic (
C_EXT_RESET_HIGH : integer;
C_ASYNC_CLKS : integer;
C_IMPL_STYLE : integer;
C_USE_CONTROL : integer;
C_FSL_DWIDTH : integer;
C_FSL_DEPTH : integer;
C_READ_CLOCK_PERIOD : integer
);
port (
FSL_Clk : in std_logic;
SYS_Rst : in std_logic;
FSL_Rst : out std_logic;
FSL_M_Clk : in std_logic;
FSL_M_Data : in std_logic_vector(0 to C_FSL_DWIDTH-1);
FSL_M_Control : in std_logic;
FSL_M_Write : in std_logic;
FSL_M_Full : out std_logic;
FSL_S_Clk : in std_logic;
FSL_S_Data : out std_logic_vector(0 to C_FSL_DWIDTH-1);
FSL_S_Control : out std_logic;
FSL_S_Read : in std_logic;
FSL_S_Exists : out std_logic;
FSL_Full : out std_logic;
FSL_Has_Data : out std_logic;
FSL_Control_IRQ : out std_logic
);
end component;
component condvar is
generic(
G_ADDR_WIDTH : integer := 11;
G_OP_WIDTH : integer := 2;
G_TID_WIDTH : integer := 8
);
port
(
msg_chan_channelDataIn : out std_logic_vector(0 to (G_TID_WIDTH - 1));
msg_chan_channelDataOut : in std_logic_vector(0 to (G_TID_WIDTH - 1));
msg_chan_exists : in std_logic;
msg_chan_full : in std_logic;
msg_chan_channelRead : out std_logic;
msg_chan_channelWrite : out std_logic;
cmd : in std_logic;
opcode : in std_logic_vector(0 to G_OP_WIDTH - 1);
cvar : in std_logic_vector(0 to G_TID_WIDTH - 1);
tid : in std_logic_vector(0 to G_TID_WIDTH - 1);
ack : out std_logic;
clock_sig : in std_logic;
reset_sig : in std_logic
);
end component condvar;
---------------------------------------------------
-- bit_set()
-- *******************
-- Determine if any bit in the array is set.
-- If any of the bits are set then '1' is returned,
-- otherwise '0' is returned.
---------------------------------------------------
function bit_set( data : in std_logic_vector ) return std_logic is
begin
for i in data'range loop
if( data(i) = '1' ) then
return '1';
end if;
end loop;
return '0';
end function;
---------------------------------------------------
function getCVAR( addr : in std_logic_vector(0 to 31)) return std_logic_vector is
begin
return "00" & addr(24 to 29);
end function;
function getTID( addr : in std_logic_vector(0 to 31)) return std_logic_vector is
begin
return addr(16 to 23);
end function;
function form_tm_addr( tid : in std_logic_vector(0 to 7)) return std_logic_vector is
variable mask : std_logic_vector(0 to 31);
begin
mask := x"00001" & "00" & tid & "00";
return C_THREAD_MANAGER_BASEADDR or mask;
end function;
begin
-- Instantiate the CV Core
cvCore: condvar PORT MAP (
msg_chan_channelDataIn => msg_chan_channelDataIn,
msg_chan_channelDataOut => msg_chan_channelDataOut,
msg_chan_exists => msg_chan_exists,
msg_chan_full => msg_chan_full,
msg_chan_channelRead => msg_chan_channelRead,
msg_chan_channelWrite => msg_chan_channelWrite,
cmd => cmd,
opcode => opcode,
cvar => cvar,
tid => tid,
ack => ack,
clock_sig => Bus2IP_Clk,
reset_sig => reset_sig
);
message_channel : fsl_v20
generic map (
C_EXT_RESET_HIGH => 1,
C_ASYNC_CLKS => 0,
C_IMPL_STYLE => 1,
C_USE_CONTROL => 0,
C_FSL_DWIDTH => 8,
C_FSL_DEPTH => 256,
C_READ_CLOCK_PERIOD => 0
)
port map (
FSL_Clk => Bus2IP_Clk,
SYS_Rst => Bus2IP_Reset,
FSL_Rst => open,
FSL_M_Clk => Bus2IP_Clk,
FSL_M_Data => msg_chan_channelDataIn,
FSL_M_Control => '0',
FSL_M_Write => msg_chan_channelWrite,
FSL_M_Full => msg_chan_full,
FSL_S_Clk => Bus2IP_Clk,
FSL_S_Data => FSL_Data,
FSL_S_Control => open,
FSL_S_Read => FSL_S_Read,
FSL_S_Exists => FSL_S_Exists,
FSL_Full => open,
FSL_Has_Data => FSL_Has_Data,
FSL_Control_IRQ => open
);
-- user logic master command interface assignments
IP2Bus_MstRd_Req <= mst_cmd_sm_rd_req;
IP2Bus_MstWr_Req <= mst_cmd_sm_wr_req;
IP2Bus_Mst_Addr <= mst_cmd_sm_ip2bus_addr;
IP2Bus_Mst_BE <= mst_cmd_sm_ip2bus_be;
IP2Bus_Mst_Lock <= mst_cmd_sm_bus_lock;
IP2Bus_Mst_Reset <= mst_cmd_sm_reset;
--implement master command interface state machine
mst_go <= FSL_S_Exists; -- Start master transaction when data exists in the FSL
MASTER_CMD_SM_PROC : process( Bus2IP_Clk ) is
begin
if ( Bus2IP_Clk'event and Bus2IP_Clk = '1' ) then
if ( Bus2IP_Reset = '1' ) then
-- reset condition
mst_cmd_sm_state <= CMD_IDLE;
mst_cmd_sm_clr_go <= '0';
mst_cmd_sm_rd_req <= '0';
mst_cmd_sm_wr_req <= '0';
mst_cmd_sm_bus_lock <= '0';
mst_cmd_sm_reset <= '0';
mst_cmd_sm_ip2bus_addr <= (others => '0');
mst_cmd_sm_ip2bus_be <= (others => '0');
mst_cmd_sm_set_done <= '0';
mst_cmd_sm_set_error <= '0';
mst_cmd_sm_set_timeout <= '0';
mst_cmd_sm_busy <= '0';
else
-- default condition
mst_cmd_sm_clr_go <= '0';
mst_cmd_sm_rd_req <= '0';
mst_cmd_sm_wr_req <= '0';
mst_cmd_sm_bus_lock <= '0';
mst_cmd_sm_reset <= '0';
mst_cmd_sm_ip2bus_addr <= (others => '0');
mst_cmd_sm_ip2bus_be <= (others => '0');
mst_cmd_sm_set_done <= '0';
mst_cmd_sm_set_error <= '0';
mst_cmd_sm_set_timeout <= '0';
mst_cmd_sm_busy <= '1';
FSL_S_Read <= '0';
-- state transition
case mst_cmd_sm_state is
when CMD_IDLE =>
if ( mst_go = '1' ) then
mst_cmd_sm_state <= CMD_RUN;
mst_cmd_sm_clr_go <= '1';
else
mst_cmd_sm_state <= CMD_IDLE;
mst_cmd_sm_busy <= '0';
end if;
when CMD_RUN =>
if ( Bus2IP_Mst_CmdAck = '1' and Bus2IP_Mst_Cmplt = '0' ) then
-- Signal a read on the FSL to pop off the element
FSL_S_Read <= '1';
mst_cmd_sm_state <= CMD_WAIT_FOR_DATA;
elsif ( Bus2IP_Mst_Cmplt = '1' ) then
-- Signal a read on the FSL to pop off the element
FSL_S_Read <= '1';
mst_cmd_sm_state <= CMD_DONE;
if ( Bus2IP_Mst_Cmd_Timeout = '1' ) then
-- PLB address phase timeout
mst_cmd_sm_set_error <= '1';
mst_cmd_sm_set_timeout <= '1';
elsif ( Bus2IP_Mst_Error = '1' ) then
-- PLB data transfer error
mst_cmd_sm_set_error <= '1';
end if;
else
mst_cmd_sm_state <= CMD_RUN;
mst_cmd_sm_rd_req <= '1'; -- Perform a write (rd = '1', wr = '0')
mst_cmd_sm_wr_req <= '0';
mst_cmd_sm_ip2bus_addr <= form_tm_addr(FSL_Data); -- Setup address
mst_cmd_sm_ip2bus_be <= (others => '1'); -- Use all byte lanes
mst_cmd_sm_bus_lock <= '0'; -- De-assert bus lock
end if;
when CMD_WAIT_FOR_DATA =>
if ( Bus2IP_Mst_Cmplt = '1' ) then
mst_cmd_sm_state <= CMD_DONE;
else
mst_cmd_sm_state <= CMD_WAIT_FOR_DATA;
end if;
when CMD_DONE =>
mst_cmd_sm_state <= CMD_IDLE;
mst_cmd_sm_set_done <= '1';
mst_cmd_sm_busy <= '0';
when others =>
mst_cmd_sm_state <= CMD_IDLE;
mst_cmd_sm_busy <= '0';
end case;
end if;
end if;
end process MASTER_CMD_SM_PROC;
-- Create concatenation signals
Bus2IP_RdCE_concat <= bit_set(Bus2IP_RdCE);
Bus2IP_WrCE_concat <= bit_set(Bus2IP_WrCE);
-- *************************************************************************
-- Process: BUS_OUTPUT_CONTROLLER
-- Purpose: Control output from IP to Bus
-- * Can be controlled using bus_data_ready, bus_ack_ready, and bus_data_out signals.
-- *************************************************************************
BUS_OUTPUT_CONTROLLER : process( Bus2IP_Clk, bus_data_ready, bus_ack_ready ) is
begin
if( Bus2IP_Clk'event and Bus2IP_Clk = '1' ) then
if( bus_data_ready = '1' and bus_ack_ready = '1' ) then
IP2Bus_Data <= bus_data_out; -- put data on bus
IP2Bus_Ack <= '1'; -- ACK bus
elsif (bus_data_ready = '1' and bus_ack_ready = '0') then
IP2Bus_Data <= bus_data_out; -- put data on bus
IP2Bus_Ack <= '0'; -- turn off ACK
else
IP2Bus_Data <= (others => '0'); -- output 0's on bus
IP2Bus_Ack <= '0'; -- turn off ACK
end if;
end if;
end process BUS_OUTPUT_CONTROLLER;
ACK_ROUTER : process (IP2Bus_Ack, Bus2IP_RdCE_concat, Bus2IP_WrCE_concat) is
begin
-- Turn an "ACK" into a specific ACK (read or write ACK)
if (Bus2IP_RdCE_concat = '1') then
IP2Bus_RdAck <= IP2Bus_Ack;
IP2Bus_WrAck <= '0';
else
IP2Bus_RdAck <= '0';
IP2Bus_WrAck <= IP2Bus_Ack;
end if;
end process;
-- *************************************************************************
-- Process: BUS_CMD_PROC
-- Purpose: Controller and decoder for incoming bus operations (reads and writes)
-- *************************************************************************
BUS_CMD_PROC : process (Bus2IP_Clk, Bus2IP_RdCE_concat, Bus2IP_WrCE_concat, Bus2IP_Addr ) is
begin
if( Bus2IP_Clk'event and Bus2IP_Clk = '1' ) then
Enqueue_Request <= '0';
Dequeue_Request <= '0';
Dequeue_All_Request <= '0';
Error_Request <= '0';
if( Bus2IP_WrCE_concat = '1' ) then
Error_Request <= '1';
elsif( Bus2IP_RdCE_concat = '1' ) then
case Bus2IP_Addr(13 to 14) is
when OPCODE_ENQUEUE => Enqueue_Request <= '1';
when OPCODE_DEQUEUE => Dequeue_Request <= '1';
when OPCODE_DEQUEUE_ALL => Dequeue_All_Request <= '1';
when others => Error_Request <= '1';
end case;
end if;
end if;
end process BUS_CMD_PROC;
-- *************************************************************************
-- Process: MASTER_FSM_STATE_PROC
-- Purpose: Synchronous FSM controller for the master state machine
-- *************************************************************************
MASTER_FSM_STATE_PROC: process(
Bus2IP_Clk, Soft_Reset, inside_reset, inside_reset_next, next_state) is
begin
if ( Bus2IP_Clk'event and Bus2IP_Clk = '1' ) then
if( Soft_Reset = '1' and inside_reset = '0' ) then
-- Initialize all signals...
current_state <= reset;
inside_reset <= '1';
else
-- Assign all signals to their next state...
current_state <= next_state;
inside_reset <= inside_reset_next;
end if;
end if;
end process MASTER_FSM_STATE_PROC;
-- *************************************************************************
-- Process: MASTER_FSM_LOGIC_PROC
-- Purpose: Combinational process that contains all state machine logic and
-- state transitions for the master state machine
-- *************************************************************************
MASTER_FSM_LOGIC_PROC: process (
current_state, inside_reset, Enqueue_Request, Dequeue_Request,
Dequeue_All_Request, Error_Request, Bus2IP_Data, Bus2IP_RdCE_concat, Bus2IP_WrCE_concat, Soft_Reset, Bus2IP_Addr, ack ) is
-- Idle Variable, concatenation of all request signals
variable idle_concat : std_logic_vector(0 to 3);
begin
IP2Bus_Error <= '0'; -- no error
IP2Bus_Addr <= (others => '0');
IP2Bus_MstRdReq <= '0';
IP2Bus_MstWr_d <= (others => '0');
Reset_Done <= '0'; -- reset is done unless we override it later
next_state <= current_state;
inside_reset_next <= inside_reset;
bus_data_out <= (others => '0');
bus_data_ready <= '0';
bus_ack_ready <= '0';
cmd <= '0';
opcode <= (others => '0');
cvar <= (others => '0');
tid <= (others => '0');
reset_sig <= '0';
case current_state is
when idle =>
-- Assign to variable for case statement
idle_concat := (Enqueue_Request & Dequeue_Request & Dequeue_All_Request & Error_Request);
-- Decode request
case (idle_concat) is
when "1000" => next_state <= enqueue_begin; -- Enqueue
when "0100" => next_state <= dequeue_begin; -- Dequeue
when "0010" => next_state <= dequeueAll_begin; -- DequeueAll
when "0001" => bus_data_out <= (others => '1'); -- Error!!!
bus_data_ready <= '1';
bus_ack_ready <= '1';
next_state <= wait_trans_done;
when others => next_state <= idle; -- Others, stay in idle state
end case;
when wait_trans_done =>
-- Goal of this state is to return to the idle state ONLY (iff) the bus transaction has COMPLETELY ended!
bus_data_ready <= '0'; -- de-assert bus transaction signals
bus_ack_ready <= '0';
if( Bus2IP_RdCE_concat = '0' and Bus2IP_WrCE_concat = '0' ) then
next_state <= idle;
end if;
when reset =>
reset_sig <= '1'; -- begin reset on cvCore
Reset_Done <= '0'; -- De-assert Reset_Done
next_state <= reset_core;
when reset_core =>
if (ack = '1') then
next_state <= reset_wait_4_ack;
else
next_state <= reset_core;
end if;
when reset_wait_4_ack =>
Reset_Done <= '1'; -- Assert that reset has completed
if( Soft_Reset = '0' ) then -- if reset is complete
Reset_Done <= '0'; -- de-assert that reset is complete
inside_reset_next <= '0'; -- de-assert to signal that process is no longer in reset
next_state <= idle; -- return to idle stage
end if;
when enqueue_begin =>
-- Setup Command
cmd <= '1';
opcode <= OPCODE_ENQUEUE;
cvar <= getCVAR(Bus2IP_Addr);
tid <= getTID(Bus2IP_Addr);
-- Persist with command until ACK is received
if (ack = '1') then
-- De-assert request and continue
cmd <= '0';
opcode <= (others => '0');
cvar <= (others => '0');
tid <= (others => '0');
next_state <= enqueue_finish;
else
-- Persist with request and remain
next_state <= enqueue_begin;
end if;
when enqueue_finish =>
-- Finish transaction
bus_data_out <= (others => '0');
bus_data_ready <= '1';
bus_ack_ready <= '1';
next_state <= wait_trans_done;
when dequeue_begin =>
-- Setup Command
cmd <= '1';
opcode <= OPCODE_DEQUEUE;
cvar <= getCVAR(Bus2IP_Addr);
tid <= getTID(Bus2IP_Addr);
-- Persist with command until ACK is received
if (ack = '1') then
-- De-assert request and continue
cmd <= '0';
opcode <= (others => '0');
cvar <= (others => '0');
tid <= (others => '0');
next_state <= dequeue_finish;
else
-- Persist with request and remain
next_state <= dequeue_begin;
end if;
when dequeue_finish =>
-- Finish transaction
bus_data_out <= (others => '0');
bus_data_ready <= '1';
bus_ack_ready <= '1';
next_state <= wait_trans_done;
when dequeueAll_begin =>
-- Setup Command
cmd <= '1';
opcode <= OPCODE_DEQUEUE_ALL;
cvar <= getCVAR(Bus2IP_Addr);
tid <= getTID(Bus2IP_Addr);
-- Persist with command until ACK is received
if (ack = '1') then
-- De-assert request and continue
cmd <= '0';
opcode <= (others => '0');
cvar <= (others => '0');
tid <= (others => '0');
next_state <= dequeueAll_finish;
else
-- Persist with request and remain
next_state <= dequeueAll_begin;
end if;
when dequeueAll_finish =>
-- Finish transaction
bus_data_out <= (others => '0');
bus_data_ready <= '1';
bus_ack_ready <= '1';
next_state <= wait_trans_done;
when others =>
next_state <= idle;
end case; -- END CASE (current_state)
end process MASTER_FSM_LOGIC_PROC;
end architecture IMP;
|
bsd-3-clause
|
masson2013/heterogeneous_hthreads
|
src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/opb_ipif_v2_00_h/hdl/vhdl/ip2bus_srmux.vhd
|
3
|
7007
|
-------------------------------------------------------------------------------
-- $Id: ip2bus_srmux.vhd,v 1.1 2003/03/15 01:05:25 ostlerf Exp $
-------------------------------------------------------------------------------
-- ip2bus_srmux.vhd - vhdl design file for the entity and architecture
-- of the Mauna Loa IPIF IP to IPIF Bus Status Reply
-- multiplexer (actually just a big OR gate).
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: ip2bus_srmux.vhd
--
-- Description: This vhdl design file is for the entity and architecture
-- of the Mauna Loa IPIF IP to IPIF Bus Status Reply
-- multiplexer (actually just a big OR gate).
--
-------------------------------------------------------------------------------
-- Structure:
--
--
-- ip2bus_srmux.vhd
--
-------------------------------------------------------------------------------
-- Author: D. Thorpe
-- History:
-- DET Apr-25-01 -- First version
--
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
-- Library definitions
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
entity ip2bus_srmux is
port (
-- Status Reply inputs from the IP
IP2Bus_WrAck : in std_logic;
IP2Bus_RdAck : in std_logic;
IP2Bus_Retry : in std_logic;
IP2Bus_Error : in std_logic;
IP2Bus_ToutSup : in std_logic;
-- Status Reply inputs from the Write FIFO
WFIFO_WrAck : in std_logic;
WFIFO_RdAck : in std_logic;
WFIFO_Retry : in std_logic;
WFIFO_Error : in std_logic;
WFIFO_ToutSup : in std_logic;
-- Status Reply inputs from the Read FIFO
RFIFO_WrAck : in std_logic;
RFIFO_RdAck : in std_logic;
RFIFO_Retry : in std_logic;
RFIFO_Error : in std_logic;
RFIFO_ToutSup : in std_logic;
-- Status Reply inputs from the DMA/SG engine
DMA2Bus_WrAck : in std_logic;
DMA2Bus_RdAck : in std_logic;
DMA2Bus_Retry : in std_logic;
DMA2Bus_Error : in std_logic;
DMA2Bus_ToutSup : in std_logic;
-- Status Reply inputs from the Interrupt Collector
IRPT_WrAck : in std_logic;
IRPT_RdAck : in std_logic;
IRPT_Retry : in std_logic;
IRPT_Error : in std_logic;
IRPT_ToutSup : in std_logic;
-- Status reply from the Reset block
RESET_WrAck : In std_logic;
RESET_RdAck : in std_logic;
RESET_Retry : in std_logic;
RESET_Error : in std_logic;
RESET_ToutSup : in std_logic;
-- Status Reply outputs to the Slave Attachment
IP2Bus_WrAck_mx : out std_logic;
IP2Bus_RdAck_mx : out std_logic;
IP2Bus_Retry_mx : out std_logic;
IP2Bus_Error_mx : out std_logic;
IP2Bus_ToutSup_mx : out std_logic
);
end ip2bus_srmux;
architecture implementation of ip2bus_srmux is
-- COMPONENTS
--TYPES
-- no types
-- CONSTANTS
-- no constants
--INTERNAL SIGNALS
--------------------------------------------------------------------------------------------------------------
-------------------------------------- start of logic -------------------------------------------------
begin
-- The following code is for a simple 'OR' function of the input signals
-- to generate a single output. This method works in place of a multiplexer
-- since by definition inactive signals are driven to a logic '0'.
-- Combinational logic
IP2Bus_WrAck_mx <= IP2Bus_WrAck or
WFIFO_WrAck or
RFIFO_WrAck or
DMA2Bus_WrAck or
IRPT_WrAck or
RESET_WrAck;
IP2Bus_RdAck_mx <= IP2Bus_RdAck or
WFIFO_RdAck or
RFIFO_RdAck or
DMA2Bus_RdAck or
IRPT_RdAck or
RESET_RdAck;
IP2Bus_Retry_mx <= IP2Bus_Retry or
WFIFO_Retry or
RFIFO_Retry or
DMA2Bus_Retry or
IRPT_Retry or
RESET_Retry;
IP2Bus_Error_mx <= IP2Bus_Error or
WFIFO_Error or
RFIFO_Error or
DMA2Bus_Error or
IRPT_Error or
RESET_Error;
IP2Bus_ToutSup_mx <= IP2Bus_ToutSup or
WFIFO_ToutSup or
RFIFO_ToutSup or
DMA2Bus_ToutSup or
IRPT_ToutSup or
RESET_ToutSup;
end implementation;
|
bsd-3-clause
|
masson2013/heterogeneous_hthreads
|
src/platforms/xilinx/smp3_opbhwti/design/pcores/opb_ipif_v2_00_h/hdl/vhdl/ip2bus_srmux.vhd
|
3
|
7007
|
-------------------------------------------------------------------------------
-- $Id: ip2bus_srmux.vhd,v 1.1 2003/03/15 01:05:25 ostlerf Exp $
-------------------------------------------------------------------------------
-- ip2bus_srmux.vhd - vhdl design file for the entity and architecture
-- of the Mauna Loa IPIF IP to IPIF Bus Status Reply
-- multiplexer (actually just a big OR gate).
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: ip2bus_srmux.vhd
--
-- Description: This vhdl design file is for the entity and architecture
-- of the Mauna Loa IPIF IP to IPIF Bus Status Reply
-- multiplexer (actually just a big OR gate).
--
-------------------------------------------------------------------------------
-- Structure:
--
--
-- ip2bus_srmux.vhd
--
-------------------------------------------------------------------------------
-- Author: D. Thorpe
-- History:
-- DET Apr-25-01 -- First version
--
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
-- Library definitions
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
entity ip2bus_srmux is
port (
-- Status Reply inputs from the IP
IP2Bus_WrAck : in std_logic;
IP2Bus_RdAck : in std_logic;
IP2Bus_Retry : in std_logic;
IP2Bus_Error : in std_logic;
IP2Bus_ToutSup : in std_logic;
-- Status Reply inputs from the Write FIFO
WFIFO_WrAck : in std_logic;
WFIFO_RdAck : in std_logic;
WFIFO_Retry : in std_logic;
WFIFO_Error : in std_logic;
WFIFO_ToutSup : in std_logic;
-- Status Reply inputs from the Read FIFO
RFIFO_WrAck : in std_logic;
RFIFO_RdAck : in std_logic;
RFIFO_Retry : in std_logic;
RFIFO_Error : in std_logic;
RFIFO_ToutSup : in std_logic;
-- Status Reply inputs from the DMA/SG engine
DMA2Bus_WrAck : in std_logic;
DMA2Bus_RdAck : in std_logic;
DMA2Bus_Retry : in std_logic;
DMA2Bus_Error : in std_logic;
DMA2Bus_ToutSup : in std_logic;
-- Status Reply inputs from the Interrupt Collector
IRPT_WrAck : in std_logic;
IRPT_RdAck : in std_logic;
IRPT_Retry : in std_logic;
IRPT_Error : in std_logic;
IRPT_ToutSup : in std_logic;
-- Status reply from the Reset block
RESET_WrAck : In std_logic;
RESET_RdAck : in std_logic;
RESET_Retry : in std_logic;
RESET_Error : in std_logic;
RESET_ToutSup : in std_logic;
-- Status Reply outputs to the Slave Attachment
IP2Bus_WrAck_mx : out std_logic;
IP2Bus_RdAck_mx : out std_logic;
IP2Bus_Retry_mx : out std_logic;
IP2Bus_Error_mx : out std_logic;
IP2Bus_ToutSup_mx : out std_logic
);
end ip2bus_srmux;
architecture implementation of ip2bus_srmux is
-- COMPONENTS
--TYPES
-- no types
-- CONSTANTS
-- no constants
--INTERNAL SIGNALS
--------------------------------------------------------------------------------------------------------------
-------------------------------------- start of logic -------------------------------------------------
begin
-- The following code is for a simple 'OR' function of the input signals
-- to generate a single output. This method works in place of a multiplexer
-- since by definition inactive signals are driven to a logic '0'.
-- Combinational logic
IP2Bus_WrAck_mx <= IP2Bus_WrAck or
WFIFO_WrAck or
RFIFO_WrAck or
DMA2Bus_WrAck or
IRPT_WrAck or
RESET_WrAck;
IP2Bus_RdAck_mx <= IP2Bus_RdAck or
WFIFO_RdAck or
RFIFO_RdAck or
DMA2Bus_RdAck or
IRPT_RdAck or
RESET_RdAck;
IP2Bus_Retry_mx <= IP2Bus_Retry or
WFIFO_Retry or
RFIFO_Retry or
DMA2Bus_Retry or
IRPT_Retry or
RESET_Retry;
IP2Bus_Error_mx <= IP2Bus_Error or
WFIFO_Error or
RFIFO_Error or
DMA2Bus_Error or
IRPT_Error or
RESET_Error;
IP2Bus_ToutSup_mx <= IP2Bus_ToutSup or
WFIFO_ToutSup or
RFIFO_ToutSup or
DMA2Bus_ToutSup or
IRPT_ToutSup or
RESET_ToutSup;
end implementation;
|
bsd-3-clause
|
masson2013/heterogeneous_hthreads
|
src/hardware/MyRepository/pcores/hw_threads/hw_acc_v1_00_a/hdl/vhdl/user_logics/functional/mutex_lock_1.vhd
|
2
|
16347
|
---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
FUNCTION_EXIT,
STATE_1,
STATE_2,
STATE_3,
STATE_4,
STATE_5,
STATE_6,
STATE_7,
STATE_8,
STATE_9,
STATE_10,
STATE_11,
STATE_12,
STATE_13,
STATE_14,
STATE_15,
STATE_16,
STATE_17,
STATE_18,
STATE_19,
STATE_20,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_STATE_1 : std_logic_vector(0 to 15) := x"0101";
constant U_STATE_2 : std_logic_vector(0 to 15) := x"0102";
constant U_STATE_3 : std_logic_vector(0 to 15) := x"0103";
constant U_STATE_4 : std_logic_vector(0 to 15) := x"0104";
constant U_STATE_5 : std_logic_vector(0 to 15) := x"0105";
constant U_STATE_6 : std_logic_vector(0 to 15) := x"0106";
constant U_STATE_7 : std_logic_vector(0 to 15) := x"0107";
constant U_STATE_8 : std_logic_vector(0 to 15) := x"0108";
constant U_STATE_9 : std_logic_vector(0 to 15) := x"0109";
constant U_STATE_10 : std_logic_vector(0 to 15) := x"0110";
constant U_STATE_11 : std_logic_vector(0 to 15) := x"0111";
constant U_STATE_12 : std_logic_vector(0 to 15) := x"0112";
constant U_STATE_13 : std_logic_vector(0 to 15) := x"0113";
constant U_STATE_14 : std_logic_vector(0 to 15) := x"0114";
constant U_STATE_15 : std_logic_vector(0 to 15) := x"0115";
constant U_STATE_16 : std_logic_vector(0 to 15) := x"0116";
constant U_STATE_17 : std_logic_vector(0 to 15) := x"0117";
constant U_STATE_18 : std_logic_vector(0 to 15) := x"0118";
constant U_STATE_19 : std_logic_vector(0 to 15) := x"0119";
constant U_STATE_20 : std_logic_vector(0 to 15) := x"0120";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
signal retVal, retVal_next : std_logic_vector(0 to 31);
signal arg, arg_next : std_logic_vector(0 to 31);
signal reg1, reg1_next : std_logic_vector(0 to 31);
signal reg2, reg2_next : std_logic_vector(0 to 31);
signal reg3, reg3_next : std_logic_vector(0 to 31);
signal reg4, reg4_next : std_logic_vector(0 to 31);
signal reg5, reg5_next : std_logic_vector(0 to 31);
signal reg6, reg6_next : std_logic_vector(0 to 31);
signal reg7, reg7_next : std_logic_vector(0 to 31);
signal reg8, reg8_next : std_logic_vector(0 to 31);
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock, intrfc2thrd_goWait) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
return_state <= return_state_next;
retVal <= retVal_next;
arg <= arg_next;
reg1 <= reg1_next;
reg2 <= reg2_next;
reg3 <= reg3_next;
reg4 <= reg4_next;
reg5 <= reg5_next;
reg6 <= reg6_next;
reg7 <= reg7_next;
reg8 <= reg8_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_STATE_1 =>
current_state <= STATE_1;
when U_STATE_2 =>
current_state <= STATE_2;
when U_STATE_3 =>
current_state <= STATE_3;
when U_STATE_4 =>
current_state <= STATE_4;
when U_STATE_5 =>
current_state <= STATE_5;
when U_STATE_6 =>
current_state <= STATE_6;
when U_STATE_7 =>
current_state <= STATE_7;
when U_STATE_8 =>
current_state <= STATE_8;
when U_STATE_9 =>
current_state <= STATE_9;
when U_STATE_10 =>
current_state <= STATE_10;
when U_STATE_11 =>
current_state <= STATE_11;
when U_STATE_12 =>
current_state <= STATE_12;
when U_STATE_13 =>
current_state <= STATE_13;
when U_STATE_14 =>
current_state <= STATE_14;
when U_STATE_15 =>
current_state <= STATE_15;
when U_STATE_16 =>
current_state <= STATE_16;
when U_STATE_17 =>
current_state <= STATE_17;
when U_STATE_18 =>
current_state <= STATE_18;
when U_STATE_19 =>
current_state <= STATE_19;
when U_STATE_20 =>
current_state <= STATE_20;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
retVal_next <= retVal;
arg_next <= arg;
reg1_next <= reg1;
reg2_next <= reg2;
reg3_next <= reg3;
reg4_next <= reg4;
reg5_next <= reg5;
reg6_next <= reg6;
reg7_next <= reg7;
reg8_next <= reg8;
-----------------------------------------------------------------------
-- mutex_lock_1.c
-----------------------------------------------------------------------
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
-- hthread_mutex_t * mutex = (hthread_mutex_t *) arg
when FUNCTION_START =>
-- Pop the argument
thrd2intrfc_value <= Z32;
thrd2intrfc_opcode <= OPCODE_POP;
next_state <= WAIT_STATE;
return_state_next <= STATE_1;
when STATE_1 =>
arg_next <= intrfc2thrd_value;
next_state <= STATE_2;
-- hthread_mutex_lock( mutex );
when STATE_2 =>
-- Push mutex
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg;
next_state <= WAIT_STATE;
return_state_next <= STATE_3;
when STATE_3 =>
-- Call hthread_mutex_lock
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_LOCK;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_4;
next_state <= WAIT_STATE;
-- if( _mutex_owner( mutex->num ) == hthread_self() )
when STATE_4 =>
-- Load the value of mutex->num
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg;
next_state <= WAIT_STATE;
return_state_next <= STATE_5;
when STATE_5 =>
reg1_next <= intrfc2thrd_value;
-- Call the Synch Manager to find out the owner
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= x"75030000"; -- and yes I"m cheating with the calculated address
next_state <= WAIT_STATE;
return_state_next <= STATE_6;
when STATE_6 =>
reg1_next <= intrfc2thrd_value;
-- Call hthread_self();
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_SELF;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_7;
next_state <= WAIT_STATE;
when STATE_7 =>
if ( intrfc2thrd_value = reg1 ) then
retVal_next <= Z32;
else
retVal_next <= x"00000001";
end if;
next_state <= STATE_8;
-- hthread_mutex_unlock( mutex );
when STATE_8 =>
-- Push mutex
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg;
next_state <= WAIT_STATE;
return_state_next <= STATE_9;
when STATE_9 =>
-- Call hthread_mutex_unlock
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_UNLOCK;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_10;
next_state <= WAIT_STATE;
when STATE_10 =>
next_state <= FUNCTION_EXIT;
when FUNCTION_EXIT =>
--Same as hthread_exit( (void *) retVal );
thrd2intrfc_value <= retVal;
thrd2intrfc_opcode <= OPCODE_RETURN;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
|
bsd-3-clause
|
masson2013/heterogeneous_hthreads
|
src/platforms/xilinx/numa3_hwti/design/pcores/plb_thread_manager_v1_00_a/hdl/vhdl/infer_bram_dual_port.vhd
|
11
|
5321
|
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
-- *************************************************************************
-- File: infer_bram_dual_port.vhd
-- Date: 06/22/05
-- Purpose: File used to instantiate an inferred BRAM (dual port),
-- According to Xilinx, this will only work with 7.1 b/c of shared variables.
-- Author: Jason Agron
-- *************************************************************************
-- *************************************************************************
-- Library declarations
-- *************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_misc.all;
use IEEE.numeric_std.all;
library Unisim;
use Unisim.all;
library Unisim;
use Unisim.all;
-- *************************************************************************
-- Entity declaration
-- *************************************************************************
entity infer_bram_dual_port is
generic (
ADDRESS_BITS : integer := 9;
DATA_BITS : integer := 32
);
port (
CLKA : in std_logic;
ENA : in std_logic;
WEA : in std_logic;
ADDRA : in std_logic_vector(0 to ADDRESS_BITS - 1);
DIA : in std_logic_vector(0 to DATA_BITS - 1);
DOA : out std_logic_vector(0 to DATA_BITS - 1);
CLKB : in std_logic;
ENB : in std_logic;
WEB : in std_logic;
ADDRB : in std_logic_vector(0 to ADDRESS_BITS - 1);
DIB : in std_logic_vector(0 to DATA_BITS - 1);
DOB : out std_logic_vector(0 to DATA_BITS - 1)
);
end entity infer_bram_dual_port;
-- *************************************************************************
-- Architecture declaration
-- *************************************************************************
architecture implementation of infer_bram_dual_port is
-- Constant declarations
constant BRAM_SIZE : integer := 2 **ADDRESS_BITS; -- # of entries in the inferred BRAM
-- BRAM data storage (array)
type bram_storage is array( 0 to BRAM_SIZE - 1 ) of std_logic_vector( 0 to DATA_BITS - 1 );
shared variable BRAM_DATA : bram_storage;
begin
-- *************************************************************************
-- Process: BRAM_CONTROLLER_A
-- Purpose: Controller for Port A of inferred dual-port BRAM, BRAM_DATA
-- *************************************************************************
BRAM_CONTROLLER_A : process(CLKA) is
begin
if( CLKA'event and CLKA = '1' ) then
if( ENA = '1' ) then
if( WEA = '1' ) then
BRAM_DATA( conv_integer(ADDRA) ) := DIA;
end if;
DOA <= BRAM_DATA( conv_integer(ADDRA) );
end if;
end if;
end process BRAM_CONTROLLER_A;
-- *************************************************************************
-- Process: BRAM_CONTROLLER_B
-- Purpose: Controller for Port B of inferred dual-port BRAM, BRAM_DATA
-- *************************************************************************
BRAM_CONTROLLER_B : process(CLKB) is
begin
if( CLKB'event and CLKB = '1' ) then
if( ENB = '1' ) then
if( WEB = '1' ) then
BRAM_DATA( conv_integer(ADDRB) ) := DIB;
end if;
DOB <= BRAM_DATA( conv_integer(ADDRB) );
end if;
end if;
end process BRAM_CONTROLLER_B;
end architecture implementation;
|
bsd-3-clause
|
masson2013/heterogeneous_hthreads
|
src/platforms/xilinx/hwti_mblaze_6smp/design/pcores/plb_thread_manager_v1_00_a/hdl/vhdl/infer_bram_dual_port.vhd
|
11
|
5321
|
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
-- *************************************************************************
-- File: infer_bram_dual_port.vhd
-- Date: 06/22/05
-- Purpose: File used to instantiate an inferred BRAM (dual port),
-- According to Xilinx, this will only work with 7.1 b/c of shared variables.
-- Author: Jason Agron
-- *************************************************************************
-- *************************************************************************
-- Library declarations
-- *************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_misc.all;
use IEEE.numeric_std.all;
library Unisim;
use Unisim.all;
library Unisim;
use Unisim.all;
-- *************************************************************************
-- Entity declaration
-- *************************************************************************
entity infer_bram_dual_port is
generic (
ADDRESS_BITS : integer := 9;
DATA_BITS : integer := 32
);
port (
CLKA : in std_logic;
ENA : in std_logic;
WEA : in std_logic;
ADDRA : in std_logic_vector(0 to ADDRESS_BITS - 1);
DIA : in std_logic_vector(0 to DATA_BITS - 1);
DOA : out std_logic_vector(0 to DATA_BITS - 1);
CLKB : in std_logic;
ENB : in std_logic;
WEB : in std_logic;
ADDRB : in std_logic_vector(0 to ADDRESS_BITS - 1);
DIB : in std_logic_vector(0 to DATA_BITS - 1);
DOB : out std_logic_vector(0 to DATA_BITS - 1)
);
end entity infer_bram_dual_port;
-- *************************************************************************
-- Architecture declaration
-- *************************************************************************
architecture implementation of infer_bram_dual_port is
-- Constant declarations
constant BRAM_SIZE : integer := 2 **ADDRESS_BITS; -- # of entries in the inferred BRAM
-- BRAM data storage (array)
type bram_storage is array( 0 to BRAM_SIZE - 1 ) of std_logic_vector( 0 to DATA_BITS - 1 );
shared variable BRAM_DATA : bram_storage;
begin
-- *************************************************************************
-- Process: BRAM_CONTROLLER_A
-- Purpose: Controller for Port A of inferred dual-port BRAM, BRAM_DATA
-- *************************************************************************
BRAM_CONTROLLER_A : process(CLKA) is
begin
if( CLKA'event and CLKA = '1' ) then
if( ENA = '1' ) then
if( WEA = '1' ) then
BRAM_DATA( conv_integer(ADDRA) ) := DIA;
end if;
DOA <= BRAM_DATA( conv_integer(ADDRA) );
end if;
end if;
end process BRAM_CONTROLLER_A;
-- *************************************************************************
-- Process: BRAM_CONTROLLER_B
-- Purpose: Controller for Port B of inferred dual-port BRAM, BRAM_DATA
-- *************************************************************************
BRAM_CONTROLLER_B : process(CLKB) is
begin
if( CLKB'event and CLKB = '1' ) then
if( ENB = '1' ) then
if( WEB = '1' ) then
BRAM_DATA( conv_integer(ADDRB) ) := DIB;
end if;
DOB <= BRAM_DATA( conv_integer(ADDRB) );
end if;
end if;
end process BRAM_CONTROLLER_B;
end architecture implementation;
|
bsd-3-clause
|
masson2013/heterogeneous_hthreads
|
src/hardware/MyRepository/pcores/axi_hthread_cores/proc_common_v3_00_a/hdl/vhdl/dynshreg2_f.vhd
|
2
|
16198
|
-------------------------------------------------------------------------------
-- $Id: dynshreg2_f.vhd,v 1.1.4.50 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- dynshreg2_f - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2005-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: dynshreg2_f.vhd
--
-- Description: This module implements a dynamic shift register with clock
-- enable. (Think, for example, of the function of the SRL16E.)
-- The width and depth of the shift register are selectable
-- via generics C_WIDTH and C_DEPTH, respectively. The C_FAMILY
-- allows the implementation to be tailored to the target
-- FPGA family. An inferred implementation is used if C_FAMILY
-- is "nofamily" (the default) or if synthesis will not produce
-- an optimal implementation. Otherwise, a structural
-- implementation will be generated.
--
-- There is no restriction on the values of C_WIDTH and
-- C_DEPTH and, in particular, the C_DEPTH does not have
-- to be a power of two.
--
-- This version differs from dynshreg_f only in that it
-- has a work around needed to get the C_DEPTH = 1 case
-- past a target synthesis tool.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-------------------------------------------------------------------------------
-- Author: Farrell Ostler
--
-- History:
-- FLO 12/05/05 First Version. Derived from srl_fifo_rbu.
-- Functionally identical but with work-around
-- as noted in the description.
--
-- ~~~~~~
-- FLO MM/DD/YYYY
-- ^^^^^^
-- History comment.
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- predecessor value by # clks: "*_p#"
---(
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.UNSIGNED;
use ieee.numeric_std.TO_INTEGER;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.clog2;
entity dynshreg2_f is
generic (
C_DEPTH : positive := 32;
C_DWIDTH : natural := 1;
C_FAMILY : string := "nofamily"
);
port (
Clk : in std_logic;
Clken : in std_logic;
Addr : in std_logic_vector(0 to clog2(C_DEPTH)-1);
Din : in std_logic_vector(0 to C_DWIDTH-1);
Dout : out std_logic_vector(0 to C_DWIDTH-1)
);
end dynshreg2_f;
library proc_common_v3_00_a;
use proc_common_v3_00_a.family_support.all;
library unisim;
use unisim.all; -- Make unisim entities available for default binding.
architecture behavioral of dynshreg2_f is
constant K_FAMILY : families_type := str2fam(C_FAMILY);
--
constant W32 : boolean := supported(K_FAMILY, u_SRLC32E) and
(C_DEPTH > 16 or not supported(K_FAMILY, u_SRL16E));
constant W16 : boolean := supported(K_FAMILY, u_SRLC16E) and not W32;
-- XST faster if these two constants are declared here
-- instead of in STRUCTURAL_A_GEN. (I.25)
--
function power_of_2(n: positive) return boolean is
variable i: positive := 1;
begin
while n > i loop i := i*2; end loop;
return n = i;
end power_of_2;
--
constant USE_ONEDEEP : boolean := (C_DEPTH = 1); -- Case needing XST workaround
--
constant USE_INFERRED : boolean := not USE_ONEDEEP
and
(
( power_of_2(C_DEPTH)
and ( (W16 and C_DEPTH >= 16)
or (W32 and C_DEPTH >= 32)
)
)
or (not W32 and not W16)
);
-- As of I.32, XST is not infering optimal dynamic shift registers for
-- depths not a power of two (by not taking advantage of don't care
-- at output when address not within the range of the depth)
-- or a power of two less than the native SRL depth (by building shift
-- register out of discrete FFs and LUTs instead of SRLs).
constant USE_STRUCTURAL_A : boolean := not USE_INFERRED and not USE_ONEDEEP;
function min(a, b: natural) return natural is
begin
if a<b then return a; else return b; end if;
end min;
----------------------------------------------------------------------------
-- Unisim components declared locally for maximum avoidance of default
-- binding and vcomponents version issues.
----------------------------------------------------------------------------
component SRLC16E
generic
(
INIT : bit_vector := X"0000"
);
port
(
Q : out STD_ULOGIC;
Q15 : out STD_ULOGIC;
A0 : in STD_ULOGIC;
A1 : in STD_ULOGIC;
A2 : in STD_ULOGIC;
A3 : in STD_ULOGIC;
CE : in STD_ULOGIC;
CLK : in STD_ULOGIC;
D : in STD_ULOGIC
);
end component;
component SRLC32E
generic
(
INIT : bit_vector := X"00000000"
);
port
(
Q : out STD_ULOGIC;
Q31 : out STD_ULOGIC;
A : in STD_LOGIC_VECTOR (4 downto 0);
CE : in STD_ULOGIC;
CLK : in STD_ULOGIC;
D : in STD_ULOGIC
);
end component;
begin
---(
STRUCTURAL_A_GEN : if USE_STRUCTURAL_A = true generate
type bo2na_type is array(boolean) of natural;
constant bo2na : bo2na_type := (false => 0, true => 1);
constant BPSRL : natural := bo2na(W16)*16 + bo2na(W32)*32; -- Bits per SRL
constant BTASRL : natural := clog2(BPSRL); -- Bits To Address SRL
constant NUM_SRLS_DEEP : natural := (C_DEPTH + BPSRL-1)/BPSRL;
constant ADDR_BITS : integer := Addr'length;
signal dynshreg_addr : std_logic_vector(ADDR_BITS-1 downto 0);
signal cascade_sigs : std_logic_vector(0 to C_DWIDTH*(NUM_SRLS_DEEP+1) - 1);
-- The data signals at the inputs and daisy-chain outputs of SRLs.
-- The last signal of each cascade is not used.
--
signal q_sigs : std_logic_vector(0 to C_DWIDTH*NUM_SRLS_DEEP - 1);
-- The data signals at the addressble outputs of SRLs.
---)(
begin
DIN_TO_CASCADE_GEN : for i in 0 to C_DWIDTH-1 generate
cascade_sigs(i*(NUM_SRLS_DEEP+1)) <= Din(i);
end generate;
dynshreg_addr(ADDR_BITS-1 downto 0) <= Addr(0 to ADDR_BITS-1);
BIT_OF_WIDTH_GEN : for i in 0 to C_DWIDTH-1 generate
CASCADES_GEN : for j in 0 to NUM_SRLS_DEEP-1 generate
signal srl_addr: std_logic_vector(4 downto 0);
begin
-- Here we form the address for the SRL elements. This is just
-- the corresponding low-order bits of dynshreg_addr but we
-- also handle the case where we have to zero-pad to the left
-- a dynshreg_addr that is smaller than the SRL address port.
SRL_ADDR_LO_GEN : for i in 0 to min(ADDR_BITS-1,4) generate
srl_addr(i) <= dynshreg_addr(i);
end generate;
SRL_ADDR_HI_GEN : for i in min(ADDR_BITS-1,4)+1 to 4 generate
srl_addr(i) <= '0';
end generate;
W16_GEN : if W16 generate
SRLC16E_I : component SRLC16E
port map
(
Q => q_sigs(j + i*NUM_SRLS_DEEP),
Q15 => cascade_sigs(j+1 + i*(NUM_SRLS_DEEP+1)),
A0 => srl_addr(0),
A1 => srl_addr(1),
A2 => srl_addr(2),
A3 => srl_addr(3),
CE => Clken,
Clk => Clk,
D => cascade_sigs(j + i*(NUM_SRLS_DEEP+1))
)
;
end generate;
W32_GEN : if W32 generate
begin
SRLC32E_I : component SRLC32E
port map
(
Q => q_sigs(j + i*NUM_SRLS_DEEP),
Q31 => cascade_sigs(j+1 + i*(NUM_SRLS_DEEP+1)),
A => srl_addr(4 downto 0),
CE => Clken,
Clk => Clk,
D => cascade_sigs(j + i*(NUM_SRLS_DEEP+1))
)
;
end generate;
end generate CASCADES_GEN;
end generate BIT_OF_WIDTH_GEN;
----------------------------------------------------------------------------
-- Generate a MUXFn structure to select the proper SRL
-- as the output of each shift register.
----------------------------------------------------------------------------
SINGLE_SRL_GEN : if NUM_SRLS_DEEP = 1 generate
Dout <= q_sigs;
end generate;
--
MULTI_SRL_GEN : if NUM_SRLS_DEEP > 1 generate
PER_BIT_GEN : for i in 0 to C_DWIDTH-1 generate
begin
MUXF_STRUCT_I0 : entity proc_common_v3_00_a.muxf_struct_f
generic map (
C_START_LEVEL => native_lut_size(fam => K_FAMILY,
no_lut_return_val => 10000),
-- Artificially high value for C_START_LEVEL when no LUT is
-- supported will cause muxf_struct_f to default to inferred
-- multiplexers.
C_NUM_INPUTS => NUM_SRLS_DEEP,
C_FAMILY => C_FAMILY
)
port map (
O => Dout(i),
Iv => q_sigs(i * (NUM_SRLS_DEEP) to
(i+1) * (NUM_SRLS_DEEP) - 1),
Sel => dynshreg_addr(ADDR_BITS-1 downto BTASRL)
--Bits To Addr SRL
)
;
end generate;
end generate;
end generate STRUCTURAL_A_GEN;
---)
---(
INFERRED_GEN : if USE_INFERRED = true generate
type dataType is array (0 to C_DEPTH-1) of std_logic_vector(0 to C_DWIDTH-1);
signal data: dataType;
begin
process(Clk)
begin
if Clk'event and Clk = '1' then
if Clken = '1' then
data <= Din & data(0 to C_DEPTH-2);
end if;
end if;
end process;
Dout <= data(TO_INTEGER(UNSIGNED(Addr)))
when (TO_INTEGER(UNSIGNED(Addr)) < C_DEPTH)
else
(others => '-');
end generate INFERRED_GEN;
---)
---(
INFERRED_ONEDEEP : if USE_ONEDEEP = true generate
signal data: std_logic_vector (0 to C_DWIDTH-1);
begin
process(Clk)
begin
if Clk'event and Clk = '1' then
if Clken = '1' then
data <= Din;
end if;
end if;
end process;
Dout <= data;
end generate INFERRED_ONEDEEP;
---)
end behavioral;
---)
|
bsd-3-clause
|
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