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tdaede/daala_zynq
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daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_auto_pc_121_0/blk_mem_gen_v8_0/blk_mem_input_block.vhd
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r2EZMqT95Hmi
`protect end_protected
|
bsd-2-clause
|
tdaede/daala_zynq
|
daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_dma_0_0/axi_dma_v7_1/hdl/src/vhdl/axi_dma_rst_module.vhd
|
1
|
24298
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_rst_module.vhd
-- Description: This entity is the top level reset module entity for the
-- AXI VDMA core.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1;
use axi_dma_v7_1.axi_dma_pkg.all;
library proc_common_v4_0;
use proc_common_v4_0.family_support.all;
-------------------------------------------------------------------------------
entity axi_dma_rst_module is
generic(
C_INCLUDE_MM2S : integer range 0 to 1 := 1;
-- Include or exclude MM2S primary data path
-- 0 = Exclude MM2S primary data path
-- 1 = Include MM2S primary data path
C_INCLUDE_S2MM : integer range 0 to 1 := 1;
-- Include or exclude S2MM primary data path
-- 0 = Exclude S2MM primary data path
-- 1 = Include S2MM primary data path
C_INCLUDE_SG : integer range 0 to 1 := 1;
-- Include or Exclude the Scatter Gather Engine
-- 0 = Exclude SG Engine - Enables Simple DMA Mode
-- 1 = Include SG Engine - Enables Scatter Gather Mode
C_SG_INCLUDE_STSCNTRL_STRM : integer range 0 to 1 := 1;
-- Include or Exclude AXI Status and AXI Control Streams
-- 0 = Exclude Status and Control Streams
-- 1 = Include Status and Control Streams
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Primary data path channels (MM2S and S2MM)
-- run asynchronous to AXI Lite, DMA Control,
-- and SG.
C_M_AXI_MM2S_ACLK_FREQ_HZ : integer := 100000000;
-- Primary clock frequency in hertz
C_M_AXI_S2MM_ACLK_FREQ_HZ : integer := 100000000;
-- Primary clock frequency in hertz
C_M_AXI_SG_ACLK_FREQ_HZ : integer := 100000000
-- Scatter Gather clock frequency in hertz
);
port (
-----------------------------------------------------------------------
-- Clock Sources
-----------------------------------------------------------------------
s_axi_lite_aclk : in std_logic ;
m_axi_sg_aclk : in std_logic ; --
m_axi_mm2s_aclk : in std_logic ; --
m_axi_s2mm_aclk : in std_logic ; --
--
----------------------------------------------------------------------- --
-- Hard Reset --
----------------------------------------------------------------------- --
axi_resetn : in std_logic ; --
----------------------------------------------------------------------- --
-- Soft Reset --
----------------------------------------------------------------------- --
soft_reset : in std_logic ; --
soft_reset_clr : out std_logic := '0' ; --
--
----------------------------------------------------------------------- --
-- MM2S Soft Reset Support --
----------------------------------------------------------------------- --
mm2s_all_idle : in std_logic ; --
mm2s_stop : in std_logic ; --
mm2s_halt : out std_logic := '0' ; --
mm2s_halt_cmplt : in std_logic ; --
--
----------------------------------------------------------------------- --
-- S2MM Soft Reset Support --
----------------------------------------------------------------------- --
s2mm_all_idle : in std_logic ; --
s2mm_stop : in std_logic ; --
s2mm_halt : out std_logic := '0' ; --
s2mm_halt_cmplt : in std_logic ; --
--
----------------------------------------------------------------------- --
-- MM2S Distributed Reset Out --
----------------------------------------------------------------------- --
-- AXI DataMover Primary Reset (Raw) --
dm_mm2s_prmry_resetn : out std_logic := '1' ; --
-- AXI DataMover Secondary Reset (Raw) --
dm_mm2s_scndry_resetn : out std_logic := '1' ;
-- AXI Stream Primary Reset Outputs --
mm2s_prmry_reset_out_n : out std_logic := '1' ; --
-- AXI Stream Control Reset Outputs --
mm2s_cntrl_reset_out_n : out std_logic := '1' ; --
-- AXI Secondary reset
mm2s_scndry_resetn : out std_logic := '1' ; --
-- AXI Upsizer and Line Buffer --
mm2s_prmry_resetn : out std_logic := '1' ; --
--
--
----------------------------------------------------------------------- --
-- S2MM Distributed Reset Out --
----------------------------------------------------------------------- --
-- AXI DataMover Primary Reset (Raw) --
dm_s2mm_prmry_resetn : out std_logic := '1' ; --
-- AXI DataMover Secondary Reset (Raw) --
dm_s2mm_scndry_resetn : out std_logic := '1' ;
-- AXI Stream Primary Reset Outputs --
s2mm_prmry_reset_out_n : out std_logic := '1' ; --
-- AXI Stream Control Reset Outputs --
s2mm_sts_reset_out_n : out std_logic := '1' ; --
-- AXI Secondary reset
s2mm_scndry_resetn : out std_logic := '1' ; --
-- AXI Upsizer and Line Buffer --
s2mm_prmry_resetn : out std_logic := '1' ; --
----------------------------------------------------------------------- --
-- Scatter Gather Distributed Reset Out
----------------------------------------------------------------------- --
-- AXI Scatter Gather Reset Out
m_axi_sg_aresetn : out std_logic := '1' ; --
-- AXI Scatter Gather Datamover Reset Out
dm_m_axi_sg_aresetn : out std_logic := '1' ; --
----------------------------------------------------------------------- --
-- Hard Reset Out --
----------------------------------------------------------------------- --
m_axi_sg_hrdresetn : out std_logic := '1' ; --
s_axi_lite_resetn : out std_logic := '1' --
);
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
Attribute KEEP of s_axi_lite_resetn : signal is "TRUE";
Attribute KEEP of m_axi_sg_hrdresetn : signal is "TRUE";
Attribute EQUIVALENT_REGISTER_REMOVAL of s_axi_lite_resetn : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of m_axi_sg_hrdresetn : signal is "no";
end axi_dma_rst_module;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_rst_module is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
ATTRIBUTE async_reg : STRING;
signal hrd_resetn_i_cdc_tig : std_logic := '1';
signal hrd_resetn_i_d1_cdc_tig : std_logic := '1';
--ATTRIBUTE async_reg OF hrd_resetn_i_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF hrd_resetn_i_d1_cdc_tig : SIGNAL IS "true";
-- Soft reset support
signal mm2s_soft_reset_clr : std_logic := '0';
signal s2mm_soft_reset_clr : std_logic := '0';
signal soft_reset_clr_i : std_logic := '0';
signal mm2s_soft_reset_done : std_logic := '0';
signal s2mm_soft_reset_done : std_logic := '0';
signal mm2s_scndry_resetn_i : std_logic := '0';
signal s2mm_scndry_resetn_i : std_logic := '0';
signal dm_mm2s_scndry_resetn_i : std_logic := '0';
signal dm_s2mm_scndry_resetn_i : std_logic := '0';
signal sg_hard_reset : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Register hard reset in
REG_HRD_RST : entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => axi_resetn,
prmry_vect_in => (others => '0'),
scndry_aclk => m_axi_sg_aclk,
scndry_resetn => '0',
scndry_out => sg_hard_reset,
scndry_vect_out => open
);
m_axi_sg_hrdresetn <= sg_hard_reset;
--REG_HRD_RST : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- hrd_resetn_i_cdc_tig <= axi_resetn;
-- m_axi_sg_hrdresetn <= hrd_resetn_i_cdc_tig;
-- end if;
-- end process REG_HRD_RST;
-- Regsiter hard reset out for axi lite interface
REG_HRD_RST_OUT : entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => axi_resetn,
prmry_vect_in => (others => '0'),
scndry_aclk => s_axi_lite_aclk,
scndry_resetn => '0',
scndry_out => s_axi_lite_resetn,
scndry_vect_out => open
);
--REG_HRD_RST_OUT : process(s_axi_lite_aclk)
-- begin
-- if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
-- hrd_resetn_i_d1_cdc_tig <= hrd_resetn_i_cdc_tig;
-- s_axi_lite_resetn <= hrd_resetn_i_d1_cdc_tig;
-- end if;
-- end process REG_HRD_RST_OUT;
dm_mm2s_scndry_resetn <= dm_mm2s_scndry_resetn_i;
dm_s2mm_scndry_resetn <= dm_s2mm_scndry_resetn_i;
-- mm2s channel included therefore map secondary resets to
-- from mm2s reset module to scatter gather interface (default)
MAP_SG_FOR_BOTH : if C_INCLUDE_MM2S = 1 and C_INCLUDE_S2MM = 1 generate
begin
-- both must be low before sg reset is asserted.
m_axi_sg_aresetn <= mm2s_scndry_resetn_i or s2mm_scndry_resetn_i;
dm_m_axi_sg_aresetn <= dm_mm2s_scndry_resetn_i or dm_s2mm_scndry_resetn_i;
end generate MAP_SG_FOR_BOTH;
-- Only s2mm channel included therefore map secondary resets to
-- from s2mm reset module to scatter gather interface
MAP_SG_FOR_S2MM : if C_INCLUDE_MM2S = 0 and C_INCLUDE_S2MM = 1 generate
begin
m_axi_sg_aresetn <= s2mm_scndry_resetn_i;
dm_m_axi_sg_aresetn <= dm_s2mm_scndry_resetn_i;
end generate MAP_SG_FOR_S2MM;
-- Only mm2s channel included therefore map secondary resets to
-- from mm2s reset module to scatter gather interface
MAP_SG_FOR_MM2S : if C_INCLUDE_MM2S = 1 and C_INCLUDE_S2MM = 0 generate
begin
m_axi_sg_aresetn <= mm2s_scndry_resetn_i;
dm_m_axi_sg_aresetn <= dm_mm2s_scndry_resetn_i;
end generate MAP_SG_FOR_MM2S;
-- Invalid configuration for axi dma - simply here for completeness
MAP_NO_SG : if C_INCLUDE_MM2S = 0 and C_INCLUDE_S2MM = 0 generate
begin
m_axi_sg_aresetn <= '1';
dm_m_axi_sg_aresetn <= '1';
end generate MAP_NO_SG;
s2mm_scndry_resetn <= s2mm_scndry_resetn_i;
mm2s_scndry_resetn <= mm2s_scndry_resetn_i;
-- Generate MM2S reset signals
GEN_RESET_FOR_MM2S : if C_INCLUDE_MM2S = 1 generate
begin
RESET_I : entity axi_dma_v7_1.axi_dma_reset
generic map(
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_AXI_PRMRY_ACLK_FREQ_HZ => C_M_AXI_MM2S_ACLK_FREQ_HZ ,
C_AXI_SCNDRY_ACLK_FREQ_HZ => C_M_AXI_SG_ACLK_FREQ_HZ ,
C_SG_INCLUDE_STSCNTRL_STRM => C_SG_INCLUDE_STSCNTRL_STRM ,
C_INCLUDE_SG => C_INCLUDE_SG
)
port map(
-- Clock Sources
m_axi_sg_aclk => m_axi_sg_aclk ,
axi_prmry_aclk => m_axi_mm2s_aclk ,
-- Hard Reset
axi_resetn => sg_hard_reset ,
-- Soft Reset
soft_reset => soft_reset ,
soft_reset_clr => mm2s_soft_reset_clr ,
soft_reset_done => soft_reset_clr_i ,
all_idle => mm2s_all_idle ,
stop => mm2s_stop ,
halt => mm2s_halt ,
halt_cmplt => mm2s_halt_cmplt ,
-- Secondary Reset
scndry_resetn => mm2s_scndry_resetn_i ,
-- AXI Upsizer and Line Buffer
prmry_resetn => mm2s_prmry_resetn ,
-- AXI DataMover Primary Reset (Raw)
dm_prmry_resetn => dm_mm2s_prmry_resetn ,
-- AXI DataMover Secondary Reset (Raw)
dm_scndry_resetn => dm_mm2s_scndry_resetn_i ,
-- AXI Stream Primary Reset Outputs
prmry_reset_out_n => mm2s_prmry_reset_out_n ,
-- AXI Stream Alternate Reset Outputs
altrnt_reset_out_n => mm2s_cntrl_reset_out_n
);
-- Sample an hold mm2s soft reset done to use in
-- combined reset done to DMACR
MM2S_SOFT_RST_DONE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(sg_hard_reset = '0' or soft_reset_clr_i = '1')then
mm2s_soft_reset_done <= '0';
elsif(mm2s_soft_reset_clr = '1')then
mm2s_soft_reset_done <= '1';
end if;
end if;
end process MM2S_SOFT_RST_DONE;
end generate GEN_RESET_FOR_MM2S;
-- No MM2S therefore tie off mm2s reset signals
GEN_NO_RESET_FOR_MM2S : if C_INCLUDE_MM2S = 0 generate
begin
mm2s_prmry_reset_out_n <= '1';
mm2s_cntrl_reset_out_n <= '1';
dm_mm2s_scndry_resetn_i <= '1';
dm_mm2s_prmry_resetn <= '1';
mm2s_prmry_resetn <= '1';
mm2s_scndry_resetn_i <= '1';
mm2s_halt <= '0';
mm2s_soft_reset_clr <= '0';
mm2s_soft_reset_done <= '1';
end generate GEN_NO_RESET_FOR_MM2S;
-- Generate S2MM reset signals
GEN_RESET_FOR_S2MM : if C_INCLUDE_S2MM = 1 generate
begin
RESET_I : entity axi_dma_v7_1.axi_dma_reset
generic map(
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_AXI_PRMRY_ACLK_FREQ_HZ => C_M_AXI_S2MM_ACLK_FREQ_HZ ,
C_AXI_SCNDRY_ACLK_FREQ_HZ => C_M_AXI_SG_ACLK_FREQ_HZ ,
C_SG_INCLUDE_STSCNTRL_STRM => C_SG_INCLUDE_STSCNTRL_STRM ,
C_INCLUDE_SG => C_INCLUDE_SG
)
port map(
-- Clock Sources
m_axi_sg_aclk => m_axi_sg_aclk ,
axi_prmry_aclk => m_axi_s2mm_aclk ,
-- Hard Reset
axi_resetn => sg_hard_reset ,
-- Soft Reset
soft_reset => soft_reset ,
soft_reset_clr => s2mm_soft_reset_clr ,
soft_reset_done => soft_reset_clr_i ,
all_idle => s2mm_all_idle ,
stop => s2mm_stop ,
halt => s2mm_halt ,
halt_cmplt => s2mm_halt_cmplt ,
-- Secondary Reset
scndry_resetn => s2mm_scndry_resetn_i ,
-- AXI Upsizer and Line Buffer
prmry_resetn => s2mm_prmry_resetn ,
-- AXI DataMover Primary Reset (Raw)
dm_prmry_resetn => dm_s2mm_prmry_resetn ,
-- AXI DataMover Secondary Reset (Raw)
dm_scndry_resetn => dm_s2mm_scndry_resetn_i ,
-- AXI Stream Primary Reset Outputs
prmry_reset_out_n => s2mm_prmry_reset_out_n ,
-- AXI Stream Alternate Reset Outputs
altrnt_reset_out_n => s2mm_sts_reset_out_n
);
-- Sample an hold s2mm soft reset done to use in
-- combined reset done to DMACR
S2MM_SOFT_RST_DONE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(sg_hard_reset = '0' or soft_reset_clr_i = '1')then
s2mm_soft_reset_done <= '0';
elsif(s2mm_soft_reset_clr = '1')then
s2mm_soft_reset_done <= '1';
end if;
end if;
end process S2MM_SOFT_RST_DONE;
end generate GEN_RESET_FOR_S2MM;
-- No SsMM therefore tie off mm2s reset signals
GEN_NO_RESET_FOR_S2MM : if C_INCLUDE_S2MM = 0 generate
begin
s2mm_prmry_reset_out_n <= '1';
dm_s2mm_scndry_resetn_i <= '1';
dm_s2mm_prmry_resetn <= '1';
s2mm_prmry_resetn <= '1';
s2mm_scndry_resetn_i <= '1';
s2mm_halt <= '0';
s2mm_soft_reset_clr <= '0';
s2mm_soft_reset_done <= '1';
end generate GEN_NO_RESET_FOR_S2MM;
-- When both mm2s and s2mm are done then drive soft reset clear and
-- also clear s_h registers above
soft_reset_clr_i <= s2mm_soft_reset_done and mm2s_soft_reset_done;
soft_reset_clr <= soft_reset_clr_i;
end implementation;
|
bsd-2-clause
|
schelleg/PYNQ
|
boards/ip/dvi2rgb_v1_7/src/SyncBase.vhd
|
15
|
3854
|
-------------------------------------------------------------------------------
--
-- File: SyncBase.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 20 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module synchronizes a signal (iIn) in one clock domain (InClk) with
-- another clock domain (OutClk) and provides it on oOut.
-- The number of FFs in the synchronizer chain
-- can be configured with kStages. The reset value for oOut can be configured
-- with kResetTo. The asynchronous reset (aReset) is always active-high.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity SyncBase is
Generic (
kResetTo : std_logic := '0'; --value when reset and upon init
kStages : natural := 2); --double sync by default
Port (
aReset : in STD_LOGIC; -- active-high asynchronous reset
InClk : in std_logic;
iIn : in STD_LOGIC;
OutClk : in STD_LOGIC;
oOut : out STD_LOGIC);
end SyncBase;
architecture Behavioral of SyncBase is
signal iIn_q : std_logic;
begin
--By re-registering iIn on its own domain, we make sure iIn_q is glitch-free
SyncSource: process(aReset, InClk)
begin
if (aReset = '1') then
iIn_q <= kResetTo;
elsif Rising_Edge(InClk) then
iIn_q <= iIn;
end if;
end process SyncSource;
--Crossing clock boundary here
SyncAsyncx: entity work.SyncAsync
generic map (
kResetTo => kResetTo,
kStages => kStages)
port map (
aReset => aReset,
aIn => iIn_q,
OutClk => OutClk,
oOut => oOut);
end Behavioral;
|
bsd-3-clause
|
schelleg/PYNQ
|
boards/ip/dvi2rgb_v1_7/src/dvi2rgb.vhd
|
4
|
11324
|
-------------------------------------------------------------------------------
--
-- File: dvi2rgb.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 24 July 2015
--
-------------------------------------------------------------------------------
-- (c) 2015 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module connects to a top level DVI 1.0 sink interface comprised of three
-- TMDS data channels and one TMDS clock channel. It includes the necessary
-- clock infrastructure, deserialization, phase alignment, channel deskew and
-- decode logic. It outputs 24-bit RGB video data along with pixel clock and
-- synchronization signals.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.DVI_Constants.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity dvi2rgb is
Generic (
kEmulateDDC : boolean := true; --will emulate a DDC EEPROM with basic EDID, if set to yes
kRstActiveHigh : boolean := true; --true, if active-high; false, if active-low
kAddBUFG : boolean := true; --true, if PixelClk should be re-buffered with BUFG
kClkRange : natural := 2; -- MULT_F = kClkRange*5 (choose >=120MHz=1, >=60MHz=2, >=40MHz=3)
kEdidFileName : string := "900p_edid.data"; -- Select EDID file to use
-- 7-series specific
kIDLY_TapValuePs : natural := 78; --delay in ps per tap
kIDLY_TapWidth : natural := 5); --number of bits for IDELAYE2 tap counter
Port (
-- DVI 1.0 TMDS video interface
TMDS_Clk_p : in std_logic;
TMDS_Clk_n : in std_logic;
TMDS_Data_p : in std_logic_vector(2 downto 0);
TMDS_Data_n : in std_logic_vector(2 downto 0);
-- Auxiliary signals
RefClk : in std_logic; --200 MHz reference clock for IDELAYCTRL, reset, lock monitoring etc.
aRst : in std_logic; --asynchronous reset; must be reset when RefClk is not within spec
aRst_n : in std_logic; --asynchronous reset; must be reset when RefClk is not within spec
-- Video out
vid_pData : out std_logic_vector(23 downto 0);
vid_pVDE : out std_logic;
vid_pHSync : out std_logic;
vid_pVSync : out std_logic;
PixelClk : out std_logic; --pixel-clock recovered from the DVI interface
SerialClk : out std_logic; -- advanced use only; 5x PixelClk
aPixelClkLckd : out std_logic; -- advanced use only; PixelClk and SerialClk stable
-- Optional DDC port
DDC_SDA_I : in std_logic;
DDC_SDA_O : out std_logic;
DDC_SDA_T : out std_logic;
DDC_SCL_I : in std_logic;
DDC_SCL_O : out std_logic;
DDC_SCL_T : out std_logic;
pRst : in std_logic; -- synchronous reset; will restart locking procedure
pRst_n : in std_logic -- synchronous reset; will restart locking procedure
);
end dvi2rgb;
architecture Behavioral of dvi2rgb is
type dataIn_t is array (2 downto 0) of std_logic_vector(7 downto 0);
type eyeSize_t is array (2 downto 0) of std_logic_vector(kIDLY_TapWidth-1 downto 0);
signal aLocked, SerialClk_int, PixelClk_int, pLockLostRst: std_logic;
signal pRdy, pVld, pDE, pAlignErr, pC0, pC1 : std_logic_vector(2 downto 0);
signal pDataIn : dataIn_t;
signal pEyeSize : eyeSize_t;
signal aRst_int, pRst_int : std_logic;
signal pData : std_logic_vector(23 downto 0);
signal pVDE, pHSync, pVSync : std_logic;
-- set KEEP attribute so that synthesis does not optimize this register
-- in case we want to connect it to an inserted ILA debug core
attribute KEEP : string;
attribute KEEP of pEyeSize: signal is "TRUE";
begin
ResetActiveLow: if not kRstActiveHigh generate
aRst_int <= not aRst_n;
pRst_int <= not pRst_n;
end generate ResetActiveLow;
ResetActiveHigh: if kRstActiveHigh generate
aRst_int <= aRst;
pRst_int <= pRst;
end generate ResetActiveHigh;
-- Clocking infrastructure to obtain a usable fast serial clock and a slow parallel clock
TMDS_ClockingX: entity work.TMDS_Clocking
generic map (
kClkRange => kClkRange)
port map (
aRst => aRst_int,
RefClk => RefClk,
TMDS_Clk_p => TMDS_Clk_p,
TMDS_Clk_n => TMDS_Clk_n,
aLocked => aLocked,
PixelClk => PixelClk_int, -- slow parallel clock
SerialClk => SerialClk_int -- fast serial clock
);
-- We need a reset bridge to use the asynchronous aLocked signal to reset our circuitry
-- and decrease the chance of metastability. The signal pLockLostRst can be used as
-- asynchronous reset for any flip-flop in the PixelClk domain, since it will be de-asserted
-- synchronously.
LockLostReset: entity work.ResetBridge
generic map (
kPolarity => '1')
port map (
aRst => not aLocked,
OutClk => PixelClk_int,
oRst => pLockLostRst);
-- Three data channel decoders
DataDecoders: for iCh in 2 downto 0 generate
DecoderX: entity work.TMDS_Decoder
generic map (
kCtlTknCount => kMinTknCntForBlank, --how many subsequent control tokens make a valid blank detection (DVI spec)
kTimeoutMs => kBlankTimeoutMs, --what is the maximum time interval for a blank to be detected (DVI spec)
kRefClkFrqMHz => 200, --what is the RefClk frequency
kIDLY_TapValuePs => kIDLY_TapValuePs, --delay in ps per tap
kIDLY_TapWidth => kIDLY_TapWidth) --number of bits for IDELAYE2 tap counter
port map (
aRst => pLockLostRst,
PixelClk => PixelClk_int,
SerialClk => SerialClk_int,
RefClk => RefClk,
pRst => pRst_int,
sDataIn_p => TMDS_Data_p(iCh),
sDataIn_n => TMDS_Data_n(iCh),
pOtherChRdy(1 downto 0) => pRdy((iCh+1) mod 3) & pRdy((iCh+2) mod 3), -- tie channels together for channel de-skew
pOtherChVld(1 downto 0) => pVld((iCh+1) mod 3) & pVld((iCh+2) mod 3), -- tie channels together for channel de-skew
pAlignErr => pAlignErr(iCh),
pC0 => pC0(iCh),
pC1 => pC1(iCh),
pMeRdy => pRdy(iCh),
pMeVld => pVld(iCh),
pVde => pDE(iCh),
pDataIn(7 downto 0) => pDataIn(iCh),
pEyeSize => pEyeSize(iCh)
);
end generate DataDecoders;
-- RGB Output conform DVI 1.0
-- except that it sends blank pixel during blanking
-- for some reason video_data uses RBG packing
pData(23 downto 16) <= pDataIn(2); -- red is channel 2
pData(7 downto 0) <= pDataIn(1); -- green is channel 1
pData(15 downto 8) <= pDataIn(0); -- blue is channel 0
pHSync <= pC0(0); -- channel 0 carries control signals too
pVSync <= pC1(0); -- channel 0 carries control signals too
pVDE <= pDE(0); -- since channels are aligned, all of them are either active or blanking at once
-- Clock outputs
SerialClk <= SerialClk_int; -- fast 5x pixel clock for advanced use only
aPixelClkLckd <= aLocked;
----------------------------------------------------------------------------------
-- Re-buffer PixelClk with a BUFG so that it can reach the whole device, unlike
-- through a BUFR. Since BUFG introduces a delay on the clock path, pixel data is
-- re-registered here.
----------------------------------------------------------------------------------
GenerateBUFG: if kAddBUFG generate
ResyncToBUFG_X: entity work.ResyncToBUFG
port map (
-- Video in
piData => pData,
piVDE => pVDE,
piHSync => pHSync,
piVSync => pVSync,
PixelClkIn => PixelClk_int,
-- Video out
poData => vid_pData,
poVDE => vid_pVDE,
poHSync => vid_pHSync,
poVSync => vid_pVSync,
PixelClkOut => PixelClk
);
end generate GenerateBUFG;
DontGenerateBUFG: if not kAddBUFG generate
vid_pData <= pData;
vid_pVDE <= pVDE;
vid_pHSync <= pHSync;
vid_pVSync <= pVSync;
PixelClk <= PixelClk_int;
end generate DontGenerateBUFG;
----------------------------------------------------------------------------------
-- Optional DDC EEPROM Display Data Channel - Bi-directional (DDC2B)
-- The EDID will be loaded from the file specified below in kInitFileName.
----------------------------------------------------------------------------------
GenerateDDC: if kEmulateDDC generate
DDC_EEPROM: entity work.EEPROM_8b
generic map (
kSampleClkFreqInMHz => 200,
kSlaveAddress => "1010000",
kAddrBits => 7, -- 128 byte EDID 1.x data
kWritable => false,
kInitFileName => kEdidFileName) -- name of file containing init values
port map(
SampleClk => RefClk,
sRst => '0',
aSDA_I => DDC_SDA_I,
aSDA_O => DDC_SDA_O,
aSDA_T => DDC_SDA_T,
aSCL_I => DDC_SCL_I,
aSCL_O => DDC_SCL_O,
aSCL_T => DDC_SCL_T);
end generate GenerateDDC;
end Behavioral;
|
bsd-3-clause
|
schelleg/PYNQ
|
boards/ip/audio_codec_ctrl_v1.0/src/axi_lite_ipif.vhd
|
4
|
13991
|
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved. --
-- --
-- This file contains confidential and proprietary information --
-- of Xilinx, Inc. and is protected under U.S. and --
-- international copyright and other intellectual property --
-- laws. --
-- --
-- DISCLAIMER --
-- This disclaimer is not a license and does not grant any --
-- rights to the materials distributed herewith. Except as --
-- otherwise provided in a valid license issued to you by --
-- Xilinx, and to the maximum extent permitted by applicable --
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --
-- (2) Xilinx shall not be liable (whether in contract or tort, --
-- including negligence, or under any other theory of --
-- liability) for any loss or damage of any kind or nature --
-- related to, arising under or in connection with these --
-- materials, including for any direct, or any indirect, --
-- special, incidental, or consequential loss or damage --
-- (including loss of data, profits, goodwill, or any type of --
-- loss or damage suffered as a result of any action brought --
-- by a third party) even if such damage or loss was --
-- reasonably foreseeable or Xilinx had been advised of the --
-- possibility of the same. --
-- --
-- CRITICAL APPLICATIONS --
-- Xilinx products are not designed or intended to be fail- --
-- safe, or for use in any application requiring fail-safe --
-- performance, such as life-support or safety devices or --
-- systems, Class III medical devices, nuclear facilities, --
-- applications related to the deployment of airbags, or any --
-- other applications that could lead to death, personal --
-- injury, or severe property or environmental damage --
-- (individually and collectively, "Critical --
-- Applications"). Customer assumes the sole risk and --
-- liability of any use of Xilinx products in Critical --
-- Applications, subject only to applicable laws and --
-- regulations governing limitations on product liability. --
-- --
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --
-- PART OF THIS FILE AT ALL TIMES. --
-------------------------------------------------------------------
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_lite_ipif.vhd
-- Version: v1.01.a
-- Description: This is the top level design file for the axi_lite_ipif
-- function. It provides a standardized slave interface
-- between the IP and the AXI. This version supports
-- single read/write transfers only. It does not provide
-- address pipelining or simultaneous read and write
-- operations.
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of axi_lite_ipif.
--
-- --axi_lite_ipif.vhd
-- --slave_attachment.vhd
-- --address_decoder.vhd
-------------------------------------------------------------------------------
-- Author: BSB
--
-- History:
--
-- BSB 05/20/10 -- First version
-- ~~~~~~
-- - Created the first version v1.00.a
-- ^^^^^^
-- ~~~~~~
-- SK 06/09/10 -- v1.01.a
-- 1. updated to reduce the utilization
-- Closed CR #574507
-- 2. Optimized the state machine code
-- 3. Optimized the address decoder logic to generate the CE's with common logic
-- 4. Address GAP decoding logic is removed and timeout counter is made active
-- for all transactions.
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
use work.common_types.all;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_S_AXI_DATA_WIDTH -- AXI data bus width
-- C_S_AXI_ADDR_WIDTH -- AXI address bus width
-- C_S_AXI_MIN_SIZE -- Minimum address range of the IP
-- C_USE_WSTRB -- Use write strobs or not
-- C_DPHASE_TIMEOUT -- Data phase time out counter
-- C_ARD_ADDR_RANGE_ARRAY-- Base /High Address Pair for each Address Range
-- C_ARD_NUM_CE_ARRAY -- Desired number of chip enables for an address range
-- C_FAMILY -- Target FPGA family
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- S_AXI_ACLK -- AXI Clock
-- S_AXI_ARESETN -- AXI Reset
-- S_AXI_AWADDR -- AXI Write address
-- S_AXI_AWVALID -- Write address valid
-- S_AXI_AWREADY -- Write address ready
-- S_AXI_WDATA -- Write data
-- S_AXI_WSTRB -- Write strobes
-- S_AXI_WVALID -- Write valid
-- S_AXI_WREADY -- Write ready
-- S_AXI_BRESP -- Write response
-- S_AXI_BVALID -- Write response valid
-- S_AXI_BREADY -- Response ready
-- S_AXI_ARADDR -- Read address
-- S_AXI_ARVALID -- Read address valid
-- S_AXI_ARREADY -- Read address ready
-- S_AXI_RDATA -- Read data
-- S_AXI_RRESP -- Read response
-- S_AXI_RVALID -- Read valid
-- S_AXI_RREADY -- Read ready
-- Bus2IP_Clk -- Synchronization clock provided to User IP
-- Bus2IP_Reset -- Active high reset for use by the User IP
-- Bus2IP_Addr -- Desired address of read or write operation
-- Bus2IP_RNW -- Read or write indicator for the transaction
-- Bus2IP_BE -- Byte enables for the data bus
-- Bus2IP_CS -- Chip select for the transcations
-- Bus2IP_RdCE -- Chip enables for the read
-- Bus2IP_WrCE -- Chip enables for the write
-- Bus2IP_Data -- Write data bus to the User IP
-- IP2Bus_Data -- Input Read Data bus from the User IP
-- IP2Bus_WrAck -- Active high Write Data qualifier from the IP
-- IP2Bus_RdAck -- Active high Read Data qualifier from the IP
-- IP2Bus_Error -- Error signal from the IP
-------------------------------------------------------------------------------
entity axi_lite_ipif is
generic (
C_S_AXI_DATA_WIDTH : integer range 32 to 32 := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0):= X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer range 0 to 512 := 8;
C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE := -- not used
(
X"0000_0000_7000_0000", -- IP user0 base address
X"0000_0000_7000_00FF", -- IP user0 high address
X"0000_0000_7000_0100", -- IP user1 base address
X"0000_0000_7000_01FF" -- IP user1 high address
);
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := -- not used
(
4, -- User0 CE Number
12 -- User1 CE Number
);
C_FAMILY : string := "virtex6"
);
port (
--System signals
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector
(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector
(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector
((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector
(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector
(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- Controls to the IP/IPIF modules
Bus2IP_Clk : out std_logic;
Bus2IP_Resetn : out std_logic;
Bus2IP_Addr : out std_logic_vector
((C_S_AXI_ADDR_WIDTH-1) downto 0);
Bus2IP_RNW : out std_logic;
Bus2IP_BE : out std_logic_vector
(((C_S_AXI_DATA_WIDTH/8)-1) downto 0);
Bus2IP_CS : out std_logic_vector
(((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1) downto 0);
Bus2IP_RdCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY)-1) downto 0);
Bus2IP_WrCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY)-1) downto 0);
Bus2IP_Data : out std_logic_vector
((C_S_AXI_DATA_WIDTH-1) downto 0);
IP2Bus_Data : in std_logic_vector
((C_S_AXI_DATA_WIDTH-1) downto 0);
IP2Bus_WrAck : in std_logic;
IP2Bus_RdAck : in std_logic;
IP2Bus_Error : in std_logic
);
end axi_lite_ipif;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture imp of axi_lite_ipif is
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Slave Attachment
-------------------------------------------------------------------------------
I_SLAVE_ATTACHMENT: entity work.slave_attachment
generic map(
C_ARD_ADDR_RANGE_ARRAY => C_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY,
C_IPIF_ABUS_WIDTH => C_S_AXI_ADDR_WIDTH,
C_IPIF_DBUS_WIDTH => C_S_AXI_DATA_WIDTH,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_FAMILY => C_FAMILY
)
port map(
-- AXI signals
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_RREADY => S_AXI_RREADY,
-- IPIC signals
Bus2IP_Clk => Bus2IP_Clk,
Bus2IP_Resetn => Bus2IP_Resetn,
Bus2IP_Addr => Bus2IP_Addr,
Bus2IP_RNW => Bus2IP_RNW,
Bus2IP_BE => Bus2IP_BE,
Bus2IP_CS => Bus2IP_CS,
Bus2IP_RdCE => Bus2IP_RdCE,
Bus2IP_WrCE => Bus2IP_WrCE,
Bus2IP_Data => Bus2IP_Data,
IP2Bus_Data => IP2Bus_Data,
IP2Bus_WrAck => IP2Bus_WrAck,
IP2Bus_RdAck => IP2Bus_RdAck,
IP2Bus_Error => IP2Bus_Error
);
end imp;
|
bsd-3-clause
|
skordal/potato
|
testbenches/tb_soc_intercon.vhd
|
1
|
2933
|
-- The Potato Processor - A simple processor for FPGAs
-- (c) Kristian Klomsten Skordal 2016 <[email protected]>
-- Report bugs and issues on <https://github.com/skordal/potato/issues>
library ieee;
use ieee.std_logic_1164.all;
entity tb_soc_intercon is
end entity tb_soc_intercon;
architecture testbench of tb_soc_intercon is
-- Clock signal:
signal clk : std_logic := '0';
constant clk_period : time := 10 ns;
-- Reset signal:
signal reset : std_logic := '1';
-- IRQ signal:
signal error_irq : std_logic;
-- Wishbone interface:
signal wb_adr_in : std_logic_vector(11 downto 0) := (others => '0');
signal wb_dat_in : std_logic_vector(31 downto 0) := (others => '0');
signal wb_dat_out : std_logic_vector(31 downto 0);
signal wb_cyc_in : std_logic := '0';
signal wb_stb_in : std_logic := '0';
signal wb_we_in : std_logic := '0';
signal wb_ack_out : std_logic;
-- Bus error interface:
signal err_adr_in : std_logic_vector(31 downto 0) := (others => '0');
signal err_dat_in : std_logic_vector(31 downto 0) := (others => '0');
signal err_sel_in : std_logic_vector( 3 downto 0) := (others => '0');
signal err_cyc_in : std_logic := '0';
signal err_stb_in : std_logic := '0';
signal err_we_in : std_logic := '0';
signal err_ack_out : std_logic;
begin
uut: entity work.pp_soc_intercon
port map(
clk => clk,
reset => reset,
error_irq => error_irq,
wb_adr_in => wb_adr_in,
wb_dat_in => wb_dat_in,
wb_dat_out => wb_dat_out,
wb_cyc_in => wb_cyc_in,
wb_stb_in => wb_stb_in,
wb_we_in => wb_we_in,
wb_ack_out => wb_ack_out,
err_adr_in => err_adr_in,
err_dat_in => err_dat_in,
err_sel_in => err_sel_in,
err_cyc_in => err_cyc_in,
err_stb_in => err_stb_in,
err_we_in => err_we_in,
err_ack_out => err_ack_out
);
clock: process
begin
clk <= '1';
wait for clk_period / 2;
clk <= '0';
wait for clk_period / 2;
end process clock;
stimulus: process
begin
wait for clk_period * 2;
reset <= '0';
wait for clk_period;
-- Do an invalid bus access to see what happens:
err_cyc_in <= '1';
err_stb_in <= '1';
err_adr_in <= x"deadbeef";
err_dat_in <= x"f000000d";
err_we_in <= '1';
wait until err_ack_out = '1';
wait for clk_period;
assert error_irq = '1';
err_cyc_in <= '0';
err_stb_in <= '0';
wait for clk_period;
-- Check the address:
wb_adr_in <= x"00c";
wb_we_in <= '0';
wb_stb_in <= '1';
wb_cyc_in <= '1';
wait until wb_ack_out = '1';
wait for clk_period;
assert wb_dat_out = x"deadbeef";
wb_stb_in <= '0';
wb_cyc_in <= '0';
wait for clk_period;
-- Reset the interrupt:
wb_adr_in <= x"000";
wb_dat_in <= x"00000001";
wb_we_in <= '1';
wb_cyc_in <= '1';
wb_stb_in <= '1';
wait until wb_ack_out = '1';
wait for clk_period;
assert error_irq = '0';
wb_stb_in <= '0';
wb_cyc_in <= '0';
wait;
end process stimulus;
end architecture testbench;
|
bsd-3-clause
|
skordal/potato
|
testbenches/tb_processor.vhd
|
1
|
8492
|
-- The Potato Processor - A simple processor for FPGAs
-- (c) Kristian Klomsten Skordal 2014-2021 <[email protected]>
-- Report bugs and issues on <https://github.com/skordal/potato/issues>
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.pp_constants.all;
use work.pp_types.all;
entity tb_processor is
generic(
IMEM_SIZE : natural := 4096; --! Size of the instruction memory in bytes.
DMEM_SIZE : natural := 4096; --! Size of the data memory in bytes.
RESET_ADDRESS : std_logic_vector := x"00000100"; --! Processor reset address
IMEM_START_ADDR : std_logic_vector := x"00000100"; --! Instruction memory start address
IMEM_FILENAME : string := "imem_testfile.hex"; --! File containing the contents of instruction memory.
DMEM_FILENAME : string := "dmem_testfile.hex" --! File containing the contents of data memory.
);
end entity tb_processor;
architecture testbench of tb_processor is
-- Clock signal:
signal clk : std_logic := '0';
constant clk_period : time := 10 ns;
-- Common inputs:
signal reset : std_logic := '1';
-- Instruction memory interface:
signal imem_address : std_logic_vector(31 downto 0);
signal imem_data_in : std_logic_vector(31 downto 0) := (others => '0');
signal imem_req : std_logic;
signal imem_ack : std_logic := '0';
-- Data memory interface:
signal dmem_address : std_logic_vector(31 downto 0);
signal dmem_data_in : std_logic_vector(31 downto 0) := (others => '0');
signal dmem_data_out : std_logic_vector(31 downto 0);
signal dmem_data_size : std_logic_vector( 1 downto 0);
signal dmem_read_req, dmem_write_req : std_logic;
signal dmem_read_ack, dmem_write_ack : std_logic := '1';
-- Test context:
signal test_context_out : test_context;
-- External interrupt input:
signal irq : std_logic_vector(7 downto 0) := (others => '0');
-- Simulation initialized:
signal imem_initialized, dmem_initialized, initialized : boolean := false;
-- Memory array type:
type memory_array is array(natural range <>) of std_logic_vector(7 downto 0);
constant IMEM_BASE : natural := 0;
constant IMEM_END : natural := IMEM_BASE + IMEM_SIZE - 1;
constant DMEM_BASE : natural := IMEM_END + 1;
constant DMEM_END : natural := IMEM_END + DMEM_SIZE;
-- Memories:
signal imem_memory : memory_array(IMEM_BASE to IMEM_END);
signal dmem_memory : memory_array(DMEM_BASE to DMEM_END);
signal simulation_finished : boolean := false;
begin
uut: entity work.pp_core
generic map(
RESET_ADDRESS => RESET_ADDRESS
) port map(
clk => clk,
reset => reset,
imem_address => imem_address,
imem_data_in => imem_data_in,
imem_req => imem_req,
imem_ack => imem_ack,
dmem_address => dmem_address,
dmem_data_in => dmem_data_in,
dmem_data_out => dmem_data_out,
dmem_data_size => dmem_data_size,
dmem_read_req => dmem_read_req,
dmem_read_ack => dmem_read_ack,
dmem_write_req => dmem_write_req,
dmem_write_ack => dmem_write_ack,
test_context_out => test_context_out,
irq => irq
);
clock: process
begin
clk <= '0';
wait for clk_period / 2;
clk <= '1';
wait for clk_period / 2;
if simulation_finished then
wait;
end if;
end process clock;
--! Initializes the instruction memory from file.
imem_init: process
file imem_file : text open READ_MODE is IMEM_FILENAME;
variable input_line : line;
variable input_index : natural;
variable input_value : std_logic_vector(31 downto 0);
begin
for i in to_integer(unsigned(IMEM_START_ADDR)) / 4 to IMEM_END / 4 loop
--for i in IMEM_BASE / 4 to IMEM_END / 4 loop
if not endfile(imem_file) then
readline(imem_file, input_line);
hread(input_line, input_value);
imem_memory(i * 4 + 0) <= input_value( 7 downto 0);
imem_memory(i * 4 + 1) <= input_value(15 downto 8);
imem_memory(i * 4 + 2) <= input_value(23 downto 16);
imem_memory(i * 4 + 3) <= input_value(31 downto 24);
else
imem_memory(i * 4 + 0) <= RISCV_NOP( 7 downto 0);
imem_memory(i * 4 + 1) <= RISCV_NOP(15 downto 8);
imem_memory(i * 4 + 2) <= RISCV_NOP(23 downto 16);
imem_memory(i * 4 + 3) <= RISCV_NOP(31 downto 24);
end if;
end loop;
imem_initialized <= true;
wait;
end process imem_init;
--! Initializes and handles writes to the data memory.
dmem_init_and_write: process(clk)
file dmem_file : text open READ_MODE is DMEM_FILENAME;
variable input_line : line;
variable input_index : natural;
variable input_value : std_logic_vector(31 downto 0);
begin
if not dmem_initialized then
for i in DMEM_BASE / 4 to DMEM_END / 4 loop
if not endfile(dmem_file) then
readline(dmem_file, input_line);
hread(input_line, input_value);
-- Read from a big-endian file:
dmem_memory(i * 4 + 3) <= input_value( 7 downto 0);
dmem_memory(i * 4 + 2) <= input_value(15 downto 8);
dmem_memory(i * 4 + 1) <= input_value(23 downto 16);
dmem_memory(i * 4 + 0) <= input_value(31 downto 24);
else
dmem_memory(i * 4 + 0) <= (others => '0');
dmem_memory(i * 4 + 1) <= (others => '0');
dmem_memory(i * 4 + 2) <= (others => '0');
dmem_memory(i * 4 + 3) <= (others => '0');
end if;
end loop;
dmem_initialized <= true;
end if;
if rising_edge(clk) then
if dmem_write_ack = '1' then
dmem_write_ack <= '0';
elsif dmem_write_req = '1' then
case dmem_data_size is
when b"00" => -- 32 bits
dmem_memory(to_integer(unsigned(dmem_address)) + 0) <= dmem_data_out(7 downto 0);
dmem_memory(to_integer(unsigned(dmem_address)) + 1) <= dmem_data_out(15 downto 8);
dmem_memory(to_integer(unsigned(dmem_address)) + 2) <= dmem_data_out(23 downto 16);
dmem_memory(to_integer(unsigned(dmem_address)) + 3) <= dmem_data_out(31 downto 24);
when b"01" => -- 8 bits
dmem_memory(to_integer(unsigned(dmem_address))) <= dmem_data_out(7 downto 0);
when b"10" => -- 16 bits
dmem_memory(to_integer(unsigned(dmem_address)) + 0) <= dmem_data_out( 7 downto 0);
dmem_memory(to_integer(unsigned(dmem_address)) + 1) <= dmem_data_out(15 downto 8);
when others =>
end case;
dmem_write_ack <= '1';
end if;
end if;
end process dmem_init_and_write;
initialized <= imem_initialized and dmem_initialized;
--! Instruction memory read process.
imem_read: process(clk)
begin
if rising_edge(clk) then
if reset = '1' then
imem_ack <= '0';
else
if to_integer(unsigned(imem_address)) > IMEM_END then
imem_data_in <= (others => 'X');
else
imem_data_in <= imem_memory(to_integer(unsigned(imem_address)) + 3)
& imem_memory(to_integer(unsigned(imem_address)) + 2)
& imem_memory(to_integer(unsigned(imem_address)) + 1)
& imem_memory(to_integer(unsigned(imem_address)) + 0);
end if;
imem_ack <= '1';
end if;
end if;
end process imem_read;
--! Data memory read process.
dmem_read: process(clk)
begin
if rising_edge(clk) then
if dmem_read_ack = '1' then
dmem_read_ack <= '0';
elsif dmem_read_req = '1' then
case dmem_data_size is
when b"00" => -- 32 bits
dmem_data_in <= dmem_memory(to_integer(unsigned(dmem_address) + 3))
& dmem_memory(to_integer(unsigned(dmem_address) + 2))
& dmem_memory(to_integer(unsigned(dmem_address) + 1))
& dmem_memory(to_integer(unsigned(dmem_address) + 0));
when b"10" => -- 16 bits
dmem_data_in(15 downto 8) <= dmem_memory(to_integer(unsigned(dmem_address)) + 1);
dmem_data_in( 7 downto 0) <= dmem_memory(to_integer(unsigned(dmem_address)) + 0);
when b"01" => -- 8 bits
dmem_data_in(7 downto 0) <= dmem_memory(to_integer(unsigned(dmem_address)));
when others =>
end case;
dmem_read_ack <= '1';
end if;
end if;
end process dmem_read;
stimulus: process
begin
wait until initialized = true;
report "Testbench initialized, starting behavioural simulation..." severity NOTE;
wait for clk_period * 2;
-- Release the processor from reset:
reset <= '0';
wait for clk_period;
wait until test_context_out.state = TEST_PASSED or test_context_out.state = TEST_FAILED;
if test_context_out.state = TEST_PASSED then
report "Success!" severity NOTE;
else
report "Failure in test " & integer'image(to_integer(unsigned(test_context_out.number))) & "!" severity NOTE;
end if;
simulation_finished <= true;
wait;
end process stimulus;
end architecture testbench;
|
bsd-3-clause
|
skordal/potato
|
src/pp_wb_adapter.vhd
|
1
|
3514
|
-- The Potato Processor - A simple processor for FPGAs
-- (c) Kristian Klomsten Skordal 2014 - 2015 <[email protected]>
-- Report bugs and issues on <https://github.com/skordal/potato/issues>
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.pp_types.all;
use work.pp_utilities.all;
--! @brief Wishbone adapter, for connecting the processor to a Wishbone bus when not using caches.
entity pp_wb_adapter is
port(
clk : in std_logic;
reset : in std_logic;
-- Processor data memory signals:
signal mem_address : in std_logic_vector(31 downto 0);
signal mem_data_in : in std_logic_vector(31 downto 0); -- Data in from the bus
signal mem_data_out : out std_logic_vector(31 downto 0); -- Data out to the bus
signal mem_data_size : in std_logic_vector( 1 downto 0);
signal mem_read_req : in std_logic;
signal mem_read_ack : out std_logic;
signal mem_write_req : in std_logic;
signal mem_write_ack : out std_logic;
-- Wishbone interface:
wb_inputs : in wishbone_master_inputs;
wb_outputs : out wishbone_master_outputs
);
end entity pp_wb_adapter;
architecture behaviour of pp_wb_adapter is
type states is (IDLE, READ_WAIT_ACK, WRITE_WAIT_ACK);
signal state : states;
signal mem_r_ack : std_logic;
function get_data_shift(size : in std_logic_vector(1 downto 0); address : in std_logic_vector)
return natural is
begin
case size is
when b"01" =>
case address(1 downto 0) is
when b"00" =>
return 0;
when b"01" =>
return 8;
when b"10" =>
return 16;
when b"11" =>
return 24;
when others =>
return 0;
end case;
when b"10" =>
if address(1) = '0' then
return 0;
else
return 16;
end if;
when others =>
return 0;
end case;
end function get_data_shift;
begin
mem_write_ack <= '1' when state = WRITE_WAIT_ACK and wb_inputs.ack = '1' else '0';
mem_read_ack <= mem_r_ack;
wishbone: process(clk)
begin
if rising_edge(clk) then
if reset = '1' then
state <= IDLE;
wb_outputs.cyc <= '0';
wb_outputs.stb <= '0';
mem_r_ack <= '0';
else
case state is
when IDLE =>
mem_r_ack <= '0';
-- Prioritize requests from the data memory:
if mem_write_req = '1' then
wb_outputs.adr <= mem_address;
wb_outputs.dat <= std_logic_vector(shift_left(unsigned(mem_data_in),
get_data_shift(mem_data_size, mem_address)));
wb_outputs.sel <= wb_get_data_sel(mem_data_size, mem_address);
wb_outputs.cyc <= '1';
wb_outputs.stb <= '1';
wb_outputs.we <= '1';
state <= WRITE_WAIT_ACK;
elsif mem_read_req = '1' then
wb_outputs.adr <= mem_address;
wb_outputs.sel <= wb_get_data_sel(mem_data_size, mem_address);
wb_outputs.cyc <= '1';
wb_outputs.stb <= '1';
wb_outputs.we <= '0';
state <= READ_WAIT_ACK;
end if;
when READ_WAIT_ACK =>
if wb_inputs.ack = '1' then
mem_data_out <= std_logic_vector(shift_right(unsigned(wb_inputs.dat),
get_data_shift(mem_data_size, mem_address)));
wb_outputs.cyc <= '0';
wb_outputs.stb <= '0';
mem_r_ack <= '1';
state <= IDLE;
end if;
when WRITE_WAIT_ACK =>
if wb_inputs.ack = '1' then
wb_outputs.cyc <= '0';
wb_outputs.stb <= '0';
wb_outputs.we <= '0';
state <= IDLE;
end if;
end case;
end if;
end if;
end process wishbone;
end architecture behaviour;
|
bsd-3-clause
|
skordal/potato
|
src/pp_memory.vhd
|
1
|
4770
|
-- The Potato Processor - A simple processor for FPGAs
-- (c) Kristian Klomsten Skordal 2014 - 2015 <[email protected]>
-- Report bugs and issues on <https://github.com/skordal/potato/issues>
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.pp_types.all;
use work.pp_csr.all;
use work.pp_utilities.all;
entity pp_memory is
port(
clk : in std_logic;
reset : in std_logic;
stall : in std_logic;
-- Data memory inputs:
dmem_read_ack : in std_logic;
dmem_write_ack : in std_logic;
dmem_data_in : in std_logic_vector(31 downto 0);
-- Current PC value:
pc : in std_logic_vector(31 downto 0);
-- Destination register signals:
rd_write_in : in std_logic;
rd_write_out : out std_logic;
rd_data_in : in std_logic_vector(31 downto 0);
rd_data_out : out std_logic_vector(31 downto 0);
rd_addr_in : in register_address;
rd_addr_out : out register_address;
-- Control signals:
branch : in branch_type;
mem_op_in : in memory_operation_type;
mem_size_in : in memory_operation_size;
mem_op_out : out memory_operation_type;
-- Whether the instruction should be counted:
count_instr_in : in std_logic;
count_instr_out : out std_logic;
-- Exception signals:
exception_in : in std_logic;
exception_out : out std_logic;
exception_context_in : in csr_exception_context;
exception_context_out : out csr_exception_context;
-- CSR signals:
csr_addr_in : in csr_address;
csr_addr_out : out csr_address;
csr_write_in : in csr_write_mode;
csr_write_out : out csr_write_mode;
csr_data_in : in std_logic_vector(31 downto 0);
csr_data_out : out std_logic_vector(31 downto 0)
);
end entity pp_memory;
architecture behaviour of pp_memory is
signal mem_op : memory_operation_type;
signal mem_size : memory_operation_size;
signal rd_data : std_logic_vector(31 downto 0);
begin
mem_op_out <= mem_op;
pipeline_register: process(clk)
begin
if rising_edge(clk) then
if reset = '1' then
rd_write_out <= '0';
csr_write_out <= CSR_WRITE_NONE;
count_instr_out <= '0';
mem_op <= MEMOP_TYPE_NONE;
elsif stall = '0' then
mem_size <= mem_size_in;
rd_data <= rd_data_in;
rd_addr_out <= rd_addr_in;
if exception_in = '1' then
mem_op <= MEMOP_TYPE_NONE;
rd_write_out <= '0';
csr_write_out <= CSR_WRITE_REPLACE;
csr_addr_out <= CSR_MEPC;
csr_data_out <= pc;
count_instr_out <= '0';
else
mem_op <= mem_op_in;
rd_write_out <= rd_write_in;
csr_write_out <= csr_write_in;
csr_addr_out <= csr_addr_in;
csr_data_out <= csr_data_in;
count_instr_out <= count_instr_in;
end if;
end if;
end if;
end process pipeline_register;
update_exception_context: process(clk)
begin
if rising_edge(clk) then
if reset = '1' then
exception_out <= '0';
else
exception_out <= exception_in or to_std_logic(branch = BRANCH_SRET);
if exception_in = '1' then
exception_context_out.ie <= '0';
exception_context_out.ie1 <= exception_context_in.ie;
exception_context_out.cause <= exception_context_in.cause;
exception_context_out.badaddr <= exception_context_in.badaddr;
elsif branch = BRANCH_SRET then
exception_context_out.ie <= exception_context_in.ie1;
exception_context_out.ie1 <= exception_context_in.ie;
exception_context_out.cause <= CSR_CAUSE_NONE;
exception_context_out.badaddr <= (others => '0');
else
exception_context_out.ie <= exception_context_in.ie;
exception_context_out.ie1 <= exception_context_in.ie1;
exception_context_out.cause <= CSR_CAUSE_NONE;
exception_context_out.badaddr <= (others => '0');
end if;
end if;
end if;
end process update_exception_context;
rd_data_mux: process(rd_data, dmem_data_in, mem_op, mem_size)
begin
if mem_op = MEMOP_TYPE_LOAD or mem_op = MEMOP_TYPE_LOAD_UNSIGNED then
case mem_size is
when MEMOP_SIZE_BYTE =>
if mem_op = MEMOP_TYPE_LOAD_UNSIGNED then
rd_data_out <= std_logic_vector(resize(unsigned(dmem_data_in(7 downto 0)), rd_data_out'length));
else
rd_data_out <= std_logic_vector(resize(signed(dmem_data_in(7 downto 0)), rd_data_out'length));
end if;
when MEMOP_SIZE_HALFWORD =>
if mem_op = MEMOP_TYPE_LOAD_UNSIGNED then
rd_data_out <= std_logic_vector(resize(unsigned(dmem_data_in(15 downto 0)), rd_data_out'length));
else
rd_data_out <= std_logic_vector(resize(signed(dmem_data_in(15 downto 0)), rd_data_out'length));
end if;
when MEMOP_SIZE_WORD =>
rd_data_out <= dmem_data_in;
end case;
else
rd_data_out <= rd_data;
end if;
end process rd_data_mux;
end architecture behaviour;
|
bsd-3-clause
|
skordal/potato
|
src/pp_potato.vhd
|
1
|
5309
|
-- The Potato Processor - A simple processor for FPGAs
-- (c) Kristian Klomsten Skordal 2014 - 2015 <[email protected]>
-- Report bugs and issues on <https://github.com/skordal/potato/issues>
library ieee;
use ieee.std_logic_1164.all;
use work.pp_types.all;
use work.pp_utilities.all;
--! @brief The Potato Processor.
--! This file provides a Wishbone-compatible interface to the Potato processor.
entity pp_potato is
generic(
PROCESSOR_ID : std_logic_vector(31 downto 0) := x"00000000"; --! Processor ID.
RESET_ADDRESS : std_logic_vector(31 downto 0) := x"00000000"; --! Address of the first instruction to execute.
MTIME_DIVIDER : positive := 5; --! Divider for the clock driving the MTIME counter.
ICACHE_ENABLE : boolean := true; --! Whether to enable the instruction cache.
ICACHE_LINE_SIZE : natural := 4; --! Number of words per instruction cache line.
ICACHE_NUM_LINES : natural := 128 --! Number of cache lines in the instruction cache.
);
port(
clk : in std_logic;
reset : in std_logic;
-- Interrupts:
irq : in std_logic_vector(7 downto 0);
-- Test interface:
test_context_out : out test_context;
-- Wishbone interface:
wb_adr_out : out std_logic_vector(31 downto 0);
wb_sel_out : out std_logic_vector( 3 downto 0);
wb_cyc_out : out std_logic;
wb_stb_out : out std_logic;
wb_we_out : out std_logic;
wb_dat_out : out std_logic_vector(31 downto 0);
wb_dat_in : in std_logic_vector(31 downto 0);
wb_ack_in : in std_logic
);
end entity pp_potato;
architecture behaviour of pp_potato is
-- Instruction memory signals:
signal imem_address : std_logic_vector(31 downto 0);
signal imem_data : std_logic_vector(31 downto 0);
signal imem_req, imem_ack : std_logic;
-- Data memory signals:
signal dmem_address : std_logic_vector(31 downto 0);
signal dmem_data_in : std_logic_vector(31 downto 0);
signal dmem_data_out : std_logic_vector(31 downto 0);
signal dmem_data_size : std_logic_vector( 1 downto 0);
signal dmem_read_req : std_logic;
signal dmem_read_ack : std_logic;
signal dmem_write_req : std_logic;
signal dmem_write_ack : std_logic;
-- Wishbone signals:
signal icache_inputs, dmem_if_inputs : wishbone_master_inputs;
signal icache_outputs, dmem_if_outputs : wishbone_master_outputs;
-- Arbiter signals:
signal m1_inputs, m2_inputs : wishbone_master_inputs;
signal m1_outputs, m2_outputs : wishbone_master_outputs;
begin
processor: entity work.pp_core
generic map(
PROCESSOR_ID => PROCESSOR_ID,
RESET_ADDRESS => RESET_ADDRESS
) port map(
clk => clk,
reset => reset,
imem_address => imem_address,
imem_data_in => imem_data,
imem_req => imem_req,
imem_ack => imem_ack,
dmem_address => dmem_address,
dmem_data_in => dmem_data_in,
dmem_data_out => dmem_data_out,
dmem_data_size => dmem_data_size,
dmem_read_req => dmem_read_req,
dmem_read_ack => dmem_read_ack,
dmem_write_req => dmem_write_req,
dmem_write_ack => dmem_write_ack,
test_context_out => test_context_out,
irq => irq
);
icache_enabled: if ICACHE_ENABLE
generate
icache: entity work.pp_icache
generic map(
LINE_SIZE => ICACHE_LINE_SIZE,
NUM_LINES => ICACHE_NUM_LINES
) port map(
clk => clk,
reset => reset,
mem_address_in => imem_address,
mem_data_out => imem_data,
mem_read_req => imem_req,
mem_read_ack => imem_ack,
wb_inputs => icache_inputs,
wb_outputs => icache_outputs
);
icache_inputs <= m1_inputs;
m1_outputs <= icache_outputs;
dmem_if_inputs <= m2_inputs;
m2_outputs <= dmem_if_outputs;
end generate icache_enabled;
icache_disabled: if not ICACHE_ENABLE
generate
imem_if: entity work.pp_wb_adapter
port map(
clk => clk,
reset => reset,
mem_address => imem_address,
mem_data_in => (others => '0'),
mem_data_out => imem_data,
mem_data_size => (others => '0'),
mem_read_req => imem_req,
mem_read_ack => imem_ack,
mem_write_req => '0',
mem_write_ack => open,
wb_inputs => icache_inputs,
wb_outputs => icache_outputs
);
dmem_if_inputs <= m1_inputs;
m1_outputs <= dmem_if_outputs;
icache_inputs <= m2_inputs;
m2_outputs <= icache_outputs;
end generate icache_disabled;
dmem_if: entity work.pp_wb_adapter
port map(
clk => clk,
reset => reset,
mem_address => dmem_address,
mem_data_in => dmem_data_out,
mem_data_out => dmem_data_in,
mem_data_size => dmem_data_size,
mem_read_req => dmem_read_req,
mem_read_ack => dmem_read_ack,
mem_write_req => dmem_write_req,
mem_write_ack => dmem_write_ack,
wb_inputs => dmem_if_inputs,
wb_outputs => dmem_if_outputs
);
arbiter: entity work.pp_wb_arbiter
port map(
clk => clk,
reset => reset,
m1_inputs => m1_inputs,
m1_outputs => m1_outputs,
m2_inputs => m2_inputs,
m2_outputs => m2_outputs,
wb_adr_out => wb_adr_out,
wb_sel_out => wb_sel_out,
wb_cyc_out => wb_cyc_out,
wb_stb_out => wb_stb_out,
wb_we_out => wb_we_out,
wb_dat_out => wb_dat_out,
wb_dat_in => wb_dat_in,
wb_ack_in => wb_ack_in
);
end architecture behaviour;
|
bsd-3-clause
|
seiken-chuouniv/ecorun
|
ecorun_fi_hardware/fi_timer/FiTimer/TestPulseTimer.vhd
|
1
|
2585
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 03:39:23 08/26/2016
-- Design Name:
-- Module Name: C:/Users/Yoshio/git/ecorun/ecorun_fi_hardware/fi_timer/FiTimer/TestPulseTimer.vhd
-- Project Name: FiTimer
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: PulseTimer
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY TestPulseTimer IS
END TestPulseTimer;
ARCHITECTURE behavior OF TestPulseTimer IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT PulseTimer
PORT(
clk : IN std_logic;
enable : IN std_logic;
start : IN std_logic;
match : IN std_logic_vector(7 downto 0);
pulse : OUT std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal enable : std_logic := '0';
signal start : std_logic := '0';
signal match : std_logic_vector(7 downto 0) := (others => '0');
--Outputs
signal pulse : std_logic;
-- Clock period definitions
constant clk_period : time := 100 us;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: PulseTimer PORT MAP (
clk => clk,
enable => enable,
start => start,
match => match,
pulse => pulse
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clk_period*10;
-- insert stimulus here
enable <= '1';
match <= "00000100";
wait for clk_period;
start <= '1';
wait for clk_period;
start <= '0';
wait for 1 ms;
wait;
end process;
END;
|
bsd-3-clause
|
sonologic/gmzpu
|
vhdl/ZetaIO/timer/test/timers_tb.vhdl
|
1
|
9048
|
-----------------------------------------------------------------------------
---- ----
---- gmzpu timer component testbench ----
---- ----
---- http://github.com/sonologic/gmzpu ----
---- ----
---- Description: ----
---- This is the testbench for the gmZPU core ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Salvador E. Tropea, salvador inti.gob.ar ----
---- - "Koen Martens" <gmc sonologic.nl> ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ----
---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ----
---- Copyright (c) 2014 Koen Martens ----
---- ----
---- Distributed under the BSD license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: zwishbone_TB ----
---- File name: gmzpu_tb.vhdl ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: zpu ----
---- Dependencies: IEEE.std_logic_1164 ----
---- IEEE.numeric_std ----
---- Target FPGA: n/a ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Modelsim ----
---- Simulation tools: Modelsim ----
---- Text editor: vim ----
---- ----
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library gmzpu;
use gmzpu.timer;
entity timers_TB is
end entity timers_TB;
architecture Behave of timers_TB is
constant CLK_FREQ : positive:=50; -- 50 MHz clock
constant CLK_S_PER : time:=1 us/(2.0*real(CLK_FREQ)); -- Clock semi period
constant ADR_WIDTH : natural:=6;
constant DATA_WIDTH : natural:=32;
component timers is
generic (
DATA_WIDTH : natural:=32;
ADR_WIDTH : natural:=4;
N_TIMERS : natural:=4
);
port (
-- wishbone bus
rst_i : in std_logic;
clk_i : in std_logic;
wb_dat_o : out unsigned(DATA_WIDTH-1 downto 0);
wb_dat_i : in unsigned(DATA_WIDTH-1 downto 0);
wb_tgd_o : out unsigned(DATA_WIDTH-1 downto 0);
wb_tgd_i : in unsigned(DATA_WIDTH-1 downto 0);
wb_ack_o : out std_logic;
wb_adr_i : in unsigned(ADR_WIDTH-1 downto 0);
wb_cyc_i : in std_logic;
wb_stall_o : out std_logic;
wb_err_o : out std_logic;
wb_lock_i : in std_logic;
wb_rty_o : out std_logic;
wb_sel_i : in std_logic_vector(DATA_WIDTH-1 downto 0);
wb_stb_i : in std_logic;
wb_tga_i : in unsigned(ADR_WIDTH-1 downto 0);
wb_tgc_i : in unsigned(DATA_WIDTH-1 downto 0); -- size correct?
wb_we_i : in std_logic;
-- non wishbone
irq_o : out std_logic
);
end component timers;
type sample is record
-- inputs
rst_i : std_logic;
wb_we_i : std_logic;
wb_cyc_i : std_logic;
wb_stb_i : std_logic;
wb_adr_i : unsigned(ADR_WIDTH-1 downto 0);
wb_dat_i : unsigned(DATA_WIDTH-1 downto 0);
-- outputs
wb_dat_o : unsigned(DATA_WIDTH-1 downto 0);
irq_o : std_logic;
wb_ack_o : std_logic;
end record;
type sample_array is array(natural range <>) of sample;
constant test_data : sample_array :=
(
-- rst we cyc stb adr_i dat_i dat_o irq_o, ack_o
('1','0','0','0',"000000", X"00000000", X"00000000", '0', 'L'),
('1','0','0','0',"000000", X"00000000", X"00000000", '0', 'L'),
('0','0','0','0',"000000", X"00000000", X"00000000", '0', 'L'),
-- write
('0','1','1','1',"000001", X"11111111", X"00000000", '0', '0'),
('0','0','1','0',"000000", X"00000000", X"00000000", '0', '1'),
('0','0','0','0',"000000", X"00000000", X"00000000", '0', 'L'),
('0','1','1','1',"000101", X"44444444", X"00000000", '0', '0'),
('0','0','1','0',"000000", X"00000000", X"00000000", '0', '1'),
('0','0','0','0',"000000", X"00000000", X"00000000", '0', 'L'),
-- read
('0','0','1','1',"000101", X"00000000", X"00000000", '0', '0'),
('0','0','1','0',"000101", X"00000000", X"44444444", '0', '1'),
('0','0','0','0',"000000", X"00000000", X"00000000", '0', 'L'),
-- terminate
('0','0','0','0',"000000", X"00000000", X"00000000", '0', 'L')
);
signal clk : std_logic;
-- inputs
signal rst_i : std_logic;
signal wb_we_i : std_logic;
signal wb_cyc_i : std_logic;
signal wb_stb_i : std_logic;
signal wb_adr_i : unsigned(ADR_WIDTH-1 downto 0);
signal wb_dat_i : unsigned(DATA_WIDTH-1 downto 0);
-- outputs
signal wb_dat_o : unsigned(DATA_WIDTH-1 downto 0);
signal irq_o : std_logic;
signal wb_ack_o : std_logic;
--
signal wb_tgd_o : unsigned(DATA_WIDTH-1 downto 0);
signal wb_stall_o : std_logic;
signal wb_err_o : std_logic;
signal wb_rty_o : std_logic;
begin
dut : timers
generic map(ADR_WIDTH => ADR_WIDTH, DATA_WIDTH => DATA_WIDTH)
port map(clk_i => clk, rst_i => rst_i,
wb_dat_o => wb_dat_o, wb_dat_i => wb_dat_i,
wb_tgd_i => (others => '0'), wb_ack_o => wb_ack_o, wb_adr_i => wb_adr_i,
wb_cyc_i => wb_cyc_i, wb_stall_o => wb_stall_o, wb_err_o => wb_err_o,
wb_lock_i => '0', wb_rty_o => wb_rty_o, wb_sel_i => (others => '1'),
wb_stb_i => wb_stb_i, wb_tga_i => (others => '0'), wb_tgc_i => (others=>'0'),
wb_we_i => wb_we_i,
irq_o => irq_o);
wb_dat_o <= (others => 'L');
wb_ack_o <= 'L';
process
variable cycle_count : integer:=0;
begin
for i in test_data'range loop
rst_i <= test_data(i).rst_i;
wb_we_i <= test_data(i).wb_we_i;
wb_cyc_i <= test_data(i).wb_cyc_i;
wb_stb_i <= test_data(i).wb_stb_i;
wb_adr_i <= test_data(i).wb_adr_i;
wb_dat_i <= test_data(i).wb_dat_i;
clk <= '1';
wait for CLK_S_PER;
clk <= '0';
wait for CLK_S_PER;
assert (wb_dat_o = test_data(i).wb_dat_o) report "dat_o output mismatch" severity error;
assert (irq_o = test_data(i).irq_o) report "irq_o output mismatch" severity error;
assert (wb_ack_o = test_data(i).wb_ack_o) report "wb_ack_o output mismatch" severity error;
-- assert (icr_o = test_data(i).icr_o) report "icr_o output mismatch" severity failure;
end loop;
clk <= '0';
wait;
end process;
end architecture Behave;
|
bsd-3-clause
|
olgirard/openmsp430
|
fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x8k_dp/simulation/random.vhd
|
6
|
4108
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_2 Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: random.vhd
--
-- Description:
-- Random Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY RANDOM IS
GENERIC ( WIDTH : INTEGER := 32;
SEED : INTEGER :=2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END RANDOM;
ARCHITECTURE BEHAVIORAL OF RANDOM IS
BEGIN
PROCESS(CLK)
VARIABLE RAND_TEMP : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
VARIABLE TEMP : STD_LOGIC := '0';
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
RAND_TEMP := CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
ELSE
IF(EN = '1') THEN
TEMP := RAND_TEMP(WIDTH-1) XOR RAND_TEMP(WIDTH-2);
RAND_TEMP(WIDTH-1 DOWNTO 1) := RAND_TEMP(WIDTH-2 DOWNTO 0);
RAND_TEMP(0) := TEMP;
END IF;
END IF;
END IF;
RANDOM_NUM <= RAND_TEMP;
END PROCESS;
END ARCHITECTURE;
|
bsd-3-clause
|
olgirard/openmsp430
|
fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_dp/simulation/random.vhd
|
6
|
4108
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_2 Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: random.vhd
--
-- Description:
-- Random Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY RANDOM IS
GENERIC ( WIDTH : INTEGER := 32;
SEED : INTEGER :=2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END RANDOM;
ARCHITECTURE BEHAVIORAL OF RANDOM IS
BEGIN
PROCESS(CLK)
VARIABLE RAND_TEMP : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
VARIABLE TEMP : STD_LOGIC := '0';
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
RAND_TEMP := CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
ELSE
IF(EN = '1') THEN
TEMP := RAND_TEMP(WIDTH-1) XOR RAND_TEMP(WIDTH-2);
RAND_TEMP(WIDTH-1 DOWNTO 1) := RAND_TEMP(WIDTH-2 DOWNTO 0);
RAND_TEMP(0) := TEMP;
END IF;
END IF;
END IF;
RANDOM_NUM <= RAND_TEMP;
END PROCESS;
END ARCHITECTURE;
|
bsd-3-clause
|
olgirard/openmsp430
|
fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_sp/simulation/random.vhd
|
6
|
4108
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_2 Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: random.vhd
--
-- Description:
-- Random Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY RANDOM IS
GENERIC ( WIDTH : INTEGER := 32;
SEED : INTEGER :=2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END RANDOM;
ARCHITECTURE BEHAVIORAL OF RANDOM IS
BEGIN
PROCESS(CLK)
VARIABLE RAND_TEMP : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
VARIABLE TEMP : STD_LOGIC := '0';
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
RAND_TEMP := CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
ELSE
IF(EN = '1') THEN
TEMP := RAND_TEMP(WIDTH-1) XOR RAND_TEMP(WIDTH-2);
RAND_TEMP(WIDTH-1 DOWNTO 1) := RAND_TEMP(WIDTH-2 DOWNTO 0);
RAND_TEMP(0) := TEMP;
END IF;
END IF;
END IF;
RANDOM_NUM <= RAND_TEMP;
END PROCESS;
END ARCHITECTURE;
|
bsd-3-clause
|
olgirard/openmsp430
|
fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_sp/example_design/ram_16x1k_sp_prod.vhd
|
1
|
10186
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: ram_16x1k_sp_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : spartan6
-- C_XDEVICEFAMILY : spartan6
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 0
-- C_BYTE_SIZE : 8
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 0
-- C_INIT_FILE_NAME : no_coe_file_loaded
-- C_USE_DEFAULT_DATA : 0
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 1
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 1
-- C_WEA_WIDTH : 2
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 16
-- C_READ_WIDTH_A : 16
-- C_WRITE_DEPTH_A : 1024
-- C_READ_DEPTH_A : 1024
-- C_ADDRA_WIDTH : 10
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 1
-- C_WEB_WIDTH : 2
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 16
-- C_READ_WIDTH_B : 16
-- C_WRITE_DEPTH_B : 1024
-- C_READ_DEPTH_B : 1024
-- C_ADDRB_WIDTH : 10
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY ram_16x1k_sp_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(9 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END ram_16x1k_sp_prod;
ARCHITECTURE xilinx OF ram_16x1k_sp_prod IS
COMPONENT ram_16x1k_sp_exdes IS
PORT (
--Port A
ENA : IN STD_LOGIC; --opt port
WEA : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : ram_16x1k_sp_exdes
PORT MAP (
--Port A
ENA => ENA,
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA
);
END xilinx;
|
bsd-3-clause
|
olgirard/openmsp430
|
fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x8k_dp/simulation/addr_gen.vhd
|
6
|
4409
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_2 Core - Address Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: addr_gen.vhd
--
-- Description:
-- Address Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY ADDR_GEN IS
GENERIC ( C_MAX_DEPTH : INTEGER := 1024 ;
RST_VALUE : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS=> '0');
RST_INC : INTEGER := 0);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
LOAD :IN STD_LOGIC;
LOAD_VALUE : IN STD_LOGIC_VECTOR (31 DOWNTO 0) := (OTHERS => '0');
ADDR_OUT : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) --OUTPUT VECTOR
);
END ADDR_GEN;
ARCHITECTURE BEHAVIORAL OF ADDR_GEN IS
SIGNAL ADDR_TEMP : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS =>'0');
BEGIN
ADDR_OUT <= ADDR_TEMP;
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 );
ELSE
IF(EN='1') THEN
IF(LOAD='1') THEN
ADDR_TEMP <=LOAD_VALUE;
ELSE
IF(ADDR_TEMP = C_MAX_DEPTH-1) THEN
ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 );
ELSE
ADDR_TEMP <= ADDR_TEMP + '1';
END IF;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE;
|
bsd-3-clause
|
olgirard/openmsp430
|
fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_sp/example_design/ram_16x1k_sp_exdes.vhd
|
1
|
4750
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: ram_16x1k_sp_exdes.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY ram_16x1k_sp_exdes IS
PORT (
--Inputs - Port A
ENA : IN STD_LOGIC; --opt port
WEA : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END ram_16x1k_sp_exdes;
ARCHITECTURE xilinx OF ram_16x1k_sp_exdes IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT ram_16x1k_sp IS
PORT (
--Port A
ENA : IN STD_LOGIC; --opt port
WEA : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bmg0 : ram_16x1k_sp
PORT MAP (
--Port A
ENA => ENA,
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA_buf
);
END xilinx;
|
bsd-3-clause
|
olgirard/openmsp430
|
fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_dp/example_design/ram_16x1k_dp_prod.vhd
|
1
|
10695
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: ram_16x1k_dp_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : spartan6
-- C_XDEVICEFAMILY : spartan6
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 2
-- C_BYTE_SIZE : 8
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 0
-- C_INIT_FILE_NAME : no_coe_file_loaded
-- C_USE_DEFAULT_DATA : 0
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 1
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 1
-- C_WEA_WIDTH : 2
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 16
-- C_READ_WIDTH_A : 16
-- C_WRITE_DEPTH_A : 1024
-- C_READ_DEPTH_A : 1024
-- C_ADDRA_WIDTH : 10
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 1
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 1
-- C_WEB_WIDTH : 2
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 16
-- C_READ_WIDTH_B : 16
-- C_WRITE_DEPTH_B : 1024
-- C_READ_DEPTH_B : 1024
-- C_ADDRB_WIDTH : 10
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 1
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY ram_16x1k_dp_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(9 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END ram_16x1k_dp_prod;
ARCHITECTURE xilinx OF ram_16x1k_dp_prod IS
COMPONENT ram_16x1k_dp_exdes IS
PORT (
--Port A
ENA : IN STD_LOGIC; --opt port
WEA : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Port B
ENB : IN STD_LOGIC; --opt port
WEB : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : ram_16x1k_dp_exdes
PORT MAP (
--Port A
ENA => ENA,
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA,
--Port B
ENB => ENB,
WEB => WEB,
ADDRB => ADDRB,
DINB => DINB,
DOUTB => DOUTB,
CLKB => CLKB
);
END xilinx;
|
bsd-3-clause
|
VectorBlox/risc-v
|
ip/orca/hdl/load_store_unit.vhd
|
1
|
8241
|
library ieee;
use ieee.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
library work;
use work.constants_pkg.all;
use work.utils.all;
entity load_store_unit is
generic (
REGISTER_SIZE : positive range 32 to 32;
SIGN_EXTENSION_SIZE : positive;
ENABLE_EXCEPTIONS : boolean
);
port (
clk : in std_logic;
reset : in std_logic;
lsu_idle : out std_logic;
to_lsu_valid : in std_logic;
from_lsu_illegal : out std_logic;
from_lsu_misalign : out std_logic;
rs1_data : in std_logic_vector(REGISTER_SIZE-1 downto 0);
rs2_data : in std_logic_vector(REGISTER_SIZE-1 downto 0);
instruction : in std_logic_vector(31 downto 0);
sign_extension : in std_logic_vector(SIGN_EXTENSION_SIZE-1 downto 0);
load_in_progress : buffer std_logic;
writeback_stall_from_lsu : buffer std_logic;
lsu_ready : out std_logic;
from_lsu_data : out std_logic_vector(REGISTER_SIZE-1 downto 0);
from_lsu_valid : out std_logic;
--ORCA-internal memory-mapped master
oimm_address : out std_logic_vector(REGISTER_SIZE-1 downto 0);
oimm_byteenable : out std_logic_vector((REGISTER_SIZE/8)-1 downto 0);
oimm_requestvalid : buffer std_logic;
oimm_readnotwrite : buffer std_logic;
oimm_writedata : out std_logic_vector(REGISTER_SIZE-1 downto 0);
oimm_readdata : in std_logic_vector(REGISTER_SIZE-1 downto 0);
oimm_readdatavalid : in std_logic;
oimm_waitrequest : in std_logic
);
end entity load_store_unit;
architecture rtl of load_store_unit is
signal from_instruction_illegal : std_logic;
signal from_alignment_illegal : std_logic;
alias base_address : std_logic_vector(REGISTER_SIZE-1 downto 0) is rs1_data;
alias source_data : std_logic_vector(REGISTER_SIZE-1 downto 0) is rs2_data;
alias opcode : std_logic_vector(6 downto 0) is instruction(INSTR_OPCODE'range);
alias func3 : std_logic_vector(2 downto 0) is instruction(INSTR_FUNC3'range);
signal imm : std_logic_vector(11 downto 0);
signal address_unaligned : std_logic_vector(REGISTER_SIZE-1 downto 0);
signal load_func3 : std_logic_vector(2 downto 0);
signal load_alignment : std_logic_vector(1 downto 0);
signal store_byte0 : std_logic_vector(7 downto 0);
signal store_byte1 : std_logic_vector(7 downto 0);
signal store_byte2 : std_logic_vector(7 downto 0);
signal store_byte3 : std_logic_vector(7 downto 0);
signal load_byte0 : std_logic_vector(7 downto 0);
signal load_byte1 : std_logic_vector(7 downto 0);
signal load_byte2 : std_logic_vector(7 downto 0);
signal load_byte3 : std_logic_vector(7 downto 0);
signal store_select : std_logic;
signal store_valid : std_logic;
signal load_select : std_logic;
signal load_valid : std_logic;
begin
--Decode instruction to select submodule. All paths must decode to exactly
--one submodule.
--ASSUMES only LOAD_OP | STORE_OP for opcode.
process (opcode, func3) is
begin
store_select <= '0';
load_select <= '0';
from_instruction_illegal <= '0';
if opcode(5) = LOAD_OP(5) then
if ENABLE_EXCEPTIONS then
case func3 is
when LS_DUBL_FUNC3 | LS_UWORD_FUNC3 | LS_UDUBL_FUNC3 =>
from_instruction_illegal <= '1';
when others =>
load_select <= '1';
end case;
else
load_select <= '1';
end if;
else
if ENABLE_EXCEPTIONS then
case func3 is
when LS_BYTE_FUNC3 | LS_HALF_FUNC3 | LS_WORD_FUNC3 =>
store_select <= '1';
when others =>
from_instruction_illegal <= '1';
end case;
else
store_select <= '1';
end if;
end if;
end process;
--Check for unaligned accesses. Disabled until properly merged exported to sys_call
from_alignment_illegal <= to_lsu_valid when (ENABLE_EXCEPTIONS and
((func3(1) = '1' and address_unaligned(1 downto 0) /= "00") or
(func3(0) = '1' and address_unaligned(0) /= '0')))
else '0';
from_lsu_misalign <= from_alignment_illegal;
from_lsu_illegal <= from_instruction_illegal;
store_valid <= store_select and (not from_alignment_illegal);
load_valid <= load_select and (not from_alignment_illegal);
oimm_requestvalid <= (load_valid or store_valid) and to_lsu_valid;
oimm_readnotwrite <= '1' when opcode(5) = LOAD_OP(5) else '0';
imm <= instruction(31 downto 25) & instruction(11 downto 7) when instruction(5) = '1'
else instruction(31 downto 20);
address_unaligned <= std_logic_vector(unsigned(sign_extension(REGISTER_SIZE-12-1 downto 0) &
imm)+unsigned(base_address));
--Little endian byte-enables
oimm_byteenable <= "0001" when func3 = LS_BYTE_FUNC3 and address_unaligned(1 downto 0) = "00" else
"0010" when func3 = LS_BYTE_FUNC3 and address_unaligned(1 downto 0) = "01" else
"0100" when func3 = LS_BYTE_FUNC3 and address_unaligned(1 downto 0) = "10" else
"1000" when func3 = LS_BYTE_FUNC3 and address_unaligned(1 downto 0) = "11" else
"0011" when func3 = LS_HALF_FUNC3 and address_unaligned(1 downto 0) = "00" else
"1100" when func3 = LS_HALF_FUNC3 and address_unaligned(1 downto 0) = "10" else
"1111";
--Align bytes for stores
store_byte3 <= source_data(7 downto 0) when address_unaligned(1 downto 0) = "11" else
source_data(15 downto 8) when address_unaligned(1 downto 0) = "10" else
source_data(31 downto 24);
store_byte2 <= source_data(7 downto 0) when address_unaligned(1 downto 0) = "10" else
source_data(23 downto 16);
store_byte1 <= source_data(7 downto 0) when address_unaligned(1 downto 0) = "01" else
source_data(15 downto 8);
store_byte0 <= source_data(7 downto 0);
oimm_writedata <= store_byte3 & store_byte2 & store_byte1 & store_byte0;
--Addresses are aligned to word boundary by memory_interface module
oimm_address <= address_unaligned(REGISTER_SIZE-1 downto 0);
--Stall if sending a request and slave is not ready or if awaiting readdata
--and it hasn't arrived yet
writeback_stall_from_lsu <= load_in_progress and (not oimm_readdatavalid);
lsu_ready <= ((not load_valid) and (not store_valid)) or (not oimm_waitrequest);
lsu_idle <= not load_in_progress; --idle is state-only
process(clk)
begin
if rising_edge(clk) then
if oimm_readdatavalid = '1' then
load_in_progress <= '0';
end if;
if (oimm_requestvalid = '1' and oimm_readnotwrite = '1') and oimm_waitrequest = '0' then
load_alignment <= address_unaligned(1 downto 0);
load_func3 <= func3;
load_in_progress <= '1';
end if;
if reset = '1' then
load_in_progress <= '0';
end if;
end if;
end process;
--Align bytes after load
load_byte3 <= oimm_readdata(31 downto 24);
load_byte2 <= oimm_readdata(23 downto 16);
load_byte1 <= oimm_readdata(15 downto 8) when load_alignment = "00" else
oimm_readdata(31 downto 24);
load_byte0 <= oimm_readdata(7 downto 0) when load_alignment = "00" else
oimm_readdata(15 downto 8) when load_alignment = "01" else
oimm_readdata(23 downto 16) when load_alignment = "10" else
oimm_readdata(31 downto 24);
--Zero/sign extend the read data
with load_func3 select
from_lsu_data <=
std_logic_vector(resize(signed(load_byte0), REGISTER_SIZE)) when LS_BYTE_FUNC3,
std_logic_vector(resize(signed(load_byte1 & load_byte0), REGISTER_SIZE)) when LS_HALF_FUNC3,
std_logic_vector(resize(unsigned(load_byte0), REGISTER_SIZE)) when LS_UBYTE_FUNC3,
std_logic_vector(resize(unsigned(load_byte1 & load_byte0), REGISTER_SIZE)) when LS_UHALF_FUNC3,
load_byte3 & load_byte2 & load_byte1 & load_byte0 when others;
from_lsu_valid <= oimm_readdatavalid;
end architecture;
|
bsd-3-clause
|
alvieboy/xtc-base
|
fetch.vhd
|
1
|
6106
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.xtcpkg.all;
entity fetch is
port (
clk: in std_logic;
rst: in std_logic;
-- Connection to ROM
stall: in std_logic;
valid: in std_logic;
address: out std_logic_vector(31 downto 0);
read: in std_logic_vector(31 downto 0);
enable: out std_logic;
strobe: out std_logic;
seq: out std_logic;
abort: out std_logic;
nseq: out std_logic;
-- Control
freeze: in std_logic;
jump: in std_logic;
jumppriv: in std_logic;
jumpaddr: in word_type;
dual: in std_logic;
-- Outputs for next stages
fuo: out fetch_output_type
);
end entity fetch;
architecture behave of fetch is
signal fr: fetch_regs_type;
signal opcode0, opcode1: std_logic_vector(15 downto 0);
signal strobe_i: std_logic;
-- debug only
signal busycnt: unsigned(31 downto 0);
begin
fault1: if FAULTCHECKS generate
process(clk)
begin
if rising_edge(clk) then
if rst='1' then
busycnt<=(others =>'0');
else
if strobe_i='1' and stall='1' then
busycnt<=busycnt+1;
else
busycnt<=(others =>'0');
end if;
end if;
end if;
end process;
fuo.internalfault<='1' when busycnt > 65535 else '0';
end generate;
strobe<=strobe_i;
fuo.r <= fr;
fuo.opcode <= opcode0 & opcode1;
address <= std_logic_vector(fr.fpc);
nseq <= '1' when fr.state=jumping else '0';
seq <= fr.seq;
process(fr, rst, clk, stall, valid, freeze, dual, jump, jumpaddr,read)
variable fw: fetch_regs_type;
variable npc: word_type;
variable realnpc: word_type;
begin
fw := fr;
npc := fr.fpc + 4;
if dual='1' then
realnpc := fr.pc + 4;
else
realnpc := fr.pc + 2;
end if;
fuo.npc <= realnpc;
fuo.valid <= valid;
abort <= '0';
enable <= not freeze;
--strobe_i <= not freeze;
strobe_i<='1';
if fr.unaligned_jump='1' and read(15)='1' then -- Extended opcode.
fuo.valid <= '0';
end if;
opcode0 <= read(31 downto 16);
if fr.invert_readout='1' then
opcode1 <= fr.qopc;
else
opcode1 <= read(15 downto 0);
end if;
fuo.inverted <= fr.unaligned;
case fr.state is
when running =>
if jump='0' then
if stall='0' and freeze='0' then
fw.fpc := npc;
end if;
if valid='1' then
if freeze='0' then
if not (fr.unaligned_jump='1' and dual='1') then
fw.pc := realnpc;
fw.seq := '1';
end if;
fw.qopc := read(15 downto 0);
fw.unaligned_jump := '0';
end if;
-- simple check
--if dual='1' and fr.unaligned_jump='1' then
-- report "DUAL" severity note;
--end if;
end if;
if dual='0' and valid='1' and freeze='0' then
-- Will go unaligned
if fr.unaligned='0' then
fw.unaligned := '1';
fw.invert_readout:='1';
--enable <= '0';
--strobe_i <= '0';
else
if fr.invert_readout='1' then
strobe_i<='0';
if fr.unaligned_jump='1' then
--strobe_i<='1';
end if;
fw.fpc := fr.fpc;
else
strobe_i <='1';
end if;
-- If we had an unaligned jump, we have to trick
-- the system into outputting directly from the RAM, since this
-- is the value usually queued.
fw.unaligned := '0';
fw.invert_readout := '0';
end if;
else
if dual='1' and freeze='0' and fr.unaligned_jump='1' then
fw.invert_readout:='1';
else
--fw.invert_readout:='0';
end if;
end if;
else
-- Jump request
fw.fpc := jumpaddr;
fw.priv:= jumppriv;
fw.unaligned := jumpaddr(1);
fw.fpc(1 downto 0) := "00";
fw.seq := '0';
fw.pc := jumpaddr;
fw.pc(0) := '0';
fw.unaligned_jump := jumpaddr(1);
fw.state := jumping;
strobe_i <= '0';
enable <= '0';
abort <= '1';
--fuo.valid <= '0';
end if;
when jumping =>
if true then
strobe_i <= '1';
enable <= '1';
if stall='0' then
fw.fpc := npc;
fw.seq := '1';
--fw.unaligned := fr.unaligned_jump;
if fr.unaligned_jump='1' then
fw.invert_readout := '1';
fw.state := aligning;
fw.unaligned_jump:='0';
else
fw.invert_readout := '0';
fw.state := running;
end if;
end if;
else
fw.fpc := jumpaddr;
fw.unaligned := jumpaddr(1);
fw.fpc(1 downto 0) := "00";
fw.pc := jumpaddr;
fw.pc(0) := '0';
fw.unaligned_jump := jumpaddr(1);
--fw.state := jumping;
strobe_i <= '0';
enable <= '0';
abort <= '1';
end if;
fuo.valid<='0';
when aligning =>
fuo.valid<='0';
if valid='1' then
fw.qopc := read(15 downto 0);
--fw.unaligned := '0';
fw.fpc := npc;
fw.seq := '1';
fw.state := running;
end if;
when others =>
end case;
if rst='1' then
fw.pc := RESETADDRESS;
fw.fpc := RESETADDRESS;
fw.seq := '0';
fw.priv:='1';
--strobe_i <= '0';
--enable <= '0';
fw.unaligned := '0';
fw.unaligned_jump := '0';
fw.invert_readout := '0';
fw.state := jumping;
fw.qopc := (others => '0');
--fuo.valid<='0';
end if;
if rising_edge(clk) then
fr <= fw;
end if;
end process;
end behave;
|
bsd-3-clause
|
alvieboy/xtc-base
|
tb_standalone.vhd
|
1
|
6683
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.xtcpkg.all;
use work.xtccomppkg.all;
use work.wishbonepkg.all;
entity tbs is
end entity tbs;
architecture sim of tbs is
constant period: time := 10 ns;
signal w_clk: std_logic := '0';
signal w_rst: std_logic := '0';
signal wb_read: std_logic_vector(31 downto 0);
signal wb_write: std_logic_vector(31 downto 0);
signal wb_address: std_logic_vector(31 downto 0);
signal wb_stb: std_logic;
signal wb_cyc: std_logic;
signal wb_sel: std_logic_vector(3 downto 0);
signal wb_we: std_logic;
signal wb_ack: std_logic;
signal wb_stall: std_logic;
signal rom_wb_ack: std_logic;
signal rom_wb_read: std_logic_vector(31 downto 0);
signal rom_wb_adr: std_logic_vector(31 downto 0);
signal rom_wb_cyc: std_logic;
signal rom_wb_stb: std_logic;
signal rom_wb_cti: std_logic_vector(2 downto 0);
signal rom_wb_stall: std_logic;
component wbarb2_1 is
generic (
ADDRESS_HIGH: integer := 31;
ADDRESS_LOW: integer := 0
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master 0 signals
m0_wb_dat_o: out std_logic_vector(31 downto 0);
m0_wb_dat_i: in std_logic_vector(31 downto 0);
m0_wb_adr_i: in std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
m0_wb_sel_i: in std_logic_vector(3 downto 0);
m0_wb_cti_i: in std_logic_vector(2 downto 0);
m0_wb_we_i: in std_logic;
m0_wb_cyc_i: in std_logic;
m0_wb_stb_i: in std_logic;
m0_wb_stall_o: out std_logic;
m0_wb_ack_o: out std_logic;
-- Master 1 signals
m1_wb_dat_o: out std_logic_vector(31 downto 0);
m1_wb_dat_i: in std_logic_vector(31 downto 0);
m1_wb_adr_i: in std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
m1_wb_sel_i: in std_logic_vector(3 downto 0);
m1_wb_cti_i: in std_logic_vector(2 downto 0);
m1_wb_we_i: in std_logic;
m1_wb_cyc_i: in std_logic;
m1_wb_stb_i: in std_logic;
m1_wb_ack_o: out std_logic;
m1_wb_stall_o: out std_logic;
-- Slave signals
s0_wb_dat_i: in std_logic_vector(31 downto 0);
s0_wb_dat_o: out std_logic_vector(31 downto 0);
s0_wb_adr_o: out std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
s0_wb_sel_o: out std_logic_vector(3 downto 0);
s0_wb_cti_o: out std_logic_vector(2 downto 0);
s0_wb_we_o: out std_logic;
s0_wb_cyc_o: out std_logic;
s0_wb_stb_o: out std_logic;
s0_wb_ack_i: in std_logic;
s0_wb_stall_i: in std_logic
);
end component;
component wb_singleport_ram is
generic (
bits: natural := 8
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(31 downto 0);
wb_dat_i: in std_logic_vector(31 downto 0);
wb_adr_i: in std_logic_vector(31 downto 0);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic
);
end component;
component wb_master_np_to_slave_p is
generic (
ADDRESS_HIGH: integer := 31;
ADDRESS_LOW: integer := 0
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master signals
m_wb_dat_o: out std_logic_vector(31 downto 0);
m_wb_dat_i: in std_logic_vector(31 downto 0);
m_wb_adr_i: in std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
m_wb_sel_i: in std_logic_vector(3 downto 0);
m_wb_cti_i: in std_logic_vector(2 downto 0);
m_wb_we_i: in std_logic;
m_wb_cyc_i: in std_logic;
m_wb_stb_i: in std_logic;
m_wb_ack_o: out std_logic;
-- Slave signals
s_wb_dat_i: in std_logic_vector(31 downto 0);
s_wb_dat_o: out std_logic_vector(31 downto 0);
s_wb_adr_o: out std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
s_wb_sel_o: out std_logic_vector(3 downto 0);
s_wb_cti_o: out std_logic_vector(2 downto 0);
s_wb_we_o: out std_logic;
s_wb_cyc_o: out std_logic;
s_wb_stb_o: out std_logic;
s_wb_ack_i: in std_logic;
s_wb_stall_i: in std_logic
);
end component;
component romram is
generic (
BITS: integer := 32
);
port (
ram_wb_clk_i: in std_logic;
ram_wb_rst_i: in std_logic;
ram_wb_ack_o: out std_logic;
ram_wb_dat_i: in std_logic_vector(31 downto 0);
ram_wb_dat_o: out std_logic_vector(31 downto 0);
ram_wb_adr_i: in std_logic_vector(BITS-1 downto 2);
ram_wb_sel_i: in std_logic_vector(3 downto 0);
ram_wb_cyc_i: in std_logic;
ram_wb_stb_i: in std_logic;
ram_wb_we_i: in std_logic;
ram_wb_stall_o: out std_logic;
rom_wb_clk_i: in std_logic;
rom_wb_rst_i: in std_logic;
rom_wb_ack_o: out std_logic;
rom_wb_dat_o: out std_logic_vector(31 downto 0);
rom_wb_adr_i: in std_logic_vector(BITS-1 downto 2);
rom_wb_cyc_i: in std_logic;
rom_wb_stb_i: in std_logic;
rom_wb_stall_o: out std_logic
);
end component;
begin
w_clk <= not w_clk after period/2;
cpu: xtc
port map (
wb_clk_i => w_clk,
wb_rst_i => w_rst,
-- Master wishbone interface
wb_ack_i => wb_ack,
wb_dat_i => wb_read,
wb_dat_o => wb_write,
wb_adr_o => wb_address,
wb_cyc_o => wb_cyc,
wb_stb_o => wb_stb,
wb_sel_o => wb_sel,
wb_we_o => wb_we,
wb_stall_i => wb_stall,
-- ROM wb interface
rom_wb_ack_i => rom_wb_ack,
rom_wb_dat_i => rom_wb_read,
rom_wb_adr_o => rom_wb_adr,
rom_wb_cyc_o => rom_wb_cyc,
rom_wb_stb_o => rom_wb_stb,
rom_wb_stall_i => rom_wb_stall,
wb_inta_i => '0',
isnmi => '0'
);
myram: romram
generic map (
BITS => 15
)
port map (
ram_wb_clk_i => w_clk,
ram_wb_rst_i => w_rst,
ram_wb_ack_o => wb_ack,
ram_wb_dat_i => wb_write,
ram_wb_dat_o => wb_read,
ram_wb_adr_i => wb_address(14 downto 2),
ram_wb_cyc_i => wb_cyc,
ram_wb_stb_i => wb_stb,
ram_wb_sel_i => wb_sel,
ram_wb_we_i => wb_we,
ram_wb_stall_o => wb_stall,
rom_wb_clk_i => w_clk,
rom_wb_rst_i => w_rst,
rom_wb_ack_o => rom_wb_ack,
rom_wb_dat_o => rom_wb_read,
rom_wb_adr_i => rom_wb_adr(14 downto 2),
rom_wb_cyc_i => rom_wb_cyc,
rom_wb_stb_i => rom_wb_stb,
rom_wb_stall_o => rom_wb_stall
);
-- Reset procedure
process
begin
w_rst<='0';
wait for period;
w_rst<='1';
wait for period;
w_rst<='0';
wait;
end process;
end sim;
|
bsd-3-clause
|
alvieboy/xtc-base
|
wb_master_p_to_slave_np.vhd
|
1
|
1496
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
library work;
use work.wishbonepkg.all;
entity wb_master_p_to_slave_np is
port (
syscon: in wb_syscon_type;
-- Master signals
mwbi: in wb_mosi_type;
mwbo: out wb_miso_type;
-- Slave signals
swbi: in wb_miso_type;
swbo: out wb_mosi_type
);
end entity wb_master_p_to_slave_np;
architecture behave of wb_master_p_to_slave_np is
type state_type is ( idle, wait_for_ack );
signal state: state_type;
signal wo: wb_mosi_type;
begin
process(syscon.clk)
begin
if rising_edge(syscon.clk) then
if syscon.rst='1' then
state <= idle;
mwbo.stall <= '0';
wo.cyc<='0';
else
case state is
when idle =>
if mwbi.cyc='1' and mwbi.stb='1' then
state <= wait_for_ack;
wo <= mwbi;
mwbo.stall <= '1';
end if;
when wait_for_ack =>
if swbi.ack='1' or swbi.err='1' then
wo.cyc <= '0';
wo.stb <= '0';
mwbo.stall <= '0';
state <= idle;
end if;
when others =>
end case;
end if;
end if;
end process;
swbo.stb <= wo.stb;-- when state=idle else '1';
swbo.dat <= wo.dat;
swbo.adr <= wo.adr;
swbo.sel <= wo.sel;
swbo.tag <= wo.tag;
swbo.we <= wo.we;
swbo.cyc <= wo.cyc;
mwbo.dat <= swbi.dat;
mwbo.ack <= swbi.ack;
mwbo.err <= swbi.err;
mwbo.tag <= swbi.tag;
end behave;
|
bsd-3-clause
|
cathalmccabe/PYNQ
|
boards/ip/dvi2rgb_v1_7/src/dvi2rgb.vhd
|
4
|
11324
|
-------------------------------------------------------------------------------
--
-- File: dvi2rgb.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 24 July 2015
--
-------------------------------------------------------------------------------
-- (c) 2015 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module connects to a top level DVI 1.0 sink interface comprised of three
-- TMDS data channels and one TMDS clock channel. It includes the necessary
-- clock infrastructure, deserialization, phase alignment, channel deskew and
-- decode logic. It outputs 24-bit RGB video data along with pixel clock and
-- synchronization signals.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.DVI_Constants.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity dvi2rgb is
Generic (
kEmulateDDC : boolean := true; --will emulate a DDC EEPROM with basic EDID, if set to yes
kRstActiveHigh : boolean := true; --true, if active-high; false, if active-low
kAddBUFG : boolean := true; --true, if PixelClk should be re-buffered with BUFG
kClkRange : natural := 2; -- MULT_F = kClkRange*5 (choose >=120MHz=1, >=60MHz=2, >=40MHz=3)
kEdidFileName : string := "900p_edid.data"; -- Select EDID file to use
-- 7-series specific
kIDLY_TapValuePs : natural := 78; --delay in ps per tap
kIDLY_TapWidth : natural := 5); --number of bits for IDELAYE2 tap counter
Port (
-- DVI 1.0 TMDS video interface
TMDS_Clk_p : in std_logic;
TMDS_Clk_n : in std_logic;
TMDS_Data_p : in std_logic_vector(2 downto 0);
TMDS_Data_n : in std_logic_vector(2 downto 0);
-- Auxiliary signals
RefClk : in std_logic; --200 MHz reference clock for IDELAYCTRL, reset, lock monitoring etc.
aRst : in std_logic; --asynchronous reset; must be reset when RefClk is not within spec
aRst_n : in std_logic; --asynchronous reset; must be reset when RefClk is not within spec
-- Video out
vid_pData : out std_logic_vector(23 downto 0);
vid_pVDE : out std_logic;
vid_pHSync : out std_logic;
vid_pVSync : out std_logic;
PixelClk : out std_logic; --pixel-clock recovered from the DVI interface
SerialClk : out std_logic; -- advanced use only; 5x PixelClk
aPixelClkLckd : out std_logic; -- advanced use only; PixelClk and SerialClk stable
-- Optional DDC port
DDC_SDA_I : in std_logic;
DDC_SDA_O : out std_logic;
DDC_SDA_T : out std_logic;
DDC_SCL_I : in std_logic;
DDC_SCL_O : out std_logic;
DDC_SCL_T : out std_logic;
pRst : in std_logic; -- synchronous reset; will restart locking procedure
pRst_n : in std_logic -- synchronous reset; will restart locking procedure
);
end dvi2rgb;
architecture Behavioral of dvi2rgb is
type dataIn_t is array (2 downto 0) of std_logic_vector(7 downto 0);
type eyeSize_t is array (2 downto 0) of std_logic_vector(kIDLY_TapWidth-1 downto 0);
signal aLocked, SerialClk_int, PixelClk_int, pLockLostRst: std_logic;
signal pRdy, pVld, pDE, pAlignErr, pC0, pC1 : std_logic_vector(2 downto 0);
signal pDataIn : dataIn_t;
signal pEyeSize : eyeSize_t;
signal aRst_int, pRst_int : std_logic;
signal pData : std_logic_vector(23 downto 0);
signal pVDE, pHSync, pVSync : std_logic;
-- set KEEP attribute so that synthesis does not optimize this register
-- in case we want to connect it to an inserted ILA debug core
attribute KEEP : string;
attribute KEEP of pEyeSize: signal is "TRUE";
begin
ResetActiveLow: if not kRstActiveHigh generate
aRst_int <= not aRst_n;
pRst_int <= not pRst_n;
end generate ResetActiveLow;
ResetActiveHigh: if kRstActiveHigh generate
aRst_int <= aRst;
pRst_int <= pRst;
end generate ResetActiveHigh;
-- Clocking infrastructure to obtain a usable fast serial clock and a slow parallel clock
TMDS_ClockingX: entity work.TMDS_Clocking
generic map (
kClkRange => kClkRange)
port map (
aRst => aRst_int,
RefClk => RefClk,
TMDS_Clk_p => TMDS_Clk_p,
TMDS_Clk_n => TMDS_Clk_n,
aLocked => aLocked,
PixelClk => PixelClk_int, -- slow parallel clock
SerialClk => SerialClk_int -- fast serial clock
);
-- We need a reset bridge to use the asynchronous aLocked signal to reset our circuitry
-- and decrease the chance of metastability. The signal pLockLostRst can be used as
-- asynchronous reset for any flip-flop in the PixelClk domain, since it will be de-asserted
-- synchronously.
LockLostReset: entity work.ResetBridge
generic map (
kPolarity => '1')
port map (
aRst => not aLocked,
OutClk => PixelClk_int,
oRst => pLockLostRst);
-- Three data channel decoders
DataDecoders: for iCh in 2 downto 0 generate
DecoderX: entity work.TMDS_Decoder
generic map (
kCtlTknCount => kMinTknCntForBlank, --how many subsequent control tokens make a valid blank detection (DVI spec)
kTimeoutMs => kBlankTimeoutMs, --what is the maximum time interval for a blank to be detected (DVI spec)
kRefClkFrqMHz => 200, --what is the RefClk frequency
kIDLY_TapValuePs => kIDLY_TapValuePs, --delay in ps per tap
kIDLY_TapWidth => kIDLY_TapWidth) --number of bits for IDELAYE2 tap counter
port map (
aRst => pLockLostRst,
PixelClk => PixelClk_int,
SerialClk => SerialClk_int,
RefClk => RefClk,
pRst => pRst_int,
sDataIn_p => TMDS_Data_p(iCh),
sDataIn_n => TMDS_Data_n(iCh),
pOtherChRdy(1 downto 0) => pRdy((iCh+1) mod 3) & pRdy((iCh+2) mod 3), -- tie channels together for channel de-skew
pOtherChVld(1 downto 0) => pVld((iCh+1) mod 3) & pVld((iCh+2) mod 3), -- tie channels together for channel de-skew
pAlignErr => pAlignErr(iCh),
pC0 => pC0(iCh),
pC1 => pC1(iCh),
pMeRdy => pRdy(iCh),
pMeVld => pVld(iCh),
pVde => pDE(iCh),
pDataIn(7 downto 0) => pDataIn(iCh),
pEyeSize => pEyeSize(iCh)
);
end generate DataDecoders;
-- RGB Output conform DVI 1.0
-- except that it sends blank pixel during blanking
-- for some reason video_data uses RBG packing
pData(23 downto 16) <= pDataIn(2); -- red is channel 2
pData(7 downto 0) <= pDataIn(1); -- green is channel 1
pData(15 downto 8) <= pDataIn(0); -- blue is channel 0
pHSync <= pC0(0); -- channel 0 carries control signals too
pVSync <= pC1(0); -- channel 0 carries control signals too
pVDE <= pDE(0); -- since channels are aligned, all of them are either active or blanking at once
-- Clock outputs
SerialClk <= SerialClk_int; -- fast 5x pixel clock for advanced use only
aPixelClkLckd <= aLocked;
----------------------------------------------------------------------------------
-- Re-buffer PixelClk with a BUFG so that it can reach the whole device, unlike
-- through a BUFR. Since BUFG introduces a delay on the clock path, pixel data is
-- re-registered here.
----------------------------------------------------------------------------------
GenerateBUFG: if kAddBUFG generate
ResyncToBUFG_X: entity work.ResyncToBUFG
port map (
-- Video in
piData => pData,
piVDE => pVDE,
piHSync => pHSync,
piVSync => pVSync,
PixelClkIn => PixelClk_int,
-- Video out
poData => vid_pData,
poVDE => vid_pVDE,
poHSync => vid_pHSync,
poVSync => vid_pVSync,
PixelClkOut => PixelClk
);
end generate GenerateBUFG;
DontGenerateBUFG: if not kAddBUFG generate
vid_pData <= pData;
vid_pVDE <= pVDE;
vid_pHSync <= pHSync;
vid_pVSync <= pVSync;
PixelClk <= PixelClk_int;
end generate DontGenerateBUFG;
----------------------------------------------------------------------------------
-- Optional DDC EEPROM Display Data Channel - Bi-directional (DDC2B)
-- The EDID will be loaded from the file specified below in kInitFileName.
----------------------------------------------------------------------------------
GenerateDDC: if kEmulateDDC generate
DDC_EEPROM: entity work.EEPROM_8b
generic map (
kSampleClkFreqInMHz => 200,
kSlaveAddress => "1010000",
kAddrBits => 7, -- 128 byte EDID 1.x data
kWritable => false,
kInitFileName => kEdidFileName) -- name of file containing init values
port map(
SampleClk => RefClk,
sRst => '0',
aSDA_I => DDC_SDA_I,
aSDA_O => DDC_SDA_O,
aSDA_T => DDC_SDA_T,
aSCL_I => DDC_SCL_I,
aSCL_O => DDC_SCL_O,
aSCL_T => DDC_SCL_T);
end generate GenerateDDC;
end Behavioral;
|
bsd-3-clause
|
cathalmccabe/PYNQ
|
boards/ip/audio_direct_1.1/src/pdm_rxtx.vhd
|
8
|
10747
|
-------------------------------------------------------------------------------
--
-- COPYRIGHT (C) 2014, Digilent RO. All rights reserved
--
-------------------------------------------------------------------------------
-- FILE NAME : pdm_rxtx.vhd
-- MODULE NAME : PDM Tranceiver
-- AUTHOR : Mihaita Nagy
-- AUTHOR'S EMAIL : [email protected]
-------------------------------------------------------------------------------
-- REVISION HISTORY
-- VERSION DATE AUTHOR DESCRIPTION
-- 1.0 2014-01-30 MihaitaN Created
-------------------------------------------------------------------------------
-- KEYWORDS : PDM
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
------------------------------------------------------------------------
-- Module Declaration
------------------------------------------------------------------------
entity pdm_rxtx is
port (
-- Global signals
CLK_I : in std_logic;
RST_I : in std_logic;
-- Control signals
START_TRANSACTION_I : in std_logic;
STOP_TRANSACTION_I : in std_logic;
RNW_I : in std_logic;
-- Tx FIFO Control signals
TX_FIFO_RST_I : in std_logic;
TX_FIFO_D_I : in std_logic_vector(15 downto 0);
TX_FIFO_WR_EN_I : in std_logic;
-- Rx FIFO Control signals
RX_FIFO_RST_I : in std_logic;
RX_FIFO_D_O : out std_logic_vector(15 downto 0);
RX_FIFO_RD_EN_I : in std_logic;
-- Tx FIFO Flags
TX_FIFO_EMPTY_O : out std_logic;
TX_FIFO_FULL_O : out std_logic;
-- Rx FIFO Flags
RX_FIFO_EMPTY_O : out std_logic;
RX_FIFO_FULL_O : out std_logic;
PDM_M_CLK_O : out std_logic;
PDM_M_DATA_I : in std_logic;
PDM_LRSEL_O : out std_logic;
PWM_AUDIO_O : out std_logic;
PWM_AUDIO_T : out std_logic;
PWM_AUDIO_I : in std_logic
);
end pdm_rxtx;
architecture Behavioral of pdm_rxtx is
------------------------------------------------------------------------
-- Type Declarations
------------------------------------------------------------------------
type States is (sIdle, sCheckRnw, sRead, sWrite);
------------------------------------------------------------------------
-- Signal Declarations
------------------------------------------------------------------------
signal CState, NState : States := sIdle;
signal StartTransaction : std_logic;
signal StopTransaction : std_logic;
signal RxEn : std_logic;
signal TxEn : std_logic;
signal Rnw : std_logic;
signal RxFifoDataIn : std_logic_vector(15 downto 0);
signal RxFifoWrEn : std_logic;
signal TxFifoDataOut : std_logic_vector(15 downto 0);
signal TxFifoRdEn : std_logic;
signal RxFifoRdEn : std_logic;
signal RxFifoRdEn_dly : std_logic;
signal TxFifoWrEn : std_logic;
signal TxFifoWrEn_dly : std_logic;
signal TxFifoEmpty : std_logic;
------------------------------------------------------------------------
-- Component Declarations
------------------------------------------------------------------------
-- deserializer
component pdm_des is
generic(
C_NR_OF_BITS : integer := 16;
C_SYS_CLK_FREQ_MHZ : integer := 100;
C_PDM_FREQ_MHZ : integer range 1 to 3 := 3);
port(
clk_i : in std_logic;
rst_i : in std_logic;
en_i : in std_logic;
done_o : out std_logic;
data_o : out std_logic_vector(15 downto 0);
pdm_m_clk_o : out std_logic;
pdm_m_data_i : in std_logic;
pdm_lrsel_o : out std_logic);
end component;
-- pdm serializer
component pdm_ser is
generic(
C_NR_OF_BITS : integer := 16;
C_SYS_CLK_FREQ_MHZ : integer := 100;
C_PDM_FREQ_MHZ : integer range 1 to 3 := 3);
port(
clk_i : in std_logic;
rst_i : in std_logic;
en_i : in std_logic;
done_o : out std_logic;
data_i : in std_logic_vector(15 downto 0);
pwm_audio_o : out std_logic;
pwm_audio_t : out std_logic;
pwm_audio_i : in std_logic);
--pwm_sdaudio_o : out std_logic);
end component;
-- the FIFO, used for Rx and Tx
component fifo_512
port (
clk : in std_logic;
rst : in std_logic;
din : in std_logic_vector(15 downto 0);
wr_en : in std_logic;
rd_en : in std_logic;
dout : out std_logic_vector(15 downto 0);
full : out std_logic;
empty : out std_logic);
end component;
------------------------------------------------------------------------
-- Module Implementation
------------------------------------------------------------------------
begin
------------------------------------------------------------------------
-- Register all inputs of the FSM
------------------------------------------------------------------------
REG_IN: process(CLK_I)
begin
if rising_edge(CLK_I) then
StartTransaction <= START_TRANSACTION_I;
StopTransaction <= STOP_TRANSACTION_I;
Rnw <= RNW_I;
end if;
end process REG_IN;
------------------------------------------------------------------------
-- Register and generate pulse out of rd/wr enables
------------------------------------------------------------------------
RDWR_PULSE: process(CLK_I)
begin
if rising_edge(CLK_I) then
RxFifoRdEn_dly <= RX_FIFO_RD_EN_I;
TxFifoWrEn_dly <= TX_FIFO_WR_EN_I;
end if;
end process RDWR_PULSE;
RxFifoRdEn <= RX_FIFO_RD_EN_I and not RxFifoRdEn_dly;
TxFifoWrEn <= TX_FIFO_WR_EN_I and not TxFifoWrEn_dly;
------------------------------------------------------------------------
-- Deserializer
------------------------------------------------------------------------
Inst_Deserializer: pdm_des
generic map(
C_NR_OF_BITS => 16,
C_SYS_CLK_FREQ_MHZ => 100,
C_PDM_FREQ_MHZ => 3)
port map(
clk_i => CLK_I,
rst_i => RST_I,
en_i => RxEn,
done_o => RxFifoWrEn,
data_o => RxFifoDataIn,
pdm_m_clk_o => PDM_M_CLK_O,
pdm_m_data_i => PDM_M_DATA_I,
pdm_lrsel_o => PDM_LRSEL_O);
------------------------------------------------------------------------
-- Serializer
------------------------------------------------------------------------
Inst_Serializer: pdm_ser
generic map(
C_NR_OF_BITS => 16,
C_SYS_CLK_FREQ_MHZ => 100,
C_PDM_FREQ_MHZ => 3)
port map(
clk_i => CLK_I,
rst_i => RST_I,
en_i => TxEn,
done_o => TxFifoRdEn,
data_i => TxFifoDataOut,
pwm_audio_o => PWM_AUDIO_O,
pwm_audio_t => PWM_AUDIO_T,
pwm_audio_i => PWM_AUDIO_I);
------------------------------------------------------------------------
-- Instantiate the transmitter fifo
------------------------------------------------------------------------
Inst_PdmTxFifo: fifo_512
port map(
clk => CLK_I,
rst => TX_FIFO_RST_I,
din => TX_FIFO_D_I,
wr_en => TxFifoWrEn,
rd_en => TxFifoRdEn,
dout => TxFifoDataOut,
full => TX_FIFO_FULL_O,
empty => TxFifoEmpty);
TX_FIFO_EMPTY_O <= TxFifoEmpty;
------------------------------------------------------------------------
-- Instantiate the receiver fifo
------------------------------------------------------------------------
Inst_PdmRxFifo: fifo_512
port map(
clk => CLK_I,
rst => RX_FIFO_RST_I,
din => RxFifoDataIn,
wr_en => RxFifoWrEn,
rd_en => RxFifoRdEn,
dout => RX_FIFO_D_O,
full => RX_FIFO_FULL_O,
empty => RX_FIFO_EMPTY_O);
------------------------------------------------------------------------
-- Main FSM, register states, next state decode
------------------------------------------------------------------------
REG_STATES: process(CLK_I)
begin
if rising_edge(CLK_I) then
if RST_I = '1' then
CState <= sIdle;
else
CState <= NState;
end if;
end if;
end process REG_STATES;
FSM_TRANS: process(CState, StartTransaction, StopTransaction, Rnw, TxFifoEmpty)
begin
NState <= CState;
case CState is
when sIdle =>
if StartTransaction = '1' then
NState <= sCheckRnw;
end if;
when sCheckRnw =>
if Rnw = '1' then
NState <= sRead;
else
NState <= sWrite;
end if;
when sWrite =>
if TxFifoEmpty = '1' then
NSTate <= sIdle;
end if;
when sRead =>
if StopTransaction = '1' then
NState <= sIdle;
end if;
when others => NState <= sIdle;
end case;
end process FSM_TRANS;
------------------------------------------------------------------------
-- Assert transmit enable
------------------------------------------------------------------------
TXEN_PROC: process(CLK_I)
begin
if rising_edge(CLK_I) then
if CState = sWrite then
TxEn <= '1';
else
TxEn <= '0';
end if;
end if;
end process TXEN_PROC;
------------------------------------------------------------------------
-- Assert receive enable
------------------------------------------------------------------------
RXEN_PROC: process(CLK_I)
begin
if rising_edge(CLK_I) then
if CState = sRead then
RxEn <= '1';
else
RxEn <= '0';
end if;
end if;
end process RXEN_PROC;
end Behavioral;
|
bsd-3-clause
|
cathalmccabe/PYNQ
|
boards/ip/audio_codec_ctrl_v1.0/src/axi_lite_ipif.vhd
|
4
|
13991
|
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved. --
-- --
-- This file contains confidential and proprietary information --
-- of Xilinx, Inc. and is protected under U.S. and --
-- international copyright and other intellectual property --
-- laws. --
-- --
-- DISCLAIMER --
-- This disclaimer is not a license and does not grant any --
-- rights to the materials distributed herewith. Except as --
-- otherwise provided in a valid license issued to you by --
-- Xilinx, and to the maximum extent permitted by applicable --
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --
-- (2) Xilinx shall not be liable (whether in contract or tort, --
-- including negligence, or under any other theory of --
-- liability) for any loss or damage of any kind or nature --
-- related to, arising under or in connection with these --
-- materials, including for any direct, or any indirect, --
-- special, incidental, or consequential loss or damage --
-- (including loss of data, profits, goodwill, or any type of --
-- loss or damage suffered as a result of any action brought --
-- by a third party) even if such damage or loss was --
-- reasonably foreseeable or Xilinx had been advised of the --
-- possibility of the same. --
-- --
-- CRITICAL APPLICATIONS --
-- Xilinx products are not designed or intended to be fail- --
-- safe, or for use in any application requiring fail-safe --
-- performance, such as life-support or safety devices or --
-- systems, Class III medical devices, nuclear facilities, --
-- applications related to the deployment of airbags, or any --
-- other applications that could lead to death, personal --
-- injury, or severe property or environmental damage --
-- (individually and collectively, "Critical --
-- Applications"). Customer assumes the sole risk and --
-- liability of any use of Xilinx products in Critical --
-- Applications, subject only to applicable laws and --
-- regulations governing limitations on product liability. --
-- --
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --
-- PART OF THIS FILE AT ALL TIMES. --
-------------------------------------------------------------------
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_lite_ipif.vhd
-- Version: v1.01.a
-- Description: This is the top level design file for the axi_lite_ipif
-- function. It provides a standardized slave interface
-- between the IP and the AXI. This version supports
-- single read/write transfers only. It does not provide
-- address pipelining or simultaneous read and write
-- operations.
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of axi_lite_ipif.
--
-- --axi_lite_ipif.vhd
-- --slave_attachment.vhd
-- --address_decoder.vhd
-------------------------------------------------------------------------------
-- Author: BSB
--
-- History:
--
-- BSB 05/20/10 -- First version
-- ~~~~~~
-- - Created the first version v1.00.a
-- ^^^^^^
-- ~~~~~~
-- SK 06/09/10 -- v1.01.a
-- 1. updated to reduce the utilization
-- Closed CR #574507
-- 2. Optimized the state machine code
-- 3. Optimized the address decoder logic to generate the CE's with common logic
-- 4. Address GAP decoding logic is removed and timeout counter is made active
-- for all transactions.
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
use work.common_types.all;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_S_AXI_DATA_WIDTH -- AXI data bus width
-- C_S_AXI_ADDR_WIDTH -- AXI address bus width
-- C_S_AXI_MIN_SIZE -- Minimum address range of the IP
-- C_USE_WSTRB -- Use write strobs or not
-- C_DPHASE_TIMEOUT -- Data phase time out counter
-- C_ARD_ADDR_RANGE_ARRAY-- Base /High Address Pair for each Address Range
-- C_ARD_NUM_CE_ARRAY -- Desired number of chip enables for an address range
-- C_FAMILY -- Target FPGA family
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- S_AXI_ACLK -- AXI Clock
-- S_AXI_ARESETN -- AXI Reset
-- S_AXI_AWADDR -- AXI Write address
-- S_AXI_AWVALID -- Write address valid
-- S_AXI_AWREADY -- Write address ready
-- S_AXI_WDATA -- Write data
-- S_AXI_WSTRB -- Write strobes
-- S_AXI_WVALID -- Write valid
-- S_AXI_WREADY -- Write ready
-- S_AXI_BRESP -- Write response
-- S_AXI_BVALID -- Write response valid
-- S_AXI_BREADY -- Response ready
-- S_AXI_ARADDR -- Read address
-- S_AXI_ARVALID -- Read address valid
-- S_AXI_ARREADY -- Read address ready
-- S_AXI_RDATA -- Read data
-- S_AXI_RRESP -- Read response
-- S_AXI_RVALID -- Read valid
-- S_AXI_RREADY -- Read ready
-- Bus2IP_Clk -- Synchronization clock provided to User IP
-- Bus2IP_Reset -- Active high reset for use by the User IP
-- Bus2IP_Addr -- Desired address of read or write operation
-- Bus2IP_RNW -- Read or write indicator for the transaction
-- Bus2IP_BE -- Byte enables for the data bus
-- Bus2IP_CS -- Chip select for the transcations
-- Bus2IP_RdCE -- Chip enables for the read
-- Bus2IP_WrCE -- Chip enables for the write
-- Bus2IP_Data -- Write data bus to the User IP
-- IP2Bus_Data -- Input Read Data bus from the User IP
-- IP2Bus_WrAck -- Active high Write Data qualifier from the IP
-- IP2Bus_RdAck -- Active high Read Data qualifier from the IP
-- IP2Bus_Error -- Error signal from the IP
-------------------------------------------------------------------------------
entity axi_lite_ipif is
generic (
C_S_AXI_DATA_WIDTH : integer range 32 to 32 := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0):= X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer range 0 to 512 := 8;
C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE := -- not used
(
X"0000_0000_7000_0000", -- IP user0 base address
X"0000_0000_7000_00FF", -- IP user0 high address
X"0000_0000_7000_0100", -- IP user1 base address
X"0000_0000_7000_01FF" -- IP user1 high address
);
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := -- not used
(
4, -- User0 CE Number
12 -- User1 CE Number
);
C_FAMILY : string := "virtex6"
);
port (
--System signals
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector
(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector
(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector
((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector
(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector
(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- Controls to the IP/IPIF modules
Bus2IP_Clk : out std_logic;
Bus2IP_Resetn : out std_logic;
Bus2IP_Addr : out std_logic_vector
((C_S_AXI_ADDR_WIDTH-1) downto 0);
Bus2IP_RNW : out std_logic;
Bus2IP_BE : out std_logic_vector
(((C_S_AXI_DATA_WIDTH/8)-1) downto 0);
Bus2IP_CS : out std_logic_vector
(((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1) downto 0);
Bus2IP_RdCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY)-1) downto 0);
Bus2IP_WrCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY)-1) downto 0);
Bus2IP_Data : out std_logic_vector
((C_S_AXI_DATA_WIDTH-1) downto 0);
IP2Bus_Data : in std_logic_vector
((C_S_AXI_DATA_WIDTH-1) downto 0);
IP2Bus_WrAck : in std_logic;
IP2Bus_RdAck : in std_logic;
IP2Bus_Error : in std_logic
);
end axi_lite_ipif;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture imp of axi_lite_ipif is
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Slave Attachment
-------------------------------------------------------------------------------
I_SLAVE_ATTACHMENT: entity work.slave_attachment
generic map(
C_ARD_ADDR_RANGE_ARRAY => C_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY,
C_IPIF_ABUS_WIDTH => C_S_AXI_ADDR_WIDTH,
C_IPIF_DBUS_WIDTH => C_S_AXI_DATA_WIDTH,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_FAMILY => C_FAMILY
)
port map(
-- AXI signals
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_RREADY => S_AXI_RREADY,
-- IPIC signals
Bus2IP_Clk => Bus2IP_Clk,
Bus2IP_Resetn => Bus2IP_Resetn,
Bus2IP_Addr => Bus2IP_Addr,
Bus2IP_RNW => Bus2IP_RNW,
Bus2IP_BE => Bus2IP_BE,
Bus2IP_CS => Bus2IP_CS,
Bus2IP_RdCE => Bus2IP_RdCE,
Bus2IP_WrCE => Bus2IP_WrCE,
Bus2IP_Data => Bus2IP_Data,
IP2Bus_Data => IP2Bus_Data,
IP2Bus_WrAck => IP2Bus_WrAck,
IP2Bus_RdAck => IP2Bus_RdAck,
IP2Bus_Error => IP2Bus_Error
);
end imp;
|
bsd-3-clause
|
SteffenReith/J1Sc
|
src/test/vhdl/J1Nexys4X_IRQ_tb.vhd
|
1
|
2576
|
--------------------------------------------------------------------------------
-- Author: Steffen Reith ([email protected])
--
-- Creation Date: Sun Dec 11 11:46:48 GMT+1 2016
-- Creator: Steffen Reith
-- Module Name: J1SoC_IRQ_TB - A simple testbench for testing the interrupts
-- of the J1 SoC
-- Project Name: J1Sc - A simple J1 implementation in scala
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
entity J1Nexys4X_IRQ_tb is
end J1Nexys4X_IRQ_tb;
architecture Behavioral of J1Nexys4X_IRQ_tb is
-- Clock period definition (100Mhz)
constant clk_period : time := 10 ns;
-- Interrupts
signal extInt : std_logic_vector(0 downto 0) := "0";
-- PModA-Interface
signal pmodA_read : std_logic_vector(7 downto 0);
signal pmodA_write : std_logic_vector(7 downto 0);
signal pmodA_writeEnable : std_logic_vector(7 downto 0);
-- UART signals
signal rx : std_logic := '0';
signal tx : std_logic;
-- I/O signals
signal leds : std_logic_vector(15 downto 0);
-- Clock and reset
signal boardClkLocked : std_logic;
signal boardClk : std_logic;
signal reset : std_logic;
begin
uut : entity work.J1Nexys4X
port map (boardClk => boardClk,
boardClkLocked => boardClkLocked,
reset => reset,
extInt => extInt,
pmodA_read => pmodA_read,
pmodA_write => pmodA_write,
pmodA_writeEnable => pmodA_writeEnable,
rx => rx,
tx => tx,
leds => leds);
-- Clock process definitions
clk_process : process
begin
-- Tell that the clock is stable
boardClkLocked <= '1';
boardClk <= '0';
wait for clk_period/2;
boardClk <= '1';
wait for clk_period/2;
end process;
reboot_proc : process
begin
-- Reset the CPU (asynchron)
reset <= '1';
-- Wait 107ns
wait for 107 ns;
-- Revoke the the reset
reset <= '0';
-- Wait forever
wait;
end process;
-- Stimulus process
stim_proc : process
-- Text I/O
variable lineBuffer : line;
begin
-- Give a info message
write(lineBuffer, string'("Start the simulation of the CPU"));
writeline(output, lineBuffer);
-- Simply wait forever
wait;
end process;
end architecture;
|
bsd-3-clause
|
schelleg/pynq_tutorial
|
Pynq-Z1/vivado/pynq_tutorial/ip/dvi2rgb_v1_6/src/SyncAsync.vhd
|
34
|
3727
|
-------------------------------------------------------------------------------
--
-- File: SyncAsync.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 20 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module synchronizes the asynchronous signal (aIn) with the OutClk clock
-- domain and provides it on oOut. The number of FFs in the synchronizer chain
-- can be configured with kStages. The reset value for oOut can be configured
-- with kResetTo. The asynchronous reset (aReset) is always active-high.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity SyncAsync is
Generic (
kResetTo : std_logic := '0'; --value when reset and upon init
kStages : natural := 2); --double sync by default
Port (
aReset : in STD_LOGIC; -- active-high asynchronous reset
aIn : in STD_LOGIC;
OutClk : in STD_LOGIC;
oOut : out STD_LOGIC);
end SyncAsync;
architecture Behavioral of SyncAsync is
signal oSyncStages : std_logic_vector(kStages-1 downto 0) := (others => kResetTo);
attribute ASYNC_REG : string;
attribute ASYNC_REG of oSyncStages: signal is "TRUE";
begin
Sync: process (OutClk, aReset)
begin
if (aReset = '1') then
oSyncStages <= (others => kResetTo);
elsif Rising_Edge(OutClk) then
oSyncStages <= oSyncStages(oSyncStages'high-1 downto 0) & aIn;
end if;
end process Sync;
oOut <= oSyncStages(oSyncStages'high);
end Behavioral;
|
bsd-3-clause
|
schelleg/pynq_tutorial
|
Pynq-Z1/vivado/pynq_tutorial/ip/rgb2dvi_v1_2/src/SyncAsync.vhd
|
34
|
3727
|
-------------------------------------------------------------------------------
--
-- File: SyncAsync.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 20 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module synchronizes the asynchronous signal (aIn) with the OutClk clock
-- domain and provides it on oOut. The number of FFs in the synchronizer chain
-- can be configured with kStages. The reset value for oOut can be configured
-- with kResetTo. The asynchronous reset (aReset) is always active-high.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity SyncAsync is
Generic (
kResetTo : std_logic := '0'; --value when reset and upon init
kStages : natural := 2); --double sync by default
Port (
aReset : in STD_LOGIC; -- active-high asynchronous reset
aIn : in STD_LOGIC;
OutClk : in STD_LOGIC;
oOut : out STD_LOGIC);
end SyncAsync;
architecture Behavioral of SyncAsync is
signal oSyncStages : std_logic_vector(kStages-1 downto 0) := (others => kResetTo);
attribute ASYNC_REG : string;
attribute ASYNC_REG of oSyncStages: signal is "TRUE";
begin
Sync: process (OutClk, aReset)
begin
if (aReset = '1') then
oSyncStages <= (others => kResetTo);
elsif Rising_Edge(OutClk) then
oSyncStages <= oSyncStages(oSyncStages'high-1 downto 0) & aIn;
end if;
end process Sync;
oOut <= oSyncStages(oSyncStages'high);
end Behavioral;
|
bsd-3-clause
|
schelleg/pynq_tutorial
|
Pynq-Z1/vivado/pynq_tutorial/ip/rgb2dvi_v1_2/src/ClockGen.vhd
|
9
|
8885
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11/03/2014 06:27:16 PM
-- Design Name:
-- Module Name: ClockGen - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity ClockGen is
Generic (
kClkRange : natural := 1; -- MULT_F = kClkRange*5 (choose >=120MHz=1, >=60MHz=2, >=40MHz=3, >=30MHz=4, >=25MHz=5
kClkPrimitive : string := "MMCM"); -- "MMCM" or "PLL" to instantiate, if kGenerateSerialClk true
Port (
PixelClkIn : in STD_LOGIC;
PixelClkOut : out STD_LOGIC;
SerialClk : out STD_LOGIC;
aRst : in STD_LOGIC;
aLocked : out STD_LOGIC);
end ClockGen;
architecture Behavioral of ClockGen is
component SyncAsync is
Generic (
kResetTo : std_logic := '0'; --value when reset and upon init
kStages : natural := 2); --double sync by default
Port (
aReset : in STD_LOGIC; -- active-high asynchronous reset
aIn : in STD_LOGIC;
OutClk : in STD_LOGIC;
oOut : out STD_LOGIC);
end component SyncAsync;
component ResetBridge is
Generic (
kPolarity : std_logic := '1');
Port (
aRst : in STD_LOGIC; -- asynchronous reset; active-high, if kPolarity=1
OutClk : in STD_LOGIC;
oRst : out STD_LOGIC);
end component ResetBridge;
signal PixelClkInX1, PixelClkInX5, FeedbackClk : std_logic;
signal aLocked_int, pLocked, pRst, pLockWasLost : std_logic;
signal pLocked_q : std_logic_vector(2 downto 0) := (others => '1');
begin
-- We need a reset bridge to use the asynchronous aRst signal to reset our circuitry
-- and decrease the chance of metastability. The signal pRst can be used as
-- asynchronous reset for any flip-flop in the PixelClkIn domain, since it will be de-asserted
-- synchronously.
LockLostReset: ResetBridge
generic map (
kPolarity => '1')
port map (
aRst => aRst,
OutClk => PixelClkIn,
oRst => pRst);
PLL_LockSyncAsync: SyncAsync
port map (
aReset => '0',
aIn => aLocked_int,
OutClk => PixelClkIn,
oOut => pLocked);
PLL_LockLostDetect: process(PixelClkIn)
begin
if (pRst = '1') then
pLocked_q <= (others => '1');
pLockWasLost <= '1';
elsif Rising_Edge(PixelClkIn) then
pLocked_q <= pLocked_q(pLocked_q'high-1 downto 0) & pLocked;
pLockWasLost <= (not pLocked_q(0) or not pLocked_q(1)) and pLocked_q(2); --two-pulse
end if;
end process;
-- The TMDS Clk channel carries a character-rate frequency reference
-- In a single Clk period a whole character (10 bits) is transmitted
-- on each data channel. For deserialization of data channel a faster,
-- serial clock needs to be generated. In 7-series architecture an
-- OSERDESE2 primitive doing a 10:1 deserialization in DDR mode needs
-- a fast 5x clock and a slow 1x clock. These two clocks are generated
-- below with an MMCME2_ADV/PLLE2_ADV.
-- Caveats:
-- 1. The primitive uses a multiply-by-5 and divide-by-1 to generate
-- a 5x fast clock.
-- While changes in the frequency of the TMDS Clk are tracked by the
-- MMCM, for some TMDS Clk frequencies the datasheet specs for the VCO
-- frequency limits are not met. In other words, there is no single
-- set of MMCM multiply and divide values that can work for the whole
-- range of resolutions and pixel clock frequencies.
-- For example: MMCM_FVCOMIN = 600 MHz
-- MMCM_FVCOMAX = 1200 MHz for Artix-7 -1 speed grade
-- while FVCO = FIN * MULT_F
-- The TMDS Clk for 720p resolution in 74.25 MHz
-- FVCO = 74.25 * 10 = 742.5 MHz, which is between FVCOMIN and FVCOMAX
-- However, the TMDS Clk for 1080p resolution in 148.5 MHz
-- FVCO = 148.5 * 10 = 1480 MHZ, which is above FVCOMAX
-- In the latter case, MULT_F = 5, DIVIDE_F = 5, DIVIDE = 1 would result
-- in a correct VCO frequency, while still generating 5x and 1x clocks
-- 2. The MMCM+BUFIO+BUFR combination results in the highest possible
-- frequencies. PLLE2_ADV could work only with BUFGs, which limits
-- the maximum achievable frequency. The reason is that only the MMCM
-- has dedicated route to BUFIO.
-- If a PLLE2_ADV with BUFGs are used a second CLKOUTx can be used to
-- generate the 1x clock.
GenMMCM: if kClkPrimitive = "MMCM" generate
DVI_ClkGenerator: MMCME2_ADV
generic map
(BANDWIDTH => "OPTIMIZED",
CLKOUT4_CASCADE => FALSE,
COMPENSATION => "ZHOLD",
STARTUP_WAIT => FALSE,
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT_F => real(kClkRange) * 5.0,
CLKFBOUT_PHASE => 0.000,
CLKFBOUT_USE_FINE_PS => FALSE,
CLKOUT0_DIVIDE_F => real(kClkRange) * 1.0,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT0_USE_FINE_PS => FALSE,
CLKOUT1_DIVIDE => kClkRange * 5,
CLKOUT1_DUTY_CYCLE => 0.5,
CLKOUT1_PHASE => 0.0,
CLKOUT1_USE_FINE_PS => FALSE,
CLKIN1_PERIOD => real(kClkRange) * 6.0,
REF_JITTER1 => 0.010)
port map
-- Output clocks
(
CLKFBOUT => FeedbackClk,
CLKFBOUTB => open,
CLKOUT0 => PixelClkInX5,
CLKOUT0B => open,
CLKOUT1 => PixelClkInX1,
CLKOUT1B => open,
CLKOUT2 => open,
CLKOUT2B => open,
CLKOUT3 => open,
CLKOUT3B => open,
CLKOUT4 => open,
CLKOUT5 => open,
CLKOUT6 => open,
-- Input clock control
CLKFBIN => FeedbackClk,
CLKIN1 => PixelClkIn,
CLKIN2 => '0',
-- Tied to always select the primary input clock
CLKINSEL => '1',
-- Ports for dynamic reconfiguration
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DO => open,
DRDY => open,
DWE => '0',
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => aLocked_int,
CLKINSTOPPED => open,
CLKFBSTOPPED => open,
PWRDWN => '0',
RST => pLockWasLost);
end generate;
GenPLL: if kClkPrimitive /= "MMCM" generate
DVI_ClkGenerator: PLLE2_ADV
generic map (
BANDWIDTH => "OPTIMIZED",
CLKFBOUT_MULT => (kClkRange + 1) * 5,
CLKFBOUT_PHASE => 0.000,
CLKIN1_PERIOD => real(kClkRange) * 6.25,
COMPENSATION => "ZHOLD",
DIVCLK_DIVIDE => 1,
REF_JITTER1 => 0.010,
STARTUP_WAIT => "FALSE",
CLKOUT0_DIVIDE => (kClkRange + 1) * 1,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => (kClkRange + 1) * 5,
CLKOUT1_DUTY_CYCLE => 0.5,
CLKOUT1_PHASE => 0.0)
port map
-- Output clocks
(
CLKFBOUT => FeedbackClk,
CLKOUT0 => PixelClkInX5,
CLKOUT1 => PixelClkInX1,
CLKOUT2 => open,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
-- Input clock control
CLKFBIN => FeedbackClk,
CLKIN1 => PixelClkIn,
CLKIN2 => '0',
-- Tied to always select the primary input clock
CLKINSEL => '1',
-- Ports for dynamic reconfiguration
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DO => open,
DRDY => open,
DWE => '0',
-- Other control and status signals
LOCKED => aLocked_int,
PWRDWN => '0',
RST => pLockWasLost);
end generate;
--No buffering used
--These clocks will only drive the OSERDESE2 primitives
SerialClk <= PixelClkInX5;
PixelClkOut <= PixelClkInX1;
aLocked <= aLocked_int;
end Behavioral;
|
bsd-3-clause
|
schelleg/pynq_tutorial
|
Pynq-Z1/vivado/pynq_tutorial/ip/dvi2rgb_v1_6/src/DVI_Constants.vhd
|
26
|
3151
|
-------------------------------------------------------------------------------
--
-- File: DVI_Constants.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 8 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This package defines constants/parameters taken from the DVI specs.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
package DVI_Constants is
-- DVI Control Tokens
constant kCtlTkn0 : std_logic_vector(9 downto 0) := "1101010100";
constant kCtlTkn1 : std_logic_vector(9 downto 0) := "0010101011";
constant kCtlTkn2 : std_logic_vector(9 downto 0) := "0101010100";
constant kCtlTkn3 : std_logic_vector(9 downto 0) := "1010101011";
constant kMinTknCntForBlank : natural := 128; --tB
constant kBlankTimeoutMs : natural := 50;
end DVI_Constants;
package body DVI_Constants is
end DVI_Constants;
|
bsd-3-clause
|
INTI-CMNB-FPGA/fpga_examples
|
examples/xilinx_ml605/mmcm/top.vhdl
|
1
|
1873
|
--
-- Mixed-Mode Clock Manager on ml605
--
-- To Do
--
-- Author(s):
-- * Rodrigo A. Melo
--
-- Copyright (c) 2016 Authors and INTI
-- Distributed under the BSD 3-Clause License
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library FPGALIB;
use FPGALIB.verif.all;
entity Top is
port (
clk_p_i : in std_logic;
clk_n_i : in std_logic;
rst_i : in std_logic;
leds_o : out std_logic_vector(5 downto 0)
);
end entity Top;
architecture RTL of Top is
signal blink_reset, locked : std_logic;
signal clk50, clk100, clk150, clk200, clk250, clk300 : std_logic;
begin
mmcm_inst: entity work.mmcm
port map (
-- Clock in ports
CLK_IN1_P => clk_p_i,
CLK_IN1_N => clk_n_i,
-- Clock out ports
CLK_OUT1 => clk50,
CLK_OUT2 => clk100,
CLK_OUT3 => clk150,
CLK_OUT4 => clk200,
CLK_OUT5 => clk250,
CLK_OUT6 => clk300,
-- Status and control signals
RESET => rst_i,
LOCKED => locked
);
blink_reset <= not(locked);
blink50_inst: Blink
generic map (FREQUENCY => 50e6)
port map(clk_i => clk50, rst_i => blink_reset, blink_o => leds_o(0));
blink100_inst: Blink
generic map (FREQUENCY => 100e6)
port map(clk_i => clk100, rst_i => blink_reset, blink_o => leds_o(1));
blink150_inst: Blink
generic map (FREQUENCY => 150e6)
port map(clk_i => clk150, rst_i => blink_reset, blink_o => leds_o(2));
blink200_inst: Blink
generic map (FREQUENCY => 200e6)
port map(clk_i => clk200, rst_i => blink_reset, blink_o => leds_o(3));
blink250_inst: Blink
generic map (FREQUENCY => 250e6)
port map(clk_i => clk250, rst_i => blink_reset, blink_o => leds_o(4));
blink300_inst: Blink
generic map (FREQUENCY => 300e6)
port map(clk_i => clk300, rst_i => blink_reset, blink_o => leds_o(5));
end architecture RTL;
|
bsd-3-clause
|
jjatria/ace
|
demo/kitchen-sink/docs/vhdl.vhd
|
472
|
830
|
library IEEE
user IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity COUNT16 is
port (
cOut :out std_logic_vector(15 downto 0); -- counter output
clkEn :in std_logic; -- count enable
clk :in std_logic; -- clock input
rst :in std_logic -- reset input
);
end entity;
architecture count_rtl of COUNT16 is
signal count :std_logic_vector (15 downto 0);
begin
process (clk, rst) begin
if(rst = '1') then
count <= (others=>'0');
elsif(rising_edge(clk)) then
if(clkEn = '1') then
count <= count + 1;
end if;
end if;
end process;
cOut <= count;
end architecture;
|
bsd-3-clause
|
INTI-CMNB-FPGA/fpga_examples
|
examples/avnet_s6micro/clock/top.vhdl
|
1
|
1700
|
--
-- Clocks on s5micro
--
-- There are four clock sources on s6micro board:
-- * 3 are user programmable. Default values:
-- * 1 Optional user installable of 66 MHz (not installed)
-- They are used to blink user leds.
-- The clock of 40 MHz (programmable) is used to blink LEDs 0.
-- The clock of 66.7 MHz (programmable) is used to blink LEDs 1.
-- The clock of 100 MHz (programmable) is used to blink LEDs 2.
-- The clock of 66.7 MHz (Fixed) is used to blink LEDs 3.
-- CPU_RESET push-button is used to stop and restart blink cycle.
--
-- Author(s):
-- * Rodrigo A. Melo
--
-- Copyright (c) 2017 Authors and INTI
-- Distributed under the BSD 3-Clause License
--
library IEEE;
use IEEE.std_logic_1164.all;
library FPGALIB;
use FPGALIB.verif.all;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Top is
port (
clk_i : in std_logic;
clk2_i : in std_logic;
clk3_i : in std_logic;
clk4_i : in std_logic;
rst_i : in std_logic;
leds_o : out std_logic_vector(3 downto 0)
);
end entity Top;
architecture RTL of Top is
signal led0, led1, led2, led3 : std_logic;
begin
blink40prog_inst: Blink
generic map (FREQUENCY => 40e6)
port map(clk_i => clk_i, rst_i => rst_i, blink_o => led0);
blink66prog_inst: Blink
generic map (FREQUENCY => 66700e3)
port map(clk_i => clk2_i, rst_i => rst_i, blink_o => led1);
blink100prog_inst: Blink
generic map (FREQUENCY => 100e6)
port map(clk_i => clk3_i, rst_i => rst_i, blink_o => led2);
blink66fixed_inst: Blink
generic map (FREQUENCY => 66700e3)
port map(clk_i => clk4_i, rst_i => rst_i, blink_o => led3);
leds_o <= led3 & led2 & led1 & led0;
end architecture RTL;
|
bsd-3-clause
|
INTI-CMNB-FPGA/fpga_examples
|
examples/xilinx_zc706/gtx/testbench/top_tb.vhdl
|
1
|
1365
|
--
-- Xilinx ml605 Minimal Transceiver Testbench
--
-- Author:
-- * Rodrigo A. Melo
--
-- Copyright (c) 2017 INTI
-- Distributed under the BSD 3-Clause License
--
library IEEE;
use IEEE.std_logic_1164.all;
library FPGALIB;
use FPGALIB.Simul.all;
entity Top_tb is
end entity Top_tb;
architecture Structural of Top_tb is
constant GTXPERIOD : time := 5 ns;
constant SYSPERIOD : time := 6.25 ns;
signal gtxclkn, gtxclkp : std_logic;
signal sysclkn, sysclkp : std_logic;
signal stop : boolean;
signal dips, leds : std_logic_vector(3 downto 0);
signal txp, txn, rxn, rxp : std_logic;
begin
gtxclk_i : Clock
generic map(PERIOD => GTXPERIOD, RESET_CLKS => 15.0)
port map(clk_o => gtxclkp, rst_o => open, stop_i => stop);
sysclk_i : Clock
generic map(PERIOD => SYSPERIOD, RESET_CLKS => 15.0)
port map(clk_o => sysclkp, rst_o => open, stop_i => stop);
gtxclkn <= not(gtxclkp);
sysclkn <= not(sysclkp);
dut: entity work.top
port map(
sysclk_p_i => sysclkp,
sysclk_n_i => sysclkn,
gtxclk_p_i => gtxclkp,
gtxclk_n_i => gtxclkn,
rx_p_i => '0',
rx_n_i => '0',
tx_p_o => open,
tx_n_o => open,
pbc_i => '0',
dips_i => "1010",
leds_o => open
);
end architecture Structural;
|
bsd-3-clause
|
INTI-CMNB-FPGA/fpga_examples
|
examples/xilinx_ml605/gtx/wrapper.vhdl
|
1
|
3361
|
--
-- Wrapper of gtx example
--
-- Author:
-- * Rodrigo A. Melo, [email protected]
--
-- Copyright (c) 2016 Authors and INTI
-- Distributed under the BSD 3-Clause License
--
library IEEE;
use IEEE.std_logic_1164.all;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Wrapper is
port (
clk_i : in std_logic;
rst_i : in std_logic;
clk_o : out std_logic;
--
rxp_i : in std_logic;
rxn_i : in std_logic;
txp_o : out std_logic;
txn_o : out std_logic;
--
loopback_i: in std_logic;
rx_data_o : out std_logic_vector(15 downto 0);
rx_isk_o : out std_logic_vector(1 downto 0);
tx_data_i : in std_logic_vector(15 downto 0);
tx_isk_i : in std_logic_vector(1 downto 0);
ready_o : out std_logic
);
end entity Wrapper;
architecture Structural of Wrapper is
signal refclk : std_logic_vector(1 downto 0);
signal outclk : std_logic;
signal rx_plllkdet : std_logic;
signal usrclk2 : std_logic;
signal rx_ready, tx_ready : std_logic;
signal loopback : std_logic_vector(2 downto 0);
begin
txoutclk_bufg0_i : BUFG
port map (
I => outclk,
O => usrclk2
);
refclk <= '0' & clk_i;
loopback <= '0' & loopback_i & '0';
gtx_v6_i : entity work.gbt1_gtx
generic map (
GTX_SIM_GTXRESET_SPEEDUP => 1,
GTX_TX_CLK_SOURCE => "RXPLL",
GTX_POWER_SAVE => "0000110100"
)
port map (
LOOPBACK_IN => loopback, -- Near-End PMA Loopback
-- RX 8b10b Decoder
RXCHARISK_OUT => rx_isk_o,
RXDISPERR_OUT => open,
RXNOTINTABLE_OUT => open,
-- RX Comma Detection and Alignment
RXBYTEISALIGNED_OUT => open,
RXENMCOMMAALIGN_IN => '1',
RXENPCOMMAALIGN_IN => '1',
-- RX Data Path interface
RXDATA_OUT => rx_data_o,
RXUSRCLK2_IN => usrclk2,
-- RX Driver
RXN_IN => rxn_i,
RXP_IN => rxp_i,
-- RX PLL Ports
GTXRXRESET_IN => rst_i,
MGTREFCLKRX_IN => refclk,
PLLRXRESET_IN => '0',
RXPLLLKDET_OUT => rx_plllkdet,
RXRESETDONE_OUT => rx_ready,
-- TX 8b10b Encoder Control Ports
TXCHARISK_IN => tx_isk_i,
-- TX Data Path interface
TXDATA_IN => tx_data_i,
TXOUTCLK_OUT => outclk,
TXUSRCLK2_IN => usrclk2,
-- TX Driver
TXN_OUT => txn_o,
TXP_OUT => txp_o,
TXPOSTEMPHASIS_IN => "00000",
TXPREEMPHASIS_IN => "0000",
-- TX PLL Ports
GTXTXRESET_IN => rst_i,
MGTREFCLKTX_IN => refclk,
PLLTXRESET_IN => '0',
TXPLLLKDET_OUT => open,
TXRESETDONE_OUT => tx_ready
);
clk_o <= usrclk2;
ready_o <= rx_ready and tx_ready and rx_plllkdet;
end architecture Structural;
|
bsd-3-clause
|
INTI-CMNB-FPGA/fpga_examples
|
examples/xilinx_ml605/gtx2/top.vhdl
|
1
|
3098
|
--
-- Top level of gtx2 example
--
-- Author:
-- * Rodrigo A. Melo
--
-- Copyright (c) 2017 Authors and INTI
-- Distributed under the BSD 3-Clause License
--
library IEEE;
use IEEE.std_logic_1164.all;
library FPGALIB;
use FPGALIB.verif.all;
use FPGALIB.sync.all;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Top is
port (
rst_i : in std_logic;
clk_p_i : in std_logic;
clk_n_i : in std_logic;
clk_o : out std_logic;
sma_rx_p_i : in std_logic;
sma_rx_n_i : in std_logic;
sma_tx_p_o : out std_logic;
sma_tx_n_o : out std_logic;
pbc_i : in std_logic;
leds_o : out std_logic_vector(7 downto 0)
);
end entity Top;
architecture RTL of top is
constant BYTES : positive:=2;
signal sysclk, clk : std_logic;
signal rst_gtx, rst_loop : std_logic;
signal locked, ready : std_logic;
signal loopback : std_logic;
-- GBT data
signal rx_data, rx_data_bound, tx_data : std_logic_vector(BYTES*8-1 downto 0);
signal rx_isk, rx_isk_bound, tx_isk : std_logic_vector(BYTES-1 downto 0);
--
signal finish : std_logic;
signal errors : std_logic_vector(4 downto 0);
begin
-- From 200 MHz differential to 150 MHz single-ended.
mmcm_inst: entity work.mmcm200to150
port map (
CLK_IN1_P => clk_p_i,
CLK_IN1_N => clk_n_i,
CLK_OUT1 => sysclk,
RESET => rst_i,
LOCKED => locked
);
rst_gtx <= not locked;
loopback <= not pbc_i;
gbt_i: entity work.Wrapper
port map (
clk_i => sysclk,
rst_i => rst_gtx,
clk_o => clk,
--
rxp_i => sma_rx_p_i,
rxn_i => sma_rx_n_i,
txp_o => sma_tx_p_o,
txn_o => sma_tx_n_o,
--
loopback_i=> loopback,
rx_data_o => rx_data,
rx_isk_o => rx_isk,
tx_data_i => tx_data,
tx_isk_i => tx_isk,
ready_o => ready
);
-- To ensure that we understand *rx_data* in the same order that *tx_data*.
bound_i: Boundary
generic map(BYTES => BYTES)
port map(
clk_i => clk,
pattern_i => (others => '1'),
comma_i => rx_isk,
data_i => rx_data,
comma_o => rx_isk_bound,
data_o => rx_data_bound
);
rst_loop <= not ready;
-- For test the loop.
loop_i: TransLoop
generic map(
TSIZE => 2048,
DBYTES => BYTES,
FSIZE => 512
)
port map(
-- TX side
tx_clk_i => clk,
tx_rst_i => rst_loop,
tx_data_i => (others => '0'),
tx_data_o => tx_data,
tx_isk_o => tx_isk,
tx_ready_i => ready,
-- RX side
rx_clk_i => clk,
rx_rst_i => rst_loop,
rx_data_i => rx_data_bound,
rx_isk_i => rx_isk_bound,
rx_errors_o => errors,
rx_finish_o => finish,
rx_cycles_o => open
);
leds_o <= finish & "00" & errors;
clk_o <= clk;
end architecture RTL;
|
bsd-3-clause
|
Khan/ace
|
demo/kitchen-sink/docs/vhdl.vhd
|
472
|
830
|
library IEEE
user IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity COUNT16 is
port (
cOut :out std_logic_vector(15 downto 0); -- counter output
clkEn :in std_logic; -- count enable
clk :in std_logic; -- clock input
rst :in std_logic -- reset input
);
end entity;
architecture count_rtl of COUNT16 is
signal count :std_logic_vector (15 downto 0);
begin
process (clk, rst) begin
if(rst = '1') then
count <= (others=>'0');
elsif(rising_edge(clk)) then
if(clkEn = '1') then
count <= count + 1;
end if;
end if;
end process;
cOut <= count;
end architecture;
|
bsd-3-clause
|
8l/freezing-spice
|
src/decode.vhd
|
2
|
8974
|
library ieee;
use ieee.std_logic_1164.all;
use work.common.all;
use work.decode_pkg.all;
entity decoder is
port (insn : in word;
decoded : inout decoded_t); -- decoded data
end entity decoder;
architecture behavioral of decoder is
-- Enumerated types
type imm_type_t is (IMM_NONE, IMM_I, IMM_S, IMM_B, IMM_U, IMM_J);
begin -- architecture behavioral
-- purpose: decode the RISCV instruction
-- type : combinational
-- inputs : insn
-- outputs: decode
decode_proc : process (insn) is
variable opcode : std_logic_vector(6 downto 0);
variable funct3 : std_logic_vector(2 downto 0);
variable imm_type : imm_type_t := IMM_NONE;
begin -- process decode_proc
-- defaults & important fields
opcode := insn(6 downto 0);
funct3 := insn(14 downto 12);
decoded.rs1 <= insn(19 downto 15);
decoded.rs2 <= insn(24 downto 20);
decoded.rd <= insn(11 downto 7);
decoded.opcode <= opcode;
decoded.rs1_rd <= '0';
decoded.rs2_rd <= '0';
decoded.alu_func <= ALU_NONE;
decoded.op2_src <= '0';
decoded.insn_type <= OP_ILLEGAL;
decoded.load_type <= LOAD_NONE;
decoded.store_type <= STORE_NONE;
decoded.imm <= (others => '0');
decoded.rs1_rd <= '0';
decoded.rs2_rd <= '0';
decoded.use_imm <= '0';
decoded.branch_type <= BRANCH_NONE;
case (opcode) is
-- Load Upper Immediate
when c_op_lui =>
decoded.insn_type <= OP_LUI;
imm_type := IMM_U;
-- Add Upper Immediate to PC
when c_op_auipc =>
decoded.insn_type <= OP_AUIPC;
imm_type := IMM_U;
-- Jump And Link
when c_op_jal =>
decoded.insn_type <= OP_JAL;
decoded.alu_func <= ALU_ADD;
imm_type := IMM_J;
-- Jump And Link Register
when c_op_jalr =>
decoded.insn_type <= OP_JALR;
decoded.alu_func <= ALU_ADD;
imm_type := IMM_I;
decoded.rs1_rd <= '1';
-- Branch to target address, if condition is met
when c_op_branch =>
decoded.insn_type <= OP_BRANCH;
decoded.alu_func <= ALU_ADD;
imm_type := IMM_B;
decoded.rs1_rd <= '1';
decoded.rs2_rd <= '1';
case (funct3) is
when "000" => decoded.branch_type <= BEQ;
when "001" => decoded.branch_type <= BNE;
when "100" => decoded.branch_type <= BLT;
when "101" => decoded.branch_type <= BGE;
when "110" => decoded.branch_type <= BLTU;
when "111" => decoded.branch_type <= BGEU;
when others => null;
end case;
-- load data from memory
when c_op_load =>
decoded.insn_type <= OP_LOAD;
imm_type := IMM_I;
decoded.rs1_rd <= '1';
case (funct3) is
when "000" => decoded.load_type <= LB;
when "001" => decoded.load_type <= LH;
when "010" => decoded.load_type <= LW;
when "100" => decoded.load_type <= LBU;
when "101" => decoded.load_type <= LHU;
when others => null;
end case;
-- store data to memory
when c_op_store =>
decoded.insn_type <= OP_STORE;
imm_type := IMM_S;
decoded.rs1_rd <= '1';
decoded.rs2_rd <= '1';
case (funct3) is
when "000" => decoded.store_type <= SB;
when "001" => decoded.store_type <= SH;
when "010" => decoded.store_type <= SW;
when others => null;
end case;
-- perform computation with immediate value and a register
when c_op_imm =>
decoded.insn_type <= OP_ALU;
decoded.op2_src <= '1';
imm_type := IMM_I;
decoded.rs1_rd <= '1';
decoded.use_imm <= '1';
case (funct3) is
when "000" => decoded.alu_func <= ALU_ADD;
when "001" => decoded.alu_func <= ALU_SLL;
when "010" => decoded.alu_func <= ALU_SLT;
when "011" => decoded.alu_func <= ALU_SLTU;
when "100" => decoded.alu_func <= ALU_XOR;
when "110" => decoded.alu_func <= ALU_OR;
when "111" => decoded.alu_func <= ALU_AND;
when "101" =>
if (insn(30) = '1') then
decoded.alu_func <= ALU_SRA;
else
decoded.alu_func <= ALU_SRL;
end if;
when others => null;
end case;
-- perform computation with two register values
when c_op_reg =>
decoded.insn_type <= OP_ALU;
decoded.rs1_rd <= '1';
decoded.rs2_rd <= '1';
case (funct3) is
when "000" =>
if (insn(30) = '1') then
decoded.alu_func <= ALU_SUB;
else
decoded.alu_func <= ALU_ADD;
end if;
when "001" => decoded.alu_func <= ALU_SLL;
when "010" => decoded.alu_func <= ALU_SLT;
when "011" => decoded.alu_func <= ALU_SLTU;
when "100" => decoded.alu_func <= ALU_XOR;
when "101" =>
if (insn(30) = '1') then
decoded.alu_func <= ALU_SRA;
else
decoded.alu_func <= ALU_SRL;
end if;
when "110" => decoded.alu_func <= ALU_OR;
when "111" => decoded.alu_func <= ALU_AND;
when others => null;
end case;
-- @TODO other insnructions
--when c_op_misc_mem =>
-- insn_type <= OP_FENCE;
--when c_op_system =>
-- insn_type <= OP_SYSTEM;
when others =>
decoded.insn_type <= OP_ILLEGAL;
end case;
-- decode and sign-extend the immediate value
case imm_type is
when IMM_I =>
for i in 31 downto 11 loop
decoded.imm(i) <= insn(31);
end loop;
decoded.imm(10 downto 5) <= insn(30 downto 25);
decoded.imm(4 downto 1) <= insn(24 downto 21);
decoded.imm(0) <= insn(20);
when IMM_S =>
for i in 31 downto 11 loop
decoded.imm(i) <= insn(31);
end loop; -- i
decoded.imm(10 downto 5) <= insn(30 downto 25);
decoded.imm(4 downto 1) <= insn(11 downto 8);
decoded.imm(0) <= insn(7);
when IMM_B =>
for i in 31 downto 13 loop
decoded.imm(i) <= insn(31);
end loop; -- i
decoded.imm(12) <= insn(31);
decoded.imm(11) <= insn(7);
decoded.imm(10 downto 5) <= insn(30 downto 25);
decoded.imm(4 downto 1) <= insn(11 downto 8);
decoded.imm(0) <= '0';
when IMM_U =>
decoded.imm(31) <= insn(31);
decoded.imm(30 downto 20) <= insn(30 downto 20);
decoded.imm(19 downto 12) <= insn(19 downto 12);
decoded.imm(11 downto 0) <= (others => '0');
when IMM_J =>
for i in 31 downto 20 loop
decoded.imm(i) <= insn(31);
end loop; -- i
decoded.imm(19 downto 12) <= insn(19 downto 12);
decoded.imm(11) <= insn(20);
decoded.imm(10 downto 5) <= insn(30 downto 25);
decoded.imm(4 downto 1) <= insn(24 downto 21);
decoded.imm(0) <= '0';
when others => decoded.imm <= (others => '0');
end case;
end process decode_proc;
end architecture behavioral;
|
bsd-3-clause
|
trxeste/wrk
|
haskell/cl3sh/vhdl/MAC/mac_mealy.vhdl
|
1
|
1541
|
-- Automatically generated VHDL-93
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.MATH_REAL.ALL;
use std.textio.all;
use work.all;
use work.mac_types.all;
entity mac_mealy is
port(w2 : in mac_types.tup2;
-- clock
system1000 : in std_logic;
-- asynchronous reset: active low
system1000_rstn : in std_logic;
result : out signed(8 downto 0));
end;
architecture structural of mac_mealy is
signal y : signed(8 downto 0);
signal result_0 : mac_types.tup2;
signal tup_case_alt : mac_types.tup2;
signal tup_app_arg : signed(8 downto 0);
signal x : signed(8 downto 0);
signal tup_app_arg_0 : signed(8 downto 0);
signal x_app_arg : signed(8 downto 0);
signal x_0 : signed(8 downto 0);
signal y_0 : signed(8 downto 0);
signal x_1 : signed(8 downto 0);
begin
result <= y;
y <= result_0.tup2_sel1;
result_0 <= tup_case_alt;
tup_case_alt <= (tup2_sel0 => tup_app_arg
,tup2_sel1 => x);
tup_app_arg <= x + tup_app_arg_0;
-- register begin
mac_mealy_register : process(system1000,system1000_rstn)
begin
if system1000_rstn = '0' then
x <= to_signed(0,9);
elsif rising_edge(system1000) then
x <= x_app_arg;
end if;
end process;
-- register end
tup_app_arg_0 <= resize(x_0 * y_0, 9);
x_app_arg <= x_1;
x_0 <= w2.tup2_sel0;
y_0 <= w2.tup2_sel1;
x_1 <= result_0.tup2_sel0;
end;
|
bsd-3-clause
|
eamadio/fpgaMSP430
|
fmsp430/core/fmsp_execution_unit.vhd
|
1
|
25135
|
------------------------------------------------------------------------------
--! Copyright (C) 2009 , Olivier Girard
--
--! Redistribution and use in source and binary forms, with or without
--! modification, are permitted provided that the following conditions
--! are met:
--! * Redistributions of source code must retain the above copyright
--! notice, this list of conditions and the following disclaimer.
--! * Redistributions in binary form must reproduce the above copyright
--! notice, this list of conditions and the following disclaimer in the
--! documentation and/or other materials provided with the distribution.
--! * Neither the name of the authors nor the names of its contributors
--! may be used to endorse or promote products derived from this software
--! without specific prior written permission.
--
--! THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--! AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
--! IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
--! ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
--! LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
--! OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--! SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--! INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--! CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--! ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
--! THE POSSIBILITY OF SUCH DAMAGE
--
------------------------------------------------------------------------------
--
--! @file fmsp_execution_unit.vhd
--!
--! @brief fpgaMSP430 Execution unit
--
--! @author Olivier Girard, [email protected]
--! @author Emmanuel Amadio, [email protected] (VHDL Rewrite)
--
------------------------------------------------------------------------------
--! @version 1
--! @date: 2017-04-21
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.fmsp_core_package.all;
use work.fmsp_functions.all;
entity fmsp_execution_unit is
port (
mclk : in std_logic; --! Main system clock
mrst : in std_logic; --! Main system reset
--! INPUTs
dbg_halt_st : in std_logic; --! Halt/Run status from CPU
dbg_mem_dout : in std_logic_vector(15 downto 0); --! Debug unit data output
dbg_reg_wr : in std_logic; --! Debug unit CPU register write
e_state : in std_logic_vector(3 downto 0); --! Execution state
exec_done : in std_logic; --! Execution completed
inst_ad : in std_logic_vector(7 downto 0); --! Decoded Inst: destination addressing mode
inst_as : in std_logic_vector(7 downto 0); --! Decoded Inst: source addressing mode
inst_alu : in std_logic_vector(11 downto 0); --! ALU control signals
inst_bw : in std_logic; --! Decoded Inst: byte width
inst_dest : in std_logic_vector(15 downto 0); --! Decoded Inst: destination (one hot)
inst_dext : in std_logic_vector(15 downto 0); --! Decoded Inst: destination extended instruction word
inst_irq_rst : in std_logic; --! Decoded Inst: reset interrupt
inst_jmp : in std_logic_vector(7 downto 0); --! Decoded Inst: Conditional jump
inst_mov : in std_logic; --! Decoded Inst: mov instruction
inst_sext : in std_logic_vector(15 downto 0); --! Decoded Inst: source extended instruction word
inst_so : in std_logic_vector(7 downto 0); --! Decoded Inst: Single-operand arithmetic
inst_src : in std_logic_vector(15 downto 0); --! Decoded Inst: source (one hot)
inst_type : in std_logic_vector(2 downto 0); --! Decoded Instruction type
mdb_in : in std_logic_vector(15 downto 0); --! Memory data bus input
pc : in std_logic_vector(15 downto 0); --! Program counter
pc_nxt : in std_logic_vector(15 downto 0); --! Next d.pc value (for CALL & IRQ)
--! OUTPUTs
cpuoff : out std_logic; --! Turns off the CPU
dbg_reg_din : out std_logic_vector(15 downto 0); --! Debug unit CPU register data input
gie : out std_logic; --! General interrupt enable
mab : out std_logic_vector(15 downto 0); --! Memory address bus
mb_en : out std_logic; --! Memory bus enable
mb_wr : out std_logic_vector(1 downto 0); --! Memory bus write transfer
mdb_out : out std_logic_vector(15 downto 0); --! Memory data bus output
oscoff : out std_logic; --! Turns off LFXT1 clock input
pc_sw : out std_logic_vector(15 downto 0); --! Program counter software value
pc_sw_wr : out std_logic; --! Program counter software write
scg0 : out std_logic; --! System clock generator 1. Turns off te DCO
scg1 : out std_logic --! System clock generator 1. Turns off the SMCLK
);
end entity fmsp_execution_unit;
architecture RTL of fmsp_execution_unit is
type fmsp_execution_unit_in_type is record
dbg_halt_st : std_logic; --! Halt/Run status from CPU
dbg_mem_dout : std_logic_vector(15 downto 0); --! Debug unit data output
dbg_reg_wr : std_logic; --! Debug unit CPU register write
e_state : std_logic_vector(3 downto 0); --! Execution state
exec_done : std_logic; --! Execution completed
inst_ad : std_logic_vector(7 downto 0); --! Decoded Inst: destination addressing mode
inst_as : std_logic_vector(7 downto 0); --! Decoded Inst: source addressing mode
inst_alu : std_logic_vector(11 downto 0); --! ALU control signals
inst_bw : std_logic; --! Decoded Inst: byte width
inst_dest : std_logic_vector(15 downto 0); --! Decoded Inst: destination (one hot)
inst_dext : std_logic_vector(15 downto 0); --! Decoded Inst: destination extended instruction word
inst_irq_rst : std_logic; --! Decoded Inst: reset interrupt
inst_jmp : std_logic_vector(7 downto 0); --! Decoded Inst: Conditional jump
inst_mov : std_logic; --! Decoded Inst: mov instruction
inst_sext : std_logic_vector(15 downto 0); --! Decoded Inst: source extended instruction word
inst_so : std_logic_vector(7 downto 0); --! Decoded Inst: Single-operand arithmetic
inst_src : std_logic_vector(15 downto 0); --! Decoded Inst: source (one hot)
inst_type : std_logic_vector(2 downto 0); --! Decoded Instruction type
mdb_in : std_logic_vector(15 downto 0); --! Memory data bus input
pc : std_logic_vector(15 downto 0); --! Program counter
pc_nxt : std_logic_vector(15 downto 0); --! Next pc value (for CALL & IRQ)
reg_dest : std_logic_vector(15 downto 0);
reg_src : std_logic_vector(15 downto 0);
alu_stat : std_logic_vector(3 downto 0);
alu_stat_wr : std_logic_vector(3 downto 0);
alu_out : std_logic_vector(15 downto 0);
alu_out_add : std_logic_vector(15 downto 0);
end record;
type reg_type is record
mdb_out_nxt : std_logic_vector(15 downto 0); --! Memory data bus output
mab_lsb : std_logic; --! Format memory data bus input depending on BW
mdb_in_buf_en : std_logic; --! Memory data bus input buffer (buffer after a source read)
mdb_in_buf_valid : std_logic;
mdb_in_buf : std_logic_vector(15 downto 0);
end record;
signal d : fmsp_execution_unit_in_type;
signal r : reg_type := ( mdb_out_nxt => x"0000", --! Memory data bus output
mab_lsb => '0',--! Format memory data bus input depending on BW
mdb_in_buf_en => '0',--! Memory data bus input buffer (buffer after a source read)
mdb_in_buf_valid => '0',
mdb_in_buf => x"0000"
);
signal rin : reg_type;
signal reg_dest_wr : std_logic;
signal reg_sp_wr : std_logic;
signal reg_sr_wr : std_logic;
signal reg_sr_clr : std_logic;
signal reg_pc_call : std_logic;
signal reg_incr : std_logic;
signal exec_cycle : std_logic;
signal status : std_logic_vector(3 downto 0);
signal op_dst : std_logic_vector(15 downto 0);
signal op_src : std_logic_vector(15 downto 0);
begin
d.dbg_halt_st <= dbg_halt_st;
d.dbg_mem_dout <= dbg_mem_dout;
d.dbg_reg_wr <= dbg_reg_wr;
d.e_state <= e_state;
d.exec_done <= exec_done;
d.inst_ad <= inst_ad;
d.inst_as <= inst_as;
d.inst_alu <= inst_alu;
d.inst_bw <= inst_bw;
d.inst_dest <= inst_dest;
d.inst_dext <= inst_dext;
d.inst_irq_rst <= inst_irq_rst;
d.inst_jmp <= inst_jmp;
d.inst_mov <= inst_mov;
d.inst_sext <= inst_sext;
d.inst_so <= inst_so;
d.inst_src <= inst_src;
d.inst_type <= inst_type;
d.mdb_in <= mdb_in;
d.pc <= pc;
d.pc_nxt <= pc_nxt;
COMB : process (all)
variable v : reg_type;
variable v_alu_stat : std_logic_vector(3 downto 0);
variable v_alu_stat_wr : std_logic_vector(3 downto 0);
variable v_op_dst : std_logic_vector(15 downto 0);
variable v_op_src : std_logic_vector(15 downto 0);
variable v_status : std_logic_vector(3 downto 0);
variable v_reg_dest_wr : std_logic;
variable v_reg_sp_wr : std_logic;
variable v_reg_sr_wr : std_logic;
variable v_reg_sr_clr : std_logic;
variable v_reg_pc_call : std_logic;
variable v_reg_incr : std_logic;
variable v_dbg_reg_din : std_logic_vector(15 downto 0);
variable v_src_reg_src_sel : std_logic;
variable v_src_reg_dest_sel : std_logic;
variable v_src_mdb_in_val_sel : std_logic;
variable v_src_inst_dext_sel : std_logic;
variable v_src_inst_sext_sel : std_logic;
variable v_dst_inst_sext_sel : std_logic;
variable v_dst_mdb_in_bw_sel : std_logic;
variable v_dst_fffe_sel : std_logic;
variable v_dst_reg_dest_sel : std_logic;
variable v_exec_cycle : std_logic;
--! Detect memory read/write access
variable v_mb_wr_det : std_logic;
variable v_mb_rd_det : std_logic;
variable v_mb_en : std_logic;
variable v_mb_wr_msk : std_logic_vector(1 downto 0);
variable v_mb_wr : std_logic_vector(1 downto 0);
--! Memory address bus
variable v_mab : std_logic_vector(15 downto 0);
variable v_mdb_out : std_logic_vector(15 downto 0);
variable v_mdb_in_bw : std_logic_vector(15 downto 0);
variable v_mdb_in_val : std_logic_vector(15 downto 0);
begin
--! default assignment
v := r;
--! overriding assignments
--=============================================================================
--! 2) REGISTER FILE
--=============================================================================
if ( ((d.e_state = E_EXEC) and (
((d.inst_type(C_INST_TO) = '1') and (d.inst_ad(C_DIR) = '1') and not (d.inst_alu(C_EXEC_NO_WR) = '1')) or
((d.inst_type(C_INST_SO) = '1') and (d.inst_as(C_DIR) = '1') and not ((d.inst_so(C_PUSH) = '1') or (d.inst_so(C_CALL) = '1') or (d.inst_so(C_RETI) = '1') )) or
(d.inst_type(C_INST_JMP) = '1'))) or (d.dbg_reg_wr = '1') ) then
v_reg_dest_wr := '1';
else
v_reg_dest_wr:= '0';
end if;
if ( ( ( (d.e_state = E_IRQ_1)
or (d.e_state = E_IRQ_3) )
and (not(d.inst_irq_rst) = '1') )
or ( (d.e_state = E_DST_RD)
and ( (d.inst_so(C_PUSH) = '1') or (d.inst_so(C_CALL) = '1') )
and (not(d.inst_as(C_IDX)) = '1')
and not( ( (d.inst_as(C_INDIR) = '1') or (d.inst_as(C_INDIR_I) = '1') ) and (d.inst_src(1) = '1') ) )
or ( (d.e_state = E_SRC_AD)
and ( (d.inst_so(C_PUSH) = '1') or (d.inst_so(C_CALL) = '1') )
and (d.inst_as(C_IDX) = '1') )
or ( (d.e_state = E_SRC_RD)
and ( (d.inst_so(C_PUSH) = '1') or (d.inst_so(C_CALL) = '1') )
and ( ((d.inst_as(C_INDIR) = '1') or (d.inst_as(C_INDIR_I) = '1')) and (d.inst_src(1) = '1') ) ) ) then
v_reg_sp_wr := '1';
else
v_reg_sp_wr := '0';
end if;
if ( (d.e_state = E_DST_RD) and (d.inst_so(C_RETI) = '1') ) then
v_reg_sr_wr := '1';
else
v_reg_sr_wr := '0';
end if;
if ( (d.e_state = E_IRQ_2) ) then
v_reg_sr_clr := '1';
else
v_reg_sr_clr := '0';
end if;
if ( ((d.e_state = E_EXEC) and (d.inst_so(C_CALL) = '1')) or
((d.e_state = E_DST_WR) and (d.inst_so(C_RETI) = '1')) ) then
v_reg_pc_call := '1';
else
v_reg_pc_call := '0';
end if;
if ( ((d.exec_done = '1') and (d.inst_as(C_INDIR_I) = '1')) or
((d.e_state = E_SRC_RD) and (d.inst_so(C_RETI) = '1')) or
((d.e_state = E_EXEC) and (d.inst_so(C_RETI) = '1')) ) then
v_reg_incr := '1';
else
v_reg_incr := '0';
end if;
v_dbg_reg_din := d.reg_dest;
--=============================================================================
--! 3) SOURCE OPERAND MUXING
--=============================================================================
--! d.inst_as(C_DIR) = '1') : Register direct. -> Source is in register
--! d.inst_as(C_IDX) = '1') : Register indexed. -> Source is in memory, address is register+offset
--! d.inst_as(C_INDIR) = '1') : Register indirect.
--! d.inst_as(C_INDIR_I) = '1'): Register indirect autoincrement.
--! d.inst_as(C_SYMB) = '1') : Symbolic (operand is in memory at address d.pc+x).
--! d.inst_as(C_IMM) = '1') : Immediate (operand is next word in the instruction stream).
--! d.inst_as(C_ABS) = '1') : Absolute (operand is in memory at address x).
--! d.inst_as(C_CONST) = '1') : Constant.
if ( ( (d.e_state = E_IRQ_0) or (d.e_state = E_IRQ_2) )
or ( (d.e_state = E_SRC_RD) and not(d.inst_as(C_ABS) = '1') )
or ( (d.e_state = E_SRC_WR) and not(d.inst_as(C_ABS) = '1') )
or ( (d.e_state = E_EXEC) and (d.inst_as(C_DIR) = '1') and not(d.inst_type(C_INST_JMP) = '1') ) ) then
v_src_reg_src_sel := '1';
else
v_src_reg_src_sel := '0';
end if;
if ( ( (d.e_state = E_IRQ_1) or (d.e_state = E_IRQ_3) )
or ( (d.e_state = E_DST_RD) and ( (d.inst_so(C_PUSH) = '1') or (d.inst_so(C_CALL) = '1') ) )
or ( (d.e_state = E_SRC_AD) and ( (d.inst_so(C_PUSH) = '1') or (d.inst_so(C_CALL) = '1') ) and (d.inst_as(C_IDX) = '1') ) ) then
v_src_reg_dest_sel := '1';
else
v_src_reg_dest_sel := '0';
end if;
if ( ( (d.e_state = E_DST_RD) and (d.inst_so(C_RETI) = '1') )
or ( (d.e_state = E_EXEC) and ( (d.inst_as(C_INDIR) = '1') or (d.inst_as(C_INDIR_I) = '1')
or (d.inst_as(C_IDX) = '1') or (d.inst_as(C_SYMB) = '1')
or (d.inst_as(C_ABS) = '1') ) ) ) then
v_src_mdb_in_val_sel := '1';
else
v_src_mdb_in_val_sel := '0';
end if;
if ( ( (d.e_state = E_DST_RD) and not( (d.inst_so(C_PUSH) = '1') or (d.inst_so(C_CALL) = '1') ) )
or ( (d.e_state = E_DST_WR) and not( (d.inst_so(C_PUSH) = '1') or (d.inst_so(C_CALL) = '1')
or (d.inst_as(C_IDX) = '1') or (d.inst_as(C_SYMB) = '1')
or (d.inst_so(C_RETI) = '1') ) ) ) then
v_src_inst_dext_sel := '1';
else
v_src_inst_dext_sel := '0';
end if;
if ( (d.e_state = E_EXEC) and ( (d.inst_type(C_INST_JMP) = '1') or (d.inst_as(C_IMM) = '1') or (d.inst_as(C_CONST) = '1')
or (d.inst_so(C_RETI) = '1') ) ) then
v_src_inst_sext_sel := '1';
else
v_src_inst_sext_sel := '0';
end if;
if (v_src_reg_src_sel = '1') then
v_op_src := d.reg_src;
elsif (v_src_reg_dest_sel = '1') then
v_op_src := d.reg_dest;
elsif (v_src_mdb_in_val_sel = '1') then
v_op_src := v_mdb_in_val;
elsif (v_src_inst_dext_sel = '1') then
v_op_src := d.inst_dext;
elsif (v_src_inst_sext_sel = '1') then
v_op_src := d.inst_sext;
else
v_op_src := x"0000";
end if;
--=============================================================================
--! 4) DESTINATION OPERAND MUXING
--=============================================================================
--! d.inst_ad(C_DIR) = '1') : Register direct.
--! d.inst_ad(C_IDX) = '1') : Register indexed.
--! d.inst_ad(C_SYMB) = '1') : Symbolic (operand is in memory at address d.pc+x).
--! d.inst_ad(C_ABS) = '1') : Absolute (operand is in memory at address x).
if ( ( (d.e_state = E_SRC_RD) and ( (d.inst_as(C_IDX) = '1') or (d.inst_as(C_SYMB) = '1')
or (d.inst_as(C_ABS) = '1') ) )
or ( (d.e_state = E_SRC_RD) and ( (d.inst_as(C_IDX) = '1') or (d.inst_as(C_SYMB) = '1')
or (d.inst_as(C_ABS) = '1') ) ) ) then
v_dst_inst_sext_sel := '1';
else
v_dst_inst_sext_sel := '0';
end if;
if ( ( (d.e_state = E_DST_WR) and (d.inst_so(C_RETI) = '1') )
or ( (d.e_state = E_EXEC) and not( (d.inst_ad(C_IDX) = '1') or (d.inst_type(C_INST_JMP) = '1')
or (d.inst_type(C_INST_SO) = '1') ) and not(d.inst_so(C_RETI) = '1') ) ) then
v_dst_mdb_in_bw_sel := '1';
else
v_dst_mdb_in_bw_sel := '0';
end if;
if ( ( (d.e_state = E_IRQ_0) or (d.e_state = E_IRQ_0) or (d.e_state = E_IRQ_3) )
or ( (d.e_state = E_DST_RD) and ( (d.inst_so(C_PUSH) = '1') or (d.inst_so(C_CALL) = '1') ) and not(d.inst_so(C_RETI) = '1') )
or ( (d.e_state = E_SRC_AD) and ( (d.inst_so(C_PUSH) = '1') or (d.inst_so(C_CALL) = '1') ) and (d.inst_as(C_IDX) = '1') )
or ( (d.e_state = E_SRC_RD) and ( (d.inst_so(C_PUSH) = '1') or (d.inst_so(C_CALL) = '1') ) and ( (d.inst_as(C_INDIR) = '1') or (d.inst_as(C_INDIR_I) = '1') ) and (d.inst_src(1) = '1') ) ) then
v_dst_fffe_sel := '1';
else
v_dst_fffe_sel := '0';
end if;
if ( ( (d.e_state = E_DST_RD) and not( (d.inst_so(C_PUSH) = '1') or (d.inst_so(C_CALL) = '1') or (d.inst_ad(C_ABS) = '1') or (d.inst_so(C_RETI) = '1') ) )
or ( (d.e_state = E_DST_WR) and not(d.inst_ad(C_ABS) = '1') )
or ( (d.e_state = E_EXEC) and ( (d.inst_ad(C_DIR) = '1') or (d.inst_type(C_INST_JMP) = '1') or (d.inst_type(C_INST_SO) = '1') ) and not(d.inst_so(C_RETI) = '1') ) ) then
v_dst_reg_dest_sel := '1';
else
v_dst_reg_dest_sel := '0';
end if;
if (d.dbg_halt_st = '1') then
v_op_dst := d.dbg_mem_dout;
elsif (v_dst_inst_sext_sel = '1') then
v_op_dst := d.inst_sext;
elsif (v_dst_mdb_in_bw_sel = '1') then
v_op_dst := v_mdb_in_bw;
elsif (v_dst_reg_dest_sel = '1') then
v_op_dst := d.reg_dest;
elsif (v_dst_fffe_sel = '1') then
v_op_dst := x"FFFE";
else
v_op_dst := x"0000";
end if;
--=============================================================================
--! 5) ALU
--=============================================================================
if (d.e_state = E_EXEC) then
v_exec_cycle := '1';
else
v_exec_cycle := '0';
end if;
--=============================================================================
--! 6) MEMORY INTERFACE
--=============================================================================
--! Detect memory read/write access
if ( ( (d.e_state = E_SRC_RD) and (d.inst_as(C_IMM) = '0') )
or ( (d.e_state = E_EXEC) and (d.inst_so(C_RETI) = '0') )
or ( (d.e_state = E_SRC_RD) and (d.inst_type(C_INST_SO) = '0') and (d.inst_mov = '0') )
) then
v_mb_rd_det := '1';
else
v_mb_rd_det := '0';
end if;
--! Detect memory read/write access
if ( ( (d.e_state = E_IRQ_1) and (not(d.inst_irq_rst) = '0') )
or ( (d.e_state = E_IRQ_3) and (not(d.inst_irq_rst) = '0') )
or ( (d.e_state = E_DST_WR) and (not(d.inst_so(C_RETI)) = '0') )
or (d.e_state = E_SRC_WR) ) then
v_mb_wr_det := '1';
else
v_mb_wr_det := '0';
end if;
if (d.inst_alu(C_EXEC_NO_WR) = '1') then
v_mb_wr_msk := "00";
elsif (d.inst_bw = '0') then
v_mb_wr_msk := "11";
elsif (d.alu_out_add(0) = '1') then
v_mb_wr_msk := "10";
else
v_mb_wr_msk := "01";
end if;
if ( ( (not(d.inst_alu(C_EXEC_NO_WR)) = '1') and (v_mb_wr_det= '1') )
or (v_mb_rd_det= '1')
) then
v_mb_en := '1';
else
v_mb_en := '0';
end if;
if (v_mb_wr_det = '1') then
v_mb_wr := v_mb_wr_msk;
else
v_mb_wr := "00";
end if;
--! Memory address bus
v_mab := d.alu_out_add;
--! Memory data bus output
if (d.e_state = E_DST_RD) then
v.mdb_out_nxt := d.pc_nxt;
elsif ( ( (d.e_state = E_EXEC) and (not(d.inst_so(C_CALL)) = '1') )
or (d.e_state = E_IRQ_0) or (d.e_state = E_IRQ_2) ) then
v.mdb_out_nxt := d.alu_out;
end if;
if (d.inst_bw = '1') then
v_mdb_out := r.mdb_out_nxt(7 downto 0) & r.mdb_out_nxt(7 downto 0);
else
v_mdb_out := r.mdb_out_nxt;
end if;
--! Format memory data bus input depending on BW
if (v_mb_en = '1') then
v.mab_lsb := d.alu_out_add(0);
end if;
if (not(d.inst_bw) = '1') then
v_mdb_in_bw := d.mdb_in;
elsif (r.mab_lsb = '1') then
v_mdb_in_bw := d.mdb_in(15 downto 8) & d.mdb_in(15 downto 8);
else
v_mdb_in_bw := d.mdb_in;
end if;
--! Memory data bus input buffer (buffer after a source read)
if (d.e_state = E_SRC_RD) then
v.mdb_in_buf_en := '1';
else
v.mdb_in_buf_en := '0';
end if;
if (d.e_state = E_EXEC) then
v.mdb_in_buf_valid := '0';
elsif (r.mdb_in_buf_en) then
v.mdb_in_buf_valid := '1';
end if;
if (r.mdb_in_buf_en = '1') then
v.mdb_in_buf := v_mdb_in_bw;
end if;
if (r.mdb_in_buf_valid = '1') then
v_mdb_in_val := r.mdb_in_buf;
else
v_mdb_in_val := v_mdb_in_bw;
end if;
--! drive register inputs
rin <= v;
--! drive module outputs
reg_dest_wr <= v_reg_dest_wr;
reg_sp_wr <= v_reg_sp_wr;
reg_sr_wr <= v_reg_sr_wr;
reg_sr_clr <= v_reg_sr_clr;
reg_pc_call <= v_reg_pc_call;
reg_incr <= v_reg_incr;
exec_cycle <= v_exec_cycle;
-- signal status : std_logic_vector(3 downto 0);
op_dst <= v_op_dst;
op_src <= v_op_src;
--! OUTPUTs
-- cpuoff : out std_logic; --! Turns off the CPU
dbg_reg_din <= v_dbg_reg_din; --! Debug unit CPU register data input
-- gie : out std_logic; --! General interrupt enable
mab <= v_mab; --! Memory address bus
mb_en <= v_mb_en; --! Memory bus enable
mb_wr <= v_mb_wr; --! Memory bus write transfer
mdb_out <= v_mdb_out; --! Memory data bus output
-- oscoff : out std_logic; --! Turns off LFXT1 clock input
-- pc_sw <= v_dbg_reg_di; --! Program counter software value
-- pc_sw_wr <= v_dbg_reg_di; --! Program counter software write
-- scg0 : out std_logic; --! System clock generator 1. Turns off hte DCO
-- scg1 : out std_logic; --! System clock generator 1. Turns off the SMCLK
end process COMB;
REGS : process (mclk,mrst)
begin
if (mrst = '1') then
r <= ( mdb_out_nxt => x"0000", --! Memory data bus output
mab_lsb => '0',--! Format memory data bus input depending on BW
mdb_in_buf_en => '0',--! Memory data bus input buffer (buffer after a source read)
mdb_in_buf_valid => '0',
mdb_in_buf => x"0000"
);
elsif rising_edge(mclk) then
r <= rin;
end if;
end process REGS;
register_file : fmsp_register_file
port map(
mclk => mclk, --! Main system clock
mrst => mrst, --! Main system reset
--! INPUTs
alu_stat => d.alu_stat, --! ALU Status {V,N,Z,C}
alu_stat_wr => d.alu_stat_wr, --! ALU Status write {V,N,Z,C}
inst_bw => d.inst_bw, --! Decoded Inst: byte width
inst_dest => d.inst_dest, --! Register destination selection
inst_src => d.inst_src, --! Register source selection
pc => d.pc, --! Program counter
reg_dest_val => d.alu_out, --! Selected register destination value
reg_dest_wr => reg_dest_wr, --! Write selected register destination
reg_pc_call => reg_pc_call, --! Trigger pc update for a CALL instruction
reg_sp_val => d.alu_out_add, --! Stack Pointer next value
reg_sp_wr => reg_sp_wr, --! Stack Pointer write
reg_sr_clr => reg_sr_clr, --! Status register clear for interrupts
reg_sr_wr => reg_sr_wr, --! Status Register update for RETI instruction
reg_incr => reg_incr, --! Increment source register
--! OUTPUTs
cpuoff => cpuoff, --! Turns off the CPU
gie => gie, --! General interrupt enable
oscoff => oscoff, --! Turns off LFXT1 clock input
pc_sw => pc_sw, --! Program counter software value
pc_sw_wr => pc_sw_wr, --! Program counter software write
reg_dest => d.reg_dest, --! Selected register destination content
reg_src => d.reg_src, --! Selected register source content
scg0 => scg0, --! System clock generator 1. Turns off the DCOK
scg1 => scg1, --! System clock generator 1. Turns off the SMCLK
status => status --! R2 Status {V,N,Z,C}
);
alu : fmsp_alu
port map(
--! INPUTs
dbg_halt_st => d.dbg_halt_st, --! Halt/Run status from CPU
exec_cycle => exec_cycle, --! Instruction execution cycle
inst_alu => d.inst_alu, --! ALU control signals
inst_bw => d.inst_bw, --! Decoded Inst: byte width
inst_jmp => d.inst_jmp, --! Decoded Inst: Conditional jump
inst_so => d.inst_so, --! Single-operand arithmetic
op_dst => op_dst, --! Destination operand
op_src => op_src, --! Source operand
status => status, --! R2 Status {V,N,Z,C}
--! OUTPUTs
alu_out => d.alu_out, --! ALU output value
alu_out_add => d.alu_out_add, --! ALU adder output value
alu_stat => d.alu_stat, --! ALU Status {V,N,Z,C}
alu_stat_wr => d.alu_stat_wr --! ALU Status write {V,N,Z,C}
);
end RTL;
|
bsd-3-clause
|
eamadio/fpgaMSP430
|
fmsp430/dbg/fmsp_dbg.vhd
|
1
|
44946
|
------------------------------------------------------------------------------
--! Copyright (C) 2009 , Olivier Girard
--
--! Redistribution and use in source and binary forms, with or without
--! modification, are permitted provided that the following conditions
--! are met:
--! * Redistributions of source code must retain the above copyright
--! notice, this list of conditions and the following disclaimer.
--! * Redistributions in binary form must reproduce the above copyright
--! notice, this list of conditions and the following disclaimer in the
--! documentation and/or other materials provided with the distribution.
--! * Neither the name of the authors nor the names of its contributors
--! may be used to endorse or promote products derived from this software
--! without specific prior written permission.
--
--! THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--! AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
--! IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
--! ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
--! LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
--! OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--! SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--! INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--! CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--! ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
--! THE POSSIBILITY OF SUCH DAMAGE
--
------------------------------------------------------------------------------
--
--! @file fmsp_dbg.vhd
--!
--! @brief fpgaMSP430 Debug interface
--
--! @author Olivier Girard, [email protected]
--! @author Emmanuel Amadio, [email protected] (VHDL Rewrite)
--
------------------------------------------------------------------------------
--! @version 1
--! @date: 2017-04-21
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all; --! standard unresolved logic UX01ZWLH-
use ieee.numeric_std.all; --! for the signed, unsigned types and arithmetic ops
use work.fmsp_functions.all;
use work.fmsp_dbg_package.all;
entity fmsp_dbg is
generic (
DBG_UART : boolean := false; --! Enable UART (8N1) debug interface
DBG_I2C : boolean := true; --! Enable I2C debug interface
DBG_I2C_BROADCAST_EN : boolean := false; --! Enable the I2C broadcast address
DBG_RST_BRK_EN : boolean := false; --! CPU break on PUC reset
DBG_HWBRK_0_EN : boolean := false; --! Include hardware breakpoints unit
DBG_HWBRK_1_EN : boolean := false; --! Include hardware breakpoints unit
DBG_HWBRK_2_EN : boolean := false; --! Include hardware breakpoints unit
DBG_HWBRK_3_EN : boolean := false; --! Include hardware breakpoints unit
DBG_HWBRK_RANGE : boolean := true; --! Enable/Disable the hardware breakpoint RANGE mode
DBG_UART_AUTO_SYNC : boolean := true; --! Debug UART interface auto data synchronization
DBG_UART_BAUD : integer := 9600; --! Debug UART interface data rate
DBG_DCO_FREQ : integer := 20000000; --! Debug DCO_CLK frequency
SYNC_DBG_UART_RXD : boolean := true --! Synchronize RXD inputs
);
port (
dbg_clk : in std_logic; --! Debug unit clock
dbg_rst : in std_logic; --! Debug unit reset
--! INPUTs
cpu_en_s : in std_logic; --! Enable CPU code execution (synchronous)
cpu_id : in std_logic_vector(31 downto 0); --! CPU ID
cpu_nr_inst : in std_logic_vector(7 downto 0); --! Current fmsp instance number
cpu_nr_total : in std_logic_vector(7 downto 0); --! Total number of fmsp instances-1
dbg_en_s : in std_logic; --! Debug interface enable (synchronous)
dbg_halt_st : in std_logic; --! Halt/Run status from CPU
dbg_i2c_addr : in std_logic_vector(6 downto 0); --! Debug interface: I2C Address
dbg_i2c_broadcast : in std_logic_vector(6 downto 0); --! Debug interface: I2C Broadcast Address (for multicore systems)
dbg_i2c_scl : in std_logic; --! Debug interface: I2C SCL
dbg_i2c_sda_in : in std_logic; --! Debug interface: I2C SDA IN
dbg_mem_din : in std_logic_vector(15 downto 0); --! Debug unit Memory data input
dbg_reg_din : in std_logic_vector(15 downto 0); --! Debug unit CPU register data input
dbg_uart_rxd : in std_logic; --! Debug interface: UART RXD (asynchronous)
decode_noirq : in std_logic; --! Frontend decode instruction
eu_mab : in std_logic_vector(15 downto 0); --! Execution-Unit Memory address bus
eu_mb_en : in std_logic; --! Execution-Unit Memory bus enable
eu_mb_wr : in std_logic_vector(1 downto 0); --! Execution-Unit Memory bus write transfer
fe_mdb_in : in std_logic_vector(15 downto 0); --! Frontend Memory data bus input
pc : in std_logic_vector(15 downto 0); --! Program counter
puc_pnd_set : in std_logic; --! PUC pending set for the serial debug interface
--! OUTPUTs
dbg_cpu_reset : out std_logic; --! Reset CPU from debug interface
dbg_freeze : out std_logic; --! Freeze peripherals
dbg_halt_cmd : out std_logic; --! Halt CPU command
dbg_i2c_sda_out : out std_logic := '1'; --! Debug interface: I2C SDA OUT
dbg_mem_addr : out std_logic_vector(15 downto 0); --! Debug address for rd/wr access
dbg_mem_dout : out std_logic_vector(15 downto 0); --! Debug unit data output
dbg_mem_en : out std_logic; --! Debug unit memory enable
dbg_mem_wr : out std_logic_vector(1 downto 0); --! Debug unit memory write
dbg_reg_wr : out std_logic; --! Debug unit CPU register write
dbg_uart_txd : out std_logic := '1' --! Debug interface: UART TXD
);
end entity fmsp_dbg;
architecture RTL of fmsp_dbg is
--! Debug interface: Software breakpoint opcode
constant DBG_SWBRK_OP : std_logic_vector(15 downto 0) :=x"4343";
----! State machine definition
constant M_IDLE : std_logic_vector(1 downto 0) := "00";
constant M_SET_BRK : std_logic_vector(1 downto 0) := "01";
constant M_ACCESS_BRK : std_logic_vector(1 downto 0) := "10";
constant M_ACCESS : std_logic_vector(1 downto 0) := "11";
--! Debug interface
constant DBG_UART_WR : integer := 18;
constant DBG_UART_BW : integer := 17;
-- constant DBG_UART_ADDR 16:11
--! Debug interface CPU_CTL register
constant HALT : integer := 0;
constant RUN : integer := 1;
constant ISTEP : integer := 2;
constant SW_BRK_EN : integer := 3;
constant FRZ_BRK_EN : integer := 4;
constant RST_BRK_EN : integer := 5;
constant CPU_RST : integer := 6;
--! Debug interface CPU_STAT register
constant HALT_RUN : integer := 0;
constant PUC_PND : integer := 1;
constant SWBRK_PND : integer := 3;
constant HWBRK0_PND : integer := 4;
constant HWBRK1_PND : integer := 5;
--! Debug interface BRKx_CTL register
constant BRK_MODE_RD : integer := 0;
constant BRK_MODE_WR : integer := 1;
-- constant BRK_MODE 1:0
constant BRK_EN : integer := 2;
constant BRK_I_EN : integer := 3;
constant BRK_RANGE : integer := 4;
--! Number of registers
constant NR_REG : integer := 25;
--! Register addresses
constant CPU_ID_LO : integer := 00;
constant CPU_ID_HI : integer := 01;
constant CPU_CTL : integer := 02;
constant CPU_STAT : integer := 03;
constant MEM_CTL : integer := 04;
constant MEM_ADDR : integer := 05;
constant C_MEM_DATA : integer := 06;
constant MEM_CNT : integer := 07;
constant BRK0_CTL : integer := 08;
constant BRK0_STAT : integer := 09;
constant BRK0_ADDR0 : integer := 10;
constant BRK0_ADDR1 : integer := 11;
constant BRK1_CTL : integer := 12;
constant BRK1_STAT : integer := 13;
constant BRK1_ADDR0 : integer := 14;
constant BRK1_ADDR1 : integer := 15;
constant BRK2_CTL : integer := 16;
constant BRK2_STAT : integer := 17;
constant BRK2_ADDR0 : integer := 18;
constant BRK2_ADDR1 : integer := 19;
constant BRK3_CTL : integer := 20;
constant BRK3_STAT : integer := 21;
constant BRK3_ADDR0 : integer := 22;
constant BRK3_ADDR1 : integer := 23;
constant CPU_NR : integer := 24;
type fmsp_dbg_in_type is record
cpu_en_s : std_logic; --! Enable CPU code execution (synchronous)
cpu_id : std_logic_vector(31 downto 0); --! CPU ID
cpu_nr_inst : std_logic_vector(7 downto 0); --! Current fmsp instance number
cpu_nr_total : std_logic_vector(7 downto 0); --! Total number of fmsp instances-1
dbg_en_s : std_logic; --! Debug interface enable (synchronous)
dbg_halt_st : std_logic; --! Halt/Run status from CPU
dbg_i2c_addr : std_logic_vector(6 downto 0); --! Debug interface: I2C Address
dbg_i2c_broadcast : std_logic_vector(6 downto 0); --! Debug interface: I2C Broadcast Address (for multicore systems)
dbg_i2c_scl : std_logic; --! Debug interface: I2C SCL
dbg_i2c_sda_in : std_logic; --! Debug interface: I2C SDA IN
dbg_mem_din : std_logic_vector(15 downto 0); --! Debug unit Memory data input
dbg_reg_din : std_logic_vector(15 downto 0); --! Debug unit CPU register data input
dbg_uart_rxd : std_logic; --! Debug interface: UART RXD (asynchronous)
decode_noirq : std_logic; --! Frontend decode instruction
eu_mab : std_logic_vector(15 downto 0); --! Execution-Unit Memory address bus
eu_mb_en : std_logic; --! Execution-Unit Memory bus enable
eu_mb_wr : std_logic_vector(1 downto 0); --! Execution-Unit Memory bus write transfer
fe_mdb_in : std_logic_vector(15 downto 0); --! Frontend Memory data bus input
pc : std_logic_vector(15 downto 0); --! Program counter
puc_pnd_set : std_logic; --! PUC pending set for the serial debug interface
--! frome Sub modules
brk0_halt : std_logic;
brk0_pnd : std_logic;
brk0_dout : std_logic_vector(15 downto 0);
brk1_halt : std_logic;
brk1_pnd : std_logic;
brk1_dout : std_logic_vector(15 downto 0);
brk2_halt : std_logic;
brk2_pnd : std_logic;
brk2_dout : std_logic_vector(15 downto 0);
brk3_halt : std_logic;
brk3_pnd : std_logic;
brk3_dout : std_logic_vector(15 downto 0);
dbg_addr_rs232 : std_logic_vector(5 downto 0);
dbg_din_rs232 : std_logic_vector(15 downto 0);
dbg_wr_rs232 : std_logic;
dbg_rd_rs232 : std_logic;
dbg_addr_i2c : std_logic_vector(5 downto 0);
dbg_din_i2c : std_logic_vector(15 downto 0);
dbg_wr_i2c : std_logic;
dbg_rd_i2c : std_logic;
end record;
type reg_type is record
mem_burst : std_logic;
dbg_mem_rd_dly : std_logic;
dbg_rd_rdy : std_logic;
--! Register address decode
reg_dec : std_logic_vector(NR_REG-1 downto 0);
cpu_ctl : std_logic_vector(6 downto 3);
cpu_stat : std_logic_vector(3 downto 2);
mem_ctl : std_logic_vector(3 downto 1);
mem_start : std_logic;
mem_data : std_logic_vector(15 downto 0);
mem_addr : std_logic_vector(15 downto 0);
mem_cnt : std_logic_vector(15 downto 0);
--! Single step
inc_step : std_logic_vector(1 downto 0);
--! Run / Halt
halt_flag : std_logic;
--! Memory access state machine
mem_state : std_logic_vector(1 downto 0);
mem_state_nxt : std_logic_vector(1 downto 0);
--! Trigger CPU Register or memory access during a burst
mem_startb : std_logic;
end record;
signal d : fmsp_dbg_in_type;
signal r : reg_type := ( mem_burst => '0',
dbg_mem_rd_dly => '0',
dbg_rd_rdy => '0',
reg_dec => (Others => '0'),
cpu_ctl => "0000",
cpu_stat => "00",
mem_ctl => "000",
mem_start => '0',
mem_data => x"0000",
mem_addr => x"0000",
mem_cnt => x"0000",
inc_step => "00",
halt_flag => '0',
mem_state => "00",
mem_state_nxt => "00",
mem_startb => '0'
);
signal rin : reg_type;
signal mem_bw : std_logic;
--! Hardware Breakpoint/Watchpoint Register read select
signal brk0_reg_rd : std_logic_vector(3 downto 0) := "0000";
signal brk1_reg_rd : std_logic_vector(3 downto 0) := "0000";
signal brk2_reg_rd : std_logic_vector(3 downto 0) := "0000";
signal brk3_reg_rd : std_logic_vector(3 downto 0) := "0000";
--! Hardware Breakpoint/Watchpoint Register write select
signal brk0_reg_wr : std_logic_vector(3 downto 0) := "0000";
signal brk1_reg_wr : std_logic_vector(3 downto 0) := "0000";
signal brk2_reg_wr : std_logic_vector(3 downto 0) := "0000";
signal brk3_reg_wr : std_logic_vector(3 downto 0) := "0000";
signal dbg_addr : std_logic_vector(5 downto 0);
signal dbg_din : std_logic_vector(15 downto 0);
signal dbg_wr : std_logic;
signal dbg_rd : std_logic;
signal dbg_dout : std_logic_vector(15 downto 0);
signal mem_burst_end : std_logic;
signal mem_burst_rd : std_logic;
signal mem_burst_wr : std_logic;
begin
d.cpu_en_s <= cpu_en_s; --! Enable CPU code execution (synchronous)
d.cpu_id <= cpu_id; --! CPU ID
d.cpu_nr_inst <= cpu_nr_inst; --! Current fmsp instance number
d.cpu_nr_total <= cpu_nr_total; --! Total number of fmsp instances-1
d.dbg_en_s <= dbg_en_s; --! Debug interface enable (synchronous)
d.dbg_halt_st <= dbg_halt_st; --! Halt/Run status from CPU
d.dbg_i2c_addr <= dbg_i2c_addr; --! Debug interface: I2C Address
d.dbg_i2c_broadcast <= dbg_i2c_broadcast; --! Debug interface: I2C Broadcast Address (for multicore systems)
d.dbg_i2c_scl <= dbg_i2c_scl; --! Debug interface: I2C SCL
d.dbg_i2c_sda_in <= dbg_i2c_sda_in; --! Debug interface: I2C SDA IN
d.dbg_mem_din <= dbg_mem_din; --! Debug unit Memory data input
d.dbg_reg_din <= dbg_reg_din; --! Debug unit CPU register data input
d.dbg_uart_rxd <= dbg_uart_rxd; --! Debug interface: UART RXD (asynchronous)
d.decode_noirq <= decode_noirq; --! Frontend decode instruction
d.eu_mab <= eu_mab; --! Execution-Unit Memory address bus
d.eu_mb_en <= eu_mb_en; --! Execution-Unit Memory bus enable
d.eu_mb_wr <= eu_mb_wr; --! Execution-Unit Memory bus write transfer
d.fe_mdb_in <= fe_mdb_in; --! Frontend Memory data bus input
d.pc <= pc; --! Program counter
d.puc_pnd_set <= puc_pnd_set; --! PUC pending set for the serial debug interface
COMB : process (d, r)
variable v : reg_type;
--============================================================================
--! 2) REGISTER DECODER
--============================================================================
--=============================================================================
--! 1) variable v_& PARAMETER DECLARATION
--=============================================================================
--! Diverse wires and registers
variable v_dbg_addr : std_logic_vector(5 downto 0);
variable v_dbg_din : std_logic_vector(15 downto 0);
variable v_dbg_wr : std_logic;
variable v_dbg_rd : std_logic;
--! Select Data register during a burst
variable v_dbg_addr_in : std_logic_vector(5 downto 0);
--! Register address decode
variable v_reg_dec : std_logic_vector(63 downto 0);
--! Read/Write probes
variable v_reg_write : std_logic;
variable v_reg_read : std_logic;
--! Read/Write vectors
variable v_reg_wr : std_logic_vector(NR_REG-1 downto 0);
variable v_reg_rd : std_logic_vector(NR_REG-1 downto 0);
--! 3) REGISTER: CORE INTERFACE
--! CPU_NR Register
variable v_cpu_nr : std_logic_vector(15 downto 0);
--! CPU_CTL Register
variable v_cpu_ctl_wr : std_logic;
variable v_cpu_ctl_full : std_logic_vector(7 downto 0);
variable v_halt_cpu : std_logic;
variable v_run_cpu : std_logic;
variable v_istep : std_logic;
--! CPU_STAT Register
variable v_cpu_stat_wr : std_logic;
variable v_cpu_stat_set : std_logic_vector(3 downto 2);
variable v_cpu_stat_clr : std_logic_vector(3 downto 2);
variable v_cpu_stat_full : std_logic_vector(7 downto 0);
--! 4) REGISTER: MEMORY INTERFACE
--! MEM_CTL Register
variable v_mem_ctl_wr : std_logic;
variable v_mem_ctl_full : std_logic_vector(7 downto 0);
variable v_mem_bw : std_logic;
--! C_MEM_DATA Register
variable v_mem_access : std_logic;
variable v_mem_data_wr : std_logic;
variable v_dbg_mem_din_bw : std_logic_vector(15 downto 0);
--! MEM_ADDR Register
variable v_mem_addr_wr : std_logic;
variable v_dbg_mem_acc : std_logic;
variable v_dbg_reg_acc : std_logic;
variable v_mem_addr_inc : std_logic_vector(15 downto 0);
--! MEM_CNT Register
variable v_mem_cnt_wr : std_logic;
variable v_mem_cnt_dec : std_logic_vector(15 downto 0);
--! 6) DATA OUTPUT GENERATION
variable v_cpu_id_lo_rd : std_logic_vector(15 downto 0);
variable v_cpu_id_hi_rd : std_logic_vector(15 downto 0);
variable v_cpu_ctl_rd : std_logic_vector(15 downto 0);
variable v_cpu_stat_rd : std_logic_vector(15 downto 0);
variable v_mem_ctl_rd : std_logic_vector(15 downto 0);
variable v_mem_data_rd : std_logic_vector(15 downto 0);
variable v_mem_addr_rd : std_logic_vector(15 downto 0);
variable v_mem_cnt_rd : std_logic_vector(15 downto 0);
variable v_cpu_nr_rd : std_logic_vector(15 downto 0);
variable v_dbg_dout : std_logic_vector(15 downto 0);
--! 7) CPU CONTROL
--! Reset CPU
variable v_dbg_cpu_reset : std_logic;
--! Break after reset
variable v_halt_rst : std_logic;
--! Freeze peripherals
variable v_dbg_freeze : std_logic;
--! Software break
variable v_dbg_swbrk : std_logic;
variable v_mem_halt_cpu : std_logic;
variable v_mem_run_cpu : std_logic;
variable v_halt_flag_clr : std_logic;
variable v_halt_flag_set : std_logic;
variable v_dbg_halt_cmd : std_logic;
--! 8) MEMORY CONTROL
variable v_mem_state_nxt : std_logic_vector(1 downto 0);
--! Control Memory bursts
variable v_mem_burst_start : std_logic;
variable v_mem_burst_end : std_logic;
--! Control signals for UART/I2C interface
variable v_mem_burst_rd : std_logic;
variable v_mem_burst_wr : std_logic;
--! Combine single and burst memory start of sequence
variable v_mem_seq_start : std_logic;
--! Interface to CPU Registers and Memory bacbkone
variable v_dbg_mem_addr : std_logic_vector(15 downto 0);
variable v_dbg_mem_dout : std_logic_vector(15 downto 0);
variable v_dbg_reg_wr : std_logic;
variable v_dbg_reg_rd : std_logic;
variable v_dbg_mem_en : std_logic;
variable v_dbg_mem_rd : std_logic;
variable v_dbg_mem_wr_msk : std_logic_vector(1 downto 0);
variable v_dbg_mem_wr : std_logic_vector(1 downto 0);
--! UNUSED UART COMMUNICATION
variable UNUSED_dbg_uart_rxd : std_logic;
--! UNUSED I2C COMMUNICATION
variable UNUSED_dbg_i2c_addr : std_logic_vector(6 downto 0);
variable UNUSED_dbg_i2c_broadcast : std_logic_vector(6 downto 0);
variable UNUSED_dbg_i2c_scl : std_logic;
variable UNUSED_dbg_i2c_sda_in : std_logic;
variable UNUSED_dbg_rd_rdy : std_logic;
begin
--! default assignment
v := r;
--! overriding assignments
if (DBG_UART = true) then
v_dbg_addr := d.dbg_addr_rs232; --! Debug register address
v_dbg_din := d.dbg_din_rs232; --! Debug register data input
v_dbg_rd := d.dbg_rd_rs232; --! Debug register data read
v_dbg_wr := d.dbg_wr_rs232; --! Debug register data write
elsif (DBG_I2C = true) then
v_dbg_addr := d.dbg_addr_i2c; --! Debug register address
v_dbg_din := d.dbg_din_i2c; --! Debug register data input
v_dbg_rd := d.dbg_rd_i2c; --! Debug register data read
v_dbg_wr := d.dbg_wr_i2c; --! Debug register data write
else
v_dbg_addr := "000000"; --! Debug register address
v_dbg_din := x"0000"; --! Debug register data input
v_dbg_rd := '0'; --! Debug register data read
v_dbg_wr := '0'; --! Debug register data writ
end if;
--============================================================================
--! 2) REGISTER DECODER
--============================================================================
--! Select Data register during a burst
if (r.mem_burst = '1') then
v_dbg_addr_in := STD_LOGIC_VECTOR(TO_UNSIGNED(C_MEM_DATA,6));
else
v_dbg_addr_in := v_dbg_addr;
end if;
--! Register address decode
v_reg_dec := onehot(v_dbg_addr_in);
--! Read/Write probes
v_reg_write := v_dbg_wr;
v_reg_read := '1';
--! Read/Write vectors
if (v_reg_write = '1') then
v_reg_wr := v_reg_dec(NR_REG-1 downto 0);
else
v_reg_wr := (Others => '0');
end if;
if (v_reg_read = '1') then
v_reg_rd := v_reg_dec(NR_REG-1 downto 0);
else
v_reg_rd := (Others => '0');
end if;
--=============================================================================
--! 3) REGISTER: CORE INTERFACE
--=============================================================================
--! CPU_ID Register
-------------------
--! -------------------------------------------------------------------
--! CPU_ID_LO: | 15 14 13 12 11 10 9 | 8 7 6 5 4 | 3 | 2 1 0 |
--! |----------------------------+-----------------+------+-------------|
--! | PER_SPACE | USER_VERSION | ASIC | CPU_VERSION |
--! --------------------------------------------------------------------
--! CPU_ID_HI: | 15 14 13 12 11 10 | 9 8 7 6 5 4 3 2 1 | 0 |
--! |----------------------------+-------------------------------+------|
--! | PMEM_SIZE | DMEM_SIZE | MPY |
--! -------------------------------------------------------------------
--! This register is assigned in the SFR module
--! CPU_NR Register
-------------------
--! -------------------------------------------------------------------
--! | 15 14 13 12 11 10 9 8 | 7 6 5 4 3 2 1 0 |
--! |---------------------------------+---------------------------------|
--! | CPU_TOTAL_NR | CPU_INST_NR |
--! -------------------------------------------------------------------
v_cpu_nr := d.cpu_nr_total & d.cpu_nr_inst;
--! CPU_CTL Register
-------------------------------------------------------------------------------
--! 7 6 5 4 3 2 1 0
--! Reserved CPU_RST RST_BRK_EN FRZ_BRK_EN SW_BRK_EN ISTEP RUN HALT
-------------------------------------------------------------------------------
v_cpu_ctl_wr := v_reg_wr(CPU_CTL);
if (v_cpu_ctl_wr = '1') then
v.cpu_ctl := v_dbg_din(6 downto 3);
end if;
v_cpu_ctl_full := '0' & r.cpu_ctl & "000";
v_halt_cpu := v_cpu_ctl_wr and v_dbg_din(HALT) and not( d.dbg_halt_st);
v_run_cpu := v_cpu_ctl_wr and v_dbg_din(RUN) and d.dbg_halt_st;
v_istep := v_cpu_ctl_wr and v_dbg_din(ISTEP) and d.dbg_halt_st;
--! Reset CPU
v_dbg_cpu_reset := r.cpu_ctl(CPU_RST);
--! Break after reset
v_halt_rst := r.cpu_ctl(RST_BRK_EN) and d.dbg_en_s and d.puc_pnd_set;
--! Freeze peripherals
v_dbg_freeze := d.dbg_halt_st and ( r.cpu_ctl(FRZ_BRK_EN) or not(d.cpu_en_s) );
--! Software break
v_dbg_swbrk := '0';
if (d.fe_mdb_in = DBG_SWBRK_OP) then
v_dbg_swbrk := d.decode_noirq and r.cpu_ctl(SW_BRK_EN);
end if;
--! Single step
if (v_istep = '1') then
v.inc_step := "11";
else
v.inc_step := r.inc_step(0) & '0';
end if;
--============================================================================
--! 7) CPU CONTROL
--============================================================================
--! Run / Halt
v_halt_flag_clr := v_run_cpu or v_mem_run_cpu;
v_halt_flag_set := v_halt_cpu or v_halt_rst or v_dbg_swbrk or v_mem_halt_cpu or d.brk0_halt or d.brk1_halt or d.brk2_halt or d.brk3_halt;
if (v_halt_flag_clr = '1') then
v.halt_flag := '0';
elsif (v_halt_flag_set = '1') then
v.halt_flag := '1';
end if;
v_dbg_halt_cmd := (r.halt_flag or v_halt_flag_set) and not(r.inc_step(1));
--! CPU_STAT Register
--------------------------------------------------------------------------------------
--! 7 6 5 4 3 2 1 0
--! HWBRK3_PND HWBRK2_PND HWBRK1_PND HWBRK0_PND SWBRK_PND PUC_PND Res. HALT_RUN
--------------------------------------------------------------------------------------
v_cpu_stat_wr := v_reg_wr(CPU_STAT);
v_cpu_stat_set := v_dbg_swbrk & d.puc_pnd_set;
v_cpu_stat_clr := not(v_dbg_din(3 downto 2));
if (v_cpu_stat_wr = '1') then
v.cpu_stat := v_cpu_stat_set or (r.cpu_stat and v_cpu_stat_clr);
else
v.cpu_stat := v_cpu_stat_set or r.cpu_stat;
end if;
v_cpu_stat_full := d.brk3_pnd & d.brk2_pnd & d.brk1_pnd & d.brk0_pnd & r.cpu_stat & '0' & d.dbg_halt_st;
-- UNUSED_eu_mab := eu_mab;
-- UNUSED_eu_mb_en := eu_mb_en;
-- UNUSED_eu_mb_wr := eu_mb_wr;
-- UNUSED_pc := pc;
--============================================================================
--! 8) MEMORY CONTROL
--============================================================================
--! Control Memory bursts
if ( (r.mem_cnt /= x"0000") and (r.mem_start = '1') ) then
v_mem_burst_start := '1';
else
v_mem_burst_start := '0';
end if;
if ( (r.mem_cnt = x"0000") and ((v_dbg_wr or r.dbg_rd_rdy) = '1') ) then
v_mem_burst_end := '1';
else
v_mem_burst_end := '0';
end if;
--! Detect when burst is on going
if (v_mem_burst_start = '1') then
v.mem_burst := '1';
elsif (v_mem_burst_end = '1') then
v.mem_burst := '0';
end if;
--! Control signals for UART/I2C interface
v_mem_burst_rd := v_mem_burst_start and not(r.mem_ctl(1));
v_mem_burst_wr := v_mem_burst_start and r.mem_ctl(1);
--! Trigger CPU Register or memory access during a burst
v.mem_startb := (r.mem_burst and (v_dbg_wr or v_dbg_rd)) or v_mem_burst_rd;
--! Combine single and burst memory start of sequence
if ( ( (r.mem_cnt = x"0000")
and (r.mem_start = '1') )
or (r.mem_startb = '1') )then
v_mem_seq_start := '1';
else
v_mem_seq_start := '0';
end if;
--! Memory access state machine
--------------------------------
--! State transition
case (r.mem_state) is
when M_IDLE =>
if (not(v_mem_seq_start) = '1') then
v_mem_state_nxt := M_IDLE;
elsif (d.dbg_halt_st = '1') then
v_mem_state_nxt := M_ACCESS;
else
v_mem_state_nxt := M_SET_BRK;
end if;
when M_SET_BRK =>
if (d.dbg_halt_st = '1') then
v_mem_state_nxt := M_ACCESS_BRK;
else
v_mem_state_nxt := M_SET_BRK;
end if;
when M_ACCESS_BRK =>
v_mem_state_nxt := M_IDLE;
when M_ACCESS =>
v_mem_state_nxt := M_IDLE;
when others =>
v_mem_state_nxt := M_IDLE;
end case;
--! State machine
v.mem_state := v_mem_state_nxt;
--! Utility signals
v_mem_halt_cpu := '0';
v_mem_run_cpu := '0';
v_mem_access := '0';
if ( (r.mem_state = M_IDLE)
and (v_mem_state_nxt = M_SET_BRK) ) then
v_mem_halt_cpu := '1';
end if;
if ( (r.mem_state = M_ACCESS_BRK)
and (v_mem_state_nxt = M_IDLE) ) then
v_mem_run_cpu := '1';
end if;
if ( (r.mem_state = M_ACCESS)
or (r.mem_state = M_ACCESS_BRK) ) then
v_mem_access := '1';
end if;
--! Interface to CPU Registers and Memory bacbkone
--------------------------------------------------
v_dbg_mem_addr := r.mem_addr;
if (not(v_mem_bw) = '1') then
v_dbg_mem_dout := r.mem_data;
elsif (r.mem_addr(0) = '1') then
v_dbg_mem_dout := r.mem_data(7 downto 0) & x"00";
else
v_dbg_mem_dout := x"00" & r.mem_data(7 downto 0);
end if;
v_dbg_reg_wr := v_mem_access and r.mem_ctl(1) and r.mem_ctl(2);
v_dbg_reg_rd := v_mem_access and not(r.mem_ctl(1)) and r.mem_ctl(2);
v_dbg_mem_en := v_mem_access and not(r.mem_ctl(2));
v_dbg_mem_rd := dbg_mem_en and not(r.mem_ctl(1));
if (not(v_mem_bw) = '1') then
v_dbg_mem_wr_msk := "11";
elsif (r.mem_addr(0) = '1') then
v_dbg_mem_wr_msk := "10";
else
v_dbg_mem_wr_msk := "01";
end if;
v_dbg_mem_wr := "00";
if ( (dbg_mem_en = '1')
and (r.mem_ctl(1) = '1') ) then
v_dbg_mem_wr := v_dbg_mem_wr_msk;
end if;
--! It takes one additional cycle to read from Memory as from registers
v.dbg_mem_rd_dly := v_dbg_mem_rd;
--=============================================================================
--! 4) REGISTER: MEMORY INTERFACE
--=============================================================================
--! MEM_CTL Register
-------------------------------------------------------------------------------
--! 7 6 5 4 3 2 1 0
--! Reserved B/W MEM/REG RD/WR START
--
--! START : - 0 : Do nothing.
--! - 1 : Initiate memory transfer.
--
--! RD/WR : - 0 : Read access.
--! - 1 : Write access.
--
--! MEM/REG: - 0 : Memory access.
--! - 1 : CPU Register access.
--
--! B/W : - 0 : 16 bit access.
--! - 1 : 8 bit access (not valid for CPU Registers).
--
-------------------------------------------------------------------------------
v_mem_ctl_wr := v_reg_wr(MEM_CTL);
if (v_mem_ctl_wr = '1') then
v.mem_ctl := v_dbg_din(3 downto 1);
end if;
v_mem_ctl_full := "0000" & r.mem_ctl & '0';
v.mem_start := v_mem_ctl_wr and v_dbg_din(0);
v_mem_bw := r.mem_ctl(3);
--! C_MEM_DATA Register
--------------------
v_mem_data_wr := v_reg_wr(C_MEM_DATA);
if (not(v_mem_bw) = '1') then
v_dbg_mem_din_bw := d.dbg_mem_din;
elsif (r.mem_addr(0) = '1') then
v_dbg_mem_din_bw := x"00" & d.dbg_mem_din(15 downto 8);
else
v_dbg_mem_din_bw := x"00" & d.dbg_mem_din(7 downto 0);
end if;
if (v_mem_data_wr = '1') then
v.mem_data := v_dbg_din;
elsif (v_dbg_reg_rd = '1') then
v.mem_data := d.dbg_reg_din;
elsif (r.dbg_mem_rd_dly = '1') then
v.mem_data := v_dbg_mem_din_bw;
end if;
--! MEM_ADDR Register
--------------------
v_mem_addr_wr := v_reg_wr(MEM_ADDR);
v_dbg_mem_acc := ( v_dbg_mem_wr(0) or v_dbg_mem_wr(1) or ( r.dbg_rd_rdy and not(r.mem_ctl(2)) ) );
v_dbg_reg_acc := ( dbg_reg_wr or ( r.dbg_rd_rdy and r.mem_ctl(2) ) );
if (r.mem_cnt = x"0000") then
v_mem_addr_inc := x"0000";
elsif ((r.mem_burst and v_dbg_mem_acc and not(v_mem_bw)) = '1') then
v_mem_addr_inc := x"0000";
elsif ((r.mem_burst and (v_dbg_mem_acc or v_dbg_reg_acc)) = '1') then
v_mem_addr_inc := x"0001";
else
v_mem_addr_inc := x"0000";
end if;
if (v_mem_addr_wr = '1') then
v.mem_addr := v_dbg_din;
else
v.mem_addr := STD_LOGIC_VECTOR( UNSIGNED(r.mem_addr) + UNSIGNED(v_mem_addr_inc) );
end if;
--! MEM_CNT Register
--------------------
v_mem_cnt_wr := v_reg_wr(MEM_CNT);
if (r.mem_cnt = x"0000") then
v_mem_cnt_dec := x"0000";
elsif ((r.mem_burst and (v_dbg_mem_acc or v_dbg_reg_acc)) = '1') then
v_mem_cnt_dec := x"FFFF";
else
v_mem_cnt_dec := x"0000";
end if;
if (v_mem_cnt_wr = '1') then
v.mem_cnt := v_dbg_din;
else
v.mem_cnt := STD_LOGIC_VECTOR( UNSIGNED(r.mem_cnt) + UNSIGNED(v_mem_cnt_dec) );
end if;
--=============================================================================
--! 9) UART COMMUNICATION
--=============================================================================
if (DBG_UART = false) then
UNUSED_dbg_uart_rxd := d.dbg_uart_rxd;
end if;
--=============================================================================
--! 10) I2C COMMUNICATION
--=============================================================================
if (DBG_I2C = false) then
UNUSED_dbg_i2c_addr := d.dbg_i2c_addr;
UNUSED_dbg_i2c_broadcast := d.dbg_i2c_broadcast;
UNUSED_dbg_i2c_scl := d.dbg_i2c_scl;
UNUSED_dbg_i2c_sda_in := d.dbg_i2c_sda_in;
--v_UNUSED_dbg_rd_rdy := d.dbg_rd_rdy;
end if;
--============================================================================
--! 6) DATA OUTPUT GENERATION
--============================================================================
-- v_cpu_id_lo_rd := word_per_select_dout( CPU_ID_LO, v_reg_rd, d.cpu_id(15 downto 0) );
-- v_cpu_id_hi_rd := word_per_select_dout( CPU_ID_HI, v_reg_rd, d.cpu_id(31 downto 16) );
-- v_cpu_ctl_rd := word_per_select_dout( CPU_CTL, v_reg_rd, (x"00" & v_cpu_ctl_full) );
-- v_cpu_stat_rd := word_per_select_dout( CPU_STAT, v_reg_rd, (x"00" & v_cpu_stat_full) );
-- v_mem_ctl_rd := word_per_select_dout( MEM_CTL, v_reg_rd, (x"00" & v_mem_ctl_full) );
-- v_mem_data_rd := word_per_select_dout( C_MEM_DATA, v_reg_rd, r.mem_data );
-- v_mem_addr_rd := word_per_select_dout( MEM_ADDR, v_reg_rd, r.mem_addr );
-- v_mem_cnt_rd := word_per_select_dout( MEM_CNT, v_reg_rd, r.mem_cnt );
-- v_cpu_nr_rd := word_per_select_dout( CPU_NR, v_reg_rd, v_cpu_nr );
if ( v_reg_rd(CPU_ID_LO) = '1' ) then
v_cpu_id_lo_rd := d.cpu_id(15 downto 0);
else
v_cpu_id_lo_rd := x"0000";
end if;
if ( v_reg_rd(CPU_ID_HI) = '1' ) then
v_cpu_id_hi_rd := d.cpu_id(31 downto 16);
else
v_cpu_id_hi_rd := x"0000";
end if;
if ( v_reg_rd(CPU_CTL) = '1' ) then
v_cpu_ctl_rd := x"00" & v_cpu_ctl_full;
else
v_cpu_ctl_rd := x"0000";
end if;
if ( v_reg_rd(CPU_STAT) = '1' ) then
v_cpu_stat_rd := x"00" & v_cpu_stat_full;
else
v_cpu_stat_rd := x"0000";
end if;
if ( v_reg_rd(MEM_CTL) = '1' ) then
v_mem_ctl_rd := x"00" & v_mem_ctl_full;
else
v_mem_ctl_rd := x"0000";
end if;
if ( v_reg_rd(C_MEM_DATA) = '1' ) then
v_mem_data_rd := r.mem_data;
else
v_mem_data_rd := x"0000";
end if;
if ( v_reg_rd(MEM_ADDR) = '1' ) then
v_mem_addr_rd := r.mem_addr;
else
v_mem_addr_rd := x"0000";
end if;
if ( v_reg_rd(MEM_CNT) = '1' ) then
v_mem_cnt_rd := r.mem_cnt;
else
v_mem_cnt_rd := x"0000";
end if;
if ( v_reg_rd(CPU_NR) = '1' ) then
v_cpu_nr_rd := v_cpu_nr;
else
v_cpu_nr_rd := x"0000";
end if;
v_dbg_dout := v_cpu_id_lo_rd or
v_cpu_id_hi_rd or
v_cpu_ctl_rd or
v_cpu_stat_rd or
v_mem_ctl_rd or
v_mem_data_rd or
v_mem_addr_rd or
v_mem_cnt_rd or
d.brk0_dout or
d.brk1_dout or
d.brk2_dout or
d.brk3_dout or
v_cpu_nr_rd;
--! Tell UART/I2C interface that the data is ready to be read
if ( (r.mem_burst = '1') or (v_mem_burst_rd = '1') ) then
v.dbg_rd_rdy := v_dbg_reg_rd or r.dbg_mem_rd_dly;
else
v.dbg_rd_rdy := v_dbg_rd;
end if;
-- if ( v_brk_stat_set /= "000000" ) then
-- v_brk_halt := r.brk_ctl(C_BRK_EN);
-- end if;
--! drive register inputs
rin <= v;
--! drive module outputs
-- brk_halt <= v_brk_halt; --! Hardware breakpoint command
-- brk_pnd <= v_brk_pnd; --! Hardware break/watch-point pending
-- brk_dout <= v_brk_dout; --! Hardware break/watch-point register data input
dbg_cpu_reset <= v_dbg_cpu_reset; --! Reset CPU from debug interface
dbg_freeze <= v_dbg_freeze; --! Freeze peripherals
dbg_halt_cmd <= v_dbg_halt_cmd; --! Halt CPU command
-- dbg_i2c_sda_out <= v_dbg_i2c_sda_out; --! Debug interface: I2C SDA OUT
dbg_mem_addr <= v_dbg_mem_addr; --! Debug address for rd/wr access
dbg_mem_dout <= v_dbg_mem_dout; --! Debug unit data output
dbg_mem_en <= v_dbg_mem_en; --! Debug unit memory enable
dbg_mem_wr <= v_dbg_mem_wr; --! Debug unit memory write
dbg_reg_wr <= v_dbg_reg_wr; --! Debug unit CPU register write
-- dbg_uart_txd <= v_dbg_uart_txd; --! Debug interface: UART TXD
--! Hardware Breakpoint/Watchpoint Register read select
brk0_reg_rd <= v_reg_rd(BRK0_ADDR1) & v_reg_rd(BRK0_ADDR0) & v_reg_rd(BRK0_STAT) & v_reg_rd(BRK0_CTL);
brk1_reg_rd <= v_reg_rd(BRK1_ADDR1) & v_reg_rd(BRK1_ADDR0) & v_reg_rd(BRK1_STAT) & v_reg_rd(BRK1_CTL);
brk2_reg_rd <= v_reg_rd(BRK2_ADDR1) & v_reg_rd(BRK2_ADDR0) & v_reg_rd(BRK2_STAT) & v_reg_rd(BRK2_CTL);
brk3_reg_rd <= v_reg_rd(BRK3_ADDR1) & v_reg_rd(BRK3_ADDR0) & v_reg_rd(BRK3_STAT) & v_reg_rd(BRK3_CTL);
--! Hardware Breakpoint/Watchpoint Register write select
brk0_reg_wr <= v_reg_wr(BRK0_ADDR1) & v_reg_wr(BRK0_ADDR0) & v_reg_wr(BRK0_STAT) & v_reg_wr(BRK0_CTL);
brk1_reg_wr <= v_reg_wr(BRK1_ADDR1) & v_reg_wr(BRK1_ADDR0) & v_reg_wr(BRK1_STAT) & v_reg_wr(BRK1_CTL);
brk2_reg_wr <= v_reg_wr(BRK2_ADDR1) & v_reg_wr(BRK2_ADDR0) & v_reg_wr(BRK2_STAT) & v_reg_wr(BRK2_CTL);
brk3_reg_wr <= v_reg_wr(BRK3_ADDR1) & v_reg_wr(BRK3_ADDR0) & v_reg_wr(BRK3_STAT) & v_reg_wr(BRK3_CTL);
dbg_din <= v_dbg_din; --! Debug register data input
dbg_dout <= v_dbg_dout; --! Debug register data output
mem_burst_end <= v_mem_burst_end;
mem_burst_rd <= v_mem_burst_rd;
mem_burst_wr <= v_mem_burst_wr;
mem_bw <= v_mem_bw;
end process COMB;
REGS : process (dbg_clk,dbg_rst)
begin
if (dbg_rst = '1') then
if (DBG_RST_BRK_EN = true) then
r.cpu_ctl <= x"6";
else
r.cpu_ctl <= x"2";
end if;
r.mem_burst <= '0';
r.dbg_mem_rd_dly <= '0';
r.dbg_rd_rdy <= '0';
r.reg_dec <= (Others => '0');
--r.cpu_ctl : std_logic_vector(6 downto 3);
r.cpu_stat <= "00";
r.mem_ctl <= "000";
r.mem_start <= '0';
r.mem_data <= x"0000";
r.mem_addr <= x"0000";
r.mem_cnt <= x"0000";
r.inc_step <= "00";
r.halt_flag <= '0';
r.mem_state <= "00";
r.mem_startb <= '0';
elsif rising_edge(dbg_clk) then
r <= rin;
end if;
end process REGS;
-- DBG_HWBRK_0 : if DBG_HWBRK_0_EN generate
dbg_hwbr_0 : fmsp_dbg_hwbrk
generic map (
DBG_HWBRK_EN => DBG_HWBRK_0_EN -- Include hardware breakpoints unit
)
port map (
dbg_clk => dbg_clk, --! Debug unit clock
dbg_rst => dbg_rst, --! Debug unit reset
--! INPUTs
brk_reg_rd => brk0_reg_rd, --! Hardware break/watch-point register read select
brk_reg_wr => brk0_reg_wr, --! Hardware break/watch-point register write select
dbg_din => dbg_din, --! Debug register data input
decode_noirq => decode_noirq, --! Frontend decode instruction
eu_mab => eu_mab, --! Execution-Unit Memory address bus
eu_mb_en => eu_mb_en, --! Execution-Unit Memory bus enable
eu_mb_wr => eu_mb_wr, --! Execution-Unit Memory bus write transfer
pc => pc, --! Program counter
--! OUTPUTs
brk_halt => d.brk0_halt, --! Hardware breakpoint command
brk_pnd => d.brk0_pnd, --! Hardware break/watch-point pending
brk_dout => d.brk0_dout --! Hardware break/watch-point register data input
);
-- end generate DBG_HWBRK_0;
-- DBG_HWBRK_1 : if DBG_HWBRK_1_EN generate
dbg_hwbr_1 : fmsp_dbg_hwbrk
generic map (
DBG_HWBRK_EN => DBG_HWBRK_1_EN -- Include hardware breakpoints unit
)
port map (
dbg_clk => dbg_clk, --! Debug unit clock
dbg_rst => dbg_rst, --! Debug unit reset
--! INPUTs
brk_reg_rd => brk1_reg_rd, --! Hardware break/watch-point register read select
brk_reg_wr => brk1_reg_wr, --! Hardware break/watch-point register write select
dbg_din => dbg_din, --! Debug register data input
decode_noirq => decode_noirq, --! Frontend decode instruction
eu_mab => eu_mab, --! Execution-Unit Memory address bus
eu_mb_en => eu_mb_en, --! Execution-Unit Memory bus enable
eu_mb_wr => eu_mb_wr, --! Execution-Unit Memory bus write transfer
pc => pc, --! Program counter
--! OUTPUTs
brk_halt => d.brk1_halt, --! Hardware breakpoint command
brk_pnd => d.brk1_pnd, --! Hardware break/watch-point pending
brk_dout => d.brk1_dout --! Hardware break/watch-point register data input
);
-- end generate DBG_HWBRK_1;
-- DBG_HWBRK_2 : if DBG_HWBRK_2_EN generate
dbg_hwbr_2 : fmsp_dbg_hwbrk
generic map (
DBG_HWBRK_EN => DBG_HWBRK_2_EN -- Include hardware breakpoints unit
)
port map (
dbg_clk => dbg_clk, --! Debug unit clock
dbg_rst => dbg_rst, --! Debug unit reset
--! INPUTs
brk_reg_rd => brk2_reg_rd, --! Hardware break/watch-point register read select
brk_reg_wr => brk2_reg_wr, --! Hardware break/watch-point register write select
dbg_din => dbg_din, --! Debug register data input
decode_noirq => decode_noirq, --! Frontend decode instruction
eu_mab => eu_mab, --! Execution-Unit Memory address bus
eu_mb_en => eu_mb_en, --! Execution-Unit Memory bus enable
eu_mb_wr => eu_mb_wr, --! Execution-Unit Memory bus write transfer
pc => pc, --! Program counter
--! OUTPUTs
brk_halt => d.brk2_halt, --! Hardware breakpoint command
brk_pnd => d.brk2_pnd, --! Hardware break/watch-point pending
brk_dout => d.brk2_dout --! Hardware break/watch-point register data input
);
-- end generate DBG_HWBRK_2;
-- DBG_HWBRK_3 : if DBG_HWBRK_3_EN generate
dbg_hwbr_3 : fmsp_dbg_hwbrk
generic map (
DBG_HWBRK_EN => DBG_HWBRK_3_EN -- Include hardware breakpoints unit
)
port map (
dbg_clk => dbg_clk, --! Debug unit clock
dbg_rst => dbg_rst, --! Debug unit reset
--! INPUTs
brk_reg_rd => brk3_reg_rd, --! Hardware break/watch-point register read select
brk_reg_wr => brk3_reg_wr, --! Hardware break/watch-point register write select
dbg_din => dbg_din, --! Debug register data input
decode_noirq => decode_noirq, --! Frontend decode instruction
eu_mab => eu_mab, --! Execution-Unit Memory address bus
eu_mb_en => eu_mb_en, --! Execution-Unit Memory bus enable
eu_mb_wr => eu_mb_wr, --! Execution-Unit Memory bus write transfer
pc => pc, --! Program counter
--! OUTPUTs
brk_halt => d.brk3_halt, --! Hardware breakpoint command
brk_pnd => d.brk3_pnd, --! Hardware break/watch-point pending
brk_dout => d.brk3_dout --! Hardware break/watch-point register data input
);
-- end generate DBG_HWBRK_3;
ADD_DEBUG_I2C : if DBG_I2C generate
dbg_i2c_0 : fmsp_dbg_i2c
generic map(
DBG_I2C_BROADCAST_EN => DBG_I2C_BROADCAST_EN --! Enable the I2C broadcast address
)
port map(
dbg_clk => dbg_clk, --! Debug unit clock
dbg_rst => dbg_rst, --! Debug unit reset
--! INPUTs
dbg_dout => dbg_dout, --! Debug register data output
dbg_i2c_addr => dbg_i2c_addr, --! Debug interface: I2C Address
dbg_i2c_broadcast => dbg_i2c_broadcast, --! Debug interface: I2C Broadcast Address (for multicore systems)
mem_burst => r.mem_burst, --! Burst on going
mem_burst_end => mem_burst_end, --! End TX/RX burst
mem_burst_rd => mem_burst_rd, --! Start TX burst
mem_burst_wr => mem_burst_wr, --! Start RX burst
mem_bw => mem_bw, --! Burst byte width
--! OUTPUTs
dbg_addr => d.dbg_addr_i2c, --! Debug register address
dbg_din => d.dbg_din_i2c, --! Debug register data input
dbg_rd => d.dbg_rd_i2c, --! Debug register data read
dbg_wr => d.dbg_wr_i2c, --! Debug register data write
--! I2C Interface
dbg_i2c_scl => dbg_i2c_scl, --! Debug interface: I2C SCL
dbg_i2c_sda_in => dbg_i2c_sda_in, --! Debug interface: I2C SDA IN
dbg_i2c_sda_out => dbg_i2c_sda_out --! Debug interface: I2C SDA OUT
);
end generate ADD_DEBUG_I2C;
ADD_DEBUG_UART : if DBG_UART generate
dbg_uart_0 : fmsp_dbg_uart
generic map(
DBG_UART_AUTO_SYNC => DBG_UART_AUTO_SYNC, --! Debug UART interface auto data synchronization
DBG_UART_BAUD => DBG_UART_BAUD, --! Debug UART interface data rate
DBG_DCO_FREQ => DBG_DCO_FREQ, --! Debug DCO_CLK frequency
DBG_HWBRK_RANGE => DBG_HWBRK_RANGE, --! Enable/Disable the hardware breakpoint RANGE mode
SYNC_DBG_UART_RXD => SYNC_DBG_UART_RXD --! Synchronize RXD inputs
)
port map(
dbg_clk => dbg_clk, --! Debug unit clock
dbg_rst => dbg_rst, --! Debug unit reset
--! INPUTs
dbg_dout => dbg_dout, --! Debug register data output
dbg_rd_rdy => r.dbg_rd_rdy, --! Debug register data is ready for read
mem_burst => r.mem_burst, --! Burst on going
mem_burst_end => mem_burst_end, --! End TX/RX burst
mem_burst_rd => mem_burst_rd, --! Start TX burst
mem_burst_wr => mem_burst_wr, --! Start RX burst
mem_bw => mem_bw, --! Burst byte width
--! OUTPUTs
dbg_addr => d.dbg_addr_rs232, --! Debug register address
dbg_din => d.dbg_din_rs232, --! Debug register data input
dbg_rd => d.dbg_rd_rs232, --! Debug register data read
dbg_wr => d.dbg_wr_rs232, --! Debug register data write
--! RS232 Interface
dbg_uart_rxd => dbg_uart_rxd, --! Debug interface: UART RXD
dbg_uart_txd => dbg_uart_txd --! Debug interface: UART TXD
);
end generate ADD_DEBUG_UART;
end RTL; --! fmsp_dbg
|
bsd-3-clause
|
eamadio/fpgaMSP430
|
fmsp430/fmsp430.vhd
|
1
|
28121
|
------------------------------------------------------------------------------
-- Copyright (C) 2009 , Olivier Girard
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
-- * Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
-- * Neither the name of the authors nor the names of its contributors
-- may be used to endorse or promote products derived from this software
-- without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
-- OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-- THE POSSIBILITY OF SUCH DAMAGE
--
------------------------------------------------------------------------------
--
--! @file fmsp430.vhd
--!
--! @brief fpgaMSP430 Top level file
--
--! @author Olivier Girard, [email protected]
--! @author Emmanuel Amadio, [email protected] (VHDL Rewrite)
--
------------------------------------------------------------------------------
--! @version 1
--! @date: 2017-04-21
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all; -- standard unresolved logic UX01ZWLH-
use ieee.numeric_std.all; -- for the signed, unsigned types and arithmetic ops
use ieee.math_real.all;
use work.fmsp_misc_package.all;
use work.fmsp_core_package.all;
use work.fmsp_per_package.all;
use work.fmsp_dbg_package.all;
use work.fmsp_functions.all;
entity fmsp430 is
generic (
INST_NR : integer := 0; -- Current fmsp instance number (for multicore systems)
TOTAL_NR : integer := 0; -- Total number of fmsp instances-1 (for multicore systems)
PMEM_SIZE : integer := 32768; -- Program Memory Size
DMEM_SIZE : integer := 16384; -- Data Memory Size
PER_SIZE : integer := 16384; -- Peripheral Memory Size
MULTIPLIER : boolean := false; -- Include/Exclude Hardware Multiplier
USER_VERSION : integer := 0; -- Custom user version number
DEBUG_EN : boolean := false; -- Include/Exclude Serial Debug interface
WATCHDOG : boolean := false; -- Include/Exclude Watchdog timer
DMA_IF_EN : boolean := false; -- Include/Exclude DMA interface support
NMI_EN : boolean := false; -- Include/Exclude Non-Maskable-Interrupt support
IRQ_NR : integer := 16; -- Number of IRQs
SYNC_NMI_EN : boolean := true; --
SYNC_CPU_EN : boolean := true; --
SYNC_DBG_EN : boolean := true; --
SYNC_DBG_UART_RXD : boolean := true; -- Synchronize RXD inputs
DBG_UART : boolean := false; -- Enable UART (8N1) debug interface
DBG_I2C : boolean := true; -- Enable I2C debug interface
DBG_I2C_BROADCAST_EN : boolean := false; -- Enable the I2C broadcast address
DBG_RST_BRK_EN : boolean := false; -- CPU break on PUC reset
DBG_HWBRK_0_EN : boolean := false; -- Include hardware breakpoints unit
DBG_HWBRK_1_EN : boolean := false; -- Include hardware breakpoints unit
DBG_HWBRK_2_EN : boolean := false; -- Include hardware breakpoints unit
DBG_HWBRK_3_EN : boolean := false; -- Include hardware breakpoints unit
DBG_HWBRK_RANGE : boolean := true; -- Enable/Disable the hardware breakpoint RANGE mode
DBG_UART_AUTO_SYNC : boolean := true; -- Debug UART interface auto data synchronization
DBG_UART_BAUD : integer := 9600; -- Debug UART interface data rate
DBG_DCO_FREQ : integer := 20000000
);
port (
mclk : in std_logic; -- Main system clock
-- Inputs
lfxt_clk : in std_logic; -- Low frequency oscillator (typ 32kHz)
reset_n : in std_logic; -- Reset Pin (active low, asynchronous and non-glitchy)
cpu_en : in std_logic; -- Enable CPU code execution (asynchronous and non-glitchy)
nmi : in std_logic; -- Non-maskable interrupt (asynchronous and non-glitchy)
-- Debug interface
dbg_en : in std_logic; -- Debug interface enable (asynchronous and non-glitchy)
dbg_i2c_addr : in std_logic_vector(6 downto 0); -- Debug interface: I2C Address
dbg_i2c_broadcast : in std_logic_vector(6 downto 0); -- Debug interface: I2C Broadcast Address (for multicore systems)
dbg_i2c_scl : in std_logic; -- Debug interface: I2C SCL
dbg_i2c_sda_in : in std_logic; -- Debug interface: I2C SDA IN
dbg_i2c_sda_out : out std_logic := '1'; -- Debug interface: I2C SDA OUT
dbg_uart_rxd : in std_logic; -- Debug interface: UART RXD (asynchronous)
dbg_uart_txd : out std_logic := '1'; -- Debug interface: UART TXD
-- DMA access
dma_addr : in std_logic_vector(15 downto 1); -- Direct Memory Access address
dma_dout : out std_logic_vector(15 downto 0); -- Direct Memory Access data output
dma_din : in std_logic_vector(15 downto 0); -- Direct Memory Access data input
dma_en : in std_logic; -- Direct Memory Access enable (high active)
dma_we : in std_logic_vector(1 downto 0); -- Direct Memory Access write byte enable (high active)
dma_priority : in std_logic; -- Direct Memory Access priority (0:low / 1:high)
dma_ready : out std_logic; -- Direct Memory Access is complete
dma_resp : out std_logic; -- Direct Memory Access response (0:Okay / 1:Error)
-- Data memory
dmem_addr : out std_logic_vector(f_log2(DMEM_SIZE)-2 downto 0); -- Data Memory address
dmem_dout : in std_logic_vector(15 downto 0); -- Data Memory data output
dmem_din : out std_logic_vector(15 downto 0); -- Data Memory data input
dmem_wen : out std_logic_vector(1 downto 0); -- Data Memory write byte enable (low active)
dmem_cen : out std_logic; -- Data Memory chip enable (low active)
-- Program memory
pmem_addr : out std_logic_vector(f_log2(PMEM_SIZE)-2 downto 0); -- Program Memory address
pmem_dout : in std_logic_vector(15 downto 0); -- Program Memory data output
pmem_din : out std_logic_vector(15 downto 0); -- Program Memory data input (optional)
pmem_wen : out std_logic_vector(1 downto 0); -- Program Memory write enable (low active) (optional)
pmem_cen : out std_logic; -- Program Memory chip enable (low active)
-- Peripheral interface
per_irq : in std_logic_vector(IRQ_NR-3 downto 0); -- Maskable interrupts (14, 30 or 62)
per_irq_acc : out std_logic_vector(IRQ_NR-3 downto 0); -- Interrupt request accepted (one-hot signal)
per_rst : out std_logic; -- Main system reset
per_freeze : out std_logic; -- Freeze peripherals
per_aclk_en : out std_logic; -- FPGA ONLY: ACLK enable
per_smclk_en : out std_logic; -- FPGA ONLY: SMCLK enable
-- Peripheral memory
per_addr : out std_logic_vector(13 downto 0); -- Peripheral address
per_dout : in std_logic_vector(15 downto 0); -- Peripheral data output
per_din : out std_logic_vector(15 downto 0); -- Peripheral data input
per_we : out std_logic_vector(1 downto 0); -- Peripheral write byte enable (high active)
per_en : out std_logic -- Peripheral enable (high active)
);
end entity fmsp430;
architecture RTL of fmsp430 is
constant C_INST_NR : std_logic_vector(7 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(INST_NR,8));--x"00";
constant C_TOTAL_NR : std_logic_vector(7 downto 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(TOTAL_NR,8));--x"00";
--=============================================================================
-- 1) INTERNAL WIRES/REGISTERS/PARAMETERS DECLARATION
--=============================================================================
type core_wires_type is record
cpu_en : std_logic;
lfxt_clk : std_logic;
cpuoff : std_logic;
oscoff : std_logic;
scg1 : std_logic;
por : std_logic;
gie : std_logic;
cpu_id : std_logic_vector(31 downto 0);
nmi : std_logic;
nmi_acc : std_logic;
nmi_pnd : std_logic;
nmi_wkup : std_logic;
irq_acc : std_logic_vector(IRQ_NR-3 downto 0); -- Interrupt request accepted (one-hot signal)
dma_dout : std_logic_vector(15 downto 0); -- Direct Memory Access data output
dma_ready : std_logic; -- Direct Memory Access is complete
dma_resp : std_logic; -- Direct Memory Access response (0:Okay / 1:Error)
mrst : std_logic; -- Main system reset
end record;
type peripheral_wires_type is record
addr : std_logic_vector(13 downto 0); -- Peripheral address
din : std_logic_vector(15 downto 0); -- Peripheral data input
en : std_logic; -- Peripheral enable (high active)
we : std_logic_vector(1 downto 0); -- Peripheral write byte enable (high active)
aclk_en : std_logic; -- FPGA ONLY: ACLK enable
smclk_en : std_logic; -- FPGA ONLY: SMCLK enable
end record;
type dbg_wires_type is record
en : std_logic;
rst : std_logic;
puc_pnd_set : std_logic;
decode_noirq : std_logic;
pc : std_logic_vector(15 downto 0);
halt_cmd : std_logic;
halt_st : std_logic;
irq : std_logic;
wkup : std_logic;
cpu_reset : std_logic;
freeze : std_logic;
mem_addr : std_logic_vector(15 downto 0);
mem_dout : std_logic_vector(15 downto 0);
mem_din : std_logic_vector(15 downto 0);
mem_wr : std_logic_vector(1 downto 0);
mem_en : std_logic;
reg_din : std_logic_vector(15 downto 0);
reg_wr : std_logic;
eu_mab : std_logic_vector(15 downto 0);
eu_mdb_in : std_logic_vector(15 downto 0);
eu_mdb_out : std_logic_vector(15 downto 0);
eu_mb_wr : std_logic_vector(1 downto 0);
eu_mb_en : std_logic;
fe_mab : std_logic_vector(15 downto 0);
fe_mdb_in : std_logic_vector(15 downto 0);
fe_mb_en : std_logic;
fe_pmem_wait : std_logic;
end record;
type wdt_wires_type is record
ie : std_logic;
nmies : std_logic;
ifg : std_logic;
irq : std_logic;
wkup : std_logic;
cpu_reset : std_logic;
ifg_sw_clr : std_logic;
ifg_sw_set : std_logic;
end record;
signal wires : core_wires_type;
signal dbg_w : dbg_wires_type := ( en => '0',
rst => '0',
puc_pnd_set => '0',
decode_noirq => '0',
pc => x"0000",
halt_cmd => '0',
halt_st => '0',
irq => '0',
wkup => '0',
cpu_reset => '0',
freeze => '0',
mem_addr => x"0000",
mem_dout => x"0000",
mem_din => x"0000",
mem_wr => "00",
mem_en => '0',
reg_din => x"0000",
reg_wr => '0',
eu_mab => x"0000",
eu_mdb_in => x"0000",
eu_mdb_out => x"0000",
eu_mb_wr => "00",
eu_mb_en => '0',
fe_mab => x"0000",
fe_mdb_in => x"0000",
fe_mb_en => '0',
fe_pmem_wait => '0'
);
signal wdt_w : wdt_wires_type;
signal per_w : peripheral_wires_type;
signal per_dout_sfr : std_logic_vector(15 downto 0);
signal per_dout_clk : std_logic_vector(15 downto 0);
signal per_dout_wdt : std_logic_vector(15 downto 0) := x"0000";
signal per_dout_mpy : std_logic_vector(15 downto 0) := x"0000";
signal per_dout_or : std_logic_vector(15 downto 0);
begin
--=============================================================================
-- 1) CORE (<=> FETCH & DECODE & EXECUTE & MEMORY BACKBONE)
--=============================================================================
--! Synchronization
sync_cell_dbg_en : fmsp_sync_cell
generic map(
SYNC_EN => SYNC_DBG_EN
)
port map(
rst => wires.por,
clk => mclk,
data_in => dbg_en,
data_out => dbg_w.en
);
sync_cell_lfxt_clk : fmsp_sync_cell
generic map(
SYNC_EN => false
)
port map(
clk => mclk,
rst => wires.por,
data_in => lfxt_clk,
data_out => wires.lfxt_clk
);
sync_cell_cpu_en : fmsp_sync_cell
generic map(
SYNC_EN => SYNC_CPU_EN
)
port map(
clk => mclk,
rst => wires.por,
data_in => cpu_en,
data_out => wires.cpu_en
);
sync_cell_nmi : fmsp_sync_cell
generic map(
SYNC_EN => SYNC_NMI_EN
)
port map(
clk => mclk,
rst => wires.mrst,
data_in => nmi,
data_out => wires.nmi
);
--=============================================================================
-- 1) CORE (<=> FETCH & DECODE & EXECUTE & MEMORY BACKBONE)
--=============================================================================
core_unit : fmsp_core
generic map(
PMEM_SIZE => PMEM_SIZE, -- Program Memory Size
DMEM_SIZE => DMEM_SIZE, -- Data Memory Size
PER_SIZE => PER_SIZE,
DMA_IF_EN => DMA_IF_EN, -- Wakeup condition from DMA interface
IRQ_NR => IRQ_NR -- Number of IRQs
)
port map(
mclk => mclk, -- Main system clock
mrst => wires.mrst, -- Main system reset
-- Debug Interface
dbg_halt_cmd => dbg_w.halt_cmd, -- Debug interface Halt CPU command
dbg_halt_st => dbg_w.halt_st, -- Halt/Run status from CPU
dbg_reg_din => dbg_w.reg_din, -- Debug unit CPU register data input
dbg_reg_wr => dbg_w.reg_wr, -- Debug unit CPU register write
dbg_mem_addr => dbg_w.mem_addr, -- Debug address for rd/wr access
dbg_mem_dout => dbg_w.mem_dout, -- Debug unit data output
dbg_mem_din => dbg_w.mem_din, -- Debug unit Memory data input
dbg_mem_en => dbg_w.mem_en, -- Debug unit memory enable
dbg_mem_wr => dbg_w.mem_wr, -- Debug unit memory write
eu_mem_addr => dbg_w.eu_mab, -- Execution-Unit Memory address bus
eu_mem_en => dbg_w.eu_mb_en, -- Execution-Unit Memory bus enable
eu_mem_wr => dbg_w.eu_mb_wr, -- Execution-Unit Memory bus write transfer
fe_mem_din => dbg_w.fe_mdb_in, -- Frontend Memory data bus input
decode_noirq => dbg_w.decode_noirq, -- Frontend decode instruction
pc => dbg_w.pc, -- Program counter
-- DMA access
dma_addr => dma_addr, -- Direct Memory Access address
dma_dout => dma_dout, -- Direct Memory Access data output
dma_din => dma_din, -- Direct Memory Access data input
dma_we => dma_we, -- Direct Memory Access write byte enable (high active)
dma_en => dma_en, -- Direct Memory Access enable (high active)
dma_priority => dma_priority, -- Direct Memory Access priority (0:low / 1:high)
dma_ready => dma_ready, -- Direct Memory Access is complete
dma_resp => dma_resp, -- Direct Memory Access response (0:Okay / 1:Error)
-- Peripheral memory
per_addr => per_w.addr, -- Peripheral address
per_dout => per_dout_or, -- Peripheral data output
per_din => per_w.din, -- Peripheral data input
per_we => per_w.we, -- Peripheral write enable (high active)
per_en => per_w.en, -- Peripheral enable (high active)
-- Data memory
dmem_addr => dmem_addr, -- Data Memory address
dmem_dout => dmem_dout, -- Data Memory data output
dmem_din => dmem_din, -- Data Memory data input
dmem_wen => dmem_wen, -- Data Memory write enable (low active)
dmem_cen => dmem_cen, -- Data Memory chip enable (low active)
-- Program memory
pmem_addr => pmem_addr, -- Program Memory address
pmem_dout => pmem_dout, -- Program Memory data output
pmem_din => pmem_din, -- Program Memory data input (optional)
pmem_wen => pmem_wen, -- Program Memory write enable (low active) (optional)
pmem_cen => pmem_cen, -- Program Memory chip enable (low active)
-- Non Maskable Interrupt
nmi_pnd => wires.nmi_pnd, -- Non-maskable interrupt pending
nmi_wkup => wires.nmi_wkup, -- NMI Wakeup
nmi_acc => wires.nmi_acc, -- Non-Maskable interrupt request accepted
-- Watchdog Interrupt
wdt_irq => wdt_w.irq, -- Watchdog-timer interrupt
wdt_wkup => wdt_w.wkup, -- Watchdog Wakeup
-- Maskable Interrupt
irq => per_irq, -- Maskable interrupts
irq_acc => wires.irq_acc, -- Interrupt request accepted
--============
cpu_en_s => wires.cpu_en, -- Enable CPU code execution (synchronous)
cpuoff => wires.cpuoff, -- Turns off the CPU
oscoff => wires.oscoff, -- Turns off LFXT1 clock input
scg1 => wires.scg1 -- System clock generator 1. Turns off the SMCLK
);
--=============================================================================
-- 2) GLOBAL CLOCK & RESET MANAGEMENT
--=============================================================================
clock_module_0 : fmsp_clock_module
generic map(
INST_NR => INST_NR, -- Current fmsp instance number (for multicore systems)
TOTAL_NR => TOTAL_NR, -- Total number of fmsp instances-1 (for multicore systems)
PMEM_SIZE => PMEM_SIZE, -- Program Memory Size
DMEM_SIZE => DMEM_SIZE, -- Data Memory Size
PER_SIZE => PER_SIZE, -- Peripheral Memory Size
DEBUG_EN => DEBUG_EN, -- Include/Exclude Serial Debug interface
WATCHDOG => WATCHDOG, -- Include/Exclude Watchdog timer
DMA_IF_EN => DMA_IF_EN, -- Include/Exclude DMA interface support
NMI_EN => NMI_EN -- Include/Exclude Non-Maskable-Interrupt support
)
port map(
mclk => mclk, -- Main system clock
-- INPUTs
reset_n => reset_n, -- Reset Pin (low active, asynchronous)
lfxt_clk => wires.lfxt_clk, -- Low frequency oscillator (typ 32kHz)
cpu_en => wires.cpu_en, -- Enable CPU code execution (synchronous)
cpuoff => wires.cpuoff, -- Turns off the CPU
oscoff => wires.oscoff, -- Turns off LFXT1 clock input
scg1 => wires.scg1, -- System clock generator 1. Turns off the SMCLK
wdt_reset => wdt_w.cpu_reset, -- Watchdog-timer reset
-- OUTPUTs
por => wires.por, -- Power-on reset
puc_rst => wires.mrst, -- Main system reset
-- Debug Interface
dbg_rst => dbg_w.rst, -- Debug unit reset
dbg_en => dbg_w.en, -- Debug interface enable (synchronous)
puc_pnd_set => dbg_w.puc_pnd_set, -- PUC pending set for the serial debug interface
dbg_cpu_reset => dbg_w.cpu_reset, -- Reset CPU from debug interface
-- Peripheral interface
smclk_en => per_w.smclk_en, -- SMCLK enable
aclk_en => per_w.aclk_en, -- ACLK enable
per_addr => per_w.addr, -- Peripheral address
per_din => per_w.din, -- Peripheral data input
per_en => per_w.en, -- Peripheral enable (high active)
per_we => per_w.we, -- Peripheral write enable (high active)
per_dout => per_dout_clk -- Peripheral data output
);
--=============================================================================
-- 3) SPECIAL FUNCTION REGISTERS
--=============================================================================
sfr_0 : fmsp_sfr
generic map(
INST_NR => INST_NR, -- Current fmsp instance number (for multicore systems)
TOTAL_NR => TOTAL_NR, -- Total number of fmsp instances-1 (for multicore systems)
PMEM_SIZE => PMEM_SIZE, -- Program Memory Size
DMEM_SIZE => DMEM_SIZE, -- Data Memory Size
PER_SIZE => PER_SIZE, -- Peripheral Memory Size
MULTIPLIER => MULTIPLIER, -- Include/Exclude Hardware Multiplier
USER_VERSION => USER_VERSION, -- Custom user version number
WATCHDOG => WATCHDOG, -- Include/Exclude Watchdog timer
NMI_EN => NMI_EN -- Include/Exclude Non-Maskable-Interrupt support
)
port map(
mclk => mclk, -- Main system clock
mrst => wires.mrst, -- Main system reset
cpu_id => wires.cpu_id, -- CPU ID
-- Non Maskable Interrupt
nmi => wires.nmi, -- Non-maskable interrupt (asynchronous)
nmi_acc => wires.nmi_acc, -- Non-Maskable interrupt request accepted
nmi_pnd => wires.nmi_pnd, -- NMI Pending
nmi_wkup => wires.nmi_wkup, -- NMI Wakeup
-- Watchdog Interface
wdtie => wdt_w.ie, -- Watchdog-timer interrupt enable
wdtifg => wdt_w.ifg, -- Watchdog-timer interrupt flag
wdtifg_sw_clr => wdt_w.ifg_sw_clr, -- Watchdog-timer interrupt flag software clear
wdtifg_sw_set => wdt_w.ifg_sw_set, -- Watchdog-timer interrupt flag software set
wdtnmies => wdt_w.nmies, -- Watchdog-timer NMI edge selection
-- Peripheral interface
per_addr => per_w.addr, -- Peripheral address
per_din => per_w.din, -- Peripheral data input
per_en => per_w.en, -- Peripheral enable (high active)
per_we => per_w.we, -- Peripheral write enable (high active)
per_dout => per_dout_sfr -- Peripheral data output
);
--=============================================================================
-- 4) WATCHDOG TIMER
--=============================================================================
ADD_WATCHDOG : if WATCHDOG generate
watchdog : fmsp_watchdog
port map(
mclk => mclk, -- Main system clock
mrst => wires.mrst, -- Main system reset
por => wires.por, -- Power-on reset
-- INPUTs
dbg_freeze => dbg_w.freeze, -- Freeze Watchdog counter
wdtie => wdt_w.ie, -- Watchdog-timer interrupt enable
wdtifg_irq_clr => wires.irq_acc(IRQ_NR-6), -- Clear Watchdog-timer interrupt flag
wdtifg_sw_clr => wdt_w.ifg_sw_clr, -- Watchdog-timer interrupt flag software clear
wdtifg_sw_set => wdt_w.ifg_sw_set, -- Watchdog-timer interrupt flag software set
-- OUTPUTs
wdt_reset => wdt_w.cpu_reset, -- Watchdog-timer reset
wdt_irq => wdt_w.irq, -- Watchdog-timer interrupt
wdt_wkup => wdt_w.wkup, -- Watchdog Wakeup
wdtifg => wdt_w.ifg, -- Watchdog-timer interrupt flag
wdtnmies => wdt_w.nmies, -- Watchdog-timer NMI edge selection
-- Peripheral interface
aclk_en => per_w.aclk_en, -- ACLK enable
smclk_en => per_w.smclk_en, -- SMCLK enable
per_addr => per_w.addr, -- Peripheral address
per_din => per_w.din, -- Peripheral data input
per_en => per_w.en, -- Peripheral enable (high active)
per_we => per_w.we, -- Peripheral write enable (high active)
per_dout => per_dout_wdt -- Peripheral data output
);
end generate ADD_WATCHDOG;
--=============================================================================
-- 5) HARDWARE MULTIPLIER
--=============================================================================
ADD_MULTIPLIER : if MULTIPLIER generate
multiplier : fmsp_multiplier
port map(
mclk => mclk, -- Main system clock
mrst => wires.mrst, -- Main system reset
-- Peripheral interface
per_addr => per_w.addr, -- Peripheral address
per_din => per_w.din, -- Peripheral data input
per_en => per_w.en, -- Peripheral enable (high active)
per_we => per_w.we, -- Peripheral write enable (high active)
per_dout => per_dout_mpy -- Peripheral data output
);
end generate ADD_MULTIPLIER;
--=============================================================================
-- 6) PERIPHERALS' OUTPUT BUS
--=============================================================================
per_dout_or <= per_dout
or per_dout_clk
or per_dout_sfr
or per_dout_wdt
or per_dout_mpy;
--=============================================================================
-- 7) DEBUG INTERFACE
--=============================================================================
dbg : fmsp_dbg
generic map(
DBG_DCO_FREQ => DBG_DCO_FREQ, -- Debug mclk frequency
DBG_UART => DBG_UART, -- Enable UART (8N1) debug interface
DBG_UART_AUTO_SYNC => DBG_UART_AUTO_SYNC, -- Debug UART interface auto data synchronization
DBG_UART_BAUD => DBG_UART_BAUD, -- Debug UART interface data rate
DBG_I2C => DBG_I2C, -- Enable I2C debug interface
DBG_I2C_BROADCAST_EN => DBG_I2C_BROADCAST_EN, -- Enable the I2C broadcast address
DBG_RST_BRK_EN => DBG_RST_BRK_EN, -- CPU break on PUC reset
DBG_HWBRK_0_EN => DBG_HWBRK_0_EN, -- Include hardware breakpoints unit
DBG_HWBRK_1_EN => DBG_HWBRK_1_EN, -- Include hardware breakpoints unit
DBG_HWBRK_2_EN => DBG_HWBRK_2_EN, -- Include hardware breakpoints unit
DBG_HWBRK_3_EN => DBG_HWBRK_3_EN, -- Include hardware breakpoints unit
DBG_HWBRK_RANGE => DBG_HWBRK_RANGE, -- Enable/Disable the hardware breakpoint RANGE mode
SYNC_DBG_UART_RXD => SYNC_DBG_UART_RXD -- Synchronize RXD inputs
)
port map(
dbg_clk => mclk, -- Debug unit clock
dbg_rst => dbg_w.rst, -- Debug unit reset
-- INPUTs
cpu_nr_inst => C_INST_NR, -- Current fmsp instance number
cpu_nr_total => C_TOTAL_NR, -- Total number of fmsp instances-1
cpu_id => wires.cpu_id, -- CPU ID
cpu_en_s => wires.cpu_en, -- Enable CPU code execution (synchronous)
dbg_en_s => dbg_w.en, -- Debug interface enable (synchronous)
dbg_halt_st => dbg_w.halt_st, -- Halt/Run status from CPU
-- I2C Interface
dbg_i2c_addr => dbg_i2c_addr, -- Debug interface: I2C Address
dbg_i2c_broadcast => dbg_i2c_broadcast, -- Debug interface: I2C Broadcast Address (for multicore systems)
dbg_i2c_scl => dbg_i2c_scl, -- Debug interface: I2C SCL
dbg_i2c_sda_in => dbg_i2c_sda_in, -- Debug interface: I2C SDA IN
dbg_i2c_sda_out => dbg_i2c_sda_out, -- Debug interface: I2C SDA OUT
-- UART Interface
dbg_uart_rxd => dbg_uart_rxd, -- Debug interface: UART RXD (asynchronous)
dbg_uart_txd => dbg_uart_txd, -- Debug interface: UART TXD
-- Core interface
dbg_mem_din => dbg_w.mem_din, -- Debug unit Memory data input
dbg_mem_addr => dbg_w.mem_addr, -- Debug address for rd/wr access
dbg_mem_dout => dbg_w.mem_dout, -- Debug unit data output
dbg_mem_en => dbg_w.mem_en, -- Debug unit memory enable
dbg_mem_wr => dbg_w.mem_wr, -- Debug unit memory write
dbg_reg_din => dbg_w.reg_din, -- Debug unit CPU register data input
decode_noirq => dbg_w.decode_noirq, -- Frontend decode instruction
eu_mab => dbg_w.eu_mab, -- Execution-Unit Memory address bus
eu_mb_en => dbg_w.eu_mb_en, -- Execution-Unit Memory bus enable
eu_mb_wr => dbg_w.eu_mb_wr, -- Execution-Unit Memory bus write transfer
fe_mdb_in => dbg_w.fe_mdb_in, -- Frontend Memory data bus input
pc => dbg_w.pc, -- Program counter
puc_pnd_set => dbg_w.puc_pnd_set, -- PUC pending set for the serial debug interface
-- OUTPUTs
dbg_cpu_reset => dbg_w.cpu_reset, -- Reset CPU from debug interface
dbg_freeze => dbg_w.freeze, -- Freeze peripherals
dbg_halt_cmd => dbg_w.halt_cmd, -- Halt CPU command
dbg_reg_wr => dbg_w.reg_wr -- Debug unit CPU register write
);
-- Peripheral interface
per_irq_acc <= wires.irq_acc; -- Interrupt request accepted (one-hot signal)
per_rst <= wires.mrst; -- Main system reset
per_freeze <= dbg_w.freeze; -- Freeze peripherals
per_aclk_en <= per_w.aclk_en; -- ACLK enable
per_smclk_en <= per_w.smclk_en; -- FPGA ONLY: SMCLK enable
per_addr <= per_w.addr; -- Peripheral address
per_din <= per_w.din; -- Peripheral data input
per_en <= per_w.en; -- Peripheral enable (high active)
per_we <= per_w.we; -- Peripheral write enable (high active)
end RTL; -- fmsp430
|
bsd-3-clause
|
FelixWinterstein/Vivado-KMeans
|
filtering_algorithm_RTL/source/vhdl/filtering_algorithm_single.vhd
|
1
|
24146
|
----------------------------------------------------------------------------------
-- Felix Winterstein, Imperial College London
--
-- Module Name: filtering_alogrithm_single - Behavioral
--
-- Revision 1.01
-- Additional Comments: distributed under a BSD license, see LICENSE.txt
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use ieee.math_real.all;
use work.filtering_algorithm_pkg.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity filtering_alogrithm_single is
port (
clk : in std_logic;
sclr : in std_logic;
start : in std_logic;
-- initial parameters
k : in centre_index_type;
root_address : in node_address_type;
-- init node and centre memory
wr_init_cent : in std_logic;
wr_centre_list_address_init : in centre_list_address_type;
wr_centre_list_data_init : in centre_index_type;
wr_init_node : in std_logic;
wr_node_address_init : in node_address_type;
wr_node_data_init : in node_data_type;
wr_init_pos : in std_logic;
wr_centre_list_pos_address_init : in centre_index_type;
wr_centre_list_pos_data_init : in data_type;
-- access centre buffer
rdo_centre_buffer : in std_logic;
centre_buffer_addr : in centre_index_type;
valid : out std_logic;
wgtCent_out : out data_type_ext;
sum_sq_out : out coord_type_ext;
count_out : out coord_type;
-- processing done
rdy : out std_logic
);
end filtering_alogrithm_single;
architecture Behavioral of filtering_alogrithm_single is
constant STACK_LAT : integer := 3;
type state_type is (idle, init, processing_phase1, processing_phase2, done);
type schedule_state_type is (free, busy, wait_cycle);
type node_addr_delay_type is array(0 to STACK_LAT-1) of node_address_type;
type centre_list_addr_delay_type is array(0 to STACK_LAT-1) of centre_list_address_type;
type k_delay_type is array(0 to STACK_LAT-1) of centre_index_type;
component memory_mgmt
port (
clk : in std_logic;
sclr : in std_logic;
rd : in std_logic;
rd_node_addr : in node_address_type;
rd_centre_list_address : in centre_list_address_type;
rd_k : in centre_index_type;
wr_cent_nd : in std_logic;
wr_cent : in std_logic;
wr_centre_list_address : in centre_list_address_type;
wr_centre_list_data : in centre_index_type;
wr_init_cent : in std_logic;
wr_centre_list_address_init : in centre_list_address_type;
wr_centre_list_data_init : in centre_index_type;
wr_init_node : in std_logic;
wr_node_address_init : in node_address_type;
wr_node_data_init : in node_data_type;
wr_init_pos : in std_logic;
wr_centre_list_pos_address_init : in centre_index_type;
wr_centre_list_pos_data_init : in data_type;
valid : out std_logic;
rd_node_data : out node_data_type;
rd_centre_list_data : out centre_index_type;
rd_centre_list_pos_data : out data_type;
last_centre : out std_logic;
item_read_twice : out std_logic;
rd_centre_list_address_out : out centre_list_address_type
);
end component;
component process_tree_node
port (
clk : in std_logic;
sclr : in std_logic;
nd : in std_logic;
u_in : in node_data_type;
centre_positions_in : in data_type;
centre_indices_in : in centre_index_type;
update_centre_buffer : out std_logic;
final_index_out : out centre_index_type;
sum_sq_out : out coord_type_ext;
rdy : out std_logic;
dead_end : out std_logic;
u_out : out node_data_type;
k_out : out centre_index_type;
centre_index_rdy : out std_logic;
centre_index_wr : out std_logic;
centre_indices_out : out centre_index_type
);
end component;
component centre_buffer_mgmt
port (
clk : in std_logic;
sclr : in std_logic;
nd : in std_logic;
init : in std_logic;
addr_in_init : in centre_index_type;
request_rdo : in std_logic;
addr_in : in centre_index_type;
wgtCent_in : in data_type_ext;
sum_sq_in : in coord_type_ext;
count_in : in coord_type;
valid : out std_logic;
wgtCent_out : out data_type_ext;
sum_sq_out : out coord_type_ext;
count_out : out coord_type
);
end component;
component stack_top
port (
clk : in STD_LOGIC;
sclr : in STD_LOGIC;
push : in std_logic;
pop : in std_logic;
node_addr_in_1 : in node_address_type;
node_addr_in_2 : in node_address_type;
cntr_addr_in_1 : in centre_list_address_type;
cntr_addr_in_2 : in centre_list_address_type;
k_in_1 : in centre_index_type;
k_in_2 : in centre_index_type;
node_addr_out : out node_address_type;
cntr_addr_out : out centre_list_address_type;
k_out : out centre_index_type;
empty : out std_logic;
valid : out std_logic
);
end component;
component allocator
generic (
MEMORY_SIZE : integer := 1024
);
port (
clk : in std_logic;
sclr : in std_logic;
alloc : in std_logic;
free : in std_logic;
address_in : in std_logic_vector(integer(ceil(log2(real(MEMORY_SIZE))))-1 downto 0);
rdy : out std_logic;
address_out : out std_logic_vector(integer(ceil(log2(real(MEMORY_SIZE))))-1 downto 0);
heap_full : out std_logic
);
end component;
-- fsm
signal state : state_type;
signal start_processing : std_logic;
signal processing_done : std_logic;
signal processing_counter_enable : std_logic;
signal processing_done_value : unsigned(INDEX_BITWIDTH+1-1 downto 0);
signal processing_done_counter : unsigned(INDEX_BITWIDTH+1-1 downto 0);
-- memory mgmt
signal memory_mgmt_rd : std_logic;
signal memory_data_valid : std_logic;
signal memory_mgmt_last_centre : std_logic;
signal memory_mgmt_item_read_twice : std_logic;
--signal memory_data_valid_reg : std_logic;
signal rd_node_addr : node_address_type;
signal rd_centre_list_address : centre_list_address_type;
signal rd_k : centre_index_type;
signal rd_node_data : node_data_type;
signal rd_centre_indices : centre_index_type;
signal rd_centre_positions : data_type;
signal rd_centre_list_address_out : centre_list_address_type;
signal rd_centre_list_address_out_reg : centre_list_address_type;
-- process_tree_node
signal ptn_update_centre_buffer : std_logic;
signal ptn_final_index_out : centre_index_type;
signal ptn_sum_sq_out : coord_type_ext;
signal ptn_rdy : std_logic;
signal ptn_dead_end : std_logic;
signal ptn_u_out : node_data_type;
signal ptn_k_out : centre_index_type;
signal ptn_centre_index_rdy : std_logic;
signal ptn_centre_index_rdy_reg : std_logic;
signal ptn_centre_index_wr : std_logic;
signal ptn_centre_indices_out : centre_index_type;
-- centre buffer mgmt
signal tmp_addr : centre_index_type;
-- stack
signal stack_push : std_logic;
signal stack_push_reg : std_logic;
signal stack_pop : std_logic;
signal node_stack_addr_in_1 : node_address_type;
signal node_stack_addr_in_2 : node_address_type;
signal cntr_stack_addr_in : centre_list_address_type;
signal cntr_stack_addr_in_reg : centre_list_address_type;
signal cntr_stack_k_in : centre_index_type;
signal stack_valid : std_logic;
signal stack_empty : std_logic;
signal node_stack_addr_out : node_address_type;
signal cntr_stack_addr_out : centre_list_address_type;
signal cntr_stack_k_out : centre_index_type;
-- scheduler
signal schedule_state : schedule_state_type;
signal schedule_counter : centre_index_type;
signal schedule_counter_done : std_logic;
signal schedule_k_reg : centre_index_type;
signal schedule_next : std_logic;
-- allocator
signal allocator_free : std_logic;
signal allocator_free_1 : std_logic;
signal allocator_free_2 : std_logic;
signal allocator_free_reg : std_logic;
signal allocator_free_address : centre_list_address_type;
signal allocator_alloc : std_logic;
signal allocator_rdy : std_logic;
signal allocator_address_out : centre_list_address_type;
signal allocator_address_out_reg : centre_list_address_type;
signal allocator_heap_full : std_logic;
-- debug and stats (not synthesised)
signal debug_u_left : node_address_type;
signal debug_u_right : node_address_type;
signal first_start : std_logic := '0';
signal visited_nodes : unsigned(31 downto 0);
signal cycle_count : unsigned(31 downto 0);
signal debug_stack_counter : unsigned(31 downto 0);
signal debug_max_stack_counter : unsigned(31 downto 0);
begin
G_NOSYNTH_0 : if SYNTHESIS = false generate
-- some statistics
vn_counter_proc : process(clk)
begin
if rising_edge(clk) then
if sclr = '1' then
visited_nodes <= (others=> '0');
elsif ptn_rdy = '1' then
visited_nodes <= visited_nodes+1;
end if;
if start = '1' then
first_start <= '1'; -- latch the first start assertion
end if;
if first_start = '0' then
cycle_count <= (others=> '0');
else -- count cycles for all iterations
cycle_count <= cycle_count+1;
end if;
if sclr = '1' then
debug_stack_counter <= (others=>'0');
debug_max_stack_counter <= (others=>'0');
else
if debug_max_stack_counter < debug_stack_counter then
debug_max_stack_counter <= debug_stack_counter;
end if;
if stack_push = '1' AND stack_pop = '0' then
debug_stack_counter <= debug_stack_counter+2;
elsif stack_push = '0' AND stack_pop = '1' then
debug_stack_counter <= debug_stack_counter-1;
end if;
end if;
end if;
end process vn_counter_proc;
end generate G_NOSYNTH_0;
fsm_proc : process(clk)
begin
if rising_edge(clk) then
if sclr = '1' then
-- state <= idle;
--elsif state = idle AND wr_init_pos = '1' then
state <= init;
elsif state = init AND start = '1' then
state <= processing_phase1;
elsif state = processing_phase1 AND ptn_rdy = '1' then
state <= processing_phase2;
elsif state = processing_phase2 AND processing_done = '1' then
state <= done;
elsif state = done then
state <= init;
end if;
end if;
end process fsm_proc;
start_processing <= '1' WHEN state = init AND start = '1' ELSE '0';
-- scheduler (decides when the next item is popped from stack)
scheduler_proc : process(clk)
--variable var_schedule_next : std_logic;
--variable var_counter_done : std_logic;
begin
if rising_edge(clk) then
--var_schedule_next := '0';
if schedule_state = busy AND stack_valid = '1' then
schedule_k_reg <= cntr_stack_k_out;
elsif schedule_state = free then
schedule_k_reg <= (others => '1');
end if;
if sclr = '1' then
schedule_state <= free;
elsif schedule_state = free AND schedule_next = '1' then
schedule_state <= busy;
elsif schedule_state = busy AND schedule_counter_done = '1' then
schedule_state <= free;
end if;
if sclr = '1' OR schedule_state = free then
schedule_counter <= to_unsigned(0,INDEX_BITWIDTH);
elsif schedule_state = busy AND schedule_counter_done = '0' then
schedule_counter <= schedule_counter+1;
end if;
end if;
end process scheduler_proc;
schedule_next <= '1' WHEN schedule_state = free AND stack_empty = '0' AND stack_push = '0' AND stack_push_reg = '0' ELSE '0';
schedule_counter_done <= '1' WHEN (stack_valid = '1' AND schedule_counter >= cntr_stack_k_out) OR (stack_valid = '0' AND schedule_counter >= schedule_k_reg) ELSE '0';
memory_mgmt_rd <= stack_valid WHEN state = processing_phase2 ELSE start_processing;
rd_node_addr <= root_address WHEN start_processing = '1' ELSE
node_stack_addr_out;
rd_centre_list_address <= std_logic_vector(to_unsigned(0,CNTR_POINTER_BITWIDTH)) WHEN start_processing = '1' ELSE
cntr_stack_addr_out;
rd_k <= k WHEN start_processing = '1' ELSE
cntr_stack_k_out;
memory_mgmt_inst : memory_mgmt
port map (
clk => clk,
sclr => sclr,
rd => memory_mgmt_rd,
rd_node_addr => rd_node_addr,
rd_centre_list_address => rd_centre_list_address,
rd_k => rd_k,
wr_cent_nd => ptn_centre_index_rdy,
wr_cent => ptn_centre_index_wr,
wr_centre_list_address => allocator_address_out,
wr_centre_list_data => ptn_centre_indices_out,
wr_init_cent => wr_init_cent,
wr_centre_list_address_init => wr_centre_list_address_init,
wr_centre_list_data_init => wr_centre_list_data_init,
wr_init_node => wr_init_node,
wr_node_address_init => wr_node_address_init,
wr_node_data_init => wr_node_data_init,
wr_init_pos => wr_init_pos,
wr_centre_list_pos_address_init => wr_centre_list_pos_address_init,
wr_centre_list_pos_data_init => wr_centre_list_pos_data_init,
valid => memory_data_valid,
rd_node_data => rd_node_data,
rd_centre_list_data => rd_centre_indices,
rd_centre_list_pos_data => rd_centre_positions,
last_centre => memory_mgmt_last_centre,
item_read_twice => memory_mgmt_item_read_twice,
rd_centre_list_address_out => rd_centre_list_address_out
);
process_tree_node_inst : process_tree_node
port map (
clk => clk,
sclr => sclr,
nd => memory_data_valid,
u_in => rd_node_data,
centre_positions_in => rd_centre_positions,
centre_indices_in => rd_centre_indices,
update_centre_buffer => ptn_update_centre_buffer,
final_index_out => ptn_final_index_out,
sum_sq_out => ptn_sum_sq_out,
rdy => ptn_rdy,
dead_end => ptn_dead_end,
u_out => ptn_u_out,
k_out => ptn_k_out,
centre_index_rdy => ptn_centre_index_rdy,
centre_index_wr => ptn_centre_index_wr,
centre_indices_out => ptn_centre_indices_out
);
debug_u_left <= ptn_u_out.left;
debug_u_right <= ptn_u_out.right;
tmp_addr <= ptn_final_index_out WHEN rdo_centre_buffer = '0' ELSE centre_buffer_addr;
centre_buffer_mgmt_inst : centre_buffer_mgmt
port map (
clk => clk,
sclr => sclr,
init => wr_init_pos,
addr_in_init => wr_centre_list_pos_address_init,
nd => ptn_update_centre_buffer,
request_rdo => rdo_centre_buffer,
addr_in => tmp_addr,
wgtCent_in => ptn_u_out.wgtCent,
sum_sq_in => ptn_sum_sq_out,
count_in => ptn_u_out.count,
valid => valid,
wgtCent_out => wgtCent_out,
sum_sq_out => sum_sq_out,
count_out => count_out
);
-- used to prevent pops right after a push
stack_push_reg_proc : process(clk)
begin
if rising_edge(clk) then
if sclr = '1' then
stack_push_reg <= '0';
else
stack_push_reg <= stack_push;
end if;
end if;
end process stack_push_reg_proc;
stack_pop <= schedule_next;
stack_push <= ptn_rdy AND NOT(ptn_dead_end);
node_stack_addr_in_1 <= ptn_u_out.right;
node_stack_addr_in_2 <= ptn_u_out.left;
stack_top_inst : stack_top
port map(
clk => clk,
sclr => sclr,
push => stack_push,
pop => stack_pop,
node_addr_in_1 => node_stack_addr_in_1,
node_addr_in_2 => node_stack_addr_in_2,
cntr_addr_in_1 => cntr_stack_addr_in,
cntr_addr_in_2 => cntr_stack_addr_in,
k_in_1 => cntr_stack_k_in,
k_in_2 => cntr_stack_k_in,
node_addr_out => node_stack_addr_out,
cntr_addr_out => cntr_stack_addr_out,
k_out => cntr_stack_k_out,
empty => stack_empty,
valid => stack_valid
);
G_NO_DYN_ALLOC : if DYN_ALLOC = false generate
-- generate a unique address for each centre list written to memory
inc_centre_list_addr_proc : process(clk)
variable new_cntr_stack_addr_in : unsigned(CNTR_POINTER_BITWIDTH-1 downto 0);
begin
if rising_edge(clk) then
if sclr = '1' then
cntr_stack_addr_in <= std_logic_vector(to_unsigned(1,CNTR_POINTER_BITWIDTH));
else
if ptn_rdy = '1' AND ptn_dead_end = '0' then
new_cntr_stack_addr_in := unsigned(cntr_stack_addr_in)+1;
cntr_stack_addr_in <= std_logic_vector(new_cntr_stack_addr_in);
end if;
end if;
end if;
end process inc_centre_list_addr_proc;
cntr_stack_k_in <= ptn_k_out;
allocator_address_out <= cntr_stack_addr_in;
end generate G_NO_DYN_ALLOC;
G_DYN_ALLOC : if DYN_ALLOC = true generate
allocator_ctrl_proc : process(clk)
begin
if rising_edge(clk) then
if sclr = '1' then
ptn_centre_index_rdy_reg <= '0';
allocator_free_reg <= '0';
else
ptn_centre_index_rdy_reg <= ptn_centre_index_rdy;
if allocator_free_1 = '1' AND allocator_free_2 = '1' then --two free requests at the same time?
allocator_free_reg <= '1';
else
allocator_free_reg <= '0';
end if;
end if;
if allocator_rdy = '1' then
allocator_address_out_reg <= allocator_address_out;
end if ;
rd_centre_list_address_out_reg <= rd_centre_list_address_out;
end if;
end process allocator_ctrl_proc;
allocator_free_1 <= ptn_rdy AND ptn_dead_end;
allocator_free_2 <= memory_mgmt_last_centre AND memory_mgmt_item_read_twice;
allocator_free_address <= allocator_address_out_reg WHEN (allocator_free_1 = '1' AND allocator_free_2 = '0') OR (allocator_free_1 = '1' AND allocator_free_2 = '1') ELSE
rd_centre_list_address_out WHEN allocator_free_1 = '0' AND allocator_free_2 = '1' ELSE
rd_centre_list_address_out_reg;
allocator_free <= allocator_free_1 OR allocator_free_2 OR allocator_free_reg;
allocator_alloc <= ptn_centre_index_rdy AND NOT(ptn_centre_index_rdy_reg); -- first cycle only --ptn_rdy AND NOT(ptn_dead_end);
allocator_inst : allocator
generic map (
MEMORY_SIZE => HEAP_SIZE
)
port map (
clk => clk,
sclr => wr_init_node,--sclr,
alloc => allocator_alloc,
free => allocator_free,
address_in => allocator_free_address,
rdy => allocator_rdy,
address_out => allocator_address_out,
heap_full => allocator_heap_full
);
cntr_stack_addr_in <= allocator_address_out_reg;
cntr_stack_k_in <= k WHEN allocator_address_out_reg = std_logic_vector(to_unsigned(0,CNTR_POINTER_BITWIDTH)) ELSE ptn_k_out;
end generate G_DYN_ALLOC;
processing_done_counter_proc : process(clk)
begin
if rising_edge(clk) then
if start_processing = '1' then
processing_done_value <= k+to_unsigned(38+100,INDEX_BITWIDTH+1);
end if;
if sclr = '1' OR state = processing_phase1 OR state = done then
processing_counter_enable <= '0';
else
if state = processing_phase2 AND ptn_rdy = '1' then
processing_counter_enable <= '1';
end if;
end if;
if sclr = '1' OR state = processing_phase1 then
processing_done_counter <= (others => '0');
elsif processing_counter_enable = '1' AND ptn_rdy = '0' then
processing_done_counter <= processing_done_counter+1;
elsif processing_counter_enable = '1' AND ptn_rdy = '1' then
processing_done_counter <= (others => '0');
end if;
end if;
end process processing_done_counter_proc;
-- output
processing_done <= '1' WHEN processing_done_counter = processing_done_value ELSE '0';
rdy <= processing_done;
end Behavioral;
|
bsd-3-clause
|
cookiezisk/ace-builds
|
demo/kitchen-sink/docs/vhdl.vhd
|
472
|
830
|
library IEEE
user IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity COUNT16 is
port (
cOut :out std_logic_vector(15 downto 0); -- counter output
clkEn :in std_logic; -- count enable
clk :in std_logic; -- clock input
rst :in std_logic -- reset input
);
end entity;
architecture count_rtl of COUNT16 is
signal count :std_logic_vector (15 downto 0);
begin
process (clk, rst) begin
if(rst = '1') then
count <= (others=>'0');
elsif(rising_edge(clk)) then
if(clkEn = '1') then
count <= count + 1;
end if;
end if;
end process;
cOut <= count;
end architecture;
|
bsd-3-clause
|
FelixWinterstein/Vivado-KMeans
|
filtering_algorithm_RTL/source/vhdl/centre_stack_mgmt.vhd
|
1
|
6178
|
----------------------------------------------------------------------------------
-- Felix Winterstein, Imperial College London
--
-- Module Name: centre_stack_mgmt - Behavioral
--
-- Revision 1.01
-- Additional Comments: distributed under a BSD license, see LICENSE.txt
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use ieee.math_real.all;
use work.filtering_algorithm_pkg.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity centre_stack_mgmt is
port (
clk : in STD_LOGIC;
sclr : in STD_LOGIC;
push : in std_logic;
pop : in std_logic;
cntr_addr_in : in centre_list_address_type;
k_in : in centre_index_type;
cntr_addr_out : out centre_list_address_type;
k_out : out centre_index_type;
empty : out std_logic;
valid : out std_logic
);
end centre_stack_mgmt;
architecture Behavioral of centre_stack_mgmt is
constant MEM_LAT : integer := 2;
constant STACK_POINTER_BITWIDTH : integer := integer(ceil(log2(real(STACK_SIZE))));
type stack_pointer_delay_line_type is array(0 to MEM_LAT-1) of unsigned(STACK_POINTER_BITWIDTH-1 downto 0);
component centre_stack_memory
port (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(STACK_POINTER_BITWIDTH-1 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(CNTR_POINTER_BITWIDTH+INDEX_BITWIDTH-1 DOWNTO 0);
clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(STACK_POINTER_BITWIDTH-1 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(CNTR_POINTER_BITWIDTH+INDEX_BITWIDTH-1 DOWNTO 0)
);
end component;
signal stack_pointer : unsigned(STACK_POINTER_BITWIDTH-1 downto 0);
signal pop_reg : std_logic;
signal push_reg : std_logic;
signal tmp_stack_addr_rd : unsigned(STACK_POINTER_BITWIDTH-1 downto 0);
signal stack_addr_rd_reg : unsigned(STACK_POINTER_BITWIDTH-1 downto 0);
signal tmp_addr_item : std_logic_vector(CNTR_POINTER_BITWIDTH-1 downto 0);
signal rec_stack_pointer : std_logic_vector(CNTR_POINTER_BITWIDTH-1 downto 0);
signal tmp_cntr_stack_din : std_logic_vector(CNTR_POINTER_BITWIDTH+INDEX_BITWIDTH-1 downto 0);
signal tmp_empty : std_logic;
signal tmp_cntr_stack_dout : std_logic_vector(CNTR_POINTER_BITWIDTH+INDEX_BITWIDTH-1 downto 0);
signal rdy_delay_line : std_logic_vector(0 to MEM_LAT-1);
signal emp_delay_line : std_logic_vector(0 to MEM_LAT-1);
signal stack_pointer_delay_line : stack_pointer_delay_line_type;
begin
update_stack_ptr_proc : process(clk)
begin
if rising_edge(clk) then
if sclr = '1' then
stack_pointer <= to_unsigned(0,STACK_POINTER_BITWIDTH);--(others => '0');
else
if push = '1' AND pop = '0' then
stack_pointer <= stack_pointer+1;
elsif push = '0' AND pop = '1' then
stack_pointer <= stack_pointer-1;
elsif push = '1' AND pop = '1' then
stack_pointer <= stack_pointer; -- add 1, remove 1
end if;
end if;
end if;
end process update_stack_ptr_proc;
tmp_stack_addr_rd <= stack_pointer-1;
tmp_empty <= '1' WHEN stack_pointer = 0 ELSE '0';
input_reg_proc : process(clk)
begin
if rising_edge(clk) then
if sclr = '1' then
pop_reg <= '0';
--push_reg <= '0';
else
pop_reg <= pop;
stack_addr_rd_reg <= tmp_stack_addr_rd;
--push_reg <= push;
--rec_stack_pointer <= std_logic_vector(stack_pointer);
end if;
end if;
end process input_reg_proc;
--tmp_addr_item <= rec_stack_pointer(CNTR_POINTER_BITWIDTH-1 downto 1) & '0' WHEN push='1' AND push_reg='1' ELSE std_logic_vector(stack_pointer(CNTR_POINTER_BITWIDTH-1 downto 1)) & '0';
tmp_cntr_stack_din(CNTR_POINTER_BITWIDTH+INDEX_BITWIDTH-1 downto INDEX_BITWIDTH) <= std_logic_vector(cntr_addr_in);
tmp_cntr_stack_din(INDEX_BITWIDTH-1 downto 0) <= std_logic_vector(k_in);
centre_stack_memory_inst_1 : centre_stack_memory
port map (
clka => clk,
wea(0) => push,
addra => std_logic_vector(stack_pointer),
dina => tmp_cntr_stack_din,
clkb => clk,
addrb => std_logic_vector(tmp_stack_addr_rd),--std_logic_vector(stack_addr_rd_reg),
doutb => tmp_cntr_stack_dout
);
delay_line_proc : process(clk)
begin
if rising_edge(clk) then
if sclr = '1' then
rdy_delay_line <= (others => '0');
emp_delay_line <= (others => '0');
else
rdy_delay_line(0) <= pop;--pop_reg;
rdy_delay_line(1 to MEM_LAT-1) <= rdy_delay_line(0 to MEM_LAT-2);
stack_pointer_delay_line(0) <= tmp_stack_addr_rd;--stack_pointer;
stack_pointer_delay_line(1 to MEM_LAT-1) <= stack_pointer_delay_line(0 to MEM_LAT-2);
end if;
end if;
end process delay_line_proc;
cntr_addr_out <= tmp_cntr_stack_dout(CNTR_POINTER_BITWIDTH+INDEX_BITWIDTH-1 downto INDEX_BITWIDTH);
k_out <= unsigned(tmp_cntr_stack_dout(INDEX_BITWIDTH-1 downto 0));
valid <= rdy_delay_line(MEM_LAT-1); -- AND NOT(emp_delay_line(MEM_LAT-1));
empty <= tmp_empty;--emp_delay_line(MEM_LAT-1);
end Behavioral;
|
bsd-3-clause
|
FelixWinterstein/Vivado-KMeans
|
filtering_algorithm_HLS/rtl/source/filtering_algorithm_wrapper.vhd
|
1
|
9161
|
----------------------------------------------------------------------------------
-- Felix Winterstein, Imperial College London
--
-- filtering_algorithm_wrapper - Behavioral
--
-- Revision 1.01
-- Additional Comments: distributed under a BSD license, see LICENSE.txt
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use ieee.math_real.all;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity filtering_algorithm_wrapper is
port (
ap_clk : in std_logic;
ap_rst : in std_logic;
ap_start : in std_logic;
ap_done : out std_logic;
ap_idle : out std_logic;
node_data_dout : in std_logic_vector (319 downto 0);
node_data_empty_n : in std_logic;
node_data_read : out std_logic;
node_address_V_dout : IN STD_LOGIC_VECTOR (15 downto 0);
node_address_V_empty_n : IN STD_LOGIC;
node_address_V_read : OUT STD_LOGIC;
cntr_pos_init_value_V_dout : in std_logic_vector (47 downto 0);
cntr_pos_init_value_V_empty_n : in std_logic;
cntr_pos_init_value_V_read : out std_logic;
n_V : in std_logic_vector (15 downto 0);
k_V : in std_logic_vector (7 downto 0);
root_V_dout : in std_logic_vector (15 downto 0);
root_V_empty_n : in std_logic;
root_V_read : out std_logic;
distortion_out_V_din : out std_logic_vector (31 downto 0);
distortion_out_V_full_n : in std_logic;
distortion_out_V_write : out std_logic;
clusters_out_value_V_din : out std_logic_vector (47 downto 0);
clusters_out_value_V_full_n : in std_logic;
clusters_out_value_V_write : out std_logic
);
end filtering_algorithm_wrapper;
architecture Behavioral of filtering_algorithm_wrapper is
component filtering_algorithm_top is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
node_data_dout : IN STD_LOGIC_VECTOR (319 downto 0);
node_data_empty_n : IN STD_LOGIC;
node_data_read : OUT STD_LOGIC;
node_address_V_dout : IN STD_LOGIC_VECTOR (15 downto 0);
node_address_V_empty_n : IN STD_LOGIC;
node_address_V_read : OUT STD_LOGIC;
cntr_pos_init_value_V_dout : IN STD_LOGIC_VECTOR (47 downto 0);
cntr_pos_init_value_V_empty_n : IN STD_LOGIC;
cntr_pos_init_value_V_read : OUT STD_LOGIC;
n_V : IN STD_LOGIC_VECTOR (15 downto 0);
k_V : IN STD_LOGIC_VECTOR (7 downto 0);
root_V_dout : IN STD_LOGIC_VECTOR (15 downto 0);
root_V_empty_n : IN STD_LOGIC;
root_V_read : OUT STD_LOGIC;
distortion_out_V_din : OUT STD_LOGIC_VECTOR (31 downto 0);
distortion_out_V_full_n : IN STD_LOGIC;
distortion_out_V_write : OUT STD_LOGIC;
clusters_out_value_V_din : OUT STD_LOGIC_VECTOR (47 downto 0);
clusters_out_value_V_full_n : IN STD_LOGIC;
clusters_out_value_V_write : OUT STD_LOGIC
);
end component;
signal tmp_clk : std_logic;
signal ap_rst_reg : std_logic;
signal ap_start_reg : std_logic;
signal ap_done_tmp : std_logic;
signal ap_done_reg : std_logic;
signal ap_idle_tmp : std_logic;
signal ap_idle_reg : std_logic;
signal node_data_dout_reg : std_logic_vector (319 downto 0);
signal node_data_empty_n_reg : std_logic;
signal node_data_read_tmp : std_logic;
signal node_data_read_reg : std_logic;
signal node_address_V_dout_reg : std_logic_vector (15 downto 0);
signal node_address_V_empty_n_reg : std_logic;
signal node_address_V_read_tmp : std_logic;
signal node_address_V_read_reg : std_logic;
signal cntr_pos_init_value_V_dout_reg : std_logic_vector (47 downto 0);
signal cntr_pos_init_value_V_empty_n_reg : std_logic;
signal cntr_pos_init_value_V_read_tmp : std_logic;
signal cntr_pos_init_value_V_read_reg : std_logic;
signal n_V_reg : std_logic_vector (15 downto 0);
signal k_V_reg : std_logic_vector (7 downto 0);
signal root_V_reg : std_logic_vector (15 downto 0);
signal root_V_dout_reg : std_logic_vector (15 downto 0);
signal root_V_empty_n_reg : std_logic;
signal root_V_read_tmp : std_logic;
signal root_V_read_reg : std_logic;
signal distortion_out_V_din_tmp : std_logic_vector (31 downto 0);
signal distortion_out_V_din_reg : std_logic_vector (31 downto 0);
signal distortion_out_V_full_n_reg : std_logic;
signal distortion_out_V_write_tmp : std_logic;
signal distortion_out_V_write_reg : std_logic;
signal clusters_out_value_V_din_tmp : std_logic_vector (47 downto 0);
signal clusters_out_value_V_din_reg : std_logic_vector (47 downto 0);
signal clusters_out_value_V_full_n_reg : std_logic;
signal clusters_out_value_V_write_tmp : std_logic;
signal clusters_out_value_V_write_reg : std_logic;
begin
ClkBuffer: IBUFG
port map (
I => ap_clk,
O => tmp_clk
);
input_reg : process(tmp_clk)
begin
if rising_edge(tmp_clk) then
ap_rst_reg <= ap_rst;
ap_start_reg <= ap_start;
node_data_dout_reg <= node_data_dout;
node_data_empty_n_reg <= node_data_empty_n;
node_address_V_dout_reg <= node_address_V_dout;
node_address_V_empty_n_reg <= node_address_V_empty_n;
cntr_pos_init_value_V_dout_reg <= cntr_pos_init_value_V_dout;
cntr_pos_init_value_V_empty_n_reg <= cntr_pos_init_value_V_empty_n;
n_V_reg <= n_V;
k_V_reg <= k_V;
root_V_dout_reg <= root_V_dout;
root_V_empty_n_reg <= root_V_empty_n;
distortion_out_V_full_n_reg <= distortion_out_V_full_n;
clusters_out_value_V_full_n_reg <= clusters_out_value_V_full_n;
end if;
end process input_reg;
filtering_alogrithm_top_inst : filtering_algorithm_top
port map(
ap_clk => tmp_clk,
ap_rst => ap_rst_reg,
ap_start => ap_start_reg,
ap_done => ap_done_tmp,
ap_idle => ap_idle_tmp,
node_data_dout => node_data_dout_reg,
node_data_empty_n => node_data_empty_n_reg,
node_data_read => node_data_read_tmp,
node_address_V_dout => node_address_V_dout_reg,
node_address_V_empty_n => node_address_V_empty_n_reg,
node_address_V_read => node_address_V_read_tmp,
cntr_pos_init_value_V_dout => cntr_pos_init_value_V_dout_reg,
cntr_pos_init_value_V_empty_n => cntr_pos_init_value_V_empty_n_reg,
cntr_pos_init_value_V_read => cntr_pos_init_value_V_read_tmp,
n_V => n_V_reg,
k_V => k_V_reg,
root_V_dout => root_V_dout_reg,
root_V_empty_n => root_V_empty_n_reg,
root_V_read => root_V_read_tmp,
distortion_out_V_din => distortion_out_V_din_tmp,
distortion_out_V_full_n => distortion_out_V_full_n_reg,
distortion_out_V_write => distortion_out_V_write_tmp,
clusters_out_value_V_din => clusters_out_value_V_din_tmp,
clusters_out_value_V_full_n => clusters_out_value_V_full_n_reg,
clusters_out_value_V_write => clusters_out_value_V_write_tmp
);
output_reg : process(tmp_clk)
begin
if rising_edge(tmp_clk) then
ap_done_reg <= ap_done_tmp;
ap_idle_reg <= ap_idle_tmp;
node_data_read_reg <= node_data_read_tmp;
node_address_V_read_reg <= node_address_V_read_tmp;
root_V_read_reg <= root_V_read_tmp;
cntr_pos_init_value_V_read_reg <= cntr_pos_init_value_V_read_tmp;
distortion_out_V_din_reg <= distortion_out_V_din_tmp;
distortion_out_V_write_reg <= distortion_out_V_write_tmp;
clusters_out_value_V_din_reg <= clusters_out_value_V_din_tmp;
clusters_out_value_V_write_reg <= clusters_out_value_V_write_tmp;
end if;
end process output_reg;
ap_done <= ap_done_reg;
ap_idle <= ap_idle_reg;
node_data_read <= node_data_read_reg;
node_address_V_read <= node_address_V_read_reg;
cntr_pos_init_value_V_read <= cntr_pos_init_value_V_read_reg;
root_V_read <= root_V_read_reg;
distortion_out_V_din <= distortion_out_V_din_reg;
distortion_out_V_write <= distortion_out_V_write_reg;
clusters_out_value_V_din <= clusters_out_value_V_din_reg;
clusters_out_value_V_write <= clusters_out_value_V_write_reg;
end Behavioral;
|
bsd-3-clause
|
FelixWinterstein/Vivado-KMeans
|
filtering_algorithm_RTL/source/vhdl/filtering_algorithm_wrapper.vhd
|
1
|
8339
|
----------------------------------------------------------------------------------
-- Felix Winterstein, Imperial College London
--
-- Module Name: filtering_algorithm_wrapper - Behavioral
--
-- Revision 1.01
-- Additional Comments: distributed under a BSD license, see LICENSE.txt
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use ieee.math_real.all;
use work.filtering_algorithm_pkg.all;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity filtering_algorithm_wrapper is
port (
clk : in std_logic;
sclr : in std_logic;
start : in std_logic;
select_input : in std_logic_vector(1 downto 0);
select_par : in std_logic_vector(integer(ceil(log2(real(PARALLEL_UNITS))))-1 downto 0);
-- initial parameters
k : in unsigned(INDEX_BITWIDTH-1 downto 0);
root_address : in std_logic_vector(NODE_POINTER_BITWIDTH-1 downto 0);
-- init node and centre memory
wr_init_nd : in std_logic;
wr_data_init : in std_logic_vector(3*D*COORD_BITWIDTH+D*COORD_BITWIDTH_EXT+COORD_BITWIDTH+COORD_BITWIDTH_EXT+2*NODE_POINTER_BITWIDTH-1 downto 0);
wr_address_init : in std_logic_vector(NODE_POINTER_BITWIDTH-1 downto 0);
-- outputs
valid : out std_logic;
clusters_out : out data_type;
distortion_out : out coord_type_ext;
-- processing done
rdy : out std_logic
);
end filtering_algorithm_wrapper;
architecture Behavioral of filtering_algorithm_wrapper is
component filtering_alogrithm_top is
port (
clk : in std_logic;
sclr : in std_logic;
start : in std_logic;
-- initial parameters
k : in centre_index_type;
root_address : in par_node_address_type;
-- init node and centre memory
wr_init_cent : in std_logic;
wr_centre_list_address_init : in centre_list_address_type;
wr_centre_list_data_init : in centre_index_type;
wr_init_node : in std_logic_vector(0 to PARALLEL_UNITS-1);
wr_node_address_init : in par_node_address_type;
wr_node_data_init : in par_node_data_type;
wr_init_pos : in std_logic;
wr_centre_list_pos_address_init : in centre_index_type;
wr_centre_list_pos_data_init : in data_type;
-- outputs
valid : out std_logic;
clusters_out : out data_type;
distortion_out : out coord_type_ext;
-- processing done
rdy : out std_logic
);
end component;
signal tmp_clk : std_logic;
signal reg_sclr : std_logic;
signal reg_start : std_logic;
-- initial parameters
signal reg_k : centre_index_type;
signal reg_root_address : node_address_type;
signal tmp_root_address : par_node_address_type;
-- init node and centre memory
signal reg_wr_init_cent : std_logic;
signal reg_wr_centre_list_address_init : centre_list_address_type;
signal reg_wr_centre_list_data_init : centre_index_type;
signal reg_wr_init_node : std_logic_vector(0 to PARALLEL_UNITS-1);
signal reg_wr_node_address_init : node_address_type;
signal tmp_wr_node_address_init : par_node_address_type;
signal reg_wr_node_data_init : node_data_type;
signal tmp_wr_node_data_init : par_node_data_type;
signal reg_wr_init_pos : std_logic;
signal reg_wr_centre_list_pos_address_init : centre_index_type;
signal reg_wr_centre_list_pos_data_init : data_type;
-- outputs
signal tmp_valid : std_logic;
signal reg_valid : std_logic;
signal tmp_clusters_out : data_type;
signal reg_clusters_out : data_type;
signal tmp_distortion_out : coord_type_ext;
signal reg_distortion_out : coord_type_ext;
-- processing done
signal tmp_rdy : std_logic;
signal reg_rdy : std_logic;
begin
ClkBuffer: IBUFG
port map (
I => clk,
O => tmp_clk
);
input_reg : process(tmp_clk)
begin
if rising_edge(tmp_clk) then
if select_input = "00" then
reg_wr_init_cent <= wr_init_nd;
reg_wr_init_pos <= '0';
elsif select_input = "01" then
reg_wr_init_cent <= '0';
reg_wr_init_pos <= '0';
else
reg_wr_init_cent <= '0';
reg_wr_init_pos <= wr_init_nd;
end if;
for I in 0 to PARALLEL_UNITS-1 loop
if select_par = std_logic_vector(to_unsigned(I,integer(ceil(log2(real(PARALLEL_UNITS)))))) then
if select_input = "00" then
reg_wr_init_node(I) <= '0';
elsif select_input = "01" then
reg_wr_init_node(I) <= wr_init_nd;
else
reg_wr_init_node(I) <= '0';
end if;
else
reg_wr_init_node(I) <= '0';
end if;
end loop;
reg_wr_centre_list_address_init <= wr_address_init(CNTR_POINTER_BITWIDTH-1 downto 0);
reg_wr_centre_list_data_init <= unsigned(wr_data_init(INDEX_BITWIDTH-1 downto 0));
reg_wr_node_address_init <= wr_address_init(NODE_POINTER_BITWIDTH-1 downto 0);
reg_wr_node_data_init <= stdlogic_2_nodedata(wr_data_init);
reg_wr_centre_list_pos_address_init <= unsigned(wr_address_init(INDEX_BITWIDTH-1 downto 0));
reg_wr_centre_list_pos_data_init <= stdlogic_2_datapoint(wr_data_init(D*COORD_BITWIDTH-1 downto 0));
reg_sclr <= sclr;
reg_start <= start;
reg_k <= k;
reg_root_address <= root_address;
end if;
end process input_reg;
-- parallel units will be initialiased one after the other (a controlled by reg_wr_init_node)
G0_PAR : for I in 0 to PARALLEL_UNITS-1 generate
tmp_wr_node_address_init(I) <= reg_wr_node_address_init;
tmp_wr_node_data_init(I) <= reg_wr_node_data_init;
tmp_root_address(I) <= reg_root_address;
end generate G0_PAR;
filtering_alogrithm_top_inst : filtering_alogrithm_top
port map(
clk => tmp_clk,
sclr => reg_sclr,
start => reg_start,
-- initial parameters
k => reg_k,
root_address => tmp_root_address,
-- init node and centre memory
wr_init_cent => reg_wr_init_cent,
wr_centre_list_address_init => reg_wr_centre_list_address_init,
wr_centre_list_data_init => reg_wr_centre_list_data_init,
wr_init_node => reg_wr_init_node,
wr_node_address_init => tmp_wr_node_address_init,
wr_node_data_init => tmp_wr_node_data_init,
wr_init_pos => reg_wr_init_pos,
wr_centre_list_pos_address_init => reg_wr_centre_list_pos_address_init,
wr_centre_list_pos_data_init => reg_wr_centre_list_pos_data_init,
-- outputs
valid => tmp_valid,
clusters_out => tmp_clusters_out,
distortion_out => tmp_distortion_out,
-- processing done
rdy => tmp_rdy
);
output_reg : process(tmp_clk)
begin
if rising_edge(tmp_clk) then
reg_valid <= tmp_valid;
reg_clusters_out <= tmp_clusters_out;
reg_distortion_out <= tmp_distortion_out;
reg_rdy <= tmp_rdy;
end if;
end process output_reg;
valid <= reg_valid;
clusters_out <= reg_clusters_out;
distortion_out <= reg_distortion_out;
rdy <= reg_rdy;
end Behavioral;
|
bsd-3-clause
|
antmicro/parallella-lcd-fpga
|
system/system_top.vhd
|
3
|
7527
|
-------------------------------------------------------------------------------
-- system_top.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_top is
port (
processing_system7_0_MIO : inout std_logic_vector(53 downto 0);
processing_system7_0_PS_SRSTB_pin : in std_logic;
processing_system7_0_PS_CLK_pin : in std_logic;
processing_system7_0_PS_PORB_pin : in std_logic;
processing_system7_0_DDR_Clk : inout std_logic;
processing_system7_0_DDR_Clk_n : inout std_logic;
processing_system7_0_DDR_CKE : inout std_logic;
processing_system7_0_DDR_CS_n : inout std_logic;
processing_system7_0_DDR_RAS_n : inout std_logic;
processing_system7_0_DDR_CAS_n : inout std_logic;
processing_system7_0_DDR_WEB_pin : out std_logic;
processing_system7_0_DDR_BankAddr : inout std_logic_vector(2 downto 0);
processing_system7_0_DDR_Addr : inout std_logic_vector(14 downto 0);
processing_system7_0_DDR_ODT : inout std_logic;
processing_system7_0_DDR_DRSTB : inout std_logic;
processing_system7_0_DDR_DQ : inout std_logic_vector(31 downto 0);
processing_system7_0_DDR_DM : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_DQS : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_DQS_n : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_VRN : inout std_logic;
processing_system7_0_DDR_VRP : inout std_logic;
I2C_SCL : inout std_logic;
I2C_SDA : inout std_logic;
I2C_INT_N : in std_logic;
HSYNC : out std_logic;
VSYNC : out std_logic;
PXL_CLK : out std_logic;
DE : out std_logic;
RED : out std_logic_vector(5 downto 0);
GREEN : out std_logic_vector(5 downto 0);
BLUE : out std_logic_vector(5 downto 0);
brigthness_pin : out std_logic;
tft_ena : out std_logic;
tft_wake_n : out std_logic
);
end system_top;
architecture STRUCTURE of system_top is
component system is
port (
processing_system7_0_MIO : inout std_logic_vector(53 downto 0);
processing_system7_0_PS_SRSTB_pin : in std_logic;
processing_system7_0_PS_CLK_pin : in std_logic;
processing_system7_0_PS_PORB_pin : in std_logic;
processing_system7_0_DDR_Clk : inout std_logic;
processing_system7_0_DDR_Clk_n : inout std_logic;
processing_system7_0_DDR_CKE : inout std_logic;
processing_system7_0_DDR_CS_n : inout std_logic;
processing_system7_0_DDR_RAS_n : inout std_logic;
processing_system7_0_DDR_CAS_n : inout std_logic;
processing_system7_0_DDR_WEB_pin : out std_logic;
processing_system7_0_DDR_BankAddr : inout std_logic_vector(2 downto 0);
processing_system7_0_DDR_Addr : inout std_logic_vector(14 downto 0);
processing_system7_0_DDR_ODT : inout std_logic;
processing_system7_0_DDR_DRSTB : inout std_logic;
processing_system7_0_DDR_DQ : inout std_logic_vector(31 downto 0);
processing_system7_0_DDR_DM : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_DQS : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_DQS_n : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_VRN : inout std_logic;
processing_system7_0_DDR_VRP : inout std_logic;
processing_system7_0_I2C0_SCL_pin :inout std_logic;
processing_system7_0_I2C0_SDA_pin :inout std_logic;
processing_system7_0_I2C0_INT_N_pin : in std_logic;
processing_system7_0_FCLK_CLK0_pin : out std_logic;
axi_dispctrl_0_HSYNC_O_pin : out std_logic;
axi_dispctrl_0_VSYNC_O_pin : out std_logic;
axi_dispctrl_0_PXL_CLK_O_pin : out std_logic;
axi_dispctrl_0_DE_O_pin : out std_logic;
axi_dispctrl_0_RED_O_pin : out std_logic_vector(7 downto 0);
axi_dispctrl_0_GREEN_O_pin : out std_logic_vector(7 downto 0);
axi_dispctrl_0_BLUE_O_pin : out std_logic_vector(7 downto 0);
axi_dispctrl_0_ENABLE_O_pin : out std_logic
);
end component;
attribute BOX_TYPE : STRING;
attribute BOX_TYPE of system : component is "user_black_box";
signal axi_dispctrl_0_HSYNC_O_pin : std_logic;
signal axi_dispctrl_0_VSYNC_O_pin : std_logic;
signal axi_dispctrl_0_PXL_CLK_O_pin : std_logic;
signal axi_dispctrl_0_DE_O_pin : std_logic;
signal axi_dispctrl_0_RED_O_pin : std_logic_vector(7 downto 0);
signal axi_dispctrl_0_GREEN_O_pin : std_logic_vector(7 downto 0);
signal axi_dispctrl_0_BLUE_O_pin : std_logic_vector(7 downto 0);
signal axi_dispctrl_0_ENABLE_O_pin : std_logic;
signal clk_100MHz : std_logic;
begin
brigthness_pin <= '1';
tft_ena <= axi_dispctrl_0_ENABLE_O_pin;
HSYNC <= axi_dispctrl_0_HSYNC_O_pin;
VSYNC <= axi_dispctrl_0_VSYNC_O_pin;
PXL_CLK <= axi_dispctrl_0_PXL_CLK_O_pin;
DE <= axi_dispctrl_0_DE_O_pin;
RED <= axi_dispctrl_0_RED_O_pin (7 downto 2);
GREEN <= axi_dispctrl_0_GREEN_O_pin (7 downto 2);
BLUE <= axi_dispctrl_0_BLUE_O_pin (7 downto 2);
lcd_reset: process (clk_100MHz)
variable rst_count: integer range 0 to 1_000_000 := 0;
begin
if( rising_edge(clk_100MHz) ) then
if( rst_count = 1_000_000 ) then
tft_wake_n <= '1';
else
tft_wake_n <= '0';
rst_count := rst_count + 1;
end if;
end if;
end process;
system_i : system
port map (
processing_system7_0_MIO => processing_system7_0_MIO,
processing_system7_0_PS_SRSTB_pin => processing_system7_0_PS_SRSTB_pin,
processing_system7_0_PS_CLK_pin => processing_system7_0_PS_CLK_pin,
processing_system7_0_PS_PORB_pin => processing_system7_0_PS_PORB_pin,
processing_system7_0_DDR_Clk => processing_system7_0_DDR_Clk,
processing_system7_0_DDR_Clk_n => processing_system7_0_DDR_Clk_n,
processing_system7_0_DDR_CKE => processing_system7_0_DDR_CKE,
processing_system7_0_DDR_CS_n => processing_system7_0_DDR_CS_n,
processing_system7_0_DDR_RAS_n => processing_system7_0_DDR_RAS_n,
processing_system7_0_DDR_CAS_n => processing_system7_0_DDR_CAS_n,
processing_system7_0_DDR_WEB_pin => processing_system7_0_DDR_WEB_pin,
processing_system7_0_DDR_BankAddr => processing_system7_0_DDR_BankAddr,
processing_system7_0_DDR_Addr => processing_system7_0_DDR_Addr,
processing_system7_0_DDR_ODT => processing_system7_0_DDR_ODT,
processing_system7_0_DDR_DRSTB => processing_system7_0_DDR_DRSTB,
processing_system7_0_DDR_DQ => processing_system7_0_DDR_DQ,
processing_system7_0_DDR_DM => processing_system7_0_DDR_DM,
processing_system7_0_DDR_DQS => processing_system7_0_DDR_DQS,
processing_system7_0_DDR_DQS_n => processing_system7_0_DDR_DQS_n,
processing_system7_0_DDR_VRN => processing_system7_0_DDR_VRN,
processing_system7_0_DDR_VRP => processing_system7_0_DDR_VRP,
processing_system7_0_I2C0_SCL_pin => I2C_SCL,
processing_system7_0_I2C0_SDA_pin => I2C_SDA,
processing_system7_0_I2C0_INT_N_pin => I2C_INT_N,
processing_system7_0_FCLK_CLK0_pin => clk_100MHz,
axi_dispctrl_0_HSYNC_O_pin => axi_dispctrl_0_HSYNC_O_pin,
axi_dispctrl_0_VSYNC_O_pin => axi_dispctrl_0_VSYNC_O_pin,
axi_dispctrl_0_PXL_CLK_O_pin => axi_dispctrl_0_PXL_CLK_O_pin,
axi_dispctrl_0_DE_O_pin => axi_dispctrl_0_DE_O_pin,
axi_dispctrl_0_RED_O_pin => axi_dispctrl_0_RED_O_pin,
axi_dispctrl_0_GREEN_O_pin => axi_dispctrl_0_GREEN_O_pin,
axi_dispctrl_0_BLUE_O_pin => axi_dispctrl_0_BLUE_O_pin,
axi_dispctrl_0_ENABLE_O_pin => axi_dispctrl_0_ENABLE_O_pin
);
end architecture STRUCTURE;
|
bsd-3-clause
|
parallella/parallella-lcd-fpga
|
system/implementation/system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1/simulation/system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_synth.vhd
|
3
|
10215
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY work;
USE work.system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_synth IS
-- FIFO interface signal declarations
SIGNAL clk_i : STD_LOGIC;
SIGNAL rst : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(5-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(5-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(5-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(5-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_rd3 OR rst_s_rd;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(clk_i'event AND clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(clk_i)
BEGIN
IF(clk_i'event AND clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
clk_i <= CLK;
------------------
rst <= RESET OR rst_s_rd AFTER 12 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
fg_dg_nv: system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_dgen
GENERIC MAP (
C_DIN_WIDTH => 5,
C_DOUT_WIDTH => 5,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_dverif
GENERIC MAP (
C_DOUT_WIDTH => 5,
C_DIN_WIDTH => 5,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 5,
C_DIN_WIDTH => 5,
C_WR_PNTR_WIDTH => 5,
C_RD_PNTR_WIDTH => 5,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => clk_i,
RD_CLK => clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_inst : system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_exdes
PORT MAP (
CLK => clk_i,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
|
bsd-3-clause
|
parallella/parallella-lcd-fpga
|
system/implementation/system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1/simulation/system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_pkg.vhd
|
3
|
11785
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for FIFO Generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_exdes IS
PORT (
CLK : IN std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(5-1 DOWNTO 0);
DOUT : OUT std_logic_vector(5-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_pkg;
PACKAGE BODY system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_pkg;
|
bsd-3-clause
|
parallella/parallella-lcd-fpga
|
system/implementation/system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2/simulation/system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_dgen.vhd
|
3
|
4760
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_dgen.vhd
--
-- Description:
-- Used for write interface stimulus generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_pkg.ALL;
ENTITY system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_dg_arch OF system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_dgen IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
SIGNAL pr_w_en : STD_LOGIC := '0';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
BEGIN
WR_EN <= PRC_WR_EN ;
WR_DATA <= wr_data_i AFTER 50 ns;
----------------------------------------------
-- Generation of DATA
----------------------------------------------
gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst1:system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_w_en
);
END GENERATE;
pr_w_en <= PRC_WR_EN AND NOT FULL;
wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0);
END ARCHITECTURE;
|
bsd-3-clause
|
parallella/parallella-lcd-fpga
|
system/implementation/system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2/simulation/system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_tb.vhd
|
3
|
6128
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_tb.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_pkg.ALL;
ENTITY system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_tb IS
END ENTITY;
ARCHITECTURE system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_arch OF system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_tb IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 100 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 110 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 2000 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Simulation Complete"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 100 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_synth
system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_synth_inst:system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 36
)
PORT MAP(
CLK => wr_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
|
bsd-3-clause
|
inforichland/freezing-spice
|
src/std_logic_textio.vhd
|
1
|
18575
|
-- std_logic_textio.vhdl
----------------------------------------------------------------------------
--
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. All rights reserved.
--
-- This source file may be used and distributed without restriction
-- provided that this copyright statement is not removed from the file
-- and that any derivative work contains this copyright notice.
--
-- Package name: STD_LOGIC_TEXTIO
--
-- Purpose: This package overloads the standard TEXTIO procedures
-- READ and WRITE.
--
-- Author: CRC, TS
--
----------------------------------------------------------------------------
use STD.textio.all;
library IEEE;
use IEEE.std_logic_1164.all;
package STD_LOGIC_TEXTIO is
--synopsys synthesis_off
-- Read and Write procedures for STD_ULOGIC and STD_ULOGIC_VECTOR
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC);
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC; GOOD: out BOOLEAN);
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR);
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR; GOOD: out BOOLEAN);
procedure WRITE(L:inout LINE; VALUE:in STD_ULOGIC;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
procedure WRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
-- Read and Write procedures for STD_LOGIC_VECTOR
procedure READ(L:inout LINE; VALUE:out STD_LOGIC_VECTOR);
procedure READ(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN);
procedure WRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
--
-- Read and Write procedures for Hex and Octal values.
-- The values appear in the file as a series of characters
-- between 0-F (Hex), or 0-7 (Octal) respectively.
--
-- Hex
procedure HREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR);
procedure HREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR; GOOD: out BOOLEAN);
procedure HWRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
procedure HREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR);
procedure HREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN);
procedure HWRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
-- Octal
procedure OREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR);
procedure OREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR; GOOD: out BOOLEAN);
procedure OWRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
procedure OREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR);
procedure OREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN);
procedure OWRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
--synopsys synthesis_on
end STD_LOGIC_TEXTIO;
package body STD_LOGIC_TEXTIO is
--synopsys synthesis_off
-- Type and constant definitions used to map STD_ULOGIC values
-- into/from character values.
type MVL9plus is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-', ERROR);
type char_indexed_by_MVL9 is array (STD_ULOGIC) of character;
type MVL9_indexed_by_char is array (character) of STD_ULOGIC;
type MVL9plus_indexed_by_char is array (character) of MVL9plus;
constant MVL9_to_char: char_indexed_by_MVL9 := "UX01ZWLH-";
constant char_to_MVL9: MVL9_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => 'U');
constant char_to_MVL9plus: MVL9plus_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => ERROR);
-- Overloaded procedures.
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC; GOOD:out BOOLEAN) is
variable c: character;
begin
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
if (char_to_MVL9plus(c) = ERROR) then
value := 'U';
good := FALSE;
else
value := char_to_MVL9(c);
good := TRUE;
end if;
end READ;
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR; GOOD:out BOOLEAN) is
variable m: STD_ULOGIC;
variable c: character;
variable s: string(1 to value'length-1);
variable mv: STD_ULOGIC_VECTOR(0 to value'length-1);
constant allU: STD_ULOGIC_VECTOR(0 to value'length-1)
:= (others => 'U');
begin
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
if (char_to_MVL9plus(c) = ERROR) then
value := allU;
good := FALSE;
return;
end if;
read(l, s);
for i in 1 to value'length-1 loop
if (char_to_MVL9plus(s(i)) = ERROR) then
value := allU;
good := FALSE;
return;
end if;
end loop;
mv(0) := char_to_MVL9(c);
for i in 1 to value'length-1 loop
mv(i) := char_to_MVL9(s(i));
end loop;
value := mv;
good := TRUE;
end READ;
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC) is
variable c: character;
begin
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
if (char_to_MVL9plus(c) = ERROR) then
value := 'U';
assert FALSE report "READ(STD_ULOGIC) Error: Character '" &
c & "' read, expected STD_ULOGIC literal.";
else
value := char_to_MVL9(c);
end if;
end READ;
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR) is
variable m: STD_ULOGIC;
variable c: character;
variable s: string(1 to value'length-1);
variable mv: STD_ULOGIC_VECTOR(0 to value'length-1);
constant allU: STD_ULOGIC_VECTOR(0 to value'length-1)
:= (others => 'U');
begin
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
if (char_to_MVL9plus(c) = ERROR) then
value := allU;
assert FALSE report
"READ(STD_ULOGIC_VECTOR) Error: Character '" &
c & "' read, expected STD_ULOGIC literal.";
return;
end if;
read(l, s);
for i in 1 to value'length-1 loop
if (char_to_MVL9plus(s(i)) = ERROR) then
value := allU;
assert FALSE report
"READ(STD_ULOGIC_VECTOR) Error: Character '" &
s(i) & "' read, expected STD_ULOGIC literal.";
return;
end if;
end loop;
mv(0) := char_to_MVL9(c);
for i in 1 to value'length-1 loop
mv(i) := char_to_MVL9(s(i));
end loop;
value := mv;
end READ;
procedure WRITE(L:inout LINE; VALUE:in STD_ULOGIC;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
write(l, MVL9_to_char(value), justified, field);
end WRITE;
procedure WRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
variable s: string(1 to value'length);
variable m: STD_ULOGIC_VECTOR(1 to value'length) := value;
begin
for i in 1 to value'length loop
s(i) := MVL9_to_char(m(i));
end loop;
write(l, s, justified, field);
end WRITE;
-- Read and Write procedures for STD_LOGIC_VECTOR
procedure READ(L:inout LINE; VALUE:out STD_LOGIC_VECTOR) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
READ(L, tmp);
VALUE := STD_LOGIC_VECTOR(tmp);
end READ;
procedure READ(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
READ(L, tmp, GOOD);
VALUE := STD_LOGIC_VECTOR(tmp);
end READ;
procedure WRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
WRITE(L, STD_ULOGIC_VECTOR(VALUE), JUSTIFIED, FIELD);
end WRITE;
--
-- Hex Read and Write procedures.
--
--
-- Hex, and Octal Read and Write procedures for BIT_VECTOR
-- (these procedures are not exported, they are only used
-- by the STD_ULOGIC hex/octal reads and writes below.
--
--
procedure Char2QuadBits(C: Character;
RESULT: out Bit_Vector(3 downto 0);
GOOD: out Boolean;
ISSUE_ERROR: in Boolean) is
begin
case c is
when '0' => result := x"0"; good := TRUE;
when '1' => result := x"1"; good := TRUE;
when '2' => result := x"2"; good := TRUE;
when '3' => result := x"3"; good := TRUE;
when '4' => result := x"4"; good := TRUE;
when '5' => result := x"5"; good := TRUE;
when '6' => result := x"6"; good := TRUE;
when '7' => result := x"7"; good := TRUE;
when '8' => result := x"8"; good := TRUE;
when '9' => result := x"9"; good := TRUE;
when 'A' => result := x"A"; good := TRUE;
when 'B' => result := x"B"; good := TRUE;
when 'C' => result := x"C"; good := TRUE;
when 'D' => result := x"D"; good := TRUE;
when 'E' => result := x"E"; good := TRUE;
when 'F' => result := x"F"; good := TRUE;
when 'a' => result := x"A"; good := TRUE;
when 'b' => result := x"B"; good := TRUE;
when 'c' => result := x"C"; good := TRUE;
when 'd' => result := x"D"; good := TRUE;
when 'e' => result := x"E"; good := TRUE;
when 'f' => result := x"F"; good := TRUE;
when others =>
if ISSUE_ERROR then
assert FALSE report
"HREAD Error: Read a '" & c &
"', expected a Hex character (0-F).";
end if;
good := FALSE;
end case;
end;
procedure HREAD(L:inout LINE; VALUE:out BIT_VECTOR) is
variable ok: boolean;
variable c: character;
constant ne: integer := value'length/4;
variable bv: bit_vector(0 to value'length-1);
variable s: string(1 to ne-1);
begin
if value'length mod 4 /= 0 then
assert FALSE report
"HREAD Error: Trying to read vector " &
"with an odd (non multiple of 4) length";
return;
end if;
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
Char2QuadBits(c, bv(0 to 3), ok, TRUE);
if not ok then
return;
end if;
read(L, s, ok);
if not ok then
assert FALSE
report "HREAD Error: Failed to read the STRING";
return;
end if;
for i in 1 to ne-1 loop
Char2QuadBits(s(i), bv(4*i to 4*i+3), ok, TRUE);
if not ok then
return;
end if;
end loop;
value := bv;
end HREAD;
procedure HREAD(L:inout LINE; VALUE:out BIT_VECTOR;GOOD: out BOOLEAN) is
variable ok: boolean;
variable c: character;
constant ne: integer := value'length/4;
variable bv: bit_vector(0 to value'length-1);
variable s: string(1 to ne-1);
begin
if value'length mod 4 /= 0 then
good := FALSE;
return;
end if;
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
Char2QuadBits(c, bv(0 to 3), ok, FALSE);
if not ok then
good := FALSE;
return;
end if;
read(L, s, ok);
if not ok then
good := FALSE;
return;
end if;
for i in 1 to ne-1 loop
Char2QuadBits(s(i), bv(4*i to 4*i+3), ok, FALSE);
if not ok then
good := FALSE;
return;
end if;
end loop;
good := TRUE;
value := bv;
end HREAD;
procedure HWRITE(L:inout LINE; VALUE:in BIT_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
variable quad: bit_vector(0 to 3);
constant ne: integer := value'length/4;
variable bv: bit_vector(0 to value'length-1) := value;
variable s: string(1 to ne);
begin
if value'length mod 4 /= 0 then
assert FALSE report
"HWRITE Error: Trying to read vector " &
"with an odd (non multiple of 4) length";
return;
end if;
for i in 0 to ne-1 loop
quad := bv(4*i to 4*i+3);
case quad is
when x"0" => s(i+1) := '0';
when x"1" => s(i+1) := '1';
when x"2" => s(i+1) := '2';
when x"3" => s(i+1) := '3';
when x"4" => s(i+1) := '4';
when x"5" => s(i+1) := '5';
when x"6" => s(i+1) := '6';
when x"7" => s(i+1) := '7';
when x"8" => s(i+1) := '8';
when x"9" => s(i+1) := '9';
when x"A" => s(i+1) := 'A';
when x"B" => s(i+1) := 'B';
when x"C" => s(i+1) := 'C';
when x"D" => s(i+1) := 'D';
when x"E" => s(i+1) := 'E';
when x"F" => s(i+1) := 'F';
end case;
end loop;
write(L, s, JUSTIFIED, FIELD);
end HWRITE;
procedure Char2TriBits(C: Character;
RESULT: out bit_vector(2 downto 0);
GOOD: out Boolean;
ISSUE_ERROR: in Boolean) is
begin
case c is
when '0' => result := o"0"; good := TRUE;
when '1' => result := o"1"; good := TRUE;
when '2' => result := o"2"; good := TRUE;
when '3' => result := o"3"; good := TRUE;
when '4' => result := o"4"; good := TRUE;
when '5' => result := o"5"; good := TRUE;
when '6' => result := o"6"; good := TRUE;
when '7' => result := o"7"; good := TRUE;
when others =>
if ISSUE_ERROR then
assert FALSE report
"OREAD Error: Read a '" & c &
"', expected an Octal character (0-7).";
end if;
good := FALSE;
end case;
end;
procedure OREAD(L:inout LINE; VALUE:out BIT_VECTOR) is
variable c: character;
variable ok: boolean;
constant ne: integer := value'length/3;
variable bv: bit_vector(0 to value'length-1);
variable s: string(1 to ne-1);
begin
if value'length mod 3 /= 0 then
assert FALSE report
"OREAD Error: Trying to read vector " &
"with an odd (non multiple of 3) length";
return;
end if;
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
Char2TriBits(c, bv(0 to 2), ok, TRUE);
if not ok then
return;
end if;
read(L, s, ok);
if not ok then
assert FALSE
report "OREAD Error: Failed to read the STRING";
return;
end if;
for i in 1 to ne-1 loop
Char2TriBits(s(i), bv(3*i to 3*i+2), ok, TRUE);
if not ok then
return;
end if;
end loop;
value := bv;
end OREAD;
procedure OREAD(L:inout LINE; VALUE:out BIT_VECTOR;GOOD: out BOOLEAN) is
variable ok: boolean;
variable c: character;
constant ne: integer := value'length/3;
variable bv: bit_vector(0 to value'length-1);
variable s: string(1 to ne-1);
begin
if value'length mod 3 /= 0 then
good := FALSE;
return;
end if;
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
Char2TriBits(c, bv(0 to 2), ok, FALSE);
if not ok then
good := FALSE;
return;
end if;
read(L, s, ok);
if not ok then
good := FALSE;
return;
end if;
for i in 1 to ne-1 loop
Char2TriBits(s(i), bv(3*i to 3*i+2), ok, FALSE);
if not ok then
good := FALSE;
return;
end if;
end loop;
good := TRUE;
value := bv;
end OREAD;
procedure OWRITE(L:inout LINE; VALUE:in BIT_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
variable tri: bit_vector(0 to 2);
constant ne: integer := value'length/3;
variable bv: bit_vector(0 to value'length-1) := value;
variable s: string(1 to ne);
begin
if value'length mod 3 /= 0 then
assert FALSE report
"OWRITE Error: Trying to read vector " &
"with an odd (non multiple of 3) length";
return;
end if;
for i in 0 to ne-1 loop
tri := bv(3*i to 3*i+2);
case tri is
when o"0" => s(i+1) := '0';
when o"1" => s(i+1) := '1';
when o"2" => s(i+1) := '2';
when o"3" => s(i+1) := '3';
when o"4" => s(i+1) := '4';
when o"5" => s(i+1) := '5';
when o"6" => s(i+1) := '6';
when o"7" => s(i+1) := '7';
end case;
end loop;
write(L, s, JUSTIFIED, FIELD);
end OWRITE;
-- Hex Read and Write procedures for STD_LOGIC_VECTOR
procedure HREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR;GOOD:out BOOLEAN) is
variable tmp: bit_vector(VALUE'length-1 downto 0);
begin
HREAD(L, tmp, GOOD);
VALUE := To_X01(tmp);
end HREAD;
procedure HREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR) is
variable tmp: bit_vector(VALUE'length-1 downto 0);
begin
HREAD(L, tmp);
VALUE := To_X01(tmp);
end HREAD;
procedure HWRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
HWRITE(L, To_bitvector(VALUE),JUSTIFIED, FIELD);
end HWRITE;
-- Hex Read and Write procedures for STD_LOGIC_VECTOR
procedure HREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
HREAD(L, tmp);
VALUE := STD_LOGIC_VECTOR(tmp);
end HREAD;
procedure HREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
HREAD(L, tmp, GOOD);
VALUE := STD_LOGIC_VECTOR(tmp);
end HREAD;
procedure HWRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
HWRITE(L, To_bitvector(VALUE), JUSTIFIED, FIELD);
end HWRITE;
-- Octal Read and Write procedures for STD_ULOGIC_VECTOR
procedure OREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR;GOOD:out BOOLEAN) is
variable tmp: bit_vector(VALUE'length-1 downto 0);
begin
OREAD(L, tmp, GOOD);
VALUE := To_X01(tmp);
end OREAD;
procedure OREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR) is
variable tmp: bit_vector(VALUE'length-1 downto 0);
begin
OREAD(L, tmp);
VALUE := To_X01(tmp);
end OREAD;
procedure OWRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
OWRITE(L, To_bitvector(VALUE),JUSTIFIED, FIELD);
end OWRITE;
-- Octal Read and Write procedures for STD_LOGIC_VECTOR
procedure OREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
OREAD(L, tmp);
VALUE := STD_LOGIC_VECTOR(tmp);
end OREAD;
procedure OREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
OREAD(L, tmp, GOOD);
VALUE := STD_LOGIC_VECTOR(tmp);
end OREAD;
procedure OWRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
OWRITE(L, STD_ULOGIC_VECTOR(VALUE), JUSTIFIED, FIELD);
end OWRITE;
--synopsys synthesis_on
end STD_LOGIC_TEXTIO;
|
bsd-3-clause
|
multiarc/ace
|
demo/kitchen-sink/docs/vhdl.vhd
|
472
|
830
|
library IEEE
user IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity COUNT16 is
port (
cOut :out std_logic_vector(15 downto 0); -- counter output
clkEn :in std_logic; -- count enable
clk :in std_logic; -- clock input
rst :in std_logic -- reset input
);
end entity;
architecture count_rtl of COUNT16 is
signal count :std_logic_vector (15 downto 0);
begin
process (clk, rst) begin
if(rst = '1') then
count <= (others=>'0');
elsif(rising_edge(clk)) then
if(clkEn = '1') then
count <= count + 1;
end if;
end if;
end process;
cOut <= count;
end architecture;
|
bsd-3-clause
|
QLJIANG/ace-builds
|
demo/kitchen-sink/docs/vhdl.vhd
|
472
|
830
|
library IEEE
user IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity COUNT16 is
port (
cOut :out std_logic_vector(15 downto 0); -- counter output
clkEn :in std_logic; -- count enable
clk :in std_logic; -- clock input
rst :in std_logic -- reset input
);
end entity;
architecture count_rtl of COUNT16 is
signal count :std_logic_vector (15 downto 0);
begin
process (clk, rst) begin
if(rst = '1') then
count <= (others=>'0');
elsif(rising_edge(clk)) then
if(clkEn = '1') then
count <= count + 1;
end if;
end if;
end process;
cOut <= count;
end architecture;
|
bsd-3-clause
|
kennethlyn/parallella-lcd-fpga
|
system/implementation/system_axi_vdma_0_wrapper_fifo_generator_v9_3/example_design/system_axi_vdma_0_wrapper_fifo_generator_v9_3_exdes.vhd
|
3
|
5689
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core - core top file for implementation
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_vdma_0_wrapper_fifo_generator_v9_3_exdes.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity system_axi_vdma_0_wrapper_fifo_generator_v9_3_exdes is
PORT (
CLK : IN std_logic;
DATA_COUNT : OUT std_logic_vector(7-1 DOWNTO 0);
WR_ACK : OUT std_logic;
VALID : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(67-1 DOWNTO 0);
DOUT : OUT std_logic_vector(67-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end system_axi_vdma_0_wrapper_fifo_generator_v9_3_exdes;
architecture xilinx of system_axi_vdma_0_wrapper_fifo_generator_v9_3_exdes is
signal clk_i : std_logic;
component system_axi_vdma_0_wrapper_fifo_generator_v9_3 is
PORT (
CLK : IN std_logic;
DATA_COUNT : OUT std_logic_vector(7-1 DOWNTO 0);
WR_ACK : OUT std_logic;
VALID : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(67-1 DOWNTO 0);
DOUT : OUT std_logic_vector(67-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_buf: bufg
PORT map(
i => CLK,
o => clk_i
);
exdes_inst : system_axi_vdma_0_wrapper_fifo_generator_v9_3
PORT MAP (
CLK => clk_i,
DATA_COUNT => data_count,
WR_ACK => wr_ack,
VALID => valid,
ALMOST_EMPTY => almost_empty,
SRST => srst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
|
bsd-3-clause
|
alemedeiros/flappy_vhdl
|
output/frame_builder.vhd
|
1
|
1895
|
-- file: output/draw_frame.vhd
-- authors: Alexandre Medeiros and Gabriel Lopes
--
-- A Flappy bird implementation in VHDL for a Digital Circuits course at
-- Unicamp.
--
-- Generate a frame from the current game state.
library ieee ;
use ieee.std_logic_1164.all ;
entity frame_builder is
generic (
H_RES : natural := 128 ; -- Horizontal Resolution
V_RES : natural := 96 ; -- Vertical Resolution
N_OBST : natural := 4 ; -- Number of obstacles
P_POS : natural := 20 -- Player Horizontal position
) ;
port (
-- Game state data.
player : in integer range 0 to V_RES - 1 ;
obst_low : in integer range 0 to V_RES - 1 ;
obst_high : in integer range 0 to V_RES - 1 ;
obst_pos : in integer range 0 to H_RES / N_OBST - 1;
obst_id : out integer range 0 to N_OBST - 1 ;
lin : in integer range 0 to V_RES - 1 ;
col : in integer range 0 to H_RES - 1 ;
enable : in std_logic ;
colour : out std_logic_vector(2 downto 0)
) ;
end frame_builder ;
architecture behavior of frame_builder is
signal c : std_logic_vector(2 downto 0) ;
signal id : integer range 0 to N_OBST - 1 ;
begin
-- Process that determines the colour of each pixel.
process(lin, col)
variable curr_id : integer range 0 to N_OBST - 1 ;
begin
-- Background colour is black
c <= "000" ;
-- Determine current obstacle.
curr_id := col / (H_RES / N_OBST) ;
id <= curr_id ;
if lin = player and col = P_POS then -- Player colour
c <= "110" ;
elsif col = curr_id * (H_RES / N_OBST) + obst_pos then -- Obstacles colour
if lin < obst_high then -- Top obstacle
c <= "010" ;
elsif lin > (V_RES - 1) - obst_low then -- Bottom obstacle
c <= "010" ;
end if ;
end if ;
end process ;
colour <= c when enable = '1' else "ZZZ" ;
obst_id <= id when enable = '1' else 0 ;
end behavior ;
|
bsd-3-clause
|
alemedeiros/flappy_vhdl
|
modules/player_pack.vhd
|
1
|
1143
|
-- file: modules/player_pack.vhd
-- authors: Alexandre Medeiros and Gabriel Lopes
--
-- A Flappy bird implementation in VHDL for a Digital Circuits course at
-- Unicamp.
library ieee ;
use ieee.std_logic_1164.all ;
package player is
-- Calculate current speed based on internal register for speed, gravity value
-- and jump signal.
component calculate_speed
generic (
V_RES : natural -- Vertical Resolution
) ;
port (
jump : in std_logic ;
gravity : in integer range 0 to V_RES - 1 ;
speed : out integer range - V_RES to V_RES - 1 ;
clock : in std_logic ;
enable : in std_logic ;
reset : in std_logic
) ;
end component ;
-- Calculate current position based on internal register for position and
-- current speed value.
component calculate_position
generic (
V_RES : natural -- Vertical Resolution
) ;
port (
jump : in std_logic ;
gravity : in integer range 0 to V_RES - 1 ;
position : out integer range 0 to V_RES - 1 ;
clock : in std_logic ;
enable : in std_logic ;
reset : in std_logic
) ;
end component ;
end player ;
|
bsd-3-clause
|
kennethlyn/parallella-lcd-fpga
|
system/implementation/system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1/simulation/system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_tb.vhd
|
3
|
6128
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_tb.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_pkg.ALL;
ENTITY system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_tb IS
END ENTITY;
ARCHITECTURE system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_arch OF system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_tb IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 100 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 110 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 2000 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Simulation Complete"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 100 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_synth
system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_synth_inst:system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 40
)
PORT MAP(
CLK => wr_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
|
bsd-3-clause
|
kennethlyn/parallella-lcd-fpga
|
system/implementation/system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2/simulation/system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_dgen.vhd
|
3
|
4760
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_dgen.vhd
--
-- Description:
-- Used for write interface stimulus generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_pkg.ALL;
ENTITY system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_dg_arch OF system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_dgen IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
SIGNAL pr_w_en : STD_LOGIC := '0';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
BEGIN
WR_EN <= PRC_WR_EN ;
WR_DATA <= wr_data_i AFTER 50 ns;
----------------------------------------------
-- Generation of DATA
----------------------------------------------
gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst1:system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_w_en
);
END GENERATE;
pr_w_en <= PRC_WR_EN AND NOT FULL;
wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0);
END ARCHITECTURE;
|
bsd-3-clause
|
RaulHuertas/rhpackageexporter
|
MurmurHashGenerator/MurmurHash32Generator.vhdl
|
1
|
21731
|
-- Murmur Hash Code Generator
-- Author: Raul Gerardo Huertas Paiva
--Copyright (c) 2014, Raul Huertas
--All rights reserved.
----Redistribution and use in source and binary forms, with or without
----modification, are permitted provided that the following conditions are met:
----
----1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
--2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
--
--THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
--ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
--WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
--DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
--ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
--(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
--LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
--ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
--(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
--SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--The views and conclusions contained in the software and documentation are those
--of the authors and should not be interpreted as representing official policies,
--either expressed or implied, of the FreeBSD Project.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.ALL;
use IEEE.numeric_std.all;
use work.MurmurHashUtils.ALL;
entity MurmurHash32Generator is
generic (
ID_PRESENT: boolean := true;
ID_LENGTH: integer := 31
);
port(
--ENTRADAS
inputBlock : in std_logic_vector(31 downto 0);
readInput : in std_logic;
blockLength : in std_logic_vector(1 downto 0);
finalBlock : in std_logic;
start : in std_logic;
operationID : in std_logic_vector(ID_LENGTH downto 0);
seed : in std_logic_vector(31 downto 0);
--SALIDAS
canAccept : out std_logic;
resultReady : out std_logic;
result : out std_logic_vector(31 downto 0);
resultID : out std_logic_vector(ID_LENGTH downto 0);
--RELOJ
clk : in std_logic;
--Salidas de depuracion
dataStep1_dbg : out std_logic_vector(31 downto 0);
dataStep2_dbg : out std_logic_vector(31 downto 0);
dataStep3_dbg : out std_logic_vector(31 downto 0);
dataStep4_dbg : out std_logic_vector(31 downto 0);
dataStep5_dbg : out std_logic_vector(31 downto 0);
dataStep1_ID_dbg : out std_logic_vector(31 downto 0);
dataStep2_ID_dbg : out std_logic_vector(31 downto 0);
dataStep3_ID_dbg : out std_logic_vector(31 downto 0);
dataStep4_ID_dbg : out std_logic_vector(31 downto 0);
dataStep5_ID_dbg : out std_logic_vector(31 downto 0);
dataStepA_dbg : out std_logic_vector(31 downto 0);
dataStepB_dbg : out std_logic_vector(31 downto 0);
dataStepC_dbg : out std_logic_vector(31 downto 0);
dataStepD_dbg : out std_logic_vector(31 downto 0);
dataStepA_ID_dbg : out std_logic_vector(31 downto 0);
dataStepB_ID_dbg : out std_logic_vector(31 downto 0);
dataStepC_ID_dbg : out std_logic_vector(31 downto 0);
dataStepD_ID_dbg : out std_logic_vector(31 downto 0);
finalStep1_dbg : out std_logic_vector(31 downto 0);
finalStep2_dbg : out std_logic_vector(31 downto 0);
finalStep3_dbg : out std_logic_vector(31 downto 0);
finalStep4_dbg : out std_logic_vector(31 downto 0);
finalStep5_dbg : out std_logic_vector(31 downto 0);
finalStep1_ID_dbg : out std_logic_vector(31 downto 0);
finalStep2_ID_dbg : out std_logic_vector(31 downto 0);
finalStep3_ID_dbg : out std_logic_vector(31 downto 0);
finalStep4_ID_dbg : out std_logic_vector(31 downto 0);
finalStep5_ID_dbg : out std_logic_vector(31 downto 0)
);
end MurmurHash32Generator;
architecture Estructural of MurmurHash32Generator is
signal trabajando : boolean ;
-- Resultados de analizar datos alineados a 4 bytes
signal resultStep1 : Step1_Capture;
signal resultStep2 : Step2_C1Mult;
signal resultStep3 : Step3_R1;
signal resultStep4 : Step4_C2Mult;
signal resultStep5 : Step5_HashResult;
-- Resultados de analizar datos NO alineados a 4 bytes
signal resultStepA : Step1_EndianSwap;
signal resultStepB : Step2_C1Mult;
signal resultStepC : Step3_R1;
signal resultStepD : Step4_C2Mult;
--Combinar ambos resultados
signal mixed : FinalStep;
signal finalStep1 : FinalStep;
signal finalStep2 : FinalStep;
signal finalStep3 : FinalStep;
signal finalStep4 : FinalStep;
signal finalStep5 : FinalStep;
signal finalStep6 : FinalStep;
signal lengthCounter: unsigned(31 downto 0);
signal stepAdata : std_logic_vector(31 downto 0);
signal CompletedDataA : std_logic_vector(31 downto 0);
signal CompletedDataB : std_logic_vector(31 downto 0);
signal CompletedDataC : std_logic_vector(31 downto 0);
signal dataBeatValidQ : boolean;
--balancing FF
signal resultReady_temp : std_logic;
signal result_temp : std_logic_vector(31 downto 0);
signal resultID_temp : std_logic_vector(ID_LENGTH downto 0);
begin
--Conectando las salidas de depuracion
dataStep1_dbg <= resultStep1.data;
dataStep2_dbg <= resultStep2.data;
dataStep3_dbg <= resultStep3.data;
dataStep4_dbg <= resultStep4.data;
dataStep5_dbg <= resultStep5.hash;
dataStepA_dbg <= resultStepA.data;
dataStepA_ID_dbg <= resultStepA.operationID;
dataStepB_dbg <= resultStepB.data;
dataStepB_ID_dbg <= resultStepB.operationID;
dataStepC_dbg <= resultStepC.data;
dataStepC_ID_dbg <= resultStepC.operationID;
dataStepD_dbg <= resultStepD.data;
dataStepD_ID_dbg <= resultStepD.operationID;
dataStep1_ID_dbg <= resultStep1.operationID;
dataStep2_ID_dbg <= resultStep2.operationID;
dataStep3_ID_dbg <= resultStep3.operationID;
dataStep4_ID_dbg <= resultStep4.operationID;
dataStep5_ID_dbg <= resultStep5.operationID;
finalStep1_dbg <= finalStep1.hash;
finalStep2_dbg <= finalStep2.hash;
finalStep3_dbg <= finalStep3.hash;
finalStep4_dbg <= finalStep4.hash;
finalStep5_dbg <= finalStep5.hash;
finalStep1_ID_dbg <= finalStep1.operationID;
finalStep2_ID_dbg <= finalStep2.operationID;
finalStep3_ID_dbg <= finalStep3.operationID;
finalStep4_ID_dbg <= finalStep4.operationID;
finalStep5_ID_dbg <= finalStep5.operationID;
canAccept <= '1';-- Siemrpe se debe poder recibir datos en este core
--Definiendo la captura de datos
CaptureStep: process(clk, inputBlock, readInput, blockLength, finalBlock, start, operationID, seed) begin
if rising_edge(clk) then
if(readInput = '1') then
resultStep1.data <= (inputBlock);
resultStep1.dataLength <= blockLength;
resultStep1.isFirst <= (start='1');
resultStep1.isLast <= (finalBlock='1');
if (start='1') then
resultStep1.operationID <= operationID;
end if;
resultStep1.seed <= seed;
end if;--readInput
resultStep1.dataValid <= (readInput='1');
end if;--clk
end process CaptureStep;
C1MultStep: process(clk, resultStep1)
variable c1MutlResult : std_logic_vector(63 downto 0);
variable dataBeatValidQ : boolean;
begin
c1MutlResult := (resultStep1.data*C1);
dataBeatValidQ := resultStep1.dataValid and (resultStep1.dataLength="11");
if rising_edge(clk) then
if(dataBeatValidQ) then
resultStep2.data <= c1MutlResult(31 downto 0);
resultStep2.dataLength <= resultStep1.dataLength;
resultStep2.isFirst <= resultStep1.isFirst;
resultStep2.isLast <= resultStep1.isLast;
resultStep2.operationID <= resultStep1.operationID;
resultStep2.seed <= resultStep1.seed;
end if;--readInput
resultStep2.dataValid <= dataBeatValidQ;
end if;--clk
end process C1MultStep;
CompletedDataA <= x"00"&x"00"&x"00"&resultStep1.data(7 downto 0);
CompletedDataB <= x"00"&x"00"&resultStep1.data(15 downto 0);
CompletedDataC <= x"00"&resultStep1.data(23 downto 0);
with resultStep1.dataLength select
stepAdata <= CompletedDataA when "00",
CompletedDataB when "01",
CompletedDataC when "10",
(others => '-') when others;
dataBeatValidQ <= (resultStep1.dataValid) and (resultStep1.dataLength/="11");
StepA_EndianSwapProcess: process(clk, resultStep1, stepAdata, dataBeatValidQ)
begin
-- if (resultStep1.dataLength="00") then
-- stepAdata := CompletedDataA;
-- elsif (resultStep1.dataLength="01") then
-- stepAdata := CompletedDataB;
-- elsif (resultStep1.dataLength="10") then
-- stepAdata := CompletedDataC;
-- else
-- stepAdata := (others => '-');
-- end if;
-- case resultStep1.dataLength is
-- when "00" => stepAdata := CompletedDataA;
-- when "01" => stepAdata := CompletedDataB;
-- when "10" => stepAdata := CompletedDataC;
-- when others => stepAdata := (others => '-');
-- end case;
if rising_edge(clk) then
if(dataBeatValidQ) then
resultStepA.data <= stepAdata;
resultStepA.dataLength <= resultStep1.dataLength;
resultStepA.isFirst <= resultStep1.isFirst;
resultStepA.isLast <= resultStep1.isLast;
resultStepA.operationID <= resultStep1.operationID;
resultStepA.seed <= resultStep1.seed;
end if;
resultStepA.dataValid <= dataBeatValidQ;
end if;--clk
end process StepA_EndianSwapProcess;
StepB_C1Mult: process(clk, resultStepA)
variable c1MutlResult : std_logic_vector(63 downto 0);
begin
c1MutlResult := (resultStepA.data*C1);
if rising_edge(clk) then
if(resultStepA.dataValid) then
resultStepB.data <= c1MutlResult(31 downto 0);
resultStepB.dataLength <= resultStepA.dataLength;
resultStepB.isFirst <= resultStepA.isFirst;
resultStepB.isLast <= resultStepA.isLast;
resultStepB.operationID <= resultStepA.operationID;
resultStepB.seed <= resultStepA.seed;
end if;--readInput
resultStepB.dataValid <= resultStepA.dataValid;
end if;--clk
end process StepB_C1Mult;
StepC_R1Rotation: process(clk, resultStepB)
begin
if rising_edge(clk) then
if(resultStepB.dataValid) then
resultStepC.data(31 downto 15) <= resultStepB.data(16 downto 0);
resultStepC.data(14 downto 0) <= resultStepB.data(31 downto 17);
resultStepC.dataLength <= resultStepB.dataLength;
resultStepC.isFirst <= resultStepB.isFirst;
resultStepC.isLast <= resultStepB.isLast;
resultStepC.operationID <= resultStepB.operationID;
resultStepC.seed <= resultStepB.seed;
end if;--readInput
resultStepC.dataValid <= resultStepB.dataValid;
end if;--clk
end process StepC_R1Rotation;
StepD_C2Mult: process(clk, resultStepC)
variable c2MutlResult : std_logic_vector(63 downto 0);
begin
c2MutlResult := (resultStepC.data*C2);
if rising_edge(clk) then
if(resultStepC.dataValid) then
resultStepD.data <= c2MutlResult(31 downto 0);
resultStepD.dataLength <= resultStepC.dataLength;
resultStepD.isFirst <= resultStepC.isFirst;
resultStepD.isLast <= resultStepC.isLast;
resultStepD.operationID <= resultStepC.operationID;
resultStepD.seed <= resultStepC.seed;
end if;--readInput
resultStepD.dataValid <= resultStepC.dataValid;
end if;--clk
end process StepD_C2Mult;
R1Step: process(clk, resultStep2)
begin
if rising_edge(clk) then
if(resultStep2.dataValid) then
resultStep3.data(31 downto 15) <= resultStep2.data(16 downto 0);
resultStep3.data(14 downto 0) <= resultStep2.data(31 downto 17);
resultStep3.dataLength <= resultStep2.dataLength;
resultStep3.isFirst <= resultStep2.isFirst;
resultStep3.isLast <= resultStep2.isLast;
resultStep3.operationID <= resultStep2.operationID;
resultStep3.seed <= resultStep2.seed;
end if;--readInput
resultStep3.dataValid <= resultStep2.dataValid;
end if;--clk
end process R1Step;
C2MultStep: process(clk, resultStep3)
variable c2MutlResult : std_logic_vector(63 downto 0);
begin
c2MutlResult := (resultStep3.data*C2);
if rising_edge(clk) then
if(resultStep3.dataValid) then
resultStep4.data <= c2MutlResult(31 downto 0);
resultStep4.dataLength <= resultStep3.dataLength;
resultStep4.isFirst <= resultStep3.isFirst;
resultStep4.isLast <= resultStep3.isLast;
resultStep4.operationID <= resultStep3.operationID;
resultStep4.seed <= resultStep3.seed;
end if;--readInput
resultStep4.dataValid <= resultStep3.dataValid;
end if;--clk
end process C2MultStep;
UpdateHashStep: process(clk, resultStep4, resultStep5, resultStepD)
variable dataAvailable : boolean;
variable selectOrigin: std_logic_vector( 1 downto 0 );
variable newHash: std_logic_vector( 31 downto 0 );
begin
if rising_edge(clk) then
dataAvailable := resultStep4.dataValid or resultStepD.dataValid;
selectOrigin := mh3_boolean_to_std_logic(resultStep4.dataValid) & mh3_boolean_to_std_logic(resultStepD.dataValid);
if(dataAvailable) then
case selectOrigin is
when "01" =>
if(resultStepD.isFirst)then
newHash := resultStepD.seed xor resultStepD.data;
else
newHash := resultStep5.hash xor resultStepD.data;
end if;
resultStep5.operationID <= resultStepD.operationID;
resultStep5.isFirst <= (resultStepD.isFirst);
resultStep5.isLast <= (resultStepD.isLast);
resultStep5.dataLength <= resultStepD.dataLength;
when "10" =>
if(resultStep4.isFirst)then
newHash :=funcionFinalHashOperation_4B(resultStep4.seed, resultStep4.data);
else
newHash := funcionFinalHashOperation_4B(resultStep5.hash, resultStep4.data);
end if;
resultStep5.operationID <= resultStep4.operationID;
resultStep5.isFirst <= (resultStep4.isFirst);
resultStep5.isLast <= (resultStep4.isLast);
resultStep5.dataLength <= resultStep4.dataLength;
when others =>
newHash := resultStep5.hash;
end case;
resultStep5.hash <= newHash;
end if;--readInput
resultStep5.resultReady <= dataAvailable;
end if;--clk
end process UpdateHashStep;
UpdateMix: process(clk, resultStep5, lengthCounter)
variable sum1 : unsigned(1 downto 0);
variable sum2 : unsigned(2 downto 0);
variable newLen : unsigned(31 downto 0);
begin
if rising_edge(clk) then
if(resultStep5.resultReady ) then
mixed.hash <= resultStep5.hash;
mixed.operationID <= resultStep5.operationID;
--mixed.totalLen <= "0000"&"0000"&"0000"&"0000"&"0000"&"0000"&"0000"&"1000";
mixed.isFirst <= (resultStep5.isFirst);
mixed.isLast <= (resultStep5.isLast);
if (resultStep5.isFirst) then
sum1 := unsigned(resultStep5.dataLength);
sum2 := ("0"&sum1)+1;
newLen( 2 downto 0) := (sum2);
newLen(lengthCounter'HIGH downto 3) := ( others=> '0');
mixed.totalLen <= std_logic_vector(newLen);
lengthCounter <= newLen;
else
sum1 := unsigned(resultStep5.dataLength);
sum2 := ("0"&sum1)+1;
newLen:= (lengthCounter+sum2);
mixed.totalLen <= std_logic_vector(newLen);
lengthCounter <= newLen;
end if;
end if;--readInput
mixed.resultReady <= resultStep5.resultReady;
end if;--clk
end process UpdateMix;
FinalProc_Step1: process(clk, mixed)
begin
if rising_edge(clk) then
if(mixed.resultReady and mixed.isLast) then
finalStep1.hash <= mixed.hash xor mixed.totalLen;
finalStep1.operationID <= mixed.operationID;
finalStep1.totalLen <= mixed.totalLen;
finalStep1.isFirst <= (mixed.isFirst);
finalStep1.isLast <= (mixed.isLast);
end if;--readInput
finalStep1.resultReady <= mixed.resultReady and mixed.isLast;
end if;--clk
end process FinalProc_Step1;
FinalProc_Step2: process(clk, finalStep1)
begin
if rising_edge(clk) then
if(finalStep1.resultReady) then
finalStep2.hash <= xor_with_shiftRight(finalStep1.hash, FinalShift1);
finalStep2.operationID <= finalStep1.operationID;
finalStep2.totalLen <= finalStep1.totalLen;
finalStep2.isFirst <= finalStep1.isFirst;
finalStep2.isLast <= finalStep1.isLast;
end if;--readInput
finalStep2.resultReady <= finalStep1.resultReady;
end if;--clk
end process FinalProc_Step2;
FinalProc_Step3: process(clk, finalStep2)
variable fullMultResult : std_logic_vector( 63 downto 0);
begin
fullMultResult := finalStep2.hash*FinalC1;
if rising_edge(clk) then
if(finalStep2.resultReady) then
finalStep3.hash <= fullMultResult(31 downto 0);
finalStep3.operationID <= finalStep2.operationID;
finalStep3.isFirst <= (finalStep2.isFirst);
finalStep3.isLast <= (finalStep2.isLast);
finalStep3.totalLen <= finalStep2.totalLen;
end if;--readInput
finalStep3.resultReady <= finalStep2.resultReady;
end if;--clk
end process FinalProc_Step3;
FinalProc_Step4: process(clk, finalStep3)
begin
if rising_edge(clk) then
if(finalStep3.resultReady) then
finalStep4.hash <= xor_with_shiftRight(finalStep3.hash, FinalShift2);
finalStep4.operationID <= finalStep3.operationID;
--finalStep4.resultReady <= finalStep3.resultReady;
finalStep4.isFirst <= (finalStep3.isFirst);
finalStep4.isLast <= (finalStep3.isLast);
finalStep4.totalLen <= finalStep3.totalLen;
end if;--readInput
finalStep4.resultReady <= finalStep3.resultReady;
end if;--clk
end process FinalProc_Step4;
FinalProc_Step5: process(clk, finalStep4)
begin
if rising_edge(clk) then
if(finalStep4.resultReady) then
finalStep5.hash <= ClampedMult(finalStep4.hash , FinalC2);
finalStep5.operationID <= finalStep4.operationID;
finalStep5.totalLen <= finalStep4.totalLen;
finalStep5.isFirst <= (finalStep4.isFirst);
finalStep5.isLast <= (finalStep4.isLast);
end if;--readInput
finalStep5.resultReady <= finalStep4.resultReady;
end if;--clk
end process FinalProc_Step5;
FinalProc_Step6: process(clk, finalStep5)
begin
if rising_edge(clk) then
if(finalStep5.resultReady) then
finalStep6.hash <= xor_with_shiftRight(finalStep5.hash, FinalShift3);
finalStep6.operationID <= finalStep5.operationID;
finalStep6.totalLen <= finalStep5.totalLen;
finalStep6.isFirst <= (finalStep5.isFirst);
finalStep6.isLast <= (finalStep5.isLast);
end if;--readInput
finalStep6.resultReady <= finalStep5.resultReady and finalStep5.isLast;
end if;--clk
end process FinalProc_Step6;
--Conectando las salidas a este ultimo paso
resultReady_temp <= mh3_boolean_to_std_logic(finalStep6.resultReady);
result_temp <= finalStep6.hash;
resultID_temp <= finalStep6.operationID;
FinalStage: process(clk, resultReady_temp, result_temp, resultID_temp) begin
if rising_edge(clk) then
resultReady <= resultReady_temp;
result <= result_temp;
resultID <= resultID_temp;
end if;--clk
end process FinalStage;
end architecture Estructural;
|
bsd-3-clause
|
kennethlyn/parallella-lcd-fpga
|
system/hdl/system_stub.vhd
|
3
|
6782
|
-------------------------------------------------------------------------------
-- system_stub.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_stub is
port (
processing_system7_0_MIO : inout std_logic_vector(53 downto 0);
processing_system7_0_PS_SRSTB_pin : in std_logic;
processing_system7_0_PS_CLK_pin : in std_logic;
processing_system7_0_PS_PORB_pin : in std_logic;
processing_system7_0_DDR_Clk : inout std_logic;
processing_system7_0_DDR_Clk_n : inout std_logic;
processing_system7_0_DDR_CKE : inout std_logic;
processing_system7_0_DDR_CS_n : inout std_logic;
processing_system7_0_DDR_RAS_n : inout std_logic;
processing_system7_0_DDR_CAS_n : inout std_logic;
processing_system7_0_DDR_WEB_pin : out std_logic;
processing_system7_0_DDR_BankAddr : inout std_logic_vector(2 downto 0);
processing_system7_0_DDR_Addr : inout std_logic_vector(14 downto 0);
processing_system7_0_DDR_ODT : inout std_logic;
processing_system7_0_DDR_DRSTB : inout std_logic;
processing_system7_0_DDR_DQ : inout std_logic_vector(31 downto 0);
processing_system7_0_DDR_DM : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_DQS : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_DQS_n : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_VRN : inout std_logic;
processing_system7_0_DDR_VRP : inout std_logic;
axi_dispctrl_0_HSYNC_O_pin : out std_logic;
axi_dispctrl_0_VSYNC_O_pin : out std_logic;
axi_dispctrl_0_PXL_CLK_O_pin : out std_logic;
axi_dispctrl_0_DE_O_pin : out std_logic;
axi_dispctrl_0_RED_O_pin : out std_logic_vector(7 downto 0);
axi_dispctrl_0_GREEN_O_pin : out std_logic_vector(7 downto 0);
axi_dispctrl_0_BLUE_O_pin : out std_logic_vector(7 downto 0);
axi_dispctrl_0_ENABLE_O_pin : out std_logic;
processing_system7_0_I2C0_SDA_pin : inout std_logic;
processing_system7_0_I2C0_SCL_pin : inout std_logic;
processing_system7_0_I2C0_INT_N_pin : in std_logic;
processing_system7_0_FCLK_CLK0_pin : out std_logic
);
end system_stub;
architecture STRUCTURE of system_stub is
component system is
port (
processing_system7_0_MIO : inout std_logic_vector(53 downto 0);
processing_system7_0_PS_SRSTB_pin : in std_logic;
processing_system7_0_PS_CLK_pin : in std_logic;
processing_system7_0_PS_PORB_pin : in std_logic;
processing_system7_0_DDR_Clk : inout std_logic;
processing_system7_0_DDR_Clk_n : inout std_logic;
processing_system7_0_DDR_CKE : inout std_logic;
processing_system7_0_DDR_CS_n : inout std_logic;
processing_system7_0_DDR_RAS_n : inout std_logic;
processing_system7_0_DDR_CAS_n : inout std_logic;
processing_system7_0_DDR_WEB_pin : out std_logic;
processing_system7_0_DDR_BankAddr : inout std_logic_vector(2 downto 0);
processing_system7_0_DDR_Addr : inout std_logic_vector(14 downto 0);
processing_system7_0_DDR_ODT : inout std_logic;
processing_system7_0_DDR_DRSTB : inout std_logic;
processing_system7_0_DDR_DQ : inout std_logic_vector(31 downto 0);
processing_system7_0_DDR_DM : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_DQS : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_DQS_n : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_VRN : inout std_logic;
processing_system7_0_DDR_VRP : inout std_logic;
axi_dispctrl_0_HSYNC_O_pin : out std_logic;
axi_dispctrl_0_VSYNC_O_pin : out std_logic;
axi_dispctrl_0_PXL_CLK_O_pin : out std_logic;
axi_dispctrl_0_DE_O_pin : out std_logic;
axi_dispctrl_0_RED_O_pin : out std_logic_vector(7 downto 0);
axi_dispctrl_0_GREEN_O_pin : out std_logic_vector(7 downto 0);
axi_dispctrl_0_BLUE_O_pin : out std_logic_vector(7 downto 0);
axi_dispctrl_0_ENABLE_O_pin : out std_logic;
processing_system7_0_I2C0_SDA_pin : inout std_logic;
processing_system7_0_I2C0_SCL_pin : inout std_logic;
processing_system7_0_I2C0_INT_N_pin : in std_logic;
processing_system7_0_FCLK_CLK0_pin : out std_logic
);
end component;
attribute BOX_TYPE : STRING;
attribute BOX_TYPE of system : component is "user_black_box";
begin
system_i : system
port map (
processing_system7_0_MIO => processing_system7_0_MIO,
processing_system7_0_PS_SRSTB_pin => processing_system7_0_PS_SRSTB_pin,
processing_system7_0_PS_CLK_pin => processing_system7_0_PS_CLK_pin,
processing_system7_0_PS_PORB_pin => processing_system7_0_PS_PORB_pin,
processing_system7_0_DDR_Clk => processing_system7_0_DDR_Clk,
processing_system7_0_DDR_Clk_n => processing_system7_0_DDR_Clk_n,
processing_system7_0_DDR_CKE => processing_system7_0_DDR_CKE,
processing_system7_0_DDR_CS_n => processing_system7_0_DDR_CS_n,
processing_system7_0_DDR_RAS_n => processing_system7_0_DDR_RAS_n,
processing_system7_0_DDR_CAS_n => processing_system7_0_DDR_CAS_n,
processing_system7_0_DDR_WEB_pin => processing_system7_0_DDR_WEB_pin,
processing_system7_0_DDR_BankAddr => processing_system7_0_DDR_BankAddr,
processing_system7_0_DDR_Addr => processing_system7_0_DDR_Addr,
processing_system7_0_DDR_ODT => processing_system7_0_DDR_ODT,
processing_system7_0_DDR_DRSTB => processing_system7_0_DDR_DRSTB,
processing_system7_0_DDR_DQ => processing_system7_0_DDR_DQ,
processing_system7_0_DDR_DM => processing_system7_0_DDR_DM,
processing_system7_0_DDR_DQS => processing_system7_0_DDR_DQS,
processing_system7_0_DDR_DQS_n => processing_system7_0_DDR_DQS_n,
processing_system7_0_DDR_VRN => processing_system7_0_DDR_VRN,
processing_system7_0_DDR_VRP => processing_system7_0_DDR_VRP,
axi_dispctrl_0_HSYNC_O_pin => axi_dispctrl_0_HSYNC_O_pin,
axi_dispctrl_0_VSYNC_O_pin => axi_dispctrl_0_VSYNC_O_pin,
axi_dispctrl_0_PXL_CLK_O_pin => axi_dispctrl_0_PXL_CLK_O_pin,
axi_dispctrl_0_DE_O_pin => axi_dispctrl_0_DE_O_pin,
axi_dispctrl_0_RED_O_pin => axi_dispctrl_0_RED_O_pin,
axi_dispctrl_0_GREEN_O_pin => axi_dispctrl_0_GREEN_O_pin,
axi_dispctrl_0_BLUE_O_pin => axi_dispctrl_0_BLUE_O_pin,
axi_dispctrl_0_ENABLE_O_pin => axi_dispctrl_0_ENABLE_O_pin,
processing_system7_0_I2C0_SDA_pin => processing_system7_0_I2C0_SDA_pin,
processing_system7_0_I2C0_SCL_pin => processing_system7_0_I2C0_SCL_pin,
processing_system7_0_I2C0_INT_N_pin => processing_system7_0_I2C0_INT_N_pin,
processing_system7_0_FCLK_CLK0_pin => processing_system7_0_FCLK_CLK0_pin
);
end architecture STRUCTURE;
|
bsd-3-clause
|
alemedeiros/flappy_vhdl
|
control/game_control.vhd
|
1
|
3155
|
-- file: control/game_control.vhd
-- authors: Alexandre Medeiros and Gabriel Lopes
--
-- A Flappy bird implementation in VHDL for a Digital Circuits course at
-- Unicamp.
--
-- Main game Finite State machine.
library ieee ;
use ieee.std_logic_1164.all ;
entity game_control is
port (
game_over : in std_logic ;
reset : in std_logic ;
pause : in std_logic ;
jump : in std_logic ;
clock : in std_logic ;
obst_rem : in std_logic ;
new_obst : out std_logic ;
timer : in std_logic ;
-- Enable signals for each module.
calculate_speed : out std_logic ;
calculate_position : out std_logic ;
obst_regbank : out std_logic ;
update_obstacles : out std_logic ;
colision_detection : out std_logic ;
draw_frame : out std_logic ;
ledcon : out std_logic ;
internal_reset : out std_logic
) ;
end game_control ;
architecture behavior of game_control is
-- State type
type state_t is (start, update, draw, loser) ;
signal state : state_t := start ;
signal next_state : state_t := start ;
begin
process (reset, clock) --clock)
variable count : integer ;
begin
if reset = '1' then
internal_reset <= '1' ;
state <= start ;
elsif rising_edge(clock) then
case state is
when start =>
state <= update ;
calculate_speed <= '0' ;
calculate_position <= '0' ;
obst_regbank <= '0' ;
update_obstacles <= '0' ;
new_obst <= '0' ;
colision_detection <= '0' ;
draw_frame <= '0' ;
ledcon <= '0' ;
internal_reset <= '1' ;
when update =>
if game_over = '1' then
state <= loser ;
elsif pause = '1' then
state <= draw ;
else
state <= update ;
end if ;
--state <= draw ;
calculate_speed <= '1' ;
calculate_position <= '1' ;
obst_regbank <= '1' ;
update_obstacles <= '1' ;
new_obst <= '0' ; -- CHECK
colision_detection <= '1' ;
draw_frame <= '1' ;
ledcon <= '0' ;
internal_reset <= '0' ;
when draw =>
if game_over = '1' then
state <= loser ;
elsif pause = '1' then
state <= draw ;
else
state <= update ;
end if ;
calculate_speed <= '0' ;
calculate_position <= '0' ;
obst_regbank <= '0' ;
update_obstacles <= '0' ;
new_obst <= '0' ;
colision_detection <= '1' ;
draw_frame <= '1' ;
ledcon <= '1' ;
internal_reset <= '0' ;
when loser =>
state <= loser ;
calculate_speed <= '0' ;
calculate_position <= '0' ;
obst_regbank <= '0' ;
update_obstacles <= '0' ;
new_obst <= '0' ;
colision_detection <= '0' ;
draw_frame <= '1' ;
ledcon <= '1' ;
internal_reset <= '0' ;
when others =>
state <= start ;
end case ;
end if ;
end process ;
end behavior ;
|
bsd-3-clause
|
kennethlyn/parallella-lcd-fpga
|
system/implementation/system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2/simulation/system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_pkg.vhd
|
3
|
11785
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for FIFO Generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_exdes IS
PORT (
CLK : IN std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(1-1 DOWNTO 0);
DOUT : OUT std_logic_vector(1-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_pkg;
PACKAGE BODY system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2_pkg;
|
bsd-3-clause
|
kennethlyn/parallella-lcd-fpga
|
system/implementation/system_axi_vdma_0_wrapper_fifo_generator_v9_3/simulation/system_axi_vdma_0_wrapper_fifo_generator_v9_3_dgen.vhd
|
4
|
4710
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_vdma_0_wrapper_fifo_generator_v9_3_dgen.vhd
--
-- Description:
-- Used for write interface stimulus generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.system_axi_vdma_0_wrapper_fifo_generator_v9_3_pkg.ALL;
ENTITY system_axi_vdma_0_wrapper_fifo_generator_v9_3_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_dg_arch OF system_axi_vdma_0_wrapper_fifo_generator_v9_3_dgen IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
SIGNAL pr_w_en : STD_LOGIC := '0';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
BEGIN
WR_EN <= PRC_WR_EN ;
WR_DATA <= wr_data_i AFTER 50 ns;
----------------------------------------------
-- Generation of DATA
----------------------------------------------
gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst1:system_axi_vdma_0_wrapper_fifo_generator_v9_3_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_w_en
);
END GENERATE;
pr_w_en <= PRC_WR_EN AND NOT FULL;
wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0);
END ARCHITECTURE;
|
bsd-3-clause
|
RaulHuertas/rhpackageexporter
|
MurmurHashGenerator/MurmurHash_BinarySearchModule.vhd
|
12226531
|
0
|
bsd-3-clause
|
|
stnolting/neo430
|
rtl/core/neo430_crc.vhd
|
1
|
8084
|
-- #################################################################################################
-- # << NEO430 - CRC Module >> #
-- # ********************************************************************************************* #
-- # This module generates CRC16 and CRC32 check sums with variable polynomial masks. #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
-- # #
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
-- # conditions and the following disclaimer. #
-- # #
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
-- # conditions and the following disclaimer in the documentation and/or other materials #
-- # provided with the distribution. #
-- # #
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
-- # endorse or promote products derived from this software without specific prior written #
-- # permission. #
-- # #
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
-- # ********************************************************************************************* #
-- # The NEO430 Processor - https://github.com/stnolting/neo430 #
-- #################################################################################################
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library neo430;
use neo430.neo430_package.all;
entity neo430_crc is
port (
-- host access --
clk_i : in std_ulogic; -- global clock line
rden_i : in std_ulogic; -- read enable
wren_i : in std_ulogic; -- write enable
addr_i : in std_ulogic_vector(15 downto 0); -- address
data_i : in std_ulogic_vector(15 downto 0); -- data in
data_o : out std_ulogic_vector(15 downto 0) -- data out
);
end neo430_crc;
architecture neo430_crc_rtl of neo430_crc is
-- IO space: module base address --
constant hi_abb_c : natural := index_size_f(io_size_c)-1; -- high address boundary bit
constant lo_abb_c : natural := index_size_f(crc_size_c); -- low address boundary bit
-- access control --
signal acc_en : std_ulogic; -- module access enable
signal addr : std_ulogic_vector(15 downto 0); -- access address
signal wren : std_ulogic;
-- accessible registers --
signal idata : std_ulogic_vector(07 downto 0);
signal poly : std_ulogic_vector(31 downto 0);
signal start : std_ulogic;
signal mode : std_ulogic;
-- core --
signal cnt : std_ulogic_vector(02 downto 0);
signal run : std_ulogic;
signal crc_bit : std_ulogic;
signal crc_sr : std_ulogic_vector(31 downto 0);
begin
-- Access Control -----------------------------------------------------------
-- -----------------------------------------------------------------------------
acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = crc_base_c(hi_abb_c downto lo_abb_c)) else '0';
addr <= crc_base_c(15 downto lo_abb_c) & addr_i(lo_abb_c-1 downto 1) & '0'; -- word aligned
wren <= acc_en and wren_i;
-- Write Access -------------------------------------------------------------
-- -----------------------------------------------------------------------------
write_access: process(clk_i)
begin
if rising_edge(clk_i) then
start <= '0';
if (wren = '1') then
-- operands --
if (addr = crc_crc16_in_addr_c) or (addr = crc_crc32_in_addr_c) then -- write data & start operation
idata <= data_i(7 downto 0);
start <= '1'; -- start operation
end if;
if (addr = crc_poly_lo_addr_c) then -- low (part) polynomial
poly(15 downto 00) <= data_i;
end if;
if (addr = crc_poly_hi_addr_c) then -- high (part) polynomial
poly(31 downto 16) <= data_i;
end if;
-- operation selection --
if (addr = crc_crc16_in_addr_c) then
mode <= '0'; -- crc16 mode
else
mode <= '1'; -- crc32 mode
end if;
end if;
end if;
end process write_access;
-- CRC Core -----------------------------------------------------------------
-- -----------------------------------------------------------------------------
crc_core: process(clk_i)
begin
if rising_edge(clk_i) then
-- arbitration --
if (start = '1') then
run <= '1';
elsif (cnt = "000") then -- all done?
run <= '0';
end if;
if (start = '1') then
cnt <= "111"; -- start with MSB
elsif (run = '1') then
cnt <= std_ulogic_vector(unsigned(cnt) - 1);
end if;
-- computation --
if ((wren = '1') and (addr = crc_resx_addr_c)) then -- write low part of CRC shift reg
crc_sr(15 downto 0) <= data_i;
elsif ((wren = '1') and (addr = crc_resy_addr_c)) then -- write high part of CRC shift reg
crc_sr(31 downto 16) <= data_i;
elsif (run = '1') then -- compute new CRC
if (crc_bit /= idata(to_integer(unsigned(cnt(2 downto 0))))) then
crc_sr <= (crc_sr(30 downto 0) & '0') xor poly;
else
crc_sr <= (crc_sr(30 downto 0) & '0');
end if;
end if;
end if;
end process crc_core;
-- select compare bit according to selected mode --
crc_bit <= crc_sr(31) when (mode = '1') else crc_sr(15);
-- Read Access --------------------------------------------------------------
-- -----------------------------------------------------------------------------
read_access: process(clk_i)
begin
if rising_edge(clk_i) then
data_o <= (others => '0');
if (acc_en = '1') and (rden_i = '1') then
if (addr = crc_resx_addr_c) then
data_o <= crc_sr(15 downto 00);
else -- if addr = crc_resy_addr_c
data_o <= crc_sr(31 downto 16);
end if;
end if;
end if;
end process read_access;
end neo430_crc_rtl;
|
bsd-3-clause
|
electronicvisions/brick
|
test/source/vhdl/counter.vhd
|
2
|
626
|
library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter is
port( clk: in std_logic;
reset: in std_logic;
enable: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture behav of counter is
signal pre_count: std_logic_vector(3 downto 0);
begin
process(clk, enable, reset)
begin
if reset = '1' then
pre_count <= "0000";
elsif (clk='1' and clk'event) then
if enable = '1' then
pre_count <= pre_count + "1";
end if;
end if;
end process;
count <= pre_count;
end behav;
|
bsd-3-clause
|
dergraaf/loa
|
fpga/modules/motor_control/hdl/dc_motor_module.vhd
|
2
|
3922
|
-------------------------------------------------------------------------------
-- Title : Motor control for DC Motors
-- Project : Loa
-------------------------------------------------------------------------------
-- Author : Fabian Greif <[email protected]>
-- Company : Roboterclub Aachen e.V.
-- Platform : Spartan 3-400
-------------------------------------------------------------------------------
-- Description:
--
-- Generates a symmetric (center-aligned) PWM without deadtime
--
-- Register Map:
-- Base Address + 0 | W | PWM
-- Base Address + 0 | R | unused
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.bus_pkg.all;
use work.utils_pkg.all;
use work.motor_control_pkg.all;
use work.symmetric_pwm_pkg.all;
entity dc_motor_module is
generic (
BASE_ADDRESS : integer range 0 to 16#7FFF#;
WIDTH : positive := 12; -- Number of bits for the PWM generation (e.g. 12 => 0..4095)
PRESCALER : positive
);
port (
pwm1_p : out std_logic; -- Halfbridge 1
pwm2_p : out std_logic; -- Halfbridge 2
sd_p : out std_logic; -- Shutdown
-- Disable switching
break_p : in std_logic;
bus_o : out busdevice_out_type;
bus_i : in busdevice_in_type;
clk : in std_logic
);
end dc_motor_module;
-------------------------------------------------------------------------------
architecture behavioral of dc_motor_module is
type dc_motor_module_type is record
data_out : std_logic_vector(15 downto 0); -- currently not used
pwm_value : std_logic_vector(WIDTH - 1 downto 0); -- PWM value
sd : std_logic; -- Shutdown
end record;
signal clk_en : std_logic := '1';
signal underflow : std_logic; -- currently not used
signal overflow : std_logic; -- currently not used
signal pwm : std_logic;
signal r, rin : dc_motor_module_type := (
data_out => (others => '0'),
pwm_value => (others => '0'),
sd => '1'
);
begin
seq_proc : process(clk)
begin
if rising_edge(clk) then
r <= rin;
end if;
end process seq_proc;
comb_proc : process(bus_i.addr, bus_i.data(15),
bus_i.data(WIDTH - 1 downto 0), bus_i.re, bus_i.we, pwm, break_p,
r, r.sd)
variable v : dc_motor_module_type;
begin
v := r;
-- Set default values
v.data_out := (others => '0');
-- Check Bus Address
if bus_i.addr = std_logic_vector(to_unsigned(BASE_ADDRESS, 15)) then
if bus_i.we = '1' then
v.pwm_value := bus_i.data(WIDTH - 1 downto 0);
v.sd := bus_i.data(15);
elsif bus_i.re = '1' then
-- v.data_out := r.counter;
end if;
end if;
if r.sd = '1' then
pwm1_p <= '0';
pwm2_p <= '0';
sd_p <= '1';
else
if break_p = '1' then
pwm1_p <= '0';
pwm2_p <= '0';
else
pwm1_p <= pwm;
pwm2_p <= not pwm;
end if;
sd_p <= '0';
end if;
rin <= v;
end process comb_proc;
bus_o.data <= r.data_out;
-- Generate clock for the PWM generator
divider : clock_divider
generic map (
DIV => PRESCALER)
port map (
clk_out_p => clk_en,
clk => clk);
pwm_generator : symmetric_pwm
generic map (
WIDTH => WIDTH)
port map (
pwm_p => pwm,
underflow_p => underflow,
overflow_p => overflow,
clk_en_p => clk_en,
value_p => r.pwm_value,
reset => '0',
clk => clk);
end behavioral;
|
bsd-3-clause
|
dergraaf/loa
|
fpga/modules/uss_tx/hdl/uss_tx_pkg.vhd
|
2
|
1661
|
-------------------------------------------------------------------------------
-- Title : Package for Ultrasonic transmitter
-------------------------------------------------------------------------------
-- Author : strongly-typed
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2012
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.bus_pkg.all;
use work.motor_control_pkg.all;
package uss_tx_pkg is
-----------------------------------------------------------------------------
-- Component declarations
-----------------------------------------------------------------------------
component uss_tx_module
generic (
BASE_ADDRESS : integer range 0 to 16#7FFF#);
port (
uss_tx0_out_p : out half_bridge_type;
uss_tx1_out_p : out half_bridge_type;
uss_tx2_out_p : out half_bridge_type;
clk_uss_enable_p : out std_logic;
bus_o : out busdevice_out_type;
bus_i : in busdevice_in_type;
clk : in std_logic);
end component;
component serialiser is
generic (
BITPATTERN_WIDTH : positive);
port (
pattern_in_p : in std_logic_vector(BITPATTERN_WIDTH - 1 downto 0);
bitstream_out_p : out std_logic;
clk_bit : in std_logic;
clk : in std_logic);
end component serialiser;
end uss_tx_pkg;
|
bsd-3-clause
|
dergraaf/loa
|
fpga/modules/adc_ltc2351/hdl/adc_ltc2351_module.vhd
|
2
|
5114
|
-------------------------------------------------------------------------------
-- ADC LTC2351 module
--
-- Operates the LTC2351 in free running mode and connects it to
-- the internal parallel bus of the beacon board.
-- Provides a 'done' signal to the bus which can be used as an interrupt
-- source
--
-- Connects the adc_ltc2351 entity to the internal bus system.
--
-- @author strongly-typed
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.bus_pkg.all;
use work.reg_file_pkg.all;
use work.adc_ltc2351_pkg.all;
-------------------------------------------------------------------------------
entity adc_ltc2351_module is
generic (
BASE_ADDRESS : integer range 0 to 16#7FFF#
);
port (
-- signals to and from real hardware
adc_out_p : out adc_ltc2351_spi_out_type;
adc_in_p : in adc_ltc2351_spi_in_type;
-- signals to and from the internal parallel bus
bus_o : out busdevice_out_type;
bus_i : in busdevice_in_type;
-- interrupt for signalling that new samples are available
done_p : out std_logic;
-- direct access to the read adc samples
adc_values_o : out adc_ltc2351_values_type(5 downto 0);
clk : in std_logic
);
end adc_ltc2351_module;
-------------------------------------------------------------------------------
architecture behavioral of adc_ltc2351_module is
-- The ADC operates in free running mode
type adc_ltc2351_module_state_type is (
IDLE, -- a new result is available
CONVERTING -- a conversion is in progress
);
type adc_ltc2351_module_type is record
state : adc_ltc2351_module_state_type;
start : std_logic;
end record;
-----------------------------------------------------------------------------
-- Internal signal declarations
-----------------------------------------------------------------------------
signal r, rin : adc_ltc2351_module_type;
signal value_s : adc_ltc2351_values_type(5 downto 0); -- TODO use generic for channel number
signal done_s : std_logic := '0';
signal reg_o : reg_file_type(7 downto 0);
signal reg_i : reg_file_type(7 downto 0);
-----------------------------------------------------------------------------
-- Component declarations
-----------------------------------------------------------------------------
begin
----------------------------------------------------------------------------
-- mapping of signals to ADC interface
----------------------------------------------------------------------------
done_p <= done_s;
copy_reg : for ii in 0 to 5 generate
reg_i(ii) <= "00" & value_s(ii);
end generate copy_reg; -- ii
-----------------------------------------------------------------------------
-- Register file to present ADC values to bus
-----------------------------------------------------------------------------
reg_file_1 : reg_file
generic map (
BASE_ADDRESS => BASE_ADDRESS,
REG_ADDR_BIT => 3 -- 2**3 = 8 registers for 6 ADC values
)
port map (
bus_o => bus_o,
bus_i => bus_i,
reg_o => reg_o,
reg_i => reg_i,
clk => clk
);
-----------------------------------------------------------------------------
-- ADC interface module
-----------------------------------------------------------------------------
adc_ltc2351_1 : adc_ltc2351
port map (
-- connection between component's signals (left) and
-- modules's signals (right)
adc_out => adc_out_p,
adc_in => adc_in_p,
values_p => value_s,
start_p => r.start,
done_p => done_s,
clk => clk
);
-----------------------------------------------------------------------------
-- seq part of FSM
-----------------------------------------------------------------------------
seq_proc : process(clk)
begin
if rising_edge(clk) then
r <= rin;
end if;
end process seq_proc;
-----------------------------------------------------------------------------
-- transitions and actions of FSM
-----------------------------------------------------------------------------
comb_proc : process(done_s, r, value_s)
variable v : adc_ltc2351_module_type;
begin
v := r;
case v.state is
when IDLE =>
-- free running mode: always start a new conversion if done;
-- if (done_s = '1') then
v.start := '1';
v.state := CONVERTING;
-- end if;
when CONVERTING =>
-- conversion is in progress
v.start := '0';
if done_s = '1' then
v.state := IDLE;
end if;
end case;
rin <= v;
end process comb_proc;
end behavioral; -- adc_ltc2351_module
|
bsd-3-clause
|
dergraaf/loa
|
fpga/toplevel/spartan6_breakout_fsmc/tb/toplevel_tb.vhd
|
1
|
2899
|
-------------------------------------------------------------------------------
-- Title : Testbench for design "toplevel"
-- Project :
-------------------------------------------------------------------------------
-- File : toplevel_tb.vhd
-- Author : fabian <fabian@rechenknecht>
-- Company :
-- Created : 2013-03-24
-- Last update: 2013-03-25
-- Platform :
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2013
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2013-03-24 1.0 fabian Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
entity toplevel_tb is
end toplevel_tb;
-------------------------------------------------------------------------------
architecture testbench of toplevel_tb is
component toplevel
port (
data_p : in std_logic_vector(7 downto 0);
led_p : out std_logic_vector (5 downto 0);
fsmc_data_p : inout std_logic_vector(15 downto 0);
fsmc_adv_np : in std_logic;
fsmc_clk_p : in std_logic;
fsmc_oe_np : in std_logic;
fsmc_we_np : in std_logic;
fsmc_cs_np : in std_logic;
fsmc_bl_np : in std_logic_vector(1 downto 0);
fsmc_wait_np : out std_logic;
clk : in std_logic);
end component;
-- component ports
signal data : std_logic_vector(7 downto 0);
signal led : std_logic_vector (5 downto 0);
signal fsmc_data : std_logic_vector(15 downto 0);
signal fsmc_adv_n : std_logic;
signal fsmc_clk : std_logic;
signal fsmc_oe_n : std_logic;
signal fsmc_we_n : std_logic;
signal fsmc_cs_n : std_logic;
signal fsmc_bl_n : std_logic_vector(1 downto 0);
signal fsmc_wait_n : std_logic;
-- clock
signal clk : std_logic := '1';
begin -- testbench
-- component instantiation
DUT : toplevel
port map (
data_p => data,
led_p => led,
fsmc_data_p => fsmc_data,
fsmc_adv_np => fsmc_adv_n,
fsmc_clk_p => fsmc_clk,
fsmc_oe_np => fsmc_oe_n,
fsmc_we_np => fsmc_we_n,
fsmc_cs_np => fsmc_cs_n,
fsmc_bl_np => fsmc_bl_n,
fsmc_wait_np => fsmc_wait_n,
clk => clk);
-- clock generation
clk <= not clk after 10 ns;
-- waveform generation
wavegen : process
begin
wait until rising_edge(clk);
end process wavegen;
end testbench;
|
bsd-3-clause
|
dergraaf/loa
|
fpga/modules/utils/hdl/fractional_clock_divider.vhd
|
1
|
1633
|
-------------------------------------------------------------------------------
-- Title : Generic clock divider
-- Project : Loa
-------------------------------------------------------------------------------
-- Author : Fabian Greif <[email protected]>
-- Company : Roboterclub Aachen e.V.
-- Platform : Spartan 3
-------------------------------------------------------------------------------
-- Description:
-- Generates a clock enable signal.
--
-- MUL must be smaller than DIV.
--
-- Example:
-- @code
-- process (clk)
-- begin
-- if rising_edge(clk) then
-- if enable = '1' then
-- ... do something with the period of the divided frequency ...
-- end if;
-- end if;
-- end process;
-- @endcode
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity fractional_clock_divider is
generic (
DIV : positive;
MUL : positive := 1
);
port (
clk_out_p : out std_logic;
clk : in std_logic
);
end fractional_clock_divider;
-- ----------------------------------------------------------------------------
architecture behavior of fractional_clock_divider is
begin
process
variable cnt : integer range 0 to (MUL + DIV - 1) := 0;
begin
wait until rising_edge(clk);
cnt := cnt + MUL;
if cnt >= DIV then
cnt := cnt - DIV;
clk_out_p <= '1';
else
clk_out_p <= '0';
end if;
end process;
end behavior;
|
bsd-3-clause
|
dergraaf/loa
|
fpga/modules/signalprocessing/tb/goertzel_pipelined_sim_tb.vhd
|
2
|
11418
|
-------------------------------------------------------------------------------
-- Title : Simulation of Pipelined Goertzel Algorithm with Block RAM
-- Project :
-------------------------------------------------------------------------------
-- File : goertzel_pipelined_sim.vhd
-- Author : strongly-typed
-- Created : 2012-04-28
-- Platform :
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description: This is a testbench that tests the goertzel_pipelined_v2
-- entity with a block ram and artifical signal sources.
-- The read cycle from the STM is simulated, too. The data is read
-- from the block RAM and written to the goertzel.bin file for
-- further simulation with the unit test of signalprocessing.cpp.
-------------------------------------------------------------------------------
-- Copyright (c) 2012 strongly-typed
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library work;
use work.adc_ltc2351_pkg.all;
use work.reg_file_pkg.all;
use work.bus_pkg.all;
use work.signalprocessing_pkg.all;
use work.signal_sources_pkg.all;
entity goertzel_pipelined_sim_tb is
end goertzel_pipelined_sim_tb;
architecture tb of goertzel_pipelined_sim_tb is
-- signals
signal clk : std_logic := '0';
constant FREQUENCIES : natural := 2;
constant CHANNELS : natural := 12;
constant SAMPLES : natural := 500;
constant Q : natural := 13;
constant BASE_ADDRESS : natural := 16#0000#;
constant BASE_ADDRESS_TIMESTAMP : natural := 16#0100#;
signal data_to_bram : std_logic_vector(35 downto 0);
signal data_from_bram : std_logic_vector(35 downto 0);
signal addr_to_bram : std_logic_vector(7 downto 0);
signal we_to_bram : std_logic;
signal irq_s : std_logic;
signal ack_s : std_logic := '0';
signal bus_i_dummy : busdevice_in_type := (addr => (others => '0'),
data => (others => '0'),
re => '0',
we => '0');
signal bus_to_stm, bus_to_stm_from_bram, bus_to_stm_from_timestamp : busdevice_out_type := (data => (others => '0'));
signal start_s : std_logic := '0';
signal ready_s : std_logic; -- Goertzel result ready, switch RAM bank.
signal bank_x_s : std_logic := '0';
signal bank_y_s : std_logic := '0';
-- One coefficient for each frequency, one input for each channel.
signal coefs : goertzel_coefs_type(FREQUENCIES-1 downto 0) := (others => (others => '0'));
signal inputs : goertzel_inputs_type(CHANNELS-1 downto 0) := (others => (others => '0'));
-- Goertzel results as signals
signal gv0, gv1 : std_logic_vector(15 downto 0) := (others => '0'); -- value read from register
type g_array is array (0 to ((FREQUENCIES * CHANNELS) - 1)) of real;
signal g_results : g_array := (others => 0.0);
-- For each frequency the goertzel results from the corresponding channel.
-- These should be the larges value of all goertzel results.
type g2_array is array (0 to (FREQUENCIES-1)) of real;
signal g2_results : g2_array := (others => 0.0);
signal d1, d2, c : real := 0.0;
-- timestamping
signal timestamp_s : timestamp_type; -- The global timestamp
signal timestamp_stm_s : integer := 0; -- The timestamp read by the STM
-- Signal generation for testbench
-- Amplitude of signal for each channel
type amplitude_array is array (0 to (CHANNELS - 1)) of real;
constant AMPLITUDE : amplitude_array := (
2.0**7,
2.0**8,
2.0**7,
others => 0.0);
constant FSAMPLE : real := 100000.0; -- Sample frequency in Hertz.
-- The sampling frequency in the
-- simulation is higher to speed up the
-- simulation. This value is used for
-- calculation of coefficients only.
-- Signal frequency of each channel
type frequency_array is array (0 to (CHANNELS - 1)) of real;
constant FSIGNAL : frequency_array := (
23625.0,
24375.0,
16425.0,
others => 0.0);
-- Output file
type IntegerFileType is file of integer;
begin -- tb
-- Clock generation: 50 MHz
clk <= not clk after 10 ns;
-- Connect the busses
bus_to_stm.data <= bus_to_stm_from_timestamp.data or bus_to_stm_from_bram.data;
-- The Block RAM
reg_file_bram_double_buffered_1 : reg_file_bram_double_buffered
generic map (
BASE_ADDRESS => BASE_ADDRESS)
port map (
bus_o => bus_to_stm_from_bram,
bus_i => bus_i_dummy,
bram_data_i => data_to_bram,
bram_data_o => data_from_bram,
bram_addr_i => addr_to_bram,
bram_we_p => we_to_bram,
irq_o => irq_s,
ack_i => ack_s,
ready_i => ready_s,
enable_o => open,
bank_x_o => bank_x_s,
bank_y_o => bank_y_s,
clk => clk);
-- The Pipeline
goertzel_pipelined_v2_1 : goertzel_pipelined_v2
generic map (
FREQUENCIES => FREQUENCIES,
CHANNELS => CHANNELS,
SAMPLES => SAMPLES,
Q => Q)
port map (
start_p => start_s,
bram_addr_p => addr_to_bram,
bram_data_i => data_from_bram,
bram_data_o => data_to_bram,
bram_we_p => we_to_bram,
ready_p => ready_s,
enable_p => '0',
coefs_p => coefs,
inputs_p => inputs,
clk => clk);
-- Take a timestamp whenever the goertzel pipeline finished a set of values
-- and switches the bnak.
timestamp_taker_1 : timestamp_taker
generic map (
BASE_ADDRESS => BASE_ADDRESS_TIMESTAMP)
port map (
timestamp_i_p => timestamp_s,
trigger_i_p => ready_s,
bank_x_i_p => bank_x_s,
bank_y_i_p => bank_y_s,
bus_o => bus_to_stm_from_timestamp,
bus_i => bus_i_dummy,
clk => clk);
-- generate a timestamp
timestamp_generator_1 : timestamp_generator
port map (
timestamp_o_p => timestamp_s,
clk => clk);
-- Simulate a signal source for each channel.
sources : for channel in 0 to (CHANNELS-1) generate
s_sine : entity work.source_sine
generic map (
DATA_WIDTH => INPUT_WIDTH,
AMPLITUDE => AMPLITUDE(channel),
SIGNAL_FREQUENCY => FSIGNAL(channel),
SAMPLING_FREQUENCY => FSAMPLE)
port map (
start_i => start_s,
signal_o => inputs(channel));
end generate sources;
-- Simulate the ADCs that deliver new samples for each channel.
adcs : process
begin -- process adcs
-- set goertzel coefficients, one for each frequency
for frequency in 0 to (FREQUENCIES-1) loop
coefs(frequency) <= to_signed(
integer(2.0 * cos(MATH_2_PI * FSIGNAL(frequency) / FSAMPLE) * 2.0**Q),
coefs(frequency)'length);
end loop; -- frequency
wait until clk = '0';
wait until clk = '0';
wait until clk = '0';
-- Start a new conversion every x clock ticks
-- This is more often than in real hardware.
-- It does not make sense to wait thousands of clock cycles until a new
-- ADC result is ready.
for ii in 0 to 20000 loop
start_s <= '1';
wait until clk = '0';
start_s <= '0';
-- The minimum time to process all channels and all frequencies must
-- be met.
for pp in 0 to (4 * (CHANNELS * FREQUENCIES + 1)) loop
wait until clk = '0';
end loop; -- pp
end loop; -- ii
-- do not repeat
wait;
end process adcs;
-- Always acknowledge new data from the Goertzel Algorithm
-- and calculate the magnitude of the goertzel values in floating point.
-- This simulates what will be done in the STM32 processor.
AckGen : process
variable d1_v, d2_v, c_v : real := 0.0;
variable gv0_v, gv1_v : std_logic_vector(15 downto 0) := (others => '0');
variable ii : integer := 0;
variable timestamp_v : integer;
file data_out : IntegerFileType open write_mode is "goertzel.bin";
begin -- process AckGen
wait until irq_s = '1';
-- STM delay
wait for 100 us;
ii := 0; -- iterate over all frequencies and
-- channels. The memory layout is
-- linear.
for fr in 0 to FREQUENCIES-1 loop
for ch in 0 to CHANNELS-1 loop
-- read data from bus and display result as a signal
-- This will happen in the STM
readWord(addr => BASE_ADDRESS + 0 + (ii * 2), bus_i => bus_i_dummy, clk => clk);
gv0_v := bus_to_stm.data;
readWord(addr => BASE_ADDRESS + 1 + (ii * 2), bus_i => bus_i_dummy, clk => clk);
gv1_v := bus_to_stm.data;
-- Write the raw bits read from block RAM to a file.
-- This can be used to check the C++ code.
-- Interpret data with
-- $ hexdump -v -e '2/4 "%08x "' -e ' 2/4 " %6d" "\n"' goertzel.bin
write(data_out, to_integer(signed(gv0_v)));
write(data_out, to_integer(signed(gv1_v)));
-- convert to real
d1_v := real(to_integer(signed(gv0_v))) / 2.0**(Q-2);
d2_v := real(to_integer(signed(gv1_v))) / 2.0**(Q-2);
c_v := real(to_integer(coefs(fr))) / 2.0**Q;
g_results(ii) <= d1_v**2 + d2_v**2 - (d1_v * d2_v * c_v);
-- Assign variables to signals so the data can be plotted in
-- gtkwave. Variables cannot be plotted.
d1 <= d1_v;
d2 <= d2_v;
c <= c_v;
gv0 <= gv0_v;
gv1 <= gv1_v;
-- wait at least one clock cycle
wait until rising_edge(clk);
ii := ii + 1;
end loop; -- ch
end loop; -- fr
-- Read timestamp
timestamp_v := 0;
for ii in 0 to 2 loop
readWord(addr => BASE_ADDRESS_TIMESTAMP + ii, bus_i => bus_i_dummy, clk => clk);
timestamp_v := timestamp_v + to_integer(unsigned(bus_to_stm.data)) * 2**(16 * ii);
end loop; -- ii
timestamp_stm_s <= timestamp_v;
-- acknowledge that all results were read
ack_s <= '1';
wait for 100 ns;
ack_s <= '0';
end process AckGen;
-- purpose: Copy all goertzel values for each channel with the matching frequency
-- type : combinational
-- inputs : g_results
-- outputs: g2_results
copyVals : process (g_results)
begin -- process copyVals
for fr in 0 to (FREQUENCIES-1) loop
g2_results(fr) <= g_results((fr * CHANNELS) + fr);
end loop; -- ch
end process copyVals;
end tb;
|
bsd-3-clause
|
dergraaf/loa
|
fpga/modules/encoder/hdl/encoder_module.vhd
|
2
|
3216
|
-------------------------------------------------------------------------------
-- Title : Encoder Module
-- Project : Loa
-------------------------------------------------------------------------------
-- Platform : Spartan 3
-------------------------------------------------------------------------------
-- Description: Connectes a quadrature decoder with a 16-bit counter to
-- the internal bus system.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.bus_pkg.all;
use work.encoder_module_pkg.all;
use work.quadrature_decoder_pkg.all;
use work.up_down_counter_pkg.all;
-------------------------------------------------------------------------------
entity encoder_module is
generic (
BASE_ADDRESS : integer range 0 to 16#7FFF#
);
port (
encoder_p : in encoder_type;
index_p : in std_logic; -- index can be used to reset the
-- counter, set to '0' if not used
load_p : in std_logic; -- Save the current encoder value in a
-- buffer register
bus_o : out busdevice_out_type;
bus_i : in busdevice_in_type;
clk : in std_logic
);
end encoder_module;
-------------------------------------------------------------------------------
architecture behavioral of encoder_module is
type encoder_module_type is record
counter : std_logic_vector(15 downto 0);
data_out : std_logic_vector(15 downto 0);
end record;
signal r, rin : encoder_module_type := (data_out => (others => '0'),
counter => (others => '0'));
signal step : std_logic := '0';
signal up_down : std_logic := '0'; -- Direction for the counter ('1' = up, '0' = down)
signal decode_error : std_logic; -- Decoding Error (A and B lines changes at the same time), currently not used
signal counter : std_logic_vector(15 downto 0);
begin
seq_proc : process(clk)
begin
if rising_edge(clk) then
r <= rin;
end if;
end process seq_proc;
comb_proc : process(bus_i, counter, load_p, r)
variable v : encoder_module_type;
begin
v := r;
v.data_out := (others => '0');
-- Load counter into own buffer
if load_p = '1' then
v.counter := counter;
end if;
-- Check Bus Address
if bus_i.addr = std_logic_vector(to_unsigned(BASE_ADDRESS, 15)) then
if bus_i.we = '1' then
-- TODO
elsif bus_i.re = '1' then
v.data_out := r.counter;
end if;
end if;
rin <= v;
end process comb_proc;
bus_o.data <= r.data_out;
decoder : quadrature_decoder
port map (
encoder_p => encoder_p,
step_p => step,
dir_p => up_down,
error_p => decode_error,
clk => clk);
up_down_counter_1 : up_down_counter
generic map (
WIDTH => 16)
port map (
clk_en_p => step,
up_down_p => up_down,
value_p => counter,
reset => '0',
clk => clk);
end behavioral;
|
bsd-3-clause
|
dergraaf/loa
|
fpga/modules/motor_control/hdl/driver_stages.vhd
|
2
|
4009
|
-------------------------------------------------------------------------------
-- Title : Driver Stage Converters
-- Project :
-------------------------------------------------------------------------------
-- Author : strongly-typed
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Convert the interface for DC and BLDC motors to driver stages
-- with halfbridges from ST.
-------------------------------------------------------------------------------
-- Copyright (c) 2013 strongly-typed
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.motor_control_pkg.all;
entity bldc_driver_stage_converter is
port (
bldc_driver_stage : in bldc_driver_stage_type;
bldc_driver_stage_st : out bldc_driver_stage_st_type
);
end bldc_driver_stage_converter;
architecture structural of bldc_driver_stage_converter is
signal shoot_through_a : std_logic := '0'; -- The bridge is requested to do
-- a shoot through. This should never happen.
signal shoot_through_b : std_logic := '0';
signal shoot_through_c : std_logic := '0';
signal shoot_through : std_logic;
begin
shoot_through_a <= '1' when ((bldc_driver_stage.a.high = '1') and (bldc_driver_stage.a.low = '1')) else '0';
shoot_through_b <= '1' when ((bldc_driver_stage.b.high = '1') and (bldc_driver_stage.b.low = '1')) else '0';
shoot_through_c <= '1' when ((bldc_driver_stage.c.high = '1') and (bldc_driver_stage.c.low = '1')) else '0';
shoot_through <= shoot_through_a or shoot_through_b or shoot_through_c;
bldc_driver_stage_st.a.high <= '1' when ((bldc_driver_stage.a.high = '1') and (shoot_through = '0')) else '0';
bldc_driver_stage_st.a.low_n <= '0' when ((bldc_driver_stage.a.low = '1') and (shoot_through = '0')) else '1';
bldc_driver_stage_st.b.high <= '1' when ((bldc_driver_stage.b.high = '1') and (shoot_through = '0')) else '0';
bldc_driver_stage_st.b.low_n <= '0' when ((bldc_driver_stage.b.low = '1') and (shoot_through = '0')) else '1';
bldc_driver_stage_st.c.high <= '1' when ((bldc_driver_stage.c.high = '1') and (shoot_through = '0')) else '0';
bldc_driver_stage_st.c.low_n <= '0' when ((bldc_driver_stage.c.low = '1') and (shoot_through = '0')) else '1';
end structural;
---------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.motor_control_pkg.all;
-- Convert from PWM1/2 + shutdown interface to ST halfbridge
entity dc_driver_stage_converter is
port (
pwm1_in_p : in std_logic;
pwm2_in_p : in std_logic;
sd_in_p : in std_logic;
dc_driver_stage_st_out_p : out dc_driver_stage_st_type
);
end dc_driver_stage_converter;
architecture structural of dc_driver_stage_converter is
begin
process (pwm1_in_p, pwm2_in_p, sd_in_p)
begin
if sd_in_p = '1' then
-- disable both
dc_driver_stage_st_out_p.a.high <= '0';
dc_driver_stage_st_out_p.a.low_n <= '1';
dc_driver_stage_st_out_p.b.high <= '0';
dc_driver_stage_st_out_p.b.low_n <= '1';
else
if pwm1_in_p = '0' then
dc_driver_stage_st_out_p.a.high <= '0';
dc_driver_stage_st_out_p.a.low_n <= '0';
else
dc_driver_stage_st_out_p.a.high <= '1';
dc_driver_stage_st_out_p.a.low_n <= '1';
end if;
if pwm2_in_p = '0' then
dc_driver_stage_st_out_p.b.high <= '0';
dc_driver_stage_st_out_p.b.low_n <= '0';
else
dc_driver_stage_st_out_p.b.high <= '1';
dc_driver_stage_st_out_p.b.low_n <= '1';
end if;
end if;
end process;
end structural;
|
bsd-3-clause
|
dergraaf/loa
|
fpga/toplevel/beacon_robot/toplevel.vhd
|
1
|
10733
|
-------------------------------------------------------------------------------
-- Title : Mobile Beacon
-------------------------------------------------------------------------------
-- File : toplevel.vhd
-- Authors : Fabian Greif <[email protected]>, strongly-typed
-- Company : Roboterclub Aachen e.V.
-- Created : 2012-03-31
-- Platform : Spartan 3A-200
-------------------------------------------------------------------------------
-- Description:
-- ...
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.bus_pkg.all;
use work.spislave_pkg.all;
use work.reg_file_pkg.all;
use work.motor_control_pkg.all;
use work.adc_ltc2351_pkg.all;
use work.uss_tx_pkg.all;
use work.ir_tx_pkg.all;
use work.utils_pkg.all;
use work.ir_rx_module_pkg.all;
use work.signalprocessing_pkg.all;
-- Read the addresses from a file
use work.memory_map_pkg.all;
-------------------------------------------------------------------------------
entity toplevel is
port (
-- Connections to the STM32F407
-- SPI
cs_np : in std_logic;
sck_p : in std_logic;
miso_p : out std_logic;
mosi_p : in std_logic;
-- hardwired
ir_irq_p : out std_logic;
us_irq_p : out std_logic;
ir_ack_p : in std_logic;
us_ack_p : in std_logic;
-- 4 MBit SRAM CY7C1049DV33-10ZSXI (428-1982-ND)
sram_addr_p : out std_logic_vector(18 downto 0);
sram_data_p : inout std_logic_vector(7 downto 0);
sram_oe_np : out std_logic;
sram_we_np : out std_logic;
sram_ce_np : out std_logic;
-- US TX
us_tx0_p : out half_bridge_type;
us_tx1_p : out half_bridge_type;
us_tx2_p : out half_bridge_type;
-- US RX: one LTC2351 ADC
us_rx_spi_in_p : in adc_ltc2351_spi_in_type;
us_rx_spi_out_p : out adc_ltc2351_spi_out_type;
-- IR TX
ir_tx_p : out std_logic;
-- IR RX: two LTC2351 ADC
ir_rx_spi_out_p : out adc_ltc2351_spi_out_type;
ir_rx0_spi_in_p : in adc_ltc2351_spi_in_type;
ir_rx1_spi_in_p : in adc_ltc2351_spi_in_type;
-- Devel
dev_o_p : out std_logic;
-- 50 MHz clock input
clk : in std_logic
);
end toplevel;
architecture structural of toplevel is
-- Peripheral Register at 0x000, required for FPGA configuration check.
signal register_out : std_logic_vector(15 downto 0);
signal register_in : std_logic_vector(15 downto 0);
-- Modulation
signal modulation_cnt : natural := 0;
signal modulation_us : std_logic_vector(2 downto 0) := (others => '0');
signal clk_modulation_us_s : std_logic := '0';
-- Synchronise inputs
signal ir_ack_r : std_logic_vector(1 downto 0) := (others => '0');
signal ir_ack : std_logic;
signal us_ack_r : std_logic_vector(1 downto 0) := (others => '0');
signal us_ack : std_logic;
-- Connection to the Busmaster
signal bus_spi_out : busmaster_out_type;
signal bus_spi_in : busmaster_in_type;
-- Outputs form the Bus devices
signal bus_register_out : busdevice_out_type;
signal bus_adc_us_out : busdevice_out_type;
signal bus_ir_tx_out : busdevice_out_type;
signal bus_ir_rx_out : busdevice_out_type;
signal bus_ir_rx_adc_values_out : busdevice_out_type;
-- Common clock enable for ADCs
signal clk_adc_en_s : std_logic;
-- Connections to and from the IR ADCs
signal ir_rx_module_spi_out : ir_rx_module_spi_out_type;
signal ir_rx_module_spi_in : ir_rx_module_spi_in_type;
signal adc_values_ltc_s : adc_ltc2351_values_type(11 downto 0);
signal adc_values_reg_s : reg_file_type(15 downto 0);
-- Timestamp
signal timestamp_s : timestamp_type := (others => '0');
begin
----------------------------------------------------------------------------
bus_spi_in.data <= bus_register_out.data or
bus_ir_rx_out.data or
bus_adc_us_out.data or
bus_ir_rx_adc_values_out.data or
bus_ir_tx_out.data;
----------------------------------------------------------------------------
-- TODO generic CHANNELS
copy_values : for ii in 0 to 11 generate
adc_values_reg_s(ii) <= "00" & adc_values_ltc_s(ii);
end generate copy_values;
----------------------------------------------------------------------------
-- SPI connection to the STM32F4xx and Busmaster
-- for the internal bus
spi : spi_slave
port map (
miso_p => miso_p,
mosi_p => mosi_p,
sck_p => sck_p,
csn_p => cs_np,
bus_o => bus_spi_out,
bus_i => bus_spi_in,
clk => clk);
----------------------------------------------------------------------------
-- 4 MBit SRAM CY7C1049DV33-10ZSXI (428-1982-ND)
sram_data_p <= (others => 'Z');
sram_addr_p <= (others => 'Z');
sram_ce_np <= 'Z';
sram_we_np <= 'Z';
sram_oe_np <= 'Z';
----------------------------------------------------------------------------
-- Register
-- some test data to test FPGA STM communication.
-- Required for testing the SPI link.
preg : peripheral_register
generic map (
BASE_ADDRESS => BASE_ADDR_REG)
port map (
dout_p => register_out,
din_p => register_in,
bus_o => bus_register_out,
bus_i => bus_spi_out,
clk => clk);
register_in <= x"abc" & "0000";
----------------------------------------------------------------------------
-- Modulation
----------------------------------------------------------------------------
clock_divider_mod : clock_divider
generic map (
DIV => 5000) -- 10 kHz <> 100 usec
port map (
clk_out_p => clk_modulation_us_s,
clk => clk);
us_modulation_proc : process (clk)
variable cnt : natural range 0 to 100 := 0;
begin -- process us_modulation_proc
if rising_edge(clk) then
if clk_modulation_us_s = '1' then
if cnt = 100 then
cnt := 0;
else
cnt := cnt + 1;
end if;
end if;
end if;
modulation_cnt <= cnt;
end process us_modulation_proc;
modulation_us <= "111" when (modulation_cnt < 3) else "000";
----------------------------------------------------------------------------
-- US TX
----------------------------------------------------------------------------
uss_tx_module_1 : uss_tx_module
generic map (
BASE_ADDRESS => BASE_ADDR_US_TX)
port map (
uss_tx0_out_p => us_tx0_p,
uss_tx1_out_p => us_tx1_p,
uss_tx2_out_p => us_tx2_p,
clk_uss_enable_p => open,
bus_o => bus_adc_us_out,
bus_i => bus_spi_out,
clk => clk);
----------------------------------------------------------------------------
-- IR TX
ir_tx_module_1 : ir_tx_module
generic map (
BASE_ADDRESS => BASE_ADDR_IR_TX)
port map (
ir_tx_p => ir_tx_p,
modulation_p => '1', -- modulation_p,
clk_ir_enable_p => open,
bus_o => bus_ir_tx_out,
bus_i => bus_spi_out,
clk => clk);
------------------------------------------------------------------------------
-- direct access to the ADC values
reg_file_adc_values : reg_file
generic map (
BASE_ADDRESS => BASE_ADDR_IR_RX_ADC,
REG_ADDR_BIT => 4) -- 2**4 = 16 values
port map (
bus_o => bus_ir_rx_adc_values_out,
bus_i => bus_spi_out,
reg_o => open,
reg_i => adc_values_reg_s,
clk => clk);
------------------------------------------------------------------------------
----------------------------------------------------------------------------
-- Common sample Clock for US RX and IR RX
-- 50 MHz / 200 = 250 kHz
-- 50 MHz / 500 = 100 kHz
-- 50 MHz / 667 = 75 kHz
----------------------------------------------------------------------------
clock_divider_adc : clock_divider
generic map (
DIV => 500)
port map (
clk_out_p => clk_adc_en_s,
clk => clk);
------------------------------------------------------------------------------
---- US RX ADC readout
------------------------------------------------------------------------------
us_rx_spi_out_p.sck <= 'Z';
us_rx_spi_out_p.conv <= 'Z';
us_irq_p <= 'Z';
-- SPI of both ADCs has common CONV and SCK
ir_rx_spi_out_p <= ir_rx_module_spi_out(0);
ir_rx_module_spi_in(0) <= ir_rx0_spi_in_p;
ir_rx_module_spi_in(1) <= ir_rx1_spi_in_p;
ir_rx_module_0 : ir_rx_module
generic map (
BASE_ADDRESS_COEFS => BASE_ADDR_IR_RX_COEFS,
BASE_ADDRESS_RESULTS => BASE_ADDR_IR_RX_RESULTS,
BASE_ADDRESS_TIMESTAMP => BASE_ADDR_IR_RX_TIMESTAMP)
port map (
adc_o_p => ir_rx_module_spi_out,
adc_i_p => ir_rx_module_spi_in,
adc_values_o_p => adc_values_ltc_s,
sync_o_p => open,
bus_o_p => bus_ir_rx_out,
bus_i_p => bus_spi_out,
done_o_p => ir_irq_p,
ack_i_p => ir_ack,
clk_sample_en_i_p => clk_adc_en_s,
timestamp_i_p => timestamp_s,
clk => clk);
----------------------------------------------------------------------------
-- Modulation
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- Timestamp
----------------------------------------------------------------------------
timestamp_generator_1 : timestamp_generator
port map (
timestamp_o_p => timestamp_s,
clk => clk);
----------------------------------------------------------------------------
-- synchronize acknowledge signals
----------------------------------------------------------------------------
synchronisation_proc : process (clk)
begin
if rising_edge(clk) then
ir_ack_r <= ir_ack_r(0) & ir_ack_p;
us_ack_r <= us_ack_r(0) & us_ack_p;
end if;
end process synchronisation_proc;
ir_ack <= ir_ack_r(1);
us_ack <= us_ack_r(1);
-- Development
dev_o_p <= us_ack_p;
end structural;
|
bsd-3-clause
|
dergraaf/loa
|
fpga/modules/encoder/tb/hall_sensor_decoder_tb.vhd
|
2
|
4424
|
-------------------------------------------------------------------------------
-- Title : Testbench for design "hall_sensor_decoder"
-------------------------------------------------------------------------------
-- Author : strongly-typed
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2013
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.hall_sensor_decoder_pkg.all;
use work.motor_control_pkg.all;
-------------------------------------------------------------------------------
entity hall_sensor_decoder_tb is
end hall_sensor_decoder_tb;
-------------------------------------------------------------------------------
architecture tb of hall_sensor_decoder_tb is
type input_type is record
a : std_logic;
b : std_logic;
c : std_logic;
end record;
type expect_type is record
step : std_logic;
dir : std_logic;
error : std_logic;
end record;
type stimulus_type is record
input : input_type;
expect : expect_type;
end record;
type stimuli_type is array (natural range <>) of stimulus_type;
constant stimuli : stimuli_type := (
-- A B C step dir error
(input => ('0', '0', '1'), expect => ('0', '-', '0')),
(input => ('1', '0', '1'), expect => ('1', '-', '0')),
(input => ('1', '0', '0'), expect => ('1', '1', '0')),
(input => ('1', '0', '0'), expect => ('0', '-', '0')),
(input => ('1', '1', '0'), expect => ('1', '1', '0')),
(input => ('0', '1', '0'), expect => ('1', '1', '0')),
(input => ('0', '1', '1'), expect => ('1', '1', '0')),
(input => ('0', '0', '1'), expect => ('1', '1', '0')),
(input => ('1', '0', '1'), expect => ('1', '1', '0')),
(input => ('1', '0', '1'), expect => ('0', '-', '0')),
(input => ('0', '0', '1'), expect => ('1', '0', '0')),
(input => ('0', '1', '1'), expect => ('1', '0', '0')),
(input => ('0', '1', '0'), expect => ('1', '0', '0')),
(input => ('1', '1', '0'), expect => ('1', '0', '0')),
(input => ('1', '1', '0'), expect => ('0', '-', '0')),
(input => ('0', '1', '0'), expect => ('1', '1', '0')),
(input => ('1', '1', '0'), expect => ('1', '0', '0')),
(input => ('0', '1', '0'), expect => ('1', '1', '0')),
(input => ('0', '1', '1'), expect => ('1', '1', '0')),
(input => ('0', '0', '1'), expect => ('1', '1', '0')),
(input => ('1', '0', '1'), expect => ('1', '1', '0')),
(input => ('1', '1', '1'), expect => ('0', '-', '1')),
(input => ('0', '1', '1'), expect => ('0', '-', '0')),
(input => ('0', '1', '0'), expect => ('1', '0', '0')),
(input => ('1', '1', '0'), expect => ('1', '0', '0')),
(input => ('0', '0', '0'), expect => ('0', '-', '1')),
(input => ('1', '0', '1'), expect => ('0', '0', '0'))
);
-- component ports
signal abc : hall_sensor_type := (a => '0', b => '0', c => '0');
signal step : std_logic;
signal dir : std_logic;
signal error : std_logic;
-- clock
signal clk : std_logic := '1';
begin
-- component instantiation
DUT : hall_sensor_decoder
port map (
hall_sensor_p => abc,
step_p => step,
dir_p => dir,
error_p => error,
clk => clk);
-- clock generation
clk <= not clk after 10 ns;
-- waveform generation
wave : process
begin
wait for 20 ns;
for i in stimuli'left to (stimuli'right + 2) loop
wait until rising_edge(clk);
if i <= stimuli'right then
abc.a <= stimuli(i).input.a;
abc.b <= stimuli(i).input.b;
abc.c <= stimuli(i).input.c;
else
abc.a <= '0';
abc.b <= '0';
abc.c <= '1';
end if;
if i > (stimuli'left + 2) then
-- values are active at the output after two clock cycles
assert (step = stimuli(i-2).expect.step) report "Wrong value for 'step'" severity note;
if not (stimuli(i-2).expect.dir = '-') then
assert (dir = stimuli(i-2).expect.dir) report "Wrong value for 'dir'" severity note;
end if;
assert (error = stimuli(i-2).expect.error) report "Wrong value for 'error'" severity note;
end if;
end loop; -- i
end process wave;
end tb;
|
bsd-3-clause
|
dergraaf/loa
|
fpga/modules/encoder/hdl/encoder_hall_sensor_module.vhd
|
2
|
3209
|
-------------------------------------------------------------------------------
-- Title : Hall Sensor Encoder Module
-- Project : Loa
-------------------------------------------------------------------------------
-- Platform : Spartan 3
-------------------------------------------------------------------------------
-- Description: Connectes a hall sensor encoder with a 16-bit counter to
-- the internal bus system.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.bus_pkg.all;
use work.encoder_module_pkg.all;
use work.motor_control_pkg.all;
use work.hall_sensor_decoder_pkg.all;
use work.up_down_counter_pkg.all;
-------------------------------------------------------------------------------
entity encoder_hall_sensor_module is
generic (
BASE_ADDRESS : integer range 0 to 16#7FFF#
);
port (
hall_sensor_p : in hall_sensor_type;
-- counter, set to '0' if not used
load_p : in std_logic; -- Save the current encoder value in a
-- buffer register
bus_o : out busdevice_out_type;
bus_i : in busdevice_in_type;
clk : in std_logic
);
end encoder_hall_sensor_module;
-------------------------------------------------------------------------------
architecture behavioral of encoder_hall_sensor_module is
type encoder_hall_sensor_module_type is record
counter : std_logic_vector(15 downto 0);
data_out : std_logic_vector(15 downto 0);
end record;
signal r, rin : encoder_hall_sensor_module_type :=
(data_out => (others => '0'),
counter => (others => '0'));
signal step : std_logic := '0';
signal up_down : std_logic := '0'; -- Direction for the counter ('1' = up, '0' = down)
signal decode_error : std_logic; -- Decoding Error, currently not used
signal counter : std_logic_vector(15 downto 0);
begin
seq_proc : process(clk)
begin
if rising_edge(clk) then
r <= rin;
end if;
end process seq_proc;
comb_proc : process(bus_i, counter, load_p, r)
variable v : encoder_hall_sensor_module_type;
begin
v := r;
v.data_out := (others => '0');
-- Load counter into own buffer
if load_p = '1' then
v.counter := counter;
end if;
-- Check Bus Address
if bus_i.addr = std_logic_vector(to_unsigned(BASE_ADDRESS, 15)) then
if bus_i.we = '1' then
-- TODO
elsif bus_i.re = '1' then
v.data_out := r.counter;
end if;
end if;
rin <= v;
end process comb_proc;
bus_o.data <= r.data_out;
decoder : hall_sensor_decoder
port map (
hall_sensor_p => hall_sensor_p,
step_p => step,
dir_p => up_down,
error_p => decode_error,
clk => clk);
up_down_counter_1 : up_down_counter
generic map (
WIDTH => 16)
port map (
clk_en_p => step,
up_down_p => up_down,
value_p => counter,
reset => '0',
clk => clk);
end behavioral;
|
bsd-3-clause
|
dergraaf/loa
|
fpga/modules/uart/tb/uart_rx_disable_tb.vhd
|
2
|
2559
|
-------------------------------------------------------------------------------
-- Title : Testbench for design "uart_rx"
-------------------------------------------------------------------------------
-- Author : Fabian Greif
-- Standard : VHDL'x
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2013
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.uart_pkg.all;
use work.uart_tb_pkg.all;
-------------------------------------------------------------------------------
entity uart_rx_disable_tb is
end entity uart_rx_disable_tb;
-------------------------------------------------------------------------------
architecture behavourial of uart_rx_disable_tb is
-- component ports
signal rxd : std_logic := '1';
signal disable : std_logic := '0';
signal data : std_logic_vector(7 downto 0);
signal we : std_logic;
signal rx_error : std_logic;
signal full : std_logic := '1';
signal clk_rx_en : std_logic := '0';
signal clk : std_logic := '0';
begin
-- component instantiation
dut : entity work.uart_rx
port map (
rxd_p => rxd,
disable_p => disable,
data_p => data,
we_p => we,
error_p => rx_error,
full_p => full,
clk_rx_en => clk_rx_en,
clk => clk);
-- clock generation
clk <= not clk after 10 ns;
-- Generate a bit clock
bitclock : process
begin
clk_rx_en <= '1';
wait until rising_edge(clk);
-- clk_rx_en <= '1';
-- wait until rising_edge(clk);
-- clk_rx_en <= '0';
-- wait for 40 ns;
end process bitclock;
-- waveform generation
waveform : process
begin
wait until rising_edge(clk);
uart_transmit(rxd, "001111100", 10000000);
wait for 200 ns;
uart_transmit(rxd, "001111100", 10000000);
wait for 200 ns;
uart_transmit(rxd, "001111100", 10000000);
wait for 200 ns;
wait;
end process waveform;
gen_disable : process
begin
wait until rising_edge(clk);
wait for 50 ns;
disable <= '1';
wait for 20 ns;
disable <= '0';
wait for 3 us;
disable <= '1';
wait for 200 ns;
disable <= '0';
wait;
end process;
end architecture behavourial;
|
bsd-3-clause
|
dergraaf/loa
|
fpga/modules/hdlc/hdl/hdlc_crc_pkg.vhd
|
2
|
3099
|
-------------------------------------------------------------------------------
-- Title : HDLC async Encoder & Decoder
-------------------------------------------------------------------------------
-- Author : Carl Treudler ([email protected])
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-- CRC-8 for HDLC, x^8 + x^2 + x^1 + 1
-------------------------------------------------------------------------------
-- Package:
-- Copyright (c) 2013, Carl Treudler
-- All Rights Reserved.
--
-- The file is part for the Loa project and is released under the
-- 3-clause BSD license. See the file `LICENSE` for the full license
-- governing this code.
-------------------------------------------------------------------------------
-- CRC function:
-- Copyright (C) 1999-2008 Easics NV. (see disclaimer over function)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package hdlc_crc_pkg is
function calc_crc_8210(Data : std_logic_vector(7 downto 0);
crc : std_logic_vector(7 downto 0)) return std_logic_vector;
end package hdlc_crc_pkg;
package body hdlc_crc_pkg is
--------------------------------------------------------------------------------
-- Copyright (C) 1999-2008 Easics NV.
-- This source file may be used and distributed without restriction
-- provided that this copyright statement is not removed from the file
-- and that any derivative work contains the original copyright notice
-- and the associated disclaimer.
--
-- THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS
-- OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
-- WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
--
-- Info : [email protected] / http://www.easics.com
--------------------------------------------------------------------------------
-- polynomial: (0 1 2 8)
-- data width: 8
-- convention: the first serial bit is D[7]
function calc_crc_8210(Data : std_logic_vector(7 downto 0);
crc : std_logic_vector(7 downto 0)) return std_logic_vector is
variable d : std_logic_vector(7 downto 0);
variable c : std_logic_vector(7 downto 0);
variable newcrc : std_logic_vector(7 downto 0);
begin
d := Data;
c := crc;
newcrc(0) := d(7) xor d(6) xor d(0) xor c(0) xor c(6) xor c(7);
newcrc(1) := d(6) xor d(1) xor d(0) xor c(0) xor c(1) xor c(6);
newcrc(2) := d(6) xor d(2) xor d(1) xor d(0) xor c(0) xor c(1) xor c(2) xor c(6);
newcrc(3) := d(7) xor d(3) xor d(2) xor d(1) xor c(1) xor c(2) xor c(3) xor c(7);
newcrc(4) := d(4) xor d(3) xor d(2) xor c(2) xor c(3) xor c(4);
newcrc(5) := d(5) xor d(4) xor d(3) xor c(3) xor c(4) xor c(5);
newcrc(6) := d(6) xor d(5) xor d(4) xor c(4) xor c(5) xor c(6);
newcrc(7) := d(7) xor d(6) xor d(5) xor c(5) xor c(6) xor c(7);
return newcrc;
end calc_crc_8210;
end hdlc_crc_pkg;
|
bsd-3-clause
|
dergraaf/loa
|
fpga/modules/peripheral_register/tb/reg_file_tb.vhd
|
2
|
3324
|
-------------------------------------------------------------------------------
-- Title : Testbench for design "reg_file"
-------------------------------------------------------------------------------
-- Author : Calle <calle@Alukiste>
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2012
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.bus_pkg.all;
use work.reg_file_pkg.all;
-------------------------------------------------------------------------------
entity reg_file_tb is
end reg_file_tb;
-------------------------------------------------------------------------------
architecture tb of reg_file_tb is
-- component generics
constant BASE_ADDRESS : integer range 0 to 16#7FFF# := 16#0010#;
constant REG_ADDR_BIT : natural := 1;
-- component ports
signal bus_o : busdevice_out_type;
signal bus_i : busdevice_in_type := (addr => (others => '0'),
data => (others => '0'),
we => '0',
re => '0');
signal reg_o : reg_file_type(2**REG_ADDR_BIT-1 downto 0);
signal reg_i : reg_file_type(2**REG_ADDR_BIT-1 downto 0);
-- clock
signal clk : std_logic := '1';
type comment_type is (idle, write, read);
signal comment : comment_type := idle;
begin -- tb
-- component instantiation
DUT : reg_file
generic map (
BASE_ADDRESS => BASE_ADDRESS,
REG_ADDR_BIT => REG_ADDR_BIT)
port map (
bus_o => bus_o,
bus_i => bus_i,
reg_o => reg_o,
reg_i => reg_i,
clk => clk);
-- clock generation
clk <= not clk after 10 ns;
-- waveform generation
WaveGen_Proc : process
begin
-- Reset
reg_i <= (others => (others => '0'));
reg_i(0)(3 downto 0) <= "0001";
reg_i(1)(3 downto 0) <= "0010";
bus_i.addr <= (others => '0');
bus_i.data <= (others => '0');
bus_i.re <= '0';
bus_i.we <= '0';
wait until Clk = '1';
comment <= write;
writeWord(addr => 16#0010#, data => 16#0055#, bus_i => bus_i, clk => clk);
wait until Clk = '1';
wait until Clk = '1';
writeWord(addr => 16#0011#, data => 16#005f#, bus_i => bus_i, clk => clk);
wait until Clk = '1';
wait until Clk = '1';
-- read the registers
-- expected data is the input to the register_file reg_i(0) and reg_i(1)
comment <= read;
readWord(addr => BASE_ADDRESS, bus_i => bus_i, clk => clk);
readWord(addr => BASE_ADDRESS + 1, bus_i => bus_i, clk => clk);
-- do the same reads, but the DUT shouldn't react
-- bus data should be 0000
readWord(addr => BASE_ADDRESS + 2, bus_i => bus_i, clk => clk);
-- read from correct address again
readWord(addr => BASE_ADDRESS + 1, bus_i => bus_i, clk => clk);
wait for 1000 ns;
end process WaveGen_Proc;
end tb;
-------------------------------------------------------------------------------
|
bsd-3-clause
|
dergraaf/loa
|
fpga/modules/signalprocessing/hdl/goertzel_pipelined_v2.vhd
|
2
|
5089
|
-------------------------------------------------------------------------------
-- Title : Goertzel Algorithm pipelined with BRAM
-- Project :
-------------------------------------------------------------------------------
-- File : goertzel_pipelined_v2.vhd
-- Author : strongly-typed
-- Created : 2012-04-24
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
--
-- ToDos : The throughput can be increased by:
-- i) Reduce steps in pipeline
-- ii) Do not wait to put a new value into the pipeline until the
-- last result was processed. Alternate reading and writing to
-- the BRAM. Need to store the address of the the data
-- currently in progress.
-------------------------------------------------------------------------------
-- Copyright (c) 2012
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.signalprocessing_pkg.all;
entity goertzel_pipelined_v2 is
generic (
FREQUENCIES : positive;
CHANNELS : positive := 12;
SAMPLES : positive := 250;
Q : positive := 13);
port (
start_p : in std_logic;
bram_addr_p : out std_logic_vector(7 downto 0);
bram_data_i : in std_logic_vector(35 downto 0);
bram_data_o : out std_logic_vector(35 downto 0);
bram_we_p : out std_logic;
ready_p : out std_logic;
enable_p : in std_logic;
coefs_p : in goertzel_coefs_type(FREQUENCIES-1 downto 0);
inputs_p : in goertzel_inputs_type(CHANNELS-1 downto 0);
clk : in std_logic);
end entity goertzel_pipelined_v2;
architecture structural of goertzel_pipelined_v2 is
signal start_s : std_logic := '0';
-- select signals of muxes
signal mux_delay1_s : std_logic := '0';
signal mux_delay2_s : std_logic := '0';
signal mux_coef_s : natural range FREQUENCIES-1 downto 0 := 0;
signal mux_input_s : natural range CHANNELS-1 downto 0 := 0;
-- outputs of the muxes
signal muxed_delay1_s : goertzel_data_type := (others => '0');
signal muxed_delay2_s : goertzel_data_type := (others => '0');
signal muxed_coef_s : goertzel_coef_type := (others => '0');
signal muxed_input_s : goertzel_input_type := (others => '0');
-- inter-instance routing
signal bram_data_i_s : goertzel_result_type := (others => (others => '0'));
signal goertzel_result_to_bram_s : goertzel_result_type := (others => (others => '0'));
signal pipeline_input_s : goertzel_result_type := (others => (others => '0'));
begin -- architecture structural
start_s <= start_p;
pipeline_input_s(0) <= muxed_delay1_s;
pipeline_input_s(1) <= muxed_delay2_s;
-- map generic std_logic_vector(35 downto 0) form bram
-- to strongly-tyed goertzel_result_type of pipeline
-- |35 ---- 18||17 ------ 0| BRAM
-- |--delay2--||--delay1--|| pipeline
bram_data_i_s(0) <= signed(bram_data_i(17 downto 0));
bram_data_i_s(1) <= signed(bram_data_i(35 downto 18));
-- from pipeline to bram
bram_data_o <= std_logic_vector(goertzel_result_to_bram_s(1)) & std_logic_vector(goertzel_result_to_bram_s(0));
-- muxes to multiplex one of the channels to the pipeline
goertzel_muxes_1 : entity work.goertzel_muxes
generic map (
CHANNELS => CHANNELS,
FREQUENCIES => FREQUENCIES)
port map (
mux_delay1_p => mux_delay1_s,
mux_delay2_p => mux_delay2_s,
mux_coef => mux_coef_s,
mux_input => mux_input_s,
bram_data => bram_data_i_s,
coefs_p => coefs_p,
inputs_p => inputs_p,
delay1_p => muxed_delay1_s,
delay2_p => muxed_delay2_s,
coef_p => muxed_coef_s,
input_p => muxed_input_s);
-- control the pipeline
goertzel_control_unit_1 : entity work.goertzel_control_unit
generic map (
SAMPLES => SAMPLES,
FREQUENCIES => FREQUENCIES,
CHANNELS => CHANNELS)
port map (
start_p => start_s,
ready_p => ready_p,
-- output to the bram
bram_addr_p => bram_addr_p,
bram_we_p => bram_we_p,
-- outputs to the mux
mux_delay1_p => mux_delay1_s,
mux_delay2_p => mux_delay2_s,
mux_coef_p => mux_coef_s,
mux_input_p => mux_input_s,
clk => clk);
-- the actual pipiline working on one frequency and on one channel
goertzel_pipeline_1 : entity work.goertzel_pipeline
generic map (
Q => Q)
port map (
coef_p => muxed_coef_s,
input_p => muxed_input_s,
delay_p => pipeline_input_s,
result_p => goertzel_result_to_bram_s,
clk => clk);
end architecture structural;
|
bsd-3-clause
|
dergraaf/loa
|
fpga/modules/utils/hdl/edge_detect.vhd
|
2
|
1070
|
-------------------------------------------------------------------------------
-- Title : Edge Detect
-------------------------------------------------------------------------------
-- Author : Lothar Miller
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: See http://www.lothar-miller.de/s9y/categories/18-Flankenerkennung
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity edge_detect is
port (async_sig : in std_logic;
clk : in std_logic;
rise : out std_logic;
fall : out std_logic);
end;
architecture RTL of edge_detect is
begin
process
variable sr : std_logic_vector (3 downto 0) := "0000";
begin
wait until rising_edge(clk);
-- detect edge
rise <= not sr(3) and sr(2);
fall <= not sr(2) and sr(3);
-- read input into shift register
sr := sr(2 downto 0) & async_sig;
end process;
end architecture;
|
bsd-3-clause
|
dergraaf/loa
|
fpga/modules/uart/tb/uart_tb_pkg.vhd
|
2
|
1595
|
-------------------------------------------------------------------------------
-- Title : UART Testbench support procedures
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2013 Fabian Greif
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package uart_tb_pkg is
procedure uart_transmit (
-- The signal that is to be driven by this model...
signal tx_line : out std_logic;
-- Inputs to control how to send one character:
data : in std_logic_vector; -- usually 8 bits
baud_rate : in integer -- e.g. 9600
);
end package uart_tb_pkg;
package body uart_tb_pkg is
procedure uart_transmit (
-- The signal that is to be driven by this model...
signal tx_line : out std_logic;
-- Inputs to control how to send one character:
data : in std_logic_vector; -- usually 8 bits
baud_rate : in integer -- e.g. 9600
) is
constant bit_time : time := 1 sec / baud_rate;
begin
-- Send the start bit
tx_line <= '0';
wait for bit_time;
-- Send the data bits, least significant first
for i in data'reverse_range loop
tx_line <= data(i);
wait for bit_time;
end loop;
-- Send the stop bit
tx_line <= '1';
wait for bit_time;
end uart_transmit;
end uart_tb_pkg;
|
bsd-3-clause
|
dergraaf/loa
|
fpga/modules/pwm/hdl/pwm.vhd
|
2
|
2242
|
--!
--! Simple PWM generator
--!
--! PWM frequency (f_pwm) is: f_pwm = clk / ((2 ^ width) - 1)
--!
--! Example:
--! clk = 50 MHz
--! clk_en = constant '1' (no prescaler)
--! width = 8 => value = 0..255
--!
--! => f_pwm = 1/510ns = 0,1960784 MHz = 50/255 MHz
--!
--! Value (for width = 8):
--! 0 => output constant low
--! 1 => 254 cycle low, 1 cycle high
--! 127 => 50% (128 cycles low, 127 cycles high)
--! 128 => 50% (127 cycles low, 128 cycles high)
--! 254 => 1 cycle low, 254 cycles high
--! 255 => output constant high
--!
--! @author Fabian Greif
--!
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pwm is
generic (
WIDTH : natural := 12); --! Number of bits used for the PWM (12bit => 0..4095)
port (
clk_en_p : in std_logic; --! clock enable
value_p : in std_logic_vector (width - 1 downto 0);
output_p : out std_logic;
reset : in std_logic; --! High active, Restarts the PWM period
clk : in std_logic
);
end pwm;
-- ----------------------------------------------------------------------------
architecture simple of pwm is
signal count : integer range 0 to ((2 ** WIDTH) - 2) := 0;
signal value_buf : std_logic_vector(width - 1 downto 0) := (others => '0');
begin
-- Counter
process
begin
wait until rising_edge(clk);
if reset = '1' then
-- Load new value and reset counter => restart periode
count <= 0;
value_buf <= value_p;
elsif clk_en_p = '1' then
-- counter
if count < ((2 ** WIDTH) - 2) then
count <= count + 1;
else
count <= 0;
-- Load new value from the shadow register (not active before
-- the next clock cycle)
value_buf <= value_p;
end if;
end if;
end process;
-- Generate Output
process
begin
wait until rising_edge(clk);
if reset = '1' then
output_p <= '0';
else
-- comparator for the output
if count >= to_integer(unsigned(value_buf)) then
output_p <= '0';
else
output_p <= '1';
end if;
end if;
end process;
end simple;
|
bsd-3-clause
|
dergraaf/loa
|
fpga/modules/ir_rx/tb/ir_rx_module_timestamp_tb.vhd
|
2
|
3560
|
-------------------------------------------------------------------------------
-- Title : Testbench for design "ir_rx_module" with timestamps
------------------------------------------------------------------------------
-- File : ir_rx_module_timestamp_tb.vhd
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2012
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.bus_pkg.all;
use work.utils_pkg.all;
use work.adc_ltc2351_pkg.all;
use work.ir_rx_module_pkg.all;
use work.signalprocessing_pkg.all;
-------------------------------------------------------------------------------
entity ir_rx_module_timestamp_tb is
end ir_rx_module_timestamp_tb;
-------------------------------------------------------------------------------
architecture tb of ir_rx_module_timestamp_tb is
-- component generics
constant BASE_ADDRESS_RESULTS : integer := 16#0800#;
constant BASE_ADDRESS_COEFS : integer := 16#0010#;
constant BASE_ADDRESS_TIMESTAMP : integer := 16#0100#;
constant TIMESTAMP_WIDTH : natural := 48;
-- component ports
signal adc_out_p : ir_rx_module_spi_out_type;
signal adc_in_p : ir_rx_module_spi_in_type := (others => (others => '0'));
signal sync_p : std_logic := '0';
signal bus_o : busdevice_out_type := (data => (others => '0'));
signal bus_i : busdevice_in_type := (addr => (others => '0'),
data => (others => '0'),
we => '0',
re => '0');
signal done_p : std_logic := '0';
signal ack_p : std_logic := '0';
signal clk_sample_en : std_logic := '0';
-- timestamp
signal timestamp_s : timestamp_type;
-- clock
signal clk : std_logic := '1';
begin -- tb
ir_rx_module_1 : entity work.ir_rx_module
generic map (
BASE_ADDRESS_COEFS => BASE_ADDRESS_COEFS,
BASE_ADDRESS_RESULTS => BASE_ADDRESS_RESULTS,
BASE_ADDRESS_TIMESTAMP => BASE_ADDRESS_TIMESTAMP,
SAMPLES => 10)
port map (
adc_o_p => adc_out_p,
adc_i_p => adc_in_p,
adc_values_o_p => open,
sync_o_p => sync_p,
bus_o_p => bus_o,
bus_i_p => bus_i,
done_o_p => done_p,
ack_i_p => ack_p,
clk_sample_en_i_p => clk_sample_en,
timestamp_i_p => timestamp_s,
clk => clk);
timestamp_1 : entity work.timestamp_generator
port map (
timestamp_o_p => timestamp_s,
clk => clk);
-- clock generation
clk <= not clk after 10 ns;
-- Trigger ADC conversions
WaveGen_Proc : process
begin
wait until clk = '1';
if done_p = '0' then
clk_sample_en <= '1';
end if;
wait until clk = '1';
clk_sample_en <= '0';
wait
for 7 us;
end process WaveGen_Proc;
-- Acknowledge if the module is finished
ack_proc : process
begin -- process ack_proc
wait until done_p = '1';
wait
for 5 us;
ack_p <= '1';
wait
for 1 us;
ack_p <= '0';
end process ack_proc;
end tb;
|
bsd-3-clause
|
dergraaf/loa
|
fpga/modules/utils/tb/edge_detect_tb.vhd
|
2
|
1875
|
-------------------------------------------------------------------------------
-- Title : Testbench for design "edge_detect"
-------------------------------------------------------------------------------
-- File : edge_detect_tb.vhd
-- Author : Lothar Miller
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use work.utils_pkg.all;
-------------------------------------------------------------------------------
entity edge_detect_tb is
end entity edge_detect_tb;
-------------------------------------------------------------------------------
architecture tb of edge_detect_tb is
--Inputs
signal async_sig : std_logic := '0';
--Outputs
signal rise : std_logic;
signal fall : std_logic;
-- clock
signal clk : std_logic := '1';
begin -- architecture tb
-- component instantiation
uut : edge_detect
port map (
async_sig => async_sig,
clk => clk,
rise => rise,
fall => fall);
-- clock generation
clk <= not clk after 5 ns;
-- Create an asynchronous, random signal
stim : process
variable seed1, seed2 : positive;
variable Rand : real;
variable IRand : integer;
begin
-- Zufallszahl ziwschen 0 und 1
uniform(seed1, seed2, rand);
-- daraus ein Integer zwischen 50 und 150
irand := integer((rand*100.0 - 0.5) + 50.0);
-- und dann diese Zeit abwarten
wait for irand * 1 ns;
async_sig <= not async_sig;
end process;
end architecture tb;
-------------------------------------------------------------------------------
|
bsd-3-clause
|
dergraaf/loa
|
fpga/modules/signalprocessing/hdl/goertzel_pipeline.vhd
|
2
|
3706
|
-------------------------------------------------------------------------------
-- Title : Fixed point implementation of Goertzel's Algorithm
-------------------------------------------------------------------------------
-- Author : strongly-typed
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description: Fixed point implementation of Goertzel's Algorithm to detect a
-- fixed frequency in an analog signal.
--
-- This is just the pipeline. The control unit in in entity
-- goertzel_control_unit and the muxes are in goertzel_muxes.
--
-- This does not implement the calculation
-- of the magnitude of the signal at the end of one block.
-- Mind overflows!
-------------------------------------------------------------------------------
-- Copyright (c) 2012
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library work;
use work.signalprocessing_pkg.all;
-------------------------------------------------------------------------------
entity goertzel_pipeline is
generic (
-- Width of ADC input
-- Due to overflow prevention: Not as wide as the internal width of
-- calculations. Set in the signalprocessing_pkg.vhd
-- INPUT_WIDTH : natural := 14;
-- Width of internal calculations
-- Remember that internal multiplier are at most 18 bits wide (in Xilinx Spartan)
-- CALC_WIDTH : natural := 18;
-- Fixed point data format
Q : natural := 13
);
port (
-- Goertzel Coefficient calculated by
coef_p : in goertzel_coef_type;
-- One values from ADC
input_p : in goertzel_input_type;
-- The old result
delay_p : in goertzel_result_type;
-- Result
result_p : out goertzel_result_type;
clk : in std_logic
);
end goertzel_pipeline;
architecture rtl of goertzel_pipeline is
signal delay_1_reg : goertzel_data_type := (others => '0');
signal delay_1_reg2 : goertzel_data_type := (others => '0');
signal delay_2_reg : goertzel_data_type := (others => '0');
signal delay_2_reg2 : goertzel_data_type := (others => '0');
signal coef_reg : goertzel_coef_type := (others => '0');
signal input_reg : goertzel_input_type := (others => '0');
signal input_reg2 : goertzel_input_type := (others => '0');
signal prod_scaled_reg : goertzel_data_type := (others => '0');
signal overflow : std_logic := '0';
begin -- architecture rtl
-- data path B
B : process (clk) is
variable prod_v : signed(35 downto 0) := (others => '0');
begin -- process B
if rising_edge(clk) then -- rising clock edge
-- 1st RTL
-- inputs from BRAM is already registered
--delay_1_reg2 <= delay_p(0);
--delay_2_reg2 <= delay_p(1);
coef_reg <= coef_p;
input_reg <= input_p;
-- 2nd RTL
delay_1_reg2 <= delay_p(0);
delay_2_reg2 <= delay_p(1);
prod_v := delay_p(0) * coef_reg;
prod_scaled_reg <= prod_v((Q + CALC_WIDTH - 1) downto Q);
if (prod_v(35 downto Q + CALC_WIDTH) = (35 downto (Q + CALC_WIDTH) => '0')) or
(prod_v(35 downto Q + CALC_WIDTH) = (35 downto (Q + CALC_WIDTH) => '1')) then
overflow <= '0';
else
overflow <= '1';
end if;
input_reg2 <= input_reg;
-- 3rd RTL
result_p(0) <= -delay_2_reg2 + prod_scaled_reg + input_reg2;
result_p(1) <= delay_1_reg2;
end if;
end process B;
end architecture rtl;
|
bsd-3-clause
|
dergraaf/loa
|
fpga/modules/peripheral_register/hdl/reg_file_bram.vhd
|
1
|
6529
|
-------------------------------------------------------------------------------
-- Title : A Register File Made of Dual Port Block RAM
-------------------------------------------------------------------------------
-- Platform : Xilinx Spartan 3A
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description: A Larger Register File Using Block RAM.
--
-- A dual port block RAM is interfaced to the internal parallel
-- bus.
--
-- Each SelectRAM in Spartan-3(A/E/AN) has 18432 data bits and can
-- be configured as 1024 address x 16 data bits.
--
-- Port A of Block RAM: connected to the internal parallel bus:
-- 1024 addresses of 16 bits
-- 1024 address = 10 bits (9 downto 0)
--
-- Port B: used by the internal processes of the design.
-- Same configuration
--
-------------------------------------------------------------------------------
-- Copyright (c) 2012 strongly-typed
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.bus_pkg.all;
use work.reg_file_pkg.all;
use work.xilinx_block_ram_pkg.all;
-------------------------------------------------------------------------------
entity reg_file_bram is
generic (
-- The module uses 10 bits for 1024 addresses and the base address must be aligned.
-- Valid BASE_ADDRESSes are 0x0000, 0x0400, 0x0800, ...
BASE_ADDRESS : integer range 0 to 2**15-1);
port (
-- Interface to the internal parallel bus.
bus_o : out busdevice_out_type;
bus_i : in busdevice_in_type;
-- Read and write interface to the block RAM for the application.
bram_data_i : in std_logic_vector(15 downto 0) := (others => '0');
bram_data_o : out std_logic_vector(15 downto 0) := (others => '0');
bram_addr_i : in std_logic_vector(9 downto 0) := (others => '0');
bram_we_p : in std_logic := '0';
-- No reset, all signals are initialised.
clk : in std_logic);
end reg_file_bram;
-------------------------------------------------------------------------------
architecture str of reg_file_bram is
constant BASE_ADDRESS_VECTOR : std_logic_vector(14 downto 0) :=
std_logic_vector(to_unsigned(BASE_ADDRESS, 15));
-- Port A to bus
constant ADDR_A_WIDTH : positive := 10;
constant DATA_A_WIDTH : positive := 16;
-- Port B to application
constant ADDR_B_WIDTH : positive := 10;
constant DATA_B_WIDTH : positive := 16;
-----------------------------------------------------------------------------
-- Internal signal declarations
-----------------------------------------------------------------------------
signal ram_a_addr : std_logic_vector(ADDR_A_WIDTH-1 downto 0) := (others => '0');
signal ram_a_out : std_logic_vector(DATA_A_WIDTH-1 downto 0) := (others => '0');
signal ram_a_in : std_logic_vector(DATA_A_WIDTH-1 downto 0) := (others => '0');
signal ram_a_we : std_logic := '0';
signal ram_a_en : std_logic := '0';
signal ram_a_ssr : std_logic := '0';
signal ram_b_addr : std_logic_vector(ADDR_B_WIDTH-1 downto 0) := (others => '0');
signal ram_b_out : std_logic_vector(DATA_B_WIDTH-1 downto 0) := (others => '0');
signal ram_b_in : std_logic_vector(DATA_B_WIDTH-1 downto 0) := (others => '0');
signal ram_b_we : std_logic := '0';
signal ram_b_en : std_logic := '0';
signal ram_b_ssr : std_logic := '0';
--
signal addr_match_a : std_logic;
signal bus_o_enable_d : std_logic := '0';
signal bus_o_enable_d2 : std_logic := '0';
begin -- str
----------------------------------------------------------------------------
-- Connections
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- Block RAM as dual port RAM with asymmetrical port widths.
----------------------------------------------------------------------------
dp_1 : xilinx_block_ram_dual_port
generic map (
ADDR_A_WIDTH => ADDR_A_WIDTH,
ADDR_B_WIDTH => ADDR_B_WIDTH,
DATA_A_WIDTH => DATA_A_WIDTH,
DATA_B_WIDTH => DATA_B_WIDTH)
port map (
addr_a => ram_a_addr,
addr_b => ram_b_addr,
din_a => ram_a_in,
din_b => ram_b_in,
dout_a => ram_a_out,
dout_b => ram_b_out,
we_a => ram_a_we,
we_b => ram_b_we,
en_a => ram_a_en,
en_b => ram_b_en,
ssr_a => ram_a_ssr,
ssr_b => ram_b_ssr,
clk_a => clk,
clk_b => clk);
----------------------------------------------------------------------------
-- Port A: parallel bus
----------------------------------------------------------------------------
-- Always present the address from the parallel bus to the block RAM.
-- When the bus address matches the address range of the block RAM
-- route the result of the Block RAM to the parallel bus.
ram_a_addr <= bus_i.addr(ADDR_A_WIDTH-1 downto 0);
ram_a_in <= bus_i.data;
-- ADDR_A_WIDTH = 10
-- 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-- |<---- match ---->|
addr_match_a <= '1' when (bus_i.addr(14 downto ADDR_A_WIDTH) = BASE_ADDRESS_VECTOR(14 downto ADDR_A_WIDTH)) else '0';
-- Always enable RAM
ram_a_en <= '1';
-- The block RAM keeps its output latches when EN is '0'. This behaviour is
-- not compatible with the parallel bus where the bus output must be 0 when
-- the device is not selected.
-- Solution: Use Synchronous Reset of the output latches:
ram_a_ssr <= '0' when (addr_match_a = '1') and (bus_i.re = '1') else '1';
-- Write enable
ram_a_we <= '1' when (addr_match_a = '1') and (bus_i.we = '1') else '0';
bus_o.data <= ram_a_out;
----------------------------------------------------------------------------
-- Port B: internal device
----------------------------------------------------------------------------
-- always enable the RAM
ram_b_en <= '1';
-- write to the RAM
ram_b_we <= bram_we_p;
ram_b_addr <= bram_addr_i;
ram_b_in <= bram_data_i;
bram_data_o <= ram_b_out;
end str;
-------------------------------------------------------------------------------
|
bsd-3-clause
|
dergraaf/loa
|
fpga/modules/encoder/tb/quadrature_decoder_tb.vhd
|
2
|
4087
|
-------------------------------------------------------------------------------
-- Title : Testbench for design "quadrature_decoder"
-------------------------------------------------------------------------------
-- Author : Fabian Greif <fabian@kleinvieh>
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2011
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.quadrature_decoder_pkg.all;
use work.encoder_module_pkg.all;
-------------------------------------------------------------------------------
entity quadrature_decoder_tb is
end quadrature_decoder_tb;
-------------------------------------------------------------------------------
architecture tb of quadrature_decoder_tb is
type input_type is record
a : std_logic;
b : std_logic;
end record;
type expect_type is record
step : std_logic;
dir : std_logic;
error : std_logic;
end record;
type stimulus_type is record
input : input_type;
expect : expect_type;
end record;
type stimuli_type is array (natural range <>) of stimulus_type;
constant stimuli : stimuli_type := (
(input => ('0', '0'), expect => ('0', '-', '0')),
(input => ('1', '0'), expect => ('1', '1', '0')),
(input => ('1', '0'), expect => ('0', '-', '0')),
(input => ('1', '1'), expect => ('1', '1', '0')),
(input => ('0', '1'), expect => ('1', '1', '0')),
(input => ('0', '0'), expect => ('1', '1', '0')),
(input => ('1', '0'), expect => ('1', '1', '0')),
(input => ('1', '1'), expect => ('1', '1', '0')),
(input => ('1', '1'), expect => ('0', '-', '0')),
(input => ('1', '0'), expect => ('1', '0', '0')),
(input => ('0', '0'), expect => ('1', '0', '0')),
(input => ('1', '0'), expect => ('1', '1', '0')),
(input => ('0', '0'), expect => ('1', '0', '0')),
(input => ('0', '0'), expect => ('0', '-', '0')),
(input => ('0', '1'), expect => ('1', '0', '0')),
(input => ('0', '0'), expect => ('1', '1', '0')),
(input => ('0', '1'), expect => ('1', '0', '0')),
(input => ('1', '1'), expect => ('1', '0', '0')),
(input => ('1', '0'), expect => ('1', '0', '0')),
(input => ('0', '0'), expect => ('1', '0', '0')),
(input => ('1', '1'), expect => ('0', '-', '1')),
(input => ('0', '0'), expect => ('0', '-', '1')),
(input => ('0', '1'), expect => ('1', '0', '0')),
(input => ('1', '1'), expect => ('1', '0', '0')),
(input => ('0', '0'), expect => ('0', '-', '1')),
(input => ('0', '0'), expect => ('0', '0', '0'))
);
-- component ports
signal ab : encoder_type := (a => '0', b => '0');
signal step : std_logic;
signal dir : std_logic;
signal error : std_logic;
-- clock
signal clk : std_logic := '1';
begin
-- component instantiation
DUT : quadrature_decoder
port map (
encoder_p => ab,
step_p => step,
dir_p => dir,
error_p => error,
clk => clk);
-- clock generation
clk <= not clk after 10 ns;
-- waveform generation
wave : process
begin
wait for 20 ns;
for i in stimuli'left to (stimuli'right + 2) loop
wait until rising_edge(clk);
if i <= stimuli'right then
ab.a <= stimuli(i).input.a;
ab.b <= stimuli(i).input.b;
else
ab.a <= '0';
ab.b <= '0';
end if;
if i > (stimuli'left + 2) then
-- values are active at the output after two clock cycles
assert (step = stimuli(i-2).expect.step) report "Wrong value for 'step'" severity note;
if not (stimuli(i-2).expect.dir = '-') then
assert (dir = stimuli(i-2).expect.dir) report "Wrong value for 'dir'" severity note;
end if;
assert (error = stimuli(i-2).expect.error) report "Wrong value for 'error'" severity note;
end if;
end loop; -- i
end process wave;
end tb;
|
bsd-3-clause
|
cnplab/blockmon
|
fw-combo/src/netcope-sim/testbench.vhd
|
1
|
19706
|
-- -----------------------------------------------------------------------
--
-- Company: INVEA-TECH a.s.
--
-- Project: IPFIX design
--
-- -----------------------------------------------------------------------
--
-- (c) Copyright 2011 INVEA-TECH a.s.
-- All rights reserved.
--
-- Please review the terms of the license agreement before using this
-- file. If you are not an authorized user, please destroy this
-- source code file and notify INVEA-TECH a.s. immediately that you
-- inadvertently received an unauthorized copy.
--
-- -----------------------------------------------------------------------
--
-- testbench.vhd: Testbench for the Application entity
-- Copyright (C) 2009 CESNET
-- Author(s): Viktor Pus <[email protected]>
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in
-- the documentation and/or other materials provided with the
-- distribution.
-- 3. Neither the name of the Company nor the names of its contributors
-- may be used to endorse or promote products derived from this
-- software without specific prior written permission.
--
-- This software is provided ``as is'', and any express or implied
-- warranties, including, but not limited to, the implied warranties of
-- merchantability and fitness for a particular purpose are disclaimed.
-- In no event shall the company or contributors be liable for any
-- direct, indirect, incidental, special, exemplary, or consequential
-- damages (including, but not limited to, procurement of substitute
-- goods or services; loss of use, data, or profits; or business
-- interruption) however caused and on any theory of liability, whether
-- in contract, strict liability, or tort (including negligence or
-- otherwise) arising in any way out of the use of this software, even
-- if advised of the possibility of such damage.
--
-- $Id: testbench.vhd 12037 2011-04-15 13:17:09Z kastovsky $
--
-- TODO:
--
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_textio.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.ib_pkg.all;
use work.ib_bfm_pkg.all;
use work.mi_bfm_pkg.all;
use work.fl_bfm_pkg.all;
use work.fl_bfm_rdy_pkg.all;
-- ----------------------------------------------------------------------------
-- Entity declaration
-- ----------------------------------------------------------------------------
entity testbench is
end entity testbench;
-- ----------------------------------------------------------------------------
-- Architecture declaration
-- ----------------------------------------------------------------------------
architecture behavioral of testbench is
constant MEMORY_BASE_ADDR : std_logic_vector(63 downto 0) := X"0000000000000000";
constant MEMORY_SIZE : integer := 16#94000#;
-- ----------------------------------------------------------------------
-- CLOCKs and RESET
-- ----------------------------------------------------------------------
-- CLK:
signal clk : std_logic;
-- reset
signal reset : std_logic;
-- ----------------------------------------------------------------------
-- Interconnection system
-- ----------------------------------------------------------------------
-- Internal Bus interface (Fast)
signal ib_up_data : std_logic_vector(63 downto 0);
signal ib_up_sop_n : std_logic;
signal ib_up_eop_n : std_logic;
signal ib_up_src_rdy_n : std_logic;
signal ib_up_dst_rdy_n : std_logic;
signal ib_down_data : std_logic_vector(63 downto 0);
signal ib_down_sop_n : std_logic;
signal ib_down_eop_n : std_logic;
signal ib_down_src_rdy_n : std_logic;
signal ib_down_dst_rdy_n : std_logic;
-- MI32
signal mi32_dwr : std_logic_vector(31 downto 0);
signal mi32_addr : std_logic_vector(31 downto 0);
signal mi32_rd : std_logic;
signal mi32_wr : std_logic;
signal mi32_be : std_logic_vector(3 downto 0);
signal mi32_drd : std_logic_vector(31 downto 0);
signal mi32_ardy : std_logic;
signal mi32_drdy : std_logic;
-- Timestamp for pacodag
signal ts : std_logic_vector(63 downto 0);
signal ts_dv : std_logic;
signal ts_clk : std_logic;
-- ----------------------------------------------------------------------
-- Experiment FrameLink interface signals
-- ----------------------------------------------------------------------
-- NETWORK -> APPLICATION
signal network_rx0_data : std_logic_vector(63 downto 0);
signal network_rx0_drem : std_logic_vector(2 downto 0);
signal network_rx0_sof_n : std_logic;
signal network_rx0_eof_n : std_logic;
signal network_rx0_sop_n : std_logic;
signal network_rx0_eop_n : std_logic;
signal network_rx0_src_rdy_n : std_logic;
signal network_rx0_dst_rdy_n : std_logic;
signal network_rx1_data : std_logic_vector(63 downto 0);
signal network_rx1_drem : std_logic_vector(2 downto 0);
signal network_rx1_sof_n : std_logic;
signal network_rx1_eof_n : std_logic;
signal network_rx1_sop_n : std_logic;
signal network_rx1_eop_n : std_logic;
signal network_rx1_src_rdy_n : std_logic;
signal network_rx1_dst_rdy_n : std_logic;
-- APPLICATION -> NETWORK
signal network_tx0_data : std_logic_vector(63 downto 0);
signal network_tx0_drem : std_logic_vector(2 downto 0);
signal network_tx0_sof_n : std_logic;
signal network_tx0_eof_n : std_logic;
signal network_tx0_sop_n : std_logic;
signal network_tx0_eop_n : std_logic;
signal network_tx0_src_rdy_n : std_logic;
signal network_tx0_dst_rdy_n : std_logic;
signal network_tx1_data : std_logic_vector(63 downto 0);
signal network_tx1_drem : std_logic_vector(2 downto 0);
signal network_tx1_sof_n : std_logic;
signal network_tx1_eof_n : std_logic;
signal network_tx1_sop_n : std_logic;
signal network_tx1_eop_n : std_logic;
signal network_tx1_src_rdy_n : std_logic;
signal network_tx1_dst_rdy_n : std_logic;
-- DMA interface
-- APPLICATION -> DMA
signal dma_rx0_data : std_logic_vector(63 downto 0);
signal dma_rx0_drem : std_logic_vector(2 downto 0);
signal dma_rx0_sof_n : std_logic;
signal dma_rx0_eof_n : std_logic;
signal dma_rx0_sop_n : std_logic;
signal dma_rx0_eop_n : std_logic;
signal dma_rx0_src_rdy_n : std_logic;
signal dma_rx0_dst_rdy_n : std_logic;
signal dma_rx1_data : std_logic_vector(63 downto 0);
signal dma_rx1_drem : std_logic_vector(2 downto 0);
signal dma_rx1_sof_n : std_logic;
signal dma_rx1_eof_n : std_logic;
signal dma_rx1_sop_n : std_logic;
signal dma_rx1_eop_n : std_logic;
signal dma_rx1_src_rdy_n : std_logic;
signal dma_rx1_dst_rdy_n : std_logic;
-- DMA -> APPLICATION
signal dma_tx0_data : std_logic_vector(63 downto 0);
signal dma_tx0_drem : std_logic_vector(2 downto 0);
signal dma_tx0_sof_n : std_logic;
signal dma_tx0_eof_n : std_logic;
signal dma_tx0_sop_n : std_logic;
signal dma_tx0_eop_n : std_logic;
signal dma_tx0_src_rdy_n : std_logic;
signal dma_tx0_dst_rdy_n : std_logic;
signal dma_tx1_data : std_logic_vector(63 downto 0);
signal dma_tx1_drem : std_logic_vector(2 downto 0);
signal dma_tx1_sof_n : std_logic;
signal dma_tx1_eof_n : std_logic;
signal dma_tx1_sop_n : std_logic;
signal dma_tx1_eop_n : std_logic;
signal dma_tx1_src_rdy_n : std_logic;
signal dma_tx1_dst_rdy_n : std_logic;
-- ----------------------------------------------------------------------
-- Time constants
-- ----------------------------------------------------------------------
constant clkper : time := 8 ns;
constant reset_time : time := 10*clkper;
-- ----------------------------------------------------------------------------
-- Architecture body
-- ----------------------------------------------------------------------------
begin
UUT : entity work.application
port map(
CLK => clk,
RESET => reset,
-- network interface
-- NETWORK -> APPLICATION
IBUF0_TX_DATA => network_rx0_data,
IBUF0_TX_REM => network_rx0_drem,
IBUF0_TX_SOF_N => network_rx0_sof_n,
IBUF0_TX_EOF_N => network_rx0_eof_n,
IBUF0_TX_SOP_N => network_rx0_sop_n,
IBUF0_TX_EOP_N => network_rx0_eop_n,
IBUF0_TX_SRC_RDY_N => network_rx0_src_rdy_n,
IBUF0_TX_DST_RDY_N => network_rx0_dst_rdy_n,
IBUF1_TX_DATA => network_rx1_data,
IBUF1_TX_REM => network_rx1_drem,
IBUF1_TX_SOF_N => network_rx1_sof_n,
IBUF1_TX_EOF_N => network_rx1_eof_n,
IBUF1_TX_SOP_N => network_rx1_sop_n,
IBUF1_TX_EOP_N => network_rx1_eop_n,
IBUF1_TX_SRC_RDY_N => network_rx1_src_rdy_n,
IBUF1_TX_DST_RDY_N => network_rx1_dst_rdy_n,
-- APPLICATION -> NETWORK
OBUF0_RX_DATA => network_tx0_data,
OBUF0_RX_REM => network_tx0_drem,
OBUF0_RX_SOF_N => network_tx0_sof_n,
OBUF0_RX_EOF_N => network_tx0_eof_n,
OBUF0_RX_SOP_N => network_tx0_sop_n,
OBUF0_RX_EOP_N => network_tx0_eop_n,
OBUF0_RX_SRC_RDY_N => network_tx0_src_rdy_n,
OBUF0_RX_DST_RDY_N => network_tx0_dst_rdy_n,
OBUF1_RX_DATA => network_tx1_data,
OBUF1_RX_REM => network_tx1_drem,
OBUF1_RX_SOF_N => network_tx1_sof_n,
OBUF1_RX_EOF_N => network_tx1_eof_n,
OBUF1_RX_SOP_N => network_tx1_sop_n,
OBUF1_RX_EOP_N => network_tx1_eop_n,
OBUF1_RX_SRC_RDY_N => network_tx1_src_rdy_n,
OBUF1_RX_DST_RDY_N => network_tx1_dst_rdy_n,
-- DMA interface
-- APPLICATION -> DMA
RX0_DATA => dma_tx0_data,
RX0_DREM => dma_tx0_drem,
RX0_SOF_N => dma_tx0_sof_n,
RX0_EOF_N => dma_tx0_eof_n,
RX0_SOP_N => dma_tx0_sop_n,
RX0_EOP_N => dma_tx0_eop_n,
RX0_SRC_RDY_N => dma_tx0_src_rdy_n,
RX0_DST_RDY_N => dma_tx0_dst_rdy_n,
RX1_DATA => dma_tx1_data,
RX1_DREM => dma_tx1_drem,
RX1_SOF_N => dma_tx1_sof_n,
RX1_EOF_N => dma_tx1_eof_n,
RX1_SOP_N => dma_tx1_sop_n,
RX1_EOP_N => dma_tx1_eop_n,
RX1_SRC_RDY_N => dma_tx1_src_rdy_n,
RX1_DST_RDY_N => dma_tx1_dst_rdy_n,
-- DMA -> APPLICATION
TX0_DATA => dma_rx0_data,
TX0_DREM => dma_rx0_drem,
TX0_SOF_N => dma_rx0_sof_n,
TX0_EOF_N => dma_rx0_eof_n,
TX0_SOP_N => dma_rx0_sop_n,
TX0_EOP_N => dma_rx0_eop_n,
TX0_SRC_RDY_N => dma_rx0_src_rdy_n,
TX0_DST_RDY_N => dma_rx0_dst_rdy_n,
TX1_DATA => dma_rx1_data,
TX1_DREM => dma_rx1_drem,
TX1_SOF_N => dma_rx1_sof_n,
TX1_EOF_N => dma_rx1_eof_n,
TX1_SOP_N => dma_rx1_sop_n,
TX1_EOP_N => dma_rx1_eop_n,
TX1_SRC_RDY_N => dma_rx1_src_rdy_n,
TX1_DST_RDY_N => dma_rx1_dst_rdy_n,
-- internal bus
IB_DOWN_DATA => ib_down_data,
IB_DOWN_SOF_N => ib_down_sop_n,
IB_DOWN_EOF_N => ib_down_eop_n,
IB_DOWN_SRC_RDY_N => ib_down_src_rdy_n,
IB_DOWN_DST_RDY_N => ib_down_dst_rdy_n,
IB_UP_DATA => ib_up_data,
IB_UP_SOF_N => ib_up_sop_n,
IB_UP_EOF_N => ib_up_eop_n,
IB_UP_SRC_RDY_N => ib_up_src_rdy_n,
IB_UP_DST_RDY_N => ib_up_dst_rdy_n,
-- mi32 bus
MI32_DWR => mi32_dwr,
MI32_ADDR => mi32_addr,
MI32_RD => mi32_rd,
MI32_WR => mi32_wr,
MI32_BE => mi32_be,
MI32_DRD => mi32_drd,
MI32_ARDY => mi32_ardy,
MI32_DRDY => mi32_drdy,
-- Timestamps for pacodag
TS => ts,
TS_DV => ts_dv,
TS_CLK => ts_clk,
-- PACODAG interface (no simulation model available)
IBUF0_CTRL_CLK => clk,
IBUF0_CTRL_DATA => open,
IBUF0_CTRL_REM => open,
IBUF0_CTRL_SRC_RDY_N => open,
IBUF0_CTRL_SOP_N => open,
IBUF0_CTRL_EOP_N => open,
IBUF0_CTRL_DST_RDY_N => '0',
IBUF0_CTRL_RDY => open,
IBUF1_CTRL_CLK => clk,
IBUF1_CTRL_DATA => open,
IBUF1_CTRL_REM => open,
IBUF1_CTRL_SRC_RDY_N => open,
IBUF1_CTRL_SOP_N => open,
IBUF1_CTRL_EOP_N => open,
IBUF1_CTRL_DST_RDY_N => '0',
IBUF1_CTRL_RDY => open,
-- IBUF status interface (no status information available)
IBUF0_SOP => '0',
IBUF0_PAYLOAD_LEN => X"0100",
IBUF0_FRAME_ERROR => '0',
IBUF0_CRC_CHECK_FAILED => '0',
IBUF0_MAC_CHECK_FAILED => '0',
IBUF0_LEN_BELOW_MIN => '0',
IBUF0_LEN_OVER_MTU => '0',
IBUF0_STAT_DV => '1',
IBUF1_SOP => '0',
IBUF1_PAYLOAD_LEN => X"0100",
IBUF1_FRAME_ERROR => '0',
IBUF1_CRC_CHECK_FAILED => '0',
IBUF1_MAC_CHECK_FAILED => '0',
IBUF1_LEN_BELOW_MIN => '0',
IBUF1_LEN_OVER_MTU => '0',
IBUF1_STAT_DV => '1'
);
-- CLK generator
clk_gen_p: process
begin
clk <= '1';
wait for clkper/2;
clk <= '0';
wait for clkper/2;
end process;
-- Internal Bus simulation component
IB_BFM_I : entity work.IB_BFM
generic map(
MEMORY_BASE_ADDR => MEMORY_BASE_ADDR,
MEMORY_SIZE => MEMORY_SIZE
)
port map(
-- Common interface
CLK => clk,
-- Internal Bus Interface
IB_DOWN_DATA => ib_down_data,
IB_DOWN_SOF_N => ib_down_sop_n,
IB_DOWN_EOF_N => ib_down_eop_n,
IB_DOWN_SRC_RDY_N => ib_down_src_rdy_n,
IB_DOWN_DST_RDY_N => ib_down_dst_rdy_n,
IB_UP_DATA => ib_up_data,
IB_UP_SOF_N => ib_up_sop_n,
IB_UP_EOF_N => ib_up_eop_n,
IB_UP_SRC_RDY_N => ib_up_src_rdy_n,
IB_UP_DST_RDY_N => ib_up_dst_rdy_n
);
-- MI32 Bus simulation component
MI_BFM_I : entity work.MI_BFM
port map (
CLK => clk,
RESET => reset,
MI32_DWR => mi32_dwr,
MI32_ADDR => mi32_addr,
MI32_BE => mi32_be,
MI32_RD => mi32_rd,
MI32_WR => mi32_wr,
MI32_ARDY => mi32_ardy,
MI32_DRD => mi32_drd,
MI32_DRDY => mi32_drdy
);
-- FrameLink simulation component
FL_BFM_NET_RX0 : entity work.FL_BFM
generic map (
DATA_WIDTH => 64,
FL_BFM_ID => 0)
port map (
-- Common interface
RESET => reset,
CLK => clk,
TX_DATA => network_rx0_data,
TX_REM => network_rx0_drem,
TX_SOF_N => network_rx0_sof_n,
TX_EOF_N => network_rx0_eof_n,
TX_SOP_N => network_rx0_sop_n,
TX_EOP_N => network_rx0_eop_n,
TX_SRC_RDY_N=> network_rx0_src_rdy_n,
TX_DST_RDY_N=> network_rx0_dst_rdy_n);
-- FrameLink simulation component
FL_BFM_NET_RX1 : entity work.FL_BFM
generic map (
DATA_WIDTH => 64,
FL_BFM_ID => 1)
port map (
-- Common interface
RESET => reset,
CLK => clk,
TX_DATA => network_rx1_data,
TX_REM => network_rx1_drem,
TX_SOF_N => network_rx1_sof_n,
TX_EOF_N => network_rx1_eof_n,
TX_SOP_N => network_rx1_sop_n,
TX_EOP_N => network_rx1_eop_n,
TX_SRC_RDY_N=> network_rx1_src_rdy_n,
TX_DST_RDY_N=> network_rx1_dst_rdy_n);
-- FrameLink simulation component
FL_BFM_DMA_TX0 : entity work.FL_BFM
generic map (
DATA_WIDTH => 64,
FL_BFM_ID => 2)
port map (
-- Common interface
RESET => reset,
CLK => clk,
TX_DATA => dma_tx0_data,
TX_REM => dma_tx0_drem,
TX_SOF_N => dma_tx0_sof_n,
TX_EOF_N => dma_tx0_eof_n,
TX_SOP_N => dma_tx0_sop_n,
TX_EOP_N => dma_tx0_eop_n,
TX_SRC_RDY_N=> dma_tx0_src_rdy_n,
TX_DST_RDY_N=> dma_tx0_dst_rdy_n);
-- FrameLink simulation component
FL_BFM_DMA_TX1 : entity work.FL_BFM
generic map (
DATA_WIDTH => 64,
FL_BFM_ID => 3)
port map (
-- Common interface
RESET => reset,
CLK => clk,
TX_DATA => dma_tx1_data,
TX_REM => dma_tx1_drem,
TX_SOF_N => dma_tx1_sof_n,
TX_EOF_N => dma_tx1_eof_n,
TX_SOP_N => dma_tx1_sop_n,
TX_EOP_N => dma_tx1_eop_n,
TX_SRC_RDY_N=> dma_tx1_src_rdy_n,
TX_DST_RDY_N=> dma_tx1_dst_rdy_n);
-----------------------------------------------------------------------------
-- Main testbench process
-----------------------------------------------------------------------------
tb : process
variable mi32_data : std_logic_vector(31 downto 0);
begin
-- Set Destination Ready signals to active
dma_rx0_dst_rdy_n <= '0';
dma_rx1_dst_rdy_n <= '0';
network_tx0_dst_rdy_n <= '0';
network_tx1_dst_rdy_n <= '0';
-- Reset the design
reset <= '1';
wait for reset_time;
reset <= '0';
wait for 5*clkper;
IBLocalWrite(X"02300000", -- DST Addr
X"FFFFFFF0", -- SRC Addr
8, -- Length (Bytes)
220, -- Tag
X"FEDCBA9876543210", -- Data
IbCmd); -- Command record
wait for 5*clkper;
IBLocalWrite(X"02300008", -- DST Addr
X"FFFFFFF0", -- SRC Addr
8, -- Length (Bytes)
220, -- Tag
X"1111222233334444", -- Data
IbCmd); -- Command record
wait for 5*clkper;
IBLocalRead( X"02300000", -- SRC Addr
X"FFFFFFF0", -- DST Addr
16, -- Length (Bytes)
220, -- Tag
IbCmd); -- Command record
wait for 5*clkper;
-- Recieve ICMP packet from network interface 0
FLWriteFile("./packets/icmp_net0.txt", EVER, flCmd_0, 0);
-- Recieve ICMP packet from network interface 1
FLWriteFile("./packets/icmp_net1.txt", EVER, flCmd_1, 1);
-- Dma module sending ICMP packet to interface 0, toggling SRC_RDY_N
FLWriteFile("./packets/icmp_dma.txt", ONOFF, flCmd_2, 2);
-- Dma module sending ICMP packet to interface 1, random SRC_RDY_N
FLWriteFile("./packets/icmp_dma.txt", RND, flCmd_3, 3);
-- Write 4 bytes through MI32 Bus
MI32Write(X"00080000", -- address
X"01234567", -- data
"1111", -- byte enables
status);
wait for 5*clkper;
-- Read 4 bytes through MI32 Bus
MI32Read(X"00080000", -- address
mi32_data, -- output data
"1111", -- byte enables
status);
wait for 5*clkper;
-- Read 4 bytes through MI32 Bus
MI32Read(X"00080800", -- address
mi32_data, -- output data
"1111", -- byte enables
status);
wait for 5*clkper;
-- Read 4 bytes through MI32 Bus
MI32Read(X"00080804", -- address
mi32_data, -- output data
"1111", -- byte enables
status);
wait;
end process;
end architecture;
|
bsd-3-clause
|
cnplab/blockmon
|
fw-combo/src/netcope-sim/models/mi_bfm.vhd
|
1
|
6184
|
-- -----------------------------------------------------------------------
--
-- Company: INVEA-TECH a.s.
--
-- Project: IPFIX design
--
-- -----------------------------------------------------------------------
--
-- (c) Copyright 2011 INVEA-TECH a.s.
-- All rights reserved.
--
-- Please review the terms of the license agreement before using this
-- file. If you are not an authorized user, please destroy this
-- source code file and notify INVEA-TECH a.s. immediately that you
-- inadvertently received an unauthorized copy.
--
-- -----------------------------------------------------------------------
--
--
-- mi_bfm.vhd : MI32 simulation component
-- Copyright (C) 2008 CESNET
-- Author(s): Jakub Sochor <[email protected]>
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in
-- the documentation and/or other materials provided with the
-- distribution.
-- 3. Neither the name of the Company nor the names of its contributors
-- may be used to endorse or promote products derived from this
-- software without specific prior written permission.
--
-- This software is provided ``as is'', and any express or implied
-- warranties, including, but not limited to, the implied warranties of
-- merchantability and fitness for a particular purpose are disclaimed.
-- In no event shall the company or contributors be liable for any
-- direct, indirect, incidental, special, exemplary, or consequential
-- damages (including, but not limited to, procurement of substitute
-- goods or services; loss of use, data, or profits; or business
-- interruption) however caused and on any theory of liability, whether
-- in contract, strict liability, or tort (including negligence or
-- otherwise) arising in any way out of the use of this software, even
-- if advised of the possibility of such damage.
--
-- $Id: mi_bfm.vhd 12021 2011-04-15 08:23:45Z kastovsky $
--
-- TODO:
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
use work.mi_bfm_pkg.all;
use work.math_pack.all;
-- ----------------------------------------------------------------------------
-- ENTITY DECLARATION --
-- ----------------------------------------------------------------------------
entity MI_BFM is
port(
-- Common interface -----------------------------------------------------
CLK : in std_logic;
RESET : in std_logic;
-- Output MI interfaces -------------------------------------------------
MI32_DWR : out std_logic_vector(31 downto 0);
MI32_ADDR : out std_logic_vector(31 downto 0);
MI32_BE : out std_logic_vector(3 downto 0);
MI32_DRD : in std_logic_vector(31 downto 0);
MI32_RD : out std_logic;
MI32_WR : out std_logic;
MI32_ARDY : in std_logic;
MI32_DRDY : in std_logic
);
end entity MI_BFM;
architecture MI_BFM_ARCH of MI_BFM is
signal commandStatus : TCommandStatus := ('0', '0', 'Z');
procedure SendTransaction(variable trans : inout TTransaction;
signal CLK : in std_logic;
signal MI32_DWR : out std_logic_vector(31 downto 0);
signal MI32_ADDR : out std_logic_vector(31 downto 0);
signal MI32_BE : out std_logic_vector(3 downto 0);
signal MI32_WR : out std_logic;
signal MI32_RD : out std_logic;
signal MI32_DRD : in std_logic_vector(31 downto 0);
signal MI32_DRDY : in std_logic;
signal MI32_ARDY : in std_logic) is
begin
if (trans.DIRECTION = READ) then
wait until (CLK'event and CLK = '1');
MI32_ADDR <= trans.ADDR;
MI32_BE <= trans.BE;
MI32_RD <= '1';
wait until (CLK'event and CLK = '1' and MI32_ARDY = '1');
MI32_RD <= '0';
MI32_ADDR <= (others => '0');
MI32_BE <= (others => '0');
wait until (CLK'event and CLK = '1' and MI32_DRDY = '1');
trans.DATA := MI32_DRD;
wait until (CLK'event and CLK = '1');
else
MI32_ADDR <= trans.ADDR;
MI32_BE <= trans.BE;
MI32_DWR <= trans.DATA;
MI32_WR <= '1';
while (MI32_ARDY = '0') loop
wait until MI32_ARDY = '1';
end loop;
wait until (CLK'event and CLK = '0');
wait until (CLK'event and CLK = '1');
MI32_WR <= '0';
MI32_ADDR <= (others => '0');
MI32_DWR <= (others => '0');
MI32_BE <= (others => '0');
end if;
end procedure;
begin
status.REQ_ACK <= commandStatus.REQ_ACK;
status.BUSY <= commandStatus.BUSY;
commandStatus.REQ <= status.REQ;
sim: process
variable transaction : TTransaction;
begin
MI32_DWR <= (others => '0');
MI32_ADDR <= (others => '0');
MI32_BE <= (others => '0');
MI32_RD <= '0';
MI32_WR <= '0';
loop
commandStatus.BUSY <= '0';
wait until commandStatus.REQ = '1';
commandStatus.BUSY <= '1';
commandStatus.REQ_ACK <= '1';
ReadTransaction(transaction);
SendTransaction(transaction, CLK, MI32_DWR, MI32_ADDR, MI32_BE, MI32_WR, MI32_RD, MI32_DRD, MI32_DRDY, MI32_ARDY);
WriteTransaction(transaction);
commandStatus.REQ_ACK <= '0';
commandStatus.BUSY <= '0';
end loop;
end process;
end architecture;
|
bsd-3-clause
|
cnplab/blockmon
|
fw-combo/src/CBF/CBFBase.vhd
|
1
|
12683
|
--ENTITY of filter
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.utils.ALL;
entity CBFfilter is
Port(
clock : in STD_LOGIC;
reset : in STD_LOGIC;
src_ip : in STD_LOGIC_VECTOR(31 downto 0);
dst_ip : in STD_LOGIC_VECTOR(31 downto 0);
src_port : in STD_LOGIC_VECTOR(15 downto 0);
dst_port : in STD_LOGIC_VECTOR(15 downto 0);
decrement : in STD_LOGIC;
start : in STD_LOGIC;
Address_CBF_dump : in STD_LOGIC_VECTOR (10 downto 0);
dump : in STD_LOGIC;
Threshold : in STD_LOGIC_VECTOR (31 downto 0);
Data_CBF_dump : out STD_LOGIC_VECTOR (31 downto 0);
osip : out STD_LOGIC_VECTOR(31 downto 0); -- SRC IP of the last flow over the threshold
odip : out STD_LOGIC_VECTOR(31 downto 0); -- DST IP of the last flow over the threshold
oport : out STD_LOGIC_VECTOR(31 downto 0); -- SRC & DST PORT of the last flow over the threshold
counter_item : out STD_LOGIC_VECTOR(31 downto 0);
max_sip : out STD_LOGIC_VECTOR(31 downto 0); -- SRC IP of the biggest flow
max_dip : out STD_LOGIC_VECTOR(31 downto 0); -- DST IP of the biggest flow
max_port : out STD_LOGIC_VECTOR(31 downto 0); -- SRC & DST PORT of the biggest flow
max_count : out STD_LOGIC_VECTOR(31 downto 0);
counter_overflow : out STD_LOGIC_VECTOR(31 downto 0)
);
end CBFfilter;
--ARCHITECTURE of filter
architecture Behavioral of CBFfilter is
type stato_filtro is (IDLE,CLEAN,ZERO_CLEAN,READ0,READ1,READ2,READ3,LAST_READ,WRITE0,WRITE1,DEC0,DEC1,DEC2,DUMP_STATE);
type HH is array(3 downto 0) of STD_LOGIC_VECTOR (10 downto 0);
type ADDR is array(3 downto 0) of STD_LOGIC_VECTOR (10 downto 0);
type CV is array(3 downto 0) of STD_LOGIC_VECTOR (15 downto 0);
type CBF is array(2047 downto 0) of STD_LOGIC_VECTOR (15 downto 0); --2048 count;
signal max_val : STD_LOGIC_VECTOR(15 downto 0); -- the value of the bigger flow
signal flow : STD_LOGIC_VECTOR(95 downto 0); -- the flow currently examined
signal int_counter_item : STD_LOGIC_VECTOR(31 downto 0); -- counts the total number of stored item
signal int_counter_overflow : STD_LOGIC_VECTOR(31 downto 0); -- count the number of overflows
signal H : HH; -- vector of hash values
signal addr_w : ADDR; -- vector of address to be updated
signal count_val : STD_LOGIC_VECTOR (15 downto 0); -- value of the counter for the current flow
signal countBF : CBF; -- memory of the CBF
signal Htot_UNI : STD_LOGIC_VECTOR (43 downto 0); -- total hash
signal stato : stato_filtro; -- FSM curent state
signal n_val : STD_LOGIC_VECTOR (2 downto 0); -- number of conter to be updated
signal decrementing : STD_LOGIC; -- the CBF is in decrementing
signal write_enable : STD_LOGIC; -- write to the CBF RAM
signal overflow : STD_LOGIC; -- checks if the current flow is over the threshold
signal HADDR : STD_LOGIC_VECTOR (10 downto 0); -- address for the CBF memory
signal HCOUNT_VAL_TRF : STD_LOGIC_VECTOR (15 downto 0); -- HCOUNT_VAL_ToReadFrom
signal HCOUNT_VAL_TWI : STD_LOGIC_VECTOR (15 downto 0); -- HCOUNT_VAL_ToWriteInto
signal i : integer range 0 to 2047;
signal j : integer range 0 to 2047;
signal k : integer range 0 to 2047;
signal w : integer range 0 to 3;
signal input_hash : STD_LOGIC_VECTOR(131 downto 0);
begin
counter_item<= int_counter_item;
counter_overflow<= int_counter_overflow;
input_hash<= x"f2a650193" & src_ip & dst_ip & src_port & dst_port;
-------------------------------------------
-- computing hash using ror and xor
-------------------------------------------
Htot_UNI <= (myror(input_hash(131 downto 88),11)) xor (myror(input_hash(87 downto 44), 7)) xor input_hash(43 downto 0);
--Htot_UNI <= (input_hash(131 downto 88) ror 11) xor (input_hash(87 downto 44) ror 7) xor input_hash(43 downto 0);
process (clock, reset)
begin
if reset = '1' then
flow<= (others =>'0');
elsif clock' event and clock='1' then
if start = '1' then
flow<= src_ip & dst_ip & src_port & dst_port;
end if;
end if;
end process;
process (clock, reset)
begin
if reset = '1' then
write_enable <= '0';
HCOUNT_VAL_TRF <= (others => '0');
addr_w(0) <= (others => '0');
addr_w(1) <= (others => '0');
addr_w(2) <= (others => '0');
addr_w(3) <= (others => '0');
count_val <= (others => '0');
H(0) <= (others => '0');
H(1) <= (others => '0');
H(2) <= (others => '0');
H(3) <= (others => '0');
n_val <= (others => '0');
stato <= ZERO_CLEAN;
decrementing <= '0';
overflow <= '0';
osip <= (others => '0');
odip <= (others => '0');
oport <= (others => '0');
int_counter_overflow <= (others => '0');
int_counter_item<= (others => '0');
i <= 0;
elsif clock' event and clock='1' then
if decrement='1' and stato /= CLEAN then
decrementing <= '1';
end if;
write_enable <= '0';
if start = '1' and stato /= CLEAN then
H(0) <= Htot_UNI(10 downto 0);
H(1) <= Htot_UNI(21 downto 11);
H(2) <= Htot_UNI(32 downto 22);
H(3) <= Htot_UNI(43 downto 33);
-- conta il numero di item inserite nel CBF
int_counter_item<= int_counter_item +1;
stato <= READ0;
end if;
--------------------------------------
-- Stati di reset dei contatori
--- stati ZERO_CLEAN e CLEAN
--------------------------------------
if stato = ZERO_CLEAN then --"01111"
i <= 0;
write_enable <= '1';
HCOUNT_VAL_TRF <= (others => '0');
stato <= CLEAN;
end if;
if stato = CLEAN then --"11111"
if i <= 2046 then
i <= i + 1;
HCOUNT_VAL_TRF <= (others => '0');
write_enable <= '1';
else
stato <= IDLE; --"01110"
write_enable <= '0';
i <= 0;
end if;
end if;
--------------------------------------
-- Stati di lettura dei contatori
--- stato >= 0 e <= 4
--------------------------------------
if stato = READ0 then
--HADDR <= H(0);
stato <= READ1;
end if;
if stato = READ1 then
--HADDR <= H(1);
stato <= READ2;
count_val <= HCOUNT_VAL_TWI;
addr_w(0) <= H(0);
n_val <= "001";
if(HCOUNT_VAL_TWI >= Threshold) then
overflow <= '1';
else
overflow <= '0';
end if;
end if;
if stato = READ2 then
stato <= READ3;
--HADDR <= H(2);
--count_val <= HCOUNT_VAL_TWI;
if(HCOUNT_VAL_TWI < Threshold) then
overflow <= '0';
end if;
--multiple counters with value = TWI
if count_val = HCOUNT_VAL_TWI then
addr_w(1) <= H(1);
n_val <= "010";
end if;
--this counter has the minimum value
if count_val > HCOUNT_VAL_TWI then
count_val <= HCOUNT_VAL_TWI;
addr_w(0) <= H(1);
n_val <= "001";
end if;
end if;
if stato = READ3 then
stato <= LAST_READ;
--HADDR <= H(3);
if(HCOUNT_VAL_TWI < Threshold) then
overflow <= '0';
end if;
--multiple counters with value = TWI
if count_val = HCOUNT_VAL_TWI then
if n_val = "001" then
addr_w(1) <= H(2);
n_val <= "010";
end if;
if n_val = "010" then
addr_w(2) <= H(2);
n_val <= "011";
end if;
end if;
--this counter has the minimum value
if count_val > HCOUNT_VAL_TWI then
count_val <= HCOUNT_VAL_TWI;
addr_w(0) <= H(2);
n_val <= "001";
end if;
end if;
--stop letture ed ultimo confronto
if stato = LAST_READ then
j <= 0;
stato <= WRITE0;
if(HCOUNT_VAL_TWI < Threshold) then
overflow <= '0';
end if;
--multiple counters with value = TWI
if count_val = HCOUNT_VAL_TWI then
if n_val = "001" then
addr_w(1) <= H(3);
n_val <= "010";
end if;
if n_val = "010" then
addr_w(2) <= H(3);
n_val <= "011";
end if;
if n_val = "011" then
addr_w(3) <= H(3);
n_val <= "100";
end if;
end if;
--this counter has the minimum value
if count_val > HCOUNT_VAL_TWI then
count_val <= HCOUNT_VAL_TWI;
addr_w(0) <= H(3);
n_val <= "001";
end if;
end if;
--------------------------------------
-- Stati di scrittura dei contatori
--- stato = 5,21
--------------------------------------
if stato = WRITE0 then
stato <= WRITE1; --"10101";
HCOUNT_VAL_TRF <= count_val + 1;
j <= 0; --number of counters to be incremented
write_enable <= '1';
if (count_val+1)>max_val then
max_val<=count_val+1;
max_sip<=flow(95 downto 64); --src_ip
max_dip<=flow(63 downto 32); --dst_ip;
max_port<=flow(31 downto 0); --src_port & dst_port;
max_count<=x"0000"&(count_val+1);
end if;
if(overflow = '1') then
--stato <= IDLE; -- go to IDLE only for saturate behaviour
--conta il numero di overflow
int_counter_overflow <= int_counter_overflow + 1;
-- store the flow over the threshold
osip<=flow(95 downto 64); --src_ip
odip<=flow(63 downto 32); --dst_ip;
oport<=flow(31 downto 0); --src_port & dst_port;
report "overflow src ip: " & integer'image(conv_integer(src_ip(31 downto 24))) & "." &
integer'image(conv_integer(src_ip(23 downto 16))) & "." &
integer'image(conv_integer(src_ip(15 downto 8))) & "." &
integer'image(conv_integer(src_ip(7 downto 0))) & LF ;
report "overflow dst ip: " & integer'image(conv_integer(dst_ip(31 downto 24))) & "." &
integer'image(conv_integer(dst_ip(23 downto 16))) & "." &
integer'image(conv_integer(dst_ip(15 downto 8))) & "." &
integer'image(conv_integer(dst_ip(7 downto 0))) & LF ;
report "overflow src port " & integer'image(conv_integer(src_port)) & LF ;
report "overflow dst port " & integer'image(conv_integer(dst_port)) & LF ;
--elsif(overflow=0)
-- here increment only if the value are below the Threshold, otherwise the counters saturate
--stato <= WRITE1; --"10101";
--HCOUNT_VAL_TRF <= count_val + 1;
--j <= 0; --number of counters to be incremented
--write_enable <= '1';
end if;
end if;
if stato = WRITE1 then
stato <= WRITE1;
--loop for all the conunters(n_val) to be incremented
if(j+1 < conv_integer(n_val)) then
HCOUNT_VAL_TRF <= count_val + 1;
j <= j + 1;
write_enable <= '1';
else
stato <= IDLE; --"01110";
j <= 0;
write_enable <= '0';
end if;
end if;
--IDLE STATE
if stato = IDLE then --"01110"
overflow <= '0';
write_enable <= '0';
if decrementing = '1' then
if i <= 2046 then
i <= i + 1;
stato <= DEC0;
else
decrementing<= '0';
stato <= IDLE; -- "01110";
i <= 0;
end if;
elsif dump='1' then
stato <= DUMP_STATE;
end if;
end if;
if stato = DUMP_STATE then
if dump='0' then
stato <= IDLE;
end if;
end if;
--decrementing state
if stato = DEC0 then
stato <= DEC1;
write_enable <= '0';
end if;
if stato = DEC1 then
stato <= DEC2;
if(conv_integer(HCOUNT_VAL_TWI) > 0) then
write_enable <= '1';
HCOUNT_VAL_TRF <= HCOUNT_VAL_TWI - 1;
end if;
end if;
--needed to write decremented value on the CBF
if stato = DEC2 then
write_enable <= '0';
stato <= IDLE; -- "01110";
end if;
end if;
end process;
HADDR <=H(0) when stato=READ0 else
H(1) when stato=READ1 else
H(2) when stato=READ2 else
H(3) when stato=READ3 else
addr_w(j) when stato=LAST_READ else
addr_w(j) when stato=WRITE0 else
addr_w(j) when stato=WRITE1 else
Address_CBF_dump when stato=DUMP_STATE else
Address_CBF_dump when stato=IDLE and dump='1' else -- hack:when dump=1 and IDLE risparmia un cilo ci clock
conv_std_logic_vector(i,11);
--with stato select
--HADDR <=H(0) when READ0,
--H(1) when READ1,
--H(2) when READ2,
--H(3) when READ3,
--addr_w(j) when LAST_READ,
--addr_w(j) when WRITE0,
--addr_w(j) when WRITE1,
--Address_CBF_dump when DUMP_STATE, -- hack:when dump=1 and IDLE risparmia un cilo ci clock
--conv_std_logic_vector(i,11) when others;
process(clock)
begin
if clock'event and clock = '1' then
HCOUNT_VAL_TWI <= countBF(conv_integer(HADDR));
if (write_enable = '1') then
countBF(conv_integer(HADDR)) <= HCOUNT_VAL_TRF;
HCOUNT_VAL_TWI <= HCOUNT_VAL_TRF; -- needed to synth block RAM
end if;
end if;
end process;
------------------------------
-- forniamo il valore memorizzato dal CBF per l'operazione di DUMP
Data_CBF_dump<= x"0000" & HCOUNT_VAL_TWI;
end Behavioral;
|
bsd-3-clause
|
cnplab/blockmon
|
fw-combo/src/IPFIX/combov2_user_const.vhd
|
1
|
5818
|
-- -----------------------------------------------------------------------
--
-- Company: INVEA-TECH a.s.
--
-- Project: IPFIX design
--
-- -----------------------------------------------------------------------
--
-- (c) Copyright 2011 INVEA-TECH a.s.
-- All rights reserved.
--
-- Please review the terms of the license agreement before using this
-- file. If you are not an authorized user, please destroy this
-- source code file and notify INVEA-TECH a.s. immediately that you
-- inadvertently received an unauthorized copy.
--
-- -----------------------------------------------------------------------
--
-- combov2_user_const.vhd: User constants for NetCOPE on ComboV2
-- Copyright (C) 2008 CESNET
-- Author(s): Viktor Pus <[email protected]>
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in
-- the documentation and/or other materials provided with the
-- distribution.
-- 3. Neither the name of the Company nor the names of its contributors
-- may be used to endorse or promote products derived from this
-- software without specific prior written permission.
--
-- This software is provided ``as is'', and any express or implied
-- warranties, including, but not limited to, the implied warranties of
-- merchantability and fitness for a particular purpose are disclaimed.
-- In no event shall the company or contributors be liable for any
-- direct, indirect, incidental, special, exemplary, or consequential
-- damages (including, but not limited to, procurement of substitute
-- goods or services; loss of use, data, or profits; or business
-- interruption) however caused and on any theory of liability, whether
-- in contract, strict liability, or tort (including negligence or
-- otherwise) arising in any way out of the use of this software, even
-- if advised of the possibility of such damage.
--
-- $Id$
--
library IEEE;
use IEEE.std_logic_1164.all;
package combov2_user_const is
-- -------------------------------------------------------------------------
-- constant PCIE_EP_IFC_125 : boolean := true;-- true=125 MHz endpoint, false=250 MHz -- now this is obsolete
-- -------------------------------------------------------------------------
-- Clock frequencies setting
-- -------------------------------------------------------------------------
constant CLK_MULT : integer := 9; -- Fvco = 62.5 MHz x CLK_MULT
constant CLK_ICS_DIV : integer := 3; -- CLK_ICS freq. = Fvco / CLK_ICS_DIV
constant CLK_USER0_DIV : integer := 5; -- CLK_USER0 freq. = Fvco / CLK_USER0_DIV
constant CLK_USER1_DIV : integer := 5; -- CLK_USER1 freq. = Fvco / CLK_USER1_DIV
constant CLK_USER2_DIV : integer := 5; -- CLK_USER2 freq. = Fvco / CLK_USER2_DIV
constant CLK_USER3_DIV : integer := 5; -- CLK_USER3 freq. = Fvco / CLK_USER3_DIV
constant CLK_USER4_DIV : integer := 5; -- CLK_USER4 freq. = Fvco / CLK_USER4_DIV
-- -------------------------------------------------------------------------
-- Design identification ---------------------------------------------------
constant ID_PROJECT : std_logic_vector( 15 downto 0):= X"F101";
constant ID_SW_MAJOR : std_logic_vector( 7 downto 0):= X"03";
constant ID_SW_MINOR : std_logic_vector( 7 downto 0):= X"0C";
constant ID_HW_MAJOR : std_logic_vector( 15 downto 0):= X"0007";
constant ID_HW_MINOR : std_logic_vector( 15 downto 0):= X"0000";
-- F l e x i b l e _ F l o w M o n\0
constant ID_PROJECT_TEXT : std_logic_vector(255 downto 0) :=
X"466C657869626C655F466C6F774D6F6E00000000000000000000000000000000";
constant ID_TX_CHANNELS : std_logic_vector( 7 downto 0):= X"00";
constant ID_RX_CHANNELS : std_logic_vector( 7 downto 0):= X"08";
-- -------------------------------------------------------------------------
-- Network Module setting (constant INBANDFCS) is done in NetCOPE's network module
-- -------------------------------------------------------------------------
-- DMA Module setting
-- straight zero copy DMA - Non-generic version
-- constant DMA_TYPE : String := "SZE";
-- straight zero copy DMA - Generic version
constant DMA_TYPE : String := "GEN";
-- packet DMA through linux kernel stack
-- constant DMA_TYPE : String := "PAC";
-- -------------------------------------------------------------------------
-- Timestamp unit setting
-- Set to false if you don't need timestamps
-- Synchronize your choice with ../top/combov2/Makefile (USE_TIMESTAMP)
constant TIMESTAMP_UNIT : boolean := true;
-- constant TIMESTAMP_UNIT : boolean := false;
-- -------------------------------------------------------------------------
-- Support for JUMBO packets
-- (un)comment all three lines together
-- Synchronize your choice with ../top/combov2/Makefile (JUMBO)
constant JUMBO : boolean := true;
constant MAX_MTU_RX : std_logic_vector(31 downto 0) := X"00003FE0";
constant MAX_MTU_TX : std_logic_vector(31 downto 0) := X"00003FE0";
-- constant JUMBO : boolean := false;
-- constant MAX_MTU_RX : std_logic_vector(31 downto 0) := X"00000FE0";
-- constant MAX_MTU_TX : std_logic_vector(31 downto 0) := X"00000FE0";
end combov2_user_const;
package body combov2_user_const is
end combov2_user_const;
|
bsd-3-clause
|
cnplab/blockmon
|
fw-combo/src/netcope-sim/models/fl_bfm.vhd
|
1
|
10462
|
-- -----------------------------------------------------------------------
--
-- Company: INVEA-TECH a.s.
--
-- Project: IPFIX design
--
-- -----------------------------------------------------------------------
--
-- (c) Copyright 2011 INVEA-TECH a.s.
-- All rights reserved.
--
-- Please review the terms of the license agreement before using this
-- file. If you are not an authorized user, please destroy this
-- source code file and notify INVEA-TECH a.s. immediately that you
-- inadvertently received an unauthorized copy.
--
-- -----------------------------------------------------------------------
--
--
-- fl_bfm.vhd: Simulation component for Frame link
-- Copyright (C) 2006 CESNET
-- Author(s): Vlastimil Kosar <[email protected]>
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in
-- the documentation and/or other materials provided with the
-- distribution.
-- 3. Neither the name of the Company nor the names of its contributors
-- may be used to endorse or promote products derived from this
-- software without specific prior written permission.
--
-- This software is provided ``as is'', and any express or implied
-- warranties, including, but not limited to, the implied warranties of
-- merchantability and fitness for a particular purpose are disclaimed.
-- In no event shall the company or contributors be liable for any
-- direct, indirect, incidental, special, exemplary, or consequential
-- damages (including, but not limited to, procurement of substitute
-- goods or services; loss of use, data, or profits; or business
-- interruption) however caused and on any theory of liability, whether
-- in contract, strict liability, or tort (including negligence or
-- otherwise) arising in any way out of the use of this software, even
-- if advised of the possibility of such damage.
--
-- $Id: fl_bfm.vhd 12021 2011-04-15 08:23:45Z kastovsky $
--
-- TODO:
--
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_textio.all;
use ieee.numeric_std.all;
use std.textio.all;
use work.fl_pkg.all;
use work.fl_bfm_rdy_pkg.all;
use work.FL_BFM_pkg.all;
-- library containing log2 function
use work.math_pack.all;
-- ----------------------------------------------------------------------------
-- Entity declaration
-- ----------------------------------------------------------------------------
entity FL_BFM is
generic(
-- FrameLink data bus width
-- only 8, 16, 32, 64 and 128 bit fl bus supported
DATA_WIDTH : integer;
-- uniqe identity of FL_BFM as one of 16 posible FL_BFMs in design
FL_BFM_ID : integer
);
port(
-- Common interface
RESET : in std_logic;
CLK : in std_logic;
-- Frame link output Interface
TX_DATA : out std_logic_vector(DATA_WIDTH-1 downto 0);
TX_REM : out std_logic_vector(log2(DATA_WIDTH/8)-1 downto 0);
TX_SOF_N : out std_logic;
TX_EOF_N : out std_logic;
TX_SOP_N : out std_logic;
TX_EOP_N : out std_logic;
TX_SRC_RDY_N : out std_logic;
TX_DST_RDY_N : in std_logic
);
end entity FL_BFM;
-- ----------------------------------------------------------------------------
-- Architecture declaration
-- ----------------------------------------------------------------------------
architecture FL_BFM_ARCH of FL_BFM is
SHARED VARIABLE Cmd : CmdTypeItem;
signal test: CmdTypeItem;
signal SRC_RDY_N : std_logic;
signal SRC_DRIVE : std_logic;
signal flCmd : flCmdTypeItem := ('0','Z','Z');
PROCEDURE Write(variable trans : IN CmdTypeItem;
signal CLK : IN std_logic;
signal DATA : OUT std_logic_vector(DATA_WIDTH-1 downto 0);
signal DREM : OUT std_logic_vector(log2(DATA_WIDTH/8)-1 downto 0);
signal SOF_N : OUT std_logic;
signal SOP_N : OUT std_logic;
signal EOP_N : OUT std_logic;
signal EOF_N : OUT std_logic;
signal SRC_RDY_N : IN std_logic;
signal DST_RDY_N : IN std_logic;
signal Enable : OUT std_logic) IS
variable index : integer;
variable byteCount : std_logic_vector(log2(DATA_WIDTH/8)-1 downto 0);
variable i : integer;
variable maxRem : std_logic_vector(log2(DATA_WIDTH/8)-1 downto 0);
BEGIN
Enable <= '0';
maxRem := (others => '1');
index := 0;
wait until (CLK'event and CLK='1' and SRC_RDY_N = '0'); --and DST_RDY_N='0');
Enable <= '1';
while (index <= trans.Length) loop
DATA(7 downto 0) <= trans.Data(index).Data;
byteCount := (others => '0');
i:= 1;
if (trans.Data(index).StartControl = SOF) then
SOF_N <= '0';
SOP_N <= '0';
elsif (trans.Data(index).StartControl = SOP) then
SOF_N <= '1';
SOP_N <= '0';
elsif (trans.Data(index).StartControl = NOP) then
SOF_N <= '1';
SOP_N <= '1';
end if;
if (DATA_WIDTH > 8) then
if (trans.Data(index).EndControl = NOP) then
while ((index + 1 <= trans.Length) and byteCount < maxRem) loop
index := index + 1;
byteCount := byteCount + '1';
i := i + 1;
DATA((i * 8) - 1 downto (i - 1) * 8) <= trans.Data(index).Data;
if ((trans.Data(index).EndControl = EOF) or (trans.Data(index).EndControl = EOP)) then
exit;
end if;
end loop;
end if;
end if;
if (trans.Data(index).EndControl = EOF) then
EOF_N <= '0';
EOP_N <= '0';
elsif (trans.Data(index).EndControl = EOP) then
EOF_N <= '1';
EOP_N <= '0';
elsif(trans.Data(index).EndControl = NOP) then
EOF_N <= '1';
EOP_N <= '1';
end if;
DREM <= byteCount;
wait until (CLK'event and CLK='1' and SRC_RDY_N = '0' and DST_RDY_N='0');
index := index + 1;
end loop;
Enable <= '0';
END Write;
begin
gen0: if (FL_BFM_ID = 0) generate
flCmd_0.Ack <= flCmd.Ack;
flCmd_0.ReqAck <= flCmd.ReqAck;
flCmd.Req <= flCmd_0.Req;
end generate gen0;
gen1: if (FL_BFM_ID = 1) generate
flCmd_1.Ack <= flCmd.Ack;
flCmd_1.ReqAck <= flCmd.ReqAck;
flCmd.Req <= flCmd_1.Req;
end generate gen1;
gen2: if (FL_BFM_ID = 2) generate
flCmd_2.Ack <= flCmd.Ack;
flCmd_2.ReqAck <= flCmd.ReqAck;
flCmd.Req <= flCmd_2.Req;
end generate gen2;
gen3: if (FL_BFM_ID = 3) generate
flCmd_3.Ack <= flCmd.Ack;
flCmd_3.ReqAck <= flCmd.ReqAck;
flCmd.Req <= flCmd_3.Req;
end generate gen3;
gen4: if (FL_BFM_ID = 4) generate
flCmd_4.Ack <= flCmd.Ack;
flCmd_4.ReqAck <= flCmd.ReqAck;
flCmd.Req <= flCmd_4.Req;
end generate gen4;
gen5: if (FL_BFM_ID = 5) generate
flCmd_5.Ack <= flCmd.Ack;
flCmd_5.ReqAck <= flCmd.ReqAck;
flCmd.Req <= flCmd_5.Req;
end generate gen5;
gen6: if (FL_BFM_ID = 6) generate
flCmd_6.Ack <= flCmd.Ack;
flCmd_6.ReqAck <= flCmd.ReqAck;
flCmd.Req <= flCmd_6.Req;
end generate gen6;
gen7: if (FL_BFM_ID = 7) generate
flCmd_7.Ack <= flCmd.Ack;
flCmd_7.ReqAck <= flCmd.ReqAck;
flCmd.Req <= flCmd_7.Req;
end generate gen7;
gen8: if (FL_BFM_ID = 8) generate
flCmd_8.Ack <= flCmd.Ack;
flCmd_8.ReqAck <= flCmd.ReqAck;
flCmd.Req <= flCmd_8.Req;
end generate gen8;
gen9: if (FL_BFM_ID = 9) generate
flCmd_9.Ack <= flCmd.Ack;
flCmd_9.ReqAck <= flCmd.ReqAck;
flCmd.Req <= flCmd_9.Req;
end generate gen9;
genA: if (FL_BFM_ID = 10) generate
flCmd_A.Ack <= flCmd.Ack;
flCmd_A.ReqAck <= flCmd.ReqAck;
flCmd.Req <= flCmd_A.Req;
end generate genA;
genB: if (FL_BFM_ID = 11) generate
flCmd_B.Ack <= flCmd.Ack;
flCmd_B.ReqAck <= flCmd.ReqAck;
flCmd.Req <= flCmd_B.Req;
end generate genB;
genC: if (FL_BFM_ID = 12) generate
flCmd_C.Ack <= flCmd.Ack;
flCmd_C.ReqAck <= flCmd.ReqAck;
flCmd.Req <= flCmd_C.Req;
end generate genC;
genD: if (FL_BFM_ID = 13) generate
flCmd_D.Ack <= flCmd.Ack;
flCmd_D.ReqAck <= flCmd.ReqAck;
flCmd.Req <= flCmd_D.Req;
end generate genD;
genE: if (FL_BFM_ID = 14) generate
flCmd_E.Ack <= flCmd.Ack;
flCmd_E.ReqAck <= flCmd.ReqAck;
flCmd.Req <= flCmd_E.Req;
end generate genE;
genF: if (FL_BFM_ID = 15) generate
flCmd_F.Ack <= flCmd.Ack;
flCmd_F.ReqAck <= flCmd.ReqAck;
flCmd.Req <= flCmd_F.Req;
end generate genF;
SEND:process
begin
TX_DATA <= (others => '0');
TX_REM <= (others => '0');
TX_SOF_N <= '1';
TX_EOF_N <= '1';
TX_SOP_N <= '1';
TX_EOP_N <= '1';
LOOP
flCmd.Ack <= '0';
flCmd.ReqAck <= '0';
SRC_DRIVE <= '0';
-- Get Command
WHILE (flCmd.Req = '0') LOOP
WAIT UNTIL (flCmd.Req = '1');
END LOOP;
-- Send Request Acknowledge
flCmd.ReqAck <= NOT(flCmd.ReqAck);
-- Wait for Reqest Deasert
WAIT ON flCmd.Req;
ReadCommand(Cmd, FL_BFM_ID);
test<=Cmd;
--SRC_DRIVE <= '1';
Write(Cmd, CLK, TX_DATA, TX_REM, TX_SOF_N, TX_SOP_N, TX_EOP_N, TX_EOF_N, SRC_RDY_N, TX_DST_RDY_N, SRC_DRIVE);
SRC_DRIVE <= '0';
-- Send Command done
flCmd.Ack <= '1';
wait until (CLK'event and CLK='1');
end loop;
end process;
-- Drive SRC_RDY_N ---------------------------------------------------------------
DRIVE_SRC_RDY_N: PROCESS
BEGIN
LOOP
IF (Cmd.RDYDriver = EVER) then
DriveRdyNAll(CLK, SRC_RDY_N);
elsif (Cmd.RDYDriver = ONOFF) then
DriveRdyN50_50(CLK, SRC_RDY_N);
elsif (Cmd.RDYDriver = RND) then
DriveRdyNRnd(CLK, SRC_RDY_N);
end if;
END LOOP;
END PROCESS;
TX_SRC_RDY_N <= SRC_RDY_N or not SRC_DRIVE;
end architecture FL_BFM_ARCH;
|
bsd-3-clause
|
thelonious/display4
|
rotary.vhd
|
1
|
1469
|
--
-- Copyright 2011, Kevin Lindsey
-- See LICENSE file for licensing information
--
-- Based on Ben Jordon's code in this forum post:
-- http://forum.allaboutcircuits.com/showthread.php?t=23344
--
library ieee;
use ieee.std_logic_1164.all;
entity Rotary is
port(
clock: in std_logic;
A: in std_logic;
B: in std_logic;
inc: out std_logic;
dec: out std_logic
);
end Rotary;
architecture behavioral of Rotary is
signal prevA, prevB: std_logic;
signal currA, currB: std_logic;
begin
read_rotary: process(clock)
begin
if clock'event and clock = '1' then
prevA <= currA;
prevB <= currB;
currA <= A;
currB <= B;
if prevA = '0' and currA = '1' then -- a rising
if currB = '1' then
inc <= '0';
dec <= '1';
elsif currB = '0' then
inc <= '1';
dec <= '0';
end if;
elsif prevA = '1' and currA = '0' then -- a falling
if currB = '1' then
inc <= '1';
dec <= '0';
elsif currB = '0' then
inc <= '0';
dec <= '1';
end if;
elsif prevB = '0' and currB = '1' then -- b rising
if currA = '1' then
inc <= '1';
dec <= '0';
elsif currA = '0' then
inc <= '0';
dec <= '1';
end if;
elsif prevB = '1' and currB = '0' then -- b falling
if currA = '1' then
inc <= '0';
dec <= '1';
elsif currA = '0' then
inc <= '1';
dec <= '0';
end if;
else
inc <= '0';
dec <= '0';
end if;
end if;
end process;
end behavioral;
|
bsd-3-clause
|
thelonious/display4
|
display_counter.vhd
|
1
|
4322
|
--
-- Copyright 2011, Kevin Lindsey
-- See LICENSE file for licensing information
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity DisplayCounter is
port(
-- main clock
clock: in std_logic;
-- rotary push button
A, B, PB: in std_logic;
-- 4-digit 7-segment display
segments: out std_logic_vector(6 downto 0);
dp: out std_logic;
sel: out std_logic_vector(3 downto 0)
);
end DisplayCounter;
architecture Behavioral of DisplayCounter is
-- component for rotary-only support of rotary switch
component Rotary is
port(
clock: in std_logic;
A: in std_logic;
B: in std_logic;
inc: out std_logic;
dec: out std_logic
);
end component;
-- component to display 4 7-segment digits
component Display4 is
generic(
DIGIT_COUNT: positive
);
port(
clock: in std_logic;
data_write_enable: in std_logic;
data: in std_logic_vector(DIGIT_COUNT * 4 - 1 downto 0);
dps: in std_logic_vector(DIGIT_COUNT - 1 downto 0);
segments: out std_logic_vector(6 downto 0);
dp: out std_logic;
sel: out std_logic_vector(DIGIT_COUNT - 1 downto 0)
);
end component;
-- component to debounce rotary push button
component Debouncer is
port(
clock: in std_logic;
reset: in std_logic;
d_in: in std_logic;
d_out: out std_logic
);
end component;
-- individual digit data and an aggregate of those values
subtype digitType is std_logic_vector(3 downto 0);
type digitTypes is array(0 to 3) of digitType;
signal digits: digitTypes;
signal display_data: std_logic_vector(15 downto 0);
-- signals from rotary indicating rotation direction
signal up, down: std_logic;
-- signals to write current display data
signal enable_write: std_logic := '1';
signal active_digit: std_logic_vector(3 downto 0) := (others => '0');
-- state tracking to detect push button edges
signal last_debounced: std_logic := '0';
signal current_debounced: std_logic := '0';
signal PB_debounced: std_logic := '0';
begin
-- create rotary decoder
r: Rotary
port map(
clock => clock,
A => A,
B => B,
inc => up,
dec => down
);
-- create 4-digit display
d4: Display4
generic map(
DIGIT_COUNT => 4
)
port map(
clock => clock,
data_write_enable => enable_write,
data => display_data,
dps => active_digit,
segments => segments,
dp => dp,
sel => sel
);
-- create button debouncer
db: Debouncer
port map(
clock => clock,
reset => PB,
d_in => not PB,
d_out => PB_debounced
);
-- concatenate individual digits into a single 16-bit value
update_display: process(clock, digits)
begin
if clock'event and clock = '1' then
display_data <= digits(0) & digits(1) & digits(2) & digits(3);
end if;
end process;
-- update current digit based on rotary output
-- update active digit which turns on that digits decimal point. Normally,
-- I would separate the logic for rotary and the push button into separate
-- processes, but since both require activation of enable_write, I decided
-- to combine both into a single process
update_counter: process(clock, up, down, PB, active_digit)
variable digit_index: integer range 0 to 3 := 0;
begin
if clock'event and clock = '1' then
-- shift last value and current value for edge detection
last_debounced <= current_debounced;
current_debounced <= PB_debounced;
-- handle increment/decrement if a digit is active; otherwise,
-- handle possible postive edge of push button
if down = '1' and active_digit /= "0000" then
digits(digit_index) <= digits(digit_index) - 1;
enable_write <= '1';
elsif up = '1' and active_digit /= "0000" then
digits(digit_index) <= digits(digit_index) + 1;
enable_write <= '1';
elsif last_debounced = '0' and current_debounced = '1' then
case active_digit is
when "0000" => active_digit <= "0001"; digit_index := 0;
when "0001" => active_digit <= "0010"; digit_index := 1;
when "0010" => active_digit <= "0100"; digit_index := 2;
when "0100" => active_digit <= "1000"; digit_index := 3;
when "1000" => active_digit <= "0000"; digit_index := 0;
when others => active_digit <= "0000"; digit_index := 0;
end case;
enable_write <= '1';
else
enable_write <= '0';
end if;
end if;
end process;
end Behavioral;
|
bsd-3-clause
|
yunqu/PYNQ
|
boards/ip/rgb2dvi_v1_2/src/ClockGen.vhd
|
9
|
8885
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11/03/2014 06:27:16 PM
-- Design Name:
-- Module Name: ClockGen - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity ClockGen is
Generic (
kClkRange : natural := 1; -- MULT_F = kClkRange*5 (choose >=120MHz=1, >=60MHz=2, >=40MHz=3, >=30MHz=4, >=25MHz=5
kClkPrimitive : string := "MMCM"); -- "MMCM" or "PLL" to instantiate, if kGenerateSerialClk true
Port (
PixelClkIn : in STD_LOGIC;
PixelClkOut : out STD_LOGIC;
SerialClk : out STD_LOGIC;
aRst : in STD_LOGIC;
aLocked : out STD_LOGIC);
end ClockGen;
architecture Behavioral of ClockGen is
component SyncAsync is
Generic (
kResetTo : std_logic := '0'; --value when reset and upon init
kStages : natural := 2); --double sync by default
Port (
aReset : in STD_LOGIC; -- active-high asynchronous reset
aIn : in STD_LOGIC;
OutClk : in STD_LOGIC;
oOut : out STD_LOGIC);
end component SyncAsync;
component ResetBridge is
Generic (
kPolarity : std_logic := '1');
Port (
aRst : in STD_LOGIC; -- asynchronous reset; active-high, if kPolarity=1
OutClk : in STD_LOGIC;
oRst : out STD_LOGIC);
end component ResetBridge;
signal PixelClkInX1, PixelClkInX5, FeedbackClk : std_logic;
signal aLocked_int, pLocked, pRst, pLockWasLost : std_logic;
signal pLocked_q : std_logic_vector(2 downto 0) := (others => '1');
begin
-- We need a reset bridge to use the asynchronous aRst signal to reset our circuitry
-- and decrease the chance of metastability. The signal pRst can be used as
-- asynchronous reset for any flip-flop in the PixelClkIn domain, since it will be de-asserted
-- synchronously.
LockLostReset: ResetBridge
generic map (
kPolarity => '1')
port map (
aRst => aRst,
OutClk => PixelClkIn,
oRst => pRst);
PLL_LockSyncAsync: SyncAsync
port map (
aReset => '0',
aIn => aLocked_int,
OutClk => PixelClkIn,
oOut => pLocked);
PLL_LockLostDetect: process(PixelClkIn)
begin
if (pRst = '1') then
pLocked_q <= (others => '1');
pLockWasLost <= '1';
elsif Rising_Edge(PixelClkIn) then
pLocked_q <= pLocked_q(pLocked_q'high-1 downto 0) & pLocked;
pLockWasLost <= (not pLocked_q(0) or not pLocked_q(1)) and pLocked_q(2); --two-pulse
end if;
end process;
-- The TMDS Clk channel carries a character-rate frequency reference
-- In a single Clk period a whole character (10 bits) is transmitted
-- on each data channel. For deserialization of data channel a faster,
-- serial clock needs to be generated. In 7-series architecture an
-- OSERDESE2 primitive doing a 10:1 deserialization in DDR mode needs
-- a fast 5x clock and a slow 1x clock. These two clocks are generated
-- below with an MMCME2_ADV/PLLE2_ADV.
-- Caveats:
-- 1. The primitive uses a multiply-by-5 and divide-by-1 to generate
-- a 5x fast clock.
-- While changes in the frequency of the TMDS Clk are tracked by the
-- MMCM, for some TMDS Clk frequencies the datasheet specs for the VCO
-- frequency limits are not met. In other words, there is no single
-- set of MMCM multiply and divide values that can work for the whole
-- range of resolutions and pixel clock frequencies.
-- For example: MMCM_FVCOMIN = 600 MHz
-- MMCM_FVCOMAX = 1200 MHz for Artix-7 -1 speed grade
-- while FVCO = FIN * MULT_F
-- The TMDS Clk for 720p resolution in 74.25 MHz
-- FVCO = 74.25 * 10 = 742.5 MHz, which is between FVCOMIN and FVCOMAX
-- However, the TMDS Clk for 1080p resolution in 148.5 MHz
-- FVCO = 148.5 * 10 = 1480 MHZ, which is above FVCOMAX
-- In the latter case, MULT_F = 5, DIVIDE_F = 5, DIVIDE = 1 would result
-- in a correct VCO frequency, while still generating 5x and 1x clocks
-- 2. The MMCM+BUFIO+BUFR combination results in the highest possible
-- frequencies. PLLE2_ADV could work only with BUFGs, which limits
-- the maximum achievable frequency. The reason is that only the MMCM
-- has dedicated route to BUFIO.
-- If a PLLE2_ADV with BUFGs are used a second CLKOUTx can be used to
-- generate the 1x clock.
GenMMCM: if kClkPrimitive = "MMCM" generate
DVI_ClkGenerator: MMCME2_ADV
generic map
(BANDWIDTH => "OPTIMIZED",
CLKOUT4_CASCADE => FALSE,
COMPENSATION => "ZHOLD",
STARTUP_WAIT => FALSE,
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT_F => real(kClkRange) * 5.0,
CLKFBOUT_PHASE => 0.000,
CLKFBOUT_USE_FINE_PS => FALSE,
CLKOUT0_DIVIDE_F => real(kClkRange) * 1.0,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT0_USE_FINE_PS => FALSE,
CLKOUT1_DIVIDE => kClkRange * 5,
CLKOUT1_DUTY_CYCLE => 0.5,
CLKOUT1_PHASE => 0.0,
CLKOUT1_USE_FINE_PS => FALSE,
CLKIN1_PERIOD => real(kClkRange) * 6.0,
REF_JITTER1 => 0.010)
port map
-- Output clocks
(
CLKFBOUT => FeedbackClk,
CLKFBOUTB => open,
CLKOUT0 => PixelClkInX5,
CLKOUT0B => open,
CLKOUT1 => PixelClkInX1,
CLKOUT1B => open,
CLKOUT2 => open,
CLKOUT2B => open,
CLKOUT3 => open,
CLKOUT3B => open,
CLKOUT4 => open,
CLKOUT5 => open,
CLKOUT6 => open,
-- Input clock control
CLKFBIN => FeedbackClk,
CLKIN1 => PixelClkIn,
CLKIN2 => '0',
-- Tied to always select the primary input clock
CLKINSEL => '1',
-- Ports for dynamic reconfiguration
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DO => open,
DRDY => open,
DWE => '0',
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => aLocked_int,
CLKINSTOPPED => open,
CLKFBSTOPPED => open,
PWRDWN => '0',
RST => pLockWasLost);
end generate;
GenPLL: if kClkPrimitive /= "MMCM" generate
DVI_ClkGenerator: PLLE2_ADV
generic map (
BANDWIDTH => "OPTIMIZED",
CLKFBOUT_MULT => (kClkRange + 1) * 5,
CLKFBOUT_PHASE => 0.000,
CLKIN1_PERIOD => real(kClkRange) * 6.25,
COMPENSATION => "ZHOLD",
DIVCLK_DIVIDE => 1,
REF_JITTER1 => 0.010,
STARTUP_WAIT => "FALSE",
CLKOUT0_DIVIDE => (kClkRange + 1) * 1,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => (kClkRange + 1) * 5,
CLKOUT1_DUTY_CYCLE => 0.5,
CLKOUT1_PHASE => 0.0)
port map
-- Output clocks
(
CLKFBOUT => FeedbackClk,
CLKOUT0 => PixelClkInX5,
CLKOUT1 => PixelClkInX1,
CLKOUT2 => open,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
-- Input clock control
CLKFBIN => FeedbackClk,
CLKIN1 => PixelClkIn,
CLKIN2 => '0',
-- Tied to always select the primary input clock
CLKINSEL => '1',
-- Ports for dynamic reconfiguration
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DO => open,
DRDY => open,
DWE => '0',
-- Other control and status signals
LOCKED => aLocked_int,
PWRDWN => '0',
RST => pLockWasLost);
end generate;
--No buffering used
--These clocks will only drive the OSERDESE2 primitives
SerialClk <= PixelClkInX5;
PixelClkOut <= PixelClkInX1;
aLocked <= aLocked_int;
end Behavioral;
|
bsd-3-clause
|
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