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lowRISC/greth-library
|
greth_library/techmap/bufg/bufgmux_micron180.vhd
|
3
|
671
|
----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov
--! @brief Clock multiplexer with buffered output for Mikron 180 nm.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity bufgmux_micron180 is
port (
O : out std_ulogic;
I1 : in std_ulogic;
I2 : in std_ulogic;
S : in std_ulogic
);
end;
architecture rtl of bufgmux_micron180 is
begin
O <= I1 when S = '0' else I2;
-- TODO: clock buffer
end;
|
bsd-2-clause
|
lowRISC/greth-library
|
greth_library/rocketlib/tilelink/htifserdes.vhd
|
2
|
5057
|
-----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - [email protected]
--! @brief Implementation of the 'htifserdes' module.
--! @details Used only for system with enabled L2-cache.
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library commonlib;
use commonlib.types_common.all;
library rocketlib;
use rocketlib.types_rocket.all;
--! @brief Uncore messages serializer/deserializer.
--! @details There is implemented logic of conversion of the 128-bit
--! 'Uncore' messages on chunks of HTIF_WIDTH bits size (default 16
--! bits). Message is formed using HostIO signal request.
entity htif_serdes is
generic (
core_idx : integer := 0
);
port (
clk : in std_logic;
nrst : in std_logic;
hostoi : in host_out_type;
hostio : out host_in_type;
srdi : in htif_serdes_in_type;
srdo : out htif_serdes_out_type
);
end;
architecture arch_htif_serdes of htif_serdes is
--! @name Uncore message IDs specific for HostIO interface.
--! @brief Used See htif.scala, class Htif, line about 105.
--! @{
--! Reading from physical memory. Not used in this SOC.
constant HTIF_CMD_READ_MEMORY : std_logic_vector(3 downto 0) := X"0";
--! Writting into physical memory. Not used in this SOC.
constant HTIF_CMD_WRITE_MEMORY : std_logic_vector(3 downto 0) := X"1";
--! Reading Control Register (CSR).
constant HTIF_CMD_READ_CONTROL_REG : std_logic_vector(3 downto 0) := X"2";
--! Writting Control Register (CSR).
constant HTIF_CMD_WRITE_CONTROL_REG : std_logic_vector(3 downto 0) := X"3";
--! Handshake success.
constant HTIF_CMD_ACK : std_logic_vector(3 downto 0) := X"4";
--! Handshake error.
constant HTIF_CMD_NACK : std_logic_vector(3 downto 0) := X"5";
--! @}
constant HTIF_DATA_EMPTY :
std_logic_vector(HTIF_WIDTH-1 downto 0) := (others => '1');
type state_type is (wait_cmd, transmit, response, resp_ready);
type registers is record
state : state_type;
muxCnt : integer range 0 to 128/HTIF_WIDTH + 1;
cmd : std_logic_vector(127 downto 0);
seqno : std_logic_vector(7 downto 0);
end record;
signal r, rin: registers;
function functionMakeMessage( r : registers;
hst : host_out_type)
return std_logic_vector is
variable ret : std_logic_vector(127 downto 0);
begin
ret(127 downto 64) := hst.csr_req_bits_data;
ret(63 downto 44) := conv_std_logic_vector(core_idx, 20);
ret(43 downto 36) := X"00";
ret(35 downto 24) := hst.csr_req_bits_addr;
ret(23 downto 16) := r.seqno;
ret(15 downto 4) := X"001"; -- total number of words
if hst.csr_req_bits_rw = '1' then
ret(3 downto 0) := HTIF_CMD_WRITE_CONTROL_REG;
else
ret(3 downto 0) := HTIF_CMD_READ_CONTROL_REG;
end if;
return ret;
end;
begin
comblogic : process(hostoi, srdi, r)
variable v : registers;
variable vo : host_in_type;
begin
v := r;
vo.grant := (others => '0');
vo.csr_req_ready := '0';
vo.csr_resp_valid := '0';
vo.csr_resp_bits := (others => '0');
vo.debug_stats_csr := '0';
case r.state is
when wait_cmd =>
vo.csr_req_ready := '1';
if hostoi.csr_req_valid = '1' then
v.state := transmit;
v.seqno := r.seqno + 1;
v.cmd := functionMakeMessage(r, hostoi);
end if;
srdo.valid <= '0';
srdo.ready <= '0';
srdo.bits <= (others => '0');
when transmit =>
--! Multiplexer of the command into HTIF bus
if srdi.ready = '1' then
v.muxCnt := r.muxCnt + 1;
end if;
v.cmd := HTIF_DATA_EMPTY & r.cmd(127 downto HTIF_WIDTH);
if r.muxCnt = (128/HTIF_WIDTH) - 1 then
v.state := response;
v.muxCnt := 0;
end if;
srdo.valid <= '1';
srdo.ready <= '0';
srdo.bits <= r.cmd(HTIF_WIDTH-1 downto 0);
when response =>
if srdi.valid = '1' then
v.muxCnt := r.muxCnt + 1;
v.cmd := srdi.bits & r.cmd(127 downto HTIF_WIDTH);
if r.muxCnt = (128/HTIF_WIDTH) - 1 then
v.state := resp_ready;
end if;
end if;
srdo.valid <= '0';
srdo.ready <= '1';
srdo.bits <= (others => '0');
when resp_ready =>
if hostoi.csr_resp_ready = '1' then
v.state := wait_cmd;
end if;
srdo.valid <= '0';
srdo.ready <= '0';
srdo.bits <= (others => '0');
vo.csr_resp_valid := '1';
vo.csr_resp_bits := r.cmd(127 downto 64);
when others =>
end case;
rin <= v;
hostio <= vo;
end process;
-- registers:
regs : process(clk, nrst)
begin
if nrst = '0' then
r.state <= wait_cmd;
r.muxCnt <= 0;
r.cmd <= (others => '0');
r.seqno <= X"01";
elsif rising_edge(clk) then
r <= rin;
end if;
end process;
end;
|
bsd-2-clause
|
lowRISC/greth-library
|
greth_library/techmap/pll/clkp90_k7.vhd
|
3
|
4258
|
-----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - [email protected]
--! @brief Clock phase offset generator (90 deg) for Kintex7 FPGA.
------------------------------------------------------------------------------
--! Standard library
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity clkp90_kintex7 is
generic (
freq : integer := 125000
);
port (
--! Active High
i_rst : in std_logic;
i_clk : in std_logic;
o_clk : out std_logic;
o_clkp90 : out std_logic;
o_clk2x : out std_logic;
o_lock : out std_logic
);
end clkp90_kintex7;
architecture rtl of clkp90_kintex7 is
constant clk_mul : integer := 8;
constant clk_div : integer := 8;
constant period : real := 1000000.0/real(freq);
constant clkio_div : integer := freq*clk_mul/200000;
signal CLKFBOUT : std_logic;
signal CLKFBIN : std_logic;
signal clk_nobuf : std_logic;
signal clk90_nobuf : std_logic;
signal clkio_nobuf : std_logic;
begin
CLKFBIN <= CLKFBOUT;
PLLE2_ADV_inst : PLLE2_ADV generic map (
BANDWIDTH => "OPTIMIZED", -- OPTIMIZED, HIGH, LOW
CLKFBOUT_MULT => clk_mul, -- Multiply value for all CLKOUT, (2-64)
CLKFBOUT_PHASE => 0.0, -- Phase offset in degrees of CLKFB, (-360.000-360.000).
-- CLKIN_PERIOD: Input clock period in nS to ps resolution (i.e. 33.333 is 30 MHz).
CLKIN1_PERIOD => period,
CLKIN2_PERIOD => 0.0,
-- CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for CLKOUT (1-128)
CLKOUT0_DIVIDE => clk_div,
CLKOUT1_DIVIDE => clk_div,
CLKOUT2_DIVIDE => clkio_div,
CLKOUT3_DIVIDE => 1,
CLKOUT4_DIVIDE => 1,
CLKOUT5_DIVIDE => 1,
-- CLKOUT0_DUTY_CYCLE - CLKOUT5_DUTY_CYCLE: Duty cycle for CLKOUT outputs (0.001-0.999).
CLKOUT0_DUTY_CYCLE => 0.5,
CLKOUT1_DUTY_CYCLE => 0.5,
CLKOUT2_DUTY_CYCLE => 0.5,
CLKOUT3_DUTY_CYCLE => 0.5,
CLKOUT4_DUTY_CYCLE => 0.5,
CLKOUT5_DUTY_CYCLE => 0.5,
-- CLKOUT0_PHASE - CLKOUT5_PHASE: Phase offset for CLKOUT outputs (-360.000-360.000).
CLKOUT0_PHASE => 0.0,
CLKOUT1_PHASE => 90.0,
CLKOUT2_PHASE => 0.0,
CLKOUT3_PHASE => 0.0,
CLKOUT4_PHASE => 0.0,
CLKOUT5_PHASE => 0.0,
COMPENSATION => "ZHOLD", -- ZHOLD, BUF_IN, EXTERNAL, INTERNAL
DIVCLK_DIVIDE => 1, -- Master division value (1-56)
-- REF_JITTER: Reference input jitter in UI (0.000-0.999).
REF_JITTER1 => 0.0,
REF_JITTER2 => 0.0,
STARTUP_WAIT => "TRUE" -- Delay DONE until PLL Locks, ("TRUE"/"FALSE")
) port map (
-- Clock Outputs: 1-bit (each) output: User configurable clock outputs
CLKOUT0 => clk_nobuf,
CLKOUT1 => clk90_nobuf,
CLKOUT2 => clkio_nobuf,
CLKOUT3 => OPEN,
CLKOUT4 => OPEN,
CLKOUT5 => OPEN,
-- DRP Ports: 16-bit (each) output: Dynamic reconfigration ports
DO => OPEN,
DRDY => OPEN,
-- Feedback Clocks: 1-bit (each) output: Clock feedback ports
CLKFBOUT => CLKFBOUT,
-- Status Ports: 1-bit (each) output: PLL status ports
LOCKED => o_lock,
-- Clock Inputs: 1-bit (each) input: Clock inputs
CLKIN1 => i_clk,
CLKIN2 => '0',
-- Con trol Ports: 1-bit (each) input: PLL control ports
CLKINSEL => '1',
PWRDWN => '0',
RST => i_rst,
-- DRP Ports: 7-bit (each) input: Dynamic reconfigration ports
DADDR => "0000000",
DCLK => '0',
DEN => '0',
DI => "0000000000000000",
DWE => '0',
-- Feedback Clocks: 1-bit (each) input: Clock feedback ports
CLKFBIN => CLKFBIN
);
bufgclk0 : BUFG port map (I => clk_nobuf, O => o_clk);
bufgclk90 : BUFG port map (I => clk90_nobuf, O => o_clkp90);
bufgclkio : BUFG port map (I => clkio_nobuf, O => o_clk2x);
end;
|
bsd-2-clause
|
lowRISC/greth-library
|
greth_library/work/simple_soc2.vhd
|
2
|
10639
|
-----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov
--! @brief Network on Chip design top level.
--! @details RISC-V "Rocket Core" based system with the AMBA AXI4 (NASTI)
--! system bus and integrated peripheries.
------------------------------------------------------------------------------
--! Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--! Data transformation and math functions library
library commonlib;
use commonlib.types_common.all;
--! Technology definition library.
library techmap;
--! Technology constants definition.
use techmap.gencomp.all;
--! "Virtual" PLL declaration.
use techmap.types_pll.all;
--! "Virtual" buffers declaration.
use techmap.types_buf.all;
--! AMBA system bus specific library
library ambalib;
--! AXI4 configuration constants.
use ambalib.types_amba4.all;
--! Rocket-chip specific library
library rocketlib;
--! SOC top-level component declaration.
use rocketlib.types_rocket.all;
--! Ethernet related declarations.
use rocketlib.grethpkg.all;
--! GNSS Sensor Ltd proprietary library
library gnsslib;
use gnsslib.types_gnss.all;
--! Top-level implementaion library
library work;
--! Target dependable configuration: RTL, FPGA or ASIC.
use work.config_target.all;
--! Target independable configuration.
use work.config_common.all;
--! @brief SOC Top-level entity declaration.
--! @details This module implements full SOC functionality and all IO signals
--! are available on FPGA/ASIC IO pins.
entity rocket_soc is port
(
--! Input reset. Active High. Usually assigned to button "Center".
i_rst : in std_logic;
--! @name Clocks:
--! @{
--! Differential clock (LVDS) positive signal.
i_sclk_p : in std_logic;
--! Differential clock (LVDS) negative signal.
i_sclk_n : in std_logic;
--! External ADC clock (default 26 MHz).
i_clk_adc : in std_logic;
--! @}
--! @name User's IOs:
--! @{
--! DIP switch.
i_int_clkrf : in std_logic;
i_dip : in std_logic_vector(3 downto 1);
--! LEDs.
o_led : out std_logic_vector(7 downto 0);
--! @}
--! @name UART1 signals:
--! @{
i_uart1_ctsn : in std_logic;
i_uart1_rd : in std_logic;
o_uart1_td : out std_logic;
o_uart1_rtsn : out std_logic;
--! @}
--! @name ADC channel A inputs (1575.4 GHz):
--! @{
i_gps_I : in std_logic_vector(1 downto 0);
i_gps_Q : in std_logic_vector(1 downto 0);
--! @}
--! @name ADC channel B inputs (1602 GHz):
--! @{
i_glo_I : in std_logic_vector(1 downto 0);
i_glo_Q : in std_logic_vector(1 downto 0);
--! @}
--! @name MAX2769 SPIs and antenna controls signals:
--! @{
i_gps_ld : in std_logic;
i_glo_ld : in std_logic;
o_max_sclk : out std_logic;
o_max_sdata : out std_logic;
o_max_ncs : out std_logic_vector(1 downto 0);
i_antext_stat : in std_logic;
i_antext_detect : in std_logic;
o_antext_ena : out std_logic;
o_antint_contr : out std_logic;
--! @}
--! Ethernet MAC PHY interface signals
--! @{
i_gmiiclk_p : in std_ulogic;
i_gmiiclk_n : in std_ulogic;
o_egtx_clk : out std_ulogic;
i_etx_clk : in std_ulogic;
i_erx_clk : in std_ulogic;
i_erxd : in std_logic_vector(3 downto 0);
i_erx_dv : in std_ulogic;
i_erx_er : in std_ulogic;
i_erx_col : in std_ulogic;
i_erx_crs : in std_ulogic;
i_emdint : in std_ulogic;
o_etxd : out std_logic_vector(3 downto 0);
o_etx_en : out std_ulogic;
o_etx_er : out std_ulogic;
o_emdc : out std_ulogic;
io_emdio : inout std_logic;
o_erstn : out std_ulogic
);
--! @}
end rocket_soc;
--! @brief SOC top-level architecture declaration.
architecture arch_rocket_soc of rocket_soc is
--! @name Buffered in/out signals.
--! @details All signals that are connected with in/out pads must be passed
--! through the dedicated buffere modules. For FPGA they are implemented
--! as an empty devices but ASIC couldn't be made without buffering.
--! @{
signal ib_rst : std_logic;
signal ib_sclk_p : std_logic;
signal ib_sclk_n : std_logic;
signal ib_clk_adc : std_logic;
signal ib_dip : std_logic_vector(3 downto 0);
signal ib_gmiiclk : std_logic;
--! @}
signal wSysReset : std_ulogic; -- Internal system reset. MUST NOT USED BY DEVICES.
signal wReset : std_ulogic; -- Global reset active HIGH
signal wNReset : std_ulogic; -- Global reset active LOW
signal soft_rst : std_logic; -- reset from exteranl debugger
signal bus_nrst : std_ulogic; -- Global reset and Soft Reset active LOW
signal wClkBus : std_ulogic; -- bus clock from the internal PLL (100MHz virtex6/40MHz Spartan6)
signal wClkAdc : std_ulogic; -- 26 MHz from the internal PLL
signal wPllLocked : std_ulogic; -- PLL status signal. 0=Unlocked; 1=locked.
signal uart1i : uart_in_type;
signal uart1o : uart_out_type;
--! Arbiter is switching only slaves output signal, data from noc
--! is connected to all slaves and to the arbiter itself.
signal aximi : nasti_master_in_type;
signal aximo : nasti_master_out_vector;
signal axisi : nasti_slave_in_type;
signal axiso : nasti_slaves_out_vector;
signal slv_cfg : nasti_slave_cfg_vector;
signal mst_cfg : nasti_master_cfg_vector;
signal eth_i : eth_in_type;
signal eth_o : eth_out_type;
signal irq_pins : std_logic_vector(CFG_IRQ_TOTAL-1 downto 0);
begin
--! PAD buffers:
irst0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_rst, i_rst);
iclkp0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_sclk_p, i_sclk_p);
iclkn0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_sclk_n, i_sclk_n);
iclk1 : ibuf_tech generic map(CFG_PADTECH) port map (ib_clk_adc, i_clk_adc);
idip0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_dip(0), i_int_clkrf);
dipx : for i in 1 to 3 generate
idipz : ibuf_tech generic map(CFG_PADTECH) port map (ib_dip(i), i_dip(i));
end generate;
igbebuf0 : igdsbuf_tech generic map (CFG_PADTECH) port map (
i_gmiiclk_p, i_gmiiclk_n, ib_gmiiclk);
--! @todo all other in/out signals via buffers:
------------------------------------
-- @brief Internal PLL device instance.
pll0 : SysPLL_tech generic map (
tech => CFG_FABTECH,
tmode_always_ena => CFG_TESTMODE_ON
) port map (
i_reset => ib_rst,
i_int_clkrf => ib_dip(0),
i_clkp => ib_sclk_p,
i_clkn => ib_sclk_n,
i_clk_adc => ib_clk_adc,
o_clk_bus => wClkBus,
o_clk_adc => wClkAdc,
o_locked => wPllLocked
);
wSysReset <= ib_rst or not wPllLocked;
------------------------------------
--! @brief System Reset device instance.
rst0 : reset_global port map (
inSysReset => wSysReset,
inSysClk => wClkBus,
inPllLock => wPllLocked,
outReset => wReset
);
wNReset <= not wReset;
bus_nrst <= not (wReset or soft_rst);
--! @brief AXI4 controller.
ctrl0 : axictrl port map (
clk => wClkBus,
nrst => wNReset,
slvoi => axiso,
mstoi => aximo,
slvio => axisi,
mstio => aximi
);
slv_cfg(CFG_NASTI_SLAVE_DSU) <= nasti_slave_config_none;
axiso(CFG_NASTI_SLAVE_DSU) <= nasti_slave_out_none;
slv_cfg(CFG_NASTI_SLAVE_ETHMAC) <= nasti_slave_config_none;
mst_cfg(CFG_NASTI_MASTER_CACHED) <= nasti_master_config_none;
aximo(CFG_NASTI_MASTER_CACHED) <= nasti_master_out_none;
mst_cfg(CFG_NASTI_MASTER_UNCACHED) <= nasti_master_config_none;
aximo(CFG_NASTI_MASTER_UNCACHED) <= nasti_master_out_none;
------------------------------------
--! @brief Controller of the LEDs, DIPs and GPIO with the AXI4 interface.
--! @details Map address:
--! 0x80000000..0x80000fff (4 KB total)
gpio0 : nasti_gpio generic map (
xindex => CFG_NASTI_SLAVE_GPIO,
xaddr => 16#80000#,
xmask => 16#fffff#
) port map (
clk => wClkBus,
nrst => wNReset,
cfg => slv_cfg(CFG_NASTI_SLAVE_GPIO),
i => axisi,
o => axiso(CFG_NASTI_SLAVE_GPIO),
i_dip => ib_dip,
o_led => o_led
);
axiso(CFG_NASTI_SLAVE_ENGINE) <= nasti_slave_out_none;
slv_cfg(CFG_NASTI_SLAVE_ENGINE) <= nasti_slave_config_none;
irq_pins(CFG_IRQ_GNSSENGINE) <= '0';
--! Gigabit clock phase rotator with buffers
clkrot90 : clkp90_tech generic map (
tech => CFG_FABTECH,
freq => 125000 -- KHz = 125 MHz
) port map (
i_rst => wReset,
i_clk => ib_gmiiclk,
o_clk => eth_i.gtx_clk,
o_clkp90 => eth_i.tx_clk_90,
o_clk2x => open, -- used in gbe 'io_ref'
o_lock => open
);
--! @brief Ethernet MAC with the AXI4 interface.
--! @details Map address:
--! 0x80040000..0x8007ffff (256 KB total)
--! EDCL IP: 192.168.0.51 = C0.A8.00.33
eth_i.tx_clk <= i_etx_clk;
eth_i.rx_clk <= i_erx_clk;
eth_i.rxd <= i_erxd;
eth_i.rx_dv <= i_erx_dv;
eth_i.rx_er <= i_erx_er;
eth_i.rx_col <= i_erx_col;
eth_i.rx_crs <= i_erx_crs;
eth_i.mdint <= i_emdint;
mac0 : grethaxi generic map (
xslvindex => CFG_NASTI_SLAVE_ETHMAC,
xmstindex => CFG_NASTI_MASTER_ETHMAC,
xaddr => 16#80040#,
xmask => 16#FFFC0#,
xirq => CFG_IRQ_ETHMAC,
memtech => CFG_MEMTECH,
mdcscaler => 60, --! System Bus clock in MHz
enable_mdio => 1,
fifosize => 16,
nsync => 1,
edcl => 1,
edclbufsz => 16,
macaddrh => 16#20789#,
macaddrl => 16#123#,
ipaddrh => 16#C0A8#,
ipaddrl => 16#0033#,
phyrstadr => 7,
enable_mdint => 1,
maxsize => 1518
) port map (
rst => wNReset,
clk => wClkBus,
msti => aximi,
msto => aximo(CFG_NASTI_MASTER_ETHMAC),
mstcfg => mst_cfg(CFG_NASTI_MASTER_ETHMAC),
msto2 => open, -- EDCL separate access is disabled
mstcfg2 => open, -- EDCL separate access is disabled
slvi => axisi,
slvo => axiso(CFG_NASTI_SLAVE_ETHMAC),
slvcfg => slv_cfg(CFG_NASTI_SLAVE_ETHMAC),
ethi => eth_i,
etho => eth_o,
irq => irq_pins(CFG_IRQ_ETHMAC)
);
emdio_pad : iobuf_tech generic map(
CFG_PADTECH
) port map (
o => eth_i.mdio_i,
io => io_emdio,
i => eth_o.mdio_o,
t => eth_o.mdio_oe
);
o_egtx_clk <= eth_i.gtx_clk;--eth_i.tx_clk_90;
o_etxd <= eth_o.txd;
o_etx_en <= eth_o.tx_en;
o_etx_er <= eth_o.tx_er;
o_emdc <= eth_o.mdc;
o_erstn <= wNReset;
end arch_rocket_soc;
|
bsd-2-clause
|
lowRISC/greth-library
|
greth_library/rocketlib/eth/eth_axi_mst.vhd
|
2
|
7538
|
-----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - [email protected]
--! @brief AXI Master device implementing DMA access.
--! @details AMBA4 AXI Master interface module dedicated for the eth MAC.
------------------------------------------------------------------------------
--! Standard library
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
--! AMBA system bus specific library.
library ambalib;
--! AXI4 configuration constants.
use ambalib.types_amba4.all;
--! Rocket-chip specific library
library rocketlib;
use rocketlib.grethpkg.all;
entity eth_axi_mst is
generic (
xindex : integer := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
aximi : in nasti_master_in_type;
aximo : out nasti_master_out_type;
tmsti : in eth_tx_ahb_in_type;
tmsto : out eth_tx_ahb_out_type;
rmsti : in eth_rx_ahb_in_type;
rmsto : out eth_rx_ahb_out_type
);
end entity;
architecture rtl of eth_axi_mst is
constant STATE_IDLE : integer := 0;
constant STATE_W : integer := STATE_IDLE+1;
constant STATE_R : integer := STATE_W+1;
constant STATE_B : integer := STATE_R+1;
type reg_type is record
state : integer range 0 to STATE_B;
addr : std_logic_vector(31 downto 0);
len : integer;
rx_tx : std_logic;
end record;
signal r, rin : reg_type;
begin
comb : process(rst, r, tmsti, rmsti, aximi) is
variable v : reg_type;
variable tretry : std_ulogic;
variable rretry : std_ulogic;
variable rready : std_ulogic;
variable tready : std_ulogic;
variable rerror : std_ulogic;
variable terror : std_ulogic;
variable tgrant : std_ulogic;
variable rgrant : std_ulogic;
variable vmsto : nasti_master_out_type;
variable rdata_lsb : std_logic_vector(31 downto 0);
variable wdata_lsb : std_logic_vector(31 downto 0);
begin
v := r;
vmsto := nasti_master_out_none;
rready := '0';
tready := '0';
tretry := '0';
rretry := '0';
rerror := '0';
terror := '0';
tgrant := '0';
rgrant := '0';
vmsto.ar_user := '0';
vmsto.ar_id := conv_std_logic_vector(xindex, CFG_ROCKET_ID_BITS);
vmsto.ar_bits.size := "010"; -- 4 bytes
vmsto.ar_bits.burst := NASTI_BURST_INCR;
vmsto.aw_user := '0';
vmsto.aw_id := conv_std_logic_vector(xindex, CFG_ROCKET_ID_BITS);
vmsto.aw_bits.size := "010"; -- 4 bytes
vmsto.aw_bits.burst := NASTI_BURST_INCR;
case r.state is
when STATE_IDLE =>
if rmsti.req = '1' then
v.rx_tx := '0';
v.addr := rmsti.addr;
vmsto.ar_valid := not rmsti.write;
vmsto.aw_valid := rmsti.write;
if rmsti.write = '1' then
vmsto.aw_bits.addr := rmsti.addr(31 downto 4) & "0000";
v.len := conv_integer(rmsti.burst_bytes(10 downto 2)) - 1;
vmsto.aw_bits.len := conv_std_logic_vector(v.len, 8);
if (aximi.grant(xindex) and aximi.aw_ready) = '1' then
rgrant := '1';
v.state := STATE_W;
end if;
else
vmsto.ar_bits.addr := rmsti.addr;
v.len := conv_integer(rmsti.burst_bytes(10 downto 2)) - 1;
vmsto.ar_bits.len := conv_std_logic_vector(v.len, 8);
if (aximi.grant(xindex) and aximi.ar_ready) = '1' then
rgrant := '1';
v.state := STATE_R;
end if;
end if;
elsif tmsti.req = '1' then
v.rx_tx := '1';
v.addr := tmsti.addr;
vmsto.ar_valid := not tmsti.write;
vmsto.aw_valid := tmsti.write;
if tmsti.write = '1' then
vmsto.aw_bits.addr := tmsti.addr(31 downto 4) & "0000";
v.len := conv_integer(tmsti.burst_bytes(10 downto 2)) - 1;
vmsto.aw_bits.len := conv_std_logic_vector(v.len, 8);
if (aximi.grant(xindex) and aximi.aw_ready) = '1' then
tgrant := '1';
v.state := STATE_W;
end if;
else
vmsto.ar_bits.addr := tmsti.addr;
v.len := conv_integer(tmsti.burst_bytes(10 downto 2)) - 1;
vmsto.ar_bits.len := conv_std_logic_vector(v.len, 8);
if (aximi.grant(xindex) and aximi.ar_ready) = '1' then
tgrant := '1';
v.state := STATE_R;
end if;
end if;
end if;
when STATE_W =>
vmsto.w_valid := '1';
case r.addr(3 downto 2) is
when "00" => vmsto.w_strb := X"000f";
when "01" => vmsto.w_strb := X"00f0";
when "10" => vmsto.w_strb := X"0f00";
when "11" => vmsto.w_strb := X"f000";
when others =>
end case;
if r.rx_tx = '0' then
wdata_lsb := rmsti.data(7 downto 0) & rmsti.data(15 downto 8)
& rmsti.data(23 downto 16) & rmsti.data(31 downto 24);
else
wdata_lsb := tmsti.data(7 downto 0) & tmsti.data(15 downto 8)
& tmsti.data(23 downto 16) & tmsti.data(31 downto 24);
end if;
vmsto.w_data := wdata_lsb & wdata_lsb & wdata_lsb & wdata_lsb;
if aximi.w_ready = '1' then
tready := r.rx_tx;
rready := not r.rx_tx;
if r.len = 0 then
v.state := STATE_B;
else
tgrant := r.rx_tx;
rgrant := not r.rx_tx;
v.len := r.len - 1;
-- Incremented on slave side
--v.addr = r.addr + 4;
end if;
end if;
when STATE_R =>
vmsto.r_ready := '1';
if aximi.r_valid = '1' then
if aximi.r_resp = NASTI_RESP_OKAY then
tready := r.rx_tx;
rready := not r.rx_tx;
else
terror := r.rx_tx;
rerror := not r.rx_tx;
end if;
if r.len = 0 then
v.state := state_idle;
else
tgrant := r.rx_tx;
rgrant := not r.rx_tx;
v.len := r.len - 1;
end if;
end if;
when STATE_B =>
vmsto.b_ready := '1';
if aximi.b_valid = '1' then
v.state := STATE_IDLE;
end if;
when others =>
end case;
if rst = '0' then
v.state := STATE_IDLE;
v.addr := (others => '0');
v.len := 0;
v.rx_tx := '0';
end if;
-- Pre-fix for SPARC byte order.
-- It is better to fix in MAC itselfm but for now it will be here.
rdata_lsb := aximi.r_data(7 downto 0) & aximi.r_data(15 downto 8)
& aximi.r_data(23 downto 16) & aximi.r_data(31 downto 24);
rin <= v;
aximo <= vmsto;
tmsto.error <= terror;
tmsto.retry <= tretry;
tmsto.ready <= tready;
tmsto.grant <= tgrant;
tmsto.data <= rdata_lsb;
rmsto.error <= rerror;
rmsto.retry <= rretry;
rmsto.ready <= rready;
rmsto.grant <= rgrant;
rmsto.data <= rdata_lsb;
end process;
regs : process(clk)
begin
if rising_edge(clk) then r <= rin; end if;
end process;
end architecture;
|
bsd-2-clause
|
lowRISC/greth-library
|
greth_library/techmap/bufg/ibuf_inferred.vhd
|
3
|
509
|
----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov
--! @brief Input buffer for simulation.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity ibuf_inferred is
port (
o : out std_logic;
i : in std_logic
);
end;
architecture rtl of ibuf_inferred is
begin
o <= i;
end;
|
bsd-2-clause
|
lowRISC/greth-library
|
greth_library/rocketlib/misc/nasti_irqctrl.vhd
|
2
|
8666
|
-----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - [email protected]
--! @brief Interrupt controller with the AXI4 interface
--! @details This module generates CPU interrupt emitting write message into
--! CSR register 'send_ipi' via HostIO bus interface.
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library commonlib;
use commonlib.types_common.all;
--! AMBA system bus specific library.
library ambalib;
--! AXI4 configuration constants.
use ambalib.types_amba4.all;
--! RISCV specific funcionality.
library rocketlib;
use rocketlib.types_rocket.all;
entity nasti_irqctrl is
generic (
xindex : integer := 0;
xaddr : integer := 0;
xmask : integer := 16#fffff#;
htif_index : integer := 0
);
port
(
clk : in std_logic;
nrst : in std_logic;
i_irqs : in std_logic_vector(CFG_IRQ_TOTAL-1 downto 0);
o_cfg : out nasti_slave_config_type;
i_axi : in nasti_slave_in_type;
o_axi : out nasti_slave_out_type;
i_host : in host_in_type;
o_host : out host_out_type
);
end;
architecture nasti_irqctrl_rtl of nasti_irqctrl is
constant CSR_MIPI : std_logic_vector(11 downto 0) := X"783";
constant xconfig : nasti_slave_config_type := (
xindex => xindex,
xaddr => conv_std_logic_vector(xaddr, CFG_NASTI_CFG_ADDR_BITS),
xmask => conv_std_logic_vector(xmask, CFG_NASTI_CFG_ADDR_BITS),
vid => VENDOR_GNSSSENSOR,
did => GNSSSENSOR_IRQCTRL,
descrtype => PNP_CFG_TYPE_SLAVE,
descrsize => PNP_CFG_SLAVE_DESCR_BYTES
);
type local_addr_array_type is array (0 to CFG_WORDS_ON_BUS-1)
of integer;
type state_type is (idle, wait_grant, wait_resp);
type registers is record
bank_axi : nasti_slave_bank_type;
host_reset : std_logic_vector(1 downto 0);
--! Message multiplexer to form 128 request message of writting into CSR
state : state_type;
--! interrupt signal delay signal to detect interrupt positive edge
irqs_z : std_logic_vector(CFG_IRQ_TOTAL-1 downto 0);
irqs_zz : std_logic_vector(CFG_IRQ_TOTAL-1 downto 0);
--! mask irq disabled: 1=disabled; 0=enabled
irqs_mask : std_logic_vector(CFG_IRQ_TOTAL-1 downto 0);
--! irq pending bit mask
irqs_pending : std_logic_vector(CFG_IRQ_TOTAL-1 downto 0);
--! interrupt handler address initialized by FW:
isr_table : std_logic_vector(63 downto 0);
--! hold-on generation of interrupt.
irq_lock : std_logic;
--! delayed interrupt
irq_wait_unlock : std_logic_vector(CFG_IRQ_TOTAL-1 downto 0);
irq_cause_idx : std_logic_vector(31 downto 0);
--! Function trap_entry copies the values of CSRs into these two regs:
dbg_cause : std_logic_vector(63 downto 0);
dbg_epc : std_logic_vector(63 downto 0);
end record;
signal r, rin: registers;
begin
comblogic : process(i_irqs, i_axi, i_host, r)
variable v : registers;
variable raddr_reg : local_addr_array_type;
variable waddr_reg : local_addr_array_type;
variable rdata : std_logic_vector(CFG_NASTI_DATA_BITS-1 downto 0);
variable tmp : std_logic_vector(31 downto 0);
variable wstrb : std_logic_vector(CFG_ALIGN_BYTES-1 downto 0);
variable w_generate_ipi : std_logic;
begin
v := r;
w_generate_ipi := '0';
procedureAxi4(i_axi, xconfig, r.bank_axi, v.bank_axi);
for n in 0 to CFG_WORDS_ON_BUS-1 loop
raddr_reg(n) := conv_integer(r.bank_axi.raddr(n)(11 downto 2));
tmp := (others => '0');
case raddr_reg(n) is
when 0 => tmp(CFG_IRQ_TOTAL-1 downto 0) := r.irqs_mask; --! [RW]: 1=irq disable; 0=enable
when 1 => tmp(CFG_IRQ_TOTAL-1 downto 0) := r.irqs_pending; --! [RO]: Rised interrupts.
when 2 => tmp := (others => '0'); --! [WO]: Clear interrupts mask.
when 3 => tmp := (others => '0'); --! [WO]: Rise interrupts mask.
when 4 => tmp := r.isr_table(31 downto 0); --! [RW]: LSB of the function address
when 5 => tmp := r.isr_table(63 downto 32); --! [RW]: MSB of the function address
when 6 => tmp := r.dbg_cause(31 downto 0); --! [RW]: Cause of the interrupt
when 7 => tmp := r.dbg_cause(63 downto 32); --! [RW]:
when 8 => tmp := r.dbg_epc(31 downto 0); --! [RW]: Instruction pointer
when 9 => tmp := r.dbg_epc(63 downto 32); --! [RW]:
when 10 => tmp(0) := r.irq_lock;
when 11 => tmp := r.irq_cause_idx;
when others =>
end case;
rdata(8*CFG_ALIGN_BYTES*(n+1)-1 downto 8*CFG_ALIGN_BYTES*n) := tmp;
end loop;
if i_axi.w_valid = '1' and
r.bank_axi.wstate = wtrans and
r.bank_axi.wresp = NASTI_RESP_OKAY then
for n in 0 to CFG_WORDS_ON_BUS-1 loop
waddr_reg(n) := conv_integer(r.bank_axi.waddr(n)(11 downto 2));
tmp := i_axi.w_data(32*(n+1)-1 downto 32*n);
wstrb := i_axi.w_strb(CFG_ALIGN_BYTES*(n+1)-1 downto CFG_ALIGN_BYTES*n);
if conv_integer(wstrb) /= 0 then
case waddr_reg(n) is
when 0 => v.irqs_mask := tmp(CFG_IRQ_TOTAL-1 downto 0);
when 1 => --! Read only
when 2 =>
v.irqs_pending := r.irqs_pending and (not tmp(CFG_IRQ_TOTAL-1 downto 0));
when 3 =>
w_generate_ipi := '1';
v.irqs_pending := (not r.irqs_mask) and tmp(CFG_IRQ_TOTAL-1 downto 0);
when 4 => v.isr_table(31 downto 0) := tmp;
when 5 => v.isr_table(63 downto 32) := tmp;
when 6 => v.dbg_cause(31 downto 0) := tmp;
when 7 => v.dbg_cause(63 downto 32) := tmp;
when 8 => v.dbg_epc(31 downto 0) := tmp;
when 9 => v.dbg_epc(63 downto 32) := tmp;
when 10 => v.irq_lock := tmp(0);
when 11 => v.irq_cause_idx := tmp;
when others =>
end case;
end if;
end loop;
end if;
v.irqs_z := i_irqs;
v.irqs_zz := r.irqs_z;
for n in 0 to CFG_IRQ_TOTAL-1 loop
if (r.irqs_z(n) = '1' and r.irqs_zz(n) = '0') or r.irq_wait_unlock(n) = '1' then
if r.irq_lock = '0' then
v.irq_wait_unlock(n) := '0';
v.irqs_pending(n) := not r.irqs_mask(n);
w_generate_ipi := w_generate_ipi or (not r.irqs_mask(n));
else
v.irq_wait_unlock(n) := '1';
end if;
end if;
end loop;
case r.state is
when idle =>
if w_generate_ipi = '1' then
v.state := wait_grant;
end if;
when wait_grant =>
if (i_host.grant(htif_index) and i_host.csr_req_ready) = '1' then
v.state := wait_resp;
end if;
when wait_resp =>
if i_host.csr_resp_valid = '1' then
v.state := idle;
end if;
when others =>
end case;
o_axi <= functionAxi4Output(r.bank_axi, rdata);
if r.state = wait_grant then
o_host.csr_req_valid <= '1';
o_host.csr_req_bits_rw <= '1';
o_host.csr_req_bits_addr <= CSR_MIPI;
o_host.csr_req_bits_data <= X"0000000000000001";
else
o_host.csr_req_valid <= '0';
o_host.csr_req_bits_rw <= '0';
o_host.csr_req_bits_addr <= (others => '0');
o_host.csr_req_bits_data <= (others => '0');
end if;
-- delayed reset (!!!previously accidentaly was ='1' check with L2)
v.host_reset := r.host_reset(0) & '0';
rin <= v;
end process;
o_cfg <= xconfig;
o_host.reset <= '0';--r.host_reset(1);
o_host.id <= '0';
o_host.csr_resp_ready <= '1';
-- registers:
regs : process(clk, nrst)
begin
if nrst = '0' then
r.bank_axi <= NASTI_SLAVE_BANK_RESET;
r.host_reset <= (others => '1');
r.state <= idle;
r.irqs_mask <= (others => '1'); -- all interrupts disabled
r.irqs_pending <= (others => '0');
r.irqs_z <= (others => '0');
r.irqs_zz <= (others => '0');
r.isr_table <= (others => '0');
r.irq_lock <= '0';
r.irq_wait_unlock <= (others => '0');
r.irq_cause_idx <= (others => '0');
r.dbg_cause <= (others => '0');
r.dbg_epc <= (others => '0');
elsif rising_edge(clk) then
r <= rin;
end if;
end process;
end;
|
bsd-2-clause
|
lowRISC/greth-library
|
greth_library/rocketlib/tilelink/axibridge.vhd
|
2
|
9670
|
-----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - [email protected]
--! @brief TileLink-to-AXI4 bridge implementation.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
--! AMBA system bus specific library.
library ambalib;
--! AXI4 configuration constants.
use ambalib.types_amba4.all;
library rocketlib;
use rocketlib.types_rocket.all;
entity AxiBridge is
generic (
xindex : integer := 0
);
port (
clk : in std_logic;
nrst : in std_logic;
--! Tile-to-AXI direction
tloi : in tile_cached_out_type;
msto : out nasti_master_out_type;
--! AXI-to-Tile direction
msti : in nasti_master_in_type;
tlio : out tile_cached_in_type
);
end;
architecture arch_AxiBridge of AxiBridge is
type tile_rstatetype is (rwait_acq, reading);
type tile_wstatetype is (wwait_acq, writting);
type registers is record
rstate : tile_rstatetype;
rd_addr : std_logic_vector(CFG_NASTI_ADDR_BITS-1 downto 0);
rd_addr_incr : integer;
rd_beat_cnt : integer;
rd_xsize : std_logic_vector(2 downto 0); -- encoded AXI4 bytes size
rd_xact_id : std_logic_vector(1 downto 0);
rd_g_type : std_logic_vector(3 downto 0);
wstate : tile_wstatetype;
wr_addr : std_logic_vector(CFG_NASTI_ADDR_BITS-1 downto 0);
wr_addr_incr : integer;
wr_beat_cnt : integer;
wr_xsize : std_logic_vector(2 downto 0); -- encoded AXI4 bytes size
wr_xact_id : std_logic_vector(1 downto 0);
wr_g_type : std_logic_vector(3 downto 0);
wmask : std_logic_vector(CFG_NASTI_DATA_BYTES-1 downto 0);
wdata : std_logic_vector(CFG_NASTI_DATA_BITS-1 downto 0);
end record;
signal r, rin : registers;
function functionAxi4MetaData(
a : std_logic_vector(CFG_NASTI_ADDR_BITS-1 downto 0);
len : integer;
sz : std_logic_vector(2 downto 0)
) return nasti_metadata_type is
variable ret : nasti_metadata_type;
begin
ret.addr := a;
ret.len := conv_std_logic_vector(len,8);
ret.size := sz;
ret.burst := NASTI_BURST_INCR;
ret.lock := '0';
ret.cache := (others => '0');
ret.prot := (others => '0');
ret.qos := (others => '0');
ret.region := (others => '0');
return (ret);
end function;
begin
comblogic : process(tloi, msti, r)
variable v : registers;
variable vmsto : nasti_master_out_type;
variable vtlio : tile_cached_in_type;
variable addr : std_logic_vector(CFG_NASTI_ADDR_BITS-1 downto 0);
variable write : std_logic;
variable next_ena : std_logic;
variable wbAddr : std_logic_vector(CFG_NASTI_ADDR_BITS-1 downto 0);
variable wWrite : std_logic;
variable wbWMask : std_logic_vector(CFG_NASTI_DATA_BYTES-1 downto 0);
variable wbAxiSize : std_logic_vector(2 downto 0);
variable wbByteAddr : std_logic_vector(3 downto 0);
variable wbBeatCnt : integer;
begin
v := r;
addr := (others => '0');
write := '0';
vmsto.aw_valid := '0';
vmsto.aw_bits := META_NONE;
vmsto.aw_id := (others => '0');
vmsto.w_valid := '0';
vmsto.w_data := (others => '0');
vmsto.w_last := '0';
vmsto.w_strb := (others => '0');
vmsto.ar_valid := '0';
vmsto.ar_bits := META_NONE;
vmsto.ar_id := (others => '0');
vmsto.r_ready := '0';
vmsto.ar_user := '0';
vmsto.aw_user := '0';
vmsto.w_user := '0';
vmsto.b_ready := '1';
vtlio.acquire_ready := '0';
vtlio.probe_valid := '0'; -- unused
vtlio.release_ready := '0'; -- unused
vtlio.grant_valid := '0';
vtlio.grant_bits_addr_beat := "00";
vtlio.grant_bits_client_xact_id := "00";
vtlio.grant_bits_manager_xact_id := "0000"; -- const
vtlio.grant_bits_is_builtin_type := '1'; -- const
vtlio.grant_bits_g_type := GRANT_ACK_RELEASE;
vtlio.grant_bits_data := (others => '0');
procedureDecodeTileAcquire(tloi.acquire_bits_a_type,--in
tloi.acquire_bits_is_builtin_type, --in
tloi.acquire_bits_union, --in
wWrite,
wbWMask,
wbAxiSize,
wbByteAddr,
wbBeatCnt);
wbAddr := tloi.acquire_bits_addr_block
& tloi.acquire_bits_addr_beat
& "0000";--wbByteAddr;
vmsto.aw_valid := tloi.acquire_valid and wWrite;
vmsto.ar_valid := tloi.acquire_valid and not wWrite;
case r.wstate is
when wwait_acq =>
if vmsto.aw_valid = '1' and msti.grant(xindex) = '1' and r.rstate = rwait_acq then
v.wr_addr := wbAddr;
v.wr_addr_incr := XSizeToBytes(conv_integer(wbAxiSize));
v.wr_beat_cnt := wbBeatCnt;
v.wr_xsize := opSizeToXSize(conv_integer(tloi.acquire_bits_union(8 downto 6)));
v.wr_xact_id := tloi.acquire_bits_client_xact_id;
if tloi.acquire_bits_is_builtin_type = '1' then
v.wr_g_type := GRANT_ACK_NON_PREFETCH_PUT;
else
v.wr_g_type := CACHED_GRANT_EXCLUSIVE_ACK;
end if;
v.wmask := wbWMask;
if msti.aw_ready = '1' then
v.wstate := writting;
v.wdata := tloi.acquire_bits_data;
end if;
vmsto.aw_bits := functionAxi4MetaData(wbAddr, wbBeatCnt, wbAxiSize);
vmsto.aw_id(1 downto 0) := tloi.acquire_bits_client_xact_id;
vmsto.aw_id(CFG_ROCKET_ID_BITS-1 downto 2) := (others => '0');
vtlio.acquire_ready := tloi.acquire_valid and msti.aw_ready;
end if;
when writting =>
if r.wr_beat_cnt = 0 and msti.w_ready = '1' then
vmsto.w_last := '1';
v.wstate := wwait_acq;
elsif msti.w_ready = '1' and tloi.acquire_valid = '1' then
v.wr_beat_cnt := r.wr_beat_cnt - 1;
v.wr_addr := r.wr_addr + r.wr_addr_incr;
v.wdata := tloi.acquire_bits_data;
end if;
vmsto.w_valid := '1';
vmsto.w_data := r.wdata;
vmsto.w_strb := r.wmask;
when others =>
end case;
case r.rstate is
when rwait_acq =>
if vmsto.ar_valid = '1' and msti.grant(xindex) = '1' and r.wstate = wwait_acq then
v.rd_addr := wbAddr;
v.rd_addr_incr := XSizeToBytes(conv_integer(wbAxiSize));
v.rd_beat_cnt := wbBeatCnt;
v.rd_xsize := opSizeToXSize(conv_integer(tloi.acquire_bits_union(8 downto 6)));
v.rd_xact_id := tloi.acquire_bits_client_xact_id;
if tloi.acquire_bits_is_builtin_type = '1' then
if wbBeatCnt = 0 then
v.rd_g_type := GRANT_SINGLE_BEAT_GET;
else
v.rd_g_type := GRANT_BLOCK_GET;
end if;
else
v.wr_g_type := CACHED_GRANT_SHARED;
--wbBeatCnt := 3;
--wbAxiSize := "100";
--v.rd_addr_incr := XSizeToBytes(conv_integer(wbAxiSize));
--v.rd_beat_cnt := wbBeatCnt;
--v.rd_xsize := wbAxiSize;
end if;
if msti.ar_ready = '1' then
v.rstate := reading;
end if;
vmsto.ar_bits := functionAxi4MetaData(wbAddr, wbBeatCnt, wbAxiSize);
vmsto.ar_id(1 downto 0) := tloi.acquire_bits_client_xact_id;
vmsto.ar_id(CFG_ROCKET_ID_BITS-1 downto 2) := (others => '0');
vtlio.acquire_ready := tloi.acquire_valid and msti.ar_ready;
end if;
when reading =>
next_ena := tloi.grant_ready and msti.r_valid;
if next_ena = '1' and r.rd_xact_id = msti.r_id(1 downto 0) then
v.rd_beat_cnt := r.rd_beat_cnt - 1;
v.rd_addr := r.rd_addr + r.rd_addr_incr;
if r.rd_beat_cnt = 0 then
v.rstate := rwait_acq;
end if;
end if;
vmsto.r_ready := tloi.grant_ready;
when others =>
end case;
if r.rstate = reading then
if r.rd_xact_id = msti.r_id(1 downto 0) then
vtlio.grant_valid := msti.r_valid;
else
vtlio.grant_valid := '0';
end if;
vtlio.grant_bits_addr_beat := r.rd_addr(5 downto 4);
vtlio.grant_bits_client_xact_id := r.rd_xact_id;
vtlio.grant_bits_g_type := r.rd_g_type;
vtlio.grant_bits_data := msti.r_data;
elsif r.wstate = writting then
vtlio.grant_valid := msti.w_ready;
vtlio.grant_bits_addr_beat := r.wr_addr(5 downto 4);
vtlio.grant_bits_client_xact_id := r.wr_xact_id;
vtlio.grant_bits_g_type := r.wr_g_type;
vtlio.grant_bits_data := (others => '0');
end if;
rin <= v;
tlio <= vtlio;
msto <= vmsto;
end process;
-- registers:
regs : process(clk, nrst)
begin
if nrst = '0' then
r.rstate <= rwait_acq;
r.wstate <= wwait_acq;
elsif rising_edge(clk) then
r <= rin;
end if;
end process;
end;
|
bsd-2-clause
|
armandas/VHDL-School
|
Sounds/test_sound1.vhd
|
1
|
809
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity test_sound1 is
generic(
ADDR_WIDTH: integer := 4
);
port(
addr: in std_logic_vector(ADDR_WIDTH - 1 downto 0);
data: out std_logic_vector(5 downto 0)
);
end test_sound1;
architecture content of test_sound1 is
type tune is array(0 to 2 ** ADDR_WIDTH - 1)
of std_logic_vector(5 downto 0);
constant TEST: tune :=
(
"011010",
"000001",
"011010",
"000001",
"100010",
"000001",
"100010",
"000001",
"101010",
"000001",
"101010",
"000000",
"000000",
"000000",
"000000",
"000000"
);
begin
data <= TEST(conv_integer(addr));
end content;
|
bsd-2-clause
|
armandas/VHDL-School
|
SquareThingy/rotate.vhd
|
1
|
1627
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity circle is
port(
clk: in std_logic;
cw: in std_logic;
disp: out std_logic_vector(3 downto 0);
value: out std_logic_vector(7 downto 0)
);
end circle;
architecture rotate of circle is
constant M: integer := 23;
signal disp_next: std_logic_vector(3 downto 0);
signal clock_divider: std_logic_vector(M-1 downto 0);
signal counter, counter_next: std_logic_vector(2 downto 0);
signal top, top_next: std_logic;
begin
process(clk, clock_divider)
begin
if (clk'event and clk = '0') then
clock_divider <= clock_divider + '1';
if (clock_divider = 0) then
counter <= counter_next;
disp <= disp_next;
top <= top_next;
end if;
end if;
end process;
counter_next <= counter + 1;
top_next <= '1' when (counter = "111" and cw = '0') or
(counter = "011" and cw = '1') else
'0' when (counter = "111" and cw = '1') or
(counter = "011" and cw = '0') else top;
value <= "01100011" when (top = '1') else "00011101";
process(counter_next)
begin
case counter_next is
when "000" | "111" =>
disp_next <= "1110";
when "001" | "110" =>
disp_next <= "1101";
when "010" | "101" =>
disp_next <= "1011";
when others =>
disp_next <= "0111";
end case;
end process;
end rotate;
|
bsd-2-clause
|
andykarpov/radio-86rk-wxeda
|
src/keyboard/PS2Controller.vhd
|
1
|
5734
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity PS2Controller is
port (Reset : in STD_LOGIC;
Clock : in STD_LOGIC;
PS2Clock : inout STD_LOGIC;
PS2Data : inout STD_LOGIC;
Send : in STD_LOGIC;
Command : in STD_LOGIC_VECTOR(7 downto 0);
PS2Busy : out STD_LOGIC;
PS2Error : buffer STD_LOGIC;
DataReady : out STD_LOGIC;
DataByte : out STD_LOGIC_VECTOR(7 downto 0));
end PS2Controller;
architecture Behavioral of PS2Controller is
constant ClockFreq : natural := 50; -- MHz
constant Time100us : natural := 100 * ClockFreq;
constant Time20us : natural := 20 * ClockFreq;
constant DebounceDelay : natural := 16;
type StateType is (Idle, ReceiveData, InhibitComunication, RequestToSend, SendData, CheckAck, WaitRiseClock);
signal State : StateType;
signal BitsRead : natural range 0 to 10;
signal BitsSent : natural range 0 to 10;
signal Byte : STD_LOGIC_VECTOR(7 downto 0);
signal CountOnes : STD_LOGIC; -- One bit only to know if even or odd number of ones
signal DReady : STD_LOGIC;
signal PS2ClockPrevious : STD_LOGIC;
signal PS2ClockOut : STD_LOGIC;
signal PS2Clock_Z : STD_LOGIC;
signal PS2Clock_D : STD_LOGIC;
signal PS2DataOut : STD_LOGIC;
signal PS2Data_Z : STD_LOGIC;
signal PS2Data_D : STD_LOGIC;
signal TimeCounter : natural range 0 to Time100us;
begin
DebounceClock: entity work.Debouncer
generic map (Delay => DebounceDelay)
port map (Clock => Clock,
Reset => Reset,
Input => PS2Clock,
Output => PS2Clock_D);
DebounceData: entity work.Debouncer
generic map (Delay => DebounceDelay)
port map (Clock => Clock,
Reset => Reset,
Input => PS2Data,
Output => PS2Data_D);
PS2Clock <= PS2ClockOut when PS2Clock_Z <= '0' else 'Z';
PS2Data <= PS2DataOut when PS2Data_Z <= '0' else 'Z';
process(Reset, Clock)
begin
if Reset = '1' then
PS2Clock_Z <= '1';
PS2ClockOut <= '1';
PS2Data_Z <= '1';
PS2DataOut <= '1';
DataReady <= '0';
DReady <= '0';
DataByte <= (others => '0');
PS2Busy <= '0';
PS2Error <= '0';
BitsRead <= 0;
BitsSent <= 0;
CountOnes <= '0';
TimeCounter <= 0;
PS2ClockPrevious <= '1';
Byte <= x"FF";
State <= InhibitComunication;
elsif rising_edge(Clock) then
PS2ClockPrevious <= PS2Clock_D;
case State is
when Idle =>
DataReady <= '0';
DReady <= '0';
BitsRead <= 0;
PS2Error <= '0';
CountOnes <= '0';
if PS2Data_D = '0' then -- Start bit
PS2Busy <= '1';
State <= ReceiveData;
elsif Send = '1' then
Byte <= Command;
PS2Busy <= '1';
TimeCounter <= 0;
State <= InhibitComunication;
else
State <= Idle;
end if;
when ReceiveData =>
if PS2ClockPrevious = '1' and PS2Clock_D = '0' then -- falling edge
case BitsRead is
when 1 to 8 => -- 8 Data bits
Byte(BitsRead - 1) <= PS2Data_D;
if PS2Data_D = '1' then
CountOnes <= not CountOnes;
end if;
when 9 => -- Parity bit
case CountOnes is
when '0' =>
if PS2Data_D = '0' then
PS2Error <= '1'; -- Error when CountOnes is even (0)
else -- and parity bit is unasserted
PS2Error <= '0';
end if;
when others =>
if PS2Data_D = '1' then
PS2Error <= '1'; -- Error when CountOnes is odd (1)
else -- and parity bit is asserted
PS2Error <= '0';
end if;
end case;
when 10 => -- Stop bit
if PS2Error = '0' then
DataByte <= Byte;
DReady <= '1';
else
DReady <= '0';
end if;
State <= WaitRiseClock;
when others => null;
end case;
BitsRead <= BitsRead + 1;
end if;
when InhibitComunication =>
PS2Clock_Z <= '0';
PS2ClockOut <= '0';
if TimeCounter = Time100us then
TimeCounter <= 0;
State <= RequestToSend;
else
TimeCounter <= TimeCounter + 1;
end if;
when RequestToSend =>
PS2Clock_Z <= '1';
PS2Data_Z <= '0';
PS2DataOut <= '0'; -- Sets the start bit, valid when PS2Clock is high
if TimeCounter = Time20us then
TimeCounter <= 0;
PS2ClockOut <= '1';
BitsSent <= 1;
State <= SendData;
else
TimeCounter <= TimeCounter + 1;
end if;
when SendData =>
PS2Clock_Z <= '1';
if PS2ClockPrevious = '1' and PS2Clock_D = '0' then -- falling edge
case BitsSent is
when 1 to 8 => -- 8 Data bits
if Byte(BitsSent - 1) = '0' then
PS2DataOut <= '0';
else
CountOnes <= not CountOnes;
PS2DataOut <= '1';
end if;
when 9 => -- Parity bit
if CountOnes = '0' then
PS2DataOut <= '1';
else
PS2DataOut <= '0';
end if;
when 10 => -- Stop bit
PS2DataOut <= '1';
State <= CheckAck;
when others => null;
end case;
BitsSent <= BitsSent + 1;
end if;
when CheckAck =>
PS2Data_Z <= '1';
if PS2ClockPrevious = '1' and PS2Clock_D = '0' then
if PS2Data_D = '1' then -- no Acknowledge received
PS2Error <= '1';
end if;
State <= WaitRiseClock;
end if;
when WaitRiseClock =>
if PS2ClockPrevious = '0' and PS2Clock_D = '1' then
PS2Busy <= '0';
DataReady <= DReady;
State <= Idle;
end if;
when others => null;
end case;
end if;
end process;
end Behavioral;
|
bsd-2-clause
|
tristanseifert/68komputer
|
VideoPLL.vhd
|
1
|
17363
|
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: VideoPLL.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.0.0 Build 156 04/24/2013 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY VideoPLL IS
PORT
(
areset : IN STD_LOGIC := '0';
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END VideoPLL;
ARCHITECTURE SYN OF videopll IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire6_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire6 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
compensate_clock : STRING;
gate_lock_signal : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
invalid_lock_multiplier : NATURAL;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
valid_lock_multiplier : NATURAL
);
PORT (
areset : IN STD_LOGIC ;
clk : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
locked : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
sub_wire6_bv(0 DOWNTO 0) <= "0";
sub_wire6 <= To_stdlogicvector(sub_wire6_bv);
sub_wire3 <= sub_wire0(0);
sub_wire1 <= sub_wire0(1);
c1 <= sub_wire1;
locked <= sub_wire2;
c0 <= sub_wire3;
sub_wire4 <= inclk0;
sub_wire5 <= sub_wire6(0 DOWNTO 0) & sub_wire4;
altpll_component : altpll
GENERIC MAP (
clk0_divide_by => 960,
clk0_duty_cycle => 50,
clk0_multiply_by => 1007,
clk0_phase_shift => "0",
clk1_divide_by => 480,
clk1_duty_cycle => 50,
clk1_multiply_by => 1007,
clk1_phase_shift => "0",
compensate_clock => "CLK0",
gate_lock_signal => "NO",
inclk0_input_frequency => 41666,
intended_device_family => "Cyclone II",
invalid_lock_multiplier => 5,
lpm_hint => "CBX_MODULE_PREFIX=VideoPLL",
lpm_type => "altpll",
operation_mode => "NORMAL",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_USED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
valid_lock_multiplier => 1
)
PORT MAP (
areset => areset,
inclk => sub_wire5,
clk => sub_wire0,
locked => sub_wire2
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "7"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "25.174999"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "50.349998"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "24.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "25.17500000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "50.35000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "VideoPLL.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "960"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1007"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "480"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "1007"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: GATE_LOCK_SIGNAL STRING "NO"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "41666"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1"
-- Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
-- Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL VideoPLL.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL VideoPLL.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL VideoPLL.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL VideoPLL.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL VideoPLL.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL VideoPLL_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON
|
bsd-2-clause
|
pmassolino/hw-goppa-mceliece
|
mceliece/backup/tb_solving_key_equation_1_v2.vhd
|
1
|
12203
|
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Tb_Solving_Key_Equation_1_v2
-- Module Name: Tb_Solving_Key_Equation_1_v2
-- Project Name: McEliece QD-Goppa Decoder
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- Test bench for solving_key_equation_1_v2 circuit.
--
-- Circuit Parameters
--
-- PERIOD :
--
-- Input clock period to be applied on the test.
--
-- gf_2_m :
--
-- The size of the field used in this circuit. This parameter depends of the
-- Goppa code used.
--
-- final_degree :
--
-- The final degree size expected for polynomial sigma to have. This parameter depends
-- of the Goppa code used.
--
-- size_final_degree :
--
-- The number of bits necessary to hold the polynomial with degree of final_degree, which
-- has final_degree + 1 coefficients. This is ceil(log2(final_degree+1)).
--
-- sigma_memory_file :
--
-- File that holds polynomial sigma coefficients.
-- This file is necessary to verify if the output of this circuit is correct.
--
-- dump_sigma_memory_file :
--
-- File that will hold the output of this circuit, polynomial sigma.
--
-- syndrome_memory_file :
--
-- File that holds the syndrome that is needed to compute polynomial sigma.
--
--
-- Dependencies:
--
-- VHDL-93
--
-- solving_key_equation_1_v2 Rev 1.0
-- inv_gf_2_m_pipeline Rev 1.0
-- ram Rev 1.0
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity tb_solving_key_equation_1_v2 is
Generic(
PERIOD : time := 10 ns;
-- QD-GOPPA [52, 28, 4, 6] --
gf_2_m : integer range 1 to 20 := 6;
final_degree : integer := 4;
size_final_degree : integer := 2;
sigma_memory_file : string := "mceliece/data_tests/sigma_qdgoppa_52_28_4_6.dat";
dump_sigma_memory_file : string := "mceliece/data_tests/dump_sigma_qdgoppa_52_28_4_6.dat";
syndrome_memory_file : string := "mceliece/data_tests/syndrome_qdgoppa_52_28_4_6.dat"
-- GOPPA [2048, 1751, 27, 11] --
-- gf_2_m : integer range 1 to 20 := 11;
-- final_degree : integer := 27;
-- size_final_degree : integer := 5;
-- sigma_memory_file : string := "mceliece/data_tests/sigma_goppa_2048_1751_27_11.dat";
-- dump_sigma_memory_file : string := "mceliece/data_tests/dump_sigma_goppa_2048_1751_27_11.dat";
-- syndrome_memory_file : string := "mceliece/data_tests/syndrome_goppa_2048_1751_27_11.dat"
-- GOPPA [2048, 1498, 50, 11] --
-- gf_2_m : integer range 1 to 20 := 11;
-- final_degree : integer := 50;
-- size_final_degree : integer := 6;
-- sigma_memory_file : string := "mceliece/data_tests/sigma_goppa_2048_1498_50_11.dat";
-- dump_sigma_memory_file : string := "mceliece/data_tests/dump_sigma_goppa_2048_1498_50_11.dat";
-- syndrome_memory_file : string := "mceliece/data_tests/syndrome_goppa_2048_1498_50_11.dat"
-- GOPPA [3307, 2515, 66, 12] --
-- gf_2_m : integer range 1 to 20 := 12;
-- final_degree : integer := 66;
-- size_final_degree : integer := 7;
-- sigma_memory_file : string := "mceliece/data_tests/sigma_goppa_3307_2515_66_12.dat";
-- dump_sigma_memory_file : string := "mceliece/data_tests/dump_sigma_goppa_3307_2515_66_12.dat";
-- syndrome_memory_file : string := "mceliece/data_tests/syndrome_goppa_3307_2515_66_12.dat"
-- QD-GOPPA [2528, 2144, 32, 12] --
-- gf_2_m : integer range 1 to 20 := 12;
-- final_degree : integer := 32;
-- size_final_degree : integer := 5;
-- sigma_memory_file : string := "mceliece/data_tests/sigma_qdgoppa_2528_2144_32_12.dat";
-- dump_sigma_memory_file : string := "mceliece/data_tests/dump_sigma_qdgoppa_2528_2144_32_12.dat";
-- syndrome_memory_file : string := "mceliece/data_tests/syndrome_qdgoppa_2528_2144_32_12.dat"
-- QD-GOPPA [2816, 2048, 64, 12] --
-- gf_2_m : integer range 1 to 20 := 12;
-- final_degree : integer := 64;
-- size_final_degree : integer := 6;
-- sigma_memory_file : string := "mceliece/data_tests/sigma_qdgoppa_2816_2048_64_12.dat";
-- dump_sigma_memory_file : string := "mceliece/data_tests/dump_sigma_qdgoppa_2816_2048_64_12.dat";
-- syndrome_memory_file : string := "mceliece/data_tests/syndrome_qdgoppa_2816_2048_64_12.dat"
-- QD-GOPPA [3328, 2560, 64, 12] --
-- gf_2_m : integer range 1 to 20 := 12;
-- final_degree : integer := 64;
-- size_final_degree : integer := 6;
-- sigma_memory_file : string := "mceliece/data_tests/sigma_qdgoppa_3328_2560_64_12.dat";
-- dump_sigma_memory_file : string := "mceliece/data_tests/dump_sigma_qdgoppa_3328_2560_64_12.dat";
-- syndrome_memory_file : string := "mceliece/data_tests/syndrome_qdgoppa_3328_2560_64_12.dat"
-- QD-GOPPA [7296, 5632, 128, 13] --
-- gf_2_m : integer range 1 to 20 := 13;
-- final_degree : integer := 128;
-- size_final_degree : integer := 7;
-- sigma_memory_file : string := "mceliece/data_tests/sigma_qdgoppa_7296_5632_128_13.dat";
-- dump_sigma_memory_file : string := "mceliece/data_tests/dump_sigma_qdgoppa_7296_5632_128_13.dat";
-- syndrome_memory_file : string := "mceliece/data_tests/syndrome_qdgoppa_7296_5632_128_13.dat"
);
end tb_solving_key_equation_1_v2;
architecture Behavioral of tb_solving_key_equation_1_v2 is
component solving_key_equation_1_v2
Generic(
gf_2_m : integer range 1 to 20 := 11;
final_degree : integer;
size_final_degree : integer
);
Port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
ready_inv : in STD_LOGIC;
value_FB : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_GC : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_inv : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal_inv : out STD_LOGIC;
key_equation_found : out STD_LOGIC;
write_enable_FB : out STD_LOGIC;
write_enable_GC : out STD_LOGIC;
new_value_inv : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_FB : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_GC : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
address_FB : out STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
address_GC : out STD_LOGIC_VECTOR((size_final_degree + 1) downto 0)
);
end component;
component ram
Generic (
ram_address_size : integer;
ram_word_size : integer;
file_ram_word_size : integer;
load_file_name : string := "ram.dat";
dump_file_name : string := "ram.dat"
);
Port (
data_in : in STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
rw : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
dump : in STD_LOGIC;
address : in STD_LOGIC_VECTOR ((ram_address_size - 1) downto 0);
rst_value : in STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
data_out : out STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0)
);
end component;
component inv_gf_2_m_pipeline
Generic(gf_2_m : integer range 1 to 20 := 20);
Port(
a : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
flag : in STD_LOGIC;
clk : in STD_LOGIC;
oflag : out STD_LOGIC;
o : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0)
);
end component;
signal clk : STD_LOGIC := '0';
signal rst : STD_LOGIC;
signal ready_inv : STD_LOGIC;
signal test_value_FB : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal test_value_GC : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal value_inv : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal signal_inv : STD_LOGIC;
signal key_equation_found : STD_LOGIC;
signal test_write_enable_FB : STD_LOGIC;
signal test_write_enable_GC : STD_LOGIC;
signal new_value_inv : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal new_value_FB : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal new_value_GC : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal test_address_FB : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal test_address_GC : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal address_FB : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal address_GC : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal write_enable_FB : STD_LOGIC;
signal write_enable_GC : STD_LOGIC;
signal true_value_GC : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal true_address_FB : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal true_address_GC : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal test_error : STD_LOGIC;
signal dump_sigma_memory : STD_LOGIC;
signal test_bench_finish : STD_LOGIC := '0';
signal cycle_count : integer range 0 to 2000000000 := 0;
for syndrome_memory : ram use entity work.ram(file_load);
for test_sigma_memory : ram use entity work.ram(simple);
for true_sigma_memory : ram use entity work.ram(file_load);
begin
test : solving_key_equation_1_v2
Generic Map(
gf_2_m => gf_2_m,
final_degree => final_degree,
size_final_degree => size_final_degree
)
Port Map(
clk => clk,
rst => rst,
ready_inv => ready_inv,
value_FB => test_value_FB,
value_GC => test_value_GC,
value_inv => value_inv,
signal_inv => signal_inv,
key_equation_found => key_equation_found,
write_enable_FB => test_write_enable_FB,
write_enable_GC => test_write_enable_GC,
new_value_inv => new_value_inv,
new_value_FB => new_value_FB,
new_value_GC => new_value_GC,
address_FB => test_address_FB,
address_GC => test_address_GC
);
syndrome_memory : ram
Generic Map(
ram_address_size => size_final_degree+2,
ram_word_size => gf_2_m,
file_ram_word_size => gf_2_m,
load_file_name => syndrome_memory_file,
dump_file_name => ""
)
Port Map(
data_in => new_value_FB,
rw => test_write_enable_FB,
clk => clk,
rst => rst,
dump => '0',
address => address_FB,
rst_value => (others => '0'),
data_out => test_value_FB
);
test_sigma_memory : ram
Generic Map(
ram_address_size => size_final_degree+2,
ram_word_size => gf_2_m,
file_ram_word_size => gf_2_m,
load_file_name => "",
dump_file_name => dump_sigma_memory_file
)
Port Map(
data_in => new_value_GC,
rw => write_enable_GC,
clk => clk,
rst => rst,
dump => dump_sigma_memory,
address => address_GC,
rst_value => (others => '0'),
data_out => test_value_GC
);
true_sigma_memory : ram
Generic Map(
ram_address_size => size_final_degree+2,
ram_word_size => gf_2_m,
file_ram_word_size => gf_2_m,
load_file_name => sigma_memory_file,
dump_file_name => ""
)
Port Map(
data_in => (others => '0'),
rw => '0',
clk => clk,
rst => rst,
dump => '0',
address => true_address_GC,
rst_value => (others => '0'),
data_out => true_value_GC
);
inverter : inv_gf_2_m_pipeline
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => new_value_inv,
flag => signal_inv,
clk => clk,
oflag => ready_inv,
o => value_inv
);
clock : process
begin
while ( test_bench_finish /= '1') loop
clk <= not clk;
wait for PERIOD/2;
cycle_count <= cycle_count+1;
end loop;
wait;
end process;
address_FB <= true_address_FB when key_equation_found = '1' else test_address_FB;
address_GC <= true_address_GC when key_equation_found = '1' else test_address_GC;
write_enable_FB <= '0' when key_equation_found = '1' else test_write_enable_FB;
write_enable_GC <= '0' when key_equation_found = '1' else test_write_enable_GC;
process
variable i : integer;
begin
true_address_FB <= (others => '0');
true_address_GC <= (others => '0');
rst <= '1';
test_error <= '0';
dump_sigma_memory <= '0';
wait for PERIOD*2;
rst <= '0';
wait until key_equation_found = '1';
report "Circuit finish = " & integer'image((cycle_count - 2)/2) & " cycles";
wait for PERIOD;
i := 0;
while (i < (final_degree + 1)) loop
true_address_FB <= std_logic_vector(to_unsigned(i, true_address_FB'Length));
true_address_GC <= std_logic_vector(to_unsigned(i, true_address_GC'Length));
wait for PERIOD*2;
if (true_value_GC = test_value_GC) then
test_error <= '0';
else
test_error <= '1';
report "Computed values do not match expected ones";
end if;
wait for PERIOD;
test_error <= '0';
wait for PERIOD;
i := i + 1;
end loop;
dump_sigma_memory <= '1';
wait for PERIOD;
dump_sigma_memory <= '0';
test_bench_finish <= '1';
wait;
end process;
end Behavioral;
|
bsd-2-clause
|
pmassolino/hw-goppa-mceliece
|
mceliece/util/synth_double_ram.vhd
|
1
|
2857
|
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Synth Double RAM
-- Module Name: Synth Double RAM
-- Project Name: Essentials
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- Circuit to simulate the behavior of a double synthesizable RAM.
--
-- The circuits parameters
--
-- ram_address_size :
--
-- Address size of the synthesizable RAM used on the circuit.
--
-- ram_word_size :
--
-- The size of internal word on the synthesizable RAM.
--
--
-- Dependencies:
-- VHDL-93
-- IEEE.NUMERIC_STD.ALL;
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity synth_double_ram is
Generic (
ram_address_size : integer;
ram_word_size : integer
);
Port (
data_in_a : in STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
data_in_b : in STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
rw_a : in STD_LOGIC;
rw_b : in STD_LOGIC;
clk : in STD_LOGIC;
address_a : in STD_LOGIC_VECTOR ((ram_address_size - 1) downto 0);
address_b : in STD_LOGIC_VECTOR ((ram_address_size - 1) downto 0);
data_out_a : out STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
data_out_b : out STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0)
);
end synth_double_ram;
architecture Behavioral of synth_double_ram is
type ramtype is array(0 to (2**ram_address_size - 1)) of std_logic_vector((ram_word_size - 1) downto 0);
shared variable memory_ram : ramtype;
begin
process (clk)
begin
if clk'event and clk = '1' then
if rw_a = '1' then
memory_ram(to_integer(unsigned(address_a))) := data_in_a((ram_word_size - 1) downto (0));
end if;
data_out_a((ram_word_size - 1) downto (0)) <= memory_ram(to_integer(unsigned(address_a)));
end if;
end process;
process (clk)
begin
if clk'event and clk = '1' then
if rw_b = '1' then
memory_ram(to_integer(unsigned(address_b))) := data_in_b((ram_word_size - 1) downto (0));
end if;
data_out_b((ram_word_size - 1) downto (0)) <= memory_ram(to_integer(unsigned(address_b)));
end if;
end process;
end Behavioral;
|
bsd-2-clause
|
pmassolino/hw-goppa-mceliece
|
mceliece/util/register_rst_nbits.vhd
|
1
|
1471
|
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Register_rst_n_bits
-- Module Name: Register_rst_n_bits
-- Project Name: Essentials
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- Register of size bits with reset signal, that only registers when ce equals to 1.
-- The reset is synchronous and the value loaded during reset is defined by reset_value.
--
-- The circuits parameters
--
-- size :
--
-- The size of the register in bits.
--
-- Dependencies:
-- VHDL-93
--
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity register_rst_nbits is
Generic (size : integer);
Port (
d : in STD_LOGIC_VECTOR ((size - 1) downto 0);
clk : in STD_LOGIC;
ce : in STD_LOGIC;
rst : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR ((size - 1) downto 0);
q : out STD_LOGIC_VECTOR ((size - 1) downto 0)
);
end register_rst_nbits;
architecture Behavioral of register_rst_nbits is
begin
process(clk, ce, rst)
begin
if(clk'event and clk = '1')then
if(rst = '1') then
q <= rst_value;
elsif(ce = '1') then
q <= d;
else
null;
end if;
end if;
end process;
end Behavioral;
|
bsd-2-clause
|
pmassolino/hw-goppa-mceliece
|
mceliece/controller_codeword_generator_3.vhd
|
1
|
17501
|
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Controller_Codeword_Generator_3
-- Module Name: Controller_Codeword_Generator_3
-- Project Name: 1st Step - Codeword Generation
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- The first and only step in QD-Goppa Code encoding.
-- This circuit is the state machine controller for Codeword_Generator_n_m_v3.
-- The state machine is composed of two operations: one to copy the
-- original message and another for multiplying the message by matrix A.
-- Both operations happen at the same time.
-- This matrix multiplication is designed for matrices composed of dyadic blocks.
-- The algorithm computes one dyadic matrix at time.
-- Each dyadic matrix is computed in a column wise strategy.
--
-- Dependencies:
-- VHDL-93
--
-- Revision:
-- Revision 1.00
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity controller_codeword_generator_3 is
Port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
limit_ctr_dyadic_column_q : in STD_LOGIC;
limit_ctr_dyadic_row_q : in STD_LOGIC;
limit_ctr_address_message_q : in STD_LOGIC;
limit_ctr_address_codeword_q : in STD_LOGIC;
zero_ctr_address_message_q : in STD_LOGIC;
write_enable_new_codeword : out STD_LOGIC;
write_enable_new_codeword_copy : out STD_LOGIC;
external_matrix_ce : out STD_LOGIC;
reg_codeword_ce : out STD_LOGIC;
reg_codeword_rst : out STD_LOGIC;
reg_message_ce : out STD_LOGIC;
reg_matrix_ce : out STD_LOGIC;
ctr_dyadic_column_ce : out STD_LOGIC;
ctr_dyadic_column_rst : out STD_LOGIC;
ctr_dyadic_row_ce : out STD_LOGIC;
ctr_dyadic_row_rst : out STD_LOGIC;
ctr_dyadic_matrices_ce : out STD_LOGIC;
ctr_dyadic_matrices_rst : out STD_LOGIC;
ctr_address_base_message_ce : out STD_LOGIC;
ctr_address_base_message_rst : out STD_LOGIC;
ctr_address_base_codeword_ce : out STD_LOGIC;
ctr_address_base_codeword_rst : out STD_LOGIC;
reg_address_new_codeword_copy_ce : out STD_LOGIC;
internal_codeword : out STD_LOGIC;
codeword_finalized : out STD_LOGIC
);
end controller_codeword_generator_3;
architecture Behavioral of controller_codeword_generator_3 is
type State is (reset, load_counter, prepare_counters, load_acc, load_acc_entire_matrix, calc_codeword, last_column_value, write_last_column_value, last_row_value, write_last_row_value, last_value, write_last_value, final);
signal actual_state, next_state : State;
begin
Clock: process (clk)
begin
if (clk'event and clk = '1') then
if (rst = '1') then
actual_state <= reset;
else
actual_state <= next_state;
end if;
end if;
end process;
Output: process (actual_state, limit_ctr_dyadic_column_q, limit_ctr_dyadic_row_q, limit_ctr_address_message_q, limit_ctr_address_codeword_q, zero_ctr_address_message_q)
begin
case (actual_state) is
when reset =>
write_enable_new_codeword <= '0';
write_enable_new_codeword_copy <= '0';
external_matrix_ce <= '0';
reg_codeword_ce <= '0';
reg_codeword_rst <= '1';
reg_message_ce <= '0';
reg_matrix_ce <= '0';
ctr_dyadic_column_ce <= '0';
ctr_dyadic_column_rst <= '1';
ctr_dyadic_row_ce <= '0';
ctr_dyadic_row_rst <= '1';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '1';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '1';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '1';
reg_address_new_codeword_copy_ce <= '0';
internal_codeword <= '0';
codeword_finalized <= '0';
when load_counter =>
write_enable_new_codeword <= '0';
write_enable_new_codeword_copy <= '0';
external_matrix_ce <= '0';
reg_codeword_ce <= '0';
reg_codeword_rst <= '1';
reg_message_ce <= '0';
reg_matrix_ce <= '0';
ctr_dyadic_column_ce <= '0';
ctr_dyadic_column_rst <= '1';
ctr_dyadic_row_ce <= '0';
ctr_dyadic_row_rst <= '1';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '1';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '1';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '0';
reg_address_new_codeword_copy_ce <= '1';
internal_codeword <= '0';
codeword_finalized <= '0';
when prepare_counters =>
write_enable_new_codeword <= '0';
write_enable_new_codeword_copy <= '0';
external_matrix_ce <= '1';
reg_codeword_ce <= '0';
reg_codeword_rst <= '0';
reg_message_ce <= '0';
reg_matrix_ce <= '0';
ctr_dyadic_column_ce <= '0';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '1';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '0';
reg_address_new_codeword_copy_ce <= '1';
internal_codeword <= '0';
codeword_finalized <= '0';
when load_acc =>
if(zero_ctr_address_message_q = '1') then
write_enable_new_codeword <= '0';
write_enable_new_codeword_copy <= '1';
external_matrix_ce <= '0';
reg_codeword_ce <= '0';
reg_codeword_rst <= '1';
reg_message_ce <= '1';
reg_matrix_ce <= '1';
ctr_dyadic_column_ce <= '0';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '1';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '0';
reg_address_new_codeword_copy_ce <= '1';
internal_codeword <= '0';
codeword_finalized <= '0';
else
write_enable_new_codeword <= '0';
write_enable_new_codeword_copy <= '1';
external_matrix_ce <= '0';
reg_codeword_ce <= '1';
reg_codeword_rst <= '0';
reg_message_ce <= '1';
reg_matrix_ce <= '1';
ctr_dyadic_column_ce <= '0';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '1';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '0';
reg_address_new_codeword_copy_ce <= '1';
internal_codeword <= '0';
codeword_finalized <= '0';
end if;
when load_acc_entire_matrix =>
if(zero_ctr_address_message_q = '1') then
write_enable_new_codeword <= '0';
write_enable_new_codeword_copy <= '1';
external_matrix_ce <= '0';
reg_codeword_ce <= '0';
reg_codeword_rst <= '1';
reg_message_ce <= '1';
reg_matrix_ce <= '1';
ctr_dyadic_column_ce <= '0';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '0';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '1';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '0';
reg_address_new_codeword_copy_ce <= '0';
internal_codeword <= '0';
codeword_finalized <= '0';
else
write_enable_new_codeword <= '0';
write_enable_new_codeword_copy <= '1';
external_matrix_ce <= '0';
reg_codeword_ce <= '1';
reg_codeword_rst <= '0';
reg_message_ce <= '1';
reg_matrix_ce <= '1';
ctr_dyadic_column_ce <= '0';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '0';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '1';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '0';
reg_address_new_codeword_copy_ce <= '0';
internal_codeword <= '0';
codeword_finalized <= '0';
end if;
when calc_codeword =>
write_enable_new_codeword <= '0';
write_enable_new_codeword_copy <= '1';
external_matrix_ce <= '0';
reg_codeword_ce <= '1';
reg_codeword_rst <= '0';
reg_message_ce <= '1';
reg_matrix_ce <= '1';
ctr_dyadic_column_ce <= '0';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '1';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '0';
reg_address_new_codeword_copy_ce <= '1';
internal_codeword <= '1';
codeword_finalized <= '0';
when last_row_value =>
write_enable_new_codeword <= '0';
write_enable_new_codeword_copy <= '1';
external_matrix_ce <= '0';
reg_codeword_ce <= '1';
reg_codeword_rst <= '0';
reg_message_ce <= '1';
reg_matrix_ce <= '1';
ctr_dyadic_column_ce <= '0';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '0';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '0';
reg_address_new_codeword_copy_ce <= '1';
internal_codeword <= '1';
codeword_finalized <= '0';
when write_last_row_value =>
write_enable_new_codeword <= '1';
write_enable_new_codeword_copy <= '0';
external_matrix_ce <= '0';
reg_codeword_ce <= '0';
reg_codeword_rst <= '0';
reg_message_ce <= '0';
reg_matrix_ce <= '0';
ctr_dyadic_column_ce <= '1';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '0';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '0';
reg_address_new_codeword_copy_ce <= '0';
internal_codeword <= '0';
codeword_finalized <= '0';
when last_column_value =>
write_enable_new_codeword <= '0';
write_enable_new_codeword_copy <= '1';
external_matrix_ce <= '0';
reg_codeword_ce <= '1';
reg_codeword_rst <= '0';
reg_message_ce <= '1';
reg_matrix_ce <= '1';
ctr_dyadic_column_ce <= '0';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '0';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '1';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '0';
reg_address_new_codeword_copy_ce <= '1';
internal_codeword <= '1';
codeword_finalized <= '0';
when write_last_column_value =>
if(limit_ctr_address_codeword_q = '1') then
write_enable_new_codeword <= '1';
write_enable_new_codeword_copy <= '0';
external_matrix_ce <= '0';
reg_codeword_ce <= '0';
reg_codeword_rst <= '0';
reg_message_ce <= '0';
reg_matrix_ce <= '0';
ctr_dyadic_column_ce <= '1';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '0';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '1';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '1';
reg_address_new_codeword_copy_ce <= '0';
internal_codeword <= '0';
codeword_finalized <= '0';
else
write_enable_new_codeword <= '1';
write_enable_new_codeword_copy <= '0';
external_matrix_ce <= '0';
reg_codeword_ce <= '0';
reg_codeword_rst <= '0';
reg_message_ce <= '0';
reg_matrix_ce <= '0';
ctr_dyadic_column_ce <= '1';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '0';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '1';
ctr_address_base_codeword_rst <= '0';
reg_address_new_codeword_copy_ce <= '0';
internal_codeword <= '0';
codeword_finalized <= '0';
end if;
when last_value =>
write_enable_new_codeword <= '0';
write_enable_new_codeword_copy <= '1';
external_matrix_ce <= '0';
reg_codeword_ce <= '1';
reg_codeword_rst <= '0';
reg_message_ce <= '1';
reg_matrix_ce <= '1';
ctr_dyadic_column_ce <= '0';
ctr_dyadic_column_rst <= '0';
ctr_dyadic_row_ce <= '0';
ctr_dyadic_row_rst <= '0';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '0';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '0';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '0';
reg_address_new_codeword_copy_ce <= '0';
internal_codeword <= '1';
codeword_finalized <= '0';
when write_last_value =>
write_enable_new_codeword <= '1';
write_enable_new_codeword_copy <= '0';
external_matrix_ce <= '0';
reg_codeword_ce <= '0';
reg_codeword_rst <= '1';
reg_message_ce <= '0';
reg_matrix_ce <= '0';
ctr_dyadic_column_ce <= '0';
ctr_dyadic_column_rst <= '1';
ctr_dyadic_row_ce <= '0';
ctr_dyadic_row_rst <= '1';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '1';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '1';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '1';
reg_address_new_codeword_copy_ce <= '0';
internal_codeword <= '0';
codeword_finalized <= '0';
when final =>
write_enable_new_codeword <= '0';
write_enable_new_codeword_copy <= '0';
external_matrix_ce <= '0';
reg_codeword_ce <= '0';
reg_codeword_rst <= '1';
reg_message_ce <= '0';
reg_matrix_ce <= '0';
ctr_dyadic_column_ce <= '0';
ctr_dyadic_column_rst <= '1';
ctr_dyadic_row_ce <= '0';
ctr_dyadic_row_rst <= '1';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '1';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '1';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '1';
reg_address_new_codeword_copy_ce <= '0';
internal_codeword <= '0';
codeword_finalized <= '1';
when others =>
write_enable_new_codeword <= '0';
write_enable_new_codeword_copy <= '0';
external_matrix_ce <= '0';
reg_codeword_ce <= '0';
reg_codeword_rst <= '1';
reg_message_ce <= '0';
reg_matrix_ce <= '0';
ctr_dyadic_column_ce <= '0';
ctr_dyadic_column_rst <= '1';
ctr_dyadic_row_ce <= '0';
ctr_dyadic_row_rst <= '1';
ctr_dyadic_matrices_ce <= '0';
ctr_dyadic_matrices_rst <= '1';
ctr_address_base_message_ce <= '0';
ctr_address_base_message_rst <= '1';
ctr_address_base_codeword_ce <= '0';
ctr_address_base_codeword_rst <= '1';
reg_address_new_codeword_copy_ce <= '0';
internal_codeword <= '0';
codeword_finalized <= '0';
end case;
end process;
NewState : process(actual_state, limit_ctr_dyadic_column_q, limit_ctr_dyadic_row_q, limit_ctr_address_message_q, limit_ctr_address_codeword_q)
begin
case (actual_state) is
when reset =>
next_state <= load_counter;
when load_counter =>
next_state <= prepare_counters;
when prepare_counters =>
if(limit_ctr_dyadic_row_q = '1') then
next_state <= load_acc_entire_matrix;
else
next_state <= load_acc;
end if;
when load_acc =>
if(limit_ctr_dyadic_row_q = '1') then
if(limit_ctr_dyadic_column_q = '1') then
if(limit_ctr_address_message_q = '1') then
if(limit_ctr_address_codeword_q = '1') then
next_state <= last_value;
else
next_state <= last_column_value;
end if;
else
next_state <= last_column_value;
end if;
else
next_state <= last_row_value;
end if;
else
next_state <= calc_codeword;
end if;
when load_acc_entire_matrix =>
if(limit_ctr_dyadic_column_q = '1') then
if(limit_ctr_address_message_q = '1') then
if(limit_ctr_address_codeword_q = '1') then
next_state <= write_last_value;
else
next_state <= write_last_column_value;
end if;
else
next_state <= write_last_column_value;
end if;
else
next_state <= write_last_row_value;
end if;
when calc_codeword =>
if(limit_ctr_dyadic_row_q = '1') then
if(limit_ctr_dyadic_column_q = '1') then
if(limit_ctr_address_message_q = '1') then
if(limit_ctr_address_codeword_q = '1') then
next_state <= last_value;
else
next_state <= last_column_value;
end if;
else
next_state <= last_column_value;
end if;
else
next_state <= last_row_value;
end if;
else
next_state <= calc_codeword;
end if;
when last_column_value =>
next_state <= write_last_column_value;
when write_last_column_value =>
next_state <= prepare_counters;
when last_row_value =>
next_state <= write_last_row_value;
when write_last_row_value =>
next_state <= prepare_counters;
when last_value =>
next_state <= write_last_value;
when write_last_value =>
next_state <= final;
when final =>
next_state <= final;
when others =>
next_state <= reset;
end case;
end process;
end Behavioral;
|
bsd-2-clause
|
pmassolino/hw-goppa-mceliece
|
mceliece/util/shift_register_rst_nbits.vhd
|
1
|
1705
|
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Shift_Register_rst_n_bits
-- Module Name: Shift_Register_rst_n_bits
-- Project Name: Essentials
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- Shift Register of size bits with reset signal, that only registers when ce equals to 1.
-- The reset is synchronous and the value loaded during reset is defined by reset_value.
--
-- The circuits parameters
--
-- size :
--
-- The size of the register in bits.
--
-- Dependencies:
-- VHDL-93
--
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity shift_register_rst_nbits is
Generic (size : integer);
Port (
data_in : in STD_LOGIC;
clk : in STD_LOGIC;
ce : in STD_LOGIC;
rst : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR ((size - 1) downto 0);
q : out STD_LOGIC_VECTOR ((size - 1) downto 0);
data_out : out STD_LOGIC
);
end shift_register_rst_nbits;
architecture Behavioral of shift_register_rst_nbits is
signal internal_value : STD_LOGIC_VECTOR((size - 1) downto 0);
begin
process(clk, ce, rst)
begin
if(clk'event and clk = '1')then
if(rst = '1') then
internal_value <= rst_value;
elsif(ce = '1') then
internal_value <= internal_value((size - 2) downto 0) & data_in;
else
null;
end if;
end if;
end process;
data_out <= internal_value(size - 1);
q <= internal_value;
end Behavioral;
|
bsd-2-clause
|
pmassolino/hw-goppa-mceliece
|
mceliece/backup/controller_polynomial_evaluator.vhd
|
1
|
15145
|
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Controller_Polynomial_Evaluator
-- Module Name: Controller_Polynomial_Evaluator
-- Project Name: McEliece Goppa Decoder
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- The 3rd step in Goppa Code Decoding.
--
-- This circuit is the state machine to control both polynomial_evaluator_n and
-- polynomial_evaluator_n_v2. Because both circuits have similar behavioral on
-- how the registers are loaded, they can share the same state machine.
-- The difference is how each pipeline computes inside each, which does not matter
-- for state machine inner workings.
--
-- This state machine works by preparing the pipeline by loading the polynomial
-- coefficients and respective first values to be evaluated. Then it loads the
-- remaining evaluated values. When there are no more values to be evaluated,
-- it restarts loading the values to be evaluated and the remaining polynomial
-- coefficients.
--
-- Dependencies:
-- VHDL-93
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity controller_polynomial_evaluator is
Port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
last_load_x_values : in STD_LOGIC;
last_store_x_values : in STD_LOGIC;
limit_polynomial_degree : in STD_LOGIC;
pipeline_ready : in STD_LOGIC;
evaluation_data_in : out STD_LOGIC;
reg_write_enable_rst : out STD_LOGIC;
ctr_load_x_address_ce : out STD_LOGIC;
ctr_load_x_address_rst : out STD_LOGIC;
ctr_store_x_address_ce : out STD_LOGIC;
ctr_store_x_address_rst : out STD_LOGIC;
reg_first_values_ce : out STD_LOGIC;
reg_first_values_rst : out STD_LOGIC;
ctr_address_polynomial_ce : out STD_LOGIC;
ctr_address_polynomial_rst : out STD_LOGIC;
reg_x_rst_rst : out STD_LOGIC;
shift_polynomial_ce_ce : out STD_LOGIC;
shift_polynomial_ce_rst : out STD_LOGIC;
last_coefficients : out STD_LOGIC;
evaluation_finalized : out STD_LOGIC
);
end controller_polynomial_evaluator;
architecture Behavioral of controller_polynomial_evaluator is
type State is (reset, load_counter, load_first_polynomial_coefficient, reset_first_polynomial_coefficient, prepare_load_polynomial_coefficient, load_polynomial_coefficient, reset_polynomial_coefficient, load_x_write_x, last_load_x_write_x, write_x, final);
signal actual_state, next_state : State;
begin
Clock: process (clk)
begin
if (clk'event and clk = '1') then
if (rst = '1') then
actual_state <= reset;
else
actual_state <= next_state;
end if;
end if;
end process;
Output: process (actual_state, last_load_x_values, last_store_x_values, limit_polynomial_degree, pipeline_ready)
begin
case (actual_state) is
when reset =>
evaluation_data_in <= '0';
reg_write_enable_rst <= '1';
ctr_load_x_address_ce <= '0';
ctr_load_x_address_rst <= '1';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '1';
reg_first_values_ce <= '0';
reg_first_values_rst <= '1';
ctr_address_polynomial_ce <= '0';
ctr_address_polynomial_rst <= '1';
reg_x_rst_rst <= '1';
shift_polynomial_ce_ce <= '0';
shift_polynomial_ce_rst <= '1';
last_coefficients <= '0';
evaluation_finalized <= '0';
when load_counter =>
evaluation_data_in <= '0';
reg_write_enable_rst <= '1';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_ce <= '1';
ctr_address_polynomial_rst <= '0';
reg_x_rst_rst <= '0';
shift_polynomial_ce_ce <= '0';
shift_polynomial_ce_rst <= '0';
last_coefficients <= '0';
evaluation_finalized <= '0';
when load_first_polynomial_coefficient =>
if(pipeline_ready = '1') then
evaluation_data_in <= '1';
reg_write_enable_rst <= '0';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_ce <= '0';
ctr_address_polynomial_rst <= '0';
reg_x_rst_rst <= '0';
shift_polynomial_ce_ce <= '1';
shift_polynomial_ce_rst <= '0';
last_coefficients <= '0';
evaluation_finalized <= '0';
elsif(limit_polynomial_degree = '1') then
evaluation_data_in <= '1';
reg_write_enable_rst <= '1';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_ce <= '0';
ctr_address_polynomial_rst <= '0';
reg_x_rst_rst <= '0';
shift_polynomial_ce_ce <= '1';
shift_polynomial_ce_rst <= '0';
last_coefficients <= '0';
evaluation_finalized <= '0';
else
evaluation_data_in <= '1';
reg_write_enable_rst <= '1';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_ce <= '1';
ctr_address_polynomial_rst <= '0';
reg_x_rst_rst <= '0';
shift_polynomial_ce_ce <= '1';
shift_polynomial_ce_rst <= '0';
last_coefficients <= '0';
evaluation_finalized <= '0';
end if;
when reset_first_polynomial_coefficient =>
if(pipeline_ready = '1') then
evaluation_data_in <= '1';
reg_write_enable_rst <= '0';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_ce <= '0';
ctr_address_polynomial_rst <= '0';
reg_x_rst_rst <= '0';
shift_polynomial_ce_ce <= '1';
shift_polynomial_ce_rst <= '0';
last_coefficients <= '1';
evaluation_finalized <= '0';
else
evaluation_data_in <= '1';
reg_write_enable_rst <= '1';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_ce <= '0';
ctr_address_polynomial_rst <= '0';
reg_x_rst_rst <= '0';
shift_polynomial_ce_ce <= '1';
shift_polynomial_ce_rst <= '0';
last_coefficients <= '1';
evaluation_finalized <= '0';
end if;
when prepare_load_polynomial_coefficient =>
evaluation_data_in <= '1';
reg_write_enable_rst <= '0';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '1';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '1';
reg_first_values_rst <= '0';
ctr_address_polynomial_ce <= '1';
ctr_address_polynomial_rst <= '0';
reg_x_rst_rst <= '0';
shift_polynomial_ce_ce <= '1';
shift_polynomial_ce_rst <= '0';
last_coefficients <= '0';
evaluation_finalized <= '0';
when load_polynomial_coefficient =>
if(pipeline_ready = '1') then
evaluation_data_in <= '1';
reg_write_enable_rst <= '0';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '1';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_ce <= '0';
ctr_address_polynomial_rst <= '0';
reg_x_rst_rst <= '0';
shift_polynomial_ce_ce <= '1';
shift_polynomial_ce_rst <= '0';
last_coefficients <= '0';
evaluation_finalized <= '0';
elsif(limit_polynomial_degree = '1') then
evaluation_data_in <= '1';
reg_write_enable_rst <= '0';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '1';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_ce <= '0';
ctr_address_polynomial_rst <= '0';
reg_x_rst_rst <= '0';
shift_polynomial_ce_ce <= '1';
shift_polynomial_ce_rst <= '0';
last_coefficients <= '0';
evaluation_finalized <= '0';
else
evaluation_data_in <= '1';
reg_write_enable_rst <= '0';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '1';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_ce <= '1';
ctr_address_polynomial_rst <= '0';
reg_x_rst_rst <= '0';
shift_polynomial_ce_ce <= '1';
shift_polynomial_ce_rst <= '0';
last_coefficients <= '0';
evaluation_finalized <= '0';
end if;
when reset_polynomial_coefficient =>
if(pipeline_ready = '1') then
evaluation_data_in <= '1';
reg_write_enable_rst <= '0';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '1';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_ce <= '0';
ctr_address_polynomial_rst <= '0';
reg_x_rst_rst <= '0';
shift_polynomial_ce_ce <= '1';
shift_polynomial_ce_rst <= '0';
last_coefficients <= '1';
evaluation_finalized <= '0';
else
evaluation_data_in <= '1';
reg_write_enable_rst <= '0';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '1';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_ce <= '0';
ctr_address_polynomial_rst <= '0';
reg_x_rst_rst <= '0';
shift_polynomial_ce_ce <= '1';
shift_polynomial_ce_rst <= '0';
last_coefficients <= '1';
evaluation_finalized <= '0';
end if;
when load_x_write_x =>
if(last_load_x_values = '1' and limit_polynomial_degree = '0') then
evaluation_data_in <= '1';
reg_write_enable_rst <= '0';
ctr_load_x_address_ce <= '0';
ctr_load_x_address_rst <= '1';
ctr_store_x_address_ce <= '1';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_ce <= '0';
ctr_address_polynomial_rst <= '0';
reg_x_rst_rst <= '0';
shift_polynomial_ce_ce <= '0';
shift_polynomial_ce_rst <= '0';
last_coefficients <= '0';
evaluation_finalized <= '0';
else
evaluation_data_in <= '1';
reg_write_enable_rst <= '0';
ctr_load_x_address_ce <= '1';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '1';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_ce <= '0';
ctr_address_polynomial_rst <= '0';
reg_x_rst_rst <= '0';
shift_polynomial_ce_ce <= '0';
shift_polynomial_ce_rst <= '0';
last_coefficients <= '0';
evaluation_finalized <= '0';
end if;
when last_load_x_write_x =>
evaluation_data_in <= '1';
reg_write_enable_rst <= '0';
ctr_load_x_address_ce <= '0';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '1';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_ce <= '0';
ctr_address_polynomial_rst <= '0';
reg_x_rst_rst <= '0';
shift_polynomial_ce_ce <= '0';
shift_polynomial_ce_rst <= '0';
last_coefficients <= '0';
evaluation_finalized <= '0';
when write_x =>
evaluation_data_in <= '0';
reg_write_enable_rst <= '0';
ctr_load_x_address_ce <= '0';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '1';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_ce <= '0';
ctr_address_polynomial_rst <= '0';
reg_x_rst_rst <= '0';
shift_polynomial_ce_ce <= '0';
shift_polynomial_ce_rst <= '0';
last_coefficients <= '0';
evaluation_finalized <= '0';
when final =>
evaluation_data_in <= '1';
reg_write_enable_rst <= '1';
ctr_load_x_address_ce <= '0';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_ce <= '0';
ctr_address_polynomial_rst <= '0';
reg_x_rst_rst <= '0';
shift_polynomial_ce_ce <= '0';
shift_polynomial_ce_rst <= '0';
last_coefficients <= '0';
evaluation_finalized <= '1';
when others =>
evaluation_data_in <= '1';
reg_write_enable_rst <= '1';
ctr_load_x_address_ce <= '0';
ctr_load_x_address_rst <= '0';
ctr_store_x_address_ce <= '0';
ctr_store_x_address_rst <= '0';
reg_first_values_ce <= '0';
reg_first_values_rst <= '0';
ctr_address_polynomial_ce <= '0';
ctr_address_polynomial_rst <= '0';
reg_x_rst_rst <= '0';
shift_polynomial_ce_ce <= '0';
shift_polynomial_ce_rst <= '0';
last_coefficients <= '0';
evaluation_finalized <= '0';
end case;
end process;
NewState: process (actual_state, last_load_x_values, last_store_x_values, limit_polynomial_degree, pipeline_ready)
begin
case (actual_state) is
when reset =>
next_state <= load_counter;
when load_counter =>
next_state <= load_first_polynomial_coefficient;
when load_first_polynomial_coefficient =>
if(pipeline_ready = '1') then
next_state <= load_x_write_x;
elsif(limit_polynomial_degree = '1') then
next_state <= reset_first_polynomial_coefficient;
else
next_state <= load_first_polynomial_coefficient;
end if;
when reset_first_polynomial_coefficient =>
if(pipeline_ready = '1') then
next_state <= load_x_write_x;
else
next_state <= reset_first_polynomial_coefficient;
end if;
when prepare_load_polynomial_coefficient =>
next_state <= load_polynomial_coefficient;
when load_polynomial_coefficient =>
if(pipeline_ready = '1') then
next_state <= load_x_write_x;
elsif(limit_polynomial_degree = '1') then
next_state <= reset_polynomial_coefficient;
else
next_state <= load_polynomial_coefficient;
end if;
when reset_polynomial_coefficient =>
if(pipeline_ready = '1') then
next_state <= load_x_write_x;
else
next_state <= reset_polynomial_coefficient;
end if;
when load_x_write_x =>
if(last_load_x_values = '1') then
if(limit_polynomial_degree = '1') then
next_state <= last_load_x_write_x;
else
next_state <= prepare_load_polynomial_coefficient;
end if;
else
next_state <= load_x_write_x;
end if;
when last_load_x_write_x =>
next_state <= write_x;
when write_x =>
if(last_store_x_values = '1') then
next_state <= final;
else
next_state <= write_x;
end if;
when final =>
next_state <= final;
when others =>
next_state <= reset;
end case;
end process;
end Behavioral;
|
bsd-2-clause
|
pmassolino/hw-goppa-mceliece
|
mceliece/backup/tb_mceliece_qd_goppa_decrypt_v2.vhd
|
1
|
32099
|
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Tb_McEliece_QD-Goppa_Decrypt_v2
-- Module Name: Tb_McEliece_QD-Goppa_Decrypt_v2
-- Project Name: McEliece Goppa Decryption
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- This test bench tests mceliece_qd_goppa_decrypt_v2 circuit.
-- The test is done only for one value loaded into memories, and in the end the output
-- memories are verified.
--
-- The circuits parameters
--
-- PERIOD :
--
-- Input clock period to be applied on the test.
--
-- number_of_polynomial_evaluator_syndrome_pipelines :
--
-- The number of pipelines in polynomial_syndrome_computing_n circuit.
-- This number can be 1 or greater.
--
-- polynomial_evaluator_syndrome_pipeline_size :
--
-- This is the number of stages on polynomial_syndrome_computing_n circuit.
-- This number can be 2 or greater.
--
-- polynomial_evaluator_syndrome_size_pipeline_size :
--
-- The number of bits necessary to hold the number of stages on the pipeline.
-- This is ceil(log2(polynomial_evaluator_syndrome_pipeline_size))
--
-- gf_2_m :
--
-- The size of the finite field extension used in this circuit.
-- This values depends of the Goppa code used.
--
-- length_codeword :
--
-- The length of the codeword in this Goppa code.
-- This values depends of the Goppa code used.
--
-- size_codeword :
--
-- The number of bits necessary to store an array of codeword lengths.
-- This is ceil(log2(length_codeword))
--
-- number_of_errors :
--
-- The number of errors the Goppa code is able to decode.
-- This values depends of the Goppa code used.
--
-- size_number_of_errors :
--
-- The number of bits necessary to store an array of number of errors + 1 length.
-- This is ceil(log2(number_of_errors+1))
--
-- file_memory_L :
--
-- This file stores the private key, support elements L.
--
-- file_memory_h :
--
-- This file stores the private key, the inverted evaluation of all support elements L
-- into polynomial g, aka g(L)^(-1)
--
-- file_memory_codeword :
--
-- This file stores the ciphertext that will be decrypted.
--
-- file_memory_message :
--
-- This file stores the plaintext obtained by decrypting the ciphertext.
-- This is necessary to verify if the circuit decrypted correctly the ciphertext.
--
-- file_memory_error :
--
-- This file stores the error array added to the codeword to transform into the ciphertext.
-- This is necessary to verify if the circuit decrypted correctly the ciphertext.
--
-- Dependencies:
-- VHDL-93
-- IEEE.NUMERIC_STD_ALL;
--
-- mceliece_qd_goppa_decrypt_v2 Rev 1.0
-- ram Rev 1.0
-- ram_double Rev 1.0
-- ram_bank Rev 1.0
-- ram_double_bank Rev 1.0
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity tb_mceliece_qd_goppa_decrypt_v2 is
Generic(
PERIOD : time := 10 ns;
-- QD-GOPPA [52, 28, 4, 6] --
-- number_of_polynomial_evaluator_syndrome_pipelines : integer := 1;
-- polynomial_evaluator_syndrome_pipeline_size : integer := 18;
-- polynomial_evaluator_syndrome_size_pipeline_size : integer := 5;
-- gf_2_m : integer range 1 to 20 := 6;
-- length_codeword : integer := 52;
-- size_codeword : integer := 6;
-- number_of_errors : integer := 4;
-- size_number_of_errors : integer := 3;
-- file_memory_L : string := "mceliece/data_tests/L_qdgoppa_52_28_4_6.dat";
-- file_memory_h : string := "mceliece/data_tests/h_qdgoppa_52_28_4_6.dat";
-- file_memory_codeword : string := "mceliece/data_tests/ciphertext_qdgoppa_52_28_4_6.dat";
-- file_memory_message : string := "mceliece/data_tests/plaintext_qdgoppa_52_28_4_6.dat";
-- file_memory_error : string := "mceliece/data_tests/error_qdgoppa_52_28_4_6.dat"
-- GOPPA [2048, 1751, 27, 11] --
-- number_of_polynomial_evaluator_syndrome_pipelines : integer := 2;
-- polynomial_evaluator_syndrome_pipeline_size : integer := 8;
-- polynomial_evaluator_syndrome_size_pipeline_size : integer := 4;
-- gf_2_m : integer range 1 to 20 := 11;
-- length_codeword : integer := 2048;
-- size_codeword : integer := 11;
-- number_of_errors : integer := 27;
-- size_number_of_errors : integer := 5;
-- file_memory_L : string := "mceliece/data_tests/L_goppa_2048_1751_27_11.dat";
-- file_memory_h : string := "mceliece/data_tests/h_goppa_2048_1751_27_11.dat";
-- file_memory_codeword : string := "mceliece/data_tests/ciphertext_goppa_2048_1751_27_11.dat";
-- file_memory_message : string := "mceliece/data_tests/plaintext_goppa_2048_1751_27_11.dat";
-- file_memory_error : string := "mceliece/data_tests/error_goppa_2048_1751_27_11.dat"
-- GOPPA [2048, 1498, 50, 11] --
-- number_of_polynomial_evaluator_syndrome_pipelines : integer := 1;
-- polynomial_evaluator_syndrome_pipeline_size : integer := 18;
-- polynomial_evaluator_syndrome_size_pipeline_size : integer := 5;
-- gf_2_m : integer range 1 to 20 := 11;
-- length_codeword : integer := 2048;
-- size_codeword : integer := 11;
-- number_of_errors : integer := 50;
-- size_number_of_errors : integer := 6;
-- file_memory_L : string := "mceliece/data_tests/L_goppa_2048_1498_50_11.dat";
-- file_memory_h : string := "mceliece/data_tests/h_goppa_2048_1498_50_11.dat";
-- file_memory_codeword : string := "mceliece/data_tests/ciphertext_goppa_2048_1498_50_11.dat";
-- file_memory_message : string := "mceliece/data_tests/plaintext_goppa_2048_1498_50_11.dat";
-- file_memory_error : string := "mceliece/data_tests/error_goppa_2048_1498_50_11.dat"
-- GOPPA [3307, 2515, 66, 12] --
number_of_polynomial_evaluator_syndrome_pipelines : integer := 2;
polynomial_evaluator_syndrome_pipeline_size : integer := 17;
polynomial_evaluator_syndrome_size_pipeline_size : integer := 5;
gf_2_m : integer range 1 to 20 := 12;
length_codeword : integer := 3307;
size_codeword : integer := 12;
number_of_errors : integer := 66;
size_number_of_errors : integer := 7;
file_memory_L : string := "mceliece/data_tests/L_goppa_3307_2515_66_12.dat";
file_memory_h : string := "mceliece/data_tests/h_goppa_3307_2515_66_12.dat";
file_memory_codeword : string := "mceliece/data_tests/ciphertext_goppa_3307_2515_66_12.dat";
file_memory_message : string := "mceliece/data_tests/plaintext_goppa_3307_2515_66_12.dat";
file_memory_error : string := "mceliece/data_tests/error_goppa_3307_2515_66_12.dat"
-- QD-GOPPA [2528, 2144, 32, 12] --
-- number_of_polynomial_evaluator_syndrome_pipelines : integer := 1;
-- polynomial_evaluator_syndrome_pipeline_size : integer := 2;
-- polynomial_evaluator_syndrome_size_pipeline_size : integer := 2;
-- gf_2_m : integer range 1 to 20 := 12;
-- length_codeword : integer := 2528;
-- size_codeword : integer := 12;
-- number_of_errors : integer := 32;
-- size_number_of_errors : integer := 6;
-- file_memory_L : string := "mceliece/data_tests/L_qdgoppa_2528_2144_32_12.dat";
-- file_memory_h : string := "mceliece/data_tests/h_qdgoppa_2528_2144_32_12.dat";
-- file_memory_codeword : string := "mceliece/data_tests/ciphertext_qdgoppa_2528_2144_32_12.dat";
-- file_memory_message : string := "mceliece/data_tests/plaintext_qdgoppa_2528_2144_32_12.dat";
-- file_memory_error : string := "mceliece/data_tests/error_qdgoppa_2528_2144_32_12.dat"
-- QD-GOPPA [2816, 2048, 64, 12] --
-- number_of_polynomial_evaluator_syndrome_pipelines : integer := 1;
-- polynomial_evaluator_syndrome_pipeline_size : integer := 18;
-- polynomial_evaluator_syndrome_size_pipeline_size : integer := 5;
-- gf_2_m : integer range 1 to 20 := 12;
-- length_codeword : integer := 2816;
-- size_codeword : integer := 12;
-- number_of_errors : integer := 64;
-- size_number_of_errors : integer := 7;
-- file_memory_L : string := "mceliece/data_tests/L_qdgoppa_2816_2048_64_12.dat";
-- file_memory_h : string := "mceliece/data_tests/h_qdgoppa_2816_2048_64_12.dat";
-- file_memory_codeword : string := "mceliece/data_tests/ciphertext_qdgoppa_2816_2048_64_12.dat";
-- file_memory_message : string := "mceliece/data_tests/plaintext_qdgoppa_2816_2048_64_12.dat";
-- file_memory_error : string := "mceliece/data_tests/error_qdgoppa_2816_2048_64_12.dat"
-- QD-GOPPA [3328, 2560, 64, 12] --
-- number_of_polynomial_evaluator_syndrome_pipelines : integer := 1;
-- polynomial_evaluator_syndrome_pipeline_size : integer := 18;
-- polynomial_evaluator_syndrome_size_pipeline_size : integer := 5;
-- gf_2_m : integer range 1 to 20 := 12;
-- length_codeword : integer := 3328;
-- size_codeword : integer := 12;
-- number_of_errors : integer := 64;
-- size_number_of_errors : integer := 7;
-- file_memory_L : string := "mceliece/data_tests/L_qdgoppa_3328_2560_64_12.dat";
-- file_memory_h : string := "mceliece/data_tests/h_qdgoppa_3328_2560_64_12.dat";
-- file_memory_codeword : string := "mceliece/data_tests/ciphertext_qdgoppa_3328_2560_64_12.dat";
-- file_memory_message : string := "mceliece/data_tests/plaintext_qdgoppa_3328_2560_64_12.dat";
-- file_memory_error : string := "mceliece/data_tests/error_qdgoppa_3328_2560_64_12.dat"
-- QD-GOPPA [7296, 5632, 128, 13] --
-- number_of_polynomial_evaluator_syndrome_pipelines : integer := 2;
-- polynomial_evaluator_syndrome_pipeline_size : integer := 18;
-- polynomial_evaluator_syndrome_size_pipeline_size : integer := 5;
-- gf_2_m : integer range 1 to 20 := 13;
-- length_codeword : integer := 7296;
-- size_codeword : integer := 13;
-- number_of_errors : integer := 128;
-- size_number_of_errors : integer := 8;
-- file_memory_L : string := "mceliece/data_tests/L_qdgoppa_7296_5632_128_13.dat";
-- file_memory_h : string := "mceliece/data_tests/h_qdgoppa_7296_5632_128_13.dat";
-- file_memory_codeword : string := "mceliece/data_tests/ciphertext_qdgoppa_7296_5632_128_13.dat";
-- file_memory_message : string := "mceliece/data_tests/plaintext_qdgoppa_7296_5632_128_13.dat";
-- file_memory_error : string := "mceliece/data_tests/error_qdgoppa_7296_5632_128_13.dat"
);
end tb_mceliece_qd_goppa_decrypt_v2;
architecture Behavioral of tb_mceliece_qd_goppa_decrypt_v2 is
component ram
Generic (
ram_address_size : integer;
ram_word_size : integer;
file_ram_word_size : integer;
load_file_name : string := "ram.dat";
dump_file_name : string := "ram.dat"
);
Port (
data_in : in STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
rw : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
dump : in STD_LOGIC;
address : in STD_LOGIC_VECTOR ((ram_address_size - 1) downto 0);
rst_value : in STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
data_out : out STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0)
);
end component;
component ram_double
Generic (
ram_address_size : integer;
ram_word_size : integer;
file_ram_word_size : integer;
load_file_name : string := "ram.dat";
dump_file_name : string := "ram.dat"
);
Port (
data_in_a : in STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
data_in_b : in STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
rw_a : in STD_LOGIC;
rw_b : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
dump : in STD_LOGIC;
address_a : in STD_LOGIC_VECTOR ((ram_address_size - 1) downto 0);
address_b : in STD_LOGIC_VECTOR ((ram_address_size - 1) downto 0);
rst_value : in STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
data_out_a : out STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
data_out_b : out STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0)
);
end component;
component ram_bank
Generic (
number_of_memories : integer;
ram_address_size : integer;
ram_word_size : integer;
file_ram_word_size : integer;
load_file_name : string := "ram.dat";
dump_file_name : string := "ram.dat"
);
Port (
data_in : in STD_LOGIC_VECTOR (((ram_word_size)*(number_of_memories) - 1) downto 0);
rw : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
dump : in STD_LOGIC;
address : in STD_LOGIC_VECTOR ((ram_address_size - 1) downto 0);
rst_value : in STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
data_out : out STD_LOGIC_VECTOR (((ram_word_size)*(number_of_memories) - 1) downto 0)
);
end component;
component ram_double_bank
Generic (
number_of_memories : integer;
ram_address_size : integer;
ram_word_size : integer;
file_ram_word_size : integer;
load_file_name : string := "ram.dat";
dump_file_name : string := "ram.dat"
);
Port (
data_in_a : in STD_LOGIC_VECTOR (((ram_word_size)*(number_of_memories) - 1) downto 0);
data_in_b : in STD_LOGIC_VECTOR (((ram_word_size)*(number_of_memories) - 1) downto 0);
rw_a : in STD_LOGIC;
rw_b : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
dump : in STD_LOGIC;
address_a : in STD_LOGIC_VECTOR ((ram_address_size - 1) downto 0);
address_b : in STD_LOGIC_VECTOR ((ram_address_size - 1) downto 0);
rst_value : in STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
data_out_a : out STD_LOGIC_VECTOR (((ram_word_size)*(number_of_memories) - 1) downto 0);
data_out_b : out STD_LOGIC_VECTOR (((ram_word_size)*(number_of_memories) - 1) downto 0)
);
end component;
component mceliece_qd_goppa_decrypt_v2
Generic(
number_of_polynomial_evaluator_syndrome_pipelines : integer;
polynomial_evaluator_syndrome_pipeline_size : integer;
polynomial_evaluator_syndrome_size_pipeline_size : integer;
gf_2_m : integer range 1 to 20;
length_codeword : integer;
size_codeword : integer;
number_of_errors : integer;
size_number_of_errors : integer
);
Port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
value_h : in STD_LOGIC_VECTOR(((number_of_polynomial_evaluator_syndrome_pipelines)*(gf_2_m) - 1) downto 0);
value_L : in STD_LOGIC_VECTOR(((number_of_polynomial_evaluator_syndrome_pipelines)*(gf_2_m) - 1) downto 0);
value_syndrome : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_codeword : in STD_LOGIC_VECTOR((number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
value_G : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_B : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_sigma : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_sigma_evaluated : in STD_LOGIC_VECTOR(((number_of_polynomial_evaluator_syndrome_pipelines)*(gf_2_m) - 1) downto 0);
syndrome_generation_finalized : out STD_LOGIC;
key_equation_finalized : out STD_LOGIC;
decryption_finalized : out STD_LOGIC;
address_value_h : out STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0);
address_value_L : out STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0);
address_value_syndrome : out STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
address_value_codeword : out STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0);
address_value_G : out STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
address_value_B : out STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
address_value_sigma : out STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
address_value_sigma_evaluated : out STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0);
new_value_syndrome : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_G : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_B : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_sigma : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_message : out STD_LOGIC_VECTOR((number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
new_value_error : out STD_LOGIC_VECTOR((number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
new_value_sigma_evaluated : out STD_LOGIC_VECTOR(((number_of_polynomial_evaluator_syndrome_pipelines)*(gf_2_m) - 1) downto 0);
write_enable_new_value_syndrome : out STD_LOGIC;
write_enable_new_value_G : out STD_LOGIC;
write_enable_new_value_B : out STD_LOGIC;
write_enable_new_value_sigma : out STD_LOGIC;
write_enable_new_value_message : out STD_LOGIC;
write_enable_new_value_error : out STD_LOGIC;
write_enable_new_value_sigma_evaluated : out STD_LOGIC;
address_new_value_syndrome : out STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
address_new_value_G : out STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
address_new_value_B : out STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
address_new_value_sigma : out STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
address_new_value_message : out STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0);
address_new_value_error : out STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0);
address_new_value_sigma_evaluated : out STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0)
);
end component;
signal clk : STD_LOGIC := '0';
signal rst : STD_LOGIC;
signal value_h : STD_LOGIC_VECTOR(((number_of_polynomial_evaluator_syndrome_pipelines)*(gf_2_m) - 1) downto 0);
signal value_L : STD_LOGIC_VECTOR(((number_of_polynomial_evaluator_syndrome_pipelines)*(gf_2_m) - 1) downto 0);
signal value_syndrome : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal value_codeword : STD_LOGIC_VECTOR(((number_of_polynomial_evaluator_syndrome_pipelines) - 1) downto 0);
signal value_G : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal value_B : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal value_sigma : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal value_sigma_evaluated : STD_LOGIC_VECTOR(((number_of_polynomial_evaluator_syndrome_pipelines)*(gf_2_m) - 1) downto 0);
signal syndrome_generation_finalized : STD_LOGIC;
signal key_equation_finalized : STD_LOGIC;
signal decryption_finalized : STD_LOGIC;
signal address_value_h : STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0);
signal address_value_L : STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0);
signal address_value_syndrome : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal address_value_codeword : STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0);
signal address_value_G : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal address_value_B : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal address_value_sigma : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal address_value_sigma_evaluated : STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0);
signal new_value_syndrome : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal new_value_G : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal new_value_B : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal new_value_sigma : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal new_value_message : STD_LOGIC_VECTOR(((number_of_polynomial_evaluator_syndrome_pipelines) - 1) downto 0);
signal new_value_error : STD_LOGIC_VECTOR(((number_of_polynomial_evaluator_syndrome_pipelines) - 1) downto 0);
signal new_value_sigma_evaluated : STD_LOGIC_VECTOR(((number_of_polynomial_evaluator_syndrome_pipelines)*(gf_2_m) - 1) downto 0);
signal write_enable_new_value_syndrome : STD_LOGIC;
signal write_enable_new_value_G : STD_LOGIC;
signal write_enable_new_value_B : STD_LOGIC;
signal write_enable_new_value_sigma : STD_LOGIC;
signal write_enable_new_value_message : STD_LOGIC;
signal write_enable_new_value_error : STD_LOGIC;
signal write_enable_new_value_sigma_evaluated : STD_LOGIC;
signal address_new_value_syndrome : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal address_new_value_G : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal address_new_value_B : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal address_new_value_sigma : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal address_new_value_message : STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0);
signal address_new_value_error : STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0);
signal address_new_value_sigma_evaluated : STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0);
signal true_address_new_value_message : STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0);
signal true_value_message : STD_LOGIC_VECTOR((number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
signal test_value_message : STD_LOGIC_VECTOR((number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
signal true_address_new_value_error : STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0);
signal true_value_error : STD_LOGIC_VECTOR((number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
signal test_value_error : STD_LOGIC_VECTOR((number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
signal error_value_message : STD_LOGIC;
signal error_value_error : STD_LOGIC;
signal test_bench_finish : STD_LOGIC := '0';
signal cycle_count : integer range 0 to 2000000000 := 0;
begin
test : mceliece_qd_goppa_decrypt_v2
Generic Map(
number_of_polynomial_evaluator_syndrome_pipelines => number_of_polynomial_evaluator_syndrome_pipelines,
polynomial_evaluator_syndrome_pipeline_size => polynomial_evaluator_syndrome_pipeline_size,
polynomial_evaluator_syndrome_size_pipeline_size => polynomial_evaluator_syndrome_size_pipeline_size,
gf_2_m => gf_2_m,
length_codeword => length_codeword,
size_codeword => size_codeword,
number_of_errors => number_of_errors,
size_number_of_errors => size_number_of_errors
)
Port Map(
clk => clk,
rst => rst,
value_h => value_h,
value_L => value_L,
value_syndrome => value_syndrome,
value_codeword => value_codeword,
value_G => value_G,
value_B => value_B,
value_sigma => value_sigma,
value_sigma_evaluated => value_sigma_evaluated,
syndrome_generation_finalized => syndrome_generation_finalized,
key_equation_finalized => key_equation_finalized,
decryption_finalized => decryption_finalized,
address_value_h => address_value_h,
address_value_L => address_value_L,
address_value_syndrome => address_value_syndrome,
address_value_codeword => address_value_codeword,
address_value_G => address_value_G,
address_value_B => address_value_B,
address_value_sigma => address_value_sigma,
address_value_sigma_evaluated => address_value_sigma_evaluated,
new_value_syndrome => new_value_syndrome,
new_value_G => new_value_G,
new_value_B => new_value_B,
new_value_sigma => new_value_sigma,
new_value_message => new_value_message,
new_value_error => new_value_error,
new_value_sigma_evaluated => new_value_sigma_evaluated,
write_enable_new_value_syndrome => write_enable_new_value_syndrome,
write_enable_new_value_G => write_enable_new_value_G,
write_enable_new_value_B => write_enable_new_value_B,
write_enable_new_value_sigma => write_enable_new_value_sigma,
write_enable_new_value_message => write_enable_new_value_message,
write_enable_new_value_error => write_enable_new_value_error,
write_enable_new_value_sigma_evaluated => write_enable_new_value_sigma_evaluated,
address_new_value_syndrome => address_new_value_syndrome,
address_new_value_G => address_new_value_G,
address_new_value_B => address_new_value_B,
address_new_value_sigma => address_new_value_sigma,
address_new_value_message => address_new_value_message,
address_new_value_error => address_new_value_error,
address_new_value_sigma_evaluated => address_new_value_sigma_evaluated
);
mem_L : entity work.ram_bank(file_load)
Generic Map(
number_of_memories => number_of_polynomial_evaluator_syndrome_pipelines,
ram_address_size => size_codeword,
ram_word_size => gf_2_m,
file_ram_word_size => gf_2_m,
load_file_name => file_memory_L,
dump_file_name => ""
)
Port Map(
data_in => (others => '0'),
rw => '0',
clk => clk,
rst => rst,
dump => '0',
address => address_value_L,
rst_value => (others => '0'),
data_out => value_L
);
mem_h : entity work.ram_bank(file_load)
Generic Map(
number_of_memories => number_of_polynomial_evaluator_syndrome_pipelines,
ram_address_size => size_codeword,
ram_word_size => gf_2_m,
file_ram_word_size => gf_2_m,
load_file_name => file_memory_h,
dump_file_name => ""
)
Port Map(
data_in => (others => '0'),
rw => '0',
clk => clk,
rst => rst,
dump => '0',
address => address_value_h,
rst_value => (others => '0'),
data_out => value_h
);
mem_codeword : entity work.ram_bank(file_load)
Generic Map(
number_of_memories => number_of_polynomial_evaluator_syndrome_pipelines,
ram_address_size => size_codeword,
ram_word_size => 1,
file_ram_word_size => 1,
load_file_name => file_memory_codeword,
dump_file_name => ""
)
Port Map(
data_in => (others => '0'),
rw => '0',
clk => clk,
rst => rst,
dump => '0',
address => address_value_codeword,
rst_value => (others => '0'),
data_out => value_codeword
);
mem_sigma_evaluated : entity work.ram_double_bank(simple)
Generic Map(
number_of_memories => number_of_polynomial_evaluator_syndrome_pipelines,
ram_address_size => size_codeword,
ram_word_size => gf_2_m,
file_ram_word_size => gf_2_m,
load_file_name => "",
dump_file_name => ""
)
Port Map(
data_in_a => (others => '0'),
data_in_b => new_value_sigma_evaluated,
rw_a => '0',
rw_b => write_enable_new_value_sigma_evaluated,
clk => clk,
rst => rst,
dump => '0',
address_a => address_value_sigma_evaluated,
address_b => address_new_value_sigma_evaluated,
rst_value => (others => '0'),
data_out_a => value_sigma_evaluated,
data_out_b => open
);
test_mem_message : entity work.ram_double_bank(simple)
Generic Map(
number_of_memories => number_of_polynomial_evaluator_syndrome_pipelines,
ram_address_size => size_codeword,
ram_word_size => 1,
file_ram_word_size => 1,
load_file_name => "",
dump_file_name => ""
)
Port Map(
data_in_a => new_value_message,
data_in_b => (others => '0'),
rw_a => write_enable_new_value_message,
rw_b => '0',
clk => clk,
rst => rst,
dump => '0',
address_a => address_new_value_message,
address_b => true_address_new_value_message,
rst_value => (others => '0'),
data_out_a => open,
data_out_b => test_value_message
);
test_mem_error : entity work.ram_double_bank(simple)
Generic Map(
number_of_memories => number_of_polynomial_evaluator_syndrome_pipelines,
ram_address_size => size_codeword,
ram_word_size => 1,
file_ram_word_size => 1,
load_file_name => "",
dump_file_name => ""
)
Port Map(
data_in_a => new_value_error,
data_in_b => (others => '0'),
rw_a => write_enable_new_value_error,
rw_b => '0',
clk => clk,
rst => rst,
dump => '0',
address_a => address_new_value_error,
address_b => true_address_new_value_error,
rst_value => (others => '0'),
data_out_a => open,
data_out_b => test_value_error
);
true_mem_message : entity work.ram_bank(file_load)
Generic Map(
number_of_memories => number_of_polynomial_evaluator_syndrome_pipelines,
ram_address_size => size_codeword,
ram_word_size => 1,
file_ram_word_size => 1,
load_file_name => file_memory_message,
dump_file_name => ""
)
Port Map(
data_in => (others => '0'),
rw => '0',
clk => clk,
rst => rst,
dump => '0',
address => true_address_new_value_message,
rst_value => (others => '0'),
data_out => true_value_message
);
true_mem_error : entity work.ram_bank(file_load)
Generic Map(
number_of_memories => number_of_polynomial_evaluator_syndrome_pipelines,
ram_address_size => size_codeword,
ram_word_size => 1,
file_ram_word_size => 1,
load_file_name => file_memory_error,
dump_file_name => ""
)
Port Map(
data_in => (others => '0'),
rw => '0',
clk => clk,
rst => rst,
dump => '0',
address => true_address_new_value_error,
rst_value => (others => '0'),
data_out => true_value_error
);
mem_syndrome : entity work.ram_double(simple)
Generic Map(
ram_address_size => size_number_of_errors + 2,
ram_word_size => gf_2_m,
file_ram_word_size => gf_2_m,
load_file_name => "",
dump_file_name => ""
)
Port Map(
data_in_a => (others => '0'),
data_in_b => new_value_syndrome,
rw_a => '0',
rw_b => write_enable_new_value_syndrome,
clk => clk,
rst => rst,
dump => '0',
address_a => address_value_syndrome,
address_b => address_new_value_syndrome,
rst_value => (others => '0'),
data_out_a => value_syndrome,
data_out_b => open
);
mem_G : entity work.ram_double(simple)
Generic Map(
ram_address_size => size_number_of_errors + 2,
ram_word_size => gf_2_m,
file_ram_word_size => gf_2_m,
load_file_name => "",
dump_file_name => ""
)
Port Map(
data_in_a => (others => '0'),
data_in_b => new_value_G,
rw_a => '0',
rw_b => write_enable_new_value_G,
clk => clk,
rst => rst,
dump => '0',
address_a => address_value_G,
address_b => address_new_value_G,
rst_value => (others => '0'),
data_out_a => value_G,
data_out_b => open
);
mem_B : entity work.ram_double(simple)
Generic Map(
ram_address_size => size_number_of_errors + 2,
ram_word_size => gf_2_m,
file_ram_word_size => gf_2_m,
load_file_name => "",
dump_file_name => ""
)
Port Map(
data_in_a => (others => '0'),
data_in_b => new_value_B,
rw_a => '0',
rw_b => write_enable_new_value_B,
clk => clk,
rst => rst,
dump => '0',
address_a => address_value_B,
address_b => address_new_value_B,
rst_value => (others => '0'),
data_out_a => value_B,
data_out_b => open
);
mem_sigma : entity work.ram_double(simple)
Generic Map(
ram_address_size => size_number_of_errors + 2,
ram_word_size => gf_2_m,
file_ram_word_size => gf_2_m,
load_file_name => "",
dump_file_name => ""
)
Port Map(
data_in_a => (others => '0'),
data_in_b => new_value_sigma,
rw_a => '0',
rw_b => write_enable_new_value_sigma,
clk => clk,
rst => rst,
dump => '0',
address_a => address_value_sigma,
address_b => address_new_value_sigma,
rst_value => (others => '0'),
data_out_a => value_sigma,
data_out_b => open
);
clock : process
begin
while ( test_bench_finish /= '1') loop
clk <= not clk;
wait for PERIOD/2;
cycle_count <= cycle_count+1;
end loop;
wait;
end process;
--clk <= not clk after PERIOD/2;
process
variable i : integer;
variable syndrome_cycle_count : integer range 0 to 2000000000 := 0;
variable key_equation_cycle_count : integer range 0 to 2000000000 := 0;
variable correct_errors_cycle_count : integer range 0 to 2000000000 := 0;
begin
true_address_new_value_message <= (others => '0');
true_address_new_value_error <= (others => '0');
rst <= '1';
error_value_message <= '0';
error_value_error <= '0';
wait for PERIOD*2;
rst <= '0';
wait until syndrome_generation_finalized = '1';
syndrome_cycle_count := cycle_count - 2;
report "Circuit finish Syndrome = " & integer'image(syndrome_cycle_count/2) & " cycles";
wait until key_equation_finalized = '1';
key_equation_cycle_count := cycle_count - syndrome_cycle_count;
report "Circuit finish Key Equation = " & integer'image(key_equation_cycle_count/2) & " cycles";
wait until decryption_finalized = '1';
correct_errors_cycle_count := cycle_count - key_equation_cycle_count - syndrome_cycle_count;
report "Circuit finish Correct Errors = " & integer'image(correct_errors_cycle_count/2) & " cycles";
report "Circuit finish = " & integer'image(cycle_count/2) & " cycles";
wait for PERIOD;
i := 0;
while (i < (length_codeword)) loop
true_address_new_value_message(size_codeword - 1 downto 0) <= std_logic_vector(to_unsigned(i, size_codeword));
true_address_new_value_error(size_codeword - 1 downto 0) <= std_logic_vector(to_unsigned(i, size_codeword));
wait for PERIOD*2;
if (true_value_message(0) = test_value_message(0)) then
error_value_message <= '0';
else
error_value_message <= '1';
report "Computed values do not match expected ones";
end if;
if (true_value_error(0) = test_value_error(0)) then
error_value_error <= '0';
else
error_value_error <= '1';
report "Computed values do not match expected ones";
end if;
wait for PERIOD;
error_value_message <= '0';
error_value_error <= '0';
wait for PERIOD;
i := i + number_of_polynomial_evaluator_syndrome_pipelines;
end loop;
wait for PERIOD;
test_bench_finish <= '1';
wait;
end process;
end Behavioral;
|
bsd-2-clause
|
pmassolino/hw-goppa-mceliece
|
mceliece/finite_field/tb_inv_gf_2_m.vhd
|
1
|
8013
|
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Tb_Inv_GF_2_M
-- Module Name: Tb_Inv_GF_2_M
-- Project Name: GF_2_M Arithmetic
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- This test bench tests inversion circuit implementation for a field GF(2^m).
--
-- The circuits parameters
--
-- PERIOD :
--
-- Input clock period to be applied on the test.
--
-- gf_2_m :
--
-- The size of the field used in this circuit.
--
-- Dependencies:
-- VHDL-93
-- IEEE.NUMERIC_STD.ALL;
-- IEEE.STD_LOGIC_TEXTIO.ALL;
-- STD.TEXTIO.ALL;
--
-- pow2_gf_2_m Rev 1.0
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_TEXTIO.ALL;
library STD;
use STD.TEXTIO.ALL;
entity tb_inv_gf_2_m is
Generic(
PERIOD : time := 10 ns;
gf_2_m : integer range 2 to 20 := 12;
-- Software --
test_memory_file_gf_2_2 : string := "mceliece/finite_field_tests/inv_gf_2_2_x2_x1_1.dat";
test_memory_file_gf_2_3 : string := "mceliece/finite_field_tests/inv_gf_2_3_x3_x1_1.dat";
test_memory_file_gf_2_4 : string := "mceliece/finite_field_tests/inv_gf_2_4_x4_x1_1.dat";
test_memory_file_gf_2_5 : string := "mceliece/finite_field_tests/inv_gf_2_5_x5_x2_1.dat";
test_memory_file_gf_2_6 : string := "mceliece/finite_field_tests/inv_gf_2_6_x6_x1_1.dat";
test_memory_file_gf_2_7 : string := "mceliece/finite_field_tests/inv_gf_2_7_x7_x1_1.dat";
test_memory_file_gf_2_8 : string := "mceliece/finite_field_tests/inv_gf_2_8_x8_x4_x3_x2_1.dat";
test_memory_file_gf_2_9 : string := "mceliece/finite_field_tests/inv_gf_2_9_x9_x4_1.dat";
test_memory_file_gf_2_10 : string := "mceliece/finite_field_tests/inv_gf_2_10_x10_x3_1.dat";
test_memory_file_gf_2_11 : string := "mceliece/finite_field_tests/inv_gf_2_11_x11_x2_1.dat";
test_memory_file_gf_2_12 : string := "mceliece/finite_field_tests/inv_gf_2_12_x12_x6_x4_x1_1.dat";
test_memory_file_gf_2_13 : string := "mceliece/finite_field_tests/inv_gf_2_13_x13_x4_x3_x1_1.dat";
test_memory_file_gf_2_14 : string := "mceliece/finite_field_tests/inv_gf_2_14_x14_x5_x3_x1_1.dat";
test_memory_file_gf_2_15 : string := "mceliece/finite_field_tests/inv_gf_2_15_x15_x1_1.dat";
test_memory_file_gf_2_16 : string := "mceliece/finite_field_tests/inv_gf_2_16_x16_x5_x3_x2_1.dat";
test_memory_file_gf_2_17 : string := "mceliece/finite_field_tests/inv_gf_2_17_x17_x3_1.dat";
test_memory_file_gf_2_18 : string := "mceliece/finite_field_tests/inv_gf_2_18_x18_x7_1.dat";
test_memory_file_gf_2_19 : string := "mceliece/finite_field_tests/inv_gf_2_19_x19_x5_x2_x1_1.dat";
test_memory_file_gf_2_20 : string := "mceliece/finite_field_tests/inv_gf_2_20_x20_x3_1.dat"
-- IEEE --
-- test_memory_file_gf_2_2 : string := "mceliece/finite_field_tests/inv_gf_2_2_x2_x1_1.dat";
-- test_memory_file_gf_2_3 : string := "mceliece/finite_field_tests/inv_gf_2_3_x3_x1_1.dat";
-- test_memory_file_gf_2_4 : string := "mceliece/finite_field_tests/inv_gf_2_4_x4_x1_1.dat";
-- test_memory_file_gf_2_5 : string := "mceliece/finite_field_tests/inv_gf_2_5_x5_x2_1.dat";
-- test_memory_file_gf_2_6 : string := "mceliece/finite_field_tests/inv_gf_2_6_x6_x1_1.dat";
-- test_memory_file_gf_2_7 : string := "mceliece/finite_field_tests/inv_gf_2_7_x7_x1_1.dat";
-- test_memory_file_gf_2_8 : string := "mceliece/finite_field_tests/inv_gf_2_8_x8_x4_x3_x1_1.dat";
-- test_memory_file_gf_2_9 : string := "mceliece/finite_field_tests/inv_gf_2_9_x9_x1_1.dat";
-- test_memory_file_gf_2_10 : string := "mceliece/finite_field_tests/inv_gf_2_10_x10_x3_1.dat";
-- test_memory_file_gf_2_11 : string := "mceliece/finite_field_tests/inv_gf_2_11_x11_x2_1.dat";
-- test_memory_file_gf_2_12 : string := "mceliece/finite_field_tests/inv_gf_2_12_x12_x3_1.dat";
-- test_memory_file_gf_2_13 : string := "mceliece/finite_field_tests/inv_gf_2_13_x13_x4_x3_x1_1.dat";
-- test_memory_file_gf_2_14 : string := "mceliece/finite_field_tests/inv_gf_2_14_x14_x5_1.dat";
-- test_memory_file_gf_2_15 : string := "mceliece/finite_field_tests/inv_gf_2_15_x15_x1_1.dat";
-- test_memory_file_gf_2_16 : string := "mceliece/finite_field_tests/inv_gf_2_16_x16_x5_x3_x1_1.dat";
-- test_memory_file_gf_2_17 : string := "mceliece/finite_field_tests/inv_gf_2_17_x17_x3_1.dat";
-- test_memory_file_gf_2_18 : string := "mceliece/finite_field_tests/inv_gf_2_18_x18_x3_1.dat";
-- test_memory_file_gf_2_19 : string := "mceliece/finite_field_tests/inv_gf_2_19_x19_x5_x2_x1_1.dat";
-- test_memory_file_gf_2_20 : string := "mceliece/finite_field_tests/inv_gf_2_20_x20_x3_1.dat"
);
end tb_inv_gf_2_m;
architecture Behavioral of tb_inv_gf_2_m is
component inv_gf_2_m is
Generic(gf_2_m : integer range 1 to 20);
Port(
a : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
o : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0)
);
end component;
signal test_a : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal test_o : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal true_o : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal error : STD_LOGIC := '0';
signal clk : STD_LOGIC := '1';
signal test_bench_finish : STD_LOGIC := '0';
begin
test : inv_gf_2_m
Generic Map(gf_2_m => gf_2_m)
Port Map(
a => test_a,
o => test_o
);
clock : process
begin
while ( test_bench_finish /= '1') loop
clk <= not clk;
wait for PERIOD/2;
end loop;
wait;
end process;
--clk <= not clk after PERIOD/2;
process
FILE ram_file : text;
variable line_n : line;
variable number_of_tests : integer;
variable read_a : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
variable read_o : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
begin
case gf_2_m is
when 2 => file_open(ram_file, test_memory_file_gf_2_2, READ_MODE);
when 3 => file_open(ram_file, test_memory_file_gf_2_3, READ_MODE);
when 4 => file_open(ram_file, test_memory_file_gf_2_4, READ_MODE);
when 5 => file_open(ram_file, test_memory_file_gf_2_5, READ_MODE);
when 6 => file_open(ram_file, test_memory_file_gf_2_6, READ_MODE);
when 7 => file_open(ram_file, test_memory_file_gf_2_7, READ_MODE);
when 8 => file_open(ram_file, test_memory_file_gf_2_8, READ_MODE);
when 9 => file_open(ram_file, test_memory_file_gf_2_9, READ_MODE);
when 10 => file_open(ram_file, test_memory_file_gf_2_10, READ_MODE);
when 11 => file_open(ram_file, test_memory_file_gf_2_11, READ_MODE);
when 12 => file_open(ram_file, test_memory_file_gf_2_12, READ_MODE);
when 13 => file_open(ram_file, test_memory_file_gf_2_13, READ_MODE);
when 14 => file_open(ram_file, test_memory_file_gf_2_14, READ_MODE);
when 15 => file_open(ram_file, test_memory_file_gf_2_15, READ_MODE);
when 16 => file_open(ram_file, test_memory_file_gf_2_16, READ_MODE);
when 17 => file_open(ram_file, test_memory_file_gf_2_17, READ_MODE);
when 18 => file_open(ram_file, test_memory_file_gf_2_18, READ_MODE);
when 19 => file_open(ram_file, test_memory_file_gf_2_19, READ_MODE);
when 20 => file_open(ram_file, test_memory_file_gf_2_20, READ_MODE);
end case;
readline (ram_file, line_n);
read (line_n, number_of_tests);
wait for PERIOD;
for I in 1 to number_of_tests loop
error <= '0';
readline (ram_file, line_n);
read (line_n, read_a);
readline (ram_file, line_n);
read (line_n, read_o);
test_a <= read_a;
true_o <= read_o;
wait for PERIOD;
if (true_o = test_o) then
error <= '0';
else
error <= '1';
report "Computed values do not match expected ones";
end if;
wait for PERIOD;
error <= '0';
wait for PERIOD;
end loop;
test_bench_finish <= '1';
wait;
end process;
end Behavioral;
|
bsd-2-clause
|
pmassolino/hw-goppa-mceliece
|
mceliece/backup/tb_codeword_generator_1.vhd
|
1
|
11723
|
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Tb_Codeword Generator 1
-- Module Name: Tb_Codeword_Generator_1
-- Project Name: McEliece QD-Goppa Encoder
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- Test bench for codeword_generator_1 circuit.
--
-- The circuits parameters
--
-- PERIOD :
--
-- Input clock period to be applied on the test.
--
-- length_message :
--
-- Length in bits of message size and also part of matrix size.
--
-- size_message :
--
-- The number of bits necessary to store the message. The ceil(log2(lenght_message))
--
-- length_codeword :
--
-- Length in bits of codeword size and also part of matrix size.
--
-- size_codeword :
--
-- The number of bits necessary to store the codeword. The ceil(log2(length_codeword))
--
-- size_dyadic_matrix :
--
-- The number of bits necessary to store one row of the dyadic matrix.
-- It is also the ceil(log2(number of errors in the code))
--
-- number_dyadic_matrices :
--
-- The number of dyadic matrices present in matrix A.
--
-- size_number_dyadic_matrices :
--
-- The number of bits necessary to store the number of dyadic matrices.
-- The ceil(log2(number_dyadic_matrices))
--
-- message_memory_file :
--
-- File that holds the message to be encoded.
--
-- codeword_memory_file :
--
-- File that holds the encoded message.
-- This will be used to verify if the circuit worked correctly.
--
-- generator_matrix_memory_file :
--
-- File that holds the public key, matrix A, in a reduced form.
--
-- dump_test_codeword_file :
--
-- File that will hold the encoded message computed by the circuit.
--
--
-- Dependencies:
--
-- VHDL-93
-- IEEE.NUMERIC_STD_ALL;
--
-- codeword_generator_1 Rev 1.0
-- ram Rev 1.0
--
-- Revision:
-- Revision 1.00 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity tb_codeword_generator_1 is
Generic (
PERIOD : time := 10 ns;
-- QD-GOPPA [52, 28, 4, 6] --
-- length_message : integer := 28;
-- size_message : integer := 5;
-- length_codeword : integer := 52;
-- size_codeword : integer := 6;
-- size_dyadic_matrix : integer := 2;
-- number_dyadic_matrices : integer := 42;
-- size_number_dyadic_matrices : integer := 6;
-- message_memory_file : string := "mceliece/data_tests/message_qdgoppa_52_28_4_6.dat";
-- codeword_memory_file : string := "mceliece/data_tests/plaintext_qdgoppa_52_28_4_6.dat";
-- generator_matrix_memory_file : string := "mceliece/data_tests/generator_matrix_qdgoppa_52_28_4_6.dat";
-- dump_test_codeword_file : string := "mceliece/data_tests/dump_plaintext_qdgoppa_52_28_4_6.dat"
-- QD-GOPPA [2528, 2144, 32, 12] --
length_message : integer := 2144;
size_message : integer := 12;
length_codeword : integer := 2528;
size_codeword : integer := 12;
size_dyadic_matrix : integer := 5;
number_dyadic_matrices : integer := 804;
size_number_dyadic_matrices : integer := 10;
message_memory_file : string := "mceliece/data_tests/message_qdgoppa_2528_2144_32_12.dat";
codeword_memory_file : string := "mceliece/data_tests/plaintext_qdgoppa_2528_2144_32_12.dat";
generator_matrix_memory_file : string := "mceliece/data_tests/generator_matrix_qdgoppa_2528_2144_32_12.dat";
dump_test_codeword_file : string := "mceliece/data_tests/dump_plaintext_qdgoppa_2528_2144_32_12.dat"
-- QD-GOPPA [2816, 2048, 64, 12] --
-- length_message : integer := 2048;
-- size_message : integer := 12;
-- length_codeword : integer := 2816;
-- size_codeword : integer := 12;
-- size_dyadic_matrix : integer := 6;
-- number_dyadic_matrices : integer := 384;
-- size_number_dyadic_matrices : integer := 9;
-- message_memory_file : string := "mceliece/data_tests/message_qdgoppa_2816_2048_64_12.dat";
-- codeword_memory_file : string := "mceliece/data_tests/plaintext_qdgoppa_2816_2048_64_12.dat";
-- generator_matrix_memory_file : string := "mceliece/data_tests/generator_matrix_qdgoppa_2816_2048_64_12.dat";
-- dump_test_codeword_file : string := "mceliece/data_tests/dump_plaintext_qdgoppa_2816_2048_64_12.dat"
-- QD-GOPPA [3328, 2560, 64, 12] --
-- length_message : integer := 2560;
-- size_message : integer := 12;
-- length_codeword : integer := 3328;
-- size_codeword : integer := 12;
-- size_dyadic_matrix : integer := 6;
-- number_dyadic_matrices : integer := 480;
-- size_number_dyadic_matrices : integer := 9;
-- message_memory_file : string := "mceliece/data_tests/message_qdgoppa_3328_2560_64_12.dat";
-- codeword_memory_file : string := "mceliece/data_tests/plaintext_qdgoppa_3328_2560_64_12.dat";
-- generator_matrix_memory_file : string := "mceliece/data_tests/generator_matrix_qdgoppa_3328_2560_64_12.dat";
-- dump_test_codeword_file : string := "mceliece/data_tests/dump_plaintext_qdgoppa_3328_2560_64_12.dat"
-- QD-GOPPA [7296, 5632, 128, 13] --
-- length_message : integer := 5632;
-- size_message : integer := 13;
-- length_codeword : integer := 7296;
-- size_codeword : integer := 13;
-- size_dyadic_matrix : integer := 7;
-- number_dyadic_matrices : integer := 572;
-- size_number_dyadic_matrices : integer := 10;
-- message_memory_file : string := "mceliece/data_tests/message_qdgoppa_7296_5632_128_13.dat";
-- codeword_memory_file : string := "mceliece/data_tests/plaintext_qdgoppa_7296_5632_128_13.dat";
-- generator_matrix_memory_file : string := "mceliece/data_tests/generator_matrix_qdgoppa_7296_5632_128_13.dat";
-- dump_test_codeword_file : string := "mceliece/data_tests/dump_plaintext_qdgoppa_7296_5632_128_13.dat"
);
end tb_codeword_generator_1;
architecture Behavioral of tb_codeword_generator_1 is
component codeword_generator_1
Generic(
length_message : integer;
size_message : integer;
length_codeword : integer;
size_codeword : integer;
size_dyadic_matrix : integer;
number_dyadic_matrices : integer;
size_number_dyadic_matrices : integer
);
Port(
codeword : in STD_LOGIC;
matrix : in STD_LOGIC;
message : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
new_codeword : out STD_LOGIC;
write_enable_new_codeword : out STD_LOGIC;
codeword_finalized : out STD_LOGIC;
address_codeword : out STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
address_message : out STD_LOGIC_VECTOR((size_message - 1) downto 0);
address_matrix : out STD_LOGIC_VECTOR((size_dyadic_matrix + size_number_dyadic_matrices - 1) downto 0)
);
end component;
component ram
Generic (
ram_address_size : integer;
ram_word_size : integer;
file_ram_word_size : integer;
load_file_name : string := "ram.dat";
dump_file_name : string := "ram.dat"
);
Port (
data_in : in STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
rw : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
dump : in STD_LOGIC;
address : in STD_LOGIC_VECTOR ((ram_address_size - 1) downto 0);
rst_value : in STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
data_out : out STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0)
);
end component;
signal clk : STD_LOGIC := '0';
signal rst : STD_LOGIC;
signal codeword : STD_LOGIC;
signal matrix : STD_LOGIC;
signal message : STD_LOGIC;
signal new_codeword : STD_LOGIC;
signal write_enable_new_codeword : STD_LOGIC;
signal codeword_finalized : STD_LOGIC;
signal address_codeword : STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
signal address_message : STD_LOGIC_VECTOR((size_message - 1) downto 0);
signal address_matrix : STD_LOGIC_VECTOR((size_dyadic_matrix + size_number_dyadic_matrices - 1) downto 0);
signal test_address_acc : STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
signal final_address_acc : STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
signal true_acc : STD_LOGIC;
signal error : STD_LOGIC;
signal dump_test_codeword : STD_LOGIC;
signal test_bench_finish : STD_LOGIC := '0';
signal cycle_count : integer range 0 to 2000000000 := 0;
for message_memory : ram use entity work.ram(file_load);
for generator_matrix_memory : ram use entity work.ram(file_load);
for test_codeword_memory : ram use entity work.ram(simple);
for true_codeword_memory : ram use entity work.ram(file_load);
begin
test : codeword_generator_1
Generic Map(
length_message => length_message,
size_message => size_message,
length_codeword => length_codeword,
size_codeword => size_codeword,
size_dyadic_matrix => size_dyadic_matrix,
number_dyadic_matrices => number_dyadic_matrices,
size_number_dyadic_matrices => size_number_dyadic_matrices
)
Port Map(
codeword => codeword,
matrix => matrix,
message => message,
clk => clk,
rst => rst,
new_codeword => new_codeword,
write_enable_new_codeword => write_enable_new_codeword,
codeword_finalized => codeword_finalized,
address_codeword => address_codeword,
address_message => address_message,
address_matrix => address_matrix
);
message_memory : ram
Generic Map(
ram_address_size => size_message,
ram_word_size => 1,
file_ram_word_size => 1,
load_file_name => message_memory_file,
dump_file_name => ""
)
Port Map(
data_in => "0",
rw => '0',
clk => clk,
rst => rst,
dump => '0',
address => address_message,
rst_value => "0",
data_out(0) => message
);
generator_matrix_memory : ram
Generic Map(
ram_address_size => size_dyadic_matrix + size_number_dyadic_matrices,
ram_word_size => 1,
file_ram_word_size => 1,
load_file_name => generator_matrix_memory_file,
dump_file_name => ""
)
Port Map(
data_in => "0",
rw => '0',
clk => clk,
rst => rst,
dump => '0',
address => address_matrix,
rst_value => "0",
data_out(0) => matrix
);
test_codeword_memory : ram
Generic Map(
ram_address_size => size_codeword,
ram_word_size => 1,
file_ram_word_size => 1,
load_file_name => "",
dump_file_name => dump_test_codeword_file
)
Port Map(
data_in(0) => new_codeword,
rw => write_enable_new_codeword,
clk => clk,
rst => rst,
dump => dump_test_codeword,
address => final_address_acc,
rst_value => "0",
data_out(0) => codeword
);
true_codeword_memory : ram
Generic Map(
ram_address_size => size_codeword,
ram_word_size => 1,
file_ram_word_size => 1,
load_file_name => codeword_memory_file,
dump_file_name => ""
)
Port Map(
data_in => "0",
rw => '0',
clk => clk,
rst => rst,
dump => '0',
address => final_address_acc,
rst_value => "0",
data_out(0) => true_acc
);
clock : process
begin
while ( test_bench_finish /= '1') loop
clk <= not clk;
wait for PERIOD/2;
cycle_count <= cycle_count+1;
end loop;
wait;
end process;
final_address_acc <= address_codeword when codeword_finalized = '0' else test_address_acc;
process
variable i : integer;
begin
test_address_acc <= (others => '0');
rst <= '1';
error <= '0';
dump_test_codeword <= '0';
wait for PERIOD*2;
rst <= '0';
wait until codeword_finalized = '1';
report "Circuit finish = " & integer'image((cycle_count - 2)/2) & " cycles";
wait for PERIOD;
i := 0;
while (i < (length_codeword)) loop
test_address_acc <= std_logic_vector(to_unsigned(i, test_address_acc'Length));
wait for PERIOD*2;
if (true_acc = codeword) then
error <= '0';
else
error <= '1';
report "Computed values do not match expected ones";
end if;
wait for PERIOD;
error <= '0';
wait for PERIOD;
i := i + 1;
end loop;
dump_test_codeword <= '1';
wait for PERIOD;
dump_test_codeword <= '0';
test_bench_finish <= '1';
wait;
end process;
end Behavioral;
|
bsd-2-clause
|
pmassolino/hw-goppa-mceliece
|
mceliece/backup/tb_syndrome_calculator_n_pipe_v3.vhd
|
1
|
22353
|
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Tb_Syndrome_Calculator_n_pipe_v3
-- Module Name: Tb_Syndrome_Calculator_n_pipe_v3
-- Project Name: McEliece Goppa Decoder
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- Test bench for syndrome_calculator_n_pipe_v3 circuit.
--
-- The circuits parameters
--
-- PERIOD :
--
-- Input clock period to be applied on the test.
--
-- number_of_syndrome_calculators :
--
-- The number of pipelines that compute parts of syndrome from
-- different parts of the ciphertext. This number must be 1 or greater.
--
-- syndrome_calculator_size :
--
-- The number of units that compute each syndrome at the same time
-- from the same ciphertext. This number must be 1 or greater.
--
-- gf_2_m :
--
-- The size of the field used in this circuit. This parameter depends of the
-- Goppa code used.
--
-- length_codeword :
--
-- The length of the codeword or in this case the ciphertext. Both the codeword
-- and ciphertext has the same size.
--
-- size_codeword :
--
-- The number of bits necessary to hold the ciphertext/codeword.
-- This is ceil(log2(length_codeword)).
--
-- length_syndrome :
--
-- The size of the syndrome array. This parameter depends of the
-- Goppa code used.
--
-- size_syndrome :
--
-- The number of bits necessary to hold the array syndrome.
-- This is ceil(log2(length_syndrome)).
--
-- file_memory_L :
--
-- The file that holds all support elements L.
-- This is part of the private key of the cryptosystem.
--
-- file_memory_h :
--
-- The file that holds all inverted evaluations of support elements L in polynomial g.
-- Therefore, g(L)^-1.
-- This is part of the private key of the cryptosystem.
--
-- file_memory_codeword :
--
-- The file that holds the received ciphertext necessary for computing the syndrome.
--
-- file_memory_syndrome :
--
-- The file that holds the syndrome previously computed.
-- This is necessary to be compared with circuit computed syndrome to verify if it worked.
--
-- dump_file_memory_syndrome :
--
-- The file that will hold the computed syndrome by the circuit.
--
-- Dependencies:
-- VHDL-93
-- IEEE.NUMERIC_STD_ALL;
--
-- syndrome_calculator_n_pipe_v3 Rev 1.0
-- ram Rev 1.0
-- ram_double Rev 1.0
-- ram_bank Rev 1.0
-- ram_double_bank Rev 1.0
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity tb_syndrome_calculator_n_pipe_v3 is
Generic(
PERIOD : time := 10 ns;
-- QD-GOPPA [52, 28, 4, 6] --
-- number_of_syndrome_calculators : integer := 4;
-- syndrome_calculator_size : integer := 16;
-- gf_2_m : integer range 1 to 20 := 6;
-- length_codeword : integer := 52;
-- size_codeword : integer := 6;
-- length_syndrome : integer := 8;
-- size_syndrome : integer := 3;
-- g_polynomial_degree : integer := 4;
-- size_g_polynomial_degree : integer := 3;
-- polynomial_evaluator_pipeline_size : integer := 5;
-- size_polynomial_evaluator_pipeline_size : integer := 3;
-- file_memory_L : string := "mceliece/data_tests/L_qdgoppa_52_28_4_6.dat";
-- file_memory_h : string := "mceliece/data_tests/h_qdgoppa_52_28_4_6.dat";
-- file_memory_codeword : string := "mceliece/data_tests/ciphertext_qdgoppa_52_28_4_6.dat";
-- file_memory_syndrome : string := "mceliece/data_tests/syndrome_qdgoppa_52_28_4_6.dat";
-- file_memory_g_polynomial : string := "mceliece/data_tests/g_polynomial_qdgoppa_52_28_4_6.dat";
-- dump_file_memory_syndrome : string := "mceliece/data_tests/dump_syndrome_qdgoppa_52_28_4_6.dat"
-- GOPPA [2048, 1751, 27, 11] --
-- number_of_syndrome_calculators : integer := 2;
-- syndrome_calculator_size : integer := 2;
-- gf_2_m : integer range 1 to 20 := 11;
-- length_codeword : integer := 2048;
-- size_codeword : integer := 11;
-- length_syndrome : integer := 54;
-- size_syndrome : integer := 6;
-- g_polynomial_degree : integer := 27;
-- size_g_polynomial_degree : integer := 5;
-- polynomial_evaluator_pipeline_size : integer := 28;
-- size_polynomial_evaluator_pipeline_size : integer := 5;
-- file_memory_L : string := "mceliece/data_tests/L_goppa_2048_1751_27_11.dat";
-- file_memory_h : string := "mceliece/data_tests/h_goppa_2048_1751_27_11.dat";
-- file_memory_codeword : string := "mceliece/data_tests/ciphertext_goppa_2048_1751_27_11.dat";
-- file_memory_syndrome : string := "mceliece/data_tests/syndrome_goppa_2048_1751_27_11.dat";
-- file_memory_g_polynomial : string := "mceliece/data_tests/g_polynomial_goppa_2048_1751_27_11.dat";
-- dump_file_memory_syndrome : string := "mceliece/data_tests/dump_syndrome_goppa_2048_1751_27_11.dat"
-- GOPPA [2048, 1498, 50, 11] --
-- number_of_syndrome_calculators : integer := 1;
-- syndrome_calculator_size : integer := 2;
-- gf_2_m : integer range 1 to 20 := 11;
-- length_codeword : integer := 2048;
-- size_codeword : integer := 11;
-- length_syndrome : integer := 100;
-- size_syndrome : integer := 7;
-- g_polynomial_degree : integer := 50;
-- size_g_polynomial_degree : integer := 6;
-- polynomial_evaluator_pipeline_size : integer := 14;
-- size_polynomial_evaluator_pipeline_size : integer := 5;
-- file_memory_L : string := "mceliece/data_tests/L_goppa_2048_1498_50_11.dat";
-- file_memory_h : string := "mceliece/data_tests/h_goppa_2048_1498_50_11.dat";
-- file_memory_codeword : string := "mceliece/data_tests/ciphertext_goppa_2048_1498_50_11.dat";
-- file_memory_syndrome : string := "mceliece/data_tests/syndrome_goppa_2048_1498_50_11.dat";
-- file_memory_g_polynomial : string := "mceliece/data_tests/g_polynomial_goppa_2048_1498_50_11.dat";
-- dump_file_memory_syndrome : string := "mceliece/data_tests/dump_syndrome_goppa_2048_1498_50_11.dat"
-- GOPPA [3307, 2515, 66, 12] --
-- number_of_syndrome_calculators : integer := 1;
-- syndrome_calculator_size : integer := 2;
-- gf_2_m : integer range 1 to 20 := 12;
-- length_codeword : integer := 3307;
-- size_codeword : integer := 12;
-- length_syndrome : integer := 132;
-- size_syndrome : integer := 8;
-- g_polynomial_degree : integer := 66;
-- size_g_polynomial_degree : integer := 7;
-- polynomial_evaluator_pipeline_size : integer := 14;
-- size_polynomial_evaluator_pipeline_size : integer := 5;
-- file_memory_L : string := "mceliece/data_tests/L_goppa_3307_2515_66_12.dat";
-- file_memory_h : string := "mceliece/data_tests/h_goppa_3307_2515_66_12.dat";
-- file_memory_codeword : string := "mceliece/data_tests/ciphertext_goppa_3307_2515_66_12.dat";
-- file_memory_syndrome : string := "mceliece/data_tests/syndrome_goppa_3307_2515_66_12.dat";
-- file_memory_g_polynomial : string := "mceliece/data_tests/g_polynomial_goppa_3307_2515_66_12.dat";
-- dump_file_memory_syndrome : string := "mceliece/data_tests/dump_syndrome_goppa_3307_2515_66_12.dat"
-- QD-GOPPA [2528, 2144, 32, 12] --
number_of_syndrome_calculators : integer := 2;
syndrome_calculator_size : integer := 16;
gf_2_m : integer range 1 to 20 := 12;
length_codeword : integer := 2528;
size_codeword : integer := 12;
length_syndrome : integer := 64;
size_syndrome : integer := 7;
g_polynomial_degree : integer := 32;
size_g_polynomial_degree : integer := 6;
polynomial_evaluator_pipeline_size : integer := 33;
size_polynomial_evaluator_pipeline_size : integer := 6;
file_memory_L : string := "mceliece/data_tests/L_qdgoppa_2528_2144_32_12.dat";
file_memory_h : string := "mceliece/data_tests/h_qdgoppa_2528_2144_32_12.dat";
file_memory_codeword : string := "mceliece/data_tests/ciphertext_qdgoppa_2528_2144_32_12.dat";
file_memory_syndrome : string := "mceliece/data_tests/syndrome_qdgoppa_2528_2144_32_12.dat";
file_memory_g_polynomial : string := "mceliece/data_tests/g_polynomial_qdgoppa_2528_2144_32_12.dat";
dump_file_memory_syndrome : string := "mceliece/data_tests/dump_syndrome_qdgoppa_2528_2144_32_12.dat"
-- QD-GOPPA [2816, 2048, 64, 12] --
-- number_of_syndrome_calculators : integer := 1;
-- syndrome_calculator_size : integer := 2;
-- gf_2_m : integer range 1 to 20 := 12;
-- length_codeword : integer := 2816;
-- size_codeword : integer := 12;
-- length_syndrome : integer := 128;
-- size_syndrome : integer := 7;
-- g_polynomial_degree : integer := 64;
-- size_g_polynomial_degree : integer := 7;
-- polynomial_evaluator_pipeline_size : integer := 14;
-- size_polynomial_evaluator_pipeline_size : integer := 5;
-- file_memory_L : string := "mceliece/data_tests/L_qdgoppa_2816_2048_64_12.dat";
-- file_memory_h : string := "mceliece/data_tests/h_qdgoppa_2816_2048_64_12.dat";
-- file_memory_codeword : string := "mceliece/data_tests/ciphertext_qdgoppa_2816_2048_64_12.dat";
-- file_memory_syndrome : string := "mceliece/data_tests/syndrome_qdgoppa_2816_2048_64_12.dat";
-- file_memory_g_polynomial : string := "mceliece/data_tests/g_polynomial_qdgoppa_2816_2048_64_12.dat";
-- dump_file_memory_syndrome : string := "mceliece/data_tests/dump_syndrome_qdgoppa_2816_2048_64_12.dat"
-- QD-GOPPA [3328, 2560, 64, 12] --
-- number_of_syndrome_calculators : integer := 1;
-- syndrome_calculator_size : integer := 2;
-- gf_2_m : integer range 1 to 20 := 12;
-- length_codeword : integer := 3328;
-- size_codeword : integer := 12;
-- length_syndrome : integer := 128;
-- size_syndrome : integer := 7;
-- g_polynomial_degree : integer := 64;
-- size_g_polynomial_degree : integer := 7;
-- polynomial_evaluator_pipeline_size : integer := 14;
-- size_polynomial_evaluator_pipeline_size : integer := 5;
-- file_memory_L : string := "mceliece/data_tests/L_qdgoppa_3328_2560_64_12.dat";
-- file_memory_h : string := "mceliece/data_tests/h_qdgoppa_3328_2560_64_12.dat";
-- file_memory_codeword : string := "mceliece/data_tests/ciphertext_qdgoppa_3328_2560_64_12.dat";
-- file_memory_syndrome : string := "mceliece/data_tests/syndrome_qdgoppa_3328_2560_64_12.dat";
-- file_memory_g_polynomial : string := "mceliece/data_tests/g_polynomial_qdgoppa_3328_2560_64_12.dat";
-- dump_file_memory_syndrome : string := "mceliece/data_tests/dump_syndrome_qdgoppa_3328_2560_64_12.dat"
-- QD-GOPPA [7296, 5632, 128, 13] --
-- number_of_syndrome_calculators : integer := 1;
-- syndrome_calculator_size : integer := 2;
-- gf_2_m : integer range 1 to 20 := 13;
-- length_codeword : integer := 7296;
-- size_codeword : integer := 13;
-- length_syndrome : integer := 256;
-- size_syndrome : integer := 8;
-- g_polynomial_degree : integer := 128;
-- size_g_polynomial_degree : integer := 8;
-- polynomial_evaluator_pipeline_size : integer := 14;
-- size_polynomial_evaluator_pipeline_size : integer := 5;
-- file_memory_L : string := "mceliece/data_tests/L_qdgoppa_7296_5632_128_13.dat";
-- file_memory_h : string := "mceliece/data_tests/h_qdgoppa_7296_5632_128_13.dat";
-- file_memory_codeword : string := "mceliece/data_tests/ciphertext_qdgoppa_7296_5632_128_13.dat";
-- file_memory_syndrome : string := "mceliece/data_tests/syndrome_qdgoppa_7296_5632_128_13.dat";
-- file_memory_g_polynomial : string := "mceliece/data_tests/g_polynomial_qdgoppa_7296_5632_128_13.dat";
-- dump_file_memory_syndrome : string := "mceliece/data_tests/dump_syndrome_qdgoppa_7296_5632_128_13.dat"
);
end tb_syndrome_calculator_n_pipe_v3;
architecture Behavioral of tb_syndrome_calculator_n_pipe_v3 is
component syndrome_calculator_n_pipe_v3
Generic(
gf_2_m : integer range 1 to 20 := 11;
length_codeword : integer := 1792;
size_codeword : integer := 11;
length_syndrome : integer := 128;
size_syndrome : integer := 7;
number_of_syndrome_calculators : integer := 1;
syndrome_calculator_size : integer := 32
);
Port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
value_h : in STD_LOGIC_VECTOR(((number_of_syndrome_calculators)*(gf_2_m) - 1) downto 0);
value_L : in STD_LOGIC_VECTOR(((number_of_syndrome_calculators)*(gf_2_m) - 1) downto 0);
value_syndrome : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_codeword : in STD_LOGIC_VECTOR((number_of_syndrome_calculators - 1) downto 0);
syndrome_finalized : out STD_LOGIC;
write_enable_new_syndrome : out STD_LOGIC;
new_value_syndrome : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
address_h : out STD_LOGIC_VECTOR(((number_of_syndrome_calculators)*(size_codeword) - 1) downto 0);
address_L : out STD_LOGIC_VECTOR(((number_of_syndrome_calculators)*(size_codeword) - 1) downto 0);
address_codeword : out STD_LOGIC_VECTOR(((number_of_syndrome_calculators)*(size_codeword) - 1) downto 0);
address_syndrome : out STD_LOGIC_VECTOR((size_syndrome - 1) downto 0);
address_new_syndrome : out STD_LOGIC_VECTOR((size_syndrome - 1) downto 0)
);
end component;
component ram
Generic (
ram_address_size : integer;
ram_word_size : integer;
file_ram_word_size : integer;
load_file_name : string := "ram.dat";
dump_file_name : string := "ram.dat"
);
Port (
data_in : in STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
rw : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
dump : in STD_LOGIC;
address : in STD_LOGIC_VECTOR ((ram_address_size - 1) downto 0);
rst_value : in STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
data_out : out STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0)
);
end component;
component ram_double
Generic (
ram_address_size : integer;
ram_word_size : integer;
file_ram_word_size : integer;
load_file_name : string := "ram.dat";
dump_file_name : string := "ram.dat"
);
Port (
data_in_a : in STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
data_in_b : in STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
rw_a : in STD_LOGIC;
rw_b : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
dump : in STD_LOGIC;
address_a : in STD_LOGIC_VECTOR ((ram_address_size - 1) downto 0);
address_b : in STD_LOGIC_VECTOR ((ram_address_size - 1) downto 0);
rst_value : in STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
data_out_a : out STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
data_out_b : out STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0)
);
end component;
component ram_bank
Generic (
number_of_memories : integer;
ram_address_size : integer;
ram_word_size : integer;
file_ram_word_size : integer;
load_file_name : string := "ram.dat";
dump_file_name : string := "ram.dat"
);
Port (
data_in : in STD_LOGIC_VECTOR (((ram_word_size)*(number_of_memories) - 1) downto 0);
rw : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
dump : in STD_LOGIC;
address : in STD_LOGIC_VECTOR ((ram_address_size - 1) downto 0);
rst_value : in STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
data_out : out STD_LOGIC_VECTOR (((ram_word_size)*(number_of_memories) - 1) downto 0)
);
end component;
component ram_double_bank
Generic (
number_of_memories : integer;
ram_address_size : integer;
ram_word_size : integer;
file_ram_word_size : integer;
load_file_name : string := "ram.dat";
dump_file_name : string := "ram.dat"
);
Port (
data_in_a : in STD_LOGIC_VECTOR (((ram_word_size)*(number_of_memories) - 1) downto 0);
data_in_b : in STD_LOGIC_VECTOR (((ram_word_size)*(number_of_memories) - 1) downto 0);
rw_a : in STD_LOGIC;
rw_b : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
dump : in STD_LOGIC;
address_a : in STD_LOGIC_VECTOR ((ram_address_size - 1) downto 0);
address_b : in STD_LOGIC_VECTOR ((ram_address_size - 1) downto 0);
rst_value : in STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
data_out_a : out STD_LOGIC_VECTOR (((ram_word_size)*(number_of_memories) - 1) downto 0);
data_out_b : out STD_LOGIC_VECTOR (((ram_word_size)*(number_of_memories) - 1) downto 0)
);
end component;
signal clk : STD_LOGIC := '0';
signal rst : STD_LOGIC;
signal synd_rst : STD_LOGIC;
signal value_h : STD_LOGIC_VECTOR(((number_of_syndrome_calculators)*(gf_2_m) - 1) downto 0);
signal value_L : STD_LOGIC_VECTOR(((number_of_syndrome_calculators)*(gf_2_m) - 1) downto 0);
signal value_codeword : STD_LOGIC_VECTOR((number_of_syndrome_calculators - 1) downto 0);
signal syndrome_finalized : STD_LOGIC;
signal write_enable_new_syndrome : STD_LOGIC;
signal new_value_syndrome : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal address_h : STD_LOGIC_VECTOR(((number_of_syndrome_calculators)*(size_codeword) - 1) downto 0);
signal address_L : STD_LOGIC_VECTOR(((number_of_syndrome_calculators)*(size_codeword) - 1) downto 0);
signal address_codeword : STD_LOGIC_VECTOR(((number_of_syndrome_calculators)*(size_codeword) - 1) downto 0);
signal address_new_syndrome : STD_LOGIC_VECTOR((size_syndrome - 1) downto 0);
signal mem_L_address : STD_LOGIC_VECTOR(((number_of_syndrome_calculators)*(size_codeword) - 1) downto 0);
signal mem_h_address : STD_LOGIC_VECTOR(((number_of_syndrome_calculators)*(size_codeword) - 1) downto 0);
signal address_syndrome : STD_LOGIC_VECTOR((size_syndrome - 1) downto 0);
signal test_address_syndrome : STD_LOGIC_VECTOR((size_syndrome - 1) downto 0);
signal true_address_syndrome : STD_LOGIC_VECTOR((size_syndrome - 1) downto 0);
signal test_value_syndrome : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal true_value_syndrome : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal error_syndrome : STD_LOGIC;
signal test_syndrome_dump : STD_LOGIC;
signal test_bench_finish : STD_LOGIC := '0';
signal cycle_count : integer range 0 to 2000000000 := 0;
for test_syndrome : ram_double use entity work.ram_double(simple);
for true_syndrome : ram use entity work.ram(file_load);
begin
test : syndrome_calculator_n_pipe_v3
Generic Map(
gf_2_m => gf_2_m,
length_codeword => length_codeword,
size_codeword => size_codeword,
length_syndrome => length_syndrome,
size_syndrome => size_syndrome,
number_of_syndrome_calculators => number_of_syndrome_calculators,
syndrome_calculator_size => syndrome_calculator_size
)
Port Map(
clk => clk,
rst => synd_rst,
value_h => value_h,
value_L => value_L,
value_syndrome => test_value_syndrome,
value_codeword => value_codeword,
syndrome_finalized => syndrome_finalized,
write_enable_new_syndrome => write_enable_new_syndrome,
new_value_syndrome => new_value_syndrome,
address_h => address_h,
address_L => address_L,
address_codeword => address_codeword,
address_syndrome => test_address_syndrome,
address_new_syndrome => address_new_syndrome
);
memory_units : for I in 0 to (number_of_syndrome_calculators - 1) generate
mem_L : entity work.ram(file_load)
Generic Map(
ram_address_size => size_codeword,
ram_word_size => gf_2_m,
file_ram_word_size => gf_2_m,
load_file_name => file_memory_L,
dump_file_name => ""
)
Port Map(
data_in => (others => '0'),
rw => '0',
clk => clk,
rst => rst,
dump => '0',
address => mem_L_address(((I+1)*(size_codeword) - 1) downto (I)*(size_codeword)),
rst_value => (others => '0'),
data_out => value_L(((I+1)*(gf_2_m) - 1) downto (I)*(gf_2_m))
);
mem_h : entity work.ram(file_load)
Generic Map(
ram_address_size => size_codeword,
ram_word_size => gf_2_m,
file_ram_word_size => gf_2_m,
load_file_name => file_memory_h,
dump_file_name => ""
)
Port Map(
data_in => (others => '0'),
rw => '0',
clk => clk,
rst => rst,
dump => '0',
address => mem_h_address(((I+1)*(size_codeword) - 1) downto (I)*(size_codeword)),
rst_value => (others => '0'),
data_out => value_h(((I+1)*(gf_2_m) - 1) downto (I)*(gf_2_m))
);
mem_codeword : entity work.ram(file_load)
Generic Map(
ram_address_size => size_codeword,
ram_word_size => 1,
file_ram_word_size => 1,
load_file_name => file_memory_codeword,
dump_file_name => ""
)
Port Map(
data_in => (others => '0'),
rw => '0',
clk => clk,
rst => rst,
dump => '0',
address => address_codeword(((I+1)*(size_codeword) - 1) downto (I)*(size_codeword)),
rst_value => (others => '0'),
data_out => value_codeword(I downto I)
);
end generate;
test_syndrome : ram_double
Generic Map(
ram_address_size => size_syndrome,
ram_word_size => gf_2_m,
file_ram_word_size => gf_2_m,
load_file_name => "",
dump_file_name => dump_file_memory_syndrome
)
Port Map(
data_in_a => (others => '0'),
data_in_b => new_value_syndrome,
rw_a => '0',
rw_b => write_enable_new_syndrome,
clk => clk,
rst => rst,
dump => test_syndrome_dump,
address_a => address_syndrome,
address_b => address_new_syndrome,
rst_value => (others => '0'),
data_out_a => test_value_syndrome,
data_out_b => open
);
true_syndrome : ram
Generic Map(
ram_address_size => size_syndrome,
ram_word_size => gf_2_m,
file_ram_word_size => gf_2_m,
load_file_name => file_memory_syndrome,
dump_file_name => ""
)
Port Map(
data_in => (others => '0'),
rw => '0',
clk => clk,
rst => rst,
dump => '0',
address => true_address_syndrome,
rst_value => (others => '0'),
data_out => true_value_syndrome
);
address_syndrome <= true_address_syndrome when syndrome_finalized = '1' else test_address_syndrome;
clock : process
begin
while ( test_bench_finish /= '1') loop
clk <= not clk;
wait for PERIOD/2;
cycle_count <= cycle_count+1;
end loop;
wait;
end process;
--clk <= not clk after PERIOD/2;
mem_h_address <= address_h;
mem_L_address <= address_L;
synd_rst <= rst;
process
variable i : integer;
begin
true_address_syndrome <= (others => '0');
rst <= '1';
error_syndrome <= '0';
test_syndrome_dump <= '0';
wait for PERIOD*2;
rst <= '0';
wait until syndrome_finalized = '1';
report "Circuit finish = " & integer'image((cycle_count - 2)/2) & " cycles";
wait for PERIOD;
i := 0;
while (i < (length_syndrome)) loop
true_address_syndrome <= std_logic_vector(to_unsigned(i, true_address_syndrome'Length));
wait for PERIOD*2;
if (true_value_syndrome = test_value_syndrome) then
error_syndrome <= '0';
else
error_syndrome <= '1';
report "Computed values do not match expected ones";
end if;
wait for PERIOD;
error_syndrome <= '0';
wait for PERIOD;
i := i + 1;
end loop;
wait for PERIOD;
test_syndrome_dump <= '1';
wait for PERIOD;
test_syndrome_dump <= '0';
test_bench_finish <= '1';
wait;
end process;
end Behavioral;
|
bsd-2-clause
|
silence4395/CPU-Design
|
cpu/work/dmemory/_primary.vhd
|
4
|
302
|
library verilog;
use verilog.vl_types.all;
entity dmemory is
port(
address : in vl_logic_vector(31 downto 0);
data : inout vl_logic_vector(31 downto 0);
read : in vl_logic;
write : in vl_logic
);
end dmemory;
|
bsd-2-clause
|
silence4395/CPU-Design
|
cpu/work/cpu/_primary.vhd
|
4
|
66
|
library verilog;
use verilog.vl_types.all;
entity cpu is
end cpu;
|
bsd-2-clause
|
silence4395/CPU-Design
|
cpu/work/icache/_primary.vhd
|
4
|
640
|
library verilog;
use verilog.vl_types.all;
entity icache is
port(
clock : in vl_logic;
address : in vl_logic_vector(31 downto 0);
data : out vl_logic_vector(127 downto 0);
read : in vl_logic;
out_address : out vl_logic_vector(31 downto 0);
out_data : in vl_logic_vector(127 downto 0);
out_read : out vl_logic;
in_databus : in vl_logic_vector(63 downto 0);
out_databus : out vl_logic_vector(63 downto 0);
write_databus : out vl_logic
);
end icache;
|
bsd-2-clause
|
scottclowe/matlab-schemer
|
develop/sample.vhdl
|
3
|
382
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Comment about the Driver here
entity Driver is
port( x : in std_logic;
F : out std_logic
);
end Driver;
architecture gate_level of Driver is
begin
if newx(x downto (x-3))="0000" then
F <= '1';
else
F <= not(x(2) xor x(2)); --XNOR gate with 2 inputs
end if;
end gate_level;
|
bsd-2-clause
|
mithro/HDMI2USB-litex-firmware
|
gateware/encoder/vhdl/MDCT.vhd
|
2
|
8291
|
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2006-2009 --
-- --
--------------------------------------------------------------------------------
--
-- Title : DCT
-- Design : MDCT Core
-- Author : Michal Krepa
-- Company : None
--
--------------------------------------------------------------------------------
--
-- File : MDCT.VHD
-- Created : Sat Feb 25 16:12 2006
--
--------------------------------------------------------------------------------
--
-- Description : Discrete Cosine Transform - chip top level (w/ memories)
--
--------------------------------------------------------------------------------
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- /// Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library WORK;
use WORK.MDCT_PKG.all;
entity MDCT is
port(
clk : in STD_LOGIC;
rst : in std_logic;
dcti : in std_logic_vector(IP_W-1 downto 0);
idv : in STD_LOGIC;
odv : out STD_LOGIC;
dcto : out std_logic_vector(COE_W-1 downto 0);
-- debug
odv1 : out STD_LOGIC;
dcto1 : out std_logic_vector(OP_W-1 downto 0)
);
end MDCT;
architecture RTL of MDCT is
signal ramdatao_s : STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
signal ramraddro_s : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
signal ramwaddro_s : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
signal ramdatai_s : STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
signal ramwe_s : STD_LOGIC;
signal romedatao_s : T_ROM1DATAO;
signal romodatao_s : T_ROM1DATAO;
signal romeaddro_s : T_ROM1ADDRO;
signal romoaddro_s : T_ROM1ADDRO;
signal rome2datao_s : T_ROM2DATAO;
signal romo2datao_s : T_ROM2DATAO;
signal rome2addro_s : T_ROM2ADDRO;
signal romo2addro_s : T_ROM2ADDRO;
signal odv2_s : STD_LOGIC;
signal dcto2_s : STD_LOGIC_VECTOR(OP_W-1 downto 0);
signal trigger2_s : STD_LOGIC;
signal trigger1_s : STD_LOGIC;
signal ramdatao1_s : STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
signal ramdatao2_s : STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
signal ramwe1_s : STD_LOGIC;
signal ramwe2_s : STD_LOGIC;
signal memswitchrd_s : STD_LOGIC;
signal memswitchwr_s : STD_LOGIC;
signal wmemsel_s : STD_LOGIC;
signal rmemsel_s : STD_LOGIC;
signal dataready_s : STD_LOGIC;
signal datareadyack_s : STD_LOGIC;
begin
------------------------------
-- 1D DCT port map
------------------------------
U_DCT1D : entity work.DCT1D
port map(
clk => clk,
rst => rst,
dcti => dcti,
idv => idv,
romedatao => romedatao_s,
romodatao => romodatao_s,
odv => odv1,
dcto => dcto1,
romeaddro => romeaddro_s,
romoaddro => romoaddro_s,
ramwaddro => ramwaddro_s,
ramdatai => ramdatai_s,
ramwe => ramwe_s,
wmemsel => wmemsel_s
);
------------------------------
-- 1D DCT port map
------------------------------
U_DCT2D : entity work.DCT2D
port map(
clk => clk,
rst => rst,
romedatao => rome2datao_s,
romodatao => romo2datao_s,
ramdatao => ramdatao_s,
dataready => dataready_s,
odv => odv,
dcto => dcto,
romeaddro => rome2addro_s,
romoaddro => romo2addro_s,
ramraddro => ramraddro_s,
rmemsel => rmemsel_s,
datareadyack => datareadyack_s
);
------------------------------
-- RAM1 port map
------------------------------
U1_RAM : entity work.RAM
port map (
d => ramdatai_s,
waddr => ramwaddro_s,
raddr => ramraddro_s,
we => ramwe1_s,
clk => clk,
q => ramdatao1_s
);
------------------------------
-- RAM2 port map
------------------------------
U2_RAM : entity work.RAM
port map (
d => ramdatai_s,
waddr => ramwaddro_s,
raddr => ramraddro_s,
we => ramwe2_s,
clk => clk,
q => ramdatao2_s
);
-- double buffer switch
ramwe1_s <= ramwe_s when memswitchwr_s = '0' else '0';
ramwe2_s <= ramwe_s when memswitchwr_s = '1' else '0';
ramdatao_s <= ramdatao1_s when memswitchrd_s = '0' else ramdatao2_s;
------------------------------
-- DBUFCTL
------------------------------
U_DBUFCTL : entity work.DBUFCTL
port map(
clk => clk,
rst => rst,
wmemsel => wmemsel_s,
rmemsel => rmemsel_s,
datareadyack => datareadyack_s,
memswitchwr => memswitchwr_s,
memswitchrd => memswitchrd_s,
dataready => dataready_s
);
------------------------------
-- 1st stage ROMs
------------------------------
G_ROM_ST1 : for i in 0 to 8 generate
U1_ROME : entity work.ROME
port map(
addr => romeaddro_s(i),
clk => clk,
datao => romedatao_s(i)
);
U1_ROMO : entity work.ROMO
port map(
addr => romoaddro_s(i),
clk => clk,
datao => romodatao_s(i)
);
end generate G_ROM_ST1;
------------------------------
-- 2nd stage ROMs
------------------------------
G_ROM_ST2 : for i in 0 to 10 generate
U2_ROME : entity work.ROME
port map(
addr => rome2addro_s(i),
clk => clk,
datao => rome2datao_s(i)
);
U2_ROMO : entity work.ROMO
port map(
addr => romo2addro_s(i),
clk => clk,
datao => romo2datao_s(i)
);
end generate G_ROM_ST2;
end RTL;
|
bsd-2-clause
|
mithro/HDMI2USB-litex-firmware
|
gateware/encoder/vhdl/DoubleFifo.vhd
|
2
|
7973
|
-------------------------------------------------------------------------------
-- File Name : DoubleFifo.vhd
--
-- Project : JPEG_ENC
--
-- Module : DoubleFifo
--
-- Content : DoubleFifo
--
-- Description :
--
-- Spec. :
--
-- Author : Michal Krepa
--
-------------------------------------------------------------------------------
-- History :
-- 20090228: (MK): Initial Creation.
-------------------------------------------------------------------------------
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- /// Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- LIBRARY/PACKAGE ---------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- generic packages/libraries:
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- user packages/libraries:
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ENTITY ------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
entity DoubleFifo is
port
(
CLK : in std_logic;
RST : in std_logic;
-- HUFFMAN
data_in : in std_logic_vector(7 downto 0);
wren : in std_logic;
-- BYTE STUFFER
buf_sel : in std_logic;
rd_req : in std_logic;
fifo_empty : out std_logic;
data_out : out std_logic_vector(7 downto 0)
);
end entity DoubleFifo;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ARCHITECTURE ------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture RTL of DoubleFifo is
signal fifo1_rd : std_logic;
signal fifo1_wr : std_logic;
signal fifo1_q : std_logic_vector(7 downto 0);
signal fifo1_full : std_logic;
signal fifo1_empty : std_logic;
signal fifo1_count : std_logic_vector(7 downto 0);
signal fifo2_rd : std_logic;
signal fifo2_wr : std_logic;
signal fifo2_q : std_logic_vector(7 downto 0);
signal fifo2_full : std_logic;
signal fifo2_empty : std_logic;
signal fifo2_count : std_logic_vector(7 downto 0);
signal fifo_data_in : std_logic_vector(7 downto 0);
-------------------------------------------------------------------------------
-- Architecture: begin
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------
-- FIFO 1
-------------------------------------------------------------------
U_FIFO_1 : entity work.FIFO
generic map
(
DATA_WIDTH => 8,
ADDR_WIDTH => 7
)
port map
(
rst => RST,
clk => CLK,
rinc => fifo1_rd,
winc => fifo1_wr,
datai => fifo_data_in,
datao => fifo1_q,
fullo => fifo1_full,
emptyo => fifo1_empty,
count => fifo1_count
);
-------------------------------------------------------------------
-- FIFO 2
-------------------------------------------------------------------
U_FIFO_2 : entity work.FIFO
generic map
(
DATA_WIDTH => 8,
ADDR_WIDTH => 7
)
port map
(
rst => RST,
clk => CLK,
rinc => fifo2_rd,
winc => fifo2_wr,
datai => fifo_data_in,
datao => fifo2_q,
fullo => fifo2_full,
emptyo => fifo2_empty,
count => fifo2_count
);
-------------------------------------------------------------------
-- mux2
-------------------------------------------------------------------
p_mux2 : process(CLK, RST)
begin
if RST = '1' then
fifo1_wr <= '0';
fifo2_wr <= '0';
elsif CLK'event and CLK = '1' then
if buf_sel = '0' then
fifo1_wr <= wren;
else
fifo2_wr <= wren;
end if;
end if;
end process;
p_mux2_data : process(RST)
begin
if CLK'event and CLK = '1' then
fifo_data_in <= data_in;
end if;
end process;
-------------------------------------------------------------------
-- mux3
-------------------------------------------------------------------
p_mux3 : process(CLK, RST)
begin
if RST = '1' then
fifo1_rd <= '0';
fifo2_rd <= '0';
fifo_empty <= '0';
elsif CLK'event and CLK = '1' then
if buf_sel = '1' then
fifo1_rd <= rd_req;
fifo_empty <= fifo1_empty;
else
fifo2_rd <= rd_req;
fifo_empty <= fifo2_empty;
end if;
end if;
end process;
p_mux3_data : process(CLK)
begin
if CLK'event and CLK = '1' then
if buf_sel = '1' then
data_out <= fifo1_q;
else
data_out <= fifo2_q;
end if;
end if;
end process;
end architecture RTL;
-------------------------------------------------------------------------------
-- Architecture: end
-------------------------------------------------------------------------------
|
bsd-2-clause
|
nihospr01/OpenSpeechPlatform-UCSD
|
Firmware/FPGA/car_field_v6_fmexg/tb_fmexg_fifo_5_tmpl.vhd
|
1
|
2661
|
-- VHDL testbench template generated by SCUBA Diamond (64-bit) 3.10.0.111.2
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.math_real.all;
use IEEE.numeric_std.all;
entity tb is
end entity tb;
architecture test of tb is
component fmexg_fifo_5
port (Data : in std_logic_vector(11 downto 0);
WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic;
RdEn: in std_logic; Reset: in std_logic; RPReset: in std_logic;
Q : out std_logic_vector(11 downto 0); Empty: out std_logic;
Full: out std_logic; AlmostEmpty: out std_logic;
AlmostFull: out std_logic
);
end component;
signal Data : std_logic_vector(11 downto 0) := (others => '0');
signal WrClock: std_logic := '0';
signal RdClock: std_logic := '0';
signal WrEn: std_logic := '0';
signal RdEn: std_logic := '0';
signal Reset: std_logic := '0';
signal RPReset: std_logic := '0';
signal Q : std_logic_vector(11 downto 0);
signal Empty: std_logic;
signal Full: std_logic;
signal AlmostEmpty: std_logic;
signal AlmostFull: std_logic;
begin
u1 : fmexg_fifo_5
port map (Data => Data, WrClock => WrClock, RdClock => RdClock,
WrEn => WrEn, RdEn => RdEn, Reset => Reset, RPReset => RPReset,
Q => Q, Empty => Empty, Full => Full, AlmostEmpty => AlmostEmpty,
AlmostFull => AlmostFull
);
process
begin
Data <= (others => '0') ;
wait for 100 ns;
wait until Reset = '0';
for i in 0 to 8195 loop
wait until WrClock'event and WrClock = '1';
Data <= Data + '1' after 1 ns;
end loop;
wait;
end process;
WrClock <= not WrClock after 5.00 ns;
RdClock <= not RdClock after 5.00 ns;
process
begin
WrEn <= '0' ;
wait for 100 ns;
wait until Reset = '0';
for i in 0 to 8195 loop
wait until WrClock'event and WrClock = '1';
WrEn <= '1' after 1 ns;
end loop;
WrEn <= '0' ;
wait;
end process;
process
begin
RdEn <= '0' ;
wait until Reset = '0';
wait until WrEn = '1';
wait until WrEn = '0';
for i in 0 to 8195 loop
wait until RdClock'event and RdClock = '1';
RdEn <= '1' after 1 ns;
end loop;
RdEn <= '0' ;
wait;
end process;
process
begin
Reset <= '1' ;
wait for 100 ns;
Reset <= '0' ;
wait;
end process;
process
begin
RPReset <= '1' ;
wait for 100 ns;
RPReset <= '0' ;
wait;
end process;
end architecture test;
|
bsd-2-clause
|
athalonis/CCL-Verification-Environment
|
src/vhdl/ise/udp_high_tech/ipcore_dir/sb_dc_fifo.vhd
|
1
|
10265
|
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2014 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file sb_dc_fifo.vhd when simulating
-- the core, sb_dc_fifo. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY sb_dc_fifo IS
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC
);
END sb_dc_fifo;
ARCHITECTURE sb_dc_fifo_a OF sb_dc_fifo IS
-- synthesis translate_off
COMPONENT wrapped_sb_dc_fifo
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_sb_dc_fifo USE ENTITY XilinxCoreLib.fifo_generator_v8_4(behavioral)
GENERIC MAP (
c_add_ngc_constraint => 0,
c_application_type_axis => 0,
c_application_type_rach => 0,
c_application_type_rdch => 0,
c_application_type_wach => 0,
c_application_type_wdch => 0,
c_application_type_wrch => 0,
c_axi_addr_width => 32,
c_axi_aruser_width => 1,
c_axi_awuser_width => 1,
c_axi_buser_width => 1,
c_axi_data_width => 64,
c_axi_id_width => 4,
c_axi_ruser_width => 1,
c_axi_type => 0,
c_axi_wuser_width => 1,
c_axis_tdata_width => 64,
c_axis_tdest_width => 4,
c_axis_tid_width => 8,
c_axis_tkeep_width => 4,
c_axis_tstrb_width => 4,
c_axis_tuser_width => 4,
c_axis_type => 0,
c_common_clock => 0,
c_count_type => 0,
c_data_count_width => 10,
c_default_value => "BlankString",
c_din_width => 16,
c_din_width_axis => 1,
c_din_width_rach => 32,
c_din_width_rdch => 64,
c_din_width_wach => 32,
c_din_width_wdch => 64,
c_din_width_wrch => 2,
c_dout_rst_val => "0",
c_dout_width => 16,
c_enable_rlocs => 0,
c_enable_rst_sync => 1,
c_error_injection_type => 0,
c_error_injection_type_axis => 0,
c_error_injection_type_rach => 0,
c_error_injection_type_rdch => 0,
c_error_injection_type_wach => 0,
c_error_injection_type_wdch => 0,
c_error_injection_type_wrch => 0,
c_family => "virtex6",
c_full_flags_rst_val => 1,
c_has_almost_empty => 0,
c_has_almost_full => 0,
c_has_axi_aruser => 0,
c_has_axi_awuser => 0,
c_has_axi_buser => 0,
c_has_axi_rd_channel => 0,
c_has_axi_ruser => 0,
c_has_axi_wr_channel => 0,
c_has_axi_wuser => 0,
c_has_axis_tdata => 0,
c_has_axis_tdest => 0,
c_has_axis_tid => 0,
c_has_axis_tkeep => 0,
c_has_axis_tlast => 0,
c_has_axis_tready => 1,
c_has_axis_tstrb => 0,
c_has_axis_tuser => 0,
c_has_backup => 0,
c_has_data_count => 0,
c_has_data_counts_axis => 0,
c_has_data_counts_rach => 0,
c_has_data_counts_rdch => 0,
c_has_data_counts_wach => 0,
c_has_data_counts_wdch => 0,
c_has_data_counts_wrch => 0,
c_has_int_clk => 0,
c_has_master_ce => 0,
c_has_meminit_file => 0,
c_has_overflow => 0,
c_has_prog_flags_axis => 0,
c_has_prog_flags_rach => 0,
c_has_prog_flags_rdch => 0,
c_has_prog_flags_wach => 0,
c_has_prog_flags_wdch => 0,
c_has_prog_flags_wrch => 0,
c_has_rd_data_count => 0,
c_has_rd_rst => 0,
c_has_rst => 1,
c_has_slave_ce => 0,
c_has_srst => 0,
c_has_underflow => 0,
c_has_valid => 1,
c_has_wr_ack => 0,
c_has_wr_data_count => 0,
c_has_wr_rst => 0,
c_implementation_type => 2,
c_implementation_type_axis => 1,
c_implementation_type_rach => 1,
c_implementation_type_rdch => 1,
c_implementation_type_wach => 1,
c_implementation_type_wdch => 1,
c_implementation_type_wrch => 1,
c_init_wr_pntr_val => 0,
c_interface_type => 0,
c_memory_type => 1,
c_mif_file_name => "BlankString",
c_msgon_val => 1,
c_optimization_mode => 0,
c_overflow_low => 0,
c_preload_latency => 0,
c_preload_regs => 1,
c_prim_fifo_type => "1kx18",
c_prog_empty_thresh_assert_val => 4,
c_prog_empty_thresh_assert_val_axis => 1022,
c_prog_empty_thresh_assert_val_rach => 1022,
c_prog_empty_thresh_assert_val_rdch => 1022,
c_prog_empty_thresh_assert_val_wach => 1022,
c_prog_empty_thresh_assert_val_wdch => 1022,
c_prog_empty_thresh_assert_val_wrch => 1022,
c_prog_empty_thresh_negate_val => 5,
c_prog_empty_type => 0,
c_prog_empty_type_axis => 5,
c_prog_empty_type_rach => 5,
c_prog_empty_type_rdch => 5,
c_prog_empty_type_wach => 5,
c_prog_empty_type_wdch => 5,
c_prog_empty_type_wrch => 5,
c_prog_full_thresh_assert_val => 1023,
c_prog_full_thresh_assert_val_axis => 1023,
c_prog_full_thresh_assert_val_rach => 1023,
c_prog_full_thresh_assert_val_rdch => 1023,
c_prog_full_thresh_assert_val_wach => 1023,
c_prog_full_thresh_assert_val_wdch => 1023,
c_prog_full_thresh_assert_val_wrch => 1023,
c_prog_full_thresh_negate_val => 1022,
c_prog_full_type => 0,
c_prog_full_type_axis => 5,
c_prog_full_type_rach => 5,
c_prog_full_type_rdch => 5,
c_prog_full_type_wach => 5,
c_prog_full_type_wdch => 5,
c_prog_full_type_wrch => 5,
c_rach_type => 0,
c_rd_data_count_width => 10,
c_rd_depth => 1024,
c_rd_freq => 1,
c_rd_pntr_width => 10,
c_rdch_type => 0,
c_reg_slice_mode_axis => 0,
c_reg_slice_mode_rach => 0,
c_reg_slice_mode_rdch => 0,
c_reg_slice_mode_wach => 0,
c_reg_slice_mode_wdch => 0,
c_reg_slice_mode_wrch => 0,
c_synchronizer_stage => 2,
c_underflow_low => 0,
c_use_common_overflow => 0,
c_use_common_underflow => 0,
c_use_default_settings => 0,
c_use_dout_rst => 1,
c_use_ecc => 0,
c_use_ecc_axis => 0,
c_use_ecc_rach => 0,
c_use_ecc_rdch => 0,
c_use_ecc_wach => 0,
c_use_ecc_wdch => 0,
c_use_ecc_wrch => 0,
c_use_embedded_reg => 0,
c_use_fifo16_flags => 0,
c_use_fwft_data_count => 0,
c_valid_low => 0,
c_wach_type => 0,
c_wdch_type => 0,
c_wr_ack_low => 0,
c_wr_data_count_width => 10,
c_wr_depth => 1024,
c_wr_depth_axis => 1024,
c_wr_depth_rach => 16,
c_wr_depth_rdch => 1024,
c_wr_depth_wach => 16,
c_wr_depth_wdch => 1024,
c_wr_depth_wrch => 16,
c_wr_freq => 1,
c_wr_pntr_width => 10,
c_wr_pntr_width_axis => 10,
c_wr_pntr_width_rach => 4,
c_wr_pntr_width_rdch => 10,
c_wr_pntr_width_wach => 4,
c_wr_pntr_width_wdch => 10,
c_wr_pntr_width_wrch => 4,
c_wr_response_latency => 1,
c_wrch_type => 0
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_sb_dc_fifo
PORT MAP (
rst => rst,
wr_clk => wr_clk,
rd_clk => rd_clk,
din => din,
wr_en => wr_en,
rd_en => rd_en,
dout => dout,
full => full,
empty => empty,
valid => valid
);
-- synthesis translate_on
END sb_dc_fifo_a;
|
bsd-2-clause
|
athalonis/CCL-Verification-Environment
|
src/vhdl/communication/udp_ip_stack/trunk/bench/vhdl/UDP_RX_tb.vhd
|
1
|
13349
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:53:03 06/10/2011
-- Design Name:
-- Module Name: C:/Users/pjf/Documents/projects/fpga/xilinx/Network/ip1/UDP_RX_tb.vhd
-- Project Name: ip1
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: UDP_RX
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.axi.all;
use work.ipv4_types.all;
ENTITY UDP_RX_tb IS
END UDP_RX_tb;
ARCHITECTURE behavior OF UDP_RX_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT UDP_RX
PORT(
-- UDP Layer signals
udp_rxo : inout udp_rx_type;
udp_rx_start : out std_logic; -- indicates receipt of udp header
-- system signals
clk : in STD_LOGIC;
reset : in STD_LOGIC;
-- IP layer RX signals
ip_rx_start : in std_logic; -- indicates receipt of ip header
ip_rx : inout ipv4_rx_type
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal ip_rx_start : std_logic := '0';
--BiDirs
signal udp_rxo : udp_rx_type;
signal ip_rx : ipv4_rx_type;
--Outputs
signal udp_rx_start : std_logic;
-- Clock period definitions
constant clk_period : time := 8 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: UDP_RX PORT MAP (
udp_rxo => udp_rxo,
udp_rx_start => udp_rx_start,
clk => clk,
reset => reset,
ip_rx_start => ip_rx_start,
ip_rx => ip_rx
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
ip_rx_start <= '0';
ip_rx.data.data_in_valid <= '0';
ip_rx.data.data_in_last <= '0';
ip_rx.hdr.is_valid <= '0';
ip_rx.hdr.protocol <= (others => '0');
ip_rx.hdr.num_frame_errors <= (others => '0');
ip_rx.hdr.last_error_code <= (others => '0');
ip_rx.hdr.is_broadcast <= '0';
reset <= '1';
wait for clk_period*10;
reset <= '0';
wait for clk_period*5;
reset <= '0';
-- check reset conditions
assert udp_rx_start = '0' report "udp_rx_start not initialised correctly on reset";
assert udp_rxo.hdr.is_valid = '0' report "udp_rxo.hdr.is_valid not initialised correctly on reset";
assert udp_rxo.data.data_in = x"00" report "udp_rxo.data.data_in not initialised correctly on reset";
assert udp_rxo.data.data_in_valid = '0' report "udp_rxo.data.data_in_valid not initialised correctly on reset";
assert udp_rxo.data.data_in_last = '0' report "udp_rxo.data.data_in_last not initialised correctly on reset";
-- insert stimulus here
------------
-- TEST 1 -- basic functional rx test with received ip pkt
------------
report "T1: Send an ip frame with IP src ip_address c0a80501, udp protocol from port x1498 to port x8724 and 3 bytes data";
ip_rx_start <= '1';
ip_rx.data.data_in_valid <= '0';
ip_rx.data.data_in_last <= '0';
ip_rx.hdr.is_valid <= '1';
ip_rx.hdr.protocol <= x"11"; -- UDP
ip_rx.hdr.data_length <= x"000b";
ip_rx.hdr.src_ip_addr<= x"c0a80501";
wait for clk_period*3;
-- now send the data
ip_rx.data.data_in_valid <= '1';
ip_rx.data.data_in <= x"14"; wait for clk_period; -- src port
ip_rx.data.data_in <= x"98"; wait for clk_period;
ip_rx.data.data_in <= x"87"; wait for clk_period; -- dst port
ip_rx.data.data_in <= x"24"; wait for clk_period;
ip_rx.data.data_in <= x"00"; wait for clk_period; -- len (hdr + data)
ip_rx.data.data_in <= x"0b"; wait for clk_period;
ip_rx.data.data_in <= x"00"; wait for clk_period; -- mty cks
ip_rx.data.data_in <= x"00"; wait for clk_period;
-- udp hdr should be valid
assert udp_rxo.hdr.is_valid = '1' report "T1: udp_rxo.hdr.is_valid not set";
ip_rx.data.data_in <= x"41"; wait for clk_period; -- data
assert udp_rxo.hdr.src_ip_addr = x"c0a80501" report "T1: udp_rxo.hdr.src_ip_addr not set correctly";
assert udp_rxo.hdr.src_port = x"1498" report "T1: udp_rxo.hdr.src_port not set correctly";
assert udp_rxo.hdr.dst_port = x"8724" report "T1: udp_rxo.hdr.dst_port not set correctly";
assert udp_rxo.hdr.data_length = x"0003" report "T1: udp_rxo.hdr.data_length not set correctly";
assert udp_rx_start = '1' report "T1: udp_rx_start not set";
assert udp_rxo.data.data_in_valid = '1' report "T1: udp_rxo.data.data_in_valid not set";
ip_rx.data.data_in <= x"45"; wait for clk_period; -- data
ip_rx.data.data_in <= x"49"; ip_rx.data.data_in_last <= '1'; wait for clk_period;
assert udp_rxo.data.data_in_last = '1' report "T1: udp_rxo.data.data_in_last not set";
ip_rx_start <= '0';
ip_rx.data.data_in_valid <= '0';
ip_rx.data.data_in_last <= '0';
ip_rx.hdr.is_valid <= '0';
wait for clk_period;
assert udp_rxo.data.data_in = x"00" report "T1: udp_rxo.data.data_in not cleared";
assert udp_rxo.data.data_in_valid = '0' report "T1: udp_rxo.data.data_in_valid not cleared";
assert udp_rxo.data.data_in_last = '0' report "T1: udp_rxo.data.data_in_last not cleared";
wait for clk_period;
------------
-- TEST 2 -- ability to receive 2nd ip pkt
------------
report "T2: Send an ip frame with IP src ip_address c0a80501, udp protocol from port x7623 to port x0365 and 5 bytes data";
ip_rx_start <= '1';
ip_rx.data.data_in_valid <= '0';
ip_rx.data.data_in_last <= '0';
ip_rx.hdr.is_valid <= '1';
ip_rx.hdr.protocol <= x"11"; -- UDP
ip_rx.hdr.data_length <= x"000b";
ip_rx.hdr.src_ip_addr<= x"c0a80501";
wait for clk_period*3;
-- now send the data
ip_rx.data.data_in_valid <= '1';
ip_rx.data.data_in <= x"76"; wait for clk_period; -- src port
ip_rx.data.data_in <= x"23"; wait for clk_period;
ip_rx.data.data_in <= x"03"; wait for clk_period; -- dst port
ip_rx.data.data_in <= x"65"; wait for clk_period;
ip_rx.data.data_in <= x"00"; wait for clk_period; -- len (hdr + data)
ip_rx.data.data_in <= x"0d"; wait for clk_period;
ip_rx.data.data_in <= x"00"; wait for clk_period; -- mty cks
ip_rx.data.data_in <= x"00"; wait for clk_period;
-- udp hdr should be valid
assert udp_rxo.hdr.is_valid = '1' report "T2: udp_rxo.hdr.is_valid not set";
ip_rx.data.data_in <= x"17"; wait for clk_period; -- data
assert udp_rxo.hdr.src_ip_addr = x"c0a80501" report "T2: udp_rxo.hdr.src_ip_addr not set correctly";
assert udp_rxo.hdr.src_port = x"7623" report "T2: udp_rxo.hdr.src_port not set correctly";
assert udp_rxo.hdr.dst_port = x"0365" report "T2: udp_rxo.hdr.dst_port not set correctly";
assert udp_rxo.hdr.data_length = x"0005" report "T2: udp_rxo.hdr.data_length not set correctly";
assert udp_rx_start = '1' report "T2: udp_rx_start not set";
assert udp_rxo.data.data_in_valid = '1' report "T2: udp_rxo.data.data_in_valid not set";
ip_rx.data.data_in <= x"37"; wait for clk_period; -- data
ip_rx.data.data_in <= x"57"; wait for clk_period; -- data
ip_rx.data.data_in <= x"73"; wait for clk_period; -- data
ip_rx.data.data_in <= x"f9"; ip_rx.data.data_in_last <= '1'; wait for clk_period;
assert udp_rxo.data.data_in_last = '1' report "T2: udp_rxo.data.data_in_last not set";
ip_rx_start <= '0';
ip_rx.data.data_in_valid <= '0';
ip_rx.data.data_in_last <= '0';
ip_rx.hdr.is_valid <= '0';
wait for clk_period;
assert udp_rxo.data.data_in = x"00" report "T2: udp_rxo.data.data_in not cleared";
assert udp_rxo.data.data_in_valid = '0' report "T2: udp_rxo.data.data_in_valid not cleared";
assert udp_rxo.data.data_in_last = '0' report "T2: udp_rxo.data.data_in_last not cleared";
------------
-- TEST 3 -- ability to reject non-udp protocols
------------
report "T3: Send an ip frame with IP src ip_address c0a80501, protocol x12 from port x7623 to port x0365 and 5 bytes data";
ip_rx_start <= '1';
ip_rx.data.data_in_valid <= '0';
ip_rx.data.data_in_last <= '0';
ip_rx.hdr.is_valid <= '1';
ip_rx.hdr.protocol <= x"12"; -- non-UDP
ip_rx.hdr.data_length <= x"000b";
ip_rx.hdr.src_ip_addr<= x"c0a80501";
wait for clk_period*3;
-- now send the data
ip_rx.data.data_in_valid <= '1';
ip_rx.data.data_in <= x"76"; wait for clk_period; -- src port
ip_rx.data.data_in <= x"23"; wait for clk_period;
ip_rx.data.data_in <= x"03"; wait for clk_period; -- dst port
ip_rx.data.data_in <= x"65"; wait for clk_period;
ip_rx.data.data_in <= x"00"; wait for clk_period; -- len (hdr + data)
ip_rx.data.data_in <= x"0d"; wait for clk_period;
ip_rx.data.data_in <= x"00"; wait for clk_period; -- mty cks
ip_rx.data.data_in <= x"00"; wait for clk_period;
-- udp hdr should be valid
assert udp_rxo.hdr.is_valid = '0' report "T3: udp_rxo.hdr.is_valid incorrectly set";
ip_rx.data.data_in <= x"17"; wait for clk_period; -- data
assert udp_rx_start = '0' report "T3: udp_rx_start incorrectly set";
assert udp_rxo.data.data_in_valid = '0' report "T3: udp_rxo.data.data_in_valid not set";
ip_rx.data.data_in <= x"37"; wait for clk_period; -- data
ip_rx.data.data_in <= x"57"; wait for clk_period; -- data
ip_rx.data.data_in <= x"73"; wait for clk_period; -- data
ip_rx.data.data_in <= x"f9"; ip_rx.data.data_in_last <= '1'; wait for clk_period;
assert udp_rxo.data.data_in_last = '0' report "T3: udp_rxo.data.data_in_last incorrectly set";
ip_rx_start <= '0';
ip_rx.data.data_in_valid <= '0';
ip_rx.data.data_in_last <= '0';
ip_rx.hdr.is_valid <= '0';
wait for clk_period;
assert udp_rxo.data.data_in = x"00" report "T3: udp_rxo.data.data_in not cleared";
assert udp_rxo.data.data_in_valid = '0' report "T3: udp_rxo.data.data_in_valid not cleared";
assert udp_rxo.data.data_in_last = '0' report "T3: udp_rxo.data.data_in_last not cleared";
wait for clk_period;
------------
-- TEST 4 -- Ability to receive UDP pkt after non-UDP pkt
------------
report "T4: Send an ip frame with IP src ip_address c0a80501, udp protocol from port x1498 to port x8724 and 3 bytes data";
ip_rx_start <= '1';
ip_rx.data.data_in_valid <= '0';
ip_rx.data.data_in_last <= '0';
ip_rx.hdr.is_valid <= '1';
ip_rx.hdr.protocol <= x"11"; -- UDP
ip_rx.hdr.data_length <= x"000b";
ip_rx.hdr.src_ip_addr<= x"c0a80501";
wait for clk_period*3;
-- now send the data
ip_rx.data.data_in_valid <= '1';
ip_rx.data.data_in <= x"14"; wait for clk_period; -- src port
ip_rx.data.data_in <= x"98"; wait for clk_period;
ip_rx.data.data_in <= x"87"; wait for clk_period; -- dst port
ip_rx.data.data_in <= x"24"; wait for clk_period;
ip_rx.data.data_in <= x"00"; wait for clk_period; -- len (hdr + data)
ip_rx.data.data_in <= x"0b"; wait for clk_period;
ip_rx.data.data_in <= x"00"; wait for clk_period; -- mty cks
ip_rx.data.data_in <= x"00"; wait for clk_period;
-- udp hdr should be valid
assert udp_rxo.hdr.is_valid = '1' report "T4: udp_rxo.hdr.is_valid not set";
ip_rx.data.data_in <= x"41"; wait for clk_period; -- data
assert udp_rxo.hdr.src_ip_addr = x"c0a80501" report "T4: udp_rxo.hdr.src_ip_addr not set correctly";
assert udp_rxo.hdr.src_port = x"1498" report "T4: udp_rxo.hdr.src_port not set correctly";
assert udp_rxo.hdr.dst_port = x"8724" report "T4: udp_rxo.hdr.dst_port not set correctly";
assert udp_rxo.hdr.data_length = x"0003" report "T4: udp_rxo.hdr.data_length not set correctly";
assert udp_rx_start = '1' report "T4: udp_rx_start not set";
assert udp_rxo.data.data_in_valid = '1' report "T4: udp_rxo.data.data_in_valid not set";
ip_rx.data.data_in <= x"45"; wait for clk_period; -- data
ip_rx.data.data_in <= x"49"; ip_rx.data.data_in_last <= '1'; wait for clk_period;
assert udp_rxo.data.data_in_last = '1' report "T4: udp_rxo.data.data_in_last not set";
ip_rx_start <= '0';
ip_rx.data.data_in_valid <= '0';
ip_rx.data.data_in_last <= '0';
ip_rx.hdr.is_valid <= '0';
wait for clk_period;
assert udp_rxo.data.data_in = x"00" report "T4: udp_rxo.data.data_in not cleared";
assert udp_rxo.data.data_in_valid = '0' report "T4: udp_rxo.data.data_in_valid not cleared";
assert udp_rxo.data.data_in_last = '0' report "T4: udp_rxo.data.data_in_last not cleared";
wait for clk_period;
report "--- end of tests ---";
wait;
end process;
END;
|
bsd-2-clause
|
athalonis/CCL-Verification-Environment
|
src/vhdl/communication/udp_ip_stack/trunk/bench/vhdl/arp_STORE_tb.vhd
|
1
|
14738
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 07:38:43 02/13/2012
-- Design Name:
-- Module Name: arp_STORE_tb.vhd
-- Project Name: udp3
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: arp_STORE_br
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_unsigned.all;
use work.arp_types.all;
ENTITY arp_STORE_tb IS
END arp_STORE_tb;
ARCHITECTURE behavior OF arp_STORE_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT arp_STORE_br
generic (
MAX_ARP_ENTRIES : integer := 256 -- max entries in the store
);
PORT(
-- read signals
read_req : in arp_store_rdrequest_t; -- requesting a '1' or store
read_result : out arp_store_result_t; -- the result
-- write signals
write_req : in arp_store_wrrequest_t; -- requesting a '1' or store
-- control and status signals
clear_store : in std_logic; -- erase all entries
entry_count : out unsigned(7 downto 0); -- how many entries currently in store
-- system signals
clk : in std_logic;
reset : in STD_LOGIC
);
END COMPONENT;
--Inputs
signal read_req : arp_store_rdrequest_t;
signal write_req : arp_store_wrrequest_t;
signal clear_store : std_logic := '0';
signal clk : std_logic := '0';
signal reset : std_logic := '0';
--Outputs
signal read_result : arp_store_result_t;
signal entry_count : unsigned(7 downto 0); -- how many entries currently in store
-- Clock period definitions
constant clk_period : time := 8 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: arp_STORE_br
generic map (
MAX_ARP_ENTRIES => 4
)
PORT MAP (
read_req => read_req,
read_result => read_result,
write_req => write_req,
clear_store => clear_store,
entry_count => entry_count,
clk => clk,
reset => reset
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
read_req.req <= '0';
read_req.ip <= (others => '0');
write_req.req <= '0';
write_req.entry.ip <= (others => '0');
write_req.entry.mac <= (others => '0');
reset <= '1';
-- hold reset state
wait for clk_period*10;
reset <= '0';
-- insert stimulus here
report "T1 - look for something when store is empty";
read_req.ip <= x"12345678";
read_req.req <= '1';
wait for clk_period*4;
assert read_result.status = NOT_FOUND report "T1: expected NOT_FOUND";
wait for clk_period;
read_req.req <= '0';
wait for clk_period*2;
assert read_result.status = IDLE report "T1: expected IDLE";
assert entry_count = x"00" report "T1: wrong entry count";
report "T2 - insert first entry into store";
write_req.entry.ip <= x"12345678";
write_req.entry.mac <= x"002398127645";
write_req.req <= '1';
wait for clk_period;
write_req.req <= '0';
wait until read_result.status = IDLE;
wait for clk_period;
assert entry_count = x"01" report "T2: wrong entry count";
report "T3 - check if can find this single entry";
read_req.ip <= x"12345678";
read_req.req <= '1';
wait until read_result.status = FOUND or read_result.status = NOT_FOUND;
wait for clk_period;
assert read_result.status = FOUND report "T3: expected FOUND";
assert read_result.entry.ip = x"12345678" report "T3: wrong ip addr";
assert read_result.entry.mac = x"002398127645" report "T3: wrong mac addr";
wait for clk_period;
read_req.req <= '0';
wait for clk_period*3;
assert read_result.status = IDLE report "T3: expected IDLE";
report "T4 - check unable to find missing entry with one entry in store";
read_req.ip <= x"12345679";
read_req.req <= '1';
wait until read_result.status = FOUND or read_result.status = NOT_FOUND;
wait for clk_period;
assert read_result.status = NOT_FOUND report "T4: expected NOT_FOUND";
wait for clk_period;
read_req.req <= '0';
wait for clk_period*3;
assert read_result.status = IDLE report "T4: expected IDLE";
report "T5 - insert 2nd entry into store and check can find both entries";
write_req.entry.ip <= x"12345679";
write_req.entry.mac <= x"101202303404";
write_req.req <= '1';
wait for clk_period;
write_req.req <= '0';
wait until read_result.status = IDLE;
wait for clk_period;
assert entry_count = x"02" report "T4: wrong entry count";
read_req.ip <= x"12345678";
read_req.req <= '1';
wait until read_result.status = FOUND or read_result.status = NOT_FOUND;
wait for clk_period;
assert read_result.status = FOUND report "T5.1: expected FOUND";
assert read_result.entry.ip = x"12345678" report "T5.1: wrong ip addr";
assert read_result.entry.mac = x"002398127645" report "T5.1: wrong mac addr";
read_req.req <= '0';
wait for clk_period*3;
assert read_result.status = IDLE report "T5.1: expected IDLE";
read_req.ip <= x"12345679";
read_req.req <= '1';
wait until read_result.status = FOUND or read_result.status = NOT_FOUND;
wait for clk_period;
assert read_result.status = FOUND report "T5.2: expected FOUND";
assert read_result.entry.ip = x"12345679" report "T5.2: wrong ip addr";
assert read_result.entry.mac = x"101202303404" report "T5.2: wrong mac addr";
read_req.req <= '0';
wait for clk_period*3;
assert read_result.status = IDLE report "T5.2: expected IDLE";
report "T6 - insert 2 more entries so that the store is full. check can find all";
write_req.entry.ip <= x"1234567a";
write_req.entry.mac <= x"10120230340a";
write_req.req <= '1';
wait for clk_period;
write_req.req <= '0';
wait until read_result.status = IDLE;
wait for clk_period;
write_req.entry.ip <= x"1234567b";
write_req.entry.mac <= x"10120230340b";
write_req.req <= '1';
wait for clk_period;
write_req.req <= '0';
wait until read_result.status = IDLE;
wait for clk_period;
assert entry_count = x"04" report "T6: wrong entry count";
read_req.ip <= x"12345678";
read_req.req <= '1';
wait until read_result.status = FOUND or read_result.status = NOT_FOUND;
wait for clk_period;
assert read_result.status = FOUND report "T6.1: expected FOUND";
assert read_result.entry.ip = x"12345678" report "T6.1: wrong ip addr";
assert read_result.entry.mac = x"002398127645" report "T6.1: wrong mac addr";
read_req.req <= '0';
wait for clk_period*3;
assert read_result.status = IDLE report "T6.1: expected IDLE";
read_req.ip <= x"12345679";
read_req.req <= '1';
wait until read_result.status = FOUND or read_result.status = NOT_FOUND;
wait for clk_period;
assert read_result.status = FOUND report "T6.2: expected FOUND";
assert read_result.entry.ip = x"12345679" report "T6.2: wrong ip addr";
assert read_result.entry.mac = x"101202303404" report "T6.2: wrong mac addr";
read_req.req <= '0';
wait for clk_period*3;
assert read_result.status = IDLE report "T6.2: expected IDLE";
read_req.ip <= x"1234567a";
read_req.req <= '1';
wait until read_result.status = FOUND or read_result.status = NOT_FOUND;
wait for clk_period;
assert read_result.status = FOUND report "T6.3: expected FOUND";
assert read_result.entry.ip = x"1234567a" report "T6.3: wrong ip addr";
assert read_result.entry.mac = x"10120230340a" report "T6.3: wrong mac addr";
read_req.req <= '0';
wait for clk_period*3;
assert read_result.status = IDLE report "T6.3: expected IDLE";
read_req.ip <= x"1234567b";
read_req.req <= '1';
wait until read_result.status = FOUND or read_result.status = NOT_FOUND;
wait for clk_period;
assert read_result.status = FOUND report "T6.4: expected FOUND";
assert read_result.entry.ip = x"1234567b" report "T6.4: wrong ip addr";
assert read_result.entry.mac = x"10120230340b" report "T6.4: wrong mac addr";
read_req.req <= '0';
wait for clk_period*3;
assert read_result.status = IDLE report "T6.4: expected IDLE";
report "T7 - with store full, check that we dont find missing item";
read_req.ip <= x"1233367b";
read_req.req <= '1';
wait until read_result.status = FOUND or read_result.status = NOT_FOUND;
wait for clk_period;
assert read_result.status = NOT_FOUND report "T7: expected NOT_FOUND";
read_req.req <= '0';
wait for clk_period*3;
assert read_result.status = IDLE report "T7: expected IDLE";
report "T8 - insert additional entry into store - will erase one of the others";
write_req.entry.ip <= x"12345699";
write_req.entry.mac <= x"992398127699";
write_req.req <= '1';
wait for clk_period;
write_req.req <= '0';
wait until read_result.status = IDLE;
wait for clk_period;
assert entry_count = x"04" report "T8: wrong entry count";
read_req.ip <= x"12345699";
read_req.req <= '1';
wait until read_result.status = FOUND or read_result.status = NOT_FOUND;
wait for clk_period;
assert read_result.status = FOUND report "T8: expected FOUND";
assert read_result.entry.ip = x"12345699" report "T8: wrong ip addr";
assert read_result.entry.mac = x"992398127699" report "T8: wrong mac addr";
read_req.req <= '0';
wait for clk_period*3;
assert read_result.status = IDLE report "T8: expected IDLE";
report "T9 - clear the store and ensure cant find something that was there";
clear_store <= '1';
wait for clk_period;
clear_store <= '0';
wait for clk_period;
assert entry_count = x"00" report "T9: wrong entry count";
read_req.ip <= x"12345699";
read_req.req <= '1';
wait until read_result.status = FOUND or read_result.status = NOT_FOUND;
wait for clk_period;
assert read_result.status = NOT_FOUND report "T9: expected NOT_FOUND";
read_req.req <= '0';
wait for clk_period*3;
assert read_result.status = IDLE report "T9: expected IDLE";
report "T10 - refill the store with three entries";
write_req.entry.ip <= x"12345675";
write_req.entry.mac <= x"10120230340a";
write_req.req <= '1';
wait for clk_period;
write_req.req <= '0';
wait until read_result.status = IDLE;
wait for clk_period;
write_req.entry.ip <= x"12345676";
write_req.entry.mac <= x"10120230340b";
write_req.req <= '1';
wait for clk_period;
write_req.req <= '0';
wait until read_result.status = IDLE;
wait for clk_period;
write_req.entry.ip <= x"12345677";
write_req.entry.mac <= x"10120230340c";
write_req.req <= '1';
wait for clk_period;
write_req.req <= '0';
wait until read_result.status = IDLE;
wait for clk_period;
assert entry_count = x"03" report "T10: wrong entry count";
report "T11 - check middle entry, then change it and check again";
read_req.ip <= x"12345676";
read_req.req <= '1';
wait until read_result.status = FOUND or read_result.status = NOT_FOUND;
wait for clk_period;
assert read_result.status = FOUND report "T11.1: expected FOUND";
assert read_result.entry.ip = x"12345676" report "T11.1: wrong ip addr";
assert read_result.entry.mac = x"10120230340b" report "T11.1: wrong mac addr";
read_req.req <= '0';
wait for clk_period*3;
assert read_result.status = IDLE report "T11.1: expected IDLE";
write_req.entry.ip <= x"12345676";
write_req.entry.mac <= x"10120990340b";
write_req.req <= '1';
wait for clk_period;
write_req.req <= '0';
wait for clk_period;
assert entry_count = x"03" report "T11: wrong entry count";
read_req.ip <= x"12345676";
read_req.req <= '1';
wait until read_result.status = FOUND or read_result.status = NOT_FOUND;
wait for clk_period;
assert read_result.status = FOUND report "T11.2: expected FOUND";
assert read_result.entry.ip = x"12345676" report "T11.2: wrong ip addr";
assert read_result.entry.mac = x"10120990340b" report "T11.2: wrong mac addr";
read_req.req <= '0';
wait for clk_period*3;
assert read_result.status = IDLE report "T11.2: expected IDLE";
report "T12 - check 2nd write at beginning";
-- clear store, write 1st entry, overwrite the entry, and check
clear_store <= '1';
wait for clk_period;
clear_store <= '0';
wait for clk_period;
assert entry_count = x"00" report "T12.1: wrong entry count";
write_req.entry.ip <= x"12345678";
write_req.entry.mac <= x"002398127645";
write_req.req <= '1';
wait for clk_period;
write_req.req <= '0';
wait until read_result.status = IDLE;
wait for clk_period;
assert entry_count = x"01" report "T12.2: wrong entry count";
write_req.entry.ip <= x"12345678";
write_req.entry.mac <= x"002398127647";
write_req.req <= '1';
wait for clk_period;
write_req.req <= '0';
wait until read_result.status = IDLE;
wait for clk_period;
assert entry_count = x"01" report "T12.3: wrong entry count";
read_req.ip <= x"12345678";
read_req.req <= '1';
wait until read_result.status = FOUND or read_result.status = NOT_FOUND;
wait for clk_period;
assert read_result.status = FOUND report "T12.4: expected FOUND";
assert read_result.entry.ip = x"12345678" report "T12.4: wrong ip addr";
assert read_result.entry.mac = x"002398127647" report "T12.4: wrong mac addr";
read_req.req <= '0';
wait for clk_period*3;
assert read_result.status = IDLE report "T12.5: expected IDLE";
report "--- end of tests ---";
wait;
end process;
END;
|
bsd-2-clause
|
athalonis/CCL-Verification-Environment
|
src/vhdl/communication/udp_ip_stack/trunk/rtl/vhdl/arp_STORE_br.vhd
|
2
|
10817
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Peter Fall
--
-- Create Date: 12:00:04 05/31/2011
-- Design Name:
-- Module Name: arp_STORE_br - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- ARP storage table using block ram with lookup based on IP address
-- implements upto 255 entries with sequential search
-- uses round robin overwrite when full (LRU would be better, but ...)
--
-- store may take a number of cycles and the request is latched
-- lookup may take a number of cycles. Assumes that request signals remain valid during lookup
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use ieee.std_logic_unsigned.all;
use work.arp_types.all;
entity arp_STORE_br is
generic (
MAX_ARP_ENTRIES : integer := 255 -- max entries in the store
);
port (
-- read signals
read_req : in arp_store_rdrequest_t; -- requesting a lookup or store
read_result : out arp_store_result_t; -- the result
-- write signals
write_req : in arp_store_wrrequest_t; -- requesting a lookup or store
-- control and status signals
clear_store : in std_logic; -- erase all entries
entry_count : out unsigned(7 downto 0); -- how many entries currently in store
-- system signals
clk : in std_logic;
reset : in std_logic
);
end arp_STORE_br;
architecture Behavioral of arp_STORE_br is
type st_state_t is (IDLE, PAUSE, SEARCH, FOUND, NOT_FOUND);
type ip_ram_t is array (0 to MAX_ARP_ENTRIES-1) of std_logic_vector(31 downto 0);
type mac_ram_t is array (0 to MAX_ARP_ENTRIES-1) of std_logic_vector(47 downto 0);
subtype addr_t is integer range 0 to MAX_ARP_ENTRIES;
type count_mode_t is (RST, INCR, HOLD);
type mode_t is (MREAD, MWRITE);
-- state variables
signal ip_ram : ip_ram_t; -- will be implemented as block ram
signal mac_ram : mac_ram_t; -- will be implemented as block ram
signal st_state : st_state_t;
signal next_write_addr : addr_t; -- where to make the next write
signal num_entries : addr_t; -- number of entries in the store
signal next_read_addr : addr_t; -- next addr to read from
signal entry_found : arp_entry_t; -- entry found in search
signal mode : mode_t; -- are we writing or reading?
signal req_entry : arp_entry_t; -- entry latched from req
-- busses
signal next_st_state : st_state_t;
signal arp_entry_val : arp_entry_t;
signal mode_val : mode_t;
signal write_addr : addr_t; -- actual write address to use
signal read_result_int : arp_store_result_t;
-- control signals
signal set_st_state : std_logic;
signal set_next_write_addr : count_mode_t;
signal set_num_entries : count_mode_t;
signal set_next_read_addr : count_mode_t;
signal write_ram : std_logic;
signal set_entry_found : std_logic;
signal set_mode : std_logic;
function read_status(status : arp_store_rslt_t; signal mode : mode_t) return arp_store_rslt_t is
variable ret : arp_store_rslt_t;
begin
case status is
when IDLE =>
ret := status;
when others =>
if mode = MWRITE then
ret := BUSY;
else
ret := status;
end if;
end case;
return ret;
end read_status;
begin
combinatorial : process (
-- input signals
read_req, write_req, clear_store, reset,
-- state variables
ip_ram, mac_ram, st_state, next_write_addr, num_entries,
next_read_addr, entry_found, mode, req_entry,
-- busses
next_st_state, arp_entry_val, mode_val, write_addr, read_result_int,
-- control signals
set_st_state, set_next_write_addr, set_num_entries, set_next_read_addr, set_entry_found,
write_ram, set_mode
)
begin
-- set output followers
read_result_int.status <= IDLE;
read_result_int.entry <= entry_found;
entry_count <= to_unsigned(num_entries, 8);
-- set bus defaults
next_st_state <= IDLE;
mode_val <= MREAD;
write_addr <= next_write_addr;
-- set signal defaults
set_st_state <= '0';
set_next_write_addr <= HOLD;
set_num_entries <= HOLD;
set_next_read_addr <= HOLD;
write_ram <= '0';
set_entry_found <= '0';
set_mode <= '0';
-- STORE FSM
case st_state is
when IDLE =>
if write_req.req = '1' then
-- need to search to see if this IP already there
set_next_read_addr <= RST; -- start lookup from beginning
mode_val <= MWRITE;
set_mode <= '1';
next_st_state <= PAUSE;
set_st_state <= '1';
elsif read_req.req = '1' then
set_next_read_addr <= RST; -- start lookup from beginning
mode_val <= MREAD;
set_mode <= '1';
next_st_state <= PAUSE;
set_st_state <= '1';
end if;
when PAUSE =>
-- wait until read addr is latched and we get first data out of the ram
read_result_int.status <= read_status(BUSY, mode);
set_next_read_addr <= INCR;
next_st_state <= SEARCH;
set_st_state <= '1';
when SEARCH =>
read_result_int.status <= read_status(SEARCHING, mode);
-- check if have a match at this entry
if req_entry.ip = arp_entry_val.ip and next_read_addr <= num_entries then
-- found it
set_entry_found <= '1';
next_st_state <= FOUND;
set_st_state <= '1';
elsif next_read_addr > num_entries or next_read_addr >= MAX_ARP_ENTRIES then
-- reached end of entry table
read_result_int.status <= read_status(NOT_FOUND, mode);
next_st_state <= NOT_FOUND;
set_st_state <= '1';
else
-- no match at this entry , go to next
set_next_read_addr <= INCR;
end if;
when FOUND =>
read_result_int.status <= read_status(FOUND, mode);
if mode = MWRITE then
write_addr <= next_read_addr - 1;
write_ram <= '1';
next_st_state <= IDLE;
set_st_state <= '1';
elsif read_req.req = '0' then -- wait in this state until request de-asserted
next_st_state <= IDLE;
set_st_state <= '1';
end if;
when NOT_FOUND =>
read_result_int.status <= read_status(NOT_FOUND, mode);
if mode = MWRITE then
-- need to write into the next free slot
write_addr <= next_write_addr;
write_ram <= '1';
set_next_write_addr <= INCR;
if num_entries < MAX_ARP_ENTRIES then
-- if not full, count another entry (if full, it just wraps)
set_num_entries <= INCR;
end if;
next_st_state <= IDLE;
set_st_state <= '1';
elsif read_req.req = '0' then -- wait in this state until request de-asserted
next_st_state <= IDLE;
set_st_state <= '1';
end if;
end case;
end process;
sequential : process (clk)
begin
if rising_edge(clk) then
-- ram processing
if write_ram = '1' then
ip_ram(write_addr) <= req_entry.ip;
mac_ram(write_addr) <= req_entry.mac;
end if;
if next_read_addr < MAX_ARP_ENTRIES then
arp_entry_val.ip <= ip_ram(next_read_addr);
arp_entry_val.mac <= mac_ram(next_read_addr);
else
arp_entry_val.ip <= (others => '0');
arp_entry_val.mac <= (others => '0');
end if;
read_result <= read_result_int;
if reset = '1' or clear_store = '1' then
-- reset state variables
st_state <= IDLE;
next_write_addr <= 0;
num_entries <= 0;
next_read_addr <= 0;
entry_found.ip <= (others => '0');
entry_found.mac <= (others => '0');
req_entry.ip <= (others => '0');
req_entry.mac <= (others => '0');
mode <= MREAD;
else
-- Next req_state processing
if set_st_state = '1' then
st_state <= next_st_state;
else
st_state <= st_state;
end if;
-- mode setting and write request latching
if set_mode = '1' then
mode <= mode_val;
if mode_val = MWRITE then
req_entry <= write_req.entry;
else
req_entry.ip <= read_req.ip;
req_entry.mac <= (others => '0');
end if;
else
mode <= mode;
req_entry <= req_entry;
end if;
-- latch entry found
if set_entry_found = '1' then
entry_found <= arp_entry_val;
else
entry_found <= entry_found;
end if;
-- next_write_addr counts and wraps
case set_next_write_addr is
when HOLD => next_write_addr <= next_write_addr;
when RST => next_write_addr <= 0;
when INCR => if next_write_addr < MAX_ARP_ENTRIES-1 then next_write_addr <= next_write_addr + 1; else next_write_addr <= 0; end if;
end case;
-- num_entries counts and holds at max
case set_num_entries is
when HOLD => num_entries <= num_entries;
when RST => num_entries <= 0;
when INCR => if next_write_addr < MAX_ARP_ENTRIES then num_entries <= num_entries + 1; else num_entries <= num_entries; end if;
end case;
-- next_read_addr counts and wraps
case set_next_read_addr is
when HOLD => next_read_addr <= next_read_addr;
when RST => next_read_addr <= 0;
when INCR => if next_read_addr < MAX_ARP_ENTRIES then next_read_addr <= next_read_addr + 1; else next_read_addr <= 0; end if;
end case;
end if;
end if;
end process;
end Behavioral;
|
bsd-2-clause
|
nihospr01/OpenSpeechPlatform-UCSD
|
Firmware/FPGA/src/r8_rising.vhd
|
1
|
595
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- 8-bit register, rising-edge triggered.
entity r8_rising is
port(
clk, reset: in std_logic;
ld: in std_logic;
din: in std_logic_vector(7 downto 0);
dout: out std_logic_vector(7 downto 0)
);
end entity;
architecture a of r8_rising is
signal reg: std_logic_vector(7 downto 0);
begin
process(clk, reset) is begin
if reset = '1' then
reg <= "00000000";
elsif rising_edge(clk) then
if ld = '1' then
reg <= din;
end if;
end if;
end process;
dout <= reg;
end architecture;
|
bsd-2-clause
|
athalonis/CCL-Verification-Environment
|
src/vhdl/sim_gmii.vhd
|
1
|
2658
|
--------------------------------------------------------------------------------
--Copyright (c) 2014, Benjamin Bässler <[email protected]>
--All rights reserved.
--
--Redistribution and use in source and binary forms, with or without
--modification, are permitted provided that the following conditions are met:
--
--* Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
--
--* Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
--
--THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
--IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
--DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
--FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
--DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
--SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
--CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
--OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
--OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--------------------------------------------------------------------------------
--! @file top_udp.vhd
--! @brief Top Module of Comparator Architecture with UDP
--! @author Benjamin Bässler
--! @email [email protected]
--! @date 2013-11-04
--------------------------------------------------------------------------------
--! Use standard library
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity sim_gmii is
port (
-- System signals
------------------
rst_in_n : in std_logic; -- asynchronous reset
clk_in : in std_logic;
-- GMII Interface
-----------------
gmii_txd : out std_logic_vector(7 downto 0);
gmii_tx_en : out std_logic;
gmii_tx_er : out std_logic;
gmii_tx_clk : out std_logic;
gmii_rxd : in std_logic_vector(7 downto 0);
gmii_rx_dv : in std_logic;
gmii_rx_er : in std_logic;
gmii_rx_clk : in std_logic;
gmii_col : in std_logic;
gmii_crs : in std_logic;
gmii_gtx_clk : out std_logic;
mii_tx_clk : in std_logic
);
end sim_gmii;
architecture sim_gmii_arc of sim_gmii is
begin
end sim_gmii_arc;
|
bsd-2-clause
|
athalonis/CCL-Verification-Environment
|
src/vhdl/stimgen.vhd
|
1
|
4731
|
--------------------------------------------------------------------------------
--Copyright (c) 2014, Benjamin Bässler <[email protected]>
--All rights reserved.
--
--Redistribution and use in source and binary forms, with or without
--modification, are permitted provided that the following conditions are met:
--
--* Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
--
--* Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
--
--THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
--IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
--DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
--FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
--DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
--SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
--CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
--OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
--OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--------------------------------------------------------------------------------
--! @file stimgen.vhd
--! @brief Generates Stimulies by using a counter
--! @author Benjamin Bässler
--! @email [email protected]
--! @date 2013-09-02
--------------------------------------------------------------------------------
--! Use standard library
library ieee;
--! Use numeric std
use IEEE.numeric_std.all;
use IEEE.std_logic_1164.all;
use IEEE.math_real.all;
use work.types.all;
use work.utils.all;
entity stimgen is
generic(
--! width of the input
G_INPUT_WIDTH : NATURAL := C_IMAGE_WIDTH * C_IMAGE_HEIGHT
);
port(
--! Clock input
clk_in : in STD_LOGIC;
--! Reset input
rst_in : in STD_LOGIC;
--! error_out valid
error_valid_out : out STD_LOGIC;
--! error valu
error_out : out STD_LOGIC_VECTOR(T_ERROR'range);
--! stimuli lead to error
stimuli_out : out STD_LOGIC_VECTOR(G_INPUT_WIDTH-1 downto 0);
--! how many stimulis are processed
--! this value has a error of G_COMP_INSTANCES
processed_out : out STD_LOGIC_VECTOR(G_INPUT_WIDTH-1 downto 0);
--! rises if check is done
check_done_out : out STD_LOGIC
);
end entity stimgen;
architecture stimgen_arc of stimgen is
CONSTANT C_MAX_STIM : UNSIGNED(G_INPUT_WIDTH-1 downto 0) := (others => '1');
Signal cnt_s : UNSIGNED(G_INPUT_WIDTH-1 downto 0);
Signal cnt_inc_s : STD_LOGIC;
Signal max_util_s : STD_LOGIC;
Signal idle_s : STD_LOGIC;
Signal stimuli_v_s : STD_LOGIC;
Signal stimuli_s : UNSIGNED(G_INPUT_WIDTH-1 downto 0);
Signal stimuli_out_s : UNSIGNED(G_INPUT_WIDTH-1 downto 0);
Signal error_out_s : T_ERROR;
begin
stimuli_out <= std_logic_vector(stimuli_out_s);
error_out <= std_logic_vector(error_out_s);
--! generate new stimuli if the verificator has not max utilization
--cnt_inc_s <= (not max_util_s) and (not rst_in);
check_done_out <= '1' when cnt_s = C_MAX_STIM and idle_s = '1' else '0';
--! this value has a error of G_COMP_INSTANCES
processed_out <= std_logic_vector(cnt_s);
--! assign the stimuli valid signal clock dependent
--! (the max_util_out dependt combinatorical on stimuli_v_in)
p_inc : process (clk_in) is
begin
if rising_edge(clk_in) then
stimuli_v_s <= '0';
cnt_inc_s <= '0';
if max_util_s = '0' and rst_in = '0' then
stimuli_v_s <= '1';
stimuli_s <= cnt_s;
cnt_inc_s <= '1';
end if;
end if;
end process p_inc;
verificator : entity work.verificator
PORT MAP(
clk_in => clk_in,
rst_in => rst_in,
stimuli_v_in => stimuli_v_s,
stimuli_in => stimuli_s,
error_valid_out => error_valid_out,
error_out => error_out_s,
stimuli_out => stimuli_out_s,
run_in => '1',
max_util_out => max_util_s,
idle_out => idle_s
);
counter : entity work.counter GENERIC MAP(
G_CNT_LENGTH => G_INPUT_WIDTH,
G_INC_VALUE => 1,
G_OFFSET => to_unsigned(1, 64) --to_unsigned(21, 64)
--G_OFFSET => x"0000000700F73906" --there should be dragons
)
PORT MAP(
clk_in => clk_in,
rst_in => rst_in,
inc_in => cnt_inc_s,
cnt_out => cnt_s
);
end architecture stimgen_arc;
|
bsd-2-clause
|
athalonis/CCL-Verification-Environment
|
src/vhdl/cam_control_unit.vhd
|
1
|
22640
|
--------------------------------------------------------------------------------
--Copyright (c) 2014, Benjamin Bässler <[email protected]>
--All rights reserved.
--
--Redistribution and use in source and binary forms, with or without
--modification, are permitted provided that the following conditions are met:
--
--* Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
--
--* Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
--
--THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
--IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
--DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
--FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
--DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
--SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
--CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
--OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
--OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--------------------------------------------------------------------------------
--! @file cam_control_unit.vhd
--! @brief Control Unit for the camera interface
--! @author Benjamin Bässler
--! @email [email protected]
--! @date 2014-04-25
--------------------------------------------------------------------------------
--! Use standard library
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.types.all;
use work.utils.all;
library pccl_lib;
use pccl_lib.common.all;
entity cam_control_unit is
generic(
G_MAX_DATA_SIZE : natural := C_MAX_SEND_DATA;
--! Number of Comparators
G_COMP_INST : NATURAL := C_COMP_INST;
--! Image width
-- value from ccl_dut common.vhd
G_IMG_WIDTH : NATURAL := C_IMAGE_WIDTH;
--! Image height
-- value from ccl_dut common.vhd
G_IMG_HEIGHT : NATURAL := C_IMAGE_HEIGHT;
--! Error Storage
G_ERR_SIZE : NATURAL := C_ERR_BUF_SIZE
);
port (
-- System signals
------------------
rst_in : in std_logic; -- asynchronous reset
rx_clk_in : in std_logic;
clk_dut_in : in std_logic;
-- Decoded data
-- read/write command
dec_valid_in : in std_logic;
write_in : in std_logic;
type_in : in unsigned(15 downto 0);
id_in : in unsigned(15 downto 0);
length_in : in unsigned(15 downto 0);
data_in : in unsigned(G_MAX_DATA_SIZE - 1 downto 0);
header_error_in : in std_logic;
-- Encoder data
enc_valid_out : out std_logic;
type_out : out unsigned(15 downto 0);
id_out : out unsigned(15 downto 0);
length_out : out unsigned(15 downto 0);
data_out : out unsigned(G_MAX_DATA_SIZE - 1 downto 0);
run_out : out std_logic
);
end cam_control_unit;
architecture cam_control_unit_arc of cam_control_unit is
CONSTANT C_RESTART_WAIT : natural := 3;
CONSTANT C_STIM_SIZE : natural := G_IMG_WIDTH*G_IMG_HEIGHT;
CONSTANT C_STIM_SIZE_BYTE : natural := div_ceil(C_STIM_SIZE, 8);
CONSTANT C_BOX_SIZE : natural := 2*(log2_ceil(G_IMG_WIDTH)+log2_ceil(G_IMG_HEIGHT));
--log2_ceil(C_MAX_IMAGE_HEIGHT)+1+log2_ceil(C_MAX_IMAGE_WIDTH)+1
CONSTANT C_BOX_SIZE_BYTE : natural := div_ceil(C_BOX_SIZE, 8);
CONSTANT C_ERR_FIFO_WIDTH : natural := 6;
CONSTANT C_ERR_FI_LV_SIZE : natural := log2_ceil(G_ERR_SIZE)+1;
CONSTANT C_ERR_FI_LV_BYTE : natural := div_ceil(C_ERR_FI_LV_SIZE, 8);
--! length of error injection package
CONSTANT C_ERR_PKG_LEN : natural := div_ceil(T_CAM_ERR'length * (log2_ceil(C_MAX_IMAGE_HEIGHT+1)+log2_ceil(C_MAX_IMAGE_WIDTH+1)+1),8);
CONSTANT C_TYP_ACK : unsigned(15 downto 0) := x"0001";
CONSTANT C_TYP_NACK : unsigned(15 downto 0) := x"0002";
CONSTANT C_TYP_HW_CFG : unsigned(15 downto 0) := x"0003";
CONSTANT C_TYP_STATUS : unsigned(15 downto 0) := x"0004";
CONSTANT C_TYP_RESET : unsigned(15 downto 0) := x"0007";
CONSTANT C_TYP_SEND_PX : unsigned(15 downto 0) := x"000E";
CONSTANT C_TYP_SEND_BOX : unsigned(15 downto 0) := x"000F";
CONSTANT C_TYP_SET_FLL_LVL : unsigned(15 downto 0) := x"0010";
CONSTANT C_TYP_SET_ACT_ERR : unsigned(15 downto 0) := x"0011";
CONSTANT C_TYP_SET_HSY_ERR : unsigned(15 downto 0) := x"0012";
CONSTANT C_TYP_SET_VSY_ERR : unsigned(15 downto 0) := x"0013";
type T_RX_STATE is (NOP, ACK, NACK, HEAD_ERR, HW_CFG, STATUS,
RESET, SEND_PX, SET_FLL_LVL,
SET_ACT_ERR, SET_HSY_ERR, SET_VSY_ERR, SEND_OUT,
SEND_OUT_LAST, UNKNOWN);
signal rx_state_s : T_RX_STATE;
--! verifier state
type T_INT_STATE is (RESTART, PROCESSING, DONE);
signal int_state_s : T_INT_STATE;
--! internal signals
signal rst_exec_s : std_logic := '0';
signal rst_prepare_s : std_logic := '0';
signal restart_cnt_s : unsigned(log2_ceil(C_RESTART_WAIT+1)-1 downto 0);
--! camif signals
Signal cam_rst_s : STD_LOGIC;
Signal cam_min_fll_lvl_s : UNSIGNED(15 downto 0);
Signal cam_di_s : UNSIGNED(G_MAX_DATA_SIZE+16 - 1 downto 0);
Signal cam_di_vl_s : STD_LOGIC;
Signal cam_di_ry_s : STD_LOGIC;
Signal cam_do_s : UNSIGNED(63 downto 0);
Signal cam_do_ry_s : STD_LOGIC;
Signal cam_do_vl_s : STD_LOGIC;
Signal cam_err_s : UNSIGNED(5 downto 0);
Signal cam_done_s : STD_LOGIC;
--! Error injection registers
signal active_err_s : T_CAM_ERR;
signal hsync_err_s : T_CAM_ERR;
signal vsync_err_s : T_CAM_ERR;
--! Signals for output fifo
signal out_fifo_rst_s : STD_LOGIC;
signal out_fifo_full_s : STD_LOGIC;
signal out_fifo_fill_s : UNSIGNED(6 downto 0);
signal out_fifo_di_s : UNSIGNED(63 downto 0) := (others => '0');
signal out_fifo_do_s : UNSIGNED(1023 downto 0);
signal out_fifo_do_vl_s : STD_LOGIC;
signal out_fifo_ack_s : STD_LOGIC;
--! Is the output fifo flushed?
signal out_fifo_flu_s : STD_LOGIC;
signal pkg_cnt_s : unsigned(id_out'range);
procedure str_unsigned
(str : string;
signal data : out unsigned;
signal data_valid : out unsigned) is
begin
for i in str'range loop
data(data'high-(i-1)*8 downto data'high-(i-1)*8-7) <=
to_unsigned(character'pos(str(i)), 8);
end loop;
data_valid <= to_unsigned(str'length, data_valid'length);
end procedure str_unsigned;
procedure hw_cfg_status(
signal hw_cfg_out : out unsigned(G_MAX_DATA_SIZE-1 downto 0);
signal hw_cfg_len_out : out unsigned(15 downto 0);
instances : in natural)
is
variable hw_cfg : unsigned(G_MAX_DATA_SIZE-1 downto 0);
variable hw_cfg_len : natural := 0;
variable pos : natural := G_MAX_DATA_SIZE-1;
variable tmp : natural;
begin
--HW-Version (4 Bytes -> hg revision)
hw_cfg(pos downto pos - (4*8-1)) := to_unsigned(C_VERSION, 4*8);
hw_cfg_len := hw_cfg_len + 4;
pos := G_MAX_DATA_SIZE-1 - hw_cfg_len*8;
-- MAX_DATA_LENGTH (2 Bytes)
hw_cfg(pos downto pos - (2*8-1)) := to_unsigned(G_MAX_DATA_SIZE, 2*8);
hw_cfg_len := hw_cfg_len + 2;
pos := G_MAX_DATA_SIZE-1 - hw_cfg_len*8;
--length of max img_width (1 byte)
tmp := div_ceil(log2_ceil(G_IMG_WIDTH), 8);
hw_cfg(pos downto pos - (1*8-1)) := to_unsigned(tmp, 1*8);
hw_cfg_len := hw_cfg_len + 1;
pos := G_MAX_DATA_SIZE-1 - hw_cfg_len*8;
-- max img_width
hw_cfg(pos downto pos - (tmp*8-1)) := to_unsigned(C_MAX_IMAGE_WIDTH, tmp*8);
hw_cfg_len := hw_cfg_len + tmp;
pos := G_MAX_DATA_SIZE-1 - hw_cfg_len*8;
-- img_width
hw_cfg(pos downto pos - (tmp*8-1)) := to_unsigned(C_IMAGE_WIDTH, tmp*8);
hw_cfg_len := hw_cfg_len + tmp;
pos := G_MAX_DATA_SIZE-1 - hw_cfg_len*8;
--length of max img_height (1 byte)
tmp := div_ceil(log2_ceil(C_MAX_IMAGE_HEIGHT), 8);
hw_cfg(pos downto pos - (1*8-1)) := to_unsigned(tmp, 1*8);
hw_cfg_len := hw_cfg_len + 1;
pos := G_MAX_DATA_SIZE-1 - hw_cfg_len*8;
--max img_height
hw_cfg(pos downto pos - (tmp*8-1)) := to_unsigned(C_MAX_IMAGE_HEIGHT, tmp*8);
hw_cfg_len := hw_cfg_len + tmp;
pos := G_MAX_DATA_SIZE-1 - hw_cfg_len*8;
--img_height
hw_cfg(pos downto pos - (tmp*8-1)) := to_unsigned(C_IMAGE_HEIGHT, tmp*8);
hw_cfg_len := hw_cfg_len + tmp;
pos := G_MAX_DATA_SIZE-1 - hw_cfg_len*8;
--length of box_size (1 byte)
tmp := div_ceil(log2_ceil(log2_ceil(C_MAX_IMAGE_HEIGHT)+1+log2_ceil(C_MAX_IMAGE_WIDTH)+1), 8);
hw_cfg(pos downto pos - (1*8-1)) := to_unsigned(tmp, 1*8);
hw_cfg_len := hw_cfg_len + 1;
pos := G_MAX_DATA_SIZE-1 - hw_cfg_len*8;
--box_size
hw_cfg(pos downto pos - (tmp*8-1)) := to_unsigned(log2_ceil(C_MAX_IMAGE_HEIGHT)+1+log2_ceil(C_MAX_IMAGE_WIDTH)+1, tmp*8);
hw_cfg_len := hw_cfg_len + tmp;
pos := G_MAX_DATA_SIZE-1 - hw_cfg_len*8;
--length of stimuli_length (log2(stimuli length))
--tmp := div_ceil(log2_ceil(2*C_MAX_IMAGE_HEIGHT * 2*C_MAX_IMAGE_WIDTH), 8);
tmp := 1;
hw_cfg(pos downto pos - (1*8-1)) := to_unsigned(tmp, 1*8);
hw_cfg_len := hw_cfg_len + 1;
pos := G_MAX_DATA_SIZE-1 - hw_cfg_len*8;
--stimuli_length
--hw_cfg(pos downto pos - (tmp*8-1)) := to_unsigned(2**C_MAX_IMAGE_HEIGHT * 2**C_MAX_IMAGE_WIDTH, tmp*8);
hw_cfg(pos downto pos - (tmp*8-1)) := to_unsigned(0, tmp*8);
hw_cfg_len := hw_cfg_len + tmp;
pos := G_MAX_DATA_SIZE-1 - hw_cfg_len*8;
--length of instances (ceil(log2(instances)))
tmp := div_ceil(log2_ceil(1), 8);
hw_cfg(pos downto pos - (1*8-1)) := to_unsigned(tmp, 1*8);
hw_cfg_len := hw_cfg_len + 1;
pos := G_MAX_DATA_SIZE-1 - hw_cfg_len*8;
-- instances
hw_cfg(pos downto pos - (tmp*8-1)) := to_unsigned(0, tmp*8);
hw_cfg_len := hw_cfg_len + tmp;
pos := G_MAX_DATA_SIZE-1 - hw_cfg_len*8;
-- comparator error_type length
hw_cfg(pos downto pos - (8-1)) := to_unsigned(cam_err_s'high-cam_err_s'low+1, 8);
hw_cfg_len := hw_cfg_len + 1;
pos := G_MAX_DATA_SIZE-1 - hw_cfg_len*8;
-- rev error_type length
hw_cfg(pos downto pos - (8-1)) := to_unsigned(0, 8);
hw_cfg_len := hw_cfg_len + 1;
pos := G_MAX_DATA_SIZE-1 - hw_cfg_len*8;
-- dut error_type length
hw_cfg(pos downto pos - (8-1)) := to_unsigned(0, 8);
hw_cfg_len := hw_cfg_len + 1;
pos := G_MAX_DATA_SIZE-1 - hw_cfg_len*8;
-- magic number for camera simulation mode
hw_cfg(pos downto pos - (8-1)) := to_unsigned(42, 8);
hw_cfg_len := hw_cfg_len + 1;
pos := G_MAX_DATA_SIZE-1 - hw_cfg_len*8;
-- T_CAM_ERR_ARY_LENGTH
hw_cfg(pos downto pos - (8-1)) := to_unsigned(T_CAM_ERR'length, 8);
hw_cfg_len := hw_cfg_len + 1;
pos := G_MAX_DATA_SIZE-1 - hw_cfg_len*8;
hw_cfg_len_out <= to_unsigned(hw_cfg_len, 2*8);
hw_cfg_out <= hw_cfg;
end procedure hw_cfg_status;
procedure read_err(
signal length_in : in unsigned(15 downto 0);
signal data_in : in unsigned(G_MAX_DATA_SIZE - 1 downto 0);
signal err_s : out T_CAM_ERR)
is
constant c_word_len : natural := (err_s(0).row'length + err_s(0).col'length + 1);
begin
-- data vector:
-- row size: log2_ceil(C_MAX_IMAGE_HEIGHT+1)
-- col size: log2_ceil(C_MAX_IMAGE_WIDTH+1)
-- data size: 1bit
-- | row(0), col(0), data(0) | row(1), col(1), data(1) | ...
for i in err_s'range loop
err_s(i).row <= data_in(
data_in'high - i*c_word_len downto
data_in'high - i*c_word_len - err_s(0).row'length +1);
err_s(i).col <= data_in(
data_in'high - i*c_word_len - err_s(0).row'length downto
data_in'high - i*c_word_len
- err_s(0).row'length - err_s(0).col'length +1);
err_s(i).val <= data_in(
data_in'high - i*c_word_len
- err_s(0).row'length - err_s(0).col'length);
end loop;
end procedure read_err;
begin
run_out <= '1' when int_state_s = PROCESSING else '0';
--! @brief This process generates the states of the incoming commands
p_rx_decode : process (rst_in, rx_clk_in) is
variable tmp : natural;
begin
if rst_in = '1' then
rx_state_s <= NOP;
cam_min_fll_lvl_s <= to_unsigned(1, cam_min_fll_lvl_s'length);
active_err_s <= (others => (row => (others => '1'), col => (others => '1'), val => '0'));
hsync_err_s <= (others => (row => (others => '1'), col => (others => '1'), val => '0'));
vsync_err_s <= (others => (row => (others => '1'), col => (others => '1'), val => '0'));
pkg_cnt_s <= (others => '0');
out_fifo_flu_s <= '0';
elsif rising_edge(rx_clk_in) then
rx_state_s <= NOP;
if int_state_s = DONE and out_fifo_fill_s*64/8 < G_MAX_DATA_SIZE/8 and
out_fifo_fill_s > 0 and out_fifo_flu_s = '0'
then
rx_state_s <= SEND_OUT_LAST;
out_fifo_flu_s<= '1';
elsif out_fifo_do_vl_s = '1' then
rx_state_s <= SEND_OUT;
pkg_cnt_s <= pkg_cnt_s + 1;
end if;
cam_di_vl_s <= '0';
if dec_valid_in = '1' then
--! default
if header_error_in = '1' then
rx_state_s <= HEAD_ERR;
else
case type_in is
when C_TYP_ACK =>
rx_state_s <= ACK;
when C_TYP_NACK =>
rx_state_s <= NACK;
when C_TYP_HW_CFG =>
rx_state_s <= HW_CFG;
when C_TYP_STATUS =>
rx_state_s <= STATUS;
when C_TYP_RESET =>
rx_state_s <= RESET;
when C_TYP_SEND_PX =>
rx_state_s <= SEND_PX;
out_fifo_flu_s <= '0';
if cam_di_ry_s = '1' then
cam_di_s <= length_in & data_in(data_in'high downto data_in'high+1-G_MAX_DATA_SIZE);
cam_di_vl_s <= '1';
end if;
when C_TYP_SET_FLL_LVL =>
rx_state_s <= SET_FLL_LVL;
cam_min_fll_lvl_s <= data_in(data_in'high downto data_in'high-15);
when C_TYP_SET_ACT_ERR =>
rx_state_s <= SET_ACT_ERR;
if length_in = C_ERR_PKG_LEN then
read_err(length_in, data_in, active_err_s);
end if;
when C_TYP_SET_HSY_ERR =>
rx_state_s <= SET_HSY_ERR;
if length_in = C_ERR_PKG_LEN then
read_err(length_in, data_in, hsync_err_s);
end if;
when C_TYP_SET_VSY_ERR =>
rx_state_s <= SET_VSY_ERR;
if length_in = C_ERR_PKG_LEN then
read_err(length_in, data_in, vsync_err_s);
end if;
when others =>
rx_state_s <= UNKNOWN;
end case;
end if; --header_error
end if; -- dec_valid
end if; --rst/clk
end process p_rx_decode;
--! @brief This process generates the answers on rx messages according to
--! udp_protocol.txt
p_tx_answer : process (
rst_in, rx_state_s, id_in, int_state_s, length_in, cam_di_ry_s,
out_fifo_fill_s, pkg_cnt_s, out_fifo_do_s
) is
variable tmp : natural;
begin
if rst_in = '1' then
--reset
rst_prepare_s <= '0';
type_out <= (others => '-');
id_out <= (others => '-');
length_out <= (others => '0');
data_out <= (others => '-');
enc_valid_out <= '0';
out_fifo_ack_s <= '0';
else
-- default values
enc_valid_out <= '0';
type_out <= (others => '-');
id_out <= (others => '-');
length_out <= (others => '0');
data_out <= (others => '-');
rst_prepare_s <= '0';
out_fifo_ack_s <= '0';
case rx_state_s is
when NOP =>
null;
when SEND_OUT_LAST =>
--image processed completed flushing buffer
--the C_TYP_SEND_BOX uses the length_out as number of valid bits
--instead of bytes
enc_valid_out <= '1';
type_out <= C_TYP_SEND_BOX;
id_out <= pkg_cnt_s;
length_out <= resize(out_fifo_fill_s*64/8, length_out'length);
data_out <= out_fifo_do_s;
when SEND_OUT =>
--enough data stored to fill one complet package
enc_valid_out <= '1';
type_out <= C_TYP_SEND_BOX;
id_out <= pkg_cnt_s;
length_out <= to_unsigned(G_MAX_DATA_SIZE/8, length_out'length);
data_out <= out_fifo_do_s;
out_fifo_ack_s <= '1';
when ACK =>
-- This case is ignored
-- TODO: implement send queue. The queue stores all send commands
-- until a ACK for this id is received. After a timeout do resend
null;
when NACK =>
-- Ignore NACK
-- TODO: remove from queue or resend
null;
when HEAD_ERR =>
enc_valid_out <= '1';
type_out <= C_TYP_NACK;
id_out <= id_in;
str_unsigned("corrupt header", data_out, length_out);
--length_out <= x"0e";
--data_out(G_MAX_DATA_SIZE-1 downto G_MAX_DATA_SIZE-(14*8))
--<= x"636f727275707420686561646572"; --corrupt header in ASCII
when HW_CFG =>
enc_valid_out <= '1';
type_out <= C_TYP_ACK;
id_out <= id_in;
hw_cfg_status(data_out, length_out, G_COMP_INST);
when STATUS =>
enc_valid_out <= '1';
type_out <= C_TYP_ACK;
id_out <= id_in;
--constant tmp
length_out <= to_unsigned(1, 16);
case int_state_s is
when RESTART =>
data_out (G_MAX_DATA_SIZE-1 downto G_MAX_DATA_SIZE-(1*8))
<= x"80";
when PROCESSING =>
data_out (G_MAX_DATA_SIZE-1 downto G_MAX_DATA_SIZE-(1*8))
<= x"81";
when DONE =>
data_out (G_MAX_DATA_SIZE-1 downto G_MAX_DATA_SIZE-(1*8))
<= x"82";
end case;
--add stimuli with alignment to the lsb
tmp := data_out'high-8+1;
when RESET =>
rst_prepare_s <= '1';
enc_valid_out <= '1';
type_out <= C_TYP_ACK;
id_out <= id_in;
when SEND_PX =>
enc_valid_out <= '1';
id_out <= id_in;
if cam_di_ry_s = '1' then
type_out <= C_TYP_ACK;
else
type_out <= C_TYP_NACK;
str_unsigned("fifo full", data_out, length_out);
end if;
when SET_FLL_LVL =>
enc_valid_out <= '1';
id_out <= id_in;
type_out <= C_TYP_ACK;
when SET_ACT_ERR =>
enc_valid_out <= '1';
id_out <= id_in;
if length_in = C_ERR_PKG_LEN then
type_out <= C_TYP_ACK;
else
type_out <= C_TYP_NACK;
end if;
when SET_HSY_ERR =>
enc_valid_out <= '1';
id_out <= id_in;
if length_in = C_ERR_PKG_LEN then
type_out <= C_TYP_ACK;
else
type_out <= C_TYP_NACK;
end if;
when SET_VSY_ERR =>
enc_valid_out <= '1';
id_out <= id_in;
if length_in = C_ERR_PKG_LEN then
type_out <= C_TYP_ACK;
else
type_out <= C_TYP_NACK;
end if;
when UNKNOWN =>
enc_valid_out <= '1';
id_out <= id_in;
type_out <= C_TYP_NACK;
str_unsigned("cmd unknown", data_out, length_out);
--when others =>
-- enc_valid_out <= '1';
-- id_out <= id_in;
-- type_out <= C_TYP_NACK;
-- str_unsigned("unexpected", data_out, length_out);
end case;
end if; --rst
end process p_tx_answer;
--! Statemachine for internal state
--! States:
--! IDLE just resetted nothing to do
--! RESTART do a restart of camif
--! PROCESSING pixel receive in progress
--! DONE image processed
p_int_state : process (rst_in, rx_clk_in) is
begin
if rst_in = '1' then
int_state_s <= RESTART;
rst_exec_s <= '0';
restart_cnt_s <= to_unsigned(C_RESTART_WAIT, restart_cnt_s'length);
elsif rising_edge(rx_clk_in) then
--! default Values
if rst_prepare_s = '1' then
rst_exec_s <= '1';
end if;
case int_state_s is
when RESTART =>
rst_exec_s <= '0';
restart_cnt_s <= restart_cnt_s - 1;
-- restart wait at least C_RESTART_WAIT clock cycles
-- and set reset signals
if restart_cnt_s = 0 then
int_state_s <= PROCESSING;
restart_cnt_s <= to_unsigned(C_RESTART_WAIT, restart_cnt_s'length);
end if;
when PROCESSING =>
if cam_done_s = '1' then
int_state_s <= DONE;
end if;
if rst_exec_s = '1' then
int_state_s <= RESTART;
end if;
when DONE =>
if rst_exec_s = '1' then
int_state_s <= RESTART;
end if;
end case;
end if;
end process p_int_state;
--! @brief Process for controling internal signals
p_ctrl : process (int_state_s, rst_in) is
begin
--default values
cam_rst_s <= '0';
out_fifo_rst_s <= '0';
if rst_in = '1' then
cam_rst_s <= '1';
else
case int_state_s is
when RESTART =>
-- reset the counter and the verifier
cam_rst_s <= '1';
out_fifo_rst_s <= '1';
when PROCESSING =>
null;
when DONE =>
null;
end case;
end if;
end process p_ctrl;
-- send ready to data_out of camif if fifo has space to store value
cam_do_ry_s <= not out_fifo_full_s;
out_fifo_di_s <= cam_do_s;
out_fifo: entity work.box_out_storage
port map(
rst_in => out_fifo_rst_s,
clk_in => rx_clk_in,
full_out => out_fifo_full_s,
fill_lvl_out => out_fifo_fill_s,
data_in => out_fifo_di_s,
data_vl_in => cam_do_vl_s,
data_out => out_fifo_do_s,
data_vl_out => out_fifo_do_vl_s,
data_ack_in => out_fifo_ack_s
);
camif : entity work.camif
generic map(
--! Image width
-- value from ccl_dut common.vhd
G_IMG_WIDTH => C_IMAGE_WIDTH,
--! Image height
-- value from ccl_dut common.vhd
G_IMG_HEIGHT => C_IMAGE_HEIGHT,
--! Number of parallel pixels
G_NO_PX => no_pixels,
--! Input width in bits
G_IN_WIDTH => G_MAX_DATA_SIZE,
G_FIFO_SIZE => 256
)
port map(
clk_in => rx_clk_in,
clk_cam_in => clk_dut_in,
rst_in => cam_rst_s,
min_fll_lvl_in => cam_min_fll_lvl_s,
-- input of image data
-- 16 MSB bits are used to save the number of valid pixels
-- only the last package of pixels can be smaller than 1024
data_in => cam_di_s, --: in UNSIGNED(G_IN_WIDTH+16 - 1 downto 0);
data_vl_in => cam_di_vl_s, -- : in STD_LOGIC;
data_in_rdy_out => cam_di_ry_s,
--! output data out
data_out => cam_do_s,
data_rdy_in => cam_do_ry_s,
data_vl_out => cam_do_vl_s,
--! error value
error_out => cam_err_s,
--! high if image processing is completed
done_out => cam_done_s,
--vsync error injection
vsync_err_in => vsync_err_s,
--hsync error injection
hsync_err_in => hsync_err_s,
--px active error injection
-- if value = 1 inserts a additional pixel before the given coordinate
-- if value = 0 forces the active signal to zero for the given coordinate
active_err_in => active_err_s
);
end architecture cam_control_unit_arc;
|
bsd-2-clause
|
athalonis/CCL-Verification-Environment
|
src/vhdl/tb_xilinx_mac.vhd
|
1
|
133905
|
------------------------------------------------------------------------
-- Title : GMII Testbench
-- Project : Xilinx LogiCORE Virtex-6 Embedded Tri-Mode Ethernet MAC
-- File : phy_tb.vhd
-- Version : 2.2
-------------------------------------------------------------------------------
--
-- (c) Copyright 2004-2008 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------
-- Description: This testbench will exercise the PHY ports of the EMAC
-- to demonstrate the functionality.
------------------------------------------------------------------------
--
-- This testbench performs the following operations on the EMAC
-- and its design example:
-- - Four frames are pushed into the receiver from the PHY
-- interface (GMII/MII):
-- The first is of minimum length (Length/Type = Length = 46 bytes).
-- The second frame sets Length/Type to Type = 0x8000.
-- The third frame has an error inserted.
-- The fourth frame only sends 4 bytes of data: the remainder of the
-- data field is padded up to the minimum frame length i.e. 46 bytes.
-- - These frames are then parsed from the MAC into the MAC's design
-- example. The design example provides a MAC client loopback
-- function so that frames which are received without error will be
-- looped back to the MAC transmitter and transmitted back to the
-- testbench. The testbench verifies that this data matches that
-- previously injected into the receiver.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb_xilinx_mac is
port(
------------------------------------------------------------------
-- GMII Interface
------------------------------------------------------------------
gmii_txd : in std_logic_vector(7 downto 0);
gmii_tx_en : in std_logic;
gmii_tx_er : in std_logic;
gmii_tx_clk : in std_logic;
gmii_rxd : out std_logic_vector(7 downto 0);
gmii_rx_dv : out std_logic;
gmii_rx_er : out std_logic;
gmii_rx_clk : out std_logic;
gmii_col : out std_logic;
gmii_crs : out std_logic;
mii_tx_clk : out std_logic;
------------------------------------------------------------------
-- Test Bench Semaphores
------------------------------------------------------------------
configuration_busy : in boolean;
monitor_finished_1g : out boolean;
monitor_finished_100m : out boolean;
monitor_finished_10m : out boolean
);
end tb_xilinx_mac;
architecture behavioral of tb_xilinx_mac is
-- run first 0 .. C_PAUSE_AFTER_FRAME frames then pause for C_PAUSE_CYCLES
constant C_PAUSE_AFTER_FRAME : Natural := 12;
constant C_PAUSE2_AFTER_FRAME : Natural := C_PAUSE_AFTER_FRAME + 7;
constant C_PAUSE3_AFTER_FRAME : Natural := C_PAUSE2_AFTER_FRAME + 1;
constant C_PAUSE_CYCLES : Natural := 1800;
constant C_PAUSE2_CYCLES : Natural := 2800;
constant C_PAUSE3_CYCLES : Natural := 29800;
----------------------------------------------------------------------
-- Types to support frame data
----------------------------------------------------------------------
-- Tx Data and Data_valid record
type data_typ is record
data : bit_vector(7 downto 0); -- data
valid : bit; -- data_valid
error : bit; -- data_error
end record;
type frame_of_data_typ is array (natural range <>) of data_typ;
-- Tx Data, Data_valid and underrun record
type frame_typ is record
columns : frame_of_data_typ(0 to 65);-- data field
bad_frame : boolean; -- does this frame contain an error?
end record;
type frame_typ_ary is array (natural range <>) of frame_typ;
----------------------------------------------------------------------
-- Stimulus - Frame data
----------------------------------------------------------------------
-- The following constant holds the stimulus for the testbench. It is
-- an ordered array of frames, with frame 0 the first to be injected
-- into the core receiver PHY interface by the testbench.
----------------------------------------------------------------------
constant frame_data : frame_typ_ary := (
-------------
-- Frame 0
-- Send an ARP request: who has 192.168.5.9? Tell 192.168.5.1
-------------
0 => (
columns => (
0 => ( DATA => x"ff", VALID => '1', ERROR => '0'), --dest adr
1 => ( DATA => x"ff", VALID => '1', ERROR => '0'),
2 => ( DATA => x"ff", VALID => '1', ERROR => '0'),
3 => ( DATA => x"ff", VALID => '1', ERROR => '0'),
4 => ( DATA => x"ff", VALID => '1', ERROR => '0'),
5 => ( DATA => x"ff", VALID => '1', ERROR => '0'),
6 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- src adr
7 => ( DATA => x"23", VALID => '1', ERROR => '0'),
8 => ( DATA => x"18", VALID => '1', ERROR => '0'),
9 => ( DATA => x"29", VALID => '1', ERROR => '0'),
10 => ( DATA => x"26", VALID => '1', ERROR => '0'),
11 => ( DATA => x"7c", VALID => '1', ERROR => '0'),
12 => ( DATA => x"08", VALID => '1', ERROR => '0'), -- type 0806 arp
13 => ( DATA => x"06", VALID => '1', ERROR => '0'),
14 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- hw adr type
15 => ( DATA => x"01", VALID => '1', ERROR => '0'),
16 => ( DATA => x"08", VALID => '1', ERROR => '0'), -- proto type
17 => ( DATA => x"00", VALID => '1', ERROR => '0'),
18 => ( DATA => x"06", VALID => '1', ERROR => '0'), -- MAC size
19 => ( DATA => x"04", VALID => '1', ERROR => '0'), -- IP size
20 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- arp req
21 => ( DATA => x"01", VALID => '1', ERROR => '0'),
22 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- src mac
23 => ( DATA => x"23", VALID => '1', ERROR => '0'),
24 => ( DATA => x"18", VALID => '1', ERROR => '0'),
25 => ( DATA => x"29", VALID => '1', ERROR => '0'),
26 => ( DATA => x"26", VALID => '1', ERROR => '0'),
27 => ( DATA => x"7c", VALID => '1', ERROR => '0'),
28 => ( DATA => x"c0", VALID => '1', ERROR => '0'), --src ip
29 => ( DATA => x"a8", VALID => '1', ERROR => '0'),
30 => ( DATA => x"05", VALID => '1', ERROR => '0'),
31 => ( DATA => x"01", VALID => '1', ERROR => '0'),
32 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- dest mac
33 => ( DATA => x"00", VALID => '1', ERROR => '0'),
34 => ( DATA => x"00", VALID => '1', ERROR => '0'),
35 => ( DATA => x"00", VALID => '1', ERROR => '0'),
36 => ( DATA => x"00", VALID => '1', ERROR => '0'),
37 => ( DATA => x"00", VALID => '1', ERROR => '0'),
38 => ( DATA => x"c0", VALID => '1', ERROR => '0'), -- dest ip
39 => ( DATA => x"a8", VALID => '1', ERROR => '0'),
40 => ( DATA => x"04", VALID => '1', ERROR => '0'),
41 => ( DATA => x"17", VALID => '1', ERROR => '0'),
42 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
43 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
44 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
45 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
46 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
47 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
48 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
49 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
50 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
51 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
52 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
53 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
54 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
55 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
56 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
57 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
58 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
59 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
others => ( DATA => x"00", VALID => '0', ERROR => '0')),
-- No error in this frame
bad_frame => false),
-------------
-- Frame 1
-- Send read HW_CFG with malformed header
-------------
1 => (
columns => (
0 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Dest Adr
1 => ( DATA => x"23", VALID => '1', ERROR => '0'),
2 => ( DATA => x"20", VALID => '1', ERROR => '0'),
3 => ( DATA => x"21", VALID => '1', ERROR => '0'),
4 => ( DATA => x"22", VALID => '1', ERROR => '0'),
5 => ( DATA => x"23", VALID => '1', ERROR => '0'),
6 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Source Address
7 => ( DATA => x"23", VALID => '1', ERROR => '0'),
8 => ( DATA => x"18", VALID => '1', ERROR => '0'),
9 => ( DATA => x"29", VALID => '1', ERROR => '0'),
10 => ( DATA => x"26", VALID => '1', ERROR => '0'),
11 => ( DATA => x"7c", VALID => '1', ERROR => '0'),
12 => ( DATA => x"08", VALID => '1', ERROR => '0'), --type 0800 IP
13 => ( DATA => x"00", VALID => '1', ERROR => '0'),
14 => ( DATA => x"45", VALID => '1', ERROR => '0'), -- IP HEADER
15 => ( DATA => x"00", VALID => '1', ERROR => '0'),
16 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- LENGTH
17 => ( DATA => x"21", VALID => '1', ERROR => '0'), -- LENGTH
18 => ( DATA => x"00", VALID => '1', ERROR => '0'),
19 => ( DATA => x"7a", VALID => '1', ERROR => '0'),
20 => ( DATA => x"00", VALID => '1', ERROR => '0'),
21 => ( DATA => x"00", VALID => '1', ERROR => '0'),
22 => ( DATA => x"80", VALID => '1', ERROR => '0'),
23 => ( DATA => x"11", VALID => '1', ERROR => '0'), -- Proto: UDP
24 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- IP HEADER CS
25 => ( DATA => x"00", VALID => '1', ERROR => '0'),
26 => ( DATA => x"c0", VALID => '1', ERROR => '0'), -- SRC IP
27 => ( DATA => x"a8", VALID => '1', ERROR => '0'),
28 => ( DATA => x"05", VALID => '1', ERROR => '0'),
29 => ( DATA => x"01", VALID => '1', ERROR => '0'),
30 => ( DATA => x"c0", VALID => '1', ERROR => '0'), -- DEST IP
31 => ( DATA => x"a8", VALID => '1', ERROR => '0'),
32 => ( DATA => x"04", VALID => '1', ERROR => '0'),
33 => ( DATA => x"17", VALID => '1', ERROR => '0'),
34 => ( DATA => x"f4", VALID => '1', ERROR => '0'), -- SRC PORT
35 => ( DATA => x"9a", VALID => '1', ERROR => '0'),
36 => ( DATA => x"D8", VALID => '1', ERROR => '0'), -- DST PORT
37 => ( DATA => x"20", VALID => '1', ERROR => '0'),
38 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- LENGTH
39 => ( DATA => x"0e", VALID => '1', ERROR => '0'), -- LENGTH
40 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- UDP CS
41 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- UDP CS
42 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Type=HW_CFG
43 => ( DATA => x"03", VALID => '1', ERROR => '0'),
44 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- ID=1
45 => ( DATA => x"01", VALID => '1', ERROR => '0'),
46 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- DATA_LENGTH=0
47 => ( DATA => x"00", VALID => '1', ERROR => '0'),
48 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
49 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
50 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
51 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
52 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
53 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
54 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
55 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
56 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
57 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
58 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
59 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
others => ( DATA => x"00", VALID => '0', ERROR => '0')),
-- No error in this frame
bad_frame => false),
-------------
-- Frame 2
-- Send read HW_CFG
-------------
2 => (
columns => (
0 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Dest Adr
1 => ( DATA => x"23", VALID => '1', ERROR => '0'),
2 => ( DATA => x"20", VALID => '1', ERROR => '0'),
3 => ( DATA => x"21", VALID => '1', ERROR => '0'),
4 => ( DATA => x"22", VALID => '1', ERROR => '0'),
5 => ( DATA => x"23", VALID => '1', ERROR => '0'),
6 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Source Address
7 => ( DATA => x"23", VALID => '1', ERROR => '0'),
8 => ( DATA => x"18", VALID => '1', ERROR => '0'),
9 => ( DATA => x"29", VALID => '1', ERROR => '0'),
10 => ( DATA => x"26", VALID => '1', ERROR => '0'),
11 => ( DATA => x"7c", VALID => '1', ERROR => '0'),
12 => ( DATA => x"08", VALID => '1', ERROR => '0'), --type 0800 IP
13 => ( DATA => x"00", VALID => '1', ERROR => '0'),
14 => ( DATA => x"45", VALID => '1', ERROR => '0'), -- IP HEADER
15 => ( DATA => x"00", VALID => '1', ERROR => '0'),
16 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- LENGTH
17 => ( DATA => x"22", VALID => '1', ERROR => '0'), -- LENGTH
18 => ( DATA => x"00", VALID => '1', ERROR => '0'),
19 => ( DATA => x"7a", VALID => '1', ERROR => '0'),
20 => ( DATA => x"00", VALID => '1', ERROR => '0'),
21 => ( DATA => x"00", VALID => '1', ERROR => '0'),
22 => ( DATA => x"80", VALID => '1', ERROR => '0'),
23 => ( DATA => x"11", VALID => '1', ERROR => '0'), -- Proto: UDP
24 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- IP HEADER CS
25 => ( DATA => x"00", VALID => '1', ERROR => '0'),
26 => ( DATA => x"c0", VALID => '1', ERROR => '0'), -- SRC IP
27 => ( DATA => x"a8", VALID => '1', ERROR => '0'),
28 => ( DATA => x"05", VALID => '1', ERROR => '0'),
29 => ( DATA => x"01", VALID => '1', ERROR => '0'),
30 => ( DATA => x"c0", VALID => '1', ERROR => '0'), -- DEST IP
31 => ( DATA => x"a8", VALID => '1', ERROR => '0'),
32 => ( DATA => x"04", VALID => '1', ERROR => '0'),
33 => ( DATA => x"17", VALID => '1', ERROR => '0'),
34 => ( DATA => x"f4", VALID => '1', ERROR => '0'), -- SRC PORT
35 => ( DATA => x"9a", VALID => '1', ERROR => '0'),
36 => ( DATA => x"D8", VALID => '1', ERROR => '0'), -- DST PORT
37 => ( DATA => x"20", VALID => '1', ERROR => '0'),
38 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- LENGTH
39 => ( DATA => x"0e", VALID => '1', ERROR => '0'), -- LENGTH
40 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- UDP CS
41 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- UDP CS
42 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Type=HW_CFG
43 => ( DATA => x"03", VALID => '1', ERROR => '0'),
44 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- ID=2
45 => ( DATA => x"02", VALID => '1', ERROR => '0'),
46 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- DATA_LENGTH=0
47 => ( DATA => x"00", VALID => '1', ERROR => '0'),
48 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
49 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
50 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
51 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
52 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
53 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
54 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
55 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
56 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
57 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
58 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
59 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
others => ( DATA => x"00", VALID => '0', ERROR => '0')),
-- No error in this frame
bad_frame => false),
-------------
-- Frame 2
-- Send UDP IP pkt dst ip_address C0A80417, from port f49a to port 2694
-------------
3 => (
columns => (
0 => ( DATA => X"00", VALID => '1', ERROR => '0'), -- Dest Adr
1 => ( DATA => X"23", VALID => '1', ERROR => '0'),
2 => ( DATA => X"20", VALID => '1', ERROR => '0'),
3 => ( DATA => X"21", VALID => '1', ERROR => '0'),
4 => ( DATA => X"22", VALID => '1', ERROR => '0'),
5 => ( DATA => X"23", VALID => '1', ERROR => '0'),
6 => ( DATA => X"00", VALID => '1', ERROR => '0'), -- Source Address
7 => ( DATA => X"23", VALID => '1', ERROR => '0'),
8 => ( DATA => X"18", VALID => '1', ERROR => '0'),
9 => ( DATA => X"29", VALID => '1', ERROR => '0'),
10 => ( DATA => X"26", VALID => '1', ERROR => '0'),
11 => ( DATA => X"7c", VALID => '1', ERROR => '0'),
12 => ( DATA => X"08", VALID => '1', ERROR => '0'), --type 0800 IP
13 => ( DATA => X"00", VALID => '1', ERROR => '0'),
14 => ( DATA => X"45", VALID => '1', ERROR => '0'), -- IP HEADER
15 => ( DATA => X"00", VALID => '1', ERROR => '0'),
16 => ( DATA => X"00", VALID => '1', ERROR => '0'), -- LENGTH
17 => ( DATA => X"21", VALID => '1', ERROR => '0'), -- LENGTH
18 => ( DATA => X"00", VALID => '1', ERROR => '0'),
19 => ( DATA => X"7a", VALID => '1', ERROR => '0'),
20 => ( DATA => X"00", VALID => '1', ERROR => '0'),
21 => ( DATA => X"00", VALID => '1', ERROR => '0'),
22 => ( DATA => X"80", VALID => '1', ERROR => '0'),
23 => ( DATA => X"11", VALID => '1', ERROR => '0'), -- Proto: UDP
24 => ( DATA => X"00", VALID => '1', ERROR => '0'), -- IP HEADER CS
25 => ( DATA => X"00", VALID => '1', ERROR => '0'),
26 => ( DATA => X"c0", VALID => '1', ERROR => '0'), -- SRC IP
27 => ( DATA => X"a8", VALID => '1', ERROR => '0'),
28 => ( DATA => X"05", VALID => '1', ERROR => '0'),
29 => ( DATA => X"01", VALID => '1', ERROR => '0'),
30 => ( DATA => X"c0", VALID => '1', ERROR => '0'), -- DEST IP
31 => ( DATA => X"a8", VALID => '1', ERROR => '0'),
32 => ( DATA => X"04", VALID => '1', ERROR => '0'),
33 => ( DATA => X"17", VALID => '1', ERROR => '0'),
34 => ( DATA => X"f4", VALID => '1', ERROR => '0'), -- SRC PORT
35 => ( DATA => X"9a", VALID => '1', ERROR => '0'),
36 => ( DATA => X"D8", VALID => '1', ERROR => '0'), -- DST PORT
37 => ( DATA => X"20", VALID => '1', ERROR => '0'),
38 => ( DATA => X"00", VALID => '1', ERROR => '0'), -- LENGTH
39 => ( DATA => X"0d", VALID => '1', ERROR => '0'), -- LENGTH
40 => ( DATA => X"8b", VALID => '1', ERROR => '0'), -- UDP CS
41 => ( DATA => X"79", VALID => '1', ERROR => '0'), -- UDP CS
42 => ( DATA => X"68", VALID => '1', ERROR => '0'), -- Type=HW_CFG
43 => ( DATA => X"65", VALID => '1', ERROR => '0'),
44 => ( DATA => X"6c", VALID => '1', ERROR => '0'), -- ID=6c6c
45 => ( DATA => X"6c", VALID => '1', ERROR => '0'),
46 => ( DATA => X"6f", VALID => '1', ERROR => '0'), -- DATA_LENGTH=0
47 => ( DATA => X"00", VALID => '1', ERROR => '0'),
48 => ( DATA => X"00", VALID => '1', ERROR => '0'), -- PADDING
49 => ( DATA => X"00", VALID => '1', ERROR => '0'), -- PADDING
50 => ( DATA => X"00", VALID => '1', ERROR => '0'), -- PADDING
51 => ( DATA => X"00", VALID => '1', ERROR => '0'), -- PADDING
52 => ( DATA => X"00", VALID => '1', ERROR => '0'), -- PADDING
53 => ( DATA => X"00", VALID => '1', ERROR => '0'), -- PADDING
54 => ( DATA => X"00", VALID => '1', ERROR => '0'), -- PADDING
55 => ( DATA => X"00", VALID => '1', ERROR => '0'), -- PADDING
56 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
57 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
58 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
59 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
others => ( DATA => X"00", VALID => '0', ERROR => '0')),
-- Error this frame
bad_frame => false),
-------------
-- Frame 3
-- Send start stimuli=0x0
-------------
4 => (
columns => (
0 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Dest Adr
1 => ( DATA => x"23", VALID => '1', ERROR => '0'),
2 => ( DATA => x"20", VALID => '1', ERROR => '0'),
3 => ( DATA => x"21", VALID => '1', ERROR => '0'),
4 => ( DATA => x"22", VALID => '1', ERROR => '0'),
5 => ( DATA => x"23", VALID => '1', ERROR => '0'),
6 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Source Address
7 => ( DATA => x"23", VALID => '1', ERROR => '0'),
8 => ( DATA => x"18", VALID => '1', ERROR => '0'),
9 => ( DATA => x"29", VALID => '1', ERROR => '0'),
10 => ( DATA => x"26", VALID => '1', ERROR => '0'),
11 => ( DATA => x"7c", VALID => '1', ERROR => '0'),
12 => ( DATA => x"08", VALID => '1', ERROR => '0'), --type 0800 IP
13 => ( DATA => x"00", VALID => '1', ERROR => '0'),
14 => ( DATA => x"45", VALID => '1', ERROR => '0'), -- IP HEADER
15 => ( DATA => x"00", VALID => '1', ERROR => '0'),
16 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- LENGTH
17 => ( DATA => x"28", VALID => '1', ERROR => '0'), -- LENGTH
18 => ( DATA => x"00", VALID => '1', ERROR => '0'),
19 => ( DATA => x"7a", VALID => '1', ERROR => '0'),
20 => ( DATA => x"00", VALID => '1', ERROR => '0'),
21 => ( DATA => x"00", VALID => '1', ERROR => '0'),
22 => ( DATA => x"80", VALID => '1', ERROR => '0'),
23 => ( DATA => x"11", VALID => '1', ERROR => '0'), -- Proto: UDP
24 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- IP HEADER CS
25 => ( DATA => x"00", VALID => '1', ERROR => '0'),
26 => ( DATA => x"c0", VALID => '1', ERROR => '0'), -- SRC IP
27 => ( DATA => x"a8", VALID => '1', ERROR => '0'),
28 => ( DATA => x"05", VALID => '1', ERROR => '0'),
29 => ( DATA => x"01", VALID => '1', ERROR => '0'),
30 => ( DATA => x"c0", VALID => '1', ERROR => '0'), -- DEST IP
31 => ( DATA => x"a8", VALID => '1', ERROR => '0'),
32 => ( DATA => x"04", VALID => '1', ERROR => '0'),
33 => ( DATA => x"17", VALID => '1', ERROR => '0'),
34 => ( DATA => x"f4", VALID => '1', ERROR => '0'), -- SRC PORT
35 => ( DATA => x"9a", VALID => '1', ERROR => '0'),
36 => ( DATA => x"D8", VALID => '1', ERROR => '0'), -- DST PORT
37 => ( DATA => x"20", VALID => '1', ERROR => '0'),
38 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- LENGTH
39 => ( DATA => x"15", VALID => '1', ERROR => '0'), -- LENGTH
40 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- UDP CS
41 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- UDP CS
42 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Type=STRStim
43 => ( DATA => x"05", VALID => '1', ERROR => '0'),
44 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- ID=4
45 => ( DATA => x"04", VALID => '1', ERROR => '0'),
46 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- DATA_LENGTH=6
47 => ( DATA => x"02", VALID => '1', ERROR => '0'), -- DATA_LENGTH
48 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- strstim
49 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- strstim
50 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- strstim
51 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- strstim
52 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- strstim
53 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- strstim
54 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
55 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
56 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
57 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
58 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
59 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
others => ( DATA => x"00", VALID => '0', ERROR => '0')),
-- No error in this frame
bad_frame => false),
-------------
-- Frame 5
-- Send end stimuli=fff...
-------------
5 => (
columns => (
0 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Dest Adr
1 => ( DATA => x"23", VALID => '1', ERROR => '0'),
2 => ( DATA => x"20", VALID => '1', ERROR => '0'),
3 => ( DATA => x"21", VALID => '1', ERROR => '0'),
4 => ( DATA => x"22", VALID => '1', ERROR => '0'),
5 => ( DATA => x"23", VALID => '1', ERROR => '0'),
6 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Source Address
7 => ( DATA => x"23", VALID => '1', ERROR => '0'),
8 => ( DATA => x"18", VALID => '1', ERROR => '0'),
9 => ( DATA => x"29", VALID => '1', ERROR => '0'),
10 => ( DATA => x"26", VALID => '1', ERROR => '0'),
11 => ( DATA => x"7c", VALID => '1', ERROR => '0'),
12 => ( DATA => x"08", VALID => '1', ERROR => '0'), --type 0800 IP
13 => ( DATA => x"00", VALID => '1', ERROR => '0'),
14 => ( DATA => x"45", VALID => '1', ERROR => '0'), -- IP HEADER
15 => ( DATA => x"00", VALID => '1', ERROR => '0'),
16 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- LENGTH
17 => ( DATA => x"28", VALID => '1', ERROR => '0'), -- LENGTH
18 => ( DATA => x"00", VALID => '1', ERROR => '0'),
19 => ( DATA => x"7a", VALID => '1', ERROR => '0'),
20 => ( DATA => x"00", VALID => '1', ERROR => '0'),
21 => ( DATA => x"00", VALID => '1', ERROR => '0'),
22 => ( DATA => x"80", VALID => '1', ERROR => '0'),
23 => ( DATA => x"11", VALID => '1', ERROR => '0'), -- Proto: UDP
24 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- IP HEADER CS
25 => ( DATA => x"00", VALID => '1', ERROR => '0'),
26 => ( DATA => x"c0", VALID => '1', ERROR => '0'), -- SRC IP
27 => ( DATA => x"a8", VALID => '1', ERROR => '0'),
28 => ( DATA => x"05", VALID => '1', ERROR => '0'),
29 => ( DATA => x"01", VALID => '1', ERROR => '0'),
30 => ( DATA => x"c0", VALID => '1', ERROR => '0'), -- DEST IP
31 => ( DATA => x"a8", VALID => '1', ERROR => '0'),
32 => ( DATA => x"04", VALID => '1', ERROR => '0'),
33 => ( DATA => x"17", VALID => '1', ERROR => '0'),
34 => ( DATA => x"f4", VALID => '1', ERROR => '0'), -- SRC PORT
35 => ( DATA => x"9a", VALID => '1', ERROR => '0'),
36 => ( DATA => x"D8", VALID => '1', ERROR => '0'), -- DST PORT
37 => ( DATA => x"20", VALID => '1', ERROR => '0'),
38 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- LENGTH
39 => ( DATA => x"15", VALID => '1', ERROR => '0'), -- LENGTH
40 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- UDP CS
41 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- UDP CS
42 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Type=ENDStim
43 => ( DATA => x"06", VALID => '1', ERROR => '0'),
44 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- ID=5
45 => ( DATA => x"05", VALID => '1', ERROR => '0'),
46 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- DATA_LENGTH=6
47 => ( DATA => x"02", VALID => '1', ERROR => '0'),
48 => ( DATA => x"ff", VALID => '1', ERROR => '0'), -- PAD + Stim
49 => ( DATA => x"ff", VALID => '1', ERROR => '0'), -- Stim
50 => ( DATA => x"ff", VALID => '1', ERROR => '0'), -- Stim
51 => ( DATA => x"ff", VALID => '1', ERROR => '0'), -- Stim
52 => ( DATA => x"ff", VALID => '1', ERROR => '0'), -- Stim
53 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Stim
54 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
55 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
56 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
57 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
58 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
59 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
others => ( DATA => x"00", VALID => '0', ERROR => '0')),
-- No error in this frame
bad_frame => false),
-------------
-- Frame 6
-- Send write restart
-------------
6 => (
columns => (
0 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Dest Adr
1 => ( DATA => x"23", VALID => '1', ERROR => '0'),
2 => ( DATA => x"20", VALID => '1', ERROR => '0'),
3 => ( DATA => x"21", VALID => '1', ERROR => '0'),
4 => ( DATA => x"22", VALID => '1', ERROR => '0'),
5 => ( DATA => x"23", VALID => '1', ERROR => '0'),
6 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Source Address
7 => ( DATA => x"23", VALID => '1', ERROR => '0'),
8 => ( DATA => x"18", VALID => '1', ERROR => '0'),
9 => ( DATA => x"29", VALID => '1', ERROR => '0'),
10 => ( DATA => x"26", VALID => '1', ERROR => '0'),
11 => ( DATA => x"7c", VALID => '1', ERROR => '0'),
12 => ( DATA => x"08", VALID => '1', ERROR => '0'), --type 0800 IP
13 => ( DATA => x"00", VALID => '1', ERROR => '0'),
14 => ( DATA => x"45", VALID => '1', ERROR => '0'), -- IP HEADER
15 => ( DATA => x"00", VALID => '1', ERROR => '0'),
16 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- LENGTH
17 => ( DATA => x"22", VALID => '1', ERROR => '0'), -- LENGTH
18 => ( DATA => x"00", VALID => '1', ERROR => '0'),
19 => ( DATA => x"7a", VALID => '1', ERROR => '0'),
20 => ( DATA => x"00", VALID => '1', ERROR => '0'),
21 => ( DATA => x"00", VALID => '1', ERROR => '0'),
22 => ( DATA => x"80", VALID => '1', ERROR => '0'),
23 => ( DATA => x"11", VALID => '1', ERROR => '0'), -- Proto: UDP
24 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- IP HEADER CS
25 => ( DATA => x"00", VALID => '1', ERROR => '0'),
26 => ( DATA => x"c0", VALID => '1', ERROR => '0'), -- SRC IP
27 => ( DATA => x"a8", VALID => '1', ERROR => '0'),
28 => ( DATA => x"05", VALID => '1', ERROR => '0'),
29 => ( DATA => x"01", VALID => '1', ERROR => '0'),
30 => ( DATA => x"c0", VALID => '1', ERROR => '0'), -- DEST IP
31 => ( DATA => x"a8", VALID => '1', ERROR => '0'),
32 => ( DATA => x"04", VALID => '1', ERROR => '0'),
33 => ( DATA => x"17", VALID => '1', ERROR => '0'),
34 => ( DATA => x"f4", VALID => '1', ERROR => '0'), -- SRC PORT
35 => ( DATA => x"9a", VALID => '1', ERROR => '0'),
36 => ( DATA => x"D8", VALID => '1', ERROR => '0'), -- DST PORT
37 => ( DATA => x"20", VALID => '1', ERROR => '0'),
38 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- LENGTH
39 => ( DATA => x"0e", VALID => '1', ERROR => '0'), -- LENGTH
40 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- UDP CS
41 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- UDP CS
42 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Type=RESET
43 => ( DATA => x"07", VALID => '1', ERROR => '0'),
44 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- ID=6
45 => ( DATA => x"06", VALID => '1', ERROR => '0'),
46 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- DATA_LENGTH=0
47 => ( DATA => x"00", VALID => '1', ERROR => '0'),
48 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
49 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
50 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
51 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
52 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
53 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
54 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
55 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
56 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
57 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
58 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
59 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
others => ( DATA => x"00", VALID => '0', ERROR => '0')),
-- No error in this frame
bad_frame => false),
-------------
-- Frame 7
-- Send UDP IP pkt dst ip_address c0a80509, from port f49a to port 2694
-------------
7 => (
columns => (
0 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Dest Adr
1 => ( DATA => x"23", VALID => '1', ERROR => '0'),
2 => ( DATA => x"20", VALID => '1', ERROR => '0'),
3 => ( DATA => x"21", VALID => '1', ERROR => '0'),
4 => ( DATA => x"22", VALID => '1', ERROR => '0'),
5 => ( DATA => x"23", VALID => '1', ERROR => '0'),
6 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Source Adr
7 => ( DATA => x"23", VALID => '1', ERROR => '0'),
8 => ( DATA => x"18", VALID => '1', ERROR => '0'),
9 => ( DATA => x"29", VALID => '1', ERROR => '0'),
10 => ( DATA => x"26", VALID => '1', ERROR => '0'),
11 => ( DATA => x"7c", VALID => '1', ERROR => '0'),
12 => ( DATA => x"08", VALID => '1', ERROR => '0'),
13 => ( DATA => x"00", VALID => '1', ERROR => '0'),
14 => ( DATA => x"45", VALID => '1', ERROR => '0'),
15 => ( DATA => x"00", VALID => '1', ERROR => '0'),
16 => ( DATA => x"00", VALID => '1', ERROR => '0'),
17 => ( DATA => x"21", VALID => '1', ERROR => '0'),
18 => ( DATA => x"00", VALID => '1', ERROR => '0'),
19 => ( DATA => x"7a", VALID => '1', ERROR => '0'),
20 => ( DATA => x"00", VALID => '1', ERROR => '0'),
21 => ( DATA => x"00", VALID => '1', ERROR => '0'),
22 => ( DATA => x"80", VALID => '1', ERROR => '0'),
23 => ( DATA => x"11", VALID => '1', ERROR => '0'),
24 => ( DATA => x"00", VALID => '1', ERROR => '0'),
25 => ( DATA => x"00", VALID => '1', ERROR => '0'),
26 => ( DATA => x"c0", VALID => '1', ERROR => '0'),
27 => ( DATA => x"a8", VALID => '1', ERROR => '0'),
28 => ( DATA => x"05", VALID => '1', ERROR => '0'),
29 => ( DATA => x"01", VALID => '1', ERROR => '0'),
30 => ( DATA => x"c0", VALID => '1', ERROR => '0'),
31 => ( DATA => x"a8", VALID => '1', ERROR => '0'),
32 => ( DATA => x"04", VALID => '1', ERROR => '0'),
33 => ( DATA => x"17", VALID => '1', ERROR => '0'),
34 => ( DATA => x"f4", VALID => '1', ERROR => '0'),
35 => ( DATA => x"9a", VALID => '1', ERROR => '0'),
36 => ( DATA => x"26", VALID => '1', ERROR => '0'),
37 => ( DATA => x"94", VALID => '1', ERROR => '0'),
38 => ( DATA => x"00", VALID => '1', ERROR => '0'),
39 => ( DATA => x"0d", VALID => '1', ERROR => '0'),
40 => ( DATA => x"8b", VALID => '1', ERROR => '0'),
41 => ( DATA => x"79", VALID => '1', ERROR => '0'),
42 => ( DATA => x"68", VALID => '1', ERROR => '0'),
43 => ( DATA => x"65", VALID => '1', ERROR => '0'),
44 => ( DATA => x"6c", VALID => '1', ERROR => '0'),
45 => ( DATA => x"6c", VALID => '1', ERROR => '0'),
46 => ( DATA => x"6f", VALID => '1', ERROR => '0'),
47 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
48 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
49 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
50 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
51 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
52 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
53 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
54 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
55 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
56 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
57 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
58 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
59 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
others => ( DATA => x"00", VALID => '0', ERROR => '0')),
-- No error in this frame
bad_frame => false),
-------------
-- Frame 8
-- Send UDP IP pkt dst ip_address C0A80417, from port f49a to port 2694
-------------
8 => (
columns => (
0 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Dest Adr
1 => ( DATA => x"23", VALID => '1', ERROR => '0'),
2 => ( DATA => x"20", VALID => '1', ERROR => '0'),
3 => ( DATA => x"21", VALID => '1', ERROR => '0'),
4 => ( DATA => x"22", VALID => '1', ERROR => '0'),
5 => ( DATA => x"23", VALID => '1', ERROR => '0'),
6 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Source Adr
7 => ( DATA => x"23", VALID => '1', ERROR => '0'),
8 => ( DATA => x"18", VALID => '1', ERROR => '0'),
9 => ( DATA => x"29", VALID => '1', ERROR => '0'),
10 => ( DATA => x"26", VALID => '1', ERROR => '0'),
11 => ( DATA => x"7c", VALID => '1', ERROR => '0'),
12 => ( DATA => x"08", VALID => '1', ERROR => '0'),
13 => ( DATA => x"00", VALID => '1', ERROR => '0'),
14 => ( DATA => x"45", VALID => '1', ERROR => '0'),
15 => ( DATA => x"00", VALID => '1', ERROR => '0'),
16 => ( DATA => x"00", VALID => '1', ERROR => '0'),
17 => ( DATA => x"21", VALID => '1', ERROR => '0'),
18 => ( DATA => x"00", VALID => '1', ERROR => '0'),
19 => ( DATA => x"7a", VALID => '1', ERROR => '0'),
20 => ( DATA => x"00", VALID => '1', ERROR => '0'),
21 => ( DATA => x"00", VALID => '1', ERROR => '0'),
22 => ( DATA => x"80", VALID => '1', ERROR => '0'),
23 => ( DATA => x"11", VALID => '1', ERROR => '0'),
24 => ( DATA => x"00", VALID => '1', ERROR => '0'),
25 => ( DATA => x"00", VALID => '1', ERROR => '0'),
26 => ( DATA => x"c0", VALID => '1', ERROR => '0'),
27 => ( DATA => x"a8", VALID => '1', ERROR => '0'),
28 => ( DATA => x"05", VALID => '1', ERROR => '0'),
29 => ( DATA => x"01", VALID => '1', ERROR => '0'),
30 => ( DATA => x"c0", VALID => '1', ERROR => '0'),
31 => ( DATA => x"a8", VALID => '1', ERROR => '0'),
32 => ( DATA => x"04", VALID => '1', ERROR => '0'),
33 => ( DATA => x"17", VALID => '1', ERROR => '0'),
34 => ( DATA => x"f4", VALID => '1', ERROR => '0'),
35 => ( DATA => x"9a", VALID => '1', ERROR => '0'),
36 => ( DATA => x"26", VALID => '1', ERROR => '0'),
37 => ( DATA => x"94", VALID => '1', ERROR => '0'),
38 => ( DATA => x"00", VALID => '1', ERROR => '0'),
39 => ( DATA => x"0d", VALID => '1', ERROR => '0'),
40 => ( DATA => x"8b", VALID => '1', ERROR => '0'),
41 => ( DATA => x"79", VALID => '1', ERROR => '0'),
42 => ( DATA => x"42", VALID => '1', ERROR => '0'),
43 => ( DATA => x"65", VALID => '1', ERROR => '0'),
44 => ( DATA => x"6c", VALID => '1', ERROR => '0'),
45 => ( DATA => x"6c", VALID => '1', ERROR => '0'),
46 => ( DATA => x"6f", VALID => '1', ERROR => '0'),
47 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
48 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
49 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
50 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
51 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
52 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
53 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
54 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
55 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
56 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
57 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
58 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
59 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
others => ( DATA => x"00", VALID => '0', ERROR => '0')),
-- No error in this frame
bad_frame => false),
-------------
-- Frame 9
-- Send UDP IP pkt dst ip_address bc, from port f49a to port 2694
-------------
9 => (
columns => (
0 => ( DATA => x"ff", VALID => '1', ERROR => '0'), -- Dest Adr
1 => ( DATA => x"ff", VALID => '1', ERROR => '0'),
2 => ( DATA => x"ff", VALID => '1', ERROR => '0'),
3 => ( DATA => x"ff", VALID => '1', ERROR => '0'),
4 => ( DATA => x"ff", VALID => '1', ERROR => '0'),
5 => ( DATA => x"ff", VALID => '1', ERROR => '0'),
6 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Source Adr
7 => ( DATA => x"23", VALID => '1', ERROR => '0'),
8 => ( DATA => x"18", VALID => '1', ERROR => '0'),
9 => ( DATA => x"29", VALID => '1', ERROR => '0'),
10 => ( DATA => x"26", VALID => '1', ERROR => '0'),
11 => ( DATA => x"7c", VALID => '1', ERROR => '0'),
12 => ( DATA => x"08", VALID => '1', ERROR => '0'),
13 => ( DATA => x"00", VALID => '1', ERROR => '0'),
14 => ( DATA => x"45", VALID => '1', ERROR => '0'),
15 => ( DATA => x"00", VALID => '1', ERROR => '0'),
16 => ( DATA => x"00", VALID => '1', ERROR => '0'),
17 => ( DATA => x"21", VALID => '1', ERROR => '0'),
18 => ( DATA => x"00", VALID => '1', ERROR => '0'),
19 => ( DATA => x"7a", VALID => '1', ERROR => '0'),
20 => ( DATA => x"00", VALID => '1', ERROR => '0'),
21 => ( DATA => x"00", VALID => '1', ERROR => '0'),
22 => ( DATA => x"80", VALID => '1', ERROR => '0'),
23 => ( DATA => x"11", VALID => '1', ERROR => '0'),
24 => ( DATA => x"00", VALID => '1', ERROR => '0'),
25 => ( DATA => x"00", VALID => '1', ERROR => '0'),
26 => ( DATA => x"c0", VALID => '1', ERROR => '0'),
27 => ( DATA => x"a8", VALID => '1', ERROR => '0'),
28 => ( DATA => x"05", VALID => '1', ERROR => '0'),
29 => ( DATA => x"01", VALID => '1', ERROR => '0'),
30 => ( DATA => x"ff", VALID => '1', ERROR => '0'),
31 => ( DATA => x"ff", VALID => '1', ERROR => '0'),
32 => ( DATA => x"ff", VALID => '1', ERROR => '0'),
33 => ( DATA => x"ff", VALID => '1', ERROR => '0'),
34 => ( DATA => x"f4", VALID => '1', ERROR => '0'),
35 => ( DATA => x"9a", VALID => '1', ERROR => '0'),
36 => ( DATA => x"26", VALID => '1', ERROR => '0'),
37 => ( DATA => x"94", VALID => '1', ERROR => '0'),
38 => ( DATA => x"00", VALID => '1', ERROR => '0'),
39 => ( DATA => x"0d", VALID => '1', ERROR => '0'),
40 => ( DATA => x"8b", VALID => '1', ERROR => '0'),
41 => ( DATA => x"79", VALID => '1', ERROR => '0'),
42 => ( DATA => x"68", VALID => '1', ERROR => '0'),
43 => ( DATA => x"65", VALID => '1', ERROR => '0'),
44 => ( DATA => x"6c", VALID => '1', ERROR => '0'),
45 => ( DATA => x"6c", VALID => '1', ERROR => '0'),
46 => ( DATA => x"6f", VALID => '1', ERROR => '0'),
47 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
48 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
49 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
50 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
51 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
52 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
53 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
54 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
55 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
56 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
57 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
58 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
59 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
others => ( DATA => x"00", VALID => '0', ERROR => '0')),
-- No error in this frame
bad_frame => false),
-------------
-- Frame 10
-- Send UDP IP pkt dst ip_address C0A80417, from port f49a to port 2694 with data x43 to trig tx to unknown IP";
-------------
10 => (
columns => (
0 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Dest Adr
1 => ( DATA => x"23", VALID => '1', ERROR => '0'),
2 => ( DATA => x"20", VALID => '1', ERROR => '0'),
3 => ( DATA => x"21", VALID => '1', ERROR => '0'),
4 => ( DATA => x"22", VALID => '1', ERROR => '0'),
5 => ( DATA => x"23", VALID => '1', ERROR => '0'),
6 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Source Adr
7 => ( DATA => x"23", VALID => '1', ERROR => '0'),
8 => ( DATA => x"18", VALID => '1', ERROR => '0'),
9 => ( DATA => x"29", VALID => '1', ERROR => '0'),
10 => ( DATA => x"26", VALID => '1', ERROR => '0'),
11 => ( DATA => x"7c", VALID => '1', ERROR => '0'),
12 => ( DATA => x"08", VALID => '1', ERROR => '0'),
13 => ( DATA => x"00", VALID => '1', ERROR => '0'),
14 => ( DATA => x"45", VALID => '1', ERROR => '0'),
15 => ( DATA => x"00", VALID => '1', ERROR => '0'),
16 => ( DATA => x"00", VALID => '1', ERROR => '0'),
17 => ( DATA => x"21", VALID => '1', ERROR => '0'),
18 => ( DATA => x"00", VALID => '1', ERROR => '0'),
19 => ( DATA => x"7a", VALID => '1', ERROR => '0'),
20 => ( DATA => x"00", VALID => '1', ERROR => '0'),
21 => ( DATA => x"00", VALID => '1', ERROR => '0'),
22 => ( DATA => x"80", VALID => '1', ERROR => '0'),
23 => ( DATA => x"11", VALID => '1', ERROR => '0'),
24 => ( DATA => x"00", VALID => '1', ERROR => '0'),
25 => ( DATA => x"00", VALID => '1', ERROR => '0'),
26 => ( DATA => x"c0", VALID => '1', ERROR => '0'),
27 => ( DATA => x"a8", VALID => '1', ERROR => '0'),
28 => ( DATA => x"05", VALID => '1', ERROR => '0'),
29 => ( DATA => x"01", VALID => '1', ERROR => '0'),
30 => ( DATA => x"c0", VALID => '1', ERROR => '0'),
31 => ( DATA => x"a8", VALID => '1', ERROR => '0'),
32 => ( DATA => x"04", VALID => '1', ERROR => '0'),
33 => ( DATA => x"17", VALID => '1', ERROR => '0'),
34 => ( DATA => x"f4", VALID => '1', ERROR => '0'),
35 => ( DATA => x"9a", VALID => '1', ERROR => '0'),
36 => ( DATA => x"26", VALID => '1', ERROR => '0'),
37 => ( DATA => x"94", VALID => '1', ERROR => '0'),
38 => ( DATA => x"00", VALID => '1', ERROR => '0'),
39 => ( DATA => x"0d", VALID => '1', ERROR => '0'),
40 => ( DATA => x"8b", VALID => '1', ERROR => '0'),
41 => ( DATA => x"79", VALID => '1', ERROR => '0'),
42 => ( DATA => x"43", VALID => '1', ERROR => '0'),
43 => ( DATA => x"65", VALID => '1', ERROR => '0'),
44 => ( DATA => x"6c", VALID => '1', ERROR => '0'),
45 => ( DATA => x"6c", VALID => '1', ERROR => '0'),
46 => ( DATA => x"6f", VALID => '1', ERROR => '0'),
47 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
48 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
49 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
50 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
51 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
52 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
53 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
54 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
55 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
56 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
57 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
58 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
59 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
others => ( DATA => x"00", VALID => '0', ERROR => '0')),
-- No error in this frame
bad_frame => false),
-------------
-- Frame 12
-- Send UDP IP pkt dst ip_address c0a80509, from port f49a to port 2694
-------------
11 => (
columns => (
0 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Dest Adr
1 => ( DATA => x"23", VALID => '1', ERROR => '0'),
2 => ( DATA => x"20", VALID => '1', ERROR => '0'),
3 => ( DATA => x"21", VALID => '1', ERROR => '0'),
4 => ( DATA => x"22", VALID => '1', ERROR => '0'),
5 => ( DATA => x"23", VALID => '1', ERROR => '0'),
6 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Source Adr
7 => ( DATA => x"23", VALID => '1', ERROR => '0'),
8 => ( DATA => x"18", VALID => '1', ERROR => '0'),
9 => ( DATA => x"29", VALID => '1', ERROR => '0'),
10 => ( DATA => x"26", VALID => '1', ERROR => '0'),
11 => ( DATA => x"7c", VALID => '1', ERROR => '0'),
12 => ( DATA => x"08", VALID => '1', ERROR => '0'),
13 => ( DATA => x"00", VALID => '1', ERROR => '0'),
14 => ( DATA => x"45", VALID => '1', ERROR => '0'),
15 => ( DATA => x"00", VALID => '1', ERROR => '0'),
16 => ( DATA => x"00", VALID => '1', ERROR => '0'),
17 => ( DATA => x"21", VALID => '1', ERROR => '0'),
18 => ( DATA => x"00", VALID => '1', ERROR => '0'),
19 => ( DATA => x"7a", VALID => '1', ERROR => '0'),
20 => ( DATA => x"00", VALID => '1', ERROR => '0'),
21 => ( DATA => x"00", VALID => '1', ERROR => '0'),
22 => ( DATA => x"80", VALID => '1', ERROR => '0'),
23 => ( DATA => x"11", VALID => '1', ERROR => '0'),
24 => ( DATA => x"00", VALID => '1', ERROR => '0'),
25 => ( DATA => x"00", VALID => '1', ERROR => '0'),
26 => ( DATA => x"c0", VALID => '1', ERROR => '0'),
27 => ( DATA => x"a8", VALID => '1', ERROR => '0'),
28 => ( DATA => x"05", VALID => '1', ERROR => '0'),
29 => ( DATA => x"01", VALID => '1', ERROR => '0'),
30 => ( DATA => x"c0", VALID => '1', ERROR => '0'),
31 => ( DATA => x"a8", VALID => '1', ERROR => '0'),
32 => ( DATA => x"04", VALID => '1', ERROR => '0'),
33 => ( DATA => x"17", VALID => '1', ERROR => '0'),
34 => ( DATA => x"f4", VALID => '1', ERROR => '0'),
35 => ( DATA => x"9a", VALID => '1', ERROR => '0'),
36 => ( DATA => x"26", VALID => '1', ERROR => '0'),
37 => ( DATA => x"94", VALID => '1', ERROR => '0'),
38 => ( DATA => x"00", VALID => '1', ERROR => '0'),
39 => ( DATA => x"0d", VALID => '1', ERROR => '0'),
40 => ( DATA => x"8b", VALID => '1', ERROR => '0'),
41 => ( DATA => x"79", VALID => '1', ERROR => '0'),
42 => ( DATA => x"68", VALID => '1', ERROR => '0'),
43 => ( DATA => x"65", VALID => '1', ERROR => '0'),
44 => ( DATA => x"6c", VALID => '1', ERROR => '0'),
45 => ( DATA => x"6c", VALID => '1', ERROR => '0'),
46 => ( DATA => x"6f", VALID => '1', ERROR => '0'),
47 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
48 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
49 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
50 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
51 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
52 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
53 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
54 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
55 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
56 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
57 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
58 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
59 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
others => ( DATA => x"00", VALID => '0', ERROR => '0')),
-- No error in this frame
bad_frame => false),
-------------
-- Frame 13
-- Send cntrd
-------------
12 => (
columns => (
0 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Dest Adr
1 => ( DATA => x"23", VALID => '1', ERROR => '0'),
2 => ( DATA => x"20", VALID => '1', ERROR => '0'),
3 => ( DATA => x"21", VALID => '1', ERROR => '0'),
4 => ( DATA => x"22", VALID => '1', ERROR => '0'),
5 => ( DATA => x"23", VALID => '1', ERROR => '0'),
6 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Source Address
7 => ( DATA => x"23", VALID => '1', ERROR => '0'),
8 => ( DATA => x"18", VALID => '1', ERROR => '0'),
9 => ( DATA => x"29", VALID => '1', ERROR => '0'),
10 => ( DATA => x"26", VALID => '1', ERROR => '0'),
11 => ( DATA => x"7c", VALID => '1', ERROR => '0'),
12 => ( DATA => x"08", VALID => '1', ERROR => '0'), --type 0800 IP
13 => ( DATA => x"00", VALID => '1', ERROR => '0'),
14 => ( DATA => x"45", VALID => '1', ERROR => '0'), -- IP HEADER
15 => ( DATA => x"00", VALID => '1', ERROR => '0'),
16 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- LENGTH
17 => ( DATA => x"22", VALID => '1', ERROR => '0'), -- LENGTH
18 => ( DATA => x"00", VALID => '1', ERROR => '0'),
19 => ( DATA => x"7a", VALID => '1', ERROR => '0'),
20 => ( DATA => x"00", VALID => '1', ERROR => '0'),
21 => ( DATA => x"00", VALID => '1', ERROR => '0'),
22 => ( DATA => x"80", VALID => '1', ERROR => '0'),
23 => ( DATA => x"11", VALID => '1', ERROR => '0'), -- Proto: UDP
24 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- IP HEADER CS
25 => ( DATA => x"00", VALID => '1', ERROR => '0'),
26 => ( DATA => x"c0", VALID => '1', ERROR => '0'), -- SRC IP
27 => ( DATA => x"a8", VALID => '1', ERROR => '0'),
28 => ( DATA => x"05", VALID => '1', ERROR => '0'),
29 => ( DATA => x"01", VALID => '1', ERROR => '0'),
30 => ( DATA => x"c0", VALID => '1', ERROR => '0'), -- DEST IP
31 => ( DATA => x"a8", VALID => '1', ERROR => '0'),
32 => ( DATA => x"04", VALID => '1', ERROR => '0'),
33 => ( DATA => x"17", VALID => '1', ERROR => '0'),
34 => ( DATA => x"f4", VALID => '1', ERROR => '0'), -- SRC PORT
35 => ( DATA => x"9a", VALID => '1', ERROR => '0'),
36 => ( DATA => x"D8", VALID => '1', ERROR => '0'), -- DST PORT
37 => ( DATA => x"20", VALID => '1', ERROR => '0'),
38 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- LENGTH
39 => ( DATA => x"0e", VALID => '1', ERROR => '0'), -- LENGTH
40 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- UDP CS
41 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- UDP CS
42 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Type=RESET
43 => ( DATA => x"0d", VALID => '1', ERROR => '0'),
44 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- ID=7
45 => ( DATA => x"07", VALID => '1', ERROR => '0'),
46 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- DATA_LENGTH=0
47 => ( DATA => x"00", VALID => '1', ERROR => '0'),
48 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
49 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
50 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
51 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
52 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
53 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
54 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
55 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
56 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
57 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
58 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
59 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
others => ( DATA => x"00", VALID => '0', ERROR => '0')),
-- No error in this frame
bad_frame => false),
-------------
-- Frame 1 after Pause
-- Send read ERROR_COUNT
-------------
C_PAUSE_AFTER_FRAME + 1 => (
columns => (
0 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Dest Adr
1 => ( DATA => x"23", VALID => '1', ERROR => '0'),
2 => ( DATA => x"20", VALID => '1', ERROR => '0'),
3 => ( DATA => x"21", VALID => '1', ERROR => '0'),
4 => ( DATA => x"22", VALID => '1', ERROR => '0'),
5 => ( DATA => x"23", VALID => '1', ERROR => '0'),
6 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Source Address
7 => ( DATA => x"23", VALID => '1', ERROR => '0'),
8 => ( DATA => x"18", VALID => '1', ERROR => '0'),
9 => ( DATA => x"29", VALID => '1', ERROR => '0'),
10 => ( DATA => x"26", VALID => '1', ERROR => '0'),
11 => ( DATA => x"7c", VALID => '1', ERROR => '0'),
12 => ( DATA => x"08", VALID => '1', ERROR => '0'), --type 0800 IP
13 => ( DATA => x"00", VALID => '1', ERROR => '0'),
14 => ( DATA => x"45", VALID => '1', ERROR => '0'), -- IP HEADER
15 => ( DATA => x"00", VALID => '1', ERROR => '0'),
16 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- LENGTH
17 => ( DATA => x"22", VALID => '1', ERROR => '0'), -- LENGTH
18 => ( DATA => x"00", VALID => '1', ERROR => '0'),
19 => ( DATA => x"7a", VALID => '1', ERROR => '0'),
20 => ( DATA => x"00", VALID => '1', ERROR => '0'),
21 => ( DATA => x"00", VALID => '1', ERROR => '0'),
22 => ( DATA => x"80", VALID => '1', ERROR => '0'),
23 => ( DATA => x"11", VALID => '1', ERROR => '0'), -- Proto: UDP
24 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- IP HEADER CS
25 => ( DATA => x"00", VALID => '1', ERROR => '0'),
26 => ( DATA => x"c0", VALID => '1', ERROR => '0'), -- SRC IP
27 => ( DATA => x"a8", VALID => '1', ERROR => '0'),
28 => ( DATA => x"05", VALID => '1', ERROR => '0'),
29 => ( DATA => x"01", VALID => '1', ERROR => '0'),
30 => ( DATA => x"c0", VALID => '1', ERROR => '0'), -- DEST IP
31 => ( DATA => x"a8", VALID => '1', ERROR => '0'),
32 => ( DATA => x"04", VALID => '1', ERROR => '0'),
33 => ( DATA => x"17", VALID => '1', ERROR => '0'),
34 => ( DATA => x"f4", VALID => '1', ERROR => '0'), -- SRC PORT
35 => ( DATA => x"9a", VALID => '1', ERROR => '0'),
36 => ( DATA => x"D8", VALID => '1', ERROR => '0'), -- DST PORT
37 => ( DATA => x"20", VALID => '1', ERROR => '0'),
38 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- LENGTH
39 => ( DATA => x"0e", VALID => '1', ERROR => '0'), -- LENGTH
40 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- UDP CS
41 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- UDP CS
42 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Type=ERRORCNT
43 => ( DATA => x"08", VALID => '1', ERROR => '0'),
44 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- ID=7
45 => ( DATA => x"07", VALID => '1', ERROR => '0'),
46 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- DATA_LENGTH=0
47 => ( DATA => x"00", VALID => '1', ERROR => '0'),
48 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
49 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
50 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
51 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
52 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
53 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
54 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
55 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
56 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
57 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
58 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
59 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
others => ( DATA => x"00", VALID => '0', ERROR => '0')),
-- No error in this frame
bad_frame => false),
-------------
-- Frame 2 after pause
-- Send read ERROR_STORED
-------------
C_PAUSE_AFTER_FRAME + 2 => (
columns => (
0 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Dest Adr
1 => ( DATA => x"23", VALID => '1', ERROR => '0'),
2 => ( DATA => x"20", VALID => '1', ERROR => '0'),
3 => ( DATA => x"21", VALID => '1', ERROR => '0'),
4 => ( DATA => x"22", VALID => '1', ERROR => '0'),
5 => ( DATA => x"23", VALID => '1', ERROR => '0'),
6 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Source Address
7 => ( DATA => x"23", VALID => '1', ERROR => '0'),
8 => ( DATA => x"18", VALID => '1', ERROR => '0'),
9 => ( DATA => x"29", VALID => '1', ERROR => '0'),
10 => ( DATA => x"26", VALID => '1', ERROR => '0'),
11 => ( DATA => x"7c", VALID => '1', ERROR => '0'),
12 => ( DATA => x"08", VALID => '1', ERROR => '0'), --type 0800 IP
13 => ( DATA => x"00", VALID => '1', ERROR => '0'),
14 => ( DATA => x"45", VALID => '1', ERROR => '0'), -- IP HEADER
15 => ( DATA => x"00", VALID => '1', ERROR => '0'),
16 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- LENGTH
17 => ( DATA => x"22", VALID => '1', ERROR => '0'), -- LENGTH
18 => ( DATA => x"00", VALID => '1', ERROR => '0'),
19 => ( DATA => x"7a", VALID => '1', ERROR => '0'),
20 => ( DATA => x"00", VALID => '1', ERROR => '0'),
21 => ( DATA => x"00", VALID => '1', ERROR => '0'),
22 => ( DATA => x"80", VALID => '1', ERROR => '0'),
23 => ( DATA => x"11", VALID => '1', ERROR => '0'), -- Proto: UDP
24 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- IP HEADER CS
25 => ( DATA => x"00", VALID => '1', ERROR => '0'),
26 => ( DATA => x"c0", VALID => '1', ERROR => '0'), -- SRC IP
27 => ( DATA => x"a8", VALID => '1', ERROR => '0'),
28 => ( DATA => x"05", VALID => '1', ERROR => '0'),
29 => ( DATA => x"01", VALID => '1', ERROR => '0'),
30 => ( DATA => x"c0", VALID => '1', ERROR => '0'), -- DEST IP
31 => ( DATA => x"a8", VALID => '1', ERROR => '0'),
32 => ( DATA => x"04", VALID => '1', ERROR => '0'),
33 => ( DATA => x"17", VALID => '1', ERROR => '0'),
34 => ( DATA => x"f4", VALID => '1', ERROR => '0'), -- SRC PORT
35 => ( DATA => x"9a", VALID => '1', ERROR => '0'),
36 => ( DATA => x"D8", VALID => '1', ERROR => '0'), -- DST PORT
37 => ( DATA => x"20", VALID => '1', ERROR => '0'),
38 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- LENGTH
39 => ( DATA => x"0e", VALID => '1', ERROR => '0'), -- LENGTH
40 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- UDP CS
41 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- UDP CS
42 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Type=ERRORstr
43 => ( DATA => x"09", VALID => '1', ERROR => '0'),
44 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- ID=8
45 => ( DATA => x"08", VALID => '1', ERROR => '0'),
46 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- DATA_LENGTH=0
47 => ( DATA => x"00", VALID => '1', ERROR => '0'),
48 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
49 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
50 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
51 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
52 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
53 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
54 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
55 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
56 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
57 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
58 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
59 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
others => ( DATA => x"00", VALID => '0', ERROR => '0')),
-- No error in this frame
bad_frame => false),
-------------
-- Frame 3
-- Send read ERRORS_DROPED
-------------
C_PAUSE_AFTER_FRAME + 3 => (
columns => (
0 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Dest Adr
1 => ( DATA => x"23", VALID => '1', ERROR => '0'),
2 => ( DATA => x"20", VALID => '1', ERROR => '0'),
3 => ( DATA => x"21", VALID => '1', ERROR => '0'),
4 => ( DATA => x"22", VALID => '1', ERROR => '0'),
5 => ( DATA => x"23", VALID => '1', ERROR => '0'),
6 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Source Address
7 => ( DATA => x"23", VALID => '1', ERROR => '0'),
8 => ( DATA => x"18", VALID => '1', ERROR => '0'),
9 => ( DATA => x"29", VALID => '1', ERROR => '0'),
10 => ( DATA => x"26", VALID => '1', ERROR => '0'),
11 => ( DATA => x"7c", VALID => '1', ERROR => '0'),
12 => ( DATA => x"08", VALID => '1', ERROR => '0'), --type 0800 IP
13 => ( DATA => x"00", VALID => '1', ERROR => '0'),
14 => ( DATA => x"45", VALID => '1', ERROR => '0'), -- IP HEADER
15 => ( DATA => x"00", VALID => '1', ERROR => '0'),
16 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- LENGTH
17 => ( DATA => x"22", VALID => '1', ERROR => '0'), -- LENGTH
18 => ( DATA => x"00", VALID => '1', ERROR => '0'),
19 => ( DATA => x"7a", VALID => '1', ERROR => '0'),
20 => ( DATA => x"00", VALID => '1', ERROR => '0'),
21 => ( DATA => x"00", VALID => '1', ERROR => '0'),
22 => ( DATA => x"80", VALID => '1', ERROR => '0'),
23 => ( DATA => x"11", VALID => '1', ERROR => '0'), -- Proto: UDP
24 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- IP HEADER CS
25 => ( DATA => x"00", VALID => '1', ERROR => '0'),
26 => ( DATA => x"c0", VALID => '1', ERROR => '0'), -- SRC IP
27 => ( DATA => x"a8", VALID => '1', ERROR => '0'),
28 => ( DATA => x"05", VALID => '1', ERROR => '0'),
29 => ( DATA => x"01", VALID => '1', ERROR => '0'),
30 => ( DATA => x"c0", VALID => '1', ERROR => '0'), -- DEST IP
31 => ( DATA => x"a8", VALID => '1', ERROR => '0'),
32 => ( DATA => x"04", VALID => '1', ERROR => '0'),
33 => ( DATA => x"17", VALID => '1', ERROR => '0'),
34 => ( DATA => x"f4", VALID => '1', ERROR => '0'), -- SRC PORT
35 => ( DATA => x"9a", VALID => '1', ERROR => '0'),
36 => ( DATA => x"D8", VALID => '1', ERROR => '0'), -- DST PORT
37 => ( DATA => x"20", VALID => '1', ERROR => '0'),
38 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- LENGTH
39 => ( DATA => x"0e", VALID => '1', ERROR => '0'), -- LENGTH
40 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- UDP CS
41 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- UDP CS
42 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Type=ERRORDRP
43 => ( DATA => x"0a", VALID => '1', ERROR => '0'),
44 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- ID=9
45 => ( DATA => x"09", VALID => '1', ERROR => '0'),
46 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- DATA_LENGTH=0
47 => ( DATA => x"00", VALID => '1', ERROR => '0'),
48 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
49 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
50 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
51 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
52 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
53 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
54 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
55 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
56 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
57 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
58 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
59 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
others => ( DATA => x"00", VALID => '0', ERROR => '0')),
-- No error in this frame
bad_frame => false),
-------------
-- Frame 4 after pause
-- Send read next error
-------------
C_PAUSE_AFTER_FRAME + 4 => (
columns => (
0 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Dest Adr
1 => ( DATA => x"23", VALID => '1', ERROR => '0'),
2 => ( DATA => x"20", VALID => '1', ERROR => '0'),
3 => ( DATA => x"21", VALID => '1', ERROR => '0'),
4 => ( DATA => x"22", VALID => '1', ERROR => '0'),
5 => ( DATA => x"23", VALID => '1', ERROR => '0'),
6 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Source Address
7 => ( DATA => x"23", VALID => '1', ERROR => '0'),
8 => ( DATA => x"18", VALID => '1', ERROR => '0'),
9 => ( DATA => x"29", VALID => '1', ERROR => '0'),
10 => ( DATA => x"26", VALID => '1', ERROR => '0'),
11 => ( DATA => x"7c", VALID => '1', ERROR => '0'),
12 => ( DATA => x"08", VALID => '1', ERROR => '0'), --type 0800 IP
13 => ( DATA => x"00", VALID => '1', ERROR => '0'),
14 => ( DATA => x"45", VALID => '1', ERROR => '0'), -- IP HEADER
15 => ( DATA => x"00", VALID => '1', ERROR => '0'),
16 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- LENGTH
17 => ( DATA => x"22", VALID => '1', ERROR => '0'), -- LENGTH
18 => ( DATA => x"00", VALID => '1', ERROR => '0'),
19 => ( DATA => x"7a", VALID => '1', ERROR => '0'),
20 => ( DATA => x"00", VALID => '1', ERROR => '0'),
21 => ( DATA => x"00", VALID => '1', ERROR => '0'),
22 => ( DATA => x"80", VALID => '1', ERROR => '0'),
23 => ( DATA => x"11", VALID => '1', ERROR => '0'), -- Proto: UDP
24 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- IP HEADER CS
25 => ( DATA => x"00", VALID => '1', ERROR => '0'),
26 => ( DATA => x"c0", VALID => '1', ERROR => '0'), -- SRC IP
27 => ( DATA => x"a8", VALID => '1', ERROR => '0'),
28 => ( DATA => x"05", VALID => '1', ERROR => '0'),
29 => ( DATA => x"01", VALID => '1', ERROR => '0'),
30 => ( DATA => x"c0", VALID => '1', ERROR => '0'), -- DEST IP
31 => ( DATA => x"a8", VALID => '1', ERROR => '0'),
32 => ( DATA => x"04", VALID => '1', ERROR => '0'),
33 => ( DATA => x"17", VALID => '1', ERROR => '0'),
34 => ( DATA => x"f4", VALID => '1', ERROR => '0'), -- SRC PORT
35 => ( DATA => x"9a", VALID => '1', ERROR => '0'),
36 => ( DATA => x"D8", VALID => '1', ERROR => '0'), -- DST PORT
37 => ( DATA => x"20", VALID => '1', ERROR => '0'),
38 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- LENGTH
39 => ( DATA => x"0e", VALID => '1', ERROR => '0'), -- LENGTH
40 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- UDP CS
41 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- UDP CS
42 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Type=getERR
43 => ( DATA => x"0b", VALID => '1', ERROR => '0'),
44 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- ID=10
45 => ( DATA => x"0a", VALID => '1', ERROR => '0'),
46 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- DATA_LENGTH=0
47 => ( DATA => x"00", VALID => '1', ERROR => '0'),
48 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
49 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
50 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
51 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
52 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
53 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
54 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
55 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
56 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
57 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
58 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
59 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
others => ( DATA => x"00", VALID => '0', ERROR => '0')),
-- No error in this frame
bad_frame => false),
-------------
-- Frame 5 after pause
-- Send read next error
-------------
C_PAUSE_AFTER_FRAME + 5 => (
columns => (
0 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Dest Adr
1 => ( DATA => x"23", VALID => '1', ERROR => '0'),
2 => ( DATA => x"20", VALID => '1', ERROR => '0'),
3 => ( DATA => x"21", VALID => '1', ERROR => '0'),
4 => ( DATA => x"22", VALID => '1', ERROR => '0'),
5 => ( DATA => x"23", VALID => '1', ERROR => '0'),
6 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Source Address
7 => ( DATA => x"23", VALID => '1', ERROR => '0'),
8 => ( DATA => x"18", VALID => '1', ERROR => '0'),
9 => ( DATA => x"29", VALID => '1', ERROR => '0'),
10 => ( DATA => x"26", VALID => '1', ERROR => '0'),
11 => ( DATA => x"7c", VALID => '1', ERROR => '0'),
12 => ( DATA => x"08", VALID => '1', ERROR => '0'), --type 0800 IP
13 => ( DATA => x"00", VALID => '1', ERROR => '0'),
14 => ( DATA => x"45", VALID => '1', ERROR => '0'), -- IP HEADER
15 => ( DATA => x"00", VALID => '1', ERROR => '0'),
16 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- LENGTH
17 => ( DATA => x"22", VALID => '1', ERROR => '0'), -- LENGTH
18 => ( DATA => x"00", VALID => '1', ERROR => '0'),
19 => ( DATA => x"7a", VALID => '1', ERROR => '0'),
20 => ( DATA => x"00", VALID => '1', ERROR => '0'),
21 => ( DATA => x"00", VALID => '1', ERROR => '0'),
22 => ( DATA => x"80", VALID => '1', ERROR => '0'),
23 => ( DATA => x"11", VALID => '1', ERROR => '0'), -- Proto: UDP
24 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- IP HEADER CS
25 => ( DATA => x"00", VALID => '1', ERROR => '0'),
26 => ( DATA => x"c0", VALID => '1', ERROR => '0'), -- SRC IP
27 => ( DATA => x"a8", VALID => '1', ERROR => '0'),
28 => ( DATA => x"05", VALID => '1', ERROR => '0'),
29 => ( DATA => x"01", VALID => '1', ERROR => '0'),
30 => ( DATA => x"c0", VALID => '1', ERROR => '0'), -- DEST IP
31 => ( DATA => x"a8", VALID => '1', ERROR => '0'),
32 => ( DATA => x"04", VALID => '1', ERROR => '0'),
33 => ( DATA => x"17", VALID => '1', ERROR => '0'),
34 => ( DATA => x"f4", VALID => '1', ERROR => '0'), -- SRC PORT
35 => ( DATA => x"9a", VALID => '1', ERROR => '0'),
36 => ( DATA => x"D8", VALID => '1', ERROR => '0'), -- DST PORT
37 => ( DATA => x"20", VALID => '1', ERROR => '0'),
38 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- LENGTH
39 => ( DATA => x"0e", VALID => '1', ERROR => '0'), -- LENGTH
40 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- UDP CS
41 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- UDP CS
42 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Type=getERR
43 => ( DATA => x"0b", VALID => '1', ERROR => '0'),
44 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- ID=10
45 => ( DATA => x"0a", VALID => '1', ERROR => '0'),
46 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- DATA_LENGTH=0
47 => ( DATA => x"00", VALID => '1', ERROR => '0'),
48 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
49 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
50 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
51 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
52 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
53 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
54 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
55 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
56 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
57 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
58 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
59 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
others => ( DATA => x"00", VALID => '0', ERROR => '0')),
-- No error in this frame
bad_frame => false),
-------------
-- Frame 6 after pause
-- Send read next error
-------------
C_PAUSE_AFTER_FRAME + 6 => (
columns => (
0 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Dest Adr
1 => ( DATA => x"23", VALID => '1', ERROR => '0'),
2 => ( DATA => x"20", VALID => '1', ERROR => '0'),
3 => ( DATA => x"21", VALID => '1', ERROR => '0'),
4 => ( DATA => x"22", VALID => '1', ERROR => '0'),
5 => ( DATA => x"23", VALID => '1', ERROR => '0'),
6 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Source Address
7 => ( DATA => x"23", VALID => '1', ERROR => '0'),
8 => ( DATA => x"18", VALID => '1', ERROR => '0'),
9 => ( DATA => x"29", VALID => '1', ERROR => '0'),
10 => ( DATA => x"26", VALID => '1', ERROR => '0'),
11 => ( DATA => x"7c", VALID => '1', ERROR => '0'),
12 => ( DATA => x"08", VALID => '1', ERROR => '0'), --type 0800 IP
13 => ( DATA => x"00", VALID => '1', ERROR => '0'),
14 => ( DATA => x"45", VALID => '1', ERROR => '0'), -- IP HEADER
15 => ( DATA => x"00", VALID => '1', ERROR => '0'),
16 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- LENGTH
17 => ( DATA => x"22", VALID => '1', ERROR => '0'), -- LENGTH
18 => ( DATA => x"00", VALID => '1', ERROR => '0'),
19 => ( DATA => x"7a", VALID => '1', ERROR => '0'),
20 => ( DATA => x"00", VALID => '1', ERROR => '0'),
21 => ( DATA => x"00", VALID => '1', ERROR => '0'),
22 => ( DATA => x"80", VALID => '1', ERROR => '0'),
23 => ( DATA => x"11", VALID => '1', ERROR => '0'), -- Proto: UDP
24 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- IP HEADER CS
25 => ( DATA => x"00", VALID => '1', ERROR => '0'),
26 => ( DATA => x"c0", VALID => '1', ERROR => '0'), -- SRC IP
27 => ( DATA => x"a8", VALID => '1', ERROR => '0'),
28 => ( DATA => x"05", VALID => '1', ERROR => '0'),
29 => ( DATA => x"01", VALID => '1', ERROR => '0'),
30 => ( DATA => x"c0", VALID => '1', ERROR => '0'), -- DEST IP
31 => ( DATA => x"a8", VALID => '1', ERROR => '0'),
32 => ( DATA => x"04", VALID => '1', ERROR => '0'),
33 => ( DATA => x"17", VALID => '1', ERROR => '0'),
34 => ( DATA => x"f4", VALID => '1', ERROR => '0'), -- SRC PORT
35 => ( DATA => x"9a", VALID => '1', ERROR => '0'),
36 => ( DATA => x"D8", VALID => '1', ERROR => '0'), -- DST PORT
37 => ( DATA => x"20", VALID => '1', ERROR => '0'),
38 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- LENGTH
39 => ( DATA => x"0e", VALID => '1', ERROR => '0'), -- LENGTH
40 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- UDP CS
41 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- UDP CS
42 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Type=ERR_RD
43 => ( DATA => x"0c", VALID => '1', ERROR => '0'),
44 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- ID=11
45 => ( DATA => x"0b", VALID => '1', ERROR => '0'),
46 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- DATA_LENGTH=0
47 => ( DATA => x"00", VALID => '1', ERROR => '0'),
48 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
49 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
50 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
51 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
52 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
53 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
54 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
55 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
56 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
57 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
58 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
59 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
others => ( DATA => x"00", VALID => '0', ERROR => '0')),
-- No error in this frame
bad_frame => false),
-------------
-- Frame 7 after pause
-- Send read next error
-------------
C_PAUSE_AFTER_FRAME + 7 => (
columns => (
0 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Dest Adr
1 => ( DATA => x"23", VALID => '1', ERROR => '0'),
2 => ( DATA => x"20", VALID => '1', ERROR => '0'),
3 => ( DATA => x"21", VALID => '1', ERROR => '0'),
4 => ( DATA => x"22", VALID => '1', ERROR => '0'),
5 => ( DATA => x"23", VALID => '1', ERROR => '0'),
6 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Source Address
7 => ( DATA => x"23", VALID => '1', ERROR => '0'),
8 => ( DATA => x"18", VALID => '1', ERROR => '0'),
9 => ( DATA => x"29", VALID => '1', ERROR => '0'),
10 => ( DATA => x"26", VALID => '1', ERROR => '0'),
11 => ( DATA => x"7c", VALID => '1', ERROR => '0'),
12 => ( DATA => x"08", VALID => '1', ERROR => '0'), --type 0800 IP
13 => ( DATA => x"00", VALID => '1', ERROR => '0'),
14 => ( DATA => x"45", VALID => '1', ERROR => '0'), -- IP HEADER
15 => ( DATA => x"00", VALID => '1', ERROR => '0'),
16 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- LENGTH
17 => ( DATA => x"22", VALID => '1', ERROR => '0'), -- LENGTH
18 => ( DATA => x"00", VALID => '1', ERROR => '0'),
19 => ( DATA => x"7a", VALID => '1', ERROR => '0'),
20 => ( DATA => x"00", VALID => '1', ERROR => '0'),
21 => ( DATA => x"00", VALID => '1', ERROR => '0'),
22 => ( DATA => x"80", VALID => '1', ERROR => '0'),
23 => ( DATA => x"11", VALID => '1', ERROR => '0'), -- Proto: UDP
24 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- IP HEADER CS
25 => ( DATA => x"00", VALID => '1', ERROR => '0'),
26 => ( DATA => x"c0", VALID => '1', ERROR => '0'), -- SRC IP
27 => ( DATA => x"a8", VALID => '1', ERROR => '0'),
28 => ( DATA => x"05", VALID => '1', ERROR => '0'),
29 => ( DATA => x"01", VALID => '1', ERROR => '0'),
30 => ( DATA => x"c0", VALID => '1', ERROR => '0'), -- DEST IP
31 => ( DATA => x"a8", VALID => '1', ERROR => '0'),
32 => ( DATA => x"04", VALID => '1', ERROR => '0'),
33 => ( DATA => x"17", VALID => '1', ERROR => '0'),
34 => ( DATA => x"f4", VALID => '1', ERROR => '0'), -- SRC PORT
35 => ( DATA => x"9a", VALID => '1', ERROR => '0'),
36 => ( DATA => x"D8", VALID => '1', ERROR => '0'), -- DST PORT
37 => ( DATA => x"20", VALID => '1', ERROR => '0'),
38 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- LENGTH
39 => ( DATA => x"0e", VALID => '1', ERROR => '0'), -- LENGTH
40 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- UDP CS
41 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- UDP CS
42 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Type=getERR
43 => ( DATA => x"0b", VALID => '1', ERROR => '0'),
44 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- ID=12
45 => ( DATA => x"0c", VALID => '1', ERROR => '0'),
46 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- DATA_LENGTH=0
47 => ( DATA => x"00", VALID => '1', ERROR => '0'),
48 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
49 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
50 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
51 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
52 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
53 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
54 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
55 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
56 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
57 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
58 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
59 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
others => ( DATA => x"00", VALID => '0', ERROR => '0')),
-- No error in this frame
bad_frame => false),
-------------
-- Frame 1 after 1. pause
-- Send write restart
-------------
C_PAUSE2_AFTER_FRAME + 1 => (
columns => (
0 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Dest Adr
1 => ( DATA => x"23", VALID => '1', ERROR => '0'),
2 => ( DATA => x"20", VALID => '1', ERROR => '0'),
3 => ( DATA => x"21", VALID => '1', ERROR => '0'),
4 => ( DATA => x"22", VALID => '1', ERROR => '0'),
5 => ( DATA => x"23", VALID => '1', ERROR => '0'),
6 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Source Address
7 => ( DATA => x"23", VALID => '1', ERROR => '0'),
8 => ( DATA => x"18", VALID => '1', ERROR => '0'),
9 => ( DATA => x"29", VALID => '1', ERROR => '0'),
10 => ( DATA => x"26", VALID => '1', ERROR => '0'),
11 => ( DATA => x"7c", VALID => '1', ERROR => '0'),
12 => ( DATA => x"08", VALID => '1', ERROR => '0'), --type 0800 IP
13 => ( DATA => x"00", VALID => '1', ERROR => '0'),
14 => ( DATA => x"45", VALID => '1', ERROR => '0'), -- IP HEADER
15 => ( DATA => x"00", VALID => '1', ERROR => '0'),
16 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- LENGTH
17 => ( DATA => x"22", VALID => '1', ERROR => '0'), -- LENGTH
18 => ( DATA => x"00", VALID => '1', ERROR => '0'),
19 => ( DATA => x"7a", VALID => '1', ERROR => '0'),
20 => ( DATA => x"00", VALID => '1', ERROR => '0'),
21 => ( DATA => x"00", VALID => '1', ERROR => '0'),
22 => ( DATA => x"80", VALID => '1', ERROR => '0'),
23 => ( DATA => x"11", VALID => '1', ERROR => '0'), -- Proto: UDP
24 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- IP HEADER CS
25 => ( DATA => x"00", VALID => '1', ERROR => '0'),
26 => ( DATA => x"c0", VALID => '1', ERROR => '0'), -- SRC IP
27 => ( DATA => x"a8", VALID => '1', ERROR => '0'),
28 => ( DATA => x"05", VALID => '1', ERROR => '0'),
29 => ( DATA => x"01", VALID => '1', ERROR => '0'),
30 => ( DATA => x"c0", VALID => '1', ERROR => '0'), -- DEST IP
31 => ( DATA => x"a8", VALID => '1', ERROR => '0'),
32 => ( DATA => x"04", VALID => '1', ERROR => '0'),
33 => ( DATA => x"17", VALID => '1', ERROR => '0'),
34 => ( DATA => x"f4", VALID => '1', ERROR => '0'), -- SRC PORT
35 => ( DATA => x"9a", VALID => '1', ERROR => '0'),
36 => ( DATA => x"D8", VALID => '1', ERROR => '0'), -- DST PORT
37 => ( DATA => x"20", VALID => '1', ERROR => '0'),
38 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- LENGTH
39 => ( DATA => x"0e", VALID => '1', ERROR => '0'), -- LENGTH
40 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- UDP CS
41 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- UDP CS
42 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Type=RESET
43 => ( DATA => x"07", VALID => '1', ERROR => '0'),
44 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- ID=6
45 => ( DATA => x"06", VALID => '1', ERROR => '0'),
46 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- DATA_LENGTH=0
47 => ( DATA => x"00", VALID => '1', ERROR => '0'),
48 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
49 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
50 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
51 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
52 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
53 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
54 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
55 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
56 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
57 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
58 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
59 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
others => ( DATA => x"00", VALID => '0', ERROR => '0')),
-- No error in this frame
bad_frame => false),
-------------
-- Frame 1 after 2. pause
-- Send read next error
-------------
C_PAUSE3_AFTER_FRAME + 1 => (
columns => (
0 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Dest Adr
1 => ( DATA => x"23", VALID => '1', ERROR => '0'),
2 => ( DATA => x"20", VALID => '1', ERROR => '0'),
3 => ( DATA => x"21", VALID => '1', ERROR => '0'),
4 => ( DATA => x"22", VALID => '1', ERROR => '0'),
5 => ( DATA => x"23", VALID => '1', ERROR => '0'),
6 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Source Address
7 => ( DATA => x"23", VALID => '1', ERROR => '0'),
8 => ( DATA => x"18", VALID => '1', ERROR => '0'),
9 => ( DATA => x"29", VALID => '1', ERROR => '0'),
10 => ( DATA => x"26", VALID => '1', ERROR => '0'),
11 => ( DATA => x"7c", VALID => '1', ERROR => '0'),
12 => ( DATA => x"08", VALID => '1', ERROR => '0'), --type 0800 IP
13 => ( DATA => x"00", VALID => '1', ERROR => '0'),
14 => ( DATA => x"45", VALID => '1', ERROR => '0'), -- IP HEADER
15 => ( DATA => x"00", VALID => '1', ERROR => '0'),
16 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- LENGTH
17 => ( DATA => x"22", VALID => '1', ERROR => '0'), -- LENGTH
18 => ( DATA => x"00", VALID => '1', ERROR => '0'),
19 => ( DATA => x"7a", VALID => '1', ERROR => '0'),
20 => ( DATA => x"00", VALID => '1', ERROR => '0'),
21 => ( DATA => x"00", VALID => '1', ERROR => '0'),
22 => ( DATA => x"80", VALID => '1', ERROR => '0'),
23 => ( DATA => x"11", VALID => '1', ERROR => '0'), -- Proto: UDP
24 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- IP HEADER CS
25 => ( DATA => x"00", VALID => '1', ERROR => '0'),
26 => ( DATA => x"c0", VALID => '1', ERROR => '0'), -- SRC IP
27 => ( DATA => x"a8", VALID => '1', ERROR => '0'),
28 => ( DATA => x"05", VALID => '1', ERROR => '0'),
29 => ( DATA => x"01", VALID => '1', ERROR => '0'),
30 => ( DATA => x"c0", VALID => '1', ERROR => '0'), -- DEST IP
31 => ( DATA => x"a8", VALID => '1', ERROR => '0'),
32 => ( DATA => x"04", VALID => '1', ERROR => '0'),
33 => ( DATA => x"17", VALID => '1', ERROR => '0'),
34 => ( DATA => x"f4", VALID => '1', ERROR => '0'), -- SRC PORT
35 => ( DATA => x"9a", VALID => '1', ERROR => '0'),
36 => ( DATA => x"D8", VALID => '1', ERROR => '0'), -- DST PORT
37 => ( DATA => x"20", VALID => '1', ERROR => '0'),
38 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- LENGTH
39 => ( DATA => x"0e", VALID => '1', ERROR => '0'), -- LENGTH
40 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- UDP CS
41 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- UDP CS
42 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Type=getERR
43 => ( DATA => x"0b", VALID => '1', ERROR => '0'),
44 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- ID=10
45 => ( DATA => x"0a", VALID => '1', ERROR => '0'),
46 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- DATA_LENGTH=0
47 => ( DATA => x"00", VALID => '1', ERROR => '0'),
48 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
49 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
50 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
51 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
52 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
53 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
54 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
55 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
56 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
57 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
58 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
59 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
others => ( DATA => x"00", VALID => '0', ERROR => '0')),
-- No error in this frame
bad_frame => false),
-------------
-- Frame 2 after 2. pause
-- Send read next error
-------------
C_PAUSE3_AFTER_FRAME + 2 => (
columns => (
0 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Dest Adr
1 => ( DATA => x"23", VALID => '1', ERROR => '0'),
2 => ( DATA => x"20", VALID => '1', ERROR => '0'),
3 => ( DATA => x"21", VALID => '1', ERROR => '0'),
4 => ( DATA => x"22", VALID => '1', ERROR => '0'),
5 => ( DATA => x"23", VALID => '1', ERROR => '0'),
6 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Source Address
7 => ( DATA => x"23", VALID => '1', ERROR => '0'),
8 => ( DATA => x"18", VALID => '1', ERROR => '0'),
9 => ( DATA => x"29", VALID => '1', ERROR => '0'),
10 => ( DATA => x"26", VALID => '1', ERROR => '0'),
11 => ( DATA => x"7c", VALID => '1', ERROR => '0'),
12 => ( DATA => x"08", VALID => '1', ERROR => '0'), --type 0800 IP
13 => ( DATA => x"00", VALID => '1', ERROR => '0'),
14 => ( DATA => x"45", VALID => '1', ERROR => '0'), -- IP HEADER
15 => ( DATA => x"00", VALID => '1', ERROR => '0'),
16 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- LENGTH
17 => ( DATA => x"22", VALID => '1', ERROR => '0'), -- LENGTH
18 => ( DATA => x"00", VALID => '1', ERROR => '0'),
19 => ( DATA => x"7a", VALID => '1', ERROR => '0'),
20 => ( DATA => x"00", VALID => '1', ERROR => '0'),
21 => ( DATA => x"00", VALID => '1', ERROR => '0'),
22 => ( DATA => x"80", VALID => '1', ERROR => '0'),
23 => ( DATA => x"11", VALID => '1', ERROR => '0'), -- Proto: UDP
24 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- IP HEADER CS
25 => ( DATA => x"00", VALID => '1', ERROR => '0'),
26 => ( DATA => x"c0", VALID => '1', ERROR => '0'), -- SRC IP
27 => ( DATA => x"a8", VALID => '1', ERROR => '0'),
28 => ( DATA => x"05", VALID => '1', ERROR => '0'),
29 => ( DATA => x"01", VALID => '1', ERROR => '0'),
30 => ( DATA => x"c0", VALID => '1', ERROR => '0'), -- DEST IP
31 => ( DATA => x"a8", VALID => '1', ERROR => '0'),
32 => ( DATA => x"04", VALID => '1', ERROR => '0'),
33 => ( DATA => x"17", VALID => '1', ERROR => '0'),
34 => ( DATA => x"f4", VALID => '1', ERROR => '0'), -- SRC PORT
35 => ( DATA => x"9a", VALID => '1', ERROR => '0'),
36 => ( DATA => x"D8", VALID => '1', ERROR => '0'), -- DST PORT
37 => ( DATA => x"20", VALID => '1', ERROR => '0'),
38 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- LENGTH
39 => ( DATA => x"0e", VALID => '1', ERROR => '0'), -- LENGTH
40 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- UDP CS
41 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- UDP CS
42 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Type=ERR_RD
43 => ( DATA => x"0c", VALID => '1', ERROR => '0'),
44 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- ID=11
45 => ( DATA => x"0b", VALID => '1', ERROR => '0'),
46 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- DATA_LENGTH=0
47 => ( DATA => x"00", VALID => '1', ERROR => '0'),
48 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
49 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
50 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
51 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
52 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
53 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
54 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
55 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
56 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
57 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
58 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
59 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
others => ( DATA => x"00", VALID => '0', ERROR => '0')),
-- No error in this frame
bad_frame => false),
-------------
-- Frame 2 after 3. pause
-- Send read next error
-------------
C_PAUSE3_AFTER_FRAME + 3 => (
columns => (
0 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Dest Adr
1 => ( DATA => x"23", VALID => '1', ERROR => '0'),
2 => ( DATA => x"20", VALID => '1', ERROR => '0'),
3 => ( DATA => x"21", VALID => '1', ERROR => '0'),
4 => ( DATA => x"22", VALID => '1', ERROR => '0'),
5 => ( DATA => x"23", VALID => '1', ERROR => '0'),
6 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Source Address
7 => ( DATA => x"23", VALID => '1', ERROR => '0'),
8 => ( DATA => x"18", VALID => '1', ERROR => '0'),
9 => ( DATA => x"29", VALID => '1', ERROR => '0'),
10 => ( DATA => x"26", VALID => '1', ERROR => '0'),
11 => ( DATA => x"7c", VALID => '1', ERROR => '0'),
12 => ( DATA => x"08", VALID => '1', ERROR => '0'), --type 0800 IP
13 => ( DATA => x"00", VALID => '1', ERROR => '0'),
14 => ( DATA => x"45", VALID => '1', ERROR => '0'), -- IP HEADER
15 => ( DATA => x"00", VALID => '1', ERROR => '0'),
16 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- LENGTH
17 => ( DATA => x"22", VALID => '1', ERROR => '0'), -- LENGTH
18 => ( DATA => x"00", VALID => '1', ERROR => '0'),
19 => ( DATA => x"7a", VALID => '1', ERROR => '0'),
20 => ( DATA => x"00", VALID => '1', ERROR => '0'),
21 => ( DATA => x"00", VALID => '1', ERROR => '0'),
22 => ( DATA => x"80", VALID => '1', ERROR => '0'),
23 => ( DATA => x"11", VALID => '1', ERROR => '0'), -- Proto: UDP
24 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- IP HEADER CS
25 => ( DATA => x"00", VALID => '1', ERROR => '0'),
26 => ( DATA => x"c0", VALID => '1', ERROR => '0'), -- SRC IP
27 => ( DATA => x"a8", VALID => '1', ERROR => '0'),
28 => ( DATA => x"05", VALID => '1', ERROR => '0'),
29 => ( DATA => x"01", VALID => '1', ERROR => '0'),
30 => ( DATA => x"c0", VALID => '1', ERROR => '0'), -- DEST IP
31 => ( DATA => x"a8", VALID => '1', ERROR => '0'),
32 => ( DATA => x"04", VALID => '1', ERROR => '0'),
33 => ( DATA => x"17", VALID => '1', ERROR => '0'),
34 => ( DATA => x"f4", VALID => '1', ERROR => '0'), -- SRC PORT
35 => ( DATA => x"9a", VALID => '1', ERROR => '0'),
36 => ( DATA => x"D8", VALID => '1', ERROR => '0'), -- DST PORT
37 => ( DATA => x"20", VALID => '1', ERROR => '0'),
38 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- LENGTH
39 => ( DATA => x"0e", VALID => '1', ERROR => '0'), -- LENGTH
40 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- UDP CS
41 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- UDP CS
42 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Type=getERR
43 => ( DATA => x"0b", VALID => '1', ERROR => '0'),
44 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- ID=10
45 => ( DATA => x"0a", VALID => '1', ERROR => '0'),
46 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- DATA_LENGTH=0
47 => ( DATA => x"00", VALID => '1', ERROR => '0'),
48 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
49 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
50 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
51 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
52 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
53 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
54 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
55 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
56 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
57 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
58 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
59 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
others => ( DATA => x"00", VALID => '0', ERROR => '0')),
-- No error in this frame
bad_frame => false),
-------------
-- Frame 4 after 2. pause
-- Send read next error
-------------
C_PAUSE3_AFTER_FRAME + 4 => (
columns => (
0 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Dest Adr
1 => ( DATA => x"23", VALID => '1', ERROR => '0'),
2 => ( DATA => x"20", VALID => '1', ERROR => '0'),
3 => ( DATA => x"21", VALID => '1', ERROR => '0'),
4 => ( DATA => x"22", VALID => '1', ERROR => '0'),
5 => ( DATA => x"23", VALID => '1', ERROR => '0'),
6 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Source Address
7 => ( DATA => x"23", VALID => '1', ERROR => '0'),
8 => ( DATA => x"18", VALID => '1', ERROR => '0'),
9 => ( DATA => x"29", VALID => '1', ERROR => '0'),
10 => ( DATA => x"26", VALID => '1', ERROR => '0'),
11 => ( DATA => x"7c", VALID => '1', ERROR => '0'),
12 => ( DATA => x"08", VALID => '1', ERROR => '0'), --type 0800 IP
13 => ( DATA => x"00", VALID => '1', ERROR => '0'),
14 => ( DATA => x"45", VALID => '1', ERROR => '0'), -- IP HEADER
15 => ( DATA => x"00", VALID => '1', ERROR => '0'),
16 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- LENGTH
17 => ( DATA => x"22", VALID => '1', ERROR => '0'), -- LENGTH
18 => ( DATA => x"00", VALID => '1', ERROR => '0'),
19 => ( DATA => x"7a", VALID => '1', ERROR => '0'),
20 => ( DATA => x"00", VALID => '1', ERROR => '0'),
21 => ( DATA => x"00", VALID => '1', ERROR => '0'),
22 => ( DATA => x"80", VALID => '1', ERROR => '0'),
23 => ( DATA => x"11", VALID => '1', ERROR => '0'), -- Proto: UDP
24 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- IP HEADER CS
25 => ( DATA => x"00", VALID => '1', ERROR => '0'),
26 => ( DATA => x"c0", VALID => '1', ERROR => '0'), -- SRC IP
27 => ( DATA => x"a8", VALID => '1', ERROR => '0'),
28 => ( DATA => x"05", VALID => '1', ERROR => '0'),
29 => ( DATA => x"01", VALID => '1', ERROR => '0'),
30 => ( DATA => x"c0", VALID => '1', ERROR => '0'), -- DEST IP
31 => ( DATA => x"a8", VALID => '1', ERROR => '0'),
32 => ( DATA => x"04", VALID => '1', ERROR => '0'),
33 => ( DATA => x"17", VALID => '1', ERROR => '0'),
34 => ( DATA => x"f4", VALID => '1', ERROR => '0'), -- SRC PORT
35 => ( DATA => x"9a", VALID => '1', ERROR => '0'),
36 => ( DATA => x"D8", VALID => '1', ERROR => '0'), -- DST PORT
37 => ( DATA => x"20", VALID => '1', ERROR => '0'),
38 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- LENGTH
39 => ( DATA => x"0e", VALID => '1', ERROR => '0'), -- LENGTH
40 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- UDP CS
41 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- UDP CS
42 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Type=ERR_RD
43 => ( DATA => x"0c", VALID => '1', ERROR => '0'),
44 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- ID=11
45 => ( DATA => x"0b", VALID => '1', ERROR => '0'),
46 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- DATA_LENGTH=0
47 => ( DATA => x"00", VALID => '1', ERROR => '0'),
48 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
49 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
50 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
51 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
52 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
53 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
54 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
55 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
56 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
57 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
58 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
59 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
others => ( DATA => x"00", VALID => '0', ERROR => '0')),
-- No error in this frame
bad_frame => false),
-------------
-- Frame 5 after pause2
-- Send read next error
-------------
C_PAUSE3_AFTER_FRAME + 5 => (
columns => (
0 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Dest Adr
1 => ( DATA => x"23", VALID => '1', ERROR => '0'),
2 => ( DATA => x"20", VALID => '1', ERROR => '0'),
3 => ( DATA => x"21", VALID => '1', ERROR => '0'),
4 => ( DATA => x"22", VALID => '1', ERROR => '0'),
5 => ( DATA => x"23", VALID => '1', ERROR => '0'),
6 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Source Address
7 => ( DATA => x"23", VALID => '1', ERROR => '0'),
8 => ( DATA => x"18", VALID => '1', ERROR => '0'),
9 => ( DATA => x"29", VALID => '1', ERROR => '0'),
10 => ( DATA => x"26", VALID => '1', ERROR => '0'),
11 => ( DATA => x"7c", VALID => '1', ERROR => '0'),
12 => ( DATA => x"08", VALID => '1', ERROR => '0'), --type 0800 IP
13 => ( DATA => x"00", VALID => '1', ERROR => '0'),
14 => ( DATA => x"45", VALID => '1', ERROR => '0'), -- IP HEADER
15 => ( DATA => x"00", VALID => '1', ERROR => '0'),
16 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- LENGTH
17 => ( DATA => x"22", VALID => '1', ERROR => '0'), -- LENGTH
18 => ( DATA => x"00", VALID => '1', ERROR => '0'),
19 => ( DATA => x"7a", VALID => '1', ERROR => '0'),
20 => ( DATA => x"00", VALID => '1', ERROR => '0'),
21 => ( DATA => x"00", VALID => '1', ERROR => '0'),
22 => ( DATA => x"80", VALID => '1', ERROR => '0'),
23 => ( DATA => x"11", VALID => '1', ERROR => '0'), -- Proto: UDP
24 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- IP HEADER CS
25 => ( DATA => x"00", VALID => '1', ERROR => '0'),
26 => ( DATA => x"c0", VALID => '1', ERROR => '0'), -- SRC IP
27 => ( DATA => x"a8", VALID => '1', ERROR => '0'),
28 => ( DATA => x"05", VALID => '1', ERROR => '0'),
29 => ( DATA => x"01", VALID => '1', ERROR => '0'),
30 => ( DATA => x"c0", VALID => '1', ERROR => '0'), -- DEST IP
31 => ( DATA => x"a8", VALID => '1', ERROR => '0'),
32 => ( DATA => x"04", VALID => '1', ERROR => '0'),
33 => ( DATA => x"17", VALID => '1', ERROR => '0'),
34 => ( DATA => x"f4", VALID => '1', ERROR => '0'), -- SRC PORT
35 => ( DATA => x"9a", VALID => '1', ERROR => '0'),
36 => ( DATA => x"D8", VALID => '1', ERROR => '0'), -- DST PORT
37 => ( DATA => x"20", VALID => '1', ERROR => '0'),
38 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- LENGTH
39 => ( DATA => x"0e", VALID => '1', ERROR => '0'), -- LENGTH
40 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- UDP CS
41 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- UDP CS
42 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- Type=getERR
43 => ( DATA => x"0b", VALID => '1', ERROR => '0'),
44 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- ID=12
45 => ( DATA => x"0c", VALID => '1', ERROR => '0'),
46 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- DATA_LENGTH=0
47 => ( DATA => x"00", VALID => '1', ERROR => '0'),
48 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
49 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
50 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
51 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
52 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
53 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
54 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
55 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
56 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
57 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
58 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
59 => ( DATA => x"00", VALID => '1', ERROR => '0'), -- PADDING
others => ( DATA => x"00", VALID => '0', ERROR => '0')),
-- No error in this frame
bad_frame => false)
);
----------------------------------------------------------------------
-- CRC engine
----------------------------------------------------------------------
function calc_crc (data : in std_logic_vector;
fcs : in std_logic_vector)
return std_logic_vector is
variable crc : std_logic_vector(31 downto 0);
variable crc_feedback : std_logic;
begin
crc := not fcs;
for I in 0 to 7 loop
crc_feedback := crc(0) xor data(I);
crc(4 downto 0) := crc(5 downto 1);
crc(5) := crc(6) xor crc_feedback;
crc(7 downto 6) := crc(8 downto 7);
crc(8) := crc(9) xor crc_feedback;
crc(9) := crc(10) xor crc_feedback;
crc(14 downto 10) := crc(15 downto 11);
crc(15) := crc(16) xor crc_feedback;
crc(18 downto 16) := crc(19 downto 17);
crc(19) := crc(20) xor crc_feedback;
crc(20) := crc(21) xor crc_feedback;
crc(21) := crc(22) xor crc_feedback;
crc(22) := crc(23);
crc(23) := crc(24) xor crc_feedback;
crc(24) := crc(25) xor crc_feedback;
crc(25) := crc(26);
crc(26) := crc(27) xor crc_feedback;
crc(27) := crc(28) xor crc_feedback;
crc(28) := crc(29);
crc(29) := crc(30) xor crc_feedback;
crc(30) := crc(31) xor crc_feedback;
crc(31) := crc_feedback;
end loop;
-- return the CRC result
return not crc;
end calc_crc;
-- Delay to provide setup and hold timing at the GMII/MII.
constant dly : time := 2 ns;
-- Testbench signals
signal mii_tx_clk_int : std_logic := '0';
signal mii_tx_clk100 : std_logic := '0';
signal mii_tx_clk10 : std_logic := '0';
signal gmii_rx_clk_int : std_logic := '0';
signal gmii_rx_clk1000 : std_logic := '0';
signal gmii_rx_clk100 : std_logic := '0';
signal gmii_rx_clk10 : std_logic := '0';
-- Testbench control signals
signal current_speed : string(1 to 6);
signal clkmux_en_100 : std_logic := '0';
signal clkmux_en_10 : std_logic := '0';
begin -- behavioral
-- Currently not used in this testbench.
gmii_col <= '0';
gmii_crs <= '0';
mii_tx_clk <= mii_tx_clk_int;
----------------------------------------------------------------------
-- gmii_rx_clk clock driver
----------------------------------------------------------------------
-- Drives gmii_rx_clk at 125 MHz for 1000Mb/s operation
p_gmii_rx_clk1000 : process
begin
gmii_rx_clk_int <= '0';
wait for 20 ns;
loop
wait for 4 ns;
gmii_rx_clk_int <= '1';
wait for 4 ns;
gmii_rx_clk_int <= '0';
end loop;
end process p_gmii_rx_clk1000;
gmii_rx_clk <= gmii_rx_clk_int;
----------------------------------------------------------------------
-- Simulus process
------------------
-- Send four frames through the MAC and Design Example
-- -- frame 0 = minimum length frame
-- -- frame 1 = type frame
-- -- frame 2 = errored frame
-- -- frame 3 = padded frame
----------------------------------------------------------------------
p_stimulus : process
variable current_col : natural := 0; -- Column counter within frame
variable fcs : std_logic_vector(31 downto 0);
variable frm_high : natural;
variable frm_low : natural;
begin
-- Initialise GMII
gmii_rxd <= "00000000";
gmii_rx_dv <= '0';
gmii_rx_er <= '0';
-- Initialize clock mux enables
clkmux_en_100 <= '0';
clkmux_en_10 <= '0';
-- Wait for the configuration to initialise the MAC
wait until configuration_busy;
wait until not configuration_busy;
current_speed <= "1gig ";
clkmux_en_100 <= '0';
clkmux_en_10 <= '0';
------------------------------------
-- Send frames at 1Gb/s speed
------------------------------------
wait until gmii_rx_clk_int'event and gmii_rx_clk_int = '1';
frm_low := 0;
frm_high := C_PAUSE_AFTER_FRAME;
for i in 1 to 4 loop
for current_frame in frm_low to frm_high loop
assert false
report "EMAC: Sending Frame " & integer'image(current_frame) & " at 1Gb/s" & cr
severity note;
-- Adding the preamble field
for j in 0 to 7 loop
gmii_rxd <= "01010101" after dly;
gmii_rx_dv <= '1' after dly;
gmii_rx_er <= '0' after dly;
wait until gmii_rx_clk_int'event and gmii_rx_clk_int = '1';
end loop;
-- Adding the Start of Frame Delimiter (SFD)
gmii_rxd <= "11010101" after dly;
gmii_rx_dv <= '1' after dly;
wait until gmii_rx_clk_int'event and gmii_rx_clk_int = '1';
-- Sending the MAC frame
fcs := (others => '0'); -- reset the FCS field
current_col := 0;
gmii_rxd <= to_stdlogicvector(frame_data(current_frame).columns(current_col).data) after dly;
fcs := calc_crc(to_stdlogicvector(frame_data(current_frame).columns(current_col).data), fcs);
gmii_rx_dv <= to_stdUlogic(frame_data(current_frame).columns(current_col).valid) after dly;
gmii_rx_er <= to_stdUlogic(frame_data(current_frame).columns(current_col).error) after dly;
wait until gmii_rx_clk_int'event and gmii_rx_clk_int = '1';
current_col := current_col + 1;
-- loop over columns in frame.
while frame_data(current_frame).columns(current_col).valid /= '0' loop
-- send one column of data
gmii_rxd <= to_stdlogicvector(frame_data(current_frame).columns(current_col).data) after dly;
fcs := calc_crc(to_stdlogicvector(frame_data(current_frame).columns(current_col).data), fcs);
gmii_rx_dv <= to_stdUlogic(frame_data(current_frame).columns(current_col).valid) after dly;
gmii_rx_er <= to_stdUlogic(frame_data(current_frame).columns(current_col).error) after dly;
current_col := current_col + 1;
wait until gmii_rx_clk_int'event and gmii_rx_clk_int = '1'; -- wait for next clock tick
end loop;
-- Send the FCS.
for j in 0 to 3 loop
gmii_rxd <= fcs(((8*j)+7) downto (8*j)) after dly;
--gmii_rxd <= x"00" after dly;
gmii_rx_dv <= '1' after dly;
gmii_rx_er <= '0' after dly;
wait until gmii_rx_clk_int'event and gmii_rx_clk_int = '1'; -- wait for next clock tick
end loop;
-- Clear the data lines.
gmii_rxd <= (others => '0') after dly;
gmii_rx_dv <= '0' after dly;
gmii_rx_er <= '0' after dly;
-- Adding the minimum Interframe gap for a receiver (8 idles)
for j in 0 to 7 loop
wait until gmii_rx_clk_int'event and gmii_rx_clk_int = '1';
end loop;
end loop; -- current_frame
-- wait for next frame burst
if i = 1 then
for j in 0 to C_PAUSE_CYCLES loop
wait until gmii_rx_clk_int'event and gmii_rx_clk_int = '1';
end loop;
frm_low := C_PAUSE_AFTER_FRAME + 1;
frm_high := C_PAUSE2_AFTER_FRAME;
elsif i = 2 then
for j in 0 to C_PAUSE2_CYCLES loop
wait until gmii_rx_clk_int'event and gmii_rx_clk_int = '1';
end loop;
frm_low := C_PAUSE2_AFTER_FRAME + 1;
frm_high := C_PAUSE3_AFTER_FRAME;
else
for j in 0 to C_PAUSE3_CYCLES loop
wait until gmii_rx_clk_int'event and gmii_rx_clk_int = '1';
end loop;
frm_low := C_PAUSE3_AFTER_FRAME + 1;
frm_high := frame_data'high;
end if;
end loop; -- second frame burst
-- Our work here is done
wait;
end process p_stimulus;
----------------------------------------------------------------------
-- Monitor process
------------------
-- This process checks the data coming out of the
-- transmitter to make sure that it matches that inserted into the
-- receiver.
-- -- frame 0 = minimum length frame
-- -- frame 1 = type frame
-- -- frame 2 = errored frame
-- -- frame 3 = padded frame
--
-- Repeated for all 3 speeds.
----------------------------------------------------------------------
p_monitor : process
variable f : frame_typ; -- temporary frame variable
variable current_col : natural := 0; -- Column counter
variable current_frame : natural := 0;
variable fcs : std_logic_vector(31 downto 0);
begin -- process p_monitor
monitor_finished_1g <= false;
monitor_finished_100m <= false;
monitor_finished_10m <= false;
-- first, get synced up with the TX clock
wait until gmii_tx_clk'event and gmii_tx_clk = '1';
wait until gmii_tx_clk'event and gmii_tx_clk = '1';
------------------------------------
-- Compare the frames at 1Gb/s speed
------------------------------------
wait until gmii_tx_clk'event and gmii_tx_clk = '1';
-- loop over all the frames in the stimulus vector
loop
current_col := 0;
-- If the current frame had an error inserted then it would have been
-- dropped by the FIFO in the design example. Therefore move
-- immediately on to the next frame.
while frame_data(current_frame).bad_frame loop
current_frame := current_frame + 1;
if current_frame = frame_data'high + 1 then
exit;
end if;
end loop;
-- There are only 4 frames in this test.
if current_frame = frame_data'high + 1 then
exit;
end if;
-- Parse over the preamble field
while gmii_tx_en /= '1' or gmii_txd = "01010101" loop
wait until gmii_tx_clk'event and gmii_tx_clk = '1';
end loop;
assert false
report "EMAC: Comparing Frame " & integer'image(current_frame) & " at 1Gb/s" & cr
severity note;
-- Parse over the Start of Frame Delimiter (SFD)
if (gmii_txd /= "11010101") then
assert false
report "EMAC: SFD not present" & cr
severity error;
end if;
fcs := (others => '0'); -- reset the FCS field
wait until gmii_tx_clk'event and gmii_tx_clk = '1';
-- frame has started, loop over columns of frame
while ((frame_data(current_frame).columns(current_col).valid)='1') loop
assert (gmii_tx_en = to_stdulogic(frame_data(current_frame).columns(current_col).valid))
report "EMAC: gmii_tx_en incorrect" & cr
severity error;
if gmii_tx_en = '1' then
-- The transmitted Destination Address was the Source Address of the injected frame
if current_col < 6 then
fcs := calc_crc(to_stdlogicvector(frame_data(current_frame).columns(current_col+6).data), fcs);
assert (gmii_txd(7 downto 0) =
to_stdlogicvector(frame_data(current_frame).columns(current_col+6).data(7 downto 0)))
report "EMAC: gmii_txd incorrect" & cr
severity error;
-- The transmitted Source Address was the Destination Address of the injected frame
elsif current_col >= 6 and current_col < 12 then
fcs := calc_crc(to_stdlogicvector(frame_data(current_frame).columns(current_col-6).data), fcs);
assert (gmii_txd(7 downto 0) =
to_stdlogicvector(frame_data(current_frame).columns(current_col-6).data(7 downto 0)))
report "EMAC: gmii_txd incorrect" & cr
severity error;
-- for remainder of frame
else
fcs := calc_crc(to_stdlogicvector(frame_data(current_frame).columns(current_col).data), fcs);
assert (gmii_txd(7 downto 0) =
to_stdlogicvector(frame_data(current_frame).columns(current_col).data(7 downto 0)))
report "EMAC: gmii_txd incorrect" & cr
severity error;
end if;
end if;
-- wait for next column of data
current_col := current_col + 1;
wait until gmii_tx_clk'event and gmii_tx_clk = '1';
end loop; -- while data valid
-- Check the FCS
-- Having checked all data columns, txd must contain FCS.
for j in 0 to 3 loop
assert (gmii_txd = fcs(((8*j)+7) downto (8*j)))
report "EMAC: gmii_txd incorrect during FCS field" & cr
severity error;
wait until gmii_tx_clk'event and gmii_tx_clk = '1';
end loop; -- j
-- move to the next frame
if current_frame = frame_data'high then
exit;
else
current_frame := current_frame + 1;
end if;
end loop;
monitor_finished_1g <= true;
-- Our work here is done
wait;
end process p_monitor;
end behavioral;
|
bsd-2-clause
|
nihospr01/OpenSpeechPlatform-UCSD
|
Firmware/FPGA/src/sr8_falling.vhd
|
1
|
996
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- 8-bit general purpose shift register (parallel-to-serial and/or serial-to-parallel)
-- Asynchronous reset, falling-edge clk
-- Shifts up (sin => pout(0) => pout(1) etc.)
-- If ld, pin is stored to internal register
-- Else if sh, register is shifted up 1 bit
-- pout is a copy of the internal register state
-- sout is just pout(7)
entity sr8_falling is
port(
clk, reset: in std_logic;
ld, sh: in std_logic;
pin: in std_logic_vector(7 downto 0);
pout: out std_logic_vector(7 downto 0);
sin: in std_logic;
sout: out std_logic
);
end entity;
architecture a of sr8_falling is
signal buf: std_logic_vector(7 downto 0);
begin
pout <= buf;
sout <= buf(7);
process(clk, reset) is begin
if reset = '1' then
buf <= (others => '0');
elsif falling_edge(clk) then
if ld = '1' then
buf <= pin;
elsif sh = '1' then
buf <= buf(6 downto 0) & sin;
end if;
end if;
end process;
end architecture;
|
bsd-2-clause
|
athalonis/CCL-Verification-Environment
|
src/vhdl/communication/udp_ip_stack/trunk/bench/vhdl/IP_complete_nomac_tb.vhd
|
1
|
17027
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:54:32 06/04/2011
-- Design Name:
-- Module Name: C:/Users/pjf/Documents/projects/fpga/xilinx/Network/ip1/IP_complete_nomac_tb.vhd
-- Project Name: ip1
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: IP_complete_nomac
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.axi.all;
use work.ipv4_types.all;
use work.arp_types.all;
ENTITY IP_complete_nomac_tb IS
END IP_complete_nomac_tb;
ARCHITECTURE behavior OF IP_complete_nomac_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT IP_complete_nomac
generic (
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr
ARP_TIMEOUT : integer := 60 -- ARP response timeout (s)
);
Port (
-- IP Layer signals
ip_tx_start : in std_logic;
ip_tx : in ipv4_tx_type; -- IP tx cxns
ip_tx_result : out std_logic_vector (1 downto 0); -- tx status (changes during transmission)
ip_tx_data_out_ready : out std_logic; -- indicates IP TX is ready to take data
ip_rx_start : out std_logic; -- indicates receipt of ip frame.
ip_rx : out ipv4_rx_type;
-- system signals
rx_clk : in STD_LOGIC;
tx_clk : in STD_LOGIC;
reset : in STD_LOGIC;
our_ip_address : in STD_LOGIC_VECTOR (31 downto 0);
our_mac_address : in std_logic_vector (47 downto 0);
control : in ip_control_type;
-- status signals
arp_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- count of arp pkts received
ip_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- number of IP pkts received for us
-- MAC Transmitter
mac_tx_tdata : out std_logic_vector(7 downto 0); -- data byte to tx
mac_tx_tvalid : out std_logic; -- tdata is valid
mac_tx_tready : in std_logic; -- mac is ready to accept data
mac_tx_tfirst : out std_logic; -- indicates first byte of frame
mac_tx_tlast : out std_logic; -- indicates last byte of frame
-- MAC Receiver
mac_rx_tdata : in std_logic_vector(7 downto 0); -- data byte received
mac_rx_tvalid : in std_logic; -- indicates tdata is valid
mac_rx_tready : out std_logic; -- tells mac that we are ready to take data
mac_rx_tlast : in std_logic -- indicates last byte of the trame
);
END COMPONENT;
--Inputs
signal ip_tx_start : std_logic := '0';
signal ip_tx : ipv4_tx_type;
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal our_ip_address : std_logic_vector(31 downto 0) := (others => '0');
signal our_mac_address : std_logic_vector(47 downto 0) := (others => '0');
signal mac_tx_tready : std_logic := '0';
signal mac_rx_tdata : std_logic_vector(7 downto 0) := (others => '0');
signal mac_rx_tvalid : std_logic := '0';
signal mac_rx_tlast : std_logic := '0';
signal control : ip_control_type;
--Outputs
signal ip_tx_result : std_logic_vector (1 downto 0); -- tx status (changes during transmission)
signal ip_tx_data_out_ready : std_logic; -- indicates IP TX is ready to take data
signal ip_rx_start : std_logic;
signal ip_rx : ipv4_rx_type;
signal arp_pkt_count : std_logic_vector(7 downto 0);
signal mac_tx_tdata : std_logic_vector(7 downto 0);
signal mac_tx_tvalid : std_logic;
signal mac_tx_tfirst : std_logic;
signal mac_tx_tlast : std_logic;
signal mac_rx_tready : std_logic;
-- Clock period definitions
constant clk_period : time := 8 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: IP_complete_nomac PORT MAP (
ip_tx_start => ip_tx_start,
ip_tx => ip_tx,
ip_tx_result => ip_tx_result,
ip_tx_data_out_ready => ip_tx_data_out_ready,
ip_rx_start => ip_rx_start,
ip_rx => ip_rx,
rx_clk => clk,
tx_clk => clk,
reset => reset,
our_ip_address => our_ip_address,
our_mac_address => our_mac_address,
control => control,
arp_pkt_count => arp_pkt_count,
mac_tx_tdata => mac_tx_tdata,
mac_tx_tvalid => mac_tx_tvalid,
mac_tx_tready => mac_tx_tready,
mac_tx_tfirst => mac_tx_tfirst,
mac_tx_tlast => mac_tx_tlast,
mac_rx_tdata => mac_rx_tdata,
mac_rx_tvalid => mac_rx_tvalid,
mac_rx_tready => mac_rx_tready,
mac_rx_tlast => mac_rx_tlast
);
-- Clock process definitions
clk_process :process
begin
clk <= '1';
wait for clk_period/2;
clk <= '0';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 80 ns;
our_ip_address <= x"c0a80509"; -- 192.168.5.9
our_mac_address <= x"002320212223";
control.arp_controls.clear_cache <= '0';
ip_tx_start <= '0';
mac_tx_tready <= '0';
reset <= '1';
wait for clk_period*10;
reset <= '0';
wait for clk_period*5;
-- check reset conditions
assert ip_tx_result = IPTX_RESULT_NONE report "ip_tx_result not initialised correctly on reset";
assert ip_tx_data_out_ready = '0' report "ip_tx_data_out_ready not initialised correctly on reset";
assert mac_tx_tvalid = '0' report "mac_tx_tvalid not initialised correctly on reset";
assert mac_tx_tlast = '0' report " mac_tx_tlast not initialised correctly on reset";
assert arp_pkt_count = x"00" report " arp_pkt_count not initialised correctly on reset";
assert ip_rx_start = '0' report "ip_rx_start not initialised correctly on reset";
assert ip_rx.hdr.is_valid = '0' report "ip_rx.hdr.is_valid not initialised correctly on reset";
assert ip_rx.hdr.protocol = x"00" report "ip_rx.hdr.protocol not initialised correctly on reset";
assert ip_rx.hdr.data_length = x"0000" report "ip_rx.hdr.data_length not initialised correctly on reset";
assert ip_rx.hdr.src_ip_addr = x"00000000" report "ip_rx.hdr.src_ip_addr not initialised correctly on reset";
assert ip_rx.hdr.num_frame_errors = x"00" report "ip_rx.hdr.num_frame_errors not initialised correctly on reset";
assert ip_rx.data.data_in = x"00" report "ip_rx.data.data_in not initialised correctly on reset";
assert ip_rx.data.data_in_valid = '0' report "ip_rx.data.data_in_valid not initialised correctly on reset";
assert ip_rx.data.data_in_last = '0' report "ip_rx.data.data_in_last not initialised correctly on reset";
-- insert stimulus here
------------
-- TEST 1 -- basic functional rx test with received ip pkt
------------
report "T1: Send an eth frame with IP pkt dst ip_address c0a80509, dst mac 002320212223";
mac_tx_tready <= '1';
mac_rx_tvalid <= '1';
-- dst MAC (bc)
mac_rx_tdata <= x"00"; wait for clk_period;
mac_rx_tdata <= x"23"; wait for clk_period;
mac_rx_tdata <= x"20"; wait for clk_period;
mac_rx_tdata <= x"21"; wait for clk_period;
mac_rx_tdata <= x"22"; wait for clk_period;
mac_rx_tdata <= x"23"; wait for clk_period;
-- src MAC
mac_rx_tdata <= x"00"; wait for clk_period;
mac_rx_tdata <= x"23"; wait for clk_period;
mac_rx_tdata <= x"18"; wait for clk_period;
mac_rx_tdata <= x"29"; wait for clk_period;
mac_rx_tdata <= x"26"; wait for clk_period;
mac_rx_tdata <= x"7c"; wait for clk_period;
-- type
mac_rx_tdata <= x"08"; wait for clk_period; -- IP pkt
mac_rx_tdata <= x"00"; wait for clk_period;
-- ver & HL / service type
mac_rx_tdata <= x"45"; wait for clk_period;
mac_rx_tdata <= x"00"; wait for clk_period;
-- total len
mac_rx_tdata <= x"00"; wait for clk_period;
mac_rx_tdata <= x"18"; wait for clk_period;
-- ID
mac_rx_tdata <= x"00"; wait for clk_period;
mac_rx_tdata <= x"00"; wait for clk_period;
-- flags & frag
mac_rx_tdata <= x"00"; wait for clk_period;
mac_rx_tdata <= x"00"; wait for clk_period;
-- TTL
mac_rx_tdata <= x"00"; wait for clk_period;
-- Protocol
mac_rx_tdata <= x"11"; wait for clk_period;
-- Header CKS
mac_rx_tdata <= x"00"; wait for clk_period;
mac_rx_tdata <= x"00"; wait for clk_period;
-- SRC IP
mac_rx_tdata <= x"c0"; wait for clk_period;
mac_rx_tdata <= x"a8"; wait for clk_period;
mac_rx_tdata <= x"05"; wait for clk_period;
mac_rx_tdata <= x"01"; wait for clk_period;
-- DST IP
mac_rx_tdata <= x"c0"; wait for clk_period;
mac_rx_tdata <= x"a8"; wait for clk_period;
mac_rx_tdata <= x"05"; wait for clk_period;
mac_rx_tdata <= x"09"; wait for clk_period;
-- user data
mac_rx_tdata <= x"24"; wait for clk_period;
-- since we are up to the user data stage, the header should be valid and the data_in_valid should be set
assert ip_rx.hdr.is_valid = '1' report "T1: ip_rx.hdr.is_valid not set";
assert ip_rx.hdr.protocol = x"11" report "T1: ip_rx.hdr.protocol not set correctly";
assert ip_rx.hdr.data_length = x"0004" report "T1: ip_rx.hdr.data_length not set correctly";
assert ip_rx.hdr.src_ip_addr = x"c0a80501" report "T1: ip_rx.hdr.src_ip_addr not set correctly";
assert ip_rx.hdr.num_frame_errors = x"00" report "T1: ip_rx.hdr.num_frame_errors not set correctly";
assert ip_rx.hdr.last_error_code = x"0" report "T1: ip_rx.hdr.last_error_code not set correctly";
assert ip_rx_start = '1' report "T1: ip_rx_start not set";
assert ip_rx.data.data_in_valid = '1' report "T1: ip_rx.data.data_in_valid not set";
mac_rx_tdata <= x"25"; wait for clk_period;
mac_rx_tdata <= x"26"; wait for clk_period;
mac_rx_tdata <= x"27"; mac_rx_tlast <= '1'; wait for clk_period;
assert ip_rx.data.data_in_last = '1' report "T1: ip_rx.data.data_in_last not set";
mac_rx_tdata <= x"00";
mac_rx_tlast <= '0';
mac_rx_tvalid <= '0';
wait for clk_period;
assert ip_rx.data.data_in_valid = '0' report "T1: ip_rx.data.data_in_valid not cleared";
assert ip_rx.data.data_in_last = '0' report "T1: ip_rx.data.data_in_last not cleared";
assert ip_rx.hdr.num_frame_errors = x"00" report "T1: ip_rx.hdr.num_frame_errors non zero at end of test";
assert ip_rx.hdr.last_error_code = x"0" report "T1: ip_rx.hdr.last_error_code indicates error at end of test";
assert ip_rx_start = '0' report "T1: ip_rx_start not cleared";
------------
-- TEST 2 -- respond with IP TX
------------
report "T2: respond with IP TX";
ip_tx.hdr.protocol <= x"35";
ip_tx.hdr.data_length <= x"0006";
ip_tx.hdr.dst_ip_addr <= x"c0123478";
ip_tx.data.data_out_valid <= '0';
ip_tx.data.data_out_last <= '0';
wait for clk_period;
ip_tx_start <= '1'; wait for clk_period;
ip_tx_start <= '0'; wait for clk_period;
assert ip_tx_result = IPTX_RESULT_SENDING report "T2: result should be IPTX_RESULT_SENDING";
wait for clk_period*2;
assert ip_tx_data_out_ready = '0' report "T2: IP data out ready asserted too early";
-- need to wait for ARP tx to complete
wait for clk_period*50;
assert mac_tx_tvalid = '0' report "T2: mac_tx_tvalid not cleared after ARP tx";
assert mac_tx_tlast = '0' report "T2: mac_tx_tlast not cleared after ARP tx";
-- now create the ARP response (rx)
-- Send the reply
-- Send an ARP reply: x"c0123478" has mac 02:12:03:23:04:54
mac_rx_tvalid <= '1';
-- dst MAC (bc)
mac_rx_tdata <= x"ff"; wait for clk_period;
mac_rx_tdata <= x"ff"; wait for clk_period;
mac_rx_tdata <= x"ff"; wait for clk_period;
mac_rx_tdata <= x"ff"; wait for clk_period;
mac_rx_tdata <= x"ff"; wait for clk_period;
mac_rx_tdata <= x"ff"; wait for clk_period;
-- src MAC
mac_rx_tdata <= x"02"; wait for clk_period;
mac_rx_tdata <= x"12"; wait for clk_period;
mac_rx_tdata <= x"03"; wait for clk_period;
mac_rx_tdata <= x"23"; wait for clk_period;
mac_rx_tdata <= x"04"; wait for clk_period;
mac_rx_tdata <= x"54"; wait for clk_period;
-- type
mac_rx_tdata <= x"08"; wait for clk_period;
mac_rx_tdata <= x"06"; wait for clk_period;
-- HW type
mac_rx_tdata <= x"00"; wait for clk_period;
mac_rx_tdata <= x"01"; wait for clk_period;
-- Protocol type
mac_rx_tdata <= x"08"; wait for clk_period;
mac_rx_tdata <= x"00"; wait for clk_period;
-- HW size
mac_rx_tdata <= x"06"; wait for clk_period;
-- protocol size
mac_rx_tdata <= x"04"; wait for clk_period;
-- Opcode
mac_rx_tdata <= x"00"; wait for clk_period;
mac_rx_tdata <= x"02"; wait for clk_period;
-- Sender MAC
mac_rx_tdata <= x"02"; wait for clk_period;
mac_rx_tdata <= x"12"; wait for clk_period;
mac_rx_tdata <= x"03"; wait for clk_period;
mac_rx_tdata <= x"23"; wait for clk_period;
mac_rx_tdata <= x"04"; wait for clk_period;
mac_rx_tdata <= x"54"; wait for clk_period;
-- Sender IP
mac_rx_tdata <= x"c0"; wait for clk_period;
mac_rx_tdata <= x"12"; wait for clk_period;
mac_rx_tdata <= x"34"; wait for clk_period;
mac_rx_tdata <= x"78"; wait for clk_period;
-- Target MAC
mac_rx_tdata <= x"00"; wait for clk_period;
mac_rx_tdata <= x"23"; wait for clk_period;
mac_rx_tdata <= x"20"; wait for clk_period;
mac_rx_tdata <= x"21"; wait for clk_period;
mac_rx_tdata <= x"22"; wait for clk_period;
mac_rx_tdata <= x"23"; wait for clk_period;
-- Target IP
mac_rx_tdata <= x"c0"; wait for clk_period;
mac_rx_tdata <= x"a8"; wait for clk_period;
mac_rx_tdata <= x"05"; wait for clk_period;
mac_rx_tdata <= x"09"; wait for clk_period;
mac_rx_tdata <= x"00"; wait for clk_period;
mac_rx_tdata <= x"00"; wait for clk_period;
mac_rx_tdata <= x"00"; wait for clk_period;
mac_rx_tlast <= '1';
mac_rx_tdata <= x"00"; wait for clk_period;
mac_rx_tlast <= '0';
mac_rx_tvalid <= '0';
wait until ip_tx_data_out_ready = '1';
-- start to tx IP data
ip_tx.data.data_out_valid <= '1';
ip_tx.data.data_out <= x"56"; wait for clk_period;
ip_tx.data.data_out <= x"57"; wait for clk_period;
ip_tx.data.data_out <= x"58"; wait for clk_period;
ip_tx.data.data_out <= x"59"; wait for clk_period;
ip_tx.data.data_out <= x"5a"; wait for clk_period;
ip_tx.data.data_out <= x"5b";
ip_tx.data.data_out_last <= '1';
wait for clk_period;
assert mac_tx_tlast = '1' report "T2: mac_tx_tlast not set on last byte";
wait for clk_period;
ip_tx.data.data_out_valid <= '0';
ip_tx.data.data_out_last <= '0';
wait for clk_period*2;
assert ip_tx_result = IPTX_RESULT_SENT report "T2: result should be SENT";
wait for clk_period*10;
------------
-- TEST 3 -- Check that sending to the same IP addr doesnt cause an ARP req as the addr is cached
------------
report "T3: Send 2nd IP TX to same IP addr - should not need to do ARP tx/rx";
ip_tx.hdr.protocol <= x"35";
ip_tx.hdr.data_length <= x"0006";
ip_tx.hdr.dst_ip_addr <= x"c0123478";
ip_tx.data.data_out_valid <= '0';
ip_tx.data.data_out_last <= '0';
wait for clk_period;
ip_tx_start <= '1'; wait for clk_period;
ip_tx_start <= '0'; wait for clk_period;
assert ip_tx_result = IPTX_RESULT_SENDING report "T3: result should be IPTX_RESULT_SENDING";
wait for clk_period*2;
assert ip_tx_data_out_ready = '0' report "T3: IP data out ready asserted too early";
wait until ip_tx_data_out_ready = '1';
-- start to tx IP data
ip_tx.data.data_out_valid <= '1';
ip_tx.data.data_out <= x"81"; wait for clk_period;
ip_tx.data.data_out <= x"83"; wait for clk_period;
ip_tx.data.data_out <= x"85"; wait for clk_period;
ip_tx.data.data_out <= x"87"; wait for clk_period;
ip_tx.data.data_out <= x"89"; wait for clk_period;
ip_tx.data.data_out <= x"8b";
ip_tx.data.data_out_last <= '1';
wait for clk_period;
assert mac_tx_tlast = '1' report "T3: mac_tx_tlast not set on last byte";
wait for clk_period;
ip_tx.data.data_out_valid <= '0';
ip_tx.data.data_out_last <= '0';
wait for clk_period*2;
assert ip_tx_result = IPTX_RESULT_SENT report "T3: result should be SENT";
wait for clk_period*2;
report "-- end of tests --";
wait;
end process;
END;
|
bsd-2-clause
|
athalonis/CCL-Verification-Environment
|
src/vhdl/boundbox_big.vhd
|
1
|
7785
|
--------------------------------------------------------------------------------
--Copyright (c) 2014, Benjamin Bässler <[email protected]>
--All rights reserved.
--
--Redistribution and use in source and binary forms, with or without
--modification, are permitted provided that the following conditions are met:
--
--* Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
--
--* Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
--
--THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
--IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
--DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
--FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
--DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
--SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
--CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
--OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
--OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--------------------------------------------------------------------------------
--! @file boundbox_big.vhd
--! @brief Computes the boundboxes of each label after equal labels matched
--! @author Benjamin Bässler
--! @email [email protected]
--! @date 2013-06-04
--------------------------------------------------------------------------------
--! Use standard library
library ieee;
--! Use numeric std
use IEEE.numeric_std.all;
use IEEE.std_logic_1164.all;
use work.types.all;
use work.utils.all;
use IEEE.math_real.all;
--! The big version needs for each possible label a boundbox storage space
entity boundbox is
generic(
--! Max image
G_MAX_IMG_WIDTH : NATURAL := C_MAX_IMAGE_WIDTH;
--! Max image
G_MAX_IMG_HEIGHT : NATURAL := C_MAX_IMAGE_HEIGHT;
--! Only for compatibility purposes
G_MAX_BOUNDBOXES : NATURAL := div_ceil(C_MAX_IMAGE_WIDTH,2)+div_ceil(C_MAX_IMAGE_HEIGHT,2)
);
port(
--! Clock input
clk_in : in STD_LOGIC;
--! Reset input
rst_in : in STD_LOGIC;
--! stall the output of bound box
stall_in : in STD_LOGIC;
--! High if the lable input valid
lbl_valid_in : in STD_LOGIC;
--! Input of Lables
label_in : in T_LABEL;
--! High if the boundbox output valid
box_valid_out : out STD_LOGIC;
--! output of bound box
box_out : out T_BOX;
--! high if all boxes are computed
box_done_out : out STD_LOGIC;
--! High if the memory free manager can't find fast new storage
--! The result of the bounding box are wrong
error_out : out STD_LOGIC;
--! width of the image at the input
img_width_in : in UNSIGNED(log2_ceil(G_MAX_IMG_WIDTH) downto 0);
--! height of the image
img_height_in : in UNSIGNED(log2_ceil(G_MAX_IMG_HEIGHT) downto 0)
);
end entity boundbox;
--! @brief arc description
--! @details more detailed description
architecture boundbox_arc of boundbox is
-- Types --------------------------------------------------------------------
type T_BOX_STORE is array (2**T_LABEL'length - 1 downto 0) of T_BOX;
-- Constants ----------------------------------------------------------------
-- Signals ------------------------------------------------------------------
signal box_store_s : T_BOX_STORE;
signal box_used_s : unsigned(T_BOX_STORE'range);
signal col_cnt_s : UNSIGNED(log2_ceil(G_MAX_IMG_WIDTH) - 1 downto 0);
signal row_cnt_s : UNSIGNED(log2_ceil(G_MAX_IMG_HEIGHT) downto 0);
signal next_chk_s : T_LABEL;
begin
box_done_out <= '1' when box_used_s = 0 else '0';
p_counter : process (clk_in, rst_in)
begin
if rst_in = '1' then
col_cnt_s <= (others => '0');
row_cnt_s <= (others => '0');
elsif rising_edge(clk_in) and rst_in = '0' then
if lbl_valid_in = '1' and stall_in = '0' then
if col_cnt_s = img_width_in - 1 then
col_cnt_s <= (others => '0');
row_cnt_s <= row_cnt_s + 1;
else
col_cnt_s <= col_cnt_s + 1;
end if;
end if;
end if;
end process p_counter;
p_box : process (clk_in, rst_in)
variable tmp_x_0_v : unsigned(log2_ceil(G_MAX_IMG_WIDTH)-1 downto 0);
variable tmp_y_0_v : unsigned(log2_ceil(G_MAX_IMG_HEIGHT)-1 downto 0);
variable tmp_x_1_v : unsigned(log2_ceil(G_MAX_IMG_WIDTH)-1 downto 0);
variable tmp_y_1_v : unsigned(log2_ceil(G_MAX_IMG_HEIGHT)-1 downto 0);
begin
if rst_in = '1' then
box_used_s <= (others => '0');
next_chk_s <= (others => '0');
error_out <= '0';
box_valid_out <= '0';
elsif rising_edge(clk_in) and rst_in = '0' then
if stall_in = '0' then
box_valid_out <= '0';
if lbl_valid_in = '1' and label_in /= C_UNLABELD then
--resize to map lable 256 to position 0
if box_used_s(to_integer(label_in)) = '0' then
-- first label of this box
-- mark heap position as inuse
box_used_s(to_integer(label_in)) <= '1';
-- store this pixel as the start of the box
box_store_s(to_integer(label_in))(T_X_END) <= col_cnt_s;
box_store_s(to_integer(label_in))(T_Y_END) <= resize(row_cnt_s, row_cnt_s'length-1);
box_store_s(to_integer(label_in))(T_X_START) <= col_cnt_s;
box_store_s(to_integer(label_in))(T_Y_START) <= resize(row_cnt_s, row_cnt_s'length-1);
else
-- the box of this label allready has stored a start point
-- x and y value of the start (0) can't be smaller
tmp_x_1_v := box_store_s(to_integer(label_in))(T_X_END);
tmp_y_1_v := box_store_s(to_integer(label_in))(T_Y_END);
tmp_x_0_v := box_store_s(to_integer(label_in))(T_X_START);
tmp_y_0_v := box_store_s(to_integer(label_in))(T_Y_START);
-- has the end point moved to the right?
if tmp_x_1_v < col_cnt_s then
tmp_x_1_v := col_cnt_s;
end if;
-- has the start point moved to the left?
if tmp_x_0_v > col_cnt_s then
tmp_x_0_v := col_cnt_s;
end if;
-- the y value need no check it can only be bigger or equals
tmp_y_1_v := resize(row_cnt_s, row_cnt_s'length-1);
-- write the new bounderies
box_store_s(to_integer(label_in))(T_X_END) <= tmp_x_1_v;
box_store_s(to_integer(label_in))(T_Y_END) <= tmp_y_1_v;
box_store_s(to_integer(label_in))(T_X_START) <= tmp_x_0_v;
box_store_s(to_integer(label_in))(T_Y_START) <= tmp_y_0_v;
end if;
else
--TODO: use the biggest possible lable to reduce the check_s range
next_chk_s <= next_chk_s + 1;
if box_used_s(to_integer(next_chk_s)) = '1' then
tmp_x_1_v := box_store_s(to_integer(next_chk_s))(T_X_END);
tmp_y_1_v := box_store_s(to_integer(next_chk_s))(T_Y_END);
if (tmp_y_1_v < row_cnt_s and resize(tmp_x_1_v, tmp_x_1_v'length+1) + 2 < col_cnt_s) or -- last lable one row before and in x at least one pixle space
tmp_y_1_v + 1 < row_cnt_s or -- one row without a pixle of this lable
(row_cnt_s = img_height_in - 1 and resize(tmp_x_1_v, tmp_x_1_v'length+1) + 1 < col_cnt_s) or -- last line
(row_cnt_s = img_height_in and col_cnt_s >= 0) -- end of image
then
-- output the processed box
box_out <= box_store_s(to_integer(next_chk_s));
box_valid_out <= '1';
-- mark heap memory as free
box_used_s(to_integer(next_chk_s)) <= '0';
end if;
end if;
end if;
end if;
end if;
end process p_box;
end architecture boundbox_arc;
|
bsd-2-clause
|
athalonis/CCL-Verification-Environment
|
src/vhdl/communication/confreg.vhd
|
12226531
|
0
|
bsd-2-clause
|
|
cr1901/HDMI2USB-litex-firmware
|
gateware/encoder/vhdl/r_divider.vhd
|
5
|
6166
|
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2009 --
-- --
--------------------------------------------------------------------------------
-- --
-- Title : DIVIDER --
-- Design : Divider using reciprocal table --
-- Author : Michal Krepa --
-- --
--------------------------------------------------------------------------------
-- --
-- File : R_DIVIDER.VHD --
-- Created : Wed 18-03-2009 --
-- --
--------------------------------------------------------------------------------
-- --
--------------------------------------------------------------------------------
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- /// Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
--------------------------------------------------------------------------------
-- MAIN DIVIDER top level
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.All;
use IEEE.NUMERIC_STD.all;
entity r_divider is
port
(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
a : in STD_LOGIC_VECTOR(11 downto 0);
d : in STD_LOGIC_VECTOR(7 downto 0);
q : out STD_LOGIC_VECTOR(11 downto 0)
) ;
end r_divider ;
architecture rtl of r_divider is
signal romr_datao : std_logic_vector(15 downto 0):=(others => '0');
signal romr_addr : std_logic_vector(7 downto 0):=(others => '0');
signal dividend : signed(11 downto 0):=(others => '0');
signal dividend_d1 : unsigned(11 downto 0):=(others => '0');
signal reciprocal : unsigned(15 downto 0):=(others => '0');
signal mult_out : unsigned(27 downto 0):=(others => '0');
signal mult_out_s : signed(11 downto 0):=(others => '0');
signal signbit : std_logic:='0';
signal signbit_d1 : std_logic:='0';
signal signbit_d2 : std_logic:='0';
signal signbit_d3 : std_logic:='0';
signal round : std_logic:='0';
begin
U_ROMR : entity work.ROMR
generic map
(
ROMADDR_W => 8,
ROMDATA_W => 16
)
port map
(
addr => romr_addr,
clk => CLK,
datao => romr_datao
);
romr_addr <= d;
reciprocal <= unsigned(romr_datao);
dividend <= signed(a);
signbit <= dividend(dividend'high);
rdiv : process(clk,rst)
begin
if rst = '1' then
mult_out <= (others => '0');
mult_out_s <= (others => '0');
dividend_d1 <= (others => '0');
q <= (others => '0');
signbit_d1 <= '0';
signbit_d2 <= '0';
signbit_d3 <= '0';
round <= '0';
elsif clk = '1' and clk'event then
signbit_d1 <= signbit;
signbit_d2 <= signbit_d1;
signbit_d3 <= signbit_d2;
if signbit = '1' then
dividend_d1 <= unsigned(0-dividend);
else
dividend_d1 <= unsigned(dividend);
end if;
mult_out <= dividend_d1 * reciprocal;
if signbit_d2 = '0' then
mult_out_s <= resize(signed(mult_out(27 downto 16)),mult_out_s'length);
else
mult_out_s <= resize(0-signed(mult_out(27 downto 16)),mult_out_s'length);
end if;
round <= mult_out(15);
if signbit_d3 = '0' then
if round = '1' then
q <= std_logic_vector(mult_out_s + 1);
else
q <= std_logic_vector(mult_out_s);
end if;
else
if round = '1' then
q <= std_logic_vector(mult_out_s - 1);
else
q <= std_logic_vector(mult_out_s);
end if;
end if;
end if;
end process;
end rtl;
|
bsd-2-clause
|
cr1901/HDMI2USB-litex-firmware
|
gateware/encoder/vhdl/SUB_RAMZ.vhd
|
5
|
5102
|
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2006 --
-- --
--------------------------------------------------------------------------------
-- --
-- Title : SUB_RAMZ --
-- Design : EV_JPEG_ENC --
-- Author : Michal Krepa -- -- --
-- --
--------------------------------------------------------------------------------
--
-- File : SUB_RAMZ.VHD
-- Created : 22/03/2009
--
--------------------------------------------------------------------------------
--
-- Description : RAM memory simulation model
--
--------------------------------------------------------------------------------
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- /// Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity SUB_RAMZ is
generic
(
RAMADDR_W : INTEGER := 6;
RAMDATA_W : INTEGER := 12
);
port (
d : in STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
waddr : in STD_LOGIC_VECTOR(RAMADDR_W-1 downto 0);
raddr : in STD_LOGIC_VECTOR(RAMADDR_W-1 downto 0);
we : in STD_LOGIC;
clk : in STD_LOGIC;
q : out STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0)
);
end SUB_RAMZ;
architecture RTL of SUB_RAMZ is
type mem_type is array ((2**RAMADDR_W)-1 downto 0) of
STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
signal mem : mem_type;
signal read_addr : STD_LOGIC_VECTOR(RAMADDR_W-1 downto 0);
--attribute ram_style: string;
--attribute ram_style of mem : signal is "distributed";
begin
-------------------------------------------------------------------------------
q_sg:
-------------------------------------------------------------------------------
q <= mem(TO_INTEGER(UNSIGNED(read_addr)));
-------------------------------------------------------------------------------
read_proc: -- register read address
-------------------------------------------------------------------------------
process (clk)
begin
if clk = '1' and clk'event then
read_addr <= raddr;
end if;
end process;
-------------------------------------------------------------------------------
write_proc: --write access
-------------------------------------------------------------------------------
process (clk) begin
if clk = '1' and clk'event then
if we = '1' then
mem(TO_INTEGER(UNSIGNED(waddr))) <= d;
end if;
end if;
end process;
end RTL;
|
bsd-2-clause
|
cr1901/HDMI2USB-litex-firmware
|
gateware/encoder/vhdl/MDCT_PKG.vhd
|
5
|
4295
|
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2006 --
-- --
--------------------------------------------------------------------------------
--
-- Title : MDCT_PKG
-- Design : MDCT Core
-- Author : Michal Krepa
--
--------------------------------------------------------------------------------
--
-- File : MDCT_PKG.VHD
-- Created : Sat Mar 5 2006
--
--------------------------------------------------------------------------------
--
-- Description : Package for MDCT core
--
--------------------------------------------------------------------------------
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- /// Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
package MDCT_PKG is
constant IP_W : INTEGER := 8;
constant OP_W : INTEGER := 12;
constant N : INTEGER := 8;
constant COE_W : INTEGER := 12;
constant ROMDATA_W : INTEGER := COE_W+2;
constant ROMADDR_W : INTEGER := 6;
constant RAMDATA_W : INTEGER := 10;
constant RAMADRR_W : INTEGER := 6;
constant COL_MAX : INTEGER := N-1;
constant ROW_MAX : INTEGER := N-1;
constant LEVEL_SHIFT : INTEGER := 128;
constant DA_W : INTEGER := ROMDATA_W+IP_W;
constant DA2_W : INTEGER := DA_W+2;
-- 2's complement numbers
constant AP : INTEGER := 1448;
constant BP : INTEGER := 1892;
constant CP : INTEGER := 784;
constant DP : INTEGER := 2009;
constant EP : INTEGER := 1703;
constant FP : INTEGER := 1138;
constant GP : INTEGER := 400;
constant AM : INTEGER := -1448;
constant BM : INTEGER := -1892;
constant CM : INTEGER := -784;
constant DM : INTEGER := -2009;
constant EM : INTEGER := -1703;
constant FM : INTEGER := -1138;
constant GM : INTEGER := -400;
type T_ROM1DATAO is array(0 to 8) of STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
type T_ROM1ADDRO is array(0 to 8) of STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
type T_ROM2DATAO is array(0 to 10) of STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
type T_ROM2ADDRO is array(0 to 10) of STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
end MDCT_PKG;
|
bsd-2-clause
|
cr1901/HDMI2USB-litex-firmware
|
gateware/encoder/vhdl/DCT1D.vhd
|
2
|
14667
|
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2006 --
-- --
--------------------------------------------------------------------------------
--
-- Title : DCT1D
-- Design : MDCT Core
-- Author : Michal Krepa
--
--------------------------------------------------------------------------------
--
-- File : DCT1D.VHD
-- Created : Sat Mar 5 7:37 2006
--
--------------------------------------------------------------------------------
--
-- Description : 1D Discrete Cosine Transform (1st stage)
--
--------------------------------------------------------------------------------
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- /// Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library WORK;
use WORK.MDCT_PKG.all;
--------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------
entity DCT1D is
port(
clk : in STD_LOGIC;
rst : in std_logic;
dcti : in std_logic_vector(IP_W-1 downto 0);
idv : in STD_LOGIC;
romedatao : in T_ROM1DATAO;
romodatao : in T_ROM1DATAO;
odv : out STD_LOGIC;
dcto : out std_logic_vector(OP_W-1 downto 0);
romeaddro : out T_ROM1ADDRO;
romoaddro : out T_ROM1ADDRO;
ramwaddro : out STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
ramdatai : out STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
ramwe : out STD_LOGIC;
wmemsel : out STD_LOGIC
);
end DCT1D;
--------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------
architecture RTL of DCT1D is
type INPUT_DATA is array (N-1 downto 0) of SIGNED(IP_W downto 0);
--**************************************************************
--**************************************************************
signal databuf_reg : INPUT_DATA;
signal latchbuf_reg : INPUT_DATA;
signal col_reg : UNSIGNED(RAMADRR_W/2-1 downto 0):=(others=>'0');
signal row_reg : UNSIGNED(RAMADRR_W/2-1 downto 0):=(others=>'0');
signal rowr_reg : UNSIGNED(RAMADRR_W/2-1 downto 0):=(others=>'0');
signal inpcnt_reg : UNSIGNED(RAMADRR_W/2-1 downto 0):=(others=>'0');
signal ramwe_s : STD_LOGIC:='0';
signal wmemsel_reg : STD_LOGIC:='0';
signal stage2_reg : STD_LOGIC:='0';
signal stage2_cnt_reg : UNSIGNED(RAMADRR_W-1 downto 0):=(others=>'1');
signal col_2_reg : UNSIGNED(RAMADRR_W/2-1 downto 0):=(others=>'0');
signal ramwaddro_s : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0):=(others=>'0');
--**************************************************************
--**************************************************************
signal even_not_odd : std_logic:='0';
signal even_not_odd_d1 : std_logic:='0';
signal even_not_odd_d2 : std_logic:='0';
signal even_not_odd_d3 : std_logic:='0';
signal ramwe_d1 : STD_LOGIC:='0';
signal ramwe_d2 : STD_LOGIC:='0';
signal ramwe_d3 : STD_LOGIC:='0';
signal ramwe_d4 : STD_LOGIC:='0';
signal ramwaddro_d1 : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0):=(others=>'0');
signal ramwaddro_d2 : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0):=(others=>'0');
signal ramwaddro_d3 : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0):=(others=>'0');
signal ramwaddro_d4 : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0):=(others=>'0');
signal wmemsel_d1 : STD_LOGIC:='0';
signal wmemsel_d2 : STD_LOGIC:='0';
signal wmemsel_d3 : STD_LOGIC:='0';
signal wmemsel_d4 : STD_LOGIC:='0';
signal romedatao_d1 : T_ROM1DATAO;
signal romodatao_d1 : T_ROM1DATAO;
signal romedatao_d2 : T_ROM1DATAO;
signal romodatao_d2 : T_ROM1DATAO;
signal romedatao_d3 : T_ROM1DATAO;
signal romodatao_d3 : T_ROM1DATAO;
signal dcto_1 : STD_LOGIC_VECTOR(DA_W-1 downto 0):=(others=>'0');
signal dcto_2 : STD_LOGIC_VECTOR(DA_W-1 downto 0):=(others=>'0');
signal dcto_3 : STD_LOGIC_VECTOR(DA_W-1 downto 0):=(others=>'0');
signal dcto_4 : STD_LOGIC_VECTOR(DA_W-1 downto 0):=(others=>'0');
begin
--**************************************************************
--**************************************************************
ramwaddro <= ramwaddro_d4;
ramwe <= ramwe_d4;
ramdatai <= dcto_4(DA_W-1 downto 12);
wmemsel <= wmemsel_d4;
--**************************************************************
--**************************************************************
process(clk,rst)
begin
if rst = '1' then
inpcnt_reg <= (others => '0');
latchbuf_reg <= (others => (others => '0'));
databuf_reg <= (others => (others => '0'));
stage2_reg <= '0';
stage2_cnt_reg <= (others => '1');
ramwe_s <= '0';
ramwaddro_s <= (others => '0');
col_reg <= (others => '0');
row_reg <= (others => '0');
wmemsel_reg <= '0';
col_2_reg <= (others => '0');
elsif rising_edge(clk) then
stage2_reg <= '0';
ramwe_s <= '0';
--------------------------------
-- 1st stage
--------------------------------
if idv = '1' then
inpcnt_reg <= inpcnt_reg + 1;
-- right shift input data
latchbuf_reg(N-2 downto 0) <= latchbuf_reg(N-1 downto 1);
latchbuf_reg(N-1) <= SIGNED('0' & dcti) - LEVEL_SHIFT;
if inpcnt_reg = N-1 then
-- after this sum databuf_reg is in range of -256 to 254 (min to max)
databuf_reg(0) <= latchbuf_reg(1)+(SIGNED('0' & dcti) - LEVEL_SHIFT);
databuf_reg(1) <= latchbuf_reg(2)+latchbuf_reg(7);
databuf_reg(2) <= latchbuf_reg(3)+latchbuf_reg(6);
databuf_reg(3) <= latchbuf_reg(4)+latchbuf_reg(5);
databuf_reg(4) <= latchbuf_reg(1)-(SIGNED('0' & dcti) - LEVEL_SHIFT);
databuf_reg(5) <= latchbuf_reg(2)-latchbuf_reg(7);
databuf_reg(6) <= latchbuf_reg(3)-latchbuf_reg(6);
databuf_reg(7) <= latchbuf_reg(4)-latchbuf_reg(5);
stage2_reg <= '1';
end if;
end if;
--------------------------------
--------------------------------
-- 2nd stage
--------------------------------
if stage2_cnt_reg < N then
stage2_cnt_reg <= stage2_cnt_reg + 1;
-- write RAM
ramwe_s <= '1';
-- reverse col/row order for transposition purpose
ramwaddro_s <= STD_LOGIC_VECTOR(col_2_reg & row_reg);
-- increment column counter
col_reg <= col_reg + 1;
col_2_reg <= col_2_reg + 1;
-- finished processing one input row
if col_reg = 0 then
row_reg <= row_reg + 1;
-- switch to 2nd memory
if row_reg = N - 1 then
wmemsel_reg <= not wmemsel_reg;
col_reg <= (others => '0');
end if;
end if;
end if;
if stage2_reg = '1' then
stage2_cnt_reg <= (others => '0');
col_reg <= (0=>'1',others => '0');
col_2_reg <= (others => '0');
end if;
----------------------------------
end if;
end process;
-- output data pipeline
p_data_out_pipe : process(CLK, RST)
begin
if RST = '1' then
even_not_odd <= '0';
even_not_odd_d1 <= '0';
even_not_odd_d2 <= '0';
even_not_odd_d3 <= '0';
ramwe_d1 <= '0';
ramwe_d2 <= '0';
ramwe_d3 <= '0';
ramwe_d4 <= '0';
ramwaddro_d1 <= (others => '0');
ramwaddro_d2 <= (others => '0');
ramwaddro_d3 <= (others => '0');
ramwaddro_d4 <= (others => '0');
wmemsel_d1 <= '0';
wmemsel_d2 <= '0';
wmemsel_d3 <= '0';
wmemsel_d4 <= '0';
dcto_1 <= (others => '0');
dcto_2 <= (others => '0');
dcto_3 <= (others => '0');
dcto_4 <= (others => '0');
elsif CLK'event and CLK = '1' then
even_not_odd <= stage2_cnt_reg(0);
even_not_odd_d1 <= even_not_odd;
even_not_odd_d2 <= even_not_odd_d1;
even_not_odd_d3 <= even_not_odd_d2;
ramwe_d1 <= ramwe_s;
ramwe_d2 <= ramwe_d1;
ramwe_d3 <= ramwe_d2;
ramwe_d4 <= ramwe_d3;
ramwaddro_d1 <= ramwaddro_s;
ramwaddro_d2 <= ramwaddro_d1;
ramwaddro_d3 <= ramwaddro_d2;
ramwaddro_d4 <= ramwaddro_d3;
wmemsel_d1 <= wmemsel_reg;
wmemsel_d2 <= wmemsel_d1;
wmemsel_d3 <= wmemsel_d2;
wmemsel_d4 <= wmemsel_d3;
if even_not_odd = '0' then
dcto_1 <= STD_LOGIC_VECTOR(RESIZE
(RESIZE(SIGNED(romedatao(0)),DA_W) +
(RESIZE(SIGNED(romedatao(1)),DA_W-1) & '0') +
(RESIZE(SIGNED(romedatao(2)),DA_W-2) & "00"),
DA_W));
else
dcto_1 <= STD_LOGIC_VECTOR(RESIZE
(RESIZE(SIGNED(romodatao(0)),DA_W) +
(RESIZE(SIGNED(romodatao(1)),DA_W-1) & '0') +
(RESIZE(SIGNED(romodatao(2)),DA_W-2) & "00"),
DA_W));
end if;
if even_not_odd_d1 = '0' then
dcto_2 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_1) +
(RESIZE(SIGNED(romedatao_d1(3)),DA_W-3) & "000") +
(RESIZE(SIGNED(romedatao_d1(4)),DA_W-4) & "0000"),
DA_W));
else
dcto_2 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_1) +
(RESIZE(SIGNED(romodatao_d1(3)),DA_W-3) & "000") +
(RESIZE(SIGNED(romodatao_d1(4)),DA_W-4) & "0000"),
DA_W));
end if;
if even_not_odd_d2 = '0' then
dcto_3 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_2) +
(RESIZE(SIGNED(romedatao_d2(5)),DA_W-5) & "00000") +
(RESIZE(SIGNED(romedatao_d2(6)),DA_W-6) & "000000"),
DA_W));
else
dcto_3 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_2) +
(RESIZE(SIGNED(romodatao_d2(5)),DA_W-5) & "00000") +
(RESIZE(SIGNED(romodatao_d2(6)),DA_W-6) & "000000"),
DA_W));
end if;
if even_not_odd_d3 = '0' then
dcto_4 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_3) +
(RESIZE(SIGNED(romedatao_d3(7)),DA_W-7) & "0000000") -
(RESIZE(SIGNED(romedatao_d3(8)),DA_W-8) & "00000000"),
DA_W));
else
dcto_4 <= STD_LOGIC_VECTOR(RESIZE
(signed(dcto_3) +
(RESIZE(SIGNED(romodatao_d3(7)),DA_W-7) & "0000000") -
(RESIZE(SIGNED(romodatao_d3(8)),DA_W-8) & "00000000"),
DA_W));
end if;
end if;
end process;
-- read precomputed MAC results from LUT
p_romaddr : process(CLK, RST)
begin
if RST = '1' then
romeaddro <= (others => (others => '0'));
romoaddro <= (others => (others => '0'));
elsif CLK'event and CLK = '1' then
for i in 0 to 8 loop
-- even
romeaddro(i) <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(0)(i) &
databuf_reg(1)(i) &
databuf_reg(2)(i) &
databuf_reg(3)(i);
-- odd
romoaddro(i) <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(4)(i) &
databuf_reg(5)(i) &
databuf_reg(6)(i) &
databuf_reg(7)(i);
end loop;
end if;
end process;
p_romdatao_d1 : process(CLK, RST)
begin
if RST = '1' then
romedatao_d1 <= (others => (others => '0'));
romodatao_d1 <= (others => (others => '0'));
romedatao_d2 <= (others => (others => '0'));
romodatao_d2 <= (others => (others => '0'));
romedatao_d3 <= (others => (others => '0'));
romodatao_d3 <= (others => (others => '0'));
elsif CLK'event and CLK = '1' then
romedatao_d1 <= romedatao;
romodatao_d1 <= romodatao;
romedatao_d2 <= romedatao_d1;
romodatao_d2 <= romodatao_d1;
romedatao_d3 <= romedatao_d2;
romodatao_d3 <= romodatao_d2;
end if;
end process;
end RTL;
--------------------------------------------------------------------------------
|
bsd-2-clause
|
cr1901/HDMI2USB-litex-firmware
|
gateware/rgmii_if.vhd
|
2
|
18022
|
--------------------------------------------------------------------------------
-- File : rgmii_v2_0_if.vhd
-- Author : Xilinx Inc.
-- ------------------------------------------------------------------------------
-- (c) Copyright 2004-2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-- ------------------------------------------------------------------------------
-- Description: This module creates a version 2.0 Reduced Gigabit Media
-- Independent Interface (RGMII v2.0) by instantiating
-- Input/Output buffers and Input/Output double data rate
-- (DDR) flip-flops as required.
--
-- This interface is used to connect the Ethernet MAC to
-- an external Ethernet PHY.
-- This module routes the rgmii_rxc from the phy chip
-- (via a bufg) onto the rx_clk line.
-- An IODELAY component is used to shift the input clock
-- to ensure that the set-up and hold times are observed.
--------------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--------------------------------------------------------------------------------
-- The entity declaration for the PHY IF design.
--------------------------------------------------------------------------------
entity rgmii_if is
port(
-- Synchronous resets
tx_reset : in std_logic;
rx_reset : in std_logic;
-- The following ports are the RGMII physical interface: these will be at
-- pins on the FPGA
rgmii_txd : out std_logic_vector(3 downto 0);
rgmii_tx_ctl : out std_logic;
rgmii_txc : out std_logic;
rgmii_rxd : in std_logic_vector(3 downto 0);
rgmii_rx_ctl : in std_logic;
rgmii_rxc : in std_logic;
-- The following signals are in the RGMII in-band status signals
link_status : out std_logic;
clock_speed : out std_logic_vector(1 downto 0);
duplex_status : out std_logic;
-- The following ports are the internal GMII connections from IOB logic
-- to the TEMAC core
txd_from_mac : in std_logic_vector(7 downto 0);
tx_en_from_mac : in std_logic;
tx_er_from_mac : in std_logic;
tx_clk : in std_logic;
crs_to_mac : out std_logic;
col_to_mac : out std_logic;
rxd_to_mac : out std_logic_vector(7 downto 0);
rx_dv_to_mac : out std_logic;
rx_er_to_mac : out std_logic;
-- Receiver clock for the MAC and Client Logic
rx_clk : out std_logic
);
end rgmii_if;
architecture PHY_IF of rgmii_if is
------------------------------------------------------------------------------
-- internal signals
------------------------------------------------------------------------------
signal not_tx_clk90 : std_logic; -- Inverted version of tx_clk90.
signal not_tx_clk : std_logic; -- Inverted version of tx_clk.
signal gmii_txd_rising : std_logic_vector(7 downto 0); -- gmii_txd signal registered on the rising edge of tx_clk.
signal gmii_tx_en_rising : std_logic; -- gmii_tx_en signal registered on the rising edge of tx_clk.
signal rgmii_tx_ctl_rising : std_logic; -- RGMII control signal registered on the rising edge of tx_clk.
signal gmii_txd_falling : std_logic_vector(3 downto 0); -- gmii_txd signal registered on the falling edge of tx_clk.
signal rgmii_tx_ctl_falling : std_logic; -- RGMII control signal registered on the falling edge of tx_clk.
signal rgmii_txc_odelay : std_logic; -- RGMII receiver clock ODDR output.
signal rgmii_tx_ctl_odelay : std_logic; -- RGMII control signal ODDR output.
signal rgmii_txd_odelay : std_logic_vector(3 downto 0); -- RGMII data ODDR output.
signal rgmii_tx_ctl_int : std_logic; -- Internal RGMII transmit control signal.
signal rgmii_rxd_delay : std_logic_vector(7 downto 0);
signal rgmii_rx_ctl_delay : std_logic;
signal rx_clk_inv : std_logic;
signal rgmii_rx_ctl_reg : std_logic; -- Internal RGMII receiver control signal.
signal gmii_rxd_reg_int : std_logic_vector(7 downto 0); -- gmii_rxd registered in IOBs.
signal gmii_rx_dv_reg_int : std_logic; -- gmii_rx_dv registered in IOBs.
signal gmii_rx_dv_reg : std_logic; -- gmii_rx_dv registered in IOBs.
signal gmii_rx_er_reg : std_logic; -- gmii_rx_er registered in IOBs.
signal gmii_rxd_reg : std_logic_vector(7 downto 0); -- gmii_rxd registered in IOBs.
signal inband_ce : std_logic; -- RGMII inband status registers clock enable
signal rx_clk_int : std_logic;
begin
-----------------------------------------------------------------------------
-- Route internal signals to output ports :
-----------------------------------------------------------------------------
rxd_to_mac <= gmii_rxd_reg;
rx_dv_to_mac <= gmii_rx_dv_reg;
rx_er_to_mac <= gmii_rx_er_reg;
-----------------------------------------------------------------------------
-- RGMII Transmitter Clock Management :
-----------------------------------------------------------------------------
-- Delay the transmitter clock relative to the data.
-- For 1 gig operation this delay is set to produce a 90 degree phase
-- shifted clock w.r.t. gtx_clk_bufg so that the clock edges are
-- centralised within the rgmii_txd[3:0] valid window.
-- Invert the clock locally at the ODDR primitive
not_tx_clk <= not(tx_clk);
-- Instantiate the Output DDR primitive
rgmii_txc_ddr : ODDR2
generic map (
DDR_ALIGNMENT => "C0",
SRTYPE => "ASYNC"
)
port map (
Q => rgmii_txc_odelay,
C0 => tx_clk,
C1 => not_tx_clk,
CE => '1',
D0 => '1',
D1 => '0',
R => tx_reset,
S => '0'
);
-- Instantiate the Output Delay primitive (delay output by 2 ns)
delay_rgmii_tx_clk : IODELAY2
generic map (
IDELAY_TYPE => "FIXED",
ODELAY_VALUE => 30, -- 50 ps per tap 0-255 taps
DELAY_SRC => "ODATAIN"
)
port map (
BUSY => open,
DATAOUT => open,
DATAOUT2 => open,
DOUT => rgmii_txc,
TOUT => open,
CAL => '0',
CE => '0',
CLK => '0',
IDATAIN => '0',
INC => '0',
IOCLK0 => '0',
IOCLK1 => '0',
ODATAIN => rgmii_txc_odelay,
RST => '0',
T => '0'
);
-----------------------------------------------------------------------------
-- RGMII Transmitter Logic :
-- drive TX signals through IOBs onto RGMII interface
-----------------------------------------------------------------------------
-- Encode rgmii ctl signal
rgmii_tx_ctl_int <= tx_en_from_mac xor tx_er_from_mac;
-- Instantiate Double Data Rate Output components.
-- Put data and control signals through ODELAY components to
-- provide similiar net delays to those seen on the clk signal.
gmii_txd_falling <= txd_from_mac(7 downto 4);
txdata_out_bus: for I in 3 downto 0 generate
begin
-- Instantiate the Output DDR primitive
rgmii_txd_out : ODDR2
generic map (
DDR_ALIGNMENT => "C0",
SRTYPE => "ASYNC"
)
port map (
Q => rgmii_txd_odelay(I),
C0 => tx_clk,
C1 => not_tx_clk,
CE => '1',
D0 => txd_from_mac(I),
D1 => gmii_txd_falling(I),
R => tx_reset,
S => '0'
);
-- Instantiate the Output Delay primitive (delay output by 2 ns)
delay_rgmii_txd : IODELAY2
generic map (
IDELAY_TYPE => "FIXED",
ODELAY_VALUE => 0, -- 50 ps per tap 0-255 taps
DELAY_SRC => "ODATAIN"
)
port map (
BUSY => open,
DATAOUT => open,
DATAOUT2 => open,
DOUT => rgmii_txd(I),
TOUT => open,
CAL => '0',
CE => '0',
CLK => '0',
IDATAIN => '0',
INC => '0',
IOCLK0 => '0',
IOCLK1 => '0',
ODATAIN => rgmii_txd_odelay(I),
RST => '0',
T => '0'
);
end generate;
-- Instantiate the Output DDR primitive
rgmii_tx_ctl_out : ODDR2
generic map (
DDR_ALIGNMENT => "C0",
SRTYPE => "ASYNC"
)
port map (
Q => rgmii_tx_ctl_odelay,
C0 => tx_clk,
C1 => not_tx_clk,
CE => '1',
D0 => tx_en_from_mac,
D1 => rgmii_tx_ctl_int,
R => tx_reset,
S => '0'
);
-- Instantiate the Output Delay primitive (delay output by 2 ns)
delay_rgmii_tx_ctl : IODELAY2
generic map (
IDELAY_TYPE => "FIXED",
ODELAY_VALUE => 0, -- 50 ps per tap 0-255 taps
DELAY_SRC => "ODATAIN"
)
port map (
BUSY => open,
DATAOUT => open,
DATAOUT2 => open,
DOUT => rgmii_tx_ctl,
TOUT => open,
CAL => '0',
CE => '0',
CLK => '0',
IDATAIN => '0',
INC => '0',
IOCLK0 => '0',
IOCLK1 => '0',
ODATAIN => rgmii_tx_ctl_odelay,
RST => '0',
T => '0'
);
-----------------------------------------------------------------------------
-- RGMII Receiver Clock Logic
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- RGMII Receiver Clock Logic
-----------------------------------------------------------------------------
bufg_rgmii_rx_clk : BUFG
port map (
I => rgmii_rxc,
O => rx_clk_int
);
-- Assign the internal clock signal to the output port
rx_clk <= rx_clk_int;
rx_clk_inv <= not rx_clk_int;
-----------------------------------------------------------------------------
-- RGMII Receiver Logic : receive signals through IOBs from RGMII interface
-----------------------------------------------------------------------------
-- Instantiate Double Data Rate Input flip-flops.
-- DDR_CLK_EDGE attribute specifies output data alignment from IDDR component
rxdata_in_bus: for I in 3 downto 0 generate
delay_rgmii_rxd : IODELAY2
generic map (
IDELAY_TYPE => "FIXED",
IDELAY_VALUE => 40,
DELAY_SRC => "IDATAIN"
)
port map (
BUSY => open,
DATAOUT => rgmii_rxd_delay(I),
DATAOUT2 => open,
DOUT => open,
TOUT => open,
CAL => '0',
CE => '0',
CLK => '0',
IDATAIN => rgmii_rxd(I),
INC => '0',
IOCLK0 => '0',
IOCLK1 => '0',
ODATAIN => '0',
RST => '0',
T => '1'
);
rgmii_rx_data_in : IDDR2
generic map (
DDR_ALIGNMENT => "C0"
)
port map (
Q0 => gmii_rxd_reg_int(I),
Q1 => gmii_rxd_reg_int(I+4),
C0 => rx_clk_int,
C1 => rx_clk_inv,
CE => '1',
D => rgmii_rxd_delay(I),
R => '0',
S => '0'
);
-- pipeline the bottom 4 bits
rxd_reg_pipe : process(rx_clk_int)
begin
if rx_clk_int'event and rx_clk_int ='1' then
gmii_rxd_reg(I) <= gmii_rxd_reg_int(I);
end if;
end process rxd_reg_pipe;
-- just pass the top 4 bits
gmii_rxd_reg(I+4) <= gmii_rxd_reg_int(I+4);
end generate;
delay_rgmii_rx_ctl : IODELAY2
generic map (
IDELAY_TYPE => "FIXED",
IDELAY_VALUE => 40,
DELAY_SRC => "IDATAIN"
)
port map (
BUSY => open,
DATAOUT => rgmii_rx_ctl_delay,
DATAOUT2 => open,
DOUT => open,
TOUT => open,
CAL => '0',
CE => '0',
CLK => '0',
IDATAIN => rgmii_rx_ctl,
INC => '0',
IOCLK0 => '0',
IOCLK1 => '0',
ODATAIN => '0',
RST => '0',
T => '1'
);
rgmii_rx_ctl_in : IDDR2
generic map (
DDR_ALIGNMENT => "C0"
)
port map (
Q0 => gmii_rx_dv_reg_int,
Q1 => rgmii_rx_ctl_reg,
C0 => rx_clk_int,
C1 => rx_clk_inv,
CE => '1',
D => rgmii_rx_ctl_delay,
R => '0',
S => '0'
);
rxdv_reg_pipe : process(rx_clk_int)
begin
if rx_clk_int'event and rx_clk_int ='1' then
gmii_rx_dv_reg <= gmii_rx_dv_reg_int;
end if;
end process rxdv_reg_pipe;
-- Decode gmii_rx_er signal
gmii_rx_er_reg <= gmii_rx_dv_reg xor rgmii_rx_ctl_reg;
-----------------------------------------------------------------------------
-- RGMII Inband Status Registers :
-- extract the inband status from received rgmii data
-----------------------------------------------------------------------------
-- Enable inband status registers during Interframe Gap
inband_ce <= gmii_rx_dv_reg nor gmii_rx_er_reg;
reg_inband_status : process(rx_clk_int)
begin
if rx_clk_int'event and rx_clk_int ='1' then
if rx_reset = '1' then
link_status <= '0';
clock_speed(1 downto 0) <= "00";
duplex_status <= '0';
elsif inband_ce = '1' then
link_status <= gmii_rxd_reg(0);
clock_speed(1 downto 0) <= gmii_rxd_reg(2 downto 1);
duplex_status <= gmii_rxd_reg(3);
end if;
end if;
end process reg_inband_status;
-----------------------------------------------------------------------------
-- Create the GMII-style Collision and Carrier Sense signals from RGMII
-----------------------------------------------------------------------------
col_to_mac <= (tx_en_from_mac or tx_er_from_mac) and (gmii_rx_dv_reg or gmii_rx_er_reg);
crs_to_mac <= (tx_en_from_mac or tx_er_from_mac) or (gmii_rx_dv_reg or gmii_rx_er_reg);
end PHY_IF;
|
bsd-2-clause
|
kirbyfan64/pygments-unofficial
|
tests/examplefiles/test.vhdl
|
75
|
4446
|
library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity top_testbench is --test
generic ( -- test
n : integer := 8 -- test
); -- test
end top_testbench; -- test
architecture top_testbench_arch of top_testbench is
component top is
generic (
n : integer
) ;
port (
clk : in std_logic;
rst : in std_logic;
d1 : in std_logic_vector (n-1 downto 0);
d2 : in std_logic_vector (n-1 downto 0);
operation : in std_logic;
result : out std_logic_vector (2*n-1 downto 0)
);
end component;
signal clk : std_logic;
signal rst : std_logic;
signal operation : std_logic;
signal d1 : std_logic_vector (n-1 downto 0);
signal d2 : std_logic_vector (n-1 downto 0);
signal result : std_logic_vector (2*n-1 downto 0);
type test_type is ( a1, a2, a3, a4, a5, a6, a7, a8, a9, a10);
attribute enum_encoding of my_state : type is "001 010 011 100 111";
begin
TESTUNIT : top generic map (n => n)
port map (clk => clk,
rst => rst,
d1 => d1,
d2 => d2,
operation => operation,
result => result);
clock_process : process
begin
clk <= '0';
wait for 5 ns;
clk <= '1';
wait for 5 ns;
end process;
data_process : process
begin
-- test case #1
operation <= '0';
rst <= '1';
wait for 5 ns;
rst <= '0';
wait for 5 ns;
d1 <= std_logic_vector(to_unsigned(60, d1'length));
d2 <= std_logic_vector(to_unsigned(12, d2'length));
wait for 360 ns;
assert (result = std_logic_vector(to_unsigned(720, result'length)))
report "Test case #1 failed" severity error;
-- test case #2
operation <= '0';
rst <= '1';
wait for 5 ns;
rst <= '0';
wait for 5 ns;
d1 <= std_logic_vector(to_unsigned(55, d1'length));
d2 <= std_logic_vector(to_unsigned(1, d2'length));
wait for 360 ns;
assert (result = std_logic_vector(to_unsigned(55, result'length)))
report "Test case #2 failed" severity error;
-- etc
end process;
end top_testbench_arch;
configuration testbench_for_top of top_testbench is
for top_testbench_arch
for TESTUNIT : top
use entity work.top(top_arch);
end for;
end for;
end testbench_for_top;
function compare(A: std_logic, B: std_Logic) return std_logic is
constant pi : real := 3.14159;
constant half_pi : real := pi / 2.0;
constant cycle_time : time := 2 ns;
constant N, N5 : integer := 5;
begin
if (A = '0' and B = '1') then
return B;
else
return A;
end if ;
end compare;
procedure print(P : std_logic_vector(7 downto 0);
U : std_logic_vector(3 downto 0)) is
variable my_line : line;
alias swrite is write [line, string, side, width] ;
begin
swrite(my_line, "sqrt( ");
write(my_line, P);
swrite(my_line, " )= ");
write(my_line, U);
writeline(output, my_line);
end print;
entity add32csa is -- one stage of carry save adder for multiplier
port(
b : in std_logic; -- a multiplier bit
a : in std_logic_vector(31 downto 0); -- multiplicand
sum_in : in std_logic_vector(31 downto 0); -- sums from previous stage
cin : in std_logic_vector(31 downto 0); -- carrys from previous stage
sum_out : out std_logic_vector(31 downto 0); -- sums to next stage
cout : out std_logic_vector(31 downto 0)); -- carrys to next stage
end add32csa;
ARCHITECTURE circuits of add32csa IS
SIGNAL zero : STD_LOGIC_VECTOR(31 downto 0) := X"00000000";
SIGNAL aa : std_logic_vector(31 downto 0) := X"00000000";
COMPONENT fadd -- duplicates entity port
PoRT(a : in std_logic;
b : in std_logic;
cin : in std_logic;
s : out std_logic;
cout : out std_logic);
end comPonent fadd;
begin -- circuits of add32csa
aa <= a when b='1' else zero after 1 ns;
stage: for I in 0 to 31 generate
sta: fadd port map(aa(I), sum_in(I), cin(I) , sum_out(I), cout(I));
end generate stage;
end architecture circuits; -- of add32csa
|
bsd-2-clause
|
HackLinux/CPU-Design
|
cpu/work/cnt/_primary.vhd
|
4
|
469
|
library verilog;
use verilog.vl_types.all;
entity cnt is
port(
clock : in vl_logic;
ex1 : in vl_logic;
ex2 : in vl_logic;
ex3 : in vl_logic;
ex4 : in vl_logic;
read1 : in vl_logic;
read2 : in vl_logic;
read3 : in vl_logic;
read4 : in vl_logic
);
end cnt;
|
bsd-2-clause
|
HackLinux/CPU-Design
|
cpu/work/dcachel2/_primary.vhd
|
2
|
771
|
library verilog;
use verilog.vl_types.all;
entity dcachel2 is
port(
clock : in vl_logic;
address : in vl_logic_vector(31 downto 0);
data : inout vl_logic_vector(31 downto 0);
read : in vl_logic;
write : in vl_logic;
rs_ex_ok : out vl_logic;
out_address : out vl_logic_vector(31 downto 0);
out_data : inout vl_logic_vector(31 downto 0);
out_read : out vl_logic;
out_write : out vl_logic;
in_databus : in vl_logic_vector(63 downto 0);
out_databus : out vl_logic_vector(63 downto 0);
write_databus : out vl_logic
);
end dcachel2;
|
bsd-2-clause
|
Khan/pygments
|
tests/examplefiles/test.vhdl
|
75
|
4446
|
library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity top_testbench is --test
generic ( -- test
n : integer := 8 -- test
); -- test
end top_testbench; -- test
architecture top_testbench_arch of top_testbench is
component top is
generic (
n : integer
) ;
port (
clk : in std_logic;
rst : in std_logic;
d1 : in std_logic_vector (n-1 downto 0);
d2 : in std_logic_vector (n-1 downto 0);
operation : in std_logic;
result : out std_logic_vector (2*n-1 downto 0)
);
end component;
signal clk : std_logic;
signal rst : std_logic;
signal operation : std_logic;
signal d1 : std_logic_vector (n-1 downto 0);
signal d2 : std_logic_vector (n-1 downto 0);
signal result : std_logic_vector (2*n-1 downto 0);
type test_type is ( a1, a2, a3, a4, a5, a6, a7, a8, a9, a10);
attribute enum_encoding of my_state : type is "001 010 011 100 111";
begin
TESTUNIT : top generic map (n => n)
port map (clk => clk,
rst => rst,
d1 => d1,
d2 => d2,
operation => operation,
result => result);
clock_process : process
begin
clk <= '0';
wait for 5 ns;
clk <= '1';
wait for 5 ns;
end process;
data_process : process
begin
-- test case #1
operation <= '0';
rst <= '1';
wait for 5 ns;
rst <= '0';
wait for 5 ns;
d1 <= std_logic_vector(to_unsigned(60, d1'length));
d2 <= std_logic_vector(to_unsigned(12, d2'length));
wait for 360 ns;
assert (result = std_logic_vector(to_unsigned(720, result'length)))
report "Test case #1 failed" severity error;
-- test case #2
operation <= '0';
rst <= '1';
wait for 5 ns;
rst <= '0';
wait for 5 ns;
d1 <= std_logic_vector(to_unsigned(55, d1'length));
d2 <= std_logic_vector(to_unsigned(1, d2'length));
wait for 360 ns;
assert (result = std_logic_vector(to_unsigned(55, result'length)))
report "Test case #2 failed" severity error;
-- etc
end process;
end top_testbench_arch;
configuration testbench_for_top of top_testbench is
for top_testbench_arch
for TESTUNIT : top
use entity work.top(top_arch);
end for;
end for;
end testbench_for_top;
function compare(A: std_logic, B: std_Logic) return std_logic is
constant pi : real := 3.14159;
constant half_pi : real := pi / 2.0;
constant cycle_time : time := 2 ns;
constant N, N5 : integer := 5;
begin
if (A = '0' and B = '1') then
return B;
else
return A;
end if ;
end compare;
procedure print(P : std_logic_vector(7 downto 0);
U : std_logic_vector(3 downto 0)) is
variable my_line : line;
alias swrite is write [line, string, side, width] ;
begin
swrite(my_line, "sqrt( ");
write(my_line, P);
swrite(my_line, " )= ");
write(my_line, U);
writeline(output, my_line);
end print;
entity add32csa is -- one stage of carry save adder for multiplier
port(
b : in std_logic; -- a multiplier bit
a : in std_logic_vector(31 downto 0); -- multiplicand
sum_in : in std_logic_vector(31 downto 0); -- sums from previous stage
cin : in std_logic_vector(31 downto 0); -- carrys from previous stage
sum_out : out std_logic_vector(31 downto 0); -- sums to next stage
cout : out std_logic_vector(31 downto 0)); -- carrys to next stage
end add32csa;
ARCHITECTURE circuits of add32csa IS
SIGNAL zero : STD_LOGIC_VECTOR(31 downto 0) := X"00000000";
SIGNAL aa : std_logic_vector(31 downto 0) := X"00000000";
COMPONENT fadd -- duplicates entity port
PoRT(a : in std_logic;
b : in std_logic;
cin : in std_logic;
s : out std_logic;
cout : out std_logic);
end comPonent fadd;
begin -- circuits of add32csa
aa <= a when b='1' else zero after 1 ns;
stage: for I in 0 to 31 generate
sta: fadd port map(aa(I), sum_in(I), cin(I) , sum_out(I), cout(I));
end generate stage;
end architecture circuits; -- of add32csa
|
bsd-2-clause
|
timvideos/HDMI2USB-jahanzeb-firmware
|
hdl/jpeg_encoder/design/r_divider.vhd
|
5
|
6166
|
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2009 --
-- --
--------------------------------------------------------------------------------
-- --
-- Title : DIVIDER --
-- Design : Divider using reciprocal table --
-- Author : Michal Krepa --
-- --
--------------------------------------------------------------------------------
-- --
-- File : R_DIVIDER.VHD --
-- Created : Wed 18-03-2009 --
-- --
--------------------------------------------------------------------------------
-- --
--------------------------------------------------------------------------------
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- /// Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
--------------------------------------------------------------------------------
-- MAIN DIVIDER top level
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.All;
use IEEE.NUMERIC_STD.all;
entity r_divider is
port
(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
a : in STD_LOGIC_VECTOR(11 downto 0);
d : in STD_LOGIC_VECTOR(7 downto 0);
q : out STD_LOGIC_VECTOR(11 downto 0)
) ;
end r_divider ;
architecture rtl of r_divider is
signal romr_datao : std_logic_vector(15 downto 0):=(others => '0');
signal romr_addr : std_logic_vector(7 downto 0):=(others => '0');
signal dividend : signed(11 downto 0):=(others => '0');
signal dividend_d1 : unsigned(11 downto 0):=(others => '0');
signal reciprocal : unsigned(15 downto 0):=(others => '0');
signal mult_out : unsigned(27 downto 0):=(others => '0');
signal mult_out_s : signed(11 downto 0):=(others => '0');
signal signbit : std_logic:='0';
signal signbit_d1 : std_logic:='0';
signal signbit_d2 : std_logic:='0';
signal signbit_d3 : std_logic:='0';
signal round : std_logic:='0';
begin
U_ROMR : entity work.ROMR
generic map
(
ROMADDR_W => 8,
ROMDATA_W => 16
)
port map
(
addr => romr_addr,
clk => CLK,
datao => romr_datao
);
romr_addr <= d;
reciprocal <= unsigned(romr_datao);
dividend <= signed(a);
signbit <= dividend(dividend'high);
rdiv : process(clk,rst)
begin
if rst = '1' then
mult_out <= (others => '0');
mult_out_s <= (others => '0');
dividend_d1 <= (others => '0');
q <= (others => '0');
signbit_d1 <= '0';
signbit_d2 <= '0';
signbit_d3 <= '0';
round <= '0';
elsif clk = '1' and clk'event then
signbit_d1 <= signbit;
signbit_d2 <= signbit_d1;
signbit_d3 <= signbit_d2;
if signbit = '1' then
dividend_d1 <= unsigned(0-dividend);
else
dividend_d1 <= unsigned(dividend);
end if;
mult_out <= dividend_d1 * reciprocal;
if signbit_d2 = '0' then
mult_out_s <= resize(signed(mult_out(27 downto 16)),mult_out_s'length);
else
mult_out_s <= resize(0-signed(mult_out(27 downto 16)),mult_out_s'length);
end if;
round <= mult_out(15);
if signbit_d3 = '0' then
if round = '1' then
q <= std_logic_vector(mult_out_s + 1);
else
q <= std_logic_vector(mult_out_s);
end if;
else
if round = '1' then
q <= std_logic_vector(mult_out_s - 1);
else
q <= std_logic_vector(mult_out_s);
end if;
end if;
end if;
end process;
end rtl;
|
bsd-2-clause
|
timvideos/HDMI2USB-jahanzeb-firmware
|
ipcore_dir/ddr2ram/example_design/rtl/traffic_gen/afifo.vhd
|
20
|
9200
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: afifo.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:16:34 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: A generic synchronous fifo.
-- Reference:
-- Revision History: 2009/01/09 corrected signal "buf_avail" and "almost_full" equation.
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
ENTITY afifo IS
GENERIC (
TCQ : TIME := 100 ps;
DSIZE : INTEGER := 32;
FIFO_DEPTH : INTEGER := 16;
ASIZE : INTEGER := 4;
SYNC : INTEGER := 1
);
PORT (
wr_clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
wr_en : IN STD_LOGIC;
wr_data : IN STD_LOGIC_VECTOR(DSIZE - 1 DOWNTO 0);
rd_en : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_data : OUT STD_LOGIC_VECTOR(DSIZE - 1 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC
);
END afifo;
ARCHITECTURE trans OF afifo IS
TYPE mem_array IS ARRAY (0 TO FIFO_DEPTH ) OF STD_LOGIC_VECTOR(DSIZE - 1 DOWNTO 0);
SIGNAL mem : mem_array;
SIGNAL rd_gray_nxt : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL rd_gray : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL rd_capture_ptr : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL pre_rd_capture_gray_ptr : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL rd_capture_gray_ptr : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL wr_gray : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL wr_gray_nxt : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL wr_capture_ptr : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL pre_wr_capture_gray_ptr : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL wr_capture_gray_ptr : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL buf_avail : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL buf_filled : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL wr_addr : STD_LOGIC_VECTOR(ASIZE - 1 DOWNTO 0);
SIGNAL rd_addr : STD_LOGIC_VECTOR(ASIZE - 1 DOWNTO 0);
SIGNAL wr_ptr : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL rd_ptr : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL i : INTEGER;
SIGNAL j : INTEGER;
SIGNAL k : INTEGER;
SIGNAL rd_strobe : STD_LOGIC;
SIGNAL n : INTEGER;
SIGNAL rd_ptr_tmp : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL wbin : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL wgraynext : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL wbinnext : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL ZERO : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL ONE : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
-- Declare intermediate signals for referenced outputs
SIGNAL full_xhdl1 : STD_LOGIC;
SIGNAL almost_full_int : STD_LOGIC;
SIGNAL empty_xhdl0 : STD_LOGIC;
BEGIN
-- Drive referenced outputs
ZERO <= std_logic_vector(to_unsigned(0,(ASIZE+1)));
ONE <= std_logic_vector(to_unsigned(1,(ASIZE+1)));
full <= full_xhdl1;
empty <= empty_xhdl0;
xhdl3 : IF (SYNC = 1) GENERATE
PROCESS (rd_ptr)
BEGIN
rd_capture_ptr <= rd_ptr;
END PROCESS;
END GENERATE;
xhdl4 : IF (SYNC = 1) GENERATE
PROCESS (wr_ptr)
BEGIN
wr_capture_ptr <= wr_ptr;
END PROCESS;
END GENERATE;
wr_addr <= wr_ptr(ASIZE-1 DOWNTO 0);
rd_data <= mem(conv_integer(rd_addr));
PROCESS (wr_clk)
BEGIN
IF (wr_clk'EVENT AND wr_clk = '1') THEN
IF ((wr_en AND NOT(full_xhdl1)) = '1') THEN
mem(to_integer(unsigned(wr_addr))) <= wr_data;
END IF;
END IF;
END PROCESS;
rd_addr <= rd_ptr(ASIZE - 1 DOWNTO 0);
rd_strobe <= rd_en AND NOT(empty_xhdl0);
PROCESS (rd_ptr)
BEGIN
rd_gray_nxt(ASIZE) <= rd_ptr(ASIZE);
FOR n IN 0 TO ASIZE - 1 LOOP
rd_gray_nxt(n) <= rd_ptr(n) XOR rd_ptr(n + 1);
END LOOP;
END PROCESS;
PROCESS (rd_clk)
BEGIN
IF (rd_clk'EVENT AND rd_clk = '1') THEN
IF (rst = '1') THEN
rd_ptr <= (others=> '0');
rd_gray <= (others=> '0');
ELSE
IF (rd_strobe = '1') THEN
rd_ptr <= rd_ptr + 1;
END IF;
rd_ptr_tmp <= rd_ptr;
rd_gray <= rd_gray_nxt;
END IF;
END IF;
END PROCESS;
buf_filled <= wr_capture_ptr - rd_ptr;
PROCESS (rd_clk)
BEGIN
IF (rd_clk'EVENT AND rd_clk = '1') THEN
IF (rst = '1') THEN
empty_xhdl0 <= '1';
ELSIF ((buf_filled = ZERO) OR (buf_filled = ONE AND rd_strobe = '1')) THEN
empty_xhdl0 <= '1';
ELSE
empty_xhdl0 <= '0';
END IF;
END IF;
END PROCESS;
PROCESS (rd_clk)
BEGIN
IF (rd_clk'EVENT AND rd_clk = '1') THEN
IF (rst = '1') THEN
wr_ptr <= (others => '0');
wr_gray <= (others => '0');
ELSE
IF (wr_en = '1') THEN
wr_ptr <= wr_ptr + 1;
END IF;
wr_gray <= wr_gray_nxt;
END IF;
END IF;
END PROCESS;
PROCESS (wr_ptr)
BEGIN
wr_gray_nxt(ASIZE) <= wr_ptr(ASIZE);
FOR n IN 0 TO ASIZE - 1 LOOP
wr_gray_nxt(n) <= wr_ptr(n) XOR wr_ptr(n + 1);
END LOOP;
END PROCESS;
buf_avail <= rd_capture_ptr + FIFO_DEPTH - wr_ptr;
PROCESS (wr_clk)
BEGIN
IF (wr_clk'EVENT AND wr_clk = '1') THEN
IF (rst = '1') THEN
full_xhdl1 <= '0';
ELSIF ((buf_avail = ZERO) OR (buf_avail = ONE AND wr_en = '1')) THEN
full_xhdl1 <= '1';
ELSE
full_xhdl1 <= '0';
END IF;
END IF;
END PROCESS;
almost_full <= almost_full_int;
PROCESS (wr_clk)
BEGIN
IF (wr_clk'EVENT AND wr_clk = '1') THEN
IF (rst = '1') THEN
almost_full_int <= '0';
ELSIF (buf_avail <= 3 AND wr_en = '1') THEN --FIFO_DEPTH
almost_full_int <= '1';
ELSE
almost_full_int <= '0';
END IF;
END IF;
END PROCESS;
END trans;
|
bsd-2-clause
|
timvideos/HDMI2USB-jahanzeb-firmware
|
ipcore_dir/bytefifo/simulation/bytefifo_pctrl.vhd
|
3
|
20422
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bytefifo_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.bytefifo_pkg.ALL;
ENTITY bytefifo_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF bytefifo_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL reset_ex1 : STD_LOGIC := '0';
SIGNAL reset_ex2 : STD_LOGIC := '0';
SIGNAL reset_ex3 : STD_LOGIC := '0';
SIGNAL ae_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL af_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL sim_done_d1 : STD_LOGIC := '0';
SIGNAL sim_done_wr1 : STD_LOGIC := '0';
SIGNAL sim_done_wr2 : STD_LOGIC := '0';
SIGNAL empty_d1 : STD_LOGIC := '0';
SIGNAL empty_wr_dom1 : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL state_rd_dom1 : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '0';
SIGNAL rd_en_wr1 : STD_LOGIC := '0';
SIGNAL wr_en_d1 : STD_LOGIC := '0';
SIGNAL wr_en_rd1 : STD_LOGIC := '0';
SIGNAL full_chk_d1 : STD_LOGIC := '0';
SIGNAL full_chk_rd1 : STD_LOGIC := '0';
SIGNAL empty_wr_dom2 : STD_LOGIC := '0';
SIGNAL state_rd_dom2 : STD_LOGIC := '0';
SIGNAL state_rd_dom3 : STD_LOGIC := '0';
SIGNAL rd_en_wr2 : STD_LOGIC := '0';
SIGNAL wr_en_rd2 : STD_LOGIC := '0';
SIGNAL full_chk_rd2 : STD_LOGIC := '0';
SIGNAL reset_en_d1 : STD_LOGIC := '0';
SIGNAL reset_en_rd1 : STD_LOGIC := '0';
SIGNAL reset_en_rd2 : STD_LOGIC := '0';
SIGNAL data_chk_wr_d1 : STD_LOGIC := '0';
SIGNAL data_chk_rd1 : STD_LOGIC := '0';
SIGNAL data_chk_rd2 : STD_LOGIC := '0';
SIGNAL full_d1 : STD_LOGIC := '0';
SIGNAL full_rd_dom1 : STD_LOGIC := '0';
SIGNAL full_rd_dom2 : STD_LOGIC := '0';
SIGNAL af_chk_d1 : STD_LOGIC := '0';
SIGNAL af_chk_rd1 : STD_LOGIC := '0';
SIGNAL af_chk_rd2 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_rd2 & empty_chk_i & af_chk_rd2 & ae_chk_i;
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_wr2 = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
rdw_gt_wrw <= (OTHERS => '1');
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0' AND state_rd_dom3 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
-- Reset pulse extension require for FULL flags checks
-- FULL flag may stay high for 3 clocks after reset is removed.
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
reset_ex1 <= '1';
reset_ex2 <= '1';
reset_ex3 <= '1';
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
reset_ex1 <= '0';
reset_ex2 <= reset_ex1;
reset_ex3 <= reset_ex2;
END IF;
END PROCESS;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_wr2 = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_rd2 = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 50 ns;
PRC_RD_EN <= prc_re_i AFTER 100 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-- Almost full flag checks
PROCESS(WR_CLK,reset_ex3)
BEGIN
IF(reset_ex3 = '1') THEN
af_chk_i <= '0';
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
IF((FULL = '1' AND ALMOST_FULL = '0') OR (empty_wr_dom2 = '1' AND ALMOST_FULL = '1' AND C_WR_PNTR_WIDTH > 4)) THEN
af_chk_i <= '1';
ELSE
af_chk_i <= '0';
END IF;
END IF;
END PROCESS;
-- Almost empty flag checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
ae_chk_i <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF((EMPTY = '1' AND ALMOST_EMPTY = '0') OR
(state = '1' AND full_rd_dom2 = '1' AND ALMOST_EMPTY = '1')) THEN
ae_chk_i <= '1';
ELSE
ae_chk_i <= '0';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- SYNCHRONIZERS B/W WRITE AND READ DOMAINS
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
empty_wr_dom1 <= '1';
empty_wr_dom2 <= '1';
state_d1 <= '0';
wr_en_d1 <= '0';
rd_en_wr1 <= '0';
rd_en_wr2 <= '0';
full_chk_d1 <= '0';
af_chk_d1 <= '0';
full_d1 <= '0';
reset_en_d1 <= '0';
sim_done_wr1 <= '0';
sim_done_wr2 <= '0';
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
sim_done_wr1 <= sim_done_d1;
sim_done_wr2 <= sim_done_wr1;
reset_en_d1 <= reset_en_i;
full_d1 <= FULL;
state_d1 <= state;
empty_wr_dom1 <= empty_d1;
empty_wr_dom2 <= empty_wr_dom1;
wr_en_d1 <= wr_en_i;
rd_en_wr1 <= rd_en_d1;
rd_en_wr2 <= rd_en_wr1;
full_chk_d1 <= full_chk_i;
af_chk_d1 <= af_chk_i;
END IF;
END PROCESS;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_d1 <= '1';
state_rd_dom1 <= '0';
state_rd_dom2 <= '0';
state_rd_dom3 <= '0';
wr_en_rd1 <= '0';
wr_en_rd2 <= '0';
rd_en_d1 <= '0';
full_chk_rd1 <= '0';
full_chk_rd2 <= '0';
af_chk_rd1 <= '0';
af_chk_rd2 <= '0';
full_rd_dom1 <= '0';
full_rd_dom2 <= '0';
reset_en_rd1 <= '0';
reset_en_rd2 <= '0';
sim_done_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
sim_done_d1 <= sim_done_i;
reset_en_rd1 <= reset_en_d1;
reset_en_rd2 <= reset_en_rd1;
empty_d1 <= EMPTY;
rd_en_d1 <= rd_en_i;
state_rd_dom1 <= state_d1;
state_rd_dom2 <= state_rd_dom1;
state_rd_dom3 <= state_rd_dom2;
wr_en_rd1 <= wr_en_d1;
wr_en_rd2 <= wr_en_rd1;
full_chk_rd1 <= full_chk_d1;
full_chk_rd2 <= full_chk_rd1;
af_chk_rd1 <= af_chk_d1;
af_chk_rd2 <= af_chk_rd1;
full_rd_dom1 <= full_d1;
full_rd_dom2 <= full_rd_dom1;
END IF;
END PROCESS;
RESET_EN <= reset_en_rd2;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:bytefifo_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_wr2 = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:bytefifo_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_rd2 = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND empty_wr_dom2 = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(empty_wr_dom2 = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
|
bsd-2-clause
|
timvideos/HDMI2USB-jahanzeb-firmware
|
ipcore_dir/edidram/simulation/checker.vhd
|
6
|
5607
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_2 Core - Checker
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: checker.vhd
--
-- Description:
-- Checker
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.BMG_TB_PKG.ALL;
ENTITY CHECKER IS
GENERIC ( WRITE_WIDTH : INTEGER :=32;
READ_WIDTH : INTEGER :=32
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR (READ_WIDTH-1 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END CHECKER;
ARCHITECTURE CHECKER_ARCH OF CHECKER IS
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
SIGNAL DATA_IN_R: STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
SIGNAL EN_R : STD_LOGIC := '0';
SIGNAL EN_2R : STD_LOGIC := '0';
--DATA PART CNT DEFINES THE ASPECT RATIO AND GIVES THE INFO TO THE DATA GENERATOR TO PROVIDE THE DATA EITHER IN PARTS OR COMPLETE DATA IN ONE SHOT
--IF READ_WIDTH > WRITE_WIDTH DIVROUNDUP RESULTS IN '1' AND DATA GENERATOR GIVES THE DATAOUT EQUALS TO MAX OF (WRITE_WIDTH, READ_WIDTH)
--IF READ_WIDTH < WRITE-WIDTH DIVROUNDUP RESULTS IN > '1' AND DATA GENERATOR GIVES THE DATAOUT IN TERMS OF PARTS(EG 4 PARTS WHEN WRITE_WIDTH 32 AND READ WIDTH 8)
CONSTANT DATA_PART_CNT: INTEGER:= DIVROUNDUP(WRITE_WIDTH,READ_WIDTH);
CONSTANT MAX_WIDTH: INTEGER:= IF_THEN_ELSE((WRITE_WIDTH>READ_WIDTH),WRITE_WIDTH,READ_WIDTH);
SIGNAL ERR_HOLD : STD_LOGIC :='0';
SIGNAL ERR_DET : STD_LOGIC :='0';
BEGIN
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST= '1') THEN
EN_R <= '0';
EN_2R <= '0';
DATA_IN_R <= (OTHERS=>'0');
ELSE
EN_R <= EN;
EN_2R <= EN_R;
DATA_IN_R <= DATA_IN;
END IF;
END IF;
END PROCESS;
EXPECTED_DATA_GEN_INST:ENTITY work.DATA_GEN
GENERIC MAP ( DATA_GEN_WIDTH =>MAX_WIDTH,
DOUT_WIDTH => READ_WIDTH,
DATA_PART_CNT => DATA_PART_CNT,
SEED => 2
)
PORT MAP (
CLK => CLK,
RST => RST,
EN => EN_2R,
DATA_OUT => EXPECTED_DATA
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(EN_2R='1') THEN
IF(EXPECTED_DATA = DATA_IN_R) THEN
ERR_DET<='0';
ELSE
ERR_DET<= '1';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(CLK,RST)
BEGIN
IF(RST='1') THEN
ERR_HOLD <= '0';
ELSIF(RISING_EDGE(CLK)) THEN
ERR_HOLD <= ERR_HOLD OR ERR_DET ;
END IF;
END PROCESS;
STATUS <= ERR_HOLD;
END ARCHITECTURE;
|
bsd-2-clause
|
timvideos/HDMI2USB-jahanzeb-firmware
|
hdl/jpeg_encoder/design/HostIF.vhd
|
3
|
11304
|
-------------------------------------------------------------------------------
-- File Name : HostIF.vhd
--
-- Project : JPEG_ENC
--
-- Module : HostIF
--
-- Content : Host Interface (Xilinx OPB v2.1)
--
-- Description :
--
-- Spec. :
--
-- Author : Michal Krepa
--
-------------------------------------------------------------------------------
-- History :
-- 20090301: (MK): Initial Creation.
-------------------------------------------------------------------------------
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- /// Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity HostIF is
port
(
CLK : in std_logic;
RST : in std_logic;
-- OPB
OPB_ABus : in std_logic_vector(31 downto 0);
OPB_BE : in std_logic_vector(3 downto 0);
OPB_DBus_in : in std_logic_vector(31 downto 0);
OPB_RNW : in std_logic;
OPB_select : in std_logic;
OPB_DBus_out : out std_logic_vector(31 downto 0);
OPB_XferAck : out std_logic;
OPB_retry : out std_logic;
OPB_toutSup : out std_logic;
OPB_errAck : out std_logic;
-- Quantizer RAM
qdata : out std_logic_vector(7 downto 0);
qaddr : out std_logic_vector(6 downto 0);
qwren : out std_logic;
-- CTRL
jpeg_ready : in std_logic;
jpeg_busy : in std_logic;
-- ByteStuffer
outram_base_addr : out std_logic_vector(9 downto 0);
num_enc_bytes : in std_logic_vector(23 downto 0);
-- others
img_size_x : out std_logic_vector(15 downto 0);
img_size_y : out std_logic_vector(15 downto 0);
img_size_wr : out std_logic;
sof : out std_logic
);
end entity HostIF;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ARCHITECTURE ------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture RTL of HostIF is
constant C_ENC_START_REG : std_logic_vector(31 downto 0) := X"0000_0000";
constant C_IMAGE_SIZE_REG : std_logic_vector(31 downto 0) := X"0000_0004";
constant C_IMAGE_RAM_ACCESS_REG : std_logic_vector(31 downto 0) := X"0000_0008";
constant C_ENC_STS_REG : std_logic_vector(31 downto 0) := X"0000_000C";
constant C_COD_DATA_ADDR_REG : std_logic_vector(31 downto 0) := X"0000_0010";
constant C_ENC_LENGTH_REG : std_logic_vector(31 downto 0) := X"0000_0014";
constant C_QUANTIZER_RAM_LUM : std_logic_vector(31 downto 0) :=
X"0000_01" & "------00";
constant C_QUANTIZER_RAM_CHR : std_logic_vector(31 downto 0) :=
X"0000_02" & "------00";
constant C_IMAGE_RAM : std_logic_vector(31 downto 0) :=
X"001" & "------------------00";
constant C_IMAGE_RAM_BASE : unsigned(31 downto 0) := X"0010_0000";
signal enc_start_reg : std_logic_vector(31 downto 0);
signal image_size_reg : std_logic_vector(31 downto 0);
signal image_ram_access_reg : std_logic_vector(31 downto 0);
signal enc_sts_reg : std_logic_vector(31 downto 0);
signal cod_data_addr_reg : std_logic_vector(31 downto 0);
signal enc_length_reg : std_logic_vector(31 downto 0);
signal rd_dval : std_logic;
signal data_read : std_logic_vector(31 downto 0);
signal write_done : std_logic;
signal OPB_select_d : std_logic;
-------------------------------------------------------------------------------
-- Architecture: begin
-------------------------------------------------------------------------------
begin
OPB_retry <= '0';
OPB_toutSup <= '0';
OPB_errAck <= '0';
img_size_x <= image_size_reg(31 downto 16);
img_size_y <= image_size_reg(15 downto 0);
outram_base_addr <= cod_data_addr_reg(outram_base_addr'range);
-------------------------------------------------------------------
-- OPB read
-------------------------------------------------------------------
p_read : process(CLK, RST)
begin
if RST = '1' then
OPB_DBus_out <= (others => '0');
rd_dval <= '0';
data_read <= (others => '0');
elsif CLK'event and CLK = '1' then
rd_dval <= '0';
OPB_DBus_out <= data_read;
if OPB_select = '1' and OPB_select_d = '0' then
-- only double word transactions are be supported
if OPB_RNW = '1' and OPB_BE = X"F" then
case OPB_ABus is
when C_ENC_START_REG =>
data_read <= enc_start_reg;
rd_dval <= '1';
when C_IMAGE_SIZE_REG =>
data_read <= image_size_reg;
rd_dval <= '1';
when C_IMAGE_RAM_ACCESS_REG =>
data_read <= image_ram_access_reg;
rd_dval <= '1';
when C_ENC_STS_REG =>
data_read <= enc_sts_reg;
rd_dval <= '1';
when C_COD_DATA_ADDR_REG =>
data_read <= cod_data_addr_reg;
rd_dval <= '1';
when C_ENC_LENGTH_REG =>
data_read <= enc_length_reg;
rd_dval <= '1';
when others =>
data_read <= (others => '0');
end case;
end if;
end if;
end if;
end process;
-------------------------------------------------------------------
-- OPB write
-------------------------------------------------------------------
p_write : process(CLK, RST)
begin
if RST = '1' then
qwren <= '0';
write_done <= '0';
enc_start_reg <= (others => '0');
image_size_reg <= (others => '0');
image_ram_access_reg <= (others => '0');
enc_sts_reg <= (others => '0');
cod_data_addr_reg <= (others => '0');
enc_length_reg <= (others => '0');
qdata <= (others => '0');
qaddr <= (others => '0');
OPB_select_d <= '0';
sof <= '0';
img_size_wr <= '0';
elsif CLK'event and CLK = '1' then
qwren <= '0';
write_done <= '0';
sof <= '0';
img_size_wr <= '0';
OPB_select_d <= OPB_select;
if OPB_select = '1' and OPB_select_d = '0' then
-- only double word transactions are be supported
if OPB_RNW = '0' and OPB_BE = X"F" then
case OPB_ABus is
when C_ENC_START_REG =>
enc_start_reg <= OPB_DBus_in;
write_done <= '1';
if OPB_DBus_in(0) = '1' then
sof <= '1';
end if;
when C_IMAGE_SIZE_REG =>
image_size_reg <= OPB_DBus_in;
img_size_wr <= '1';
write_done <= '1';
when C_IMAGE_RAM_ACCESS_REG =>
image_ram_access_reg <= OPB_DBus_in;
write_done <= '1';
when C_ENC_STS_REG =>
enc_sts_reg <= (others => '0');
write_done <= '1';
when C_COD_DATA_ADDR_REG =>
cod_data_addr_reg <= OPB_DBus_in;
write_done <= '1';
when C_ENC_LENGTH_REG =>
--enc_length_reg <= OPB_DBus_in;
write_done <= '1';
when others =>
null;
end case;
if std_match(OPB_ABus, C_QUANTIZER_RAM_LUM) then
qdata <= OPB_DBus_in(qdata'range);
qaddr <= '0' & OPB_ABus(qaddr'high+2-1 downto 2);
qwren <= '1';
write_done <= '1';
end if;
if std_match(OPB_ABus, C_QUANTIZER_RAM_CHR) then
qdata <= OPB_DBus_in(qdata'range);
qaddr <= '1' & OPB_ABus(qaddr'high+2-1 downto 2);
qwren <= '1';
write_done <= '1';
end if;
end if;
end if;
-- special handling of status reg
if jpeg_ready = '1' then
-- set jpeg done flag
enc_sts_reg(1) <= '1';
end if;
enc_sts_reg(0) <= jpeg_busy;
enc_length_reg <= (others => '0');
enc_length_reg(num_enc_bytes'range) <= num_enc_bytes;
end if;
end process;
-------------------------------------------------------------------
-- transfer ACK
-------------------------------------------------------------------
p_ack : process(CLK, RST)
begin
if RST = '1' then
OPB_XferAck <= '0';
elsif CLK'event and CLK = '1' then
OPB_XferAck <= rd_dval or write_done;
end if;
end process;
end architecture RTL;
-------------------------------------------------------------------------------
-- Architecture: end
-------------------------------------------------------------------------------
|
bsd-2-clause
|
timvideos/HDMI2USB-jahanzeb-firmware
|
ipcore_dir/ddr2ram/example_design/rtl/memc3_tb_top.vhd
|
6
|
29617
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.92
-- \ \ Application : MIG
-- / / Filename : memc3_tb_top.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:56 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
--Device : Spartan-6
--Design Name : DDR/DDR2/DDR3/LPDDR
--Purpose : This is top level module for test bench. which instantiates
-- init_mem_pattern_ctr and mcb_traffic_gen modules for each user
-- port.
--Reference :
--Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity memc3_tb_top is
generic
(
C_P0_MASK_SIZE : integer := 4;
C_P0_DATA_PORT_SIZE : integer := 32;
C_P1_MASK_SIZE : integer := 4;
C_P1_DATA_PORT_SIZE : integer := 32;
C_MEM_BURST_LEN : integer := 8;
C_SIMULATION : string := "FALSE";
C_MEM_NUM_COL_BITS : integer := 11;
C_NUM_DQ_PINS : integer := 8;
C_SMALL_DEVICE : string := "FALSE";
C_p2_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000100";
C_p2_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
C_p2_END_ADDRESS : std_logic_vector(31 downto 0) := X"000002ff";
C_p2_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"fffffc00";
C_p2_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00000100";
C_p3_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000500";
C_p3_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
C_p3_END_ADDRESS : std_logic_vector(31 downto 0) := X"000006ff";
C_p3_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"fffff800";
C_p3_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00000500"
);
port
(
clk0 : in std_logic;
rst0 : in std_logic;
calib_done : in std_logic;
p2_mcb_cmd_en_o : out std_logic;
p2_mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
p2_mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
p2_mcb_cmd_addr_o : out std_logic_vector(29 downto 0);
p2_mcb_cmd_full_i : in std_logic;
p2_mcb_rd_en_o : out std_logic;
p2_mcb_rd_data_i : in std_logic_vector(31 downto 0);
p2_mcb_rd_empty_i : in std_logic;
p2_mcb_rd_fifo_counts : in std_logic_vector(6 downto 0);
p3_mcb_cmd_en_o : out std_logic;
p3_mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
p3_mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
p3_mcb_cmd_addr_o : out std_logic_vector(29 downto 0);
p3_mcb_cmd_full_i : in std_logic;
p3_mcb_wr_en_o : out std_logic;
p3_mcb_wr_mask_o : out std_logic_vector(3 downto 0);
p3_mcb_wr_data_o : out std_logic_vector(31 downto 0);
p3_mcb_wr_full_i : in std_logic;
p3_mcb_wr_fifo_counts : in std_logic_vector(6 downto 0);
vio_modify_enable : in std_logic;
vio_data_mode_value : in std_logic_vector(2 downto 0);
vio_addr_mode_value : in std_logic_vector(2 downto 0);
cmp_error : out std_logic;
cmp_data : out std_logic_vector(31 downto 0);
cmp_data_valid : out std_logic;
error : out std_logic;
error_status : out std_logic_vector(127 downto 0)
);
end memc3_tb_top;
architecture arc of memc3_tb_top is
function ERROR_DQWIDTH (val_i : integer) return integer is
begin
if (val_i = 4) then
return 1;
else
return val_i/8;
end if;
end function ERROR_DQWIDTH;
constant DQ_ERROR_WIDTH : integer := ERROR_DQWIDTH(C_NUM_DQ_PINS);
component init_mem_pattern_ctr IS
generic (
FAMILY : string;
BEGIN_ADDRESS : std_logic_vector(31 downto 0);
END_ADDRESS : std_logic_vector(31 downto 0);
DWIDTH : integer;
CMD_SEED_VALUE : std_logic_vector(31 downto 0);
DATA_SEED_VALUE : std_logic_vector(31 downto 0);
DATA_MODE : std_logic_vector(3 downto 0);
PORT_MODE : string
);
PORT (
clk_i : in std_logic;
rst_i : in std_logic;
mcb_cmd_bl_i : in std_logic_vector(5 downto 0);
mcb_cmd_en_i : in std_logic;
mcb_cmd_instr_i : in std_logic_vector(2 downto 0);
mcb_init_done_i : in std_logic;
mcb_wr_en_i : in std_logic;
vio_modify_enable : in std_logic;
vio_data_mode_value : in std_logic_vector(2 downto 0);
vio_addr_mode_value : in std_logic_vector(2 downto 0);
vio_bl_mode_value : in STD_LOGIC_VECTOR(1 downto 0);
vio_fixed_bl_value : in STD_LOGIC_VECTOR(5 downto 0);
cmp_error : in std_logic;
run_traffic_o : out std_logic;
start_addr_o : out std_logic_vector(31 downto 0);
end_addr_o : out std_logic_vector(31 downto 0);
cmd_seed_o : out std_logic_vector(31 downto 0);
data_seed_o : out std_logic_vector(31 downto 0);
load_seed_o : out std_logic;
addr_mode_o : out std_logic_vector(2 downto 0);
instr_mode_o : out std_logic_vector(3 downto 0);
bl_mode_o : out std_logic_vector(1 downto 0);
data_mode_o : out std_logic_vector(3 downto 0);
mode_load_o : out std_logic;
fixed_bl_o : out std_logic_vector(5 downto 0);
fixed_instr_o : out std_logic_vector(2 downto 0);
fixed_addr_o : out std_logic_vector(31 downto 0)
);
end component;
component mcb_traffic_gen is
generic (
FAMILY : string;
SIMULATION : string;
MEM_BURST_LEN : integer;
PORT_MODE : string;
DATA_PATTERN : string;
CMD_PATTERN : string;
ADDR_WIDTH : integer;
CMP_DATA_PIPE_STAGES : integer;
MEM_COL_WIDTH : integer;
NUM_DQ_PINS : integer;
DQ_ERROR_WIDTH : integer;
DWIDTH : integer;
PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0);
PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0);
PRBS_EADDR : std_logic_vector(31 downto 0);
PRBS_SADDR : std_logic_vector(31 downto 0)
);
port (
clk_i : in std_logic;
rst_i : in std_logic;
run_traffic_i : in std_logic;
manual_clear_error : in std_logic;
-- *** runtime parameter ***
start_addr_i : in std_logic_vector(31 downto 0);
end_addr_i : in std_logic_vector(31 downto 0);
cmd_seed_i : in std_logic_vector(31 downto 0);
data_seed_i : in std_logic_vector(31 downto 0);
load_seed_i : in std_logic;
addr_mode_i : in std_logic_vector(2 downto 0);
instr_mode_i : in std_logic_vector(3 downto 0);
bl_mode_i : in std_logic_vector(1 downto 0);
data_mode_i : in std_logic_vector(3 downto 0);
mode_load_i : in std_logic;
-- fixed pattern inputs interface
fixed_bl_i : in std_logic_vector(5 downto 0);
fixed_instr_i : in std_logic_vector(2 downto 0);
fixed_addr_i : in std_logic_vector(31 downto 0);
fixed_data_i : IN STD_LOGIC_VECTOR(DWIDTH-1 DOWNTO 0);
bram_cmd_i : in std_logic_vector(38 downto 0);
bram_valid_i : in std_logic;
bram_rdy_o : out std_logic;
--///////////////////////////////////////////////////////////////////////////
-- MCB INTERFACE
-- interface to mcb command port
mcb_cmd_en_o : out std_logic;
mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
mcb_cmd_addr_o : out std_logic_vector(ADDR_WIDTH - 1 downto 0);
mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
mcb_cmd_full_i : in std_logic;
-- interface to mcb wr data port
mcb_wr_en_o : out std_logic;
mcb_wr_data_o : out std_logic_vector(DWIDTH - 1 downto 0);
mcb_wr_mask_o : out std_logic_vector((DWIDTH / 8) - 1 downto 0);
mcb_wr_data_end_o : OUT std_logic;
mcb_wr_full_i : in std_logic;
mcb_wr_fifo_counts : in std_logic_vector(6 downto 0);
-- interface to mcb rd data port
mcb_rd_en_o : out std_logic;
mcb_rd_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
mcb_rd_empty_i : in std_logic;
mcb_rd_fifo_counts : in std_logic_vector(6 downto 0);
--///////////////////////////////////////////////////////////////////////////
-- status feedback
counts_rst : in std_logic;
wr_data_counts : out std_logic_vector(47 downto 0);
rd_data_counts : out std_logic_vector(47 downto 0);
cmp_data : out std_logic_vector(DWIDTH - 1 downto 0);
cmp_data_valid : out std_logic;
cmp_error : out std_logic;
error : out std_logic;
error_status : out std_logic_vector(64 + (2 * DWIDTH - 1) downto 0);
mem_rd_data : out std_logic_vector(DWIDTH - 1 downto 0);
dq_error_bytelane_cmp : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0);
cumlative_dq_lane_error : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0)
);
end component;
-- Function to determine the number of data patterns to be generated
function DATA_PATTERN_CALC return string is
begin
if (C_SMALL_DEVICE = "FALSE") then
return "DGEN_ALL";
else
return "DGEN_ADDR";
end if;
end function;
constant FAMILY : string := "SPARTAN6";
constant DATA_PATTERN : string := DATA_PATTERN_CALC;
constant CMD_PATTERN : string := "CGEN_ALL";
constant ADDR_WIDTH : integer := 30;
constant CMP_DATA_PIPE_STAGES : integer := 0;
constant PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00007000";
constant PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"FFFF8000";
constant PRBS_SADDR : std_logic_vector(31 downto 0) := X"00005000";
constant PRBS_EADDR : std_logic_vector(31 downto 0) := X"00007fff";
constant BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000000";
constant END_ADDRESS : std_logic_vector(31 downto 0) := X"00000fff";
constant DATA_MODE : std_logic_vector(3 downto 0) := "0010";
constant p2_DWIDTH : integer := 32;
constant p3_DWIDTH : integer := 32;
constant p2_PORT_MODE : string := "RD_MODE";
constant p3_PORT_MODE : string := "WR_MODE";
signal p0_mcb_cmd_addr_o_int : std_logic_vector(ADDR_WIDTH - 1 DOWNTO 0);
signal p0_mcb_cmd_bl_o_int : std_logic_vector(5 DOWNTO 0);
signal p0_mcb_cmd_en_o_int : std_logic;
signal p0_mcb_cmd_instr_o_int : std_logic_vector(2 DOWNTO 0);
signal p0_mcb_wr_en_o_int : std_logic;
--p2 Signal declarations
signal p2_tg_run_traffic : std_logic;
signal p2_tg_start_addr : std_logic_vector(31 downto 0);
signal p2_tg_end_addr : std_logic_vector(31 downto 0);
signal p2_tg_cmd_seed : std_logic_vector(31 downto 0);
signal p2_tg_data_seed : std_logic_vector(31 downto 0);
signal p2_tg_load_seed : std_logic;
signal p2_tg_addr_mode : std_logic_vector(2 downto 0);
signal p2_tg_instr_mode : std_logic_vector(3 downto 0);
signal p2_tg_bl_mode : std_logic_vector(1 downto 0);
signal p2_tg_data_mode : std_logic_vector(3 downto 0);
signal p2_tg_mode_load : std_logic;
signal p2_tg_fixed_bl : std_logic_vector(5 downto 0);
signal p2_tg_fixed_instr : std_logic_vector(2 downto 0);
signal p2_tg_fixed_addr : std_logic_vector(31 downto 0);
signal p2_error_status : std_logic_vector(64 + (2*p2_DWIDTH - 1) downto 0);
signal p2_error : std_logic;
signal p2_cmp_error : std_logic;
signal p2_cmp_data : std_logic_vector(p2_DWIDTH-1 downto 0);
signal p2_cmp_data_valid : std_logic;
signal p2_mcb_cmd_en_o_int : std_logic;
signal p2_mcb_cmd_instr_o_int : std_logic_vector(2 downto 0);
signal p2_mcb_cmd_bl_o_int : std_logic_vector(5 downto 0);
signal p2_mcb_cmd_addr_o_int : std_logic_vector(29 downto 0);
signal p2_mcb_wr_en_o_int : std_logic;
--p3 Signal declarations
signal p3_tg_run_traffic : std_logic;
signal p3_tg_start_addr : std_logic_vector(31 downto 0);
signal p3_tg_end_addr : std_logic_vector(31 downto 0);
signal p3_tg_cmd_seed : std_logic_vector(31 downto 0);
signal p3_tg_data_seed : std_logic_vector(31 downto 0);
signal p3_tg_load_seed : std_logic;
signal p3_tg_addr_mode : std_logic_vector(2 downto 0);
signal p3_tg_instr_mode : std_logic_vector(3 downto 0);
signal p3_tg_bl_mode : std_logic_vector(1 downto 0);
signal p3_tg_data_mode : std_logic_vector(3 downto 0);
signal p3_tg_mode_load : std_logic;
signal p3_tg_fixed_bl : std_logic_vector(5 downto 0);
signal p3_tg_fixed_instr : std_logic_vector(2 downto 0);
signal p3_tg_fixed_addr : std_logic_vector(31 downto 0);
signal p3_error_status : std_logic_vector(64 + (2*p3_DWIDTH - 1) downto 0);
signal p3_error : std_logic;
signal p3_cmp_error : std_logic;
signal p3_cmp_data : std_logic_vector(p3_DWIDTH-1 downto 0);
signal p3_cmp_data_valid : std_logic;
signal p3_mcb_cmd_en_o_int : std_logic;
signal p3_mcb_cmd_instr_o_int : std_logic_vector(2 downto 0);
signal p3_mcb_cmd_bl_o_int : std_logic_vector(5 downto 0);
signal p3_mcb_cmd_addr_o_int : std_logic_vector(29 downto 0);
signal p3_mcb_wr_en_o_int : std_logic;
signal p2_mcb_wr_en_o : std_logic;
signal p2_mcb_wr_full_i : std_logic;
signal p2_mcb_wr_data_o : std_logic_vector(31 downto 0);
signal p2_mcb_wr_mask_o : std_logic_vector(3 downto 0);
signal p2_mcb_wr_fifo_counts : std_logic_vector(6 downto 0);
signal p3_mcb_rd_en_o : std_logic;
signal p3_mcb_rd_empty_i : std_logic;
signal p3_mcb_rd_fifo_counts : std_logic_vector(6 downto 0);
signal p3_mcb_rd_data_i : std_logic_vector(31 downto 0);
--signal cmp_data : std_logic_vector(31 downto 0);
begin
cmp_error <= p2_cmp_error or p3_cmp_error;
error <= p2_error or p3_error;
error_status <= p2_error_status;
cmp_data <= p2_cmp_data(31 downto 0);
cmp_data_valid <= p2_cmp_data_valid;
p2_mcb_cmd_en_o <= p2_mcb_cmd_en_o_int;
p2_mcb_cmd_instr_o <= p2_mcb_cmd_instr_o_int;
p2_mcb_cmd_bl_o <= p2_mcb_cmd_bl_o_int;
p2_mcb_cmd_addr_o <= p2_mcb_cmd_addr_o_int;
p2_mcb_wr_en_o <= p2_mcb_wr_en_o_int;
init_mem_pattern_ctr_p2 :init_mem_pattern_ctr
generic map
(
DWIDTH => p2_DWIDTH,
FAMILY => FAMILY,
BEGIN_ADDRESS => C_p3_BEGIN_ADDRESS,
END_ADDRESS => C_p3_END_ADDRESS,
CMD_SEED_VALUE => X"56456783",
DATA_SEED_VALUE => X"12345678",
DATA_MODE => C_p3_DATA_MODE,
PORT_MODE => p2_PORT_MODE
)
port map
(
clk_i => clk0,
rst_i => rst0,
mcb_cmd_en_i => p3_mcb_cmd_en_o_int,
mcb_cmd_instr_i => p3_mcb_cmd_instr_o_int,
mcb_cmd_bl_i => p3_mcb_cmd_bl_o_int,
mcb_wr_en_i => p3_mcb_wr_en_o_int,
vio_modify_enable => vio_modify_enable,
vio_data_mode_value => vio_data_mode_value,
vio_addr_mode_value => vio_addr_mode_value,
vio_bl_mode_value => "10",--vio_bl_mode_value,
vio_fixed_bl_value => "000000",--vio_fixed_bl_value,
mcb_init_done_i => calib_done,
cmp_error => p2_error,
run_traffic_o => p2_tg_run_traffic,
start_addr_o => p2_tg_start_addr,
end_addr_o => p2_tg_end_addr ,
cmd_seed_o => p2_tg_cmd_seed ,
data_seed_o => p2_tg_data_seed ,
load_seed_o => p2_tg_load_seed ,
addr_mode_o => p2_tg_addr_mode ,
instr_mode_o => p2_tg_instr_mode ,
bl_mode_o => p2_tg_bl_mode ,
data_mode_o => p2_tg_data_mode ,
mode_load_o => p2_tg_mode_load ,
fixed_bl_o => p2_tg_fixed_bl ,
fixed_instr_o => p2_tg_fixed_instr,
fixed_addr_o => p2_tg_fixed_addr
);
m_traffic_gen_p2 : mcb_traffic_gen
generic map(
MEM_BURST_LEN => C_MEM_BURST_LEN,
MEM_COL_WIDTH => C_MEM_NUM_COL_BITS,
NUM_DQ_PINS => C_NUM_DQ_PINS,
DQ_ERROR_WIDTH => DQ_ERROR_WIDTH,
PORT_MODE => p2_PORT_MODE,
DWIDTH => p2_DWIDTH,
CMP_DATA_PIPE_STAGES => CMP_DATA_PIPE_STAGES,
FAMILY => FAMILY,
SIMULATION => "FALSE",
DATA_PATTERN => DATA_PATTERN,
CMD_PATTERN => "CGEN_ALL",
ADDR_WIDTH => 30,
PRBS_SADDR_MASK_POS => C_p3_PRBS_SADDR_MASK_POS,
PRBS_EADDR_MASK_POS => C_p3_PRBS_EADDR_MASK_POS,
PRBS_SADDR => C_p3_BEGIN_ADDRESS,
PRBS_EADDR => C_p3_END_ADDRESS
)
port map
(
clk_i => clk0,
rst_i => rst0,
run_traffic_i => p2_tg_run_traffic,
manual_clear_error => rst0,
-- runtime parameter
start_addr_i => p2_tg_start_addr ,
end_addr_i => p2_tg_end_addr ,
cmd_seed_i => p2_tg_cmd_seed ,
data_seed_i => p2_tg_data_seed ,
load_seed_i => p2_tg_load_seed,
addr_mode_i => p2_tg_addr_mode,
instr_mode_i => p2_tg_instr_mode ,
bl_mode_i => p2_tg_bl_mode ,
data_mode_i => p2_tg_data_mode ,
mode_load_i => p2_tg_mode_load ,
-- fixed pattern inputs interface
fixed_bl_i => p2_tg_fixed_bl,
fixed_instr_i => p2_tg_fixed_instr,
fixed_addr_i => p2_tg_fixed_addr,
fixed_data_i => (others => '0'),
-- BRAM interface.
bram_cmd_i => (others => '0'),
bram_valid_i => '0',
bram_rdy_o => open,
-- MCB INTERFACE
mcb_cmd_en_o => p2_mcb_cmd_en_o_int,
mcb_cmd_instr_o => p2_mcb_cmd_instr_o_int,
mcb_cmd_bl_o => p2_mcb_cmd_bl_o_int,
mcb_cmd_addr_o => p2_mcb_cmd_addr_o_int,
mcb_cmd_full_i => p2_mcb_cmd_full_i,
mcb_wr_en_o => p2_mcb_wr_en_o_int,
mcb_wr_mask_o => p2_mcb_wr_mask_o,
mcb_wr_data_o => p2_mcb_wr_data_o,
mcb_wr_data_end_o => open,
mcb_wr_full_i => p2_mcb_wr_full_i,
mcb_wr_fifo_counts => p2_mcb_wr_fifo_counts,
mcb_rd_en_o => p2_mcb_rd_en_o,
mcb_rd_data_i => p2_mcb_rd_data_i,
mcb_rd_empty_i => p2_mcb_rd_empty_i,
mcb_rd_fifo_counts => p2_mcb_rd_fifo_counts,
-- status feedback
counts_rst => rst0,
wr_data_counts => open,
rd_data_counts => open,
cmp_data => p2_cmp_data,
cmp_data_valid => p2_cmp_data_valid,
cmp_error => p2_cmp_error,
error => p2_error,
error_status => p2_error_status,
mem_rd_data => open,
dq_error_bytelane_cmp => open,
cumlative_dq_lane_error => open
);
p3_mcb_cmd_en_o <= p3_mcb_cmd_en_o_int;
p3_mcb_cmd_instr_o <= p3_mcb_cmd_instr_o_int;
p3_mcb_cmd_bl_o <= p3_mcb_cmd_bl_o_int;
p3_mcb_cmd_addr_o <= p3_mcb_cmd_addr_o_int;
p3_mcb_wr_en_o <= p3_mcb_wr_en_o_int;
init_mem_pattern_ctr_p3 :init_mem_pattern_ctr
generic map
(
DWIDTH => p3_DWIDTH,
FAMILY => FAMILY,
BEGIN_ADDRESS => C_p3_BEGIN_ADDRESS,
END_ADDRESS => C_p3_END_ADDRESS,
CMD_SEED_VALUE => X"56456783",
DATA_SEED_VALUE => X"12345678",
DATA_MODE => C_p3_DATA_MODE,
PORT_MODE => p3_PORT_MODE
)
port map
(
clk_i => clk0,
rst_i => rst0,
mcb_cmd_en_i => p3_mcb_cmd_en_o_int,
mcb_cmd_instr_i => p3_mcb_cmd_instr_o_int,
mcb_cmd_bl_i => p3_mcb_cmd_bl_o_int,
mcb_wr_en_i => p3_mcb_wr_en_o_int,
vio_modify_enable => vio_modify_enable,
vio_data_mode_value => vio_data_mode_value,
vio_addr_mode_value => vio_addr_mode_value,
vio_bl_mode_value => "10",--vio_bl_mode_value,
vio_fixed_bl_value => "000000",--vio_fixed_bl_value,
mcb_init_done_i => calib_done,
cmp_error => p3_error,
run_traffic_o => p3_tg_run_traffic,
start_addr_o => p3_tg_start_addr,
end_addr_o => p3_tg_end_addr ,
cmd_seed_o => p3_tg_cmd_seed ,
data_seed_o => p3_tg_data_seed ,
load_seed_o => p3_tg_load_seed ,
addr_mode_o => p3_tg_addr_mode ,
instr_mode_o => p3_tg_instr_mode ,
bl_mode_o => p3_tg_bl_mode ,
data_mode_o => p3_tg_data_mode ,
mode_load_o => p3_tg_mode_load ,
fixed_bl_o => p3_tg_fixed_bl ,
fixed_instr_o => p3_tg_fixed_instr,
fixed_addr_o => p3_tg_fixed_addr
);
m_traffic_gen_p3 : mcb_traffic_gen
generic map(
MEM_BURST_LEN => C_MEM_BURST_LEN,
MEM_COL_WIDTH => C_MEM_NUM_COL_BITS,
NUM_DQ_PINS => C_NUM_DQ_PINS,
DQ_ERROR_WIDTH => DQ_ERROR_WIDTH,
PORT_MODE => p3_PORT_MODE,
DWIDTH => p3_DWIDTH,
CMP_DATA_PIPE_STAGES => CMP_DATA_PIPE_STAGES,
FAMILY => FAMILY,
SIMULATION => "FALSE",
DATA_PATTERN => DATA_PATTERN,
CMD_PATTERN => "CGEN_ALL",
ADDR_WIDTH => 30,
PRBS_SADDR_MASK_POS => C_p3_PRBS_SADDR_MASK_POS,
PRBS_EADDR_MASK_POS => C_p3_PRBS_EADDR_MASK_POS,
PRBS_SADDR => C_p3_BEGIN_ADDRESS,
PRBS_EADDR => C_p3_END_ADDRESS
)
port map
(
clk_i => clk0,
rst_i => rst0,
run_traffic_i => p3_tg_run_traffic,
manual_clear_error => rst0,
-- runtime parameter
start_addr_i => p3_tg_start_addr ,
end_addr_i => p3_tg_end_addr ,
cmd_seed_i => p3_tg_cmd_seed ,
data_seed_i => p3_tg_data_seed ,
load_seed_i => p3_tg_load_seed,
addr_mode_i => p3_tg_addr_mode,
instr_mode_i => p3_tg_instr_mode ,
bl_mode_i => p3_tg_bl_mode ,
data_mode_i => p3_tg_data_mode ,
mode_load_i => p3_tg_mode_load ,
-- fixed pattern inputs interface
fixed_bl_i => p3_tg_fixed_bl,
fixed_instr_i => p3_tg_fixed_instr,
fixed_addr_i => p3_tg_fixed_addr,
fixed_data_i => (others => '0'),
-- BRAM interface.
bram_cmd_i => (others => '0'),
bram_valid_i => '0',
bram_rdy_o => open,
-- MCB INTERFACE
mcb_cmd_en_o => p3_mcb_cmd_en_o_int,
mcb_cmd_instr_o => p3_mcb_cmd_instr_o_int,
mcb_cmd_bl_o => p3_mcb_cmd_bl_o_int,
mcb_cmd_addr_o => p3_mcb_cmd_addr_o_int,
mcb_cmd_full_i => p3_mcb_cmd_full_i,
mcb_wr_en_o => p3_mcb_wr_en_o_int,
mcb_wr_mask_o => p3_mcb_wr_mask_o,
mcb_wr_data_o => p3_mcb_wr_data_o,
mcb_wr_data_end_o => open,
mcb_wr_full_i => p3_mcb_wr_full_i,
mcb_wr_fifo_counts => p3_mcb_wr_fifo_counts,
mcb_rd_en_o => p3_mcb_rd_en_o,
mcb_rd_data_i => p3_mcb_rd_data_i,
mcb_rd_empty_i => p3_mcb_rd_empty_i,
mcb_rd_fifo_counts => p3_mcb_rd_fifo_counts,
-- status feedback
counts_rst => rst0,
wr_data_counts => open,
rd_data_counts => open,
cmp_data => p3_cmp_data,
cmp_data_valid => p3_cmp_data_valid,
cmp_error => p3_cmp_error,
error => p3_error,
error_status => p3_error_status,
mem_rd_data => open,
dq_error_bytelane_cmp => open,
cumlative_dq_lane_error => open
);
end architecture;
|
bsd-2-clause
|
timvideos/HDMI2USB-jahanzeb-firmware
|
ipcore_dir/edidram/simulation/edidram_tb.vhd
|
3
|
4405
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_2 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: edidram_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY edidram_tb IS
END ENTITY;
ARCHITECTURE edidram_tb_ARCH OF edidram_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL CLKB : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
CLKB_GEN: PROCESS BEGIN
CLKB <= NOT CLKB;
WAIT FOR 100 NS;
CLKB <= NOT CLKB;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
edidram_synth_inst:ENTITY work.edidram_synth
PORT MAP(
CLK_IN => CLK,
CLKB_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
|
bsd-2-clause
|
timvideos/HDMI2USB-jahanzeb-firmware
|
ipcore_dir/ddr2ram/example_design/sim/functional/sim_tb_top.vhd
|
3
|
16489
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.92
-- \ \ Application : MIG
-- / / Filename : sim_tb_top.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:56 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
-- Device : Spartan-6
-- Design Name : DDR/DDR2/DDR3/LPDDR
-- Purpose : This is the simulation testbench which is used to verify the
-- design. The basic clocks and resets to the interface are
-- generated here. This also connects the memory interface to the
-- memory model.
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity sim_tb_top is
end entity sim_tb_top;
architecture arch of sim_tb_top is
-- ========================================================================== --
-- Parameters --
-- ========================================================================== --
constant DEBUG_EN : integer :=0;
constant C3_HW_TESTING : string := "FALSE";
function c3_sim_hw (val1:std_logic_vector( 31 downto 0); val2: std_logic_vector( 31 downto 0) ) return std_logic_vector is
begin
if (C3_HW_TESTING = "FALSE") then
return val1;
else
return val2;
end if;
end function;
constant C3_MEMCLK_PERIOD : integer := 3200;
constant C3_RST_ACT_LOW : integer := 0;
constant C3_INPUT_CLK_TYPE : string := "SINGLE_ENDED";
constant C3_CLK_PERIOD_NS : real := 3200.0 / 1000.0;
constant C3_TCYC_SYS : real := C3_CLK_PERIOD_NS/2.0;
constant C3_TCYC_SYS_DIV2 : time := C3_TCYC_SYS * 1 ns;
constant C3_NUM_DQ_PINS : integer := 16;
constant C3_MEM_ADDR_WIDTH : integer := 13;
constant C3_MEM_BANKADDR_WIDTH : integer := 3;
constant C3_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN";
constant C3_P0_MASK_SIZE : integer := 4;
constant C3_P0_DATA_PORT_SIZE : integer := 32;
constant C3_P1_MASK_SIZE : integer := 4;
constant C3_P1_DATA_PORT_SIZE : integer := 32;
constant C3_CALIB_SOFT_IP : string := "TRUE";
constant C3_SIMULATION : string := "TRUE";
-- ========================================================================== --
-- Component Declarations
-- ========================================================================== --
component example_top is
generic
(
C3_P0_MASK_SIZE : integer;
C3_P0_DATA_PORT_SIZE : integer;
C3_P1_MASK_SIZE : integer;
C3_P1_DATA_PORT_SIZE : integer;
C3_MEMCLK_PERIOD : integer;
C3_RST_ACT_LOW : integer;
C3_INPUT_CLK_TYPE : string;
DEBUG_EN : integer;
C3_CALIB_SOFT_IP : string;
C3_SIMULATION : string;
C3_HW_TESTING : string;
C3_MEM_ADDR_ORDER : string;
C3_NUM_DQ_PINS : integer;
C3_MEM_ADDR_WIDTH : integer;
C3_MEM_BANKADDR_WIDTH : integer
);
port
(
calib_done : out std_logic;
error : out std_logic;
mcb3_dram_dq : inout std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
mcb3_dram_a : out std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
mcb3_dram_ba : out std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_odt : out std_logic;
mcb3_dram_cke : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_rzq : inout std_logic;
mcb3_zio : inout std_logic;
c3_sys_clk : in std_logic;
c3_sys_rst_i : in std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_dram_udm : out std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic
);
end component;
component ddr2_model_c3 is
port (
ck : in std_logic;
ck_n : in std_logic;
cke : in std_logic;
cs_n : in std_logic;
ras_n : in std_logic;
cas_n : in std_logic;
we_n : in std_logic;
dm_rdqs : inout std_logic_vector((C3_NUM_DQ_PINS/16) downto 0);
ba : in std_logic_vector((C3_MEM_BANKADDR_WIDTH - 1) downto 0);
addr : in std_logic_vector((C3_MEM_ADDR_WIDTH - 1) downto 0);
dq : inout std_logic_vector((C3_NUM_DQ_PINS - 1) downto 0);
dqs : inout std_logic_vector((C3_NUM_DQ_PINS/16) downto 0);
dqs_n : inout std_logic_vector((C3_NUM_DQ_PINS/16) downto 0);
rdqs_n : out std_logic_vector((C3_NUM_DQ_PINS/16) downto 0);
odt : in std_logic
);
end component;
-- ========================================================================== --
-- Signal Declarations --
-- ========================================================================== --
-- Clocks
signal c3_sys_clk : std_logic := '0';
signal c3_sys_clk_p : std_logic;
signal c3_sys_clk_n : std_logic;
-- System Reset
signal c3_sys_rst : std_logic := '0';
signal c3_sys_rst_i : std_logic;
-- Design-Top Port Map
signal mcb3_dram_a : std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
signal mcb3_dram_ba : std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
signal mcb3_dram_ck : std_logic;
signal mcb3_dram_ck_n : std_logic;
signal mcb3_dram_dq : std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
signal mcb3_dram_dqs : std_logic;
signal mcb3_dram_dqs_n : std_logic;
signal mcb3_dram_dm : std_logic;
signal mcb3_dram_ras_n : std_logic;
signal mcb3_dram_cas_n : std_logic;
signal mcb3_dram_we_n : std_logic;
signal mcb3_dram_cke : std_logic;
signal mcb3_dram_odt : std_logic;
signal calib_done : std_logic;
signal error : std_logic;
signal mcb3_dram_udqs : std_logic;
signal mcb3_dram_udqs_n : std_logic;
signal mcb3_dram_dqs_vector : std_logic_vector(1 downto 0);
signal mcb3_dram_dqs_n_vector : std_logic_vector(1 downto 0);
signal mcb3_dram_udm :std_logic; -- for X16 parts
signal mcb3_dram_dm_vector : std_logic_vector(1 downto 0);
signal mcb3_command : std_logic_vector(2 downto 0);
signal mcb3_enable1 : std_logic;
signal mcb3_enable2 : std_logic;
signal rzq3 : std_logic;
signal zio3 : std_logic;
function vector (asi:std_logic) return std_logic_vector is
variable v : std_logic_vector(0 downto 0) ;
begin
v(0) := asi;
return(v);
end function vector;
begin
-- ========================================================================== --
-- Clocks Generation --
-- ========================================================================== --
process
begin
c3_sys_clk <= not c3_sys_clk;
wait for (C3_TCYC_SYS_DIV2);
end process;
c3_sys_clk_p <= c3_sys_clk;
c3_sys_clk_n <= not c3_sys_clk;
-- ========================================================================== --
-- Reset Generation --
-- ========================================================================== --
process
begin
c3_sys_rst <= '0';
wait for 200 ns;
c3_sys_rst <= '1';
wait;
end process;
c3_sys_rst_i <= c3_sys_rst when (C3_RST_ACT_LOW = 1) else (not c3_sys_rst);
-- The PULLDOWN component is connected to the ZIO signal primarily to avoid the
-- unknown state in simulation. In real hardware, ZIO should be a no connect(NC) pin.
zio_pulldown3 : PULLDOWN port map(O => zio3);
rzq_pulldown3 : PULLDOWN port map(O => rzq3);
-- ========================================================================== --
-- DESIGN TOP INSTANTIATION --
-- ========================================================================== --
design_top : example_top generic map
(
C3_P0_MASK_SIZE => C3_P0_MASK_SIZE,
C3_P0_DATA_PORT_SIZE => C3_P0_DATA_PORT_SIZE,
C3_P1_MASK_SIZE => C3_P1_MASK_SIZE,
C3_P1_DATA_PORT_SIZE => C3_P1_DATA_PORT_SIZE,
C3_MEMCLK_PERIOD => C3_MEMCLK_PERIOD,
C3_RST_ACT_LOW => C3_RST_ACT_LOW,
C3_INPUT_CLK_TYPE => C3_INPUT_CLK_TYPE,
DEBUG_EN => DEBUG_EN,
C3_MEM_ADDR_ORDER => C3_MEM_ADDR_ORDER,
C3_NUM_DQ_PINS => C3_NUM_DQ_PINS,
C3_MEM_ADDR_WIDTH => C3_MEM_ADDR_WIDTH,
C3_MEM_BANKADDR_WIDTH => C3_MEM_BANKADDR_WIDTH,
C3_HW_TESTING => C3_HW_TESTING,
C3_SIMULATION => C3_SIMULATION,
C3_CALIB_SOFT_IP => C3_CALIB_SOFT_IP
)
port map (
calib_done => calib_done,
error => error,
c3_sys_clk => c3_sys_clk,
c3_sys_rst_i => c3_sys_rst_i,
mcb3_dram_dq => mcb3_dram_dq,
mcb3_dram_a => mcb3_dram_a,
mcb3_dram_ba => mcb3_dram_ba,
mcb3_dram_ras_n => mcb3_dram_ras_n,
mcb3_dram_cas_n => mcb3_dram_cas_n,
mcb3_dram_we_n => mcb3_dram_we_n,
mcb3_dram_odt => mcb3_dram_odt,
mcb3_dram_cke => mcb3_dram_cke,
mcb3_dram_ck => mcb3_dram_ck,
mcb3_dram_ck_n => mcb3_dram_ck_n,
mcb3_dram_dqs_n => mcb3_dram_dqs_n,
mcb3_dram_udqs => mcb3_dram_udqs, -- for X16 parts
mcb3_dram_udqs_n => mcb3_dram_udqs_n, -- for X16 parts
mcb3_dram_udm => mcb3_dram_udm, -- for X16 parts
mcb3_dram_dm => mcb3_dram_dm,
mcb3_rzq => rzq3,
mcb3_zio => zio3,
mcb3_dram_dqs => mcb3_dram_dqs
);
-- ========================================================================== --
-- Memory model instances --
-- ========================================================================== --
mcb3_command <= (mcb3_dram_ras_n & mcb3_dram_cas_n & mcb3_dram_we_n);
process(mcb3_dram_ck)
begin
if (rising_edge(mcb3_dram_ck)) then
if (c3_sys_rst = '0') then
mcb3_enable1 <= '0';
mcb3_enable2 <= '0';
elsif (mcb3_command = "100") then
mcb3_enable2 <= '0';
elsif (mcb3_command = "101") then
mcb3_enable2 <= '1';
else
mcb3_enable2 <= mcb3_enable2;
end if;
mcb3_enable1 <= mcb3_enable2;
end if;
end process;
-----------------------------------------------------------------------------
--read
-----------------------------------------------------------------------------
mcb3_dram_dqs_vector(1 downto 0) <= (mcb3_dram_udqs & mcb3_dram_dqs)
when (mcb3_enable2 = '0' and mcb3_enable1 = '0')
else "ZZ";
mcb3_dram_dqs_n_vector(1 downto 0) <= (mcb3_dram_udqs_n & mcb3_dram_dqs_n)
when (mcb3_enable2 = '0' and mcb3_enable1 = '0')
else "ZZ";
-----------------------------------------------------------------------------
--write
-----------------------------------------------------------------------------
mcb3_dram_dqs <= mcb3_dram_dqs_vector(0)
when ( mcb3_enable1 = '1') else 'Z';
mcb3_dram_udqs <= mcb3_dram_dqs_vector(1)
when (mcb3_enable1 = '1') else 'Z';
mcb3_dram_dqs_n <= mcb3_dram_dqs_n_vector(0)
when (mcb3_enable1 = '1') else 'Z';
mcb3_dram_udqs_n <= mcb3_dram_dqs_n_vector(1)
when (mcb3_enable1 = '1') else 'Z';
mcb3_dram_dm_vector <= (mcb3_dram_udm & mcb3_dram_dm);
u_mem_c3 : ddr2_model_c3 port map(
ck => mcb3_dram_ck,
ck_n => mcb3_dram_ck_n,
cke => mcb3_dram_cke,
cs_n => '0',
ras_n => mcb3_dram_ras_n,
cas_n => mcb3_dram_cas_n,
we_n => mcb3_dram_we_n,
dm_rdqs => mcb3_dram_dm_vector ,
ba => mcb3_dram_ba,
addr => mcb3_dram_a,
dq => mcb3_dram_dq,
dqs => mcb3_dram_dqs_vector,
dqs_n => mcb3_dram_dqs_n_vector,
rdqs_n => open,
odt => mcb3_dram_odt
);
-----------------------------------------------------------------------------
-- Reporting the test case status
-----------------------------------------------------------------------------
Logging: process
begin
wait for 200 us;
if (calib_done = '1') then
if (error = '0') then
report ("****TEST PASSED****");
else
report ("****TEST FAILED: DATA ERROR****");
end if;
else
report ("****TEST FAILED: INITIALIZATION DID NOT COMPLETE****");
end if;
end process;
end architecture;
|
bsd-2-clause
|
shailcoolboy/Warp-Trinity
|
edk_user_repository/WARP/pcores/user_io_board_controller_plbw_v1_01_a/hdl/vhdl/user_io_board_controller_plbw.vhd
|
4
|
14883
|
-------------------------------------------------------------------
-- System Generator version 10.1.00 VHDL source file.
--
-- Copyright(C) 2007 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2007 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity plbaddrpref is
generic (
C_BASEADDR : std_logic_vector(31 downto 0) := X"80000000";
C_HIGHADDR : std_logic_vector(31 downto 0) := X"8000FFFF";
C_SPLB_DWIDTH : integer range 32 to 128 := 32;
C_SPLB_NATIVE_DWIDTH : integer range 32 to 32 := 32
);
port (
addrpref : out std_logic_vector(15-1 downto 0);
sl_rddbus : out std_logic_vector(0 to C_SPLB_DWIDTH-1);
plb_wrdbus : in std_logic_vector(0 to C_SPLB_DWIDTH-1);
sgsl_rddbus : in std_logic_vector(0 to C_SPLB_NATIVE_DWIDTH-1);
sgplb_wrdbus : out std_logic_vector(0 to C_SPLB_NATIVE_DWIDTH-1)
);
end plbaddrpref;
architecture behavior of plbaddrpref is
signal sl_rddbus_i : std_logic_vector(0 to C_SPLB_DWIDTH-1);
begin
addrpref <= C_BASEADDR(32-1 downto 17);
-------------------------------------------------------------------------------
-- Mux/Steer data/be's correctly for connect 32-bit slave to 128-bit plb
-------------------------------------------------------------------------------
GEN_128_TO_32_SLAVE : if C_SPLB_NATIVE_DWIDTH = 32 and C_SPLB_DWIDTH = 128 generate
begin
-----------------------------------------------------------------------
-- Map lower rd data to each quarter of the plb slave read bus
-----------------------------------------------------------------------
sl_rddbus_i(0 to 31) <= sgsl_rddbus(0 to C_SPLB_NATIVE_DWIDTH-1);
sl_rddbus_i(32 to 63) <= sgsl_rddbus(0 to C_SPLB_NATIVE_DWIDTH-1);
sl_rddbus_i(64 to 95) <= sgsl_rddbus(0 to C_SPLB_NATIVE_DWIDTH-1);
sl_rddbus_i(96 to 127) <= sgsl_rddbus(0 to C_SPLB_NATIVE_DWIDTH-1);
end generate GEN_128_TO_32_SLAVE;
-------------------------------------------------------------------------------
-- Mux/Steer data/be's correctly for connect 32-bit slave to 64-bit plb
-------------------------------------------------------------------------------
GEN_64_TO_32_SLAVE : if C_SPLB_NATIVE_DWIDTH = 32 and C_SPLB_DWIDTH = 64 generate
begin
---------------------------------------------------------------------------
-- Map lower rd data to upper and lower halves of plb slave read bus
---------------------------------------------------------------------------
sl_rddbus_i(0 to 31) <= sgsl_rddbus(0 to C_SPLB_NATIVE_DWIDTH-1);
sl_rddbus_i(32 to 63) <= sgsl_rddbus(0 to C_SPLB_NATIVE_DWIDTH-1);
end generate GEN_64_TO_32_SLAVE;
-------------------------------------------------------------------------------
-- IPIF DWidth = PLB DWidth
-- If IPIF Slave Data width is equal to the PLB Bus Data Width
-- Then BE and Read Data Bus map directly to eachother.
-------------------------------------------------------------------------------
GEN_FOR_EQUAL_SLAVE : if C_SPLB_NATIVE_DWIDTH = C_SPLB_DWIDTH generate
sl_rddbus_i <= sgsl_rddbus;
end generate GEN_FOR_EQUAL_SLAVE;
sl_rddbus <= sl_rddbus_i;
sgplb_wrdbus <= plb_wrdbus(0 to C_SPLB_NATIVE_DWIDTH-1);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity user_io_board_controller_plbw is
generic (
C_BASEADDR: std_logic_vector(31 downto 0) := X"80000000";
C_HIGHADDR: std_logic_vector(31 downto 0) := X"80000FFF";
C_SPLB_DWIDTH: integer range 32 to 128 := 32;
C_SPLB_NATIVE_DWIDTH: integer range 32 to 32 := 32;
C_SPLB_AWIDTH: integer := 0;
C_SPLB_P2P: integer := 0;
C_SPLB_MID_WIDTH: integer := 0;
C_SPLB_NUM_MASTERS: integer := 0;
C_SPLB_SUPPORT_BURSTS: integer := 0;
C_MEMMAP_BUTTONS_BIG: integer := 0;
C_MEMMAP_BUTTONS_BIG_N_BITS: integer := 0;
C_MEMMAP_BUTTONS_BIG_BIN_PT: integer := 0;
C_MEMMAP_BUTTONS_SMALL: integer := 0;
C_MEMMAP_BUTTONS_SMALL_N_BITS: integer := 0;
C_MEMMAP_BUTTONS_SMALL_BIN_PT: integer := 0;
C_MEMMAP_DIP_SWITCH: integer := 0;
C_MEMMAP_DIP_SWITCH_N_BITS: integer := 0;
C_MEMMAP_DIP_SWITCH_BIN_PT: integer := 0;
C_MEMMAP_TRACKBALL: integer := 0;
C_MEMMAP_TRACKBALL_N_BITS: integer := 0;
C_MEMMAP_TRACKBALL_BIN_PT: integer := 0;
C_MEMMAP_BUZZER_DUTYCYCLE: integer := 0;
C_MEMMAP_BUZZER_DUTYCYCLE_N_BITS: integer := 0;
C_MEMMAP_BUZZER_DUTYCYCLE_BIN_PT: integer := 0;
C_MEMMAP_BUZZER_ENABLE: integer := 0;
C_MEMMAP_BUZZER_ENABLE_N_BITS: integer := 0;
C_MEMMAP_BUZZER_ENABLE_BIN_PT: integer := 0;
C_MEMMAP_BUZZER_PERIOD: integer := 0;
C_MEMMAP_BUZZER_PERIOD_N_BITS: integer := 0;
C_MEMMAP_BUZZER_PERIOD_BIN_PT: integer := 0;
C_MEMMAP_LCD_BACKGROUNDCOLOR: integer := 0;
C_MEMMAP_LCD_BACKGROUNDCOLOR_N_BITS: integer := 0;
C_MEMMAP_LCD_BACKGROUNDCOLOR_BIN_PT: integer := 0;
C_MEMMAP_LCD_CHARACTEROFFSET: integer := 0;
C_MEMMAP_LCD_CHARACTEROFFSET_N_BITS: integer := 0;
C_MEMMAP_LCD_CHARACTEROFFSET_BIN_PT: integer := 0;
C_MEMMAP_LCD_CHARACTERSSELECT: integer := 0;
C_MEMMAP_LCD_CHARACTERSSELECT_N_BITS: integer := 0;
C_MEMMAP_LCD_CHARACTERSSELECT_BIN_PT: integer := 0;
C_MEMMAP_LCD_COLSET: integer := 0;
C_MEMMAP_LCD_COLSET_N_BITS: integer := 0;
C_MEMMAP_LCD_COLSET_BIN_PT: integer := 0;
C_MEMMAP_LCD_CONFIGLOCATION: integer := 0;
C_MEMMAP_LCD_CONFIGLOCATION_N_BITS: integer := 0;
C_MEMMAP_LCD_CONFIGLOCATION_BIN_PT: integer := 0;
C_MEMMAP_LCD_DIVIDERSELECT: integer := 0;
C_MEMMAP_LCD_DIVIDERSELECT_N_BITS: integer := 0;
C_MEMMAP_LCD_DIVIDERSELECT_BIN_PT: integer := 0;
C_MEMMAP_LCD_FIRSTEND: integer := 0;
C_MEMMAP_LCD_FIRSTEND_N_BITS: integer := 0;
C_MEMMAP_LCD_FIRSTEND_BIN_PT: integer := 0;
C_MEMMAP_LCD_FIRSTSTART: integer := 0;
C_MEMMAP_LCD_FIRSTSTART_N_BITS: integer := 0;
C_MEMMAP_LCD_FIRSTSTART_BIN_PT: integer := 0;
C_MEMMAP_LCD_LINEOFFSET: integer := 0;
C_MEMMAP_LCD_LINEOFFSET_N_BITS: integer := 0;
C_MEMMAP_LCD_LINEOFFSET_BIN_PT: integer := 0;
C_MEMMAP_LCD_RAMWRITE: integer := 0;
C_MEMMAP_LCD_RAMWRITE_N_BITS: integer := 0;
C_MEMMAP_LCD_RAMWRITE_BIN_PT: integer := 0;
C_MEMMAP_LCD_RESET: integer := 0;
C_MEMMAP_LCD_RESET_N_BITS: integer := 0;
C_MEMMAP_LCD_RESET_BIN_PT: integer := 0;
C_MEMMAP_LCD_RESETLCD: integer := 0;
C_MEMMAP_LCD_RESETLCD_N_BITS: integer := 0;
C_MEMMAP_LCD_RESETLCD_BIN_PT: integer := 0;
C_MEMMAP_LCD_ROWSET: integer := 0;
C_MEMMAP_LCD_ROWSET_N_BITS: integer := 0;
C_MEMMAP_LCD_ROWSET_BIN_PT: integer := 0;
C_MEMMAP_LCD_SECONDEND: integer := 0;
C_MEMMAP_LCD_SECONDEND_N_BITS: integer := 0;
C_MEMMAP_LCD_SECONDEND_BIN_PT: integer := 0;
C_MEMMAP_LCD_SECONDSTART: integer := 0;
C_MEMMAP_LCD_SECONDSTART_N_BITS: integer := 0;
C_MEMMAP_LCD_SECONDSTART_BIN_PT: integer := 0;
C_MEMMAP_LCD_SEND: integer := 0;
C_MEMMAP_LCD_SEND_N_BITS: integer := 0;
C_MEMMAP_LCD_SEND_BIN_PT: integer := 0;
C_MEMMAP_LCD_TOTALCMDTRANSFER: integer := 0;
C_MEMMAP_LCD_TOTALCMDTRANSFER_N_BITS: integer := 0;
C_MEMMAP_LCD_TOTALCMDTRANSFER_BIN_PT: integer := 0;
C_MEMMAP_LEDS: integer := 0;
C_MEMMAP_LEDS_N_BITS: integer := 0;
C_MEMMAP_LEDS_BIN_PT: integer := 0;
C_MEMMAP_LCD_CHARACTERMAP: integer := 0;
C_MEMMAP_LCD_CHARACTERMAP_N_BITS: integer := 0;
C_MEMMAP_LCD_CHARACTERMAP_BIN_PT: integer := 0;
C_MEMMAP_LCD_CHARACTERS: integer := 0;
C_MEMMAP_LCD_CHARACTERS_N_BITS: integer := 0;
C_MEMMAP_LCD_CHARACTERS_BIN_PT: integer := 0;
C_MEMMAP_LCD_COMMANDS: integer := 0;
C_MEMMAP_LCD_COMMANDS_N_BITS: integer := 0;
C_MEMMAP_LCD_COMMANDS_BIN_PT: integer := 0
);
port (
buttons_big: in std_logic_vector(0 to 1);
buttons_small: in std_logic_vector(0 to 5);
ce: in std_logic;
dip_switch: in std_logic_vector(0 to 3);
plb_abus: in std_logic_vector(0 to 31);
plb_pavalid: in std_logic;
plb_rnw: in std_logic;
plb_wrdbus: in std_logic_vector(0 to C_SPLB_DWIDTH-1);
reset: in std_logic;
splb_clk: in std_logic;
splb_rst: in std_logic;
trackball_ox: in std_logic;
trackball_oxn: in std_logic;
trackball_oy: in std_logic;
trackball_oyn: in std_logic;
trackball_sel2: in std_logic;
buzzer: out std_logic;
cs: out std_logic;
leds: out std_logic_vector(0 to 7);
resetlcd: out std_logic;
scl: out std_logic;
sdi: out std_logic;
sl_addrack: out std_logic;
sl_rdcomp: out std_logic;
sl_rddack: out std_logic;
sl_rddbus: out std_logic_vector(0 to C_SPLB_DWIDTH-1);
sl_wait: out std_logic;
sl_wrcomp: out std_logic;
sl_wrdack: out std_logic;
trackball_sel1: out std_logic;
trackball_xscn: out std_logic;
trackball_yscn: out std_logic
);
end user_io_board_controller_plbw;
architecture structural of user_io_board_controller_plbw is
signal buttons_big_x0: std_logic_vector(1 downto 0);
signal buttons_small_x0: std_logic_vector(5 downto 0);
signal buzzer_x0: std_logic;
signal ce_x0: std_logic;
signal clk: std_logic;
signal cs_x0: std_logic;
signal dip_switch_x0: std_logic_vector(3 downto 0);
signal leds_x0: std_logic_vector(7 downto 0);
signal plb_abus_x0: std_logic_vector(31 downto 0);
signal plb_pavalid_x0: std_logic;
signal plb_rnw_x0: std_logic;
signal plbaddrpref_addrpref_net: std_logic_vector(14 downto 0);
signal plbaddrpref_plb_wrdbus_net: std_logic_vector(C_SPLB_DWIDTH-1 downto 0);
signal plbaddrpref_sgplb_wrdbus_net: std_logic_vector(31 downto 0);
signal plbaddrpref_sgsl_rddbus_net: std_logic_vector(31 downto 0);
signal plbaddrpref_sl_rddbus_net: std_logic_vector(C_SPLB_DWIDTH-1 downto 0);
signal reset_x0: std_logic;
signal resetlcd_x0: std_logic;
signal scl_x0: std_logic;
signal sdi_x0: std_logic;
signal sl_addrack_x0: std_logic;
signal sl_rdcomp_x0: std_logic;
signal sl_rddack_x0: std_logic;
signal sl_wait_x0: std_logic;
signal sl_wrcomp_x0: std_logic;
signal sl_wrdack_x0: std_logic;
signal splb_rst_x0: std_logic;
signal trackball_ox_x0: std_logic;
signal trackball_oxn_x0: std_logic;
signal trackball_oy_x0: std_logic;
signal trackball_oyn_x0: std_logic;
signal trackball_sel1_x0: std_logic;
signal trackball_sel2_x0: std_logic;
signal trackball_xscn_x0: std_logic;
signal trackball_yscn_x0: std_logic;
begin
buttons_big_x0 <= buttons_big;
buttons_small_x0 <= buttons_small;
ce_x0 <= ce;
dip_switch_x0 <= dip_switch;
plb_abus_x0 <= plb_abus;
plb_pavalid_x0 <= plb_pavalid;
plb_rnw_x0 <= plb_rnw;
plbaddrpref_plb_wrdbus_net <= plb_wrdbus;
reset_x0 <= reset;
clk <= splb_clk;
splb_rst_x0 <= splb_rst;
trackball_ox_x0 <= trackball_ox;
trackball_oxn_x0 <= trackball_oxn;
trackball_oy_x0 <= trackball_oy;
trackball_oyn_x0 <= trackball_oyn;
trackball_sel2_x0 <= trackball_sel2;
buzzer <= buzzer_x0;
cs <= cs_x0;
leds <= leds_x0;
resetlcd <= resetlcd_x0;
scl <= scl_x0;
sdi <= sdi_x0;
sl_addrack <= sl_addrack_x0;
sl_rdcomp <= sl_rdcomp_x0;
sl_rddack <= sl_rddack_x0;
sl_rddbus <= plbaddrpref_sl_rddbus_net;
sl_wait <= sl_wait_x0;
sl_wrcomp <= sl_wrcomp_x0;
sl_wrdack <= sl_wrdack_x0;
trackball_sel1 <= trackball_sel1_x0;
trackball_xscn <= trackball_xscn_x0;
trackball_yscn <= trackball_yscn_x0;
plbaddrpref_x0: entity work.plbaddrpref
generic map (
C_BASEADDR => C_BASEADDR,
C_HIGHADDR => C_HIGHADDR,
C_SPLB_DWIDTH => C_SPLB_DWIDTH,
C_SPLB_NATIVE_DWIDTH => C_SPLB_NATIVE_DWIDTH
)
port map (
plb_wrdbus => plbaddrpref_plb_wrdbus_net,
sgsl_rddbus => plbaddrpref_sgsl_rddbus_net,
addrpref => plbaddrpref_addrpref_net,
sgplb_wrdbus => plbaddrpref_sgplb_wrdbus_net,
sl_rddbus => plbaddrpref_sl_rddbus_net
);
sysgen_dut: entity work.user_io_board_controller_cw
port map (
buttons_big => buttons_big_x0,
buttons_small => buttons_small_x0,
ce => ce_x0,
clk => clk,
dip_switch => dip_switch_x0,
plb_abus => plb_abus_x0,
plb_pavalid => plb_pavalid_x0,
plb_rnw => plb_rnw_x0,
plb_wrdbus => plbaddrpref_sgplb_wrdbus_net,
reset => reset_x0,
sg_plb_addrpref => plbaddrpref_addrpref_net,
splb_rst => splb_rst_x0,
trackball_ox => trackball_ox_x0,
trackball_oxn => trackball_oxn_x0,
trackball_oy => trackball_oy_x0,
trackball_oyn => trackball_oyn_x0,
trackball_sel2 => trackball_sel2_x0,
buzzer => buzzer_x0,
cs => cs_x0,
leds => leds_x0,
resetlcd => resetlcd_x0,
scl => scl_x0,
sdi => sdi_x0,
sl_addrack => sl_addrack_x0,
sl_rdcomp => sl_rdcomp_x0,
sl_rddack => sl_rddack_x0,
sl_rddbus => plbaddrpref_sgsl_rddbus_net,
sl_wait => sl_wait_x0,
sl_wrcomp => sl_wrcomp_x0,
sl_wrdack => sl_wrdack_x0,
trackball_sel1 => trackball_sel1_x0,
trackball_xscn => trackball_xscn_x0,
trackball_yscn => trackball_yscn_x0
);
end structural;
|
bsd-2-clause
|
timvideos/HDMI2USB-jahanzeb-firmware
|
ipcore_dir/ddr2ram/example_design/rtl/traffic_gen/tg_status.vhd
|
20
|
5700
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: tg_status.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:16:42 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This module compare the memory read data agaisnt compare data that generated from data_gen module.
-- Error signal will be asserted if the comparsion is not equal.
-- Reference:
-- Revision History:
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
entity tg_status is
generic (
TCQ : TIME := 100 ps;
DWIDTH : integer := 32
);
port (
clk_i : in std_logic;
rst_i : in std_logic;
manual_clear_error : in std_logic;
data_error_i : in std_logic;
cmp_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
rd_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
cmp_addr_i : in std_logic_vector(31 downto 0);
cmp_bl_i : in std_logic_vector(5 downto 0);
mcb_cmd_full_i : in std_logic;
mcb_wr_full_i : in std_logic;
mcb_rd_empty_i : in std_logic;
error_status : out std_logic_vector(64 + (2 * DWIDTH - 1) downto 0);
error : out std_logic
);
end entity tg_status;
architecture trans of tg_status is
signal data_error_r : std_logic;
signal error_set : std_logic;
begin
error <= error_set;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
data_error_r <= data_error_i;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ((rst_i or manual_clear_error) = '1') then
-- error_status <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
error_status <= (others => '0');
error_set <= '0';
else
-- latch the first error only
if ((data_error_i and not(data_error_r) and not(error_set)) = '1') then
error_status(31 downto 0) <= cmp_addr_i;
error_status(37 downto 32) <= cmp_bl_i;
error_status(40) <= mcb_cmd_full_i;
error_status(41) <= mcb_wr_full_i;
error_status(42) <= mcb_rd_empty_i;
error_set <= '1';
error_status(64 + (DWIDTH - 1) downto 64) <= cmp_data_i;
error_status(64 + (2 * DWIDTH - 1) downto 64 + DWIDTH) <= rd_data_i;
end if;
error_status(39 downto 38) <= "00"; -- reserved
error_status(63 downto 43) <= "000000000000000000000"; -- reserved
end if;
end if;
end process;
end architecture trans;
|
bsd-2-clause
|
timvideos/HDMI2USB-jahanzeb-firmware
|
ipcore_dir/ddr2ram/example_design/rtl/traffic_gen/read_posted_fifo.vhd
|
20
|
11980
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: read_posted_fifo.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:16:40 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This module instantiated by read_data_path module and sits between
-- mcb_flow_control module and read_data_gen module to buffer up the
-- commands that has sent to memory controller.
-- Reference:
-- Revision History:
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
entity read_posted_fifo is
generic (
TCQ : time := 100 ps;
MEM_BURST_LEN : integer := 4;
FAMILY : string := "SPARTAN6";
ADDR_WIDTH : integer := 32;
BL_WIDTH : integer := 6
);
port (
clk_i : in std_logic;
rst_i : in std_logic;
cmd_rdy_o : out std_logic;
cmd_valid_i : in std_logic;
data_valid_i : in std_logic;
addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
bl_i : in std_logic_vector(BL_WIDTH - 1 downto 0);
user_bl_cnt_is_1 : in std_logic;
cmd_sent : in std_logic_vector(2 downto 0);
bl_sent : in std_logic_vector(5 downto 0);
cmd_en_i : in std_logic;
gen_rdy_i : in std_logic;
gen_valid_o : out std_logic;
gen_addr_o : out std_logic_vector(ADDR_WIDTH - 1 downto 0);
gen_bl_o : out std_logic_vector(BL_WIDTH - 1 downto 0);
rd_buff_avail_o : out std_logic_vector(6 downto 0);
rd_mdata_fifo_empty : in std_logic;
rd_mdata_en : out std_logic
);
end entity read_posted_fifo;
architecture trans of read_posted_fifo is
component afifo is
generic (
DSIZE : integer := 32;
FIFO_DEPTH : integer := 16;
ASIZE : integer := 4;
SYNC : integer := 1
);
port (
wr_clk : in std_logic;
rst : in std_logic;
wr_en : in std_logic;
wr_data : in std_logic_vector(DSIZE - 1 downto 0);
rd_en : in std_logic;
rd_clk : in std_logic;
rd_data : out std_logic_vector(DSIZE - 1 downto 0);
full : out std_logic;
empty : out std_logic;
almost_full : out std_logic
);
end component;
signal full : std_logic;
signal empty : std_logic;
signal wr_en : std_logic;
signal rd_en : std_logic;
signal data_valid_r : std_logic;
signal user_bl_cnt_not_1 : std_logic;
signal buf_avail_r : std_logic_vector(6 downto 0);
signal rd_data_received_counts : std_logic_vector(6 downto 0);
signal rd_data_counts_asked : std_logic_vector(6 downto 0);
signal dfifo_has_enough_room : std_logic;
signal wait_cnt : std_logic_vector(1 downto 0);
signal wait_done : std_logic;
signal dfifo_has_enough_room_d1 : std_logic;
signal empty_r : std_logic;
signal rd_first_data : std_logic;
-- current count is 1 and data_is_valie, then next cycle is not 1
-- calculate how many buf still available
-- assign buf_avail = 64 - (rd_data_counts_asked - rd_data_received_counts);
-- signal tmp_buf_avil : std_logic_vector(5 downto 0);
-- X-HDL generated signals
signal xhdl3 : std_logic;
signal xhdl4 : std_logic;
signal xhdl5 : std_logic_vector(37 downto 0);
signal xhdl6 : std_logic_vector(37 downto 0);
-- Declare intermediate signals for referenced outputs
signal cmd_rdy_o_xhdl0 : std_logic;
signal gen_addr_o_xhdl1 : std_logic_vector(ADDR_WIDTH - 1 downto 0);
signal gen_bl_o_xhdl2 : std_logic_vector(BL_WIDTH - 1 downto 0);
begin
-- Drive referenced outputs
cmd_rdy_o <= cmd_rdy_o_xhdl0;
-- gen_addr_o <= gen_addr_o_xhdl1;
-- gen_bl_o <= gen_bl_o_xhdl2;
gen_bl_o <= xhdl6(BL_WIDTH+ADDR_WIDTH-1 downto ADDR_WIDTH);
gen_addr_o <= xhdl6(ADDR_WIDTH-1 downto 0);
rd_mdata_en <= rd_en;
rd_buff_avail_o <= buf_avail_r;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
cmd_rdy_o_xhdl0 <= not(full) and dfifo_has_enough_room and wait_done;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i = '1') then
wait_cnt <= "00";
elsif ((cmd_rdy_o_xhdl0 and cmd_valid_i) = '1') then
wait_cnt <= "10";
elsif (wait_cnt > "00") then
wait_cnt <= wait_cnt - "01";
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i = '1') then
wait_done <= '1';
elsif ((cmd_rdy_o_xhdl0 and cmd_valid_i) = '1') then
wait_done <= '0';
elsif (wait_cnt = "00") then
wait_done <= '1';
else
wait_done <= '0';
end if;
end if;
end process;
xhdl3 <= '1' when (buf_avail_r >= "0111110") else
'0';
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
dfifo_has_enough_room <= xhdl3;
dfifo_has_enough_room_d1 <= dfifo_has_enough_room;
end if;
end process;
wr_en <= cmd_valid_i and not(full) and dfifo_has_enough_room_d1 and wait_done;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
data_valid_r <= data_valid_i;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ((data_valid_i and user_bl_cnt_is_1) = '1') then
user_bl_cnt_not_1 <= '1';
else
user_bl_cnt_not_1 <= '0';
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i = '1') then
rd_data_counts_asked <= (others => '0');
elsif (cmd_en_i = '1' and cmd_sent(0) = '1') then
rd_data_counts_asked <= rd_data_counts_asked + (bl_sent + "0000001" );
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i = '1') then
rd_data_received_counts <= "0000000";
elsif (data_valid_i = '1') then
rd_data_received_counts <= rd_data_received_counts + "0000001";
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
buf_avail_r <= "1000000" - (rd_data_counts_asked - rd_data_received_counts);
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
empty_r <= empty;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i = '1') then
rd_first_data <= '0';
elsif ( empty = '0' AND empty_r = '1') then
rd_first_data <= '1';
end if;
end if;
end process;
process (gen_rdy_i, empty,empty_r, data_valid_i, data_valid_r, user_bl_cnt_not_1,rd_mdata_fifo_empty,rd_first_data)
begin
if (FAMILY = "SPARTAN6") then
rd_en <= gen_rdy_i and not(empty);
else
IF (MEM_BURST_LEN = 4) then
rd_en <= (not(empty) and empty_r and not(rd_first_data)) or (not(rd_mdata_fifo_empty) and not(empty)) or
(user_bl_cnt_not_1 and data_valid_i);
ELSE
rd_en <= (data_valid_i and not(data_valid_r)) or (user_bl_cnt_not_1 and data_valid_i);
END IF;
end if;
end process;
gen_valid_o <= not(empty);
-- set the SYNC to 1 because rd_clk = wr_clk to reduce latency
-- xhdl4 <= to_integer(to_stdlogic(BL_WIDTH) + to_stdlogic(ADDR_WIDTH));
xhdl5 <= (bl_i & addr_i);
-- (gen_bl_o_xhdl2, gen_addr_o_xhdl1) <= xhdl6;
rd_fifo : afifo
GENERIC MAP (
DSIZE => (BL_WIDTH + ADDR_WIDTH),--xhdl4,
FIFO_DEPTH => 16,
ASIZE => 4,
SYNC => 1
)
port map (
wr_clk => clk_i,
rst => rst_i,
wr_en => wr_en,
wr_data => xhdl5,
rd_en => rd_en,
rd_clk => clk_i,
rd_data => xhdl6,
full => full,
empty => empty,
almost_full => open
);
end architecture trans;
|
bsd-2-clause
|
timvideos/HDMI2USB-jahanzeb-firmware
|
hdl/jpeg_encoder/design/JpegEnc.vhd
|
3
|
19969
|
-------------------------------------------------------------------------------
-- File Name : JpegEnc.vhd
--
-- Project : JPEG_ENC
--
-- Module : JpegEnc
--
-- Content : JPEG Encoder Top Level
--
-- Description :
--
-- Spec. :
--
-- Author : Michal Krepa
--
-------------------------------------------------------------------------------
-- History :
-- 20090301: (MK): Initial Creation.
-------------------------------------------------------------------------------
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- /// Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- LIBRARY/PACKAGE ---------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- generic packages/libraries:
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- user packages/libraries:
-------------------------------------------------------------------------------
library work;
use work.JPEG_PKG.all;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ENTITY ------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
entity JpegEnc is
port
(
CLK : in std_logic;
RST : in std_logic;
-- OPB
OPB_ABus : in std_logic_vector(31 downto 0);
OPB_BE : in std_logic_vector(3 downto 0);
OPB_DBus_in : in std_logic_vector(31 downto 0);
OPB_RNW : in std_logic;
OPB_select : in std_logic;
OPB_DBus_out : out std_logic_vector(31 downto 0);
OPB_XferAck : out std_logic;
OPB_retry : out std_logic;
OPB_toutSup : out std_logic;
OPB_errAck : out std_logic;
-- IMAGE RAM
iram_wdata : in std_logic_vector(C_PIXEL_BITS-1 downto 0);
iram_wren : in std_logic;
iram_fifo_afull : out std_logic;
-- OUT RAM
ram_byte : out std_logic_vector(7 downto 0);
ram_wren : out std_logic;
ram_wraddr : out std_logic_vector(23 downto 0);
outif_almost_full : in std_logic;
--debug signal
frame_size : out std_logic_vector(23 downto 0)
);
end entity JpegEnc;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ARCHITECTURE ------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture RTL of JpegEnc is
signal qdata : std_logic_vector(7 downto 0);
signal qaddr : std_logic_vector(6 downto 0);
signal qwren : std_logic;
signal jpeg_ready : std_logic;
signal jpeg_busy : std_logic;
signal outram_base_addr : std_logic_vector(9 downto 0);
signal num_enc_bytes : std_logic_vector(23 downto 0);
signal img_size_x : std_logic_vector(15 downto 0);
signal img_size_y : std_logic_vector(15 downto 0);
signal sof : std_logic;
signal jpg_iram_rden : std_logic;
signal jpg_iram_rdaddr : std_logic_vector(31 downto 0);
signal jpg_iram_rdata : std_logic_vector(23 downto 0);
signal fdct_start : std_logic;
signal fdct_ready : std_logic;
signal zig_start : std_logic;
signal zig_ready : std_logic;
signal qua_start : std_logic;
signal qua_ready : std_logic;
signal rle_start : std_logic;
signal rle_ready : std_logic;
signal huf_start : std_logic;
signal huf_ready : std_logic;
signal bs_start : std_logic;
signal bs_ready : std_logic;
signal zz_buf_sel : std_logic;
signal zz_rd_addr : std_logic_vector(5 downto 0);
signal zz_data : std_logic_vector(11 downto 0);
signal rle_buf_sel : std_logic;
signal rle_rdaddr : std_logic_vector(5 downto 0);
signal rle_data : std_logic_vector(11 downto 0);
signal qua_buf_sel : std_logic;
signal qua_rdaddr : std_logic_vector(5 downto 0);
signal qua_data : std_logic_vector(11 downto 0);
signal huf_buf_sel : std_logic;
signal huf_rdaddr : std_logic_vector(5 downto 0);
signal huf_rden : std_logic;
signal huf_runlength : std_logic_vector(3 downto 0);
signal huf_size : std_logic_vector(3 downto 0);
signal huf_amplitude : std_logic_vector(11 downto 0);
signal huf_dval : std_logic;
signal bs_buf_sel : std_logic;
signal bs_fifo_empty : std_logic;
signal bs_rd_req : std_logic;
signal bs_packed_byte : std_logic_vector(7 downto 0);
signal huf_fifo_empty : std_logic;
signal zz_rden : std_logic;
signal fdct_sm_settings : T_SM_SETTINGS;
signal zig_sm_settings : T_SM_SETTINGS;
signal qua_sm_settings : T_SM_SETTINGS;
signal rle_sm_settings : T_SM_SETTINGS;
signal huf_sm_settings : T_SM_SETTINGS;
signal bs_sm_settings : T_SM_SETTINGS;
signal image_size_reg : std_logic_vector(31 downto 0);
signal jfif_ram_byte : std_logic_vector(7 downto 0);
signal jfif_ram_wren : std_logic;
signal jfif_ram_wraddr : std_logic_vector(23 downto 0);
signal out_mux_ctrl : std_logic;
signal img_size_wr : std_logic;
signal jfif_start : std_logic;
signal jfif_ready : std_logic;
signal bs_ram_byte : std_logic_vector(7 downto 0);
signal bs_ram_wren : std_logic;
signal bs_ram_wraddr : std_logic_vector(23 downto 0);
signal jfif_eoi : std_logic;
signal fdct_fifo_rd : std_logic;
signal fdct_fifo_q : std_logic_vector(23 downto 0);
signal fdct_fifo_hf_full : std_logic;
-------------------------------------------------------------------------------
-- Architecture: begin
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------
-- Host Interface
-------------------------------------------------------------------
U_HostIF : entity work.HostIF
port map
(
CLK => CLK,
RST => RST,
-- OPB
OPB_ABus => OPB_ABus,
OPB_BE => OPB_BE,
OPB_DBus_in => OPB_DBus_in,
OPB_RNW => OPB_RNW,
OPB_select => OPB_select,
OPB_DBus_out => OPB_DBus_out,
OPB_XferAck => OPB_XferAck,
OPB_retry => OPB_retry,
OPB_toutSup => OPB_toutSup,
OPB_errAck => OPB_errAck,
-- Quantizer RAM
qdata => qdata,
qaddr => qaddr,
qwren => qwren,
-- CTRL
jpeg_ready => jpeg_ready,
jpeg_busy => jpeg_busy,
-- ByteStuffer
outram_base_addr => outram_base_addr,
num_enc_bytes => num_enc_bytes,
-- global
img_size_x => img_size_x,
img_size_y => img_size_y,
img_size_wr => img_size_wr,
sof => sof
);
-------------------------------------------------------------------
-- BUF_FIFO
-------------------------------------------------------------------
U_BUF_FIFO : entity work.BUF_FIFO
port map
(
CLK => CLK,
RST => RST,
-- HOST PROG
img_size_x => img_size_x,
img_size_y => img_size_y,
sof => sof,
-- HOST DATA
iram_wren => iram_wren,
iram_wdata => iram_wdata,
fifo_almost_full => iram_fifo_afull,
-- FDCT
fdct_fifo_rd => fdct_fifo_rd,
fdct_fifo_q => fdct_fifo_q,
fdct_fifo_hf_full => fdct_fifo_hf_full
);
-------------------------------------------------------------------
-- Controller
-------------------------------------------------------------------
U_CtrlSM : entity work.CtrlSM
port map
(
CLK => CLK,
RST => RST,
-- output IF
outif_almost_full => outif_almost_full,
-- HOST IF
sof => sof,
img_size_x => img_size_x,
img_size_y => img_size_y,
jpeg_ready => jpeg_ready,
jpeg_busy => jpeg_busy,
-- FDCT
fdct_start => fdct_start,
fdct_ready => fdct_ready,
fdct_sm_settings => fdct_sm_settings,
-- ZIGZAG
zig_start => zig_start,
zig_ready => zig_ready,
zig_sm_settings => zig_sm_settings,
-- Quantizer
qua_start => qua_start,
qua_ready => qua_ready,
qua_sm_settings => qua_sm_settings,
-- RLE
rle_start => rle_start,
rle_ready => rle_ready,
rle_sm_settings => rle_sm_settings,
-- Huffman
huf_start => huf_start,
huf_ready => huf_ready,
huf_sm_settings => huf_sm_settings,
-- ByteStuffdr
bs_start => bs_start,
bs_ready => bs_ready,
bs_sm_settings => bs_sm_settings,
-- JFIF GEN
jfif_start => jfif_start,
jfif_ready => jfif_ready,
jfif_eoi => jfif_eoi,
-- OUT MUX
out_mux_ctrl => out_mux_ctrl
);
-------------------------------------------------------------------
-- FDCT
-------------------------------------------------------------------
U_FDCT : entity work.FDCT
port map
(
CLK => CLK,
RST => RST,
-- CTRL
start_pb => fdct_start,
ready_pb => fdct_ready,
fdct_sm_settings => fdct_sm_settings,
-- BUF_FIFO
bf_fifo_rd => fdct_fifo_rd,
bf_fifo_q => fdct_fifo_q,
bf_fifo_hf_full => fdct_fifo_hf_full,
-- ZIG ZAG
zz_buf_sel => zz_buf_sel,
zz_rd_addr => zz_rd_addr,
zz_data => zz_data,
zz_rden => zz_rden,
-- HOST
img_size_x => img_size_x,
img_size_y => img_size_y,
sof => sof
);
-------------------------------------------------------------------
-- ZigZag top level
-------------------------------------------------------------------
U_ZZ_TOP : entity work.ZZ_TOP
port map
(
CLK => CLK,
RST => RST,
-- CTRL
start_pb => zig_start,
ready_pb => zig_ready,
zig_sm_settings => zig_sm_settings,
-- Quantizer
qua_buf_sel => qua_buf_sel,
qua_rdaddr => qua_rdaddr,
qua_data => qua_data,
-- FDCT
fdct_buf_sel => zz_buf_sel,
fdct_rd_addr => zz_rd_addr,
fdct_data => zz_data,
fdct_rden => zz_rden
);
-------------------------------------------------------------------
-- Quantizer top level
-------------------------------------------------------------------
U_QUANT_TOP : entity work.QUANT_TOP
port map
(
CLK => CLK,
RST => RST,
-- CTRL
start_pb => qua_start,
ready_pb => qua_ready,
qua_sm_settings => qua_sm_settings,
-- RLE
rle_buf_sel => rle_buf_sel,
rle_rdaddr => rle_rdaddr,
rle_data => rle_data,
-- ZIGZAG
zig_buf_sel => qua_buf_sel,
zig_rd_addr => qua_rdaddr,
zig_data => qua_data,
-- HOST
qdata => qdata,
qaddr => qaddr,
qwren => qwren
);
-------------------------------------------------------------------
-- RLE TOP
-------------------------------------------------------------------
U_RLE_TOP : entity work.RLE_TOP
port map
(
CLK => CLK,
RST => RST,
-- CTRL
start_pb => rle_start,
ready_pb => rle_ready,
rle_sm_settings => rle_sm_settings,
-- HUFFMAN
huf_buf_sel => huf_buf_sel,
huf_rden => huf_rden,
huf_runlength => huf_runlength,
huf_size => huf_size,
huf_amplitude => huf_amplitude,
huf_dval => huf_dval,
huf_fifo_empty => huf_fifo_empty,
-- Quantizer
qua_buf_sel => rle_buf_sel,
qua_rd_addr => rle_rdaddr,
qua_data => rle_data,
-- HostIF
sof => sof
);
-------------------------------------------------------------------
-- Huffman Encoder
-------------------------------------------------------------------
U_Huffman : entity work.Huffman
port map
(
CLK => CLK,
RST => RST,
-- CTRL
start_pb => huf_start,
ready_pb => huf_ready,
huf_sm_settings => huf_sm_settings,
-- HOST IF
sof => sof,
img_size_x => img_size_x,
img_size_y => img_size_y,
-- RLE
rle_buf_sel => huf_buf_sel,
rd_en => huf_rden,
runlength => huf_runlength,
VLI_size => huf_size,
VLI => huf_amplitude,
d_val => huf_dval,
rle_fifo_empty => huf_fifo_empty,
-- Byte Stuffer
bs_buf_sel => bs_buf_sel,
bs_fifo_empty => bs_fifo_empty,
bs_rd_req => bs_rd_req,
bs_packed_byte => bs_packed_byte
);
-------------------------------------------------------------------
-- Byte Stuffer
-------------------------------------------------------------------
U_ByteStuffer : entity work.ByteStuffer
port map
(
CLK => CLK,
RST => RST,
-- CTRL
start_pb => bs_start,
ready_pb => bs_ready,
-- HOST IF
sof => sof,
num_enc_bytes => num_enc_bytes,
outram_base_addr => outram_base_addr,
-- Huffman
huf_buf_sel => bs_buf_sel,
huf_fifo_empty => bs_fifo_empty,
huf_rd_req => bs_rd_req,
huf_packed_byte => bs_packed_byte,
-- OUT RAM
ram_byte => bs_ram_byte,
ram_wren => bs_ram_wren,
ram_wraddr => bs_ram_wraddr
);
--debug signal
frame_size <= num_enc_bytes;
-------------------------------------------------------------------
-- JFIF Generator
-------------------------------------------------------------------
U_JFIFGen : entity work.JFIFGen
port map
(
CLK => CLK,
RST => RST,
-- CTRL
start => jfif_start,
ready => jfif_ready,
eoi => jfif_eoi,
-- ByteStuffer
num_enc_bytes => num_enc_bytes,
-- HOST IF
qwren => qwren,
qwaddr => qaddr,
qwdata => qdata,
image_size_reg => image_size_reg,
image_size_reg_wr => img_size_wr,
-- OUT RAM
ram_byte => jfif_ram_byte,
ram_wren => jfif_ram_wren,
ram_wraddr => jfif_ram_wraddr
);
image_size_reg <= img_size_x & img_size_y;
-------------------------------------------------------------------
-- OutMux
-------------------------------------------------------------------
U_OutMux : entity work.OutMux
port map
(
CLK => CLK,
RST => RST,
-- CTRL
out_mux_ctrl => out_mux_ctrl,
-- ByteStuffer
bs_ram_byte => bs_ram_byte,
bs_ram_wren => bs_ram_wren,
bs_ram_wraddr => bs_ram_wraddr,
-- ByteStuffer
jfif_ram_byte => jfif_ram_byte,
jfif_ram_wren => jfif_ram_wren,
jfif_ram_wraddr => jfif_ram_wraddr,
-- OUT RAM
ram_byte => ram_byte,
ram_wren => ram_wren,
ram_wraddr => ram_wraddr
);
end architecture RTL;
-------------------------------------------------------------------------------
-- Architecture: end
-------------------------------------------------------------------------------
|
bsd-2-clause
|
timvideos/HDMI2USB-jahanzeb-firmware
|
ipcore_dir/cmdfifo/simulation/cmdfifo_dgen.vhd
|
3
|
5110
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: cmdfifo_dgen.vhd
--
-- Description:
-- Used for write interface stimulus generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.cmdfifo_pkg.ALL;
ENTITY cmdfifo_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_dg_arch OF cmdfifo_dgen IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL pr_w_en : STD_LOGIC := '0';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
SIGNAL wr_d_sel : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
WR_EN <= PRC_WR_EN ;
WR_DATA <= wr_data_i AFTER 100 ns;
----------------------------------------------
-- Generation of DATA
----------------------------------------------
gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst1:cmdfifo_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_w_en
);
END GENERATE;
pr_w_en <= (AND_REDUCE(wr_d_sel)) AND PRC_WR_EN AND NOT FULL;
wr_data_i <= rand_num(C_DOUT_WIDTH-C_DIN_WIDTH*conv_integer(wr_d_sel)-1 DOWNTO C_DOUT_WIDTH-C_DIN_WIDTH*(conv_integer(wr_d_sel)+1));
PROCESS(WR_CLK,RESET)
BEGIN
IF(RESET = '1') THEN
wr_d_sel <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK = '1') THEN
IF(FULL = '0' AND PRC_WR_EN = '1') THEN
wr_d_sel <= wr_d_sel + "1";
END IF;
END IF;
END PROCESS;
END ARCHITECTURE;
|
bsd-2-clause
|
timvideos/HDMI2USB-jahanzeb-firmware
|
ipcore_dir/ddr2ram/user_design/sim/wr_data_gen.vhd
|
20
|
18946
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: wr_data_gen.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/05/27 15:50:28 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose:
-- Reference:
-- Revision History:
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity wr_data_gen is
generic (
TCQ : TIME := 100 ps;
FAMILY : string := "SPARTAN6"; -- "SPARTAN6", "VIRTEX6"
MEM_BURST_LEN : integer := 8;
MODE : string := "WR"; --"WR", "RD"
ADDR_WIDTH : integer := 32;
BL_WIDTH : integer := 6;
DWIDTH : integer := 32;
DATA_PATTERN : string := "DGEN_PRBS"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : integer := 8;
SEL_VICTIM_LINE : integer := 3; -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
COLUMN_WIDTH : integer := 10;
EYE_TEST : string := "FALSE"
);
port (
clk_i : in std_logic; --
rst_i : in std_logic_vector(4 downto 0);
prbs_fseed_i : in std_logic_vector(31 downto 0);
data_mode_i : in std_logic_vector(3 downto 0); -- "00" = bram;
cmd_rdy_o : out std_logic; -- ready to receive command. It should assert when data_port is ready at the // beginning and will be deasserted once see the cmd_valid_i is asserted.
-- And then it should reasserted when
-- it is generating the last_word.
cmd_valid_i : in std_logic; -- when both cmd_valid_i and cmd_rdy_o is high, the command is valid.
cmd_validB_i : in std_logic;
cmd_validC_i : in std_logic;
last_word_o : out std_logic;
-- input [5:0] port_data_counts_i,// connect to data port fifo counts
-- m_addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
fixed_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0); -- generated address used to determine data pattern.
bl_i : in std_logic_vector(BL_WIDTH - 1 downto 0); -- generated burst length for control the burst data
data_rdy_i : in std_logic; -- connect from mcb_wr_full when used as wr_data_gen
-- connect from mcb_rd_empty when used as rd_data_gen
-- When both data_rdy and data_valid is asserted, the ouput data is valid.
data_valid_o : out std_logic; -- connect to wr_en or rd_en and is asserted whenever the
-- pattern is available.
data_o : out std_logic_vector(DWIDTH - 1 downto 0); -- generated data pattern
data_wr_end_o : out std_logic
);
end entity wr_data_gen;
architecture trans of wr_data_gen is
COMPONENT sp6_data_gen IS
GENERIC (
ADDR_WIDTH : INTEGER := 32;
BL_WIDTH : INTEGER := 6;
DWIDTH : INTEGER := 32;
DATA_PATTERN : STRING := "DGEN_PRBS";
NUM_DQ_PINS : INTEGER := 8;
COLUMN_WIDTH : INTEGER := 10
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : IN STD_LOGIC;
prbs_fseed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
data_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
data_rdy_i : IN STD_LOGIC;
cmd_startA : IN STD_LOGIC;
cmd_startB : IN STD_LOGIC;
cmd_startC : IN STD_LOGIC;
cmd_startD : IN STD_LOGIC;
cmd_startE : IN STD_LOGIC;
fixed_data_i : IN std_logic_vector(DWIDTH - 1 downto 0);
addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
user_burst_cnt : IN STD_LOGIC_VECTOR(BL_WIDTH DOWNTO 0);
fifo_rdy_i : IN STD_LOGIC;
data_o : OUT STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0)
);
END COMPONENT;
COMPONENT v6_data_gen IS
GENERIC (
ADDR_WIDTH : INTEGER := 32;
BL_WIDTH : INTEGER := 6;
MEM_BURST_LEN : integer := 8;
DWIDTH : INTEGER := 32;
DATA_PATTERN : STRING := "DGEN_PRBS";
NUM_DQ_PINS : INTEGER := 8;
SEL_VICTIM_LINE : INTEGER := 3;
COLUMN_WIDTH : INTEGER := 10;
EYE_TEST : STRING := "FALSE"
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : IN STD_LOGIC;
prbs_fseed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
data_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
data_rdy_i : IN STD_LOGIC;
cmd_startA : IN STD_LOGIC;
cmd_startB : IN STD_LOGIC;
cmd_startC : IN STD_LOGIC;
cmd_startD : IN STD_LOGIC;
fixed_data_i : IN std_logic_vector(DWIDTH - 1 downto 0);
cmd_startE : IN STD_LOGIC;
m_addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
user_burst_cnt : IN STD_LOGIC_VECTOR(BL_WIDTH DOWNTO 0);
fifo_rdy_i : IN STD_LOGIC;
data_o : OUT STD_LOGIC_VECTOR(NUM_DQ_PINS*4 - 1 DOWNTO 0)
);
END COMPONENT;
signal data : std_logic_vector(DWIDTH - 1 downto 0);
signal cmd_rdy : std_logic;
signal cmd_rdyB : std_logic;
signal cmd_rdyC : std_logic;
signal cmd_rdyD : std_logic;
signal cmd_rdyE : std_logic;
signal cmd_rdyF : std_logic;
signal cmd_start : std_logic;
signal cmd_startB : std_logic;
signal cmd_startC : std_logic;
signal cmd_startD : std_logic;
signal cmd_startE : std_logic;
signal cmd_startF : std_logic;
signal burst_count_reached2 : std_logic;
signal data_valid : std_logic;
signal user_burst_cnt : std_logic_vector(6 downto 0);
signal walk_cnt : std_logic_vector(2 downto 0);
signal fifo_not_full : std_logic;
signal i : integer;
signal j : integer;
signal w3data : std_logic_vector(31 downto 0);
-- counter to count user burst length
-- bl_i;
signal u_bcount_2 : std_logic;
signal last_word_t : std_logic;
-- Declare intermediate signals for referenced outputs
signal last_word_o_xhdl1 : std_logic;
signal data_o_xhdl0 : std_logic_vector(DWIDTH - 1 downto 0);
signal tpt_hdata_xhdl2 : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
begin
-- Drive referenced outputs
last_word_o <= last_word_o_xhdl1;
data_o <= data_o_xhdl0;
fifo_not_full <= data_rdy_i;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (((user_burst_cnt = "0000010") or (((cmd_start = '1') and (bl_i = "000001")) and FAMILY = "VIRTEX6")) and (fifo_not_full = '1')) then
data_wr_end_o <= '1';
else
data_wr_end_o <= '0';
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
cmd_start <= cmd_validC_i and cmd_rdyC;
cmd_startB <= cmd_valid_i and cmd_rdyB;
cmd_startC <= cmd_validB_i and cmd_rdyC;
cmd_startD <= cmd_validB_i and cmd_rdyD;
cmd_startE <= cmd_validB_i and cmd_rdyE;
cmd_startF <= cmd_validB_i and cmd_rdyF;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ((rst_i(0)) = '1') then
user_burst_cnt <= "0000000" ;
elsif (cmd_start = '1') then
if (FAMILY = "SPARTAN6") then
if (bl_i = "000000") then
user_burst_cnt <= "1000000" ;
else
user_burst_cnt <= ('0' & bl_i) ;
end if;
else
user_burst_cnt <= ('0' & bl_i) ;
end if;
elsif (fifo_not_full = '1') then
if (user_burst_cnt /= "0000000") then
user_burst_cnt <= user_burst_cnt - "0000001" ;
else
user_burst_cnt <= "0000000" ;
end if;
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ((user_burst_cnt = "0000010" and fifo_not_full = '1') or (cmd_startC = '1' and bl_i = "000001")) then
u_bcount_2 <= '1' ;
elsif (last_word_o_xhdl1 = '1') then
u_bcount_2 <= '0' ;
end if;
end if;
end process;
last_word_o_xhdl1 <= u_bcount_2 and fifo_not_full;
-- cmd_rdy_o assert when the dat fifo is not full and deassert once cmd_valid_i
-- is assert and reassert during the last data
cmd_rdy_o <= cmd_rdy and fifo_not_full;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ((rst_i(0)) = '1') then
cmd_rdy <= '1' ;
elsif (cmd_start = '1') then
if (bl_i = "000001") then
cmd_rdy <= '1' ;
else
cmd_rdy <= '0' ;
end if;
elsif (user_burst_cnt = "0000010" and fifo_not_full = '1') then
cmd_rdy <= '1' ;
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ((rst_i(0)) = '1') then
cmd_rdyB <= '1' ;
elsif (cmd_startB = '1') then
if (bl_i = "000001") then
cmd_rdyB <= '1' ;
else
cmd_rdyB <= '0' ;
end if;
elsif (user_burst_cnt = "0000010" and fifo_not_full = '1') then
cmd_rdyB <= '1' ;
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ((rst_i(0)) = '1') then
cmd_rdyC <= '1' ;
elsif (cmd_startC = '1') then
if (bl_i = "000001") then
cmd_rdyC <= '1' ;
else
cmd_rdyC <= '0' ;
end if;
elsif (user_burst_cnt = "0000010" and fifo_not_full = '1') then
cmd_rdyC <= '1' ;
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ((rst_i(0)) = '1') then
cmd_rdyD <= '1' ;
elsif (cmd_startD = '1') then
if (bl_i = "000001") then
cmd_rdyD <= '1' ;
else
cmd_rdyD <= '0' ;
end if;
elsif (user_burst_cnt = "0000010" and fifo_not_full = '1') then
cmd_rdyD <= '1' ;
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ((rst_i(0)) = '1') then
cmd_rdyE <= '1' ;
elsif (cmd_startE = '1') then
if (bl_i = "000001") then
cmd_rdyE <= '1' ;
else
cmd_rdyE <= '0' ;
end if;
elsif (user_burst_cnt = "0000010" and fifo_not_full = '1') then
cmd_rdyE <= '1' ;
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ((rst_i(0)) = '1') then
cmd_rdyF <= '1' ;
elsif (cmd_startF = '1') then
if (bl_i = "000001") then
cmd_rdyF <= '1' ;
else
cmd_rdyF <= '0' ;
end if;
elsif (user_burst_cnt = "0000010" and fifo_not_full = '1') then
cmd_rdyF <= '1' ;
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ((rst_i(1)) = '1') then
data_valid <= '0' ;
elsif (cmd_start = '1') then
data_valid <= '1' ;
elsif (fifo_not_full = '1' and user_burst_cnt <= "0000001") then
data_valid <= '0' ;
end if;
end if;
end process;
data_valid_o <= data_valid and fifo_not_full;
s6_wdgen : if (FAMILY = "SPARTAN6") generate
sp6_data_gen_inst : sp6_data_gen
generic map (
ADDR_WIDTH => 32,
BL_WIDTH => BL_WIDTH,
DWIDTH => DWIDTH,
DATA_PATTERN => DATA_PATTERN,
NUM_DQ_PINS => NUM_DQ_PINS,
COLUMN_WIDTH => COLUMN_WIDTH
)
port map (
clk_i => clk_i,
rst_i => rst_i(1),
data_rdy_i => data_rdy_i,
prbs_fseed_i => prbs_fseed_i,
data_mode_i => data_mode_i,
cmd_startA => cmd_start,
cmd_startB => cmd_startB,
cmd_startC => cmd_startC,
cmd_startD => cmd_startD,
cmd_startE => cmd_startE,
fixed_data_i => fixed_data_i,
addr_i => addr_i,
user_burst_cnt => user_burst_cnt,
fifo_rdy_i => fifo_not_full,
data_o => data_o_xhdl0
);
end generate;
v6_wdgen : if (FAMILY = "VIRTEX6") generate
v6_data_gen_inst : v6_data_gen
generic map (
ADDR_WIDTH => 32,
BL_WIDTH => BL_WIDTH,
DWIDTH => DWIDTH,
MEM_BURST_LEN => MEM_BURST_LEN,
DATA_PATTERN => DATA_PATTERN,
NUM_DQ_PINS => NUM_DQ_PINS,
SEL_VICTIM_LINE => SEL_VICTIM_LINE,
COLUMN_WIDTH => COLUMN_WIDTH,
EYE_TEST => EYE_TEST
)
port map (
clk_i => clk_i,
rst_i => rst_i(1),
data_rdy_i => data_rdy_i,
prbs_fseed_i => prbs_fseed_i,
data_mode_i => data_mode_i,
cmd_starta => cmd_start,
cmd_startb => cmd_startB,
cmd_startc => cmd_startC,
cmd_startd => cmd_startD,
cmd_starte => cmd_startE,
fixed_data_i => fixed_data_i,
m_addr_i => addr_i, --m_addr_i,
addr_i => addr_i,
user_burst_cnt => user_burst_cnt,
fifo_rdy_i => fifo_not_full,
data_o => data_o_xhdl0
);
end generate;
end architecture trans;
|
bsd-2-clause
|
timvideos/HDMI2USB-jahanzeb-firmware
|
ipcore_dir/ddr2ram/example_design/rtl/traffic_gen/cmd_prbs_gen.vhd
|
20
|
8359
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: cmd_prbs_gen.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:16:37 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This moduel use LFSR to generate random address, isntructions
-- or burst_length.
-- Reference:
-- Revision History:
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
ENTITY cmd_prbs_gen IS
GENERIC (
TCQ : time := 100 ps;
FAMILY : STRING := "SPARTAN6";
ADDR_WIDTH : INTEGER := 29;
DWIDTH : INTEGER := 32;
PRBS_CMD : STRING := "ADDRESS";
PRBS_WIDTH : INTEGER := 64;
SEED_WIDTH : INTEGER := 32;
PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"FFFFD000";
PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00002000";
PRBS_EADDR : std_logic_vector(31 downto 0) := X"00002000";
PRBS_SADDR : std_logic_vector(31 downto 0) := X"00002000"
);
PORT (
clk_i : IN STD_LOGIC;
prbs_seed_init : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
prbs_seed_i : IN STD_LOGIC_VECTOR(SEED_WIDTH - 1 DOWNTO 0);
prbs_o : OUT STD_LOGIC_VECTOR(SEED_WIDTH - 1 DOWNTO 0)
);
END cmd_prbs_gen;
ARCHITECTURE trans OF cmd_prbs_gen IS
SIGNAL ZEROS : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
SIGNAL prbs : STD_LOGIC_VECTOR(SEED_WIDTH - 1 DOWNTO 0);
SIGNAL lfsr_q : STD_LOGIC_VECTOR(PRBS_WIDTH DOWNTO 1);
function logb2 (val : integer) return integer is
variable vec_con : integer;
variable rtn : integer := 1;
begin
vec_con := val;
for index in 0 to 31 loop
if(vec_con = 1) then
rtn := rtn + 1;
return(rtn);
end if;
vec_con := vec_con/2;
rtn := rtn + 1;
end loop;
end function logb2;
BEGIN
ZEROS <= std_logic_vector(to_unsigned(0,ADDR_WIDTH));
xhdl0 : IF (PRBS_CMD = "ADDRESS" AND PRBS_WIDTH = 64) GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (prbs_seed_init = '1') THEN
lfsr_q <= ('0' & ("0000000000000000000000000000000" & prbs_seed_i)) ;
ELSIF (clk_en = '1') THEN
lfsr_q(64) <= lfsr_q(64) XOR lfsr_q(63) ;
lfsr_q(63) <= lfsr_q(62) ;
lfsr_q(62) <= lfsr_q(64) XOR lfsr_q(61) ;
lfsr_q(61) <= lfsr_q(64) XOR lfsr_q(60) ;
lfsr_q(60 DOWNTO 2) <= lfsr_q(59 DOWNTO 1) ;
lfsr_q(1) <= lfsr_q(64) ;
END IF;
END IF;
END PROCESS;
PROCESS (lfsr_q(32 DOWNTO 1))
BEGIN
prbs <= lfsr_q(32 DOWNTO 1);
END PROCESS;
END GENERATE;
xhdl1 : IF (PRBS_CMD = "ADDRESS" AND PRBS_WIDTH = 32) GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (prbs_seed_init = '1') THEN
lfsr_q <= prbs_seed_i ;
ELSIF (clk_en = '1') THEN
lfsr_q(32 DOWNTO 9) <= lfsr_q(31 DOWNTO 8) ;
lfsr_q(8) <= lfsr_q(32) XOR lfsr_q(7) ;
lfsr_q(7) <= lfsr_q(32) XOR lfsr_q(6) ;
lfsr_q(6 DOWNTO 4) <= lfsr_q(5 DOWNTO 3) ;
lfsr_q(3) <= lfsr_q(32) XOR lfsr_q(2) ;
lfsr_q(2) <= lfsr_q(1) ;
lfsr_q(1) <= lfsr_q(32) ;
END IF;
END IF;
END PROCESS;
PROCESS (lfsr_q(32 DOWNTO 1))
BEGIN
IF (FAMILY = "SPARTAN6") THEN
FOR i IN (logb2(DWIDTH) + 1) TO SEED_WIDTH - 1 LOOP
IF (PRBS_SADDR_MASK_POS(i) = '1') THEN
prbs(i) <= PRBS_SADDR(i) OR lfsr_q(i + 1);
ELSIF (PRBS_EADDR_MASK_POS(i) = '1') THEN
prbs(i) <= PRBS_EADDR(i) AND lfsr_q(i + 1);
ELSE
prbs(i) <= lfsr_q(i + 1);
END IF;
END LOOP;
prbs(logb2(DWIDTH) downto 0) <= (others => '0');
ELSE
FOR i IN (logb2(DWIDTH) - 4) TO SEED_WIDTH - 1 LOOP
IF (PRBS_SADDR_MASK_POS(i) = '1') THEN
prbs(i) <= PRBS_SADDR(i) OR lfsr_q(i + 1);
ELSIF (PRBS_EADDR_MASK_POS(i) = '1') THEN
prbs(i) <= PRBS_EADDR(i) AND lfsr_q(i + 1);
ELSE
prbs(i) <= lfsr_q(i + 1);
END IF;
END LOOP;
prbs(logb2(DWIDTH) downto 0) <= (others => '0');
END IF;
END PROCESS;
END GENERATE;
xhdl2 : IF (PRBS_CMD = "INSTR" OR PRBS_CMD = "BLEN") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (prbs_seed_init = '1') THEN
lfsr_q <= ("00000" & prbs_seed_i(14 DOWNTO 0)) ;
ELSIF (clk_en = '1') THEN
lfsr_q(20) <= lfsr_q(19) ;
lfsr_q(19) <= lfsr_q(18) ;
lfsr_q(18) <= lfsr_q(20) XOR lfsr_q(17) ;
lfsr_q(17 DOWNTO 2) <= lfsr_q(16 DOWNTO 1) ;
lfsr_q(1) <= lfsr_q(20) ;
END IF;
END IF;
END PROCESS;
PROCESS (lfsr_q(SEED_WIDTH - 1 DOWNTO 1), ZEROS)
BEGIN
prbs <= (ZEROS(SEED_WIDTH - 1 DOWNTO 6) & lfsr_q(6 DOWNTO 1));
END PROCESS;
END GENERATE;
prbs_o <= prbs;
END trans;
|
bsd-2-clause
|
timvideos/HDMI2USB-jahanzeb-firmware
|
ipcore_dir/image_selector_fifo.vhd
|
3
|
10548
|
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2013 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file image_selector_fifo.vhd when simulating
-- the core, image_selector_fifo. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY image_selector_fifo IS
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC
);
END image_selector_fifo;
ARCHITECTURE image_selector_fifo_a OF image_selector_fifo IS
-- synthesis translate_off
COMPONENT wrapped_image_selector_fifo
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_image_selector_fifo USE ENTITY XilinxCoreLib.fifo_generator_v9_2(behavioral)
GENERIC MAP (
c_add_ngc_constraint => 0,
c_application_type_axis => 0,
c_application_type_rach => 0,
c_application_type_rdch => 0,
c_application_type_wach => 0,
c_application_type_wdch => 0,
c_application_type_wrch => 0,
c_axi_addr_width => 32,
c_axi_aruser_width => 1,
c_axi_awuser_width => 1,
c_axi_buser_width => 1,
c_axi_data_width => 64,
c_axi_id_width => 4,
c_axi_ruser_width => 1,
c_axi_type => 0,
c_axi_wuser_width => 1,
c_axis_tdata_width => 64,
c_axis_tdest_width => 4,
c_axis_tid_width => 8,
c_axis_tkeep_width => 4,
c_axis_tstrb_width => 4,
c_axis_tuser_width => 4,
c_axis_type => 0,
c_common_clock => 0,
c_count_type => 0,
c_data_count_width => 8,
c_default_value => "BlankString",
c_din_width => 24,
c_din_width_axis => 1,
c_din_width_rach => 32,
c_din_width_rdch => 64,
c_din_width_wach => 32,
c_din_width_wdch => 64,
c_din_width_wrch => 2,
c_dout_rst_val => "0",
c_dout_width => 24,
c_enable_rlocs => 0,
c_enable_rst_sync => 1,
c_error_injection_type => 0,
c_error_injection_type_axis => 0,
c_error_injection_type_rach => 0,
c_error_injection_type_rdch => 0,
c_error_injection_type_wach => 0,
c_error_injection_type_wdch => 0,
c_error_injection_type_wrch => 0,
c_family => "spartan6",
c_full_flags_rst_val => 0,
c_has_almost_empty => 1,
c_has_almost_full => 1,
c_has_axi_aruser => 0,
c_has_axi_awuser => 0,
c_has_axi_buser => 0,
c_has_axi_rd_channel => 0,
c_has_axi_ruser => 0,
c_has_axi_wr_channel => 0,
c_has_axi_wuser => 0,
c_has_axis_tdata => 0,
c_has_axis_tdest => 0,
c_has_axis_tid => 0,
c_has_axis_tkeep => 0,
c_has_axis_tlast => 0,
c_has_axis_tready => 1,
c_has_axis_tstrb => 0,
c_has_axis_tuser => 0,
c_has_backup => 0,
c_has_data_count => 0,
c_has_data_counts_axis => 0,
c_has_data_counts_rach => 0,
c_has_data_counts_rdch => 0,
c_has_data_counts_wach => 0,
c_has_data_counts_wdch => 0,
c_has_data_counts_wrch => 0,
c_has_int_clk => 0,
c_has_master_ce => 0,
c_has_meminit_file => 0,
c_has_overflow => 0,
c_has_prog_flags_axis => 0,
c_has_prog_flags_rach => 0,
c_has_prog_flags_rdch => 0,
c_has_prog_flags_wach => 0,
c_has_prog_flags_wdch => 0,
c_has_prog_flags_wrch => 0,
c_has_rd_data_count => 0,
c_has_rd_rst => 0,
c_has_rst => 1,
c_has_slave_ce => 0,
c_has_srst => 0,
c_has_underflow => 0,
c_has_valid => 1,
c_has_wr_ack => 0,
c_has_wr_data_count => 0,
c_has_wr_rst => 0,
c_implementation_type => 2,
c_implementation_type_axis => 1,
c_implementation_type_rach => 1,
c_implementation_type_rdch => 1,
c_implementation_type_wach => 1,
c_implementation_type_wdch => 1,
c_implementation_type_wrch => 1,
c_init_wr_pntr_val => 0,
c_interface_type => 0,
c_memory_type => 1,
c_mif_file_name => "BlankString",
c_msgon_val => 1,
c_optimization_mode => 0,
c_overflow_low => 0,
c_preload_latency => 0,
c_preload_regs => 1,
c_prim_fifo_type => "512x36",
c_prog_empty_thresh_assert_val => 4,
c_prog_empty_thresh_assert_val_axis => 1022,
c_prog_empty_thresh_assert_val_rach => 1022,
c_prog_empty_thresh_assert_val_rdch => 1022,
c_prog_empty_thresh_assert_val_wach => 1022,
c_prog_empty_thresh_assert_val_wdch => 1022,
c_prog_empty_thresh_assert_val_wrch => 1022,
c_prog_empty_thresh_negate_val => 5,
c_prog_empty_type => 0,
c_prog_empty_type_axis => 0,
c_prog_empty_type_rach => 0,
c_prog_empty_type_rdch => 0,
c_prog_empty_type_wach => 0,
c_prog_empty_type_wdch => 0,
c_prog_empty_type_wrch => 0,
c_prog_full_thresh_assert_val => 255,
c_prog_full_thresh_assert_val_axis => 1023,
c_prog_full_thresh_assert_val_rach => 1023,
c_prog_full_thresh_assert_val_rdch => 1023,
c_prog_full_thresh_assert_val_wach => 1023,
c_prog_full_thresh_assert_val_wdch => 1023,
c_prog_full_thresh_assert_val_wrch => 1023,
c_prog_full_thresh_negate_val => 254,
c_prog_full_type => 0,
c_prog_full_type_axis => 0,
c_prog_full_type_rach => 0,
c_prog_full_type_rdch => 0,
c_prog_full_type_wach => 0,
c_prog_full_type_wdch => 0,
c_prog_full_type_wrch => 0,
c_rach_type => 0,
c_rd_data_count_width => 8,
c_rd_depth => 256,
c_rd_freq => 1,
c_rd_pntr_width => 8,
c_rdch_type => 0,
c_reg_slice_mode_axis => 0,
c_reg_slice_mode_rach => 0,
c_reg_slice_mode_rdch => 0,
c_reg_slice_mode_wach => 0,
c_reg_slice_mode_wdch => 0,
c_reg_slice_mode_wrch => 0,
c_synchronizer_stage => 2,
c_underflow_low => 0,
c_use_common_overflow => 0,
c_use_common_underflow => 0,
c_use_default_settings => 0,
c_use_dout_rst => 1,
c_use_ecc => 0,
c_use_ecc_axis => 0,
c_use_ecc_rach => 0,
c_use_ecc_rdch => 0,
c_use_ecc_wach => 0,
c_use_ecc_wdch => 0,
c_use_ecc_wrch => 0,
c_use_embedded_reg => 0,
c_use_fifo16_flags => 0,
c_use_fwft_data_count => 0,
c_valid_low => 0,
c_wach_type => 0,
c_wdch_type => 0,
c_wr_ack_low => 0,
c_wr_data_count_width => 8,
c_wr_depth => 256,
c_wr_depth_axis => 1024,
c_wr_depth_rach => 16,
c_wr_depth_rdch => 1024,
c_wr_depth_wach => 16,
c_wr_depth_wdch => 1024,
c_wr_depth_wrch => 16,
c_wr_freq => 1,
c_wr_pntr_width => 8,
c_wr_pntr_width_axis => 10,
c_wr_pntr_width_rach => 4,
c_wr_pntr_width_rdch => 10,
c_wr_pntr_width_wach => 4,
c_wr_pntr_width_wdch => 10,
c_wr_pntr_width_wrch => 4,
c_wr_response_latency => 1,
c_wrch_type => 0
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_image_selector_fifo
PORT MAP (
rst => rst,
wr_clk => wr_clk,
rd_clk => rd_clk,
din => din,
wr_en => wr_en,
rd_en => rd_en,
dout => dout,
full => full,
almost_full => almost_full,
empty => empty,
almost_empty => almost_empty,
valid => valid
);
-- synthesis translate_on
END image_selector_fifo_a;
|
bsd-2-clause
|
timvideos/HDMI2USB-jahanzeb-firmware
|
ipcore_dir/cmdfifo.vhd
|
3
|
10425
|
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2013 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file cmdfifo.vhd when simulating
-- the core, cmdfifo. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY cmdfifo IS
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC
);
END cmdfifo;
ARCHITECTURE cmdfifo_a OF cmdfifo IS
-- synthesis translate_off
COMPONENT wrapped_cmdfifo
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_cmdfifo USE ENTITY XilinxCoreLib.fifo_generator_v9_2(behavioral)
GENERIC MAP (
c_add_ngc_constraint => 0,
c_application_type_axis => 0,
c_application_type_rach => 0,
c_application_type_rdch => 0,
c_application_type_wach => 0,
c_application_type_wdch => 0,
c_application_type_wrch => 0,
c_axi_addr_width => 32,
c_axi_aruser_width => 1,
c_axi_awuser_width => 1,
c_axi_buser_width => 1,
c_axi_data_width => 64,
c_axi_id_width => 4,
c_axi_ruser_width => 1,
c_axi_type => 0,
c_axi_wuser_width => 1,
c_axis_tdata_width => 64,
c_axis_tdest_width => 4,
c_axis_tid_width => 8,
c_axis_tkeep_width => 4,
c_axis_tstrb_width => 4,
c_axis_tuser_width => 4,
c_axis_type => 0,
c_common_clock => 0,
c_count_type => 0,
c_data_count_width => 9,
c_default_value => "BlankString",
c_din_width => 8,
c_din_width_axis => 1,
c_din_width_rach => 32,
c_din_width_rdch => 64,
c_din_width_wach => 32,
c_din_width_wdch => 64,
c_din_width_wrch => 2,
c_dout_rst_val => "0",
c_dout_width => 16,
c_enable_rlocs => 0,
c_enable_rst_sync => 1,
c_error_injection_type => 0,
c_error_injection_type_axis => 0,
c_error_injection_type_rach => 0,
c_error_injection_type_rdch => 0,
c_error_injection_type_wach => 0,
c_error_injection_type_wdch => 0,
c_error_injection_type_wrch => 0,
c_family => "spartan6",
c_full_flags_rst_val => 1,
c_has_almost_empty => 1,
c_has_almost_full => 1,
c_has_axi_aruser => 0,
c_has_axi_awuser => 0,
c_has_axi_buser => 0,
c_has_axi_rd_channel => 0,
c_has_axi_ruser => 0,
c_has_axi_wr_channel => 0,
c_has_axi_wuser => 0,
c_has_axis_tdata => 0,
c_has_axis_tdest => 0,
c_has_axis_tid => 0,
c_has_axis_tkeep => 0,
c_has_axis_tlast => 0,
c_has_axis_tready => 1,
c_has_axis_tstrb => 0,
c_has_axis_tuser => 0,
c_has_backup => 0,
c_has_data_count => 0,
c_has_data_counts_axis => 0,
c_has_data_counts_rach => 0,
c_has_data_counts_rdch => 0,
c_has_data_counts_wach => 0,
c_has_data_counts_wdch => 0,
c_has_data_counts_wrch => 0,
c_has_int_clk => 0,
c_has_master_ce => 0,
c_has_meminit_file => 0,
c_has_overflow => 0,
c_has_prog_flags_axis => 0,
c_has_prog_flags_rach => 0,
c_has_prog_flags_rdch => 0,
c_has_prog_flags_wach => 0,
c_has_prog_flags_wdch => 0,
c_has_prog_flags_wrch => 0,
c_has_rd_data_count => 0,
c_has_rd_rst => 0,
c_has_rst => 1,
c_has_slave_ce => 0,
c_has_srst => 0,
c_has_underflow => 0,
c_has_valid => 1,
c_has_wr_ack => 0,
c_has_wr_data_count => 0,
c_has_wr_rst => 0,
c_implementation_type => 2,
c_implementation_type_axis => 1,
c_implementation_type_rach => 1,
c_implementation_type_rdch => 1,
c_implementation_type_wach => 1,
c_implementation_type_wdch => 1,
c_implementation_type_wrch => 1,
c_init_wr_pntr_val => 0,
c_interface_type => 0,
c_memory_type => 1,
c_mif_file_name => "BlankString",
c_msgon_val => 1,
c_optimization_mode => 0,
c_overflow_low => 0,
c_preload_latency => 0,
c_preload_regs => 1,
c_prim_fifo_type => "512x36",
c_prog_empty_thresh_assert_val => 4,
c_prog_empty_thresh_assert_val_axis => 1022,
c_prog_empty_thresh_assert_val_rach => 1022,
c_prog_empty_thresh_assert_val_rdch => 1022,
c_prog_empty_thresh_assert_val_wach => 1022,
c_prog_empty_thresh_assert_val_wdch => 1022,
c_prog_empty_thresh_assert_val_wrch => 1022,
c_prog_empty_thresh_negate_val => 5,
c_prog_empty_type => 0,
c_prog_empty_type_axis => 0,
c_prog_empty_type_rach => 0,
c_prog_empty_type_rdch => 0,
c_prog_empty_type_wach => 0,
c_prog_empty_type_wdch => 0,
c_prog_empty_type_wrch => 0,
c_prog_full_thresh_assert_val => 511,
c_prog_full_thresh_assert_val_axis => 1023,
c_prog_full_thresh_assert_val_rach => 1023,
c_prog_full_thresh_assert_val_rdch => 1023,
c_prog_full_thresh_assert_val_wach => 1023,
c_prog_full_thresh_assert_val_wdch => 1023,
c_prog_full_thresh_assert_val_wrch => 1023,
c_prog_full_thresh_negate_val => 510,
c_prog_full_type => 0,
c_prog_full_type_axis => 0,
c_prog_full_type_rach => 0,
c_prog_full_type_rdch => 0,
c_prog_full_type_wach => 0,
c_prog_full_type_wdch => 0,
c_prog_full_type_wrch => 0,
c_rach_type => 0,
c_rd_data_count_width => 8,
c_rd_depth => 256,
c_rd_freq => 1,
c_rd_pntr_width => 8,
c_rdch_type => 0,
c_reg_slice_mode_axis => 0,
c_reg_slice_mode_rach => 0,
c_reg_slice_mode_rdch => 0,
c_reg_slice_mode_wach => 0,
c_reg_slice_mode_wdch => 0,
c_reg_slice_mode_wrch => 0,
c_synchronizer_stage => 2,
c_underflow_low => 0,
c_use_common_overflow => 0,
c_use_common_underflow => 0,
c_use_default_settings => 0,
c_use_dout_rst => 1,
c_use_ecc => 0,
c_use_ecc_axis => 0,
c_use_ecc_rach => 0,
c_use_ecc_rdch => 0,
c_use_ecc_wach => 0,
c_use_ecc_wdch => 0,
c_use_ecc_wrch => 0,
c_use_embedded_reg => 0,
c_use_fifo16_flags => 0,
c_use_fwft_data_count => 0,
c_valid_low => 0,
c_wach_type => 0,
c_wdch_type => 0,
c_wr_ack_low => 0,
c_wr_data_count_width => 9,
c_wr_depth => 512,
c_wr_depth_axis => 1024,
c_wr_depth_rach => 16,
c_wr_depth_rdch => 1024,
c_wr_depth_wach => 16,
c_wr_depth_wdch => 1024,
c_wr_depth_wrch => 16,
c_wr_freq => 1,
c_wr_pntr_width => 9,
c_wr_pntr_width_axis => 10,
c_wr_pntr_width_rach => 4,
c_wr_pntr_width_rdch => 10,
c_wr_pntr_width_wach => 4,
c_wr_pntr_width_wdch => 10,
c_wr_pntr_width_wrch => 4,
c_wr_response_latency => 1,
c_wrch_type => 0
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_cmdfifo
PORT MAP (
rst => rst,
wr_clk => wr_clk,
rd_clk => rd_clk,
din => din,
wr_en => wr_en,
rd_en => rd_en,
dout => dout,
full => full,
almost_full => almost_full,
empty => empty,
almost_empty => almost_empty,
valid => valid
);
-- synthesis translate_on
END cmdfifo_a;
|
bsd-2-clause
|
timvideos/HDMI2USB-jahanzeb-firmware
|
ipcore_dir/cdcfifo/simulation/cdcfifo_pctrl.vhd
|
3
|
20416
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: cdcfifo_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.cdcfifo_pkg.ALL;
ENTITY cdcfifo_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF cdcfifo_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL reset_ex1 : STD_LOGIC := '0';
SIGNAL reset_ex2 : STD_LOGIC := '0';
SIGNAL reset_ex3 : STD_LOGIC := '0';
SIGNAL ae_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL af_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL sim_done_d1 : STD_LOGIC := '0';
SIGNAL sim_done_wr1 : STD_LOGIC := '0';
SIGNAL sim_done_wr2 : STD_LOGIC := '0';
SIGNAL empty_d1 : STD_LOGIC := '0';
SIGNAL empty_wr_dom1 : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL state_rd_dom1 : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '0';
SIGNAL rd_en_wr1 : STD_LOGIC := '0';
SIGNAL wr_en_d1 : STD_LOGIC := '0';
SIGNAL wr_en_rd1 : STD_LOGIC := '0';
SIGNAL full_chk_d1 : STD_LOGIC := '0';
SIGNAL full_chk_rd1 : STD_LOGIC := '0';
SIGNAL empty_wr_dom2 : STD_LOGIC := '0';
SIGNAL state_rd_dom2 : STD_LOGIC := '0';
SIGNAL state_rd_dom3 : STD_LOGIC := '0';
SIGNAL rd_en_wr2 : STD_LOGIC := '0';
SIGNAL wr_en_rd2 : STD_LOGIC := '0';
SIGNAL full_chk_rd2 : STD_LOGIC := '0';
SIGNAL reset_en_d1 : STD_LOGIC := '0';
SIGNAL reset_en_rd1 : STD_LOGIC := '0';
SIGNAL reset_en_rd2 : STD_LOGIC := '0';
SIGNAL data_chk_wr_d1 : STD_LOGIC := '0';
SIGNAL data_chk_rd1 : STD_LOGIC := '0';
SIGNAL data_chk_rd2 : STD_LOGIC := '0';
SIGNAL full_d1 : STD_LOGIC := '0';
SIGNAL full_rd_dom1 : STD_LOGIC := '0';
SIGNAL full_rd_dom2 : STD_LOGIC := '0';
SIGNAL af_chk_d1 : STD_LOGIC := '0';
SIGNAL af_chk_rd1 : STD_LOGIC := '0';
SIGNAL af_chk_rd2 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_rd2 & empty_chk_i & af_chk_rd2 & ae_chk_i;
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_wr2 = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
rdw_gt_wrw <= (OTHERS => '1');
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0' AND state_rd_dom3 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
-- Reset pulse extension require for FULL flags checks
-- FULL flag may stay high for 3 clocks after reset is removed.
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
reset_ex1 <= '1';
reset_ex2 <= '1';
reset_ex3 <= '1';
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
reset_ex1 <= '0';
reset_ex2 <= reset_ex1;
reset_ex3 <= reset_ex2;
END IF;
END PROCESS;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_wr2 = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_rd2 = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 100 ns;
PRC_RD_EN <= prc_re_i AFTER 50 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-- Almost full flag checks
PROCESS(WR_CLK,reset_ex3)
BEGIN
IF(reset_ex3 = '1') THEN
af_chk_i <= '0';
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
IF((FULL = '1' AND ALMOST_FULL = '0') OR (empty_wr_dom2 = '1' AND ALMOST_FULL = '1' AND C_WR_PNTR_WIDTH > 4)) THEN
af_chk_i <= '1';
ELSE
af_chk_i <= '0';
END IF;
END IF;
END PROCESS;
-- Almost empty flag checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
ae_chk_i <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF((EMPTY = '1' AND ALMOST_EMPTY = '0') OR
(state = '1' AND full_rd_dom2 = '1' AND ALMOST_EMPTY = '1')) THEN
ae_chk_i <= '1';
ELSE
ae_chk_i <= '0';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- SYNCHRONIZERS B/W WRITE AND READ DOMAINS
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
empty_wr_dom1 <= '1';
empty_wr_dom2 <= '1';
state_d1 <= '0';
wr_en_d1 <= '0';
rd_en_wr1 <= '0';
rd_en_wr2 <= '0';
full_chk_d1 <= '0';
af_chk_d1 <= '0';
full_d1 <= '0';
reset_en_d1 <= '0';
sim_done_wr1 <= '0';
sim_done_wr2 <= '0';
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
sim_done_wr1 <= sim_done_d1;
sim_done_wr2 <= sim_done_wr1;
reset_en_d1 <= reset_en_i;
full_d1 <= FULL;
state_d1 <= state;
empty_wr_dom1 <= empty_d1;
empty_wr_dom2 <= empty_wr_dom1;
wr_en_d1 <= wr_en_i;
rd_en_wr1 <= rd_en_d1;
rd_en_wr2 <= rd_en_wr1;
full_chk_d1 <= full_chk_i;
af_chk_d1 <= af_chk_i;
END IF;
END PROCESS;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_d1 <= '1';
state_rd_dom1 <= '0';
state_rd_dom2 <= '0';
state_rd_dom3 <= '0';
wr_en_rd1 <= '0';
wr_en_rd2 <= '0';
rd_en_d1 <= '0';
full_chk_rd1 <= '0';
full_chk_rd2 <= '0';
af_chk_rd1 <= '0';
af_chk_rd2 <= '0';
full_rd_dom1 <= '0';
full_rd_dom2 <= '0';
reset_en_rd1 <= '0';
reset_en_rd2 <= '0';
sim_done_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
sim_done_d1 <= sim_done_i;
reset_en_rd1 <= reset_en_d1;
reset_en_rd2 <= reset_en_rd1;
empty_d1 <= EMPTY;
rd_en_d1 <= rd_en_i;
state_rd_dom1 <= state_d1;
state_rd_dom2 <= state_rd_dom1;
state_rd_dom3 <= state_rd_dom2;
wr_en_rd1 <= wr_en_d1;
wr_en_rd2 <= wr_en_rd1;
full_chk_rd1 <= full_chk_d1;
full_chk_rd2 <= full_chk_rd1;
af_chk_rd1 <= af_chk_d1;
af_chk_rd2 <= af_chk_rd1;
full_rd_dom1 <= full_d1;
full_rd_dom2 <= full_rd_dom1;
END IF;
END PROCESS;
RESET_EN <= reset_en_rd2;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:cdcfifo_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_wr2 = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:cdcfifo_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_rd2 = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND empty_wr_dom2 = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(empty_wr_dom2 = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
|
bsd-2-clause
|
shailcoolboy/Warp-Trinity
|
PlatformSupport/CustomPeripherals/pcores/linkport_v1_00_a/hdl/vhdl/rx_ll_nfc.vhd
|
4
|
6822
|
--
-- Project: Aurora Module Generator version 2.4
--
-- Date: $Date: 2005/11/07 21:30:54 $
-- Tag: $Name: i+IP+98818 $
-- File: $RCSfile: rx_ll_nfc_vhd.ejava,v $
-- Rev: $Revision: 1.1.2.4 $
--
-- Company: Xilinx
-- Contributors: R. K. Awalt, B. L. Woodard, N. Gulstone
--
-- Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
-- INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
-- PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-- ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
-- APPLICATION OR STANDARD, XILINX IS MAKING NO
-- REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
-- FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
-- RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
-- REQUIRE FOR YOUR IMPLEMENTATION. XILINX
-- EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
-- RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
-- INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
-- FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
-- OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE.
--
-- (c) Copyright 2004 Xilinx, Inc.
-- All rights reserved.
--
--
-- RX_LL_NFC
--
-- Author: Nigel Gulstone
-- Xilinx - Embedded Networking System Engineering Group
--
-- VHDL Translation: B. Woodard, N. Gulstone
--
-- Description: the RX_LL_NFC module detects, decodes and executes NFC messages
-- from the channel partner. When a message is recieved, the module
-- signals the TX_LL module that idles are required until the number
-- of idles the TX_LL module sends are enough to fulfil the request.
--
-- This module supports 1 2-byte lane designs
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use WORK.AURORA.all;
entity RX_LL_NFC is
port (
-- Aurora Lane Interface
RX_SNF : in std_logic;
RX_FC_NB : in std_logic_vector(0 to 3);
-- TX_LL Interface
DECREMENT_NFC : in std_logic;
TX_WAIT : out std_logic;
-- Global Logic Interface
CHANNEL_UP : in std_logic;
-- USER Interface
USER_CLK : in std_logic
);
end RX_LL_NFC;
architecture RTL of RX_LL_NFC is
-- Parameter Declarations --
constant DLY : time := 1 ns;
-- External Register Declarations --
signal TX_WAIT_Buffer : std_logic;
-- Internal Register Declarations --
signal load_nfc_r : std_logic;
signal fcnb_r : std_logic_vector(0 to 3);
signal nfc_counter_r : std_logic_vector(0 to 8);
signal xoff_r : std_logic;
signal fcnb_decode_c : std_logic_vector(0 to 8);
begin
TX_WAIT <= TX_WAIT_Buffer;
-- Main Body of Code --
-- ____________________Stage 1: Detect the most recent NFC message___________
-- Generate the load NFC signal if an NFC signal is detected.
process(USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
load_nfc_r <= RX_SNF after DLY;
end if;
end process;
-- Register the FC_NB signal.
process(USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
fcnb_r <= RX_FC_NB after DLY;
end if;
end process;
-- _________________Stage 2: Use the FCNB code to set the counter ______________
-- We use a counter to keep track of the number of dead cycles we must produce to
-- satisfy the NFC request from the Channel Partner. Note we *increment* nfc_counter
-- when decrement NFC is asserted. This is because the nfc counter uses the difference
-- between the max value and the current value to determine how many cycles to demand
-- a pause. This allows us to use the carry chain more effectively to save LUTS, and
-- gives us a registered output from the counter.
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
if (CHANNEL_UP = '0') then
nfc_counter_r <= "100000000" after DLY;
else
if (load_nfc_r = '1') then
nfc_counter_r <= fcnb_decode_c after DLY;
else
if ((not nfc_counter_r(0) and DECREMENT_NFC and not xoff_r) = '1') then
nfc_counter_r <= nfc_counter_r + "000000001";
end if;
end if;
end if;
end if;
end process;
-- We load the counter with a decoded version of the FCNB code. The decode values are
-- chosen such that the counter will assert TX_WAIT for the number of cycles required
-- by the FCNB code.
process (fcnb_r)
begin
case fcnb_r is
when "0000" =>
fcnb_decode_c <= "100000000"; -- XON
when "0001" =>
fcnb_decode_c <= "011111110"; -- 2
when "0010" =>
fcnb_decode_c <= "011111100"; -- 4
when "0011" =>
fcnb_decode_c <= "011111000"; -- 8
when "0100" =>
fcnb_decode_c <= "011110000"; -- 16
when "0101" =>
fcnb_decode_c <= "011100000"; -- 32
when "0110" =>
fcnb_decode_c <= "011000000"; -- 64
when "0111" =>
fcnb_decode_c <= "010000000"; -- 128
when "1000" =>
fcnb_decode_c <= "000000000"; -- 256
when "1111" =>
fcnb_decode_c <= "000000000"; -- 8
when others =>
fcnb_decode_c <= "100000000"; -- 8
end case;
end process;
-- The XOFF signal forces an indefinite wait. We decode FCNB to determine whether
-- XOFF should be asserted.
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
if (CHANNEL_UP = '0') then
xoff_r <= '0' after DLY;
else
if (load_nfc_r = '1') then
if (fcnb_r = "1111") then
xoff_r <= '1' after DLY;
else
xoff_r <= '0' after DLY;
end if;
end if;
end if;
end if;
end process;
-- The TXWAIT signal comes from the MSBit of the counter. We wait whenever the counter
-- is not at max value.
TX_WAIT_Buffer <= not nfc_counter_r(0);
end RTL;
|
bsd-2-clause
|
shailcoolboy/Warp-Trinity
|
PlatformSupport/CustomPeripherals/pcores/linkport_v1_00_a/hdl/vhdl/aurora_ctrl.vhd
|
4
|
850
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity aurora_ctrl is
port (
pwdn_in : in std_logic ;
user_clk : in std_logic ;
dcm_not_locked : out std_logic;
loopback : out std_logic_vector(1 downto 0);
power_down : out std_logic;
nfc_req_1 : out std_logic ;
nfc_nb : out std_logic_vector(3 downto 0)
);
end aurora_ctrl;
architecture aurora_ctrl_b1 of aurora_ctrl is
signal pwdn_reg : std_logic_vector(1 downto 0);
begin
dcm_not_locked <= '0';
loopback <= "00";
process(user_clk)
begin
if user_clk = '1' and user_clk'event then
pwdn_reg <= pwdn_reg(0)&pwdn_in;
end if;
end process;
-- power_down <= pwdn_reg(1);
power_down <= '0';
-- Native Flow Control Interface
nfc_req_1 <= '1';
nfc_nb <= "0000";
end aurora_ctrl_b1;
|
bsd-2-clause
|
timvideos/HDMI2USB-jahanzeb-firmware
|
ipcore_dir/bytefifoFPGA.vhd
|
3
|
10675
|
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2013 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file bytefifoFPGA.vhd when simulating
-- the core, bytefifoFPGA. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY bytefifoFPGA IS
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
prog_full : OUT STD_LOGIC
);
END bytefifoFPGA;
ARCHITECTURE bytefifoFPGA_a OF bytefifoFPGA IS
-- synthesis translate_off
COMPONENT wrapped_bytefifoFPGA
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
prog_full : OUT STD_LOGIC
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_bytefifoFPGA USE ENTITY XilinxCoreLib.fifo_generator_v9_2(behavioral)
GENERIC MAP (
c_add_ngc_constraint => 0,
c_application_type_axis => 0,
c_application_type_rach => 0,
c_application_type_rdch => 0,
c_application_type_wach => 0,
c_application_type_wdch => 0,
c_application_type_wrch => 0,
c_axi_addr_width => 32,
c_axi_aruser_width => 1,
c_axi_awuser_width => 1,
c_axi_buser_width => 1,
c_axi_data_width => 64,
c_axi_id_width => 4,
c_axi_ruser_width => 1,
c_axi_type => 0,
c_axi_wuser_width => 1,
c_axis_tdata_width => 64,
c_axis_tdest_width => 4,
c_axis_tid_width => 8,
c_axis_tkeep_width => 4,
c_axis_tstrb_width => 4,
c_axis_tuser_width => 4,
c_axis_type => 0,
c_common_clock => 0,
c_count_type => 0,
c_data_count_width => 15,
c_default_value => "BlankString",
c_din_width => 8,
c_din_width_axis => 1,
c_din_width_rach => 32,
c_din_width_rdch => 64,
c_din_width_wach => 32,
c_din_width_wdch => 64,
c_din_width_wrch => 2,
c_dout_rst_val => "0",
c_dout_width => 8,
c_enable_rlocs => 0,
c_enable_rst_sync => 1,
c_error_injection_type => 0,
c_error_injection_type_axis => 0,
c_error_injection_type_rach => 0,
c_error_injection_type_rdch => 0,
c_error_injection_type_wach => 0,
c_error_injection_type_wdch => 0,
c_error_injection_type_wrch => 0,
c_family => "spartan6",
c_full_flags_rst_val => 0,
c_has_almost_empty => 1,
c_has_almost_full => 1,
c_has_axi_aruser => 0,
c_has_axi_awuser => 0,
c_has_axi_buser => 0,
c_has_axi_rd_channel => 0,
c_has_axi_ruser => 0,
c_has_axi_wr_channel => 0,
c_has_axi_wuser => 0,
c_has_axis_tdata => 0,
c_has_axis_tdest => 0,
c_has_axis_tid => 0,
c_has_axis_tkeep => 0,
c_has_axis_tlast => 0,
c_has_axis_tready => 1,
c_has_axis_tstrb => 0,
c_has_axis_tuser => 0,
c_has_backup => 0,
c_has_data_count => 0,
c_has_data_counts_axis => 0,
c_has_data_counts_rach => 0,
c_has_data_counts_rdch => 0,
c_has_data_counts_wach => 0,
c_has_data_counts_wdch => 0,
c_has_data_counts_wrch => 0,
c_has_int_clk => 0,
c_has_master_ce => 0,
c_has_meminit_file => 0,
c_has_overflow => 1,
c_has_prog_flags_axis => 0,
c_has_prog_flags_rach => 0,
c_has_prog_flags_rdch => 0,
c_has_prog_flags_wach => 0,
c_has_prog_flags_wdch => 0,
c_has_prog_flags_wrch => 0,
c_has_rd_data_count => 0,
c_has_rd_rst => 0,
c_has_rst => 1,
c_has_slave_ce => 0,
c_has_srst => 0,
c_has_underflow => 1,
c_has_valid => 0,
c_has_wr_ack => 0,
c_has_wr_data_count => 0,
c_has_wr_rst => 0,
c_implementation_type => 2,
c_implementation_type_axis => 1,
c_implementation_type_rach => 1,
c_implementation_type_rdch => 1,
c_implementation_type_wach => 1,
c_implementation_type_wdch => 1,
c_implementation_type_wrch => 1,
c_init_wr_pntr_val => 0,
c_interface_type => 0,
c_memory_type => 1,
c_mif_file_name => "BlankString",
c_msgon_val => 1,
c_optimization_mode => 0,
c_overflow_low => 0,
c_preload_latency => 0,
c_preload_regs => 1,
c_prim_fifo_type => "8kx4",
c_prog_empty_thresh_assert_val => 4,
c_prog_empty_thresh_assert_val_axis => 1022,
c_prog_empty_thresh_assert_val_rach => 1022,
c_prog_empty_thresh_assert_val_rdch => 1022,
c_prog_empty_thresh_assert_val_wach => 1022,
c_prog_empty_thresh_assert_val_wdch => 1022,
c_prog_empty_thresh_assert_val_wrch => 1022,
c_prog_empty_thresh_negate_val => 5,
c_prog_empty_type => 0,
c_prog_empty_type_axis => 0,
c_prog_empty_type_rach => 0,
c_prog_empty_type_rdch => 0,
c_prog_empty_type_wach => 0,
c_prog_empty_type_wdch => 0,
c_prog_empty_type_wrch => 0,
c_prog_full_thresh_assert_val => 32256,
c_prog_full_thresh_assert_val_axis => 1023,
c_prog_full_thresh_assert_val_rach => 1023,
c_prog_full_thresh_assert_val_rdch => 1023,
c_prog_full_thresh_assert_val_wach => 1023,
c_prog_full_thresh_assert_val_wdch => 1023,
c_prog_full_thresh_assert_val_wrch => 1023,
c_prog_full_thresh_negate_val => 32255,
c_prog_full_type => 1,
c_prog_full_type_axis => 0,
c_prog_full_type_rach => 0,
c_prog_full_type_rdch => 0,
c_prog_full_type_wach => 0,
c_prog_full_type_wdch => 0,
c_prog_full_type_wrch => 0,
c_rach_type => 0,
c_rd_data_count_width => 15,
c_rd_depth => 32768,
c_rd_freq => 1,
c_rd_pntr_width => 15,
c_rdch_type => 0,
c_reg_slice_mode_axis => 0,
c_reg_slice_mode_rach => 0,
c_reg_slice_mode_rdch => 0,
c_reg_slice_mode_wach => 0,
c_reg_slice_mode_wdch => 0,
c_reg_slice_mode_wrch => 0,
c_synchronizer_stage => 2,
c_underflow_low => 0,
c_use_common_overflow => 0,
c_use_common_underflow => 0,
c_use_default_settings => 0,
c_use_dout_rst => 1,
c_use_ecc => 0,
c_use_ecc_axis => 0,
c_use_ecc_rach => 0,
c_use_ecc_rdch => 0,
c_use_ecc_wach => 0,
c_use_ecc_wdch => 0,
c_use_ecc_wrch => 0,
c_use_embedded_reg => 0,
c_use_fifo16_flags => 0,
c_use_fwft_data_count => 0,
c_valid_low => 0,
c_wach_type => 0,
c_wdch_type => 0,
c_wr_ack_low => 0,
c_wr_data_count_width => 15,
c_wr_depth => 32768,
c_wr_depth_axis => 1024,
c_wr_depth_rach => 16,
c_wr_depth_rdch => 1024,
c_wr_depth_wach => 16,
c_wr_depth_wdch => 1024,
c_wr_depth_wrch => 16,
c_wr_freq => 1,
c_wr_pntr_width => 15,
c_wr_pntr_width_axis => 10,
c_wr_pntr_width_rach => 4,
c_wr_pntr_width_rdch => 10,
c_wr_pntr_width_wach => 4,
c_wr_pntr_width_wdch => 10,
c_wr_pntr_width_wrch => 4,
c_wr_response_latency => 1,
c_wrch_type => 0
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_bytefifoFPGA
PORT MAP (
rst => rst,
wr_clk => wr_clk,
rd_clk => rd_clk,
din => din,
wr_en => wr_en,
rd_en => rd_en,
dout => dout,
full => full,
almost_full => almost_full,
overflow => overflow,
empty => empty,
almost_empty => almost_empty,
underflow => underflow,
prog_full => prog_full
);
-- synthesis translate_on
END bytefifoFPGA_a;
|
bsd-2-clause
|
shailcoolboy/Warp-Trinity
|
edk_user_repository/WARP/pcores/linkport_v1_00_a/hdl/vhdl/error_detect.vhd
|
4
|
9545
|
--
-- Project: Aurora Module Generator version 2.4
--
-- Date: $Date: 2005/11/07 21:30:52 $
-- Tag: $Name: i+IP+98818 $
-- File: $RCSfile: error_detect_vhd.ejava,v $
-- Rev: $Revision: 1.1.2.1 $
--
-- Company: Xilinx
-- Contributors: R. K. Awalt, B. L. Woodard, N. Gulstone
--
-- Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
-- INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
-- PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-- ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
-- APPLICATION OR STANDARD, XILINX IS MAKING NO
-- REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
-- FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
-- RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
-- REQUIRE FOR YOUR IMPLEMENTATION. XILINX
-- EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
-- RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
-- INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
-- FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
-- OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE.
--
-- (c) Copyright 2004 Xilinx, Inc.
-- All rights reserved.
--
--
-- ERROR_DETECT
--
-- Author: Nigel Gulstone
-- Xilinx - Embedded Networking System Engineering Group
--
-- VHDL Translation: Brian Woodard
-- Xilinx - Garden Valley Design Team
--
-- Description : The ERROR_DETECT module monitors the MGT to detect hard
-- errors. It accumulates the Soft errors according to the
-- leaky bucket algorithm described in the Aurora
-- Specification to detect Hard errors. All errors are
-- reported to the Global Logic Interface.
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use WORK.AURORA.all;
entity ERROR_DETECT is
port (
-- Lane Init SM Interface
ENABLE_ERROR_DETECT : in std_logic;
HARD_ERROR_RESET : out std_logic;
-- Global Logic Interface
SOFT_ERROR : out std_logic;
HARD_ERROR : out std_logic;
-- MGT Interface
RX_DISP_ERR : in std_logic_vector(1 downto 0);
TX_K_ERR : in std_logic_vector(1 downto 0);
RX_NOT_IN_TABLE : in std_logic_vector(1 downto 0);
RX_BUF_STATUS : in std_logic;
TX_BUF_ERR : in std_logic;
RX_REALIGN : in std_logic;
-- System Interface
USER_CLK : in std_logic
);
end ERROR_DETECT;
architecture RTL of ERROR_DETECT is
-- Parameter Declarations --
constant DLY : time := 1 ns;
-- External Register Declarations --
signal HARD_ERROR_RESET_Buffer : std_logic;
signal SOFT_ERROR_Buffer : std_logic;
signal HARD_ERROR_Buffer : std_logic;
-- Internal Register Declarations --
signal count_r : std_logic_vector(0 to 1);
signal bucket_full_r : std_logic;
signal soft_error_r : std_logic_vector(0 to 1);
signal good_count_r : std_logic_vector(0 to 1);
signal soft_error_flop_r : std_logic; -- Traveling flop for timing.
signal hard_error_flop_r : std_logic; -- Traveling flop for timing.
begin
HARD_ERROR_RESET <= HARD_ERROR_RESET_Buffer;
SOFT_ERROR <= SOFT_ERROR_Buffer;
HARD_ERROR <= HARD_ERROR_Buffer;
-- Main Body of Code --
-- Detect Soft Errors
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
if (ENABLE_ERROR_DETECT = '1') then
soft_error_r(0) <= RX_DISP_ERR(1) or RX_NOT_IN_TABLE(1) after DLY;
soft_error_r(1) <= RX_DISP_ERR(0) or RX_NOT_IN_TABLE(0) after DLY;
else
soft_error_r(0) <= '0' after DLY;
soft_error_r(1) <= '0' after DLY;
end if;
end if;
end process;
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
soft_error_flop_r <= soft_error_r(0) or
soft_error_r(1) after DLY;
SOFT_ERROR_Buffer <= soft_error_flop_r after DLY;
end if;
end process;
-- Detect Hard Errors
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
if (ENABLE_ERROR_DETECT = '1') then
hard_error_flop_r <= std_bool(TX_K_ERR /= "00") or
RX_BUF_STATUS or
TX_BUF_ERR or
RX_REALIGN or
bucket_full_r after DLY;
HARD_ERROR_Buffer <= hard_error_flop_r after DLY;
else
hard_error_flop_r <= '0' after DLY;
HARD_ERROR_Buffer <= '0' after DLY;
end if;
end if;
end process;
-- Assert hard error reset when there is a hard error. This assignment
-- just renames the two fanout branches of the hard error signal.
HARD_ERROR_RESET_Buffer <= hard_error_flop_r;
-- Leaky Bucket --
-- Good cycle counter: it takes 2 consecutive good cycles to remove a demerit from
-- the leaky bucket
process (USER_CLK)
variable err_vec : std_logic_vector(3 downto 0);
begin
if (USER_CLK 'event and USER_CLK = '1') then
if (ENABLE_ERROR_DETECT = '0') then
good_count_r <= "01" after DLY;
else
err_vec := soft_error_r & good_count_r;
case err_vec is
when "0000" => good_count_r <= "01" after DLY;
when "0001" => good_count_r <= "10" after DLY;
when "0010" => good_count_r <= "01" after DLY;
when "0011" => good_count_r <= "01" after DLY;
when others => good_count_r <= "00" after DLY;
end case;
end if;
end if;
end process;
-- Perform the leaky bucket algorithm using an up/down counter. A drop is
-- added to the bucket whenever a soft error occurs and is allowed to leak
-- out whenever the good cycles counter reaches 2. Once the bucket fills
-- (3 drops) it stays full until it is reset by disabling and then enabling
-- the error detection circuit.
process (USER_CLK)
variable leaky_bucket : std_logic_vector(4 downto 0);
begin
if (USER_CLK 'event and USER_CLK = '1') then
if (ENABLE_ERROR_DETECT = '0') then
count_r <= "00" after DLY;
else
leaky_bucket := soft_error_r & good_count_r(0) & count_r;
case leaky_bucket is
when "00000" => count_r <= count_r after DLY;
when "00001" => count_r <= count_r after DLY;
when "00010" => count_r <= count_r after DLY;
when "00011" => count_r <= count_r after DLY;
when "00100" => count_r <= "00" after DLY;
when "00101" => count_r <= "00" after DLY;
when "00110" => count_r <= "01" after DLY;
when "00111" => count_r <= "11" after DLY;
when "01000" => count_r <= "01" after DLY;
when "01001" => count_r <= "10" after DLY;
when "01010" => count_r <= "11" after DLY;
when "01011" => count_r <= "11" after DLY;
when "01100" => count_r <= "01" after DLY;
when "01101" => count_r <= "10" after DLY;
when "01110" => count_r <= "11" after DLY;
when "01111" => count_r <= "11" after DLY;
when "10000" => count_r <= "01" after DLY;
when "10001" => count_r <= "10" after DLY;
when "10010" => count_r <= "11" after DLY;
when "10011" => count_r <= "11" after DLY;
when "10100" => count_r <= "01" after DLY;
when "10101" => count_r <= "10" after DLY;
when "10110" => count_r <= "11" after DLY;
when "10111" => count_r <= "11" after DLY;
when "11000" => count_r <= "10" after DLY;
when "11001" => count_r <= "11" after DLY;
when "11010" => count_r <= "11" after DLY;
when "11011" => count_r <= "11" after DLY;
when "11100" => count_r <= "10" after DLY;
when "11101" => count_r <= "11" after DLY;
when "11110" => count_r <= "11" after DLY;
when "11111" => count_r <= "11" after DLY;
when others => count_r <= "XX" after DLY;
end case;
end if;
end if;
end process;
-- Detect when the bucket is full and register the signal.
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
bucket_full_r <= std_bool(count_r = "11") after DLY;
end if;
end process;
end RTL;
|
bsd-2-clause
|
timvideos/HDMI2USB-jahanzeb-firmware
|
ipcore_dir/edidram/example_design/edidram_exdes.vhd
|
3
|
4962
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: edidram_exdes.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY edidram_exdes IS
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Inputs - Port B
ADDRB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END edidram_exdes;
ARCHITECTURE xilinx OF edidram_exdes IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT edidram IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Port B
ADDRB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bufg_B : BUFG
PORT MAP (
I => CLKB,
O => CLKB_buf
);
bmg0 : edidram
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
CLKA => CLKA_buf,
--Port B
ADDRB => ADDRB,
DOUTB => DOUTB,
CLKB => CLKB_buf
);
END xilinx;
|
bsd-2-clause
|
timvideos/HDMI2USB-jahanzeb-firmware
|
hdl/jpeg_encoder/design/SingleSM.vhd
|
5
|
5666
|
-------------------------------------------------------------------------------
-- File Name : SingleSM.vhd
--
-- Project :
--
-- Module :
--
-- Content :
--
-- Description :
--
-- Spec. :
--
-- Author : Michal Krepa
-------------------------------------------------------------------------------
-- History :
-- 20080301: (MK): Initial Creation.
-------------------------------------------------------------------------------
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- /// Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
library ieee;
use ieee.std_logic_1164.all;
entity SingleSM is
port
(
CLK : in std_logic;
RST : in std_logic;
-- from/to SM(m)
start_i : in std_logic;
idle_o : out std_logic;
-- from/to SM(m+1)
idle_i : in std_logic;
start_o : out std_logic;
-- from/to processing block
pb_rdy_i : in std_logic;
pb_start_o : out std_logic;
-- state debug
fsm_o : out std_logic_vector(1 downto 0)
);
end entity SingleSM;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ARCHITECTURE ------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture SingleSM_rtl of SingleSM is
-------------------------------------------------------------------------------
-- Architecture: Signal definition.
-------------------------------------------------------------------------------
type T_STATE is (IDLE, WAIT_FOR_BLK_RDY, WAIT_FOR_BLK_IDLE);
signal state : T_STATE;
-------------------------------------------------------------------------------
-- Architecture: begin
-------------------------------------------------------------------------------
begin
fsm_o <= "00" when state = IDLE else
"01" when state = WAIT_FOR_BLK_RDY else
"10" when state = WAIT_FOR_BLK_IDLE else
"11";
------------------------------------------------------------------------------
-- FSM
------------------------------------------------------------------------------
p_fsm : process(CLK, RST)
begin
if RST = '1' then
idle_o <= '0';
start_o <= '0';
pb_start_o <= '0';
state <= IDLE;
elsif CLK'event and CLK = '1' then
idle_o <= '0';
start_o <= '0';
pb_start_o <= '0';
case state is
when IDLE =>
idle_o <= '1';
-- this fsm is started
if start_i = '1' then
state <= WAIT_FOR_BLK_RDY;
-- start processing block associated with this FSM
pb_start_o <= '1';
idle_o <= '0';
end if;
when WAIT_FOR_BLK_RDY =>
-- wait until processing block completes
if pb_rdy_i = '1' then
-- wait until next FSM is idle before starting it
if idle_i = '1' then
state <= IDLE;
start_o <= '1';
else
state <= WAIT_FOR_BLK_IDLE;
end if;
end if;
when WAIT_FOR_BLK_IDLE =>
if idle_i = '1' then
state <= IDLE;
start_o <= '1';
end if;
when others =>
idle_o <= '0';
start_o <= '0';
pb_start_o <= '0';
state <= IDLE;
end case;
end if;
end process;
end architecture SingleSM_rtl;
-------------------------------------------------------------------------------
-- Architecture: end
-------------------------------------------------------------------------------
|
bsd-2-clause
|
mbrobbel/capi-streaming-framework
|
accelerator/rtl/afu.vhd
|
1
|
6048
|
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.psl.all;
use work.functions.all;
use work.frame_package.all;
entity afu is
port (
ah_cvalid : out std_logic;
ah_ctag : out std_logic_vector(PSL_TAG_WIDTH - 1 downto 0);
ah_ctagpar : out std_logic;
ah_com : out std_logic_vector(PSL_COMMAND_WIDTH - 1 downto 0);
ah_compar : out std_logic;
ah_cabt : out std_logic_vector(PSL_ABT_WIDTH - 1 downto 0);
ah_cea : out std_logic_vector(PSL_ADDRESS_WIDTH - 1 downto 0);
ah_ceapar : out std_logic;
ah_cch : out std_logic_vector(PSL_CH_WIDTH - 1 downto 0);
ah_csize : out std_logic_vector(PSL_SIZE_WIDTH - 1 downto 0);
ha_croom : in std_logic_vector(PSL_ROOM_WIDTH - 1 downto 0);
ha_brvalid : in std_logic;
ha_brtag : in std_logic_vector(PSL_TAG_WIDTH - 1 downto 0);
ha_brtagpar : in std_logic;
ha_brad : in std_logic_vector(PSL_HALFLINE_INDEX_WIDTH - 1 downto 0);
ah_brlat : out std_logic_vector(PSL_LATENCY_WIDTH - 1 downto 0);
ah_brdata : out std_logic_vector(PSL_DATA_WIDTH - 1 downto 0);
ah_brpar : out std_logic_vector((PSL_DATA_WIDTH - 1) / PSL_DOUBLE_WORD_WIDTH downto 0);
ha_bwvalid : in std_logic;
ha_bwtag : in std_logic_vector(PSL_TAG_WIDTH - 1 downto 0);
ha_bwtagpar : in std_logic;
ha_bwad : in std_logic_vector(PSL_HALFLINE_INDEX_WIDTH - 1 downto 0);
ha_bwdata : in std_logic_vector(PSL_DATA_WIDTH - 1 downto 0);
ha_bwpar : in std_logic_vector((PSL_DATA_WIDTH - 1) / PSL_DOUBLE_WORD_WIDTH downto 0);
ha_rvalid : in std_logic;
ha_rtag : in std_logic_vector(PSL_TAG_WIDTH - 1 downto 0);
ha_rtagpar : in std_logic;
ha_response : in std_logic_vector(PSL_RESPONSE_WIDTH - 1 downto 0);
ha_rcredits : in std_logic_vector(PSL_CREDITS_WIDTH - 1 downto 0);
ha_rcachestate : in std_logic_vector(PSL_CACHESTATE_WIDTH - 1 downto 0);
ha_rcachepos : in std_logic_vector(PSL_CACHEPOS_WIDTH - 1 downto 0);
ha_mmval : in std_logic;
ha_mmcfg : in std_logic;
ha_mmrnw : in std_logic;
ha_mmdw : in std_logic;
ha_mmad : in std_logic_vector(PSL_MMIO_ADDRESS_WIDTH - 1 downto 0);
ha_mmadpar : in std_logic;
ha_mmdata : in std_logic_vector(PSL_MMIO_DATA_WIDTH - 1 downto 0);
ha_mmdatapar : in std_logic;
ah_mmack : out std_logic;
ah_mmdata : out std_logic_vector(PSL_MMIO_DATA_WIDTH - 1 downto 0);
ah_mmdatapar : out std_logic;
ha_jval : in std_logic;
ha_jcom : in std_logic_vector(PSL_JOB_COMMAND_WIDTH - 1 downto 0);
ha_jcompar : in std_logic;
ha_jea : in std_logic_vector(PSL_ADDRESS_WIDTH - 1 downto 0);
ha_jeapar : in std_logic;
ah_jrunning : out std_logic;
ah_jdone : out std_logic;
ah_jcack : out std_logic;
ah_jerror : out std_logic_vector(PSL_ERROR_WIDTH - 1 downto 0);
ah_jyield : out std_logic;
ah_tbreq : out std_logic;
ah_paren : out std_logic;
ha_pclock : in std_logic
);
end entity afu;
architecture logic of afu is
signal ha : frame_in;
signal ah : frame_out;
begin
----------------------------------------------------------------------------------------------------------------------- inputs
--ha.c.room <= ha_croom;
ha.b.rvalid <= ha_brvalid;
ha.b.rtag <= u(ha_brtag);
--ha.b.rtagpar <= ha_brtagpar;
ha.b.rad <= u(ha_brad);
ha.b.wvalid <= ha_bwvalid;
ha.b.wtag <= u(ha_bwtag);
--ha.b.wtagpar <= ha_bwtagpar;
ha.b.wad <= u(ha_bwad);
ha.b.wdata <= ha_bwdata;
--ha.b.wpar <= ha_bwpar;
ha.r.valid <= ha_rvalid;
ha.r.tag <= u(ha_rtag);
--ha.r.tagpar <= ha_rtagpar;
ha.r.response <= ha_response;
--ha.r.credits <= ha_rcredits;
--ha.r.cachestate <= ha_rcachestate;
--ha.r.cachepos <= ha_rcachepos;
ha.mm.val <= ha_mmval;
ha.mm.cfg <= ha_mmcfg;
ha.mm.rnw <= ha_mmrnw;
ha.mm.dw <= ha_mmdw;
ha.mm.ad <= u(ha_mmad);
--ha.mm.adpar <= ha_mmadpar;
ha.mm.data <= ha_mmdata;
--ha.mm.datapar <= ha_mmdatapar;
ha.j.com <= ha_jcom;
ha.j.val <= ha_jval;
--ha.j.compar <= ha_jcompar;
ha.j.ea <= u(ha_jea);
--ha.j.eapar <= ha_jeapar;
ha.j.pclock <= ha_pclock;
----------------------------------------------------------------------------------------------------------------------- outputs
ah_cvalid <= ah.c.valid;
ah_ctag <= slv(ah.c.tag);
ah_ctagpar <= '0'; --ah.c.tagpar;
ah_com <= ah.c.com;
ah_compar <= '0'; --ah.c.compar;
ah_cabt <= PTOB_PAGE; --ah.c.abt;
ah_cea <= slv(ah.c.ea);
ah_ceapar <= '0'; --ah.c.eapar;
ah_cch <= (others => '0'); --ah.c.ch;
ah_csize <= slv(ah.c.size);
ah_brlat <= slv(1, PSL_LATENCY_WIDTH); --ah.b.rlat;
ah_brdata <= ah.b.rdata;
ah_brpar <= (others => '0'); --ah.b.rpar;
ah_mmack <= ah.mm.ack;
ah_mmdata <= ah.mm.data;
ah_mmdatapar <= '0'; --ah.mm.datapar;
ah_jrunning <= ah.j.running;
ah_jdone <= ah.j.done;
ah_jcack <= '0'; --ah.j.ack;
ah_jerror <= (others => '0'); --ah.j.error;
ah_jyield <= '0'; --ah.j.yield;
ah_tbreq <= '0'; --ah.j.tbreq;
ah_paren <= '0'; --ah.j.paren;
f0 : entity work.frame port map (ha, ah);
end architecture logic;
|
bsd-2-clause
|
mbrobbel/capi-streaming-framework
|
accelerator/rtl/dma.vhd
|
1
|
23418
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.functions.all;
use work.psl.all;
use work.dma_package.all;
entity dma is
port (
i : in dma_in;
o : out dma_out
);
end entity dma;
architecture logic of dma is
signal q, r : dma_int;
signal re : dma_ext;
alias write : std_logic is i.r.tag(PSL_TAG_WIDTH - 1);
alias tag : unsigned(DMA_TAG_WIDTH - 1 downto 0) is i.r.tag(DMA_TAG_WIDTH - 1 downto 0);
begin
comb : process(all)
variable v : dma_int;
begin
----------------------------------------------------------------------------------------------------------------------- default assignments
v := r;
v.read := '0';
v.read_touch := '0';
v.write := '0';
v.write_touch := '0';
v.o.dc.read.valid := '0';
v.o.dc.write.valid := '0';
v.id := r.id + u(i.cd.read.valid or i.cd.write.request.valid);
v.read_credits := r.read_credits + u(i.r.valid and not(write));
v.write_credits := r.write_credits + u(i.r.valid and write);
v.rt.available := not is_full(r.rt.tag, r.rb.pull_address);
v.wt.available := not is_full(r.wt.tag, r.wb.pull_address);
v.rse.engine(r.rse.pull_engine).touch.count := r.rse.engine(r.rse.pull_engine).touch.count + u(r.read and not(r.read_touch));
v.wse.engine(r.wse.pull_engine).touch.count := r.wse.engine(r.wse.pull_engine).touch.count + u(r.write and not(r.write_touch));
if i.b.rad(0) then
v.o.b.rdata := re.wb.data(1023 downto 512);
else
v.o.b.rdata := re.wb.data(511 downto 0);
end if;
----------------------------------------------------------------------------------------------------------------------- select read/write
if l(r.rse.active_count > 0 and r.wse.active_count > 0 and v.read_credits > 0 and v.write_credits > 0) and v.rt.available and v.wt.available then
v.read := not(DMA_WRITE_PRIORITY);
v.write := DMA_WRITE_PRIORITY;
elsif v.rt.available and l(r.rse.active_count > 0 and v.read_credits > 0) then
v.read := '1';
elsif v.wt.available and l(r.wse.active_count > 0 and v.write_credits > 0) then
v.write := '1';
end if;
if v.read then
v.o.c.tag := "0" & r.rt.tag(DMA_TAG_WIDTH - 1 downto 0);
else
v.o.c.tag := "1" & r.wt.tag(DMA_TAG_WIDTH - 1 downto 0);
end if;
v.o.c.valid := v.read or v.write;
v.read_credits := v.read_credits - u(v.read);
v.write_credits := v.write_credits - u(v.write);
v.rt.tag := r.rt.tag + u(v.read);
v.wt.tag := r.wt.tag + u(v.write);
----------------------------------------------------------------------------------------------------------------------- move requests to stream engines
for stream in 0 to DMA_READ_ENGINES - 1 loop
if not(re.rq(stream).empty) and r.rse.free(stream) then
v.rse.free(stream) := '0';
v.rse.ready(stream) := '1';
v.rse.engine(stream).hold := (others => '0');
v.rse.engine(stream).touch.touch := '0';
v.rse.engine(stream).touch.count := (others => '0');
v.rse.engine(stream).touch.address := re.rq(stream).request.address + PSL_PAGESIZE;
v.rse.engine(stream).request := re.rq(stream).request;
end if;
end loop;
for stream in 0 to DMA_WRITE_ENGINES - 1 loop
if not(re.wq(stream).empty) and r.wse.free(stream) then
v.wse.free(stream) := '0';
v.wse.ready(stream) := '1';
v.wse.engine(stream).hold := (others => '0');
v.wse.engine(stream).touch.touch := '0';
v.wse.engine(stream).touch.count := (others => '0');
v.wse.engine(stream).touch.address := re.wq(stream).request.address + PSL_PAGESIZE;
v.wse.engine(stream).request := re.wq(stream).request;
end if;
end loop;
----------------------------------------------------------------------------------------------------------------------- select stream engine
for stream in 0 to DMA_READ_ENGINES - 1 loop
if r.rse.ready(stream) and not(r.rse.free(stream)) then
v.rse.pull_engine := stream;
end if;
end loop;
v.rse.pull_stream := (others => '0');
v.rse.pull_stream(v.rse.pull_engine) := '1';
for stream in 0 to DMA_WRITE_ENGINES - 1 loop
if r.wse.ready(stream) and not(r.wse.free(stream)) and not(re.wqb(stream).empty) then
v.wse.pull_engine := stream;
end if;
end loop;
v.wse.pull_stream := (others => '0');
v.wse.pull_stream(v.wse.pull_engine) := '1';
v.wqb(v.wse.pull_engine) := v.wqb(v.wse.pull_engine) - u(v.write and not(v.write_touch));
----------------------------------------------------------------------------------------------------------------------- generate commands
if v.read then
if DMA_READ_TOUCH and l(r.rse.engine(v.rse.pull_engine).touch.count = DMA_TOUCH_COUNT and r.rse.engine(v.rse.pull_engine).request.size + DMA_TOUCH_COUNT > PSL_PAGESIZE)
and not(r.rse.engine(v.rse.pull_engine).touch.touch)
then
v.o.c.com := PCO_TOUCH_I;
v.o.c.ea := r.rse.engine(v.rse.pull_engine).touch.address;
v.read_touch := '1';
v.rse.engine(v.rse.pull_engine).touch.touch := '1';
v.rse.engine(v.rse.pull_engine).touch.address := r.rse.engine(v.rse.pull_engine).touch.address + PSL_PAGESIZE;
else
v.read_touch := '0';
v.rse.engine(v.rse.pull_engine).touch.touch := '0';
v.o.c.ea := r.rse.engine(v.rse.pull_engine).request.address;
if r.rse.engine(v.rse.pull_engine).request.size < PSL_CACHELINE_BYTES then
v.o.c.size := r.rse.engine(v.rse.pull_engine).request.size(PSL_SIZE_WIDTH - 1 downto 0);
v.o.c.com := PCO_READ_PNA;
else
v.o.c.size := PSL_CACHELINE_BYTES_OUT;
v.o.c.com := PCO_READ_CL_NA;
end if;
v.rse.free(v.rse.pull_engine) := l(r.rse.engine(v.rse.pull_engine).request.size <= PSL_CACHELINE_BYTES);
v.rse.active_count := v.rse.active_count - u(l(r.rse.engine(v.rse.pull_engine).request.size <= PSL_CACHELINE_BYTES));
v.rse.engine(v.rse.pull_engine).request.size := r.rse.engine(v.rse.pull_engine).request.size - PSL_CACHELINE_BYTES;
v.rse.engine(v.rse.pull_engine).request.address := r.rse.engine(v.rse.pull_engine).request.address + PSL_CACHELINE_BYTES;
v.rse.ready(v.rse.pull_engine) := not(v.rse.free(v.rse.pull_engine) or l(r.rse.active_count > 1));
end if;
end if;
if v.write then
if DMA_WRITE_TOUCH and l(r.wse.engine(v.wse.pull_engine).touch.count = DMA_TOUCH_COUNT and r.wse.engine(v.wse.pull_engine).request.size + DMA_TOUCH_COUNT > PSL_PAGESIZE)
and not(r.wse.engine(v.wse.pull_engine).touch.touch)
then
v.o.c.com := PCO_TOUCH_I;
v.o.c.ea := r.wse.engine(v.wse.pull_engine).touch.address;
v.write_touch := '1';
v.wse.engine(v.wse.pull_engine).touch.touch := '1';
v.wse.engine(v.wse.pull_engine).touch.address := r.wse.engine(v.wse.pull_engine).touch.address + PSL_PAGESIZE;
else
v.write_touch := '0';
v.wse.engine(v.wse.pull_engine).touch.touch := '0';
v.o.c.ea := r.wse.engine(v.wse.pull_engine).request.address;
v.o.c.com := PCO_WRITE_NA;
if r.wse.engine(v.wse.pull_engine).request.size <= PSL_CACHELINE_BYTES then
v.o.c.size := r.wse.engine(v.wse.pull_engine).request.size(PSL_SIZE_WIDTH - 1 downto 0);
v.wse.free(v.wse.pull_engine) := '1';
v.wse.active_count := v.wse.active_count - 1;
else
v.o.c.size := PSL_CACHELINE_BYTES_OUT;
end if;
v.wse.engine(v.wse.pull_engine).request.size := r.wse.engine(v.wse.pull_engine).request.size - PSL_CACHELINE_BYTES;
v.wse.engine(v.wse.pull_engine).request.address := r.wse.engine(v.wse.pull_engine).request.address + PSL_CACHELINE_BYTES;
v.wse.ready(v.wse.pull_engine) := not(v.wse.free(v.wse.pull_engine) or l(r.wse.active_count > 1));
end if;
end if;
v.rse.active_count := u(ones(not(v.rse.free)), v.rse.active_count'length);
v.wse.active_count := (others => '0');
for stream in 0 to DMA_WRITE_ENGINES - 1 loop
v.wqb(stream) := v.wqb(stream) + u(i.cd.write.data.valid and i.cd.write.data.stream(stream));
v.wse.active_count := v.wse.active_count + u(l(v.wqb(stream) > 0) and not(v.wse.free(stream)));
end loop;
for stream in 0 to DMA_READ_ENGINES - 1 loop
if not(v.rse.pull_stream(stream)) then
if not(v.rse.free(stream)) and not(v.rse.ready(stream)) then
v.rse.engine(stream).hold := r.rse.engine(stream).hold + u(v.read and not(v.rse.free(stream)));
if v.rse.engine(stream).hold >= v.rse.active_count - 1 then
v.rse.ready(stream) := '1';
v.rse.engine(stream).hold := (others => '0');
end if;
end if;
end if;
end loop;
for stream in 0 to DMA_WRITE_ENGINES - 1 loop
if stream /= v.wse.pull_engine then
if not(v.wse.free(stream)) and not(v.wse.ready(stream)) then
v.wse.engine(stream).hold := r.wse.engine(stream).hold + u(v.write);
if v.wse.engine(stream).hold >= v.wse.active_count - 1 then
v.wse.ready(stream) := '1';
v.wse.engine(stream).hold := (others => '0');
end if;
end if;
end if;
end loop;
--------------------------------------------------------------------------------------------------------------------- handle responses
if i.r.valid and not(write) and
l((i.r.tag < r.rb.pull_address(DMA_TAG_WIDTH - 1 downto 0) and r.rb.put_flip = r.rb.pull_flip) or
(i.r.tag >= r.rb.pull_address(DMA_TAG_WIDTH - 1 downto 0) and r.rb.put_flip /= r.rb.pull_flip))
then
v.rb.put_flip := not r.rb.put_flip;
end if;
if i.r.valid and write and
l((tag < r.wb.pull_address(DMA_TAG_WIDTH - 1 downto 0) and r.wb.put_flip = r.wb.pull_flip) or
(tag >= r.wb.pull_address(DMA_TAG_WIDTH - 1 downto 0) and r.wb.put_flip /= r.wb.pull_flip))
then
v.wb.put_flip := not r.wb.put_flip;
end if;
if i.r.valid then
if write then
v.wb.status(idx(tag)) := v.wb.put_flip;
else
v.rb.status(idx(tag)) := v.rb.put_flip;
end if;
end if;
if r.rb.status(idx(r.rb.pull_address(DMA_TAG_WIDTH - 1 downto 0))) = r.rb.pull_flip then
v.o.dc.read.valid := not re.rh.touch;
v.rb.pull_address := r.rb.pull_address + 1;
if r.rb.pull_address(DMA_TAG_WIDTH - 1 downto 0) = (DMA_TAG_WIDTH - 1 downto 0 => '1') then
v.rb.pull_flip := not r.rb.pull_flip;
end if;
elsif r.wb.status(idx(r.wb.pull_address(DMA_TAG_WIDTH - 1 downto 0))) = r.wb.pull_flip then
v.o.dc.write.valid := not re.wh.touch;
v.wb.pull_address := r.wb.pull_address + 1;
if r.wb.pull_address(DMA_TAG_WIDTH - 1 downto 0) = (DMA_TAG_WIDTH - 1 downto 0 => '1') then
v.wb.pull_flip := not r.wb.pull_flip;
end if;
end if;
----------------------------------------------------------------------------------------------------------------------- outputs
q <= v;
o <= r.o;
o.dc.id <= q.id;
o.dc.read.id <= re.rh.id;
o.dc.read.stream <= slv(re.rh.stream);
o.dc.read.data <= re.rb.data1 & re.rb.data0;
for stream in 0 to DMA_READ_ENGINES - 1 loop
o.dc.read.full(stream) <= re.rq(stream).full;
end loop;
o.dc.write.id <= re.wh.id;
o.dc.write.stream <= slv(re.wh.stream);
for stream in 0 to DMA_WRITE_ENGINES - 1 loop
o.dc.write.full(stream) <= re.wq(stream).full or l(r.wqb(stream) >= (2**DMA_WRITE_QUEUE_DEPTH - 4));
end loop;
end process comb;
----------------------------------------------------------------------------------------------------------------------- read queues
rqs : for stream in 0 to DMA_READ_ENGINES - 1 generate
rq : entity work.fifo_unsigned generic map (DMA_ID_WIDTH + PSL_ADDRESS_WIDTH + DMA_SIZE_WIDTH, DMA_WRITE_QUEUE_DEPTH, '1', 1)
port map (
cr => i.cr,
put => i.cd.read.valid and i.cd.read.stream(stream),
data_in => r.id & i.cd.read.address & i.cd.read.size,
pull => not(re.rq(stream).empty) and r.rse.free(stream),
data_out => re.rq(stream).data,
empty => re.rq(stream).empty,
full => re.rq(stream).full
);
re.rq(stream).request.id <= re.rq(stream).data(DMA_ID_WIDTH + PSL_ADDRESS_WIDTH + DMA_SIZE_WIDTH - 1 downto PSL_ADDRESS_WIDTH + DMA_SIZE_WIDTH);
re.rq(stream).request.address <= re.rq(stream).data(PSL_ADDRESS_WIDTH + DMA_SIZE_WIDTH - 1 downto DMA_SIZE_WIDTH);
re.rq(stream).request.size <= re.rq(stream).data(DMA_SIZE_WIDTH - 1 downto 0);
end generate rqs;
----------------------------------------------------------------------------------------------------------------------- write queues + buffers
wqs : for stream in 0 to DMA_WRITE_ENGINES - 1 generate
wq : entity work.fifo_unsigned generic map (DMA_ID_WIDTH + PSL_ADDRESS_WIDTH + DMA_SIZE_WIDTH, DMA_WRITE_QUEUE_DEPTH, '1', 1)
port map (
cr => i.cr,
put => i.cd.write.request.valid and i.cd.write.request.stream(stream),
data_in => r.id & i.cd.write.request.address & i.cd.write.request.size,
pull => not(re.wq(stream).empty) and r.wse.free(stream),
data_out => re.wq(stream).data,
empty => re.wq(stream).empty,
full => re.wq(stream).full
);
re.wq(stream).request.id <= re.wq(stream).data(DMA_ID_WIDTH + PSL_ADDRESS_WIDTH + DMA_SIZE_WIDTH - 1 downto PSL_ADDRESS_WIDTH + DMA_SIZE_WIDTH);
re.wq(stream).request.address <= re.wq(stream).data(PSL_ADDRESS_WIDTH + DMA_SIZE_WIDTH - 1 downto DMA_SIZE_WIDTH);
re.wq(stream).request.size <= re.wq(stream).data(DMA_SIZE_WIDTH - 1 downto 0);
wqb : entity work.fifo generic map (DMA_DATA_WIDTH, DMA_WRITE_BUFFER_DEPTH, '0', 1)
port map (
cr => i.cr,
put => i.cd.write.data.valid and i.cd.write.data.stream(stream),
data_in => endian_swap(i.cd.write.data.data),
pull => r.write and not(r.write_touch) and r.wse.pull_stream(stream),
data_out => re.wqb(stream).data,
empty => re.wqb(stream).empty,
full => re.wqb(stream).full
);
end generate wqs;
----------------------------------------------------------------------------------------------------------------------- write buffer
wb : entity work.ram_dual generic map (DMA_DATA_WIDTH, DMA_TAG_WIDTH, '0')
port map (
clk => i.cr.clk,
put => r.write,
write_address => r.o.c.tag(DMA_TAG_WIDTH - 1 downto 0),
data_in => re.wqb(r.wse.pull_engine).data,
read_address => i.b.rtag(DMA_TAG_WIDTH - 1 downto 0),
data_out => re.wb.data
);
----------------------------------------------------------------------------------------------------------------------- read buffer
rb0 : entity work.ram_dual generic map (PSL_DATA_WIDTH, DMA_TAG_WIDTH, '0')
port map (
clk => i.cr.clk,
put => i.b.wvalid and not(i.b.wad(0)),
write_address => i.b.wtag(DMA_TAG_WIDTH - 1 downto 0),
data_in => endian_swap(i.b.wdata),
read_address => r.rb.pull_address(DMA_TAG_WIDTH - 1 downto 0),
data_out => re.rb.data0
);
rb1 : entity work.ram_dual generic map (PSL_DATA_WIDTH, DMA_TAG_WIDTH, '0')
port map (
clk => i.cr.clk,
put => i.b.wvalid and i.b.wad(0),
write_address => i.b.wtag(DMA_TAG_WIDTH - 1 downto 0),
data_in => endian_swap(i.b.wdata),
read_address => r.rb.pull_address(DMA_TAG_WIDTH - 1 downto 0),
data_out => re.rb.data1
);
----------------------------------------------------------------------------------------------------------------------- command history
rh : entity work.ram_dual_unsigned generic map (DMA_ID_WIDTH + DMA_READ_ENGINES + 1, DMA_TAG_WIDTH, '0')
port map (
clk => i.cr.clk,
put => r.read,
write_address => r.o.c.tag(DMA_TAG_WIDTH - 1 downto 0),
data_in => r.rse.engine(r.rse.pull_engine).request.id & u(r.rse.pull_stream) & r.rse.engine(r.rse.pull_engine).touch.touch,
read_address => r.rb.pull_address(DMA_TAG_WIDTH - 1 downto 0),
data_out => re.rh.data
);
re.rh.id <= re.rh.data(DMA_ID_WIDTH + DMA_READ_ENGINES downto DMA_READ_ENGINES + 1);
re.rh.stream <= re.rh.data(DMA_READ_ENGINES downto 1);
re.rh.touch <= re.rh.data(0);
wh : entity work.ram_dual_unsigned generic map (DMA_ID_WIDTH + DMA_WRITE_ENGINES + 1, DMA_TAG_WIDTH, '0')
port map (
clk => i.cr.clk,
put => r.write,
write_address => r.o.c.tag(DMA_TAG_WIDTH - 1 downto 0),
data_in => r.wse.engine(r.wse.pull_engine).request.id & u(r.wse.pull_stream) & r.wse.engine(r.wse.pull_engine).touch.touch,
read_address => r.wb.pull_address(DMA_TAG_WIDTH - 1 downto 0),
data_out => re.wh.data
);
re.wh.id <= re.wh.data(DMA_ID_WIDTH + DMA_WRITE_ENGINES downto DMA_WRITE_ENGINES + 1);
re.wh.stream <= re.wh.data(DMA_WRITE_ENGINES downto 1);
re.wh.touch <= re.wh.data(0);
----------------------------------------------------------------------------------------------------------------------- reset & registers
reg : process(i.cr)
begin
if rising_edge(i.cr.clk) then
if i.cr.rst then
dma_reset(r);
else
r <= q;
end if;
end if;
end process;
end architecture logic;
|
bsd-2-clause
|
dpolad/dlx
|
DLX_vhd/a.i.a.d.c.c-G.vhd
|
2
|
271
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity g is
Port ( g: In std_logic;
p: In std_logic;
g_prec: In std_logic;
g_out: Out std_logic);
end g;
architecture beh of g is
begin
g_out <= g OR (p AND g_prec);
end beh;
|
bsd-2-clause
|
dpolad/dlx
|
DLX_synth/005-MUX41.vhd
|
2
|
782
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.myTypes.all;
entity mux41 is
generic (
MUX_SIZE : integer := 32
);
port (
IN0 : in std_logic_vector(MUX_SIZE - 1 downto 0);
IN1 : in std_logic_vector(MUX_SIZE - 1 downto 0);
IN2 : in std_logic_vector(MUX_SIZE - 1 downto 0);
IN3 : in std_logic_vector(MUX_SIZE - 1 downto 0);
CTRL : in std_logic_vector(1 downto 0);
OUT1 : out std_logic_vector(MUX_SIZE - 1 downto 0)
);
end mux41;
architecture bhe of mux41 is
begin
process ( CTRL, IN0, IN1, IN2, IN3)
begin
case CTRL is
when "00" => OUT1 <= IN0;
when "01" => OUT1 <= IN1;
when "10" => OUT1 <= IN2;
when "11" => OUT1 <= IN3;
when others => OUT1 <= (others => 'X'); -- should never appear
end case;
end process;
end bhe;
|
bsd-2-clause
|
dpolad/dlx
|
DLX_vhd/useless/fake_mult.vhd
|
1
|
1064
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity fake_mult is
generic (
DATA_SIZE : integer := 32);
port (
IN1 : in std_logic_vector(DATA_SIZE - 1 downto 0);
IN2 : in std_logic_vector(DATA_SIZE - 1 downto 0);
DOUT : out std_logic_vector(DATA_SIZE - 1 downto 0);
stall_o : out std_logic;
enable : in std_logic;
Clock : in std_logic;
Reset : in std_logic
);
end fake_mult;
architecture Bhe of fake_mult is
signal count : unsigned(2 downto 0);
begin
process(enable,Reset,Clock)
begin
if Reset = '1' then
DOUT <= X"00000000";
stall_o <= '0';
count <= "000";
else
if enable = '1' and enable'event then
stall_o <= '1';
count <= "111";
DOUT <= "00000000000000000000000000001000";
end if;
if enable = '1' and Clock = '1' and clock'event then
DOUT <= "00000000000000000000000000000"&std_logic_vector(count);
if count/="000" then
count <= count-1;
end if;
if count = "000" then
stall_o <= '0';
DOUT <= X"11111111";
end if;
end if;
end if;
end process;
end Bhe;
|
bsd-2-clause
|
dpolad/dlx
|
DLX_vhd/a.f.b-EXTENDER32.vhd
|
2
|
890
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--use work.myTypes.all;
entity extender_32 is
generic (
SIZE : integer := 32
);
port (
IN1 : in std_logic_vector(SIZE - 1 downto 0);
CTRL : in std_logic; -- when 0 extend on 16 bits , when 1 extend on 26 bits
SIGN : in std_logic; -- when 0 unsigned, when 1 signed
OUT1 : out std_logic_vector(SIZE - 1 downto 0)
);
end extender_32;
architecture Bhe of extender_32 is
signal TEMP16 : std_logic_vector(15 downto 0);
signal TEMP26 : std_logic_vector(25 downto 0);
begin
TEMP16 <= IN1(15 downto 0);
TEMP26 <= IN1(25 downto 0);
OUT1 <= std_logic_vector(resize(signed(TEMP26),SIZE)) when CTRL = '1' else
std_logic_vector(resize(signed(TEMP16),SIZE)) when CTRL = '0' and SIGN = '1' else
std_logic_vector(resize(unsigned(TEMP16),SIZE)); -- CTRL = 0 SIGN = 0
end Bhe;
|
bsd-2-clause
|
dpolad/dlx
|
DLX_synth/003-FF32_EN_IR.vhd
|
2
|
597
|
library ieee;
use ieee. std_logic_1164.all;
use ieee. std_logic_arith.all;
use ieee. std_logic_unsigned.all;
entity ff32_en_IR is
generic (
SIZE : integer := 32
);
PORT(
D : in std_logic_vector(SIZE - 1 downto 0);
en : in std_logic;
clk : in std_logic;
rst : in std_logic;
Q : out std_logic_vector(SIZE - 1 downto 0)
);
end ff32_en_IR;
architecture behavioral of ff32_en_IR is
begin
process(clk,rst)
begin
if(rst='1') then
Q <= X"54000000";
else
if(clk='1' and clk'EVENT) then
if en = '1' then
Q <= D;
end if;
end if;
end if;
end process;
end behavioral;
|
bsd-2-clause
|
dpolad/dlx
|
DLX_vhd/a.i.a.b.b-T2LEVEL2.vhd
|
2
|
690
|
library ieee;
use ieee.std_logic_1164.all;
use work.myTypes.all;
--00 mask00
--01 mask08
--10 mask16
entity shift_secondLevel is
port(sel : in std_logic_vector(1 downto 0);
mask00 : in std_logic_vector(38 downto 0);
mask08 : in std_logic_vector(38 downto 0);
mask16 : in std_logic_vector(38 downto 0);
Y : out std_logic_vector(38 downto 0));
end shift_secondLevel;
architecture behav of shift_secondLevel is
begin
process(sel, mask00, mask08, mask16)
begin
case sel is
when "00" =>
Y <= mask00;
when "01" =>
Y <= mask08;
when "10" =>
Y <= mask16;
when others => Y <= x"000000000" & "000";
end case;
end process;
end behav;
|
bsd-2-clause
|
dpolad/dlx
|
DLX_vhd/a.c.a-2BITPREDICTOR.vhd
|
2
|
1943
|
-- *** 2_bit_predictor.vhd *** --
-- this block is a simple 2 bit predictor.
-- it implements the canonical FSM for 2 bit preditcors
-- look at the scheme on Hennessy Patterson 5th Ed., figure C-18
-- this needs to be implemented for each line of the BTB cache
-- Future improvements: integrate this into the BTB in order to instatiate only one
library ieee;
use ieee.std_logic_1164.all;
entity predictor_2 is
port (
clock : in std_logic;
reset : in std_logic;
enable : in std_logic; -- if 1 FSM advances, 0 is frozen
taken_i : in std_logic; -- input bit -> 1 taken, 0 not taken
prediction_o : out std_logic -- output but -> 1 taken, 0 not taken
);
end predictor_2;
architecture bhe of predictor_2 is
-- state is on 2 bits
-- 00 strong NT
-- 01 weak NT
-- 10 weak T
-- 11 strong T
signal STATE : std_logic_vector(1 downto 0);
signal next_STATE : std_logic_vector(1 downto 0);
begin
-- output of the circuit is the MSB of the state
prediction_o <= STATE(1);
-- sequential process for state update
process(clock,reset)
begin
if reset='1' then
STATE <= "00";
elsif clock = '1' and clock'event and enable = '1' then
STATE <= next_STATE;
end if;
end process;
-- combinatorial process for next_STATE computation
-- Future improvements : do this by hand
process(taken_i, enable)
begin
if enable = '1' then
if taken_i = '1' then
case STATE is
when "00" => next_STATE <= "01";
when "01" => next_STATE <= "10";
when "10" => next_STATE <= "11";
when "11" => next_STATE <= "11";
when others => next_STATE <= "00"; -- might not be synthesizable
end case;
else
case STATE is
when "00" => next_STATE <= "00";
when "01" => next_STATE <= "00";
when "10" => next_STATE <= "01";
when "11" => next_STATE <= "10";
when others => next_STATE <= "00"; -- might not be synthesizable
end case;
end if;
end if;
end process;
end bhe;
|
bsd-2-clause
|
dpolad/dlx
|
DLX_vhd/useless/boothmul_pipelined.vhd
|
1
|
6860
|
library ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
ENTITY boothmul_pipelined IS
generic (N : integer := 8);
PORT(
Clock : in std_logic;
Reset : in std_logic;
sign : in std_logic;
A : IN std_logic_vector (N-1 downto 0);
B : IN std_logic_vector (N-1 downto 0);
P : OUT std_logic_vector (2*N-1 downto 0)
);
END boothmul_pipelined;
architecture BEHAVIOR of boothmul_pipelined is
component booth_encoder
PORT(
B_in : IN std_logic_vector (2 downto 0);
A_out : OUT std_logic_vector (2 downto 0)
);
end component;
component mux8to1_gen
generic ( M : integer := 64);
PORT(
A : IN std_logic_vector (M-1 downto 0);
B : IN std_logic_vector (M-1 downto 0);
C : IN std_logic_vector (M-1 downto 0);
D : IN std_logic_vector (M-1 downto 0);
E : IN std_logic_vector (M-1 downto 0);
F : IN std_logic_vector (M-1 downto 0);
G : IN std_logic_vector (M-1 downto 0);
H : IN std_logic_vector (M-1 downto 0);
S : IN std_logic_vector (2 downto 0);
Y : OUT std_logic_vector (M-1 downto 0)
);
end component;
component RCA
generic (M : integer := 64
);
Port ( A : In std_logic_vector(M-1 downto 0);
B : In std_logic_vector(M-1 downto 0);
S : Out std_logic_vector(M-1 downto 0)
);
end component;
signal b_enc : std_logic_vector(N downto 0);
signal last_enc : std_logic_vector(2 downto 0);
signal zeros : std_logic_vector(2*N-1 downto 0);
type mux_select is array (N/2 downto 0) of std_logic_vector(2 downto 0);
type mux_in is array (4 downto 0) of std_logic_vector (2*N-1 downto 0);
type tot_in is array (N/2 downto 0) of mux_in;
type tot_out is array (N/2 downto 0) of std_logic_vector (2*N-1 downto 0);
type tot_out_reg is array (N/2 downto 0) of tot_out;
type tot_sum is array (N/2 downto 0) of std_logic_vector (2*N-1 downto 0);
signal tot_mux_in : tot_in;
signal tot_mux_out : tot_out;
signal tot_mux_out_reg : tot_out_reg;
signal tot_select : mux_select;
signal mux_ini : mux_in;
signal mux_out0 : std_logic_vector (2*N-1 downto 0);
signal mux_outi : std_logic_vector (2*N-1 downto 0);
signal sum : tot_sum;
signal next_sum : tot_sum;
signal extend : std_logic;
signal Cin : std_logic;
signal Cout : std_logic;
type not_type is array (N/2 downto 0) of std_logic_vector ( 2*N-1 downto 0);
signal notmuxA : not_type;
signal notmux2A : not_type;
BEGIN
--TODO: add comments
b_enc <= B &'0';
zeros <= (others => '0');
extend <= sign;
last_enc <= sign&sign&B(N-1);
Cin <= '0';
P <= sum(N/2-1);
encod_loop: for i in 0 to N/2 generate
en_level0 : IF i = 0 generate
encod_0 : booth_encoder port map(b_enc(2 downto 0), tot_select(i));
end generate en_level0;
en_levelN : IF i = N/2 generate
encod_i : booth_encoder port map(last_enc, tot_select(i));
end generate en_levelN;
en_leveli : IF i > 0 and i < N/2 generate
encod_i : booth_encoder port map(B(2*i+1 downto 2*i-1), tot_select(i));
end generate en_leveli;
end generate encod_loop;
in_mu : for i in 0 to N/2 generate
mlevel_0 : IF i = 0 generate
tot_mux_in(i)(0) <= (others => '0' );
tot_mux_in(i)(1)(2*N-1 downto N) <= (others => ('0'OR A(N-1)) and extend); -- take sign of A (last bit and extend)
tot_mux_in(i)(1)(N-1 downto 0) <= A; --lowest 16 bits are A
--notmuxA is A flipped (twos complement)
notmuxA(i)(2*N-1 downto N) <= (others => ('0'OR A(N-1)) and extend);
notmuxA(i)(N-1 downto 0) <= A;
tot_mux_in(i)(2) <= std_logic_vector(signed(NOT(notmuxA(i))) + 1);
tot_mux_in(i)(3)(2*N-1 downto N+1) <= (others => ('0'OR A(N-1)) and extend);
tot_mux_in(i)(3)(N downto 1) <= A;
tot_mux_in(i)(3)(0 downto 0) <= (others => '0');
notmux2A(i)(2*N-1 downto N+1) <= (others => ('0'OR A(N-1)) and extend);
notmux2A(i)(N downto 1) <= A;
notmux2A(i)(0 downto 0) <= (others => '0');
tot_mux_in(i)(4) <= std_logic_vector(signed(NOT(notmux2A(i))) + 1);
end generate mlevel_0;
mlevel_N : IF i = N/2 generate
tot_mux_in(i)(0) <= (others => '0');
tot_mux_in(i)(1)(2*N-1 downto N+2*i) <= (others => ('0'OR A(N-1)) and extend);
tot_mux_in(i)(1)(N+2*i-1 downto 2*i) <= A;
tot_mux_in(i)(1)(2*i-1 downto 0) <= (others => '0');
end generate mlevel_N;
mlevel_i : IF i > 0 and i < N/2 generate
tot_mux_in(i)(0) <= (others => '0');
tot_mux_in(i)(1)(2*N-1 downto N+2*i) <= (others => ('0'OR A(N-1)) and extend);
tot_mux_in(i)(1)(N+2*i-1 downto 2*i) <= A;
tot_mux_in(i)(1)(2*i-1 downto 0) <= (others => '0');
notmuxA(i)(2*N-1 downto N+2*i) <= (others => ('0'OR A(N-1)) and extend);
notmuxA(i)(N+2*i-1 downto 2*i) <= A;
notmuxA(i)(2*i-1 downto 0) <= (others => '0');
tot_mux_in(i)(2) <= std_logic_vector(signed(NOT(notmuxA(i))) + 1);
tot_mux_in(i)(3)(2*N-1 downto N+1+2*i) <= (others => ('0'OR A(N-1)) and extend);
tot_mux_in(i)(3)(N+2*i downto 2*i+1) <= A;
tot_mux_in(i)(3)(2*i downto 0) <= (others => '0');
notmux2A(i)(2*N-1 downto N+1+2*i) <= (others => ('0'OR A(N-1)) and extend);
notmux2A(i)(N+2*i downto 2*i+1) <= A;
notmux2A(i)(2*i downto 0) <= (others => '0');
tot_mux_in(i)(4) <= std_logic_vector(signed(NOT(notmux2A(i))) + 1);
end generate mlevel_i;
end generate in_mu;
mux_loop: for i in 0 to N/2 generate
mux_i : mux8to1_gen
generic map (M => 2*N)
-- TODO:fix this with a proper port map
port map (tot_mux_in(i)(0), tot_mux_in(i)(1), tot_mux_in(i)(2), tot_mux_in(i)(3), tot_mux_in(i)(4), zeros, zeros, zeros, tot_select(i), tot_mux_out_reg(0)(i));
end generate mux_loop;
sum_loop: for i in 0 to N/2-1 generate
level_0 : IF i = 0 generate
sum1 : rca
generic map (M => 2*N)
port map(tot_mux_out_reg(0)(0),tot_mux_out_reg(0)(1), next_sum(i));
end generate level_0;
level_i : IF i > 0 generate
sum_i : rca
generic map (M => 2*N)
port map(sum(i-1), tot_mux_out_reg(i)(i+1), next_sum(i));
end generate level_i;
end generate sum_loop;
process(Reset,Clock)
begin
if Reset = '1' then
for i in 0 to N/2 loop
sum(i) <= (others => '0');
-- tot_mux_out_reg(0)(i) <= (others => '0');
end loop;
else
if Clock = '1' and Clock'event then
for i in 0 to N/2 loop
sum(i) <= next_sum(i);
end loop;
tot_mux_out_reg(1) <= tot_mux_out_reg(0);
tot_mux_out_reg(2) <= tot_mux_out_reg(1);
tot_mux_out_reg(3) <= tot_mux_out_reg(2);
tot_mux_out_reg(4) <= tot_mux_out_reg(3);
tot_mux_out_reg(5) <= tot_mux_out_reg(4);
tot_mux_out_reg(6) <= tot_mux_out_reg(5);
tot_mux_out_reg(7) <= tot_mux_out_reg(6);
tot_mux_out_reg(8) <= tot_mux_out_reg(7);
end if;
end if;
end process;
end BEHAVIOR;
|
bsd-2-clause
|
dpolad/dlx
|
DLX_vhd/a.i.a.d.a-XOR32.vhd
|
2
|
358
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity xor_gen is
generic (
N : integer := 32
);
Port (
A : In std_logic_vector(N-1 downto 0);
B : In std_logic;
S : Out std_logic_vector(N-1 downto 0)
);
end xor_gen;
architecture bhe of xor_gen is
begin
S <= A xor (N-1 downto 0 => B);
end bhe;
|
bsd-2-clause
|
rqou/yavhdl
|
parser_tests/name3.vhd
|
1
|
62
|
entity test is
constant a : b :=
foo(5)(0 to 2);
end;
|
bsd-2-clause
|
rqou/yavhdl
|
parser_tests/ext_id5.vhd
|
1
|
23
|
entity \test
\ is end;
|
bsd-2-clause
|
rqou/yavhdl
|
analyser_json_tests/entity_empty.vhd
|
2
|
26
|
entity test is begin end;
|
bsd-2-clause
|
rqou/yavhdl
|
parser_tests/comment1.vhd
|
1
|
61
|
entity test is--This is a comment a
¡¢£ÀÁÂÃðñòó
end;
|
bsd-2-clause
|
rqou/yavhdl
|
parser_tests/subtype_indication_generic_map_arrow23.vhd
|
1
|
71
|
entity test is
package a is new b generic map(c => foo(bar));
end;
|
bsd-2-clause
|
rqou/yavhdl
|
parser_tests/expr8.vhd
|
1
|
72
|
entity test is
constant a : b :=
foo /= bar nand nand baz;
end;
|
bsd-2-clause
|
rqou/yavhdl
|
parser_tests/entity2.vhd
|
1
|
27
|
entity test is end entity;
|
bsd-2-clause
|
rqou/yavhdl
|
parser_tests/name_ext2.vhd
|
1
|
73
|
entity test is
constant a : b :=
<<constant @foo.bar : t>>;
end;
|
bsd-2-clause
|
rqou/yavhdl
|
parser_tests/lit_based6.vhd
|
1
|
55
|
entity test is
type t is range 0 to 16#g.f#2;
end;
|
bsd-2-clause
|
rqou/yavhdl
|
parser_tests/subtype_indication_generic_map_arrow8.vhd
|
1
|
91
|
entity test is
package a is new b generic map(c => bar foo'subtype range 0 to 2);
end;
|
bsd-2-clause
|
rqou/yavhdl
|
analyser_json_tests/type_enum4_overload.vhd
|
1
|
86
|
entity test is
type test1 is (foo, bar);
type test2 is (foo, baz);
begin end;
|
bsd-2-clause
|
rqou/yavhdl
|
parser_tests/expr_primary6.vhd
|
1
|
69
|
entity test is
constant a : b :=
foo'(bar, baz => qux);
end;
|
bsd-2-clause
|
rqou/yavhdl
|
parser_tests/subtype_indication_generic_map_arrow28.vhd
|
1
|
85
|
entity test is
package a is new b generic map(c => foo(bar)(0 to 2)(open));
end;
|
bsd-2-clause
|
rqou/yavhdl
|
parser_tests/package1.vhd
|
1
|
21
|
package test is end;
|
bsd-2-clause
|
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