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stringlengths 6
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stringlengths 5
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stringclasses 54
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stringlengths 1
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stringlengths 0
1.04M
⌀ | license
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values |
|---|---|---|---|---|---|
daringer/schemmaker
|
testdata/circuit_bi1_0op324_2.vhdl
|
1
|
3737
|
package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias1: electrical;
terminal vdd: electrical;
terminal gnd: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical;
terminal vbias4: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
begin
subnet0_subnet0_m1 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in1,
S => net2
);
subnet0_subnet0_m2 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => out1,
G => in2,
S => net2
);
subnet0_subnet0_m3 : entity pmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net2,
G => vbias1,
S => vdd
);
subnet0_subnet1_m1 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net1,
G => net1,
S => gnd
);
subnet0_subnet1_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcmcout_1,
scope => private
)
port map(
D => out1,
G => net1,
S => gnd
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
I => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net3
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net3,
G => vbias4,
S => gnd
);
end simple;
|
apache-2.0
|
daringer/schemmaker
|
testdata/circuit_bi1_0op332_1.vhdl
|
1
|
4729
|
package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias1: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
begin
subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in1,
S => net4
);
subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in2,
S => net4
);
subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net4,
G => vbias4,
S => gnd
);
subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => Lcm_2,
W => Wcm_2,
scope => private,
symmetry_scope => sym_1
)
port map(
D => net1,
G => net1,
S => vdd
);
subnet0_subnet1_m2 : entity pmos(behave)
generic map(
L => Lcm_2,
W => Wcmout_2,
scope => private,
symmetry_scope => sym_1
)
port map(
D => net3,
G => net1,
S => vdd
);
subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => Lcm_2,
W => Wcm_2,
scope => private,
symmetry_scope => sym_1
)
port map(
D => net2,
G => net2,
S => vdd
);
subnet0_subnet2_m2 : entity pmos(behave)
generic map(
L => Lcm_2,
W => Wcmout_2,
scope => private,
symmetry_scope => sym_1
)
port map(
D => out1,
G => net2,
S => vdd
);
subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net3,
G => net3,
S => gnd
);
subnet0_subnet3_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcmcout_1,
scope => private
)
port map(
D => out1,
G => net3,
S => gnd
);
subnet0_subnet3_c1 : entity cap(behave)
generic map(
C => Ccurmir_1,
scope => private
)
port map(
P => out1,
N => net3
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
I => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net5
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net5,
G => vbias4,
S => gnd
);
end simple;
|
apache-2.0
|
sergeykhbr/riscv_vhdl
|
vhdl/rtl/techmap/mem/syncram_2p_inferred.vhd
|
1
|
2121
|
-----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - [email protected]
--! @brief Synchronous 2-port ram, common clock
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
entity syncram_2p_inferred is
generic (
abits : integer := 8;
dbits : integer := 32;
sepclk: integer := 0
);
port (
rclk : in std_ulogic;
wclk : in std_ulogic;
rdaddress: in std_logic_vector (abits -1 downto 0);
wraddress: in std_logic_vector (abits -1 downto 0);
data: in std_logic_vector (dbits -1 downto 0);
wren : in std_ulogic;
q: out std_logic_vector (dbits -1 downto 0)
);
end;
architecture arch_syncram_2p_inferred of syncram_2p_inferred is
type dregtype is array (0 to 2**abits - 1)
of std_logic_vector(dbits -1 downto 0);
--! This fuinction just to check with C++ reference model. Can be removed.
impure function init_ram(file_name : in string) return dregtype is
variable temp_mem : dregtype;
begin
for i in 0 to (2**abits - 1) loop
if dbits = 64 then
temp_mem(i) := X"0000000000000000";--X"CCCCCCCC";
elsif dbits = 32 then
temp_mem(i) := X"00000000";--X"CCCCCCCC";
else
temp_mem(i) := X"0000";--X"CCCC";
end if;
end loop;
return temp_mem;
end function;
signal rfd : dregtype := init_ram("");
begin
wp : process(wclk)
begin
if rising_edge(wclk) then
if wren = '1' then rfd(conv_integer(wraddress)) <= data; end if;
end if;
end process;
oneclk : if sepclk = 0 generate
rp : process(wclk) begin
if rising_edge(wclk) then
q <= rfd(conv_integer(rdaddress));
end if;
end process;
end generate;
twoclk : if sepclk = 1 generate
rp : process(rclk) begin
if rising_edge(rclk) then q <= rfd(conv_integer(rdaddress)); end if;
end process;
end generate;
end;
|
apache-2.0
|
sergeykhbr/riscv_vhdl
|
vhdl/rtl/techmap/mem/otp_clocked.vhd
|
1
|
2191
|
--!
--! Copyright 2019 Sergey Khabarov, [email protected]
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS,
--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--! See the License for the specific language governing permissions and
--! limitations under the License.
--!
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.ALL;
use IEEE.STD_LOGIC_TEXTIO.ALL;
use std.textio.all;
library commonlib;
use commonlib.types_common.all;
entity otp_clocked is
port (
clk : in std_ulogic;
we : in std_ulogic;
re : in std_ulogic;
address : in std_logic_vector(11 downto 0);
wdata : in std_logic_vector(15 downto 0);
rdata : out std_logic_vector(15 downto 0)
);
end;
architecture arch_otp_clocked of otp_clocked is
constant SRAM_LENGTH : integer := 2**12;
constant FILE_IMAGE_LINES_TOTAL : integer := SRAM_LENGTH;
type ram_type is array (0 to SRAM_LENGTH-1) of std_logic_vector(15 downto 0);
impure function init_ram(file_name : in string) return ram_type is
file ram_file : text open read_mode is file_name;
variable ram_line : line;
variable temp_bv : std_logic_vector(15 downto 0);
variable temp_mem : ram_type;
begin
for i in 0 to (FILE_IMAGE_LINES_TOTAL-1) loop
readline(ram_file, ram_line);
hread(ram_line, temp_bv);
temp_mem(i) := temp_bv;
end loop;
return temp_mem;
end function;
--! @warning SIMULATION INITIALIZATION
signal ram : ram_type;-- := init_ram(init_file);
begin
reg : process (clk, address, we, re, wdata, ram) begin
if rising_edge(clk) then
if we = '1' then
ram(conv_integer(address)) <= wdata;
end if;
end if;
if wdata = X"FFFF" and re = '1' then
rdata <= ram(conv_integer(address));
else
rdata <= X"CCCC";
end if;
end process;
end;
|
apache-2.0
|
sergeykhbr/riscv_vhdl
|
vhdl/rtl/techmap/mem/ram_tech.vhd
|
1
|
1894
|
--!
--! Copyright 2019 Sergey Khabarov, [email protected]
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS,
--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--! See the License for the specific language governing permissions and
--! limitations under the License.
--!
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
library techmap;
use techmap.gencomp.all;
use techmap.types_mem.all;
entity ram_tech is generic (
memtech : integer := 0;
abits : integer := 12;
dbits : integer := 64
);
port (
i_clk : in std_logic;
i_addr : in std_logic_vector(abits-1 downto 0);
o_rdata : out std_logic_vector(dbits-1 downto 0);
i_wena : in std_logic;
i_wdata : in std_logic_vector(dbits-1 downto 0)
);
end;
architecture rtl of ram_tech is
component ram_inferred is
generic (
abits : integer := 12;
dbits : integer := 64
);
port (
i_clk : in std_logic;
i_addr : in std_logic_vector(abits-1 downto 0);
o_rdata : out std_logic_vector(dbits-1 downto 0);
i_wena : in std_logic;
i_wdata : in std_logic_vector(dbits-1 downto 0)
);
end component;
begin
inf0 : if memtech = inferred or is_fpga(memtech) /= 0 generate
x0 : ram_inferred generic map
(
abits => abits,
dbits => dbits
) port map (
i_clk => i_clk,
i_addr => i_addr,
o_rdata => o_rdata,
i_wena => i_wena,
i_wdata => i_wdata
);
end generate;
end;
|
apache-2.0
|
sergeykhbr/riscv_vhdl
|
vhdl/rtl/riverlib/core/arith/int_mul.vhd
|
1
|
9049
|
--!
--! Copyright 2019 Sergey Khabarov, [email protected]
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS,
--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--! See the License for the specific language governing permissions and
--! limitations under the License.
--!
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all; -- or_reduce()
library commonlib;
use commonlib.types_common.all;
--! RIVER CPU specific library.
library riverlib;
--! RIVER CPU configuration constants.
use riverlib.river_cfg.all;
entity IntMul is generic (
async_reset : boolean
);
port (
i_clk : in std_logic;
i_nrst : in std_logic;
i_ena : in std_logic; -- Enable bit
i_unsigned : in std_logic; -- Unsigned operands
i_hsu : in std_logic; -- MULHSU instruction signed * unsigned
i_high : in std_logic; -- High multiplied bits [127:64]
i_rv32 : in std_logic; -- 32-bits operands enable
i_a1 : in std_logic_vector(RISCV_ARCH-1 downto 0); -- Operand 1
i_a2 : in std_logic_vector(RISCV_ARCH-1 downto 0); -- Operand 1
o_res : out std_logic_vector(RISCV_ARCH-1 downto 0); -- Result
o_valid : out std_logic; -- Result is valid
o_busy : out std_logic -- Multiclock instruction under processing
);
end;
architecture arch_IntMul of IntMul is
type Level0Type is array (0 to 31) of std_logic_vector(65 downto 0);
type Level1Type is array (0 to 15) of std_logic_vector(68 downto 0);
type Level2Type is array (0 to 7) of std_logic_vector(73 downto 0);
type Level3Type is array (0 to 3) of std_logic_vector(82 downto 0);
type Level4Type is array (0 to 1) of std_logic_vector(99 downto 0);
type RegistersType is record
busy : std_logic;
ena : std_logic_vector(3 downto 0);
a1 : std_logic_vector(RISCV_ARCH-1 downto 0);
a2 : std_logic_vector(RISCV_ARCH-1 downto 0);
unsign : std_logic;
high : std_logic;
rv32 : std_logic;
zero : std_logic;
inv : std_logic;
result : std_logic_vector(127 downto 0);
end record;
constant R_RESET : RegistersType := (
'0', (others => '0'), -- busy, ena
(others => '0'), (others => '0'), '0', -- a1, a2, unsign
'0', '0', -- high, rv32,
'0', '0', -- zero, inv
(others => '0') -- result
);
-- Some synthezators crush when try to initialize two-dimensional array
-- so exclude from register type and avoid using (others => (others =>))
signal r_lvl1, rin_lvl1 : Level1Type;
signal r_lvl3, rin_lvl3 : Level3Type;
signal r, rin : RegistersType;
begin
comb : process(i_nrst, i_ena, i_unsigned, i_hsu, i_high, i_rv32, i_a1, i_a2,
r, r_lvl1, r_lvl3)
variable v : RegistersType;
variable v_lvl1 : Level1Type;
variable v_lvl3 : Level3Type;
variable wb_mux_lvl0 : std_logic_vector(1 downto 0);
variable wb_lvl0 : Level0Type;
variable wb_lvl2 : Level2Type;
variable wb_lvl4 : Level4Type;
variable wb_lvl5 : std_logic_vector(127 downto 0);
variable wb_res32 : std_logic_vector(127 downto 0);
variable wb_res : std_logic_vector(RISCV_ARCH-1 downto 0);
variable vb_a1s : std_logic_vector(63 downto 0);
variable vb_a2s : std_logic_vector(63 downto 0);
variable v_a1s_nzero : std_logic;
variable v_a2s_nzero : std_logic;
begin
v := r;
v_a1s_nzero := or_reduce(i_a1(62 downto 0));
if v_a1s_nzero = '1' and i_a1(63) = '1' then
vb_a1s := (not i_a1) + 1;
else
vb_a1s := i_a1;
end if;
v_a2s_nzero := or_reduce(i_a2(62 downto 0));
if v_a2s_nzero = '1' and i_a2(63) = '1' then
vb_a2s := (not i_a2) + 1;
else
vb_a2s := i_a2;
end if;
v_lvl1 := r_lvl1;
v_lvl3 := r_lvl3;
for i in 0 to 7 loop
wb_lvl2(i) := (others => '0');
end loop;
for i in 0 to 1 loop
wb_lvl4(i) := (others => '0');
end loop;
wb_lvl5 := (others => '0');
wb_res32 := (others => '0');
v.ena := r.ena(2 downto 0) & (i_ena and not r.busy);
if i_ena = '1' then
v.busy := '1';
v.inv := '0';
v.zero := '0';
if i_rv32 = '1' then
v.a1(31 downto 0) := i_a1(31 downto 0);
if (not i_unsigned and i_a1(31)) = '1' then
v.a1(63 downto 32) := (others => '1');
end if;
v.a2(31 downto 0) := i_a2(31 downto 0);
if (not i_unsigned and i_a2(31)) = '1' then
v.a2(63 downto 32) := (others => '1');
end if;
elsif i_high = '1' then
if i_hsu = '1' then
v.zero := (not v_a1s_nzero) or (not or_reduce(i_a2));
v.inv := i_a1(63);
v.a1 := vb_a1s;
v.a2 := i_a2;
elsif i_unsigned = '1' then
v.a1 := i_a1;
v.a2 := i_a2;
else
v.zero := (not v_a1s_nzero) or (not v_a2s_nzero);
v.inv := i_a1(63) xor i_a2(63);
v.a1 := vb_a1s;
v.a2 := vb_a2s;
end if;
else
v.a1 := i_a1;
v.a2 := i_a2;
end if;
v.rv32 := i_rv32;
v.unsign := i_unsigned;
v.high := i_high;
end if;
if r.ena(0) = '1' then
for i in 0 to 31 loop
wb_mux_lvl0 := r.a2(2*i + 1 downto 2*i);
if wb_mux_lvl0 = "00" then
wb_lvl0(i) := (others => '0');
elsif wb_mux_lvl0 = "01" then
wb_lvl0(i) := ("00" & r.a1);
elsif wb_mux_lvl0 = "10" then
wb_lvl0(i) := ("0" & r.a1 & "0");
else
wb_lvl0(i) := ("00" & r.a1) + ("0" & r.a1 & "0");
end if;
end loop;
for i in 0 to 15 loop
v_lvl1(i) := ("0" & wb_lvl0(2*i + 1) & "00")
+ ("000" & wb_lvl0(2*i));
end loop;
end if;
if r.ena(1) = '1' then
for i in 0 to 7 loop
wb_lvl2(i) := ("0" & r_lvl1(2*i + 1) & "0000")
+ ("00000" & r_lvl1(2*i));
end loop;
for i in 0 to 3 loop
v_lvl3(i) := ("0" & wb_lvl2(2*i + 1) & "00000000")
+ ("000000000" & wb_lvl2(2*i));
end loop;
end if;
if r.ena(2) = '1' then
v.busy := '0';
for i in 0 to 1 loop
wb_lvl4(i) := ("0" & r_lvl3(2*i + 1) & "0000000000000000")
+ ("00000000000000000" & r_lvl3(2*i));
end loop;
wb_lvl5 := (wb_lvl4(1)(95 downto 0) & X"00000000")
+ (X"0000000" & wb_lvl4(0));
if r.rv32 = '1' then
wb_res32(31 downto 0) := wb_lvl5(31 downto 0);
if r.unsign = '1' or wb_lvl5(31) = '0' then
wb_res32(127 downto 32) := (others => '0');
else
wb_res32(127 downto 32) := (others => '1');
end if;
v.result := wb_res32;
elsif r.high = '1' then
v.result(63 downto 0) := wb_lvl5(63 downto 0); -- ignore low part
if r.zero = '1' then
v.result(127 downto 64) := (others => '0');
elsif r.inv = '1' then
v.result(127 downto 64) := not wb_lvl5(127 downto 64);
else
v.result(127 downto 64) := wb_lvl5(127 downto 64);
end if;
else
v.result := wb_lvl5;
end if;
end if;
wb_res := r.result(63 downto 0);
if r.high = '1' then
wb_res := r.result(127 downto 64); --! not tested yet
end if;
if not async_reset and i_nrst = '0' then
v := R_RESET;
for i in 0 to 15 loop
v_lvl1(i) := (others => '0');
end loop;
for i in 0 to 3 loop
v_lvl3(i) := (others => '0');
end loop;
end if;
o_res <= wb_res;
o_valid <= r.ena(3);
o_busy <= r.busy;
rin <= v;
rin_lvl1 <= v_lvl1;
rin_lvl3 <= v_lvl3;
end process;
-- registers:
regs : process(i_clk, i_nrst)
begin
if async_reset and i_nrst = '0' then
r <= R_RESET;
for i in 0 to 15 loop
r_lvl1(i) <= (others => '0');
end loop;
for i in 0 to 3 loop
r_lvl3(i) <= (others => '0');
end loop;
elsif rising_edge(i_clk) then
r <= rin;
r_lvl1 <= rin_lvl1;
r_lvl3 <= rin_lvl3;
end if;
end process;
end;
|
apache-2.0
|
sergeykhbr/riscv_vhdl
|
vhdl/rtl/misclib/axi4_gptimers.vhd
|
1
|
8456
|
--!
--! Copyright 2019 Sergey Khabarov, [email protected]
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS,
--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--! See the License for the specific language governing permissions and
--! limitations under the License.
--!
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
--! AMBA system bus specific library.
library ambalib;
--! AXI4 configuration constants.
use ambalib.types_amba4.all;
library misclib;
use misclib.types_misc.all;
entity axi4_gptimers is
generic (
async_reset : boolean := false;
xaddr : integer := 0;
xmask : integer := 16#fffff#;
xirq : integer := 0;
tmr_total : integer := 2
);
port (
clk : in std_logic;
nrst : in std_logic;
cfg : out axi4_slave_config_type;
i_axi : in axi4_slave_in_type;
o_axi : out axi4_slave_out_type;
o_pwm : out std_logic_vector(tmr_total-1 downto 0);
o_irq : out std_logic
);
end;
architecture arch_axi4_gptimers of axi4_gptimers is
constant xconfig : axi4_slave_config_type := (
descrtype => PNP_CFG_TYPE_SLAVE,
descrsize => PNP_CFG_SLAVE_DESCR_BYTES,
irq_idx => conv_std_logic_vector(xirq, 8),
xaddr => conv_std_logic_vector(xaddr, CFG_SYSBUS_CFG_ADDR_BITS),
xmask => conv_std_logic_vector(xmask, CFG_SYSBUS_CFG_ADDR_BITS),
vid => VENDOR_GNSSSENSOR,
did => GNSSSENSOR_GPTIMERS
);
constant zero64 : std_logic_vector(63 downto 0) := (others => '0');
type timer_type is record
count_ena : std_logic;
irq_ena : std_logic;
pwm_ena : std_logic;
pwm_polarity : std_logic;
value : std_logic_vector(63 downto 0);
init_value : std_logic_vector(63 downto 0);
pwm_threshold : std_logic_vector(63 downto 0);
end record;
constant timer_type_reset : timer_type :=
('0', '0',
'0', '0',
(others => '0'),
(others => '0'),
(others => '0'));
type vector_timer_type is array (0 to tmr_total-1) of timer_type;
type registers is record
tmr : vector_timer_type;
highcnt : std_logic_vector(63 downto 0);
pending : std_logic_vector(tmr_total-1 downto 0);
pwm : std_logic_vector(tmr_total-1 downto 0);
raddr : global_addr_array_type;
end record;
constant R_RESET : registers := (
(others => timer_type_reset), (others => '0'), (others => '0'),
(others => '0'), ((others => '0'), (others => '0'))
);
signal r, rin : registers;
signal wb_dev_rdata : std_logic_vector(CFG_SYSBUS_DATA_BITS-1 downto 0);
signal wb_bus_raddr : global_addr_array_type;
signal w_bus_re : std_logic;
signal wb_bus_waddr : global_addr_array_type;
signal w_bus_we : std_logic;
signal wb_bus_wstrb : std_logic_vector(CFG_SYSBUS_DATA_BYTES-1 downto 0);
signal wb_bus_wdata : std_logic_vector(CFG_SYSBUS_DATA_BITS-1 downto 0);
begin
axi0 : axi4_slave generic map (
async_reset => async_reset
) port map (
i_clk => clk,
i_nrst => nrst,
i_xcfg => xconfig,
i_xslvi => i_axi,
o_xslvo => o_axi,
i_ready => '1',
i_rdata => wb_dev_rdata,
o_re => w_bus_re,
o_r32 => open,
o_radr => wb_bus_raddr,
o_wadr => wb_bus_waddr,
o_we => w_bus_we,
o_wstrb => wb_bus_wstrb,
o_wdata => wb_bus_wdata
);
comblogic : process(nrst, r, w_bus_re, wb_bus_raddr, wb_bus_waddr,
w_bus_we, wb_bus_wstrb, wb_bus_wdata)
variable v : registers;
variable raddr : integer;
variable waddr : integer;
variable vrdata : std_logic_vector(CFG_SYSBUS_DATA_BITS-1 downto 0);
variable tmp : std_logic_vector(31 downto 0);
variable irq_ena : std_logic;
begin
v := r;
v.raddr := wb_bus_raddr;
v.highcnt := r.highcnt + 1;
irq_ena := '0';
for n in 0 to tmr_total-1 loop
if r.tmr(n).count_ena = '1' then
if r.tmr(n).pwm_ena = '1' and r.tmr(n).value = r.tmr(n).pwm_threshold then
v.pwm(n) := not r.pwm(n);
end if;
if r.tmr(n).value = zero64 then
irq_ena := irq_ena or r.tmr(n).irq_ena;
v.pending(n) := r.tmr(n).irq_ena;
v.pwm(n) := r.tmr(n).pwm_polarity;
v.tmr(n).value := r.tmr(n).init_value;
else
v.tmr(n).value := r.tmr(n).value - 1;
end if;
else
v.tmr(n).value := r.tmr(n).init_value;
v.pwm(n) := r.tmr(n).pwm_polarity;
end if;
end loop;
for n in 0 to CFG_WORDS_ON_BUS-1 loop
tmp := (others => '0');
raddr := conv_integer(r.raddr(n)(11 downto 2));
case raddr is
when 0 =>
tmp := r.highcnt(31 downto 0);
when 1 =>
tmp := r.highcnt(63 downto 32);
when 2 =>
tmp(tmr_total-1 downto 0) := r.pending;
when 3 =>
tmp(tmr_total-1 downto 0) := r.pwm;
when others =>
for k in 0 to tmr_total-1 loop
if raddr = (16 + 8*k) then
tmp(0) := r.tmr(k).count_ena;
tmp(1) := r.tmr(k).irq_ena;
tmp(4) := r.tmr(k).pwm_ena;
tmp(5) := r.tmr(k).pwm_polarity;
elsif raddr = (16 + 8*k + 2) then
tmp := r.tmr(k).value(31 downto 0);
elsif raddr = (16 + 8*k + 3) then
tmp := r.tmr(k).value(63 downto 32);
elsif raddr = (16 + 8*k + 4) then
tmp := r.tmr(k).init_value(31 downto 0);
elsif raddr = (16 + 8*k + 5) then
tmp := r.tmr(k).init_value(63 downto 32);
elsif raddr = (16 + 8*k + 6) then
tmp := r.tmr(k).pwm_threshold(31 downto 0);
elsif raddr = (16 + 8*k + 7) then
tmp := r.tmr(k).pwm_threshold(63 downto 32);
end if;
end loop;
end case;
vrdata(8*CFG_ALIGN_BYTES*(n+1)-1 downto 8*CFG_ALIGN_BYTES*n) := tmp;
end loop;
if w_bus_we = '1' then
for n in 0 to CFG_WORDS_ON_BUS-1 loop
if conv_integer(wb_bus_wstrb(CFG_ALIGN_BYTES*(n+1)-1 downto CFG_ALIGN_BYTES*n)) /= 0 then
tmp := wb_bus_wdata(8*CFG_ALIGN_BYTES*(n+1)-1 downto 8*CFG_ALIGN_BYTES*n);
waddr := conv_integer(wb_bus_waddr(n)(11 downto 2));
case waddr is
when 2 =>
v.pending := tmp(tmr_total-1 downto 0);
when others =>
for k in 0 to tmr_total-1 loop
if waddr = (16 + 8*k) then
v.tmr(k).count_ena := tmp(0);
v.tmr(k).irq_ena := tmp(1);
v.tmr(k).pwm_ena := tmp(4);
v.tmr(k).pwm_polarity := tmp(5);
elsif waddr = (16 + 8*k + 2) then
v.tmr(k).value(31 downto 0) := tmp;
elsif waddr = (16 + 8*k + 3) then
v.tmr(k).value(63 downto 32) := tmp;
elsif waddr = (16 + 8*k + 4) then
v.tmr(k).init_value(31 downto 0) := tmp;
elsif waddr = (16 + 8*k + 5) then
v.tmr(k).init_value(63 downto 32) := tmp;
elsif waddr = (16 + 8*k + 6) then
v.tmr(k).pwm_threshold(31 downto 0) := tmp;
elsif waddr = (16 + 8*k + 7) then
v.tmr(k).pwm_threshold(63 downto 32) := tmp;
end if;
end loop;
end case;
end if;
end loop;
end if;
if not async_reset and nrst = '0' then
v := R_RESET;
end if;
rin <= v;
o_irq <= irq_ena;
o_pwm <= r.pwm;
wb_dev_rdata <= vrdata;
end process;
cfg <= xconfig;
-- registers:
regs : process(clk, nrst)
begin
if async_reset and nrst = '0' then
r <= R_RESET;
elsif rising_edge(clk) then
r <= rin;
end if;
end process;
end;
|
apache-2.0
|
sergeykhbr/riscv_vhdl
|
vhdl/rtl/work/riscv_soc.vhd
|
1
|
24812
|
--!
--! Copyright 2019 Sergey Khabarov, [email protected]
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS,
--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--! See the License for the specific language governing permissions and
--! limitations under the License.
--!
--! Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--! Data transformation and math functions library
library commonlib;
use commonlib.types_common.all;
--! Technology definition library.
library techmap;
--! Technology constants definition.
use techmap.gencomp.all;
--! AMBA system bus specific library
library ambalib;
--! AXI4 configuration constants.
use ambalib.types_amba4.all;
use ambalib.types_bus0.all;
--! Misc modules library
library misclib;
use misclib.types_misc.all;
--! Ethernet related declarations.
library ethlib;
use ethlib.types_eth.all;
--! gnss sub-system library
library gnsslib;
use gnsslib.types_gnss.all;
--! River CPU specific library
library riverlib;
--! River top level with AMBA interface module declaration
use riverlib.types_river.all;
--! Top-level implementaion library
library work;
--! Target dependable configuration: RTL, FPGA or ASIC.
use work.config_target.all;
--! @brief SOC Top-level entity declaration.
--! @details This module implements full SOC functionality and all IO signals
--! are available on FPGA/ASIC IO pins.
entity riscv_soc is port
(
i_rst : in std_logic;
i_clk : in std_logic;
--! GPIO.
i_gpio : in std_logic_vector(11 downto 0);
o_gpio : out std_logic_vector(11 downto 0);
o_gpio_dir : out std_logic_vector(11 downto 0);
--! GPTimers
o_pwm : out std_logic_vector(1 downto 0);
--! JTAG signals:
i_jtag_tck : in std_logic;
i_jtag_ntrst : in std_logic;
i_jtag_tms : in std_logic;
i_jtag_tdi : in std_logic;
o_jtag_tdo : out std_logic;
o_jtag_vref : out std_logic;
--! UART1 signals:
i_uart1_ctsn : in std_logic;
i_uart1_rd : in std_logic;
o_uart1_td : out std_logic;
o_uart1_rtsn : out std_logic;
--! UART2 (debug port) signals:
i_uart2_ctsn : in std_logic;
i_uart2_rd : in std_logic;
o_uart2_td : out std_logic;
o_uart2_rtsn : out std_logic;
--! SPI Flash
i_flash_si : in std_logic;
o_flash_so : out std_logic;
o_flash_sck : out std_logic;
o_flash_csn : out std_logic;
o_flash_wpn : out std_logic;
o_flash_holdn : out std_logic;
o_flash_reset : out std_logic;
--! OTP Memory
i_otp_d : in std_logic_vector(15 downto 0);
o_otp_d : out std_logic_vector(15 downto 0);
o_otp_a : out std_logic_vector(11 downto 0);
o_otp_we : out std_logic;
o_otp_re : out std_logic;
--! Ethernet MAC PHY interface signals
i_etx_clk : in std_ulogic;
i_erx_clk : in std_ulogic;
i_erxd : in std_logic_vector(3 downto 0);
i_erx_dv : in std_ulogic;
i_erx_er : in std_ulogic;
i_erx_col : in std_ulogic;
i_erx_crs : in std_ulogic;
i_emdint : in std_ulogic;
o_etxd : out std_logic_vector(3 downto 0);
o_etx_en : out std_ulogic;
o_etx_er : out std_ulogic;
o_emdc : out std_ulogic;
i_eth_mdio : in std_logic;
o_eth_mdio : out std_logic;
o_eth_mdio_oe : out std_logic;
i_eth_gtx_clk : in std_logic;
i_eth_gtx_clk_90 : in std_logic;
o_erstn : out std_ulogic;
-- GNSS Sub-system signals:
i_clk_adc : in std_logic; -- GNSS ADC clock (4..40 MHz)
i_gps_I : in std_logic_vector(1 downto 0); -- Channel 0 sampled I value
i_gps_Q : in std_logic_vector(1 downto 0); -- Channel 0 sampled Q value
i_glo_I : in std_logic_vector(1 downto 0); -- Channel 1 sampled I value
i_glo_Q : in std_logic_vector(1 downto 0); -- Channel 1 sampled I value
o_pps : out std_logic; -- Pulse Per Second signal
i_gps_ld : in std_logic; -- Channel 0 RF front-end Lock detect
i_glo_ld : in std_logic; -- Channel 1 RF front-end Lock detect
o_max_sclk : out std_logic; -- RF synthesizer SPI clock
o_max_sdata : out std_logic; -- RF synthesizer SPI data
o_max_ncs : out std_logic_vector(1 downto 0); -- RF synthesizer channel 0/1 selector
i_antext_stat : in std_logic; -- Antenna powered status
i_antext_detect : in std_logic; -- Antenna connected status
o_antext_ena : out std_logic; -- Enabling/disabling antenna
o_antint_contr : out std_logic -- Antenna Internal/External selector
);
--! @}
end riscv_soc;
--! @brief SOC top-level architecture declaration.
architecture arch_riscv_soc of riscv_soc is
signal w_glob_rst : std_ulogic; -- Global reset active HIGH
signal w_glob_nrst : std_ulogic; -- Global reset active LOW
signal w_soft_rst : std_ulogic; -- Software reset (acitve HIGH) from DSU
signal w_bus_nrst : std_ulogic; -- Global reset and Soft Reset active LOW
signal uart1i : uart_in_type;
signal uart1o : uart_out_type;
signal uart2i : uart_in_type;
signal uart2o : uart_out_type;
signal spiflashi : spi_in_type;
signal spiflasho : spi_out_type;
--! Arbiter is switching only slaves output signal, data from noc
--! is connected to all slaves and to the arbiter itself.
signal aximi : bus0_xmst_in_vector;
signal aximo : bus0_xmst_out_vector;
signal axisi : bus0_xslv_in_vector;
signal axiso : bus0_xslv_out_vector;
signal slv_cfg : bus0_xslv_cfg_vector;
signal mst_cfg : bus0_xmst_cfg_vector;
signal wb_core_irq : std_logic_vector(CFG_TOTAL_CPU_MAX-1 downto 0);
signal w_ext_irq : std_logic;
signal dport_i : dport_in_vector;
signal dport_o : dport_out_vector;
signal dmi_dport_i : dport_in_vector;
signal dmi_dport_o : dport_out_vector;
signal dsu_dport_i : dport_in_vector;
signal dsu_dport_o : dport_out_vector;
signal wb_bus_util_w : std_logic_vector(CFG_BUS0_XMST_TOTAL-1 downto 0);
signal wb_bus_util_r : std_logic_vector(CFG_BUS0_XMST_TOTAL-1 downto 0);
signal w_dmi_jtag_req_valid : std_logic;
signal w_dmi_jtag_req_ready : std_logic;
signal w_dmi_jtag_write : std_logic;
signal wb_dmi_jtag_addr : std_logic_vector(6 downto 0);
signal wb_dmi_jtag_wdata : std_logic_vector(31 downto 0);
signal w_dmi_jtag_resp_valid : std_logic;
signal w_dmi_jtag_resp_ready : std_logic;
signal wb_dmi_jtag_rdata : std_logic_vector(31 downto 0);
signal w_dmi_dsu_req_valid : std_logic;
signal w_dmi_dsu_req_ready : std_logic;
signal w_dmi_dsu_write : std_logic;
signal wb_dmi_dsu_addr : std_logic_vector(6 downto 0);
signal wb_dmi_dsu_wdata : std_logic_vector(31 downto 0);
signal w_dmi_dsu_resp_valid : std_logic;
signal w_dmi_dsu_resp_ready : std_logic;
signal wb_dmi_dsu_rdata : std_logic_vector(31 downto 0);
signal wb_dmi_hartsel : std_logic_vector(CFG_LOG2_CPU_MAX-1 downto 0);
signal eth_i : eth_in_type;
signal eth_o : eth_out_type;
signal irq_pins : std_logic_vector(CFG_IRQ_TOTAL-1 downto 1);
signal w_otp_busy : std_logic;
signal wb_otp_cfg_rsetup : std_logic_vector(3 downto 0);
signal wb_otp_cfg_wadrsetup : std_logic_vector(3 downto 0);
signal wb_otp_cfg_wactive : std_logic_vector(31 downto 0);
signal wb_otp_cfg_whold : std_logic_vector(3 downto 0);
begin
------------------------------------
--! @brief System Reset device instance.
rst0 : reset_global port map (
inSysReset => i_rst,
inSysClk => i_clk,
outReset => w_glob_rst
);
w_glob_nrst <= not w_glob_rst;
w_bus_nrst <= not (w_glob_rst or w_soft_rst);
--! @brief AXI4 controller.
ctrl0 : axictrl_bus0 generic map (
async_reset => CFG_ASYNC_RESET
) port map (
i_clk => i_clk,
i_nrst => w_glob_nrst,
i_slvcfg => slv_cfg,
i_slvo => axiso,
i_msto => aximo,
o_slvi => axisi,
o_msti => aximi,
o_bus_util_w => wb_bus_util_w, -- Bus write access utilization per master statistic
o_bus_util_r => wb_bus_util_r -- Bus read access utilization per master statistic
);
wb_core_irq(CFG_TOTAL_CPU_MAX-1 downto 1) <= (others => '0');
wb_core_irq(0) <= w_ext_irq; -- TODO: other CPU interrupts
group0 : river_workgroup generic map (
cpunum => CFG_CPU_NUM,
memtech => CFG_MEMTECH,
async_reset => CFG_ASYNC_RESET,
fpu_ena => true,
coherence_ena => false,
tracer_ena => false
) port map (
i_nrst => w_bus_nrst,
i_clk => i_clk,
i_msti => aximi(CFG_BUS0_XMST_WORKGROUP),
o_msto => aximo(CFG_BUS0_XMST_WORKGROUP),
o_mstcfg => mst_cfg(CFG_BUS0_XMST_WORKGROUP),
i_dport => dport_i,
o_dport => dport_o,
i_ext_irq => wb_core_irq
);
-- Access to Debug port of the CPUs workgroup
dmregs0 : dmi_regs generic map (
async_reset => CFG_ASYNC_RESET,
cpu_available => CFG_CPU_NUM
) port map (
clk => i_clk,
nrst => w_glob_nrst,
-- port[0] connected to JTAG TAP has access to AXI master interface (SBA registers)
i_dmi_jtag_req_valid => w_dmi_jtag_req_valid,
o_dmi_jtag_req_ready => w_dmi_jtag_req_ready,
i_dmi_jtag_write => w_dmi_jtag_write,
i_dmi_jtag_addr => wb_dmi_jtag_addr,
i_dmi_jtag_wdata => wb_dmi_jtag_wdata,
o_dmi_jtag_resp_valid => w_dmi_jtag_resp_valid,
i_dmi_jtag_resp_ready => w_dmi_jtag_resp_ready,
o_dmi_jtag_rdata => wb_dmi_jtag_rdata,
-- port[1] connected to DSU doesn't have access to AXI master interface
i_dmi_dsu_req_valid => w_dmi_dsu_req_valid,
o_dmi_dsu_req_ready => w_dmi_dsu_req_ready,
i_dmi_dsu_write => w_dmi_dsu_write,
i_dmi_dsu_addr => wb_dmi_dsu_addr,
i_dmi_dsu_wdata => wb_dmi_dsu_wdata,
o_dmi_dsu_resp_valid => w_dmi_dsu_resp_valid,
i_dmi_dsu_resp_ready => w_dmi_dsu_resp_ready,
o_dmi_dsu_rdata => wb_dmi_dsu_rdata,
o_hartsel => wb_dmi_hartsel,
o_dmstat => open,
o_ndmreset => w_soft_rst,
o_cfg => mst_cfg(CFG_BUS0_XMST_DMI),
i_xmsti => aximi(CFG_BUS0_XMST_DMI),
o_xmsto => aximo(CFG_BUS0_XMST_DMI),
o_dporti => dmi_dport_i,
i_dporto => dmi_dport_o
);
-- Interconnect between DMI register and DSU debug interfaces
icdport0 : ic_dport_2s_1m generic map (
async_reset => CFG_ASYNC_RESET
) port map (
clk => i_clk,
nrst => w_glob_nrst,
i_sdport0i => dmi_dport_i,
o_sdport0o => dmi_dport_o,
i_sdport1i => dsu_dport_i,
o_sdport1o => dsu_dport_o,
o_mdporti => dport_i,
i_mdporto => dport_o
);
dsu_ena : if CFG_DSU_ENABLE generate
------------------------------------
--! @brief Debug Support Unit with access to the CSRs
--! @details Map address:
--! 0x80080000..0x8009ffff (128 KB total)
dsu0 : axi_dsu generic map (
async_reset => CFG_ASYNC_RESET,
xaddr => 16#80080#,
xmask => 16#fffe0#
) port map (
clk => i_clk,
nrst => w_glob_nrst,
o_cfg => slv_cfg(CFG_BUS0_XSLV_DSU),
i_axi => axisi(CFG_BUS0_XSLV_DSU),
o_axi => axiso(CFG_BUS0_XSLV_DSU),
o_dporti => dsu_dport_i,
i_dporto => dsu_dport_o,
i_dmi_hartsel => wb_dmi_hartsel,
o_dmi_req_valid => w_dmi_dsu_req_valid,
i_dmi_req_ready => w_dmi_dsu_req_ready,
o_dmi_write => w_dmi_dsu_write,
o_dmi_addr => wb_dmi_dsu_addr,
o_dmi_wdata => wb_dmi_dsu_wdata,
i_dmi_resp_valid => w_dmi_dsu_resp_valid,
o_dmi_resp_ready => w_dmi_dsu_resp_ready,
i_dmi_rdata => wb_dmi_dsu_rdata,
-- Run time platform statistic signals (move to tracer):
i_bus_util_w => wb_bus_util_w, -- Write access bus utilization per master statistic
i_bus_util_r => wb_bus_util_r -- Read access bus utilization per master statistic
);
end generate;
dsu_dis : if not CFG_DSU_ENABLE generate
slv_cfg(CFG_BUS0_XSLV_DSU) <= axi4_slave_config_none;
axiso(CFG_BUS0_XSLV_DSU) <= axi4_slave_out_none;
dsu_dport_i <= (others => dport_in_none);
w_dmi_dsu_req_valid <= '0';
w_dmi_dsu_write <= '0';
wb_dmi_dsu_addr <= (others => '0');
wb_dmi_dsu_wdata <= (others => '0');
w_dmi_dsu_resp_ready <= '0';
end generate;
------------------------------------
-- JTAG TAP interface
jtag0 : tap_jtag port map (
nrst => w_glob_nrst,
clk => i_clk,
i_tck => i_jtag_tck,
i_ntrst => i_jtag_ntrst,
i_tms => i_jtag_tms,
i_tdi => i_jtag_tdi,
o_tdo => o_jtag_tdo,
o_jtag_vref => o_jtag_vref,
-- DMI interface
o_dmi_req_valid => w_dmi_jtag_req_valid,
i_dmi_req_ready => w_dmi_jtag_req_ready,
o_dmi_write => w_dmi_jtag_write,
o_dmi_addr => wb_dmi_jtag_addr,
o_dmi_wdata => wb_dmi_jtag_wdata,
i_dmi_resp_valid => w_dmi_jtag_resp_valid,
o_dmi_resp_ready => w_dmi_jtag_resp_ready,
i_dmi_rdata => wb_dmi_jtag_rdata
);
------------------------------------
--! @brief TAP via UART (debug port) with master interface.
uart2i.cts <= not i_uart2_ctsn;
uart2i.rd <= i_uart2_rd;
uart2 : uart_tap port map (
nrst => w_glob_nrst,
clk => i_clk,
i_uart => uart2i,
o_uart => uart2o,
i_msti => aximi(CFG_BUS0_XMST_MSTUART),
o_msto => aximo(CFG_BUS0_XMST_MSTUART),
o_mstcfg => mst_cfg(CFG_BUS0_XMST_MSTUART)
);
o_uart2_td <= uart2o.td;
o_uart2_rtsn <= not uart2o.rts;
------------------------------------
--! @brief BOOT ROM module instance with the AXI4 interface.
--! @details Map address:
--! 0x00000000..0x00007fff (32 KB total)
boot0 : axi4_rom generic map (
memtech => CFG_MEMTECH,
async_reset => CFG_ASYNC_RESET,
xaddr => 16#00000#,
xmask => 16#ffff8#,
sim_hexfile => CFG_SIM_BOOTROM_HEX
) port map (
clk => i_clk,
nrst => w_glob_nrst,
cfg => slv_cfg(CFG_BUS0_XSLV_BOOTROM),
i => axisi(CFG_BUS0_XSLV_BOOTROM),
o => axiso(CFG_BUS0_XSLV_BOOTROM)
);
------------------------------------
--! @brief OTP module instance with the AXI4 interface.
--! @details Map address:
--! 0x00010000..0x00011fff (8 KB total)
otp_ena : if CFG_OTP8KB_ENA generate
otp0 : axi4_otp generic map (
async_reset => CFG_ASYNC_RESET,
xaddr => 16#00010#,
xmask => 16#ffffe#
) port map (
clk => i_clk,
nrst => w_glob_nrst,
cfg => slv_cfg(CFG_BUS0_XSLV_OTP),
i_axi => axisi(CFG_BUS0_XSLV_OTP),
o_axi => axiso(CFG_BUS0_XSLV_OTP),
o_otp_we => o_otp_we,
o_otp_re => o_otp_re,
o_otp_addr => o_otp_a,
o_otp_wdata => o_otp_d,
i_otp_rdata => i_otp_d,
i_cfg_rsetup => wb_otp_cfg_rsetup,
i_cfg_wadrsetup => wb_otp_cfg_wadrsetup,
i_cfg_wactive => wb_otp_cfg_wactive,
i_cfg_whold => wb_otp_cfg_whold,
o_busy => w_otp_busy
);
end generate;
otp_dis : if not CFG_OTP8KB_ENA generate
slv_cfg(CFG_BUS0_XSLV_OTP) <= axi4_slave_config_none;
axiso(CFG_BUS0_XSLV_OTP) <= axi4_slave_out_none;
o_otp_d <= X"0000";
o_otp_a <= X"000";
o_otp_we <= '0';
o_otp_re <= '0';
w_otp_busy <= '0';
end generate;
------------------------------------
--! @brief Firmware Image ROM with the AXI4 interface.
--! @details Map address:
--! 0x00100000..0x0013ffff (256 KB total)
--! @warning Don't forget to change ROM_ADDR_WIDTH in rom implementation
img0 : axi4_rom generic map (
memtech => CFG_MEMTECH,
async_reset => CFG_ASYNC_RESET,
xaddr => 16#00100#,
xmask => 16#fffc0#,
sim_hexfile => CFG_SIM_FWIMAGE_HEX
) port map (
clk => i_clk,
nrst => w_glob_nrst,
cfg => slv_cfg(CFG_BUS0_XSLV_ROMIMAGE),
i => axisi(CFG_BUS0_XSLV_ROMIMAGE),
o => axiso(CFG_BUS0_XSLV_ROMIMAGE)
);
------------------------------------
--! @brief SPI FLASH module isntance with the AXI4 interface.
--! @details Map address:
--! 0x00200000..0x0023ffff (256 KB total)
spiflashi.SDI <= i_flash_si;
flash_ena : if CFG_EXT_FLASH_ENA generate
flash0 : axi4_flashspi generic map (
async_reset => CFG_ASYNC_RESET,
xaddr => 16#00200#,
xmask => 16#fffc0#,
wait_while_write => true
) port map (
clk => i_clk,
nrst => w_glob_nrst,
cfg => slv_cfg(CFG_BUS0_XSLV_EXTFLASH),
i_spi => spiflashi,
o_spi => spiflasho,
i_axi => axisi(CFG_BUS0_XSLV_EXTFLASH),
o_axi => axiso(CFG_BUS0_XSLV_EXTFLASH)
);
end generate;
flash_dis : if not CFG_EXT_FLASH_ENA generate
slv_cfg(CFG_BUS0_XSLV_EXTFLASH) <= axi4_slave_config_none;
axiso(CFG_BUS0_XSLV_EXTFLASH) <= axi4_slave_out_none;
spiflasho <= spi_out_none;
end generate;
o_flash_so <= spiflasho.SDO;
o_flash_sck <= spiflasho.SCK;
o_flash_csn <= spiflasho.nCS;
o_flash_wpn <= spiflasho.nWP;
o_flash_holdn <= spiflasho.nHOLD;
o_flash_reset <= spiflasho.RESET;
------------------------------------
--! Internal SRAM module instance with the AXI4 interface.
--! @details Map address:
--! 0x10000000..0x1007ffff (512 KB total)
sram0 : axi4_sram generic map (
memtech => CFG_MEMTECH,
async_reset => CFG_ASYNC_RESET,
xaddr => 16#10000#,
xmask => 16#fff80#, -- 512 KB mask
abits => (10 + log2(512)), -- 512 KB address
init_file => CFG_SIM_FWIMAGE_HEX -- Used only for inferred
) port map (
clk => i_clk,
nrst => w_glob_nrst,
cfg => slv_cfg(CFG_BUS0_XSLV_SRAM),
i => axisi(CFG_BUS0_XSLV_SRAM),
o => axiso(CFG_BUS0_XSLV_SRAM)
);
------------------------------------
--! @brief Controller of the LEDs, DIPs and GPIO with the AXI4 interface.
--! @details Map address:
--! 0x80000000..0x80000fff (4 KB total)
gpio0 : axi4_gpio generic map (
async_reset => CFG_ASYNC_RESET,
xaddr => 16#80000#,
xmask => 16#fffff#,
xirq => 0,
width => 12
) port map (
clk => i_clk,
nrst => w_glob_nrst,
cfg => slv_cfg(CFG_BUS0_XSLV_GPIO),
i => axisi(CFG_BUS0_XSLV_GPIO),
o => axiso(CFG_BUS0_XSLV_GPIO),
i_gpio => i_gpio,
o_gpio => o_gpio,
o_gpio_dir => o_gpio_dir
);
------------------------------------
uart1i.cts <= not i_uart1_ctsn;
uart1i.rd <= i_uart1_rd;
--! @brief UART Controller with the AXI4 interface.
--! @details Map address:
--! 0x80001000..0x80001fff (4 KB total)
uart1 : axi4_uart generic map (
async_reset => CFG_ASYNC_RESET,
xaddr => 16#80001#,
xmask => 16#FFFFF#,
xirq => CFG_IRQ_UART1,
fifosz => 16
) port map (
nrst => w_glob_nrst,
clk => i_clk,
cfg => slv_cfg(CFG_BUS0_XSLV_UART1),
i_uart => uart1i,
o_uart => uart1o,
i_axi => axisi(CFG_BUS0_XSLV_UART1),
o_axi => axiso(CFG_BUS0_XSLV_UART1),
o_irq => irq_pins(CFG_IRQ_UART1)
);
o_uart1_td <= uart1o.td;
o_uart1_rtsn <= not uart1o.rts;
------------------------------------
--! @brief Interrupt controller with the AXI4 interface.
--! @details Map address:
--! 0x80002000..0x80002fff (4 KB total)
irq0 : axi4_irqctrl generic map (
async_reset => CFG_ASYNC_RESET,
xaddr => 16#80002#,
xmask => 16#FFFFF#
) port map (
clk => i_clk,
nrst => w_bus_nrst,
i_irqs => irq_pins,
o_cfg => slv_cfg(CFG_BUS0_XSLV_IRQCTRL),
i_axi => axisi(CFG_BUS0_XSLV_IRQCTRL),
o_axi => axiso(CFG_BUS0_XSLV_IRQCTRL),
o_irq_meip => w_ext_irq
);
--! @brief Timers with the AXI4 interface.
--! @details Map address:
--! 0x80005000..0x80005fff (4 KB total)
gptmr0 : axi4_gptimers generic map (
async_reset => CFG_ASYNC_RESET,
xaddr => 16#80005#,
xmask => 16#fffff#,
xirq => CFG_IRQ_GPTIMERS,
tmr_total => 2
) port map (
clk => i_clk,
nrst => w_glob_nrst,
cfg => slv_cfg(CFG_BUS0_XSLV_GPTIMERS),
i_axi => axisi(CFG_BUS0_XSLV_GPTIMERS),
o_axi => axiso(CFG_BUS0_XSLV_GPTIMERS),
o_pwm => o_pwm,
o_irq => irq_pins(CFG_IRQ_GPTIMERS)
);
--! @brief GNSS Sub-System with the AXI4 interface.
--! @details Map address:
--! 0x80008000..0x8000ffff (32 KB total)
--!
--! 0x80008000..0x80008fff (4 KB total) RF Controller
--! 0x80009000..0x80009fff (4 KB total) Engine
--! 0x8000a000..0x8000afff (4 KB total) GPS FSE
gnss_ena : if CFG_GNSS_SS_ENA generate
gnss0 : gnss_ss generic map (
async_reset => CFG_ASYNC_RESET,
tech => CFG_MEMTECH,
xaddr => 16#80008#,
xmask => 16#FFFF8#,
xirq => CFG_IRQ_GNSSENGINE
) port map (
i_nrst => w_glob_nrst,
i_clk_bus => i_clk,
i_clk_adc => i_clk_adc,
i_gps_I => i_gps_I,
i_gps_Q => i_gps_Q,
i_glo_I => i_glo_I,
i_glo_Q => i_glo_Q,
o_pps => o_pps,
i_gps_ld => i_gps_ld,
i_glo_ld => i_glo_ld,
o_max_sclk => o_max_sclk,
o_max_sdata => o_max_sdata,
o_max_ncs => o_max_ncs,
i_antext_stat => i_antext_stat,
i_antext_detect => i_antext_detect,
o_antext_ena => o_antext_ena,
o_antint_contr => o_antint_contr,
o_cfg => slv_cfg(CFG_BUS0_XSLV_GNSS_SS),
i_axi => axisi(CFG_BUS0_XSLV_GNSS_SS),
o_axi => axiso(CFG_BUS0_XSLV_GNSS_SS),
o_irq => irq_pins(CFG_IRQ_GNSSENGINE)
);
end generate;
gnss_dis : if not CFG_GNSS_SS_ENA generate
axiso(CFG_BUS0_XSLV_GNSS_SS) <= axi4_slave_out_none;
slv_cfg(CFG_BUS0_XSLV_GNSS_SS) <= axi4_slave_config_none;
irq_pins(CFG_IRQ_GNSSENGINE) <= '0';
end generate;
--! @brief Ethernet MAC with the AXI4 interface.
--! @details Map address:
--! 0x80040000..0x8007ffff (256 KB total)
--! EDCL IP: 192.168.1.51 = C0.A8.01.33
eth0_ena : if CFG_ETHERNET_ENABLE generate
eth_i.tx_clk <= i_etx_clk;
eth_i.rx_clk <= i_erx_clk;
eth_i.rxd <= i_erxd;
eth_i.rx_dv <= i_erx_dv;
eth_i.rx_er <= i_erx_er;
eth_i.rx_col <= i_erx_col;
eth_i.rx_crs <= i_erx_crs;
eth_i.mdint <= i_emdint;
eth_i.mdio_i <= i_eth_mdio;
eth_i.gtx_clk <= i_eth_gtx_clk;
mac0 : grethaxi generic map (
xaddr => 16#80040#,
xmask => 16#FFFC0#,
xirq => CFG_IRQ_ETHMAC,
memtech => CFG_MEMTECH,
mdcscaler => 60, --! System Bus clock in MHz
enable_mdio => 1,
fifosize => 16,
nsync => 1,
edcl => 1,
edclbufsz => 16,
macaddrh => 16#20789#,
macaddrl => 16#123#,
ipaddrh => 16#C0A8#,
ipaddrl => 16#0033#,
phyrstadr => 7,
enable_mdint => 1,
maxsize => 1518
) port map (
rst => w_glob_nrst,
clk => i_clk,
msti => aximi(CFG_BUS0_XMST_ETHMAC),
msto => aximo(CFG_BUS0_XMST_ETHMAC),
mstcfg => mst_cfg(CFG_BUS0_XMST_ETHMAC),
msto2 => open, -- EDCL separate access is disabled
mstcfg2 => open, -- EDCL separate access is disabled
slvi => axisi(CFG_BUS0_XSLV_ETHMAC),
slvo => axiso(CFG_BUS0_XSLV_ETHMAC),
slvcfg => slv_cfg(CFG_BUS0_XSLV_ETHMAC),
ethi => eth_i,
etho => eth_o,
irq => irq_pins(CFG_IRQ_ETHMAC)
);
end generate;
--! Ethernet disabled
eth0_dis : if not CFG_ETHERNET_ENABLE generate
slv_cfg(CFG_BUS0_XSLV_ETHMAC) <= axi4_slave_config_none;
axiso(CFG_BUS0_XSLV_ETHMAC) <= axi4_slave_out_none;
mst_cfg(CFG_BUS0_XMST_ETHMAC) <= axi4_master_config_none;
aximo(CFG_BUS0_XMST_ETHMAC) <= axi4_master_out_none;
irq_pins(CFG_IRQ_ETHMAC) <= '0';
eth_i.gtx_clk <= '0';
eth_o <= eth_out_none;
end generate;
o_etxd <= eth_o.txd;
o_etx_en <= eth_o.tx_en;
o_etx_er <= eth_o.tx_er;
o_emdc <= eth_o.mdc;
o_eth_mdio <= eth_o.mdio_o;
o_eth_mdio_oe <= eth_o.mdio_oe;
o_erstn <= w_glob_nrst;
--! @brief Plug'n'Play controller of the current configuration with the
--! AXI4 interface.
--! @details Map address:
--! 0xfffff000..0xffffffff (4 KB total)
pnp0 : axi4_pnp generic map (
async_reset => CFG_ASYNC_RESET,
xaddr => 16#fffff#,
xmask => 16#fffff#,
tech => CFG_MEMTECH,
hw_id => CFG_HW_ID
) port map (
sys_clk => i_clk,
adc_clk => '0',
nrst => w_glob_nrst,
mstcfg => mst_cfg,
slvcfg => slv_cfg,
cfg => slv_cfg(CFG_BUS0_XSLV_PNP),
i => axisi(CFG_BUS0_XSLV_PNP),
o => axiso(CFG_BUS0_XSLV_PNP),
-- OTP Timing control
i_otp_busy => w_otp_busy,
o_otp_cfg_rsetup => wb_otp_cfg_rsetup,
o_otp_cfg_wadrsetup => wb_otp_cfg_wadrsetup,
o_otp_cfg_wactive => wb_otp_cfg_wactive,
o_otp_cfg_whold => wb_otp_cfg_whold
);
end arch_riscv_soc;
|
apache-2.0
|
sergeykhbr/riscv_vhdl
|
vhdl/rtl/misclib/tap_jtag.vhd
|
1
|
10868
|
--!
--! Copyright 2018 Sergey Khabarov, [email protected]
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS,
--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--! See the License for the specific language governing permissions and
--! limitations under the License.
--!
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
--! AMBA system bus specific library.
library ambalib;
--! AXI4 configuration constants.
use ambalib.types_amba4.all;
library misclib;
use misclib.types_misc.all;
entity tap_jtag is
port (
nrst : in std_logic;
clk : in std_logic;
i_tck : in std_logic; -- in: Test Clock
i_ntrst : in std_logic;
i_tms : in std_logic; -- in: Test Mode State
i_tdi : in std_logic; -- in: Test Data Input
o_tdo : out std_logic; -- out: Test Data Output
o_jtag_vref : out std_logic;
-- DMI interface
o_dmi_req_valid : out std_logic;
i_dmi_req_ready : in std_logic;
o_dmi_write : out std_logic;
o_dmi_addr : out std_logic_vector(6 downto 0);
o_dmi_wdata : out std_logic_vector(31 downto 0);
i_dmi_resp_valid : in std_logic;
o_dmi_resp_ready : out std_logic;
i_dmi_rdata : in std_logic_vector(31 downto 0)
);
end;
architecture rtl of tap_jtag is
constant ADDBITS : integer := 10;
type dmi_req_state_type is (
DMIREQ_IDLE,
DMIREQ_SYNC_START,
DMIREQ_START,
DMIREQ_WAIT_READ_RESP,
DMIREQ_SYNC_RESP
);
type tckpreg_type is record
dmishft : std_logic_vector(40 downto 0);
datashft : std_logic_vector(32 downto 0);
done_sync : std_ulogic;
prun : std_ulogic;
inshift : std_ulogic;
holdn : std_ulogic;
end record;
type tcknreg_type is record
run: std_ulogic;
done_sync1: std_ulogic;
qual_rdata: std_ulogic;
addrlo : std_logic_vector(ADDBITS-1 downto 2);
data : std_logic_vector(32 downto 0);
end record;
type axireg_type is record
run_sync: std_logic_vector(1 downto 0);
qual_dreg: std_ulogic;
qual_dmireg: std_ulogic;
dmireg: std_logic_vector(40 downto 0);
dreg: std_logic_vector(31 downto 0);
done: std_ulogic;
dmi_req_state : dmi_req_state_type;
end record;
signal ar, arin : axireg_type;
signal tpr, tprin: tckpreg_type;
signal tnr, tnrin: tcknreg_type;
signal qual_rdata, rdataq: std_logic_vector(31 downto 0);
signal qual_dreg, dregq: std_logic_vector(31 downto 0);
signal qual_dmireg, dmiregq: std_logic_vector(40 downto 0);
signal dma_response : dma_response_type;
signal tapi_tdo : std_logic;
signal tapo_rst : std_logic;
signal tapo_tck : std_logic;
signal tapo_tdi : std_logic;
signal tapo_inst : std_logic_vector(4 downto 0);
signal tapo_capt : std_logic;
signal tapo_shft : std_logic;
signal tapo_upd : std_logic;
signal tapo_xsel1 : std_logic;
signal tapo_xsel2 : std_logic;
attribute syn_keep: boolean;
attribute syn_keep of rdataq : signal is true;
attribute syn_keep of dregq : signal is true;
attribute syn_keep of dmiregq : signal is true;
component dcom_jtag is generic (
id : std_logic_vector(31 downto 0) := X"01040093"
);
port (
rst : in std_ulogic;
tck : in std_ulogic;
tms : in std_ulogic;
tdi : in std_ulogic;
tdo : out std_ulogic;
tapi_tdo : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_inst : out std_logic_vector(4 downto 0);
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end component;
begin
qual_rdata <= (others => tnr.qual_rdata);
rdataq <= not (ar.dreg(31 downto 0) and qual_rdata(31 downto 0));
qual_dreg <= (others => ar.qual_dreg);
dregq <= not (tnr.data(31 downto 0) and qual_dreg(31 downto 0));
qual_dmireg <= (others => ar.qual_dmireg);
dmiregq <= not (tpr.dmishft and qual_dmireg);
comb : process (nrst, ar, dma_response,
tapo_tck, tapo_tdi, tapo_inst, tapo_rst, tapo_capt, tapo_shft, tapo_upd, tapo_xsel1, tapo_xsel2,
i_dmi_req_ready, i_dmi_resp_valid, i_dmi_rdata,
tpr, tnr, dmiregq, dregq, rdataq)
variable av : axireg_type;
variable tpv : tckpreg_type;
variable tnv : tcknreg_type;
variable dsel : std_ulogic;
variable vtapi_tdo : std_logic;
variable write, seq : std_ulogic;
variable v_dmi_req_valid : std_logic;
variable v_dmi_write : std_logic;
variable vb_dmi_addr : std_logic_vector(6 downto 0);
variable vb_dmi_wdata : std_logic_vector(31 downto 0);
variable vb_dmi_resp_ready : std_logic;
variable wb_dma_response : dma_response_type;
begin
av := ar;
tpv := tpr;
tnv := tnr;
---------------------------------------------------------------------------
-- TCK side logic
---------------------------------------------------------------------------
dsel := tapo_xsel2;
vtapi_tdo := tpr.dmishft(0);
if dsel='1' then
vtapi_tdo := tpr.datashft(0) and tpr.holdn;
end if;
write := tpr.dmishft(34);
seq := tpr.datashft(32);
-- Sync regs using alternating phases
tnv.done_sync1 := ar.done;
tpv.done_sync := tnr.done_sync1;
-- Data CDC
if tnr.qual_rdata='1' then
-- tpv.datashft(32 downto 0) := '1' & (not rdataq);
tpv.dmishft(33 downto 0) := (not rdataq) & "00"; -- 00=status OK
end if;
-- Track whether we're in the middle of shifting
if tapo_shft = '1' then
tpv.inshift:='1';
end if;
if tapo_upd = '1' then
tpv.inshift:='0';
end if;
if tapo_shft = '1' then
if tapo_xsel1 = '1' and tpr.prun='0' then
tpv.dmishft(40 downto 0) := tapo_tdi & tpr.dmishft(40 downto 1);
end if;
if dsel = '1' and tpr.holdn='1' then
tpv.datashft(32 downto 0) := tapo_tdi & tpr.datashft(32 downto 1);
end if;
end if;
if tnr.run='0' then
tpv.holdn := '1';
end if;
tpv.prun := tnr.run;
if tpr.prun='0' then
tnv.qual_rdata := '0';
if tapo_shft = '0' and tapo_upd = '1' then
if dsel = '1' then
tnv.data := tpr.datashft;
end if;
if tapo_xsel1 = '1' then
tpv.holdn := '0';
tnv.run := '1';
end if;
if (dsel and (write or (not write and seq))) = '1' then
tnv.run := '1';
if (seq and not write) = '1' then
tnv.addrlo := tnr.addrlo + 1;
tpv.holdn := '0';
end if;
end if;
end if;
else
if tpr.done_sync='1' and tpv.inshift='0' then
tnv.run := '0';
tnv.qual_rdata := '1';
end if;
end if;
if tapo_rst = '1' then
tpv.inshift := '0';
tnv.run := '0';
end if;
av.qual_dreg := '0';
av.qual_dmireg := '0';
v_dmi_req_valid := '0';
v_dmi_write := '0';
vb_dmi_addr := (others => '0');
vb_dmi_wdata := (others => '0');
vb_dmi_resp_ready := '0';
--! DMA control
case ar.dmi_req_state is
when DMIREQ_IDLE =>
if ar.run_sync(0) = '1' then
av.qual_dreg := '1';
av.qual_dmireg := '1';
av.dmi_req_state := DMIREQ_SYNC_START;
end if;
when DMIREQ_SYNC_START =>
av.dmi_req_state := DMIREQ_START;
when DMIREQ_START =>
v_dmi_req_valid := ar.dmireg(1) or ar.dmireg(0);
v_dmi_write := ar.dmireg(1);
vb_dmi_addr := ar.dmireg(40 downto 34);
vb_dmi_wdata := ar.dmireg(33 downto 2);
if v_dmi_req_valid = '0' then
-- empty request 'nop'
av.done := '1';
av.dmi_req_state := DMIREQ_SYNC_RESP;
elsif i_dmi_req_ready = '1' then
av.dmi_req_state := DMIREQ_WAIT_READ_RESP;
end if;
when DMIREQ_WAIT_READ_RESP =>
vb_dmi_resp_ready := '1';
if i_dmi_resp_valid = '1' then
av.done := '1';
av.dreg := i_dmi_rdata(31 downto 0);
av.dmi_req_state := DMIREQ_SYNC_RESP;
end if;
when DMIREQ_SYNC_RESP =>
if ar.run_sync(0) = '0' then
av.done := '0';
av.dmi_req_state := DMIREQ_IDLE;
end if;
when others =>
end case;
-- Sync regs and CDC transfer
av.run_sync := tnr.run & ar.run_sync(1);
if ar.qual_dreg='1' then
av.dreg := not dregq;
end if;
if ar.qual_dmireg='1' then
av.dmireg := not dmiregq;
end if;
if (nrst = '0') then
av.dmi_req_state := DMIREQ_IDLE;
av.qual_dreg := '0';
av.qual_dmireg := '0';
av.done := '0';
av.dmireg := (others => '0');
av.dreg := (others => '0');
end if;
tprin <= tpv;
tnrin <= tnv;
arin <= av;
tapi_tdo <= vtapi_tdo;
o_dmi_req_valid <= v_dmi_req_valid;
o_dmi_write <= v_dmi_write;
o_dmi_addr <= vb_dmi_addr;
o_dmi_wdata <= vb_dmi_wdata;
o_dmi_resp_ready <= vb_dmi_resp_ready;
end process;
o_jtag_vref <= '1';
jtagcom0 : dcom_jtag generic map (
id => X"00000001"
) port map (
rst => nrst,
tck => i_tck,
tms => i_tms,
tdi => i_tdi,
tdo => o_tdo,
tapi_tdo => tapi_tdo,
tapo_tck => tapo_tck,
tapo_tdi => tapo_tdi,
tapo_inst => tapo_inst,
tapo_rst => tapo_rst,
tapo_capt => tapo_capt,
tapo_shft => tapo_shft,
tapo_upd => tapo_upd,
tapo_xsel1 => tapo_xsel1,
tapo_xsel2 => tapo_xsel2
);
axireg : process(clk)
begin
if rising_edge(clk) then
ar <= arin;
end if;
end process;
tckpreg: process(tapo_tck, tapo_rst)
begin
if rising_edge(tapo_tck) then
tpr <= tprin;
end if;
if tapo_rst = '1' then
tpr.dmishft <= (others => '0');
tpr.datashft <= (others => '0');
tpr.done_sync <= '0';
tpr.prun <= '0';
tpr.inshift <= '0';
tpr.holdn <= '1';
end if;
end process;
tcknreg: process(tapo_tck, tapo_rst)
begin
if falling_edge(tapo_tck) then
tnr <= tnrin;
end if;
if tapo_rst = '1' then
tnr.run <= '0';
tnr.done_sync1 <= '0';
tnr.qual_rdata <= '0';
tnr.addrlo <= (others => '0');
tnr.data <= (others => '0');
end if;
end process;
end;
|
apache-2.0
|
rdsalemi/uvmprimer
|
10_An_Object_Oriented_Testbench/tinyalu_dut/tinyalu.vhd
|
24
|
4250
|
-- Copyright 2013 Ray Salemi
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity tinyalu is
port(
A : in unsigned ( 7 downto 0 );
B : in unsigned ( 7 downto 0 );
clk : in std_logic;
op : in std_logic_vector ( 2 downto 0 );
reset_n : in std_logic;
start : in std_logic;
done : out std_logic;
result : out unsigned ( 15 downto 0 )
);
-- Declarations
end tinyalu;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
library work;
architecture rtl of tinyalu is
-- Architecture declarations
-- Internal signal declarations
signal done_aax : std_logic;
signal done_mult : std_logic;
signal result_aax : unsigned(15 downto 0);
signal result_mult : unsigned(15 downto 0);
signal start_single : std_logic; -- Start signal for single cycle ops
signal start_mult : std_logic; -- start signal for multiply
-- Implicit buffer signal declarations
signal done_internal : std_logic;
-- Component Declarations
component single_cycle
port (
A : in unsigned ( 7 downto 0 );
B : in unsigned ( 7 downto 0 );
clk : in std_logic;
op : in std_logic_vector ( 2 downto 0 );
reset_n : in std_logic;
start : in std_logic;
done_aax : out std_logic;
result_aax : out unsigned (15 downto 0)
);
end component;
component three_cycle
port (
A : in unsigned ( 7 downto 0 );
B : in unsigned ( 7 downto 0 );
clk : in std_logic;
reset_n : in std_logic;
start : in std_logic;
done_mult : out std_logic;
result_mult : out unsigned (15 downto 0)
);
end component;
-- Optional embedded configurations
-- pragma synthesis_off
for all : single_cycle use entity work.single_cycle;
for all : three_cycle use entity work.three_cycle;
-- pragma synthesis_on
begin
-- purpose: This block shunts the start signal to the correct block.
-- The multiply only sees the start signal when op(2) is '1'
-- type : combinational
-- inputs : op(2),start
-- outputs: start_mult, start_single
start_demux: process (op(2),start)
begin -- process start_demux
case op(2) is
when '0' =>
start_single <= start;
start_mult <= '0';
when '1' =>
start_single <= '0';
start_mult <= start;
when others => null;
end case;
end process start_demux;
result_mux : process(result_aax, result_mult, op)
begin
case op(2) is
when '0' => result <= result_aax;
when '1' => result <= result_mult;
when others => result <= (others => 'X');
end case;
end process result_mux;
done_mux : process(done_aax, done_mult, op)
begin
case op(2) is
when '0' => done_internal <= done_aax;
when '1' => done_internal <= done_mult;
when others => done_internal <= 'X';
end case;
end process done_mux;
-- Instance port mappings.
add_and_xor : single_cycle
port map (
A => A,
B => B,
clk => clk,
op => op,
reset_n => reset_n,
start => start_single,
done_aax => done_aax,
result_aax => result_aax
);
mult : three_cycle
port map (
A => A,
B => B,
clk => clk,
reset_n => reset_n,
start => start_mult,
done_mult => done_mult,
result_mult => result_mult
);
-- Implicit buffered output assignments
done <= done_internal;
end rtl;
|
apache-2.0
|
ntb-ch/cb20
|
FPGA_Designs/mpu9250/cb20/synthesis/cb20_altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo.vhd
|
1
|
8099
|
-- cb20_altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo.vhd
-- Generated using ACDS version 13.0sp1 232 at 2016.10.11.08:07:37
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity cb20_altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo is
generic (
SYMBOLS_PER_BEAT : integer := 1;
BITS_PER_SYMBOL : integer := 34;
FIFO_DEPTH : integer := 2;
CHANNEL_WIDTH : integer := 0;
ERROR_WIDTH : integer := 0;
USE_PACKETS : integer := 0;
USE_FILL_LEVEL : integer := 0;
EMPTY_LATENCY : integer := 0;
USE_MEMORY_BLOCKS : integer := 0;
USE_STORE_FORWARD : integer := 0;
USE_ALMOST_FULL_IF : integer := 0;
USE_ALMOST_EMPTY_IF : integer := 0
);
port (
clk : in std_logic := '0'; -- clk.clk
reset : in std_logic := '0'; -- clk_reset.reset
in_data : in std_logic_vector(33 downto 0) := (others => '0'); -- in.data
in_valid : in std_logic := '0'; -- .valid
in_ready : out std_logic; -- .ready
out_data : out std_logic_vector(33 downto 0); -- out.data
out_valid : out std_logic; -- .valid
out_ready : in std_logic := '0'; -- .ready
almost_empty_data : out std_logic;
almost_full_data : out std_logic;
csr_address : in std_logic_vector(1 downto 0) := (others => '0');
csr_read : in std_logic := '0';
csr_readdata : out std_logic_vector(31 downto 0);
csr_write : in std_logic := '0';
csr_writedata : in std_logic_vector(31 downto 0) := (others => '0');
in_channel : in std_logic := '0';
in_empty : in std_logic := '0';
in_endofpacket : in std_logic := '0';
in_error : in std_logic := '0';
in_startofpacket : in std_logic := '0';
out_channel : out std_logic;
out_empty : out std_logic;
out_endofpacket : out std_logic;
out_error : out std_logic;
out_startofpacket : out std_logic
);
end entity cb20_altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo;
architecture rtl of cb20_altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo is
component altera_avalon_sc_fifo is
generic (
SYMBOLS_PER_BEAT : integer := 1;
BITS_PER_SYMBOL : integer := 8;
FIFO_DEPTH : integer := 16;
CHANNEL_WIDTH : integer := 0;
ERROR_WIDTH : integer := 0;
USE_PACKETS : integer := 0;
USE_FILL_LEVEL : integer := 0;
EMPTY_LATENCY : integer := 3;
USE_MEMORY_BLOCKS : integer := 1;
USE_STORE_FORWARD : integer := 0;
USE_ALMOST_FULL_IF : integer := 0;
USE_ALMOST_EMPTY_IF : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
in_data : in std_logic_vector(33 downto 0) := (others => 'X'); -- data
in_valid : in std_logic := 'X'; -- valid
in_ready : out std_logic; -- ready
out_data : out std_logic_vector(33 downto 0); -- data
out_valid : out std_logic; -- valid
out_ready : in std_logic := 'X'; -- ready
csr_address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
csr_read : in std_logic := 'X'; -- read
csr_write : in std_logic := 'X'; -- write
csr_readdata : out std_logic_vector(31 downto 0); -- readdata
csr_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
almost_full_data : out std_logic; -- data
almost_empty_data : out std_logic; -- data
in_startofpacket : in std_logic := 'X'; -- startofpacket
in_endofpacket : in std_logic := 'X'; -- endofpacket
out_startofpacket : out std_logic; -- startofpacket
out_endofpacket : out std_logic; -- endofpacket
in_empty : in std_logic := 'X'; -- empty
out_empty : out std_logic; -- empty
in_error : in std_logic := 'X'; -- error
out_error : out std_logic; -- error
in_channel : in std_logic := 'X'; -- channel
out_channel : out std_logic -- channel
);
end component altera_avalon_sc_fifo;
begin
altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo : component altera_avalon_sc_fifo
generic map (
SYMBOLS_PER_BEAT => SYMBOLS_PER_BEAT,
BITS_PER_SYMBOL => BITS_PER_SYMBOL,
FIFO_DEPTH => FIFO_DEPTH,
CHANNEL_WIDTH => CHANNEL_WIDTH,
ERROR_WIDTH => ERROR_WIDTH,
USE_PACKETS => USE_PACKETS,
USE_FILL_LEVEL => USE_FILL_LEVEL,
EMPTY_LATENCY => EMPTY_LATENCY,
USE_MEMORY_BLOCKS => USE_MEMORY_BLOCKS,
USE_STORE_FORWARD => USE_STORE_FORWARD,
USE_ALMOST_FULL_IF => USE_ALMOST_FULL_IF,
USE_ALMOST_EMPTY_IF => USE_ALMOST_EMPTY_IF
)
port map (
clk => clk, -- clk.clk
reset => reset, -- clk_reset.reset
in_data => in_data, -- in.data
in_valid => in_valid, -- .valid
in_ready => in_ready, -- .ready
out_data => out_data, -- out.data
out_valid => out_valid, -- .valid
out_ready => out_ready, -- .ready
csr_address => "00", -- (terminated)
csr_read => '0', -- (terminated)
csr_write => '0', -- (terminated)
csr_readdata => open, -- (terminated)
csr_writedata => "00000000000000000000000000000000", -- (terminated)
almost_full_data => open, -- (terminated)
almost_empty_data => open, -- (terminated)
in_startofpacket => '0', -- (terminated)
in_endofpacket => '0', -- (terminated)
out_startofpacket => open, -- (terminated)
out_endofpacket => open, -- (terminated)
in_empty => '0', -- (terminated)
out_empty => open, -- (terminated)
in_error => '0', -- (terminated)
out_error => open, -- (terminated)
in_channel => '0', -- (terminated)
out_channel => open -- (terminated)
);
end architecture rtl; -- of cb20_altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo
|
apache-2.0
|
ntb-ch/cb20
|
FPGA_Designs/mpu9250/cb20/synthesis/cb20_info_device_0_avalon_slave_translator.vhd
|
1
|
14655
|
-- cb20_info_device_0_avalon_slave_translator.vhd
-- Generated using ACDS version 13.0sp1 232 at 2016.10.12.10:12:44
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity cb20_info_device_0_avalon_slave_translator is
generic (
AV_ADDRESS_W : integer := 5;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 1;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 17;
UAV_BURSTCOUNT_W : integer := 3;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 0;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 1;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := '0'; -- clk.clk
reset : in std_logic := '0'; -- reset.reset
uav_address : in std_logic_vector(16 downto 0) := (others => '0'); -- avalon_universal_slave_0.address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => '0'); -- .burstcount
uav_read : in std_logic := '0'; -- .read
uav_write : in std_logic := '0'; -- .write
uav_waitrequest : out std_logic; -- .waitrequest
uav_readdatavalid : out std_logic; -- .readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => '0'); -- .byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- .readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
uav_lock : in std_logic := '0'; -- .lock
uav_debugaccess : in std_logic := '0'; -- .debugaccess
av_address : out std_logic_vector(4 downto 0); -- avalon_anti_slave_0.address
av_write : out std_logic; -- .write
av_read : out std_logic; -- .read
av_readdata : in std_logic_vector(31 downto 0) := (others => '0'); -- .readdata
av_writedata : out std_logic_vector(31 downto 0); -- .writedata
av_byteenable : out std_logic_vector(3 downto 0); -- .byteenable
av_waitrequest : in std_logic := '0'; -- .waitrequest
av_beginbursttransfer : out std_logic;
av_begintransfer : out std_logic;
av_burstcount : out std_logic_vector(0 downto 0);
av_chipselect : out std_logic;
av_clken : out std_logic;
av_debugaccess : out std_logic;
av_lock : out std_logic;
av_outputenable : out std_logic;
av_readdatavalid : in std_logic := '0';
av_response : in std_logic_vector(1 downto 0) := (others => '0');
av_writebyteenable : out std_logic_vector(3 downto 0);
av_writeresponserequest : out std_logic;
av_writeresponsevalid : in std_logic := '0';
uav_clken : in std_logic := '0';
uav_response : out std_logic_vector(1 downto 0);
uav_writeresponserequest : in std_logic := '0';
uav_writeresponsevalid : out std_logic
);
end entity cb20_info_device_0_avalon_slave_translator;
architecture rtl of cb20_info_device_0_avalon_slave_translator is
component altera_merlin_slave_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(16 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(4 downto 0); -- address
av_write : out std_logic; -- write
av_read : out std_logic; -- read
av_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
av_writedata : out std_logic_vector(31 downto 0); -- writedata
av_byteenable : out std_logic_vector(3 downto 0); -- byteenable
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_begintransfer : out std_logic; -- begintransfer
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_writebyteenable : out std_logic_vector(3 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
av_chipselect : out std_logic; -- chipselect
av_clken : out std_logic; -- clken
uav_clken : in std_logic := 'X'; -- clken
av_debugaccess : out std_logic; -- debugaccess
av_outputenable : out std_logic; -- outputenable
uav_response : out std_logic_vector(1 downto 0); -- response
av_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response
uav_writeresponserequest : in std_logic := 'X'; -- writeresponserequest
uav_writeresponsevalid : out std_logic; -- writeresponsevalid
av_writeresponserequest : out std_logic; -- writeresponserequest
av_writeresponsevalid : in std_logic := 'X' -- writeresponsevalid
);
end component altera_merlin_slave_translator;
begin
info_device_0_avalon_slave_translator : component altera_merlin_slave_translator
generic map (
AV_ADDRESS_W => AV_ADDRESS_W,
AV_DATA_W => AV_DATA_W,
UAV_DATA_W => UAV_DATA_W,
AV_BURSTCOUNT_W => AV_BURSTCOUNT_W,
AV_BYTEENABLE_W => AV_BYTEENABLE_W,
UAV_BYTEENABLE_W => UAV_BYTEENABLE_W,
UAV_ADDRESS_W => UAV_ADDRESS_W,
UAV_BURSTCOUNT_W => UAV_BURSTCOUNT_W,
AV_READLATENCY => AV_READLATENCY,
USE_READDATAVALID => USE_READDATAVALID,
USE_WAITREQUEST => USE_WAITREQUEST,
USE_UAV_CLKEN => USE_UAV_CLKEN,
USE_READRESPONSE => USE_READRESPONSE,
USE_WRITERESPONSE => USE_WRITERESPONSE,
AV_SYMBOLS_PER_WORD => AV_SYMBOLS_PER_WORD,
AV_ADDRESS_SYMBOLS => AV_ADDRESS_SYMBOLS,
AV_BURSTCOUNT_SYMBOLS => AV_BURSTCOUNT_SYMBOLS,
AV_CONSTANT_BURST_BEHAVIOR => AV_CONSTANT_BURST_BEHAVIOR,
UAV_CONSTANT_BURST_BEHAVIOR => UAV_CONSTANT_BURST_BEHAVIOR,
AV_REQUIRE_UNALIGNED_ADDRESSES => AV_REQUIRE_UNALIGNED_ADDRESSES,
CHIPSELECT_THROUGH_READLATENCY => CHIPSELECT_THROUGH_READLATENCY,
AV_READ_WAIT_CYCLES => AV_READ_WAIT_CYCLES,
AV_WRITE_WAIT_CYCLES => AV_WRITE_WAIT_CYCLES,
AV_SETUP_WAIT_CYCLES => AV_SETUP_WAIT_CYCLES,
AV_DATA_HOLD_CYCLES => AV_DATA_HOLD_CYCLES
)
port map (
clk => clk, -- clk.clk
reset => reset, -- reset.reset
uav_address => uav_address, -- avalon_universal_slave_0.address
uav_burstcount => uav_burstcount, -- .burstcount
uav_read => uav_read, -- .read
uav_write => uav_write, -- .write
uav_waitrequest => uav_waitrequest, -- .waitrequest
uav_readdatavalid => uav_readdatavalid, -- .readdatavalid
uav_byteenable => uav_byteenable, -- .byteenable
uav_readdata => uav_readdata, -- .readdata
uav_writedata => uav_writedata, -- .writedata
uav_lock => uav_lock, -- .lock
uav_debugaccess => uav_debugaccess, -- .debugaccess
av_address => av_address, -- avalon_anti_slave_0.address
av_write => av_write, -- .write
av_read => av_read, -- .read
av_readdata => av_readdata, -- .readdata
av_writedata => av_writedata, -- .writedata
av_byteenable => av_byteenable, -- .byteenable
av_waitrequest => av_waitrequest, -- .waitrequest
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_chipselect => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open, -- (terminated)
uav_response => open, -- (terminated)
av_response => "00", -- (terminated)
uav_writeresponserequest => '0', -- (terminated)
uav_writeresponsevalid => open, -- (terminated)
av_writeresponserequest => open, -- (terminated)
av_writeresponsevalid => '0' -- (terminated)
);
end architecture rtl; -- of cb20_info_device_0_avalon_slave_translator
|
apache-2.0
|
ntb-ch/cb20
|
FPGA_Designs/watchdog/cb20/synthesis/submodules/ppwa.m.vhd
|
2
|
5130
|
-------------------------------------------------------------------------------
-- ____ _____ __ __ ________ _______
-- | | \ \ | \ | | |__ __| | __ \
-- |____| \____\ | \| | | | | |__> )
-- ____ ____ | |\ \ | | | | __ <
-- | | | | | | \ | | | | |__> )
-- |____| |____| |__| \__| |__| |_______/
--
-- NTB University of Applied Sciences in Technology
--
-- Campus Buchs - Werdenbergstrasse 4 - 9471 Buchs - Switzerland
-- Campus Waldau - Schoenauweg 4 - 9013 St. Gallen - Switzerland
--
-- Web http://www.ntb.ch Tel. +41 81 755 33 11
--
-------------------------------------------------------------------------------
-- Copyright 2013 NTB University of Applied Sciences in Technology
-------------------------------------------------------------------------------
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.numeric_std.ALL;
-------------------------------------------------------------------------------
-- PACKAGE DEFINITION
-------------------------------------------------------------------------------
PACKAGE ppwa_pkg IS
COMPONENT ppwa IS
GENERIC(
counter_resolution : INTEGER := 32
);
PORT(
isl_clk : IN STD_LOGIC;
isl_reset_n : IN STD_LOGIC;
isl_measure_signal : IN STD_LOGIC;
ousig_period_count : OUT UNSIGNED(counter_resolution - 1 DOWNTO 0);
ousig_hightime_count : OUT UNSIGNED(counter_resolution - 1 DOWNTO 0)
);
END COMPONENT ppwa;
END PACKAGE ppwa_pkg;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.numeric_std.ALL;
USE work.ppwa_pkg.ALL;
-------------------------------------------------------------------------------
-- ENTITIY
-------------------------------------------------------------------------------
ENTITY ppwa IS
GENERIC(
counter_resolution : INTEGER := 32
);
PORT(
isl_clk : IN STD_LOGIC;
isl_reset_n : IN STD_LOGIC;
isl_measure_signal : IN STD_LOGIC;
ousig_period_count : OUT UNSIGNED(counter_resolution - 1 DOWNTO 0);
ousig_hightime_count : OUT UNSIGNED(counter_resolution - 1 DOWNTO 0)
);
END ENTITY ppwa;
-------------------------------------------------------------------------------
-- ARCHITECTURE
-------------------------------------------------------------------------------
ARCHITECTURE rtl OF ppwa IS
TYPE t_internal_register IS RECORD
-- synchronize signals
sl_measure_signal_1 : STD_LOGIC;
sl_measure_signal_2 : STD_LOGIC;
usig_counter_running : UNSIGNED(counter_resolution - 1 DOWNTO 0);
usig_counter_period : UNSIGNED(counter_resolution - 1 DOWNTO 0);
usig_counter_high : UNSIGNED(counter_resolution - 1 DOWNTO 0);
END RECORD;
SIGNAL ri, ri_next : t_internal_register;
BEGIN
--------------------------------------------
-- combinatorial process
--------------------------------------------
comb_process: PROCESS(ri, isl_reset_n,isl_measure_signal)
VARIABLE vi: t_internal_register;
BEGIN
-- keep variables stable
vi:=ri;
-- input buffer, to synchronize asynchronous inputs
vi.sl_measure_signal_2 := vi.sl_measure_signal_1;
vi.sl_measure_signal_1 := isl_measure_signal;
vi.usig_counter_running := vi.usig_counter_running + 1;
IF vi.sl_measure_signal_2 = '0' AND vi.sl_measure_signal_1 = '1' THEN --rising edge
vi.usig_counter_period := vi.usig_counter_running;
vi.usig_counter_running := (OTHERS => '0');
ELSIF vi.sl_measure_signal_2 = '1' AND vi.sl_measure_signal_1 = '0' THEN --falling edge
vi.usig_counter_high := vi.usig_counter_running;
END IF;
-- reset
IF isl_reset_n = '0' THEN
vi.usig_counter_period := (OTHERS => '0');
vi.usig_counter_high := (OTHERS => '0');
vi.usig_counter_running := (OTHERS => '0');
END IF;
-- setting outputs
ri_next <= vi;
END PROCESS comb_process;
--------------------------------------------
-- registered process
--------------------------------------------
reg_process: PROCESS (isl_clk)
BEGIN
IF rising_edge(isl_clk) THEN
ri <= ri_next;
END IF;
END PROCESS reg_process;
--------------------------------------------
-- output assignment
--------------------------------------------
ousig_period_count <= ri.usig_counter_period;
ousig_hightime_count <= ri.usig_counter_high;
END ARCHITECTURE rtl;
|
apache-2.0
|
ntb-ch/cb20
|
FPGA_Designs/mpu9250/cb20/synthesis/submodules/adjustable_pwm.m.vhd
|
1
|
4099
|
-------------------------------------------------------------------------------
-- _________ _____ _____ ____ _____ ___ ____ --
-- |_ ___ | |_ _| |_ _| |_ \|_ _| |_ ||_ _| --
-- | |_ \_| | | | | | \ | | | |_/ / --
-- | _| | | _ | | | |\ \| | | __'. --
-- _| |_ _| |__/ | _| |_ _| |_\ |_ _| | \ \_ --
-- |_____| |________| |_____| |_____|\____| |____||____| --
-- --
-------------------------------------------------------------------------------
-- --
-- Adjustable PWM Signal Generator --
-- --
-------------------------------------------------------------------------------
-- Copyright 2014 NTB University of Applied Sciences in Technology --
-- --
-- Licensed under the Apache License, Version 2.0 (the "License"); --
-- you may not use this file except in compliance with the License. --
-- You may obtain a copy of the License at --
-- --
-- http://www.apache.org/licenses/LICENSE-2.0 --
-- --
-- Unless required by applicable law or agreed to in writing, software --
-- distributed under the License is distributed on an "AS IS" BASIS, --
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. --
-- See the License for the specific language governing permissions and --
-- limitations under the License. --
-------------------------------------------------------------------------------
-- Based on the PWM block of Marco Tinner from the AirBotOne project
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
PACKAGE adjustable_pwm_pkg IS
COMPONENT adjustable_pwm IS
GENERIC(frequency_resolution : INTEGER := 32);
PORT (
sl_clk : IN STD_LOGIC;
sl_reset_n : IN STD_LOGIC;
slv_frequency_divider : IN UNSIGNED(frequency_resolution-1 DOWNTO 0);
slv_ratio : IN UNSIGNED(frequency_resolution-1 DOWNTO 0);
sl_pwm : OUT STD_LOGIC
);
END COMPONENT adjustable_pwm;
END PACKAGE adjustable_pwm_pkg;
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE work.adjustable_pwm_pkg.ALL;
ENTITY adjustable_pwm IS
GENERIC(frequency_resolution : INTEGER := 32);
PORT (
sl_clk : IN STD_LOGIC;
sl_reset_n : IN STD_LOGIC;
slv_frequency_divider : IN UNSIGNED(frequency_resolution-1 DOWNTO 0); -- pwm frequency divider for example if this value is 2 the pwm output frequency is f_sl_clk/2
slv_ratio : IN UNSIGNED(frequency_resolution-1 DOWNTO 0); -- the high time part in clk cyles this value has alway to be smaller than the slv_frequency_divider
sl_pwm : OUT STD_LOGIC
);
END ENTITY adjustable_pwm;
ARCHITECTURE rtl OF adjustable_pwm IS
SIGNAL cycle_counter : UNSIGNED(frequency_resolution-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
proc : PROCESS (sl_reset_n,sl_clk)
BEGIN
IF sl_reset_n = '0' THEN
sl_pwm <= '0';
cycle_counter <= (OTHERS => '0');
ELSIF rising_edge(sl_clk) THEN
IF slv_ratio > slv_frequency_divider THEN
sl_pwm <= '0';
cycle_counter <= (OTHERS => '0');
ELSIF cycle_counter >= slv_frequency_divider THEN
sl_pwm <= '0';
cycle_counter <= (OTHERS => '0');
ELSIF cycle_counter < slv_ratio THEN
sl_pwm <= '1';
cycle_counter <= cycle_counter + 1;
ELSE
sl_pwm <= '0';
cycle_counter <= cycle_counter + 1;
END IF;
END IF;
END PROCESS proc;
END ARCHITECTURE rtl;
|
apache-2.0
|
ntb-ch/cb20
|
FPGA_Designs/watchdog/cb20/synthesis/submodules/watchdog.m.vhd
|
2
|
5319
|
-------------------------------------------------------------------------------
-- ____ _____ __ __ ________ _______
-- | | \ \ | \ | | |__ __| | __ \
-- |____| \____\ | \| | | | | |__> )
-- ____ ____ | |\ \ | | | | __ <
-- | | | | | | \ | | | | |__> )
-- |____| |____| |__| \__| |__| |_______/
--
-- NTB University of Applied Sciences in Technology
--
-- Campus Buchs - Werdenbergstrasse 4 - 9471 Buchs - Switzerland
-- Campus Waldau - Schoenauweg 4 - 9013 St. Gallen - Switzerland
--
-- Web http://www.ntb.ch Tel. +41 81 755 33 11
--
-------------------------------------------------------------------------------
-- Copyright 2013 NTB University of Applied Sciences in Technology
-------------------------------------------------------------------------------
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.numeric_std.ALL;
-------------------------------------------------------------------------------
-- PACKAGE DEFINITION
-------------------------------------------------------------------------------
PACKAGE watchdog_pkg IS
COMPONENT watchdog IS
GENERIC(
gi_counter_resolution : INTEGER := 32
);
PORT(
isl_clk : IN STD_LOGIC;
isl_reset_n : IN STD_LOGIC;
iusig_counter_set : IN UNSIGNED(gi_counter_resolution-1 DOWNTO 0); -- value the internal counter is set after set isl_counter_change to high
isl_counter_change : IN STD_LOGIC; -- every time this value is set high the internal counter is set to iusig_counter_set's value; this signal should only be assigned for one cycle.
isl_rearm : IN STD_LOGIC; --if the watchdog fired this signal has to be set to high for one cycle before the watchdog starts counting again.
osl_counter_val : OUT UNSIGNED(gi_counter_resolution-1 DOWNTO 0); --the actual value of the internal counter
osl_granted : OUT STD_LOGIC -- '1' if the counter is higher than zero and the rearm was set after the watchdog fired
);
END COMPONENT watchdog;
END PACKAGE watchdog_pkg;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.numeric_std.ALL;
USE work.watchdog_pkg.ALL;
-------------------------------------------------------------------------------
-- ENTITIY
-------------------------------------------------------------------------------
ENTITY watchdog IS
GENERIC(
gi_counter_resolution : INTEGER := 32
);
PORT(
isl_clk : IN STD_LOGIC;
isl_reset_n : IN STD_LOGIC;
iusig_counter_set : IN UNSIGNED(gi_counter_resolution-1 DOWNTO 0);
isl_counter_change : IN STD_LOGIC;
isl_rearm : IN STD_LOGIC;
osl_counter_val : OUT UNSIGNED(gi_counter_resolution-1 DOWNTO 0);
osl_granted : OUT STD_LOGIC
);
END ENTITY watchdog;
-------------------------------------------------------------------------------
-- ARCHITECTURE
-------------------------------------------------------------------------------
ARCHITECTURE rtl OF watchdog IS
TYPE t_internal_register IS RECORD
watchdog_fired : STD_LOGIC;
granted : STD_LOGIC;
counter : UNSIGNED(gi_counter_resolution-1 DOWNTO 0);
END RECORD;
SIGNAL ri, ri_next : t_internal_register;
BEGIN
--------------------------------------------
-- combinatorial process
--------------------------------------------
comb_process: PROCESS(ri, isl_reset_n,iusig_counter_set,isl_counter_change,isl_rearm)
VARIABLE vi: t_internal_register;
BEGIN
-- keep variables stable
vi:=ri;
IF isl_rearm = '1' THEN
vi.watchdog_fired := '0';
END IF;
IF isl_counter_change = '1' THEN
vi.counter := iusig_counter_set;
END IF;
IF vi.watchdog_fired = '0' THEN
IF vi.counter > to_unsigned(0,gi_counter_resolution) THEN
vi.counter := vi.counter -1;
vi.granted := '1';
END IF;
ELSE
vi.granted := '0';
END IF;
IF vi.counter = to_unsigned(0,gi_counter_resolution) THEN
vi.watchdog_fired := '1';
END IF;
-- reset
IF isl_reset_n = '0' THEN
vi.counter := (OTHERS => '0');
vi.watchdog_fired := '1';
vi.granted := '0';
END IF;
-- setting outputs
ri_next <= vi;
END PROCESS comb_process;
--------------------------------------------
-- registered process
--------------------------------------------
reg_process: PROCESS (isl_clk)
BEGIN
IF rising_edge(isl_clk) THEN
ri <= ri_next;
END IF;
END PROCESS reg_process;
osl_granted <= ri.granted;
osl_counter_val <= ri.counter;
END ARCHITECTURE rtl;
|
apache-2.0
|
ntb-ch/cb20
|
FPGA_Designs/standard/cb20/synthesis/submodules/avalon_gpio_interface.m.vhd
|
4
|
11144
|
-------------------------------------------------------------------------------
-- _________ _____ _____ ____ _____ ___ ____ --
-- |_ ___ | |_ _| |_ _| |_ \|_ _| |_ ||_ _| --
-- | |_ \_| | | | | | \ | | | |_/ / --
-- | _| | | _ | | | |\ \| | | __'. --
-- _| |_ _| |__/ | _| |_ _| |_\ |_ _| | \ \_ --
-- |_____| |________| |_____| |_____|\____| |____||____| --
-- --
-------------------------------------------------------------------------------
-- --
-- Avalon MM interface for GPIO --
-- --
-------------------------------------------------------------------------------
-- Copyright 2014 NTB University of Applied Sciences in Technology --
-- --
-- Licensed under the Apache License, Version 2.0 (the "License"); --
-- you may not use this file except in compliance with the License. --
-- You may obtain a copy of the License at --
-- --
-- http://www.apache.org/licenses/LICENSE-2.0 --
-- --
-- Unless required by applicable law or agreed to in writing, software --
-- distributed under the License is distributed on an "AS IS" BASIS, --
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. --
-- See the License for the specific language governing permissions and --
-- limitations under the License. --
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE IEEE.math_real.ALL;
USE work.fLink_definitions.ALL;
PACKAGE avalon_gpio_interface_pkg IS
CONSTANT c_max_number_of_GPIOs : INTEGER := 128;
CONSTANT c_gpio_interface_address_with : INTEGER := 4;
COMPONENT avalon_gpio_interface IS
GENERIC (
number_of_gpios: INTEGER RANGE 1 TO c_max_number_of_GPIOs := 1;
unique_id: STD_LOGIC_VECTOR (c_fLink_avs_data_width-1 DOWNTO 0) := (OTHERS => '0')
);
PORT (
isl_clk : IN STD_LOGIC;
isl_reset_n : IN STD_LOGIC;
islv_avs_address : IN STD_LOGIC_VECTOR(c_gpio_interface_address_with-1 DOWNTO 0);
islv_avs_byteenable : IN STD_LOGIC_VECTOR(c_fLink_avs_data_width_in_byte-1 DOWNTO 0);
isl_avs_read : IN STD_LOGIC;
isl_avs_write : IN STD_LOGIC;
osl_avs_waitrequest : OUT STD_LOGIC;
islv_avs_write_data : IN STD_LOGIC_VECTOR(c_fLink_avs_data_width-1 DOWNTO 0);
oslv_avs_read_data : OUT STD_LOGIC_VECTOR(c_fLink_avs_data_width-1 DOWNTO 0);
oslv_gpios : INOUT STD_LOGIC_VECTOR(number_of_gpios-1 DOWNTO 0)
);
END COMPONENT;
CONSTANT c_gpio_subtype_id : INTEGER := 0;
CONSTANT c_gpio_interface_version : INTEGER := 0;
END PACKAGE avalon_gpio_interface_pkg;
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE IEEE.math_real.ALL;
USE work.avalon_gpio_interface_pkg.ALL;
USE work.fLink_definitions.ALL;
ENTITY avalon_gpio_interface IS
GENERIC (
number_of_gpios: INTEGER RANGE 1 TO c_max_number_of_GPIOs := 1;
unique_id: STD_LOGIC_VECTOR (c_fLink_avs_data_width-1 DOWNTO 0) := (OTHERS => '0')
);
PORT (
isl_clk : IN STD_LOGIC;
isl_reset_n : IN STD_LOGIC;
islv_avs_address : IN STD_LOGIC_VECTOR(c_gpio_interface_address_with-1 DOWNTO 0);
islv_avs_byteenable : IN STD_LOGIC_VECTOR(c_fLink_avs_data_width_in_byte-1 DOWNTO 0);
isl_avs_read : IN STD_LOGIC;
isl_avs_write : IN STD_LOGIC;
osl_avs_waitrequest : OUT STD_LOGIC;
islv_avs_write_data : IN STD_LOGIC_VECTOR(c_fLink_avs_data_width-1 DOWNTO 0);
oslv_avs_read_data : OUT STD_LOGIC_VECTOR(c_fLink_avs_data_width-1 DOWNTO 0);
oslv_gpios : INOUT STD_LOGIC_VECTOR(number_of_gpios-1 DOWNTO 0)
);
CONSTANT c_configuration_reg_address: UNSIGNED(c_gpio_interface_address_with-1 DOWNTO 0) := to_unsigned(c_fLink_configuration_address, c_gpio_interface_address_with);
CONSTANT c_usig_dir_regs_address: UNSIGNED(c_gpio_interface_address_with-1 DOWNTO 0) := to_unsigned(c_fLink_number_of_std_registers,c_gpio_interface_address_with);
CONSTANT c_usig_number_of_regs: UNSIGNED(c_gpio_interface_address_with-1 DOWNTO 0) := to_unsigned((number_of_gpios-1)/c_fLink_avs_data_width+1,c_gpio_interface_address_with);
CONSTANT c_usig_value_regs_address: UNSIGNED(c_gpio_interface_address_with-1 DOWNTO 0) := c_usig_dir_regs_address + c_usig_number_of_regs;
CONSTANT c_usig_value_regs_max_address: UNSIGNED(c_gpio_interface_address_with-1 DOWNTO 0) := c_usig_value_regs_address + c_usig_number_of_regs;
CONSTANT c_int_nr_of_gpio_reg: INTEGER := number_of_gpios/c_fLink_avs_data_width;
END ENTITY avalon_gpio_interface;
ARCHITECTURE rtl OF avalon_gpio_interface IS
TYPE t_internal_register IS RECORD
conf_reg : STD_LOGIC_VECTOR(c_fLink_avs_data_width-1 DOWNTO 0);
dir_reg : STD_LOGIC_VECTOR(c_max_number_of_GPIOs-1 DOWNTO 0);
value_reg : STD_LOGIC_VECTOR(c_max_number_of_GPIOs-1 DOWNTO 0);
END RECORD;
SIGNAL ri,ri_next : t_internal_register;
BEGIN
-- combinatoric process
comb_proc : PROCESS (isl_reset_n, ri, isl_avs_write, islv_avs_address, isl_avs_read, islv_avs_write_data, oslv_gpios,islv_avs_byteenable)
VARIABLE vi : t_internal_register;
VARIABLE gpio_part_nr: INTEGER := 0;
VARIABLE avs_address: UNSIGNED(c_gpio_interface_address_with-1 DOWNTO 0) := to_unsigned(0,c_gpio_interface_address_with);
BEGIN
-- Keep variables stable
vi := ri;
avs_address := UNSIGNED(islv_avs_address);
-- Set read data to default value
oslv_avs_read_data <= (OTHERS => '0');
-- Avalon slave interface: write part
IF isl_avs_write = '1' THEN
-- Write to config register
IF avs_address = c_configuration_reg_address THEN
FOR i IN 0 TO c_fLink_avs_data_width_in_byte-1 LOOP
IF islv_avs_byteenable(i) = '1' THEN
vi.conf_reg((i + 1) * 8 - 1 DOWNTO i * 8) := islv_avs_write_data((i + 1) * 8 - 1 DOWNTO i * 8);
END IF;
END LOOP;
-- Write to direction registers
ELSIF avs_address >= c_usig_dir_regs_address AND avs_address < c_usig_value_regs_address THEN
gpio_part_nr := to_integer(avs_address-c_usig_dir_regs_address);
FOR i IN 0 TO c_fLink_avs_data_width_in_byte-1 LOOP
IF islv_avs_byteenable(i) = '1' THEN
vi.dir_reg(gpio_part_nr * c_fLink_avs_data_width + (i + 1) * 8 - 1 DOWNTO gpio_part_nr * c_fLink_avs_data_width + i * 8) := islv_avs_write_data((i + 1) * 8 - 1 DOWNTO i * 8);
END IF;
END LOOP;
-- Write to value registers
ELSIF avs_address>= c_usig_value_regs_address AND avs_address< c_usig_value_regs_max_address THEN
gpio_part_nr := to_integer(avs_address-c_usig_value_regs_address);
FOR i IN 0 TO c_fLink_avs_data_width_in_byte-1 LOOP
IF islv_avs_byteenable(i) = '1' THEN
vi.value_reg(gpio_part_nr * c_fLink_avs_data_width + (i + 1) * 8 - 1 DOWNTO gpio_part_nr * c_fLink_avs_data_width + i * 8) := islv_avs_write_data((i + 1) * 8 - 1 DOWNTO i * 8);
END IF;
END LOOP;
END IF;
END IF;
FOR i IN 0 TO number_of_gpios-1 LOOP
IF ri.dir_reg(i) = '1' THEN --output
oslv_gpios(i) <= ri.value_reg(i);
ELSE --input
oslv_gpios(i) <= 'Z';
vi.value_reg(i) := oslv_gpios(i);
END IF;
END LOOP;
--avalon slave interface read part
IF isl_avs_read = '1' THEN
CASE avs_address IS
-- Read type register
WHEN to_unsigned(c_fLink_typdef_address, c_gpio_interface_address_with) =>
oslv_avs_read_data((c_fLink_interface_version_length + c_fLink_subtype_length + c_fLink_id_length-1) DOWNTO
(c_fLink_interface_version_length + c_fLink_subtype_length)) <= STD_LOGIC_VECTOR(to_unsigned(c_fLink_digital_io_id,c_fLink_id_length));
oslv_avs_read_data((c_fLink_interface_version_length + c_fLink_subtype_length - 1) DOWNTO c_fLink_interface_version_length) <= STD_LOGIC_VECTOR(to_unsigned(c_gpio_subtype_id,c_fLink_subtype_length));
oslv_avs_read_data(c_fLink_interface_version_length-1 DOWNTO 0) <= STD_LOGIC_VECTOR(to_unsigned(c_gpio_interface_version,c_fLink_interface_version_length));
-- Read mem size register
WHEN to_unsigned(c_fLink_mem_size_address,c_gpio_interface_address_with) =>
oslv_avs_read_data(c_gpio_interface_address_with + 2) <= '1';
-- Read number of channels register
WHEN to_unsigned(c_fLink_number_of_channels_address, c_gpio_interface_address_with) =>
oslv_avs_read_data <= std_logic_vector(to_unsigned(number_of_gpios, c_fLink_avs_data_width));
-- Read config register
WHEN to_unsigned(c_fLink_configuration_address, c_gpio_interface_address_with) =>
oslv_avs_read_data <= vi.conf_reg;
-- Read unique id register
WHEN to_unsigned(c_fLink_unique_id_address,c_gpio_interface_address_with) =>
oslv_avs_read_data <= unique_id;
-- Read direction or value register
WHEN OTHERS =>
IF avs_address >= c_usig_dir_regs_address AND avs_address< c_usig_value_regs_address THEN
gpio_part_nr := to_integer(avs_address)-c_fLink_number_of_std_registers;
IF gpio_part_nr <c_int_nr_of_gpio_reg THEN
oslv_avs_read_data <= vi.dir_reg((gpio_part_nr+1) * c_fLink_avs_data_width -1 DOWNTO gpio_part_nr * c_fLink_avs_data_width);
ELSE
FOR i IN 0 TO (number_of_gpios mod c_fLink_avs_data_width)-1 LOOP
oslv_avs_read_data(i) <= vi.dir_reg(i+gpio_part_nr*c_fLink_avs_data_width);
END LOOP;
END IF;
ELSIF avs_address>= c_usig_value_regs_address AND avs_address< c_usig_value_regs_max_address THEN
gpio_part_nr := to_integer(avs_address-c_usig_value_regs_address);
IF gpio_part_nr <c_int_nr_of_gpio_reg THEN
oslv_avs_read_data <= vi.value_reg((gpio_part_nr+1) * c_fLink_avs_data_width -1 DOWNTO gpio_part_nr * c_fLink_avs_data_width);
ELSE
FOR i IN 0 TO (number_of_gpios mod c_fLink_avs_data_width)-1 LOOP
oslv_avs_read_data(i) <= vi.value_reg(i+gpio_part_nr*c_fLink_avs_data_width);
END LOOP;
END IF;
ELSE
oslv_avs_read_data <= (OTHERS => '0');
END IF;
END CASE;
END IF;
IF isl_reset_n = '0' OR vi.conf_reg(c_fLink_reset_bit_num) = '1' THEN
vi.conf_reg := (OTHERS =>'0');
vi.value_reg := (OTHERS =>'0');
vi.dir_reg := (OTHERS =>'0');
END IF;
ri_next <= vi;
END PROCESS comb_proc;
reg_proc : PROCESS (isl_clk)
BEGIN
IF rising_edge(isl_clk) THEN
ri <= ri_next;
END IF;
END PROCESS reg_proc;
osl_avs_waitrequest <= '0';
END rtl;
|
apache-2.0
|
ntb-ch/cb20
|
FPGA_Designs/watchdog/cb20/synthesis/cb20_info_device_0_avalon_slave_translator.vhd
|
1
|
14655
|
-- cb20_info_device_0_avalon_slave_translator.vhd
-- Generated using ACDS version 13.0sp1 232 at 2020.06.03.16:36:13
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity cb20_info_device_0_avalon_slave_translator is
generic (
AV_ADDRESS_W : integer := 5;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 1;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 17;
UAV_BURSTCOUNT_W : integer := 3;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 0;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 1;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := '0'; -- clk.clk
reset : in std_logic := '0'; -- reset.reset
uav_address : in std_logic_vector(16 downto 0) := (others => '0'); -- avalon_universal_slave_0.address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => '0'); -- .burstcount
uav_read : in std_logic := '0'; -- .read
uav_write : in std_logic := '0'; -- .write
uav_waitrequest : out std_logic; -- .waitrequest
uav_readdatavalid : out std_logic; -- .readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => '0'); -- .byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- .readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
uav_lock : in std_logic := '0'; -- .lock
uav_debugaccess : in std_logic := '0'; -- .debugaccess
av_address : out std_logic_vector(4 downto 0); -- avalon_anti_slave_0.address
av_write : out std_logic; -- .write
av_read : out std_logic; -- .read
av_readdata : in std_logic_vector(31 downto 0) := (others => '0'); -- .readdata
av_writedata : out std_logic_vector(31 downto 0); -- .writedata
av_byteenable : out std_logic_vector(3 downto 0); -- .byteenable
av_waitrequest : in std_logic := '0'; -- .waitrequest
av_beginbursttransfer : out std_logic;
av_begintransfer : out std_logic;
av_burstcount : out std_logic_vector(0 downto 0);
av_chipselect : out std_logic;
av_clken : out std_logic;
av_debugaccess : out std_logic;
av_lock : out std_logic;
av_outputenable : out std_logic;
av_readdatavalid : in std_logic := '0';
av_response : in std_logic_vector(1 downto 0) := (others => '0');
av_writebyteenable : out std_logic_vector(3 downto 0);
av_writeresponserequest : out std_logic;
av_writeresponsevalid : in std_logic := '0';
uav_clken : in std_logic := '0';
uav_response : out std_logic_vector(1 downto 0);
uav_writeresponserequest : in std_logic := '0';
uav_writeresponsevalid : out std_logic
);
end entity cb20_info_device_0_avalon_slave_translator;
architecture rtl of cb20_info_device_0_avalon_slave_translator is
component altera_merlin_slave_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(16 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(4 downto 0); -- address
av_write : out std_logic; -- write
av_read : out std_logic; -- read
av_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
av_writedata : out std_logic_vector(31 downto 0); -- writedata
av_byteenable : out std_logic_vector(3 downto 0); -- byteenable
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_begintransfer : out std_logic; -- begintransfer
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_writebyteenable : out std_logic_vector(3 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
av_chipselect : out std_logic; -- chipselect
av_clken : out std_logic; -- clken
uav_clken : in std_logic := 'X'; -- clken
av_debugaccess : out std_logic; -- debugaccess
av_outputenable : out std_logic; -- outputenable
uav_response : out std_logic_vector(1 downto 0); -- response
av_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response
uav_writeresponserequest : in std_logic := 'X'; -- writeresponserequest
uav_writeresponsevalid : out std_logic; -- writeresponsevalid
av_writeresponserequest : out std_logic; -- writeresponserequest
av_writeresponsevalid : in std_logic := 'X' -- writeresponsevalid
);
end component altera_merlin_slave_translator;
begin
info_device_0_avalon_slave_translator : component altera_merlin_slave_translator
generic map (
AV_ADDRESS_W => AV_ADDRESS_W,
AV_DATA_W => AV_DATA_W,
UAV_DATA_W => UAV_DATA_W,
AV_BURSTCOUNT_W => AV_BURSTCOUNT_W,
AV_BYTEENABLE_W => AV_BYTEENABLE_W,
UAV_BYTEENABLE_W => UAV_BYTEENABLE_W,
UAV_ADDRESS_W => UAV_ADDRESS_W,
UAV_BURSTCOUNT_W => UAV_BURSTCOUNT_W,
AV_READLATENCY => AV_READLATENCY,
USE_READDATAVALID => USE_READDATAVALID,
USE_WAITREQUEST => USE_WAITREQUEST,
USE_UAV_CLKEN => USE_UAV_CLKEN,
USE_READRESPONSE => USE_READRESPONSE,
USE_WRITERESPONSE => USE_WRITERESPONSE,
AV_SYMBOLS_PER_WORD => AV_SYMBOLS_PER_WORD,
AV_ADDRESS_SYMBOLS => AV_ADDRESS_SYMBOLS,
AV_BURSTCOUNT_SYMBOLS => AV_BURSTCOUNT_SYMBOLS,
AV_CONSTANT_BURST_BEHAVIOR => AV_CONSTANT_BURST_BEHAVIOR,
UAV_CONSTANT_BURST_BEHAVIOR => UAV_CONSTANT_BURST_BEHAVIOR,
AV_REQUIRE_UNALIGNED_ADDRESSES => AV_REQUIRE_UNALIGNED_ADDRESSES,
CHIPSELECT_THROUGH_READLATENCY => CHIPSELECT_THROUGH_READLATENCY,
AV_READ_WAIT_CYCLES => AV_READ_WAIT_CYCLES,
AV_WRITE_WAIT_CYCLES => AV_WRITE_WAIT_CYCLES,
AV_SETUP_WAIT_CYCLES => AV_SETUP_WAIT_CYCLES,
AV_DATA_HOLD_CYCLES => AV_DATA_HOLD_CYCLES
)
port map (
clk => clk, -- clk.clk
reset => reset, -- reset.reset
uav_address => uav_address, -- avalon_universal_slave_0.address
uav_burstcount => uav_burstcount, -- .burstcount
uav_read => uav_read, -- .read
uav_write => uav_write, -- .write
uav_waitrequest => uav_waitrequest, -- .waitrequest
uav_readdatavalid => uav_readdatavalid, -- .readdatavalid
uav_byteenable => uav_byteenable, -- .byteenable
uav_readdata => uav_readdata, -- .readdata
uav_writedata => uav_writedata, -- .writedata
uav_lock => uav_lock, -- .lock
uav_debugaccess => uav_debugaccess, -- .debugaccess
av_address => av_address, -- avalon_anti_slave_0.address
av_write => av_write, -- .write
av_read => av_read, -- .read
av_readdata => av_readdata, -- .readdata
av_writedata => av_writedata, -- .writedata
av_byteenable => av_byteenable, -- .byteenable
av_waitrequest => av_waitrequest, -- .waitrequest
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_chipselect => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open, -- (terminated)
uav_response => open, -- (terminated)
av_response => "00", -- (terminated)
uav_writeresponserequest => '0', -- (terminated)
uav_writeresponsevalid => open, -- (terminated)
av_writeresponserequest => open, -- (terminated)
av_writeresponsevalid => '0' -- (terminated)
);
end architecture rtl; -- of cb20_info_device_0_avalon_slave_translator
|
apache-2.0
|
marzoul/PoC
|
src/xil/xil_ChipScopeICON.vhdl
|
2
|
7863
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Patrick Lehmann
--
-- Module: Generic Xilinx ChipScope ICON wrapper
--
-- Description:
-- ------------------------------------
-- This module wraps 15 ChipScope ICON IPCore netlists generated from ChipScope
-- ICON xco files. The generic parameter PORTS selects the apropriate ICON
-- instance with 1 to 15 ICON ControlBus ports. Each ControlBus port is of type
-- T_XIL_CHIPSCOPE_CONTROL and of mode 'inout'.
--
-- PoC IPCore compiler:
-- ------------------------------------
-- Please use the provided PoC netlist compiler tool to recreate the needed source
-- and netlist files on your computer.
--
-- cd <PoCRoot>\netlist
-- .\netlist.ps1 -rl --coregen PoC.xil.ChipScopeICON_1 --board KC705
-- [...]
-- .\netlist.ps1 -rl --coregen PoC.xil.ChipScopeICON_15 --board KC705
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library PoC;
use PoC.xil.all;
entity xil_ChipScopeICON is
generic (
PORTS : POSITIVE
);
port (
ControlBus : inout T_XIL_CHIPSCOPE_CONTROL_VECTOR(PORTS - 1 downto 0)
);
end entity;
architecture rtl of xil_ChipScopeICON is
begin
assert (PORTS < 16) report "To many ICON control ports." severity failure;
genICON1 : if (PORTS = 1) generate
ICON : entity PoC.xil_ChipScopeICON_1
port map (
control0 => ControlBus(0)
);
end generate;
genICON2 : if (PORTS = 2) generate
ICON : entity PoC.xil_ChipScopeICON_2
port map (
control0 => ControlBus(0),
control1 => ControlBus(1)
);
end generate;
genICON3 : if (PORTS = 3) generate
ICON : entity PoC.xil_ChipScopeICON_3
port map (
control0 => ControlBus(0),
control1 => ControlBus(1),
control2 => ControlBus(2)
);
end generate;
genICON4 : if (PORTS = 4) generate
ICON : entity PoC.xil_ChipScopeICON_4
port map (
control0 => ControlBus(0),
control1 => ControlBus(1),
control2 => ControlBus(2),
control3 => ControlBus(3)
);
end generate;
genICON5 : if (PORTS = 5) generate
ICON : entity PoC.xil_ChipScopeICON_5
port map (
control0 => ControlBus(0),
control1 => ControlBus(1),
control2 => ControlBus(2),
control3 => ControlBus(3),
control4 => ControlBus(4)
);
end generate;
genICON6 : if (PORTS = 6) generate
ICON : entity PoC.xil_ChipScopeICON_6
port map (
control0 => ControlBus(0),
control1 => ControlBus(1),
control2 => ControlBus(2),
control3 => ControlBus(3),
control4 => ControlBus(4),
control5 => ControlBus(5)
);
end generate;
genICON7 : if (PORTS = 7) generate
ICON : entity PoC.xil_ChipScopeICON_7
port map (
control0 => ControlBus(0),
control1 => ControlBus(1),
control2 => ControlBus(2),
control3 => ControlBus(3),
control4 => ControlBus(4),
control5 => ControlBus(5),
control6 => ControlBus(6)
);
end generate;
genICON8 : if (PORTS = 8) generate
ICON : entity PoC.xil_ChipScopeICON_8
port map (
control0 => ControlBus(0),
control1 => ControlBus(1),
control2 => ControlBus(2),
control3 => ControlBus(3),
control4 => ControlBus(4),
control5 => ControlBus(5),
control6 => ControlBus(6),
control7 => ControlBus(7)
);
end generate;
genICON9 : if (PORTS = 9) generate
ICON : entity PoC.xil_ChipScopeICON_9
port map (
control0 => ControlBus(0),
control1 => ControlBus(1),
control2 => ControlBus(2),
control3 => ControlBus(3),
control4 => ControlBus(4),
control5 => ControlBus(5),
control6 => ControlBus(6),
control7 => ControlBus(7),
control8 => ControlBus(8)
);
end generate;
genICON10 : if (PORTS = 10) generate
ICON : entity PoC.xil_ChipScopeICON_10
port map (
control0 => ControlBus(0),
control1 => ControlBus(1),
control2 => ControlBus(2),
control3 => ControlBus(3),
control4 => ControlBus(4),
control5 => ControlBus(5),
control6 => ControlBus(6),
control7 => ControlBus(7),
control8 => ControlBus(8),
control9 => ControlBus(9)
);
end generate;
genICON11 : if (PORTS = 11) generate
ICON : entity PoC.xil_ChipScopeICON_11
port map (
control0 => ControlBus(0),
control1 => ControlBus(1),
control2 => ControlBus(2),
control3 => ControlBus(3),
control4 => ControlBus(4),
control5 => ControlBus(5),
control6 => ControlBus(6),
control7 => ControlBus(7),
control8 => ControlBus(8),
control9 => ControlBus(9),
control10 => ControlBus(10)
);
end generate;
genICON12 : if (PORTS = 12) generate
ICON : entity PoC.xil_ChipScopeICON_12
port map (
control0 => ControlBus(0),
control1 => ControlBus(1),
control2 => ControlBus(2),
control3 => ControlBus(3),
control4 => ControlBus(4),
control5 => ControlBus(5),
control6 => ControlBus(6),
control7 => ControlBus(7),
control8 => ControlBus(8),
control9 => ControlBus(9),
control10 => ControlBus(10),
control11 => ControlBus(11)
);
end generate;
genICON13 : if (PORTS = 13) generate
ICON : entity PoC.xil_ChipScopeICON_13
port map (
control0 => ControlBus(0),
control1 => ControlBus(1),
control2 => ControlBus(2),
control3 => ControlBus(3),
control4 => ControlBus(4),
control5 => ControlBus(5),
control6 => ControlBus(6),
control7 => ControlBus(7),
control8 => ControlBus(8),
control9 => ControlBus(9),
control10 => ControlBus(10),
control11 => ControlBus(11),
control12 => ControlBus(12)
);
end generate;
genICON14 : if (PORTS = 14) generate
ICON : entity PoC.xil_ChipScopeICON_14
port map (
control0 => ControlBus(0),
control1 => ControlBus(1),
control2 => ControlBus(2),
control3 => ControlBus(3),
control4 => ControlBus(4),
control5 => ControlBus(5),
control6 => ControlBus(6),
control7 => ControlBus(7),
control8 => ControlBus(8),
control9 => ControlBus(9),
control10 => ControlBus(10),
control11 => ControlBus(11),
control12 => ControlBus(12),
control13 => ControlBus(13)
);
end generate;
genICON15 : if (PORTS = 15) generate
ICON : entity PoC.xil_ChipScopeICON_15
port map (
control0 => ControlBus(0),
control1 => ControlBus(1),
control2 => ControlBus(2),
control3 => ControlBus(3),
control4 => ControlBus(4),
control5 => ControlBus(5),
control6 => ControlBus(6),
control7 => ControlBus(7),
control8 => ControlBus(8),
control9 => ControlBus(9),
control10 => ControlBus(10),
control11 => ControlBus(11),
control12 => ControlBus(12),
control13 => ControlBus(13),
control14 => ControlBus(14)
);
end generate;
end architecture;
|
apache-2.0
|
marzoul/PoC
|
tb/common/my_config_Atlys.vhdl
|
2
|
1748
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Thomas B. Preusser
-- Martin Zabel
-- Patrick Lehmann
--
-- Package: Project specific configuration.
--
-- Description:
-- ------------------------------------
-- This file was created from template <PoCRoot>/src/common/my_config.template.vhdl.
--
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library PoC;
package my_config is
-- Change these lines to setup configuration.
constant MY_BOARD : string := "Atlys"; -- Digilent Atlys - Xilinx Spartan-6: XC6SLX45
constant MY_DEVICE : string := "None"; -- infer from MY_BOARD
-- For internal use only
constant MY_VERBOSE : boolean := FALSE;
end package;
|
apache-2.0
|
marzoul/PoC
|
src/io/io_FanControl.vhdl
|
1
|
10106
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Patrick Lehmann
--
-- Module: Generic Fan Controller
--
-- Description:
-- ------------------------------------
-- This module generates a PWM signal for a 3-pin (transistor controlled) or
-- 4-pin fan header. The FPGAs temperature is read from device specific system
-- monitors (normal, user temperature, over temperature).
--
-- For example the Xilinx System Monitors are configured as follows:
--
-- | /-----\
-- Temp_ov on=80 | - - - - - - /-------/ \
-- | / | \
-- Temp_ov off=60 | - - - - - / - - - - | - - - - \----\
-- | / | \
-- | / | | \
-- Temp_us on=35 | - /---/ | | \
-- Temp_us off=30 | - / - -|- - - - - - | - - - - - - -|- \------\
-- | / | | | \
-- ----------------|--------|------------|--------------|----------|---------
-- pwm = | min | medium | max | medium | min
--
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library PoC;
use PoC.config.all;
use PoC.utils.all;
use PoC.vectors.all;
use PoC.physical.all;
use PoC.components.all;
use PoC.xil.all;
entity io_FanControl is
generic (
CLOCK_FREQ : FREQ;
ADD_INPUT_SYNCHRONIZERS : BOOLEAN := TRUE;
ENABLE_TACHO : BOOLEAN := FALSE
);
port (
Clock : in STD_LOGIC;
Reset : in STD_LOGIC;
Fan_PWM : out STD_LOGIC;
Fan_Tacho : in STD_LOGIC;
TachoFrequency : out STD_LOGIC_VECTOR(ite(ENABLE_TACHO, 16, 1) - 1 downto 0)
);
end;
architecture rtl of io_FanControl is
constant TIME_STARTUP : TIME := 500 ms; -- StartUp time
constant PWM_RESOLUTION : POSITIVE := 4; -- 4 Bit resolution => 0 to 15 steps
constant PWM_FREQ : FREQ := 10 Hz; --
constant TACHO_RESOLUTION : POSITIVE := 8;
signal PWM_PWMIn : STD_LOGIC_VECTOR(PWM_RESOLUTION - 1 downto 0);
signal PWM_PWMOut : STD_LOGIC := '0';
begin
-- System Monitor and temperature to PWM ratio calculation for Virtex6
-- ==========================================================================================================================================================
genXilinx : if (VENDOR = VENDOR_XILINX) generate
signal OverTemperature_async : STD_LOGIC;
signal OverTemperature_sync : STD_LOGIC;
signal UserTemperature_async : STD_LOGIC;
signal UserTemperature_sync : STD_LOGIC;
signal TC_Timeout : STD_LOGIC;
signal StartUp : STD_LOGIC;
begin
genML605 : if (BOARD = BOARD_ML605) generate
SystemMonitor : xil_SystemMonitor_Virtex6
port map (
Reset => Reset, -- Reset signal for the System Monitor control logic
Alarm_UserTemp => UserTemperature_async, -- Temperature-sensor alarm output
Alarm_OverTemp => OverTemperature_async, -- Over-Temperature alarm output
Alarm => open, -- OR'ed output of all the Alarms
VP => '0', -- Dedicated Analog Input Pair
VN => '0'
);
end generate;
genSeries7Board : if ((BOARD = BOARD_KC705) or (BOARD = BOARD_VC707)) generate
SystemMonitor : xil_SystemMonitor_Series7
port map (
Reset => Reset, -- Reset signal for the System Monitor control logic
Alarm_UserTemp => UserTemperature_async, -- Temperature-sensor alarm output
Alarm_OverTemp => OverTemperature_async, -- Over-Temperature alarm output
Alarm => open, -- OR'ed output of all the Alarms
VP => '0', -- Dedicated Analog Input Pair
VN => '0'
);
end generate;
sync : entity PoC.sync_Bits
generic map (
BITS => 2
)
port map (
Clock => Clock,
Input(0) => OverTemperature_async,
Input(1) => UserTemperature_async,
Output(0) => OverTemperature_sync,
Output(1) => UserTemperature_sync
);
-- timer for warm-up control
-- ==========================================================================================================================================================
TC : entity PoC.io_TimingCounter
generic map (
TIMING_TABLE => (0 => TimingToCycles(TIME_STARTUP, CLOCK_FREQ)) -- timing table
)
port map (
Clock => Clock, -- clock
Enable => StartUp, -- enable counter
Load => '0', -- load Timing Value from TIMING_TABLE selected by slot
Slot => 0, --
Timeout => TC_Timeout -- timing reached
);
StartUp <= not TC_Timeout;
process(StartUp, UserTemperature_sync, OverTemperature_sync)
begin
if (StartUp = '1') then PWM_PWMIn <= to_slv(2**(PWM_RESOLUTION) - 1, PWM_RESOLUTION); -- 100%; start up
elsif (OverTemperature_sync = '1') then PWM_PWMIn <= to_slv(2**(PWM_RESOLUTION) - 1, PWM_RESOLUTION); -- 100%
elsif (UserTemperature_sync = '1') then PWM_PWMIn <= to_slv(2**(PWM_RESOLUTION - 1), PWM_RESOLUTION); -- 50%
else PWM_PWMIn <= to_slv(4, PWM_RESOLUTION); -- 13%
end if;
end process;
end generate;
genAltera : if (VENDOR = VENDOR_ALTERA) generate
-- signal OverTemperature_async : STD_LOGIC;
signal OverTemperature_sync : STD_LOGIC;
-- signal UserTemperature_async : STD_LOGIC;
signal UserTemperature_sync : STD_LOGIC;
signal TC_Timeout : STD_LOGIC;
signal StartUp : STD_LOGIC;
begin
genDE4 : if (BOARD = BOARD_DE4) generate
OverTemperature_sync <= '0';
UserTemperature_sync <= '1';
end generate;
-- timer for warm-up control
-- ==========================================================================================================================================================
TC : entity PoC.io_TimingCounter
generic map (
TIMING_TABLE => (0 => TimingToCycles(TIME_STARTUP, CLOCK_FREQ)) -- timing table
)
port map (
Clock => Clock, -- clock
Enable => StartUp, -- enable counter
Load => '0', -- load Timing Value from TIMING_TABLE selected by slot
Slot => 0, --
Timeout => TC_Timeout -- timing reached
);
StartUp <= not TC_Timeout;
process(StartUp, UserTemperature_sync, OverTemperature_sync)
begin
if (StartUp = '1') then PWM_PWMIn <= to_slv(2**(PWM_RESOLUTION) - 1, PWM_RESOLUTION); -- 100%; start up
elsif (OverTemperature_sync = '1') then PWM_PWMIn <= to_slv(2**(PWM_RESOLUTION) - 1, PWM_RESOLUTION); -- 100%
elsif (UserTemperature_sync = '1') then PWM_PWMIn <= to_slv(2**(PWM_RESOLUTION - 1), PWM_RESOLUTION); -- 50%
else PWM_PWMIn <= to_slv(4, PWM_RESOLUTION); -- 13%
end if;
end process;
end generate;
-- PWM signal modulator
-- ==========================================================================================================================================================
PWM : entity PoC.io_PulseWidthModulation
generic map (
CLOCK_FREQ => CLOCK_FREQ, --
PWM_FREQ => PWM_FREQ, --
PWM_RESOLUTION => PWM_RESOLUTION --
)
port map (
Clock => Clock,
Reset => Reset,
PWMIn => PWM_PWMIn,
PWMOut => PWM_PWMOut
);
-- registered output
Fan_PWM <= PWM_PWMOut when rising_edge(Clock);
-- tacho signal interpretation -> convert to RPM
-- ==========================================================================================================================================================
genNoTacho : if (ENABLE_TACHO = FALSE) generate
TachoFrequency <= (TachoFrequency'range => '0');
end generate;
genTacho : if (ENABLE_TACHO = TRUE) generate
signal Tacho_sync : STD_LOGIC;
signal Tacho_Freq : STD_LOGIC_VECTOR(TACHO_RESOLUTION - 1 downto 0);
begin
-- Input Synchronization
genNoSync : if (ADD_INPUT_SYNCHRONIZERS = FALSE) generate
Tacho_sync <= Fan_Tacho;
end generate;
genSync : if (ADD_INPUT_SYNCHRONIZERS = TRUE) generate
sync_i : entity PoC.sync_Bits
port map (
Clock => Clock, -- Clock to be synchronized to
Input(0) => Fan_Tacho, -- Data to be synchronized
Output(0) => Tacho_sync -- synchronised data
);
end generate;
Tacho : entity PoC.io_FrequencyCounter
generic map (
CLOCK_FREQ => CLOCK_FREQ, --
TIMEBASE => (60 sec / 64), -- ca. 1 second
RESOLUTION => 8 -- max. ca. 256 RPS -> max. ca. 16k RPM
)
port map (
Clock => Clock,
Reset => Reset,
FreqIn => Tacho_sync,
FreqOut => Tacho_Freq
);
-- multiply by 64; divide by 2 for RPMs (2 impulses per revolution) => append 5x '0'
TachoFrequency <= resize(Tacho_Freq & "00000", TachoFrequency'length); -- resizing to 16 bit
end generate;
end;
|
apache-2.0
|
marzoul/PoC
|
src/arith/arith_prefix_or.vhdl
|
2
|
2917
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Description: Prefix OR computation: y(i) <= '0' when x(i downto 0) = (i downto 0 => '0') else '1'
-- This implementation uses carry chains for wider implementations.
--
-- Authors: Thomas B. Preusser
-- ================================================================================
-- Copyright 2007-2015 Technische Universität Dresden - Germany, Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ===================================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
library poc;
use poc.config.all;
entity arith_prefix_or is
generic (
N : positive
);
port (
x : in std_logic_vector(N-1 downto 0);
y : out std_logic_vector(N-1 downto 0)
);
end arith_prefix_or;
architecture rtl of arith_prefix_or is
begin
y(0) <= x(0);
gen1: if N > 1 generate
signal p : unsigned(N-1 downto 1);
begin
p(1) <= x(0) or x(1);
gen2: if N > 2 generate
-- Generic Carry Chain through Addition
genGeneric: if VENDOR /= VENDOR_XILINX generate
signal s : std_logic_vector(N downto 1);
begin
p(N-1 downto 2) <= unsigned(x(N-1 downto 2));
s <= std_logic_vector(('1' & p) - 1);
y(N-1 downto 2) <= s(N downto 3) xnor ('1' & x(N-1 downto 3));
end generate genGeneric;
-- Direct Carry Chain by MUXCY Instantiation
genXilinx: if VENDOR = VENDOR_XILINX generate
component MUXCY
port (
S : in std_logic;
DI : in std_logic;
CI : in std_logic;
O : out std_logic
);
end component;
constant d : std_logic_vector(N-2 downto 0) := (N-2 downto 1 => '1') & '0';
signal c : std_logic_vector(N-1 downto 0);
begin
p(N-1 downto 2) <= not unsigned(x(N-1 downto 2));
c(0) <= '1';
genChain: for i in 1 to N-1 generate
mux : MUXCY
port map (
S => p(i),
DI => d(i-1),
CI => c(i-1),
O => c(i)
);
end generate genChain;
y(N-1 downto 2) <= c(N-1 downto 2);
end generate genXilinx;
end generate gen2;
y(1) <= p(1);
end generate gen1;
end rtl;
|
apache-2.0
|
marzoul/PoC
|
src/mem/ocram/ocram_sdp.vhdl
|
1
|
6867
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Martin Zabel
-- Thomas B. Preusser
-- Patrick Lehmann
--
-- Module: Simple dual-port memory.
--
-- Description:
-- ------------------------------------
-- Inferring / instantiating simple dual-port memory, with:
-- * dual clock, clock enable,
-- * 1 read port plus 1 write port.
--
-- The generalized behavior across Altera and Xilinx FPGAs since
-- Stratix/Cyclone and Spartan-3/Virtex-5, respectively, is as follows:
--
-- The Altera M512/M4K TriMatrix memory (as found e.g. in Stratix and
-- Stratix II FPGAs) defines the minimum time after which the written data at
-- the write port can be read-out at read port again. As stated in the Stratix
-- Handbook, Volume 2, page 2-13, data is actually written with the falling
-- (instead of the rising) edge of the clock into the memory array. The write
-- itself takes the write-cycle time which is less or equal to the minimum
-- clock-period time. After this, the data can be read-out at the other port.
-- Consequently, data "d" written at the rising-edge of "wclk" at address
-- "wa" can be read-out at the read port from the same address with the
-- 2nd rising-edge of "rclk" following the falling-edge of "wclk".
-- If the rising-edge of "rclk" coincides with the falling-edge of "wclk"
-- (e.g. same clock signal), then it is counted as the 1st rising-edge of
-- "rclk" in this timing.
--
-- WARNING: The simulated behavior on RT-level is not correct.
--
-- TODO: add timing diagram
-- TODO: implement correct behavior for RT-level simulation
--
-- License:
-- ============================================================================
-- Copyright 2008-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library STD;
use STD.TextIO.all;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_textio.all;
library PoC;
use PoC.config.all;
use PoC.utils.all;
use PoC.strings.all;
entity ocram_sdp is
generic (
A_BITS : positive;
D_BITS : positive;
FILENAME : STRING := ""
);
port (
rclk : in std_logic; -- read clock
rce : in std_logic; -- read clock-enable
wclk : in std_logic; -- write clock
wce : in std_logic; -- write clock-enable
we : in std_logic; -- write enable
ra : in unsigned(A_BITS-1 downto 0); -- read address
wa : in unsigned(A_BITS-1 downto 0); -- write address
d : in std_logic_vector(D_BITS-1 downto 0); -- data in
q : out std_logic_vector(D_BITS-1 downto 0)); -- data out
end entity;
architecture rtl of ocram_sdp is
attribute ramstyle : string;
constant DEPTH : positive := 2**A_BITS;
begin
gInfer: if VENDOR = VENDOR_XILINX or VENDOR = VENDOR_ALTERA generate
-- RAM can be inferred correctly
-- Xilinx notes:
-- WRITE_MODE is set to WRITE_FIRST, but this also means that read data
-- is unknown on the opposite port. (As expected.)
-- Altera notes:
-- Setting attribute "ramstyle" to "no_rw_check" suppresses generation of
-- bypass logic, when 'clk1'='clk2' and 'ra' is feed from a register.
-- This is the expected behaviour.
-- With two different clocks, synthesis complains about an undefined
-- read-write behaviour, that can be ignored.
subtype word_t is std_logic_vector(D_BITS - 1 downto 0);
type ram_t is array(0 to DEPTH - 1) of word_t;
begin
genLoadFile : if (str_length(FileName) /= 0) generate
-- Read a *.mem or *.hex file
impure function ocram_ReadMemFile(FileName : STRING) return ram_t is
file FileHandle : TEXT open READ_MODE is FileName;
variable CurrentLine : LINE;
variable TempWord : STD_LOGIC_VECTOR((div_ceil(word_t'length, 4) * 4) - 1 downto 0);
variable Result : ram_t := (others => (others => '0'));
begin
-- discard the first line of a mem file
if (str_toLower(FileName(FileName'length - 3 to FileName'length)) = ".mem") then
readline(FileHandle, CurrentLine);
end if;
for i in 0 to DEPTH - 1 loop
exit when endfile(FileHandle);
readline(FileHandle, CurrentLine);
hread(CurrentLine, TempWord);
Result(i) := resize(TempWord, word_t'length);
end loop;
return Result;
end function;
signal ram : ram_t := ocram_ReadMemFile(FILENAME);
attribute ramstyle of ram : signal is "no_rw_check";
begin
process (wclk)
begin
if rising_edge(wclk) then
if (wce and we) = '1' then
ram(to_integer(wa)) <= d;
end if;
end if;
end process;
process (rclk)
begin
if rising_edge(rclk) then
-- read data doesn't care, when reading at write address
if rce = '1' then
--synthesis translate_off
if Is_X(std_logic_vector(ra)) then
q <= (others => 'X');
else
--synthesis translate_on
q <= ram(to_integer(ra));
--synthesis translate_off
end if;
--synthesis translate_on
end if;
end if;
end process;
end generate;
genNoLoadFile : if (str_length(FileName) = 0) generate
signal ram : ram_t;
attribute ramstyle of ram : signal is "no_rw_check";
begin
process (wclk)
begin
if rising_edge(wclk) then
if (wce and we) = '1' then
ram(to_integer(wa)) <= d;
end if;
end if;
end process;
process (rclk)
begin
if rising_edge(rclk) then
-- read data doesn't care, when reading at write address
if rce = '1' then
--synthesis translate_off
if Is_X(std_logic_vector(ra)) then
q <= (others => 'X');
else
--synthesis translate_on
q <= ram(to_integer(ra));
--synthesis translate_off
end if;
--synthesis translate_on
end if;
end if;
end process;
end generate;
end generate gInfer;
assert VENDOR = VENDOR_XILINX or VENDOR = VENDOR_ALTERA
report "Device not yet supported."
severity failure;
end rtl;
|
apache-2.0
|
marzoul/PoC
|
src/misc/stat/stat_Minimum.vhdl
|
2
|
5264
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Module: Counts the least significant data words
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library PoC;
use PoC.utils.all;
use PoC.vectors.all;
entity stat_Minimum is
generic (
DEPTH : POSITIVE := 8;
DATA_BITS : POSITIVE := 16;
COUNTER_BITS : POSITIVE := 16
);
port (
Clock : in STD_LOGIC;
Reset : in STD_LOGIC;
Enable : in STD_LOGIC;
DataIn : in STD_LOGIC_VECTOR(DATA_BITS - 1 downto 0);
Valids : out STD_LOGIC_VECTOR(DEPTH - 1 downto 0);
Minimums : out T_SLM(DEPTH - 1 downto 0, DATA_BITS - 1 downto 0);
Counts : out T_SLM(DEPTH - 1 downto 0, COUNTER_BITS - 1 downto 0)
);
end entity;
architecture rtl of stat_Minimum is
type T_TAG_MEMORY is array(NATURAL range <>) of UNSIGNED(DATA_BITS - 1 downto 0);
type T_COUNTER_MEMORY is array(NATURAL range <>) of UNSIGNED(COUNTER_BITS - 1 downto 0);
-- create matrix from vector-vector
function to_slm(usv : T_TAG_MEMORY) return t_slm is
variable slm : t_slm(usv'range, DATA_BITS - 1 downto 0);
begin
for i in usv'range loop
for j in DATA_BITS - 1 downto 0 loop
slm(i, j) := usv(i)(j);
end loop;
end loop;
return slm;
end function;
function to_slm(usv : T_COUNTER_MEMORY) return t_slm is
variable slm : t_slm(usv'range, COUNTER_BITS - 1 downto 0);
begin
for i in usv'range loop
for j in COUNTER_BITS - 1 downto 0 loop
slm(i, j) := usv(i)(j);
end loop;
end loop;
return slm;
end function;
signal DataIn_us : UNSIGNED(DataIn'range);
signal TagHit : STD_LOGIC_VECTOR(DEPTH - 1 downto 0);
signal MinimumHit : STD_LOGIC_VECTOR(DEPTH - 1 downto 0);
signal TagMemory : T_TAG_MEMORY(DEPTH - 1 downto 0) := (others => (others => '1'));
signal CounterMemory : T_COUNTER_MEMORY(DEPTH - 1 downto 0) := (others => (others => '0'));
signal MinimumIndex : STD_LOGIC_VECTOR(DEPTH - 1 downto 0) := ((DEPTH - 1) => '1', others => '0');
signal ValidMemory : STD_LOGIC_VECTOR(DEPTH - 1 downto 0) := (others => '0');
begin
DataIn_us <= unsigned(DataIn);
genTagHit : for i in 0 to DEPTH - 1 generate
TagHit(i) <= to_sl(TagMemory(i) = DataIn_us);
MinimumHit(i) <= to_sl(TagMemory(i) > DataIn_us);
end generate;
process(Clock)
variable NewMinimum_nxt : STD_LOGIC_VECTOR(DEPTH - 1 downto 0);
variable NewMinimum_idx : NATURAL;
variable TagHit_idx : NATURAL;
begin
NewMinimum_nxt := MinimumIndex(MinimumIndex'high - 1 downto 0) & MinimumIndex(MinimumIndex'high);
NewMinimum_idx := to_index(onehot2bin(NewMinimum_nxt));
TagHit_idx := to_index(onehot2bin(TagHit));
if rising_edge(Clock) then
if (Reset = '1') then
ValidMemory <= (others => '0');
elsif ((slv_nand(ValidMemory) and slv_nor(TagHit) and Enable) = '1') then
for i in DEPTH - 1 downto 1 loop
if (MinimumHit(i) = '1') then
TagMemory(i) <= TagMemory(i - 1);
ValidMemory(i) <= ValidMemory(i - 1);
CounterMemory(i) <= CounterMemory(i - 1);
end if;
end loop;
for i in 0 to DEPTH - 1 loop
if (MinimumHit(i) = '1') then
TagMemory(i) <= DataIn_us;
ValidMemory(i) <= '1';
CounterMemory(i) <= to_unsigned(1, COUNTER_BITS);
exit;
end if;
end loop;
elsif ((slv_or(MinimumHit) and slv_nor(TagHit) and Enable) = '1') then
for i in DEPTH - 1 downto 1 loop
if (MinimumHit(i) = '1') then
TagMemory(i) <= TagMemory(i - 1);
ValidMemory(i) <= ValidMemory(i - 1);
CounterMemory(i) <= CounterMemory(i - 1);
end if;
end loop;
for i in 0 to DEPTH - 1 loop
if (MinimumHit(i) = '1') then
TagMemory(i) <= DataIn_us;
ValidMemory(i) <= '1';
CounterMemory(i) <= to_unsigned(1, COUNTER_BITS);
exit;
end if;
end loop;
elsif ((slv_or(TagHit) and Enable)= '1') then
CounterMemory(TagHit_idx) <= CounterMemory(TagHit_idx) + 1;
end if;
end if;
end process;
Valids <= ValidMemory;
Minimums <= to_slm(TagMemory);
Counts <= to_slm(CounterMemory);
end architecture;
|
apache-2.0
|
marzoul/PoC
|
src/arith/arith_counter_gray.vhdl
|
2
|
4565
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Module: Gray-Code counter.
--
-- Authors: Thomas B. Preusser
-- Martin Zabel
-- Steffen Koehler
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- ============================================================================
-- Copyright 2007-2014 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity arith_counter_gray is
generic (
BITS : positive; -- Bit width of the counter
INIT : natural := 0 -- Initial/reset counter value
);
port (
clk : in std_logic;
rst : in std_logic; -- Reset to INIT value
inc : in std_logic; -- Increment
dec : in std_logic := '0'; -- Decrement
val : out std_logic_vector(BITS-1 downto 0); -- Value output
cry : out std_logic -- Carry output
);
end arith_counter_gray;
architecture rtl of arith_counter_gray is
-- purpose: gray constant encoder
function gray_encode (val : natural; len : positive) return unsigned is
variable bin : unsigned(len-1 downto 0) := to_unsigned(val, len);
begin
if len = 1 then
return bin;
end if;
return bin xor '0' & bin(len-1 downto 1);
end gray_encode;
-- purpose: parity generation
function parity (val : unsigned) return std_logic is
variable res : std_logic := '0';
begin -- parity
for i in val'range loop
res := res xor val(i);
end loop;
return res;
end parity;
-- Counter Register
constant INIT_GRAY : unsigned(BITS-1 downto 0) := gray_encode(INIT, BITS);
signal gray_cnt_r : unsigned(BITS-1 downto 0) := INIT_GRAY;
signal gray_cnt_nxt : unsigned(BITS-1 downto 0);
signal en : std_logic; -- enable: inc xor dec
begin
-----------------------------------------------------------------------------
-- Actual Counter Register
en <= inc xor dec;
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
gray_cnt_r <= INIT_GRAY;
elsif en = '1' then
gray_cnt_r <= gray_cnt_nxt;
end if;
end if;
end process;
val <= std_logic_vector(gray_cnt_r);
-----------------------------------------------------------------------------
-- Computation of Increment/Decrement
-- Trivial one-bit Counter
g1: if BITS = 1 generate
gray_cnt_nxt <= not gray_cnt_r;
cry <= gray_cnt_r(0) xor dec;
end generate g1;
-- Multi-Bit Counter
g2: if BITS > 1 generate
constant INIT_PAR : std_logic := parity(INIT_GRAY);
-- search for first one in gray_cnt_r(MSB-1 downto LSB)
-- first_one_n(i) = '1' denotes position i
-- parity of gray_cnt_r
signal par_r : std_logic := INIT_PAR;
signal par_nxt : std_logic;
begin
-- Parity Register
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
par_r <= INIT_PAR;
elsif en = '1' then
par_r <= par_nxt;
end if;
end if;
end process;
-- Computation of next Value
process(gray_cnt_r, par_r, dec)
variable x : unsigned(BITS-1 downto 0);
variable s : unsigned(BITS-1 downto 0);
begin
-- Prefer inc over dec to keep combinational path short in standard use.
x := gray_cnt_r(BITS-2 downto 0) & (par_r xnor dec);
x(x'left) := not gray_cnt_r(BITS-1); -- catch final carry to invert last bit
s := not x + 1; -- locate first intermediate '1'
gray_cnt_nxt <= s(BITS-1) & (gray_cnt_r(BITS-2 downto 0) xor
(s(BITS-2 downto 0) and x(BITS-2 downto 0)));
par_nxt <= s(0) xor dec;
end process;
cry <= ((gray_cnt_r(BITS-1) xor dec) and (gray_cnt_nxt(BITS-1) xnor dec));
end generate g2;
end rtl;
|
apache-2.0
|
marzoul/PoC
|
src/fifo/fifo_cc_got_tempgot.vhdl
|
2
|
13813
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================================================================================================
-- Module: FIFO, common clock (cc), pipelined interface,
-- reads only become effective after explicit commit
--
-- Authors: Thomas B. Preusser
-- Steffen Koehler
-- Martin Zabel
--
-- Description:
-- ------------------------------------
-- The specified depth (MIN_DEPTH) is rounded up to the next suitable value.
--
-- As uncommitted reads occupy FIFO space that is not yet available for
-- writing, an instance of this FIFO can, indeed, report 'full' and 'not vld'
-- at the same time. While a 'commit' would eventually make space available for
-- writing ('not ful'), a 'rollback' would re-iterate data for reading
-- ('vld').
--
-- 'commit' and 'rollback' are inclusive and apply to all reads ('got') since
-- the previous 'commit' or 'rollback' up to and including a potentially
-- simultaneous read.
--
-- The FIFO state upon a simultaneous assertion of 'commit' and 'rollback' is
-- *undefined*!
--
-- *STATE_*_BITS defines the granularity of the fill state indicator
-- '*state_*'. 'fstate_rd' is associated with the read clock domain and outputs
-- the guaranteed number of words available in the FIFO. 'estate_wr' is
-- associated with the write clock domain and outputs the number of words that
-- is guaranteed to be accepted by the FIFO without a capacity overflow. Note
-- that both these indicators cannot replace the 'full' or 'valid' outputs as
-- they may be implemented as giving pessimistic bounds that are minimally off
-- the true fill state.
--
-- If a fill state is not of interest, set *STATE_*_BITS = 0.
--
-- 'fstate_rd' and 'estate_wr' are combinatorial outputs and include an address
-- comparator (subtractor) in their path.
--
-- Examples:
-- - FSTATE_RD_BITS = 1: fstate_rd == 0 => 0/2 full
-- fstate_rd == 1 => 1/2 full (half full)
--
-- - FSTATE_RD_BITS = 2: fstate_rd == 0 => 0/4 full
-- fstate_rd == 1 => 1/4 full
-- fstate_rd == 2 => 2/4 full
-- fstate_rd == 3 => 3/4 full
--
-- License:
-- ============================================================================================================================================================
-- Copyright 2007-2014 Technische Universitaet Dresden - Germany, Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================================================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library poc;
use poc.config.all;
use poc.utils.all;
use poc.ocram.ocram_sdp;
entity fifo_cc_got_tempgot is
generic (
D_BITS : positive; -- Data Width
MIN_DEPTH : positive; -- Minimum FIFO Depth
DATA_REG : boolean := false; -- Store Data Content in Registers
STATE_REG : boolean := false; -- Registered Full/Empty Indicators
OUTPUT_REG : boolean := false; -- Registered FIFO Output
ESTATE_WR_BITS : natural := 0; -- Empty State Bits
FSTATE_RD_BITS : natural := 0 -- Full State Bits
);
port (
-- Global Reset and Clock
rst, clk : in std_logic;
-- Writing Interface
put : in std_logic; -- Write Request
din : in std_logic_vector(D_BITS-1 downto 0); -- Input Data
full : out std_logic;
estate_wr : out std_logic_vector(imax(0, ESTATE_WR_BITS-1) downto 0);
-- Reading Interface
got : in std_logic; -- Read Completed
dout : out std_logic_vector(D_BITS-1 downto 0); -- Output Data
valid : out std_logic;
fstate_rd : out std_logic_vector(imax(0, FSTATE_RD_BITS-1) downto 0);
commit : in std_logic;
rollback : in std_logic
);
end fifo_cc_got_tempgot;
architecture rtl of fifo_cc_got_tempgot is
-- Address Width
constant A_BITS : natural := log2ceil(MIN_DEPTH);
-- Force Carry-Chain Use for Pointer Increments on Xilinx Architectures
constant FORCE_XILCY : boolean := (not SIMULATION) and (VENDOR = VENDOR_XILINX) and STATE_REG and (A_BITS > 4);
-----------------------------------------------------------------------------
-- Memory Pointers
-- Actual Input and Output Pointers
signal IP0 : unsigned(A_BITS-1 downto 0) := (others => '0');
signal OP0 : unsigned(A_BITS-1 downto 0) := (others => '0');
-- Incremented Input and Output Pointers
signal IP1 : unsigned(A_BITS-1 downto 0);
signal OP1 : unsigned(A_BITS-1 downto 0);
-- Commited Read Pointer (Commit Marker)
signal OPm : unsigned(A_BITS-1 downto 0) := (others => '0');
-----------------------------------------------------------------------------
-- Backing Memory Connectivity
-- Write Port
signal wa : unsigned(A_BITS-1 downto 0);
signal we : std_logic;
-- Read Port
signal ra : unsigned(A_BITS-1 downto 0);
signal re : std_logic;
-- Internal full and empty indicators
signal fulli : std_logic;
signal empti : std_logic;
begin
-----------------------------------------------------------------------------
-- Pointer Logic
genCCN: if not FORCE_XILCY generate
IP1 <= IP0 + 1;
OP1 <= OP0 + 1;
end generate;
genCCY: if FORCE_XILCY generate
component MUXCY
port (
O : out std_ulogic;
CI : in std_ulogic;
DI : in std_ulogic;
S : in std_ulogic
);
end component;
component XORCY
port (
O : out std_ulogic;
CI : in std_ulogic;
LI : in std_ulogic
);
end component;
signal ci, co : std_logic_vector(A_BITS downto 0);
begin
ci(0) <= '1';
genCCI : for i in 0 to A_BITS-1 generate
MUXCY_inst : MUXCY
port map (
O => ci(i+1),
CI => ci(i),
DI => '0',
S => IP0(i)
);
XORCY_inst : XORCY
port map (
O => IP1(i),
CI => ci(i),
LI => IP0(i)
);
end generate genCCI;
co(0) <= '1';
genCCO: for i in 0 to A_BITS-1 generate
MUXCY_inst : MUXCY
port map (
O => co(i+1),
CI => co(i),
DI => '0',
S => OP0(i)
);
XORCY_inst : XORCY
port map (
O => OP1(i),
CI => co(i),
LI => OP0(i)
);
end generate genCCO;
end generate;
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
IP0 <= (others => '0');
OP0 <= (others => '0');
OPm <= (others => '0');
else
-- Update Input Pointer upon Write
if we = '1' then
IP0 <= IP1;
end if;
-- Update Output Pointer upon Read or Rollback
if rollback = '1' then
OP0 <= OPm;
elsif re = '1' then
OP0 <= OP1;
end if;
-- Update Commit Marker
if commit = '1' then
if re = '1' then
OPm <= OP1;
else
OPm <= OP0;
end if;
end if;
end if;
end if;
end process;
wa <= IP0;
ra <= OP0;
-- Fill State Computation (soft indicators)
process(fulli, IP0, OP0, OPm)
variable d : std_logic_vector(A_BITS-1 downto 0);
begin
-- Available Space
if ESTATE_WR_BITS > 0 then
-- Compute Pointer Difference
if fulli = '1' then
d := (others => '1'); -- true number minus one when full
else
d := std_logic_vector(IP0 - OPm); -- true number of valid entries
end if;
estate_wr <= not d(d'left downto d'left-ESTATE_WR_BITS+1);
else
estate_wr <= (others => 'X');
end if;
-- Available Content
if FSTATE_RD_BITS > 0 then
-- Compute Pointer Difference
if fulli = '1' then
d := (others => '1'); -- true number minus one when full
else
d := std_logic_vector(IP0 - OP0); -- true number of valid entries
end if;
fstate_rd <= d(d'left downto d'left-FSTATE_RD_BITS+1);
else
fstate_rd <= (others => 'X');
end if;
end process;
-----------------------------------------------------------------------------
-- Computation of full and empty indications.
--
-- The STATE_REG generic is ignored as two different comparators are
-- needed to compare IP with OPm (full) and IP with OP (empty) anyways.
-- So the register implementation is always used.
blkState: block
signal Ful : std_logic := '0';
signal Pnd : std_logic := '0';
signal Avl : std_logic := '0';
begin
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
Ful <= '0';
Pnd <= '0';
Avl <= '0';
else
-- Pending Indicator for uncommitted Data
if commit = '1' or rollback = '1' then
Pnd <= '0';
elsif re = '1' then
Pnd <= '1';
end if;
-- Update Full Indicator
if commit = '1' and (re = '1' or Pnd = '1') then
Ful <= '0';
elsif we = '1' and IP1 = OPm then
Ful <= '1';
end if;
-- Update Empty Indicator
if we = '1' or (rollback = '1' and Pnd = '1') then
Avl <= '1';
elsif re = '1' and we = '0' and OP1 = IP0 then
Avl <= '0';
end if;
end if;
end if;
end process;
fulli <= Ful;
empti <= not Avl;
end block;
-----------------------------------------------------------------------------
-- Memory Access
-- Write Interface => Input
full <= fulli;
we <= put and not fulli;
-- Backing Memory and Read Interface => Output
genLarge: if not DATA_REG generate
signal do : std_logic_vector(D_BITS-1 downto 0);
begin
-- Backing Memory
ram : ocram_sdp
generic map (
A_BITS => A_BITS,
D_BITS => D_BITS
)
port map (
wclk => clk,
rclk => clk,
wce => '1',
wa => wa,
we => we,
d => din,
ra => ra,
rce => re,
q => do
);
-- Read Interface => Output
genOutputCmb : if not OUTPUT_REG generate
signal Vld : std_logic := '0'; -- valid output of RAM module
begin
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
Vld <= '0';
else
Vld <= (Vld and not got) or not empti;
end if;
end if;
end process;
re <= (not Vld or got) and not empti;
dout <= do;
valid <= Vld;
end generate genOutputCmb;
genOutputReg: if OUTPUT_REG generate
-- Extra Buffer Register for Output Data
signal Buf : std_logic_vector(D_BITS-1 downto 0) := (others => '-');
signal Vld : std_logic_vector(0 to 1) := (others => '0');
-- Vld(0) -- valid output of RAM module
-- Vld(1) -- valid word in Buf
begin
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
Buf <= (others => '-');
Vld <= (others => '0');
else
Vld(0) <= (Vld(0) and Vld(1) and not got) or not empti;
Vld(1) <= (Vld(1) and not got) or Vld(0);
if Vld(1) = '0' or got = '1' then
Buf <= do;
end if;
end if;
end if;
end process;
re <= (not Vld(0) or not Vld(1) or got) and not empti;
dout <= Buf;
valid <= Vld(1);
end generate genOutputReg;
end generate genLarge;
genSmall: if DATA_REG generate
-- Memory modelled as Array
type regfile_t is array(0 to 2**A_BITS-1) of std_logic_vector(D_BITS-1 downto 0);
signal regfile : regfile_t;
attribute ram_style : string; -- XST specific
attribute ram_style of regfile : signal is "distributed";
-- Altera Quartus II: Allow automatic RAM type selection.
-- For small RAMs, registers are used on Cyclone devices and the M512 type
-- is used on Stratix devices. Pass-through logic is automatically added
-- if required. (Warning can be ignored.)
begin
-- Memory State
process(clk)
begin
if rising_edge(clk) then
--synthesis translate_off
if SIMULATION AND (rst = '1') then
regfile <= (others => (others => '-'));
else
--synthesis translate_on
if we = '1' then
regfile(to_integer(wa)) <= din;
end if;
--synthesis translate_off
end if;
--synthesis translate_on
end if;
end process;
-- Memory Output
re <= got and not empti;
dout <= (others => 'X') when Is_X(std_logic_vector(ra)) else
regfile(to_integer(ra));
valid <= not empti;
end generate genSmall;
end rtl;
|
apache-2.0
|
marzoul/PoC
|
tb/common/simulation.v08.vhdl
|
4
|
12321
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Patrick Lehmann
-- Thomas B. Preusser
--
-- Package: Simulation constants, functions and utilities.
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library PoC;
use PoC.vectors.all;
use PoC.strings.all;
use PoC.physical.all;
package simulation is
-- predefined constants to ease testvector concatenation
constant U8 : T_SLV_8 := (others => 'U');
constant U16 : T_SLV_16 := (others => 'U');
constant U24 : T_SLV_24 := (others => 'U');
constant U32 : T_SLV_32 := (others => 'U');
constant D8 : T_SLV_8 := (others => '-');
constant D16 : T_SLV_16 := (others => '-');
constant D24 : T_SLV_24 := (others => '-');
constant D32 : T_SLV_32 := (others => '-');
-- Testbench Status Management
-- ===========================================================================
-- VHDL'08: Provide a protected tSimStatus type that may be used for
-- other purposes as well. For compatibility with the VHDL'93
-- implementation, the plain procedure implementation is also
-- provided on top of a package private instance of this type.
type T_TB_STATUS is protected
-- The status is changed to failed. If a message is provided, it is
-- reported as an error.
procedure simFail(msg : in string := "");
-- If the passed condition has evaluated false, the status is marked
-- as failed. In this case, the optional message will be reported as
-- an error if provided.
procedure simAssert(cond : in boolean; msg : in string := "");
-- Prints the final status. Unless simFail() or simAssert() with a
-- false condition have been called before, a successful completion
-- will be indicated, a failure otherwise.
procedure simReport;
end protected;
type T_SIM_STATUS is protected
procedure stop;
impure function isStopped return BOOLEAN;
end protected;
-- The testbench is marked as failed. If a message is provided, it is
-- reported as an error.
procedure tbFail(msg : in string := "");
-- If the passed condition has evaluated false, the testbench is marked
-- as failed. In this case, the optional message will be reported as an
-- error if one was provided.
procedure tbAssert(cond : in boolean; msg : in string := "");
-- Prints out the overall testbench result as defined by the automated
-- testbench process. Unless tbFail() or tbAssert() with a false condition
-- have been called before, a successful completion will be reported, a
-- failure otherwise.
procedure tbPrintResult;
-- clock generation
-- ===========================================================================
subtype T_DutyCycle is REAL range 0.0 to 1.0;
procedure simStop;
impure function simIsStopped return BOOLEAN;
procedure simGenerateClock(signal Clock : out STD_LOGIC; constant Frequency : in FREQ; constant DutyCycle : T_DutyCycle := 0.5);
procedure simGenerateClock(signal Clock : out STD_LOGIC; constant Period : in TIME; constant DutyCycle : T_DutyCycle := 0.5);
-- waveform generation
-- ===========================================================================
type T_SIM_WAVEFORM_TUPLE_SL is record
Delay : TIME;
Value : STD_LOGIC;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_8 is record
Delay : TIME;
Value : T_SLV_8;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_16 is record
Delay : TIME;
Value : T_SLV_16;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_24 is record
Delay : TIME;
Value : T_SLV_24;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_32 is record
Delay : TIME;
Value : T_SLV_32;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_48 is record
Delay : TIME;
Value : T_SLV_48;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_64 is record
Delay : TIME;
Value : T_SLV_64;
end record;
type T_SIM_WAVEFORM_SL is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SL;
type T_SIM_WAVEFORM_SLV_8 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_8;
type T_SIM_WAVEFORM_SLV_16 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_16;
type T_SIM_WAVEFORM_SLV_24 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_24;
type T_SIM_WAVEFORM_SLV_32 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_32;
type T_SIM_WAVEFORM_SLV_48 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_48;
type T_SIM_WAVEFORM_SLV_64 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_64;
procedure simGenerateWaveform(signal Wave : out BOOLEAN; Waveform: T_TIMEVEC; InitialValue : BOOLEAN);
procedure simGenerateWaveform(signal Wave : out STD_LOGIC; Waveform: T_TIMEVEC; InitialValue : STD_LOGIC := '0');
procedure simGenerateWaveform(signal Wave : out STD_LOGIC; Waveform: T_SIM_WAVEFORM_SL; InitialValue : STD_LOGIC := '0');
procedure simGenerateWaveform(signal Wave : out T_SLV_8; Waveform: T_SIM_WAVEFORM_SLV_8; InitialValue : T_SLV_8);
procedure simGenerateWaveform(signal Wave : out T_SLV_16; Waveform: T_SIM_WAVEFORM_SLV_16; InitialValue : T_SLV_16);
procedure simGenerateWaveform(signal Wave : out T_SLV_24; Waveform: T_SIM_WAVEFORM_SLV_24; InitialValue : T_SLV_24);
procedure simGenerateWaveform(signal Wave : out T_SLV_32; Waveform: T_SIM_WAVEFORM_SLV_32; InitialValue : T_SLV_32);
procedure simGenerateWaveform(signal Wave : out T_SLV_48; Waveform: T_SIM_WAVEFORM_SLV_48; InitialValue : T_SLV_48);
procedure simGenerateWaveform(signal Wave : out T_SLV_64; Waveform: T_SIM_WAVEFORM_SLV_64; InitialValue : T_SLV_64);
function simGenerateWaveform_Reset(constant Pause : TIME := 0 ns; ResetPulse : TIME := 10 ns) return T_TIMEVEC;
end;
use std.TextIO.all;
package body simulation is
-- Testbench Status Management
-- ===========================================================================
type T_TB_STATUS is protected body
-- Internal state variable to log a failure condition for final reporting.
-- Once de-asserted, this variable will never return to a value of true.
variable pass : boolean := true;
procedure simFail(msg : in string := "") is
begin
if msg'length > 0 then
report msg severity error;
end if;
pass := false;
end;
procedure simAssert(cond : in boolean; msg : in string := "") is
begin
if not cond then
simFail(msg);
end if;
end;
procedure simReport is
variable l : line;
begin
write(l, string'("SIMULATION RESULT = "));
if pass then
write(l, string'("PASSED"));
else
write(l, string'("FAILED"));
end if;
writeline(output, l);
end;
end protected body;
type T_SIM_STATUS is protected body
variable stopped : BOOLEAN := FALSE;
procedure stop is
begin
stopped := TRUE;
end procedure;
impure function isStopped return BOOLEAN is
begin
return stopped;
end function;
end protected body;
-- The default global tSimStatus object.
shared variable tbStatus : T_TB_STATUS;
shared variable simStatus : T_SIM_STATUS;
-- legacy procedures
-- ===========================================================================
procedure tbFail(msg : in string := "") is
begin
tbStatus.simFail(msg);
end;
procedure tbAssert(cond : in boolean; msg : in string := "") is
begin
tbStatus.simAssert(cond, msg);
end;
procedure tbPrintResult is
begin
tbStatus.simReport;
end procedure;
-- clock generation
-- ===========================================================================
procedure simStop is
begin
simStatus.stop;
end procedure;
impure function simIsStopped return BOOLEAN is
begin
return simStatus.isStopped;
end function;
procedure simGenerateClock(signal Clock : out STD_LOGIC; constant Frequency : in FREQ; constant DutyCycle : T_DutyCycle := 0.5) is
constant Period : TIME := to_time(Frequency);
begin
simGenerateClock(Clock, Period, DutyCycle);
end procedure;
procedure simGenerateClock(signal Clock : out STD_LOGIC; constant Period : in TIME; constant DutyCycle : T_DutyCycle := 0.5) is
constant TIME_HIGH : TIME := Period * DutyCycle;
constant TIME_LOW : TIME := Period - TIME_HIGH;
begin
Clock <= '0';
while (not simStatus.isStopped) loop
wait for TIME_LOW;
Clock <= '1';
wait for TIME_HIGH;
Clock <= '0';
end loop;
end procedure;
-- waveform generation
-- ===========================================================================
procedure simGenerateWaveform(signal Wave : out BOOLEAN; Waveform : T_TIMEVEC; InitialValue : BOOLEAN) is
variable State : BOOLEAN := InitialValue;
begin
Wave <= State;
for i in Waveform'range loop
wait for Waveform(i);
State := not State;
Wave <= State;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out STD_LOGIC; Waveform: T_TIMEVEC; InitialValue : STD_LOGIC := '0') is
variable State : STD_LOGIC := InitialValue;
begin
Wave <= State;
for i in Waveform'range loop
wait for Waveform(i);
State := not State;
Wave <= State;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out STD_LOGIC; Waveform: T_SIM_WAVEFORM_SL; InitialValue : STD_LOGIC := '0') is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out T_SLV_8; Waveform: T_SIM_WAVEFORM_SLV_8; InitialValue : T_SLV_8) is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out T_SLV_16; Waveform: T_SIM_WAVEFORM_SLV_16; InitialValue : T_SLV_16) is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out T_SLV_24; Waveform: T_SIM_WAVEFORM_SLV_24; InitialValue : T_SLV_24) is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out T_SLV_32; Waveform: T_SIM_WAVEFORM_SLV_32; InitialValue : T_SLV_32) is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out T_SLV_48; Waveform: T_SIM_WAVEFORM_SLV_48; InitialValue : T_SLV_48) is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out T_SLV_64; Waveform: T_SIM_WAVEFORM_SLV_64; InitialValue : T_SLV_64) is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
end loop;
end procedure;
function simGenerateWaveform_Reset(constant Pause : TIME := 0 ns; ResetPulse : TIME := 10 ns) return T_TIMEVEC is
begin
return (0 => Pause, 1 => ResetPulse);
end function;
end package body;
|
apache-2.0
|
TheClams/SmartVHDL
|
syntax_test.vhd
|
1
|
1665
|
-- SYNTAX TEST "VHDL.sublime-syntax"
architecture tmp_arc of tmp is
-- ^^^^^^^ meta.block.architecture meta.block.architecture.begin.vhdl entity.name.type.architecture.begin.vhdl
-- ^^^ entity.name.type.entity.reference.vhdl
signal clk : std_logic;
--^^^^^^ meta.block.signal.vhdl keyword.language.vhdl
-- ^ meta.block.signal.vhdl punctuation.vhdl
-- ^^^^^^^^^ storage.type.ieee.std_logic_1164.vhdl
signal rst : std_logic;
begin
test_proc: process is
--^^^^^^^^^ meta.block.process.vhdl entity.name.section.process.begin.vhdl
-- ^^^^^^^ keyword.language.vhdl
wait on clk until rising_edge(clk) and rst = '0' for 20 ns;
-- ^^^^ keyword.language.vhdl
-- ^^^^^ keyword.language.vhdl
-- ^^^^^^^^^^^ support.function.ieee.std_logic_1164.vhdl
-- ^^^ keyword.operator.word.vhdl
-- ^^^ keyword.language.vhdl
-- ^^ storage.type.std.standard.vhdl
wait for c_stim_cycle - (now - v_start_time);
-- ^^^ storage.type.std.standard.vhdl
end process;
report "current time = " & time'image(now);
-- ^^^^^^^^^^^^^^^^^ string.quoted.double.vhdl
-- ^ keyword.operator.vhdl
-- ^^^^ storage.type.std.standard.vhdl
-- ^^^^^^ variable.other.member.vhdl
-- ^^^ storage.type.std.standard.vhdl
end tmp_arc;
-- ^^^^^^^ meta.block.architecture entity.name.type.architecture.end.vhdl
|
apache-2.0
|
pgavin/carpe
|
hdl/sim/mem_1rw-behav.vhdl
|
1
|
13165
|
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
use std.textio.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library util;
use util.names_pkg.all;
use util.numeric_pkg.all;
use util.io_pkg.all;
use work.options_pkg.all;
architecture behav of mem_1rw is
constant addr_lo_bits : integer := addr_bits / 2;
constant addr_hi_bits : integer := addr_bits - addr_lo_bits;
subtype addr_type is std_ulogic_vector(addr_bits-1 downto 0);
subtype addr_hi_type is std_ulogic_vector(addr_hi_bits-1 downto 0);
subtype addr_lo_type is std_ulogic_vector(addr_lo_bits-1 downto 0);
constant byte_bits : integer := 2**log2_byte_bits;
constant bus_bytes : integer := 2**log2_bus_bytes;
constant bus_bits : integer := 2**(log2_byte_bits+log2_bus_bytes);
constant size_bits : integer := bitsize(log2_bus_bytes);
subtype byte_type is std_ulogic_vector(byte_bits-1 downto 0);
subtype bus_type is std_ulogic_vector(bus_bits-1 downto 0);
subtype size_type is std_ulogic_vector(size_bits-1 downto 0);
constant entry_size : integer := 2**addr_lo_bits;
constant num_entries : integer := 2**addr_hi_bits;
type entry_type is array (0 to entry_size-1) of std_ulogic_vector(byte_bits-1 downto 0);
type entry_ptr is access entry_type;
type entry_array_type is array (0 to num_entries-1) of entry_ptr;
subtype mask_type is std_ulogic_vector(2**log2_bus_bytes-1 downto 0);
procedure check_addr(v_addr : in addr_type) is
variable templine : line;
begin
if is_x(v_addr) then
write(templine, string'("invalid address: "));
write(templine, v_addr);
assert not is_x(v_addr) report templine.all severity warning;
deallocate(templine);
end if;
end procedure check_addr;
procedure check_size(v_size : in size_type) is
variable templine : line;
begin
if is_x(v_size) or to_integer(unsigned(v_size)) > log2_bus_bytes then
write(templine, string'("invalid size: "));
write(templine, v_size);
assert not is_x(v_size) report templine.all severity warning;
deallocate(templine);
end if;
end procedure check_size;
procedure check_be(v_be : in std_ulogic) is
variable templine : line;
begin
if is_x(v_be) then
write(templine, string'("invalid endianness flag: "));
write(templine, v_be);
assert not is_x(v_be) report templine.all severity warning;
deallocate(templine);
end if;
end procedure check_be;
procedure check_align(v_addr : in addr_type; v_size : in size_type) is
variable templine : line;
variable v_mask : addr_type;
variable v_size_n : integer;
begin
v_mask := (others => '0');
v_size_n := to_integer(unsigned(v_size));
if v_size_n > 0 then
for n in v_size_n-1 downto 0 loop
v_mask(n) := '1';
end loop;
end if;
if (v_addr and v_mask) /= (addr_bits-1 downto 0 => '0') then
write(templine, string'("invalid alignment: addr "));
write(templine, v_addr);
write(templine, string'(", size "));
write(templine, v_size);
assert (v_addr and v_mask) /= (addr_bits-1 downto 0 => '0') report templine.all severity warning;
deallocate(templine);
end if;
end procedure check_align;
procedure split_addr(v_addr : in addr_type;
v_addr_hi : out addr_hi_type;
v_addr_lo : out addr_lo_type) is
begin
v_addr_hi := v_addr(addr_bits-1 downto addr_lo_bits);
v_addr_lo := v_addr(addr_lo_bits-1 downto 0);
end procedure split_addr;
type memory_type is protected
procedure clear;
procedure init_addr(v_addr : in addr_type);
procedure read_byte(v_addr : in addr_type;
v_byte : out byte_type);
procedure write_byte(v_addr : in addr_type;
v_byte : in byte_type);
end protected;
type memory_type is protected body
variable entries : entry_array_type;
procedure clear is
begin
for n in 0 to num_entries-1 loop
if entries(n) /= null then
deallocate(entries(n));
entries(n) := null;
end if;
end loop;
end procedure clear;
procedure init_addr(v_addr : in addr_type) is
variable v_addr_hi : addr_hi_type;
variable v_addr_lo : addr_lo_type;
begin
split_addr(v_addr, v_addr_hi, v_addr_lo);
if entries(to_integer(unsigned(v_addr_hi))) = null then
entries(to_integer(unsigned(v_addr_hi))) := new entry_type'(others => (others => '0'));
end if;
end procedure init_addr;
procedure read_byte(v_addr : in addr_type;
v_byte : out byte_type) is
variable v_addr_hi : addr_hi_type;
variable v_addr_lo : addr_lo_type;
begin
check_addr(v_addr);
init_addr(v_addr);
if not is_x(v_addr) then
split_addr(v_addr, v_addr_hi, v_addr_lo);
v_byte := entries(to_integer(unsigned(v_addr_hi)))(to_integer(unsigned(v_addr_lo)));
else
v_byte := (others => 'X');
end if;
end procedure read_byte;
procedure write_byte(v_addr : in addr_type;
v_byte : in byte_type) is
variable v_addr_hi : addr_hi_type;
variable v_addr_lo : addr_lo_type;
variable v_templine : line;
begin
check_addr(v_addr);
init_addr(v_addr);
if not is_x(v_addr) then
--if is_x(v_byte) then
-- write(v_templine, string'("warning: writing uninitialized data to address "));
-- write(v_templine, v_addr);
-- write(v_templine, string'(" (data: "));
-- write(v_templine, v_byte);
-- write(v_templine, string'(")"));
-- report v_templine.all severity warning;
-- deallocate(v_templine);
--end if;
split_addr(v_addr, v_addr_hi, v_addr_lo);
entries(to_integer(unsigned(v_addr_hi)))(to_integer(unsigned(v_addr_lo))) := v_byte;
end if;
end procedure write_byte;
end protected body;
shared variable memory : memory_type;
procedure read_bus(v_addr : in addr_type;
v_size : in size_type;
v_be : in std_ulogic;
v_bus : out bus_type) is
variable v_byte_addr : addr_type;
variable v_byte : std_ulogic_vector(byte_bits-1 downto 0);
variable v_bus_tmp : bus_type;
variable v_size_n : integer;
variable v_bus_off : integer;
begin
check_addr(v_addr);
check_size(v_size);
check_be(v_be);
check_align(v_addr, v_size);
v_bus_tmp := (others => 'X');
v_size_n := 2**to_integer(unsigned(v_size));
v_bus_off := 0;
while v_bus_off <= v_size_n-1 loop
v_byte_addr := std_ulogic_vector(unsigned(v_addr) + to_unsigned(v_bus_off, addr_bits));
memory.read_byte(v_byte_addr, v_byte);
if v_be = '1' then
v_bus_tmp(v_size_n*byte_bits-byte_bits*v_bus_off-1 downto v_size_n*byte_bits-byte_bits*(v_bus_off+1)) := v_byte;
else
v_bus_tmp(byte_bits*(v_bus_off+1)-1 downto byte_bits*v_bus_off) := v_byte;
end if;
v_bus_off := v_bus_off + 1;
end loop;
v_bus := v_bus_tmp;
end procedure read_bus;
procedure write_bus(v_addr : in addr_type;
v_size : in size_type;
v_be : std_ulogic;
v_bus : in bus_type) is
variable v_byte_addr : addr_type;
variable v_byte : std_ulogic_vector(byte_bits-1 downto 0);
variable v_size_n : integer;
variable v_bus_off : integer;
begin
check_addr(v_addr);
check_size(v_size);
check_be(v_be);
check_align(v_addr, v_size);
v_size_n := 2**to_integer(unsigned(v_size));
v_bus_off := 0;
while v_bus_off <= v_size_n-1 loop
v_byte_addr := std_ulogic_vector(unsigned(v_addr) + to_unsigned(v_bus_off, addr_bits));
if v_be = '1' then
v_byte := v_bus(v_size_n*byte_bits-byte_bits*v_bus_off-1 downto v_size_n*byte_bits-byte_bits*(v_bus_off+1));
else
v_byte := v_bus(byte_bits*(v_bus_off+1)-1 downto byte_bits*v_bus_off);
end if;
memory.write_byte(v_byte_addr, v_byte);
v_bus_off := v_bus_off + 1;
end loop;
end procedure write_bus;
procedure read_srec is
variable filename : line;
file srecfile : text;
variable c : character;
variable srecline : line;
variable srectype : character;
variable srecdatalenv : std_ulogic_vector(byte_bits-1 downto 0);
variable srecdatalen : integer;
variable srecaddrtmp : std_ulogic_vector(31 downto 0);
variable srecaddr : addr_type;
variable srecbyte : byte_type;
variable templine : line;
begin
filename := new string'(option(entity_path_name(mem_1rw'path_name) & ":srec_file"));
assert filename.all /= ""
report "option " & entity_path_name(mem_1rw'path_name) & ":srec_file not set"
severity failure;
file_open(srecfile, filename.all, read_mode);
deallocate(filename);
while not endfile(srecfile) loop
readline(srecfile, srecline);
--report "read line: " & srecline.all;
read(srecline, c);
if c /= 'S' and c /= 's' then
next;
end if;
read(srecline, srectype);
case srectype is
when '1'|'2'|'3' =>
null;
when others =>
next;
end case;
hread(srecline, srecdatalenv);
srecdatalen := to_integer(unsigned(srecdatalenv));
srecaddrtmp := (others => '0');
case srectype is
when '1' =>
hread(srecline, srecaddrtmp(15 downto 0));
srecdatalen := srecdatalen - 2;
when '2' =>
hread(srecline, srecaddrtmp(23 downto 0));
srecdatalen := srecdatalen - 3;
when '3' =>
hread(srecline, srecaddrtmp(31 downto 0));
srecdatalen := srecdatalen - 4;
when others =>
next;
end case;
if addr_bits = 32 then
srecaddr := srecaddrtmp;
elsif addr_bits > 32 then
srecaddr(addr_bits-1 downto 32) := (others => '0');
srecaddr(31 downto 0) := srecaddrtmp;
else
srecaddr(addr_bits-1 downto 0) := srecaddrtmp(addr_bits-1 downto 0);
end if;
-- ignore checksum byte
srecdatalen := srecdatalen - 1;
for n in 0 to srecdatalen-1 loop
hread(srecline, srecbyte);
memory.write_byte(srecaddr, srecbyte);
srecaddr := std_ulogic_vector(unsigned(srecaddr) + to_unsigned(1, 32));
end loop;
end loop;
--report "done.";
file_close(srecfile);
end procedure read_srec;
begin
seq : process(clk)
variable v_dout : bus_type;
variable templine : line;
begin
if rising_edge(clk) then
case rstn is
when '0' =>
memory.clear;
read_srec;
when '1' =>
case en is
when '1' =>
case we is
when '1' =>
write_bus(addr, size, be, din);
when '0' =>
read_bus(addr, size, be, v_dout);
dout <= v_dout;
when others =>
assert not is_x(we)
report "we is metavalue"
severity warning;
end case;
when '0' =>
when others =>
assert not is_x(en)
report "en is metavalue"
severity warning;
end case;
when others =>
assert not is_x(rstn)
report "rstn is metavalue"
severity warning;
end case;
end if;
end process;
end;
|
apache-2.0
|
Paebbels/pauloBlaze
|
testbench/tb_lockstep.vhd
|
2
|
7835
|
-- EMACS settings: -*- tab-width: 4; indent-tabs-mode: t -*-
-- vim: tabstop=4:shiftwidth=4:noexpandtab
-- kate: tab-width 4; replace-tabs off; indent-width 4;
--
-- =============================================================================
-- Authors: Paul Genssler
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- =============================================================================
-- Copyright 2007-2019 Paul Genssler - Germany
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS is" BASIS,
-- WITHOUT WARRANTIES or CONDITIONS of ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
use ieee.math_real.all;
use work.op_codes.all;
ENTITY tb_lockstep IS
END tb_lockstep;
ARCHITECTURE behavior OF tb_lockstep IS
--Inputs
signal clk : std_logic := '0';
signal clk_5ns_delayed : std_logic := '0';
signal clk_5ns_enable : std_logic := '0';
signal reset : std_logic := '0';
signal sleep : std_logic := '0';
signal instruction : std_logic_vector(17 downto 0) := (others => '0');
signal in_port : std_logic_vector(7 downto 0) := (others => '0');
signal in_port_del : std_logic_vector(7 downto 0) := (others => '0');
signal interrupt : std_logic := '0';
--Outputs
signal address : std_logic_vector(11 downto 0);
signal bram_enable : std_logic;
signal out_port : std_logic_vector(7 downto 0);
signal port_id : std_logic_vector(7 downto 0);
signal write_strobe : std_logic;
signal k_write_strobe : std_logic;
signal read_strobe : std_logic;
signal interrupt_ack : std_logic;
-- PicoBlaze Outputs
signal pico_address : std_logic_vector(11 downto 0);
signal pico_instruction : std_logic_vector(17 downto 0) := (others => '0');
signal pico_bram_enable : std_logic;
signal pico_out_port : std_logic_vector(7 downto 0);
signal pico_port_id : std_logic_vector(7 downto 0);
signal pico_write_strobe : std_logic;
signal pico_k_write_strobe : std_logic;
signal pico_read_strobe : std_logic;
signal pico_interrupt_ack : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
type io_data is array (0 to 4) of unsigned(7 downto 0);
signal data : io_data := (x"00", x"AB", x"CD", x"12", x"00");
signal prog_mem_en : std_logic;
signal done : std_logic;
signal pico_done : std_logic;
signal sleep_en : std_logic := '1';
signal inter_en : std_logic := '1';
signal reset_en : std_logic := '1';
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: entity work.pauloBlaze
generic map (
debug => true,
interrupt_vector => x"300",
hwbuild => x"41",
scratch_pad_memory_size => 64 )
PORT MAP (
-- clk => clk_5ns_delayed,
clk => clk,
reset => reset,
sleep => sleep,
address => address,
instruction => instruction,
bram_enable => bram_enable,
in_port => in_port,
out_port => out_port,
port_id => port_id,
write_strobe => write_strobe,
k_write_strobe => k_write_strobe,
read_strobe => read_strobe,
interrupt => interrupt,
interrupt_ack => interrupt_ack );
-- end port map
picoblaze: entity work.kcpsm6
generic map ( hwbuild => X"41",
interrupt_vector => X"300",
scratch_pad_memory_size => 64)
port map( address => pico_address,
instruction => pico_instruction,
bram_enable => pico_bram_enable,
port_id => pico_port_id,
write_strobe => pico_write_strobe,
k_write_strobe => pico_k_write_strobe,
out_port => pico_out_port,
read_strobe => pico_read_strobe,
in_port => in_port,
interrupt => interrupt,
interrupt_ack => pico_interrupt_ack,
sleep => sleep,
reset => reset,
clk => clk);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
sleeping : process begin
if (sleep_en = '1') then
wait for 1035 ns;
sleep <= '1';
wait for 1 * clk_period;
sleep <= '0';
wait for 5000 ns;
sleep <= '1';
wait for 7 * clk_period;
sleep <= '0';
end if;
wait;
end process sleeping;
inter_static : process
begin
if (inter_en = '1') then
wait for 490 ns;
interrupt <= '1';
wait for 3 * clk_period;
interrupt <= '0';
wait for 875 ns;
interrupt <= '1';
wait until interrupt_ack = '1';
interrupt <= '0';
end if;
wait;
end process inter_static;
prog_mem : entity work.code_loader
Port map (
address => address,
instruction => instruction,
enable => bram_enable,
done => done,
rdl => open,
clk => clk);
prog_mem_pico : entity work.code_loader
Port map (
address => pico_address,
instruction => pico_instruction,
enable => pico_bram_enable,
done => pico_done,
rdl => open,
clk => clk);
reset_proc: process
begin
reset <= '1';
wait until (done = '1' and pico_done = '1');
wait until clk = '0';
reset <= '0';
if (reset_en = '1') then
wait for 465 ns;
reset <= '1';
wait for 86 ns;
reset <= '0';
end if;
wait for 1337 ns;
wait until rising_edge(clk);
if (reset_en = '1') then
wait for 85 ns;
reset <= '1';
wait for 35 ns;
reset <= '0';
end if;
wait;
end process;
process begin
wait for 20 ns;
in_port <= in_port_del;
end process;
data_in_proc : process (port_id) begin
case (port_id) is
when x"05" =>
in_port_del <= x"F3";
when others =>
in_port_del <= port_id;
end case;
end process data_in_proc;
compare_process: process begin
wait until reset = '0';
loop
wait until rising_edge(clk);
wait until rising_edge(clk);
assert pico_address = address report "address is different" severity error;
assert pico_bram_enable = bram_enable report "bram_enable is different" severity error;
assert pico_write_strobe = write_strobe report "write_strobe is different" severity error;
assert pico_k_write_strobe = k_write_strobe report "k_write_strobe is different" severity error;
if (pico_write_strobe = '1' or write_strobe = '1' or
pico_k_write_strobe = '1' or k_write_strobe = '1' ) then
assert pico_out_port = out_port report "out_port is different" severity error;
if (pico_k_write_strobe = '1' or k_write_strobe = '1' ) then
assert pico_port_id(3 downto 0) = port_id(3 downto 0) report "port_id is different" severity error;
else
assert pico_port_id = port_id report "port_id is different" severity error;
end if;
end if;
assert pico_read_strobe = read_strobe report "read_strobe is different" severity error;
assert pico_interrupt_ack = interrupt_ack report "interrupt_ack is different" severity error;
end loop;
end process;
END;
|
apache-2.0
|
Paebbels/pauloBlaze
|
sources/regFile.vhd
|
2
|
3984
|
-- EMACS settings: -*- tab-width: 4; indent-tabs-mode: t -*-
-- vim: tabstop=4:shiftwidth=4:noexpandtab
-- kate: tab-width 4; replace-tabs off; indent-width 4;
--
-- =============================================================================
-- Authors: Paul Genssler
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Paul Genssler - Dresden, Germany
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS is" BASIS,
-- WITHOUT WARRANTIES or CONDITIONS of ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.op_codes.all;
entity reg_file is
generic (
debug : boolean := false;
scratch_pad_memory_size : integer := 64
);
port (
clk : in std_logic;
value : in unsigned (7 downto 0);
write_en : in std_logic;
reg0 : out unsigned (7 downto 0);
reg1 : out unsigned (7 downto 0);
reg_address : in unsigned (7 downto 0);
reg_select : in std_logic;
reg_star : in std_logic;
spm_addr_ss : in unsigned (7 downto 0);
spm_ss : in std_logic; -- 0: spm_addr = reg1, 1: spm_addr = spm_addr_ss
spm_we : in std_logic;
spm_rd : in std_logic
);
end reg_file;
architecture Behavioral of reg_file is
-- Logarithms: log*ceil*
-- From PoC-Library https://github.com/VLSI-EDA/PoC
-- ==========================================================================
function log2ceil(arg : positive) return natural is
variable tmp : positive := 1;
variable log : natural := 0;
begin
if arg = 1 then return 0; end if;
while arg > tmp loop
tmp := tmp * 2;
log := log + 1;
end loop;
return log;
end function;
type reg_file_t is array (31 downto 0) of unsigned(7 downto 0);
signal reg : reg_file_t := (others=>(others=>'0'));
type scratchpad_t is array(integer range <>) of unsigned(7 downto 0);
signal scratchpad : scratchpad_t((scratch_pad_memory_size-1) downto 0) := (others=>(others=>'0'));
constant spm_addr_width : integer := log2ceil(scratch_pad_memory_size); -- address failsafes into a truncated one
signal spm_addr : unsigned ( spm_addr_width-1 downto 0);
signal spm_read : unsigned (7 downto 0);
signal reg0_buf : unsigned ( 7 downto 0);
signal reg0_o : unsigned ( 7 downto 0);
signal reg1_buf : unsigned ( 7 downto 0);
signal reg1_o : unsigned ( 7 downto 0);
signal reg_wr_data : unsigned ( 7 downto 0);
begin
reg0 <= reg0_o;
reg1 <= reg1_o;
reg_wr_data <= spm_read when spm_rd = '1' else value when reg_star = '0' else reg1_buf;
spm_addr <= spm_addr_ss(spm_addr_width -1 downto 0) when spm_ss = '1' else reg1_buf(spm_addr_width -1 downto 0);
spm_read <= scratchpad(to_integer(spm_addr));
reg0_o <= reg(to_integer(reg_select & reg_address(7 downto 4)));
reg1_o <= reg(to_integer(reg_select & reg_address(3 downto 0)));
write_reg : process (clk) begin
if rising_edge(clk) then
if (write_en = '1') then
reg(to_integer(reg_select & reg_address(7 downto 4))) <= reg_wr_data;
end if;
end if;
end process write_reg;
write_spm : process (clk) begin
if rising_edge(clk) then
if (spm_we = '1') then
scratchpad(to_integer(spm_addr)) <= reg0_buf;
end if;
end if;
end process write_spm;
buf_reg0_p : process (clk) begin
if rising_edge(clk) then
reg0_buf <= reg0_o;
reg1_buf <= reg1_o;
end if;
end process buf_reg0_p;
end Behavioral;
|
apache-2.0
|
willtmwu/vhdlExamples
|
BCD Adder/Simple/bcd_1_adder.vhd
|
1
|
1482
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity bcd_1_adder is
port (
A: in STD_LOGIC_VECTOR (3 downto 0);
B: in STD_LOGIC_VECTOR (3 downto 0);
C_IN: in STD_LOGIC;
SUM: out STD_LOGIC_VECTOR (3 downto 0);
C_OUT: out STD_LOGIC
);
end bcd_1_adder;
--algorithm
-- If A + B <= 9 then -- assume both A and B are valid BCD numbers
-- RESULT = A + B ;
-- CARRY = 0 ;
-- else
-- RESULT = A + B + 6 ;
-- CARRY = 1;
-- end if ;
architecture bcd_1_adder_arch of bcd_1_adder is
begin
--BCD adder logic
process (A,B,C_IN)
variable temp : std_logic_vector(3 downto 0);
variable overflow : boolean;
begin
temp := A + B + C_IN;
overflow := A(0) and B(0) and A(1) and B(1) and A(2) and B(2) and A(3) and B(3) and C_IN;
if (temp <= 9) then
SUM <= temp + overflow*6;
C_OUT <= overflow;
else
SUM <= (temp + 6);
C_OUT <= '1';
end if;
-- if (A >0 and B >0 and A + B < 9) then
-- SUM <= temp+6;
-- C_OUT <= '1';
-- else
-- if ( temp <= 9 ) then
-- SUM <= temp;
-- C_OUT <= '0';
-- else
-- SUM <= (temp + 6);
-- C_OUT <= '1';
-- end if;
-- end if;
-- if ( ('0'&A) + ('0'&B) + C_IN <= 9 ) then
-- SUM <= (A + B + C_IN);
-- C_OUT <= '0';
-- else
-- SUM <= (A + B + C_IN + 6);
-- C_OUT <= '1';
-- end if;
end process;
end bcd_1_adder_arch;
|
apache-2.0
|
zambreno/RCL
|
sccCyGraph/coregen/fifo_generator_1_s512.vhd
|
1
|
136365
|
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: O.87xd
-- \ \ Application: netgen
-- / / Filename: fifo_generator_1_s512.vhd
-- /___/ /\ Timestamp: Mon Aug 18 13:51:53 2014
-- \ \ / \
-- \___\/\___\
--
-- Command : -w -sim -ofmt vhdl /home/ogamal/coregen/tmp/_cg/fifo_generator_1_s512.ngc /home/ogamal/coregen/tmp/_cg/fifo_generator_1_s512.vhd
-- Device : 5vlx330ff1760-2
-- Input file : /home/ogamal/coregen/tmp/_cg/fifo_generator_1_s512.ngc
-- Output file : /home/ogamal/coregen/tmp/_cg/fifo_generator_1_s512.vhd
-- # of Entities : 1
-- Design Name : fifo_generator_1_s512
-- Xilinx : /remote/Xilinx/13.4/ISE/
--
-- Purpose:
-- This VHDL netlist is a verification model and uses simulation
-- primitives which may not represent the true implementation of the
-- device, however the netlist is functionally correct and should not
-- be modified. This file cannot be synthesized and should only be used
-- with supported simulation tools.
--
-- Reference:
-- Command Line Tools User Guide, Chapter 23
-- Synthesis and Simulation Design Guide, Chapter 6
--
--------------------------------------------------------------------------------
-- synthesis translate_off
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;
entity fifo_generator_1_s512 is
port (
clk : in STD_LOGIC := 'X';
rd_en : in STD_LOGIC := 'X';
almost_full : out STD_LOGIC;
rst : in STD_LOGIC := 'X';
empty : out STD_LOGIC;
wr_en : in STD_LOGIC := 'X';
valid : out STD_LOGIC;
full : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 0 downto 0 );
din : in STD_LOGIC_VECTOR ( 0 downto 0 )
);
end fifo_generator_1_s512;
architecture STRUCTURE of fifo_generator_1_s512 is
signal N0 : STD_LOGIC;
signal N1 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_0_1 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_0_2 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_0_3 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_1_1 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_1_2 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_1_3 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_2_1 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_2_2 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_2_3 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_3_1 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_3_2 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_3_3 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_4_1 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_4_2 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_4_3 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_5_1 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_5_2 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_5_3 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_6_1 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_6_2 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_6_3 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_7_1 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_7_2 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_7_3 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_8_1 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_8_2 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_8_3 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_cntr_en : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_grhf_rhf_ram_valid_d1_143 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_grhf_rhf_ram_valid_i_inv1_inv1 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_comp0 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_comp1 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_ram_empty_comb : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_ram_empty_fb_i_166 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_ram_empty_i_167 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_comp0 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_comp1 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_comp2 : STD_LOGIC;
signal NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_ram_afull_i : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_ram_afull_i_or0000 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_ram_full_comb : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_ram_full_fb_i_201 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_ram_full_i_202 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_Mmux_dout_mem_0_6_203 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_Mmux_dout_mem_0_7_204 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_Mmux_dout_mem_0_71_205 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_Mmux_dout_mem_0_8_206 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_dout_mem : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN_241 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_242 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1_243 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d2_244 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d1_248 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2_249 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d3_250 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_251 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1_252 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d2_253 : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_gsms_gsms_15_sms_gram_gsms_0_gv5_srl32_Q31_UNCONNECTED : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result : STD_LOGIC_VECTOR ( 8 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_cy : STD_LOGIC_VECTOR ( 7 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_lut : STD_LOGIC_VECTOR ( 8 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count : STD_LOGIC_VECTOR ( 8 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_cy : STD_LOGIC_VECTOR ( 7 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_lut : STD_LOGIC_VECTOR ( 8 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_count : STD_LOGIC_VECTOR ( 8 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_cy : STD_LOGIC_VECTOR ( 7 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_lut : STD_LOGIC_VECTOR ( 8 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_count : STD_LOGIC_VECTOR ( 8 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_cy : STD_LOGIC_VECTOR ( 7 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_lut : STD_LOGIC_VECTOR ( 8 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count : STD_LOGIC_VECTOR ( 8 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c0_carrynet : STD_LOGIC_VECTOR ( 3 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c0_v1 : STD_LOGIC_VECTOR ( 4 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c1_carrynet : STD_LOGIC_VECTOR ( 3 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c1_v1 : STD_LOGIC_VECTOR ( 4 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c0_carrynet : STD_LOGIC_VECTOR ( 3 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c0_v1 : STD_LOGIC_VECTOR ( 4 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c1_carrynet : STD_LOGIC_VECTOR ( 3 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c1_v1 : STD_LOGIC_VECTOR ( 4 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_gaf_c2_carrynet : STD_LOGIC_VECTOR ( 3 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_gaf_c2_v1 : STD_LOGIC_VECTOR ( 4 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_dout_2d : STD_LOGIC_VECTOR ( 15 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_dout_i : STD_LOGIC_VECTOR ( 0 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_shft_connect : STD_LOGIC_VECTOR ( 14 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg : STD_LOGIC_VECTOR ( 1 downto 0 );
begin
almost_full <= NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_ram_afull_i;
empty <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_ram_empty_i_167;
valid <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_grhf_rhf_ram_valid_d1_143;
full <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_ram_full_i_202;
dout(0) <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_dout_i(0);
XST_GND : GND
port map (
G => N0
);
XST_VCC : VCC
port map (
P => N1
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN : FDC
generic map(
INIT => '0'
)
port map (
C => clk,
CLR => rst,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d3_250,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN_241
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d3 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2_249,
PRE => rst,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d3_250
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d2 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1_243,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d2_244
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d2 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1_252,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d2_253
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d1_248,
PRE => rst,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2_249
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_242,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1_243
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg : FDPE
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1_252,
D => N0,
PRE => rst,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_251
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_251,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1_252
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg : FDPE
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1_243,
D => N0,
PRE => rst,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_242
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d1 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => N0,
PRE => rst,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d1_248
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_1 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => N0,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg_0 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => N0,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_gsms_sm1_gram_gsms_0_gv5_srl32 : SRLC32E
generic map(
INIT => X"00000000"
)
port map (
CLK => clk,
D => din(0),
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_dout_2d(0),
Q31 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_shft_connect(0),
A(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(4),
A(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(3),
A(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(2),
A(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(1),
A(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_gsms_gsms_1_sms_gram_gsms_0_gv5_srl32 : SRLC32E
generic map(
INIT => X"00000000"
)
port map (
CLK => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_shft_connect(0),
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_dout_2d(1),
Q31 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_shft_connect(1),
A(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(4),
A(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(3),
A(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(2),
A(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(1),
A(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_gsms_gsms_2_sms_gram_gsms_0_gv5_srl32 : SRLC32E
generic map(
INIT => X"00000000"
)
port map (
CLK => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_shft_connect(1),
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_dout_2d(2),
Q31 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_shft_connect(2),
A(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(4),
A(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(3),
A(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(2),
A(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(1),
A(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_gsms_gsms_3_sms_gram_gsms_0_gv5_srl32 : SRLC32E
generic map(
INIT => X"00000000"
)
port map (
CLK => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_shft_connect(2),
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_dout_2d(3),
Q31 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_shft_connect(3),
A(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(4),
A(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(3),
A(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(2),
A(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(1),
A(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_gsms_gsms_4_sms_gram_gsms_0_gv5_srl32 : SRLC32E
generic map(
INIT => X"00000000"
)
port map (
CLK => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_shft_connect(3),
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_dout_2d(4),
Q31 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_shft_connect(4),
A(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(4),
A(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(3),
A(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(2),
A(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(1),
A(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_gsms_gsms_5_sms_gram_gsms_0_gv5_srl32 : SRLC32E
generic map(
INIT => X"00000000"
)
port map (
CLK => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_shft_connect(4),
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_dout_2d(5),
Q31 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_shft_connect(5),
A(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(4),
A(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(3),
A(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(2),
A(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(1),
A(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_gsms_gsms_6_sms_gram_gsms_0_gv5_srl32 : SRLC32E
generic map(
INIT => X"00000000"
)
port map (
CLK => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_shft_connect(5),
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_dout_2d(6),
Q31 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_shft_connect(6),
A(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(4),
A(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(3),
A(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(2),
A(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(1),
A(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_gsms_gsms_7_sms_gram_gsms_0_gv5_srl32 : SRLC32E
generic map(
INIT => X"00000000"
)
port map (
CLK => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_shft_connect(6),
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_dout_2d(7),
Q31 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_shft_connect(7),
A(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(4),
A(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(3),
A(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(2),
A(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(1),
A(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_gsms_gsms_8_sms_gram_gsms_0_gv5_srl32 : SRLC32E
generic map(
INIT => X"00000000"
)
port map (
CLK => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_shft_connect(7),
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_dout_2d(8),
Q31 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_shft_connect(8),
A(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(4),
A(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(3),
A(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(2),
A(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(1),
A(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_gsms_gsms_9_sms_gram_gsms_0_gv5_srl32 : SRLC32E
generic map(
INIT => X"00000000"
)
port map (
CLK => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_shft_connect(8),
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_dout_2d(9),
Q31 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_shft_connect(9),
A(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(4),
A(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(3),
A(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(2),
A(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(1),
A(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_gsms_gsms_10_sms_gram_gsms_0_gv5_srl32 : SRLC32E
generic map(
INIT => X"00000000"
)
port map (
CLK => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_shft_connect(9),
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_dout_2d(10),
Q31 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_shft_connect(10),
A(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(4),
A(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(3),
A(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(2),
A(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(1),
A(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_gsms_gsms_11_sms_gram_gsms_0_gv5_srl32 : SRLC32E
generic map(
INIT => X"00000000"
)
port map (
CLK => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_shft_connect(10),
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_dout_2d(11),
Q31 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_shft_connect(11),
A(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(4),
A(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(3),
A(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(2),
A(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(1),
A(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_gsms_gsms_12_sms_gram_gsms_0_gv5_srl32 : SRLC32E
generic map(
INIT => X"00000000"
)
port map (
CLK => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_shft_connect(11),
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_dout_2d(12),
Q31 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_shft_connect(12),
A(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(4),
A(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(3),
A(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(2),
A(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(1),
A(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_gsms_gsms_13_sms_gram_gsms_0_gv5_srl32 : SRLC32E
generic map(
INIT => X"00000000"
)
port map (
CLK => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_shft_connect(12),
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_dout_2d(13),
Q31 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_shft_connect(13),
A(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(4),
A(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(3),
A(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(2),
A(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(1),
A(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_gsms_gsms_14_sms_gram_gsms_0_gv5_srl32 : SRLC32E
generic map(
INIT => X"00000000"
)
port map (
CLK => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_shft_connect(13),
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_dout_2d(14),
Q31 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_shft_connect(14),
A(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(4),
A(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(3),
A(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(2),
A(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(1),
A(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_gsms_gsms_15_sms_gram_gsms_0_gv5_srl32 : SRLC32E
generic map(
INIT => X"00000000"
)
port map (
CLK => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_shft_connect(14),
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_dout_2d(15),
Q31 => NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_gsms_gsms_15_sms_gram_gsms_0_gv5_srl32_Q31_UNCONNECTED,
A(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(4),
A(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(3),
A(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(2),
A(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(1),
A(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_Mmux_dout_mem_0_6 : LUT6
generic map(
INIT => X"F7E6B3A2D5C49180"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(6),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(5),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_dout_2d(7),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_dout_2d(4),
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_dout_2d(5),
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_dout_2d(6),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_Mmux_dout_mem_0_6_203
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_Mmux_dout_mem_0_7 : LUT6
generic map(
INIT => X"F7E6B3A2D5C49180"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(6),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(5),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_dout_2d(3),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_dout_2d(0),
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_dout_2d(1),
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_dout_2d(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_Mmux_dout_mem_0_7_204
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_Mmux_dout_mem_0_71 : LUT6
generic map(
INIT => X"F7E6B3A2D5C49180"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(6),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(5),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_dout_2d(15),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_dout_2d(12),
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_dout_2d(13),
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_dout_2d(14),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_Mmux_dout_mem_0_71_205
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_Mmux_dout_mem_0_8 : LUT6
generic map(
INIT => X"F7E6B3A2D5C49180"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(6),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(5),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_dout_2d(11),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_dout_2d(8),
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_dout_2d(9),
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_dout_2d(10),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_Mmux_dout_mem_0_8_206
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_dout_i_0 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_grhf_rhf_ram_valid_i_inv1_inv1,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg(0),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_dout_mem,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_dout_i(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_ram_afull_i : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_ram_afull_i_or0000,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2_249,
Q => NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_ram_afull_i
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_ram_full_i : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_ram_full_comb,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2_249,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_ram_full_i_202
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_ram_full_fb_i : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_ram_full_comb,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rst_d2_249,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_ram_full_fb_i_201
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_gaf_c2_gmux_gm_4_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_gaf_c2_carrynet(3),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_gaf_c2_v1(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_comp2
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_gaf_c2_gmux_gm_3_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_gaf_c2_carrynet(2),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_gaf_c2_v1(3),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_gaf_c2_carrynet(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_gaf_c2_gmux_gm_2_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_gaf_c2_carrynet(1),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_gaf_c2_v1(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_gaf_c2_carrynet(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_gaf_c2_gmux_gm_1_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_gaf_c2_carrynet(0),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_gaf_c2_v1(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_gaf_c2_carrynet(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_gaf_c2_gmux_gm_0_gm1_m1 : MUXCY
port map (
CI => N1,
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_gaf_c2_v1(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_gaf_c2_carrynet(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c1_gmux_gm_4_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c1_carrynet(3),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c1_v1(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_comp1
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c1_gmux_gm_3_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c1_carrynet(2),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c1_v1(3),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c1_carrynet(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c1_gmux_gm_2_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c1_carrynet(1),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c1_v1(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c1_carrynet(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c1_gmux_gm_1_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c1_carrynet(0),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c1_v1(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c1_carrynet(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c1_gmux_gm_0_gm1_m1 : MUXCY
port map (
CI => N1,
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c1_v1(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c1_carrynet(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c0_gmux_gm_4_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c0_carrynet(3),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c0_v1(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_comp0
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c0_gmux_gm_3_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c0_carrynet(2),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c0_v1(3),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c0_carrynet(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c0_gmux_gm_2_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c0_carrynet(1),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c0_v1(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c0_carrynet(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c0_gmux_gm_1_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c0_carrynet(0),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c0_v1(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c0_carrynet(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c0_gmux_gm_0_gm1_m1 : MUXCY
port map (
CI => N1,
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c0_v1(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c0_carrynet(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c1_gmux_gm_0_gm1_m1 : MUXCY
port map (
CI => N1,
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c1_v1(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c1_carrynet(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c1_gmux_gm_1_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c1_carrynet(0),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c1_v1(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c1_carrynet(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c1_gmux_gm_2_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c1_carrynet(1),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c1_v1(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c1_carrynet(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c1_gmux_gm_3_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c1_carrynet(2),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c1_v1(3),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c1_carrynet(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c1_gmux_gm_4_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c1_carrynet(3),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c1_v1(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_comp1
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c0_gmux_gm_0_gm1_m1 : MUXCY
port map (
CI => N1,
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c0_v1(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c0_carrynet(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c0_gmux_gm_1_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c0_carrynet(0),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c0_v1(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c0_carrynet(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c0_gmux_gm_2_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c0_carrynet(1),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c0_v1(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c0_carrynet(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c0_gmux_gm_3_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c0_carrynet(2),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c0_v1(3),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c0_carrynet(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c0_gmux_gm_4_gms_ms : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c0_carrynet(3),
DI => N0,
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c0_v1(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_comp0
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_ram_empty_fb_i : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_ram_empty_comb,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_ram_empty_fb_i_166
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_ram_empty_i : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_ram_empty_comb,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_ram_empty_i_167
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_xor_8_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_cy(7),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_lut(8),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_8_2
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_xor_7_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_cy(6),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_lut(7),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_7_2
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_cy_7_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_cy(6),
DI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count(7),
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_lut(7),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_cy(7)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_xor_6_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_cy(5),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_lut(6),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_6_2
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_cy_6_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_cy(5),
DI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count(6),
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_lut(6),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_cy(6)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_xor_5_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_cy(4),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_lut(5),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_5_2
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_cy_5_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_cy(4),
DI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count(5),
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_lut(5),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_cy(5)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_xor_4_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_cy(3),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_lut(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_4_2
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_cy_4_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_cy(3),
DI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count(4),
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_lut(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_cy(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_xor_3_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_cy(2),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_lut(3),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_3_2
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_cy_3_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_cy(2),
DI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count(3),
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_lut(3),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_cy(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_xor_2_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_cy(1),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_lut(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_2_2
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_cy_2_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_cy(1),
DI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count(2),
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_lut(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_cy(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_xor_1_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_cy(0),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_lut(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_1_2
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_cy_1_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_cy(0),
DI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count(1),
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_lut(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_cy(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_xor_0_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_grhf_rhf_ram_valid_i_inv1_inv1,
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_lut(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_0_2
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_cy_0_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_grhf_rhf_ram_valid_i_inv1_inv1,
DI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count(0),
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_lut(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_cy(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_xor_8_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_cy(7),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_lut(8),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_8_1
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_xor_7_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_cy(6),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_lut(7),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_7_1
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_cy_7_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_cy(6),
DI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_count(7),
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_lut(7),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_cy(7)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_xor_6_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_cy(5),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_lut(6),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_6_1
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_cy_6_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_cy(5),
DI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_count(6),
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_lut(6),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_cy(6)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_xor_5_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_cy(4),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_lut(5),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_5_1
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_cy_5_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_cy(4),
DI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_count(5),
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_lut(5),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_cy(5)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_xor_4_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_cy(3),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_lut(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_4_1
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_cy_4_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_cy(3),
DI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_count(4),
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_lut(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_cy(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_xor_3_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_cy(2),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_lut(3),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_3_1
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_cy_3_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_cy(2),
DI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_count(3),
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_lut(3),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_cy(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_xor_2_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_cy(1),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_lut(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_2_1
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_cy_2_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_cy(1),
DI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_count(2),
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_lut(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_cy(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_xor_1_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_cy(0),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_lut(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_1_1
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_cy_1_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_cy(0),
DI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_count(1),
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_lut(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_cy(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_xor_0_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_grhf_rhf_ram_valid_i_inv1_inv1,
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_lut(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_0_1
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_cy_0_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_grhf_rhf_ram_valid_i_inv1_inv1,
DI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_count(0),
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_lut(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_cy(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_xor_8_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_cy(7),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_lut(8),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_8_3
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_xor_7_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_cy(6),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_lut(7),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_7_3
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_cy_7_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_cy(6),
DI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_count(7),
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_lut(7),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_cy(7)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_xor_6_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_cy(5),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_lut(6),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_6_3
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_cy_6_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_cy(5),
DI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_count(6),
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_lut(6),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_cy(6)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_xor_5_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_cy(4),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_lut(5),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_5_3
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_cy_5_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_cy(4),
DI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_count(5),
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_lut(5),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_cy(5)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_xor_4_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_cy(3),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_lut(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_4_3
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_cy_4_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_cy(3),
DI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_count(4),
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_lut(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_cy(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_xor_3_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_cy(2),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_lut(3),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_3_3
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_cy_3_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_cy(2),
DI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_count(3),
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_lut(3),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_cy(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_xor_2_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_cy(1),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_lut(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_2_3
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_cy_2_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_cy(1),
DI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_count(2),
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_lut(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_cy(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_xor_1_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_cy(0),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_lut(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_1_3
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_cy_1_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_cy(0),
DI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_count(1),
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_lut(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_cy(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_xor_0_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_grhf_rhf_ram_valid_i_inv1_inv1,
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_lut(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_0_3
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_cy_0_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_grhf_rhf_ram_valid_i_inv1_inv1,
DI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_count(0),
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_lut(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_cy(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_xor_8_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_cy(7),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_lut(8),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result(8)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_xor_7_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_cy(6),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_lut(7),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result(7)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_cy_7_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_cy(6),
DI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(7),
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_lut(7),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_cy(7)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_xor_6_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_cy(5),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_lut(6),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result(6)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_cy_6_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_cy(5),
DI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(6),
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_lut(6),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_cy(6)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_xor_5_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_cy(4),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_lut(5),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result(5)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_cy_5_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_cy(4),
DI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(5),
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_lut(5),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_cy(5)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_xor_4_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_cy(3),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_lut(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_cy_4_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_cy(3),
DI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(4),
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_lut(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_cy(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_xor_3_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_cy(2),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_lut(3),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_cy_3_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_cy(2),
DI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(3),
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_lut(3),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_cy(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_xor_2_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_cy(1),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_lut(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_cy_2_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_cy(1),
DI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(2),
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_lut(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_cy(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_xor_1_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_cy(0),
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_lut(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_cy_1_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_cy(0),
DI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(1),
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_lut(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_cy(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_xor_0_Q : XORCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_grhf_rhf_ram_valid_i_inv1_inv1,
LI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_lut(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_cy_0_Q : MUXCY
port map (
CI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_grhf_rhf_ram_valid_i_inv1_inv1,
DI => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(0),
S => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_lut(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_cy(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_count_8 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_cntr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_8_3,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_count(8)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_count_8 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_cntr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_8_1,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_count(8)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count_8 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_cntr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_8_2,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count(8)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count_7 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_cntr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_7_2,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count(7)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count_6 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_cntr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_6_2,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count(6)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count_5 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_cntr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_5_2,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count(5)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count_4 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_cntr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_4_2,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count_3 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_cntr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_3_2,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count_2 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_cntr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_2_2,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count_1 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_cntr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_1_2,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count_0 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_cntr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_0_2,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_count_7 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_cntr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_7_3,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_count(7)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_count_6 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_cntr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_6_3,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_count(6)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_count_4 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_cntr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_4_3,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_count(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_count_3 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_cntr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_3_3,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_count(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_count_5 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_cntr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_5_3,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_count(5)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_count_1 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_cntr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_1_3,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_count(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_count_0 : FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_cntr_en,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_0_3,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_count(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_count_2 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_cntr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_2_3,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_count(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_count_6 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_cntr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_6_1,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_count(6)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_count_5 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_cntr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_5_1,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_count(5)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_count_7 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_cntr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_7_1,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_count(7)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_count_3 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_cntr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_3_1,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_count(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_count_2 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_cntr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_2_1,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_count(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_count_4 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_cntr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_4_1,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_count(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_count_0 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_cntr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_0_1,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_count(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_count_1 : FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_cntr_en,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result_1_1,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_count(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count_8 : FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_cntr_en,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result(8),
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(8)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count_7 : FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_cntr_en,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result(7),
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(7)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count_6 : FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_cntr_en,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result(6),
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(6)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count_5 : FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_cntr_en,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result(5),
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(5)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count_4 : FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_cntr_en,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result(4),
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count_3 : FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_cntr_en,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result(3),
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count_2 : FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_cntr_en,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result(2),
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count_1 : FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_cntr_en,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result(1),
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count_0 : FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_cntr_en,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Result(0),
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_grhf_rhf_ram_valid_d1 : FDC
generic map(
INIT => '0'
)
port map (
C => clk,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_grhf_rhf_ram_valid_i_inv1_inv1,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_grhf_rhf_ram_valid_d1_143
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb1 : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_242,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d2_244,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_ram_wr_en_i1 : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_en,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_ram_full_fb_i_201,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_gaf_c2_v1_3_and00001 : LUT2
generic map(
INIT => X"1"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_count(7),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_count(6),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_gaf_c2_v1(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c1_v1_3_and00001 : LUT2
generic map(
INIT => X"1"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_count(7),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_count(6),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c1_v1(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c0_v1_3_and00001 : LUT2
generic map(
INIT => X"1"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count(7),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count(6),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c0_v1(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c1_v1_3_and00001 : LUT2
generic map(
INIT => X"1"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count(7),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count(6),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c1_v1(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c0_v1_3_and00001 : LUT2
generic map(
INIT => X"1"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count(7),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count(6),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c0_v1(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_gaf_c2_v1_2_and00001 : LUT2
generic map(
INIT => X"1"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_count(5),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_count(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_gaf_c2_v1(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c1_v1_2_and00001 : LUT2
generic map(
INIT => X"1"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_count(5),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_count(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c1_v1(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c0_v1_2_and00001 : LUT2
generic map(
INIT => X"1"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count(5),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c0_v1(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c1_v1_2_and00001 : LUT2
generic map(
INIT => X"1"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count(5),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c1_v1(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c0_v1_2_and00001 : LUT2
generic map(
INIT => X"1"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count(5),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count(4),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c0_v1(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_gaf_c2_v1_1_and00001 : LUT2
generic map(
INIT => X"1"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_count(3),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_count(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_gaf_c2_v1(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c1_v1_1_and00001 : LUT2
generic map(
INIT => X"1"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_count(3),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_count(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c1_v1(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c0_v1_1_and00001 : LUT2
generic map(
INIT => X"1"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count(3),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c0_v1(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c1_v1_1_and00001 : LUT2
generic map(
INIT => X"1"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count(3),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c1_v1(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c0_v1_1_and00001 : LUT2
generic map(
INIT => X"1"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count(3),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c0_v1(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_gaf_c2_v1_0_and00001 : LUT2
generic map(
INIT => X"1"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_count(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_count(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_gaf_c2_v1(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c1_v1_0_and00001 : LUT2
generic map(
INIT => X"1"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_count(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_count(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c1_v1(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c0_v1_0_and00001 : LUT2
generic map(
INIT => X"1"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c0_v1(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c1_v1_0_and00001 : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count(0),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c1_v1(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c0_v1_0_and00001 : LUT2
generic map(
INIT => X"1"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c0_v1(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_ram_afull_i_or00001 : LUT6
generic map(
INIT => X"080CAEAE080C0C0C"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
I1 => NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_ram_afull_i,
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN_241,
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_comp1,
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_grhf_rhf_ram_valid_i_inv1_inv1,
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_comp2,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_ram_afull_i_or0000
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_grhf_rhf_ram_valid_i1 : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_en,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_ram_empty_fb_i_166,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_grhf_rhf_ram_valid_i_inv1_inv1
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_RD_PNTR_8_1 : LUT6
generic map(
INIT => X"F7E6B3A2D5C49180"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(8),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(7),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_Mmux_dout_mem_0_71_205,
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_Mmux_dout_mem_0_7_204,
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_Mmux_dout_mem_0_6_203,
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_Mmux_dout_mem_0_8_206,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gsm_sm_dout_mem
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_lut_0_Q : LUT3
generic map(
INIT => X"59"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count(0),
I1 => rd_en,
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_ram_empty_fb_i_166,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_lut(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_lut_0_Q : LUT3
generic map(
INIT => X"59"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_count(0),
I1 => rd_en,
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_ram_empty_fb_i_166,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_lut(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_lut_0_Q : LUT3
generic map(
INIT => X"59"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_count(0),
I1 => rd_en,
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_ram_empty_fb_i_166,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_lut(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_lut_0_Q : LUT3
generic map(
INIT => X"59"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(0),
I1 => rd_en,
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_ram_empty_fb_i_166,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_lut(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_lut_1_Q : LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_ram_empty_fb_i_166,
I2 => rd_en,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_lut(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_lut_1_Q : LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_count(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_ram_empty_fb_i_166,
I2 => rd_en,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_lut(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_lut_1_Q : LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_count(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_ram_empty_fb_i_166,
I2 => rd_en,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_lut(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_lut_1_Q : LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_ram_empty_fb_i_166,
I2 => rd_en,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_lut(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_lut_2_Q : LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count(2),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_ram_empty_fb_i_166,
I2 => rd_en,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_lut(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_lut_2_Q : LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_count(2),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_ram_empty_fb_i_166,
I2 => rd_en,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_lut(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_lut_2_Q : LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_count(2),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_ram_empty_fb_i_166,
I2 => rd_en,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_lut(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_lut_2_Q : LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(2),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_ram_empty_fb_i_166,
I2 => rd_en,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_lut(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_lut_3_Q : LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count(3),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_ram_empty_fb_i_166,
I2 => rd_en,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_lut(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_lut_3_Q : LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_count(3),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_ram_empty_fb_i_166,
I2 => rd_en,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_lut(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_lut_3_Q : LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_count(3),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_ram_empty_fb_i_166,
I2 => rd_en,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_lut(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_lut_3_Q : LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(3),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_ram_empty_fb_i_166,
I2 => rd_en,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_lut(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_lut_4_Q : LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count(4),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_ram_empty_fb_i_166,
I2 => rd_en,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_lut(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_lut_4_Q : LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_count(4),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_ram_empty_fb_i_166,
I2 => rd_en,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_lut(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_lut_4_Q : LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_count(4),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_ram_empty_fb_i_166,
I2 => rd_en,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_lut(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_lut_4_Q : LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(4),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_ram_empty_fb_i_166,
I2 => rd_en,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_lut(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_lut_5_Q : LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count(5),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_ram_empty_fb_i_166,
I2 => rd_en,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_lut(5)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_lut_5_Q : LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_count(5),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_ram_empty_fb_i_166,
I2 => rd_en,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_lut(5)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_lut_5_Q : LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_count(5),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_ram_empty_fb_i_166,
I2 => rd_en,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_lut(5)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_lut_5_Q : LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(5),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_ram_empty_fb_i_166,
I2 => rd_en,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_lut(5)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_lut_6_Q : LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count(6),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_ram_empty_fb_i_166,
I2 => rd_en,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_lut(6)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_lut_6_Q : LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_count(6),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_ram_empty_fb_i_166,
I2 => rd_en,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_lut(6)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_lut_6_Q : LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_count(6),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_ram_empty_fb_i_166,
I2 => rd_en,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_lut(6)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_lut_6_Q : LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(6),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_ram_empty_fb_i_166,
I2 => rd_en,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_lut(6)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_lut_7_Q : LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count(7),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_ram_empty_fb_i_166,
I2 => rd_en,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_lut(7)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_lut_7_Q : LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_count(7),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_ram_empty_fb_i_166,
I2 => rd_en,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_lut(7)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_lut_7_Q : LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_count(7),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_ram_empty_fb_i_166,
I2 => rd_en,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_lut(7)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_lut_7_Q : LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(7),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_ram_empty_fb_i_166,
I2 => rd_en,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_lut(7)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_ram_full_comb1 : LUT6
generic map(
INIT => X"0702020227222222"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_ram_full_fb_i_201,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN_241,
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_grhf_rhf_ram_valid_i_inv1_inv1,
I3 => wr_en,
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_comp1,
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_comp0,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_ram_full_comb
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_ram_empty_comb1 : LUT6
generic map(
INIT => X"AEFF8CCC8CCC8CCC"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_ram_full_fb_i_201,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_ram_empty_fb_i_166,
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_comp0,
I3 => wr_en,
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_comp1,
I5 => rd_en,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_ram_empty_comb
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_lut_8_Q : LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count(8),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_ram_empty_fb_i_166,
I2 => rd_en,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_Mcount_count_lut(8)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_lut_8_Q : LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_count(8),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_ram_empty_fb_i_166,
I2 => rd_en,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_Mcount_count_lut(8)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_lut_8_Q : LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_count(8),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_ram_empty_fb_i_166,
I2 => rd_en,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_Mcount_count_lut(8)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_lut_8_Q : LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_count(8),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_ram_empty_fb_i_166,
I2 => rd_en,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_crd_Mcount_count_lut(8)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_Mxor_cntr_en_Result1 : LUT4
generic map(
INIT => X"6530"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_ram_empty_fb_i_166,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_ram_full_fb_i_201,
I2 => wr_en,
I3 => rd_en,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_cntr_en
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_gaf_c2_v1_4_not00001_INV_0 : INV
port map (
I => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c2_count(8),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_gaf_c2_v1(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c1_v1_4_not00001_INV_0 : INV
port map (
I => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c1_count(8),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c1_v1(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c0_v1_4_not00001_INV_0 : INV
port map (
I => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count(8),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_wsts_c0_v1(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c1_v1_4_not00001_INV_0 : INV
port map (
I => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count(8),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c1_v1(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c0_v1_4_not00001_INV_0 : INV
port map (
I => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_c0_count(8),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl1_lsshft_rsts_c0_v1(4)
);
end STRUCTURE;
-- synthesis translate_on
|
apache-2.0
|
willtmwu/vhdlExamples
|
BCD Adder/Advanced/harware_interface.vhd
|
1
|
6620
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity hardware_interface is
Port ( ssegAnode : out STD_LOGIC_VECTOR (7 downto 0);
ssegCathode : out STD_LOGIC_VECTOR (7 downto 0);
slideSwitches : in STD_LOGIC_VECTOR (15 downto 0);
pushButtons : in STD_LOGIC_VECTOR (4 downto 0);
LEDs : out STD_LOGIC_VECTOR (15 downto 0);
clk100mhz : in STD_LOGIC;
logic_analyzer : out STD_LOGIC_VECTOR (7 downto 0);
aclMISO : IN std_logic;
aclMOSI : OUT std_logic;
aclSCLK : OUT std_logic;
aclCS : OUT std_logic;
RGB1_Red : OUT std_logic;
RGB1_Green : OUT std_logic;
RGB1_Blue : OUT std_logic
);
end hardware_interface;
architecture Behavioral of hardware_interface is
component ssegDriver port (
clk : in std_logic;
rst : in std_logic;
cathode_p : out std_logic_vector(7 downto 0);
anode_p : out std_logic_vector(7 downto 0);
digit1_p : in std_logic_vector(3 downto 0);
digit2_p : in std_logic_vector(3 downto 0);
digit3_p : in std_logic_vector(3 downto 0);
digit4_p : in std_logic_vector(3 downto 0);
digit5_p : in std_logic_vector(3 downto 0);
digit6_p : in std_logic_vector(3 downto 0);
digit7_p : in std_logic_vector(3 downto 0);
digit8_p : in std_logic_vector(3 downto 0)
);
end component;
component spi_accel port (
clk100MHz : in STD_LOGIC;
masterReset : in STD_LOGIC;
CS : out STD_LOGIC;
SCLK : out STD_LOGIC;
MOSI : out STD_LOGIC;
MISO : in STD_LOGIC;
READY : out STD_LOGIC;
X_VAL : out STD_LOGIC_VECTOR(7 downto 0);
Y_VAL : out STD_LOGIC_VECTOR(7 downto 0);
Z_VAL : out STD_LOGIC_VECTOR(7 downto 0)
);
end component;
component led_bright port(
clk : IN std_logic;
masterReset : IN std_logic;
ready : IN std_logic;
accel_val : IN std_logic_vector(7 downto 0);
pwm_out : OUT std_logic
);
end component;
component bcd_display port (
clk : in std_logic;
masterReset : in std_logic;
byte_in : in STD_LOGIC_VECTOR(7 downto 0);
bcd_val : out STD_LOGIC_VECTOR(11 downto 0)
);
end component;
--Central Button
signal masterReset : std_logic;
signal buttonLeft : std_logic;
signal buttonRight : std_logic;
signal buttonUp : std_logic;
signal buttonDown : std_logic;
signal displayLower : std_logic_vector(15 downto 0);
signal displayUpper : std_logic_vector(15 downto 0);
signal clockScalers : std_logic_vector (26 downto 0);
-- Component Signals
signal CS : std_logic := '1';
signal SCLK : std_logic := '0';
signal MOSI : std_logic := '0';
signal MISO : std_logic := '0';
signal READY : std_logic := '0';
signal X_VAL : std_logic_vector(7 downto 0) := (others => '0');
signal Y_VAL : std_logic_vector(7 downto 0) := (others => '0');
signal Z_VAL : std_logic_vector(7 downto 0) := (others => '0');
signal X_VAL_D : std_logic_vector(11 downto 0) := (others => '0');
signal Y_VAL_D : std_logic_vector(11 downto 0) := (others => '0');
signal Z_VAL_D : std_logic_vector(11 downto 0) := (others => '0');
signal X_PWM : std_logic := '0';
signal Y_PWM : std_logic := '0';
signal Z_PWM : std_logic := '0';
begin
--Central Button
masterReset <= pushButtons(4);
buttonLeft <= pushButtons(3);
buttonRight <= pushButtons(0);
buttonUp <= pushButtons(2);
buttonDown <= pushButtons(1);
LEDs (15 downto 8) <= clockScalers(26 downto 19);
--logic_analyzer (7 downto 0) <= clockScalers(26 downto 19);
process (clk100mhz, masterReset) begin
if (masterReset = '1') then
clockScalers <= "000000000000000000000000000";
elsif (clk100mhz'event and clk100mhz = '1')then
clockScalers <= clockScalers + '1';
end if;
end process;
u1 : ssegDriver port map (
clk => clockScalers(11),
rst => masterReset,
cathode_p => ssegCathode,
anode_p => ssegAnode,
digit1_p => displayLower (3 downto 0),
digit2_p => displayLower (7 downto 4),
digit3_p => displayLower (11 downto 8),
digit4_p => displayLower (15 downto 12),
digit5_p => displayUpper (3 downto 0),
digit6_p => displayUpper (7 downto 4),
digit7_p => displayUpper (11 downto 8),
digit8_p => displayUpper (15 downto 12)
);
m1 : spi_accel port map (clk100Mhz, masterReset, CS, SCLK, MOSI, MISO, READY, X_VAL, Y_VAL, Z_VAL);
logic_analyzer(0) <= clk100Mhz;
logic_analyzer(1) <= masterReset;
logic_analyzer(2) <= CS;
logic_analyzer(3) <= SCLK;
logic_analyzer(4) <= MOSI;
logic_analyzer(5) <= MISO;
logic_analyzer(6) <= READY;
--logic_analyzer(7) <= '0';
--Accel Linking
aclCS <= CS;
aclSCLK <= SCLk;
aclMOSI <= MOSI;
MISO <= aclMISO;
-- displayLower(15 downto 8) <= X_VAL;
-- displayLower(7 downto 0) <= Y_VAL;
-- displayUpper(7 downto 0) <= Z_VAL;
D1 : bcd_display port map (Ready, masterReset, X_VAL, X_VAL_D);
D2 : bcd_display port map (Ready, masterReset, Y_VAL, Y_VAL_D);
D3 : bcd_display port map (Ready, masterReset, Z_VAL, Z_VAL_D);
--PWM Linking
P1 : led_bright port map(clk100Mhz, masterReset, ready, X_VAL, X_PWM);
P2 : led_bright port map(clk100Mhz, masterReset, ready, Y_VAL, Y_PWM);
P3 : led_bright port map(clk100Mhz, masterReset, ready, Z_VAL, Z_PWM);
--LEDBAR and PWM Linking
process ( slideSwitches(15 downto 13) ) begin
if ( (slideSwitches(15) = '0') and (slideSwitches(14) = '0') and (slideSwitches(13) = '1')) then
LEDs(7 downto 0) <= Y_VAL;
displayLower(11 downto 0) <= Y_VAL_D;
logic_analyzer(7) <= Y_PWM;
RGB1_Red <= '0';
RGB1_Green <= Y_PWM;
RGB1_Blue <= '0';
elsif ( (slideSwitches(15) = '0') and (slideSwitches(14) = '1') and (slideSwitches(13) = '0')) then
LEDs(7 downto 0) <= X_VAL;
displayLower(11 downto 0) <= X_VAL_D;
logic_analyzer(7) <= X_PWM;
RGB1_Red <= X_PWM;
RGB1_Green <= '0';
RGB1_Blue <= '0';
elsif ( (slideSwitches(15) = '1') and (slideSwitches(14) = '0') and (slideSwitches(13) = '0')) then
LEDs(7 downto 0) <= Z_VAL;
displayLower(11 downto 0) <= Z_VAL_D;
logic_analyzer(7) <= Z_PWM;
RGB1_Red <= '0';
RGB1_Green <= '0';
RGB1_Blue <= Z_PWM;
elsif ( (slideSwitches(15) = '1') and (slideSwitches(14) = '1') and (slideSwitches(13) = '1')) then
LEDs(7 downto 0) <= "10101010";
RGB1_Red <= X_PWM;
RGB1_Green <= Y_PWM;
RGB1_Blue <= Z_PWM;
else
LEDs(7 downto 0) <= (others => '0');
RGB1_Red <= '0';
RGB1_Green <= '0';
RGB1_Blue <= '0';
end if;
end process;
end Behavioral;
|
apache-2.0
|
google/myelin-acorn-electron-hardware
|
minus_one/cpld/minus_one.vhd
|
1
|
3415
|
-- Copyright 2017 Google Inc.
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity minus_one is
Port (
-- can't use a std_logic_vector here because we're missing A7-4 :(
A15 : in std_logic;
A14 : in std_logic;
A13 : in std_logic;
A12 : in std_logic;
A11 : in std_logic;
A10 : in std_logic;
A9 : in std_logic;
A8 : in std_logic;
A3 : in std_logic;
A2 : in std_logic;
A1 : in std_logic;
A0 : in std_logic;
D : in std_logic_vector(7 downto 0);
nRST : in std_logic;
PHI0 : in std_logic;
RnW : in std_logic;
cart0_nOE : out std_logic;
cart2_nOE : out std_logic;
cart4_nOE : out std_logic;
cart_nOE2 : out std_logic;
cart_ROMQA : out std_logic;
cart_nINFC : out std_logic;
cart_nINFD : out std_logic;
cart_nROMSTB : out std_logic;
GPIO1 : in std_logic;
GPIO2 : in std_logic;
GPIO3 : in std_logic
);
end minus_one;
architecture Behavioural of minus_one is
-- '1' when A = &8000-BFFF, i.e. sideways address space
signal sideways_select : std_logic;
-- high byte on the address bus
signal A_high : std_logic_vector(7 downto 0);
-- low nybble on the address bus
signal A_low : std_logic_vector(3 downto 0);
-- register: currently selected bank
signal bank : std_logic_vector(3 downto 0) := "1101";
begin
A_high <= A15 & A14 & A13 & A12 & A11 & A10 & A9 & A8;
A_low <= A3 & A2 & A1 & A0;
-- '1' when A = &8000-BFFF
sideways_select <= '1' when (A15 & A14 = "10") else '0';
-- nOE for all cartridges
cart0_nOE <= '0' when sideways_select = '1' and (bank(3 downto 1) = "000") else '1';
cart2_nOE <= '0' when sideways_select = '1' and (bank(3 downto 1) = "001") else '1';
cart4_nOE <= '0' when sideways_select = '1' and (bank(3 downto 1) = "010") else '1';
-- bank select within cartridge address space
cart_ROMQA <= bank(0);
-- nOE2 (shared by all cartridges)
cart_nOE2 <= '0' when sideways_select = '1' and bank = "1101" else '1';
-- '0' when A = FCxx
cart_nINFC <= '0' when (A_high = x"FC") else '1';
-- '0' when A = FDxx
cart_nINFD <= '0' when (A_high = x"FD") else '1';
-- nROMSTB is not implemented
cart_nROMSTB <= '1';
process (PHI0)
begin
if nRST = '0' then
-- default to something that'll deactivate all cartridges
bank <= "1010";
elsif falling_edge(PHI0) then
-- ROM bank is selected by writing "0000xxxx" to &FEx5
if RnW = '0' and A_high = x"FE" and A_low = x"5" and D(7 downto 4) = "0000" then
bank <= D(3 downto 0);
end if;
end if;
end process;
end Behavioural;
|
apache-2.0
|
michel-castan/LILASHOME
|
doc/index_166.vhd
|
1
|
913
|
--------------------------------------------
-- généré par LILASV4 --
--------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.Numeric_Std.all;
use IEEE.std_logic_unsigned.all;
entity tst_code_logic_LocalInternal is
port(
a : IN std_logic := '0';
b : IN std_logic := '0';
cin : IN std_logic := '0';
cout : OUT std_logic := '0';
s : OUT std_logic := '0');
end entity tst_code_logic_LocalInternal;
architecture a_tst_code_logic_LocalInternal of tst_code_logic_LocalInternal is
-- déclaration des variables modules
-- déclaration des signaux internes
signal p : std_logic := 'U';
-- déclaration des variables locales
begin
process (a, b, p, cin)
variable g : std_logic;
begin
g := (a and b);
p <= (a or b);
cout <= (g or (p and cin));
s <= (a xor b xor cin);
end process;
end architecture a_tst_code_logic_LocalInternal;
|
apache-2.0
|
Raane/Term-Assigment-TFE4140-mod-anal-dig-sys
|
Project/liaison/src/controller.vhd
|
1
|
5216
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity controller is
port(
di_ready : in STD_LOGIC;
clk : in STD_LOGIC;
reset : in STD_LOGIC;
do_ready : out STD_LOGIC;
control_signals : out STD_LOGIC_VECTOR(9 downto 0);
voted_data_selector : out STD_LOGIC_VECTOR(3 downto 0)
);
end controller;
architecture controller of controller is
-- Next-signals used for clock updates
signal next_control_signals: std_logic_vector(9 downto 0);
signal next_vdsi: std_logic_vector(3 downto 0);
signal next_do_ready: std_logic;
signal do_ready_internal: std_logic; -- For internal use of do_ready
signal control_signals_internal : STD_LOGIC_VECTOR(9 downto 0); -- For internal use of control_signals
signal vdsi : STD_LOGIC_VECTOR(3 downto 0); -- For internal use of voted_data_selector (shortened to vdsi, i for internal)
begin
-- Setting component output from internal output signals
do_ready <= do_ready_internal;
control_signals <= control_signals_internal;
voted_data_selector <= vdsi;
-- Setting current output
clock_tick : process(clk)
begin
if (rising_edge(clk)) then
if (reset = '1') then
control_signals_internal <= "0000000000";
vdsi <= "0111"; -- 0111 is the first output, from V7
do_ready_internal <= '0';
else
-- Updating the controller's output values
-- based on current selected next-values
control_signals_internal <= next_control_signals;
vdsi <= next_vdsi;
do_ready_internal <= next_do_ready;
end if;
end if;
end process;
-- Selects register for storing input among voted data, status data and ECC data,
-- and also activates do_ready after 8 cycles
handle_input : process(di_ready, control_signals_internal)
variable nd_variable : std_logic; -- Used to set next_do_ready
begin
nd_variable := '0';
case control_signals_internal is
when "0000000000" =>
if (di_ready = '1') then -- di_ready works only when system is idle, with value "0000000000"
next_control_signals <= "0010000000"; -- store as bit 7
else
next_control_signals <= "0000000000"; -- Stay idle, di_ready has not yet hit in
end if;
when "0010000000" =>
next_control_signals <= "0001000000"; -- store as bit 6
when "0001000000" =>
next_control_signals <= "0000100000"; -- store as bit 5
when "0000100000" =>
next_control_signals <= "0000010000"; -- store as bit 4
when "0000010000" =>
next_control_signals <= "0000001000"; -- store as bit 3
when "0000001000" =>
next_control_signals <= "0000000100"; -- store as bit 2
when "0000000100" =>
next_control_signals <= "0000000010"; -- store as bit 1
when "0000000010" =>
nd_variable := '1'; -- Setting do_ready 8 cycles after di_ready has initiated storing. Otherwise, keep do_ready at 0
next_control_signals <= "0000000001"; -- store as bit 0
when "0000000001" =>
next_control_signals <= "0100000000"; -- store status
when "0100000000" =>
next_control_signals <= "1000000000"; -- update ECC-registers
when others => -- Done running through register storing. Do nothing until di_ready has been set again.
next_control_signals <= "0000000000";
end case;
next_do_ready <= nd_variable;
end process;
-- Selects output from the different registers, one at a time
-- default when idle is register v7
handle_output : process (vdsi, do_ready_internal)
begin
case vdsi is
when "0111" =>
if (do_ready_internal = '1') then
next_vdsi <= "0110"; -- set output from liaison to voted data bit 6
else
next_vdsi <= "0111"; -- Idle, do_ready is not 1, keep output on voted data bit 7
end if;
when "0110" =>
next_vdsi <= "0101"; -- set output from liaison to voted data bit 5
when "0101" =>
next_vdsi <= "0100"; -- set output from liaison to voted data bit 4
when "0100" =>
next_vdsi <= "0011"; -- set output from liaison to voted data bit 3
when "0011" =>
next_vdsi <= "0010"; -- set output from liaison to voted data bit 2
when "0010" =>
next_vdsi <= "0001"; -- set output from liaison to voted data bit 1
when "0001" =>
next_vdsi <= "0000"; -- set output from liaison to voted data bit 0
when "0000" =>
next_vdsi <= "1010"; -- set output from liaison to status bit 2
when "1010" =>
next_vdsi <= "1001"; -- set output from liaison to status bit 1
when "1001" =>
next_vdsi <= "1000"; -- set output from liaison to status bit 0
when "1000" =>
next_vdsi <= "1110"; -- set output from liaison to ECC bit 3
when "1110" =>
next_vdsi <= "1101"; -- set output from liaison to ECC bit 2
when "1101" =>
next_vdsi <= "1100"; -- set output from liaison to ECC bit 1
when "1100" =>
next_vdsi <= "1011"; -- set output from liaison to ECC bit 0
when others =>
next_vdsi <= "0111";
-- Reached when vdsi = "01111". Cycle is at end, setting output at voted data bit 7.
-- Using "When others" in case of glitch as well, though other values should never be reached.
-- Ideally, do_ready should have been set to 1 at the same time for max throughput
end case;
end process;
end controller;
|
apache-2.0
|
dpolad/dlx
|
DLX_vhd/a-DLX.vhd
|
1
|
15892
|
library IEEE;
use IEEE.std_logic_1164.all;
use work.myTypes.all;
entity top_level is
port(
clock : in std_logic;
rst : in std_logic;
IRAM_Addr_o : out std_logic_vector(31 downto 0);
IRAM_Dout_i : in std_logic_vector(31 downto 0);
DRAM_Enable_o : out std_logic;
DRAM_WR_o : out std_logic;
DRAM_Din_o : out std_logic_vector(31 downto 0);
DRAM_Addr_o : out std_logic_vector(31 downto 0);
DRAM_Dout_i : in std_logic_vector(31 downto 0)
);
end top_level;
architecture arch of top_level is
component fetch_block
port (
branch_target_i : in std_logic_vector(31 downto 0);
sum_addr_i : in std_logic_vector(31 downto 0);
A_i : in std_logic_vector(31 downto 0);
NPC4_i : in std_logic_vector(31 downto 0);
S_MUX_PC_BUS_i : in std_logic_vector(1 downto 0);
PC_o : out std_logic_vector(31 downto 0);
PC4_o : out std_logic_vector(31 downto 0);
PC_BUS_pre_BTB : out std_logic_vector(31 downto 0);
stall_i : in std_logic;
mispredict_i : in std_logic;
take_prediction_i : in std_logic;
predicted_PC : in std_logic_vector(31 downto 0);
clk : in std_logic;
rst : in std_logic
);
end component;
component fetch_regs is
port (
NPCF_i : in std_logic_vector(31 downto 0);
IR_i : in std_logic_vector(31 downto 0);
NPCF_o : out std_logic_vector(31 downto 0);
IR_o : out std_logic_vector(31 downto 0);
stall_i : in std_logic;
clk : in std_logic;
rst : in std_logic
);
end component;
component jump_logic is
port (
NPCF_i : in std_logic_vector(31 downto 0);
IR_i : in std_logic_vector(31 downto 0);
A_i : in std_logic_vector(31 downto 0);
A_o : out std_logic_vector(31 downto 0);
rA_o : out std_logic_vector(4 downto 0);
rB_o : out std_logic_vector(4 downto 0);
rC_o : out std_logic_vector(4 downto 0);
branch_target_o : out std_logic_vector(31 downto 0);
sum_addr_o : out std_logic_vector(31 downto 0);
extended_imm : out std_logic_vector(31 downto 0);
taken_o : out std_logic; --was the branch taken or not?
FW_X_i : in std_logic_vector(31 downto 0);
FW_W_i : in std_logic_vector(31 downto 0);
S_FW_Adec_i : in std_logic_vector(1 downto 0);
S_EXT_i : in std_logic;
S_EXT_SIGN_i : in std_logic;
S_MUX_LINK_i : in std_logic;
S_EQ_NEQ_i : in std_logic
);
end component;
component dlx_regfile is
port ( Clk: in std_logic;
Rst: in std_logic;
ENABLE: in std_logic;
RD1: in std_logic;
RD2: in std_logic;
WR: in std_logic;
ADD_WR: in std_logic_vector(4 downto 0);
ADD_RD1: in std_logic_vector(4 downto 0);
ADD_RD2: in std_logic_vector(4 downto 0);
DATAIN: in std_logic_vector(31 downto 0);
OUT1: out std_logic_vector(31 downto 0);
OUT2: out std_logic_vector(31 downto 0));
end component;
component dlx_cu is
generic (
MICROCODE_MEM_SIZE : integer := 64; -- Microcode Memory Size
FUNC_SIZE : integer := 11; -- Func Field Size for R-Type Ops
OP_CODE_SIZE : integer := 6; -- Op Code Size
IR_SIZE : integer := 32; -- Instruction Register Size
CW_SIZE : integer := 13); -- Control Word Size
port (
Clk : in std_logic; -- clock
Rst : in std_logic; -- rst:Active-Low
IR_IN : in std_logic_vector(31 downto 0);
stall_exe_i : in std_logic;
mispredict_i : in std_logic;
D1_i : in std_logic_vector(4 downto 0);
D2_i : in std_logic_vector(4 downto 0);
S1_LATCH_EN : out std_logic;
S2_LATCH_EN : out std_logic;
S3_LATCH_EN : out std_logic;
S_MUX_PC_BUS : out std_logic_vector(1 downto 0);
S_EXT : out std_logic;
S_EXT_SIGN : out std_logic;
S_EQ_NEQ : out std_logic;
S_MUX_LINK : out std_logic;
S_MUX_DEST : out std_logic_vector(1 downto 0);
S_MUX_MEM : out std_logic;
S_MEM_EN : out std_logic;
S_MEM_W_R : out std_logic;
S_RF_W_wb : out std_logic;
S_RF_W_mem : out std_logic;
S_RF_W_exe : out std_logic;
S_MUX_ALUIN : out std_logic;
stall_exe_o : out std_logic;
stall_dec_o : out std_logic;
stall_fetch_o : out std_logic;
stall_btb_o : out std_logic;
was_branch_o : out std_logic;
was_jmp_o : out std_logic;
ALU_WORD_o : out std_logic_vector(12 downto 0); -- Opcode to ALU
ALU_OPCODE : out aluOp
);
end component;
component decode_regs is
port (
A_i : in std_logic_vector(31 downto 0);
B_i : in std_logic_vector(31 downto 0);
rA_i : in std_logic_vector(4 downto 0);
rB_i : in std_logic_vector(4 downto 0);
rC_i : in std_logic_vector(4 downto 0);
IMM_i : in std_logic_vector(31 downto 0);
ALUW_i : in std_logic_vector(12 downto 0);
A_o : out std_logic_vector(31 downto 0);
B_o : out std_logic_vector(31 downto 0);
rA_o : out std_logic_vector(4 downto 0);
rB_o : out std_logic_vector(4 downto 0);
rC_o : out std_logic_vector(4 downto 0);
IMM_o : out std_logic_vector(31 downto 0);
ALUW_o : out std_logic_vector(12 downto 0);
stall_i : in std_logic;
clk : in std_logic;
rst : in std_logic
);
end component;
component execute_regs
port (
X_i : in std_logic_vector(31 downto 0);
S_i : in std_logic_vector(31 downto 0);
D2_i : in std_logic_vector(4 downto 0);
X_o : out std_logic_vector(31 downto 0);
S_o : out std_logic_vector(31 downto 0);
D2_o : out std_logic_vector(4 downto 0);
stall_i : in std_logic;
clk : in std_logic;
rst : in std_logic
);
end component;
component execute_block
port (
IMM_i : in std_logic_vector(31 downto 0);
A_i : in std_logic_vector(31 downto 0);
rB_i : in std_logic_vector(4 downto 0);
rC_i : in std_logic_vector(4 downto 0);
MUXED_B_i : in std_logic_vector(31 downto 0);
S_MUX_ALUIN_i : in std_logic;
FW_X_i : in std_logic_vector(31 downto 0);
FW_W_i : in std_logic_vector(31 downto 0);
FW_4_i : in std_logic_vector(31 downto 0);
S_FW_A_i : in std_logic_vector(1 downto 0);
S_FW_B_i : in std_logic_vector(1 downto 0);
muxed_dest : out std_logic_vector(4 downto 0);
muxed_B : out std_logic_vector(31 downto 0);
S_MUX_DEST_i : in std_logic_vector(1 downto 0);
OP : in AluOp;
ALUW_i : in std_logic_vector(12 downto 0);
DOUT : out std_logic_vector(31 downto 0);
stall_o : out std_logic;
clock : in std_logic;
Reset : in std_logic
);
end component;
component mem_regs
port (
W_i : in std_logic_vector(31 downto 0);
D3_i : in std_logic_vector(4 downto 0);
W_o : out std_logic_vector(31 downto 0);
D3_o : out std_logic_vector(4 downto 0);
FW_4_o : out std_logic_vector(31 downto 0);
clk : in std_logic;
rst : in std_logic
);
end component;
component mem_block
port (
X_i : in std_logic_vector(31 downto 0);
LOAD_i : in std_logic_vector(31 downto 0);
S_MUX_MEM_i : in std_logic;
W_o : out std_logic_vector(31 downto 0)
);
end component;
component fw_logic is
port (
clock : in std_logic;
reset : in std_logic;
D1_i : in std_logic_vector(4 downto 0); -- taken from output of destination mux in EXE stage
rAdec_i : in std_logic_vector(4 downto 0); -- taken from IR directly in DEC stage
D2_i : in std_logic_vector(4 downto 0);
D3_i : in std_logic_vector(4 downto 0);
rA_i : in std_logic_vector(4 downto 0);
rB_i : in std_logic_vector(4 downto 0);
S_mem_W : in std_logic; -- will the current instruction in MEM stage write to RF?
S_mem_LOAD : in std_logic; -- is the current instruction in MEM stage a LOAD?
S_wb_W : in std_logic; -- will the current instruction in WB stage write to RF?
S_exe_W : in std_logic; -- will the current instruction in EXE stage write to RF?
S_FWAdec : out std_logic_vector(1 downto 0); -- this signal controls forward of A in DEC stage
S_FWA : out std_logic_vector(1 downto 0);
S_FWB : out std_logic_vector(1 downto 0)
);
end component;
component btb is
generic (
N_LINES : integer ;
SIZE : integer
);
port (
clock : in std_logic;
reset : in std_logic;
stall_i : in std_logic;
TAG_i : in std_logic_vector(N_LINES - 1 downto 0); -- TAG is taken from the PC ( remove 2 lowest bits)
target_PC_i : in std_logic_vector(SIZE - 1 downto 0); -- correct value from dec stage
was_taken_i : in std_logic; -- correct value from dec stage
predicted_next_PC_o : out std_logic_vector(SIZE - 1 downto 0); -- output to PC
taken_o : out std_logic; -- control to bypass PC_MUX and use prediction
mispredict_o : out std_logic -- 1 when last branch was not correctly predicted
);
end component;
signal PC : std_logic_vector(31 downto 0);
signal PC4 : std_logic_vector(31 downto 0);
signal TARGET_PC : std_logic_vector(31 downto 0);
signal IR : std_logic_vector(31 downto 0);
signal NPCF : std_logic_vector(31 downto 0);
signal AtoComp : std_logic_vector(31 downto 0);
signal dummy_A : std_logic_vector(31 downto 0);
signal dummy_B : std_logic_vector(31 downto 0);
signal dummy_branch_target : std_logic_vector(31 downto 0);
signal dummy_sum_addr : std_logic_vector(31 downto 0);
signal dummy_S_MUX_PC_BUS : std_logic_vector(1 downto 0);
signal dummy_S_MUX_DEST : std_logic_vector(1 downto 0);
signal dummy_S_EXT : std_logic;
signal dummy_S_EXT_SIGN : std_logic;
signal dummy_S_MUX_LINK : std_logic;
signal dummy_S_MUX_ALUIN : std_logic;
signal dummy_S_EQ_NEQ : std_logic;
signal dummy_S_MEM_W_R : std_logic;
signal dummy_S_MEM_EN : std_logic;
signal dummy_S_RF_W_wb : std_logic;
signal dummy_S_RF_W_mem : std_logic;
signal dummy_S_RF_W_exe : std_logic;
signal dummy_S_FWA2exe : std_logic_vector(1 downto 0);
signal dummy_S_FWB2exe : std_logic_vector(1 downto 0);
signal dummy_S_FWAdec : std_logic_vector(1 downto 0);
signal dummy_S_MUX_MEM : std_logic;
signal dummy_OP : AluOp;
signal ALUW_dec : std_logic_vector(12 downto 0);
signal ALUW : std_logic_vector(12 downto 0);
signal help_B : std_logic_vector(31 downto 0);
signal help_DEST : std_logic_vector(4 downto 0);
signal help_IMM : std_logic_vector(31 downto 0);
signal A2exe : std_logic_vector(31 downto 0);
signal B2exe : std_logic_vector(31 downto 0);
signal IMM2exe : std_logic_vector(31 downto 0);
signal D12exe : std_logic_vector(4 downto 0);
signal rA2reg : std_logic_vector(4 downto 0);
signal rB2reg : std_logic_vector(4 downto 0);
signal rC2reg : std_logic_vector(4 downto 0);
signal rA2fw : std_logic_vector(4 downto 0);
signal rB2mux : std_logic_vector(4 downto 0);
signal rC2mux : std_logic_vector(4 downto 0);
signal muxed_dest2exe : std_logic_vector(4 downto 0);
signal X2mem : std_logic_vector(31 downto 0);
signal S2mem : std_logic_vector(31 downto 0);
signal D22D3 : std_logic_vector(4 downto 0);
signal S2wb : std_logic_vector(31 downto 0);
signal X2wb : std_logic_vector(31 downto 0);
signal L2wb : std_logic_vector(31 downto 0);
signal W2wb : std_logic_vector(31 downto 0);
signal wb2reg : std_logic_vector(31 downto 0);
signal D32reg : std_logic_vector(4 downto 0);
signal stall_fetch : std_logic;
signal stall_btb : std_logic;
signal stall_decode : std_logic;
signal stall_exe : std_logic;
signal exe_stall_cu : std_logic;
signal dec_stall_cu : std_logic;
signal was_taken_from_jl : std_logic;
signal was_taken : std_logic;
signal was_branch : std_logic;
signal was_jmp : std_logic;
signal enable_regfile : std_logic;
signal mispredict : std_logic;
signal take_prediction : std_logic;
signal wrong_back_pred : std_logic;
signal predicted_PC : std_logic_vector(31 downto 0);
signal FW4 : std_logic_vector(31 downto 0);
begin
was_taken <= (was_taken_from_jl and was_branch) or was_jmp;
-- instance of DLX
UFETCH_BLOCK: fetch_block
Port Map(
branch_target_i => dummy_branch_target,
sum_addr_i => dummy_sum_addr,
A_i => dummy_A,
NPC4_i => NPCF,
S_MUX_PC_BUS_i => dummy_S_MUX_PC_BUS,
PC_o => PC,
PC4_o => PC4, --this is actually PC4
PC_BUS_pre_BTB => TARGET_PC,
stall_i => stall_fetch,
mispredict_i => mispredict,
take_prediction_i => take_prediction,
predicted_PC => predicted_PC,
clk => clock,
rst => rst
);
UBTB : btb
generic map(
N_LINES => PRED_SIZE,
SIZE => 32
)
port map(
clock => clock,
reset => rst,
stall_i => stall_btb,
TAG_i => PC(2+PRED_SIZE-1 downto 2),
target_PC_i => TARGET_PC,
was_taken_i => was_taken,
predicted_next_PC_o => predicted_PC,
taken_o => take_prediction,
mispredict_o => mispredict
);
IRAM_Addr_o <= PC;
UFEETCH_REGS: fetch_regs
Port Map (PC4,IRAM_Dout_i,NPCF,IR,stall_decode,clock, rst);
UJUMP_LOGIC: jump_logic
Port Map (
NPCF_i => NPCF,
IR_i => IR,
A_i => AtoComp,
A_o => dummy_A,
rA_o => rA2reg,
rB_o => rB2reg,
rC_o => rC2reg,
branch_target_o => dummy_branch_target,
sum_addr_o => dummy_sum_addr,
extended_imm => help_IMM,
taken_o => was_taken_from_jl,
FW_X_i => X2wb,
FW_W_i => wb2reg,
S_FW_Adec_i => dummy_S_FWAdec,
S_EXT_i => dummy_S_EXT,
S_EXT_SIGN_i => dummy_S_EXT_SIGN,
S_MUX_LINK_i => dummy_S_MUX_LINK,
S_EQ_NEQ_i => dummy_S_EQ_NEQ
);
UCU: dlx_cu
generic map(
MICROCODE_MEM_SIZE => 64,
FUNC_SIZE => 11,
OP_CODE_SIZE => 6,
IR_SIZE => 32,
CW_SIZE => 13
)
Port Map (
Clk => clock,
Rst => rst,
IR_IN => IR,
stall_exe_i => exe_stall_cu,
mispredict_i => mispredict,
D1_i => muxed_dest2exe,
D2_i => D22D3,
S1_LATCH_EN => open,
S2_LATCH_EN => open,
S3_LATCH_EN => open,
S_MUX_PC_BUS => dummy_S_MUX_PC_BUS,
S_EXT => dummy_S_EXT,
S_EXT_SIGN => dummy_S_EXT_SIGN,
S_EQ_NEQ => dummy_S_EQ_NEQ,
S_MUX_LINK => dummy_S_MUX_LINK,
S_MUX_DEST => dummy_S_MUX_DEST,
S_MUX_MEM => dummy_S_MUX_MEM,
S_MEM_EN => dummy_S_MEM_EN,
S_MEM_W_R => dummy_S_MEM_W_R,
S_RF_W_wb => dummy_S_RF_W_wb,
S_RF_W_mem => dummy_S_RF_W_mem,
S_RF_W_exe => dummy_S_RF_W_exe,
S_MUX_ALUIN => dummy_S_MUX_ALUIN,
stall_exe_o => stall_exe,
stall_dec_o => stall_decode,
stall_fetch_o => stall_fetch,
stall_btb_o => stall_btb,
was_branch_o => was_branch,
was_jmp_o => was_jmp,
ALU_WORD_o => ALUW_dec,
ALU_OPCODE => dummy_OP
);
enable_regfile <= not(stall_decode);
RF: dlx_regfile
Port Map (
Clk => clock,
Rst => rst,
ENABLE => enable_regfile,
RD1 => '1',
RD2 => '1',
WR => dummy_S_RF_W_mem,
ADD_WR => D22D3,
ADD_RD1 => IRAM_Dout_i(25 downto 21),
ADD_RD2 => IRAM_Dout_i(20 downto 16),
DATAIN => W2wb,
OUT1 => AtoComp,
OUT2 => dummy_B
);
UDECODE_REGS: decode_regs
Port Map (
A_i => AtoComp,
B_i => dummy_B,
rA_i => rA2reg,
rB_i => rB2reg,
rC_i => rC2reg,
IMM_i => help_IMM,
ALUW_i => ALUW_dec,
A_o => A2exe,
B_o => B2exe,
rA_o => rA2fw,
rB_o => rB2mux,
rC_o => rC2mux,
IMM_o => IMM2exe,
stall_i => stall_exe,
ALUW_o => ALUW,
clk => clock,
rst => rst
);
UEXECUTE_REGS: execute_regs
Port Map (X2mem,S2mem,muxed_dest2exe,X2wb,S2wb,D22D3,'0',clock,rst);
UEXECUTE_BLOCK : execute_block
Port Map(
IMM_i => IMM2exe,
A_i => A2exe,
rB_i => rB2mux,
rC_i => rC2mux,
MUXED_B_i => B2exe,
S_MUX_ALUIN_i => dummy_S_MUX_ALUIN,
FW_X_i => X2wb,
FW_W_i => wb2reg,
FW_4_i => FW4,
S_FW_A_i => dummy_S_FWA2exe,
S_FW_B_i => dummy_S_FWB2exe,
muxed_dest => muxed_dest2exe,
muxed_B => S2mem,
S_MUX_DEST_i => dummy_S_MUX_DEST,
OP => dummy_OP,
ALUW_i => ALUW,
DOUT => X2mem,
stall_o => exe_stall_cu,
clock => clock,
Reset => rst
);
-- UDMEM : DRAM
-- generic map ( RAM_DEPTH => 4096, I_SIZE => 32)
-- Port Map (clock,rst,dummy_S_MEM_EN,dummy_S_MEM_W_R,S2wb,X2wb,L2wb);
DRAM_Enable_o <= dummy_S_MEM_EN;
DRAM_WR_o <= dummy_S_MEM_W_R;
DRAM_Din_o <= S2wb;
DRAM_Addr_o <= X2wb;
L2wb <= DRAM_Dout_i;
UMEM_REGS: mem_regs
Port Map (W2wb,D22D3,wb2reg,D32reg,FW4,clock,rst);
UMEM_BLOCK: mem_block
Port Map (X2wb,L2wb,dummy_S_MUX_MEM,W2wb);
UFW_LOGIC: fw_logic
Port Map(
clock => clock,
reset => rst,
D1_i => muxed_dest2exe,
D2_i => D22D3,
D3_i => D32reg,
rAdec_i => IR(25 downto 21),
rA_i => rA2fw,
rB_i => rB2mux,
S_exe_W => dummy_S_RF_W_exe,
S_mem_W => dummy_S_RF_W_mem,
S_mem_LOAD => dummy_S_MUX_MEM,
S_wb_W => dummy_S_RF_W_wb,
S_FWAdec => dummy_S_FWAdec,
S_FWA => dummy_S_FWA2exe,
S_FWB => dummy_S_FWB2exe
);
end arch;
|
bsd-2-clause
|
dpolad/dlx
|
DLX_vhd/a.a-CU_HW.vhd
|
1
|
13316
|
-- *** a.a-CU-HW.vhd *** --
-- this block is describes the control unit.
-- This is a Hardwired control unit
-- Microcode LUT is declared directly here
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use work.myTypes.all;
entity dlx_cu is
generic (
MICROCODE_MEM_SIZE : integer := 64; -- Microcode Memory Size
FUNC_SIZE : integer := 11; -- Func Field Size for R-Type Ops
OP_CODE_SIZE : integer := 6; -- Op Code Size
IR_SIZE : integer := 32; -- Instruction Register Size
CW_SIZE : integer := 13); -- Control Word Size
port (
Clk : in std_logic; -- Clock
Rst : in std_logic; -- Reset: Active-High
IR_IN : in std_logic_vector(IR_SIZE - 1 downto 0); -- Instruction Register
stall_exe_i : in std_logic; -- Stall signal coming from EXE stage
mispredict_i : in std_logic;
D1_i : in std_logic_vector(4 downto 0); -- Destination register of exe stage
D2_i : in std_logic_vector(4 downto 0); -- Destination register of mem stage
S1_LATCH_EN : out std_logic; -- Latch enable of Fetch stage
S2_LATCH_EN : out std_logic; -- Latch enable of Dec stage
S3_LATCH_EN : out std_logic; -- Latch enable of Exe stage
S_MUX_PC_BUS : out std_logic_vector(1 downto 0); -- Control of mux to PC
S_EXT : out std_logic; -- Control of extender
S_EXT_SIGN : out std_logic; -- Control of extender sign
S_EQ_NEQ : out std_logic; -- Control of Comparator
S_MUX_DEST : out std_logic_vector(1 downto 0); -- Control of Destination register
S_MUX_LINK : out std_logic; -- Control of link mux
S_MUX_MEM : out std_logic; -- Control of mux to memory address
S_MEM_W_R : out std_logic; -- Control of mem W/R
S_MEM_EN : out std_logic; -- Control mem enable
S_RF_W_wb : out std_logic; -- Control WB enable
S_RF_W_mem : out std_logic; -- Current op in mem is going to write on wb?
S_RF_W_exe : out std_logic; -- Current op in exe is going to write on wb?
S_MUX_ALUIN : out std_logic; -- Control ALU input ( IMM or B )
stall_exe_o : out std_logic; -- Stall exe stage
stall_dec_o : out std_logic; -- Stall dec stage
stall_fetch_o : out std_logic; -- Stall fetch stage
stall_btb_o : out std_logic; -- Stall btb
was_branch_o : out std_logic; -- Op in decode is a branch or not?
was_jmp_o : out std_logic;
ALU_WORD_o : out std_logic_vector(12 downto 0); -- Opcode to ALU
ALU_OPCODE : out aluOp -- Opcode to ALU
);
end dlx_cu;
architecture dlx_cu_hw of dlx_cu is
-- ***************************
-- *** SIGNAL DECLARATIONS ***
-- ***************************
-- this is the microcode memory, it works as a LUT -> to decode an instruction it's opcode indexes this memory
signal IR_opcode : std_logic_vector(OP_CODE_SIZE -1 downto 0); -- OpCode part of IR
signal IR_func : std_logic_vector(FUNC_SIZE -1 downto 0); -- Func part of IR when Rtype
signal cw_d : std_logic_vector(CW_SIZE - 1 downto 0);
signal cw_from_mem : std_logic_vector(CW_SIZE - 1 downto 0); -- full control word read from cw_mem
-- control word is shifted to the correct stage
signal cw_e : std_logic_vector(CW_SIZE - 1 - 6 downto 0); -- second stage
signal cw_m : std_logic_vector(CW_SIZE - 1 - 9 downto 0); -- third stage
signal cw_w : std_logic_vector(CW_SIZE - 1 - 12 downto 0); -- fourth stage
signal aluOpcode_d : aluOp := NOP; -- ALUOP defined in package -- ! MIGHT NOT BE SYNTHESIZABLE
signal aluOpcode_e : aluOp := NOP; -- shifted ALUOP to feed execute stage -- ! MIGHT NOT BE SYNTHESIZABLE
signal S_MEM_LOAD : std_logic; -- is current op in mem stage a LOAD?
signal S_EXE_LOAD : std_logic; -- is current op in exe stage a LOAD?
-- stall signals from stall unit
signal stall_exe_o_TEMP : std_logic;
signal stall_dec_o_TEMP : std_logic;
signal stall_btb_o_TEMP : std_logic;
signal stall_fetch_o_TEMP : std_logic;
signal bubble_dec : std_logic; -- transform next op in decode into a NOP
signal next_bubble_dec : std_logic;
signal bubble_exe : std_logic; -- transform next op in exe into a NOP
signal next_bubble_exe : std_logic;
-- ********************************
-- *** COMPONENTS DECLARATION ***
-- ********************************
component cw_mem is
generic (
MICROCODE_MEM_SIZE : integer; -- Microcode Memory Size
OP_CODE_SIZE : integer; -- Op Code Size
CW_SIZE : integer -- Control Word Size
);
port (
OPCODE_IN : in std_logic_vector(OP_CODE_SIZE - 1 downto 0); -- Instruction Register
CW_OUT : out std_logic_vector(CW_SIZE - 1 downto 0)
);
end component;
component alu_ctrl is
port (
OP : in AluOp;
BOOTH_STALL : in std_logic;
ALU_WORD : out std_logic_vector(12 downto 0)
);
end component;
-- instantiation of stall_logic block
component stall_logic is
generic (
FUNC_SIZE : integer; -- Func Field Size for R-Type Ops
OP_CODE_SIZE : integer -- Op Code Size
);
port (
-- Instruction Register
OPCODE_i : in std_logic_vector(OP_CODE_SIZE-1 downto 0);
FUNC_i : in std_logic_vector(FUNC_SIZE-1 downto 0);
rA_i : in std_logic_vector(4 downto 0);
rB_i : in std_logic_vector(4 downto 0);
D1_i : in std_logic_vector(4 downto 0); -- taken from output of destination mux in EXE stage
D2_i : in std_logic_vector(4 downto 0);
S_mem_LOAD_i : in std_logic;
S_exe_LOAD_i : in std_logic;
S_exe_WRITE_i : in std_logic;
S_MUX_PC_BUS_i : in std_logic_vector(1 downto 0);
mispredict_i : in std_logic;
bubble_dec_o : out std_logic;
bubble_exe_o : out std_logic;
stall_exe_o : out std_logic;
stall_dec_o : out std_logic;
stall_btb_o : out std_logic;
stall_fetch_o : out std_logic
);
end component;
begin
-- ********************************
-- *** COMPONENTS INSTANTIATION ***
-- ********************************
STALL_L : stall_logic
generic map (
FUNC_SIZE => 11,
OP_CODE_SIZE => 6
)
port map(
-- Instruction Register
OPCODE_i => IR_opcode,
FUNC_i => IR_func,
rA_i => IR_IN(25 downto 21),
rB_i => IR_IN(20 downto 16),
D1_i => D1_i,
D2_i => D2_i,
S_mem_LOAD_i => S_MEM_LOAD,
S_exe_LOAD_i => S_EXE_LOAD,
S_exe_WRITE_i => cw_e(CW_SIZE - 13),
S_MUX_PC_BUS_i => cw_d(CW_SIZE - 1 downto CW_SIZE - 2),
mispredict_i => mispredict_i,
bubble_dec_o => next_bubble_dec,
bubble_exe_o => next_bubble_exe,
stall_exe_o => stall_exe_o_TEMP,
stall_dec_o => stall_dec_o_TEMP,
stall_btb_o => stall_btb_o_TEMP,
stall_fetch_o => stall_fetch_o_TEMP
);
CWM : cw_mem
generic map(
MICROCODE_MEM_SIZE => MICROCODE_MEM_SIZE,
OP_CODE_SIZE => OP_CODE_SIZE,
CW_SIZE => CW_SIZE
)
port map(
OPCODE_IN => IR_opcode,
CW_OUT => cw_from_mem
);
ALU_C: alu_ctrl
port map(
OP => aluopcode_d,
BOOTH_STALL => stall_dec_o_TEMP,
ALU_WORD => ALU_WORD_o
);
-- stall signals for each individual stage of the pipeline
-- an OR is needed cause a stall might come from ALU too
stall_exe_o <= stall_exe_i or stall_exe_o_TEMP;
stall_dec_o <= stall_exe_i or stall_dec_o_TEMP;
stall_fetch_o <= stall_exe_i or stall_fetch_o_TEMP;
stall_btb_o <= stall_exe_i or stall_btb_o_TEMP;
-- split function in OPCODE and FUNC
IR_opcode(5 downto 0) <= IR_IN(31 downto 26);
IR_func(10 downto 0) <= IR_IN(FUNC_SIZE - 1 downto 0);
-- control work is assigned to the word looked up in microcode memory
-- in case of bubble_dec, a NOP cw is fed instead
cw_d <= cw_from_mem when bubble_dec = '0' else "0000000000000";
-- *** ATM THE LATCH ENABLES ARE DOING NOTHING! EVERYTHING IS CONTROLLED BY STALL ***
S1_LATCH_EN <= '1';
S2_LATCH_EN <= '1';
S3_LATCH_EN <= '1';
-- DEC stage control signals
S_MUX_PC_BUS <= cw_d(CW_SIZE - 1 downto CW_SIZE - 2);
S_EXT <= cw_d(CW_SIZE - 3);
S_EXT_SIGN <= cw_d(CW_SIZE - 4);
S_EQ_NEQ <= cw_d(CW_SIZE - 5);
S_MUX_LINK <= cw_d(CW_SIZE - 6);
-- EXE stage control signals
S_MUX_ALUIN <= cw_e(CW_SIZE - 7);
S_MUX_DEST <= cw_e(CW_SIZE - 8 downto CW_SIZE - 9);
-- MEM stage control signals
S_MEM_EN <= cw_m(CW_SIZE - 10);
S_MEM_W_R <= cw_m(CW_SIZE - 11);
S_MUX_MEM <= cw_m(CW_SIZE - 12);
-- WB stage control signals
S_RF_W_wb <= cw_w(CW_SIZE - 13);
-- RF write signal is sent to other stages to compute hazards/forwarding
S_RF_W_mem <= cw_m(CW_SIZE - 13);
S_RF_W_exe <= cw_e(CW_SIZE - 13);
-- is the current op in mem stage a LOAD?
S_MEM_LOAD <= cw_m(CW_SIZE - 10) and (not cw_m(CW_SIZE - 11));
-- is the current op in exe stage a LOAD?
S_EXE_LOAD <= cw_e(CW_SIZE - 10) and (not cw_e(CW_SIZE - 11));
-- is current op in DEC stage a branch?
was_branch_o <= cw_d(CW_SIZE - 1) and cw_d(CW_SIZE - 2);
-- is current op in DEC stage an inconditional jump?
was_jmp_o <= cw_d(CW_SIZE - 1) xor cw_d(CW_SIZE - 2);
ALU_OPCODE <= aluOpcode_e;
-- ********************************
-- *** PROCESSES ***
-- ********************************
-- sequential process to manage and pipeline control words
CW_PIPE: process (Clk, Rst)
begin -- process Clk
if Rst = '1' then -- asynchronous reset (active high)
cw_e <= (others => '0');
cw_m <= (others => '0');
cw_w <= (others => '0');
aluOpcode_e <= NOP;
elsif Clk'event and Clk = '1' then -- rising clock edge
-- update of the bubbe signal
-- bubble means: cancel next operation and make it a nop ( used in case of misprediction or inconditional jumps)
bubble_dec <= next_bubble_dec;
bubble_exe <= next_bubble_exe;
-- EXE stalled
if stall_exe_i = '1' or stall_exe_o_TEMP = '1' then
cw_m <= "0000"; -- NOP instertion
cw_e <= cw_e;
aluOpcode_e <= aluOpcode_e;
-- DEC stalled
elsif stall_dec_o_TEMP = '1' then
cw_e <= "0000000"; -- NOP instertion
cw_m <= cw_e(CW_SIZE - 1 - 9 downto 0);
-- no stall
else
cw_e <= cw_d(CW_SIZE - 1 - 6 downto 0);
cw_m <= cw_e(CW_SIZE - 1 - 9 downto 0);
aluOpcode_e <= aluOpcode_d;
end if;
-- WB cannot be stalled
cw_w <= cw_m(CW_SIZE - 1 - 12 downto 0);
end if;
end process CW_PIPE;
-- combinatorial process to generate ALU OP CODES
ALU_OP_CODE_P : process (IR_opcode, IR_func)
begin
case conv_integer(unsigned(IR_opcode)) is
-- case of R type requires analysis of FUNC
when 0 =>
case conv_integer(unsigned(IR_func)) is
when 4 => aluOpcode_d <= SLLS; -- sll according to instruction set coding
when 6 => aluOpcode_d <= SRLS;
when 7 => aluOpcode_d <= SRAS;
when 32 => aluOpcode_d <= ADDS;
when 33 => aluOpcode_d <= ADDUS;
when 34 => aluOpcode_d <= SUBS;
when 35 => aluOpcode_d <= SUBUS;
when 36 => aluOpcode_d <= ANDS;
when 37 => aluOpcode_d <= ORS;
when 38 => aluOpcode_d <= XORS;
when 40 => aluOpcode_d <= SEQS;
when 41 => aluOpcode_d <= SNES;
when 42 => aluOpcode_d <= SLTS;
when 43 => aluOpcode_d <= SGTS;
when 44 => aluOpcode_d <= SLES;
when 45 => aluOpcode_d <= SGES;
when 48 => aluOpcode_d <= MOVI2SS;
when 49 => aluOpcode_d <= MOVS2IS;
when 50 => aluOpcode_d <= MOVFS;
when 51 => aluOpcode_d <= MOVDS;
when 52 => aluOpcode_d <= MOVFP2IS;
when 53 => aluOpcode_d <= MOVI2FP;
when 54 => aluOpcode_d <= MOVI2TS;
when 55 => aluOpcode_d <= MOVT2IS;
when 58 => aluOpcode_d <= SLTUS;
when 59 => aluOpcode_d <= SGTUS;
when 60 => aluOpcode_d <= SLEUS;
when 61 => aluOpcode_d <= SGEUS;
when others => aluOpcode_d <= NOP; -- might not be synthesizable
end case;
-- type F instruction case -- MULT only at the moment
when 1 =>
case conv_integer(unsigned(IR_func)) is
when 22 => aluOpcode_d <= MULTU;
when 14 => aluOpcode_d <= MULTS;
when others => aluOpcode_d <= NOP; -- might not be synthesizable
end case;
-- I-TYPE instructions
when 2 => aluOpcode_d <= NOP; -- j
when 3 => aluOpcode_d <= NOP; -- jal
when 4 => aluOpcode_d <= NOP; -- beqz
when 5 => aluOpcode_d <= NOP; -- bnez
when 8 => aluOpcode_d <= ADDS; -- addi
when 9 => aluOpcode_d <= ADDUS; -- addui
when 10 => aluOpcode_d <= SUBS; -- subi
when 11 => aluOpcode_d <= SUBUS; -- subui
when 12 => aluOpcode_d <= ANDS; -- andi
when 13 => aluOpcode_d <= ORS; -- ori
when 14 => aluOpcode_d <= XORS; -- xori
when 18 => aluOpcode_d <= NOP; -- jr
when 19 => aluOpcode_d <= NOP; -- jalr
when 20 => aluOpcode_d <= SLLS; -- slli
when 21 => aluOpcode_d <= NOP; -- nop
when 22 => aluOpcode_d <= SRLS; -- srli
when 23 => aluOpcode_d <= SRAS; -- srai
when 24 => aluOpcode_d <= SEQS; -- seqi
when 25 => aluOpcode_d <= SNES; -- snei
when 26 => aluOpcode_d <= SLTS; -- slti
when 27 => aluOpcode_d <= SGTS; -- sgti
when 28 => aluOpcode_d <= SLES; -- slei
when 29 => aluOpcode_d <= SGES; -- sgei
when 35 => aluOpcode_d <= ADDS; -- lw
when 43 => aluOpcode_d <= ADDS; -- sw
when 58 => aluOpcode_d <= SLTUS; -- sltui
when 59 => aluOpcode_d <= SGTUS; -- sgtui
when 60 => aluOpcode_d <= SLEUS; -- sleui
when 61 => aluOpcode_d <= SGEUS; -- sgeui
when others => aluOpcode_d <= NOP; -- might not be synthesizable
end case;
end process ALU_OP_CODE_P;
end dlx_cu_hw;
|
bsd-2-clause
|
dpolad/dlx
|
DLX_vhd/a.i.a.d.b-SUMGEN.vhd
|
2
|
913
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity sum_gen is
generic (
N : integer := 32);
Port ( A: In std_logic_vector(N-1 downto 0);
B: In std_logic_vector(N-1 downto 0);
Cin: In std_logic_vector(N/4 downto 0);
S: Out std_logic_vector(N-1 downto 0)
);
end sum_gen;
architecture STRUCTURAL of sum_gen is
component carry_sel_gen
generic( N : integer := 4);
Port ( A: In std_logic_vector(N-1 downto 0);
B: In std_logic_vector(N-1 downto 0);
Ci: In std_logic;
S: Out std_logic_vector(N-1 downto 0);
Co: Out std_logic);
end component;
begin
csel_gen: for i in 0 to N/4-1 generate
csel_N: carry_sel_gen port map(A((i+1)*4-1 downto i*4),B((i+1)*4-1 downto i*4),Cin(i),S((i+1)*4-1 downto i*4),open);
end generate csel_gen;
end STRUCTURAL;
|
bsd-2-clause
|
dpolad/dlx
|
DLX_vhd/useless/fakealu.vhd
|
1
|
3133
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.myTypes.all;
entity fakeALU is
generic (
DATA_SIZE : integer := 32);
port (
IN1 : in std_logic_vector(DATA_SIZE - 1 downto 0);
IN2 : in std_logic_vector(DATA_SIZE - 1 downto 0);
OP : in AluOp;
DOUT : out std_logic_vector(DATA_SIZE - 1 downto 0);
ZEROUT : out std_logic;
stall_o : out std_logic;
Clock : in std_logic;
Reset : in std_logic
);
end fakeALU;
architecture Bhe of fakealu is
component fake_mult
port (
IN1 : in std_logic_vector(31 downto 0);
IN2 : in std_logic_vector(31 downto 0);
DOUT : out std_logic_vector(31 downto 0);
stall_o : out std_logic;
enable : in std_logic;
Clock : in std_logic;
Reset : in std_logic
);
end component;
signal enable2mult : std_logic := '0';
signal multDATA : std_logic_vector(31 downto 0);
begin
MULT: fake_mult port Map(
IN1 => IN1,
IN2 => IN2,
DOUT => multDATA,
stall_o => stall_o,
enable => enable2mult,
Clock => Clock,
Reset => Reset
);
ZEROUT <= '0';
process(IN1,IN2,OP,multDATA)
begin
case OP is
when NOP => DOUT <= (others => '0');
when SLLS => DOUT <= (others => '0');
when SRLS => DOUT <= (others => '0');
when SRAS => DOUT <= (others => '0');
when ADDS => DOUT <= std_logic_vector(signed(IN1)+signed(IN2));
when ADDUS => DOUT <= std_logic_vector(unsigned(IN1)+unsigned(IN2));
when SUBS => DOUT <= std_logic_vector(signed(IN1)-signed(IN2));
when SUBUS => DOUT <= std_logic_vector(unsigned(IN1)-unsigned(IN2));
when ANDS => DOUT <= IN1 and IN2;
when ORS => DOUT <= IN1 or IN2;
when XORS => DOUT <= IN1 xor IN2;
when SEQS =>
if(IN1 = IN2) then
DOUT <= X"00000001";
else
DOUT <= X"00000000";
end if;
when SNES =>
if(IN1 /= IN2) then
DOUT <= X"00000001";
else
DOUT <= X"00000000";
end if;
when SLTS =>
if(signed(IN1) < signed(IN2)) then
DOUT <= X"00000001";
else
DOUT <= X"00000000";
end if;
when SGTS => DOUT <= (others => '0');
when SLES =>
if(signed(IN1) <= signed(IN2)) then
DOUT <= X"00000001";
else
DOUT <= X"00000000";
end if;
when SGES =>
if(signed(IN1) >= signed(IN2)) then
DOUT <= X"00000001";
else
DOUT <= X"00000000";
end if;
when MOVI2SS => DOUT <= (others => '0');
when MOVS2IS => DOUT <= (others => '0');
when MOVFS => DOUT <= (others => '0');
when MOVDS => DOUT <= (others => '0');
when MOVFP2IS => DOUT <= (others => '0');
when MOVI2FP => DOUT <= (others => '0');
when MOVI2TS => DOUT <= (others => '0');
when MOVT2IS => DOUT <= (others => '0');
when SLTUS => DOUT <= (others => '0');
when SGTUS => DOUT <= (others => '0');
when SLEUS => DOUT <= (others => '0');
when SGEUS => DOUT <= (others => '0');
when MULTU =>
DOUT <= multDATA;
enable2mult <= '1';
when others => DOUT <= (others => '0');
end case;
end process;
end Bhe;
|
bsd-2-clause
|
dpolad/dlx
|
DLX_synth/a.i.a.c-LOGICUNIT.vhd
|
2
|
674
|
-- logic_unit.vhd --
-- TODO: replace this with a better structural LOGIC UNIT.
library ieee;
use ieee.std_logic_1164.all;
--use work.myTypes.all;
entity logic_unit is
generic (
SIZE : integer := 32
);
port (
IN1 : in std_logic_vector(SIZE - 1 downto 0);
IN2 : in std_logic_vector(SIZE - 1 downto 0);
CTRL : in std_logic_vector(1 downto 0); -- need to do only and, or and xor
OUT1 : out std_logic_vector(SIZE - 1 downto 0)
);
end logic_unit;
architecture Bhe of logic_unit is
begin
OUT1 <= IN1 and IN2 when CTRL = "00" else
IN1 or IN2 when CTRL = "01" else
IN1 xor IN2 when CTRL = "10" else
(others => '0'); -- should never appear
end Bhe;
|
bsd-2-clause
|
dpolad/dlx
|
DLX_vhd/a.a.c-STALLLOGIC.vhd
|
1
|
4148
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_misc.all;
use work.myTypes.all;
--use ieee.numeric_std.all;
--use work.all;
entity stall_logic is
generic (
FUNC_SIZE : integer := 11; -- Func Field Size for R-Type Ops
OP_CODE_SIZE : integer := 6 -- Op Code Size
);
port (
-- Instruction Register
OPCODE_i : in std_logic_vector(OP_CODE_SIZE-1 downto 0);
FUNC_i : in std_logic_vector(FUNC_SIZE-1 downto 0);
rA_i : in std_logic_vector(4 downto 0);
rB_i : in std_logic_vector(4 downto 0);
D1_i : in std_logic_vector(4 downto 0); -- taken from output of destination mux in EXE stage
D2_i : in std_logic_vector(4 downto 0);
S_mem_LOAD_i : in std_logic;
S_exe_LOAD_i : in std_logic;
S_exe_WRITE_i : in std_logic;
S_MUX_PC_BUS_i : in std_logic_vector(1 downto 0);
mispredict_i : in std_logic;
bubble_dec_o : out std_logic;
bubble_exe_o : out std_logic;
stall_exe_o : out std_logic;
stall_dec_o : out std_logic;
stall_btb_o : out std_logic;
stall_fetch_o : out std_logic
);
end stall_logic;
architecture stall_logic_hw of stall_logic is
signal IS_JMP_BRANCH : std_logic;
signal STALL_JMP_BRANCH_DECODE : std_logic;
signal STALL_JMP_BRANCH_LOAD : std_logic;
signal STALL_LOAD_RTYPE : std_logic;
signal STALL_LOAD_ITYPE : std_logic;
signal IS_NO_STALL : std_logic;
signal IS_JMP : std_logic;
signal stall_dec_help : std_logic;
begin
-- every jump operation but branches
IS_JMP <= S_MUX_PC_BUS_i(1) xor S_MUX_PC_BUS_i(0);
-- TODO: need to add JALR???
-- this operation might have an hazard on decode stage ( need to access A )
IS_JMP_BRANCH <= (not or_reduce(OPCODE_i xor ITYPE_JR)) or (not or_reduce(OPCODE_i xor ITYPE_JALR)) or (not or_reduce(OPCODE_i xor ITYPE_BEQZ)) or (not or_reduce(OPCODE_i xor ITYPE_BNEZ));
-- jump operation that wont trigger any hazard ( do not require data from registers )
IS_NO_STALL <= (not or_reduce(OPCODE_i xor ITYPE_J)) or (not or_reduce(OPCODE_i xor ITYPE_JAL)) or (not or_reduce(OPCODE_i xor ITYPE_TRAP)) or (not or_reduce(OPCODE_i xor ITYPE_RFE)) or (not or_reduce(OPCODE_i xor ITYPE_NOP));
-- stall if current decoded instruction is JMP/BRANCH and it needs the same register as the one that will be written by current op in EXE
STALL_JMP_BRANCH_DECODE <= IS_JMP_BRANCH and S_exe_WRITE_i and (not or_reduce(rA_i xor D1_i));
-- stall if current decoded instruction is JMP/BRANCH and it needs the same register as the one that will be written by current LOAD
STALL_JMP_BRANCH_LOAD <= IS_JMP_BRANCH and S_mem_LOAD_i and (not or_reduce(rA_i xor D2_i));
-- TODO: check if all R type operations need both A and B
-- stall if there is data dependency between current op in dec and the next is a LOAD
STALL_LOAD_RTYPE <= S_exe_LOAD_i and ((not or_reduce(OPCODE_i xor RTYPE)) or (not or_reduce(OPCODE_i xor FTYPE))) and ( (not or_reduce(rA_i xor D1_i)) or (not or_reduce(rB_i xor D1_i))) ;
-- TODO: check if all ITYPE operation require A ( also already checked in IS_NO_STALL )
-- ITYPE instructions only need to look at A
-- TODO: IS RTYPE HERE CORRECT OR NOT??? CHECK WITH A TESTBENCH
STALL_LOAD_ITYPE <= S_exe_LOAD_i and (or_reduce(OPCODE_i xor RTYPE) and or_reduce(OPCODE_i xor FTYPE)) and (not IS_NO_STALL) and (not or_reduce(rA_i xor D1_i)) ;
--TODO: add stall for MULT and MULTU
--exe is never stopped at the moment
stall_exe_o <= '0';
-- stalls for ALL hazards + jumps
stall_dec_o <= stall_dec_help;
stall_dec_help <= STALL_JMP_BRANCH_LOAD or STALL_JMP_BRANCH_DECODE or STALL_LOAD_RTYPE or STALL_LOAD_ITYPE;
-- stalls for ALL hazards + jumps
stall_btb_o <= STALL_JMP_BRANCH_LOAD or STALL_JMP_BRANCH_DECODE or STALL_LOAD_RTYPE or STALL_LOAD_ITYPE ;
-- stall only in case of hazard, not for jumps
stall_fetch_o <= STALL_JMP_BRANCH_LOAD or STALL_JMP_BRANCH_DECODE or STALL_LOAD_RTYPE or STALL_LOAD_ITYPE;
-- bubble is triggered only for mispredictions or unpredictable jumps
bubble_dec_o <= mispredict_i and (not stall_dec_help);
bubble_exe_o <= stall_dec_help;
end stall_logic_hw;
|
bsd-2-clause
|
notti/dis_se
|
testbench/tb_cpu.vhd
|
1
|
17957
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library std;
use std.textio.all;
library work;
use work.all;
use work.procedures.all;
entity tb_cpu is
end tb_cpu;
architecture behav of tb_cpu is
signal rst : std_logic := '1';
signal clk : std_logic := '0';
signal clk2x : std_logic := '0';
signal ena : std_logic := '0';
signal addra : t_data2 := (others => '0');
signal doa : t_data2 := (others => '0');
signal enb : std_logic := '0';
signal addrb : t_data2 := (others => '0');
signal dob : t_data2 := (others => '0');
signal web : std_logic_vector(1 downto 0) := (others => '0');
signal dib : t_data2 := (others => '0');
signal bbusy : std_logic := '0';
signal mem : t_data2_array(4095 downto 0) := (others => (others => '0'));
signal serial : t_data_array(1023 downto 0) :=
(0 => X"55",
1 => X"AA",
2 => X"00",
3 => X"00",
4 => X"1a",
5 => X"00",
6 => X"34",
7 => X"00",
8 => X"4b",
9 => X"00",
10 => X"5f",
11 => X"00",
12 => X"6e",
13 => X"00",
14 => X"79",
15 => X"00",
16 => X"7f",
17 => X"00",
18 => X"7f",
19 => X"00",
20 => X"79",
21 => X"00",
22 => X"6e",
23 => X"00",
24 => X"5f",
25 => X"00",
26 => X"4b",
27 => X"00",
28 => X"34",
29 => X"00",
30 => X"1a",
31 => X"00",
32 => X"00",
33 => X"00",
34 => X"e6",
35 => X"00",
36 => X"cc",
37 => X"00",
38 => X"b5",
39 => X"00",
40 => X"a1",
41 => X"00",
42 => X"92",
43 => X"00",
44 => X"87",
45 => X"00",
46 => X"81",
47 => X"00",
48 => X"81",
49 => X"00",
50 => X"87",
51 => X"00",
52 => X"92",
53 => X"00",
54 => X"a1",
55 => X"00",
56 => X"b5",
57 => X"00",
58 => X"cc",
59 => X"00",
60 => X"e6",
61 => X"00",
62 => X"00",
63 => X"00",
64 => X"1a",
65 => X"00",
66 => X"34",
67 => X"00",
68 => X"4b",
69 => X"00",
70 => X"5f",
71 => X"00",
72 => X"6e",
73 => X"00",
74 => X"79",
75 => X"00",
76 => X"7f",
77 => X"00",
78 => X"7f",
79 => X"00",
80 => X"79",
81 => X"00",
82 => X"6e",
83 => X"00",
84 => X"5f",
85 => X"00",
86 => X"4b",
87 => X"00",
88 => X"34",
89 => X"00",
90 => X"1a",
91 => X"00",
92 => X"00",
93 => X"00",
94 => X"e6",
95 => X"00",
96 => X"cc",
97 => X"00",
98 => X"b5",
99 => X"00",
100 => X"a1",
101 => X"00",
102 => X"92",
103 => X"00",
104 => X"87",
105 => X"00",
106 => X"81",
107 => X"00",
108 => X"81",
109 => X"00",
110 => X"87",
111 => X"00",
112 => X"92",
113 => X"00",
114 => X"a1",
115 => X"00",
116 => X"b5",
117 => X"00",
118 => X"cc",
119 => X"00",
120 => X"e6",
121 => X"00",
122 => X"00",
123 => X"00",
124 => X"1a",
125 => X"00",
126 => X"34",
127 => X"00",
128 => X"4b",
129 => X"00",
130 => X"5f",
131 => X"00",
132 => X"6e",
133 => X"00",
134 => X"79",
135 => X"00",
136 => X"7f",
137 => X"00",
138 => X"7f",
139 => X"00",
140 => X"79",
141 => X"00",
142 => X"6e",
143 => X"00",
144 => X"5f",
145 => X"00",
146 => X"4b",
147 => X"00",
148 => X"34",
149 => X"00",
150 => X"1a",
151 => X"00",
152 => X"00",
153 => X"00",
154 => X"e6",
155 => X"00",
156 => X"cc",
157 => X"00",
158 => X"b5",
159 => X"00",
160 => X"a1",
161 => X"00",
162 => X"92",
163 => X"00",
164 => X"87",
165 => X"00",
166 => X"81",
167 => X"00",
168 => X"81",
169 => X"00",
170 => X"87",
171 => X"00",
172 => X"92",
173 => X"00",
174 => X"a1",
175 => X"00",
176 => X"b5",
177 => X"00",
178 => X"cc",
179 => X"00",
180 => X"e6",
181 => X"00",
182 => X"00",
183 => X"00",
184 => X"1a",
185 => X"00",
186 => X"34",
187 => X"00",
188 => X"4b",
189 => X"00",
190 => X"5f",
191 => X"00",
192 => X"6e",
193 => X"00",
194 => X"79",
195 => X"00",
196 => X"7f",
197 => X"00",
198 => X"7f",
199 => X"00",
200 => X"79",
201 => X"00",
202 => X"6e",
203 => X"00",
204 => X"5f",
205 => X"00",
206 => X"4b",
207 => X"00",
208 => X"34",
209 => X"00",
210 => X"1a",
211 => X"00",
212 => X"00",
213 => X"00",
214 => X"e6",
215 => X"00",
216 => X"cc",
217 => X"00",
218 => X"b5",
219 => X"00",
220 => X"a1",
221 => X"00",
222 => X"92",
223 => X"00",
224 => X"87",
225 => X"00",
226 => X"81",
227 => X"00",
228 => X"81",
229 => X"00",
230 => X"87",
231 => X"00",
232 => X"92",
233 => X"00",
234 => X"a1",
235 => X"00",
236 => X"b5",
237 => X"00",
238 => X"cc",
239 => X"00",
240 => X"e6",
241 => X"00",
242 => X"00",
243 => X"00",
244 => X"1a",
245 => X"00",
246 => X"34",
247 => X"00",
248 => X"4b",
249 => X"00",
250 => X"5f",
251 => X"00",
252 => X"6e",
253 => X"00",
254 => X"79",
255 => X"00",
256 => X"7f",
257 => X"00",
258 => X"7f",
259 => X"00",
260 => X"79",
261 => X"00",
262 => X"6e",
263 => X"00",
264 => X"5f",
265 => X"00",
266 => X"4b",
267 => X"00",
268 => X"34",
269 => X"00",
270 => X"1a",
271 => X"00",
272 => X"00",
273 => X"00",
274 => X"e6",
275 => X"00",
276 => X"cc",
277 => X"00",
278 => X"b5",
279 => X"00",
280 => X"a1",
281 => X"00",
282 => X"92",
283 => X"00",
284 => X"87",
285 => X"00",
286 => X"81",
287 => X"00",
288 => X"81",
289 => X"00",
290 => X"87",
291 => X"00",
292 => X"92",
293 => X"00",
294 => X"a1",
295 => X"00",
296 => X"b5",
297 => X"00",
298 => X"cc",
299 => X"00",
300 => X"e6",
301 => X"00",
302 => X"00",
303 => X"00",
304 => X"1a",
305 => X"00",
306 => X"34",
307 => X"00",
308 => X"4b",
309 => X"00",
310 => X"5f",
311 => X"00",
312 => X"6e",
313 => X"00",
314 => X"79",
315 => X"00",
316 => X"7f",
317 => X"00",
318 => X"7f",
319 => X"00",
320 => X"79",
321 => X"00",
322 => X"6e",
323 => X"00",
324 => X"5f",
325 => X"00",
326 => X"4b",
327 => X"00",
328 => X"34",
329 => X"00",
330 => X"1a",
331 => X"00",
332 => X"00",
333 => X"00",
334 => X"e6",
335 => X"00",
336 => X"cc",
337 => X"00",
338 => X"b5",
339 => X"00",
340 => X"a1",
341 => X"00",
342 => X"92",
343 => X"00",
344 => X"87",
345 => X"00",
346 => X"81",
347 => X"00",
348 => X"81",
349 => X"00",
350 => X"87",
351 => X"00",
352 => X"92",
353 => X"00",
354 => X"a1",
355 => X"00",
356 => X"b5",
357 => X"00",
358 => X"cc",
359 => X"00",
360 => X"e6",
361 => X"00",
362 => X"00",
363 => X"00",
364 => X"1a",
365 => X"00",
366 => X"34",
367 => X"00",
368 => X"4b",
369 => X"00",
370 => X"5f",
371 => X"00",
372 => X"6e",
373 => X"00",
374 => X"79",
375 => X"00",
376 => X"7f",
377 => X"00",
378 => X"7f",
379 => X"00",
380 => X"79",
381 => X"00",
382 => X"6e",
383 => X"00",
384 => X"5f",
385 => X"00",
386 => X"4b",
387 => X"00",
388 => X"34",
389 => X"00",
390 => X"1a",
391 => X"00",
392 => X"00",
393 => X"00",
394 => X"e6",
395 => X"00",
396 => X"cc",
397 => X"00",
398 => X"b5",
399 => X"00",
400 => X"a1",
401 => X"00",
402 => X"92",
403 => X"00",
404 => X"87",
405 => X"00",
406 => X"81",
407 => X"00",
408 => X"81",
409 => X"00",
410 => X"87",
411 => X"00",
412 => X"92",
413 => X"00",
414 => X"a1",
415 => X"00",
416 => X"b5",
417 => X"00",
418 => X"cc",
419 => X"00",
420 => X"e6",
421 => X"00",
422 => X"00",
423 => X"00",
424 => X"1a",
425 => X"00",
426 => X"34",
427 => X"00",
428 => X"4b",
429 => X"00",
430 => X"5f",
431 => X"00",
432 => X"6e",
433 => X"00",
434 => X"79",
435 => X"00",
436 => X"7f",
437 => X"00",
438 => X"7f",
439 => X"00",
440 => X"79",
441 => X"00",
442 => X"6e",
443 => X"00",
444 => X"5f",
445 => X"00",
446 => X"4b",
447 => X"00",
448 => X"34",
449 => X"00",
450 => X"1a",
451 => X"00",
452 => X"00",
453 => X"00",
454 => X"e6",
455 => X"00",
456 => X"cc",
457 => X"00",
458 => X"b5",
459 => X"00",
460 => X"a1",
461 => X"00",
462 => X"92",
463 => X"00",
464 => X"87",
465 => X"00",
466 => X"81",
467 => X"00",
468 => X"81",
469 => X"00",
470 => X"87",
471 => X"00",
472 => X"92",
473 => X"00",
474 => X"a1",
475 => X"00",
476 => X"b5",
477 => X"00",
478 => X"cc",
479 => X"00",
480 => X"e6",
481 => X"00",
482 => X"00",
483 => X"00",
484 => X"1a",
485 => X"00",
486 => X"34",
487 => X"00",
488 => X"4b",
489 => X"00",
490 => X"5f",
491 => X"00",
492 => X"6e",
493 => X"00",
494 => X"79",
495 => X"00",
496 => X"7f",
497 => X"00",
498 => X"7f",
499 => X"00",
500 => X"79",
501 => X"00",
502 => X"6e",
503 => X"00",
504 => X"5f",
505 => X"00",
506 => X"4b",
507 => X"00",
508 => X"34",
509 => X"00",
510 => X"1a",
511 => X"00",
512 => X"00",
513 => X"00",
others => X"00");
procedure hex2slv(c : character; slv : out std_logic_vector(3 downto 0); good : out boolean) is
begin
good := true;
case c is
when 'A' to 'F' => slv := std_logic_vector(to_unsigned(character'pos(c) - character'pos('A') + 10, 4)); return;
when 'a' to 'f' => slv := std_logic_vector(to_unsigned(character'pos(c) - character'pos('a') + 10, 4)); return;
when '0' to '9' => slv := std_logic_vector(to_unsigned(character'pos(c) - character'pos('0'), 4)); return;
when others => good := false; return;
end case;
end procedure;
signal init : boolean := false;
begin
process
begin
clk <= '1';
clk2x <= '1';
wait for 5 ns;
clk2x <= '0';
wait for 5 ns;
clk <= '0';
clk2x <= '1';
wait for 5 ns;
clk2x <= '0';
wait for 5 ns;
end process;
process(clk)
file memfile : text;
variable fname : string(1 to 63) := "/home/notti/uni/master/dis_vertiefung/se/project/src/fft_mp.mem";
variable buf_in, buf_out : line;
variable f_status : FILE_OPEN_STATUS;
variable good: boolean := true;
variable o: character;
variable i: integer := 1;
variable val: std_logic_vector(15 downto 0);
variable r: boolean := true;
variable ok:boolean := false;
variable ser_out : integer;
begin
if rising_edge(clk) then
if rst = '1' and init = false then
file_open(f_status, memfile, fname, read_mode);
readline(memfile, buf_in);
for j in 0 to 4 loop
read(buf_in, o, good);
assert good report "memfile error" severity failure;
end loop;
i := 0;
loop
read(buf_in, o, good);
exit when not good;
assert o = ' ' report "memfile error: " & o severity failure;
for j in 0 to 3 loop
read(buf_in, o, good);
assert good report "memfile error" severity failure;
hex2slv(o, val((j+1)*4-1 downto j*4), good);
assert good report "memfile error" severity failure;
end loop;
mem(i) <= val;
i := i + 1;
end loop;
assert false report "read " & integer'image(i) & " tokens" severity note;
init <= true;
i := 0;
elsif rst = '0' then
if ena = '1' then
doa <= mem(to_integer(unsigned(addra)));
end if;
if enb = '1' then
if addrb = X"FFFF" then
if web = "00" then
if i = 514 then
assert false report "stop" severity failure;
end if;
dob <= serial(i) & serial(i);
i := i + 1;
else
if web(0) = '1' then
ser_out := to_integer(signed(dib(7 downto 0)));
else
ser_out := to_integer(signed(dib(15 downto 8)));
end if;
if not ok then
if ser_out = 49 then
ok := true;
else
assert false report "no ok received!" severity failure;
end if;
else
if r then
write(buf_out, ser_out);
write(buf_out, ',');
write(buf_out, ' ');
r := false;
else
write(buf_out, ser_out);
writeline(output, buf_out);
r := true;
end if;
end if;
end if;
else
dob <= mem(to_integer(unsigned(addrb)));
if web(1) = '1' then
mem(to_integer(unsigned(addrb)))(15 downto 8) <= dib(15 downto 8);
end if;
if web(0) = '1' then
mem(to_integer(unsigned(addrb)))(7 downto 0) <= dib(7 downto 0);
end if;
end if;
end if;
end if;
end if;
end process;
process
begin
wait for 61 ns;
rst <= '0';
wait for 20 ns;
end process;
asoc: entity work.cpu
port map(
rst => rst,
clk => clk,
clk2x => clk2x,
ena => ena,
addra => addra,
doa => doa,
enb => enb,
addrb => addrb,
dob => dob,
web => web,
dib => dib,
bbusy => bbusy
);
end behav;
|
bsd-2-clause
|
notti/dis_se
|
testbench/tb_serial.vhd
|
1
|
1460
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library std;
use std.textio.all;
library work;
use work.all;
use work.procedures.all;
entity tb_serial is
end tb_serial;
architecture behav of tb_serial is
signal rst : std_logic := '1';
signal clk : std_logic := '0';
signal rx : std_logic := '1';
signal tx : std_logic := '1';
signal ena : std_logic := '0';
signal wea : std_logic := '0';
signal dia : std_logic_vector(7 downto 0) := (others => '0');
signal doa : std_logic_vector(7 downto 0) := (others => '0');
signal busy : std_logic := '0';
begin
process
begin
clk <= '1';
wait for 10 ns;
clk <= '0';
wait for 10 ns;
end process;
process
variable l : line;
begin
wait for 61 ns;
rst <= '0';
wait for 20 ns;
ena <= '1';
wea <= '1';
dia <= X"A1";
wait for 20 ns;
dia <= X"A2";
wait for 20 ns;
dia <= X"A3";
wait for 20 ns;
wea <= '0';
wait for 300 us;
assert false report "stop" severity failure;
end process;
aserial: entity work.serial
port map(
rst => rst,
clk => clk,
rx => rx,
tx => tx,
ena => ena,
wea => wea,
dia => dia,
doa => doa,
busy => busy
);
rx <= tx;
end behav;
|
bsd-2-clause
|
notti/dis_se
|
testbench/tb_mp_stage3.vhd
|
1
|
3860
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library std;
use std.textio.all;
library work;
use work.all;
use work.procedures.all;
entity tb_mp_stage3 is
end tb_mp_stage3;
architecture behav of tb_mp_stage3 is
signal clk : std_logic := '0';
signal rst : std_logic := '1';
signal cmd_in : t_vliw := empty_vliw;
signal arg_in : t_data_array(4 downto 0) := (others => (others => '0'));
signal val_in : t_data_array(4 downto 0) := (others => (others => '0'));
signal arg_out : t_data_array(4 downto 0) := (others => (others => '0'));
signal val_out : t_data_array(4 downto 0) := (others => (others => '0'));
signal cmd_out : t_vliw := empty_vliw;
type op_type is (op_noop, op_add, op_sub, op_sar, op_slr, op_and, op_or, op_xor);
type op_arr is array(natural range <>) of op_type;
signal op_lut : op_arr(7 downto 0) := (
0 => op_noop,
1 => op_add,
2 => op_sub,
3 => op_sar,
4 => op_slr,
5 => op_and,
6 => op_or,
7 => op_xor);
procedure prime_inputs(a0, a1, a2, a3, a4 : in integer;
in1a, in1b, out1, in2a, in2b, out2: in integer;
op1, op2 : in op_type;
signal args : out t_data_array(4 downto 0);
signal cmd : out t_vliw) is
begin
args(0) <= std_logic_vector(to_signed(a0, t_data'length));
args(1) <= std_logic_vector(to_signed(a1, t_data'length));
args(2) <= std_logic_vector(to_signed(a2, t_data'length));
args(3) <= std_logic_vector(to_signed(a3, t_data'length));
args(4) <= std_logic_vector(to_signed(a4, t_data'length));
for i in 7 downto 0 loop
if op1 = op_lut(i) then
cmd.s3_op1 <= std_logic_vector(to_unsigned(i, cmd.s3_op1'length));
end if;
if op2 = op_lut(i) then
cmd.s3_op2 <= std_logic_vector(to_unsigned(i, cmd.s3_op1'length));
end if;
end loop;
cmd.s3_in1a <= std_logic_vector(to_unsigned(in1a, cmd.s3_in1a'length));
cmd.s3_in1b <= std_logic_vector(to_unsigned(in1b, cmd.s3_in1b'length));
cmd.s3_out1 <= std_logic_vector(to_unsigned(out1, cmd.s3_out1'length));
cmd.s3_in2a <= std_logic_vector(to_unsigned(in2a, cmd.s3_in2a'length));
cmd.s3_in2b <= std_logic_vector(to_unsigned(in2b, cmd.s3_in2b'length));
cmd.s3_out2 <= std_logic_vector(to_unsigned(out2, cmd.s3_out2'length));
end procedure;
begin
clock: process
begin
clk <= '0', '1' after 10 ns;
wait for 20 ns;
end process clock;
process
variable l : line;
begin
wait for 10 ns;
wait for 60 ns;
rst <= '0';
prime_inputs(64, 10, 64, 0, 0,
0, 1, 0,
2, 3, 1,
op_add, op_add,
val_in, cmd_in);
wait for 20 ns;
prime_inputs(0, 45, 64, -64, 64,
4, 3, 0,
2, 1, 4,
op_add, op_add,
val_in, cmd_in);
wait for 20 ns;
prime_inputs(-15, 11, -45, 0, 0,
2, 0, 3,
2, 1, 4,
op_add, op_add,
val_in, cmd_in);
-- 74 64 64 0 0
-- 0 45 64 -64 109
-- -15 11 -45 -60 -34
wait for 80 ns;
assert false report "stop" severity failure;
end process;
mp_stage3_i: entity work.mp_stage3
port map(
rst => rst,
clk => clk,
cmd_in => cmd_in,
arg_in => arg_in,
val_in => val_in,
arg_out => arg_out,
val_out => val_out,
cmd_out => cmd_out
);
end behav;
|
bsd-2-clause
|
notti/dis_se
|
testbench/tb_simple_alu.vhd
|
1
|
2391
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library std;
use std.textio.all;
library work;
use work.all;
use work.procedures.all;
entity tb_simple_alu is
end tb_simple_alu;
architecture behav of tb_simple_alu is
signal clk : std_logic := '0';
signal a : t_data := (others => '0');
signal b : t_data := (others => '0');
signal op : std_logic_vector(2 downto 0) := (others => '0');
signal c : t_data := (others => '0');
type op_type is (op_noop, op_add, op_sub, op_sar, op_slr, op_and, op_or, op_xor);
type op_arr is array(natural range <>) of op_type;
signal current_op : op_type;
signal op_lut : op_arr(7 downto 0) := (
0 => op_noop,
1 => op_add,
2 => op_sub,
3 => op_sar,
4 => op_slr,
5 => op_and,
6 => op_or,
7 => op_xor);
begin
clock: process
begin
clk <= '0', '1' after 10 ns;
wait for 20 ns;
end process clock;
current_op <= op_lut(to_integer(unsigned(op)));
process
variable l : line;
begin
wait for 10 ns;
wait for 20 ns;
a <= X"00";
b <= X"00";
for i in 0 to 7 loop
op <= std_logic_vector(to_unsigned(i, op'length));
wait for 20 ns;
end loop;
wait for 20 ns;
a <= X"AA";
b <= X"55";
for i in 0 to 7 loop
op <= std_logic_vector(to_unsigned(i, op'length));
wait for 20 ns;
end loop;
wait for 20 ns;
a <= X"55";
b <= X"AA";
for i in 0 to 7 loop
op <= std_logic_vector(to_unsigned(i, op'length));
wait for 20 ns;
end loop;
wait for 20 ns;
a <= X"FF";
b <= X"FF";
for i in 0 to 7 loop
op <= std_logic_vector(to_unsigned(i, op'length));
wait for 20 ns;
end loop;
wait for 20 ns;
a <= X"01";
b <= X"01";
for i in 0 to 7 loop
op <= std_logic_vector(to_unsigned(i, op'length));
wait for 20 ns;
end loop;
wait for 20 ns;
assert false report "stop" severity failure;
end process;
simple_alu_1: entity work.simple_alu
port map(
clk => clk,
a => a,
b => b,
op => op,
c => c
);
end behav;
|
bsd-2-clause
|
szanni/aeshw
|
zybo-base/lib/Digilent/axi_dispctrl_1.0/hdl/axi_dispctrl_v1_0.vhd
|
7
|
18671
|
--------------------------------------------------------------------------------
--
-- File:
-- axi_dispctrl_v1_0.vhd
--
-- Module:
-- AXIS Display Controller
--
-- Author:
-- Tinghui Wang (Steve)
-- Sam Bobrowicz
--
-- Description:
-- Wrapper for AXI Display Controller
--
-- Additional Notes:
-- TODO - 1) Add Parameter to select whether to use a PLL or MMCM
-- 2) Add Parameter to use external pixel clock (no MMCM or PLL)
-- 3) Add Hot-plug detect and EDID control, selectable with parameter
-- 4) Add feature detect register, for determining enabled parameters from software
--
-- Copyright notice:
-- Copyright (C) 2014 Digilent Inc.
--
-- License:
-- This program is free software; distributed under the terms of
-- BSD 3-clause license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
-- IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
-- OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
-- OF THE POSSIBILITY OF SUCH DAMAGE.
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library UNISIM;
use UNISIM.VComponents.all;
entity axi_dispctrl_v1_0 is
generic (
-- Users to add parameters here
C_USE_BUFR_DIV5 : integer := 0;
C_RED_WIDTH : integer := 8;
C_GREEN_WIDTH : integer := 8;
C_BLUE_WIDTH : integer := 8;
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Parameters of Axi Slave Bus Interface S_AXI
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 6;
-- Parameters of Axi Slave Bus Interface S_AXIS_MM2S
C_S_AXIS_MM2S_TDATA_WIDTH : integer := 32
);
port (
-- Users to add ports here
-- Clock Signals
REF_CLK_I : in std_logic;
PXL_CLK_O : out std_logic;
PXL_CLK_5X_O : out std_logic;
LOCKED_O : out std_logic;
-- Display Signals
FSYNC_O : out std_logic;
HSYNC_O : out std_logic;
VSYNC_O : out std_logic;
DE_O : out std_logic;
RED_O : out std_logic_vector(C_RED_WIDTH-1 downto 0);
GREEN_O : out std_logic_vector(C_GREEN_WIDTH-1 downto 0);
BLUE_O : out std_logic_vector(C_BLUE_WIDTH-1 downto 0);
-- Debug Signals
DEBUG_O : out std_logic_vector(31 downto 0);
-- User ports ends
-- Do not modify the ports beyond this line
-- Ports of Axi Slave Bus Interface S_AXI
s_axi_aclk : in std_logic;
s_axi_aresetn : in std_logic;
s_axi_awaddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
s_axi_awprot : in std_logic_vector(2 downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
s_axi_wstrb : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_araddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
s_axi_arprot : in std_logic_vector(2 downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rdata : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
-- Ports of Axi Slave Bus Interface S_AXIS_MM2S
s_axis_mm2s_aclk : in std_logic;
s_axis_mm2s_aresetn : in std_logic;
s_axis_mm2s_tready : out std_logic;
s_axis_mm2s_tdata : in std_logic_vector(C_S_AXIS_MM2S_TDATA_WIDTH-1 downto 0);
s_axis_mm2s_tstrb : in std_logic_vector((C_S_AXIS_MM2S_TDATA_WIDTH/8)-1 downto 0);
s_axis_mm2s_tlast : in std_logic;
s_axis_mm2s_tvalid : in std_logic
);
end axi_dispctrl_v1_0;
architecture arch_imp of axi_dispctrl_v1_0 is
-- component declaration
component axi_dispctrl_v1_0_S_AXI is
generic (
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 6
);
port (
CTRL_REG :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
STAT_REG :in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
FRAME_REG :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
HPARAM1_REG :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
HPARAM2_REG :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
VPARAM1_REG :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
VPARAM2_REG :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
CLK_O_REG :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
CLK_FB_REG :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
CLK_FRAC_REG :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
CLK_DIV_REG :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
CLK_LOCK_REG :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
CLK_FLTR_REG :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic
);
end component axi_dispctrl_v1_0_S_AXI;
component mmcme2_drp
generic (
DIV_F : integer
);
port(
SEN : in std_logic;
SCLK : in std_logic;
RST : in std_logic;
S1_CLKOUT0 : in std_logic_vector(35 downto 0);
S1_CLKFBOUT : in std_logic_vector(35 downto 0);
S1_DIVCLK : in std_logic_vector(13 downto 0);
S1_LOCK : in std_logic_vector(39 downto 0);
S1_DIGITAL_FILT : in std_logic_vector(9 downto 0);
REF_CLK : in std_logic;
CLKFBOUT_I : in std_logic;
CLKFBOUT_O : out std_logic;
SRDY : out std_logic;
PXL_CLK : out std_logic;
LOCKED_O : out std_logic
);
end component;
component vdma_to_vga
generic (
C_RED_WIDTH : integer := 8;
C_GREEN_WIDTH : integer := 8;
C_BLUE_WIDTH : integer := 8;
C_S_AXIS_TDATA_WIDTH : integer := 32
);
port(
LOCKED_I : in std_logic;
ENABLE_I : in std_logic;
S_AXIS_ACLK : in std_logic;
S_AXIS_ARESETN : in std_logic;
S_AXIS_TREADY : out std_logic;
S_AXIS_TDATA : in std_logic_vector(C_S_AXIS_TDATA_WIDTH-1 downto 0);
S_AXIS_TSTRB : in std_logic_vector((C_S_AXIS_TDATA_WIDTH/8)-1 downto 0);
S_AXIS_TLAST : in std_logic;
S_AXIS_TVALID : in std_logic;
DEBUG_O : out std_logic_vector(31 downto 0);
USR_WIDTH_I : in std_logic_vector(11 downto 0);
USR_HEIGHT_I : in std_logic_vector(11 downto 0);
USR_HPS_I : in std_logic_vector(11 downto 0);
USR_HPE_I : in std_logic_vector(11 downto 0);
USR_HPOL_I : in std_logic;
USR_HMAX_I : in std_logic_vector(11 downto 0);
USR_VPS_I : in std_logic_vector(11 downto 0);
USR_VPE_I : in std_logic_vector(11 downto 0);
USR_VPOL_I : in std_logic;
USR_VMAX_I : in std_logic_vector(11 downto 0);
RUNNING_O : out std_logic;
FSYNC_O : out std_logic;
HSYNC_O : out std_logic;
VSYNC_O : out std_logic;
DE_O : out std_logic;
RED_O : out std_logic_vector(C_RED_WIDTH-1 downto 0);
GREEN_O : out std_logic_vector(C_GREEN_WIDTH-1 downto 0);
BLUE_O : out std_logic_vector(C_BLUE_WIDTH-1 downto 0)
);
end component;
signal CTRL_REG : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal STAT_REG : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal FRAME_REG : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal HPARAM1_REG : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal HPARAM2_REG : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal VPARAM1_REG : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal VPARAM2_REG : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal CLK_O_REG : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal CLK_FB_REG : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal CLK_FRAC_REG : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal CLK_DIV_REG : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal CLK_LOCK_REG : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal CLK_FLTR_REG : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
type CLK_STATE_TYPE is (RESET, WAIT_LOCKED, WAIT_EN, WAIT_SRDY, WAIT_RUN, ENABLED, WAIT_FRAME_DONE);
signal clk_state : CLK_STATE_TYPE := RESET;
signal srdy : std_logic;
signal enable_reg : std_logic := '0';
signal sen_reg : std_logic := '0';
signal pxl_clk : std_logic;
signal locked : std_logic;
signal locked_n : std_logic;
signal mmcm_fbclk_in : std_logic;
signal mmcm_fbclk_out : std_logic;
signal mmcm_clk : std_logic;
signal vga_running : std_logic;
begin
-- Instantiation of Axi Bus Interface S_AXI
axi_dispctrl_v1_0_S_AXI_inst : axi_dispctrl_v1_0_S_AXI
generic map (
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH
)
port map (
CTRL_REG => CTRL_REG,
STAT_REG => STAT_REG,
FRAME_REG => FRAME_REG,
HPARAM1_REG => HPARAM1_REG,
HPARAM2_REG => HPARAM2_REG,
VPARAM1_REG => VPARAM1_REG,
VPARAM2_REG => VPARAM2_REG,
CLK_O_REG => CLK_O_REG,
CLK_FB_REG => CLK_FB_REG,
CLK_FRAC_REG => CLK_FRAC_REG,
CLK_DIV_REG => CLK_DIV_REG,
CLK_LOCK_REG => CLK_LOCK_REG,
CLK_FLTR_REG => CLK_FLTR_REG,
S_AXI_ACLK => s_axi_aclk,
S_AXI_ARESETN => s_axi_aresetn,
S_AXI_AWADDR => s_axi_awaddr,
S_AXI_AWPROT => s_axi_awprot,
S_AXI_AWVALID => s_axi_awvalid,
S_AXI_AWREADY => s_axi_awready,
S_AXI_WDATA => s_axi_wdata,
S_AXI_WSTRB => s_axi_wstrb,
S_AXI_WVALID => s_axi_wvalid,
S_AXI_WREADY => s_axi_wready,
S_AXI_BRESP => s_axi_bresp,
S_AXI_BVALID => s_axi_bvalid,
S_AXI_BREADY => s_axi_bready,
S_AXI_ARADDR => s_axi_araddr,
S_AXI_ARPROT => s_axi_arprot,
S_AXI_ARVALID => s_axi_arvalid,
S_AXI_ARREADY => s_axi_arready,
S_AXI_RDATA => s_axi_rdata,
S_AXI_RRESP => s_axi_rresp,
S_AXI_RVALID => s_axi_rvalid,
S_AXI_RREADY => s_axi_rready
);
USE_BUFR_DIV5 : if C_USE_BUFR_DIV5 = 1 generate
BUFIO_inst : BUFIO
port map (
O => PXL_CLK_5X_O, -- 1-bit output: Clock output (connect to I/O clock loads).
I => mmcm_clk -- 1-bit input: Clock input (connect to an IBUF or BUFMR).
);
BUFR_inst : BUFR
generic map (
BUFR_DIVIDE => "5", -- Values: "BYPASS, 1, 2, 3, 4, 5, 6, 7, 8"
SIM_DEVICE => "7SERIES" -- Must be set to "7SERIES"
)
port map (
O => pxl_clk, -- 1-bit output: Clock output port
CE => '1', -- 1-bit input: Active high, clock enable (Divided modes only)
CLR => locked_n, -- 1-bit input: Active high, asynchronous clear (Divided modes only)
I => mmcm_clk -- 1-bit input: Clock buffer input driven by an IBUF, MMCM or local interconnect
);
locked_n <= not(locked);
Inst_mmcme2_drp: mmcme2_drp
GENERIC MAP(
DIV_F => 2
)
PORT MAP(
SEN => sen_reg,
SCLK => s_axi_aclk,
RST => not(s_axi_aresetn),
SRDY => srdy,
S1_CLKOUT0 => CLK_FRAC_REG(3 downto 0) & CLK_O_REG,
S1_CLKFBOUT => CLK_FRAC_REG(19 downto 16) & CLK_FB_REG,
S1_DIVCLK => CLK_DIV_REG(13 downto 0),
S1_LOCK => CLK_FLTR_REG(7 downto 0) & CLK_LOCK_REG,
S1_DIGITAL_FILT => CLK_FLTR_REG(25 downto 16),
REF_CLK => REF_CLK_I,
PXL_CLK => mmcm_clk,
CLKFBOUT_O => mmcm_fbclk_out,
CLKFBOUT_I => mmcm_fbclk_in,
LOCKED_O => locked
);
end generate;
DONT_USE_BUFR_DIV5 : if C_USE_BUFR_DIV5 /= 1 generate
PXL_CLK_5X_O <= '0';
BUFG_inst : BUFG
port map (
O => pxl_clk, -- 1-bit output: Clock output
I => mmcm_clk -- 1-bit input: Clock input
);
Inst_mmcme2_drp: mmcme2_drp
GENERIC MAP(
DIV_F => 10
)
PORT MAP(
SEN => sen_reg,
SCLK => s_axi_aclk,
RST => not(s_axi_aresetn),
SRDY => srdy,
S1_CLKOUT0 => CLK_FRAC_REG(3 downto 0) & CLK_O_REG,
S1_CLKFBOUT => CLK_FRAC_REG(19 downto 16) & CLK_FB_REG,
S1_DIVCLK => CLK_DIV_REG(13 downto 0),
S1_LOCK => CLK_FLTR_REG(7 downto 0) & CLK_LOCK_REG,
S1_DIGITAL_FILT => CLK_FLTR_REG(25 downto 16),
REF_CLK => REF_CLK_I,
PXL_CLK => mmcm_clk,
CLKFBOUT_O => mmcm_fbclk_out,
CLKFBOUT_I => mmcm_fbclk_in,
LOCKED_O => locked
);
end generate;
mmcm_fbclk_in <= mmcm_fbclk_out; --Don't bother compensating for any delay, because we don't need a phase relationship between
--REF_CLK and PXL_CLK
PXL_CLK_O <= pxl_clk;
LOCKED_O <= locked;
process (s_axi_aclk)
begin
if (rising_edge(s_axi_aclk)) then
if (s_axi_aresetn = '0') then
clk_state <= RESET;
else
case clk_state is
when RESET =>
clk_state <= WAIT_LOCKED;
when WAIT_LOCKED =>
-- This state ensures that the initial SRDY pulse
-- doesnt interfere with the WAIT_SRDY state
if (locked = '1') then
clk_state <= WAIT_EN;
end if;
when WAIT_EN =>
if (CTRL_REG(0) = '1') then
clk_state <= WAIT_SRDY;
end if;
when WAIT_SRDY =>
if (srdy = '1') then
clk_state <= WAIT_RUN;
end if;
when WAIT_RUN =>
if (STAT_REG(0) = '1') then
clk_state <= ENABLED;
end if;
when ENABLED =>
if (CTRL_REG(0) = '0') then
clk_state <= WAIT_FRAME_DONE;
end if;
when WAIT_FRAME_DONE =>
if (STAT_REG(0) = '0') then
clk_state <= WAIT_EN;
end if;
when others => --Never reached
clk_state <= RESET;
end case;
end if;
end if;
end process;
process (s_axi_aclk)
begin
if (rising_edge(s_axi_aclk)) then
if (s_axi_aresetn = '0') then
enable_reg <= '0';
sen_reg <= '0';
else
if (clk_state = WAIT_EN and CTRL_REG(0) = '1') then
sen_reg <= '1';
else
sen_reg <= '0';
end if;
if (clk_state = WAIT_RUN or clk_state = ENABLED) then
enable_reg <= '1';
else
enable_reg <= '0';
end if;
end if;
end if;
end process;
Inst_vdma_to_vga: vdma_to_vga
generic map (
C_RED_WIDTH => C_RED_WIDTH,
C_GREEN_WIDTH => C_GREEN_WIDTH,
C_BLUE_WIDTH => C_BLUE_WIDTH,
C_S_AXIS_TDATA_WIDTH => C_S_AXIS_MM2S_TDATA_WIDTH
)
PORT MAP(
LOCKED_I => locked,
ENABLE_I => enable_reg,
RUNNING_O => vga_running,
S_AXIS_ACLK => s_axis_mm2s_aclk,
S_AXIS_ARESETN => s_axis_mm2s_aresetn,
S_AXIS_TREADY => s_axis_mm2s_tready,
S_AXIS_TDATA => s_axis_mm2s_tdata,
S_AXIS_TSTRB => s_axis_mm2s_tstrb,
S_AXIS_TLAST => s_axis_mm2s_tlast,
S_AXIS_TVALID => s_axis_mm2s_tvalid,
FSYNC_O => FSYNC_O,
HSYNC_O => HSYNC_O,
VSYNC_O => VSYNC_O,
DEBUG_O => DEBUG_O,
DE_O => DE_O,
RED_O => RED_O,
GREEN_O => GREEN_O,
BLUE_O => BLUE_O,
USR_WIDTH_I => FRAME_REG(27 downto 16),
USR_HEIGHT_I => FRAME_REG(11 downto 0),
USR_HPS_I => HPARAM1_REG(27 downto 16),
USR_HPE_I => HPARAM1_REG(11 downto 0),
USR_HPOL_I => HPARAM2_REG(16),
USR_HMAX_I => HPARAM2_REG(11 downto 0),
USR_VPS_I => VPARAM1_REG(27 downto 16),
USR_VPE_I => VPARAM1_REG(11 downto 0),
USR_VPOL_I => VPARAM2_REG(16),
USR_VMAX_I => VPARAM2_REG(11 downto 0)
);
STAT_REG(C_S_AXI_DATA_WIDTH-1 downto 1) <= (others => '0');
process (s_axi_aclk)
begin
if (rising_edge(s_axi_aclk)) then
if (s_axi_aresetn = '0') then
STAT_REG(0) <= '0';
else
STAT_REG(0) <= vga_running;
end if;
end if;
end process;
-- User logic ends
end arch_imp;
|
bsd-2-clause
|
szanni/aeshw
|
zybo-base/zybo_bsd/zybo_bsd.srcs/sources_1/bd/system/ip/system_auto_pc_5/fifo_generator_v11_0/ramfifo/wr_logic_pkt_fifo.vhd
|
19
|
31831
|
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`protect end_protected
|
bsd-2-clause
|
codepainters/vhdl-utils
|
tests/t_hd44780_iface.vhd
|
1
|
7315
|
--------------------------------------------------------------------------------
-- Copyright (c) 2015, Przemyslaw Wegrzyn <[email protected]>
-- This file is distributed under the Modified BSD License.
--
-- Testbench for teh HD44780 LCD interface.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity t_hd44780_iface is
end t_hd44780_iface;
architecture behavior of t_hd44780_iface is
component hd44780_iface
generic (time_base_period : integer);
port(clk : in std_logic;
time_base : in std_logic;
db : in std_logic_vector(7 downto 0);
rs : in std_logic;
strb : in std_logic;
rdy : out std_logic;
lcd_e : out std_logic;
lcd_rs : out std_logic;
lcd_rw : out std_logic;
lcd_d : out std_logic_vector(7 downto 4)
);
end component;
signal clk : std_logic := '0';
signal time_base : std_logic := '0';
signal db : std_logic_vector(7 downto 0) := (others => '0');
signal rs : std_logic := '0';
signal strb : std_logic := '0';
signal ready : std_logic;
signal lcd_e : std_logic;
signal lcd_rs : std_logic;
signal lcd_rw : std_logic;
signal lcd_d : std_logic_vector(7 downto 4);
-- 50MHz main clock, 1kHz time base
constant clk_period : time := 20 ns;
constant time_base_ratio : integer := 5_000;
constant time_base_period : integer := 100; -- microseconds
-- E pulse timing paramters, from the Hitachi HD44780U datahseet,
-- worst case (VCC 2.7..4.5V)
constant min_power_up_delay : time := 40 ms;
constant min_addr_setup_time : time := 60 ns;
constant min_addr_hold_time : time := 20 ns;
constant min_data_setup_time : time := 195 ns;
constant min_data_hold_time : time := 10 ns;
constant min_e_pulse_width : time := 450 ns;
-- minimum time between E rising edges
constant min_e_cycle_time : time := 1000 ns;
-- datasheet says 37us (+ 4us for RAM access), let's add some margin
constant normal_cmd_delay : time := 50 us;
-- can't find it stated explicitely anywhere - assuming same
-- as command delay (probably much longer than needed)
constant high_nibble_delay : time := normal_cmd_delay;
-- Clear Display and Return Home need more time (1.6 ms + margin)
constant long_cmd_delay : time := 2 ms;
-- init sequence
type t_init_sequence_entry is record
data : std_logic_vector(7 downto 4);
delay : time;
end record;
type t_init_sequence is array (0 to 3) of t_init_sequence_entry;
signal init_sequence : t_init_sequence := (
(X"3", 4.1 ms),
(X"3", 100 us),
(X"3", 100 us),
(X"2", 100 us));
-- user commands
type t_user_command is record
rs : std_logic;
data: std_logic_vector(7 downto 0);
end record;
type t_user_commands is array (0 to 3) of t_user_command;
signal user_commands : t_user_commands := (
('0', X"01"), -- Display Clear command
('0', X"02"), -- Return Home command
('1', X"41"),
('1', X"5A"));
begin
-- TODO: check ready signal handling
uut: hd44780_iface
generic map (time_base_period => time_base_period)
port map (
clk => clk,
time_base => time_base,
db => db,
rs => rs,
strb => strb,
rdy => ready,
lcd_e => lcd_e,
lcd_rs => lcd_rs,
lcd_rw => lcd_rw,
lcd_d => lcd_d);
-- Clock process definitions
clk_process : process
variable i : integer;
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
time_base_process : process
begin
time_base <= '0';
wait for clk_period * (time_base_ratio - 1);
time_base <= '1';
wait for clk_period;
end process;
user_process : process
variable minimum_delay: time;
begin
-- note: we can't progress on the same edge when ready goes '1'
wait until ready = '1' and falling_edge(clk);
for i in user_commands'low to user_commands'high loop
rs <= user_commands(i).rs;
db <= user_commands(i).data;
strb <= '1';
wait for clk_period;
strb <= '0';
-- after one clk period 'ready' should be low
assert ready = '0' report "ready not low after submitting a byte" severity error;
wait until ready = '1';
-- ensure enough time was given for the command to execute
if user_commands(i).data = B"00000001" or user_commands(i).data(7 downto 1) = B"0000001" then
-- Clear Display or Return Home
minimum_delay := long_cmd_delay;
else
minimum_delay := normal_cmd_delay;
end if;
assert lcd_e = '0' and lcd_e'last_event > minimum_delay
report "command execution time not respected" severity error;
wait until falling_edge(clk);
end loop;
-- TODO: stop clocks to terminate simulation
wait until False;
end process;
t_lcd_timing : process
variable e_prev : time;
variable e_start : time := 0 ns;
begin
-- wait for E raising edge
wait until lcd_e = '1';
e_prev := e_start;
e_start := now;
assert e_start > min_power_up_delay report "initial power-up delay time violated" severity error;
-- check minimum cycle time
if e_prev /= 0 ns then
assert e_start - e_prev > min_e_cycle_time report "lcd_e minimum cycle time violated" severity error;
end if;
-- check setup time
assert lcd_rs'stable(min_addr_setup_time) report "lcd_rs setup time violated" severity error;
assert lcd_d'stable(min_data_setup_time) report "lcd_d setup time violated" severity error;
-- wait for E falling edge, check pulse width
wait until lcd_e = '0';
assert now - e_start > min_e_pulse_width report "lcd_e minimum pulse width violated" severity error;
-- check hold time
assert lcd_rs'stable(min_addr_hold_time) report "lcd_rs hold time violated" severity error;
assert lcd_d'stable(min_data_hold_time) report "lcd_d hold time violated" severity error;
end process;
t_lcd_init : process
variable cmd_start : time;
begin
wait until lcd_e = '1';
assert now > min_power_up_delay report "initial power-up delay time violated" severity error;
for i in init_sequence'low to init_sequence'high loop
wait until lcd_e = '0';
cmd_start := now;
assert lcd_d = init_sequence(i).data report "invalid init sequence" severity error;
-- check enough time is given for each command to execute
wait until lcd_e = '1';
assert now - cmd_start >= init_sequence(i).delay report "init sequence delay violation" severity error;
end loop;
-- when we get here, lcd_e is '1' - first user command was just submitted (high nibble)
wait until False;
end process;
end;
|
bsd-2-clause
|
armandas/Plong
|
bar.vhd
|
2
|
2693
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity bar_rom is
port(
clk: in std_logic;
addr: in std_logic_vector(5 downto 0);
data: out std_logic_vector(0 to 19)
);
end bar_rom;
architecture content of bar_rom is
type rom_type is array(0 to 63) of std_logic_vector(19 downto 0);
constant BAR: rom_type :=
(
"11111101111111110111",
"11010100000000010001",
"10110010101010101101",
"10011000100010000101",
"10101000000000010011",
"10101100000000000101",
"10101100001000000101",
"10100110001000000101",
"10101110000101001011",
"10100011010001010101",
"10100101010000100101",
"10100100101010100101",
"10001001010100000101",
"10100010001100000101",
"10101000010110100011",
"01001010010010010001",
"10100000101110100111",
"10100000000101010001",
"10100000010010100111",
"10100000000101100001",
"10000010101011000111",
"11100000001011000001",
"10000010010110000111",
"10100010001010000001",
"10100001010100100111",
"10100001010100100001",
"10101010111000000111",
"10100101101000010001",
"10110111000000100111",
"11011110000000100001",
"10110000100001001011",
"10101100000001000101",
"10001100000000010111",
"11101100000000000001",
"10111000000000101011",
"11011000000100000001",
"10110000001000000111",
"11111000000010000001",
"10010000000100000101",
"11011000010001000101",
"10101000100010010011",
"11011100000000000101",
"10101100001000000101",
"10100110001000000101",
"10101110000101001011",
"10100011010001010101",
"10100101010000100101",
"10100100101010100101",
"10001001010100000101",
"10100010001100000101",
"10101000010110100011",
"01001010010010010001",
"10100000101110100111",
"10100000000101010001",
"10100000010010100111",
"10100000000101100001",
"10000010101011000111",
"11100000001011000001",
"10000010010110000111",
"10100010001010000001",
"10100001010100100111",
"11010101011101010101",
"10101101111010101111",
"11111111111111111111"
);
signal addr_reg: std_logic_vector(5 downto 0);
begin
process(clk)
begin
if clk'event and clk = '1' then
addr_reg <= addr;
end if;
end process;
data <= BAR(conv_integer(addr_reg));
end content;
|
bsd-2-clause
|
armandas/Arcade
|
bar.vhd
|
2
|
2693
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity bar_rom is
port(
clk: in std_logic;
addr: in std_logic_vector(5 downto 0);
data: out std_logic_vector(0 to 19)
);
end bar_rom;
architecture content of bar_rom is
type rom_type is array(0 to 63) of std_logic_vector(19 downto 0);
constant BAR: rom_type :=
(
"11111101111111110111",
"11010100000000010001",
"10110010101010101101",
"10011000100010000101",
"10101000000000010011",
"10101100000000000101",
"10101100001000000101",
"10100110001000000101",
"10101110000101001011",
"10100011010001010101",
"10100101010000100101",
"10100100101010100101",
"10001001010100000101",
"10100010001100000101",
"10101000010110100011",
"01001010010010010001",
"10100000101110100111",
"10100000000101010001",
"10100000010010100111",
"10100000000101100001",
"10000010101011000111",
"11100000001011000001",
"10000010010110000111",
"10100010001010000001",
"10100001010100100111",
"10100001010100100001",
"10101010111000000111",
"10100101101000010001",
"10110111000000100111",
"11011110000000100001",
"10110000100001001011",
"10101100000001000101",
"10001100000000010111",
"11101100000000000001",
"10111000000000101011",
"11011000000100000001",
"10110000001000000111",
"11111000000010000001",
"10010000000100000101",
"11011000010001000101",
"10101000100010010011",
"11011100000000000101",
"10101100001000000101",
"10100110001000000101",
"10101110000101001011",
"10100011010001010101",
"10100101010000100101",
"10100100101010100101",
"10001001010100000101",
"10100010001100000101",
"10101000010110100011",
"01001010010010010001",
"10100000101110100111",
"10100000000101010001",
"10100000010010100111",
"10100000000101100001",
"10000010101011000111",
"11100000001011000001",
"10000010010110000111",
"10100010001010000001",
"10100001010100100111",
"11010101011101010101",
"10101101111010101111",
"11111111111111111111"
);
signal addr_reg: std_logic_vector(5 downto 0);
begin
process(clk)
begin
if clk'event and clk = '1' then
addr_reg <= addr;
end if;
end process;
data <= BAR(conv_integer(addr_reg));
end content;
|
bsd-2-clause
|
rohit91/HDMI2USB
|
ipcore_dir/ddr2ram/example_design/rtl/iodrp_controller.vhd
|
19
|
14635
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: iodrp_controller.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:17:25 $
-- \ \ / \ Date Created: Mon Feb 9 2009
-- \___\/\___\
--
--Device: Spartan6
--Design Name: DDR/DDR2/DDR3/LPDDR
--Purpose: Xilinx reference design for IODRP controller for v0.9 device
--
--Reference:
--
-- Revision: Date: Comment
-- 1.0: 02/06/09: Initial version for MIG wrapper.
-- 1.1: 02/01/09: updates to indentations.
-- 1.2: 02/12/09: changed non-blocking assignments to blocking ones
-- for state machine always block. Also, assigned
-- intial value to load_shift_n to avoid latch
-- End Revision
--*******************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity iodrp_controller is
--output to IODRP SDI pin
--input from IODRP SDO pin
-- Register where memcell_address is captured during the READY state
-- Register which stores the write data until it is ready to be shifted out
-- The shift register which shifts out SDO and shifts in SDI.
-- This register is loaded before the address or data phase, but continues
-- to shift for a writeback of read data
-- The signal which causes shift_through_reg to load the new value from data_out_mux, or continue to shift data in from DRP_SDO
-- The signal which indicates where the shift_through_reg should load from. 0 -> data_reg 1 -> memcell_addr_reg
-- The counter for which bit is being shifted during address or data phase
-- This is set after the first address phase has executed
-- (* FSM_ENCODING="GRAY" *) reg [2:0] state, nextstate;
-- The mux which selects between data_reg and memcell_addr_reg for sending to shift_through_reg
-- added so that DRP_SDI output is only active when DRP_CS is active
port (
memcell_address : in std_logic_vector(7 downto 0);
write_data : in std_logic_vector(7 downto 0);
read_data : out std_logic_vector(7 downto 0);
rd_not_write : in std_logic;
cmd_valid : in std_logic;
rdy_busy_n : out std_logic;
use_broadcast : in std_logic;
sync_rst : in std_logic;
DRP_CLK : in std_logic;
DRP_CS : out std_logic;
DRP_SDI : out std_logic;
DRP_ADD : out std_logic;
DRP_BKST : out std_logic;
DRP_SDO : in std_logic
);
end entity iodrp_controller;
architecture trans of iodrp_controller is
constant READY : std_logic_vector(2 downto 0) := "000";
constant DECIDE : std_logic_vector(2 downto 0) := "001";
constant ADDR_PHASE : std_logic_vector(2 downto 0) := "010";
constant ADDR_TO_DATA_GAP : std_logic_vector(2 downto 0) := "011";
constant ADDR_TO_DATA_GAP2 : std_logic_vector(2 downto 0) := "100";
constant ADDR_TO_DATA_GAP3 : std_logic_vector(2 downto 0) := "101";
constant DATA_PHASE : std_logic_vector(2 downto 0) := "110";
constant ALMOST_READY : std_logic_vector(2 downto 0) := "111";
constant IOI_DQ0 : std_logic_vector(4 downto 0) := "00001";
constant IOI_DQ1 : std_logic_vector(4 downto 0) := "00000";
constant IOI_DQ2 : std_logic_vector(4 downto 0) := "00011";
constant IOI_DQ3 : std_logic_vector(4 downto 0) := "00010";
constant IOI_DQ4 : std_logic_vector(4 downto 0) := "00101";
constant IOI_DQ5 : std_logic_vector(4 downto 0) := "00100";
constant IOI_DQ6 : std_logic_vector(4 downto 0) := "00111";
constant IOI_DQ7 : std_logic_vector(4 downto 0) := "00110";
constant IOI_DQ8 : std_logic_vector(4 downto 0) := "01001";
constant IOI_DQ9 : std_logic_vector(4 downto 0) := "01000";
constant IOI_DQ10 : std_logic_vector(4 downto 0) := "01011";
constant IOI_DQ11 : std_logic_vector(4 downto 0) := "01010";
constant IOI_DQ12 : std_logic_vector(4 downto 0) := "01101";
constant IOI_DQ13 : std_logic_vector(4 downto 0) := "01100";
constant IOI_DQ14 : std_logic_vector(4 downto 0) := "01111";
constant IOI_DQ15 : std_logic_vector(4 downto 0) := "01110";
constant IOI_UDQS_CLK : std_logic_vector(4 downto 0) := "11101";
constant IOI_UDQS_PIN : std_logic_vector(4 downto 0) := "11100";
constant IOI_LDQS_CLK : std_logic_vector(4 downto 0) := "11111";
constant IOI_LDQS_PIN : std_logic_vector(4 downto 0) := "11110";
signal memcell_addr_reg : std_logic_vector(7 downto 0);
signal data_reg : std_logic_vector(7 downto 0);
signal shift_through_reg : std_logic_vector(7 downto 0);
signal load_shift_n : std_logic;
signal addr_data_sel_n : std_logic;
signal bit_cnt : std_logic_vector(2 downto 0);
signal rd_not_write_reg : std_logic;
signal AddressPhase : std_logic;
signal capture_read_data : std_logic;
signal state : std_logic_vector(2 downto 0);
signal nextstate : std_logic_vector(2 downto 0);
signal data_out_mux : std_logic_vector(7 downto 0);
signal DRP_SDI_pre : std_logic;
signal ALMOST_READY_ST : std_logic;
signal ADDR_PHASE_ST : std_logic;
signal BIT_CNT7 : std_logic;
signal ADDR_PHASE_ST1 : std_logic;
signal DATA_PHASE_ST : std_logic;
signal state_ascii : std_logic_vector(32 * 8 - 1 downto 0);
begin
--synthesis translate_off
-- process (state)
-- begin
-- case state is
-- when READY =>
-- state_ascii <= "READY";
-- when DECIDE =>
-- state_ascii <= "DECIDE";
-- when ADDR_PHASE =>
-- state_ascii <= "ADDR_PHASE";
-- when ADDR_TO_DATA_GAP =>
-- state_ascii <= "ADDR_TO_DATA_GAP";
-- when ADDR_TO_DATA_GAP2 =>
-- state_ascii <= "ADDR_TO_DATA_GAP2";
-- when ADDR_TO_DATA_GAP3 =>
-- state_ascii <= "ADDR_TO_DATA_GAP3";
-- when DATA_PHASE =>
-- state_ascii <= "DATA_PHASE";
-- when ALMOST_READY => -- case(state)
-- state_ascii <= "ALMOST_READY";
-- when others =>
-- null;
-- end case;
-- end process;
--synthesis translate_on
process (DRP_CLK)
begin
if (DRP_CLK'event and DRP_CLK = '1') then
if (state = READY) then
memcell_addr_reg <= memcell_address;
data_reg <= write_data;
rd_not_write_reg <= rd_not_write;
end if;
end if;
end process;
rdy_busy_n <= '1' when (state = READY) else '0';
data_out_mux <= memcell_addr_reg when (addr_data_sel_n = '1') else
data_reg;
process (DRP_CLK)
begin
if (DRP_CLK'event and DRP_CLK = '1') then
if (sync_rst = '1') then
shift_through_reg <= "00000000";
else
if (load_shift_n = '1') then --Assume the shifter is either loading or shifting, bit 0 is shifted out first
shift_through_reg <= data_out_mux;
else
shift_through_reg <= (DRP_SDO & shift_through_reg(7 downto 1));
end if;
end if;
end if;
end process;
process (DRP_CLK)
begin
if (DRP_CLK'event and DRP_CLK = '1') then
if (((state = ADDR_PHASE) or (state = DATA_PHASE)) and (not(sync_rst)) = '1') then
bit_cnt <= bit_cnt + "001";
else
bit_cnt <= "000";
end if;
end if;
end process;
process (DRP_CLK)
begin
if (DRP_CLK'event and DRP_CLK = '1') then
if (sync_rst = '1') then
-- capture_read_data <= 1'b0;
read_data <= "00000000";
else
-- capture_read_data <= (state == DATA_PHASE);
-- if(capture_read_data)
if (state = ALMOST_READY) then
-- else
-- read_data <= read_data;
read_data <= shift_through_reg;
end if;
end if;
end if;
end process;
ALMOST_READY_ST <= '1' when state = ALMOST_READY else '0';
ADDR_PHASE_ST <= '1' when state = ADDR_PHASE else '0';
BIT_CNT7 <= '1' when bit_cnt = "111" else '0';
process (DRP_CLK)
begin
if (DRP_CLK'event and DRP_CLK = '1') then
if (sync_rst = '1') then
AddressPhase <= '0';
else
if (AddressPhase = '1') then
-- Keep it set until we finish the cycle
AddressPhase <= AddressPhase and (not ALMOST_READY_ST);
else
-- set the address phase when ever we finish the address phase
AddressPhase <= (ADDR_PHASE_ST and BIT_CNT7);
end if;
end if;
end if;
end process;
ADDR_PHASE_ST1 <= '1' when nextstate = ADDR_PHASE else '0';
DATA_PHASE_ST <= '1' when nextstate = DATA_PHASE else '0';
process (DRP_CLK)
begin
if (DRP_CLK'event and DRP_CLK = '1') then
DRP_ADD <= ADDR_PHASE_ST1;
DRP_CS <= ADDR_PHASE_ST1 or DATA_PHASE_ST;
if (state = READY) then
DRP_BKST <= use_broadcast;
end if;
end if;
end process;
-- assign DRP_SDI_pre = (DRP_CS)? shift_through_reg[0] : 1'b0; //if DRP_CS is inactive, just drive 0 out - this is a possible place to pipeline for increased performance
-- assign DRP_SDI = (rd_not_write_reg & DRP_CS & !DRP_ADD)? DRP_SDO : DRP_SDI_pre; //If reading, then feed SDI back out SDO - this is a possible place to pipeline for increased performance
DRP_SDI <= shift_through_reg(0); -- The new read method only requires that we shift out the address and the write data
process (state, cmd_valid, bit_cnt, rd_not_write_reg, AddressPhase,BIT_CNT7)
begin
addr_data_sel_n <= '0';
load_shift_n <= '0';
case state is
when READY =>
if (cmd_valid = '1') then
nextstate <= DECIDE;
else
nextstate <= READY;
end if;
when DECIDE =>
load_shift_n <= '1';
addr_data_sel_n <= '1';
nextstate <= ADDR_PHASE;
-- After the second pass go to end of statemachine
-- execute a second address phase for the read access.
when ADDR_PHASE =>
if (BIT_CNT7 = '1') then
if (rd_not_write_reg = '1') then
if (AddressPhase = '1') then
nextstate <= ALMOST_READY;
else
nextstate <= DECIDE;
end if;
else
nextstate <= ADDR_TO_DATA_GAP;
end if;
else
nextstate <= ADDR_PHASE;
end if;
when ADDR_TO_DATA_GAP =>
load_shift_n <= '1';
nextstate <= ADDR_TO_DATA_GAP2;
when ADDR_TO_DATA_GAP2 =>
load_shift_n <= '1';
nextstate <= ADDR_TO_DATA_GAP3;
when ADDR_TO_DATA_GAP3 =>
load_shift_n <= '1';
nextstate <= DATA_PHASE;
when DATA_PHASE =>
if (BIT_CNT7 = '1') then
nextstate <= ALMOST_READY;
else
nextstate <= DATA_PHASE;
end if;
when ALMOST_READY =>
nextstate <= READY;
when others =>
nextstate <= READY;
end case;
end process;
process (DRP_CLK)
begin
if (DRP_CLK'event and DRP_CLK = '1') then
if (sync_rst = '1') then
state <= READY;
else
state <= nextstate;
end if;
end if;
end process;
end architecture trans;
|
bsd-2-clause
|
rohit91/HDMI2USB
|
ipcore_dir/ddr2ram/user_design/rtl/ddr2ram.vhd
|
3
|
32669
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.92
-- \ \ Application : MIG
-- / / Filename : ddr2ram.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:56 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
--Device : Spartan-6
--Design Name : DDR/DDR2/DDR3/LPDDR
--Purpose : This is the design top level. which instantiates top wrapper,
-- test bench top and infrastructure modules.
--Reference :
--Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
entity ddr2ram is
generic
(
C3_P0_MASK_SIZE : integer := 4;
C3_P0_DATA_PORT_SIZE : integer := 32;
C3_P1_MASK_SIZE : integer := 4;
C3_P1_DATA_PORT_SIZE : integer := 32;
C3_MEMCLK_PERIOD : integer := 3200;
-- Memory data transfer clock period.
C3_RST_ACT_LOW : integer := 0;
-- # = 1 for active low reset,
-- # = 0 for active high reset.
C3_INPUT_CLK_TYPE : string := "SINGLE_ENDED";
-- input clock type DIFFERENTIAL or SINGLE_ENDED.
C3_CALIB_SOFT_IP : string := "TRUE";
-- # = TRUE, Enables the soft calibration logic,
-- # = FALSE, Disables the soft calibration logic.
C3_SIMULATION : string := "FALSE";
-- # = TRUE, Simulating the design. Useful to reduce the simulation time,
-- # = FALSE, Implementing the design.
DEBUG_EN : integer := 0;
-- # = 1, Enable debug signals/controls,
-- = 0, Disable debug signals/controls.
C3_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN";
-- The order in which user address is provided to the memory controller,
-- ROW_BANK_COLUMN or BANK_ROW_COLUMN.
C3_NUM_DQ_PINS : integer := 16;
-- External memory data width.
C3_MEM_ADDR_WIDTH : integer := 13;
-- External memory address width.
C3_MEM_BANKADDR_WIDTH : integer := 3
-- External memory bank address width.
);
port
(
mcb3_dram_dq : inout std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
mcb3_dram_a : out std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
mcb3_dram_ba : out std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_odt : out std_logic;
mcb3_dram_cke : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_rzq : inout std_logic;
mcb3_zio : inout std_logic;
mcb3_dram_udm : out std_logic;
c3_sys_clk : in std_logic;
c3_sys_rst_i : in std_logic;
c3_calib_done : out std_logic;
c3_clk0 : out std_logic;
c3_rst0 : out std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
clk_img : out std_logic;
c3_p2_cmd_clk : in std_logic;
c3_p2_cmd_en : in std_logic;
c3_p2_cmd_instr : in std_logic_vector(2 downto 0);
c3_p2_cmd_bl : in std_logic_vector(5 downto 0);
c3_p2_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p2_cmd_empty : out std_logic;
c3_p2_cmd_full : out std_logic;
c3_p2_rd_clk : in std_logic;
c3_p2_rd_en : in std_logic;
c3_p2_rd_data : out std_logic_vector(31 downto 0);
c3_p2_rd_full : out std_logic;
c3_p2_rd_empty : out std_logic;
c3_p2_rd_count : out std_logic_vector(6 downto 0);
c3_p2_rd_overflow : out std_logic;
c3_p2_rd_error : out std_logic;
c3_p3_cmd_clk : in std_logic;
c3_p3_cmd_en : in std_logic;
c3_p3_cmd_instr : in std_logic_vector(2 downto 0);
c3_p3_cmd_bl : in std_logic_vector(5 downto 0);
c3_p3_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p3_cmd_empty : out std_logic;
c3_p3_cmd_full : out std_logic;
c3_p3_wr_clk : in std_logic;
c3_p3_wr_en : in std_logic;
c3_p3_wr_mask : in std_logic_vector(3 downto 0);
c3_p3_wr_data : in std_logic_vector(31 downto 0);
c3_p3_wr_full : out std_logic;
c3_p3_wr_empty : out std_logic;
c3_p3_wr_count : out std_logic_vector(6 downto 0);
c3_p3_wr_underrun : out std_logic;
c3_p3_wr_error : out std_logic
);
end ddr2ram;
architecture arc of ddr2ram is
component memc3_infrastructure is
generic (
C_RST_ACT_LOW : integer;
C_INPUT_CLK_TYPE : string;
C_CLKOUT0_DIVIDE : integer;
C_CLKOUT1_DIVIDE : integer;
C_CLKOUT2_DIVIDE : integer;
C_CLKOUT3_DIVIDE : integer;
C_CLKOUT4_DIVIDE : integer;
C_CLKFBOUT_MULT : integer;
C_DIVCLK_DIVIDE : integer;
C_INCLK_PERIOD : integer
);
port (
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
sys_clk : in std_logic;
sys_rst_i : in std_logic;
clk0 : out std_logic;
clk_img : out std_logic;
rst0 : out std_logic;
async_rst : out std_logic;
sysclk_2x : out std_logic;
sysclk_2x_180 : out std_logic;
pll_ce_0 : out std_logic;
pll_ce_90 : out std_logic;
pll_lock : out std_logic;
mcb_drp_clk : out std_logic
);
end component;
component memc3_wrapper is
generic (
C_MEMCLK_PERIOD : integer;
C_CALIB_SOFT_IP : string;
C_SIMULATION : string;
C_P0_MASK_SIZE : integer;
C_P0_DATA_PORT_SIZE : integer;
C_P1_MASK_SIZE : integer;
C_P1_DATA_PORT_SIZE : integer;
C_ARB_NUM_TIME_SLOTS : integer;
C_ARB_TIME_SLOT_0 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_1 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_2 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_3 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_4 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_5 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_6 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_7 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_8 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_9 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_10 : bit_vector(5 downto 0);
C_ARB_TIME_SLOT_11 : bit_vector(5 downto 0);
C_MEM_TRAS : integer;
C_MEM_TRCD : integer;
C_MEM_TREFI : integer;
C_MEM_TRFC : integer;
C_MEM_TRP : integer;
C_MEM_TWR : integer;
C_MEM_TRTP : integer;
C_MEM_TWTR : integer;
C_MEM_ADDR_ORDER : string;
C_NUM_DQ_PINS : integer;
C_MEM_TYPE : string;
C_MEM_DENSITY : string;
C_MEM_BURST_LEN : integer;
C_MEM_CAS_LATENCY : integer;
C_MEM_ADDR_WIDTH : integer;
C_MEM_BANKADDR_WIDTH : integer;
C_MEM_NUM_COL_BITS : integer;
C_MEM_DDR1_2_ODS : string;
C_MEM_DDR2_RTT : string;
C_MEM_DDR2_DIFF_DQS_EN : string;
C_MEM_DDR2_3_PA_SR : string;
C_MEM_DDR2_3_HIGH_TEMP_SR : string;
C_MEM_DDR3_CAS_LATENCY : integer;
C_MEM_DDR3_ODS : string;
C_MEM_DDR3_RTT : string;
C_MEM_DDR3_CAS_WR_LATENCY : integer;
C_MEM_DDR3_AUTO_SR : string;
C_MEM_DDR3_DYN_WRT_ODT : string;
C_MEM_MOBILE_PA_SR : string;
C_MEM_MDDR_ODS : string;
C_MC_CALIB_BYPASS : string;
C_MC_CALIBRATION_MODE : string;
C_MC_CALIBRATION_DELAY : string;
C_SKIP_IN_TERM_CAL : integer;
C_SKIP_DYNAMIC_CAL : integer;
C_LDQSP_TAP_DELAY_VAL : integer;
C_LDQSN_TAP_DELAY_VAL : integer;
C_UDQSP_TAP_DELAY_VAL : integer;
C_UDQSN_TAP_DELAY_VAL : integer;
C_DQ0_TAP_DELAY_VAL : integer;
C_DQ1_TAP_DELAY_VAL : integer;
C_DQ2_TAP_DELAY_VAL : integer;
C_DQ3_TAP_DELAY_VAL : integer;
C_DQ4_TAP_DELAY_VAL : integer;
C_DQ5_TAP_DELAY_VAL : integer;
C_DQ6_TAP_DELAY_VAL : integer;
C_DQ7_TAP_DELAY_VAL : integer;
C_DQ8_TAP_DELAY_VAL : integer;
C_DQ9_TAP_DELAY_VAL : integer;
C_DQ10_TAP_DELAY_VAL : integer;
C_DQ11_TAP_DELAY_VAL : integer;
C_DQ12_TAP_DELAY_VAL : integer;
C_DQ13_TAP_DELAY_VAL : integer;
C_DQ14_TAP_DELAY_VAL : integer;
C_DQ15_TAP_DELAY_VAL : integer
);
port (
mcb3_dram_dq : inout std_logic_vector((C_NUM_DQ_PINS-1) downto 0);
mcb3_dram_a : out std_logic_vector((C_MEM_ADDR_WIDTH-1) downto 0);
mcb3_dram_ba : out std_logic_vector((C_MEM_BANKADDR_WIDTH-1) downto 0);
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_odt : out std_logic;
mcb3_dram_cke : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_rzq : inout std_logic;
mcb3_zio : inout std_logic;
mcb3_dram_udm : out std_logic;
calib_done : out std_logic;
async_rst : in std_logic;
sysclk_2x : in std_logic;
sysclk_2x_180 : in std_logic;
pll_ce_0 : in std_logic;
pll_ce_90 : in std_logic;
pll_lock : in std_logic;
mcb_drp_clk : in std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
p2_cmd_clk : in std_logic;
p2_cmd_en : in std_logic;
p2_cmd_instr : in std_logic_vector(2 downto 0);
p2_cmd_bl : in std_logic_vector(5 downto 0);
p2_cmd_byte_addr : in std_logic_vector(29 downto 0);
p2_cmd_empty : out std_logic;
p2_cmd_full : out std_logic;
p2_rd_clk : in std_logic;
p2_rd_en : in std_logic;
p2_rd_data : out std_logic_vector(31 downto 0);
p2_rd_full : out std_logic;
p2_rd_empty : out std_logic;
p2_rd_count : out std_logic_vector(6 downto 0);
p2_rd_overflow : out std_logic;
p2_rd_error : out std_logic;
p3_cmd_clk : in std_logic;
p3_cmd_en : in std_logic;
p3_cmd_instr : in std_logic_vector(2 downto 0);
p3_cmd_bl : in std_logic_vector(5 downto 0);
p3_cmd_byte_addr : in std_logic_vector(29 downto 0);
p3_cmd_empty : out std_logic;
p3_cmd_full : out std_logic;
p3_wr_clk : in std_logic;
p3_wr_en : in std_logic;
p3_wr_mask : in std_logic_vector(3 downto 0);
p3_wr_data : in std_logic_vector(31 downto 0);
p3_wr_full : out std_logic;
p3_wr_empty : out std_logic;
p3_wr_count : out std_logic_vector(6 downto 0);
p3_wr_underrun : out std_logic;
p3_wr_error : out std_logic;
selfrefresh_enter : in std_logic;
selfrefresh_mode : out std_logic
);
end component;
constant C3_CLKOUT0_DIVIDE : integer := 1;
constant C3_CLKOUT1_DIVIDE : integer := 1;
constant C3_CLKOUT2_DIVIDE : integer := 8;
constant C3_CLKOUT3_DIVIDE : integer := 4;
constant C3_CLKOUT4_DIVIDE : integer := 25; -- img clock divider
constant C3_CLKFBOUT_MULT : integer := 25;
constant C3_DIVCLK_DIVIDE : integer := 4;
constant C3_INCLK_PERIOD : integer := ((C3_MEMCLK_PERIOD * C3_CLKFBOUT_MULT) / (C3_DIVCLK_DIVIDE * C3_CLKOUT0_DIVIDE * 2));
constant C3_ARB_NUM_TIME_SLOTS : integer := 12;
constant C3_ARB_TIME_SLOT_0 : bit_vector(5 downto 0) := o"23";
constant C3_ARB_TIME_SLOT_1 : bit_vector(5 downto 0) := o"32";
constant C3_ARB_TIME_SLOT_2 : bit_vector(5 downto 0) := o"23";
constant C3_ARB_TIME_SLOT_3 : bit_vector(5 downto 0) := o"32";
constant C3_ARB_TIME_SLOT_4 : bit_vector(5 downto 0) := o"23";
constant C3_ARB_TIME_SLOT_5 : bit_vector(5 downto 0) := o"32";
constant C3_ARB_TIME_SLOT_6 : bit_vector(5 downto 0) := o"23";
constant C3_ARB_TIME_SLOT_7 : bit_vector(5 downto 0) := o"32";
constant C3_ARB_TIME_SLOT_8 : bit_vector(5 downto 0) := o"23";
constant C3_ARB_TIME_SLOT_9 : bit_vector(5 downto 0) := o"32";
constant C3_ARB_TIME_SLOT_10 : bit_vector(5 downto 0) := o"23";
constant C3_ARB_TIME_SLOT_11 : bit_vector(5 downto 0) := o"32";
constant C3_MEM_TRAS : integer := 42500;
constant C3_MEM_TRCD : integer := 12500;
constant C3_MEM_TREFI : integer := 7800000;
constant C3_MEM_TRFC : integer := 127500;
constant C3_MEM_TRP : integer := 12500;
constant C3_MEM_TWR : integer := 15000;
constant C3_MEM_TRTP : integer := 7500;
constant C3_MEM_TWTR : integer := 7500;
constant C3_MEM_TYPE : string := "DDR2";
constant C3_MEM_DENSITY : string := "1Gb";
constant C3_MEM_BURST_LEN : integer := 4;
constant C3_MEM_CAS_LATENCY : integer := 5;
constant C3_MEM_NUM_COL_BITS : integer := 10;
constant C3_MEM_DDR1_2_ODS : string := "FULL";
constant C3_MEM_DDR2_RTT : string := "50OHMS";
constant C3_MEM_DDR2_DIFF_DQS_EN : string := "YES";
constant C3_MEM_DDR2_3_PA_SR : string := "FULL";
constant C3_MEM_DDR2_3_HIGH_TEMP_SR : string := "NORMAL";
constant C3_MEM_DDR3_CAS_LATENCY : integer := 6;
constant C3_MEM_DDR3_ODS : string := "DIV6";
constant C3_MEM_DDR3_RTT : string := "DIV2";
constant C3_MEM_DDR3_CAS_WR_LATENCY : integer := 5;
constant C3_MEM_DDR3_AUTO_SR : string := "ENABLED";
constant C3_MEM_DDR3_DYN_WRT_ODT : string := "OFF";
constant C3_MEM_MOBILE_PA_SR : string := "FULL";
constant C3_MEM_MDDR_ODS : string := "FULL";
constant C3_MC_CALIB_BYPASS : string := "NO";
constant C3_MC_CALIBRATION_MODE : string := "CALIBRATION";
constant C3_MC_CALIBRATION_DELAY : string := "HALF";
constant C3_SKIP_IN_TERM_CAL : integer := 0;
constant C3_SKIP_DYNAMIC_CAL : integer := 0;
constant C3_LDQSP_TAP_DELAY_VAL : integer := 0;
constant C3_LDQSN_TAP_DELAY_VAL : integer := 0;
constant C3_UDQSP_TAP_DELAY_VAL : integer := 0;
constant C3_UDQSN_TAP_DELAY_VAL : integer := 0;
constant C3_DQ0_TAP_DELAY_VAL : integer := 0;
constant C3_DQ1_TAP_DELAY_VAL : integer := 0;
constant C3_DQ2_TAP_DELAY_VAL : integer := 0;
constant C3_DQ3_TAP_DELAY_VAL : integer := 0;
constant C3_DQ4_TAP_DELAY_VAL : integer := 0;
constant C3_DQ5_TAP_DELAY_VAL : integer := 0;
constant C3_DQ6_TAP_DELAY_VAL : integer := 0;
constant C3_DQ7_TAP_DELAY_VAL : integer := 0;
constant C3_DQ8_TAP_DELAY_VAL : integer := 0;
constant C3_DQ9_TAP_DELAY_VAL : integer := 0;
constant C3_DQ10_TAP_DELAY_VAL : integer := 0;
constant C3_DQ11_TAP_DELAY_VAL : integer := 0;
constant C3_DQ12_TAP_DELAY_VAL : integer := 0;
constant C3_DQ13_TAP_DELAY_VAL : integer := 0;
constant C3_DQ14_TAP_DELAY_VAL : integer := 0;
constant C3_DQ15_TAP_DELAY_VAL : integer := 0;
constant C3_SMALL_DEVICE : string := "FALSE"; -- The parameter is set to TRUE for all packages of xc6slx9 device
-- as most of them cannot fit the complete example design when the
-- Chip scope modules are enabled
signal c3_sys_clk_p : std_logic;
signal c3_sys_clk_n : std_logic;
signal c3_async_rst : std_logic;
signal c3_sysclk_2x : std_logic;
signal c3_sysclk_2x_180 : std_logic;
signal c3_pll_ce_0 : std_logic;
signal c3_pll_ce_90 : std_logic;
signal c3_pll_lock : std_logic;
signal c3_mcb_drp_clk : std_logic;
signal c3_cmp_error : std_logic;
signal c3_cmp_data_valid : std_logic;
signal c3_vio_modify_enable : std_logic;
signal c3_error_status : std_logic_vector(127 downto 0);
signal c3_vio_data_mode_value : std_logic_vector(2 downto 0);
signal c3_vio_addr_mode_value : std_logic_vector(2 downto 0);
signal c3_cmp_data : std_logic_vector(31 downto 0);
signal c3_selfrefresh_enter : std_logic;
signal c3_selfrefresh_mode : std_logic;
begin
c3_sys_clk_p <= '0';
c3_sys_clk_n <= '0';
c3_selfrefresh_enter <= '0';
memc3_infrastructure_inst : memc3_infrastructure
generic map
(
C_RST_ACT_LOW => C3_RST_ACT_LOW,
C_INPUT_CLK_TYPE => C3_INPUT_CLK_TYPE,
C_CLKOUT0_DIVIDE => C3_CLKOUT0_DIVIDE,
C_CLKOUT1_DIVIDE => C3_CLKOUT1_DIVIDE,
C_CLKOUT2_DIVIDE => C3_CLKOUT2_DIVIDE,
C_CLKOUT3_DIVIDE => C3_CLKOUT3_DIVIDE,
C_CLKOUT4_DIVIDE => C3_CLKOUT4_DIVIDE,
C_CLKFBOUT_MULT => C3_CLKFBOUT_MULT,
C_DIVCLK_DIVIDE => C3_DIVCLK_DIVIDE,
C_INCLK_PERIOD => C3_INCLK_PERIOD
)
port map
(
sys_clk_p => c3_sys_clk_p,
sys_clk_n => c3_sys_clk_n,
sys_clk => c3_sys_clk,
sys_rst_i => c3_sys_rst_i,
clk0 => c3_clk0,
clk_img => clk_img,
rst0 => c3_rst0,
async_rst => c3_async_rst,
sysclk_2x => c3_sysclk_2x,
sysclk_2x_180 => c3_sysclk_2x_180,
pll_ce_0 => c3_pll_ce_0,
pll_ce_90 => c3_pll_ce_90,
pll_lock => c3_pll_lock,
mcb_drp_clk => c3_mcb_drp_clk
);
-- wrapper instantiation
memc3_wrapper_inst : memc3_wrapper
generic map
(
C_MEMCLK_PERIOD => C3_MEMCLK_PERIOD,
C_CALIB_SOFT_IP => C3_CALIB_SOFT_IP,
C_SIMULATION => C3_SIMULATION,
C_P0_MASK_SIZE => C3_P0_MASK_SIZE,
C_P0_DATA_PORT_SIZE => C3_P0_DATA_PORT_SIZE,
C_P1_MASK_SIZE => C3_P1_MASK_SIZE,
C_P1_DATA_PORT_SIZE => C3_P1_DATA_PORT_SIZE,
C_ARB_NUM_TIME_SLOTS => C3_ARB_NUM_TIME_SLOTS,
C_ARB_TIME_SLOT_0 => C3_ARB_TIME_SLOT_0,
C_ARB_TIME_SLOT_1 => C3_ARB_TIME_SLOT_1,
C_ARB_TIME_SLOT_2 => C3_ARB_TIME_SLOT_2,
C_ARB_TIME_SLOT_3 => C3_ARB_TIME_SLOT_3,
C_ARB_TIME_SLOT_4 => C3_ARB_TIME_SLOT_4,
C_ARB_TIME_SLOT_5 => C3_ARB_TIME_SLOT_5,
C_ARB_TIME_SLOT_6 => C3_ARB_TIME_SLOT_6,
C_ARB_TIME_SLOT_7 => C3_ARB_TIME_SLOT_7,
C_ARB_TIME_SLOT_8 => C3_ARB_TIME_SLOT_8,
C_ARB_TIME_SLOT_9 => C3_ARB_TIME_SLOT_9,
C_ARB_TIME_SLOT_10 => C3_ARB_TIME_SLOT_10,
C_ARB_TIME_SLOT_11 => C3_ARB_TIME_SLOT_11,
C_MEM_TRAS => C3_MEM_TRAS,
C_MEM_TRCD => C3_MEM_TRCD,
C_MEM_TREFI => C3_MEM_TREFI,
C_MEM_TRFC => C3_MEM_TRFC,
C_MEM_TRP => C3_MEM_TRP,
C_MEM_TWR => C3_MEM_TWR,
C_MEM_TRTP => C3_MEM_TRTP,
C_MEM_TWTR => C3_MEM_TWTR,
C_MEM_ADDR_ORDER => C3_MEM_ADDR_ORDER,
C_NUM_DQ_PINS => C3_NUM_DQ_PINS,
C_MEM_TYPE => C3_MEM_TYPE,
C_MEM_DENSITY => C3_MEM_DENSITY,
C_MEM_BURST_LEN => C3_MEM_BURST_LEN,
C_MEM_CAS_LATENCY => C3_MEM_CAS_LATENCY,
C_MEM_ADDR_WIDTH => C3_MEM_ADDR_WIDTH,
C_MEM_BANKADDR_WIDTH => C3_MEM_BANKADDR_WIDTH,
C_MEM_NUM_COL_BITS => C3_MEM_NUM_COL_BITS,
C_MEM_DDR1_2_ODS => C3_MEM_DDR1_2_ODS,
C_MEM_DDR2_RTT => C3_MEM_DDR2_RTT,
C_MEM_DDR2_DIFF_DQS_EN => C3_MEM_DDR2_DIFF_DQS_EN,
C_MEM_DDR2_3_PA_SR => C3_MEM_DDR2_3_PA_SR,
C_MEM_DDR2_3_HIGH_TEMP_SR => C3_MEM_DDR2_3_HIGH_TEMP_SR,
C_MEM_DDR3_CAS_LATENCY => C3_MEM_DDR3_CAS_LATENCY,
C_MEM_DDR3_ODS => C3_MEM_DDR3_ODS,
C_MEM_DDR3_RTT => C3_MEM_DDR3_RTT,
C_MEM_DDR3_CAS_WR_LATENCY => C3_MEM_DDR3_CAS_WR_LATENCY,
C_MEM_DDR3_AUTO_SR => C3_MEM_DDR3_AUTO_SR,
C_MEM_DDR3_DYN_WRT_ODT => C3_MEM_DDR3_DYN_WRT_ODT,
C_MEM_MOBILE_PA_SR => C3_MEM_MOBILE_PA_SR,
C_MEM_MDDR_ODS => C3_MEM_MDDR_ODS,
C_MC_CALIB_BYPASS => C3_MC_CALIB_BYPASS,
C_MC_CALIBRATION_MODE => C3_MC_CALIBRATION_MODE,
C_MC_CALIBRATION_DELAY => C3_MC_CALIBRATION_DELAY,
C_SKIP_IN_TERM_CAL => C3_SKIP_IN_TERM_CAL,
C_SKIP_DYNAMIC_CAL => C3_SKIP_DYNAMIC_CAL,
C_LDQSP_TAP_DELAY_VAL => C3_LDQSP_TAP_DELAY_VAL,
C_LDQSN_TAP_DELAY_VAL => C3_LDQSN_TAP_DELAY_VAL,
C_UDQSP_TAP_DELAY_VAL => C3_UDQSP_TAP_DELAY_VAL,
C_UDQSN_TAP_DELAY_VAL => C3_UDQSN_TAP_DELAY_VAL,
C_DQ0_TAP_DELAY_VAL => C3_DQ0_TAP_DELAY_VAL,
C_DQ1_TAP_DELAY_VAL => C3_DQ1_TAP_DELAY_VAL,
C_DQ2_TAP_DELAY_VAL => C3_DQ2_TAP_DELAY_VAL,
C_DQ3_TAP_DELAY_VAL => C3_DQ3_TAP_DELAY_VAL,
C_DQ4_TAP_DELAY_VAL => C3_DQ4_TAP_DELAY_VAL,
C_DQ5_TAP_DELAY_VAL => C3_DQ5_TAP_DELAY_VAL,
C_DQ6_TAP_DELAY_VAL => C3_DQ6_TAP_DELAY_VAL,
C_DQ7_TAP_DELAY_VAL => C3_DQ7_TAP_DELAY_VAL,
C_DQ8_TAP_DELAY_VAL => C3_DQ8_TAP_DELAY_VAL,
C_DQ9_TAP_DELAY_VAL => C3_DQ9_TAP_DELAY_VAL,
C_DQ10_TAP_DELAY_VAL => C3_DQ10_TAP_DELAY_VAL,
C_DQ11_TAP_DELAY_VAL => C3_DQ11_TAP_DELAY_VAL,
C_DQ12_TAP_DELAY_VAL => C3_DQ12_TAP_DELAY_VAL,
C_DQ13_TAP_DELAY_VAL => C3_DQ13_TAP_DELAY_VAL,
C_DQ14_TAP_DELAY_VAL => C3_DQ14_TAP_DELAY_VAL,
C_DQ15_TAP_DELAY_VAL => C3_DQ15_TAP_DELAY_VAL
)
port map
(
mcb3_dram_dq => mcb3_dram_dq,
mcb3_dram_a => mcb3_dram_a,
mcb3_dram_ba => mcb3_dram_ba,
mcb3_dram_ras_n => mcb3_dram_ras_n,
mcb3_dram_cas_n => mcb3_dram_cas_n,
mcb3_dram_we_n => mcb3_dram_we_n,
mcb3_dram_odt => mcb3_dram_odt,
mcb3_dram_cke => mcb3_dram_cke,
mcb3_dram_dm => mcb3_dram_dm,
mcb3_dram_udqs => mcb3_dram_udqs,
mcb3_dram_udqs_n => mcb3_dram_udqs_n,
mcb3_rzq => mcb3_rzq,
mcb3_zio => mcb3_zio,
mcb3_dram_udm => mcb3_dram_udm,
calib_done => c3_calib_done,
async_rst => c3_async_rst,
sysclk_2x => c3_sysclk_2x,
sysclk_2x_180 => c3_sysclk_2x_180,
pll_ce_0 => c3_pll_ce_0,
pll_ce_90 => c3_pll_ce_90,
pll_lock => c3_pll_lock,
mcb_drp_clk => c3_mcb_drp_clk,
mcb3_dram_dqs => mcb3_dram_dqs,
mcb3_dram_dqs_n => mcb3_dram_dqs_n,
mcb3_dram_ck => mcb3_dram_ck,
mcb3_dram_ck_n => mcb3_dram_ck_n,
p2_cmd_clk => c3_p2_cmd_clk,
p2_cmd_en => c3_p2_cmd_en,
p2_cmd_instr => c3_p2_cmd_instr,
p2_cmd_bl => c3_p2_cmd_bl,
p2_cmd_byte_addr => c3_p2_cmd_byte_addr,
p2_cmd_empty => c3_p2_cmd_empty,
p2_cmd_full => c3_p2_cmd_full,
p2_rd_clk => c3_p2_rd_clk,
p2_rd_en => c3_p2_rd_en,
p2_rd_data => c3_p2_rd_data,
p2_rd_full => c3_p2_rd_full,
p2_rd_empty => c3_p2_rd_empty,
p2_rd_count => c3_p2_rd_count,
p2_rd_overflow => c3_p2_rd_overflow,
p2_rd_error => c3_p2_rd_error,
p3_cmd_clk => c3_p3_cmd_clk,
p3_cmd_en => c3_p3_cmd_en,
p3_cmd_instr => c3_p3_cmd_instr,
p3_cmd_bl => c3_p3_cmd_bl,
p3_cmd_byte_addr => c3_p3_cmd_byte_addr,
p3_cmd_empty => c3_p3_cmd_empty,
p3_cmd_full => c3_p3_cmd_full,
p3_wr_clk => c3_p3_wr_clk,
p3_wr_en => c3_p3_wr_en,
p3_wr_mask => c3_p3_wr_mask,
p3_wr_data => c3_p3_wr_data,
p3_wr_full => c3_p3_wr_full,
p3_wr_empty => c3_p3_wr_empty,
p3_wr_count => c3_p3_wr_count,
p3_wr_underrun => c3_p3_wr_underrun,
p3_wr_error => c3_p3_wr_error,
selfrefresh_enter => c3_selfrefresh_enter,
selfrefresh_mode => c3_selfrefresh_mode
);
end arc;
|
bsd-2-clause
|
rohit91/HDMI2USB
|
hdl/jpeg_encoder/design/DoubleFifo.vhd
|
3
|
7847
|
-------------------------------------------------------------------------------
-- File Name : DoubleFifo.vhd
--
-- Project : JPEG_ENC
--
-- Module : DoubleFifo
--
-- Content : DoubleFifo
--
-- Description :
--
-- Spec. :
--
-- Author : Michal Krepa
--
-------------------------------------------------------------------------------
-- History :
-- 20090228: (MK): Initial Creation.
-------------------------------------------------------------------------------
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- /// Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- LIBRARY/PACKAGE ---------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- generic packages/libraries:
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- user packages/libraries:
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ENTITY ------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
entity DoubleFifo is
port
(
CLK : in std_logic;
RST : in std_logic;
-- HUFFMAN
data_in : in std_logic_vector(7 downto 0);
wren : in std_logic;
-- BYTE STUFFER
buf_sel : in std_logic;
rd_req : in std_logic;
fifo_empty : out std_logic;
data_out : out std_logic_vector(7 downto 0)
);
end entity DoubleFifo;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ARCHITECTURE ------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture RTL of DoubleFifo is
signal fifo1_rd : std_logic;
signal fifo1_wr : std_logic;
signal fifo1_q : std_logic_vector(7 downto 0);
signal fifo1_full : std_logic;
signal fifo1_empty : std_logic;
signal fifo1_count : std_logic_vector(7 downto 0);
signal fifo2_rd : std_logic;
signal fifo2_wr : std_logic;
signal fifo2_q : std_logic_vector(7 downto 0);
signal fifo2_full : std_logic;
signal fifo2_empty : std_logic;
signal fifo2_count : std_logic_vector(7 downto 0);
signal fifo_data_in : std_logic_vector(7 downto 0);
-------------------------------------------------------------------------------
-- Architecture: begin
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------
-- FIFO 1
-------------------------------------------------------------------
U_FIFO_1 : entity work.FIFO
generic map
(
DATA_WIDTH => 8,
ADDR_WIDTH => 7
)
port map
(
rst => RST,
clk => CLK,
rinc => fifo1_rd,
winc => fifo1_wr,
datai => fifo_data_in,
datao => fifo1_q,
fullo => fifo1_full,
emptyo => fifo1_empty,
count => fifo1_count
);
-------------------------------------------------------------------
-- FIFO 2
-------------------------------------------------------------------
U_FIFO_2 : entity work.FIFO
generic map
(
DATA_WIDTH => 8,
ADDR_WIDTH => 7
)
port map
(
rst => RST,
clk => CLK,
rinc => fifo2_rd,
winc => fifo2_wr,
datai => fifo_data_in,
datao => fifo2_q,
fullo => fifo2_full,
emptyo => fifo2_empty,
count => fifo2_count
);
-------------------------------------------------------------------
-- mux2
-------------------------------------------------------------------
p_mux2 : process(CLK, RST)
begin
if RST = '1' then
fifo1_wr <= '0';
fifo2_wr <= '0';
fifo_data_in <= (others => '0');
elsif CLK'event and CLK = '1' then
if buf_sel = '0' then
fifo1_wr <= wren;
else
fifo2_wr <= wren;
end if;
fifo_data_in <= data_in;
end if;
end process;
-------------------------------------------------------------------
-- mux3
-------------------------------------------------------------------
p_mux3 : process(CLK, RST)
begin
if RST = '1' then
data_out <= (others => '0');
fifo1_rd <= '0';
fifo2_rd <= '0';
fifo_empty <= '0';
elsif CLK'event and CLK = '1' then
if buf_sel = '1' then
data_out <= fifo1_q;
fifo1_rd <= rd_req;
fifo_empty <= fifo1_empty;
else
data_out <= fifo2_q;
fifo2_rd <= rd_req;
fifo_empty <= fifo2_empty;
end if;
end if;
end process;
end architecture RTL;
-------------------------------------------------------------------------------
-- Architecture: end
-------------------------------------------------------------------------------
|
bsd-2-clause
|
rohit91/HDMI2USB
|
ipcore_dir/ddr2ram/example_design/rtl/traffic_gen/cmd_prbs_gen.vhd
|
20
|
8359
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: cmd_prbs_gen.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:16:37 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This moduel use LFSR to generate random address, isntructions
-- or burst_length.
-- Reference:
-- Revision History:
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
ENTITY cmd_prbs_gen IS
GENERIC (
TCQ : time := 100 ps;
FAMILY : STRING := "SPARTAN6";
ADDR_WIDTH : INTEGER := 29;
DWIDTH : INTEGER := 32;
PRBS_CMD : STRING := "ADDRESS";
PRBS_WIDTH : INTEGER := 64;
SEED_WIDTH : INTEGER := 32;
PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"FFFFD000";
PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00002000";
PRBS_EADDR : std_logic_vector(31 downto 0) := X"00002000";
PRBS_SADDR : std_logic_vector(31 downto 0) := X"00002000"
);
PORT (
clk_i : IN STD_LOGIC;
prbs_seed_init : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
prbs_seed_i : IN STD_LOGIC_VECTOR(SEED_WIDTH - 1 DOWNTO 0);
prbs_o : OUT STD_LOGIC_VECTOR(SEED_WIDTH - 1 DOWNTO 0)
);
END cmd_prbs_gen;
ARCHITECTURE trans OF cmd_prbs_gen IS
SIGNAL ZEROS : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
SIGNAL prbs : STD_LOGIC_VECTOR(SEED_WIDTH - 1 DOWNTO 0);
SIGNAL lfsr_q : STD_LOGIC_VECTOR(PRBS_WIDTH DOWNTO 1);
function logb2 (val : integer) return integer is
variable vec_con : integer;
variable rtn : integer := 1;
begin
vec_con := val;
for index in 0 to 31 loop
if(vec_con = 1) then
rtn := rtn + 1;
return(rtn);
end if;
vec_con := vec_con/2;
rtn := rtn + 1;
end loop;
end function logb2;
BEGIN
ZEROS <= std_logic_vector(to_unsigned(0,ADDR_WIDTH));
xhdl0 : IF (PRBS_CMD = "ADDRESS" AND PRBS_WIDTH = 64) GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (prbs_seed_init = '1') THEN
lfsr_q <= ('0' & ("0000000000000000000000000000000" & prbs_seed_i)) ;
ELSIF (clk_en = '1') THEN
lfsr_q(64) <= lfsr_q(64) XOR lfsr_q(63) ;
lfsr_q(63) <= lfsr_q(62) ;
lfsr_q(62) <= lfsr_q(64) XOR lfsr_q(61) ;
lfsr_q(61) <= lfsr_q(64) XOR lfsr_q(60) ;
lfsr_q(60 DOWNTO 2) <= lfsr_q(59 DOWNTO 1) ;
lfsr_q(1) <= lfsr_q(64) ;
END IF;
END IF;
END PROCESS;
PROCESS (lfsr_q(32 DOWNTO 1))
BEGIN
prbs <= lfsr_q(32 DOWNTO 1);
END PROCESS;
END GENERATE;
xhdl1 : IF (PRBS_CMD = "ADDRESS" AND PRBS_WIDTH = 32) GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (prbs_seed_init = '1') THEN
lfsr_q <= prbs_seed_i ;
ELSIF (clk_en = '1') THEN
lfsr_q(32 DOWNTO 9) <= lfsr_q(31 DOWNTO 8) ;
lfsr_q(8) <= lfsr_q(32) XOR lfsr_q(7) ;
lfsr_q(7) <= lfsr_q(32) XOR lfsr_q(6) ;
lfsr_q(6 DOWNTO 4) <= lfsr_q(5 DOWNTO 3) ;
lfsr_q(3) <= lfsr_q(32) XOR lfsr_q(2) ;
lfsr_q(2) <= lfsr_q(1) ;
lfsr_q(1) <= lfsr_q(32) ;
END IF;
END IF;
END PROCESS;
PROCESS (lfsr_q(32 DOWNTO 1))
BEGIN
IF (FAMILY = "SPARTAN6") THEN
FOR i IN (logb2(DWIDTH) + 1) TO SEED_WIDTH - 1 LOOP
IF (PRBS_SADDR_MASK_POS(i) = '1') THEN
prbs(i) <= PRBS_SADDR(i) OR lfsr_q(i + 1);
ELSIF (PRBS_EADDR_MASK_POS(i) = '1') THEN
prbs(i) <= PRBS_EADDR(i) AND lfsr_q(i + 1);
ELSE
prbs(i) <= lfsr_q(i + 1);
END IF;
END LOOP;
prbs(logb2(DWIDTH) downto 0) <= (others => '0');
ELSE
FOR i IN (logb2(DWIDTH) - 4) TO SEED_WIDTH - 1 LOOP
IF (PRBS_SADDR_MASK_POS(i) = '1') THEN
prbs(i) <= PRBS_SADDR(i) OR lfsr_q(i + 1);
ELSIF (PRBS_EADDR_MASK_POS(i) = '1') THEN
prbs(i) <= PRBS_EADDR(i) AND lfsr_q(i + 1);
ELSE
prbs(i) <= lfsr_q(i + 1);
END IF;
END LOOP;
prbs(logb2(DWIDTH) downto 0) <= (others => '0');
END IF;
END PROCESS;
END GENERATE;
xhdl2 : IF (PRBS_CMD = "INSTR" OR PRBS_CMD = "BLEN") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (prbs_seed_init = '1') THEN
lfsr_q <= ("00000" & prbs_seed_i(14 DOWNTO 0)) ;
ELSIF (clk_en = '1') THEN
lfsr_q(20) <= lfsr_q(19) ;
lfsr_q(19) <= lfsr_q(18) ;
lfsr_q(18) <= lfsr_q(20) XOR lfsr_q(17) ;
lfsr_q(17 DOWNTO 2) <= lfsr_q(16 DOWNTO 1) ;
lfsr_q(1) <= lfsr_q(20) ;
END IF;
END IF;
END PROCESS;
PROCESS (lfsr_q(SEED_WIDTH - 1 DOWNTO 1), ZEROS)
BEGIN
prbs <= (ZEROS(SEED_WIDTH - 1 DOWNTO 6) & lfsr_q(6 DOWNTO 1));
END PROCESS;
END GENERATE;
prbs_o <= prbs;
END trans;
|
bsd-2-clause
|
rohit91/HDMI2USB
|
ipcore_dir/ddr2ram/example_design/rtl/traffic_gen/init_mem_pattern_ctr.vhd
|
20
|
25087
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: init_mem_pattern_ctr.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:16:39 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This moduel has a small FSM to control the operation of
-- mcb_traffic_gen module.It first fill up the memory with a selected
-- DATA pattern and then starts the memory testing state.
-- Reference:
-- Revision History: 1.1 Modify to allow data_mode_o to be controlled by parameter DATA_MODE
-- and the fixed_bl_o is fixed at 64 if data_mode_o == PRBS and FAMILY == "SPARTAN6"
-- The fixed_bl_o in Virtex6 is determined by the MEM_BURST_LENGTH.
-- 1.2 05/19/2010 If MEM_BURST_LEN value is passed with value of zero, it is treated as
-- "OTF" Burst Mode and TG will only generate BL 8 traffic.
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
ENTITY init_mem_pattern_ctr IS
GENERIC (
FAMILY : STRING := "SPARTAN6";
TST_MEM_INSTR_MODE : STRING := "R_W_INSTR_MODE";
MEM_BURST_LEN : INTEGER := 8;
CMD_PATTERN : STRING := "CGEN_ALL";
BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000000";
END_ADDRESS : std_logic_vector(31 downto 0) := X"00000fff";
ADDR_WIDTH : INTEGER := 30;
DWIDTH : INTEGER := 32;
CMD_SEED_VALUE : std_logic_vector(31 downto 0) := X"12345678";
DATA_SEED_VALUE : std_logic_vector(31 downto 0) := X"ca345675";
DATA_MODE : std_logic_vector(3 downto 0) := "0010";
PORT_MODE : STRING := "BI_MODE";
EYE_TEST : STRING := "FALSE"
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : IN STD_LOGIC;
mcb_cmd_bl_i : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
mcb_cmd_en_i : IN STD_LOGIC;
mcb_cmd_instr_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
mcb_wr_en_i : IN STD_LOGIC;
vio_modify_enable : IN STD_LOGIC;
vio_data_mode_value : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
vio_addr_mode_value : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
vio_bl_mode_value : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
vio_fixed_bl_value : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
mcb_init_done_i : IN STD_LOGIC;
cmp_error : IN STD_LOGIC;
run_traffic_o : OUT STD_LOGIC;
start_addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
end_addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
cmd_seed_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
data_seed_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
load_seed_o : OUT STD_LOGIC;
addr_mode_o : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
instr_mode_o : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bl_mode_o : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
data_mode_o : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
mode_load_o : OUT STD_LOGIC;
fixed_bl_o : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
fixed_instr_o : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
fixed_addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END init_mem_pattern_ctr;
ARCHITECTURE trans OF init_mem_pattern_ctr IS
constant IDLE : std_logic_vector(4 downto 0) := "00001";
constant INIT_MEM_WRITE : std_logic_vector(4 downto 0) := "00010";
constant INIT_MEM_READ : std_logic_vector(4 downto 0) := "00100";
constant TEST_MEM : std_logic_vector(4 downto 0) := "01000";
constant CMP_ERROR1 : std_logic_vector(4 downto 0) := "10000";
constant BRAM_ADDR : std_logic_vector(1 downto 0) := "00";
constant FIXED_ADDR : std_logic_vector(2 downto 0) := "001";
constant PRBS_ADDR : std_logic_vector(2 downto 0) := "010";
constant SEQUENTIAL_ADDR : std_logic_vector(2 downto 0) := "011";
constant BRAM_INSTR_MODE : std_logic_vector(3 downto 0) := "0000";
constant FIXED_INSTR_MODE : std_logic_vector(3 downto 0) := "0001";
constant FIXED_INSTR_MODE_WITH_REFRESH : std_logic_vector(3 downto 0) := "0110";
constant R_W_INSTR_MODE : std_logic_vector(3 downto 0) := "0010";
constant RP_WP_INSTR_MODE : std_logic_vector(3 downto 0) := "0011";
constant R_RP_W_WP_INSTR_MODE : std_logic_vector(3 downto 0) := "0100";
constant R_RP_W_WP_REF_INSTR_MODE : std_logic_vector(3 downto 0) := "0101";
constant BRAM_BL_MODE : std_logic_vector(1 downto 0) := "00";
constant FIXED_BL_MODE : std_logic_vector(1 downto 0) := "01";
constant PRBS_BL_MODE : std_logic_vector(1 downto 0) := "10";
constant BRAM_DATAL_MODE : std_logic_vector(3 downto 0) := "0000";
constant FIXED_DATA_MODE : std_logic_vector(3 downto 0) := "0001";
constant ADDR_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
constant HAMMER_DATA_MODE : std_logic_vector(3 downto 0) := "0011";
constant NEIGHBOR_DATA_MODE : std_logic_vector(3 downto 0) := "0100";
constant WALKING1_DATA_MODE : std_logic_vector(3 downto 0) := "0101";
constant WALKING0_DATA_MODE : std_logic_vector(3 downto 0) := "0110";
constant PRBS_DATA_MODE : std_logic_vector(3 downto 0) := "0111";
constant RD_INSTR : std_logic_vector(2 downto 0) := "001";
constant RDP_INSTR : std_logic_vector(2 downto 0) := "011";
constant WR_INSTR : std_logic_vector(2 downto 0) := "000";
constant WRP_INSTR : std_logic_vector(2 downto 0) := "010";
constant REFRESH_INSTR : std_logic_vector(2 downto 0) := "100";
constant NOP_WR_INSTR : std_logic_vector(2 downto 0) := "101";
SIGNAL current_state : STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL next_state : STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL mcb_init_done_reg : STD_LOGIC;
SIGNAL mcb_init_done_reg1 : STD_LOGIC;
SIGNAL AC2_G_E2 : STD_LOGIC;
SIGNAL AC1_G_E1 : STD_LOGIC;
SIGNAL AC3_G_E3 : STD_LOGIC;
SIGNAL upper_end_matched : STD_LOGIC;
SIGNAL end_boundary_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL mcb_cmd_en_r : STD_LOGIC;
SIGNAL mcb_cmd_bl_r : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL lower_end_matched : STD_LOGIC;
SIGNAL end_addr_reached : STD_LOGIC;
SIGNAL run_traffic : STD_LOGIC;
SIGNAL current_address : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL fix_bl_value : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL data_mode_sel : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL addr_mode_sel : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL bl_mode_sel : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL addr_mode : STD_LOGIC_VECTOR(2 DOWNTO 0);
-- SIGNAL data_mode1 : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL INC_COUNTS : STD_LOGIC_VECTOR(10 DOWNTO 0);
SIGNAL FIXEDBL : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL FIXED_BL_VALUE : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL bram_mode_enable : STD_LOGIC;
SIGNAL syn1_vio_data_mode_value : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL syn1_vio_addr_mode_value : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL test_mem_instr_mode : STD_LOGIC_VECTOR(3 DOWNTO 0);
-- Declare intermediate signals for referenced outputs
SIGNAL bl_mode_o_xhdl0 : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL data_mode_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
test_mem_instr_mode <= "0000" when TST_MEM_INSTR_MODE = "BRAM_INSTR_MODE" else
"0001" when (TST_MEM_INSTR_MODE = "FIXED_INSTR_R_MODE") OR
(TST_MEM_INSTR_MODE = "FIXED_INSTR_W_MODE") else
"0010" when TST_MEM_INSTR_MODE = "R_W_INSTR_MODE" else
"0011" when (TST_MEM_INSTR_MODE = "RP_WP_INSTR_MODE" AND
FAMILY = "SPARTAN6") else
"0100" when (TST_MEM_INSTR_MODE = "R_RP_W_WP_INSTR_MODE" AND
FAMILY = "SPARTAN6")else
"0101" when (TST_MEM_INSTR_MODE = "R_RP_W_WP_REF_INSTR_MODE"AND
FAMILY = "SPARTAN6") else
"0010" ;
-- Drive referenced outputs
bl_mode_o <= bl_mode_o_xhdl0;
FIXEDBL <= "000000";
xhdl1 : IF (FAMILY = "SPARTAN6") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
INC_COUNTS <= std_logic_vector(to_unsigned(DWIDTH/8,11));
END IF;
END PROCESS;
END GENERATE;
xhdl2 : IF (FAMILY = "VIRTEX6") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (DWIDTH >= 256 AND DWIDTH <= 576) THEN
INC_COUNTS <= "00000100000";
ELSIF ((DWIDTH >= 128) AND (DWIDTH <= 224)) THEN
INC_COUNTS <= "00000010000";
ELSIF ((DWIDTH = 64) OR (DWIDTH = 96)) THEN
INC_COUNTS <= "00000001000";
ELSIF (DWIDTH = 32) THEN
INC_COUNTS <= "00000000100";
END IF;
END IF;
END PROCESS;
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i = '1') THEN
current_address <= BEGIN_ADDRESS;
ELSIF (
-- ((mcb_wr_en_i = '1' AND (current_state = INIT_MEM_WRITE AND ((PORT_MODE = "WR_MODE") OR (PORT_MODE = "BI_MODE")))) OR
(mcb_wr_en_i = '1' AND (current_state = INIT_MEM_WRITE AND (PORT_MODE = "WR_MODE" OR PORT_MODE = "BI_MODE"))) OR
(mcb_wr_en_i = '1' AND (current_state = IDLE AND PORT_MODE = "RD_MODE" ))
) THEN
current_address <= current_address + ("000000000000000000000" & INC_COUNTS);
ELSE
current_address <= current_address;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (current_address(29 DOWNTO 24) >= end_boundary_addr(29 DOWNTO 24)) THEN
AC3_G_E3 <= '1';
ELSE
AC3_G_E3 <= '0';
END IF;
IF (current_address(23 DOWNTO 16) >= end_boundary_addr(23 DOWNTO 16)) THEN
AC2_G_E2 <= '1';
ELSE
AC2_G_E2 <= '0';
END IF;
IF (current_address(15 DOWNTO 8) >= end_boundary_addr(15 DOWNTO 8)) THEN
AC1_G_E1 <= '1';
ELSE
AC1_G_E1 <= '0';
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i = '1') THEN
upper_end_matched <= '0';
ELSIF (mcb_cmd_en_i = '1') THEN
upper_end_matched <= AC3_G_E3 AND AC2_G_E2 AND AC1_G_E1;
END IF;
END IF;
END PROCESS;
FIXED_BL_VALUE <= "0000010" WHEN ((FAMILY = "VIRTEX6") AND ((MEM_BURST_LEN = 8) OR (MEM_BURST_LEN = 0))) ELSE
"0000001" WHEN ((FAMILY = "VIRTEX6") AND (MEM_BURST_LEN = 4)) ELSE
('0' & FIXEDBL);
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
end_boundary_addr <= std_logic_vector(to_unsigned((to_integer(unsigned(END_ADDRESS)) - (DWIDTH / 8) + 1),32));
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (current_address(7 DOWNTO 0) >= end_boundary_addr(7 DOWNTO 0)) THEN
lower_end_matched <= '1';
ELSE
lower_end_matched <= '0';
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (mcb_cmd_en_i = '1') THEN
mcb_cmd_bl_r <= mcb_cmd_bl_i;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (((upper_end_matched = '1' AND lower_end_matched = '1') AND FAMILY = "SPARTAN6" AND (DWIDTH = 32)) OR
((upper_end_matched = '1' AND lower_end_matched = '1') AND FAMILY = "SPARTAN6" AND (DWIDTH = 64)) OR
(upper_end_matched = '1' AND DWIDTH = 128 AND FAMILY = "SPARTAN6") OR
((upper_end_matched = '1' AND lower_end_matched = '1') AND FAMILY = "VIRTEX6")) THEN
end_addr_reached <= '1';
ELSE
end_addr_reached <= '0';
END IF;
END IF;
END PROCESS;
fixed_addr_o <= "00000000000000000001001000110100";
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
mcb_init_done_reg1 <= mcb_init_done_i;
mcb_init_done_reg <= mcb_init_done_reg1;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
run_traffic_o <= run_traffic;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i = '1') THEN
current_state <= "00001";
ELSE
current_state <= next_state;
END IF;
END IF;
END PROCESS;
start_addr_o <= BEGIN_ADDRESS;
end_addr_o <= END_ADDRESS;
cmd_seed_o <= CMD_SEED_VALUE;
data_seed_o <= DATA_SEED_VALUE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i = '1') THEN
syn1_vio_data_mode_value <= "011";
syn1_vio_addr_mode_value <= "011";
ELSIF (vio_modify_enable = '1') THEN
syn1_vio_data_mode_value <= vio_data_mode_value;
syn1_vio_addr_mode_value <= vio_addr_mode_value;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i = '1') THEN
data_mode_sel <= DATA_MODE; --"0101" ADDR_DATA_MODE;
addr_mode_sel <= "011";
ELSIF (vio_modify_enable = '1') THEN
data_mode_sel <= '0' & syn1_vio_data_mode_value(2 DOWNTO 0);
addr_mode_sel <= vio_addr_mode_value;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i = '1') OR (FAMILY = "VIRTEX6")) THEN
fix_bl_value <= FIXED_BL_VALUE(5 DOWNTO 0);
ELSIF (vio_modify_enable = '1') THEN
fix_bl_value <= vio_fixed_bl_value;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i = '1' OR (FAMILY = "VIRTEX6")) THEN
IF (FAMILY = "VIRTEX6") THEN
bl_mode_sel <= FIXED_BL_MODE;
ELSE
bl_mode_sel <= PRBS_BL_MODE;
END IF;
ELSIF (vio_modify_enable = '1') THEN
bl_mode_sel <= vio_bl_mode_value;
END IF;
END IF;
END PROCESS;
data_mode_o <= data_mode_reg;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
data_mode_reg <= data_mode_sel;
addr_mode_o <= addr_mode;
IF (syn1_vio_addr_mode_value = 0 AND vio_modify_enable = '1') THEN
bram_mode_enable <= '1';
ELSE
bram_mode_enable <= '0';
END IF;
END IF;
END PROCESS;
PROCESS (FIXED_BL_VALUE,fix_bl_value,bram_mode_enable,test_mem_instr_mode, current_state, mcb_init_done_reg, end_addr_reached, cmp_error, bl_mode_sel, addr_mode_sel, data_mode_reg,bl_mode_o_xhdl0)
BEGIN
load_seed_o <= '0';
IF (CMD_PATTERN = "CGEN_BRAM" or bram_mode_enable = '1') THEN
addr_mode <= (others => '0');
ELSE
addr_mode <= SEQUENTIAL_ADDR;
END IF;
IF (CMD_PATTERN = "CGEN_BRAM" or bram_mode_enable = '1') THEN
instr_mode_o <= (others => '0');
ELSE
instr_mode_o <= FIXED_INSTR_MODE;
END IF;
IF (CMD_PATTERN = "CGEN_BRAM" or bram_mode_enable = '1') THEN
bl_mode_o_xhdl0 <= (others => '0');
ELSE
bl_mode_o_xhdl0 <= FIXED_BL_MODE;
END IF;
-- data_mode1 <= WALKING1_DATA_MODE;
IF (FAMILY = "VIRTEX6") THEN
fixed_bl_o <= FIXED_BL_VALUE(5 downto 0); --"000010"; --2
-- PRBS mode
else if (data_mode_reg(2 downto 0) = "111" and FAMILY = "SPARTAN6") then
fixed_bl_o <= "000000";-- 64 Our current PRBS algorithm wants to maximize the range bl from 1 to 64.
else
fixed_bl_o <= fix_bl_value;
end if;
end if;
mode_load_o <= '0';
run_traffic <= '0';
next_state <= IDLE;
IF (PORT_MODE = "RD_MODE") THEN
fixed_instr_o <= RD_INSTR;
ELSIF (PORT_MODE = "WR_MODE" OR PORT_MODE = "BI_MODE") THEN
fixed_instr_o <= WR_INSTR;
END IF;
CASE current_state IS
WHEN IDLE =>
IF (mcb_init_done_reg = '1') THEN
IF (PORT_MODE = "WR_MODE" OR PORT_MODE = "BI_MODE") THEN
next_state <= INIT_MEM_WRITE;
mode_load_o <= '1';
run_traffic <= '0';
load_seed_o <= '1';
ELSIF (PORT_MODE = "RD_MODE" AND end_addr_reached = '1') THEN
next_state <= TEST_MEM;
mode_load_o <= '1';
run_traffic <= '1';
load_seed_o <= '1';
END IF;
ELSE
next_state <= IDLE;
run_traffic <= '0';
load_seed_o <= '0';
END IF;
WHEN INIT_MEM_WRITE =>
IF (end_addr_reached = '1' AND EYE_TEST = "FALSE") THEN
next_state <= TEST_MEM;
mode_load_o <= '1';
load_seed_o <= '1';
run_traffic <= '1';
ELSE
next_state <= INIT_MEM_WRITE;
run_traffic <= '1';
mode_load_o <= '0';
load_seed_o <= '0';
IF (EYE_TEST = "TRUE") THEN
addr_mode <= FIXED_ADDR;
ELSIF (CMD_PATTERN = "CGEN_BRAM" OR bram_mode_enable = '1') THEN
addr_mode <= "000";
ELSE
addr_mode <= SEQUENTIAL_ADDR;
END IF;
END IF;
WHEN INIT_MEM_READ =>
IF (end_addr_reached = '1') THEN
next_state <= TEST_MEM;
mode_load_o <= '1';
load_seed_o <= '1';
ELSE
next_state <= INIT_MEM_READ;
run_traffic <= '0';
mode_load_o <= '0';
load_seed_o <= '0';
END IF;
WHEN TEST_MEM =>
IF (cmp_error = '1') THEN
next_state <= CMP_ERROR1;
ELSE
next_state <= TEST_MEM;
END IF;
run_traffic <= '1';
IF (PORT_MODE = "BI_MODE" AND TST_MEM_INSTR_MODE = "FIXED_INSTR_W_MODE") THEN
fixed_instr_o <= WR_INSTR;
ELSIF (PORT_MODE = "BI_MODE" AND TST_MEM_INSTR_MODE = "FIXED_INSTR_R_MODE") THEN
fixed_instr_o <= RD_INSTR;
ELSIF (PORT_MODE = "RD_MODE") THEN
fixed_instr_o <= RD_INSTR;
ELSIF (PORT_MODE = "WR_MODE") THEN
fixed_instr_o <= WR_INSTR;
END IF;
if (FAMILY = "VIRTEX6") then
fixed_bl_o <= fix_bl_value; --"000010"; 2
else if ((data_mode_reg = "0111") and (FAMILY = "SPARTAN6")) then
fixed_bl_o <= "000000"; -- 64 Our current PRBS algorithm wants to maximize the range bl from 1 to 64.
else
fixed_bl_o <= fix_bl_value;
end if;
end if;
bl_mode_o_xhdl0 <= bl_mode_sel;
IF (bl_mode_o_xhdl0 = PRBS_BL_MODE) THEN
addr_mode <= PRBS_ADDR;
ELSE
addr_mode <= addr_mode_sel;
END IF;
IF (PORT_MODE = "BI_MODE") THEN
IF (CMD_PATTERN = "CGEN_BRAM" OR bram_mode_enable = '1') THEN
instr_mode_o <= BRAM_INSTR_MODE;
ELSE
instr_mode_o <= test_mem_instr_mode;
--R_RP_W_WP_REF_INSTR_MODE;--FIXED_INSTR_MODE;--R_W_INSTR_MODE;--R_RP_W_WP_INSTR_MODE;--R_W_INSTR_MODE;
--R_W_INSTR_MODE; --FIXED_INSTR_MODE;--
END IF;
ELSIF (PORT_MODE = "RD_MODE" OR PORT_MODE = "WR_MODE") THEN
instr_mode_o <= FIXED_INSTR_MODE;
END IF;
WHEN CMP_ERROR1 =>
next_state <= CMP_ERROR1;
bl_mode_o_xhdl0 <= bl_mode_sel;
fixed_instr_o <= RD_INSTR;
addr_mode <= SEQUENTIAL_ADDR;
IF (CMD_PATTERN = "CGEN_BRAM" OR bram_mode_enable = '1') THEN
instr_mode_o <= BRAM_INSTR_MODE;
ELSE
instr_mode_o <= test_mem_instr_mode;
--R_W_INSTR_MODE;--R_W_INSTR_MODE; --FIXED_INSTR_MODE;--
END IF;
run_traffic <= '1';
WHEN OTHERS =>
next_state <= IDLE;
END CASE;
END PROCESS;
END trans;
|
bsd-2-clause
|
rohit91/HDMI2USB
|
ipcore_dir/cdcfifo/simulation/cdcfifo_synth.vhd
|
3
|
11266
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: cdcfifo_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY work;
USE work.cdcfifo_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY cdcfifo_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF cdcfifo_synth IS
-- FIFO interface signal declarations
SIGNAL wr_clk_i : STD_LOGIC;
SIGNAL rd_clk_i : STD_LOGIC;
SIGNAL almost_full : STD_LOGIC;
SIGNAL almost_empty : STD_LOGIC;
SIGNAL rst : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(8-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(8-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(8-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(8-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_s_wr1 : STD_LOGIC := '0';
SIGNAL rst_s_wr2 : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_wr1 : STD_LOGIC := '0';
SIGNAL rst_async_wr2 : STD_LOGIC := '0';
SIGNAL rst_async_wr3 : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_wr3 OR rst_s_wr3;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(rd_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
PROCESS(wr_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_wr1 <= '1';
rst_async_wr2 <= '1';
rst_async_wr3 <= '1';
ELSIF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_async_wr1 <= RESET;
rst_async_wr2 <= rst_async_wr1;
rst_async_wr3 <= rst_async_wr2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(rd_clk_i)
BEGIN
IF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(wr_clk_i)
BEGIN
IF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_s_wr1 <= rst_s_rd;
rst_s_wr2 <= rst_s_wr1;
rst_s_wr3 <= rst_s_wr2;
IF(rst_s_wr3 = '1' AND rst_s_wr2 = '0') THEN
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
wr_clk_i <= WR_CLK;
rd_clk_i <= RD_CLK;
------------------
rst <= RESET OR rst_s_rd AFTER 12 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
almost_empty_i <= almost_empty;
almost_full_i <= almost_full;
fg_dg_nv: cdcfifo_dgen
GENERIC MAP (
C_DIN_WIDTH => 8,
C_DOUT_WIDTH => 8,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => wr_clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: cdcfifo_dverif
GENERIC MAP (
C_DOUT_WIDTH => 8,
C_DIN_WIDTH => 8,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => rd_clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: cdcfifo_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 8,
C_DIN_WIDTH => 8,
C_WR_PNTR_WIDTH => 11,
C_RD_PNTR_WIDTH => 11,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
cdcfifo_inst : cdcfifo_exdes
PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
ALMOST_FULL => almost_full,
ALMOST_EMPTY => almost_empty,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
|
bsd-2-clause
|
rohit91/HDMI2USB
|
ipcore_dir/cmdfifo/simulation/cmdfifo_rng.vhd
|
3
|
3884
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: cmdfifo_rng.vhd
--
-- Description:
-- Used for generation of pseudo random numbers
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
ENTITY cmdfifo_rng IS
GENERIC (
WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0));
END ENTITY;
ARCHITECTURE rg_arch OF cmdfifo_rng IS
BEGIN
PROCESS (CLK,RESET)
VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width);
VARIABLE temp : STD_LOGIC := '0';
BEGIN
IF(RESET = '1') THEN
rand_temp := conv_std_logic_vector(SEED,width);
temp := '0';
ELSIF (CLK'event AND CLK = '1') THEN
IF (ENABLE = '1') THEN
temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5);
rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0);
rand_temp(0) := temp;
END IF;
END IF;
RANDOM_NUM <= rand_temp;
END PROCESS;
END ARCHITECTURE;
|
bsd-2-clause
|
rohit91/HDMI2USB
|
hdl/misc/controller.vhd
|
2
|
13411
|
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- // Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
--
-- Adds
-- U = usb/uvc
-- J = jpeg encoder
-- S = source selector
-- H = Hdmi
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
entity controller is
port
(
status : out std_logic_vector(4 downto 0);
usb_cmd : out std_logic_vector(2 downto 0); -- UVCpayloadheader(0), raw/jpeg(1), uvc on/off(2)
jpeg_encoder_cmd : out std_logic_vector(1 downto 0); -- encodingQuality(1 downto 0)
selector_cmd : out std_logic_vector(12 downto 0); -- (1:0 source ) (2 gray/color) (3 inverted/not-inverted) (4:5 blue depth) (6:7 green depth) (8:9 red depth) (10 blue on/off) (11 green on/off) (12 red on/off)
HB_on : out std_logic;
uart_rd : out std_logic;
uart_rx_empty : in std_logic;
uart_din : in std_logic_vector(7 downto 0);
uart_clk : in std_logic;
usb_or_uart : in std_logic;
hdmi_cmd : out std_logic_vector(1 downto 0); -- if 1 then dvi else hdmi
hdmi_dvi : in std_logic_vector(1 downto 0); -- if 1 then dvi else hdmi
rdy_H : in std_logic_vector(1 downto 0);
btnu : in std_logic;
btnd : in std_logic;
btnl : in std_logic;
btnr : in std_logic;
uvc_rst : out std_logic;
cmd_byte : in std_logic_vector(7 downto 0);
cmd_en : in std_logic;
rst : in std_logic;
ifclk : in std_logic;
clk : in std_logic
);
end entity;
ARCHITECTURE rtl OF controller is
COMPONENT cmdfifo
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC
);
END COMPONENT;
signal usb_cmd_i : std_logic_vector(2 downto 0); -- UVCpayloadheader(0), raw/jpeg(1), uvc on/off(2)
signal jpeg_encoder_cmd_i : std_logic_vector(1 downto 0); -- encodingQuality(1 downto 0)
signal selector_cmd_i : std_logic_vector(12 downto 0); -- (1:0 source ) (2 gray/color) (3 inverted/not-inverted) (4:5 blue depth) (6:7 green depth) (8:9 red depth) (10 blue on/off) (11 green on/off) (12 red on/off)
signal HB_on_i : std_logic;
signal hdmi_cmd_i : std_logic_vector(1 downto 0); -- if 1 then dvi else hdmi
signal hdmi_dvi_q : std_logic_vector(1 downto 0); -- if 1 then dvi else hdmi
signal counter : std_logic_vector(7 downto 0);
signal cmd : STD_LOGIC_VECTOR(7 DOWNTO 0);
signal add : STD_LOGIC_VECTOR(7 DOWNTO 0);
signal rd_en : STD_LOGIC;
signal dout : STD_LOGIC_VECTOR(15 DOWNTO 0);
signal full : STD_LOGIC;
signal almost_full : STD_LOGIC;
signal empty : STD_LOGIC;
signal almost_empty : STD_LOGIC;
signal valid : STD_LOGIC;
signal uvc_rst_i : STD_LOGIC;
signal vsync_q : STD_LOGIC;
signal vsync_rising_edge : STD_LOGIC;
signal pressed : STD_LOGIC;
signal toggle : STD_LOGIC;
signal uart_rd_s : STD_LOGIC;
signal empty_s : STD_LOGIC;
signal fifo_din : STD_LOGIC_VECTOR(7 downto 0);
signal fifo_clk : STD_LOGIC;
signal fifo_wr : STD_LOGIC;
begin
-- comb logic
usb_cmd <= usb_cmd_i;
jpeg_encoder_cmd <= jpeg_encoder_cmd_i;
selector_cmd <= selector_cmd_i;
hdmi_cmd <= hdmi_cmd_i;
HB_on <= HB_on_i;
-- CMD Decoder
process(rst,clk)
begin
if rst = '1' then
usb_cmd_i <= "001"; -- uvc on/off(2) raw/jpeg(1) UVCpayloadheader(0)
jpeg_encoder_cmd_i <= "00"; -- encodingQuality(1 downto 0)
selector_cmd_i(3 downto 0) <= "0111"; -- (1:0 source ) (2 gray/color) (3 inverted/not-inverted)
selector_cmd_i(12 downto 4) <= "111000000"; --(4:5 blue depth) (6:7 green depth) (8:9 red depth) (10 blue on/off) (11 green on/off) (12 red on/off)
HB_on_i <= '1';
hdmi_cmd_i <= "11"; -- if 1 then dvi else hdmi
uvc_rst_i <= '1';
pressed <= '0';
hdmi_dvi_q <= "00";
status <= (others => '0');
toggle <= '0';
counter <= (others => '0');
elsif rising_edge(clk) then
if uvc_rst_i = '1' then
uvc_rst <= '1';
counter <= (others => '0');
toggle <= '1';
else
counter <= counter+1;
end if;
if counter = (counter'range => '1') and toggle = '1' then
uvc_rst <= '0';
toggle <= '0';
end if;
uvc_rst_i <= '0';
status <= (others => '0');
rd_en <= '0';
hdmi_dvi_q <= hdmi_dvi;
if (hdmi_dvi_q(0) xor hdmi_dvi(0)) = '1' then
hdmi_cmd_i(0) <= hdmi_dvi(0);
end if;
if (hdmi_dvi_q(1) xor hdmi_dvi(1)) = '1' then
hdmi_cmd_i(1) <= hdmi_dvi(1);
end if;
if btnd = '1' and pressed = '0' then
uvc_rst_i <= '1';
selector_cmd_i(1 downto 0) <= "11";
pressed <= '1';
else
pressed <= '0';
end if;
if btnl = '1' and pressed = '0' and rdy_H(1) = '1' then
uvc_rst_i <= '1';
selector_cmd_i(1 downto 0) <= "01";
pressed <= '1';
else
pressed <= '0';
end if;
if btnu = '1' and pressed = '0' and rdy_H(0) = '1' then
uvc_rst_i <= '1';
selector_cmd_i(1 downto 0) <= "00";
pressed <= '1';
else
pressed <= '0';
end if;
if empty = '0' and rd_en = '0' then
rd_en <= '1';
case add is
when X"55" | X"75" => -- U UVC/USB / UVCpayloadheader(0), raw/jpeg(1), uvc on/off(2)
case cmd is
when X"4a" | X"6a" => -- J j
usb_cmd_i(1) <= '1';
uvc_rst_i <= '1';
when X"52" | X"72" => -- Rr
usb_cmd_i(1) <= '0';
uvc_rst_i <= '1';
when X"4e" | X"6e" => -- N n (on)
usb_cmd_i(2) <= '1';
uvc_rst_i <= '1';
when X"46" | X"66" => -- Ff (off)
usb_cmd_i(2) <= '0';
uvc_rst_i <= '1';
when X"56" | X"76" => -- V v (video) header on
usb_cmd_i(0) <= '1';
uvc_rst_i <= '1';
when X"49" | X"69" => -- I i (image) header off
usb_cmd_i(0) <= '0';
uvc_rst_i <= '1';
when X"53" | X"73" => -- Status
status(0) <= '1';
when X"48" | X"68" => -- H
uvc_rst_i <= '1';
if (selector_cmd_i(1 downto 0) = "00") then -- hdmi 0
hdmi_cmd_i(0) <= '0'; -- HDMI
elsif (selector_cmd_i(1 downto 0) = "01") then -- hdmi 1
hdmi_cmd_i(1) <= '0'; -- HDMI
end if;
when X"44" | X"64" => -- D
uvc_rst_i <= '1';
if (selector_cmd_i(1 downto 0) = "00") then -- hdmi 0
hdmi_cmd_i(0) <= '1'; -- DVI
elsif (selector_cmd_i(1 downto 0) = "01") then -- hdmi 1
hdmi_cmd_i(1) <= '1'; -- DVI
end if;
when others =>
end case;
when X"4a" | X"6a" => -- J Jpeg
case cmd is
when X"53" | X"73" => -- Status
status(1) <= '1';
when X"30" => -- quality 100 %
jpeg_encoder_cmd_i(1 downto 0) <= "00";
when X"31" => -- quality 85%
jpeg_encoder_cmd_i(1 downto 0) <= "01";
when X"32" => -- quality 75%
jpeg_encoder_cmd_i(1 downto 0) <= "10";
when X"33" => -- quality 50%
jpeg_encoder_cmd_i(1 downto 0) <= "11";
when others =>
end case;
when X"48" | X"68" => -- H Hdmi
case cmd is
when X"53" | X"73" => -- Status
status(3) <= '1';
when X"30" => -- Force HDMI 0 to 720p
hdmi_cmd_i(0) <= '0';
uvc_rst_i <= '1';
when X"31" => -- Force HDMI 0 to 1024
hdmi_cmd_i(0) <= '1';
uvc_rst_i <= '1';
when X"32" => -- Force HDMI 1 to 720p
hdmi_cmd_i(1) <= '0';
uvc_rst_i <= '1';
when X"33" => -- Force HDMI 1 to 1024
hdmi_cmd_i(1) <= '1';
uvc_rst_i <= '1';
when others =>
end case;
when X"53" | X"73" => -- S Source Selector
case cmd is -- (1:0 source ) (2 gray/color) (3 inverted/not-inverted) (4:5 blue depth) (6:7 green depth) (8:9 red depth) (10 blue on/off) (11 green on/off) (12 red on/off)
when X"53" | X"73" => -- Status
status(2) <= '1';
when X"55" | X"75" => -- U button force source to HDMI0
if rdy_H(0) = '1' then
selector_cmd_i(1 downto 0) <= "00";
uvc_rst_i <= '1';
end if;
when X"4c" | X"6c" => -- L button force source to HDMI1
if rdy_H(1) = '1' then
selector_cmd_i(1 downto 0) <= "01";
uvc_rst_i <= '1';
end if;
when X"52" | X"72" => -- V button force source to VGA
-- selector_cmd_i(1 downto 0) <= "10";
when X"44" | X"64" => -- D button force source to test pattern
selector_cmd_i(1 downto 0) <= "11";
uvc_rst_i <= '1';
when X"47" | X"67" => -- Froce Gray
selector_cmd_i(2) <= '0';
when X"43" | X"63" => -- Froce Color
selector_cmd_i(2) <= '1';
when X"49" | X"69" => -- Invert Color
selector_cmd_i(3) <= not selector_cmd_i(3);
when X"48" | X"68" => -- Heart Beat On/Off
HB_on_i <= not HB_on_i;
when others =>
end case;
-- RGB (4:5 blue depth) (6:7 green depth) (8:9 red depth) (10 blue on/off) (11 green on/off) (12 red on/off)
when X"52" | X"72" => -- Red
case cmd is
when X"4e" | X"6e" => -- N n (on)
selector_cmd_i(12) <= '1';
when X"46" | X"66" => -- Ff (off)
selector_cmd_i(12) <= '0';
when X"30" =>
selector_cmd_i(9 downto 8) <= "00";
when X"31" =>
selector_cmd_i(9 downto 8) <= "01";
when X"32" =>
selector_cmd_i(9 downto 8) <= "10";
when X"33" =>
selector_cmd_i(9 downto 8) <= "11";
when others =>
end case;
when X"47" | X"67" => -- Green (4:5 blue depth) (6:7 green depth) (8:9 red depth) (10 blue on/off) (11 green on/off) (12 red on/off)
case cmd is
when X"4e" | X"6e" => -- N n (on)
selector_cmd_i(11) <= '1';
when X"46" | X"66" => -- Ff (off)
selector_cmd_i(11) <= '0';
when X"30" =>
selector_cmd_i(7 downto 6) <= "00";
when X"31" =>
selector_cmd_i(7 downto 6) <= "01";
when X"32" =>
selector_cmd_i(7 downto 6) <= "10";
when X"33" =>
selector_cmd_i(7 downto 6) <= "11";
when others =>
end case;
when X"42" | X"62" => -- Blue
case cmd is
when X"4e" | X"6e" => -- N n (on)
selector_cmd_i(10) <= '1';
when X"46" | X"66" => -- Ff (off)
selector_cmd_i(10) <= '0';
when X"30" =>
selector_cmd_i(5 downto 4) <= "00";
when X"31" =>
selector_cmd_i(5 downto 4) <= "01";
when X"32" =>
selector_cmd_i(5 downto 4) <= "10";
when X"33" =>
selector_cmd_i(5 downto 4) <= "11";
when others =>
end case;
when X"44" | X"64" => --Debug
case cmd is
when X"53" | X"73" => --Status
status(4) <= '1';
when others =>
end case;
when others =>
end case; -- case add
end if; -- cmd_en
end if; -- clk
end process;
uart_rd <= uart_rd_s;
uart_ctrl : process(uart_clk, uart_rx_empty, empty_s)
begin
if rst = '1' then
uart_rd_s <= '0';
elsif rising_edge(uart_clk) then
empty_s <= uart_rx_empty;
end if;
if empty_s = '1' and uart_rx_empty = '0' then
uart_rd_s <= '1';
end if;
if empty_s = uart_rx_empty then
uart_rd_s <= '0';
end if;
end process;
fifo_mux: process(usb_or_uart, uart_rd_s, cmd_en, uart_din, cmd_byte, uart_clk, ifclk)
begin
if usb_or_uart = '0' then
fifo_din <= cmd_byte;
fifo_wr <= cmd_en;
fifo_clk <= ifclk;
else
fifo_din <= uart_din;
fifo_wr <= uart_rd_s;
fifo_clk <= uart_clk;
end if;
end process;
cmd <= dout(7 downto 0);
add <= dout(15 downto 8);
cmdfifo_comp : cmdfifo
PORT MAP (
rst => rst,
wr_clk => fifo_clk,
rd_clk => clk,
din => fifo_din,
wr_en => fifo_wr,
rd_en => rd_en,
dout => dout,
full => full,
almost_full => almost_full,
empty => empty,
almost_empty => almost_empty,
valid => valid
);
END ARCHITECTURE;
|
bsd-2-clause
|
rohit91/HDMI2USB
|
ipcore_dir/ddr2ram/user_design/rtl/mcb_soft_calibration.vhd
|
9
|
92176
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: mcb_soft_calibration.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:17:26 $
-- \ \ / \ Date Created: Mon Feb 9 2009
-- \___\/\___\
--
--Device: Spartan6
--Design Name: DDR/DDR2/DDR3/LPDDR
--Purpose: Xilinx reference design for MCB Soft
-- Calibration
--Reference:
--
-- Revision: Date: Comment
-- 1.0: 2/06/09: Initial version for MIG wrapper.
-- 1.1: 2/09/09: moved Max_Value_Previous assignments to be completely inside CASE statement for next-state logic (needed to get it working
-- correctly)
-- 1.2: 2/12/09: Many other changes.
-- 1.3: 2/26/09: Removed section with Max_Value_pre and DQS_COUNT_PREVIOUS_pre, and instead added PREVIOUS_STATE reg and moved assignment to within
-- STATE
-- 1.4: 3/02/09: Removed comments out of sensitivity list of always block to mux SDI, SDO, CS, and ADD.Also added reg declaration for PREVIOUS_STATE
-- 1.5: 3/16/09: Added pll_lock port, and using it to gate reset. Changing RST (except input port) to RST_reg and gating it with pll_lock.
-- 1.6: 6/05/09: Added START_DYN_CAL_PRE with pulse on SYSRST; removed MCB_UIDQCOUNT.
-- 1.7: 6/24/09: Gave RZQ and ZIO each their own unique ADD and SDI nets
-- 2.6: 12/15/09: Changed STATE from 7-bit to 6-bit. Dropped (* FSM_ENCODING="BINARY" *) for STATE. Moved MCB_UICMDEN = 0 from OFF_RZQ_PTERM to
-- RST_DELAY.
-- Changed the "reset" always block so that RST_reg is always set to 1 when the PLL loses lock, and is now held in reset for at least
-- 16 clocks. Added PNSKEW option.
-- 2.7: 12/23/09: Added new states "SKEW" and "MULTIPLY_DIVIDE" to help with timing.
-- 2.8: 01/14/10: Added functionality to allow for SUSPEND. Changed MCB_SYSRST port from wire to reg.
-- 2.9: 02/01/10: More changes to SUSPEND and Reset logic to handle SUSPEND properly. Also - eliminated 2's comp DQS_COUNT_VIRTUAL, and replaced
-- with 8bit TARGET_DQS_DELAY which
-- will track most recnet Max_Value. Eliminated DQS_COUNT_PREVIOUS. Combined DQS_COUNT_INITIAL and DQS_DELAY into DQS_DELAY_INITIAL.
-- Changed DQS_COUNT* to DQS_DELAY*.
-- Changed MCB_SYSRST port back to wire (from reg).
-- 3.0: 02/10/10: Added count_inc and count_dec to add few (4) UI_CLK cycles latency to the INC and DEC signals(to deal with latency on UOREFRSHFLAG)
-- 3.1: 02/23/10: Registered the DONE_SOFTANDHARD_CAL for timing.
-- 3.2: 02/28/10: Corrected the WAIT_SELFREFRESH_EXIT_DQS_CAL logic;
-- 3.3: 03/02/10: Changed PNSKEW to default on (1'b1)
-- 3.4: 03/04/10: Recoded the RST_Reg logic.
-- 3.5: 03/05/10: Changed Result register to be 16-bits. Changed DQS_NUMERATOR/DENOMINATOR values to 3/8 (from 6/16)
-- 3.6 03/10/10: Improvements to Reset logic.
-- 3.7: 04/26/10: Added DDR2 Initialization fix to meet 400 ns wait as outlined in step d) of JEDEC DDR2 spec .
-- 3.8: 05/05/10: Added fixes for the CR# 559092 (updated Mult_Divide function) and 555416 (added IOB attribute to DONE_SOFTANDHARD_CAL).
-- 3.9: 05/24/10: Added 200us Wait logic to control CKE_Train. The 200us Wait counter assumes UI_CLK freq not higher than 100 MHz.
-- 3.10 10/22/10: Fixed PERFORM_START_DYN_CAL_AFTER_SELFREFRESH logic.
-- 3.11 2/14/11: Apply a different skkew for the P and N inputs for the differential LDQS and UDQS signals to provide more noise immunity.
-- 4.1 03/08/12: Fixed SELFREFRESH_MCB_REQ logic. It should not need depend on the SM STATE so that
-- MCB can come out of selfresh mode. SM requires refresh cycle to update the DQS value.
-- 4.2 05/10/12: All P/N terms of input and bidir memory pins are initialized with value of ZERO. TZQINIT_MAXCNT
-- are set to 8 for LPDDR,DDR and DDR2 interface .
-- Keep the UICMDEN in assertion state when SM is in RST_DELAY state so that MCB will not start doing
-- Premable detection until the second deassertion of MCB_SYSRST.
-- End Revision
--**********************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
entity mcb_soft_calibration is
generic (
C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000"; -- DDR3 Minimum delay between resets
SKIP_IN_TERM_CAL : integer := 0; -- provides option to skip the input termination calibration
SKIP_DYNAMIC_CAL : integer := 0; -- provides option to skip the dynamic delay calibration
SKIP_DYN_IN_TERM : integer := 1; -- provides option to skip the input termination calibration
C_MC_CALIBRATION_MODE : string := "CALIBRATION"; -- if set to CALIBRATION will reset DQS IDELAY to DQS_NUMERATOR/DQS_DENOMINATOR local_param value
-- if set to NOCALIBRATION then defaults to hard cal blocks setting of C_MC_CALBRATION_DELAY
-- (Quarter, etc)
C_SIMULATION : string := "FALSE"; -- Tells us whether the design is being simulated or implemented
C_MEM_TYPE : string := "DDR"
);
port (
UI_CLK : in std_logic; -- main clock input for logic and IODRP CLK pins. At top level, this should also connect to IODRP2_MCB
-- CLK pins
RST : in std_logic; -- main system reset for both the Soft Calibration block - also will act as a passthrough to MCB's SYSRST
DONE_SOFTANDHARD_CAL : out std_logic; -- active high flag signals soft calibration of input delays is complete and MCB_UODONECAL is high (MCB
-- hard calib complete)
PLL_LOCK : in std_logic; -- Lock signal from PLL
SELFREFRESH_REQ : in std_logic;
SELFREFRESH_MCB_MODE : in std_logic;
SELFREFRESH_MCB_REQ : out std_logic;
SELFREFRESH_MODE : out std_logic;
IODRP_ADD : out std_logic; -- IODRP ADD port
IODRP_SDI : out std_logic; -- IODRP SDI port
RZQ_IN : in std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
RZQ_IODRP_SDO : in std_logic; -- RZQ IODRP's SDO port
RZQ_IODRP_CS : out std_logic := '0'; -- RZQ IODRP's CS port
ZIO_IN : in std_logic; -- Z-stated IO pin - garanteed not to be driven externally
ZIO_IODRP_SDO : in std_logic; -- ZIO IODRP's SDO port
ZIO_IODRP_CS : out std_logic := '0'; -- ZIO IODRP's CS port
MCB_UIADD : out std_logic; -- to MCB's UIADD port
MCB_UISDI : out std_logic; -- to MCB's UISDI port
MCB_UOSDO : in std_logic; -- from MCB's UOSDO port (User output SDO)
MCB_UODONECAL : in std_logic; -- indicates when MCB hard calibration process is complete
MCB_UOREFRSHFLAG : in std_logic; -- high during refresh cycle and time when MCB is innactive
MCB_UICS : out std_logic; -- to MCB's UICS port (User Input CS)
MCB_UIDRPUPDATE : out std_logic := '1'; -- MCB's UIDRPUPDATE port (gets passed to IODRP2_MCB's MEMUPDATE port: this controls shadow latch used
-- during IODRP2_MCB writes). Currently just trasnparent
MCB_UIBROADCAST : out std_logic; -- only to MCB's UIBROADCAST port (User Input BROADCAST - gets passed to IODRP2_MCB's BKST port)
MCB_UIADDR : out std_logic_vector(4 downto 0) := "00000"; -- to MCB's UIADDR port (gets passed to IODRP2_MCB's AUXADDR port
MCB_UICMDEN : out std_logic := '1'; -- set to 1 to take control of UI interface - removes control from internal calib block
MCB_UIDONECAL : out std_logic := '0'; -- set to 0 to "tell" controller that it's still in a calibrate state
MCB_UIDQLOWERDEC : out std_logic ;
MCB_UIDQLOWERINC : out std_logic ;
MCB_UIDQUPPERDEC : out std_logic ;
MCB_UIDQUPPERINC : out std_logic ;
MCB_UILDQSDEC : out std_logic := '0';
MCB_UILDQSINC : out std_logic := '0';
MCB_UIREAD : out std_logic; -- enables read w/o writing by turning on a SDO->SDI loopback inside the IODRP2_MCBs (doesn't exist in
-- regular IODRP2). IODRPCTRLR_R_WB becomes don't-care.
MCB_UIUDQSDEC : out std_logic := '0';
MCB_UIUDQSINC : out std_logic := '0';
MCB_RECAL : out std_logic ; -- future hook to drive MCB's RECAL pin - initiates a hard re-calibration sequence when high
MCB_UICMD : out std_logic;
MCB_UICMDIN : out std_logic;
MCB_UIDQCOUNT : out std_logic_vector(3 downto 0);
MCB_UODATA : in std_logic_vector(7 downto 0);
MCB_UODATAVALID : in std_logic;
MCB_UOCMDREADY : in std_logic;
MCB_UO_CAL_START : in std_logic;
MCB_SYSRST : out std_logic; -- drives the MCB's SYSRST pin - the main reset for MCB
Max_Value : out std_logic_vector(7 downto 0);
CKE_Train : out std_logic
);
end entity mcb_soft_calibration;
architecture trans of mcb_soft_calibration is
constant IOI_DQ0 : std_logic_vector(4 downto 0) := ("0000" & '1');
constant IOI_DQ1 : std_logic_vector(4 downto 0) := ("0000" & '0');
constant IOI_DQ2 : std_logic_vector(4 downto 0) := ("0001" & '1');
constant IOI_DQ3 : std_logic_vector(4 downto 0) := ("0001" & '0');
constant IOI_DQ4 : std_logic_vector(4 downto 0) := ("0010" & '1');
constant IOI_DQ5 : std_logic_vector(4 downto 0) := ("0010" & '0');
constant IOI_DQ6 : std_logic_vector(4 downto 0) := ("0011" & '1');
constant IOI_DQ7 : std_logic_vector(4 downto 0) := ("0011" & '0');
constant IOI_DQ8 : std_logic_vector(4 downto 0) := ("0100" & '1');
constant IOI_DQ9 : std_logic_vector(4 downto 0) := ("0100" & '0');
constant IOI_DQ10 : std_logic_vector(4 downto 0) := ("0101" & '1');
constant IOI_DQ11 : std_logic_vector(4 downto 0) := ("0101" & '0');
constant IOI_DQ12 : std_logic_vector(4 downto 0) := ("0110" & '1');
constant IOI_DQ13 : std_logic_vector(4 downto 0) := ("0110" & '0');
constant IOI_DQ14 : std_logic_vector(4 downto 0) := ("0111" & '1');
constant IOI_DQ15 : std_logic_vector(4 downto 0) := ("0111" & '0');
constant IOI_UDM : std_logic_vector(4 downto 0) := ("1000" & '1');
constant IOI_LDM : std_logic_vector(4 downto 0) := ("1000" & '0');
constant IOI_CK_P : std_logic_vector(4 downto 0) := ("1001" & '1');
constant IOI_CK_N : std_logic_vector(4 downto 0) := ("1001" & '0');
constant IOI_RESET : std_logic_vector(4 downto 0) := ("1010" & '1');
constant IOI_A11 : std_logic_vector(4 downto 0) := ("1010" & '0');
constant IOI_WE : std_logic_vector(4 downto 0) := ("1011" & '1');
constant IOI_BA2 : std_logic_vector(4 downto 0) := ("1011" & '0');
constant IOI_BA0 : std_logic_vector(4 downto 0) := ("1100" & '1');
constant IOI_BA1 : std_logic_vector(4 downto 0) := ("1100" & '0');
constant IOI_RASN : std_logic_vector(4 downto 0) := ("1101" & '1');
constant IOI_CASN : std_logic_vector(4 downto 0) := ("1101" & '0');
constant IOI_UDQS_CLK : std_logic_vector(4 downto 0) := ("1110" & '1');
constant IOI_UDQS_PIN : std_logic_vector(4 downto 0) := ("1110" & '0');
constant IOI_LDQS_CLK : std_logic_vector(4 downto 0) := ("1111" & '1');
constant IOI_LDQS_PIN : std_logic_vector(4 downto 0) := ("1111" & '0');
constant START : std_logic_vector(5 downto 0) := "000000";
constant LOAD_RZQ_NTERM : std_logic_vector(5 downto 0) := "000001";
constant WAIT1 : std_logic_vector(5 downto 0) := "000010";
constant LOAD_RZQ_PTERM : std_logic_vector(5 downto 0) := "000011";
constant WAIT2 : std_logic_vector(5 downto 0) := "000100";
constant INC_PTERM : std_logic_vector(5 downto 0) := "000101";
constant MULTIPLY_DIVIDE : std_logic_vector(5 downto 0) := "000110";
constant LOAD_ZIO_PTERM : std_logic_vector(5 downto 0) := "000111";
constant WAIT3 : std_logic_vector(5 downto 0) := "001000";
constant LOAD_ZIO_NTERM : std_logic_vector(5 downto 0) := "001001";
constant WAIT4 : std_logic_vector(5 downto 0) := "001010";
constant INC_NTERM : std_logic_vector(5 downto 0) := "001011";
constant SKEW : std_logic_vector(5 downto 0) := "001100";
constant WAIT_FOR_START_BROADCAST : std_logic_vector(5 downto 0) := "001101";
constant BROADCAST_PTERM : std_logic_vector(5 downto 0) := "001110";
constant WAIT5 : std_logic_vector(5 downto 0) := "001111";
constant BROADCAST_NTERM : std_logic_vector(5 downto 0) := "010000";
constant WAIT6 : std_logic_vector(5 downto 0) := "010001";
constant LDQS_CLK_WRITE_P_TERM : std_logic_vector(5 downto 0) := "010010";
constant LDQS_CLK_P_TERM_WAIT : std_logic_vector(5 downto 0) := "010011";
constant LDQS_CLK_WRITE_N_TERM : std_logic_vector(5 downto 0) := "010100";
constant LDQS_CLK_N_TERM_WAIT : std_logic_vector(5 downto 0) := "010101";
constant LDQS_PIN_WRITE_P_TERM : std_logic_vector(5 downto 0) := "010110";
constant LDQS_PIN_P_TERM_WAIT : std_logic_vector(5 downto 0) := "010111";
constant LDQS_PIN_WRITE_N_TERM : std_logic_vector(5 downto 0) := "011000";
constant LDQS_PIN_N_TERM_WAIT : std_logic_vector(5 downto 0) := "011001";
constant UDQS_CLK_WRITE_P_TERM : std_logic_vector(5 downto 0) := "011010";
constant UDQS_CLK_P_TERM_WAIT : std_logic_vector(5 downto 0) := "011011";
constant UDQS_CLK_WRITE_N_TERM : std_logic_vector(5 downto 0) := "011100";
constant UDQS_CLK_N_TERM_WAIT : std_logic_vector(5 downto 0) := "011101";
constant UDQS_PIN_WRITE_P_TERM : std_logic_vector(5 downto 0) := "011110";
constant UDQS_PIN_P_TERM_WAIT : std_logic_vector(5 downto 0) := "011111";
constant UDQS_PIN_WRITE_N_TERM : std_logic_vector(5 downto 0) := "100000";
constant UDQS_PIN_N_TERM_WAIT : std_logic_vector(5 downto 0) := "100001";
constant OFF_RZQ_PTERM : std_logic_vector(5 downto 0) := "100010";
constant WAIT7 : std_logic_vector(5 downto 0) := "100011";
constant OFF_ZIO_NTERM : std_logic_vector(5 downto 0) := "100100";
constant WAIT8 : std_logic_vector(5 downto 0) := "100101";
constant RST_DELAY : std_logic_vector(5 downto 0) := "100110";
constant START_DYN_CAL_PRE : std_logic_vector(5 downto 0) := "100111";
constant WAIT_FOR_UODONE : std_logic_vector(5 downto 0) := "101000";
constant LDQS_WRITE_POS_INDELAY : std_logic_vector(5 downto 0) := "101001";
constant LDQS_WAIT1 : std_logic_vector(5 downto 0) := "101010";
constant LDQS_WRITE_NEG_INDELAY : std_logic_vector(5 downto 0) := "101011";
constant LDQS_WAIT2 : std_logic_vector(5 downto 0) := "101100";
constant UDQS_WRITE_POS_INDELAY : std_logic_vector(5 downto 0) := "101101";
constant UDQS_WAIT1 : std_logic_vector(5 downto 0) := "101110";
constant UDQS_WRITE_NEG_INDELAY : std_logic_vector(5 downto 0) := "101111";
constant UDQS_WAIT2 : std_logic_vector(5 downto 0) := "110000";
constant START_DYN_CAL : std_logic_vector(5 downto 0) := "110001";
constant WRITE_CALIBRATE : std_logic_vector(5 downto 0) := "110010";
constant WAIT9 : std_logic_vector(5 downto 0) := "110011";
constant READ_MAX_VALUE : std_logic_vector(5 downto 0) := "110100";
constant WAIT10 : std_logic_vector(5 downto 0) := "110101";
constant ANALYZE_MAX_VALUE : std_logic_vector(5 downto 0) := "110110";
constant FIRST_DYN_CAL : std_logic_vector(5 downto 0) := "110111";
constant INCREMENT : std_logic_vector(5 downto 0) := "111000";
constant DECREMENT : std_logic_vector(5 downto 0) := "111001";
constant DONE : std_logic_vector(5 downto 0) := "111010";
--constant INCREMENT_TA : std_logic_vector(5 downto 0) := "111011";
constant RZQ : std_logic_vector(1 downto 0) := "00";
constant ZIO : std_logic_vector(1 downto 0) := "01";
constant MCB_PORT : std_logic_vector(1 downto 0) := "11";
constant WRITE_MODE : std_logic := '0';
constant READ_MODE : std_logic := '1';
-- IOI Registers
constant NoOp : std_logic_vector(7 downto 0) := "00000000";
constant DelayControl : std_logic_vector(7 downto 0) := "00000001";
constant PosEdgeInDly : std_logic_vector(7 downto 0) := "00000010";
constant NegEdgeInDly : std_logic_vector(7 downto 0) := "00000011";
constant PosEdgeOutDly : std_logic_vector(7 downto 0) := "00000100";
constant NegEdgeOutDly : std_logic_vector(7 downto 0) := "00000101";
constant MiscCtl1 : std_logic_vector(7 downto 0) := "00000110";
constant MiscCtl2 : std_logic_vector(7 downto 0) := "00000111";
constant MaxValue : std_logic_vector(7 downto 0) := "00001000";
-- IOB Registers
constant PDrive : std_logic_vector(7 downto 0) := "10000000";
constant PTerm : std_logic_vector(7 downto 0) := "10000001";
constant NDrive : std_logic_vector(7 downto 0) := "10000010";
constant NTerm : std_logic_vector(7 downto 0) := "10000011";
constant SlewRateCtl : std_logic_vector(7 downto 0) := "10000100";
constant LVDSControl : std_logic_vector(7 downto 0) := "10000101";
constant MiscControl : std_logic_vector(7 downto 0) := "10000110";
constant InputControl : std_logic_vector(7 downto 0) := "10000111";
constant TestReadback : std_logic_vector(7 downto 0) := "10001000";
-- No multi/divide is required when a 55 ohm resister is used on RZQ
-- localparam MULT = 1;
-- localparam DIV = 1;
-- use 7/4 scaling factor when the 100 ohm RZQ is used
constant MULT : integer := 7;
constant DIV : integer := 4;
constant PNSKEW : std_logic := '1'; -- Default is 1'b1. Change to 1'b0 if PSKEW and NSKEW are not required
constant PNSKEWDQS : std_logic := '1';
constant MULT_S : integer := 9;
constant DIV_S : integer := 8;
constant MULT_W : integer := 7;
constant DIV_W : integer := 8;
constant DQS_NUMERATOR : integer := 3;
constant DQS_DENOMINATOR : integer := 8;
constant INCDEC_THRESHOLD : std_logic_vector(7 downto 0) := X"03";
-- parameter for the threshold which triggers an inc/dec to occur. 2 for half, 4 for quarter,
-- 3 for three eighths
constant RST_CNT : std_logic_vector(9 downto 0) := "0000010000";
constant IN_TERM_PASS : std_logic := '0';
constant DYN_CAL_PASS : std_logic := '1';
function TZQINIT_MAXCNT_W return std_logic_vector is
variable temp : std_logic_vector(9 downto 0) := (others=>'0');
begin
if (C_MEM_TYPE = "DDR3") then
temp := C_MEM_TZQINIT_MAXCNT + RST_CNT;
else
temp := 8 + RST_CNT;
end if;
return temp(9 downto 0);
end function;
constant TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := TZQINIT_MAXCNT_W;
component iodrp_mcb_controller is
port (
memcell_address : in std_logic_vector(7 downto 0);
write_data : in std_logic_vector(7 downto 0);
read_data : out std_logic_vector(7 downto 0);
rd_not_write : in std_logic;
cmd_valid : in std_logic;
rdy_busy_n : out std_logic;
use_broadcast : in std_logic;
drp_ioi_addr : in std_logic_vector(4 downto 0);
sync_rst : in std_logic;
DRP_CLK : in std_logic;
DRP_CS : out std_logic;
DRP_SDI : out std_logic;
DRP_ADD : out std_logic;
DRP_BKST : out std_logic;
DRP_SDO : in std_logic;
MCB_UIREAD : out std_logic
);
end component;
component iodrp_controller is
port (
memcell_address : in std_logic_vector(7 downto 0);
write_data : in std_logic_vector(7 downto 0);
read_data : out std_logic_vector(7 downto 0);
rd_not_write : in std_logic;
cmd_valid : in std_logic;
rdy_busy_n : out std_logic;
use_broadcast : in std_logic;
sync_rst : in std_logic;
DRP_CLK : in std_logic;
DRP_CS : out std_logic;
DRP_SDI : out std_logic;
DRP_ADD : out std_logic;
DRP_BKST : out std_logic;
DRP_SDO : in std_logic
);
end component;
signal P_Term : std_logic_vector(5 downto 0) := "000000";
signal N_Term : std_logic_vector(6 downto 0) := "0000000";
signal P_Term_s : std_logic_vector(5 downto 0) := "000000";
signal N_Term_s : std_logic_vector(6 downto 0) := "0000000";
signal P_Term_w : std_logic_vector(5 downto 0) := "000000";
signal N_Term_w : std_logic_vector(6 downto 0) := "0000000";
signal P_Term_Prev : std_logic_vector(5 downto 0) := "000000";
signal N_Term_Prev : std_logic_vector(6 downto 0) := "0000000";
signal STATE : std_logic_vector(5 downto 0);
signal IODRPCTRLR_MEMCELL_ADDR : std_logic_vector(7 downto 0);
signal IODRPCTRLR_WRITE_DATA : std_logic_vector(7 downto 0);
signal Active_IODRP : std_logic_vector(1 downto 0);
signal IODRPCTRLR_R_WB : std_logic := '0';
signal IODRPCTRLR_CMD_VALID : std_logic := '0';
signal IODRPCTRLR_USE_BKST : std_logic := '0';
signal MCB_CMD_VALID : std_logic := '0';
signal MCB_USE_BKST : std_logic := '0';
signal Pre_SYSRST : std_logic := '1'; -- internally generated reset which will OR with RST input to drive MCB's
-- SYSRST pin (MCB_SYSRST)
signal IODRP_SDO : std_logic;
signal Max_Value_Previous : std_logic_vector(7 downto 0) := "00000000";
signal count : std_logic_vector(5 downto 0) := "000000"; -- counter for adding 18 extra clock cycles after setting Calibrate bit
signal counter_en : std_logic := '0'; -- counter enable for "count"
signal First_Dyn_Cal_Done : std_logic := '0'; -- flag - high after the very first dynamic calibration is done
signal START_BROADCAST : std_logic ; -- Trigger to start Broadcast to IODRP2_MCBs to set Input Impedance -
-- state machine will wait for this to be high
signal DQS_DELAY_INITIAL : std_logic_vector(7 downto 0) := "00000000";
signal DQS_DELAY : std_logic_vector(7 downto 0); -- contains the latest values written to LDQS and UDQS Input Delays
signal TARGET_DQS_DELAY : std_logic_vector(7 downto 0); -- used to track the target for DQS input delays - only gets updated if
-- the Max Value changes by more than the threshold
signal counter_inc : std_logic_vector(7 downto 0); -- used to delay Inc signal by several ui_clk cycles (to deal with
-- latency on UOREFRSHFLAG)
signal counter_dec : std_logic_vector(7 downto 0); -- used to delay Dec signal by several ui_clk cycles (to deal with
-- latency on UOREFRSHFLAG)
signal IODRPCTRLR_READ_DATA : std_logic_vector(7 downto 0);
signal IODRPCTRLR_RDY_BUSY_N : std_logic;
signal IODRP_CS : std_logic;
signal MCB_READ_DATA : std_logic_vector(7 downto 0);
signal RST_reg : std_logic;
signal Block_Reset : std_logic;
signal MCB_UODATAVALID_U : std_logic;
signal Inc_Dec_REFRSH_Flag : std_logic_vector(2 downto 0); -- 3-bit flag to show:Inc is needed, Dec needed, refresh cycle taking place
signal Max_Value_Delta_Up : std_logic_vector(7 downto 0); -- tracks amount latest Max Value has gone up from previous Max Value read
signal Half_MV_DU : std_logic_vector(7 downto 0); -- half of Max_Value_Delta_Up
signal Max_Value_Delta_Dn : std_logic_vector(7 downto 0); -- tracks amount latest Max Value has gone down from previous Max Value read
signal Half_MV_DD : std_logic_vector(7 downto 0); -- half of Max_Value_Delta_Dn
signal RstCounter : std_logic_vector(9 downto 0) := (others => '0');
signal rst_tmp : std_logic;
signal LastPass_DynCal : std_logic;
signal First_In_Term_Done : std_logic;
signal Inc_Flag : std_logic; -- flag to increment Dynamic Delay
signal Dec_Flag : std_logic; -- flag to decrement Dynamic Delay
signal CALMODE_EQ_CALIBRATION : std_logic; -- will calculate and set the DQS input delays if C_MC_CALIBRATION_MODE
-- parameter = "CALIBRATION"
signal DQS_DELAY_LOWER_LIMIT : std_logic_vector(7 downto 0); -- Lower limit for DQS input delays
signal DQS_DELAY_UPPER_LIMIT : std_logic_vector(7 downto 0); -- Upper limit for DQS input delays
signal SKIP_DYN_IN_TERMINATION : std_logic; -- wire to allow skipping dynamic input termination if either the
-- one-time or dynamic parameters are 1
signal SKIP_DYNAMIC_DQS_CAL : std_logic; -- wire allowing skipping dynamic DQS delay calibration if either
-- SKIP_DYNIMIC_CAL=1, or if C_MC_CALIBRATION_MODE=NOCALIBRATION
signal Quarter_Max_Value : std_logic_vector(7 downto 0);
signal Half_Max_Value : std_logic_vector(7 downto 0);
signal PLL_LOCK_R1 : std_logic;
signal PLL_LOCK_R2 : std_logic;
signal MCB_RDY_BUSY_N : std_logic;
signal SELFREFRESH_REQ_R1 : std_logic;
signal SELFREFRESH_REQ_R2 : std_logic;
signal SELFREFRESH_REQ_R3 : std_logic;
signal SELFREFRESH_MCB_MODE_R1 : std_logic;
signal SELFREFRESH_MCB_MODE_R2 : std_logic;
signal SELFREFRESH_MCB_MODE_R3 : std_logic;
signal WAIT_SELFREFRESH_EXIT_DQS_CAL : std_logic;
signal PERFORM_START_DYN_CAL_AFTER_SELFREFRESH : std_logic;
signal START_DYN_CAL_STATE_R1 : std_logic;
signal PERFORM_START_DYN_CAL_AFTER_SELFREFRESH_R1 : std_logic;
-- Declare intermediate signals for referenced outputs
signal IODRP_ADD_xilinx0 : std_logic;
signal IODRP_SDI_xilinx1 : std_logic;
signal MCB_UIADD_xilinx2 : std_logic;
signal MCB_UISDI_xilinx11 : std_logic;
signal MCB_UICS_xilinx6 : std_logic;
signal MCB_UIBROADCAST_xilinx4 : std_logic;
signal MCB_UIADDR_int : std_logic_vector(4 downto 0);
signal MCB_UIDONECAL_xilinx7 : std_logic;
signal MCB_UIREAD_xilinx10 : std_logic;
signal SELFREFRESH_MODE_xilinx11 : std_logic;
signal Max_Value_int : std_logic_vector(7 downto 0);
signal Rst_condition1 : std_logic;
--signal Rst_condition2 : std_logic;
signal non_violating_rst : std_logic;
signal WAIT_200us_COUNTER : std_logic_vector(15 downto 0);
signal WaitTimer : std_logic_vector(7 downto 0);
signal WarmEnough : std_logic;
signal WaitCountEnable : std_logic;
signal State_Start_DynCal_R1 : std_logic;
signal State_Start_DynCal : std_logic;
signal pre_sysrst_minpulse_width_ok : std_logic;
signal pre_sysrst_cnt : std_logic_vector(3 downto 0);
-- This function multiplies by a constant MULT and then divides by the DIV constant
function Mult_Divide (Input : std_logic_vector(7 downto 0); MULT : integer ; DIV : integer ) return std_logic_vector is
variable Result : integer := 0;
variable temp : std_logic_vector(14 downto 0) := "000000000000000";
begin
for count in 0 to (MULT-1) loop
temp := temp + ("0000000" & Input);
end loop;
Result := (to_integer(unsigned(temp))) / (DIV);
temp := std_logic_vector(to_unsigned(Result,15));
return temp(7 downto 0);
end function Mult_Divide;
attribute syn_preserve : boolean;
attribute syn_preserve of P_Term : signal is TRUE;
attribute syn_preserve of N_Term : signal is TRUE;
attribute syn_preserve of P_Term_s : signal is TRUE;
attribute syn_preserve of N_Term_s : signal is TRUE;
attribute syn_preserve of P_Term_w : signal is TRUE;
attribute syn_preserve of N_Term_w : signal is TRUE;
attribute syn_preserve of P_Term_Prev : signal is TRUE;
attribute syn_preserve of N_Term_Prev : signal is TRUE;
attribute syn_preserve of IODRPCTRLR_MEMCELL_ADDR : signal is TRUE;
attribute syn_preserve of IODRPCTRLR_WRITE_DATA : signal is TRUE;
attribute syn_preserve of Max_Value_Previous : signal is TRUE;
attribute syn_preserve of DQS_DELAY_INITIAL : signal is TRUE;
attribute iob : string;
attribute iob of DONE_SOFTANDHARD_CAL : signal is "FALSE";
begin
-- move the default assignment here to make FORMALITY happy.
START_BROADCAST <= '1';
MCB_RECAL <= '0';
MCB_UIDQLOWERDEC <= '0';
MCB_UIADDR <= MCB_UIADDR_int;
MCB_UIDQLOWERINC <= '0';
MCB_UIDQUPPERDEC <= '0';
MCB_UIDQUPPERINC <= '0';
Max_Value <= Max_Value_int;
-- Drive referenced outputs
IODRP_ADD <= IODRP_ADD_xilinx0;
IODRP_SDI <= IODRP_SDI_xilinx1;
MCB_UIADD <= MCB_UIADD_xilinx2;
MCB_UISDI <= MCB_UISDI_xilinx11;
MCB_UICS <= MCB_UICS_xilinx6;
MCB_UIBROADCAST <= MCB_UIBROADCAST_xilinx4;
MCB_UIDONECAL <= MCB_UIDONECAL_xilinx7;
MCB_UIREAD <= MCB_UIREAD_xilinx10;
SELFREFRESH_MODE <= SELFREFRESH_MODE_xilinx11;
Inc_Dec_REFRSH_Flag <= (Inc_Flag & Dec_Flag & MCB_UOREFRSHFLAG);
Max_Value_Delta_Up <= Max_Value_int - Max_Value_Previous;
Half_MV_DU <= ('0' & Max_Value_Delta_Up(7 downto 1));
Max_Value_Delta_Dn <= Max_Value_Previous - Max_Value_int;
Half_MV_DD <= ('0' & Max_Value_Delta_Dn(7 downto 1));
CALMODE_EQ_CALIBRATION <= '1' when (C_MC_CALIBRATION_MODE = "CALIBRATION") else '0'; -- will calculate and set the DQS input delays if = 1'b1
Half_Max_Value <= ('0' & Max_Value_int(7 downto 1));
Quarter_Max_Value <= ("00" & Max_Value_int(7 downto 2));
DQS_DELAY_LOWER_LIMIT <= Quarter_Max_Value; -- limit for DQS_DELAY for decrements; could optionally be assigned to any 8-bit hex value here
DQS_DELAY_UPPER_LIMIT <= Half_Max_Value; -- limit for DQS_DELAY for increments; could optionally be assigned to any 8-bit hex value here
SKIP_DYN_IN_TERMINATION <= '1' when ((SKIP_DYN_IN_TERM = 1) or (SKIP_IN_TERM_CAL = 1)) else '0';
-- skip dynamic input termination if either the one-time or dynamic parameters are 1
SKIP_DYNAMIC_DQS_CAL <= '1' when ((CALMODE_EQ_CALIBRATION = '0') or (SKIP_DYNAMIC_CAL = 1)) else '0';
-- skip dynamic DQS delay calibration if either SKIP_DYNAMIC_CAL=1, or if C_MC_CALIBRATION_MODE=NOCALIBRATION
process (UI_CLK)
begin
if (UI_CLK'event and UI_CLK = '1') then
if ((DQS_DELAY_INITIAL /= X"00") or (STATE = DONE)) then
DONE_SOFTANDHARD_CAL <= MCB_UODONECAL; -- high when either DQS input delays initialized, or STATE=DONE and UODONECAL high
else
DONE_SOFTANDHARD_CAL <= '0';
end if;
end if;
end process;
iodrp_controller_inst : iodrp_controller
port map (
memcell_address => IODRPCTRLR_MEMCELL_ADDR,
write_data => IODRPCTRLR_WRITE_DATA,
read_data => IODRPCTRLR_READ_DATA,
rd_not_write => IODRPCTRLR_R_WB,
cmd_valid => IODRPCTRLR_CMD_VALID,
rdy_busy_n => IODRPCTRLR_RDY_BUSY_N,
use_broadcast => '0',
sync_rst => RST_reg,
DRP_CLK => UI_CLK,
DRP_CS => IODRP_CS,
DRP_SDI => IODRP_SDI_xilinx1,
DRP_ADD => IODRP_ADD_xilinx0,
DRP_SDO => IODRP_SDO,
DRP_BKST => open
);
iodrp_mcb_controller_inst : iodrp_mcb_controller
port map (
memcell_address => IODRPCTRLR_MEMCELL_ADDR,
write_data => IODRPCTRLR_WRITE_DATA,
read_data => MCB_READ_DATA,
rd_not_write => IODRPCTRLR_R_WB,
cmd_valid => MCB_CMD_VALID,
rdy_busy_n => MCB_RDY_BUSY_N,
use_broadcast => MCB_USE_BKST,
drp_ioi_addr => MCB_UIADDR_int,
sync_rst => RST_reg,
DRP_CLK => UI_CLK,
DRP_CS => MCB_UICS_xilinx6,
DRP_SDI => MCB_UISDI_xilinx11,
DRP_ADD => MCB_UIADD_xilinx2,
DRP_BKST => MCB_UIBROADCAST_xilinx4,
DRP_SDO => MCB_UOSDO,
MCB_UIREAD => MCB_UIREAD_xilinx10
);
process (UI_CLK, RST) begin
if (RST = '1') then
if (C_SIMULATION = "TRUE") then
WAIT_200us_COUNTER <= X"7FF0";
else
WAIT_200us_COUNTER <= (others => '0');
end if;
elsif (UI_CLK'event and UI_CLK = '1') then
if (WAIT_200us_COUNTER(15) = '1') then
WAIT_200us_COUNTER <= WAIT_200us_COUNTER;
else
WAIT_200us_COUNTER <= WAIT_200us_COUNTER + '1';
end if;
end if;
end process;
-- init_sequence_skip: if (C_SIMULATION = "TRUE") generate
-- WAIT_200us_COUNTER <= X"FFFF";
-- process
-- begin
-- report "The 200 us wait period required before CKE goes active has been skipped in Simulation";
-- wait;
-- end process;
-- end generate;
gen_CKE_Train_a: if (C_MEM_TYPE = "DDR2") generate
process (UI_CLK, RST) begin
if (RST = '1') then
CKE_Train <= '0';
elsif (UI_CLK'event and UI_CLK = '1') then
if (STATE = WAIT_FOR_UODONE and MCB_UODONECAL = '1') then
CKE_Train <= '0';
elsif (WAIT_200us_COUNTER(15) = '1' and MCB_UODONECAL = '0') then
CKE_Train <= '1';
else
CKE_Train <= '0';
end if;
end if;
end process;
end generate ;
gen_CKE_Train_b: if (not(C_MEM_TYPE = "DDR2")) generate
process (UI_CLK) begin
if (UI_CLK'event and UI_CLK = '1') then
CKE_Train <= '0';
end if;
end process;
end generate ;
--********************************************
-- PLL_LOCK and RST signals
--********************************************
--MCB_SYSRST <= Pre_SYSRST or RST_reg; -- Pre_SYSRST is generated from the STATE state machine, and is OR'd with RST_reg input to drive MCB's
-- SYSRST pin (MCB_SYSRST)
rst_tmp <= not(SELFREFRESH_MODE_xilinx11) and not(PLL_LOCK_R2); -- rst_tmp becomes 1 if you lose Lock and the device is not in SUSPEND
process (UI_CLK, RST) begin
if (RST = '1') then
--Block_Reset <= '0';
--RstCounter <= (others => '0');
--elsif (UI_CLK'event and UI_CLK = '1') then
-- if (rst_tmp = '1') then -- this is to deal with not allowing the user-reset "RST" to violate TZQINIT_MAXCNT (min time between resets to DDR3)
Block_Reset <= '0';
RstCounter <= (others => '0');
elsif (UI_CLK'event and UI_CLK = '1') then
Block_Reset <= '0'; -- default to allow STATE to move out of RST_DELAY state
if (Pre_SYSRST = '1') then
RstCounter <= RST_CNT; -- whenever STATE wants to reset the MCB, set RstCounter to h10
else
if (RstCounter < TZQINIT_MAXCNT) then -- if RstCounter is less than d512 than this will execute
Block_Reset <= '1'; -- STATE won't exit RST_DELAY state
RstCounter <= RstCounter + "1"; -- and Rst_Counter increments
end if;
end if;
end if;
--end if;
end process;
-- Rst_contidtion1 is to make sure RESET will not happen again within TZQINIT_MAXCNT
non_violating_rst <= RST and Rst_condition1;
MCB_SYSRST <= Pre_SYSRST;
process (UI_CLK) begin
if (UI_CLK'event and UI_CLK = '1') then
if (RstCounter >= TZQINIT_MAXCNT) then
Rst_condition1 <= '1';
else
Rst_condition1 <= '0';
end if;
end if;
end process;
-- -- non_violating_rst asserts whenever (system-level reset) RST is asserted but must be after TZQINIT_MAXCNT is reached (min-time between resets for DDR3)
-- -- After power stablizes, we will hold MCB in reset state for at least 200us before beginning initialization process.
-- -- If the PLL loses lock during normal operation, no ui_clk will be present because mcb_drp_clk is from a BUFGCE which
-- is gated by pll's lock signal. When the PLL locks again, the RST_reg stays asserted for at least 200 us which
-- will cause MCB to reset and reinitialize the memory afterwards.
-- -- During SUSPEND operation, the PLL will lose lock but non_violating_rst remains low (de-asserted) and WAIT_200us_COUNTER stays at
-- its terminal count. The PLL_LOCK input does not come direct from PLL, rather it is driven by gated_pll_lock from mcb_raw_wrapper module
-- The gated_pll_lock in the mcb_raw_wrapper does not de-assert during SUSPEND operation, hence PLL_LOCK will not de-assert, and the soft calibration
-- state machine will not reset during SUSPEND.
-- -- RST_reg is the control signal that resets the mcb_soft_calibration's State Machine. The MCB_SYSRST is now equal to
-- Pre_SYSRST. When State Machine is performing "INPUT Termination Calibration", it holds the MCB in reset by assertign MCB_SYSRST.
-- It will deassert the MCB_SYSRST so that it can grab the bus to broadcast the P and N term value to all of the DQ pins. Once the calibrated INPUT
-- termination is set, the State Machine will issue another short MCB_SYSRST so that MCB will use the tuned input termination during DQS preamble calibration.
--process (UI_CLK) begin
-- if (UI_CLK'event and UI_CLK = '1') then
--
-- if (RstCounter < RST_CNT) then
-- Rst_condition2 <= '1';
-- else
-- Rst_condition2 <= '0';
-- end if;
-- end if;
--end process;
process (UI_CLK, non_violating_rst) begin
if (non_violating_rst = '1') then
RST_reg <= '1'; -- STATE and MCB_SYSRST will both be reset if you lose lock when the device is not in SUSPEND
elsif (UI_CLK'event and UI_CLK = '1') then
if (WAIT_200us_COUNTER(15) = '0') then
RST_reg <= '1';
else
--RST_reg <= Rst_condition2 or rst_tmp; -- insures RST_reg is at least h10 pulses long
RST_reg <= rst_tmp; -- insures RST_reg is at least h10 pulses long
end if;
end if;
end process;
--*************************************************************
-- Stretching the pre_sysrst to satisfy the minimum pulse width
--*************************************************************
process (UI_CLK) begin
if (UI_CLK'event and UI_CLK = '1') then
if (STATE = START_DYN_CAL_PRE) then
pre_sysrst_cnt <= pre_sysrst_cnt + '1';
else
pre_sysrst_cnt <= (others=>'0');
end if;
end if;
end process;
pre_sysrst_minpulse_width_ok <= pre_sysrst_cnt(3);
--********************************************
-- SUSPEND Logic
--********************************************
process (UI_CLK,RST)
begin
if (RST = '1') then
SELFREFRESH_MCB_MODE_R1 <= '0';
SELFREFRESH_MCB_MODE_R2 <= '0';
SELFREFRESH_MCB_MODE_R3 <= '0';
SELFREFRESH_REQ_R1 <= '0';
SELFREFRESH_REQ_R2 <= '0';
SELFREFRESH_REQ_R3 <= '0';
PLL_LOCK_R1 <= '0';
PLL_LOCK_R2 <= '0';
elsif (UI_CLK'event and UI_CLK = '1') then
-- SELFREFRESH_MCB_MODE is clocked by sysclk_2x_180
SELFREFRESH_MCB_MODE_R1 <= SELFREFRESH_MCB_MODE;
SELFREFRESH_MCB_MODE_R2 <= SELFREFRESH_MCB_MODE_R1;
SELFREFRESH_MCB_MODE_R3 <= SELFREFRESH_MCB_MODE_R2;
-- SELFREFRESH_REQ is clocked by user's application clock
SELFREFRESH_REQ_R1 <= SELFREFRESH_REQ;
SELFREFRESH_REQ_R2 <= SELFREFRESH_REQ_R1;
SELFREFRESH_REQ_R3 <= SELFREFRESH_REQ_R2;
PLL_LOCK_R1 <= PLL_LOCK;
PLL_LOCK_R2 <= PLL_LOCK_R1;
end if;
end process;
-- SELFREFRESH should only be deasserted after PLL_LOCK is asserted.
-- This is to make sure MCB get a locked sys_2x_clk before exiting
-- SELFREFRESH mode.
process (UI_CLK)
begin
if (UI_CLK'event and UI_CLK = '1') then
if (RST = '1') then
SELFREFRESH_MCB_REQ <= '0';
--elsif ((PLL_LOCK_R2 = '1') and (SELFREFRESH_REQ_R3 = '0') and (STATE = START_DYN_CAL)) then
elsif ((PLL_LOCK_R2 = '1') and (SELFREFRESH_REQ_R3 = '0')) then
SELFREFRESH_MCB_REQ <= '0';
elsif ((STATE = START_DYN_CAL) and (SELFREFRESH_REQ_R3 = '1')) then
SELFREFRESH_MCB_REQ <= '1';
end if;
end if;
end process;
process (UI_CLK)
begin
if (UI_CLK'event and UI_CLK = '1') then
if (RST = '1') then
WAIT_SELFREFRESH_EXIT_DQS_CAL <= '0';
elsif ((SELFREFRESH_MCB_MODE_R2 = '1') and (SELFREFRESH_MCB_MODE_R3 = '0')) then
WAIT_SELFREFRESH_EXIT_DQS_CAL <= '1';
elsif ((WAIT_SELFREFRESH_EXIT_DQS_CAL = '1') and (SELFREFRESH_REQ_R3 = '0') and (PERFORM_START_DYN_CAL_AFTER_SELFREFRESH = '1')) then
-- START_DYN_CAL is next state
WAIT_SELFREFRESH_EXIT_DQS_CAL <= '0';
end if;
end if;
end process;
-- Need to detect when SM entering START_DYN_CAL
process (UI_CLK)
begin
if (UI_CLK'event and UI_CLK = '1') then
if (RST = '1') then
PERFORM_START_DYN_CAL_AFTER_SELFREFRESH <= '0';
START_DYN_CAL_STATE_R1 <= '0';
else
-- register PERFORM_START_DYN_CAL_AFTER_SELFREFRESH to detect end of cycle
PERFORM_START_DYN_CAL_AFTER_SELFREFRESH_R1 <= PERFORM_START_DYN_CAL_AFTER_SELFREFRESH;
if (STATE = START_DYN_CAL) then
START_DYN_CAL_STATE_R1 <= '1';
else
START_DYN_CAL_STATE_R1 <= '0';
end if;
if ((WAIT_SELFREFRESH_EXIT_DQS_CAL = '1') and (STATE /= START_DYN_CAL) and (START_DYN_CAL_STATE_R1 = '1')) then
PERFORM_START_DYN_CAL_AFTER_SELFREFRESH <= '1';
elsif ((STATE = START_DYN_CAL) and (SELFREFRESH_MCB_MODE_R3 = '0')) then
PERFORM_START_DYN_CAL_AFTER_SELFREFRESH <= '0';
end if;
end if;
end if;
end process;
-- SELFREFRESH_MCB_MODE deasserted status is hold off
-- until Soft_Calib has at least done one loop of DQS update.
-- New logic WarmeEnough is added to make sure PLL_Lock is lockec and all IOs stable before
-- deassert the status of MCB's SELFREFRESH_MODE. This is to ensure all IOs are stable before
-- user logic sending new commands to MCB.
process (UI_CLK)
begin
if (UI_CLK'event and UI_CLK = '1') then
if (RST = '1') then
SELFREFRESH_MODE_xilinx11 <= '0';
elsif (SELFREFRESH_MCB_MODE_R2 = '1') then
SELFREFRESH_MODE_xilinx11 <= '1';
elsif (WarmEnough = '1') then
SELFREFRESH_MODE_xilinx11 <= '0';
end if;
end if;
end process;
process (UI_CLK)
begin
if (UI_CLK'event and UI_CLK = '1') then
if (RST = '1') then
WaitCountEnable <= '0';
elsif (SELFREFRESH_REQ_R2 = '0' and SELFREFRESH_REQ_R1 = '1') then
WaitCountEnable <= '0';
elsif ((PERFORM_START_DYN_CAL_AFTER_SELFREFRESH = '0') and (PERFORM_START_DYN_CAL_AFTER_SELFREFRESH_R1 = '1')) then
WaitCountEnable <= '1';
else
WaitCountEnable <= WaitCountEnable;
end if;
end if;
end process;
process (UI_CLK)
begin
if (UI_CLK'event and UI_CLK = '1') then
if (RST = '1') then
State_Start_DynCal <= '0';
elsif (STATE = START_DYN_CAL) then
State_Start_DynCal <= '1';
else
State_Start_DynCal <= '0';
end if;
end if;
end process;
process (UI_CLK)
begin
if (UI_CLK'event and UI_CLK = '1') then
if (RST = '1') then
State_Start_DynCal_R1 <= '0';
else
State_Start_DynCal_R1 <= State_Start_DynCal;
end if;
end if;
end process;
process (UI_CLK)
begin
if (UI_CLK'event and UI_CLK = '1') then
if (RST = '1') then
WaitTimer <= (others => '0');
WarmEnough <= '1';
elsif ((SELFREFRESH_REQ_R2 = '0') and (SELFREFRESH_REQ_R1 = '1')) then
WaitTimer <= (others => '0');
WarmEnough <= '0';
elsif (WaitTimer = X"04") then
WaitTimer <= WaitTimer ;
WarmEnough <= '1';
elsif (WaitCountEnable = '1') then
WaitTimer <= WaitTimer + '1';
else
WaitTimer <= WaitTimer ;
end if;
end if;
end process;
--********************************************
--Comparitor for Dynamic Calibration circuit
--********************************************
Dec_Flag <= '1' when (TARGET_DQS_DELAY < DQS_DELAY) else '0';
Inc_Flag <= '1' when (TARGET_DQS_DELAY > DQS_DELAY) else '0';
--*********************************************************************************************
--Counter for extra clock cycles injected after setting Calibrate bit in IODRP2 for Dynamic Cal
--*********************************************************************************************
process (UI_CLK)
begin
if (UI_CLK'event and UI_CLK = '1') then
if (RST_reg = '1') then
count <= "000000";
elsif (counter_en = '1') then
count <= count + "000001";
else
count <= "000000";
end if;
end if;
end process;
--*********************************************************************************************
-- Capture narrow MCB_UODATAVALID pulse - only one sysclk90 cycle wide
--*********************************************************************************************
process (UI_CLK, MCB_UODATAVALID)
begin
if(MCB_UODATAVALID = '1') then
MCB_UODATAVALID_U <= '1';
elsif(UI_CLK'event and UI_CLK = '1') then
MCB_UODATAVALID_U <= MCB_UODATAVALID;
end if;
end process;
--**************************************************************************************************************
--Always block to mux SDI, SDO, CS, and ADD depending on which IODRP is active: RZQ, ZIO or MCB's UI port (to IODRP2_MCBs)
--**************************************************************************************************************
process (Active_IODRP, IODRP_CS, RZQ_IODRP_SDO, ZIO_IODRP_SDO)
begin
case Active_IODRP is
when RZQ =>
RZQ_IODRP_CS <= IODRP_CS;
ZIO_IODRP_CS <= '0';
IODRP_SDO <= RZQ_IODRP_SDO;
when ZIO =>
RZQ_IODRP_CS <= '0';
ZIO_IODRP_CS <= IODRP_CS;
IODRP_SDO <= ZIO_IODRP_SDO;
when MCB_PORT =>
RZQ_IODRP_CS <= '0';
ZIO_IODRP_CS <= '0';
IODRP_SDO <= '0';
when others =>
RZQ_IODRP_CS <= '0';
ZIO_IODRP_CS <= '0';
IODRP_SDO <= '0';
end case;
end process;
--******************************************************************
--State Machine's Always block / Case statement for Next State Logic
--
--The WAIT1,2,etc states were required after every state where the
--DRP controller was used to do a write to the IODRPs - this is because
--there's a clock cycle latency on IODRPCTRLR_RDY_BUSY_N whenever the DRP controller
--sees IODRPCTRLR_CMD_VALID go high. OFF_RZQ_PTERM and OFF_ZIO_NTERM were added
--soley for the purpose of reducing power, particularly on RZQ as
--that pin is expected to have a permanent external resistor to gnd.
--******************************************************************
NEXT_STATE_LOGIC: process (UI_CLK)
begin
if (UI_CLK'event and UI_CLK = '1') then
if (RST_reg = '1') then -- Synchronous reset
MCB_CMD_VALID <= '0';
MCB_UIADDR_int <= "00000"; -- take control of UI/UO port
MCB_UICMDEN <= '1'; -- tells MCB that it is in Soft Cal.
MCB_UIDONECAL_xilinx7 <= '0';
MCB_USE_BKST <= '0';
MCB_UIDRPUPDATE <= '1';
Pre_SYSRST <= '1'; -- keeps MCB in reset
IODRPCTRLR_CMD_VALID <= '0';
IODRPCTRLR_MEMCELL_ADDR <= NoOp;
IODRPCTRLR_WRITE_DATA <= "00000000";
IODRPCTRLR_R_WB <= WRITE_MODE;
IODRPCTRLR_USE_BKST <= '0';
P_Term <= "000000";
N_Term <= "0000000";
P_Term_s <= "000000";
N_Term_w <= "0000000";
P_Term_w <= "000000";
N_Term_s <= "0000000";
P_Term_Prev <= "000000";
N_Term_Prev <= "0000000";
Active_IODRP <= RZQ;
MCB_UILDQSINC <= '0'; --no inc or dec
MCB_UIUDQSINC <= '0'; --no inc or dec
MCB_UILDQSDEC <= '0'; --no inc or dec
MCB_UIUDQSDEC <= '0';
counter_en <= '0'; --flag that the First Dynamic Calibration completed
First_Dyn_Cal_Done <= '0';
Max_Value_int <= "00000000";
Max_Value_Previous <= "00000000";
STATE <= START;
DQS_DELAY <= "00000000";
DQS_DELAY_INITIAL <= "00000000";
TARGET_DQS_DELAY <= "00000000";
LastPass_DynCal <= IN_TERM_PASS;
First_In_Term_Done <= '0';
MCB_UICMD <= '0';
MCB_UICMDIN <= '0';
MCB_UIDQCOUNT <= "0000";
counter_inc <= "00000000";
counter_dec <= "00000000";
else
counter_en <= '0';
IODRPCTRLR_CMD_VALID <= '0';
IODRPCTRLR_MEMCELL_ADDR <= NoOp;
IODRPCTRLR_R_WB <= READ_MODE;
IODRPCTRLR_USE_BKST <= '0';
MCB_CMD_VALID <= '0'; --no inc or dec
MCB_UILDQSINC <= '0'; --no inc or dec
MCB_UIUDQSINC <= '0'; --no inc or dec
MCB_UILDQSDEC <= '0'; --no inc or dec
MCB_UIUDQSDEC <= '0';
MCB_USE_BKST <= '0';
MCB_UICMDIN <= '0';
DQS_DELAY <= DQS_DELAY;
TARGET_DQS_DELAY <= TARGET_DQS_DELAY;
case STATE is
when START => --h00
MCB_UICMDEN <= '1'; -- take control of UI/UO port
MCB_UIDONECAL_xilinx7 <= '0'; -- tells MCB that it is in Soft Cal.
P_Term <= "000000";
N_Term <= "0000000";
Pre_SYSRST <= '1'; -- keeps MCB in reset
LastPass_DynCal <= IN_TERM_PASS;
if (SKIP_IN_TERM_CAL = 1) then
--STATE <= WRITE_CALIBRATE;
STATE <= WAIT_FOR_START_BROADCAST;
P_Term <= "000000";
N_Term <= "0000000";
elsif (IODRPCTRLR_RDY_BUSY_N = '1') then
STATE <= LOAD_RZQ_NTERM;
else
STATE <= START;
end if;
--***************************
-- IOB INPUT TERMINATION CAL
--***************************
when LOAD_RZQ_NTERM => --h01
Active_IODRP <= RZQ;
IODRPCTRLR_CMD_VALID <= '1';
IODRPCTRLR_MEMCELL_ADDR <= NTerm;
IODRPCTRLR_WRITE_DATA <= ('0' & N_Term);
IODRPCTRLR_R_WB <= WRITE_MODE;
if (IODRPCTRLR_RDY_BUSY_N = '1') then
STATE <= LOAD_RZQ_NTERM;
else
STATE <= WAIT1;
end if;
when WAIT1 => --h02
if (IODRPCTRLR_RDY_BUSY_N = '0') then
STATE <= WAIT1;
else
STATE <= LOAD_RZQ_PTERM;
end if;
when LOAD_RZQ_PTERM => --h03
IODRPCTRLR_CMD_VALID <= '1';
IODRPCTRLR_MEMCELL_ADDR <= PTerm;
IODRPCTRLR_WRITE_DATA <= ("00" & P_Term);
IODRPCTRLR_R_WB <= WRITE_MODE;
if (IODRPCTRLR_RDY_BUSY_N = '1') then
STATE <= LOAD_RZQ_PTERM;
else
STATE <= WAIT2;
end if;
when WAIT2 => --h04
if (IODRPCTRLR_RDY_BUSY_N = '0') then
STATE <= WAIT2;
elsif ((RZQ_IN = '1') or (P_Term = "111111")) then
STATE <= MULTIPLY_DIVIDE; -- LOAD_ZIO_PTERM
else
STATE <= INC_PTERM;
end if;
when INC_PTERM => --h05
P_Term <= P_Term + "000001";
STATE <= LOAD_RZQ_PTERM;
when MULTIPLY_DIVIDE => -- h06
-- 13/4/2011 compensate the added sync FF
P_Term <= Mult_Divide(("00" & (P_Term - '1')),MULT,DIV)(5 downto 0);
STATE <= LOAD_ZIO_PTERM;
when LOAD_ZIO_PTERM => --h07
Active_IODRP <= ZIO;
IODRPCTRLR_CMD_VALID <= '1';
IODRPCTRLR_MEMCELL_ADDR <= PTerm;
IODRPCTRLR_WRITE_DATA <= ("00" & P_Term);
IODRPCTRLR_R_WB <= WRITE_MODE;
if (IODRPCTRLR_RDY_BUSY_N = '1') then
STATE <= LOAD_ZIO_PTERM;
else
STATE <= WAIT3;
end if;
when WAIT3 => --h08
if ((not(IODRPCTRLR_RDY_BUSY_N)) = '1') then
STATE <= WAIT3;
else
STATE <= LOAD_ZIO_NTERM;
end if;
when LOAD_ZIO_NTERM => --h09
Active_IODRP <= ZIO;
IODRPCTRLR_CMD_VALID <= '1';
IODRPCTRLR_MEMCELL_ADDR <= NTerm;
IODRPCTRLR_WRITE_DATA <= ('0' & N_Term);
IODRPCTRLR_R_WB <= WRITE_MODE;
if (IODRPCTRLR_RDY_BUSY_N = '1') then
STATE <= LOAD_ZIO_NTERM;
else
STATE <= WAIT4;
end if;
when WAIT4 => --h0A
if ((not(IODRPCTRLR_RDY_BUSY_N)) = '1') then
STATE <= WAIT4;
elsif (((not(ZIO_IN))) = '1' or (N_Term = "1111111")) then
if (PNSKEW = '1') then
STATE <= SKEW;
else
STATE <= WAIT_FOR_START_BROADCAST;
end if;
else
STATE <= INC_NTERM;
end if;
when INC_NTERM => --h0B
N_Term <= N_Term + "0000001";
STATE <= LOAD_ZIO_NTERM;
when SKEW => -- h0C
P_Term_s <= Mult_Divide(("00" & P_Term), MULT_S, DIV_S)(5 downto 0);
N_Term_w <= Mult_Divide(('0' & (N_Term-'1')), MULT_W, DIV_W)(6 downto 0);
P_Term_w <= Mult_Divide(("00" & P_Term), MULT_W, DIV_W)(5 downto 0);
N_Term_s <= Mult_Divide(('0' & (N_Term-'1')), MULT_S, DIV_S)(6 downto 0);
P_Term <= Mult_Divide(("00" & P_Term), MULT_S, DIV_S)(5 downto 0);
N_Term <= Mult_Divide(('0' & (N_Term-'1')), MULT_W, DIV_W)(6 downto 0);
STATE <= WAIT_FOR_START_BROADCAST;
when WAIT_FOR_START_BROADCAST => --h0D
Pre_SYSRST <= '0'; -- release SYSRST, but keep UICMDEN=1 and UIDONECAL=0. This is needed to do Broadcast through UI interface, while
-- keeping the MCB in calibration mode
Active_IODRP <= MCB_PORT;
if ((START_BROADCAST and IODRPCTRLR_RDY_BUSY_N) = '1') then
if ((P_Term /= P_Term_Prev) or (SKIP_IN_TERM_CAL = 1)) then
STATE <= BROADCAST_PTERM;
P_Term_Prev <= P_Term;
elsif (N_Term /= N_Term_Prev) then
N_Term_Prev <= N_Term;
STATE <= BROADCAST_NTERM;
else
STATE <= OFF_RZQ_PTERM;
end if;
else
STATE <= WAIT_FOR_START_BROADCAST;
end if;
when BROADCAST_PTERM => --h0E
IODRPCTRLR_MEMCELL_ADDR <= PTerm;
IODRPCTRLR_WRITE_DATA <= ("00" & P_Term);
IODRPCTRLR_R_WB <= WRITE_MODE;
MCB_CMD_VALID <= '1';
MCB_UIDRPUPDATE <= not First_In_Term_Done; -- Set the update flag if this is the first time through
MCB_USE_BKST <= '1';
if (MCB_RDY_BUSY_N = '1') then
STATE <= BROADCAST_PTERM;
else
STATE <= WAIT5;
end if;
when WAIT5 => --h0F
if ((not(MCB_RDY_BUSY_N)) = '1') then
STATE <= WAIT5;
elsif (First_In_Term_Done = '1') then -- If first time through is already set, then this must be dynamic in term
if (MCB_UOREFRSHFLAG = '1')then
MCB_UIDRPUPDATE <= '1';
if (N_Term /= N_Term_Prev) then
N_Term_Prev <= N_Term;
STATE <= BROADCAST_NTERM;
else
STATE <= OFF_RZQ_PTERM;
end if;
else
STATE <= WAIT5; -- wait for a Refresh cycle
end if;
else
N_Term_Prev <= N_Term;
STATE <= BROADCAST_NTERM;
end if;
when BROADCAST_NTERM => -- h10
IODRPCTRLR_MEMCELL_ADDR <= NTerm;
IODRPCTRLR_WRITE_DATA <= ("0" & N_Term);
IODRPCTRLR_R_WB <= WRITE_MODE;
MCB_CMD_VALID <= '1';
MCB_USE_BKST <= '1';
MCB_UIDRPUPDATE <= not(First_In_Term_Done); -- Set the update flag if this is the first time through
if (MCB_RDY_BUSY_N = '1') then
STATE <= BROADCAST_NTERM;
else
STATE <= WAIT6;
end if;
when WAIT6 => -- h11
if (MCB_RDY_BUSY_N = '0') then
STATE <= WAIT6;
elsif (First_In_Term_Done = '1') then -- If first time through is already set, then this must be dynamic in term
if (MCB_UOREFRSHFLAG = '1')then
MCB_UIDRPUPDATE <= '1';
STATE <= OFF_RZQ_PTERM;
else
STATE <= WAIT6; -- wait for a Refresh cycle
end if;
else
-- if (PNSKEWDQS = '1') then
STATE <= LDQS_CLK_WRITE_P_TERM;
-- else
-- STATE <= OFF_RZQ_PTERM;
-- end if;
end if;
-- *********************
when LDQS_CLK_WRITE_P_TERM => -- h12
IODRPCTRLR_MEMCELL_ADDR <= PTerm;
IODRPCTRLR_R_WB <= WRITE_MODE;
IODRPCTRLR_WRITE_DATA <= "00" & P_Term_w;
MCB_UIADDR_int <= IOI_LDQS_CLK;
MCB_CMD_VALID <= '1';
if (MCB_RDY_BUSY_N = '1') then
STATE <= LDQS_CLK_WRITE_P_TERM;
else
STATE <= LDQS_CLK_P_TERM_WAIT;
end if;
when LDQS_CLK_P_TERM_WAIT => --7'h13
if (MCB_RDY_BUSY_N = '0') then
STATE <= LDQS_CLK_P_TERM_WAIT;
else
STATE <= LDQS_CLK_WRITE_N_TERM;
end if;
when LDQS_CLK_WRITE_N_TERM => --7'h14
IODRPCTRLR_MEMCELL_ADDR <= NTerm;
IODRPCTRLR_R_WB <= WRITE_MODE;
IODRPCTRLR_WRITE_DATA <= '0' & N_Term_s;
MCB_UIADDR_int <= IOI_LDQS_CLK;
MCB_CMD_VALID <= '1';
if (MCB_RDY_BUSY_N = '1') then
STATE <= LDQS_CLK_WRITE_N_TERM;
else
STATE <= LDQS_CLK_N_TERM_WAIT;
end if;
--**
when LDQS_CLK_N_TERM_WAIT => --7'h15
if (MCB_RDY_BUSY_N = '0') then
STATE <= LDQS_CLK_N_TERM_WAIT;
else
STATE <= LDQS_PIN_WRITE_P_TERM;
end if;
when LDQS_PIN_WRITE_P_TERM => --7'h16
IODRPCTRLR_MEMCELL_ADDR <= PTerm;
IODRPCTRLR_R_WB <= WRITE_MODE;
IODRPCTRLR_WRITE_DATA <= "00" & P_Term_s;
MCB_UIADDR_int <= IOI_LDQS_PIN;
MCB_CMD_VALID <= '1';
if (MCB_RDY_BUSY_N = '1') then
STATE <= LDQS_PIN_WRITE_P_TERM;
else
STATE <= LDQS_PIN_P_TERM_WAIT;
end if;
when LDQS_PIN_P_TERM_WAIT => --7'h17
if (MCB_RDY_BUSY_N = '0') then
STATE <= LDQS_PIN_P_TERM_WAIT;
else
STATE <= LDQS_PIN_WRITE_N_TERM;
end if;
when LDQS_PIN_WRITE_N_TERM => --7'h18
IODRPCTRLR_MEMCELL_ADDR <= NTerm;
IODRPCTRLR_R_WB <= WRITE_MODE;
IODRPCTRLR_WRITE_DATA <= '0' & N_Term_w;
MCB_UIADDR_int <= IOI_LDQS_PIN;
MCB_CMD_VALID <= '1';
if (MCB_RDY_BUSY_N = '1') then
STATE <= LDQS_PIN_WRITE_N_TERM;
else
STATE <= LDQS_PIN_N_TERM_WAIT;
end if;
when LDQS_PIN_N_TERM_WAIT => --7'h19
if (MCB_RDY_BUSY_N = '0') then
STATE <= LDQS_PIN_N_TERM_WAIT;
else
STATE <= UDQS_CLK_WRITE_P_TERM;
end if;
when UDQS_CLK_WRITE_P_TERM => --7'h1A
IODRPCTRLR_MEMCELL_ADDR <= PTerm;
IODRPCTRLR_R_WB <= WRITE_MODE;
IODRPCTRLR_WRITE_DATA <= "00" & P_Term_w;
MCB_UIADDR_int <= IOI_UDQS_CLK;
MCB_CMD_VALID <= '1';
if (MCB_RDY_BUSY_N = '1') then
STATE <= UDQS_CLK_WRITE_P_TERM;
else
STATE <= UDQS_CLK_P_TERM_WAIT;
end if;
when UDQS_CLK_P_TERM_WAIT => --7'h1B
if (MCB_RDY_BUSY_N = '0') then
STATE <= UDQS_CLK_P_TERM_WAIT;
else
STATE <= UDQS_CLK_WRITE_N_TERM;
end if;
when UDQS_CLK_WRITE_N_TERM => --7'h1C
IODRPCTRLR_MEMCELL_ADDR <= NTerm;
IODRPCTRLR_R_WB <= WRITE_MODE;
IODRPCTRLR_WRITE_DATA <= '0' & N_Term_s;
MCB_UIADDR_int <= IOI_UDQS_CLK;
MCB_CMD_VALID <= '1';
if (MCB_RDY_BUSY_N = '1') then
STATE <= UDQS_CLK_WRITE_N_TERM;
else
STATE <= UDQS_CLK_N_TERM_WAIT;
end if;
when UDQS_CLK_N_TERM_WAIT => --7'h1D
if (MCB_RDY_BUSY_N = '0') then
STATE <= UDQS_CLK_N_TERM_WAIT;
else
STATE <= UDQS_PIN_WRITE_P_TERM;
end if;
when UDQS_PIN_WRITE_P_TERM => --7'h1E
IODRPCTRLR_MEMCELL_ADDR <= PTerm;
IODRPCTRLR_R_WB <= WRITE_MODE;
IODRPCTRLR_WRITE_DATA <= "00" & P_Term_s;
MCB_UIADDR_int <= IOI_UDQS_PIN;
MCB_CMD_VALID <= '1';
if (MCB_RDY_BUSY_N = '1') then
STATE <= UDQS_PIN_WRITE_P_TERM;
else
STATE <= UDQS_PIN_P_TERM_WAIT;
end if;
when UDQS_PIN_P_TERM_WAIT => --7'h1F
if (MCB_RDY_BUSY_N = '0') then
STATE <= UDQS_PIN_P_TERM_WAIT;
else
STATE <= UDQS_PIN_WRITE_N_TERM;
end if;
when UDQS_PIN_WRITE_N_TERM => --7'h20
IODRPCTRLR_MEMCELL_ADDR <= NTerm;
IODRPCTRLR_R_WB <= WRITE_MODE;
IODRPCTRLR_WRITE_DATA <= '0' & N_Term_w;
MCB_UIADDR_int <= IOI_UDQS_PIN;
MCB_CMD_VALID <= '1';
if (MCB_RDY_BUSY_N = '1') then
STATE <= UDQS_PIN_WRITE_N_TERM;
else
STATE <= UDQS_PIN_N_TERM_WAIT;
end if;
when UDQS_PIN_N_TERM_WAIT => --7'h21
if (MCB_RDY_BUSY_N = '0') then
STATE <= UDQS_PIN_N_TERM_WAIT;
else
STATE <= OFF_RZQ_PTERM;
end if;
-- *********************
when OFF_RZQ_PTERM => -- h22
Active_IODRP <= RZQ;
IODRPCTRLR_CMD_VALID <= '1';
IODRPCTRLR_MEMCELL_ADDR <= PTerm;
IODRPCTRLR_WRITE_DATA <= "00000000";
IODRPCTRLR_R_WB <= WRITE_MODE;
P_Term <= "000000";
N_Term <= "0000000";
MCB_UIDRPUPDATE <= not(First_In_Term_Done); -- Set the update flag if this is the first time through
if (IODRPCTRLR_RDY_BUSY_N = '1') then
STATE <= OFF_RZQ_PTERM;
else
STATE <= WAIT7;
end if;
when WAIT7 => -- h23
if ((not(IODRPCTRLR_RDY_BUSY_N)) = '1') then
STATE <= WAIT7;
else
STATE <= OFF_ZIO_NTERM;
end if;
when OFF_ZIO_NTERM => -- h24
Active_IODRP <= ZIO;
IODRPCTRLR_CMD_VALID <= '1';
IODRPCTRLR_MEMCELL_ADDR <= NTerm;
IODRPCTRLR_WRITE_DATA <= "00000000";
IODRPCTRLR_R_WB <= WRITE_MODE;
if (IODRPCTRLR_RDY_BUSY_N = '1') then
STATE <= OFF_ZIO_NTERM;
else
STATE <= WAIT8;
end if;
when WAIT8 => -- h25
if (IODRPCTRLR_RDY_BUSY_N = '0') then
STATE <= WAIT8;
else
if (First_In_Term_Done = '1') then
STATE <= START_DYN_CAL; -- No need to reset the MCB if we are in InTerm tuning
else
STATE <= WRITE_CALIBRATE; -- go read the first Max_Value_int from RZQ
end if;
end if;
when RST_DELAY => -- h26
--MCB_UICMDEN <= '0'; -- release control of UI/UO port
if (Block_Reset = '1') then -- this ensures that more than 512 clock cycles occur since the last reset after MCB_WRITE_CALIBRATE ???
STATE <= RST_DELAY;
else
STATE <= START_DYN_CAL_PRE;
end if;
--***************************
--DYNAMIC CALIBRATION PORTION
--***************************
when START_DYN_CAL_PRE => -- h27
LastPass_DynCal <= IN_TERM_PASS;
MCB_UICMDEN <= '0'; -- release UICMDEN
MCB_UIDONECAL_xilinx7 <= '1'; -- release UIDONECAL - MCB will now initialize.
Pre_SYSRST <= '1'; -- SYSRST pulse
if (CALMODE_EQ_CALIBRATION = '0') then -- if C_MC_CALIBRATION_MODE is set to NOCALIBRATION
STATE <= START_DYN_CAL; -- we'll skip setting the DQS delays manually
elsif (pre_sysrst_minpulse_width_ok = '1') then
STATE <= WAIT_FOR_UODONE;
end if;
when WAIT_FOR_UODONE => -- h28
Pre_SYSRST <= '0'; -- SYSRST pulse
if ((IODRPCTRLR_RDY_BUSY_N and MCB_UODONECAL) = '1')then --IODRP Controller needs to be ready, & MCB needs to be done with hard calibration
MCB_UICMDEN <= '1'; -- grab UICMDEN
DQS_DELAY_INITIAL <= Mult_Divide(Max_Value_int, DQS_NUMERATOR, DQS_DENOMINATOR);
STATE <= LDQS_WRITE_POS_INDELAY;
else
STATE <= WAIT_FOR_UODONE;
end if;
when LDQS_WRITE_POS_INDELAY => -- h29
IODRPCTRLR_MEMCELL_ADDR <= PosEdgeInDly;
IODRPCTRLR_R_WB <= WRITE_MODE;
IODRPCTRLR_WRITE_DATA <= DQS_DELAY_INITIAL;
MCB_UIADDR_int <= IOI_LDQS_CLK;
MCB_CMD_VALID <= '1';
if (MCB_RDY_BUSY_N = '1') then
STATE <= LDQS_WRITE_POS_INDELAY;
else
STATE <= LDQS_WAIT1;
end if;
when LDQS_WAIT1 => -- h2A
if (MCB_RDY_BUSY_N = '0')then
STATE <= LDQS_WAIT1;
else
STATE <= LDQS_WRITE_NEG_INDELAY;
end if;
when LDQS_WRITE_NEG_INDELAY => -- h2B
IODRPCTRLR_MEMCELL_ADDR <= NegEdgeInDly;
IODRPCTRLR_R_WB <= WRITE_MODE;
IODRPCTRLR_WRITE_DATA <= DQS_DELAY_INITIAL;
MCB_UIADDR_int <= IOI_LDQS_CLK;
MCB_CMD_VALID <= '1';
if (MCB_RDY_BUSY_N = '1')then
STATE <= LDQS_WRITE_NEG_INDELAY;
else
STATE <= LDQS_WAIT2;
end if;
when LDQS_WAIT2 => -- 7'h2C
if(MCB_RDY_BUSY_N = '0')then
STATE <= LDQS_WAIT2;
else
STATE <= UDQS_WRITE_POS_INDELAY;
end if;
when UDQS_WRITE_POS_INDELAY => -- 7'h2D
IODRPCTRLR_MEMCELL_ADDR <= PosEdgeInDly;
IODRPCTRLR_R_WB <= WRITE_MODE;
IODRPCTRLR_WRITE_DATA <= DQS_DELAY_INITIAL;
MCB_UIADDR_int <= IOI_UDQS_CLK;
MCB_CMD_VALID <= '1';
if (MCB_RDY_BUSY_N = '1')then
STATE <= UDQS_WRITE_POS_INDELAY;
else
STATE <= UDQS_WAIT1;
end if;
when UDQS_WAIT1 => -- 7'h2E
if (MCB_RDY_BUSY_N = '0')then
STATE <= UDQS_WAIT1;
else
STATE <= UDQS_WRITE_NEG_INDELAY;
end if;
when UDQS_WRITE_NEG_INDELAY => -- 7'h2F
IODRPCTRLR_MEMCELL_ADDR <= NegEdgeInDly;
IODRPCTRLR_R_WB <= WRITE_MODE;
IODRPCTRLR_WRITE_DATA <= DQS_DELAY_INITIAL;
MCB_UIADDR_int <= IOI_UDQS_CLK;
MCB_CMD_VALID <= '1';
if (MCB_RDY_BUSY_N = '1')then
STATE <= UDQS_WRITE_NEG_INDELAY;
else
STATE <= UDQS_WAIT2;
end if;
when UDQS_WAIT2 => -- 7'h30
if (MCB_RDY_BUSY_N = '0')then
STATE <= UDQS_WAIT2;
else
DQS_DELAY <= DQS_DELAY_INITIAL;
TARGET_DQS_DELAY <= DQS_DELAY_INITIAL;
STATE <= START_DYN_CAL;
end if;
when START_DYN_CAL => -- h31
Pre_SYSRST <= '0'; -- SYSRST not driven
counter_inc <= (others => '0');
counter_dec <= (others => '0');
if (SKIP_DYNAMIC_DQS_CAL = '1' and SKIP_DYN_IN_TERMINATION = '1')then
STATE <= DONE; --if we're skipping both dynamic algorythms, go directly to DONE
elsif ((IODRPCTRLR_RDY_BUSY_N = '1') and (MCB_UODONECAL = '1') and (SELFREFRESH_REQ_R1 = '0')) then
--IODRP Controller needs to be ready, & MCB needs to be done with hard calibration
-- Alternate between Dynamic Input Termination and Dynamic Tuning routines
if ((SKIP_DYN_IN_TERMINATION = '0') and (LastPass_DynCal = DYN_CAL_PASS)) then
LastPass_DynCal <= IN_TERM_PASS;
STATE <= LOAD_RZQ_NTERM;
else
LastPass_DynCal <= DYN_CAL_PASS;
STATE <= WRITE_CALIBRATE;
end if;
else
STATE <= START_DYN_CAL;
end if;
when WRITE_CALIBRATE => -- h32
Pre_SYSRST <= '0';
IODRPCTRLR_CMD_VALID <= '1';
IODRPCTRLR_MEMCELL_ADDR <= DelayControl;
IODRPCTRLR_WRITE_DATA <= "00100000";
IODRPCTRLR_R_WB <= WRITE_MODE;
Active_IODRP <= RZQ;
if (IODRPCTRLR_RDY_BUSY_N = '1') then
STATE <= WRITE_CALIBRATE;
else
STATE <= WAIT9;
end if;
when WAIT9 => -- h33
counter_en <= '1';
if (count < "100110") then -- this adds approximately 22 extra clock cycles after WRITE_CALIBRATE
STATE <= WAIT9;
else
STATE <= READ_MAX_VALUE;
end if;
when READ_MAX_VALUE => -- h34
IODRPCTRLR_CMD_VALID <= '1';
IODRPCTRLR_MEMCELL_ADDR <= MaxValue;
IODRPCTRLR_R_WB <= READ_MODE;
Max_Value_Previous <= Max_Value_int;
if (IODRPCTRLR_RDY_BUSY_N = '1') then
STATE <= READ_MAX_VALUE;
else
STATE <= WAIT10;
end if;
when WAIT10 => -- h35
if (IODRPCTRLR_RDY_BUSY_N = '0') then
STATE <= WAIT10;
else
Max_Value_int <= IODRPCTRLR_READ_DATA; --record the Max_Value_int from the IODRP controller
if (First_In_Term_Done = '0') then
STATE <= RST_DELAY;
First_In_Term_Done <= '1';
else
STATE <= ANALYZE_MAX_VALUE;
end if;
end if;
when ANALYZE_MAX_VALUE => -- h36 only do a Inc or Dec during a REFRESH cycle.
if (First_Dyn_Cal_Done = '0')then
STATE <= FIRST_DYN_CAL;
elsif ((Max_Value_int < Max_Value_Previous) and (Max_Value_Delta_Dn >= INCDEC_THRESHOLD)) then
STATE <= DECREMENT; -- May need to Decrement
TARGET_DQS_DELAY <= Mult_Divide(Max_Value_int, DQS_NUMERATOR, DQS_DENOMINATOR);
-- DQS_COUNT_VIRTUAL updated (could be negative value)
elsif ((Max_Value_int > Max_Value_Previous) and (Max_Value_Delta_Up >= INCDEC_THRESHOLD)) then
STATE <= INCREMENT; -- May need to Increment
TARGET_DQS_DELAY <= Mult_Divide(Max_Value_int, DQS_NUMERATOR, DQS_DENOMINATOR);
else
Max_Value_int <= Max_Value_Previous;
STATE <= START_DYN_CAL;
end if;
when FIRST_DYN_CAL => -- h37
First_Dyn_Cal_Done <= '1'; -- set flag that the First Dynamic Calibration has been completed
STATE <= START_DYN_CAL;
when INCREMENT => -- h38
STATE <= START_DYN_CAL; -- Default case: Inc is not high or no longer in REFRSH
MCB_UILDQSINC <= '0'; -- Default case: no inc or dec
MCB_UIUDQSINC <= '0'; -- Default case: no inc or dec
MCB_UILDQSDEC <= '0'; -- Default case: no inc or dec
MCB_UIUDQSDEC <= '0'; -- Default case: no inc or dec
case Inc_Dec_REFRSH_Flag is -- {Increment_Flag,Decrement_Flag,MCB_UOREFRSHFLAG},
when "101" =>
counter_inc <= counter_inc + '1';
STATE <= INCREMENT; -- Increment is still high, still in REFRSH cycle
if ((DQS_DELAY < DQS_DELAY_UPPER_LIMIT) and (counter_inc >= X"04")) then
-- if not at the upper limit yet, and you've waited 4 clks, increment
MCB_UILDQSINC <= '1';
MCB_UIUDQSINC <= '1';
DQS_DELAY <= DQS_DELAY + '1';
end if;
when "100" =>
if (DQS_DELAY < DQS_DELAY_UPPER_LIMIT) then
STATE <= INCREMENT; -- Increment is still high, REFRESH ended - wait for next REFRESH
end if;
when others =>
STATE <= START_DYN_CAL;
end case;
when DECREMENT => -- h39
STATE <= START_DYN_CAL; -- Default case: Dec is not high or no longer in REFRSH
MCB_UILDQSINC <= '0'; -- Default case: no inc or dec
MCB_UIUDQSINC <= '0'; -- Default case: no inc or dec
MCB_UILDQSDEC <= '0'; -- Default case: no inc or dec
MCB_UIUDQSDEC <= '0'; -- Default case: no inc or dec
if (DQS_DELAY /= "00000000") then
case Inc_Dec_REFRSH_Flag is -- {Increment_Flag,Decrement_Flag,MCB_UOREFRSHFLAG},
when "011" =>
counter_dec <= counter_dec + '1';
STATE <= DECREMENT; -- Decrement is still high, still in REFRSH cycle
if ((DQS_DELAY > DQS_DELAY_LOWER_LIMIT) and (counter_dec >= X"04")) then
-- if not at the lower limit, and you've waited 4 clks, decrement
MCB_UILDQSDEC <= '1'; -- decrement
MCB_UIUDQSDEC <= '1'; -- decrement
DQS_DELAY <= DQS_DELAY - '1'; -- SBS
end if;
when "010" =>
if (DQS_DELAY > DQS_DELAY_LOWER_LIMIT) then --if not at the lower limit, decrement
STATE <= DECREMENT; --Decrement is still high, REFRESH ended - wait for next REFRESH
end if;
when others =>
STATE <= START_DYN_CAL;
end case;
end if;
when DONE => -- h3A
Pre_SYSRST <= '0'; -- SYSRST cleared
MCB_UICMDEN <= '0'; -- release UICMDEN
STATE <= DONE;
when others =>
MCB_UICMDEN <= '0'; -- release UICMDEN
MCB_UIDONECAL_xilinx7 <= '1'; -- release UIDONECAL - MCB will now initialize.
Pre_SYSRST <= '0'; -- SYSRST not driven
IODRPCTRLR_CMD_VALID <= '0';
IODRPCTRLR_MEMCELL_ADDR <= "00000000";
IODRPCTRLR_WRITE_DATA <= "00000000";
IODRPCTRLR_R_WB <= '0';
IODRPCTRLR_USE_BKST <= '0';
P_Term <= "000000";
N_Term <= "0000000";
Active_IODRP <= ZIO;
Max_Value_Previous <= "00000000";
MCB_UILDQSINC <= '0'; -- no inc or dec
MCB_UIUDQSINC <= '0'; -- no inc or dec
MCB_UILDQSDEC <= '0'; -- no inc or dec
MCB_UIUDQSDEC <= '0'; -- no inc or dec
counter_en <= '0';
First_Dyn_Cal_Done <= '0'; -- flag that the First Dynamic Calibration completed
Max_Value_int <= Max_Value_int;
STATE <= START;
end case;
end if;
end if;
end process;
end architecture trans;
|
bsd-2-clause
|
tomstuart/pygments
|
tests/examplefiles/test.vhdl
|
75
|
4446
|
library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity top_testbench is --test
generic ( -- test
n : integer := 8 -- test
); -- test
end top_testbench; -- test
architecture top_testbench_arch of top_testbench is
component top is
generic (
n : integer
) ;
port (
clk : in std_logic;
rst : in std_logic;
d1 : in std_logic_vector (n-1 downto 0);
d2 : in std_logic_vector (n-1 downto 0);
operation : in std_logic;
result : out std_logic_vector (2*n-1 downto 0)
);
end component;
signal clk : std_logic;
signal rst : std_logic;
signal operation : std_logic;
signal d1 : std_logic_vector (n-1 downto 0);
signal d2 : std_logic_vector (n-1 downto 0);
signal result : std_logic_vector (2*n-1 downto 0);
type test_type is ( a1, a2, a3, a4, a5, a6, a7, a8, a9, a10);
attribute enum_encoding of my_state : type is "001 010 011 100 111";
begin
TESTUNIT : top generic map (n => n)
port map (clk => clk,
rst => rst,
d1 => d1,
d2 => d2,
operation => operation,
result => result);
clock_process : process
begin
clk <= '0';
wait for 5 ns;
clk <= '1';
wait for 5 ns;
end process;
data_process : process
begin
-- test case #1
operation <= '0';
rst <= '1';
wait for 5 ns;
rst <= '0';
wait for 5 ns;
d1 <= std_logic_vector(to_unsigned(60, d1'length));
d2 <= std_logic_vector(to_unsigned(12, d2'length));
wait for 360 ns;
assert (result = std_logic_vector(to_unsigned(720, result'length)))
report "Test case #1 failed" severity error;
-- test case #2
operation <= '0';
rst <= '1';
wait for 5 ns;
rst <= '0';
wait for 5 ns;
d1 <= std_logic_vector(to_unsigned(55, d1'length));
d2 <= std_logic_vector(to_unsigned(1, d2'length));
wait for 360 ns;
assert (result = std_logic_vector(to_unsigned(55, result'length)))
report "Test case #2 failed" severity error;
-- etc
end process;
end top_testbench_arch;
configuration testbench_for_top of top_testbench is
for top_testbench_arch
for TESTUNIT : top
use entity work.top(top_arch);
end for;
end for;
end testbench_for_top;
function compare(A: std_logic, B: std_Logic) return std_logic is
constant pi : real := 3.14159;
constant half_pi : real := pi / 2.0;
constant cycle_time : time := 2 ns;
constant N, N5 : integer := 5;
begin
if (A = '0' and B = '1') then
return B;
else
return A;
end if ;
end compare;
procedure print(P : std_logic_vector(7 downto 0);
U : std_logic_vector(3 downto 0)) is
variable my_line : line;
alias swrite is write [line, string, side, width] ;
begin
swrite(my_line, "sqrt( ");
write(my_line, P);
swrite(my_line, " )= ");
write(my_line, U);
writeline(output, my_line);
end print;
entity add32csa is -- one stage of carry save adder for multiplier
port(
b : in std_logic; -- a multiplier bit
a : in std_logic_vector(31 downto 0); -- multiplicand
sum_in : in std_logic_vector(31 downto 0); -- sums from previous stage
cin : in std_logic_vector(31 downto 0); -- carrys from previous stage
sum_out : out std_logic_vector(31 downto 0); -- sums to next stage
cout : out std_logic_vector(31 downto 0)); -- carrys to next stage
end add32csa;
ARCHITECTURE circuits of add32csa IS
SIGNAL zero : STD_LOGIC_VECTOR(31 downto 0) := X"00000000";
SIGNAL aa : std_logic_vector(31 downto 0) := X"00000000";
COMPONENT fadd -- duplicates entity port
PoRT(a : in std_logic;
b : in std_logic;
cin : in std_logic;
s : out std_logic;
cout : out std_logic);
end comPonent fadd;
begin -- circuits of add32csa
aa <= a when b='1' else zero after 1 ns;
stage: for I in 0 to 31 generate
sta: fadd port map(aa(I), sum_in(I), cin(I) , sum_out(I), cout(I));
end generate stage;
end architecture circuits; -- of add32csa
|
bsd-2-clause
|
saidwivedi/Face-Recognition-Hardware
|
ANN_FPGA/ipcore_dir/test_image/simulation/addr_gen.vhd
|
101
|
4409
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Address Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: addr_gen.vhd
--
-- Description:
-- Address Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY ADDR_GEN IS
GENERIC ( C_MAX_DEPTH : INTEGER := 1024 ;
RST_VALUE : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS=> '0');
RST_INC : INTEGER := 0);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
LOAD :IN STD_LOGIC;
LOAD_VALUE : IN STD_LOGIC_VECTOR (31 DOWNTO 0) := (OTHERS => '0');
ADDR_OUT : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) --OUTPUT VECTOR
);
END ADDR_GEN;
ARCHITECTURE BEHAVIORAL OF ADDR_GEN IS
SIGNAL ADDR_TEMP : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS =>'0');
BEGIN
ADDR_OUT <= ADDR_TEMP;
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 );
ELSE
IF(EN='1') THEN
IF(LOAD='1') THEN
ADDR_TEMP <=LOAD_VALUE;
ELSE
IF(ADDR_TEMP = C_MAX_DEPTH-1) THEN
ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 );
ELSE
ADDR_TEMP <= ADDR_TEMP + '1';
END IF;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE;
|
bsd-2-clause
|
saidwivedi/Face-Recognition-Hardware
|
ANN_FPGA/ipcore_dir/weight_hid/example_design/weight_hid_exdes.vhd
|
1
|
4629
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: weight_hid_exdes.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY weight_hid_exdes IS
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(319 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(319 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END weight_hid_exdes;
ARCHITECTURE xilinx OF weight_hid_exdes IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT weight_hid IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(319 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(319 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bmg0 : weight_hid
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA_buf
);
END xilinx;
|
bsd-2-clause
|
saidwivedi/Face-Recognition-Hardware
|
ANN_FPGA/ipcore_dir/test_image/simulation/data_gen.vhd
|
69
|
5024
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Data Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: data_gen.vhd
--
-- Description:
-- Data Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.BMG_TB_PKG.ALL;
ENTITY DATA_GEN IS
GENERIC ( DATA_GEN_WIDTH : INTEGER := 32;
DOUT_WIDTH : INTEGER := 32;
DATA_PART_CNT : INTEGER := 1;
SEED : INTEGER := 2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
DATA_OUT : OUT STD_LOGIC_VECTOR (DOUT_WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END DATA_GEN;
ARCHITECTURE DATA_GEN_ARCH OF DATA_GEN IS
CONSTANT LOOP_COUNT : INTEGER := DIVROUNDUP(DATA_GEN_WIDTH,8);
SIGNAL RAND_DATA : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL LOCAL_DATA_OUT : STD_LOGIC_VECTOR(DATA_GEN_WIDTH-1 DOWNTO 0);
SIGNAL LOCAL_CNT : INTEGER :=1;
SIGNAL DATA_GEN_I : STD_LOGIC :='0';
BEGIN
LOCAL_DATA_OUT <= RAND_DATA(DATA_GEN_WIDTH-1 DOWNTO 0);
DATA_OUT <= LOCAL_DATA_OUT(((DOUT_WIDTH*LOCAL_CNT)-1) DOWNTO ((DOUT_WIDTH*LOCAL_CNT)-DOUT_WIDTH));
DATA_GEN_I <= '0' WHEN (LOCAL_CNT < DATA_PART_CNT) ELSE EN;
PROCESS(CLK)
BEGIN
IF(RISING_EDGE (CLK)) THEN
IF(EN ='1' AND (DATA_PART_CNT =1)) THEN
LOCAL_CNT <=1;
ELSIF(EN='1' AND (DATA_PART_CNT>1)) THEN
IF(LOCAL_CNT = 1) THEN
LOCAL_CNT <= LOCAL_CNT+1;
ELSIF(LOCAL_CNT < DATA_PART_CNT) THEN
LOCAL_CNT <= LOCAL_CNT+1;
ELSE
LOCAL_CNT <= 1;
END IF;
ELSE
LOCAL_CNT <= 1;
END IF;
END IF;
END PROCESS;
RAND_GEN:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
RAND_GEN_INST:ENTITY work.RANDOM
GENERIC MAP(
WIDTH => 8,
SEED => (SEED+N)
)
PORT MAP(
CLK => CLK,
RST => RST,
EN => DATA_GEN_I,
RANDOM_NUM => RAND_DATA(8*(N+1)-1 DOWNTO 8*N)
);
END GENERATE RAND_GEN;
END ARCHITECTURE;
|
bsd-2-clause
|
saidwivedi/Face-Recognition-Hardware
|
ANN_FPGA/ipcore_dir/blk_mem_gen_v7_3/simulation/data_gen.vhd
|
69
|
5024
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Data Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: data_gen.vhd
--
-- Description:
-- Data Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.BMG_TB_PKG.ALL;
ENTITY DATA_GEN IS
GENERIC ( DATA_GEN_WIDTH : INTEGER := 32;
DOUT_WIDTH : INTEGER := 32;
DATA_PART_CNT : INTEGER := 1;
SEED : INTEGER := 2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
DATA_OUT : OUT STD_LOGIC_VECTOR (DOUT_WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END DATA_GEN;
ARCHITECTURE DATA_GEN_ARCH OF DATA_GEN IS
CONSTANT LOOP_COUNT : INTEGER := DIVROUNDUP(DATA_GEN_WIDTH,8);
SIGNAL RAND_DATA : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL LOCAL_DATA_OUT : STD_LOGIC_VECTOR(DATA_GEN_WIDTH-1 DOWNTO 0);
SIGNAL LOCAL_CNT : INTEGER :=1;
SIGNAL DATA_GEN_I : STD_LOGIC :='0';
BEGIN
LOCAL_DATA_OUT <= RAND_DATA(DATA_GEN_WIDTH-1 DOWNTO 0);
DATA_OUT <= LOCAL_DATA_OUT(((DOUT_WIDTH*LOCAL_CNT)-1) DOWNTO ((DOUT_WIDTH*LOCAL_CNT)-DOUT_WIDTH));
DATA_GEN_I <= '0' WHEN (LOCAL_CNT < DATA_PART_CNT) ELSE EN;
PROCESS(CLK)
BEGIN
IF(RISING_EDGE (CLK)) THEN
IF(EN ='1' AND (DATA_PART_CNT =1)) THEN
LOCAL_CNT <=1;
ELSIF(EN='1' AND (DATA_PART_CNT>1)) THEN
IF(LOCAL_CNT = 1) THEN
LOCAL_CNT <= LOCAL_CNT+1;
ELSIF(LOCAL_CNT < DATA_PART_CNT) THEN
LOCAL_CNT <= LOCAL_CNT+1;
ELSE
LOCAL_CNT <= 1;
END IF;
ELSE
LOCAL_CNT <= 1;
END IF;
END IF;
END PROCESS;
RAND_GEN:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
RAND_GEN_INST:ENTITY work.RANDOM
GENERIC MAP(
WIDTH => 8,
SEED => (SEED+N)
)
PORT MAP(
CLK => CLK,
RST => RST,
EN => DATA_GEN_I,
RANDOM_NUM => RAND_DATA(8*(N+1)-1 DOWNTO 8*N)
);
END GENERATE RAND_GEN;
END ARCHITECTURE;
|
bsd-2-clause
|
saidwivedi/Face-Recognition-Hardware
|
ANN_FPGA/controller-risotto-2.vhd
|
1
|
4736
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.custom_pkg.all;
entity controller is
port ( clk : in std_logic;
rst : in std_logic;
wea : in std_logic_vector(0 downto 0);
dina_image : in std_logic_vector(7 downto 0);
dina_weights : in std_logic_vector(23 downto 0);
addra_image : in std_logic_vector(4 downto 0);
addra_weights : in std_logic_vector(4 downto 0)
);
end controller;
architecture Behavioral of controller is
signal'
num_neurons, input : std_logic_vector(7 downto 0);
signal layer : layer_type;
constant num_hidden_neurons : Integer := 3;
signal weight_hid, weight : eight_bit(num_hidden_neurons-1 downto 0);
signal output_hid : std_logic_vector(7 downto 0);
signal shift_over_flag, active_activation, rst_layer : std_logic := '0';
signal curr_state,next_state : layer_type;
COMPONENT test_image
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
COMPONENT weight_hid
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END COMPONENT;
COMPONENT weight_out
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END COMPONENT;
COMPONENT hidden_layer
port ( clk : in std_logic ;
num_neurons : in std_logic_vector(7 downto 0);
layer : in layer_type;
rst : in std_logic ;
image : in std_logic_vector(7 downto 0);
weight_hid : in eight_bit(num_hidden_neurons-1 downto 0);
shift_over_flag : out std_logic;
active_ativation : out std_logic;
output_hid : out std_logic_vector(7 downto 0)
);
END COMPONENT;
begin
test_image_map : test_image
PORT MAP (clk, wea, addra_image, dina_image, image);
layer_map : hidden_layer
PORT MAP (clk, num_neurons, layer, rst_layer, image, weight, shift_over_flag, active_activation, output_hid);
weight_hid_map: weight_hid
PORT MAP (clk, "0", addr_weight_hid, in_weight_hid, out_weight_hid);
weight_out_map: weight_out
PORT MAP (clk, "0", addr_weight_out, in_weight_out, out_weight_out);
transition : process (clk,reset)
begin
if rst ='1' then
curr_state <= idle; --default state on reset.
elsif (rising_edge(clk)) then
if curr_state = weighted_sum_layer1 and active_activation = '0' then
curr_state <= next_state; --state change.
end if;
end process;
next_state_logic : process (curr_state, shift_over_flag, active_activation) begin
case curr_state is
when idle =>
if active_activation = '0' then
next_state <= weighted_sum_layer1;
else
next_state <= idle;
end if;
when weighted_sum_layer1 =>
if active_activation = '1' then
next_state <= activate_layer1;
else
next_state <= weighted_sum_layer1;
end if;
when activate_layer1 =>
if shift_over_flag = '1' then
next_state <= rst_layer;
else
next_state <= activate_layer1;
end if;
when reset_layer =>
if active_activation = '0' then
next_state <= weighted_sum_layer2;
else
next_state <= rst_layer;
end if;
when weighted_sum_layer2 =>
if active_activation = '1' then
next_state <= activate_layer2;
else
next_state <= weighted_sum_layer2;
end if;
when activate_layer2 =>
if shift_over_flag = '1' then
next_state <= idle;
else
next_state <= activate_layer2;
end if;
end case;
end process;
Output: process (curr_state) begin
case curr_state is
when idle =>
rst_layer <= '1';
num_neurons <= (others=>'0');
layer <= idle;
image <= (others=>'0');
weight <= (others=>'0');
when weighted_sum_layer1 =>
rst_layer <= '0';
num_neurons <= "00000100";
layer <= weighted_sum_layer1;
image <= douta_image;
weight <= "00001";
when activate_layer1 =>
rst_layer <= '0';
num_neurons <= "00000100";
layer <= activate_layer1;
image <= (others=>'0');
weight <= (others=>'0');
when reset_layer =>
rst_layer <= '1';
num_neurons <= (others=>'0');
layer <= idle;
image <= (others=>'0');
weight <= (others=>'0');
when weighted_sum_layer2 =>
rst_layer <= '0';
num_neurons <= "00000011";
layer <= weighted_sum_layer2;
image <= douta_image;
weight <= "00010";
end case;
end process;
end process;
end Behavioral;
|
bsd-2-clause
|
tommylommykins/logipi-midi-player
|
hdl/top.vhd
|
1
|
5473
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
library virtual_button_lib;
use virtual_button_lib.utils.all;
use virtual_button_lib.constants.all;
use virtual_button_lib.button_pkg.all;
use virtual_button_lib.sine_lut_pkg.all;
use virtual_button_lib.midi_pkg.all;
entity top is
port(
clk_50mhz : in std_logic;
pb_0 : in std_logic;
pb_1 : in std_logic;
sw_0 : in std_logic;
sw_1 : in std_logic;
led_0 : out std_logic;
led_1 : out std_logic;
--uart interface
pi_to_fpga_pin : in std_logic;
fpga_to_pi_pin : out std_logic;
-- spi interface
sclk : in std_logic;
cs_n : in std_logic;
mosi : in std_logic;
miso : out std_logic;
-- light square output
light_square_data : out std_logic
);
end top;
architecture rtl of top is
signal ctrl : ctrl_t;
signal clk : std_logic;
-- uart signals
signal uart_rx_data : std_logic_vector(7 downto 0);
signal uart_received : std_logic;
signal uart_framing_error : std_logic;
signal run_counter_dbg : std_logic;
-- button signals
signal buttons : button_arr;
-- spi signals
signal miso_int : std_logic;
signal spi_new_mcu_to_fpga_data : std_logic;
signal spi_mcu_to_fpga_data : std_logic_vector(spi_word_length - 1 downto 0);
signal spi_fpga_to_mcu_data : std_logic_vector(15 downto 0);
signal spi_enqueue_fpga_to_mcu_data : std_logic;
signal spi_contents_count : integer range 0 to spi_tx_ram_depth;
signal spi_tx_buffer_full : std_logic;
signal enable_spi_tx : std_logic;
--midi signals
signal pcm_out : signed(15 downto 0);
signal new_pcm_out : std_logic;
signal enable_decoder : std_logic;
signal errors : errors_t;
signal midi_nos : midi_note_arr_t;
-- midi ram signals
signal midi_ram_empty : std_logic;
signal midi_ram_full : std_logic;
signal midi_ram_contents_count : natural range 0 to midi_file_rx_bram_depth;
begin
uart_top_1 : entity virtual_button_lib.uart_top
port map (
ctrl => ctrl,
uart_rx => pi_to_fpga_pin,
uart_tx => fpga_to_pi_pin,
rx_data => uart_rx_data,
received => uart_received,
framing_error => uart_framing_error,
run_counter_dbg => run_counter_dbg
);
many_buttons_1 : entity virtual_button_lib.many_buttons
port map (
ctrl => ctrl,
data => uart_rx_data,
new_data => uart_received,
buttons => buttons
);
spi_top_1 : entity virtual_button_lib.spi_top
generic map (
tx_ram_depth => spi_tx_ram_depth,
tx_max_block_size => spi_tx_max_block_size,
cpol => 0,
cpha => 0)
port map (
ctrl => ctrl,
cs_n => cs_n,
sclk => sclk,
mosi => mosi,
miso => miso_int,
new_mcu_to_fpga_data => spi_new_mcu_to_fpga_data,
mcu_to_fpga_data => spi_mcu_to_fpga_data,
enqueue_fpga_to_mcu_data => spi_enqueue_fpga_to_mcu_data,
fpga_to_mcu_data => spi_fpga_to_mcu_data,
full => spi_tx_buffer_full,
contents_count => spi_contents_count
);
spi_fpga_to_mcu_data <= std_logic_vector(pcm_out);
temp_midi_note_player_1 : entity work.many_sines
port map (
ctrl => ctrl,
midi_nos => midi_nos,
pcm_out => pcm_out,
new_pcm_out => new_pcm_out);
spi_enqueue_fpga_to_mcu_data <= new_pcm_out;
midi_top_1 : entity virtual_button_lib.midi_top
port map (
ctrl => ctrl,
buttons => buttons,
enqueue => spi_new_mcu_to_fpga_data,
write_in_data => spi_mcu_to_fpga_data,
midi_nos => midi_nos,
empty => midi_ram_empty,
full => midi_ram_full,
enable_decoder => enable_decoder,
errors => errors,
contents_count => midi_ram_contents_count);
debug_light_generator_1 : entity virtual_button_lib.debug_light_generator
generic map(
spi_tx_max_block_size => spi_tx_max_block_size,
spi_tx_ram_depth => spi_tx_ram_depth
)
port map (
ctrl => ctrl,
spi_tx_buffer_full => spi_tx_buffer_full,
contents_count => spi_contents_count,
buttons => buttons,
cs_n => cs_n,
enable_spi_tx => enable_spi_tx,
uart_framing_error => uart_framing_error,
midi_ram_contents_count => midi_ram_contents_count,
enable_decoder => enable_decoder,
errors => errors,
run_counter_dbg => run_counter_dbg,
light_square_data => light_square_data
);
-----------------------------------------------------------------------------
ctrl.clk <= clk_50mhz;
resetting : process (ctrl.clk) is
begin
if rising_edge(ctrl.clk) then
if buttons(r).pressed = '1' or sw_0 = '0' then
ctrl.reset_n <= '0';
else
ctrl.reset_n <= '1';
end if;
end if;
end process resetting;
tom_is_the_best : process (ctrl.clk) is
begin
if rising_edge(ctrl.clk) then
if ctrl.reset_n = '0' then
led_0 <= '0';
else
led_0 <= pb_0 xor sw_0 xor pb_1 xor sw_1;
end if;
end if;
end process;
-- Enable/disable spi data transmission.
enable_spi_tx <= '1';
led_1 <= '0';
miso <= miso_int;
end rtl;
|
bsd-2-clause
|
tdaede/daala_zynq
|
daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_auto_pc_121_0/fifo_generator_v11_0/ramfifo/rd_handshaking_flags.vhd
|
2
|
13849
|
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`protect end_protected
|
bsd-2-clause
|
tdaede/daala_zynq
|
daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_auto_pc_120_0/blk_mem_gen_v8_0/blk_mem_output_block.vhd
|
2
|
17222
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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6ngRJqZPBg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 11008)
`protect data_block
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`protect end_protected
|
bsd-2-clause
|
tdaede/daala_zynq
|
daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_auto_pc_121_0/blk_mem_gen_v8_0/blk_mem_output_block.vhd
|
2
|
17222
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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6ngRJqZPBg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 11008)
`protect data_block
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`protect end_protected
|
bsd-2-clause
|
tdaede/daala_zynq
|
daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_dma_0_0/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_addr_cntl.vhd
|
1
|
42473
|
----------------------------------------------------------------------------
-- axi_datamover_addr_cntl.vhd
----------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
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-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_addr_cntl.vhd
--
-- Description:
-- This file implements the axi_datamover Master Address Controller.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_datamover_addr_cntl.vhd
--
-------------------------------------------------------------------------------
-- Revision History:
--
--
-- Author: DET
--
-- History:
-- DET 04/19/2011 Initial Version for EDK 13.3
--
--
-- DET 9/1/2011 Initial Version for EDK 13.3
-- ~~~~~~
-- - Fixed Lint reported excesive line length for line 196.
-- ^^^^^^
--
-- DET 9/1/2011 Initial Version for EDK 13.3
-- ~~~~~~
-- - Fixed a Lint reported issue with the vector widths of the addr2axi_aprot
-- assignment to the constant APROT_VALUE. The code was ok but Spyglass
-- was not interpreting the vector MS Index correctly, I changed the HDL
-- anyway.
-- ^^^^^^
--
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_datamover_v5_1;
Use axi_datamover_v5_1.axi_datamover_fifo;
-------------------------------------------------------------------------------
entity axi_datamover_addr_cntl is
generic (
C_ADDR_FIFO_DEPTH : Integer range 1 to 32 := 4;
-- sets the depth of the Command Queue FIFO
C_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Sets the address bus width
C_ADDR_ID : Integer range 0 to 255 := 0;
-- Sets the value to be on the AxID output
C_ADDR_ID_WIDTH : Integer range 1 to 8 := 4;
-- Sets the width of the AxID output
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Sets the width of the Command Tag field width
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA family
);
port (
-- Clock input ---------------------------------------------
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
------------------------------------------------------------
-- AXI Address Channel I/O --------------------------------------------
addr2axi_aid : out std_logic_vector(C_ADDR_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
addr2axi_aaddr : out std_logic_vector(C_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
addr2axi_alen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
addr2axi_asize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
addr2axi_aburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
addr2axi_acache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel BURST output --
--
addr2axi_auser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel BURST output --
--
addr2axi_aprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
addr2axi_avalid : out std_logic; --
-- AXI Address Channel VALID output --
--
axi2addr_aready : in std_logic; --
-- AXI Address Channel READY input --
------------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -------
-- addr2axi_alock : out std_logic_vector(2 downto 0); --
-- addr2axi_acache : out std_logic_vector(4 downto 0); --
-- addr2axi_aqos : out std_logic_vector(3 downto 0); --
-- addr2axi_aregion : out std_logic_vector(3 downto 0); --
-------------------------------------------------------------------
-- Command Calculation Interface -----------------------------------------
mstr2addr_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2addr_addr : In std_logic_vector(C_ADDR_WIDTH-1 downto 0); --
-- The next command address to put on the AXI MMap ADDR --
--
mstr2addr_len : In std_logic_vector(7 downto 0); --
-- The next command length to put on the AXI MMap LEN --
-- Sized to support 256 data beat bursts --
--
mstr2addr_size : In std_logic_vector(2 downto 0); --
-- The next command size to put on the AXI MMap SIZE --
--
mstr2addr_burst : In std_logic_vector(1 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_cache : In std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_user : In std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_cmd_cmplt : In std_logic; --
-- The indication to the Address Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2addr_calc_error : In std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2addr_cmd_valid : in std_logic; --
-- The next command valid indication to the Address Channel --
-- Controller for the AXI MMap --
--
addr2mstr_cmd_ready : out std_logic; --
-- Indication to the Command Calculator that the --
-- command is being accepted --
--------------------------------------------------------------------------
-- Halted Indication to Reset Module ------------------------------
addr2rst_stop_cmplt : out std_logic; --
-- Output flag indicating the address controller has stopped --
-- posting commands to the Address Channel due to a stop --
-- request vai the data2addr_stop_req input port --
------------------------------------------------------------------
-- Address Generation Control ---------------------------------------
allow_addr_req : in std_logic; --
-- Input used to enable/stall the posting of address requests. --
-- 0 = stall address request generation. --
-- 1 = Enable Address request geneartion --
--
addr_req_posted : out std_logic; --
-- Indication from the Address Channel Controller to external --
-- User logic that an address has been posted to the --
-- AXI Address Channel. --
---------------------------------------------------------------------
-- Data Channel Interface ---------------------------------------------
addr2data_addr_posted : Out std_logic; --
-- Indication from the Address Channel Controller to the --
-- Data Controller that an address has been posted to the --
-- AXI Address Channel. --
--
data2addr_data_rdy : In std_logic; --
-- Indication that the Data Channel is ready to send the first --
-- databeat of the next command on the write data channel. --
-- This is used for the "wait for data" feature which keeps the --
-- address controller from issuing a transfer requset until the --
-- corresponding data is ready. This is expected to be held in --
-- the asserted state until the addr2data_addr_posted signal is --
-- asserted. --
--
data2addr_stop_req : In std_logic; --
-- Indication that the Data Channel has encountered an error --
-- or a soft shutdown request and needs the Address Controller --
-- to stop posting commands to the AXI Address channel --
-----------------------------------------------------------------------
-- Status Module Interface ---------------------------------------
addr2stat_calc_error : out std_logic; --
-- Indication to the Status Module that the Addr Cntl FIFO --
-- is loaded with a Calc error --
--
addr2stat_cmd_fifo_empty : out std_logic --
-- Indication to the Status Module that the Addr Cntl FIFO --
-- is empty --
------------------------------------------------------------------
);
end entity axi_datamover_addr_cntl;
architecture implementation of axi_datamover_addr_cntl is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Constant Declarations --------------------------------------------
Constant APROT_VALUE : std_logic_vector(2 downto 0) := (others => '0');
--'0' & -- bit 2, Normal Access
--'0' & -- bit 1, Nonsecure Access
--'0'; -- bit 0, Data Access
Constant LEN_WIDTH : integer := 8;
Constant SIZE_WIDTH : integer := 3;
Constant BURST_WIDTH : integer := 2;
Constant CMD_CMPLT_WIDTH : integer := 1;
Constant CALC_ERROR_WIDTH : integer := 1;
Constant ADDR_QUAL_WIDTH : integer := C_TAG_WIDTH + -- Cmd Tag field width
C_ADDR_WIDTH + -- Cmd Address field width
LEN_WIDTH + -- Cmd Len field width
SIZE_WIDTH + -- Cmd Size field width
BURST_WIDTH + -- Cmd Burst field width
CMD_CMPLT_WIDTH + -- Cmd Cmplt filed width
CALC_ERROR_WIDTH + -- Cmd Calc Error flag
8; -- Cmd Cache, user fields
Constant USE_SYNC_FIFO : integer := 0;
Constant REG_FIFO_PRIM : integer := 0;
Constant BRAM_FIFO_PRIM : integer := 1;
Constant SRL_FIFO_PRIM : integer := 2;
Constant FIFO_PRIM_TYPE : integer := SRL_FIFO_PRIM;
-- Signal Declarations --------------------------------------------
signal sig_axi_addr : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_axi_alen : std_logic_vector(7 downto 0) := (others => '0');
signal sig_axi_asize : std_logic_vector(2 downto 0) := (others => '0');
signal sig_axi_aburst : std_logic_vector(1 downto 0) := (others => '0');
signal sig_axi_acache : std_logic_vector(3 downto 0) := (others => '0');
signal sig_axi_auser : std_logic_vector(3 downto 0) := (others => '0');
signal sig_axi_avalid : std_logic := '0';
signal sig_axi_aready : std_logic := '0';
signal sig_addr_posted : std_logic := '0';
signal sig_calc_error : std_logic := '0';
signal sig_cmd_fifo_empty : std_logic := '0';
Signal sig_aq_fifo_data_in : std_logic_vector(ADDR_QUAL_WIDTH-1 downto 0) := (others => '0');
Signal sig_aq_fifo_data_out : std_logic_vector(ADDR_QUAL_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_addr : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_fifo_next_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_fifo_next_burst : std_logic_vector(1 downto 0) := (others => '0');
signal sig_fifo_next_user : std_logic_vector(3 downto 0) := (others => '0');
signal sig_fifo_next_cache : std_logic_vector(3 downto 0) := (others => '0');
signal sig_fifo_next_cmd_cmplt : std_logic := '0';
signal sig_fifo_calc_error : std_logic := '0';
signal sig_fifo_wr_cmd_valid : std_logic := '0';
signal sig_fifo_wr_cmd_ready : std_logic := '0';
signal sig_fifo_rd_cmd_valid : std_logic := '0';
signal sig_fifo_rd_cmd_ready : std_logic := '0';
signal sig_next_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_next_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_next_len_reg : std_logic_vector(7 downto 0) := (others => '0');
signal sig_next_size_reg : std_logic_vector(2 downto 0) := (others => '0');
signal sig_next_burst_reg : std_logic_vector(1 downto 0) := (others => '0');
signal sig_next_cache_reg : std_logic_vector(3 downto 0) := (others => '0');
signal sig_next_user_reg : std_logic_vector(3 downto 0) := (others => '0');
signal sig_next_cmd_cmplt_reg : std_logic := '0';
signal sig_addr_valid_reg : std_logic := '0';
signal sig_calc_error_reg : std_logic := '0';
signal sig_pop_addr_reg : std_logic := '0';
signal sig_push_addr_reg : std_logic := '0';
signal sig_addr_reg_empty : std_logic := '0';
signal sig_addr_reg_full : std_logic := '0';
signal sig_posted_to_axi : std_logic := '0';
-- obsoleted signal sig_set_wfd_flop : std_logic := '0';
-- obsoleted signal sig_clr_wfd_flop : std_logic := '0';
-- obsoleted signal sig_wait_for_data : std_logic := '0';
-- obsoleted signal sig_data2addr_data_rdy_reg : std_logic := '0';
signal sig_allow_addr_req : std_logic := '0';
signal sig_posted_to_axi_2 : std_logic := '0';
signal new_cmd_in : std_logic;
signal first_addr_valid : std_logic;
signal first_addr_valid_del : std_logic;
signal first_addr_int : std_logic_vector (C_ADDR_WIDTH-1 downto 0);
signal last_addr_int : std_logic_vector (C_ADDR_WIDTH-1 downto 0);
signal addr2axi_cache_int : std_logic_vector (7 downto 0);
signal addr2axi_cache_int1 : std_logic_vector (7 downto 0);
signal last_one : std_logic;
signal latch : std_logic;
signal first_one : std_logic;
signal latch_n : std_logic;
signal latch_n_del : std_logic;
signal mstr2addr_cache_info_int : std_logic_vector (7 downto 0);
-- Register duplication attribute assignments to control fanout
-- on handshake output signals
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
Attribute KEEP of sig_posted_to_axi : signal is "TRUE"; -- definition
Attribute KEEP of sig_posted_to_axi_2 : signal is "TRUE"; -- definition
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_posted_to_axi : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_posted_to_axi_2 : signal is "no";
begin --(architecture implementation)
-- AXI I/O Port assignments
addr2axi_aid <= STD_LOGIC_VECTOR(TO_UNSIGNED(C_ADDR_ID, C_ADDR_ID_WIDTH));
addr2axi_aaddr <= sig_axi_addr ;
addr2axi_alen <= sig_axi_alen ;
addr2axi_asize <= sig_axi_asize ;
addr2axi_aburst <= sig_axi_aburst;
addr2axi_acache <= sig_axi_acache;
addr2axi_auser <= sig_axi_auser;
addr2axi_aprot <= APROT_VALUE ;
addr2axi_avalid <= sig_axi_avalid;
sig_axi_aready <= axi2addr_aready;
-- Command Calculator Handshake output
sig_fifo_wr_cmd_valid <= mstr2addr_cmd_valid ;
addr2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
-- Data Channel Controller synchro pulse output
addr2data_addr_posted <= sig_addr_posted;
-- Status Module Interface outputs
addr2stat_calc_error <= sig_calc_error ;
addr2stat_cmd_fifo_empty <= sig_addr_reg_empty and
sig_cmd_fifo_empty;
-- Flag Indicating the Address Controller has completed a Stop
addr2rst_stop_cmplt <= (data2addr_stop_req and -- normal shutdown case
sig_addr_reg_empty) or
(data2addr_stop_req and -- shutdown after error trap
sig_calc_error);
-- Assign the address posting control and status
sig_allow_addr_req <= allow_addr_req ;
addr_req_posted <= sig_posted_to_axi_2 ;
-- Internal logic ------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ADDR_FIFO
--
-- If Generate Description:
-- Implements the case where the cmd qualifier depth is
-- greater than 1.
--
------------------------------------------------------------
GEN_ADDR_FIFO : if (C_ADDR_FIFO_DEPTH > 1) generate
begin
-- Format the input FIFO data word
sig_aq_fifo_data_in <= mstr2addr_cache &
mstr2addr_user &
mstr2addr_calc_error &
mstr2addr_cmd_cmplt &
mstr2addr_burst &
mstr2addr_size &
mstr2addr_len &
mstr2addr_addr &
mstr2addr_tag ;
-- Rip fields from FIFO output data word
sig_fifo_next_cache <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
C_TAG_WIDTH +
LEN_WIDTH +
SIZE_WIDTH +
BURST_WIDTH +
CMD_CMPLT_WIDTH +
CALC_ERROR_WIDTH + 7)
downto
(C_ADDR_WIDTH +
C_TAG_WIDTH +
LEN_WIDTH +
SIZE_WIDTH +
BURST_WIDTH +
CMD_CMPLT_WIDTH +
CALC_ERROR_WIDTH + 4)
);
sig_fifo_next_user <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
C_TAG_WIDTH +
LEN_WIDTH +
SIZE_WIDTH +
BURST_WIDTH +
CMD_CMPLT_WIDTH +
CALC_ERROR_WIDTH + 3)
downto
(C_ADDR_WIDTH +
C_TAG_WIDTH +
LEN_WIDTH +
SIZE_WIDTH +
BURST_WIDTH +
CMD_CMPLT_WIDTH +
CALC_ERROR_WIDTH)
);
sig_fifo_calc_error <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
C_TAG_WIDTH +
LEN_WIDTH +
SIZE_WIDTH +
BURST_WIDTH +
CMD_CMPLT_WIDTH +
CALC_ERROR_WIDTH)-1);
sig_fifo_next_cmd_cmplt <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
C_TAG_WIDTH +
LEN_WIDTH +
SIZE_WIDTH +
BURST_WIDTH +
CMD_CMPLT_WIDTH)-1);
sig_fifo_next_burst <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
C_TAG_WIDTH +
LEN_WIDTH +
SIZE_WIDTH +
BURST_WIDTH)-1
downto
C_ADDR_WIDTH +
C_TAG_WIDTH +
LEN_WIDTH +
SIZE_WIDTH) ;
sig_fifo_next_size <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
C_TAG_WIDTH +
LEN_WIDTH +
SIZE_WIDTH)-1
downto
C_ADDR_WIDTH +
C_TAG_WIDTH +
LEN_WIDTH) ;
sig_fifo_next_len <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
C_TAG_WIDTH +
LEN_WIDTH)-1
downto
C_ADDR_WIDTH +
C_TAG_WIDTH) ;
sig_fifo_next_addr <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
C_TAG_WIDTH)-1
downto
C_TAG_WIDTH) ;
sig_fifo_next_tag <= sig_aq_fifo_data_out(C_TAG_WIDTH-1 downto 0);
------------------------------------------------------------
-- Instance: I_ADDR_QUAL_FIFO
--
-- Description:
-- Instance for the Address/Qualifier FIFO
--
------------------------------------------------------------
I_ADDR_QUAL_FIFO : entity axi_datamover_v5_1.axi_datamover_fifo
generic map (
C_DWIDTH => ADDR_QUAL_WIDTH ,
C_DEPTH => C_ADDR_FIFO_DEPTH ,
C_IS_ASYNC => USE_SYNC_FIFO ,
C_PRIM_TYPE => FIFO_PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_fifo_wr_cmd_valid ,
fifo_wr_tready => sig_fifo_wr_cmd_ready ,
fifo_wr_tdata => sig_aq_fifo_data_in ,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_fifo_rd_cmd_valid ,
fifo_rd_tready => sig_fifo_rd_cmd_ready ,
fifo_rd_tdata => sig_aq_fifo_data_out ,
fifo_rd_empty => sig_cmd_fifo_empty
);
end generate GEN_ADDR_FIFO;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_ADDR_FIFO
--
-- If Generate Description:
-- Implements the case where no additional FIFOing is needed
-- on the input command address/qualifiers.
--
------------------------------------------------------------
GEN_NO_ADDR_FIFO : if (C_ADDR_FIFO_DEPTH = 1) generate
begin
-- Bypass FIFO
sig_fifo_next_tag <= mstr2addr_tag ;
sig_fifo_next_addr <= mstr2addr_addr ;
sig_fifo_next_len <= mstr2addr_len ;
sig_fifo_next_size <= mstr2addr_size ;
sig_fifo_next_burst <= mstr2addr_burst ;
sig_fifo_next_cache <= mstr2addr_cache ;
sig_fifo_next_user <= mstr2addr_user ;
sig_fifo_next_cmd_cmplt <= mstr2addr_cmd_cmplt ;
sig_fifo_calc_error <= mstr2addr_calc_error ;
sig_cmd_fifo_empty <= sig_addr_reg_empty ;
sig_fifo_wr_cmd_ready <= sig_fifo_rd_cmd_ready ;
sig_fifo_rd_cmd_valid <= sig_fifo_wr_cmd_valid ;
end generate GEN_NO_ADDR_FIFO;
-- Output Register Logic -------------------------------------------
sig_axi_addr <= sig_next_addr_reg ;
sig_axi_alen <= sig_next_len_reg ;
sig_axi_asize <= sig_next_size_reg ;
sig_axi_aburst <= sig_next_burst_reg ;
sig_axi_acache <= sig_next_cache_reg ;
sig_axi_auser <= sig_next_user_reg ;
sig_axi_avalid <= sig_addr_valid_reg ;
sig_calc_error <= sig_calc_error_reg ;
sig_fifo_rd_cmd_ready <= sig_addr_reg_empty and
sig_allow_addr_req and
-- obsoleted not(sig_wait_for_data) and
not(data2addr_stop_req);
sig_addr_posted <= sig_posted_to_axi ;
-- Internal signals
sig_push_addr_reg <= sig_addr_reg_empty and
sig_fifo_rd_cmd_valid and
sig_allow_addr_req and
-- obsoleted not(sig_wait_for_data) and
not(data2addr_stop_req);
sig_pop_addr_reg <= not(sig_calc_error_reg) and
sig_axi_aready and
sig_addr_reg_full;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ADDR_FIFO_REG
--
-- Process Description:
-- This process implements a register for the Address
-- Control FIFO that operates like a 1 deep Sync FIFO.
--
-------------------------------------------------------------
IMP_ADDR_FIFO_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_pop_addr_reg = '1') then
sig_next_tag_reg <= (others => '0') ;
sig_next_addr_reg <= (others => '0') ;
sig_next_len_reg <= (others => '0') ;
sig_next_size_reg <= (others => '0') ;
sig_next_burst_reg <= (others => '0') ;
sig_next_cache_reg <= (others => '0') ;
sig_next_user_reg <= (others => '0') ;
sig_next_cmd_cmplt_reg <= '0' ;
sig_addr_valid_reg <= '0' ;
sig_calc_error_reg <= '0' ;
sig_addr_reg_empty <= '1' ;
sig_addr_reg_full <= '0' ;
elsif (sig_push_addr_reg = '1') then
sig_next_tag_reg <= sig_fifo_next_tag ;
sig_next_addr_reg <= sig_fifo_next_addr ;
sig_next_len_reg <= sig_fifo_next_len ;
sig_next_size_reg <= sig_fifo_next_size ;
sig_next_burst_reg <= sig_fifo_next_burst ;
sig_next_cache_reg <= sig_fifo_next_cache ;
sig_next_user_reg <= sig_fifo_next_user ;
sig_next_cmd_cmplt_reg <= sig_fifo_next_cmd_cmplt ;
sig_addr_valid_reg <= not(sig_fifo_calc_error);
sig_calc_error_reg <= sig_fifo_calc_error ;
sig_addr_reg_empty <= '0' ;
sig_addr_reg_full <= '1' ;
else
null; -- don't change state
end if;
end if;
end process IMP_ADDR_FIFO_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_POSTED_FLAG
--
-- Process Description:
-- This implements a FLOP that creates a 1 clock wide pulse
-- indicating a new address/qualifier set has been posted to
-- the AXI Addres Channel outputs. This is used to synchronize
-- the Data Channel Controller.
--
-------------------------------------------------------------
IMP_POSTED_FLAG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_posted_to_axi <= '0';
sig_posted_to_axi_2 <= '0';
elsif (sig_push_addr_reg = '1') then
sig_posted_to_axi <= '1';
sig_posted_to_axi_2 <= '1';
else
sig_posted_to_axi <= '0';
sig_posted_to_axi_2 <= '0';
end if;
end if;
end process IMP_POSTED_FLAG;
-- PROC_CMD_DETECT : process (primary_aclk)
-- begin
-- if (mmap_reset = '1') then
-- first_addr_valid_del <= '0';
-- elsif (primary_aclk'event and primary_aclk = '1') then
-- first_addr_valid_del <= first_addr_valid;
-- end if;
-- end process PROC_CMD_DETECT;
--
-- PROC_ADDR_DET : process (primary_aclk)
-- begin
-- if (mmap_reset = '1') then
-- first_addr_valid <= '0';
-- first_addr_int <= (others => '0');
-- last_addr_int <= (others => '0');
-- elsif (primary_aclk'event and primary_aclk = '1') then
-- if (mstr2addr_cmd_valid = '1' and first_addr_valid = '0') then
-- first_addr_valid <= '1';
-- first_addr_int <= mstr2addr_addr;
-- last_addr_int <= last_addr_int;
-- elsif (mstr2addr_cmd_cmplt = '1') then
-- first_addr_valid <= '0';
-- first_addr_int <= first_addr_int;
-- last_addr_int <= mstr2addr_addr;
-- end if;
-- end if;
-- end process PROC_ADDR_DET;
--
-- latch <= first_addr_valid and (not first_addr_valid_del);
-- latch_n <= (not first_addr_valid) and first_addr_valid_del;
--
-- PROC_CACHE1 : process (primary_aclk)
-- begin
-- if (mmap_reset = '1') then
-- mstr2addr_cache_info_int <= (others => '0');
-- latch_n_del <= '0';
-- elsif (primary_aclk'event and primary_aclk = '1') then
-- if (latch_n = '1') then
-- mstr2addr_cache_info_int <= mstr2addr_cache_info;
-- end if;
-- latch_n_del <= latch_n;
-- end if;
-- end process PROC_CACHE1;
--
--
-- PROC_CACHE : process (primary_aclk)
-- begin
-- if (mmap_reset = '1') then
-- addr2axi_cache_int1 <= (others => '0');
-- first_one <= '0';
-- elsif (primary_aclk'event and primary_aclk = '1') then
-- first_one <= '0';
---- if (latch = '1' and first_one = '0') then -- first one
-- if (sig_addr_valid_reg = '0' and first_addr_valid = '0') then
-- addr2axi_cache_int1 <= mstr2addr_cache_info;
---- first_one <= '1';
---- elsif (latch_n_del = '1') then
---- addr2axi_cache_int <= mstr2addr_cache_info_int;
-- elsif ((first_addr_int = sig_next_addr_reg) and (sig_addr_valid_reg = '1')) then
-- addr2axi_cache_int1 <= addr2axi_cache_int1; --mstr2addr_cache_info (7 downto 4);
-- elsif ((last_addr_int >= sig_next_addr_reg) and (sig_addr_valid_reg = '1')) then
-- addr2axi_cache_int1 <= addr2axi_cache_int1; --mstr2addr_cache_info (7 downto 4);
-- end if;
-- end if;
-- end process PROC_CACHE;
--
--
-- PROC_CACHE2 : process (primary_aclk)
-- begin
-- if (mmap_reset = '1') then
-- addr2axi_cache_int <= (others => '0');
-- elsif (primary_aclk'event and primary_aclk = '1') then
-- addr2axi_cache_int <= addr2axi_cache_int1;
-- end if;
-- end process PROC_CACHE2;
--
--addr2axi_cache <= addr2axi_cache_int (3 downto 0);
--addr2axi_user <= addr2axi_cache_int (7 downto 4);
--
end implementation;
|
bsd-2-clause
|
tdaede/daala_zynq
|
daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_dma_0_0/proc_common_v4_0/hdl/src/vhdl/pf_counter.vhd
|
15
|
9203
|
-------------------------------------------------------------------------------
-- $Id: pf_counter.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- pf_counter - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pf_counter.vhd
--
-- Description: Implements 32-bit timer/counter
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pf_counter.vhd
--
-------------------------------------------------------------------------------
-- Author: B.L. Tise
-- Revision: $Revision: 1.1.4.1 $
-- Date: $Date: 2010/09/14 22:35:46 $
--
-- History:
-- D. Thorpe 2001-08-30 First Version
-- - adapted from B Tise MicroBlaze counters
--
-- DET 2001-09-11
-- - Added the Rst input to the pf_counter_bit component
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
library proc_common_v4_0;
use proc_common_v4_0.pf_counter_bit;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity pf_counter is
generic (
C_COUNT_WIDTH : integer := 9
);
port (
Clk : in std_logic;
Rst : in std_logic;
Carry_Out : out std_logic;
Load_In : in std_logic_vector(0 to C_COUNT_WIDTH-1);
Count_Enable : in std_logic;
Count_Load : in std_logic;
Count_Down : in std_logic;
Count_Out : out std_logic_vector(0 to C_COUNT_WIDTH-1)
);
end entity pf_counter;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of pf_counter is
constant CY_START : integer := 1;
signal alu_cy : std_logic_vector(0 to C_COUNT_WIDTH);
signal iCount_Out : std_logic_vector(0 to C_COUNT_WIDTH-1);
signal count_clock_en : std_logic;
signal carry_active_high : std_logic;
begin -- VHDL_RTL
-----------------------------------------------------------------------------
-- Generate the Counter bits
-----------------------------------------------------------------------------
alu_cy(C_COUNT_WIDTH) <= (Count_Down and Count_Load) or
(not Count_Down and not Count_load);
count_clock_en <= Count_Enable or Count_Load;
I_ADDSUB_GEN : for i in 0 to C_COUNT_WIDTH-1 generate
begin
Counter_Bit_I : entity proc_common_v4_0.pf_counter_bit
port map (
Clk => Clk, -- [in]
Rst => Rst, -- [in]
Count_In => iCount_Out(i), -- [in]
Load_In => Load_In(i), -- [in]
Count_Load => Count_Load, -- [in]
Count_Down => Count_Down, -- [in]
Carry_In => alu_cy(i+CY_Start), -- [in]
Clock_Enable => count_clock_en, -- [in]
Result => iCount_Out(i), -- [out]
Carry_Out => alu_cy(i+(1-CY_Start))); -- [out]
end generate I_ADDSUB_GEN;
carry_active_high <= alu_cy(0) xor Count_Down;
I_CARRY_OUT: FDRE
port map (
Q => Carry_Out, -- [out]
C => Clk, -- [in]
CE => count_clock_en, -- [in]
D => carry_active_high, -- [in]
R => Rst -- [in]
);
Count_Out <= iCount_Out;
end architecture implementation;
|
bsd-2-clause
|
tdaede/daala_zynq
|
daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_dma_0_0/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_s2mm_scatter.vhd
|
1
|
69756
|
-------------------------------------------------------------------------------
-- axi_datamover_s2mm_scatter.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_s2mm_scatter.vhd
--
-- Description:
-- This file implements the S2MM Scatter support module. Scatter requires
-- the input Stream to be stopped and disected at command boundaries. The
-- Scatter module splits the input stream data at the command boundaries
-- and force feeds the S2MM DRE with data and source alignment.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_datamover_s2mm_scatter.vhd
--
-------------------------------------------------------------------------------
-- Revision History:
--
--
-- Author: DET
--
-- History:
-- DET 04/19/2011 Initial Version for EDK 13.3
--
-- DET 6/20/2011 Initial Version for EDK 13.3
-- ~~~~~~
-- - Added 512 and 1024 data width support
-- ^^^^^^
--
-- DET 6/29/2011 Initial Version for EDK 13.3
-- ~~~~~~
-- - Incorporated the Indeterminate BTT mode overflow absorption
-- changes needed by AXI VDMA.
-- ^^^^^^
--
-- DET 7/18/2011 Initial Version for EDK 13.3
-- ~~~~~~
-- -- Per CR617164
-- - Added TSTRB fifo empty qualifier to the overflow absorption logic
-- in the IBTT mode case. Also added additional qualification to the
-- sig_gated_fifo_freeze_out signal in the IBTT mode IfGen.
-- ^^^^^^
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_datamover_v5_1;
use axi_datamover_v5_1.axi_datamover_strb_gen2;
use axi_datamover_v5_1.axi_datamover_mssai_skid_buf;
use axi_datamover_v5_1.axi_datamover_fifo;
use axi_datamover_v5_1.axi_datamover_slice;
-------------------------------------------------------------------------------
entity axi_datamover_s2mm_scatter is
generic (
C_ENABLE_INDET_BTT : Integer range 0 to 1 := 0;
-- Indicates if the IBTT Indeterminate BTT is enabled
-- (external to this module)
C_DRE_ALIGN_WIDTH : Integer range 1 to 3 := 2;
-- Sets the width of the S2MM DRE alignment control ports
C_BTT_USED : Integer range 8 to 23 := 16;
-- Sets the width of the BTT input port
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Sets the width of the input and output data streams
C_ENABLE_S2MM_TKEEP : integer range 0 to 1 := 1;
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA device family
);
port (
-- Clock and Reset inputs --------------------------------------------------
--
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
----------------------------------------------------------------------------
-- DRE Realign Controller I/O ----------------------------------------------
--
scatter2drc_cmd_ready : Out std_logic; --
-- Indicates the Scatter Engine is ready to accept a new command --
--
drc2scatter_push_cmd : In std_logic; --
-- Indicates a new command is being read from the command que --
--
drc2scatter_btt : In std_logic_vector(C_BTT_USED-1 downto 0); --
-- Indicates the new command's BTT value --
--
drc2scatter_eof : In std_logic; --
-- Indicates that the input command is also the last of a packet --
-- This input is ignored when C_ENABLE_INDET_BTT = 1 --
----------------------------------------------------------------------------
-- DRE Source Alignment ---------------------------------------------------------
--
scatter2drc_src_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); --
-- Indicates the next source alignment to the DRE control --
--------------------------------------------------------------------------------
-- AXI Slave Stream In ----------------------------------------------------------
--
s2mm_strm_tready : Out Std_logic; --
-- AXI Stream READY input --
--
s2mm_strm_tvalid : In std_logic; --
-- AXI Stream VALID Output --
--
s2mm_strm_tdata : In std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- AXI Stream data output --
--
s2mm_strm_tstrb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- AXI Stream STRB output --
--
s2mm_strm_tlast : In std_logic; --
-- AXI Stream LAST output --
--------------------------------------------------------------------------------
-- Stream Out to S2MM DRE -------------------------------------------------------
--
drc2scatter_tready : In Std_logic; --
-- S2MM DRE Stream READY input --
--
scatter2drc_tvalid : Out std_logic; --
-- S2MM DRE VALID Output --
--
scatter2drc_tdata : Out std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- S2MM DRE data output --
--
scatter2drc_tstrb : Out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- S2MM DRE STRB output --
--
scatter2drc_tlast : Out std_logic; --
-- S2MM DRE LAST output --
--
scatter2drc_flush : Out std_logic; --
-- S2MM DRE LAST output --
--
scatter2drc_eop : Out std_logic; --
-- S2MM DRE End of Packet marker --
--------------------------------------------------------------------------------
-- Premature TLAST assertion error flag ---------------------------------------
--
scatter2drc_tlast_error : Out std_logic --
-- When asserted, this indicates the scatter Engine detected --
-- a Early/Late TLAST assertion on the incoming data stream --
-- relative to the commands given to the DataMover Cmd FIFO. --
-------------------------------------------------------------------------------
);
end entity axi_datamover_s2mm_scatter;
architecture implementation of axi_datamover_s2mm_scatter is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function declaration ----------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_index
--
-- Function Description:
-- This function calculates the bus bit index corresponding
-- to the MSB of the Slice lane index input and the Slice width.
--
-------------------------------------------------------------------
function get_start_index (lane_index : integer;
lane_width : integer)
return integer is
Variable bit_index_start : Integer := 0;
begin
bit_index_start := lane_index*lane_width;
return(bit_index_start);
end function get_start_index;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_index
--
-- Function Description:
-- This function calculates the bus bit index corresponding
-- to the LSB of the Slice lane index input and the Slice width.
--
-------------------------------------------------------------------
function get_end_index (lane_index : integer;
lane_width : integer)
return integer is
Variable bit_index_end : Integer := 0;
begin
bit_index_end := (lane_index*lane_width) + (lane_width-1);
return(bit_index_end);
end function get_end_index;
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_num_offset_bits
--
-- Function Description:
-- This function calculates the number of bits needed for specifying
-- a byte lane offset for the input transfer data width.
--
-------------------------------------------------------------------
function func_num_offset_bits (stream_dwidth_value : integer) return integer is
Variable num_offset_bits_needed : Integer range 1 to 7 := 1;
begin
case stream_dwidth_value is
when 8 => -- 1 byte lanes
num_offset_bits_needed := 1;
when 16 => -- 2 byte lanes
num_offset_bits_needed := 1;
when 32 => -- 4 byte lanes
num_offset_bits_needed := 2;
when 64 => -- 8 byte lanes
num_offset_bits_needed := 3;
when 128 => -- 16 byte lanes
num_offset_bits_needed := 4;
when 256 => -- 32 byte lanes
num_offset_bits_needed := 5;
when 512 => -- 64 byte lanes
num_offset_bits_needed := 6;
when others => -- 1024 bits with 128 byte lanes
num_offset_bits_needed := 7;
end case;
Return (num_offset_bits_needed);
end function func_num_offset_bits;
function func_fifo_prim (stream_dwidth_value : integer) return integer is
Variable prim_needed : Integer range 0 to 2 := 1;
begin
case stream_dwidth_value is
when 8 => -- 1 byte lanes
prim_needed := 2;
when 16 => -- 2 byte lanes
prim_needed := 2;
when 32 => -- 4 byte lanes
prim_needed := 2;
when 64 => -- 8 byte lanes
prim_needed := 2;
when 128 => -- 16 byte lanes
prim_needed := 0;
when others => -- 256 bits and above
prim_needed := 0;
end case;
Return (prim_needed);
end function func_fifo_prim;
-- Constant Declarations -------------------------------------------------
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '0';
Constant BYTE_WIDTH : integer := 8; -- bits
Constant STRM_NUM_BYTE_LANES : integer := C_STREAM_DWIDTH/BYTE_WIDTH;
Constant STRM_STRB_WIDTH : integer := STRM_NUM_BYTE_LANES;
Constant SLICE_WIDTH : integer := BYTE_WIDTH+2; -- 8 data bits plus Strobe plus TLAST bit
Constant SLICE_STROBE_INDEX : integer := (BYTE_WIDTH-1)+1;
Constant SLICE_TLAST_INDEX : integer := SLICE_STROBE_INDEX+1;
Constant ZEROED_SLICE : std_logic_vector(SLICE_WIDTH-1 downto 0) := (others => '0');
Constant CMD_BTT_WIDTH : Integer := C_BTT_USED;
Constant BTT_OF_ZERO : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
Constant MAX_BTT_INCR : integer := C_STREAM_DWIDTH/8;
Constant NUM_OFFSET_BITS : integer := func_num_offset_bits(C_STREAM_DWIDTH);
-- Minimum Number of bits needed to represent the byte lane position within the Stream Data
Constant NUM_INCR_BITS : integer := NUM_OFFSET_BITS+1;
-- Minimum Number of bits needed to represent the maximum per dbeat increment value
Constant OFFSET_ONE : unsigned(NUM_OFFSET_BITS-1 downto 0) := TO_UNSIGNED(1 , NUM_OFFSET_BITS);
Constant OFFSET_MAX : unsigned(NUM_OFFSET_BITS-1 downto 0) := TO_UNSIGNED(STRM_STRB_WIDTH - 1 , NUM_OFFSET_BITS);
Constant INCR_MAX : unsigned(NUM_INCR_BITS-1 downto 0) := TO_UNSIGNED(MAX_BTT_INCR , NUM_INCR_BITS);
Constant MSSAI_INDEX_WIDTH : integer := NUM_OFFSET_BITS;
Constant TSTRB_FIFO_DEPTH : integer := 16;
Constant TSTRB_FIFO_DWIDTH : integer := 1 + -- TLAST Bit
1 + -- EOF Bit
1 + -- Freeze Bit
MSSAI_INDEX_WIDTH + -- MSSAI Value
STRM_STRB_WIDTH*C_ENABLE_S2MM_TKEEP ; -- Strobe Value
Constant USE_SYNC_FIFO : integer := 0;
Constant REG_FIFO_PRIM : integer := 0;
Constant BRAM_FIFO_PRIM : integer := 1;
Constant SRL_FIFO_PRIM : integer := 2;
Constant FIFO_PRIM : integer := func_fifo_prim(C_STREAM_DWIDTH);
Constant FIFO_TLAST_INDEX : integer := TSTRB_FIFO_DWIDTH-1;
Constant FIFO_EOF_INDEX : integer := FIFO_TLAST_INDEX-1;
Constant FIFO_FREEZE_INDEX : integer := FIFO_EOF_INDEX-1;
Constant FIFO_MSSAI_MS_INDEX : integer := FIFO_FREEZE_INDEX-1;
Constant FIFO_MSSAI_LS_INDEX : integer := FIFO_MSSAI_MS_INDEX - (MSSAI_INDEX_WIDTH-1);
Constant FIFO_TSTRB_MS_INDEX : integer := FIFO_MSSAI_LS_INDEX-1;
Constant FIFO_TSTRB_LS_INDEX : integer := 0;
-- Types ------------------------------------------------------------------
type byte_lane_type is array(STRM_NUM_BYTE_LANES-1 downto 0) of
std_logic_vector(SLICE_WIDTH-1 downto 0);
-- Signal Declarations ---------------------------------------------------
signal sig_good_strm_dbeat : std_logic := '0';
signal sig_strm_tready : std_logic := '0';
signal sig_strm_tvalid : std_logic := '0';
signal sig_strm_tdata : std_logic_vector(C_STREAM_DWIDTH-1 downto 0) := (others => '0');
signal sig_strm_tstrb : std_logic_vector(STRM_NUM_BYTE_LANES-1 downto 0) := (others => '0');
signal sig_strm_tlast : std_logic := '0';
signal sig_drc2scatter_tready : std_logic := '0';
signal sig_scatter2drc_tvalid : std_logic := '0';
signal sig_scatter2drc_tdata : std_logic_vector(C_STREAM_DWIDTH-1 downto 0) := (others => '0');
signal sig_scatter2drc_tstrb : std_logic_vector(STRM_NUM_BYTE_LANES-1 downto 0) := (others => '0');
signal sig_scatter2drc_tlast : std_logic := '0';
signal sig_scatter2drc_flush : std_logic := '0';
signal sig_valid_dre_output_dbeat : std_logic := '0';
signal sig_ld_cmd : std_logic := '0';
signal sig_cmd_full : std_logic := '0';
signal sig_cmd_empty : std_logic := '0';
signal sig_drc2scatter_push_cmd : std_logic := '0';
signal sig_drc2scatter_btt : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_drc2scatter_eof : std_logic := '0';
signal sig_btt_offset_slice : unsigned(NUM_OFFSET_BITS-1 downto 0) := (others => '0');
signal sig_curr_strt_offset : unsigned(NUM_OFFSET_BITS-1 downto 0) := (others => '0');
signal sig_next_strt_offset : unsigned(NUM_OFFSET_BITS-1 downto 0) := (others => '0');
signal sig_next_dre_src_align : std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_curr_dbeat_offset : std_logic_vector(NUM_OFFSET_BITS-1 downto 0) := (others => '0');
signal sig_cmd_sof : std_logic := '0';
signal sig_curr_eof_reg : std_logic := '0';
signal sig_btt_cntr : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_cntr_dup : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_ld_btt_cntr : std_logic := '0';
signal sig_decr_btt_cntr : std_logic := '0';
signal sig_btt_cntr_decr_value : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_stb_gen_slice : std_logic_vector(NUM_INCR_BITS-1 downto 0) := (others => '0');
signal sig_btt_eq_0 : std_logic := '0';
signal sig_btt_lteq_max_first_incr : std_logic := '0';
signal sig_btt_gteq_max_incr : std_logic := '0';
signal sig_max_first_increment : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_cntr_prv : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_eq_0_pre_reg : std_logic := '0';
signal sig_set_tlast_error : std_logic := '0';
signal sig_tlast_error_over : std_logic := '0';
signal sig_tlast_error_under : std_logic := '0';
signal sig_tlast_error_exact : std_logic := '0';
signal sig_tlast_error_reg : std_logic := '0';
signal sig_stbgen_tstrb : std_logic_vector(STRM_NUM_BYTE_LANES-1 downto 0) := (others => '0');
signal sig_tlast_error_out : std_logic := '0';
signal sig_freeze_it : std_logic := '0';
signal sig_tstrb_fifo_data_in : std_logic_vector(TSTRB_FIFO_DWIDTH-1 downto 0);
signal sig_tstrb_fifo_data_out : std_logic_vector(TSTRB_FIFO_DWIDTH-1 downto 0);
signal slice_insert_data : std_logic_vector(TSTRB_FIFO_DWIDTH-1 downto 0);
signal slice_insert_ready : std_logic := '0';
signal slice_insert_valid : std_logic := '0';
signal sig_tstrb_fifo_rdy : std_logic := '0';
signal sig_tstrb_fifo_valid : std_logic := '0';
signal sig_valid_fifo_ld : std_logic := '0';
signal sig_fifo_tlast_out : std_logic := '0';
signal sig_fifo_eof_out : std_logic := '0';
signal sig_fifo_freeze_out : std_logic := '0';
signal sig_fifo_tstrb_out : std_logic_vector(STRM_STRB_WIDTH-1 downto 0);
signal sig_tstrb_valid : std_logic := '0';
signal sig_get_tstrb : std_logic := '0';
signal sig_tstrb_fifo_empty : std_logic := '0';
signal sig_clr_fifo_ld_regs : std_logic := '0';
signal ld_btt_cntr_reg1 : std_logic := '0';
signal ld_btt_cntr_reg2 : std_logic := '0';
signal ld_btt_cntr_reg3 : std_logic := '0';
signal sig_btt_eq_0_reg : std_logic := '0';
signal sig_tlast_ld_beat : std_logic := '0';
signal sig_eof_ld_dbeat : std_logic := '0';
signal sig_strb_error : std_logic := '0';
signal sig_mssa_index : std_logic_vector(MSSAI_INDEX_WIDTH-1 downto 0) := (others => '0');
signal sig_tstrb_fifo_mssai_in : std_logic_vector(MSSAI_INDEX_WIDTH-1 downto 0);
signal sig_tstrb_fifo_mssai_out : std_logic_vector(MSSAI_INDEX_WIDTH-1 downto 0);
signal sig_fifo_mssai : unsigned(NUM_OFFSET_BITS-1 downto 0) := (others => '0');
signal sig_clr_tstrb_fifo : std_logic := '0';
signal sig_eop_sent : std_logic := '0';
signal sig_eop_sent_reg : std_logic := '0';
signal sig_scatter2drc_eop : std_logic := '0';
signal sig_set_packet_done : std_logic := '0';
signal sig_tlast_sent : std_logic := '0';
signal sig_gated_fifo_freeze_out : std_logic := '0';
signal sig_cmd_side_ready : std_logic := '0';
signal sig_eop_halt_xfer : std_logic := '0';
signal sig_err_underflow_reg : std_logic := '0';
signal sig_assert_valid_out : std_logic := '0';
-- Attribute KEEP : string; -- declaration
-- Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
-- Attribute KEEP of sig_btt_cntr_dup : signal is "TRUE"; -- definition
-- Attribute EQUIVALENT_REGISTER_REMOVAL of sig_btt_cntr_dup : signal is "no";
begin --(architecture implementation)
-- Output stream assignments (to DRE) -----------------
sig_drc2scatter_tready <= drc2scatter_tready ;
scatter2drc_tvalid <= sig_scatter2drc_tvalid ;
scatter2drc_tdata <= sig_scatter2drc_tdata ;
scatter2drc_tstrb <= sig_scatter2drc_tstrb ;
scatter2drc_tlast <= sig_scatter2drc_tlast ;
scatter2drc_flush <= sig_scatter2drc_flush ;
scatter2drc_eop <= sig_scatter2drc_eop ;
-- DRC Control ----------------------------------------
scatter2drc_cmd_ready <= sig_cmd_empty;
sig_drc2scatter_push_cmd <= drc2scatter_push_cmd ;
sig_drc2scatter_btt <= drc2scatter_btt ;
sig_drc2scatter_eof <= drc2scatter_eof ;
-- Next source alignment control to the S2Mm DRE ------
scatter2drc_src_align <= sig_next_dre_src_align;
-- TLAST error flag output ----------------------------
scatter2drc_tlast_error <= sig_tlast_error_out;
-- Data to DRE output ---------------------------------
sig_scatter2drc_tdata <= sig_strm_tdata ;
sig_scatter2drc_tvalid <= sig_assert_valid_out and -- Asserting the valid output
sig_cmd_side_ready; -- and the tstrb fifo has an entry pending
-- Create flag indicating a qualified output stream data beat to the DRE
sig_valid_dre_output_dbeat <= sig_drc2scatter_tready and
sig_scatter2drc_tvalid;
-- Databeat DRE FLUSH output --------------------------
sig_scatter2drc_flush <= '0';
sig_ld_cmd <= sig_drc2scatter_push_cmd and
not(sig_cmd_full);
sig_next_dre_src_align <= STD_LOGIC_VECTOR(RESIZE(sig_next_strt_offset,
C_DRE_ALIGN_WIDTH));
sig_good_strm_dbeat <= sig_strm_tready and
sig_assert_valid_out ;
-- Set the valid out flag
sig_assert_valid_out <= (sig_strm_tvalid or -- there is valid data in the Skid buffer output register
sig_err_underflow_reg); -- or an underflow error has been detected and needs to flush
--- Input Stream Skid Buffer with Special Functions ------------------------------
------------------------------------------------------------
-- Instance: I_MSSAI_SKID_BUF
--
-- Description:
-- Instance for the MSSAI Skid Buffer needed for Fmax
-- closure when the Scatter Module is included in the DataMover
-- S2MM.
--
------------------------------------------------------------
I_MSSAI_SKID_BUF : entity axi_datamover_v5_1.axi_datamover_mssai_skid_buf
generic map (
C_WDATA_WIDTH => C_STREAM_DWIDTH ,
C_INDEX_WIDTH => MSSAI_INDEX_WIDTH
)
port map (
-- System Ports
aclk => primary_aclk ,
arst => mmap_reset ,
-- Shutdown control (assert for 1 clk pulse)
skid_stop => LOGIC_LOW ,
-- Slave Side (Stream Data Input)
s_valid => s2mm_strm_tvalid ,
s_ready => s2mm_strm_tready ,
s_data => s2mm_strm_tdata ,
s_strb => s2mm_strm_tstrb ,
s_last => s2mm_strm_tlast ,
-- Master Side (Stream Data Output
m_valid => sig_strm_tvalid ,
m_ready => sig_strm_tready ,
m_data => sig_strm_tdata ,
m_strb => sig_strm_tstrb ,
m_last => sig_strm_tlast ,
m_mssa_index => sig_mssa_index ,
m_strb_error => sig_strb_error
);
-------------------------------------------------------------
-- packet Done Logic
-------------------------------------------------------------
sig_set_packet_done <= sig_eop_sent_reg;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CMD_FLAG_REG
--
-- Process Description:
-- Implement the Scatter transfer command full/empty tracking
-- flops
--
-------------------------------------------------------------
IMP_CMD_FLAG_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_tlast_sent = '1') then
sig_cmd_full <= '0';
sig_cmd_empty <= '1';
elsif (sig_ld_cmd = '1') then
sig_cmd_full <= '1';
sig_cmd_empty <= '0';
else
null; -- hold current state
end if;
end if;
end process IMP_CMD_FLAG_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CURR_OFFSET_REG
--
-- Process Description:
-- Implements the register holding the current starting
-- byte position offset of the first byte of the current
-- command. This implementation assumes that only the first
-- databeat can be unaligned from Byte position 0.
--
-------------------------------------------------------------
IMP_CURR_OFFSET_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_set_packet_done = '1' or
sig_valid_fifo_ld = '1') then
sig_curr_strt_offset <= (others => '0');
elsif (sig_ld_cmd = '1') then
sig_curr_strt_offset <= sig_next_strt_offset;
else
null; -- Hold current state
end if;
end if;
end process IMP_CURR_OFFSET_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_NEXT_OFFSET_REG
--
-- Process Description:
-- Implements the register holding the predicted byte position
-- offset of the first byte of the next command. If the current
-- command has EOF set, then the next command's first data input
-- byte offset must be at byte lane 0 in the input stream.
--
-------------------------------------------------------------
IMP_NEXT_OFFSET_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_set_packet_done = '1' or
STRM_NUM_BYTE_LANES = 1) then
sig_next_strt_offset <= (others => '0');
elsif (sig_ld_cmd = '1') then
sig_next_strt_offset <= sig_next_strt_offset + sig_btt_offset_slice;
else
null; -- Hold current state
end if;
end if;
end process IMP_NEXT_OFFSET_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FIFO_MSSAI_REG
--
-- Process Description:
-- Implements the register holding the predicted byte position
-- offset of the last valid byte defined by the current command.
--
-------------------------------------------------------------
IMP_FIFO_MSSAI_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_set_packet_done = '1' or
STRM_NUM_BYTE_LANES = 1 ) then
sig_fifo_mssai <= (others => '0');
elsif (ld_btt_cntr_reg1 = '1' and
ld_btt_cntr_reg2 = '0') then
sig_fifo_mssai <= sig_next_strt_offset - OFFSET_ONE;
else
null; -- Hold current state
end if;
end if;
end process IMP_FIFO_MSSAI_REG;
-- Strobe Generation Logic ------------------------------------------------
sig_curr_dbeat_offset <= STD_LOGIC_VECTOR(sig_curr_strt_offset);
------------------------------------------------------------
-- Instance: I_SCATTER_STROBE_GEN
--
-- Description:
-- Strobe generator instance. Generates strobe bits for
-- a designated starting byte lane and the number of bytes
-- to be transfered (for that data beat).
--
------------------------------------------------------------
I_SCATTER_STROBE_GEN : entity axi_datamover_v5_1.axi_datamover_strb_gen2
generic map (
C_OP_MODE => 0 , -- 0 = Offset/Length mode
C_STRB_WIDTH => STRM_NUM_BYTE_LANES ,
C_OFFSET_WIDTH => NUM_OFFSET_BITS ,
C_NUM_BYTES_WIDTH => NUM_INCR_BITS
)
port map (
start_addr_offset => sig_curr_dbeat_offset ,
end_addr_offset => sig_curr_dbeat_offset , -- not used in op mode 0
num_valid_bytes => sig_btt_stb_gen_slice , -- not used in op mode 1
strb_out => sig_stbgen_tstrb
);
-- BTT Counter stuff ------------------------------------------------------
sig_btt_stb_gen_slice <= STD_LOGIC_VECTOR(INCR_MAX)
when (sig_btt_gteq_max_incr = '1')
else '0' & STD_LOGIC_VECTOR(sig_btt_cntr(NUM_OFFSET_BITS-1 downto 0));
sig_btt_offset_slice <= UNSIGNED(sig_drc2scatter_btt(NUM_OFFSET_BITS-1 downto 0));
sig_btt_lteq_max_first_incr <= '1'
when (sig_btt_cntr <= RESIZE(sig_max_first_increment, CMD_BTT_WIDTH)) -- more timing improv
Else '0'; -- more timing improv
-- more timing improv
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_MAX_FIRST_INCR_REG
--
-- Process Description:
-- Implements the Max first increment register value.
--
-------------------------------------------------------------
IMP_MAX_FIRST_INCR_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_max_first_increment <= (others => '0');
Elsif (sig_ld_cmd = '1') Then
sig_max_first_increment <= RESIZE(TO_UNSIGNED(MAX_BTT_INCR,NUM_INCR_BITS) -
RESIZE(sig_next_strt_offset,NUM_INCR_BITS),
CMD_BTT_WIDTH);
Elsif (sig_valid_fifo_ld = '1') Then
sig_max_first_increment <= RESIZE(TO_UNSIGNED(MAX_BTT_INCR,NUM_INCR_BITS), CMD_BTT_WIDTH);
else
null; -- hold current value
end if;
end if;
end process IMP_MAX_FIRST_INCR_REG;
sig_btt_cntr_decr_value <= sig_btt_cntr
When (sig_btt_lteq_max_first_incr = '1')
Else sig_max_first_increment;
sig_ld_btt_cntr <= sig_ld_cmd ;
sig_decr_btt_cntr <= not(sig_btt_eq_0) and
sig_valid_fifo_ld;
-- New intermediate value for reduced Timing path
sig_btt_cntr_prv <= UNSIGNED(sig_drc2scatter_btt)
when (sig_ld_btt_cntr = '1')
-- Else sig_btt_cntr_dup-sig_btt_cntr_decr_value;
Else sig_btt_cntr-sig_btt_cntr_decr_value;
sig_btt_eq_0_pre_reg <= '1'
when (sig_btt_cntr_prv = BTT_OF_ZERO)
Else '0';
-- sig_btt_eq_0 <= '1'
-- when (sig_btt_cntr = BTT_OF_ZERO)
-- Else '0';
sig_btt_gteq_max_incr <= '1'
when (sig_btt_cntr >= TO_UNSIGNED(MAX_BTT_INCR, CMD_BTT_WIDTH))
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_BTT_CNTR_REG
--
-- Process Description:
-- Implements the registered portion of the BTT Counter. The
-- BTT Counter has been recoded this way to minimize long
-- timing paths in the btt -> strobgen-> EOP Demux path.
--
-------------------------------------------------------------
IMP_BTT_CNTR_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_eop_sent = '1') then
sig_btt_cntr <= (others => '0');
-- sig_btt_cntr_dup <= (others => '0');
sig_btt_eq_0 <= '1';
elsif (sig_ld_btt_cntr = '1' or
sig_decr_btt_cntr = '1') then
sig_btt_cntr <= sig_btt_cntr_prv;
-- sig_btt_cntr_dup <= sig_btt_cntr_prv;
sig_btt_eq_0 <= sig_btt_eq_0_pre_reg;
else
Null; -- Hold current state
end if;
end if;
end process IMP_BTT_CNTR_REG;
-- IMP_BTT_CNTR_REG : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1' or
-- sig_eop_sent = '1') then
-- sig_btt_cntr <= (others => '0');
---- sig_btt_eq_0 <= '1';
-- elsif (sig_ld_btt_cntr = '1') then
-- sig_btt_cntr <= UNSIGNED(sig_drc2scatter_btt); --sig_btt_cntr_prv;
---- sig_btt_eq_0 <= sig_btt_eq_0_pre_reg;
-- elsif (sig_decr_btt_cntr = '1') then
-- sig_btt_cntr <= sig_btt_cntr-sig_btt_cntr_decr_value; --sig_btt_cntr_prv;
---- sig_btt_eq_0 <= sig_btt_eq_0_pre_reg;
-- else
-- Null; -- Hold current state
-- end if;
-- end if;
-- end process IMP_BTT_CNTR_REG;
------------------------------------------------------------------------
-- DRE TVALID Gating logic
------------------------------------------------------------------------
sig_cmd_side_ready <= not(sig_tstrb_fifo_empty) and
not(sig_eop_halt_xfer);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_EOP_HALT_FLOP
--
-- Process Description:
-- Implements a flag that is set when an end of packet is sent
-- to the DRE and cleared after the TSTRB FIFO has been reset.
-- This flag inhibits the TVALID sent to the DRE.
-------------------------------------------------------------
IMP_EOP_HALT_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_eop_sent = '1') then
sig_eop_halt_xfer <= '1';
Elsif (sig_valid_fifo_ld = '1') Then
sig_eop_halt_xfer <= '0';
else
null; -- hold current state
end if;
end if;
end process IMP_EOP_HALT_FLOP;
------------------------------------------------------------------------
-- TSTRB FIFO Logic
------------------------------------------------------------------------
sig_tlast_ld_beat <= sig_btt_lteq_max_first_incr;
sig_eof_ld_dbeat <= sig_curr_eof_reg and sig_tlast_ld_beat;
-- Set the MSSAI offset value to the maximum for non-tlast dbeat
-- case, otherwise use the calculated value for the TLSAT case.
sig_tstrb_fifo_mssai_in <= STD_LOGIC_VECTOR(sig_fifo_mssai)
when (sig_tlast_ld_beat = '1')
else STD_LOGIC_VECTOR(OFFSET_MAX);
GEN_S2MM_TKEEP_ENABLE3 : if C_ENABLE_S2MM_TKEEP = 1 generate
begin
-- Merge the various pieces to go through the TSTRB FIFO into a single vector
sig_tstrb_fifo_data_in <= sig_tlast_ld_beat & -- the last beat of this sub-packet
sig_eof_ld_dbeat & -- the end of the whole packet
sig_freeze_it & -- A sub-packet boundary
sig_tstrb_fifo_mssai_in & -- the index of EOF byte position
sig_stbgen_tstrb; -- The calculated strobes
end generate GEN_S2MM_TKEEP_ENABLE3;
GEN_S2MM_TKEEP_DISABLE3 : if C_ENABLE_S2MM_TKEEP = 0 generate
begin
-- Merge the various pieces to go through the TSTRB FIFO into a single vector
sig_tstrb_fifo_data_in <= sig_tlast_ld_beat & -- the last beat of this sub-packet
sig_eof_ld_dbeat & -- the end of the whole packet
sig_freeze_it & -- A sub-packet boundary
sig_tstrb_fifo_mssai_in; --& -- the index of EOF byte position
--sig_stbgen_tstrb; -- The calculated strobes
end generate GEN_S2MM_TKEEP_DISABLE3;
-- FIFO Load control
sig_valid_fifo_ld <= sig_tstrb_fifo_valid and
sig_tstrb_fifo_rdy;
GEN_S2MM_TKEEP_ENABLE4 : if C_ENABLE_S2MM_TKEEP = 1 generate
begin
-- Rip the various pieces from the FIFO output
sig_fifo_tlast_out <= sig_tstrb_fifo_data_out(FIFO_TLAST_INDEX) ;
sig_fifo_eof_out <= sig_tstrb_fifo_data_out(FIFO_EOF_INDEX) ;
sig_fifo_freeze_out <= sig_tstrb_fifo_data_out(FIFO_FREEZE_INDEX);
sig_tstrb_fifo_mssai_out <= sig_tstrb_fifo_data_out(FIFO_MSSAI_MS_INDEX downto FIFO_MSSAI_LS_INDEX);
sig_fifo_tstrb_out <= sig_tstrb_fifo_data_out(FIFO_TSTRB_MS_INDEX downto FIFO_TSTRB_LS_INDEX);
end generate GEN_S2MM_TKEEP_ENABLE4;
GEN_S2MM_TKEEP_DISABLE4 : if C_ENABLE_S2MM_TKEEP = 0 generate
begin
-- Rip the various pieces from the FIFO output
sig_fifo_tlast_out <= sig_tstrb_fifo_data_out(FIFO_TLAST_INDEX) ;
sig_fifo_eof_out <= sig_tstrb_fifo_data_out(FIFO_EOF_INDEX) ;
sig_fifo_freeze_out <= sig_tstrb_fifo_data_out(FIFO_FREEZE_INDEX);
sig_tstrb_fifo_mssai_out <= sig_tstrb_fifo_data_out(FIFO_MSSAI_MS_INDEX downto FIFO_MSSAI_LS_INDEX);
sig_fifo_tstrb_out <= (others => '1');
end generate GEN_S2MM_TKEEP_DISABLE4;
-- FIFO Read Control
sig_get_tstrb <= sig_valid_dre_output_dbeat ;
sig_tstrb_fifo_valid <= ld_btt_cntr_reg2 or
(ld_btt_cntr_reg3 and
not(sig_btt_eq_0));
sig_clr_fifo_ld_regs <= (sig_tlast_ld_beat and
sig_valid_fifo_ld) or
sig_eop_sent;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FIFO_LD_1
--
-- Process Description:
-- Implements the fifo loading control flop stage 1
--
-------------------------------------------------------------
IMP_FIFO_LD_1 : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_clr_fifo_ld_regs = '1') then
ld_btt_cntr_reg1 <= '0';
Elsif (sig_ld_btt_cntr = '1') Then
ld_btt_cntr_reg1 <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_FIFO_LD_1;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FIFO_LD_2
--
-- Process Description:
-- Implements special fifo loading control flops
--
-------------------------------------------------------------
IMP_FIFO_LD_2 : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_clr_fifo_ld_regs = '1') then
ld_btt_cntr_reg2 <= '0';
ld_btt_cntr_reg3 <= '0';
Elsif (sig_tstrb_fifo_rdy = '1') Then
ld_btt_cntr_reg2 <= ld_btt_cntr_reg1;
ld_btt_cntr_reg3 <= ld_btt_cntr_reg2 or
ld_btt_cntr_reg3; -- once set, keep it set until cleared
else
null; -- Hold current state
end if;
end if;
end process IMP_FIFO_LD_2;
HIGHER_DATAWIDTH : if TSTRB_FIFO_DWIDTH > 40 generate
begin
SLICE_INSERTION : entity axi_datamover_v5_1.axi_datamover_slice
generic map (
C_DATA_WIDTH => TSTRB_FIFO_DWIDTH
)
port map (
ACLK => primary_aclk,
ARESET => mmap_reset,
-- Slave side
S_PAYLOAD_DATA => sig_tstrb_fifo_data_in,
S_VALID => sig_tstrb_fifo_valid,
S_READY => sig_tstrb_fifo_rdy,
-- Master side
M_PAYLOAD_DATA => slice_insert_data,
M_VALID => slice_insert_valid,
M_READY => slice_insert_ready
);
------------------------------------------------------------
-- Instance: I_TSTRB_FIFO
--
-- Description:
-- Instance for the TSTRB FIFO
--
------------------------------------------------------------
I_TSTRB_FIFO : entity axi_datamover_v5_1.axi_datamover_fifo
generic map (
C_DWIDTH => TSTRB_FIFO_DWIDTH ,
C_DEPTH => TSTRB_FIFO_DEPTH ,
C_IS_ASYNC => USE_SYNC_FIFO ,
C_PRIM_TYPE => FIFO_PRIM ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => sig_clr_tstrb_fifo ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => slice_insert_valid, --sig_tstrb_fifo_valid ,
fifo_wr_tready => slice_insert_ready, --sig_tstrb_fifo_rdy ,
fifo_wr_tdata => slice_insert_data, --sig_tstrb_fifo_data_in,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_tstrb_valid ,
fifo_rd_tready => sig_get_tstrb ,
fifo_rd_tdata => sig_tstrb_fifo_data_out ,
fifo_rd_empty => sig_tstrb_fifo_empty
);
end generate HIGHER_DATAWIDTH;
LOWER_DATAWIDTH : if TSTRB_FIFO_DWIDTH <= 40 generate
begin
------------------------------------------------------------
-- Instance: I_TSTRB_FIFO
--
-- Description:
-- Instance for the TSTRB FIFO
--
------------------------------------------------------------
I_TSTRB_FIFO : entity axi_datamover_v5_1.axi_datamover_fifo
generic map (
C_DWIDTH => TSTRB_FIFO_DWIDTH ,
C_DEPTH => TSTRB_FIFO_DEPTH ,
C_IS_ASYNC => USE_SYNC_FIFO ,
C_PRIM_TYPE => FIFO_PRIM ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => sig_clr_tstrb_fifo ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_tstrb_fifo_valid ,
fifo_wr_tready => sig_tstrb_fifo_rdy ,
fifo_wr_tdata => sig_tstrb_fifo_data_in,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_tstrb_valid ,
fifo_rd_tready => sig_get_tstrb ,
fifo_rd_tdata => sig_tstrb_fifo_data_out ,
fifo_rd_empty => sig_tstrb_fifo_empty
);
end generate LOWER_DATAWIDTH;
------------------------------------------------------------
-- TSTRB FIFO Clear Logic
------------------------------------------------------------
-- Special TSTRB FIFO Clear Logic to clean out any residue
-- once EOP has been sent out to DRE. This is primarily
-- needed in Indeterminate BTT mode but is also included in
-- the non-Indeterminate BTT mode for a more robust design.
sig_clr_tstrb_fifo <= mmap_reset or
sig_set_packet_done;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_EOP_SENT_REG
--
-- Process Description:
-- Register the EOP being sent out to the DRE stage. This
-- is used to clear the TSTRB FIFO of any residue.
--
-------------------------------------------------------------
IMP_EOP_SENT_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_eop_sent_reg = '1') then
sig_eop_sent_reg <= '0';
else
sig_eop_sent_reg <= sig_eop_sent;
end if;
end if;
end process IMP_EOP_SENT_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_EOF_REG
--
-- Process Description:
-- Implement a sample and hold flop for the command EOF
-- The Commanded EOF is used when C_ENABLE_INDET_BTT = 0.
-------------------------------------------------------------
IMP_EOF_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_set_packet_done = '1') then
sig_curr_eof_reg <= '0';
elsif (sig_ld_cmd = '1') then
sig_curr_eof_reg <= sig_drc2scatter_eof;
else
null; -- hold current state
end if;
end if;
end process IMP_EOF_REG;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OMIT_INDET_BTT
--
-- If Generate Description:
-- Implements the Scatter Freeze Register Controls plus
-- other logic needed when Indeterminate BTT Mode is not enabled.
--
--
--
------------------------------------------------------------
GEN_OMIT_INDET_BTT : if (C_ENABLE_INDET_BTT = 0) generate
signal lsig_eop_matches_ms_strb : std_logic := '0';
begin
sig_eop_sent <= sig_scatter2drc_eop and
sig_valid_dre_output_dbeat;
sig_tlast_sent <= sig_scatter2drc_tlast and
sig_valid_dre_output_dbeat;
sig_freeze_it <= not(sig_stbgen_tstrb(STRM_NUM_BYTE_LANES-1)) and -- ms strobe not set
sig_valid_fifo_ld and -- tstrb fifo being loaded
not(sig_curr_eof_reg); -- Current input cmd does not have eof set
-- Assign the TREADY out to the Stream In
sig_strm_tready <= '0'
when (sig_gated_fifo_freeze_out = '1' or
sig_cmd_side_ready = '0')
Else sig_drc2scatter_tready;
-- Without Indeterminate BTT, FIFO Freeze does not
-- need to be gated.
sig_gated_fifo_freeze_out <= sig_fifo_freeze_out;
-- Strobe outputs are always generated from the input command
-- with Indeterminate BTT omitted. Stream input Strobes are not
-- sent to output.
sig_scatter2drc_tstrb <= sig_fifo_tstrb_out;
-- The EOF marker is generated from the input command
-- with Indeterminate BTT omitted. Stream input TLAST is monitored
-- but not sent to output to DRE.
sig_scatter2drc_eop <= sig_fifo_eof_out and
sig_scatter2drc_tvalid;
-- TLast output marker always generated from the input command
sig_scatter2drc_tlast <= sig_fifo_tlast_out and
sig_scatter2drc_tvalid;
--- TLAST Error Detection -------------------------------------------------
sig_tlast_error_out <= sig_set_tlast_error or
sig_tlast_error_reg;
-- Compare the Most significant Asserted TSTRB from the TSTRB FIFO
-- with that from the Input Skid Buffer
lsig_eop_matches_ms_strb <= '1'
when (sig_tstrb_fifo_mssai_out = sig_mssa_index)
Else '0';
-- Detect the case when the calculated end of packet
-- marker preceeds the received end of packet marker
-- and a freeze condition is not enabled
sig_tlast_error_over <= '1'
when (sig_valid_dre_output_dbeat = '1' and
sig_fifo_freeze_out = '0' and
sig_fifo_eof_out = '1' and
sig_strm_tlast = '0')
Else '0';
-- Detect the case when the received end of packet marker preceeds
-- the calculated end of packet
-- and a freeze condition is not enabled
sig_tlast_error_under <= '1'
when (sig_valid_dre_output_dbeat = '1' and
sig_fifo_freeze_out = '0' and
sig_fifo_eof_out = '0' and
sig_strm_tlast = '1')
Else '0';
-- Detect the case when the received end of packet marker occurs
-- in the same beat as the calculated end of packet but the most
-- significant received strobe that is asserted does not match
-- the most significant calcualted strobe that is asserted.
-- Also, a freeze condition is not enabled
sig_tlast_error_exact <= '1'
When (sig_valid_dre_output_dbeat = '1' and
sig_fifo_freeze_out = '0' and
sig_fifo_eof_out = '1' and
sig_strm_tlast = '1' and
lsig_eop_matches_ms_strb = '0')
Else '0';
-- Combine all of the possible error conditions
sig_set_tlast_error <= sig_tlast_error_over or
sig_tlast_error_under or
sig_tlast_error_exact;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_TLAST_ERROR_REG
--
-- Process Description:
--
--
-------------------------------------------------------------
IMP_TLAST_ERROR_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_tlast_error_reg <= '0';
elsif (sig_set_tlast_error = '1') then
sig_tlast_error_reg <= '1';
else
Null; -- Hold current State
end if;
end if;
end process IMP_TLAST_ERROR_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_TLAST_ERROR_UNDER_REG
--
-- Process Description:
-- Sample and Hold flop for the case when an underrun is
-- detected. This flag is used to force a a tvalid output.
--
-------------------------------------------------------------
IMP_TLAST_ERROR_UNDER_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_err_underflow_reg <= '0';
elsif (sig_tlast_error_under = '1') then
sig_err_underflow_reg <= '1';
else
Null; -- Hold current State
end if;
end if;
end process IMP_TLAST_ERROR_UNDER_REG;
end generate GEN_OMIT_INDET_BTT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INDET_BTT
--
-- If Generate Description:
-- Implements the Scatter Freeze Register and Controls plus
-- other logic needed to support the Indeterminate BTT Mode
-- of Operation.
--
--
------------------------------------------------------------
GEN_INDET_BTT : if (C_ENABLE_INDET_BTT = 1) generate
-- local signals
-- signal lsig_valid_eop_dbeat : std_logic := '0';
signal lsig_strm_eop_asserted : std_logic := '0';
signal lsig_absorb2tlast : std_logic := '0';
signal lsig_set_absorb2tlast : std_logic := '0';
signal lsig_clr_absorb2tlast : std_logic := '0';
begin
-- Detect an end of packet condition. This is an EOP sent to the DRE or
-- an overflow data absorption condition
sig_eop_sent <= (sig_scatter2drc_eop and
sig_valid_dre_output_dbeat) or
(lsig_set_absorb2tlast and
not(lsig_absorb2tlast));
sig_tlast_sent <= (sig_scatter2drc_tlast and --
sig_valid_dre_output_dbeat and -- Normal Tlast Sent condition
not(lsig_set_absorb2tlast)) or --
(lsig_absorb2tlast and
lsig_clr_absorb2tlast); -- Overflow absorbion condition
-- TStrb FIFO Input Stream Freeze control
sig_freeze_it <= not(sig_stbgen_tstrb(STRM_NUM_BYTE_LANES-1)) and -- ms strobe not set
-- not(sig_curr_eof_reg) and -- tstrb fifo being loaded
sig_valid_fifo_ld ; -- Current input cmd has eof set
-- Stream EOP assertion is caused when the stream input TLAST
-- is asserted and the most significant strobe bit asserted in
-- the input stream data beat is less than or equal to the most
-- significant calculated asserted strobe bit for the data beat.
lsig_strm_eop_asserted <= '1'
when (sig_mssa_index <= sig_tstrb_fifo_mssai_out) and
(sig_strm_tlast = '1' and
sig_strm_tvalid = '1')
else '0';
-- Must not freeze the Stream input skid buffer if an EOF
-- condition exists on the Stream input (skid buf output)
sig_gated_fifo_freeze_out <= sig_fifo_freeze_out and
not(lsig_strm_eop_asserted) and
sig_strm_tvalid; -- CR617164
-- Databeat DRE EOP output ---------------------------
sig_scatter2drc_eop <= (--sig_fifo_eof_out or
lsig_strm_eop_asserted) and
sig_scatter2drc_tvalid;
-- Databeat DRE Last output ---------------------------
sig_scatter2drc_tlast <= (sig_fifo_tlast_out or
lsig_strm_eop_asserted) and
sig_scatter2drc_tvalid;
-- Formulate the output TSTRB vector. It is an AND of the command
-- generated TSTRB and the actual TSTRB received from the Stream input.
sig_scatter2drc_tstrb <= sig_fifo_tstrb_out and
sig_strm_tstrb;
sig_tlast_error_over <= '0'; -- no tlast error in Indeterminate BTT
sig_tlast_error_under <= '0'; -- no tlast error in Indeterminate BTT
sig_tlast_error_exact <= '0'; -- no tlast error in Indeterminate BTT
sig_set_tlast_error <= '0'; -- no tlast error in Indeterminate BTT
sig_tlast_error_reg <= '0'; -- no tlast error in Indeterminate BTT
sig_tlast_error_out <= '0'; -- no tlast error in Indeterminate BTT
------------------------------------------------
-- Data absorption to TLAST logic
-- This is used for the Stream Input overflow case. In this case, the
-- input stream data is absorbed (thrown away) until the TLAST databeat
-- is received (also thrown away). However, data is only absorbed if
-- the EOP bit from the TSTRB FIFO is encountered before the TLST from
-- the Stream input.
-- In addition, the scatter2drc_eop assertion is suppressed from the output
-- to the DRE.
-- Assign the TREADY out to the Stream In with Overflow data absorption
-- case added.
sig_strm_tready <= '0'
when (lsig_absorb2tlast = '0' and
(sig_gated_fifo_freeze_out = '1' or -- Normal case
sig_cmd_side_ready = '0'))
Else '1'
When (lsig_absorb2tlast = '1') -- Absorb overflow case
Else sig_drc2scatter_tready;
-- Check for the condition for absorbing overflow data. The start of new input
-- packet cannot reside in the same databeat as the end of the previous
-- packet. Thus anytime an EOF is encountered from the TSTRB FIFO output, the
-- entire databeat needs to be discarded after transfer to the DRE of the
-- appropriate data.
lsig_set_absorb2tlast <= '1'
when (sig_fifo_eof_out = '1' and
sig_tstrb_fifo_empty = '0' and -- CR617164
(sig_strm_tlast = '0' and
sig_strm_tvalid = '1'))
Else '1'
When (sig_gated_fifo_freeze_out = '1' and
sig_fifo_eof_out = '1' and
sig_tstrb_fifo_empty = '0') -- CR617164
else '0';
lsig_clr_absorb2tlast <= '1'
when lsig_absorb2tlast = '1' and
(sig_strm_tlast = '1' and
sig_strm_tvalid = '1')
else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ABSORB_FLOP
--
-- Process Description:
-- Implements the flag for indicating a overflow absorption
-- case is active.
--
-------------------------------------------------------------
IMP_ABSORB_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
lsig_clr_absorb2tlast = '1') then
lsig_absorb2tlast <= '0';
elsif (lsig_set_absorb2tlast = '1') then
lsig_absorb2tlast <= '1';
else
null; -- Hold Current State
end if;
end if;
end process IMP_ABSORB_FLOP;
end generate GEN_INDET_BTT;
end implementation;
|
bsd-2-clause
|
tdaede/daala_zynq
|
daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_auto_pc_120_0/fifo_generator_v11_0/common/wr_pf_as.vhd
|
2
|
27402
|
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9f/LPcAOyHJ4J1sN8eAsCunGk2ouy/qSLgfjfNRByBGOIcuLSLbgMN3FODBZK/dQRvEiuL33fEj3
wsW7PwNfPBoN1fbLdxzrhKAFsZv87K2GxMfTiivo+3f2CFnV/4LKW40G4QPU3jrwQfFHYRFjKfbn
Fj2gqSDFHxMe5lfNbF0a5NX4ies8myaSEFkjnHvk8K7ImWmZPGuUR7AAIfRIC7a1Nd2VoOOf1diC
tB3tQ81AggAnfSk2zvqZLuOxl6PC6qkshER6qNDYuy8F3exJlVLh5UXyJ+i1Ucs0rxRcYN9emRn2
GVFT7FuXXysTqkARdkeauYjHnh8cXJfQetVbWVxQmpNc6Z/viTRLfczDCVoZgsc88v8M0Sgc12cm
KvTfDmbai+hNokrd12gEZZajLrrRO5UUu/Dkn5Dmkn/Gb6D86cFjLMdhYb9cEDfe563BAhR6jE8C
c+FGekADRglH4bF9hrF/itNgvA==
`protect end_protected
|
bsd-2-clause
|
tdaede/daala_zynq
|
daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_dma_0_0/axi_dma_v7_1/hdl/src/vhdl/axi_dma_mm2s_sts_mngr.vhd
|
1
|
11936
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_mm2s_sts_mngr.vhd
-- Description: This entity mangages 'halt' and 'idle' status for the MM2S
-- channel
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library proc_common_v4_0;
library axi_dma_v7_1;
use axi_dma_v7_1.axi_dma_pkg.all;
-------------------------------------------------------------------------------
entity axi_dma_mm2s_sts_mngr is
generic (
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Any one of the 4 clock inputs is not
-- synchronous to the other
);
port (
-- system signals
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- dma control and sg engine status signals --
mm2s_run_stop : in std_logic ; --
--
mm2s_ftch_idle : in std_logic ; --
mm2s_updt_idle : in std_logic ; --
mm2s_cmnd_idle : in std_logic ; --
mm2s_sts_idle : in std_logic ; --
--
-- stop and halt control/status --
mm2s_stop : in std_logic ; --
mm2s_halt_cmplt : in std_logic ; --
--
-- system state and control --
mm2s_all_idle : out std_logic ; --
mm2s_halted_clr : out std_logic ; --
mm2s_halted_set : out std_logic ; --
mm2s_idle_set : out std_logic ; --
mm2s_idle_clr : out std_logic --
);
end axi_dma_mm2s_sts_mngr;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_mm2s_sts_mngr is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
ATTRIBUTE async_reg : STRING;
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal all_is_idle : std_logic := '0';
signal all_is_idle_d1 : std_logic := '0';
signal all_is_idle_re : std_logic := '0';
signal all_is_idle_fe : std_logic := '0';
signal mm2s_datamover_idle : std_logic := '0';
signal mm2s_halt_cmpt_d1_cdc_tig : std_logic := '0';
signal mm2s_halt_cmpt_cdc_d2 : std_logic := '0';
--ATTRIBUTE async_reg OF mm2s_halt_cmpt_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF mm2s_halt_cmpt_cdc_d2 : SIGNAL IS "true";
signal mm2s_halt_cmpt_d2 : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Everything is idle when everything is idle
all_is_idle <= mm2s_ftch_idle
and mm2s_updt_idle
and mm2s_cmnd_idle
and mm2s_sts_idle;
-- Pass out for soft reset use
mm2s_all_idle <= all_is_idle;
-------------------------------------------------------------------------------
-- For data mover halting look at halt complete to determine when halt
-- is done and datamover has completly halted. If datamover not being
-- halted then can ignore flag thus simply flag as idle.
-------------------------------------------------------------------------------
GEN_FOR_ASYNC : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
-- Double register to secondary clock domain. This is sufficient
-- because halt_cmplt will remain asserted until detected in
-- reset module in secondary clock domain.
AWVLD_CDC_TO : entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => mm2s_halt_cmplt,
prmry_vect_in => (others => '0'),
scndry_aclk => m_axi_sg_aclk,
scndry_resetn => '0',
scndry_out => mm2s_halt_cmpt_cdc_d2,
scndry_vect_out => open
);
-- REG_TO_SECONDARY : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- -- if(m_axi_sg_aresetn = '0')then
-- -- mm2s_halt_cmpt_d1_cdc_tig <= '0';
-- -- mm2s_halt_cmpt_d2 <= '0';
-- -- else
-- mm2s_halt_cmpt_d1_cdc_tig <= mm2s_halt_cmplt;
-- mm2s_halt_cmpt_cdc_d2 <= mm2s_halt_cmpt_d1_cdc_tig;
-- -- end if;
-- end if;
-- end process REG_TO_SECONDARY;
mm2s_halt_cmpt_d2 <= mm2s_halt_cmpt_cdc_d2;
end generate GEN_FOR_ASYNC;
GEN_FOR_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
-- No clock crossing required therefore simple pass through
mm2s_halt_cmpt_d2 <= mm2s_halt_cmplt;
end generate GEN_FOR_SYNC;
mm2s_datamover_idle <= '1' when (mm2s_stop = '1' and mm2s_halt_cmpt_d2 = '1')
or (mm2s_stop = '0')
else '0';
-------------------------------------------------------------------------------
-- Set halt bit if run/stop cleared and all processes are idle
-------------------------------------------------------------------------------
HALT_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_halted_set <= '0';
-- DMACR.Run/Stop is cleared, all processes are idle, datamover halt cmplted
elsif(mm2s_run_stop = '0' and all_is_idle = '1' and mm2s_datamover_idle = '1')then
mm2s_halted_set <= '1';
else
mm2s_halted_set <= '0';
end if;
end if;
end process HALT_PROCESS;
-------------------------------------------------------------------------------
-- Clear halt bit if run/stop is set and SG engine begins to fetch descriptors
-------------------------------------------------------------------------------
NOT_HALTED_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_halted_clr <= '0';
elsif(mm2s_run_stop = '1')then
mm2s_halted_clr <= '1';
else
mm2s_halted_clr <= '0';
end if;
end if;
end process NOT_HALTED_PROCESS;
-------------------------------------------------------------------------------
-- Register ALL is Idle to create rising and falling edges on idle flag
-------------------------------------------------------------------------------
IDLE_REG_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
all_is_idle_d1 <= '0';
else
all_is_idle_d1 <= all_is_idle;
end if;
end if;
end process IDLE_REG_PROCESS;
all_is_idle_re <= all_is_idle and not all_is_idle_d1;
all_is_idle_fe <= not all_is_idle and all_is_idle_d1;
-- Set or Clear IDLE bit in DMASR
mm2s_idle_set <= all_is_idle_re and mm2s_run_stop;
mm2s_idle_clr <= all_is_idle_fe;
end implementation;
|
bsd-2-clause
|
cpulabs/mist1032sa
|
sim/inst_level/work/altmult_accum/_primary.vhd
|
1
|
17708
|
library verilog;
use verilog.vl_types.all;
entity altmult_accum is
generic(
width_a : integer := 2;
width_b : integer := 2;
width_c : integer := 22;
width_result : integer := 5;
number_of_multipliers: integer := 1;
input_reg_a : string := "CLOCK0";
input_aclr_a : string := "ACLR3";
multiplier1_direction: string := "UNUSED";
multiplier3_direction: string := "UNUSED";
input_reg_b : string := "CLOCK0";
input_aclr_b : string := "ACLR3";
port_addnsub : string := "PORT_CONNECTIVITY";
addnsub_reg : string := "CLOCK0";
addnsub_aclr : string := "ACLR3";
addnsub_pipeline_reg: string := "CLOCK0";
addnsub_pipeline_aclr: string := "ACLR3";
accum_direction : string := "ADD";
accum_sload_reg : string := "CLOCK0";
accum_sload_aclr: string := "ACLR3";
accum_sload_pipeline_reg: string := "CLOCK0";
accum_sload_pipeline_aclr: string := "ACLR3";
representation_a: string := "UNSIGNED";
port_signa : string := "PORT_CONNECTIVITY";
sign_reg_a : string := "CLOCK0";
sign_aclr_a : string := "ACLR3";
sign_pipeline_reg_a: string := "CLOCK0";
sign_pipeline_aclr_a: string := "ACLR3";
port_signb : string := "PORT_CONNECTIVITY";
representation_b: string := "UNSIGNED";
sign_reg_b : string := "CLOCK0";
sign_aclr_b : string := "ACLR3";
sign_pipeline_reg_b: string := "CLOCK0";
sign_pipeline_aclr_b: string := "ACLR3";
multiplier_reg : string := "CLOCK0";
multiplier_aclr : string := "ACLR3";
output_reg : string := "CLOCK0";
output_aclr : string := "ACLR3";
lpm_type : string := "altmult_accum";
lpm_hint : string := "UNUSED";
extra_multiplier_latency: integer := 0;
extra_accumulator_latency: integer := 0;
dedicated_multiplier_circuitry: string := "AUTO";
dsp_block_balancing: string := "AUTO";
intended_device_family: string := "Stratix";
accum_round_aclr: string := "ACLR3";
accum_round_pipeline_aclr: string := "ACLR3";
accum_round_pipeline_reg: string := "CLOCK0";
accum_round_reg : string := "CLOCK0";
accum_saturation_aclr: string := "ACLR3";
accum_saturation_pipeline_aclr: string := "ACLR3";
accum_saturation_pipeline_reg: string := "CLOCK0";
accum_saturation_reg: string := "CLOCK0";
accum_sload_upper_data_aclr: string := "ACLR3";
accum_sload_upper_data_pipeline_aclr: string := "ACLR3";
accum_sload_upper_data_pipeline_reg: string := "CLOCK0";
accum_sload_upper_data_reg: string := "CLOCK0";
mult_round_aclr : string := "ACLR3";
mult_round_reg : string := "CLOCK0";
mult_saturation_aclr: string := "ACLR3";
mult_saturation_reg: string := "CLOCK0";
input_source_a : string := "DATAA";
input_source_b : string := "DATAB";
width_upper_data: integer := 1;
multiplier_rounding: string := "NO";
multiplier_saturation: string := "NO";
accumulator_rounding: string := "NO";
accumulator_saturation: string := "NO";
port_mult_is_saturated: string := "UNUSED";
port_accum_is_saturated: string := "UNUSED";
int_width_a : vl_notype;
int_width_b : vl_notype;
int_width_result: vl_notype;
int_extra_width : vl_notype;
diff_width_a : vl_notype;
diff_width_b : vl_notype;
sat_for_ini : vl_notype;
mult_round_for_ini: vl_notype;
bits_to_round : vl_notype;
sload_for_limit : vl_notype;
accum_sat_for_limit: vl_notype;
int_width_extra_bit: vl_notype;
preadder_mode : string := "SIMPLE";
loadconst_value : integer := 0;
width_coef : integer := 0;
loadconst_control_register: string := "CLOCK0";
loadconst_control_aclr: string := "ACLR0";
coefsel0_register: string := "CLOCK0";
coefsel1_register: string := "CLOCK0";
coefsel2_register: string := "CLOCK0";
coefsel3_register: string := "CLOCK0";
coefsel0_aclr : string := "ACLR0";
coefsel1_aclr : string := "ACLR0";
coefsel2_aclr : string := "ACLR0";
coefsel3_aclr : string := "ACLR0";
preadder_direction_0: string := "ADD";
preadder_direction_1: string := "ADD";
preadder_direction_2: string := "ADD";
preadder_direction_3: string := "ADD";
systolic_delay1 : string := "UNREGISTERED";
systolic_delay3 : string := "UNREGISTERED";
systolic_aclr1 : string := "NONE";
systolic_aclr3 : string := "NONE";
coef0_0 : integer := 0;
coef0_1 : integer := 0;
coef0_2 : integer := 0;
coef0_3 : integer := 0;
coef0_4 : integer := 0;
coef0_5 : integer := 0;
coef0_6 : integer := 0;
coef0_7 : integer := 0;
coef1_0 : integer := 0;
coef1_1 : integer := 0;
coef1_2 : integer := 0;
coef1_3 : integer := 0;
coef1_4 : integer := 0;
coef1_5 : integer := 0;
coef1_6 : integer := 0;
coef1_7 : integer := 0;
coef2_0 : integer := 0;
coef2_1 : integer := 0;
coef2_2 : integer := 0;
coef2_3 : integer := 0;
coef2_4 : integer := 0;
coef2_5 : integer := 0;
coef2_6 : integer := 0;
coef2_7 : integer := 0;
coef3_0 : integer := 0;
coef3_1 : integer := 0;
coef3_2 : integer := 0;
coef3_3 : integer := 0;
coef3_4 : integer := 0;
coef3_5 : integer := 0;
coef3_6 : integer := 0;
coef3_7 : integer := 0
);
port(
dataa : in vl_logic_vector;
datab : in vl_logic_vector;
datac : in vl_logic_vector;
scanina : in vl_logic_vector;
scaninb : in vl_logic_vector;
sourcea : in vl_logic;
sourceb : in vl_logic;
accum_sload_upper_data: in vl_logic_vector;
addnsub : in vl_logic;
accum_sload : in vl_logic;
signa : in vl_logic;
signb : in vl_logic;
clock0 : in vl_logic;
clock1 : in vl_logic;
clock2 : in vl_logic;
clock3 : in vl_logic;
ena0 : in vl_logic;
ena1 : in vl_logic;
ena2 : in vl_logic;
ena3 : in vl_logic;
aclr0 : in vl_logic;
aclr1 : in vl_logic;
aclr2 : in vl_logic;
aclr3 : in vl_logic;
result : out vl_logic_vector;
overflow : out vl_logic;
scanouta : out vl_logic_vector;
scanoutb : out vl_logic_vector;
mult_round : in vl_logic;
mult_saturation : in vl_logic;
accum_round : in vl_logic;
accum_saturation: in vl_logic;
mult_is_saturated: out vl_logic;
accum_is_saturated: out vl_logic;
coefsel0 : in vl_logic_vector(2 downto 0);
coefsel1 : in vl_logic_vector(2 downto 0);
coefsel2 : in vl_logic_vector(2 downto 0);
coefsel3 : in vl_logic_vector(2 downto 0)
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of width_a : constant is 1;
attribute mti_svvh_generic_type of width_b : constant is 1;
attribute mti_svvh_generic_type of width_c : constant is 1;
attribute mti_svvh_generic_type of width_result : constant is 1;
attribute mti_svvh_generic_type of number_of_multipliers : constant is 1;
attribute mti_svvh_generic_type of input_reg_a : constant is 1;
attribute mti_svvh_generic_type of input_aclr_a : constant is 1;
attribute mti_svvh_generic_type of multiplier1_direction : constant is 1;
attribute mti_svvh_generic_type of multiplier3_direction : constant is 1;
attribute mti_svvh_generic_type of input_reg_b : constant is 1;
attribute mti_svvh_generic_type of input_aclr_b : constant is 1;
attribute mti_svvh_generic_type of port_addnsub : constant is 1;
attribute mti_svvh_generic_type of addnsub_reg : constant is 1;
attribute mti_svvh_generic_type of addnsub_aclr : constant is 1;
attribute mti_svvh_generic_type of addnsub_pipeline_reg : constant is 1;
attribute mti_svvh_generic_type of addnsub_pipeline_aclr : constant is 1;
attribute mti_svvh_generic_type of accum_direction : constant is 1;
attribute mti_svvh_generic_type of accum_sload_reg : constant is 1;
attribute mti_svvh_generic_type of accum_sload_aclr : constant is 1;
attribute mti_svvh_generic_type of accum_sload_pipeline_reg : constant is 1;
attribute mti_svvh_generic_type of accum_sload_pipeline_aclr : constant is 1;
attribute mti_svvh_generic_type of representation_a : constant is 1;
attribute mti_svvh_generic_type of port_signa : constant is 1;
attribute mti_svvh_generic_type of sign_reg_a : constant is 1;
attribute mti_svvh_generic_type of sign_aclr_a : constant is 1;
attribute mti_svvh_generic_type of sign_pipeline_reg_a : constant is 1;
attribute mti_svvh_generic_type of sign_pipeline_aclr_a : constant is 1;
attribute mti_svvh_generic_type of port_signb : constant is 1;
attribute mti_svvh_generic_type of representation_b : constant is 1;
attribute mti_svvh_generic_type of sign_reg_b : constant is 1;
attribute mti_svvh_generic_type of sign_aclr_b : constant is 1;
attribute mti_svvh_generic_type of sign_pipeline_reg_b : constant is 1;
attribute mti_svvh_generic_type of sign_pipeline_aclr_b : constant is 1;
attribute mti_svvh_generic_type of multiplier_reg : constant is 1;
attribute mti_svvh_generic_type of multiplier_aclr : constant is 1;
attribute mti_svvh_generic_type of output_reg : constant is 1;
attribute mti_svvh_generic_type of output_aclr : constant is 1;
attribute mti_svvh_generic_type of lpm_type : constant is 1;
attribute mti_svvh_generic_type of lpm_hint : constant is 1;
attribute mti_svvh_generic_type of extra_multiplier_latency : constant is 1;
attribute mti_svvh_generic_type of extra_accumulator_latency : constant is 1;
attribute mti_svvh_generic_type of dedicated_multiplier_circuitry : constant is 1;
attribute mti_svvh_generic_type of dsp_block_balancing : constant is 1;
attribute mti_svvh_generic_type of intended_device_family : constant is 1;
attribute mti_svvh_generic_type of accum_round_aclr : constant is 1;
attribute mti_svvh_generic_type of accum_round_pipeline_aclr : constant is 1;
attribute mti_svvh_generic_type of accum_round_pipeline_reg : constant is 1;
attribute mti_svvh_generic_type of accum_round_reg : constant is 1;
attribute mti_svvh_generic_type of accum_saturation_aclr : constant is 1;
attribute mti_svvh_generic_type of accum_saturation_pipeline_aclr : constant is 1;
attribute mti_svvh_generic_type of accum_saturation_pipeline_reg : constant is 1;
attribute mti_svvh_generic_type of accum_saturation_reg : constant is 1;
attribute mti_svvh_generic_type of accum_sload_upper_data_aclr : constant is 1;
attribute mti_svvh_generic_type of accum_sload_upper_data_pipeline_aclr : constant is 1;
attribute mti_svvh_generic_type of accum_sload_upper_data_pipeline_reg : constant is 1;
attribute mti_svvh_generic_type of accum_sload_upper_data_reg : constant is 1;
attribute mti_svvh_generic_type of mult_round_aclr : constant is 1;
attribute mti_svvh_generic_type of mult_round_reg : constant is 1;
attribute mti_svvh_generic_type of mult_saturation_aclr : constant is 1;
attribute mti_svvh_generic_type of mult_saturation_reg : constant is 1;
attribute mti_svvh_generic_type of input_source_a : constant is 1;
attribute mti_svvh_generic_type of input_source_b : constant is 1;
attribute mti_svvh_generic_type of width_upper_data : constant is 1;
attribute mti_svvh_generic_type of multiplier_rounding : constant is 1;
attribute mti_svvh_generic_type of multiplier_saturation : constant is 1;
attribute mti_svvh_generic_type of accumulator_rounding : constant is 1;
attribute mti_svvh_generic_type of accumulator_saturation : constant is 1;
attribute mti_svvh_generic_type of port_mult_is_saturated : constant is 1;
attribute mti_svvh_generic_type of port_accum_is_saturated : constant is 1;
attribute mti_svvh_generic_type of int_width_a : constant is 3;
attribute mti_svvh_generic_type of int_width_b : constant is 3;
attribute mti_svvh_generic_type of int_width_result : constant is 3;
attribute mti_svvh_generic_type of int_extra_width : constant is 3;
attribute mti_svvh_generic_type of diff_width_a : constant is 3;
attribute mti_svvh_generic_type of diff_width_b : constant is 3;
attribute mti_svvh_generic_type of sat_for_ini : constant is 3;
attribute mti_svvh_generic_type of mult_round_for_ini : constant is 3;
attribute mti_svvh_generic_type of bits_to_round : constant is 3;
attribute mti_svvh_generic_type of sload_for_limit : constant is 3;
attribute mti_svvh_generic_type of accum_sat_for_limit : constant is 3;
attribute mti_svvh_generic_type of int_width_extra_bit : constant is 3;
attribute mti_svvh_generic_type of preadder_mode : constant is 1;
attribute mti_svvh_generic_type of loadconst_value : constant is 1;
attribute mti_svvh_generic_type of width_coef : constant is 1;
attribute mti_svvh_generic_type of loadconst_control_register : constant is 1;
attribute mti_svvh_generic_type of loadconst_control_aclr : constant is 1;
attribute mti_svvh_generic_type of coefsel0_register : constant is 1;
attribute mti_svvh_generic_type of coefsel1_register : constant is 1;
attribute mti_svvh_generic_type of coefsel2_register : constant is 1;
attribute mti_svvh_generic_type of coefsel3_register : constant is 1;
attribute mti_svvh_generic_type of coefsel0_aclr : constant is 1;
attribute mti_svvh_generic_type of coefsel1_aclr : constant is 1;
attribute mti_svvh_generic_type of coefsel2_aclr : constant is 1;
attribute mti_svvh_generic_type of coefsel3_aclr : constant is 1;
attribute mti_svvh_generic_type of preadder_direction_0 : constant is 1;
attribute mti_svvh_generic_type of preadder_direction_1 : constant is 1;
attribute mti_svvh_generic_type of preadder_direction_2 : constant is 1;
attribute mti_svvh_generic_type of preadder_direction_3 : constant is 1;
attribute mti_svvh_generic_type of systolic_delay1 : constant is 1;
attribute mti_svvh_generic_type of systolic_delay3 : constant is 1;
attribute mti_svvh_generic_type of systolic_aclr1 : constant is 1;
attribute mti_svvh_generic_type of systolic_aclr3 : constant is 1;
attribute mti_svvh_generic_type of coef0_0 : constant is 1;
attribute mti_svvh_generic_type of coef0_1 : constant is 1;
attribute mti_svvh_generic_type of coef0_2 : constant is 1;
attribute mti_svvh_generic_type of coef0_3 : constant is 1;
attribute mti_svvh_generic_type of coef0_4 : constant is 1;
attribute mti_svvh_generic_type of coef0_5 : constant is 1;
attribute mti_svvh_generic_type of coef0_6 : constant is 1;
attribute mti_svvh_generic_type of coef0_7 : constant is 1;
attribute mti_svvh_generic_type of coef1_0 : constant is 1;
attribute mti_svvh_generic_type of coef1_1 : constant is 1;
attribute mti_svvh_generic_type of coef1_2 : constant is 1;
attribute mti_svvh_generic_type of coef1_3 : constant is 1;
attribute mti_svvh_generic_type of coef1_4 : constant is 1;
attribute mti_svvh_generic_type of coef1_5 : constant is 1;
attribute mti_svvh_generic_type of coef1_6 : constant is 1;
attribute mti_svvh_generic_type of coef1_7 : constant is 1;
attribute mti_svvh_generic_type of coef2_0 : constant is 1;
attribute mti_svvh_generic_type of coef2_1 : constant is 1;
attribute mti_svvh_generic_type of coef2_2 : constant is 1;
attribute mti_svvh_generic_type of coef2_3 : constant is 1;
attribute mti_svvh_generic_type of coef2_4 : constant is 1;
attribute mti_svvh_generic_type of coef2_5 : constant is 1;
attribute mti_svvh_generic_type of coef2_6 : constant is 1;
attribute mti_svvh_generic_type of coef2_7 : constant is 1;
attribute mti_svvh_generic_type of coef3_0 : constant is 1;
attribute mti_svvh_generic_type of coef3_1 : constant is 1;
attribute mti_svvh_generic_type of coef3_2 : constant is 1;
attribute mti_svvh_generic_type of coef3_3 : constant is 1;
attribute mti_svvh_generic_type of coef3_4 : constant is 1;
attribute mti_svvh_generic_type of coef3_5 : constant is 1;
attribute mti_svvh_generic_type of coef3_6 : constant is 1;
attribute mti_svvh_generic_type of coef3_7 : constant is 1;
end altmult_accum;
|
bsd-2-clause
|
cpulabs/mist1032sa
|
sim/inst_level/work/stratix_lvds_rx/_primary.vhd
|
1
|
751
|
library verilog;
use verilog.vl_types.all;
entity stratix_lvds_rx is
generic(
number_of_channels: integer := 1;
deserialization_factor: integer := 4;
REGISTER_WIDTH : vl_notype
);
port(
rx_in : in vl_logic_vector;
rx_fastclk : in vl_logic;
rx_enable0 : in vl_logic;
rx_enable1 : in vl_logic;
rx_out : out vl_logic_vector
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of number_of_channels : constant is 1;
attribute mti_svvh_generic_type of deserialization_factor : constant is 1;
attribute mti_svvh_generic_type of REGISTER_WIDTH : constant is 3;
end stratix_lvds_rx;
|
bsd-2-clause
|
cpulabs/mist1032sa
|
sim/inst_level/work/mist1032sa_arbiter_matching_queue/_primary.vhd
|
1
|
948
|
library verilog;
use verilog.vl_types.all;
entity mist1032sa_arbiter_matching_queue is
generic(
D : integer := 8;
DN : integer := 3;
FN : integer := 1
);
port(
iCLOCK : in vl_logic;
inRESET : in vl_logic;
iFLASH : in vl_logic;
iWR_REQ : in vl_logic;
iWR_FLAG : in vl_logic_vector;
oWR_FULL : out vl_logic;
iRD_REQ : in vl_logic;
oRD_VALID : out vl_logic;
oRD_FLAG : out vl_logic_vector;
oRD_EMPTY : out vl_logic
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of D : constant is 1;
attribute mti_svvh_generic_type of DN : constant is 1;
attribute mti_svvh_generic_type of FN : constant is 1;
end mist1032sa_arbiter_matching_queue;
|
bsd-2-clause
|
cpulabs/mist1032sa
|
sim/inst_level/work/l1_data_cache_64entry_4way_line64b_bus_8b_damy/_primary.vhd
|
1
|
1314
|
library verilog;
use verilog.vl_types.all;
entity l1_data_cache_64entry_4way_line64b_bus_8b_damy is
port(
iCLOCK : in vl_logic;
inRESET : in vl_logic;
iREMOVE : in vl_logic;
iRD_REQ : in vl_logic;
oRD_BUSY : out vl_logic;
iRD_ADDR : in vl_logic_vector(31 downto 0);
oRD_VALID : out vl_logic;
oRD_HIT : out vl_logic;
iRD_BUSY : in vl_logic;
oRD_DATA : out vl_logic_vector(31 downto 0);
oRD_MMU_FLAGS : out vl_logic_vector(13 downto 0);
iUP_REQ : in vl_logic;
oUP_BUSY : out vl_logic;
iUP_ORDER : in vl_logic_vector(1 downto 0);
iUP_MASK : in vl_logic_vector(3 downto 0);
iUP_ADDR : in vl_logic_vector(31 downto 0);
iUP_DATA : in vl_logic_vector(31 downto 0);
iWR_REQ : in vl_logic;
oWR_BUSY : out vl_logic;
iWR_ADDR : in vl_logic_vector(31 downto 0);
iWR_DATA : in vl_logic_vector(511 downto 0);
iWR_MMU_FLAGS : in vl_logic_vector(255 downto 0)
);
end l1_data_cache_64entry_4way_line64b_bus_8b_damy;
|
bsd-2-clause
|
jrrk2/greth_library
|
greth_library/techmap/bufg/obuf_tech.vhd
|
2
|
1073
|
----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov
--! @brief Virtual simple output buffer.
----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity obuf_tech is
generic
(
generic_tech : integer := 0
);
port (
o : out std_logic;
i : in std_logic
);
end;
architecture rtl of obuf_tech is
component obuf_inferred is
port (
o : out std_logic;
i : in std_logic
);
end component;
component obuf_micron180 is
port (
o : out std_logic;
i : in std_logic
);
end component;
begin
m180 : if generic_tech = micron180 generate
bufm : obuf_micron180 port map
(
o => o,
i => i
);
end generate;
inf0 : if generic_tech /= micron180 generate
bufinf : obuf_inferred port map
(
o => o,
i => i
);
end generate;
end;
|
bsd-2-clause
|
jrrk2/greth_library
|
greth_library/work/simple_soc.vhd
|
2
|
10798
|
-----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov
--! @brief Network on Chip design top level.
--! @details RISC-V "Rocket Core" based system with the AMBA AXI4 (NASTI)
--! system bus and integrated peripheries.
------------------------------------------------------------------------------
--! Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--! Data transformation and math functions library
library commonlib;
use commonlib.types_common.all;
--! Technology definition library.
library techmap;
--! Technology constants definition.
use techmap.gencomp.all;
--! "Virtual" PLL declaration.
use techmap.types_pll.all;
--! "Virtual" buffers declaration.
use techmap.types_buf.all;
--! AMBA system bus specific library
library ambalib;
--! AXI4 configuration constants.
use ambalib.types_amba4.all;
--! Rocket-chip specific library
library rocketlib;
--! SOC top-level component declaration.
use rocketlib.types_rocket.all;
--! Ethernet related declarations.
use rocketlib.grethpkg.all;
--! GNSS Sensor Ltd proprietary library
library gnsslib;
use gnsslib.types_gnss.all;
--! Top-level implementaion library
library work;
--! Target dependable configuration: RTL, FPGA or ASIC.
use work.config_target.all;
--! Target independable configuration.
use work.config_common.all;
--! @brief SOC Top-level entity declaration.
--! @details This module implements full SOC functionality and all IO signals
--! are available on FPGA/ASIC IO pins.
entity rocket_soc is port
(
--! Input reset. Active High. Usually assigned to button "Center".
i_rst : in std_logic;
--! @name Clocks:
--! @{
--! Differential clock (LVDS) positive signal.
i_sclk_p : in std_logic;
--! Differential clock (LVDS) negative signal.
i_sclk_n : in std_logic;
--! External ADC clock (default 26 MHz).
i_clk_adc : in std_logic;
--! @}
--! @name User's IOs:
--! @{
--! DIP switch.
i_int_clkrf : in std_logic;
i_dip : in std_logic_vector(3 downto 1);
--! LEDs.
o_led : out std_logic_vector(7 downto 0);
--! @}
--! @name UART1 signals:
--! @{
i_uart1_ctsn : in std_logic;
i_uart1_rd : in std_logic;
o_uart1_td : out std_logic;
o_uart1_rtsn : out std_logic;
--! @}
--! @name ADC channel A inputs (1575.4 GHz):
--! @{
i_gps_I : in std_logic_vector(1 downto 0);
i_gps_Q : in std_logic_vector(1 downto 0);
--! @}
--! @name ADC channel B inputs (1602 GHz):
--! @{
i_glo_I : in std_logic_vector(1 downto 0);
i_glo_Q : in std_logic_vector(1 downto 0);
--! @}
--! @name MAX2769 SPIs and antenna controls signals:
--! @{
i_gps_ld : in std_logic;
i_glo_ld : in std_logic;
o_max_sclk : out std_logic;
o_max_sdata : out std_logic;
o_max_ncs : out std_logic_vector(1 downto 0);
i_antext_stat : in std_logic;
i_antext_detect : in std_logic;
o_antext_ena : out std_logic;
o_antint_contr : out std_logic;
--! @}
--! Ethernet MAC PHY interface signals
--! @{
i_gmiiclk_p : in std_ulogic;
i_gmiiclk_n : in std_ulogic;
o_egtx_clk : out std_ulogic;
i_etx_clk : in std_ulogic;
i_erx_clk : in std_ulogic;
i_erxd : in std_logic_vector(3 downto 0);
i_erx_dv : in std_ulogic;
i_erx_er : in std_ulogic;
i_erx_col : in std_ulogic;
i_erx_crs : in std_ulogic;
i_emdint : in std_ulogic;
o_etxd : out std_logic_vector(3 downto 0);
o_etx_en : out std_ulogic;
o_etx_er : out std_ulogic;
o_emdc : out std_ulogic;
io_emdio : inout std_logic;
o_erstn : out std_ulogic
);
--! @}
end rocket_soc;
--! @brief SOC top-level architecture declaration.
architecture arch_rocket_soc of rocket_soc is
--! @name Buffered in/out signals.
--! @details All signals that are connected with in/out pads must be passed
--! through the dedicated buffere modules. For FPGA they are implemented
--! as an empty devices but ASIC couldn't be made without buffering.
--! @{
signal ib_rst : std_logic;
signal ib_sclk_p : std_logic;
signal ib_sclk_n : std_logic;
signal ib_clk_adc : std_logic;
signal ib_dip : std_logic_vector(3 downto 0);
signal ib_gmiiclk : std_logic;
--! @}
signal wSysReset : std_ulogic; -- Internal system reset. MUST NOT USED BY DEVICES.
signal wReset : std_ulogic; -- Global reset active HIGH
signal wNReset : std_ulogic; -- Global reset active LOW
signal soft_rst : std_logic; -- reset from exteranl debugger
signal bus_nrst : std_ulogic; -- Global reset and Soft Reset active LOW
signal wClkBus : std_ulogic; -- bus clock from the internal PLL (100MHz virtex6/40MHz Spartan6)
signal wClkAdc : std_ulogic; -- 26 MHz from the internal PLL
signal wPllLocked : std_ulogic; -- PLL status signal. 0=Unlocked; 1=locked.
signal uart1i : uart_in_type;
signal uart1o : uart_out_type;
--! Arbiter is switching only slaves output signal, data from noc
--! is connected to all slaves and to the arbiter itself.
signal aximi : nasti_master_in_type;
signal aximo : nasti_master_out_type;
signal axisi : nasti_slave_in_type;
signal axiso : nasti_slave_out_type;
signal slv_cfg : nasti_slave_cfg_vector;
signal mst_cfg : nasti_master_cfg_vector;
signal eth_i : eth_in_type;
signal eth_o : eth_out_type;
signal irq_pins : std_logic_vector(CFG_IRQ_TOTAL-1 downto 0);
begin
--! PAD buffers:
irst0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_rst, i_rst);
iclkp0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_sclk_p, i_sclk_p);
iclkn0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_sclk_n, i_sclk_n);
iclk1 : ibuf_tech generic map(CFG_PADTECH) port map (ib_clk_adc, i_clk_adc);
idip0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_dip(0), i_int_clkrf);
dipx : for i in 1 to 3 generate
idipz : ibuf_tech generic map(CFG_PADTECH) port map (ib_dip(i), i_dip(i));
end generate;
igbebuf0 : igdsbuf_tech generic map (CFG_PADTECH) port map (
i_gmiiclk_p, i_gmiiclk_n, ib_gmiiclk);
--! @todo all other in/out signals via buffers:
------------------------------------
-- @brief Internal PLL device instance.
pll0 : SysPLL_tech generic map (
tech => CFG_FABTECH,
tmode_always_ena => CFG_TESTMODE_ON
) port map (
i_reset => ib_rst,
i_int_clkrf => ib_dip(0),
i_clkp => ib_sclk_p,
i_clkn => ib_sclk_n,
i_clk_adc => ib_clk_adc,
o_clk_bus => wClkBus,
o_clk_adc => wClkAdc,
o_locked => wPllLocked
);
wSysReset <= ib_rst or not wPllLocked;
------------------------------------
--! @brief System Reset device instance.
rst0 : reset_global port map (
inSysReset => wSysReset,
inSysClk => wClkBus,
inPllLock => wPllLocked,
outReset => wReset
);
wNReset <= not wReset;
bus_nrst <= not (wReset or soft_rst);
aximi.grant <= "1";
aximi.aw_ready <= axiso.aw_ready;
aximi.w_ready <= axiso.w_ready;
aximi.b_valid <= axiso.b_valid;
aximi.b_resp <= axiso.b_resp;
aximi.b_id <= axiso.b_id;
aximi.b_user <= axiso.b_user;
aximi.ar_ready <= axiso.ar_ready;
aximi.r_valid <= axiso.r_valid;
aximi.r_resp <= axiso.r_resp;
aximi.r_data <= axiso.r_data;
aximi.r_last <= axiso.r_last;
aximi.r_id <= axiso.r_id;
aximi.r_user <= axiso.r_user;
axisi.aw_valid <= aximo.aw_valid;
axisi.aw_bits <= aximo.aw_bits;
axisi.aw_id <= aximo.aw_id;
axisi.aw_user <= aximo.aw_user;
axisi.w_valid <= aximo.w_valid;
axisi.w_data <= aximo.w_data;
axisi.w_last <= aximo.w_last;
axisi.w_strb <= aximo.w_strb;
axisi.w_user <= aximo.w_user;
axisi.b_ready <= aximo.b_ready;
axisi.ar_valid <= aximo.ar_valid;
axisi.ar_bits <= aximo.ar_bits;
axisi.ar_id <= aximo.ar_id;
axisi.ar_user <= aximo.ar_user;
axisi.r_ready <= aximo.r_ready;
------------------------------------
--! @brief Controller of the LEDs, DIPs and GPIO with the AXI4 interface.
--! @details Map address:
--! 0x80000000..0x80000fff (4 KB total)
gpio0 : nasti_gpio generic map (
xindex => CFG_NASTI_SLAVE_GPIO,
xaddr => 16#80000#,
xmask => 16#fffff#
) port map (
clk => wClkBus,
nrst => wNReset,
cfg => slv_cfg(CFG_NASTI_SLAVE_GPIO),
i => axisi,
o => axiso,
i_dip => ib_dip,
o_led => o_led
);
--! Gigabit clock phase rotator with buffers
clkrot90 : clkp90_tech generic map (
tech => CFG_FABTECH,
freq => 125000 -- KHz = 125 MHz
) port map (
i_rst => wReset,
i_clk => ib_gmiiclk,
o_clk => eth_i.gtx_clk,
o_clkp90 => eth_i.tx_clk_90,
o_clk2x => open, -- used in gbe 'io_ref'
o_lock => open
);
--! @brief Ethernet MAC with the AXI4 interface.
--! @details Map address:
--! 0x80040000..0x8007ffff (256 KB total)
--! EDCL IP: 192.168.0.51 = C0.A8.00.33
eth_i.tx_clk <= i_etx_clk;
eth_i.rx_clk <= i_erx_clk;
eth_i.rxd <= i_erxd;
eth_i.rx_dv <= i_erx_dv;
eth_i.rx_er <= i_erx_er;
eth_i.rx_col <= i_erx_col;
eth_i.rx_crs <= i_erx_crs;
eth_i.mdint <= i_emdint;
mac0 : grethaxi generic map (
xslvindex => CFG_NASTI_SLAVE_ETHMAC,
xmstindex => CFG_NASTI_MASTER_ETHMAC,
xaddr => 16#80040#,
xmask => 16#FFFC0#,
xirq => CFG_IRQ_ETHMAC,
memtech => CFG_MEMTECH,
mdcscaler => 60, --! System Bus clock in MHz
enable_mdio => 1,
fifosize => 16,
nsync => 1,
edcl => 1,
edclbufsz => 16,
macaddrh => 16#20789#,
macaddrl => 16#123#,
ipaddrh => 16#C0A8#,
ipaddrl => 16#0033#,
phyrstadr => 7,
enable_mdint => 1,
maxsize => 1518
) port map (
rst => wNReset,
clk => wClkBus,
msti => aximi,
msto => aximo,
mstcfg => mst_cfg(CFG_NASTI_MASTER_ETHMAC),
msto2 => open, -- EDCL separate access is disabled
mstcfg2 => open, -- EDCL separate access is disabled
slvi => axisi,
slvo => open,
slvcfg => slv_cfg(CFG_NASTI_SLAVE_ETHMAC),
ethi => eth_i,
etho => eth_o,
irq => irq_pins(CFG_IRQ_ETHMAC)
);
emdio_pad : iobuf_tech generic map(
CFG_PADTECH
) port map (
o => eth_i.mdio_i,
io => io_emdio,
i => eth_o.mdio_o,
t => eth_o.mdio_oe
);
o_egtx_clk <= eth_i.gtx_clk;--eth_i.tx_clk_90;
o_etxd <= eth_o.txd;
o_etx_en <= eth_o.tx_en;
o_etx_er <= eth_o.tx_er;
o_emdc <= eth_o.mdc;
o_erstn <= wNReset;
end arch_rocket_soc;
|
bsd-2-clause
|
jrrk2/greth_library
|
greth_library/work/simple_soc3.vhd
|
2
|
19629
|
-----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov
--! @brief Network on Chip design top level.
--! @details RISC-V "Rocket Core" based system with the AMBA AXI4 (NASTI)
--! system bus and integrated peripheries.
------------------------------------------------------------------------------
--! Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--! Data transformation and math functions library
library commonlib;
use commonlib.types_common.all;
--! Technology definition library.
library techmap;
--! Technology constants definition.
use techmap.gencomp.all;
--! "Virtual" PLL declaration.
use techmap.types_pll.all;
--! "Virtual" buffers declaration.
use techmap.types_buf.all;
--! AMBA system bus specific library
library ambalib;
--! AXI4 configuration constants.
use ambalib.types_amba4.all;
--! Rocket-chip specific library
library rocketlib;
--! SOC top-level component declaration.
use rocketlib.types_rocket.all;
--! Ethernet related declarations.
use rocketlib.grethpkg.all;
--! GNSS Sensor Ltd proprietary library
library gnsslib;
use gnsslib.types_gnss.all;
--! Top-level implementaion library
library work;
--! Target dependable configuration: RTL, FPGA or ASIC.
use work.config_target.all;
--! Target independable configuration.
use work.config_common.all;
--! @brief SOC Top-level entity declaration.
--! @details This module implements full SOC functionality and all IO signals
--! are available on FPGA/ASIC IO pins.
entity rocket_soc is port
(
--! Input reset. Active High. Usually assigned to button "Center".
i_rst : in std_logic;
--! @name Clocks:
--! @{
--! Differential clock (LVDS) positive signal.
i_sclk_p : in std_logic;
--! Differential clock (LVDS) negative signal.
i_sclk_n : in std_logic;
--! External ADC clock (default 26 MHz).
i_clk_adc : in std_logic;
--! @}
--! @name User's IOs:
--! @{
--! DIP switch.
i_int_clkrf : in std_logic;
i_dip : in std_logic_vector(3 downto 1);
--! LEDs.
o_led : out std_logic_vector(7 downto 0);
--! @}
--! @name UART1 signals:
--! @{
i_uart1_ctsn : in std_logic;
i_uart1_rd : in std_logic;
o_uart1_td : out std_logic;
o_uart1_rtsn : out std_logic;
--! @}
--! @name ADC channel A inputs (1575.4 GHz):
--! @{
i_gps_I : in std_logic_vector(1 downto 0);
i_gps_Q : in std_logic_vector(1 downto 0);
--! @}
--! @name ADC channel B inputs (1602 GHz):
--! @{
i_glo_I : in std_logic_vector(1 downto 0);
i_glo_Q : in std_logic_vector(1 downto 0);
--! @}
--! @name MAX2769 SPIs and antenna controls signals:
--! @{
i_gps_ld : in std_logic;
i_glo_ld : in std_logic;
o_max_sclk : out std_logic;
o_max_sdata : out std_logic;
o_max_ncs : out std_logic_vector(1 downto 0);
i_antext_stat : in std_logic;
i_antext_detect : in std_logic;
o_antext_ena : out std_logic;
o_antint_contr : out std_logic;
--! @}
--! Ethernet MAC PHY interface signals
--! @{
i_gmiiclk_p : in std_ulogic;
i_gmiiclk_n : in std_ulogic;
o_egtx_clk : out std_ulogic;
i_etx_clk : in std_ulogic;
i_erx_clk : in std_ulogic;
i_erxd : in std_logic_vector(3 downto 0);
i_erx_dv : in std_ulogic;
i_erx_er : in std_ulogic;
i_erx_col : in std_ulogic;
i_erx_crs : in std_ulogic;
i_emdint : in std_ulogic;
o_etxd : out std_logic_vector(3 downto 0);
o_etx_en : out std_ulogic;
o_etx_er : out std_ulogic;
o_emdc : out std_ulogic;
io_emdio : inout std_logic;
o_erstn : out std_ulogic
);
--! @}
end rocket_soc;
--! @brief SOC top-level architecture declaration.
architecture arch_rocket_soc of rocket_soc is
--! @name Buffered in/out signals.
--! @details All signals that are connected with in/out pads must be passed
--! through the dedicated buffere modules. For FPGA they are implemented
--! as an empty devices but ASIC couldn't be made without buffering.
--! @{
signal ib_rst : std_logic;
signal ib_sclk_p : std_logic;
signal ib_sclk_n : std_logic;
signal ib_clk_adc : std_logic;
signal ib_dip : std_logic_vector(3 downto 0);
signal ib_gmiiclk : std_logic;
--! @}
signal wSysReset : std_ulogic; -- Internal system reset. MUST NOT USED BY DEVICES.
signal wReset : std_ulogic; -- Global reset active HIGH
signal wNReset : std_ulogic; -- Global reset active LOW
signal soft_rst : std_logic; -- reset from exteranl debugger
signal bus_nrst : std_ulogic; -- Global reset and Soft Reset active LOW
signal wClkBus : std_ulogic; -- bus clock from the internal PLL (100MHz virtex6/40MHz Spartan6)
signal wClkAdc : std_ulogic; -- 26 MHz from the internal PLL
signal wPllLocked : std_ulogic; -- PLL status signal. 0=Unlocked; 1=locked.
signal uart1i : uart_in_type;
signal uart1o : uart_out_type;
--! Arbiter is switching only slaves output signal, data from noc
--! is connected to all slaves and to the arbiter itself.
signal aximi : nasti_master_in_type;
signal aximo : nasti_master_out_vector;
signal axisi : nasti_slave_in_type;
signal axiso : nasti_slaves_out_vector;
signal slv_cfg : nasti_slave_cfg_vector;
signal mst_cfg : nasti_master_cfg_vector;
--! From modules-to-tile requests
signal htifo : host_out_vector;
--! Selected request with the highest priority.
signal htifo_mux : host_out_type;
--! tile-to-module response.
signal htifi : host_in_type;
--! response with the 'grant' signal marking the exact recipient.
signal htifi_grant : host_in_type;
signal gnss_i : gns_in_type;
signal gnss_o : gns_out_type;
signal fse_i : fse_in_type;
signal fse_o : fse_out_type;
signal eth_i : eth_in_type;
signal eth_o : eth_out_type;
signal irq_pins : std_logic_vector(CFG_IRQ_TOTAL-1 downto 0);
begin
--! PAD buffers:
irst0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_rst, i_rst);
iclkp0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_sclk_p, i_sclk_p);
iclkn0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_sclk_n, i_sclk_n);
iclk1 : ibuf_tech generic map(CFG_PADTECH) port map (ib_clk_adc, i_clk_adc);
idip0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_dip(0), i_int_clkrf);
dipx : for i in 1 to 3 generate
idipz : ibuf_tech generic map(CFG_PADTECH) port map (ib_dip(i), i_dip(i));
end generate;
igbebuf0 : igdsbuf_tech generic map (CFG_PADTECH) port map (
i_gmiiclk_p, i_gmiiclk_n, ib_gmiiclk);
--! @todo all other in/out signals via buffers:
------------------------------------
-- @brief Internal PLL device instance.
pll0 : SysPLL_tech generic map (
tech => CFG_FABTECH,
tmode_always_ena => CFG_TESTMODE_ON
) port map (
i_reset => ib_rst,
i_int_clkrf => ib_dip(0),
i_clkp => ib_sclk_p,
i_clkn => ib_sclk_n,
i_clk_adc => ib_clk_adc,
o_clk_bus => wClkBus,
o_clk_adc => wClkAdc,
o_locked => wPllLocked
);
wSysReset <= ib_rst or not wPllLocked;
------------------------------------
--! @brief System Reset device instance.
rst0 : reset_global port map (
inSysReset => wSysReset,
inSysClk => wClkBus,
inPllLock => wPllLocked,
outReset => wReset
);
wNReset <= not wReset;
bus_nrst <= not (wReset or soft_rst);
--! @brief AXI4 controller.
ctrl0 : axictrl port map (
clk => wClkBus,
nrst => wNReset,
slvoi => axiso,
mstoi => aximo,
slvio => axisi,
mstio => aximi
);
--! @brief HostIO controller.
htif0 : htifctrl port map (
clk => wClkBus,
nrst => wNReset,
srcsi => htifo,
srcso => htifo_mux,
htifii => htifi,
htifio => htifi_grant
);
mst_cfg(CFG_NASTI_MASTER_CACHED) <= nasti_master_config_none;
aximo(CFG_NASTI_MASTER_CACHED) <= nasti_master_out_none;
mst_cfg(CFG_NASTI_MASTER_UNCACHED) <= nasti_master_config_none;
aximo(CFG_NASTI_MASTER_UNCACHED) <= nasti_master_out_none;
dsu_ena : if CFG_DSU_ENABLE generate
------------------------------------
--! @brief Debug Support Unit with access to the CSRs
--! @details Map address:
--! 0x80080000..0x8009ffff (128 KB total)
dsu0 : nasti_dsu generic map (
xindex => CFG_NASTI_SLAVE_DSU,
xaddr => 16#80080#,
xmask => 16#fffe0#,
htif_index => CFG_HTIF_SRC_DSU
) port map (
clk => wClkBus,
nrst => wNReset,
o_cfg => slv_cfg(CFG_NASTI_SLAVE_DSU),
i_axi => axisi,
o_axi => axiso(CFG_NASTI_SLAVE_DSU),
i_host => htifi_grant,
o_host => htifo(CFG_HTIF_SRC_DSU),
o_soft_reset => soft_rst
);
end generate;
dsu_dis : if not CFG_DSU_ENABLE generate
slv_cfg(CFG_NASTI_SLAVE_DSU) <= nasti_slave_config_none;
axiso(CFG_NASTI_SLAVE_DSU) <= nasti_slave_out_none;
htifo(CFG_HTIF_SRC_DSU) <= host_out_none;
end generate;
------------------------------------
--! @brief BOOT ROM module isntance with the AXI4 interface.
--! @details Map address:
--! 0x00000000..0x00001fff (8 KB total)
boot0 : nasti_bootrom generic map (
memtech => CFG_MEMTECH,
xindex => CFG_NASTI_SLAVE_BOOTROM,
xaddr => 0,
xmask => 16#ffffe#,
sim_hexfile => CFG_SIM_BOOTROM_HEX
) port map (
clk => wClkBus,
nrst => wNReset,
cfg => slv_cfg(CFG_NASTI_SLAVE_BOOTROM),
i => axisi,
o => axiso(CFG_NASTI_SLAVE_BOOTROM)
);
------------------------------------
--! @brief Firmware Image ROM with the AXI4 interface.
--! @details Map address:
--! 0x00100000..0x0013ffff (256 KB total)
--! @warning Don't forget to change ROM_ADDR_WIDTH in rom implementation
img0 : nasti_romimage generic map (
memtech => CFG_MEMTECH,
xindex => CFG_NASTI_SLAVE_ROMIMAGE,
xaddr => 16#00100#,
xmask => 16#fffc0#,
sim_hexfile => CFG_SIM_FWIMAGE_HEX
) port map (
clk => wClkBus,
nrst => wNReset,
cfg => slv_cfg(CFG_NASTI_SLAVE_ROMIMAGE),
i => axisi,
o => axiso(CFG_NASTI_SLAVE_ROMIMAGE)
);
------------------------------------
--! Internal SRAM module instance with the AXI4 interface.
--! @details Map address:
--! 0x10000000..0x1007ffff (512 KB total)
sram0 : nasti_sram generic map (
memtech => CFG_MEMTECH,
xindex => CFG_NASTI_SLAVE_SRAM,
xaddr => 16#10000#,
xmask => 16#fff80#, -- 512 KB mask
abits => (10 + log2(512)), -- 512 KB address
init_file => CFG_SIM_FWIMAGE_HEX -- Used only for inferred
) port map (
clk => wClkBus,
nrst => wNReset,
cfg => slv_cfg(CFG_NASTI_SLAVE_SRAM),
i => axisi,
o => axiso(CFG_NASTI_SLAVE_SRAM)
);
------------------------------------
--! @brief Controller of the LEDs, DIPs and GPIO with the AXI4 interface.
--! @details Map address:
--! 0x80000000..0x80000fff (4 KB total)
gpio0 : nasti_gpio generic map (
xindex => CFG_NASTI_SLAVE_GPIO,
xaddr => 16#80000#,
xmask => 16#fffff#
) port map (
clk => wClkBus,
nrst => wNReset,
cfg => slv_cfg(CFG_NASTI_SLAVE_GPIO),
i => axisi,
o => axiso(CFG_NASTI_SLAVE_GPIO),
i_dip => ib_dip,
o_led => o_led
);
------------------------------------
uart1i.cts <= not i_uart1_ctsn;
uart1i.rd <= i_uart1_rd;
--! @brief UART Controller with the AXI4 interface.
--! @details Map address:
--! 0x80001000..0x80001fff (4 KB total)
uart1 : nasti_uart generic map (
xindex => CFG_NASTI_SLAVE_UART1,
xaddr => 16#80001#,
xmask => 16#FFFFF#,
fifosz => 16
) port map (
nrst => wNReset,
clk => wClkbus,
cfg => slv_cfg(CFG_NASTI_SLAVE_UART1),
i_uart => uart1i,
o_uart => uart1o,
i_axi => axisi,
o_axi => axiso(CFG_NASTI_SLAVE_UART1),
o_irq => irq_pins(CFG_IRQ_UART1)
);
o_uart1_td <= uart1o.td;
o_uart1_rtsn <= not uart1o.rts;
------------------------------------
--! @brief Interrupt controller with the AXI4 interface.
--! @details Map address:
--! 0x80002000..0x80002fff (4 KB total)
irq0 : nasti_irqctrl generic map (
xindex => CFG_NASTI_SLAVE_IRQCTRL,
xaddr => 16#80002#,
xmask => 16#FFFFF#,
htif_index => CFG_HTIF_SRC_IRQCTRL
) port map (
clk => wClkBus,
nrst => bus_nrst,
i_irqs => irq_pins,
o_cfg => slv_cfg(CFG_NASTI_SLAVE_IRQCTRL),
i_axi => axisi,
o_axi => axiso(CFG_NASTI_SLAVE_IRQCTRL),
i_host => htifi_grant,
o_host => htifo(CFG_HTIF_SRC_IRQCTRL)
);
------------------------------------
--! @brief GNSS Engine stub with the AXI4 interface.
--! @details Map address:
--! 0x80003000..0x80003fff (4 KB total)
geneng_ena : if CFG_GNSSLIB_ENABLE generate
gnss_i.nrst <= wNReset;
gnss_i.clk_bus <= wClkBus;
gnss_i.axi <= axisi;
gnss_i.clk_adc <= wClkAdc;
gnss_i.gps_I <= i_gps_I;
gnss_i.gps_Q <= i_gps_Q;
gnss_i.glo_I <= i_glo_I;
gnss_i.glo_Q <= i_glo_I;
gnss0 : gnssengine generic map (
tech => CFG_MEMTECH,
xindex => CFG_NASTI_SLAVE_ENGINE,
xaddr => 16#80003#,
xmask => 16#FFFFF#
) port map (
i => gnss_i,
o => gnss_o
);
axiso(CFG_NASTI_SLAVE_ENGINE) <= gnss_o.axi;
slv_cfg(CFG_NASTI_SLAVE_ENGINE) <= gnss_o.cfg;
irq_pins(CFG_IRQ_GNSSENGINE) <= gnss_o.ms_pulse;
end generate;
geneng_dis : if not CFG_GNSSLIB_ENABLE generate
axiso(CFG_NASTI_SLAVE_ENGINE) <= nasti_slave_out_none;
slv_cfg(CFG_NASTI_SLAVE_ENGINE) <= nasti_slave_config_none;
irq_pins(CFG_IRQ_GNSSENGINE) <= '0';
end generate;
--! @brief RF front-end controller with the AXI4 interface.
--! @details Map address:
--! 0x80004000..0x80004fff (4 KB total)
rf0 : axi_rfctrl generic map (
xindex => CFG_NASTI_SLAVE_RFCTRL,
xaddr => 16#80004#,
xmask => 16#fffff#
) port map (
nrst => wNReset,
clk => wClkBus,
o_cfg => slv_cfg(CFG_NASTI_SLAVE_RFCTRL),
i_axi => axisi,
o_axi => axiso(CFG_NASTI_SLAVE_RFCTRL),
i_gps_ld => i_gps_ld,
i_glo_ld => i_glo_ld,
outSCLK => o_max_sclk,
outSDATA => o_max_sdata,
outCSn => o_max_ncs,
inExtAntStat => i_antext_stat,
inExtAntDetect => i_antext_detect,
outExtAntEna => o_antext_ena,
outIntAntContr => o_antint_contr
);
--! @brief Timers with the AXI4 interface.
--! @details Map address:
--! 0x80005000..0x80005fff (4 KB total)
gptmr0 : nasti_gptimers generic map (
xindex => CFG_NASTI_SLAVE_GPTIMERS,
xaddr => 16#80005#,
xmask => 16#fffff#,
tmr_total => 2
) port map (
clk => wClkBus,
nrst => wNReset,
cfg => slv_cfg(CFG_NASTI_SLAVE_GPTIMERS),
i_axi => axisi,
o_axi => axiso(CFG_NASTI_SLAVE_GPTIMERS),
o_irq => irq_pins(CFG_IRQ_GPTIMERS)
);
--! @brief GPS-CA Fast Search Engine with the AXI4 interface.
--! @details Map address:
--! 0x8000a000..0x8000afff (4 KB total)
fse0_ena : if CFG_GNSSLIB_ENABLE and CFG_GNSSLIB_FSEGPS_ENABLE = 1 generate
fse_i.nrst <= wNReset;
fse_i.clk_bus <= wClkBus;
fse_i.clk_fse <= wClkBus;
fse_i.axi <= axisi;
fse_i.clk_adc <= wClkAdc;
fse_i.I <= i_gps_I;
fse_i.Q <= i_gps_Q;
fse_i.ms_pulse <= gnss_o.ms_pulse;
fse_i.pps <= gnss_o.pps;
fse_i.test_mode <= '0';
fse0 : TopFSE generic map (
tech => CFG_MEMTECH,
xindex => CFG_NASTI_SLAVE_FSE_GPS,
xaddr => 16#8000a#,
xmask => 16#fffff#,
sys => GEN_SYSTEM_GPSCA
) port map (
i => fse_i,
o => fse_o
);
slv_cfg(CFG_NASTI_SLAVE_FSE_GPS) <= fse_o.cfg;
axiso(CFG_NASTI_SLAVE_FSE_GPS) <= fse_o.axi;
end generate;
--! FSE GPS disable
fse0_dis : if CFG_GNSSLIB_FSEGPS_ENABLE = 0 generate
slv_cfg(CFG_NASTI_SLAVE_FSE_GPS) <= nasti_slave_config_none;
axiso(CFG_NASTI_SLAVE_FSE_GPS) <= nasti_slave_out_none;
end generate;
--! Gigabit clock phase rotator with buffers
clkrot90 : clkp90_tech generic map (
tech => CFG_FABTECH,
freq => 125000 -- KHz = 125 MHz
) port map (
i_rst => wReset,
i_clk => ib_gmiiclk,
o_clk => eth_i.gtx_clk,
o_clkp90 => eth_i.tx_clk_90,
o_clk2x => open, -- used in gbe 'io_ref'
o_lock => open
);
--! @brief Ethernet MAC with the AXI4 interface.
--! @details Map address:
--! 0x80040000..0x8007ffff (256 KB total)
--! EDCL IP: 192.168.1.51 = C0.A8.01.33
eth0_ena : if CFG_ETHERNET_ENABLE generate
eth_i.tx_clk <= i_etx_clk;
eth_i.rx_clk <= i_erx_clk;
eth_i.rxd <= i_erxd;
eth_i.rx_dv <= i_erx_dv;
eth_i.rx_er <= i_erx_er;
eth_i.rx_col <= i_erx_col;
eth_i.rx_crs <= i_erx_crs;
eth_i.mdint <= i_emdint;
mac0 : grethaxi generic map (
xslvindex => CFG_NASTI_SLAVE_ETHMAC,
xmstindex => CFG_NASTI_MASTER_ETHMAC,
xaddr => 16#80040#,
xmask => 16#FFFC0#,
xirq => CFG_IRQ_ETHMAC,
memtech => CFG_MEMTECH,
mdcscaler => 60, --! System Bus clock in MHz
enable_mdio => 1,
fifosize => 16,
nsync => 1,
edcl => 1,
edclbufsz => 16,
macaddrh => 16#20789#,
macaddrl => 16#123#,
ipaddrh => 16#C0A8#,
ipaddrl => 16#0033#,
phyrstadr => 7,
enable_mdint => 1,
maxsize => 1518
) port map (
rst => wNReset,
clk => wClkBus,
msti => aximi,
msto => aximo(CFG_NASTI_MASTER_ETHMAC),
mstcfg => mst_cfg(CFG_NASTI_MASTER_ETHMAC),
msto2 => open, -- EDCL separate access is disabled
mstcfg2 => open, -- EDCL separate access is disabled
slvi => axisi,
slvo => axiso(CFG_NASTI_SLAVE_ETHMAC),
slvcfg => slv_cfg(CFG_NASTI_SLAVE_ETHMAC),
ethi => eth_i,
etho => eth_o,
irq => irq_pins(CFG_IRQ_ETHMAC)
);
end generate;
--! Ethernet disabled
eth0_dis : if not CFG_ETHERNET_ENABLE generate
slv_cfg(CFG_NASTI_SLAVE_ETHMAC) <= nasti_slave_config_none;
axiso(CFG_NASTI_SLAVE_ETHMAC) <= nasti_slave_out_none;
mst_cfg(CFG_NASTI_MASTER_ETHMAC) <= nasti_master_config_none;
aximo(CFG_NASTI_MASTER_ETHMAC) <= nasti_master_out_none;
irq_pins(CFG_IRQ_ETHMAC) <= '0';
eth_o <= eth_out_none;
end generate;
emdio_pad : iobuf_tech generic map(
CFG_PADTECH
) port map (
o => eth_i.mdio_i,
io => io_emdio,
i => eth_o.mdio_o,
t => eth_o.mdio_oe
);
o_egtx_clk <= eth_i.gtx_clk;--eth_i.tx_clk_90;
o_etxd <= eth_o.txd;
o_etx_en <= eth_o.tx_en;
o_etx_er <= eth_o.tx_er;
o_emdc <= eth_o.mdc;
o_erstn <= wNReset;
--! @brief Plug'n'Play controller of the current configuration with the
--! AXI4 interface.
--! @details Map address:
--! 0xfffff000..0xffffffff (4 KB total)
pnp0 : nasti_pnp generic map (
xindex => CFG_NASTI_SLAVE_PNP,
xaddr => 16#fffff#,
xmask => 16#fffff#,
tech => CFG_MEMTECH
) port map (
sys_clk => wClkBus,
adc_clk => wClkAdc,
nrst => wNReset,
mstcfg => mst_cfg,
slvcfg => slv_cfg,
cfg => slv_cfg(CFG_NASTI_SLAVE_PNP),
i => axisi,
o => axiso(CFG_NASTI_SLAVE_PNP)
);
end arch_rocket_soc;
|
bsd-2-clause
|
mithro/HDMI2USB
|
hdl/jpeg_encoder/design/r_divider.vhd
|
5
|
6166
|
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2009 --
-- --
--------------------------------------------------------------------------------
-- --
-- Title : DIVIDER --
-- Design : Divider using reciprocal table --
-- Author : Michal Krepa --
-- --
--------------------------------------------------------------------------------
-- --
-- File : R_DIVIDER.VHD --
-- Created : Wed 18-03-2009 --
-- --
--------------------------------------------------------------------------------
-- --
--------------------------------------------------------------------------------
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- /// Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
--------------------------------------------------------------------------------
-- MAIN DIVIDER top level
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.All;
use IEEE.NUMERIC_STD.all;
entity r_divider is
port
(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
a : in STD_LOGIC_VECTOR(11 downto 0);
d : in STD_LOGIC_VECTOR(7 downto 0);
q : out STD_LOGIC_VECTOR(11 downto 0)
) ;
end r_divider ;
architecture rtl of r_divider is
signal romr_datao : std_logic_vector(15 downto 0):=(others => '0');
signal romr_addr : std_logic_vector(7 downto 0):=(others => '0');
signal dividend : signed(11 downto 0):=(others => '0');
signal dividend_d1 : unsigned(11 downto 0):=(others => '0');
signal reciprocal : unsigned(15 downto 0):=(others => '0');
signal mult_out : unsigned(27 downto 0):=(others => '0');
signal mult_out_s : signed(11 downto 0):=(others => '0');
signal signbit : std_logic:='0';
signal signbit_d1 : std_logic:='0';
signal signbit_d2 : std_logic:='0';
signal signbit_d3 : std_logic:='0';
signal round : std_logic:='0';
begin
U_ROMR : entity work.ROMR
generic map
(
ROMADDR_W => 8,
ROMDATA_W => 16
)
port map
(
addr => romr_addr,
clk => CLK,
datao => romr_datao
);
romr_addr <= d;
reciprocal <= unsigned(romr_datao);
dividend <= signed(a);
signbit <= dividend(dividend'high);
rdiv : process(clk,rst)
begin
if rst = '1' then
mult_out <= (others => '0');
mult_out_s <= (others => '0');
dividend_d1 <= (others => '0');
q <= (others => '0');
signbit_d1 <= '0';
signbit_d2 <= '0';
signbit_d3 <= '0';
round <= '0';
elsif clk = '1' and clk'event then
signbit_d1 <= signbit;
signbit_d2 <= signbit_d1;
signbit_d3 <= signbit_d2;
if signbit = '1' then
dividend_d1 <= unsigned(0-dividend);
else
dividend_d1 <= unsigned(dividend);
end if;
mult_out <= dividend_d1 * reciprocal;
if signbit_d2 = '0' then
mult_out_s <= resize(signed(mult_out(27 downto 16)),mult_out_s'length);
else
mult_out_s <= resize(0-signed(mult_out(27 downto 16)),mult_out_s'length);
end if;
round <= mult_out(15);
if signbit_d3 = '0' then
if round = '1' then
q <= std_logic_vector(mult_out_s + 1);
else
q <= std_logic_vector(mult_out_s);
end if;
else
if round = '1' then
q <= std_logic_vector(mult_out_s - 1);
else
q <= std_logic_vector(mult_out_s);
end if;
end if;
end if;
end process;
end rtl;
|
bsd-2-clause
|
mithro/HDMI2USB
|
ipcore_dir/clkGen/simulation/timing/clkGen_tb.vhd
|
3
|
6295
|
-- file: clkGen_tb.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- Clocking wizard demonstration testbench
------------------------------------------------------------------------------
-- This demonstration testbench instantiates the example design for the
-- clocking wizard. Input clocks are toggled, which cause the clocking
-- network to lock and the counters to increment.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
library std;
use std.textio.all;
library work;
use work.all;
entity clkGen_tb is
end clkGen_tb;
architecture test of clkGen_tb is
-- Clock to Q delay of 100 ps
constant TCQ : time := 100 ps;
-- timescale is 1ps
constant ONE_NS : time := 1 ns;
-- how many cycles to run
constant COUNT_PHASE : integer := 1024 + 1;
-- we'll be using the period in many locations
constant PER1 : time := 10.000 ns;
-- Declare the input clock signals
signal CLK_IN1 : std_logic := '1';
-- The high bits of the sampling counters
signal COUNT : std_logic_vector(3 downto 1);
signal COUNTER_RESET : std_logic := '0';
signal timeout_counter : std_logic_vector (13 downto 0) := (others => '0');
-- signal defined to stop mti simulation without severity failure in the report
signal end_of_sim : std_logic := '0';
signal CLK_OUT : std_logic_vector(3 downto 1);
--Freq Check using the M & D values setting and actual Frequency generated
component clkGen_exdes
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Reset that only drives logic in example design
COUNTER_RESET : in std_logic;
CLK_OUT : out std_logic_vector(3 downto 1) ;
-- High bits of counters driven by clocks
COUNT : out std_logic_vector(3 downto 1)
);
end component;
begin
-- Input clock generation
--------------------------------------
process begin
CLK_IN1 <= not CLK_IN1; wait for (PER1/2);
end process;
-- Test sequence
process
procedure simtimeprint is
variable outline : line;
begin
write(outline, string'("## SYSTEM_CYCLE_COUNTER "));
write(outline, NOW/PER1);
write(outline, string'(" ns"));
writeline(output,outline);
end simtimeprint;
procedure simfreqprint (period : time; clk_num : integer) is
variable outputline : LINE;
variable str1 : string(1 to 16);
variable str2 : integer;
variable str3 : string(1 to 2);
variable str4 : integer;
variable str5 : string(1 to 4);
begin
str1 := "Freq of CLK_OUT(";
str2 := clk_num;
str3 := ") ";
str4 := 1000000 ps/period ;
str5 := " MHz" ;
write(outputline, str1 );
write(outputline, str2);
write(outputline, str3);
write(outputline, str4);
write(outputline, str5);
writeline(output, outputline);
end simfreqprint;
begin
report "Timing checks are not valid" severity note;
-- can't probe into hierarchy, wait "some time" for lock
wait for (PER1*2500);
wait for (PER1*20);
COUNTER_RESET <= '1';
wait for (PER1*19.5);
COUNTER_RESET <= '0';
wait for (PER1*1);
report "Timing checks are valid" severity note;
wait for (PER1*COUNT_PHASE);
simtimeprint;
end_of_sim <= '1';
wait for 1 ps;
report "Simulation Stopped." severity failure;
wait;
end process;
-- Instantiation of the example design containing the clock
-- network and sampling counters
-----------------------------------------------------------
dut : clkGen_exdes
port map
(-- Clock in ports
CLK_IN1 => CLK_IN1,
-- Reset for logic in example design
COUNTER_RESET => COUNTER_RESET,
CLK_OUT => CLK_OUT,
-- High bits of the counters
COUNT => COUNT);
-- Freq Check
end test;
|
bsd-2-clause
|
pombredanne/pygments-1
|
tests/examplefiles/test.vhdl
|
75
|
4446
|
library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity top_testbench is --test
generic ( -- test
n : integer := 8 -- test
); -- test
end top_testbench; -- test
architecture top_testbench_arch of top_testbench is
component top is
generic (
n : integer
) ;
port (
clk : in std_logic;
rst : in std_logic;
d1 : in std_logic_vector (n-1 downto 0);
d2 : in std_logic_vector (n-1 downto 0);
operation : in std_logic;
result : out std_logic_vector (2*n-1 downto 0)
);
end component;
signal clk : std_logic;
signal rst : std_logic;
signal operation : std_logic;
signal d1 : std_logic_vector (n-1 downto 0);
signal d2 : std_logic_vector (n-1 downto 0);
signal result : std_logic_vector (2*n-1 downto 0);
type test_type is ( a1, a2, a3, a4, a5, a6, a7, a8, a9, a10);
attribute enum_encoding of my_state : type is "001 010 011 100 111";
begin
TESTUNIT : top generic map (n => n)
port map (clk => clk,
rst => rst,
d1 => d1,
d2 => d2,
operation => operation,
result => result);
clock_process : process
begin
clk <= '0';
wait for 5 ns;
clk <= '1';
wait for 5 ns;
end process;
data_process : process
begin
-- test case #1
operation <= '0';
rst <= '1';
wait for 5 ns;
rst <= '0';
wait for 5 ns;
d1 <= std_logic_vector(to_unsigned(60, d1'length));
d2 <= std_logic_vector(to_unsigned(12, d2'length));
wait for 360 ns;
assert (result = std_logic_vector(to_unsigned(720, result'length)))
report "Test case #1 failed" severity error;
-- test case #2
operation <= '0';
rst <= '1';
wait for 5 ns;
rst <= '0';
wait for 5 ns;
d1 <= std_logic_vector(to_unsigned(55, d1'length));
d2 <= std_logic_vector(to_unsigned(1, d2'length));
wait for 360 ns;
assert (result = std_logic_vector(to_unsigned(55, result'length)))
report "Test case #2 failed" severity error;
-- etc
end process;
end top_testbench_arch;
configuration testbench_for_top of top_testbench is
for top_testbench_arch
for TESTUNIT : top
use entity work.top(top_arch);
end for;
end for;
end testbench_for_top;
function compare(A: std_logic, B: std_Logic) return std_logic is
constant pi : real := 3.14159;
constant half_pi : real := pi / 2.0;
constant cycle_time : time := 2 ns;
constant N, N5 : integer := 5;
begin
if (A = '0' and B = '1') then
return B;
else
return A;
end if ;
end compare;
procedure print(P : std_logic_vector(7 downto 0);
U : std_logic_vector(3 downto 0)) is
variable my_line : line;
alias swrite is write [line, string, side, width] ;
begin
swrite(my_line, "sqrt( ");
write(my_line, P);
swrite(my_line, " )= ");
write(my_line, U);
writeline(output, my_line);
end print;
entity add32csa is -- one stage of carry save adder for multiplier
port(
b : in std_logic; -- a multiplier bit
a : in std_logic_vector(31 downto 0); -- multiplicand
sum_in : in std_logic_vector(31 downto 0); -- sums from previous stage
cin : in std_logic_vector(31 downto 0); -- carrys from previous stage
sum_out : out std_logic_vector(31 downto 0); -- sums to next stage
cout : out std_logic_vector(31 downto 0)); -- carrys to next stage
end add32csa;
ARCHITECTURE circuits of add32csa IS
SIGNAL zero : STD_LOGIC_VECTOR(31 downto 0) := X"00000000";
SIGNAL aa : std_logic_vector(31 downto 0) := X"00000000";
COMPONENT fadd -- duplicates entity port
PoRT(a : in std_logic;
b : in std_logic;
cin : in std_logic;
s : out std_logic;
cout : out std_logic);
end comPonent fadd;
begin -- circuits of add32csa
aa <= a when b='1' else zero after 1 ns;
stage: for I in 0 to 31 generate
sta: fadd port map(aa(I), sum_in(I), cin(I) , sum_out(I), cout(I));
end generate stage;
end architecture circuits; -- of add32csa
|
bsd-2-clause
|
mithro/HDMI2USB
|
hdl/misc/debouncer.vhd
|
3
|
678
|
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
entity debouncer is
port
( clk : in std_logic;
rst_n : in std_logic;
insig : in std_logic;
outsig : out std_logic
);
end entity debouncer;
architecture rtl of debouncer is
signal input_q : std_logic_vector(7 downto 0);
begin
process(rst_n,clk)
begin
if rst_n = '0' then
input_q <= (others => '0');
outsig <= '0';
elsif rising_edge(clk) then
input_q <= (input_q(6 downto 0) & insig);
if input_q = "11111111" then
outsig <= '1';
elsif input_q = "00000000" then
outsig <= '0';
end if;
end if;
end process;
end architecture;
|
bsd-2-clause
|
mithro/HDMI2USB
|
ipcore_dir/ddr2ram/user_design/sim/sp6_data_gen.vhd
|
20
|
37259
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: sp6_data_gen.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:16:40 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This module generates different data pattern as described in
-- parameter DATA_PATTERN and is set up for Spartan 6 family.
-- Reference:
-- Revision History:
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
entity sp6_data_gen is
generic (
ADDR_WIDTH : integer := 32;
BL_WIDTH : integer := 6;
DWIDTH : integer := 32;
DATA_PATTERN : string := "DGEN_ALL"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : integer := 8;
COLUMN_WIDTH : integer := 10
);
port (
clk_i : in std_logic; --
rst_i : in std_logic;
prbs_fseed_i : in std_logic_vector(31 downto 0);
data_mode_i : in std_logic_vector(3 downto 0); -- "00" = bram;
data_rdy_i : in std_logic;
cmd_startA : in std_logic;
cmd_startB : in std_logic;
cmd_startC : in std_logic;
cmd_startD : in std_logic;
cmd_startE : in std_logic;
fixed_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0); -- generated address used to determine data pattern.
user_burst_cnt : in std_logic_vector(6 downto 0); -- generated burst length for control the burst data
fifo_rdy_i : in std_logic; -- connect from mcb_wr_full when used as wr_data_gen
-- connect from mcb_rd_empty when used as rd_data_gen
-- When both data_rdy and data_valid is asserted, the ouput data is valid.
data_o : out std_logic_vector(DWIDTH - 1 downto 0) -- generated data pattern
);
end entity sp6_data_gen;
architecture trans of sp6_data_gen is
COMPONENT data_prbs_gen IS
GENERIC (
EYE_TEST : STRING := "FALSE";
PRBS_WIDTH : INTEGER := 32;
SEED_WIDTH : INTEGER := 32
);
PORT (
clk_i : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
rst_i : IN STD_LOGIC;
prbs_fseed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
prbs_seed_init : IN STD_LOGIC;
prbs_seed_i : IN STD_LOGIC_VECTOR(PRBS_WIDTH - 1 DOWNTO 0);
prbs_o : OUT STD_LOGIC_VECTOR(PRBS_WIDTH - 1 DOWNTO 0)
);
END COMPONENT;
--
signal prbs_data : std_logic_vector(31 downto 0);
signal adata : std_logic_vector(31 downto 0);
signal hdata : std_logic_vector(DWIDTH - 1 downto 0);
signal ndata : std_logic_vector(DWIDTH - 1 downto 0);
signal w1data : std_logic_vector(DWIDTH - 1 downto 0);
signal data : std_logic_vector(DWIDTH - 1 downto 0);
signal burst_count_reached2 : std_logic;
signal data_valid : std_logic;
signal walk_cnt : std_logic_vector(2 downto 0);
signal user_address : std_logic_vector(ADDR_WIDTH - 1 downto 0);
signal i : integer;
signal j : integer;
signal user_bl : std_logic_vector(BL_WIDTH - 1 downto 0);
signal BLANK : std_logic_vector(7 downto 0);
signal SHIFT_0 : std_logic_vector(7 downto 0);
signal SHIFT_1 : std_logic_vector(7 downto 0);
signal SHIFT_2 : std_logic_vector(7 downto 0);
signal SHIFT_3 : std_logic_vector(7 downto 0);
signal SHIFT_4 : std_logic_vector(7 downto 0);
signal SHIFT_5 : std_logic_vector(7 downto 0);
signal SHIFT_6 : std_logic_vector(7 downto 0);
signal SHIFT_7 : std_logic_vector(7 downto 0);
signal SHIFTB_0 : std_logic_vector(31 downto 0);
signal SHIFTB_1 : std_logic_vector(31 downto 0);
signal SHIFTB_2 : std_logic_vector(31 downto 0);
signal SHIFTB_3 : std_logic_vector(31 downto 0);
signal SHIFTB_4 : std_logic_vector(31 downto 0);
signal SHIFTB_5 : std_logic_vector(31 downto 0);
signal SHIFTB_6 : std_logic_vector(31 downto 0);
signal SHIFTB_7 : std_logic_vector(31 downto 0);
signal TSTB : std_logic_vector(3 downto 0);
--*********************************************************************************************
-- 4'b0000: data = 32'b0; //bram
-- 4'b0001: data = 32'b0; // fixed
-- address as data
-- DGEN_HAMMER
-- DGEN_NEIGHBOUR
-- DGEN_WALKING1
-- DGEN_WALKING0
--bram
-- fixed
-- address as data
-- DGEN_HAMMER
-- DGEN_NEIGHBOUR
-- DGEN_WALKING1
-- DGEN_WALKING0
--bram
-- fixed
-- address as data
-- DGEN_HAMMER
-- DGEN_NEIGHBOUR
-- DGEN_WALKING1
-- DGEN_WALKING0
-- WALKING ONES:
-- WALKING ONE
-- NEIGHBOR ONE
-- WALKING ZERO
-- WALKING ONE
-- NEIGHBOR ONE
-- WALKING ZERO
signal tmpdata : std_logic_vector(DWIDTH - 1 downto 0);
signal ndata_rising : std_logic;
signal shift_en : std_logic;
signal data_clk_en : std_logic;
SIGNAL ZEROS : STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0) ;--:= (others => '0');
begin
ZEROS <= (others => '0');
data_o <= data;
xhdl0 : if (DWIDTH = 32) generate
process (adata, hdata, ndata, w1data, prbs_data, data_mode_i,fixed_data_i)
begin
case data_mode_i is
when "0001" =>
data <= fixed_data_i;
when "0010" =>
data <= adata;
when "0011" =>
data <= hdata;
when "0100" =>
data <= ndata;
when "0101" =>
data <= w1data;
when "0110" =>
data <= w1data;
when "0111" =>
data <= prbs_data;
WHEN OTHERS =>
data <= (others => '0');
END CASE;
END PROCESS;
end generate;
xhdl1 : if (DWIDTH = 64) generate
process (adata, hdata, ndata, w1data, prbs_data, data_mode_i,fixed_data_i)
begin
case data_mode_i is
when "0000" =>
data <= (others => '0');
when "0001" =>
data <= fixed_data_i;
when "0010" =>
-- data <= (adata & adata)(31 downto 0);
data <= (adata & adata);
when "0011" =>
data <= hdata;
when "0100" =>
data <= ndata;
when "0101" =>
data <= w1data;
when "0110" =>
data <= w1data;
when "0111" =>
-- data <= (prbs_data & prbs_data)(31 downto 0);
data <= (prbs_data & prbs_data);
when others =>
data <= (others => '0');
end case;
end process;
end generate;
xhdl2 : if (DWIDTH = 128) generate
process (adata, hdata, ndata, w1data, prbs_data, data_mode_i,fixed_data_i)
begin
case data_mode_i is
when "0000" =>
data <= (others => '0');
when "0001" =>
data <= fixed_data_i;
when "0010" =>
-- data <= (adata & adata & adata & adata)(31 downto 0);
data <= (adata & adata & adata & adata);
when "0011" =>
data <= hdata;
when "0100" =>
data <= ndata;
when "0101" =>
data <= w1data;
when "0110" =>
data <= w1data;
when "0111" =>
-- data <= (prbs_data & prbs_data & prbs_data & prbs_data)(31 downto 0);
data <= (prbs_data & prbs_data & prbs_data & prbs_data);
when others =>
data <= (others => '0');--"00000000000000000000000000000000";
end case;
end process;
end generate;
xhdl3 : if ((DWIDTH = 64) or (DWIDTH = 128)) generate
process (data_mode_i)
begin
if (data_mode_i = "0101" or data_mode_i = "0100") then
BLANK <= "00000000";
SHIFT_0 <= "00000001";
SHIFT_1 <= "00000010";
SHIFT_2 <= "00000100";
SHIFT_3 <= "00001000";
SHIFT_4 <= "00010000";
SHIFT_5 <= "00100000";
SHIFT_6 <= "01000000";
SHIFT_7 <= "10000000";
elsif (data_mode_i = "0100") then
BLANK <= "00000000";
SHIFT_0 <= "00000001";
SHIFT_1 <= "00000010";
SHIFT_2 <= "00000100";
SHIFT_3 <= "00001000";
SHIFT_4 <= "00010000";
SHIFT_5 <= "00100000";
SHIFT_6 <= "01000000";
SHIFT_7 <= "10000000";
elsif (data_mode_i = "0110") then
BLANK <= "11111111";
SHIFT_0 <= "11111110";
SHIFT_1 <= "11111101";
SHIFT_2 <= "11111011";
SHIFT_3 <= "11110111";
SHIFT_4 <= "11101111";
SHIFT_5 <= "11011111";
SHIFT_6 <= "10111111";
SHIFT_7 <= "01111111";
else
BLANK <= "11111111";
SHIFT_0 <= "11111110";
SHIFT_1 <= "11111101";
SHIFT_2 <= "11111011";
SHIFT_3 <= "11110111";
SHIFT_4 <= "11101111";
SHIFT_5 <= "11011111";
SHIFT_6 <= "10111111";
SHIFT_7 <= "01111111";
end if;
end process;
end generate;
process (data_mode_i)
begin
if (data_mode_i = "0101") then
SHIFTB_0 <= "00000000000000100000000000000001";
SHIFTB_1 <= "00000000000010000000000000000100";
SHIFTB_2 <= "00000000001000000000000000010000";
SHIFTB_3 <= "00000000100000000000000001000000";
SHIFTB_4 <= "00000010000000000000000100000000";
SHIFTB_5 <= "00001000000000000000010000000000";
SHIFTB_6 <= "00100000000000000001000000000000";
SHIFTB_7 <= "10000000000000000100000000000000";
elsif (data_mode_i = "0100") then
SHIFTB_0 <= "00000000000000000000000000000001";
SHIFTB_1 <= "00000000000000000000000000000010";
SHIFTB_2 <= "00000000000000000000000000000100";
SHIFTB_3 <= "00000000000000000000000000001000";
SHIFTB_4 <= "00000000000000000000000000010000";
SHIFTB_5 <= "00000000000000000000000000100000";
SHIFTB_6 <= "00000000000000000000000001000000";
SHIFTB_7 <= "00000000000000000000000010000000";
else
SHIFTB_0 <= "11111111111111011111111111111110";
SHIFTB_1 <= "11111111111101111111111111111011";
SHIFTB_2 <= "11111111110111111111111111101111";
SHIFTB_3 <= "11111111011111111111111110111111";
SHIFTB_4 <= "11111101111111111111111011111111";
SHIFTB_5 <= "11110111111111111111101111111111";
SHIFTB_6 <= "11011111111111111110111111111111";
SHIFTB_7 <= "01111111111111111011111111111111";
end if;
end process;
xhdl4 : if (DWIDTH = 32 and (DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i = '1') then
w1data <= (others => '0');
ndata_rising <= '1';
shift_en <= '0';
elsif ((fifo_rdy_i = '1' and user_burst_cnt /= "0000000") or cmd_startC = '1') then
if (NUM_DQ_PINS = 16) then
if (cmd_startC = '1') then
case addr_i(4 downto 2) is
when "000" =>
w1data <= SHIFTB_0;
when "001" =>
w1data <= SHIFTB_1;
when "010" =>
w1data <= SHIFTB_2;
when "011" =>
w1data <= SHIFTB_3;
when "100" =>
w1data <= SHIFTB_4;
when "101" =>
w1data <= SHIFTB_5;
when "110" =>
w1data <= SHIFTB_6;
when "111" =>
w1data <= SHIFTB_7;
when others =>
w1data <= SHIFTB_0;
end case;
ndata_rising <= '0'; --(NUM_DQ_PINS == 16) (cmd_startC)
--shifting
elsif (data_mode_i = "0100") then
w1data <= ("0000000000000000" & w1data(14 downto 0) & w1data(15));
else
w1data <= (w1data(29 downto 16) & w1data(31 downto 30) & w1data(13 downto 0) & w1data(15 downto 14)); --(DQ_PINS == 16
end if;
elsif (NUM_DQ_PINS = 8) then
if (cmd_startC = '1') then -- loading data pattern according the incoming address
case addr_i(2) is
when '0' =>
w1data <= SHIFTB_0;
when '1' =>
w1data <= SHIFTB_1;
when others =>
w1data <= SHIFTB_0;
end case;
else
-- (cmd_startC)
-- Shifting
-- need neigbour pattern ********************
w1data <= (w1data(27 downto 24) & w1data(31 downto 28) & w1data(19 downto 16) & w1data(23 downto 20) & w1data(11 downto 8) & w1data(15 downto 12) & w1data(3 downto 0) & w1data(7 downto 4)); --(NUM_DQ_PINS == 8)
end if;
elsif (NUM_DQ_PINS = 4) then -- NUM_DQ_PINS == 4
-- need neigbour pattern ********************
if (data_mode_i = "0100") then
w1data <= "00001000000001000000001000000001";
else
w1data <= "10000100001000011000010000100001"; -- (NUM_DQ_PINS_4
end if;
end if;
end if;
end if;
end process;
-- <outdent> -- DWIDTH == 32
end generate;
xhdl5 : if (DWIDTH = 64 and (DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i = '1') then
w1data <= (others => '0');
elsif ((fifo_rdy_i = '1' and user_burst_cnt /= "0000000") or cmd_startC = '1') then
if (NUM_DQ_PINS = 16) then
if (cmd_startC = '1') then
case addr_i(4 downto 3) is
-- 7:0
when "00" =>
w1data(2 * DWIDTH / 4 - 1 downto 0 * DWIDTH / 4) <= SHIFTB_0(31 downto 0);
w1data(4 * DWIDTH / 4 - 1 downto 2 * DWIDTH / 4) <= SHIFTB_1(31 downto 0);
when "01" =>
w1data(2 * DWIDTH / 4 - 1 downto 0 * DWIDTH / 4) <= SHIFTB_2(31 downto 0);
w1data(4 * DWIDTH / 4 - 1 downto 2 * DWIDTH / 4) <= SHIFTB_3(31 downto 0);
when "10" =>
w1data(2 * DWIDTH / 4 - 1 downto 0 * DWIDTH / 4) <= SHIFTB_4(31 downto 0);
w1data(4 * DWIDTH / 4 - 1 downto 2 * DWIDTH / 4) <= SHIFTB_5(31 downto 0);
when "11" =>
w1data(2 * DWIDTH / 4 - 1 downto 0 * DWIDTH / 4) <= SHIFTB_6(31 downto 0);
w1data(4 * DWIDTH / 4 - 1 downto 2 * DWIDTH / 4) <= SHIFTB_7(31 downto 0);
--15:8
when others =>
w1data <= (ZEROS(DWIDTH-1 downto 8) & BLANK);
end case;
else
--(NUM_DQ_PINS == 16) (cmd_startC)
--shifting
if (data_mode_i = "0100") then
w1data(63 downto 48) <= "0000000000000000";
w1data(47 downto 32) <= (w1data(45 downto 32) & w1data(47 downto 46));
w1data(31 downto 16) <= "0000000000000000";
w1data(15 downto 0) <= (w1data(13 downto 0) & w1data(15 downto 14));
else
-- w1data(DWIDTH - 1 downto 0) <= (w1data(4 * DWIDTH / 4 - 5 downto 4 * DWIDTH / 4 - 16) & w1data(4 * DWIDTH / 4 - 1 downto 4 * DWIDTH / 4 - 4) & w1data(3 * DWIDTH / 4 - 5 downto 3 * DWIDTH / 4 - 16) & w1data(3 * DWIDTH / 4 - 1 downto 3 * DWIDTH / 4 - 4) & w1data(2 * DWIDTH / 4 - 5 downto 2 * DWIDTH / 4 - 16) & w1data(2 * DWIDTH / 4 - 1 downto 2 * DWIDTH / 4 - 4) & w1data(1 * DWIDTH / 4 - 5 to 1 * DWIDTH / 4 - 16) & w1data(1 * DWIDTH / 4 - 1 downto 1 * DWIDTH / 4 - 4))(31 downto 0);
w1data(DWIDTH - 1 downto 0) <= (w1data(4 * DWIDTH / 4 - 5 downto 4 * DWIDTH / 4 - 16) &
w1data(4 * DWIDTH / 4 - 1 downto 4 * DWIDTH / 4 - 4) &
w1data(3 * DWIDTH / 4 - 5 downto 3 * DWIDTH / 4 - 16) &
w1data(3 * DWIDTH / 4 - 1 downto 3 * DWIDTH / 4 - 4) &
w1data(2 * DWIDTH / 4 - 5 downto 2 * DWIDTH / 4 - 16) &
w1data(2 * DWIDTH / 4 - 1 downto 2 * DWIDTH / 4 - 4) &
w1data(1 * DWIDTH / 4 - 5 downto 1 * DWIDTH / 4 - 16) &
w1data(1 * DWIDTH / 4 - 1 downto 1 * DWIDTH / 4 - 4));
end if;
end if;
--(DQ_PINS == 16
elsif (NUM_DQ_PINS = 8) then
if (cmd_startC = '1') then -- loading data pattern according the incoming address
if (data_mode_i = "0100") then
case addr_i(3) is
when '0' =>
w1data <= (BLANK & SHIFT_3 & BLANK & SHIFT_2 & BLANK & SHIFT_1 & BLANK & SHIFT_0);
when '1' =>
w1data <= (BLANK & SHIFT_7 & BLANK & SHIFT_6 & BLANK & SHIFT_5 & BLANK & SHIFT_4);
--15:8
when others =>
w1data <= (others => '0');--"00000000000000000000000000000000";
end case;
else
w1data <= ("10000000010000000010000000010000" & "00001000000001000000001000000001"); --**** checked
w1data <= ("10000000010000000010000000010000" & "00001000000001000000001000000001"); --**** checked
w1data <= ("10000000010000000010000000010000" & "00001000000001000000001000000001"); --**** checked
end if;
-- Shifting
elsif (data_mode_i = "0100") then
w1data(63 downto 56) <= "00000000";
w1data(55 downto 48) <= (w1data(51 downto 48) & w1data(55 downto 52));
w1data(47 downto 40) <= "00000000";
w1data(39 downto 32) <= (w1data(35 downto 32) & w1data(39 downto 36));
w1data(31 downto 24) <= "00000000";
w1data(23 downto 16) <= (w1data(19 downto 16) & w1data(23 downto 20));
w1data(15 downto 8) <= "00000000";
w1data(7 downto 0) <= (w1data(3 downto 0) & w1data(7 downto 4));
else
w1data <= w1data; --(NUM_DQ_PINS == 8)
end if;
elsif (NUM_DQ_PINS = 4) then -- NUM_DQ_PINS == 4
if (data_mode_i = "0100") then
w1data <= "0000100000000100000000100000000100001000000001000000001000000001";
else
w1data <= "1000010000100001100001000010000110000100001000011000010000100001";
end if;
end if;
end if;
end if;
end process;
end generate;
xhdl6 : if (DWIDTH = 128 and (DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i = '1') then
w1data <= (others => '0');
elsif ((fifo_rdy_i = '1' and user_burst_cnt /= "0000000") or cmd_startC = '1') then
if (NUM_DQ_PINS = 16) then
if (cmd_startC = '1') then
case addr_i(4) is
-- 32
when '0' =>
w1data(1 * DWIDTH / 4 - 1 downto 0 * DWIDTH / 4) <= SHIFTB_0(31 downto 0);
w1data(2 * DWIDTH / 4 - 1 downto 1 * DWIDTH / 4) <= SHIFTB_1(31 downto 0);
w1data(3 * DWIDTH / 4 - 1 downto 2 * DWIDTH / 4) <= SHIFTB_2(31 downto 0);
w1data(4 * DWIDTH / 4 - 1 downto 3 * DWIDTH / 4) <= SHIFTB_3(31 downto 0);
-- 32
when '1' =>
w1data(1 * DWIDTH / 4 - 1 downto 0 * DWIDTH / 4) <= SHIFTB_4(31 downto 0);
w1data(2 * DWIDTH / 4 - 1 downto 1 * DWIDTH / 4) <= SHIFTB_5(31 downto 0);
w1data(3 * DWIDTH / 4 - 1 downto 2 * DWIDTH / 4) <= SHIFTB_6(31 downto 0);
w1data(4 * DWIDTH / 4 - 1 downto 3 * DWIDTH / 4) <= SHIFTB_7(31 downto 0);
--15:8
when others =>
w1data <= ZEROS(DWIDTH-1 downto 8) & BLANK;
end case;
else
--(NUM_DQ_PINS == 16) (cmd_startC)
--shifting
if (data_mode_i = "0100") then
w1data(127 downto 112) <= "0000000000000000";
w1data(111 downto 96) <= (w1data(107 downto 96) & w1data(111 downto 108));
w1data(95 downto 80) <= "0000000000000000";
w1data(79 downto 64) <= (w1data(75 downto 64) & w1data(79 downto 76));
w1data(63 downto 48) <= "0000000000000000";
w1data(47 downto 32) <= (w1data(43 downto 32) & w1data(47 downto 44));
w1data(31 downto 16) <= "0000000000000000";
w1data(15 downto 0) <= (w1data(11 downto 0) & w1data(15 downto 12));
else
w1data(DWIDTH - 1 downto 0) <= (w1data(4 * DWIDTH / 4 - 9 downto 4 * DWIDTH / 4 - 16) & w1data(4 * DWIDTH / 4 - 1 downto 4 * DWIDTH / 4 - 8) & w1data(4 * DWIDTH / 4 - 25 downto 4 * DWIDTH / 4 - 32) & w1data(4 * DWIDTH / 4 - 17 downto 4 * DWIDTH / 4 - 24) & w1data(3 * DWIDTH / 4 - 9 downto 3 * DWIDTH / 4 - 16) & w1data(3 * DWIDTH / 4 - 1 downto 3 * DWIDTH / 4 - 8) & w1data(3 * DWIDTH / 4 - 25 downto 3 * DWIDTH / 4 - 32) & w1data(3 * DWIDTH / 4 - 17 downto 3 * DWIDTH / 4 - 24) & w1data(2 * DWIDTH / 4 - 9 downto 2 * DWIDTH / 4 - 16) & w1data(2 * DWIDTH / 4 - 1 downto 2 * DWIDTH / 4 - 8) & w1data(2 * DWIDTH / 4 - 25 downto 2 * DWIDTH / 4 - 32) & w1data(2 * DWIDTH / 4 - 17 downto 2 * DWIDTH / 4 - 24) & w1data(1 * DWIDTH / 4 - 9 downto 1 * DWIDTH / 4 - 16) & w1data(1 * DWIDTH / 4 - 1 downto 1 * DWIDTH / 4 - 8) & w1data(1 * DWIDTH / 4 - 25 downto 1 * DWIDTH / 4 - 32) & w1data(1 * DWIDTH / 4 - 17 downto 1 * DWIDTH / 4 - 24));
end if;
end if;
--(DQ_PINS == 16
elsif (NUM_DQ_PINS = 8) then
if (cmd_startC = '1') then -- loading data pattern according the incoming address
if (data_mode_i = "0100") then
w1data <= (BLANK & SHIFT_7 & BLANK & SHIFT_6 & BLANK & SHIFT_5 & BLANK & SHIFT_4 & BLANK & SHIFT_3 & BLANK & SHIFT_2 & BLANK & SHIFT_1 & BLANK & SHIFT_0);
else
w1data <= (SHIFT_7 & SHIFT_6 & SHIFT_5 & SHIFT_4 & SHIFT_3 & SHIFT_2 & SHIFT_1 & SHIFT_0 & SHIFT_7 & SHIFT_6 & SHIFT_5 & SHIFT_4 & SHIFT_3 & SHIFT_2 & SHIFT_1 & SHIFT_0); -- (cmd_startC)
end if;
else
-- Shifting
--{w1data[96:64], w1data[127:97],w1data[31:0], w1data[63:32]};
w1data <= w1data; -- else
end if;
--(NUM_DQ_PINS == 8)
elsif (data_mode_i = "0100") then
w1data <= "00001000000001000000001000000001000010000000010000000010000000010000100000000100000000100000000100001000000001000000001000000001";
else
w1data <= "10000100001000011000010000100001100001000010000110000100001000011000010000100001100001000010000110000100001000011000010000100001";
end if;
end if;
end if;
end process;
end generate;
-- HAMMER_PATTERN: Alternating 1s and 0s on DQ pins
-- => the rsing data pattern will be 32'b11111111_11111111_11111111_11111111
-- => the falling data pattern will be 32'b00000000_00000000_00000000_00000000
xhdl7 : if (DWIDTH = 32 and (DATA_PATTERN = "DGEN_HAMMER" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i = '1') then
hdata <= (others => '0');
-- elsif ((fifo_rdy_i = '1' and user_burst_cnt(5 downto 0) /= "000000") or cmd_startC = '1') then
elsif ((fifo_rdy_i = '1' and user_burst_cnt /= 0) or cmd_startC = '1') then
if (NUM_DQ_PINS = 16) then
hdata <= "00000000000000001111111111111111";
elsif (NUM_DQ_PINS = 8) then
hdata <= "00000000111111110000000011111111"; -- NUM_DQ_PINS == 4
elsif (NUM_DQ_PINS = 4) then
hdata <= "00001111000011110000111100001111";
end if;
end if;
end if;
end process;
end generate;
xhdl8 : if (DWIDTH = 64 and (DATA_PATTERN = "DGEN_HAMMER" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i = '1') then
hdata <= (others => '0');
elsif ((fifo_rdy_i = '1' and user_burst_cnt /= 0) or cmd_startC = '1') then
if (NUM_DQ_PINS = 16) then
hdata <= "0000000000000000111111111111111100000000000000001111111111111111";
elsif (NUM_DQ_PINS = 8) then
hdata <= "0000000011111111000000001111111100000000111111110000000011111111";
elsif (NUM_DQ_PINS = 4) then
hdata <= "0000111100001111000011110000111100001111000011110000111100001111";
end if;
end if;
end if;
end process;
end generate;
xhdl9 : if (DWIDTH = 128 and (DATA_PATTERN = "DGEN_HAMMER" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i = '1') then
hdata <= (others => '0');
elsif ((fifo_rdy_i = '1' and user_burst_cnt /= 0) or cmd_startC = '1') then
if (NUM_DQ_PINS = 16) then
hdata <= "00000000000000001111111111111111000000000000000011111111111111110000000000000000111111111111111100000000000000001111111111111111";
elsif (NUM_DQ_PINS = 8) then
hdata <= "00000000111111110000000011111111000000001111111100000000111111110000000011111111000000001111111100000000111111110000000011111111";
elsif (NUM_DQ_PINS = 4) then
hdata <= "00001111000011110000111100001111000011110000111100001111000011110000111100001111000011110000111100001111000011110000111100001111";
end if;
end if;
end if;
end process;
end generate;
process (w1data, hdata)
begin
for i in 0 to DWIDTH - 1 loop
ndata(i) <= hdata(i) xor w1data(i);
end loop;
end process;
-- HAMMER_PATTERN_MINUS: generate walking HAMMER data pattern except 1 bit for the whole burst. The incoming addr_i[5:2] determine
-- the position of the pin driving oppsite polarity
-- addr_i[6:2] = 5'h0f ; 32 bit data port
-- => the rsing data pattern will be 32'b11111111_11111111_01111111_11111111
-- => the falling data pattern will be 32'b00000000_00000000_00000000_00000000
-- ADDRESS_PATTERN: use the address as the 1st data pattern for the whole burst. For example
-- Dataport 32 bit width with starting addr_i = 30'h12345678, user burst length 4
-- => the 1st data pattern : 32'h12345678
-- => the 2nd data pattern : 32'h12345679
-- => the 3rd data pattern : 32'h1234567a
-- => the 4th data pattern : 32'h1234567b
--data_rdy_i
xhdl10 : if (DATA_PATTERN = "DGEN_ADDR" or DATA_PATTERN = "DGEN_ALL") generate
--data_o logic
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (cmd_startD = '1') then
adata <= addr_i;
elsif ((fifo_rdy_i and data_rdy_i) = '1' and user_burst_cnt > "0000001") then
if (DWIDTH = 128) then
adata <= adata + "00000000000000000000000000010000";
elsif (DWIDTH = 64) then
adata <= adata + "00000000000000000000000000001000"; -- DWIDTH == 32
else
adata <= adata + "00000000000000000000000000000100";
end if;
end if;
end if;
end process;
end generate;
-- PRBS_PATTERN: use the address as the PRBS seed data pattern for the whole burst. For example
-- Dataport 32 bit width with starting addr_i = 30'h12345678, user burst length 4
--
xhdl11 : if (DATA_PATTERN = "DGEN_PRBS" or DATA_PATTERN = "DGEN_ALL") generate
-- PRBS DATA GENERATION
-- xor all the tap positions before feedback to 1st stage.
-- data_clk_en <= fifo_rdy_i and data_rdy_i and to_stdlogicvector(user_burst_cnt > "0000001", 7)(0);
data_clk_en <= (fifo_rdy_i AND data_rdy_i) when (user_burst_cnt > "0000001") ELSE '0';
data_prbs_gen_inst : data_prbs_gen
generic map (
prbs_width => 32,
seed_width => 32
)
port map (
clk_i => clk_i,
clk_en => data_clk_en,
rst_i => rst_i,
prbs_fseed_i => prbs_fseed_i,
prbs_seed_init => cmd_startE,
prbs_seed_i => addr_i(31 downto 0),
prbs_o => prbs_data
);
end generate;
end architecture trans;
|
bsd-2-clause
|
mithro/HDMI2USB
|
ipcore_dir/ddr2ram/example_design/rtl/memc3_tb_top.vhd
|
6
|
29617
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.92
-- \ \ Application : MIG
-- / / Filename : memc3_tb_top.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:56 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
--Device : Spartan-6
--Design Name : DDR/DDR2/DDR3/LPDDR
--Purpose : This is top level module for test bench. which instantiates
-- init_mem_pattern_ctr and mcb_traffic_gen modules for each user
-- port.
--Reference :
--Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity memc3_tb_top is
generic
(
C_P0_MASK_SIZE : integer := 4;
C_P0_DATA_PORT_SIZE : integer := 32;
C_P1_MASK_SIZE : integer := 4;
C_P1_DATA_PORT_SIZE : integer := 32;
C_MEM_BURST_LEN : integer := 8;
C_SIMULATION : string := "FALSE";
C_MEM_NUM_COL_BITS : integer := 11;
C_NUM_DQ_PINS : integer := 8;
C_SMALL_DEVICE : string := "FALSE";
C_p2_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000100";
C_p2_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
C_p2_END_ADDRESS : std_logic_vector(31 downto 0) := X"000002ff";
C_p2_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"fffffc00";
C_p2_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00000100";
C_p3_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000500";
C_p3_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
C_p3_END_ADDRESS : std_logic_vector(31 downto 0) := X"000006ff";
C_p3_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"fffff800";
C_p3_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00000500"
);
port
(
clk0 : in std_logic;
rst0 : in std_logic;
calib_done : in std_logic;
p2_mcb_cmd_en_o : out std_logic;
p2_mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
p2_mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
p2_mcb_cmd_addr_o : out std_logic_vector(29 downto 0);
p2_mcb_cmd_full_i : in std_logic;
p2_mcb_rd_en_o : out std_logic;
p2_mcb_rd_data_i : in std_logic_vector(31 downto 0);
p2_mcb_rd_empty_i : in std_logic;
p2_mcb_rd_fifo_counts : in std_logic_vector(6 downto 0);
p3_mcb_cmd_en_o : out std_logic;
p3_mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
p3_mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
p3_mcb_cmd_addr_o : out std_logic_vector(29 downto 0);
p3_mcb_cmd_full_i : in std_logic;
p3_mcb_wr_en_o : out std_logic;
p3_mcb_wr_mask_o : out std_logic_vector(3 downto 0);
p3_mcb_wr_data_o : out std_logic_vector(31 downto 0);
p3_mcb_wr_full_i : in std_logic;
p3_mcb_wr_fifo_counts : in std_logic_vector(6 downto 0);
vio_modify_enable : in std_logic;
vio_data_mode_value : in std_logic_vector(2 downto 0);
vio_addr_mode_value : in std_logic_vector(2 downto 0);
cmp_error : out std_logic;
cmp_data : out std_logic_vector(31 downto 0);
cmp_data_valid : out std_logic;
error : out std_logic;
error_status : out std_logic_vector(127 downto 0)
);
end memc3_tb_top;
architecture arc of memc3_tb_top is
function ERROR_DQWIDTH (val_i : integer) return integer is
begin
if (val_i = 4) then
return 1;
else
return val_i/8;
end if;
end function ERROR_DQWIDTH;
constant DQ_ERROR_WIDTH : integer := ERROR_DQWIDTH(C_NUM_DQ_PINS);
component init_mem_pattern_ctr IS
generic (
FAMILY : string;
BEGIN_ADDRESS : std_logic_vector(31 downto 0);
END_ADDRESS : std_logic_vector(31 downto 0);
DWIDTH : integer;
CMD_SEED_VALUE : std_logic_vector(31 downto 0);
DATA_SEED_VALUE : std_logic_vector(31 downto 0);
DATA_MODE : std_logic_vector(3 downto 0);
PORT_MODE : string
);
PORT (
clk_i : in std_logic;
rst_i : in std_logic;
mcb_cmd_bl_i : in std_logic_vector(5 downto 0);
mcb_cmd_en_i : in std_logic;
mcb_cmd_instr_i : in std_logic_vector(2 downto 0);
mcb_init_done_i : in std_logic;
mcb_wr_en_i : in std_logic;
vio_modify_enable : in std_logic;
vio_data_mode_value : in std_logic_vector(2 downto 0);
vio_addr_mode_value : in std_logic_vector(2 downto 0);
vio_bl_mode_value : in STD_LOGIC_VECTOR(1 downto 0);
vio_fixed_bl_value : in STD_LOGIC_VECTOR(5 downto 0);
cmp_error : in std_logic;
run_traffic_o : out std_logic;
start_addr_o : out std_logic_vector(31 downto 0);
end_addr_o : out std_logic_vector(31 downto 0);
cmd_seed_o : out std_logic_vector(31 downto 0);
data_seed_o : out std_logic_vector(31 downto 0);
load_seed_o : out std_logic;
addr_mode_o : out std_logic_vector(2 downto 0);
instr_mode_o : out std_logic_vector(3 downto 0);
bl_mode_o : out std_logic_vector(1 downto 0);
data_mode_o : out std_logic_vector(3 downto 0);
mode_load_o : out std_logic;
fixed_bl_o : out std_logic_vector(5 downto 0);
fixed_instr_o : out std_logic_vector(2 downto 0);
fixed_addr_o : out std_logic_vector(31 downto 0)
);
end component;
component mcb_traffic_gen is
generic (
FAMILY : string;
SIMULATION : string;
MEM_BURST_LEN : integer;
PORT_MODE : string;
DATA_PATTERN : string;
CMD_PATTERN : string;
ADDR_WIDTH : integer;
CMP_DATA_PIPE_STAGES : integer;
MEM_COL_WIDTH : integer;
NUM_DQ_PINS : integer;
DQ_ERROR_WIDTH : integer;
DWIDTH : integer;
PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0);
PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0);
PRBS_EADDR : std_logic_vector(31 downto 0);
PRBS_SADDR : std_logic_vector(31 downto 0)
);
port (
clk_i : in std_logic;
rst_i : in std_logic;
run_traffic_i : in std_logic;
manual_clear_error : in std_logic;
-- *** runtime parameter ***
start_addr_i : in std_logic_vector(31 downto 0);
end_addr_i : in std_logic_vector(31 downto 0);
cmd_seed_i : in std_logic_vector(31 downto 0);
data_seed_i : in std_logic_vector(31 downto 0);
load_seed_i : in std_logic;
addr_mode_i : in std_logic_vector(2 downto 0);
instr_mode_i : in std_logic_vector(3 downto 0);
bl_mode_i : in std_logic_vector(1 downto 0);
data_mode_i : in std_logic_vector(3 downto 0);
mode_load_i : in std_logic;
-- fixed pattern inputs interface
fixed_bl_i : in std_logic_vector(5 downto 0);
fixed_instr_i : in std_logic_vector(2 downto 0);
fixed_addr_i : in std_logic_vector(31 downto 0);
fixed_data_i : IN STD_LOGIC_VECTOR(DWIDTH-1 DOWNTO 0);
bram_cmd_i : in std_logic_vector(38 downto 0);
bram_valid_i : in std_logic;
bram_rdy_o : out std_logic;
--///////////////////////////////////////////////////////////////////////////
-- MCB INTERFACE
-- interface to mcb command port
mcb_cmd_en_o : out std_logic;
mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
mcb_cmd_addr_o : out std_logic_vector(ADDR_WIDTH - 1 downto 0);
mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
mcb_cmd_full_i : in std_logic;
-- interface to mcb wr data port
mcb_wr_en_o : out std_logic;
mcb_wr_data_o : out std_logic_vector(DWIDTH - 1 downto 0);
mcb_wr_mask_o : out std_logic_vector((DWIDTH / 8) - 1 downto 0);
mcb_wr_data_end_o : OUT std_logic;
mcb_wr_full_i : in std_logic;
mcb_wr_fifo_counts : in std_logic_vector(6 downto 0);
-- interface to mcb rd data port
mcb_rd_en_o : out std_logic;
mcb_rd_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
mcb_rd_empty_i : in std_logic;
mcb_rd_fifo_counts : in std_logic_vector(6 downto 0);
--///////////////////////////////////////////////////////////////////////////
-- status feedback
counts_rst : in std_logic;
wr_data_counts : out std_logic_vector(47 downto 0);
rd_data_counts : out std_logic_vector(47 downto 0);
cmp_data : out std_logic_vector(DWIDTH - 1 downto 0);
cmp_data_valid : out std_logic;
cmp_error : out std_logic;
error : out std_logic;
error_status : out std_logic_vector(64 + (2 * DWIDTH - 1) downto 0);
mem_rd_data : out std_logic_vector(DWIDTH - 1 downto 0);
dq_error_bytelane_cmp : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0);
cumlative_dq_lane_error : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0)
);
end component;
-- Function to determine the number of data patterns to be generated
function DATA_PATTERN_CALC return string is
begin
if (C_SMALL_DEVICE = "FALSE") then
return "DGEN_ALL";
else
return "DGEN_ADDR";
end if;
end function;
constant FAMILY : string := "SPARTAN6";
constant DATA_PATTERN : string := DATA_PATTERN_CALC;
constant CMD_PATTERN : string := "CGEN_ALL";
constant ADDR_WIDTH : integer := 30;
constant CMP_DATA_PIPE_STAGES : integer := 0;
constant PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00007000";
constant PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"FFFF8000";
constant PRBS_SADDR : std_logic_vector(31 downto 0) := X"00005000";
constant PRBS_EADDR : std_logic_vector(31 downto 0) := X"00007fff";
constant BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000000";
constant END_ADDRESS : std_logic_vector(31 downto 0) := X"00000fff";
constant DATA_MODE : std_logic_vector(3 downto 0) := "0010";
constant p2_DWIDTH : integer := 32;
constant p3_DWIDTH : integer := 32;
constant p2_PORT_MODE : string := "RD_MODE";
constant p3_PORT_MODE : string := "WR_MODE";
signal p0_mcb_cmd_addr_o_int : std_logic_vector(ADDR_WIDTH - 1 DOWNTO 0);
signal p0_mcb_cmd_bl_o_int : std_logic_vector(5 DOWNTO 0);
signal p0_mcb_cmd_en_o_int : std_logic;
signal p0_mcb_cmd_instr_o_int : std_logic_vector(2 DOWNTO 0);
signal p0_mcb_wr_en_o_int : std_logic;
--p2 Signal declarations
signal p2_tg_run_traffic : std_logic;
signal p2_tg_start_addr : std_logic_vector(31 downto 0);
signal p2_tg_end_addr : std_logic_vector(31 downto 0);
signal p2_tg_cmd_seed : std_logic_vector(31 downto 0);
signal p2_tg_data_seed : std_logic_vector(31 downto 0);
signal p2_tg_load_seed : std_logic;
signal p2_tg_addr_mode : std_logic_vector(2 downto 0);
signal p2_tg_instr_mode : std_logic_vector(3 downto 0);
signal p2_tg_bl_mode : std_logic_vector(1 downto 0);
signal p2_tg_data_mode : std_logic_vector(3 downto 0);
signal p2_tg_mode_load : std_logic;
signal p2_tg_fixed_bl : std_logic_vector(5 downto 0);
signal p2_tg_fixed_instr : std_logic_vector(2 downto 0);
signal p2_tg_fixed_addr : std_logic_vector(31 downto 0);
signal p2_error_status : std_logic_vector(64 + (2*p2_DWIDTH - 1) downto 0);
signal p2_error : std_logic;
signal p2_cmp_error : std_logic;
signal p2_cmp_data : std_logic_vector(p2_DWIDTH-1 downto 0);
signal p2_cmp_data_valid : std_logic;
signal p2_mcb_cmd_en_o_int : std_logic;
signal p2_mcb_cmd_instr_o_int : std_logic_vector(2 downto 0);
signal p2_mcb_cmd_bl_o_int : std_logic_vector(5 downto 0);
signal p2_mcb_cmd_addr_o_int : std_logic_vector(29 downto 0);
signal p2_mcb_wr_en_o_int : std_logic;
--p3 Signal declarations
signal p3_tg_run_traffic : std_logic;
signal p3_tg_start_addr : std_logic_vector(31 downto 0);
signal p3_tg_end_addr : std_logic_vector(31 downto 0);
signal p3_tg_cmd_seed : std_logic_vector(31 downto 0);
signal p3_tg_data_seed : std_logic_vector(31 downto 0);
signal p3_tg_load_seed : std_logic;
signal p3_tg_addr_mode : std_logic_vector(2 downto 0);
signal p3_tg_instr_mode : std_logic_vector(3 downto 0);
signal p3_tg_bl_mode : std_logic_vector(1 downto 0);
signal p3_tg_data_mode : std_logic_vector(3 downto 0);
signal p3_tg_mode_load : std_logic;
signal p3_tg_fixed_bl : std_logic_vector(5 downto 0);
signal p3_tg_fixed_instr : std_logic_vector(2 downto 0);
signal p3_tg_fixed_addr : std_logic_vector(31 downto 0);
signal p3_error_status : std_logic_vector(64 + (2*p3_DWIDTH - 1) downto 0);
signal p3_error : std_logic;
signal p3_cmp_error : std_logic;
signal p3_cmp_data : std_logic_vector(p3_DWIDTH-1 downto 0);
signal p3_cmp_data_valid : std_logic;
signal p3_mcb_cmd_en_o_int : std_logic;
signal p3_mcb_cmd_instr_o_int : std_logic_vector(2 downto 0);
signal p3_mcb_cmd_bl_o_int : std_logic_vector(5 downto 0);
signal p3_mcb_cmd_addr_o_int : std_logic_vector(29 downto 0);
signal p3_mcb_wr_en_o_int : std_logic;
signal p2_mcb_wr_en_o : std_logic;
signal p2_mcb_wr_full_i : std_logic;
signal p2_mcb_wr_data_o : std_logic_vector(31 downto 0);
signal p2_mcb_wr_mask_o : std_logic_vector(3 downto 0);
signal p2_mcb_wr_fifo_counts : std_logic_vector(6 downto 0);
signal p3_mcb_rd_en_o : std_logic;
signal p3_mcb_rd_empty_i : std_logic;
signal p3_mcb_rd_fifo_counts : std_logic_vector(6 downto 0);
signal p3_mcb_rd_data_i : std_logic_vector(31 downto 0);
--signal cmp_data : std_logic_vector(31 downto 0);
begin
cmp_error <= p2_cmp_error or p3_cmp_error;
error <= p2_error or p3_error;
error_status <= p2_error_status;
cmp_data <= p2_cmp_data(31 downto 0);
cmp_data_valid <= p2_cmp_data_valid;
p2_mcb_cmd_en_o <= p2_mcb_cmd_en_o_int;
p2_mcb_cmd_instr_o <= p2_mcb_cmd_instr_o_int;
p2_mcb_cmd_bl_o <= p2_mcb_cmd_bl_o_int;
p2_mcb_cmd_addr_o <= p2_mcb_cmd_addr_o_int;
p2_mcb_wr_en_o <= p2_mcb_wr_en_o_int;
init_mem_pattern_ctr_p2 :init_mem_pattern_ctr
generic map
(
DWIDTH => p2_DWIDTH,
FAMILY => FAMILY,
BEGIN_ADDRESS => C_p3_BEGIN_ADDRESS,
END_ADDRESS => C_p3_END_ADDRESS,
CMD_SEED_VALUE => X"56456783",
DATA_SEED_VALUE => X"12345678",
DATA_MODE => C_p3_DATA_MODE,
PORT_MODE => p2_PORT_MODE
)
port map
(
clk_i => clk0,
rst_i => rst0,
mcb_cmd_en_i => p3_mcb_cmd_en_o_int,
mcb_cmd_instr_i => p3_mcb_cmd_instr_o_int,
mcb_cmd_bl_i => p3_mcb_cmd_bl_o_int,
mcb_wr_en_i => p3_mcb_wr_en_o_int,
vio_modify_enable => vio_modify_enable,
vio_data_mode_value => vio_data_mode_value,
vio_addr_mode_value => vio_addr_mode_value,
vio_bl_mode_value => "10",--vio_bl_mode_value,
vio_fixed_bl_value => "000000",--vio_fixed_bl_value,
mcb_init_done_i => calib_done,
cmp_error => p2_error,
run_traffic_o => p2_tg_run_traffic,
start_addr_o => p2_tg_start_addr,
end_addr_o => p2_tg_end_addr ,
cmd_seed_o => p2_tg_cmd_seed ,
data_seed_o => p2_tg_data_seed ,
load_seed_o => p2_tg_load_seed ,
addr_mode_o => p2_tg_addr_mode ,
instr_mode_o => p2_tg_instr_mode ,
bl_mode_o => p2_tg_bl_mode ,
data_mode_o => p2_tg_data_mode ,
mode_load_o => p2_tg_mode_load ,
fixed_bl_o => p2_tg_fixed_bl ,
fixed_instr_o => p2_tg_fixed_instr,
fixed_addr_o => p2_tg_fixed_addr
);
m_traffic_gen_p2 : mcb_traffic_gen
generic map(
MEM_BURST_LEN => C_MEM_BURST_LEN,
MEM_COL_WIDTH => C_MEM_NUM_COL_BITS,
NUM_DQ_PINS => C_NUM_DQ_PINS,
DQ_ERROR_WIDTH => DQ_ERROR_WIDTH,
PORT_MODE => p2_PORT_MODE,
DWIDTH => p2_DWIDTH,
CMP_DATA_PIPE_STAGES => CMP_DATA_PIPE_STAGES,
FAMILY => FAMILY,
SIMULATION => "FALSE",
DATA_PATTERN => DATA_PATTERN,
CMD_PATTERN => "CGEN_ALL",
ADDR_WIDTH => 30,
PRBS_SADDR_MASK_POS => C_p3_PRBS_SADDR_MASK_POS,
PRBS_EADDR_MASK_POS => C_p3_PRBS_EADDR_MASK_POS,
PRBS_SADDR => C_p3_BEGIN_ADDRESS,
PRBS_EADDR => C_p3_END_ADDRESS
)
port map
(
clk_i => clk0,
rst_i => rst0,
run_traffic_i => p2_tg_run_traffic,
manual_clear_error => rst0,
-- runtime parameter
start_addr_i => p2_tg_start_addr ,
end_addr_i => p2_tg_end_addr ,
cmd_seed_i => p2_tg_cmd_seed ,
data_seed_i => p2_tg_data_seed ,
load_seed_i => p2_tg_load_seed,
addr_mode_i => p2_tg_addr_mode,
instr_mode_i => p2_tg_instr_mode ,
bl_mode_i => p2_tg_bl_mode ,
data_mode_i => p2_tg_data_mode ,
mode_load_i => p2_tg_mode_load ,
-- fixed pattern inputs interface
fixed_bl_i => p2_tg_fixed_bl,
fixed_instr_i => p2_tg_fixed_instr,
fixed_addr_i => p2_tg_fixed_addr,
fixed_data_i => (others => '0'),
-- BRAM interface.
bram_cmd_i => (others => '0'),
bram_valid_i => '0',
bram_rdy_o => open,
-- MCB INTERFACE
mcb_cmd_en_o => p2_mcb_cmd_en_o_int,
mcb_cmd_instr_o => p2_mcb_cmd_instr_o_int,
mcb_cmd_bl_o => p2_mcb_cmd_bl_o_int,
mcb_cmd_addr_o => p2_mcb_cmd_addr_o_int,
mcb_cmd_full_i => p2_mcb_cmd_full_i,
mcb_wr_en_o => p2_mcb_wr_en_o_int,
mcb_wr_mask_o => p2_mcb_wr_mask_o,
mcb_wr_data_o => p2_mcb_wr_data_o,
mcb_wr_data_end_o => open,
mcb_wr_full_i => p2_mcb_wr_full_i,
mcb_wr_fifo_counts => p2_mcb_wr_fifo_counts,
mcb_rd_en_o => p2_mcb_rd_en_o,
mcb_rd_data_i => p2_mcb_rd_data_i,
mcb_rd_empty_i => p2_mcb_rd_empty_i,
mcb_rd_fifo_counts => p2_mcb_rd_fifo_counts,
-- status feedback
counts_rst => rst0,
wr_data_counts => open,
rd_data_counts => open,
cmp_data => p2_cmp_data,
cmp_data_valid => p2_cmp_data_valid,
cmp_error => p2_cmp_error,
error => p2_error,
error_status => p2_error_status,
mem_rd_data => open,
dq_error_bytelane_cmp => open,
cumlative_dq_lane_error => open
);
p3_mcb_cmd_en_o <= p3_mcb_cmd_en_o_int;
p3_mcb_cmd_instr_o <= p3_mcb_cmd_instr_o_int;
p3_mcb_cmd_bl_o <= p3_mcb_cmd_bl_o_int;
p3_mcb_cmd_addr_o <= p3_mcb_cmd_addr_o_int;
p3_mcb_wr_en_o <= p3_mcb_wr_en_o_int;
init_mem_pattern_ctr_p3 :init_mem_pattern_ctr
generic map
(
DWIDTH => p3_DWIDTH,
FAMILY => FAMILY,
BEGIN_ADDRESS => C_p3_BEGIN_ADDRESS,
END_ADDRESS => C_p3_END_ADDRESS,
CMD_SEED_VALUE => X"56456783",
DATA_SEED_VALUE => X"12345678",
DATA_MODE => C_p3_DATA_MODE,
PORT_MODE => p3_PORT_MODE
)
port map
(
clk_i => clk0,
rst_i => rst0,
mcb_cmd_en_i => p3_mcb_cmd_en_o_int,
mcb_cmd_instr_i => p3_mcb_cmd_instr_o_int,
mcb_cmd_bl_i => p3_mcb_cmd_bl_o_int,
mcb_wr_en_i => p3_mcb_wr_en_o_int,
vio_modify_enable => vio_modify_enable,
vio_data_mode_value => vio_data_mode_value,
vio_addr_mode_value => vio_addr_mode_value,
vio_bl_mode_value => "10",--vio_bl_mode_value,
vio_fixed_bl_value => "000000",--vio_fixed_bl_value,
mcb_init_done_i => calib_done,
cmp_error => p3_error,
run_traffic_o => p3_tg_run_traffic,
start_addr_o => p3_tg_start_addr,
end_addr_o => p3_tg_end_addr ,
cmd_seed_o => p3_tg_cmd_seed ,
data_seed_o => p3_tg_data_seed ,
load_seed_o => p3_tg_load_seed ,
addr_mode_o => p3_tg_addr_mode ,
instr_mode_o => p3_tg_instr_mode ,
bl_mode_o => p3_tg_bl_mode ,
data_mode_o => p3_tg_data_mode ,
mode_load_o => p3_tg_mode_load ,
fixed_bl_o => p3_tg_fixed_bl ,
fixed_instr_o => p3_tg_fixed_instr,
fixed_addr_o => p3_tg_fixed_addr
);
m_traffic_gen_p3 : mcb_traffic_gen
generic map(
MEM_BURST_LEN => C_MEM_BURST_LEN,
MEM_COL_WIDTH => C_MEM_NUM_COL_BITS,
NUM_DQ_PINS => C_NUM_DQ_PINS,
DQ_ERROR_WIDTH => DQ_ERROR_WIDTH,
PORT_MODE => p3_PORT_MODE,
DWIDTH => p3_DWIDTH,
CMP_DATA_PIPE_STAGES => CMP_DATA_PIPE_STAGES,
FAMILY => FAMILY,
SIMULATION => "FALSE",
DATA_PATTERN => DATA_PATTERN,
CMD_PATTERN => "CGEN_ALL",
ADDR_WIDTH => 30,
PRBS_SADDR_MASK_POS => C_p3_PRBS_SADDR_MASK_POS,
PRBS_EADDR_MASK_POS => C_p3_PRBS_EADDR_MASK_POS,
PRBS_SADDR => C_p3_BEGIN_ADDRESS,
PRBS_EADDR => C_p3_END_ADDRESS
)
port map
(
clk_i => clk0,
rst_i => rst0,
run_traffic_i => p3_tg_run_traffic,
manual_clear_error => rst0,
-- runtime parameter
start_addr_i => p3_tg_start_addr ,
end_addr_i => p3_tg_end_addr ,
cmd_seed_i => p3_tg_cmd_seed ,
data_seed_i => p3_tg_data_seed ,
load_seed_i => p3_tg_load_seed,
addr_mode_i => p3_tg_addr_mode,
instr_mode_i => p3_tg_instr_mode ,
bl_mode_i => p3_tg_bl_mode ,
data_mode_i => p3_tg_data_mode ,
mode_load_i => p3_tg_mode_load ,
-- fixed pattern inputs interface
fixed_bl_i => p3_tg_fixed_bl,
fixed_instr_i => p3_tg_fixed_instr,
fixed_addr_i => p3_tg_fixed_addr,
fixed_data_i => (others => '0'),
-- BRAM interface.
bram_cmd_i => (others => '0'),
bram_valid_i => '0',
bram_rdy_o => open,
-- MCB INTERFACE
mcb_cmd_en_o => p3_mcb_cmd_en_o_int,
mcb_cmd_instr_o => p3_mcb_cmd_instr_o_int,
mcb_cmd_bl_o => p3_mcb_cmd_bl_o_int,
mcb_cmd_addr_o => p3_mcb_cmd_addr_o_int,
mcb_cmd_full_i => p3_mcb_cmd_full_i,
mcb_wr_en_o => p3_mcb_wr_en_o_int,
mcb_wr_mask_o => p3_mcb_wr_mask_o,
mcb_wr_data_o => p3_mcb_wr_data_o,
mcb_wr_data_end_o => open,
mcb_wr_full_i => p3_mcb_wr_full_i,
mcb_wr_fifo_counts => p3_mcb_wr_fifo_counts,
mcb_rd_en_o => p3_mcb_rd_en_o,
mcb_rd_data_i => p3_mcb_rd_data_i,
mcb_rd_empty_i => p3_mcb_rd_empty_i,
mcb_rd_fifo_counts => p3_mcb_rd_fifo_counts,
-- status feedback
counts_rst => rst0,
wr_data_counts => open,
rd_data_counts => open,
cmp_data => p3_cmp_data,
cmp_data_valid => p3_cmp_data_valid,
cmp_error => p3_cmp_error,
error => p3_error,
error_status => p3_error_status,
mem_rd_data => open,
dq_error_bytelane_cmp => open,
cumlative_dq_lane_error => open
);
end architecture;
|
bsd-2-clause
|
mithro/HDMI2USB
|
ipcore_dir/ddr2ram/example_design/rtl/mcb_soft_calibration_top.vhd
|
19
|
21926
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: mcb_soft_calibration_top.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:17:26 $
-- \ \ / \ Date Created: Mon Feb 9 2009
-- \___\/\___\
--
--Device: Spartan6
--Design Name: DDR/DDR2/DDR3/LPDDR
--Purpose: Xilinx reference design top-level simulation
-- wrapper file for input termination calibration
--Reference:
--
-- Revision: Date: Comment
-- 1.0: 2/06/09: Initial version for MIG wrapper.
-- 1.1: 3/16/09: Added pll_lock port, for using it to gate reset
-- 1.2: 6/06/09: Removed MCB_UIDQCOUNT.
-- 1.3: 6/18/09: corrected/changed MCB_SYSRST to be an output port
-- 1.4: 6/24/09: gave RZQ and ZIO each their own unique ADD and SDI nets
-- 1.5: 10/08/09: removed INCDEC_TRESHOLD parameter - making it a localparam inside mcb_soft_calibration
-- 1.5: 10/08/09: removed INCDEC_TRESHOLD parameter - making it a localparam inside mcb_soft_calibration
-- 1.6: 02/04/09: Added condition generate statmenet for ZIO pin.
-- 1.7: 04/12/10: Added CKE_Train signal to fix DDR2 init wait .
-- End Revision
--**********************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
entity mcb_soft_calibration_top is
generic (
C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000"; -- DDR3 Minimum delay between resets
C_MC_CALIBRATION_MODE : string := "CALIBRATION"; -- if set to CALIBRATION will reset DQS IDELAY to DQS_NUMERATOR/DQS_DENOMINATOR local_param values,
-- and does dynamic recal,
-- if set to NOCALIBRATION then defaults to hard cal blocks setting of C_MC_CALBRATION_DELAY *and*
-- no dynamic recal will be done
SKIP_IN_TERM_CAL : integer := 0; -- provides option to skip the input termination calibration
SKIP_DYNAMIC_CAL : integer := 0; -- provides option to skip the dynamic delay calibration
SKIP_DYN_IN_TERM : integer := 0; -- provides option to skip the dynamic delay calibration
C_SIMULATION : string := "FALSE"; -- Tells us whether the design is being simulated or implemented
C_MEM_TYPE : string := "DDR" -- provides the memory device used for the design
);
port (
UI_CLK : in std_logic; -- Input - global clock to be used for input_term_tuner and IODRP clock
RST : in std_logic; -- Input - reset for input_term_tuner - synchronous for input_term_tuner state machine, asynch for
-- IODRP (sub)controller
IOCLK : in std_logic; -- Input - IOCLK input to the IODRP's
DONE_SOFTANDHARD_CAL : out std_logic; -- active high flag signals soft calibration of input delays is complete and MCB_UODONECAL is high
-- (MCB hard calib complete)
PLL_LOCK : in std_logic; -- Lock signal from PLL
SELFREFRESH_REQ : in std_logic;
SELFREFRESH_MCB_MODE : in std_logic;
SELFREFRESH_MCB_REQ : out std_logic;
SELFREFRESH_MODE : out std_logic;
MCB_UIADD : out std_logic; -- to MCB's UIADD port
MCB_UISDI : out std_logic; -- to MCB's UISDI port
MCB_UOSDO : in std_logic;
MCB_UODONECAL : in std_logic;
MCB_UOREFRSHFLAG : in std_logic;
MCB_UICS : out std_logic;
MCB_UIDRPUPDATE : out std_logic;
MCB_UIBROADCAST : out std_logic;
MCB_UIADDR : out std_logic_vector(4 downto 0);
MCB_UICMDEN : out std_logic;
MCB_UIDONECAL : out std_logic;
MCB_UIDQLOWERDEC : out std_logic;
MCB_UIDQLOWERINC : out std_logic;
MCB_UIDQUPPERDEC : out std_logic;
MCB_UIDQUPPERINC : out std_logic;
MCB_UILDQSDEC : out std_logic;
MCB_UILDQSINC : out std_logic;
MCB_UIREAD : out std_logic;
MCB_UIUDQSDEC : out std_logic;
MCB_UIUDQSINC : out std_logic;
MCB_RECAL : out std_logic;
MCB_SYSRST : out std_logic;
MCB_UICMD : out std_logic;
MCB_UICMDIN : out std_logic;
MCB_UIDQCOUNT : out std_logic_vector(3 downto 0);
MCB_UODATA : in std_logic_vector(7 downto 0);
MCB_UODATAVALID : in std_logic;
MCB_UOCMDREADY : in std_logic;
MCB_UO_CAL_START : in std_logic;
RZQ_PIN : inout std_logic;
ZIO_PIN : inout std_logic;
CKE_Train : out std_logic
);
end entity mcb_soft_calibration_top;
architecture trans of mcb_soft_calibration_top is
component mcb_soft_calibration is
generic (
C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000"; -- DDR3 Minimum delay between resets
SKIP_IN_TERM_CAL : integer := 0; -- provides option to skip the input termination calibration
SKIP_DYNAMIC_CAL : integer := 0; -- provides option to skip the dynamic delay calibration
SKIP_DYN_IN_TERM : integer := 1; -- provides option to skip the input termination calibration
C_MC_CALIBRATION_MODE : string := "CALIBRATION"; -- if set to CALIBRATION will reset DQS IDELAY to DQS_NUMERATOR/DQS_DENOMINATOR local_param value
-- if set to NOCALIBRATION then defaults to hard cal blocks setting of C_MC_CALBRATION_DELAY
-- (Quarter, etc)
C_SIMULATION : string := "FALSE"; -- Tells us whether the design is being simulated or implemented
C_MEM_TYPE : string := "DDR"
);
port (
UI_CLK : in std_logic; -- main clock input for logic and IODRP CLK pins. At top level, this should also connect to IODRP2_MCB
-- CLK pins
RST : in std_logic; -- main system reset for both the Soft Calibration block - also will act as a passthrough to MCB's SYSRST
DONE_SOFTANDHARD_CAL : out std_logic; -- active high flag signals soft calibration of input delays is complete and MCB_UODONECAL is high (MCB
-- hard calib complete)
PLL_LOCK : in std_logic; -- Lock signal from PLL
SELFREFRESH_REQ : in std_logic;
SELFREFRESH_MCB_MODE : in std_logic;
SELFREFRESH_MCB_REQ : out std_logic;
SELFREFRESH_MODE : out std_logic;
IODRP_ADD : out std_logic; -- IODRP ADD port
IODRP_SDI : out std_logic; -- IODRP SDI port
RZQ_IN : in std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
RZQ_IODRP_SDO : in std_logic; -- RZQ IODRP's SDO port
RZQ_IODRP_CS : out std_logic := '0'; -- RZQ IODRP's CS port
ZIO_IN : in std_logic; -- Z-stated IO pin - garanteed not to be driven externally
ZIO_IODRP_SDO : in std_logic; -- ZIO IODRP's SDO port
ZIO_IODRP_CS : out std_logic := '0'; -- ZIO IODRP's CS port
MCB_UIADD : out std_logic; -- to MCB's UIADD port
MCB_UISDI : out std_logic; -- to MCB's UISDI port
MCB_UOSDO : in std_logic; -- from MCB's UOSDO port (User output SDO)
MCB_UODONECAL : in std_logic; -- indicates when MCB hard calibration process is complete
MCB_UOREFRSHFLAG : in std_logic; -- high during refresh cycle and time when MCB is innactive
MCB_UICS : out std_logic; -- to MCB's UICS port (User Input CS)
MCB_UIDRPUPDATE : out std_logic := '1'; -- MCB's UIDRPUPDATE port (gets passed to IODRP2_MCB's MEMUPDATE port: this controls shadow latch used
-- during IODRP2_MCB writes). Currently just trasnparent
MCB_UIBROADCAST : out std_logic; -- only to MCB's UIBROADCAST port (User Input BROADCAST - gets passed to IODRP2_MCB's BKST port)
MCB_UIADDR : out std_logic_vector(4 downto 0) := "00000"; -- to MCB's UIADDR port (gets passed to IODRP2_MCB's AUXADDR port
MCB_UICMDEN : out std_logic := '1'; -- set to 1 to take control of UI interface - removes control from internal calib block
MCB_UIDONECAL : out std_logic := '0'; -- set to 0 to "tell" controller that it's still in a calibrate state
MCB_UIDQLOWERDEC : out std_logic := '0';
MCB_UIDQLOWERINC : out std_logic := '0';
MCB_UIDQUPPERDEC : out std_logic := '0';
MCB_UIDQUPPERINC : out std_logic := '0';
MCB_UILDQSDEC : out std_logic := '0';
MCB_UILDQSINC : out std_logic := '0';
MCB_UIREAD : out std_logic; -- enables read w/o writing by turning on a SDO->SDI loopback inside the IODRP2_MCBs (doesn't exist in
-- regular IODRP2). IODRPCTRLR_R_WB becomes don't-care.
MCB_UIUDQSDEC : out std_logic := '0';
MCB_UIUDQSINC : out std_logic := '0';
MCB_RECAL : out std_logic := '0'; -- future hook to drive MCB's RECAL pin - initiates a hard re-calibration sequence when high
MCB_UICMD : out std_logic;
MCB_UICMDIN : out std_logic;
MCB_UIDQCOUNT : out std_logic_vector(3 downto 0);
MCB_UODATA : in std_logic_vector(7 downto 0);
MCB_UODATAVALID : in std_logic;
MCB_UOCMDREADY : in std_logic;
MCB_UO_CAL_START : in std_logic;
MCB_SYSRST : out std_logic; -- drives the MCB's SYSRST pin - the main reset for MCB
Max_Value : out std_logic_vector(7 downto 0);
CKE_Train : out std_logic
);
end component;
signal IODRP_ADD : std_logic;
signal IODRP_SDI : std_logic;
signal RZQ_IODRP_SDO : std_logic;
signal RZQ_IODRP_CS : std_logic;
signal ZIO_IODRP_SDO : std_logic;
signal ZIO_IODRP_CS : std_logic;
signal IODRP_SDO : std_logic;
signal IODRP_CS : std_logic;
signal IODRP_BKST : std_logic;
signal RZQ_ZIO_ODATAIN : std_logic;
signal RZQ_ZIO_TRISTATE : std_logic;
signal RZQ_TOUT : std_logic;
signal ZIO_TOUT : std_logic;
signal Max_Value : std_logic_vector(7 downto 0);
signal RZQ_IN : std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
signal RZQ_IN_R1 : std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
signal RZQ_IN_R2 : std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
signal ZIO_IN : std_logic; -- Z-stated IO pin - garanteed not to be driven externally
signal ZIO_IN_R1 : std_logic; -- Z-stated IO pin - garanteed not to be driven externally
signal ZIO_IN_R2 : std_logic; -- Z-stated IO pin - garanteed not to be driven externally
signal RZQ_OUT : std_logic;
signal ZIO_OUT : std_logic;
-- Declare intermediate signals for referenced outputs
signal DONE_SOFTANDHARD_CAL_xilinx0 : std_logic;
signal MCB_UIADD_xilinx3 : std_logic;
signal MCB_UISDI_xilinx17 : std_logic;
signal MCB_UICS_xilinx7 : std_logic;
signal MCB_UIDRPUPDATE_xilinx13 : std_logic;
signal MCB_UIBROADCAST_xilinx5 : std_logic;
signal MCB_UIADDR_xilinx4 : std_logic_vector(4 downto 0);
signal MCB_UICMDEN_xilinx6 : std_logic;
signal MCB_UIDONECAL_xilinx8 : std_logic;
signal MCB_UIDQLOWERDEC_xilinx9 : std_logic;
signal MCB_UIDQLOWERINC_xilinx10 : std_logic;
signal MCB_UIDQUPPERDEC_xilinx11 : std_logic;
signal MCB_UIDQUPPERINC_xilinx12 : std_logic;
signal MCB_UILDQSDEC_xilinx14 : std_logic;
signal MCB_UILDQSINC_xilinx15 : std_logic;
signal MCB_UIREAD_xilinx16 : std_logic;
signal MCB_UIUDQSDEC_xilinx18 : std_logic;
signal MCB_UIUDQSINC_xilinx19 : std_logic;
signal MCB_RECAL_xilinx1 : std_logic;
signal MCB_SYSRST_xilinx2 : std_logic;
begin
-- Drive referenced outputs
DONE_SOFTANDHARD_CAL <= DONE_SOFTANDHARD_CAL_xilinx0;
MCB_UIADD <= MCB_UIADD_xilinx3;
MCB_UISDI <= MCB_UISDI_xilinx17;
MCB_UICS <= MCB_UICS_xilinx7;
MCB_UIDRPUPDATE <= MCB_UIDRPUPDATE_xilinx13;
MCB_UIBROADCAST <= MCB_UIBROADCAST_xilinx5;
MCB_UIADDR <= MCB_UIADDR_xilinx4;
MCB_UICMDEN <= MCB_UICMDEN_xilinx6;
MCB_UIDONECAL <= MCB_UIDONECAL_xilinx8;
MCB_UIDQLOWERDEC <= MCB_UIDQLOWERDEC_xilinx9;
MCB_UIDQLOWERINC <= MCB_UIDQLOWERINC_xilinx10;
MCB_UIDQUPPERDEC <= MCB_UIDQUPPERDEC_xilinx11;
MCB_UIDQUPPERINC <= MCB_UIDQUPPERINC_xilinx12;
MCB_UILDQSDEC <= MCB_UILDQSDEC_xilinx14;
MCB_UILDQSINC <= MCB_UILDQSINC_xilinx15;
MCB_UIREAD <= MCB_UIREAD_xilinx16;
MCB_UIUDQSDEC <= MCB_UIUDQSDEC_xilinx18;
MCB_UIUDQSINC <= MCB_UIUDQSINC_xilinx19;
MCB_RECAL <= MCB_RECAL_xilinx1;
MCB_SYSRST <= MCB_SYSRST_xilinx2;
RZQ_ZIO_ODATAIN <= not(RST);
RZQ_ZIO_TRISTATE <= not(RST);
IODRP_BKST <= '0'; -- future hook for possible BKST to ZIO and RZQ
mcb_soft_calibration_inst : mcb_soft_calibration
generic map (
C_MEM_TZQINIT_MAXCNT => C_MEM_TZQINIT_MAXCNT,
C_MC_CALIBRATION_MODE => C_MC_CALIBRATION_MODE,
SKIP_IN_TERM_CAL => SKIP_IN_TERM_CAL,
SKIP_DYNAMIC_CAL => SKIP_DYNAMIC_CAL,
SKIP_DYN_IN_TERM => SKIP_DYN_IN_TERM,
C_SIMULATION => C_SIMULATION,
C_MEM_TYPE => C_MEM_TYPE
)
port map (
UI_CLK => UI_CLK,
RST => RST,
PLL_LOCK => PLL_LOCK,
SELFREFRESH_REQ => SELFREFRESH_REQ,
SELFREFRESH_MCB_MODE => SELFREFRESH_MCB_MODE,
SELFREFRESH_MCB_REQ => SELFREFRESH_MCB_REQ,
SELFREFRESH_MODE => SELFREFRESH_MODE,
DONE_SOFTANDHARD_CAL => DONE_SOFTANDHARD_CAL_xilinx0,
IODRP_ADD => IODRP_ADD,
IODRP_SDI => IODRP_SDI,
RZQ_IN => RZQ_IN_R2,
RZQ_IODRP_SDO => RZQ_IODRP_SDO,
RZQ_IODRP_CS => RZQ_IODRP_CS,
ZIO_IN => ZIO_IN_R2,
ZIO_IODRP_SDO => ZIO_IODRP_SDO,
ZIO_IODRP_CS => ZIO_IODRP_CS,
MCB_UIADD => MCB_UIADD_xilinx3,
MCB_UISDI => MCB_UISDI_xilinx17,
MCB_UOSDO => MCB_UOSDO,
MCB_UODONECAL => MCB_UODONECAL,
MCB_UOREFRSHFLAG => MCB_UOREFRSHFLAG,
MCB_UICS => MCB_UICS_xilinx7,
MCB_UIDRPUPDATE => MCB_UIDRPUPDATE_xilinx13,
MCB_UIBROADCAST => MCB_UIBROADCAST_xilinx5,
MCB_UIADDR => MCB_UIADDR_xilinx4,
MCB_UICMDEN => MCB_UICMDEN_xilinx6,
MCB_UIDONECAL => MCB_UIDONECAL_xilinx8,
MCB_UIDQLOWERDEC => MCB_UIDQLOWERDEC_xilinx9,
MCB_UIDQLOWERINC => MCB_UIDQLOWERINC_xilinx10,
MCB_UIDQUPPERDEC => MCB_UIDQUPPERDEC_xilinx11,
MCB_UIDQUPPERINC => MCB_UIDQUPPERINC_xilinx12,
MCB_UILDQSDEC => MCB_UILDQSDEC_xilinx14,
MCB_UILDQSINC => MCB_UILDQSINC_xilinx15,
MCB_UIREAD => MCB_UIREAD_xilinx16,
MCB_UIUDQSDEC => MCB_UIUDQSDEC_xilinx18,
MCB_UIUDQSINC => MCB_UIUDQSINC_xilinx19,
MCB_RECAL => MCB_RECAL_xilinx1,
MCB_UICMD => MCB_UICMD,
MCB_UICMDIN => MCB_UICMDIN,
MCB_UIDQCOUNT => MCB_UIDQCOUNT,
MCB_UODATA => MCB_UODATA,
MCB_UODATAVALID => MCB_UODATAVALID,
MCB_UOCMDREADY => MCB_UOCMDREADY,
MCB_UO_CAL_START => MCB_UO_CAL_START,
mcb_sysrst => MCB_SYSRST_xilinx2,
Max_Value => Max_Value,
CKE_Train => CKE_Train
);
process(UI_CLK,RST)
begin
if (RST = '1') then
ZIO_IN_R1 <= '0';
ZIO_IN_R2 <= '0';
RZQ_IN_R1 <= '0';
RZQ_IN_R2 <= '0';
elsif (UI_CLK'event and UI_CLK = '1') then
ZIO_IN_R1 <= ZIO_IN;
ZIO_IN_R2 <= ZIO_IN_R1;
RZQ_IN_R1 <= RZQ_IN;
RZQ_IN_R2 <= RZQ_IN_R1;
end if;
end process;
IOBUF_RZQ : IOBUF
port map (
o => RZQ_IN,
io => RZQ_PIN,
i => RZQ_OUT,
t => RZQ_TOUT
);
IODRP2_RZQ : IODRP2
port map (
dataout => open,
dataout2 => open,
dout => RZQ_OUT,
sdo => RZQ_IODRP_SDO,
tout => RZQ_TOUT,
add => IODRP_ADD,
bkst => IODRP_BKST,
clk => UI_CLK,
cs => RZQ_IODRP_CS,
idatain => RZQ_IN,
ioclk0 => IOCLK,
ioclk1 => '1',
odatain => RZQ_ZIO_ODATAIN,
sdi => IODRP_SDI,
t => RZQ_ZIO_TRISTATE
);
gen_zio: if ( ((C_MEM_TYPE = "DDR") or (C_MEM_TYPE = "DDR2") or (C_MEM_TYPE = "DDR3")) and
(SKIP_IN_TERM_CAL = 0)) generate
IOBUF_ZIO : IOBUF
port map (
o => ZIO_IN,
io => ZIO_PIN,
i => ZIO_OUT,
t => ZIO_TOUT
);
IODRP2_ZIO : IODRP2
port map (
dataout => open,
dataout2 => open,
dout => ZIO_OUT,
sdo => ZIO_IODRP_SDO,
tout => ZIO_TOUT,
add => IODRP_ADD,
bkst => IODRP_BKST,
clk => UI_CLK,
cs => ZIO_IODRP_CS,
idatain => ZIO_IN,
ioclk0 => IOCLK,
ioclk1 => '1',
odatain => RZQ_ZIO_ODATAIN,
sdi => IODRP_SDI,
t => RZQ_ZIO_TRISTATE
);
end generate;
end architecture trans;
|
bsd-2-clause
|
mithro/HDMI2USB
|
ipcore_dir/ddr2ram/example_design/rtl/traffic_gen/data_prbs_gen.vhd
|
20
|
4942
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: data_prbs_gen.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:16:39 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This module is used LFSR to generate random data for memory
-- data write or memory data read comparison.The first data is
-- seeded by the input prbs_seed_i which is connected to memory address.
-- Reference:
-- Revision History:
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY data_prbs_gen IS
GENERIC (
EYE_TEST : STRING := "FALSE";
PRBS_WIDTH : INTEGER := 32;
SEED_WIDTH : INTEGER := 32
-- TAPS : STD_LOGIC_VECTOR(PRBS_WIDTH - 1 DOWNTO 0) := "10000000001000000000000001100010"
);
PORT (
clk_i : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
rst_i : IN STD_LOGIC;
prbs_fseed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
prbs_seed_init : IN STD_LOGIC;
prbs_seed_i : IN STD_LOGIC_VECTOR(PRBS_WIDTH - 1 DOWNTO 0);
prbs_o : OUT STD_LOGIC_VECTOR(PRBS_WIDTH - 1 DOWNTO 0)
);
END data_prbs_gen;
ARCHITECTURE trans OF data_prbs_gen IS
SIGNAL prbs : STD_LOGIC_VECTOR(PRBS_WIDTH - 1 DOWNTO 0);
SIGNAL lfsr_q : STD_LOGIC_VECTOR(PRBS_WIDTH DOWNTO 1);
SIGNAL i : INTEGER;
BEGIN
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (((prbs_seed_init = '1') AND (EYE_TEST = "FALSE")) OR (rst_i = '1')) THEN
lfsr_q <= prbs_seed_i + prbs_fseed_i(31 DOWNTO 0) + "01010101010101010101010101010101";
ELSIF (clk_en = '1') THEN
lfsr_q(32 DOWNTO 9) <= lfsr_q(31 DOWNTO 8);
lfsr_q(8) <= lfsr_q(32) XOR lfsr_q(7);
lfsr_q(7) <= lfsr_q(32) XOR lfsr_q(6);
lfsr_q(6 DOWNTO 4) <= lfsr_q(5 DOWNTO 3);
lfsr_q(3) <= lfsr_q(32) XOR lfsr_q(2);
lfsr_q(2) <= lfsr_q(1);
lfsr_q(1) <= lfsr_q(32);
END IF;
END IF;
END PROCESS;
PROCESS (lfsr_q(PRBS_WIDTH DOWNTO 1))
BEGIN
prbs <= lfsr_q(PRBS_WIDTH DOWNTO 1);
END PROCESS;
prbs_o <= prbs;
END trans;
|
bsd-2-clause
|
mithro/HDMI2USB
|
ipcore_dir/edidram.vhd
|
3
|
5695
|
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2013 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file edidram.vhd when simulating
-- the core, edidram. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY edidram IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END edidram;
ARCHITECTURE edidram_a OF edidram IS
-- synthesis translate_off
COMPONENT wrapped_edidram
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_edidram USE ENTITY XilinxCoreLib.blk_mem_gen_v7_2(behavioral)
GENERIC MAP (
c_addra_width => 8,
c_addrb_width => 8,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "0",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_enable_32bit_address => 0,
c_family => "spartan6",
c_has_axi_id => 0,
c_has_ena => 0,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file_name => "no_coe_file_loaded",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 0,
c_mem_type => 1,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 256,
c_read_depth_b => 256,
c_read_width_a => 8,
c_read_width_b => 8,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 0,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 256,
c_write_depth_b => 256,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 8,
c_write_width_b => 8,
c_xdevicefamily => "spartan6"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_edidram
PORT MAP (
clka => clka,
wea => wea,
addra => addra,
dina => dina,
clkb => clkb,
addrb => addrb,
doutb => doutb
);
-- synthesis translate_on
END edidram_a;
|
bsd-2-clause
|
mithro/HDMI2USB
|
hdl/jpeg_encoder/design/ROMR.vhd
|
5
|
7225
|
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2009 --
-- --
--------------------------------------------------------------------------------
--
-- Title : ROMR
-- Design : EV_JPEG_ENC
-- Author : Michal Krepa
--
--------------------------------------------------------------------------------
--
-- File : ROMR.VHD
-- Created : Wed Mar 19 21:09 2009
--
--------------------------------------------------------------------------------
--
-- Description : Reciprocal of 1/X where X is 1..255
--
--------------------------------------------------------------------------------
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- /// Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
entity ROMR is
generic
(
ROMADDR_W : INTEGER := 8;
ROMDATA_W : INTEGER := 16
);
port(
addr : in STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
clk : in STD_LOGIC;
datao : out STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0)
);
end ROMR;
architecture RTL of ROMR is
constant CK : integer := 256*256;
type ROMQ_TYPE is array (0 to 2**ROMADDR_W-1)
of INTEGER range 0 to 2**ROMDATA_W-1;
constant rom : ROMQ_TYPE :=
(
0,
65535,
32768,
21845,
16384,
13107,
10923,
9362,
8192,
7282,
6554,
5958,
5461,
5041,
4681,
4369,
4096,
3855,
3641,
3449,
3277,
3121,
2979,
2849,
2731,
2621,
2521,
2427,
2341,
2260,
2185,
2114,
2048,
1986,
1928,
1872,
1820,
1771,
1725,
1680,
1638,
1598,
1560,
1524,
1489,
1456,
1425,
1394,
1365,
1337,
1311,
1285,
1260,
1237,
1214,
1192,
1170,
1150,
1130,
1111,
1092,
1074,
1057,
1040,
1024,
1008,
993,
978,
964,
950,
936,
923,
910,
898,
886,
874,
862,
851,
840,
830,
819,
809,
799,
790,
780,
771,
762,
753,
745,
736,
728,
720,
712,
705,
697,
690,
683,
676,
669,
662,
655,
649,
643,
636,
630,
624,
618,
612,
607,
601,
596,
590,
585,
580,
575,
570,
565,
560,
555,
551,
546,
542,
537,
533,
529,
524,
520,
516,
512,
508,
504,
500,
496,
493,
489,
485,
482,
478,
475,
471,
468,
465,
462,
458,
455,
452,
449,
446,
443,
440,
437,
434,
431,
428,
426,
423,
420,
417,
415,
412,
410,
407,
405,
402,
400,
397,
395,
392,
390,
388,
386,
383,
381,
379,
377,
374,
372,
370,
368,
366,
364,
362,
360,
358,
356,
354,
352,
350,
349,
347,
345,
343,
341,
340,
338,
336,
334,
333,
331,
329,
328,
326,
324,
323,
321,
320,
318,
317,
315,
314,
312,
311,
309,
308,
306,
305,
303,
302,
301,
299,
298,
297,
295,
294,
293,
291,
290,
289,
287,
286,
285,
284,
282,
281,
280,
279,
278,
277,
275,
274,
273,
272,
271,
270,
269,
267,
266,
265,
264,
263,
262,
261,
260,
259,
258,
257
);
signal addr_reg : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
begin
datao <= STD_LOGIC_VECTOR(TO_UNSIGNED( rom( TO_INTEGER(UNSIGNED(addr_reg)) ), ROMDATA_W));
process(clk)
begin
if clk = '1' and clk'event then
addr_reg <= addr;
end if;
end process;
end RTL;
|
bsd-2-clause
|
mithro/HDMI2USB
|
ipcore_dir/ddr2ram/example_design/rtl/iodrp_mcb_controller.vhd
|
19
|
18779
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: iodrp_mcb_controller.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:17:25 $
-- \ \ / \ Date Created: Mon Feb 9 2009
-- \___\/\___\
--
--Device: Spartan6
--Design Name: DDR/DDR2/DDR3/LPDDR
--Purpose: Xilinx reference design for IODRP controller for v0.9 device
--
--Reference:
--
-- Revision: Date: Comment
-- 1.0: 03/19/09: Initial version for IODRP_MCB read operations.
-- 1.1: 04/03/09: SLH - Added left shift for certain IOI's
-- 1.2: 02/14/11: Change FSM encoding from one-hot to gray to match Verilog version.
-- End Revision
--*******************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity iodrp_mcb_controller is
--output to IODRP SDI pin
--input from IODRP SDO pin
-- Register where memcell_address is captured during the READY state
-- Register which stores the write data until it is ready to be shifted out
-- The shift register which shifts out SDO and shifts in SDI.
-- This register is loaded before the address or data phase, but continues to shift for a writeback of read data
-- The signal which causes shift_through_reg to load the new value from data_out_mux, or continue to shift data in from DRP_SDO
-- The signal which indicates where the shift_through_reg should load from. 0 -> data_reg 1 -> memcell_addr_reg
-- The counter for which bit is being shifted during address or data phase
-- This is set after the first address phase has executed
-- The mux which selects between data_reg and memcell_addr_reg for sending to shift_through_reg
--added so that DRP_SDI output is only active when DRP_CS is active
port (
memcell_address : in std_logic_vector(7 downto 0);
write_data : in std_logic_vector(7 downto 0);
read_data : out std_logic_vector(7 downto 0);
rd_not_write : in std_logic;
cmd_valid : in std_logic;
rdy_busy_n : out std_logic;
use_broadcast : in std_logic;
drp_ioi_addr : in std_logic_vector(4 downto 0);
sync_rst : in std_logic;
DRP_CLK : in std_logic;
DRP_CS : out std_logic;
DRP_SDI : out std_logic;
DRP_ADD : out std_logic;
DRP_BKST : out std_logic;
DRP_SDO : in std_logic;
MCB_UIREAD : out std_logic
);
end entity iodrp_mcb_controller;
architecture trans of iodrp_mcb_controller is
type StType is (
READY,
DECIDE ,
ADDR_PHASE ,
ADDR_TO_DATA_GAP ,
ADDR_TO_DATA_GAP2,
ADDR_TO_DATA_GAP3,
DATA_PHASE ,
ALMOST_READY ,
ALMOST_READY2 ,
ALMOST_READY3
);
constant IOI_DQ0 : std_logic_vector(4 downto 0) := "00001";
constant IOI_DQ1 : std_logic_vector(4 downto 0) := "00000";
constant IOI_DQ2 : std_logic_vector(4 downto 0) := "00011";
constant IOI_DQ3 : std_logic_vector(4 downto 0) := "00010";
constant IOI_DQ4 : std_logic_vector(4 downto 0) := "00101";
constant IOI_DQ5 : std_logic_vector(4 downto 0) := "00100";
constant IOI_DQ6 : std_logic_vector(4 downto 0) := "00111";
constant IOI_DQ7 : std_logic_vector(4 downto 0) := "00110";
constant IOI_DQ8 : std_logic_vector(4 downto 0) := "01001";
constant IOI_DQ9 : std_logic_vector(4 downto 0) := "01000";
constant IOI_DQ10 : std_logic_vector(4 downto 0) := "01011";
constant IOI_DQ11 : std_logic_vector(4 downto 0) := "01010";
constant IOI_DQ12 : std_logic_vector(4 downto 0) := "01101";
constant IOI_DQ13 : std_logic_vector(4 downto 0) := "01100";
constant IOI_DQ14 : std_logic_vector(4 downto 0) := "01111";
constant IOI_DQ15 : std_logic_vector(4 downto 0) := "01110";
constant IOI_UDQS_CLK : std_logic_vector(4 downto 0) := "11101";
constant IOI_UDQS_PIN : std_logic_vector(4 downto 0) := "11100";
constant IOI_LDQS_CLK : std_logic_vector(4 downto 0) := "11111";
constant IOI_LDQS_PIN : std_logic_vector(4 downto 0) := "11110";
signal memcell_addr_reg : std_logic_vector(7 downto 0);
signal data_reg : std_logic_vector(7 downto 0);
signal shift_through_reg : std_logic_vector(8 downto 0);
signal load_shift_n : std_logic;
signal addr_data_sel_n : std_logic;
signal bit_cnt : std_logic_vector(2 downto 0);
signal rd_not_write_reg : std_logic;
signal AddressPhase : std_logic;
signal DRP_CS_pre : std_logic;
signal extra_cs : std_logic;
signal state,nextstate : StType;
attribute fsm_encoding : string;
attribute fsm_encoding of state : signal is "gray";
attribute fsm_encoding of nextstate : signal is "gray";
signal data_out : std_logic_vector(8 downto 0);
signal data_out_mux : std_logic_vector(8 downto 0);
signal DRP_SDI_pre : std_logic;
--synthesis translate_off
signal state_ascii : std_logic_vector(32 * 8 - 1 downto 0);
-- case(state)
--synthesis translate_on
-- The changes below are to compensate for an issue with 1.0 silicon.
-- It may still be necessary to add a clock cycle to the ADD and CS signals
--`define DRP_v1_0_FIX // Uncomment out this line for synthesis
procedure shift_n_expand(
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(8 downto 0)) is
variable data_out_xilinx2 : std_logic_vector(8 downto 0);
begin
if ((data_in(0)) = '1') then
data_out_xilinx2(1 downto 0) := "11";
else
data_out_xilinx2(1 downto 0) := "00";
end if;
if (data_in(1 downto 0) = "10") then
data_out_xilinx2(2 downto 1) := "11";
else
data_out_xilinx2(2 downto 1) := (data_in(1) & data_out_xilinx2(1));
end if;
if (data_in(2 downto 1) = "10") then
data_out_xilinx2(3 downto 2) := "11";
else
data_out_xilinx2(3 downto 2) := (data_in(2) & data_out_xilinx2(2));
end if;
if (data_in(3 downto 2) = "10") then
data_out_xilinx2(4 downto 3) := "11";
else
data_out_xilinx2(4 downto 3) := (data_in(3) & data_out_xilinx2(3));
end if;
if (data_in(4 downto 3) = "10") then
data_out_xilinx2(5 downto 4) := "11";
else
data_out_xilinx2(5 downto 4) := (data_in(4) & data_out_xilinx2(4));
end if;
if (data_in(5 downto 4) = "10") then
data_out_xilinx2(6 downto 5) := "11";
else
data_out_xilinx2(6 downto 5) := (data_in(5) & data_out_xilinx2(5));
end if;
if (data_in(6 downto 5) = "10") then
data_out_xilinx2(7 downto 6) := "11";
else
data_out_xilinx2(7 downto 6) := (data_in(6) & data_out_xilinx2(6));
end if;
if (data_in(7 downto 6) = "10") then
data_out_xilinx2(8 downto 7) := "11";
else
data_out_xilinx2(8 downto 7) := (data_in(7) & data_out_xilinx2(7));
end if;
end shift_n_expand;
-- Declare intermediate signals for referenced outputs
signal DRP_CS_xilinx1 : std_logic;
signal DRP_ADD_xilinx0 : std_logic;
signal ALMOST_READY2_ST : std_logic;
signal ADDR_PHASE_ST : std_logic;
signal BIT_CNT7 : std_logic;
signal ADDR_PHASE_ST1 : std_logic;
signal DATA_PHASE_ST : std_logic;
begin
-- Drive referenced outputs
DRP_CS <= DRP_CS_xilinx1;
DRP_ADD <= DRP_ADD_xilinx0;
-- process (state)
-- begin
-- case state is
-- when READY =>
-- state_ascii <= "READY";
-- when DECIDE =>
-- state_ascii <= "DECIDE";
-- when ADDR_PHASE =>
-- state_ascii <= "ADDR_PHASE";
-- when ADDR_TO_DATA_GAP =>
-- state_ascii <= "ADDR_TO_DATA_GAP";
-- when ADDR_TO_DATA_GAP2 =>
-- state_ascii <= "ADDR_TO_DATA_GAP2";
-- when ADDR_TO_DATA_GAP3 =>
-- state_ascii <= "ADDR_TO_DATA_GAP3";
-- when DATA_PHASE =>
-- state_ascii <= "DATA_PHASE";
-- when ALMOST_READY =>
-- state_ascii <= "ALMOST_READY";
-- when ALMOST_READY2 =>
-- state_ascii <= "ALMOST_READY2";
-- when ALMOST_READY3 =>
-- state_ascii <= "ALMOST_READY3";
-- when others =>
-- null;
-- end case;
-- end process;
process (DRP_CLK)
begin
if (DRP_CLK'event and DRP_CLK = '1') then
if (state = READY) then
memcell_addr_reg <= memcell_address;
data_reg <= write_data;
rd_not_write_reg <= rd_not_write;
end if;
end if;
end process;
rdy_busy_n <= '1' when state = READY else '0';
process (drp_ioi_addr, data_out)
begin
case drp_ioi_addr is
when IOI_DQ0 =>
data_out_mux <= data_out;
when IOI_DQ1 =>
data_out_mux <= data_out;
when IOI_DQ2 =>
data_out_mux <= data_out;
when IOI_DQ3 =>
data_out_mux <= data_out;
when IOI_DQ4 =>
data_out_mux <= data_out;
when IOI_DQ5 =>
data_out_mux <= data_out;
when IOI_DQ6 =>
data_out_mux <= data_out;
when IOI_DQ7 =>
data_out_mux <= data_out;
when IOI_DQ8 =>
data_out_mux <= data_out;
when IOI_DQ9 =>
data_out_mux <= data_out;
when IOI_DQ10 =>
data_out_mux <= data_out;
when IOI_DQ11 =>
data_out_mux <= data_out;
when IOI_DQ12 =>
data_out_mux <= data_out;
when IOI_DQ13 =>
data_out_mux <= data_out;
when IOI_DQ14 =>
data_out_mux <= data_out;
when IOI_DQ15 =>
data_out_mux <= data_out;
when IOI_UDQS_CLK =>
data_out_mux <= data_out;
when IOI_UDQS_PIN =>
data_out_mux <= data_out;
when IOI_LDQS_CLK =>
data_out_mux <= data_out;
when IOI_LDQS_PIN =>
data_out_mux <= data_out;
when others =>
data_out_mux <= data_out;
end case;
end process;
data_out <= ('0' & memcell_addr_reg) when (addr_data_sel_n = '1') else
('0' & data_reg);
process (DRP_CLK)
begin
if (DRP_CLK'event and DRP_CLK = '1') then
if (sync_rst = '1') then
shift_through_reg <= "000000000";
else
if (load_shift_n = '1') then --Assume the shifter is either loading or shifting, bit 0 is shifted out first
shift_through_reg <= data_out_mux;
else
shift_through_reg <= ('0' & DRP_SDO & shift_through_reg(7 downto 1));
end if;
end if;
end if;
end process;
process (DRP_CLK)
begin
if (DRP_CLK'event and DRP_CLK = '1') then
if (((state = ADDR_PHASE) or (state = DATA_PHASE)) and (sync_rst = '0')) then
bit_cnt <= bit_cnt + "001";
else
bit_cnt <= "000";
end if;
end if;
end process;
process (DRP_CLK)
begin
if (DRP_CLK'event and DRP_CLK = '1') then
if (sync_rst = '1') then
read_data <= "00000000";
else
if (state = ALMOST_READY3) then
read_data <= shift_through_reg(7 downto 0);
end if;
end if;
end if;
end process;
ALMOST_READY2_ST <= '1' when state = ALMOST_READY2 else '0';
ADDR_PHASE_ST <= '1' when state = ADDR_PHASE else '0';
BIT_CNT7 <= '1' when bit_cnt = "111" else '0';
process (DRP_CLK)
begin
if (DRP_CLK'event and DRP_CLK = '1') then
if (sync_rst = '1') then
AddressPhase <= '0';
else
if (AddressPhase = '1') then
-- Keep it set until we finish the cycle
AddressPhase <= AddressPhase and (not ALMOST_READY2_ST);
else
-- set the address phase when ever we finish the address phase
AddressPhase <= (ADDR_PHASE_ST and BIT_CNT7);
end if;
end if;
end if;
end process;
ADDR_PHASE_ST1 <= '1' when nextstate = ADDR_PHASE else '0';
DATA_PHASE_ST <= '1' when nextstate = DATA_PHASE else '0';
process (DRP_CLK)
begin
if (DRP_CLK'event and DRP_CLK = '1') then
DRP_ADD_xilinx0 <= ADDR_PHASE_ST1;
-- DRP_CS <= (drp_ioi_addr != IOI_DQ0) ? (nextstate == ADDR_PHASE) | (nextstate == DATA_PHASE) : (bit_cnt != 3'b111) && (nextstate == ADDR_PHASE) | (nextstate == DATA_PHASE);
DRP_CS_xilinx1 <= ADDR_PHASE_ST1 or DATA_PHASE_ST;
MCB_UIREAD <= DATA_PHASE_ST and rd_not_write_reg;
if (state = READY) then
DRP_BKST <= use_broadcast;
end if;
end if;
end process;
DRP_SDI_pre <= shift_through_reg(0) when (DRP_CS_xilinx1 = '1') else --if DRP_CS is inactive, just drive 0 out - this is a possible place to pipeline for increased performance
'0';
DRP_SDI <= DRP_SDO when ((rd_not_write_reg and DRP_CS_xilinx1 and not(DRP_ADD_xilinx0)) = '1') else --If reading, then feed SDI back out SDO - this is a possible place to pipeline for increased performance
DRP_SDI_pre;
process (state, cmd_valid, bit_cnt, rd_not_write_reg, AddressPhase,BIT_CNT7)
begin
addr_data_sel_n <= '0';
load_shift_n <= '0';
case state is
when READY =>
load_shift_n <= '0';
if (cmd_valid = '1') then
nextstate <= DECIDE;
else
nextstate <= READY;
end if;
when DECIDE =>
load_shift_n <= '1';
addr_data_sel_n <= '1';
nextstate <= ADDR_PHASE;
-- After the second pass go to end of statemachine
-- execute a second address phase for the alternative access method.
when ADDR_PHASE =>
load_shift_n <= '0';
if (BIT_CNT7 = '1') then
if (('1' and rd_not_write_reg) = '1') then
if (AddressPhase = '1') then
nextstate <= ALMOST_READY;
else
nextstate <= DECIDE;
end if;
else
nextstate <= ADDR_TO_DATA_GAP;
end if;
else
nextstate <= ADDR_PHASE;
end if;
when ADDR_TO_DATA_GAP =>
load_shift_n <= '1';
nextstate <= ADDR_TO_DATA_GAP2;
when ADDR_TO_DATA_GAP2 =>
load_shift_n <= '1';
nextstate <= ADDR_TO_DATA_GAP3;
when ADDR_TO_DATA_GAP3 =>
load_shift_n <= '1';
nextstate <= DATA_PHASE;
when DATA_PHASE =>
load_shift_n <= '0';
if (BIT_CNT7 = '1') then
nextstate <= ALMOST_READY;
else
nextstate <= DATA_PHASE;
end if;
when ALMOST_READY =>
load_shift_n <= '0';
nextstate <= ALMOST_READY2;
when ALMOST_READY2 =>
load_shift_n <= '0';
nextstate <= ALMOST_READY3;
when ALMOST_READY3 =>
load_shift_n <= '0';
nextstate <= READY;
when others =>
load_shift_n <= '0';
nextstate <= READY;
end case;
end process;
process (DRP_CLK)
begin
if (DRP_CLK'event and DRP_CLK = '1') then
if (sync_rst = '1') then
state <= READY;
else
state <= nextstate;
end if;
end if;
end process;
end architecture trans;
|
bsd-2-clause
|
mithro/HDMI2USB
|
ipcore_dir/edidram/example_design/edidram_prod.vhd
|
3
|
10241
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: edidram_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : spartan6
-- C_XDEVICEFAMILY : spartan6
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 1
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 0
-- C_INIT_FILE_NAME : no_coe_file_loaded
-- C_USE_DEFAULT_DATA : 0
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 8
-- C_READ_WIDTH_A : 8
-- C_WRITE_DEPTH_A : 256
-- C_READ_DEPTH_A : 256
-- C_ADDRA_WIDTH : 8
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 8
-- C_READ_WIDTH_B : 8
-- C_WRITE_DEPTH_B : 256
-- C_READ_DEPTH_B : 256
-- C_ADDRB_WIDTH : 8
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY edidram_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END edidram_prod;
ARCHITECTURE xilinx OF edidram_prod IS
COMPONENT edidram_exdes IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Port B
ADDRB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : edidram_exdes
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
CLKA => CLKA,
--Port B
ADDRB => ADDRB,
DOUTB => DOUTB,
CLKB => CLKB
);
END xilinx;
|
bsd-2-clause
|
mithro/HDMI2USB
|
ipcore_dir/ddr2ram/example_design/rtl/traffic_gen/cmd_gen.vhd
|
20
|
39433
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: cmd_gen.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/05/27 15:50:27 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This module genreates different type of commands, address,
-- burst_length to mcb_flow_control module.
-- Reference:
-- Revision History:
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
ENTITY cmd_gen IS
GENERIC (
FAMILY : STRING := "SPARTAN6";
MEM_BURST_LEN : INTEGER := 8;
TCQ : TIME := 100 ps;
PORT_MODE : STRING := "BI_MODE";
NUM_DQ_PINS : INTEGER := 8;
DATA_PATTERN : STRING := "DGEN_ALL";
CMD_PATTERN : STRING := "CGEN_ALL";
ADDR_WIDTH : INTEGER := 30;
DWIDTH : INTEGER := 32;
PIPE_STAGES : INTEGER := 0;
MEM_COL_WIDTH : INTEGER := 10;
PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"FFFFD000";
PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00002000";
PRBS_EADDR : std_logic_vector(31 downto 0) := X"00002000";
PRBS_SADDR : std_logic_vector(31 downto 0) := X"00002000"
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
run_traffic_i : IN STD_LOGIC;
rd_buff_avail_i : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
force_wrcmd_gen_i : IN STD_LOGIC;
start_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
end_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
cmd_seed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
data_seed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
load_seed_i : IN STD_LOGIC;
addr_mode_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
data_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
instr_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
bl_mode_i : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
mode_load_i : IN STD_LOGIC;
fixed_bl_i : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
fixed_instr_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
fixed_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_instr_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
bram_bl_i : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
bram_valid_i : IN STD_LOGIC;
bram_rdy_o : OUT STD_LOGIC;
reading_rd_data_i : IN STD_LOGIC;
rdy_i : IN STD_LOGIC;
addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
instr_o : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
bl_o : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
-- m_addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
cmd_o_vld : OUT STD_LOGIC
);
END cmd_gen;
ARCHITECTURE trans OF cmd_gen IS
constant PRBS_ADDR_WIDTH : INTEGER := 32;
constant INSTR_PRBS_WIDTH : INTEGER := 16;
constant BL_PRBS_WIDTH : INTEGER := 16;
constant BRAM_DATAL_MODE : std_logic_vector(3 downto 0) := "0000";
constant FIXED_DATA_MODE : std_logic_vector(3 downto 0) := "0001";
constant ADDR_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
constant HAMMER_DATA_MODE : std_logic_vector(3 downto 0) := "0011";
constant NEIGHBOR_DATA_MODE : std_logic_vector(3 downto 0) := "0100";
constant WALKING1_DATA_MODE : std_logic_vector(3 downto 0) := "0101";
constant WALKING0_DATA_MODE : std_logic_vector(3 downto 0) := "0110";
constant PRBS_DATA_MODE : std_logic_vector(3 downto 0) := "0111";
COMPONENT pipeline_inserter IS
GENERIC (
DATA_WIDTH : INTEGER := 32;
PIPE_STAGES : INTEGER := 1
);
PORT (
data_i : IN STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0);
clk_i : IN STD_LOGIC;
en_i : IN STD_LOGIC;
data_o : OUT STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT cmd_prbs_gen IS
GENERIC (
TCQ : time := 100 ps;
FAMILY : STRING := "SPARTAN6";
ADDR_WIDTH : INTEGER := 29;
DWIDTH : INTEGER := 32;
PRBS_CMD : STRING := "ADDRESS";
PRBS_WIDTH : INTEGER := 64;
SEED_WIDTH : INTEGER := 32;
PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"FFFFD000";
PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00002000";
PRBS_EADDR : std_logic_vector(31 downto 0) := X"00002000";
PRBS_SADDR : std_logic_vector(31 downto 0) := X"00002000"
);
PORT (
clk_i : IN STD_LOGIC;
prbs_seed_init : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
prbs_seed_i : IN STD_LOGIC_VECTOR(SEED_WIDTH - 1 DOWNTO 0);
prbs_o : OUT STD_LOGIC_VECTOR(SEED_WIDTH - 1 DOWNTO 0)
);
END COMPONENT;
function BOOLEAN_TO_STD_LOGIC(A : in BOOLEAN) return std_logic is
begin
if A = true then
return '1';
else
return '0';
end if;
end function BOOLEAN_TO_STD_LOGIC;
SIGNAL INC_COUNTS : STD_LOGIC_VECTOR(10 DOWNTO 0);
SIGNAL addr_mode_reg : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL bl_mode_reg : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL addr_counts : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL prbs_bl : STD_LOGIC_VECTOR(14 DOWNTO 0);
SIGNAL instr_out : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL prbs_instr_a : STD_LOGIC_VECTOR(14 DOWNTO 0);
SIGNAL prbs_instr_b : STD_LOGIC_VECTOR(14 DOWNTO 0);
SIGNAL prbs_brlen : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL prbs_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL seq_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL fixed_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL bl_out : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL bl_out_reg : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL mode_load_d1 : STD_LOGIC;
SIGNAL mode_load_d2 : STD_LOGIC;
SIGNAL mode_load_pulse : STD_LOGIC;
SIGNAL pipe_data_o : STD_LOGIC_VECTOR(41 DOWNTO 0);
SIGNAL cmd_clk_en : STD_LOGIC;
SIGNAL pipe_out_vld : STD_LOGIC;
SIGNAL end_addr_range : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL force_bl1 : STD_LOGIC;
SIGNAL A0_G_E0 : STD_LOGIC;
SIGNAL A1_G_E1 : STD_LOGIC;
SIGNAL A2_G_E2 : STD_LOGIC;
SIGNAL A3_G_E3 : STD_LOGIC;
SIGNAL AC3_G_E3 : STD_LOGIC;
SIGNAL AC2_G_E2 : STD_LOGIC;
SIGNAL AC1_G_E1 : STD_LOGIC;
SIGNAL bl_out_clk_en : STD_LOGIC;
SIGNAL pipe_data_in : STD_LOGIC_VECTOR(41 DOWNTO 0);
SIGNAL instr_vld : STD_LOGIC;
SIGNAL bl_out_vld : STD_LOGIC;
SIGNAL cmd_vld : STD_LOGIC;
SIGNAL run_traffic_r : STD_LOGIC;
SIGNAL run_traffic_pulse : STD_LOGIC;
SIGNAL pipe_data_in_vld : STD_LOGIC;
SIGNAL gen_addr_larger : STD_LOGIC;
SIGNAL buf_avail_r : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL rd_data_received_counts : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL rd_data_counts_asked : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL rd_data_received_counts_total : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL instr_vld_dly1 : STD_LOGIC;
SIGNAL first_load_pulse : STD_LOGIC;
SIGNAL mem_init_done : STD_LOGIC;
SIGNAL i : INTEGER;
SIGNAL force_wrcmd_gen : STD_LOGIC;
SIGNAL force_smallvalue : STD_LOGIC;
SIGNAL end_addr_r : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL force_rd_counts : STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL force_rd : STD_LOGIC;
SIGNAL addr_counts_next_r : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL refresh_cmd_en : STD_LOGIC;
SIGNAL refresh_timer : STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL refresh_prbs : STD_LOGIC;
SIGNAL cmd_clk_en_r : STD_LOGIC;
signal instr_mode_reg : std_logic_vector(3 downto 0);
-- X-HDL generated signals
SIGNAL xhdl4 : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL xhdl12 : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL xhdl14 : STD_LOGIC_VECTOR(5 DOWNTO 0);
-- Declare intermediate signals for referenced outputs
SIGNAL bl_o_xhdl0 : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL mode_load_pulse_r1 : STD_LOGIC;
BEGIN
-- Drive referenced outputs
bl_o <= bl_o_xhdl0;
addr_o <= pipe_data_o(31 DOWNTO 0);
instr_o <= pipe_data_o(34 DOWNTO 32);
bl_o_xhdl0 <= pipe_data_o(40 DOWNTO 35);
cmd_o_vld <= pipe_data_o(41) AND run_traffic_r;
pipe_out_vld <= pipe_data_o(41) AND run_traffic_r;
pipe_data_o <= pipe_data_in;
cv1 : IF (CMD_PATTERN = "CGEN_BRAM") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
cmd_vld <= cmd_clk_en;
END IF;
END PROCESS;
END GENERATE;
cv3 : IF (CMD_PATTERN = "CGEN_PRBS" OR CMD_PATTERN = "CGEN_ALL" OR CMD_PATTERN = "CGEN_SEQUENTIAL" OR CMD_PATTERN = "CGEN_FIXED") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
cmd_vld <= cmd_clk_en OR (mode_load_pulse AND first_load_pulse);
END IF;
END PROCESS;
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
run_traffic_r <= run_traffic_i ;
IF ( run_traffic_i= '1' AND run_traffic_r = '0' ) THEN
run_traffic_pulse <= '1' ;
ELSE
run_traffic_pulse <= '0' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
instr_vld <= cmd_clk_en OR (mode_load_pulse AND first_load_pulse) ;
bl_out_clk_en <= cmd_clk_en OR (mode_load_pulse AND first_load_pulse) ;
bl_out_vld <= bl_out_clk_en ;
pipe_data_in_vld <= instr_vld ;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0) = '1') THEN
first_load_pulse <= '1' ;
ELSIF (mode_load_pulse = '1') THEN
first_load_pulse <= '0' ;
ELSE
first_load_pulse <= first_load_pulse ;
END IF;
END IF;
END PROCESS;
cmd_clk_en <= (rdy_i AND pipe_out_vld AND run_traffic_i) OR (mode_load_pulse AND BOOLEAN_TO_STD_LOGIC(CMD_PATTERN = "CGEN_BRAM"));
pipe_in_s6 : IF (FAMILY = "SPARTAN6") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(0)) = '1') THEN
pipe_data_in(31 DOWNTO 0) <= start_addr_i ;
ELSIF (instr_vld = '1') THEN
IF (gen_addr_larger = '1' AND (addr_mode_reg = "100" OR addr_mode_reg = "010")) THEN
IF (DWIDTH = 32) THEN
pipe_data_in(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 8) & "00000000") ;
ELSIF (DWIDTH = 64) THEN
pipe_data_in(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 9) & "000000000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 10) & "0000000000") ;
END IF;
ELSE
IF (DWIDTH = 32) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 2) & "00") ;
ELSIF (DWIDTH = 64) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000") ;
ELSIF (DWIDTH = 128) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) & "0000") ;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
pipe_in_v6 : IF (FAMILY = "VIRTEX6") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(1)) = '1') THEN
pipe_data_in(31 DOWNTO 0) <= start_addr_i ;
ELSIF (instr_vld = '1') THEN
IF (gen_addr_larger = '1' AND (addr_mode_reg = "100" OR addr_mode_reg = "010")) THEN
pipe_data_in(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 8) & "00000000") ;
ELSIF ((NUM_DQ_PINS >= 128) AND (NUM_DQ_PINS <= 144)) THEN
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 7) & "0000000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 6) & "000000") ;
END IF;
ELSIF ((NUM_DQ_PINS >= 64) AND (NUM_DQ_PINS < 128)) THEN
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 6) & "000000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 5) & "00000") ;
END IF;
ELSIF ((NUM_DQ_PINS = 32) OR (NUM_DQ_PINS = 40) OR (NUM_DQ_PINS = 48) OR (NUM_DQ_PINS = 56)) THEN
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 5) & "00000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) & "0000") ;
END IF;
ELSIF ((NUM_DQ_PINS = 16) OR (NUM_DQ_PINS = 24)) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000");
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) & "0000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000") ;
END IF;
ELSIF (NUM_DQ_PINS = 8) THEN
IF (MEM_BURST_LEN = 8) THEN
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000") ;
ELSE
pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 2) & "00") ;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
-- pipe_m_addr_o : IF (FAMILY = "VIRTEX6") GENERATE
-- PROCESS (clk_i)
-- BEGIN
-- IF (clk_i'EVENT AND clk_i = '1') THEN
-- IF ((rst_i(1)) = '1') THEN
-- m_addr_o(31 DOWNTO 0) <= start_addr_i ;
-- ELSIF (instr_vld = '1') THEN
-- IF (gen_addr_larger = '1' AND (addr_mode_reg = "100" OR addr_mode_reg = "010")) THEN
-- m_addr_o(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 8) & "00000000") ;
--
-- ELSIF ((NUM_DQ_PINS >= 128) AND (NUM_DQ_PINS < 256)) THEN
-- m_addr_o <= (addr_out(31 DOWNTO 6) & "000000") ;
--
-- ELSIF ((NUM_DQ_PINS >= 64) AND (NUM_DQ_PINS < 128)) THEN
-- m_addr_o <= (addr_out(31 DOWNTO 5) & "00000") ;
-- ELSIF ((NUM_DQ_PINS = 32) OR (NUM_DQ_PINS = 40) OR (NUM_DQ_PINS = 48) OR (NUM_DQ_PINS = 56)) THEN
-- m_addr_o(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) & "0000") ;
-- ELSIF ((NUM_DQ_PINS = 16) OR (NUM_DQ_PINS = 17)) THEN
-- m_addr_o(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000") ;
-- ELSIF ((NUM_DQ_PINS = 8) OR (NUM_DQ_PINS = 9)) THEN
-- m_addr_o(31 DOWNTO 0) <= (addr_out(31 DOWNTO 2) & "00") ;
-- END IF;
-- END IF;
-- END IF;
-- END PROCESS;
--
-- END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0) = '1') THEN
force_wrcmd_gen <= '0' ;
ELSIF (buf_avail_r = "0111111") THEN
force_wrcmd_gen <= '0' ;
ELSIF (instr_vld_dly1 = '1' AND pipe_data_in(32) = '1' AND pipe_data_in(41 DOWNTO 35) > "0010000") THEN
force_wrcmd_gen <= '1' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
instr_mode_reg <= instr_mode_i ;
END IF;
END PROCESS;
-- **********************************************
PROCESS (clk_i) BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(2)) = '1') THEN
pipe_data_in(40 DOWNTO 32) <= "000000000";
force_smallvalue <= '0';
ELSIF (instr_vld = '1') THEN
IF (instr_mode_reg = 0) THEN
pipe_data_in(34 DOWNTO 32) <= instr_out ;
ELSIF (instr_out(2) = '1') THEN
pipe_data_in(34 DOWNTO 32) <= "100" ;
ELSIF (FAMILY = "SPARTAN6" AND PORT_MODE = "RD_MODE") THEN
pipe_data_in(34 DOWNTO 32) <= instr_out(2 downto 1) & '1' ;
ELSIF ((force_wrcmd_gen = '1' OR buf_avail_r <= "0001111") AND FAMILY = "SPARTAN6" AND PORT_MODE /= "RD_MODE") THEN
pipe_data_in(34 DOWNTO 32) <= instr_out(2) & "00";
ELSE
pipe_data_in(34 DOWNTO 32) <= instr_out;
END IF;
----********* condition the generated bl value except if TG is programmed for BRAM interface'
---- if the generated address is close to end address range, the bl_out will be altered to 1.
--
IF (bl_mode_i = 0) THEN
pipe_data_in(40 DOWNTO 35) <= bl_out ;
ELSIF ( FAMILY = "VIRTEX6") THEN
pipe_data_in(40 DOWNTO 35) <= bl_out ;
ELSIF (force_bl1 = '1' AND (bl_mode_reg = "10") AND FAMILY = "SPARTAN6") THEN
pipe_data_in(40 DOWNTO 35) <= "000001" ;
-- **********************************************
ELSIF (buf_avail_r(5 DOWNTO 0) >= "111100" AND buf_avail_r(6) = '0' AND pipe_data_in(32) = '1' AND FAMILY = "SPARTAN6") THEN
IF (bl_mode_reg = "10") THEN
force_smallvalue <= NOT(force_smallvalue) ;
END IF;
IF (buf_avail_r(6) = '1' AND bl_mode_reg = "10") THEN
pipe_data_in(40 DOWNTO 35) <= ("00" & bl_out(3 DOWNTO 1) & '1') ;
ELSE
pipe_data_in(40 DOWNTO 35) <= bl_out ;
END IF;
ELSIF (buf_avail_r < "1000000" AND rd_buff_avail_i >= "0000000" AND instr_out(0) = '1' AND (bl_mode_reg = "10")) THEN
IF (FAMILY = "SPARTAN6") THEN
pipe_data_in(40 DOWNTO 35) <= ("00" & bl_out(3 DOWNTO 0)) + '1' ;
ELSE
pipe_data_in(40 DOWNTO 35) <= bl_out ;
END IF;
END IF; --IF (bl_mode_i = 0) THEN
END IF; --IF ((rst_i(2)) = '1') THEN
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(2)) = '1') THEN
pipe_data_in(41) <= '0' ;
ELSIF (cmd_vld = '1') THEN
pipe_data_in(41) <= instr_vld ;
ELSIF ((rdy_i AND pipe_out_vld) = '1') THEN
pipe_data_in(41) <= '0' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
instr_vld_dly1 <= instr_vld;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0) = '1') THEN
rd_data_counts_asked <= (others => '0') ;
ELSIF (instr_vld_dly1 = '1' AND pipe_data_in(32) = '1') THEN
IF (pipe_data_in(40 DOWNTO 35) = "000000") THEN
rd_data_counts_asked <= rd_data_counts_asked + 64 ;
ELSE
rd_data_counts_asked <= rd_data_counts_asked + ('0' & (pipe_data_in(40 DOWNTO 35)));
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0) = '1') THEN
rd_data_received_counts <= (others => '0');
rd_data_received_counts_total <= (others => '0');
ELSIF (reading_rd_data_i = '1') THEN
rd_data_received_counts <= rd_data_received_counts + '1';
rd_data_received_counts_total <= rd_data_received_counts_total + "0000000000000001";
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
buf_avail_r <= (rd_data_received_counts + 64) - rd_data_counts_asked;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(3)) = '1') THEN
IF (CMD_PATTERN = "CGEN_BRAM") THEN
addr_mode_reg <= "000";
ELSE
addr_mode_reg <= "011";
END IF;
ELSIF (mode_load_pulse = '1') THEN
addr_mode_reg <= addr_mode_i;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (mode_load_pulse = '1') THEN
bl_mode_reg <= bl_mode_i;
END IF;
mode_load_d1 <= mode_load_i;
mode_load_d2 <= mode_load_d1;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
mode_load_pulse <= mode_load_d1 AND NOT(mode_load_d2);
END IF;
END PROCESS;
xhdl4 <= addr_mode_reg;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(3)) = '1') THEN
addr_out <= start_addr_i;
ELSE
CASE xhdl4 IS
WHEN "000" =>
addr_out <= bram_addr_i;
WHEN "001" =>
addr_out <= fixed_addr;
WHEN "010" =>
addr_out <= prbs_addr;
WHEN "011" =>
addr_out <= ("00" & seq_addr(29 DOWNTO 0));
WHEN "100" =>
-- addr_out <= (prbs_addr(31 DOWNTO 6) & "000000");
addr_out <= ("000" & seq_addr(6 DOWNTO 2) & seq_addr(23 DOWNTO 0));--(prbs_addr(31 DOWNTO 6) & "000000");
WHEN "101" =>
addr_out <= (prbs_addr(31 DOWNTO 20) & seq_addr(19 DOWNTO 0));
-- addr_out <= (prbs_addr(31 DOWNTO MEM_COL_WIDTH) & seq_addr(MEM_COL_WIDTH - 1 DOWNTO 0));
WHEN OTHERS =>
addr_out <= (others => '0');--"00000000000000000000000000000000";
END CASE;
END IF;
END IF;
END PROCESS;
xhdl5 : IF (CMD_PATTERN = "CGEN_PRBS" OR CMD_PATTERN = "CGEN_ALL") GENERATE
addr_prbs_gen : cmd_prbs_gen
GENERIC MAP (
family => FAMILY,
addr_width => 32,
dwidth => DWIDTH,
prbs_width => 32,
seed_width => 32,
prbs_eaddr_mask_pos => PRBS_EADDR_MASK_POS,
prbs_saddr_mask_pos => PRBS_SADDR_MASK_POS,
prbs_eaddr => PRBS_EADDR,
prbs_saddr => PRBS_SADDR
)
PORT MAP (
clk_i => clk_i,
clk_en => cmd_clk_en,
prbs_seed_init => mode_load_pulse,
prbs_seed_i => cmd_seed_i(31 DOWNTO 0),
prbs_o => prbs_addr
);
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (addr_out(31 DOWNTO 8) >= end_addr_i(31 DOWNTO 8)) THEN
gen_addr_larger <= '1';
ELSE
gen_addr_larger <= '0';
END IF;
END IF;
END PROCESS;
xhdl6 : IF (FAMILY = "SPARTAN6") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (mem_init_done = '1') THEN
INC_COUNTS <= std_logic_vector(to_unsigned((DWIDTH/8 * to_integer(unsigned(bl_out_reg))),11));
ELSE
IF (fixed_bl_i = "000000") THEN
INC_COUNTS <= std_logic_vector(to_unsigned((DWIDTH/8)*(64), 11));
ELSE
INC_COUNTS <= std_logic_vector(to_unsigned((DWIDTH/8 * to_integer(unsigned(fixed_bl_i))),11));
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
xhdl7 : IF (FAMILY = "VIRTEX6") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (NUM_DQ_PINS >= 128 AND NUM_DQ_PINS <= 144) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(64 * (MEM_BURST_LEN/4), 11));
ELSIF (NUM_DQ_PINS >= 64 AND NUM_DQ_PINS < 128) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(32 * (MEM_BURST_LEN/4), 11));
ELSIF (NUM_DQ_PINS >= 32 AND NUM_DQ_PINS < 64) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(16 * (MEM_BURST_LEN/4), 11));
ELSIF (NUM_DQ_PINS = 16 OR NUM_DQ_PINS = 24) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(8 * (MEM_BURST_LEN/4), 11));
ELSIF (NUM_DQ_PINS = 8 OR NUM_DQ_PINS = 9) THEN
INC_COUNTS <= std_logic_vector(to_unsigned(4 * (MEM_BURST_LEN/4), 11));
END IF;
END IF;
END PROCESS;
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
end_addr_r <= end_addr_i - std_logic_vector(to_unsigned(DWIDTH/8*to_integer(unsigned(fixed_bl_i)),32)) + "00000000000000000000000000000001";
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (addr_out(31 DOWNTO 24) >= end_addr_r(31 DOWNTO 24)) THEN
AC3_G_E3 <= '1';
ELSE
AC3_G_E3 <= '0';
END IF;
IF (addr_out(23 DOWNTO 16) >= end_addr_r(23 DOWNTO 16)) THEN
AC2_G_E2 <= '1';
ELSE
AC2_G_E2 <= '0';
END IF;
IF (addr_out(15 DOWNTO 8) >= end_addr_r(15 DOWNTO 8)) THEN
AC1_G_E1 <= '1';
ELSE
AC1_G_E1 <= '0';
END IF;
END IF;
END PROCESS;
-- xhdl8 : IF (CMD_PATTERN = "CGEN_SEQUENTIAL" OR CMD_PATTERN = "CGEN_ALL") GENERATE
seq_addr <= addr_counts;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
mode_load_pulse_r1 <= mode_load_pulse;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
end_addr_range <= end_addr_i(15 DOWNTO 0) - std_logic_vector(to_unsigned((DWIDTH/8 * to_integer(unsigned(bl_out_reg))),16)) + "0000000000000001";
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
addr_counts_next_r <= addr_counts + (INC_COUNTS);
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
cmd_clk_en_r <= cmd_clk_en;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
addr_counts <= start_addr_i;
mem_init_done <= '0';
ELSIF ((cmd_clk_en_r OR mode_load_pulse_r1) = '1') THEN
-- IF ((DWIDTH = 32 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND (addr_counts(7 DOWNTO 0) >= end_addr_r(7 DOWNTO 0))) OR (DWIDTH = 64 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND (addr_counts(7 DOWNTO 0) >= end_addr_r(7 DOWNTO 0))) OR ((DWIDTH = 128 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND FAMILY = "SPARTAN6") OR (DWIDTH = 128 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND (addr_counts(7 DOWNTO 0) >= end_addr_r(7 DOWNTO 0)) AND FAMILY = "VIRTEX6") OR (DWIDTH >= 256 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND (addr_counts(7 DOWNTO 0) >= end_addr_r(7 DOWNTO 0)) AND FAMILY = "VIRTEX6"))) THEN
IF (addr_counts_next_r >= end_addr_i) THEN
addr_counts <= start_addr_i;
mem_init_done <= '1';
ELSIF (addr_counts < end_addr_r) THEN
addr_counts <= addr_counts + INC_COUNTS;
END IF;
END IF;
END IF;
END PROCESS;
--END GENERATE;
xhdl9 : IF (CMD_PATTERN = "CGEN_FIXED" OR CMD_PATTERN = "CGEN_ALL") GENERATE
fixed_addr <= (fixed_addr_i(31 DOWNTO 2) & "00") WHEN (DWIDTH = 32) ELSE
(fixed_addr_i(31 DOWNTO 3) & "000") WHEN (DWIDTH = 64) ELSE
(fixed_addr_i(31 DOWNTO 4) & "0000") WHEN (DWIDTH = 128) ELSE
(fixed_addr_i(31 DOWNTO 5) & "00000") WHEN (DWIDTH = 256) ELSE
(fixed_addr_i(31 DOWNTO 6) & "000000");
END GENERATE;
xhdl10 : IF (CMD_PATTERN = "CGEN_BRAM" OR CMD_PATTERN = "CGEN_ALL") GENERATE
bram_rdy_o <= (run_traffic_i AND cmd_clk_en AND bram_valid_i) OR (mode_load_pulse);
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
force_rd_counts <= (others => '0');--"0000000000";
ELSIF (instr_vld = '1') THEN
force_rd_counts <= force_rd_counts + "0000000001";
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
force_rd <= '0';
ELSIF ((force_rd_counts(3)) = '1') THEN
force_rd <= '1';
ELSE
force_rd <= '0';
END IF;
END IF;
END PROCESS;
-- adding refresh timer to limit the amount of issuing refresh command.
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
refresh_timer <= (others => '0');
ELSE
refresh_timer <= refresh_timer + 1;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(4)) = '1') THEN
refresh_cmd_en <= '0';
ELSIF (refresh_timer = "1111111111") THEN
refresh_cmd_en <= '1';
ELSIF ((cmd_clk_en and refresh_cmd_en) = '1') THEN
refresh_cmd_en <= '0';
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (FAMILY = "SPARTAN6") THEN
refresh_prbs <= prbs_instr_b(3) and refresh_cmd_en;
ELSE
refresh_prbs <= '0';
END IF;
END IF;
END PROCESS;
--synthesis translate_off
PROCESS (instr_mode_i)
BEGIN
IF ((instr_mode_i > "0010") and (FAMILY = "VIRTEX6")) THEN
report "Error ! Not valid instruction mode";
END IF;
END PROCESS;
--synthesis translate_on
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
CASE instr_mode_i IS
WHEN "0000" =>
instr_out <= bram_instr_i;
WHEN "0001" =>
instr_out <= fixed_instr_i;
WHEN "0010" =>
instr_out <= ("00" & (prbs_instr_a(0) OR force_rd));
WHEN "0011" =>
instr_out <= ("00" & prbs_instr_a(0));
WHEN "0100" =>
instr_out <= ('0' & prbs_instr_b(0) & prbs_instr_a(0));
WHEN "0101" =>
instr_out <= (refresh_prbs & prbs_instr_b(0) & prbs_instr_a(0));
WHEN OTHERS =>
instr_out <= ("00" & prbs_instr_a(0));
END CASE;
END IF;
END PROCESS;
xhdl11 : IF (CMD_PATTERN = "CGEN_PRBS" OR CMD_PATTERN = "CGEN_ALL") GENERATE
instr_prbs_gen_a : cmd_prbs_gen
GENERIC MAP (
prbs_cmd => "INSTR",
family => FAMILY,
addr_width => 32,
seed_width => 15,
prbs_width => 20
)
PORT MAP (
clk_i => clk_i,
clk_en => cmd_clk_en,
prbs_seed_init => load_seed_i,
prbs_seed_i => cmd_seed_i(14 DOWNTO 0),
prbs_o => prbs_instr_a
);
instr_prbs_gen_b : cmd_prbs_gen
GENERIC MAP (
prbs_cmd => "INSTR",
family => FAMILY,
seed_width => 15,
prbs_width => 20
)
PORT MAP (
clk_i => clk_i,
clk_en => cmd_clk_en,
prbs_seed_init => load_seed_i,
prbs_seed_i => cmd_seed_i(16 DOWNTO 2),
prbs_o => prbs_instr_b
);
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (addr_out(31 DOWNTO 24) >= end_addr_i(31 DOWNTO 24)) THEN
A3_G_E3 <= '1' ;
ELSE
A3_G_E3 <= '0' ;
END IF;
IF (addr_out(23 DOWNTO 16) >= end_addr_i(23 DOWNTO 16)) THEN
A2_G_E2 <= '1' ;
ELSE
A2_G_E2 <= '0' ;
END IF;
IF (addr_out(15 DOWNTO 8) >= end_addr_i(15 DOWNTO 8)) THEN
A1_G_E1 <= '1' ;
ELSE
A1_G_E1 <= '0' ;
END IF;
IF (addr_out(7 DOWNTO 0) > (end_addr_i(7 DOWNTO 0) - std_logic_vector(to_unsigned((DWIDTH/8)*to_integer(unsigned(bl_out) ),32)) + '1') ) THEN -- OK
A0_G_E0 <= '1' ;
ELSE
A0_G_E0 <= '0' ;
END IF;
END IF;
END PROCESS;
--testout <= std_logic_vector(to_unsigned((DWIDTH/8)*to_integer(unsigned(bl_out) ),testout'length)) + '1';
PROCESS (addr_out,buf_avail_r, bl_out, end_addr_i, rst_i)
BEGIN
IF ((rst_i(5)) = '1') THEN
force_bl1 <= '0';
ELSIF (addr_out + std_logic_vector(to_unsigned((DWIDTH/8)*to_integer(unsigned(bl_out) ),32)) >= end_addr_i) OR
(buf_avail_r <= 50 and PORT_MODE = "RD_MODE") THEN
force_bl1 <= '1' ;
ELSE
force_bl1 <= '0' ;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(6)) = '1') THEN
bl_out_reg <= fixed_bl_i;
ELSIF (bl_out_vld = '1') THEN
bl_out_reg <= bl_out;
END IF;
END IF;
END PROCESS;
xhdl12 <= bl_mode_reg;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (mode_load_pulse = '1') THEN
bl_out <= fixed_bl_i;
ELSIF (cmd_clk_en = '1') THEN
CASE xhdl12 IS
WHEN "00" =>
bl_out <= bram_bl_i;
WHEN "01" =>
bl_out <= fixed_bl_i;
WHEN "10" =>
bl_out <= prbs_brlen;
WHEN OTHERS =>
bl_out <= "000001";
END CASE;
END IF;
END IF;
END PROCESS;
--synthesis translate_off
PROCESS (bl_out)
BEGIN
IF (bl_out > "000010" AND FAMILY = "VIRTEX6") THEN
report "Error ! Not valid burst length"; --severity ERROR;
END IF;
END PROCESS;
--synthesis translate_on
xhdl13 : IF (CMD_PATTERN = "CGEN_PRBS" OR CMD_PATTERN = "CGEN_ALL") GENERATE
bl_prbs_gen : cmd_prbs_gen
GENERIC MAP (
TCQ => TCQ,
family => FAMILY,
prbs_cmd => "BLEN",
addr_width => 32,
seed_width => 15,
prbs_width => 20
)
PORT MAP (
clk_i => clk_i,
clk_en => cmd_clk_en,
prbs_seed_init => load_seed_i,
prbs_seed_i => cmd_seed_i(16 DOWNTO 2),
prbs_o => prbs_bl
);
END GENERATE;
-- xhdl14 <= "000001" WHEN (prbs_bl(5 DOWNTO 0) = "000000") ELSE prbs_bl(5 DOWNTO 0);
PROCESS (prbs_bl) BEGIN
IF (FAMILY = "SPARTAN6") THEN
if (prbs_bl(5 DOWNTO 0) = "000000") then
-- prbs_brlen <= xhdl14;
prbs_brlen <= "000001";
else
prbs_brlen <= prbs_bl(5 DOWNTO 0);
end if;
ELSE
prbs_brlen <= "000010";
END IF;
END PROCESS;
END trans;
|
bsd-2-clause
|
mithro/HDMI2USB
|
ipcore_dir/bytefifo/simulation/bytefifo_synth.vhd
|
3
|
11598
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bytefifo_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY work;
USE work.bytefifo_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY bytefifo_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF bytefifo_synth IS
-- FIFO interface signal declarations
SIGNAL wr_clk_i : STD_LOGIC;
SIGNAL rd_clk_i : STD_LOGIC;
SIGNAL almost_full : STD_LOGIC;
SIGNAL almost_empty : STD_LOGIC;
SIGNAL rst : STD_LOGIC;
SIGNAL prog_full : STD_LOGIC;
SIGNAL overflow : STD_LOGIC;
SIGNAL underflow : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(8-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(8-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(8-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(8-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_s_wr1 : STD_LOGIC := '0';
SIGNAL rst_s_wr2 : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_wr1 : STD_LOGIC := '0';
SIGNAL rst_async_wr2 : STD_LOGIC := '0';
SIGNAL rst_async_wr3 : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_wr3 OR rst_s_wr3;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(rd_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
PROCESS(wr_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_wr1 <= '1';
rst_async_wr2 <= '1';
rst_async_wr3 <= '1';
ELSIF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_async_wr1 <= RESET;
rst_async_wr2 <= rst_async_wr1;
rst_async_wr3 <= rst_async_wr2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(rd_clk_i)
BEGIN
IF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(wr_clk_i)
BEGIN
IF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_s_wr1 <= rst_s_rd;
rst_s_wr2 <= rst_s_wr1;
rst_s_wr3 <= rst_s_wr2;
IF(rst_s_wr3 = '1' AND rst_s_wr2 = '0') THEN
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
wr_clk_i <= WR_CLK;
rd_clk_i <= RD_CLK;
------------------
rst <= RESET OR rst_s_rd AFTER 12 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
almost_empty_i <= almost_empty;
almost_full_i <= almost_full;
fg_dg_nv: bytefifo_dgen
GENERIC MAP (
C_DIN_WIDTH => 8,
C_DOUT_WIDTH => 8,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => wr_clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: bytefifo_dverif
GENERIC MAP (
C_DOUT_WIDTH => 8,
C_DIN_WIDTH => 8,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => rd_clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: bytefifo_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 8,
C_DIN_WIDTH => 8,
C_WR_PNTR_WIDTH => 10,
C_RD_PNTR_WIDTH => 10,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
bytefifo_inst : bytefifo_exdes
PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
ALMOST_FULL => almost_full,
ALMOST_EMPTY => almost_empty,
RST => rst,
PROG_FULL => prog_full,
OVERFLOW => overflow,
UNDERFLOW => underflow,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
|
bsd-2-clause
|
mithro/HDMI2USB
|
hdl/misc/image_selector.vhd
|
3
|
11357
|
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
Library UNISIM;
use UNISIM.vcomponents.all;
entity image_selector is
port
(
-- HMDI input 0
rgb_H0 : in std_logic_vector(23 downto 0);
de_H0 : in std_logic;
pclk_H0 : in std_logic;
hsync_H0 : in std_logic;
vsync_H0 : in std_logic;
resX_H0 : in std_logic_vector(15 downto 0);
resY_H0 : in std_logic_vector(15 downto 0);
-- HMDI input 1
rgb_H1 : in std_logic_vector(23 downto 0);
de_H1 : in std_logic;
pclk_H1 : in std_logic;
hsync_H1 : in std_logic;
vsync_H1 : in std_logic;
resX_H1 : in std_logic_vector(15 downto 0);
resY_H1 : in std_logic_vector(15 downto 0);
-- Test Pattern
rgb_tp : in std_logic_vector(23 downto 0);
de_tp : in std_logic;
pclk_tp : in std_logic;
hsync_tp : in std_logic;
vsync_tp : in std_logic;
resX_tp : in std_logic_vector(15 downto 0);
resY_tp : in std_logic_vector(15 downto 0);
-- VGA input
rgb_vga : in std_logic_vector(23 downto 0);
de_vga : in std_logic;
pclk_vga : in std_logic;
hsync_vga : in std_logic;
vsync_vga : in std_logic;
resX_vga : in std_logic_vector(15 downto 0);
resY_vga : in std_logic_vector(15 downto 0);
-- selector_cmd
selector_cmd : in std_logic_vector(12 downto 0);
--Heart Beat Signals
HB_on : in std_logic; -- Port control of heart beat
HB_sw : in std_logic; -- Switch Control of heart beat
-- selected output
rgb : out std_logic_vector(23 downto 0);
de : out std_logic;
hsync : out std_logic;
vsync : out std_logic;
resX : out std_logic_vector(15 downto 0);
resY : out std_logic_vector(15 downto 0);
-- for HDMI Matrix input
rgb_H : out std_logic_vector(23 downto 0);
de_H : out std_logic;
pclk_H : out std_logic;
clk : in std_logic;
rst : in std_logic
);
end entity image_selector;
architecture rtl of image_selector is
COMPONENT image_selector_fifo
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT heart_beater is
Generic( HB_length : integer :=5; --length of the heart beat in pixels
HB_width : integer :=5; --width of the heart beat in pixels
alt_aft_frame : integer :=3 --alternate color after this many frames (max value 31)
);
PORT
(
clk : in std_logic;
rst : in std_logic;
HB_on : in std_logic;
HB_sw : in std_logic;
din : in std_logic_vector(23 downto 0);
vsync : in std_logic;
wr_en : in std_logic;
pclk_i : in std_logic;
resX : in std_logic_vector(15 downto 0);
resY : in std_logic_vector(15 downto 0);
dout : out std_logic_vector(23 downto 0)
);
END COMPONENT;
signal pclk_i : std_logic;
signal hdmi_clk : std_logic;
--signal vga_tp_clk : std_logic;
signal full : std_logic;
signal almost_full : std_logic;
signal empty : std_logic;
signal almost_empty : std_logic;
signal valid : std_logic;
signal de_q : std_logic;
signal de_qq : std_logic;
signal de_qqq : std_logic;
signal de_qqqq : std_logic;
signal de_qqqqq : std_logic;
signal de_i : std_logic;
signal rgb_q : std_logic_vector(23 downto 0);
signal rgb_i : std_logic_vector(23 downto 0);
signal din : std_logic_vector(23 downto 0);
signal din_q : std_logic_vector(23 downto 0);
signal Y : std_logic_vector(17 downto 0);
signal Y1 : std_logic_vector(14 downto 0);
signal Y2 : std_logic_vector(16 downto 0);
signal Y3 : std_logic_vector(17 downto 0);
signal red_i : std_logic_vector(7 downto 0);
signal green_i : std_logic_vector(7 downto 0);
signal blue_i : std_logic_vector(7 downto 0);
signal red_q : std_logic_vector(7 downto 0);
signal green_q : std_logic_vector(7 downto 0);
signal blue_q : std_logic_vector(7 downto 0);
signal red_qq : std_logic_vector(7 downto 0);
signal green_qq : std_logic_vector(7 downto 0);
signal blue_qq : std_logic_vector(7 downto 0);
signal red_qqq : std_logic_vector(7 downto 0);
signal green_qqq : std_logic_vector(7 downto 0);
signal blue_qqq : std_logic_vector(7 downto 0);
signal selector : std_logic_vector(12 downto 0);
signal wr_en : std_logic;
signal de_H0_q : std_logic;
signal rgb_H0_q : std_logic_vector(23 downto 0);
signal hsync_H0_q : std_logic;
signal vsync_H0_q : std_logic;
signal resX_H0_q : std_logic_vector(15 downto 0);
signal resY_H0_q : std_logic_vector(15 downto 0);
signal rgb_H1_q : std_logic_vector(23 downto 0);
signal hsync_H1_q : std_logic;
signal de_H1_q : std_logic;
signal vsync_H1_q : std_logic;
signal resX_H1_q : std_logic_vector(15 downto 0);
signal resY_H1_q : std_logic_vector(15 downto 0);
signal rgb_tp_q : std_logic_vector(23 downto 0);
signal de_tp_q : std_logic;
signal hsync_tp_q : std_logic;
signal vsync_tp_q : std_logic;
signal resX_tp_q : std_logic_vector(15 downto 0);
signal resY_tp_q : std_logic_vector(15 downto 0);
signal resX_signal : std_logic_vector(15 downto 0);
signal resY_signal : std_logic_vector(15 downto 0);
signal vsync_s : std_logic;
begin
pclk_H <= pclk_i;--clk input to HDMI Matrix
resX <= resX_signal;
resY <= resY_signal;
process(rst,pclk_H0)
begin
if rst = '1' then
elsif rising_edge(pclk_H0) then
rgb_H0_q <=rgb_H0;
de_H0_q <= de_H0;
hsync_H0_q <= hsync_H0;
vsync_H0_q <= vsync_H0;
resX_H0_q <= resX_H0;
resY_H0_q <= resY_H0;
end if;
end process;
process(rst,pclk_H1)
begin
if rst = '1' then
elsif rising_edge(pclk_H1) then
rgb_H1_q <= rgb_H1;
de_H1_q <= de_H1;
hsync_H1_q <= hsync_H1;
vsync_H1_q <= vsync_H1;
resX_H1_q <= resX_H1;
resY_H1_q <= resY_H1;
end if;
end process;
process(rst,pclk_tp)
begin
if rst = '1' then
elsif rising_edge(pclk_tp) then
rgb_tp_q <= rgb_tp;
de_tp_q <= de_tp;
hsync_tp_q <= hsync_tp;
vsync_tp_q <= vsync_tp;
resX_tp_q <= resX_tp;
resY_tp_q <= resY_tp;
end if;
end process;
process(rst,pclk_i)
begin
if rst = '1' then
valid <= '0';
rgb_i <= (others => '0');
hsync <= '0';
vsync <= '0';
resX_signal <= (others => '0');
resY_signal <= (others => '0');
selector <= (others => '0');
elsif rising_edge(pclk_i) then
selector <= selector_cmd;
case selector(1 downto 0) is
when "00" => -- hdmi 0
rgb_i <= rgb_H0_q;
de_i <= de_H0_q;
hsync <= hsync_H0_q;
vsync <= vsync_H0_q;
resX_signal <= resX_H0_q;
resY_signal <= resY_H0_q;
vsync_s <= vsync_H0_q;
when "01" => -- hdmi 1
rgb_i <= rgb_H1_q;
de_i <= de_H1_q;
hsync <= hsync_H1_q;
vsync <= vsync_H1_q;
resX_signal <= resX_H1_q;
resY_signal <= resY_H1_q;
vsync_s <= vsync_H1_q;
-- when "10" => -- VGA
-- rgb_i <= rgb_vga_q;
-- valid <= de_vga_q;
-- hsync <= hsync_vga_q;
-- vsync <= vsync_vga_q;
-- resX_signal <= resX_vga_q;
-- resY_signal <= resY_vga_q;
when "11" => -- Test Pattern
rgb_i <= rgb_tp_q;
de_i <= de_tp_q;
hsync <= hsync_tp_q;
vsync <= vsync_tp_q;
resX_signal <= resX_tp_q;
resY_signal <= resY_tp_q;
vsync_s <= vsync_tp_q;
when others =>
end case;
end if;
end process;
BUFGMUX_HDMI : BUFGMUX
generic map (
CLK_SEL_TYPE => "SYNC" -- Glitchles ("SYNC") or fast ("ASYNC") clock switch-over
)
port map (
O => hdmi_clk, -- 1-bit output: Clock buffer output
I0 => pclk_H0, -- 1-bit input: Clock buffer input (S=0)
I1 => pclk_H1, -- 1-bit input: Clock buffer input (S=1)
S => selector_cmd(0) -- 1-bit input: Clock buffer select
);
-- BUFGMUX_VGATP : BUFGMUX
-- generic map (
-- CLK_SEL_TYPE => "SYNC" -- Glitchles ("SYNC") or fast ("ASYNC") clock switch-over
-- )
-- port map (
-- O => vga_tp_clk, -- 1-bit output: Clock buffer output
-- I0 => pclk_vga, -- 1-bit input: Clock buffer input (S=0)
-- I1 => pclk_tp, -- 1-bit input: Clock buffer input (S=1)
-- S => selector_q(0) -- 1-bit input: Clock buffer select
-- );
BUFGMUX_PCLK : BUFGMUX
generic map (
CLK_SEL_TYPE => "SYNC" -- Glitchles ("SYNC") or fast ("ASYNC") clock switch-over
)
port map (
O => pclk_i, -- 1-bit output: Clock buffer output
I0 => hdmi_clk, -- 1-bit input: Clock buffer input (S=0)
I1 => pclk_tp, -- 1-bit input: Clock buffer input (S=1)
S => selector_cmd(1) -- 1-bit input: Clock buffer select
);
Y <= Y1 + Y2 + Y3;
rgb_H <= din_q;
de_H <= wr_en;
imgprocess: process(rst,pclk_i)
begin
if rst = '1' then
rgb_q <= (others => '0');
elsif rising_edge(pclk_i) then
Y1 <= conv_std_logic_vector(113,7)*blue_qqq;
Y2 <= conv_std_logic_vector(307,9)*red_qqq;
Y3 <= conv_std_logic_vector(604,10)*green_qqq;
rgb_q <= (blue_i & green_i & red_i);
din <= rgb_q;
wr_en <= de_qqqqq;
de_q <= de_i;
de_qq <= de_q;
de_qqq <= de_qq;
de_qqqq <= de_qqq;
de_qqqqq<= de_qqqq;
if selector(10) = '1' then blue_q <= rgb_i(23 downto 16); else blue_q <= (others => '0'); end if;
if selector(11) = '1' then green_q <= rgb_i(15 downto 8); else green_q <= (others => '0'); end if;
if selector(12) = '1' then red_q <= rgb_i(7 downto 0); else red_q <= (others => '0'); end if;
case selector(5 downto 4) is -- blue
when "00" => blue_qq <= blue_q;
when "01" => blue_qq <= (blue_q(7 downto 3) & "000");
when "10" => blue_qq <= (blue_q(7 downto 4) & "0000");
when "11" => blue_qq <= (blue_q(7 downto 5) & "00000");
when others =>
end case;
case selector(7 downto 6) is -- green
when "00" => green_qq <= green_q;
when "01" => green_qq <= (green_q(7 downto 3) & "000");
when "10" => green_qq <= (green_q(7 downto 4) & "0000");
when "11" => green_qq <= (green_q(7 downto 5) & "00000");
when others =>
end case;
case selector(9 downto 8) is -- red
when "00" => red_qq <= red_q;
when "01" => red_qq <= (red_q(7 downto 3) & "000");
when "10" => red_qq <= (red_q(7 downto 4) & "0000");
when "11" => red_qq <= (red_q(7 downto 5) & "00000");
when others =>
end case;
if selector(3) = '1' then
blue_qqq <= ("11111111" - blue_qq);
green_qqq <= ("11111111" - green_qq);
red_qqq <= ("11111111" - red_qq);
else
blue_qqq <= blue_qq;
green_qqq <= green_qq;
red_qqq <= red_qq;
end if;
if selector(2) = '1' then
blue_i <= blue_qqq;
green_i <= green_qqq;
red_i <= red_qqq;
else
blue_i <= Y(17 downto 10);
green_i <= Y(17 downto 10);
red_i <= Y(17 downto 10);
end if;
end if;-- clk
end process; -- imgprocess
selector_fifo : image_selector_fifo
PORT MAP (
rst => rst,
wr_clk => pclk_i,
rd_clk => clk,
din => din_q,
wr_en => wr_en,
rd_en => '1',
dout => rgb,
full => full,
almost_full => almost_full,
empty => empty,
almost_empty => almost_empty,
valid => de
);
Inst_heart_beater: heart_beater
GENERIC MAP (
HB_length => 5,-- length of heart beat in pixel
HB_width => 5,-- width of heart beat in pixel
alt_aft_frame=>30 --the color alternates after this many frames
)
PORT MAP(
clk => clk,
rst =>rst ,
HB_on => HB_on,
HB_sw => HB_sw,
din => din,
wr_en => wr_en,
vsync => vsync_s,
pclk_i => pclk_i,
resX => resX_signal,
resY => resY_signal,
dout => din_q
);
end architecture;
|
bsd-2-clause
|
Alix82/mip32vhdl
|
decoder.vhd
|
1
|
4769
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use ieee.std_logic_unsigned.all;
library work;
use work.mips_constants.all;
Entity decoder is
port(clk : in std_logic;
instruction : in std_logic_vector(31 downto 0);
pcD : in std_logic_vector(31 downto 0);
discard : in std_logic;
decoded : out std_logic_vector(11 downto 0);
opcode : out std_logic_vector(5 downto 0);
func : out std_logic_vector(5 downto 0);
shamt : out std_logic_vector(4 downto 0);
pcF : out std_logic_vector(31 downto 0);
Reg1 : out std_logic_vector(4 downto 0);
Reg2 : out std_logic_vector(4 downto 0);
Reg3 : out std_logic_vector(4 downto 0);
Fetch : out std_logic
);
End decoder;
Architecture rtl of decoder is
signal n_decoded : integer := 0;
begin
process (clk)
Variable decoded_o : std_logic_vector (7 downto 0);
Variable op : std_logic_vector(5 downto 0);
Variable lfunc : std_logic_vector(5 downto 0);
Variable control_o : std_logic_vector(11 downto 0);
Variable read_reg: std_logic;
Variable instructionlocal : std_logic_vector(31 downto 0);
begin
if rising_edge(clk) then
instructionlocal := X"00000000";
Fetch <= not discard;
instructionlocal := Instruction;
lfunc := instructionlocal(5 downto 0);
op := instructionlocal(31 downto 26);
control_o := "000000000000";
read_reg := '0';
-- linkbit := '0';
case op is
when "000010" => control_o := "010000000000"; -- J label
when "000011" => control_o := "010000000010"; read_reg := '1'; -- JAL label
when "000000" =>
case lfunc is
when "001000" => control_o := "010000000001"; -- JR
when "010000" => control_o := "000001001000"; -- MFHI
when "010010" => control_o := "000001001000"; -- MFLO
when "100100" => control_o := "100001001000"; read_reg:='1'; -- add/addu, and/andu
when "100000" => control_o := "100001001000"; read_reg:='1'; -- add/addu, and/andu
when "100001" => control_o := "100001001000"; read_reg:='1'; -- add/addu, and/andu
when others => control_o := "000000000000";
end case;
when "001000" => control_o := "100001011000"; read_reg:='1'; -- addi
when "001001" => control_o := "000001011000"; read_reg:='1'; -- addiu
when "101011" => control_o := "000001110000"; read_reg:='1'; -- SW
when "100011" => control_o := "000111011000"; read_reg:='1'; -- LW
when "101000" => control_o := "000001110000"; read_reg:='1'; -- SB
when "100000" => control_o := "000111011000"; read_reg:='1'; -- LB
when "001111" => control_o := "000001011000"; read_reg:='1'; -- LUI
when "001110" => control_o := "000001011000"; read_reg:='1'; -- XORI
when "001101" => control_o := "000001011000"; read_reg:='1'; -- ORI
when "000101" => control_o := "001001000000"; read_reg:='1'; -- BNE
when "000100" => control_o := "001001000000"; read_reg:='1'; -- BEQ
when "000001" =>
if instructionlocal(20) = '1' then
control_o := "001001000110"; read_reg:='1'; -- BGEZAL/BLTZAL
else
control_o := "001001000100"; read_reg:='1'; -- BGEZ/BLTZ
end if;
when "000111" => control_o := "001001000100"; read_reg:='1';-- BGTZ
when "000110" => control_o := "001001000100"; read_reg:='1';-- BGTZ
when others => control_o := "000000000000"; --error := '1';
end case;
--prevregwrite <= control_o(3);
decoded <= control_o;
n_decoded <= n_decoded + 1;
opcode <= op;
func <= lfunc;
shamt <= instructionlocal(10 downto 6);
reg1 <= instructionlocal(25 downto 21);
reg2 <= instructionlocal(20 downto 16);
reg3 <= instructionlocal(15 downto 11);
pcF <= pcD;
end if;
end process;
end;
|
bsd-2-clause
|
lowRISC/greth-library
|
greth_library/techmap/gencomp/gencomp.vhd
|
2
|
5253
|
-----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - [email protected]
--! @brief Definition of the gencomp package.
--! @details This file defines constants that are used to enable/disable
--! target dependable modules.
--! This file inherits values from the \e grlib library that
--! that are published under GPL license. All unused values may
--! freely removed or reassigned on others values.
------------------------------------------------------------------------------
--! Standard library
library ieee;
use ieee.std_logic_1164.all;
--! @brief Technologies names definition
--! @details This package must be built first in a case of manual compilation
--! order (\e ModelSim).
package gencomp is
--! @brief Total number of the known technologies.
--! @details These values was inherited from the \e grlib library.
constant NTECH : integer := 53;
--! Prototype of the data type for mapping name on certain index.
type tech_ability_type is array (0 to NTECH) of integer;
--! @name Techologies names.
--! @brief Set of the predefined technology names.
--! @{
constant inferred : integer := 0; --! Behaviour simulation target.
constant virtex : integer := 1; --! Not implemented.
constant virtex2 : integer := 2; --! Not implemented.
constant memvirage : integer := 3; --! Not implemented.
constant axcel : integer := 4; --! Not implemented.
constant proasic : integer := 5; --! Not implemented.
constant atc18s : integer := 6; --! Not implemented.
constant altera : integer := 7; --! Not implemented.
constant umc : integer := 8; --! Not implemented.
constant rhumc : integer := 9; --! Not implemented.
constant apa3 : integer := 10; --! Not implemented.
constant spartan3 : integer := 11; --! Not implemented.
constant ihp25 : integer := 12; --! Not implemented.
constant rhlib18t : integer := 13; --! Not implemented.
constant virtex4 : integer := 14; --! Not implemented.
constant lattice : integer := 15; --! Not implemented.
constant ut25 : integer := 16; --! Not implemented.
constant spartan3e : integer := 17; --! Not implemented.
constant peregrine : integer := 18; --! Not implemented.
constant memartisan : integer := 19; --! Not implemented.
constant virtex5 : integer := 20; --! Not implemented.
constant custom1 : integer := 21; --! Not implemented.
constant ihp25rh : integer := 22; --! Not implemented.
constant stratix1 : integer := 23; --! Not implemented.
constant stratix2 : integer := 24; --! Not implemented.
constant eclipse : integer := 25; --! Not implemented.
constant stratix3 : integer := 26; --! Not implemented.
constant cyclone3 : integer := 27; --! Not implemented.
constant memvirage90 : integer := 28; --! Not implemented.
constant tsmc90 : integer := 29; --! Not implemented.
constant easic90 : integer := 30; --! Not implemented.
constant atc18rha : integer := 31; --! Not implemented.
constant smic013 : integer := 32; --! Not implemented.
constant tm65gpl : integer := 33; --! Not implemented.
constant axdsp : integer := 34; --! Not implemented.
constant spartan6 : integer := 35; --! Supported. Use files with the '_s6' suffix.
constant virtex6 : integer := 36; --! Supported. Use files with the '_v6' suffix.
constant actfus : integer := 37; --! Not implemented.
constant stratix4 : integer := 38; --! Not implemented.
constant st65lp : integer := 39; --! Not implemented.
constant st65gp : integer := 40; --! Not implemented.
constant easic45 : integer := 41; --! Not implemented.
constant cmos9sf : integer := 42; --! Not implemented.
constant apa3e : integer := 43; --! Not implemented.
constant apa3l : integer := 44; --! Not implemented.
constant ut130 : integer := 45; --! Not implemented.
constant ut90 : integer := 46; --! Not implemented.
constant gf65 : integer := 47; --! Not implemented.
constant virtex7 : integer := 48; --! Not implemented.
constant kintex7 : integer := 49; --! Supported. Use files with the '_k7' suffix.
constant artix7 : integer := 50; --! Partially implemented.
constant zynq7000 : integer := 51; --! Not implemented.
constant rhlib13t : integer := 52; --! Not implemented.
constant micron180 : integer := 53; --! Mikron 180nm. Use files with the '_micron180' suffix.
--! @}
--! @name FPGAs technologies group.
--! @details It is convinient sometimes to implement one module for a group of
--! technologies, this array specifies FPGA group.
constant is_fpga : tech_ability_type :=
(inferred => 1, virtex => 1, virtex2 => 1, axcel => 1,
proasic => 1, altera => 1, apa3 => 1, spartan3 => 1,
virtex4 => 1, lattice => 1, spartan3e => 1, virtex5 => 1,
stratix1 => 1, stratix2 => 1, eclipse => 1,
stratix3 => 1, cyclone3 => 1, axdsp => 1,
spartan6 => 1, virtex6 => 1, actfus => 1,
stratix4 => 1, apa3e => 1, apa3l => 1, virtex7 => 1, kintex7 => 1,
artix7 => 1, zynq7000 => 1,
others => 0);
end;
|
bsd-2-clause
|
lowRISC/greth-library
|
greth_library/techmap/pll/SysPLL_micron180.vhd
|
2
|
920
|
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1____70.000
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
entity SysPLL_micron180 is
port
(
CLK_IN1_P : in std_logic;
CLK_IN1_N : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic;
CLK_OUT2 : out std_logic;
-- Status and control signals
RESET : in std_logic;
LOCKED : out std_logic
);
end SysPLL_micron180;
architecture rtl of SysPLL_micron180 is
begin
CLK_OUT1 <= CLK_IN1_P;
LOCKED <= not RESET;
end rtl;
|
bsd-2-clause
|
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