repo_name
stringlengths 6
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stringlengths 5
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stringclasses 54
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stringlengths 1
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stringlengths 0
1.04M
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stringclasses 15
values |
|---|---|---|---|---|---|
sakolkar/4BitSorter
|
Synopsis/sorter.vhd
|
1
|
3047
|
----------------------------------------------------------
-- EE453 Lab3 Tutorial - 4 Unsigned 4-Bit Inputs Bubble Sorter
-- Khaled Al-Amoodi
-- Top level: sorter
-- Sorts 4 unsigned 4-bit inputs (A-D) so that S1 is largest
-- and S4 is smallest.
----------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY sorter IS
Port (
Clk : IN STD_LOGIC;
A : IN STD_LOGIC_VECTOR(3 downto 0);
B : IN STD_LOGIC_VECTOR(3 downto 0);
C : IN STD_LOGIC_VECTOR(3 downto 0);
D : IN STD_LOGIC_VECTOR(3 downto 0);
S1reg : OUT STD_LOGIC_VECTOR(3 downto 0);
S2reg : OUT STD_LOGIC_VECTOR(3 downto 0);
S3reg : OUT STD_LOGIC_VECTOR(3 downto 0);
S4reg : OUT STD_LOGIC_VECTOR(3 downto 0)
);
END sorter;
architecture RTL of sorter is
-- Internal Signal Declaration
signal Areg : std_logic_vector(3 downto 0);
signal Breg : std_logic_vector(3 downto 0);
signal Creg : std_logic_vector(3 downto 0);
signal Dreg : std_logic_vector(3 downto 0);
signal S1 : std_logic_vector(3 downto 0);
signal S2 : std_logic_vector(3 downto 0);
signal S3 : std_logic_vector(3 downto 0);
signal S4 : std_logic_vector(3 downto 0);
-- Temporary signals within stages
signal T1_1, T1_2, T2_1, T2_2, T3_1, T3_2 : std_logic_vector(3 downto 0);
-- Signals between stages 1 and 2
signal O1_A, O1_B, O1_C, O1_D : std_logic_vector(3 downto 0);
-- Signals between stages 3 and 4
signal O2_A, O2_B, O2_C, O2_D : std_logic_vector(3 downto 0);
signal R1_A, R1_B, R1_C, R1_D : std_logic_vector(3 downto 0);
signal R2_A, R2_B, R2_C, R2_D : std_logic_vector(3 downto 0);
begin -- RTL
process (Clk)
begin -- process
if rising_edge(Clk) then
Areg <= A;
Breg <= B;
Creg <= C;
Dreg <= D;
R1_A <= O1_A;
R1_B <= O1_B;
R1_C <= O1_C;
R1_D <= O1_D;
R2_A <= O2_A;
R2_B <= O2_B;
R2_C <= O2_C;
R2_D <= O2_D;
S1reg <= S1;
S2reg <= S2;
S3reg <= S3;
S4reg <= S4;
end if;
end process;
-- Stage 1
O1_A <= Breg when (Areg < Breg) else Areg;
T1_1 <= Areg when (Areg < Breg) else Breg;
O1_B <= Creg when (T1_1 < Creg) else T1_1;
T1_2 <= T1_1 when (T1_1 < Creg) else Creg;
O1_C <= Dreg when (T1_2 < Dreg) else T1_2;
O1_D <= T1_2 when (T1_2 < Dreg) else Dreg;
-- Stage 2
O2_A <= R1_B when (R1_A < R1_B) else R1_A;
T2_1 <= R1_A when (R1_A < R1_B) else R1_B;
O2_B <= R1_C when (T2_1 < R1_C) else T2_1;
T2_2 <= T2_1 when (T2_1 < R1_C) else R1_C;
O2_C <= R1_D when (T2_2 < R1_D) else T2_2;
O2_D <= T2_2 when (T2_2 < R1_D) else R1_D;
-- Stage 3
S1 <= R2_B when (R2_A < R2_B) else R2_A;
T3_1 <= R2_A when (R2_A < R2_B) else R2_B;
S2 <= R2_C when (T3_1 < R2_C) else T3_1;
T3_2 <= T3_1 when (T3_1 < R2_C) else R2_C;
S3 <= R2_D when (T3_2 < R2_D) else T3_2;
S4 <= T3_2 when (T3_2 < R2_D) else R2_D;
END RTL;
|
apache-2.0
|
alainmarcel/Surelog
|
third_party/tests/ariane/fpga/src/apb_uart/src/slib_counter.vhd
|
5
|
2883
|
--
-- Counter
--
-- Author: Sebastian Witt
-- Date: 27.01.2008
-- Version: 1.2
--
-- This code is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the
-- Free Software Foundation, Inc., 59 Temple Place, Suite 330,
-- Boston, MA 02111-1307 USA
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;
-- Counter
entity slib_counter is
generic (
WIDTH : natural := 4 -- Counter width
);
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
CLEAR : in std_logic; -- Clear counter register
LOAD : in std_logic; -- Load counter register
ENABLE : in std_logic; -- Enable count operation
DOWN : in std_logic; -- Count direction down
D : in std_logic_vector(WIDTH-1 downto 0); -- Load counter register input
Q : out std_logic_vector(WIDTH-1 downto 0); -- Shift register output
OVERFLOW : out std_logic -- Counter overflow
);
end slib_counter;
architecture rtl of slib_counter is
signal iCounter : unsigned(WIDTH downto 0); -- Counter register
begin
-- Counter process
COUNT_SHIFT: process (RST, CLK)
begin
if (RST = '1') then
iCounter <= (others => '0'); -- Reset counter register
elsif (CLK'event and CLK='1') then
if (CLEAR = '1') then
iCounter <= (others => '0'); -- Clear counter register
elsif (LOAD = '1') then -- Load counter register
iCounter <= unsigned('0' & D);
elsif (ENABLE = '1') then -- Enable counter
if (DOWN = '0') then -- Count up
iCounter <= iCounter + 1;
else -- Count down
iCounter <= iCounter - 1;
end if;
end if;
if (iCounter(WIDTH) = '1') then -- Clear overflow
iCounter(WIDTH) <= '0';
end if;
end if;
end process;
-- Output ports
Q <= std_logic_vector(iCounter(WIDTH-1 downto 0));
OVERFLOW <= iCounter(WIDTH);
end rtl;
|
apache-2.0
|
alainmarcel/Surelog
|
third_party/tests/YosysTests/verific/vhdl/top.vhd
|
2
|
862
|
library ieee;
use ieee.std_logic_1164.all;
library foo;
use foo.foo_m;
library bar;
use bar.bar_m;
entity top is
port (
clock : in std_logic;
a : in std_logic;
b : in std_logic;
x : out std_logic;
y : out std_logic
);
end entity;
architecture rtl of top is
component foo_m is
port (
clock : in std_logic;
a : in std_logic;
b : in std_logic;
x : out std_logic;
y : out std_logic
);
end component;
component bar_m is
port (
clock : in std_logic;
a : in std_logic;
b : in std_logic;
x : out std_logic;
y : out std_logic
);
end component;
signal t1, t2 : std_logic;
begin
foo_inst : foo_m port map (
clock => clock,
a => a,
b => b,
x => t1,
y => t2
);
bar_inst : bar_m port map (
clock => clock,
a => t1,
b => t2,
x => x,
y => y
);
end architecture;
|
apache-2.0
|
alainmarcel/Surelog
|
third_party/tests/ariane/fpga/src/apb_uart/src/apb_uart.vhd
|
2
|
51558
|
--
-- UART 16750
--
-- Author: Sebastian Witt
-- Date: 29.01.2008
-- Version: 1.5
--
-- History: 1.0 - Initial version
-- 1.1 - THR empty interrupt register connected to RST
-- 1.2 - Registered outputs
-- 1.3 - Automatic flow control
-- 1.4 - De-assert IIR FIFO64 when FIFO is disabled
-- 1.5 - Inverted low active outputs when RST is active
--
--
-- This code is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the
-- Free Software Foundation, Inc., 59 Temple Place, Suite 330,
-- Boston, MA 02111-1307 USA
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;
-- Serial UART
entity apb_uart is
port (
CLK : in std_logic; -- Clock
RSTN : in std_logic; -- Reset negated
PSEL : in std_logic; -- APB psel signal
PENABLE : in std_logic; -- APB penable signal
PWRITE : in std_logic; -- APB pwrite signal
PADDR : in std_logic_vector(2 downto 0); -- APB paddr signal
PWDATA : in std_logic_vector(31 downto 0); -- APB pwdata signal
PRDATA : out std_logic_vector(31 downto 0); -- APB prdata signal
PREADY : out std_logic; -- APB pready signal
PSLVERR : out std_logic; -- APB pslverr signal
INT : out std_logic; -- Interrupt output
OUT1N : out std_logic; -- Output 1
OUT2N : out std_logic; -- Output 2
RTSN : out std_logic; -- RTS output
DTRN : out std_logic; -- DTR output
CTSN : in std_logic; -- CTS input
DSRN : in std_logic; -- DSR input
DCDN : in std_logic; -- DCD input
RIN : in std_logic; -- RI input
SIN : in std_logic; -- Receiver input
SOUT : out std_logic -- Transmitter output
);
end apb_uart;
architecture rtl of apb_uart is
-- UART transmitter
component uart_transmitter is
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
TXCLK : in std_logic; -- Transmitter clock (2x baudrate)
TXSTART : in std_logic; -- Start transmitter
CLEAR : in std_logic; -- Clear transmitter state
WLS : in std_logic_vector(1 downto 0); -- Word length select
STB : in std_logic; -- Number of stop bits
PEN : in std_logic; -- Parity enable
EPS : in std_logic; -- Even parity select
SP : in std_logic; -- Stick parity
BC : in std_logic; -- Break control
DIN : in std_logic_vector(7 downto 0); -- Input data
TXFINISHED : out std_logic; -- Transmitter operation finished
SOUT : out std_logic -- Transmitter output
);
end component;
-- UART receiver
component uart_receiver is
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
RXCLK : in std_logic; -- Receiver clock (16x baudrate)
RXCLEAR : in std_logic; -- Reset receiver state
WLS : in std_logic_vector(1 downto 0); -- Word length select
STB : in std_logic; -- Number of stop bits
PEN : in std_logic; -- Parity enable
EPS : in std_logic; -- Even parity select
SP : in std_logic; -- Stick parity
SIN : in std_logic; -- Receiver input
PE : out std_logic; -- Parity error
FE : out std_logic; -- Framing error
BI : out std_logic; -- Break interrupt
DOUT : out std_logic_vector(7 downto 0); -- Output data
RXFINISHED : out std_logic -- Receiver operation finished
);
end component;
-- UART interrupt control
component uart_interrupt is
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
IER : in std_logic_vector(3 downto 0); -- IER 3:0
LSR : in std_logic_vector(4 downto 0); -- LSR 4:0
THI : in std_logic; -- Transmitter holding register empty interrupt
RDA : in std_logic; -- Receiver data available
CTI : in std_logic; -- Character timeout indication
AFE : in std_logic; -- Automatic flow control enable
MSR : in std_logic_vector(3 downto 0); -- MSR 3:0
IIR : out std_logic_vector(3 downto 0); -- IIR 3:0
INT : out std_logic -- Interrupt
);
end component;
-- UART baudrate generator
component uart_baudgen is
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
CE : in std_logic; -- Clock enable
CLEAR : in std_logic; -- Reset generator (synchronization)
DIVIDER : in std_logic_vector(15 downto 0); -- Clock divider
BAUDTICK : out std_logic -- 16xBaudrate tick
);
end component;
-- UART FIFO
component slib_fifo is
generic (
WIDTH : integer := 8; -- FIFO width
SIZE_E : integer := 6 -- FIFO size (2^SIZE_E)
);
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
CLEAR : in std_logic; -- Clear FIFO
WRITE : in std_logic; -- Write to FIFO
READ : in std_logic; -- Read from FIFO
D : in std_logic_vector(WIDTH-1 downto 0); -- FIFO input
Q : out std_logic_vector(WIDTH-1 downto 0); -- FIFO output
EMPTY : out std_logic; -- FIFO is empty
FULL : out std_logic; -- FIFO is full
USAGE : out std_logic_vector(SIZE_E-1 downto 0) -- FIFO usage
);
end component;
-- Edge detect
component slib_edge_detect is
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
D : in std_logic; -- Signal input
RE : out std_logic; -- Rising edge detected
FE : out std_logic -- Falling edge detected
);
end component;
-- Input synchronization
component slib_input_sync is
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
D : in std_logic; -- Signal input
Q : out std_logic -- Signal output
);
end component;
-- Input filter
component slib_input_filter is
generic (
SIZE : natural := 4 -- Filter width
);
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
CE : in std_logic; -- Clock enable
D : in std_logic; -- Signal input
Q : out std_logic -- Signal output
);
end component;
-- Clock enable generation
component slib_clock_div is
generic (
RATIO : integer := 8 -- Clock divider ratio
);
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
CE : in std_logic; -- Clock enable input
Q : out std_logic -- New clock enable output
);
end component;
-- Global device signals
signal iWrite : std_logic; -- Write to UART
signal iRead : std_logic; -- Read from UART
signal iRST : std_logic; -- RST negated
-- UART registers read/write signals
signal iRBRRead : std_logic; -- Read from RBR
signal iTHRWrite : std_logic; -- Write to THR
signal iDLLWrite : std_logic; -- Write to DLL
signal iDLMWrite : std_logic; -- Write to DLM
signal iIERWrite : std_logic; -- Write to IER
signal iIIRRead : std_logic; -- Read from IIR
signal iFCRWrite : std_logic; -- Write to FCR
signal iLCRWrite : std_logic; -- Write to LCR
signal iMCRWrite : std_logic; -- Write to MCR
signal iLSRRead : std_logic; -- Read from LSR
signal iMSRRead : std_logic; -- Read from MSR
signal iSCRWrite : std_logic; -- Write to SCR
-- UART registers
signal iTSR : std_logic_vector(7 downto 0); -- Transmitter holding register
signal iRBR : std_logic_vector(7 downto 0); -- Receiver buffer register
signal iDLL : std_logic_vector(7 downto 0); -- Divisor latch LSB
signal iDLM : std_logic_vector(7 downto 0); -- Divisor latch MSB
signal iIER : std_logic_vector(7 downto 0); -- Interrupt enable register
signal iIIR : std_logic_vector(7 downto 0); -- Interrupt identification register
signal iFCR : std_logic_vector(7 downto 0); -- FIFO control register
signal iLCR : std_logic_vector(7 downto 0); -- Line control register
signal iMCR : std_logic_vector(7 downto 0); -- Modem control register
signal iLSR : std_logic_vector(7 downto 0); -- Line status register
signal iMSR : std_logic_vector(7 downto 0); -- Modem status register
signal iSCR : std_logic_vector(7 downto 0); -- Scratch register
-- IER register signals
signal iIER_ERBI : std_logic; -- IER: Enable received data available interrupt
signal iIER_ETBEI : std_logic; -- IER: Enable transmitter holding register empty interrupt
signal iIER_ELSI : std_logic; -- IER: Enable receiver line status interrupt
signal iIER_EDSSI : std_logic; -- IER: Enable modem status interrupt
-- IIR register signals
signal iIIR_PI : std_logic; -- IIR: Pending interrupt
signal iIIR_ID0 : std_logic; -- IIR: Interrupt ID0
signal iIIR_ID1 : std_logic; -- IIR: Interrupt ID1
signal iIIR_ID2 : std_logic; -- IIR: Interrupt ID2
signal iIIR_FIFO64 : std_logic; -- IIR: 64 byte FIFO enabled
-- FCR register signals
signal iFCR_FIFOEnable : std_logic; -- FCR: FIFO enable
signal iFCR_RXFIFOReset : std_logic; -- FCR: Receiver FIFO reset
signal iFCR_TXFIFOReset : std_logic; -- FCR: Transmitter FIFO reset
signal iFCR_DMAMode : std_logic; -- FCR: DMA mode select
signal iFCR_FIFO64E : std_logic; -- FCR: 64 byte FIFO enable
signal iFCR_RXTrigger : std_logic_vector(1 downto 0); -- FCR: Receiver trigger
-- LCR register signals
signal iLCR_WLS : std_logic_vector(1 downto 0); -- LCR: Word length select
signal iLCR_STB : std_logic; -- LCR: Number of stop bits
signal iLCR_PEN : std_logic; -- LCR: Parity enable
signal iLCR_EPS : std_logic; -- LCR: Even parity select
signal iLCR_SP : std_logic; -- LCR: Sticky parity
signal iLCR_BC : std_logic; -- LCR: Break control
signal iLCR_DLAB : std_logic; -- LCR: Divisor latch access bit
-- MCR register signals
signal iMCR_DTR : std_logic; -- MCR: Data terminal ready
signal iMCR_RTS : std_logic; -- MCR: Request to send
signal iMCR_OUT1 : std_logic; -- MCR: OUT1
signal iMCR_OUT2 : std_logic; -- MCR: OUT2
signal iMCR_LOOP : std_logic; -- MCR: Loop
signal iMCR_AFE : std_logic; -- MCR: Auto flow control enable
-- LSR register signals
signal iLSR_DR : std_logic; -- LSR: Data ready
signal iLSR_OE : std_logic; -- LSR: Overrun error
signal iLSR_PE : std_logic; -- LSR: Parity error
signal iLSR_FE : std_logic; -- LSR: Framing error
signal iLSR_BI : std_logic; -- LSR: Break Interrupt
signal iLSR_THRE : std_logic; -- LSR: Transmitter holding register empty
signal iLSR_THRNF : std_logic; -- LSR: Transmitter holding register not full
signal iLSR_TEMT : std_logic; -- LSR: Transmitter empty
signal iLSR_FIFOERR : std_logic; -- LSR: Error in receiver FIFO
-- MSR register signals
signal iMSR_dCTS : std_logic; -- MSR: Delta CTS
signal iMSR_dDSR : std_logic; -- MSR: Delta DSR
signal iMSR_TERI : std_logic; -- MSR: Trailing edge ring indicator
signal iMSR_dDCD : std_logic; -- MSR: Delta DCD
signal iMSR_CTS : std_logic; -- MSR: CTS
signal iMSR_DSR : std_logic; -- MSR: DSR
signal iMSR_RI : std_logic; -- MSR: RI
signal iMSR_DCD : std_logic; -- MSR: DCD
-- UART MSR signals
signal iCTSNs : std_logic; -- Synchronized CTSN input
signal iDSRNs : std_logic; -- Synchronized DSRN input
signal iDCDNs : std_logic; -- Synchronized DCDN input
signal iRINs : std_logic; -- Synchronized RIN input
signal iCTSn : std_logic; -- Filtered CTSN input
signal iDSRn : std_logic; -- Filtered DSRN input
signal iDCDn : std_logic; -- Filtered DCDN input
signal iRIn : std_logic; -- Filtered RIN input
signal iCTSnRE : std_logic; -- CTSn rising edge
signal iCTSnFE : std_logic; -- CTSn falling edge
signal iDSRnRE : std_logic; -- DSRn rising edge
signal iDSRnFE : std_logic; -- DSRn falling edge
signal iDCDnRE : std_logic; -- DCDn rising edge
signal iDCDnFE : std_logic; -- DCDn falling edge
signal iRInRE : std_logic; -- RIn rising edge
signal iRInFE : std_logic; -- RIn falling edge
-- UART baudrate generation signals
signal iBaudgenDiv : std_logic_vector(15 downto 0); -- Baudrate divider
signal iBaudtick16x : std_logic; -- 16x Baudrate output from baudrate generator
signal iBaudtick2x : std_logic; -- 2x Baudrate for transmitter
signal iRCLK : std_logic; -- 16x Baudrate for receiver
signal iBAUDOUTN : std_logic;
-- UART FIFO signals
signal iTXFIFOClear : std_logic; -- Clear TX FIFO
signal iTXFIFOWrite : std_logic; -- Write to TX FIFO
signal iTXFIFORead : std_logic; -- Read from TX FIFO
signal iTXFIFOEmpty : std_logic; -- TX FIFO is empty
signal iTXFIFOFull : std_logic; -- TX FIFO is full
signal iTXFIFO16Full : std_logic; -- TX FIFO 16 byte mode is full
signal iTXFIFO64Full : std_logic; -- TX FIFO 64 byte mode is full
signal iTXFIFOUsage : std_logic_vector(5 downto 0); -- RX FIFO usage
signal iTXFIFOQ : std_logic_vector(7 downto 0); -- TX FIFO output
signal iRXFIFOClear : std_logic; -- Clear RX FIFO
signal iRXFIFOWrite : std_logic; -- Write to RX FIFO
signal iRXFIFORead : std_logic; -- Read from RX FIFO
signal iRXFIFOEmpty : std_logic; -- RX FIFO is empty
signal iRXFIFOFull : std_logic; -- RX FIFO is full
signal iRXFIFO16Full : std_logic; -- RX FIFO 16 byte mode is full
signal iRXFIFO64Full : std_logic; -- RX FIFO 64 byte mode is full
signal iRXFIFOD : std_logic_vector(10 downto 0); -- RX FIFO input
signal iRXFIFOQ : std_logic_vector(10 downto 0); -- RX FIFO output
signal iRXFIFOUsage : std_logic_vector(5 downto 0); -- RX FIFO usage
signal iRXFIFOTrigger : std_logic; -- FIFO trigger level reached
signal iRXFIFO16Trigger : std_logic; -- FIFO 16 byte mode trigger level reached
signal iRXFIFO64Trigger : std_logic; -- FIFO 64 byte mode trigger level reached
signal iRXFIFOPE : std_logic; -- Parity error from FIFO
signal iRXFIFOFE : std_logic; -- Frame error from FIFO
signal iRXFIFOBI : std_logic; -- Break interrupt from FIFO
-- UART transmitter signals
signal iSOUT : std_logic; -- Transmitter output
signal iTXStart : std_logic; -- Start transmitter
signal iTXClear : std_logic; -- Clear transmitter status
signal iTXFinished : std_logic; -- TX finished, character transmitted
signal iTXRunning : std_logic; -- TX in progress
-- UART receiver signals
signal iSINr : std_logic; -- Synchronized SIN input
signal iSIN : std_logic; -- Receiver input
signal iRXFinished : std_logic; -- RX finished, character received
signal iRXClear : std_logic; -- Clear receiver status
signal iRXData : std_logic_vector(7 downto 0); -- RX data
signal iRXPE : std_logic; -- RX parity error
signal iRXFE : std_logic; -- RX frame error
signal iRXBI : std_logic; -- RX break interrupt
-- UART control signals
signal iFERE : std_logic; -- Frame error detected
signal iPERE : std_logic; -- Parity error detected
signal iBIRE : std_logic; -- Break interrupt detected
signal iFECounter : integer range 0 to 64; -- FIFO error counter
signal iFEIncrement : std_logic; -- FIFO error counter increment
signal iFEDecrement : std_logic; -- FIFO error counter decrement
signal iRDAInterrupt : std_logic; -- Receiver data available interrupt (DA or FIFO trigger level)
signal iTimeoutCount : unsigned(5 downto 0); -- Character timeout counter (FIFO mode)
signal iCharTimeout : std_logic; -- Character timeout indication (FIFO mode)
signal iLSR_THRERE : std_logic; -- LSR THRE rising edge for interrupt generation
signal iTHRInterrupt : std_logic; -- Transmitter holding register empty interrupt
signal iTXEnable : std_logic; -- Transmitter enable signal
signal iRTS : std_logic; -- Internal RTS signal with/without automatic flow control
begin
-- Global device signals
iWrite <= '1' when PSEL = '1' and PENABLE = '1' and PWRITE = '1' else '0';
iRead <= '1' when PSEL = '1' and PENABLE = '1' and PWRITE = '0' else '0';
iRST <= '1' when RSTN = '0' else '0';
-- UART registers read/write signals
iRBRRead <= '1' when iRead = '1' and PADDR = "000" and iLCR_DLAB = '0' else '0';
iTHRWrite <= '1' when iWrite = '1' and PADDR = "000" and iLCR_DLAB = '0' else '0';
iDLLWrite <= '1' when iWrite = '1' and PADDR = "000" and iLCR_DLAB = '1' else '0';
iDLMWrite <= '1' when iWrite = '1' and PADDR = "001" and iLCR_DLAB = '1' else '0';
iIERWrite <= '1' when iWrite = '1' and PADDR = "001" and iLCR_DLAB = '0' else '0';
iIIRRead <= '1' when iRead = '1' and PADDR = "010" else '0';
iFCRWrite <= '1' when iWrite = '1' and PADDR = "010" else '0';
iLCRWrite <= '1' when iWrite = '1' and PADDR = "011" else '0';
iMCRWrite <= '1' when iWrite = '1' and PADDR = "100" else '0';
iLSRRead <= '1' when iRead = '1' and PADDR = "101" else '0';
iMSRRead <= '1' when iRead = '1' and PADDR = "110" else '0';
iSCRWrite <= '1' when iWrite = '1' and PADDR = "111" else '0';
-- Async. input synchronization
UART_IS_SIN: slib_input_sync port map (CLK, iRST, SIN, iSINr);
UART_IS_CTS: slib_input_sync port map (CLK, iRST, CTSN, iCTSNs);
UART_IS_DSR: slib_input_sync port map (CLK, iRST, DSRN, iDSRNs);
UART_IS_DCD: slib_input_sync port map (CLK, iRST, DCDN, iDCDNs);
UART_IS_RI: slib_input_sync port map (CLK, iRST, RIN, iRINs);
-- Input filter for UART control signals
UART_IF_CTS: slib_input_filter generic map (SIZE => 2) port map (CLK, iRST, iBaudtick2x, iCTSNs, iCTSn);
UART_IF_DSR: slib_input_filter generic map (SIZE => 2) port map (CLK, iRST, iBaudtick2x, iDSRNs, iDSRn);
UART_IF_DCD: slib_input_filter generic map (SIZE => 2) port map (CLK, iRST, iBaudtick2x, iDCDNs, iDCDn);
UART_IF_RI: slib_input_filter generic map (SIZE => 2) port map (CLK, iRST, iBaudtick2x, iRINs, iRIn);
-- Divisor latch register
UART_DLR: process (CLK, iRST)
begin
if (iRST = '1') then
iDLL <= (others => '0');
iDLM <= (others => '0');
elsif (CLK'event and CLK = '1') then
if (iDLLWrite = '1') then
iDLL <= PWDATA(7 downto 0);
end if;
if (iDLMWrite = '1') then
iDLM <= PWDATA(7 downto 0);
end if;
end if;
end process;
-- Interrupt enable register
UART_IER: process (CLK, iRST)
begin
if (iRST = '1') then
iIER(3 downto 0) <= (others => '0');
elsif (CLK'event and CLK = '1') then
if (iIERWrite = '1') then
iIER(3 downto 0) <= PWDATA(3 downto 0);
end if;
end if;
end process;
iIER_ERBI <= iIER(0);
iIER_ETBEI <= iIER(1);
iIER_ELSI <= iIER(2);
iIER_EDSSI <= iIER(3);
iIER(7 downto 4) <= (others => '0');
-- Interrupt control and IIR
UART_IIC: uart_interrupt port map (CLK => CLK,
RST => iRST,
IER => iIER(3 downto 0),
LSR => iLSR(4 downto 0),
THI => iTHRInterrupt,
RDA => iRDAInterrupt,
CTI => iCharTimeout,
AFE => iMCR_AFE,
MSR => iMSR(3 downto 0),
IIR => iIIR(3 downto 0),
INT => INT
);
-- THR empty interrupt
UART_IIC_THRE_ED: slib_edge_detect port map (CLK => CLK, RST => iRST, D => iLSR_THRE, RE => iLSR_THRERE);
UART_IIC_THREI: process (CLK, iRST)
begin
if (iRST = '1') then
iTHRInterrupt <= '0';
elsif (CLK'event and CLK = '1') then
if (iLSR_THRERE = '1' or iFCR_TXFIFOReset = '1' or (iIERWrite = '1' and PWDATA(1) = '1' and iLSR_THRE = '1')) then
iTHRInterrupt <= '1'; -- Set on THRE, TX FIFO reset (FIFO enable) or ETBEI enable
elsif ((iIIRRead = '1' and iIIR(3 downto 1) = "001") or iTHRWrite = '1') then
iTHRInterrupt <= '0'; -- Clear on IIR read (if source of interrupt) or THR write
end if;
end if;
end process;
iRDAInterrupt <= '1' when (iFCR_FIFOEnable = '0' and iLSR_DR = '1') or
(iFCR_FIFOEnable = '1' and iRXFIFOTrigger = '1') else '0';
iIIR_PI <= iIIR(0);
iIIR_ID0 <= iIIR(1);
iIIR_ID1 <= iIIR(2);
iIIR_ID2 <= iIIR(3);
iIIR_FIFO64 <= iIIR(5);
iIIR(4) <= '0';
iIIR(5) <= iFCR_FIFO64E when iFCR_FIFOEnable = '1' else '0';
iIIR(6) <= iFCR_FIFOEnable;
iIIR(7) <= iFCR_FIFOEnable;
-- Character timeout indication
UART_CTI: process (CLK, iRST)
begin
if (iRST = '1') then
iTimeoutCount <= (others => '0');
iCharTimeout <= '0';
elsif (CLK'event and CLK = '1') then
if (iRXFIFOEmpty = '1' or iRBRRead = '1' or iRXFIFOWrite = '1') then
iTimeoutCount <= (others => '0');
elsif (iRXFIFOEmpty = '0' and iBaudtick2x = '1' and iTimeoutCount(5) = '0') then
iTimeoutCount <= iTimeoutCount + 1;
end if;
-- Timeout indication
if (iFCR_FIFOEnable = '1') then
if (iRBRRead = '1') then
iCharTimeout <= '0';
elsif (iTimeoutCount(5) = '1') then
iCharTimeout <= '1';
end if;
else
iCharTimeout <= '0';
end if;
end if;
end process;
-- FIFO control register
UART_FCR: process (CLK, iRST)
begin
if (iRST = '1') then
iFCR_FIFOEnable <= '0';
iFCR_RXFIFOReset <= '0';
iFCR_TXFIFOReset <= '0';
iFCR_DMAMode <= '0';
iFCR_FIFO64E <= '0';
iFCR_RXTrigger <= (others => '0');
elsif (CLK'event and CLK = '1') then
-- FIFO reset pulse only
iFCR_RXFIFOReset <= '0';
iFCR_TXFIFOReset <= '0';
if (iFCRWrite = '1') then
iFCR_FIFOEnable <= PWDATA(0);
iFCR_DMAMode <= PWDATA(3);
iFCR_RXTrigger <= PWDATA(7 downto 6);
if (iLCR_DLAB = '1') then
iFCR_FIFO64E <= PWDATA(5);
end if;
-- RX FIFO reset control, reset on FIFO enable/disable
if (PWDATA(1) = '1' or (iFCR_FIFOEnable = '0' and PWDATA(0) = '1') or (iFCR_FIFOEnable = '1' and PWDATA(0) = '0')) then
iFCR_RXFIFOReset <= '1';
end if;
-- TX FIFO reset control, reset on FIFO enable/disable
if (PWDATA(2) = '1' or (iFCR_FIFOEnable = '0' and PWDATA(0) = '1') or (iFCR_FIFOEnable = '1' and PWDATA(0) = '0')) then
iFCR_TXFIFOReset <= '1';
end if;
end if;
end if;
end process;
iFCR(0) <= iFCR_FIFOEnable;
iFCR(1) <= iFCR_RXFIFOReset;
iFCR(2) <= iFCR_TXFIFOReset;
iFCR(3) <= iFCR_DMAMode;
iFCR(4) <= '0';
iFCR(5) <= iFCR_FIFO64E;
iFCR(7 downto 6) <= iFCR_RXTrigger;
-- Line control register
UART_LCR: process (CLK, iRST)
begin
if (iRST = '1') then
iLCR <= (others => '0');
elsif (CLK'event and CLK = '1') then
if (iLCRWrite = '1') then
iLCR <= PWDATA(7 downto 0);
end if;
end if;
end process;
iLCR_WLS <= iLCR(1 downto 0);
iLCR_STB <= iLCR(2);
iLCR_PEN <= iLCR(3);
iLCR_EPS <= iLCR(4);
iLCR_SP <= iLCR(5);
iLCR_BC <= iLCR(6);
iLCR_DLAB <= iLCR(7);
-- Modem control register
UART_MCR: process (CLK, iRST)
begin
if (iRST = '1') then
iMCR(5 downto 0) <= (others => '0');
elsif (CLK'event and CLK = '1') then
if (iMCRWrite = '1') then
iMCR(5 downto 0) <= PWDATA(5 downto 0);
end if;
end if;
end process;
iMCR_DTR <= iMCR(0);
iMCR_RTS <= iMCR(1);
iMCR_OUT1 <= iMCR(2);
iMCR_OUT2 <= iMCR(3);
iMCR_LOOP <= iMCR(4);
iMCR_AFE <= iMCR(5);
iMCR(6) <= '0';
iMCR(7) <= '0';
-- Line status register
UART_LSR: process (CLK, iRST)
begin
if (iRST = '1') then
iLSR_OE <= '0';
iLSR_PE <= '0';
iLSR_FE <= '0';
iLSR_BI <= '0';
iFECounter <= 0;
iLSR_FIFOERR <= '0';
elsif (CLK'event and CLK = '1') then
-- Overrun error
if ((iFCR_FIFOEnable = '0' and iLSR_DR = '1' and iRXFinished = '1') or
(iFCR_FIFOEnable = '1' and iRXFIFOFull = '1' and iRXFinished = '1')) then
iLSR_OE <= '1';
elsif (iLSRRead = '1') then
iLSR_OE <= '0';
end if;
-- Parity error
if (iPERE = '1') then
iLSR_PE <= '1';
elsif (iLSRRead = '1') then
iLSR_PE <= '0';
end if;
-- Frame error
if (iFERE = '1') then
iLSR_FE <= '1';
elsif (iLSRRead = '1') then
iLSR_FE <= '0';
end if;
-- Break interrupt
if (iBIRE = '1') then
iLSR_BI <= '1';
elsif (iLSRRead = '1') then
iLSR_BI <= '0';
end if;
-- FIFO error
-- Datasheet: Cleared by LSR read when no subsequent errors in FIFO
-- Observed: Cleared when no subsequent errors in FIFO
if (iFECounter /= 0) then
iLSR_FIFOERR <= '1';
--elsif (iLSRRead = '1' and iFECounter = 0 and not (iRXFIFOEmpty = '0' and iRXFIFOQ(10 downto 8) /= "000")) then
elsif (iRXFIFOEmpty = '1' or iRXFIFOQ(10 downto 8) = "000") then
iLSR_FIFOERR <= '0';
end if;
-- FIFO error counter
if (iRXFIFOClear = '1') then
iFECounter <= 0;
else
if (iFEIncrement = '1' and iFEDecrement = '0') then
iFECounter <= iFECounter + 1;
elsif (iFEIncrement = '0' and iFEDecrement = '1') then
iFECounter <= iFECounter - 1;
end if;
end if;
end if;
end process;
iRXFIFOPE <= '1' when iRXFIFOEmpty = '0' and iRXFIFOQ(8) = '1' else '0';
iRXFIFOFE <= '1' when iRXFIFOEmpty = '0' and iRXFIFOQ(9) = '1' else '0';
iRXFIFOBI <= '1' when iRXFIFOEmpty = '0' and iRXFIFOQ(10) = '1' else '0';
UART_PEDET: slib_edge_detect port map (CLK, iRST, iRXFIFOPE, iPERE);
UART_FEDET: slib_edge_detect port map (CLK, iRST, iRXFIFOFE, iFERE);
UART_BIDET: slib_edge_detect port map (CLK, iRST, iRXFIFOBI, iBIRE);
iFEIncrement <= '1' when iRXFIFOWrite = '1' and iRXFIFOD(10 downto 8) /= "000" else '0';
iFEDecrement <= '1' when iFECounter /= 0 and iRXFIFOEmpty = '0' and (iPERE = '1' or iFERE = '1' or iBIRE = '1') else '0';
iLSR(0) <= iLSR_DR;
iLSR(1) <= iLSR_OE;
iLSR(2) <= iLSR_PE;
iLSR(3) <= iLSR_FE;
iLSR(4) <= iLSR_BI;
iLSR(5) <= iLSR_THRNF;
iLSR(6) <= iLSR_TEMT;
iLSR(7) <= '1' when iFCR_FIFOEnable = '1' and iLSR_FIFOERR = '1' else '0';
iLSR_DR <= '1' when iRXFIFOEmpty = '0' or iRXFIFOWrite = '1' else '0';
iLSR_THRE <= '1' when iTXFIFOEmpty = '1' else '0';
iLSR_TEMT <= '1' when iTXRunning = '0' and iLSR_THRE = '1' else '0';
iLSR_THRNF <= '1' when ((iFCR_FIFOEnable = '0' and iTXFIFOEmpty = '1') or (iFCR_FIFOEnable = '1' and iTXFIFOFull = '0')) else '0';
-- Modem status register
iMSR_CTS <= '1' when (iMCR_LOOP = '1' and iRTS = '1') or (iMCR_LOOP = '0' and iCTSn = '0') else '0';
iMSR_DSR <= '1' when (iMCR_LOOP = '1' and iMCR_DTR = '1') or (iMCR_LOOP = '0' and iDSRn = '0') else '0';
iMSR_RI <= '1' when (iMCR_LOOP = '1' and iMCR_OUT1 = '1') or (iMCR_LOOP = '0' and iRIn = '0') else '0';
iMSR_DCD <= '1' when (iMCR_LOOP = '1' and iMCR_OUT2 = '1') or (iMCR_LOOP = '0' and iDCDn = '0') else '0';
-- Edge detection for CTS, DSR, DCD and RI
UART_ED_CTS: slib_edge_detect port map (CLK => CLK, RST => iRST, D => iMSR_CTS, RE => iCTSnRE, FE => iCTSnFE);
UART_ED_DSR: slib_edge_detect port map (CLK => CLK, RST => iRST, D => iMSR_DSR, RE => iDSRnRE, FE => iDSRnFE);
UART_ED_RI: slib_edge_detect port map (CLK => CLK, RST => iRST, D => iMSR_RI, RE => iRInRE, FE => iRInFE);
UART_ED_DCD: slib_edge_detect port map (CLK => CLK, RST => iRST, D => iMSR_DCD, RE => iDCDnRE, FE => iDCDnFE);
UART_MSR: process (CLK, iRST)
begin
if (iRST = '1') then
iMSR_dCTS <= '0';
iMSR_dDSR <= '0';
iMSR_TERI <= '0';
iMSR_dDCD <= '0';
elsif (CLK'event and CLK = '1') then
-- Delta CTS
if (iCTSnRE = '1' or iCTSnFE = '1') then
iMSR_dCTS <= '1';
elsif (iMSRRead = '1') then
iMSR_dCTS <= '0';
end if;
-- Delta DSR
if (iDSRnRE = '1' or iDSRnFE = '1') then
iMSR_dDSR <= '1';
elsif (iMSRRead = '1') then
iMSR_dDSR <= '0';
end if;
-- Trailing edge RI
if (iRInFE = '1') then
iMSR_TERI <= '1';
elsif (iMSRRead = '1') then
iMSR_TERI <= '0';
end if;
-- Delta DCD
if (iDCDnRE = '1' or iDCDnFE = '1') then
iMSR_dDCD <= '1';
elsif (iMSRRead = '1') then
iMSR_dDCD <= '0';
end if;
end if;
end process;
iMSR(0) <= iMSR_dCTS;
iMSR(1) <= iMSR_dDSR;
iMSR(2) <= iMSR_TERI;
iMSR(3) <= iMSR_dDCD;
iMSR(4) <= iMSR_CTS;
iMSR(5) <= iMSR_DSR;
iMSR(6) <= iMSR_RI;
iMSR(7) <= iMSR_DCD;
-- Scratch register
UART_SCR: process (CLK, iRST)
begin
if (iRST = '1') then
iSCR <= (others => '0');
elsif (CLK'event and CLK = '1') then
if (iSCRWrite = '1') then
iSCR <= PWDATA(7 downto 0);
end if;
end if;
end process;
-- Baudrate generator
iBaudgenDiv <= iDLM & iDLL;
UART_BG16: uart_baudgen port map (CLK => CLK,
RST => iRST,
CE => '1',
CLEAR => '0',
DIVIDER => iBaudgenDiv,
BAUDTICK => iBaudtick16x
);
UART_BG2: slib_clock_div generic map (RATIO => 8)
port map (CLK => CLK,
RST => iRST,
CE => iBaudtick16x,
Q => iBaudtick2x
);
UART_RCLK: slib_edge_detect port map (CLK => CLK,
RST => iRST,
D => iBAUDOUTN,
RE => iRCLK
);
-- Transmitter FIFO
UART_TXFF: slib_fifo generic map (WIDTH => 8, SIZE_E => 6)
port map (CLK => CLK,
RST => iRST,
CLEAR => iTXFIFOClear,
WRITE => iTXFIFOWrite,
READ => iTXFIFORead,
D => PWDATA(7 downto 0),
Q => iTXFIFOQ,
EMPTY => iTXFIFOEmpty,
FULL => iTXFIFO64Full,
USAGE => iTXFIFOUsage
);
-- Transmitter FIFO inputs
iTXFIFO16Full <= iTXFIFOUsage(4);
iTXFIFOFull <= iTXFIFO16Full when iFCR_FIFO64E = '0' else iTXFIFO64Full;
iTXFIFOWrite <= '1' when ((iFCR_FIFOEnable = '0' and iTXFIFOEmpty = '1') or (iFCR_FIFOEnable = '1' and iTXFIFOFull = '0')) and iTHRWrite = '1' else '0';
iTXFIFOClear <= '1' when iFCR_TXFIFOReset = '1' else '0';
-- Receiver FIFO
UART_RXFF: slib_fifo generic map (WIDTH => 11, SIZE_E => 6)
port map (CLK => CLK,
RST => iRST,
CLEAR => iRXFIFOClear,
WRITE => iRXFIFOWrite,
READ => iRXFIFORead,
D => iRXFIFOD,
Q => iRXFIFOQ,
EMPTY => iRXFIFOEmpty,
FULL => iRXFIFO64Full,
USAGE => iRXFIFOUsage
);
-- Receiver FIFO inputs
iRXFIFORead <= '1' when iRBRRead = '1' else '0';
iRXFIFO16Full <= iRXFIFOUsage(4);
iRXFIFOFull <= iRXFIFO16Full when iFCR_FIFO64E = '0' else iRXFIFO64Full;
-- Receiver FIFO outputs
iRBR <= iRXFIFOQ(7 downto 0);
-- FIFO trigger level: 1, 4, 8, 14
iRXFIFO16Trigger <= '1' when (iFCR_RXTrigger = "00" and iRXFIFOEmpty = '0') or
(iFCR_RXTrigger = "01" and (iRXFIFOUsage(2) = '1' or iRXFIFOUsage(3) = '1')) or
(iFCR_RXTrigger = "10" and iRXFIFOUsage(3) = '1') or
(iFCR_RXTrigger = "11" and iRXFIFOUsage(3) = '1' and iRXFIFOUsage(2) = '1' and iRXFIFOUsage(1) = '1') or
iRXFIFO16Full = '1' else '0';
-- FIFO 64 trigger level: 1, 16, 32, 56
iRXFIFO64Trigger <= '1' when (iFCR_RXTrigger = "00" and iRXFIFOEmpty = '0') or
(iFCR_RXTrigger = "01" and (iRXFIFOUsage(4) = '1' or iRXFIFOUsage(5) = '1')) or
(iFCR_RXTrigger = "10" and iRXFIFOUsage(5) = '1') or
(iFCR_RXTrigger = "11" and iRXFIFOUsage(5) = '1' and iRXFIFOUsage(4) = '1' and iRXFIFOUsage(3) = '1') or
iRXFIFO64Full = '1' else '0';
iRXFIFOTrigger <= iRXFIFO16Trigger when iFCR_FIFO64E = '0' else iRXFIFO64Trigger;
-- Transmitter
UART_TX: uart_transmitter port map (CLK => CLK,
RST => iRST,
TXCLK => iBaudtick2x,
TXSTART => iTXStart,
CLEAR => iTXClear,
WLS => iLCR_WLS,
STB => iLCR_STB,
PEN => iLCR_PEN,
EPS => iLCR_EPS,
SP => iLCR_SP,
BC => iLCR_BC,
DIN => iTSR,
TXFINISHED => iTXFinished,
SOUT => iSOUT
);
iTXClear <= '0';
-- Receiver
UART_RX: uart_receiver port map (CLK => CLK,
RST => iRST,
RXCLK => iRCLK,
RXCLEAR => iRXClear,
WLS => iLCR_WLS,
STB => iLCR_STB,
PEN => iLCR_PEN,
EPS => iLCR_EPS,
SP => iLCR_SP,
SIN => iSIN,
PE => iRXPE,
FE => iRXFE,
BI => iRXBI,
DOUT => iRXData,
RXFINISHED => iRXFinished
);
iRXClear <= '0';
iSIN <= iSINr when iMCR_LOOP = '0' else iSOUT;
-- Transmitter enable signal
-- TODO: Use iCTSNs instead of iMSR_CTS? Input filter increases delay for Auto-CTS recognition.
iTXEnable <= '1' when iTXFIFOEmpty = '0' and (iMCR_AFE = '0' or (iMCR_AFE = '1' and iMSR_CTS = '1')) else '0';
-- Transmitter process
UART_TXPROC: process (CLK, iRST)
type state_type is (IDLE, TXSTART, TXRUN, TXEND);
variable State : state_type;
begin
if (iRST = '1') then
State := IDLE;
iTSR <= (others => '0');
iTXStart <= '0';
iTXFIFORead <= '0';
iTXRunning <= '0';
elsif (CLK'event and CLK = '1') then
-- Defaults
iTXStart <= '0';
iTXFIFORead <= '0';
iTXRunning <= '0';
case State is
when IDLE => if (iTXEnable = '1') then
iTXStart <= '1'; -- Start transmitter
State := TXSTART;
else
State := IDLE;
end if;
when TXSTART => iTSR <= iTXFIFOQ;
iTXStart <= '1'; -- Start transmitter
iTXFIFORead <= '1'; -- Increment TX FIFO read counter
State := TXRUN;
when TXRUN => if (iTXFinished = '1') then -- TX finished
State := TXEND;
else
State := TXRUN;
end if;
iTXRunning <= '1';
iTXStart <= '1';
when TXEND => State := IDLE;
when others => State := IDLE;
end case;
end if;
end process;
-- Receiver process
UART_RXPROC: process (CLK, iRST)
type state_type is (IDLE, RXSAVE);
variable State : state_type;
begin
if (iRST = '1') then
State := IDLE;
iRXFIFOWrite <= '0';
iRXFIFOClear <= '0';
iRXFIFOD <= (others => '0');
elsif (CLK'event and CLK = '1') then
-- Defaults
iRXFIFOWrite <= '0';
iRXFIFOClear <= iFCR_RXFIFOReset;
case State is
when IDLE => if (iRXFinished = '1') then -- Receive finished
iRXFIFOD <= iRXBI & iRXFE & iRXPE & iRXData;
if (iFCR_FIFOEnable = '0') then
iRXFIFOClear <= '1'; -- Non-FIFO mode
end if;
State := RXSAVE;
else
State := IDLE;
end if;
when RXSAVE => if (iFCR_FIFOEnable = '0') then
iRXFIFOWrite <= '1'; -- Non-FIFO mode: Overwrite
elsif (iRXFIFOFull = '0') then
iRXFIFOWrite <= '1'; -- FIFO mode
end if;
State := IDLE;
when others => State := IDLE;
end case;
end if;
end process;
-- Automatic flow control
UART_AFC: process (CLK, iRST)
begin
if (iRST = '1') then
iRTS <= '0';
elsif (CLK'event and CLK = '1') then
if (iMCR_RTS = '0' or (iMCR_AFE = '1' and iRXFIFOTrigger = '1')) then
-- Deassert when MCR_RTS is not set or AFC is enabled and the RX FIFO trigger level is reached
iRTS <= '0';
elsif (iMCR_RTS = '1' and (iMCR_AFE = '0' or (iMCR_AFE = '1' and iRXFIFOEmpty = '1'))) then
-- Assert when MCR_RTS is set and AFC is disabled or when AFC is enabled and the RX FIFO is empty
iRTS <= '1';
end if;
end if;
end process;
-- Output registers
UART_OUTREGS: process (CLK, iRST)
begin
if (iRST = '1') then
iBAUDOUTN <= '1';
OUT1N <= '1';
OUT2N <= '1';
RTSN <= '1';
DTRN <= '1';
SOUT <= '1';
elsif (CLK'event and CLK = '1') then
-- Default values
iBAUDOUTN <= '0';
OUT1N <= '0';
OUT2N <= '0';
RTSN <= '0';
DTRN <= '0';
SOUT <= '0';
-- BAUDOUTN
if (iBaudtick16x = '0') then
iBAUDOUTN <= '1';
end if;
-- OUT1N
if (iMCR_LOOP = '1' or iMCR_OUT1 = '0') then
OUT1N <= '1';
end if;
-- OUT2N
if (iMCR_LOOP = '1' or iMCR_OUT2 = '0') then
OUT2N <= '1';
end if;
-- RTS
if (iMCR_LOOP = '1' or iRTS = '0') then
RTSN <= '1';
end if;
-- DTR
if (iMCR_LOOP = '1' or iMCR_DTR = '0') then
DTRN <= '1';
end if;
-- SOUT
if (iMCR_LOOP = '1' or iSOUT = '1') then
SOUT <= '1';
end if;
end if;
end process;
-- UART data output
UART_DOUT: process (PADDR, iLCR_DLAB, iRBR, iDLL, iDLM, iIER, iIIR, iLCR, iMCR, iLSR, iMSR, iSCR)
begin
case PADDR is
when "000" => if (iLCR_DLAB = '0') then
PRDATA(7 downto 0) <= iRBR;
else
PRDATA(7 downto 0) <= iDLL;
end if;
when "001" => if (iLCR_DLAB = '0') then
PRDATA(7 downto 0) <= iIER;
else
PRDATA(7 downto 0) <= iDLM;
end if;
when "010" => PRDATA(7 downto 0) <= iIIR;
when "011" => PRDATA(7 downto 0) <= iLCR;
when "100" => PRDATA(7 downto 0) <= iMCR;
when "101" => PRDATA(7 downto 0) <= iLSR;
when "110" => PRDATA(7 downto 0) <= iMSR;
when "111" => PRDATA(7 downto 0) <= iSCR;
when others => PRDATA(7 downto 0) <= iRBR;
end case;
end process;
PRDATA(31 downto 8) <= (others => '0');
PREADY <= '1';
PSLVERR <= '0';
end rtl;
|
apache-2.0
|
sakolkar/4BitSorter
|
Synopsis/sorter_top.vhd
|
1
|
3216
|
----------------------------------------------------------
-- ECE403 Lab3 Sorter Toplevel - 4 4-bit unsigned sorter
-- Jiawei Wu
-- Satyen Akolkar
-- Top level: sorter_top.vhd
-- Maps the multiplier core to the input and output pads
----------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY sorter_top IS
Port (
padA, padB, padC, padD : IN STD_LOGIC_VECTOR(3 downto 0);
padClk : IN STD_LOGIC;
padS1reg, padS2reg, padS3reg, padS4reg : OUT STD_LOGIC_VECTOR(3 downto 0)
);
END sorter_top;
ARCHITECTURE Structure of sorter_top IS
component sorter IS
Port (
Clk : IN STD_LOGIC;
A : IN STD_LOGIC_VECTOR(3 downto 0);
B : IN STD_LOGIC_VECTOR(3 downto 0);
C : IN STD_LOGIC_VECTOR(3 downto 0);
D : IN STD_LOGIC_VECTOR(3 downto 0);
S1reg : OUT STD_LOGIC_VECTOR(3 downto 0);
S2reg : OUT STD_LOGIC_VECTOR(3 downto 0);
S3reg : OUT STD_LOGIC_VECTOR(3 downto 0);
S4reg : OUT STD_LOGIC_VECTOR(3 downto 0)
);
END component;
component PDO12CDG
port(A : in std_logic;
PAD : out std_logic);
end component;
component PDUDGZ
port(Y : out std_logic;
PAD : in std_logic);
end component;
signal A, B, C, D : STD_LOGIC_VECTOR(3 downto 0);
signal S1reg, S2reg, S3reg, S4reg : STD_LOGIC_VECTOR(3 downto 0);
signal clk : STD_LOGIC;
begin
-- Input A pad mapping
padAGen: for i in 3 downto 0 generate
begin
inpA: PDUDGZ port map (Y => A(i), PAD => padA(i));
end generate;
-- Input B pad mapping
padBGen: for i in 3 downto 0 generate
begin
inpB: PDUDGZ port map (Y => B(i), PAD => padB(i));
end generate;
-- Input C pad mapping
padCGen: for i in 3 downto 0 generate
begin
inpC: PDUDGZ port map (Y => C(i), PAD => padC(i));
end generate;
-- Input D pad mapping
padDGen: for i in 3 downto 0 generate
begin
inpD: PDUDGZ port map (Y => D(i), PAD => padD(i));
end generate;
-- Output result pad mapping
padS1Gen: for i in 3 downto 0 generate
begin
opResS1: PDO12CDG port map (PAD => padS1reg(i), A => S1reg(i));
end generate;
padS2Gen: for i in 3 downto 0 generate
begin
opResS2: PDO12CDG port map (PAD => padS2reg(i), A => S2reg(i));
end generate;
padS3Gen: for i in 3 downto 0 generate
begin
opResS3: PDO12CDG port map (PAD => padS3reg(i), A => S3reg(i));
end generate;
padS4Gen: for i in 3 downto 0 generate
begin
opResS4: PDO12CDG port map (PAD => padS4reg(i), A => S4reg(i));
end generate;
-- Misc pad mapping
padClkG: PDUDGZ port map (Y => Clk, PAD => padClk);
-- Sorter mapping
coreG: sorter port map (Clk => Clk, A => A, B => B, C => C, D => D, S1reg => S1reg,
S2reg => S2reg, S3reg => S3reg, S4reg => S4reg);
END Structure;
|
apache-2.0
|
sakolkar/4BitSorter
|
Synopsis/PDO12CDG.vhd
|
1
|
319
|
LIBRARY IEEE;
USE STD.standard.all;
USE STD.textio.all;
USE IEEE.std_logic_1164.all;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity PDO12CDG is
port(A : in std_logic;
PAD : out std_logic);
end PDO12CDG;
architecture outpad_arc of PDO12CDG is
begin
process(A)
begin
PAD <= A;
end process;
end outpad_arc;
|
apache-2.0
|
alainmarcel/Surelog
|
third_party/tests/ariane/fpga/src/apb_uart/src/slib_input_filter.vhd
|
5
|
2084
|
--
-- Input filter
--
-- Author: Sebastian Witt
-- Data: 06.03.2008
-- Version: 1.0
--
-- This code is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the
-- Free Software Foundation, Inc., 59 Temple Place, Suite 330,
-- Boston, MA 02111-1307 USA
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;
entity slib_input_filter is
generic (
SIZE : natural := 4 -- Filter counter size
);
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
CE : in std_logic; -- Clock enable
D : in std_logic; -- Signal input
Q : out std_logic -- Signal output
);
end slib_input_filter;
architecture rtl of slib_input_filter is
signal iCount : integer range 0 to SIZE;
begin
IF_D: process (RST, CLK)
begin
if (RST = '1') then
iCount <= 0;
Q <= '0';
elsif (CLK'event and CLK='1') then
-- Input counter
if (CE = '1' ) then
if (D = '1' and iCount /= SIZE) then
iCount <= iCount + 1;
elsif (D = '0' and iCount /= 0) then
iCount <= iCount - 1;
end if;
end if;
-- Output
if (iCount = SIZE) then
Q <= '1';
elsif (iCount = 0) then
Q <= '0';
end if;
end if;
end process;
end rtl;
|
apache-2.0
|
Paebbels/PicoBlaze-Examples
|
psm/ExampleDesign/main_Page1.vhdl
|
1
|
29160
|
-- Program defined by '{psmname}.{psmext}'.
--
-- Generated by {assembler}: 2015-07-08T15:28:56.
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
library UniSim;
use UniSim.vComponents.all;
entity main_Page1 is
port (
Clock : in std_logic;
Fetch : in std_logic;
Address : in std_logic_vector(11 downto 0);
Instruction : out std_logic_vector(17 downto 0);
JTAGLoader_Clock : in std_logic;
JTAGLoader_Enable : in std_logic;
JTAGLoader_Address : in std_logic_vector(11 downto 0);
JTAGLoader_WriteEnable : in std_logic;
JTAGLoader_DataIn : in std_logic_vector(17 downto 0);
JTAGLoader_DataOut : out std_logic_vector(17 downto 0)
);
end;
architecture page of main_Page1 is
--
signal address_a : std_logic_vector(15 downto 0);
signal data_in_a : std_logic_vector(35 downto 0);
signal data_out_a : std_logic_vector(35 downto 0);
signal data_out_a_l : std_logic_vector(35 downto 0);
signal data_out_a_h : std_logic_vector(35 downto 0);
signal address_b : std_logic_vector(15 downto 0);
signal data_in_b : std_logic_vector(35 downto 0);
signal data_in_b_l : std_logic_vector(35 downto 0);
signal data_out_b : std_logic_vector(35 downto 0);
signal data_out_b_l : std_logic_vector(35 downto 0);
signal data_in_b_h : std_logic_vector(35 downto 0);
signal data_out_b_h : std_logic_vector(35 downto 0);
signal we_b : std_logic_vector(7 downto 0);
signal we_b_l : std_logic_vector(3 downto 0);
signal we_b_h : std_logic_vector(3 downto 0);
--
begin
address_a <= '1' & Address(11 downto 0) & "111";
Instruction <= data_out_a_h(32) & data_out_a_h(7 downto 0) & data_out_a_l(32) & data_out_a_l(7 downto 0);
we_b <= (others => JTAGLoader_WriteEnable);
address_b <= '1' & JTAGLoader_Address(11 downto 0) & "111";
data_in_b_l <= "000" & JTAGLoader_DataIn(8) & x"000000" & JTAGLoader_DataIn(7 downto 0);
data_in_b_h <= "000" & JTAGLoader_DataIn(17) & x"000000" & JTAGLoader_DataIn(16 downto 9);
JTAGLoader_DataOut <= data_out_b_h(32) & data_out_b_h(7 downto 0) & data_out_b_l(32) & data_out_b_l(7 downto 0);
rom0 : RAMB36E1
generic map (
READ_WIDTH_A => 9,
WRITE_WIDTH_A => 9,
DOA_REG => 0,
INIT_A => X"000000000",
RSTREG_PRIORITY_A => "REGCE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
READ_WIDTH_B => 9,
WRITE_WIDTH_B => 9,
DOB_REG => 0,
INIT_B => X"000000000",
RSTREG_PRIORITY_B => "REGCE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
SIM_DEVICE => "7SERIES",
INIT_00 => X"2F4E002F2F2F2F4E002F2F2F4E002F490303030C0B0A09080706050403020202",
INIT_01 => X"3900011E0000A0250001DCDCDCDCDCDCDCDCDCDCDCDCDCDCDCDC530500AC4900",
INIT_02 => X"18313372186D3072530010702E4E0020702E490040702E100A4000011E4700A0",
INIT_03 => X"AAFDE3E57CCE85B89D9139005B1B106D70183533727018333372701832337270",
INIT_04 => X"A2005C005D454E4F445B584096006100203E4154415358398A00660606060606",
INIT_05 => X"41465B5840BD005C005D44454C4941465B5840AF005C00203A524F5252455839",
INIT_06 => X"616D6D6F43206E776F6E6B6E555840D3005C0021544C4148203E2D205D4C4154",
INIT_07 => X"020166002E2E2E20414750466F5320676E69746F6F6265525840E8005C00646E",
INIT_08 => X"61572021776F6E2073726567676972742065706F635370696843206D72415839",
INIT_09 => X"0124584044016B00202E2E2E2073646E6F636573203520726F6620676E697469",
INIT_0A => X"205F5F5F5F205F5F5F5F5F20202020202020205F5F5F5F202020202021244000",
INIT_0B => X"5F20207C205F5F5F20207C5F5F5F202F202020200A5F202020205F5F5F5F2020",
INIT_0C => X"205C205F5F5F5C202020200A5C202F20207C5F5F5F202F205C205F20207C5F5F",
INIT_0D => X"200A5C205F202F20205F20207C207C20295F7C207C20205F7C207C5C205F202F",
INIT_0E => X"7C5F7C207C2F5F5F20207C207C5F20207C20295F28207C20295F5F5F20202020",
INIT_0F => X"2020207C5F7C2F5F5F5F5C202F5F5F5F5F7C202020200A5C205F5F5F202F7C20",
INIT_10 => X"203A65736E6563694C0A005C5F5C2020202F5F2F5F5F5F5F5C202020207C5F7C",
INIT_11 => X"72746150203A73726F687475410A302E322065736E6563694C20656863617041",
INIT_12 => X"69736544656C706D61784520203A6E67697365440A6E6E616D68654C206B6369",
INIT_13 => X"4C407F02006E67697365442065636E657265666552202D2073796C74415F6E67",
INIT_14 => X"2C48202C68203A73646E616D6D6F6320656C62616C6961766120666F20747369",
INIT_15 => X"35202C34202C33202C32202C31202C63202C6D202C50202C70202C52202C7220",
INIT_16 => X"6974616E616C70786520726F662048207373657270280A30202C39202C36202C",
INIT_17 => X"6E616D6D6F6320656C62616C6961766120666F207473694C40E802000A296E6F",
INIT_18 => X"0A6567617020706C656820736968742079616C7073696420204820200A3A7364",
INIT_19 => X"206572757361656D20206D20200A79616C70736964207261656C632020632020",
INIT_1A => X"200A6B636174534154415320746573657220207220200A79636E657571657266",
INIT_1B => X"776F64207265776F7020207020200A414750466F5320746F6F62657220205220",
INIT_1C => X"745341544153207075207265776F7020205020200A6B6361745341544153206E",
INIT_1D => X"6174732042694D20312073656D6974203031206461657220203120200A6B6361",
INIT_1E => X"3031206461657220203220200A302074657366666F206D6F726620676E697472",
INIT_1F => X"657366666F206D6F726620676E6974726174732042694720312073656D697420",
INIT_20 => X"302074657366666F20746120426947203436206461657220203320200A302074",
INIT_21 => X"20657469727720203420200A736574756E696D20332D2D322073656B6174202C",
INIT_22 => X"66666F206D6F726620676E6974726174732042694D20312073656D6974203031",
INIT_23 => X"2042694720312073656D697420303120657469727720203520200A3020746573",
INIT_24 => X"7469727720203620200A302074657366666F206D6F726620676E697472617473",
INIT_25 => X"332D2D322073656B6174202C302074657366666F207461204269472034362065",
INIT_26 => X"32206F7420657A695374737275422074657320203920200A736574756E696D20",
INIT_27 => X"203233206F7420657A695374737275422074657320203020200A42694B203635",
INIT_28 => X"642043324920726F6620676E696E6E616353390E05B3927A462A0B000A42694D",
INIT_29 => X"65747369676572206C6C6120676E6964616552392D05002E2E2E736563697665",
INIT_2A => X"6563637573206E6F69746172756769666E6F4320433249394905002E2E2E7372",
INIT_2B => X"433249397D0500656369766564206F74206E65747469727720796C6C75667373",
INIT_2C => X"5320676E6972757361654D3995050064656C696166206E6F6974617265706F20",
INIT_2D => X"030303030303030303137A484D003D66203A79636E6575716572662030373569",
INIT_2E => X"0303030303030303030303030303030303030303030303030303030303030303",
INIT_2F => X"0303030303030303030303030303030303030303030303030303030303030303",
INIT_30 => X"0303030303030303030303030303030303030303030303030303030303030303",
INIT_31 => X"0303030303030303030303030303030303030303030303030303030303030303",
INIT_32 => X"0303030303030303030303030303030303030303030303030303030303030303",
INIT_33 => X"0303030303030303030303030303030303030303030303030303030303030303",
INIT_34 => X"0303030303030303030303030303030303030303030303030303030303030303",
INIT_35 => X"0303030303030303030303030303030303030303030303030303030303030303",
INIT_36 => X"0303030303030303030303030303030303030303030303030303030303030303",
INIT_37 => X"0303030303030303030303030303030303030303030303030303030303030303",
INIT_38 => X"0303030303030303030303030303030303030303030303030303030303030303",
INIT_39 => X"0303030303030303030303030303030303030303030303030303030303030303",
INIT_3A => X"0303030303030303030303030303030303030303030303030303030303030303",
INIT_3B => X"0303030303030303030303030303030303030303030303030303030303030303",
INIT_3C => X"0303030303030303030303030303030303030303030303030303030303030303",
INIT_3D => X"0303030303030303030303030303030303030303030303030303030303030303",
INIT_3E => X"0303030303030303030303030303030303030303030303030303030303030303",
INIT_3F => X"0303030303030303030303030303030303030303030303030303030303030303",
INIT_40 => X"0303030303030303030303030303030303030303030303030303030303030303",
INIT_41 => X"0303030303030303030303030303030303030303030303030303030303030303",
INIT_42 => X"0303030303030303030303030303030303030303030303030303030303030303",
INIT_43 => X"0303030303030303030303030303030303030303030303030303030303030303",
INIT_44 => X"0303030303030303030303030303030303030303030303030303030303030303",
INIT_45 => X"0303030303030303030303030303030303030303030303030303030303030303",
INIT_46 => X"0303030303030303030303030303030303030303030303030303030303030303",
INIT_47 => X"0303030303030303030303030303030303030303030303030303030303030303",
INIT_48 => X"0303030303030303030303030303030303030303030303030303030303030303",
INIT_49 => X"0303030303030303030303030303030303030303030303030303030303030303",
INIT_4A => X"0303030303030303030303030303030303030303030303030303030303030303",
INIT_4B => X"0303030303030303030303030303030303030303030303030303030303030303",
INIT_4C => X"0303030303030303030303030303030303030303030303030303030303030303",
INIT_4D => X"0303030303030303030303030303030303030303030303030303030303030303",
INIT_4E => X"0303030303030303030303030303030303030303030303030303030303030303",
INIT_4F => X"0303030303030303030303030303030303030303030303030303030303030303",
INIT_50 => X"0303030303030303030303030303030303030303030303030303030303030303",
INIT_51 => X"0303030303030303030303030303030303030303030303030303030303030303",
INIT_52 => X"0303030303030303030303030303030303030303030303030303030303030303",
INIT_53 => X"0303030303030303030303030303030303030303030303030303030303030303",
INIT_54 => X"0303030303030303030303030303030303030303030303030303030303030303",
INIT_55 => X"0303030303030303030303030303030303030303030303030303030303030303",
INIT_56 => X"0303030303030303030303030303030303030303030303030303030303030303",
INIT_57 => X"0303030303030303030303030303030303030303030303030303030303030303",
INIT_58 => X"0303030303030303030303030303030303030303030303030303030303030303",
INIT_59 => X"0303030303030303030303030303030303030303030303030303030303030303",
INIT_5A => X"0303030303030303030303030303030303030303030303030303030303030303",
INIT_5B => X"0303030303030303030303030303030303030303030303030303030303030303",
INIT_5C => X"0303030303030303030303030303030303030303030303030303030303030303",
INIT_5D => X"0303030303030303030303030303030303030303030303030303030303030303",
INIT_5E => X"0303030303030303030303030303030303030303030303030303030303030303",
INIT_5F => X"0303030303030303030303030303030303030303030303030303030303030303",
INIT_60 => X"0303030303030303030303030303030303030303030303030303030303030303",
INIT_61 => X"0303030303030303030303030303030303030303030303030303030303030303",
INIT_62 => X"0303030303030303030303030303030303030303030303030303030303030303",
INIT_63 => X"0303030303030303030303030303030303030303030303030303030303030303",
INIT_64 => X"0303030303030303030303030303030303030303030303030303030303030303",
INIT_65 => X"0303030303030303030303030303030303030303030303030303030303030303",
INIT_66 => X"0303030303030303030303030303030303030303030303030303030303030303",
INIT_67 => X"0303030303030303030303030303030303030303030303030303030303030303",
INIT_68 => X"0303030303030303030303030303030303030303030303030303030303030303",
INIT_69 => X"0303030303030303030303030303030303030303030303030303030303030303",
INIT_6A => X"0303030303030303030303030303030303030303030303030303030303030303",
INIT_6B => X"0303030303030303030303030303030303030303030303030303030303030303",
INIT_6C => X"0303030303030303030303030303030303030303030303030303030303030303",
INIT_6D => X"0303030303030303030303030303030303030303030303030303030303030303",
INIT_6E => X"0303030303030303030303030303030303030303030303030303030303030303",
INIT_6F => X"0303030303030303030303030303030303030303030303030303030303030303",
INIT_70 => X"0303030303030303030303030303030303030303030303030303030303030303",
INIT_71 => X"0303030303030303030303030303030303030303030303030303030303030303",
INIT_72 => X"0303030303030303030303030303030303030303030303030303030303030303",
INIT_73 => X"0303030303030303030303030303030303030303030303030303030303030303",
INIT_74 => X"0303030303030303030303030303030303030303030303030303030303030303",
INIT_75 => X"0303030303030303030303030303030303030303030303030303030303030303",
INIT_76 => X"0303030303030303030303030303030303030303030303030303030303030303",
INIT_77 => X"0303030303030303030303030303030303030303030303030303030303030303",
INIT_78 => X"0303030303030303030303030303030303030303030303030303030303030303",
INIT_79 => X"0303030303030303030303030303030303030303030303030303030303030303",
INIT_7A => X"0303030303030303030303030303030303030303030303030303030303030303",
INIT_7B => X"0303030303030303030303030303030303030303030303030303030303030303",
INIT_7C => X"0303030303030303030303030303030303030303030303030303030303030303",
INIT_7D => X"0071BF61BF51BF41BF31BF21BF11BF0103030303030303030303030303030303",
INIT_7E => X"03030111A0010001A000750071D461D451D441D431D421D411D4010001A00505",
INIT_7F => X"04040404040404040404040404040404030303030303030303DA00000FF00601",
INITP_00 => X"400000100000800002000800400400400028210844000021423FFFC014200000",
INITP_01 => X"0000000000000000000000000000000000000000000000010400000000000000",
INITP_02 => X"0000002000000000000000000000000010000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000001000000004000004000000000000400000040000000FE0",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000006808D55546AAAA00000000000000000000000000000000000000000000"
)
port map (
ADDRARDADDR => address_a,
ENARDEN => Fetch,
CLKARDCLK => Clock,
DOADO => data_out_a_l(31 downto 0),
DOPADOP => data_out_a_l(35 downto 32),
DIADI => x"00000000",
DIPADIP => x"0",
WEA => "0000",
REGCEAREGCE => '0',
RSTRAMARSTRAM => '0',
RSTREGARSTREG => '0',
ADDRBWRADDR => address_b,
ENBWREN => JTAGLoader_Enable,
CLKBWRCLK => JTAGLoader_Clock,
DOBDO => data_out_b_l(31 downto 0),
DOPBDOP => data_out_b_l(35 downto 32),
DIBDI => data_in_b_l(31 downto 0),
DIPBDIP => data_in_b_l(35 downto 32),
WEBWE => we_b,
REGCEB => '0',
RSTRAMB => '0',
RSTREGB => '0',
CASCADEINA => '0',
CASCADEINB => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0'
);
--
rom1 : RAMB36E1
generic map (
READ_WIDTH_A => 9,
WRITE_WIDTH_A => 9,
DOA_REG => 0,
INIT_A => X"000000000",
RSTREG_PRIORITY_A => "REGCE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
READ_WIDTH_B => 9,
WRITE_WIDTH_B => 9,
DOB_REG => 0,
INIT_B => X"000000000",
RSTREG_PRIORITY_B => "REGCE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
SIM_DEVICE => "7SERIES",
INIT_00 => X"6F00286969686800286968680028680010101010101010101010101010101010",
INIT_01 => X"109D8D0088EF251088CF59595959595959595959595959595959000F28580028",
INIT_02 => X"000909001009090010886A1A4A10886A1A4A10886A1A4A1008109D8D0090EF25",
INIT_03 => X"1010101111101010101010280808100810000909001000090900100009090010",
INIT_04 => X"0D0D000F0F0F0F0F0F0F10000D0D000F0F0F0F0F0F0F10000D0D001010101010",
INIT_05 => X"0F0F0F10000D0D000F0F0F0F0F0F0F0F0F10000D0D000F0F0F0F0F0F0F0F1000",
INIT_06 => X"0F0F0F0F0F0F0F0F0F0F0F0F0F10000D0D000F0F0F0F0F0F0F0F0F0F0F0F0F0F",
INIT_07 => X"0D0D000F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F10000D0D000F0F0F",
INIT_08 => X"0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F1000",
INIT_09 => X"8D0000000D0D000F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F",
INIT_0A => X"0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F1000009D",
INIT_0B => X"0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F",
INIT_0C => X"0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F",
INIT_0D => X"0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F",
INIT_0E => X"0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F",
INIT_0F => X"0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F",
INIT_10 => X"0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F",
INIT_11 => X"0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F",
INIT_12 => X"0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F",
INIT_13 => X"0F100D0D0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F",
INIT_14 => X"0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F",
INIT_15 => X"0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F",
INIT_16 => X"0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F",
INIT_17 => X"0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F100D0D0F0F0F0F0F",
INIT_18 => X"0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F",
INIT_19 => X"0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F",
INIT_1A => X"0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F",
INIT_1B => X"0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F",
INIT_1C => X"0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F",
INIT_1D => X"0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F",
INIT_1E => X"0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F",
INIT_1F => X"0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F",
INIT_20 => X"0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F",
INIT_21 => X"0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F",
INIT_22 => X"0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F",
INIT_23 => X"0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F",
INIT_24 => X"0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F",
INIT_25 => X"0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F",
INIT_26 => X"0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F",
INIT_27 => X"0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F",
INIT_28 => X"0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F100D0D1212121212120F0F0F0F0F",
INIT_29 => X"0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F100D0D0F0F0F0F0F0F0F0F0F0F",
INIT_2A => X"0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F100D0D0F0F0F0F0F0F",
INIT_2B => X"0F0F0F100D0D0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F",
INIT_2C => X"0F0F0F0F0F0F0F0F0F0F0F100D0D0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F",
INIT_2D => X"101010101010101010100908080F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F",
INIT_2E => X"1010101010101010101010101010101010101010101010101010101010101010",
INIT_2F => X"1010101010101010101010101010101010101010101010101010101010101010",
INIT_30 => X"1010101010101010101010101010101010101010101010101010101010101010",
INIT_31 => X"1010101010101010101010101010101010101010101010101010101010101010",
INIT_32 => X"1010101010101010101010101010101010101010101010101010101010101010",
INIT_33 => X"1010101010101010101010101010101010101010101010101010101010101010",
INIT_34 => X"1010101010101010101010101010101010101010101010101010101010101010",
INIT_35 => X"1010101010101010101010101010101010101010101010101010101010101010",
INIT_36 => X"1010101010101010101010101010101010101010101010101010101010101010",
INIT_37 => X"1010101010101010101010101010101010101010101010101010101010101010",
INIT_38 => X"1010101010101010101010101010101010101010101010101010101010101010",
INIT_39 => X"1010101010101010101010101010101010101010101010101010101010101010",
INIT_3A => X"1010101010101010101010101010101010101010101010101010101010101010",
INIT_3B => X"1010101010101010101010101010101010101010101010101010101010101010",
INIT_3C => X"1010101010101010101010101010101010101010101010101010101010101010",
INIT_3D => X"1010101010101010101010101010101010101010101010101010101010101010",
INIT_3E => X"1010101010101010101010101010101010101010101010101010101010101010",
INIT_3F => X"1010101010101010101010101010101010101010101010101010101010101010",
INIT_40 => X"1010101010101010101010101010101010101010101010101010101010101010",
INIT_41 => X"1010101010101010101010101010101010101010101010101010101010101010",
INIT_42 => X"1010101010101010101010101010101010101010101010101010101010101010",
INIT_43 => X"1010101010101010101010101010101010101010101010101010101010101010",
INIT_44 => X"1010101010101010101010101010101010101010101010101010101010101010",
INIT_45 => X"1010101010101010101010101010101010101010101010101010101010101010",
INIT_46 => X"1010101010101010101010101010101010101010101010101010101010101010",
INIT_47 => X"1010101010101010101010101010101010101010101010101010101010101010",
INIT_48 => X"1010101010101010101010101010101010101010101010101010101010101010",
INIT_49 => X"1010101010101010101010101010101010101010101010101010101010101010",
INIT_4A => X"1010101010101010101010101010101010101010101010101010101010101010",
INIT_4B => X"1010101010101010101010101010101010101010101010101010101010101010",
INIT_4C => X"1010101010101010101010101010101010101010101010101010101010101010",
INIT_4D => X"1010101010101010101010101010101010101010101010101010101010101010",
INIT_4E => X"1010101010101010101010101010101010101010101010101010101010101010",
INIT_4F => X"1010101010101010101010101010101010101010101010101010101010101010",
INIT_50 => X"1010101010101010101010101010101010101010101010101010101010101010",
INIT_51 => X"1010101010101010101010101010101010101010101010101010101010101010",
INIT_52 => X"1010101010101010101010101010101010101010101010101010101010101010",
INIT_53 => X"1010101010101010101010101010101010101010101010101010101010101010",
INIT_54 => X"1010101010101010101010101010101010101010101010101010101010101010",
INIT_55 => X"1010101010101010101010101010101010101010101010101010101010101010",
INIT_56 => X"1010101010101010101010101010101010101010101010101010101010101010",
INIT_57 => X"1010101010101010101010101010101010101010101010101010101010101010",
INIT_58 => X"1010101010101010101010101010101010101010101010101010101010101010",
INIT_59 => X"1010101010101010101010101010101010101010101010101010101010101010",
INIT_5A => X"1010101010101010101010101010101010101010101010101010101010101010",
INIT_5B => X"1010101010101010101010101010101010101010101010101010101010101010",
INIT_5C => X"1010101010101010101010101010101010101010101010101010101010101010",
INIT_5D => X"1010101010101010101010101010101010101010101010101010101010101010",
INIT_5E => X"1010101010101010101010101010101010101010101010101010101010101010",
INIT_5F => X"1010101010101010101010101010101010101010101010101010101010101010",
INIT_60 => X"1010101010101010101010101010101010101010101010101010101010101010",
INIT_61 => X"1010101010101010101010101010101010101010101010101010101010101010",
INIT_62 => X"1010101010101010101010101010101010101010101010101010101010101010",
INIT_63 => X"1010101010101010101010101010101010101010101010101010101010101010",
INIT_64 => X"1010101010101010101010101010101010101010101010101010101010101010",
INIT_65 => X"1010101010101010101010101010101010101010101010101010101010101010",
INIT_66 => X"1010101010101010101010101010101010101010101010101010101010101010",
INIT_67 => X"1010101010101010101010101010101010101010101010101010101010101010",
INIT_68 => X"1010101010101010101010101010101010101010101010101010101010101010",
INIT_69 => X"1010101010101010101010101010101010101010101010101010101010101010",
INIT_6A => X"1010101010101010101010101010101010101010101010101010101010101010",
INIT_6B => X"1010101010101010101010101010101010101010101010101010101010101010",
INIT_6C => X"1010101010101010101010101010101010101010101010101010101010101010",
INIT_6D => X"1010101010101010101010101010101010101010101010101010101010101010",
INIT_6E => X"1010101010101010101010101010101010101010101010101010101010101010",
INIT_6F => X"1010101010101010101010101010101010101010101010101010101010101010",
INIT_70 => X"1010101010101010101010101010101010101010101010101010101010101010",
INIT_71 => X"1010101010101010101010101010101010101010101010101010101010101010",
INIT_72 => X"1010101010101010101010101010101010101010101010101010101010101010",
INIT_73 => X"1010101010101010101010101010101010101010101010101010101010101010",
INIT_74 => X"1010101010101010101010101010101010101010101010101010101010101010",
INIT_75 => X"1010101010101010101010101010101010101010101010101010101010101010",
INIT_76 => X"1010101010101010101010101010101010101010101010101010101010101010",
INIT_77 => X"1010101010101010101010101010101010101010101010101010101010101010",
INIT_78 => X"1010101010101010101010101010101010101010101010101010101010101010",
INIT_79 => X"1010101010101010101010101010101010101010101010101010101010101010",
INIT_7A => X"1010101010101010101010101010101010101010101010101010101010101010",
INIT_7B => X"1010101010101010101010101010101010101010101010101010101010101010",
INIT_7C => X"1010101010101010101010101010101010101010101010101010101010101010",
INIT_7D => X"0D58175817581758175817581758175810101010101010101010101010101010",
INIT_7E => X"1010485825582858259D8D0D5817581758175817581758175817582858259D8D",
INIT_7F => X"10101010101010101010101010101010101010101010101010179D850D0D48B8",
INITP_00 => X"3FFFFFCFFFFE7FFFF9FFE7FF3FF3FF3FFFF2CE7399C6314D9BBFFFEFFFFFFFFF",
INITP_01 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE73FFFFFFFFFFFFFF",
INITP_02 => X"FFFFFF9FFFFFFFFFFFFFFFFFFFFFFFFFCFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INITP_03 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INITP_04 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INITP_05 => X"FFFFFFFFFFFFFFFFFFC7FFFFFFF3FFFFF3FFFFFFFFFFFF3FFFFFF3FFFFFFE7FF",
INITP_06 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INITP_07 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INITP_08 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INITP_09 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INITP_0A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INITP_0B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INITP_0C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INITP_0D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INITP_0E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INITP_0F => X"FFFFFFC1FF8FFFFC7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
)
port map (
ADDRARDADDR => address_a,
ENARDEN => Fetch,
CLKARDCLK => Clock,
DOADO => data_out_a_h(31 downto 0),
DOPADOP => data_out_a_h(35 downto 32),
DIADI => x"00000000",
DIPADIP => x"0",
WEA => "0000",
REGCEAREGCE => '0',
RSTRAMARSTRAM => '0',
RSTREGARSTREG => '0',
ADDRBWRADDR => address_b,
ENBWREN => JTAGLoader_Enable,
CLKBWRCLK => JTAGLoader_Clock,
DOBDO => data_out_b_h(31 downto 0),
DOPBDOP => data_out_b_h(35 downto 32),
DIBDI => data_in_b_h(31 downto 0),
DIPBDIP => data_in_b_h(35 downto 32),
WEBWE => we_b,
REGCEB => '0',
RSTRAMB => '0',
RSTREGB => '0',
CASCADEINA => '0',
CASCADEINB => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0'
);
end page;
|
apache-2.0
|
flink-project/flinkvhdl
|
axiComponents/subDevices/watchdogDevice/hdl/watchdogDevice_S00_AXI.vhd
|
1
|
28322
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.flink_definitions.all;
use work.watchdog_pkg.all;
entity watchdogDevice_v1_0_S00_AXI is
generic (
-- Users to add parameters here
base_clk : INTEGER := 100000000;
unique_id : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width of ID for for write address, write data, read address and read data
C_S_AXI_ID_WIDTH : integer := 1;
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bus
C_S_AXI_ADDR_WIDTH : integer := 12;
-- Width of optional user defined signal in write address channel
C_S_AXI_AWUSER_WIDTH : integer := 0;
-- Width of optional user defined signal in read address channel
C_S_AXI_ARUSER_WIDTH : integer := 0;
-- Width of optional user defined signal in write data channel
C_S_AXI_WUSER_WIDTH : integer := 0;
-- Width of optional user defined signal in read data channel
C_S_AXI_RUSER_WIDTH : integer := 0;
-- Width of optional user defined signal in write response channel
C_S_AXI_BUSER_WIDTH : integer := 0
);
port (
-- Users to add ports here
osl_watchdog_pwm : OUT STD_LOGIC;
osl_granted : OUT STD_LOGIC;
-- User ports ends
-- Do not modify the ports beyond this line
-- Global Clock Signal
S_AXI_ACLK : in std_logic;
-- Global Reset Signal. This Signal is Active LOW
S_AXI_ARESETN : in std_logic;
-- Write Address ID
S_AXI_AWID : in std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
-- Write address
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Burst length. The burst length gives the exact number of transfers in a burst
S_AXI_AWLEN : in std_logic_vector(7 downto 0);
-- Burst size. This signal indicates the size of each transfer in the burst
S_AXI_AWSIZE : in std_logic_vector(2 downto 0);
-- Burst type. The burst type and the size information,
-- determine how the address for each transfer within the burst is calculated.
S_AXI_AWBURST : in std_logic_vector(1 downto 0);
-- Lock type. Provides additional information about the
-- atomic characteristics of the transfer.
S_AXI_AWLOCK : in std_logic;
-- Memory type. This signal indicates how transactions
-- are required to progress through a system.
S_AXI_AWCACHE : in std_logic_vector(3 downto 0);
-- Protection type. This signal indicates the privilege
-- and security level of the transaction, and whether
-- the transaction is a data access or an instruction access.
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
-- Quality of Service, QoS identifier sent for each
-- write transaction.
S_AXI_AWQOS : in std_logic_vector(3 downto 0);
-- Region identifier. Permits a single physical interface
-- on a slave to be used for multiple logical interfaces.
S_AXI_AWREGION : in std_logic_vector(3 downto 0);
-- Optional User-defined signal in the write address channel.
S_AXI_AWUSER : in std_logic_vector(C_S_AXI_AWUSER_WIDTH-1 downto 0);
-- Write address valid. This signal indicates that
-- the channel is signaling valid write address and
-- control information.
S_AXI_AWVALID : in std_logic;
-- Write address ready. This signal indicates that
-- the slave is ready to accept an address and associated
-- control signals.
S_AXI_AWREADY : out std_logic;
-- Write Data
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Write strobes. This signal indicates which byte
-- lanes hold valid data. There is one write strobe
-- bit for each eight bits of the write data bus.
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
-- Write last. This signal indicates the last transfer
-- in a write burst.
S_AXI_WLAST : in std_logic;
-- Optional User-defined signal in the write data channel.
S_AXI_WUSER : in std_logic_vector(C_S_AXI_WUSER_WIDTH-1 downto 0);
-- Write valid. This signal indicates that valid write
-- data and strobes are available.
S_AXI_WVALID : in std_logic;
-- Write ready. This signal indicates that the slave
-- can accept the write data.
S_AXI_WREADY : out std_logic;
-- Response ID tag. This signal is the ID tag of the
-- write response.
S_AXI_BID : out std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
-- Write response. This signal indicates the status
-- of the write transaction.
S_AXI_BRESP : out std_logic_vector(1 downto 0);
-- Optional User-defined signal in the write response channel.
S_AXI_BUSER : out std_logic_vector(C_S_AXI_BUSER_WIDTH-1 downto 0);
-- Write response valid. This signal indicates that the
-- channel is signaling a valid write response.
S_AXI_BVALID : out std_logic;
-- Response ready. This signal indicates that the master
-- can accept a write response.
S_AXI_BREADY : in std_logic;
-- Read address ID. This signal is the identification
-- tag for the read address group of signals.
S_AXI_ARID : in std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
-- Read address. This signal indicates the initial
-- address of a read burst transaction.
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Burst length. The burst length gives the exact number of transfers in a burst
S_AXI_ARLEN : in std_logic_vector(7 downto 0);
-- Burst size. This signal indicates the size of each transfer in the burst
S_AXI_ARSIZE : in std_logic_vector(2 downto 0);
-- Burst type. The burst type and the size information,
-- determine how the address for each transfer within the burst is calculated.
S_AXI_ARBURST : in std_logic_vector(1 downto 0);
-- Lock type. Provides additional information about the
-- atomic characteristics of the transfer.
S_AXI_ARLOCK : in std_logic;
-- Memory type. This signal indicates how transactions
-- are required to progress through a system.
S_AXI_ARCACHE : in std_logic_vector(3 downto 0);
-- Protection type. This signal indicates the privilege
-- and security level of the transaction, and whether
-- the transaction is a data access or an instruction access.
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
-- Quality of Service, QoS identifier sent for each
-- read transaction.
S_AXI_ARQOS : in std_logic_vector(3 downto 0);
-- Region identifier. Permits a single physical interface
-- on a slave to be used for multiple logical interfaces.
S_AXI_ARREGION : in std_logic_vector(3 downto 0);
-- Optional User-defined signal in the read address channel.
S_AXI_ARUSER : in std_logic_vector(C_S_AXI_ARUSER_WIDTH-1 downto 0);
-- Write address valid. This signal indicates that
-- the channel is signaling valid read address and
-- control information.
S_AXI_ARVALID : in std_logic;
-- Read address ready. This signal indicates that
-- the slave is ready to accept an address and associated
-- control signals.
S_AXI_ARREADY : out std_logic;
-- Read ID tag. This signal is the identification tag
-- for the read data group of signals generated by the slave.
S_AXI_RID : out std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
-- Read Data
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Read response. This signal indicates the status of
-- the read transfer.
S_AXI_RRESP : out std_logic_vector(1 downto 0);
-- Read last. This signal indicates the last transfer
-- in a read burst.
S_AXI_RLAST : out std_logic;
-- Optional User-defined signal in the read address channel.
S_AXI_RUSER : out std_logic_vector(C_S_AXI_RUSER_WIDTH-1 downto 0);
-- Read valid. This signal indicates that the channel
-- is signaling the required read data.
S_AXI_RVALID : out std_logic;
-- Read ready. This signal indicates that the master can
-- accept the read data and response information.
S_AXI_RREADY : in std_logic
);
end watchdogDevice_v1_0_S00_AXI;
architecture arch_imp of watchdogDevice_v1_0_S00_AXI is
-- AXI4FULL signals
signal axi_awaddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_awready : std_logic;
signal axi_wready : std_logic;
signal axi_bresp : std_logic_vector(1 downto 0);
signal axi_buser : std_logic_vector(C_S_AXI_BUSER_WIDTH-1 downto 0);
signal axi_bvalid : std_logic;
signal axi_araddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_arready : std_logic;
signal axi_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal axi_rresp : std_logic_vector(1 downto 0);
signal axi_rlast : std_logic;
signal axi_ruser : std_logic_vector(C_S_AXI_RUSER_WIDTH-1 downto 0);
signal axi_rvalid : std_logic;
-- aw_wrap_en determines wrap boundary and enables wrapping
signal aw_wrap_en : std_logic;
-- ar_wrap_en determines wrap boundary and enables wrapping
signal ar_wrap_en : std_logic;
-- aw_wrap_size is the size of the write transfer, the
-- write address wraps to a lower address if upper address
-- limit is reached
signal aw_wrap_size : integer;
-- ar_wrap_size is the size of the read transfer, the
-- read address wraps to a lower address if upper address
-- limit is reached
signal ar_wrap_size : integer;
-- The axi_awv_awr_flag flag marks the presence of write address valid
signal axi_awv_awr_flag : std_logic;
--The axi_arv_arr_flag flag marks the presence of read address valid
signal axi_arv_arr_flag : std_logic;
-- The axi_awlen_cntr internal write address counter to keep track of beats in a burst transaction
signal axi_awlen_cntr : std_logic_vector(7 downto 0);
--The axi_arlen_cntr internal read address counter to keep track of beats in a burst transaction
signal axi_arlen_cntr : std_logic_vector(7 downto 0);
signal axi_arburst : std_logic_vector(2-1 downto 0);
signal axi_awburst : std_logic_vector(2-1 downto 0);
signal axi_arlen : std_logic_vector(8-1 downto 0);
signal axi_awlen : std_logic_vector(8-1 downto 0);
--local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
--ADDR_LSB is used for addressing 32/64 bit registers/memories
--ADDR_LSB = 2 for 32 bits (n downto 2)
--ADDR_LSB = 3 for 42 bits (n downto 3)
constant ADDR_LSB : integer := (C_S_AXI_DATA_WIDTH/32)+ 1;
constant OPT_MEM_ADDR_BITS : integer := 3;
constant USER_NUM_MEM: integer := 1;
constant low : std_logic_vector (C_S_AXI_ADDR_WIDTH - 1 downto 0) := (OTHERS => '0');
CONSTANT c_usig_typdef_address : STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(c_fLink_typdef_address, C_S_AXI_ADDR_WIDTH));
CONSTANT c_usig_mem_size_address : STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(c_fLink_mem_size_address*4, C_S_AXI_ADDR_WIDTH));
CONSTANT c_usig_number_of_channels_address : STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(c_fLink_number_of_channels_address*4, C_S_AXI_ADDR_WIDTH));
CONSTANT c_usig_unique_id_address : STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(c_fLink_unique_id_address*4, C_S_AXI_ADDR_WIDTH));
CONSTANT c_usig_status_address : STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(c_fLink_status_address*4, C_S_AXI_ADDR_WIDTH));
CONSTANT c_usig_configuration_address : STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(c_fLink_configuration_address*4, C_S_AXI_ADDR_WIDTH));
CONSTANT c_usig_base_clk_address : STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(c_fLink_number_of_std_registers*4, C_S_AXI_ADDR_WIDTH));
CONSTANT c_usig_counter_val_address : STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 DOWNTO 0) := STD_LOGIC_VECTOR(unsigned(c_usig_base_clk_address)+4);
CONSTANT c_usig_max_address : STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 DOWNTO 0) := STD_LOGIC_VECTOR(unsigned(c_usig_counter_val_address)+4);
CONSTANT id : STD_LOGIC_VECTOR(15 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(c_fLink_watchdog_id, 16));
CONSTANT subtype_id : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
CONSTANT interface_version : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
TYPE t_internal_reg IS RECORD
counter_set_reg : UNSIGNED(C_S_AXI_DATA_WIDTH-1 DOWNTO 0);
reset_n : STD_LOGIC;
rearm : STD_LOGIC;
counter_changed : STD_LOGIC;
pwm_state : STD_LOGIC;
granted : STD_LOGIC;
END RECORD;
CONSTANT INTERNAL_REG_RESET : t_internal_reg := (
counter_set_reg => (OTHERS => '0'),
reset_n => '0',
rearm => '0',
counter_changed => '0',
pwm_state => '0',
granted => '0'
);
SIGNAL ri, ri_next : t_internal_reg := INTERNAL_REG_RESET;
SIGNAL granted : STD_LOGIC;
SIGNAL counter_val : UNSIGNED(C_S_AXI_DATA_WIDTH-1 DOWNTO 0);
------------------------------------------------
---- Signals for user logic memory space example
--------------------------------------------------
signal mem_address : std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
signal mem_select : std_logic_vector(USER_NUM_MEM-1 downto 0);
type word_array is array (0 to USER_NUM_MEM-1) of std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal mem_data_out : word_array;
signal i : integer;
signal j : integer;
signal mem_byte_index : integer;
type BYTE_RAM_TYPE is array (0 to 15) of std_logic_vector(7 downto 0);
begin
-- I/O Connections assignments
S_AXI_AWREADY <= axi_awready;
S_AXI_WREADY <= axi_wready;
S_AXI_BRESP <= axi_bresp;
S_AXI_BUSER <= axi_buser;
S_AXI_BVALID <= axi_bvalid;
S_AXI_ARREADY <= axi_arready;
S_AXI_RDATA <= axi_rdata;
S_AXI_RRESP <= axi_rresp;
S_AXI_RLAST <= axi_rlast;
S_AXI_RUSER <= axi_ruser;
S_AXI_RVALID <= axi_rvalid;
S_AXI_BID <= S_AXI_AWID;
S_AXI_RID <= S_AXI_ARID;
aw_wrap_size <= ((C_S_AXI_DATA_WIDTH)/8 * to_integer(unsigned(axi_awlen)));
ar_wrap_size <= ((C_S_AXI_DATA_WIDTH)/8 * to_integer(unsigned(axi_arlen)));
aw_wrap_en <= '1' when (((axi_awaddr AND std_logic_vector(to_unsigned(aw_wrap_size,C_S_AXI_ADDR_WIDTH))) XOR std_logic_vector(to_unsigned(aw_wrap_size,C_S_AXI_ADDR_WIDTH))) = low) else '0';
ar_wrap_en <= '1' when (((axi_araddr AND std_logic_vector(to_unsigned(ar_wrap_size,C_S_AXI_ADDR_WIDTH))) XOR std_logic_vector(to_unsigned(ar_wrap_size,C_S_AXI_ADDR_WIDTH))) = low) else '0';
-- Implement axi_awready generation
-- axi_awready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awready <= '0';
axi_awv_awr_flag <= '0';
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and axi_awv_awr_flag = '0' and axi_arv_arr_flag = '0') then
-- slave is ready to accept an address and
-- associated control signals
axi_awv_awr_flag <= '1'; -- used for generation of bresp() and bvalid
axi_awready <= '1';
elsif (S_AXI_WLAST = '1' and axi_wready = '1') then
-- preparing to accept next address after current write burst tx completion
axi_awv_awr_flag <= '0';
else
axi_awready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_awaddr latching
-- This process is used to latch the address when both
-- S_AXI_AWVALID and S_AXI_WVALID are valid.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awaddr <= (others => '0');
axi_awburst <= (others => '0');
axi_awlen <= (others => '0');
axi_awlen_cntr <= (others => '0');
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and axi_awv_awr_flag = '0') then
-- address latching
axi_awaddr <= S_AXI_AWADDR(C_S_AXI_ADDR_WIDTH - 1 downto 0); ---- start address of transfer
axi_awlen_cntr <= (others => '0');
axi_awburst <= S_AXI_AWBURST;
axi_awlen <= S_AXI_AWLEN;
elsif((axi_awlen_cntr <= axi_awlen) and axi_wready = '1' and S_AXI_WVALID = '1') then
axi_awlen_cntr <= std_logic_vector (unsigned(axi_awlen_cntr) + 1);
case (axi_awburst) is
when "00" => -- fixed burst
-- The write address for all the beats in the transaction are fixed
axi_awaddr <= axi_awaddr; ----for awsize = 4 bytes (010)
when "01" => --incremental burst
-- The write address for all the beats in the transaction are increments by awsize
axi_awaddr(C_S_AXI_ADDR_WIDTH - 1 downto ADDR_LSB) <= std_logic_vector (unsigned(axi_awaddr(C_S_AXI_ADDR_WIDTH - 1 downto ADDR_LSB)) + 1);--awaddr aligned to 4 byte boundary
axi_awaddr(ADDR_LSB-1 downto 0) <= (others => '0'); ----for awsize = 4 bytes (010)
when "10" => --Wrapping burst
-- The write address wraps when the address reaches wrap boundary
if (aw_wrap_en = '1') then
axi_awaddr <= std_logic_vector (unsigned(axi_awaddr) - (to_unsigned(aw_wrap_size,C_S_AXI_ADDR_WIDTH)));
else
axi_awaddr(C_S_AXI_ADDR_WIDTH - 1 downto ADDR_LSB) <= std_logic_vector (unsigned(axi_awaddr(C_S_AXI_ADDR_WIDTH - 1 downto ADDR_LSB)) + 1);--awaddr aligned to 4 byte boundary
axi_awaddr(ADDR_LSB-1 downto 0) <= (others => '0'); ----for awsize = 4 bytes (010)
end if;
when others => --reserved (incremental burst for example)
axi_awaddr(C_S_AXI_ADDR_WIDTH - 1 downto ADDR_LSB) <= std_logic_vector (unsigned(axi_awaddr(C_S_AXI_ADDR_WIDTH - 1 downto ADDR_LSB)) + 1);--for awsize = 4 bytes (010)
axi_awaddr(ADDR_LSB-1 downto 0) <= (others => '0');
end case;
end if;
end if;
end if;
end process;
-- Implement axi_wready generation
-- axi_wready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_wready <= '0';
else
if (axi_wready = '0' and S_AXI_WVALID = '1' and axi_awv_awr_flag = '1') then
axi_wready <= '1';
-- elsif (axi_awv_awr_flag = '0') then
elsif (S_AXI_WLAST = '1' and axi_wready = '1') then
axi_wready <= '0';
end if;
end if;
end if;
end process;
-- Implement write response logic generation
-- The write response and response valid signals are asserted by the slave
-- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
-- This marks the acceptance of address and indicates the status of
-- write transaction.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_bvalid <= '0';
axi_bresp <= "00"; --need to work more on the responses
axi_buser <= (others => '0');
else
if (axi_awv_awr_flag = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0' and S_AXI_WLAST = '1' ) then
axi_bvalid <= '1';
axi_bresp <= "00";
elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then
--check if bready is asserted while bvalid is high)
axi_bvalid <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_arready generation
-- axi_arready is asserted for one S_AXI_ACLK clock cycle when
-- S_AXI_ARVALID is asserted. axi_awready is
-- de-asserted when reset (active low) is asserted.
-- The read address is also latched when S_AXI_ARVALID is
-- asserted. axi_araddr is reset to zero on reset assertion.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_arready <= '0';
axi_arv_arr_flag <= '0';
else
if (axi_arready = '0' and S_AXI_ARVALID = '1' and axi_awv_awr_flag = '0' and axi_arv_arr_flag = '0') then
axi_arready <= '1';
axi_arv_arr_flag <= '1';
elsif (axi_rvalid = '1' and S_AXI_RREADY = '1' and (axi_arlen_cntr = axi_arlen)) then
-- preparing to accept next address after current read completion
axi_arv_arr_flag <= '0';
else
axi_arready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_araddr latching
--This process is used to latch the address when both
--S_AXI_ARVALID and S_AXI_RVALID are valid.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_araddr <= (others => '0');
axi_arburst <= (others => '0');
axi_arlen <= (others => '0');
axi_arlen_cntr <= (others => '0');
axi_rlast <= '0';
axi_ruser <= (others => '0');
else
if (axi_arready = '0' and S_AXI_ARVALID = '1' and axi_arv_arr_flag = '0') then
-- address latching
axi_araddr <= S_AXI_ARADDR(C_S_AXI_ADDR_WIDTH - 1 downto 0); ---- start address of transfer
axi_arlen_cntr <= (others => '0');
axi_rlast <= '0';
axi_arburst <= S_AXI_ARBURST;
axi_arlen <= S_AXI_ARLEN;
elsif((axi_arlen_cntr <= axi_arlen) and axi_rvalid = '1' and S_AXI_RREADY = '1') then
axi_arlen_cntr <= std_logic_vector (unsigned(axi_arlen_cntr) + 1);
axi_rlast <= '0';
case (axi_arburst) is
when "00" => -- fixed burst
-- The read address for all the beats in the transaction are fixed
axi_araddr <= axi_araddr; ----for arsize = 4 bytes (010)
when "01" => --incremental burst
-- The read address for all the beats in the transaction are increments by awsize
axi_araddr(C_S_AXI_ADDR_WIDTH - 1 downto ADDR_LSB) <= std_logic_vector (unsigned(axi_araddr(C_S_AXI_ADDR_WIDTH - 1 downto ADDR_LSB)) + 1); --araddr aligned to 4 byte boundary
axi_araddr(ADDR_LSB-1 downto 0) <= (others => '0'); ----for awsize = 4 bytes (010)
when "10" => --Wrapping burst
-- The read address wraps when the address reaches wrap boundary
if (ar_wrap_en = '1') then
axi_araddr <= std_logic_vector (unsigned(axi_araddr) - (to_unsigned(ar_wrap_size,C_S_AXI_ADDR_WIDTH)));
else
axi_araddr(C_S_AXI_ADDR_WIDTH - 1 downto ADDR_LSB) <= std_logic_vector (unsigned(axi_araddr(C_S_AXI_ADDR_WIDTH - 1 downto ADDR_LSB)) + 1); --araddr aligned to 4 byte boundary
axi_araddr(ADDR_LSB-1 downto 0) <= (others => '0'); ----for awsize = 4 bytes (010)
end if;
when others => --reserved (incremental burst for example)
axi_araddr(C_S_AXI_ADDR_WIDTH - 1 downto ADDR_LSB) <= std_logic_vector (unsigned(axi_araddr(C_S_AXI_ADDR_WIDTH - 1 downto ADDR_LSB)) + 1);--for arsize = 4 bytes (010)
axi_araddr(ADDR_LSB-1 downto 0) <= (others => '0');
end case;
elsif((axi_arlen_cntr = axi_arlen) and axi_rlast = '0' and axi_arv_arr_flag = '1') then
axi_rlast <= '1';
elsif (S_AXI_RREADY = '1') then
axi_rlast <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_arvalid generation
-- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_ARVALID and axi_arready are asserted. The slave registers
-- data are available on the axi_rdata bus at this instance. The
-- assertion of axi_rvalid marks the validity of read data on the
-- bus and axi_rresp indicates the status of read transaction.axi_rvalid
-- is deasserted on reset (active low). axi_rresp and axi_rdata are
-- cleared to zero on reset (active low).
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
ri <= ri_next;
if S_AXI_ARESETN = '0' then
axi_rvalid <= '0';
axi_rresp <= "00";
else
if (axi_arv_arr_flag = '1' and axi_rvalid = '0') then
axi_rvalid <= '1';
axi_rresp <= "00"; -- 'OKAY' response
elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then
axi_rvalid <= '0';
end if;
end if;
end if;
end process;
-- ------------------------------------------
-- -- Example code to access user logic memory region
-- ------------------------------------------
--read data
process( axi_rvalid,axi_araddr,ri ) is
begin
if (axi_rvalid = '1') then
-- output the read dada
IF(axi_araddr = c_usig_typdef_address) THEN
axi_rdata(31 DOWNTO 16) <= id;
axi_rdata(15 DOWNTO 8) <= subtype_id;
axi_rdata(7 DOWNTO 0) <= interface_version;
ELSIF(axi_araddr = c_usig_mem_size_address)THEN
axi_rdata <= (others => '0');
axi_rdata(C_S_AXI_ADDR_WIDTH) <= '1';
ELSIF(axi_araddr = c_usig_number_of_channels_address)THEN
axi_rdata <= std_logic_vector(to_unsigned(1,C_S_AXI_DATA_WIDTH));
ELSIF(axi_araddr = c_usig_unique_id_address) THEN
axi_rdata <= unique_id;
ELSIF(axi_araddr = c_usig_status_address) THEN
axi_rdata <= (OTHERS => '0');
axi_rdata(0) <= ri.granted;
ELSIF(axi_araddr = c_usig_configuration_address) THEN
axi_rdata <= (OTHERS => '0');
ELSIF(axi_araddr = c_usig_base_clk_address) THEN
axi_rdata <= STD_LOGIC_VECTOR(to_unsigned(base_clk,axi_rdata'length));
ELSIF (axi_araddr >= c_usig_counter_val_address AND axi_araddr < c_usig_max_address) THEN
axi_rdata <= STD_LOGIC_VECTOR(counter_val);
ELSE
axi_rdata <= (others => '0');
END IF;
else
axi_rdata <= (others => '0');
end if;
end process;
--write
process( axi_wready,S_AXI_WVALID,S_AXI_WDATA,axi_awaddr,S_AXI_WSTRB,ri,S_AXI_ARESETN,granted)
VARIABLE vi: t_internal_reg := INTERNAL_REG_RESET;
BEGIN
-- keep variables stable
vi := ri;
vi.granted := granted;
--standard values
vi.reset_n := '1';
vi.rearm := '0';
vi.counter_changed := '0';
IF(axi_wready = '1') THEN
IF(axi_awaddr >= c_usig_configuration_address AND axi_awaddr < c_usig_counter_val_address) THEN
IF(S_AXI_WSTRB(0) = '1')THEN
vi.rearm := S_AXI_WDATA(0);
END IF;
ELSIF(axi_awaddr >= c_usig_counter_val_address AND axi_awaddr < c_usig_max_address) THEN
IF(S_AXI_WSTRB(0) = '1')THEN
vi.counter_set_reg(7 DOWNTO 0) := unsigned(S_AXI_WDATA(7 DOWNTO 0));
vi.counter_changed := '1';
END IF;
IF(S_AXI_WSTRB(1) = '1')THEN
vi.counter_set_reg(15 DOWNTO 8) := unsigned(S_AXI_WDATA(15 DOWNTO 8));
vi.counter_changed := '1';
END IF;
IF(S_AXI_WSTRB(2) = '1')THEN
vi.counter_set_reg(23 DOWNTO 16) := unsigned(S_AXI_WDATA(23 DOWNTO 16));
vi.counter_changed := '1';
END IF;
IF(S_AXI_WSTRB(3) = '1')THEN
vi.counter_set_reg(31 DOWNTO 24) := unsigned(S_AXI_WDATA(31 DOWNTO 24));
vi.counter_changed := '1';
END IF;
vi.counter_changed := '1';
IF granted = '1' THEN
vi.pwm_state := NOT vi.pwm_state;
END IF;
END IF;
END IF;
IF(S_AXI_ARESETN = '0')THEN
vi := INTERNAL_REG_RESET;
END IF;
ri_next <= vi;
END PROCESS;
gen_wd: watchdog GENERIC MAP(gi_counter_resolution => C_S_AXI_DATA_WIDTH)
PORT MAP(S_AXI_ACLK, ri.reset_n, ri.counter_set_reg, ri.counter_changed, ri.rearm, counter_val, granted);
-- Add user logic here
osl_watchdog_pwm <= ri.pwm_state;
osl_granted <= ri.granted;
-- User logic ends
end arch_imp;
|
apache-2.0
|
flink-project/flinkvhdl
|
functionalBlocks/adcad7476/src/adcad7476A.m.vhd
|
1
|
7632
|
--------------------------------------------------------------------------------
-- ____ _____ __ __ ________ _______
-- | | \ \ | \ | | |__ __| | __ \
-- |____| \____\ | \| | | | | |__> )
-- ____ ____ | |\ \ | | | | __ <
-- | | | | | | \ | | | | |__> )
-- |____| |____| |__| \__| |__| |_______/
--
-- INTERSTATE UNIVERSITY OF AAPLIED SCIENCES OF TECHNOLOGY
--
-- Campus Buchs - Werdenbergstrasse 4 - CH-9471 Buchs
-- Campus Waldau - Schoenauweg4 - CH9013 St. Gallen
--
-- Tel. +41 (0)81 755 33 11 Fax +41 (0)81 756 54 34
--
--------------------------------------------------------------------------------
-- Project : ADC Interface for ADCS7476A
-- Unit : adcs7476A_interface
-- Author : Laszlo Arato
-- Created : June 2014
--------------------------------------------------------------------------------
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--------------------------------------------------------------------------------
-- ADCS7476A Analog-Digital Converter
-- SCLK max frequency = 20 MHz
-- t_convert = 16 x t_sclk
-- t_quiet = 50 ns min.
-- t2 = CS-to-SCLK Setup time = 10 ns min.
-- SCLK-to-Data Valid hold time = 7 ns
-- __ ______ _____________
-- CS \______________________________________/ \
-- <- t2 -> <- t_quiet ->
-- _______________ __ __ __ __ __ __ __ __ _ _ _ _
-- SCLK \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \_/ \_/ \_/ \_/ \_/ \_/
-- _______ _____ _____ _____ _____ _____ ______
-- SDATA -------<___Z3__X__Z2_X__Z1_X__Z0_X_D11_X_D10_X
-- Data is applied on the falling edge, so sample it on falling edge for maximum timing
-- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
-- 50 MHz Clock \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/
-- __ ______
-- CS \_____________________________________________________
-- __________ ___________ ___________
-- SCLK \___________/ \___________/ \___________/
-- ___ _______________________ _______________________ _______________________
-- SDATA ------< Z0X__________Z1___________X_______________________X_______________________
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
PACKAGE adcad7476A_pkg IS
COMPONENT adcad7476A IS
GENERIC(
base_clk : INTEGER := 33000000;
sclk_frequency : INTEGER := 8000000 -- max 20Mhz
);
PORT (
isl_reset : IN std_logic ; -- Reset
isl_clock : IN std_logic ; -- Clock
osl_adc_sclk : OUT std_logic; -- ADC clock
osl_adc_csn : OUT std_logic; -- ADC chip select not
isl_adc_sdata : IN std_logic; -- ADC serial data
oslv12_hex_data : OUT std_logic_vector(11 DOWNTO 0) -- ADC result out
);
END COMPONENT adcad7476A;
END PACKAGE adcad7476A_pkg;
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY adcad7476A IS
GENERIC(
base_clk : INTEGER := 33000000;
sclk_frequency : INTEGER := 8000000 -- max 20Mhz
);
PORT (
isl_reset : IN std_logic ; -- Reset
isl_clock : IN std_logic ; -- Clock
osl_adc_sclk : OUT std_logic; -- ADC clock
osl_adc_csn : OUT std_logic; -- ADC chip select not
isl_adc_sdata : IN std_logic; -- ADC serial data
oslv12_hex_data : OUT std_logic_vector(11 DOWNTO 0) -- ADC result out
);
END ENTITY adcad7476A;
-------------------------------------------------------------------------------
ARCHITECTURE rtl OF adcad7476A IS
CONSTANT cint_rx_bitcount : integer := 16;
TYPE t_fsm_state IS (INIT, CS_START, READ_Z3, SCLK_LOW, SCLK_HIGH);
TYPE t_adc_signals IS RECORD
sl_serial_clock : std_logic;
sl_chip_select_bar : std_logic;
fsm_state : t_fsm_state;
usig2_clk_div_count : unsigned(1 DOWNTO 0);
usig4_bit_count : unsigned(3 DOWNTO 0);
slv_rx_tmp_data : std_logic_vector(cint_rx_bitcount - 1 DOWNTO 0);
slv_rx_out_data : std_logic_vector(cint_rx_bitcount - 1 DOWNTO 0);
END RECORD;
SIGNAL r, r_next : t_adc_signals;
SIGNAL sl_reset : std_logic;
BEGIN
adc_comb_proc : PROCESS (isl_reset, isl_adc_sdata, r)
VARIABLE v : t_adc_signals;
BEGIN
v := r; -- Initialize variables
CASE r.fsm_state IS
WHEN INIT => v.sl_chip_select_bar := '1';
v.sl_serial_clock := '1';
v.slv_rx_out_data := r.slv_rx_tmp_data;
v.fsm_state := CS_START;
WHEN CS_START => v.sl_chip_select_bar := '0';
v.usig4_bit_count := to_unsigned(cint_rx_bitcount - 1,4);
v.usig2_clk_div_count := "10";
v.fsm_state := READ_Z3;
WHEN READ_Z3 => v.sl_serial_clock := '0';
v.fsm_state := SCLK_LOW;
WHEN SCLK_LOW => IF r.usig2_clk_div_count = 2 THEN
v.usig4_bit_count := r.usig4_bit_count - 1;
v.usig2_clk_div_count := r.usig2_clk_div_count - 1;
ELSIF r.usig2_clk_div_count > 0 THEN
v.usig2_clk_div_count := r.usig2_clk_div_count - 1;
ELSE
v.sl_serial_clock := '1';
v.usig2_clk_div_count := "10";
v.fsm_state := SCLK_HIGH;
END IF;
WHEN SCLK_HIGH => IF r.usig2_clk_div_count > 0 THEN
v.usig2_clk_div_count := r.usig2_clk_div_count - 1;
ELSE
IF r.usig4_bit_count = 0 THEN
v.fsm_state := INIT;
ELSE
v.sl_serial_clock := '0';
v.usig2_clk_div_count := "10";
v.fsm_state := SCLK_LOW;
END IF;
END IF;
WHEN OTHERS => v.fsm_state := INIT;
END CASE;
-- Sample Serial Data Values
IF r.fsm_state = SCLK_HIGH AND r.usig2_clk_div_count = 2 THEN
v.slv_rx_tmp_data(to_integer(r.usig4_bit_count)) := isl_adc_sdata;
END IF;
-- Reset State
IF isl_reset = '1' THEN
v.fsm_state := INIT;
END IF;
r_next <= v; -- Copy variables to signal
END PROCESS adc_comb_proc;
adc_reg_proc : PROCESS (isl_clock)
BEGIN
IF rising_edge(isl_clock) THEN
r <= r_next;
END IF;
END PROCESS adc_reg_proc;
osl_adc_sclk <= r.sl_serial_clock; -- ADC_SCLK
osl_adc_csn <= r.sl_chip_select_bar; -- ADC_CSN
oslv12_hex_data <= r.slv_rx_out_data(oslv12_hex_data'LENGTH - 1 DOWNTO 0);
END ARCHITECTURE rtl;
|
apache-2.0
|
flink-project/flinkvhdl
|
avalonComponents/subDevices/infoDevice/sim/info_device_tb.vhd
|
1
|
6819
|
-------------------------------------------------------------------------------
-- ____ _____ __ __ ________ _______
-- | | \ \ | \ | | |__ __| | __ \
-- |____| \____\ | \| | | | | |__> )
-- ____ ____ | |\ \ | | | | __ <
-- | | | | | | \ | | | | |__> )
-- |____| |____| |__| \__| |__| |_______/
--
-- NTB University of Applied Sciences in Technology
--
-- Campus Buchs - Werdenbergstrasse 4 - 9471 Buchs - Switzerland
-- Campus Waldau - Schoenauweg 4 - 9013 St. Gallen - Switzerland
--
-- Web http://www.ntb.ch Tel. +41 81 755 33 11
--
-------------------------------------------------------------------------------
-- Copyright 2013 NTB University of Applied Sciences in Technology
-------------------------------------------------------------------------------
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance witdh the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- witdhOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE IEEE.math_real.ALL;
USE work.fLink_definitions.ALL;
USE work.info_device_pkg.ALL;
ENTITY info_device_tb IS
END ENTITY info_device_tb;
ARCHITECTURE sim OF info_device_tb IS
CONSTANT main_period : TIME := 8 ns; -- 125MHz
CONSTANT dev_size: INTEGER := 128;
CONSTANT unique_id: STD_LOGIC_VECTOR(c_fLink_avs_data_width-1 DOWNTO 0) := x"00001337";
CONSTANT description: STD_LOGIC_VECTOR (c_int_number_of_descr_register*c_fLink_avs_data_width-1 DOWNTO 0) := x"000000000000000000000000000000664c696e6b2050726f6a656374"; --fLink Project
SIGNAL sl_clk : STD_LOGIC := '0';
SIGNAL sl_reset_n : STD_LOGIC := '1';
SIGNAL slv_avs_address : STD_LOGIC_VECTOR (info_device_address_width-1 DOWNTO 0):= (OTHERS =>'0');
SIGNAL sl_avs_read : STD_LOGIC:= '0';
SIGNAL sl_avs_write : STD_LOGIC:= '0';
SIGNAL slv_avs_write_data : STD_LOGIC_VECTOR(c_fLink_avs_data_width-1 DOWNTO 0):= (OTHERS =>'0');
SIGNAL slv_avs_read_data : STD_LOGIC_VECTOR(c_fLink_avs_data_width-1 DOWNTO 0):= (OTHERS =>'0');
SIGNAL slv_avs_byteenable : STD_LOGIC_VECTOR(c_fLink_avs_data_width_in_byte-1 DOWNTO 0):= (OTHERS =>'1');
BEGIN
--create component
my_unit_under_test : info_device
GENERIC MAP(
unique_id => unique_id,
description => description,
dev_size => dev_size
)
PORT MAP(
isl_clk => sl_clk,
isl_reset_n => sl_reset_n,
islv_avs_address => slv_avs_address,
isl_avs_read => sl_avs_read,
isl_avs_write => sl_avs_write,
islv_avs_write_data => slv_avs_write_data,
oslv_avs_read_data => slv_avs_read_data,
islv_avs_byteenable => slv_avs_byteenable
);
sl_clk <= NOT sl_clk after main_period/2;
tb_main_proc : PROCESS
BEGIN
sl_reset_n <= '0';
WAIT FOR 100*main_period;
sl_reset_n <= '1';
WAIT FOR main_period/2;
--test id register:
WAIT FOR 10*main_period;
sl_avs_read <= '1';
slv_avs_address <= STD_LOGIC_VECTOR(to_unsigned(c_fLink_typdef_address,info_device_address_width));
WAIT FOR main_period;
sl_avs_read <= '0';
slv_avs_address <= (OTHERS =>'0');
ASSERT slv_avs_read_data(c_fLink_interface_version_length-1 DOWNTO 0) = STD_LOGIC_VECTOR(to_unsigned(info_device_interface_version,c_fLink_interface_version_length))
REPORT "Interface Version Missmatch" SEVERITY FAILURE;
ASSERT slv_avs_read_data(c_fLink_interface_version_length+c_fLink_subtype_length-1 DOWNTO c_fLink_interface_version_length) = STD_LOGIC_VECTOR(to_unsigned(info_device_subtype_id,c_fLink_subtype_length))
REPORT "Subtype ID Missmatch" SEVERITY FAILURE;
ASSERT slv_avs_read_data(c_fLink_avs_data_width-1 DOWNTO c_fLink_interface_version_length+c_fLink_interface_version_length) = STD_LOGIC_VECTOR(to_unsigned(c_fLink_info_id,c_fLink_id_length))
REPORT "Type ID Missmatch" SEVERITY FAILURE;
--test mem size register register:
WAIT FOR 10*main_period;
sl_avs_read <= '1';
slv_avs_address <= STD_LOGIC_VECTOR(to_unsigned(c_fLink_mem_size_address,info_device_address_width));
WAIT FOR main_period;
sl_avs_read <= '0';
slv_avs_address <= (OTHERS =>'0');
ASSERT to_integer(UNSIGNED(slv_avs_read_data)) = 4*INTEGER(2**info_device_address_width)
REPORT "Memory Size Error: "&INTEGER'IMAGE(4*INTEGER(2**info_device_address_width))&"/"&INTEGER'IMAGE(to_integer(UNSIGNED(slv_avs_read_data))) SEVERITY FAILURE;
--test unique id register:
WAIT FOR 10*main_period;
sl_avs_read <= '1';
slv_avs_address <= STD_LOGIC_VECTOR(to_unsigned(c_fLink_unique_id_address,info_device_address_width));
WAIT FOR main_period;
sl_avs_read <= '0';
slv_avs_address <= (OTHERS =>'0');
ASSERT slv_avs_read_data = unique_id
REPORT "unique ID Error" SEVERITY FAILURE;
--test number of channels register:
WAIT FOR 10*main_period;
sl_avs_read <= '1';
slv_avs_address <= STD_LOGIC_VECTOR(to_unsigned(c_fLink_number_of_channels_address,info_device_address_width));
WAIT FOR main_period;
sl_avs_read <= '0';
slv_avs_address <= (OTHERS =>'0');
ASSERT slv_avs_read_data(c_fLink_interface_version_length-1 DOWNTO 0) = STD_LOGIC_VECTOR(to_unsigned(0,c_fLink_interface_version_length))
REPORT "Number of Channels Error" SEVERITY FAILURE;
--test dev_size
WAIT FOR 10*main_period;
sl_avs_read <= '1';
slv_avs_address <= STD_LOGIC_VECTOR(c_usig_dev_size_address);
WAIT FOR main_period;
sl_avs_read <= '0';
slv_avs_address <= (OTHERS =>'0');
ASSERT slv_avs_read_data = STD_LOGIC_VECTOR(to_unsigned(dev_size,c_fLink_avs_data_width))
REPORT "Number of Channels Error" SEVERITY FAILURE;
--test description
FOR i in c_int_number_of_descr_register-1 DOWNTO 0 LOOP
WAIT FOR 10*main_period;
sl_avs_read <= '1';
slv_avs_address <= STD_LOGIC_VECTOR(c_usig_description_address + to_unsigned(c_int_number_of_descr_register-i-1,info_device_address_width));
WAIT FOR main_period;
sl_avs_read <= '0';
slv_avs_address <= (OTHERS =>'0');
ASSERT slv_avs_read_data = description((i+1)*32-1 DOWNTO i*32)
REPORT "Test Description Error: "&INTEGER'IMAGE(i) SEVERITY FAILURE;
END LOOP;
WAIT FOR 10*main_period;
ASSERT false REPORT "End of simulation" SEVERITY FAILURE;
END PROCESS tb_main_proc;
END ARCHITECTURE sim;
|
apache-2.0
|
flink-project/flinkvhdl
|
avalonComponents/subDevices/avalon_watchdog_interface/sim/avalon_watchdog_interface_tb.vhd
|
1
|
11078
|
-------------------------------------------------------------------------------
-- ____ _____ __ __ ________ _______
-- | | \ \ | \ | | |__ __| | __ \
-- |____| \____\ | \| | | | | |__> )
-- ____ ____ | |\ \ | | | | __ <
-- | | | | | | \ | | | | |__> )
-- |____| |____| |__| \__| |__| |_______/
--
-- NTB University of Applied Sciences in Technology
--
-- Campus Buchs - Werdenbergstrasse 4 - 9471 Buchs - Switzerland
-- Campus Waldau - Schoenauweg 4 - 9013 St. Gallen - Switzerland
--
-- Web http://www.ntb.ch Tel. +41 81 755 33 11
--
-------------------------------------------------------------------------------
-- Copyright 2013 NTB University of Applied Sciences in Technology
-------------------------------------------------------------------------------
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE IEEE.math_real.ALL;
USE work.fLink_definitions.ALL;
USE work.avalon_watchdog_interface_pkg.ALL;
ENTITY avalon_watchdog_interface_tb IS
END ENTITY avalon_watchdog_interface_tb;
ARCHITECTURE sim OF avalon_watchdog_interface_tb IS
CONSTANT main_period : TIME := 8 ns; -- 125MHz
CONSTANT number_of_watchdogs : INTEGER := 1;
CONSTANT unique_id: STD_LOGIC_VECTOR (c_fLink_avs_data_width-1 DOWNTO 0) := x"00007764"; --wd
SIGNAL sl_clk : STD_LOGIC := '0';
SIGNAL sl_reset_n : STD_LOGIC := '1';
SIGNAL slv_avs_address : STD_LOGIC_VECTOR (c_watchdog_interface_address_width-1 DOWNTO 0):= (OTHERS =>'0');
SIGNAL sl_avs_read : STD_LOGIC:= '0';
SIGNAL sl_avs_write : STD_LOGIC:= '0';
SIGNAL slv_avs_write_data : STD_LOGIC_VECTOR(c_fLink_avs_data_width-1 DOWNTO 0):= (OTHERS =>'0');
SIGNAL slv_avs_read_data : STD_LOGIC_VECTOR(c_fLink_avs_data_width-1 DOWNTO 0):= (OTHERS =>'0');
SIGNAL sl_watchdog_pwm : STD_LOGIC := '0';
SIGNAL sl_granted : STD_LOGIC := '0';
SIGNAL slv_avs_byteenable : STD_LOGIC_VECTOR(c_fLink_avs_data_width_in_byte-1 DOWNTO 0) := (OTHERS =>'1');
BEGIN
--create component
my_unit_under_test : avalon_watchdog_interface
GENERIC MAP(
base_clk => 125000000,
unique_id => unique_id
)
PORT MAP(
isl_clk => sl_clk,
isl_reset_n => sl_reset_n,
islv_avs_address => slv_avs_address,
isl_avs_read => sl_avs_read,
isl_avs_write => sl_avs_write,
islv_avs_write_data => slv_avs_write_data,
islv_avs_byteenable => slv_avs_byteenable,
oslv_avs_read_data => slv_avs_read_data,
osl_watchdog_pwm => sl_watchdog_pwm,
osl_granted => sl_granted
);
sl_clk <= NOT sl_clk after main_period/2;
tb_main_proc : PROCESS
BEGIN
sl_reset_n <= '1';
WAIT FOR 100*main_period;
sl_reset_n <= '0';
WAIT FOR 100*main_period;
sl_reset_n <= '1';
WAIT FOR main_period/2;
--test id register:
WAIT FOR 10*main_period;
sl_avs_read <= '1';
slv_avs_address <= STD_LOGIC_VECTOR(to_unsigned(c_fLink_typdef_address,c_watchdog_interface_address_width));
WAIT FOR main_period;
sl_avs_read <= '0';
slv_avs_address <= (OTHERS =>'0');
ASSERT slv_avs_read_data(c_fLink_interface_version_length-1 DOWNTO 0) = STD_LOGIC_VECTOR(to_unsigned(c_watchdog_interface_version,c_fLink_interface_version_length))
REPORT "Interface Version Missmatch" SEVERITY FAILURE;
ASSERT slv_avs_read_data(c_fLink_interface_version_length+c_fLink_subtype_length-1 DOWNTO c_fLink_interface_version_length) = STD_LOGIC_VECTOR(to_unsigned(c_watchdog_subtype_id,c_fLink_subtype_length))
REPORT "Subtype ID Missmatch" SEVERITY FAILURE;
ASSERT slv_avs_read_data(c_fLink_avs_data_width-1 DOWNTO c_fLink_interface_version_length+c_fLink_interface_version_length) = STD_LOGIC_VECTOR(to_unsigned(c_fLink_watchdog_id,c_fLink_id_length))
REPORT "Type ID Missmatch" SEVERITY FAILURE;
--test mem size register register:
WAIT FOR 10*main_period;
sl_avs_read <= '1';
slv_avs_address <= STD_LOGIC_VECTOR(to_unsigned(c_fLink_mem_size_address,c_watchdog_interface_address_width));
WAIT FOR main_period;
sl_avs_read <= '0';
slv_avs_address <= (OTHERS =>'0');
ASSERT to_integer(UNSIGNED(slv_avs_read_data)) = 4*INTEGER(2**c_watchdog_interface_address_width)
REPORT "Memory Size Error: "&INTEGER'IMAGE(4*INTEGER(2**number_of_watchdogs))&"/"&INTEGER'IMAGE(to_integer(UNSIGNED(slv_avs_read_data))) SEVERITY FAILURE;
--test number of chanels register:
WAIT FOR 10*main_period;
sl_avs_read <= '1';
slv_avs_address <= STD_LOGIC_VECTOR(to_unsigned(c_fLink_number_of_channels_address,c_watchdog_interface_address_width));
WAIT FOR main_period;
sl_avs_read <= '0';
slv_avs_address <= (OTHERS =>'0');
ASSERT slv_avs_read_data(c_fLink_interface_version_length-1 DOWNTO 0) = STD_LOGIC_VECTOR(to_unsigned(number_of_watchdogs,c_fLink_interface_version_length))
REPORT "Number of Channels Error" SEVERITY FAILURE;
--test unic id register:
WAIT FOR 10*main_period;
sl_avs_read <= '1';
slv_avs_address <= STD_LOGIC_VECTOR(to_unsigned(c_fLink_unique_id_address,c_watchdog_interface_address_width));
WAIT FOR main_period;
sl_avs_read <= '0';
slv_avs_address <= (OTHERS =>'0');
ASSERT slv_avs_read_data = unique_id
REPORT "Unic Id Error" SEVERITY FAILURE;
--test base clock register
WAIT FOR 10*main_period;
sl_avs_read <= '1';
slv_avs_address <= STD_LOGIC_VECTOR(c_usig_base_clk_address);
WAIT FOR main_period;
sl_avs_read <= '0';
slv_avs_address <= (OTHERS =>'0');
ASSERT slv_avs_read_data(c_fLink_interface_version_length-1 DOWNTO 0) = STD_LOGIC_VECTOR(to_unsigned(125000000,c_fLink_interface_version_length))
REPORT "Base clock Error" SEVERITY FAILURE;
--test status register
WAIT FOR 10*main_period;
sl_avs_read <= '1';
slv_avs_address <= STD_LOGIC_VECTOR(c_usig_wd_status_conf_address);
WAIT FOR main_period;
sl_avs_read <= '0';
slv_avs_address <= (OTHERS =>'0');
ASSERT slv_avs_read_data(c_int_status_bit) = '0' REPORT "osl_granted should be zero at this point" SEVERITY FAILURE;
ASSERT slv_avs_read_data(c_int_rearm_bit) = '0' REPORT "Rearm not set to zero after reset" SEVERITY FAILURE;
-- test set counter register
WAIT FOR 10*main_period;
sl_avs_write <= '1';
slv_avs_address <= STD_LOGIC_VECTOR(c_usig_counter_address);
slv_avs_write_data <= STD_LOGIC_VECTOR(to_unsigned(100,c_fLink_avs_data_width));
WAIT FOR main_period;
sl_avs_write <= '0';
slv_avs_address <= (OTHERS =>'0');
slv_avs_write_data <= (OTHERS =>'0');
WAIT FOR main_period;
sl_avs_read <= '1';
slv_avs_address <= STD_LOGIC_VECTOR(c_usig_counter_address);
WAIT FOR main_period;
sl_avs_read <= '0';
slv_avs_address <= (OTHERS =>'0');
ASSERT slv_avs_read_data = STD_LOGIC_VECTOR(to_unsigned(100,c_fLink_avs_data_width))
REPORT "counter not stayed at set value" SEVERITY FAILURE;
--rearm
WAIT FOR 10*main_period;
sl_avs_write <= '1';
slv_avs_address <= STD_LOGIC_VECTOR(c_usig_wd_status_conf_address);
slv_avs_write_data(c_int_rearm_bit) <= '1';
WAIT FOR main_period;
sl_avs_write <= '0';
slv_avs_address <= (OTHERS =>'0');
slv_avs_write_data <= (OTHERS =>'0');
WAIT FOR main_period;
sl_avs_read <= '1';
slv_avs_address <= STD_LOGIC_VECTOR(c_usig_wd_status_conf_address);
WAIT FOR main_period;
sl_avs_read <= '0';
slv_avs_address <= (OTHERS =>'0');
ASSERT slv_avs_read_data(c_int_status_bit) = '1' REPORT "osl_granted should be set at this point" SEVERITY FAILURE;
ASSERT slv_avs_read_data(c_int_rearm_bit) = '0' REPORT "Rearm not set because self clearing" SEVERITY FAILURE;
-- set counter again
WAIT FOR 10*main_period;
sl_avs_write <= '1';
slv_avs_address <= STD_LOGIC_VECTOR(c_usig_counter_address);
slv_avs_write_data <= STD_LOGIC_VECTOR(to_unsigned(100,c_fLink_avs_data_width));
WAIT FOR main_period;
sl_avs_write <= '0';
slv_avs_address <= (OTHERS =>'0');
slv_avs_write_data <= (OTHERS =>'0');
-- test granted again
WAIT FOR 10*main_period;
sl_avs_read <= '1';
slv_avs_address <= STD_LOGIC_VECTOR(c_usig_wd_status_conf_address);
WAIT FOR main_period;
sl_avs_read <= '0';
slv_avs_address <= (OTHERS =>'0');
ASSERT slv_avs_read_data(c_int_status_bit) = '1' REPORT "osl_granted should be set at this point" SEVERITY FAILURE;
ASSERT slv_avs_read_data(c_int_rearm_bit) = '0' REPORT "Rearm not set because self clearing" SEVERITY FAILURE;
-- write counter again to see if pwm chages
WAIT FOR 10*main_period;
sl_avs_write <= '1';
slv_avs_address <= STD_LOGIC_VECTOR(c_usig_counter_address);
slv_avs_write_data <= STD_LOGIC_VECTOR(to_unsigned(100,c_fLink_avs_data_width));
WAIT FOR main_period;
sl_avs_write <= '0';
slv_avs_address <= (OTHERS =>'0');
slv_avs_write_data <= (OTHERS =>'0');
-- read counter
WAIT FOR 10*main_period;
sl_avs_read <= '1';
slv_avs_address <= STD_LOGIC_VECTOR(c_usig_counter_address);
WAIT FOR main_period;
sl_avs_read <= '0';
slv_avs_address <= (OTHERS =>'0');
-- wait and see if osl_granted goes low
WAIT FOR 91*main_period;
sl_avs_read <= '1';
slv_avs_address <= STD_LOGIC_VECTOR(c_usig_wd_status_conf_address);
WAIT FOR main_period;
sl_avs_read <= '0';
slv_avs_address <= (OTHERS =>'0');
ASSERT slv_avs_read_data(c_int_status_bit) = '0' REPORT "osl_granted should be zero at this point" SEVERITY FAILURE;
ASSERT slv_avs_read_data(c_int_rearm_bit) = '0' REPORT "Rearm not set because self clearing" SEVERITY FAILURE;
-- rearm and then reset and see what happends:
WAIT FOR 100*main_period;
sl_avs_write <= '1';
slv_avs_address <= STD_LOGIC_VECTOR(c_usig_counter_address);
slv_avs_write_data <= STD_LOGIC_VECTOR(to_unsigned(100,c_fLink_avs_data_width));
WAIT FOR main_period;
sl_avs_write <= '0';
slv_avs_address <= (OTHERS =>'0');
slv_avs_write_data <= (OTHERS =>'0');
WAIT FOR 10*main_period;
sl_avs_write <= '1';
slv_avs_address <= STD_LOGIC_VECTOR(c_usig_wd_status_conf_address);
slv_avs_write_data(c_int_rearm_bit) <= '1';
WAIT FOR main_period;
sl_avs_write <= '0';
slv_avs_address <= (OTHERS =>'0');
slv_avs_write_data <= (OTHERS =>'0');
WAIT FOR 20*main_period;
sl_reset_n <= '0';
WAIT FOR 100*main_period;
sl_reset_n <= '1';
WAIT FOR 1000*main_period;
ASSERT false REPORT "End of simulation" SEVERITY FAILURE;
END PROCESS tb_main_proc;
END ARCHITECTURE sim;
|
apache-2.0
|
flink-project/flinkvhdl
|
functionalBlocks/ppwa/sim/ppwa_rtl_tb.vhd
|
1
|
2825
|
-------------------------------------------------------------------------------
-- ____ _____ __ __ ________ _______
-- | | \ \ | \ | | |__ __| | __ \
-- |____| \____\ | \| | | | | |__> )
-- ____ ____ | |\ \ | | | | __ <
-- | | | | | | \ | | | | |__> )
-- |____| |____| |__| \__| |__| |_______/
--
-- NTB University of Applied Sciences in Technology
--
-- Campus Buchs - Werdenbergstrasse 4 - 9471 Buchs - Switzerland
-- Campus Waldau - Schoenauweg 4 - 9013 St. Gallen - Switzerland
--
-- Web http://www.ntb.ch Tel. +41 81 755 33 11
--
-------------------------------------------------------------------------------
-- Copyright 2013 NTB University of Applied Sciences in Technology
-------------------------------------------------------------------------------
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE work.ppwa_pkg.ALL;
ENTITY ppwa_rtl_tb IS
END ENTITY ppwa_rtl_tb;
ARCHITECTURE sim OF ppwa_rtl_tb IS
--Sumulation Parameter:
CONSTANT main_period : TIME := 8 ns; -- 125MHz
CONSTANT measure_period : TIME := 800 ns; -- 12.5MHz
CONSTANT resolution : INTEGER := 32;
SIGNAL sl_clk : STD_LOGIC := '0';
SIGNAL sl_reset_n : STD_LOGIC := '0';
SIGNAL sl_measure_signal : STD_LOGIC := '0';
SIGNAL usig_period_count : UNSIGNED(resolution - 1 DOWNTO 0);
SIGNAL usig_hightime_count : UNSIGNED(resolution - 1 DOWNTO 0);
BEGIN
--create component
my_unit_under_test : ppwa
GENERIC MAP(resolution)
PORT MAP(
isl_clk => sl_clk,
isl_reset_n => sl_reset_n,
isl_measure_signal => sl_measure_signal,
ousig_period_count => usig_period_count,
ousig_hightime_count => usig_hightime_count
);
sl_clk <= NOT sl_clk after main_period/2;
sl_measure_signal <= NOT sl_measure_signal after measure_period/2;
tb_main_proc : PROCESS
BEGIN
sl_reset_n <= '0';
WAIT FOR 2*main_period;
sl_reset_n <= '1';
WAIT FOR 1000*main_period;
ASSERT false REPORT "End of simulation" SEVERITY FAILURE;
END PROCESS tb_main_proc;
END ARCHITECTURE sim;
|
apache-2.0
|
flink-project/flinkvhdl
|
fLink/core/const_test_vector.m.vhd
|
1
|
1501
|
--------------------------------------------------------------------------------------
-- _ _ _____ _ _____ _____ _____ _____ _ _____ _ __
-- | | / / / _ \ | | |_ _| | ____| | _ \ | ___| | | / _ \ | | / /
-- | | / / | | | | | | | | | |__ | | | | | |__ | | | | | | | | __ / /
-- | | / / | | | | | | | | | __| | | | | | __| | | | | | | | | / | / /
-- | |/ / | |_| | | |__ | | | |___ | |_| | | | | |___ | |_| | | |/ |/ /
-- |___/ \_____/ |_____| |_| |_____| |_____/ |_| |_____| \_____/ |___/|___/
--
-------------------------------------------------------------------------------------
-- OCI O'Connor Informatics
-- Allwegmatte 10
-- CH 6372 Ennetmoos, Switzerland
--
-----------------------------------------------------------------------------------
-- Unit : const_test_vector.m.vhd
-- Author : Marco Tinner, NTB Buchs
-- Created : July 2012
-----------------------------------------------------------------------------------
-- Copyright(C) 2012: OCI O'Connor Informatics, Switzerland
-----------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY const_test_vector IS
PORT (
test_out: OUT std_logic_vector(39 DOWNTO 0)
);
END ENTITY const_test_vector;
ARCHITECTURE rtl OF const_test_vector IS
BEGIN
test_out <= x"00000000A8";
END ARCHITECTURE rtl;
|
apache-2.0
|
flink-project/flinkvhdl
|
avalonComponents/subDevices/avalon_dacad5668_interface/sim/avalon_dacad5668_interface_tb.vhd
|
1
|
6152
|
-------------------------------------------------------------------------------
-- ____ _____ __ __ ________ _______
-- | | \ \ | \ | | |__ __| | __ \
-- |____| \____\ | \| | | | | |__> )
-- ____ ____ | |\ \ | | | | __ <
-- | | | | | | \ | | | | |__> )
-- |____| |____| |__| \__| |__| |_______/
--
-- NTB University of Applied Sciences in Technology
--
-- Campus Buchs - Werdenbergstrasse 4 - 9471 Buchs - Switzerland
-- Campus Waldau - Schoenauweg 4 - 9013 St. Gallen - Switzerland
--
-- Web http://www.ntb.ch Tel. +41 81 755 33 11
--
-------------------------------------------------------------------------------
-- Copyright 2013 NTB University of Applied Sciences in Technology
-------------------------------------------------------------------------------
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE IEEE.math_real.ALL;
USE work.fLink_definitions.ALL;
USE work.avalon_dacad5668_interface_pkg.ALL;
USE work.dacad5668_pkg.ALL;
ENTITY avalon_dacad5668_interface_tb IS
END ENTITY avalon_dacad5668_interface_tb;
ARCHITECTURE sim OF avalon_dacad5668_interface_tb IS
CONSTANT main_period : TIME := 8 ns; -- 125MHz
CONSTANT unique_id: STD_LOGIC_VECTOR (c_fLink_avs_data_width-1 DOWNTO 0) := x"00646163"; --dac
SIGNAL sl_clk : STD_LOGIC := '0';
SIGNAL sl_reset_n : STD_LOGIC := '1';
SIGNAL slv_avs_address : STD_LOGIC_VECTOR (c_analog_output_interface_address_width-1 DOWNTO 0):= (OTHERS =>'0');
SIGNAL sl_avs_read : STD_LOGIC:= '0';
SIGNAL sl_avs_write : STD_LOGIC:= '0';
SIGNAL slv_avs_write_data : STD_LOGIC_VECTOR(c_fLink_avs_data_width-1 DOWNTO 0):= (OTHERS =>'0');
SIGNAL slv_avs_read_data : STD_LOGIC_VECTOR(c_fLink_avs_data_width-1 DOWNTO 0):= (OTHERS =>'0');
SIGNAL slv_avs_byteenable : STD_LOGIC_VECTOR(c_fLink_avs_data_width_in_byte-1 DOWNTO 0):= (OTHERS =>'1');
SIGNAL sl_sclk : STD_LOGIC:= '0';
SIGNAL slv_Ss : STD_LOGIC:= '0';
SIGNAL sl_mosi : STD_LOGIC:= '0';
SIGNAL sl_LDAC_n : STD_LOGIC:= '0';
SIGNAL sl_CLR_n : STD_LOGIC:= '0';
BEGIN
--create component
my_unit_under_test : avalon_dacad5668_interface
GENERIC MAP(
BASE_CLK => 33000000,
SCLK_FREQUENCY => 1000000,
INTERNAL_REFERENCE => '1',
UNIQUE_ID => unique_id
)
PORT MAP(
isl_clk => sl_clk,
isl_reset_n => sl_reset_n,
islv_avs_address => slv_avs_address,
isl_avs_read => sl_avs_read,
isl_avs_write => sl_avs_write,
islv_avs_write_data => slv_avs_write_data,
islv_avs_byteenable => slv_avs_byteenable,
oslv_avs_read_data => slv_avs_read_data,
osl_sclk => sl_sclk,
oslv_Ss => slv_Ss,
osl_mosi => sl_mosi,
osl_LDAC_n => sl_LDAC_n,
osl_CLR_n => sl_CLR_n
);
sl_clk <= NOT sl_clk after main_period/2;
tb_main_proc : PROCESS
BEGIN
sl_reset_n <= '0';
WAIT FOR 100*main_period;
sl_reset_n <= '1';
WAIT FOR main_period/2;
--test id register:
WAIT FOR 10*main_period;
sl_avs_read <= '1';
slv_avs_address <= STD_LOGIC_VECTOR(to_unsigned(c_fLink_typdef_address,c_analog_output_interface_address_width));
WAIT FOR main_period;
sl_avs_read <= '0';
slv_avs_address <= (OTHERS =>'0');
ASSERT slv_avs_read_data(c_fLink_interface_version_length-1 DOWNTO 0) = c_dacad5668_interface_version
REPORT "Interface Version Missmatch" SEVERITY FAILURE;
ASSERT slv_avs_read_data(c_fLink_interface_version_length+c_fLink_subtype_length-1 DOWNTO c_fLink_interface_version_length) = c_dacad5668_subtype_id
REPORT "Subtype ID Missmatch" SEVERITY FAILURE;
ASSERT slv_avs_read_data(c_fLink_avs_data_width-1 DOWNTO c_fLink_interface_version_length+c_fLink_interface_version_length) = STD_LOGIC_VECTOR(to_unsigned(c_fLink_analog_output_id,c_fLink_id_length))
REPORT "Type ID Missmatch" SEVERITY FAILURE;
--test mem size register register:
WAIT FOR 10*main_period;
sl_avs_read <= '1';
slv_avs_address <= STD_LOGIC_VECTOR(to_unsigned(c_fLink_mem_size_address,c_analog_output_interface_address_width));
WAIT FOR main_period;
sl_avs_read <= '0';
slv_avs_address <= (OTHERS =>'0');
ASSERT to_integer(UNSIGNED(slv_avs_read_data)) = 4*INTEGER(2**c_analog_output_interface_address_width)
REPORT "Memory Size Error: "&INTEGER'IMAGE(4*INTEGER(2**NUMBER_OF_CHANNELS))&"/"&INTEGER'IMAGE(to_integer(UNSIGNED(slv_avs_read_data))) SEVERITY FAILURE;
--test unic id register:
WAIT FOR 10*main_period;
sl_avs_read <= '1';
slv_avs_address <= STD_LOGIC_VECTOR(to_unsigned(c_fLink_unique_id_address,c_analog_output_interface_address_width));
WAIT FOR main_period;
sl_avs_read <= '0';
slv_avs_address <= (OTHERS =>'0');
ASSERT slv_avs_read_data = unique_id
REPORT "Unic Id Error" SEVERITY FAILURE;
--test number of channels register:
WAIT FOR 10*main_period;
sl_avs_read <= '1';
slv_avs_address <= STD_LOGIC_VECTOR(to_unsigned(c_fLink_number_of_channels_address,c_analog_output_interface_address_width));
WAIT FOR main_period;
sl_avs_read <= '0';
slv_avs_address <= (OTHERS =>'0');
ASSERT slv_avs_read_data(c_fLink_interface_version_length-1 DOWNTO 0) = STD_LOGIC_VECTOR(to_unsigned(NUMBER_OF_CHANNELS,c_fLink_interface_version_length))
REPORT "Number of Channels Error" SEVERITY FAILURE;
WAIT FOR 10000*main_period;
ASSERT false REPORT "End of simulation" SEVERITY FAILURE;
END PROCESS tb_main_proc;
END ARCHITECTURE sim;
|
apache-2.0
|
flink-project/flinkvhdl
|
fLink/core/flink_definitions.vhd
|
1
|
4333
|
-------------------------------------------------------------------------------
-- _________ _____ _____ ____ _____ ___ ____ --
-- |_ ___ | |_ _| |_ _| |_ \|_ _| |_ ||_ _| --
-- | |_ \_| | | | | | \ | | | |_/ / --
-- | _| | | _ | | | |\ \| | | __'. --
-- _| |_ _| |__/ | _| |_ _| |_\ |_ _| | \ \_ --
-- |_____| |________| |_____| |_____|\____| |____||____| --
-- --
-------------------------------------------------------------------------------
-- --
-- fLink definitions --
-- --
-- THIS FILE WAS CREATED AUTOMATICALLY - do not change --
-- --
-- Created with: flinkinterface/func_id/ --
-- create_flink_definitions.vhd_flinkVHDL.sh --
-- --
-------------------------------------------------------------------------------
-- Copyright 2014 NTB University of Applied Sciences in Technology --
-- --
-- Licensed under the Apache License, Version 2.0 (the "License"); --
-- you may not use this file except in compliance with the License. --
-- You may obtain a copy of the License at --
-- --
-- http://www.apache.org/licenses/LICENSE-2.0 --
-- --
-- Unless required by applicable law or agreed to in writing, software --
-- distributed under the License is distributed on an "AS IS" BASIS, --
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. --
-- See the License for the specific language governing permissions and --
-- limitations under the License. --
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
PACKAGE fLink_definitions IS
-- Global
CONSTANT c_fLink_avs_data_width : INTEGER := 32;
CONSTANT c_fLink_avs_data_width_in_byte : INTEGER := c_fLink_avs_data_width/8;
-- Header registers
CONSTANT c_fLink_number_of_std_registers : INTEGER := 8;
CONSTANT c_fLink_typdef_address : INTEGER := 0;
CONSTANT c_fLink_mem_size_address : INTEGER := 1;
CONSTANT c_fLink_number_of_channels_address : INTEGER := 2;
CONSTANT c_fLink_unique_id_address : INTEGER := 3;
CONSTANT c_fLink_status_address : INTEGER := 4;
CONSTANT c_fLink_configuration_address : INTEGER := 5;
CONSTANT c_fLink_id_length : INTEGER := 16;
CONSTANT c_fLink_subtype_length : INTEGER := 8;
CONSTANT c_fLink_interface_version_length : INTEGER := 8;
CONSTANT c_fLink_reset_bit_num : INTEGER := 0;
-- Interface IDs:
CONSTANT c_fLink_info_id : INTEGER RANGE 0 TO 65535 := 0;
CONSTANT c_fLink_analog_input_id : INTEGER RANGE 0 TO 65535 := 1;
CONSTANT c_fLink_analog_output_id : INTEGER RANGE 0 TO 65535 := 2;
CONSTANT c_fLink_digital_io_id : INTEGER RANGE 0 TO 65535 := 5;
CONSTANT c_fLink_counter_id : INTEGER RANGE 0 TO 65535 := 6;
CONSTANT c_fLink_timer_id : INTEGER RANGE 0 TO 65535 := 7;
CONSTANT c_fLink_memory_id : INTEGER RANGE 0 TO 65535 := 8;
CONSTANT c_fLink_pwm_out_id : INTEGER RANGE 0 TO 65535 := 12;
CONSTANT c_fLink_ppwa_id : INTEGER RANGE 0 TO 65535 := 13;
CONSTANT c_fLink_uart_id : INTEGER RANGE 0 TO 65535 := 15;
CONSTANT c_fLink_watchdog_id : INTEGER RANGE 0 TO 65535 := 16;
CONSTANT c_fLink_sensor_id : INTEGER RANGE 0 TO 65535 := 17;
END PACKAGE fLink_definitions;
|
apache-2.0
|
flink-project/flinkvhdl
|
avalonComponents/subDevices/avalon_fqd_counter_interface/sim/avalon_fqd_counter_interface_tb.vhd
|
1
|
7868
|
-------------------------------------------------------------------------------
-- _________ _____ _____ ____ _____ ___ ____ --
-- |_ ___ | |_ _| |_ _| |_ \|_ _| |_ ||_ _| --
-- | |_ \_| | | | | | \ | | | |_/ / --
-- | _| | | _ | | | |\ \| | | __'. --
-- _| |_ _| |__/ | _| |_ _| |_\ |_ _| | \ \_ --
-- |_____| |________| |_____| |_____|\____| |____||____| --
-- --
-------------------------------------------------------------------------------
-- --
-- Test bench to "Avalon MM interface for FQD" --
-- --
-------------------------------------------------------------------------------
-- Copyright 2014 NTB University of Applied Sciences in Technology --
-- --
-- Licensed under the Apache License, Version 2.0 (the "License"); --
-- you may not use this file except in compliance with the License. --
-- You may obtain a copy of the License at --
-- --
-- http://www.apache.org/licenses/LICENSE-2.0 --
-- --
-- Unless required by applicable law or agreed to in writing, software --
-- distributed under the License is distributed on an "AS IS" BASIS, --
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. --
-- See the License for the specific language governing permissions and --
-- limitations under the License. --
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE IEEE.math_real.ALL;
USE work.fLink_definitions.ALL;
USE work.avalon_fqd_counter_interface_pkg.ALL;
ENTITY avalon_fqd_counter_interface_tb IS
END ENTITY avalon_fqd_counter_interface_tb;
ARCHITECTURE sim OF avalon_fqd_counter_interface_tb IS
CONSTANT main_period : TIME := 8 ns; -- 125MHz
CONSTANT number_of_fqds : INTEGER := 1;
CONSTANT velocity : REAL := 20000.0;--500.0; --1/s
CONSTANT direction : INTEGER := 1; -- forwards:1 backwards: -1
CONSTANT enc_tick_per_turn : REAL := 512.0;
CONSTANT wait_time : TIME := (1.0 / velocity / enc_tick_per_turn / 4.0) * 1 sec;
CONSTANT unique_id: STD_LOGIC_VECTOR (c_fLink_avs_data_width-1 DOWNTO 0) := x"00667164"; --fqd
SIGNAL sl_clk : STD_LOGIC := '0';
SIGNAL sl_reset_n : STD_LOGIC := '0';
SIGNAL slv_avs_address : STD_LOGIC_VECTOR (c_counter_interface_address_width-1 DOWNTO 0):= (OTHERS =>'0');
SIGNAL sl_avs_read : STD_LOGIC:= '0';
SIGNAL sl_avs_write : STD_LOGIC:= '0';
SIGNAL slv_avs_write_data : STD_LOGIC_VECTOR(c_fLink_avs_data_width-1 DOWNTO 0):= (OTHERS =>'0');
SIGNAL slv_avs_read_data : STD_LOGIC_VECTOR(c_fLink_avs_data_width-1 DOWNTO 0):= (OTHERS =>'0');
SIGNAL slv_enc_A : STD_LOGIC_VECTOR(number_of_fqds-1 DOWNTO 0):= (OTHERS =>'0');
SIGNAL slv_enc_B : STD_LOGIC_VECTOR(number_of_fqds-1 DOWNTO 0):= (OTHERS =>'0');
SIGNAL slv_avs_byteenable : STD_LOGIC_VECTOR(c_fLink_avs_data_width_in_byte-1 DOWNTO 0) := (OTHERS =>'1');
BEGIN
--create component
my_unit_under_test : avalon_fqd_counter_interface
GENERIC MAP(
number_of_fqds =>number_of_fqds,
unique_id => unique_id
)
PORT MAP(
isl_clk => sl_clk,
isl_reset_n => sl_reset_n,
islv_avs_address => slv_avs_address,
isl_avs_read => sl_avs_read,
isl_avs_write => sl_avs_write,
islv_avs_write_data => slv_avs_write_data,
islv_avs_byteenable => slv_avs_byteenable,
oslv_avs_read_data => slv_avs_read_data,
islv_enc_A => slv_enc_A,
islv_enc_B => slv_enc_B
);
sl_clk <= NOT sl_clk after main_period/2;
tb_main_proc : PROCESS
BEGIN
sl_reset_n <= '0';
WAIT FOR 2*main_period;
sl_reset_n <= '1';
WAIT FOR main_period/2;
--test id register:
WAIT FOR 10*main_period;
sl_avs_read <= '1';
slv_avs_address <= STD_LOGIC_VECTOR(to_unsigned(c_fLink_typdef_address,c_counter_interface_address_width));
WAIT FOR main_period;
sl_avs_read <= '0';
slv_avs_address <= (OTHERS =>'0');
ASSERT slv_avs_read_data(c_fLink_interface_version_length-1 DOWNTO 0) = STD_LOGIC_VECTOR(to_unsigned(c_fqd_interface_version,c_fLink_interface_version_length))
REPORT "Interface Version Missmatch" SEVERITY FAILURE;
ASSERT slv_avs_read_data(c_fLink_interface_version_length+c_fLink_subtype_length-1 DOWNTO c_fLink_interface_version_length) = STD_LOGIC_VECTOR(to_unsigned(c_fqd_subtype_id,c_fLink_subtype_length))
REPORT "Subtype ID Missmatch" SEVERITY FAILURE;
ASSERT slv_avs_read_data(c_fLink_avs_data_width-1 DOWNTO c_fLink_interface_version_length+c_fLink_interface_version_length) = STD_LOGIC_VECTOR(to_unsigned(c_fLink_counter_id,c_fLink_id_length))
REPORT "Type ID Missmatch" SEVERITY FAILURE;
--test mem size register register:
WAIT FOR 10*main_period;
sl_avs_read <= '1';
slv_avs_address <= STD_LOGIC_VECTOR(to_unsigned(c_fLink_mem_size_address,c_counter_interface_address_width));
WAIT FOR main_period;
sl_avs_read <= '0';
slv_avs_address <= (OTHERS =>'0');
ASSERT to_integer(UNSIGNED(slv_avs_read_data)) = 4*INTEGER(2**c_counter_interface_address_width)
REPORT "Memory Size Error: "&INTEGER'IMAGE(4*INTEGER(2**ceil(log2(REAL(number_of_fqds+c_fLink_number_of_std_registers)))))&"/"&INTEGER'IMAGE(to_integer(UNSIGNED(slv_avs_read_data))) SEVERITY FAILURE;
--test number of channels register:
WAIT FOR 10*main_period;
sl_avs_read <= '1';
slv_avs_address <= STD_LOGIC_VECTOR(to_unsigned(c_fLink_number_of_channels_address,c_counter_interface_address_width));
WAIT FOR main_period;
sl_avs_read <= '0';
slv_avs_address <= (OTHERS =>'0');
ASSERT slv_avs_read_data(c_fLink_interface_version_length-1 DOWNTO 0) = STD_LOGIC_VECTOR(to_unsigned(number_of_fqds,c_fLink_interface_version_length))
REPORT "Number of Channels Error" SEVERITY FAILURE;
--test unic id register:
WAIT FOR 10*main_period;
sl_avs_read <= '1';
slv_avs_address <= STD_LOGIC_VECTOR(to_unsigned(c_fLink_unique_id_address,c_counter_interface_address_width));
WAIT FOR main_period;
sl_avs_read <= '0';
slv_avs_address <= (OTHERS =>'0');
ASSERT slv_avs_read_data = unique_id
REPORT "Unic Id Error" SEVERITY FAILURE;
--test number of chanels register:
WAIT FOR 1000*main_period;
sl_avs_read <= '1';
slv_avs_address <= STD_LOGIC_VECTOR(to_unsigned(c_fLink_number_of_std_registers,c_counter_interface_address_width));
WAIT FOR main_period;
sl_avs_read <= '0';
slv_avs_address <= (OTHERS =>'0');
WAIT FOR 1000*main_period;
ASSERT false REPORT "End of simulation" SEVERITY FAILURE;
END PROCESS tb_main_proc;
enc_sim : PROCESS
BEGIN
WHILE TRUE LOOP
IF direction >= 0 THEN
slv_enc_A <= (OTHERS => '1');
WAIT FOR wait_time;
slv_enc_B <= (OTHERS => '1');
WAIT FOR wait_time;
slv_enc_A <= (OTHERS => '0');
WAIT FOR wait_time;
slv_enc_B <= (OTHERS => '0');
WAIT FOR wait_time;
ELSE
slv_enc_B <= (OTHERS => '1');
WAIT FOR wait_time;
slv_enc_A <= (OTHERS => '1');
WAIT FOR wait_time;
slv_enc_B <= (OTHERS => '0');
WAIT FOR wait_time;
slv_enc_A <= (OTHERS => '0');
WAIT FOR wait_time;
END IF;
END LOOP;
END PROCESS enc_sim;
END ARCHITECTURE sim;
|
apache-2.0
|
flink-project/flinkvhdl
|
axiComponents/subDevices/gpioDevice/hdl/gpioDevice.vhd
|
1
|
6070
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity gpioDevice_v1_0 is
generic (
-- Users to add parameters here
number_of_gpios: INTEGER RANGE 1 TO 128 := 1;
unique_id: STD_LOGIC_VECTOR (31 DOWNTO 0) := (OTHERS => '0');
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Parameters of Axi Slave Bus Interface S00_AXI
C_S00_AXI_ID_WIDTH : integer := 1;
C_S00_AXI_DATA_WIDTH : integer := 32;
C_S00_AXI_ADDR_WIDTH : integer := 12
);
port (
-- Users to add ports here
slv_gpios_io_i : IN STD_LOGIC_VECTOR(number_of_gpios-1 DOWNTO 0);
slv_gpios_io_o : OUT STD_LOGIC_VECTOR(number_of_gpios-1 DOWNTO 0);
slv_gpios_io_t : OUT STD_LOGIC_VECTOR(number_of_gpios-1 DOWNTO 0);
-- User ports ends
-- Do not modify the ports beyond this line
-- Ports of Axi Slave Bus Interface S00_AXI
s00_axi_aclk : in std_logic;
s00_axi_aresetn : in std_logic;
s00_axi_awid : in std_logic_vector(C_S00_AXI_ID_WIDTH-1 downto 0);
s00_axi_awaddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
s00_axi_awlen : in std_logic_vector(7 downto 0);
s00_axi_awsize : in std_logic_vector(2 downto 0);
s00_axi_awburst : in std_logic_vector(1 downto 0);
s00_axi_awvalid : in std_logic;
s00_axi_awready : out std_logic;
s00_axi_wdata : in std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
s00_axi_wstrb : in std_logic_vector((C_S00_AXI_DATA_WIDTH/8)-1 downto 0);
s00_axi_wlast : in std_logic;
s00_axi_wvalid : in std_logic;
s00_axi_wready : out std_logic;
s00_axi_bid : out std_logic_vector(C_S00_AXI_ID_WIDTH-1 downto 0);
s00_axi_bresp : out std_logic_vector(1 downto 0);
s00_axi_bvalid : out std_logic;
s00_axi_bready : in std_logic;
s00_axi_arid : in std_logic_vector(C_S00_AXI_ID_WIDTH-1 downto 0);
s00_axi_araddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
s00_axi_arlen : in std_logic_vector(7 downto 0);
s00_axi_arsize : in std_logic_vector(2 downto 0);
s00_axi_arburst : in std_logic_vector(1 downto 0);
s00_axi_arvalid : in std_logic;
s00_axi_arready : out std_logic;
s00_axi_rid : out std_logic_vector(C_S00_AXI_ID_WIDTH-1 downto 0);
s00_axi_rdata : out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
s00_axi_rresp : out std_logic_vector(1 downto 0);
s00_axi_rlast : out std_logic;
s00_axi_rvalid : out std_logic;
s00_axi_rready : in std_logic
);
end gpioDevice_v1_0;
architecture arch_imp of gpioDevice_v1_0 is
-- component declaration
component gpioDevice_v1_0_S00_AXI is
generic (
number_of_gpios: INTEGER RANGE 1 TO 128 := 1;
unique_id: STD_LOGIC_VECTOR (31 DOWNTO 0) := (OTHERS => '0');
C_S_AXI_ID_WIDTH : integer := 1;
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 12
);
port (
slv_gpios_io_i : IN STD_LOGIC_VECTOR(number_of_gpios-1 DOWNTO 0);
slv_gpios_io_o : OUT STD_LOGIC_VECTOR(number_of_gpios-1 DOWNTO 0);
slv_gpios_io_t : OUT STD_LOGIC_VECTOR(number_of_gpios-1 DOWNTO 0);
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWID : in std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWLEN : in std_logic_vector(7 downto 0);
S_AXI_AWSIZE : in std_logic_vector(2 downto 0);
S_AXI_AWBURST : in std_logic_vector(1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WLAST : in std_logic;
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BID : out std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARID : in std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARLEN : in std_logic_vector(7 downto 0);
S_AXI_ARSIZE : in std_logic_vector(2 downto 0);
S_AXI_ARBURST : in std_logic_vector(1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RID : out std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RLAST : out std_logic;
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic
);
end component gpioDevice_v1_0_S00_AXI;
begin
-- Instantiation of Axi Bus Interface S00_AXI
gpioDevice_v1_0_S00_AXI_inst : gpioDevice_v1_0_S00_AXI
generic map (
number_of_gpios => number_of_gpios,
unique_id => unique_id,
C_S_AXI_ID_WIDTH => C_S00_AXI_ID_WIDTH,
C_S_AXI_DATA_WIDTH => C_S00_AXI_DATA_WIDTH,
C_S_AXI_ADDR_WIDTH => C_S00_AXI_ADDR_WIDTH
)
port map (
slv_gpios_io_i => slv_gpios_io_i,
slv_gpios_io_o => slv_gpios_io_o,
slv_gpios_io_t => slv_gpios_io_t,
S_AXI_ACLK => s00_axi_aclk,
S_AXI_ARESETN => s00_axi_aresetn,
S_AXI_AWID => s00_axi_awid,
S_AXI_AWADDR => s00_axi_awaddr,
S_AXI_AWLEN => s00_axi_awlen,
S_AXI_AWSIZE => s00_axi_awsize,
S_AXI_AWBURST => s00_axi_awburst,
S_AXI_AWVALID => s00_axi_awvalid,
S_AXI_AWREADY => s00_axi_awready,
S_AXI_WDATA => s00_axi_wdata,
S_AXI_WSTRB => s00_axi_wstrb,
S_AXI_WLAST => s00_axi_wlast,
S_AXI_WVALID => s00_axi_wvalid,
S_AXI_WREADY => s00_axi_wready,
S_AXI_BID => s00_axi_bid,
S_AXI_BRESP => s00_axi_bresp,
S_AXI_BVALID => s00_axi_bvalid,
S_AXI_BREADY => s00_axi_bready,
S_AXI_ARID => s00_axi_arid,
S_AXI_ARADDR => s00_axi_araddr,
S_AXI_ARLEN => s00_axi_arlen,
S_AXI_ARSIZE => s00_axi_arsize,
S_AXI_ARBURST => s00_axi_arburst,
S_AXI_ARVALID => s00_axi_arvalid,
S_AXI_ARREADY => s00_axi_arready,
S_AXI_RID => s00_axi_rid,
S_AXI_RDATA => s00_axi_rdata,
S_AXI_RRESP => s00_axi_rresp,
S_AXI_RLAST => s00_axi_rlast,
S_AXI_RVALID => s00_axi_rvalid,
S_AXI_RREADY => s00_axi_rready
);
-- Add user logic here
-- User logic ends
end arch_imp;
|
apache-2.0
|
flink-project/flinkvhdl
|
axiComponents/subDevices/pwmDevice/hdl/pwmDevice.vhd
|
1
|
8115
|
-------------------------------------------------------------------------------
-- _________ _____ _____ ____ _____ ___ ____ --
-- |_ ___ | |_ _| |_ _| |_ \|_ _| |_ ||_ _| --
-- | |_ \_| | | | | | \ | | | |_/ / --
-- | _| | | _ | | | |\ \| | | __'. --
-- _| |_ _| |__/ | _| |_ _| |_\ |_ _| | \ \_ --
-- |_____| |________| |_____| |_____|\____| |____||____| --
-- --
-------------------------------------------------------------------------------
-- --
-- AXI interface for PWM --
-- --
-------------------------------------------------------------------------------
-- Copyright 2014 NTB University of Applied Sciences in Technology --
-- --
-- Licensed under the Apache License, Version 2.0 (the "License"); --
-- you may not use this file except in compliance with the License. --
-- You may obtain a copy of the License at --
-- --
-- http://www.apache.org/licenses/LICENSE-2.0 --
-- --
-- Unless required by applicable law or agreed to in writing, software --
-- distributed under the License is distributed on an "AS IS" BASIS, --
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. --
-- See the License for the specific language governing permissions and --
-- limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pwmDevice is
generic (
-- Users to add parameters here
unique_id : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
number_of_pwms: INTEGER RANGE 0 TO 64 := 1;--number of pwms which will be generated
base_clk: INTEGER := 100000000;--clock frequency which is used on the clock input signal of this block
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Parameters of Axi Slave Bus Interface S00_AXI
C_S00_AXI_ID_WIDTH : integer := 1;
C_S00_AXI_DATA_WIDTH : integer := 32;
C_S00_AXI_ADDR_WIDTH : integer := 12
);
port (
-- Users to add ports here
s00_oslv_pwm : OUT STD_LOGIC_VECTOR(number_of_pwms-1 DOWNTO 0);
-- User ports ends
-- Do not modify the ports beyond this line
-- Ports of Axi Slave Bus Interface S00_AXI
s00_axi_aclk : in std_logic;
s00_axi_aresetn : in std_logic;
s00_axi_awid : in std_logic_vector(C_S00_AXI_ID_WIDTH-1 downto 0);
s00_axi_awaddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
s00_axi_awlen : in std_logic_vector(7 downto 0);
s00_axi_awsize : in std_logic_vector(2 downto 0);
s00_axi_awburst : in std_logic_vector(1 downto 0);
s00_axi_awvalid : in std_logic;
s00_axi_awready : out std_logic;
s00_axi_wdata : in std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
s00_axi_wstrb : in std_logic_vector((C_S00_AXI_DATA_WIDTH/8)-1 downto 0);
s00_axi_wlast : in std_logic;
s00_axi_wvalid : in std_logic;
s00_axi_wready : out std_logic;
s00_axi_bid : out std_logic_vector(C_S00_AXI_ID_WIDTH-1 downto 0);
s00_axi_bresp : out std_logic_vector(1 downto 0);
s00_axi_bvalid : out std_logic;
s00_axi_bready : in std_logic;
s00_axi_arid : in std_logic_vector(C_S00_AXI_ID_WIDTH-1 downto 0);
s00_axi_araddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
s00_axi_arlen : in std_logic_vector(7 downto 0);
s00_axi_arsize : in std_logic_vector(2 downto 0);
s00_axi_arburst : in std_logic_vector(1 downto 0);
s00_axi_arvalid : in std_logic;
s00_axi_arready : out std_logic;
s00_axi_rid : out std_logic_vector(C_S00_AXI_ID_WIDTH-1 downto 0);
s00_axi_rdata : out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
s00_axi_rresp : out std_logic_vector(1 downto 0);
s00_axi_rlast : out std_logic;
s00_axi_rvalid : out std_logic;
s00_axi_rready : in std_logic
);
end pwmDevice;
architecture arch_imp of pwmDevice is
-- component declaration
component pwmDevice_S00_AXI is
generic (
unique_id : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
number_of_pwms: INTEGER RANGE 0 TO 64 := 1;--number of pwms which will be generated
base_clk: INTEGER := 125000000;--clock frequency which is used on the clock input signal of this block
C_S_AXI_ID_WIDTH : integer := 1;
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 12
);
port (
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWID : in std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWLEN : in std_logic_vector(7 downto 0);
S_AXI_AWSIZE : in std_logic_vector(2 downto 0);
S_AXI_AWBURST : in std_logic_vector(1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WLAST : in std_logic;
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BID : out std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARID : in std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARLEN : in std_logic_vector(7 downto 0);
S_AXI_ARSIZE : in std_logic_vector(2 downto 0);
S_AXI_ARBURST : in std_logic_vector(1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RID : out std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RLAST : out std_logic;
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
S_oslv_pwm : OUT STD_LOGIC_VECTOR(number_of_pwms-1 DOWNTO 0)
);
end component pwmDevice_S00_AXI;
begin
-- Instantiation of Axi Bus Interface S00_AXI
pwmDevice_S00_AXI_inst : pwmDevice_S00_AXI
generic map (
unique_id => unique_id,
number_of_pwms => number_of_pwms,
base_clk => base_clk,
C_S_AXI_ID_WIDTH => C_S00_AXI_ID_WIDTH,
C_S_AXI_DATA_WIDTH => C_S00_AXI_DATA_WIDTH,
C_S_AXI_ADDR_WIDTH => C_S00_AXI_ADDR_WIDTH
)
port map (
S_AXI_ACLK => s00_axi_aclk,
S_AXI_ARESETN => s00_axi_aresetn,
S_AXI_AWID => s00_axi_awid,
S_AXI_AWADDR => s00_axi_awaddr,
S_AXI_AWLEN => s00_axi_awlen,
S_AXI_AWSIZE => s00_axi_awsize,
S_AXI_AWBURST => s00_axi_awburst,
S_AXI_AWVALID => s00_axi_awvalid,
S_AXI_AWREADY => s00_axi_awready,
S_AXI_WDATA => s00_axi_wdata,
S_AXI_WSTRB => s00_axi_wstrb,
S_AXI_WLAST => s00_axi_wlast,
S_AXI_WVALID => s00_axi_wvalid,
S_AXI_WREADY => s00_axi_wready,
S_AXI_BID => s00_axi_bid,
S_AXI_BRESP => s00_axi_bresp,
S_AXI_BVALID => s00_axi_bvalid,
S_AXI_BREADY => s00_axi_bready,
S_AXI_ARID => s00_axi_arid,
S_AXI_ARADDR => s00_axi_araddr,
S_AXI_ARLEN => s00_axi_arlen,
S_AXI_ARSIZE => s00_axi_arsize,
S_AXI_ARBURST => s00_axi_arburst,
S_AXI_ARVALID => s00_axi_arvalid,
S_AXI_ARREADY => s00_axi_arready,
S_AXI_RID => s00_axi_rid,
S_AXI_RDATA => s00_axi_rdata,
S_AXI_RRESP => s00_axi_rresp,
S_AXI_RLAST => s00_axi_rlast,
S_AXI_RVALID => s00_axi_rvalid,
S_AXI_RREADY => s00_axi_rready,
S_oslv_pwm => s00_oslv_pwm
);
-- Add user logic here
-- User logic ends
end arch_imp;
|
apache-2.0
|
flink-project/flinkvhdl
|
functionalBlocks/adc128S102/sim/adc128s102_rtl_tb.vhd
|
1
|
2766
|
-------------------------------------------------------------------------------
-- ____ _____ __ __ ________ _______
-- | | \ \ | \ | | |__ __| | __ \
-- |____| \____\ | \| | | | | |__> )
-- ____ ____ | |\ \ | | | | __ <
-- | | | | | | \ | | | | |__> )
-- |____| |____| |__| \__| |__| |_______/
--
-- NTB University of Applied Sciences in Technology
--
-- Campus Buchs - Werdenbergstrasse 4 - 9471 Buchs - Switzerland
-- Campus Waldau - Schoenauweg 4 - 9013 St. Gallen - Switzerland
--
-- Web http://www.ntb.ch Tel. +41 81 755 33 11
--
-------------------------------------------------------------------------------
-- Copyright 2013 NTB University of Applied Sciences in Technology
-------------------------------------------------------------------------------
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE work.adc128S102_pkg.ALL;
ENTITY adc128S102_rtl_tb IS
END ENTITY adc128S102_rtl_tb;
ARCHITECTURE sim OF adc128S102_rtl_tb IS
--Sumulation Parameter:
CONSTANT main_period : TIME := 8 ns; -- 125MHz
SIGNAL sl_clk : STD_LOGIC := '0';
SIGNAL sl_reset_n : STD_LOGIC := '0';
SIGNAL values : t_value_regs;
SIGNAL sl_sclk : STD_LOGIC := '0';
SIGNAL slv_Ss : STD_LOGIC := '0';
SIGNAL sl_mosi : STD_LOGIC := '0';
SIGNAL sl_miso : STD_LOGIC := '0';
BEGIN
--create component
my_unit_under_test : adc128S102
GENERIC MAP(
BASE_CLK => 33000000,
SCLK_FREQUENCY => 1000000
)
PORT MAP(
isl_clk => sl_clk,
isl_reset_n => sl_reset_n,
ot_values => values,
osl_sclk => sl_sclk,
oslv_Ss => slv_Ss,
osl_mosi => sl_mosi,
isl_miso => sl_miso
);
sl_clk <= NOT sl_clk after main_period/2;
tb_main_proc : PROCESS
BEGIN
sl_reset_n <= '0';
WAIT FOR 2*main_period;
sl_reset_n <= '1';
WAIT FOR 3000*main_period;
ASSERT false REPORT "End of simulation" SEVERITY FAILURE;
END PROCESS tb_main_proc;
END ARCHITECTURE sim;
|
apache-2.0
|
flink-project/flinkvhdl
|
axiComponents/subDevices/adc128S102Device/hdl/adc128S102Device.vhd
|
1
|
6012
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity adc128S102Device_v1_0 is
generic (
-- Users to add parameters here
base_clk : INTEGER := 33000000;
sclk_frequency : INTEGER := 8000000;
unique_id : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Parameters of Axi Slave Bus Interface S00_AXI
C_S00_AXI_ID_WIDTH : integer := 1;
C_S00_AXI_DATA_WIDTH : integer := 32;
C_S00_AXI_ADDR_WIDTH : integer := 12
);
port (
-- Users to add ports here
osl_mosi : OUT STD_LOGIC;
isl_miso : IN STD_LOGIC;
osl_sclk : OUT STD_LOGIC;
osl_ss : OUT STD_LOGIC;
-- User ports ends
-- Do not modify the ports beyond this line
-- Ports of Axi Slave Bus Interface S00_AXI
s00_axi_aclk : in std_logic;
s00_axi_aresetn : in std_logic;
s00_axi_awid : in std_logic_vector(C_S00_AXI_ID_WIDTH-1 downto 0);
s00_axi_awaddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
s00_axi_awlen : in std_logic_vector(7 downto 0);
s00_axi_awsize : in std_logic_vector(2 downto 0);
s00_axi_awburst : in std_logic_vector(1 downto 0);
s00_axi_awvalid : in std_logic;
s00_axi_awready : out std_logic;
s00_axi_wdata : in std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
s00_axi_wstrb : in std_logic_vector((C_S00_AXI_DATA_WIDTH/8)-1 downto 0);
s00_axi_wlast : in std_logic;
s00_axi_wvalid : in std_logic;
s00_axi_wready : out std_logic;
s00_axi_bid : out std_logic_vector(C_S00_AXI_ID_WIDTH-1 downto 0);
s00_axi_bresp : out std_logic_vector(1 downto 0);
s00_axi_bvalid : out std_logic;
s00_axi_bready : in std_logic;
s00_axi_arid : in std_logic_vector(C_S00_AXI_ID_WIDTH-1 downto 0);
s00_axi_araddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
s00_axi_arlen : in std_logic_vector(7 downto 0);
s00_axi_arsize : in std_logic_vector(2 downto 0);
s00_axi_arburst : in std_logic_vector(1 downto 0);
s00_axi_arvalid : in std_logic;
s00_axi_arready : out std_logic;
s00_axi_rid : out std_logic_vector(C_S00_AXI_ID_WIDTH-1 downto 0);
s00_axi_rdata : out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
s00_axi_rresp : out std_logic_vector(1 downto 0);
s00_axi_rlast : out std_logic;
s00_axi_rvalid : out std_logic;
s00_axi_rready : in std_logic
);
end adc128S102Device_v1_0;
architecture arch_imp of adc128S102Device_v1_0 is
-- component declaration
component adc128S102Device_v1_0_S00_AXI is
generic (
base_clk : INTEGER := 33000000;
sclk_frequency : INTEGER := 8000000;
unique_id : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
C_S_AXI_ID_WIDTH : integer := 1;
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 12
);
port (
osl_mosi : OUT STD_LOGIC;
isl_miso : IN STD_LOGIC;
osl_sclk : OUT STD_LOGIC;
osl_ss : OUT STD_LOGIC;
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWID : in std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWLEN : in std_logic_vector(7 downto 0);
S_AXI_AWSIZE : in std_logic_vector(2 downto 0);
S_AXI_AWBURST : in std_logic_vector(1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WLAST : in std_logic;
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BID : out std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARID : in std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARLEN : in std_logic_vector(7 downto 0);
S_AXI_ARSIZE : in std_logic_vector(2 downto 0);
S_AXI_ARBURST : in std_logic_vector(1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RID : out std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RLAST : out std_logic;
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic
);
end component adc128S102Device_v1_0_S00_AXI;
begin
-- Instantiation of Axi Bus Interface S00_AXI
adc128S102Device_v1_0_S00_AXI_inst : adc128S102Device_v1_0_S00_AXI
generic map (
base_clk => base_clk,
sclk_frequency => sclk_frequency,
unique_id => unique_id,
C_S_AXI_ID_WIDTH => C_S00_AXI_ID_WIDTH,
C_S_AXI_DATA_WIDTH => C_S00_AXI_DATA_WIDTH,
C_S_AXI_ADDR_WIDTH => C_S00_AXI_ADDR_WIDTH
)
port map (
isl_miso => isl_miso,
osl_mosi => osl_mosi,
osl_sclk => osl_sclk,
osl_ss => osl_ss,
S_AXI_ACLK => s00_axi_aclk,
S_AXI_ARESETN => s00_axi_aresetn,
S_AXI_AWID => s00_axi_awid,
S_AXI_AWADDR => s00_axi_awaddr,
S_AXI_AWLEN => s00_axi_awlen,
S_AXI_AWSIZE => s00_axi_awsize,
S_AXI_AWBURST => s00_axi_awburst,
S_AXI_AWVALID => s00_axi_awvalid,
S_AXI_AWREADY => s00_axi_awready,
S_AXI_WDATA => s00_axi_wdata,
S_AXI_WSTRB => s00_axi_wstrb,
S_AXI_WLAST => s00_axi_wlast,
S_AXI_WVALID => s00_axi_wvalid,
S_AXI_WREADY => s00_axi_wready,
S_AXI_BID => s00_axi_bid,
S_AXI_BRESP => s00_axi_bresp,
S_AXI_BVALID => s00_axi_bvalid,
S_AXI_BREADY => s00_axi_bready,
S_AXI_ARID => s00_axi_arid,
S_AXI_ARADDR => s00_axi_araddr,
S_AXI_ARLEN => s00_axi_arlen,
S_AXI_ARSIZE => s00_axi_arsize,
S_AXI_ARBURST => s00_axi_arburst,
S_AXI_ARVALID => s00_axi_arvalid,
S_AXI_ARREADY => s00_axi_arready,
S_AXI_RID => s00_axi_rid,
S_AXI_RDATA => s00_axi_rdata,
S_AXI_RRESP => s00_axi_rresp,
S_AXI_RLAST => s00_axi_rlast,
S_AXI_RVALID => s00_axi_rvalid,
S_AXI_RREADY => s00_axi_rready
);
-- Add user logic here
-- User logic ends
end arch_imp;
|
apache-2.0
|
OgacNS94/C-3PU
|
vhdl_files/Data_memory.vhd
|
1
|
1556
|
--
-- Copyright 2016 Ognjen Glamocanin
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity data_memory is
port(
clk: in std_logic;
--A1, read chanell 1
address: in std_logic_vector(31 downto 0);
rdata: out std_logic_vector(31 downto 0);
wdata: in std_logic_vector(31 downto 0);
write1: in std_logic
);
end entity data_memory;
--RAM WITH ASYNCHRONOUS READING
architecture behavioral of data_memory is
--2^19x32 = 2^20x2x8 = 2MB RAM
type ram_type is array (0 to 524287) of std_logic_vector(31 downto 0);
signal ram_s: ram_type := (others => X"00000000");
begin
--process modelling writing:
write_ram: process (clk) is
begin
if(clk'event and clk='1') then
if(write1 = '1') then
ram_s(conv_integer(address)) <= wdata;
end if;
end if;
end process;
--asynchronous reading:
rdata <= ram_s(conv_integer(address));
end architecture behavioral;
|
apache-2.0
|
SKravitsky/ECEC412
|
MEMWBRegister.vhd
|
1
|
1108
|
library ieee;
use ieee.std_logic_1164.all;
entity MEMWBRegister is
port(
clk, MemtoRegIn, RegWriteIn: in std_logic;
WriteRegisterIn: in std_logic_vector(4 downto 0);
ReadDataIn, ALUResultIn: in std_logic_vector(31 downto 0);
MemtoRegOut, RegWriteOut: out std_logic;
WriteRegisterOut: out std_logic_vector(4 downto 0);
ReadDataOut, ALUResultOut: out std_logic_vector(31 downto 0)
);
end MEMWBRegister;
architecture Structural of MEMWBRegister is
signal MemtoReg, RegWrite: std_logic := '0';
signal WriteRegister: std_logic_vector(4 downto 0) := "00000";
signal ReadData, ALUResult: std_logic_vector(31 downto 0) := X"00000000";
begin
MemtoRegOut <= MemtoReg;
RegWriteOut <= RegWrite;
WriteRegisterOut <= WriteRegister;
ReadDataOut <= ReadData;
ALUResultOut <= ALUResult;
process(clk)
begin
if rising_edge(clk) then
MemtoReg <= MemtoRegIn;
RegWrite <= RegWriteIn;
WriteRegister <= WriteRegisterIn;
ReadData <= ReadDataIn;
ALUResult <= ALUResultIn;
end if;
end process;
end Structural;
|
apache-2.0
|
SKravitsky/ECEC412
|
Or2.vhd
|
1
|
196
|
library ieee;
use ieee.std_logic_1164.all;
entity Or2 is
port(
a, b: in std_logic;
y: out std_logic
);
end Or2;
architecture Structural of Or2 is
begin
y <= a or b;
end Structural;
|
apache-2.0
|
SKravitsky/ECEC412
|
Control.vhd
|
1
|
1748
|
library ieee;
use ieee.std_logic_1164.all;
entity Control is
port(
Opcode: in std_logic_vector(5 downto 0);
RegDst, Branch, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite, Jump: out std_logic;
ALUOp: out std_logic_vector(1 downto 0)
);
end Control;
architecture Structural of Control is
begin
process(Opcode)
begin
case Opcode is
when "000000" => --add/sub
RegDst <= '1';
Branch <= '0';
MemRead <= '0';
MemtoReg <= '0';
MemWrite <= '0';
ALUSrc <= '0';
RegWrite <= '1';
Jump <= '0';
ALUOp <= "10";
when "100011" => --lw
RegDst <= '0';
Branch <= '0';
MemRead <= '1';
MemtoReg <= '1';
MemWrite <= '0';
ALUSrc <= '1';
RegWrite <= '1';
Jump <= '0';
ALUOp <= "00";
when "000100" => --beq
RegDst <= '0';
Branch <= '1';
MemRead <= '0';
MemtoReg <= '0';
MemWrite <= '0';
ALUSrc <= '0';
RegWrite <= '0';
Jump <= '0';
ALUOp <= "01";
when "000010" => --j
RegDst <= '0';
Branch <= '0';
MemRead <= '0';
MemtoReg <= '0';
MemWrite <= '0';
ALUSrc <= '0';
RegWrite <= '0';
Jump <= '1';
ALUOp <= "00";
when "101011" => --sw
RegDst <= '0';
Branch <= '0';
MemRead <= '0';
MemtoReg <= '0';
MemWrite <= '1';
ALUSrc <= '1';
RegWrite <= '0';
Jump <= '0';
ALUOp <= "00";
when others =>
null;
end case;
end process;
end Structural;
|
apache-2.0
|
SKravitsky/ECEC412
|
Registers.vhd
|
1
|
1798
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Registers is
port(
RR1, RR2, WR : in std_logic_vector(4 downto 0);
WD : in std_logic_vector(31 downto 0);
RegWrite, Clk : in std_logic;
RD1, RD2 : out std_logic_vector(31 downto 0)
);
end Registers;
architecture Structural of Registers is
type mem_array is array(0 to 31) of std_logic_vector(31 downto 0);
signal reg_mem: mem_array :=(
X"00000000", --0 $zero (constant value 0)
X"00000000", -- $at (reserved for the assembler)
X"00000000", -- $v0 (value for results and expression)
X"00000000", -- $v1
X"00000000", -- $a0 (arguments)
X"00000000", --5 $a1
X"00000000", -- $a2
X"00000000", -- $a3
X"00000004", -- $t0 (temporaries)
X"00000000", -- $t1
X"00000000", --10 $t2
X"00000000", -- $t3
X"00000000", -- $t4
X"00000000", -- $t5
X"00000000", -- $t6
X"00000000", --15 $t7
X"00000000", -- $s0 (saved)
X"00000000", -- $s1
X"0000000D", -- $s2
X"00000004", -- $s3
X"00000000", --20 $s4
X"00000000", -- $s5
X"00000000", -- $s6
X"00000000", -- $s7
X"00000000", -- $t8 (more temporaries)
X"00000000", --25 $t9
X"00000000", -- $k0 (reserved for the operating system)
X"00000000", -- $k1
X"00000000", -- $gp (global pointer)
X"00000000", -- $sp (stack pointer)
X"00000000", --30 $fp (frame pointer)
X"00000000" -- $ra (return address)
);
begin
RD1 <= reg_mem(to_integer(unsigned(RR1)));
RD2 <= reg_mem(to_integer(unsigned(RR2)));
process(Clk)
begin
if rising_edge(Clk) then
if RegWrite = '1' then
reg_mem(to_integer(unsigned(WR))) <= WD;
end if;
end if;
end process;
end Structural;
|
apache-2.0
|
mkotormus/G3_OrchestraConductorDemo
|
src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/axi_master_burst_v2_0/1af76933/hdl/src/vhdl/axi_master_burst_stbs_set.vhd
|
1
|
17012
|
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- Filename: axi_master_burst_stbs_set.vhd
--
-- Description:
-- This file implements a module to count the number of strobe bits that
-- are asserted active high on the input strobe bus. This module does not
-- support sparse strobe assertions (asserted strobes must be contiguous
-- with each other).
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_master_burst_stbs_set.vhd
--
-------------------------------------------------------------------------------
-- Revision History:
--
--
-- Author: DET
-- Revision: $Revision: 1.0 $
-- Date: $1/19/2011$
--
-- History:
-- DET 1/19/2011 Initial
-- ~~~~~~
-- - Adapted from AXI DataMover v2_00_a axi_datamvore_stbs_set.vhd
-- ^^^^^^
-- ~~~~~~
-- SK 12/16/12 -- v2.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI MASTER BURST to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_v4_0
-- 4. No Logic Updates
-- ^^^^^^
--
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_master_burst_stbs_set is
generic (
C_STROBE_WIDTH : Integer range 1 to 32 := 8
-- Specifies the width (in bits) ob the input strobe bus.
);
port (
tstrb_in : in std_logic_vector(C_STROBE_WIDTH-1 downto 0);
-- Input Strobe bus
num_stbs_asserted : Out std_logic_vector(7 downto 0)
-- Indicates the number of asserted tstrb_in bits
);
end entity axi_master_burst_stbs_set;
architecture implementation of axi_master_burst_stbs_set is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_8bit_stbs_set
--
-- Function Description:
-- Implements an 8-bit lookup table for calculating the number
-- of asserted bits within an 8-bit strobe vector.
--
-- Note that this function assumes that asserted strobes are
-- contiguous with each other (no sparse strobe assertions).
--
-------------------------------------------------------------------
function funct_8bit_stbs_set (strb_8 : std_logic_vector(7 downto 0)) return unsigned is
Constant ASSERTED_VALUE_WIDTH : integer := 4;-- 4 bits needed
Variable lvar_num_set : Integer range 0 to 8 := 0;
begin
case strb_8 is
------- 1 bit --------------------------
when "00000001" | "00000010" | "00000100" | "00001000" |
"00010000" | "00100000" | "01000000" | "10000000" =>
lvar_num_set := 1;
------- 2 bit --------------------------
when "00000011" | "00000110" | "00001100" | "00011000" |
"00110000" | "01100000" | "11000000" =>
lvar_num_set := 2;
------- 3 bit --------------------------
when "00000111" | "00001110" | "00011100" | "00111000" |
"01110000" | "11100000" =>
lvar_num_set := 3;
------- 4 bit --------------------------
when "00001111" | "00011110" | "00111100" | "01111000" |
"11110000" =>
lvar_num_set := 4;
------- 5 bit --------------------------
when "00011111" | "00111110" | "01111100" | "11111000" =>
lvar_num_set := 5;
------- 6 bit --------------------------
when "00111111" | "01111110" | "11111100" =>
lvar_num_set := 6;
------- 7 bit --------------------------
when "01111111" | "11111110" =>
lvar_num_set := 7;
------- 8 bit --------------------------
when "11111111" =>
lvar_num_set := 8;
------- all zeros or sparse strobes ------
When others =>
lvar_num_set := 0;
end case;
Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
end function funct_8bit_stbs_set;
-- Constants
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant BITS_FOR_STBS_ASSERTED : integer := 8; -- increments of 8 bits
Constant NUM_ZEROS_WIDTH : integer := BITS_FOR_STBS_ASSERTED;
-- Signals
signal sig_strb_input : std_logic_vector(C_STROBE_WIDTH-1 downto 0) := (others => '0');
signal sig_stbs_asserted : std_logic_vector(BITS_FOR_STBS_ASSERTED-1 downto 0) := (others => '0');
begin --(architecture implementation)
num_stbs_asserted <= sig_stbs_asserted;
sig_strb_input <= tstrb_in ;
-------------------------------------------------------------------------
---------------- Asserted TSTRB calculation logic ---------------------
-------------------------------------------------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_1_STRB
--
-- If Generate Description:
-- 1-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_1_STRB : if (C_STROBE_WIDTH = 1) generate
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_1BIT_STRB
--
-- Process Description:
--
--
-------------------------------------------------------------
IMP_1BIT_STRB : process (sig_strb_input)
begin
-- Concatonate the strobe to the ls bit of
-- the asserted value
sig_stbs_asserted <= "0000000" &
sig_strb_input(0);
end process IMP_1BIT_STRB;
end generate GEN_1_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_2_STRB
--
-- If Generate Description:
-- 2-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_2_STRB : if (C_STROBE_WIDTH = 2) generate
signal lsig_num_set : integer range 0 to 2 := 0;
signal lsig_strb_vect : std_logic_vector(1 downto 0) := (others => '0');
begin
lsig_strb_vect <= sig_strb_input;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_2BIT_STRB
--
-- Process Description:
-- Calculates the number of strobes set fo the 2-bit
-- strobe case
--
-------------------------------------------------------------
IMP_2BIT_STRB : process (lsig_strb_vect)
begin
case lsig_strb_vect is
when "01" | "10" =>
lsig_num_set <= 1;
when "11" =>
lsig_num_set <= 2;
when others =>
lsig_num_set <= 0;
end case;
end process IMP_2BIT_STRB;
sig_stbs_asserted <= STD_LOGIC_VECTOR(TO_UNSIGNED(lsig_num_set,
BITS_FOR_STBS_ASSERTED));
end generate GEN_2_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_4_STRB
--
-- If Generate Description:
-- 4-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_4_STRB : if (C_STROBE_WIDTH = 4) generate
signal lsig_strb_vect : std_logic_vector(7 downto 0) := (others => '0');
begin
lsig_strb_vect <= "0000" & sig_strb_input; -- make and 8-bit vector
-- for the function call
sig_stbs_asserted <= STD_LOGIC_VECTOR(RESIZE(funct_8bit_stbs_set(lsig_strb_vect),
BITS_FOR_STBS_ASSERTED));
end generate GEN_4_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_8_STRB
--
-- If Generate Description:
-- 8-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_8_STRB : if (C_STROBE_WIDTH = 8) generate
signal lsig_strb_vect : std_logic_vector(7 downto 0) := (others => '0');
begin
lsig_strb_vect <= sig_strb_input; -- make and 8-bit vector
-- for the function call
sig_stbs_asserted <= STD_LOGIC_VECTOR(RESIZE(funct_8bit_stbs_set(lsig_strb_vect),
BITS_FOR_STBS_ASSERTED));
end generate GEN_8_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_16_STRB
--
-- If Generate Description:
-- 16-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_16_STRB : if (C_STROBE_WIDTH = 16) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
end generate GEN_16_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_32_STRB
--
-- If Generate Description:
-- 32-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_32_STRB : if (C_STROBE_WIDTH = 32) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect3 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect4 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs3 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs4 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_strb_vect3 <= sig_strb_input(23 downto 16); -- make and 8-bit vector
-- for the function call
lsig_strb_vect4 <= sig_strb_input(31 downto 24); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_in_stbs3 <= funct_8bit_stbs_set(lsig_strb_vect3) ;
lsig_num_in_stbs4 <= funct_8bit_stbs_set(lsig_strb_vect4) ;
lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs3 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs4 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
end generate GEN_32_STRB;
end implementation;
|
apache-2.0
|
mkotormus/G3_OrchestraConductorDemo
|
src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/microblaze_v9_3/7b6e2d75/hdl/vhdl/fpu_addsub.vhd
|
1
|
44605
|
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`protect end_protected
|
apache-2.0
|
mkotormus/G3_OrchestraConductorDemo
|
src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/axi_uartlite_v2_0/6e58ba99/hdl/src/vhdl/baudrate.vhd
|
1
|
8909
|
-------------------------------------------------------------------------------
-- baudrate - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- -- ** (c) Copyright [2007] - [2011] Xilinx, Inc. All rights reserved.*
-- -- ** *
-- -- ** This file contains confidential and proprietary information *
-- -- ** of Xilinx, Inc. and is protected under U.S. and *
-- -- ** international copyright and other intellectual property *
-- -- ** laws. *
-- -- ** *
-- -- ** DISCLAIMER *
-- -- ** This disclaimer is not a license and does not grant any *
-- -- ** rights to the materials distributed herewith. Except as *
-- -- ** otherwise provided in a valid license issued to you by *
-- -- ** Xilinx, and to the maximum extent permitted by applicable *
-- -- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- -- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- -- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- -- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- -- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- -- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- -- ** including negligence, or under any other theory of *
-- -- ** liability) for any loss or damage of any kind or nature *
-- -- ** related to, arising under or in connection with these *
-- -- ** materials, including for any direct, or any indirect, *
-- -- ** special, incidental, or consequential loss or damage *
-- -- ** (including loss of data, profits, goodwill, or any type of *
-- -- ** loss or damage suffered as a result of any action brought *
-- -- ** by a third party) even if such damage or loss was *
-- -- ** reasonably foreseeable or Xilinx had been advised of the *
-- -- ** possibility of the same. *
-- -- ** *
-- -- ** CRITICAL APPLICATIONS *
-- -- ** Xilinx products are not designed or intended to be fail- *
-- -- ** safe, or for use in any application requiring fail-safe *
-- -- ** performance, such as life-support or safety devices or *
-- -- ** systems, Class III medical devices, nuclear facilities, *
-- -- ** applications related to the deployment of airbags, or any *
-- -- ** other applications that could lead to death, personal *
-- -- ** injury, or severe property or environmental damage *
-- -- ** (individually and collectively, "Critical *
-- -- ** Applications"). Customer assumes the sole risk and *
-- -- ** liability of any use of Xilinx products in Critical *
-- -- ** Applications, subject only to applicable laws and *
-- -- ** regulations governing limitations on product liability. *
-- -- ** *
-- -- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- -- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename: baudrate.vhd
-- Version: v2.0
-- Description: Baud rate enable logic
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of axi_uartlite.
--
-- axi_uartlite.vhd
-- --axi_lite_ipif.vhd
-- --uartlite_core.vhd
-- --uartlite_tx.vhd
-- --uartlite_rx.vhd
-- --baudrate.vhd
-------------------------------------------------------------------------------
-- Author: USM
--
-- USM 07/22/09
-- ^^^^^^
-- - Initial release of v1.00.a
-- ~~~~~~
-- ~~~~~~
-- 20/09/20 SK
-- - Updated the version as AXI Lite IPIF version is updated.
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics :
-------------------------------------------------------------------------------
-- UART Lite generics
-- C_RATIO -- The ratio between clk and the asked baudrate
-- multiplied with 16
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Ports :
-------------------------------------------------------------------------------
-- System Signals
-- Clk -- Clock signal
-- Reset -- Reset signal
-- Internal UART interface signals
-- EN_16x_Baud -- Enable signal which is 16x times baud rate
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity Section
-------------------------------------------------------------------------------
entity baudrate is
generic
(
C_RATIO : integer := 48 -- The ratio between clk and the asked
-- baudrate multiplied with 16
);
port
(
Clk : in std_logic;
Reset : in std_logic;
EN_16x_Baud : out std_logic
);
end entity baudrate;
-------------------------------------------------------------------------------
-- Architecture Section
-------------------------------------------------------------------------------
architecture RTL of baudrate is
-- Pragma Added to supress synth warnings
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
---------------------------------------------------------------------------
-- Signal Declarations
---------------------------------------------------------------------------
signal count : natural range 0 to C_RATIO-1;
begin -- architecture VHDL_RTL
---------------------------------------------------------------------------
-- COUNTER_PROCESS : Down counter for generating EN_16x_Baud signal
---------------------------------------------------------------------------
COUNTER_PROCESS : process (Clk) is
begin
if Clk'event and Clk = '1' then -- rising clock edge
if (Reset = '1') then
count <= 0;
EN_16x_Baud <= '0';
else
if (count = 0) then
count <= C_RATIO-1;
EN_16x_Baud <= '1';
else
count <= count - 1;
EN_16x_Baud <= '0';
end if;
end if;
end if;
end process COUNTER_PROCESS;
end architecture RTL;
|
apache-2.0
|
mkotormus/G3_OrchestraConductorDemo
|
src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/proc_common_v4_0/bb615326/hdl/src/vhdl/conv_funs_pkg.vhd
|
15
|
15316
|
-------------------------------------------------------------------------------
-- $Id: conv_funs_pkg.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
----------------------------------------------------------------------------
-- conv_funs_pkg.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2002-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
----------------------------------------------------------------------------
-- Filename: conv_funs_pkg.vhd
--
-- Description:
-- Various string conversion functions.
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- conv_funs_pkg.vhd
--
-------------------------------------------------------------------------------
-- Revision History:
--
--
-- Author: unknown
-- Revision: $Revision: 1.1.4.1 $
-- Date: $1/1/2002$
--
-- History:
-- XXX 1/1/2002 Initial Version
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
package conv_funs_pkg is
-- hex string to std_logic_vector
function hex_string_to_slv (instring : STRING;
return_length : POSITIVE range 1 to 64 := 32)
return STD_LOGIC_VECTOR;
-- octal string to std_logic_vector
function oct_string_to_slv (instring : STRING;
return_length : POSITIVE range 1 to 64 := 32)
return STD_LOGIC_VECTOR;
-- binary string to std_logic_vector
function bin_string_to_slv (instring : STRING;
return_length : POSITIVE range 1 to 64 := 32)
return STD_LOGIC_VECTOR;
-- string to std_logic_vector
function string_to_std_logic_vector (instring : STRING;
return_length : POSITIVE range 1 to 64 := 32)
return STD_LOGIC_VECTOR;
end conv_funs_pkg;
--
--------------------------------------------------------------------------------
--
package body conv_funs_pkg is
type basetype is (binary, octal, decimal, hex);
function max(x, y : INTEGER) return INTEGER is
begin
if x > y then return x; else return y; end if;
end max;
function MIN(x, y : INTEGER) return INTEGER is
begin
if x < y then return x; else return y; end if;
end MIN;
function hex_string_to_slv (instring : STRING;
return_length : POSITIVE range 1 to 64 := 32)
return STD_LOGIC_VECTOR is
-- if return_length is < than instring'length*4, result will be truncated on the left
-- if instring is other than characters 0 to 9 or a,A to f,F or
-- x,X,z,Z,u,U,-,w,W,
-- those result bits will be set to 0
variable temp_string : STRING(1 to instring'LENGTH) := instring;
variable vector_size : POSITIVE := max(instring'LENGTH*4, return_length);
variable char_ptr : INTEGER range -3 to max(instring'LENGTH*4, return_length) := max(instring'LENGTH*4, return_length);
variable return_vector : STD_LOGIC_VECTOR(1 to max(instring'LENGTH*4, return_length)) := (others => '0');
begin
for i in temp_string'REVERSE_RANGE loop
case temp_string(i) is
when '0' => return_vector(char_ptr-3 to char_ptr) := "0000";
when '1' => return_vector(char_ptr-3 to char_ptr) := "0001";
when '2' => return_vector(char_ptr-3 to char_ptr) := "0010";
when '3' => return_vector(char_ptr-3 to char_ptr) := "0011";
when '4' => return_vector(char_ptr-3 to char_ptr) := "0100";
when '5' => return_vector(char_ptr-3 to char_ptr) := "0101";
when '6' => return_vector(char_ptr-3 to char_ptr) := "0110";
when '7' => return_vector(char_ptr-3 to char_ptr) := "0111";
when '8' => return_vector(char_ptr-3 to char_ptr) := "1000";
when '9' => return_vector(char_ptr-3 to char_ptr) := "1001";
when 'a'|'A' => return_vector(char_ptr-3 to char_ptr) := "1010";
when 'b'|'B' => return_vector(char_ptr-3 to char_ptr) := "1011";
when 'c'|'C' => return_vector(char_ptr-3 to char_ptr) := "1100";
when 'd'|'D' => return_vector(char_ptr-3 to char_ptr) := "1101";
when 'e'|'E' => return_vector(char_ptr-3 to char_ptr) := "1110";
when 'f'|'F' => return_vector(char_ptr-3 to char_ptr) := "1111";
-- xst doesn't handle these
-- when 'U' => return_vector(char_ptr-3 to char_ptr) := "UUUU";
-- when 'X' => return_vector(char_ptr-3 to char_ptr) := "XXXX";
-- when 'Z' => return_vector(char_ptr-3 to char_ptr) := "ZZZZ";
-- when 'W' => return_vector(char_ptr-3 to char_ptr) := "WWWW";
-- when 'H' => return_vector(char_ptr-3 to char_ptr) := "HHHH";
-- when 'L' => return_vector(char_ptr-3 to char_ptr) := "LLLL";
-- when '-' => return_vector(char_ptr-3 to char_ptr) := "----";
-- but synplicity does
when '_' => char_ptr := char_ptr + 4;
when others =>
assert FALSE
report lf &
"hex_string_to_slv conversion found illegal input character: " &
temp_string(i) & lf & "converting character to '----'"
severity WARNING;
return_vector(char_ptr-3 to char_ptr) := "----";
end case;
char_ptr := char_ptr - 4;
end loop;
return return_vector(vector_size-return_length+1 to vector_size);
end hex_string_to_slv;
function oct_string_to_slv (instring : STRING;
return_length : POSITIVE range 1 to 64 := 32)
return STD_LOGIC_VECTOR is
-- if return_length is < than instring'length*3, result will be truncated on the left
-- if instring is other than characters 0 to 7 or or x,X,z,Z,u,U,-,w,W,
-- those result bits will be set to 0
variable temp_string : STRING(1 to instring'LENGTH) := instring;
variable vector_size : POSITIVE := max(instring'LENGTH*3, return_length);
variable char_ptr : INTEGER range -2 to max(instring'LENGTH*3, return_length) := max(instring'LENGTH*3, return_length);
variable return_vector : STD_LOGIC_VECTOR(1 to max(instring'LENGTH*3, return_length)) := (others => '0');
begin
for i in temp_string'REVERSE_RANGE loop
case temp_string(i) is
when '0' => return_vector(char_ptr-2 to char_ptr) := "000";
when '1' => return_vector(char_ptr-2 to char_ptr) := "001";
when '2' => return_vector(char_ptr-2 to char_ptr) := "010";
when '3' => return_vector(char_ptr-2 to char_ptr) := "011";
when '4' => return_vector(char_ptr-2 to char_ptr) := "100";
when '5' => return_vector(char_ptr-2 to char_ptr) := "101";
when '6' => return_vector(char_ptr-2 to char_ptr) := "110";
when '7' => return_vector(char_ptr-2 to char_ptr) := "111";
-- xst doesn't handle these
-- when 'U' => return_vector(char_ptr-2 to char_ptr) := "UUU";
-- when 'X' => return_vector(char_ptr-2 to char_ptr) := "XXX";
-- when 'Z' => return_vector(char_ptr-2 to char_ptr) := "ZZZ";
-- when 'W' => return_vector(char_ptr-2 to char_ptr) := "WWW";
-- when 'H' => return_vector(char_ptr-2 to char_ptr) := "HHH";
-- when 'L' => return_vector(char_ptr-2 to char_ptr) := "LLL";
-- when '-' => return_vector(char_ptr-2 to char_ptr) := "---";
-- but synplicity does
when '_' => char_ptr := char_ptr + 3;
when others =>
assert FALSE
report lf &
"oct_string_to_slv conversion found illegal input character: " &
temp_string(i) & lf & "converting character to '---'"
severity WARNING;
return_vector(char_ptr-2 to char_ptr) := "---";
end case;
char_ptr := char_ptr - 3;
end loop;
return return_vector(vector_size-return_length+1 to vector_size);
end oct_string_to_slv;
function bin_string_to_slv (instring : STRING;
return_length : POSITIVE range 1 to 64 := 32)
return STD_LOGIC_VECTOR is
-- if return_length is < than instring'length, result will be truncated on the left
-- if instring is other than characters 0 to 1 or x,X,z,Z,u,U,-,w,W,
-- those result bits will be set to 0
variable temp_string : STRING(1 to instring'LENGTH) := instring;
variable vector_size : POSITIVE := max(instring'LENGTH, return_length);
variable char_ptr : INTEGER range 0 to max(instring'LENGTH, return_length)+1 := max(instring'LENGTH, return_length);
variable return_vector : STD_LOGIC_VECTOR(1 to max(instring'LENGTH, return_length)) := (others => '0');
begin
for i in temp_string'REVERSE_RANGE loop
case temp_string(i) is
when '0' => return_vector(char_ptr) := '0';
when '1' => return_vector(char_ptr) := '1';
-- xst doesn't handle these
-- when 'U' => return_vector(char_ptr) := 'U';
-- when 'X' => return_vector(char_ptr) := 'X';
-- when 'Z' => return_vector(char_ptr) := 'Z';
-- when 'W' => return_vector(char_ptr) := 'W';
-- when 'H' => return_vector(char_ptr) := 'H';
-- when 'L' => return_vector(char_ptr) := 'L';
-- when '-' => return_vector(char_ptr) := '-';
-- but synplicity does
when '_' => char_ptr := char_ptr + 1;
when others =>
assert FALSE
report lf &
"bin_string_to_slv conversion found illegal input character: " &
temp_string(i) & lf & "converting character to '-'"
severity WARNING;
return_vector(char_ptr) := '-';
end case;
char_ptr := char_ptr - 1;
end loop;
return return_vector(vector_size-return_length+1 to vector_size);
end bin_string_to_slv;
function string_to_std_logic_vector (instring : STRING;
return_length : POSITIVE range 1 to 64 := 32)
return STD_LOGIC_VECTOR is
variable instring_length : POSITIVE := instring'LENGTH;
variable temp_string : STRING(1 to instring'LENGTH-2);
begin -- function string_to_std_logic_vector
if instring(1) = '0' and (instring(2) = 'x' or instring(2) = 'X') then
temp_string := instring(3 to instring_length);
return hex_string_to_slv(temp_string, return_length);
elsif instring(1) = '0' and (instring(2) = 'o' or instring(2) = 'O') then
temp_string := instring(3 to instring_length);
return oct_string_to_slv(temp_string, return_length);
elsif instring(1) = '0' and (instring(2) = 'b' or instring(2) = 'B') then
temp_string := instring(3 to instring_length);
return bin_string_to_slv(temp_string, return_length);
else
return bin_string_to_slv(instring, return_length);
end if;
end function string_to_std_logic_vector;
end conv_funs_pkg;
|
apache-2.0
|
mkotormus/G3_OrchestraConductorDemo
|
src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/microblaze_v9_3/7b6e2d75/hdl/vhdl/microblaze_types_pkg.vhd
|
1
|
13071
|
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`protect end_protected
|
apache-2.0
|
mkotormus/G3_OrchestraConductorDemo
|
src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/microblaze_v9_3/7b6e2d75/hdl/vhdl/microblaze_core.vhd
|
1
|
619735
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 457024)
`protect data_block
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`protect end_protected
|
apache-2.0
|
mkotormus/G3_OrchestraConductorDemo
|
src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/microblaze_v9_3/7b6e2d75/hdl/vhdl/msr_reg_bit.vhd
|
1
|
9914
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5600)
`protect data_block
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`protect end_protected
|
apache-2.0
|
mkotormus/G3_OrchestraConductorDemo
|
src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/microblaze_v9_3/7b6e2d75/hdl/vhdl/shift_logic_gti.vhd
|
1
|
49902
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 35200)
`protect data_block
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`protect end_protected
|
apache-2.0
|
mkotormus/G3_OrchestraConductorDemo
|
src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/proc_common_v4_0/bb615326/hdl/src/vhdl/srl_fifo_rbu.vhd
|
15
|
18227
|
-------------------------------------------------------------------------------
-- $Id: srl_fifo_rbu.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- srl_fifo_rbu - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2005-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: srl_fifo_rbu.vhd
--
-- Description: A small-depth FIFO with capability to back up and reread data.
-- SRL16 primitives are used for the FIFO storage.
--
-- Features:
-- - Width (arbitrary) and depth (1..16) are
-- instance selectable.
-- - Commands: read, write, and reread n.
-- - Flags: empty and full.
-- - The reread n command (executed by applying
-- a non-zero value, n, to signal Num_To_Reread
-- for one clock period) allows n
-- previously read elements to be restored to the FIFO,
-- limited, however, to the number of elements that have
-- not been overwritten. (User's responsibility to
-- assure that the elements being restored
-- are actually in the FIFO storage.)
-- - Commands may be asserted simultaneously.
-- However, if read and reread n are asserted
-- simultaneously, only the read is carried out.
-- - Overflow and underflow are detected and latched until
-- Reset. The state of the FIFO is undefined during
--------------------------------------------------------------------------------
-- status of underflow and overflow. If neither overflow
-- nor underflow needs to be detected, the
-- Overflow and Underflow output ports may be left open
-- to allow the tools to optimize away the associated
-- logic.
-- - The resources needed to address the storage scale with
-- selected depth. (e.g. a 7-deep FIFO gets by with
-- one fewer address bits than an 8-deep, etc.)
-- - The Addr output is always one less than the current
-- occupancy when the FIFO is non-empty, and is all ones
-- otherwise.
--
-- Srl_fifo_rbu is a descendent of srl_fifo and srl_fifo2,
-- but the internals are somewhat reworked. The essential
-- new feature is the read-backup capability. Other
-- differences are:
-- -The Data_Exists signal of those FIFOs--which
-- had meaning "fifo not empty"--is eliminated and
-- signal FIFO_Empty is available to determine the
-- empty/non-empty condition.
-- -The Addr output has a different definition than the
-- two ancestor FIFOs. (Srl_fifo and srl_fifo2 have
-- addr=0 when the FIFO contains one element and when
-- the FIFO is empty.)
-- -The ancestor FIFOs inhibited FIFO operations that
-- would have caused an overflow or underflow but
-- did not report the error. This FIFO allows the
-- operation (which puts the FIFO in an undefined state)
-- but reports the error.
-- -If the overflow and underflow flags are not used,
-- srl_fifo_rbu has no size disadvantage compared to
-- srl_fifo and srl_fifo2, despite the added capability
-- of reread n.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl_fifo_rbu.vhd
-- proc_common_pkg.vhd
--
-------------------------------------------------------------------------------
-- Author: Farrell Ostler for the enhancements relative to earlier
-- srl_fifos. Original srl_fifo by Goran Bilski.
--
-- History:
-- FLO 05/01/02 First Version
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- predecessor value by # clks: "*_p#"
library ieee;
library unisim;
library proc_common_v4_0;
use ieee.std_logic_1164.all;
use ieee.numeric_std.UNSIGNED;
use ieee.numeric_std.">=";
use ieee.numeric_std.TO_UNSIGNED;
use unisim.all;
use proc_common_v4_0.proc_common_pkg.log2;
entity srl_fifo_rbu is
generic (
C_DWIDTH : positive := 8;
C_DEPTH : positive := 16;
C_XON : boolean := false -- for mixed mode sims
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DWIDTH-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
FIFO_Full : out std_logic;
FIFO_Empty : out std_logic;
Addr : out std_logic_vector(0 to log2(C_DEPTH)-1);
Num_To_Reread : in std_logic_vector(0 to log2(C_DEPTH)-1);
Underflow : out std_logic;
Overflow : out std_logic
);
--Note:
--ToDo, Num_To_Reread is a good candidate testcase for unconstrained ports.
-- The user would specify--by the width of the signal that is hooked up to
-- Num_To_Reread-- how many bits are needed for the reread count.
-- If Num_To_Reread were hooked up to the null array, then the
-- reread capability would be disabled.
end entity srl_fifo_rbu;
architecture imp of srl_fifo_rbu is
component SRL16E is
-- pragma translate_off
generic (
INIT : bit_vector := X"0000"
);
-- pragma translate_on
port (
CE : in std_logic;
D : in std_logic;
Clk : in std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
Q : out std_logic);
end component SRL16E;
component MULT_AND
port (
I0 : in std_logic;
I1 : in std_logic;
LO : out std_logic);
end component;
component MUXCY_L
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
LO : out std_logic);
end component;
component XORCY
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component;
component FDS is
port (
Q : out std_logic;
C : in std_logic;
D : in std_logic;
S : in std_logic);
end component FDS;
--function log2(n: natural) return natural is
-- variable i: integer := 1;
-- variable r: integer := 0;
--begin
-- while i < n loop
-- i := 2*i; r := r+1;
-- end loop;
-- return r;
--end log2;
function bitwise_or(s: std_logic_vector) return std_logic is
variable v: std_logic := '0';
begin
for i in s'range loop
v := v or s(i);
end loop;
return v;
end bitwise_or;
constant ADDR_BITS : integer := log2(C_DEPTH);
-- An extra bit will be carried as the empty flag.
signal addr_i : std_logic_vector(ADDR_BITS downto 0);
signal hsum_A : std_logic_vector(ADDR_BITS downto 0);
signal addr_i_p1 : std_logic_vector(ADDR_BITS downto 0);
signal num_to_reread_zeroext : std_logic_vector(ADDR_BITS downto 0);
signal addr_cy : std_logic_vector(ADDR_BITS+1 downto 0);
signal fifo_empty_i : std_logic;
signal overflow_i : std_logic;
signal underflow_i : std_logic;
signal srl16_addr : std_logic_vector(3 downto 0);
-- Used to zero high-order bits if C_DEPTH is 7 or less.
begin -- architecture IMP
-----------------------------------------------------------------------------
-- C_DEPTH is positive, which ensures the fifo is at least 1 element deep.
-- Make sure it is not greater than 16 locations deep.
-----------------------------------------------------------------------------
-- pragma translate_off
assert C_DEPTH <= 16
report "SRL Fifo's must be 16 or less elements deep"
severity FAILURE;
-- pragma translate_on
FULL_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset='1' then
FIFO_Full <= '0';
else
if addr_i_p1 = std_logic_vector(
TO_UNSIGNED(
C_DEPTH-1,ADDR_BITS+1
)
) then
FIFO_Full <= '1';
else
FIFO_Full <= '0';
end if;
end if;
end if;
end process;
fifo_empty_i <= addr_i(ADDR_BITS);
FIFO_Empty <= fifo_empty_i;
process (Num_To_Reread)
begin
num_to_reread_zeroext <= (others => '0');
num_to_reread_zeroext(Num_To_Reread'length-1 downto 0) <= Num_To_Reread;
end process;
addr_cy(0) <= FIFO_Write;
Addr_Counters : for I in 0 to ADDR_BITS generate
hsum_A(I) <= ((FIFO_Read or num_to_reread_zeroext(i)) xor addr_i(I));
MUXCY_L_I : MUXCY_L
port map (
DI => addr_i(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
S => hsum_A(I), -- [in std_logic]
LO => addr_cy(I+1)); -- [out std_logic]
XORCY_I : XORCY
port map (
LI => hsum_A(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
O => addr_i_p1(I)); -- [out std_logic]
FDS_I : FDS
port map (
Q => addr_i(I), -- [out std_logic]
C => Clk, -- [in std_logic]
D => addr_i_p1(I), -- [in std_logic]
S => Reset); -- [in std_logic]
end generate Addr_Counters;
process (addr_i)
begin
srl16_addr <= (others => '0');
srl16_addr(ADDR_BITS-1 downto 0) <= addr_i(ADDR_BITS-1 downto 0);
end process;
FIFO_RAM : for I in 0 to C_DWIDTH-1 generate
SRL16E_I : SRL16E
-- pragma translate_off
generic map (
INIT => x"0000")
-- pragma translate_on
port map (
CE => FIFO_Write, -- [in std_logic]
D => Data_In(I), -- [in std_logic]
Clk => Clk, -- [in std_logic]
A0 => srl16_addr(0), -- [in std_logic]
A1 => srl16_addr(1), -- [in std_logic]
A2 => srl16_addr(2), -- [in std_logic]
A3 => srl16_addr(3), -- [in std_logic]
Q => Data_Out(I)); -- [out std_logic]
end generate FIFO_RAM;
Addr(0 to ADDR_BITS-1) <= addr_i(ADDR_BITS-1 downto 0);
UNDERFLOW_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset = '1' then
underflow_i <= '0';
elsif underflow_i = '1' then
underflow_i <= '1'; -- Underflow sticks until reset
else
underflow_i <= fifo_empty_i and FIFO_Read;
end if;
end if;
end process;
Underflow <= underflow_i;
------------------------------------------------------------------------------
-- Overflow detection:
-- The only case of non-erroneous operation for which addr_i (including
-- the high-order bit used as the empty flag) taken as an unsigned value
-- may be greater than or equal to C_DEPTH is when the FIFO is empty.
-- No overflow is possible when FIFO_Read, since Num_To_Reread is
-- overriden in this case and the number elements can at most remain
-- unchanged (that being when there is a simultaneous FIFO_Write).
-- However, when there is no FIFO_Read and but there is either a
-- FIFO_Write or a restoration of one or more read elements, then
-- addr_i becoming greater than or equal to C_DEPTH indicates an overflow.
------------------------------------------------------------------------------
OVERFLOW_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset = '1' then
overflow_i <= '0';
elsif overflow_i = '1' then
overflow_i <= '1'; -- Overflow sticks until Reset
elsif FIFO_Read = '0' and
(FIFO_Write= '1' or bitwise_or(Num_To_Reread)='1') and
UNSIGNED(addr_i_p1) >= C_DEPTH then
overflow_i <= '1';
else
overflow_i <= '0';
end if;
end if;
end process;
Overflow <= overflow_i;
end architecture imp;
|
apache-2.0
|
mkotormus/G3_OrchestraConductorDemo
|
src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/microblaze_v9_3/7b6e2d75/hdl/vhdl/mmu_tlb.vhd
|
1
|
28978
|
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`protect end_protected
|
apache-2.0
|
mkotormus/G3_OrchestraConductorDemo
|
src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/axi_master_burst_v2_0/1af76933/hdl/src/vhdl/axi_master_burst_skid2mm_buf.vhd
|
1
|
18117
|
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- Filename: axi_master_burst_skid2mm_buf.vhd
--
-- Description:
-- Implements the AXi Skid Buffer in the Option 2 (Registerd outputs) mode.
--
-- This Module also provides Write Data Bus Mirroring and WSTRB
-- Demuxing to match a narrow Stream to a wider MMap Write
-- Channel. By doing this in the skid buffer, the resource
-- utilization of the skid buffer can be minimized by only
-- having to buffer/mux the Stream data width, not the MMap
-- Data width.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_master_burst_skid2mm_buf.vhd
-- |
-- |- axi_master_burst_wr_demux.vhd
--
-------------------------------------------------------------------------------
-- Revision History:
--
--
-- Author: DET
-- Revision: $Revision: 1.0 $
-- Date: $10/19/2009$
--
-- History:
-- DET 1/19/2011 Initial
-- ~~~~~~
-- - Adapted from AXI DataMover v2_00_a axi_datamover_skid2axi_buf.vhd
-- ^^^^^^
--
-- DET 2/10/2011 Initial for EDK 13.2
-- ~~~~~~
-- -- Per CR593362
-- - Removed resets from the data path of the Skid and Output registers.
-- ^^^^^^
-- ~~~~~~
-- SK 12/16/12 -- v2.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI MASTER BURST to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_v4_0
-- 4. No Logic Updates
-- ^^^^^^
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_master_burst_v2_0;
use axi_master_burst_v2_0.axi_master_burst_wr_demux;
-------------------------------------------------------------------------------
entity axi_master_burst_skid2mm_buf is
generic (
C_MDATA_WIDTH : INTEGER range 32 to 256 := 32 ;
-- Width of the MMap Write Data bus (in bits)
C_SDATA_WIDTH : INTEGER range 8 to 256 := 32 ;
-- Width of the Stream Data bus (in bits)
C_ADDR_LSB_WIDTH : INTEGER range 1 to 8 := 5
-- Width of the LS address bus needed to Demux the WSTRB
);
port (
--------------------------------------------------------------------------
-- System Ports
--------------------------------------------------------------------------
aclk : In std_logic ; -- clock
arst : In std_logic ; -- reset
--------------------------------------------------------------------------
-- Slave Side (Wr Data Controller Input Side )
--------------------------------------------------------------------------
s_addr_lsb : in std_logic_vector(C_ADDR_LSB_WIDTH-1 downto 0); -- Demuxing Control
s_valid : In std_logic ; -- AXI4 Stream Like
s_ready : Out std_logic ; -- AXI4 Stream Like
s_data : In std_logic_vector(C_SDATA_WIDTH-1 downto 0); -- AXI4 Stream Like
s_strb : In std_logic_vector((C_SDATA_WIDTH/8)-1 downto 0); -- AXI4 Stream Like
s_last : In std_logic ; -- AXI4 Stream Like
--------------------------------------------------------------------------
-- Master Side (MMap Write Data Output Side)
--------------------------------------------------------------------------
m_valid : Out std_logic ; -- AXI4 Stream Like
m_ready : In std_logic ; -- AXI4 Stream Like
m_data : Out std_logic_vector(C_MDATA_WIDTH-1 downto 0); -- AXI4 Stream Like
m_strb : Out std_logic_vector((C_MDATA_WIDTH/8)-1 downto 0); -- AXI4 Stream Like
m_last : Out std_logic -- AXI4 Stream Like
);
end entity axi_master_burst_skid2mm_buf;
architecture implementation of axi_master_burst_skid2mm_buf is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
Constant IN_DATA_WIDTH : integer := C_SDATA_WIDTH;
Constant MM2STRM_WIDTH_RATIO : integer := C_MDATA_WIDTH/C_SDATA_WIDTH;
-- Signals decalrations -------------------------
Signal sig_reset_reg : std_logic := '0';
signal sig_spcl_s_ready_set : std_logic := '0';
signal sig_data_skid_reg : std_logic_vector(IN_DATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_skid_reg : std_logic_vector((C_MDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_skid_reg : std_logic := '0';
signal sig_skid_reg_en : std_logic := '0';
signal sig_data_skid_mux_out : std_logic_vector(IN_DATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_skid_mux_out : std_logic_vector((C_MDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_skid_mux_out : std_logic := '0';
signal sig_skid_mux_sel : std_logic := '0';
signal sig_data_reg_out : std_logic_vector(IN_DATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_reg_out : std_logic_vector((C_MDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_reg_out : std_logic := '0';
signal sig_data_reg_out_en : std_logic := '0';
signal sig_m_valid_out : std_logic := '0';
signal sig_m_valid_dup : std_logic := '0';
signal sig_m_valid_comb : std_logic := '0';
signal sig_s_ready_out : std_logic := '0';
signal sig_s_ready_dup : std_logic := '0';
signal sig_s_ready_comb : std_logic := '0';
signal sig_mirror_data_out : std_logic_vector(C_MDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_wstrb_demux_out : std_logic_vector((C_MDATA_WIDTH/8)-1 downto 0) := (others => '0');
-- Register duplication attribute assignments to control fanout
-- on handshake output signals
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
Attribute KEEP of sig_m_valid_out : signal is "TRUE"; -- definition
Attribute KEEP of sig_m_valid_dup : signal is "TRUE"; -- definition
Attribute KEEP of sig_s_ready_out : signal is "TRUE"; -- definition
Attribute KEEP of sig_s_ready_dup : signal is "TRUE"; -- definition
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_m_valid_out : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_m_valid_dup : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_out : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_dup : signal is "no";
begin --(architecture implementation)
m_valid <= sig_m_valid_out;
s_ready <= sig_s_ready_out;
m_strb <= sig_strb_reg_out;
m_last <= sig_last_reg_out;
m_data <= sig_mirror_data_out;
-- Assign the special s_ready FLOP set signal
sig_spcl_s_ready_set <= sig_reset_reg;
-- Generate the ouput register load enable control
sig_data_reg_out_en <= m_ready or not(sig_m_valid_dup);
-- Generate the skid inpit register load enable control
sig_skid_reg_en <= sig_s_ready_dup;
-- Generate the skid mux select control
sig_skid_mux_sel <= not(sig_s_ready_dup);
-- Skid Mux
sig_data_skid_mux_out <= sig_data_skid_reg
When (sig_skid_mux_sel = '1')
Else s_data;
sig_strb_skid_mux_out <= sig_strb_skid_reg
When (sig_skid_mux_sel = '1')
--Else s_strb;
Else sig_wstrb_demux_out;
sig_last_skid_mux_out <= sig_last_skid_reg
When (sig_skid_mux_sel = '1')
Else s_last;
-- m_valid combinational logic
sig_m_valid_comb <= s_valid or
(sig_m_valid_dup and
(not(sig_s_ready_dup) or
not(m_ready)));
-- s_ready combinational logic
sig_s_ready_comb <= m_ready or
(sig_s_ready_dup and
(not(sig_m_valid_dup) or
not(s_valid)));
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_THE_RST
--
-- Process Description:
-- Register input reset
--
-------------------------------------------------------------
REG_THE_RST : process (aclk)
begin
if (aclk'event and aclk = '1') then
sig_reset_reg <= arst;
end if;
end process REG_THE_RST;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: s_ready_FLOP
--
-- Process Description:
-- Registers s_ready handshake signals per Skid Buffer
-- Option 2 scheme
--
-------------------------------------------------------------
s_ready_FLOP : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (arst = '1') then
sig_s_ready_out <= '0';
sig_s_ready_dup <= '0';
Elsif (sig_spcl_s_ready_set = '1') Then
sig_s_ready_out <= '1';
sig_s_ready_dup <= '1';
else
sig_s_ready_out <= sig_s_ready_comb;
sig_s_ready_dup <= sig_s_ready_comb;
end if;
end if;
end process s_ready_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: m_valid_FLOP
--
-- Process Description:
-- Registers m_valid handshake signals per Skid Buffer
-- Option 2 scheme
--
-------------------------------------------------------------
m_valid_FLOP : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (arst = '1' or
sig_spcl_s_ready_set = '1') then -- Fix from AXI DMA
sig_m_valid_out <= '0';
sig_m_valid_dup <= '0';
else
sig_m_valid_out <= sig_m_valid_comb;
sig_m_valid_dup <= sig_m_valid_comb;
end if;
end if;
end process m_valid_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SKID_DATA_REG
--
-- Process Description:
-- This process implements the Skid register for the
-- Skid Buffer Data signals.
--
-------------------------------------------------------------
SKID_DATA_REG : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (sig_skid_reg_en = '1') then
sig_data_skid_reg <= s_data;
else
null; -- hold current state
end if;
end if;
end process SKID_DATA_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SKID_CNTL_REG
--
-- Process Description:
-- This process implements the Output registers for the
-- Skid Buffer Control signals
--
-------------------------------------------------------------
SKID_CNTL_REG : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (arst = '1') then
sig_strb_skid_reg <= (others => '0');
sig_last_skid_reg <= '0';
elsif (sig_skid_reg_en = '1') then
sig_strb_skid_reg <= sig_wstrb_demux_out;
sig_last_skid_reg <= s_last;
else
null; -- hold current state
end if;
end if;
end process SKID_CNTL_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: OUTPUT_DATA_REG
--
-- Process Description:
-- This process implements the Output register for the
-- Data signals.
--
-------------------------------------------------------------
OUTPUT_DATA_REG : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (sig_data_reg_out_en = '1') then
sig_data_reg_out <= sig_data_skid_mux_out;
else
null; -- hold current state
end if;
end if;
end process OUTPUT_DATA_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: OUTPUT_CNTL_REG
--
-- Process Description:
-- This process implements the Output registers for the
-- control signals.
--
-------------------------------------------------------------
OUTPUT_CNTL_REG : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (arst = '1') then
sig_strb_reg_out <= (others => '0');
sig_last_reg_out <= '0';
elsif (sig_data_reg_out_en = '1') then
sig_strb_reg_out <= sig_strb_skid_mux_out;
sig_last_reg_out <= sig_last_skid_mux_out;
else
null; -- hold current state
end if;
end if;
end process OUTPUT_CNTL_REG;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_WR_DATA_MIRROR
--
-- Process Description:
-- Implement the Write Data Mirror structure
--
-- Note that it is required that the Stream Width be less than
-- or equal to the MMap WData width.
--
-------------------------------------------------------------
DO_WR_DATA_MIRROR : process (sig_data_reg_out)
begin
for slice_index in 0 to MM2STRM_WIDTH_RATIO-1 loop
sig_mirror_data_out(((C_SDATA_WIDTH*slice_index)+C_SDATA_WIDTH)-1
downto C_SDATA_WIDTH*slice_index)
<= sig_data_reg_out;
end loop;
end process DO_WR_DATA_MIRROR;
------------------------------------------------------------
-- Instance: I_WSTRB_DEMUX
--
-- Description:
-- Instance for the Write Strobe DeMux.
--
------------------------------------------------------------
I_WSTRB_DEMUX : entity axi_master_burst_v2_0.axi_master_burst_wr_demux
generic map (
C_SEL_ADDR_WIDTH => C_ADDR_LSB_WIDTH ,
C_MMAP_DWIDTH => C_MDATA_WIDTH ,
C_STREAM_DWIDTH => C_SDATA_WIDTH
)
port map (
wstrb_in => s_strb ,
demux_wstrb_out => sig_wstrb_demux_out ,
debeat_saddr_lsb => s_addr_lsb
);
end implementation;
|
apache-2.0
|
mkotormus/G3_OrchestraConductorDemo
|
src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/proc_common_v4_0/bb615326/hdl/src/vhdl/ipif_mirror128.vhd
|
15
|
17011
|
--SINGLE_FILE_TAG
-------------------------------------------------------------------------------
-- $Id: ipif_mirror128.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- ipif_mirror128 - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: ipif_steer128.vhd
-- Version: v1.00b
-- Description: Read and Write Steering logic for IPIF
--
-- For writes, this logic mirrors data from the master with
-- the smaller bus width to the correct byte lanes of the
-- larger IPIF devices. The BE signals are also mirrored.
--
-- For reads, the Decode_size signal determines how read
-- data is steered onto the byte lanes. To simplify the
-- logic, the read data is mirrored onto the entire data
-- bus, insuring that the lanes corrsponding to the BE's
-- have correct data.
--
--
--
-------------------------------------------------------------------------------
-- Structure:
--
-- ipif_steer128.vhd
--
-------------------------------------------------------------------------------
-- Author: Gary Burch
-- History:
-- GAB 10-10-2008 -- First version
-- ^^^^^^
-- First version of IPIF mirror logic.
-- ~~~~~~
--
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-------------------------------------------------------------------------------
-- Port declarations
-- generic definitions:
-- C_DWIDTH : integer := width of IPIF Slave
-- C_SMALLEST : integer := width of smallest Master (not access size)
-- that will access the IPIF Slave
-- C_AWIDTH : integer := width of the host address bus attached to
-- the IPIF
-- port definitions:
-- Wr_Data_In : in Write Data In (from host data bus)
-- Rd_Data_In : in Read Data In (from IPIC data bus)
-- Addr : in Address bus from host address bus
-- BE_In : in Byte Enables In from host side
-- Decode_size : in Size of Master accessing slave
-- Size indication (Decode_size)
-- 00 - 32-Bit Master
-- 01 - 64-Bit Master
-- 10 - 128-Bit Master
-- 11 - 256-Bit Master (Not Support)
--
-- Wr_Data_Out : out Write Data Out (to IPIF data bus)
-- Rd_Data_Out : out Read Data Out (to host data bus)
-- BE_Out : out Byte Enables Out to IPIF side
--
-------------------------------------------------------------------------------
entity ipif_mirror128 is
generic (
C_DWIDTH : integer := 32; -- 64, 128 (Slave Dwidth)
C_SMALLEST : integer := 32; -- 32, 64, 128 (Smallest Master)
C_AWIDTH : integer := 32
);
port (
Wr_Addr : in std_logic_vector(0 to C_AWIDTH-1);
Wr_Size : in std_logic_vector(0 to 1);
Rd_Addr : in std_logic_vector(0 to C_AWIDTH-1);
Rd_Size : in std_logic_vector(0 to 1);
Wr_Data_In : in std_logic_vector(0 to C_DWIDTH-1);
Rd_Data_In : in std_logic_vector(0 to C_DWIDTH-1);
BE_In : in std_logic_vector(0 to C_DWIDTH/8-1);
Wr_Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
Rd_Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
BE_Out : out std_logic_vector(0 to C_DWIDTH/8-1)
);
end entity ipif_mirror128;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture IMP of ipif_mirror128 is
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin -- architecture IMP
GEN_SAME: if C_DWIDTH <= C_SMALLEST generate
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
Rd_Data_Out <= Rd_Data_In;
end generate GEN_SAME;
-------------------------------------------------------------------------------
-- Write Data Mirroring
-------------------------------------------------------------------------------
---------------------
-- 64 Bit Support --
---------------------
GEN_WR_64_32: if C_DWIDTH = 64 and C_SMALLEST = 32 generate
signal addr_bits : std_logic;
begin
CONNECT_PROC: process (addr_bits,Wr_Addr,Wr_Data_In,BE_In,Wr_Size)
begin
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
addr_bits <= Wr_Addr(C_AWIDTH-3); --a29
case addr_bits is
when '0' =>
case Wr_Size is
when "00" => -- 32-Bit Master
BE_Out(4 to 7) <= (others => '0');
when others => null;
end case;
when '1' =>
case Wr_Size is
when "00" => -- 32-Bit Master
Wr_Data_Out(32 to 63) <= Wr_Data_In(0 to 31);
BE_Out(4 to 7) <= BE_In(0 to 3);
BE_Out(0 to 3) <= (others => '0');
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_WR_64_32;
---------------------
-- 128 Bit Support --
---------------------
GEN_WR_128_32: if C_DWIDTH = 128 and C_SMALLEST = 32 generate
signal addr_bits : std_logic_vector(0 to 1);
begin
CONNECT_PROC: process (addr_bits,Wr_Addr,Wr_Data_In,BE_In,Wr_Size)
begin
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
addr_bits <= Wr_Addr(C_AWIDTH-4 to C_AWIDTH-3);
case addr_bits is
when "00" => --0
case Wr_Size is
when "00" => -- 32-Bit Master
BE_Out(4 to 15) <= (others => '0');
when "01" => -- 64-Bit Master
BE_Out(8 to 15) <= (others => '0');
when others => null;
end case;
when "01" => --4
case Wr_Size is
when "00" => -- 32-Bit Master
Wr_Data_Out(32 to 63) <= Wr_Data_In(0 to 31);
BE_Out(4 to 7) <= BE_In(0 to 3);
BE_Out(0 to 3) <= (others => '0');
BE_Out(8 to 15) <= (others => '0');
when others => null;
end case;
when "10" => --8
case Wr_Size is
when "00" => -- 32-Bit Master
Wr_Data_Out(64 to 95) <= Wr_Data_In(0 to 31);
BE_Out(8 to 11) <= BE_In(0 to 3);
BE_Out(0 to 7) <= (others => '0');
BE_Out(12 to 15) <= (others => '0');
when "01" => -- 64-Bit Master
Wr_Data_Out(64 to 127) <= Wr_Data_In(0 to 63);
BE_Out(8 to 15) <= BE_In(0 to 7);
BE_Out(0 to 7) <= (others => '0');
when others => null;
end case;
when "11" => --C
case Wr_Size is
when "00" => --32-Bit Master
Wr_Data_Out(96 to 127) <= Wr_Data_In(0 to 31);
BE_Out(12 to 15) <= BE_In(0 to 3);
BE_Out(0 to 11) <= (others => '0');
when "01" => --64-Bit Master
Wr_Data_Out(64 to 127) <= Wr_Data_In(0 to 63);
BE_Out(8 to 15) <= BE_In(0 to 7);
BE_Out(0 to 7) <= (others => '0');
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_WR_128_32;
GEN_WR_128_64: if C_DWIDTH = 128 and C_SMALLEST = 64 generate
signal addr_bits : std_logic;
begin
CONNECT_PROC: process (addr_bits,Wr_Addr,Wr_Data_In,BE_In,Wr_Size)
begin
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
addr_bits <= Wr_Addr(C_AWIDTH-4);
case addr_bits is
when '0' =>
case Wr_Size is
when "01" => -- 64-Bit Master
BE_Out(8 to 15) <= (others => '0');
when others => null;
end case;
when '1' => --8
case Wr_Size is
when "01" => -- 64-Bit Master
Wr_Data_Out(64 to 127) <= Wr_Data_In(0 to 63);
BE_Out(8 to 15) <= BE_In(0 to 7);
BE_Out(0 to 7) <= (others => '0');
when others => null;
end case;
when others =>
null;
end case;
end process CONNECT_PROC;
end generate GEN_WR_128_64;
-------------------------------------------------------------------------------
-- Read Data Steering
-------------------------------------------------------------------------------
---------------------
-- 64 Bit Support --
---------------------
GEN_RD_64_32: if C_DWIDTH = 64 and C_SMALLEST = 32 generate
signal addr_bits : std_logic;
begin
CONNECT_PROC: process (addr_bits,Rd_Addr,Rd_Data_In,Rd_Size)
begin
Rd_Data_Out <= Rd_Data_In;
addr_bits <= Rd_Addr(C_AWIDTH-3); --a29
case addr_bits is
when '1' =>
case Rd_Size is
when "00" => -- 32-Bit Master
Rd_Data_Out(0 to 31) <= Rd_Data_In(32 to 63);
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_RD_64_32;
---------------------
-- 128 Bit Support --
---------------------
GEN_RD_128_32: if C_DWIDTH = 128 and C_SMALLEST = 32 generate
signal addr_bits : std_logic_vector(0 to 1);
begin
CONNECT_PROC: process (addr_bits,Rd_Addr,Rd_Data_In,Rd_Size)
begin
Rd_Data_Out <= Rd_Data_In;
addr_bits <= Rd_Addr(C_AWIDTH-4 to C_AWIDTH-3);
case addr_bits is
when "01" => --4
case Rd_Size is
when "00" => -- 32-Bit Master
Rd_Data_Out(0 to 31) <= Rd_Data_In(32 to 63);
when others => null;
end case;
when "10" => --8
case Rd_Size is
when "00" => -- 32-Bit Master
Rd_Data_Out(0 to 31) <= Rd_Data_In(64 to 95);
when "01" => -- 64-Bit Master
Rd_Data_Out(0 to 63) <= Rd_Data_In(64 to 127);
when others => null;
end case;
when "11" => --C
case Rd_Size is
when "00" => --32-Bit Master
Rd_Data_Out(0 to 31) <= Rd_Data_In(96 to 127);
when "01" => --64-Bit Master
Rd_Data_Out(0 to 63) <= Rd_Data_In(64 to 127);
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_RD_128_32;
GEN_RD_128_64: if C_DWIDTH = 128 and C_SMALLEST = 64 generate
signal addr_bits : std_logic;
begin
CONNECT_PROC: process (addr_bits,Rd_Addr,Rd_Data_In,Rd_Size)
begin
Rd_Data_Out <= Rd_Data_In;
addr_bits <= Rd_Addr(C_AWIDTH-4);
case addr_bits is
when '1' => --8
case Rd_Size is
when "01" => -- 64-Bit Master
Rd_Data_Out(0 to 63) <= Rd_Data_In(64 to 127);
when others => null;
end case;
when others =>
null;
end case;
end process CONNECT_PROC;
end generate GEN_RD_128_64;
end architecture IMP;
|
apache-2.0
|
mkotormus/G3_OrchestraConductorDemo
|
src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/proc_common_v4_0/bb615326/hdl/src/vhdl/pselect_mask.vhd
|
15
|
13363
|
-------------------------------------------------------------------------------
-- $Id: pselect_mask.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pselect_mask.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2002-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pselect_mask.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pselect_mask.vhd
--
-------------------------------------------------------------------------------
-- Author: goran
-- Revision: $Revision: 1.1.4.1 $
-- Date: $Date: 2010/09/14 22:35:47 $
--
-- History:
-- goran 2002-02-06 First Version
--
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library Unisim;
use Unisim.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_AB -- number of address bits to decode
-- C_AW -- width of address bus
-- C_BAR -- base address of peripheral (peripheral select
-- is asserted when the C_AB most significant
-- address bits match the C_AB most significant
-- C_BAR bits
-- Definition of Ports:
-- A -- address input
-- AValid -- address qualifier
-- PS -- peripheral select
-------------------------------------------------------------------------------
entity pselect_mask is
generic (
C_AW : integer := 32;
C_BAR : std_logic_vector(0 to 31) := "00000000000000100000000000000000";
C_MASK : std_logic_vector(0 to 31) := "00000000000001111100000000000000"
);
port (
A : in std_logic_vector(0 to C_AW-1);
Valid : in std_logic;
CS : out std_logic
);
end entity pselect_mask;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
library unisim;
use unisim.all;
architecture imp of pselect_mask is
-- component LUT4
-- generic(
-- INIT : bit_vector := X"0000"
-- );
-- port (
-- O : out std_logic;
-- I0 : in std_logic := '0';
-- I1 : in std_logic := '0';
-- I2 : in std_logic := '0';
-- I3 : in std_logic := '0');
-- end component;
-- component MUXCY is
-- port (
-- O : out std_logic;
-- CI : in std_logic;
-- DI : in std_logic;
-- S : in std_logic
-- );
-- end component MUXCY;
function Nr_Of_Ones (S : std_logic_vector) return natural is
variable tmp : natural := 0;
begin -- function Nr_Of_Ones
for I in S'range loop
if (S(I) = '1') then
tmp := tmp + 1;
end if;
end loop; -- I
return tmp;
end function Nr_Of_Ones;
function fix_AB (B : boolean; I : integer) return integer is
begin -- function fix_AB
if (not B) then
return I + 1;
else
return I;
end if;
end function fix_AB;
constant Nr : integer := Nr_Of_Ones(C_MASK);
constant Use_CIN : boolean := ((Nr mod 4) = 0);
constant AB : integer := fix_AB(Use_CIN, Nr);
attribute INIT : string;
constant NUM_LUTS : integer := (AB-1)/4+1;
-- signal lut_out : std_logic_vector(0 to NUM_LUTS-1);
-- signal carry_chain : std_logic_vector(0 to NUM_LUTS);
-- function to initialize LUT within pselect
type int4 is array (3 downto 0) of integer;
function pselect_init_lut(i : integer;
AB : integer;
NUM_LUTS : integer;
C_AW : integer;
C_BAR : std_logic_vector(0 to 31))
return bit_vector is
variable init_vector : bit_vector(15 downto 0) := X"0001";
variable j : integer := 0;
variable val_in : int4;
begin
for j in 0 to 3 loop
if i < NUM_LUTS-1 or j <= ((AB-1) mod 4) then
val_in(j) := conv_integer(C_BAR(i*4+j));
else val_in(j) := 0;
end if;
end loop;
init_vector := To_bitvector(conv_std_logic_vector(2**(val_in(3)*8+
val_in(2)*4+val_in(1)*2+val_in(0)*1),16));
return init_vector;
end pselect_init_lut;
signal A_Bus : std_logic_vector(0 to AB);
signal BAR : std_logic_vector(0 to AB);
-------------------------------------------------------------------------------
-- Begin architecture section
-------------------------------------------------------------------------------
begin -- VHDL_RTL
Make_Busses : process (A,Valid) is
variable tmp : natural;
begin -- process Make_Busses
tmp := 0;
A_Bus <= (others => '0');
BAR <= (others => '0');
for I in C_MASK'range loop
if (C_MASK(I) = '1') then
A_Bus(tmp) <= A(I);
BAR(tmp) <= C_BAR(I);
tmp := tmp + 1;
end if;
end loop; -- I
if (not Use_CIN) then
BAR(tmp) <= '1';
A_Bus(tmp) <= Valid;
end if;
end process Make_Busses;
-- More_Than_3_Bits : if (AB > 3) generate
-- Using_CIn: if (Use_CIN) generate
-- carry_chain(0) <= Valid;
-- end generate Using_CIn;
-- No_CIn: if (not Use_CIN) generate
-- carry_chain(0) <= '1';
-- end generate No_CIn;
-- GEN_DECODE : for i in 0 to NUM_LUTS-1 generate
-- signal lut_in : std_logic_vector(3 downto 0);
-- begin
-- GEN_LUT_INPUTS : for j in 0 to 3 generate
-- -- Generate to assign address bits to LUT4 inputs
-- GEN_INPUT : if i < NUM_LUTS-1 or j <= ((AB-1) mod 4) generate
-- lut_in(j) <= A_Bus(i*4+j);
-- end generate;
-- -- Generate to assign zeros to remaining LUT4 inputs
-- GEN_ZEROS : if not(i < NUM_LUTS-1 or j <= ((AB-1) mod 4)) generate
-- lut_in(j) <= '0';
-- end generate;
-- end generate;
---------------------------------------------------------------------------------
---- RTL version without LUT instantiation for XST
---------------------------------------------------------------------------------
-- lut_out(i) <= (lut_in(0) xnor BAR(i*4+0)) and
-- (lut_in(1) xnor BAR(i*4+1)) and
-- (lut_in(2) xnor BAR(i*4+2)) and
-- (lut_in(3) xnor BAR(i*4+3));
---------------------------------------------------------------------------------
---- Structural version with LUT instantiation for Synplicity (when RLOC is
---- desired for placing LUT
---------------------------------------------------------------------------------
---- LUT4_I : LUT4
---- generic map(
---- -- Function init_lut is used to generate INIT value for LUT4
---- INIT => pselect_init_lut(i,C_AB,NUM_LUTS,C_AW,C_BAR)
---- )
---- port map (
---- O => lut_out(i), -- [out]
---- I0 => lut_in(0), -- [in]
---- I1 => lut_in(1), -- [in]
---- I2 => lut_in(2), -- [in]
---- I3 => lut_in(3)); -- [in]
---------------------------------------------------------------------------------
-- MUXCY_I : MUXCY
-- port map (
-- O => carry_chain(i+1), --[out]
-- CI => carry_chain(i), --[in]
-- DI => '0', --[in]
-- S => lut_out(i) --[in]
-- );
-- end generate;
-- CS <= carry_chain(NUM_LUTS); -- assign end of carry chain to output
-- end generate More_Than_3_Bits;
-- Less_than_4_bits: if (AB < 4) generate
CS <= Valid when A_Bus=BAR else '0';
-- end generate Less_than_4_bits;
end imp;
|
apache-2.0
|
mkotormus/G3_OrchestraConductorDemo
|
src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/microblaze_v9_3/7b6e2d75/hdl/vhdl/mux_bus.vhd
|
1
|
12443
|
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`protect end_protected
|
apache-2.0
|
mkotormus/G3_OrchestraConductorDemo
|
src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/microblaze_v9_3/7b6e2d75/hdl/vhdl/fpu_sqrt.vhd
|
1
|
16983
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 10832)
`protect data_block
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8dQ=
`protect end_protected
|
apache-2.0
|
mkotormus/G3_OrchestraConductorDemo
|
src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/microblaze_v9_3/7b6e2d75/hdl/vhdl/operand_select.vhd
|
1
|
40780
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 28448)
`protect data_block
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`protect end_protected
|
apache-2.0
|
mkotormus/G3_OrchestraConductorDemo
|
src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/fifo_generator_v12_0/924f3d25/hdl/ramfifo/wr_bin_cntr.vhd
|
5
|
24719
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 16560)
`protect data_block
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`protect end_protected
|
apache-2.0
|
mkotormus/G3_OrchestraConductorDemo
|
src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/microblaze_v9_3/7b6e2d75/hdl/vhdl/mul_unit.vhd
|
1
|
72119
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 51648)
`protect data_block
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4zCyCQ8l
`protect end_protected
|
apache-2.0
|
mkotormus/G3_OrchestraConductorDemo
|
src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/fifo_generator_v12_0/924f3d25/hdl/ramfifo/bram_sync_reg.vhd
|
5
|
7904
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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AhXEh1hsTg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4112)
`protect data_block
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`protect end_protected
|
apache-2.0
|
mkotormus/G3_OrchestraConductorDemo
|
src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/blk_mem_gen_v8_2/f2a44852/hdl/blk_mem_gen_top.vhd
|
11
|
73440
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 52624)
`protect data_block
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`protect end_protected
|
apache-2.0
|
mkotormus/G3_OrchestraConductorDemo
|
src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/axi_intc_v4_1/28e93d3e/hdl/src/vhdl/double_synchronizer.vhd
|
5
|
6181
|
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename : double_synchronizer.vhd
-- Version : v3.0
-- Description: The double_synchronizer is having the double flop synchronization logic
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-------------------------------------------------------------------------------
-- Author: NLR
-- History:
-- NLR 3/21/2011 Initial version
-- ^^^^^^^
-- ^^^^^^^
-- SK 10/10/12
--
-- 1. Added cascade mode support in v1.03.a version of the core
-- 2. Updated major version of the core
-- ~~~~~~
-- ~~~~~~
-- SK 12/16/12 -- v3.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_v4_0
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*N"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- RESET_2 signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- counter signals: "*cntr*", "*count*"
-- ports: - Names in Uppercase
-- processes: "*_REG", "*_CMB"
-- component instantiations: "<ENTITY_>MODULE<#|_FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library axi_intc_v4_1;
use axi_intc_v4_1.all;
library unisim;
use unisim.vcomponents.FDR;
-------------------------------------------------------------------------------
entity double_synchronizer is
generic (
C_DWIDTH : integer range 1 to 32 := 1
);
port (
CLK_2 : in std_logic;
RESET_2_n : in std_logic; -- active_low
DATA_IN : in std_logic_vector(C_DWIDTH-1 downto 0);
SYNC_DATA_OUT : out std_logic_vector(C_DWIDTH-1 downto 0)
);
end entity;
-------------------------------------------------------------------------------
architecture RTL of double_synchronizer is
signal RESET_2_p : std_logic;
signal data_in_d1 : std_logic_vector(C_DWIDTH-1 downto 0);
-----
begin
-----
-- active high Reset
RESET_2_p <= not RESET_2_n;
REG_GEN : for i in 0 to (C_DWIDTH - 1) generate
BLOCK_GEN: block
attribute ASYNC_REG : string;
attribute ASYNC_REG of FIRST_FLOP_i : label is "TRUE";
begin
FIRST_FLOP_i: component FDR
port map (
Q => data_in_d1(i),
C => CLK_2,
D => DATA_IN(i),
R => RESET_2_p
);
SECOND_FLOP_i: component FDR
port map (
Q => SYNC_DATA_OUT(i),
C => CLK_2,
D => data_in_d1(i),
R => RESET_2_p
);
end block BLOCK_GEN;
end generate REG_GEN;
-------------------------------------------------------------------------------
end RTL;
-------------------------------------------------------------------------------
|
apache-2.0
|
mkotormus/G3_OrchestraConductorDemo
|
src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/proc_common_v4_0/bb615326/hdl/src/vhdl/pf_occ_counter_top.vhd
|
15
|
12619
|
-------------------------------------------------------------------------------
-- $Id: pf_occ_counter_top.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pf_occ_counter_top - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pf_occ_counter_top.vhd
--
-- Description: Implements parameterized up/down counter
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pf_occ_counter_top.vhd
--
-------------------------------------------------------------------------------
-- Author: D. Thorpe
-- Revision: $Revision: 1.1.4.1 $
-- Date: $Date: 2010/09/14 22:35:47 $
--
-- History:
-- DET 2001-08-30 First Version
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
--Use IEEE.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
library proc_common_v4_0;
use proc_common_v4_0.pf_occ_counter;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity pf_occ_counter_top is
generic (
C_COUNT_WIDTH : integer := 10
);
port (
Clk : in std_logic;
Rst : in std_logic;
Load_Enable : in std_logic;
Load_value : in std_logic_vector(0 to C_COUNT_WIDTH-1);
Count_Down : in std_logic;
Count_Up : in std_logic;
By_2 : In std_logic;
Count_Out : out std_logic_vector(0 to C_COUNT_WIDTH-1);
almost_full : Out std_logic;
full : Out std_logic;
almost_empty : Out std_logic;
empty : Out std_logic
);
end entity pf_occ_counter_top;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of pf_occ_counter_top is
Signal sig_cnt_enable : std_logic;
Signal sig_cnt_up_n_dwn : std_logic;
Signal sig_carry_out : std_logic;
Signal sig_count_out : std_logic_vector(0 to C_COUNT_WIDTH-1);
Signal upper_cleared : std_logic;
Signal lower_set : std_logic;
Signal lower_cleared : std_logic;
Signal empty_state : std_logic_vector(0 to 2);
Signal full_state : std_logic_vector(0 to 3);
Signal sig_full : std_logic;
Signal sig_almost_full : std_logic;
Signal sig_going_full : std_logic;
Signal sig_empty : std_logic;
Signal sig_almost_empty : std_logic;
begin -- VHDL_RTL
full <= sig_full;
almost_full <= sig_almost_full;
empty <= sig_empty;
almost_empty <= sig_almost_empty;
-- Misc signal assignments
Count_Out <= sig_count_out;
sig_cnt_enable <= (Count_Up and not(sig_full))
xor (Count_Down and not(sig_empty));
sig_cnt_up_n_dwn <= not(Count_Up);
I_UP_DWN_COUNTER : entity proc_common_v4_0.pf_occ_counter
generic map (
C_COUNT_WIDTH
)
port map(
Clk => Clk,
Rst => Rst,
Carry_Out => sig_carry_out,
Load_In => Load_value,
Count_Enable => sig_cnt_enable,
Count_Load => Load_Enable,
Count_Down => sig_cnt_up_n_dwn,
Cnt_by_2 => By_2,
Count_Out => sig_count_out
);
TEST_UPPER_BITS : process (sig_count_out)
Variable all_cleared : boolean;
Variable loop_count : integer;
Begin
--loop_count := 0;
all_cleared := True;
for loop_count in 0 to C_COUNT_WIDTH-2 loop
If (sig_count_out(loop_count) = '1') Then
all_cleared := False;
else
null;
End if;
End loop;
-- -- Search through the upper counter bits starting with the MSB
-- while (loop_count < C_COUNT_WIDTH-2) loop
--
-- If (sig_count_out(loop_count) = '1') Then
-- all_cleared := False;
-- else
-- null;
-- End if;
--
-- loop_count := loop_count + 1;
--
-- End loop;
-- now assign the outputs
If (all_cleared) then
upper_cleared <= '1';
else
upper_cleared <= '0';
End if;
End process TEST_UPPER_BITS;
empty_state <= upper_cleared & sig_count_out(C_COUNT_WIDTH-2) &
sig_count_out(C_COUNT_WIDTH-1);
STATIC_EMPTY_DETECT : process (empty_state)
Begin
Case empty_state Is
When "100" =>
sig_empty <= '1';
sig_almost_empty <= '0';
When "101" =>
sig_empty <= '0';
sig_almost_empty <= '1';
When "110" =>
sig_empty <= '0';
sig_almost_empty <= '0';
When others =>
sig_empty <= '0';
sig_almost_empty <= '0';
End case;
End process STATIC_EMPTY_DETECT;
TEST_LOWER_BITS : process (sig_count_out)
Variable all_cleared : boolean;
Variable all_set : boolean;
Variable loop_count : integer;
Begin
--loop_count := 1;
all_set := True;
all_cleared := True;
for loop_count in 1 to C_COUNT_WIDTH-1 loop
If (sig_count_out(loop_count) = '0') Then
all_set := False;
else
all_cleared := False;
End if;
End loop;
-- -- Search through the lower counter bits starting with the MSB+1
-- while (loop_count < C_COUNT_WIDTH-1) loop
--
-- If (sig_count_out(loop_count) = '0') Then
-- all_set := False;
-- else
-- all_cleared := False;
-- End if;
--
-- loop_count := loop_count + 1;
--
-- End loop;
-- now assign the outputs
If (all_cleared) then
lower_cleared <= '1';
lower_set <= '0';
elsif (all_set) Then
lower_cleared <= '0';
lower_set <= '1';
else
lower_cleared <= '0';
lower_set <= '0';
End if;
End process TEST_LOWER_BITS;
full_state <= sig_count_out(0)
& lower_set
& lower_cleared
& sig_count_out(C_COUNT_WIDTH-1);
STATIC_FULL_DETECT : process (full_state, sig_count_out)
Begin
sig_full <= sig_count_out(0); -- MSB set implies full
Case full_state Is
When "0100" =>
sig_almost_full <= '0';
sig_going_full <= '1';
When "0101" =>
sig_almost_full <= '1';
sig_going_full <= '0';
When others =>
sig_almost_full <= '0';
sig_going_full <= '0';
End case;
End process STATIC_FULL_DETECT;
end architecture implementation;
|
apache-2.0
|
mkotormus/G3_OrchestraConductorDemo
|
src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/blk_mem_gen_v8_2/f2a44852/hdl/blk_mem_axi_regs_fwd.vhd
|
11
|
9545
|
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`protect end_protected
|
apache-2.0
|
mkotormus/G3_OrchestraConductorDemo
|
src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/blk_mem_gen_v8_2/f2a44852/hdl/blk_mem_min_area_pkg.vhd
|
11
|
20310
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 13296)
`protect data_block
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`protect end_protected
|
apache-2.0
|
mkotormus/G3_OrchestraConductorDemo
|
src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/fifo_generator_v12_0/924f3d25/hdl/ramfifo/async_fifo.vhd
|
5
|
33343
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 22944)
`protect data_block
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`protect end_protected
|
apache-2.0
|
mkotormus/G3_OrchestraConductorDemo
|
src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/lmb_bram_if_cntlr_v4_0/816dc01c/hdl/vhdl/xor18.vhd
|
1
|
6196
|
-------------------------------------------------------------------------------
-- $Id: xor18.vhd,v 1.1.2.3 2010/09/06 09:01:24 rolandp Exp $
-------------------------------------------------------------------------------
--
-- (c) Copyright [2003] - [2011] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES
--
------------------------------------------------------------------------------
-- Filename: xor18.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- xor18.vhd
--
-------------------------------------------------------------------------------
-- Author: rolandp
-- Revision: $Revision: 1.1.2.3 $
-- Date: $Date: 2010/09/06 09:01:24 $
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity XOR18 is
generic (
C_USE_LUT6 : boolean);
port (
InA : in std_logic_vector(0 to 17);
res : out std_logic);
end entity XOR18;
architecture IMP of XOR18 is
begin -- architecture IMP
Using_LUT6: if (C_USE_LUT6) generate
signal xor6_1 : std_logic;
signal xor6_2 : std_logic;
signal xor6_3 : std_logic;
signal xor18_c1 : std_logic;
signal xor18_c2 : std_logic;
begin -- generate Using_LUT6
XOR6_1_LUT : LUT6
generic map(
INIT => X"6996966996696996")
port map(
O => xor6_1,
I0 => InA(17),
I1 => InA(16),
I2 => InA(15),
I3 => InA(14),
I4 => InA(13),
I5 => InA(12));
XOR_1st_MUXCY : MUXCY_L
port map (
DI => '1',
CI => '0',
S => xor6_1,
LO => xor18_c1);
XOR6_2_LUT : LUT6
generic map(
INIT => X"6996966996696996")
port map(
O => xor6_2,
I0 => InA(11),
I1 => InA(10),
I2 => InA(9),
I3 => InA(8),
I4 => InA(7),
I5 => InA(6));
XOR_2nd_MUXCY : MUXCY_L
port map (
DI => xor6_1,
CI => xor18_c1,
S => xor6_2,
LO => xor18_c2);
XOR6_3_LUT : LUT6
generic map(
INIT => X"6996966996696996")
port map(
O => xor6_3,
I0 => InA(5),
I1 => InA(4),
I2 => InA(3),
I3 => InA(2),
I4 => InA(1),
I5 => InA(0));
XOR18_XORCY : XORCY
port map (
LI => xor6_3,
CI => xor18_c2,
O => res);
end generate Using_LUT6;
Not_Using_LUT6: if (not C_USE_LUT6) generate
begin -- generate Not_Using_LUT6
res <= InA(17) xor InA(16) xor InA(15) xor InA(14) xor InA(13) xor InA(12) xor
InA(11) xor InA(10) xor InA(9) xor InA(8) xor InA(7) xor InA(6) xor
InA(5) xor InA(4) xor InA(3) xor InA(2) xor InA(1) xor InA(0);
end generate Not_Using_LUT6;
end architecture IMP;
|
apache-2.0
|
mkotormus/G3_OrchestraConductorDemo
|
src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/microblaze_v9_3/7b6e2d75/hdl/vhdl/address_data_hit.vhd
|
1
|
18020
|
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`protect end_protected
|
apache-2.0
|
mkotormus/G3_OrchestraConductorDemo
|
src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/fifo_generator_v12_0/924f3d25/hdl/ramfifo/logic_sshft.vhd
|
5
|
30599
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 20912)
`protect data_block
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`protect end_protected
|
apache-2.0
|
mkotormus/G3_OrchestraConductorDemo
|
src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/axi_master_burst_v2_0/1af76933/hdl/src/vhdl/axi_master_burst_wr_demux.vhd
|
1
|
32014
|
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- Filename: axi_master_burst_wr_demux.vhd
--
-- Description:
-- This file implements the AXI Master Burst Write Strobe De-Multiplexer.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_master_burst_wr_demux.vhd
--
-------------------------------------------------------------------------------
-- Revision History:
--
--
-- Author: DET
-- Revision: $Revision: 1.0 $
-- Date: $1/19/2011$
--
-- History:
-- DET 1/19/2011 Initial
-- ~~~~~~
-- - Adapted from AXi DataMover v2_00_a axi_datamover_wr_demux.vhd
-- ^^^^^^
--
-- DET 2/15/2011 Initial for EDk 13.2
-- ~~~~~~
-- -- Per CR593812
-- - Modifications to remove unused features to improve Code coverage.
-- Used "-- coverage off" and "-- coverage on" strings.
-- ^^^^^^
-- ~~~~~~
-- SK 12/16/12 -- v2.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI MASTER BURST to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_v4_0
-- 4. No Logic Updates
-- ^^^^^^
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_master_burst_wr_demux is
generic (
C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5;
C_MMAP_DWIDTH : Integer range 32 to 256 := 32;
C_STREAM_DWIDTH : Integer range 8 to 256 := 32
);
port (
-- AXI MMap Data Channel Input -------------------------------
wstrb_in : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0);
-- data input
-- AXI Master Stream -----------------------------------
demux_wstrb_out : Out std_logic_vector((C_MMAP_DWIDTH/8)-1 downto 0);
--De-Mux strb output
-- Command Calculator Interface --------------------------
debeat_saddr_lsb : In std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0)
-- The next command start address LSbs to use for the read data
-- mux (only used if Stream data width is less than the MMap Data
-- Width).
);
end entity axi_master_burst_wr_demux;
architecture implementation of axi_master_burst_wr_demux is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function Decalarations -------------------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_mux_sel_width
--
-- Function Description:
-- Calculates the number of needed bits for the Mux Select control
-- based on the number of input channels to the mux.
--
-- Note that the number of input mux channels are always a
-- power of 2.
--
-------------------------------------------------------------------
function func_mux_sel_width (num_channels : integer) return integer is
Variable var_sel_width : integer := 0;
begin
case num_channels is
when 2 =>
var_sel_width := 1;
when 4 =>
var_sel_width := 2;
when 8 =>
var_sel_width := 3;
-- coverage off
when 16 =>
var_sel_width := 4;
when 32 =>
var_sel_width := 5;
-- coverage on
when others =>
var_sel_width := 0;
end case;
Return (var_sel_width);
end function func_mux_sel_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_sel_ls_index
--
-- Function Description:
-- Calculates the LS index of the select field to rip from the
-- input select bus.
--
-- Note that the number of input mux channels are always a
-- power of 2.
--
-------------------------------------------------------------------
function func_sel_ls_index (stream_width : integer) return integer is
Variable var_sel_ls_index : integer := 0;
begin
case stream_width is
-- coverage off
when 16 =>
var_sel_ls_index := 1;
-- coverage on
when 32 =>
var_sel_ls_index := 2;
when 64 =>
var_sel_ls_index := 3;
when 128 =>
var_sel_ls_index := 4;
-- coverage off
when others =>
var_sel_ls_index := 0;
-- coverage on
end case;
Return (var_sel_ls_index);
end function func_sel_ls_index;
-- Constant Decalarations -------------------------------------------------
Constant STREAM_WSTB_WIDTH : integer := C_STREAM_DWIDTH/8;
Constant MMAP_WSTB_WIDTH : integer := C_MMAP_DWIDTH/8;
Constant NUM_MUX_CHANNELS : integer := MMAP_WSTB_WIDTH/STREAM_WSTB_WIDTH;
Constant MUX_SEL_WIDTH : integer := func_mux_sel_width(NUM_MUX_CHANNELS);
Constant MUX_SEL_LS_INDEX : integer := func_sel_ls_index(C_STREAM_DWIDTH);
-- Signal Declarations --------------------------------------------
signal sig_demux_wstrb_out : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0');
begin --(architecture implementation)
-- Assign the Output data port
demux_wstrb_out <= sig_demux_wstrb_out;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_STRM_EQ_MMAP
--
-- If Generate Description:
-- This IfGen implements the case where the Stream Data Width is
-- the same as the Memeory Map read Data width.
--
--
------------------------------------------------------------
GEN_STRM_EQ_MMAP : if (C_MMAP_DWIDTH = C_STREAM_DWIDTH) generate
begin
sig_demux_wstrb_out <= wstrb_in;
end generate GEN_STRM_EQ_MMAP;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_2XN
--
-- If Generate Description:
-- 2 channel demux case
--
--
------------------------------------------------------------
GEN_2XN : if (NUM_MUX_CHANNELS = 2) generate
-- local signals
signal sig_demux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_int : integer range 0 to 31 := 0;
signal lsig_demux_sel_int_local : integer range 0 to 31 := 0;
signal lsig_demux_wstrb_out : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0');
begin
-- Rip the Mux Select bits needed for the Mux case from the input select bus
sig_demux_sel_slice <= debeat_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX);
sig_demux_sel_unsgnd <= UNSIGNED(sig_demux_sel_slice); -- convert to unsigned
sig_demux_sel_int <= TO_INTEGER(sig_demux_sel_unsgnd); -- convert to integer for MTI compile issue
-- with locally static subtype error in each of the
-- Mux IfGens
lsig_demux_sel_int_local <= sig_demux_sel_int;
sig_demux_wstrb_out <= lsig_demux_wstrb_out;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_2XN_DEMUX
--
-- Process Description:
-- Implement the 2XN DeMux
--
-------------------------------------------------------------
DO_2XN_DEMUX : process (lsig_demux_sel_int_local,
wstrb_in)
begin
-- Set default value
lsig_demux_wstrb_out <= (others => '0');
case lsig_demux_sel_int_local is
when 1 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*2)-1 downto STREAM_WSTB_WIDTH*1) <= wstrb_in;
when others =>
lsig_demux_wstrb_out(STREAM_WSTB_WIDTH-1 downto 0) <= wstrb_in;
end case;
end process DO_2XN_DEMUX;
end generate GEN_2XN;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_4XN
--
-- If Generate Description:
-- 4 channel demux case
--
--
------------------------------------------------------------
GEN_4XN : if (NUM_MUX_CHANNELS = 4) generate
-- local signals
signal sig_demux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_int : integer range 0 to 31 := 0;
signal lsig_demux_sel_int_local : integer range 0 to 31 := 0;
signal lsig_demux_wstrb_out : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0');
begin
-- Rip the Mux Select bits needed for the Mux case from the input select bus
sig_demux_sel_slice <= debeat_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX);
sig_demux_sel_unsgnd <= UNSIGNED(sig_demux_sel_slice); -- convert to unsigned
sig_demux_sel_int <= TO_INTEGER(sig_demux_sel_unsgnd); -- convert to integer for MTI compile issue
-- with locally static subtype error in each of the
-- Mux IfGens
lsig_demux_sel_int_local <= sig_demux_sel_int;
sig_demux_wstrb_out <= lsig_demux_wstrb_out;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_4XN_DEMUX
--
-- Process Description:
-- Implement the 4XN DeMux
--
-------------------------------------------------------------
DO_4XN_DEMUX : process (lsig_demux_sel_int_local,
wstrb_in)
begin
-- Set default value
lsig_demux_wstrb_out <= (others => '0');
case lsig_demux_sel_int_local is
when 1 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*2)-1 downto STREAM_WSTB_WIDTH*1) <= wstrb_in;
when 2 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*3)-1 downto STREAM_WSTB_WIDTH*2) <= wstrb_in;
when 3 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*4)-1 downto STREAM_WSTB_WIDTH*3) <= wstrb_in;
when others =>
lsig_demux_wstrb_out(STREAM_WSTB_WIDTH-1 downto 0) <= wstrb_in;
end case;
end process DO_4XN_DEMUX;
end generate GEN_4XN;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_8XN
--
-- If Generate Description:
-- 8 channel demux case
--
--
------------------------------------------------------------
GEN_8XN : if (NUM_MUX_CHANNELS = 8) generate
-- local signals
signal sig_demux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_int : integer range 0 to 31 := 0;
signal lsig_demux_sel_int_local : integer range 0 to 31 := 0;
signal lsig_demux_wstrb_out : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0');
begin
-- Rip the Mux Select bits needed for the Mux case from the input select bus
sig_demux_sel_slice <= debeat_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX);
sig_demux_sel_unsgnd <= UNSIGNED(sig_demux_sel_slice); -- convert to unsigned
sig_demux_sel_int <= TO_INTEGER(sig_demux_sel_unsgnd); -- convert to integer for MTI compile issue
-- with locally static subtype error in each of the
-- Mux IfGens
lsig_demux_sel_int_local <= sig_demux_sel_int;
sig_demux_wstrb_out <= lsig_demux_wstrb_out;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_8XN_DEMUX
--
-- Process Description:
-- Implement the 8XN DeMux
--
-------------------------------------------------------------
DO_8XN_DEMUX : process (lsig_demux_sel_int_local,
wstrb_in)
begin
-- Set default value
lsig_demux_wstrb_out <= (others => '0');
case lsig_demux_sel_int_local is
when 1 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*2)-1 downto STREAM_WSTB_WIDTH*1) <= wstrb_in;
when 2 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*3)-1 downto STREAM_WSTB_WIDTH*2) <= wstrb_in;
when 3 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*4)-1 downto STREAM_WSTB_WIDTH*3) <= wstrb_in;
when 4 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*5)-1 downto STREAM_WSTB_WIDTH*4) <= wstrb_in;
when 5 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*6)-1 downto STREAM_WSTB_WIDTH*5) <= wstrb_in;
when 6 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*7)-1 downto STREAM_WSTB_WIDTH*6) <= wstrb_in;
when 7 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*8)-1 downto STREAM_WSTB_WIDTH*7) <= wstrb_in;
when others =>
lsig_demux_wstrb_out(STREAM_WSTB_WIDTH-1 downto 0) <= wstrb_in;
end case;
end process DO_8XN_DEMUX;
end generate GEN_8XN;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_16XN
--
-- If Generate Description:
-- 16 channel demux case
--
--
------------------------------------------------------------
GEN_16XN : if (NUM_MUX_CHANNELS = 16) generate
-- local signals
signal sig_demux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_int : integer range 0 to 31 := 0;
signal lsig_demux_sel_int_local : integer range 0 to 31 := 0;
signal lsig_demux_wstrb_out : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0');
begin
-- Rip the Mux Select bits needed for the Mux case from the input select bus
sig_demux_sel_slice <= debeat_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX);
sig_demux_sel_unsgnd <= UNSIGNED(sig_demux_sel_slice); -- convert to unsigned
sig_demux_sel_int <= TO_INTEGER(sig_demux_sel_unsgnd); -- convert to integer for MTI compile issue
-- with locally static subtype error in each of the
-- Mux IfGens
lsig_demux_sel_int_local <= sig_demux_sel_int;
sig_demux_wstrb_out <= lsig_demux_wstrb_out;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_16XN_DEMUX
--
-- Process Description:
-- Implement the 16XN DeMux
--
-------------------------------------------------------------
DO_16XN_DEMUX : process (lsig_demux_sel_int_local,
wstrb_in)
begin
-- Set default value
lsig_demux_wstrb_out <= (others => '0');
case lsig_demux_sel_int_local is
when 1 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*2)-1 downto STREAM_WSTB_WIDTH*1) <= wstrb_in;
when 2 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*3)-1 downto STREAM_WSTB_WIDTH*2) <= wstrb_in;
when 3 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*4)-1 downto STREAM_WSTB_WIDTH*3) <= wstrb_in;
when 4 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*5)-1 downto STREAM_WSTB_WIDTH*4) <= wstrb_in;
when 5 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*6)-1 downto STREAM_WSTB_WIDTH*5) <= wstrb_in;
when 6 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*7)-1 downto STREAM_WSTB_WIDTH*6) <= wstrb_in;
when 7 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*8)-1 downto STREAM_WSTB_WIDTH*7) <= wstrb_in;
when 8 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*9)-1 downto STREAM_WSTB_WIDTH*8) <= wstrb_in;
when 9 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*10)-1 downto STREAM_WSTB_WIDTH*9) <= wstrb_in;
when 10 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*11)-1 downto STREAM_WSTB_WIDTH*10) <= wstrb_in;
when 11 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*12)-1 downto STREAM_WSTB_WIDTH*11) <= wstrb_in;
when 12 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*13)-1 downto STREAM_WSTB_WIDTH*12) <= wstrb_in;
when 13 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*14)-1 downto STREAM_WSTB_WIDTH*13) <= wstrb_in;
when 14 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*15)-1 downto STREAM_WSTB_WIDTH*14) <= wstrb_in;
when 15 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*16)-1 downto STREAM_WSTB_WIDTH*15) <= wstrb_in;
when others =>
lsig_demux_wstrb_out(STREAM_WSTB_WIDTH-1 downto 0) <= wstrb_in;
end case;
end process DO_16XN_DEMUX;
end generate GEN_16XN;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_32XN
--
-- If Generate Description:
-- 32 channel demux case
--
--
------------------------------------------------------------
GEN_32XN : if (NUM_MUX_CHANNELS = 32) generate
-- local signals
signal sig_demux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_int : integer range 0 to 31 := 0;
signal lsig_demux_sel_int_local : integer range 0 to 31 := 0;
signal lsig_demux_wstrb_out : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0');
begin
-- Rip the Mux Select bits needed for the Mux case from the input select bus
sig_demux_sel_slice <= debeat_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX);
sig_demux_sel_unsgnd <= UNSIGNED(sig_demux_sel_slice); -- convert to unsigned
sig_demux_sel_int <= TO_INTEGER(sig_demux_sel_unsgnd); -- convert to integer for MTI compile issue
-- with locally static subtype error in each of the
-- Mux IfGens
lsig_demux_sel_int_local <= sig_demux_sel_int;
sig_demux_wstrb_out <= lsig_demux_wstrb_out;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_32XN_DEMUX
--
-- Process Description:
-- Implement the 32XN DeMux
--
-------------------------------------------------------------
DO_32XN_DEMUX : process (lsig_demux_sel_int_local,
wstrb_in)
begin
-- Set default value
lsig_demux_wstrb_out <= (others => '0');
case lsig_demux_sel_int_local is
when 1 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*2)-1 downto STREAM_WSTB_WIDTH*1) <= wstrb_in;
when 2 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*3)-1 downto STREAM_WSTB_WIDTH*2) <= wstrb_in;
when 3 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*4)-1 downto STREAM_WSTB_WIDTH*3) <= wstrb_in;
when 4 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*5)-1 downto STREAM_WSTB_WIDTH*4) <= wstrb_in;
when 5 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*6)-1 downto STREAM_WSTB_WIDTH*5) <= wstrb_in;
when 6 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*7)-1 downto STREAM_WSTB_WIDTH*6) <= wstrb_in;
when 7 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*8)-1 downto STREAM_WSTB_WIDTH*7) <= wstrb_in;
when 8 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*9)-1 downto STREAM_WSTB_WIDTH*8) <= wstrb_in;
when 9 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*10)-1 downto STREAM_WSTB_WIDTH*9) <= wstrb_in;
when 10 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*11)-1 downto STREAM_WSTB_WIDTH*10) <= wstrb_in;
when 11 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*12)-1 downto STREAM_WSTB_WIDTH*11) <= wstrb_in;
when 12 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*13)-1 downto STREAM_WSTB_WIDTH*12) <= wstrb_in;
when 13 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*14)-1 downto STREAM_WSTB_WIDTH*13) <= wstrb_in;
when 14 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*15)-1 downto STREAM_WSTB_WIDTH*14) <= wstrb_in;
when 15 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*16)-1 downto STREAM_WSTB_WIDTH*15) <= wstrb_in;
when 16 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*17)-1 downto STREAM_WSTB_WIDTH*16) <= wstrb_in;
when 17 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*18)-1 downto STREAM_WSTB_WIDTH*17) <= wstrb_in;
when 18 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*19)-1 downto STREAM_WSTB_WIDTH*18) <= wstrb_in;
when 19 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*20)-1 downto STREAM_WSTB_WIDTH*19) <= wstrb_in;
when 20 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*21)-1 downto STREAM_WSTB_WIDTH*20) <= wstrb_in;
when 21 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*22)-1 downto STREAM_WSTB_WIDTH*21) <= wstrb_in;
when 22 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*23)-1 downto STREAM_WSTB_WIDTH*22) <= wstrb_in;
when 23 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*24)-1 downto STREAM_WSTB_WIDTH*23) <= wstrb_in;
when 24 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*25)-1 downto STREAM_WSTB_WIDTH*24) <= wstrb_in;
when 25 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*26)-1 downto STREAM_WSTB_WIDTH*25) <= wstrb_in;
when 26 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*27)-1 downto STREAM_WSTB_WIDTH*26) <= wstrb_in;
when 27 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*28)-1 downto STREAM_WSTB_WIDTH*27) <= wstrb_in;
when 28 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*29)-1 downto STREAM_WSTB_WIDTH*28) <= wstrb_in;
when 29 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*30)-1 downto STREAM_WSTB_WIDTH*29) <= wstrb_in;
when 30 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*31)-1 downto STREAM_WSTB_WIDTH*30) <= wstrb_in;
when 31 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*32)-1 downto STREAM_WSTB_WIDTH*31) <= wstrb_in;
when others =>
lsig_demux_wstrb_out(STREAM_WSTB_WIDTH-1 downto 0) <= wstrb_in;
end case;
end process DO_32XN_DEMUX;
end generate GEN_32XN;
end implementation;
|
apache-2.0
|
mkotormus/G3_OrchestraConductorDemo
|
src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/microblaze_v9_3/7b6e2d75/hdl/vhdl/mmu_types_pkg.vhd
|
1
|
10388
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_block
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`protect data_block
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`protect end_protected
|
apache-2.0
|
mkotormus/G3_OrchestraConductorDemo
|
src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/fifo_generator_v12_0/924f3d25/hdl/ramfifo/dmem.vhd
|
5
|
12333
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 7392)
`protect data_block
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l/D96kdqL3fyOR9k7UC4j/7pjCm9AfhD+G1XEjQDu/0C1dC+gpzdYTHz1tnd4Dm595FdrP/rqR+c
3L0KC9kfYgF6nZuGQQ+gGKCjegK0oWGsc7R76LyyLMRj/+8W79k9pVbRl7Mg1HylC7uA2hNRfqQt
C/iMRignhGTRTOBg0AXBFFJxOwgRM+4cZy43fauZpGMMbucNLumLouL3WK/d0Aef4sLYiiH3FvXf
INlWJGTUXgX6OasTy4vHiXvxMQvUuBmPo8gsXCqviCzkVh0gPnzq
`protect end_protected
|
apache-2.0
|
mkotormus/G3_OrchestraConductorDemo
|
src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/axi_uartlite_v2_0/6e58ba99/hdl/src/vhdl/axi_uartlite.vhd
|
1
|
17784
|
-------------------------------------------------------------------------------
-- axi_uartlite - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- -- ** (c) Copyright [2007] - [2011] Xilinx, Inc. All rights reserved.*
-- -- ** *
-- -- ** This file contains confidential and proprietary information *
-- -- ** of Xilinx, Inc. and is protected under U.S. and *
-- -- ** international copyright and other intellectual property *
-- -- ** laws. *
-- -- ** *
-- -- ** DISCLAIMER *
-- -- ** This disclaimer is not a license and does not grant any *
-- -- ** rights to the materials distributed herewith. Except as *
-- -- ** otherwise provided in a valid license issued to you by *
-- -- ** Xilinx, and to the maximum extent permitted by applicable *
-- -- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- -- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- -- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- -- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- -- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- -- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- -- ** including negligence, or under any other theory of *
-- -- ** liability) for any loss or damage of any kind or nature *
-- -- ** related to, arising under or in connection with these *
-- -- ** materials, including for any direct, or any indirect, *
-- -- ** special, incidental, or consequential loss or damage *
-- -- ** (including loss of data, profits, goodwill, or any type of *
-- -- ** loss or damage suffered as a result of any action brought *
-- -- ** by a third party) even if such damage or loss was *
-- -- ** reasonably foreseeable or Xilinx had been advised of the *
-- -- ** possibility of the same. *
-- -- ** *
-- -- ** CRITICAL APPLICATIONS *
-- -- ** Xilinx products are not designed or intended to be fail- *
-- -- ** safe, or for use in any application requiring fail-safe *
-- -- ** performance, such as life-support or safety devices or *
-- -- ** systems, Class III medical devices, nuclear facilities, *
-- -- ** applications related to the deployment of airbags, or any *
-- -- ** other applications that could lead to death, personal *
-- -- ** injury, or severe property or environmental damage *
-- -- ** (individually and collectively, "Critical *
-- -- ** Applications"). Customer assumes the sole risk and *
-- -- ** liability of any use of Xilinx products in Critical *
-- -- ** Applications, subject only to applicable laws and *
-- -- ** regulations governing limitations on product liability. *
-- -- ** *
-- -- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- -- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_uartlite.vhd
-- Version: v1.02.a
-- Description: AXI UART Lite Interface
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of axi_uartlite.
--
-- axi_uartlite.vhd
-- --axi_lite_ipif.vhd
-- --uartlite_core.vhd
-- --uartlite_tx.vhd
-- --uartlite_rx.vhd
-- --baudrate.vhd
-------------------------------------------------------------------------------
-- Author: USM
--
-- USM 07/22/09
-- ^^^^^^
-- - Initial release of v1.00.a
-- ~~~~~~
-- 20/09/20 SK
-- - 1. Updated the version as AXI Lite IPIF version is updated.
-- - 2. constant C_DPHASE_TIMEOUT value changed from 4 to 0
-- ^^^^^^
-- ~~~~~~
-- 01/02/10 NLR
-- - 1. Updated the version of axi_uartlite as uartlite_core.vhd changed
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library proc_common_v4_0;
-- SLV64_ARRAY_TYPE refered from ipif_pkg
use proc_common_v4_0.ipif_pkg.SLV64_ARRAY_TYPE;
-- INTEGER_ARRAY_TYPE refered from ipif_pkg
use proc_common_v4_0.ipif_pkg.INTEGER_ARRAY_TYPE;
-- calc_num_ce comoponent refered from ipif_pkg
use proc_common_v4_0.ipif_pkg.calc_num_ce;
library axi_lite_ipif_v2_0;
-- axi_lite_ipif refered from axi_lite_ipif_v2_0
use axi_lite_ipif_v2_0.axi_lite_ipif;
library axi_uartlite_v2_0;
-- uartlite_core refered from axi_uartlite_v2_0
use axi_uartlite_v2_0.uartlite_core;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics :
-------------------------------------------------------------------------------
-- System generics
-- C_FAMILY -- Xilinx FPGA Family
-- C_S_AXI_ACLK_FREQ_HZ -- System clock frequency driving UART lite
-- peripheral in Hz
-- AXI generics
-- C_S_AXI_ADDR_WIDTH -- Width of AXI Address Bus (in bits)
-- C_S_AXI_DATA_WIDTH -- Width of the AXI Data Bus (in bits)
--
-- UART Lite generics
-- C_BAUDRATE -- Baud rate of UART Lite in bits per second
-- C_DATA_BITS -- The number of data bits in the serial frame
-- C_USE_PARITY -- Determines whether parity is used or not
-- C_ODD_PARITY -- If parity is used determines whether parity
-- is even or odd
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Ports :
-------------------------------------------------------------------------------
--System signals
-- s_axi_aclk -- AXI Clock
-- s_axi_aresetn -- AXI Reset
-- Interrupt -- UART Interrupt
--AXI signals
-- s_axi_awaddr -- AXI Write address
-- s_axi_awvalid -- Write address valid
-- s_axi_awready -- Write address ready
-- s_axi_wdata -- Write data
-- s_axi_wstrb -- Write strobes
-- s_axi_wvalid -- Write valid
-- s_axi_wready -- Write ready
-- s_axi_bresp -- Write response
-- s_axi_bvalid -- Write response valid
-- s_axi_bready -- Response ready
-- s_axi_araddr -- Read address
-- s_axi_arvalid -- Read address valid
-- s_axi_arready -- Read address ready
-- s_axi_rdata -- Read data
-- s_axi_rresp -- Read response
-- s_axi_rvalid -- Read valid
-- s_axi_rready -- Read ready
--UARTLite Interface Signals
-- rx -- Receive Data
-- tx -- Transmit Data
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity Section
-------------------------------------------------------------------------------
entity axi_uartlite is
generic
(
-- -- System Parameter
C_FAMILY : string := "virtex7";
C_S_AXI_ACLK_FREQ_HZ : integer := 100_000_000;
-- -- AXI Parameters
C_S_AXI_ADDR_WIDTH : integer := 4;
C_S_AXI_DATA_WIDTH : integer range 32 to 128 := 32;
-- -- UARTLite Parameters
C_BAUDRATE : integer := 9600;
C_DATA_BITS : integer range 5 to 8 := 8;
C_USE_PARITY : integer range 0 to 1 := 0;
C_ODD_PARITY : integer range 0 to 1 := 0
);
port
(
-- System signals
s_axi_aclk : in std_logic;
s_axi_aresetn : in std_logic;
interrupt : out std_logic;
-- AXI signals
s_axi_awaddr : in std_logic_vector
(3 downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector
(31 downto 0);
s_axi_wstrb : in std_logic_vector
(3 downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_araddr : in std_logic_vector
(3 downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rdata : out std_logic_vector
(31 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
-- UARTLite Interface Signals
rx : in std_logic;
tx : out std_logic
);
-------------------------------------------------------------------------------
-- Attributes
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Fan-Out attributes for XST
-------------------------------------------------------------------------------
ATTRIBUTE MAX_FANOUT : string;
ATTRIBUTE MAX_FANOUT of s_axi_aclk : signal is "10000";
ATTRIBUTE MAX_FANOUT of s_axi_aresetn : signal is "10000";
end entity axi_uartlite;
-------------------------------------------------------------------------------
-- Architecture Section
-------------------------------------------------------------------------------
architecture RTL of axi_uartlite is
-- Pragma Added to supress synth warnings
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
--------------------------------------------------------------------------
-- Constant declarations
--------------------------------------------------------------------------
constant ZEROES : std_logic_vector(31 downto 0)
:= X"00000000";
constant C_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
-- UARTLite registers Base Address
ZEROES & X"00000000",
ZEROES & (X"00000000" or X"0000000F")
);
constant C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 4
);
constant C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0)
:= X"0000000F";
constant C_USE_WSTRB : integer := 0;
constant C_DPHASE_TIMEOUT : integer := 0;
--------------------------------------------------------------------------
-- Signal declarations
--------------------------------------------------------------------------
signal bus2ip_clk : std_logic;
signal bus2ip_reset : std_logic;
signal bus2ip_resetn : std_logic;
signal ip2bus_data : std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0)
:= (others => '0');
signal ip2bus_error : std_logic := '0';
signal ip2bus_wrack : std_logic := '0';
signal ip2bus_rdack : std_logic := '0';
signal bus2ip_data : std_logic_vector
(C_S_AXI_DATA_WIDTH - 1 downto 0);
signal bus2ip_cs : std_logic_vector
(((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1 downto 0);
signal bus2ip_rdce : std_logic_vector
(calc_num_ce(C_ARD_NUM_CE_ARRAY)-1 downto 0);
signal bus2ip_wrce : std_logic_vector
(calc_num_ce(C_ARD_NUM_CE_ARRAY)-1 downto 0);
begin -- architecture IMP
--------------------------------------------------------------------------
-- RESET signal assignment - IPIC RESET is active low
--------------------------------------------------------------------------
bus2ip_reset <= not bus2ip_resetn;
--------------------------------------------------------------------------
-- ip2bus_data assignment - as core is using maximum upto 8 bits
--------------------------------------------------------------------------
ip2bus_data((C_S_AXI_DATA_WIDTH-1) downto 8) <= (others => '0');
--------------------------------------------------------------------------
-- Instansiating the UART core
--------------------------------------------------------------------------
UARTLITE_CORE_I : entity axi_uartlite_v2_0.uartlite_core
generic map
(
C_FAMILY => C_FAMILY,
C_S_AXI_ACLK_FREQ_HZ => C_S_AXI_ACLK_FREQ_HZ,
C_BAUDRATE => C_BAUDRATE,
C_DATA_BITS => C_DATA_BITS,
C_USE_PARITY => C_USE_PARITY,
C_ODD_PARITY => C_ODD_PARITY
)
port map
(
Clk => bus2ip_clk,
Reset => bus2ip_reset,
bus2ip_data => bus2ip_data(7 downto 0),
bus2ip_rdce => bus2ip_rdce(3 downto 0),
bus2ip_wrce => bus2ip_wrce(3 downto 0),
bus2ip_cs => bus2ip_cs(0),
ip2bus_rdack => ip2bus_rdack,
ip2bus_wrack => ip2bus_wrack,
ip2bus_error => ip2bus_error,
SIn_DBus => ip2bus_data(7 downto 0),
RX => rx,
TX => tx,
Interrupt => Interrupt
);
--------------------------------------------------------------------------
-- Instantiate AXI lite IPIF
--------------------------------------------------------------------------
AXI_LITE_IPIF_I : entity axi_lite_ipif_v2_0.axi_lite_ipif
generic map
(
C_FAMILY => C_FAMILY,
C_S_AXI_ADDR_WIDTH => 4,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => C_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY
)
port map
(
S_AXI_ACLK => s_axi_aclk,
S_AXI_ARESETN => s_axi_aresetn,
S_AXI_AWADDR => s_axi_awaddr,
S_AXI_AWVALID => s_axi_awvalid,
S_AXI_AWREADY => s_axi_awready,
S_AXI_WDATA => s_axi_wdata,
S_AXI_WSTRB => s_axi_wstrb,
S_AXI_WVALID => s_axi_wvalid,
S_AXI_WREADY => s_axi_wready,
S_AXI_BRESP => s_axi_bresp,
S_AXI_BVALID => s_axi_bvalid,
S_AXI_BREADY => s_axi_bready,
S_AXI_ARADDR => s_axi_araddr,
S_AXI_ARVALID => s_axi_arvalid,
S_AXI_ARREADY => s_axi_arready,
S_AXI_RDATA => s_axi_rdata,
S_AXI_RRESP => s_axi_rresp,
S_AXI_RVALID => s_axi_rvalid,
S_AXI_RREADY => s_axi_rready,
-- IP Interconnect (IPIC) port signals
Bus2IP_Clk => bus2ip_clk,
Bus2IP_Resetn => bus2ip_resetn,
IP2Bus_Data => ip2bus_data,
IP2Bus_WrAck => ip2bus_wrack,
IP2Bus_RdAck => ip2bus_rdack,
IP2Bus_Error => ip2bus_error,
Bus2IP_Addr => open,
Bus2IP_Data => bus2ip_data,
Bus2IP_RNW => open,
Bus2IP_BE => open,
Bus2IP_CS => bus2ip_cs,
Bus2IP_RdCE => bus2ip_rdce,
Bus2IP_WrCE => bus2ip_wrce
);
end architecture RTL;
|
apache-2.0
|
mkotormus/G3_OrchestraConductorDemo
|
src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/proc_common_v4_0/bb615326/hdl/src/vhdl/or_gate.vhd
|
15
|
9199
|
-------------------------------------------------------------------------------
-- $Id: or_gate.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- or_gate.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: or_gate.vhd
-- Version: v1.00a
-- Description: OR gate implementation
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- or_gate.vhd
--
-------------------------------------------------------------------------------
-- Author: B.L. Tise
-- History:
-- BLT 2001-05-23 First Version
-- ^^^^^^
-- First version of OPB Bus.
-- ~~~~~~
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library proc_common_v4_0;
use proc_common_v4_0.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_OR_WIDTH -- Which Xilinx FPGA family to target when
-- syntesizing, affect the RLOC string values
-- C_BUS_WIDTH -- Which Y position the RLOC should start from
--
-- Definition of Ports:
-- A -- Input. Input buses are concatenated together to
-- form input A. Example: to OR buses R, S, and T,
-- assign A <= R & S & T;
-- Y -- Output. Same width as input buses.
--
-------------------------------------------------------------------------------
entity or_gate is
generic (
C_OR_WIDTH : natural range 1 to 32 := 17;
C_BUS_WIDTH : natural range 1 to 64 := 1;
C_USE_LUT_OR : boolean := TRUE
);
port (
A : in std_logic_vector(0 to C_OR_WIDTH*C_BUS_WIDTH-1);
Y : out std_logic_vector(0 to C_BUS_WIDTH-1)
);
end entity or_gate;
architecture imp of or_gate is
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
component or_muxcy
generic (
C_NUM_BITS : integer := 8
);
port (
In_bus : in std_logic_vector(0 to C_NUM_BITS-1);
Or_out : out std_logic
);
end component or_muxcy;
signal test : std_logic_vector(0 to C_BUS_WIDTH-1);
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin
USE_LUT_OR_GEN: if C_USE_LUT_OR generate
OR_PROCESS: process( A ) is
variable yi : std_logic_vector(0 to (C_OR_WIDTH));
begin
for j in 0 to C_BUS_WIDTH-1 loop
yi(0) := '0';
for i in 0 to C_OR_WIDTH-1 loop
yi(i+1) := yi(i) or A(i*C_BUS_WIDTH+j);
end loop;
Y(j) <= yi(C_OR_WIDTH);
end loop;
end process OR_PROCESS;
end generate USE_LUT_OR_GEN;
USE_MUXCY_OR_GEN: if not C_USE_LUT_OR generate
BUS_WIDTH_FOR_GEN: for i in 0 to C_BUS_WIDTH-1 generate
signal in_Bus : std_logic_vector(0 to C_OR_WIDTH-1);
begin
ORDER_INPUT_BUS_PROCESS: process( A ) is
begin
for k in 0 to C_OR_WIDTH-1 loop
in_Bus(k) <= A(k*C_BUS_WIDTH+i);
end loop;
end process ORDER_INPUT_BUS_PROCESS;
OR_BITS_I: or_muxcy
generic map (
C_NUM_BITS => C_OR_WIDTH
)
port map (
In_bus => in_Bus, --[in]
Or_out => Y(i) --[out]
);
end generate BUS_WIDTH_FOR_GEN;
end generate USE_MUXCY_OR_GEN;
end architecture imp;
|
apache-2.0
|
mkotormus/G3_OrchestraConductorDemo
|
src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/proc_common_v4_0/bb615326/hdl/src/vhdl/pf_adder.vhd
|
15
|
10246
|
-------------------------------------------------------------------------------
-- $Id: pf_adder.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- pf_adder - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pf_adder.vhd
--
-- Description: Parameterized adder/subtractor for Mauna Loa Packet FIFO
-- vacancy calculation. This design has a combinational
-- output. The carry out is not used by the PFIFO so it has
-- been removed.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pf_adder.vhd
--
-------------------------------------------------------------------------------
-- Author: D. Thorpe
-- Revision: $Revision: 1.1.4.1 $
-- Date: $Date: 2010/09/14 22:35:46 $
--
-- History:
-- DET 2001-08-30 First Version
-- - adapted from B Tise MicroBlaze timer counters
--
-- DET 2001-09-11
-- - Added the Rst input to the pf_adder_bit component
--
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity pf_adder is
generic (
C_REGISTERED_RESULT : Boolean := false;
C_COUNT_WIDTH : integer := 10
);
port (
Clk : in std_logic;
Rst : in std_logic;
--Carry_Out : out std_logic;
Ain : in std_logic_vector(0 to C_COUNT_WIDTH-1);
Bin : in std_logic_vector(0 to C_COUNT_WIDTH-1);
Add_sub_n : in std_logic;
result_out : out std_logic_vector(0 to C_COUNT_WIDTH-1)
);
end entity pf_adder;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of pf_adder is
component pf_adder_bit is
generic (
C_REGISTERED_RESULT : Boolean
);
port (
Clk : in std_logic;
Rst : In std_logic;
Ain : in std_logic;
Bin : in std_logic;
Add_sub_n : in std_logic;
Carry_In : in std_logic;
Clock_Enable : in std_logic;
Result : out std_logic;
Carry_Out : out std_logic);
end component pf_adder_bit;
-- component FDRE is
-- port (
-- Q : out std_logic;
-- C : in std_logic;
-- CE : in std_logic;
-- D : in std_logic;
-- R : in std_logic
-- );
-- end component FDRE;
--
constant CY_START : integer := 1;
signal alu_cy : std_logic_vector(0 to C_COUNT_WIDTH);
signal iresult_out : std_logic_vector(0 to C_COUNT_WIDTH-1);
signal count_clock_en : std_logic;
--signal carry_active_high : std_logic;
begin -- VHDL_RTL
-----------------------------------------------------------------------------
-- Generate the Counter bits
-----------------------------------------------------------------------------
alu_cy(C_COUNT_WIDTH) <= not(Add_sub_n); -- initial carry-in to adder LSB
count_clock_en <= '1';
I_ADDSUB_GEN : for i in 0 to C_COUNT_WIDTH-1 generate
begin
Counter_Bit_I : pf_adder_bit
Generic map(
C_REGISTERED_RESULT => C_REGISTERED_RESULT
)
port map (
Clk => Clk, -- [in]
Rst => Rst, -- [in]
Ain => Ain(i), -- [in]
Bin => Bin(i), -- [in]
Add_sub_n => Add_sub_n, -- [in]
Carry_In => alu_cy(i+CY_Start), -- [in]
Clock_Enable => count_clock_en, -- [in]
Result => iresult_out(i), -- [out]
Carry_Out => alu_cy(i+(1-CY_Start))); -- [out]
end generate I_ADDSUB_GEN;
-- carry_active_high <= alu_cy(0) xor not(Add_sub_n);
--
--
--
-- I_CARRY_OUT: FDRE
-- port map (
-- Q => Carry_Out, -- [out]
-- C => Clk, -- [in]
-- CE => count_clock_en, -- [in]
-- D => carry_active_high, -- [in]
-- R => Rst -- [in]
-- );
result_out <= iresult_out;
end architecture implementation;
|
apache-2.0
|
Stederr/ESCOM
|
Arquitectura de Computadoras/Practica04_OsciladorEnable/enable.vhd
|
1
|
206
|
library ieee;
use ieee.std_logic_1164.all;
entity enable is
port(
enable_in: in std_logic;
enable: out std_logic);
end;
architecture aenable of enable is
begin
enable <= not enable_in;
end aenable;
|
apache-2.0
|
Stederr/ESCOM
|
Arquitectura de Computadoras/Practica04_OsciladorEnable/toposc.vhd
|
1
|
1105
|
library ieee;
use ieee.std_logic_1164.all;
use packageoscint.all;
entity toposc is
port(
indiv0: in std_logic_vector(3 downto 0);
habilitar: in std_logic;
resetear: in std_logic;
outdiv0: inout std_logic);
attribute loc: string;
attribute loc of indiv0: signal is "p125, p124, p123, p122";
attribute loc of habilitar: signal is "p121";
attribute loc of resetear: signal is "p120";
attribute loc of outdiv0: signal is "p24";
end toposc;
--port(
--oscdis0: in std_logic;
--tmrrst0: in std_logic;
--oscout0: out std_logic);
--attribute loc: string;
--attribute loc of oscdis0: signal is "p125";
--attribute loc of tmrrst0: signal is "p124";
--attribute loc of oscout0: signal is "p5";
--end;
architecture atoposc of toposc is
signal oscout0, tmrout, enb: std_logic;
begin
U1: OSCINT port map(
osc_dis => enb,
tmr_rst => resetear,
tmr_out => outdiv0,
osc_out => oscout0); --tmr_out => tmrout
--U2: div port map(
-- clkdiv => tmrout,
-- indiv => indiv0,
-- outdiv => outdiv0);
U3: enable port map(
enable_in => habilitar,
enable => enb);
end atoposc;
|
apache-2.0
|
Stederr/ESCOM
|
Arquitectura de Computadoras/Practica02_Semisumador4Bits/paquete_sumadormedio.vhd
|
2
|
490
|
library ieee;
use ieee.std_logic_1164.all;
-- IPN - ESCOM
-- Arquitectura de Computadoras
-- ww ww ww - 3CM9
-- ww.com/arquitectura
package pack_sum_medio is
component eAnd
port(
entrada1_and: in std_logic;
entrada2_and: in std_logic;
salida_and: out std_logic);
end component;
component eXor
port(
entrada1_xor: in std_logic;
entrada2_xor: in std_logic;
salida_xor: out std_logic);
end component;
end pack_sum_medio;
|
apache-2.0
|
Stederr/ESCOM
|
Arquitectura de Computadoras/Practica02_SumadorRestador4Bits/paquete_sumador.vhd
|
1
|
847
|
library ieee;
use ieee.std_logic_1164.all;
-- IPN - ESCOM
-- Arquitectura de Computadoras
-- ww ww ww - 3CM9
-- ww.com/arquitectura
package pack_sum is
component eTopSumCompleto is
port(
acarreoI_tsc: in std_logic;
entrada1_tsc: in std_logic;
entrada2_tsc: in std_logic;
resultado_tsc: out std_logic;
acarreoO_tsc: out std_logic);
end component;
component eXnor
port(
entrada1_xnor: in std_logic;
entrada2_xnor: in std_logic;
salida_xnor: out std_logic);
end component;
component eAnd
port(
entrada1_and: in std_logic;
entrada2_and: in std_logic;
salida_and: out std_logic);
end component;
component eXor
port(
entrada1_xor: in std_logic;
entrada2_xor: in std_logic;
salida_xor: out std_logic);
end component;
end pack_sum;
|
apache-2.0
|
Stederr/ESCOM
|
Arquitectura de Computadoras/Practica05_ArquitecturaGenericaMultiAportes/xnor00.vhd
|
1
|
1399
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity xnor00 is
port(
clkxnr: in std_logic ;
codopxnr: in std_logic_vector ( 3 downto 0 );
portAxnr: in std_logic_vector ( 7 downto 0 );
portBxnr: in std_logic_vector ( 7 downto 0 );
inFlagxnr: in std_logic;
outxnr: out std_logic_vector ( 7 downto 0 );
outFlagxnr: out std_logic );
end;
architecture xnor0 of xnor00 is
begin
pxnor: process(codopxnr, portAxnr, portBxnr)
begin
if(codopxnr = "0110") then
outxnr <= portAxnr xnor portBxnr;
outFlagxnr <= '1';
else
outxnr <= (others => 'Z');
outFlagxnr <= 'Z';
end if;
end process pxnor;
-- pnand: process(clknd, codopnd, inFlagnd)
-- --variable auxnd: bit:='0';
-- begin
-- if (clknd = '1') then
----clknd'event and
-- if (codopnd = "0100") then
-- if (inFlagnd = '1') then
-- --if (auxnd = '0') then
-- --auxnd:= '1';
-- outnd <= portAnd nand portBnd;
-- outFlagnd <= '1';
-- --end if;
-- else
-- outFlagnd <= '0';
-- end if;
-- else
-- outnd <= (others => 'Z');
-- outFlagnd <= 'Z';
-- --auxnd:='0';
-- end if;
-- end if;
-- end process pnand;
end xnor0;
|
apache-2.0
|
Stederr/ESCOM
|
Arquitectura de Computadoras/Practica05_ArquitecturaGenericaMultiAportes/topadder00.vhd
|
1
|
1415
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity topadder00 is
port(
clkadd: in std_logic ;
codopadd: in std_logic_vector ( 3 downto 0 );
inFlagadd: in std_logic ;
portAaddin: in std_logic_vector ( 7 downto 0 );
portBaddin: in std_logic_vector ( 7 downto 0 );
SLaddin: in std_logic ;
LEDaddin: in std_logic ;
portAaddout: out std_logic_vector ( 7 downto 0 );
portBaddout: out std_logic_vector ( 7 downto 0 );
SLaddout: out std_logic ;
LEDaddout: out std_logic ;
outFlagadd: out std_logic;
Soaddin: in std_logic_vector ( 7 downto 0 );
Soaddout: out std_logic_vector ( 7 downto 0 ) );
end;
architecture topadder0 of topadder00 is
begin
padd: process(clkadd, inFlagadd)
begin
if (clkadd'event and clkadd = '1') then
if ((codopadd = "0101") or (codopadd = "0110")) then
portAaddout <= portAaddin;
portBaddout <= portBaddin;
SLaddout <= SLaddin;
if (inFlagadd = '1') then
Soaddout <= Soaddin;
LEDaddout <= LEDaddin;
outFlagadd <= '1';
else
outFlagadd <= '0';
end if;
else
Soaddout <= (others => 'Z');
outFlagadd <= 'Z';
LEDaddout <= 'Z';
end if;
end if;
end process padd;
end topadder0;
|
apache-2.0
|
dm-urievich/afc-smm
|
software/third-patry/dds_synthesizer/trunk/vhdl/sine_lut/sine_lut_12_x_16.vhd
|
2
|
46353
|
-- This file is automatically generated by a matlab script
--
-- Do not modify directly!
--
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_arith.all;
use IEEE.STD_LOGIC_signed.all;
package sine_lut_pkg is
constant PHASE_WIDTH : integer := 12;
constant AMPL_WIDTH : integer := 16;
type lut_type is array(0 to 2**(PHASE_WIDTH-2)-1) of std_logic_vector(AMPL_WIDTH-1 downto 0);
constant sine_lut : lut_type := (
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(151,AMPL_WIDTH),
conv_std_logic_vector(201,AMPL_WIDTH),
conv_std_logic_vector(251,AMPL_WIDTH),
conv_std_logic_vector(302,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(553,AMPL_WIDTH),
conv_std_logic_vector(603,AMPL_WIDTH),
conv_std_logic_vector(653,AMPL_WIDTH),
conv_std_logic_vector(704,AMPL_WIDTH),
conv_std_logic_vector(754,AMPL_WIDTH),
conv_std_logic_vector(804,AMPL_WIDTH),
conv_std_logic_vector(854,AMPL_WIDTH),
conv_std_logic_vector(905,AMPL_WIDTH),
conv_std_logic_vector(955,AMPL_WIDTH),
conv_std_logic_vector(1005,AMPL_WIDTH),
conv_std_logic_vector(1055,AMPL_WIDTH),
conv_std_logic_vector(1106,AMPL_WIDTH),
conv_std_logic_vector(1156,AMPL_WIDTH),
conv_std_logic_vector(1206,AMPL_WIDTH),
conv_std_logic_vector(1256,AMPL_WIDTH),
conv_std_logic_vector(1307,AMPL_WIDTH),
conv_std_logic_vector(1357,AMPL_WIDTH),
conv_std_logic_vector(1407,AMPL_WIDTH),
conv_std_logic_vector(1457,AMPL_WIDTH),
conv_std_logic_vector(1507,AMPL_WIDTH),
conv_std_logic_vector(1558,AMPL_WIDTH),
conv_std_logic_vector(1608,AMPL_WIDTH),
conv_std_logic_vector(1658,AMPL_WIDTH),
conv_std_logic_vector(1708,AMPL_WIDTH),
conv_std_logic_vector(1758,AMPL_WIDTH),
conv_std_logic_vector(1809,AMPL_WIDTH),
conv_std_logic_vector(1859,AMPL_WIDTH),
conv_std_logic_vector(1909,AMPL_WIDTH),
conv_std_logic_vector(1959,AMPL_WIDTH),
conv_std_logic_vector(2009,AMPL_WIDTH),
conv_std_logic_vector(2059,AMPL_WIDTH),
conv_std_logic_vector(2110,AMPL_WIDTH),
conv_std_logic_vector(2160,AMPL_WIDTH),
conv_std_logic_vector(2210,AMPL_WIDTH),
conv_std_logic_vector(2260,AMPL_WIDTH),
conv_std_logic_vector(2310,AMPL_WIDTH),
conv_std_logic_vector(2360,AMPL_WIDTH),
conv_std_logic_vector(2410,AMPL_WIDTH),
conv_std_logic_vector(2461,AMPL_WIDTH),
conv_std_logic_vector(2511,AMPL_WIDTH),
conv_std_logic_vector(2561,AMPL_WIDTH),
conv_std_logic_vector(2611,AMPL_WIDTH),
conv_std_logic_vector(2661,AMPL_WIDTH),
conv_std_logic_vector(2711,AMPL_WIDTH),
conv_std_logic_vector(2761,AMPL_WIDTH),
conv_std_logic_vector(2811,AMPL_WIDTH),
conv_std_logic_vector(2861,AMPL_WIDTH),
conv_std_logic_vector(2911,AMPL_WIDTH),
conv_std_logic_vector(2962,AMPL_WIDTH),
conv_std_logic_vector(3012,AMPL_WIDTH),
conv_std_logic_vector(3062,AMPL_WIDTH),
conv_std_logic_vector(3112,AMPL_WIDTH),
conv_std_logic_vector(3162,AMPL_WIDTH),
conv_std_logic_vector(3212,AMPL_WIDTH),
conv_std_logic_vector(3262,AMPL_WIDTH),
conv_std_logic_vector(3312,AMPL_WIDTH),
conv_std_logic_vector(3362,AMPL_WIDTH),
conv_std_logic_vector(3412,AMPL_WIDTH),
conv_std_logic_vector(3462,AMPL_WIDTH),
conv_std_logic_vector(3512,AMPL_WIDTH),
conv_std_logic_vector(3562,AMPL_WIDTH),
conv_std_logic_vector(3612,AMPL_WIDTH),
conv_std_logic_vector(3662,AMPL_WIDTH),
conv_std_logic_vector(3712,AMPL_WIDTH),
conv_std_logic_vector(3761,AMPL_WIDTH),
conv_std_logic_vector(3811,AMPL_WIDTH),
conv_std_logic_vector(3861,AMPL_WIDTH),
conv_std_logic_vector(3911,AMPL_WIDTH),
conv_std_logic_vector(3961,AMPL_WIDTH),
conv_std_logic_vector(4011,AMPL_WIDTH),
conv_std_logic_vector(4061,AMPL_WIDTH),
conv_std_logic_vector(4111,AMPL_WIDTH),
conv_std_logic_vector(4161,AMPL_WIDTH),
conv_std_logic_vector(4210,AMPL_WIDTH),
conv_std_logic_vector(4260,AMPL_WIDTH),
conv_std_logic_vector(4310,AMPL_WIDTH),
conv_std_logic_vector(4360,AMPL_WIDTH),
conv_std_logic_vector(4410,AMPL_WIDTH),
conv_std_logic_vector(4460,AMPL_WIDTH),
conv_std_logic_vector(4509,AMPL_WIDTH),
conv_std_logic_vector(4559,AMPL_WIDTH),
conv_std_logic_vector(4609,AMPL_WIDTH),
conv_std_logic_vector(4659,AMPL_WIDTH),
conv_std_logic_vector(4708,AMPL_WIDTH),
conv_std_logic_vector(4758,AMPL_WIDTH),
conv_std_logic_vector(4808,AMPL_WIDTH),
conv_std_logic_vector(4858,AMPL_WIDTH),
conv_std_logic_vector(4907,AMPL_WIDTH),
conv_std_logic_vector(4957,AMPL_WIDTH),
conv_std_logic_vector(5007,AMPL_WIDTH),
conv_std_logic_vector(5056,AMPL_WIDTH),
conv_std_logic_vector(5106,AMPL_WIDTH),
conv_std_logic_vector(5156,AMPL_WIDTH),
conv_std_logic_vector(5205,AMPL_WIDTH),
conv_std_logic_vector(5255,AMPL_WIDTH),
conv_std_logic_vector(5305,AMPL_WIDTH),
conv_std_logic_vector(5354,AMPL_WIDTH),
conv_std_logic_vector(5404,AMPL_WIDTH),
conv_std_logic_vector(5453,AMPL_WIDTH),
conv_std_logic_vector(5503,AMPL_WIDTH),
conv_std_logic_vector(5552,AMPL_WIDTH),
conv_std_logic_vector(5602,AMPL_WIDTH),
conv_std_logic_vector(5651,AMPL_WIDTH),
conv_std_logic_vector(5701,AMPL_WIDTH),
conv_std_logic_vector(5750,AMPL_WIDTH),
conv_std_logic_vector(5800,AMPL_WIDTH),
conv_std_logic_vector(5849,AMPL_WIDTH),
conv_std_logic_vector(5899,AMPL_WIDTH),
conv_std_logic_vector(5948,AMPL_WIDTH),
conv_std_logic_vector(5998,AMPL_WIDTH),
conv_std_logic_vector(6047,AMPL_WIDTH),
conv_std_logic_vector(6096,AMPL_WIDTH),
conv_std_logic_vector(6146,AMPL_WIDTH),
conv_std_logic_vector(6195,AMPL_WIDTH),
conv_std_logic_vector(6245,AMPL_WIDTH),
conv_std_logic_vector(6294,AMPL_WIDTH),
conv_std_logic_vector(6343,AMPL_WIDTH),
conv_std_logic_vector(6393,AMPL_WIDTH),
conv_std_logic_vector(6442,AMPL_WIDTH),
conv_std_logic_vector(6491,AMPL_WIDTH),
conv_std_logic_vector(6540,AMPL_WIDTH),
conv_std_logic_vector(6590,AMPL_WIDTH),
conv_std_logic_vector(6639,AMPL_WIDTH),
conv_std_logic_vector(6688,AMPL_WIDTH),
conv_std_logic_vector(6737,AMPL_WIDTH),
conv_std_logic_vector(6786,AMPL_WIDTH),
conv_std_logic_vector(6836,AMPL_WIDTH),
conv_std_logic_vector(6885,AMPL_WIDTH),
conv_std_logic_vector(6934,AMPL_WIDTH),
conv_std_logic_vector(6983,AMPL_WIDTH),
conv_std_logic_vector(7032,AMPL_WIDTH),
conv_std_logic_vector(7081,AMPL_WIDTH),
conv_std_logic_vector(7130,AMPL_WIDTH),
conv_std_logic_vector(7179,AMPL_WIDTH),
conv_std_logic_vector(7228,AMPL_WIDTH),
conv_std_logic_vector(7277,AMPL_WIDTH),
conv_std_logic_vector(7326,AMPL_WIDTH),
conv_std_logic_vector(7375,AMPL_WIDTH),
conv_std_logic_vector(7424,AMPL_WIDTH),
conv_std_logic_vector(7473,AMPL_WIDTH),
conv_std_logic_vector(7522,AMPL_WIDTH),
conv_std_logic_vector(7571,AMPL_WIDTH),
conv_std_logic_vector(7620,AMPL_WIDTH),
conv_std_logic_vector(7669,AMPL_WIDTH),
conv_std_logic_vector(7718,AMPL_WIDTH),
conv_std_logic_vector(7767,AMPL_WIDTH),
conv_std_logic_vector(7815,AMPL_WIDTH),
conv_std_logic_vector(7864,AMPL_WIDTH),
conv_std_logic_vector(7913,AMPL_WIDTH),
conv_std_logic_vector(7962,AMPL_WIDTH),
conv_std_logic_vector(8010,AMPL_WIDTH),
conv_std_logic_vector(8059,AMPL_WIDTH),
conv_std_logic_vector(8108,AMPL_WIDTH),
conv_std_logic_vector(8157,AMPL_WIDTH),
conv_std_logic_vector(8205,AMPL_WIDTH),
conv_std_logic_vector(8254,AMPL_WIDTH),
conv_std_logic_vector(8303,AMPL_WIDTH),
conv_std_logic_vector(8351,AMPL_WIDTH),
conv_std_logic_vector(8400,AMPL_WIDTH),
conv_std_logic_vector(8448,AMPL_WIDTH),
conv_std_logic_vector(8497,AMPL_WIDTH),
conv_std_logic_vector(8545,AMPL_WIDTH),
conv_std_logic_vector(8594,AMPL_WIDTH),
conv_std_logic_vector(8642,AMPL_WIDTH),
conv_std_logic_vector(8691,AMPL_WIDTH),
conv_std_logic_vector(8739,AMPL_WIDTH),
conv_std_logic_vector(8788,AMPL_WIDTH),
conv_std_logic_vector(8836,AMPL_WIDTH),
conv_std_logic_vector(8885,AMPL_WIDTH),
conv_std_logic_vector(8933,AMPL_WIDTH),
conv_std_logic_vector(8981,AMPL_WIDTH),
conv_std_logic_vector(9030,AMPL_WIDTH),
conv_std_logic_vector(9078,AMPL_WIDTH),
conv_std_logic_vector(9126,AMPL_WIDTH),
conv_std_logic_vector(9175,AMPL_WIDTH),
conv_std_logic_vector(9223,AMPL_WIDTH),
conv_std_logic_vector(9271,AMPL_WIDTH),
conv_std_logic_vector(9319,AMPL_WIDTH),
conv_std_logic_vector(9367,AMPL_WIDTH),
conv_std_logic_vector(9416,AMPL_WIDTH),
conv_std_logic_vector(9464,AMPL_WIDTH),
conv_std_logic_vector(9512,AMPL_WIDTH),
conv_std_logic_vector(9560,AMPL_WIDTH),
conv_std_logic_vector(9608,AMPL_WIDTH),
conv_std_logic_vector(9656,AMPL_WIDTH),
conv_std_logic_vector(9704,AMPL_WIDTH),
conv_std_logic_vector(9752,AMPL_WIDTH),
conv_std_logic_vector(9800,AMPL_WIDTH),
conv_std_logic_vector(9848,AMPL_WIDTH),
conv_std_logic_vector(9896,AMPL_WIDTH),
conv_std_logic_vector(9944,AMPL_WIDTH),
conv_std_logic_vector(9992,AMPL_WIDTH),
conv_std_logic_vector(10039,AMPL_WIDTH),
conv_std_logic_vector(10087,AMPL_WIDTH),
conv_std_logic_vector(10135,AMPL_WIDTH),
conv_std_logic_vector(10183,AMPL_WIDTH),
conv_std_logic_vector(10231,AMPL_WIDTH),
conv_std_logic_vector(10278,AMPL_WIDTH),
conv_std_logic_vector(10326,AMPL_WIDTH),
conv_std_logic_vector(10374,AMPL_WIDTH),
conv_std_logic_vector(10421,AMPL_WIDTH),
conv_std_logic_vector(10469,AMPL_WIDTH),
conv_std_logic_vector(10517,AMPL_WIDTH),
conv_std_logic_vector(10564,AMPL_WIDTH),
conv_std_logic_vector(10612,AMPL_WIDTH),
conv_std_logic_vector(10659,AMPL_WIDTH),
conv_std_logic_vector(10707,AMPL_WIDTH),
conv_std_logic_vector(10754,AMPL_WIDTH),
conv_std_logic_vector(10802,AMPL_WIDTH),
conv_std_logic_vector(10849,AMPL_WIDTH),
conv_std_logic_vector(10897,AMPL_WIDTH),
conv_std_logic_vector(10944,AMPL_WIDTH),
conv_std_logic_vector(10992,AMPL_WIDTH),
conv_std_logic_vector(11039,AMPL_WIDTH),
conv_std_logic_vector(11086,AMPL_WIDTH),
conv_std_logic_vector(11133,AMPL_WIDTH),
conv_std_logic_vector(11181,AMPL_WIDTH),
conv_std_logic_vector(11228,AMPL_WIDTH),
conv_std_logic_vector(11275,AMPL_WIDTH),
conv_std_logic_vector(11322,AMPL_WIDTH),
conv_std_logic_vector(11370,AMPL_WIDTH),
conv_std_logic_vector(11417,AMPL_WIDTH),
conv_std_logic_vector(11464,AMPL_WIDTH),
conv_std_logic_vector(11511,AMPL_WIDTH),
conv_std_logic_vector(11558,AMPL_WIDTH),
conv_std_logic_vector(11605,AMPL_WIDTH),
conv_std_logic_vector(11652,AMPL_WIDTH),
conv_std_logic_vector(11699,AMPL_WIDTH),
conv_std_logic_vector(11746,AMPL_WIDTH),
conv_std_logic_vector(11793,AMPL_WIDTH),
conv_std_logic_vector(11840,AMPL_WIDTH),
conv_std_logic_vector(11886,AMPL_WIDTH),
conv_std_logic_vector(11933,AMPL_WIDTH),
conv_std_logic_vector(11980,AMPL_WIDTH),
conv_std_logic_vector(12027,AMPL_WIDTH),
conv_std_logic_vector(12074,AMPL_WIDTH),
conv_std_logic_vector(12120,AMPL_WIDTH),
conv_std_logic_vector(12167,AMPL_WIDTH),
conv_std_logic_vector(12214,AMPL_WIDTH),
conv_std_logic_vector(12260,AMPL_WIDTH),
conv_std_logic_vector(12307,AMPL_WIDTH),
conv_std_logic_vector(12353,AMPL_WIDTH),
conv_std_logic_vector(12400,AMPL_WIDTH),
conv_std_logic_vector(12446,AMPL_WIDTH),
conv_std_logic_vector(12493,AMPL_WIDTH),
conv_std_logic_vector(12539,AMPL_WIDTH),
conv_std_logic_vector(12586,AMPL_WIDTH),
conv_std_logic_vector(12632,AMPL_WIDTH),
conv_std_logic_vector(12679,AMPL_WIDTH),
conv_std_logic_vector(12725,AMPL_WIDTH),
conv_std_logic_vector(12771,AMPL_WIDTH),
conv_std_logic_vector(12817,AMPL_WIDTH),
conv_std_logic_vector(12864,AMPL_WIDTH),
conv_std_logic_vector(12910,AMPL_WIDTH),
conv_std_logic_vector(12956,AMPL_WIDTH),
conv_std_logic_vector(13002,AMPL_WIDTH),
conv_std_logic_vector(13048,AMPL_WIDTH),
conv_std_logic_vector(13094,AMPL_WIDTH),
conv_std_logic_vector(13141,AMPL_WIDTH),
conv_std_logic_vector(13187,AMPL_WIDTH),
conv_std_logic_vector(13233,AMPL_WIDTH),
conv_std_logic_vector(13279,AMPL_WIDTH),
conv_std_logic_vector(13324,AMPL_WIDTH),
conv_std_logic_vector(13370,AMPL_WIDTH),
conv_std_logic_vector(13416,AMPL_WIDTH),
conv_std_logic_vector(13462,AMPL_WIDTH),
conv_std_logic_vector(13508,AMPL_WIDTH),
conv_std_logic_vector(13554,AMPL_WIDTH),
conv_std_logic_vector(13599,AMPL_WIDTH),
conv_std_logic_vector(13645,AMPL_WIDTH),
conv_std_logic_vector(13691,AMPL_WIDTH),
conv_std_logic_vector(13736,AMPL_WIDTH),
conv_std_logic_vector(13782,AMPL_WIDTH),
conv_std_logic_vector(13828,AMPL_WIDTH),
conv_std_logic_vector(13873,AMPL_WIDTH),
conv_std_logic_vector(13919,AMPL_WIDTH),
conv_std_logic_vector(13964,AMPL_WIDTH),
conv_std_logic_vector(14010,AMPL_WIDTH),
conv_std_logic_vector(14055,AMPL_WIDTH),
conv_std_logic_vector(14101,AMPL_WIDTH),
conv_std_logic_vector(14146,AMPL_WIDTH),
conv_std_logic_vector(14191,AMPL_WIDTH),
conv_std_logic_vector(14236,AMPL_WIDTH),
conv_std_logic_vector(14282,AMPL_WIDTH),
conv_std_logic_vector(14327,AMPL_WIDTH),
conv_std_logic_vector(14372,AMPL_WIDTH),
conv_std_logic_vector(14417,AMPL_WIDTH),
conv_std_logic_vector(14462,AMPL_WIDTH),
conv_std_logic_vector(14507,AMPL_WIDTH),
conv_std_logic_vector(14553,AMPL_WIDTH),
conv_std_logic_vector(14598,AMPL_WIDTH),
conv_std_logic_vector(14643,AMPL_WIDTH),
conv_std_logic_vector(14688,AMPL_WIDTH),
conv_std_logic_vector(14732,AMPL_WIDTH),
conv_std_logic_vector(14777,AMPL_WIDTH),
conv_std_logic_vector(14822,AMPL_WIDTH),
conv_std_logic_vector(14867,AMPL_WIDTH),
conv_std_logic_vector(14912,AMPL_WIDTH),
conv_std_logic_vector(14956,AMPL_WIDTH),
conv_std_logic_vector(15001,AMPL_WIDTH),
conv_std_logic_vector(15046,AMPL_WIDTH),
conv_std_logic_vector(15090,AMPL_WIDTH),
conv_std_logic_vector(15135,AMPL_WIDTH),
conv_std_logic_vector(15180,AMPL_WIDTH),
conv_std_logic_vector(15224,AMPL_WIDTH),
conv_std_logic_vector(15269,AMPL_WIDTH),
conv_std_logic_vector(15313,AMPL_WIDTH),
conv_std_logic_vector(15358,AMPL_WIDTH),
conv_std_logic_vector(15402,AMPL_WIDTH),
conv_std_logic_vector(15446,AMPL_WIDTH),
conv_std_logic_vector(15491,AMPL_WIDTH),
conv_std_logic_vector(15535,AMPL_WIDTH),
conv_std_logic_vector(15579,AMPL_WIDTH),
conv_std_logic_vector(15623,AMPL_WIDTH),
conv_std_logic_vector(15667,AMPL_WIDTH),
conv_std_logic_vector(15712,AMPL_WIDTH),
conv_std_logic_vector(15756,AMPL_WIDTH),
conv_std_logic_vector(15800,AMPL_WIDTH),
conv_std_logic_vector(15844,AMPL_WIDTH),
conv_std_logic_vector(15888,AMPL_WIDTH),
conv_std_logic_vector(15932,AMPL_WIDTH),
conv_std_logic_vector(15976,AMPL_WIDTH),
conv_std_logic_vector(16019,AMPL_WIDTH),
conv_std_logic_vector(16063,AMPL_WIDTH),
conv_std_logic_vector(16107,AMPL_WIDTH),
conv_std_logic_vector(16151,AMPL_WIDTH),
conv_std_logic_vector(16195,AMPL_WIDTH),
conv_std_logic_vector(16238,AMPL_WIDTH),
conv_std_logic_vector(16282,AMPL_WIDTH),
conv_std_logic_vector(16325,AMPL_WIDTH),
conv_std_logic_vector(16369,AMPL_WIDTH),
conv_std_logic_vector(16413,AMPL_WIDTH),
conv_std_logic_vector(16456,AMPL_WIDTH),
conv_std_logic_vector(16499,AMPL_WIDTH),
conv_std_logic_vector(16543,AMPL_WIDTH),
conv_std_logic_vector(16586,AMPL_WIDTH),
conv_std_logic_vector(16630,AMPL_WIDTH),
conv_std_logic_vector(16673,AMPL_WIDTH),
conv_std_logic_vector(16716,AMPL_WIDTH),
conv_std_logic_vector(16759,AMPL_WIDTH),
conv_std_logic_vector(16802,AMPL_WIDTH),
conv_std_logic_vector(16846,AMPL_WIDTH),
conv_std_logic_vector(16889,AMPL_WIDTH),
conv_std_logic_vector(16932,AMPL_WIDTH),
conv_std_logic_vector(16975,AMPL_WIDTH),
conv_std_logic_vector(17018,AMPL_WIDTH),
conv_std_logic_vector(17061,AMPL_WIDTH),
conv_std_logic_vector(17104,AMPL_WIDTH),
conv_std_logic_vector(17146,AMPL_WIDTH),
conv_std_logic_vector(17189,AMPL_WIDTH),
conv_std_logic_vector(17232,AMPL_WIDTH),
conv_std_logic_vector(17275,AMPL_WIDTH),
conv_std_logic_vector(17317,AMPL_WIDTH),
conv_std_logic_vector(17360,AMPL_WIDTH),
conv_std_logic_vector(17403,AMPL_WIDTH),
conv_std_logic_vector(17445,AMPL_WIDTH),
conv_std_logic_vector(17488,AMPL_WIDTH),
conv_std_logic_vector(17530,AMPL_WIDTH),
conv_std_logic_vector(17573,AMPL_WIDTH),
conv_std_logic_vector(17615,AMPL_WIDTH),
conv_std_logic_vector(17657,AMPL_WIDTH),
conv_std_logic_vector(17700,AMPL_WIDTH),
conv_std_logic_vector(17742,AMPL_WIDTH),
conv_std_logic_vector(17784,AMPL_WIDTH),
conv_std_logic_vector(17827,AMPL_WIDTH),
conv_std_logic_vector(17869,AMPL_WIDTH),
conv_std_logic_vector(17911,AMPL_WIDTH),
conv_std_logic_vector(17953,AMPL_WIDTH),
conv_std_logic_vector(17995,AMPL_WIDTH),
conv_std_logic_vector(18037,AMPL_WIDTH),
conv_std_logic_vector(18079,AMPL_WIDTH),
conv_std_logic_vector(18121,AMPL_WIDTH),
conv_std_logic_vector(18163,AMPL_WIDTH),
conv_std_logic_vector(18204,AMPL_WIDTH),
conv_std_logic_vector(18246,AMPL_WIDTH),
conv_std_logic_vector(18288,AMPL_WIDTH),
conv_std_logic_vector(18330,AMPL_WIDTH),
conv_std_logic_vector(18371,AMPL_WIDTH),
conv_std_logic_vector(18413,AMPL_WIDTH),
conv_std_logic_vector(18454,AMPL_WIDTH),
conv_std_logic_vector(18496,AMPL_WIDTH),
conv_std_logic_vector(18537,AMPL_WIDTH),
conv_std_logic_vector(18579,AMPL_WIDTH),
conv_std_logic_vector(18620,AMPL_WIDTH),
conv_std_logic_vector(18661,AMPL_WIDTH),
conv_std_logic_vector(18703,AMPL_WIDTH),
conv_std_logic_vector(18744,AMPL_WIDTH),
conv_std_logic_vector(18785,AMPL_WIDTH),
conv_std_logic_vector(18826,AMPL_WIDTH),
conv_std_logic_vector(18868,AMPL_WIDTH),
conv_std_logic_vector(18909,AMPL_WIDTH),
conv_std_logic_vector(18950,AMPL_WIDTH),
conv_std_logic_vector(18991,AMPL_WIDTH),
conv_std_logic_vector(19032,AMPL_WIDTH),
conv_std_logic_vector(19072,AMPL_WIDTH),
conv_std_logic_vector(19113,AMPL_WIDTH),
conv_std_logic_vector(19154,AMPL_WIDTH),
conv_std_logic_vector(19195,AMPL_WIDTH),
conv_std_logic_vector(19236,AMPL_WIDTH),
conv_std_logic_vector(19276,AMPL_WIDTH),
conv_std_logic_vector(19317,AMPL_WIDTH),
conv_std_logic_vector(19357,AMPL_WIDTH),
conv_std_logic_vector(19398,AMPL_WIDTH),
conv_std_logic_vector(19438,AMPL_WIDTH),
conv_std_logic_vector(19479,AMPL_WIDTH),
conv_std_logic_vector(19519,AMPL_WIDTH),
conv_std_logic_vector(19560,AMPL_WIDTH),
conv_std_logic_vector(19600,AMPL_WIDTH),
conv_std_logic_vector(19640,AMPL_WIDTH),
conv_std_logic_vector(19680,AMPL_WIDTH),
conv_std_logic_vector(19721,AMPL_WIDTH),
conv_std_logic_vector(19761,AMPL_WIDTH),
conv_std_logic_vector(19801,AMPL_WIDTH),
conv_std_logic_vector(19841,AMPL_WIDTH),
conv_std_logic_vector(19881,AMPL_WIDTH),
conv_std_logic_vector(19921,AMPL_WIDTH),
conv_std_logic_vector(19961,AMPL_WIDTH),
conv_std_logic_vector(20000,AMPL_WIDTH),
conv_std_logic_vector(20040,AMPL_WIDTH),
conv_std_logic_vector(20080,AMPL_WIDTH),
conv_std_logic_vector(20120,AMPL_WIDTH),
conv_std_logic_vector(20159,AMPL_WIDTH),
conv_std_logic_vector(20199,AMPL_WIDTH),
conv_std_logic_vector(20238,AMPL_WIDTH),
conv_std_logic_vector(20278,AMPL_WIDTH),
conv_std_logic_vector(20317,AMPL_WIDTH),
conv_std_logic_vector(20357,AMPL_WIDTH),
conv_std_logic_vector(20396,AMPL_WIDTH),
conv_std_logic_vector(20436,AMPL_WIDTH),
conv_std_logic_vector(20475,AMPL_WIDTH),
conv_std_logic_vector(20514,AMPL_WIDTH),
conv_std_logic_vector(20553,AMPL_WIDTH),
conv_std_logic_vector(20592,AMPL_WIDTH),
conv_std_logic_vector(20631,AMPL_WIDTH),
conv_std_logic_vector(20670,AMPL_WIDTH),
conv_std_logic_vector(20709,AMPL_WIDTH),
conv_std_logic_vector(20748,AMPL_WIDTH),
conv_std_logic_vector(20787,AMPL_WIDTH),
conv_std_logic_vector(20826,AMPL_WIDTH),
conv_std_logic_vector(20865,AMPL_WIDTH),
conv_std_logic_vector(20904,AMPL_WIDTH),
conv_std_logic_vector(20942,AMPL_WIDTH),
conv_std_logic_vector(20981,AMPL_WIDTH),
conv_std_logic_vector(21019,AMPL_WIDTH),
conv_std_logic_vector(21058,AMPL_WIDTH),
conv_std_logic_vector(21096,AMPL_WIDTH),
conv_std_logic_vector(21135,AMPL_WIDTH),
conv_std_logic_vector(21173,AMPL_WIDTH),
conv_std_logic_vector(21212,AMPL_WIDTH),
conv_std_logic_vector(21250,AMPL_WIDTH),
conv_std_logic_vector(21288,AMPL_WIDTH),
conv_std_logic_vector(21326,AMPL_WIDTH),
conv_std_logic_vector(21364,AMPL_WIDTH),
conv_std_logic_vector(21403,AMPL_WIDTH),
conv_std_logic_vector(21441,AMPL_WIDTH),
conv_std_logic_vector(21479,AMPL_WIDTH),
conv_std_logic_vector(21516,AMPL_WIDTH),
conv_std_logic_vector(21554,AMPL_WIDTH),
conv_std_logic_vector(21592,AMPL_WIDTH),
conv_std_logic_vector(21630,AMPL_WIDTH),
conv_std_logic_vector(21668,AMPL_WIDTH),
conv_std_logic_vector(21705,AMPL_WIDTH),
conv_std_logic_vector(21743,AMPL_WIDTH),
conv_std_logic_vector(21781,AMPL_WIDTH),
conv_std_logic_vector(21818,AMPL_WIDTH),
conv_std_logic_vector(21856,AMPL_WIDTH),
conv_std_logic_vector(21893,AMPL_WIDTH),
conv_std_logic_vector(21930,AMPL_WIDTH),
conv_std_logic_vector(21968,AMPL_WIDTH),
conv_std_logic_vector(22005,AMPL_WIDTH),
conv_std_logic_vector(22042,AMPL_WIDTH),
conv_std_logic_vector(22079,AMPL_WIDTH),
conv_std_logic_vector(22116,AMPL_WIDTH),
conv_std_logic_vector(22154,AMPL_WIDTH),
conv_std_logic_vector(22191,AMPL_WIDTH),
conv_std_logic_vector(22227,AMPL_WIDTH),
conv_std_logic_vector(22264,AMPL_WIDTH),
conv_std_logic_vector(22301,AMPL_WIDTH),
conv_std_logic_vector(22338,AMPL_WIDTH),
conv_std_logic_vector(22375,AMPL_WIDTH),
conv_std_logic_vector(22411,AMPL_WIDTH),
conv_std_logic_vector(22448,AMPL_WIDTH),
conv_std_logic_vector(22485,AMPL_WIDTH),
conv_std_logic_vector(22521,AMPL_WIDTH),
conv_std_logic_vector(22558,AMPL_WIDTH),
conv_std_logic_vector(22594,AMPL_WIDTH),
conv_std_logic_vector(22631,AMPL_WIDTH),
conv_std_logic_vector(22667,AMPL_WIDTH),
conv_std_logic_vector(22703,AMPL_WIDTH),
conv_std_logic_vector(22739,AMPL_WIDTH),
conv_std_logic_vector(22776,AMPL_WIDTH),
conv_std_logic_vector(22812,AMPL_WIDTH),
conv_std_logic_vector(22848,AMPL_WIDTH),
conv_std_logic_vector(22884,AMPL_WIDTH),
conv_std_logic_vector(22920,AMPL_WIDTH),
conv_std_logic_vector(22956,AMPL_WIDTH),
conv_std_logic_vector(22991,AMPL_WIDTH),
conv_std_logic_vector(23027,AMPL_WIDTH),
conv_std_logic_vector(23063,AMPL_WIDTH),
conv_std_logic_vector(23099,AMPL_WIDTH),
conv_std_logic_vector(23134,AMPL_WIDTH),
conv_std_logic_vector(23170,AMPL_WIDTH),
conv_std_logic_vector(23205,AMPL_WIDTH),
conv_std_logic_vector(23241,AMPL_WIDTH),
conv_std_logic_vector(23276,AMPL_WIDTH),
conv_std_logic_vector(23311,AMPL_WIDTH),
conv_std_logic_vector(23347,AMPL_WIDTH),
conv_std_logic_vector(23382,AMPL_WIDTH),
conv_std_logic_vector(23417,AMPL_WIDTH),
conv_std_logic_vector(23452,AMPL_WIDTH),
conv_std_logic_vector(23487,AMPL_WIDTH),
conv_std_logic_vector(23522,AMPL_WIDTH),
conv_std_logic_vector(23557,AMPL_WIDTH),
conv_std_logic_vector(23592,AMPL_WIDTH),
conv_std_logic_vector(23627,AMPL_WIDTH),
conv_std_logic_vector(23662,AMPL_WIDTH),
conv_std_logic_vector(23697,AMPL_WIDTH),
conv_std_logic_vector(23731,AMPL_WIDTH),
conv_std_logic_vector(23766,AMPL_WIDTH),
conv_std_logic_vector(23801,AMPL_WIDTH),
conv_std_logic_vector(23835,AMPL_WIDTH),
conv_std_logic_vector(23870,AMPL_WIDTH),
conv_std_logic_vector(23904,AMPL_WIDTH),
conv_std_logic_vector(23938,AMPL_WIDTH),
conv_std_logic_vector(23973,AMPL_WIDTH),
conv_std_logic_vector(24007,AMPL_WIDTH),
conv_std_logic_vector(24041,AMPL_WIDTH),
conv_std_logic_vector(24075,AMPL_WIDTH),
conv_std_logic_vector(24109,AMPL_WIDTH),
conv_std_logic_vector(24143,AMPL_WIDTH),
conv_std_logic_vector(24177,AMPL_WIDTH),
conv_std_logic_vector(24211,AMPL_WIDTH),
conv_std_logic_vector(24245,AMPL_WIDTH),
conv_std_logic_vector(24279,AMPL_WIDTH),
conv_std_logic_vector(24312,AMPL_WIDTH),
conv_std_logic_vector(24346,AMPL_WIDTH),
conv_std_logic_vector(24380,AMPL_WIDTH),
conv_std_logic_vector(24413,AMPL_WIDTH),
conv_std_logic_vector(24447,AMPL_WIDTH),
conv_std_logic_vector(24480,AMPL_WIDTH),
conv_std_logic_vector(24514,AMPL_WIDTH),
conv_std_logic_vector(24547,AMPL_WIDTH),
conv_std_logic_vector(24580,AMPL_WIDTH),
conv_std_logic_vector(24613,AMPL_WIDTH),
conv_std_logic_vector(24647,AMPL_WIDTH),
conv_std_logic_vector(24680,AMPL_WIDTH),
conv_std_logic_vector(24713,AMPL_WIDTH),
conv_std_logic_vector(24746,AMPL_WIDTH),
conv_std_logic_vector(24779,AMPL_WIDTH),
conv_std_logic_vector(24811,AMPL_WIDTH),
conv_std_logic_vector(24844,AMPL_WIDTH),
conv_std_logic_vector(24877,AMPL_WIDTH),
conv_std_logic_vector(24910,AMPL_WIDTH),
conv_std_logic_vector(24942,AMPL_WIDTH),
conv_std_logic_vector(24975,AMPL_WIDTH),
conv_std_logic_vector(25007,AMPL_WIDTH),
conv_std_logic_vector(25040,AMPL_WIDTH),
conv_std_logic_vector(25072,AMPL_WIDTH),
conv_std_logic_vector(25105,AMPL_WIDTH),
conv_std_logic_vector(25137,AMPL_WIDTH),
conv_std_logic_vector(25169,AMPL_WIDTH),
conv_std_logic_vector(25201,AMPL_WIDTH),
conv_std_logic_vector(25233,AMPL_WIDTH),
conv_std_logic_vector(25265,AMPL_WIDTH),
conv_std_logic_vector(25297,AMPL_WIDTH),
conv_std_logic_vector(25329,AMPL_WIDTH),
conv_std_logic_vector(25361,AMPL_WIDTH),
conv_std_logic_vector(25393,AMPL_WIDTH),
conv_std_logic_vector(25425,AMPL_WIDTH),
conv_std_logic_vector(25456,AMPL_WIDTH),
conv_std_logic_vector(25488,AMPL_WIDTH),
conv_std_logic_vector(25519,AMPL_WIDTH),
conv_std_logic_vector(25551,AMPL_WIDTH),
conv_std_logic_vector(25582,AMPL_WIDTH),
conv_std_logic_vector(25614,AMPL_WIDTH),
conv_std_logic_vector(25645,AMPL_WIDTH),
conv_std_logic_vector(25676,AMPL_WIDTH),
conv_std_logic_vector(25708,AMPL_WIDTH),
conv_std_logic_vector(25739,AMPL_WIDTH),
conv_std_logic_vector(25770,AMPL_WIDTH),
conv_std_logic_vector(25801,AMPL_WIDTH),
conv_std_logic_vector(25832,AMPL_WIDTH),
conv_std_logic_vector(25863,AMPL_WIDTH),
conv_std_logic_vector(25893,AMPL_WIDTH),
conv_std_logic_vector(25924,AMPL_WIDTH),
conv_std_logic_vector(25955,AMPL_WIDTH),
conv_std_logic_vector(25986,AMPL_WIDTH),
conv_std_logic_vector(26016,AMPL_WIDTH),
conv_std_logic_vector(26047,AMPL_WIDTH),
conv_std_logic_vector(26077,AMPL_WIDTH),
conv_std_logic_vector(26108,AMPL_WIDTH),
conv_std_logic_vector(26138,AMPL_WIDTH),
conv_std_logic_vector(26168,AMPL_WIDTH),
conv_std_logic_vector(26198,AMPL_WIDTH),
conv_std_logic_vector(26229,AMPL_WIDTH),
conv_std_logic_vector(26259,AMPL_WIDTH),
conv_std_logic_vector(26289,AMPL_WIDTH),
conv_std_logic_vector(26319,AMPL_WIDTH),
conv_std_logic_vector(26349,AMPL_WIDTH),
conv_std_logic_vector(26378,AMPL_WIDTH),
conv_std_logic_vector(26408,AMPL_WIDTH),
conv_std_logic_vector(26438,AMPL_WIDTH),
conv_std_logic_vector(26468,AMPL_WIDTH),
conv_std_logic_vector(26497,AMPL_WIDTH),
conv_std_logic_vector(26527,AMPL_WIDTH),
conv_std_logic_vector(26556,AMPL_WIDTH),
conv_std_logic_vector(26586,AMPL_WIDTH),
conv_std_logic_vector(26615,AMPL_WIDTH),
conv_std_logic_vector(26644,AMPL_WIDTH),
conv_std_logic_vector(26674,AMPL_WIDTH),
conv_std_logic_vector(26703,AMPL_WIDTH),
conv_std_logic_vector(26732,AMPL_WIDTH),
conv_std_logic_vector(26761,AMPL_WIDTH),
conv_std_logic_vector(26790,AMPL_WIDTH),
conv_std_logic_vector(26819,AMPL_WIDTH),
conv_std_logic_vector(26848,AMPL_WIDTH),
conv_std_logic_vector(26876,AMPL_WIDTH),
conv_std_logic_vector(26905,AMPL_WIDTH),
conv_std_logic_vector(26934,AMPL_WIDTH),
conv_std_logic_vector(26962,AMPL_WIDTH),
conv_std_logic_vector(26991,AMPL_WIDTH),
conv_std_logic_vector(27019,AMPL_WIDTH),
conv_std_logic_vector(27048,AMPL_WIDTH),
conv_std_logic_vector(27076,AMPL_WIDTH),
conv_std_logic_vector(27104,AMPL_WIDTH),
conv_std_logic_vector(27133,AMPL_WIDTH),
conv_std_logic_vector(27161,AMPL_WIDTH),
conv_std_logic_vector(27189,AMPL_WIDTH),
conv_std_logic_vector(27217,AMPL_WIDTH),
conv_std_logic_vector(27245,AMPL_WIDTH),
conv_std_logic_vector(27273,AMPL_WIDTH),
conv_std_logic_vector(27300,AMPL_WIDTH),
conv_std_logic_vector(27328,AMPL_WIDTH),
conv_std_logic_vector(27356,AMPL_WIDTH),
conv_std_logic_vector(27384,AMPL_WIDTH),
conv_std_logic_vector(27411,AMPL_WIDTH),
conv_std_logic_vector(27439,AMPL_WIDTH),
conv_std_logic_vector(27466,AMPL_WIDTH),
conv_std_logic_vector(27493,AMPL_WIDTH),
conv_std_logic_vector(27521,AMPL_WIDTH),
conv_std_logic_vector(27548,AMPL_WIDTH),
conv_std_logic_vector(27575,AMPL_WIDTH),
conv_std_logic_vector(27602,AMPL_WIDTH),
conv_std_logic_vector(27629,AMPL_WIDTH),
conv_std_logic_vector(27656,AMPL_WIDTH),
conv_std_logic_vector(27683,AMPL_WIDTH),
conv_std_logic_vector(27710,AMPL_WIDTH),
conv_std_logic_vector(27737,AMPL_WIDTH),
conv_std_logic_vector(27764,AMPL_WIDTH),
conv_std_logic_vector(27790,AMPL_WIDTH),
conv_std_logic_vector(27817,AMPL_WIDTH),
conv_std_logic_vector(27843,AMPL_WIDTH),
conv_std_logic_vector(27870,AMPL_WIDTH),
conv_std_logic_vector(27896,AMPL_WIDTH),
conv_std_logic_vector(27923,AMPL_WIDTH),
conv_std_logic_vector(27949,AMPL_WIDTH),
conv_std_logic_vector(27975,AMPL_WIDTH),
conv_std_logic_vector(28001,AMPL_WIDTH),
conv_std_logic_vector(28027,AMPL_WIDTH),
conv_std_logic_vector(28053,AMPL_WIDTH),
conv_std_logic_vector(28079,AMPL_WIDTH),
conv_std_logic_vector(28105,AMPL_WIDTH),
conv_std_logic_vector(28131,AMPL_WIDTH),
conv_std_logic_vector(28157,AMPL_WIDTH),
conv_std_logic_vector(28182,AMPL_WIDTH),
conv_std_logic_vector(28208,AMPL_WIDTH),
conv_std_logic_vector(28234,AMPL_WIDTH),
conv_std_logic_vector(28259,AMPL_WIDTH),
conv_std_logic_vector(28284,AMPL_WIDTH),
conv_std_logic_vector(28310,AMPL_WIDTH),
conv_std_logic_vector(28335,AMPL_WIDTH),
conv_std_logic_vector(28360,AMPL_WIDTH),
conv_std_logic_vector(28385,AMPL_WIDTH),
conv_std_logic_vector(28411,AMPL_WIDTH),
conv_std_logic_vector(28436,AMPL_WIDTH),
conv_std_logic_vector(28460,AMPL_WIDTH),
conv_std_logic_vector(28485,AMPL_WIDTH),
conv_std_logic_vector(28510,AMPL_WIDTH),
conv_std_logic_vector(28535,AMPL_WIDTH),
conv_std_logic_vector(28560,AMPL_WIDTH),
conv_std_logic_vector(28584,AMPL_WIDTH),
conv_std_logic_vector(28609,AMPL_WIDTH),
conv_std_logic_vector(28633,AMPL_WIDTH),
conv_std_logic_vector(28658,AMPL_WIDTH),
conv_std_logic_vector(28682,AMPL_WIDTH),
conv_std_logic_vector(28706,AMPL_WIDTH),
conv_std_logic_vector(28730,AMPL_WIDTH),
conv_std_logic_vector(28755,AMPL_WIDTH),
conv_std_logic_vector(28779,AMPL_WIDTH),
conv_std_logic_vector(28803,AMPL_WIDTH),
conv_std_logic_vector(28827,AMPL_WIDTH),
conv_std_logic_vector(28850,AMPL_WIDTH),
conv_std_logic_vector(28874,AMPL_WIDTH),
conv_std_logic_vector(28898,AMPL_WIDTH),
conv_std_logic_vector(28922,AMPL_WIDTH),
conv_std_logic_vector(28945,AMPL_WIDTH),
conv_std_logic_vector(28969,AMPL_WIDTH),
conv_std_logic_vector(28992,AMPL_WIDTH),
conv_std_logic_vector(29016,AMPL_WIDTH),
conv_std_logic_vector(29039,AMPL_WIDTH),
conv_std_logic_vector(29062,AMPL_WIDTH),
conv_std_logic_vector(29085,AMPL_WIDTH),
conv_std_logic_vector(29108,AMPL_WIDTH),
conv_std_logic_vector(29131,AMPL_WIDTH),
conv_std_logic_vector(29154,AMPL_WIDTH),
conv_std_logic_vector(29177,AMPL_WIDTH),
conv_std_logic_vector(29200,AMPL_WIDTH),
conv_std_logic_vector(29223,AMPL_WIDTH),
conv_std_logic_vector(29246,AMPL_WIDTH),
conv_std_logic_vector(29268,AMPL_WIDTH),
conv_std_logic_vector(29291,AMPL_WIDTH),
conv_std_logic_vector(29313,AMPL_WIDTH),
conv_std_logic_vector(29336,AMPL_WIDTH),
conv_std_logic_vector(29358,AMPL_WIDTH),
conv_std_logic_vector(29380,AMPL_WIDTH),
conv_std_logic_vector(29403,AMPL_WIDTH),
conv_std_logic_vector(29425,AMPL_WIDTH),
conv_std_logic_vector(29447,AMPL_WIDTH),
conv_std_logic_vector(29469,AMPL_WIDTH),
conv_std_logic_vector(29491,AMPL_WIDTH),
conv_std_logic_vector(29513,AMPL_WIDTH),
conv_std_logic_vector(29534,AMPL_WIDTH),
conv_std_logic_vector(29556,AMPL_WIDTH),
conv_std_logic_vector(29578,AMPL_WIDTH),
conv_std_logic_vector(29599,AMPL_WIDTH),
conv_std_logic_vector(29621,AMPL_WIDTH),
conv_std_logic_vector(29642,AMPL_WIDTH),
conv_std_logic_vector(29664,AMPL_WIDTH),
conv_std_logic_vector(29685,AMPL_WIDTH),
conv_std_logic_vector(29706,AMPL_WIDTH),
conv_std_logic_vector(29728,AMPL_WIDTH),
conv_std_logic_vector(29749,AMPL_WIDTH),
conv_std_logic_vector(29770,AMPL_WIDTH),
conv_std_logic_vector(29791,AMPL_WIDTH),
conv_std_logic_vector(29812,AMPL_WIDTH),
conv_std_logic_vector(29832,AMPL_WIDTH),
conv_std_logic_vector(29853,AMPL_WIDTH),
conv_std_logic_vector(29874,AMPL_WIDTH),
conv_std_logic_vector(29894,AMPL_WIDTH),
conv_std_logic_vector(29915,AMPL_WIDTH),
conv_std_logic_vector(29936,AMPL_WIDTH),
conv_std_logic_vector(29956,AMPL_WIDTH),
conv_std_logic_vector(29976,AMPL_WIDTH),
conv_std_logic_vector(29997,AMPL_WIDTH),
conv_std_logic_vector(30017,AMPL_WIDTH),
conv_std_logic_vector(30037,AMPL_WIDTH),
conv_std_logic_vector(30057,AMPL_WIDTH),
conv_std_logic_vector(30077,AMPL_WIDTH),
conv_std_logic_vector(30097,AMPL_WIDTH),
conv_std_logic_vector(30117,AMPL_WIDTH),
conv_std_logic_vector(30136,AMPL_WIDTH),
conv_std_logic_vector(30156,AMPL_WIDTH),
conv_std_logic_vector(30176,AMPL_WIDTH),
conv_std_logic_vector(30195,AMPL_WIDTH),
conv_std_logic_vector(30215,AMPL_WIDTH),
conv_std_logic_vector(30234,AMPL_WIDTH),
conv_std_logic_vector(30253,AMPL_WIDTH),
conv_std_logic_vector(30273,AMPL_WIDTH),
conv_std_logic_vector(30292,AMPL_WIDTH),
conv_std_logic_vector(30311,AMPL_WIDTH),
conv_std_logic_vector(30330,AMPL_WIDTH),
conv_std_logic_vector(30349,AMPL_WIDTH),
conv_std_logic_vector(30368,AMPL_WIDTH),
conv_std_logic_vector(30387,AMPL_WIDTH),
conv_std_logic_vector(30406,AMPL_WIDTH),
conv_std_logic_vector(30424,AMPL_WIDTH),
conv_std_logic_vector(30443,AMPL_WIDTH),
conv_std_logic_vector(30462,AMPL_WIDTH),
conv_std_logic_vector(30480,AMPL_WIDTH),
conv_std_logic_vector(30498,AMPL_WIDTH),
conv_std_logic_vector(30517,AMPL_WIDTH),
conv_std_logic_vector(30535,AMPL_WIDTH),
conv_std_logic_vector(30553,AMPL_WIDTH),
conv_std_logic_vector(30571,AMPL_WIDTH),
conv_std_logic_vector(30589,AMPL_WIDTH),
conv_std_logic_vector(30607,AMPL_WIDTH),
conv_std_logic_vector(30625,AMPL_WIDTH),
conv_std_logic_vector(30643,AMPL_WIDTH),
conv_std_logic_vector(30661,AMPL_WIDTH),
conv_std_logic_vector(30679,AMPL_WIDTH),
conv_std_logic_vector(30696,AMPL_WIDTH),
conv_std_logic_vector(30714,AMPL_WIDTH),
conv_std_logic_vector(30731,AMPL_WIDTH),
conv_std_logic_vector(30749,AMPL_WIDTH),
conv_std_logic_vector(30766,AMPL_WIDTH),
conv_std_logic_vector(30783,AMPL_WIDTH),
conv_std_logic_vector(30800,AMPL_WIDTH),
conv_std_logic_vector(30818,AMPL_WIDTH),
conv_std_logic_vector(30835,AMPL_WIDTH),
conv_std_logic_vector(30852,AMPL_WIDTH),
conv_std_logic_vector(30868,AMPL_WIDTH),
conv_std_logic_vector(30885,AMPL_WIDTH),
conv_std_logic_vector(30902,AMPL_WIDTH),
conv_std_logic_vector(30919,AMPL_WIDTH),
conv_std_logic_vector(30935,AMPL_WIDTH),
conv_std_logic_vector(30952,AMPL_WIDTH),
conv_std_logic_vector(30968,AMPL_WIDTH),
conv_std_logic_vector(30985,AMPL_WIDTH),
conv_std_logic_vector(31001,AMPL_WIDTH),
conv_std_logic_vector(31017,AMPL_WIDTH),
conv_std_logic_vector(31033,AMPL_WIDTH),
conv_std_logic_vector(31050,AMPL_WIDTH),
conv_std_logic_vector(31066,AMPL_WIDTH),
conv_std_logic_vector(31082,AMPL_WIDTH),
conv_std_logic_vector(31097,AMPL_WIDTH),
conv_std_logic_vector(31113,AMPL_WIDTH),
conv_std_logic_vector(31129,AMPL_WIDTH),
conv_std_logic_vector(31145,AMPL_WIDTH),
conv_std_logic_vector(31160,AMPL_WIDTH),
conv_std_logic_vector(31176,AMPL_WIDTH),
conv_std_logic_vector(31191,AMPL_WIDTH),
conv_std_logic_vector(31206,AMPL_WIDTH),
conv_std_logic_vector(31222,AMPL_WIDTH),
conv_std_logic_vector(31237,AMPL_WIDTH),
conv_std_logic_vector(31252,AMPL_WIDTH),
conv_std_logic_vector(31267,AMPL_WIDTH),
conv_std_logic_vector(31282,AMPL_WIDTH),
conv_std_logic_vector(31297,AMPL_WIDTH),
conv_std_logic_vector(31312,AMPL_WIDTH),
conv_std_logic_vector(31327,AMPL_WIDTH),
conv_std_logic_vector(31341,AMPL_WIDTH),
conv_std_logic_vector(31356,AMPL_WIDTH),
conv_std_logic_vector(31371,AMPL_WIDTH),
conv_std_logic_vector(31385,AMPL_WIDTH),
conv_std_logic_vector(31400,AMPL_WIDTH),
conv_std_logic_vector(31414,AMPL_WIDTH),
conv_std_logic_vector(31428,AMPL_WIDTH),
conv_std_logic_vector(31442,AMPL_WIDTH),
conv_std_logic_vector(31456,AMPL_WIDTH),
conv_std_logic_vector(31470,AMPL_WIDTH),
conv_std_logic_vector(31484,AMPL_WIDTH),
conv_std_logic_vector(31498,AMPL_WIDTH),
conv_std_logic_vector(31512,AMPL_WIDTH),
conv_std_logic_vector(31526,AMPL_WIDTH),
conv_std_logic_vector(31539,AMPL_WIDTH),
conv_std_logic_vector(31553,AMPL_WIDTH),
conv_std_logic_vector(31567,AMPL_WIDTH),
conv_std_logic_vector(31580,AMPL_WIDTH),
conv_std_logic_vector(31593,AMPL_WIDTH),
conv_std_logic_vector(31607,AMPL_WIDTH),
conv_std_logic_vector(31620,AMPL_WIDTH),
conv_std_logic_vector(31633,AMPL_WIDTH),
conv_std_logic_vector(31646,AMPL_WIDTH),
conv_std_logic_vector(31659,AMPL_WIDTH),
conv_std_logic_vector(31672,AMPL_WIDTH),
conv_std_logic_vector(31685,AMPL_WIDTH),
conv_std_logic_vector(31698,AMPL_WIDTH),
conv_std_logic_vector(31710,AMPL_WIDTH),
conv_std_logic_vector(31723,AMPL_WIDTH),
conv_std_logic_vector(31736,AMPL_WIDTH),
conv_std_logic_vector(31748,AMPL_WIDTH),
conv_std_logic_vector(31760,AMPL_WIDTH),
conv_std_logic_vector(31773,AMPL_WIDTH),
conv_std_logic_vector(31785,AMPL_WIDTH),
conv_std_logic_vector(31797,AMPL_WIDTH),
conv_std_logic_vector(31809,AMPL_WIDTH),
conv_std_logic_vector(31821,AMPL_WIDTH),
conv_std_logic_vector(31833,AMPL_WIDTH),
conv_std_logic_vector(31845,AMPL_WIDTH),
conv_std_logic_vector(31857,AMPL_WIDTH),
conv_std_logic_vector(31869,AMPL_WIDTH),
conv_std_logic_vector(31880,AMPL_WIDTH),
conv_std_logic_vector(31892,AMPL_WIDTH),
conv_std_logic_vector(31903,AMPL_WIDTH),
conv_std_logic_vector(31915,AMPL_WIDTH),
conv_std_logic_vector(31926,AMPL_WIDTH),
conv_std_logic_vector(31937,AMPL_WIDTH),
conv_std_logic_vector(31949,AMPL_WIDTH),
conv_std_logic_vector(31960,AMPL_WIDTH),
conv_std_logic_vector(31971,AMPL_WIDTH),
conv_std_logic_vector(31982,AMPL_WIDTH),
conv_std_logic_vector(31993,AMPL_WIDTH),
conv_std_logic_vector(32004,AMPL_WIDTH),
conv_std_logic_vector(32014,AMPL_WIDTH),
conv_std_logic_vector(32025,AMPL_WIDTH),
conv_std_logic_vector(32036,AMPL_WIDTH),
conv_std_logic_vector(32046,AMPL_WIDTH),
conv_std_logic_vector(32057,AMPL_WIDTH),
conv_std_logic_vector(32067,AMPL_WIDTH),
conv_std_logic_vector(32077,AMPL_WIDTH),
conv_std_logic_vector(32087,AMPL_WIDTH),
conv_std_logic_vector(32098,AMPL_WIDTH),
conv_std_logic_vector(32108,AMPL_WIDTH),
conv_std_logic_vector(32118,AMPL_WIDTH),
conv_std_logic_vector(32128,AMPL_WIDTH),
conv_std_logic_vector(32137,AMPL_WIDTH),
conv_std_logic_vector(32147,AMPL_WIDTH),
conv_std_logic_vector(32157,AMPL_WIDTH),
conv_std_logic_vector(32166,AMPL_WIDTH),
conv_std_logic_vector(32176,AMPL_WIDTH),
conv_std_logic_vector(32185,AMPL_WIDTH),
conv_std_logic_vector(32195,AMPL_WIDTH),
conv_std_logic_vector(32204,AMPL_WIDTH),
conv_std_logic_vector(32213,AMPL_WIDTH),
conv_std_logic_vector(32223,AMPL_WIDTH),
conv_std_logic_vector(32232,AMPL_WIDTH),
conv_std_logic_vector(32241,AMPL_WIDTH),
conv_std_logic_vector(32250,AMPL_WIDTH),
conv_std_logic_vector(32258,AMPL_WIDTH),
conv_std_logic_vector(32267,AMPL_WIDTH),
conv_std_logic_vector(32276,AMPL_WIDTH),
conv_std_logic_vector(32285,AMPL_WIDTH),
conv_std_logic_vector(32293,AMPL_WIDTH),
conv_std_logic_vector(32302,AMPL_WIDTH),
conv_std_logic_vector(32310,AMPL_WIDTH),
conv_std_logic_vector(32318,AMPL_WIDTH),
conv_std_logic_vector(32327,AMPL_WIDTH),
conv_std_logic_vector(32335,AMPL_WIDTH),
conv_std_logic_vector(32343,AMPL_WIDTH),
conv_std_logic_vector(32351,AMPL_WIDTH),
conv_std_logic_vector(32359,AMPL_WIDTH),
conv_std_logic_vector(32367,AMPL_WIDTH),
conv_std_logic_vector(32375,AMPL_WIDTH),
conv_std_logic_vector(32382,AMPL_WIDTH),
conv_std_logic_vector(32390,AMPL_WIDTH),
conv_std_logic_vector(32397,AMPL_WIDTH),
conv_std_logic_vector(32405,AMPL_WIDTH),
conv_std_logic_vector(32412,AMPL_WIDTH),
conv_std_logic_vector(32420,AMPL_WIDTH),
conv_std_logic_vector(32427,AMPL_WIDTH),
conv_std_logic_vector(32434,AMPL_WIDTH),
conv_std_logic_vector(32441,AMPL_WIDTH),
conv_std_logic_vector(32448,AMPL_WIDTH),
conv_std_logic_vector(32455,AMPL_WIDTH),
conv_std_logic_vector(32462,AMPL_WIDTH),
conv_std_logic_vector(32469,AMPL_WIDTH),
conv_std_logic_vector(32476,AMPL_WIDTH),
conv_std_logic_vector(32482,AMPL_WIDTH),
conv_std_logic_vector(32489,AMPL_WIDTH),
conv_std_logic_vector(32495,AMPL_WIDTH),
conv_std_logic_vector(32502,AMPL_WIDTH),
conv_std_logic_vector(32508,AMPL_WIDTH),
conv_std_logic_vector(32514,AMPL_WIDTH),
conv_std_logic_vector(32521,AMPL_WIDTH),
conv_std_logic_vector(32527,AMPL_WIDTH),
conv_std_logic_vector(32533,AMPL_WIDTH),
conv_std_logic_vector(32539,AMPL_WIDTH),
conv_std_logic_vector(32545,AMPL_WIDTH),
conv_std_logic_vector(32550,AMPL_WIDTH),
conv_std_logic_vector(32556,AMPL_WIDTH),
conv_std_logic_vector(32562,AMPL_WIDTH),
conv_std_logic_vector(32567,AMPL_WIDTH),
conv_std_logic_vector(32573,AMPL_WIDTH),
conv_std_logic_vector(32578,AMPL_WIDTH),
conv_std_logic_vector(32584,AMPL_WIDTH),
conv_std_logic_vector(32589,AMPL_WIDTH),
conv_std_logic_vector(32594,AMPL_WIDTH),
conv_std_logic_vector(32599,AMPL_WIDTH),
conv_std_logic_vector(32604,AMPL_WIDTH),
conv_std_logic_vector(32609,AMPL_WIDTH),
conv_std_logic_vector(32614,AMPL_WIDTH),
conv_std_logic_vector(32619,AMPL_WIDTH),
conv_std_logic_vector(32624,AMPL_WIDTH),
conv_std_logic_vector(32628,AMPL_WIDTH),
conv_std_logic_vector(32633,AMPL_WIDTH),
conv_std_logic_vector(32637,AMPL_WIDTH),
conv_std_logic_vector(32642,AMPL_WIDTH),
conv_std_logic_vector(32646,AMPL_WIDTH),
conv_std_logic_vector(32650,AMPL_WIDTH),
conv_std_logic_vector(32655,AMPL_WIDTH),
conv_std_logic_vector(32659,AMPL_WIDTH),
conv_std_logic_vector(32663,AMPL_WIDTH),
conv_std_logic_vector(32667,AMPL_WIDTH),
conv_std_logic_vector(32671,AMPL_WIDTH),
conv_std_logic_vector(32674,AMPL_WIDTH),
conv_std_logic_vector(32678,AMPL_WIDTH),
conv_std_logic_vector(32682,AMPL_WIDTH),
conv_std_logic_vector(32685,AMPL_WIDTH),
conv_std_logic_vector(32689,AMPL_WIDTH),
conv_std_logic_vector(32692,AMPL_WIDTH),
conv_std_logic_vector(32696,AMPL_WIDTH),
conv_std_logic_vector(32699,AMPL_WIDTH),
conv_std_logic_vector(32702,AMPL_WIDTH),
conv_std_logic_vector(32705,AMPL_WIDTH),
conv_std_logic_vector(32708,AMPL_WIDTH),
conv_std_logic_vector(32711,AMPL_WIDTH),
conv_std_logic_vector(32714,AMPL_WIDTH),
conv_std_logic_vector(32717,AMPL_WIDTH),
conv_std_logic_vector(32720,AMPL_WIDTH),
conv_std_logic_vector(32722,AMPL_WIDTH),
conv_std_logic_vector(32725,AMPL_WIDTH),
conv_std_logic_vector(32728,AMPL_WIDTH),
conv_std_logic_vector(32730,AMPL_WIDTH),
conv_std_logic_vector(32732,AMPL_WIDTH),
conv_std_logic_vector(32735,AMPL_WIDTH),
conv_std_logic_vector(32737,AMPL_WIDTH),
conv_std_logic_vector(32739,AMPL_WIDTH),
conv_std_logic_vector(32741,AMPL_WIDTH),
conv_std_logic_vector(32743,AMPL_WIDTH),
conv_std_logic_vector(32745,AMPL_WIDTH),
conv_std_logic_vector(32747,AMPL_WIDTH),
conv_std_logic_vector(32748,AMPL_WIDTH),
conv_std_logic_vector(32750,AMPL_WIDTH),
conv_std_logic_vector(32752,AMPL_WIDTH),
conv_std_logic_vector(32753,AMPL_WIDTH),
conv_std_logic_vector(32755,AMPL_WIDTH),
conv_std_logic_vector(32756,AMPL_WIDTH),
conv_std_logic_vector(32757,AMPL_WIDTH),
conv_std_logic_vector(32758,AMPL_WIDTH),
conv_std_logic_vector(32759,AMPL_WIDTH),
conv_std_logic_vector(32760,AMPL_WIDTH),
conv_std_logic_vector(32761,AMPL_WIDTH),
conv_std_logic_vector(32762,AMPL_WIDTH),
conv_std_logic_vector(32763,AMPL_WIDTH),
conv_std_logic_vector(32764,AMPL_WIDTH),
conv_std_logic_vector(32765,AMPL_WIDTH),
conv_std_logic_vector(32765,AMPL_WIDTH),
conv_std_logic_vector(32766,AMPL_WIDTH),
conv_std_logic_vector(32766,AMPL_WIDTH),
conv_std_logic_vector(32766,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH)
);
end sine_lut_pkg;
package body sine_lut_pkg is
end sine_lut_pkg;
|
apache-2.0
|
dm-urievich/afc-smm
|
software/LEDA.vhd
|
1
|
2131
|
--???21EDA??
--?????:A-C8V4
--www.21eda.com
--??LED???LED??????0??????1???
--????????21EDA????????
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.std_logic_unsigned.ALL;
ENTITY LEDA is
PORT(
clk:in STD_LOGIC; --System Clk
led1:out STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END LEDA ;
ARCHITECTURE light OF LEDA IS
SIGNAL clk1 :std_logic;
BEGIN
PROCESS( clk )
VARIABLE Count : integer range 0 to 65535;
BEGIN
IF( clk'EVENT AND clk='1' ) THEN
IF( Count > 50000 ) THEN
Count := 0;
clk1 <= '1';
ELSE
Count := Count + 1;
clk1 <= '0';
END IF;
END IF;
END PROCESS;
---------------------------------------------------------
P2:PROCESS(clk)
variable count1:INTEGER RANGE 0 TO 7;
BEGIN
IF clk'event AND clk='1'THEN
if (clk1 = '1') then
if count1<=4 then
if count1=4 then
count1:=0;
end if;
CASE count1 IS
WHEN 0=>led1<="0111";
WHEN 1=>led1<="1011";
WHEN 2=>led1<="1101";
WHEN 3=>led1<="1110";
WHEN OTHERS=>led1<="1111";
END CASE;
count1:=count1+1;
end if;
end if;
end if;
end process;
END light;
|
apache-2.0
|
xuefei1/ElectronicEngineControl
|
vhd/frequency_counter.vhd
|
3
|
1272
|
-- frequency_counter.vhd
-- This file was auto-generated as a prototype implementation of a module
-- created in component editor. It ties off all outputs to ground and
-- ignores all inputs. It needs to be edited to make it do something
-- useful.
--
-- This file will not be automatically regenerated. You should check it in
-- to your version control system if you want to keep it.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity frequency_counter is
generic (
AUTO_CLOCK_CLOCK_RATE : string := "-1"
);
port (
clock : in std_logic := '0'; -- clock.clk
data_out : out std_logic_vector(31 downto 0) := "00000000000000000000000000000000"; -- avalon_slave.readdata
freq_in : in std_logic := '0'; -- conduit_end.export
reset : in std_logic := '0' -- reset.reset_n
);
end entity frequency_counter;
architecture rtl of frequency_counter is
signal count : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
begin
process(freq_in)
begin
if(freq_in = '1') then
count <= std_logic_vector( unsigned(count) + 1 );
data_out <= count;
end if;
end process;
end architecture rtl; -- of frequency_counter
|
apache-2.0
|
xuefei1/ElectronicEngineControl
|
niosII_system/synthesis/submodules/solenoid_controller.vhd
|
2
|
2625
|
-- solenoid_controller.vhd
-- Author: Fred
-- Status: Tested and passed
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity solenoid_controller is
port (
clock : in std_logic := '0'; -- clock
status : out std_logic_vector(7 downto 0) := "00000000"; -- read
control : in std_logic_vector(7 downto 0) := "00000000"; -- write
chip_select : in std_logic := '0'; -- cs
write_enable : in std_logic := '0'; -- write enable
btn_shift_up_in : in std_logic := '0'; -- conduit_end.export
btn_shift_down_in : in std_logic := '0'; -- conduit_end.export
sol_shift_up_out : out std_logic := '0'; -- conduit_end.export
sol_shift_down_out : out std_logic := '0'; -- conduit_end.export
irq_btn_out : out std_logic := '0'; -- conduit_end.export
reset : in std_logic := '0' -- reset
);
end entity solenoid_controller;
architecture ctrl of solenoid_controller is
signal handling_btn : std_logic := '0';
signal handling_control : std_logic := '0';
signal tmp_control : std_logic_vector(7 downto 0) := "00000000";
begin
process(clock, reset)
begin
if(reset = '1') then
irq_btn_out <= '0';
status <= "00000000";
sol_shift_up_out <= '0';
sol_shift_down_out <= '0';
handling_btn <= '0';
handling_control <= '0';
elsif(rising_edge(clock)) then
if(btn_shift_up_in = '1' and handling_btn = '0') then
handling_btn <= '1';
status <= "00000001";
irq_btn_out <= '1';
elsif (btn_shift_down_in = '1' and handling_btn = '0') then
handling_btn <= '1';
status <= "00000010";
irq_btn_out <= '1';
elsif(btn_shift_up_in = '0' and btn_shift_down_in = '0') then
handling_btn <= '0';
status <= "00000000";
end if;
if(write_enable = '1' and chip_select = '1') then
tmp_control <= control;
end if;
if(tmp_control = "00000000") then
sol_shift_up_out <= '0';
sol_shift_down_out <= '0';
elsif(unsigned(tmp_control AND "10000000") = 128) then
irq_btn_out <= '0';
status <= "00000000";
elsif(unsigned(tmp_control AND "00000001") = 1) then
sol_shift_up_out <= '1';
sol_shift_down_out <= '0';
elsif(unsigned(tmp_control AND "00000010") = 2) then
sol_shift_up_out <= '0';
sol_shift_down_out <= '1';
end if;
end if;
end process;
end architecture ctrl; -- of solenoid_controller
|
apache-2.0
|
corneydavid/HT_FPGA
|
Exercises/Demonstrations/Failing Path in CLIP/DemoClipAdder.vhd
|
1
|
872
|
Library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity DemoClipAdder is
port (
clk : in std_logic;
aReset : in std_logic;
cPortA : in std_logic_vector(63 downto 0);
cPortB : in std_logic_vector(63 downto 0);
cPortC : in std_logic_vector(63 downto 0);
cPortD : in std_logic_vector(63 downto 0);
cPortE : in std_logic_vector(63 downto 0);
cAddOut : out std_logic_vector(63 downto 0) := (others => '0')
);
end DemoClipAdder;
architecture rtl of DemoClipAdder is
begin
process(aReset, clk) begin
if(aReset = '1') then
cAddOut <= (others => '0');
elsif rising_edge(clk) then
cAddOut <= std_logic_vector(signed(cPortA) + signed(cPortB) + signed(cPortC) + signed(cPortD) + signed(cPortE));
end if;
end process;
end rtl;
|
apache-2.0
|
Krabby127/ADC
|
scratch.vhd
|
1
|
3152
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.all;
library std;
USE std.textio.all;
entity tb2 is
end entity;
architecture behav2 of tb2 is
component adclb
port (
reset :in std_logic;
clk :in std_logic;
clrb :in std_logic;
scl :out std_logic;
sdai :in std_logic;
sdao :out std_logic;
sda_oe :out std_logic;
min_flag :out std_logic;
max_flag :out std_logic;
diff_flag :out std_logic;
max :out std_logic_vector (7 downto 0);
min :out std_logic_vector (7 downto 0);
value :inout std_logic_vector (7 downto 0) -- data sent back to master
);
end component;
signal clk : std_logic;
signal reset : std_logic;
signal sdai : std_logic;
signal sdao : std_logic;
signal sda_oe : std_logic;
signal min_i : std_logic;
signal max_i : std_logic;
signal diff_i : std_logic;
signal upd : std_logic;
signal scl : std_logic;
-- signal start_bit : std_logic;
-- signal stop_bit : std_logic;
-- shared variable bit_count : integer := 0;
begin
adc: adclb
port map (
reset => reset,
clk => clk,
clrb => reset,
scl => scl,
sdai => sdai,
sdao => sdao,
sda_oe => sda_oe,
diff_flag => diff_i,
min_flag => min_i,
max_flag => max_i,
max => open,
min => open,
value => open
);
clk_p:process
begin
clk <= '1';
wait for 5 ns;
clk <= '0';
wait for 5 ns;
end process;
testb:process
begin
reset <= '1';
-- start_bit <= '0';
sdai <= '0';
upd <= '0';
wait for 200ns;
reset <= '0';
wait for 5ms;
reset<='1';
wait for 200ns;
reset<='0';
wait for 6103us;
sdai <= '1';
wait for 2us;
sdai <= '0';
wait;
end process;
-- start_b:process
-- begin
-- wait until falling_edge(sdao);
---- wait for 0.64us;
-- wait until falling_edge(scl);
-- if stop_bit /= '1' then
-- start_bit<='1';
-- else
-- start_bit<='0';
-- end if;
-- end process;
--
--
-- stop_b:process
-- begin
-- wait until rising_edge(scl) and sdao='0';
-- if sdao='0' then
-- stop_bit<='1';
-- else
-- stop_bit<='0';
-- end if;
---- if rising_edge(sdao) then
---- stop_bit<='1';
---- else
---- stop_bit<='0';
---- end if;
-- end process;
--
-- count_bits:process
-- begin
-- if stop_bit='1' then
-- bit_count:=0;
-- end if;
-- wait until start_bit='1';
-- if rising_edge(scl) then
-- bit_count:=bit_count+1;
-- else
-- bit_count:=bit_count;
-- end if;
-- end process;
end;
|
apache-2.0
|
takeshineshiro/utrasound_fpga_modelsim
|
fpga_sim/model_trans/work/@a@d9273_@s@p@i_@config/_primary.vhd
|
1
|
1875
|
library verilog;
use verilog.vl_types.all;
entity AD9273_SPI_Config is
generic(
CHIP_PORT_CONFIG: integer := 24;
CHIP_ID : integer := 47;
CHIP_GRADE : integer := 16;
DEVICE_INDEX2 : integer := 15;
DEVICE_INDEX1 : integer := 15;
DEVICE_UPDATE_EN: integer := 1;
DEVICE_UPDATE_DIS: integer := 0;
Modes : integer := 0;
Clock : integer := 1;
TEST_IO : integer := 0;
FLEX_CHANNEL_INPUT: integer := 14;
FLEX_OFFSET : integer := 32;
FLEX_GAIN : integer := 14;
BIAS_CURRENT : integer := 8;
OUTPUT_MODE : integer := 0;
OUTPUT_ADJUST : integer := 49;
OUTPUT_PHASE : integer := 3;
FLEX_VREF : integer := 0;
USER_PATT1_LSB : integer := 0;
USER_PATT1_MSB : integer := 0;
USER_PATT2_LSB : integer := 0;
USER_PATT2_MSB : integer := 0;
SERIAL_CONTROL : integer := 0;
SERIAL_CH_STAT : integer := 0;
FLEX_FILTER : integer := 0;
ANALOG_INPUT : integer := 1;
CROSS_POINT_SWITCH: integer := 0;
DELAY_A : integer := 3;
DELAY_B : integer := 3;
DELAY_C : integer := 3;
DELAY_D : integer := 3;
DELAY_E : integer := 3;
DELAY_F : integer := 3;
DELAY_G : integer := 3;
DELAY_H : integer := 3;
SPI_PR : integer := 0;
SPI_REQ : integer := 1;
SPI_WAIT : integer := 2;
SPI_END : integer := 3
);
port(
RST_n : in vl_logic;
SPI_CLK : in vl_logic;
SPI_Data : inout vl_logic;
SPI_CS : out vl_logic
);
end AD9273_SPI_Config;
|
apache-2.0
|
airhdl/spi-to-axi-bridge
|
tb/tb_spi2axi.vhd
|
1
|
9013
|
----------------------------------------------------------------------------------------------------
--
-- SPI to AXI4-Lite Bridge Testbench
--
-- Description:
-- OSVVM testbench for the SPI to AXI4-Lite Bridge component. Use SPI master verification
-- component (VC) to issue SPI transactions to the unit under test, and AXI4Lite subordinate
-- VC to emulate an AXI4 lite register bank.
--
-- Author(s):
-- Guy Eschemann, [email protected]
--
----------------------------------------------------------------------------------------------------
--
-- Copyright (c) 2022 Guy Eschemann
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
----------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library OSVVM;
context OSVVM.OsvvmContext;
library osvvm_spi;
context osvvm_spi.SpiContext;
library osvvm_axi4;
context osvvm_axi4.Axi4LiteContext;
entity tb_spi2axi is
generic(
SPI_CPOL : natural range 0 to 1 := 0; -- SPI clock polarity
SPI_CPHA : natural range 0 to 1 := 0 -- SPI clock phase
);
end entity tb_spi2axi;
architecture TestHarness of tb_spi2axi is
-------------------------------------------------------------------------------
-- Components
-------------------------------------------------------------------------------
component tb_spi2axi_testctrl is
generic(
SPI_CPOL : natural range 0 to 1; -- SPI clock polarity
SPI_CPHA : natural range 0 to 1 -- SPI clock phase
);
port(
-- Record Interfaces
SpiRec : inout SpiRecType;
Axi4MemRec : inout AddressBusRecType;
-- Global Signal Interface
Clk : in std_logic;
nReset : in std_logic
);
end component;
------------------------------------------------------------------------------------------------
-- Constants
------------------------------------------------------------------------------------------------
constant AXI_ADDR_WIDTH : integer := 32; -- AXI address bus width, in bits
constant AXI_DATA_WIDTH : integer := 32;
constant AXI_STRB_WIDTH : integer := AXI_DATA_WIDTH / 8;
constant AXI_CLK_PERIOD : time := 10 ns;
constant TPD : time := 2 ns;
------------------------------------------------------------------------------------------------
-- Signals
------------------------------------------------------------------------------------------------
signal Axi4LiteBus : Axi4LiteRecType(
WriteAddress(Addr(AXI_ADDR_WIDTH - 1 downto 0)),
WriteData(Data(AXI_DATA_WIDTH - 1 downto 0), Strb(AXI_STRB_WIDTH - 1 downto 0)),
ReadAddress(Addr(AXI_ADDR_WIDTH - 1 downto 0)),
ReadData(Data(AXI_DATA_WIDTH - 1 downto 0))
);
signal Axi4MemRec : AddressBusRecType(
Address(AXI_ADDR_WIDTH - 1 downto 0),
DataToModel(AXI_DATA_WIDTH - 1 downto 0),
DataFromModel(AXI_DATA_WIDTH - 1 downto 0)
);
signal SpiRec : SpiRecType;
signal spi_sck : std_logic; -- SPI clock
signal spi_ss_n : std_logic; -- SPI slave select (low active)
signal spi_mosi : std_logic; -- SPI master-out-slave-in
signal spi_miso : std_logic; -- SPI master-in-slave-out
signal axi_aclk : std_logic;
signal axi_aresetn : std_logic;
signal s_axi_awvalid : std_logic;
signal s_axi_awvalid_mask : std_logic := '1'; -- @suppress "signal s_axi_awvalid_mask is never written"
signal s_axi_arvalid : std_logic;
signal s_axi_arvalid_mask : std_logic := '1'; -- @suppress "signal s_axi_arvalid_mask is never written"
begin
------------------------------------------------------------------------------------------------
-- Clock generator
------------------------------------------------------------------------------------------------
Osvvm.TbUtilPkg.CreateClock(
Clk => axi_aclk,
Period => AXI_CLK_PERIOD
);
------------------------------------------------------------------------------------------------
-- Reset generator
------------------------------------------------------------------------------------------------
Osvvm.TbUtilPkg.CreateReset(
Reset => axi_aresetn,
ResetActive => '0',
Clk => axi_aclk,
Period => 7 * AXI_CLK_PERIOD,
tpd => TPD
);
------------------------------------------------------------------------------------------------
-- Test controller
------------------------------------------------------------------------------------------------
testctrl_inst : tb_spi2axi_testctrl
generic map(
SPI_CPOL => SPI_CPOL,
SPI_CPHA => SPI_CPHA
)
port map(
SpiRec => SpiRec,
Axi4MemRec => Axi4MemRec,
Clk => axi_aclk,
nReset => axi_aresetn
);
------------------------------------------------------------------------------------------------
-- SPI master verification component
------------------------------------------------------------------------------------------------
spi_master_inst : entity osvvm_spi.Spi
generic map(
MODEL_ID_NAME => "Spi",
DEFAULT_SCLK_PERIOD => SPI_SCLK_PERIOD_1M
)
port map(
TransRec => SpiRec,
SCLK => spi_sck,
SS => spi_ss_n,
MOSI => spi_mosi,
MISO => spi_miso
);
------------------------------------------------------------------------------------------------
-- Unit under test
------------------------------------------------------------------------------------------------
uut : entity work.spi2axi
generic map(
SPI_CPOL => SPI_CPOL,
SPI_CPHA => SPI_CPHA,
AXI_ADDR_WIDTH => AXI_ADDR_WIDTH
)
port map(
spi_sck => spi_sck,
spi_ss_n => spi_ss_n,
spi_mosi => spi_mosi,
spi_miso => spi_miso,
axi_aclk => axi_aclk,
axi_aresetn => axi_aresetn,
s_axi_awaddr => Axi4LiteBus.WriteAddress.Addr,
s_axi_awprot => Axi4LiteBus.WriteAddress.Prot,
s_axi_awvalid => s_axi_awvalid, -- Axi4LiteBus.WriteAddress.Valid,
s_axi_awready => Axi4LiteBus.WriteAddress.Ready,
s_axi_wdata => Axi4LiteBus.WriteData.Data,
s_axi_wstrb => Axi4LiteBus.WriteData.Strb,
s_axi_wvalid => Axi4LiteBus.WriteData.Valid,
s_axi_wready => Axi4LiteBus.WriteData.Ready,
s_axi_araddr => Axi4LiteBus.ReadAddress.Addr,
s_axi_arprot => Axi4LiteBus.ReadAddress.Prot,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => Axi4LiteBus.ReadAddress.Ready,
s_axi_rdata => Axi4LiteBus.ReadData.Data,
s_axi_rresp => Axi4LiteBus.ReadData.Resp,
s_axi_rvalid => Axi4LiteBus.ReadData.Valid,
s_axi_rready => Axi4LiteBus.ReadData.Ready,
s_axi_bresp => Axi4LiteBus.WriteResponse.Resp,
s_axi_bvalid => Axi4LiteBus.WriteResponse.Valid,
s_axi_bready => Axi4LiteBus.WriteResponse.Ready
);
Axi4LiteBus.WriteAddress.Valid <= s_axi_awvalid and s_axi_awvalid_mask;
Axi4LiteBus.ReadAddress.Valid <= s_axi_arvalid and s_axi_arvalid_mask;
------------------------------------------------------------------------------------------------
-- AXI4 lite memory verification component
------------------------------------------------------------------------------------------------
axi4lite_memory_inst : entity osvvm_axi4.Axi4LiteMemory
generic map(
MODEL_ID_NAME => "Axi4LiteMemory",
MEMORY_NAME => "Axi4LiteMemory",
tperiod_Clk => AXI_CLK_PERIOD
)
port map(
-- Globals
Clk => axi_aclk,
nReset => axi_aresetn,
-- AXI Manager Functional Interface
AxiBus => Axi4LiteBus,
-- Testbench Transaction Interface
TransRec => Axi4MemRec
);
end architecture TestHarness;
|
apache-2.0
|
takeshineshiro/utrasound_fpga_modelsim
|
fpga_sim/model_trans/work/butterfly_radix4_2nd/_primary.vhd
|
2
|
5250
|
library verilog;
use verilog.vl_types.all;
entity butterfly_radix4_2nd is
generic(
cos0 : integer := 32767;
cos1 : integer := 32767;
cos2 : integer := 32767;
cos3 : integer := 30273;
cos4 : integer := 23170;
cos5 : integer := 12540;
cos6 : integer := 23170;
cos7 : integer := 0;
cos8 : integer := 42366;
cos9 : integer := 12540;
cos10 : integer := 42366;
cos11 : integer := 35263;
sin0 : integer := 0;
sin1 : integer := 0;
sin2 : integer := 0;
sin3 : integer := 52996;
sin4 : integer := 42366;
sin5 : integer := 35263;
sin6 : integer := 42366;
sin7 : integer := 32769;
sin8 : integer := 42366;
sin9 : integer := 35263;
sin10 : integer := 42366;
sin11 : integer := 12540
);
port(
clk : in vl_logic;
re_0 : in vl_logic_vector(15 downto 0);
re_1 : in vl_logic_vector(15 downto 0);
re_2 : in vl_logic_vector(15 downto 0);
re_3 : in vl_logic_vector(15 downto 0);
re_4 : in vl_logic_vector(15 downto 0);
re_5 : in vl_logic_vector(15 downto 0);
re_6 : in vl_logic_vector(15 downto 0);
re_7 : in vl_logic_vector(15 downto 0);
re_8 : in vl_logic_vector(15 downto 0);
re_9 : in vl_logic_vector(15 downto 0);
re_10 : in vl_logic_vector(15 downto 0);
re_11 : in vl_logic_vector(15 downto 0);
re_12 : in vl_logic_vector(15 downto 0);
re_13 : in vl_logic_vector(15 downto 0);
re_14 : in vl_logic_vector(15 downto 0);
re_15 : in vl_logic_vector(15 downto 0);
im_0 : in vl_logic_vector(15 downto 0);
im_1 : in vl_logic_vector(15 downto 0);
im_2 : in vl_logic_vector(15 downto 0);
im_3 : in vl_logic_vector(15 downto 0);
im_4 : in vl_logic_vector(15 downto 0);
im_5 : in vl_logic_vector(15 downto 0);
im_6 : in vl_logic_vector(15 downto 0);
im_7 : in vl_logic_vector(15 downto 0);
im_8 : in vl_logic_vector(15 downto 0);
im_9 : in vl_logic_vector(15 downto 0);
im_10 : in vl_logic_vector(15 downto 0);
im_11 : in vl_logic_vector(15 downto 0);
im_12 : in vl_logic_vector(15 downto 0);
im_13 : in vl_logic_vector(15 downto 0);
im_14 : in vl_logic_vector(15 downto 0);
im_15 : in vl_logic_vector(15 downto 0);
butterfly_re0 : out vl_logic_vector(15 downto 0);
butterfly_re1 : out vl_logic_vector(15 downto 0);
butterfly_re2 : out vl_logic_vector(15 downto 0);
butterfly_re3 : out vl_logic_vector(15 downto 0);
butterfly_re4 : out vl_logic_vector(15 downto 0);
butterfly_re5 : out vl_logic_vector(15 downto 0);
butterfly_re6 : out vl_logic_vector(15 downto 0);
butterfly_re7 : out vl_logic_vector(15 downto 0);
butterfly_re8 : out vl_logic_vector(15 downto 0);
butterfly_re9 : out vl_logic_vector(15 downto 0);
butterfly_re10 : out vl_logic_vector(15 downto 0);
butterfly_re11 : out vl_logic_vector(15 downto 0);
butterfly_re12 : out vl_logic_vector(15 downto 0);
butterfly_re13 : out vl_logic_vector(15 downto 0);
butterfly_re14 : out vl_logic_vector(15 downto 0);
butterfly_re15 : out vl_logic_vector(15 downto 0);
butterfly_im0 : out vl_logic_vector(15 downto 0);
butterfly_im1 : out vl_logic_vector(15 downto 0);
butterfly_im2 : out vl_logic_vector(15 downto 0);
butterfly_im3 : out vl_logic_vector(15 downto 0);
butterfly_im4 : out vl_logic_vector(15 downto 0);
butterfly_im5 : out vl_logic_vector(15 downto 0);
butterfly_im6 : out vl_logic_vector(15 downto 0);
butterfly_im7 : out vl_logic_vector(15 downto 0);
butterfly_im8 : out vl_logic_vector(15 downto 0);
butterfly_im9 : out vl_logic_vector(15 downto 0);
butterfly_im10 : out vl_logic_vector(15 downto 0);
butterfly_im11 : out vl_logic_vector(15 downto 0);
butterfly_im12 : out vl_logic_vector(15 downto 0);
butterfly_im13 : out vl_logic_vector(15 downto 0);
butterfly_im14 : out vl_logic_vector(15 downto 0);
butterfly_im15 : out vl_logic_vector(15 downto 0)
);
end butterfly_radix4_2nd;
|
apache-2.0
|
zyq524/Habitat
|
src/Foundation/Theming/code/bower_components/ace-builds/demo/kitchen-sink/docs/vhdl.vhd
|
472
|
830
|
library IEEE
user IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity COUNT16 is
port (
cOut :out std_logic_vector(15 downto 0); -- counter output
clkEn :in std_logic; -- count enable
clk :in std_logic; -- clock input
rst :in std_logic -- reset input
);
end entity;
architecture count_rtl of COUNT16 is
signal count :std_logic_vector (15 downto 0);
begin
process (clk, rst) begin
if(rst = '1') then
count <= (others=>'0');
elsif(rising_edge(clk)) then
if(clkEn = '1') then
count <= count + 1;
end if;
end if;
end process;
cOut <= count;
end architecture;
|
apache-2.0
|
takeshineshiro/utrasound_fpga_modelsim
|
fpga_sim/model_rec/work/@d@a@s_@r@f/_primary.vhd
|
2
|
426
|
library verilog;
use verilog.vl_types.all;
entity DAS_RF is
port(
clock : in vl_logic;
data : in vl_logic_vector(15 downto 0);
rdaddress : in vl_logic_vector(13 downto 0);
wraddress : in vl_logic_vector(13 downto 0);
wren : in vl_logic;
q : out vl_logic_vector(15 downto 0)
);
end DAS_RF;
|
apache-2.0
|
takeshineshiro/utrasound_fpga_modelsim
|
fpga_sim/model_trans/work/butter_2/_primary.vhd
|
1
|
867
|
library verilog;
use verilog.vl_types.all;
entity butter_2 is
generic(
RST_LVL : integer := 0
);
port(
clk : in vl_logic;
rst : in vl_logic;
butt2_real0 : in vl_logic_vector(15 downto 0);
butt2_imag0 : in vl_logic_vector(15 downto 0);
butt2_real1 : in vl_logic_vector(15 downto 0);
butt2_imag1 : in vl_logic_vector(15 downto 0);
factor_real : in vl_logic_vector(15 downto 0);
factor_imag : in vl_logic_vector(15 downto 0);
y0_real : out vl_logic_vector(15 downto 0);
y0_imag : out vl_logic_vector(15 downto 0);
y1_real : out vl_logic_vector(15 downto 0);
y1_imag : out vl_logic_vector(15 downto 0)
);
end butter_2;
|
apache-2.0
|
takeshineshiro/utrasound_fpga_modelsim
|
fpga_sim/model_trans/work/mult12_8/_primary.vhd
|
2
|
323
|
library verilog;
use verilog.vl_types.all;
entity mult12_8 is
port(
clock : in vl_logic;
dataa : in vl_logic_vector(11 downto 0);
datab : in vl_logic_vector(7 downto 0);
result : out vl_logic_vector(19 downto 0)
);
end mult12_8;
|
apache-2.0
|
takeshineshiro/utrasound_fpga_modelsim
|
fpga_sim/model_trans/work/@a@b@s/_primary.vhd
|
2
|
212
|
library verilog;
use verilog.vl_types.all;
entity \ABS\ is
port(
data : in vl_logic_vector(29 downto 0);
result : out vl_logic_vector(29 downto 0)
);
end \ABS\;
|
apache-2.0
|
LabVIEW-Power-Electronic-Control/Scale-And-Limit
|
dev/Core/AIScale/I16ToSGL_convert/xbip_utils_v3_0_5/hdl/xbip_utils_v3_0_vh_rfs.vhd
|
1
|
157786
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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kUFzXQkGKA==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 114672)
`protect data_block
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`protect end_protected
|
apache-2.0
|
LabVIEW-Power-Electronic-Control/Scale-And-Limit
|
dev/Core/AIScale/I16ToSGL_convert/xbip_dsp48_multadd_v3_0_1/hdl/xbip_dsp48_multadd_v3_0_vh_rfs.vhd
|
1
|
73491
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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Pb0s5EPqQg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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/Xw/fmPusBCAjypI7W8=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
q/HCqeI7pjLZP7dTRc9Wsm0ELyKVRBTbBIQceFsa7XBrwSB/Hxn+c9ZemJdK3ZQqnTgalYuqvGzT
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5GsyZ5fS8fCECjX6zWuv/hbEbAYwMw5FsbVNLw==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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j8YlkVnGzaHwXMVAkuQ=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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UG+FTLWF3eQptYgGPO1l+wDJ6LNKgIdZWc712w==
`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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lKi9OSHc+sAGQLf46joESuhuInipfrkgBi+Sbw==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 52272)
`protect data_block
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`protect end_protected
|
apache-2.0
|
DGideas/THU-FPGA-makecomputer
|
src/cpu/if_id_segment_regfile.vhd
|
1
|
927
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity if_id_segment_regfile is
port
(
if_id_segment_regfile_clk: in std_logic;
if_id_segment_regfile_write_in: in std_logic;
if_id_segment_regfile_instruction_in: in std_logic_vector(15 downto 0);
if_id_segment_regfile_instruction_out: out std_logic_vector(15 downto 0);
if_id_segment_regfile_pc_in: in std_logic_vector(15 downto 0);
if_id_segment_regfile_pc_out: out std_logic_vector(15 downto 0)
);
end if_id_segment_regfile;
architecture Behavioral of if_id_segment_regfile is
begin
process(if_id_segment_regfile_clk, if_id_segment_regfile_write_in)
begin
if (if_id_segment_regfile_write_in = '1') then
if_id_segment_regfile_pc_out <= if_id_segment_regfile_pc_in;
if_id_segment_regfile_instruction_out <= if_id_segment_regfile_instruction_in;
end if;
end process;
end Behavioral;
|
apache-2.0
|
wsoltys/AtomFpga
|
src/AVR8/Memory/XDM4Kx8.vhd
|
1
|
2292
|
--************************************************************************************************
-- 4Kx8(16 KB) DM RAM for AVR Core(Xilinx)
-- Version 0.2
-- Designed by Ruslan Lepetenok
-- Jack Gassett for use with Papilio
-- Modified 30.07.2005
--************************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use WORK.SynthCtrlPack.all; -- Synthesis control
-- For Synplicity Synplify
--library virtexe;
--use virtexe.components.all;
-- Aldec
library unisim;
use unisim.vcomponents.all;
entity XDM4Kx8 is port(
cp2 : in std_logic;
ce : in std_logic;
address : in std_logic_vector(CDATAMEMSIZE downto 0);
din : in std_logic_vector(7 downto 0);
dout : out std_logic_vector(7 downto 0);
we : in std_logic
);
end XDM4Kx8;
architecture RTL of XDM4Kx8 is
type RAMBlDOut_Type is array(2**(address'length-11)-1 downto 0) of std_logic_vector(dout'range);
signal RAMBlDOut : RAMBlDOut_Type;
signal WEB : std_logic_vector(2**(address'length-11)-1 downto 0);
signal cp2n : std_logic;
signal gnd : std_logic;
signal DIP : STD_LOGIC_VECTOR(0 downto 0) := "1";
signal SSR : STD_LOGIC := '0'; -- Don't use the output resets.
begin
gnd <= '0';
WEB_Dcd:for i in WEB'range generate
WEB(i) <= '1' when (we='1' and address(address'high downto 11)=i) else '0';
end generate ;
RAM_Inst:for i in 0 to 2**(address'length-11)-1 generate
RAM_Byte:component RAMB16_S9 port map(
DO => RAMBlDOut(i)(7 downto 0),
ADDR => address(10 downto 0),
DI => din(7 downto 0),
DIP => DIP,
EN => ce,
SSR => SSR,
CLK => cp2,
WE => WEB(i)
);
end generate;
-- Output data mux
dout <= RAMBlDOut(CONV_INTEGER(address(address'high downto 11)));
end RTL;
|
apache-2.0
|
wsoltys/AtomFpga
|
src/AtomGodilVideo/src/MINIUART/Rxunit.vhd
|
1
|
3421
|
-------------------------------------------------------------------------------
-- Title : UART
-- Project : UART
-------------------------------------------------------------------------------
-- File : Rxunit.vhd
-- Author : Philippe CARTON
-- ([email protected])
-- Organization:
-- Created : 15/12/2001
-- Last update : 8/1/2003
-- Platform : Foundation 3.1i
-- Simulators : ModelSim 5.5b
-- Synthesizers: Xilinx Synthesis
-- Targets : Xilinx Spartan
-- Dependency : IEEE std_logic_1164
-------------------------------------------------------------------------------
-- Description: RxUnit is a serial to parallel unit Receiver.
-------------------------------------------------------------------------------
-- Copyright (c) notice
-- This core adheres to the GNU public license
--
-------------------------------------------------------------------------------
-- Revisions :
-- Revision Number :
-- Version :
-- Date :
-- Modifier : name <email>
-- Description :
--
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity RxUnit is
port (
Clk : in std_logic; -- system clock signal
Reset : in std_logic; -- Reset input
Enable : in std_logic; -- Enable input
ReadA : in Std_logic; -- Async Read Received Byte
RxD : in std_logic; -- RS-232 data input
RxAv : out std_logic; -- Byte available
DataO : out std_logic_vector(7 downto 0)); -- Byte received
end RxUnit;
architecture Behaviour of RxUnit is
signal RReg : std_logic_vector(7 downto 0); -- receive register
signal RRegL : std_logic; -- Byte received
begin
-- RxAv process
RxAvProc : process(RRegL,Reset,ReadA)
begin
if ReadA = '1' or Reset = '1' then
RxAv <= '0'; -- Negate RxAv when RReg read
elsif Rising_Edge(RRegL) then
RxAv <= '1'; -- Assert RxAv when RReg written
end if;
end process;
-- Rx Process
RxProc : process(Clk,Reset,Enable,RxD,RReg)
variable BitPos : INTEGER range 0 to 10; -- Position of the bit in the frame
variable SampleCnt : INTEGER range 0 to 3; -- Count from 0 to 3 in each bit
begin
if Reset = '1' then -- Reset
RRegL <= '0';
BitPos := 0;
elsif Rising_Edge(Clk) then
if Enable = '1' then
case BitPos is
when 0 => -- idle
RRegL <= '0';
if RxD = '0' then -- Start Bit
SampleCnt := 0;
BitPos := 1;
end if;
when 10 => -- Stop Bit
BitPos := 0; -- next is idle
RRegL <= '1'; -- Indicate byte received
DataO <= RReg; -- Store received byte
when others =>
if (SampleCnt = 1 and BitPos >= 2) then -- Sample RxD on 1
RReg(BitPos-2) <= RxD; -- Deserialisation
end if;
if SampleCnt = 3 then -- Increment BitPos on 3
BitPos := BitPos + 1;
end if;
end case;
if SampleCnt = 3 then
SampleCnt := 0;
else
sampleCnt := SampleCnt + 1;
end if;
end if;
end if;
end process;
end Behaviour;
|
apache-2.0
|
lumig242/Hue-Integration-with-CDAP
|
tools/ace-editor/demo/kitchen-sink/docs/vhdl.vhd
|
472
|
830
|
library IEEE
user IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity COUNT16 is
port (
cOut :out std_logic_vector(15 downto 0); -- counter output
clkEn :in std_logic; -- count enable
clk :in std_logic; -- clock input
rst :in std_logic -- reset input
);
end entity;
architecture count_rtl of COUNT16 is
signal count :std_logic_vector (15 downto 0);
begin
process (clk, rst) begin
if(rst = '1') then
count <= (others=>'0');
elsif(rising_edge(clk)) then
if(clkEn = '1') then
count <= count + 1;
end if;
end if;
end process;
cOut <= count;
end architecture;
|
apache-2.0
|
wsoltys/AtomFpga
|
src/AtomGodilVideo/src/DCM/DCM0.vhd
|
2
|
2059
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.Vcomponents.all;
entity DCM0 is
port (CLKIN_IN : in std_logic;
CLK0_OUT : out std_logic;
CLK0_OUT1 : out std_logic;
CLK2X_OUT : out std_logic);
end DCM0;
architecture BEHAVIORAL of DCM0 is
signal CLKFX_BUF : std_logic;
signal CLKIN_IBUFG : std_logic;
signal GND_BIT : std_logic;
begin
GND_BIT <= '0';
CLKFX_BUFG_INST : BUFG
port map (I => CLKFX_BUF, O => CLK0_OUT);
DCM_INST : DCM
generic map(CLK_FEEDBACK => "NONE",
CLKDV_DIVIDE => 4.0, -- 25.368 =49.152 * 16 / 31
CLKFX_DIVIDE => 31,
CLKFX_MULTIPLY => 16,
CLKIN_DIVIDE_BY_2 => false,
CLKIN_PERIOD => 20.344,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => true,
FACTORY_JF => x"C080",
PHASE_SHIFT => 0,
STARTUP_WAIT => false)
port map (CLKFB => GND_BIT,
CLKIN => CLKIN_IN,
DSSEN => GND_BIT,
PSCLK => GND_BIT,
PSEN => GND_BIT,
PSINCDEC => GND_BIT,
RST => GND_BIT,
CLKDV => open,
CLKFX => CLKFX_BUF,
CLKFX180 => open,
CLK0 => open,
CLK2X => CLK2X_OUT,
CLK2X180 => open,
CLK90 => open,
CLK180 => open,
CLK270 => open,
LOCKED => open,
PSDONE => open,
STATUS => open);
end BEHAVIORAL;
|
apache-2.0
|
takeshineshiro/fpga_fibre_scan
|
HUCB2P0_150701/frontend/const_delay.vhd
|
1
|
2565
|
-- This is the implementation of a constant delay
--
-- This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License
-- as published by the Free Software Foundation; either version 3 of the License, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along with this program;
-- if not, see <http://www.gnu.org/licenses/>.
-- Package Definition
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_arith.all;
use IEEE.STD_LOGIC_unsigned.all;
package const_delay_pkg is
component const_delay
generic(
data_width : integer;
delay_in_clks : integer
);
port(
clk_i : in std_logic;
rst_i : in std_logic;
data_i : in std_logic_vector(data_width-1 downto 0);
data_str_i : in std_logic;
data_o : out std_logic_vector(data_width-1 downto 0);
data_str_o : out std_logic
);
end component;
end const_delay_pkg;
package body const_delay_pkg is
end const_delay_pkg;
-- Entity Definition
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_arith.all;
use IEEE.STD_LOGIC_unsigned.all;
entity const_delay is
generic(
data_width : integer := 16;
delay_in_clks : integer := 10
);
port(
clk_i : in std_logic;
rst_i : in std_logic;
data_i : in std_logic_vector(data_width-1 downto 0);
data_str_i : in std_logic;
data_o : out std_logic_vector(data_width-1 downto 0);
data_str_o : out std_logic
);
end const_delay;
architecture const_delay_arch of const_delay is
type register_line is array(0 to delay_in_clks-1) of std_logic_vector(data_width-1 downto 0);
type data_str_line is array(0 to delay_in_clks-1) of std_logic;
signal data_int : register_line;
signal data_str_int : data_str_line;
begin
process (clk_i, rst_i)
begin
if rst_i = '1' then
for i in 0 to delay_in_clks-1 loop
data_int(i) <= (others => '0');
data_str_int(i) <= '0';
end loop;
elsif clk_i'EVENT and clk_i = '1' then
data_int(0) <= data_i;
data_str_int(0) <= data_str_i;
for i in 0 to delay_in_clks-2 loop
data_int(i+1) <= data_int(i);
data_str_int(i+1) <= data_str_int(i);
end loop;
end if;
end process;
data_o <= data_int(delay_in_clks-1);
data_str_o <= data_str_int(delay_in_clks-1);
end const_delay_arch;
|
apache-2.0
|
rauenzi/VHDL-Communications
|
top_level.vhd
|
1
|
6220
|
----------------------------------------------------------------------------------
--Code by: Zachary Rauen
--Date: 10/6/14
--Last Modified: 1/22/15
--
--
--Version: 1.2
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use IEEE.std_logic_unsigned.all; -- add to do arithmetic operations
use IEEE.std_logic_arith.all; -- add to do arithmetic operations
entity top_level is
Generic (constant SequenceDisplaySpeed : integer := 1; -- 1 Hz
constant RefreshSpeed : integer := 1000; -- 1 KHz
constant sequenceCount : integer := 8;
constant BoardClock : integer := 100000000;
constant buttonMax: std_logic_vector(15 downto 0) := X"FFFF";
constant baud : integer := 9600;
constant SPIspeed : integer :=250000); -- 1KHz, 1Hz
-- Generic (constant SequenceDisplaySpeed : integer := 1000;
-- constant RefreshSpeed : integer := 100000;
-- constant BoardClock : integer := 100000000;
-- constant sequenceCount : integer := 8;
-- constant buttonMax: std_logic_vector(15 downto 0) := X"0002";
-- constant baud : integer := 2000000;
-- constant SPIspeed : integer :=2000000);
----The above lines are used for simulation and chipscope.
Port ( clk : in std_logic;
reset : in std_logic;
reverse : in std_logic;
enabler : in std_logic;
DispVector : out std_logic_vector(7 downto 0);
SegVector : out std_logic_vector(7 downto 0);
oRx : out std_logic;
oSCK : out std_logic;
oSS : out std_logic;
oMOSI : out std_logic;
i2c_sda : inout std_logic;
i2c_scl : inout std_logic);
end top_level;
architecture Behavioral of top_level is
component BoardDisplay is
Generic (RefreshRate : integer := 1000;
ClockSpeed : integer := 100000000);
Port ( ClockState : in std_logic;
Data : in std_logic_vector(15 downto 0);
DisplayVector : out std_logic_vector(7 downto 0);
SegmentVector : out std_logic_vector(7 downto 0));
end component BoardDisplay;
component SequenceController is
Generic (NumOfSequences : integer := 8;
DesiredDisplaySpeed : integer := 100000;
InputClockSpeed : integer := 100000000);
Port ( ClockState : in std_logic;
Enabler : in std_logic;
Reset : in std_logic;
Reverse : in std_logic;
MemAddress : out integer := 0);
end component SequenceController;
component Serial_TTL_display is
Generic (BaudSpeed : integer :=9600;
Boardspeed : integer :=100000000);
Port ( Clock : in STD_LOGIC;
Data : in STD_LOGIC_VECTOR (15 downto 0);
RX : out STD_LOGIC);
end component Serial_TTL_display;
component btn_debounce_toggle is
GENERIC (
CONSTANT CNTR_MAX : std_logic_vector(15 downto 0) := X"FFFF");
Port ( BTN_I : in STD_LOGIC;
CLK : in STD_LOGIC;
BTN_O : out STD_LOGIC;
TOGGLE_O : out STD_LOGIC);
end component btn_debounce_toggle;
-- SequenceStorage should be a Xilinx single port ROM IP-Core
COMPONENT SequenceStorage
PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END COMPONENT;
component SPI_display is
Generic (constant BoardClockSpeed : integer := 100000000;
constant SCKSpeed : integer := 250000);
Port ( BoardClock : in STD_LOGIC;
Data : in STD_LOGIC_VECTOR (15 downto 0);
SCK : out STD_LOGIC;
SS : out STD_LOGIC;
MOSI : out STD_LOGIC
);
end component SPI_display;
component i2c_controller is
Port ( Clock : in STD_LOGIC;
dataIn : in STD_LOGIC_VECTOR (15 downto 0);
oSDA : inout STD_LOGIC;
oSCL : inout STD_LOGIC);
end component i2c_controller;
signal resetDebounce, enablerToggle, reverseToggle : std_logic;
signal DataFromRom : std_logic_vector(15 downto 0);
signal DataAddress : integer;
signal DataAddressToRom : std_logic_vector(3 downto 0);
signal notReverseToggle : std_logic;
signal high : std_logic := '1';
begin
notReverseToggle <= NOT reverseToggle;
DataAddressToRom <= std_logic_vector(to_unsigned(DataAddress,4));
Reset_debounce: btn_debounce_toggle
generic map (CNTR_MAX => buttonMax)
port map (BTN_I=>reset,CLK=>clk,BTN_O=>resetDebounce,TOGGLE_O=>OPEN);
Enabler_debounce: btn_debounce_toggle
generic map (CNTR_MAX => buttonMax)
port map (BTN_I=>enabler,CLK=>clk,BTN_O=>OPEN,TOGGLE_O=>enablerToggle);
Reverse_debounce: btn_debounce_toggle
generic map (CNTR_MAX => buttonMax)
port map (BTN_I=>reverse,CLK=>clk,BTN_O=>OPEN,TOGGLE_O=>reverseToggle);
SequenceControl: SequenceController
Generic map (NumOfSequences=>sequenceCount,
DesiredDisplaySpeed=>SequenceDisplaySpeed,
InputClockSpeed=>BoardClock)
Port map (ClockState=>clk,
Enabler=>enablerToggle,
Reset=>resetDebounce,
Reverse=> notReverseToggle,
MemAddress=>DataAddress);
BoardController: BoardDisplay
generic map (RefreshRate=>RefreshSpeed,
ClockSpeed=>BoardClock)
port map ( ClockState=>clk,
Data=>DataFromRom,
DisplayVector=>DispVector,
SegmentVector=>SegVector);
TTL: Serial_TTL_display
generic map (BaudSpeed=>baud,
Boardspeed=>BoardClock)
Port map ( Clock=>clk,
Data=>DataFromRom,
RX=>oRx);
MainRom: SequenceStorage
PORT MAP (
clka => clk,
addra => DataAddressToRom,
douta => DataFromRom
);
SPI: SPI_display
generic map (BoardClockSpeed=>BoardClock,
SCKSpeed=>SPIspeed)
Port map ( BoardClock=>clk,
Data=>DataFromRom,
SCK=>oSCK,
SS=>oSS,
MOSI=>oMOSI
);
I2C: i2c_controller
Port map ( Clock=>clk,
dataIn=>DataFromRom,
oSDA=>i2c_sda,
oSCL=>i2c_scl);
end Behavioral;
|
apache-2.0
|
wsoltys/AtomFpga
|
src/AVR8/resync/rsnc_l_vect.vhd
|
4
|
1771
|
--**********************************************************************************************
-- Resynchronizer (for n-bit vector) with latch
-- Version 0.1
-- Modified 10.01.2007
-- Designed by Ruslan Lepetenok
--**********************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
entity rsnc_l_vect is generic(
tech : integer := 0;
width : integer := 8;
add_stgs_num : integer := 0
);
port(
clk : in std_logic;
di : in std_logic_vector(width-1 downto 0);
do : out std_logic_vector(width-1 downto 0)
);
end rsnc_l_vect;
architecture rtl of rsnc_l_vect is
type rsnc_vect_type is array(add_stgs_num+1 downto 0) of std_logic_vector(width-1 downto 0);
signal rsnc_rg_current : rsnc_vect_type;
signal rsnc_rg_next : rsnc_vect_type;
begin
-- Latch
latch_prc:process(clk)
begin
if(clk='0') then
rsnc_rg_current(rsnc_rg_current'low) <= rsnc_rg_next(rsnc_rg_next'low);
end if;
end process;
-- Latch
seq_re_prc:process(clk)
begin
if(clk='1' and clk'event) then -- Clock (rising edge)
rsnc_rg_current(rsnc_rg_current'high downto rsnc_rg_current'low+1) <= rsnc_rg_next(rsnc_rg_current'high downto rsnc_rg_current'low+1);
end if;
end process;
comb_prc:process(di,rsnc_rg_current)
begin
rsnc_rg_next(0) <= di;
for i in 1 to rsnc_rg_next'high loop
rsnc_rg_next(i) <= rsnc_rg_current(i-1);
end loop;
end process;
do <= rsnc_rg_current(rsnc_rg_current'high);
end rtl;
|
apache-2.0
|
takeshineshiro/fpga_fibre_scan
|
HUCB2P0_150701/frontend/fir_band_pass.vhd
|
1
|
11585
|
-- megafunction wizard: %FIR Compiler v12.1%
-- GENERATION: XML
-- ============================================================
-- Megafunction Name(s):
-- fir_band_pass_ast
-- ============================================================
-- Generated by FIR Compiler 12.1 [Altera, IP Toolbench 1.3.0 Build 243]
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-- ************************************************************
-- Copyright (C) 1991-2013 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera. Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner. Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors. No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.
library IEEE;
use IEEE.std_logic_1164.all;
ENTITY fir_band_pass IS
PORT (
clk : IN STD_LOGIC;
reset_n : IN STD_LOGIC;
ast_sink_data : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
ast_sink_valid : IN STD_LOGIC;
ast_source_ready : IN STD_LOGIC;
ast_sink_error : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
ast_source_data : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
ast_sink_ready : OUT STD_LOGIC;
ast_source_valid : OUT STD_LOGIC;
ast_source_error : OUT STD_LOGIC_VECTOR (1 DOWNTO 0)
);
END fir_band_pass;
ARCHITECTURE SYN OF fir_band_pass IS
COMPONENT fir_band_pass_ast
PORT (
clk : IN STD_LOGIC;
reset_n : IN STD_LOGIC;
ast_sink_data : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
ast_sink_valid : IN STD_LOGIC;
ast_source_ready : IN STD_LOGIC;
ast_sink_error : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
ast_source_data : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
ast_sink_ready : OUT STD_LOGIC;
ast_source_valid : OUT STD_LOGIC;
ast_source_error : OUT STD_LOGIC_VECTOR (1 DOWNTO 0)
);
END COMPONENT;
BEGIN
fir_band_pass_ast_inst : fir_band_pass_ast
PORT MAP (
clk => clk,
reset_n => reset_n,
ast_sink_data => ast_sink_data,
ast_source_data => ast_source_data,
ast_sink_valid => ast_sink_valid,
ast_sink_ready => ast_sink_ready,
ast_source_valid => ast_source_valid,
ast_source_ready => ast_source_ready,
ast_sink_error => ast_sink_error,
ast_source_error => ast_source_error
);
END SYN;
-- =========================================================
-- FIR Compiler Wizard Data
-- ===============================
-- DO NOT EDIT FOLLOWING DATA
-- @Altera, IP Toolbench@
-- Warning: If you modify this section, FIR Compiler Wizard may not be able to reproduce your chosen configuration.
--
-- Retrieval info: <?xml version="1.0"?>
-- Retrieval info: <MEGACORE title="FIR Compiler" version="12.1" build="243" iptb_version="1.3.0 Build 243" format_version="120" >
-- Retrieval info: <NETLIST_SECTION class="altera.ipbu.flowbase.netlist.model.FIRModelClass" active_core="fir_band_pass_ast" >
-- Retrieval info: <STATIC_SECTION>
-- Retrieval info: <PRIVATES>
-- Retrieval info: <NAMESPACE name = "parameterization">
-- Retrieval info: <PRIVATE name = "use_mem" value="1" type="BOOLEAN" enable="1" />
-- Retrieval info: <PRIVATE name = "mem_type" value="M512" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "filter_rate" value="Single Rate" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "filter_factor" value="2" type="INTEGER" enable="0" />
-- Retrieval info: <PRIVATE name = "coefficient_scaling_type" value="Auto" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "coefficient_scaling_factor" value="2663.965303912064" type="STRING" enable="0" />
-- Retrieval info: <PRIVATE name = "coefficient_bit_width" value="11" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "coefficient_binary_point_position" value="0" type="INTEGER" enable="0" />
-- Retrieval info: <PRIVATE name = "number_of_input_channels" value="1" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "input_number_system" value="Signed Binary" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "input_bit_width" value="12" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "input_binary_point_position" value="0" type="INTEGER" enable="0" />
-- Retrieval info: <PRIVATE name = "output_bit_width_method" value="Actual Coefficients" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "output_number_system" value="Custom Resolution" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "output_bit_width" value="16" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "output_bits_right_of_binary_point" value="16" type="INTEGER" enable="0" />
-- Retrieval info: <PRIVATE name = "output_bits_removed_from_lsb" value="9" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "output_lsb_remove_type" value="Truncate" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "output_msb_remove_type" value="Truncate" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "flow_control" value="0" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "flow_control_input" value="Slave Sink" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "flow_control_output" value="Master Source" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "device_family" value="Cyclone III" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "structure" value="Distributed Arithmetic : Fully Parallel Filter" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "pipeline_level" value="3" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "clocks_to_compute" value="1" type="INTEGER" enable="0" />
-- Retrieval info: <PRIVATE name = "number_of_serial_units" value="2" type="INTEGER" enable="0" />
-- Retrieval info: <PRIVATE name = "data_storage" value="Logic Cells" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "coefficient_storage" value="Logic Cells" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "multiplier_storage" value="Logic Cells" type="STRING" enable="0" />
-- Retrieval info: <PRIVATE name = "force_non_symmetric_structure" value="0" type="BOOLEAN" enable="0" />
-- Retrieval info: <PRIVATE name = "coefficients_reload" value="0" type="BOOLEAN" enable="0" />
-- Retrieval info: <PRIVATE name = "coefficients_reload_sgl_clock" value="0" type="BOOLEAN" enable="1" />
-- Retrieval info: <PRIVATE name = "max_clocks_to_compute" value="1" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "set_1" value="Low Pass Set, Floating, Band Pass, Hanning, 32, 1.5E8, 1.5E7, 5.5E7, 0, -1.12474E-4, 4.74116E-4, -0.00209712, -0.00527236, 9.87553E-4, -0.00989875, 0.00532489, 0.0263621, 0.0, 0.0480273, 0.0178911, -0.0654593, 0.0137166, -0.180396, -0.232389, 0.384014, 0.384014, -0.232389, -0.180396, 0.0137166, -0.0654593, 0.0178911, 0.0480273, 0.0, 0.0263621, 0.00532489, -0.00989875, 9.87553E-4, -0.00527236, -0.00209712, 4.74116E-4, -1.12474E-4" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "number_of_sets" value="1" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "output_full_bit_width" value="25" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "output_full_bits_right_of_binary_point" value="21" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "coefficient_reload_bit_width" value="14" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "logic_cell" value="2584" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "m512" value="0" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "m4k" value="0" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "m144k" value="0" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "m9k" value="0" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "m20k" value="0" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "mlab" value="0" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "megaram" value="0" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "dsp_block" value="0" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "input_clock_period" value="1" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "output_clock_period" value="1" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "throughput" value="1" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "memory_units" value="0" type="INTEGER" enable="1" />
-- Retrieval info: </NAMESPACE>
-- Retrieval info: <NAMESPACE name = "simgen_enable">
-- Retrieval info: <PRIVATE name = "matlab_enable" value="1" type="BOOLEAN" enable="1" />
-- Retrieval info: <PRIVATE name = "testbench_enable" value="1" type="BOOLEAN" enable="1" />
-- Retrieval info: <PRIVATE name = "testbench_simulation_clock_period" value="10.0" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "language" value="VHDL" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "enabled" value="0" type="BOOLEAN" enable="1" />
-- Retrieval info: </NAMESPACE>
-- Retrieval info: <NAMESPACE name = "simgen">
-- Retrieval info: <PRIVATE name = "filename" value="fir_band_pass.vho" type="STRING" enable="1" />
-- Retrieval info: </NAMESPACE>
-- Retrieval info: <NAMESPACE name = "quartus_settings">
-- Retrieval info: <PRIVATE name = "DEVICE" value="EP2S60F672I4" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "FAMILY" value="Stratix II" type="STRING" enable="1" />
-- Retrieval info: </NAMESPACE>
-- Retrieval info: <NAMESPACE name = "serializer"/>
-- Retrieval info: </PRIVATES>
-- Retrieval info: <FILES/>
-- Retrieval info: <PORTS/>
-- Retrieval info: <LIBRARIES/>
-- Retrieval info: </STATIC_SECTION>
-- Retrieval info: </NETLIST_SECTION>
-- Retrieval info: </MEGACORE>
-- =========================================================
|
apache-2.0
|
wsoltys/AtomFpga
|
src/AVR8/uC/BusMastCompPack.vhd
|
4
|
4467
|
--************************************************************************************************
-- Component declarations for AVR core (Bus Masters)
-- Version 0.3
-- Designed by Ruslan Lepetenok
-- Modified 04.08.2005
--************************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
package BusMastCompPack is
component uart_dma_top is port(
-- Clock and reset
ireset : in std_logic;
cp2 : in std_logic;
-- Data memory i/f (Slave part)
stb_IO : in std_logic; -- SE
stb_module : in std_logic; -- SE
sramadr : in std_logic_vector(3 downto 0); -- ??
sramre : in std_logic;
sramwe : in std_logic;
sram_dbus_out : out std_logic_vector(7 downto 0);
sram_dbus_in : in std_logic_vector(7 downto 0);
sram_dbus_out_en : out std_logic;
-- Data memory i/f (Master part)
mramadr : out std_logic_vector(15 downto 0);
mramre : out std_logic;
mramwe : out std_logic;
mram_dbus_out : in std_logic_vector(7 downto 0);
mram_dbus_in : out std_logic_vector(7 downto 0);
mack : in std_logic;
-- UART related ports
adr : in std_logic_vector(5 downto 0);
dbus_in : in std_logic_vector(7 downto 0);
dbus_out : out std_logic_vector(7 downto 0);
iore : in std_logic;
iowe : in std_logic;
out_en : out std_logic;
-- Interrupts
txcirq : out std_logic;
txc_irqack : in std_logic;
udreirq : out std_logic;
udreirq_ack : in std_logic;
rxcirq : out std_logic;
rxcirq_ack : in std_logic;
-- Wake up IRQ
wupirq : out std_logic;
wup_irqack : in std_logic;
-- External connections
rxd : in std_logic;
txd : out std_logic;
rx_en : out std_logic;
tx_en : out std_logic;
-- IE status
ie_stat : out std_logic_vector(4 downto 0)
);
end component;
component aescmdi_top is port(
-- Clock and reset
cp2 : in std_logic;
ireset : in std_logic;
-- RAM interface (Slave part)
--ssel : in std_logic;
stb_IO : in std_logic;
stb_module : in std_logic;
sramadr : in std_logic_vector(3 downto 0); -- ??
sramre : in std_logic;
sramwe : in std_logic;
sram_dbus_out : out std_logic_vector(7 downto 0);
sram_dbus_in : in std_logic_vector(7 downto 0);
sram_dbus_out_en : out std_logic;
-- RAM interface (Master part)
mramadr : out std_logic_vector(15 downto 0);
mramre : out std_logic;
mramwe : out std_logic;
mram_dbus_out : in std_logic_vector(7 downto 0);
mram_dbus_in : out std_logic_vector(7 downto 0);
mack : in std_logic;
-- Interrupt support
aes_irq : out std_logic;
aes_irqack : in std_logic
);
end component;
end BusMastCompPack;
|
apache-2.0
|
takeshineshiro/fpga_fibre_scan
|
HUCB2P0_150701/frontend/r2p_CordicPipe.vhd
|
1
|
3882
|
--
-- file: r2p_CordicPipe.vhd
-- author: Richard Herveille
-- rev. 1.0 initial release
-- rev. 1.1 March 19th, 2001. Richard Herveille. Changed function Delta, it is compatible with Xilinx WebPack software now
-- rev. 1.2 May 18th, 2001. Richard Herveille. Added documentation to function ATAN (by popular request).
-- rev. 1.3 June 4th, 2001. Richard Herveille. Revised design (made it simpler and easier to understand).
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity r2p_CordicPipe is
generic(
WIDTH : natural := 16;
PIPEID : natural := 1
);
port(
clk : in std_logic;
ena : in std_logic;
Xi : in signed(WIDTH -1 downto 0);
Yi : in signed(WIDTH -1 downto 0);
Zi : in signed(19 downto 0);
Xo : out signed(WIDTH -1 downto 0);
Yo : out signed(WIDTH -1 downto 0);
Zo : out signed(19 downto 0)
);
end entity r2p_CordicPipe;
architecture dataflow of r2p_CordicPipe is
--
-- functions
--
-- Function CATAN (constante arc-tangent).
-- This is a lookup table containing pre-calculated arc-tangents.
-- 'n' is the number of the pipe, returned is a 20bit arc-tangent value.
-- The numbers are calculated as follows: Z(n) = atan(1/2^n)
-- examples:
-- 20bit values => 2^20 = 2pi(rad)
-- 1(rad) = 2^20/2pi = 166886.053....
-- n:1, atan(1/2) = 0.4636...(rad)
-- 0.4636... * 166886.053... = 77376.32(dec) = 12E40(hex)
-- n:2, atan(1/4) = 0.2449...(rad)
-- 0.2449... * 166886.053... = 40883.52(dec) = 9FB3(hex)
-- n:3, atan(1/8) = 0.1243...(rad)
-- 0.1243... * 166886.053... = 20753.11(dec) = 5111(hex)
--
function CATAN(n :natural) return integer is
variable result :integer;
begin
case n is
when 0 => result := 16#020000#;
when 1 => result := 16#012E40#;
when 2 => result := 16#09FB4#;
when 3 => result := 16#05111#;
when 4 => result := 16#028B1#;
when 5 => result := 16#0145D#;
when 6 => result := 16#0A2F#;
when 7 => result := 16#0518#;
when 8 => result := 16#028C#;
when 9 => result := 16#0146#;
when 10 => result := 16#0A3#;
when 11 => result := 16#051#;
when 12 => result := 16#029#;
when 13 => result := 16#014#;
when 14 => result := 16#0A#;
when 15 => result := 16#05#;
when 16 => result := 16#03#;
when 17 => result := 16#01#;
when others => result := 16#0#;
end case;
return result;
end CATAN;
-- function Delta is actually an arithmatic shift right
-- This strange construction is needed for compatibility with Xilinx WebPack
function Delta(Arg : signed; Cnt : natural) return signed is
variable tmp : signed(Arg'range);
constant lo : integer := Arg'high -cnt +1;
begin
for n in Arg'high downto lo loop
tmp(n) := Arg(Arg'high);
end loop;
for n in Arg'high -cnt downto 0 loop
tmp(n) := Arg(n +cnt);
end loop;
return tmp;
end function Delta;
function AddSub(dataa, datab : in signed; add_sub : in std_logic) return signed is
begin
if (add_sub = '1') then
return dataa + datab;
else
return dataa - datab;
end if;
end;
--
-- ARCHITECTURE BODY
--
signal dX, Xresult : signed(WIDTH -1 downto 0);
signal dY, Yresult : signed(WIDTH -1 downto 0);
signal atan, Zresult : signed(19 downto 0);
signal Yneg, Ypos : std_logic;
begin
dX <= Delta(Xi, PIPEID);
dY <= Delta(Yi, PIPEID);
atan <= conv_signed( catan(PIPEID), 20); -- Angle can not be negative, catan never returns a negative value, so conv_signed can be used
-- generate adder structures
Yneg <= Yi(WIDTH -1);
Ypos <= not Yi(WIDTH -1);
-- xadd
Xresult <= AddSub(Xi, dY, YPos);
-- yadd
Yresult <= AddSub(Yi, dX, Yneg);
-- zadd
Zresult <= AddSub(Zi, atan, Ypos);
gen_regs: process(clk)
begin
if(clk'event and clk='1') then
if (ena = '1') then
Xo <= Xresult;
Yo <= Yresult;
Zo <= Zresult;
end if;
end if;
end process;
end architecture dataflow;
|
apache-2.0
|
wsoltys/AtomFpga
|
src/Atomic_top.vhd
|
1
|
6684
|
--------------------------------------------------------------------------------
-- Copyright (c) 2009 Alan Daly. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ /
-- \ \ \/
-- \ \
-- / / Filename : Atomic_top.vhf
-- /___/ /\ Timestamp : 02/03/2013 06:17:50
-- \ \ / \
-- \___\/\___\
--
--Design Name: Atomic_top
--Device: spartan3A
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity Atomic_top is
port (clk_25M00 : in std_logic;
ps2_clk : in std_logic;
ps2_data : in std_logic;
ERSTn : in std_logic;
red : out std_logic_vector (2 downto 0);
green : out std_logic_vector (2 downto 0);
blue : out std_logic_vector (2 downto 0);
vsync : out std_logic;
hsync : out std_logic;
CE1 : out std_logic;
RAMWRn : out std_logic;
RAMOEn : out std_logic;
RamA : out std_logic_vector (15 downto 0);
RamD : inout std_logic_vector (15 downto 0);
audiol : out std_logic;
audioR : out std_logic;
SDMISO : in std_logic;
SDSS : out std_logic;
SDCLK : out std_logic;
SDMOSI : out std_logic);
end Atomic_top;
architecture behavioral of Atomic_top is
component dcm2
port (
CLKIN_IN : in std_logic;
CLK0_OUT : out std_logic;
CLK0_OUT1 : out std_logic;
CLK2X_OUT : out std_logic
);
end component;
component dcm3
port (CLKIN_IN : in std_logic;
CLK0_OUT : out std_logic;
CLK0_OUT1 : out std_logic;
CLK2X_OUT : out std_logic
);
end component;
component InternalROM
port (
CLK : in std_logic;
ADDR : in std_logic_vector(16 downto 0);
DATA : out std_logic_vector(7 downto 0)
);
end component;
component Atomic_core
generic (
CImplSDDOS : boolean;
CImplGraphicsExt : boolean;
CImplSoftChar : boolean;
CImplSID : boolean;
CImplVGA80x40 : boolean;
CImplHWScrolling : boolean;
CImplMouse : boolean;
CImplUart : boolean;
MainClockSpeed : integer;
DefaultBaud : integer
);
port (
clk_vga : in std_logic;
clk_16M00 : in std_logic;
clk_32M00 : in std_logic;
ps2_clk : in std_logic;
ps2_data : in std_logic;
ps2_mouse_clk : inout std_logic;
ps2_mouse_data : inout std_logic;
ERSTn : in std_logic;
IRSTn : out std_logic;
SDMISO : in std_logic;
red : out std_logic_vector(2 downto 0);
green : out std_logic_vector(2 downto 0);
blue : out std_logic_vector(2 downto 0);
vsync : out std_logic;
hsync : out std_logic;
RamCE : out std_logic;
RomCE : out std_logic;
Phi2 : out std_logic;
ExternWE : out std_logic;
ExternA : out std_logic_vector (16 downto 0);
ExternDin : out std_logic_vector (7 downto 0);
ExternDout: in std_logic_vector (7 downto 0);
audiol : out std_logic;
audioR : out std_logic;
SDSS : out std_logic;
SDCLK : out std_logic;
SDMOSI : out std_logic;
uart_RxD : in std_logic;
uart_TxD : out std_logic;
LED1 : out std_logic;
LED2 : out std_logic
);
end component;
signal clk_12M58 : std_logic;
signal clk_16M00 : std_logic;
signal clk_32M00 : std_logic;
signal Phi2 : std_logic;
signal RomDout : std_logic_vector (7 downto 0);
signal RamCE : std_logic;
signal RomCE : std_logic;
signal ExternA : std_logic_vector (16 downto 0);
signal ExternWE : std_logic;
signal ExternDin : std_logic_vector (7 downto 0);
signal ExternDout : std_logic_vector (7 downto 0);
begin
inst_dcm2 : dcm2 port map(
CLKIN_IN => clk_25M00,
CLK0_OUT => clk_16M00,
CLK0_OUT1 => open,
CLK2X_OUT => open);
inst_dcm3 : dcm3 port map (
CLKIN_IN => clk_16M00,
CLK0_OUT => clk_32M00,
CLK0_OUT1 => open,
CLK2X_OUT => open);
rom_c000_ffff : InternalROM port map(
CLK => clk_16M00,
ADDR => ExternA,
DATA => RomDout
);
inst_Atomic_core : Atomic_core
generic map (
CImplSDDOS => true,
CImplGraphicsExt => false,
CImplSoftChar => false,
CImplSID => true,
CImplVGA80x40 => false,
CImplHWScrolling => false,
CImplMouse => false,
CImplUart => false,
MainClockSpeed => 16000000,
DefaultBaud => 115200
)
port map(
clk_vga => clk_25M00,
clk_16M00 => clk_16M00,
clk_32M00 => clk_32M00,
ps2_clk => ps2_clk,
ps2_data => ps2_data,
ps2_mouse_clk => open,
ps2_mouse_data => open,
ERSTn => ERSTn,
IRSTn => open,
red => red,
green => green,
blue => blue,
vsync => vsync,
hsync => hsync,
RamCE => RamCE,
RomCE => RomCE,
Phi2 => Phi2,
ExternWE => ExternWE,
ExternA => ExternA,
ExternDin => ExternDin,
ExternDout => ExternDout,
audiol => audiol,
audioR => audioR,
SDMISO => SDMISO,
SDSS => SDSS,
SDCLK => SDCLK,
SDMOSI => SDMOSI,
uart_RxD => '1',
uart_TxD => open,
LED1 => open,
LED2 => open
);
CE1 <= not RAMCE;
RAMWRn <= not (ExternWE and Phi2);
RAMOEn <= not RAMCE;
RamD <= ExternDin & ExternDin when ExternWE = '1' else "ZZZZZZZZZZZZZZZZ";
ExternDout <= RamD(7 downto 0) when RamCE = '1' else
RomDout when RomCE = '1' else
"11110001";
RamA <= '0' & ExternA(14 downto 0);
end behavioral;
|
apache-2.0
|
wsoltys/AtomFpga
|
src/AVR8/spi_mod/spi_mod.vhd
|
4
|
20772
|
--**********************************************************************************************
-- SPI Peripheral for the AVR Core
-- Version 1.2
-- Modified 10.01.2007
-- Designed by Ruslan Lepetenok
-- Internal resynchronizers for scki and ss_b inputs were added
--**********************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use WORK.std_library.all;
use WORK.avr_adr_pack.all;
use WORK.rsnc_comp_pack.all;
entity spi_mod is port(
-- AVR Control
ireset : in std_logic;
cp2 : in std_logic;
adr : in std_logic_vector(15 downto 0);
dbus_in : in std_logic_vector(7 downto 0);
dbus_out : out std_logic_vector(7 downto 0);
iore : in std_logic;
iowe : in std_logic;
out_en : out std_logic;
-- SPI i/f
misoi : in std_logic;
mosii : in std_logic;
scki : in std_logic; -- Resynch
ss_b : in std_logic; -- Resynch
misoo : out std_logic;
mosio : out std_logic;
scko : out std_logic;
spe : out std_logic;
spimaster : out std_logic;
-- IRQ
spiirq : out std_logic;
spiack : in std_logic;
-- Slave Programming Mode
por : in std_logic;
spiextload : in std_logic;
spidwrite : out std_logic;
spiload : out std_logic
);
end spi_mod;
architecture RTL of spi_mod is
-- Resynch
signal scki_resync : std_logic;
signal ss_b_resync : std_logic;
-- Registers
signal SPCR : std_logic_vector(7 downto 0);
alias SPIE : std_logic is SPCR(7);
alias SPEB : std_logic is SPCR(6); -- SPE in Atmel's doc
alias DORD : std_logic is SPCR(5);
alias MSTR : std_logic is SPCR(4);
alias CPOL : std_logic is SPCR(3);
alias CPHA : std_logic is SPCR(2);
alias SPR : std_logic_vector(1 downto 0) is SPCR(1 downto 0);
signal SPSR : std_logic_vector(7 downto 0);
alias SPIF : std_logic is SPSR(7);
alias WCOL : std_logic is SPSR(6);
alias SPI2X : std_logic is SPSR(0);
signal SPIE_Next : std_logic;
signal SPEB_Next : std_logic;
signal DORD_Next : std_logic;
signal CPOL_Next : std_logic;
signal CPHA_Next : std_logic;
signal SPR_Next : std_logic_vector(SPR'range);
signal SPI2X_Next : std_logic;
signal SPDR_Rc : std_logic_vector(7 downto 0);
signal SPDR_Rc_Next : std_logic_vector(7 downto 0);
signal SPDR_Sh_Current : std_logic_vector(7 downto 0);
signal SPDR_Sh_Next : std_logic_vector(7 downto 0);
signal Div_Next : std_logic_vector(5 downto 0);
signal Div_Current : std_logic_vector(5 downto 0);
signal Div_Toggle : std_logic;
signal DivCntMsb_Current : std_logic;
signal DivCntMsb_Next : std_logic;
type MstSMSt_Type is (MstSt_Idle,MstSt_B0,MstSt_B1,MstSt_B2,MstSt_B3,MstSt_B4,MstSt_B5,MstSt_B6,MstSt_B7);
signal MstSMSt_Current : MstSMSt_Type;
signal MstSMSt_Next : MstSMSt_Type;
signal TrStart : std_logic;
signal scko_Next : std_logic;
signal scko_Current : std_logic; --!!!
signal UpdRcDataRg_Current : std_logic;
signal UpdRcDataRg_Next : std_logic;
signal TmpIn_Current : std_logic;
signal TmpIn_Next : std_logic;
-- Slave
signal sck_EdgeDetDFF : std_logic;
signal SlvSampleSt : std_logic;
signal SlvSMChangeSt : std_logic;
type SlvSMSt_Type is (SlvSt_Idle,SlvSt_B0I,SlvSt_B0,SlvSt_B1,SlvSt_B2,SlvSt_B3,SlvSt_B4,SlvSt_B5,SlvSt_B6,SlvSt_B6W);
signal SlvSMSt_Current : SlvSMSt_Type;
signal SlvSMSt_Next : SlvSMSt_Type;
-- SIF clear SM
signal SPIFClrSt_Current : std_logic;
signal SPIFClrSt_Next : std_logic;
-- WCOL clear SM
signal WCOLClrSt_Current : std_logic;
signal WCOLClrSt_Next : std_logic;
signal MSTR_Next : std_logic;
signal SPIF_Next : std_logic;
signal WCOL_Next : std_logic;
signal MstDSamp_Next : std_logic;
signal MstDSamp_Current : std_logic;
function Fn_RevBitVector(InVector : std_logic_vector) return std_logic_vector is
variable TmpVect : std_logic_vector(InVector'range);
begin
for i in TmpVect'range loop
TmpVect(i) := InVector(InVector'high-i);
end loop;
return TmpVect;
end Fn_RevBitVector;
begin
-- ******************** Resynchronizers ************************************
scki_resync_inst:component rsnc_bit generic map(
add_stgs_num => 0,
inv_f_stgs => 0
)
port map(
clk => cp2,
di => scki,
do => scki_resync
);
ss_b_resync_inst:component rsnc_bit generic map(
add_stgs_num => 0,
inv_f_stgs => 0
)
port map(
clk => cp2,
di => ss_b,
do => ss_b_resync
);
-- ******************** Resynchronizers ************************************
SeqPrc:process(ireset,cp2)
begin
if (ireset='0') then -- Reset
SPCR <= (others => '0');
SPIF <= '0';
WCOL <= '0';
SPI2X <= '0';
Div_Current <= (others => '0');
DivCntMsb_Current <= '0';
MstSMSt_Current <= MstSt_Idle;
SlvSMSt_Current <= SlvSt_Idle;
SPDR_Sh_Current <= (others => '1');
SPDR_Rc <= (others => '0');
sck_EdgeDetDFF <= '0';
SPIFClrSt_Current <= '0';
WCOLClrSt_Current <= '0';
scko <= '0';
scko_Current <= '0';
misoo <= '0';
mosio <= '0';
TmpIn_Current <= '0';
UpdRcDataRg_Current <= '0';
MstDSamp_Current <= '0';
elsif (cp2='1' and cp2'event) then -- Clock
SPIE <= SPIE_Next;
SPEB <= SPEB_Next;
DORD <= DORD_Next;
CPOL <= CPOL_Next;
CPHA <= CPHA_Next;
SPR <= SPR_Next;
MSTR <= MSTR_Next;
SPIF <= SPIF_Next;
SPI2X <= SPI2X_Next;
WCOL <= WCOL_Next;
Div_Current <= Div_Next;
DivCntMsb_Current <= DivCntMsb_Next;
MstSMSt_Current <= MstSMSt_Next;
SlvSMSt_Current <= SlvSMSt_Next;
SPDR_Sh_Current <= SPDR_Sh_Next;
SPDR_Rc <= SPDR_Rc_Next;
sck_EdgeDetDFF <= scki_resync;
SPIFClrSt_Current <= SPIFClrSt_Next;
WCOLClrSt_Current <= WCOLClrSt_Next;
scko_Current <= scko_Next;
scko <= scko_Next;
misoo <= SPDR_Sh_Next(SPDR_Sh_Next'high);
mosio <= SPDR_Sh_Next(SPDR_Sh_Next'high);
TmpIn_Current <= TmpIn_Next;
UpdRcDataRg_Current <= UpdRcDataRg_Next;
MstDSamp_Current <= MstDSamp_Next;
end if;
end process;
IORegWriteComb:process(adr,iowe,SPCR,SPSR,dbus_in)
begin
SPIE_Next <= SPIE;
SPEB_Next <= SPEB;
DORD_Next <= DORD;
CPOL_Next <= CPOL;
CPHA_Next <= CPHA;
SPR_Next <= SPR;
SPI2X_Next <= SPI2X;
if(fn_to_integer(adr)=SPCR_Address and iowe='1') then
SPIE_Next <= dbus_in(7);
SPEB_Next <= dbus_in(6);
DORD_Next <= dbus_in(5);
CPOL_Next <= dbus_in(3);
CPHA_Next <= dbus_in(2);
SPR_Next <= dbus_in(1 downto 0);
end if;
if(fn_to_integer(adr)=SPSR_Address and iowe='1') then
SPI2X_Next <= dbus_in(0);
end if;
end process;
SPSR(5 downto 1) <= (others => '0');
-- Divider
-- SPI2X | SPR1 | SPR0 | SCK Frequency
-- 0 | 0 | 0 | fosc /4 (2)
-- 0 | 0 | 1 | fosc /16 (8)
-- 0 | 1 | 0 | fosc /64 (32)
-- 0 | 1 | 1 | fosc /128 (64)
-- ------+------+------+-------------
-- 1 | 0 | 0 | fosc /2 (1)
-- 1 | 0 | 1 | fosc /8 (4)
-- 1 | 1 | 0 | fosc /32 (16)
-- 1 | 1 | 1 | fosc /64 (32)
DividerToggleComb:process(MstSMSt_Current,Div_Current,SPCR,SPSR)
begin
Div_Toggle <= '0';
if(MstSMSt_Current /= MstSt_Idle) then
if(SPI2X='1') then -- Extended mode
case SPR is
when "00" => if (Div_Current="000001") then Div_Toggle <= '1'; end if; -- fosc /2
when "01" => if (Div_Current="000011") then Div_Toggle <= '1'; end if; -- fosc /8
when "10" => if (Div_Current="001111") then Div_Toggle <= '1'; end if; -- fosc /32
when "11" => if (Div_Current="011111") then Div_Toggle <= '1'; end if; -- fosc /64
when others => Div_Toggle <= '0';
end case;
else -- Normal mode
case SPR is
when "00" => if (Div_Current="000001") then Div_Toggle <= '1'; end if; -- fosc /4
when "01" => if (Div_Current="000111") then Div_Toggle <= '1'; end if; -- fosc /16
when "10" => if (Div_Current="011111") then Div_Toggle <= '1'; end if; -- fosc /64
when "11" => if (Div_Current="111111") then Div_Toggle <= '1'; end if; -- fosc /128
when others => Div_Toggle <= '0';
end case;
end if;
end if;
end process;
DividerNextComb:process(MstSMSt_Current,Div_Current,DivCntMsb_Current,Div_Toggle)
begin
Div_Next <= Div_Current;
DivCntMsb_Next <= DivCntMsb_Current;
if(MstSMSt_Current /= MstSt_Idle) then
if(Div_Toggle='1') then
Div_Next <= (others => '0');
DivCntMsb_Next <= not DivCntMsb_Current;
else
Div_Next <= Div_Current + 1;
end if;
end if;
end process;
TrStart <= '1' when (fn_to_integer(adr)=SPDR_Address and iowe='1' and SPEB='1') else '0';
-- Transmitter Master Mode Shift Control SM
MstSmNextComb:process(MstSMSt_Current,DivCntMsb_Current,Div_Toggle,TrStart,SPCR)
begin
MstSMSt_Next <= MstSMSt_Current;
case MstSMSt_Current is
when MstSt_Idle =>
if(TrStart='1' and MSTR='1') then
MstSMSt_Next <= MstSt_B0;
end if;
when MstSt_B0 =>
if(DivCntMsb_Current='1' and Div_Toggle='1') then
MstSMSt_Next <= MstSt_B1;
end if;
when MstSt_B1 =>
if(DivCntMsb_Current='1' and Div_Toggle='1') then
MstSMSt_Next <= MstSt_B2;
end if;
when MstSt_B2 =>
if(DivCntMsb_Current='1' and Div_Toggle='1') then
MstSMSt_Next <= MstSt_B3;
end if;
when MstSt_B3 =>
if(DivCntMsb_Current='1' and Div_Toggle='1') then
MstSMSt_Next <= MstSt_B4;
end if;
when MstSt_B4 =>
if(DivCntMsb_Current='1' and Div_Toggle='1') then
MstSMSt_Next <= MstSt_B5;
end if;
when MstSt_B5 =>
if(DivCntMsb_Current='1' and Div_Toggle='1') then
MstSMSt_Next <= MstSt_B6;
end if;
when MstSt_B6 =>
if(DivCntMsb_Current='1' and Div_Toggle='1') then
MstSMSt_Next <= MstSt_B7;
end if;
when MstSt_B7 =>
if(DivCntMsb_Current='1' and Div_Toggle='1') then
MstSMSt_Next <= MstSt_Idle;
end if;
when others => MstSMSt_Next <= MstSt_Idle;
end case;
end process;
SPIFClrCombProc:process(SPIFClrSt_Current,SPCR,SPSR,adr,iore,iowe)
begin
SPIFClrSt_Next <= SPIFClrSt_Current;
case SPIFClrSt_Current is
when '0' =>
if(fn_to_integer(adr)=SPSR_Address and iore='1' and SPIF='1' and SPEB='1') then
SPIFClrSt_Next <= '1';
end if;
when '1' =>
if(fn_to_integer(adr)=SPDR_Address and (iore='1' or iowe='1')) then
SPIFClrSt_Next <= '0';
end if;
when others => SPIFClrSt_Next <= SPIFClrSt_Current;
end case;
end process; --SPIFClrCombProc
WCOLClrCombProc:process(WCOLClrSt_Current,SPSR,adr,iore,iowe)
begin
WCOLClrSt_Next <= WCOLClrSt_Current;
case WCOLClrSt_Current is
when '0' =>
if(fn_to_integer(adr)=SPSR_Address and iore='1' and WCOL='1') then
WCOLClrSt_Next <= '1';
end if;
when '1' =>
if(fn_to_integer(adr)=SPDR_Address and (iore='1' or iowe='1')) then
WCOLClrSt_Next <= '0';
end if;
when others => WCOLClrSt_Next <= WCOLClrSt_Current;
end case;
end process; --WCOLClrCombProc
MstDataSamplingComb:process(SPCR,scko_Current,scko_Next,MstDSamp_Current,MstSMSt_Current)
begin
MstDSamp_Next <= '0';
case MstDSamp_Current is
when '0' =>
if(MstSMSt_Current/=MstSt_Idle) then
if(CPHA=CPOL) then
if(scko_Next='1' and scko_Current='0') then -- Rising edge
MstDSamp_Next <= '1';
end if;
else -- CPHA/=CPOL
if(scko_Next='0' and scko_Current='1') then -- Falling edge
MstDSamp_Next <= '1';
end if;
end if;
end if;
when '1' => MstDSamp_Next <= '0';
when others => MstDSamp_Next <= '0';
end case;
end process; -- MstDataSamplingComb
--
DRLatchComb:process(UpdRcDataRg_Current,MstSMSt_Current,MstSMSt_Next,SlvSMSt_Current,SlvSMSt_Next,SPCR)
begin
UpdRcDataRg_Next <= '0';
case UpdRcDataRg_Current is
when '0' =>
if((MSTR='1' and MstSMSt_Current/=MstSt_Idle and MstSMSt_Next=MstSt_Idle)or
(MSTR='0' and SlvSMSt_Current/=SlvSt_Idle and SlvSMSt_Next=SlvSt_Idle)) then
UpdRcDataRg_Next <= '1';
end if;
when '1' => UpdRcDataRg_Next <= '0';
when others => UpdRcDataRg_Next <= '0';
end case;
end process;
TmpInComb:process(TmpIn_Current,mosii,misoi,MstDSamp_Current,SlvSampleSt,SPCR,ss_b_resync)
begin
TmpIn_Next <= TmpIn_Current;
if(MSTR='1' and MstDSamp_Current='1') then -- Master mode
TmpIn_Next <= misoi;
elsif(MSTR='0' and SlvSampleSt='1' and ss_b_resync='0') then -- Slave mode ???
TmpIn_Next <= mosii;
end if;
end process;
ShiftRgComb:process(MstSMSt_Current,SlvSMSt_Current,SPDR_Sh_Current,SPCR,DivCntMsb_Current,Div_Toggle,TrStart,dbus_in,ss_b_resync,TmpIn_Current,SlvSMChangeSt,SlvSampleSt,UpdRcDataRg_Current)
begin
SPDR_Sh_Next <= SPDR_Sh_Current;
if(TrStart='1' and (MstSMSt_Current=MstSt_Idle and SlvSMSt_Current = SlvSt_Idle and not(MSTR='0' and SlvSampleSt='1' and ss_b_resync='0') )) then -- Load
if (DORD='1') then -- the LSB of the data word is transmitted first
SPDR_Sh_Next <= Fn_RevBitVector(dbus_in);
else -- the MSB of the data word is transmitted first
SPDR_Sh_Next <= dbus_in;
end if;
elsif(MSTR='1' and UpdRcDataRg_Current='1') then -- ???
SPDR_Sh_Next(SPDR_Sh_Next'high) <= '1';
elsif((MSTR='1' and MstSMSt_Current/=MstSt_Idle and DivCntMsb_Current='1' and Div_Toggle='1') or
(MSTR='0' and SlvSMSt_Current/=SlvSt_Idle and SlvSMChangeSt='1' and ss_b_resync='0')) then
-- Shift
SPDR_Sh_Next <= SPDR_Sh_Current(SPDR_Sh_Current'high-1 downto SPDR_Sh_Current'low)&TmpIn_Current;
end if;
end process; --ShiftRgComb
sckoGenComb:process(scko_Current,SPCR,adr,iowe,dbus_in,DivCntMsb_Next,DivCntMsb_Current,TrStart,MstSMSt_Current,MstSMSt_Next)
begin
scko_Next <= scko_Current;
if(fn_to_integer(adr)=SPCR_Address and iowe='1') then -- Write to SPCR
scko_Next <= dbus_in(3); -- CPOL
elsif(TrStart='1' and CPHA='1' and MstSMSt_Current=MstSt_Idle) then
scko_Next <= not CPOL;
elsif(MstSMSt_Current/=MstSt_Idle and MstSMSt_Next=MstSt_Idle) then -- "Parking"
scko_Next <= CPOL;
elsif(MstSMSt_Current/=MstSt_Idle and DivCntMsb_Current/=DivCntMsb_Next) then
scko_Next <= not scko_Current;
end if;
end process;
-- Receiver data register
SPDRRcComb:process(SPDR_Rc,SPCR,SPDR_Sh_Current,UpdRcDataRg_Current,TmpIn_Current)
begin
SPDR_Rc_Next <= SPDR_Rc;
if(UpdRcDataRg_Current='1') then
if(MSTR='0' and CPHA='1') then
if (DORD='1') then -- the LSB of the data word is transmitted first
SPDR_Rc_Next <= Fn_RevBitVector(SPDR_Sh_Current(SPDR_Sh_Current'high-1 downto 0)&TmpIn_Current);
else -- the MSB of the data word is transmitted first
SPDR_Rc_Next <= SPDR_Sh_Current(SPDR_Sh_Current'high-1 downto 0)&TmpIn_Current;
end if;
else
if (DORD='1') then -- the LSB of the data word is transmitted first
SPDR_Rc_Next <= Fn_RevBitVector(SPDR_Sh_Current);
else -- the MSB of the data word is transmitted first
SPDR_Rc_Next <= SPDR_Sh_Current;
end if;
end if;
end if;
end process;
--****************************************************************************************
-- Slave
--****************************************************************************************
SlvSampleSt <= '1' when ((sck_EdgeDetDFF='0' and scki_resync='1' and CPOL=CPHA)or -- Rising edge
(sck_EdgeDetDFF='1' and scki_resync='0' and CPOL/=CPHA))else '0'; -- Falling edge
SlvSMChangeSt <= '1' when ((sck_EdgeDetDFF='1' and scki_resync='0' and CPOL=CPHA)or -- Falling edge
(sck_EdgeDetDFF='0' and scki_resync='1' and CPOL/=CPHA))else '0'; -- Rising edge
-- Slave Master Mode Shift Control SM
SlvSMNextComb:process(SlvSMSt_Current,SPCR,SlvSampleSt,SlvSMChangeSt,ss_b_resync)
begin
SlvSMSt_Next <= SlvSMSt_Current;
if(ss_b_resync='0') then
case SlvSMSt_Current is
when SlvSt_Idle =>
if(MSTR='0') then
if(CPHA='1') then
if(SlvSMChangeSt='1') then
SlvSMSt_Next <= SlvSt_B0;
end if;
else -- CPHA='0'
if(SlvSampleSt='1') then
SlvSMSt_Next <= SlvSt_B0I;
end if;
end if;
end if;
when SlvSt_B0I =>
if(SlvSMChangeSt='1') then
SlvSMSt_Next <= SlvSt_B0;
end if;
when SlvSt_B0 =>
if(SlvSMChangeSt='1') then
SlvSMSt_Next <= SlvSt_B1;
end if;
when SlvSt_B1 =>
if(SlvSMChangeSt='1') then
SlvSMSt_Next <= SlvSt_B2;
end if;
when SlvSt_B2 =>
if(SlvSMChangeSt='1') then
SlvSMSt_Next <= SlvSt_B3;
end if;
when SlvSt_B3 =>
if(SlvSMChangeSt='1') then
SlvSMSt_Next <= SlvSt_B4;
end if;
when SlvSt_B4 =>
if(SlvSMChangeSt='1') then
SlvSMSt_Next <= SlvSt_B5;
end if;
when SlvSt_B5 =>
if(SlvSMChangeSt='1') then
SlvSMSt_Next <= SlvSt_B6;
end if;
when SlvSt_B6 =>
if(SlvSMChangeSt='1') then
if(CPHA='0') then
SlvSMSt_Next <= SlvSt_Idle;
else -- CPHA='1'
SlvSMSt_Next <= SlvSt_B6W;
end if;
end if;
when SlvSt_B6W =>
if(SlvSampleSt='1')then
SlvSMSt_Next <= SlvSt_Idle;
end if;
when others => SlvSMSt_Next <= SlvSt_Idle;
end case;
end if;
end process;
MSTRGenComb:process(adr,iowe,dbus_in,ss_b_resync,SPCR)
begin
MSTR_Next <= MSTR;
case MSTR is
when '0' =>
if(fn_to_integer(adr)=SPCR_Address and iowe='1' and dbus_in(4)='1') then -- TBD (ss_b_resync='0')
MSTR_Next <= '1';
end if;
when '1' =>
if((fn_to_integer(adr)=SPCR_Address and iowe='1' and dbus_in(4)='0') or
(ss_b_resync='0')) then
MSTR_Next <= '0';
end if;
when others => MSTR_Next <= MSTR;
end case;
end process;
WCOLGenComb:process(WCOLClrSt_Current,SlvSMSt_Current,MstSMSt_Current,adr,iowe,iore,SPCR,SPSR,SlvSampleSt,ss_b_resync)
begin
WCOL_Next <= WCOL;
case WCOL is
when '0' =>
if(fn_to_integer(adr)=SPDR_Address and iowe='1' and
((MSTR='0' and (SlvSMSt_Current/=SlvSt_Idle or (SlvSampleSt='1' and ss_b_resync='0'))) or
(MSTR='1' and MstSMSt_Current/=MstSt_Idle))) then
WCOL_Next <= '1';
end if;
when '1' =>
if(((fn_to_integer(adr)=SPDR_Address and (iowe='1' or iore='1')) and WCOLClrSt_Current='1') and
not (fn_to_integer(adr)=SPDR_Address and iowe='1' and
((MSTR='0' and (SlvSMSt_Current/=SlvSt_Idle or (SlvSampleSt='1' and ss_b_resync='0'))) or
(MSTR='1' and MstSMSt_Current/=MstSt_Idle)))) then
WCOL_Next <= '0';
end if;
when others => WCOL_Next <= WCOL;
end case;
end process;
SPIFGenComb:process(SPIFClrSt_Current,adr,iowe,iore,SPCR,SPSR,SlvSMSt_Current,SlvSMSt_Next,MstSMSt_Current,MstSMSt_Next,spiack)
begin
SPIF_Next <= SPIF;
case SPIF is
when '0' =>
if((MSTR='0' and SlvSMSt_Current/=SlvSt_Idle and SlvSMSt_Next=SlvSt_Idle) or
(MSTR='1' and MstSMSt_Current/=MstSt_Idle and MstSMSt_Next=MstSt_Idle))then
SPIF_Next <= '1';
end if;
when '1' =>
if((fn_to_integer(adr)=SPDR_Address and (iowe='1' or iore='1') and SPIFClrSt_Current='1') or spiack='1') then
SPIF_Next <= '0';
end if;
when others => SPIF_Next <= SPIF;
end case;
end process;
--*************************************************************************************
spimaster <= MSTR;
spe <= SPEB;
-- IRQ
spiirq <= SPIE and SPIF;
OutMuxComb:process(adr,iore,SPDR_Rc,SPSR,SPCR)
begin
case(fn_to_integer(adr)) is
when SPDR_Address => dbus_out <= SPDR_Rc; out_en <= iore;
when SPSR_Address => dbus_out <= SPSR; out_en <= iore;
when SPCR_Address => dbus_out <= SPCR; out_en <= iore;
when others => dbus_out <= (others => '0'); out_en <= '0';
end case;
end process; -- OutMuxComb
--
spidwrite <= '0';
spiload <= '0';
end RTL;
|
apache-2.0
|
wsoltys/AtomFpga
|
src/AVR8/FrqDiv/FrqDiv.vhd
|
1
|
1384
|
--**********************************************************************************************
-- Frequency divider for AVR uC (40 MHz -> 4 MHz or 40 MHz -> 20 MHz)
-- Version 1.52(Dust Inc version)
-- Modified 16.01.2006
-- Designed by Ruslan Lepetenok
--**********************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use WORK.AVRuCPackage.all;
entity FrqDiv is port(
clk_in : in std_logic;
clk_out : out std_logic
);
end FrqDiv;
architecture RTL of FrqDiv is
signal DivCnt : std_logic_vector(3 downto 0);
signal clk_out_int : std_logic;
constant Div2 : boolean := TRUE;
begin
-- Must be sequentially encoded
DivideBy10:if not Div2 generate
Gen:process(clk_in)
begin
if(clk_in='1' and clk_in'event) then -- Clock
if(DivCnt=x"4") then DivCnt <= x"0";
else DivCnt <= DivCnt + 1;
end if;
if(DivCnt=x"4") then clk_out_int <= not clk_out_int;
end if;
end if;
end process;
end generate;
DivideBy10:if Div2 generate
Gen:process(clk_in)
begin
if(clk_in='1' and clk_in'event) then -- Clock
clk_out_int <= not clk_out_int;
end if;
end process;
end generate;
clk_out <= clk_out_int;
end RTL;
|
apache-2.0
|
wsoltys/AtomFpga
|
src/AVR8/MemArbAndMux/MemAccessCompPack.vhd
|
4
|
1997
|
-- *****************************************************************************************
--
-- Version 0.1
-- Modified 24.07.2005
-- Designed by Ruslan Lepetenok
-- *****************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use WORK.MemAccessCtrlPack.all;
package MemAccessCompPack is
component ArbiterAndMux is port(
--Clock and reset
ireset : in std_logic;
cp2 : in std_logic;
-- Bus masters
busmin : in MastersOutBus_Type;
busmwait : out std_logic_vector(CNumOfBusMasters-1 downto 0);
-- Memory Address,Data and Control
ramadr : out std_logic_vector(15 downto 0);
ramdout : out std_logic_vector(7 downto 0);
ramre : out std_logic;
ramwe : out std_logic;
cpuwait : in std_logic
);
end component;
component MemRdMux is port(
slv_outs : in SlavesOutBus_Type;
ram_sel : in std_logic; -- Data RAM selection(optional input)
ram_dout : in std_logic_vector(7 downto 0); -- Data memory output
dout : out std_logic_vector(7 downto 0) -- Data output
);
end component;
component RAMAdrDcd is port(
ramadr : in std_logic_vector(15 downto 0);
ramre : in std_logic;
ramwe : in std_logic;
-- Memory mapped I/O i/f
stb_IO : out std_logic;
stb_IOmod : out std_logic_vector(CNumOfSlaves-1 downto 0);
-- Data memory i/f
ram_we : out std_logic;
ram_ce : out std_logic;
ram_sel : out std_logic
);
end component;
end MemAccessCompPack;
|
apache-2.0
|
wsoltys/AtomFpga
|
src/ROM/fpgautils.vhd
|
1
|
33364
|
-- generated with romgen by MikeJ
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity fpgautils is
port (
CLK : in std_logic;
ADDR : in std_logic_vector(11 downto 0);
DATA : out std_logic_vector(7 downto 0)
);
end;
architecture RTL of fpgautils is
type ROM_ARRAY is array(0 to 4095) of std_logic_vector(7 downto 0);
constant ROM : ROM_ARRAY := (
x"40",x"BF",x"A2",x"FF",x"A4",x"5E",x"88",x"E8", -- 0x0000
x"C8",x"BD",x"3C",x"A0",x"30",x"14",x"D1",x"05", -- 0x0008
x"F0",x"F5",x"E8",x"BD",x"3B",x"A0",x"10",x"FA", -- 0x0010
x"B1",x"05",x"C9",x"2E",x"D0",x"E6",x"C8",x"CA", -- 0x0018
x"B0",x"E7",x"84",x"03",x"85",x"53",x"BD",x"3D", -- 0x0020
x"A0",x"85",x"52",x"A2",x"00",x"86",x"04",x"20", -- 0x0028
x"39",x"A0",x"A2",x"00",x"86",x"04",x"4C",x"58", -- 0x0030
x"C5",x"6C",x"52",x"00",x"46",x"48",x"45",x"4C", -- 0x0038
x"50",x"A6",x"44",x"42",x"41",x"55",x"44",x"A3", -- 0x0040
x"BC",x"53",x"49",x"4E",x"4F",x"55",x"54",x"A3", -- 0x0048
x"84",x"53",x"49",x"4E",x"A3",x"87",x"53",x"4F", -- 0x0050
x"55",x"54",x"A3",x"A2",x"55",x"50",x"4C",x"4F", -- 0x0058
x"41",x"44",x"A4",x"0A",x"44",x"4E",x"4C",x"4F", -- 0x0060
x"41",x"44",x"A4",x"3C",x"43",x"52",x"43",x"A1", -- 0x0068
x"06",x"52",x"4C",x"49",x"53",x"54",x"A6",x"BC", -- 0x0070
x"46",x"4C",x"41",x"53",x"48",x"A5",x"00",x"42", -- 0x0078
x"45",x"45",x"42",x"A6",x"2C",x"56",x"47",x"41", -- 0x0080
x"38",x"30",x"AA",x"C9",x"C5",x"58",x"00",x"3C", -- 0x0088
x"42",x"41",x"55",x"44",x"20",x"52",x"41",x"54", -- 0x0090
x"45",x"3E",x"00",x"00",x"00",x"00",x"3C",x"53", -- 0x0098
x"54",x"41",x"52",x"54",x"3E",x"2C",x"3C",x"45", -- 0x00A0
x"4E",x"44",x"3E",x"00",x"3C",x"53",x"54",x"41", -- 0x00A8
x"52",x"54",x"3E",x"00",x"3C",x"53",x"54",x"41", -- 0x00B0
x"52",x"54",x"3E",x"2C",x"3C",x"45",x"4E",x"44", -- 0x00B8
x"3E",x"00",x"00",x"3C",x"53",x"54",x"41",x"52", -- 0x00C0
x"54",x"3E",x"2C",x"3C",x"42",x"41",x"4E",x"4B", -- 0x00C8
x"3E",x"00",x"00",x"00",x"20",x"BC",x"C8",x"20", -- 0x00D0
x"31",x"C2",x"20",x"BC",x"C8",x"20",x"31",x"C2", -- 0x00D8
x"A5",x"16",x"85",x"80",x"A5",x"25",x"85",x"81", -- 0x00E0
x"A5",x"17",x"85",x"82",x"A5",x"26",x"85",x"83", -- 0x00E8
x"60",x"20",x"D1",x"F7",x"46",x"50",x"47",x"41", -- 0x00F0
x"20",x"55",x"54",x"49",x"4C",x"53",x"20",x"56", -- 0x00F8
x"30",x"2E",x"32",x"31",x"EA",x"60",x"20",x"D4", -- 0x0100
x"A0",x"A2",x"00",x"20",x"1B",x"A1",x"A5",x"89", -- 0x0108
x"20",x"02",x"F8",x"A5",x"88",x"20",x"02",x"F8", -- 0x0110
x"4C",x"ED",x"FF",x"78",x"98",x"48",x"8A",x"48", -- 0x0118
x"10",x"05",x"29",x"1F",x"8D",x"FF",x"BF",x"A5", -- 0x0120
x"80",x"85",x"84",x"A5",x"81",x"85",x"85",x"A9", -- 0x0128
x"00",x"85",x"88",x"85",x"89",x"A0",x"00",x"A6", -- 0x0130
x"88",x"A5",x"89",x"5D",x"84",x"A1",x"85",x"88", -- 0x0138
x"B1",x"84",x"5D",x"84",x"A2",x"85",x"89",x"E6", -- 0x0140
x"84",x"D0",x"02",x"E6",x"85",x"A5",x"84",x"C5", -- 0x0148
x"82",x"D0",x"E4",x"A5",x"85",x"C5",x"83",x"D0", -- 0x0150
x"DE",x"A5",x"88",x"A2",x"07",x"0A",x"66",x"8A", -- 0x0158
x"CA",x"10",x"FA",x"A5",x"8A",x"48",x"A5",x"89", -- 0x0160
x"A2",x"07",x"0A",x"66",x"8A",x"CA",x"10",x"FA", -- 0x0168
x"A5",x"8A",x"85",x"88",x"68",x"85",x"89",x"A5", -- 0x0170
x"FD",x"29",x"0F",x"8D",x"FF",x"BF",x"58",x"68", -- 0x0178
x"AA",x"68",x"A8",x"60",x"00",x"68",x"D0",x"B8", -- 0x0180
x"A0",x"C8",x"70",x"18",x"40",x"28",x"90",x"F8", -- 0x0188
x"E0",x"88",x"30",x"58",x"80",x"E8",x"50",x"38", -- 0x0190
x"20",x"48",x"F0",x"98",x"C0",x"A8",x"10",x"78", -- 0x0198
x"60",x"08",x"B0",x"D8",x"00",x"68",x"D0",x"B8", -- 0x01A0
x"A0",x"C8",x"70",x"18",x"40",x"28",x"90",x"F8", -- 0x01A8
x"E0",x"88",x"30",x"58",x"80",x"E8",x"50",x"38", -- 0x01B0
x"20",x"48",x"F0",x"98",x"C0",x"A8",x"10",x"78", -- 0x01B8
x"60",x"08",x"B0",x"D8",x"00",x"68",x"D0",x"B8", -- 0x01C0
x"A0",x"C8",x"70",x"18",x"40",x"28",x"90",x"F8", -- 0x01C8
x"E0",x"88",x"30",x"58",x"80",x"E8",x"50",x"38", -- 0x01D0
x"20",x"48",x"F0",x"98",x"C0",x"A8",x"10",x"78", -- 0x01D8
x"60",x"08",x"B0",x"D8",x"00",x"68",x"D0",x"B8", -- 0x01E0
x"A0",x"C8",x"70",x"18",x"40",x"28",x"90",x"F8", -- 0x01E8
x"E0",x"88",x"30",x"58",x"80",x"E8",x"50",x"38", -- 0x01F0
x"20",x"48",x"F0",x"98",x"C0",x"A8",x"10",x"78", -- 0x01F8
x"60",x"08",x"B0",x"D8",x"00",x"68",x"D0",x"B8", -- 0x0200
x"A0",x"C8",x"70",x"18",x"40",x"28",x"90",x"F8", -- 0x0208
x"E0",x"88",x"30",x"58",x"80",x"E8",x"50",x"38", -- 0x0210
x"20",x"48",x"F0",x"98",x"C0",x"A8",x"10",x"78", -- 0x0218
x"60",x"08",x"B0",x"D8",x"00",x"68",x"D0",x"B8", -- 0x0220
x"A0",x"C8",x"70",x"18",x"40",x"28",x"90",x"F8", -- 0x0228
x"E0",x"88",x"30",x"58",x"80",x"E8",x"50",x"38", -- 0x0230
x"20",x"48",x"F0",x"98",x"C0",x"A8",x"10",x"78", -- 0x0238
x"60",x"08",x"B0",x"D8",x"00",x"68",x"D0",x"B8", -- 0x0240
x"A0",x"C8",x"70",x"18",x"40",x"28",x"90",x"F8", -- 0x0248
x"E0",x"88",x"30",x"58",x"80",x"E8",x"50",x"38", -- 0x0250
x"20",x"48",x"F0",x"98",x"C0",x"A8",x"10",x"78", -- 0x0258
x"60",x"08",x"B0",x"D8",x"00",x"68",x"D0",x"B8", -- 0x0260
x"A0",x"C8",x"70",x"18",x"40",x"28",x"90",x"F8", -- 0x0268
x"E0",x"88",x"30",x"58",x"80",x"E8",x"50",x"38", -- 0x0270
x"20",x"48",x"F0",x"98",x"C0",x"A8",x"10",x"78", -- 0x0278
x"60",x"08",x"B0",x"D8",x"00",x"01",x"02",x"03", -- 0x0280
x"05",x"04",x"07",x"06",x"0B",x"0A",x"09",x"08", -- 0x0288
x"0E",x"0F",x"0C",x"0D",x"16",x"17",x"14",x"15", -- 0x0290
x"13",x"12",x"11",x"10",x"1D",x"1C",x"1F",x"1E", -- 0x0298
x"18",x"19",x"1A",x"1B",x"2D",x"2C",x"2F",x"2E", -- 0x02A0
x"28",x"29",x"2A",x"2B",x"26",x"27",x"24",x"25", -- 0x02A8
x"23",x"22",x"21",x"20",x"3B",x"3A",x"39",x"38", -- 0x02B0
x"3E",x"3F",x"3C",x"3D",x"30",x"31",x"32",x"33", -- 0x02B8
x"35",x"34",x"37",x"36",x"5A",x"5B",x"58",x"59", -- 0x02C0
x"5F",x"5E",x"5D",x"5C",x"51",x"50",x"53",x"52", -- 0x02C8
x"54",x"55",x"56",x"57",x"4C",x"4D",x"4E",x"4F", -- 0x02D0
x"49",x"48",x"4B",x"4A",x"47",x"46",x"45",x"44", -- 0x02D8
x"42",x"43",x"40",x"41",x"77",x"76",x"75",x"74", -- 0x02E0
x"72",x"73",x"70",x"71",x"7C",x"7D",x"7E",x"7F", -- 0x02E8
x"79",x"78",x"7B",x"7A",x"61",x"60",x"63",x"62", -- 0x02F0
x"64",x"65",x"66",x"67",x"6A",x"6B",x"68",x"69", -- 0x02F8
x"6F",x"6E",x"6D",x"6C",x"B4",x"B5",x"B6",x"B7", -- 0x0300
x"B1",x"B0",x"B3",x"B2",x"BF",x"BE",x"BD",x"BC", -- 0x0308
x"BA",x"BB",x"B8",x"B9",x"A2",x"A3",x"A0",x"A1", -- 0x0310
x"A7",x"A6",x"A5",x"A4",x"A9",x"A8",x"AB",x"AA", -- 0x0318
x"AC",x"AD",x"AE",x"AF",x"99",x"98",x"9B",x"9A", -- 0x0320
x"9C",x"9D",x"9E",x"9F",x"92",x"93",x"90",x"91", -- 0x0328
x"97",x"96",x"95",x"94",x"8F",x"8E",x"8D",x"8C", -- 0x0330
x"8A",x"8B",x"88",x"89",x"84",x"85",x"86",x"87", -- 0x0338
x"81",x"80",x"83",x"82",x"EE",x"EF",x"EC",x"ED", -- 0x0340
x"EB",x"EA",x"E9",x"E8",x"E5",x"E4",x"E7",x"E6", -- 0x0348
x"E0",x"E1",x"E2",x"E3",x"F8",x"F9",x"FA",x"FB", -- 0x0350
x"FD",x"FC",x"FF",x"FE",x"F3",x"F2",x"F1",x"F0", -- 0x0358
x"F6",x"F7",x"F4",x"F5",x"C3",x"C2",x"C1",x"C0", -- 0x0360
x"C6",x"C7",x"C4",x"C5",x"C8",x"C9",x"CA",x"CB", -- 0x0368
x"CD",x"CC",x"CF",x"CE",x"D5",x"D4",x"D7",x"D6", -- 0x0370
x"D0",x"D1",x"D2",x"D3",x"DE",x"DF",x"DC",x"DD", -- 0x0378
x"DB",x"DA",x"D9",x"D8",x"20",x"A2",x"A3",x"A9", -- 0x0380
x"97",x"8D",x"0A",x"02",x"A9",x"A3",x"8D",x"0B", -- 0x0388
x"02",x"A9",x"C0",x"8D",x"B1",x"BD",x"60",x"AD", -- 0x0390
x"B1",x"BD",x"29",x"02",x"F0",x"F9",x"AD",x"B0", -- 0x0398
x"BD",x"60",x"A9",x"AD",x"8D",x"08",x"02",x"A9", -- 0x03A0
x"A3",x"8D",x"09",x"02",x"60",x"48",x"AD",x"B1", -- 0x03A8
x"BD",x"29",x"01",x"F0",x"F9",x"68",x"8D",x"B0", -- 0x03B0
x"BD",x"4C",x"52",x"FE",x"20",x"BC",x"C8",x"20", -- 0x03B8
x"31",x"C2",x"A5",x"16",x"85",x"53",x"A5",x"25", -- 0x03C0
x"85",x"54",x"A5",x"34",x"85",x"55",x"A5",x"43", -- 0x03C8
x"85",x"56",x"A9",x"00",x"85",x"57",x"A9",x"09", -- 0x03D0
x"85",x"58",x"A9",x"3D",x"85",x"59",x"A9",x"00", -- 0x03D8
x"85",x"5A",x"A9",x"00",x"85",x"5B",x"85",x"5C", -- 0x03E0
x"85",x"5D",x"85",x"5E",x"20",x"8C",x"C6",x"26", -- 0x03E8
x"57",x"26",x"58",x"26",x"59",x"26",x"5A",x"A5", -- 0x03F0
x"58",x"8D",x"B3",x"BD",x"20",x"02",x"F8",x"A5", -- 0x03F8
x"57",x"8D",x"B2",x"BD",x"20",x"02",x"F8",x"4C", -- 0x0400
x"ED",x"FF",x"20",x"D4",x"A0",x"20",x"1B",x"A1", -- 0x0408
x"20",x"0E",x"A1",x"A5",x"80",x"85",x"84",x"A5", -- 0x0410
x"81",x"85",x"85",x"A0",x"00",x"AD",x"B1",x"BD", -- 0x0418
x"29",x"01",x"F0",x"F9",x"B1",x"84",x"8D",x"B0", -- 0x0420
x"BD",x"E6",x"84",x"D0",x"02",x"E6",x"85",x"A5", -- 0x0428
x"84",x"C5",x"82",x"D0",x"E8",x"A5",x"85",x"C5", -- 0x0430
x"83",x"D0",x"E2",x"60",x"20",x"BC",x"C8",x"20", -- 0x0438
x"31",x"C2",x"A5",x"16",x"85",x"80",x"A5",x"25", -- 0x0440
x"85",x"81",x"20",x"D1",x"F7",x"53",x"45",x"4E", -- 0x0448
x"44",x"20",x"44",x"41",x"54",x"41",x"0A",x"0D", -- 0x0450
x"EA",x"A5",x"80",x"85",x"82",x"A5",x"81",x"85", -- 0x0458
x"83",x"A0",x"00",x"84",x"88",x"84",x"89",x"AD", -- 0x0460
x"B1",x"BD",x"29",x"02",x"F0",x"F9",x"D0",x"11", -- 0x0468
x"A2",x"00",x"AD",x"B1",x"BD",x"29",x"02",x"D0", -- 0x0470
x"08",x"CA",x"D0",x"F6",x"88",x"D0",x"F3",x"F0", -- 0x0478
x"25",x"A0",x"00",x"AD",x"02",x"B0",x"49",x"04", -- 0x0480
x"8D",x"02",x"B0",x"A6",x"88",x"A5",x"89",x"5D", -- 0x0488
x"84",x"A1",x"85",x"88",x"AD",x"B0",x"BD",x"91", -- 0x0490
x"82",x"5D",x"84",x"A2",x"85",x"89",x"E6",x"82", -- 0x0498
x"D0",x"CE",x"E6",x"83",x"D0",x"CA",x"20",x"D1", -- 0x04A0
x"F7",x"53",x"54",x"41",x"52",x"54",x"3A",x"20", -- 0x04A8
x"EA",x"A5",x"81",x"20",x"02",x"F8",x"A5",x"80", -- 0x04B0
x"20",x"02",x"F8",x"20",x"D1",x"F7",x"0A",x"0D", -- 0x04B8
x"20",x"20",x"45",x"4E",x"44",x"3A",x"20",x"EA", -- 0x04C0
x"A5",x"83",x"20",x"02",x"F8",x"A5",x"82",x"20", -- 0x04C8
x"02",x"F8",x"A5",x"88",x"A2",x"07",x"0A",x"66", -- 0x04D0
x"8A",x"CA",x"10",x"FA",x"A5",x"8A",x"48",x"A5", -- 0x04D8
x"89",x"A2",x"07",x"0A",x"66",x"8A",x"CA",x"10", -- 0x04E0
x"FA",x"A5",x"8A",x"85",x"88",x"68",x"85",x"89", -- 0x04E8
x"20",x"D1",x"F7",x"0A",x"0D",x"20",x"20",x"43", -- 0x04F0
x"52",x"43",x"3A",x"20",x"EA",x"4C",x"0E",x"A1", -- 0x04F8
x"20",x"BC",x"C8",x"20",x"31",x"C2",x"20",x"BC", -- 0x0500
x"C8",x"20",x"31",x"C2",x"20",x"D1",x"F7",x"50", -- 0x0508
x"52",x"4F",x"47",x"52",x"41",x"4D",x"20",x"42", -- 0x0510
x"41",x"4E",x"4B",x"20",x"EA",x"A5",x"17",x"85", -- 0x0518
x"84",x"20",x"02",x"F8",x"20",x"D1",x"F7",x"20", -- 0x0520
x"46",x"52",x"4F",x"4D",x"20",x"EA",x"A5",x"25", -- 0x0528
x"85",x"81",x"20",x"02",x"F8",x"A5",x"16",x"85", -- 0x0530
x"80",x"20",x"02",x"F8",x"20",x"ED",x"FF",x"20", -- 0x0538
x"D1",x"F7",x"43",x"4F",x"4E",x"46",x"49",x"52", -- 0x0540
x"4D",x"20",x"28",x"59",x"2F",x"4E",x"29",x"3F", -- 0x0548
x"20",x"EA",x"20",x"E3",x"FF",x"C9",x"59",x"F0", -- 0x0550
x"11",x"20",x"D1",x"F7",x"4E",x"0A",x"0D",x"41", -- 0x0558
x"42",x"4F",x"52",x"54",x"45",x"44",x"0A",x"0D", -- 0x0560
x"EA",x"60",x"20",x"D1",x"F7",x"59",x"0A",x"0D", -- 0x0568
x"50",x"52",x"4F",x"47",x"52",x"41",x"4D",x"4D", -- 0x0570
x"49",x"4E",x"47",x"2E",x"2E",x"2E",x"0A",x"0D", -- 0x0578
x"EA",x"A0",x"00",x"B9",x"91",x"A5",x"99",x"00", -- 0x0580
x"28",x"C8",x"C0",x"9B",x"D0",x"F5",x"4C",x"00", -- 0x0588
x"28",x"78",x"A9",x"05",x"8D",x"FF",x"BF",x"A9", -- 0x0590
x"AA",x"8D",x"55",x"A5",x"A9",x"02",x"8D",x"FF", -- 0x0598
x"BF",x"A9",x"55",x"8D",x"AA",x"AA",x"A9",x"05", -- 0x05A0
x"8D",x"FF",x"BF",x"A9",x"80",x"8D",x"55",x"A5", -- 0x05A8
x"A9",x"05",x"8D",x"FF",x"BF",x"A9",x"AA",x"8D", -- 0x05B0
x"55",x"A5",x"A9",x"02",x"8D",x"FF",x"BF",x"A9", -- 0x05B8
x"55",x"8D",x"AA",x"AA",x"A5",x"84",x"8D",x"FF", -- 0x05C0
x"BF",x"A9",x"30",x"8D",x"00",x"A0",x"A0",x"00", -- 0x05C8
x"A2",x"00",x"CA",x"D0",x"FD",x"88",x"D0",x"F8", -- 0x05D0
x"A9",x"00",x"85",x"82",x"A9",x"A0",x"85",x"83", -- 0x05D8
x"A0",x"00",x"A9",x"05",x"8D",x"FF",x"BF",x"A9", -- 0x05E0
x"AA",x"8D",x"55",x"A5",x"A9",x"02",x"8D",x"FF", -- 0x05E8
x"BF",x"A9",x"55",x"8D",x"AA",x"AA",x"A9",x"05", -- 0x05F0
x"8D",x"FF",x"BF",x"A9",x"A0",x"8D",x"55",x"A5", -- 0x05F8
x"A5",x"84",x"8D",x"FF",x"BF",x"B1",x"80",x"91", -- 0x0600
x"82",x"A2",x"08",x"CA",x"D0",x"FD",x"C8",x"D0", -- 0x0608
x"D1",x"E6",x"81",x"E6",x"83",x"A5",x"83",x"C9", -- 0x0610
x"B0",x"D0",x"C7",x"A5",x"FD",x"29",x"0F",x"8D", -- 0x0618
x"FF",x"BF",x"58",x"68",x"68",x"A2",x"00",x"86", -- 0x0620
x"04",x"4C",x"58",x"C5",x"A0",x"00",x"B9",x"3C", -- 0x0628
x"A6",x"99",x"00",x"28",x"C8",x"C0",x"08",x"D0", -- 0x0630
x"F5",x"4C",x"00",x"28",x"A9",x"08",x"8D",x"FE", -- 0x0638
x"BF",x"6C",x"FC",x"FF",x"20",x"F1",x"A0",x"20", -- 0x0640
x"ED",x"FF",x"A2",x"00",x"A0",x"00",x"A9",x"20", -- 0x0648
x"20",x"F4",x"FF",x"BD",x"3C",x"A0",x"30",x"06", -- 0x0650
x"20",x"F4",x"FF",x"E8",x"D0",x"F5",x"A9",x"20", -- 0x0658
x"20",x"F4",x"FF",x"A5",x"E0",x"C9",x"08",x"D0", -- 0x0660
x"F5",x"B9",x"8E",x"A0",x"F0",x"06",x"20",x"F4", -- 0x0668
x"FF",x"C8",x"D0",x"F5",x"20",x"ED",x"FF",x"C8", -- 0x0670
x"E8",x"E8",x"BD",x"3C",x"A0",x"10",x"CF",x"20", -- 0x0678
x"D1",x"F7",x"45",x"58",x"41",x"4D",x"50",x"4C", -- 0x0680
x"45",x"53",x"3A",x"0A",x"0D",x"20",x"42",x"41", -- 0x0688
x"55",x"44",x"20",x"31",x"31",x"35",x"32",x"30", -- 0x0690
x"30",x"0A",x"0D",x"20",x"44",x"4E",x"4C",x"4F", -- 0x0698
x"41",x"44",x"20",x"23",x"34",x"30",x"30",x"30", -- 0x06A0
x"0A",x"0D",x"20",x"46",x"4C",x"41",x"53",x"48", -- 0x06A8
x"20",x"23",x"34",x"30",x"30",x"30",x"2C",x"34", -- 0x06B0
x"0A",x"0D",x"EA",x"60",x"A0",x"00",x"B9",x"84", -- 0x06B8
x"A1",x"99",x"00",x"3A",x"B9",x"84",x"A2",x"99", -- 0x06C0
x"00",x"3B",x"C8",x"D0",x"F1",x"B9",x"1B",x"A1", -- 0x06C8
x"99",x"00",x"28",x"C8",x"C0",x"69",x"D0",x"F5", -- 0x06D0
x"A9",x"00",x"8D",x"21",x"28",x"A9",x"3A",x"8D", -- 0x06D8
x"22",x"28",x"A9",x"00",x"8D",x"28",x"28",x"A9", -- 0x06E0
x"3B",x"8D",x"29",x"28",x"A9",x"00",x"85",x"80", -- 0x06E8
x"85",x"82",x"A9",x"A0",x"85",x"81",x"A9",x"B0", -- 0x06F0
x"85",x"83",x"A2",x"00",x"20",x"00",x"28",x"A5", -- 0x06F8
x"88",x"85",x"86",x"A5",x"89",x"85",x"87",x"A2", -- 0x0700
x"80",x"20",x"00",x"28",x"A5",x"88",x"C9",x"84", -- 0x0708
x"D0",x"06",x"A5",x"89",x"C9",x"2A",x"F0",x"20", -- 0x0710
x"8A",x"29",x"1F",x"20",x"02",x"F8",x"A9",x"20", -- 0x0718
x"20",x"F4",x"FF",x"A5",x"89",x"20",x"02",x"F8", -- 0x0720
x"A5",x"88",x"20",x"02",x"F8",x"A9",x"20",x"20", -- 0x0728
x"F4",x"FF",x"20",x"3E",x"A7",x"20",x"ED",x"FF", -- 0x0730
x"E8",x"E0",x"A0",x"D0",x"CC",x"60",x"A5",x"88", -- 0x0738
x"C5",x"86",x"D0",x"09",x"A5",x"89",x"C5",x"87", -- 0x0740
x"D0",x"03",x"4C",x"F1",x"A0",x"A9",x"92",x"85", -- 0x0748
x"84",x"A9",x"A7",x"85",x"85",x"A0",x"00",x"B1", -- 0x0750
x"84",x"C8",x"C5",x"88",x"D0",x"12",x"B1",x"84", -- 0x0758
x"C5",x"89",x"D0",x"0C",x"C8",x"B1",x"84",x"F0", -- 0x0760
x"06",x"20",x"F4",x"FF",x"C8",x"D0",x"F6",x"60", -- 0x0768
x"B1",x"84",x"88",x"31",x"84",x"C8",x"C8",x"C9", -- 0x0770
x"FF",x"F0",x"EA",x"B1",x"84",x"F0",x"03",x"C8", -- 0x0778
x"D0",x"F9",x"C8",x"98",x"18",x"65",x"84",x"85", -- 0x0780
x"84",x"A9",x"00",x"A8",x"65",x"85",x"85",x"85", -- 0x0788
x"D0",x"C5",x"7D",x"D6",x"41",x"42",x"41",x"53", -- 0x0790
x"49",x"43",x"20",x"4F",x"52",x"49",x"47",x"00", -- 0x0798
x"A1",x"AA",x"41",x"46",x"4C",x"4F",x"41",x"54", -- 0x07A0
x"20",x"4F",x"52",x"49",x"47",x"00",x"86",x"E3", -- 0x07A8
x"41",x"4B",x"45",x"52",x"4E",x"45",x"4C",x"20", -- 0x07B0
x"4F",x"52",x"49",x"47",x"00",x"45",x"4C",x"41", -- 0x07B8
x"44",x"4F",x"53",x"20",x"4F",x"52",x"49",x"47", -- 0x07C0
x"00",x"F6",x"14",x"42",x"42",x"43",x"20",x"42", -- 0x07C8
x"41",x"53",x"49",x"43",x"20",x"31",x"2F",x"34", -- 0x07D0
x"00",x"55",x"E6",x"42",x"42",x"43",x"20",x"42", -- 0x07D8
x"41",x"53",x"49",x"43",x"20",x"32",x"2F",x"34", -- 0x07E0
x"00",x"5C",x"DA",x"42",x"42",x"43",x"20",x"42", -- 0x07E8
x"41",x"53",x"49",x"43",x"20",x"33",x"2F",x"34", -- 0x07F0
x"00",x"1F",x"2B",x"42",x"42",x"43",x"20",x"42", -- 0x07F8
x"41",x"53",x"49",x"43",x"20",x"34",x"2F",x"34", -- 0x0800
x"00",x"58",x"49",x"41",x"46",x"4C",x"4F",x"41", -- 0x0808
x"54",x"20",x"50",x"41",x"54",x"43",x"48",x"45", -- 0x0810
x"44",x"00",x"B9",x"F0",x"41",x"4B",x"45",x"52", -- 0x0818
x"4E",x"45",x"4C",x"20",x"50",x"41",x"54",x"43", -- 0x0820
x"48",x"45",x"44",x"00",x"2A",x"98",x"41",x"54", -- 0x0828
x"4F",x"4D",x"4D",x"43",x"32",x"20",x"41",x"56", -- 0x0830
x"52",x"20",x"56",x"32",x"2E",x"39",x"35",x"00", -- 0x0838
x"49",x"B4",x"53",x"44",x"44",x"4F",x"53",x"20", -- 0x0840
x"41",x"56",x"52",x"20",x"56",x"33",x"2E",x"32", -- 0x0848
x"35",x"00",x"19",x"BE",x"47",x"41",x"47",x"53", -- 0x0850
x"20",x"56",x"32",x"2E",x"33",x"00",x"B4",x"EA", -- 0x0858
x"42",x"42",x"43",x"20",x"4D",x"4F",x"53",x"20", -- 0x0860
x"48",x"4F",x"47",x"4C",x"45",x"54",x"20",x"56", -- 0x0868
x"33",x"00",x"17",x"57",x"53",x"44",x"44",x"4F", -- 0x0870
x"53",x"20",x"56",x"33",x"2E",x"32",x"35",x"00", -- 0x0878
x"9A",x"4B",x"41",x"43",x"4F",x"52",x"4E",x"20", -- 0x0880
x"43",x"41",x"4C",x"43",x"00",x"16",x"5B",x"41", -- 0x0888
x"43",x"4F",x"52",x"4E",x"20",x"43",x"41",x"4C", -- 0x0890
x"43",x"00",x"C5",x"B1",x"41",x"43",x"4F",x"52", -- 0x0898
x"4E",x"20",x"43",x"41",x"4C",x"43",x"00",x"E2", -- 0x08A0
x"F4",x"41",x"43",x"4F",x"52",x"4E",x"20",x"43", -- 0x08A8
x"41",x"4C",x"43",x"00",x"F5",x"49",x"41",x"43", -- 0x08B0
x"4F",x"52",x"4E",x"20",x"44",x"45",x"4D",x"4F", -- 0x08B8
x"00",x"F1",x"B0",x"41",x"43",x"4F",x"52",x"4E", -- 0x08C0
x"20",x"45",x"44",x"36",x"34",x"00",x"FA",x"CE", -- 0x08C8
x"41",x"43",x"4F",x"52",x"4E",x"20",x"45",x"44", -- 0x08D0
x"38",x"30",x"00",x"26",x"B3",x"41",x"43",x"4F", -- 0x08D8
x"52",x"4E",x"20",x"57",x"4F",x"52",x"44",x"00", -- 0x08E0
x"43",x"92",x"41",x"45",x"4B",x"20",x"4D",x"4F", -- 0x08E8
x"4E",x"49",x"54",x"4F",x"52",x"00",x"01",x"12", -- 0x08F0
x"41",x"45",x"4B",x"20",x"53",x"43",x"52",x"45", -- 0x08F8
x"45",x"4E",x"00",x"E9",x"F3",x"41",x"45",x"4B", -- 0x0900
x"20",x"53",x"43",x"52",x"45",x"45",x"4E",x"00", -- 0x0908
x"61",x"72",x"41",x"26",x"46",x"20",x"55",x"54", -- 0x0910
x"49",x"4C",x"49",x"54",x"59",x"00",x"FB",x"E1", -- 0x0918
x"41",x"43",x"45",x"20",x"56",x"32",x"2E",x"30", -- 0x0920
x"00",x"BE",x"97",x"41",x"43",x"45",x"20",x"56", -- 0x0928
x"32",x"2E",x"32",x"00",x"BB",x"2B",x"41",x"43", -- 0x0930
x"45",x"20",x"56",x"33",x"2E",x"30",x"00",x"34", -- 0x0938
x"42",x"41",x"54",x"4F",x"4D",x"49",x"43",x"20", -- 0x0940
x"57",x"49",x"4E",x"44",x"4F",x"57",x"53",x"20", -- 0x0948
x"56",x"31",x"2E",x"31",x"00",x"81",x"7D",x"41", -- 0x0950
x"54",x"4F",x"4D",x"49",x"43",x"20",x"57",x"49", -- 0x0958
x"4E",x"44",x"4F",x"57",x"53",x"20",x"56",x"31", -- 0x0960
x"2E",x"32",x"42",x"44",x"00",x"EB",x"CC",x"41", -- 0x0968
x"58",x"52",x"31",x"00",x"D4",x"54",x"43",x"4F", -- 0x0970
x"4D",x"42",x"4F",x"58",x"00",x"F9",x"B2",x"44", -- 0x0978
x"49",x"53",x"4B",x"52",x"4F",x"4D",x"00",x"3B", -- 0x0980
x"1B",x"44",x"49",x"53",x"4B",x"52",x"4F",x"4D", -- 0x0988
x"00",x"78",x"CB",x"44",x"49",x"53",x"4B",x"52", -- 0x0990
x"4F",x"4D",x"00",x"4C",x"9F",x"47",x"41",x"47", -- 0x0998
x"53",x"20",x"56",x"32",x"2E",x"34",x"00",x"06", -- 0x09A0
x"62",x"4A",x"4F",x"53",x"42",x"4F",x"58",x"00", -- 0x09A8
x"90",x"6D",x"4D",x"4F",x"55",x"53",x"45",x"42", -- 0x09B0
x"4F",x"58",x"20",x"56",x"31",x"2E",x"30",x"31", -- 0x09B8
x"00",x"6B",x"C1",x"50",x"43",x"48",x"41",x"52", -- 0x09C0
x"4D",x"45",x"20",x"56",x"31",x"2E",x"37",x"33", -- 0x09C8
x"00",x"E6",x"46",x"52",x"58",x"42",x"4F",x"58", -- 0x09D0
x"20",x"56",x"31",x"2E",x"31",x"00",x"75",x"9F", -- 0x09D8
x"53",x"41",x"4C",x"46",x"41",x"41",x"20",x"56", -- 0x09E0
x"32",x"2E",x"36",x"00",x"26",x"5F",x"53",x"44", -- 0x09E8
x"52",x"4F",x"4D",x"20",x"56",x"32",x"2E",x"33", -- 0x09F0
x"00",x"E2",x"CE",x"53",x"44",x"52",x"4F",x"4D", -- 0x09F8
x"20",x"56",x"33",x"2E",x"32",x"34",x"00",x"BD", -- 0x0A00
x"B1",x"50",x"50",x"20",x"53",x"55",x"50",x"45", -- 0x0A08
x"52",x"42",x"41",x"53",x"49",x"43",x"00",x"0E", -- 0x0A10
x"66",x"50",x"50",x"20",x"54",x"4F",x"4F",x"4C", -- 0x0A18
x"42",x"4F",x"58",x"00",x"9E",x"6C",x"50",x"50", -- 0x0A20
x"20",x"54",x"4F",x"4F",x"4C",x"42",x"4F",x"58", -- 0x0A28
x"00",x"49",x"70",x"50",x"52",x"4F",x"43",x"59", -- 0x0A30
x"4F",x"4E",x"20",x"44",x"49",x"53",x"41",x"54", -- 0x0A38
x"4F",x"4D",x"00",x"1E",x"85",x"50",x"52",x"4F", -- 0x0A40
x"43",x"59",x"4F",x"4E",x"20",x"44",x"49",x"53", -- 0x0A48
x"41",x"54",x"4F",x"4D",x"00",x"60",x"01",x"50", -- 0x0A50
x"53",x"49",x"4F",x"4E",x"20",x"44",x"45",x"42", -- 0x0A58
x"55",x"47",x"00",x"9F",x"12",x"50",x"53",x"49", -- 0x0A60
x"4F",x"4E",x"20",x"45",x"44",x"49",x"54",x"00", -- 0x0A68
x"45",x"5B",x"50",x"53",x"49",x"4F",x"4E",x"20", -- 0x0A70
x"45",x"44",x"49",x"54",x"00",x"A1",x"5B",x"50", -- 0x0A78
x"53",x"49",x"4F",x"4E",x"20",x"45",x"44",x"49", -- 0x0A80
x"54",x"00",x"99",x"4B",x"52",x"4F",x"53",x"53", -- 0x0A88
x"20",x"55",x"54",x"49",x"4C",x"49",x"54",x"59", -- 0x0A90
x"00",x"45",x"F5",x"57",x"41",x"54",x"46",x"4F", -- 0x0A98
x"52",x"44",x"20",x"57",x"45",x"52",x"4F",x"4D", -- 0x0AA0
x"00",x"15",x"F3",x"57",x"49",x"4C",x"4C",x"4F", -- 0x0AA8
x"57",x"20",x"55",x"54",x"49",x"4C",x"49",x"54", -- 0x0AB0
x"59",x"20",x"56",x"31",x"2E",x"31",x"00",x"FF", -- 0x0AB8
x"FF",x"55",x"4E",x"4B",x"4E",x"4F",x"57",x"4E", -- 0x0AC0
x"00",x"A9",x"E6",x"8D",x"08",x"02",x"A9",x"AB", -- 0x0AC8
x"8D",x"09",x"02",x"A9",x"FA",x"8D",x"0A",x"02", -- 0x0AD0
x"A9",x"AB",x"8D",x"0B",x"02",x"A9",x"80",x"8D", -- 0x0AD8
x"E0",x"BD",x"A9",x"0C",x"4C",x"F4",x"FF",x"C9", -- 0x0AE0
x"06",x"F0",x"1D",x"C9",x"15",x"F0",x"1C",x"A4", -- 0x0AE8
x"E0",x"30",x"1B",x"C9",x"1B",x"F0",x"11",x"C9", -- 0x0AF0
x"07",x"F0",x"14",x"20",x"2D",x"AB",x"A2",x"0A", -- 0x0AF8
x"20",x"2C",x"AC",x"D0",x"0D",x"4C",x"1D",x"AC", -- 0x0B00
x"4C",x"0B",x"FD",x"4C",x"11",x"FD",x"60",x"4C", -- 0x0B08
x"1A",x"FD",x"C9",x"20",x"90",x"17",x"69",x"1F", -- 0x0B10
x"30",x"02",x"49",x"60",x"20",x"6B",x"FE",x"91", -- 0x0B18
x"DE",x"C8",x"C0",x"50",x"90",x"05",x"20",x"7D", -- 0x0B20
x"AB",x"A0",x"00",x"84",x"E0",x"4C",x"44",x"FD", -- 0x0B28
x"20",x"C9",x"AB",x"A9",x"20",x"20",x"6B",x"FE", -- 0x0B30
x"91",x"DE",x"10",x"EF",x"20",x"C9",x"AB",x"4C", -- 0x0B38
x"2B",x"AB",x"20",x"7D",x"AB",x"A4",x"E0",x"10", -- 0x0B40
x"E2",x"A0",x"80",x"84",x"E1",x"A0",x"00",x"8C", -- 0x0B48
x"00",x"B0",x"A9",x"20",x"99",x"00",x"80",x"99", -- 0x0B50
x"00",x"81",x"20",x"7A",x"AC",x"C8",x"D0",x"F4", -- 0x0B58
x"4C",x"7D",x"FD",x"20",x"CE",x"AB",x"4C",x"2B", -- 0x0B60
x"AB",x"18",x"A9",x"28",x"85",x"E6",x"4C",x"92", -- 0x0B68
x"FD",x"29",x"05",x"2E",x"01",x"B0",x"2A",x"20", -- 0x0B70
x"E7",x"AA",x"4C",x"00",x"AC",x"A5",x"DE",x"A4", -- 0x0B78
x"DF",x"C0",x"8C",x"90",x"3B",x"C9",x"30",x"90", -- 0x0B80
x"37",x"A4",x"E6",x"30",x"0C",x"88",x"D0",x"07", -- 0x0B88
x"20",x"71",x"FE",x"B0",x"FB",x"A0",x"28",x"84", -- 0x0B90
x"E6",x"A0",x"50",x"20",x"66",x"FE",x"B9",x"00", -- 0x0B98
x"80",x"99",x"B0",x"7F",x"C8",x"D0",x"F7",x"20", -- 0x0BA0
x"6B",x"FE",x"B9",x"00",x"81",x"99",x"B0",x"80", -- 0x0BA8
x"C8",x"D0",x"F7",x"20",x"9C",x"AC",x"A0",x"4F", -- 0x0BB0
x"A9",x"20",x"91",x"DE",x"88",x"10",x"FB",x"60", -- 0x0BB8
x"69",x"50",x"85",x"DE",x"90",x"02",x"E6",x"DF", -- 0x0BC0
x"60",x"88",x"10",x"19",x"A0",x"4F",x"A5",x"DE", -- 0x0BC8
x"D0",x"0B",x"A6",x"DF",x"E0",x"80",x"D0",x"05", -- 0x0BD0
x"68",x"68",x"4C",x"45",x"AB",x"E9",x"50",x"85", -- 0x0BD8
x"DE",x"B0",x"02",x"C6",x"DF",x"60",x"20",x"FB", -- 0x0BE0
x"FE",x"08",x"48",x"D8",x"84",x"E5",x"86",x"E4", -- 0x0BE8
x"20",x"E7",x"AA",x"68",x"A6",x"E4",x"A4",x"E5", -- 0x0BF0
x"28",x"60",x"08",x"D8",x"86",x"E4",x"84",x"E5", -- 0x0BF8
x"2C",x"02",x"B0",x"50",x"05",x"20",x"71",x"FE", -- 0x0C00
x"90",x"F6",x"20",x"8A",x"FB",x"20",x"71",x"FE", -- 0x0C08
x"B0",x"FB",x"20",x"71",x"FE",x"B0",x"F6",x"98", -- 0x0C10
x"A2",x"17",x"20",x"2C",x"AC",x"BD",x"4A",x"AC", -- 0x0C18
x"85",x"E2",x"BD",x"62",x"AC",x"85",x"E3",x"98", -- 0x0C20
x"6C",x"E2",x"00",x"CA",x"DD",x"32",x"AC",x"90", -- 0x0C28
x"FA",x"60",x"00",x"08",x"09",x"0A",x"0B",x"0C", -- 0x0C30
x"0D",x"0E",x"0F",x"1E",x"7F",x"00",x"01",x"05", -- 0x0C38
x"06",x"08",x"0E",x"0F",x"10",x"11",x"1C",x"20", -- 0x0C40
x"21",x"3B",x"2D",x"3C",x"21",x"42",x"63",x"49", -- 0x0C48
x"29",x"69",x"6E",x"60",x"30",x"DF",x"D2",x"9A", -- 0x0C50
x"71",x"E2",x"AE",x"C0",x"DF",x"D8",x"D6",x"C8", -- 0x0C58
x"C6",x"C2",x"AB",x"AB",x"AB",x"AB",x"AB",x"AB", -- 0x0C60
x"AB",x"AB",x"AB",x"AB",x"AB",x"FD",x"FD",x"FD", -- 0x0C68
x"AB",x"FD",x"FD",x"FD",x"FD",x"FD",x"FD",x"FD", -- 0x0C70
x"FD",x"FD",x"99",x"00",x"82",x"99",x"00",x"83", -- 0x0C78
x"99",x"00",x"84",x"99",x"00",x"85",x"99",x"00", -- 0x0C80
x"86",x"99",x"00",x"87",x"99",x"00",x"88",x"99", -- 0x0C88
x"00",x"89",x"99",x"00",x"8A",x"99",x"00",x"8B", -- 0x0C90
x"99",x"00",x"8C",x"60",x"B9",x"00",x"82",x"99", -- 0x0C98
x"B0",x"81",x"C8",x"D0",x"F7",x"B9",x"00",x"83", -- 0x0CA0
x"99",x"B0",x"82",x"C8",x"D0",x"F7",x"B9",x"00", -- 0x0CA8
x"84",x"99",x"B0",x"83",x"C8",x"D0",x"F7",x"B9", -- 0x0CB0
x"00",x"85",x"99",x"B0",x"84",x"C8",x"D0",x"F7", -- 0x0CB8
x"B9",x"00",x"86",x"99",x"B0",x"85",x"C8",x"D0", -- 0x0CC0
x"F7",x"B9",x"00",x"87",x"99",x"B0",x"86",x"C8", -- 0x0CC8
x"D0",x"F7",x"B9",x"00",x"88",x"99",x"B0",x"87", -- 0x0CD0
x"C8",x"D0",x"F7",x"B9",x"00",x"89",x"99",x"B0", -- 0x0CD8
x"88",x"C8",x"D0",x"F7",x"B9",x"00",x"8A",x"99", -- 0x0CE0
x"B0",x"89",x"C8",x"D0",x"F7",x"B9",x"00",x"8B", -- 0x0CE8
x"99",x"B0",x"8A",x"C8",x"D0",x"F7",x"B9",x"00", -- 0x0CF0
x"8C",x"99",x"B0",x"8B",x"C8",x"D0",x"F7",x"60", -- 0x0CF8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0D00
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0D08
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0D10
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0D18
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0D20
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0D28
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0D30
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0D38
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0D40
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0D48
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0D50
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0D58
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0D60
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0D68
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0D70
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0D78
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0D80
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0D88
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0D90
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0D98
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0DA0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0DA8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0DB0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0DB8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0DC0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0DC8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0DD0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0DD8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0DE0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0DE8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0DF0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0DF8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0E00
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0E08
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0E10
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0E18
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0E20
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0E28
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0E30
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0E38
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0E40
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0E48
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0E50
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0E58
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0E60
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0E68
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0E70
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0E78
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0E80
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0E88
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0E90
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0E98
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0EA0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0EA8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0EB0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0EB8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0EC0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0EC8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0ED0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0ED8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0EE0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0EE8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0EF0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0EF8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0F00
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0F08
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0F10
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0F18
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0F20
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0F28
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0F30
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0F38
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0F40
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0F48
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0F50
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0F58
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0F60
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0F68
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0F70
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0F78
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0F80
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0F88
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0F90
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0F98
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0FA0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0FA8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0FB0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0FB8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0FC0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0FC8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0FD0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0FD8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0FE0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0FE8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0FF0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"84",x"A3" -- 0x0FF8
);
begin
p_rom : process
begin
wait until rising_edge(CLK);
DATA <= ROM(to_integer(unsigned(ADDR)));
end process;
end RTL;
|
apache-2.0
|
wsoltys/AtomFpga
|
src/T6502/T65_Pack.vhd
|
1
|
4662
|
-- ****
-- T65(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 300 Bugfixes by ehenciak added
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- 65xx compatible microprocessor core
--
-- Version : 0246
--
-- Copyright (c) 2002 Daniel Wallner ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t65/
--
-- Limitations :
--
-- File history :
--
library IEEE;
use IEEE.std_logic_1164.all;
package T65_Pack is
constant Flag_C : integer := 0;
constant Flag_Z : integer := 1;
constant Flag_I : integer := 2;
constant Flag_D : integer := 3;
constant Flag_B : integer := 4;
constant Flag_1 : integer := 5;
constant Flag_V : integer := 6;
constant Flag_N : integer := 7;
component T65_MCode
port(
Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65816
IR : in std_logic_vector(7 downto 0);
MCycle : in std_logic_vector(2 downto 0);
P : in std_logic_vector(7 downto 0);
LCycle : out std_logic_vector(2 downto 0);
ALU_Op : out std_logic_vector(3 downto 0);
Set_BusA_To : out std_logic_vector(2 downto 0); -- DI,A,X,Y,S,P
Set_Addr_To : out std_logic_vector(1 downto 0); -- PC Adder,S,AD,BA
Write_Data : out std_logic_vector(2 downto 0); -- DL,A,X,Y,S,P,PCL,PCH
Jump : out std_logic_vector(1 downto 0); -- PC,++,DIDL,Rel
BAAdd : out std_logic_vector(1 downto 0); -- None,DB Inc,BA Add,BA Adj
BreakAtNA : out std_logic;
ADAdd : out std_logic;
AddY : out std_logic;
PCAdd : out std_logic;
Inc_S : out std_logic;
Dec_S : out std_logic;
LDA : out std_logic;
LDP : out std_logic;
LDX : out std_logic;
LDY : out std_logic;
LDS : out std_logic;
LDDI : out std_logic;
LDALU : out std_logic;
LDAD : out std_logic;
LDBAL : out std_logic;
LDBAH : out std_logic;
SaveP : out std_logic;
Write : out std_logic
);
end component;
component T65_ALU
port(
Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65C816
Op : in std_logic_vector(3 downto 0);
BusA : in std_logic_vector(7 downto 0);
BusB : in std_logic_vector(7 downto 0);
P_In : in std_logic_vector(7 downto 0);
P_Out : out std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0)
);
end component;
end;
|
apache-2.0
|
its2mc/PCFG
|
pcfg/m7bitRegister.vhd
|
1
|
1065
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:02:47 11/21/2016
-- Design Name:
-- Module Name: 7bitRegister - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity 7bitRegister is
Port ( input : in STD_LOGIC_VECTOR (7 downto 0);
load_cs : in STD_LOGIC;
output : in STD_LOGIC_VECTOR (7 downto 0));
end 7bitRegister;
architecture Behavioral of 7bitRegister is
begin
end Behavioral;
|
apache-2.0
|
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