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jza00425/SingleCycleARM
|
lab2/outputs/1108-121610/sim/work/clock/_primary.vhd
|
3
|
229
|
library verilog;
use verilog.vl_types.all;
entity clock is
generic(
start : integer := 0;
halfPeriod : integer := 50
);
port(
clockSignal : out vl_logic
);
end clock;
|
unlicense
|
OrganicMonkeyMotion/fpga_experiments
|
small_board/LABS/digital_logic/vhdl/lab1/part6/mux_2bit_4to1.vhd
|
2
|
418
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
-- implements a 2-bit wide 4-to-1 multiplexer
ENTITY mux_2bit_4to1 IS
PORT ( S, U, V, W, X : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M : OUT STD_LOGIC_VECTOR(1 DOWNTO 0));
END mux_2bit_4to1;
ARCHITECTURE Behavior OF mux_2bit_4to1 IS
BEGIN -- Behavior
WITH S SELECT
M <= U WHEN "00",
V WHEN "01",
W WHEN "10",
X WHEN "11",
U WHEN OTHERS;
END Behavior;
|
unlicense
|
simonspa/pixel-dtb-firmware
|
dtb/lpm_mux1.vhd
|
2
|
5446
|
-- megafunction wizard: %LPM_MUX%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_MUX
-- ============================================================
-- File Name: lpm_mux1.vhd
-- Megafunction Name(s):
-- LPM_MUX
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 12.1 Build 243 01/31/2013 SP 1 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2012 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
ENTITY lpm_mux1 IS
PORT
(
clock : IN STD_LOGIC ;
data0 : IN STD_LOGIC ;
data1 : IN STD_LOGIC ;
data2 : IN STD_LOGIC ;
data3 : IN STD_LOGIC ;
data4 : IN STD_LOGIC ;
data5 : IN STD_LOGIC ;
data6 : IN STD_LOGIC ;
data7 : IN STD_LOGIC ;
sel : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
result : OUT STD_LOGIC
);
END lpm_mux1;
ARCHITECTURE SYN OF lpm_mux1 IS
-- type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC;
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC_2D (7 DOWNTO 0, 0 DOWNTO 0);
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC ;
SIGNAL sub_wire6 : STD_LOGIC ;
SIGNAL sub_wire7 : STD_LOGIC ;
SIGNAL sub_wire8 : STD_LOGIC ;
SIGNAL sub_wire9 : STD_LOGIC ;
SIGNAL sub_wire10 : STD_LOGIC ;
BEGIN
sub_wire10 <= data0;
sub_wire9 <= data1;
sub_wire8 <= data2;
sub_wire7 <= data3;
sub_wire6 <= data4;
sub_wire5 <= data5;
sub_wire4 <= data6;
sub_wire1 <= sub_wire0(0);
result <= sub_wire1;
sub_wire2 <= data7;
sub_wire3(7, 0) <= sub_wire2;
sub_wire3(6, 0) <= sub_wire4;
sub_wire3(5, 0) <= sub_wire5;
sub_wire3(4, 0) <= sub_wire6;
sub_wire3(3, 0) <= sub_wire7;
sub_wire3(2, 0) <= sub_wire8;
sub_wire3(1, 0) <= sub_wire9;
sub_wire3(0, 0) <= sub_wire10;
LPM_MUX_component : LPM_MUX
GENERIC MAP (
lpm_pipeline => 1,
lpm_size => 8,
lpm_type => "LPM_MUX",
lpm_width => 1,
lpm_widths => 3
)
PORT MAP (
clock => clock,
data => sub_wire3,
sel => sel,
result => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "1"
-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "8"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
-- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "3"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
-- Retrieval info: USED_PORT: data0 0 0 0 0 INPUT NODEFVAL "data0"
-- Retrieval info: USED_PORT: data1 0 0 0 0 INPUT NODEFVAL "data1"
-- Retrieval info: USED_PORT: data2 0 0 0 0 INPUT NODEFVAL "data2"
-- Retrieval info: USED_PORT: data3 0 0 0 0 INPUT NODEFVAL "data3"
-- Retrieval info: USED_PORT: data4 0 0 0 0 INPUT NODEFVAL "data4"
-- Retrieval info: USED_PORT: data5 0 0 0 0 INPUT NODEFVAL "data5"
-- Retrieval info: USED_PORT: data6 0 0 0 0 INPUT NODEFVAL "data6"
-- Retrieval info: USED_PORT: data7 0 0 0 0 INPUT NODEFVAL "data7"
-- Retrieval info: USED_PORT: result 0 0 0 0 OUTPUT NODEFVAL "result"
-- Retrieval info: USED_PORT: sel 0 0 3 0 INPUT NODEFVAL "sel[2..0]"
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data 1 0 1 0 data0 0 0 0 0
-- Retrieval info: CONNECT: @data 1 1 1 0 data1 0 0 0 0
-- Retrieval info: CONNECT: @data 1 2 1 0 data2 0 0 0 0
-- Retrieval info: CONNECT: @data 1 3 1 0 data3 0 0 0 0
-- Retrieval info: CONNECT: @data 1 4 1 0 data4 0 0 0 0
-- Retrieval info: CONNECT: @data 1 5 1 0 data5 0 0 0 0
-- Retrieval info: CONNECT: @data 1 6 1 0 data6 0 0 0 0
-- Retrieval info: CONNECT: @data 1 7 1 0 data7 0 0 0 0
-- Retrieval info: CONNECT: @sel 0 0 3 0 sel 0 0 3 0
-- Retrieval info: CONNECT: result 0 0 0 0 @result 0 0 1 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux1.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux1.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux1.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux1.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux1_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
unlicense
|
simonspa/pixel-dtb-firmware
|
dtb/ram_dq_PHASE_l.vhd
|
2
|
7072
|
-- megafunction wizard: %RAM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: ram_dq_PHASE_l.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 12.1 Build 243 01/31/2013 SP 1 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2012 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY ram_dq_PHASE_l IS
PORT
(
address : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
clock : IN STD_LOGIC := '1';
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
wren : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END ram_dq_PHASE_l;
ARCHITECTURE SYN OF ram_dq_phase_l IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
clock_enable_input_a : STRING;
clock_enable_output_a : STRING;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_reg_a : STRING;
power_up_uninitialized : STRING;
read_during_write_mode_port_a : STRING;
widthad_a : NATURAL;
width_a : NATURAL;
width_byteena_a : NATURAL
);
PORT (
address_a : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
clock0 : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
wren_a : IN STD_LOGIC ;
q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(7 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
intended_device_family => "Cyclone III",
lpm_hint => "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=PH_l",
lpm_type => "altsyncram",
numwords_a => 32,
operation_mode => "SINGLE_PORT",
outdata_aclr_a => "NONE",
outdata_reg_a => "CLOCK0",
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
widthad_a => 5,
width_a => 8,
width_byteena_a => 1
)
PORT MAP (
address_a => address,
clock0 => clock,
data_a => data,
wren_a => wren,
q_a => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrData NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1"
-- Retrieval info: PRIVATE: JTAG_ID STRING "PH_l"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING ""
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "32"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegData NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
-- Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "5"
-- Retrieval info: PRIVATE: WidthData NUMERIC "8"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=PH_l"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "32"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "5"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 5 0 INPUT NODEFVAL "address[4..0]"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
-- Retrieval info: CONNECT: @address_a 0 0 5 0 address 0 0 5 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_PHASE_l.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_PHASE_l.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_PHASE_l.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_PHASE_l.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_PHASE_l_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
|
unlicense
|
OrganicMonkeyMotion/fpga_experiments
|
small_board/LABS/digital_logic/vhdl/lab1/part6a/DE1_disp.vhd
|
1
|
1283
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY DE1_disp IS
PORT ( HEX0, HEX1, HEX2, HEX3 : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
clk : IN STD_LOGIC;
HEX : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
DISPn: OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END DE1_disp;
ARCHITECTURE Behavior OF DE1_disp IS
COMPONENT sweep
Port ( mclk : in STD_LOGIC;
sweep_out : out std_logic_vector(1 downto 0));
END COMPONENT;
SIGNAL M0 : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL M1 : STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN -- Behavior
S0: sweep PORT MAP (clk,M0);
DISPProcess: process (M0) is
begin
CASE M0 IS
WHEN "00" => DISPn <= "1110";
WHEN "01" => DISPn <= "1101";
WHEN "10" => DISPn <= "1011";
WHEN "11" => DISPn <= "0111";
WHEN OTHERS => NULL;
END CASE;
end process DISPProcess;
HEXProcess: process (M1) is
begin
CASE M1 IS
WHEN "00" => HEX <= HEX0;
WHEN "01" => HEX <= HEX1 ;
WHEN "10" => HEX <= HEX2 ;
WHEN "11" => HEX <= HEX3 ;
WHEN OTHERS => NULL;
END CASE;
end process HEXProcess;
CLKProcess: process (clk) is
begin
if falling_edge(clk) then
M1 <= M0 after 25ps;
end if;
end process CLKProcess;
END Behavior;
|
unlicense
|
simonspa/pixel-dtb-firmware
|
dtb/gl_counter5b.vhd
|
2
|
4624
|
-- megafunction wizard: %LPM_COUNTER%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_counter
-- ============================================================
-- File Name: gl_counter5b.vhd
-- Megafunction Name(s):
-- lpm_counter
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.0 Build 184 04/29/2009 SP 1 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2009 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY gl_counter5b IS
PORT
(
clock : IN STD_LOGIC ;
cnt_en : IN STD_LOGIC ;
sclr : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
);
END gl_counter5b;
ARCHITECTURE SYN OF gl_counter5b IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
COMPONENT lpm_counter
GENERIC (
lpm_direction : STRING;
lpm_port_updown : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
sclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
cnt_en : IN STD_LOGIC
);
END COMPONENT;
BEGIN
q <= sub_wire0(4 DOWNTO 0);
lpm_counter_component : lpm_counter
GENERIC MAP (
lpm_direction => "UP",
lpm_port_updown => "PORT_UNUSED",
lpm_type => "LPM_COUNTER",
lpm_width => 5
)
PORT MAP (
sclr => sclr,
clock => clock,
cnt_en => cnt_en,
q => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
-- Retrieval info: PRIVATE: ASET NUMERIC "0"
-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
-- Retrieval info: PRIVATE: CNT_EN NUMERIC "1"
-- Retrieval info: PRIVATE: CarryIn NUMERIC "0"
-- Retrieval info: PRIVATE: CarryOut NUMERIC "0"
-- Retrieval info: PRIVATE: Direction NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix"
-- Retrieval info: PRIVATE: ModulusCounter NUMERIC "0"
-- Retrieval info: PRIVATE: ModulusValue NUMERIC "0"
-- Retrieval info: PRIVATE: SCLR NUMERIC "1"
-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: SSET NUMERIC "0"
-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "5"
-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "UP"
-- Retrieval info: CONSTANT: LPM_PORT_UPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COUNTER"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "5"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
-- Retrieval info: USED_PORT: cnt_en 0 0 0 0 INPUT NODEFVAL cnt_en
-- Retrieval info: USED_PORT: q 0 0 5 0 OUTPUT NODEFVAL q[4..0]
-- Retrieval info: USED_PORT: sclr 0 0 0 0 INPUT NODEFVAL sclr
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 5 0 @q 0 0 5 0
-- Retrieval info: CONNECT: @cnt_en 0 0 0 0 cnt_en 0 0 0 0
-- Retrieval info: CONNECT: @sclr 0 0 0 0 sclr 0 0 0 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL gl_counter5b.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL gl_counter5b.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL gl_counter5b.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL gl_counter5b.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL gl_counter5b_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL gl_counter5b_waveforms.html TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL gl_counter5b_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: lpm
|
unlicense
|
OrganicMonkeyMotion/fpga_experiments
|
small_board/LABS/digital_logic/vhdl/lab2/part6/lpm_constant1.vhd
|
1
|
3515
|
-- megafunction wizard: %LPM_CONSTANT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_CONSTANT
-- ============================================================
-- File Name: lpm_constant1.vhd
-- Megafunction Name(s):
-- LPM_CONSTANT
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 11.1 Build 259 01/25/2012 SP 2 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2011 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_constant1 IS
PORT
(
result : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END lpm_constant1;
ARCHITECTURE SYN OF lpm_constant1 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (3 DOWNTO 0);
COMPONENT lpm_constant
GENERIC (
lpm_cvalue : NATURAL;
lpm_hint : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
result : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END COMPONENT;
BEGIN
result <= sub_wire0(3 DOWNTO 0);
LPM_CONSTANT_component : LPM_CONSTANT
GENERIC MAP (
lpm_cvalue => 4,
lpm_hint => "ENABLE_RUNTIME_MOD=YES, INSTANCE_NAME=NONE",
lpm_type => "LPM_CONSTANT",
lpm_width => 4
)
PORT MAP (
result => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: Radix NUMERIC "2"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: Value NUMERIC "4"
-- Retrieval info: PRIVATE: nBit NUMERIC "4"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "4"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES, INSTANCE_NAME=NONE"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "4"
-- Retrieval info: USED_PORT: result 0 0 4 0 OUTPUT NODEFVAL "result[3..0]"
-- Retrieval info: CONNECT: result 0 0 4 0 @result 0 0 4 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant1.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant1.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant1.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant1.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant1_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
unlicense
|
simonspa/pixel-dtb-firmware
|
dtb/ram_dq_INST_ka.vhd
|
2
|
7075
|
-- megafunction wizard: %RAM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: ram_dq_INST_ka.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 12.1 Build 243 01/31/2013 SP 1 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2012 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY ram_dq_INST_ka IS
PORT
(
address : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
clock : IN STD_LOGIC := '1';
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
wren : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END ram_dq_INST_ka;
ARCHITECTURE SYN OF ram_dq_inst_ka IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
clock_enable_input_a : STRING;
clock_enable_output_a : STRING;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_reg_a : STRING;
power_up_uninitialized : STRING;
read_during_write_mode_port_a : STRING;
widthad_a : NATURAL;
width_a : NATURAL;
width_byteena_a : NATURAL
);
PORT (
address_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
clock0 : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
wren_a : IN STD_LOGIC ;
q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(7 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
intended_device_family => "Cyclone III",
lpm_hint => "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=N_ka",
lpm_type => "altsyncram",
numwords_a => 256,
operation_mode => "SINGLE_PORT",
outdata_aclr_a => "NONE",
outdata_reg_a => "CLOCK0",
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
widthad_a => 8,
width_a => 8,
width_byteena_a => 1
)
PORT MAP (
address_a => address,
clock0 => clock,
data_a => data,
wren_a => wren,
q_a => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrData NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1"
-- Retrieval info: PRIVATE: JTAG_ID STRING "N_ka"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING ""
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegData NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
-- Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "8"
-- Retrieval info: PRIVATE: WidthData NUMERIC "8"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=N_ka"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
-- Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_INST_ka.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_INST_ka.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_INST_ka.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_INST_ka.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_INST_ka_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
|
unlicense
|
OrganicMonkeyMotion/fpga_experiments
|
small_board/LABS/digital_logic/vhdl/lab2/part6/segseven.vhd
|
1
|
1724
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY segseven IS
PORT (SW : IN STD_LOGIC_VECTOR (3 DOWNTO 0); -- (3)=A, (2)=B, (1)=C, (0)=D
LEDSEG : OUT STD_LOGIC_VECTOR (6 DOWNTO 0)
);
END segseven;
ARCHITECTURE Behavior OF segseven IS
BEGIN
-- SEG A : In3' In2' In1' In0 + In2 In1' In0' + In3 In1 + In3 In2;
LEDSEG(0) <= (NOT SW(3) AND NOT SW(2) AND NOT SW(1) AND SW(0)) OR
(SW(2) AND NOT SW(1) AND NOT SW(0)) OR
(SW(3) AND SW(1)) OR
(SW(3) AND SW(2));
-- SEG B : In2 In1' In0 + In3 In1 + In2 In1 In0' + In3 In2;
LEDSEG(1) <= (SW(2) AND NOT SW(1) AND SW(0)) OR
(SW(3) AND SW(1)) OR
(SW(2) AND SW(1) AND NOT SW(0)) OR
(SW(3) AND SW(2));
-- SEG C : In2' In1 In0' + In3 In2 + In3 In1;
LEDSEG(2) <= (NOT SW(2) AND SW(1) AND NOT SW(0)) OR
(SW(3) AND SW(2)) OR
(SW(3) AND SW(1));
-- SEG D : In3 In0 + In2 In1' In0' + In2' In1' In0 + In3 In1 + In2 In1 In0;
LEDSEG(3) <= (SW(3) AND SW(0)) OR
(SW(2) AND NOT SW(1) AND NOT SW(0)) OR
(NOT SW(2) AND NOT SW(1) AND SW(0)) OR
(SW(2) AND SW(1) AND SW(0)) OR
(SW(3) AND SW(1));
-- SEG E : In2 In1' + In3 In1 + In0;
LEDSEG(4) <= (SW(3) AND SW(1)) OR
(SW(2) AND NOT SW(1)) OR
(SW(0));
-- SEG F : In3 In2 + In3' In2' In0 + In2' In1 + In1 In0;
LEDSEG(5) <= (NOT SW(3) AND NOT SW(2) AND SW(0)) OR
(SW(3) AND SW(2)) OR
(NOT SW(2) AND SW(1)) OR
(SW(1) AND SW(0));
-- SED G : In3' In2' In1' + In2 In1 In0 + In3 In2 + In3 In1;
LEDSEG(6) <= (NOT SW(3) AND NOT SW(2) AND NOT SW(1)) OR
(SW(2) AND SW(1) AND SW(0)) OR
(SW(3) AND SW(1)) OR
(SW(3) AND SW(2));
END Behavior;
|
unlicense
|
OrganicMonkeyMotion/fpga_experiments
|
small_board/LABS/digital_logic/vhdl/lab2/part5/bcd_adder.vhd
|
1
|
850
|
library ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.ALL;
ENTITY bcd_adder IS
PORT (b_in : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
a_in : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
c_in : IN STD_LOGIC;
c_out : OUT STD_LOGIC;
s_out : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)) ;
END bcd_adder;
ARCHITECTURE Behavior OF bcd_adder IS
signal t: STD_LOGIC_VECTOR (3 DOWNTO 0);
signal z: STD_LOGIC_VECTOR (3 DOWNTO 0);
signal a: STD_LOGIC_VECTOR (3 DOWNTO 0);
signal b: STD_LOGIC_VECTOR (3 DOWNTO 0);
signal c1: STD_LOGIC;
BEGIN
process (a_in, b_in) begin
t <= STD_LOGIC_VECTOR(unsigned(a_in) + unsigned(b_in) + (c_in & ""));
if (t > "1001") then
z <= "1010";
c1 <= '1';
else
z <= "0000";
c1 <= '0';
end if;
s_out <= STD_LOGIC_VECTOR(unsigned(t) - unsigned(z));
c_out <= c1;
end process;
END Behavior;
|
unlicense
|
simonspa/pixel-dtb-firmware
|
dtb/TBM_H_FSM.vhd
|
2
|
4425
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity TBM_H_FSM is
port (clk_i : in std_logic;
reset_i : in std_logic;
TBM_H_start_i : in std_logic;
serdat_i: in std_logic;
payload_o : out std_logic_vector(3 downto 0);
type_o : out std_logic_vector(3 downto 0);
wen_o : out std_logic);
end TBM_H_FSM;
architecture rtl of TBM_H_FSM is
type t_state is (waiting,
tick_EN7,
tick_EN6,
tick_EN5,
tick_EN4,
tick_EN3,
tick_EN2,
tick_EN1,
tick_EN0,
tick_STF,
tick_PKR,
tick_SC5,
tick_SC4,
tick_SC3,
tick_SC2,
tick_SC1,
tick_SC0);
signal s_state : t_state;
begin
p_format: process (clk_i, reset_i)
begin -- process p_serin
if (reset_i = '1') then -- asynchronous reset
wen_o <= '0';
payload_o <= "0000";
type_o <= "0000";
s_state <= waiting;
elsif rising_edge(clk_i) then -- rising clock edge
case s_state is
-------------------------------------------------------------------------
when tick_EN7 =>
wen_o <= '0';
payload_o(3)<=serdat_i;
s_state <= tick_EN6 ;
-------------------------------------------------------------------------
when tick_EN6 =>
payload_o(2)<=serdat_i;
s_state <= tick_EN5 ;
-------------------------------------------------------------------------
when tick_EN5 =>
payload_o(1)<=serdat_i;
s_state <= tick_EN4 ;
-------------------------------------------------------------------------
when tick_EN4 =>
payload_o(0)<=serdat_i;
type_o <= "1000";
wen_o <= '1';
s_state <= tick_EN3 ;
-------------------------------------------------------------------------
when tick_EN3 =>
payload_o(3)<=serdat_i;
wen_o <= '0';
s_state <= tick_EN2 ;
-------------------------------------------------------------------------
when tick_EN2 =>
payload_o(2)<=serdat_i;
s_state <= tick_EN1 ;
-------------------------------------------------------------------------
when tick_EN1 =>
payload_o(1)<=serdat_i;
s_state <= tick_EN0 ;
-------------------------------------------------------------------------
when tick_EN0 =>
payload_o(0)<=serdat_i;
type_o <= "1001";
wen_o <= '1';
s_state <= tick_STF ;
-------------------------------------------------------------------------
when tick_STF =>
payload_o(3)<=serdat_i;
wen_o <= '0';
s_state <= tick_PKR ;
-------------------------------------------------------------------------
when tick_PKR =>
payload_o(2)<=serdat_i;
s_state <= tick_SC5 ;
-------------------------------------------------------------------------
when tick_SC5 =>
payload_o(1)<=serdat_i;
s_state <= tick_SC4 ;
-------------------------------------------------------------------------
when tick_SC4 =>
payload_o(0)<=serdat_i;
type_o <= "1010";
wen_o <= '1';
s_state <= tick_SC3 ;
-------------------------------------------------------------------------
when tick_SC3 =>
payload_o(3)<=serdat_i;
wen_o <= '0';
s_state <= tick_SC2 ;
-------------------------------------------------------------------------
when tick_SC2 =>
payload_o(2)<=serdat_i;
s_state <= tick_SC1 ;
-------------------------------------------------------------------------
when tick_SC1 =>
payload_o(1)<=serdat_i;
s_state <= tick_SC0 ;
-------------------------------------------------------------------------
when tick_SC0 =>
payload_o(0)<=serdat_i;
wen_o <= '1';
type_o <= "1011";
s_state <= waiting ;
-------------------------------------------------------------------------
when others =>
if TBM_H_start_i = '1' then
wen_o <= '0';
s_state <= tick_EN7;
else
wen_o <= '0';
s_state <= waiting;
end if;
end case;
end if;
end process p_format;
end rtl;
|
unlicense
|
simonspa/pixel-dtb-firmware
|
dtb/gl_and4b.vhd
|
2
|
3278
|
-- megafunction wizard: %LPM_AND%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_and
-- ============================================================
-- File Name: gl_and4b.vhd
-- Megafunction Name(s):
-- lpm_and
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.0 Build 184 04/29/2009 SP 1 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2009 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
ENTITY gl_and4b IS
PORT
(
data : IN STD_LOGIC_2D (3 DOWNTO 0, 0 DOWNTO 0);
result : OUT STD_LOGIC
);
END gl_and4b;
ARCHITECTURE SYN OF gl_and4b IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
BEGIN
sub_wire1 <= sub_wire0(0);
result <= sub_wire1;
lpm_and_component : lpm_and
GENERIC MAP (
lpm_size => 4,
lpm_type => "LPM_AND",
lpm_width => 1
)
PORT MAP (
data => data,
result => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: CompactSymbol NUMERIC "0"
-- Retrieval info: PRIVATE: GateFunction NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix"
-- Retrieval info: PRIVATE: InputAsBus NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: WidthInput NUMERIC "1"
-- Retrieval info: PRIVATE: nInput NUMERIC "4"
-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "4"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_AND"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
-- Retrieval info: USED_PORT: data 4 0 1 0 INPUT NODEFVAL data[3..0][0..0]
-- Retrieval info: USED_PORT: result 0 0 0 0 OUTPUT NODEFVAL result
-- Retrieval info: CONNECT: @data 4 0 1 0 data 4 0 1 0
-- Retrieval info: CONNECT: result 0 0 0 0 @result 0 0 1 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL gl_and4b.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL gl_and4b.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL gl_and4b.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL gl_and4b.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL gl_and4b_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
unlicense
|
OrganicMonkeyMotion/fpga_experiments
|
small_board/LABS/digital_logic/vhdl/lab2/part6/DE1_disp.vhd
|
4
|
843
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY DE1_disp IS
PORT ( HEX0, HEX1, HEX2, HEX3: IN STD_LOGIC_VECTOR(6 DOWNTO 0);
clk : IN STD_LOGIC;
HEX : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
DISPn: OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END DE1_disp;
ARCHITECTURE Behavior OF DE1_disp IS
COMPONENT sweep
Port ( mclk : in STD_LOGIC;
sweep_out : out std_logic_vector(2 downto 0));
END COMPONENT;
SIGNAL M : STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN -- Behavior
S0: sweep PORT MAP (clk,M);
HEX <= HEX0 WHEN M = "000" ELSE
HEX1 WHEN M = "010" ELSE
HEX2 WHEN M = "100" ELSE
HEX3 WHEN M = "110" ELSE
"1111111";
DISPn <= "1110" WHEN M = "000" ELSE
"1101" WHEN M = "010" ELSE
"1011" WHEN M = "100" ELSE
"0111" WHEN M = "110" ELSE
"1111";
END Behavior;
|
unlicense
|
simonspa/pixel-dtb-firmware
|
dtb/PhSeROM.vhd
|
1
|
5796
|
-- megafunction wizard: %ROM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: PhSeROM.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
ENTITY PhSeROM IS
PORT
(
address : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
clock : IN STD_LOGIC := '1';
rden : IN STD_LOGIC := '1';
q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END PhSeROM;
ARCHITECTURE SYN OF phserom IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (3 DOWNTO 0);
BEGIN
q <= sub_wire0(3 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_aclr_a => "NONE",
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => "PhaseSelectErr.mif",
intended_device_family => "Cyclone III",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 256,
operation_mode => "ROM",
outdata_aclr_a => "NONE",
outdata_reg_a => "UNREGISTERED",
widthad_a => 8,
width_a => 4,
width_byteena_a => 1
)
PORT MAP (
address_a => address,
clock0 => clock,
rden_a => rden,
q_a => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING "PhaseSelectErr.mif"
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "8"
-- Retrieval info: PRIVATE: WidthData NUMERIC "4"
-- Retrieval info: PRIVATE: rden NUMERIC "1"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INIT_FILE STRING "PhaseSelectErr.mif"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "4"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: q 0 0 4 0 OUTPUT NODEFVAL "q[3..0]"
-- Retrieval info: USED_PORT: rden 0 0 0 0 INPUT VCC "rden"
-- Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @rden_a 0 0 0 0 rden 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 4 0 @q_a 0 0 4 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL PhSeROM.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL PhSeROM.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL PhSeROM.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL PhSeROM.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL PhSeROM_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
|
unlicense
|
OrganicMonkeyMotion/fpga_experiments
|
small_board/LABS/digital_logic/vhdl/lab2/part6/lpm_constant0.vhd
|
1
|
3513
|
-- megafunction wizard: %LPM_CONSTANT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_CONSTANT
-- ============================================================
-- File Name: lpm_constant0.vhd
-- Megafunction Name(s):
-- LPM_CONSTANT
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 11.1 Build 259 01/25/2012 SP 2 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2011 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_constant0 IS
PORT
(
result : OUT STD_LOGIC_VECTOR (5 DOWNTO 0)
);
END lpm_constant0;
ARCHITECTURE SYN OF lpm_constant0 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (5 DOWNTO 0);
COMPONENT lpm_constant
GENERIC (
lpm_cvalue : NATURAL;
lpm_hint : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
result : OUT STD_LOGIC_VECTOR (5 DOWNTO 0)
);
END COMPONENT;
BEGIN
result <= sub_wire0(5 DOWNTO 0);
LPM_CONSTANT_component : LPM_CONSTANT
GENERIC MAP (
lpm_cvalue => 0,
lpm_hint => "ENABLE_RUNTIME_MOD=YES, INSTANCE_NAME=BIN",
lpm_type => "LPM_CONSTANT",
lpm_width => 6
)
PORT MAP (
result => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1"
-- Retrieval info: PRIVATE: JTAG_ID STRING "BIN"
-- Retrieval info: PRIVATE: Radix NUMERIC "16"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: Value NUMERIC "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "6"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "0"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES, INSTANCE_NAME=BIN"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "6"
-- Retrieval info: USED_PORT: result 0 0 6 0 OUTPUT NODEFVAL "result[5..0]"
-- Retrieval info: CONNECT: result 0 0 6 0 @result 0 0 6 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
unlicense
|
simonspa/pixel-dtb-firmware
|
dtb/mod12counter.vhd
|
2
|
4774
|
-- megafunction wizard: %LPM_COUNTER%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_counter
-- ============================================================
-- File Name: mod12counter.vhd
-- Megafunction Name(s):
-- lpm_counter
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 350 03/24/2010 SP 2 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY mod12counter IS
PORT
(
clock : IN STD_LOGIC ;
sclr : IN STD_LOGIC ;
cout : OUT STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END mod12counter;
ARCHITECTURE SYN OF mod12counter IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (3 DOWNTO 0);
COMPONENT lpm_counter
GENERIC (
lpm_direction : STRING;
lpm_modulus : NATURAL;
lpm_port_updown : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
sclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
cout : OUT STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END COMPONENT;
BEGIN
cout <= sub_wire0;
q <= sub_wire1(3 DOWNTO 0);
lpm_counter_component : lpm_counter
GENERIC MAP (
lpm_direction => "UP",
lpm_modulus => 12,
lpm_port_updown => "PORT_UNUSED",
lpm_type => "LPM_COUNTER",
lpm_width => 4
)
PORT MAP (
sclr => sclr,
clock => clock,
cout => sub_wire0,
q => sub_wire1
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
-- Retrieval info: PRIVATE: ASET NUMERIC "0"
-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
-- Retrieval info: PRIVATE: CNT_EN NUMERIC "0"
-- Retrieval info: PRIVATE: CarryIn NUMERIC "0"
-- Retrieval info: PRIVATE: CarryOut NUMERIC "1"
-- Retrieval info: PRIVATE: Direction NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria GX"
-- Retrieval info: PRIVATE: ModulusCounter NUMERIC "1"
-- Retrieval info: PRIVATE: ModulusValue NUMERIC "12"
-- Retrieval info: PRIVATE: SCLR NUMERIC "1"
-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: SSET NUMERIC "0"
-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "4"
-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "UP"
-- Retrieval info: CONSTANT: LPM_MODULUS NUMERIC "12"
-- Retrieval info: CONSTANT: LPM_PORT_UPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COUNTER"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "4"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
-- Retrieval info: USED_PORT: cout 0 0 0 0 OUTPUT NODEFVAL cout
-- Retrieval info: USED_PORT: q 0 0 4 0 OUTPUT NODEFVAL q[3..0]
-- Retrieval info: USED_PORT: sclr 0 0 0 0 INPUT NODEFVAL sclr
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 4 0 @q 0 0 4 0
-- Retrieval info: CONNECT: cout 0 0 0 0 @cout 0 0 0 0
-- Retrieval info: CONNECT: @sclr 0 0 0 0 sclr 0 0 0 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL mod12counter.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL mod12counter.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL mod12counter.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL mod12counter.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL mod12counter_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL mod12counter_waveforms.html TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL mod12counter_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: lpm
|
unlicense
|
OrganicMonkeyMotion/fpga_experiments
|
small_board/LABS/digital_logic/vhdl/lab2/part4/sweep.vhd
|
4
|
562
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sweep is
Port ( mclk : in STD_LOGIC;
sweep_out : out std_logic_vector(2 downto 0));
end sweep;
architecture arch of sweep is
signal q: std_logic_vector(11 downto 0);
begin
--clock divider
process(mclk)
begin
if q = "111111111111" then
q <= "000000000000";
elsif mclk'event and mclk = '1' then
q <= std_logic_vector(unsigned(q)+1);
end if;
end process;
sweep_out <= q(11)&q(10)&q(9);
end arch;
|
unlicense
|
simonspa/pixel-dtb-firmware
|
dtb/ram_dq_INST_kb.vhd
|
2
|
7075
|
-- megafunction wizard: %RAM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: ram_dq_INST_kb.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 12.1 Build 243 01/31/2013 SP 1 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2012 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY ram_dq_INST_kb IS
PORT
(
address : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
clock : IN STD_LOGIC := '1';
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
wren : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END ram_dq_INST_kb;
ARCHITECTURE SYN OF ram_dq_inst_kb IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
clock_enable_input_a : STRING;
clock_enable_output_a : STRING;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_reg_a : STRING;
power_up_uninitialized : STRING;
read_during_write_mode_port_a : STRING;
widthad_a : NATURAL;
width_a : NATURAL;
width_byteena_a : NATURAL
);
PORT (
address_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
clock0 : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
wren_a : IN STD_LOGIC ;
q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(7 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
intended_device_family => "Cyclone III",
lpm_hint => "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=N_kb",
lpm_type => "altsyncram",
numwords_a => 256,
operation_mode => "SINGLE_PORT",
outdata_aclr_a => "NONE",
outdata_reg_a => "CLOCK0",
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
widthad_a => 8,
width_a => 8,
width_byteena_a => 1
)
PORT MAP (
address_a => address,
clock0 => clock,
data_a => data,
wren_a => wren,
q_a => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrData NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1"
-- Retrieval info: PRIVATE: JTAG_ID STRING "N_kb"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING ""
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegData NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
-- Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "8"
-- Retrieval info: PRIVATE: WidthData NUMERIC "8"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=N_kb"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
-- Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_INST_kb.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_INST_kb.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_INST_kb.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_INST_kb.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_INST_kb_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
|
unlicense
|
simonspa/pixel-dtb-firmware
|
dtb/gl_dff5.vhd
|
2
|
3893
|
-- megafunction wizard: %LPM_FF%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_ff
-- ============================================================
-- File Name: gl_dff5.vhd
-- Megafunction Name(s):
-- lpm_ff
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 222 10/21/2009 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2009 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY gl_dff5 IS
PORT
(
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
);
END gl_dff5;
ARCHITECTURE SYN OF gl_dff5 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
COMPONENT lpm_ff
GENERIC (
lpm_fftype : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
data : IN STD_LOGIC_VECTOR (4 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(4 DOWNTO 0);
lpm_ff_component : lpm_ff
GENERIC MAP (
lpm_fftype => "DFF",
lpm_type => "LPM_FF",
lpm_width => 5
)
PORT MAP (
clock => clock,
data => data,
q => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
-- Retrieval info: PRIVATE: ASET NUMERIC "0"
-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
-- Retrieval info: PRIVATE: DFF NUMERIC "1"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix"
-- Retrieval info: PRIVATE: SCLR NUMERIC "0"
-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: SSET NUMERIC "0"
-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "5"
-- Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "5"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
-- Retrieval info: USED_PORT: data 0 0 5 0 INPUT NODEFVAL data[4..0]
-- Retrieval info: USED_PORT: q 0 0 5 0 OUTPUT NODEFVAL q[4..0]
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 5 0 @q 0 0 5 0
-- Retrieval info: CONNECT: @data 0 0 5 0 data 0 0 5 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL gl_dff5.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL gl_dff5.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL gl_dff5.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL gl_dff5.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL gl_dff5_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
unlicense
|
simonspa/pixel-dtb-firmware
|
dtb/ROC_H_FSM.vhd
|
2
|
2237
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity ROC_H_FSM is
port (clk_i : in std_logic;
reset_i : in std_logic;
ROC_start_i : in std_logic;
serdat_i : in std_logic;
payload_o : out std_logic_vector(3 downto 0);
type_o : out std_logic_vector(3 downto 0);
wen_o : out std_logic);
end ROC_H_FSM;
architecture rtl of ROC_H_FSM is
type t_state is (waiting,
tick_RB3,
tick_RB2,
tick_RB1,
tick_RB0);
signal s_state : t_state;
--signal s_count : unsigned(3 downto 0);
begin
p_format: process (clk_i, reset_i)
begin -- process p_serin
if (reset_i = '1') then -- asynchronous reset
wen_o <= '0';
payload_o <= "0000";
type_o <= "0000";
s_state <= waiting;
elsif rising_edge(clk_i) then -- rising clock edge
case s_state is
-------------------------------------------------------------------------
when tick_RB3 =>
wen_o <= '0';
payload_o(3)<=serdat_i;
s_state <= tick_RB2;
-------------------------------------------------------------------------
when tick_RB2 =>
payload_o(2)<=serdat_i;
s_state <= tick_RB1;
-------------------------------------------------------------------------
when tick_RB1 =>
payload_o(1)<=serdat_i;
s_state <= tick_RB0;
-------------------------------------------------------------------------
when tick_RB0 =>
payload_o(0)<=serdat_i;
type_o <= "0111";
wen_o <= '1';
s_state <= waiting ;
-------------------------------------------------------------------------
-------------------------------------------------------------------------
when others =>
if ROC_start_i = '1' then
wen_o <= '0';
payload_o <= "0000";
s_state <= tick_RB3;
else
wen_o <= '0';
s_state <= waiting;
end if;
end case;
end if;
end process p_format;
end rtl;
|
unlicense
|
simonspa/pixel-dtb-firmware
|
dtb/SFL.vhd
|
2
|
2984
|
-- megafunction wizard: %Serial Flash Loader%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altserial_flash_loader
-- ============================================================
-- File Name: SFL.vhd
-- Megafunction Name(s):
-- altserial_flash_loader
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 222 10/21/2009 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2009 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY SFL IS
PORT
(
noe_in : IN STD_LOGIC
);
END SFL;
ARCHITECTURE SYN OF sfl IS
COMPONENT altserial_flash_loader
GENERIC (
enable_shared_access : STRING;
enhanced_mode : NATURAL;
intended_device_family : STRING;
lpm_type : STRING
);
PORT (
noe : IN STD_LOGIC
);
END COMPONENT;
BEGIN
altserial_flash_loader_component : altserial_flash_loader
GENERIC MAP (
enable_shared_access => "OFF",
enhanced_mode => 0,
intended_device_family => "Arria GX",
lpm_type => "altserial_flash_loader"
)
PORT MAP (
noe => noe_in
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria GX"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ENABLE_SHARED_ACCESS STRING "OFF"
-- Retrieval info: CONSTANT: ENHANCED_MODE NUMERIC "0"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria GX"
-- Retrieval info: USED_PORT: noe_in 0 0 0 0 INPUT NODEFVAL "noe_in"
-- Retrieval info: CONNECT: @noe 0 0 0 0 noe_in 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL SFL.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL SFL.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL SFL.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL SFL.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL SFL_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
|
unlicense
|
OrganicMonkeyMotion/fpga_experiments
|
small_board/LABS/digital_logic/vhdl/lab2/part4/part4_code.vhd
|
2
|
1807
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY part4_code IS
PORT(
BUTTONS : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
CONSTANTS : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
LED : OUT STD_LOGIC_VECTOR (6 DOWNTO 0);
DISP: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
clk_in : IN STD_LOGIC;
carry_in : IN STD_LOGIC;
carry_out : OUT STD_LOGIC
);
END part4_code;
ARCHITECTURE Behaviour of part4_code IS
SIGNAL carry : STD_LOGIC;
SIGNAL HEX_0, HEX_1, BLANK: STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL s_o : STD_LOGIC_VECTOR (3 DOWNTO 0);
COMPONENT segseven PORT ( SW : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
LEDSEG : OUT STD_LOGIC_VECTOR (6 DOWNTO 0)); END COMPONENT;
COMPONENT circuitb PORT ( SW : IN STD_LOGIC;
LEDSEG : OUT STD_LOGIC_VECTOR (6 DOWNTO 0)); END COMPONENT;
COMPONENT DE1_disp PORT ( HEX0, HEX1, HEX2, HEX3 : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
clk : IN STD_LOGIC;
HEX : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
DISPn: OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); END COMPONENT;
COMPONENT bcd_adder PORT (b_in : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
a_in : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
c_in : IN STD_LOGIC;
c_out : OUT STD_LOGIC;
s_out : OUT STD_LOGIC_VECTOR (3 DOWNTO 0));END COMPONENT;
BEGIN
BLANK <= "1111111";
S0 : segseven PORT MAP (SW=>s_o, LEDSEG=>HEX_0);
S1 : circuitb PORT MAP (SW=>carry, LEDSEG=>HEX_1);
DE1: DE1_disp PORT MAP (HEX0=>HEX_0, HEX1=>HEX_1, HEX2=>BLANK, HEX3=>BLANK, clk=>clk_in,HEX=>LED,DISPn=>DISP);
badder: bcd_adder PORT MAP (b_in=> NOT BUTTONS, a_in => CONSTANTS, c_in =>carry_in, c_out=> carry, s_out => s_o);
carry_out <= carry;
END Behaviour;
|
unlicense
|
OrganicMonkeyMotion/fpga_experiments
|
small_board/LABS/digital_logic/vhdl/lab2/part5/part4_code.vhd
|
2
|
1807
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY part4_code IS
PORT(
BUTTONS : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
CONSTANTS : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
LED : OUT STD_LOGIC_VECTOR (6 DOWNTO 0);
DISP: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
clk_in : IN STD_LOGIC;
carry_in : IN STD_LOGIC;
carry_out : OUT STD_LOGIC
);
END part4_code;
ARCHITECTURE Behaviour of part4_code IS
SIGNAL carry : STD_LOGIC;
SIGNAL HEX_0, HEX_1, BLANK: STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL s_o : STD_LOGIC_VECTOR (3 DOWNTO 0);
COMPONENT segseven PORT ( SW : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
LEDSEG : OUT STD_LOGIC_VECTOR (6 DOWNTO 0)); END COMPONENT;
COMPONENT circuitb PORT ( SW : IN STD_LOGIC;
LEDSEG : OUT STD_LOGIC_VECTOR (6 DOWNTO 0)); END COMPONENT;
COMPONENT DE1_disp PORT ( HEX0, HEX1, HEX2, HEX3 : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
clk : IN STD_LOGIC;
HEX : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
DISPn: OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); END COMPONENT;
COMPONENT bcd_adder PORT (b_in : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
a_in : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
c_in : IN STD_LOGIC;
c_out : OUT STD_LOGIC;
s_out : OUT STD_LOGIC_VECTOR (3 DOWNTO 0));END COMPONENT;
BEGIN
BLANK <= "1111111";
S0 : segseven PORT MAP (SW=>s_o, LEDSEG=>HEX_0);
S1 : circuitb PORT MAP (SW=>carry, LEDSEG=>HEX_1);
DE1: DE1_disp PORT MAP (HEX0=>HEX_0, HEX1=>HEX_1, HEX2=>BLANK, HEX3=>BLANK, clk=>clk_in,HEX=>LED,DISPn=>DISP);
badder: bcd_adder PORT MAP (b_in=> NOT BUTTONS, a_in => CONSTANTS, c_in =>carry_in, c_out=> carry, s_out => s_o);
carry_out <= carry;
END Behaviour;
|
unlicense
|
idinev/Desilog
|
tutorial/tute2/autogen/mypack.vhd
|
1
|
979
|
-----------------------------------------------------------
--------- AUTOGENERATED FILE, DO NOT EDIT -----------------
-----------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.desilog.all;
package mypack is
type MEM_CTL is record
act: std_ulogic;
write: std_ulogic;
addr: u8;
wdata: u8;
end record;
type MEM_RES is record
valid: std_ulogic;
busy: std_ulogic;
rdata: u8;
end record;
type MyEnum is (
MyEnum_one,
MyEnum_two,
MyEnum_three);
subtype myVec55 is unsigned(54 downto 0);
type myArr256_u8 is array(0 to 255) of u8;
function DoXorAnd (aa : u8; bb : u8; isXor : std_ulogic) return u8;
end package;
package body mypack is
function DoXorAnd (aa : u8; bb : u8; isXor : std_ulogic) return u8 is
variable result: u8;
begin
result := X"00"; -- local-var zero-init
if (isXor = '1') then
result := (aa xor bb);
else
result := (aa and bb);
end if;
end;
end;
|
unlicense
|
idinev/Desilog
|
tutorial/tute2/autogen/tute2.vhd
|
1
|
1704
|
-----------------------------------------------------------
--------- AUTOGENERATED FILE, DO NOT EDIT -----------------
-----------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.desilog.all;
use work.mypack.all;
use work.myentities.all;
--#------- tute2 ------------------------------------
architecture rtl of tute2 is
type myArr16_u4 is array(0 to 15) of u4;
type LOC_FSM is (
LOC_FSM_state1,
LOC_FSM_state2,
LOC_FSM_idle);
signal nextData: u8; -- reg
signal fsm: MyEnum; -- reg
----- internal regs/wires/etc --------
signal dg_c_memctl: MEM_CTL;
signal dg_c_memres: MEM_RES;
signal dg_o_memres: MEM_RES;
signal dg_w_resXorAnd: u8;
signal dg_c_nextData: u8;
signal dg_c_fsm: MyEnum;
begin
main: process (all)
begin
dg_c_memres <= dg_o_memres; -- reg preload
dg_w_resXorAnd <= X"00"; -- wire pre-zero-init
dg_c_nextData <= nextData; -- reg preload
dg_c_memres.valid <= '0';
dg_c_memres.busy <= '0';
if (memctl.act = '1') then
if (memctl.write = '1') then
dg_c_nextData <= memctl.wdata;
else
dg_c_memres.rdata <= nextData;
dg_c_memres.valid <= '1';
dg_c_nextData <= nextData + X"01";
end if;
end if;
dg_w_resXorAnd <= DoXorAnd(memctl.wdata, nextData, '1');
end process;
----[ sync clock pump for clk ]------
process begin
wait until rising_edge(clk_clk);
dg_o_memres <= dg_c_memres;
nextData <= dg_c_nextData;
fsm <= dg_c_fsm;
if clk_reset_n = '0' then
nextData <= X"22";
fsm <= MyEnum_one;
end if;
end process;
------[ output registers/wires/latches ] --------------
memres <= dg_o_memres;
resXorAnd <= dg_w_resXorAnd;
end;
|
unlicense
|
idinev/Desilog
|
tutorial/tute0/autogen/tute0_tb.vhd
|
1
|
2136
|
-----------------------------------------------------------
--------- AUTOGENERATED FILE, DO NOT EDIT -----------------
-----------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.desilog.all;
entity tute0_tb is end entity;
architecture testbench of tute0_tb is
signal success, done, error : std_ulogic := '0';
signal reset_n, clk : std_ulogic := '0';
signal counter : integer := 0;
signal xx : u8;
signal yy : u8;
signal someUnused : u8;
signal sum : u8;
signal totalSum : u8;
signal outXorWire : u8;
signal outLatch : u8;
begin
process(clk, reset_n) begin
someUnused <= X"77";
end process;
success <= done and (not error);
process begin
clk <= '0'; wait for 5 ps;
clk <= '1'; wait for 5 ps;
end process;
process begin
wait until rising_edge(clk);
counter <= counter + 1;
if counter >= 10 then
reset_n <= '1';
end if;
end process;
test: entity work.tute0 port map(
clk_clk => clk, clk_reset_n => reset_n,
xx => xx ,
yy => yy ,
someUnused => someUnused ,
sum => sum ,
totalSum => totalSum ,
outXorWire => outXorWire ,
outLatch => outLatch
);
process begin
wait until rising_edge(clk);
case counter is -- write values
when 15 =>
xx <= X"03";
yy <= X"04";
when 16 =>
xx <= X"55";
yy <= X"11";
when 17 =>
xx <= X"01";
yy <= X"01";
when others => null;
end case;
case counter is -- read+verify values
when 17 =>
if sum /= X"07" then
error <= '1';
end if;
if totalSum /= X"07" then
error <= '1';
end if;
when 18 =>
if sum /= X"66" then
error <= '1';
end if;
if totalSum /= X"6D" then
error <= '1';
end if;
when 19 =>
if sum /= X"02" then
error <= '1';
end if;
if totalSum /= X"6F" then
error <= '1';
end if;
when 25 => done <= '1';
if error='0' then
report "---------[ TESTBENCH SUCCESS ]---------------";
else
report "---------[ !!! TESTBENCH FAILURE !!! ]---------------";
end if;
when others => null;
end case;
end process;
end;
|
unlicense
|
idinev/Desilog
|
tutorial/tute1/autogen/tute1.vhd
|
1
|
2193
|
-----------------------------------------------------------
--------- AUTOGENERATED FILE, DO NOT EDIT -----------------
-----------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.desilog.all;
entity MyAdder is port(
clkAdd_clk, clkAdd_reset_n: in std_ulogic;
x: in u8; -- reg
y: in u8; -- reg
zout: out u8 -- reg
);
end entity;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.desilog.all;
entity tute1 is port(
clk_clk, clk_reset_n: in std_ulogic;
oout: out u8 -- reg
);
end entity;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.desilog.all;
--#------- MyAdder ------------------------------------
architecture rtl of MyAdder is
signal dg_o_zout: u8; -- reg
begin
main: process
begin
wait until rising_edge(clkAdd_clk)
dg_o_zout <= (x + y);
end process;
------[ output registers/wires/latches ] --------------
zout <= dg_o_zout;
end;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.desilog.all;
--#------- tute1 ------------------------------------
architecture rtl of tute1 is
signal dg_o_oout: u8; -- reg
----- sub-unit signals -------------
signal madd_x : u8;
signal madd_y : u8;
signal madd_zout : u8;
signal madd2_x : u8;
signal madd2_y : u8;
signal madd2_zout : u8;
signal madd2_clkAdd_clk, madd2_clkAdd_reset_n : std_ulogic;
begin
main: process
begin
wait until rising_edge(clk_clk)
madd_x <= X"01";
madd_y <= X"02";
madd2_y <= X"05";
dg_o_oout <= (madd_zout + madd2_zout);
end process;
-------[ sub-units ]-----------
madd : entity work.MyAdder port map(
clkAdd_clk => clk_clk,
clkAdd_reset_n => clk_reset_n,
x => madd_x,
y => madd_y,
zout => madd_zout
);
madd2 : entity work.MyAdder port map(
clkAdd_clk => madd2_clkAdd_clk,
clkAdd_reset_n => madd2_clkAdd_reset_n,
x => madd2_x,
y => madd2_y,
zout => madd2_zout
);
-------[ links ]----------
madd2_clkAdd_clk <= clk_clk;
madd2_clkAdd_reset_n <= clk_reset_n;
madd2_x <= madd_zout;
------[ output registers/wires/latches ] --------------
oout <= dg_o_oout;
end;
|
unlicense
|
augustollenz/pwm-controller
|
src/pwm.vhd
|
1
|
963
|
library ieee;
use ieee.std_logic_1164.all;
entity pwm is
port (
clk: in std_logic;
reset: in std_logic;
output: out std_logic
);
end pwm;
architecture example of pwm is
constant frequency: integer := 1000;
constant duty_cycle: integer range 0 to 100 := 50;
-- signal counter: integer range 0 to 1000 := 0;
signal counter: integer := 0;
signal out_buffer: std_logic := '0';
begin
process (clk, reset) is
begin
if reset = '0' then
output <= '0';
out_buffer <= '0';
counter <= 0;
elsif rising_edge(clk) then
counter <= counter + 1;
if counter = frequency then
counter <= 0;
out_buffer <= '0';
elsif counter > (100 - duty_cycle) * (frequency / 100) then
out_buffer <= '1';
end if;
end if;
end process;
output <= out_buffer;
end example;
|
unlicense
|
jza00425/ARM_Pipelining
|
lab3/outputs/1108-121610/sim/work/arm_mem/_primary.vhd
|
4
|
1464
|
library verilog;
use verilog.vl_types.all;
entity arm_mem is
generic(
data_start : integer := 268435456;
data_words : integer := 262144;
text_start : integer := 4194304;
text_words : integer := 65536;
--stack_top : integer type with unrepresentable value!
stack_words : integer := 65536;
--kdata_start : integer type with unrepresentable value!
kdata_words : integer := 262144;
--ktext_start : integer type with unrepresentable value!
ktext_words : integer := 16384
);
port(
addr1 : in vl_logic_vector(29 downto 0);
data_in1 : in vl_logic_vector(31 downto 0);
data_out1 : out vl_logic_vector(31 downto 0);
we1 : in vl_logic_vector(0 to 3);
excpt1 : out vl_logic;
allow_kernel1 : in vl_logic;
kernel1 : out vl_logic;
addr2 : in vl_logic_vector(29 downto 0);
data_in2 : in vl_logic_vector(31 downto 0);
data_out2 : out vl_logic_vector(31 downto 0);
we2 : in vl_logic_vector(0 to 3);
excpt2 : out vl_logic;
allow_kernel2 : in vl_logic;
kernel2 : out vl_logic;
rst_b : in vl_logic;
clk : in vl_logic
);
end arm_mem;
|
unlicense
|
jza00425/ARM_Pipelining
|
lab3/outputs/1108-121610/sim/work/arm_barrel_shift/_primary.vhd
|
3
|
509
|
library verilog;
use verilog.vl_types.all;
entity arm_barrel_shift is
port(
inst : in vl_logic_vector(31 downto 0);
rm_data_in : in vl_logic_vector(31 downto 0);
rs_data_in : in vl_logic_vector(31 downto 0);
cpsr : in vl_logic_vector(31 downto 0);
is_imm : in vl_logic;
operand2 : out vl_logic_vector(31 downto 0);
potential_cout : out vl_logic
);
end arm_barrel_shift;
|
unlicense
|
jza00425/ARM_Pipelining
|
lab3/outputs/1108-121610/sim/work/arm_alu/_primary.vhd
|
3
|
578
|
library verilog;
use verilog.vl_types.all;
entity arm_alu is
port(
alu_out : out vl_logic_vector(31 downto 0);
alu_cpsr : out vl_logic_vector(3 downto 0);
alu_op1 : in vl_logic_vector(31 downto 0);
alu_op2 : in vl_logic_vector(31 downto 0);
alu_sel : in vl_logic_vector(3 downto 0);
alu_cin : in vl_logic;
is_alu_for_mem_addr: in vl_logic;
up_down : in vl_logic;
potential_cout : in vl_logic
);
end arm_alu;
|
unlicense
|
jza00425/ARM_Pipelining
|
lab3/sim/work/regfile/_primary.vhd
|
4
|
1165
|
library verilog;
use verilog.vl_types.all;
entity regfile is
generic(
text_start : integer := 4194304
);
port(
rn_data : out vl_logic_vector(31 downto 0);
rm_data : out vl_logic_vector(31 downto 0);
rs_data : out vl_logic_vector(31 downto 0);
pc_out : out vl_logic_vector(31 downto 0);
cpsr_out : out vl_logic_vector(31 downto 0);
rn_num : in vl_logic_vector(3 downto 0);
rm_num : in vl_logic_vector(3 downto 0);
rs_num : in vl_logic_vector(3 downto 0);
rd_num : in vl_logic_vector(3 downto 0);
rd_data : in vl_logic_vector(31 downto 0);
rd_we : in vl_logic;
pc_in : in vl_logic_vector(31 downto 0);
pc_we : in vl_logic;
cpsr_in : in vl_logic_vector(31 downto 0);
cpsr_we : in vl_logic;
clk : in vl_logic;
rst_b : in vl_logic;
halted : in vl_logic
);
end regfile;
|
unlicense
|
jza00425/ARM_Pipelining
|
lab3/sim/work/arm_alu/_primary.vhd
|
1
|
621
|
library verilog;
use verilog.vl_types.all;
entity arm_alu is
port(
alu_or_mac : in vl_logic;
alu_op1 : in vl_logic_vector(31 downto 0);
alu_op2 : in vl_logic_vector(31 downto 0);
alu_sel : in vl_logic_vector(3 downto 0);
alu_cin : in vl_logic;
is_alu_for_mem_addr: in vl_logic;
up_down : in vl_logic;
potential_cout : in vl_logic;
alu_out : out vl_logic_vector(31 downto 0);
alu_cpsr : out vl_logic_vector(3 downto 0)
);
end arm_alu;
|
unlicense
|
jza00425/ARM_Pipelining
|
lab3/sim/work/arm_mac/_primary.vhd
|
1
|
490
|
library verilog;
use verilog.vl_types.all;
entity arm_mac is
port(
mac_op1 : in vl_logic_vector(31 downto 0);
mac_op2 : in vl_logic_vector(31 downto 0);
mac_acc : in vl_logic_vector(31 downto 0);
mac_sel : in vl_logic;
alu_or_mac : in vl_logic;
mac_out : out vl_logic_vector(31 downto 0);
mac_cpsr : out vl_logic_vector(3 downto 0)
);
end arm_mac;
|
unlicense
|
jza00425/ARM_Pipelining
|
lab3/outputs/1108-121610/sim/work/clock/_primary.vhd
|
3
|
229
|
library verilog;
use verilog.vl_types.all;
entity clock is
generic(
start : integer := 0;
halfPeriod : integer := 50
);
port(
clockSignal : out vl_logic
);
end clock;
|
unlicense
|
sahandKashani/TRDB-D5M
|
DE1-SoC/hw/hdl/DE1_SoC_TRDB_D5M_top_level.vhd
|
2
|
10224
|
-- #############################################################################
-- DE1_SoC_TRDB_D5M_top_level.vhd
--
-- BOARD : DE1-SoC from Terasic
-- Author : Sahand Kashani-Akhavan from Terasic documentation
-- Revision : 1.6
-- Creation date : 04/02/2015
--
-- Syntax Rule : GROUP_NAME_N[bit]
--
-- GROUP : specify a particular interface (ex: SDR_)
-- NAME : signal name (ex: CONFIG, D, ...)
-- bit : signal index
-- _N : to specify an active-low signal
-- #############################################################################
library ieee;
use ieee.std_logic_1164.all;
entity DE1_SoC_TRDB_D5M_top_level is
port(
---- ADC
--ADC_CS_n : out std_logic;
--ADC_DIN : out std_logic;
--ADC_DOUT : in std_logic;
--ADC_SCLK : out std_logic;
---- Audio
--AUD_ADCDAT : in std_logic;
--AUD_ADCLRCK : inout std_logic;
--AUD_BCLK : inout std_logic;
--AUD_DACDAT : out std_logic;
--AUD_DACLRCK : inout std_logic;
--AUD_XCK : out std_logic;
-- CLOCK
CLOCK_50 : in std_logic;
--CLOCK2_50 : in std_logic;
--CLOCK3_50 : in std_logic;
--CLOCK4_50 : in std_logic;
-- SDRAM
DRAM_ADDR : out std_logic_vector(12 downto 0);
DRAM_BA : out std_logic_vector(1 downto 0);
DRAM_CAS_N : out std_logic;
DRAM_CKE : out std_logic;
DRAM_CLK : out std_logic;
DRAM_CS_N : out std_logic;
DRAM_DQ : inout std_logic_vector(15 downto 0);
DRAM_LDQM : out std_logic;
DRAM_RAS_N : out std_logic;
DRAM_UDQM : out std_logic;
DRAM_WE_N : out std_logic;
---- I2C for Audio and Video-In
--FPGA_I2C_SCLK : out std_logic;
--FPGA_I2C_SDAT : inout std_logic;
---- SEG7
--HEX0_N : out std_logic_vector(6 downto 0);
--HEX1_N : out std_logic_vector(6 downto 0);
--HEX2_N : out std_logic_vector(6 downto 0);
--HEX3_N : out std_logic_vector(6 downto 0);
--HEX4_N : out std_logic_vector(6 downto 0);
--HEX5_N : out std_logic_vector(6 downto 0);
---- IR
--IRDA_RXD : in std_logic;
--IRDA_TXD : out std_logic;
---- KEY_N
--KEY_N : in std_logic_vector(3 downto 0);
---- LED
--LEDR : out std_logic_vector(9 downto 0);
---- PS2
--PS2_CLK : inout std_logic;
--PS2_CLK2 : inout std_logic;
--PS2_DAT : inout std_logic;
--PS2_DAT2 : inout std_logic;
---- SW
--SW : in std_logic_vector(9 downto 0);
---- Video-In
--TD_CLK27 : inout std_logic;
--TD_DATA : out std_logic_vector(7 downto 0);
--TD_HS : out std_logic;
--TD_RESET_N : out std_logic;
--TD_VS : out std_logic;
---- VGA
--VGA_B : out std_logic_vector(7 downto 0);
--VGA_BLANK_N : out std_logic;
--VGA_CLK : out std_logic;
--VGA_G : out std_logic_vector(7 downto 0);
--VGA_HS : out std_logic;
--VGA_R : out std_logic_vector(7 downto 0);
--VGA_SYNC_N : out std_logic;
--VGA_VS : out std_logic;
-- GPIO_0
GPIO_0_D5M_D : in std_logic_vector(11 downto 0);
GPIO_0_D5M_FVAL : in std_logic;
GPIO_0_D5M_LVAL : in std_logic;
GPIO_0_D5M_PIXCLK : in std_logic;
GPIO_0_D5M_RESET_N : out std_logic;
GPIO_0_D5M_SCLK : inout std_logic;
GPIO_0_D5M_SDATA : inout std_logic;
GPIO_0_D5M_STROBE : in std_logic;
GPIO_0_D5M_TRIGGER : out std_logic;
GPIO_0_D5M_XCLKIN : out std_logic
---- GPIO_1
--GPIO_1 : inout std_logic_vector(35 downto 0);
---- HPS
--HPS_CONV_USB_N : inout std_logic;
--HPS_DDR3_ADDR : out std_logic_vector(14 downto 0);
--HPS_DDR3_BA : out std_logic_vector(2 downto 0);
--HPS_DDR3_CAS_N : out std_logic;
--HPS_DDR3_CK_N : out std_logic;
--HPS_DDR3_CK_P : out std_logic;
--HPS_DDR3_CKE : out std_logic;
--HPS_DDR3_CS_N : out std_logic;
--HPS_DDR3_DM : out std_logic_vector(3 downto 0);
--HPS_DDR3_DQ : inout std_logic_vector(31 downto 0);
--HPS_DDR3_DQS_N : inout std_logic_vector(3 downto 0);
--HPS_DDR3_DQS_P : inout std_logic_vector(3 downto 0);
--HPS_DDR3_ODT : out std_logic;
--HPS_DDR3_RAS_N : out std_logic;
--HPS_DDR3_RESET_N : out std_logic;
--HPS_DDR3_RZQ : in std_logic;
--HPS_DDR3_WE_N : out std_logic;
--HPS_ENET_GTX_CLK : out std_logic;
--HPS_ENET_INT_N : inout std_logic;
--HPS_ENET_MDC : out std_logic;
--HPS_ENET_MDIO : inout std_logic;
--HPS_ENET_RX_CLK : in std_logic;
--HPS_ENET_RX_DATA : in std_logic_vector(3 downto 0);
--HPS_ENET_RX_DV : in std_logic;
--HPS_ENET_TX_DATA : out std_logic_vector(3 downto 0);
--HPS_ENET_TX_EN : out std_logic;
--HPS_FLASH_DATA : inout std_logic_vector(3 downto 0);
--HPS_FLASH_DCLK : out std_logic;
--HPS_FLASH_NCSO : out std_logic;
--HPS_GSENSOR_INT : inout std_logic;
--HPS_I2C_CONTROL : inout std_logic;
--HPS_I2C1_SCLK : inout std_logic;
--HPS_I2C1_SDAT : inout std_logic;
--HPS_I2C2_SCLK : inout std_logic;
--HPS_I2C2_SDAT : inout std_logic;
--HPS_KEY_N : inout std_logic;
--HPS_LED : inout std_logic;
--HPS_LTC_GPIO : inout std_logic;
--HPS_SD_CLK : out std_logic;
--HPS_SD_CMD : inout std_logic;
--HPS_SD_DATA : inout std_logic_vector(3 downto 0);
--HPS_SPIM_CLK : out std_logic;
--HPS_SPIM_MISO : in std_logic;
--HPS_SPIM_MOSI : out std_logic;
--HPS_SPIM_SS : inout std_logic;
--HPS_UART_RX : in std_logic;
--HPS_UART_TX : out std_logic;
--HPS_USB_CLKOUT : in std_logic;
--HPS_USB_DATA : inout std_logic_vector(7 downto 0);
--HPS_USB_DIR : in std_logic;
--HPS_USB_NXT : in std_logic;
--HPS_USB_STP : out std_logic
);
end entity DE1_SoC_TRDB_D5M_top_level;
architecture rtl of DE1_SoC_TRDB_D5M_top_level is
component system is
port(
clk_clk : in std_logic := 'X';
reset_reset_n : in std_logic := 'X';
sdram_clk_clk : out std_logic;
sdram_controller_addr : out std_logic_vector(12 downto 0);
sdram_controller_ba : out std_logic_vector(1 downto 0);
sdram_controller_cas_n : out std_logic;
sdram_controller_cke : out std_logic;
sdram_controller_cs_n : out std_logic;
sdram_controller_dq : inout std_logic_vector(15 downto 0) := (others => 'X');
sdram_controller_dqm : out std_logic_vector(1 downto 0);
sdram_controller_ras_n : out std_logic;
sdram_controller_we_n : out std_logic;
trdb_d5m_xclkin_clk : out std_logic;
trdb_d5m_cmos_sensor_frame_valid : in std_logic := 'X';
trdb_d5m_cmos_sensor_line_valid : in std_logic := 'X';
trdb_d5m_cmos_sensor_data : in std_logic_vector(11 downto 0) := (others => 'X');
trdb_d5m_i2c_scl : inout std_logic := 'X';
trdb_d5m_i2c_sda : inout std_logic := 'X';
trdb_d5m_pixclk_clk : in std_logic := 'X'
);
end component system;
begin
GPIO_0_D5M_RESET_N <= '1';
GPIO_0_D5M_TRIGGER <= '0';
system_inst : component system
port map(
clk_clk => CLOCK_50,
reset_reset_n => '1',
sdram_clk_clk => DRAM_CLK,
sdram_controller_addr => DRAM_ADDR,
sdram_controller_ba => DRAM_BA,
sdram_controller_cas_n => DRAM_CAS_N,
sdram_controller_cke => DRAM_CKE,
sdram_controller_cs_n => DRAM_CS_N,
sdram_controller_dq => DRAM_DQ,
sdram_controller_dqm(1) => DRAM_UDQM,
sdram_controller_dqm(0) => DRAM_LDQM,
sdram_controller_ras_n => DRAM_RAS_N,
sdram_controller_we_n => DRAM_WE_N,
trdb_d5m_xclkin_clk => GPIO_0_D5M_XCLKIN,
trdb_d5m_cmos_sensor_frame_valid => GPIO_0_D5M_FVAL,
trdb_d5m_cmos_sensor_line_valid => GPIO_0_D5M_LVAL,
trdb_d5m_cmos_sensor_data => GPIO_0_D5M_D,
trdb_d5m_i2c_scl => GPIO_0_D5M_SCLK,
trdb_d5m_i2c_sda => GPIO_0_D5M_SDATA,
trdb_d5m_pixclk_clk => GPIO_0_D5M_PIXCLK
);
end;
|
unlicense
|
sahandKashani/TRDB-D5M
|
DE1-SoC/hw/hdl/i2c/hdl/i2c_core.vhd
|
5
|
21685
|
------------------------------------------------------
-- i2c_core.vhd - I2C core V2 logic
------------------------------------------------------
-- Author : Cédric Gaudin
-- Version : 0.4 alpha
-- History :
-- 20-mar-2002 CG 0.1 initial alpha release
-- 22-mar-2002 CG 0.2 complete rewrite
-- 27-mar-2002 CG 0.3 minor corrections
-- 02-apr-2002 CG 0.4 sync. of outputs
------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity i2c_core is
port(
-- I2C signals
sda_in : in std_logic;
scl_in : in std_logic;
sda_out : out std_logic;
scl_out : out std_logic;
-- interface signals
clk : in std_logic;
rst : in std_logic;
sclk : in std_logic;
ack_in : in std_logic;
ack_out : out std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
cmd_start : in std_logic;
cmd_stop : in std_logic;
cmd_read : in std_logic;
cmd_write : in std_logic;
cmd_done_ack : in std_logic;
cmd_done : out std_logic;
busy : out std_logic
-- debug signals
-- state : out std_logic_vector(5 downto 0)
);
end i2c_core;
architecture behavorial of i2c_core is
type state_type is (
s_Reset, s_Idle, s_Done, s_DoneAck,
s_Start_A, s_Start_B, s_Start_C, s_Start_D,
s_Stop_A, s_Stop_B, s_Stop_C,
s_Rd_A, s_Rd_B, s_Rd_C, s_Rd_D, s_Rd_E, s_Rd_F,
s_RdAck_A, s_RdAck_B, s_RdAck_C, s_RdAck_D, s_RdAck_E,
s_Wr_A, s_Wr_B, s_Wr_C, s_Wr_D, s_Wr_E,
s_WrAck_A, s_WrAck_B, s_WrAck_C, s_WrAck_D
);
-- data output register
signal i_dout_ld : std_logic;
signal i_dout : std_logic_vector(7 downto 0);
-- ack output register
signal i_ack_out_ld : std_logic;
signal i_ack_out : std_logic;
-- data input bit
signal i_data_in : std_logic;
-- bit counter
signal i_ctr : unsigned(2 downto 0);
signal i_ctr_incr : std_logic;
signal i_ctr_clr : std_logic;
signal p_state : state_type;
signal n_state : state_type;
signal i_scl_out : std_logic;
signal i_sda_out : std_logic;
signal i_sclk_en : std_logic;
signal i_cmd_done : std_logic;
signal i_cmd_go : std_logic;
signal i_busy : std_logic;
begin
-- syncronize output signals
output_sync : process(clk, rst)
begin
if (rst = '1') then
scl_out <= '1';
sda_out <= '1';
data_out <= (others => '0');
ack_out <= '0';
busy <= '0';
cmd_done <= '0';
elsif (rising_edge(clk)) then
scl_out <= i_scl_out;
sda_out <= i_sda_out;
data_out <= i_dout;
ack_out <= i_ack_out;
busy <= i_busy;
cmd_done <= i_cmd_done;
end if;
end process output_sync;
-- select current bit
data_input_selector : process(i_ctr, data_in)
begin
case i_ctr is
when "000" => i_data_in <= data_in(7);
when "001" => i_data_in <= data_in(6);
when "010" => i_data_in <= data_in(5);
when "011" => i_data_in <= data_in(4);
when "100" => i_data_in <= data_in(3);
when "101" => i_data_in <= data_in(2);
when "110" => i_data_in <= data_in(1);
when "111" => i_data_in <= data_in(0);
when others => null;
end case;
end process data_input_selector;
-- indicate start of command
i_cmd_go <= (cmd_read OR cmd_write) AND NOT i_busy;
-- i2c bit counter
counter : process(clk, rst)
begin
if (rst = '1') then
i_ctr <= (others => '0');
elsif (rising_edge(clk)) then
if (i_ctr_clr = '1') then
i_ctr <= (others => '0');
elsif (i_ctr_incr = '1') then
i_ctr <= i_ctr + 1;
end if;
end if;
end process counter;
-- data output register
dout_reg : process(clk, rst)
begin
if (rst = '1') then
i_dout <= (others => '0');
elsif (rising_edge(clk)) then
if (i_dout_ld = '1') then
case i_ctr is
when "000" => i_dout(7) <= sda_in;
when "001" => i_dout(6) <= sda_in;
when "010" => i_dout(5) <= sda_in;
when "011" => i_dout(4) <= sda_in;
when "100" => i_dout(3) <= sda_in;
when "101" => i_dout(2) <= sda_in;
when "110" => i_dout(1) <= sda_in;
when "111" => i_dout(0) <= sda_in;
when others => null;
end case;
end if;
end if;
end process dout_reg;
-- ack bit output register
ack_out_reg : process(clk, rst)
begin
if (rst = '1') then
i_ack_out <= '0';
elsif (rising_edge(clk)) then
if (i_ack_out_ld = '1') then
i_ack_out <= sda_in;
end if;
end if;
end process ack_out_reg;
-- i2c send / receive byte
i2c_sync : process(rst, clk)
begin
if (rst = '1') then
p_state <= s_Reset;
elsif (rising_edge(clk)) then
if ((sclk = '1' and i_sclk_en = '1') or i_sclk_en = '0') then
p_state <= n_state;
end if;
end if;
end process i2c_sync;
i2c_comb : process(p_state, sda_in, scl_in, i_cmd_go, i_ctr, ack_in, i_data_in, cmd_start, cmd_stop, cmd_write, cmd_read, cmd_done_ack)
begin
n_state <= p_state;
--n_state <= p_state;
i_sclk_en <= '0';
i_busy <= '0';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
--i_dout_ld <= '0';
--i_ack_out_ld <= '0';
i_sda_out <= sda_in;
i_scl_out <= scl_in;
--state <= "111111";
case p_state is
when s_Reset =>
--state <= "000000";
i_sclk_en <= '0';
i_busy <= '0';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= '1';
n_state <= s_Idle;
when s_Idle =>
--state <= "000001";
i_sclk_en <= '0';
i_busy <= '0';
i_ctr_clr <= '1';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= sda_in;
i_scl_out <= scl_in;
if (i_cmd_go = '1') then
if (cmd_start = '1') then
-- do a START
n_state <= s_Start_A;
elsif (cmd_write = '1') then
-- do a WRITE
n_state <= s_Wr_A;
elsif (cmd_read = '1') then
-- do a READ
n_state <= s_Rd_A;
end if;
end if;
when s_Start_A =>
--state <= "001000";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= scl_in;
n_state <= s_Start_B;
when s_Start_B =>
--state <= "001001";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= '1';
n_state <= s_Start_C;
when s_Start_C =>
--state <= "001010";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '0';
i_scl_out <= '1';
n_state <= s_Start_D;
when s_Start_D =>
--state <= "001011";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '0';
i_scl_out <= '0';
if (cmd_write = '1') then
-- do a WRITE
n_state <= s_Wr_A;
elsif (cmd_read = '1') then
-- do a READ
n_state <= s_Rd_A;
end if;
when s_Rd_A =>
--state <= "010000";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= '0';
n_state <= s_Rd_B;
when s_Rd_B =>
--state <= "010001";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= '1';
n_state <= s_Rd_C;
when s_Rd_C =>
--state <= "010010";
i_sclk_en <= '0';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '1';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= '1';
n_state <= s_Rd_D;
when s_Rd_D =>
--state <= "010011";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= '1';
n_state <= s_Rd_E;
when s_Rd_E =>
--state <= "010100";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= '0';
if (i_ctr = 7) then
-- do ACKOUT
n_state <= s_WrAck_A;
else
-- increment bit counter
n_state <= s_Rd_F;
end if;
when s_Rd_F =>
--state <= "010101";
i_sclk_en <= '0';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '1';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= '0';
n_state <= s_Rd_A;
when s_WrAck_A =>
--state <= "011000";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= ack_in;
i_scl_out <= '0';
n_state <= s_WrAck_B;
when s_WrAck_B =>
--state <= "011001";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= ack_in;
i_scl_out <= '1';
n_state <= s_WrAck_C;
when s_WrAck_C =>
--state <= "011010";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= ack_in;
i_scl_out <= '1';
n_state <= s_WrAck_D;
when s_WrAck_D =>
--state <= "011011";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= ack_in;
i_scl_out <= '0';
-- do a STOP ?
if (cmd_stop = '1') then
n_state <= s_Stop_A;
else
-- we are DONE
n_state <= s_Done;
end if;
when s_Wr_A =>
--state <= "100000";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= i_data_in;
i_scl_out <= '0';
n_state <= s_Wr_B;
when s_Wr_B =>
--state <= "100001";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= i_data_in;
i_scl_out <= '1';
n_state <= s_Wr_C;
when s_Wr_C =>
--state <= "100010";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= i_data_in;
i_scl_out <= '1';
n_state <= s_Wr_D;
when s_Wr_D =>
--state <= "100011";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= i_data_in;
i_scl_out <= '0';
if (i_ctr = 7) then
-- do ACKIN
n_state <= s_RdAck_A;
else
-- increment bit counter
n_state <= s_Wr_E;
end if;
when s_Wr_E =>
--state <= "100100";
i_sclk_en <= '0';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '1';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= i_data_in;
i_scl_out <= '0';
n_state <= s_Wr_A;
when s_RdAck_A =>
--state <= "101000";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= '0';
n_state <= s_RdAck_B;
when s_RdAck_B =>
--state <= "101001";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= '1';
n_state <= s_RdAck_C;
when s_RdAck_C =>
--state <= "101010";
i_sclk_en <= '0';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '1';
i_sda_out <= '1';
i_scl_out <= '1';
n_state <= s_RdAck_D;
when s_RdAck_D =>
--state <= "101011";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= '1';
n_state <= s_RdAck_E;
when s_RdAck_E =>
--state <= "101100";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= '0';
if (cmd_stop = '1') then
-- do a STOP
n_state <= s_Stop_A;
else
-- we are DONE
n_state <= s_Done;
end if;
when s_Stop_A =>
--state <= "111000";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '0';
i_scl_out <= '0';
n_state <= s_Stop_B;
when s_Stop_B =>
--state <= "111001";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '0';
i_scl_out <= '1';
n_state <= s_Stop_C;
when s_Stop_C =>
--state <= "111010";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= '1';
n_state <= s_Done;
when s_Done =>
--state <= "000010";
i_sclk_en <= '0';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '1';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= sda_in;
i_scl_out <= scl_in;
n_state <= s_DoneAck;
when s_DoneAck =>
--state <= "000011";
i_sclk_en <= '0';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '1';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= sda_in;
i_scl_out <= scl_in;
if (cmd_done_ack = '1') then
n_state <= s_Idle;
end if;
end case;
end process i2c_comb;
end behavorial;
|
unlicense
|
sahandKashani/TRDB-D5M
|
DE0-Nano/hw/hdl/cmos_sensor_input/hdl/cmos_sensor_input_synchronizer.vhd
|
5
|
2616
|
library ieee;
use ieee.std_logic_1164.all;
use work.cmos_sensor_input_constants.all;
entity cmos_sensor_input_synchronizer is
generic(
PIX_DEPTH : positive;
SAMPLE_EDGE : string
);
port(
clk : in std_logic;
reset : in std_logic;
-- cmos sensor
frame_valid_in : in std_logic;
line_valid_in : in std_logic;
data_in : in std_logic_vector(PIX_DEPTH - 1 downto 0);
-- sampler
frame_valid_out : out std_logic;
line_valid_out : out std_logic;
data_out : out std_logic_vector(PIX_DEPTH - 1 downto 0)
);
end entity cmos_sensor_input_synchronizer;
architecture rtl of cmos_sensor_input_synchronizer is
signal reg_frame_valid_in : std_logic;
signal reg_line_valid_in : std_logic;
signal reg_data_in : std_logic_vector(data_in'range);
-- registered outputs
signal reg_frame_valid_out : std_logic;
signal reg_line_valid_out : std_logic;
signal reg_data_out : std_logic_vector(data_out'range);
begin
-- registered outputs
frame_valid_out <= reg_frame_valid_out;
line_valid_out <= reg_line_valid_out;
data_out <= reg_data_out;
process(clk, reset)
begin
if SAMPLE_EDGE = "RISING" then
if reset = '1' then
reg_frame_valid_in <= '0';
reg_line_valid_in <= '0';
reg_data_in <= (others => '0');
elsif rising_edge(clk) then
reg_frame_valid_in <= frame_valid_in;
reg_line_valid_in <= line_valid_in;
reg_data_in <= data_in;
end if;
elsif SAMPLE_EDGE = "FALLING" then
if reset = '1' then
reg_frame_valid_in <= '0';
reg_line_valid_in <= '0';
reg_data_in <= (others => '0');
elsif falling_edge(clk) then
reg_frame_valid_in <= frame_valid_in;
reg_line_valid_in <= line_valid_in;
reg_data_in <= data_in;
end if;
end if;
end process;
process(clk, reset)
begin
if reset = '1' then
reg_frame_valid_out <= '0';
reg_line_valid_out <= '0';
reg_data_out <= (others => '0');
elsif rising_edge(clk) then
reg_frame_valid_out <= reg_frame_valid_in;
reg_line_valid_out <= reg_line_valid_in;
reg_data_out <= reg_data_in;
end if;
end process;
end architecture rtl;
|
unlicense
|
sahandKashani/TRDB-D5M
|
DE1-SoC/hw/hdl/cmos_sensor_input/hdl/cmos_sensor_input_packer.vhd
|
5
|
3601
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.cmos_sensor_input_constants.all;
entity cmos_sensor_input_packer is
generic(
PIX_DEPTH : positive;
PACK_WIDTH : positive
);
port(
clk : in std_logic;
reset : in std_logic;
-- avalon_mm_slave
stop_and_reset : in std_logic;
-- sampler / debayer
valid_in : in std_logic;
data_in : in std_logic_vector(PIX_DEPTH - 1 downto 0);
start_of_frame_in : in std_logic;
end_of_frame_in : in std_logic;
-- fifo
valid_out : out std_logic;
data_out : out std_logic_vector(PACK_WIDTH - 1 downto 0);
end_of_frame_out : out std_logic
);
end entity cmos_sensor_input_packer;
architecture rtl of cmos_sensor_input_packer is
constant COMPRESSED_PIX_COUNT : positive := floor_div(data_out'length, PIX_DEPTH);
signal reg_count : unsigned(bit_width(COMPRESSED_PIX_COUNT) - 1 downto 0);
signal reg_data_out : std_logic_vector((COMPRESSED_PIX_COUNT - 1) * PIX_DEPTH - 1 downto 0);
begin
process(clk, reset)
begin
if reset = '1' then
reg_count <= (others => '0');
reg_data_out <= (others => '0');
elsif rising_edge(clk) then
valid_out <= '0';
data_out <= (others => '0');
end_of_frame_out <= '0';
if stop_and_reset = '1' then
reg_count <= to_unsigned(0, reg_count'length);
reg_data_out <= (others => '0');
else
if valid_in = '1' then
if start_of_frame_in = '1' then
reg_count <= to_unsigned(1, reg_count'length);
reg_data_out(PIX_DEPTH - 1 downto 0) <= data_in;
reg_data_out(reg_data_out'length - 1 downto PIX_DEPTH) <= (others => '0');
elsif end_of_frame_in = '1' then
valid_out <= '1';
data_out(PIX_DEPTH - 1 downto 0) <= data_in;
data_out(reg_data_out'length + PIX_DEPTH - 1 downto PIX_DEPTH) <= reg_data_out;
end_of_frame_out <= '1';
reg_count <= to_unsigned(0, reg_count'length);
elsif reg_count < COMPRESSED_PIX_COUNT - 1 then
reg_count <= reg_count + 1;
reg_data_out(PIX_DEPTH - 1 downto 0) <= data_in;
reg_data_out(reg_data_out'length - 1 downto PIX_DEPTH) <= reg_data_out(reg_data_out'length - PIX_DEPTH - 1 downto 0);
elsif reg_count = COMPRESSED_PIX_COUNT - 1 then
valid_out <= '1';
data_out(PIX_DEPTH - 1 downto 0) <= data_in;
data_out(reg_data_out'length + PIX_DEPTH - 1 downto PIX_DEPTH) <= reg_data_out;
reg_count <= to_unsigned(0, reg_count'length);
reg_data_out <= (others => '0');
end if;
end if;
end if;
end if;
end process;
end architecture rtl;
|
unlicense
|
sahandKashani/HDL-IP-cores
|
cmos_sensor_output_generator/hdl/cmos_sensor_output_generator_constants.vhd
|
1
|
3191
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
package cmos_sensor_output_generator_constants is
constant CMOS_SENSOR_OUTPUT_GENERATOR_MM_S_DATA_WIDTH : positive := 32;
-- register offsets
constant CMOS_SENSOR_OUTPUT_GENERATOR_CONFIG_FRAME_WIDTH_OFST : std_logic_vector(2 downto 0) := "000"; -- RW
constant CMOS_SENSOR_OUTPUT_GENERATOR_CONFIG_FRAME_HEIGHT_OFST : std_logic_vector(2 downto 0) := "001"; -- RW
constant CMOS_SENSOR_OUTPUT_GENERATOR_CONFIG_FRAME_FRAME_BLANK_OFST : std_logic_vector(2 downto 0) := "010"; -- RW
constant CMOS_SENSOR_OUTPUT_GENERATOR_CONFIG_FRAME_LINE_BLANK_OFST : std_logic_vector(2 downto 0) := "011"; -- RW
constant CMOS_SENSOR_OUTPUT_GENERATOR_CONFIG_LINE_LINE_BLANK_OFST : std_logic_vector(2 downto 0) := "100"; -- RW
constant CMOS_SENSOR_OUTPUT_GENERATOR_CONFIG_LINE_FRAME_BLANK_OFST : std_logic_vector(2 downto 0) := "101"; -- RW
constant CMOS_SENSOR_OUTPUT_GENERATOR_COMMAND_OFST : std_logic_vector(2 downto 0) := "110"; -- WO
constant CMOS_SENSOR_OUTPUT_GENERATOR_STATUS_OFST : std_logic_vector(2 downto 0) := "111"; -- RO
-- CONFIG register minimum values
constant CMOS_SENSOR_OUTPUT_GENERATOR_CONFIG_FRAME_WIDTH_MIN : positive := 1;
constant CMOS_SENSOR_OUTPUT_GENERATOR_CONFIG_FRAME_HEIGHT_MIN : positive := 1;
constant CMOS_SENSOR_OUTPUT_GENERATOR_CONFIG_FRAME_FRAME_BLANK_MIN : positive := 1;
constant CMOS_SENSOR_OUTPUT_GENERATOR_CONFIG_FRAME_LINE_BLANK_MIN : natural := 0;
constant CMOS_SENSOR_OUTPUT_GENERATOR_CONFIG_LINE_LINE_BLANK_MIN : positive := 1;
constant CMOS_SENSOR_OUTPUT_GENERATOR_CONFIG_LINE_FRAME_BLANK_MIN : natural := 0;
-- COMMAND register
constant CMOS_SENSOR_OUTPUT_GENERATOR_COMMAND_WIDTH : positive := 1;
constant CMOS_SENSOR_OUTPUT_GENERATOR_COMMAND_STOP : std_logic_vector(0 downto 0) := "0";
constant CMOS_SENSOR_OUTPUT_GENERATOR_COMMAND_START : std_logic_vector(0 downto 0) := "1";
-- STATUS register
constant CMOS_SENSOR_OUTPUT_GENERATOR_STATUS_IDLE : std_logic_vector(CMOS_SENSOR_OUTPUT_GENERATOR_MM_S_DATA_WIDTH - 1 downto 0) := X"00000001";
constant CMOS_SENSOR_OUTPUT_GENERATOR_STATUS_BUSY : std_logic_vector(CMOS_SENSOR_OUTPUT_GENERATOR_MM_S_DATA_WIDTH - 1 downto 0) := X"00000000";
function ceil_log2(num : positive) return natural;
function bit_width(num : positive) return positive;
function max(left : positive; right : positive) return positive;
end package cmos_sensor_output_generator_constants;
package body cmos_sensor_output_generator_constants is
function ceil_log2(num : positive) return natural is
begin
return integer(ceil(log2(real(num))));
end function ceil_log2;
function bit_width(num : positive) return positive is
begin
return ceil_log2(num + 1);
end function bit_width;
function max(left : positive; right : positive) return positive is
begin
if left > right then
return left;
else
return right;
end if;
end max;
end package body cmos_sensor_output_generator_constants;
|
unlicense
|
Nibble-Knowledge/cpu-vhdl
|
Nibble_Knowledge_CPU/netgen/synthesis/CPU_synthesis.vhd
|
1
|
88074
|
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: P.20131013
-- \ \ Application: netgen
-- / / Filename: CPU_synthesis.vhd
-- /___/ /\ Timestamp: Sat Oct 31 19:35:20 2015
-- \ \ / \
-- \___\/\___\
--
-- Command : -intstyle ise -ar Structure -tm CPU -w -dir netgen/synthesis -ofmt vhdl -sim CPU.ngc CPU_synthesis.vhd
-- Device : xc3s250e-5-vq100
-- Input file : CPU.ngc
-- Output file : C:\Users\Colton\Desktop\Nibble_Knowledge_CPU\netgen\synthesis\CPU_synthesis.vhd
-- # of Entities : 1
-- Design Name : CPU
-- Xilinx : C:\Xilinx\14.7\ISE_DS\ISE\
--
-- Purpose:
-- This VHDL netlist is a verification model and uses simulation
-- primitives which may not represent the true implementation of the
-- device, however the netlist is functionally correct and should not
-- be modified. This file cannot be synthesized and should only be used
-- with supported simulation tools.
--
-- Reference:
-- Command Line Tools User Guide, Chapter 23
-- Synthesis and Simulation Design Guide, Chapter 6
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;
entity CPU is
port (
clk : in STD_LOGIC := 'X';
clk_out : out STD_LOGIC;
ram_write_enable : out STD_LOGIC;
reset : in STD_LOGIC := 'X';
ram_data : inout STD_LOGIC_VECTOR ( 3 downto 0 );
a_data : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_address : out STD_LOGIC_VECTOR ( 15 downto 0 )
);
end CPU;
architecture Structure of CPU is
signal Intern_clock_hundredHzClock_Mcount_current_count : STD_LOGIC;
signal Intern_clock_hundredHzClock_Mcount_current_count1 : STD_LOGIC;
signal Intern_clock_hundredHzClock_Mcount_current_count2 : STD_LOGIC;
signal Intern_clock_hundredHzClock_Mcount_current_count3 : STD_LOGIC;
signal Intern_clock_hundredHzClock_i_zero_8 : STD_LOGIC;
signal Intern_clock_hundredHzClock_i_zero_or0000_9 : STD_LOGIC;
signal Intern_clock_kiloHzClock_Mcount_current_count_cy_0_rt_11 : STD_LOGIC;
signal Intern_clock_kiloHzClock_Mcount_current_count_eqn_0 : STD_LOGIC;
signal Intern_clock_kiloHzClock_Mcount_current_count_eqn_1 : STD_LOGIC;
signal Intern_clock_kiloHzClock_Mcount_current_count_eqn_10 : STD_LOGIC;
signal Intern_clock_kiloHzClock_Mcount_current_count_eqn_11 : STD_LOGIC;
signal Intern_clock_kiloHzClock_Mcount_current_count_eqn_12 : STD_LOGIC;
signal Intern_clock_kiloHzClock_Mcount_current_count_eqn_13 : STD_LOGIC;
signal Intern_clock_kiloHzClock_Mcount_current_count_eqn_14 : STD_LOGIC;
signal Intern_clock_kiloHzClock_Mcount_current_count_eqn_2 : STD_LOGIC;
signal Intern_clock_kiloHzClock_Mcount_current_count_eqn_3 : STD_LOGIC;
signal Intern_clock_kiloHzClock_Mcount_current_count_eqn_4 : STD_LOGIC;
signal Intern_clock_kiloHzClock_Mcount_current_count_eqn_5 : STD_LOGIC;
signal Intern_clock_kiloHzClock_Mcount_current_count_eqn_6 : STD_LOGIC;
signal Intern_clock_kiloHzClock_Mcount_current_count_eqn_7 : STD_LOGIC;
signal Intern_clock_kiloHzClock_Mcount_current_count_eqn_8 : STD_LOGIC;
signal Intern_clock_kiloHzClock_Mcount_current_count_eqn_9 : STD_LOGIC;
signal Intern_clock_kiloHzClock_current_count_cmp_eq0000 : STD_LOGIC;
signal Intern_clock_kiloHzClock_current_count_cmp_eq000012_70 : STD_LOGIC;
signal Intern_clock_kiloHzClock_current_count_cmp_eq000025_71 : STD_LOGIC;
signal Intern_clock_kiloHzClock_current_count_cmp_eq000049_72 : STD_LOGIC;
signal Intern_clock_kiloHzClock_current_count_cmp_eq000058_73 : STD_LOGIC;
signal Intern_clock_kiloHzClock_i_zero_74 : STD_LOGIC;
signal Intern_clock_kiloHzClock_i_zero_or0000 : STD_LOGIC;
signal Intern_clock_oneHZClock_Mcount_current_count : STD_LOGIC;
signal Intern_clock_oneHZClock_Mcount_current_count1 : STD_LOGIC;
signal Intern_clock_oneHZClock_Mcount_current_count2 : STD_LOGIC;
signal Intern_clock_oneHZClock_Mcount_current_count3 : STD_LOGIC;
signal Intern_clock_oneHZClock_i_zero_84 : STD_LOGIC;
signal Intern_clock_oneHZClock_i_zero1 : STD_LOGIC;
signal Intern_clock_oneHZClock_i_zero_or0000_86 : STD_LOGIC;
signal Intern_clock_tenHzClock_Mcount_current_count : STD_LOGIC;
signal Intern_clock_tenHzClock_Mcount_current_count1 : STD_LOGIC;
signal Intern_clock_tenHzClock_Mcount_current_count2 : STD_LOGIC;
signal Intern_clock_tenHzClock_Mcount_current_count3 : STD_LOGIC;
signal Intern_clock_tenHzClock_i_zero_95 : STD_LOGIC;
signal Intern_clock_tenHzClock_i_zero_or0000_96 : STD_LOGIC;
signal MEM_Mcount_i_nibbleCount : STD_LOGIC;
signal MEM_Mcount_i_nibbleCount1 : STD_LOGIC;
signal MEM_q_0_not0001 : STD_LOGIC;
signal MEM_q_10_not0001 : STD_LOGIC;
signal MEM_q_12_not0001 : STD_LOGIC;
signal MEM_q_4_not0001 : STD_LOGIC;
signal N0 : STD_LOGIC;
signal N1 : STD_LOGIC;
signal N102 : STD_LOGIC;
signal N104 : STD_LOGIC;
signal N106 : STD_LOGIC;
signal N107 : STD_LOGIC;
signal N108 : STD_LOGIC;
signal N109 : STD_LOGIC;
signal N11 : STD_LOGIC;
signal N110 : STD_LOGIC;
signal N111 : STD_LOGIC;
signal N114 : STD_LOGIC;
signal N120 : STD_LOGIC;
signal N122 : STD_LOGIC;
signal N123 : STD_LOGIC;
signal N124 : STD_LOGIC;
signal N125 : STD_LOGIC;
signal N126 : STD_LOGIC;
signal N127 : STD_LOGIC;
signal N128 : STD_LOGIC;
signal N129 : STD_LOGIC;
signal N13 : STD_LOGIC;
signal N130 : STD_LOGIC;
signal N131 : STD_LOGIC;
signal N132 : STD_LOGIC;
signal N133 : STD_LOGIC;
signal N134 : STD_LOGIC;
signal N135 : STD_LOGIC;
signal N32 : STD_LOGIC;
signal N33 : STD_LOGIC;
signal N38 : STD_LOGIC;
signal N39 : STD_LOGIC;
signal N41 : STD_LOGIC;
signal N42 : STD_LOGIC;
signal N44 : STD_LOGIC;
signal N45 : STD_LOGIC;
signal N47 : STD_LOGIC;
signal N49 : STD_LOGIC;
signal N50 : STD_LOGIC;
signal N56 : STD_LOGIC;
signal N57 : STD_LOGIC;
signal N58 : STD_LOGIC;
signal N59 : STD_LOGIC;
signal N64 : STD_LOGIC;
signal N65 : STD_LOGIC;
signal N67 : STD_LOGIC;
signal N69 : STD_LOGIC;
signal N70 : STD_LOGIC;
signal N72 : STD_LOGIC;
signal N73 : STD_LOGIC;
signal N75 : STD_LOGIC;
signal N76 : STD_LOGIC;
signal N78 : STD_LOGIC;
signal N79 : STD_LOGIC;
signal N81 : STD_LOGIC;
signal N82 : STD_LOGIC;
signal N84 : STD_LOGIC;
signal N85 : STD_LOGIC;
signal N87 : STD_LOGIC;
signal N88 : STD_LOGIC;
signal N9 : STD_LOGIC;
signal N90 : STD_LOGIC;
signal N91 : STD_LOGIC;
signal N93 : STD_LOGIC;
signal N95 : STD_LOGIC;
signal N96 : STD_LOGIC;
signal N98 : STD_LOGIC;
signal N99 : STD_LOGIC;
signal adder_16bit_N11 : STD_LOGIC;
signal adder_16bit_N3 : STD_LOGIC;
signal adder_16bit_N4 : STD_LOGIC;
signal adder_16bit_N5 : STD_LOGIC;
signal adder_16bit_bit11_cout_and0001 : STD_LOGIC;
signal adder_16bit_bit6_cout_and0001 : STD_LOGIC;
signal clk_BUFGP_231 : STD_LOGIC;
signal cpu_alu_DECODER_N11 : STD_LOGIC;
signal cpu_alu_N0 : STD_LOGIC;
signal cpu_alu_N18 : STD_LOGIC;
signal cpu_alu_STAT_data_out_0_Q : STD_LOGIC;
signal cpu_alu_STAT_data_out_1_Q : STD_LOGIC;
signal cpu_alu_STAT_data_out_3_Q : STD_LOGIC;
signal cpu_alu_i_A_EN : STD_LOGIC;
signal cpu_alu_i_A_in_1_97 : STD_LOGIC;
signal cpu_alu_i_A_in_3_1 : STD_LOGIC;
signal cpu_alu_i_MSB_cin : STD_LOGIC;
signal cpu_alu_i_STAT_EN : STD_LOGIC;
signal cpu_alu_i_XORb_in_256 : STD_LOGIC;
signal cpu_alu_i_arith_S : STD_LOGIC;
signal cpu_alu_i_carry_in_258 : STD_LOGIC;
signal cpu_alu_i_stat_S : STD_LOGIC;
signal cycle_control_unit_Mcount_cycle_counter : STD_LOGIC;
signal cycle_control_unit_Mcount_cycle_counter1 : STD_LOGIC;
signal cycle_control_unit_Mcount_cycle_counter2 : STD_LOGIC;
signal cycle_control_unit_Mcount_cycle_counter_val : STD_LOGIC;
signal cycle_control_unit_cycle_counter_or0000 : STD_LOGIC;
signal cycle_control_unit_exe_268 : STD_LOGIC;
signal cycle_control_unit_exe_mux0000 : STD_LOGIC;
signal cycle_control_unit_mem_en_270 : STD_LOGIC;
signal cycle_control_unit_mem_en_mux0000 : STD_LOGIC;
signal cycle_control_unit_op_en_272 : STD_LOGIC;
signal cycle_control_unit_op_en_mux0000 : STD_LOGIC;
signal cycle_control_unit_pc_en_274 : STD_LOGIC;
signal cycle_control_unit_pc_en_mux0000 : STD_LOGIC;
signal cycle_control_unit_received_hlt_276 : STD_LOGIC;
signal cycle_control_unit_received_hlt_0_not0000 : STD_LOGIC;
signal i_hlt : STD_LOGIC;
signal i_jmp : STD_LOGIC;
signal i_pc_en_after_or : STD_LOGIC;
signal i_pc_prime_10_19_287 : STD_LOGIC;
signal i_pc_prime_10_69 : STD_LOGIC;
signal i_pc_prime_10_691_289 : STD_LOGIC;
signal i_pc_prime_10_8_290 : STD_LOGIC;
signal i_pc_prime_14_9_295 : STD_LOGIC;
signal i_pc_prime_4_17_301 : STD_LOGIC;
signal i_pc_prime_5_30_303 : STD_LOGIC;
signal i_pc_prime_5_4_304 : STD_LOGIC;
signal i_pc_prime_7_1_307 : STD_LOGIC;
signal i_pc_prime_7_2_308 : STD_LOGIC;
signal i_pc_prime_8_1_310 : STD_LOGIC;
signal i_pc_prime_9_35 : STD_LOGIC;
signal i_pc_prime_9_9_313 : STD_LOGIC;
signal i_received_hlt_314 : STD_LOGIC;
signal ram_address_0_OBUF_331 : STD_LOGIC;
signal ram_address_10_OBUF_332 : STD_LOGIC;
signal ram_address_11_OBUF_333 : STD_LOGIC;
signal ram_address_12_OBUF_334 : STD_LOGIC;
signal ram_address_13_OBUF_335 : STD_LOGIC;
signal ram_address_14_OBUF_336 : STD_LOGIC;
signal ram_address_15_OBUF_337 : STD_LOGIC;
signal ram_address_1_OBUF_338 : STD_LOGIC;
signal ram_address_2_OBUF_339 : STD_LOGIC;
signal ram_address_3_OBUF_340 : STD_LOGIC;
signal ram_address_4_OBUF_341 : STD_LOGIC;
signal ram_address_5_OBUF_342 : STD_LOGIC;
signal ram_address_6_OBUF_343 : STD_LOGIC;
signal ram_address_7_OBUF_344 : STD_LOGIC;
signal ram_address_8_OBUF_345 : STD_LOGIC;
signal ram_address_9_OBUF_346 : STD_LOGIC;
signal ram_data_i_data_to_ram_not0000_inv : STD_LOGIC;
signal reset_IBUF_354 : STD_LOGIC;
signal reset_IBUF1 : STD_LOGIC;
signal Intern_clock_hundredHzClock_current_count : STD_LOGIC_VECTOR ( 3 downto 0 );
signal Intern_clock_kiloHzClock_Mcount_current_count_cy : STD_LOGIC_VECTOR ( 13 downto 0 );
signal Intern_clock_kiloHzClock_Mcount_current_count_lut : STD_LOGIC_VECTOR ( 14 downto 1 );
signal Intern_clock_kiloHzClock_current_count : STD_LOGIC_VECTOR ( 14 downto 0 );
signal Intern_clock_oneHZClock_current_count : STD_LOGIC_VECTOR ( 3 downto 0 );
signal Intern_clock_tenHzClock_current_count : STD_LOGIC_VECTOR ( 3 downto 0 );
signal MEM_i_nibbleCount : STD_LOGIC_VECTOR ( 1 downto 0 );
signal MEM_q : STD_LOGIC_VECTOR ( 15 downto 0 );
signal PCreg_q : STD_LOGIC_VECTOR ( 15 downto 0 );
signal Result : STD_LOGIC_VECTOR ( 14 downto 0 );
signal cpu_alu_A_data_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal cpu_alu_DECODER_stored_OP_Code : STD_LOGIC_VECTOR ( 3 downto 0 );
signal cpu_alu_i_A_in : STD_LOGIC_VECTOR ( 3 downto 0 );
signal cycle_control_unit_cycle_counter : STD_LOGIC_VECTOR ( 2 downto 0 );
signal i_data_frm_ram : STD_LOGIC_VECTOR ( 3 downto 0 );
signal i_pc_prime : STD_LOGIC_VECTOR ( 15 downto 0 );
begin
XST_GND : GND
port map (
G => N0
);
XST_VCC : VCC
port map (
P => N1
);
i_received_hlt : LDP
port map (
D => N0,
G => reset_IBUF_354,
PRE => i_hlt,
Q => i_received_hlt_314
);
Intern_clock_hundredHzClock_i_zero : FDR
port map (
C => clk_BUFGP_231,
D => N1,
R => Intern_clock_hundredHzClock_i_zero_or0000_9,
Q => Intern_clock_hundredHzClock_i_zero_8
);
Intern_clock_tenHzClock_i_zero : FDR
port map (
C => clk_BUFGP_231,
D => N1,
R => Intern_clock_tenHzClock_i_zero_or0000_96,
Q => Intern_clock_tenHzClock_i_zero_95
);
Intern_clock_oneHZClock_i_zero : FDR
port map (
C => clk_BUFGP_231,
D => N1,
R => Intern_clock_oneHZClock_i_zero_or0000_86,
Q => Intern_clock_oneHZClock_i_zero1
);
Intern_clock_kiloHzClock_i_zero : FDR
port map (
C => clk_BUFGP_231,
D => N1,
R => Intern_clock_kiloHzClock_i_zero_or0000,
Q => Intern_clock_kiloHzClock_i_zero_74
);
Intern_clock_hundredHzClock_current_count_0 : FDSE
port map (
C => clk_BUFGP_231,
CE => Intern_clock_kiloHzClock_i_zero_74,
D => Intern_clock_hundredHzClock_Mcount_current_count,
S => reset_IBUF1,
Q => Intern_clock_hundredHzClock_current_count(0)
);
Intern_clock_hundredHzClock_current_count_1 : FDRE
port map (
C => clk_BUFGP_231,
CE => Intern_clock_kiloHzClock_i_zero_74,
D => Intern_clock_hundredHzClock_Mcount_current_count1,
R => reset_IBUF1,
Q => Intern_clock_hundredHzClock_current_count(1)
);
Intern_clock_hundredHzClock_current_count_2 : FDRE
port map (
C => clk_BUFGP_231,
CE => Intern_clock_kiloHzClock_i_zero_74,
D => Intern_clock_hundredHzClock_Mcount_current_count2,
R => reset_IBUF1,
Q => Intern_clock_hundredHzClock_current_count(2)
);
Intern_clock_hundredHzClock_current_count_3 : FDSE
port map (
C => clk_BUFGP_231,
CE => Intern_clock_kiloHzClock_i_zero_74,
D => Intern_clock_hundredHzClock_Mcount_current_count3,
S => reset_IBUF1,
Q => Intern_clock_hundredHzClock_current_count(3)
);
Intern_clock_tenHzClock_current_count_0 : FDSE
port map (
C => clk_BUFGP_231,
CE => Intern_clock_hundredHzClock_i_zero_8,
D => Intern_clock_tenHzClock_Mcount_current_count,
S => reset_IBUF1,
Q => Intern_clock_tenHzClock_current_count(0)
);
Intern_clock_tenHzClock_current_count_1 : FDRE
port map (
C => clk_BUFGP_231,
CE => Intern_clock_hundredHzClock_i_zero_8,
D => Intern_clock_tenHzClock_Mcount_current_count1,
R => reset_IBUF1,
Q => Intern_clock_tenHzClock_current_count(1)
);
Intern_clock_tenHzClock_current_count_2 : FDRE
port map (
C => clk_BUFGP_231,
CE => Intern_clock_hundredHzClock_i_zero_8,
D => Intern_clock_tenHzClock_Mcount_current_count2,
R => reset_IBUF1,
Q => Intern_clock_tenHzClock_current_count(2)
);
Intern_clock_tenHzClock_current_count_3 : FDSE
port map (
C => clk_BUFGP_231,
CE => Intern_clock_hundredHzClock_i_zero_8,
D => Intern_clock_tenHzClock_Mcount_current_count3,
S => reset_IBUF1,
Q => Intern_clock_tenHzClock_current_count(3)
);
Intern_clock_oneHZClock_current_count_0 : FDSE
port map (
C => clk_BUFGP_231,
CE => Intern_clock_tenHzClock_i_zero_95,
D => Intern_clock_oneHZClock_Mcount_current_count,
S => reset_IBUF1,
Q => Intern_clock_oneHZClock_current_count(0)
);
Intern_clock_oneHZClock_current_count_1 : FDRE
port map (
C => clk_BUFGP_231,
CE => Intern_clock_tenHzClock_i_zero_95,
D => Intern_clock_oneHZClock_Mcount_current_count1,
R => reset_IBUF1,
Q => Intern_clock_oneHZClock_current_count(1)
);
Intern_clock_oneHZClock_current_count_2 : FDRE
port map (
C => clk_BUFGP_231,
CE => Intern_clock_tenHzClock_i_zero_95,
D => Intern_clock_oneHZClock_Mcount_current_count2,
R => reset_IBUF1,
Q => Intern_clock_oneHZClock_current_count(2)
);
Intern_clock_oneHZClock_current_count_3 : FDSE
port map (
C => clk_BUFGP_231,
CE => Intern_clock_tenHzClock_i_zero_95,
D => Intern_clock_oneHZClock_Mcount_current_count3,
S => reset_IBUF1,
Q => Intern_clock_oneHZClock_current_count(3)
);
Intern_clock_kiloHzClock_current_count_0 : FDS
port map (
C => clk_BUFGP_231,
D => Intern_clock_kiloHzClock_Mcount_current_count_eqn_0,
S => reset_IBUF1,
Q => Intern_clock_kiloHzClock_current_count(0)
);
Intern_clock_kiloHzClock_current_count_1 : FDS
port map (
C => clk_BUFGP_231,
D => Intern_clock_kiloHzClock_Mcount_current_count_eqn_1,
S => reset_IBUF1,
Q => Intern_clock_kiloHzClock_current_count(1)
);
Intern_clock_kiloHzClock_current_count_2 : FDR
port map (
C => clk_BUFGP_231,
D => Intern_clock_kiloHzClock_Mcount_current_count_eqn_2,
R => reset_IBUF1,
Q => Intern_clock_kiloHzClock_current_count(2)
);
Intern_clock_kiloHzClock_current_count_3 : FDS
port map (
C => clk_BUFGP_231,
D => Intern_clock_kiloHzClock_Mcount_current_count_eqn_3,
S => reset_IBUF1,
Q => Intern_clock_kiloHzClock_current_count(3)
);
Intern_clock_kiloHzClock_current_count_4 : FDS
port map (
C => clk_BUFGP_231,
D => Intern_clock_kiloHzClock_Mcount_current_count_eqn_4,
S => reset_IBUF1,
Q => Intern_clock_kiloHzClock_current_count(4)
);
Intern_clock_kiloHzClock_current_count_5 : FDS
port map (
C => clk_BUFGP_231,
D => Intern_clock_kiloHzClock_Mcount_current_count_eqn_5,
S => reset_IBUF1,
Q => Intern_clock_kiloHzClock_current_count(5)
);
Intern_clock_kiloHzClock_current_count_6 : FDR
port map (
C => clk_BUFGP_231,
D => Intern_clock_kiloHzClock_Mcount_current_count_eqn_6,
R => reset_IBUF1,
Q => Intern_clock_kiloHzClock_current_count(6)
);
Intern_clock_kiloHzClock_current_count_7 : FDR
port map (
C => clk_BUFGP_231,
D => Intern_clock_kiloHzClock_Mcount_current_count_eqn_7,
R => reset_IBUF1,
Q => Intern_clock_kiloHzClock_current_count(7)
);
Intern_clock_kiloHzClock_current_count_8 : FDS
port map (
C => clk_BUFGP_231,
D => Intern_clock_kiloHzClock_Mcount_current_count_eqn_8,
S => reset_IBUF1,
Q => Intern_clock_kiloHzClock_current_count(8)
);
Intern_clock_kiloHzClock_current_count_9 : FDS
port map (
C => clk_BUFGP_231,
D => Intern_clock_kiloHzClock_Mcount_current_count_eqn_9,
S => reset_IBUF1,
Q => Intern_clock_kiloHzClock_current_count(9)
);
Intern_clock_kiloHzClock_current_count_10 : FDS
port map (
C => clk_BUFGP_231,
D => Intern_clock_kiloHzClock_Mcount_current_count_eqn_10,
S => reset_IBUF1,
Q => Intern_clock_kiloHzClock_current_count(10)
);
Intern_clock_kiloHzClock_current_count_11 : FDS
port map (
C => clk_BUFGP_231,
D => Intern_clock_kiloHzClock_Mcount_current_count_eqn_11,
S => reset_IBUF1,
Q => Intern_clock_kiloHzClock_current_count(11)
);
Intern_clock_kiloHzClock_current_count_12 : FDR
port map (
C => clk_BUFGP_231,
D => Intern_clock_kiloHzClock_Mcount_current_count_eqn_12,
R => reset_IBUF1,
Q => Intern_clock_kiloHzClock_current_count(12)
);
Intern_clock_kiloHzClock_current_count_13 : FDR
port map (
C => clk_BUFGP_231,
D => Intern_clock_kiloHzClock_Mcount_current_count_eqn_13,
R => reset_IBUF1,
Q => Intern_clock_kiloHzClock_current_count(13)
);
Intern_clock_kiloHzClock_current_count_14 : FDR
port map (
C => clk_BUFGP_231,
D => Intern_clock_kiloHzClock_Mcount_current_count_eqn_14,
R => reset_IBUF1,
Q => Intern_clock_kiloHzClock_current_count(14)
);
Intern_clock_kiloHzClock_Mcount_current_count_cy_0_Q : MUXCY
port map (
CI => N1,
DI => N0,
S => Intern_clock_kiloHzClock_Mcount_current_count_cy_0_rt_11,
O => Intern_clock_kiloHzClock_Mcount_current_count_cy(0)
);
Intern_clock_kiloHzClock_Mcount_current_count_xor_0_Q : XORCY
port map (
CI => N1,
LI => Intern_clock_kiloHzClock_Mcount_current_count_cy_0_rt_11,
O => Result(0)
);
Intern_clock_kiloHzClock_Mcount_current_count_cy_1_Q : MUXCY
port map (
CI => Intern_clock_kiloHzClock_Mcount_current_count_cy(0),
DI => N1,
S => Intern_clock_kiloHzClock_Mcount_current_count_lut(1),
O => Intern_clock_kiloHzClock_Mcount_current_count_cy(1)
);
Intern_clock_kiloHzClock_Mcount_current_count_xor_1_Q : XORCY
port map (
CI => Intern_clock_kiloHzClock_Mcount_current_count_cy(0),
LI => Intern_clock_kiloHzClock_Mcount_current_count_lut(1),
O => Result(1)
);
Intern_clock_kiloHzClock_Mcount_current_count_cy_2_Q : MUXCY
port map (
CI => Intern_clock_kiloHzClock_Mcount_current_count_cy(1),
DI => N1,
S => Intern_clock_kiloHzClock_Mcount_current_count_lut(2),
O => Intern_clock_kiloHzClock_Mcount_current_count_cy(2)
);
Intern_clock_kiloHzClock_Mcount_current_count_xor_2_Q : XORCY
port map (
CI => Intern_clock_kiloHzClock_Mcount_current_count_cy(1),
LI => Intern_clock_kiloHzClock_Mcount_current_count_lut(2),
O => Result(2)
);
Intern_clock_kiloHzClock_Mcount_current_count_cy_3_Q : MUXCY
port map (
CI => Intern_clock_kiloHzClock_Mcount_current_count_cy(2),
DI => N1,
S => Intern_clock_kiloHzClock_Mcount_current_count_lut(3),
O => Intern_clock_kiloHzClock_Mcount_current_count_cy(3)
);
Intern_clock_kiloHzClock_Mcount_current_count_xor_3_Q : XORCY
port map (
CI => Intern_clock_kiloHzClock_Mcount_current_count_cy(2),
LI => Intern_clock_kiloHzClock_Mcount_current_count_lut(3),
O => Result(3)
);
Intern_clock_kiloHzClock_Mcount_current_count_cy_4_Q : MUXCY
port map (
CI => Intern_clock_kiloHzClock_Mcount_current_count_cy(3),
DI => N1,
S => Intern_clock_kiloHzClock_Mcount_current_count_lut(4),
O => Intern_clock_kiloHzClock_Mcount_current_count_cy(4)
);
Intern_clock_kiloHzClock_Mcount_current_count_xor_4_Q : XORCY
port map (
CI => Intern_clock_kiloHzClock_Mcount_current_count_cy(3),
LI => Intern_clock_kiloHzClock_Mcount_current_count_lut(4),
O => Result(4)
);
Intern_clock_kiloHzClock_Mcount_current_count_cy_5_Q : MUXCY
port map (
CI => Intern_clock_kiloHzClock_Mcount_current_count_cy(4),
DI => N1,
S => Intern_clock_kiloHzClock_Mcount_current_count_lut(5),
O => Intern_clock_kiloHzClock_Mcount_current_count_cy(5)
);
Intern_clock_kiloHzClock_Mcount_current_count_xor_5_Q : XORCY
port map (
CI => Intern_clock_kiloHzClock_Mcount_current_count_cy(4),
LI => Intern_clock_kiloHzClock_Mcount_current_count_lut(5),
O => Result(5)
);
Intern_clock_kiloHzClock_Mcount_current_count_cy_6_Q : MUXCY
port map (
CI => Intern_clock_kiloHzClock_Mcount_current_count_cy(5),
DI => N1,
S => Intern_clock_kiloHzClock_Mcount_current_count_lut(6),
O => Intern_clock_kiloHzClock_Mcount_current_count_cy(6)
);
Intern_clock_kiloHzClock_Mcount_current_count_xor_6_Q : XORCY
port map (
CI => Intern_clock_kiloHzClock_Mcount_current_count_cy(5),
LI => Intern_clock_kiloHzClock_Mcount_current_count_lut(6),
O => Result(6)
);
Intern_clock_kiloHzClock_Mcount_current_count_cy_7_Q : MUXCY
port map (
CI => Intern_clock_kiloHzClock_Mcount_current_count_cy(6),
DI => N1,
S => Intern_clock_kiloHzClock_Mcount_current_count_lut(7),
O => Intern_clock_kiloHzClock_Mcount_current_count_cy(7)
);
Intern_clock_kiloHzClock_Mcount_current_count_xor_7_Q : XORCY
port map (
CI => Intern_clock_kiloHzClock_Mcount_current_count_cy(6),
LI => Intern_clock_kiloHzClock_Mcount_current_count_lut(7),
O => Result(7)
);
Intern_clock_kiloHzClock_Mcount_current_count_cy_8_Q : MUXCY
port map (
CI => Intern_clock_kiloHzClock_Mcount_current_count_cy(7),
DI => N1,
S => Intern_clock_kiloHzClock_Mcount_current_count_lut(8),
O => Intern_clock_kiloHzClock_Mcount_current_count_cy(8)
);
Intern_clock_kiloHzClock_Mcount_current_count_xor_8_Q : XORCY
port map (
CI => Intern_clock_kiloHzClock_Mcount_current_count_cy(7),
LI => Intern_clock_kiloHzClock_Mcount_current_count_lut(8),
O => Result(8)
);
Intern_clock_kiloHzClock_Mcount_current_count_cy_9_Q : MUXCY
port map (
CI => Intern_clock_kiloHzClock_Mcount_current_count_cy(8),
DI => N1,
S => Intern_clock_kiloHzClock_Mcount_current_count_lut(9),
O => Intern_clock_kiloHzClock_Mcount_current_count_cy(9)
);
Intern_clock_kiloHzClock_Mcount_current_count_xor_9_Q : XORCY
port map (
CI => Intern_clock_kiloHzClock_Mcount_current_count_cy(8),
LI => Intern_clock_kiloHzClock_Mcount_current_count_lut(9),
O => Result(9)
);
Intern_clock_kiloHzClock_Mcount_current_count_cy_10_Q : MUXCY
port map (
CI => Intern_clock_kiloHzClock_Mcount_current_count_cy(9),
DI => N1,
S => Intern_clock_kiloHzClock_Mcount_current_count_lut(10),
O => Intern_clock_kiloHzClock_Mcount_current_count_cy(10)
);
Intern_clock_kiloHzClock_Mcount_current_count_xor_10_Q : XORCY
port map (
CI => Intern_clock_kiloHzClock_Mcount_current_count_cy(9),
LI => Intern_clock_kiloHzClock_Mcount_current_count_lut(10),
O => Result(10)
);
Intern_clock_kiloHzClock_Mcount_current_count_cy_11_Q : MUXCY
port map (
CI => Intern_clock_kiloHzClock_Mcount_current_count_cy(10),
DI => N1,
S => Intern_clock_kiloHzClock_Mcount_current_count_lut(11),
O => Intern_clock_kiloHzClock_Mcount_current_count_cy(11)
);
Intern_clock_kiloHzClock_Mcount_current_count_xor_11_Q : XORCY
port map (
CI => Intern_clock_kiloHzClock_Mcount_current_count_cy(10),
LI => Intern_clock_kiloHzClock_Mcount_current_count_lut(11),
O => Result(11)
);
Intern_clock_kiloHzClock_Mcount_current_count_cy_12_Q : MUXCY
port map (
CI => Intern_clock_kiloHzClock_Mcount_current_count_cy(11),
DI => N1,
S => Intern_clock_kiloHzClock_Mcount_current_count_lut(12),
O => Intern_clock_kiloHzClock_Mcount_current_count_cy(12)
);
Intern_clock_kiloHzClock_Mcount_current_count_xor_12_Q : XORCY
port map (
CI => Intern_clock_kiloHzClock_Mcount_current_count_cy(11),
LI => Intern_clock_kiloHzClock_Mcount_current_count_lut(12),
O => Result(12)
);
Intern_clock_kiloHzClock_Mcount_current_count_cy_13_Q : MUXCY
port map (
CI => Intern_clock_kiloHzClock_Mcount_current_count_cy(12),
DI => N1,
S => Intern_clock_kiloHzClock_Mcount_current_count_lut(13),
O => Intern_clock_kiloHzClock_Mcount_current_count_cy(13)
);
Intern_clock_kiloHzClock_Mcount_current_count_xor_13_Q : XORCY
port map (
CI => Intern_clock_kiloHzClock_Mcount_current_count_cy(12),
LI => Intern_clock_kiloHzClock_Mcount_current_count_lut(13),
O => Result(13)
);
Intern_clock_kiloHzClock_Mcount_current_count_xor_14_Q : XORCY
port map (
CI => Intern_clock_kiloHzClock_Mcount_current_count_cy(13),
LI => Intern_clock_kiloHzClock_Mcount_current_count_lut(14),
O => Result(14)
);
PCreg_q_15 : FDCE
port map (
C => Intern_clock_oneHZClock_i_zero_84,
CE => i_pc_en_after_or,
CLR => reset_IBUF1,
D => i_pc_prime(15),
Q => PCreg_q(15)
);
PCreg_q_14 : FDCE
port map (
C => Intern_clock_oneHZClock_i_zero_84,
CE => i_pc_en_after_or,
CLR => reset_IBUF1,
D => i_pc_prime(14),
Q => PCreg_q(14)
);
PCreg_q_13 : FDCE
port map (
C => Intern_clock_oneHZClock_i_zero_84,
CE => i_pc_en_after_or,
CLR => reset_IBUF1,
D => i_pc_prime(13),
Q => PCreg_q(13)
);
PCreg_q_12 : FDCE
port map (
C => Intern_clock_oneHZClock_i_zero_84,
CE => i_pc_en_after_or,
CLR => reset_IBUF1,
D => i_pc_prime(12),
Q => PCreg_q(12)
);
PCreg_q_11 : FDCE
port map (
C => Intern_clock_oneHZClock_i_zero_84,
CE => i_pc_en_after_or,
CLR => reset_IBUF1,
D => i_pc_prime(11),
Q => PCreg_q(11)
);
PCreg_q_10 : FDCE
port map (
C => Intern_clock_oneHZClock_i_zero_84,
CE => i_pc_en_after_or,
CLR => reset_IBUF1,
D => i_pc_prime(10),
Q => PCreg_q(10)
);
PCreg_q_9 : FDCE
port map (
C => Intern_clock_oneHZClock_i_zero_84,
CE => i_pc_en_after_or,
CLR => reset_IBUF1,
D => i_pc_prime(9),
Q => PCreg_q(9)
);
PCreg_q_8 : FDCE
port map (
C => Intern_clock_oneHZClock_i_zero_84,
CE => i_pc_en_after_or,
CLR => reset_IBUF1,
D => i_pc_prime(8),
Q => PCreg_q(8)
);
PCreg_q_7 : FDCE
port map (
C => Intern_clock_oneHZClock_i_zero_84,
CE => i_pc_en_after_or,
CLR => reset_IBUF1,
D => i_pc_prime(7),
Q => PCreg_q(7)
);
PCreg_q_6 : FDCE
port map (
C => Intern_clock_oneHZClock_i_zero_84,
CE => i_pc_en_after_or,
CLR => reset_IBUF1,
D => i_pc_prime(6),
Q => PCreg_q(6)
);
PCreg_q_5 : FDCE
port map (
C => Intern_clock_oneHZClock_i_zero_84,
CE => i_pc_en_after_or,
CLR => reset_IBUF1,
D => i_pc_prime(5),
Q => PCreg_q(5)
);
PCreg_q_4 : FDPE
port map (
C => Intern_clock_oneHZClock_i_zero_84,
CE => i_pc_en_after_or,
D => i_pc_prime(4),
PRE => reset_IBUF1,
Q => PCreg_q(4)
);
PCreg_q_3 : FDCE
port map (
C => Intern_clock_oneHZClock_i_zero_84,
CE => i_pc_en_after_or,
CLR => reset_IBUF1,
D => i_pc_prime(3),
Q => PCreg_q(3)
);
PCreg_q_2 : FDCE
port map (
C => Intern_clock_oneHZClock_i_zero_84,
CE => i_pc_en_after_or,
CLR => reset_IBUF1,
D => i_pc_prime(2),
Q => PCreg_q(2)
);
PCreg_q_1 : FDPE
port map (
C => Intern_clock_oneHZClock_i_zero_84,
CE => i_pc_en_after_or,
D => i_pc_prime(1),
PRE => reset_IBUF1,
Q => PCreg_q(1)
);
PCreg_q_0 : FDPE
port map (
C => Intern_clock_oneHZClock_i_zero_84,
CE => i_pc_en_after_or,
D => i_pc_prime(0),
PRE => reset_IBUF1,
Q => PCreg_q(0)
);
MEM_i_nibbleCount_1 : FDPE
port map (
C => Intern_clock_oneHZClock_i_zero_84,
CE => cycle_control_unit_mem_en_270,
D => MEM_Mcount_i_nibbleCount1,
PRE => reset_IBUF1,
Q => MEM_i_nibbleCount(1)
);
MEM_i_nibbleCount_0 : FDPE
port map (
C => Intern_clock_oneHZClock_i_zero_84,
CE => cycle_control_unit_mem_en_270,
D => MEM_Mcount_i_nibbleCount,
PRE => reset_IBUF1,
Q => MEM_i_nibbleCount(0)
);
MEM_q_15 : FDCE
port map (
C => Intern_clock_oneHZClock_i_zero_84,
CE => MEM_q_12_not0001,
CLR => reset_IBUF1,
D => i_data_frm_ram(3),
Q => MEM_q(15)
);
MEM_q_14 : FDCE
port map (
C => Intern_clock_oneHZClock_i_zero_84,
CE => MEM_q_12_not0001,
CLR => reset_IBUF1,
D => i_data_frm_ram(2),
Q => MEM_q(14)
);
MEM_q_13 : FDCE
port map (
C => Intern_clock_oneHZClock_i_zero_84,
CE => MEM_q_12_not0001,
CLR => reset_IBUF1,
D => i_data_frm_ram(1),
Q => MEM_q(13)
);
MEM_q_9 : FDCE
port map (
C => Intern_clock_oneHZClock_i_zero_84,
CE => MEM_q_10_not0001,
CLR => reset_IBUF1,
D => i_data_frm_ram(1),
Q => MEM_q(9)
);
MEM_q_12 : FDCE
port map (
C => Intern_clock_oneHZClock_i_zero_84,
CE => MEM_q_12_not0001,
CLR => reset_IBUF1,
D => i_data_frm_ram(0),
Q => MEM_q(12)
);
MEM_q_8 : FDCE
port map (
C => Intern_clock_oneHZClock_i_zero_84,
CE => MEM_q_10_not0001,
CLR => reset_IBUF1,
D => i_data_frm_ram(0),
Q => MEM_q(8)
);
MEM_q_11 : FDCE
port map (
C => Intern_clock_oneHZClock_i_zero_84,
CE => MEM_q_10_not0001,
CLR => reset_IBUF1,
D => i_data_frm_ram(3),
Q => MEM_q(11)
);
MEM_q_7 : FDCE
port map (
C => Intern_clock_oneHZClock_i_zero_84,
CE => MEM_q_4_not0001,
CLR => reset_IBUF1,
D => i_data_frm_ram(3),
Q => MEM_q(7)
);
MEM_q_10 : FDCE
port map (
C => Intern_clock_oneHZClock_i_zero_84,
CE => MEM_q_10_not0001,
CLR => reset_IBUF1,
D => i_data_frm_ram(2),
Q => MEM_q(10)
);
MEM_q_6 : FDCE
port map (
C => Intern_clock_oneHZClock_i_zero_84,
CE => MEM_q_4_not0001,
CLR => reset_IBUF1,
D => i_data_frm_ram(2),
Q => MEM_q(6)
);
MEM_q_5 : FDCE
port map (
C => Intern_clock_oneHZClock_i_zero_84,
CE => MEM_q_4_not0001,
CLR => reset_IBUF1,
D => i_data_frm_ram(1),
Q => MEM_q(5)
);
MEM_q_4 : FDCE
port map (
C => Intern_clock_oneHZClock_i_zero_84,
CE => MEM_q_4_not0001,
CLR => reset_IBUF1,
D => i_data_frm_ram(0),
Q => MEM_q(4)
);
MEM_q_3 : FDCE
port map (
C => Intern_clock_oneHZClock_i_zero_84,
CE => MEM_q_0_not0001,
CLR => reset_IBUF1,
D => i_data_frm_ram(3),
Q => MEM_q(3)
);
MEM_q_1 : FDCE
port map (
C => Intern_clock_oneHZClock_i_zero_84,
CE => MEM_q_0_not0001,
CLR => reset_IBUF1,
D => i_data_frm_ram(1),
Q => MEM_q(1)
);
MEM_q_0 : FDCE
port map (
C => Intern_clock_oneHZClock_i_zero_84,
CE => MEM_q_0_not0001,
CLR => reset_IBUF1,
D => i_data_frm_ram(0),
Q => MEM_q(0)
);
MEM_q_2 : FDCE
port map (
C => Intern_clock_oneHZClock_i_zero_84,
CE => MEM_q_0_not0001,
CLR => reset_IBUF1,
D => i_data_frm_ram(2),
Q => MEM_q(2)
);
cycle_control_unit_cycle_counter_1 : FDC
port map (
C => Intern_clock_oneHZClock_i_zero_84,
CLR => cycle_control_unit_Mcount_cycle_counter_val,
D => cycle_control_unit_Mcount_cycle_counter1,
Q => cycle_control_unit_cycle_counter(1)
);
cycle_control_unit_cycle_counter_0 : FDCP
port map (
C => Intern_clock_oneHZClock_i_zero_84,
CLR => cycle_control_unit_cycle_counter_or0000,
D => cycle_control_unit_Mcount_cycle_counter,
PRE => reset_IBUF1,
Q => cycle_control_unit_cycle_counter(0)
);
cycle_control_unit_cycle_counter_2 : FDC
port map (
C => Intern_clock_oneHZClock_i_zero_84,
CLR => cycle_control_unit_Mcount_cycle_counter_val,
D => cycle_control_unit_Mcount_cycle_counter2,
Q => cycle_control_unit_cycle_counter(2)
);
cycle_control_unit_received_hlt : LDCE
port map (
CLR => reset_IBUF1,
D => N1,
G => i_hlt,
GE => cycle_control_unit_received_hlt_0_not0000,
Q => cycle_control_unit_received_hlt_276
);
cycle_control_unit_op_en : FDCP
port map (
C => Intern_clock_oneHZClock_i_zero_84,
CLR => cycle_control_unit_cycle_counter_or0000,
D => cycle_control_unit_op_en_mux0000,
PRE => reset_IBUF1,
Q => cycle_control_unit_op_en_272
);
cycle_control_unit_exe : FDC
port map (
C => Intern_clock_oneHZClock_i_zero_84,
CLR => cycle_control_unit_Mcount_cycle_counter_val,
D => cycle_control_unit_exe_mux0000,
Q => cycle_control_unit_exe_268
);
cycle_control_unit_mem_en : FDC
port map (
C => Intern_clock_oneHZClock_i_zero_84,
CLR => cycle_control_unit_Mcount_cycle_counter_val,
D => cycle_control_unit_mem_en_mux0000,
Q => cycle_control_unit_mem_en_270
);
cycle_control_unit_pc_en : FDCP
port map (
C => Intern_clock_oneHZClock_i_zero_84,
CLR => cycle_control_unit_cycle_counter_or0000,
D => cycle_control_unit_pc_en_mux0000,
PRE => reset_IBUF1,
Q => cycle_control_unit_pc_en_274
);
cpu_alu_DECODER_stored_OP_Code_0 : FDE
port map (
C => Intern_clock_oneHZClock_i_zero_84,
CE => cycle_control_unit_op_en_272,
D => i_data_frm_ram(0),
Q => cpu_alu_DECODER_stored_OP_Code(0)
);
cpu_alu_DECODER_stored_OP_Code_1 : FDE
port map (
C => Intern_clock_oneHZClock_i_zero_84,
CE => cycle_control_unit_op_en_272,
D => i_data_frm_ram(1),
Q => cpu_alu_DECODER_stored_OP_Code(1)
);
cpu_alu_DECODER_stored_OP_Code_2 : FDE
port map (
C => Intern_clock_oneHZClock_i_zero_84,
CE => cycle_control_unit_op_en_272,
D => i_data_frm_ram(2),
Q => cpu_alu_DECODER_stored_OP_Code(2)
);
cpu_alu_DECODER_stored_OP_Code_3 : FDE
port map (
C => Intern_clock_oneHZClock_i_zero_84,
CE => cycle_control_unit_op_en_272,
D => i_data_frm_ram(3),
Q => cpu_alu_DECODER_stored_OP_Code(3)
);
cpu_alu_STAT_data_out_0 : FDRE
port map (
C => Intern_clock_oneHZClock_i_zero_84,
CE => cpu_alu_i_STAT_EN,
D => cpu_alu_i_carry_in_258,
R => reset_IBUF1,
Q => cpu_alu_STAT_data_out_0_Q
);
cpu_alu_STAT_data_out_1 : FDRE
port map (
C => Intern_clock_oneHZClock_i_zero_84,
CE => cpu_alu_i_STAT_EN,
D => i_hlt,
R => reset_IBUF1,
Q => cpu_alu_STAT_data_out_1_Q
);
cpu_alu_STAT_data_out_3 : FDRE
port map (
C => Intern_clock_oneHZClock_i_zero_84,
CE => cpu_alu_i_STAT_EN,
D => cpu_alu_i_XORb_in_256,
R => reset_IBUF1,
Q => cpu_alu_STAT_data_out_3_Q
);
cycle_control_unit_cycle_counter_or00001 : LUT3
generic map(
INIT => X"32"
)
port map (
I0 => i_hlt,
I1 => reset_IBUF1,
I2 => cycle_control_unit_received_hlt_276,
O => cycle_control_unit_cycle_counter_or0000
);
cycle_control_unit_Mcount_cycle_counter_val1 : LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => reset_IBUF1,
I1 => i_hlt,
I2 => cycle_control_unit_received_hlt_276,
O => cycle_control_unit_Mcount_cycle_counter_val
);
i_ram_address_9_1 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => cycle_control_unit_exe_268,
I1 => MEM_q(9),
I2 => PCreg_q(9),
O => ram_address_9_OBUF_346
);
i_ram_address_8_1 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => cycle_control_unit_exe_268,
I1 => MEM_q(8),
I2 => PCreg_q(8),
O => ram_address_8_OBUF_345
);
i_ram_address_7_1 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => cycle_control_unit_exe_268,
I1 => MEM_q(7),
I2 => PCreg_q(7),
O => ram_address_7_OBUF_344
);
i_ram_address_6_1 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => cycle_control_unit_exe_268,
I1 => MEM_q(6),
I2 => PCreg_q(6),
O => ram_address_6_OBUF_343
);
i_ram_address_5_1 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => cycle_control_unit_exe_268,
I1 => MEM_q(5),
I2 => PCreg_q(5),
O => ram_address_5_OBUF_342
);
i_ram_address_4_1 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => cycle_control_unit_exe_268,
I1 => MEM_q(4),
I2 => PCreg_q(4),
O => ram_address_4_OBUF_341
);
i_ram_address_3_1 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => cycle_control_unit_exe_268,
I1 => MEM_q(3),
I2 => PCreg_q(3),
O => ram_address_3_OBUF_340
);
i_ram_address_2_1 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => cycle_control_unit_exe_268,
I1 => MEM_q(2),
I2 => PCreg_q(2),
O => ram_address_2_OBUF_339
);
i_ram_address_1_1 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => cycle_control_unit_exe_268,
I1 => MEM_q(1),
I2 => PCreg_q(1),
O => ram_address_1_OBUF_338
);
i_ram_address_15_1 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => cycle_control_unit_exe_268,
I1 => MEM_q(15),
I2 => PCreg_q(15),
O => ram_address_15_OBUF_337
);
i_ram_address_14_1 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => cycle_control_unit_exe_268,
I1 => MEM_q(14),
I2 => PCreg_q(14),
O => ram_address_14_OBUF_336
);
i_ram_address_13_1 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => cycle_control_unit_exe_268,
I1 => MEM_q(13),
I2 => PCreg_q(13),
O => ram_address_13_OBUF_335
);
i_ram_address_12_1 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => cycle_control_unit_exe_268,
I1 => MEM_q(12),
I2 => PCreg_q(12),
O => ram_address_12_OBUF_334
);
i_ram_address_11_1 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => cycle_control_unit_exe_268,
I1 => MEM_q(11),
I2 => PCreg_q(11),
O => ram_address_11_OBUF_333
);
i_ram_address_10_1 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => cycle_control_unit_exe_268,
I1 => MEM_q(10),
I2 => PCreg_q(10),
O => ram_address_10_OBUF_332
);
i_ram_address_0_1 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => cycle_control_unit_exe_268,
I1 => MEM_q(0),
I2 => PCreg_q(0),
O => ram_address_0_OBUF_331
);
MEM_Mcount_i_nibbleCount_xor_1_11 : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => MEM_i_nibbleCount(0),
I1 => MEM_i_nibbleCount(1),
O => MEM_Mcount_i_nibbleCount1
);
cycle_control_unit_Mcount_cycle_counter_xor_2_11 : LUT3
generic map(
INIT => X"62"
)
port map (
I0 => cycle_control_unit_cycle_counter(2),
I1 => cycle_control_unit_cycle_counter(0),
I2 => cycle_control_unit_cycle_counter(1),
O => cycle_control_unit_Mcount_cycle_counter2
);
cycle_control_unit_Mcount_cycle_counter_xor_1_11 : LUT3
generic map(
INIT => X"26"
)
port map (
I0 => cycle_control_unit_cycle_counter(1),
I1 => cycle_control_unit_cycle_counter(0),
I2 => cycle_control_unit_cycle_counter(2),
O => cycle_control_unit_Mcount_cycle_counter1
);
cycle_control_unit_pc_en_mux00001 : LUT4
generic map(
INIT => X"BF1F"
)
port map (
I0 => cycle_control_unit_cycle_counter(1),
I1 => cycle_control_unit_cycle_counter(0),
I2 => cycle_control_unit_cycle_counter(2),
I3 => cycle_control_unit_pc_en_274,
O => cycle_control_unit_pc_en_mux0000
);
cycle_control_unit_exe_mux00001 : LUT4
generic map(
INIT => X"A280"
)
port map (
I0 => cycle_control_unit_cycle_counter(2),
I1 => cycle_control_unit_cycle_counter(1),
I2 => cycle_control_unit_exe_268,
I3 => cycle_control_unit_cycle_counter(0),
O => cycle_control_unit_exe_mux0000
);
cycle_control_unit_op_en_mux00001 : LUT4
generic map(
INIT => X"8091"
)
port map (
I0 => cycle_control_unit_cycle_counter(1),
I1 => cycle_control_unit_cycle_counter(2),
I2 => cycle_control_unit_op_en_272,
I3 => cycle_control_unit_cycle_counter(0),
O => cycle_control_unit_op_en_mux0000
);
Intern_clock_tenHzClock_Mcount_current_count_xor_1_11 : LUT4
generic map(
INIT => X"9998"
)
port map (
I0 => Intern_clock_tenHzClock_current_count(0),
I1 => Intern_clock_tenHzClock_current_count(1),
I2 => Intern_clock_tenHzClock_current_count(2),
I3 => Intern_clock_tenHzClock_current_count(3),
O => Intern_clock_tenHzClock_Mcount_current_count1
);
Intern_clock_oneHZClock_Mcount_current_count_xor_1_11 : LUT4
generic map(
INIT => X"9998"
)
port map (
I0 => Intern_clock_oneHZClock_current_count(0),
I1 => Intern_clock_oneHZClock_current_count(1),
I2 => Intern_clock_oneHZClock_current_count(2),
I3 => Intern_clock_oneHZClock_current_count(3),
O => Intern_clock_oneHZClock_Mcount_current_count1
);
Intern_clock_hundredHzClock_Mcount_current_count_xor_1_11 : LUT4
generic map(
INIT => X"9998"
)
port map (
I0 => Intern_clock_hundredHzClock_current_count(0),
I1 => Intern_clock_hundredHzClock_current_count(1),
I2 => Intern_clock_hundredHzClock_current_count(2),
I3 => Intern_clock_hundredHzClock_current_count(3),
O => Intern_clock_hundredHzClock_Mcount_current_count1
);
Intern_clock_tenHzClock_Mcount_current_count_xor_2_11 : LUT4
generic map(
INIT => X"C9C8"
)
port map (
I0 => Intern_clock_tenHzClock_current_count(1),
I1 => Intern_clock_tenHzClock_current_count(2),
I2 => Intern_clock_tenHzClock_current_count(0),
I3 => Intern_clock_tenHzClock_current_count(3),
O => Intern_clock_tenHzClock_Mcount_current_count2
);
Intern_clock_oneHZClock_Mcount_current_count_xor_2_11 : LUT4
generic map(
INIT => X"C9C8"
)
port map (
I0 => Intern_clock_oneHZClock_current_count(1),
I1 => Intern_clock_oneHZClock_current_count(2),
I2 => Intern_clock_oneHZClock_current_count(0),
I3 => Intern_clock_oneHZClock_current_count(3),
O => Intern_clock_oneHZClock_Mcount_current_count2
);
Intern_clock_hundredHzClock_Mcount_current_count_xor_2_11 : LUT4
generic map(
INIT => X"C9C8"
)
port map (
I0 => Intern_clock_hundredHzClock_current_count(1),
I1 => Intern_clock_hundredHzClock_current_count(2),
I2 => Intern_clock_hundredHzClock_current_count(0),
I3 => Intern_clock_hundredHzClock_current_count(3),
O => Intern_clock_hundredHzClock_Mcount_current_count2
);
cycle_control_unit_mem_en_mux00001 : LUT4
generic map(
INIT => X"BE36"
)
port map (
I0 => cycle_control_unit_cycle_counter(1),
I1 => cycle_control_unit_cycle_counter(2),
I2 => cycle_control_unit_cycle_counter(0),
I3 => cycle_control_unit_mem_en_270,
O => cycle_control_unit_mem_en_mux0000
);
Intern_clock_tenHzClock_Mcount_current_count_xor_3_11 : LUT4
generic map(
INIT => X"AAA9"
)
port map (
I0 => Intern_clock_tenHzClock_current_count(3),
I1 => Intern_clock_tenHzClock_current_count(1),
I2 => Intern_clock_tenHzClock_current_count(0),
I3 => Intern_clock_tenHzClock_current_count(2),
O => Intern_clock_tenHzClock_Mcount_current_count3
);
Intern_clock_oneHZClock_Mcount_current_count_xor_3_11 : LUT4
generic map(
INIT => X"AAA9"
)
port map (
I0 => Intern_clock_oneHZClock_current_count(3),
I1 => Intern_clock_oneHZClock_current_count(1),
I2 => Intern_clock_oneHZClock_current_count(0),
I3 => Intern_clock_oneHZClock_current_count(2),
O => Intern_clock_oneHZClock_Mcount_current_count3
);
Intern_clock_hundredHzClock_Mcount_current_count_xor_3_11 : LUT4
generic map(
INIT => X"AAA9"
)
port map (
I0 => Intern_clock_hundredHzClock_current_count(3),
I1 => Intern_clock_hundredHzClock_current_count(1),
I2 => Intern_clock_hundredHzClock_current_count(0),
I3 => Intern_clock_hundredHzClock_current_count(2),
O => Intern_clock_hundredHzClock_Mcount_current_count3
);
MEM_q_4_not00011 : LUT3
generic map(
INIT => X"20"
)
port map (
I0 => MEM_i_nibbleCount(0),
I1 => MEM_i_nibbleCount(1),
I2 => cycle_control_unit_mem_en_270,
O => MEM_q_4_not0001
);
MEM_q_12_not00011 : LUT3
generic map(
INIT => X"80"
)
port map (
I0 => MEM_i_nibbleCount(1),
I1 => MEM_i_nibbleCount(0),
I2 => cycle_control_unit_mem_en_270,
O => MEM_q_12_not0001
);
MEM_q_10_not00011 : LUT3
generic map(
INIT => X"20"
)
port map (
I0 => MEM_i_nibbleCount(1),
I1 => MEM_i_nibbleCount(0),
I2 => cycle_control_unit_mem_en_270,
O => MEM_q_10_not0001
);
MEM_q_0_not00011 : LUT3
generic map(
INIT => X"04"
)
port map (
I0 => MEM_i_nibbleCount(1),
I1 => cycle_control_unit_mem_en_270,
I2 => MEM_i_nibbleCount(0),
O => MEM_q_0_not0001
);
Intern_clock_tenHzClock_i_zero_or0000_SW0 : LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => Intern_clock_tenHzClock_current_count(3),
I1 => Intern_clock_tenHzClock_current_count(2),
I2 => reset_IBUF1,
O => N9
);
Intern_clock_tenHzClock_i_zero_or0000 : LUT4
generic map(
INIT => X"FFFB"
)
port map (
I0 => Intern_clock_tenHzClock_current_count(0),
I1 => Intern_clock_hundredHzClock_i_zero_8,
I2 => Intern_clock_tenHzClock_current_count(1),
I3 => N9,
O => Intern_clock_tenHzClock_i_zero_or0000_96
);
Intern_clock_oneHZClock_i_zero_or0000_SW0 : LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => Intern_clock_oneHZClock_current_count(3),
I1 => Intern_clock_oneHZClock_current_count(2),
I2 => reset_IBUF1,
O => N11
);
Intern_clock_oneHZClock_i_zero_or0000 : LUT4
generic map(
INIT => X"FFFB"
)
port map (
I0 => Intern_clock_oneHZClock_current_count(1),
I1 => Intern_clock_tenHzClock_i_zero_95,
I2 => Intern_clock_oneHZClock_current_count(0),
I3 => N11,
O => Intern_clock_oneHZClock_i_zero_or0000_86
);
Intern_clock_hundredHzClock_i_zero_or0000_SW0 : LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => Intern_clock_hundredHzClock_current_count(3),
I1 => Intern_clock_hundredHzClock_current_count(2),
I2 => reset_IBUF1,
O => N13
);
Intern_clock_hundredHzClock_i_zero_or0000 : LUT4
generic map(
INIT => X"FFFB"
)
port map (
I0 => Intern_clock_hundredHzClock_current_count(1),
I1 => Intern_clock_kiloHzClock_i_zero_74,
I2 => Intern_clock_hundredHzClock_current_count(0),
I3 => N13,
O => Intern_clock_hundredHzClock_i_zero_or0000_9
);
cpu_alu_DECODER_STAT_EN_and00001 : LUT3
generic map(
INIT => X"20"
)
port map (
I0 => cpu_alu_i_A_EN,
I1 => cpu_alu_DECODER_stored_OP_Code(2),
I2 => cpu_alu_DECODER_stored_OP_Code(1),
O => cpu_alu_i_STAT_EN
);
Intern_clock_kiloHzClock_Mcount_current_count_eqn_15 : LUT2
generic map(
INIT => X"E"
)
port map (
I0 => Result(1),
I1 => Intern_clock_kiloHzClock_current_count_cmp_eq0000,
O => Intern_clock_kiloHzClock_Mcount_current_count_eqn_1
);
Intern_clock_kiloHzClock_Mcount_current_count_eqn_01 : LUT2
generic map(
INIT => X"E"
)
port map (
I0 => Result(0),
I1 => Intern_clock_kiloHzClock_current_count_cmp_eq0000,
O => Intern_clock_kiloHzClock_Mcount_current_count_eqn_0
);
cpu_alu_DECODER_HLT_and00002 : LUT3
generic map(
INIT => X"04"
)
port map (
I0 => cpu_alu_DECODER_stored_OP_Code(2),
I1 => N128,
I2 => cpu_alu_DECODER_stored_OP_Code(1),
O => i_hlt
);
i_pc_en_after_or1 : LUT2
generic map(
INIT => X"E"
)
port map (
I0 => cycle_control_unit_pc_en_274,
I1 => i_jmp,
O => i_pc_en_after_or
);
Intern_clock_kiloHzClock_Mcount_current_count_eqn_21 : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => Result(2),
I1 => Intern_clock_kiloHzClock_current_count_cmp_eq0000,
O => Intern_clock_kiloHzClock_Mcount_current_count_eqn_2
);
Intern_clock_kiloHzClock_Mcount_current_count_eqn_31 : LUT2
generic map(
INIT => X"E"
)
port map (
I0 => Result(3),
I1 => Intern_clock_kiloHzClock_current_count_cmp_eq0000,
O => Intern_clock_kiloHzClock_Mcount_current_count_eqn_3
);
Intern_clock_kiloHzClock_Mcount_current_count_eqn_41 : LUT2
generic map(
INIT => X"E"
)
port map (
I0 => Result(4),
I1 => Intern_clock_kiloHzClock_current_count_cmp_eq0000,
O => Intern_clock_kiloHzClock_Mcount_current_count_eqn_4
);
Intern_clock_kiloHzClock_Mcount_current_count_eqn_51 : LUT2
generic map(
INIT => X"E"
)
port map (
I0 => Result(5),
I1 => Intern_clock_kiloHzClock_current_count_cmp_eq0000,
O => Intern_clock_kiloHzClock_Mcount_current_count_eqn_5
);
Intern_clock_kiloHzClock_i_zero_or00001 : LUT2
generic map(
INIT => X"D"
)
port map (
I0 => Intern_clock_kiloHzClock_current_count_cmp_eq0000,
I1 => reset_IBUF1,
O => Intern_clock_kiloHzClock_i_zero_or0000
);
Intern_clock_kiloHzClock_current_count_cmp_eq000012 : LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => Intern_clock_kiloHzClock_current_count(1),
I1 => Intern_clock_kiloHzClock_current_count(14),
I2 => Intern_clock_kiloHzClock_current_count(2),
I3 => Intern_clock_kiloHzClock_current_count(3),
O => Intern_clock_kiloHzClock_current_count_cmp_eq000012_70
);
Intern_clock_kiloHzClock_current_count_cmp_eq000025 : LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => Intern_clock_kiloHzClock_current_count(4),
I1 => Intern_clock_kiloHzClock_current_count(5),
I2 => Intern_clock_kiloHzClock_current_count(6),
I3 => Intern_clock_kiloHzClock_current_count(7),
O => Intern_clock_kiloHzClock_current_count_cmp_eq000025_71
);
Intern_clock_kiloHzClock_current_count_cmp_eq000049 : LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => Intern_clock_kiloHzClock_current_count(8),
I1 => Intern_clock_kiloHzClock_current_count(9),
I2 => Intern_clock_kiloHzClock_current_count(10),
I3 => Intern_clock_kiloHzClock_current_count(11),
O => Intern_clock_kiloHzClock_current_count_cmp_eq000049_72
);
Intern_clock_kiloHzClock_current_count_cmp_eq000058 : LUT3
generic map(
INIT => X"01"
)
port map (
I0 => Intern_clock_kiloHzClock_current_count(12),
I1 => Intern_clock_kiloHzClock_current_count(13),
I2 => Intern_clock_kiloHzClock_current_count(0),
O => Intern_clock_kiloHzClock_current_count_cmp_eq000058_73
);
Intern_clock_kiloHzClock_current_count_cmp_eq000071 : LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => Intern_clock_kiloHzClock_current_count_cmp_eq000012_70,
I1 => Intern_clock_kiloHzClock_current_count_cmp_eq000025_71,
I2 => Intern_clock_kiloHzClock_current_count_cmp_eq000049_72,
I3 => Intern_clock_kiloHzClock_current_count_cmp_eq000058_73,
O => Intern_clock_kiloHzClock_current_count_cmp_eq0000
);
Intern_clock_kiloHzClock_Mcount_current_count_eqn_61 : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => Result(6),
I1 => Intern_clock_kiloHzClock_current_count_cmp_eq0000,
O => Intern_clock_kiloHzClock_Mcount_current_count_eqn_6
);
Intern_clock_kiloHzClock_Mcount_current_count_eqn_71 : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => Result(7),
I1 => Intern_clock_kiloHzClock_current_count_cmp_eq0000,
O => Intern_clock_kiloHzClock_Mcount_current_count_eqn_7
);
Intern_clock_kiloHzClock_Mcount_current_count_eqn_81 : LUT2
generic map(
INIT => X"E"
)
port map (
I0 => Result(8),
I1 => Intern_clock_kiloHzClock_current_count_cmp_eq0000,
O => Intern_clock_kiloHzClock_Mcount_current_count_eqn_8
);
Intern_clock_kiloHzClock_Mcount_current_count_eqn_91 : LUT2
generic map(
INIT => X"E"
)
port map (
I0 => Result(9),
I1 => Intern_clock_kiloHzClock_current_count_cmp_eq0000,
O => Intern_clock_kiloHzClock_Mcount_current_count_eqn_9
);
Intern_clock_kiloHzClock_Mcount_current_count_eqn_101 : LUT2
generic map(
INIT => X"E"
)
port map (
I0 => Result(10),
I1 => Intern_clock_kiloHzClock_current_count_cmp_eq0000,
O => Intern_clock_kiloHzClock_Mcount_current_count_eqn_10
);
cpu_alu_DECODER_Stat_S_and00001 : LUT3
generic map(
INIT => X"80"
)
port map (
I0 => cpu_alu_DECODER_stored_OP_Code(1),
I1 => cpu_alu_DECODER_stored_OP_Code(2),
I2 => cpu_alu_i_A_EN,
O => cpu_alu_i_stat_S
);
i_pc_prime_6_1 : LUT4
generic map(
INIT => X"BE14"
)
port map (
I0 => i_jmp,
I1 => adder_16bit_bit6_cout_and0001,
I2 => PCreg_q(6),
I3 => MEM_q(6),
O => i_pc_prime(6)
);
Intern_clock_kiloHzClock_Mcount_current_count_eqn_111 : LUT2
generic map(
INIT => X"E"
)
port map (
I0 => Result(11),
I1 => Intern_clock_kiloHzClock_current_count_cmp_eq0000,
O => Intern_clock_kiloHzClock_Mcount_current_count_eqn_11
);
Intern_clock_kiloHzClock_Mcount_current_count_eqn_121 : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => Result(12),
I1 => Intern_clock_kiloHzClock_current_count_cmp_eq0000,
O => Intern_clock_kiloHzClock_Mcount_current_count_eqn_12
);
Intern_clock_kiloHzClock_Mcount_current_count_eqn_131 : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => Result(13),
I1 => Intern_clock_kiloHzClock_current_count_cmp_eq0000,
O => Intern_clock_kiloHzClock_Mcount_current_count_eqn_13
);
Intern_clock_kiloHzClock_Mcount_current_count_eqn_141 : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => Result(14),
I1 => Intern_clock_kiloHzClock_current_count_cmp_eq0000,
O => Intern_clock_kiloHzClock_Mcount_current_count_eqn_14
);
i_data_frm_ram_3_LogicTrst1 : LUT2
generic map(
INIT => X"D"
)
port map (
I0 => ram_data_i_data_to_ram_not0000_inv,
I1 => N56,
O => i_data_frm_ram(3)
);
cpu_alu_DECODER_Arith_S_and000011 : LUT3
generic map(
INIT => X"20"
)
port map (
I0 => cycle_control_unit_exe_268,
I1 => cpu_alu_DECODER_stored_OP_Code(3),
I2 => cpu_alu_DECODER_stored_OP_Code(0),
O => cpu_alu_i_A_EN
);
cpu_alu_DECODER_Arith_S_and00001 : LUT3
generic map(
INIT => X"20"
)
port map (
I0 => cpu_alu_DECODER_stored_OP_Code(2),
I1 => cpu_alu_DECODER_stored_OP_Code(1),
I2 => cpu_alu_i_A_EN,
O => cpu_alu_i_arith_S
);
i_pc_prime_11_1 : LUT4
generic map(
INIT => X"A3AC"
)
port map (
I0 => MEM_q(11),
I1 => PCreg_q(11),
I2 => i_jmp,
I3 => adder_16bit_bit11_cout_and0001,
O => i_pc_prime(11)
);
i_pc_prime_9_9 : LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => PCreg_q(6),
I1 => PCreg_q(7),
I2 => PCreg_q(8),
I3 => PCreg_q(9),
O => i_pc_prime_9_9_313
);
i_pc_prime_10_8 : LUT2
generic map(
INIT => X"7"
)
port map (
I0 => PCreg_q(8),
I1 => PCreg_q(9),
O => i_pc_prime_10_8_290
);
i_pc_prime_10_19 : LUT4
generic map(
INIT => X"DFFF"
)
port map (
I0 => PCreg_q(6),
I1 => i_pc_prime_10_8_290,
I2 => PCreg_q(7),
I3 => N130,
O => i_pc_prime_10_19_287
);
i_data_frm_ram_2_LogicTrst1 : LUT2
generic map(
INIT => X"D"
)
port map (
I0 => ram_data_i_data_to_ram_not0000_inv,
I1 => N57,
O => i_data_frm_ram(2)
);
i_pc_prime_12_SW0 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => i_jmp,
I1 => MEM_q(12),
I2 => PCreg_q(12),
O => N32
);
i_pc_prime_12_Q : LUT4
generic map(
INIT => X"D8F0"
)
port map (
I0 => PCreg_q(11),
I1 => N33,
I2 => N32,
I3 => adder_16bit_bit11_cout_and0001,
O => i_pc_prime(12)
);
i_pc_prime_13_SW0 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => i_jmp,
I1 => MEM_q(13),
I2 => PCreg_q(13),
O => N38
);
i_pc_prime_13_Q : LUT4
generic map(
INIT => X"D8F0"
)
port map (
I0 => PCreg_q(12),
I1 => N39,
I2 => N38,
I3 => adder_16bit_bit11_cout_and0001,
O => i_pc_prime(13)
);
i_data_frm_ram_1_LogicTrst1 : LUT2
generic map(
INIT => X"D"
)
port map (
I0 => ram_data_i_data_to_ram_not0000_inv,
I1 => N58,
O => i_data_frm_ram(1)
);
i_pc_prime_14_9 : LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => PCreg_q(11),
I1 => PCreg_q(12),
I2 => PCreg_q(13),
I3 => PCreg_q(14),
O => i_pc_prime_14_9_295
);
i_pc_prime_15_SW0 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => i_jmp,
I1 => MEM_q(15),
I2 => PCreg_q(15),
O => N41
);
i_pc_prime_15_SW1 : LUT3
generic map(
INIT => X"B1"
)
port map (
I0 => i_jmp,
I1 => PCreg_q(15),
I2 => MEM_q(15),
O => N42
);
i_pc_prime_15_Q : LUT4
generic map(
INIT => X"CCE4"
)
port map (
I0 => PCreg_q(14),
I1 => N41,
I2 => N42,
I3 => N132,
O => i_pc_prime(15)
);
i_pc_prime_0_SW1 : LUT4
generic map(
INIT => X"EB41"
)
port map (
I0 => i_jmp,
I1 => PCreg_q(14),
I2 => PCreg_q(0),
I3 => MEM_q(0),
O => N45
);
i_pc_prime_0_Q : LUT4
generic map(
INIT => X"CCE4"
)
port map (
I0 => PCreg_q(15),
I1 => N44,
I2 => N45,
I3 => adder_16bit_N5,
O => i_pc_prime(0)
);
i_data_frm_ram_0_LogicTrst1 : LUT2
generic map(
INIT => X"D"
)
port map (
I0 => ram_data_i_data_to_ram_not0000_inv,
I1 => N59,
O => i_data_frm_ram(0)
);
cpu_alu_DECODER_WE : LUT4
generic map(
INIT => X"FFFB"
)
port map (
I0 => cpu_alu_DECODER_stored_OP_Code(0),
I1 => cycle_control_unit_exe_268,
I2 => cpu_alu_DECODER_stored_OP_Code(2),
I3 => N47,
O => ram_data_i_data_to_ram_not0000_inv
);
i_pc_prime_1_SW1 : LUT4
generic map(
INIT => X"F3E2"
)
port map (
I0 => adder_16bit_N11,
I1 => i_jmp,
I2 => MEM_q(1),
I3 => PCreg_q(1),
O => N50
);
adder_16bit_bit6_Mxor_s_xo_0_31 : LUT3
generic map(
INIT => X"80"
)
port map (
I0 => PCreg_q(1),
I1 => N131,
I2 => PCreg_q(2),
O => adder_16bit_N4
);
adder_16bit_bit11_cout_and00011 : LUT3
generic map(
INIT => X"20"
)
port map (
I0 => PCreg_q(9),
I1 => N133,
I2 => PCreg_q(10),
O => adder_16bit_bit11_cout_and0001
);
i_pc_prime_5_4 : LUT2
generic map(
INIT => X"7"
)
port map (
I0 => PCreg_q(3),
I1 => PCreg_q(4),
O => i_pc_prime_5_4_304
);
i_pc_prime_5_30 : LUT4
generic map(
INIT => X"4000"
)
port map (
I0 => PCreg_q(5),
I1 => PCreg_q(4),
I2 => PCreg_q(3),
I3 => adder_16bit_N4,
O => i_pc_prime_5_30_303
);
reset_IBUF : IBUF
port map (
I => reset,
O => reset_IBUF1
);
clk_out_OBUF : OBUF
port map (
I => i_received_hlt_314,
O => clk_out
);
ram_write_enable_OBUF : OBUF
port map (
I => ram_data_i_data_to_ram_not0000_inv,
O => ram_write_enable
);
a_data_3_OBUF : OBUF
port map (
I => cpu_alu_A_data_out(3),
O => a_data(3)
);
a_data_2_OBUF : OBUF
port map (
I => cpu_alu_A_data_out(2),
O => a_data(2)
);
a_data_1_OBUF : OBUF
port map (
I => cpu_alu_A_data_out(1),
O => a_data(1)
);
a_data_0_OBUF : OBUF
port map (
I => cpu_alu_A_data_out(0),
O => a_data(0)
);
ram_address_15_OBUF : OBUF
port map (
I => ram_address_15_OBUF_337,
O => ram_address(15)
);
ram_address_14_OBUF : OBUF
port map (
I => ram_address_14_OBUF_336,
O => ram_address(14)
);
ram_address_13_OBUF : OBUF
port map (
I => ram_address_13_OBUF_335,
O => ram_address(13)
);
ram_address_12_OBUF : OBUF
port map (
I => ram_address_12_OBUF_334,
O => ram_address(12)
);
ram_address_11_OBUF : OBUF
port map (
I => ram_address_11_OBUF_333,
O => ram_address(11)
);
ram_address_10_OBUF : OBUF
port map (
I => ram_address_10_OBUF_332,
O => ram_address(10)
);
ram_address_9_OBUF : OBUF
port map (
I => ram_address_9_OBUF_346,
O => ram_address(9)
);
ram_address_8_OBUF : OBUF
port map (
I => ram_address_8_OBUF_345,
O => ram_address(8)
);
ram_address_7_OBUF : OBUF
port map (
I => ram_address_7_OBUF_344,
O => ram_address(7)
);
ram_address_6_OBUF : OBUF
port map (
I => ram_address_6_OBUF_343,
O => ram_address(6)
);
ram_address_5_OBUF : OBUF
port map (
I => ram_address_5_OBUF_342,
O => ram_address(5)
);
ram_address_4_OBUF : OBUF
port map (
I => ram_address_4_OBUF_341,
O => ram_address(4)
);
ram_address_3_OBUF : OBUF
port map (
I => ram_address_3_OBUF_340,
O => ram_address(3)
);
ram_address_2_OBUF : OBUF
port map (
I => ram_address_2_OBUF_339,
O => ram_address(2)
);
ram_address_1_OBUF : OBUF
port map (
I => ram_address_1_OBUF_338,
O => ram_address(1)
);
ram_address_0_OBUF : OBUF
port map (
I => ram_address_0_OBUF_331,
O => ram_address(0)
);
Intern_clock_kiloHzClock_Mcount_current_count_cy_0_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => Intern_clock_kiloHzClock_current_count(0),
O => Intern_clock_kiloHzClock_Mcount_current_count_cy_0_rt_11
);
i_pc_prime_3_SW0_SW0 : LUT4
generic map(
INIT => X"F3E2"
)
port map (
I0 => adder_16bit_N4,
I1 => i_jmp,
I2 => MEM_q(3),
I3 => PCreg_q(3),
O => N64
);
i_pc_prime_3_SW0_SW1 : LUT4
generic map(
INIT => X"AE04"
)
port map (
I0 => i_jmp,
I1 => adder_16bit_N4,
I2 => PCreg_q(3),
I3 => MEM_q(3),
O => N65
);
adder_16bit_bit1_Mxor_s_xo_0_11_SW0 : LUT2
generic map(
INIT => X"8"
)
port map (
I0 => PCreg_q(15),
I1 => PCreg_q(14),
O => N67
);
i_pc_prime_5_18_SW1 : LUT4
generic map(
INIT => X"AFAC"
)
port map (
I0 => MEM_q(5),
I1 => PCreg_q(5),
I2 => i_jmp,
I3 => i_pc_prime_5_30_303,
O => N70
);
i_pc_prime_4_11_SW0 : LUT4
generic map(
INIT => X"AFAC"
)
port map (
I0 => MEM_q(4),
I1 => PCreg_q(4),
I2 => i_jmp,
I3 => i_pc_prime_4_17_301,
O => N72
);
cpu_alu_i_A_in_2_11 : LUT4
generic map(
INIT => X"8CEF"
)
port map (
I0 => N58,
I1 => cpu_alu_A_data_out(1),
I2 => ram_data_i_data_to_ram_not0000_inv,
I3 => N134,
O => cpu_alu_N0
);
adder_16bit_bit1_Mxor_s_xo_0_11_SW2 : LUT4
generic map(
INIT => X"ABA8"
)
port map (
I0 => N129,
I1 => PCreg_q(14),
I2 => PCreg_q(0),
I3 => N50,
O => N79
);
i_pc_prime_1_Q : LUT4
generic map(
INIT => X"CCE4"
)
port map (
I0 => PCreg_q(15),
I1 => N78,
I2 => N79,
I3 => adder_16bit_N5,
O => i_pc_prime(1)
);
adder_16bit_bit1_Mxor_s_xo_0_11_SW4 : LUT4
generic map(
INIT => X"ABA8"
)
port map (
I0 => N135,
I1 => PCreg_q(14),
I2 => PCreg_q(0),
I3 => N76,
O => N82
);
i_pc_prime_2_23 : LUT4
generic map(
INIT => X"CCE4"
)
port map (
I0 => PCreg_q(15),
I1 => N81,
I2 => N82,
I3 => adder_16bit_N5,
O => i_pc_prime(2)
);
i_pc_prime_3_Q : LUT4
generic map(
INIT => X"F0D8"
)
port map (
I0 => N67,
I1 => N85,
I2 => N84,
I3 => adder_16bit_N5,
O => i_pc_prime(3)
);
i_pc_prime_5_59 : LUT4
generic map(
INIT => X"F0D8"
)
port map (
I0 => N67,
I1 => N88,
I2 => N87,
I3 => adder_16bit_N5,
O => i_pc_prime(5)
);
i_pc_prime_4_40 : LUT4
generic map(
INIT => X"F0D8"
)
port map (
I0 => N67,
I1 => N91,
I2 => N90,
I3 => adder_16bit_N5,
O => i_pc_prime(4)
);
cpu_alu_JMP_SW0_SW0 : LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => cpu_alu_A_data_out(3),
I1 => cpu_alu_A_data_out(2),
I2 => cpu_alu_A_data_out(1),
I3 => cpu_alu_A_data_out(0),
O => N93
);
cpu_alu_JMP : LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => cpu_alu_DECODER_N11,
I1 => cpu_alu_DECODER_stored_OP_Code(1),
I2 => cpu_alu_DECODER_stored_OP_Code(2),
I3 => N93,
O => i_jmp
);
i_pc_prime_14_35_SW1 : LUT2
generic map(
INIT => X"D"
)
port map (
I0 => i_jmp,
I1 => MEM_q(14),
O => N96
);
i_pc_prime_14_35 : LUT4
generic map(
INIT => X"D8F0"
)
port map (
I0 => PCreg_q(14),
I1 => N96,
I2 => N95,
I3 => adder_16bit_N5,
O => i_pc_prime(14)
);
i_pc_prime_5_18_SW0 : MUXF5
port map (
I0 => N98,
I1 => N99,
S => i_pc_prime_5_30_303,
O => N69
);
i_pc_prime_5_18_SW0_F : LUT4
generic map(
INIT => X"AE04"
)
port map (
I0 => i_jmp,
I1 => PCreg_q(5),
I2 => PCreg_q(2),
I3 => MEM_q(5),
O => N98
);
i_pc_prime_5_18_SW0_G : LUT2
generic map(
INIT => X"D"
)
port map (
I0 => i_jmp,
I1 => MEM_q(5),
O => N99
);
i_pc_prime_2_12_SW0_F : LUT3
generic map(
INIT => X"62"
)
port map (
I0 => PCreg_q(2),
I1 => PCreg_q(1),
I2 => adder_16bit_N11,
O => N102
);
adder_16bit_bit3_Mxor_s_xo_0_11_SW0 : MUXF5
port map (
I0 => N106,
I1 => N107,
S => N65,
O => N84
);
adder_16bit_bit3_Mxor_s_xo_0_11_SW0_F : LUT4
generic map(
INIT => X"2AAA"
)
port map (
I0 => N64,
I1 => PCreg_q(0),
I2 => PCreg_q(2),
I3 => PCreg_q(1),
O => N106
);
adder_16bit_bit3_Mxor_s_xo_0_11_SW0_G : LUT4
generic map(
INIT => X"FF80"
)
port map (
I0 => PCreg_q(0),
I1 => PCreg_q(2),
I2 => PCreg_q(1),
I3 => N64,
O => N107
);
adder_16bit_bit3_Mxor_s_xo_0_11_SW2 : MUXF5
port map (
I0 => N108,
I1 => N109,
S => N69,
O => N87
);
adder_16bit_bit3_Mxor_s_xo_0_11_SW2_F : LUT4
generic map(
INIT => X"F700"
)
port map (
I0 => PCreg_q(0),
I1 => PCreg_q(1),
I2 => i_pc_prime_5_4_304,
I3 => N70,
O => N108
);
adder_16bit_bit3_Mxor_s_xo_0_11_SW2_G : LUT4
generic map(
INIT => X"FF08"
)
port map (
I0 => PCreg_q(0),
I1 => PCreg_q(1),
I2 => i_pc_prime_5_4_304,
I3 => N70,
O => N109
);
adder_16bit_bit3_Mxor_s_xo_0_11_SW4 : MUXF5
port map (
I0 => N110,
I1 => N111,
S => N73,
O => N90
);
adder_16bit_bit3_Mxor_s_xo_0_11_SW4_F : LUT4
generic map(
INIT => X"7F00"
)
port map (
I0 => PCreg_q(2),
I1 => PCreg_q(0),
I2 => PCreg_q(1),
I3 => N72,
O => N110
);
adder_16bit_bit3_Mxor_s_xo_0_11_SW4_G : LUT4
generic map(
INIT => X"FF80"
)
port map (
I0 => PCreg_q(0),
I1 => PCreg_q(2),
I2 => PCreg_q(1),
I3 => N72,
O => N111
);
cpu_alu_i_A_in_0_SW2 : LUT4
generic map(
INIT => X"7363"
)
port map (
I0 => N59,
I1 => cpu_alu_A_data_out(0),
I2 => ram_data_i_data_to_ram_not0000_inv,
I3 => cpu_alu_i_arith_S,
O => N114
);
cpu_alu_i_A_in_0_Q : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => cpu_alu_i_stat_S,
I1 => cpu_alu_STAT_data_out_0_Q,
I2 => N114,
O => cpu_alu_i_A_in(0)
);
cpu_alu_ADDER_cell_3_cout1 : LUT4
generic map(
INIT => X"EF8C"
)
port map (
I0 => N57,
I1 => cpu_alu_A_data_out(2),
I2 => ram_data_i_data_to_ram_not0000_inv,
I3 => cpu_alu_N0,
O => cpu_alu_i_MSB_cin
);
cpu_alu_i_A_in_2_Q : LUT4
generic map(
INIT => X"1333"
)
port map (
I0 => cpu_alu_DECODER_stored_OP_Code(2),
I1 => N120,
I2 => cpu_alu_i_A_EN,
I3 => cpu_alu_DECODER_stored_OP_Code(1),
O => cpu_alu_i_A_in(2)
);
i_pc_prime_2_12_SW11 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => i_jmp,
I1 => MEM_q(2),
I2 => N104,
O => N76
);
i_pc_prime_4_11_SW1 : MUXF5
port map (
I0 => N122,
I1 => N123,
S => adder_16bit_N4,
O => N73
);
i_pc_prime_4_11_SW1_F : LUT4
generic map(
INIT => X"AE04"
)
port map (
I0 => i_jmp,
I1 => PCreg_q(4),
I2 => PCreg_q(3),
I3 => MEM_q(4),
O => N122
);
i_pc_prime_4_11_SW1_G : LUT4
generic map(
INIT => X"BE14"
)
port map (
I0 => i_jmp,
I1 => PCreg_q(4),
I2 => PCreg_q(3),
I3 => MEM_q(4),
O => N123
);
cpu_alu_i_carry_in : MUXF5
port map (
I0 => N124,
I1 => N125,
S => cpu_alu_i_MSB_cin,
O => cpu_alu_i_carry_in_258
);
cpu_alu_i_carry_in_F : LUT4
generic map(
INIT => X"EC20"
)
port map (
I0 => i_data_frm_ram(3),
I1 => i_hlt,
I2 => cpu_alu_A_data_out(3),
I3 => cpu_alu_STAT_data_out_0_Q,
O => N124
);
cpu_alu_i_carry_in_G : LUT4
generic map(
INIT => X"F3E2"
)
port map (
I0 => cpu_alu_A_data_out(3),
I1 => i_hlt,
I2 => cpu_alu_STAT_data_out_0_Q,
I3 => i_data_frm_ram(3),
O => N125
);
cpu_alu_i_XORb_in : MUXF5
port map (
I0 => N126,
I1 => N127,
S => cpu_alu_i_MSB_cin,
O => cpu_alu_i_XORb_in_256
);
cpu_alu_i_XORb_in_F : LUT4
generic map(
INIT => X"F3E2"
)
port map (
I0 => cpu_alu_A_data_out(3),
I1 => i_hlt,
I2 => cpu_alu_STAT_data_out_3_Q,
I3 => i_data_frm_ram(3),
O => N126
);
cpu_alu_i_XORb_in_G : LUT4
generic map(
INIT => X"EC20"
)
port map (
I0 => i_data_frm_ram(3),
I1 => i_hlt,
I2 => cpu_alu_A_data_out(3),
I3 => cpu_alu_STAT_data_out_3_Q,
O => N127
);
Intern_clock_oneHZClock_i_zero_BUFG : BUFG
port map (
I => Intern_clock_oneHZClock_i_zero1,
O => Intern_clock_oneHZClock_i_zero_84
);
clk_BUFGP : BUFGP
port map (
I => clk,
O => clk_BUFGP_231
);
reset_IBUF_BUFG : BUFG
port map (
I => reset_IBUF1,
O => reset_IBUF_354
);
Intern_clock_kiloHzClock_Mcount_current_count_lut_1_INV_0 : INV
port map (
I => Intern_clock_kiloHzClock_current_count(1),
O => Intern_clock_kiloHzClock_Mcount_current_count_lut(1)
);
Intern_clock_kiloHzClock_Mcount_current_count_lut_2_INV_0 : INV
port map (
I => Intern_clock_kiloHzClock_current_count(2),
O => Intern_clock_kiloHzClock_Mcount_current_count_lut(2)
);
Intern_clock_kiloHzClock_Mcount_current_count_lut_3_INV_0 : INV
port map (
I => Intern_clock_kiloHzClock_current_count(3),
O => Intern_clock_kiloHzClock_Mcount_current_count_lut(3)
);
Intern_clock_kiloHzClock_Mcount_current_count_lut_4_INV_0 : INV
port map (
I => Intern_clock_kiloHzClock_current_count(4),
O => Intern_clock_kiloHzClock_Mcount_current_count_lut(4)
);
Intern_clock_kiloHzClock_Mcount_current_count_lut_5_INV_0 : INV
port map (
I => Intern_clock_kiloHzClock_current_count(5),
O => Intern_clock_kiloHzClock_Mcount_current_count_lut(5)
);
Intern_clock_kiloHzClock_Mcount_current_count_lut_6_INV_0 : INV
port map (
I => Intern_clock_kiloHzClock_current_count(6),
O => Intern_clock_kiloHzClock_Mcount_current_count_lut(6)
);
Intern_clock_kiloHzClock_Mcount_current_count_lut_7_INV_0 : INV
port map (
I => Intern_clock_kiloHzClock_current_count(7),
O => Intern_clock_kiloHzClock_Mcount_current_count_lut(7)
);
Intern_clock_kiloHzClock_Mcount_current_count_lut_8_INV_0 : INV
port map (
I => Intern_clock_kiloHzClock_current_count(8),
O => Intern_clock_kiloHzClock_Mcount_current_count_lut(8)
);
Intern_clock_kiloHzClock_Mcount_current_count_lut_9_INV_0 : INV
port map (
I => Intern_clock_kiloHzClock_current_count(9),
O => Intern_clock_kiloHzClock_Mcount_current_count_lut(9)
);
Intern_clock_kiloHzClock_Mcount_current_count_lut_10_INV_0 : INV
port map (
I => Intern_clock_kiloHzClock_current_count(10),
O => Intern_clock_kiloHzClock_Mcount_current_count_lut(10)
);
Intern_clock_kiloHzClock_Mcount_current_count_lut_11_INV_0 : INV
port map (
I => Intern_clock_kiloHzClock_current_count(11),
O => Intern_clock_kiloHzClock_Mcount_current_count_lut(11)
);
Intern_clock_kiloHzClock_Mcount_current_count_lut_12_INV_0 : INV
port map (
I => Intern_clock_kiloHzClock_current_count(12),
O => Intern_clock_kiloHzClock_Mcount_current_count_lut(12)
);
Intern_clock_kiloHzClock_Mcount_current_count_lut_13_INV_0 : INV
port map (
I => Intern_clock_kiloHzClock_current_count(13),
O => Intern_clock_kiloHzClock_Mcount_current_count_lut(13)
);
Intern_clock_kiloHzClock_Mcount_current_count_lut_14_INV_0 : INV
port map (
I => Intern_clock_kiloHzClock_current_count(14),
O => Intern_clock_kiloHzClock_Mcount_current_count_lut(14)
);
cycle_control_unit_Mcount_cycle_counter_xor_0_11_INV_0 : INV
port map (
I => cycle_control_unit_cycle_counter(0),
O => cycle_control_unit_Mcount_cycle_counter
);
MEM_Mcount_i_nibbleCount_xor_0_11_INV_0 : INV
port map (
I => MEM_i_nibbleCount(0),
O => MEM_Mcount_i_nibbleCount
);
Intern_clock_tenHzClock_Mcount_current_count_xor_0_11_INV_0 : INV
port map (
I => Intern_clock_tenHzClock_current_count(0),
O => Intern_clock_tenHzClock_Mcount_current_count
);
Intern_clock_oneHZClock_Mcount_current_count_xor_0_11_INV_0 : INV
port map (
I => Intern_clock_oneHZClock_current_count(0),
O => Intern_clock_oneHZClock_Mcount_current_count
);
Intern_clock_hundredHzClock_Mcount_current_count_xor_0_11_INV_0 : INV
port map (
I => Intern_clock_hundredHzClock_current_count(0),
O => Intern_clock_hundredHzClock_Mcount_current_count
);
cycle_control_unit_received_hlt_0_not00001_INV_0 : INV
port map (
I => cycle_control_unit_received_hlt_276,
O => cycle_control_unit_received_hlt_0_not0000
);
ram_data_3_IOBUF : IOBUF
port map (
I => cpu_alu_A_data_out(3),
T => ram_data_i_data_to_ram_not0000_inv,
O => N56,
IO => ram_data(3)
);
cpu_alu_A_data_out_3 : FDRE
port map (
C => Intern_clock_oneHZClock_i_zero_84,
CE => cpu_alu_i_A_EN,
D => cpu_alu_i_A_in(3),
R => reset_IBUF1,
Q => cpu_alu_A_data_out(3)
);
ram_data_2_IOBUF : IOBUF
port map (
I => cpu_alu_A_data_out(2),
T => ram_data_i_data_to_ram_not0000_inv,
O => N57,
IO => ram_data(2)
);
cpu_alu_A_data_out_2 : FDRE
port map (
C => Intern_clock_oneHZClock_i_zero_84,
CE => cpu_alu_i_A_EN,
D => cpu_alu_i_A_in(2),
R => reset_IBUF1,
Q => cpu_alu_A_data_out(2)
);
ram_data_1_IOBUF : IOBUF
port map (
I => cpu_alu_A_data_out(1),
T => ram_data_i_data_to_ram_not0000_inv,
O => N58,
IO => ram_data(1)
);
cpu_alu_A_data_out_1 : FDRE
port map (
C => Intern_clock_oneHZClock_i_zero_84,
CE => cpu_alu_i_A_EN,
D => cpu_alu_i_A_in(1),
R => reset_IBUF1,
Q => cpu_alu_A_data_out(1)
);
ram_data_0_IOBUF : IOBUF
port map (
I => cpu_alu_A_data_out(0),
T => ram_data_i_data_to_ram_not0000_inv,
O => N59,
IO => ram_data(0)
);
cpu_alu_A_data_out_0 : FDRE
port map (
C => Intern_clock_oneHZClock_i_zero_84,
CE => cpu_alu_i_A_EN,
D => cpu_alu_i_A_in(0),
R => reset_IBUF1,
Q => cpu_alu_A_data_out(0)
);
i_pc_prime_9_351 : LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => adder_16bit_bit6_cout_and0001,
I1 => i_pc_prime_9_9_313,
I2 => adder_16bit_N3,
I3 => PCreg_q(9),
O => i_pc_prime_9_35
);
i_pc_prime_9_35_f5 : MUXF5
port map (
I0 => i_pc_prime_9_35,
I1 => MEM_q(9),
S => i_jmp,
O => i_pc_prime(9)
);
i_pc_prime_10_691 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => i_jmp,
I1 => MEM_q(10),
I2 => i_pc_prime_10_19_287,
O => i_pc_prime_10_69
);
i_pc_prime_10_692 : LUT4
generic map(
INIT => X"AE04"
)
port map (
I0 => i_jmp,
I1 => PCreg_q(9),
I2 => adder_16bit_N3,
I3 => MEM_q(10),
O => i_pc_prime_10_691_289
);
i_pc_prime_10_69_f5 : MUXF5
port map (
I0 => i_pc_prime_10_691_289,
I1 => i_pc_prime_10_69,
S => PCreg_q(10),
O => i_pc_prime(10)
);
cpu_alu_i_A_in_1_971 : LUT4
generic map(
INIT => X"5F69"
)
port map (
I0 => i_data_frm_ram(1),
I1 => cpu_alu_N18,
I2 => cpu_alu_A_data_out(1),
I3 => cpu_alu_i_arith_S,
O => cpu_alu_i_A_in_1_97
);
cpu_alu_i_A_in_1_97_f5 : MUXF5
port map (
I0 => cpu_alu_i_A_in_1_97,
I1 => cpu_alu_STAT_data_out_1_Q,
S => cpu_alu_i_stat_S,
O => cpu_alu_i_A_in(1)
);
i_pc_prime_7_1 : LUT4
generic map(
INIT => X"BF15"
)
port map (
I0 => i_jmp,
I1 => PCreg_q(6),
I2 => adder_16bit_bit6_cout_and0001,
I3 => MEM_q(7),
O => i_pc_prime_7_1_307
);
i_pc_prime_7_2 : LUT4
generic map(
INIT => X"EC20"
)
port map (
I0 => adder_16bit_bit6_cout_and0001,
I1 => i_jmp,
I2 => PCreg_q(6),
I3 => MEM_q(7),
O => i_pc_prime_7_2_308
);
i_pc_prime_7_f5 : MUXF5
port map (
I0 => i_pc_prime_7_2_308,
I1 => i_pc_prime_7_1_307,
S => PCreg_q(7),
O => i_pc_prime(7)
);
i_pc_prime_8_1 : LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => PCreg_q(8),
I1 => PCreg_q(6),
I2 => PCreg_q(7),
I3 => adder_16bit_bit6_cout_and0001,
O => i_pc_prime_8_1_310
);
i_pc_prime_8_f5 : MUXF5
port map (
I0 => i_pc_prime_8_1_310,
I1 => MEM_q(8),
S => i_jmp,
O => i_pc_prime(8)
);
cpu_alu_i_A_in_3_11 : LUT4
generic map(
INIT => X"7796"
)
port map (
I0 => cpu_alu_A_data_out(3),
I1 => i_data_frm_ram(3),
I2 => cpu_alu_i_MSB_cin,
I3 => cpu_alu_i_arith_S,
O => cpu_alu_i_A_in_3_1
);
cpu_alu_i_A_in_3_1_f5 : MUXF5
port map (
I0 => cpu_alu_i_A_in_3_1,
I1 => cpu_alu_STAT_data_out_3_Q,
S => cpu_alu_i_stat_S,
O => cpu_alu_i_A_in(3)
);
cpu_alu_DECODER_HLT_and000011 : LUT3_D
generic map(
INIT => X"04"
)
port map (
I0 => cpu_alu_DECODER_stored_OP_Code(0),
I1 => cycle_control_unit_exe_268,
I2 => cpu_alu_DECODER_stored_OP_Code(3),
LO => N128,
O => cpu_alu_DECODER_N11
);
i_pc_prime_12_SW1 : LUT3_L
generic map(
INIT => X"B1"
)
port map (
I0 => i_jmp,
I1 => PCreg_q(12),
I2 => MEM_q(12),
LO => N33
);
i_pc_prime_13_SW1 : LUT4_L
generic map(
INIT => X"BE14"
)
port map (
I0 => i_jmp,
I1 => PCreg_q(13),
I2 => PCreg_q(11),
I3 => MEM_q(13),
LO => N39
);
i_pc_prime_0_SW0 : LUT3_L
generic map(
INIT => X"B1"
)
port map (
I0 => i_jmp,
I1 => PCreg_q(0),
I2 => MEM_q(0),
LO => N44
);
cpu_alu_DECODER_WE_SW0 : LUT2_L
generic map(
INIT => X"B"
)
port map (
I0 => cpu_alu_DECODER_stored_OP_Code(3),
I1 => cpu_alu_DECODER_stored_OP_Code(1),
LO => N47
);
i_pc_prime_1_SW0 : LUT4_D
generic map(
INIT => X"AE04"
)
port map (
I0 => i_jmp,
I1 => adder_16bit_N11,
I2 => PCreg_q(1),
I3 => MEM_q(1),
LO => N129,
O => N49
);
adder_16bit_bit6_cout_and00011 : LUT4_D
generic map(
INIT => X"8000"
)
port map (
I0 => PCreg_q(5),
I1 => PCreg_q(3),
I2 => PCreg_q(4),
I3 => adder_16bit_N4,
LO => N130,
O => adder_16bit_bit6_cout_and0001
);
adder_16bit_bit6_Mxor_s_xo_0_21 : LUT4_D
generic map(
INIT => X"AEAA"
)
port map (
I0 => PCreg_q(0),
I1 => PCreg_q(15),
I2 => adder_16bit_N5,
I3 => PCreg_q(14),
LO => N131,
O => adder_16bit_N11
);
adder_16bit_bit15_Mxor_s_xo_0_11 : LUT4_D
generic map(
INIT => X"7FFF"
)
port map (
I0 => adder_16bit_bit11_cout_and0001,
I1 => PCreg_q(11),
I2 => PCreg_q(12),
I3 => PCreg_q(13),
LO => N132,
O => adder_16bit_N5
);
adder_16bit_bit11_Mxor_s_xo_0_11 : LUT4_D
generic map(
INIT => X"7FFF"
)
port map (
I0 => adder_16bit_bit6_cout_and0001,
I1 => PCreg_q(6),
I2 => PCreg_q(7),
I3 => PCreg_q(8),
LO => N133,
O => adder_16bit_N3
);
i_pc_prime_4_17 : LUT3_L
generic map(
INIT => X"20"
)
port map (
I0 => PCreg_q(3),
I1 => PCreg_q(4),
I2 => adder_16bit_N4,
LO => i_pc_prime_4_17_301
);
cpu_alu_i_A_in_1_231 : LUT3_D
generic map(
INIT => X"73"
)
port map (
I0 => N59,
I1 => cpu_alu_A_data_out(0),
I2 => ram_data_i_data_to_ram_not0000_inv,
LO => N134,
O => cpu_alu_N18
);
adder_16bit_bit1_Mxor_s_xo_0_11_SW1 : LUT3_L
generic map(
INIT => X"D8"
)
port map (
I0 => PCreg_q(0),
I1 => N49,
I2 => N50,
LO => N78
);
adder_16bit_bit1_Mxor_s_xo_0_11_SW3 : LUT3_L
generic map(
INIT => X"D8"
)
port map (
I0 => PCreg_q(0),
I1 => N75,
I2 => N76,
LO => N81
);
adder_16bit_bit3_Mxor_s_xo_0_11_SW1 : LUT4_L
generic map(
INIT => X"EC4C"
)
port map (
I0 => PCreg_q(2),
I1 => N64,
I2 => PCreg_q(1),
I3 => N65,
LO => N85
);
adder_16bit_bit3_Mxor_s_xo_0_11_SW3 : LUT4_L
generic map(
INIT => X"FB40"
)
port map (
I0 => i_pc_prime_5_4_304,
I1 => PCreg_q(1),
I2 => N69,
I3 => N70,
LO => N88
);
adder_16bit_bit3_Mxor_s_xo_0_11_SW5 : LUT4_L
generic map(
INIT => X"F780"
)
port map (
I0 => PCreg_q(2),
I1 => PCreg_q(1),
I2 => N73,
I3 => N72,
LO => N91
);
i_pc_prime_14_35_SW0 : LUT4_L
generic map(
INIT => X"ACA0"
)
port map (
I0 => MEM_q(14),
I1 => i_pc_prime_14_9_295,
I2 => i_jmp,
I3 => adder_16bit_bit11_cout_and0001,
LO => N95
);
i_pc_prime_2_12_SW1_F : LUT3_L
generic map(
INIT => X"F8"
)
port map (
I0 => adder_16bit_N11,
I1 => PCreg_q(1),
I2 => PCreg_q(2),
LO => N104
);
cpu_alu_i_A_in_2_SW0 : LUT4_L
generic map(
INIT => X"8689"
)
port map (
I0 => cpu_alu_A_data_out(2),
I1 => i_data_frm_ram(2),
I2 => cpu_alu_i_arith_S,
I3 => cpu_alu_N0,
LO => N120
);
i_pc_prime_2_12_SW01 : LUT3_D
generic map(
INIT => X"D8"
)
port map (
I0 => i_jmp,
I1 => MEM_q(2),
I2 => N102,
LO => N135,
O => N75
);
end Structure;
|
unlicense
|
PiJoules/Zybo-Vision-Processing
|
hdmi_passthrough_720p.srcs/sources_1/ipshared/digilentinc.com/dvi2rgb_v1_4/4f0fd262/src/TMDS_Clocking.vhd
|
14
|
11908
|
-------------------------------------------------------------------------------
--
-- File: TMDS_Clocking.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 10 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module instantiates all the necessary primitives to obtain a fast
-- serial clock from the TMDS Clock pins to be used for deserializing the TMDS
-- Data channels. Connect this module directly to the top-level TMDS Clock pins
-- and a 200/300 MHz reference clock.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.math_real.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity TMDS_Clocking is
Generic (
kClkRange : natural := 1); -- MULT_F = kClkRange*5 (choose >=120MHz=1, >=60MHz=2, >=40MHz=3, >=30MHz=4, >=25MHz=5
Port (
TMDS_Clk_p : in std_logic;
TMDS_Clk_n : in std_logic;
RefClk : in std_logic; -- 200MHz reference clock for IDELAY primitives; independent of DVI_Clk!
aRst : in std_logic; --asynchronous reset; must be reset when RefClk is not within spec
SerialClk : out std_logic;
PixelClk : out std_logic;
aLocked : out std_logic);
end TMDS_Clocking;
architecture Behavioral of TMDS_Clocking is
constant kDlyRstDelay : natural := 32;
signal aDlyLckd, rDlyRst, rBUFR_Rst, rLockLostRst : std_logic;
signal rDlyRstCnt : natural range 0 to kDlyRstDelay - 1 := kDlyRstDelay - 1;
signal clkfbout_hdmi_clk, CLK_IN_hdmi_clk, CLK_OUT_1x_hdmi_clk, CLK_OUT_5x_hdmi_clk : std_logic;
signal clkout1b_unused, clkout2_unused, clkout2b_unused, clkout3_unused, clkout3b_unused, clkout4_unused, clkout5_unused, clkout6_unused,
drdy_unused, psdone_unused, clkfbstopped_unused, clkinstopped_unused, clkfboutb_unused, clkout0b_unused, clkout1_unused : std_logic;
signal do_unused : std_logic_vector(15 downto 0);
signal LOCKED_int, rRdyRst : std_logic;
signal aMMCM_Locked, rMMCM_Locked_ms, rMMCM_Locked, rMMCM_LckdFallingFlag, rMMCM_LckdRisingFlag : std_logic;
signal rMMCM_Reset_q : std_logic_vector(1 downto 0);
signal rMMCM_Locked_q : std_logic_vector(1 downto 0);
begin
-- We need a reset bridge to use the asynchronous aRst signal to reset our circuitry
-- and decrease the chance of metastability. The signal rLockLostRst can be used as
-- asynchronous reset for any flip-flop in the RefClk domain, since it will be de-asserted
-- synchronously.
LockLostReset: entity work.ResetBridge
generic map (
kPolarity => '1')
port map (
aRst => aRst,
OutClk => RefClk,
oRst => rLockLostRst);
--IDELAYCTRL must be reset after configuration or refclk lost for 52ns(K7), 72ns(A7) at least
ResetIDELAYCTRL: process(rLockLostRst, RefClk)
begin
if Rising_Edge(RefClk) then
if (rLockLostRst = '1') then
rDlyRstCnt <= kDlyRstDelay - 1;
rDlyRst <= '1';
elsif (rDlyRstCnt /= 0) then
rDlyRstCnt <= rDlyRstCnt - 1;
else
rDlyRst <= '0';
end if;
end if;
end process;
IDelayCtrlX: IDELAYCTRL
port map (
RDY => aDlyLckd,
REFCLK => RefClk,
RST => rDlyRst);
RdyLostReset: entity work.ResetBridge
generic map (
kPolarity => '1')
port map (
aRst => not aDlyLckd,
OutClk => RefClk,
oRst => rRdyRst);
InputBuffer: IBUFDS
generic map (
DIFF_TERM => FALSE, -- Differential Termination
IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "TMDS_33")
port map
(
O => CLK_IN_hdmi_clk,
I => TMDS_Clk_p,
IB => TMDS_Clk_n);
-- The TMDS Clk channel carries a character-rate frequency reference
-- In a single Clk period a whole character (10 bits) is transmitted
-- on each data channel. For deserialization of data channel a faster,
-- serial clock needs to be generated. In 7-series architecture an
-- ISERDESE2 primitive doing a 10:1 deserialization in DDR mode needs
-- a fast 5x clock and a slow 1x clock. These two clocks are generated
-- below with an MMCME2_ADV and BUFR primitive.
-- Caveats:
-- 1. The primitive uses a multiply-by-5 and divide-by-1 to generate
-- a 5x fast clock.
-- While changes in the frequency of the TMDS Clk are tracked by the
-- MMCM, for some TMDS Clk frequencies the datasheet specs for the VCO
-- frequency limits are not met. In other words, there is no single
-- set of MMCM multiply and divide values that can work for the whole
-- range of resolutions and pixel clock frequencies.
-- For example: MMCM_FVCOMIN = 600 MHz
-- MMCM_FVCOMAX = 1200 MHz for Artix-7 -1 speed grade
-- while FVCO = FIN * MULT_F
-- The TMDS Clk for 720p resolution in 74.25 MHz
-- FVCO = 74.25 * 10 = 742.5 MHz, which is between FVCOMIN and FVCOMAX
-- However, the TMDS Clk for 1080p resolution in 148.5 MHz
-- FVCO = 148.5 * 10 = 1480 MHZ, which is above FVCOMAX
-- In the latter case, MULT_F = 5, DIVIDE_F = 5, DIVIDE = 1 would result
-- in a correct VCO frequency, while still generating 5x and 1x clocks
-- 2. The MMCM+BUFIO+BUFR combination results in the highest possible
-- frequencies. PLLE2_ADV could work only with BUFGs, which limits
-- the maximum achievable frequency. The reason is that only the MMCM
-- has dedicated route to BUFIO.
-- If a PLLE2_ADV with BUFGs are used a second CLKOUTx can be used to
-- generate the 1x clock.
DVI_ClkGenerator: MMCME2_ADV
generic map
(BANDWIDTH => "OPTIMIZED",
CLKOUT4_CASCADE => FALSE,
COMPENSATION => "ZHOLD",
STARTUP_WAIT => FALSE,
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT_F => real(kClkRange) * 5.0,
CLKFBOUT_PHASE => 0.000,
CLKFBOUT_USE_FINE_PS => FALSE,
CLKOUT0_DIVIDE_F => real(kClkRange) * 1.0,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT0_USE_FINE_PS => FALSE,
CLKIN1_PERIOD => real(kClkRange) * 6.0,
REF_JITTER1 => 0.010)
port map
-- Output clocks
(
CLKFBOUT => clkfbout_hdmi_clk,
CLKFBOUTB => clkfboutb_unused,
CLKOUT0 => CLK_OUT_5x_hdmi_clk,
CLKOUT0B => clkout0b_unused,
CLKOUT1 => clkout1_unused,
CLKOUT1B => clkout1b_unused,
CLKOUT2 => clkout2_unused,
CLKOUT2B => clkout2b_unused,
CLKOUT3 => clkout3_unused,
CLKOUT3B => clkout3b_unused,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
CLKOUT6 => clkout6_unused,
-- Input clock control
CLKFBIN => clkfbout_hdmi_clk,
CLKIN1 => CLK_IN_hdmi_clk,
CLKIN2 => '0',
-- Tied to always select the primary input clock
CLKINSEL => '1',
-- Ports for dynamic reconfiguration
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DO => do_unused,
DRDY => drdy_unused,
DWE => '0',
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => psdone_unused,
-- Other control and status signals
LOCKED => aMMCM_Locked,
CLKINSTOPPED => clkinstopped_unused,
CLKFBSTOPPED => clkfbstopped_unused,
PWRDWN => '0',
RST => rMMCM_Reset_q(0));
-- 5x fast serial clock
SerialClkBuffer: BUFIO
port map (
O => SerialClk, -- 1-bit output: Clock output (connect to I/O clock loads).
I => CLK_OUT_5x_hdmi_clk -- 1-bit input: Clock input (connect to an IBUF or BUFMR).
);
-- 1x slow parallel clock
PixelClkBuffer: BUFR
generic map (
BUFR_DIVIDE => "5", -- Values: "BYPASS, 1, 2, 3, 4, 5, 6, 7, 8"
SIM_DEVICE => "7SERIES" -- Must be set to "7SERIES"
)
port map (
O => PixelClk, -- 1-bit output: Clock output port
CE => '1', -- 1-bit input: Active high, clock enable (Divided modes only)
CLR => rBUFR_Rst, -- 1-bit input: Active high, asynchronous clear (Divided modes only)
I => CLK_OUT_5x_hdmi_clk -- 1-bit input: Clock buffer input driven by an IBUF, MMCM or local interconnect
);
rBUFR_Rst <= rMMCM_LckdRisingFlag; --pulse CLR on BUFR one the clock returns
MMCM_Reset: process(rLockLostRst, RefClk)
begin
if (rLockLostRst = '1') then
rMMCM_Reset_q <= (others => '1'); -- MMCM_RSTMINPULSE Minimum Reset Pulse Width 5.00ns = two RefClk periods min
elsif Rising_Edge(RefClk) then
if (rMMCM_LckdFallingFlag = '1') then
rMMCM_Reset_q <= (others => '1');
else
rMMCM_Reset_q <= '0' & rMMCM_Reset_q(rMMCM_Reset_q'high downto 1);
end if;
end if;
end process MMCM_Reset;
MMCM_LockSync: entity work.SyncAsync
port map (
aReset => '0',
aIn => aMMCM_Locked,
OutClk => RefClk,
oOut => rMMCM_Locked);
MMCM_LockedDetect: process(RefClk)
begin
if Rising_Edge(RefClk) then
rMMCM_Locked_q <= rMMCM_Locked & rMMCM_Locked_q(1);
rMMCM_LckdFallingFlag <= rMMCM_Locked_q(1) and not rMMCM_Locked;
rMMCM_LckdRisingFlag <= not rMMCM_Locked_q(1) and rMMCM_Locked;
end if;
end process MMCM_LockedDetect;
GlitchFreeLocked: process(rRdyRst, RefClk)
begin
if (rRdyRst = '1') then
aLocked <= '0';
elsif Rising_Edge(RefClk) then
aLocked <= rMMCM_Locked_q(0);
end if;
end process GlitchFreeLocked;
end Behavioral;
|
unlicense
|
PiJoules/Zybo-Vision-Processing
|
hdmi_passthrough_720p.srcs/sources_1/ipshared/digilentinc.com/dvi2rgb_v1_4/4f0fd262/src/SyncBase.vhd
|
15
|
3854
|
-------------------------------------------------------------------------------
--
-- File: SyncBase.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 20 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module synchronizes a signal (iIn) in one clock domain (InClk) with
-- another clock domain (OutClk) and provides it on oOut.
-- The number of FFs in the synchronizer chain
-- can be configured with kStages. The reset value for oOut can be configured
-- with kResetTo. The asynchronous reset (aReset) is always active-high.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity SyncBase is
Generic (
kResetTo : std_logic := '0'; --value when reset and upon init
kStages : natural := 2); --double sync by default
Port (
aReset : in STD_LOGIC; -- active-high asynchronous reset
InClk : in std_logic;
iIn : in STD_LOGIC;
OutClk : in STD_LOGIC;
oOut : out STD_LOGIC);
end SyncBase;
architecture Behavioral of SyncBase is
signal iIn_q : std_logic;
begin
--By re-registering iIn on its own domain, we make sure iIn_q is glitch-free
SyncSource: process(aReset, InClk)
begin
if (aReset = '1') then
iIn_q <= kResetTo;
elsif Rising_Edge(InClk) then
iIn_q <= iIn;
end if;
end process SyncSource;
--Crossing clock boundary here
SyncAsyncx: entity work.SyncAsync
generic map (
kResetTo => kResetTo,
kStages => kStages)
port map (
aReset => aReset,
aIn => iIn_q,
OutClk => OutClk,
oOut => oOut);
end Behavioral;
|
unlicense
|
PiJoules/Zybo-Vision-Processing
|
hdmi_passthrough_720p.srcs/sources_1/ipshared/digilentinc.com/dvi2rgb_v1_4/4f0fd262/src/GlitchFilter.vhd
|
15
|
3919
|
-------------------------------------------------------------------------------
--
-- File: GlitchFilter.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 22 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module filters any pulses on sIn lasting less than the number of
-- periods specified in kNoOfPeriodsToFilter. The output sOut will be
-- delayed by kNoOfPeriodsToFilter cycles, but glitch-free.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity GlitchFilter is
Generic (
kNoOfPeriodsToFilter : natural);
Port (
SampleClk : in STD_LOGIC;
sIn : in STD_LOGIC;
sOut : out STD_LOGIC;
sRst : in STD_LOGIC);
end GlitchFilter;
architecture Behavioral of GlitchFilter is
signal cntPeriods : natural range 0 to kNoOfPeriodsToFilter - 1 := kNoOfPeriodsToFilter - 1;
signal sIn_q : std_logic;
begin
Bypass: if kNoOfPeriodsToFilter = 0 generate
sOut <= sIn;
end generate Bypass;
Filter: if kNoOfPeriodsToFilter > 0 generate
process (SampleClk)
begin
if Rising_Edge(SampleClk) then
sIn_q <= sIn;
if (cntPeriods = 0) then
sOut <= sIn_q;
end if;
end if;
end process;
PeriodCounter: process (SampleClk)
begin
if Rising_Edge(SampleClk) then
if (sIn_q /= sIn or sRst = '1') then --edge detected
cntPeriods <= kNoOfPeriodsToFilter - 1; --reset counter
elsif (cntPeriods /= 0) then
cntPeriods <= cntPeriods - 1; --count down
end if;
end if;
end process PeriodCounter;
end generate Filter;
end Behavioral;
|
unlicense
|
TWW12/lzw
|
final_project_sim/lzw/lzw.srcs/sources_1/imports/temp/dictionary_block_2.vhd
|
4
|
5040
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity dictionary_block_2 is
generic( block_num : integer := 0);
port (
clk : in std_logic;
rst : in std_logic;
start_search : in std_logic;
search_entry : in std_logic_vector(19 downto 0);
halt_search : in std_logic;
--Write enable & entries
wr_en : in std_logic;
wr_addr : in std_logic_vector(10 downto 0);
wr_entry : in std_logic_vector(19 downto 0);
--Outputs
prefix : out std_logic_vector(10 downto 0);
entry_found : out std_logic;
search_completed : out std_logic);
end dictionary_block_2;
architecture Behavioral of dictionary_block_2 is
component bram_2048_0 is
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(19 DOWNTO 0)
);
end component;
component bram_2048_1 is
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(19 DOWNTO 0)
);
end component;
type state_type is (S_RST,S_GO,S_WAIT,S_SEARCH);
signal state : state_type;
signal rd_addr : std_logic_vector(11 downto 0);
signal addr : std_logic_vector(10 downto 0);
signal bram_out : std_logic_vector(19 downto 0);
signal full : std_logic;
signal rd_addr_delay : std_logic_vector(11 downto 0);
signal wr_entry_delay : std_logic_vector(19 downto 0);
begin
GEN_BLOCK_0: if block_num = 0 generate
U_BRAM : bram_2048_0
port map(
clka => clk,
ena => '1',
wea(0) => wr_en,
addra => addr,
dina => wr_entry_delay,
douta => bram_out);
end generate GEN_BLOCK_0;
GEN_BLOCK_1 : if block_num = 1 generate
U_BRAM : bram_2048_1
port map(
clka => clk,
ena => '1',
wea(0) => wr_en,
addra => addr,
dina => wr_entry_delay,
douta => bram_out);
end generate GEN_BLOCK_1;
with wr_en select addr <=
wr_addr when '1',
rd_addr(10 downto 0) when others;
process(clk,rst)
begin
if rst = '1' then
state <= S_RST;
rd_addr <= (rd_addr'range => '0');
entry_found <= '0';
search_completed <= '0';
prefix <= (prefix'range => '0');
wr_entry_delay <= (wr_entry_delay'range => '0');
rd_addr_delay <= (rd_addr_delay'range => '0');
elsif rising_edge(clk) then
rd_addr_delay <= rd_addr;
wr_entry_delay <= wr_entry;
case state is
when S_RST =>
state <= S_GO;
--idle until its time to search
when S_GO =>
rd_addr <= (rd_addr'range => '0');
entry_found <= '0';
search_completed <= '0';
prefix <= (prefix'range => '0');
if start_search = '1' then
state <= S_WAIT;
end if;
when S_WAIT =>
state <= S_SEARCH;
when S_SEARCH =>
rd_addr <= std_logic_vector(unsigned(rd_addr)+to_unsigned(1,12));
--Did we find the entry?
if search_entry = bram_out then
state <= S_GO;
entry_found <= '1';
search_completed <= '1';
prefix <= rd_addr_delay(10 downto 0);--std_logic_vector(unsigned(rd_addr(10 downto 0))-to_unsigned(1,11));
rd_addr <= (others => '0');
end if;
--Did we go through the whole dictionary?
if start_search = '1' then
state <= S_SEARCH;
rd_addr <= (others => '0');
elsif halt_search = '1' then
state <= S_GO;
rd_addr <= (others => '0');
elsif rd_addr = std_logic_vector(unsigned(wr_addr)+to_unsigned(3,12)) then
state <= S_GO;
rd_addr <= (others => '0');
search_completed <= '1';
end if;
end case;
end if;
end process;
end Behavioral;
|
unlicense
|
TWW12/lzw
|
final_project/lzw_compression/lzw_compression.srcs/sources_1/bd/design_1/ip/design_1_axi_compression_0_0/src/bram_2048_0/synth/bram_2048_0.vhd
|
4
|
14460
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_3_5;
USE blk_mem_gen_v8_3_5.blk_mem_gen_v8_3_5;
ENTITY bram_2048_0 IS
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(19 DOWNTO 0)
);
END bram_2048_0;
ARCHITECTURE bram_2048_0_arch OF bram_2048_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF bram_2048_0_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_3_5 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
rsta_busy : OUT STD_LOGIC;
rstb_busy : OUT STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(10 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_5;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF bram_2048_0_arch: ARCHITECTURE IS "blk_mem_gen_v8_3_5,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF bram_2048_0_arch : ARCHITECTURE IS "bram_2048_0,blk_mem_gen_v8_3_5,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF bram_2048_0_arch: ARCHITECTURE IS "bram_2048_0,blk_mem_gen_v8_3_5,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.3,x_ipCoreRevision=5,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=0,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=bram_2048_0.mi" &
"f,C_INIT_FILE=bram_2048_0.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=20,C_READ_WIDTH_A=20,C_WRITE_DEPTH_A=2048,C_READ_DEPTH_A=2048,C_ADDRA_WIDTH=11,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=20,C_READ_WIDTH_B=20,C_WRITE_DE" &
"PTH_B=2048,C_READ_DEPTH_B=2048,C_ADDRB_WIDTH=11,C_HAS_MEM_OUTPUT_REGS_A=1,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_EN_SAFETY_CKT=0,C_DISABLE" &
"_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=1,C_COUNT_18K_BRAM=1,C_EST_POWER_SUMMARY=Estimated Power for IP _ 3.9373 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : blk_mem_gen_v8_3_5
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 0,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 1,
C_INIT_FILE_NAME => "bram_2048_0.mif",
C_INIT_FILE => "bram_2048_0.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 1,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 20,
C_READ_WIDTH_A => 20,
C_WRITE_DEPTH_A => 2048,
C_READ_DEPTH_A => 2048,
C_ADDRA_WIDTH => 11,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 20,
C_READ_WIDTH_B => 20,
C_WRITE_DEPTH_B => 2048,
C_READ_DEPTH_B => 2048,
C_ADDRB_WIDTH => 11,
C_HAS_MEM_OUTPUT_REGS_A => 1,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_EN_SAFETY_CKT => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "1",
C_COUNT_18K_BRAM => "1",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 3.9373 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => ena,
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => '0',
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 11)),
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 20)),
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 20)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END bram_2048_0_arch;
|
unlicense
|
TWW12/lzw
|
ip_repo/axi_compression_1.0/src/bram_2048_0/synth/bram_2048_0.vhd
|
4
|
14460
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_3_5;
USE blk_mem_gen_v8_3_5.blk_mem_gen_v8_3_5;
ENTITY bram_2048_0 IS
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(19 DOWNTO 0)
);
END bram_2048_0;
ARCHITECTURE bram_2048_0_arch OF bram_2048_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF bram_2048_0_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_3_5 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
rsta_busy : OUT STD_LOGIC;
rstb_busy : OUT STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(10 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_5;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF bram_2048_0_arch: ARCHITECTURE IS "blk_mem_gen_v8_3_5,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF bram_2048_0_arch : ARCHITECTURE IS "bram_2048_0,blk_mem_gen_v8_3_5,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF bram_2048_0_arch: ARCHITECTURE IS "bram_2048_0,blk_mem_gen_v8_3_5,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.3,x_ipCoreRevision=5,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=0,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=bram_2048_0.mi" &
"f,C_INIT_FILE=bram_2048_0.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=20,C_READ_WIDTH_A=20,C_WRITE_DEPTH_A=2048,C_READ_DEPTH_A=2048,C_ADDRA_WIDTH=11,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=20,C_READ_WIDTH_B=20,C_WRITE_DE" &
"PTH_B=2048,C_READ_DEPTH_B=2048,C_ADDRB_WIDTH=11,C_HAS_MEM_OUTPUT_REGS_A=1,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_EN_SAFETY_CKT=0,C_DISABLE" &
"_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=1,C_COUNT_18K_BRAM=1,C_EST_POWER_SUMMARY=Estimated Power for IP _ 3.9373 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : blk_mem_gen_v8_3_5
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 0,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 1,
C_INIT_FILE_NAME => "bram_2048_0.mif",
C_INIT_FILE => "bram_2048_0.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 1,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 20,
C_READ_WIDTH_A => 20,
C_WRITE_DEPTH_A => 2048,
C_READ_DEPTH_A => 2048,
C_ADDRA_WIDTH => 11,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 20,
C_READ_WIDTH_B => 20,
C_WRITE_DEPTH_B => 2048,
C_READ_DEPTH_B => 2048,
C_ADDRB_WIDTH => 11,
C_HAS_MEM_OUTPUT_REGS_A => 1,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_EN_SAFETY_CKT => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "1",
C_COUNT_18K_BRAM => "1",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 3.9373 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => ena,
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => '0',
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 11)),
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 20)),
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 20)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END bram_2048_0_arch;
|
unlicense
|
TWW12/lzw
|
final_project_sim/lzw/lzw.cache/ip/40c681daa8c49851/bram_1024_2_sim_netlist.vhdl
|
1
|
52972
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Tue Apr 18 23:18:54 2017
-- Host : DESKTOP-I9J3TQJ running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ bram_1024_2_sim_netlist.vhdl
-- Design : bram_1024_2
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init is
port (
douta : out STD_LOGIC_VECTOR ( 19 downto 0 );
clka : in STD_LOGIC;
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 );
dina : in STD_LOGIC_VECTOR ( 19 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_21\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_22\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_23\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_29\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_30\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_31\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_37\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_38\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_39\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_45\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_46\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_47\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_85\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_86\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_87\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000001F0000001B00000017000000130000000F0000000B0000000700000003",
INIT_01 => X"0000011F0000011B00000117000001130000010F0000010B0000010700000103",
INIT_02 => X"0000021F0000021B00000217000002130000020F0000020B0000020700000203",
INIT_03 => X"0000031F0000031B00000317000003130000030F0000030B0000030700000303",
INIT_04 => X"0000041F0000041B00000417000004130000040F0000040B0000040700000403",
INIT_05 => X"0000051F0000051B00000517000005130000050F0000050B0000050700000503",
INIT_06 => X"0000061F0000061B00000617000006130000060F0000060B0000060700000603",
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INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => addra(9 downto 0),
ADDRARDADDR(4 downto 0) => B"11111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 29) => B"000",
DIADI(28 downto 24) => dina(19 downto 15),
DIADI(23 downto 21) => B"000",
DIADI(20 downto 16) => dina(14 downto 10),
DIADI(15 downto 13) => B"000",
DIADI(12 downto 8) => dina(9 downto 5),
DIADI(7 downto 5) => B"000",
DIADI(4 downto 0) => dina(4 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_21\,
DOADO(30) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_22\,
DOADO(29) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_23\,
DOADO(28 downto 24) => douta(19 downto 15),
DOADO(23) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_29\,
DOADO(22) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_30\,
DOADO(21) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_31\,
DOADO(20 downto 16) => douta(14 downto 10),
DOADO(15) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_37\,
DOADO(14) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_38\,
DOADO(13) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_39\,
DOADO(12 downto 8) => douta(9 downto 5),
DOADO(7) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_45\,
DOADO(6) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_46\,
DOADO(5) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_47\,
DOADO(4 downto 0) => douta(4 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_85\,
DOPADOP(2) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_86\,
DOPADOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_87\,
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\,
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => ena,
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width is
port (
douta : out STD_LOGIC_VECTOR ( 19 downto 0 );
clka : in STD_LOGIC;
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 );
dina : in STD_LOGIC_VECTOR ( 19 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width is
begin
\prim_init.ram\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
dina(19 downto 0) => dina(19 downto 0),
douta(19 downto 0) => douta(19 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr is
port (
douta : out STD_LOGIC_VECTOR ( 19 downto 0 );
clka : in STD_LOGIC;
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 );
dina : in STD_LOGIC_VECTOR ( 19 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr is
begin
\ramloop[0].ram.r\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
dina(19 downto 0) => dina(19 downto 0),
douta(19 downto 0) => douta(19 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top is
port (
douta : out STD_LOGIC_VECTOR ( 19 downto 0 );
clka : in STD_LOGIC;
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 );
dina : in STD_LOGIC_VECTOR ( 19 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top is
begin
\valid.cstr\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
dina(19 downto 0) => dina(19 downto 0),
douta(19 downto 0) => douta(19 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5_synth is
port (
douta : out STD_LOGIC_VECTOR ( 19 downto 0 );
clka : in STD_LOGIC;
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 );
dina : in STD_LOGIC_VECTOR ( 19 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5_synth;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5_synth is
begin
\gnbram.gnativebmg.native_blk_mem_gen\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
dina(19 downto 0) => dina(19 downto 0),
douta(19 downto 0) => douta(19 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 is
port (
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
regcea : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 9 downto 0 );
dina : in STD_LOGIC_VECTOR ( 19 downto 0 );
douta : out STD_LOGIC_VECTOR ( 19 downto 0 );
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
regceb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 9 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 19 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 19 downto 0 );
injectsbiterr : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
eccpipece : in STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
rdaddrecc : out STD_LOGIC_VECTOR ( 9 downto 0 );
sleep : in STD_LOGIC;
deepsleep : in STD_LOGIC;
shutdown : in STD_LOGIC;
rsta_busy : out STD_LOGIC;
rstb_busy : out STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 19 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 19 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_injectsbiterr : in STD_LOGIC;
s_axi_injectdbiterr : in STD_LOGIC;
s_axi_sbiterr : out STD_LOGIC;
s_axi_dbiterr : out STD_LOGIC;
s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 10;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 10;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "1";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "Estimated Power for IP : 2.74095 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "zynq";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "bram_1024_2.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "bram_1024_2.mif";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 1024;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 1024;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 20;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 20;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 1024;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 1024;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 20;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 20;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "zynq";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "yes";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 is
signal \<const0>\ : STD_LOGIC;
begin
dbiterr <= \<const0>\;
doutb(19) <= \<const0>\;
doutb(18) <= \<const0>\;
doutb(17) <= \<const0>\;
doutb(16) <= \<const0>\;
doutb(15) <= \<const0>\;
doutb(14) <= \<const0>\;
doutb(13) <= \<const0>\;
doutb(12) <= \<const0>\;
doutb(11) <= \<const0>\;
doutb(10) <= \<const0>\;
doutb(9) <= \<const0>\;
doutb(8) <= \<const0>\;
doutb(7) <= \<const0>\;
doutb(6) <= \<const0>\;
doutb(5) <= \<const0>\;
doutb(4) <= \<const0>\;
doutb(3) <= \<const0>\;
doutb(2) <= \<const0>\;
doutb(1) <= \<const0>\;
doutb(0) <= \<const0>\;
rdaddrecc(9) <= \<const0>\;
rdaddrecc(8) <= \<const0>\;
rdaddrecc(7) <= \<const0>\;
rdaddrecc(6) <= \<const0>\;
rdaddrecc(5) <= \<const0>\;
rdaddrecc(4) <= \<const0>\;
rdaddrecc(3) <= \<const0>\;
rdaddrecc(2) <= \<const0>\;
rdaddrecc(1) <= \<const0>\;
rdaddrecc(0) <= \<const0>\;
rsta_busy <= \<const0>\;
rstb_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(3) <= \<const0>\;
s_axi_bid(2) <= \<const0>\;
s_axi_bid(1) <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_dbiterr <= \<const0>\;
s_axi_rdaddrecc(9) <= \<const0>\;
s_axi_rdaddrecc(8) <= \<const0>\;
s_axi_rdaddrecc(7) <= \<const0>\;
s_axi_rdaddrecc(6) <= \<const0>\;
s_axi_rdaddrecc(5) <= \<const0>\;
s_axi_rdaddrecc(4) <= \<const0>\;
s_axi_rdaddrecc(3) <= \<const0>\;
s_axi_rdaddrecc(2) <= \<const0>\;
s_axi_rdaddrecc(1) <= \<const0>\;
s_axi_rdaddrecc(0) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(3) <= \<const0>\;
s_axi_rid(2) <= \<const0>\;
s_axi_rid(1) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_sbiterr <= \<const0>\;
s_axi_wready <= \<const0>\;
sbiterr <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
inst_blk_mem_gen: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5_synth
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
dina(19 downto 0) => dina(19 downto 0),
douta(19 downto 0) => douta(19 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
clka : in STD_LOGIC;
ena : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 9 downto 0 );
dina : in STD_LOGIC_VECTOR ( 19 downto 0 );
douta : out STD_LOGIC_VECTOR ( 19 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "bram_1024_2,blk_mem_gen_v8_3_5,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "blk_mem_gen_v8_3_5,Vivado 2016.4";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_doutb_UNCONNECTED : STD_LOGIC_VECTOR ( 19 downto 0 );
signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 19 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of U0 : label is 10;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of U0 : label is 10;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of U0 : label is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of U0 : label is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of U0 : label is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of U0 : label is "0";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of U0 : label is "1";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of U0 : label is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of U0 : label is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of U0 : label is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of U0 : label is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of U0 : label is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of U0 : label is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of U0 : label is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 2.74095 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "zynq";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of U0 : label is 1;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of U0 : label is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 1;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of U0 : label is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of U0 : label is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of U0 : label is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of U0 : label is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of U0 : label is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of U0 : label is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of U0 : label is "bram_1024_2.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of U0 : label is "bram_1024_2.mif";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of U0 : label is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of U0 : label is 0;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of U0 : label is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of U0 : label is 1024;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of U0 : label is 1024;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of U0 : label is 20;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of U0 : label is 20;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of U0 : label is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of U0 : label is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of U0 : label is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of U0 : label is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of U0 : label is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of U0 : label is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of U0 : label is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of U0 : label is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of U0 : label is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of U0 : label is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of U0 : label is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of U0 : label is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of U0 : label is 1024;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of U0 : label is 1024;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of U0 : label is 20;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of U0 : label is 20;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "zynq";
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5
port map (
addra(9 downto 0) => addra(9 downto 0),
addrb(9 downto 0) => B"0000000000",
clka => clka,
clkb => '0',
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
deepsleep => '0',
dina(19 downto 0) => dina(19 downto 0),
dinb(19 downto 0) => B"00000000000000000000",
douta(19 downto 0) => douta(19 downto 0),
doutb(19 downto 0) => NLW_U0_doutb_UNCONNECTED(19 downto 0),
eccpipece => '0',
ena => ena,
enb => '0',
injectdbiterr => '0',
injectsbiterr => '0',
rdaddrecc(9 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(9 downto 0),
regcea => '0',
regceb => '0',
rsta => '0',
rsta_busy => NLW_U0_rsta_busy_UNCONNECTED,
rstb => '0',
rstb_busy => NLW_U0_rstb_busy_UNCONNECTED,
s_aclk => '0',
s_aresetn => '0',
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"00",
s_axi_arid(3 downto 0) => B"0000",
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arsize(2 downto 0) => B"000",
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"00",
s_axi_awid(3 downto 0) => B"0000",
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awsize(2 downto 0) => B"000",
s_axi_awvalid => '0',
s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
s_axi_injectdbiterr => '0',
s_axi_injectsbiterr => '0',
s_axi_rdaddrecc(9 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(9 downto 0),
s_axi_rdata(19 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(19 downto 0),
s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
s_axi_wdata(19 downto 0) => B"00000000000000000000",
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(0) => '0',
s_axi_wvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
shutdown => '0',
sleep => '0',
wea(0) => wea(0),
web(0) => '0'
);
end STRUCTURE;
|
unlicense
|
TWW12/lzw
|
final_project/lzw_compression/lzw_compression.ipdefs/axi_compression_1.0_0_0/src/bram_4096/misc/blk_mem_gen_v8_3.vhd
|
45
|
8325
|
library ieee;
use ieee.std_logic_1164.all;
entity blk_mem_gen_v8_3_5 is
generic (
C_FAMILY : string := "virtex7";
C_XDEVICEFAMILY : string := "virtex7";
C_ELABORATION_DIR : string := "";
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE : integer := 1;
C_AXI_SLAVE_TYPE : integer := 0;
C_USE_BRAM_BLOCK : integer := 0;
C_ENABLE_32BIT_ADDRESS : integer := 0;
C_CTRL_ECC_ALGO : string := "ECCHSIAO32-7";
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
C_MEM_TYPE : integer := 2;
C_BYTE_SIZE : integer := 9;
C_ALGORITHM : integer := 0;
C_PRIM_TYPE : integer := 3;
C_LOAD_INIT_FILE : integer := 0;
C_INIT_FILE_NAME : string := "no_coe_file_loaded";
C_INIT_FILE : string := "no_mem_file_loaded";
C_USE_DEFAULT_DATA : integer := 0;
C_DEFAULT_DATA : string := "0";
C_HAS_RSTA : integer := 0;
C_RST_PRIORITY_A : string := "ce";
C_RSTRAM_A : integer := 0;
C_INITA_VAL : string := "0";
C_HAS_ENA : integer := 1;
C_HAS_REGCEA : integer := 0;
C_USE_BYTE_WEA : integer := 0;
C_WEA_WIDTH : integer := 1;
C_WRITE_MODE_A : string := "WRITE_FIRST";
C_WRITE_WIDTH_A : integer := 9;
C_READ_WIDTH_A : integer := 9;
C_WRITE_DEPTH_A : integer := 2048;
C_READ_DEPTH_A : integer := 2048;
C_ADDRA_WIDTH : integer := 11;
C_HAS_RSTB : integer := 0;
C_RST_PRIORITY_B : string := "ce";
C_RSTRAM_B : integer := 0;
C_INITB_VAL : string := "0";
C_HAS_ENB : integer := 1;
C_HAS_REGCEB : integer := 0;
C_USE_BYTE_WEB : integer := 0;
C_WEB_WIDTH : integer := 1;
C_WRITE_MODE_B : string := "WRITE_FIRST";
C_WRITE_WIDTH_B : integer := 9;
C_READ_WIDTH_B : integer := 9;
C_WRITE_DEPTH_B : integer := 2048;
C_READ_DEPTH_B : integer := 2048;
C_ADDRB_WIDTH : integer := 11;
C_HAS_MEM_OUTPUT_REGS_A : integer := 0;
C_HAS_MEM_OUTPUT_REGS_B : integer := 0;
C_HAS_MUX_OUTPUT_REGS_A : integer := 0;
C_HAS_MUX_OUTPUT_REGS_B : integer := 0;
C_MUX_PIPELINE_STAGES : integer := 0;
C_HAS_SOFTECC_INPUT_REGS_A : integer := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : integer := 0;
C_USE_SOFTECC : integer := 0;
C_USE_ECC : integer := 0;
C_EN_ECC_PIPE : integer := 0;
C_HAS_INJECTERR : integer := 0;
C_SIM_COLLISION_CHECK : string := "none";
C_COMMON_CLK : integer := 0;
C_DISABLE_WARN_BHV_COLL : integer := 0;
C_EN_SLEEP_PIN : integer := 0;
C_USE_URAM : integer := 0;
C_EN_RDADDRA_CHG : integer := 0;
C_EN_RDADDRB_CHG : integer := 0;
C_EN_DEEPSLEEP_PIN : integer := 0;
C_EN_SHUTDOWN_PIN : integer := 0;
C_EN_SAFETY_CKT : integer := 0;
C_DISABLE_WARN_BHV_RANGE : integer := 0;
C_COUNT_36K_BRAM : string := "";
C_COUNT_18K_BRAM : string := "";
C_EST_POWER_SUMMARY : string := ""
);
port (
clka : in std_logic := '0';
rsta : in std_logic := '0';
ena : in std_logic := '0';
regcea : in std_logic := '0';
wea : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
addra : in std_logic_vector(c_addra_width - 1 downto 0) := (others => '0');
dina : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
douta : out std_logic_vector(c_read_width_a - 1 downto 0);
clkb : in std_logic := '0';
rstb : in std_logic := '0';
enb : in std_logic := '0';
regceb : in std_logic := '0';
web : in std_logic_vector(c_web_width - 1 downto 0) := (others => '0');
addrb : in std_logic_vector(c_addrb_width - 1 downto 0) := (others => '0');
dinb : in std_logic_vector(c_write_width_b - 1 downto 0) := (others => '0');
doutb : out std_logic_vector(c_read_width_b - 1 downto 0);
injectsbiterr : in std_logic := '0';
injectdbiterr : in std_logic := '0';
eccpipece : in std_logic := '0';
sbiterr : out std_logic;
dbiterr : out std_logic;
rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0);
sleep : in std_logic := '0';
deepsleep : in std_logic := '0';
shutdown : in std_logic := '0';
rsta_busy : out std_logic;
rstb_busy : out std_logic;
s_aclk : in std_logic := '0';
s_aresetn : in std_logic := '0';
s_axi_awid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_awaddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_awlen : in std_logic_vector(7 downto 0) := (others => '0');
s_axi_awsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_awburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_awvalid : in std_logic := '0';
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
s_axi_wstrb : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
s_axi_wlast : in std_logic := '0';
s_axi_wvalid : in std_logic := '0';
s_axi_wready : out std_logic;
s_axi_bid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic := '0';
s_axi_arid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_araddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_arlen : in std_logic_vector(8 - 1 downto 0) := (others => '0');
s_axi_arsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_arburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_arvalid : in std_logic := '0';
s_axi_arready : out std_logic;
s_axi_rid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_rdata : out std_logic_vector(c_write_width_b - 1 downto 0);
s_axi_rresp : out std_logic_vector(2 - 1 downto 0);
s_axi_rlast : out std_logic;
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic := '0';
s_axi_injectsbiterr : in std_logic := '0';
s_axi_injectdbiterr : in std_logic := '0';
s_axi_sbiterr : out std_logic;
s_axi_dbiterr : out std_logic;
s_axi_rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0)
);
end entity blk_mem_gen_v8_3_5;
architecture xilinx of blk_mem_gen_v8_3_5 is
begin
end
architecture xilinx;
|
unlicense
|
TWW12/lzw
|
final_project_sim/lzw/lzw.srcs/sim_1/imports/temp/dictionary_block_tb.vhd
|
1
|
3115
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity dictionary_block_tb is
end dictionary_block_tb;
architecture Behavioral of dictionary_block_tb is
signal clk : std_logic;
signal rst : std_logic;
signal start_search : std_logic := '0';
signal search_entry : std_logic_vector(19 downto 0);
signal wr_en : std_logic := '0';
signal wr_entry : std_logic_vector(19 downto 0) := x"00000";
signal prefix : std_logic_vector(11 downto 0);
signal entry_found : std_logic;
signal search_completed : std_logic;
signal search_prefix : std_logic_vector(11 downto 0) := x"000";
signal search_char : std_logic_vector(7 downto 0) := x"00";
begin
search_entry(19 downto 8) <= search_prefix;
search_entry(7 downto 0) <= search_char;
UUT : entity work.dictionary_4
port map(
clk => clk,
rst => rst,
start_search => start_search,
search_entry => search_entry,
wr_en => wr_en,
wr_entry => wr_entry,
prefix => prefix,
entry_found => entry_found,
search_completed => search_completed);
--Clock generation
process
begin
clk <= '0';
wait for 5 ns;
clk <= '1';
wait for 5 ns;
end process;
--Actual testing
process
begin
--hold reset for 3 cycles
rst <= '1';
wait for 30 ns;
rst <= '0';
wait for 10 ns;
--first search for an entry that shouldnt exist
search_prefix <= x"001";
search_char <= x"30";
start_search <= '1';
wait for 10 ns;
start_search <= '0';
--wait for search to complete
wait until search_completed = '1';
assert entry_found = '0' report "Entry found asserted for non-existant entry." severity failure;
wait for 10 ns;
--Check all dictionary entries
for i in 1 to 255 loop
search_prefix <= x"000";
search_char <= std_logic_vector(to_unsigned(i,8));
start_search <= '1';
wait for 10 ns;
start_search <= '0';
wait until search_completed = '1';
assert entry_found = '1' report "Entry not found." severity warning;
assert prefix = std_logic_vector(to_unsigned(i,12)) report "Incorrect resulting prefix." severity warning;
wait for 10 ns;
end loop;
--Write an entry to the dictionary
wr_entry <= x"00130"; --prefix = 0x001, char = 0x30
wr_en <= '1';
wait for 10 ns;
wr_en <= '0';
--Now try looking for it!
search_prefix <= x"001";
search_char <= x"30";
start_search <= '1';
wait for 10 ns;
start_search <= '0';
wait for 10 ns;
wait until search_completed = '1';
assert entry_found = '1' report "Newly written entry not found" severity failure;
report "Testbench completed." severity note;
wait;
end process;
end Behavioral;
|
unlicense
|
TWW12/lzw
|
final_project_sim/lzw/lzw.srcs/sim_1/imports/temp/lzw_tb.vhd
|
1
|
2909
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity lzw_tb is
end lzw_tb;
architecture Behavioral of lzw_tb is
--the rain in Spain falls mainly on the plain
constant str_len : integer := 43;
signal test_vector : std_logic_vector(str_len*8-1 downto 0) := x"746865207261696e20696e20537061696e2066616c6c73206d61696e6c79206f6e2074686520706c61696e";
constant result_len : integer := 33;
signal result_vector : std_logic_vector(result_len*12-1 downto 0) := x"07406806502007206106906E02010602005307010510706606106C06C07302006D10D06C07902006F10710010207006C10D";
signal clk : std_logic;
signal rst : std_logic;
signal char_in : std_logic_vector(7 downto 0) := x"00";
signal input_valid : std_logic := '0';
signal input_rd : std_logic;
signal prefix_out : std_logic_vector(11 downto 0);
signal expected : std_logic_vector(11 downto 0);
signal output_valid : std_logic;
signal done : std_logic;
signal file_size : std_logic_vector(15 downto 0) := std_logic_vector(to_unsigned(str_len,16));
begin
UUT : entity work.lzw
port map(
clk => clk,
rst => rst,
char_in => char_in,
input_valid => input_valid,
input_rd => input_rd,
file_size => file_size,
prefix_out => prefix_out,
done => done,
output_valid => output_valid);
clk_proc: process
begin
clk <= '1';
wait for 5 ns;
clk <= '0';
wait for 5 ns;
end process;
input_proc: process
variable i : integer := str_len-1;
begin
rst <= '1';
wait for 30 ns;
rst <= '0';
input_valid <= '1';
char_in <= test_vector(str_len*8-1 downto (str_len-1)*8);
while i /= 0 loop
if input_rd = '1' then
char_in <= test_vector(i*8-1 downto (i-1)*8);
i := i-1;
end if;
wait for 10 ns;
end loop;
char_in <= test_vector(7 downto 0);
wait until input_rd = '1';
input_valid <= '0';
wait for 10 ns;
char_in <= x"00";
wait;
end process;
output_proc : process
variable i : integer := result_len;
begin
wait for 10 ns;
expected <= result_vector(i*12-1 downto (i-1)*12);
if output_valid = '1' then
assert result_vector(i*12-1 downto (i-1)*12) = prefix_out report "Output prefix does not match." severity warning;
i := i-1;
end if;
if i = 1 then
report "Testbench completed." severity note;
wait;
end if;
end process;
end Behavioral;
|
unlicense
|
TWW12/lzw
|
final_project/lzw_compression/lzw_compression.ipdefs/axi_compression_1.0_0_0/src/input_fifo/synth/input_fifo.vhd
|
2
|
38764
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fifo_generator:13.1
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fifo_generator_v13_1_3;
USE fifo_generator_v13_1_3.fifo_generator_v13_1_3;
ENTITY input_fifo IS
PORT (
clk : IN STD_LOGIC;
srst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END input_fifo;
ARCHITECTURE input_fifo_arch OF input_fifo IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF input_fifo_arch: ARCHITECTURE IS "yes";
COMPONENT fifo_generator_v13_1_3 IS
GENERIC (
C_COMMON_CLOCK : INTEGER;
C_SELECT_XPM : INTEGER;
C_COUNT_TYPE : INTEGER;
C_DATA_COUNT_WIDTH : INTEGER;
C_DEFAULT_VALUE : STRING;
C_DIN_WIDTH : INTEGER;
C_DOUT_RST_VAL : STRING;
C_DOUT_WIDTH : INTEGER;
C_ENABLE_RLOCS : INTEGER;
C_FAMILY : STRING;
C_FULL_FLAGS_RST_VAL : INTEGER;
C_HAS_ALMOST_EMPTY : INTEGER;
C_HAS_ALMOST_FULL : INTEGER;
C_HAS_BACKUP : INTEGER;
C_HAS_DATA_COUNT : INTEGER;
C_HAS_INT_CLK : INTEGER;
C_HAS_MEMINIT_FILE : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_RD_DATA_COUNT : INTEGER;
C_HAS_RD_RST : INTEGER;
C_HAS_RST : INTEGER;
C_HAS_SRST : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_VALID : INTEGER;
C_HAS_WR_ACK : INTEGER;
C_HAS_WR_DATA_COUNT : INTEGER;
C_HAS_WR_RST : INTEGER;
C_IMPLEMENTATION_TYPE : INTEGER;
C_INIT_WR_PNTR_VAL : INTEGER;
C_MEMORY_TYPE : INTEGER;
C_MIF_FILE_NAME : STRING;
C_OPTIMIZATION_MODE : INTEGER;
C_OVERFLOW_LOW : INTEGER;
C_PRELOAD_LATENCY : INTEGER;
C_PRELOAD_REGS : INTEGER;
C_PRIM_FIFO_TYPE : STRING;
C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER;
C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER;
C_PROG_EMPTY_TYPE : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER;
C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER;
C_PROG_FULL_TYPE : INTEGER;
C_RD_DATA_COUNT_WIDTH : INTEGER;
C_RD_DEPTH : INTEGER;
C_RD_FREQ : INTEGER;
C_RD_PNTR_WIDTH : INTEGER;
C_UNDERFLOW_LOW : INTEGER;
C_USE_DOUT_RST : INTEGER;
C_USE_ECC : INTEGER;
C_USE_EMBEDDED_REG : INTEGER;
C_USE_PIPELINE_REG : INTEGER;
C_POWER_SAVING_MODE : INTEGER;
C_USE_FIFO16_FLAGS : INTEGER;
C_USE_FWFT_DATA_COUNT : INTEGER;
C_VALID_LOW : INTEGER;
C_WR_ACK_LOW : INTEGER;
C_WR_DATA_COUNT_WIDTH : INTEGER;
C_WR_DEPTH : INTEGER;
C_WR_FREQ : INTEGER;
C_WR_PNTR_WIDTH : INTEGER;
C_WR_RESPONSE_LATENCY : INTEGER;
C_MSGON_VAL : INTEGER;
C_ENABLE_RST_SYNC : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_ERROR_INJECTION_TYPE : INTEGER;
C_SYNCHRONIZER_STAGE : INTEGER;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_HAS_AXI_WR_CHANNEL : INTEGER;
C_HAS_AXI_RD_CHANNEL : INTEGER;
C_HAS_SLAVE_CE : INTEGER;
C_HAS_MASTER_CE : INTEGER;
C_ADD_NGC_CONSTRAINT : INTEGER;
C_USE_COMMON_OVERFLOW : INTEGER;
C_USE_COMMON_UNDERFLOW : INTEGER;
C_USE_DEFAULT_SETTINGS : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_AXI_ADDR_WIDTH : INTEGER;
C_AXI_DATA_WIDTH : INTEGER;
C_AXI_LEN_WIDTH : INTEGER;
C_AXI_LOCK_WIDTH : INTEGER;
C_HAS_AXI_ID : INTEGER;
C_HAS_AXI_AWUSER : INTEGER;
C_HAS_AXI_WUSER : INTEGER;
C_HAS_AXI_BUSER : INTEGER;
C_HAS_AXI_ARUSER : INTEGER;
C_HAS_AXI_RUSER : INTEGER;
C_AXI_ARUSER_WIDTH : INTEGER;
C_AXI_AWUSER_WIDTH : INTEGER;
C_AXI_WUSER_WIDTH : INTEGER;
C_AXI_BUSER_WIDTH : INTEGER;
C_AXI_RUSER_WIDTH : INTEGER;
C_HAS_AXIS_TDATA : INTEGER;
C_HAS_AXIS_TID : INTEGER;
C_HAS_AXIS_TDEST : INTEGER;
C_HAS_AXIS_TUSER : INTEGER;
C_HAS_AXIS_TREADY : INTEGER;
C_HAS_AXIS_TLAST : INTEGER;
C_HAS_AXIS_TSTRB : INTEGER;
C_HAS_AXIS_TKEEP : INTEGER;
C_AXIS_TDATA_WIDTH : INTEGER;
C_AXIS_TID_WIDTH : INTEGER;
C_AXIS_TDEST_WIDTH : INTEGER;
C_AXIS_TUSER_WIDTH : INTEGER;
C_AXIS_TSTRB_WIDTH : INTEGER;
C_AXIS_TKEEP_WIDTH : INTEGER;
C_WACH_TYPE : INTEGER;
C_WDCH_TYPE : INTEGER;
C_WRCH_TYPE : INTEGER;
C_RACH_TYPE : INTEGER;
C_RDCH_TYPE : INTEGER;
C_AXIS_TYPE : INTEGER;
C_IMPLEMENTATION_TYPE_WACH : INTEGER;
C_IMPLEMENTATION_TYPE_WDCH : INTEGER;
C_IMPLEMENTATION_TYPE_WRCH : INTEGER;
C_IMPLEMENTATION_TYPE_RACH : INTEGER;
C_IMPLEMENTATION_TYPE_RDCH : INTEGER;
C_IMPLEMENTATION_TYPE_AXIS : INTEGER;
C_APPLICATION_TYPE_WACH : INTEGER;
C_APPLICATION_TYPE_WDCH : INTEGER;
C_APPLICATION_TYPE_WRCH : INTEGER;
C_APPLICATION_TYPE_RACH : INTEGER;
C_APPLICATION_TYPE_RDCH : INTEGER;
C_APPLICATION_TYPE_AXIS : INTEGER;
C_PRIM_FIFO_TYPE_WACH : STRING;
C_PRIM_FIFO_TYPE_WDCH : STRING;
C_PRIM_FIFO_TYPE_WRCH : STRING;
C_PRIM_FIFO_TYPE_RACH : STRING;
C_PRIM_FIFO_TYPE_RDCH : STRING;
C_PRIM_FIFO_TYPE_AXIS : STRING;
C_USE_ECC_WACH : INTEGER;
C_USE_ECC_WDCH : INTEGER;
C_USE_ECC_WRCH : INTEGER;
C_USE_ECC_RACH : INTEGER;
C_USE_ECC_RDCH : INTEGER;
C_USE_ECC_AXIS : INTEGER;
C_ERROR_INJECTION_TYPE_WACH : INTEGER;
C_ERROR_INJECTION_TYPE_WDCH : INTEGER;
C_ERROR_INJECTION_TYPE_WRCH : INTEGER;
C_ERROR_INJECTION_TYPE_RACH : INTEGER;
C_ERROR_INJECTION_TYPE_RDCH : INTEGER;
C_ERROR_INJECTION_TYPE_AXIS : INTEGER;
C_DIN_WIDTH_WACH : INTEGER;
C_DIN_WIDTH_WDCH : INTEGER;
C_DIN_WIDTH_WRCH : INTEGER;
C_DIN_WIDTH_RACH : INTEGER;
C_DIN_WIDTH_RDCH : INTEGER;
C_DIN_WIDTH_AXIS : INTEGER;
C_WR_DEPTH_WACH : INTEGER;
C_WR_DEPTH_WDCH : INTEGER;
C_WR_DEPTH_WRCH : INTEGER;
C_WR_DEPTH_RACH : INTEGER;
C_WR_DEPTH_RDCH : INTEGER;
C_WR_DEPTH_AXIS : INTEGER;
C_WR_PNTR_WIDTH_WACH : INTEGER;
C_WR_PNTR_WIDTH_WDCH : INTEGER;
C_WR_PNTR_WIDTH_WRCH : INTEGER;
C_WR_PNTR_WIDTH_RACH : INTEGER;
C_WR_PNTR_WIDTH_RDCH : INTEGER;
C_WR_PNTR_WIDTH_AXIS : INTEGER;
C_HAS_DATA_COUNTS_WACH : INTEGER;
C_HAS_DATA_COUNTS_WDCH : INTEGER;
C_HAS_DATA_COUNTS_WRCH : INTEGER;
C_HAS_DATA_COUNTS_RACH : INTEGER;
C_HAS_DATA_COUNTS_RDCH : INTEGER;
C_HAS_DATA_COUNTS_AXIS : INTEGER;
C_HAS_PROG_FLAGS_WACH : INTEGER;
C_HAS_PROG_FLAGS_WDCH : INTEGER;
C_HAS_PROG_FLAGS_WRCH : INTEGER;
C_HAS_PROG_FLAGS_RACH : INTEGER;
C_HAS_PROG_FLAGS_RDCH : INTEGER;
C_HAS_PROG_FLAGS_AXIS : INTEGER;
C_PROG_FULL_TYPE_WACH : INTEGER;
C_PROG_FULL_TYPE_WDCH : INTEGER;
C_PROG_FULL_TYPE_WRCH : INTEGER;
C_PROG_FULL_TYPE_RACH : INTEGER;
C_PROG_FULL_TYPE_RDCH : INTEGER;
C_PROG_FULL_TYPE_AXIS : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_PROG_EMPTY_TYPE_WACH : INTEGER;
C_PROG_EMPTY_TYPE_WDCH : INTEGER;
C_PROG_EMPTY_TYPE_WRCH : INTEGER;
C_PROG_EMPTY_TYPE_RACH : INTEGER;
C_PROG_EMPTY_TYPE_RDCH : INTEGER;
C_PROG_EMPTY_TYPE_AXIS : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_REG_SLICE_MODE_WACH : INTEGER;
C_REG_SLICE_MODE_WDCH : INTEGER;
C_REG_SLICE_MODE_WRCH : INTEGER;
C_REG_SLICE_MODE_RACH : INTEGER;
C_REG_SLICE_MODE_RDCH : INTEGER;
C_REG_SLICE_MODE_AXIS : INTEGER
);
PORT (
backup : IN STD_LOGIC;
backup_marker : IN STD_LOGIC;
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
srst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh_assert : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh_negate : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
int_clk : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
injectsbiterr : IN STD_LOGIC;
sleep : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
wr_ack : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
wr_rst_busy : OUT STD_LOGIC;
rd_rst_busy : OUT STD_LOGIC;
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
m_aclk_en : IN STD_LOGIC;
s_aclk_en : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awvalid : OUT STD_LOGIC;
m_axi_awready : IN STD_LOGIC;
m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_wlast : OUT STD_LOGIC;
m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wvalid : OUT STD_LOGIC;
m_axi_wready : IN STD_LOGIC;
m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bvalid : IN STD_LOGIC;
m_axi_bready : OUT STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arvalid : OUT STD_LOGIC;
m_axi_arready : IN STD_LOGIC;
m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_rlast : IN STD_LOGIC;
m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rvalid : IN STD_LOGIC;
m_axi_rready : OUT STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tstrb : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_injectsbiterr : IN STD_LOGIC;
axi_aw_injectdbiterr : IN STD_LOGIC;
axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_sbiterr : OUT STD_LOGIC;
axi_aw_dbiterr : OUT STD_LOGIC;
axi_aw_overflow : OUT STD_LOGIC;
axi_aw_underflow : OUT STD_LOGIC;
axi_aw_prog_full : OUT STD_LOGIC;
axi_aw_prog_empty : OUT STD_LOGIC;
axi_w_injectsbiterr : IN STD_LOGIC;
axi_w_injectdbiterr : IN STD_LOGIC;
axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_sbiterr : OUT STD_LOGIC;
axi_w_dbiterr : OUT STD_LOGIC;
axi_w_overflow : OUT STD_LOGIC;
axi_w_underflow : OUT STD_LOGIC;
axi_w_prog_full : OUT STD_LOGIC;
axi_w_prog_empty : OUT STD_LOGIC;
axi_b_injectsbiterr : IN STD_LOGIC;
axi_b_injectdbiterr : IN STD_LOGIC;
axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_sbiterr : OUT STD_LOGIC;
axi_b_dbiterr : OUT STD_LOGIC;
axi_b_overflow : OUT STD_LOGIC;
axi_b_underflow : OUT STD_LOGIC;
axi_b_prog_full : OUT STD_LOGIC;
axi_b_prog_empty : OUT STD_LOGIC;
axi_ar_injectsbiterr : IN STD_LOGIC;
axi_ar_injectdbiterr : IN STD_LOGIC;
axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_sbiterr : OUT STD_LOGIC;
axi_ar_dbiterr : OUT STD_LOGIC;
axi_ar_overflow : OUT STD_LOGIC;
axi_ar_underflow : OUT STD_LOGIC;
axi_ar_prog_full : OUT STD_LOGIC;
axi_ar_prog_empty : OUT STD_LOGIC;
axi_r_injectsbiterr : IN STD_LOGIC;
axi_r_injectdbiterr : IN STD_LOGIC;
axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_sbiterr : OUT STD_LOGIC;
axi_r_dbiterr : OUT STD_LOGIC;
axi_r_overflow : OUT STD_LOGIC;
axi_r_underflow : OUT STD_LOGIC;
axi_r_prog_full : OUT STD_LOGIC;
axi_r_prog_empty : OUT STD_LOGIC;
axis_injectsbiterr : IN STD_LOGIC;
axis_injectdbiterr : IN STD_LOGIC;
axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_sbiterr : OUT STD_LOGIC;
axis_dbiterr : OUT STD_LOGIC;
axis_overflow : OUT STD_LOGIC;
axis_underflow : OUT STD_LOGIC;
axis_prog_full : OUT STD_LOGIC;
axis_prog_empty : OUT STD_LOGIC
);
END COMPONENT fifo_generator_v13_1_3;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF input_fifo_arch: ARCHITECTURE IS "fifo_generator_v13_1_3,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF input_fifo_arch : ARCHITECTURE IS "input_fifo,fifo_generator_v13_1_3,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF input_fifo_arch: ARCHITECTURE IS "input_fifo,fifo_generator_v13_1_3,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=13.1,x_ipCoreRevision=3,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_COMMON_CLOCK=1,C_SELECT_XPM=0,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=11,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=8,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=8,C_ENABLE_RLOCS=0,C_FAMILY=zynq,C_FULL_FLAGS_RST_VAL=0,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_HAS_MEMINIT_" &
"FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=0,C_HAS_SRST=1,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=0,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=1,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=0,C_PRELOAD_REGS=1,C_PRIM_FIFO_TYPE=1kx18,C_PROG_EMPTY_THRESH_ASSERT_VAL=4,C_PROG_EMPTY_THRESH_NEGATE_VAL=5,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=1023,C_PROG_FULL_THRESH_NE" &
"GATE_VAL=1022,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=11,C_RD_DEPTH=1024,C_RD_FREQ=1,C_RD_PNTR_WIDTH=10,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=1,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=11,C_WR_DEPTH=1024,C_WR_FREQ=1,C_WR_PNTR_WIDTH=10,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_EN_SAFETY_CKT=0,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE_TY" &
"PE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C" &
"_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATION_TYPE_RDCH" &
"=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERROR_I" &
"NJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=1,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_WR_" &
"PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1023,C_P" &
"ROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL" &
"_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 core_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF din: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA";
ATTRIBUTE X_INTERFACE_INFO OF wr_en: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN";
ATTRIBUTE X_INTERFACE_INFO OF rd_en: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN";
ATTRIBUTE X_INTERFACE_INFO OF dout: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA";
ATTRIBUTE X_INTERFACE_INFO OF full: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL";
ATTRIBUTE X_INTERFACE_INFO OF empty: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY";
BEGIN
U0 : fifo_generator_v13_1_3
GENERIC MAP (
C_COMMON_CLOCK => 1,
C_SELECT_XPM => 0,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => 11,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => 8,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => 8,
C_ENABLE_RLOCS => 0,
C_FAMILY => "zynq",
C_FULL_FLAGS_RST_VAL => 0,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => 0,
C_HAS_RD_DATA_COUNT => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 0,
C_HAS_SRST => 1,
C_HAS_UNDERFLOW => 0,
C_HAS_VALID => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_DATA_COUNT => 0,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => 0,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => 1,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => 0,
C_PRELOAD_REGS => 1,
C_PRIM_FIFO_TYPE => "1kx18",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 4,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 5,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 1023,
C_PROG_FULL_THRESH_NEGATE_VAL => 1022,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => 11,
C_RD_DEPTH => 1024,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => 10,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => 0,
C_USE_PIPELINE_REG => 0,
C_POWER_SAVING_MODE => 0,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 1,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => 11,
C_WR_DEPTH => 1024,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => 10,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_EN_SAFETY_CKT => 0,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => 2,
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_HAS_AXI_WR_CHANNEL => 1,
C_HAS_AXI_RD_CHANNEL => 1,
C_HAS_SLAVE_CE => 0,
C_HAS_MASTER_CE => 0,
C_ADD_NGC_CONSTRAINT => 0,
C_USE_COMMON_OVERFLOW => 0,
C_USE_COMMON_UNDERFLOW => 0,
C_USE_DEFAULT_SETTINGS => 0,
C_AXI_ID_WIDTH => 1,
C_AXI_ADDR_WIDTH => 32,
C_AXI_DATA_WIDTH => 64,
C_AXI_LEN_WIDTH => 8,
C_AXI_LOCK_WIDTH => 1,
C_HAS_AXI_ID => 0,
C_HAS_AXI_AWUSER => 0,
C_HAS_AXI_WUSER => 0,
C_HAS_AXI_BUSER => 0,
C_HAS_AXI_ARUSER => 0,
C_HAS_AXI_RUSER => 0,
C_AXI_ARUSER_WIDTH => 1,
C_AXI_AWUSER_WIDTH => 1,
C_AXI_WUSER_WIDTH => 1,
C_AXI_BUSER_WIDTH => 1,
C_AXI_RUSER_WIDTH => 1,
C_HAS_AXIS_TDATA => 1,
C_HAS_AXIS_TID => 0,
C_HAS_AXIS_TDEST => 0,
C_HAS_AXIS_TUSER => 1,
C_HAS_AXIS_TREADY => 1,
C_HAS_AXIS_TLAST => 0,
C_HAS_AXIS_TSTRB => 0,
C_HAS_AXIS_TKEEP => 0,
C_AXIS_TDATA_WIDTH => 8,
C_AXIS_TID_WIDTH => 1,
C_AXIS_TDEST_WIDTH => 1,
C_AXIS_TUSER_WIDTH => 4,
C_AXIS_TSTRB_WIDTH => 1,
C_AXIS_TKEEP_WIDTH => 1,
C_WACH_TYPE => 0,
C_WDCH_TYPE => 0,
C_WRCH_TYPE => 0,
C_RACH_TYPE => 0,
C_RDCH_TYPE => 0,
C_AXIS_TYPE => 0,
C_IMPLEMENTATION_TYPE_WACH => 1,
C_IMPLEMENTATION_TYPE_WDCH => 1,
C_IMPLEMENTATION_TYPE_WRCH => 1,
C_IMPLEMENTATION_TYPE_RACH => 1,
C_IMPLEMENTATION_TYPE_RDCH => 1,
C_IMPLEMENTATION_TYPE_AXIS => 1,
C_APPLICATION_TYPE_WACH => 0,
C_APPLICATION_TYPE_WDCH => 0,
C_APPLICATION_TYPE_WRCH => 0,
C_APPLICATION_TYPE_RACH => 0,
C_APPLICATION_TYPE_RDCH => 0,
C_APPLICATION_TYPE_AXIS => 0,
C_PRIM_FIFO_TYPE_WACH => "512x36",
C_PRIM_FIFO_TYPE_WDCH => "1kx36",
C_PRIM_FIFO_TYPE_WRCH => "512x36",
C_PRIM_FIFO_TYPE_RACH => "512x36",
C_PRIM_FIFO_TYPE_RDCH => "1kx36",
C_PRIM_FIFO_TYPE_AXIS => "1kx18",
C_USE_ECC_WACH => 0,
C_USE_ECC_WDCH => 0,
C_USE_ECC_WRCH => 0,
C_USE_ECC_RACH => 0,
C_USE_ECC_RDCH => 0,
C_USE_ECC_AXIS => 0,
C_ERROR_INJECTION_TYPE_WACH => 0,
C_ERROR_INJECTION_TYPE_WDCH => 0,
C_ERROR_INJECTION_TYPE_WRCH => 0,
C_ERROR_INJECTION_TYPE_RACH => 0,
C_ERROR_INJECTION_TYPE_RDCH => 0,
C_ERROR_INJECTION_TYPE_AXIS => 0,
C_DIN_WIDTH_WACH => 1,
C_DIN_WIDTH_WDCH => 64,
C_DIN_WIDTH_WRCH => 2,
C_DIN_WIDTH_RACH => 32,
C_DIN_WIDTH_RDCH => 64,
C_DIN_WIDTH_AXIS => 1,
C_WR_DEPTH_WACH => 16,
C_WR_DEPTH_WDCH => 1024,
C_WR_DEPTH_WRCH => 16,
C_WR_DEPTH_RACH => 16,
C_WR_DEPTH_RDCH => 1024,
C_WR_DEPTH_AXIS => 1024,
C_WR_PNTR_WIDTH_WACH => 4,
C_WR_PNTR_WIDTH_WDCH => 10,
C_WR_PNTR_WIDTH_WRCH => 4,
C_WR_PNTR_WIDTH_RACH => 4,
C_WR_PNTR_WIDTH_RDCH => 10,
C_WR_PNTR_WIDTH_AXIS => 10,
C_HAS_DATA_COUNTS_WACH => 0,
C_HAS_DATA_COUNTS_WDCH => 0,
C_HAS_DATA_COUNTS_WRCH => 0,
C_HAS_DATA_COUNTS_RACH => 0,
C_HAS_DATA_COUNTS_RDCH => 0,
C_HAS_DATA_COUNTS_AXIS => 0,
C_HAS_PROG_FLAGS_WACH => 0,
C_HAS_PROG_FLAGS_WDCH => 0,
C_HAS_PROG_FLAGS_WRCH => 0,
C_HAS_PROG_FLAGS_RACH => 0,
C_HAS_PROG_FLAGS_RDCH => 0,
C_HAS_PROG_FLAGS_AXIS => 0,
C_PROG_FULL_TYPE_WACH => 0,
C_PROG_FULL_TYPE_WDCH => 0,
C_PROG_FULL_TYPE_WRCH => 0,
C_PROG_FULL_TYPE_RACH => 0,
C_PROG_FULL_TYPE_RDCH => 0,
C_PROG_FULL_TYPE_AXIS => 0,
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023,
C_PROG_EMPTY_TYPE_WACH => 0,
C_PROG_EMPTY_TYPE_WDCH => 0,
C_PROG_EMPTY_TYPE_WRCH => 0,
C_PROG_EMPTY_TYPE_RACH => 0,
C_PROG_EMPTY_TYPE_RDCH => 0,
C_PROG_EMPTY_TYPE_AXIS => 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022,
C_REG_SLICE_MODE_WACH => 0,
C_REG_SLICE_MODE_WDCH => 0,
C_REG_SLICE_MODE_WRCH => 0,
C_REG_SLICE_MODE_RACH => 0,
C_REG_SLICE_MODE_RDCH => 0,
C_REG_SLICE_MODE_AXIS => 0
)
PORT MAP (
backup => '0',
backup_marker => '0',
clk => clk,
rst => '0',
srst => srst,
wr_clk => '0',
wr_rst => '0',
rd_clk => '0',
rd_rst => '0',
din => din,
wr_en => wr_en,
rd_en => rd_en,
prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
int_clk => '0',
injectdbiterr => '0',
injectsbiterr => '0',
sleep => '0',
dout => dout,
full => full,
empty => empty,
m_aclk => '0',
s_aclk => '0',
s_aresetn => '0',
m_aclk_en => '0',
s_aclk_en => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awvalid => '0',
s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wlast => '0',
s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wvalid => '0',
s_axi_bready => '0',
m_axi_awready => '0',
m_axi_wready => '0',
m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bvalid => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arvalid => '0',
s_axi_rready => '0',
m_axi_arready => '0',
m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_rlast => '0',
m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rvalid => '0',
s_axis_tvalid => '0',
s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tlast => '0',
s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
m_axis_tready => '0',
axi_aw_injectsbiterr => '0',
axi_aw_injectdbiterr => '0',
axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_w_injectsbiterr => '0',
axi_w_injectdbiterr => '0',
axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_b_injectsbiterr => '0',
axi_b_injectdbiterr => '0',
axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_injectsbiterr => '0',
axi_ar_injectdbiterr => '0',
axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_r_injectsbiterr => '0',
axi_r_injectdbiterr => '0',
axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_injectsbiterr => '0',
axis_injectdbiterr => '0',
axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10))
);
END input_fifo_arch;
|
unlicense
|
TWW12/lzw
|
final_project_sim/lzw/lzw.srcs/sources_1/ip/bram_1024_0/synth/bram_1024_0.vhd
|
4
|
14457
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_3_5;
USE blk_mem_gen_v8_3_5.blk_mem_gen_v8_3_5;
ENTITY bram_1024_0 IS
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(19 DOWNTO 0)
);
END bram_1024_0;
ARCHITECTURE bram_1024_0_arch OF bram_1024_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF bram_1024_0_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_3_5 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
rsta_busy : OUT STD_LOGIC;
rstb_busy : OUT STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_5;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF bram_1024_0_arch: ARCHITECTURE IS "blk_mem_gen_v8_3_5,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF bram_1024_0_arch : ARCHITECTURE IS "bram_1024_0,blk_mem_gen_v8_3_5,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF bram_1024_0_arch: ARCHITECTURE IS "bram_1024_0,blk_mem_gen_v8_3_5,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.3,x_ipCoreRevision=5,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=0,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=bram_1024_0.mi" &
"f,C_INIT_FILE=bram_1024_0.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=20,C_READ_WIDTH_A=20,C_WRITE_DEPTH_A=1024,C_READ_DEPTH_A=1024,C_ADDRA_WIDTH=10,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=20,C_READ_WIDTH_B=20,C_WRITE_DE" &
"PTH_B=1024,C_READ_DEPTH_B=1024,C_ADDRB_WIDTH=10,C_HAS_MEM_OUTPUT_REGS_A=1,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_EN_SAFETY_CKT=0,C_DISABLE" &
"_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=1,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 2.74095 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : blk_mem_gen_v8_3_5
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 0,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 1,
C_INIT_FILE_NAME => "bram_1024_0.mif",
C_INIT_FILE => "bram_1024_0.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 1,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 20,
C_READ_WIDTH_A => 20,
C_WRITE_DEPTH_A => 1024,
C_READ_DEPTH_A => 1024,
C_ADDRA_WIDTH => 10,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 20,
C_READ_WIDTH_B => 20,
C_WRITE_DEPTH_B => 1024,
C_READ_DEPTH_B => 1024,
C_ADDRB_WIDTH => 10,
C_HAS_MEM_OUTPUT_REGS_A => 1,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_EN_SAFETY_CKT => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "1",
C_COUNT_18K_BRAM => "0",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 2.74095 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => ena,
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => '0',
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 20)),
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 20)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END bram_1024_0_arch;
|
unlicense
|
TWW12/lzw
|
final_project/lzw_compression/lzw_compression.ipdefs/axi_compression_1.0_0_0/hdl/axi_compression_v1_0_S00_AXI.vhd
|
3
|
24405
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity axi_compression_v1_0_S00_AXI is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bus
C_S_AXI_ADDR_WIDTH : integer := 6
);
port (
-- Users to add ports here
-- User ports ends
-- Do not modify the ports beyond this line
-- Global Clock Signal
S_AXI_ACLK : in std_logic;
-- Global Reset Signal. This Signal is Active LOW
S_AXI_ARESETN : in std_logic;
-- Write address (issued by master, acceped by Slave)
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Write channel Protection type. This signal indicates the
-- privilege and security level of the transaction, and whether
-- the transaction is a data access or an instruction access.
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
-- Write address valid. This signal indicates that the master signaling
-- valid write address and control information.
S_AXI_AWVALID : in std_logic;
-- Write address ready. This signal indicates that the slave is ready
-- to accept an address and associated control signals.
S_AXI_AWREADY : out std_logic;
-- Write data (issued by master, acceped by Slave)
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Write strobes. This signal indicates which byte lanes hold
-- valid data. There is one write strobe bit for each eight
-- bits of the write data bus.
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
-- Write valid. This signal indicates that valid write
-- data and strobes are available.
S_AXI_WVALID : in std_logic;
-- Write ready. This signal indicates that the slave
-- can accept the write data.
S_AXI_WREADY : out std_logic;
-- Write response. This signal indicates the status
-- of the write transaction.
S_AXI_BRESP : out std_logic_vector(1 downto 0);
-- Write response valid. This signal indicates that the channel
-- is signaling a valid write response.
S_AXI_BVALID : out std_logic;
-- Response ready. This signal indicates that the master
-- can accept a write response.
S_AXI_BREADY : in std_logic;
-- Read address (issued by master, acceped by Slave)
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Protection type. This signal indicates the privilege
-- and security level of the transaction, and whether the
-- transaction is a data access or an instruction access.
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
-- Read address valid. This signal indicates that the channel
-- is signaling valid read address and control information.
S_AXI_ARVALID : in std_logic;
-- Read address ready. This signal indicates that the slave is
-- ready to accept an address and associated control signals.
S_AXI_ARREADY : out std_logic;
-- Read data (issued by slave)
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Read response. This signal indicates the status of the
-- read transfer.
S_AXI_RRESP : out std_logic_vector(1 downto 0);
-- Read valid. This signal indicates that the channel is
-- signaling the required read data.
S_AXI_RVALID : out std_logic;
-- Read ready. This signal indicates that the master can
-- accept the read data and response information.
S_AXI_RREADY : in std_logic
);
end axi_compression_v1_0_S00_AXI;
architecture arch_imp of axi_compression_v1_0_S00_AXI is
signal lzw_rst : std_logic;
signal input_fifo_wr_en : std_logic;
signal input_fifo_rd_en : std_logic;
signal input_fifo_output : std_logic_vector(7 downto 0);
signal input_fifo_full : std_logic_vector(31 downto 0);
signal input_fifo_empty : std_logic;
signal input_fifo_not_empty : std_logic;
signal input_fifo_wr_ack : std_logic_vector(31 downto 0);
signal output_fifo_rd_en : std_logic;
signal output_fifo_wr_en : std_logic;
signal output_fifo_din : std_logic_vector(11 downto 0);
signal output_fifo_dout : std_logic_vector(31 downto 0);
signal output_fifo_full : std_logic_vector(31 downto 0);
signal output_fifo_empty : std_logic_vector(31 downto 0);
signal output_fifo_valid : std_logic_vector(31 downto 0);
signal compression_done : std_logic_vector(31 downto 0);
signal clock_count : std_logic_vector(31 downto 0);
--Input FIFO for compression
COMPONENT input_fifo
PORT (
clk : IN STD_LOGIC;
srst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
wr_ack : OUT STD_LOGIC
);
END COMPONENT;
--Output FIFO for decompressed results
COMPONENT output_fifo
PORT (
clk : IN STD_LOGIC;
srst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT clock_counter
PORT (
enable : IN STD_LOGIC;
count : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
done : IN STD_LOGIC;
clk : IN STD_LOGIC;
rst : IN STD_LOGIC
);
END COMPONENT;
-- AXI4LITE signals
signal axi_awaddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_awready : std_logic;
signal axi_wready : std_logic;
signal axi_bresp : std_logic_vector(1 downto 0);
signal axi_bvalid : std_logic;
signal axi_araddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_arready : std_logic;
signal axi_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal axi_rresp : std_logic_vector(1 downto 0);
signal axi_rvalid : std_logic;
-- Example-specific design signals
-- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
-- ADDR_LSB is used for addressing 32/64 bit registers/memories
-- ADDR_LSB = 2 for 32 bits (n downto 2)
-- ADDR_LSB = 3 for 64 bits (n downto 3)
constant ADDR_LSB : integer := (C_S_AXI_DATA_WIDTH/32)+ 1;
constant OPT_MEM_ADDR_BITS : integer := 3;
------------------------------------------------
---- Signals for user logic register space example
--------------------------------------------------
---- Number of Slave Registers 12
signal slv_reg0 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg1 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg2 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg3 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg4 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg5 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg6 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg7 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg8 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg9 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg10 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg11 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg_rden : std_logic;
signal slv_reg_wren : std_logic;
signal reg_data_out :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal byte_index : integer;
begin
-- I/O Connections assignments
S_AXI_AWREADY <= axi_awready;
S_AXI_WREADY <= axi_wready;
S_AXI_BRESP <= axi_bresp;
S_AXI_BVALID <= axi_bvalid;
S_AXI_ARREADY <= axi_arready;
S_AXI_RDATA <= axi_rdata;
S_AXI_RRESP <= axi_rresp;
S_AXI_RVALID <= axi_rvalid;
-- Implement axi_awready generation
-- axi_awready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awready <= '0';
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- slave is ready to accept write address when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_awready <= '1';
else
axi_awready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_awaddr latching
-- This process is used to latch the address when both
-- S_AXI_AWVALID and S_AXI_WVALID are valid.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awaddr <= (others => '0');
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- Write Address latching
axi_awaddr <= S_AXI_AWADDR;
end if;
end if;
end if;
end process;
-- Implement axi_wready generation
-- axi_wready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_wready <= '0';
else
if (axi_wready = '0' and S_AXI_WVALID = '1' and S_AXI_AWVALID = '1') then
-- slave is ready to accept write data when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_wready <= '1';
else
axi_wready <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and write logic generation
-- The write data is accepted and written to memory mapped registers when
-- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
-- select byte enables of slave registers while writing.
-- These registers are cleared when reset (active low) is applied.
-- Slave register write enable is asserted when valid address and data are available
-- and the slave is ready to accept the write address and write data.
slv_reg_wren <= axi_wready and S_AXI_WVALID and axi_awready and S_AXI_AWVALID ;
process (S_AXI_ACLK)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
slv_reg0 <= (others => '0');
slv_reg1 <= (others => '0');
slv_reg2 <= (others => '0');
slv_reg3 <= (others => '0');
slv_reg4 <= (others => '0');
slv_reg5 <= (others => '0');
slv_reg6 <= (others => '0');
slv_reg7 <= (others => '0');
slv_reg8 <= (others => '0');
slv_reg9 <= (others => '0');
slv_reg10 <= (others => '0');
slv_reg11 <= (others => '0');
input_fifo_wr_en <= '0';
output_fifo_rd_en <= '0';
else
input_fifo_wr_en <= '0';
output_fifo_rd_en <= '0';
loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
if (slv_reg_wren = '1') then
case loc_addr is
when b"0000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
input_fifo_wr_en <= '1';
-- Respective byte enables are asserted as per write strobes
-- slave registor 0
slv_reg0(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"0001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 1
slv_reg1(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"0010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 2
slv_reg2(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"0011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 3
slv_reg3(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"0100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
output_fifo_rd_en <= '1';
-- Respective byte enables are asserted as per write strobes
-- slave registor 4
slv_reg4(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"0101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 5
slv_reg5(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"0110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 6
slv_reg6(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"0111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 7
slv_reg7(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"1000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 8
slv_reg8(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"1001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 9
slv_reg9(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"1010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 10
slv_reg10(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"1011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 11
slv_reg11(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when others =>
slv_reg0 <= slv_reg0;
slv_reg1 <= slv_reg1;
slv_reg2 <= slv_reg2;
slv_reg3 <= slv_reg3;
slv_reg4 <= slv_reg4;
slv_reg5 <= slv_reg5;
slv_reg6 <= slv_reg6;
slv_reg7 <= slv_reg7;
slv_reg8 <= slv_reg8;
slv_reg9 <= slv_reg9;
slv_reg10 <= slv_reg10;
slv_reg11 <= slv_reg11;
end case;
end if;
end if;
end if;
end process;
-- Implement write response logic generation
-- The write response and response valid signals are asserted by the slave
-- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
-- This marks the acceptance of address and indicates the status of
-- write transaction.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_bvalid <= '0';
axi_bresp <= "00"; --need to work more on the responses
else
if (axi_awready = '1' and S_AXI_AWVALID = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0' ) then
axi_bvalid <= '1';
axi_bresp <= "00";
elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high)
axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high)
end if;
end if;
end if;
end process;
-- Implement axi_arready generation
-- axi_arready is asserted for one S_AXI_ACLK clock cycle when
-- S_AXI_ARVALID is asserted. axi_awready is
-- de-asserted when reset (active low) is asserted.
-- The read address is also latched when S_AXI_ARVALID is
-- asserted. axi_araddr is reset to zero on reset assertion.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_arready <= '0';
axi_araddr <= (others => '1');
else
if (axi_arready = '0' and S_AXI_ARVALID = '1') then
-- indicates that the slave has acceped the valid read address
axi_arready <= '1';
-- Read Address latching
axi_araddr <= S_AXI_ARADDR;
else
axi_arready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_arvalid generation
-- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_ARVALID and axi_arready are asserted. The slave registers
-- data are available on the axi_rdata bus at this instance. The
-- assertion of axi_rvalid marks the validity of read data on the
-- bus and axi_rresp indicates the status of read transaction.axi_rvalid
-- is deasserted on reset (active low). axi_rresp and axi_rdata are
-- cleared to zero on reset (active low).
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_rvalid <= '0';
axi_rresp <= "00";
else
if (axi_arready = '1' and S_AXI_ARVALID = '1' and axi_rvalid = '0') then
-- Valid read data is available at the read data bus
axi_rvalid <= '1';
axi_rresp <= "00"; -- 'OKAY' response
elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then
-- Read data is accepted by the master
axi_rvalid <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and read logic generation
-- Slave register read enable is asserted when valid address is available
-- and the slave is ready to accept the read address.
slv_reg_rden <= axi_arready and S_AXI_ARVALID and (not axi_rvalid) ;
process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, slv_reg8, slv_reg9, slv_reg10, slv_reg11, axi_araddr, S_AXI_ARESETN, slv_reg_rden)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
-- Address decoding for reading registers
loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
case loc_addr is
when b"0000" =>
reg_data_out <= slv_reg0;
when b"0001" =>
reg_data_out <= slv_reg1;
when b"0010" =>
reg_data_out <= input_fifo_full;
when b"0011" =>
reg_data_out <= slv_reg3;
when b"0100" =>
reg_data_out <= slv_reg4;
when b"0101" =>
reg_data_out <= output_fifo_dout;
when b"0110" =>
reg_data_out <= output_fifo_full;
when b"0111" =>
reg_data_out <= output_fifo_empty;
when b"1000" =>
reg_data_out <= compression_done;
when b"1001" =>
reg_data_out <= input_fifo_wr_ack;
when b"1010" =>
reg_data_out <= output_fifo_valid;
when b"1011" =>
reg_data_out <= clock_count;
when others =>
reg_data_out <= (others => '0');
end case;
end process;
-- Output register or memory read data
process( S_AXI_ACLK ) is
begin
if (rising_edge (S_AXI_ACLK)) then
if ( S_AXI_ARESETN = '0' ) then
axi_rdata <= (others => '0');
else
if (slv_reg_rden = '1') then
-- When there is a valid read address (S_AXI_ARVALID) with
-- acceptance of read address by the slave (axi_arready),
-- output the read dada
-- Read address mux
axi_rdata <= reg_data_out; -- register read data
end if;
end if;
end if;
end process;
-- Add user logic here
lzw_rst <= NOT(S_AXI_ARESETN);
fifo0 : input_fifo
port map(
clk => S_AXI_ACLK,
srst => lzw_rst,
din => slv_reg1(7 downto 0),
wr_en => input_fifo_wr_en,
rd_en => input_fifo_rd_en,
dout => input_fifo_output,
full => input_fifo_full(0),
empty => input_fifo_empty,
wr_ack => input_fifo_wr_ack(0)
);
fifo1 : output_fifo
port map(
clk => S_AXI_ACLK,
srst => lzw_rst,
din => output_fifo_din,
wr_en => output_fifo_wr_en,
rd_en => output_fifo_rd_en,
dout => output_fifo_dout(11 downto 0),
full => output_fifo_full(0),
empty => output_fifo_empty(0),
valid => output_fifo_valid(0)
);
input_fifo_not_empty <= NOT(input_fifo_empty);
compression : entity work.lzw
generic map( num_blocks => 4)
port map(
clk => S_AXI_ACLK,
rst => lzw_rst,
char_in => input_fifo_output,
input_valid => input_fifo_not_empty,
file_size => slv_reg3(15 downto 0),
input_rd => input_fifo_rd_en,
prefix_out => output_fifo_din,
output_valid => output_fifo_wr_en,
done => compression_done(0)
);
clk_count : clock_counter
port map(
enable => input_fifo_not_empty,
count => clock_count,
done => compression_done(0),
clk => S_AXI_ACLK,
rst => lzw_rst
);
-- User logic ends
end arch_imp;
|
unlicense
|
TWW12/lzw
|
ip_repo/axi_compression_1.0/hdl/axi_compression_v1_0_S00_AXI.vhd
|
3
|
24405
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity axi_compression_v1_0_S00_AXI is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bus
C_S_AXI_ADDR_WIDTH : integer := 6
);
port (
-- Users to add ports here
-- User ports ends
-- Do not modify the ports beyond this line
-- Global Clock Signal
S_AXI_ACLK : in std_logic;
-- Global Reset Signal. This Signal is Active LOW
S_AXI_ARESETN : in std_logic;
-- Write address (issued by master, acceped by Slave)
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Write channel Protection type. This signal indicates the
-- privilege and security level of the transaction, and whether
-- the transaction is a data access or an instruction access.
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
-- Write address valid. This signal indicates that the master signaling
-- valid write address and control information.
S_AXI_AWVALID : in std_logic;
-- Write address ready. This signal indicates that the slave is ready
-- to accept an address and associated control signals.
S_AXI_AWREADY : out std_logic;
-- Write data (issued by master, acceped by Slave)
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Write strobes. This signal indicates which byte lanes hold
-- valid data. There is one write strobe bit for each eight
-- bits of the write data bus.
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
-- Write valid. This signal indicates that valid write
-- data and strobes are available.
S_AXI_WVALID : in std_logic;
-- Write ready. This signal indicates that the slave
-- can accept the write data.
S_AXI_WREADY : out std_logic;
-- Write response. This signal indicates the status
-- of the write transaction.
S_AXI_BRESP : out std_logic_vector(1 downto 0);
-- Write response valid. This signal indicates that the channel
-- is signaling a valid write response.
S_AXI_BVALID : out std_logic;
-- Response ready. This signal indicates that the master
-- can accept a write response.
S_AXI_BREADY : in std_logic;
-- Read address (issued by master, acceped by Slave)
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Protection type. This signal indicates the privilege
-- and security level of the transaction, and whether the
-- transaction is a data access or an instruction access.
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
-- Read address valid. This signal indicates that the channel
-- is signaling valid read address and control information.
S_AXI_ARVALID : in std_logic;
-- Read address ready. This signal indicates that the slave is
-- ready to accept an address and associated control signals.
S_AXI_ARREADY : out std_logic;
-- Read data (issued by slave)
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Read response. This signal indicates the status of the
-- read transfer.
S_AXI_RRESP : out std_logic_vector(1 downto 0);
-- Read valid. This signal indicates that the channel is
-- signaling the required read data.
S_AXI_RVALID : out std_logic;
-- Read ready. This signal indicates that the master can
-- accept the read data and response information.
S_AXI_RREADY : in std_logic
);
end axi_compression_v1_0_S00_AXI;
architecture arch_imp of axi_compression_v1_0_S00_AXI is
signal lzw_rst : std_logic;
signal input_fifo_wr_en : std_logic;
signal input_fifo_rd_en : std_logic;
signal input_fifo_output : std_logic_vector(7 downto 0);
signal input_fifo_full : std_logic_vector(31 downto 0);
signal input_fifo_empty : std_logic;
signal input_fifo_not_empty : std_logic;
signal input_fifo_wr_ack : std_logic_vector(31 downto 0);
signal output_fifo_rd_en : std_logic;
signal output_fifo_wr_en : std_logic;
signal output_fifo_din : std_logic_vector(11 downto 0);
signal output_fifo_dout : std_logic_vector(31 downto 0);
signal output_fifo_full : std_logic_vector(31 downto 0);
signal output_fifo_empty : std_logic_vector(31 downto 0);
signal output_fifo_valid : std_logic_vector(31 downto 0);
signal compression_done : std_logic_vector(31 downto 0);
signal clock_count : std_logic_vector(31 downto 0);
--Input FIFO for compression
COMPONENT input_fifo
PORT (
clk : IN STD_LOGIC;
srst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
wr_ack : OUT STD_LOGIC
);
END COMPONENT;
--Output FIFO for decompressed results
COMPONENT output_fifo
PORT (
clk : IN STD_LOGIC;
srst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT clock_counter
PORT (
enable : IN STD_LOGIC;
count : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
done : IN STD_LOGIC;
clk : IN STD_LOGIC;
rst : IN STD_LOGIC
);
END COMPONENT;
-- AXI4LITE signals
signal axi_awaddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_awready : std_logic;
signal axi_wready : std_logic;
signal axi_bresp : std_logic_vector(1 downto 0);
signal axi_bvalid : std_logic;
signal axi_araddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_arready : std_logic;
signal axi_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal axi_rresp : std_logic_vector(1 downto 0);
signal axi_rvalid : std_logic;
-- Example-specific design signals
-- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
-- ADDR_LSB is used for addressing 32/64 bit registers/memories
-- ADDR_LSB = 2 for 32 bits (n downto 2)
-- ADDR_LSB = 3 for 64 bits (n downto 3)
constant ADDR_LSB : integer := (C_S_AXI_DATA_WIDTH/32)+ 1;
constant OPT_MEM_ADDR_BITS : integer := 3;
------------------------------------------------
---- Signals for user logic register space example
--------------------------------------------------
---- Number of Slave Registers 12
signal slv_reg0 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg1 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg2 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg3 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg4 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg5 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg6 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg7 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg8 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg9 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg10 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg11 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg_rden : std_logic;
signal slv_reg_wren : std_logic;
signal reg_data_out :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal byte_index : integer;
begin
-- I/O Connections assignments
S_AXI_AWREADY <= axi_awready;
S_AXI_WREADY <= axi_wready;
S_AXI_BRESP <= axi_bresp;
S_AXI_BVALID <= axi_bvalid;
S_AXI_ARREADY <= axi_arready;
S_AXI_RDATA <= axi_rdata;
S_AXI_RRESP <= axi_rresp;
S_AXI_RVALID <= axi_rvalid;
-- Implement axi_awready generation
-- axi_awready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awready <= '0';
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- slave is ready to accept write address when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_awready <= '1';
else
axi_awready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_awaddr latching
-- This process is used to latch the address when both
-- S_AXI_AWVALID and S_AXI_WVALID are valid.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awaddr <= (others => '0');
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- Write Address latching
axi_awaddr <= S_AXI_AWADDR;
end if;
end if;
end if;
end process;
-- Implement axi_wready generation
-- axi_wready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_wready <= '0';
else
if (axi_wready = '0' and S_AXI_WVALID = '1' and S_AXI_AWVALID = '1') then
-- slave is ready to accept write data when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_wready <= '1';
else
axi_wready <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and write logic generation
-- The write data is accepted and written to memory mapped registers when
-- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
-- select byte enables of slave registers while writing.
-- These registers are cleared when reset (active low) is applied.
-- Slave register write enable is asserted when valid address and data are available
-- and the slave is ready to accept the write address and write data.
slv_reg_wren <= axi_wready and S_AXI_WVALID and axi_awready and S_AXI_AWVALID ;
process (S_AXI_ACLK)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
slv_reg0 <= (others => '0');
slv_reg1 <= (others => '0');
slv_reg2 <= (others => '0');
slv_reg3 <= (others => '0');
slv_reg4 <= (others => '0');
slv_reg5 <= (others => '0');
slv_reg6 <= (others => '0');
slv_reg7 <= (others => '0');
slv_reg8 <= (others => '0');
slv_reg9 <= (others => '0');
slv_reg10 <= (others => '0');
slv_reg11 <= (others => '0');
input_fifo_wr_en <= '0';
output_fifo_rd_en <= '0';
else
input_fifo_wr_en <= '0';
output_fifo_rd_en <= '0';
loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
if (slv_reg_wren = '1') then
case loc_addr is
when b"0000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
input_fifo_wr_en <= '1';
-- Respective byte enables are asserted as per write strobes
-- slave registor 0
slv_reg0(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"0001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 1
slv_reg1(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"0010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 2
slv_reg2(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"0011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 3
slv_reg3(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"0100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
output_fifo_rd_en <= '1';
-- Respective byte enables are asserted as per write strobes
-- slave registor 4
slv_reg4(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"0101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 5
slv_reg5(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"0110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 6
slv_reg6(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"0111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 7
slv_reg7(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"1000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 8
slv_reg8(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"1001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 9
slv_reg9(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"1010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 10
slv_reg10(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"1011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 11
slv_reg11(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when others =>
slv_reg0 <= slv_reg0;
slv_reg1 <= slv_reg1;
slv_reg2 <= slv_reg2;
slv_reg3 <= slv_reg3;
slv_reg4 <= slv_reg4;
slv_reg5 <= slv_reg5;
slv_reg6 <= slv_reg6;
slv_reg7 <= slv_reg7;
slv_reg8 <= slv_reg8;
slv_reg9 <= slv_reg9;
slv_reg10 <= slv_reg10;
slv_reg11 <= slv_reg11;
end case;
end if;
end if;
end if;
end process;
-- Implement write response logic generation
-- The write response and response valid signals are asserted by the slave
-- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
-- This marks the acceptance of address and indicates the status of
-- write transaction.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_bvalid <= '0';
axi_bresp <= "00"; --need to work more on the responses
else
if (axi_awready = '1' and S_AXI_AWVALID = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0' ) then
axi_bvalid <= '1';
axi_bresp <= "00";
elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high)
axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high)
end if;
end if;
end if;
end process;
-- Implement axi_arready generation
-- axi_arready is asserted for one S_AXI_ACLK clock cycle when
-- S_AXI_ARVALID is asserted. axi_awready is
-- de-asserted when reset (active low) is asserted.
-- The read address is also latched when S_AXI_ARVALID is
-- asserted. axi_araddr is reset to zero on reset assertion.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_arready <= '0';
axi_araddr <= (others => '1');
else
if (axi_arready = '0' and S_AXI_ARVALID = '1') then
-- indicates that the slave has acceped the valid read address
axi_arready <= '1';
-- Read Address latching
axi_araddr <= S_AXI_ARADDR;
else
axi_arready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_arvalid generation
-- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_ARVALID and axi_arready are asserted. The slave registers
-- data are available on the axi_rdata bus at this instance. The
-- assertion of axi_rvalid marks the validity of read data on the
-- bus and axi_rresp indicates the status of read transaction.axi_rvalid
-- is deasserted on reset (active low). axi_rresp and axi_rdata are
-- cleared to zero on reset (active low).
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_rvalid <= '0';
axi_rresp <= "00";
else
if (axi_arready = '1' and S_AXI_ARVALID = '1' and axi_rvalid = '0') then
-- Valid read data is available at the read data bus
axi_rvalid <= '1';
axi_rresp <= "00"; -- 'OKAY' response
elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then
-- Read data is accepted by the master
axi_rvalid <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and read logic generation
-- Slave register read enable is asserted when valid address is available
-- and the slave is ready to accept the read address.
slv_reg_rden <= axi_arready and S_AXI_ARVALID and (not axi_rvalid) ;
process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, slv_reg8, slv_reg9, slv_reg10, slv_reg11, axi_araddr, S_AXI_ARESETN, slv_reg_rden)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
-- Address decoding for reading registers
loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
case loc_addr is
when b"0000" =>
reg_data_out <= slv_reg0;
when b"0001" =>
reg_data_out <= slv_reg1;
when b"0010" =>
reg_data_out <= input_fifo_full;
when b"0011" =>
reg_data_out <= slv_reg3;
when b"0100" =>
reg_data_out <= slv_reg4;
when b"0101" =>
reg_data_out <= output_fifo_dout;
when b"0110" =>
reg_data_out <= output_fifo_full;
when b"0111" =>
reg_data_out <= output_fifo_empty;
when b"1000" =>
reg_data_out <= compression_done;
when b"1001" =>
reg_data_out <= input_fifo_wr_ack;
when b"1010" =>
reg_data_out <= output_fifo_valid;
when b"1011" =>
reg_data_out <= clock_count;
when others =>
reg_data_out <= (others => '0');
end case;
end process;
-- Output register or memory read data
process( S_AXI_ACLK ) is
begin
if (rising_edge (S_AXI_ACLK)) then
if ( S_AXI_ARESETN = '0' ) then
axi_rdata <= (others => '0');
else
if (slv_reg_rden = '1') then
-- When there is a valid read address (S_AXI_ARVALID) with
-- acceptance of read address by the slave (axi_arready),
-- output the read dada
-- Read address mux
axi_rdata <= reg_data_out; -- register read data
end if;
end if;
end if;
end process;
-- Add user logic here
lzw_rst <= NOT(S_AXI_ARESETN);
fifo0 : input_fifo
port map(
clk => S_AXI_ACLK,
srst => lzw_rst,
din => slv_reg1(7 downto 0),
wr_en => input_fifo_wr_en,
rd_en => input_fifo_rd_en,
dout => input_fifo_output,
full => input_fifo_full(0),
empty => input_fifo_empty,
wr_ack => input_fifo_wr_ack(0)
);
fifo1 : output_fifo
port map(
clk => S_AXI_ACLK,
srst => lzw_rst,
din => output_fifo_din,
wr_en => output_fifo_wr_en,
rd_en => output_fifo_rd_en,
dout => output_fifo_dout(11 downto 0),
full => output_fifo_full(0),
empty => output_fifo_empty(0),
valid => output_fifo_valid(0)
);
input_fifo_not_empty <= NOT(input_fifo_empty);
compression : entity work.lzw
generic map( num_blocks => 4)
port map(
clk => S_AXI_ACLK,
rst => lzw_rst,
char_in => input_fifo_output,
input_valid => input_fifo_not_empty,
file_size => slv_reg3(15 downto 0),
input_rd => input_fifo_rd_en,
prefix_out => output_fifo_din,
output_valid => output_fifo_wr_en,
done => compression_done(0)
);
clk_count : clock_counter
port map(
enable => input_fifo_not_empty,
count => clock_count,
done => compression_done(0),
clk => S_AXI_ACLK,
rst => lzw_rst
);
-- User logic ends
end arch_imp;
|
unlicense
|
TWW12/lzw
|
final_project_sim/lzw/lzw.cache/ip/9495202d6046313a/bram_2048_1_stub.vhdl
|
1
|
1613
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Tue Apr 18 23:15:16 2017
-- Host : DESKTOP-I9J3TQJ running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ bram_2048_1_stub.vhdl
-- Design : bram_2048_1
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
clka : in STD_LOGIC;
ena : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 10 downto 0 );
dina : in STD_LOGIC_VECTOR ( 19 downto 0 );
douta : out STD_LOGIC_VECTOR ( 19 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clka,ena,wea[0:0],addra[10:0],dina[19:0],douta[19:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "blk_mem_gen_v8_3_5,Vivado 2016.4";
begin
end;
|
unlicense
|
sahandKashani/TRDB_D5M
|
DE1-SoC/hw/hdl/i2c/hdl/i2c_interface.vhd
|
5
|
11176
|
------------------------------------------------------------------
-- i2c_interface.vhd -- I2C Master Interface for
-- Avalon Bus Slave Interface
------------------------------------------------------------------
-- Author : Cédric Gaudin
-- Version : 0.8 alpha
-- History :
-- 20-mar-2002 CG 0.1 initial alpha release
-- 20-mar-2002 CG 0.2 minor corrections
-- 27-mar-2002 CG 0.6 interface is working yet
-- 02-apr-2002 CG 0.7 minor corrections
-- 09-05 -2006 RB 0.8 synchronise scl_in and sda_in with rising_edge of clk
------------------------------------------------------------------
-- Registers description:
--
-- Adr RW Name
-- 00 RW DR - transmit and receive data register
-- 01 RW CR - control register (changed to RW mode)
-- 10 RO SR - status register
-- 11 RW CD - clock divisor
--
-- SR - status register bits
--
-- +---------+-------+-------+-------+-------+
-- |bit 7..5 | bit 3 | bit 2 | bit 1 | bit 0 |
-- +---------+-------+-------+-------+-------+
-- | UNUSED | TIP | IPE | BSY | LAR |
-- +---------+-------+-------+-------+-------+
--
-- TIP - transfer in progress
-- IPE - interrupt pending
-- BSY - I2C bus busy
-- LAR - last acknowledge received
--
-- CR - control register bits
--
-- +---------+-------+-------+-------+-------+-------+-------+
-- | bit 7..6| bit 5 | bit 4 | bit 3 | bit 2 | bit 1 | bit 0 |
-- +---------+-------+-------+-------+-------+-------+-------+
-- | UNUSED | IEN | WR | RD | STA | STP | ACK |
-- +---------+-------+-------+-------+-------+-------+-------+
--
-- ACK - Acknowledge bit for reading
-- STP - Generate a I2C Stop Sequence
-- STA - Generate a I2C Start Sequence
-- RD - Read command bit
-- WR - Write command bit
-- IEN - Interrupt Enable
--
-- To start a transfer WR or RD *MUST* BE set.
-- When command transfer has started TIP goes high
-- and write to CR are ignored until TIP goes low.
-- At end of transfer IRQ goes high if interrupt is enabled (IEN=1).
--
------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity i2c_interface is
port(
clk : in std_logic;
reset : in std_logic;
-- Avalon bus signals
address : in std_logic_vector(1 downto 0);
chipselect : in std_logic;
write : in std_logic;
writedata : in std_logic_vector(7 downto 0);
read : in std_logic;
readdata : out std_logic_vector(7 downto 0);
irq : out std_logic;
-- I2C signals
scl : inout std_logic;
sda : inout std_logic
);
end i2c_interface;
architecture structural of i2c_interface is
component i2c_core
port(
-- I2C signals
sda_in : in std_logic;
scl_in : in std_logic;
sda_out : out std_logic;
scl_out : out std_logic;
-- interface signals
clk : in std_logic;
rst : in std_logic;
sclk : in std_logic;
ack_in : in std_logic;
ack_out : out std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
cmd_start : in std_logic;
cmd_stop : in std_logic;
cmd_read : in std_logic;
cmd_write : in std_logic;
cmd_done_ack : in std_logic;
cmd_done : out std_logic;
busy : out std_logic
-- debug signals
--state : out std_logic_vector(5 downto 0)
);
end component;
component i2c_clkgen
port(
signal clk : in std_logic;
signal rst : in std_logic;
signal clk_cnt : in std_logic_vector(7 downto 0);
-- I2C clock generated
signal sclk : out std_logic;
-- I2C clock line SCL (used for clock stretching)
signal scl_in : in std_logic;
signal scl_out : in std_logic
);
end component;
-- I2C base clock
signal i_sclk : std_logic;
-- I2C serial clock output
signal i_scl_out : std_logic;
-- clock divisor register
signal i_clkdiv_reg : std_logic_vector(7 downto 0);
-- status register bits
signal i_tip_reg : std_logic; -- transfer in progress ( bit 3 )
signal i_int_pe_reg : std_logic; -- interrupt pending ( bit 2 )
signal i_busy_reg : std_logic; -- busy ( bit 1 )
signal i_lar_reg : std_logic; -- last acknowledge received ( bit 0 )
-- control register bits
signal i_int_en_reg : std_logic; -- interrupt enable ( bit 5 )
signal i_write_reg : std_logic; -- write command ( bit 4 )
signal i_read_reg : std_logic; -- read command ( bit 3 )
signal i_start_reg : std_logic; -- command with a start ( bit 2 )
signal i_stop_reg : std_logic; -- command with a stop ( bit 1 )
signal i_ack_reg : std_logic; -- acknowledge to send ( bit 0 )
-- data register
signal i_data_out : std_logic_vector(7 downto 0);
signal i_data_in : std_logic_vector(7 downto 0);
-- command done & acknowledge signals
signal i_cmd_done_ack : std_logic;
signal i_cmd_done : std_logic;
-- internal signals
signal i_readdata : std_logic_vector(7 downto 0);
signal i_irq : std_logic;
-- write strobe
signal i_write_strobe : std_logic;
-- read strobe
signal i_read_strobe : std_logic;
-- interrupt clear
signal i_int_clr : std_logic;
-- just implement open collector in module
signal scl_in : std_logic;
signal sda_in : std_logic;
signal scl_out : std_logic;
signal sda_out : std_logic;
begin
scl_in <= scl when rising_edge(clk); -- RB 0.8
sda_in <= sda when rising_edge(clk); -- RB 0.8
--scl <= 'Z' when (scl_out = '1') else '0';
scl <= '1' when (scl_out = '1') else '0'; -- RB 0.8 to have nice scl ( no more open collector !! )
sda <= 'Z' when (sda_out = '1') else '0';
clkgen : i2c_clkgen port map(
clk => clk,
rst => reset,
clk_cnt => i_clkdiv_reg,
sclk => i_sclk,
scl_in => scl_in,
scl_out => i_scl_out
);
core : i2c_core port map(
clk => clk,
rst => reset,
sclk => i_sclk,
ack_in => i_ack_reg,
ack_out => i_lar_reg,
data_in => i_data_in,
data_out => i_data_out,
cmd_start => i_start_reg,
cmd_stop => i_stop_reg,
cmd_read => i_read_reg,
cmd_write => i_write_reg,
cmd_done_ack => i_cmd_done_ack,
cmd_done => i_cmd_done,
busy => i_busy_reg,
sda_in => sda_in,
scl_in => scl_in,
sda_out => sda_out,
scl_out => i_scl_out
-- state => state
);
-- read strobe
i_read_strobe <= (chipselect and read);
-- output to avalon bus
data_out_sync : process(clk, reset)
begin
if (reset = '1') then
readdata <= (others => '0');
irq <= '0';
elsif (rising_edge(clk)) then
if (i_read_strobe = '1') then
readdata <= i_readdata;
end if;
irq <= i_irq;
end if;
end process;
-- output multiplexer
data_out_comb : process(address, i_ack_reg, i_stop_reg, i_start_reg, i_read_reg, i_write_reg, i_int_en_reg, i_data_out, i_lar_reg, i_busy_reg, i_int_pe_reg, i_tip_reg, i_clkdiv_reg)
begin
i_readdata <= (others => '0');
case address is
when "00" => i_readdata <= i_data_out;
when "01" =>
i_readdata(0) <= i_ack_reg;
i_readdata(1) <= i_stop_reg;
i_readdata(2) <= i_start_reg;
i_readdata(3) <= i_read_reg;
i_readdata(4) <= i_write_reg;
i_readdata(5) <= i_int_en_reg;
when "10" => i_readdata(0) <= i_lar_reg;
i_readdata(1) <= i_busy_reg;
i_readdata(2) <= i_int_pe_reg;
i_readdata(3) <= i_tip_reg;
when "11" => i_readdata <= i_clkdiv_reg;
when others => i_readdata <= (others => '0');
end case;
end process;
-- output scl already syncronized in core
scl_out <= i_scl_out;
-- transfer in progress
i_tip_reg <= (i_read_reg OR i_write_reg);
-- write strobe
i_write_strobe <= (chipselect and write);
-- interrupt output
i_irq <= (i_int_pe_reg AND i_int_en_reg);
-- interrupt clear signal coming from outside
i_int_clr <= '1' when (address = "00" and chipselect = '1') else '0';
data_in_sync : process(clk, reset)
begin
if (reset = '1') then
i_int_pe_reg <= '0';
i_data_in <= (others => '0');
i_int_en_reg <= '0';
i_write_reg <= '0';
i_read_reg <= '0';
i_start_reg <= '0';
i_stop_reg <= '0';
i_ack_reg <= '0';
i_clkdiv_reg <= "10000011";
i_cmd_done_ack <= '0';
elsif (rising_edge(clk)) then
i_cmd_done_ack <= '0';
-- no transfer in progress
if (i_tip_reg = '0') then
if (i_write_strobe = '1') then
case address is
when "00" => i_data_in <= writedata;
when "01" => i_ack_reg <= writedata(0);
i_stop_reg <= writedata(1);
i_start_reg <= writedata(2);
i_read_reg <= writedata(3);
i_write_reg <= writedata(4);
i_int_en_reg <= writedata(5);
when "11" => i_clkdiv_reg <= writedata;
when others => null;
end case;
end if;
if (i_int_clr = '1') then
i_int_pe_reg <= '0';
end if;
else
if (i_cmd_done = '1') then
-- clear command bits
i_write_reg <= '0';
i_read_reg <= '0';
i_start_reg <= '0';
i_stop_reg <= '0';
-- set interrupt pending
i_int_pe_reg <= '1';
-- acknowledge cmd done to core controller
i_cmd_done_ack <= '1';
end if;
end if;
end if;
end process data_in_sync;
end structural;
|
unlicense
|
ricardo-jasinski/vhdl-game-engine
|
hdl/implementation/engine/video_pll.vhd
|
1
|
14999
|
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: video_pll.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 12.1 Build 243 01/31/2013 SP 1 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2012 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY video_pll IS
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC
);
END video_pll;
ARCHITECTURE SYN OF video_pll IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire4_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire4 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING
);
PORT (
clk : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire4_bv(0 DOWNTO 0) <= "0";
sub_wire4 <= To_stdlogicvector(sub_wire4_bv);
sub_wire1 <= sub_wire0(0);
c0 <= sub_wire1;
sub_wire2 <= inclk0;
sub_wire3 <= sub_wire4(0 DOWNTO 0) & sub_wire2;
altpll_component : altpll
GENERIC MAP (
clk0_divide_by => 2,
clk0_duty_cycle => 50,
clk0_multiply_by => 1,
clk0_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 20000,
intended_device_family => "Cyclone II",
lpm_hint => "CBX_MODULE_PREFIX=video_pll",
lpm_type => "altpll",
operation_mode => "NORMAL",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_UNUSED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_UNUSED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_UNUSED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED"
)
PORT MAP (
inclk => sub_wire3,
clk => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "25.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "25.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "video_pll.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "2"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
-- Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL video_pll.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL video_pll.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL video_pll.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL video_pll.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL video_pll.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL video_pll_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON
|
unlicense
|
ricardo-jasinski/vhdl-game-engine
|
hdl/testbench/tbu_text_out_pkg.vhd
|
1
|
1309
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
package tbu_text_out_pkg is
procedure put(text: string);
procedure print(text: string; newline: boolean := true);
procedure put(value: real);
procedure putv(value: std_logic_vector);
procedure putv(value: unsigned);
end;
package body tbu_text_out_pkg is
procedure put(text: string) is
variable s: line;
begin
write(s, text);
writeline(output,s);
end;
shared variable current_line: line;
procedure print(text: string; newline: boolean := true) is
--variable s: line;
begin
write(current_line, text);
if (newline) then
writeline(output, current_line);
end if;
end;
procedure put(value: real) is begin
-- synthesis translate_off
put(to_string(value));
-- synthesis translate_on
end;
procedure putv(value: std_logic_vector) is begin
-- synthesis translate_off
put(to_string(value));
-- synthesis translate_on
end;
procedure putv(value: unsigned) is begin
-- synthesis translate_off
put(to_string(value));
-- synthesis translate_on
end;
end;
|
unlicense
|
ricardo-jasinski/vhdl-game-engine
|
hdl/implementation/game/adventure_demo/adventure_demo_top.vhd
|
1
|
9161
|
library ieee;
use ieee.std_logic_1164.all;
use work.basic_types_pkg.all;
use work.input_types_pkg.all;
use work.graphics_types_pkg.all;
use work.text_mode_pkg.all;
use work.sprites_pkg.all;
use work.game_state_pkg.all;
use work.resource_handles_pkg.all;
use work.resource_handles_helper_pkg.all;
use work.resource_data_pkg.all;
use work.resource_data_helper_pkg.all;
use work.npc_pkg.all;
use work.vga_pkg.all;
-- Top-level entity for the "Adventure" game demo using VAGE. On top of this
-- entity, there should be only a very simple wrapper intantiating this entity
-- and connecting its ports to the board used. It should be fairly easy to use
-- this entity in other hardware platforms, without any modifications.
entity adventure_demo_top is
port (
-- synchronous reset, used by all user logic
reset: in std_logic;
-- system clock used for all user logic
clock_50_Mhz: in std_logic;
-- VGA clock used by the video renderer; should be approximately
-- 25.715 MHz (25 MHz is acceptable)
vga_clock_in: in std_logic;
-- Same as VGA input clock, must be passed along to the video DAC chip
vga_clock_out: out std_logic;
-- VGA blank, low during horizontal or vertical retrace (pixels should be blank)
vga_blank: out std_logic;
-- VGA Hsync, low during horizontal synchronism pulse
vga_n_hsync: out std_logic;
-- VGA Vsync, low during vertical synchronism pulse
vga_n_vsync: out std_logic;
-- Composite sync for the ADV7123; if not used, should be tied low
vga_n_sync: out std_logic;
-- VGA red channel output
vga_red: out std_logic_vector(9 downto 0);
-- VGA green channel output
vga_green: out std_logic_vector(9 downto 0);
-- VGA blue channel output
vga_blue: out std_logic_vector(9 downto 0);
-- Input toggle switches, active high
input_switches: in std_logic_vector(1 downto 0);
-- Input push-button switches, active high
input_buttons: in std_logic_vector(3 downto 0);
-- Debug pins for debugging game logic (e.g., connecting to board leds)
debug_bits: out std_logic_vector(7 downto 0)
);
end;
architecture rtl of adventure_demo_top is
-- Medium-resolution time base (used for game state updates and
-- reading the inputs switches)
signal time_base_50_ms: std_logic;
-- Maximum value for the game time counter
constant GAME_TIMER_50_MS_MAX: integer := 1000;
-- Monotonic game time counter, updated every 50 ms. Can be used by
-- the game logic (eg., to animate or move sprites)
signal elapsed_time: integer range 0 to GAME_TIMER_50_MS_MAX;
-- Video engine output uses custom data type; we'll convert here to std_logic
signal vga_output_signals: vga_output_signals_type;
-- Array containing the position of each sprite on the screen; generated by
-- the game logic module and used as an input by the sprites engine
signal sprite_positions: point_array_type(GAME_SPRITES'range);
-- Each element is 'true' while the two corresponding sprites are colliding.
signal sprite_collisions: bool_vector(GAME_COLLISIONS'range);
-- Background image to be used by the video engine; currently, the game
-- logic is responsible for providing the video engine with a background tile
signal background_bitmap: paletted_bitmap_type(0 to 7, 0 to 7);
-- User logic must inform the NPC engine what are the target positions
-- for the NPCs; some types of AI (e.g., AI_FOLLOWER) use this value to
-- calculate their next position
signal npc_target_positions: point_array_type(GAME_NPCS'range);
-- The game engine (NPC engine, actually) calculates the NPC positions
-- and these values are handed over to the game logic
signal npc_positions: point_array_type(GAME_NPCS'range);
signal in_buttons: input_buttons_type;
signal game_state: game_state_type;
-- Text strgins displayed on the screen
signal text_mode_strings: text_mode_strings_type(0 to game_strings_count-1);
begin
----------------------------------------------------------------------------
-- Overall architecture description:
-- 1) Instantiate the game logic
-- 2) Instantiate the NPC engine
-- 3) Instantiate the game engine
-- 4) Select a background bitmap based on the current game state
-- 5) Convert signals between std_logic and custom data types. Internally,
-- we use custom types for better abstraction; at the interface, we use
-- std_logic for better portability and easier instantiation
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- Section 1) Instantiate the game logic. This entity receives the raw game
-- data and events, and updates the game state accordingly.
----------------------------------------------------------------------------
logic: entity work.game_logic
port map(
clock => clock_50_Mhz,
reset => reset,
time_base_50_ms => time_base_50_ms,
npc_positions => npc_positions,
npc_target_positions => npc_target_positions,
sprite_collisions => sprite_collisions,
sprites_positions => sprite_positions,
input_buttons => in_buttons,
game_state => game_state,
debug_bits => debug_bits,
text_mode_strings => text_mode_strings
);
----------------------------------------------------------------------------
-- Section 2) Instantiate the NPC engine. This entity receives low-level
-- game data, and updates the NPC positions.
----------------------------------------------------------------------------
npc: entity work.npcs_engine
generic map (
NPC_DEFINITIONS => make_npcs_initial_values(GAME_NPCS)
) port map (
clock => clock_50_Mhz,
reset => reset,
time_base => time_base_50_ms,
npc_enables => (GAME_NPCS'range => true),
npc_target_positions => npc_target_positions,
npc_positions => npc_positions
);
----------------------------------------------------------------------------
-- Section 3) Instantiate the game engine. The game engine
-- performs basic functions such as calculating sprite collisions and
-- rendering the video output.
----------------------------------------------------------------------------
engine: entity work.game_engine
generic map (
SPRITES_INITIAL_VALUES => make_sprites_initial_values(GAME_SPRITES),
SPRITES_COLLISION_QUERY => make_sprites_collision_query(GAME_COLLISIONS)
) port map (
clock_50MHz => clock_50_Mhz,
reset => reset,
sprites_enabled => (GAME_SPRITES'range => true),
sprites_coordinates => sprite_positions,
sprite_collisions_results => sprite_collisions,
elapsed_time => elapsed_time,
time_base_50_ms => time_base_50_ms,
game_state => game_state,
background_bitmap => background_bitmap,
vga_clock_in => vga_clock_in,
vga_signals => vga_output_signals,
text_mode_strings => text_mode_strings
);
----------------------------------------------------------------------------
-- Section 4)
-- Select a background bitmap based on current game state (currently, this
-- is the only feedback we provide the player with)
with game_state select background_bitmap <=
get_bitmap_from_handle(BITMAP_GAME_OVER_TILE) when GS_GAME_OVER,
get_bitmap_from_handle(BITMAP_GAME_WON_TILE) when GS_GAME_WON,
get_bitmap_from_handle(BITMAP_FOREST_TILE) when others;
----------------------------------------------------------------------------
-- Section 5) Convert signals between std_logic and custom data types.
-- Internally, we use custom types for better abstraction; at the interface,
-- we use std_logic for better portability and easier instantiation.
-- Connect each pushbutton to the corresponding game input function
in_buttons <= (
up => input_buttons(3),
down => input_buttons(2),
left => input_buttons(1),
right => input_buttons(0),
fire => input_switches(0)
);
-- Connect each VGA output signal to the correspoding VGA pin or port
vga_clock_out <= vga_output_signals.vga_clock_out;
vga_blank <= vga_output_signals.blank;
vga_n_hsync <= vga_output_signals.hsync;
vga_n_vsync <= vga_output_signals.vsync;
vga_n_sync <= vga_output_signals.sync;
vga_red <= vga_output_signals.red;
vga_green <= vga_output_signals.green;
vga_blue <= vga_output_signals.blue;
end;
|
unlicense
|
ricardo-jasinski/vhdl-game-engine
|
hdl/implementation/engine/npcs_engine.vhd
|
1
|
2406
|
library ieee;
use ieee.std_logic_1164.all;
use work.basic_types_pkg.all;
use work.npc_pkg.all;
use work.graphics_types_pkg.all;
entity npcs_engine is
generic (
NPC_DEFINITIONS: npc_array_type
);
port (
clock: in std_logic;
reset: in std_logic;
time_base: in std_logic;
npc_enables: in bool_vector;
npc_target_positions: in point_array_type;
npc_positions: out point_array_type
);
end;
architecture rtl of npcs_engine is
alias npcs: npc_array_type is NPC_DEFINITIONS;
begin
create_npcs: for i in npcs'range generate
npc_is_follower: if npcs(i).ai_type = AI_FOLLOWER generate
follower_npc: entity work.npc_ai_follower port map (
reset => reset, clock => clock, time_base => time_base,
allowed_region => npcs(i).allowed_region,
initial_position => npcs(i).initial_position,
absolute_speed => npcs(i).absolute_speed,
slowdown_factor => npcs(i).slowdown_factor,
enabled => npc_enables(i),
assigned_position => npc_target_positions(i),
npc_position => npc_positions(i)
);
end generate;
npc_is_bouncer: if npcs(i).ai_type = AI_BOUNCER generate
bouncer_npc: entity work.npc_ai_bouncer port map(
reset => reset, clock => clock, time_base => time_base,
initial_position => npcs(i).initial_position,
initial_speed => npcs(i).initial_speed,
allowed_region => npcs(i).allowed_region,
enabled => npc_enables(i),
npc_position => npc_positions(i)
);
end generate;
npc_is_projectile: if npcs(i).ai_type = AI_PROJECTILE generate
projectile_npc: entity work.npc_ai_projectile port map(
reset => reset, clock => clock, time_base => time_base,
initial_position => npcs(i).initial_position,
initial_speed => npcs(i).initial_speed,
allowed_region => npcs(i).allowed_region,
enabled => npc_enables(i),
assigned_position => npc_target_positions(i),
npc_position => npc_positions(i)
);
end generate;
end generate;
end;
|
unlicense
|
Nibble-Knowledge/peripheral-ide
|
IDE/IDE3_write/parity_check.vhd
|
1
|
1128
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:03:33 11/10/2015
-- Design Name:
-- Module Name: parity_check - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity parity_check is
Port ( cs : in STD_LOGIC;
pa : in STD_LOGIC;
cpu_wr : in STD_LOGIC;
checked : out STD_LOGIC);
end parity_check;
architecture Behavioral of parity_check is
signal temp: STD_LOGIC;
begin
temp <= pa and cs;
checked <= temp and cpu_wr;
end Behavioral;
|
unlicense
|
Nibble-Knowledge/peripheral-ide
|
IDE/IDE3_write/regtest.vhd
|
1
|
2763
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:51:47 11/11/2015
-- Design Name:
-- Module Name: C:/Users/Gham/Desktop/Actual files/IDE/IDE3_final/IDE3_final/regtest.vhd
-- Project Name: IDE3_final
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: SHIFT_REGISTER
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY regtest IS
END regtest;
ARCHITECTURE behavior OF regtest IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT SHIFT_REGISTER
PORT(
CLK : IN std_logic;
DATA : IN std_logic_vector(3 downto 0);
RESET,enable : IN std_logic;
OUTPUT : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
--Inputs
signal CLK : std_logic := '0';
signal DATA : std_logic_vector(3 downto 0) := (others => '0');
signal RESET, enable : std_logic := '0';
--Outputs
signal OUTPUT : std_logic_vector(15 downto 0);
-- Clock period definitions
constant CLK_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: SHIFT_REGISTER PORT MAP (
CLK => CLK,
DATA => DATA,
RESET => RESET,
enable=> enable,
OUTPUT => OUTPUT
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 10 ns;
-- wait for CLK_period*10;
RESET <= '1';
WAIT FOR 10 NS;
RESET <= '0';
WAIT FOR 10 NS;
-- insert stimulus here
DATA <= "1111";
WAIT FOR 10 NS ;
enable<= '1';
WAIT FOR 10 NS ;
enable<= '0';
DATA <= "0000";
WAIT FOR 10 NS ;
enable<= '1';
WAIT FOR 10 NS ;
enable<= '0';
DATA <= "1111";
WAIT FOR 10 NS ;
enable<= '1';
WAIT FOR 10 NS ;
enable<= '0';
DATA <= "0000";
WAIT FOR 10 NS ;
enable<= '1';
WAIT FOR 10 NS ;
enable<= '0';
wait;
end process;
END;
|
unlicense
|
eliben/luz-cpu
|
experimental/luz_uc/luz_uc_rtl/cpu/cpu_top.vhd
|
2
|
5611
|
-- CPU core top-level entity
--
-- Luz micro-controller implementation
-- Eli Bendersky (C) 2008-2010
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.cpu_defs.all;
entity luz_cpu is
generic
(
RESET_ADDRESS: word
);
port
(
clk: in std_logic;
reset_n: in std_logic;
-- Standard Wishbone signals
--
cyc_o: out std_logic;
stb_o: out std_logic;
we_o: out std_logic;
sel_o: out std_logic_vector(3 downto 0);
adr_o: out word;
data_o: out word;
ack_i: in std_logic;
err_i: in std_logic;
data_i: in word;
-- IRQs
--
irq_i: in word;
-- '1' when the CPU executes the 'halt' instruction
--
halt: out std_logic;
-- '1' when the CPU fetches an instruction from the bus
--
ifetch: out std_logic;
-- core regs ports
--
core_reg_read_sel: out core_reg_sel;
core_reg_read_data: in word;
core_reg_write_sel: out core_reg_sel;
core_reg_write_strobe: out std_logic;
core_reg_write_data: out word
);
end luz_cpu;
architecture luz_cpu_arc of luz_cpu is
signal mem_read: std_logic;
signal mem_write: std_logic;
signal mem_bytesel: std_logic_vector(3 downto 0);
signal mem_addr: word;
signal mem_data_out: word;
signal mem_ack: std_logic;
signal mem_data_in: word;
signal reg_sel_a: std_logic_vector(4 downto 0);
signal reg_a_out: word;
signal reg_sel_b: std_logic_vector(4 downto 0);
signal reg_b_out: word;
signal reg_sel_c: std_logic_vector(4 downto 0);
signal reg_c_out: word;
signal reg_sel_y: std_logic_vector(4 downto 0);
signal reg_write_y: std_logic;
signal reg_y_in: word;
signal reg_sel_z: std_logic_vector(4 downto 0);
signal reg_write_z: std_logic;
signal reg_z_in: word;
signal alu_op: cpu_opcode;
signal alu_rs_in: word;
signal alu_rd_in: word;
signal alu_rt_in: word;
signal alu_imm_in: word;
signal alu_output_a: word;
signal alu_output_b: word;
signal pc_in: word;
signal pc_out: word;
signal pc_write: std_logic;
begin
controller_map: entity work.controller(controller_arc)
port map
(
clk => clk,
reset_n => reset_n,
mem_read => mem_read,
mem_write => mem_write,
mem_bytesel => mem_bytesel,
mem_addr => mem_addr,
mem_data_out => mem_data_out,
mem_ack => mem_ack,
mem_data_in => mem_data_in,
reg_sel_a => reg_sel_a,
reg_a_out => reg_a_out,
reg_sel_b => reg_sel_b,
reg_b_out => reg_b_out,
reg_sel_c => reg_sel_c,
reg_c_out => reg_c_out,
reg_sel_y => reg_sel_y,
reg_write_y => reg_write_y,
reg_y_in => reg_y_in,
reg_sel_z => reg_sel_z,
reg_write_z => reg_write_z,
reg_z_in => reg_z_in,
alu_op => alu_op,
alu_rs_in => alu_rs_in,
alu_rd_in => alu_rd_in,
alu_rt_in => alu_rt_in,
alu_imm_in => alu_imm_in,
alu_output_a => alu_output_a,
alu_output_b => alu_output_b,
pc_in => pc_in,
pc_out => pc_out,
pc_write => pc_write
);
-- Bridging the controller memory interface to Wishbone
--
mem_ack <= ack_i;
mem_data_in <= data_i;
cyc_o <= mem_write or mem_read;
stb_o <= mem_write or mem_read;
we_o <= mem_write;
sel_o <= mem_bytesel;
adr_o <= mem_addr;
data_o <= mem_data_out;
alu_map: entity work.alu(alu_arc)
port map
(
clk => clk,
reset_n => reset_n,
op => alu_op,
rs_in => alu_rs_in,
rt_in => alu_rt_in,
rd_in => alu_rd_in,
imm_in => alu_imm_in,
output_a => alu_output_a,
output_b => alu_output_b
);
gp_registers_map: entity work.registers(registers_arc)
generic map
(
NREGS_LOG2 => 5
)
port map
(
clk => clk,
reset_n => reset_n,
sel_a => reg_sel_a,
reg_a_out => reg_a_out,
sel_b => reg_sel_b,
reg_b_out => reg_b_out,
sel_c => reg_sel_c,
reg_c_out => reg_c_out,
sel_y => reg_sel_y,
write_y => reg_write_y,
reg_y_in => reg_y_in,
sel_z => reg_sel_z,
write_z => reg_write_z,
reg_z_in => reg_z_in
);
pc_map: entity work.program_counter(program_counter_arc)
generic map
(
INIT => RESET_ADDRESS
)
port map
(
clk => clk,
reset_n => reset_n,
pc_in => pc_in,
pc_out => pc_out,
pc_write => pc_write
);
end;
|
unlicense
|
azeemshaikh38/PipelinedProcessorWithInterrupts
|
Processor/decoder_ldstr.vhd
|
1
|
10225
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity decode is
port(
din: in std_logic_vector(15 downto 0);
reg_rd_en : out std_logic;
Raddr1:out std_logic_vector(3 downto 0);
Raddr2:out std_logic_vector(3 downto 0);
memaddr: out std_logic_vector(7 downto 0);
operation:out std_logic_vector(4 downto 0);
dest_reg_en: out std_logic;
dest_reg: out std_logic_vector(3 downto 0);
src_reg1_en: out std_logic;
src_reg1: out std_logic_vector(3 downto 0);
src_reg2_en: out std_logic;
src_reg2: out std_logic_vector(3 downto 0);
return_from_interrupt : out std_logic
);
end decode;
architecture behav of decode is
begin
process(din)
variable check : std_logic_vector(3 downto 0);
begin
dest_reg_en <= '0';
dest_reg <= "0000";
src_reg1_en <= '0';
src_reg1 <= "0000";
src_reg2_en <= '0';
src_reg2 <= "0000";
return_from_interrupt <= '0';
reg_rd_en <= '1';
check := din(15 downto 12);
case check is
-------------------------------- No Operation ------------------------------------------
when "0000" => -- no op
Raddr1 <= "0000";
Raddr2 <= "0000";
memaddr<= "00000000";
operation <= "00000";
dest_reg_en <= '0';
src_reg1_en <= '0';
src_reg2_en <= '0';
reg_rd_en <= '0';
---------------------------------- Add/Subtract Operations ------------------------------
when "0001" => -- add immediate
Raddr1<= din(11 downto 8);
Raddr2<= "0000";
memaddr<= din(7 downto 0);
operation<= "00001";
dest_reg_en <= '1';
dest_reg <= din(11 downto 8);
src_reg1_en <= '1';
src_reg1 <= din(11 downto 8);
src_reg2_en <= '0';
when "0010" => -- add/sub
Raddr1<= din(7 downto 4);
Raddr2<= din(3 downto 0);
memaddr<= "00000000";
if (din(11 downto 8) = "0000") then
operation<= "00010"; --add
else
operation<= "00011"; --sub
end if;
dest_reg_en <= '1';
dest_reg <= din(7 downto 4);
src_reg1_en <= '1';
src_reg1 <= din(7 downto 4);
src_reg2_en <= '1';
src_reg2 <= din(3 downto 0);
--------------------------------------- Increment/Decrement ---------------------------------
when "0011" => -- increment/decrement
Raddr1<= din(11 downto 8);
Raddr2<= "0000";
memaddr<= "00000000";
if (din(11 downto 8) = "0000") then
operation<= "00100"; --inc
else
operation<= "00101"; --dec
end if;
dest_reg_en <= '1';
dest_reg <= din(11 downto 8);
src_reg1_en <= '1';
src_reg1 <= din(11 downto 8);
src_reg2_en <= '0';
------------------------------------------ Shift Operations -----------------------------------
when "0100" => -- shift left/right
Raddr1<= din(11 downto 8);
Raddr2<= "0000";
memaddr<= "00000000";
if (din(11 downto 8) = "0000") then
operation<= "00110"; --shift left
else
operation<= "00111"; --shift right
end if;
dest_reg_en <= '1';
dest_reg <= din(11 downto 8);
src_reg1_en <= '1';
src_reg1 <= din(11 downto 8);
src_reg2_en <= '0';
-------------------------------------------- Logical Operations ---------------------------------
when "0101" => --- logical operator
dest_reg_en <= '1';
dest_reg <= din(7 downto 4);
src_reg1_en <= '1';
src_reg1 <= din(7 downto 4);
src_reg2_en <= '1';
src_reg2 <= din(3 downto 0);
if(din(11 downto 8) = "0000") then -- not
operation<= "01000";
Raddr1<= din(11 downto 8);
Raddr2<= "0000";
memaddr<= "00000000";
dest_reg <= din(11 downto 8);
src_reg1 <= din(11 downto 8);
src_reg2_en <= '0';
end if;
if(din(11 downto 8) = "0001") then -- nor
operation<= "01001";
Raddr1<= din(7 downto 4);
Raddr2<= din(3 downto 0);
memaddr<= "00000000";
end if;
if(din(11 downto 8) = "0010") then -- nand
operation<= "01010";
Raddr1<= din(7 downto 4);
Raddr2<= din(3 downto 0);
memaddr<= "00000000";
end if;
if(din(11 downto 8) = "0011") then -- xor
operation<= "01011";
Raddr1<= din(7 downto 4);
Raddr2<= din(3 downto 0);
memaddr<= "00000000";
end if;
if(din(11 downto 8) = "0100") then -- and
operation<= "01100";
Raddr1<= din(7 downto 4);
Raddr2<= din(3 downto 0);
memaddr<= "00000000";
end if;
if(din(11 downto 8) = "0101") then -- nor
operation<= "01101";
Raddr1<= din(7 downto 4);
Raddr2<= din(3 downto 0);
memaddr<= "00000000";
end if;
------------------------------------- Set/Clear Operations -------------------------
if(din(11 downto 8) = "0110") then -- clear
operation<= "01110";
Raddr1<= din(7 downto 4);
Raddr2<= "0000";
memaddr<= "00000000";
dest_reg <= din(7 downto 4);
src_reg1 <= din(7 downto 4);
src_reg2_en <= '0';
end if;
if(din(11 downto 8) = "0111" ) then -- set
operation<= "01111";
Raddr1<= din(7 downto 4);
Raddr2<= "0000";
memaddr<= "00000000";
dest_reg <= din(7 downto 4);
src_reg1 <= din(7 downto 4);
src_reg2_en <= '0';
end if;
if(din(11 downto 8) = "1111") then -- set if less than
operation<= "10000";
Raddr1<= din(7 downto 4);
Raddr2<= din(3 downto 0);
memaddr<= "00000000";
dest_reg <= din(7 downto 4);
src_reg1 <= din(7 downto 4);
src_reg2 <= din(3 downto 0);
end if;
-------------------------------------- Move Operations -------------------------------------
if(din(11 downto 8) = "1000") then -- move
operation<= "10001";
Raddr1<= din(7 downto 4);
Raddr2<= din(3 downto 0);
memaddr<= "00000000";
dest_reg <= din(7 downto 4);
src_reg1 <= din(3 downto 0);
src_reg2_en <= '0';
end if;
------------------------------------- Enable Interrupt -------------------------------------
when "0111" => --enable interrupts
operation<= "10010";
Raddr1<= "0000";
Raddr2<= "0000";
memaddr<= "00000000";
dest_reg_en <= '0';
src_reg1_en <= '0';
src_reg2_en <= '0';
reg_rd_en <= '0';
----------------------------------- Load/Store Operations ----------------------------------
when "1000" => --load indirect
Raddr1<= din(7 downto 4);
Raddr2<= din(3 downto 0);
memaddr<= "00000000";
operation<= "10011";
dest_reg_en <= '1';
dest_reg <= din(7 downto 4);
src_reg1_en <= '0';
src_reg2_en <= '1';
src_reg2 <= din(3 downto 0);
when "1001" => --store indirect
Raddr1<= din(7 downto 4);
Raddr2<= din(3 downto 0);
memaddr<= "00000000";
operation <= "10100";
dest_reg_en <= '0';
src_reg1_en <= '1';
src_reg1 <= din(7 downto 4);
src_reg2_en <= '1';
src_reg2 <= din(3 downto 0);
--reg_rd_en <= '1';
when "1010"=> -- load register
Raddr1 <= din(11 downto 8);
Raddr2 <= "0000";
memaddr <= din(7 downto 0);
operation <= "10101";
dest_reg_en <= '1';
dest_reg <= din(11 downto 8);
src_reg1_en <= '0';
src_reg2_en <= '0';
reg_rd_en <= '0';
when "1011"=> -- store register
Raddr1 <= din(11 downto 8);
Raddr2 <= "0000";
memaddr <= din(7 downto 0);
operation <= "10110";
dest_reg_en <= '0';
src_reg1_en <= '1';
src_reg1 <= din(11 downto 8);
src_reg2_en <= '0';
--reg_rd_en <= '1';
------------------------------------------- Branch Intructions -----------------------------------
when "1100" => -- Jump
Raddr1 <= X"0";
Raddr2 <= X"0";
memaddr <= din(7 downto 0);
operation <= "10111";
dest_reg_en <= '0';
src_reg1_en <= '0';
src_reg2_en <= '0';
reg_rd_en <= '0';
when "1101" => -- Branch if Zero
Raddr1 <= din(11 downto 8);
Raddr2 <= X"0";
memaddr <= din(7 downto 0);
operation <= "11000";
dest_reg_en <= '0';
src_reg1_en <= '1';
src_reg1 <= din(11 downto 8);
src_reg2_en <= '0';
--reg_rd_en <= '0';
when "1110" => -- Branch if not Zero
Raddr1 <= din(11 downto 8);
Raddr2 <= X"0";
memaddr <= din(7 downto 0);
operation <= "11001";
dest_reg_en <= '0';
src_reg1_en <= '1';
src_reg1 <= din(11 downto 8);
src_reg2_en <= '0';
--reg_rd_en <= '0';
------------------------------------------ Return from Interrupt -----------------------------------
when "1111" => -- Return from Interrupt
Raddr1 <= "0000";
Raddr2 <= "0000";
memaddr<= "00000000";
operation <= "00000";
dest_reg_en <= '0';
src_reg1_en <= '0';
src_reg2_en <= '0';
reg_rd_en <= '0';
return_from_interrupt <= '1';
---------------------------------------------- Default/Nop ------------------------------------------
when others =>
Raddr1 <= "0000";
Raddr2 <= "0000";
memaddr<= "00000000";
operation <= "00000";
dest_reg_en <= '0';
src_reg1_en <= '0';
src_reg2_en <= '0';
reg_rd_en <= '0';
end case;
end process;
end architecture;
|
unlicense
|
EJDomi/pixel-dtb-firmware-readout-chain-master
|
dtb/nedge_s.vhd
|
2
|
2654
|
-- Copyright (C) 1991-2010 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- PROGRAM "Quartus II 64-Bit"
-- VERSION "Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Full Version"
-- CREATED "Thu Oct 31 13:57:57 2013"
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY work;
ENTITY nedge_s IS
PORT
(
D : IN STD_LOGIC;
CK : IN STD_LOGIC;
Q : OUT STD_LOGIC
);
END nedge_s;
ARCHITECTURE bdf_type OF nedge_s IS
SIGNAL SYNTHESIZED_WIRE_0 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_1 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_2 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_8 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_3 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_4 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_5 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_6 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_7 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_9 : STD_LOGIC;
BEGIN
SYNTHESIZED_WIRE_0 <= '1';
SYNTHESIZED_WIRE_1 <= '1';
SYNTHESIZED_WIRE_2 <= '1';
SYNTHESIZED_WIRE_3 <= '1';
SYNTHESIZED_WIRE_4 <= '1';
SYNTHESIZED_WIRE_6 <= '1';
PROCESS(CK,SYNTHESIZED_WIRE_0,SYNTHESIZED_WIRE_1)
BEGIN
IF (SYNTHESIZED_WIRE_0 = '0') THEN
SYNTHESIZED_WIRE_8 <= '0';
ELSIF (SYNTHESIZED_WIRE_1 = '0') THEN
SYNTHESIZED_WIRE_8 <= '1';
ELSIF (RISING_EDGE(CK)) THEN
SYNTHESIZED_WIRE_8 <= D;
END IF;
END PROCESS;
PROCESS(CK,SYNTHESIZED_WIRE_2,SYNTHESIZED_WIRE_3)
BEGIN
IF (SYNTHESIZED_WIRE_2 = '0') THEN
SYNTHESIZED_WIRE_9 <= '0';
ELSIF (SYNTHESIZED_WIRE_3 = '0') THEN
SYNTHESIZED_WIRE_9 <= '1';
ELSIF (RISING_EDGE(CK)) THEN
SYNTHESIZED_WIRE_9 <= SYNTHESIZED_WIRE_8;
END IF;
END PROCESS;
PROCESS(CK,SYNTHESIZED_WIRE_4,SYNTHESIZED_WIRE_6)
BEGIN
IF (SYNTHESIZED_WIRE_4 = '0') THEN
Q <= '0';
ELSIF (SYNTHESIZED_WIRE_6 = '0') THEN
Q <= '1';
ELSIF (RISING_EDGE(CK)) THEN
Q <= SYNTHESIZED_WIRE_5;
END IF;
END PROCESS;
SYNTHESIZED_WIRE_5 <= SYNTHESIZED_WIRE_7 AND SYNTHESIZED_WIRE_9;
SYNTHESIZED_WIRE_7 <= SYNTHESIZED_WIRE_8 XOR SYNTHESIZED_WIRE_9;
END bdf_type;
|
unlicense
|
EJDomi/pixel-dtb-firmware-readout-chain-master
|
dtb/HeRhTr.vhd
|
2
|
4092
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity HeRhTr is
Port ( clk : in STD_LOGIC;
reset:in STD_LOGIC;
sd_in: in STD_LOGIC;
sd_out:out STD_LOGIC;
TbmHeader:out STD_LOGIC;
RocHeader:out STD_LOGIC;
TbmTrailer:out STD_LOGIC;
TP:out STD_LOGIC;
TPP:out STD_LOGIC;
allowRocH:out STD_LOGIC);
end HeRhTr;
architecture Behaviorial of HeRhTr is
--signal
signal s_1: STD_LOGIC:='0';
signal s_2: STD_LOGIC:='0';
signal s_3: STD_LOGIC:='0';
signal s_4: STD_LOGIC:='0';
signal s_5: STD_LOGIC:='0';
signal s_6: STD_LOGIC:='0';
signal s_7: STD_LOGIC:='0';
signal s_8: STD_LOGIC:='0';
signal s_9: STD_LOGIC:='0';
signal s_10: STD_LOGIC:='0';
signal s_11: STD_LOGIC:='0';
signal s_12: STD_LOGIC:='0';
signal s_13: STD_LOGIC:='0';
signal s_d1: STD_LOGIC:='0';
signal s_d2: STD_LOGIC:='0';
signal s_d3: STD_LOGIC:='0';
signal s_d4: STD_LOGIC:='0';
signal s_d5: STD_LOGIC:='0';
signal s_d6: STD_LOGIC:='0';
signal s_d7: STD_LOGIC:='0';
signal s_d8: STD_LOGIC:='0';
signal s_d9: STD_LOGIC:='0';
signal s_d10: STD_LOGIC:='0';
signal s_d11: STD_LOGIC:='0';
signal s_d12: STD_LOGIC:='0';
signal s_d13: STD_LOGIC:='0';
signal s_d14: STD_LOGIC:='0';
signal s_d15: STD_LOGIC:='0';
signal s_d16: STD_LOGIC:='0';
signal s_HEADER: STD_LOGIC:='0';
signal s_ROC: STD_LOGIC:='0';
signal s_TRAILER: STD_LOGIC:='0';
signal s_DataWindow: STD_LOGIC:='0';
signal s_count: STD_LOGIC_VECTOR (3 downto 0):="0000";
signal s_TC: STD_LOGIC:='0';
begin
------------------------------------------------------------
p_pipe: process (clk)
begin
if (rising_edge(clk)) then
s_1 <= sd_in;
s_2 <= s_1;
s_3 <= s_2;
s_4 <= s_3;
s_5 <= s_4;
s_6 <= s_5;
s_7 <= s_6;
s_8 <= s_7;
s_9 <= s_8;
s_10 <= s_9;
s_11 <= s_10;
s_12 <= s_11;
s_13 <= s_12;
end if;
end process p_pipe;
sd_out <= s_13;
------------------------------------------------------------
s_HEADER <= ( (not s_11) and s_10 and s_9 and s_8 and s_7
and s_6 and s_5 and s_4 and s_3 and s_2
and (not s_1) and (not sd_in) );
s_ROC <= ( (not s_11) and s_10 and s_9 and s_8 and s_7
and s_6 and s_5 and s_4 and s_3 and (not s_2)
and s_d15 and s_DataWindow);
s_TRAILER <= ( (not s_11) and s_10 and s_9 and s_8 and s_7
and s_6 and s_5 and s_4 and s_3 and s_2
and s_1 and sd_in );
------------------------------------------------------------
p_DataWindow: process (clk, reset)
begin
if (reset = '1') then
s_DataWindow <= '0';
elsif (rising_edge(clk)) then
if ( s_HEADER = '1') then
s_DataWindow <= '1';
elsif ( s_TRAILER = '1') then
s_DataWindow <= '0';
end if;
end if;
end process p_DataWindow;
TP <= s_DataWindow;
------------------------------------------------------------
p_Mod12Cnt: process (clk)
begin
if (rising_edge(clk)) then
if (s_DataWindow = '1') then --count
if (s_count= "1011") then
s_count <= "0000";
s_TC <='1';
else
s_count <= s_count +1;
s_TC <='0';
end if;
else -- do not count
s_count <= "0000";
s_TC <='0';
end if;
end if;
end process p_Mod12Cnt;
TPP <= s_TC;
------------------------------------------------------------
p_delay: process (clk)
begin
if (rising_edge(clk)) then
s_d1 <= s_TC;
s_d2 <= s_d1;
s_d3 <= s_d2;
s_d4 <= s_d3;
s_d5 <= s_d4;
s_d6 <= s_d5;
s_d7 <= s_d6;
s_d8 <= s_d7;
s_d9 <= s_d8;
s_d10 <= s_d9;
s_d11 <= s_d10;
s_d12 <= s_d11;
s_d13 <= s_d12;
s_d14 <= s_d13;
s_d15 <= s_d14;
s_d16 <= s_d15;
end if;
end process p_delay;
allowRocH <= s_d16;
------------------------------------------------------------
p_output_registers : process (clk)
begin
if (rising_edge(clk)) then
TbmHeader <= s_HEADER;
RocHeader <= s_ROC;
TbmTrailer <= s_TRAILER;
end if;
end process p_output_registers;
------------------------------------------------------------
end;--Behavioral
|
unlicense
|
EJDomi/pixel-dtb-firmware-readout-chain-master
|
dtb/lpm_counter3.vhd
|
2
|
4425
|
-- megafunction wizard: %LPM_COUNTER%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_counter
-- ============================================================
-- File Name: lpm_counter3.vhd
-- Megafunction Name(s):
-- lpm_counter
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 350 03/24/2010 SP 2 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_counter3 IS
PORT
(
aclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (1 DOWNTO 0)
);
END lpm_counter3;
ARCHITECTURE SYN OF lpm_counter3 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (1 DOWNTO 0);
COMPONENT lpm_counter
GENERIC (
lpm_direction : STRING;
lpm_port_updown : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
aclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (1 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(1 DOWNTO 0);
lpm_counter_component : lpm_counter
GENERIC MAP (
lpm_direction => "UP",
lpm_port_updown => "PORT_UNUSED",
lpm_type => "LPM_COUNTER",
lpm_width => 2
)
PORT MAP (
aclr => aclr,
clock => clock,
q => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACLR NUMERIC "1"
-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
-- Retrieval info: PRIVATE: ASET NUMERIC "0"
-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
-- Retrieval info: PRIVATE: CNT_EN NUMERIC "0"
-- Retrieval info: PRIVATE: CarryIn NUMERIC "0"
-- Retrieval info: PRIVATE: CarryOut NUMERIC "0"
-- Retrieval info: PRIVATE: Direction NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria GX"
-- Retrieval info: PRIVATE: ModulusCounter NUMERIC "0"
-- Retrieval info: PRIVATE: ModulusValue NUMERIC "0"
-- Retrieval info: PRIVATE: SCLR NUMERIC "0"
-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: SSET NUMERIC "0"
-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "2"
-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "UP"
-- Retrieval info: CONSTANT: LPM_PORT_UPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COUNTER"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "2"
-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
-- Retrieval info: USED_PORT: q 0 0 2 0 OUTPUT NODEFVAL q[1..0]
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 2 0 @q 0 0 2 0
-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter3.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter3.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter3.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter3.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter3_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter3_waveforms.html TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter3_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: lpm
|
unlicense
|
TWW12/lzw
|
final_project_sim/lzw/lzw.srcs/sources_1/imports/temp/lzw.vhd
|
4
|
7433
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity lzw is
generic (num_blocks : integer := 4);
Port (
clk : in std_logic;
rst : in std_logic;
--Input character from FIFO
char_in : in std_logic_vector(7 downto 0);
--Input character valid? (tie to NOT fifo_empty)
input_valid : in std_logic;
--How many characters is the input file
file_size : in std_logic_vector(15 downto 0);
--FIFO read acknowledgement
input_rd : out std_logic;
--Output data
prefix_out : out std_logic_vector(11 downto 0);
--Output data is valid, tie to output FIFO wr_en
output_valid : out std_logic;
--Done processing current file
done : out std_logic);
end lzw;
architecture Behavioral of lzw is
type state_type is (S_RST,S_WAIT,S_READ_FIRST_CHAR,S_READ,S_SEARCH);
signal state : state_type;
signal current_char : std_logic_vector(7 downto 0);
signal current_prefix : std_logic_vector(11 downto 0);
signal output_last_prefix : std_logic;
signal start_search : std_logic;
signal search_entry : std_logic_vector(19 downto 0);
signal dict_wr : std_logic;
signal wr_entry : std_logic_vector(19 downto 0);
signal match_prefix : std_logic_vector(11 downto 0);
signal entry_found : std_logic;
signal search_completed : std_logic;
signal dictionary_full : std_logic;
signal eof : std_logic;
signal bytes_read : std_logic_vector(15 downto 0);
begin
prefix_out <= current_prefix;
GEN_DICT1: if num_blocks = 1 generate
U_DICTIONARY : entity work.dictionary_block
port map (
clk => clk,
rst => rst,
start_search => start_search,
search_entry => search_entry,
wr_en => dict_wr,
wr_entry => wr_entry,
prefix => match_prefix,
entry_found => entry_found,
search_completed => search_completed,
dictionary_full => dictionary_full);
end generate GEN_DICT1;
GEN_DICT2: if num_blocks = 2 generate
U_DICTIONARY : entity work.dictionary_2
port map (
clk => clk,
rst => rst,
start_search => start_search,
search_entry => search_entry,
wr_en => dict_wr,
wr_entry => wr_entry,
prefix => match_prefix,
entry_found => entry_found,
search_completed => search_completed,
dictionary_full => dictionary_full);
end generate GEN_DICT2;
GEN_DICT4: if num_blocks = 4 generate
U_DICTIONARY : entity work.dictionary_4
port map (
clk => clk,
rst => rst,
start_search => start_search,
search_entry => search_entry,
wr_en => dict_wr,
wr_entry => wr_entry,
prefix => match_prefix,
entry_found => entry_found,
search_completed => search_completed,
dictionary_full => dictionary_full);
end generate GEN_DICT4;
search_entry(7 downto 0) <= current_char;
search_entry(19 downto 8) <= current_prefix;
wr_entry <= search_entry;
--State machine and synchronous outputs
process(clk,rst)
begin
if rst = '1' then
state <= S_RST;
current_char <= x"00";
current_prefix <= x"000";
start_search <= '0';
input_rd <= '0';
bytes_read <= (bytes_read'range => '0');
done <= '0';
elsif rising_edge(clk) then
--default values
input_rd <= '0';
start_search <= '0';
case state is
when S_RST =>
state <= S_READ_FIRST_CHAR;
when S_READ_FIRST_CHAR =>
if input_valid = '1' then
current_prefix(7 downto 0) <= char_in;
input_rd <= '1';
state <= S_WAIT;
bytes_read <= x"0001";
done <= '0';
end if;
when S_WAIT =>
input_rd <= '0';
state <= S_READ;
--read in another character
when S_READ =>
if input_valid = '1' then
current_char <= char_in;
start_search <= '1';
input_rd <= '1';
state <= S_SEARCH;
bytes_read <= std_logic_vector(unsigned(bytes_read)+to_unsigned(1,16));
end if;
when S_SEARCH =>
if search_completed = '1' then
state <= S_READ;
--if its found, save the prefix, read another char and look for another string
if entry_found = '1' then
current_prefix <= match_prefix;
--otherwise we'll be writing to the dictionary (look at asynchronous outputs below)
--and clearing out our saved values
else
current_char <= x"00";
current_prefix(11 downto 8) <= x"0";
current_prefix(7 downto 0) <= current_char;
end if;
if eof = '1' then
state <= S_READ_FIRST_CHAR;
done <= '1';
end if;
end if;
end case;
end if;
end process;
--when we force the controller to output the last prefix value
--we need to delay it by one cycle or else the wrong value is marked as valid
process(clk,rst)
begin
if rst = '1' then
output_last_prefix <= '0';
elsif rising_edge(clk) then
if state = S_SEARCH and search_completed = '1' and
entry_found = '1' and eof = '1' then
output_last_prefix <= '1';
else
output_last_prefix <= '0';
end if;
end if;
end process;
--Asynchronous outputs
process(state,search_completed,entry_found,dictionary_full,bytes_read,file_size)
begin
output_valid <= output_last_prefix;
dict_wr <= '0';
--if we finished a search and no entry was found, write new entry to the dictionary
--and output the current values
if state = S_SEARCH and search_completed = '1' and entry_found = '0' then
output_valid <= '1';
dict_wr <= not dictionary_full;
end if;
if bytes_read = file_size then
eof <= '1';
else
eof <= '0';
end if;
end process;
end Behavioral;
|
unlicense
|
TWW12/lzw
|
ip_repo/axi_compression_1.0/src/bram_1024_2/synth/bram_1024_2.vhd
|
4
|
14457
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_3_5;
USE blk_mem_gen_v8_3_5.blk_mem_gen_v8_3_5;
ENTITY bram_1024_2 IS
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(19 DOWNTO 0)
);
END bram_1024_2;
ARCHITECTURE bram_1024_2_arch OF bram_1024_2 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF bram_1024_2_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_3_5 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
rsta_busy : OUT STD_LOGIC;
rstb_busy : OUT STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_5;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF bram_1024_2_arch: ARCHITECTURE IS "blk_mem_gen_v8_3_5,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF bram_1024_2_arch : ARCHITECTURE IS "bram_1024_2,blk_mem_gen_v8_3_5,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF bram_1024_2_arch: ARCHITECTURE IS "bram_1024_2,blk_mem_gen_v8_3_5,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.3,x_ipCoreRevision=5,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=0,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=bram_1024_2.mi" &
"f,C_INIT_FILE=bram_1024_2.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=20,C_READ_WIDTH_A=20,C_WRITE_DEPTH_A=1024,C_READ_DEPTH_A=1024,C_ADDRA_WIDTH=10,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=20,C_READ_WIDTH_B=20,C_WRITE_DE" &
"PTH_B=1024,C_READ_DEPTH_B=1024,C_ADDRB_WIDTH=10,C_HAS_MEM_OUTPUT_REGS_A=1,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_EN_SAFETY_CKT=0,C_DISABLE" &
"_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=1,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 2.74095 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : blk_mem_gen_v8_3_5
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 0,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 1,
C_INIT_FILE_NAME => "bram_1024_2.mif",
C_INIT_FILE => "bram_1024_2.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 1,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 20,
C_READ_WIDTH_A => 20,
C_WRITE_DEPTH_A => 1024,
C_READ_DEPTH_A => 1024,
C_ADDRA_WIDTH => 10,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 20,
C_READ_WIDTH_B => 20,
C_WRITE_DEPTH_B => 1024,
C_READ_DEPTH_B => 1024,
C_ADDRB_WIDTH => 10,
C_HAS_MEM_OUTPUT_REGS_A => 1,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_EN_SAFETY_CKT => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "1",
C_COUNT_18K_BRAM => "0",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 2.74095 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => ena,
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => '0',
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 20)),
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 20)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END bram_1024_2_arch;
|
unlicense
|
ricardo-jasinski/vhdl-csv-file-reader
|
hdl/testbench/csv_file_reader_pkg_tb.vhd
|
1
|
3209
|
use std.env.all;
use std.textio.all;
use work.testbench_utils.all;
use work.csv_file_reader_pkg.all;
-- Testbench for the csv_file_reader_pkg package. Test the package's basic
-- operation by reading data from known test files and checking the values read
-- against their expected values.
entity csv_file_read_pkg_tb is
end;
architecture testbench of csv_file_read_pkg_tb is
procedure read_test_files is
variable csv_file_1: csv_file_reader_type;
variable csv_file_2: csv_file_reader_type;
variable read_string: string(1 to 256);
variable read_integer: integer;
variable read_boolean: boolean;
variable read_real: real;
begin
puts("opening CSV files");
csv_file_1.initialize("c:\intel\projects\fpga\decision_tree_nsl_kdd\vhdl\testbench\data\test_file_1.csv");
csv_file_2.initialize("c:\intel\projects\fpga\decision_tree_nsl_kdd\vhdl\testbench\data\test_file_2.csv");
puts("testing 1st line of the csv file: 1,abc,true,0.5,0110");
csv_file_1.readline;
read_integer := csv_file_1.read_integer;
read_string := csv_file_1.read_string;
read_boolean := csv_file_1.read_boolean;
read_real := csv_file_1.read_real;
assert_that("integer value read is 1", read_integer = 1);
assert_that("string value read is 'abc'", read_string(1 to 3) = "abc");
assert_that("boolean value read is 'true'", read_boolean = true);
assert_that("real value read is 0.5", read_real = 0.5);
assert_that("end of file was not reached", csv_file_1.end_of_file = false);
puts("testing 1st line of the 2nd csv file: 3,def,false,-0.5,0110");
csv_file_2.readline;
read_integer := csv_file_2.read_integer;
read_string := csv_file_2.read_string;
read_boolean := csv_file_2.read_boolean;
read_real := csv_file_2.read_real;
assert_that("integer value read is 3", read_integer = 3);
assert_that("string value read is 'def'", read_string(1 to 3) = "def");
assert_that("boolean value read is 'false'", read_boolean = false);
assert_that("real value read is -0.5", read_real = -0.5);
assert_that("end of file was not reached", csv_file_1.end_of_file = false);
puts("testing 2nd line of the csv file: 2,xyz,false,-1.0,0000");
csv_file_1.readline;
read_integer := csv_file_1.read_integer;
read_string := csv_file_1.read_string;
read_boolean := csv_file_1.read_boolean;
read_real := csv_file_1.read_real;
assert_that("integer value read is 2", read_integer = 2);
assert_that("string value read is 'xyz'", read_string(1 to 3) = "xyz");
assert_that("boolean value read is 'false'", read_boolean = false);
assert_that("real value read is -1.0", read_real = -1.0);
assert_that("end of file was reached", csv_file_1.end_of_file = true);
end;
begin
run_tests: process begin
puts("Starting testbench...");
read_test_files;
puts("End of testbench. All tests passed.");
finish;
end process;
end;
|
unlicense
|
hgunicamp/Mips8B
|
src_test/memory_test.vhdl
|
1
|
3820
|
-- Teste geral para a estrutura do Processador Mips8B
Library Ieee;
Use Ieee.Std_Logic_1164.all;
Use Ieee.Numeric_Std.all;
Entity memory_test is
Port(Clock_Mem: In Std_Logic;
MAddr: In Std_Logic_Vector(7 downto 0);
MCmd: In Std_Logic_Vector(1 downto 0);
MData: In Std_Logic_Vector(7 downto 0);
SData: Out Std_Logic_Vector(7 downto 0);
SCmdAccept: Out Std_Logic);
End Entity memory_test;
Architecture behave of memory_test is
Type Memory_Array is Array(Natural Range <>) of Std_Logic_Vector(7 downto 0);
Use Work.MIPS8B_Base.ocpIDLE_little;
Use Work.MIPS8B_Base.ocpWR_little;
Use Work.MIPS8B_Base.ocpRD_little;
Use Work.MIPS8B_Base.ocpNULL_little;
Use Work.MIPS8B_Base.ocpDVA_little;
Begin
Memory: Process
Variable int_SCmdAccept: Std_Logic;
Variable address: Unsigned(7 downto 0);
Variable mem_int: Memory_Array(0 to 255) := (
"00100000", "00000001", "00000000", "11001000",
"00100000", "00000010", "00000000", "10001001",
"00100000", "00000011", "00000000", "11001101",
"10100000", "00100010", "00000000", "00000000",
"00100000", "00100001", "00000000", "00000001",
"00100000", "01000010", "00000000", "11101111",
"00010000", "01100001", "00000000", "00000010",
"00010000", "00000000", "00000000", "11111100",
"00000000", "00000000", "00001000", "00100101",
"00100000", "00000110", "00000000", "11001000",
"00100000", "11000111", "00000000", "00000001",
"00100000", "00000101", "00000000", "11001101",
"00010000", "10100111", "00000000", "00001011",
"10000000", "11000011", "00000000", "00000000",
"10000000", "11100100", "00000000", "00000000",
"00000000", "10000011", "00010000", "00101010",
"00010000", "01000000", "00000000", "00000100",
"00100000", "00100001", "00000000", "00000001",
"10100000", "11000100", "00000000", "00000000",
"10100000", "11100011", "00000000", "00000000",
"00000000", "11100000", "00110000", "00100000",
"00100000", "11100111", "00000000", "00000001",
"00010000", "00000000", "00000000", "11110110",
"00010000", "00000001", "00000000", "00000010",
"00010000", "00000000", "00000000", "11110000",
"00100000", "00000011", "00000000", "11001101",
"00100000", "00000001", "00000000", "11001000",
"10000000", "00100010", "00000000", "00000000",
"10100000", "00100010", "00000000", "00000000",
"00100000", "00100001", "00000000", "00000001",
"00010000", "01100001", "00000000", "11111100",
"00010000", "00000000", "00000000", "11111100",
Others => "00000000");
Begin
Wait Until Clock_Mem'Event and Clock_Mem='1';
Case MCmd is
When ocpWR_little =>
If int_SCmdAccept = ocpNULL_little then
int_SCmdAccept := ocpDVA_little;
address := Unsigned(MAddr);
mem_int(to_integer(address)) := MData;
Else
int_SCmdAccept := ocpNULL_little;
End If;
When ocpRD_little =>
If int_SCmdAccept = ocpNULL_little then
int_SCmdAccept := ocpDVA_little;
address := Unsigned(MAddr);
SData <= mem_int(to_integer(address));
Else
int_SCmdAccept := ocpNULL_little;
End If;
When Others =>
int_SCmdAccept := ocpNULL_little;
End Case;
SCmdAccept <= int_SCmdAccept;
End Process Memory;
End Architecture behave;
Configuration general_test of memory_test is
For behave
End For;
End Configuration general_test;
|
unlicense
|
ricardo-jasinski/vhdl-bit-matrix-lib
|
testbenches/tbu_bdd_pkg.vhd
|
1
|
657
|
use work.tbu_text_out_pkg.all;
-- Routines to help write testbenches at a higher level of abstraction (BDD)
package tbu_bdd_pkg is
procedure describe(function_name: string);
procedure should(msg: string; expr: boolean);
procedure done;
end;
package body tbu_bdd_pkg is
procedure describe(function_name: string) is begin
put("Function " & function_name & " should:");
end;
procedure should(msg: string; expr: boolean) is begin
assert expr report "error in test case '" & msg & "'" severity failure;
put("- " & msg);
end;
procedure done is begin
wait;
end;
end;
|
unlicense
|
jza00425/SingleCycleARM
|
lab2/work/arm_barrel_shift/_primary.vhd
|
3
|
509
|
library verilog;
use verilog.vl_types.all;
entity arm_barrel_shift is
port(
inst : in vl_logic_vector(31 downto 0);
rm_data_in : in vl_logic_vector(31 downto 0);
rs_data_in : in vl_logic_vector(31 downto 0);
cpsr : in vl_logic_vector(31 downto 0);
is_imm : in vl_logic;
operand2 : out vl_logic_vector(31 downto 0);
potential_cout : out vl_logic
);
end arm_barrel_shift;
|
unlicense
|
jza00425/SingleCycleARM
|
lab2/outputs/1108-121610/sim/work/arm_barrel_shift/_primary.vhd
|
3
|
509
|
library verilog;
use verilog.vl_types.all;
entity arm_barrel_shift is
port(
inst : in vl_logic_vector(31 downto 0);
rm_data_in : in vl_logic_vector(31 downto 0);
rs_data_in : in vl_logic_vector(31 downto 0);
cpsr : in vl_logic_vector(31 downto 0);
is_imm : in vl_logic;
operand2 : out vl_logic_vector(31 downto 0);
potential_cout : out vl_logic
);
end arm_barrel_shift;
|
unlicense
|
jza00425/SingleCycleARM
|
lab2/outputs/1108-121610/sim/work/regfile/_primary.vhd
|
4
|
1165
|
library verilog;
use verilog.vl_types.all;
entity regfile is
generic(
text_start : integer := 4194304
);
port(
rn_data : out vl_logic_vector(31 downto 0);
rm_data : out vl_logic_vector(31 downto 0);
rs_data : out vl_logic_vector(31 downto 0);
pc_out : out vl_logic_vector(31 downto 0);
cpsr_out : out vl_logic_vector(31 downto 0);
rn_num : in vl_logic_vector(3 downto 0);
rm_num : in vl_logic_vector(3 downto 0);
rs_num : in vl_logic_vector(3 downto 0);
rd_num : in vl_logic_vector(3 downto 0);
rd_data : in vl_logic_vector(31 downto 0);
rd_we : in vl_logic;
pc_in : in vl_logic_vector(31 downto 0);
pc_we : in vl_logic;
cpsr_in : in vl_logic_vector(31 downto 0);
cpsr_we : in vl_logic;
clk : in vl_logic;
rst_b : in vl_logic;
halted : in vl_logic
);
end regfile;
|
unlicense
|
krabo0om/pauloBlaze
|
testbench/tb_lockstep.vhd
|
2
|
7835
|
-- EMACS settings: -*- tab-width: 4; indent-tabs-mode: t -*-
-- vim: tabstop=4:shiftwidth=4:noexpandtab
-- kate: tab-width 4; replace-tabs off; indent-width 4;
--
-- =============================================================================
-- Authors: Paul Genssler
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- =============================================================================
-- Copyright 2007-2019 Paul Genssler - Germany
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS is" BASIS,
-- WITHOUT WARRANTIES or CONDITIONS of ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
use ieee.math_real.all;
use work.op_codes.all;
ENTITY tb_lockstep IS
END tb_lockstep;
ARCHITECTURE behavior OF tb_lockstep IS
--Inputs
signal clk : std_logic := '0';
signal clk_5ns_delayed : std_logic := '0';
signal clk_5ns_enable : std_logic := '0';
signal reset : std_logic := '0';
signal sleep : std_logic := '0';
signal instruction : std_logic_vector(17 downto 0) := (others => '0');
signal in_port : std_logic_vector(7 downto 0) := (others => '0');
signal in_port_del : std_logic_vector(7 downto 0) := (others => '0');
signal interrupt : std_logic := '0';
--Outputs
signal address : std_logic_vector(11 downto 0);
signal bram_enable : std_logic;
signal out_port : std_logic_vector(7 downto 0);
signal port_id : std_logic_vector(7 downto 0);
signal write_strobe : std_logic;
signal k_write_strobe : std_logic;
signal read_strobe : std_logic;
signal interrupt_ack : std_logic;
-- PicoBlaze Outputs
signal pico_address : std_logic_vector(11 downto 0);
signal pico_instruction : std_logic_vector(17 downto 0) := (others => '0');
signal pico_bram_enable : std_logic;
signal pico_out_port : std_logic_vector(7 downto 0);
signal pico_port_id : std_logic_vector(7 downto 0);
signal pico_write_strobe : std_logic;
signal pico_k_write_strobe : std_logic;
signal pico_read_strobe : std_logic;
signal pico_interrupt_ack : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
type io_data is array (0 to 4) of unsigned(7 downto 0);
signal data : io_data := (x"00", x"AB", x"CD", x"12", x"00");
signal prog_mem_en : std_logic;
signal done : std_logic;
signal pico_done : std_logic;
signal sleep_en : std_logic := '1';
signal inter_en : std_logic := '1';
signal reset_en : std_logic := '1';
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: entity work.pauloBlaze
generic map (
debug => true,
interrupt_vector => x"300",
hwbuild => x"41",
scratch_pad_memory_size => 64 )
PORT MAP (
-- clk => clk_5ns_delayed,
clk => clk,
reset => reset,
sleep => sleep,
address => address,
instruction => instruction,
bram_enable => bram_enable,
in_port => in_port,
out_port => out_port,
port_id => port_id,
write_strobe => write_strobe,
k_write_strobe => k_write_strobe,
read_strobe => read_strobe,
interrupt => interrupt,
interrupt_ack => interrupt_ack );
-- end port map
picoblaze: entity work.kcpsm6
generic map ( hwbuild => X"41",
interrupt_vector => X"300",
scratch_pad_memory_size => 64)
port map( address => pico_address,
instruction => pico_instruction,
bram_enable => pico_bram_enable,
port_id => pico_port_id,
write_strobe => pico_write_strobe,
k_write_strobe => pico_k_write_strobe,
out_port => pico_out_port,
read_strobe => pico_read_strobe,
in_port => in_port,
interrupt => interrupt,
interrupt_ack => pico_interrupt_ack,
sleep => sleep,
reset => reset,
clk => clk);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
sleeping : process begin
if (sleep_en = '1') then
wait for 1035 ns;
sleep <= '1';
wait for 1 * clk_period;
sleep <= '0';
wait for 5000 ns;
sleep <= '1';
wait for 7 * clk_period;
sleep <= '0';
end if;
wait;
end process sleeping;
inter_static : process
begin
if (inter_en = '1') then
wait for 490 ns;
interrupt <= '1';
wait for 3 * clk_period;
interrupt <= '0';
wait for 875 ns;
interrupt <= '1';
wait until interrupt_ack = '1';
interrupt <= '0';
end if;
wait;
end process inter_static;
prog_mem : entity work.code_loader
Port map (
address => address,
instruction => instruction,
enable => bram_enable,
done => done,
rdl => open,
clk => clk);
prog_mem_pico : entity work.code_loader
Port map (
address => pico_address,
instruction => pico_instruction,
enable => pico_bram_enable,
done => pico_done,
rdl => open,
clk => clk);
reset_proc: process
begin
reset <= '1';
wait until (done = '1' and pico_done = '1');
wait until clk = '0';
reset <= '0';
if (reset_en = '1') then
wait for 465 ns;
reset <= '1';
wait for 86 ns;
reset <= '0';
end if;
wait for 1337 ns;
wait until rising_edge(clk);
if (reset_en = '1') then
wait for 85 ns;
reset <= '1';
wait for 35 ns;
reset <= '0';
end if;
wait;
end process;
process begin
wait for 20 ns;
in_port <= in_port_del;
end process;
data_in_proc : process (port_id) begin
case (port_id) is
when x"05" =>
in_port_del <= x"F3";
when others =>
in_port_del <= port_id;
end case;
end process data_in_proc;
compare_process: process begin
wait until reset = '0';
loop
wait until rising_edge(clk);
wait until rising_edge(clk);
assert pico_address = address report "address is different" severity error;
assert pico_bram_enable = bram_enable report "bram_enable is different" severity error;
assert pico_write_strobe = write_strobe report "write_strobe is different" severity error;
assert pico_k_write_strobe = k_write_strobe report "k_write_strobe is different" severity error;
if (pico_write_strobe = '1' or write_strobe = '1' or
pico_k_write_strobe = '1' or k_write_strobe = '1' ) then
assert pico_out_port = out_port report "out_port is different" severity error;
if (pico_k_write_strobe = '1' or k_write_strobe = '1' ) then
assert pico_port_id(3 downto 0) = port_id(3 downto 0) report "port_id is different" severity error;
else
assert pico_port_id = port_id report "port_id is different" severity error;
end if;
end if;
assert pico_read_strobe = read_strobe report "read_strobe is different" severity error;
assert pico_interrupt_ack = interrupt_ack report "interrupt_ack is different" severity error;
end loop;
end process;
END;
|
apache-2.0
|
krabo0om/pauloBlaze
|
sources/regFile.vhd
|
2
|
3984
|
-- EMACS settings: -*- tab-width: 4; indent-tabs-mode: t -*-
-- vim: tabstop=4:shiftwidth=4:noexpandtab
-- kate: tab-width 4; replace-tabs off; indent-width 4;
--
-- =============================================================================
-- Authors: Paul Genssler
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Paul Genssler - Dresden, Germany
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS is" BASIS,
-- WITHOUT WARRANTIES or CONDITIONS of ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.op_codes.all;
entity reg_file is
generic (
debug : boolean := false;
scratch_pad_memory_size : integer := 64
);
port (
clk : in std_logic;
value : in unsigned (7 downto 0);
write_en : in std_logic;
reg0 : out unsigned (7 downto 0);
reg1 : out unsigned (7 downto 0);
reg_address : in unsigned (7 downto 0);
reg_select : in std_logic;
reg_star : in std_logic;
spm_addr_ss : in unsigned (7 downto 0);
spm_ss : in std_logic; -- 0: spm_addr = reg1, 1: spm_addr = spm_addr_ss
spm_we : in std_logic;
spm_rd : in std_logic
);
end reg_file;
architecture Behavioral of reg_file is
-- Logarithms: log*ceil*
-- From PoC-Library https://github.com/VLSI-EDA/PoC
-- ==========================================================================
function log2ceil(arg : positive) return natural is
variable tmp : positive := 1;
variable log : natural := 0;
begin
if arg = 1 then return 0; end if;
while arg > tmp loop
tmp := tmp * 2;
log := log + 1;
end loop;
return log;
end function;
type reg_file_t is array (31 downto 0) of unsigned(7 downto 0);
signal reg : reg_file_t := (others=>(others=>'0'));
type scratchpad_t is array(integer range <>) of unsigned(7 downto 0);
signal scratchpad : scratchpad_t((scratch_pad_memory_size-1) downto 0) := (others=>(others=>'0'));
constant spm_addr_width : integer := log2ceil(scratch_pad_memory_size); -- address failsafes into a truncated one
signal spm_addr : unsigned ( spm_addr_width-1 downto 0);
signal spm_read : unsigned (7 downto 0);
signal reg0_buf : unsigned ( 7 downto 0);
signal reg0_o : unsigned ( 7 downto 0);
signal reg1_buf : unsigned ( 7 downto 0);
signal reg1_o : unsigned ( 7 downto 0);
signal reg_wr_data : unsigned ( 7 downto 0);
begin
reg0 <= reg0_o;
reg1 <= reg1_o;
reg_wr_data <= spm_read when spm_rd = '1' else value when reg_star = '0' else reg1_buf;
spm_addr <= spm_addr_ss(spm_addr_width -1 downto 0) when spm_ss = '1' else reg1_buf(spm_addr_width -1 downto 0);
spm_read <= scratchpad(to_integer(spm_addr));
reg0_o <= reg(to_integer(reg_select & reg_address(7 downto 4)));
reg1_o <= reg(to_integer(reg_select & reg_address(3 downto 0)));
write_reg : process (clk) begin
if rising_edge(clk) then
if (write_en = '1') then
reg(to_integer(reg_select & reg_address(7 downto 4))) <= reg_wr_data;
end if;
end if;
end process write_reg;
write_spm : process (clk) begin
if rising_edge(clk) then
if (spm_we = '1') then
scratchpad(to_integer(spm_addr)) <= reg0_buf;
end if;
end if;
end process write_spm;
buf_reg0_p : process (clk) begin
if rising_edge(clk) then
reg0_buf <= reg0_o;
reg1_buf <= reg1_o;
end if;
end process buf_reg0_p;
end Behavioral;
|
apache-2.0
|
krabo0om/pauloBlaze
|
sources/program_counter.vhd
|
2
|
4197
|
-- EMACS settings: -*- tab-width: 4; indent-tabs-mode: t -*-
-- vim: tabstop=4:shiftwidth=4:noexpandtab
-- kate: tab-width 4; replace-tabs off; indent-width 4;
--
-- =============================================================================
-- Authors: Paul Genssler
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Paul Genssler - Dresden, Germany
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS is" BASIS,
-- WITHOUT WARRANTIES or CONDITIONS of ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity program_counter is
generic (
interrupt_vector : unsigned(11 downto 0) := X"3FF";
stack_depth : positive := 30
);
Port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
rst_req : out std_logic;
bram_pause : in STD_LOGIC;
call : in STD_LOGIC;
ret : in std_logic;
inter_j : in std_logic;
jump : in STD_LOGIC;
jmp_addr : in unsigned (11 downto 0);
address : out unsigned (11 downto 0));
end program_counter;
architecture Behavioral of program_counter is
-- Logarithms: log*ceil*
-- From PoC-Library https://github.com/VLSI-EDA/PoC
-- ==========================================================================
function log2ceil(arg : positive) return natural is
variable tmp : positive := 1;
variable log : natural := 0;
begin
if arg = 1 then return 0; end if;
while arg > tmp loop
tmp := tmp * 2;
log := log + 1;
end loop;
return log;
end function;
type stack_t is array (stack_depth-1 downto 0) of unsigned(11 downto 0);
signal stack : stack_t := (others => (others => '0'));
signal pointer : unsigned (log2ceil(stack_depth+1)-1 downto 0);
signal counter : unsigned (12 downto 0);
signal jmp_int : std_logic;
signal jmp_done : std_logic;
signal addr_o : unsigned (11 downto 0);
begin
jmp_int <= jump or call or inter_j;
address <= interrupt_vector when inter_j = '1' else addr_o ;
clken : process (clk)
variable p : unsigned(pointer'left+1 downto 0);
variable addr_next : unsigned (11 downto 0);
begin
if (rising_edge(clk)) then
if (reset = '1') then
counter <= x"001" & '0';
addr_o <= (others => '0');
jmp_done <= '0';
pointer <= (others => '0');
rst_req <= '0';
else
if (bram_pause = '1') then
-- counter <= addr_o & '1';
jmp_done <= jmp_done;
-- addr_o <= counter(12 downto 1);
elsif (ret = '1' and jmp_done <= '0') then
p := ('0' & pointer) - 1;
if (p = (p'range => '1')) then
rst_req <= '1';
else
pointer <= p(pointer'range);
addr_next := stack(to_integer(p));
counter <= addr_next & '1';
addr_o <= addr_next;
jmp_done <= '1';
end if;
elsif (inter_j = '1') then
p := ('0' & pointer) + 1;
if (p > stack_depth) then
rst_req <= '1';
else
stack(to_integer(pointer)) <= addr_o-1;
pointer <= p(pointer'range);
counter <= (interrupt_vector & '1') + ("" & '1');
addr_o <= interrupt_vector;
jmp_done <= '1';
end if;
elsif (jmp_int = '1' and jmp_done <= '0') then
if (call = '1') then
p := ('0' & pointer) +1;
if (p > stack_depth) then
rst_req <= '1';
else
stack(to_integer(pointer)) <= addr_o+1;
pointer <= p(pointer'range);
end if;
end if;
counter <= jmp_addr & '1';
addr_o <= jmp_addr;
jmp_done <= '1';
else
jmp_done <= '0';
counter <= counter + 1;
addr_o <= counter(12 downto 1);
end if;
end if;
end if;
end process clken;
end Behavioral;
|
apache-2.0
|
krabo0om/pauloBlaze
|
sources/alu.vhd
|
2
|
8026
|
-- EMACS settings: -*- tab-width: 4; indent-tabs-mode: t -*-
-- vim: tabstop=4:shiftwidth=4:noexpandtab
-- kate: tab-width 4; replace-tabs off; indent-width 4;
--
-- =============================================================================
-- Authors: Paul Genssler
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Paul Genssler - Dresden, Germany
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS is" BASIS,
-- WITHOUT WARRANTIES or CONDITIONS of ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.op_codes.all;
entity ALU is
generic (
debug : boolean := false;
hwbuild : unsigned(7 downto 0) := X"41"
);
port (
clk : in STD_LOGIC;
clk2 : in STD_LOGIC;
reset : in STD_LOGIC;
sleep_int : in STD_LOGIC;
opcode : in unsigned (5 downto 0);
opB : in unsigned (7 downto 0);
preserve_flags : in std_logic;
restore_flags : in std_logic;
carry : out STD_LOGIC;
zero : out STD_LOGIC;
reg_value : out unsigned (7 downto 0);
reg_we : out std_logic;
reg_reg0 : in unsigned (7 downto 0);
reg_reg1 : in unsigned (7 downto 0)
);
end ALU;
architecture Behavioral of ALU is
signal result : unsigned(7 downto 0);
signal res_valid : std_logic; -- result should be written to register
signal inter_flank : std_logic;
signal carry_c : std_logic;
signal carry_o : std_logic;
signal carry_i : std_logic; -- saved during interrupt
signal zero_i : std_logic; -- same
signal zero_c : std_logic;
signal zero_o : std_logic;
signal debug_opA_value : unsigned(7 downto 0);
signal debug_opB_value : unsigned(7 downto 0);
begin
process (clk)
begin
if rising_edge(clk) then
reg_value <= result;
reg_we <= not clk2 and res_valid and not sleep_int;
end if;
end process;
carry <= carry_o;
zero <= zero_o;
op : process (reset, opcode, opB, carry_o, zero_o, reg_reg0, reg_reg1, clk2)
variable opB_value : unsigned(7 downto 0);
variable opA_value : unsigned(7 downto 0);
variable result_v : unsigned(8 downto 0);
variable parity_v : std_logic;
variable padding : std_logic;
variable tmp : std_logic;
begin
opA_value := reg_reg0;
if (opcode (0) = '0') then -- LSB 0 = op_x sx, sy
opB_value := reg_reg1;
else -- LSB 1 = op_x sx, kk
opB_value := opB;
end if;
if (debug) then
padding := '0'; --looks better during simulation
debug_opA_value <= opA_value;
debug_opB_value <= opB_value;
else
padding := '-';
end if;
res_valid <= '0';
carry_c <= carry_o;
zero_c <= zero_o;
result_v := (others => padding);
parity_v := '0';
if (reset = '0') then
case opcode is
--register loading
when OP_LOAD_SX_SY | OP_LOAD_SX_KK | OP_LOADRETURN_SX_KK =>
result_v := padding & opB_value;
res_valid <= '1';
when OP_STAR_SX_SY =>
--Logical
when OP_AND_SX_SY | OP_AND_SX_KK =>
result_v := padding & (opA_value and opB_value);
res_valid <= '1';
if (result_v(7 downto 0) = "00000000") then
zero_c <= '1';
else
zero_c <= '0';
end if;
carry_c <= '0';
when OP_OR_SX_SY | OP_OR_SX_KK =>
result_v := padding & (opA_value or opB_value);
res_valid <= '1';
if (result_v(7 downto 0) = "00000000") then
zero_c <= '1';
else
zero_c <= '0';
end if;
carry_c <= '0';
when OP_XOR_SX_SY | OP_XOR_SX_KK =>
result_v := padding & (opA_value xor opB_value);
res_valid <= '1';
if (result_v(7 downto 0) = "00000000") then
zero_c <= '1';
else
zero_c <= '0';
end if;
carry_c <= '0';
--Arithmetic
when OP_ADD_SX_SY | OP_ADD_SX_KK | OP_SUB_SX_SY | OP_SUB_SX_KK |
OP_ADDCY_SX_SY | OP_ADDCY_SX_KK | OP_SUBCY_SX_SY | OP_SUBCY_SX_KK =>
if (opcode(3) = '0') then
result_v := ('0' & opA_value) + ('0' & opB_value) + ("" & (carry_o and opCode(1)));
else
result_v := ('0' & opA_value) - ('0' & opB_value) - ("" & (carry_o and opCode(1)));
end if;
if (result_v(7 downto 0) = "00000000") then
if (opcode = OP_ADDCY_SX_SY or opcode = OP_ADDCY_SX_KK or opcode = OP_SUBCY_SX_SY or opcode = OP_SUBCY_SX_KK) then
zero_c <= zero_o;
else
zero_c <= '1';
end if;
else
zero_c <= '0';
end if;
carry_c <= result_v(8);
res_valid <= '1';
--Test and Compare
when OP_TEST_SX_SY | OP_TEST_SX_KK | OP_TESTCY_SX_SY | OP_TESTCY_SX_KK =>
result_v := (padding & (opA_value and opB_value));
-- opCode(1) == 0 : TEST
-- opCode(1) == 1 : TESTCY
if (result_v(7 downto 0) = "00000000") then
if (opCode(1) = '0') then
zero_c <= '1';
else
zero_c <= zero_o;
end if;
else
zero_c <= '0';
end if;
for i in 0 to 7 loop
parity_v := parity_v xor result_v(i);
end loop;
if (opCode(1) = '0') then
-- TEST
carry_c <= parity_v;
else
-- TESTCY
carry_c <= parity_v xor carry_o;
end if;
when OP_COMPARE_SX_SY | OP_COMPARE_SX_KK | OP_COMPARECY_SX_SY | OP_COMPARECY_SX_KK =>
-- opCode(1) == 0 : COMAPRE
-- opCode(1) == 1 : COMAPRECY
-- mask carry with it
result_v := ('0' & opA_value) - ('0' & opB_value) - ("" & (opCode(1) and carry_o));
if (result_v(7 downto 0) = "00000000") then
if (opCode(1) = '0') then
zero_c <= '1';
else
zero_c <= zero_o;
end if;
else
zero_c <= '0';
end if;
carry_c <= result_v(8);
--Shift and Rotate ... and hwbuild OP_HWBUILD_SX
when OP_SL0_SX =>
if (opB(7) = '1') then -- hw build op
result_v := padding & hwbuild;
res_valid <= '1';
carry_c <= '1';
if (result_v(7 downto 0) = "00000000") then
zero_c <= '1';
else
zero_c <= '0';
end if;
else
-- shift and rotate
case opB(2 downto 0) is
when "110" | "111" =>
tmp := opB(0);
when "010" => -- RL
tmp := opA_value(7);
when "100" => -- RR
tmp := opA_value(0);
when "000" =>
tmp := carry_o;
when others =>
tmp := '0';
end case;
if (opB(3) = '1') then
result_v := opA_value(0) & tmp & opA_value(7 downto 1);
else -- concat the carry value into the result and shift
result_v := opA_value(7) & opA_value(6 downto 0) & tmp;
end if;
carry_c <= result_v(8);
if (result_v(7 downto 0) = "00000000") then
zero_c <= '1';
else
zero_c <= '0';
end if;
res_valid <= '1';
end if;
when others =>
result_v := (others => padding);
end case;
end if;
result <= result_v(7 downto 0);
end process;
flags : process (clk) begin
if (rising_edge(clk)) then
if (reset = '1') then
carry_o <= '0';
zero_o <= '0';
carry_i <= '0';
zero_i <= '0';
else
if (preserve_flags = '1') then
-- preserve flags
carry_i <= carry_o;
zero_i <= zero_o;
end if;
if (restore_flags = '1') then
-- restore flags
carry_o <= carry_i;
zero_o <= zero_i;
elsif (clk2 = '1') then
carry_o <= carry_c;
zero_o <= zero_c;
else
carry_o <= carry_o;
zero_o <= zero_o;
end if;
end if;
end if;
end process flags;
end Behavioral;
|
apache-2.0
|
kumasento/zedboard-thesis
|
examples/2014_zynq_labs/lab3/lab3.srcs/sources_1/bd/system/ip/system_axi_gpio_0_0/sim/system_axi_gpio_0_0.vhd
|
1
|
8743
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
-- IP Revision: 7
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_gpio_v2_0;
USE axi_gpio_v2_0.axi_gpio;
ENTITY system_axi_gpio_0_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END system_axi_gpio_0_0;
ARCHITECTURE system_axi_gpio_0_0_arch OF system_axi_gpio_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_axi_gpio_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_gpio IS
GENERIC (
C_FAMILY : STRING;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_GPIO_WIDTH : INTEGER;
C_GPIO2_WIDTH : INTEGER;
C_ALL_INPUTS : INTEGER;
C_ALL_INPUTS_2 : INTEGER;
C_ALL_OUTPUTS : INTEGER;
C_ALL_OUTPUTS_2 : INTEGER;
C_INTERRUPT_PRESENT : INTEGER;
C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_IS_DUAL : INTEGER;
C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0)
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
gpio2_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_gpio;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_I";
BEGIN
U0 : axi_gpio
GENERIC MAP (
C_FAMILY => "zynq",
C_S_AXI_ADDR_WIDTH => 9,
C_S_AXI_DATA_WIDTH => 32,
C_GPIO_WIDTH => 8,
C_GPIO2_WIDTH => 32,
C_ALL_INPUTS => 1,
C_ALL_INPUTS_2 => 0,
C_ALL_OUTPUTS => 0,
C_ALL_OUTPUTS_2 => 0,
C_INTERRUPT_PRESENT => 0,
C_DOUT_DEFAULT => X"00000000",
C_TRI_DEFAULT => X"FFFFFFFF",
C_IS_DUAL => 0,
C_DOUT_DEFAULT_2 => X"00000000",
C_TRI_DEFAULT_2 => X"FFFFFFFF"
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
gpio_io_i => gpio_io_i,
gpio2_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32))
);
END system_axi_gpio_0_0_arch;
|
apache-2.0
|
Fju/LeafySan
|
src/modelsim/uart_testbench.vhd
|
1
|
10709
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.standard.all;
use std.textio.all;
use std.env.all;
library work;
use work.iac_pkg.all;
entity uart_testbench is
end uart_testbench;
architecture sim of uart_testbench is
constant SYSTEM_CYCLE_TIME : time := 20 ns; -- 50MHz
constant SIMULATION_TIME : time := 100000 * SYSTEM_CYCLE_TIME;
constant UART_WR_BYTE_COUNT : natural := 13;
constant UART_RD_BYTE_COUNT : natural := 9;
constant UART_DATA_WIDTH : natural := 6; -- 6-bits
signal clock, reset_n, reset : std_ulogic;
-- UART registers
signal uart_sent_bytes, uart_sent_bytes_nxt : unsigned(to_log2(UART_WR_BYTE_COUNT) - 1 downto 0);
signal uart_received_bytes, uart_received_bytes_nxt : unsigned(to_log2(UART_RD_BYTE_COUNT) - 1 downto 0);
type uart_protocol_entry_t is record
cmd : std_ulogic_vector(1 downto 0);
data : std_ulogic_vector(5 downto 0);
end record;
type uart_protocol_array is array (natural range <>) of uart_protocol_entry_t;
signal uart_wr_array, uart_wr_array_nxt : uart_protocol_array(0 to UART_WR_BYTE_COUNT - 1);
signal uart_rd_array, uart_rd_array_nxt : uart_protocol_array(0 to UART_RD_BYTE_COUNT);
type uart_state_t is (S_UART_RD_WAIT_START, S_UART_RD_READ_LOOP, S_UART_WR_START, S_UART_WR_WRITE_LOOP, S_UART_WR_END);
signal uart_state, uart_state_nxt : uart_state_t;
signal uart_cs : std_ulogic;
signal uart_wr : std_ulogic;
signal uart_addr : std_ulogic_vector(CW_ADDR_UART-1 downto 0);
signal uart_din : std_ulogic_vector(CW_DATA_UART-1 downto 0);
signal uart_dout : std_ulogic_vector(CW_DATA_UART-1 downto 0);
signal uart_irq_rx : std_ulogic;
signal uart_irq_tx : std_ulogic;
signal uart_ack_rx : std_ulogic;
signal uart_ack_tx : std_ulogic;
signal uart_rts, uart_cts, uart_rxd, uart_txd : std_ulogic;
signal end_simulation : std_ulogic;
signal heating_thresh, heating_thresh_nxt : unsigned(11 downto 0);
signal lighting_thresh, lighting_thresh_nxt : unsigned(15 downto 0);
signal watering_thresh, watering_thresh_nxt : unsigned(15 downto 0);
component uart is
generic (
SIMULATION : boolean := true
);
port (
-- global signals
clock : in std_ulogic;
reset_n : in std_ulogic;
-- bus interface
iobus_cs : in std_ulogic;
iobus_wr : in std_ulogic;
iobus_addr : in std_ulogic_vector(CW_ADDR_UART-1 downto 0);
iobus_din : in std_ulogic_vector(CW_DATA_UART-1 downto 0);
iobus_dout : out std_ulogic_vector(CW_DATA_UART-1 downto 0);
-- IRQ handling
iobus_irq_rx : out std_ulogic;
iobus_irq_tx : out std_ulogic;
iobus_ack_rx : in std_ulogic;
iobus_ack_tx : in std_ulogic;
-- pins to outside
rts : in std_ulogic;
cts : out std_ulogic;
rxd : in std_ulogic;
txd : out std_ulogic
);
end component uart;
component uart_model is
generic (
SYSTEM_CYCLE_TIME : time;
FILE_NAME_COMMAND : string;
FILE_NAME_DUMP : string;
BAUD_RATE : natural;
SIMULATION : boolean
);
port (
end_simulation : in std_ulogic;
rx : in std_ulogic;
tx : out std_ulogic
);
end component uart_model;
begin
uart_inst : uart
generic map (
SIMULATION => true
)
port map (
-- global signals
clock => clock,
reset_n => reset_n,
-- bus interface
iobus_cs => uart_cs,
iobus_wr => uart_wr,
iobus_addr => uart_addr,
iobus_din => uart_dout, -- caution!
iobus_dout => uart_din, -- caution!
-- IRQ handling
iobus_irq_rx => uart_irq_rx,
iobus_irq_tx => uart_irq_tx,
iobus_ack_rx => uart_ack_rx,
iobus_ack_tx => uart_ack_tx,
-- pins to outside
rts => uart_rts,
cts => uart_cts,
rxd => uart_rxd,
txd => uart_txd
);
uart_model_inst : uart_model
generic map (
SYSTEM_CYCLE_TIME => SYSTEM_CYCLE_TIME,
FILE_NAME_COMMAND => "uart_command.txt",
FILE_NAME_DUMP => "uart_dump.txt",
BAUD_RATE => CV_UART_BAUDRATE,
SIMULATION => true
)
port map (
end_simulation => end_simulation,
rx => uart_txd,
tx => uart_rxd
);
reset <= not(reset_n);
clk : process
begin
clock <= '1';
wait for SYSTEM_CYCLE_TIME/2;
clock <= '0';
wait for SYSTEM_CYCLE_TIME/2;
end process clk;
rst : process
begin
reset_n <= '0';
wait for 2*SYSTEM_CYCLE_TIME;
reset_n <= '1';
wait;
end process rst;
end_sim : process
begin
end_simulation <= '0';
wait for SIMULATION_TIME;
end_simulation <= '1';
wait;
end process end_sim;
seq : process(clock, reset)
begin
if reset = '1' then
uart_state <= S_UART_RD_WAIT_START;
uart_wr_array <= (others => (others => (others => '0')));
uart_rd_array <= (others => (others => (others => '0')));
uart_sent_bytes <= (others => '0');
uart_received_bytes <= (others => '0');
heating_thresh <= to_unsigned(240, heating_thresh'length); -- 24,0 °C
lighting_thresh <= to_unsigned(400, lighting_thresh'length); -- 400 lx
watering_thresh <= to_unsigned(500, watering_thresh'length); -- 50,0 %
elsif rising_edge(clock) then
uart_state <= uart_state_nxt;
uart_wr_array <= uart_wr_array_nxt;
uart_rd_array <= uart_rd_array_nxt;
uart_sent_bytes <= uart_sent_bytes_nxt;
uart_received_bytes <= uart_received_bytes_nxt;
heating_thresh <= heating_thresh_nxt;
lighting_thresh <= lighting_thresh_nxt;
watering_thresh <= watering_thresh_nxt;
end if;
end process seq;
comb : process(uart_state, uart_wr_array, uart_rd_array, uart_sent_bytes, uart_received_bytes, uart_irq_tx, uart_irq_rx, uart_din, lighting_thresh, watering_thresh, heating_thresh)
constant VALUE_COUNT : natural := 5; -- amount of data segments (four segments for each sensor + one segment including all states (on/off) of peripherals)
constant SEGMENT_COUNT : natural := 3; -- 3 bytes per "segment"
variable i, j : natural := 0; -- loop variables
variable segment_cmd : std_ulogic_vector(1 downto 0);
variable segment_data : unsigned(SEGMENT_COUNT * UART_DATA_WIDTH - 1 downto 0);
variable item : uart_protocol_entry_t;
variable segment_value : std_ulogic_vector(15 downto 0);
begin
uart_cs <= '0';
uart_wr <= '0';
uart_addr <= (others => '0');
uart_dout <= (others => '0');
uart_ack_rx <= '0';
uart_ack_tx <= '0';
-- hold values
uart_state_nxt <= uart_state;
uart_sent_bytes_nxt <= uart_sent_bytes;
uart_received_bytes_nxt <= uart_received_bytes;
uart_rd_array_nxt <= uart_rd_array;
lighting_thresh_nxt <= lighting_thresh;
watering_thresh_nxt <= watering_thresh;
heating_thresh_nxt <= heating_thresh;
-- assign sensor values to protocol
for i in 0 to VALUE_COUNT - 1 loop
if i = 0 then
segment_cmd := "10";
segment_data := to_unsigned(150, segment_data'length - 2) & "00"; -- replace with lux
elsif i = 1 then
segment_cmd := "11";
segment_data := to_unsigned(300, segment_data'length - 2) & "01"; -- replace with moisture
elsif i = 2 then
segment_cmd := "10";
segment_data := to_unsigned(271, segment_data'length - 2) & "10"; -- replace with temp
elsif i = 3 then
segment_cmd := "11";
segment_data := to_unsigned(3000, segment_data'length - 2) & "11"; -- replace with co2
else
segment_cmd := "10";
segment_data := (others => '0'); -- replace with peripherals
end if;
for j in 0 to SEGMENT_COUNT - 1 loop
if i < 4 or j = 0 then
uart_wr_array_nxt(j + i * SEGMENT_COUNT) <= (
segment_cmd, -- cmd
std_ulogic_vector(resize(shift_right(segment_data, (2 - j) * UART_DATA_WIDTH), UART_DATA_WIDTH)) -- data
);
end if;
end loop;
end loop;
case uart_state is
when S_UART_RD_WAIT_START =>
if uart_irq_rx = '1' then
uart_cs <= '1';
uart_addr <= CV_ADDR_UART_DATA_RX;
uart_wr <= '0';
-- save data
if uart_din(7 downto 0) = "01000000" then
uart_received_bytes_nxt <= to_unsigned(0, uart_received_bytes'length);
uart_rd_array_nxt <= (others => (others => (others => '0')));
uart_state_nxt <= S_UART_RD_READ_LOOP;
end if;
end if;
when S_UART_RD_READ_LOOP =>
if uart_irq_rx = '1' then
uart_cs <= '1';
uart_addr <= CV_ADDR_UART_DATA_RX;
uart_wr <= '0';
-- increment counter
if uart_din(7 downto 0) = "00111111" then
-- received end command
if uart_received_bytes = to_unsigned(UART_RD_BYTE_COUNT, uart_received_bytes'length) then
for i in 0 to 2 loop
if uart_rd_array(i*3).cmd = "10" or uart_rd_array(i*3).cmd = "11" then
segment_value := uart_rd_array(i*3).data & uart_rd_array(i*3+1).data & uart_rd_array(i*3+2).data(5 downto 2);
if uart_rd_array(i*3+2).data(1 downto 0) = "00" then
lighting_thresh_nxt <= unsigned(segment_value);
elsif uart_rd_array(i*3+2).data(1 downto 0) = "01" then
watering_thresh_nxt <= unsigned(segment_value);
elsif uart_rd_array(i*3+2).data(1 downto 0) = "10" then
heating_thresh_nxt <= resize(unsigned(segment_value), heating_thresh'length);
end if;
end if;
end loop;
end if;
uart_state_nxt <= S_UART_WR_START;
else
uart_rd_array_nxt(to_integer(uart_received_bytes)) <= (
uart_din(7 downto 6), -- cmd
uart_din(5 downto 0) -- data
);
uart_received_bytes_nxt <= uart_received_bytes + to_unsigned(1, uart_received_bytes'length);
end if;
end if;
when S_UART_WR_START =>
if uart_irq_tx = '1' then
uart_cs <= '1';
uart_addr <= CV_ADDR_UART_DATA_TX;
uart_wr <= '1';
-- write `start` cmd
uart_dout(7 downto 0) <= "01000000";
--
uart_state_nxt <= S_UART_WR_WRITE_LOOP;
end if;
when S_UART_WR_WRITE_LOOP =>
if uart_irq_tx = '1' then
uart_cs <= '1';
uart_addr <= CV_ADDR_UART_DATA_TX;
uart_wr <= '1';
item := uart_wr_array(to_integer(uart_sent_bytes));
uart_dout(7 downto 0) <= item.cmd & item.data;
if uart_sent_bytes = to_unsigned(UART_WR_BYTE_COUNT - 1, uart_sent_bytes'length) then
-- last byte sent
uart_sent_bytes_nxt <= (others => '0'); -- reset counter
uart_state_nxt <= S_UART_WR_END;
else
-- increment counter
uart_sent_bytes_nxt <= uart_sent_bytes + to_unsigned(1, uart_sent_bytes'length);
end if;
end if;
when S_UART_WR_END =>
if uart_irq_tx = '1' then
uart_cs <= '1';
uart_addr <= CV_ADDR_UART_DATA_TX;
uart_wr <= '1';
-- write `end` cmd
uart_dout(7 downto 0) <= "00111111";
uart_state_nxt <= S_UART_RD_WAIT_START;
end if;
end case;
end process comb;
end sim;
|
apache-2.0
|
Fju/LeafySan
|
src/vhdl/testbench/adc_model.vhdl
|
1
|
4121
|
-----------------------------------------------------------------
-- Project : Invent a Chip
-- Module : ADC Model
-- Last update : 27.04.2015
-----------------------------------------------------------------
-- Libraries
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
entity adc_model is
generic(
SYSTEM_CYCLE_TIME : time := 20 ns; -- 50 MHz
FULL_DEBUG : natural := 0;
FILE_NAME_PRELOAD : string := "adc_preload.txt"
);
port(
-- Global Signals
end_simulation : in std_ulogic;
-- SPI Signals
spi_clk : in std_ulogic;
spi_miso : out std_logic;
spi_cs_n : in std_ulogic;
-- Switch Signals
swt_select : in std_ulogic_vector(2 downto 0);
swt_enable_n : in std_ulogic
);
end entity adc_model;
architecture sim of adc_model is
file file_preload : text open read_mode is FILE_NAME_PRELOAD;
type adc_reg_t is array (0 to 7) of std_ulogic_vector(15 downto 0);
signal tx : std_ulogic_vector(15 downto 0);
signal swt_sel_lut : std_ulogic_vector(2 downto 0);
begin
process
variable adc_reg : adc_reg_t;
variable active_line, out_line : line;
variable cnt : natural := 0;
variable neol : boolean := false;
variable adc_val : real := 0.000;
begin
adc_reg := (others => (others => 'U'));
tx <= (others => 'U');
-- force wait for 1 ps to display full-debug messages after library warnings
if FULL_DEBUG = 1 then
wait for 1 ps;
end if;
-- preload data from adc file here...
while not endfile(file_preload) loop
readline(file_preload, active_line);
loop
read(active_line, adc_val, neol);
exit when not neol;
exit when cnt = 8;
adc_reg(cnt) := std_ulogic_vector(to_unsigned(integer(adc_val*real(4096)/real(3.3)), tx'length));
-- display read values from file
if FULL_DEBUG = 1 then
write(out_line, "[ADC] Preloading channel " & integer'image(cnt) & " with ");
write(out_line, adc_val, right, 3, 3);
write(out_line, 'V');
writeline(output, out_line);
end if;
cnt := cnt + 1;
end loop;
exit when cnt = 8;
end loop;
file_close(file_preload);
-- display unassigned channels
if FULL_DEBUG = 1 then
if cnt < 8 then
for i in cnt to 7 loop
write(out_line, "[ADC] Channel " & integer'image(i) & " is unassigned!");
writeline(output, out_line);
end loop;
end if;
end if;
-- do real work (send adc-values by request)
loop
exit when end_simulation = '1';
if spi_cs_n = '0' then
if swt_enable_n = '0' then
-- data has to be sent out shifted one bit to the left (as in actual chip)
tx <= adc_reg(to_integer(unsigned(swt_sel_lut)))(14 downto 0) & '0';
else
tx <= (others => 'U');
end if;
for i in 0 to 15 loop
wait until spi_clk = '1';
wait until spi_clk = '0';
tx <= tx(14 downto 0) & '0';
end loop;
wait until spi_cs_n = '1';
else
wait for SYSTEM_CYCLE_TIME;
end if;
end loop;
wait;
end process;
spi_miso <= '0' when tx(15) = '0' AND spi_cs_n = '0' else 'Z';
-- lut to map swt_select to correct register content (inverse to interface)
process(swt_select)
variable sel : natural;
begin
sel := to_integer(unsigned(swt_select));
case sel is
when 0 => swt_sel_lut <= std_ulogic_vector(to_unsigned(5, swt_sel_lut'length));
when 1 => swt_sel_lut <= std_ulogic_vector(to_unsigned(3, swt_sel_lut'length));
when 2 => swt_sel_lut <= std_ulogic_vector(to_unsigned(1, swt_sel_lut'length));
when 3 => swt_sel_lut <= std_ulogic_vector(to_unsigned(7, swt_sel_lut'length));
when 4 => swt_sel_lut <= std_ulogic_vector(to_unsigned(6, swt_sel_lut'length));
when 5 => swt_sel_lut <= std_ulogic_vector(to_unsigned(2, swt_sel_lut'length));
when 6 => swt_sel_lut <= std_ulogic_vector(to_unsigned(4, swt_sel_lut'length));
when 7 => swt_sel_lut <= std_ulogic_vector(to_unsigned(0, swt_sel_lut'length));
when others => swt_sel_lut <= std_ulogic_vector(to_unsigned(5, swt_sel_lut'length));
end case;
end process;
end architecture sim;
|
apache-2.0
|
Fju/LeafySan
|
src/vhdl/examples/invent_a_chip_audio_adc_to_gain.vhdl
|
1
|
12897
|
----------------------------------------------------------------------
-- Project : Invent a Chip
-- Authors : Jan Dürre
-- Year : 2013
-- Description : This example uses adc-channel 0 as gain-control
-- for audio pass-through. Two independent FSMs are
-- required, since the lcd is too slow for 44,1kHz
-- sampling rate.
----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.iac_pkg.all;
entity invent_a_chip is
port (
-- Global Signals
clock : in std_ulogic;
reset : in std_ulogic;
-- Interface Signals
-- 7-Seg
sevenseg_cs : out std_ulogic;
sevenseg_wr : out std_ulogic;
sevenseg_addr : out std_ulogic_vector(CW_ADDR_SEVENSEG-1 downto 0);
sevenseg_din : in std_ulogic_vector(CW_DATA_SEVENSEG-1 downto 0);
sevenseg_dout : out std_ulogic_vector(CW_DATA_SEVENSEG-1 downto 0);
-- ADC/DAC
adc_dac_cs : out std_ulogic;
adc_dac_wr : out std_ulogic;
adc_dac_addr : out std_ulogic_vector(CW_ADDR_ADC_DAC-1 downto 0);
adc_dac_din : in std_ulogic_vector(CW_DATA_ADC_DAC-1 downto 0);
adc_dac_dout : out std_ulogic_vector(CW_DATA_ADC_DAC-1 downto 0);
-- AUDIO
audio_cs : out std_ulogic;
audio_wr : out std_ulogic;
audio_addr : out std_ulogic_vector(CW_ADDR_AUDIO-1 downto 0);
audio_din : in std_ulogic_vector(CW_DATA_AUDIO-1 downto 0);
audio_dout : out std_ulogic_vector(CW_DATA_AUDIO-1 downto 0);
audio_irq_left : in std_ulogic;
audio_irq_right : in std_ulogic;
audio_ack_left : out std_ulogic;
audio_ack_right : out std_ulogic;
-- Infra-red Receiver
ir_cs : out std_ulogic;
ir_wr : out std_ulogic;
ir_addr : out std_ulogic_vector(CW_ADDR_IR-1 downto 0);
ir_din : in std_ulogic_vector(CW_DATA_IR-1 downto 0);
ir_dout : out std_ulogic_vector(CW_DATA_IR-1 downto 0);
ir_irq_rx : in std_ulogic;
ir_ack_rx : out std_ulogic;
-- LCD
lcd_cs : out std_ulogic;
lcd_wr : out std_ulogic;
lcd_addr : out std_ulogic_vector(CW_ADDR_LCD-1 downto 0);
lcd_din : in std_ulogic_vector(CW_DATA_LCD-1 downto 0);
lcd_dout : out std_ulogic_vector(CW_DATA_LCD-1 downto 0);
lcd_irq_rdy : in std_ulogic;
lcd_ack_rdy : out std_ulogic;
-- SRAM
sram_cs : out std_ulogic;
sram_wr : out std_ulogic;
sram_addr : out std_ulogic_vector(CW_ADDR_SRAM-1 downto 0);
sram_din : in std_ulogic_vector(CW_DATA_SRAM-1 downto 0);
sram_dout : out std_ulogic_vector(CW_DATA_SRAM-1 downto 0);
-- UART
uart_cs : out std_ulogic;
uart_wr : out std_ulogic;
uart_addr : out std_ulogic_vector(CW_ADDR_UART-1 downto 0);
uart_din : in std_ulogic_vector(CW_DATA_UART-1 downto 0);
uart_dout : out std_ulogic_vector(CW_DATA_UART-1 downto 0);
uart_irq_rx : in std_ulogic;
uart_irq_tx : in std_ulogic;
uart_ack_rx : out std_ulogic;
uart_ack_tx : out std_ulogic;
-- GPIO
gp_ctrl : out std_ulogic_vector(15 downto 0);
gp_in : in std_ulogic_vector(15 downto 0);
gp_out : out std_ulogic_vector(15 downto 0);
-- LED/Switches/Keys
led_green : out std_ulogic_vector(8 downto 0);
led_red : out std_ulogic_vector(17 downto 0);
switch : in std_ulogic_vector(17 downto 0);
key : in std_ulogic_vector(2 downto 0)
);
end invent_a_chip;
architecture rtl of invent_a_chip is
-- state register for audio control
type state_audio_t is (S_INIT, S_WAIT_SAMPLE, S_ADC_READ, S_WRITE_SAMPLE_LEFT, S_WRITE_SAMPLE_RIGHT, S_WRITE_CONFIG);
signal state_audio, state_audio_nxt : state_audio_t;
-- state register for lcd control
type state_lcd_t is (S_WAIT_LCD, S_PRINT_CHARACTERS, S_WAIT_FOR_NEW_GAIN);
signal state_lcd, state_lcd_nxt : state_lcd_t;
-- register to save audio-sample
signal sample, sample_nxt : std_ulogic_vector(CW_AUDIO_SAMPLE-1 downto 0);
-- register to save adc-value
signal adc_value, adc_value_nxt : std_ulogic_vector(11 downto 0);
-- signals to communicate between fsms
signal lcd_refresh, lcd_refresh_nxt : std_ulogic;
signal lcd_refresh_ack : std_ulogic;
-- array of every single character to print out to the lcd
signal lcd_cmds, lcd_cmds_nxt : lcd_commands_t(0 to 12);
-- counter
signal char_count, char_count_nxt : unsigned(to_log2(lcd_cmds'length)-1 downto 0);
begin
-- sequential process
process(clock, reset)
begin
-- asynchronous reset
if reset = '1' then
state_audio <= S_INIT;
sample <= (others => '0');
adc_value <= (others => '0');
lcd_refresh <= '0';
state_lcd <= S_WAIT_LCD;
lcd_cmds <= lcd_cmd(lcd_cursor_pos(0, 0) & asciitext("Volume: XXX%"));
char_count <= (others => '0');
elsif rising_edge(clock) then
state_audio <= state_audio_nxt;
sample <= sample_nxt;
adc_value <= adc_value_nxt;
lcd_refresh <= lcd_refresh_nxt;
state_lcd <= state_lcd_nxt;
lcd_cmds <= lcd_cmds_nxt;
char_count <= char_count_nxt;
end if;
end process;
-- audio data-path (combinational process contains logic only)
process(state_audio, state_lcd, key, adc_dac_din, audio_din, audio_irq_left, audio_irq_right, lcd_refresh, lcd_refresh_ack, sample, adc_value, switch)
begin
-- default assignment
-- leds
led_green <= (others => '0');
-- adc/dac interface
adc_dac_cs <= '0';
adc_dac_wr <= '0';
adc_dac_addr <= (others => '0');
adc_dac_dout <= (others => '0');
-- audio interface
audio_cs <= '0';
audio_wr <= '0';
audio_addr <= (others => '0');
audio_dout <= (others => '0');
audio_ack_left <= '0';
audio_ack_right <= '0';
-- communication between fsms
lcd_refresh_nxt <= lcd_refresh;
-- hold previous values of all registers
state_audio_nxt <= state_audio;
sample_nxt <= sample;
adc_value_nxt <= adc_value;
-- reset lcd_refresh if lcd-fsm acks request
if lcd_refresh_ack = '1' then
lcd_refresh_nxt <= '0';
end if;
-- audio data-path
case state_audio is
-- initial state
when S_INIT =>
led_green(0) <= '1';
-- wait for key 0 to start work
if key(0) = '1' then
-- activate ADC channel 0
adc_dac_cs <= '1';
adc_dac_wr <= '1';
adc_dac_addr <= CV_ADDR_ADC_DAC_CTRL;
adc_dac_dout(9 downto 0) <= "0000000001";
-- next state
state_audio_nxt <= S_WAIT_SAMPLE;
end if;
-- wait for audio-interrupt signals to indicate new audio-sample
when S_WAIT_SAMPLE =>
led_green(1) <= '1';
-- new audio sample on left or right channel detected
if (audio_irq_left = '1') or (audio_irq_right = '1') then
-- start reading adc-value
state_audio_nxt <= S_ADC_READ;
end if;
-- read adc value
when S_ADC_READ =>
led_green(2) <= '1';
-- chip select for adc/dac-interface
adc_dac_cs <= '1';
-- read mode
adc_dac_wr <= '0';
-- address of adc-channel 0
adc_dac_addr <= CV_ADDR_ADC0;
-- if adc-value has changed:
if adc_dac_din(11 downto 0) /= adc_value then
-- save adc-value of selected channel to register
adc_value_nxt <= adc_dac_din(11 downto 0);
-- initiate rewrite of lcd display
lcd_refresh_nxt <= '1';
end if;
-- choose correct audio channel
if audio_irq_left = '1' then
-- chip select for audio-interface
audio_cs <= '1';
-- read mode
audio_wr <= '0';
-- acknowledge interrupt
audio_ack_left <= '1';
-- set address for left channel
audio_addr <= CV_ADDR_AUDIO_LEFT_IN;
-- save sample to register
sample_nxt <= audio_din;
-- next state
state_audio_nxt <= S_WRITE_SAMPLE_LEFT;
end if;
if audio_irq_right = '1' then
-- chip select for audio-interface
audio_cs <= '1';
-- read mode
audio_wr <= '0';
-- acknowledge interrupt
audio_ack_right <= '1';
-- set address for right channel
audio_addr <= CV_ADDR_AUDIO_RIGHT_IN;
-- save sample to register
sample_nxt <= audio_din;
-- next state
state_audio_nxt <= S_WRITE_SAMPLE_RIGHT;
end if;
-- write new sample to left channel
when S_WRITE_SAMPLE_LEFT =>
led_green(5) <= '1';
-- chip select for audio-interface
audio_cs <= '1';
-- write mode
audio_wr <= '1';
-- set address for left channel
audio_addr <= CV_ADDR_AUDIO_LEFT_OUT;
-- write sample * gain-factor to audio-interface
audio_dout <= std_ulogic_vector(resize(shift_right(signed(sample) * signed('0' & adc_value(11 downto 4)), 7), audio_dout'length));
-- write config to acodec
state_audio_nxt <= S_WRITE_CONFIG;
-- write new sample to right channel
when S_WRITE_SAMPLE_RIGHT =>
led_green(6) <= '1';
-- chip select for audio-interface
audio_cs <= '1';
-- write mode
audio_wr <= '1';
-- set address for right channel
audio_addr <= CV_ADDR_AUDIO_RIGHT_OUT;
-- write sample * gain-factor to audio-interface
audio_dout <= std_ulogic_vector(resize(shift_right(signed(sample) * signed('0' & adc_value(11 downto 4)), 7), audio_dout'length));
-- write config to acodec
state_audio_nxt <= S_WRITE_CONFIG;
when S_WRITE_CONFIG =>
led_green(7) <= '1';
-- chip select for audio-interface
audio_cs <= '1';
-- write mode
audio_wr <= '1';
-- set address for config register
audio_addr <= CV_ADDR_AUDIO_CONFIG;
-- set mic boost & in-select
audio_dout <= "00000000000000" & switch(1) & switch(0);
-- back to wait-state
state_audio_nxt <= S_WAIT_SAMPLE;
end case;
end process;
-- lcd control (combinational process contains logic only)
process(state_lcd, lcd_cmds, char_count, lcd_din, lcd_irq_rdy, lcd_refresh, adc_value)
variable bcd_value : unsigned(11 downto 0) := (others => '0');
variable adc_recalc : std_ulogic_vector(11 downto 0) := (others => '0');
begin
-- default assignment
-- leds
led_red <= (others => '0');
-- lcd interface
lcd_cs <= '0';
lcd_wr <= '0';
lcd_addr <= (others => '0');
lcd_dout <= (others => '0');
lcd_ack_rdy <= '0';
-- communication between FSMs
lcd_refresh_ack <= '0';
--registers
state_lcd_nxt <= state_lcd;
lcd_cmds_nxt <= lcd_cmds;
char_count_nxt <= char_count;
-- second state machine to generate output on lcd-screen
case state_lcd is
-- wait for lcd-interface to be 'not busy' / finished writing old commands to lcd
when S_WAIT_LCD =>
led_red(0) <= '1';
-- chip select for lcd-interface
lcd_cs <= '1';
-- read mode
lcd_wr <= '0';
-- set address for status
lcd_addr <= CV_ADDR_LCD_STATUS;
-- start printing characters
if lcd_din(0) = '0' then
state_lcd_nxt <= S_PRINT_CHARACTERS;
end if;
-- send characters to lcd-interface
when S_PRINT_CHARACTERS =>
led_red(1) <= '1';
-- lcd ready for data
if lcd_irq_rdy = '1' then
-- chip select for lcd-interface
lcd_cs <= '1';
-- write mode
lcd_wr <= '1';
-- set address for data register of lcd
lcd_addr <= CV_ADDR_LCD_DATA;
-- select character from lcd-commands-array
lcd_dout(7 downto 0) <= lcd_cmds(to_integer(char_count));
-- decide if every character has been sent
if char_count = lcd_cmds'length-1 then
state_lcd_nxt <= S_WAIT_FOR_NEW_GAIN;
-- continue sending characters to lcd-interface
else
char_count_nxt <= char_count + 1;
end if;
end if;
when S_WAIT_FOR_NEW_GAIN =>
led_red(2) <= '1';
-- write new value, only when adc value has changed
if lcd_refresh = '1' then
-- ack refresh request
lcd_refresh_ack <= '1';
-- calculate gain-value
adc_recalc := std_ulogic_vector(resize(shift_right( unsigned(adc_value(11 downto 4)) * 200,8), adc_recalc'length));
bcd_value := unsigned(to_bcd(adc_recalc, 3));
-- generate lcd-commands
lcd_cmds_nxt <= lcd_cmd(lcd_cursor_pos(0, 0) & asciitext("Volume: ") & ascii(bcd_value(11 downto 8)) & ascii(bcd_value(7 downto 4)) & ascii(bcd_value(3 downto 0)) & asciitext("%"));
-- reset char counter
char_count_nxt <= (others => '0');
-- start writing to lcd
state_lcd_nxt <= S_WAIT_LCD;
end if;
end case;
end process;
-- default assignments for unused signals
gp_ctrl <= (others => '0');
gp_out <= (others => '0');
sevenseg_cs <= '0';
sevenseg_wr <= '0';
sevenseg_addr <= (others => '0');
sevenseg_dout <= (others => '0');
ir_cs <= '0';
ir_wr <= '0';
ir_addr <= (others => '0');
ir_dout <= (others => '0');
ir_ack_rx <= '0';
sram_cs <= '0';
sram_wr <= '0';
sram_addr <= (others => '0');
sram_dout <= (others => '0');
uart_cs <= '0';
uart_wr <= '0';
uart_addr <= (others => '0');
uart_dout <= (others => '0');
uart_ack_rx <= '0';
uart_ack_tx <= '0';
end rtl;
|
apache-2.0
|
hoglet67/AtomFpga
|
src/common/AVR8/spi_mod/spi_slv_sel_comp_pack.vhd
|
4
|
1099
|
--**********************************************************************************************
--
-- Version 0.2
-- Modified 10.01.2007
-- Designed by Ruslan Lepetenok
--**********************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
package spi_slv_sel_comp_pack is
component spi_slv_sel is generic(num_of_slvs : integer := 7);
port(
-- AVR Control
ireset : in std_logic;
cp2 : in std_logic;
adr : in std_logic_vector(15 downto 0);
dbus_in : in std_logic_vector(7 downto 0);
dbus_out : out std_logic_vector(7 downto 0);
iore : in std_logic;
iowe : in std_logic;
out_en : out std_logic;
-- Output
slv_sel_n : out std_logic_vector(num_of_slvs-1 downto 0)
);
end component;
end spi_slv_sel_comp_pack;
|
apache-2.0
|
hoglet67/AtomFpga
|
src/altera/i2s_intf.vhd
|
2
|
7214
|
-- ZX Spectrum for Altera DE1
--
-- Copyright (c) 2009-2011 Mike Stirling
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- * Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- * Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written agreement from the author.
--
-- * License is granted for non-commercial use only. A fee may not be charged
-- for redistributions as source code or in synthesized/hardware form without
-- specific prior written agreement from the author.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity i2s_intf is
generic(
-- CLK is now the 32Mhz clock
inclk_rate : positive := 32000000;
-- The DAC is fed with a 16MHz clock, and configured to FS=MCLK/125, giving FS=125KHz
sample_rate : positive := 125000;
preamble : positive := 1; -- I2S
word_length : positive := 16
);
port (
-- 2x MCLK in (e.g. 24 MHz for WM8731 USB mode)
CLK : in std_logic;
nRESET : in std_logic;
-- Parallel IO
PCM_INL : out std_logic_vector(word_length - 1 downto 0);
PCM_INR : out std_logic_vector(word_length - 1 downto 0);
PCM_OUTL : in std_logic_vector(word_length - 1 downto 0);
PCM_OUTR : in std_logic_vector(word_length - 1 downto 0);
-- Codec interface (right justified mode)
-- MCLK is generated at half of the CLK input
I2S_MCLK : out std_logic;
-- LRCLK is equal to the sample rate and is synchronous to
-- MCLK. It must be related to MCLK by the oversampling ratio
-- given in the codec datasheet.
I2S_LRCLK : out std_logic;
-- Data is shifted out on the falling edge of BCLK, sampled
-- on the rising edge. The bit rate is determined such that
-- it is fast enough to fit preamble + word_length bits into
-- each LRCLK half cycle. The last cycle of each word may be
-- stretched to fit to LRCLK. This is OK at least for the
-- WM8731 codec.
-- The first falling edge of each timeslot is always synchronised
-- with the LRCLK edge.
I2S_BCLK : out std_logic;
-- Output bitstream
I2S_DOUT : out std_logic;
-- Input bitstream
I2S_DIN : in std_logic
);
end i2s_intf;
architecture i2s_intf_arch of i2s_intf is
-- this works out at 256
constant ratio_inclk_fs : positive := (inclk_rate / sample_rate);
-- this work out at 127
constant lrdivider_top : positive := (ratio_inclk_fs / 2) - 1;
-- this works out as 1; erring on the small side is fine
constant bdivider_top : positive := (ratio_inclk_fs / 8 / (preamble + word_length) * 2) - 1;
-- this works out as 17
constant nbits : positive := preamble + word_length;
subtype lrdivider_t is integer range 0 to lrdivider_top;
subtype bdivider_t is integer range 0 to bdivider_top;
subtype bitcount_t is integer range 0 to nbits;
signal lrdivider : lrdivider_t := lrdivider_top;
signal bdivider : bdivider_t := bdivider_top;
signal bitcount : bitcount_t := nbits;
signal mclk_r : std_logic := '0';
signal lrclk_r : std_logic := '0';
signal bclk_r : std_logic := '0';
-- Shift register is long enough for the number of data bits
-- plus the preamble, plus an extra bit on the right to register
-- the incoming data
signal shiftreg : std_logic_vector(nbits downto 0);
begin
I2S_MCLK <= mclk_r;
I2S_LRCLK <= lrclk_r;
I2S_BCLK <= bclk_r;
I2S_DOUT <= shiftreg(nbits); -- data goes out MSb first
process(nRESET,CLK)
begin
if nRESET = '0' then
PCM_INL <= (others => '0');
PCM_INR <= (others => '0');
-- Preload down-counters for clock generation
lrdivider <= lrdivider_top;
bdivider <= bdivider_top;
bitcount <= nbits;
mclk_r <= '0';
lrclk_r <= '0';
bclk_r <= '0';
shiftreg <= (others => '0');
elsif rising_edge(CLK) then
-- Generate MCLK at half input clock rate
mclk_r <= not mclk_r;
-- Generate LRCLK at rate specified by codec configuration
if lrdivider = 0 then
-- LRCLK divider has reached 0 - start again from the top
lrdivider <= lrdivider_top;
-- Generate LRCLK edge and sync the BCLK counter
lrclk_r <= not lrclk_r;
bclk_r <= '0';
bitcount <= nbits; -- 1 extra required for setup
bdivider <= bdivider_top;
-- Load shift register with output data padding preamble
-- with 0s. Load output buses with input word from the
-- previous timeslot.
shiftreg(nbits downto nbits - preamble + 1) <= (others => '0');
if lrclk_r = '0' then
-- Previous channel input is LEFT. This is available in the
-- shift register at the end of a cycle, right justified
PCM_INL <= shiftreg(word_length - 1 downto 0);
-- Next channel to output is RIGHT. Load this into the
-- shift register at the start of a cycle, left justified
shiftreg(word_length downto 1) <= PCM_OUTR;
else
-- Previous channel input is RIGHT
PCM_INR <= shiftreg(word_length - 1 downto 0);
-- Next channel is LEFT
shiftreg(word_length downto 1) <= PCM_OUTL;
end if;
else
-- Decrement the LRCLK counter
lrdivider <= lrdivider - 1;
-- Generate BCLK at a suitable rate to fit the required number
-- of bits into each timeslot. Data is changed on the falling edge,
-- sampled on the rising edge
if bdivider = 0 then
-- If all bits have been output for this phase then
-- stop and wait to sync back up with LRCLK
if bitcount > 0 then
-- Reset
bdivider <= bdivider_top;
-- Toggle BCLK
bclk_r <= not bclk_r;
if bclk_r = '0' then
-- Rising edge - shift in current bit and decrement bit counter
bitcount <= bitcount - 1;
shiftreg(0) <= I2S_DIN;
else
-- Falling edge - shift out next bit
shiftreg(nbits downto 1) <= shiftreg(nbits - 1 downto 0);
end if;
end if;
else
-- Decrement the BCLK counter
bdivider <= bdivider - 1;
end if;
end if;
end if;
end process;
end i2s_intf_arch;
|
apache-2.0
|
daringer/schemmaker
|
testdata/new/circuit_bi1_0op988_4.vhdl
|
1
|
5741
|
package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias2: electrical;
terminal vbias1: electrical;
terminal vbias3: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
begin
subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in1,
S => net6
);
subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in2,
S => net6
);
subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net6,
G => vbias4,
S => gnd
);
subnet0_subnet0_m4 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net7,
G => in1,
S => net6
);
subnet0_subnet0_m5 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net7,
G => in2,
S => net6
);
subnet0_subnet0_m6 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net7,
G => net7,
S => vdd
);
subnet0_subnet0_m7 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net7,
G => net7,
S => vdd
);
subnet0_subnet0_m8 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net1,
G => net7,
S => vdd
);
subnet0_subnet0_m9 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net2,
G => net7,
S => vdd
);
subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => Lsrc,
W => Wsrc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net3,
G => net1,
S => vdd
);
subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => Lsrc,
W => Wsrc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net4,
G => net2,
S => vdd
);
subnet0_subnet3_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => net5,
G => vbias2,
S => net3
);
subnet0_subnet4_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => out1,
G => vbias2,
S => net4
);
subnet0_subnet5_m1 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net5,
G => net5,
S => gnd
);
subnet0_subnet5_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcmcout_1,
scope => private
)
port map(
D => out1,
G => net5,
S => gnd
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net8
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net8,
G => vbias4,
S => gnd
);
end simple;
|
apache-2.0
|
daringer/schemmaker
|
testdata/new/circuit_bi1_0op954_4.vhdl
|
1
|
4611
|
package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vbias3: electrical;
terminal vdd: electrical;
terminal vbias2: electrical;
terminal vbias1: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
begin
subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in1,
S => net4
);
subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in2,
S => net4
);
subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net4,
G => vbias4,
S => gnd
);
subnet0_subnet1_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net3,
G => vbias3,
S => net1
);
subnet0_subnet2_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => out1,
G => vbias3,
S => net2
);
subnet0_subnet3_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => net3,
G => vbias2,
S => net5
);
subnet0_subnet3_m2 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net5,
G => net3,
S => vdd
);
subnet0_subnet3_m3 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcmout_1,
scope => private
)
port map(
D => net6,
G => net3,
S => vdd
);
subnet0_subnet3_m4 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => out1,
G => vbias2,
S => net6
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net7
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net7,
G => vbias4,
S => gnd
);
end simple;
|
apache-2.0
|
daringer/schemmaker
|
testdata/new/circuit_bi1_0op974_1.vhdl
|
1
|
4110
|
package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias1: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
begin
subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net3,
G => in1,
S => net2
);
subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in2,
S => net2
);
subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net2,
G => vbias4,
S => gnd
);
subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net1,
G => net1,
S => vdd
);
subnet0_subnet1_m2 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcmout_1,
scope => private
)
port map(
D => net3,
G => net1,
S => vdd
);
subnet0_subnet3_m1 : entity pmos(behave)
generic map(
L => Lsrc,
W => Wsrc_2,
scope => Wprivate
)
port map(
D => out1,
G => net3,
S => vdd
);
subnet0_subnet4_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcursrc_3,
scope => Wprivate
)
port map(
D => out1,
G => vbias4,
S => gnd
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net4
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net4,
G => vbias4,
S => gnd
);
end simple;
|
apache-2.0
|
daringer/schemmaker
|
testdata/new/circuit_bi1_0op948_4.vhdl
|
1
|
4611
|
package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias1: electrical;
terminal vdd: electrical;
terminal vbias2: electrical;
terminal gnd: electrical;
terminal vbias3: electrical;
terminal vbias4: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
begin
subnet0_subnet0_m1 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in1,
S => net4
);
subnet0_subnet0_m2 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in2,
S => net4
);
subnet0_subnet0_m3 : entity pmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net4,
G => vbias1,
S => vdd
);
subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net3,
G => vbias2,
S => net1
);
subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => out1,
G => vbias2,
S => net2
);
subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => net3,
G => vbias3,
S => net5
);
subnet0_subnet3_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net5,
G => net3,
S => gnd
);
subnet0_subnet3_m3 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcmout_1,
scope => private
)
port map(
D => net6,
G => net3,
S => gnd
);
subnet0_subnet3_m4 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => out1,
G => vbias3,
S => net6
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net7
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net7,
G => vbias4,
S => gnd
);
end simple;
|
apache-2.0
|
daringer/schemmaker
|
testdata/circuit_op324_0.vhdl
|
1
|
2225
|
package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity opamp is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias1: electrical;
terminal vdd: electrical;
terminal gnd: electrical);
end opamp;
architecture simple of opamp is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
terminal net1: electrical;
terminal net4: electrical;
begin
subnet0_m1 : entity pmos(behave)
generic map(
L => Ldiff,
W => Wdiff,
scope => private
)
port map(
D => net1,
G => in1,
S => net4
);
subnet0_m2 : entity pmos(behave)
generic map(
L => Ldiff,
W => Wdiff,
scope => private
)
port map(
D => out1,
G => in2,
S => net4
);
subnet0_m3 : entity pmos(behave)
generic map(
L => LBias
)
port map(
D => net4,
G => vbias1,
S => vdd
);
subnet1_m1 : entity nmos(behave)
generic map(
L => Lcm,
W => Wcm,
scope => private
)
port map(
D => net1,
G => net1,
S => gnd
);
subnet1_m2 : entity nmos(behave)
generic map(
L => Lcm,
W => Wcmcout,
scope => private
)
port map(
D => out1,
G => net1,
S => gnd
);
subnet1_c1 : entity cap(behave)
generic map(
C => Ccurmir,
scope => private
)
port map(
P => out1,
N => net1
);
end simple;
|
apache-2.0
|
sergeykhbr/riscv_vhdl
|
vhdl/rtl/techmap/pll/SysPLL_inferred.vhd
|
1
|
1052
|
-----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - [email protected]
--! @details PLL instance for the behaviour simulation
--!
--! "Output Output Phase Duty Pk-to-Pk Phase"
--! "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
--!
--! CLK_OUT1____70.000
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
--library unisim;
--use unisim.vcomponents.all;
entity SysPLL_inferred is
port
(-- Clock in ports
CLK_IN : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic;
-- Status and control signals
RESET : in std_logic;
LOCKED : out std_logic
);
end SysPLL_inferred;
architecture rtl of SysPLL_inferred is
begin
CLK_OUT1 <= CLK_IN;
LOCKED <= not RESET;
end rtl;
|
apache-2.0
|
BBN-Q/VHDL-FIR-filters
|
src/CoeffHelpers.vhd
|
1
|
992
|
library ieee;
use ieee.math_real.all;
library ieee_proposed;
use ieee_proposed.standard_additions.all;
package CoeffHelpers is
function optimum_scaling(coeffs : real_vector) return integer;
function scale_coeffs(coeffs : real_vector; scale : real) return integer_vector;
end package;
package body CoeffHelpers is
-- Determine the optimum power of two scaling for filter coefficients
-- to make the fixed point representation with minimum leading zeros
function optimum_scaling(coeffs : real_vector) return integer is
begin
return integer(trunc(log2(maximum(coeffs))));
end optimum_scaling;
-- Scale a real ceofficient vector and convert to integers
function scale_coeffs(coeffs : real_vector; scale : real) return integer_vector is
variable result_vec : integer_vector(0 to coeffs'length-1);
begin
for ct in coeffs'range loop
result_vec(ct) := integer(scale*coeffs(ct));
end loop;
return result_vec;
end scale_coeffs;
end CoeffHelpers;
|
apache-2.0
|
ntb-ch/cb20
|
FPGA_Designs/watchdog/cb20/synthesis/submodules/avalon_ppwa_interface.m.vhd
|
2
|
9054
|
-------------------------------------------------------------------------------
-- _________ _____ _____ ____ _____ ___ ____ --
-- |_ ___ | |_ _| |_ _| |_ \|_ _| |_ ||_ _| --
-- | |_ \_| | | | | | \ | | | |_/ / --
-- | _| | | _ | | | |\ \| | | __'. --
-- _| |_ _| |__/ | _| |_ _| |_\ |_ _| | \ \_ --
-- |_____| |________| |_____| |_____|\____| |____||____| --
-- --
-------------------------------------------------------------------------------
-- --
-- Avalon MM interface for PPWA --
-- --
-------------------------------------------------------------------------------
-- Copyright 2014 NTB University of Applied Sciences in Technology --
-- --
-- Licensed under the Apache License, Version 2.0 (the "License"); --
-- you may not use this file except in compliance with the License. --
-- You may obtain a copy of the License at --
-- --
-- http://www.apache.org/licenses/LICENSE-2.0 --
-- --
-- Unless required by applicable law or agreed to in writing, software --
-- distributed under the License is distributed on an "AS IS" BASIS, --
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. --
-- See the License for the specific language governing permissions and --
-- limitations under the License. --
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE IEEE.math_real.ALL;
USE work.fLink_definitions.ALL;
PACKAGE avalon_ppwa_interface_pkg IS
CONSTANT c_max_number_of_ppwas : INTEGER := 11;
CONSTANT c_ppwa_interface_address_width : INTEGER := 5;
COMPONENT avalon_ppwa_interface IS
GENERIC (
number_of_ppwas: INTEGER RANGE 1 TO c_max_number_of_ppwas:= 1;
base_clk: INTEGER := 125000000;
unique_id: STD_LOGIC_VECTOR (c_fLink_avs_data_width-1 DOWNTO 0) := (OTHERS => '0')
);
PORT (
isl_clk : IN STD_LOGIC;
isl_reset_n : IN STD_LOGIC;
islv_avs_address : IN STD_LOGIC_VECTOR(c_ppwa_interface_address_width-1 DOWNTO 0);
isl_avs_read : IN STD_LOGIC;
isl_avs_write : IN STD_LOGIC;
osl_avs_waitrequest : OUT STD_LOGIC;
islv_avs_write_data : IN STD_LOGIC_VECTOR(c_fLink_avs_data_width-1 DOWNTO 0);
islv_avs_byteenable : IN STD_LOGIC_VECTOR(c_fLink_avs_data_width_in_byte-1 DOWNTO 0);
oslv_avs_read_data : OUT STD_LOGIC_VECTOR(c_fLink_avs_data_width-1 DOWNTO 0);
islv_signals_to_measure : IN STD_LOGIC_VECTOR(number_of_ppwas-1 DOWNTO 0)
);
END COMPONENT;
CONSTANT c_ppwa_subtype_id : INTEGER := 0;
CONSTANT c_ppwa_interface_version : INTEGER := 0;
END PACKAGE avalon_ppwa_interface_pkg;
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE IEEE.math_real.ALL;
USE work.avalon_ppwa_interface_pkg.ALL;
USE work.fLink_definitions.ALL;
USE work.ppwa_pkg.ALL;
ENTITY avalon_ppwa_interface IS
GENERIC (
number_of_ppwas: INTEGER RANGE 1 TO c_max_number_of_ppwas:= 1;
base_clk: INTEGER := 125000000;
unique_id: STD_LOGIC_VECTOR (c_fLink_avs_data_width-1 DOWNTO 0) := (OTHERS => '0')
);
PORT (
isl_clk : IN STD_LOGIC;
isl_reset_n : IN STD_LOGIC;
islv_avs_address : IN STD_LOGIC_VECTOR(c_ppwa_interface_address_width-1 DOWNTO 0);
isl_avs_read : IN STD_LOGIC;
isl_avs_write : IN STD_LOGIC;
osl_avs_waitrequest : OUT STD_LOGIC;
islv_avs_write_data : IN STD_LOGIC_VECTOR(c_fLink_avs_data_width-1 DOWNTO 0);
islv_avs_byteenable : IN STD_LOGIC_VECTOR(c_fLink_avs_data_width_in_byte-1 DOWNTO 0);
oslv_avs_read_data : OUT STD_LOGIC_VECTOR(c_fLink_avs_data_width-1 DOWNTO 0);
islv_signals_to_measure : IN STD_LOGIC_VECTOR(number_of_ppwas-1 DOWNTO 0)
);
CONSTANT c_usig_base_clk_address: UNSIGNED(c_ppwa_interface_address_width-1 DOWNTO 0) := to_unsigned(c_fLink_number_of_std_registers,c_ppwa_interface_address_width);
CONSTANT c_usig_period_time_address: UNSIGNED(c_ppwa_interface_address_width-1 DOWNTO 0) := c_usig_base_clk_address + 1;
CONSTANT c_usig_high_time_address: UNSIGNED(c_ppwa_interface_address_width-1 DOWNTO 0) := c_usig_period_time_address + number_of_ppwas;
CONSTANT c_usig_ppwa_max_address: UNSIGNED(c_ppwa_interface_address_width-1 DOWNTO 0) := c_usig_high_time_address + number_of_ppwas;
END ENTITY avalon_ppwa_interface;
ARCHITECTURE rtl OF avalon_ppwa_interface IS
Type t_counter_regs IS ARRAY(number_of_ppwas-1 DOWNTO 0) OF UNSIGNED(c_fLink_avs_data_width-1 DOWNTO 0);
TYPE t_internal_register IS RECORD
config_reg : STD_LOGIC_VECTOR(c_fLink_avs_data_width-1 DOWNTO 0);
END RECORD;
SIGNAL ri,ri_next : t_internal_register;
SIGNAL ppwa_reset_n : STD_LOGIC;
SIGNAL usig_period_count_regs : t_counter_regs;
SIGNAL usig_hightime_count_regs : t_counter_regs;
BEGIN
gen_ppwa:
FOR i IN 0 TO number_of_ppwas-1 GENERATE
my_ppwa : ppwa
GENERIC MAP (counter_resolution => c_fLink_avs_data_width)
PORT MAP (isl_clk,ppwa_reset_n,islv_signals_to_measure(i),usig_period_count_regs(i),usig_hightime_count_regs(i));
END GENERATE gen_ppwa;
-- combinatorial process
comb_proc : PROCESS (isl_reset_n,ri,isl_avs_write,islv_avs_address,isl_avs_read,islv_avs_write_data,islv_avs_byteenable)
VARIABLE vi : t_internal_register;
VARIABLE ppwa_part_nr: INTEGER := 0;
BEGIN
-- keep variables stable
vi := ri;
--standard values
oslv_avs_read_data <= (OTHERS => '0');
ppwa_reset_n <= '1';
--avalon slave interface write part
IF isl_avs_write = '1' THEN
IF UNSIGNED(islv_avs_address) = to_unsigned(c_fLink_configuration_address,c_ppwa_interface_address_width) THEN
FOR i IN 0 TO c_fLink_avs_data_width_in_byte-1 LOOP
IF islv_avs_byteenable(i) = '1' THEN
vi.config_reg((i + 1) * 8 - 1 DOWNTO i * 8) := islv_avs_write_data((i + 1) * 8 - 1 DOWNTO i * 8);
END IF;
END LOOP;
END IF;
END IF;
--avalon slave interface read part
IF isl_avs_read = '1' THEN
CASE UNSIGNED(islv_avs_address) IS
WHEN to_unsigned(c_fLink_typdef_address,c_ppwa_interface_address_width) =>
oslv_avs_read_data ((c_fLink_interface_version_length + c_fLink_subtype_length + c_fLink_id_length - 1) DOWNTO
(c_fLink_interface_version_length + c_fLink_subtype_length)) <= STD_LOGIC_VECTOR(to_unsigned(c_fLink_ppwa_id,c_fLink_id_length));
oslv_avs_read_data((c_fLink_interface_version_length + c_fLink_subtype_length - 1) DOWNTO c_fLink_interface_version_length) <= STD_LOGIC_VECTOR(to_unsigned(c_ppwa_subtype_id,c_fLink_subtype_length));
oslv_avs_read_data(c_fLink_interface_version_length-1 DOWNTO 0) <= STD_LOGIC_VECTOR(to_unsigned(c_ppwa_interface_version,c_fLink_interface_version_length));
WHEN to_unsigned(c_fLink_mem_size_address,c_ppwa_interface_address_width) =>
oslv_avs_read_data(c_ppwa_interface_address_width+2) <= '1';
WHEN to_unsigned(c_fLink_number_of_channels_address,c_ppwa_interface_address_width) =>
oslv_avs_read_data <= std_logic_vector(to_unsigned(number_of_ppwas,c_fLink_avs_data_width));
WHEN c_usig_base_clk_address =>
oslv_avs_read_data <= std_logic_vector(to_unsigned(base_clk,c_fLink_avs_data_width));
WHEN to_unsigned(c_fLink_unique_id_address,c_ppwa_interface_address_width) =>
oslv_avs_read_data <= unique_id;
WHEN OTHERS =>
IF UNSIGNED(islv_avs_address)>= c_usig_period_time_address AND UNSIGNED(islv_avs_address)< c_usig_high_time_address THEN
ppwa_part_nr := to_integer(UNSIGNED(islv_avs_address) - c_usig_period_time_address);
oslv_avs_read_data <= std_logic_vector(usig_period_count_regs(ppwa_part_nr));
ELSIF UNSIGNED(islv_avs_address)>= c_usig_high_time_address AND UNSIGNED(islv_avs_address)< c_usig_ppwa_max_address THEN
ppwa_part_nr := to_integer(UNSIGNED(islv_avs_address)-c_usig_high_time_address);
oslv_avs_read_data <= std_logic_vector(usig_hightime_count_regs(ppwa_part_nr));
END IF;
END CASE;
END IF;
IF isl_reset_n = '0' OR vi.config_reg(c_fLink_reset_bit_num) = '1' THEN
vi.config_reg := (OTHERS =>'0');
ppwa_reset_n <= '0';
END IF;
ri_next <= vi;
END PROCESS comb_proc;
reg_proc : PROCESS (isl_clk)
BEGIN
IF rising_edge(isl_clk) THEN
ri <= ri_next;
END IF;
END PROCESS reg_proc;
osl_avs_waitrequest <= '0';
END rtl;
|
apache-2.0
|
rdsalemi/uvmprimer
|
12_UVM_Components/tinyalu_dut/three_cycle_mult.vhd
|
24
|
2435
|
-- Copyright 2013 Ray Salemi
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
-- VHDL Architecture tinyalu_lib.three_cycle.mult
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY three_cycle IS
PORT(
A : IN unsigned ( 7 DOWNTO 0 );
B : IN unsigned ( 7 DOWNTO 0 );
clk : IN std_logic;
reset_n : IN std_logic;
start : IN std_logic;
done_mult : OUT std_logic;
result_mult : OUT unsigned (15 DOWNTO 0)
);
-- Declarations
END three_cycle ;
--
architecture mult of three_cycle is
signal a_int,b_int : unsigned (7 downto 0); -- start pipeline
signal mult1,mult2 : unsigned (15 downto 0); -- pipeline registers
signal done3,done2,done1,done_mult_int : std_logic; -- pipeline the done signal
begin
-- purpose: Three stage pipelined multiplier
-- type : sequential
-- inputs : clk, reset_n, a,b
-- outputs: result_mult
multiplier: process (clk, reset_n)
begin -- process multiplier
if reset_n = '0' then -- asynchronous reset (active low)
done_mult_int <= '0';
done3 <= '0';
done2 <= '0';
done1 <= '0';
a_int <= "00000000";
b_int <= "00000000";
mult1 <= "0000000000000000";
mult2 <= "0000000000000000";
result_mult <= "0000000000000000";
elsif clk'event and clk = '1' then -- rising clock edge
a_int <= a;
b_int <= b;
mult1 <= a_int * b_int;
mult2 <= mult1;
result_mult <= mult2;
done3 <= start and (not done_mult_int);
done2 <= done3 and (not done_mult_int);
done1 <= done2 and (not done_mult_int);
done_mult_int <= done1 and (not done_mult_int);
end if;
end process multiplier;
done_mult <= done_mult_int;
end architecture mult;
|
apache-2.0
|
rdsalemi/uvmprimer
|
10_An_Object_Oriented_Testbench/tinyalu_dut/three_cycle_mult.vhd
|
24
|
2435
|
-- Copyright 2013 Ray Salemi
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
-- VHDL Architecture tinyalu_lib.three_cycle.mult
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY three_cycle IS
PORT(
A : IN unsigned ( 7 DOWNTO 0 );
B : IN unsigned ( 7 DOWNTO 0 );
clk : IN std_logic;
reset_n : IN std_logic;
start : IN std_logic;
done_mult : OUT std_logic;
result_mult : OUT unsigned (15 DOWNTO 0)
);
-- Declarations
END three_cycle ;
--
architecture mult of three_cycle is
signal a_int,b_int : unsigned (7 downto 0); -- start pipeline
signal mult1,mult2 : unsigned (15 downto 0); -- pipeline registers
signal done3,done2,done1,done_mult_int : std_logic; -- pipeline the done signal
begin
-- purpose: Three stage pipelined multiplier
-- type : sequential
-- inputs : clk, reset_n, a,b
-- outputs: result_mult
multiplier: process (clk, reset_n)
begin -- process multiplier
if reset_n = '0' then -- asynchronous reset (active low)
done_mult_int <= '0';
done3 <= '0';
done2 <= '0';
done1 <= '0';
a_int <= "00000000";
b_int <= "00000000";
mult1 <= "0000000000000000";
mult2 <= "0000000000000000";
result_mult <= "0000000000000000";
elsif clk'event and clk = '1' then -- rising clock edge
a_int <= a;
b_int <= b;
mult1 <= a_int * b_int;
mult2 <= mult1;
result_mult <= mult2;
done3 <= start and (not done_mult_int);
done2 <= done3 and (not done_mult_int);
done1 <= done2 and (not done_mult_int);
done_mult_int <= done1 and (not done_mult_int);
end if;
end process multiplier;
done_mult <= done_mult_int;
end architecture mult;
|
apache-2.0
|
ntb-ch/cb20
|
FPGA_Designs/mpu9250/cb20/synthesis/cb20_width_adapter_001.vhd
|
1
|
10454
|
-- cb20_width_adapter_001.vhd
-- Generated using ACDS version 13.0sp1 232 at 2016.10.12.10:12:44
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity cb20_width_adapter_001 is
generic (
IN_PKT_ADDR_H : integer := 52;
IN_PKT_ADDR_L : integer := 36;
IN_PKT_DATA_H : integer := 31;
IN_PKT_DATA_L : integer := 0;
IN_PKT_BYTEEN_H : integer := 35;
IN_PKT_BYTEEN_L : integer := 32;
IN_PKT_BYTE_CNT_H : integer := 61;
IN_PKT_BYTE_CNT_L : integer := 59;
IN_PKT_TRANS_COMPRESSED_READ : integer := 53;
IN_PKT_BURSTWRAP_H : integer := 62;
IN_PKT_BURSTWRAP_L : integer := 62;
IN_PKT_BURST_SIZE_H : integer := 65;
IN_PKT_BURST_SIZE_L : integer := 63;
IN_PKT_RESPONSE_STATUS_H : integer := 87;
IN_PKT_RESPONSE_STATUS_L : integer := 86;
IN_PKT_TRANS_EXCLUSIVE : integer := 58;
IN_PKT_BURST_TYPE_H : integer := 67;
IN_PKT_BURST_TYPE_L : integer := 66;
IN_ST_DATA_W : integer := 88;
OUT_PKT_ADDR_H : integer := 34;
OUT_PKT_ADDR_L : integer := 18;
OUT_PKT_DATA_H : integer := 15;
OUT_PKT_DATA_L : integer := 0;
OUT_PKT_BYTEEN_H : integer := 17;
OUT_PKT_BYTEEN_L : integer := 16;
OUT_PKT_BYTE_CNT_H : integer := 43;
OUT_PKT_BYTE_CNT_L : integer := 41;
OUT_PKT_TRANS_COMPRESSED_READ : integer := 35;
OUT_PKT_BURST_SIZE_H : integer := 47;
OUT_PKT_BURST_SIZE_L : integer := 45;
OUT_PKT_RESPONSE_STATUS_H : integer := 69;
OUT_PKT_RESPONSE_STATUS_L : integer := 68;
OUT_PKT_TRANS_EXCLUSIVE : integer := 40;
OUT_PKT_BURST_TYPE_H : integer := 49;
OUT_PKT_BURST_TYPE_L : integer := 48;
OUT_ST_DATA_W : integer := 70;
ST_CHANNEL_W : integer := 7;
OPTIMIZE_FOR_RSP : integer := 1;
RESPONSE_PATH : integer := 1
);
port (
clk : in std_logic := '0'; -- clk.clk
reset : in std_logic := '0'; -- clk_reset.reset
in_valid : in std_logic := '0'; -- sink.valid
in_channel : in std_logic_vector(6 downto 0) := (others => '0'); -- .channel
in_startofpacket : in std_logic := '0'; -- .startofpacket
in_endofpacket : in std_logic := '0'; -- .endofpacket
in_ready : out std_logic; -- .ready
in_data : in std_logic_vector(87 downto 0) := (others => '0'); -- .data
out_endofpacket : out std_logic; -- src.endofpacket
out_data : out std_logic_vector(69 downto 0); -- .data
out_channel : out std_logic_vector(6 downto 0); -- .channel
out_valid : out std_logic; -- .valid
out_ready : in std_logic := '0'; -- .ready
out_startofpacket : out std_logic; -- .startofpacket
in_command_size_data : in std_logic_vector(2 downto 0) := (others => '0')
);
end entity cb20_width_adapter_001;
architecture rtl of cb20_width_adapter_001 is
component altera_merlin_width_adapter is
generic (
IN_PKT_ADDR_H : integer := 60;
IN_PKT_ADDR_L : integer := 36;
IN_PKT_DATA_H : integer := 31;
IN_PKT_DATA_L : integer := 0;
IN_PKT_BYTEEN_H : integer := 35;
IN_PKT_BYTEEN_L : integer := 32;
IN_PKT_BYTE_CNT_H : integer := 63;
IN_PKT_BYTE_CNT_L : integer := 61;
IN_PKT_TRANS_COMPRESSED_READ : integer := 65;
IN_PKT_BURSTWRAP_H : integer := 67;
IN_PKT_BURSTWRAP_L : integer := 66;
IN_PKT_BURST_SIZE_H : integer := 70;
IN_PKT_BURST_SIZE_L : integer := 68;
IN_PKT_RESPONSE_STATUS_H : integer := 72;
IN_PKT_RESPONSE_STATUS_L : integer := 71;
IN_PKT_TRANS_EXCLUSIVE : integer := 73;
IN_PKT_BURST_TYPE_H : integer := 75;
IN_PKT_BURST_TYPE_L : integer := 74;
IN_ST_DATA_W : integer := 76;
OUT_PKT_ADDR_H : integer := 60;
OUT_PKT_ADDR_L : integer := 36;
OUT_PKT_DATA_H : integer := 31;
OUT_PKT_DATA_L : integer := 0;
OUT_PKT_BYTEEN_H : integer := 35;
OUT_PKT_BYTEEN_L : integer := 32;
OUT_PKT_BYTE_CNT_H : integer := 63;
OUT_PKT_BYTE_CNT_L : integer := 61;
OUT_PKT_TRANS_COMPRESSED_READ : integer := 65;
OUT_PKT_BURST_SIZE_H : integer := 68;
OUT_PKT_BURST_SIZE_L : integer := 66;
OUT_PKT_RESPONSE_STATUS_H : integer := 70;
OUT_PKT_RESPONSE_STATUS_L : integer := 69;
OUT_PKT_TRANS_EXCLUSIVE : integer := 71;
OUT_PKT_BURST_TYPE_H : integer := 73;
OUT_PKT_BURST_TYPE_L : integer := 72;
OUT_ST_DATA_W : integer := 74;
ST_CHANNEL_W : integer := 32;
OPTIMIZE_FOR_RSP : integer := 0;
RESPONSE_PATH : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
in_valid : in std_logic := 'X'; -- valid
in_channel : in std_logic_vector(6 downto 0) := (others => 'X'); -- channel
in_startofpacket : in std_logic := 'X'; -- startofpacket
in_endofpacket : in std_logic := 'X'; -- endofpacket
in_ready : out std_logic; -- ready
in_data : in std_logic_vector(87 downto 0) := (others => 'X'); -- data
out_endofpacket : out std_logic; -- endofpacket
out_data : out std_logic_vector(69 downto 0); -- data
out_channel : out std_logic_vector(6 downto 0); -- channel
out_valid : out std_logic; -- valid
out_ready : in std_logic := 'X'; -- ready
out_startofpacket : out std_logic; -- startofpacket
in_command_size_data : in std_logic_vector(2 downto 0) := (others => 'X') -- data
);
end component altera_merlin_width_adapter;
begin
width_adapter_001 : component altera_merlin_width_adapter
generic map (
IN_PKT_ADDR_H => IN_PKT_ADDR_H,
IN_PKT_ADDR_L => IN_PKT_ADDR_L,
IN_PKT_DATA_H => IN_PKT_DATA_H,
IN_PKT_DATA_L => IN_PKT_DATA_L,
IN_PKT_BYTEEN_H => IN_PKT_BYTEEN_H,
IN_PKT_BYTEEN_L => IN_PKT_BYTEEN_L,
IN_PKT_BYTE_CNT_H => IN_PKT_BYTE_CNT_H,
IN_PKT_BYTE_CNT_L => IN_PKT_BYTE_CNT_L,
IN_PKT_TRANS_COMPRESSED_READ => IN_PKT_TRANS_COMPRESSED_READ,
IN_PKT_BURSTWRAP_H => IN_PKT_BURSTWRAP_H,
IN_PKT_BURSTWRAP_L => IN_PKT_BURSTWRAP_L,
IN_PKT_BURST_SIZE_H => IN_PKT_BURST_SIZE_H,
IN_PKT_BURST_SIZE_L => IN_PKT_BURST_SIZE_L,
IN_PKT_RESPONSE_STATUS_H => IN_PKT_RESPONSE_STATUS_H,
IN_PKT_RESPONSE_STATUS_L => IN_PKT_RESPONSE_STATUS_L,
IN_PKT_TRANS_EXCLUSIVE => IN_PKT_TRANS_EXCLUSIVE,
IN_PKT_BURST_TYPE_H => IN_PKT_BURST_TYPE_H,
IN_PKT_BURST_TYPE_L => IN_PKT_BURST_TYPE_L,
IN_ST_DATA_W => IN_ST_DATA_W,
OUT_PKT_ADDR_H => OUT_PKT_ADDR_H,
OUT_PKT_ADDR_L => OUT_PKT_ADDR_L,
OUT_PKT_DATA_H => OUT_PKT_DATA_H,
OUT_PKT_DATA_L => OUT_PKT_DATA_L,
OUT_PKT_BYTEEN_H => OUT_PKT_BYTEEN_H,
OUT_PKT_BYTEEN_L => OUT_PKT_BYTEEN_L,
OUT_PKT_BYTE_CNT_H => OUT_PKT_BYTE_CNT_H,
OUT_PKT_BYTE_CNT_L => OUT_PKT_BYTE_CNT_L,
OUT_PKT_TRANS_COMPRESSED_READ => OUT_PKT_TRANS_COMPRESSED_READ,
OUT_PKT_BURST_SIZE_H => OUT_PKT_BURST_SIZE_H,
OUT_PKT_BURST_SIZE_L => OUT_PKT_BURST_SIZE_L,
OUT_PKT_RESPONSE_STATUS_H => OUT_PKT_RESPONSE_STATUS_H,
OUT_PKT_RESPONSE_STATUS_L => OUT_PKT_RESPONSE_STATUS_L,
OUT_PKT_TRANS_EXCLUSIVE => OUT_PKT_TRANS_EXCLUSIVE,
OUT_PKT_BURST_TYPE_H => OUT_PKT_BURST_TYPE_H,
OUT_PKT_BURST_TYPE_L => OUT_PKT_BURST_TYPE_L,
OUT_ST_DATA_W => OUT_ST_DATA_W,
ST_CHANNEL_W => ST_CHANNEL_W,
OPTIMIZE_FOR_RSP => OPTIMIZE_FOR_RSP,
RESPONSE_PATH => RESPONSE_PATH
)
port map (
clk => clk, -- clk.clk
reset => reset, -- clk_reset.reset
in_valid => in_valid, -- sink.valid
in_channel => in_channel, -- .channel
in_startofpacket => in_startofpacket, -- .startofpacket
in_endofpacket => in_endofpacket, -- .endofpacket
in_ready => in_ready, -- .ready
in_data => in_data, -- .data
out_endofpacket => out_endofpacket, -- src.endofpacket
out_data => out_data, -- .data
out_channel => out_channel, -- .channel
out_valid => out_valid, -- .valid
out_ready => out_ready, -- .ready
out_startofpacket => out_startofpacket, -- .startofpacket
in_command_size_data => "000" -- (terminated)
);
end architecture rtl; -- of cb20_width_adapter_001
|
apache-2.0
|
rdsalemi/uvmprimer
|
13_UVM_Environments/tinyalu_dut/single_cycle_add_and_xor.vhd
|
24
|
3045
|
-- Copyright 2013 Ray Salemi
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity single_cycle is
port(
A : in unsigned ( 7 downto 0 );
B : in unsigned ( 7 downto 0 );
clk : in std_logic;
op : in std_logic_vector ( 2 downto 0 );
reset_n : in std_logic;
start : in std_logic;
done_aax : out std_logic;
result_aax : out unsigned (15 downto 0)
);
-- Declarations
end single_cycle;
--
architecture add_and_xor of single_cycle is
signal a_int, b_int : unsigned (7 downto 0);
signal mul_int1, mul_int2 : unsigned(15 downto 0);
signal done_aax_int : std_logic; -- VHDL can't read an output -- Doh!
begin
-----------------------------------------------------------------
single_cycle_ops : process (clk)
-----------------------------------------------------------------
begin
if (clk'event and clk = '1') then
-- Synchronous Reset
if (reset_n = '0') then
-- Reset Actions
result_aax <= "0000000000000000";
else
if START = '1' then
case op is
when "001" =>
result_aax <= ("00000000" & A) +
("00000000" & B);
when "010" =>
result_aax <= unsigned(std_logic_vector("00000000" & A) and
std_logic_vector("00000000" & B));
when "011" =>
result_aax <= unsigned(std_logic_vector("00000000" & A) xor
std_logic_vector("00000000" & B));
when others => null;
end case;
end if;
end if;
end if;
end process single_cycle_ops;
-- purpose: This block sets the done signal. This is set on the clock edge if the start signal is high.
-- type : sequential
-- inputs : clk, reset_n, start,op
-- outputs: done_aax_int
set_done : process (clk, reset_n)
begin -- process set_done_sig
if reset_n = '0' then -- asynchronous reset (active low)
done_aax_int <= '0';
elsif clk'event and clk = '1' then -- rising clock edge
if ((start = '1') and (op /= "000")) then
done_aax_int <= '1';
else
done_aax_int <= '0';
end if;
end if;
end process set_done;
done_aax <= done_aax_int;
end architecture add_and_xor;
|
apache-2.0
|
rdsalemi/uvmprimer
|
23_UVM_Sequences/tinyalu_dut/single_cycle_add_and_xor.vhd
|
24
|
3045
|
-- Copyright 2013 Ray Salemi
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity single_cycle is
port(
A : in unsigned ( 7 downto 0 );
B : in unsigned ( 7 downto 0 );
clk : in std_logic;
op : in std_logic_vector ( 2 downto 0 );
reset_n : in std_logic;
start : in std_logic;
done_aax : out std_logic;
result_aax : out unsigned (15 downto 0)
);
-- Declarations
end single_cycle;
--
architecture add_and_xor of single_cycle is
signal a_int, b_int : unsigned (7 downto 0);
signal mul_int1, mul_int2 : unsigned(15 downto 0);
signal done_aax_int : std_logic; -- VHDL can't read an output -- Doh!
begin
-----------------------------------------------------------------
single_cycle_ops : process (clk)
-----------------------------------------------------------------
begin
if (clk'event and clk = '1') then
-- Synchronous Reset
if (reset_n = '0') then
-- Reset Actions
result_aax <= "0000000000000000";
else
if START = '1' then
case op is
when "001" =>
result_aax <= ("00000000" & A) +
("00000000" & B);
when "010" =>
result_aax <= unsigned(std_logic_vector("00000000" & A) and
std_logic_vector("00000000" & B));
when "011" =>
result_aax <= unsigned(std_logic_vector("00000000" & A) xor
std_logic_vector("00000000" & B));
when others => null;
end case;
end if;
end if;
end if;
end process single_cycle_ops;
-- purpose: This block sets the done signal. This is set on the clock edge if the start signal is high.
-- type : sequential
-- inputs : clk, reset_n, start,op
-- outputs: done_aax_int
set_done : process (clk, reset_n)
begin -- process set_done_sig
if reset_n = '0' then -- asynchronous reset (active low)
done_aax_int <= '0';
elsif clk'event and clk = '1' then -- rising clock edge
if ((start = '1') and (op /= "000")) then
done_aax_int <= '1';
else
done_aax_int <= '0';
end if;
end if;
end process set_done;
done_aax <= done_aax_int;
end architecture add_and_xor;
|
apache-2.0
|
rdsalemi/uvmprimer
|
16_Analysis_Ports_In_the_Testbench/tinyalu_dut/single_cycle_add_and_xor.vhd
|
24
|
3045
|
-- Copyright 2013 Ray Salemi
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity single_cycle is
port(
A : in unsigned ( 7 downto 0 );
B : in unsigned ( 7 downto 0 );
clk : in std_logic;
op : in std_logic_vector ( 2 downto 0 );
reset_n : in std_logic;
start : in std_logic;
done_aax : out std_logic;
result_aax : out unsigned (15 downto 0)
);
-- Declarations
end single_cycle;
--
architecture add_and_xor of single_cycle is
signal a_int, b_int : unsigned (7 downto 0);
signal mul_int1, mul_int2 : unsigned(15 downto 0);
signal done_aax_int : std_logic; -- VHDL can't read an output -- Doh!
begin
-----------------------------------------------------------------
single_cycle_ops : process (clk)
-----------------------------------------------------------------
begin
if (clk'event and clk = '1') then
-- Synchronous Reset
if (reset_n = '0') then
-- Reset Actions
result_aax <= "0000000000000000";
else
if START = '1' then
case op is
when "001" =>
result_aax <= ("00000000" & A) +
("00000000" & B);
when "010" =>
result_aax <= unsigned(std_logic_vector("00000000" & A) and
std_logic_vector("00000000" & B));
when "011" =>
result_aax <= unsigned(std_logic_vector("00000000" & A) xor
std_logic_vector("00000000" & B));
when others => null;
end case;
end if;
end if;
end if;
end process single_cycle_ops;
-- purpose: This block sets the done signal. This is set on the clock edge if the start signal is high.
-- type : sequential
-- inputs : clk, reset_n, start,op
-- outputs: done_aax_int
set_done : process (clk, reset_n)
begin -- process set_done_sig
if reset_n = '0' then -- asynchronous reset (active low)
done_aax_int <= '0';
elsif clk'event and clk = '1' then -- rising clock edge
if ((start = '1') and (op /= "000")) then
done_aax_int <= '1';
else
done_aax_int <= '0';
end if;
end if;
end process set_done;
done_aax <= done_aax_int;
end architecture add_and_xor;
|
apache-2.0
|
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